commit 054430fe49055a207f585235797cde675686465c Author: yunhai8432 Date: Fri Jan 9 09:50:07 2026 +0800 touch README.md git init git checkout -b main git add README.md git commit -m "first commit" git remote add origin ssh://git@gitea.qutrobot.top:222/yunhai/Infantry.git git push -u origin main diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..3293382 --- /dev/null +++ b/.mxproject @@ -0,0 +1,41 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\port.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h;Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\freertos.c;..\Core\Src\can.c;..\Core\Src\dma.c;..\Core\Src\i2c.c;..\Core\Src\spi.c;..\Core\Src\tim.c;..\Core\Src\usart.c;..\Core\Src\stm32f4xx_it.c;..\Core\Src\stm32f4xx_hal_msp.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Middlewares\Third_Party\FreeRTOS\Source\croutine.c;..\Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;..\Middlewares\Third_Party\FreeRTOS\Source\list.c;..\Middlewares\Third_Party\FreeRTOS\Source\queue.c;..\Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;..\Middlewares\Third_Party\FreeRTOS\Source\tasks.c;..\Middlewares\Third_Party\FreeRTOS\Source\timers.c;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\port.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;..\Middlewares\Third_Party\FreeRTOS\Source\croutine.c;..\Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;..\Middlewares\Third_Party\FreeRTOS\Source\list.c;..\Middlewares\Third_Party\FreeRTOS\Source\queue.c;..\Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;..\Middlewares\Third_Party\FreeRTOS\Source\tasks.c;..\Middlewares\Third_Party\FreeRTOS\Source\timers.c;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\port.c;..\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;..\Core\Src\system_stm32f4xx.c;;;..\Middlewares\Third_Party\FreeRTOS\Source\croutine.c;..\Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;..\Middlewares\Third_Party\FreeRTOS\Source\list.c;..\Middlewares\Third_Party\FreeRTOS\Source\queue.c;..\Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;..\Middlewares\Third_Party\FreeRTOS\Source\tasks.c;..\Middlewares\Third_Party\FreeRTOS\Source\timers.c;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\port.c; +HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Middlewares\Third_Party\FreeRTOS\Source\include;..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=11 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\FreeRTOSConfig.h +HeaderFiles#2=..\Core\Inc\can.h +HeaderFiles#3=..\Core\Inc\dma.h +HeaderFiles#4=..\Core\Inc\i2c.h +HeaderFiles#5=..\Core\Inc\spi.h +HeaderFiles#6=..\Core\Inc\tim.h +HeaderFiles#7=..\Core\Inc\usart.h +HeaderFiles#8=..\Core\Inc\stm32f4xx_it.h +HeaderFiles#9=..\Core\Inc\stm32f4xx_hal_conf.h +HeaderFiles#10=..\Core\Inc\main.h +HeaderFolderListSize=1 +HeaderPath#0=..\Core\Inc +HeaderFiles=; +SourceFileListSize=11 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\freertos.c +SourceFiles#2=..\Core\Src\can.c +SourceFiles#3=..\Core\Src\dma.c +SourceFiles#4=..\Core\Src\i2c.c +SourceFiles#5=..\Core\Src\spi.c +SourceFiles#6=..\Core\Src\tim.c +SourceFiles#7=..\Core\Src\usart.c +SourceFiles#8=..\Core\Src\stm32f4xx_it.c +SourceFiles#9=..\Core\Src\stm32f4xx_hal_msp.c +SourceFiles#10=..\Core\Src\main.c +SourceFolderListSize=1 +SourcePath#0=..\Core\Src +SourceFiles=; + diff --git a/Core/Inc/FreeRTOSConfig.h b/Core/Inc/FreeRTOSConfig.h new file mode 100644 index 0000000..b67e7ed --- /dev/null +++ b/Core/Inc/FreeRTOSConfig.h @@ -0,0 +1,171 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + #include + extern uint32_t SystemCoreClock; + void xPortSysTickHandler(void); +#endif +#ifndef CMSIS_device_header +#define CMSIS_device_header "stm32f4xx.h" +#endif /* CMSIS_device_header */ + +#define configENABLE_FPU 0 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configTOTAL_HEAP_SIZE ((size_t)0x19999) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 256 + +/* CMSIS-RTOS V2 flags */ +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#define configUSE_OS2_THREAD_ENUMERATE 1 +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#define configUSE_OS2_THREAD_FLAGS 1 +#define configUSE_OS2_TIMER 1 +#define configUSE_OS2_MUTEX 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ +#define configASSERT( x ) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 1 + +/* USER CODE BEGIN Defines */ +/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */ +/* USER CODE END Defines */ + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Core/Inc/can.h b/Core/Inc/can.h new file mode 100644 index 0000000..2889c8c --- /dev/null +++ b/Core/Inc/can.h @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file can.h + * @brief This file contains all the function prototypes for + * the can.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CAN_H__ +#define __CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern CAN_HandleTypeDef hcan1; + +extern CAN_HandleTypeDef hcan2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_CAN1_Init(void); +void MX_CAN2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_H__ */ + diff --git a/Core/Inc/dma.h b/Core/Inc/dma.h new file mode 100644 index 0000000..afad30d --- /dev/null +++ b/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/Core/Inc/gpio.h b/Core/Inc/gpio.h new file mode 100644 index 0000000..3c91c4d --- /dev/null +++ b/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/Core/Inc/i2c.h b/Core/Inc/i2c.h new file mode 100644 index 0000000..52cbb17 --- /dev/null +++ b/Core/Inc/i2c.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..4f1c55f --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,87 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define CMPS_RST_Pin GPIO_PIN_6 +#define CMPS_RST_GPIO_Port GPIOG +#define CMPS_INT_Pin GPIO_PIN_3 +#define CMPS_INT_GPIO_Port GPIOG +#define CMPS_INT_EXTI_IRQn EXTI3_IRQn +#define USER_KEY_Pin GPIO_PIN_0 +#define USER_KEY_GPIO_Port GPIOA +#define USER_KEY_EXTI_IRQn EXTI0_IRQn +#define ACCL_CS_Pin GPIO_PIN_4 +#define ACCL_CS_GPIO_Port GPIOA +#define ACCL_INT_Pin GPIO_PIN_4 +#define ACCL_INT_GPIO_Port GPIOC +#define ACCL_INT_EXTI_IRQn EXTI4_IRQn +#define GYRO_INT_Pin GPIO_PIN_5 +#define GYRO_INT_GPIO_Port GPIOC +#define GYRO_INT_EXTI_IRQn EXTI9_5_IRQn +#define GYRO_CS_Pin GPIO_PIN_0 +#define GYRO_CS_GPIO_Port GPIOB + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Core/Inc/spi.h b/Core/Inc/spi.h new file mode 100644 index 0000000..d1b1dcf --- /dev/null +++ b/Core/Inc/spi.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SPI_HandleTypeDef hspi1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SPI1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h new file mode 100644 index 0000000..6f8aa96 --- /dev/null +++ b/Core/Inc/stm32f4xx_hal_conf.h @@ -0,0 +1,495 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CONF_H +#define __STM32F4xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCCARD_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_FMPI2C_MODULE_ENABLED */ +/* #define HAL_FMPSMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE 12000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U +#define DATA_CACHE_ENABLE 1U + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ +#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY 0x000000FFU +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY 0x00000FFFU + +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f4xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f4xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f4xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f4xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f4xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f4xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f4xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f4xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f4xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f4xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f4xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f4xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f4xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f4xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f4xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f4xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCCARD_MODULE_ENABLED + #include "stm32f4xx_hal_pccard.h" +#endif /* HAL_PCCARD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f4xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f4xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f4xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f4xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f4xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f4xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f4xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f4xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f4xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f4xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f4xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f4xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f4xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f4xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f4xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f4xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f4xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f4xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f4xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f4xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f4xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f4xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f4xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMPI2C_MODULE_ENABLED + #include "stm32f4xx_hal_fmpi2c.h" +#endif /* HAL_FMPI2C_MODULE_ENABLED */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + #include "stm32f4xx_hal_fmpsmbus.h" +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f4xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f4xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f4xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f4xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CONF_H */ diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h new file mode 100644 index 0000000..7b5ae3a --- /dev/null +++ b/Core/Inc/stm32f4xx_it.h @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_IT_H +#define __STM32F4xx_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void SysTick_Handler(void); +void EXTI0_IRQHandler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); +void DMA1_Stream1_IRQHandler(void); +void CAN1_TX_IRQHandler(void); +void CAN1_RX0_IRQHandler(void); +void CAN1_RX1_IRQHandler(void); +void CAN1_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void DMA2_Stream2_IRQHandler(void); +void DMA2_Stream3_IRQHandler(void); +void CAN2_TX_IRQHandler(void); +void CAN2_RX1_IRQHandler(void); +void CAN2_SCE_IRQHandler(void); +void USART6_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_IT_H */ diff --git a/Core/Inc/tim.h b/Core/Inc/tim.h new file mode 100644 index 0000000..d6f45d5 --- /dev/null +++ b/Core/Inc/tim.h @@ -0,0 +1,54 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim10; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM10_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h new file mode 100644 index 0000000..fde6fd7 --- /dev/null +++ b/Core/Inc/usart.h @@ -0,0 +1,61 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart1; + +extern UART_HandleTypeDef huart2; + +extern UART_HandleTypeDef huart3; + +extern UART_HandleTypeDef huart6; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); +void MX_USART3_UART_Init(void); +void MX_USART6_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/Core/Src/can.c b/Core/Src/can.c new file mode 100644 index 0000000..6f21d15 --- /dev/null +++ b/Core/Src/can.c @@ -0,0 +1,233 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file can.c + * @brief This file provides code for the configuration + * of the CAN instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "can.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +CAN_HandleTypeDef hcan1; +CAN_HandleTypeDef hcan2; + +/* CAN1 init function */ +void MX_CAN1_Init(void) +{ + + /* USER CODE BEGIN CAN1_Init 0 */ + + /* USER CODE END CAN1_Init 0 */ + + /* USER CODE BEGIN CAN1_Init 1 */ + + /* USER CODE END CAN1_Init 1 */ + hcan1.Instance = CAN1; + hcan1.Init.Prescaler = 3; + hcan1.Init.Mode = CAN_MODE_NORMAL; + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_10TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_3TQ; + hcan1.Init.TimeTriggeredMode = DISABLE; + hcan1.Init.AutoBusOff = DISABLE; + hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoRetransmission = ENABLE; + hcan1.Init.ReceiveFifoLocked = DISABLE; + hcan1.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN1_Init 2 */ + + /* USER CODE END CAN1_Init 2 */ + +} +/* CAN2 init function */ +void MX_CAN2_Init(void) +{ + + /* USER CODE BEGIN CAN2_Init 0 */ + + /* USER CODE END CAN2_Init 0 */ + + /* USER CODE BEGIN CAN2_Init 1 */ + + /* USER CODE END CAN2_Init 1 */ + hcan2.Instance = CAN2; + hcan2.Init.Prescaler = 3; + hcan2.Init.Mode = CAN_MODE_NORMAL; + hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan2.Init.TimeSeg1 = CAN_BS1_10TQ; + hcan2.Init.TimeSeg2 = CAN_BS2_3TQ; + hcan2.Init.TimeTriggeredMode = DISABLE; + hcan2.Init.AutoBusOff = DISABLE; + hcan2.Init.AutoWakeUp = DISABLE; + hcan2.Init.AutoRetransmission = ENABLE; + hcan2.Init.ReceiveFifoLocked = DISABLE; + hcan2.Init.TransmitFifoPriority = DISABLE; + if (HAL_CAN_Init(&hcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CAN2_Init 2 */ + + /* USER CODE END CAN2_Init 2 */ + +} + +static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0; + +void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(canHandle->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspInit 0 */ + + /* USER CODE END CAN1_MspInit 0 */ + /* CAN1 clock enable */ + HAL_RCC_CAN1_CLK_ENABLED++; + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + __HAL_RCC_CAN1_CLK_ENABLE(); + } + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**CAN1 GPIO Configuration + PD0 ------> CAN1_RX + PD1 ------> CAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* CAN1 interrupt Init */ + HAL_NVIC_SetPriority(CAN1_TX_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN1_TX_IRQn); + HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); + HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn); + HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn); + /* USER CODE BEGIN CAN1_MspInit 1 */ + + /* USER CODE END CAN1_MspInit 1 */ + } + else if(canHandle->Instance==CAN2) + { + /* USER CODE BEGIN CAN2_MspInit 0 */ + + /* USER CODE END CAN2_MspInit 0 */ + /* CAN2 clock enable */ + __HAL_RCC_CAN2_CLK_ENABLE(); + HAL_RCC_CAN1_CLK_ENABLED++; + if(HAL_RCC_CAN1_CLK_ENABLED==1){ + __HAL_RCC_CAN1_CLK_ENABLE(); + } + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**CAN2 GPIO Configuration + PB6 ------> CAN2_TX + PB12 ------> CAN2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* CAN2 interrupt Init */ + HAL_NVIC_SetPriority(CAN2_TX_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); + HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); + HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn); + /* USER CODE BEGIN CAN2_MspInit 1 */ + + /* USER CODE END CAN2_MspInit 1 */ + } +} + +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle) +{ + + if(canHandle->Instance==CAN1) + { + /* USER CODE BEGIN CAN1_MspDeInit 0 */ + + /* USER CODE END CAN1_MspDeInit 0 */ + /* Peripheral clock disable */ + HAL_RCC_CAN1_CLK_ENABLED--; + if(HAL_RCC_CAN1_CLK_ENABLED==0){ + __HAL_RCC_CAN1_CLK_DISABLE(); + } + + /**CAN1 GPIO Configuration + PD0 ------> CAN1_RX + PD1 ------> CAN1_TX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1); + + /* CAN1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(CAN1_TX_IRQn); + HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn); + HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn); + HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn); + /* USER CODE BEGIN CAN1_MspDeInit 1 */ + + /* USER CODE END CAN1_MspDeInit 1 */ + } + else if(canHandle->Instance==CAN2) + { + /* USER CODE BEGIN CAN2_MspDeInit 0 */ + + /* USER CODE END CAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CAN2_CLK_DISABLE(); + HAL_RCC_CAN1_CLK_ENABLED--; + if(HAL_RCC_CAN1_CLK_ENABLED==0){ + __HAL_RCC_CAN1_CLK_DISABLE(); + } + + /**CAN2 GPIO Configuration + PB6 ------> CAN2_TX + PB12 ------> CAN2_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_12); + + /* CAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(CAN2_TX_IRQn); + HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn); + HAL_NVIC_DisableIRQ(CAN2_SCE_IRQn); + /* USER CODE BEGIN CAN2_MspDeInit 1 */ + + /* USER CODE END CAN2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/dma.c b/Core/Src/dma.c new file mode 100644 index 0000000..c96adb8 --- /dev/null +++ b/Core/Src/dma.c @@ -0,0 +1,62 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); + /* DMA2_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/Core/Src/freertos.c b/Core/Src/freertos.c new file mode 100644 index 0000000..a0c04eb --- /dev/null +++ b/Core/Src/freertos.c @@ -0,0 +1,127 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : freertos.c + * Description : Code for freertos applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "FreeRTOS.h" +#include "task.h" +#include "main.h" +#include "cmsis_os.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +#include "task/user_task.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN Variables */ + +/* USER CODE END Variables */ +/* Definitions for defaultTask */ +osThreadId_t defaultTaskHandle; +const osThreadAttr_t defaultTask_attributes = { + .name = "defaultTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN FunctionPrototypes */ + +/* USER CODE END FunctionPrototypes */ + +void StartDefaultTask(void *argument); + +void MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */ + +/** + * @brief FreeRTOS initialization + * @param None + * @retval None + */ +void MX_FREERTOS_Init(void) { + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* USER CODE BEGIN RTOS_MUTEX */ + /* add mutexes, ... */ + /* USER CODE END RTOS_MUTEX */ + + /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* add semaphores, ... */ + /* USER CODE END RTOS_SEMAPHORES */ + + /* USER CODE BEGIN RTOS_TIMERS */ + /* start timers, add new ones, ... */ + /* USER CODE END RTOS_TIMERS */ + + /* USER CODE BEGIN RTOS_QUEUES */ + /* add queues, ... */ + /* USER CODE END RTOS_QUEUES */ + + /* Create the thread(s) */ + /* creation of defaultTask */ + defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); + + /* USER CODE BEGIN RTOS_THREADS */ + /* add threads, ... */ + osThreadNew(Task_Init, NULL, &attr_init); // 创建初始化任务 + /* USER CODE END RTOS_THREADS */ + + /* USER CODE BEGIN RTOS_EVENTS */ + /* add events, ... */ + /* USER CODE END RTOS_EVENTS */ + +} + +/* USER CODE BEGIN Header_StartDefaultTask */ +/** + * @brief Function implementing the defaultTask thread. + * @param argument: Not used + * @retval None + */ +/* USER CODE END Header_StartDefaultTask */ +void StartDefaultTask(void *argument) +{ + /* USER CODE BEGIN StartDefaultTask */ + osThreadTerminate(osThreadGetId()); + /* USER CODE END StartDefaultTask */ +} + +/* Private application code --------------------------------------------------*/ +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ + diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c new file mode 100644 index 0000000..348429a --- /dev/null +++ b/Core/Src/gpio.c @@ -0,0 +1,121 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(CMPS_RST_GPIO_Port, CMPS_RST_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(ACCL_CS_GPIO_Port, ACCL_CS_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GYRO_CS_GPIO_Port, GYRO_CS_Pin, GPIO_PIN_SET); + + /*Configure GPIO pin : CMPS_RST_Pin */ + GPIO_InitStruct.Pin = CMPS_RST_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(CMPS_RST_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : CMPS_INT_Pin */ + GPIO_InitStruct.Pin = CMPS_INT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(CMPS_INT_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_KEY_Pin */ + GPIO_InitStruct.Pin = USER_KEY_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(USER_KEY_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pin : ACCL_CS_Pin */ + GPIO_InitStruct.Pin = ACCL_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(ACCL_CS_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : ACCL_INT_Pin GYRO_INT_Pin */ + GPIO_InitStruct.Pin = ACCL_INT_Pin|GYRO_INT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : GYRO_CS_Pin */ + GPIO_InitStruct.Pin = GYRO_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; + HAL_GPIO_Init(GYRO_CS_GPIO_Port, &GPIO_InitStruct); + + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI0_IRQn); + + HAL_NVIC_SetPriority(EXTI3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI3_IRQn); + + HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI4_IRQn); + + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/Core/Src/i2c.c b/Core/Src/i2c.c new file mode 100644 index 0000000..71a00f7 --- /dev/null +++ b/Core/Src/i2c.c @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c2; + +/* I2C2 init function */ +void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + hi2c2.Init.ClockSpeed = 100000; + hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2; + hi2c2.Init.OwnAddress1 = 0; + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c2.Init.OwnAddress2 = 0; + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(i2cHandle->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspInit 0 */ + + /* USER CODE END I2C2_MspInit 0 */ + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**I2C2 GPIO Configuration + PF0 ------> I2C2_SDA + PF1 ------> I2C2_SCL + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* I2C2 clock enable */ + __HAL_RCC_I2C2_CLK_ENABLE(); + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspDeInit 0 */ + + /* USER CODE END I2C2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C2_CLK_DISABLE(); + + /**I2C2 GPIO Configuration + PF0 ------> I2C2_SDA + PF1 ------> I2C2_SCL + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_1); + + /* USER CODE BEGIN I2C2_MspDeInit 1 */ + + /* USER CODE END I2C2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..b8e108f --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,209 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "cmsis_os.h" +#include "can.h" +#include "dma.h" +#include "i2c.h" +#include "spi.h" +#include "tim.h" +#include "usart.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +void MX_FREERTOS_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_CAN1_Init(); + MX_CAN2_Init(); + MX_SPI1_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); + MX_USART3_UART_Init(); + MX_I2C2_Init(); + MX_USART6_UART_Init(); + MX_TIM10_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Init scheduler */ + osKernelInitialize(); /* Call init function for freertos objects (in cmsis_os2.c) */ + MX_FREERTOS_Init(); + + /* Start scheduler */ + osKernelStart(); + + /* We should never get here as control is now taken by the scheduler */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 168; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/spi.c b/Core/Src/spi.c new file mode 100644 index 0000000..4ad7ade --- /dev/null +++ b/Core/Src/spi.c @@ -0,0 +1,171 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SPI_HandleTypeDef hspi1; +DMA_HandleTypeDef hdma_spi1_rx; +DMA_HandleTypeDef hdma_spi1_tx; + +/* SPI1 init function */ +void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; + hspi1.Init.CLKPhase = SPI_PHASE_2EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* SPI1 clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PB4 ------> SPI1_MISO + PB3 ------> SPI1_SCK + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* SPI1 DMA Init */ + /* SPI1_RX Init */ + hdma_spi1_rx.Instance = DMA2_Stream2; + hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3; + hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi1_rx.Init.Mode = DMA_NORMAL; + hdma_spi1_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi1_rx); + + /* SPI1_TX Init */ + hdma_spi1_tx.Instance = DMA2_Stream3; + hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3; + hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi1_tx.Init.Mode = DMA_NORMAL; + hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH; + hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) +{ + + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PB4 ------> SPI1_MISO + PB3 ------> SPI1_SCK + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7); + + /* SPI1 DMA DeInit */ + HAL_DMA_DeInit(spiHandle->hdmarx); + HAL_DMA_DeInit(spiHandle->hdmatx); + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c new file mode 100644 index 0000000..a4e2b79 --- /dev/null +++ b/Core/Src/stm32f4xx_hal_msp.c @@ -0,0 +1,84 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c new file mode 100644 index 0000000..0f1d615 --- /dev/null +++ b/Core/Src/stm32f4xx_it.c @@ -0,0 +1,435 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f4xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f4xx_it.h" +#include "FreeRTOS.h" +#include "task.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "bsp/uart.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern CAN_HandleTypeDef hcan1; +extern CAN_HandleTypeDef hcan2; +extern DMA_HandleTypeDef hdma_spi1_rx; +extern DMA_HandleTypeDef hdma_spi1_tx; +extern DMA_HandleTypeDef hdma_usart3_rx; +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +extern UART_HandleTypeDef huart6; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M4 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + { +#endif /* INCLUDE_xTaskGetSchedulerState */ + xPortSysTickHandler(); +#if (INCLUDE_xTaskGetSchedulerState == 1 ) + } +#endif /* INCLUDE_xTaskGetSchedulerState */ + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F4xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f4xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles EXTI line0 interrupt. + */ +void EXTI0_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI0_IRQn 0 */ + + /* USER CODE END EXTI0_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(USER_KEY_Pin); + /* USER CODE BEGIN EXTI0_IRQn 1 */ + + /* USER CODE END EXTI0_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line3 interrupt. + */ +void EXTI3_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI3_IRQn 0 */ + + /* USER CODE END EXTI3_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(CMPS_INT_Pin); + /* USER CODE BEGIN EXTI3_IRQn 1 */ + + /* USER CODE END EXTI3_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line4 interrupt. + */ +void EXTI4_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI4_IRQn 0 */ + + /* USER CODE END EXTI4_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(ACCL_INT_Pin); + /* USER CODE BEGIN EXTI4_IRQn 1 */ + + /* USER CODE END EXTI4_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream1 global interrupt. + */ +void DMA1_Stream1_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ + + /* USER CODE END DMA1_Stream1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart3_rx); + /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ + + /* USER CODE END DMA1_Stream1_IRQn 1 */ +} + +/** + * @brief This function handles CAN1 TX interrupts. + */ +void CAN1_TX_IRQHandler(void) +{ + /* USER CODE BEGIN CAN1_TX_IRQn 0 */ + + /* USER CODE END CAN1_TX_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + /* USER CODE BEGIN CAN1_TX_IRQn 1 */ + + /* USER CODE END CAN1_TX_IRQn 1 */ +} + +/** + * @brief This function handles CAN1 RX0 interrupts. + */ +void CAN1_RX0_IRQHandler(void) +{ + /* USER CODE BEGIN CAN1_RX0_IRQn 0 */ + + /* USER CODE END CAN1_RX0_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + /* USER CODE BEGIN CAN1_RX0_IRQn 1 */ + + /* USER CODE END CAN1_RX0_IRQn 1 */ +} + +/** + * @brief This function handles CAN1 RX1 interrupt. + */ +void CAN1_RX1_IRQHandler(void) +{ + /* USER CODE BEGIN CAN1_RX1_IRQn 0 */ + + /* USER CODE END CAN1_RX1_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + /* USER CODE BEGIN CAN1_RX1_IRQn 1 */ + + /* USER CODE END CAN1_RX1_IRQn 1 */ +} + +/** + * @brief This function handles CAN1 SCE interrupt. + */ +void CAN1_SCE_IRQHandler(void) +{ + /* USER CODE BEGIN CAN1_SCE_IRQn 0 */ + + /* USER CODE END CAN1_SCE_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + /* USER CODE BEGIN CAN1_SCE_IRQn 1 */ + + /* USER CODE END CAN1_SCE_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line[9:5] interrupts. + */ +void EXTI9_5_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ + + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(GYRO_INT_Pin); + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ + + /* USER CODE END EXTI9_5_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + BSP_UART_IRQHandler(&huart1); + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream2 global interrupt. + */ +void DMA2_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ + + /* USER CODE END DMA2_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi1_rx); + /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ + + /* USER CODE END DMA2_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream3 global interrupt. + */ +void DMA2_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */ + + /* USER CODE END DMA2_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi1_tx); + /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */ + + /* USER CODE END DMA2_Stream3_IRQn 1 */ +} + +/** + * @brief This function handles CAN2 TX interrupts. + */ +void CAN2_TX_IRQHandler(void) +{ + /* USER CODE BEGIN CAN2_TX_IRQn 0 */ + + /* USER CODE END CAN2_TX_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + /* USER CODE BEGIN CAN2_TX_IRQn 1 */ + + /* USER CODE END CAN2_TX_IRQn 1 */ +} + +/** + * @brief This function handles CAN2 RX1 interrupt. + */ +void CAN2_RX1_IRQHandler(void) +{ + /* USER CODE BEGIN CAN2_RX1_IRQn 0 */ + + /* USER CODE END CAN2_RX1_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + /* USER CODE BEGIN CAN2_RX1_IRQn 1 */ + + /* USER CODE END CAN2_RX1_IRQn 1 */ +} + +/** + * @brief This function handles CAN2 SCE interrupt. + */ +void CAN2_SCE_IRQHandler(void) +{ + /* USER CODE BEGIN CAN2_SCE_IRQn 0 */ + + /* USER CODE END CAN2_SCE_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + /* USER CODE BEGIN CAN2_SCE_IRQn 1 */ + + /* USER CODE END CAN2_SCE_IRQn 1 */ +} + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + /* USER CODE BEGIN USART6_IRQn 0 */ + + /* USER CODE END USART6_IRQn 0 */ + HAL_UART_IRQHandler(&huart6); + /* USER CODE BEGIN USART6_IRQn 1 */ + BSP_UART_IRQHandler(&huart6); + + /* USER CODE END USART6_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/system_stm32f4xx.c b/Core/Src/system_stm32f4xx.c new file mode 100644 index 0000000..7a61e9c --- /dev/null +++ b/Core/Src/system_stm32f4xx.c @@ -0,0 +1,747 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp, pllvco, pllp, pllsource, pllm; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Core/Src/tim.c b/Core/Src/tim.c new file mode 100644 index 0000000..0996279 --- /dev/null +++ b/Core/Src/tim.c @@ -0,0 +1,132 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim10; + +/* TIM10 init function */ +void MX_TIM10_Init(void) +{ + + /* USER CODE BEGIN TIM10_Init 0 */ + + /* USER CODE END TIM10_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM10_Init 1 */ + + /* USER CODE END TIM10_Init 1 */ + htim10.Instance = TIM10; + htim10.Init.Prescaler = 0; + htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + htim10.Init.Period = 5000; + htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim10, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM10_Init 2 */ + + /* USER CODE END TIM10_Init 2 */ + HAL_TIM_MspPostInit(&htim10); + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspInit 0 */ + + /* USER CODE END TIM10_MspInit 0 */ + /* TIM10 clock enable */ + __HAL_RCC_TIM10_CLK_ENABLE(); + /* USER CODE BEGIN TIM10_MspInit 1 */ + + /* USER CODE END TIM10_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspPostInit 0 */ + + /* USER CODE END TIM10_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM10 GPIO Configuration + PB8 ------> TIM10_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM10; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM10_MspPostInit 1 */ + + /* USER CODE END TIM10_MspPostInit 1 */ + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspDeInit 0 */ + + /* USER CODE END TIM10_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM10_CLK_DISABLE(); + /* USER CODE BEGIN TIM10_MspDeInit 1 */ + + /* USER CODE END TIM10_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c new file mode 100644 index 0000000..b727c46 --- /dev/null +++ b/Core/Src/usart.c @@ -0,0 +1,377 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; +UART_HandleTypeDef huart3; +UART_HandleTypeDef huart6; +DMA_HandleTypeDef hdma_usart3_rx; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 100000; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_EVEN; + huart3.Init.Mode = UART_MODE_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} +/* USART6 init function */ + +void MX_USART6_UART_Init(void) +{ + + /* USER CODE BEGIN USART6_Init 0 */ + + /* USER CODE END USART6_Init 0 */ + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + huart6.Instance = USART6; + huart6.Init.BaudRate = 115200; + huart6.Init.WordLength = UART_WORDLENGTH_8B; + huart6.Init.StopBits = UART_STOPBITS_1; + huart6.Init.Parity = UART_PARITY_NONE; + huart6.Init.Mode = UART_MODE_TX_RX; + huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart6.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart6) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART2 GPIO Configuration + PD6 ------> USART2_RX + PD5 ------> USART2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + /* USART3 clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + /**USART3 GPIO Configuration + PC11 ------> USART3_RX + PC10 ------> USART3_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USART3 DMA Init */ + /* USART3_RX Init */ + hdma_usart3_rx.Instance = DMA1_Stream1; + hdma_usart3_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart3_rx.Init.Mode = DMA_CIRCULAR; + hdma_usart3_rx.Init.Priority = DMA_PRIORITY_HIGH; + hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + else if(uartHandle->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspInit 0 */ + + /* USER CODE END USART6_MspInit 0 */ + /* USART6 clock enable */ + __HAL_RCC_USART6_CLK_ENABLE(); + + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**USART6 GPIO Configuration + PG14 ------> USART6_TX + PG9 ------> USART6_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USART6 interrupt Init */ + HAL_NVIC_SetPriority(USART6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(USART6_IRQn); + /* USER CODE BEGIN USART6_MspInit 1 */ + + /* USER CODE END USART6_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB7 ------> USART1_RX + PA9 ------> USART1_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PD6 ------> USART2_RX + PD5 ------> USART2_TX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6|GPIO_PIN_5); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PC11 ------> USART3_RX + PC10 ------> USART3_TX + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_11|GPIO_PIN_10); + + /* USART3 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART6) + { + /* USER CODE BEGIN USART6_MspDeInit 0 */ + + /* USER CODE END USART6_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART6_CLK_DISABLE(); + + /**USART6 GPIO Configuration + PG14 ------> USART6_TX + PG9 ------> USART6_RX + */ + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_9); + + /* USART6 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART6_IRQn); + /* USER CODE BEGIN USART6_MspDeInit 1 */ + + /* USER CODE END USART6_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Drivers/CMSIS/Core/Include/cachel1_armv7.h b/Drivers/CMSIS/Core/Include/cachel1_armv7.h new file mode 100644 index 0000000..abebc95 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/Drivers/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..a955d47 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/Drivers/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1e255d5 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/Drivers/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/Drivers/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core/Include/cmsis_version.h b/Drivers/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/Drivers/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Core/Include/core_armv81mml.h b/Drivers/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000..94128a1 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/Drivers/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..932d3d1 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_armv8mml.h b/Drivers/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..c119fbf --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0.h b/Drivers/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..6441ff3 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm0plus.h b/Drivers/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..4e7179a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm1.h b/Drivers/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm23.h b/Drivers/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..55fff99 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm3.h b/Drivers/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..74fb87e --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm33.h b/Drivers/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..18a2e6f --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm35p.h b/Drivers/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000..3843d95 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm4.h b/Drivers/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..e21cd14 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm55.h b/Drivers/CMSIS/Core/Include/core_cm55.h new file mode 100644 index 0000000..faa30ce --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm7.h b/Drivers/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..010506e --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_cm85.h b/Drivers/CMSIS/Core/Include/core_cm85.h new file mode 100644 index 0000000..6046311 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc000.h b/Drivers/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..dbc755f --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_sc300.h b/Drivers/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..d666210 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/core_starmc1.h b/Drivers/CMSIS/Core/Include/core_starmc1.h new file mode 100644 index 0000000..d86c8d3 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core/Include/mpu_armv7.h b/Drivers/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Core/Include/mpu_armv8.h b/Drivers/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..3de16ef --- /dev/null +++ b/Drivers/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Core/Include/pac_armv81.h b/Drivers/CMSIS/Core/Include/pac_armv81.h new file mode 100644 index 0000000..854b60a --- /dev/null +++ b/Drivers/CMSIS/Core/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/Drivers/CMSIS/Core/Include/pmu_armv8.h b/Drivers/CMSIS/Core/Include/pmu_armv8.h new file mode 100644 index 0000000..f8f3d89 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/Drivers/CMSIS/Core/Include/tz_context.h b/Drivers/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000..273607b --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000..e2e8294 --- /dev/null +++ b/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h new file mode 100644 index 0000000..0d9c374 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h @@ -0,0 +1,563 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.5 + * @date 05. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + */ +#define __DMB() __dmb(0xF) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(void); */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R1,FPSCR + LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R1,R1,R2 + VMSR FPSCR,R1 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h new file mode 100644 index 0000000..e64eba9 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h @@ -0,0 +1,614 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.2.1 + * @date 05. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() __builtin_arm_dsb(0xF) + +/** + \brief Data Memory Barrier + */ +#define __DMB() __builtin_arm_dmb(0xF) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD8 __builtin_arm_qadd8 +#define __QSUB8 __builtin_arm_qsub8 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __SXTB16 __builtin_arm_sxtb16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSDX __builtin_arm_smlsdx +#define __USAT16 __builtin_arm_usat16 +#define __SSUB8 __builtin_arm_ssub8 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 + + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h new file mode 100644 index 0000000..dfd07a2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h @@ -0,0 +1,213 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h new file mode 100644 index 0000000..891bec2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h new file mode 100644 index 0000000..920d612 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h @@ -0,0 +1,917 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.3.2 + * @date 24. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h new file mode 100644 index 0000000..08aa224 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -0,0 +1,573 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 15. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Core_A/Include/core_ca.h b/Drivers/CMSIS/Core_A/Include/core_ca.h new file mode 100644 index 0000000..c4f9269 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/core_ca.h @@ -0,0 +1,2614 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.3 + * @date 28. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h new file mode 100644 index 0000000..1ca29a2 --- /dev/null +++ b/Drivers/CMSIS/Core_A/Include/irq_ctrl.h @@ -0,0 +1,192 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.1.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +// Encoding in some early GIC implementations +#define IRQ_MODE_MODEL_Pos (13U) +#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos) +#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model +#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c new file mode 100644 index 0000000..15588bf --- /dev/null +++ b/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -0,0 +1,418 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.1.1 + * @date 29. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + int32_t status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + cfg = 0x00U; + status = -1; + } + + val = (mode & IRQ_MODE_MODEL_Msk); + if (val == IRQ_MODE_MODEL_1N) { + cfg |= 1; // 1-N model + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0U; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1U; + } else { + secure = 0U; + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFFU; + } else { + cpu = (uint8_t)(val >> IRQ_MODE_CPU_Pos); + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + if (val & 1U) { + mode |= IRQ_MODE_MODEL_1N; + } + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt (irq); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h b/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h new file mode 100644 index 0000000..5e62cf4 --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Config/DAP_config.h @@ -0,0 +1,561 @@ +/* + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 16. June 2021 + * $Revision: V2.1.0 + * + * Project: CMSIS-DAP Configuration + * Title: DAP_config.h CMSIS-DAP Configuration File (Template) + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). + - Debug Unit communication packet size. + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#ifdef _RTE_ +#include "RTE_Components.h" +#include CMSIS_device_header +#else +#include "device.h" // Debug Unit Cortex-M Processor Header File +#endif + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 100000000U ///< Specifies the CPU Clock in Hz. + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#define DAP_PACKET_SIZE 512U ///< Specifies Packet Size in bytes. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). +#define DAP_PACKET_COUNT 8U ///< Specifies number of packets buffered. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART SWO. +#define SWO_UART_DRIVER 0 ///< USART Driver instance number (Driver_USART#). + +/// Maximum SWO UART Baudrate. +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 100000000U ///< Timestamp clock in Hz (0 = timestamps not supported). + +/// Indicate that UART Communication Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART 1 ///< DAP UART: 1 = available, 0 = not available. + +/// USART Driver instance number for the UART Communication Port. +#define DAP_UART_DRIVER 1 ///< USART Driver instance number (Driver_USART#). + +/// UART Receive Buffer Size. +#define DAP_UART_RX_BUFFER_SIZE 1024U ///< Uart Receive Buffer Size in bytes (must be 2^n). + +/// UART Transmit Buffer Size. +#define DAP_UART_TX_BUFFER_SIZE 1024U ///< Uart Transmit Buffer Size in bytes (must be 2^n). + +/// Indicate that UART Communication via USB COM Port is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_UART_USB_COM_PORT 1 ///< USB COM Port: 1 = available, 0 = not available. + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor, Device Name, Board Vendor and Board Name strings +/// are stored and may be used by the debugger or IDE to configure device parameters. +#define TARGET_FIXED 0 ///< Target: 1 = known, 0 = unknown; + +#define TARGET_DEVICE_VENDOR "Arm" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Cortex-M" ///< String indicating the Target Device +#define TARGET_BOARD_VENDOR "Arm" ///< String indicating the Board Vendor +#define TARGET_BOARD_NAME "Arm board" ///< String indicating the Board Name + +#if TARGET_FIXED != 0 +#include +static const char TargetDeviceVendor [] = TARGET_DEVICE_VENDOR; +static const char TargetDeviceName [] = TARGET_DEVICE_NAME; +static const char TargetBoardVendor [] = TARGET_BOARD_VENDOR; +static const char TargetBoardName [] = TARGET_BOARD_NAME; +#endif + +/** Get Vendor Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { + (void)str; + return (0U); +} + +/** Get Product Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { + (void)str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { + (void)str; + return (0U); +} + +/** Get Target Device Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceVendor); + len = (uint8_t)(strlen(TargetDeviceVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Device Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetDeviceNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetDeviceName); + len = (uint8_t)(strlen(TargetDeviceName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Vendor string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardVendorString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardVendor); + len = (uint8_t)(strlen(TargetBoardVendor) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Target Board Name string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetTargetBoardNameString (char *str) { +#if TARGET_FIXED != 0 + uint8_t len; + + strcpy(str, TargetBoardName); + len = (uint8_t)(strlen(TargetBoardName) + 1U); + return (len); +#else + (void)str; + return (0U); +#endif +} + +/** Get Product Firmware Version string. +\param str Pointer to buffer to store the string (max 60 characters). +\return String length (including terminating NULL character) or 0 (no string). +*/ +__STATIC_INLINE uint8_t DAP_GetProductFirmwareVersionString (char *str) { + (void)str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP (void) { + ; +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP (void) { + ; +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF (void) { + ; +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { + return (0U); +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { + ; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { + ; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { + return (0U); +} + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { + ; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { + ; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { + return (0U); +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { + ; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { + ; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { + ; +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { + return (0U); +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { + ; +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { + return (0U); +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { + return (0U); +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { + ; +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { + return (0U); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { + ; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { + return (DWT->CYCCNT); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP (void) { + ; +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint8_t RESET_TARGET (void) { + return (0U); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/Drivers/CMSIS/DAP/Firmware/Include/DAP.h b/Drivers/CMSIS/DAP/Firmware/Include/DAP.h new file mode 100644 index 0000000..55cf686 --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Include/DAP.h @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Include + * Title: DAP.h Definitions + * + *---------------------------------------------------------------------------*/ + +#ifndef __DAP_H__ +#define __DAP_H__ + + +// DAP Firmware Version +#ifdef DAP_FW_V1 +#define DAP_FW_VER "1.3.0" +#else +#define DAP_FW_VER "2.1.1" +#endif + +// DAP Command IDs +#define ID_DAP_Info 0x00U +#define ID_DAP_HostStatus 0x01U +#define ID_DAP_Connect 0x02U +#define ID_DAP_Disconnect 0x03U +#define ID_DAP_TransferConfigure 0x04U +#define ID_DAP_Transfer 0x05U +#define ID_DAP_TransferBlock 0x06U +#define ID_DAP_TransferAbort 0x07U +#define ID_DAP_WriteABORT 0x08U +#define ID_DAP_Delay 0x09U +#define ID_DAP_ResetTarget 0x0AU +#define ID_DAP_SWJ_Pins 0x10U +#define ID_DAP_SWJ_Clock 0x11U +#define ID_DAP_SWJ_Sequence 0x12U +#define ID_DAP_SWD_Configure 0x13U +#define ID_DAP_SWD_Sequence 0x1DU +#define ID_DAP_JTAG_Sequence 0x14U +#define ID_DAP_JTAG_Configure 0x15U +#define ID_DAP_JTAG_IDCODE 0x16U +#define ID_DAP_SWO_Transport 0x17U +#define ID_DAP_SWO_Mode 0x18U +#define ID_DAP_SWO_Baudrate 0x19U +#define ID_DAP_SWO_Control 0x1AU +#define ID_DAP_SWO_Status 0x1BU +#define ID_DAP_SWO_ExtendedStatus 0x1EU +#define ID_DAP_SWO_Data 0x1CU +#define ID_DAP_UART_Transport 0x1FU +#define ID_DAP_UART_Configure 0x20U +#define ID_DAP_UART_Control 0x22U +#define ID_DAP_UART_Status 0x23U +#define ID_DAP_UART_Transfer 0x21U + +#define ID_DAP_QueueCommands 0x7EU +#define ID_DAP_ExecuteCommands 0x7FU + +// DAP Vendor Command IDs +#define ID_DAP_Vendor0 0x80U +#define ID_DAP_Vendor1 0x81U +#define ID_DAP_Vendor2 0x82U +#define ID_DAP_Vendor3 0x83U +#define ID_DAP_Vendor4 0x84U +#define ID_DAP_Vendor5 0x85U +#define ID_DAP_Vendor6 0x86U +#define ID_DAP_Vendor7 0x87U +#define ID_DAP_Vendor8 0x88U +#define ID_DAP_Vendor9 0x89U +#define ID_DAP_Vendor10 0x8AU +#define ID_DAP_Vendor11 0x8BU +#define ID_DAP_Vendor12 0x8CU +#define ID_DAP_Vendor13 0x8DU +#define ID_DAP_Vendor14 0x8EU +#define ID_DAP_Vendor15 0x8FU +#define ID_DAP_Vendor16 0x90U +#define ID_DAP_Vendor17 0x91U +#define ID_DAP_Vendor18 0x92U +#define ID_DAP_Vendor19 0x93U +#define ID_DAP_Vendor20 0x94U +#define ID_DAP_Vendor21 0x95U +#define ID_DAP_Vendor22 0x96U +#define ID_DAP_Vendor23 0x97U +#define ID_DAP_Vendor24 0x98U +#define ID_DAP_Vendor25 0x99U +#define ID_DAP_Vendor26 0x9AU +#define ID_DAP_Vendor27 0x9BU +#define ID_DAP_Vendor28 0x9CU +#define ID_DAP_Vendor29 0x9DU +#define ID_DAP_Vendor30 0x9EU +#define ID_DAP_Vendor31 0x9FU + +#define ID_DAP_Invalid 0xFFU + +// DAP Status Code +#define DAP_OK 0U +#define DAP_ERROR 0xFFU + +// DAP ID +#define DAP_ID_VENDOR 1U +#define DAP_ID_PRODUCT 2U +#define DAP_ID_SER_NUM 3U +#define DAP_ID_DAP_FW_VER 4U +#define DAP_ID_DEVICE_VENDOR 5U +#define DAP_ID_DEVICE_NAME 6U +#define DAP_ID_BOARD_VENDOR 7U +#define DAP_ID_BOARD_NAME 8U +#define DAP_ID_PRODUCT_FW_VER 9U +#define DAP_ID_CAPABILITIES 0xF0U +#define DAP_ID_TIMESTAMP_CLOCK 0xF1U +#define DAP_ID_UART_RX_BUFFER_SIZE 0xFBU +#define DAP_ID_UART_TX_BUFFER_SIZE 0xFCU +#define DAP_ID_SWO_BUFFER_SIZE 0xFDU +#define DAP_ID_PACKET_COUNT 0xFEU +#define DAP_ID_PACKET_SIZE 0xFFU + +// DAP Host Status +#define DAP_DEBUGGER_CONNECTED 0U +#define DAP_TARGET_RUNNING 1U + +// DAP Port +#define DAP_PORT_AUTODETECT 0U // Autodetect Port +#define DAP_PORT_DISABLED 0U // Port Disabled (I/O pins in High-Z) +#define DAP_PORT_SWD 1U // SWD Port (SWCLK, SWDIO) + nRESET +#define DAP_PORT_JTAG 2U // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET + +// DAP SWJ Pins +#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK +#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS +#define DAP_SWJ_TDI 2 // TDI +#define DAP_SWJ_TDO 3 // TDO +#define DAP_SWJ_nTRST 5 // nTRST +#define DAP_SWJ_nRESET 7 // nRESET + +// DAP Transfer Request +#define DAP_TRANSFER_APnDP (1U<<0) +#define DAP_TRANSFER_RnW (1U<<1) +#define DAP_TRANSFER_A2 (1U<<2) +#define DAP_TRANSFER_A3 (1U<<3) +#define DAP_TRANSFER_MATCH_VALUE (1U<<4) +#define DAP_TRANSFER_MATCH_MASK (1U<<5) +#define DAP_TRANSFER_TIMESTAMP (1U<<7) + +// DAP Transfer Response +#define DAP_TRANSFER_OK (1U<<0) +#define DAP_TRANSFER_WAIT (1U<<1) +#define DAP_TRANSFER_FAULT (1U<<2) +#define DAP_TRANSFER_ERROR (1U<<3) +#define DAP_TRANSFER_MISMATCH (1U<<4) + +// DAP SWO Trace Mode +#define DAP_SWO_OFF 0U +#define DAP_SWO_UART 1U +#define DAP_SWO_MANCHESTER 2U + +// DAP SWO Trace Status +#define DAP_SWO_CAPTURE_ACTIVE (1U<<0) +#define DAP_SWO_CAPTURE_PAUSED (1U<<1) +#define DAP_SWO_STREAM_ERROR (1U<<6) +#define DAP_SWO_BUFFER_OVERRUN (1U<<7) + +// DAP UART Transport +#define DAP_UART_TRANSPORT_NONE 0U +#define DAP_UART_TRANSPORT_USB_COM_PORT 1U +#define DAP_UART_TRANSPORT_DAP_COMMAND 2U + +// DAP UART Control +#define DAP_UART_CONTROL_RX_ENABLE (1U<<0) +#define DAP_UART_CONTROL_RX_DISABLE (1U<<1) +#define DAP_UART_CONTROL_RX_BUF_FLUSH (1U<<2) +#define DAP_UART_CONTROL_TX_ENABLE (1U<<4) +#define DAP_UART_CONTROL_TX_DISABLE (1U<<5) +#define DAP_UART_CONTROL_TX_BUF_FLUSH (1U<<6) + +// DAP UART Status +#define DAP_UART_STATUS_RX_ENABLED (1U<<0) +#define DAP_UART_STATUS_RX_DATA_LOST (1U<<1) +#define DAP_UART_STATUS_FRAMING_ERROR (1U<<2) +#define DAP_UART_STATUS_PARITY_ERROR (1U<<3) +#define DAP_UART_STATUS_TX_ENABLED (1U<<4) + +// DAP UART Configure Error +#define DAP_UART_CFG_ERROR_DATA_BITS (1U<<0) +#define DAP_UART_CFG_ERROR_PARITY (1U<<1) +#define DAP_UART_CFG_ERROR_STOP_BITS (1U<<2) + +// Debug Port Register Addresses +#define DP_IDCODE 0x00U // IDCODE Register (SW Read only) +#define DP_ABORT 0x00U // Abort Register (SW Write only) +#define DP_CTRL_STAT 0x04U // Control & Status +#define DP_WCR 0x04U // Wire Control Register (SW Only) +#define DP_SELECT 0x08U // Select Register (JTAG R/W & SW W) +#define DP_RESEND 0x08U // Resend (SW Read Only) +#define DP_RDBUFF 0x0CU // Read Buffer (Read Only) + +// JTAG IR Codes +#define JTAG_ABORT 0x08U +#define JTAG_DPACC 0x0AU +#define JTAG_APACC 0x0BU +#define JTAG_IDCODE 0x0EU +#define JTAG_BYPASS 0x0FU + +// JTAG Sequence Info +#define JTAG_SEQUENCE_TCK 0x3FU // TCK count +#define JTAG_SEQUENCE_TMS 0x40U // TMS value +#define JTAG_SEQUENCE_TDO 0x80U // TDO capture + +// SWD Sequence Info +#define SWD_SEQUENCE_CLK 0x3FU // SWCLK count +#define SWD_SEQUENCE_DIN 0x80U // SWDIO capture + + +#include +#include +#include "cmsis_compiler.h" + +// DAP Data structure +typedef struct { + uint8_t debug_port; // Debug Port + uint8_t fast_clock; // Fast Clock Flag + uint8_t padding[2]; + uint32_t clock_delay; // Clock Delay + uint32_t timestamp; // Last captured Timestamp + struct { // Transfer Configuration + uint8_t idle_cycles; // Idle cycles after transfer + uint8_t padding[3]; + uint16_t retry_count; // Number of retries after WAIT response + uint16_t match_retry; // Number of retries if read value does not match + uint32_t match_mask; // Match Mask + } transfer; +#if (DAP_SWD != 0) + struct { // SWD Configuration + uint8_t turnaround; // Turnaround period + uint8_t data_phase; // Always generate Data Phase + } swd_conf; +#endif +#if (DAP_JTAG != 0) + struct { // JTAG Device Chain + uint8_t count; // Number of devices + uint8_t index; // Device index (device at TDO has index 0) +#if (DAP_JTAG_DEV_CNT != 0) + uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits + uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR + uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR +#endif + } jtag_dev; +#endif +} DAP_Data_t; + +extern DAP_Data_t DAP_Data; // DAP Data +extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +#ifdef __cplusplus +extern "C" +{ +#endif + +// Functions +extern void SWJ_Sequence (uint32_t count, const uint8_t *data); +extern void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi); +extern void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo); +extern void JTAG_IR (uint32_t ir); +extern uint32_t JTAG_ReadIDCode (void); +extern void JTAG_WriteAbort (uint32_t data); +extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data); +extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data); + +extern void Delayms (uint32_t delay); + +extern uint32_t SWO_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Mode (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Control (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Status (uint8_t *response); +extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response); +extern uint32_t SWO_Data (const uint8_t *request, uint8_t *response); + +extern void SWO_QueueTransfer (uint8_t *buf, uint32_t num); +extern void SWO_AbortTransfer (void); +extern void SWO_TransferComplete (void); + +extern uint32_t SWO_Mode_UART (uint32_t enable); +extern uint32_t SWO_Baudrate_UART (uint32_t baudrate); +extern uint32_t SWO_Control_UART (uint32_t active); +extern void SWO_Capture_UART (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_UART (void); + +extern uint32_t SWO_Mode_Manchester (uint32_t enable); +extern uint32_t SWO_Baudrate_Manchester (uint32_t baudrate); +extern uint32_t SWO_Control_Manchester (uint32_t active); +extern void SWO_Capture_Manchester (uint8_t *buf, uint32_t num); +extern uint32_t SWO_GetCount_Manchester (void); + +extern uint32_t UART_Transport (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Configure (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Control (const uint8_t *request, uint8_t *response); +extern uint32_t UART_Status (uint8_t *response); +extern uint32_t UART_Transfer (const uint8_t *request, uint8_t *response); + +extern uint8_t USB_COM_PORT_Activate (uint32_t cmd); + +extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ProcessCommand (const uint8_t *request, uint8_t *response); +extern uint32_t DAP_ExecuteCommand (const uint8_t *request, uint8_t *response); + +extern void DAP_Setup (void); + +// Configurable delay for clock generation +#ifndef DELAY_SLOW_CYCLES +#define DELAY_SLOW_CYCLES 3U // Number of cycles for one iteration +#endif +#if defined(__CC_ARM) +__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { + uint32_t count = delay; + while (--count); +} +#else +__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) { + __ASM volatile ( + ".syntax unified\n" + "0:\n\t" + "subs %0,%0,#1\n\t" + "bne 0b\n" + : "+l" (delay) : : "cc" + ); +} +#endif + +// Fixed delay for fast clock generation +#ifndef DELAY_FAST_CYCLES +#define DELAY_FAST_CYCLES 0U // Number of cycles: 0..3 +#endif +__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) { +#if (DELAY_FAST_CYCLES >= 1U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 2U) + __NOP(); +#endif +#if (DELAY_FAST_CYCLES >= 3U) + __NOP(); +#endif +} + +#ifdef __cplusplus +} +#endif + + +#endif /* __DAP_H__ */ diff --git a/Drivers/CMSIS/DAP/Firmware/Source/DAP.c b/Drivers/CMSIS/DAP/Firmware/Source/DAP.c new file mode 100644 index 0000000..606917e --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/DAP.c @@ -0,0 +1,1812 @@ +/* + * Copyright (c) 2013-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 26. April 2022 + * $Revision: V2.1.1 + * + * Project: CMSIS-DAP Source + * Title: DAP.c CMSIS-DAP Commands + * + *---------------------------------------------------------------------------*/ + +#include +#include "DAP_config.h" +#include "DAP.h" + + +#if (DAP_PACKET_SIZE < 64U) +#error "Minimum Packet Size is 64!" +#endif +#if (DAP_PACKET_SIZE > 32768U) +#error "Maximum Packet Size is 32768!" +#endif +#if (DAP_PACKET_COUNT < 1U) +#error "Minimum Packet Count is 1!" +#endif +#if (DAP_PACKET_COUNT > 255U) +#error "Maximum Packet Count is 255!" +#endif + + +// Clock Macros +#define MAX_SWJ_CLOCK(delay_cycles) \ + ((CPU_CLOCK/2U) / (IO_PORT_WRITE_CYCLES + delay_cycles)) + + + DAP_Data_t DAP_Data; // DAP Data +volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag + + +static const char DAP_FW_Ver [] = DAP_FW_VER; + + +// Common clock delay calculation routine +// clock: requested SWJ frequency in Hertz +static void Set_Clock_Delay(uint32_t clock) { + uint32_t delay; + + if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES)) { + DAP_Data.fast_clock = 1U; + DAP_Data.clock_delay = 1U; + } else { + DAP_Data.fast_clock = 0U; + + delay = ((CPU_CLOCK/2U) + (clock - 1U)) / clock; + if (delay > IO_PORT_WRITE_CYCLES) { + delay -= IO_PORT_WRITE_CYCLES; + delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES; + } else { + delay = 1U; + } + + DAP_Data.clock_delay = delay; + } +} + + +// Get DAP Information +// id: info identifier +// info: pointer to info data +// return: number of bytes in info data +static uint8_t DAP_Info(uint8_t id, uint8_t *info) { + uint8_t length = 0U; + + switch (id) { + case DAP_ID_VENDOR: + length = DAP_GetVendorString((char *)info); + break; + case DAP_ID_PRODUCT: + length = DAP_GetProductString((char *)info); + break; + case DAP_ID_SER_NUM: + length = DAP_GetSerNumString((char *)info); + break; + case DAP_ID_DAP_FW_VER: + length = (uint8_t)sizeof(DAP_FW_Ver); + memcpy(info, DAP_FW_Ver, length); + break; + case DAP_ID_DEVICE_VENDOR: + length = DAP_GetTargetDeviceVendorString((char *)info); + break; + case DAP_ID_DEVICE_NAME: + length = DAP_GetTargetDeviceNameString((char *)info); + break; + case DAP_ID_BOARD_VENDOR: + length = DAP_GetTargetBoardVendorString((char *)info); + break; + case DAP_ID_BOARD_NAME: + length = DAP_GetTargetBoardNameString((char *)info); + break; + case DAP_ID_PRODUCT_FW_VER: + length = DAP_GetProductFirmwareVersionString((char *)info); + break; + case DAP_ID_CAPABILITIES: + info[0] = ((DAP_SWD != 0) ? (1U << 0) : 0U) | + ((DAP_JTAG != 0) ? (1U << 1) : 0U) | + ((SWO_UART != 0) ? (1U << 2) : 0U) | + ((SWO_MANCHESTER != 0) ? (1U << 3) : 0U) | + /* Atomic Commands */ (1U << 4) | + ((TIMESTAMP_CLOCK != 0U) ? (1U << 5) : 0U) | + ((SWO_STREAM != 0U) ? (1U << 6) : 0U) | + ((DAP_UART != 0U) ? (1U << 7) : 0U); + + info[1] = ((DAP_UART_USB_COM_PORT != 0) ? (1U << 0) : 0U); + length = 2U; + break; + case DAP_ID_TIMESTAMP_CLOCK: +#if (TIMESTAMP_CLOCK != 0U) + info[0] = (uint8_t)(TIMESTAMP_CLOCK >> 0); + info[1] = (uint8_t)(TIMESTAMP_CLOCK >> 8); + info[2] = (uint8_t)(TIMESTAMP_CLOCK >> 16); + info[3] = (uint8_t)(TIMESTAMP_CLOCK >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_RX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_RX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_UART_TX_BUFFER_SIZE: +#if (DAP_UART != 0) + info[0] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(DAP_UART_TX_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_SWO_BUFFER_SIZE: +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + info[0] = (uint8_t)(SWO_BUFFER_SIZE >> 0); + info[1] = (uint8_t)(SWO_BUFFER_SIZE >> 8); + info[2] = (uint8_t)(SWO_BUFFER_SIZE >> 16); + info[3] = (uint8_t)(SWO_BUFFER_SIZE >> 24); + length = 4U; +#endif + break; + case DAP_ID_PACKET_SIZE: + info[0] = (uint8_t)(DAP_PACKET_SIZE >> 0); + info[1] = (uint8_t)(DAP_PACKET_SIZE >> 8); + length = 2U; + break; + case DAP_ID_PACKET_COUNT: + info[0] = DAP_PACKET_COUNT; + length = 1U; + break; + default: + break; + } + + return (length); +} + + +// Delay for specified time +// delay: delay time in ms +void Delayms(uint32_t delay) { + delay *= ((CPU_CLOCK/1000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + PIN_DELAY_SLOW(delay); +} + + +// Process Delay command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Delay(const uint8_t *request, uint8_t *response) { + uint32_t delay; + + delay = (uint32_t)(*(request+0)) | + (uint32_t)(*(request+1) << 8); + delay *= ((CPU_CLOCK/1000000U) + (DELAY_SLOW_CYCLES-1U)) / DELAY_SLOW_CYCLES; + + PIN_DELAY_SLOW(delay); + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Host Status command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_HostStatus(const uint8_t *request, uint8_t *response) { + + switch (*request) { + case DAP_DEBUGGER_CONNECTED: + LED_CONNECTED_OUT((*(request+1) & 1U)); + break; + case DAP_TARGET_RUNNING: + LED_RUNNING_OUT((*(request+1) & 1U)); + break; + default: + *response = DAP_ERROR; + return ((2U << 16) | 1U); + } + + *response = DAP_OK; + return ((2U << 16) | 1U); +} + + +// Process Connect command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Connect(const uint8_t *request, uint8_t *response) { + uint32_t port; + + if (*request == DAP_PORT_AUTODETECT) { + port = DAP_DEFAULT_PORT; + } else { + port = *request; + } + + switch (port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + DAP_Data.debug_port = DAP_PORT_SWD; + PORT_SWD_SETUP(); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + DAP_Data.debug_port = DAP_PORT_JTAG; + PORT_JTAG_SETUP(); + break; +#endif + default: + port = DAP_PORT_DISABLED; + break; + } + + *response = (uint8_t)port; + return ((1U << 16) | 1U); +} + + +// Process Disconnect command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_Disconnect(uint8_t *response) { + + DAP_Data.debug_port = DAP_PORT_DISABLED; + PORT_OFF(); + + *response = DAP_OK; + return (1U); +} + + +// Process Reset Target command and prepare response +// response: pointer to response data +// return: number of bytes in response +static uint32_t DAP_ResetTarget(uint8_t *response) { + + *(response+1) = RESET_TARGET(); + *(response+0) = DAP_OK; + return (2U); +} + + +// Process SWJ Pins command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Pins(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t value; + uint32_t select; + uint32_t wait; + uint32_t timestamp; + + value = (uint32_t) *(request+0); + select = (uint32_t) *(request+1); + wait = (uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8) | + (uint32_t)(*(request+4) << 16) | + (uint32_t)(*(request+5) << 24); + + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + PIN_SWCLK_TCK_SET(); + } else { + PIN_SWCLK_TCK_CLR(); + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + PIN_TDI_OUT(value >> DAP_SWJ_TDI); + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + PIN_nTRST_OUT(value >> DAP_SWJ_nTRST); + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U){ + PIN_nRESET_OUT(value >> DAP_SWJ_nRESET); + } + + if (wait != 0U) { +#if (TIMESTAMP_CLOCK != 0U) + if (wait > 3000000U) { + wait = 3000000U; + } +#if (TIMESTAMP_CLOCK >= 1000000U) + wait *= TIMESTAMP_CLOCK / 1000000U; +#else + wait /= 1000000U / TIMESTAMP_CLOCK; +#endif +#else + wait = 1U; +#endif + timestamp = TIMESTAMP_GET(); + do { + if ((select & (1U << DAP_SWJ_SWCLK_TCK)) != 0U) { + if ((value >> DAP_SWJ_SWCLK_TCK) ^ PIN_SWCLK_TCK_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_SWDIO_TMS)) != 0U) { + if ((value >> DAP_SWJ_SWDIO_TMS) ^ PIN_SWDIO_TMS_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_TDI)) != 0U) { + if ((value >> DAP_SWJ_TDI) ^ PIN_TDI_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nTRST)) != 0U) { + if ((value >> DAP_SWJ_nTRST) ^ PIN_nTRST_IN()) { + continue; + } + } + if ((select & (1U << DAP_SWJ_nRESET)) != 0U) { + if ((value >> DAP_SWJ_nRESET) ^ PIN_nRESET_IN()) { + continue; + } + } + break; + } while ((TIMESTAMP_GET() - timestamp) < wait); + } + + value = (PIN_SWCLK_TCK_IN() << DAP_SWJ_SWCLK_TCK) | + (PIN_SWDIO_TMS_IN() << DAP_SWJ_SWDIO_TMS) | + (PIN_TDI_IN() << DAP_SWJ_TDI) | + (PIN_TDO_IN() << DAP_SWJ_TDO) | + (PIN_nTRST_IN() << DAP_SWJ_nTRST) | + (PIN_nRESET_IN() << DAP_SWJ_nRESET); + + *response = (uint8_t)value; +#else + *response = 0U; +#endif + + return ((6U << 16) | 1U); +} + + +// Process SWJ Clock command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Clock(const uint8_t *request, uint8_t *response) { +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + uint32_t clock; + uint32_t delay; + + clock = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + + if (clock == 0U) { + *response = DAP_ERROR; + return ((4U << 16) | 1U); + } + + Set_Clock_Delay(clock); + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((4U << 16) | 1U); +} + + +// Process SWJ Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWJ_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t count; + + count = *request++; + if (count == 0U) { + count = 256U; + } + +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) + SWJ_Sequence(count, request); + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + count = (count + 7U) >> 3; + + return (((count + 1U) << 16) | 1U); +} + + +// Process SWD Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Configure(const uint8_t *request, uint8_t *response) { +#if (DAP_SWD != 0) + uint8_t value; + + value = *request; + DAP_Data.swd_conf.turnaround = (value & 0x03U) + 1U; + DAP_Data.swd_conf.data_phase = (value & 0x04U) ? 1U : 0U; + + *response = DAP_OK; +#else + *response = DAP_ERROR; +#endif + + return ((1U << 16) | 1U); +} + + +// Process SWD Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_SWD_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_SWD != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & SWD_SEQUENCE_CLK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_SWD != 0) + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + PIN_SWDIO_OUT_DISABLE(); + } else { + PIN_SWDIO_OUT_ENABLE(); + } + SWD_Sequence(sequence_info, request, response); + if (sequence_count == 0U) { + PIN_SWDIO_OUT_ENABLE(); + } +#endif + if ((sequence_info & SWD_SEQUENCE_DIN) != 0U) { + request_count++; +#if (DAP_SWD != 0) + response += count; + response_count += count; +#endif + } else { + request += count; + request_count += count + 1U; + } + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Sequence command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Sequence(const uint8_t *request, uint8_t *response) { + uint32_t sequence_info; + uint32_t sequence_count; + uint32_t request_count; + uint32_t response_count; + uint32_t count; + +#if (DAP_JTAG != 0) + *response++ = DAP_OK; +#else + *response++ = DAP_ERROR; +#endif + request_count = 1U; + response_count = 1U; + + sequence_count = *request++; + while (sequence_count--) { + sequence_info = *request++; + count = sequence_info & JTAG_SEQUENCE_TCK; + if (count == 0U) { + count = 64U; + } + count = (count + 7U) / 8U; +#if (DAP_JTAG != 0) + JTAG_Sequence(sequence_info, request, response); +#endif + request += count; + request_count += count + 1U; +#if (DAP_JTAG != 0) + if ((sequence_info & JTAG_SEQUENCE_TDO) != 0U) { + response += count; + response_count += count; + } +#endif + } + + return ((request_count << 16) | response_count); +} + + +// Process JTAG Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_Configure(const uint8_t *request, uint8_t *response) { + uint32_t count; +#if (DAP_JTAG != 0) + uint32_t length; + uint32_t bits; + uint32_t n; + + count = *request++; + DAP_Data.jtag_dev.count = (uint8_t)count; + + bits = 0U; + for (n = 0U; n < count; n++) { + length = *request++; + DAP_Data.jtag_dev.ir_length[n] = (uint8_t)length; + DAP_Data.jtag_dev.ir_before[n] = (uint16_t)bits; + bits += length; + } + for (n = 0U; n < count; n++) { + bits -= DAP_Data.jtag_dev.ir_length[n]; + DAP_Data.jtag_dev.ir_after[n] = (uint16_t)bits; + } + + *response = DAP_OK; +#else + count = *request; + *response = DAP_ERROR; +#endif + + return (((count + 1U) << 16) | 1U); +} + + +// Process JTAG IDCODE command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_JTAG_IDCode(const uint8_t *request, uint8_t *response) { +#if (DAP_JTAG != 0) + uint32_t data; + + if (DAP_Data.debug_port != DAP_PORT_JTAG) { + goto id_error; + } + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto id_error; + } + + // Select JTAG chain + JTAG_IR(JTAG_IDCODE); + + // Read IDCODE register + data = JTAG_ReadIDCode(); + + // Store Data + *(response+0) = DAP_OK; + *(response+1) = (uint8_t)(data >> 0); + *(response+2) = (uint8_t)(data >> 8); + *(response+3) = (uint8_t)(data >> 16); + *(response+4) = (uint8_t)(data >> 24); + + return ((1U << 16) | 5U); + +id_error: +#endif + *response = DAP_ERROR; + return ((1U << 16) | 1U); +} + + +// Process Transfer Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferConfigure(const uint8_t *request, uint8_t *response) { + + DAP_Data.transfer.idle_cycles = *(request+0); + DAP_Data.transfer.retry_count = (uint16_t) *(request+1) | + (uint16_t)(*(request+2) << 8); + DAP_Data.transfer.match_retry = (uint16_t) *(request+3) | + (uint16_t)(*(request+4) << 8); + + *response = DAP_OK; + return ((5U << 16) | 1U); +} + + +// Process SWD Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t check_write; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + post_read = 0U; + check_write = 0U; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((request_value & (DAP_TRANSFER_APnDP | DAP_TRANSFER_MATCH_VALUE)) == DAP_TRANSFER_APnDP) { + // Read previous AP data and post next AP read + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Read previous AP data + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous AP data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + retry = DAP_Data.transfer.retry_count; + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Read AP register + if (post_read == 0U) { + // Post AP read + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } else { + // Read DP register + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } + } + check_write = 0U; + } else { + // Write register + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + check_write = 1U; + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else if (check_write) { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + uint32_t request_ir; + uint8_t *response_head; + uint32_t response_count; + uint32_t response_value; + uint32_t post_read; + uint32_t match_value; + uint32_t match_retry; + uint32_t retry; + uint32_t data; + uint32_t ir; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t timestamp; +#endif + + request_head = request; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 2; + + DAP_TransferAbort = 0U; + + ir = 0U; + post_read = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + request_value = *request++; + request_ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if (post_read) { + // Read was posted before + retry = DAP_Data.transfer.retry_count; + if ((ir == request_ir) && ((request_value & DAP_TRANSFER_MATCH_VALUE) == 0U)) { + // Read previous data and post next read + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } else { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + post_read = 0U; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); +#if (TIMESTAMP_CLOCK != 0U) + if (post_read) { + // Store Timestamp of next AP read + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } + } +#endif + } + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + match_value = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + match_retry = DAP_Data.transfer.match_retry; + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + do { + // Read register until its value matches or retry counter expires + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + } while (((data & DAP_Data.transfer.match_mask) != match_value) && match_retry-- && !DAP_TransferAbort); + if ((data & DAP_Data.transfer.match_mask) != match_value) { + response_value |= DAP_TRANSFER_MISMATCH; + } + if (response_value != DAP_TRANSFER_OK) { + break; + } + } else { + // Normal read + if (post_read == 0U) { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Post DP/AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + post_read = 1U; + } + } + } else { + // Write register + if (post_read) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + post_read = 0U; + } + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + if ((request_value & DAP_TRANSFER_MATCH_MASK) != 0U) { + // Write match mask + DAP_Data.transfer.match_mask = data; + response_value = DAP_TRANSFER_OK; + } else { + // Select JTAG chain + if (ir != request_ir) { + ir = request_ir; + JTAG_IR(ir); + } + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + break; + } +#if (TIMESTAMP_CLOCK != 0U) + // Store Timestamp + if ((request_value & DAP_TRANSFER_TIMESTAMP) != 0U) { + timestamp = DAP_Data.timestamp; + *response++ = (uint8_t) timestamp; + *response++ = (uint8_t)(timestamp >> 8); + *response++ = (uint8_t)(timestamp >> 16); + *response++ = (uint8_t)(timestamp >> 24); + } +#endif + } + } + response_count++; + if (DAP_TransferAbort) { + break; + } + } + + for (; request_count != 0U; request_count--) { + // Process canceled requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + if (response_value == DAP_TRANSFER_OK) { + // Select JTAG chain + if (ir != JTAG_DPACC) { + ir = JTAG_DPACC; + JTAG_IR(ir); + } + if (post_read) { + // Read previous data + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store previous data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + } else { + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + } + +end: + *(response_head+0) = (uint8_t)response_count; + *(response_head+1) = (uint8_t)response_value; + + return (((uint32_t)(request - request_head) << 16) | (uint32_t)(response - response_head)); +} +#endif + + +// Process Dummy Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Dummy_Transfer(const uint8_t *request, uint8_t *response) { + const + uint8_t *request_head; + uint32_t request_count; + uint32_t request_value; + + request_head = request; + + request++; // Ignore DAP index + + request_count = *request++; + + for (; request_count != 0U; request_count--) { + // Process dummy requests + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register + if ((request_value & DAP_TRANSFER_MATCH_VALUE) != 0U) { + // Read with value match + request += 4; + } + } else { + // Write register + request += 4; + } + } + + *(response+0) = 0U; // Response count + *(response+1) = 0U; // Response value + + return (((uint32_t)(request - request_head) << 16) | 2U); +} + + +// Process Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_Transfer(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_Transfer(request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_Transfer(request, response); + break; +#endif + default: + num = DAP_Dummy_Transfer(request, response); + break; + } + + return (num); +} + + +// Process SWD Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + request++; // Ignore DAP index + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Read register block + if ((request_value & DAP_TRANSFER_APnDP) != 0U) { + // Post AP read + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + } + while (request_count--) { + // Read DP/AP register + if ((request_count == 0U) && ((request_value & DAP_TRANSFER_APnDP) != 0U)) { + // Last AP read + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + retry = DAP_Data.transfer.retry_count; + do { + response_value = SWD_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process JTAG Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t request_count; + uint32_t request_value; + uint32_t response_count; + uint32_t response_value; + uint8_t *response_head; + uint32_t retry; + uint32_t data; + uint32_t ir; + + response_count = 0U; + response_value = 0U; + response_head = response; + response += 3; + + DAP_TransferAbort = 0U; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request++; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + goto end; + } + + request_count = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + request += 2; + if (request_count == 0U) { + goto end; + } + + request_value = *request++; + + // Select JTAG chain + ir = (request_value & DAP_TRANSFER_APnDP) ? JTAG_APACC : JTAG_DPACC; + JTAG_IR(ir); + + if ((request_value & DAP_TRANSFER_RnW) != 0U) { + // Post read + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Read register block + while (request_count--) { + // Read DP/AP register + if (request_count == 0U) { + // Last read + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + request_value = DP_RDBUFF | DAP_TRANSFER_RnW; + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + // Store data + *response++ = (uint8_t) data; + *response++ = (uint8_t)(data >> 8); + *response++ = (uint8_t)(data >> 16); + *response++ = (uint8_t)(data >> 24); + response_count++; + } + } else { + // Write register block + while (request_count--) { + // Load data + data = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + request += 4; + // Write DP/AP register + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(request_value, &data); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + if (response_value != DAP_TRANSFER_OK) { + goto end; + } + response_count++; + } + // Check last write + if (ir != JTAG_DPACC) { + JTAG_IR(JTAG_DPACC); + } + retry = DAP_Data.transfer.retry_count; + do { + response_value = JTAG_Transfer(DP_RDBUFF | DAP_TRANSFER_RnW, NULL); + } while ((response_value == DAP_TRANSFER_WAIT) && retry-- && !DAP_TransferAbort); + } + +end: + *(response_head+0) = (uint8_t)(response_count >> 0); + *(response_head+1) = (uint8_t)(response_count >> 8); + *(response_head+2) = (uint8_t) response_value; + + return ((uint32_t)(response - response_head)); +} +#endif + + +// Process Transfer Block command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_TransferBlock(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_TransferBlock (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_TransferBlock(request, response); + break; +#endif + default: + *(response+0) = 0U; // Response count [7:0] + *(response+1) = 0U; // Response count[15:8] + *(response+2) = 0U; // Response value + num = 3U; + break; + } + + if ((*(request+3) & DAP_TRANSFER_RnW) != 0U) { + // Read register block + num |= 4U << 16; + } else { + // Write register block + num |= (4U + (((uint32_t)(*(request+1)) | (uint32_t)(*(request+2) << 8)) * 4)) << 16; + } + + return (num); +} + + +// Process SWD Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_SWD != 0) +static uint32_t DAP_SWD_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Load data (Ignore DAP index) + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + SWD_Transfer(DP_ABORT, &data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process JTAG Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response +#if (DAP_JTAG != 0) +static uint32_t DAP_JTAG_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t data; + + // Device index (JTAP TAP) + DAP_Data.jtag_dev.index = *request; + if (DAP_Data.jtag_dev.index >= DAP_Data.jtag_dev.count) { + *response = DAP_ERROR; + return (1U); + } + + // Select JTAG chain + JTAG_IR(JTAG_ABORT); + + // Load data + data = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + // Write Abort register + JTAG_WriteAbort(data); + + *response = DAP_OK; + return (1U); +} +#endif + + +// Process Write ABORT command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +static uint32_t DAP_WriteAbort(const uint8_t *request, uint8_t *response) { + uint32_t num; + + switch (DAP_Data.debug_port) { +#if (DAP_SWD != 0) + case DAP_PORT_SWD: + num = DAP_SWD_WriteAbort (request, response); + break; +#endif +#if (DAP_JTAG != 0) + case DAP_PORT_JTAG: + num = DAP_JTAG_WriteAbort(request, response); + break; +#endif + default: + *response = DAP_ERROR; + num = 1U; + break; + } + return ((5U << 16) | num); +} + + +// Process DAP Vendor command request and prepare response +// Default function (can be overridden) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +__WEAK uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + (void)request; + *response = ID_DAP_Invalid; + return ((1U << 16) | 1U); +} + + +// Process DAP command request and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ProcessCommand(const uint8_t *request, uint8_t *response) { + uint32_t num; + + if ((*request >= ID_DAP_Vendor0) && (*request <= ID_DAP_Vendor31)) { + return DAP_ProcessVendorCommand(request, response); + } + + *response++ = *request; + + switch (*request++) { + case ID_DAP_Info: + num = DAP_Info(*request, response+1); + *response = (uint8_t)num; + return ((2U << 16) + 2U + num); + + case ID_DAP_HostStatus: + num = DAP_HostStatus(request, response); + break; + + case ID_DAP_Connect: + num = DAP_Connect(request, response); + break; + case ID_DAP_Disconnect: + num = DAP_Disconnect(response); + break; + + case ID_DAP_Delay: + num = DAP_Delay(request, response); + break; + + case ID_DAP_ResetTarget: + num = DAP_ResetTarget(response); + break; + + case ID_DAP_SWJ_Pins: + num = DAP_SWJ_Pins(request, response); + break; + case ID_DAP_SWJ_Clock: + num = DAP_SWJ_Clock(request, response); + break; + case ID_DAP_SWJ_Sequence: + num = DAP_SWJ_Sequence(request, response); + break; + + case ID_DAP_SWD_Configure: + num = DAP_SWD_Configure(request, response); + break; + case ID_DAP_SWD_Sequence: + num = DAP_SWD_Sequence(request, response); + break; + + case ID_DAP_JTAG_Sequence: + num = DAP_JTAG_Sequence(request, response); + break; + case ID_DAP_JTAG_Configure: + num = DAP_JTAG_Configure(request, response); + break; + case ID_DAP_JTAG_IDCODE: + num = DAP_JTAG_IDCode(request, response); + break; + + case ID_DAP_TransferConfigure: + num = DAP_TransferConfigure(request, response); + break; + case ID_DAP_Transfer: + num = DAP_Transfer(request, response); + break; + case ID_DAP_TransferBlock: + num = DAP_TransferBlock(request, response); + break; + + case ID_DAP_WriteABORT: + num = DAP_WriteAbort(request, response); + break; + +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + case ID_DAP_SWO_Transport: + num = SWO_Transport(request, response); + break; + case ID_DAP_SWO_Mode: + num = SWO_Mode(request, response); + break; + case ID_DAP_SWO_Baudrate: + num = SWO_Baudrate(request, response); + break; + case ID_DAP_SWO_Control: + num = SWO_Control(request, response); + break; + case ID_DAP_SWO_Status: + num = SWO_Status(response); + break; + case ID_DAP_SWO_ExtendedStatus: + num = SWO_ExtendedStatus(request, response); + break; + case ID_DAP_SWO_Data: + num = SWO_Data(request, response); + break; +#endif + +#if (DAP_UART != 0) + case ID_DAP_UART_Transport: + num = UART_Transport(request, response); + break; + case ID_DAP_UART_Configure: + num = UART_Configure(request, response); + break; + case ID_DAP_UART_Control: + num = UART_Control(request, response); + break; + case ID_DAP_UART_Status: + num = UART_Status(response); + break; + case ID_DAP_UART_Transfer: + num = UART_Transfer(request, response); + break; +#endif + + default: + *(response-1) = ID_DAP_Invalid; + return ((1U << 16) | 1U); + } + + return ((1U << 16) + 1U + num); +} + + +// Execute DAP command (process request and prepare response) +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t DAP_ExecuteCommand(const uint8_t *request, uint8_t *response) { + uint32_t cnt, num, n; + + if (*request == ID_DAP_ExecuteCommands) { + *response++ = *request++; + cnt = *request++; + *response++ = (uint8_t)cnt; + num = (2U << 16) | 2U; + while (cnt--) { + n = DAP_ProcessCommand(request, response); + num += n; + request += (uint16_t)(n >> 16); + response += (uint16_t) n; + } + return (num); + } + + return DAP_ProcessCommand(request, response); +} + + +// Setup DAP +void DAP_Setup(void) { + + // Default settings + DAP_Data.debug_port = 0U; + DAP_Data.transfer.idle_cycles = 0U; + DAP_Data.transfer.retry_count = 100U; + DAP_Data.transfer.match_retry = 0U; + DAP_Data.transfer.match_mask = 0x00000000U; +#if (DAP_SWD != 0) + DAP_Data.swd_conf.turnaround = 1U; + DAP_Data.swd_conf.data_phase = 0U; +#endif +#if (DAP_JTAG != 0) + DAP_Data.jtag_dev.count = 0U; +#endif + + // Sets DAP_Data.fast_clock and DAP_Data.clock_delay. + Set_Clock_Delay(DAP_DEFAULT_SWJ_CLOCK); + + DAP_SETUP(); // Device specific setup +} diff --git a/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c b/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c new file mode 100644 index 0000000..4f2477a --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/DAP_vendor.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: DAP_vendor.c CMSIS-DAP Vendor Commands + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + +//************************************************************************************************** +/** +\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands +\ingroup DAP_Vendor_gr +@{ + +The file DAP_vendor.c provides template source code for extension of a Debug Unit with +Vendor Commands. Copy this file to the project folder of the Debug Unit and add the +file to the MDK-ARM project under the file group Configuration. +*/ + +/** Process DAP Vendor Command and prepare Response Data +\param request pointer to request data +\param response pointer to response data +\return number of bytes in response (lower 16 bits) + number of bytes in request (upper 16 bits) +*/ +uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + uint32_t num = (1U << 16) | 1U; + + *response++ = *request; // copy Command ID + + switch (*request++) { // first byte in request is Command ID + case ID_DAP_Vendor0: +#if 0 // example user command + num += 1U << 16; // increment request count + if (*request == 1U) { // when first command data byte is 1 + *response++ = 'X'; // send 'X' as response + num++; // increment response count + } +#endif + break; + + case ID_DAP_Vendor1: break; + case ID_DAP_Vendor2: break; + case ID_DAP_Vendor3: break; + case ID_DAP_Vendor4: break; + case ID_DAP_Vendor5: break; + case ID_DAP_Vendor6: break; + case ID_DAP_Vendor7: break; + case ID_DAP_Vendor8: break; + case ID_DAP_Vendor9: break; + case ID_DAP_Vendor10: break; + case ID_DAP_Vendor11: break; + case ID_DAP_Vendor12: break; + case ID_DAP_Vendor13: break; + case ID_DAP_Vendor14: break; + case ID_DAP_Vendor15: break; + case ID_DAP_Vendor16: break; + case ID_DAP_Vendor17: break; + case ID_DAP_Vendor18: break; + case ID_DAP_Vendor19: break; + case ID_DAP_Vendor20: break; + case ID_DAP_Vendor21: break; + case ID_DAP_Vendor22: break; + case ID_DAP_Vendor23: break; + case ID_DAP_Vendor24: break; + case ID_DAP_Vendor25: break; + case ID_DAP_Vendor26: break; + case ID_DAP_Vendor27: break; + case ID_DAP_Vendor28: break; + case ID_DAP_Vendor29: break; + case ID_DAP_Vendor30: break; + case ID_DAP_Vendor31: break; + } + + return (num); +} + +///@} diff --git a/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c b/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c new file mode 100644 index 0000000..24b1f3f --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/JTAG_DP.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: JTAG_DP.c CMSIS-DAP JTAG DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// JTAG Macros + +#define PIN_TCK_SET PIN_SWCLK_TCK_SET +#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR +#define PIN_TMS_SET PIN_SWDIO_TMS_SET +#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR + +#define JTAG_CYCLE_TCK() \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDI(tdi) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDO(tdo) \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define JTAG_CYCLE_TDIO(tdi,tdo) \ + PIN_TDI_OUT(tdi); \ + PIN_TCK_CLR(); \ + PIN_DELAY(); \ + tdo = PIN_TDO_IN(); \ + PIN_TCK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +#if (DAP_JTAG != 0) + + +// Generate JTAG Sequence +// info: sequence information +// tdi: pointer to TDI generated data +// tdo: pointer to TDO captured data +// return: none +void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) { + uint32_t i_val; + uint32_t o_val; + uint32_t bit; + uint32_t n, k; + + n = info & JTAG_SEQUENCE_TCK; + if (n == 0U) { + n = 64U; + } + + if (info & JTAG_SEQUENCE_TMS) { + PIN_TMS_SET(); + } else { + PIN_TMS_CLR(); + } + + while (n) { + i_val = *tdi++; + o_val = 0U; + for (k = 8U; k && n; k--, n--) { + JTAG_CYCLE_TDIO(i_val, bit); + i_val >>= 1; + o_val >>= 1; + o_val |= bit << 7; + } + o_val >>= k; + if (info & JTAG_SEQUENCE_TDO) { + *tdo++ = (uint8_t)o_val; + } + } +} + + +// JTAG Set IR +// ir: IR value +// return: none +#define JTAG_IR_Function(speed) /**/ \ +static void JTAG_IR_##speed (uint32_t ir) { \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-IR */ \ + JTAG_CYCLE_TCK(); /* Shift-IR */ \ + \ + PIN_TDI_OUT(1U); \ + for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \ + JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \ + ir >>= 1; \ + } \ + n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \ + if (n) { \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \ + PIN_TDI_OUT(1U); \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \ + } \ + \ + JTAG_CYCLE_TCK(); /* Update-IR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define JTAG_TransferFunction(speed) /**/ \ +static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t n; \ + \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Capture-DR */ \ + JTAG_CYCLE_TCK(); /* Shift-DR */ \ + \ + for (n = DAP_Data.jtag_dev.index; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass before data */ \ + } \ + \ + JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \ + ack = bit << 1; \ + JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \ + ack |= bit << 0; \ + JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \ + ack |= bit << 2; \ + \ + if (ack != DAP_TRANSFER_OK) { \ + /* Exit on error */ \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Exit1-DR */ \ + goto exit; \ + } \ + \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read Transfer */ \ + val = 0U; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \ + val |= bit << 31; \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDO(bit); /* Get D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \ + } \ + val |= bit << 31; \ + if (data) { *data = val; } \ + } else { \ + /* Write Transfer */ \ + val = *data; \ + for (n = 31U; n; n--) { \ + JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \ + val >>= 1; \ + } \ + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \ + if (n) { \ + JTAG_CYCLE_TDI(val); /* Set D31 */ \ + for (--n; n; n--) { \ + JTAG_CYCLE_TCK(); /* Bypass after data */ \ + } \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \ + } else { \ + PIN_TMS_SET(); \ + JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \ + } \ + } \ + \ +exit: \ + JTAG_CYCLE_TCK(); /* Update-DR */ \ + PIN_TMS_CLR(); \ + JTAG_CYCLE_TCK(); /* Idle */ \ + PIN_TDI_OUT(1U); \ + \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + while (n--) { \ + JTAG_CYCLE_TCK(); /* Idle */ \ + } \ + \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +JTAG_IR_Function(Fast) +JTAG_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +JTAG_IR_Function(Slow) +JTAG_TransferFunction(Slow) + + +// JTAG Read IDCODE register +// return: value read +uint32_t JTAG_ReadIDCode (void) { + uint32_t bit; + uint32_t val; + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + val = 0U; + for (n = 31U; n; n--) { + JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ + val |= bit << 31; + val >>= 1; + } + PIN_TMS_SET(); + JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ + val |= bit << 31; + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + + return (val); +} + + +// JTAG Write ABORT register +// data: value to write +// return: none +void JTAG_WriteAbort (uint32_t data) { + uint32_t n; + + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Select-DR-Scan */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Capture-DR */ + JTAG_CYCLE_TCK(); /* Shift-DR */ + + for (n = DAP_Data.jtag_dev.index; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass before data */ + } + + PIN_TDI_OUT(0U); + JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */ + JTAG_CYCLE_TCK(); /* Set A2=0 */ + JTAG_CYCLE_TCK(); /* Set A3=0 */ + + for (n = 31U; n; n--) { + JTAG_CYCLE_TDI(data); /* Set D0..D30 */ + data >>= 1; + } + n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; + if (n) { + JTAG_CYCLE_TDI(data); /* Set D31 */ + for (--n; n; n--) { + JTAG_CYCLE_TCK(); /* Bypass after data */ + } + PIN_TMS_SET(); + JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ + } else { + PIN_TMS_SET(); + JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */ + } + + JTAG_CYCLE_TCK(); /* Update-DR */ + PIN_TMS_CLR(); + JTAG_CYCLE_TCK(); /* Idle */ + PIN_TDI_OUT(1U); +} + + +// JTAG Set IR +// ir: IR value +// return: none +void JTAG_IR (uint32_t ir) { + if (DAP_Data.fast_clock) { + JTAG_IR_Fast(ir); + } else { + JTAG_IR_Slow(ir); + } +} + + +// JTAG Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return JTAG_TransferFast(request, data); + } else { + return JTAG_TransferSlow(request, data); + } +} + + +#endif /* (DAP_JTAG != 0) */ diff --git a/Drivers/CMSIS/DAP/Firmware/Source/SWO.c b/Drivers/CMSIS/DAP/Firmware/Source/SWO.c new file mode 100644 index 0000000..4a850cf --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/SWO.c @@ -0,0 +1,798 @@ +/* + * Copyright (c) 2013-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 29. March 2021 + * $Revision: V2.0.1 + * + * Project: CMSIS-DAP Source + * Title: SWO.c CMSIS-DAP SWO I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" +#if (SWO_UART != 0) +#include "Driver_USART.h" +#endif +#if (SWO_STREAM != 0) +#include "cmsis_os2.h" +#define osObjectsExternal +#include "osObjects.h" +#endif + +#if (SWO_STREAM != 0) +#ifdef DAP_FW_V1 +#error "SWO Streaming Trace not supported in DAP V1!" +#endif +#endif + +#if (SWO_UART != 0) + +// USART Driver +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) +extern ARM_DRIVER_USART USART_Driver_(SWO_UART_DRIVER); +#define pUSART (&USART_Driver_(SWO_UART_DRIVER)) + +static uint8_t USART_Ready = 0U; + +#endif /* (SWO_UART != 0) */ + + +#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) + + +#define SWO_STREAM_TIMEOUT 50U /* Stream timeout in ms */ + +#define USB_BLOCK_SIZE 512U /* USB Block Size */ +#define TRACE_BLOCK_SIZE 64U /* Trace Block Size (2^n: 32...512) */ + +// Trace State +static uint8_t TraceTransport = 0U; /* Trace Transport */ +static uint8_t TraceMode = 0U; /* Trace Mode */ +static uint8_t TraceStatus = 0U; /* Trace Status without Errors */ +static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */ +static uint8_t TraceError_n = 0U; /* Active Trace Error bank */ + +// Trace Buffer +static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */ +static volatile uint32_t TraceIndexI = 0U; /* Incoming Trace Index */ +static volatile uint32_t TraceIndexO = 0U; /* Outgoing Trace Index */ +static volatile uint8_t TraceUpdate; /* Trace Update Flag */ +static uint32_t TraceBlockSize; /* Current Trace Block Size */ + +#if (TIMESTAMP_CLOCK != 0U) +// Trace Timestamp +static volatile struct { + uint32_t index; + uint32_t tick; +} TraceTimestamp; +#endif + +// Trace Helper functions +static void ClearTrace (void); +static void ResumeTrace (void); +static uint32_t GetTraceCount (void); +static uint8_t GetTraceStatus (void); +static void SetTraceError (uint8_t flag); + +#if (SWO_STREAM != 0) +extern osThreadId_t SWO_ThreadId; +static volatile uint8_t TransferBusy = 0U; /* Transfer Busy Flag */ +static uint32_t TransferSize; /* Current Transfer Size */ +#endif + + +#if (SWO_UART != 0) + +// USART Driver Callback function +// event: event mask +static void USART_Callback (uint32_t event) { + uint32_t index_i; + uint32_t index_o; + uint32_t count; + uint32_t num; + + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.tick = TIMESTAMP_GET(); +#endif + index_o = TraceIndexO; + index_i = TraceIndexI; + index_i += TraceBlockSize; + TraceIndexI = index_i; +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.index = index_i; +#endif + num = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U)); + count = index_i - index_o; + if (count <= (SWO_BUFFER_SIZE - num)) { + index_i &= SWO_BUFFER_SIZE - 1U; + TraceBlockSize = num; + pUSART->Receive(&TraceBuf[index_i], num); + } else { + TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED; + } + TraceUpdate = 1U; +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) { + osThreadFlagsSet(SWO_ThreadId, 1U); + } + } +#endif + } + if (event & ARM_USART_EVENT_RX_OVERFLOW) { + SetTraceError(DAP_SWO_BUFFER_OVERRUN); + } + if (event & (ARM_USART_EVENT_RX_BREAK | + ARM_USART_EVENT_RX_FRAMING_ERROR | + ARM_USART_EVENT_RX_PARITY_ERROR)) { + SetTraceError(DAP_SWO_STREAM_ERROR); + } +} + +// Enable or disable SWO Mode (UART) +// enable: enable flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Mode_UART (uint32_t enable) { + int32_t status; + + USART_Ready = 0U; + + if (enable != 0U) { + status = pUSART->Initialize(USART_Callback); + if (status != ARM_DRIVER_OK) { + return (0U); + } + status = pUSART->PowerControl(ARM_POWER_FULL); + if (status != ARM_DRIVER_OK) { + pUSART->Uninitialize(); + return (0U); + } + } else { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + pUSART->PowerControl(ARM_POWER_OFF); + pUSART->Uninitialize(); + } + return (1U); +} + +// Configure SWO Baudrate (UART) +// baudrate: requested baudrate +// return: actual baudrate or 0 when not configured +__WEAK uint32_t SWO_Baudrate_UART (uint32_t baudrate) { + int32_t status; + uint32_t index; + uint32_t num; + + if (baudrate > SWO_UART_MAX_BAUDRATE) { + baudrate = SWO_UART_MAX_BAUDRATE; + } + + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + if (pUSART->GetStatus().rx_busy) { + TraceIndexI += pUSART->GetRxCount(); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + } + } + + status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_DATA_BITS_8 | + ARM_USART_PARITY_NONE | + ARM_USART_STOP_BITS_1, + baudrate); + + if (status == ARM_DRIVER_OK) { + USART_Ready = 1U; + } else { + USART_Ready = 0U; + return (0U); + } + + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) { + index = TraceIndexI & (SWO_BUFFER_SIZE - 1U); + num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U)); + TraceBlockSize = num; + pUSART->Receive(&TraceBuf[index], num); + } + pUSART->Control(ARM_USART_CONTROL_RX, 1U); + } + + return (baudrate); +} + +// Control SWO Capture (UART) +// active: active flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Control_UART (uint32_t active) { + int32_t status; + + if (active) { + if (!USART_Ready) { + return (0U); + } + TraceBlockSize = 1U; + status = pUSART->Receive(&TraceBuf[0], 1U); + if (status != ARM_DRIVER_OK) { + return (0U); + } + status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); + if (status != ARM_DRIVER_OK) { + return (0U); + } + } else { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + if (pUSART->GetStatus().rx_busy) { + TraceIndexI += pUSART->GetRxCount(); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + } + } + return (1U); +} + +// Start SWO Capture (UART) +// buf: pointer to buffer for capturing +// num: number of bytes to capture +__WEAK void SWO_Capture_UART (uint8_t *buf, uint32_t num) { + TraceBlockSize = num; + pUSART->Receive(buf, num); +} + +// Get SWO Pending Trace Count (UART) +// return: number of pending trace data bytes +__WEAK uint32_t SWO_GetCount_UART (void) { + uint32_t count; + + if (pUSART->GetStatus().rx_busy) { + count = pUSART->GetRxCount(); + } else { + count = 0U; + } + return (count); +} + +#endif /* (SWO_UART != 0) */ + + +#if (SWO_MANCHESTER != 0) + +// Enable or disable SWO Mode (Manchester) +// enable: enable flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Mode_Manchester (uint32_t enable) { + return (0U); +} + +// Configure SWO Baudrate (Manchester) +// baudrate: requested baudrate +// return: actual baudrate or 0 when not configured +__WEAK uint32_t SWO_Baudrate_Manchester (uint32_t baudrate) { + return (0U); +} + +// Control SWO Capture (Manchester) +// active: active flag +// return: 1 - Success, 0 - Error +__WEAK uint32_t SWO_Control_Manchester (uint32_t active) { + return (0U); +} + +// Start SWO Capture (Manchester) +// buf: pointer to buffer for capturing +// num: number of bytes to capture +__WEAK void SWO_Capture_Manchester (uint8_t *buf, uint32_t num) { +} + +// Get SWO Pending Trace Count (Manchester) +// return: number of pending trace data bytes +__WEAK uint32_t SWO_GetCount_Manchester (void) { +} + +#endif /* (SWO_MANCHESTER != 0) */ + + +// Clear Trace Errors and Data +static void ClearTrace (void) { + +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + if (TransferBusy != 0U) { + SWO_AbortTransfer(); + TransferBusy = 0U; + } + } +#endif + + TraceError[0] = 0U; + TraceError[1] = 0U; + TraceError_n = 0U; + TraceIndexI = 0U; + TraceIndexO = 0U; + +#if (TIMESTAMP_CLOCK != 0U) + TraceTimestamp.index = 0U; + TraceTimestamp.tick = 0U; +#endif +} + +// Resume Trace Capture +static void ResumeTrace (void) { + uint32_t index_i; + uint32_t index_o; + + if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) { + index_i = TraceIndexI; + index_o = TraceIndexO; + if ((index_i - index_o) < SWO_BUFFER_SIZE) { + index_i &= SWO_BUFFER_SIZE - 1U; + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + TraceStatus = DAP_SWO_CAPTURE_ACTIVE; + SWO_Capture_UART(&TraceBuf[index_i], 1U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + TraceStatus = DAP_SWO_CAPTURE_ACTIVE; + SWO_Capture_Manchester(&TraceBuf[index_i], 1U); + break; +#endif + default: + break; + } + } + } +} + +// Get Trace Count +// return: number of available data bytes in trace buffer +static uint32_t GetTraceCount (void) { + uint32_t count; + + if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) { + do { + TraceUpdate = 0U; + count = TraceIndexI - TraceIndexO; + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + count += SWO_GetCount_UART(); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + count += SWO_GetCount_Manchester(); + break; +#endif + default: + break; + } + } while (TraceUpdate != 0U); + } else { + count = TraceIndexI - TraceIndexO; + } + + return (count); +} + +// Get Trace Status (clear Error flags) +// return: Trace Status (Active flag and Error flags) +static uint8_t GetTraceStatus (void) { + uint8_t status; + uint32_t n; + + n = TraceError_n; + TraceError_n ^= 1U; + status = TraceStatus | TraceError[n]; + TraceError[n] = 0U; + + return (status); +} + +// Set Trace Error flag(s) +// flag: error flag(s) to set +static void SetTraceError (uint8_t flag) { + TraceError[TraceError_n] |= flag; +} + + +// Process SWO Transport command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) { + uint8_t transport; + uint32_t result; + + if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) { + transport = *request; + switch (transport) { + case 0U: + case 1U: +#if (SWO_STREAM != 0) + case 2U: +#endif + TraceTransport = transport; + result = 1U; + break; + default: + result = 0U; + break; + } + } else { + result = 0U; + } + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Mode command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) { + uint8_t mode; + uint32_t result; + + mode = *request; + + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + SWO_Mode_UART(0U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + SWO_Mode_Manchester(0U); + break; +#endif + default: + break; + } + + switch (mode) { + case DAP_SWO_OFF: + result = 1U; + break; +#if (SWO_UART != 0) + case DAP_SWO_UART: + result = SWO_Mode_UART(1U); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + result = SWO_Mode_Manchester(1U); + break; +#endif + default: + result = 0U; + break; + } + if (result != 0U) { + TraceMode = mode; + } else { + TraceMode = DAP_SWO_OFF; + } + + TraceStatus = 0U; + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Baudrate command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) { + uint32_t baudrate; + + baudrate = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8) | + (uint32_t)(*(request+2) << 16) | + (uint32_t)(*(request+3) << 24); + + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + baudrate = SWO_Baudrate_UART(baudrate); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + baudrate = SWO_Baudrate_Manchester(baudrate); + break; +#endif + default: + baudrate = 0U; + break; + } + + if (baudrate == 0U) { + TraceStatus = 0U; + } + + *response++ = (uint8_t)(baudrate >> 0); + *response++ = (uint8_t)(baudrate >> 8); + *response++ = (uint8_t)(baudrate >> 16); + *response = (uint8_t)(baudrate >> 24); + + return ((4U << 16) | 4U); +} + + +// Process SWO Control command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Control (const uint8_t *request, uint8_t *response) { + uint8_t active; + uint32_t result; + + active = *request & DAP_SWO_CAPTURE_ACTIVE; + + if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) { + if (active) { + ClearTrace(); + } + switch (TraceMode) { +#if (SWO_UART != 0) + case DAP_SWO_UART: + result = SWO_Control_UART(active); + break; +#endif +#if (SWO_MANCHESTER != 0) + case DAP_SWO_MANCHESTER: + result = SWO_Control_Manchester(active); + break; +#endif + default: + result = 0U; + break; + } + if (result != 0U) { + TraceStatus = active; +#if (SWO_STREAM != 0) + if (TraceTransport == 2U) { + osThreadFlagsSet(SWO_ThreadId, 1U); + } +#endif + } + } else { + result = 1U; + } + + if (result != 0U) { + *response = DAP_OK; + } else { + *response = DAP_ERROR; + } + + return ((1U << 16) | 1U); +} + + +// Process SWO Status command and prepare response +// response: pointer to response data +// return: number of bytes in response +uint32_t SWO_Status (uint8_t *response) { + uint8_t status; + uint32_t count; + + status = GetTraceStatus(); + count = GetTraceCount(); + + *response++ = status; + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + *response++ = (uint8_t)(count >> 16); + *response = (uint8_t)(count >> 24); + + return (5U); +} + + +// Process SWO Extended Status command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) { + uint8_t cmd; + uint8_t status; + uint32_t count; +#if (TIMESTAMP_CLOCK != 0U) + uint32_t index; + uint32_t tick; +#endif + uint32_t num; + + num = 0U; + cmd = *request; + + if (cmd & 0x01U) { + status = GetTraceStatus(); + *response++ = status; + num += 1U; + } + + if (cmd & 0x02U) { + count = GetTraceCount(); + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + *response++ = (uint8_t)(count >> 16); + *response++ = (uint8_t)(count >> 24); + num += 4U; + } + +#if (TIMESTAMP_CLOCK != 0U) + if (cmd & 0x04U) { + do { + TraceUpdate = 0U; + index = TraceTimestamp.index; + tick = TraceTimestamp.tick; + } while (TraceUpdate != 0U); + *response++ = (uint8_t)(index >> 0); + *response++ = (uint8_t)(index >> 8); + *response++ = (uint8_t)(index >> 16); + *response++ = (uint8_t)(index >> 24); + *response++ = (uint8_t)(tick >> 0); + *response++ = (uint8_t)(tick >> 8); + *response++ = (uint8_t)(tick >> 16); + *response++ = (uint8_t)(tick >> 24); + num += 4U; + } +#endif + + return ((1U << 16) | num); +} + + +// Process SWO Data command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t SWO_Data (const uint8_t *request, uint8_t *response) { + uint8_t status; + uint32_t count; + uint32_t index; + uint32_t n, i; + + status = GetTraceStatus(); + count = GetTraceCount(); + + if (TraceTransport == 1U) { + n = (uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8); + if (n > (DAP_PACKET_SIZE - 4U)) { + n = DAP_PACKET_SIZE - 4U; + } + if (count > n) { + count = n; + } + } else { + count = 0U; + } + + *response++ = status; + *response++ = (uint8_t)(count >> 0); + *response++ = (uint8_t)(count >> 8); + + if (TraceTransport == 1U) { + index = TraceIndexO; + for (i = index, n = count; n; n--) { + i &= SWO_BUFFER_SIZE - 1U; + *response++ = TraceBuf[i++]; + } + TraceIndexO = index + count; + ResumeTrace(); + } + + return ((2U << 16) | (3U + count)); +} + + +#if (SWO_STREAM != 0) + +// SWO Data Transfer complete callback +void SWO_TransferComplete (void) { + TraceIndexO += TransferSize; + TransferBusy = 0U; + ResumeTrace(); + osThreadFlagsSet(SWO_ThreadId, 1U); +} + +// SWO Thread +__NO_RETURN void SWO_Thread (void *argument) { + uint32_t timeout; + uint32_t flags; + uint32_t count; + uint32_t index; + uint32_t i, n; + (void) argument; + + timeout = osWaitForever; + + for (;;) { + flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout); + if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) { + timeout = SWO_STREAM_TIMEOUT; + } else { + timeout = osWaitForever; + flags = osFlagsErrorTimeout; + } + if (TransferBusy == 0U) { + count = GetTraceCount(); + if (count != 0U) { + index = TraceIndexO & (SWO_BUFFER_SIZE - 1U); + n = SWO_BUFFER_SIZE - index; + if (count > n) { + count = n; + } + if (flags != osFlagsErrorTimeout) { + i = index & (USB_BLOCK_SIZE - 1U); + if (i == 0U) { + count &= ~(USB_BLOCK_SIZE - 1U); + } else { + n = USB_BLOCK_SIZE - i; + if (count >= n) { + count = n; + } else { + count = 0U; + } + } + } + if (count != 0U) { + TransferSize = count; + TransferBusy = 1U; + SWO_QueueTransfer(&TraceBuf[index], count); + } + } + } + } +} + +#endif /* (SWO_STREAM != 0) */ + + +#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */ diff --git a/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c b/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c new file mode 100644 index 0000000..803cf42 --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/SW_DP.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. December 2017 + * $Revision: V2.0.0 + * + * Project: CMSIS-DAP Source + * Title: SW_DP.c CMSIS-DAP SW DP I/O + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + + +// SW Macros + +#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET +#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR + +#define SW_CLOCK_CYCLE() \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_WRITE_BIT(bit) \ + PIN_SWDIO_OUT(bit); \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define SW_READ_BIT(bit) \ + PIN_SWCLK_CLR(); \ + PIN_DELAY(); \ + bit = PIN_SWDIO_IN(); \ + PIN_SWCLK_SET(); \ + PIN_DELAY() + +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) + + +// Generate SWJ Sequence +// count: sequence bit count +// data: pointer to sequence bit data +// return: none +#if ((DAP_SWD != 0) || (DAP_JTAG != 0)) +void SWJ_Sequence (uint32_t count, const uint8_t *data) { + uint32_t val; + uint32_t n; + + val = 0U; + n = 0U; + while (count--) { + if (n == 0U) { + val = *data++; + n = 8U; + } + if (val & 1U) { + PIN_SWDIO_TMS_SET(); + } else { + PIN_SWDIO_TMS_CLR(); + } + SW_CLOCK_CYCLE(); + val >>= 1; + n--; + } +} +#endif + + +// Generate SWD Sequence +// info: sequence information +// swdo: pointer to SWDIO generated data +// swdi: pointer to SWDIO captured data +// return: none +#if (DAP_SWD != 0) +void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) { + uint32_t val; + uint32_t bit; + uint32_t n, k; + + n = info & SWD_SEQUENCE_CLK; + if (n == 0U) { + n = 64U; + } + + if (info & SWD_SEQUENCE_DIN) { + while (n) { + val = 0U; + for (k = 8U; k && n; k--, n--) { + SW_READ_BIT(bit); + val >>= 1; + val |= bit << 7; + } + val >>= k; + *swdi++ = (uint8_t)val; + } + } else { + while (n) { + val = *swdo++; + for (k = 8U; k && n; k--, n--) { + SW_WRITE_BIT(val); + val >>= 1; + } + } + } +} +#endif + + +#if (DAP_SWD != 0) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +#define SWD_TransferFunction(speed) /**/ \ +static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \ + uint32_t ack; \ + uint32_t bit; \ + uint32_t val; \ + uint32_t parity; \ + \ + uint32_t n; \ + \ + /* Packet Request */ \ + parity = 0U; \ + SW_WRITE_BIT(1U); /* Start Bit */ \ + bit = request >> 0; \ + SW_WRITE_BIT(bit); /* APnDP Bit */ \ + parity += bit; \ + bit = request >> 1; \ + SW_WRITE_BIT(bit); /* RnW Bit */ \ + parity += bit; \ + bit = request >> 2; \ + SW_WRITE_BIT(bit); /* A2 Bit */ \ + parity += bit; \ + bit = request >> 3; \ + SW_WRITE_BIT(bit); /* A3 Bit */ \ + parity += bit; \ + SW_WRITE_BIT(parity); /* Parity Bit */ \ + SW_WRITE_BIT(0U); /* Stop Bit */ \ + SW_WRITE_BIT(1U); /* Park Bit */ \ + \ + /* Turnaround */ \ + PIN_SWDIO_OUT_DISABLE(); \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + \ + /* Acknowledge response */ \ + SW_READ_BIT(bit); \ + ack = bit << 0; \ + SW_READ_BIT(bit); \ + ack |= bit << 1; \ + SW_READ_BIT(bit); \ + ack |= bit << 2; \ + \ + if (ack == DAP_TRANSFER_OK) { /* OK response */ \ + /* Data transfer */ \ + if (request & DAP_TRANSFER_RnW) { \ + /* Read data */ \ + val = 0U; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_READ_BIT(bit); /* Read RDATA[0:31] */ \ + parity += bit; \ + val >>= 1; \ + val |= bit << 31; \ + } \ + SW_READ_BIT(bit); /* Read Parity */ \ + if ((parity ^ bit) & 1U) { \ + ack = DAP_TRANSFER_ERROR; \ + } \ + if (data) { *data = val; } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + } else { \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + /* Write data */ \ + val = *data; \ + parity = 0U; \ + for (n = 32U; n; n--) { \ + SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \ + parity += val; \ + val >>= 1; \ + } \ + SW_WRITE_BIT(parity); /* Write Parity Bit */ \ + } \ + /* Capture Timestamp */ \ + if (request & DAP_TRANSFER_TIMESTAMP) { \ + DAP_Data.timestamp = TIMESTAMP_GET(); \ + } \ + /* Idle cycles */ \ + n = DAP_Data.transfer.idle_cycles; \ + if (n) { \ + PIN_SWDIO_OUT(0U); \ + for (; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \ + /* WAIT or FAULT response */ \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \ + } \ + } \ + /* Turnaround */ \ + for (n = DAP_Data.swd_conf.turnaround; n; n--) { \ + SW_CLOCK_CYCLE(); \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \ + PIN_SWDIO_OUT(0U); \ + for (n = 32U+1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \ + } \ + } \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ + } \ + \ + /* Protocol error */ \ + for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \ + SW_CLOCK_CYCLE(); /* Back off data phase */ \ + } \ + PIN_SWDIO_OUT_ENABLE(); \ + PIN_SWDIO_OUT(1U); \ + return ((uint8_t)ack); \ +} + + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_FAST() +SWD_TransferFunction(Fast) + +#undef PIN_DELAY +#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay) +SWD_TransferFunction(Slow) + + +// SWD Transfer I/O +// request: A[3:2] RnW APnDP +// data: DATA[31:0] +// return: ACK[2:0] +uint8_t SWD_Transfer(uint32_t request, uint32_t *data) { + if (DAP_Data.fast_clock) { + return SWD_TransferFast(request, data); + } else { + return SWD_TransferSlow(request, data); + } +} + + +#endif /* (DAP_SWD != 0) */ diff --git a/Drivers/CMSIS/DAP/Firmware/Source/UART.c b/Drivers/CMSIS/DAP/Firmware/Source/UART.c new file mode 100644 index 0000000..8e9eae5 --- /dev/null +++ b/Drivers/CMSIS/DAP/Firmware/Source/UART.c @@ -0,0 +1,652 @@ +/* + * Copyright (c) 2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 1. March 2021 + * $Revision: V1.0.0 + * + * Project: CMSIS-DAP Source + * Title: UART.c CMSIS-DAP UART + * + *---------------------------------------------------------------------------*/ + +#include "DAP_config.h" +#include "DAP.h" + +#if (DAP_UART != 0) + +#ifdef DAP_FW_V1 +#error "UART Communication Port not supported in DAP V1!" +#endif + +#include "Driver_USART.h" + +#include "cmsis_os2.h" +#include + +#define UART_RX_BLOCK_SIZE 32U /* Uart Rx Block Size (must be 2^n) */ + +// USART Driver +#define _USART_Driver_(n) Driver_USART##n +#define USART_Driver_(n) _USART_Driver_(n) +extern ARM_DRIVER_USART USART_Driver_(DAP_UART_DRIVER); +#define pUSART (&USART_Driver_(DAP_UART_DRIVER)) + +// UART Configuration +#if (DAP_UART_USB_COM_PORT != 0) +static uint8_t UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; +#else +static uint8_t UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + +// UART Flags +static uint8_t UartConfigured = 0U; +static uint8_t UartReceiveEnabled = 0U; +static uint8_t UartTransmitEnabled = 0U; +static uint8_t UartTransmitActive = 0U; + +// UART TX Buffer +static uint8_t UartTxBuf[DAP_UART_TX_BUFFER_SIZE]; +static volatile uint32_t UartTxIndexI = 0U; +static volatile uint32_t UartTxIndexO = 0U; + +// UART RX Buffer +static uint8_t UartRxBuf[DAP_UART_RX_BUFFER_SIZE]; +static volatile uint32_t UartRxIndexI = 0U; +static volatile uint32_t UartRxIndexO = 0U; + +// Uart Errors +static volatile uint8_t UartErrorRxDataLost = 0U; +static volatile uint8_t UartErrorFraming = 0U; +static volatile uint8_t UartErrorParity = 0U; + +// UART Transmit +static uint32_t UartTxNum = 0U; + +// Function prototypes +static uint8_t UART_Init (void); +static void UART_Uninit (void); +static uint8_t UART_Get_Status (void); +static uint8_t UART_Receive_Enable (void); +static uint8_t UART_Transmit_Enable (void); +static void UART_Receive_Disable (void); +static void UART_Transmit_Disable (void); +static void UART_Receive_Flush (void); +static void UART_Transmit_Flush (void); +static void UART_Receive (void); +static void UART_Transmit (void); + + +// USART Driver Callback function +// event: event mask +static void USART_Callback (uint32_t event) { + if (event & ARM_USART_EVENT_SEND_COMPLETE) { + UartTxIndexO += UartTxNum; + UartTransmitActive = 0U; + UART_Transmit(); + } + if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) { + UartRxIndexI += UART_RX_BLOCK_SIZE; + UART_Receive(); + } + if (event & ARM_USART_EVENT_RX_OVERFLOW) { + UartErrorRxDataLost = 1U; + } + if (event & ARM_USART_EVENT_RX_FRAMING_ERROR) { + UartErrorFraming = 1U; + } + if (event & ARM_USART_EVENT_RX_PARITY_ERROR) { + UartErrorParity = 1U; + } +} + +// Init UART +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Init (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + UartConfigured = 0U; + UartReceiveEnabled = 0U; + UartTransmitEnabled = 0U; + UartTransmitActive = 0U; + UartErrorRxDataLost = 0U; + UartErrorFraming = 0U; + UartErrorParity = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartRxIndexI = 0U; + UartRxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Initialize(USART_Callback); + if (status == ARM_DRIVER_OK) { + status = pUSART->PowerControl(ARM_POWER_FULL); + } + if (status == ARM_DRIVER_OK) { + ret = DAP_OK; + } + + return (ret); +} + +// Un-Init UART +static void UART_Uninit (void) { + UartConfigured = 0U; + + pUSART->PowerControl(ARM_POWER_OFF); + pUSART->Uninitialize(); +} + +// Get UART Status +// return: status +static uint8_t UART_Get_Status (void) { + uint8_t status = 0U; + + if (UartReceiveEnabled != 0U) { + status |= DAP_UART_STATUS_RX_ENABLED; + } + if (UartErrorRxDataLost != 0U) { + UartErrorRxDataLost = 0U; + status |= DAP_UART_STATUS_RX_DATA_LOST; + } + if (UartErrorFraming != 0U) { + UartErrorFraming = 0U; + status |= DAP_UART_STATUS_FRAMING_ERROR; + } + if (UartErrorParity != 0U) { + UartErrorParity = 0U; + status |= DAP_UART_STATUS_PARITY_ERROR; + } + if (UartTransmitEnabled != 0U) { + status |= DAP_UART_STATUS_TX_ENABLED; + } + + return (status); +} + +// Enable UART Receive +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Receive_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartReceiveEnabled == 0U) { + // Flush Buffers + UartRxIndexI = 0U; + UartRxIndexO = 0U; + + UART_Receive(); + status = pUSART->Control(ARM_USART_CONTROL_RX, 1U); + if (status == ARM_DRIVER_OK) { + UartReceiveEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Enable UART Transmit +// return: DAP_OK or DAP_ERROR +static uint8_t UART_Transmit_Enable (void) { + int32_t status; + uint8_t ret = DAP_ERROR; + + if (UartTransmitEnabled == 0U) { + // Flush Buffers + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; + + status = pUSART->Control(ARM_USART_CONTROL_TX, 1U); + if (status == ARM_DRIVER_OK) { + UartTransmitEnabled = 1U; + ret = DAP_OK; + } + } else { + ret = DAP_OK; + } + + return (ret); +} + +// Disable UART Receive +static void UART_Receive_Disable (void) { + if (UartReceiveEnabled != 0U) { + pUSART->Control(ARM_USART_CONTROL_RX, 0U); + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartReceiveEnabled = 0U; + } +} + +// Disable UART Transmit +static void UART_Transmit_Disable (void) { + if (UartTransmitEnabled != 0U) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + pUSART->Control(ARM_USART_CONTROL_TX, 0U); + UartTransmitActive = 0U; + UartTransmitEnabled = 0U; + } +} + +// Flush UART Receive buffer +static void UART_Receive_Flush (void) { + pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U); + UartRxIndexI = 0U; + UartRxIndexO = 0U; + if (UartReceiveEnabled != 0U) { + UART_Receive(); + } +} + +// Flush UART Transmit buffer +static void UART_Transmit_Flush (void) { + pUSART->Control(ARM_USART_ABORT_SEND, 0U); + UartTransmitActive = 0U; + UartTxIndexI = 0U; + UartTxIndexO = 0U; + UartTxNum = 0U; +} + +// Receive data from target via UART +static void UART_Receive (void) { + uint32_t index; + + index = UartRxIndexI & (DAP_UART_RX_BUFFER_SIZE - 1U); + pUSART->Receive(&UartRxBuf[index], UART_RX_BLOCK_SIZE); +} + +// Transmit available data to target via UART +static void UART_Transmit (void) { + uint32_t count; + uint32_t index; + + count = UartTxIndexI - UartTxIndexO; + index = UartTxIndexO & (DAP_UART_TX_BUFFER_SIZE - 1U); + + if (count != 0U) { + if ((index + count) <= DAP_UART_TX_BUFFER_SIZE) { + UartTxNum = count; + } else { + UartTxNum = DAP_UART_TX_BUFFER_SIZE - index; + } + UartTransmitActive = 1U; + pUSART->Send(&UartTxBuf[index], UartTxNum); + } +} + +// Process UART Transport command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transport (const uint8_t *request, uint8_t *response) { + uint8_t transport; + uint8_t ret = DAP_ERROR; + + transport = *request; + switch (transport) { + case DAP_UART_TRANSPORT_NONE: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret = DAP_OK; +#endif + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; + ret= DAP_OK; + break; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: + ret = DAP_OK; + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + UART_Receive_Disable(); + UART_Transmit_Disable(); + UART_Uninit(); + UartTransport = DAP_UART_TRANSPORT_NONE; +#if (DAP_UART_USB_COM_PORT != 0) + if (USB_COM_PORT_Activate(1U) == 0U) { + UartTransport = DAP_UART_TRANSPORT_USB_COM_PORT; + ret = DAP_OK; + } +#endif + break; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + switch (UartTransport) { + case DAP_UART_TRANSPORT_NONE: + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_USB_COM_PORT: +#if (DAP_UART_USB_COM_PORT != 0) + USB_COM_PORT_Activate(0U); + UartTransport = DAP_UART_TRANSPORT_NONE; +#endif + ret = UART_Init(); + if (ret == DAP_OK) { + UartTransport = DAP_UART_TRANSPORT_DAP_COMMAND; + } + break; + case DAP_UART_TRANSPORT_DAP_COMMAND: + ret = DAP_OK; + break; + } + break; + default: + break; + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Configure command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Configure (const uint8_t *request, uint8_t *response) { + uint8_t control, status; + uint32_t baudrate; + int32_t result; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; // baudrate error + } else { + + status = 0U; + control = *request; + baudrate = (uint32_t)(*(request+1) << 0) | + (uint32_t)(*(request+2) << 8) | + (uint32_t)(*(request+3) << 16) | + (uint32_t)(*(request+4) << 24); + + result = pUSART->Control(control | + ARM_USART_MODE_ASYNCHRONOUS | + ARM_USART_FLOW_CONTROL_NONE, + baudrate); + if (result == ARM_DRIVER_OK) { + UartConfigured = 1U; + } else { + UartConfigured = 0U; + switch (result) { + case ARM_USART_ERROR_BAUDRATE: + status = 0U; + baudrate = 0U; + break; + case ARM_USART_ERROR_DATA_BITS: + status = DAP_UART_CFG_ERROR_DATA_BITS; + break; + case ARM_USART_ERROR_PARITY: + status = DAP_UART_CFG_ERROR_PARITY; + break; + case ARM_USART_ERROR_STOP_BITS: + status = DAP_UART_CFG_ERROR_STOP_BITS; + break; + default: + status = DAP_UART_CFG_ERROR_DATA_BITS | + DAP_UART_CFG_ERROR_PARITY | + DAP_UART_CFG_ERROR_STOP_BITS; + baudrate = 0U; + break; + } + } + } + + *response++ = status; + *response++ = (uint8_t)(baudrate >> 0); + *response++ = (uint8_t)(baudrate >> 8); + *response++ = (uint8_t)(baudrate >> 16); + *response = (uint8_t)(baudrate >> 24); + + return ((5U << 16) | 5U); +} + +// Process UART Control command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Control (const uint8_t *request, uint8_t *response) { + uint8_t control; + uint8_t result; + uint8_t ret = DAP_OK; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + ret = DAP_ERROR; + } else { + + control = *request; + + if ((control & DAP_UART_CONTROL_RX_DISABLE) != 0U) { + // Receive disable + UART_Receive_Disable(); + } else if ((control & DAP_UART_CONTROL_RX_ENABLE) != 0U) { + // Receive enable + if (UartConfigured != 0U) { + result = UART_Receive_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_RX_BUF_FLUSH) != 0U) { + UART_Receive_Flush(); + } + + if ((control & DAP_UART_CONTROL_TX_DISABLE) != 0U) { + // Transmit disable + UART_Transmit_Disable(); + } else if ((control & DAP_UART_CONTROL_TX_ENABLE) != 0U) { + // Transmit enable + if (UartConfigured != 0U) { + result = UART_Transmit_Enable(); + if (result != DAP_OK) { + ret = DAP_ERROR; + } + } else { + ret = DAP_ERROR; + } + } + if ((control & DAP_UART_CONTROL_TX_BUF_FLUSH) != 0U) { + UART_Transmit_Flush(); + } + } + + *response = ret; + + return ((1U << 16) | 1U); +} + +// Process UART Status command and prepare response +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Status (uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t cnt; + uint8_t status; + + if ((UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) || + (UartConfigured == 0U)) { + rx_cnt = 0U; + tx_cnt = 0U; + status = 0U; + } else { + + rx_cnt = UartRxIndexI - UartRxIndexO; + rx_cnt += pUSART->GetRxCount(); + if (rx_cnt > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_cnt = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_cnt; + } + + tx_cnt = UartTxIndexI - UartTxIndexO; + cnt = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_cnt -= cnt; + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(rx_cnt >> 0); + *response++ = (uint8_t)(rx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 16); + *response++ = (uint8_t)(rx_cnt >> 24); + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(tx_cnt >> 16); + *response = (uint8_t)(tx_cnt >> 24); + + return ((0U << 16) | 9U); +} + +// Process UART Transfer command and prepare response +// request: pointer to request data +// response: pointer to response data +// return: number of bytes in response (lower 16 bits) +// number of bytes in request (upper 16 bits) +uint32_t UART_Transfer (const uint8_t *request, uint8_t *response) { + uint32_t rx_cnt, tx_cnt; + uint32_t rx_num, tx_num; + uint8_t *rx_data; + const + uint8_t *tx_data; + uint32_t num; + uint32_t index; + uint8_t status; + + if (UartTransport != DAP_UART_TRANSPORT_DAP_COMMAND) { + status = 0U; + rx_cnt = 0U; + tx_cnt = 0U; + } else { + + // RX Data + rx_cnt = ((uint32_t)(*(request+0) << 0) | + (uint32_t)(*(request+1) << 8)); + + if (rx_cnt > (DAP_PACKET_SIZE - 6U)) { + rx_cnt = (DAP_PACKET_SIZE - 6U); + } + rx_num = UartRxIndexI - UartRxIndexO; + rx_num += pUSART->GetRxCount(); + if (rx_num > (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2))) { + // Overflow + UartErrorRxDataLost = 1U; + rx_num = (DAP_UART_RX_BUFFER_SIZE - (UART_RX_BLOCK_SIZE*2)); + UartRxIndexO = UartRxIndexI - rx_num; + } + if (rx_cnt > rx_num) { + rx_cnt = rx_num; + } + + rx_data = (response+5); + index = UartRxIndexO & (DAP_UART_RX_BUFFER_SIZE - 1U); + if ((index + rx_cnt) <= DAP_UART_RX_BUFFER_SIZE) { + memcpy( rx_data, &UartRxBuf[index], rx_cnt); + } else { + num = DAP_UART_RX_BUFFER_SIZE - index; + memcpy( rx_data, &UartRxBuf[index], num); + memcpy(&rx_data[num], &UartRxBuf[0], rx_cnt - num); + } + UartRxIndexO += rx_cnt; + + // TX Data + tx_cnt = ((uint32_t)(*(request+2) << 0) | + (uint32_t)(*(request+3) << 8)); + tx_data = (request+4); + + if (tx_cnt > (DAP_PACKET_SIZE - 5U)) { + tx_cnt = (DAP_PACKET_SIZE - 5U); + } + tx_num = UartTxIndexI - UartTxIndexO; + num = pUSART->GetTxCount(); + if (UartTransmitActive != 0U) { + tx_num -= num; + } + if (tx_cnt > (DAP_UART_TX_BUFFER_SIZE - tx_num)) { + tx_cnt = (DAP_UART_TX_BUFFER_SIZE - tx_num); + } + + index = UartTxIndexI & (DAP_UART_TX_BUFFER_SIZE - 1U); + if ((index + tx_cnt) <= DAP_UART_TX_BUFFER_SIZE) { + memcpy(&UartTxBuf[index], tx_data, tx_cnt); + } else { + num = DAP_UART_TX_BUFFER_SIZE - index; + memcpy(&UartTxBuf[index], tx_data, num); + memcpy(&UartTxBuf[0], &tx_data[num], tx_cnt - num); + } + UartTxIndexI += tx_cnt; + + if (UartTransmitActive == 0U) { + UART_Transmit(); + } + + status = UART_Get_Status(); + } + + *response++ = status; + *response++ = (uint8_t)(tx_cnt >> 0); + *response++ = (uint8_t)(tx_cnt >> 8); + *response++ = (uint8_t)(rx_cnt >> 0); + *response = (uint8_t)(rx_cnt >> 8); + + return (((4U + tx_cnt) << 16) | (5U + rx_cnt)); +} + +#endif /* DAP_UART */ diff --git a/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h b/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h new file mode 100644 index 0000000..29838bd --- /dev/null +++ b/Drivers/CMSIS/DSP/ComputeLibrary/Include/NEMath.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2016, 2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef __ARM_COMPUTE_NEMATH_H__ +#define __ARM_COMPUTE_NEMATH_H__ + + +#if defined(ARM_MATH_NEON) +/** Calculate floor of a vector. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated floor vector. + */ +static inline float32x4_t vfloorq_f32(float32x4_t val); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float32x2_t vinvsqrt_f32(float32x2_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float32x4_t vinvsqrtq_f32(float32x4_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float32x2_t vinv_f32(float32x2_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float32x4_t vinvq_f32(float32x4_t x); + +/** Perform a 7th degree polynomial approximation using Estrin's method. + * + * @param[in] x Input vector value in F32 format. + * @param[in] coeffs Polynomial coefficients table. (array of flattened float32x4_t vectors) + * + * @return The calculated approximation. + */ +static inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs); + +/** Calculate exponential + * + * @param[in] x Input vector value in F32 format. + * + * @return The calculated exponent. + */ +static inline float32x4_t vexpq_f32(float32x4_t x); + +/** Calculate logarithm + * + * @param[in] x Input vector value in F32 format. + * + * @return The calculated logarithm. + */ +static inline float32x4_t vlogq_f32(float32x4_t x); + +/** Calculate hyperbolic tangent. + * + * tanh(x) = (e^2x - 1)/(e^2x + 1) + * + * @note We clamp x to [-5,5] to avoid overflowing issues. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated Hyperbolic Tangent. + */ +static inline float32x4_t vtanhq_f32(float32x4_t val); + +/** Calculate n power of a number. + * + * pow(x,n) = e^(n*log(x)) + * + * @param[in] val Input vector value in F32 format. + * @param[in] n Powers to raise the input to. + * + * @return The calculated power. + */ +static inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n); + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +/** Calculate hyperbolic tangent. + * + * tanh(x) = (e^2x - 1)/(e^2x + 1) + * + * @note We clamp x to [-5,5] to avoid overflowing issues. + * + * @param[in] val Input vector value in F32 format. + * + * @return The calculated Hyperbolic Tangent. + */ +static inline float16x8_t vtanhq_f16(float16x8_t val); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float16x4_t vinv_f16(float16x4_t x); + +/** Calculate reciprocal. + * + * @param[in] x Input value. + * + * @return The calculated reciprocal. + */ +static inline float16x8_t vinvq_f16(float16x8_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float16x4_t vinvsqrt_f16(float16x4_t x); + +/** Calculate inverse square root. + * + * @param[in] x Input value. + * + * @return The calculated inverse square root. + */ +static inline float16x8_t vinvsqrtq_f16(float16x8_t x); + +/** Calculate exponential + * + * @param[in] x Input vector value in F16 format. + * + * @return The calculated exponent. + */ +static inline float16x8_t vexpq_f16(float16x8_t x); + +/** Calculate n power of a number. + * + * pow(x,n) = e^(n*log(x)) + * + * @param[in] val Input vector value in F16 format. + * @param[in] n Powers to raise the input to. + * + * @return The calculated power. + */ +static inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n); +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ + +/** Exponent polynomial coefficients */ +extern const float32_t exp_tab[4*8]; + + +/** Logarithm polynomial coefficients */ +extern const float32_t log_tab[4*8]; + +#ifndef DOXYGEN_SKIP_THIS +inline float32x4_t vfloorq_f32(float32x4_t val) +{ + static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f}; + + const int32x4_t z = vcvtq_s32_f32(val); + const float32x4_t r = vcvtq_f32_s32(z); + + return vbslq_f32(vcgtq_f32(r, val), vsubq_f32(r, vld1q_f32(CONST_1)), r); +} + +inline float32x2_t vinvsqrt_f32(float32x2_t x) +{ + float32x2_t sqrt_reciprocal = vrsqrte_f32(x); + sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmul_f32(vrsqrts_f32(vmul_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + + return sqrt_reciprocal; +} + +inline float32x4_t vinvsqrtq_f32(float32x4_t x) +{ + float32x4_t sqrt_reciprocal = vrsqrteq_f32(x); + sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + + return sqrt_reciprocal; +} + +inline float32x2_t vinv_f32(float32x2_t x) +{ + float32x2_t recip = vrecpe_f32(x); + recip = vmul_f32(vrecps_f32(x, recip), recip); + recip = vmul_f32(vrecps_f32(x, recip), recip); + return recip; +} + +inline float32x4_t vinvq_f32(float32x4_t x) +{ + float32x4_t recip = vrecpeq_f32(x); + recip = vmulq_f32(vrecpsq_f32(x, recip), recip); + recip = vmulq_f32(vrecpsq_f32(x, recip), recip); + return recip; +} + +inline float32x4_t vtaylor_polyq_f32(float32x4_t x, const float32_t *coeffs) +{ + float32x4_t A = vmlaq_f32(vld1q_f32(&coeffs[4*0]), vld1q_f32(&coeffs[4*4]), x); + float32x4_t B = vmlaq_f32(vld1q_f32(&coeffs[4*2]), vld1q_f32(&coeffs[4*6]), x); + float32x4_t C = vmlaq_f32(vld1q_f32(&coeffs[4*1]), vld1q_f32(&coeffs[4*5]), x); + float32x4_t D = vmlaq_f32(vld1q_f32(&coeffs[4*3]), vld1q_f32(&coeffs[4*7]), x); + float32x4_t x2 = vmulq_f32(x, x); + float32x4_t x4 = vmulq_f32(x2, x2); + float32x4_t res = vmlaq_f32(vmlaq_f32(A, B, x2), vmlaq_f32(C, D, x2), x4); + return res; +} + +inline float32x4_t vexpq_f32(float32x4_t x) +{ + static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2) + static const float32_t CONST_INV_LN2[4] = {1.4426950408f,1.4426950408f,1.4426950408f,1.4426950408f}; // 1/ln(2) + static const float32_t CONST_0[4] = {0.f,0.f,0.f,0.f}; + static const int32_t CONST_NEGATIVE_126[4] = {-126,-126,-126,-126}; + + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_f32(x, vld1q_f32(CONST_INV_LN2))); + float32x4_t val = vmlsq_f32(x, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2)); + + // Polynomial Approximation + float32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = vreinterpretq_f32_s32(vqaddq_s32(vreinterpretq_s32_f32(poly), vqshlq_n_s32(m, 23))); + poly = vbslq_f32(vcltq_s32(m, vld1q_s32(CONST_NEGATIVE_126)), vld1q_f32(CONST_0), poly); + + return poly; +} + +inline float32x4_t vlogq_f32(float32x4_t x) +{ + static const int32_t CONST_127[4] = {127,127,127,127}; // 127 + static const float32_t CONST_LN2[4] = {0.6931471805f,0.6931471805f,0.6931471805f,0.6931471805f}; // ln(2) + + // Extract exponent + int32x4_t m = vsubq_s32(vreinterpretq_s32_u32(vshrq_n_u32(vreinterpretq_u32_f32(x), 23)), vld1q_s32(CONST_127)); + float32x4_t val = vreinterpretq_f32_s32(vsubq_s32(vreinterpretq_s32_f32(x), vshlq_n_s32(m, 23))); + + // Polynomial Approximation + float32x4_t poly = vtaylor_polyq_f32(val, log_tab); + + // Reconstruct + poly = vmlaq_f32(poly, vcvtq_f32_s32(m), vld1q_f32(CONST_LN2)); + + return poly; +} + +inline float32x4_t vtanhq_f32(float32x4_t val) +{ + static const float32_t CONST_1[4] = {1.f,1.f,1.f,1.f}; + static const float32_t CONST_2[4] = {2.f,2.f,2.f,2.f}; + static const float32_t CONST_MIN_TANH[4] = {-10.f,-10.f,-10.f,-10.f}; + static const float32_t CONST_MAX_TANH[4] = {10.f,10.f,10.f,10.f}; + + float32x4_t x = vminq_f32(vmaxq_f32(val, vld1q_f32(CONST_MIN_TANH)), vld1q_f32(CONST_MAX_TANH)); + float32x4_t exp2x = vexpq_f32(vmulq_f32(vld1q_f32(CONST_2), x)); + float32x4_t num = vsubq_f32(exp2x, vld1q_f32(CONST_1)); + float32x4_t den = vaddq_f32(exp2x, vld1q_f32(CONST_1)); + float32x4_t tanh = vmulq_f32(num, vinvq_f32(den)); + return tanh; +} + +inline float32x4_t vpowq_f32(float32x4_t val, float32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} +#endif /* DOXYGEN_SKIP_THIS */ + +#ifdef __ARM_FEATURE_FP16_VECTOR_ARITHMETIC +/** Exponent polynomial coefficients */ +/** Logarithm polynomial coefficients */ +#ifndef DOXYGEN_SKIP_THIS +inline float16x8_t vfloorq_f16(float16x8_t val) +{ + static const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f}; + + const int16x8_t z = vcvtq_s16_f16(val); + const float16x8_t r = vcvtq_f16_s16(z); + + return vbslq_f16(vcgtq_f16(r, val), vsubq_f16(r, vld1q_f16(CONST_1)), r); +} +inline float16x4_t vinvsqrt_f16(float16x4_t x) +{ + float16x4_t sqrt_reciprocal = vrsqrte_f16(x); + sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmul_f16(vrsqrts_f16(vmul_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + return sqrt_reciprocal; +} + +inline float16x8_t vinvsqrtq_f16(float16x8_t x) +{ + float16x8_t sqrt_reciprocal = vrsqrteq_f16(x); + sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + sqrt_reciprocal = vmulq_f16(vrsqrtsq_f16(vmulq_f16(x, sqrt_reciprocal), sqrt_reciprocal), sqrt_reciprocal); + return sqrt_reciprocal; +} + +inline float16x4_t vinv_f16(float16x4_t x) +{ + float16x4_t recip = vrecpe_f16(x); + recip = vmul_f16(vrecps_f16(x, recip), recip); + recip = vmul_f16(vrecps_f16(x, recip), recip); + return recip; +} + +inline float16x8_t vinvq_f16(float16x8_t x) +{ + float16x8_t recip = vrecpeq_f16(x); + recip = vmulq_f16(vrecpsq_f16(x, recip), recip); + recip = vmulq_f16(vrecpsq_f16(x, recip), recip); + return recip; +} + +inline float16x8_t vtanhq_f16(float16x8_t val) +{ + const float16_t CONST_1[8] = {1.f,1.f,1.f,1.f,1.f,1.f,1.f,1.f}; + const float16_t CONST_2[8] = {2.f,2.f,2.f,2.f,2.f,2.f,2.f,2.f}; + const float16_t CONST_MIN_TANH[8] = {-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f,-10.f}; + const float16_t CONST_MAX_TANH[8] = {10.f,10.f,10.f,10.f,10.f,10.f,10.f,10.f}; + + const float16x8_t x = vminq_f16(vmaxq_f16(val, vld1q_f16(CONST_MIN_TANH)), vld1q_f16(CONST_MAX_TANH)); + const float16x8_t exp2x = vexpq_f16(vmulq_f16(vld1q_f16(CONST_2), x)); + const float16x8_t num = vsubq_f16(exp2x, vld1q_f16(CONST_1)); + const float16x8_t den = vaddq_f16(exp2x, vld1q_f16(CONST_1)); + const float16x8_t tanh = vmulq_f16(num, vinvq_f16(den)); + return tanh; +} + +inline float16x8_t vtaylor_polyq_f16(float16x8_t x, const float16_t *coeffs) +{ + const float16x8_t A = vaddq_f16(vld1q_f16(&coeffs[8*0]), vmulq_f16(vld1q_f16(&coeffs[8*4]), x)); + const float16x8_t B = vaddq_f16(vld1q_f16(&coeffs[8*2]), vmulq_f16(vld1q_f16(&coeffs[8*6]), x)); + const float16x8_t C = vaddq_f16(vld1q_f16(&coeffs[8*1]), vmulq_f16(vld1q_f16(&coeffs[8*5]), x)); + const float16x8_t D = vaddq_f16(vld1q_f16(&coeffs[8*3]), vmulq_f16(vld1q_f16(&coeffs[8*7]), x)); + const float16x8_t x2 = vmulq_f16(x, x); + const float16x8_t x4 = vmulq_f16(x2, x2); + const float16x8_t res = vaddq_f16(vaddq_f16(A, vmulq_f16(B, x2)), vmulq_f16(vaddq_f16(C, vmulq_f16(D, x2)), x4)); + return res; +} + +inline float16x8_t vexpq_f16(float16x8_t x) +{ + // TODO (COMPMID-1535) : Revisit FP16 approximations + const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x)); + const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x)); + + const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vexpq_f32(x_low)), vexpq_f32(x_high)); + return res; +} + +inline float16x8_t vlogq_f16(float16x8_t x) +{ + // TODO (COMPMID-1535) : Revisit FP16 approximations + const float32x4_t x_high = vcvt_f32_f16(vget_high_f16(x)); + const float32x4_t x_low = vcvt_f32_f16(vget_low_f16(x)); + + const float16x8_t res = vcvt_high_f16_f32(vcvt_f16_f32(vlogq_f32(x_low)), vlogq_f32(x_high)); + return res; +} + +inline float16x8_t vpowq_f16(float16x8_t val, float16x8_t n) +{ + // TODO (giaiod01) - COMPMID-1535 + float32x4_t n0_f32 = vcvt_f32_f16(vget_low_f16(n)); + float32x4_t n1_f32 = vcvt_f32_f16(vget_high_f16(n)); + float32x4_t val0_f32 = vcvt_f32_f16(vget_low_f16(val)); + float32x4_t val1_f32 = vcvt_f32_f16(vget_high_f16(val)); + + float32x4_t res0_f32 = vexpq_f32(vmulq_f32(n0_f32, vlogq_f32(val0_f32))); + float32x4_t res1_f32 = vexpq_f32(vmulq_f32(n1_f32, vlogq_f32(val1_f32))); + + return vcombine_f16(vcvt_f16_f32(res0_f32), vcvt_f16_f32(res1_f32)); +} +#endif /* DOXYGEN_SKIP_THIS */ +#endif /* __ARM_FEATURE_FP16_VECTOR_ARITHMETIC */ +#endif +#endif /* __ARM_COMPUTE_NEMATH_H__ */ diff --git a/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt b/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt new file mode 100644 index 0000000..5429278 --- /dev/null +++ b/Drivers/CMSIS/DSP/ComputeLibrary/LICENSE.txt @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2017-2019 ARM Software + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c b/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c new file mode 100644 index 0000000..bdd39a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/ComputeLibrary/Source/arm_cl_tables.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, 2019 ARM Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_math.h" +#include "NEMath.h" + +#if defined(ARM_MATH_NEON) + +/** Exponent polynomial coefficients */ +const float32_t exp_tab[4*8] = +{ + 1.f,1.f,1.f,1.f, + 0.0416598916054f,0.0416598916054f,0.0416598916054f,0.0416598916054f, + 0.500000596046f,0.500000596046f,0.500000596046f,0.500000596046f, + 0.0014122662833f,0.0014122662833f,0.0014122662833f,0.0014122662833f, + 1.00000011921f,1.00000011921f,1.00000011921f,1.00000011921f, + 0.00833693705499f,0.00833693705499f,0.00833693705499f,0.00833693705499f, + 0.166665703058f,0.166665703058f,0.166665703058f,0.166665703058f, + 0.000195780929062f,0.000195780929062f,0.000195780929062f,0.000195780929062f +}; + +/** Logarithm polynomial coefficients */ +const float32_t log_tab[4*8] = +{ + -2.29561495781f,-2.29561495781f,-2.29561495781f,-2.29561495781f, + -2.47071170807f,-2.47071170807f,-2.47071170807f,-2.47071170807f, + -5.68692588806f,-5.68692588806f,-5.68692588806f,-5.68692588806f, + -0.165253549814f,-0.165253549814f,-0.165253549814f,-0.165253549814f, + 5.17591238022f,5.17591238022f,5.17591238022f,5.17591238022f, + 0.844007015228f,0.844007015228f,0.844007015228f,0.844007015228f, + 4.58445882797f,4.58445882797f,4.58445882797f,4.58445882797f, + 0.0141278216615f,0.0141278216615f,0.0141278216615f,0.0141278216615f +}; + +#endif diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt new file mode 100644 index 0000000..54e9bec --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_class_marks_example + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt new file mode 100644 index 0000000..6ac92d4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_bayes_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_bayes_example) + + +include(config) +configApp(arm_bayes_example ${ROOT}) + +target_sources(arm_bayes_example PRIVATE arm_bayes_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_bayes_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c new file mode 100644 index 0000000..1be97d6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_bayes_example/arm_bayes_example_f32.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2019-2020 ARM Limited. All rights reserved. +* +* $Date: 09. December 2019 +* $Revision: V1.0.0 +* +* Project: CMSIS DSP Library +* Title: arm_bayes_example_f32.c +* +* Description: Example code demonstrating how to use Bayes functions. +* +* Target Processor: Cortex-M/Cortex-A +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup BayesExample Bayes Example + * + * \par Description: + * \par + * Demonstrates the use of Bayesian classifier functions. It is complementing the tutorial + * about classical ML with CMSIS-DSP and python scikit-learn: + * https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classical-ml-with-arm-cmsis-dsp-libraries + * + */ + + +/** \example arm_bayes_example_f32.c + */ + +#include +#include +#include "arm_math.h" + +/* +Those parameters can be generated with the python library scikit-learn. +*/ +arm_gaussian_naive_bayes_instance_f32 S; + +#define NB_OF_CLASSES 3 +#define VECTOR_DIMENSION 2 + +const float32_t theta[NB_OF_CLASSES*VECTOR_DIMENSION] = { + 1.4539529436590528f, 0.8722776016801852f, + -1.5267934452462473f, 0.903204577814203f, + -0.15338006360932258f, -2.9997913665803964f +}; /**< Mean values for the Gaussians */ + +const float32_t sigma[NB_OF_CLASSES*VECTOR_DIMENSION] = { + 1.0063470889514925f, 0.9038018246524426f, + 1.0224479953244736f, 0.7768764290432544f, + 1.1217662403241206f, 1.2303890106020325f +}; /**< Variances for the Gaussians */ + +const float32_t classPriors[NB_OF_CLASSES] = { + 0.3333333333333333f, 0.3333333333333333f, 0.3333333333333333f +}; /**< Class prior probabilities */ + +int32_t main(void) +{ + /* Array of input data */ + float32_t in[2]; + + /* Result of the classifier */ + float32_t result[NB_OF_CLASSES]; + float32_t temp[NB_OF_CLASSES]; + float32_t maxProba; + uint32_t index; + + S.vectorDimension = VECTOR_DIMENSION; + S.numberOfClasses = NB_OF_CLASSES; + S.theta = theta; + S.sigma = sigma; + S.classPriors = classPriors; + S.epsilon=4.328939296523643e-09f; + + in[0] = 1.5f; + in[1] = 1.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + + in[0] = -1.5f; + in[1] = 1.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + + in[0] = 0.0f; + in[1] = -3.0f; + + index = arm_gaussian_naive_bayes_predict_f32(&S, in, result,temp); + + maxProba = result[index]; + +#if defined(SEMIHOSTING) + printf("Class = %d\n", index); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt new file mode 100644 index 0000000..54e9bec --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_class_marks_example + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt new file mode 100644 index 0000000..a987446 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_class_marks_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_class_marks_example) + + +include(config) +configApp(arm_class_marks_example ${ROOT}) + +target_sources(arm_class_marks_example PRIVATE arm_class_marks_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_class_marks_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c new file mode 100644 index 0000000..1bc2ad1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_class_marks_example_f32.c +* +* Description: Example code to calculate Minimum, Maximum +* Mean, std and variance of marks obtained in a class +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ClassMarks Class Marks Example + * + * \par Description: + * \par + * Demonstrates the use the Maximum, Minimum, Mean, Standard Deviation, Variance + * and Matrix functions to calculate statistical values of marks obtained in a class. + * + * \note This example also demonstrates the usage of static initialization. + * + * \par Variables Description: + * \par + * \li \c testMarks_f32 points to the marks scored by 20 students in 4 subjects + * \li \c max_marks Maximum of all marks + * \li \c min_marks Minimum of all marks + * \li \c mean Mean of all marks + * \li \c var Variance of the marks + * \li \c std Standard deviation of the marks + * \li \c numStudents Total number of students in the class + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_mult_f32() + * - arm_max_f32() + * - arm_min_f32() + * - arm_mean_f32() + * - arm_std_f32() + * - arm_var_f32() + * + * Refer + * \link arm_class_marks_example_f32.c \endlink + * + */ + + +/** \example arm_class_marks_example_f32.c + */ +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define USE_STATIC_INIT + + /* ---------------------------------------------------------------------- +** Global defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES (20*4) + +/* ---------------------------------------------------------------------- +** List of Marks scored by 20 students for 4 subjects +** ------------------------------------------------------------------- */ +const float32_t testMarks_f32[TEST_LENGTH_SAMPLES] = +{ + 42.000000, 37.000000, 81.000000, 28.000000, + 83.000000, 72.000000, 36.000000, 38.000000, + 32.000000, 51.000000, 63.000000, 64.000000, + 97.000000, 82.000000, 95.000000, 90.000000, + 66.000000, 51.000000, 54.000000, 42.000000, + 67.000000, 56.000000, 45.000000, 57.000000, + 67.000000, 69.000000, 35.000000, 52.000000, + 29.000000, 81.000000, 58.000000, 47.000000, + 38.000000, 76.000000, 100.000000, 29.000000, + 33.000000, 47.000000, 29.000000, 50.000000, + 34.000000, 41.000000, 61.000000, 46.000000, + 52.000000, 50.000000, 48.000000, 36.000000, + 47.000000, 55.000000, 44.000000, 40.000000, + 100.000000, 94.000000, 84.000000, 37.000000, + 32.000000, 71.000000, 47.000000, 77.000000, + 31.000000, 50.000000, 49.000000, 35.000000, + 63.000000, 67.000000, 40.000000, 31.000000, + 29.000000, 68.000000, 61.000000, 38.000000, + 31.000000, 28.000000, 28.000000, 76.000000, + 55.000000, 33.000000, 29.000000, 39.000000 +}; + + +/* ---------------------------------------------------------------------- +* Number of subjects X 1 +* ------------------------------------------------------------------- */ +const float32_t testUnity_f32[4] = +{ + 1.000, 1.000, 1.000, 1.000 +}; + + +/* ---------------------------------------------------------------------- +** f32 Output buffer +** ------------------------------------------------------------------- */ +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + + +/* ------------------------------------------------------------------ +* Global defines +*------------------------------------------------------------------- */ +#define NUMSTUDENTS 20 +#define NUMSUBJECTS 4 + +/* ------------------------------------------------------------------ +* Global variables +*------------------------------------------------------------------- */ + + uint32_t numStudents = 20; + uint32_t numSubjects = 4; +float32_t max_marks, min_marks, mean, std, var; + uint32_t student_num; + +/* ---------------------------------------------------------------------------------- +* Main f32 test function. It returns maximum marks secured and student number +* ------------------------------------------------------------------------------- */ + +int32_t main() +{ + +#ifndef USE_STATIC_INIT + + arm_matrix_instance_f32 srcA; + arm_matrix_instance_f32 srcB; + arm_matrix_instance_f32 dstC; + + /* Input and output matrices initializations */ + arm_mat_init_f32(&srcA, numStudents, numSubjects, (float32_t *)testMarks_f32); + arm_mat_init_f32(&srcB, numSubjects, 1, (float32_t *)testUnity_f32); + arm_mat_init_f32(&dstC, numStudents, 1, testOutput); + +#else + + /* Static Initializations of Input and output matrix sizes and array */ + arm_matrix_instance_f32 srcA = {NUMSTUDENTS, NUMSUBJECTS, (float32_t *)testMarks_f32}; + arm_matrix_instance_f32 srcB = {NUMSUBJECTS, 1, (float32_t *)testUnity_f32}; + arm_matrix_instance_f32 dstC = {NUMSTUDENTS, 1, testOutput}; + +#endif + + + /* ---------------------------------------------------------------------- + *Call the Matrix multiplication process function + * ------------------------------------------------------------------- */ + arm_mat_mult_f32(&srcA, &srcB, &dstC); + + /* ---------------------------------------------------------------------- + ** Call the Max function to calculate max marks among numStudents + ** ------------------------------------------------------------------- */ + arm_max_f32(testOutput, numStudents, &max_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Min function to calculate min marks among numStudents + ** ------------------------------------------------------------------- */ + arm_min_f32(testOutput, numStudents, &min_marks, &student_num); + + /* ---------------------------------------------------------------------- + ** Call the Mean function to calculate mean + ** ------------------------------------------------------------------- */ + arm_mean_f32(testOutput, numStudents, &mean); + + /* ---------------------------------------------------------------------- + ** Call the std function to calculate standard deviation + ** ------------------------------------------------------------------- */ + arm_std_f32(testOutput, numStudents, &std); + + /* ---------------------------------------------------------------------- + ** Call the var function to calculate variance + ** ------------------------------------------------------------------- */ + arm_var_f32(testOutput, numStudents, &var); + +#if defined(SEMIHOSTING) + printf("mean = %f, std = %f\n",mean,std); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt new file mode 100644 index 0000000..95aed2e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_convolution_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt new file mode 100644 index 0000000..c6acc7a --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_convolution_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_convolution_example) + + +include(config) +configApp(arm_convolution_example ${ROOT}) + +target_sources(arm_convolution_example PRIVATE arm_convolution_example_f32.c math_helper.c) + +### Sources and libs + +target_link_libraries(arm_convolution_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c new file mode 100644 index 0000000..099f92e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c @@ -0,0 +1,263 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_convolution_example_f32.c +* +* Description: Example code demonstrating Convolution of two input signals using fft. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup ConvolutionExample Convolution Example + * + * \par Description: + * \par + * Demonstrates the convolution theorem with the use of the Complex FFT, Complex-by-Complex + * Multiplication, and Support Functions. + * + * \par Algorithm: + * \par + * The convolution theorem states that convolution in the time domain corresponds to + * multiplication in the frequency domain. Therefore, the Fourier transform of the convoution of + * two signals is equal to the product of their individual Fourier transforms. + * The Fourier transform of a signal can be evaluated efficiently using the Fast Fourier Transform (FFT). + * \par + * Two input signals, a[n] and b[n], with lengths \c n1 and \c n2 respectively, + * are zero padded so that their lengths become \c N, which is greater than or equal to (n1+n2-1) + * and is a power of 4 as FFT implementation is radix-4. + * The convolution of a[n] and b[n] is obtained by taking the FFT of the input + * signals, multiplying the Fourier transforms of the two signals, and taking the inverse FFT of + * the multiplied result. + * \par + * This is denoted by the following equations: + * 
 A[k] = FFT(a[n],N)
+ * B[k] = FFT(b[n],N)
+ * conv(a[n], b[n]) = IFFT(A[k] * B[k], N)
+ * where A[k] and B[k] are the N-point FFTs of the signals a[n] + * and b[n] respectively. + * The length of the convolved signal is (n1+n2-1). + * + * \par Block Diagram: + * \par + * \image html Convolution.gif + * + * \par Variables Description: + * \par + * \li \c testInputA_f32 points to the first input sequence + * \li \c srcALen length of the first input sequence + * \li \c testInputB_f32 points to the second input sequence + * \li \c srcBLen length of the second input sequence + * \li \c outLen length of convolution output sequence, (srcALen + srcBLen - 1) + * \li \c AxB points to the output array where the product of individual FFTs of inputs is stored. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fill_f32() + * - arm_copy_f32() + * - arm_cfft_radix4_init_f32() + * - arm_cfft_radix4_f32() + * - arm_cmplx_mult_cmplx_f32() + * + * Refer + * \link arm_convolution_example_f32.c \endlink + * + */ + + +/** \example arm_convolution_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 128 +#define DELTA (0.000001f) +#define SNR_THRESHOLD 90 + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t Ak[MAX_BLOCKSIZE]; /* Input A */ +float32_t Bk[MAX_BLOCKSIZE]; /* Input B */ +float32_t AxB[MAX_BLOCKSIZE * 2]; /* Output */ + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Convolution example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +float32_t testInputA_f32[64] = +{ + -0.808920, 1.357369, 1.180861, -0.504544, 1.762637, -0.703285, + 1.696966, 0.620571, -0.151093, -0.100235, -0.872382, -0.403579, + -0.860749, -0.382648, -1.052338, 0.128113, -0.646269, 1.093377, + -2.209198, 0.471706, 0.408901, 1.266242, 0.598252, 1.176827, + -0.203421, 0.213596, -0.851964, -0.466958, 0.021841, -0.698938, + -0.604107, 0.461778, -0.318219, 0.942520, 0.577585, 0.417619, + 0.614665, 0.563679, -1.295073, -0.764437, 0.952194, -0.859222, + -0.618554, -2.268542, -1.210592, 1.655853, -2.627219, -0.994249, + -1.374704, 0.343799, 0.025619, 1.227481, -0.708031, 0.069355, + -1.845228, -1.570886, 1.010668, -1.802084, 1.630088, 1.286090, + -0.161050, -0.940794, 0.367961, 0.291907 + +}; + +float32_t testInputB_f32[64] = +{ + 0.933724, 0.046881, 1.316470, 0.438345, 0.332682, 2.094885, + 0.512081, 0.035546, 0.050894, -2.320371, 0.168711, -1.830493, + -0.444834, -1.003242, -0.531494, -1.365600, -0.155420, -0.757692, + -0.431880, -0.380021, 0.096243, -0.695835, 0.558850, -1.648962, + 0.020369, -0.363630, 0.887146, 0.845503, -0.252864, -0.330397, + 1.269131, -1.109295, -1.027876, 0.135940, 0.116721, -0.293399, + -1.349799, 0.166078, -0.802201, 0.369367, -0.964568, -2.266011, + 0.465178, 0.651222, -0.325426, 0.320245, -0.784178, -0.579456, + 0.093374, 0.604778, -0.048225, 0.376297, -0.394412, 0.578182, + -1.218141, -1.387326, 0.692462, -0.631297, 0.153137, -0.638952, + 0.635474, -0.970468, 1.334057, -0.111370 +}; + +const float testRefOutput_f32[127] = +{ + -0.818943, 1.229484, -0.533664, 1.016604, 0.341875, -1.963656, + 5.171476, 3.478033, 7.616361, 6.648384, 0.479069, 1.792012, + -1.295591, -7.447818, 0.315830, -10.657445, -2.483469, -6.524236, + -7.380591, -3.739005, -8.388957, 0.184147, -1.554888, 3.786508, + -1.684421, 5.400610, -1.578126, 7.403361, 8.315999, 2.080267, + 11.077776, 2.749673, 7.138962, 2.748762, 0.660363, 0.981552, + 1.442275, 0.552721, -2.576892, 4.703989, 0.989156, 8.759344, + -0.564825, -3.994680, 0.954710, -5.014144, 6.592329, 1.599488, + -13.979146, -0.391891, -4.453369, -2.311242, -2.948764, 1.761415, + -0.138322, 10.433007, -2.309103, 4.297153, 8.535523, 3.209462, + 8.695819, 5.569919, 2.514304, 5.582029, 2.060199, 0.642280, + 7.024616, 1.686615, -6.481756, 1.343084, -3.526451, 1.099073, + -2.965764, -0.173723, -4.111484, 6.528384, -6.965658, 1.726291, + 1.535172, 11.023435, 2.338401, -4.690188, 1.298210, 3.943885, + 8.407885, 5.168365, 0.684131, 1.559181, 1.859998, 2.852417, + 8.574070, -6.369078, 6.023458, 11.837963, -6.027632, 4.469678, + -6.799093, -2.674048, 6.250367, -6.809971, -3.459360, 9.112410, + -2.711621, -1.336678, 1.564249, -1.564297, -1.296760, 8.904013, + -3.230109, 6.878013, -7.819823, 3.369909, -1.657410, -2.007358, + -4.112825, 1.370685, -3.420525, -6.276605, 3.244873, -3.352638, + 1.545372, 0.902211, 0.197489, -1.408732, 0.523390, 0.348440, 0 +}; + + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t srcALen = 64; /* Length of Input A */ +uint32_t srcBLen = 64; /* Length of Input B */ +uint32_t outLen; /* Length of convolution output */ +float32_t snr; /* output SNR */ + +int32_t main(void) +{ + arm_status status; /* Status of the example */ + arm_cfft_radix4_instance_f32 cfft_instance; /* CFFT Structure instance */ + +#if defined(SEMIHOSTING) + printf("START\n"); +#endif + + /* CFFT Structure instance pointer */ + arm_cfft_radix4_instance_f32 *cfft_instance_ptr = + (arm_cfft_radix4_instance_f32*) &cfft_instance; + + /* output length of convolution */ + outLen = srcALen + srcBLen - 1; + + /* Initialise the fft input buffers with all zeros */ + arm_fill_f32(0.0, Ak, MAX_BLOCKSIZE); + arm_fill_f32(0.0, Bk, MAX_BLOCKSIZE); + + /* Copy the input values to the fft input buffers */ + arm_copy_f32(testInputA_f32, Ak, MAX_BLOCKSIZE/2); + arm_copy_f32(testInputB_f32, Bk, MAX_BLOCKSIZE/2); + + /* Initialize the CFFT function to compute 64 point fft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 0, 1); + + /* Transform input a[n] from time domain to frequency domain A[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Ak); + /* Transform input b[n] from time domain to frequency domain B[k] */ + arm_cfft_radix4_f32(cfft_instance_ptr, Bk); + + /* Complex Multiplication of the two input buffers in frequency domain */ + arm_cmplx_mult_cmplx_f32(Ak, Bk, AxB, MAX_BLOCKSIZE/2); + + /* Initialize the CIFFT function to compute 64 point ifft */ + status = arm_cfft_radix4_init_f32(cfft_instance_ptr, 64, 1, 1); + + /* Transform the multiplication output from frequency domain to time domain, + that gives the convolved output. */ + arm_cfft_radix4_f32(cfft_instance_ptr, AxB); + + /* SNR Calculation */ + snr = arm_snr_f32((float32_t *)testRefOutput_f32, AxB, srcALen + srcBLen - 1); + + /* Compare the SNR with threshold to test whether the + computed output is matched with the reference output values. */ + status = (snr <= SNR_THRESHOLD) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c new file mode 100644 index 0000000..950bf42 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c @@ -0,0 +1,474 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt new file mode 100644 index 0000000..4d290d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_dotproduct_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt new file mode 100644 index 0000000..9f4496b --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_dotproduct_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_dotproduct_example) + + +include(config) +configApp(arm_dotproduct_example ${ROOT}) + +target_sources(arm_dotproduct_example PRIVATE arm_dotproduct_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_dotproduct_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c new file mode 100644 index 0000000..a94a415 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_dotproduct_example_f32.c +* +* Description: Example code computing dot product of two vectors. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup DotproductExample Dot Product Example + * + * \par Description: + * \par + * Demonstrates the use of the Multiply and Add functions to perform the dot product. + * The dot product of two vectors is obtained by multiplying corresponding elements + * and summing the products. + + * \par Algorithm: + * \par + * The two input vectors \c A and \c B with length \c n, are multiplied element-by-element + * and then added to obtain dot product. + * \par + * This is denoted by the following equation: + * 
  dotProduct = A[0] * B[0] + A[1] * B[1] + ... + A[n-1] * B[n-1]
+ * + * \par Block Diagram: + * \par + * \image html dotProduct.gif + * + * \par Variables Description: + * \par + * \li \c srcA_buf_f32 points to first input vector + * \li \c srcB_buf_f32 points to second input vector + * \li \c testOutput stores dot product of the two input vectors. + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_dotproduct_example_f32.c \endlink + * + */ + + +/** \example arm_dotproduct_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Dot Product example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ +/* ---------------------------------------------------------------------- +** Test input data of srcA for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcA_buf_f32[MAX_BLOCKSIZE] = +{ + -0.4325648115282207, -1.6655843782380970, 0.1253323064748307, + 0.2876764203585489, -1.1464713506814637, 1.1909154656429988, + 1.1891642016521031, -0.0376332765933176, 0.3272923614086541, + 0.1746391428209245, -0.1867085776814394, 0.7257905482933027, + -0.5883165430141887, 2.1831858181971011, -0.1363958830865957, + 0.1139313135208096, 1.0667682113591888, 0.0592814605236053, + -0.0956484054836690, -0.8323494636500225, 0.2944108163926404, + -1.3361818579378040, 0.7143245518189522, 1.6235620644462707, + -0.6917757017022868, 0.8579966728282626, 1.2540014216025324, + -1.5937295764474768, -1.4409644319010200, 0.5711476236581780, + -0.3998855777153632, 0.6899973754643451 +}; + +/* ---------------------------------------------------------------------- +** Test input data of srcB for blockSize 32 +** ------------------------------------------------------------------- */ +float32_t srcB_buf_f32[MAX_BLOCKSIZE] = +{ + 1.7491401329284098, 0.1325982188803279, 0.3252281811989881, + -0.7938091410349637, 0.3149236145048914, -0.5272704888029532, + 0.9322666565031119, 1.1646643544607362, -2.0456694357357357, + -0.6443728590041911, 1.7410657940825480, 0.4867684246821860, + 1.0488288293660140, 1.4885752747099299, 1.2705014969484090, + -1.8561241921210170, 2.1343209047321410, 1.4358467535865909, + -0.9173023332875400, -1.1060770780029008, 0.8105708062681296, + 0.6985430696369063, -0.4015827425012831, 1.2687512030669628, + -0.7836083053674872, 0.2132664971465569, 0.7878984786088954, + 0.8966819356782295, -0.1869172943544062, 1.0131816724341454, + 0.2484350696132857, 0.0596083377937976 +}; + +/* Reference dot product output */ +float32_t refDotProdOut = 5.9273644806352142; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +float32_t multOutput[MAX_BLOCKSIZE]; /* Intermediate output */ +float32_t testOutput; /* Final ouput */ + +arm_status status; /* Status of the example */ + +int32_t main(void) +{ + uint32_t i; /* Loop counter */ + float32_t diff; /* Difference between reference and test outputs */ + + /* Multiplication of two input buffers */ + arm_mult_f32(srcA_buf_f32, srcB_buf_f32, multOutput, MAX_BLOCKSIZE); + + /* Accumulate the multiplication output values to + get the dot product of the two inputs */ + for(i=0; i< MAX_BLOCKSIZE; i++) + { + arm_add_f32(&testOutput, &multOutput[i], &testOutput, 1); + } + + /* absolute value of difference between ref and test */ + diff = fabsf(refDotProdOut - testOutput); + + /* Comparison of dot product value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt new file mode 100644 index 0000000..8609b69 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_fft_bin_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt new file mode 100644 index 0000000..a56d0fb --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_fft_bin_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_fft_bin_example) + + +include(config) +configApp(arm_fft_bin_example ${ROOT}) + +target_sources(arm_fft_bin_example PRIVATE arm_fft_bin_data.c arm_fft_bin_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_fft_bin_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c new file mode 100644 index 0000000..b5159e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +Test Input signal contains 10KHz signal + Uniformly distributed white noise +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_10khz[2048] = +{ +-0.865129623056441, 0.000000000000000, -2.655020678073846, 0.000000000000000, 0.600664612949661, 0.000000000000000, 0.080378093886515, 0.000000000000000, +-2.899160484012034, 0.000000000000000, 2.563004262857762, 0.000000000000000, 3.078328403304206, 0.000000000000000, 0.105906778385130, 0.000000000000000, +0.048366940168201, 0.000000000000000, -0.145696461188734, 0.000000000000000, -0.023417155362879, 0.000000000000000, 2.127729174988954, 0.000000000000000, +-1.176633086028377, 0.000000000000000, 3.690223557991855, 0.000000000000000, -0.622791766173194, 0.000000000000000, 0.722837373872203, 0.000000000000000, +2.739754205367484, 0.000000000000000, -0.062610410524552, 0.000000000000000, -0.891296810967338, 0.000000000000000, -1.845872258871811, 0.000000000000000, +1.195039415434387, 0.000000000000000, -2.177388969045026, 0.000000000000000, 1.078649103637905, 0.000000000000000, 2.570976050490193, 0.000000000000000, +-1.383551403404574, 0.000000000000000, 2.392141424058873, 0.000000000000000, 2.858002843205065, 0.000000000000000, -3.682433899725536, 0.000000000000000, +-3.488146646451150, 0.000000000000000, 1.323468578888120, 0.000000000000000, -0.099771155430726, 0.000000000000000, 1.561168082500454, 0.000000000000000, +1.025026795103179, 0.000000000000000, 0.928841900171200, 0.000000000000000, 2.930499509864950, 0.000000000000000, 2.013349089766430, 0.000000000000000, +2.381676148486737, 0.000000000000000, -3.081062307950236, 0.000000000000000, -0.389579115537544, 0.000000000000000, 0.181540149166620, 0.000000000000000, +-2.601953341353208, 0.000000000000000, 0.333435137783218, 0.000000000000000, -2.812945856162965, 0.000000000000000, 2.649109640172910, 0.000000000000000, +-1.003963025744654, 0.000000000000000, 1.552460768755035, 0.000000000000000, 0.088641345335247, 0.000000000000000, -2.519951327113426, 0.000000000000000, +-4.341348988610527, 0.000000000000000, 0.557772429359965, 0.000000000000000, -1.671267412948494, 0.000000000000000, 0.733951350960387, 0.000000000000000, +0.409263788034864, 0.000000000000000, 3.566033071952806, 0.000000000000000, 1.882565173848352, 0.000000000000000, -1.106017073793287, 0.000000000000000, +0.154456720778718, 0.000000000000000, -2.513205795512153, 0.000000000000000, 0.310978660939421, 0.000000000000000, 0.579706500111723, 0.000000000000000, +0.000086383683251, 0.000000000000000, -1.311866980897721, 0.000000000000000, 1.840007477574986, 0.000000000000000, -3.253005768451345, 0.000000000000000, +1.462584328739432, 0.000000000000000, 1.610103610851738, 0.000000000000000, 0.761914676858907, 0.000000000000000, 0.974541361089834, 0.000000000000000, +0.686845845885983, 0.000000000000000, 1.849153122025191, 0.000000000000000, 0.787800410401453, 0.000000000000000, -1.187438909666279, 0.000000000000000, +-0.754937911044720, 0.000000000000000, 0.084373858395232, 0.000000000000000, -2.600269011710521, 0.000000000000000, -0.962982842142644, 0.000000000000000, +-0.369328108540868, 0.000000000000000, 0.810791418361879, 0.000000000000000, 3.587016488699641, 0.000000000000000, -0.520776145083723, 0.000000000000000, +0.640249919627884, 0.000000000000000, 1.103122489464969, 0.000000000000000, 2.231779881455556, 0.000000000000000, -1.308035392685241, 0.000000000000000, +0.424070304330106, 0.000000000000000, -0.200383932651189, 0.000000000000000, -2.365526783356541, 0.000000000000000, -0.989114757436628, 0.000000000000000, +2.770807688959777, 0.000000000000000, -0.444172737462307, 0.000000000000000, 0.079760979374078, 0.000000000000000, -0.005199118412183, 0.000000000000000, +-0.664712668309527, 0.000000000000000, -0.624171857561896, 0.000000000000000, 0.537306979007338, 0.000000000000000, -2.575955675497642, 0.000000000000000, +1.562363235756780, 0.000000000000000, 1.814069369848895, 0.000000000000000, -1.293428583392509, 0.000000000000000, -1.026188449495686, 0.000000000000000, +-2.981771815588717, 0.000000000000000, -4.223468103075124, 0.000000000000000, 2.672674782004045, 0.000000000000000, -0.856096801117735, 0.000000000000000, +0.048517345512563, 0.000000000000000, -0.026860721136222, 0.000000000000000, 0.392932277758187, 0.000000000000000, -1.331740855093099, 0.000000000000000, +-1.894292129477081, 0.000000000000000, -1.425006468460681, 0.000000000000000, -2.721772427617057, 0.000000000000000, -1.616831100216806, 0.000000000000000, +3.551177651488947, 0.000000000000000, -0.069685667896087, 0.000000000000000, -3.134634907409102, 0.000000000000000, -0.263627598944639, 0.000000000000000, +-1.650469945991350, 0.000000000000000, -2.203580339374399, 0.000000000000000, -0.872203246123242, 0.000000000000000, 1.230782812607287, 0.000000000000000, +0.257288860093291, 0.000000000000000, 1.989083106173137, 0.000000000000000, -1.985638729453261, 0.000000000000000, -1.416185105842892, 0.000000000000000, +-1.131097688325772, 0.000000000000000, -2.245130805416057, 0.000000000000000, -1.938873996219074, 0.000000000000000, 2.043608361562645, 0.000000000000000, +-0.583727989880841, 0.000000000000000, -1.785266378212929, 0.000000000000000, 1.961457586224753, 0.000000000000000, 1.139400099963223, 0.000000000000000, +-1.979519343363991, 0.000000000000000, 2.003023322818429, 0.000000000000000, 0.229004069076829, 0.000000000000000, 3.452808862193135, 0.000000000000000, +2.882273808365857, 0.000000000000000, -1.549450501844438, 0.000000000000000, -3.283872089931876, 0.000000000000000, -0.327025884099064, 0.000000000000000, +-0.054979977136430, 0.000000000000000, -1.192280531479012, 0.000000000000000, 0.645539328365578, 0.000000000000000, 2.300832863404618, 0.000000000000000, +-1.092951789535240, 0.000000000000000, -1.017368249363773, 0.000000000000000, -0.142673056169787, 0.000000000000000, 0.831073544881250, 0.000000000000000, +-2.314612531587064, 0.000000000000000, -2.221456299106321, 0.000000000000000, 0.460261143885226, 0.000000000000000, 0.050585301888595, 0.000000000000000, +0.364373329183988, 0.000000000000000, -1.685956552069538, 0.000000000000000, 0.050664512351055, 0.000000000000000, -0.193355783902718, 0.000000000000000, +-0.158660446046828, 0.000000000000000, 2.394156453841953, 0.000000000000000, -1.562965718554525, 0.000000000000000, -2.199750600869900, 0.000000000000000, +1.544984022381773, 0.000000000000000, -1.988307216807315, 0.000000000000000, -0.628240722541046, 0.000000000000000, -1.436235771505429, 0.000000000000000, +1.677013691147313, 0.000000000000000, 1.600741781678228, 0.000000000000000, -0.757380959134706, 0.000000000000000, -4.784797439515566, 0.000000000000000, +0.265121462834569, 0.000000000000000, 3.862029485934378, 0.000000000000000, 2.386823577249430, 0.000000000000000, -3.655779745436893, 0.000000000000000, +-0.763541621368016, 0.000000000000000, -1.182140388432962, 0.000000000000000, -1.349106114858063, 0.000000000000000, -2.287533624396759, 0.000000000000000, +-0.028603745188423, 0.000000000000000, -1.353580755934427, 0.000000000000000, 0.461602380352937, 0.000000000000000, -0.059599055078928, 0.000000000000000, +-0.929946734342228, 0.000000000000000, 0.065773089295561, 0.000000000000000, 1.106565863102982, 0.000000000000000, 4.719295086373593, 0.000000000000000, +-2.108377703544395, 0.000000000000000, -2.226393620240159, 0.000000000000000, 1.375668397437521, 0.000000000000000, -0.960772428525443, 0.000000000000000, +-2.156313465390571, 0.000000000000000, 1.126060012375311, 0.000000000000000, 2.756485137030720, 0.000000000000000, 0.739639690862600, 0.000000000000000, +3.914769510295006, 0.000000000000000, 1.685232785586675, 0.000000000000000, 4.079058040970612, 0.000000000000000, -1.174598301660513, 0.000000000000000, +-2.885776587275580, 0.000000000000000, -0.241073635188767, 0.000000000000000, 3.080489872502403, 0.000000000000000, -2.051244183999421, 0.000000000000000, +0.664330486845139, 0.000000000000000, -1.697798999370016, 0.000000000000000, 1.452369423649782, 0.000000000000000, -1.523532831019280, 0.000000000000000, +0.171981186587481, 0.000000000000000, -4.685274721583927, 0.000000000000000, -1.336175835319380, 0.000000000000000, 1.419070770428945, 0.000000000000000, +-0.035791601713475, 0.000000000000000, 2.291937971632081, 0.000000000000000, -1.962559313450293, 0.000000000000000, -4.831595589339301, 0.000000000000000, +-1.857055284000925, 0.000000000000000, 2.606271522635512, 0.000000000000000, -0.576447978738030, 0.000000000000000, 0.082299166967720, 0.000000000000000, +1.888399453494614, 0.000000000000000, -3.564705298046079, 0.000000000000000, -0.939357831083889, 0.000000000000000, -1.903578203697778, 0.000000000000000, +-2.642492215447250, 0.000000000000000, -0.182990405251017, 0.000000000000000, 3.742026478011174, 0.000000000000000, 0.104295803798333, 0.000000000000000, +1.848678195370347, 0.000000000000000, -1.887384346896369, 0.000000000000000, 0.365048973046045, 0.000000000000000, -0.889638010354219, 0.000000000000000, +1.173877118428863, 0.000000000000000, -1.178562827540109, 0.000000000000000, 0.610271645685184, 0.000000000000000, 1.831284815697871, 0.000000000000000, +0.449575390102283, 0.000000000000000, 1.597171905253443, 0.000000000000000, 3.918574971904773, 0.000000000000000, 0.868104027970404, 0.000000000000000, +0.582643134746494, 0.000000000000000, 2.321256382353331, 0.000000000000000, -0.238118642223180, 0.000000000000000, -2.890287868054370, 0.000000000000000, +0.970995414625622, 0.000000000000000, 0.666137930891283, 0.000000000000000, -0.202435718709502, 0.000000000000000, 2.057930200518194, 0.000000000000000, +3.120583443719949, 0.000000000000000, -0.863945271701041, 0.000000000000000, 0.906848893874630, 0.000000000000000, -1.434124930222570, 0.000000000000000, +0.754659384848783, 0.000000000000000, -5.224154442713778, 0.000000000000000, 2.330229744098967, 0.000000000000000, 1.113946320164698, 0.000000000000000, +0.523324920322840, 0.000000000000000, 1.750740911548348, 0.000000000000000, -0.899333972913577, 0.000000000000000, 0.228705845203506, 0.000000000000000, +-1.934782624767648, 0.000000000000000, -3.508386237231303, 0.000000000000000, -2.107108523073510, 0.000000000000000, 0.380587645474815, 0.000000000000000, +-0.476200877183279, 0.000000000000000, -2.172086712642198, 0.000000000000000, 1.795372535780299, 0.000000000000000, -2.100318983391055, 0.000000000000000, +-0.022571122461405, 0.000000000000000, 0.674514020010955, 0.000000000000000, -0.148872569390857, 0.000000000000000, 0.298175890592737, 0.000000000000000, +-1.134244492493590, 0.000000000000000, -3.146848422289455, 0.000000000000000, -1.357950199087602, 0.000000000000000, 0.667362732020878, 0.000000000000000, +-3.119397998316724, 0.000000000000000, -1.189341126297637, 0.000000000000000, -1.532744386856668, 0.000000000000000, -1.672972484202534, 0.000000000000000, +-2.042283373871558, 0.000000000000000, -1.479481547595924, 0.000000000000000, -0.002668662875396, 0.000000000000000, 0.262737760129546, 0.000000000000000, +2.734456080621830, 0.000000000000000, -0.671945925075102, 0.000000000000000, -3.735078262179111, 0.000000000000000, -0.161705013319883, 0.000000000000000, +0.748963512361001, 0.000000000000000, 1.128046374367600, 0.000000000000000, 0.649651335592966, 0.000000000000000, 1.880020215025867, 0.000000000000000, +-1.095632293842306, 0.000000000000000, 1.197764876160487, 0.000000000000000, 0.323646656252985, 0.000000000000000, -1.655502751114502, 0.000000000000000, +3.666399062961496, 0.000000000000000, -0.334060899735197, 0.000000000000000, -2.119056978738397, 0.000000000000000, 3.721375117275012, 0.000000000000000, +0.044874186872307, 0.000000000000000, -2.733053897593234, 0.000000000000000, 1.590700278891042, 0.000000000000000, 3.215711772781902, 0.000000000000000, +-1.792085012843801, 0.000000000000000, -0.405797188885475, 0.000000000000000, -0.628080020080892, 0.000000000000000, -1.831815840843960, 0.000000000000000, +2.973656862522834, 0.000000000000000, -0.212032655138417, 0.000000000000000, 0.372437389437234, 0.000000000000000, -1.614030579023492, 0.000000000000000, +-0.704900996358698, 0.000000000000000, 1.123700273452105, 0.000000000000000, -0.136371848130819, 0.000000000000000, 3.020284357635585, 0.000000000000000, +-0.550211350877649, 0.000000000000000, 5.101256236381711, 0.000000000000000, 3.367051512192333, 0.000000000000000, -4.385131946669234, 0.000000000000000, +-3.967303337694391, 0.000000000000000, -0.965894936640022, 0.000000000000000, 0.328366945264681, 0.000000000000000, 0.199041562924914, 0.000000000000000, +1.067681999025495, 0.000000000000000, -1.939516091697170, 0.000000000000000, -1.092980954328824, 0.000000000000000, 0.273786079368066, 0.000000000000000, +-0.040928322190265, 0.000000000000000, -0.118368078577437, 0.000000000000000, 1.766589628899997, 0.000000000000000, 1.738321311635393, 0.000000000000000, +-2.895012794321649, 0.000000000000000, 1.213521771395142, 0.000000000000000, 0.922971726633985, 0.000000000000000, 1.091516563636489, 0.000000000000000, +3.226378465469620, 0.000000000000000, 1.149169778666974, 0.000000000000000, -1.695986327709386, 0.000000000000000, -0.974803077355813, 0.000000000000000, +-4.898035507513607, 0.000000000000000, 1.622719302889447, 0.000000000000000, 0.583891313586579, 0.000000000000000, -1.677182424094957, 0.000000000000000, +-1.915633132814685, 0.000000000000000, -1.980150370851616, 0.000000000000000, 0.604538269404190, 0.000000000000000, 0.939862406149365, 0.000000000000000, +-1.266939874246416, 0.000000000000000, -1.494771249200063, 0.000000000000000, 0.278042784093988, 0.000000000000000, 0.326627416008916, 0.000000000000000, +-1.914530157643303, 0.000000000000000, 1.908947721862196, 0.000000000000000, 0.531819285694044, 0.000000000000000, 3.056856632319658, 0.000000000000000, +-0.389241827774643, 0.000000000000000, -2.418606606780420, 0.000000000000000, 0.915299238878703, 0.000000000000000, -0.098774174295283, 0.000000000000000, +-0.906199428444304, 0.000000000000000, 0.316716451217743, 0.000000000000000, -4.367700643578311, 0.000000000000000, 1.491687997515293, 0.000000000000000, +-1.962381126288365, 0.000000000000000, -0.700829196527045, 0.000000000000000, 3.028958963615630, 0.000000000000000, -2.313461067462598, 0.000000000000000, +-1.431933239886712, 0.000000000000000, -0.831153039725342, 0.000000000000000, 3.939495598250743, 0.000000000000000, 0.342974753984771, 0.000000000000000, +-2.768330763002974, 0.000000000000000, -2.744010370019008, 0.000000000000000, 3.821352685212561, 0.000000000000000, 4.551065271455856, 0.000000000000000, +3.270136437041298, 0.000000000000000, -3.188028411950982, 0.000000000000000, -0.777075012417436, 0.000000000000000, 0.097110650265216, 0.000000000000000, +1.221216137608812, 0.000000000000000, -1.325824244541822, 0.000000000000000, -2.655296734084113, 0.000000000000000, -1.074792144885704, 0.000000000000000, +2.770401584439407, 0.000000000000000, 5.240270645610543, 0.000000000000000, 0.108576672208892, 0.000000000000000, -1.209394350650142, 0.000000000000000, +1.403344353838785, 0.000000000000000, -0.299032904177277, 0.000000000000000, 4.074959450638227, 0.000000000000000, 1.718727473952107, 0.000000000000000, +-3.061349227080806, 0.000000000000000, -1.158596888541269, 0.000000000000000, 3.381858904662625, 0.000000000000000, 0.957339964054052, 0.000000000000000, +0.179900074904899, 0.000000000000000, -3.909641902506081, 0.000000000000000, 0.805717289408649, 0.000000000000000, 2.047413793928261, 0.000000000000000, +-1.273580225826614, 0.000000000000000, -2.681359186869971, 0.000000000000000, -0.721241345822093, 0.000000000000000, -1.613090681569475, 0.000000000000000, +0.463138804815955, 0.000000000000000, 0.377223507800954, 0.000000000000000, 2.046550684968141, 0.000000000000000, 0.178508732797712, 0.000000000000000, +-0.477815330358845, 0.000000000000000, 3.763355908332053, 0.000000000000000, 1.300430303035163, 0.000000000000000, -0.214625793857725, 0.000000000000000, +1.343267891864081, 0.000000000000000, -0.340007682433245, 0.000000000000000, 2.062703194680005, 0.000000000000000, 0.042032160234235, 0.000000000000000, +0.643732569732250, 0.000000000000000, -1.913502543857589, 0.000000000000000, 3.771340762937158, 0.000000000000000, 1.050024807363386, 0.000000000000000, +-4.440489488592649, 0.000000000000000, 0.444904302066643, 0.000000000000000, 2.898702265650048, 0.000000000000000, 1.953232980548558, 0.000000000000000, +2.761564952735079, 0.000000000000000, 1.963537633260397, 0.000000000000000, -2.168858472916215, 0.000000000000000, -4.116235357699841, 0.000000000000000, +4.183678271896528, 0.000000000000000, 0.600422284944681, 0.000000000000000, -0.659352647255126, 0.000000000000000, -0.993127338218109, 0.000000000000000, +-2.463571314945747, 0.000000000000000, 0.937720951545881, 0.000000000000000, -3.098957308429730, 0.000000000000000, -2.354719140045463, 0.000000000000000, +-0.417285119323949, 0.000000000000000, 2.187974075975947, 0.000000000000000, 1.101468905172585, 0.000000000000000, -3.185800678152109, 0.000000000000000, +2.357534709345083, 0.000000000000000, 0.246645606729407, 0.000000000000000, 4.440905650784504, 0.000000000000000, -2.236807716637866, 0.000000000000000, +-2.171481518317550, 0.000000000000000, -2.029571795072690, 0.000000000000000, 0.135599790431348, 0.000000000000000, -1.277965265520191, 0.000000000000000, +-1.927976233157507, 0.000000000000000, -5.434492783745394, 0.000000000000000, -2.026375829312657, 0.000000000000000, 1.009666016819321, 0.000000000000000, +0.238549782367247, 0.000000000000000, -0.516403923971309, 0.000000000000000, -0.933977817429352, 0.000000000000000, 0.155803015935614, 0.000000000000000, +-0.396194809997929, 0.000000000000000, -0.915178100253214, 0.000000000000000, 0.666329367985015, 0.000000000000000, -1.517991149945785, 0.000000000000000, +0.458266744144822, 0.000000000000000, -1.242845974381418, 0.000000000000000, 0.057914823556477, 0.000000000000000, 0.994101307476875, 0.000000000000000, +-2.387209849199325, 0.000000000000000, 0.459297048883826, 0.000000000000000, 0.227711405683905, 0.000000000000000, 0.030255073506117, 0.000000000000000, +-1.323361608181337, 0.000000000000000, -4.650244457426706, 0.000000000000000, 0.062908579526021, 0.000000000000000, 3.462831028244432, 0.000000000000000, +1.303608183314856, 0.000000000000000, -1.430415193881612, 0.000000000000000, -1.672886118942142, 0.000000000000000, 0.992890699210099, 0.000000000000000, +-0.160814531784247, 0.000000000000000, -1.238132939350430, 0.000000000000000, -0.589223271459376, 0.000000000000000, 2.326363810561534, 0.000000000000000, +-4.433789496230785, 0.000000000000000, 1.664686987538929, 0.000000000000000, -2.366128834617921, 0.000000000000000, 1.212421570743837, 0.000000000000000, +-4.847914267690055, 0.000000000000000, 0.228485221404712, 0.000000000000000, 0.466139765470957, 0.000000000000000, -1.344202776943546, 0.000000000000000, +-1.012053673330574, 0.000000000000000, -2.844980626424742, 0.000000000000000, -1.552703722026340, 0.000000000000000, -1.448830983885038, 0.000000000000000, +0.127010756753980, 0.000000000000000, -1.667188263752299, 0.000000000000000, 3.424818052085100, 0.000000000000000, 0.956291135453840, 0.000000000000000, +-3.725533331754662, 0.000000000000000, -1.584534272368832, 0.000000000000000, -1.654148210472472, 0.000000000000000, 0.701610500675698, 0.000000000000000, +0.164954538683927, 0.000000000000000, -0.739260064712987, 0.000000000000000, -2.167324026090101, 0.000000000000000, -0.310240491909496, 0.000000000000000, +-2.281790349106906, 0.000000000000000, 1.719655331305361, 0.000000000000000, -2.997005923606441, 0.000000000000000, -1.999301431556852, 0.000000000000000, +-0.292229010068828, 0.000000000000000, 1.172317994855851, 0.000000000000000, 0.196734885241533, 0.000000000000000, 2.981365193477068, 0.000000000000000, +2.637726016926352, 0.000000000000000, 1.434045125217982, 0.000000000000000, 0.883627180451827, 0.000000000000000, -1.434040761445747, 0.000000000000000, +-1.528891971086553, 0.000000000000000, -3.306913135367542, 0.000000000000000, -0.399059265470646, 0.000000000000000, -0.265674394285178, 0.000000000000000, +3.502591252855384, 0.000000000000000, 0.830301156604454, 0.000000000000000, -0.220021317046083, 0.000000000000000, -0.090553770476646, 0.000000000000000, +0.771863477047951, 0.000000000000000, 1.351209629105760, 0.000000000000000, 3.773699756201963, 0.000000000000000, 0.472600118752329, 0.000000000000000, +2.332825668012222, 0.000000000000000, 1.853747950314528, 0.000000000000000, 0.759515251766178, 0.000000000000000, 1.327112776215496, 0.000000000000000, +2.518730296237868, 0.000000000000000, 0.764450208786353, 0.000000000000000, -0.278275349491296, 0.000000000000000, -0.041559465082020, 0.000000000000000, +1.387166083167787, 0.000000000000000, 2.612996769598122, 0.000000000000000, -0.385404831721799, 0.000000000000000, 2.005630016170309, 0.000000000000000, +-0.950500047307998, 0.000000000000000, -1.166884021392492, 0.000000000000000, 1.432973552928162, 0.000000000000000, 2.540370505384567, 0.000000000000000, +-1.140505295054501, 0.000000000000000, -3.673358835201185, 0.000000000000000, -0.450691288038056, 0.000000000000000, 1.601024294408014, 0.000000000000000, +0.773213556014045, 0.000000000000000, 2.973873693246168, 0.000000000000000, -1.361548406382279, 0.000000000000000, 1.409136332424815, 0.000000000000000, +-0.963382518314713, 0.000000000000000, -2.031268227368161, 0.000000000000000, 0.983309972085586, 0.000000000000000, -3.461412488471631, 0.000000000000000, +-2.601124929406039, 0.000000000000000, -0.533896239766343, 0.000000000000000, -2.627129008866350, 0.000000000000000, 0.622111169161305, 0.000000000000000, +-1.160926365580422, 0.000000000000000, -2.406196188132628, 0.000000000000000, -1.076870362758737, 0.000000000000000, -1.791866820937175, 0.000000000000000, +-0.749453071522325, 0.000000000000000, -5.324156615990973, 0.000000000000000, -1.038698022238289, 0.000000000000000, -2.106629944730630, 0.000000000000000, +0.659295598564773, 0.000000000000000, 0.520940881580988, 0.000000000000000, -0.055649203928700, 0.000000000000000, 0.292096765423137, 0.000000000000000, +-4.663743901790872, 0.000000000000000, -0.125066503391666, 0.000000000000000, -2.452620252445380, 0.000000000000000, -0.712128227397468, 0.000000000000000, +-0.048938037970968, 0.000000000000000, -1.821520226003361, 0.000000000000000, 0.810106421304257, 0.000000000000000, -0.196636623956257, 0.000000000000000, +-0.701769836763804, 0.000000000000000, 2.460345045649201, 0.000000000000000, 3.506597671641116, 0.000000000000000, -2.711322611972225, 0.000000000000000, +-0.658079876600542, 0.000000000000000, -2.040082099646173, 0.000000000000000, 2.201668355395807, 0.000000000000000, 1.181507395879711, 0.000000000000000, +-1.640739552179682, 0.000000000000000, -1.613393726467190, 0.000000000000000, -1.156741241731352, 0.000000000000000, 2.527773464519963, 0.000000000000000, +-0.497040638009502, 0.000000000000000, -0.975817112895589, 0.000000000000000, -2.866830755546166, 0.000000000000000, 1.120214498507878, 0.000000000000000, +5.986771654661698, 0.000000000000000, 0.398219252656757, 0.000000000000000, -3.545606013198135, 0.000000000000000, 0.312398099396191, 0.000000000000000, +-2.265327979531788, 0.000000000000000, 0.792121001107366, 0.000000000000000, -3.736145137670100, 0.000000000000000, 0.762228883650802, 0.000000000000000, +2.283545661214646, 0.000000000000000, 3.780020629583529, 0.000000000000000, 3.117260228608810, 0.000000000000000, -2.011159255609613, 0.000000000000000, +0.279107700476072, 0.000000000000000, 2.003369134246936, 0.000000000000000, -1.448171234480257, 0.000000000000000, 0.584697150310140, 0.000000000000000, +0.919508663636197, 0.000000000000000, -3.071349141675388, 0.000000000000000, -1.555923649263667, 0.000000000000000, 2.232497079438850, 0.000000000000000, +-0.012662139119883, 0.000000000000000, 0.372825540734715, 0.000000000000000, 2.378543590847629, 0.000000000000000, 1.459053407813062, 0.000000000000000, +-0.967913907390927, 0.000000000000000, 1.322825200678212, 0.000000000000000, -1.033775820061824, 0.000000000000000, -1.813629552693142, 0.000000000000000, +4.794348161661486, 0.000000000000000, 0.655279811518676, 0.000000000000000, -2.224590138589720, 0.000000000000000, 0.595329481295766, 0.000000000000000, +3.364055988866225, 0.000000000000000, 1.863416422998127, 0.000000000000000, 1.930305751828105, 0.000000000000000, -0.284467053432545, 0.000000000000000, +-0.923374905878938, 0.000000000000000, 1.922988234041399, 0.000000000000000, 0.310482143432719, 0.000000000000000, 0.332122302397134, 0.000000000000000, +-1.659487472408966, 0.000000000000000, -1.865943507877961, 0.000000000000000, -0.186775297569864, 0.000000000000000, -1.700543850628361, 0.000000000000000, +0.497157959366735, 0.000000000000000, -0.471244843957418, 0.000000000000000, -0.432013753969948, 0.000000000000000, -4.000189880113231, 0.000000000000000, +-0.415335170016467, 0.000000000000000, 0.317311950972859, 0.000000000000000, 0.038393428927595, 0.000000000000000, 0.177219909465206, 0.000000000000000, +0.531650958095143, 0.000000000000000, -2.711644985175806, 0.000000000000000, 0.328744077805156, 0.000000000000000, -0.938417707547928, 0.000000000000000, +0.970379584897379, 0.000000000000000, 1.873649473917137, 0.000000000000000, 0.177938226987023, 0.000000000000000, 0.155609346302393, 0.000000000000000, +-1.276504241867208, 0.000000000000000, -0.463725075928807, 0.000000000000000, -0.064748250389500, 0.000000000000000, -1.725568534062385, 0.000000000000000, +-0.139066584804067, 0.000000000000000, 1.975514554117767, 0.000000000000000, -0.807063199499478, 0.000000000000000, -0.326926659682788, 0.000000000000000, +1.445727032487938, 0.000000000000000, -0.597151107739100, 0.000000000000000, 2.732557531709386, 0.000000000000000, -2.907130934109188, 0.000000000000000, +-1.461264832679981, 0.000000000000000, -1.708588604968163, 0.000000000000000, 3.652851925431363, 0.000000000000000, 0.682050868282879, 0.000000000000000, +-0.281312579963294, 0.000000000000000, 0.554966483307825, 0.000000000000000, -0.981341739340932, 0.000000000000000, 1.279543331141603, 0.000000000000000, +0.036589747826856, 0.000000000000000, 2.312073745896073, 0.000000000000000, 1.754682200732425, 0.000000000000000, -0.957515875428627, 0.000000000000000, +-0.833596942819695, 0.000000000000000, 0.437054368791033, 0.000000000000000, -0.898819399360279, 0.000000000000000, -0.296050580896839, 0.000000000000000, +-0.785144257649601, 0.000000000000000, -2.541503089003311, 0.000000000000000, 2.225075846758761, 0.000000000000000, -1.587290487902002, 0.000000000000000, +-1.421404172056462, 0.000000000000000, -3.015149802293631, 0.000000000000000, 1.780874288867949, 0.000000000000000, -0.865812740882613, 0.000000000000000, +-2.845327531197112, 0.000000000000000, 1.445225867774367, 0.000000000000000, 2.183733236584647, 0.000000000000000, 1.163371072749080, 0.000000000000000, +0.883547693520409, 0.000000000000000, -1.224093106684675, 0.000000000000000, -1.854501116331044, 0.000000000000000, 1.783082089255796, 0.000000000000000, +2.301508706196191, 0.000000000000000, -0.539901944139077, 0.000000000000000, 1.962315832319967, 0.000000000000000, -0.060709041870503, 0.000000000000000, +-1.353139923300238, 0.000000000000000, -1.482887537805234, 0.000000000000000, 1.273732601967176, 0.000000000000000, -3.456609915556321, 0.000000000000000, +-3.752320586540873, 0.000000000000000, 3.536356614978951, 0.000000000000000, 0.206035952043233, 0.000000000000000, 5.933966913773842, 0.000000000000000, +-0.486633898075490, 0.000000000000000, -0.329595089863342, 0.000000000000000, 1.496414153905337, 0.000000000000000, 0.137868749388880, 0.000000000000000, +-0.437192030996792, 0.000000000000000, 2.682750615210656, 0.000000000000000, -2.440234892848570, 0.000000000000000, 1.433910252426186, 0.000000000000000, +-0.415051506104074, 0.000000000000000, 1.982003013708649, 0.000000000000000, 1.345796609972435, 0.000000000000000, -2.335949513404370, 0.000000000000000, +1.065988867433025, 0.000000000000000, 2.741844905000464, 0.000000000000000, -1.754047930934362, 0.000000000000000, 0.229252730015575, 0.000000000000000, +-0.679791016408669, 0.000000000000000, -2.274097820043743, 0.000000000000000, 0.149802252231876, 0.000000000000000, -0.139697151364830, 0.000000000000000, +-2.773367420505435, 0.000000000000000, -4.403400246165611, 0.000000000000000, -1.468974515184135, 0.000000000000000, 0.664990623095844, 0.000000000000000, +-3.446979775557143, 0.000000000000000, 1.850006428987618, 0.000000000000000, -1.550866747921936, 0.000000000000000, -3.632874882935257, 0.000000000000000, +0.828039662992464, 0.000000000000000, 2.794055182632816, 0.000000000000000, -0.593995716682633, 0.000000000000000, 0.142788156054200, 0.000000000000000, +0.552461945119668, 0.000000000000000, 0.842127129738758, 0.000000000000000, 1.414335509600077, 0.000000000000000, -0.311559241382430, 0.000000000000000, +1.510590844695250, 0.000000000000000, 1.692217183824300, 0.000000000000000, 0.613760285711957, 0.000000000000000, 0.065233463207770, 0.000000000000000, +-2.571912893711505, 0.000000000000000, -1.707001531141341, 0.000000000000000, 0.673884968382041, 0.000000000000000, 0.889863883420103, 0.000000000000000, +-2.395635435233346, 0.000000000000000, 1.129247296359819, 0.000000000000000, 0.569074704779735, 0.000000000000000, 6.139436017480722, 0.000000000000000, +0.822158309259017, 0.000000000000000, -3.289872016222589, 0.000000000000000, 0.417612988384414, 0.000000000000000, 1.493982103868165, 0.000000000000000, +-0.415353391377005, 0.000000000000000, 0.288670764933155, 0.000000000000000, -1.895650228872272, 0.000000000000000, -0.139631694475020, 0.000000000000000, +1.445103299005436, 0.000000000000000, 2.877182243683429, 0.000000000000000, 1.192428490172580, 0.000000000000000, -5.964591921763842, 0.000000000000000, +0.570859795882959, 0.000000000000000, 2.328333316356666, 0.000000000000000, 0.333755014930026, 0.000000000000000, 1.221901577771909, 0.000000000000000, +0.943358697415568, 0.000000000000000, 2.793063983613067, 0.000000000000000, 3.163005066073616, 0.000000000000000, 2.098300664513867, 0.000000000000000, +-3.915313164333447, 0.000000000000000, -2.475766769064539, 0.000000000000000, 1.720472044894277, 0.000000000000000, -1.273591949275665, 0.000000000000000, +-1.213451272938616, 0.000000000000000, 0.697439404325690, 0.000000000000000, -0.309902287574293, 0.000000000000000, 2.622575852162781, 0.000000000000000, +-2.075881936219060, 0.000000000000000, 0.777847545691770, 0.000000000000000, -3.967947986440650, 0.000000000000000, -3.066503371806472, 0.000000000000000, +1.193780625937845, 0.000000000000000, 0.214246579281311, 0.000000000000000, -2.610681491162162, 0.000000000000000, -1.261224183972745, 0.000000000000000, +-1.165071748544285, 0.000000000000000, -1.116548474834374, 0.000000000000000, 0.847202164846982, 0.000000000000000, -3.474301529532390, 0.000000000000000, +0.020799541946476, 0.000000000000000, -3.868995473288166, 0.000000000000000, 1.757979409638067, 0.000000000000000, 0.868115130183109, 0.000000000000000, +0.910167436737958, 0.000000000000000, -1.878855115563720, 0.000000000000000, 1.710357104174161, 0.000000000000000, -1.468933980990902, 0.000000000000000, +1.799544171601169, 0.000000000000000, -4.922332880027887, 0.000000000000000, 0.219424548939720, 0.000000000000000, -0.971671113451924, 0.000000000000000, +-0.940533475616266, 0.000000000000000, 0.122510114412152, 0.000000000000000, -1.373686254916911, 0.000000000000000, 1.760348103896323, 0.000000000000000, +0.391745067829643, 0.000000000000000, 2.521958505327354, 0.000000000000000, -1.300693516405092, 0.000000000000000, -0.538251788309178, 0.000000000000000, +0.797184135810173, 0.000000000000000, 2.908800548982588, 0.000000000000000, 1.590902251655215, 0.000000000000000, -1.070323714487264, 0.000000000000000, +-3.349764443340999, 0.000000000000000, -1.190563529731447, 0.000000000000000, 1.363369471291963, 0.000000000000000, -1.814270299924576, 0.000000000000000, +-0.023381588315711, 0.000000000000000, 1.719182048679569, 0.000000000000000, 0.839917213252626, 0.000000000000000, 1.006099633839122, 0.000000000000000, +0.812462674381527, 0.000000000000000, 1.755814336346739, 0.000000000000000, 2.546848681206319, 0.000000000000000, -1.555300208869455, 0.000000000000000, +1.017053811631167, 0.000000000000000, 0.996591039170903, 0.000000000000000, -1.228047247924881, 0.000000000000000, 4.809462271463009, 0.000000000000000, +2.318113116151685, 0.000000000000000, -1.206932520679733, 0.000000000000000, 1.273757685623312, 0.000000000000000, 0.724335352481802, 0.000000000000000, +1.519876652073198, 0.000000000000000, -2.749670314714158, 0.000000000000000, 3.424042481847581, 0.000000000000000, -3.714668360421517, 0.000000000000000, +1.612834197004014, 0.000000000000000, -2.038234723985566, 0.000000000000000, 1.470938786562152, 0.000000000000000, 2.111634918450302, 0.000000000000000, +1.030376670151787, 0.000000000000000, -0.420877189003829, 0.000000000000000, -1.502024800532894, 0.000000000000000, 0.452310749163804, 0.000000000000000, +-1.606059382300987, 0.000000000000000, -4.006159967834147, 0.000000000000000, -2.152801208196508, 0.000000000000000, 1.671674089372579, 0.000000000000000, +1.714536333564101, 0.000000000000000, -1.011518543005344, 0.000000000000000, -0.576410282180584, 0.000000000000000, 0.733689809480836, 0.000000000000000, +1.004245602717974, 0.000000000000000, 1.010090391888449, 0.000000000000000, 3.811459513385621, 0.000000000000000, -5.230621089271954, 0.000000000000000, +0.678044861034399, 0.000000000000000, 1.255935859598107, 0.000000000000000, 1.674521701615288, 0.000000000000000, -1.656695216761705, 0.000000000000000, +1.169286028869693, 0.000000000000000, 0.524915416191998, 0.000000000000000, 2.397642885039520, 0.000000000000000, 2.108711400616072, 0.000000000000000, +2.037618211018084, 0.000000000000000, -0.623664553406925, 0.000000000000000, 2.984106170984409, 0.000000000000000, 1.132182737400932, 0.000000000000000, +-2.859274340352130, 0.000000000000000, -0.975550071398723, 0.000000000000000, -1.359935119997407, 0.000000000000000, -2.963308211050121, 0.000000000000000, +-0.228726662781163, 0.000000000000000, -1.411110379682043, 0.000000000000000, 0.741553355734225, 0.000000000000000, 0.497554254758309, 0.000000000000000, +2.371907950598855, 0.000000000000000, 1.063465168988748, 0.000000000000000, -0.641082692081488, 0.000000000000000, -0.855439878540726, 0.000000000000000, +0.578321738578726, 0.000000000000000, 3.005809768796194, 0.000000000000000, 1.961458699064065, 0.000000000000000, -3.206261663772745, 0.000000000000000, +-0.364431989095434, 0.000000000000000, -0.263182496622273, 0.000000000000000, 1.843464680631139, 0.000000000000000, -0.419107530229249, 0.000000000000000, +1.662335873298487, 0.000000000000000, -0.853687563304005, 0.000000000000000, -2.584133404357169, 0.000000000000000, 3.466839568922895, 0.000000000000000, +0.881671345091973, 0.000000000000000, 0.454620014206908, 0.000000000000000, -1.737245187402739, 0.000000000000000, 2.162713238369243, 0.000000000000000, +-3.868539002714486, 0.000000000000000, 2.014114855933826, 0.000000000000000, -0.703233831811006, 0.000000000000000, -3.410319935997574, 0.000000000000000, +-1.851235811006584, 0.000000000000000, 0.909783907894036, 0.000000000000000, 0.091884002136728, 0.000000000000000, -2.688294201131650, 0.000000000000000, +-0.906134178460955, 0.000000000000000, 3.475054609035133, 0.000000000000000, -0.573927964170323, 0.000000000000000, -0.429542937515399, 0.000000000000000, +0.991348618739939, 0.000000000000000, 1.974804904926325, 0.000000000000000, 0.975783450796698, 0.000000000000000, -3.057119549071503, 0.000000000000000, +-3.899429237481194, 0.000000000000000, 0.362439009175350, 0.000000000000000, -1.124461670265618, 0.000000000000000, 1.806000360163583, 0.000000000000000, +-2.768333362600288, 0.000000000000000, 0.244387897900379, 0.000000000000000, 0.908767296720926, 0.000000000000000, 1.254669374391882, 0.000000000000000, +-1.420441929463686, 0.000000000000000, -0.875658895966293, 0.000000000000000, 0.183824603376167, 0.000000000000000, -3.361653917011686, 0.000000000000000, +-0.796615630227952, 0.000000000000000, -1.660226542658673, 0.000000000000000, 1.654439358307226, 0.000000000000000, 2.782812946709771, 0.000000000000000, +1.418064412811531, 0.000000000000000, -0.819645647243761, 0.000000000000000, 0.807724772592699, 0.000000000000000, -0.941967976379298, 0.000000000000000, +-2.312768306047469, 0.000000000000000, 0.872426936477443, 0.000000000000000, 0.919528961530845, 0.000000000000000, -2.084904575264847, 0.000000000000000, +-1.972464868459322, 0.000000000000000, -1.050687203338466, 0.000000000000000, 1.659579707007902, 0.000000000000000, -1.820640014705855, 0.000000000000000, +-1.195078061671045, 0.000000000000000, -1.639773173762048, 0.000000000000000, 1.616744338157063, 0.000000000000000, 4.019216096811563, 0.000000000000000, +3.461021102549681, 0.000000000000000, 1.642352734361484, 0.000000000000000, -0.046354693720813, 0.000000000000000, -0.041936252359677, 0.000000000000000, +-2.393307519480551, 0.000000000000000, -0.341471634615121, 0.000000000000000, -0.392073595257017, 0.000000000000000, -0.219299018372730, 0.000000000000000, +-2.016391579662071, 0.000000000000000, -0.653096251969787, 0.000000000000000, 1.466353155666821, 0.000000000000000, -2.872058864320412, 0.000000000000000, +-2.157180779503830, 0.000000000000000, 0.723257479841560, 0.000000000000000, 3.769951308104384, 0.000000000000000, -1.923392042420024, 0.000000000000000, +0.644899359942840, 0.000000000000000, -2.090226891621437, 0.000000000000000, -0.277043982890403, 0.000000000000000, -0.528271428321112, 0.000000000000000, +2.518120645960652, 0.000000000000000, 1.040820431111488, 0.000000000000000, -4.560583754742486, 0.000000000000000, -0.226899614918836, 0.000000000000000, +1.713331231108959, 0.000000000000000, -3.293941019163642, 0.000000000000000, -1.113331444648290, 0.000000000000000, -1.032308423149906, 0.000000000000000, +1.593774272982443, 0.000000000000000, -1.246840475090529, 0.000000000000000, -0.190344684920137, 0.000000000000000, -1.719386356896355, 0.000000000000000, +-2.827721754659679, 0.000000000000000, -0.092438285279020, 0.000000000000000, -0.565844430675246, 0.000000000000000, -1.077916121691716, 0.000000000000000, +-1.208665809504693, 0.000000000000000, -2.996014266381254, 0.000000000000000, 2.888573323402423, 0.000000000000000, 2.829507048720695, 0.000000000000000, +-0.859177034120755, 0.000000000000000, -1.969302377743254, 0.000000000000000, 0.777437674525362, 0.000000000000000, -0.124910190157646, 0.000000000000000, +0.129875493115290, 0.000000000000000, -4.192139262163992, 0.000000000000000, 3.023496047962126, 0.000000000000000, 1.149775163736637, 0.000000000000000, +2.038151304801731, 0.000000000000000, 3.016122489841263, 0.000000000000000, -4.829481812137012, 0.000000000000000, -1.668436615909279, 0.000000000000000, +0.958586784636918, 0.000000000000000, 1.550652410058678, 0.000000000000000, -1.456305257976716, 0.000000000000000, -0.079588392344731, 0.000000000000000, +-2.453213599392345, 0.000000000000000, 0.296795909127105, 0.000000000000000, -0.253426616607643, 0.000000000000000, 1.418937160028195, 0.000000000000000, +-1.672949529066915, 0.000000000000000, -1.620990298572947, 0.000000000000000, -1.085103073196045, 0.000000000000000, 0.738606361195386, 0.000000000000000, +-2.097831202853255, 0.000000000000000, 2.711952282071310, 0.000000000000000, 1.498539238246888, 0.000000000000000, 1.317457282535915, 0.000000000000000, +-0.302765938349717, 0.000000000000000, -0.044623707947201, 0.000000000000000, 2.337405215062395, 0.000000000000000, -3.980689173859100, 0.000000000000000, + + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c new file mode 100644 index 0000000..c9fc8c4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c @@ -0,0 +1,167 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fft_bin_example_f32.c +* +* Description: Example code demonstrating calculation of Max energy bin of +* frequency domain of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FrequencyBin Frequency Bin Example + * + * \par Description + * \par + * Demonstrates the calculation of the maximum energy bin in the frequency + * domain of the input signal with the use of Complex FFT, Complex + * Magnitude, and Maximum functions. + * + * \par Algorithm: + * \par + * The input test signal contains a 10 kHz signal with uniformly distributed white noise. + * Calculating the FFT of the input signal will give us the maximum energy of the + * bin corresponding to the input frequency of 10 kHz. + * + * \par Block Diagram: + * \image html FFTBin.gif "Block Diagram" + * \par + * The figure below shows the time domain signal of 10 kHz signal with + * uniformly distributed white noise, and the next figure shows the input + * in the frequency domain. The bin with maximum energy corresponds to 10 kHz signal. + * \par + * \image html FFTBinInput.gif "Input signal in Time domain" + * \image html FFTBinOutput.gif "Input signal in Frequency domain" + * + * \par Variables Description: + * \par + * \li \c testInput_f32_10khz points to the input data + * \li \c testOutput points to the output data + * \li \c fftSize length of FFT + * \li \c ifftFlag flag for the selection of CFFT/CIFFT + * \li \c doBitReverse Flag for selection of normal order or bit reversed order + * \li \c refIndex reference index value at which maximum energy of bin ocuurs + * \li \c testIndex calculated index value at which maximum energy of bin ocuurs + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cfft_f32() + * - arm_cmplx_mag_f32() + * - arm_max_f32() + * + * Refer + * \link arm_fft_bin_example_f32.c \endlink + * + */ + + +/** \example arm_fft_bin_example_f32.c + */ + + +#include "arm_math.h" +#include "arm_const_structs.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define TEST_LENGTH_SAMPLES 2048 + +/* ------------------------------------------------------------------- +* External Input and Output buffer Declarations for FFT Bin Example +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32_10khz[TEST_LENGTH_SAMPLES]; +static float32_t testOutput[TEST_LENGTH_SAMPLES/2]; + +/* ------------------------------------------------------------------ +* Global variables for FFT Bin Example +* ------------------------------------------------------------------- */ +uint32_t fftSize = 1024; +uint32_t ifftFlag = 0; +uint32_t doBitReverse = 1; +arm_cfft_instance_f32 varInstCfftF32; + +/* Reference index at which max energy of bin ocuurs */ +uint32_t refIndex = 213, testIndex = 0; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_status status; + float32_t maxValue; + + status = ARM_MATH_SUCCESS; + + status=arm_cfft_init_f32(&varInstCfftF32,fftSize); + + /* Process the data through the CFFT/CIFFT module */ + arm_cfft_f32(&varInstCfftF32, testInput_f32_10khz, ifftFlag, doBitReverse); + + /* Process the data through the Complex Magnitude Module for + calculating the magnitude at each bin */ + arm_cmplx_mag_f32(testInput_f32_10khz, testOutput, fftSize); + + /* Calculates maxValue and returns corresponding BIN value */ + arm_max_f32(testOutput, fftSize, &maxValue, &testIndex); + + status = (testIndex != refIndex) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt new file mode 100644 index 0000000..06f68a2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_fir_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt new file mode 100644 index 0000000..bf85044 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_fir_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_fir_example) + + +include(config) +configApp(arm_fir_example ${ROOT}) + +target_sources(arm_fir_example PRIVATE arm_fir_data.c math_helper.c arm_fir_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_fir_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c new file mode 100644 index 0000000..283a25e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_fir_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input signal contains 1000Hz + 15000 Hz +** ------------------------------------------------------------------- */ + +float32_t testInput_f32_1kHz_15kHz[320] = +{ ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, +-0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, ++0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +-0.8660254038f, -0.4619397663f, -1.3194792169f, -1.1827865776f, -0.5000000000f, -1.1827865776f, -1.3194792169f, -0.4619397663f, +-0.8660254038f, -1.2552931065f, -0.3535533906f, -0.4174197128f, -1.0000000000f, -0.1913417162f, +0.0947343455f, -0.5924659585f, +-0.0000000000f, +0.5924659585f, -0.0947343455f, +0.1913417162f, +1.0000000000f, +0.4174197128f, +0.3535533906f, +1.2552931065f, ++0.8660254038f, +0.4619397663f, +1.3194792169f, +1.1827865776f, +0.5000000000f, +1.1827865776f, +1.3194792169f, +0.4619397663f, ++0.8660254038f, +1.2552931065f, +0.3535533906f, +0.4174197128f, +1.0000000000f, +0.1913417162f, -0.0947343455f, +0.5924659585f, ++0.0000000000f, -0.5924659585f, +0.0947343455f, -0.1913417162f, -1.0000000000f, -0.4174197128f, -0.3535533906f, -1.2552931065f, +}; + +float32_t refOutput[320] = +{ ++0.0000000000f, -0.0010797829f, -0.0007681386f, -0.0001982932f, +0.0000644313f, +0.0020854271f, +0.0036891871f, +0.0015855941f, +-0.0026280805f, -0.0075907658f, -0.0119390538f, -0.0086665968f, +0.0088981202f, +0.0430539279f, +0.0974468742f, +0.1740405600f, ++0.2681416601f, +0.3747720089f, +0.4893362230f, +0.6024154672f, +0.7058740791f, +0.7968348987f, +0.8715901940f, +0.9277881093f, ++0.9682182661f, +0.9934674267f, +1.0012052245f, +0.9925859371f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, -0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, -0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f, ++0.7085021596f, +0.6100062330f, +0.5012752767f, +0.3834386057f, +0.2592435399f, +0.1309866321f, +0.0000000000f, -0.1309866321f, +-0.2592435399f, -0.3834386057f, -0.5012752767f, -0.6100062330f, -0.7085021596f, -0.7952493046f, -0.8679010068f, -0.9257026822f, +-0.9681538347f, -0.9936657199f, -1.0019733630f, -0.9936657199f, -0.9681538347f, -0.9257026822f, -0.8679010068f, -0.7952493046f, +-0.7085021596f, -0.6100062330f, -0.5012752767f, -0.3834386057f, -0.2592435399f, -0.1309866321f, +0.0000000000f, +0.1309866321f, ++0.2592435399f, +0.3834386057f, +0.5012752767f, +0.6100062330f, +0.7085021596f, +0.7952493046f, +0.8679010068f, +0.9257026822f, ++0.9681538347f, +0.9936657199f, +1.0019733630f, +0.9936657199f, +0.9681538347f, +0.9257026822f, +0.8679010068f, +0.7952493046f +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c new file mode 100644 index 0000000..f28359f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library + * Title: arm_fir_example_f32.c + * + * Description: Example code demonstrating how an FIR filter can be used + * as a low pass filter. + * + * Target Processor: Cortex-M4/Cortex-M3 + * +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup FIRLPF FIR Lowpass Filter Example + * + * \par Description: + * \par + * Removes high frequency signal components from the input using an FIR lowpass filter. + * The example demonstrates how to configure an FIR filter and then pass data through + * it in a block-by-block fashion. + * \image html FIRLPF_signalflow.gif + * + * \par Algorithm: + * \par + * The input signal is a sum of two sine waves: 1 kHz and 15 kHz. + * This is processed by an FIR lowpass filter with cutoff frequency 6 kHz. + * The lowpass filter eliminates the 15 kHz signal leaving only the 1 kHz sine wave at the output. + * \par + * The lowpass filter was designed using MATLAB with a sample rate of 48 kHz and + * a length of 29 points. + * The MATLAB code to generate the filter coefficients is shown below: + * 
+ *     h = fir1(28, 6/24);
+ *
+ * The first argument is the "order" of the filter and is always one less than the desired length. + * The second argument is the normalized cutoff frequency. This is in the range 0 (DC) to 1.0 (Nyquist). + * A 6 kHz cutoff with a Nyquist frequency of 24 kHz lies at a normalized frequency of 6/24 = 0.25. + * The CMSIS FIR filter function requires the coefficients to be in time reversed order. + * 
+ *     fliplr(h)
+ *
+ * The resulting filter coefficients and are shown below. + * Note that the filter is symmetric (a property of linear phase FIR filters) + * and the point of symmetry is sample 14. Thus the filter will have a delay of + * 14 samples for all frequencies. + * \par + * \image html FIRLPF_coeffs.gif + * \par + * The frequency response of the filter is shown next. + * The passband gain of the filter is 1.0 and it reaches 0.5 at the cutoff frequency 6 kHz. + * \par + * \image html FIRLPF_response.gif + * \par + * The input signal is shown below. + * The left hand side shows the signal in the time domain while the right hand side is a frequency domain representation. + * The two sine wave components can be clearly seen. + * \par + * \image html FIRLPF_input.gif + * \par + * The output of the filter is shown below. The 15 kHz component has been eliminated. + * \par + * \image html FIRLPF_output.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32_1kHz_15kHz points to the input data + * \li \c refOutput points to the reference output data + * \li \c testOutput points to the test output data + * \li \c firStateF32 points to state buffer + * \li \c firCoeffs32 points to coefficient buffer + * \li \c blockSize number of samples processed at a time + * \li \c numBlocks number of frames + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fir_init_f32() + * - arm_fir_f32() + * + * Refer + * \link arm_fir_example_f32.c \endlink + * + */ + + +/** \example arm_fir_example_f32.c + */ + +/* ---------------------------------------------------------------------- +** Include Files +** ------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + + +/* ---------------------------------------------------------------------- +** Macro Defines +** ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 320 +/* + +This SNR is a bit small. Need to understand why +this example is not giving better SNR ... + +*/ +#define SNR_THRESHOLD_F32 75.0f +#define BLOCK_SIZE 32 + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +/* Must be a multiple of 16 */ +#define NUM_TAPS_ARRAY_SIZE 32 +#else +#define NUM_TAPS_ARRAY_SIZE 29 +#endif + +#define NUM_TAPS 29 + +/* ------------------------------------------------------------------- + * The input signal and reference output (computed with MATLAB) + * are defined externally in arm_fir_lpf_data.c. + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32_1kHz_15kHz[TEST_LENGTH_SAMPLES]; +extern float32_t refOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare Test output buffer + * ------------------------------------------------------------------- */ + +static float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/* ------------------------------------------------------------------- + * Declare State buffer of size (numTaps + blockSize - 1) + * ------------------------------------------------------------------- */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +static float32_t firStateF32[2 * BLOCK_SIZE + NUM_TAPS - 1]; +#else +static float32_t firStateF32[BLOCK_SIZE + NUM_TAPS - 1]; +#endif + +/* ---------------------------------------------------------------------- +** FIR Coefficients buffer generated using fir1() MATLAB function. +** fir1(28, 6/24) +** ------------------------------------------------------------------- */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +const float32_t firCoeffs32[NUM_TAPS_ARRAY_SIZE] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f, 0.0f,0.0f,0.0f +}; +#else +const float32_t firCoeffs32[NUM_TAPS_ARRAY_SIZE] = { + -0.0018225230f, -0.0015879294f, +0.0000000000f, +0.0036977508f, +0.0080754303f, +0.0085302217f, -0.0000000000f, -0.0173976984f, + -0.0341458607f, -0.0333591565f, +0.0000000000f, +0.0676308395f, +0.1522061835f, +0.2229246956f, +0.2504960933f, +0.2229246956f, + +0.1522061835f, +0.0676308395f, +0.0000000000f, -0.0333591565f, -0.0341458607f, -0.0173976984f, -0.0000000000f, +0.0085302217f, + +0.0080754303f, +0.0036977508f, +0.0000000000f, -0.0015879294f, -0.0018225230f +}; +#endif + +/* ------------------------------------------------------------------ + * Global variables for FIR LPF Example + * ------------------------------------------------------------------- */ + +uint32_t blockSize = BLOCK_SIZE; +uint32_t numBlocks = TEST_LENGTH_SAMPLES/BLOCK_SIZE; + +float32_t snr; + +/* ---------------------------------------------------------------------- + * FIR LPF Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_fir_instance_f32 S; + arm_status status; + float32_t *inputF32, *outputF32; + + /* Initialize input and output buffer pointers */ + inputF32 = &testInput_f32_1kHz_15kHz[0]; + outputF32 = &testOutput[0]; + + /* Call FIR init function to initialize the instance structure. */ + arm_fir_init_f32(&S, NUM_TAPS, (float32_t *)&firCoeffs32[0], &firStateF32[0], blockSize); + + /* ---------------------------------------------------------------------- + ** Call the FIR process function for every blockSize samples + ** ------------------------------------------------------------------- */ + + for(i=0; i < numBlocks; i++) + { + arm_fir_f32(&S, inputF32 + (i * blockSize), outputF32 + (i * blockSize), blockSize); + } + + /* ---------------------------------------------------------------------- + ** Compare the generated output against the reference output computed + ** in MATLAB. + ** ------------------------------------------------------------------- */ + + snr = arm_snr_f32(&refOutput[0], &testOutput[0], TEST_LENGTH_SAMPLES); + + status = (snr < SNR_THRESHOLD_F32) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } +} + +/** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c new file mode 100644 index 0000000..950bf42 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c @@ -0,0 +1,474 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt new file mode 100644 index 0000000..8c97744 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_graphic_equalizer_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt new file mode 100644 index 0000000..9cf05e1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_graphic_equalizer_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_graphic_equalizer_example) + + +include(config) +configApp(arm_graphic_equalizer_example ${ROOT}) + +target_sources(arm_graphic_equalizer_example PRIVATE math_helper.c arm_graphic_equalizer_data.c arm_graphic_equalizer_example_q31.c) + +### Sources and libs + +target_link_libraries(arm_graphic_equalizer_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c new file mode 100644 index 0000000..ffb0ff3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_data.c +* +* Description: Data file used for example code +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +#include "arm_math.h" + +float32_t testRefOutput_f32[320] = { + +0.000000000000000000, 0.001898396760225296, 0.004215449094772339, 0.007432077080011368, 0.010948467999696732, 0.015026375651359558, 0.019191544502973557, 0.023574527353048325, +0.027919445186853409, 0.032277785241603851, 0.036551639437675476, 0.040732793509960175, 0.044799156486988068, 0.048710610717535019, 0.052476800978183746, 0.056059073656797409, +0.059482168406248093, 0.062726479023694992, 0.065821025520563126, 0.068763464689254761, 0.071577839553356171, 0.074270240962505341, 0.076856281608343124, 0.079344697296619415, +0.081745062023401260, 0.084067162126302719, 0.086318407207727432, 0.088509257882833481, 0.090647127479314804, 0.092742368578910828, 0.094802625477313995, 0.096837285906076431, +0.098853722214698792, 0.100859899073839190, 0.102862443774938580, 0.104867763817310330, 0.106881409883499150, 0.108908228576183320, 0.110952425748109820, 0.113017357885837550, +0.115105822682380680, 0.117219865322113040, 0.119361080229282380, 0.121530555188655850, 0.123729091137647630, 0.125957202166318890, 0.128215309232473370, 0.130503740161657330, +0.132822841405868530, 0.135173004120588300, 0.137554679065942760, 0.139968376606702800, 0.142414685338735580, 0.144894234836101530, 0.147407654672861100, 0.149955596774816510, +0.152538605034351350, 0.155157200992107390, 0.157811731100082400, 0.160502441227436070, 0.163229387253522870, 0.165992442518472670, 0.168791320174932480, 0.171625509858131410, +0.174494370818138120, 0.177397061139345170, 0.180332608520984650, 0.183299910277128220, 0.186297744512557980, 0.189324837177991870, 0.192379791289567950, 0.195461250841617580, +0.198567759245634080, 0.201697919517755510, 0.204850304871797560, 0.208023533225059510, 0.211216274648904800, 0.214427210390567780, 0.217655111104249950, 0.220898788422346120, +0.224157124757766720, 0.227429077029228210, 0.230713658034801480, 0.234009962528944020, 0.237317133694887160, 0.240634419023990630, 0.243961080908775330, 0.247296508401632310, +0.250640105456113820, 0.253991369158029560, 0.257349837571382520, 0.260715119540691380, 0.264086868613958360, 0.267464816570281980, 0.270848698914051060, 0.274238351732492450, +0.277633611112833020, 0.281034380197525020, 0.284440591931343080, 0.287852220237255100, 0.291269283741712570, 0.294691801071166990, 0.298119872808456420, 0.301553562283515930, +0.304993014782667160, 0.308438356965780260, 0.311889752745628360, 0.315347377210855480, 0.318811416625976560, 0.322282072156667710, 0.325759567320346830, 0.329244095832109450, +0.332735907286405560, 0.336235217750072480, 0.339742250740528110, 0.343257248401641850, 0.346780419349670410, 0.350311983376741410, 0.353852160274982450, 0.357401121407747270, +0.360959105193614960, 0.364526227116584780, 0.368102725595235820, 0.371688675135374070, 0.375284302979707720, 0.378889638930559160, 0.382504884153604510, 0.386130042374134060, +0.389765247702598570, 0.393410529941320420, 0.397065933793783190, 0.400731507688760760, 0.404407206922769550, 0.408093083649873730, 0.411789052188396450, 0.415495119988918300, +0.419211201369762420, 0.422937240451574330, 0.426673140376806260, 0.430418811738491060, 0.434174135327339170, 0.437938995659351350, 0.441713258624076840, 0.445496778935194020, +0.449289388954639430, 0.453090950846672060, 0.456901267170906070, 0.460720170289278030, 0.464547459036111830, 0.468382950872182850, 0.472226426005363460, 0.476077698171138760, +0.479936532676219940, 0.483802750706672670, 0.487676106393337250, 0.491556398570537570, 0.495443399995565410, 0.499336875975131990, 0.503236617892980580, 0.507142387330532070, +0.511053957045078280, 0.514971107244491580, 0.518893606960773470, 0.522821225225925450, 0.526753749698400500, 0.530690938234329220, 0.534632585942745210, 0.538578454405069350, +0.542528338730335240, 0.546481993049383160, 0.550439231097698210, 0.554399792104959490, 0.558363504707813260, 0.562330115586519240, 0.566299438476562500, 0.570271246135234830, +0.574245333671569820, 0.578221492469310760, 0.582199502736330030, 0.586179181933403020, 0.590160276740789410, 0.594142623245716090, 0.598125983029603960, 0.602110169827938080, +0.606094967573881150, 0.610080175101757050, 0.614065583795309070, 0.618050977587699890, 0.622036151587963100, 0.626020893454551700, 0.630004994571208950, 0.633988231420516970, +0.637970402836799620, 0.641951277852058410, 0.645930647850036620, 0.649908289313316350, 0.653883971273899080, 0.657857488840818410, 0.661828581243753430, 0.665797054767608640, +0.669762641191482540, 0.673725124448537830, 0.677684243768453600, 0.681639779359102250, 0.685591462999582290, 0.689539063721895220, 0.693482317030429840, 0.697420965880155560, +0.701354760676622390, 0.705283410847187040, 0.709206689149141310, 0.713124278932809830, 0.717035952955484390, 0.720941375941038130, 0.724840316921472550, 0.728732451796531680, +0.732617516070604320, 0.736495196819305420, 0.740365199744701390, 0.744227230548858640, 0.748080968856811520, 0.751926124095916750, 0.755762357264757160, 0.759589381515979770, +0.763406842947006230, 0.767214450985193250, 0.771011855453252790, 0.774798732250928880, 0.778574761003255840, 0.782339565455913540, 0.786092851310968400, 0.789834223687648770, +0.793563373386859890, 0.797279909253120420, 0.800983514636754990, 0.804673787206411360, 0.808350402861833570, 0.812012966722249980, 0.815661124885082240, 0.819294504821300510, +0.822912722826004030, 0.826515413820743560, 0.830102190375328060, 0.833672653883695600, 0.837226435542106630, 0.840763118118047710, 0.844282336533069610, 0.847783654928207400, +0.851266715675592420, 0.854731071740388870, 0.858176350593566890, 0.861602116376161580, 0.865007970482110980, 0.868393491953611370, 0.871758259832859040, 0.875101849436759950, +0.878423850983381270, 0.881723806262016300, 0.885001312941312790, 0.888255912810564040, 0.891487173736095430, 0.894694659858942030, 0.897877920418977740, 0.901036512106657030, +0.904169965535402300, 0.907277844846248630, 0.910359673202037810, 0.913415014743804930, 0.916443370282649990, 0.919444311410188670, 0.922417331486940380, 0.925361987203359600, +0.928277771919965740, 0.931164238601922990, 0.934020876884460450, 0.936847217381000520, 0.939642757177352910, 0.942407000809907910, 0.945139460265636440, 0.947839632630348210, +0.950507018715143200, 0.953141096979379650, 0.955741371959447860, 0.958307322114706040, 0.960838429629802700, 0.963334184139966960, 0.965794049203395840, 0.968217510730028150, +0.970604017376899720, 0.972953058779239650, 0.975264083594083790, 0.977536566555500030, 0.979769956320524220, 0.981963708996772770, 0.984117280691862110, 0.986230112612247470, +0.988301653414964680, 0.990331344306468960, 0.992318630218505860, 0.994262944906950000, 0.996163722127676010, 0.998020399361848830, 0.999832402914762500, 1.001599155366420700, +1.003320086747407900, 1.004994612187147100, 1.006622135639190700, 1.008202098309993700, 1.009733878076076500, 1.011216927319765100, 1.012650609016418500, 1.014034371823072400, +1.015367589890956900, 1.016649682074785200, 1.017880033701658200, 1.019058048725128200, 1.020183108747005500, 1.021254621446132700, 1.022271949797868700, 1.023234523832798000, + +}; +/* ---------------------------------------------------------------------- +** Test input - logarithmic chirp signal +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[320] = + { + 0.000000000000000061, 0.002622410992047861, 0.005253663973466970, 0.007893770384930297, 0.010542741395035495, 0.013200587895525877, 0.015867320496454066, 0.018542949521290073, +0.021227485001971542, 0.023920936673895138, 0.026623313970853074, 0.029334626019908643, 0.032054881636210709, 0.034784089317753723, 0.037522257240071598, 0.040269393250875855, +0.043025504864628375, 0.045790599257054837, 0.048564683259595690, 0.051347763353792118, 0.054139845665610427, 0.056940935959702531, 0.059751039633601337, 0.062570161711849828, +0.065398306840066575, 0.068235479278943648, 0.071081682898178900, 0.073936921170339814, 0.076801197164660218, 0.079674513540768196, 0.082556872542344922, 0.085448275990715375, +0.088348725278367082, 0.091258221362398390, 0.094176764757897533, 0.097104355531246703, 0.100040993293358240, 0.102986677192832010, 0.105941405909045980, 0.108905177645166230, +0.111877990121087980, 0.114859840566297130, 0.117850725712659680, 0.120850641787131110, 0.123859584504392860, 0.126877549059407400, 0.129904530119898690, 0.132940521818751430, +0.135985517746334080, 0.139039510942737950, 0.142102493889940090, 0.145174458503884160, 0.148255396126476810, 0.151345297517508140, 0.154444152846483080, 0.157551951684374300, +0.160668682995289720, 0.163794335128054890, 0.166928895807713030, 0.170072352126936720, 0.173224690537355760, 0.176385896840798810, 0.179555956180445340, 0.182734853031894270, +0.185922571194139130, 0.189119093780459800, 0.192324403209221870, 0.195538481194587030, 0.198761308737133020, 0.201992866114384050, 0.205233132871247170, 0.208482087810360570, +0.211739708982344370, 0.215005973675965020, 0.218280858408200220, 0.221564338914212730, 0.224856390137231970, 0.228156986218334190, 0.231466100486134670, 0.234783705446379690, +0.238109772771442410, 0.241444273289723230, 0.244787176974952890, 0.248138452935395580, 0.251498069402956710, 0.254865993722190930, 0.258242192339209860, 0.261626630790492030, +0.265019273691591620, 0.268420084725748410, 0.271829026632395280, 0.275246061195565440, 0.278671149232197430, 0.282104250580339830, 0.285545324087251580, 0.288994327597401960, +0.292451217940364990, 0.295915950918612280, 0.299388481295203350, 0.302868762781368150, 0.306356748023990040, 0.309852388592980640, 0.313355634968552230, 0.316866436528383590, +0.320384741534681720, 0.323910497121136620, 0.327443649279772870, 0.330984142847692230, 0.334531921493712690, 0.338086927704900790, 0.341649102772995210, 0.345218386780727190, +0.348794718588032520, 0.352378035818156910, 0.355968274843654950, 0.359565370772282730, 0.363169257432780890, 0.366779867360555120, 0.370397131783246010, 0.374020980606193880, +0.377651342397795690, 0.381288144374756830, 0.384931312387234990, 0.388580770903877330, 0.392236442996751310, 0.395898250326170650, 0.399566113125414350, 0.403239950185338420, +0.406919678838884410, 0.410605214945482130, 0.414296472875345100, 0.417993365493664670, 0.421695804144698540, 0.425403698635752780, 0.429116957221065130, 0.432835486585582130, +0.436559191828633180, 0.440287976447505720, 0.444021742320914510, 0.447760389692375140, 0.451503817153472210, 0.455251921627031540, 0.459004598350192470, 0.462761740857380200, +0.466523240963184150, 0.470288988745136360, 0.474058872526396560, 0.477832778858340690, 0.481610592503056990, 0.485392196415748600, 0.489177471727042850, 0.492966297725213780, +0.496758551838309250, 0.500554109616195060, 0.504352844712508190, 0.508154628866524960, 0.511959331884944910, 0.515766821623591440, 0.519576963969030530, 0.523389622820107150, +0.527204660069405030, 0.531021935584629400, 0.534841307189911630, 0.538662630647041900, 0.542485759636628150, 0.546310545739186690, 0.550136838416161340, 0.553964484990880020, +0.557793330629441700, 0.561623218321546380, 0.565453988861259300, 0.569285480827721570, 0.573117530565801950, 0.576949972166696630, 0.580782637448476910, 0.584615355936589420, +0.588447954844309340, 0.592280259053150400, 0.596112091093235260, 0.599943271123626440, 0.603773616912622660, 0.607602943818024150, 0.611431064767369080, 0.615257790238142090, +0.619082928237961740, 0.622906284284749700, 0.626727661386881850, 0.630546860023327600, 0.634363678123782030, 0.638177911048790960, 0.641989351569874020, 0.645797789849653410, +0.649603013421986450, 0.653404807172108140, 0.657202953316791350, 0.660997231384523490, 0.664787418195706640, 0.668573287842887610, 0.672354611671016960, 0.676131158257749170, +0.679902693393781730, 0.683668980063242500, 0.687429778424128110, 0.691184845788802130, 0.694933936604551380, 0.698676802434213370, 0.702413191936877570, 0.706142850848662460, +0.709865521963579990, 0.713580945114492330, 0.717288857154159800, 0.720988991936399870, 0.724681080297347790, 0.728364850036839040, 0.732040025899910680, 0.735706329558433620, +0.739363479592880620, 0.743011191474238440, 0.746649177546067850, 0.750277147006723990, 0.753894805891742180, 0.757501857056394940, 0.761098000158428880, 0.764682931640995540, +0.768256344715771980, 0.771817929346292900, 0.775367372231492210, 0.778904356789468790, 0.782428563141483460, 0.785939668096195860, 0.789437345134148760, 0.792921264392515420, +0.796391092650110770, 0.799846493312681210, 0.803287126398485760, 0.806712648524170680, 0.810122712890953390, 0.813516969271127150, 0.816895063994893090, 0.820256639937531280, +0.823601336506926020, 0.826928789631450890, 0.830238631748229430, 0.833530491791779850, 0.836803995183058700, 0.840058763818912760, 0.843294416061954100, 0.846510566730867220, +0.849706827091166740, 0.852882804846411770, 0.856038104129895340, 0.859172325496819990, 0.862285065916973510, 0.865375918767918860, 0.868444473828712590, 0.871490317274166260, +0.874513031669661770, 0.877512195966544280, 0.880487385498096800, 0.883438171976119850, 0.886364123488128100, 0.889264804495180530, 0.892139775830360640, 0.894988594697921020, +0.897810814673113080, 0.900605985702712770, 0.903373654106265470, 0.906113362578062300, 0.908824650189867690, 0.911507052394417540, 0.914160101029702910, 0.916783324324059180, +0.919376246902079860, 0.921938389791372770, 0.924469270430179120, 0.926968402675872660, 0.929435296814361430, 0.931869459570409790, 0.934270394118903560, 0.936637600097074200, +0.938970573617708970, 0.941268807283364040, 0.943531790201601380, 0.945759008001275100, 0.947949942849885320, 0.950104073472023970, 0.952220875168933280, 0.954299819839202090, +0.956340376000621160, 0.958342008813221960, 0.960304180103520260, 0.962226348389994210, 0.964107968909812760, 0.965948493646846980, 0.967747371360983650, 0.969504047618768740, +0.971217964825405680, 0.972888562258134030, 0.974515276101013520, 0.976097539481141750, 0.977634782506330400, 0.979126432304266880, 0.980571913063189360, 0.981970646074102120, +0.983322049774557390, 0.984625539794035220, 0.985880529000944810, 0.987086427551279730, 0.988242642938953360, 0.989348580047844540, 0.990403641205582440, 0.991407226239099710, +0.992358732531984260, 0.993257555083659870, 0.994103086570423680, 0.994894717408374870, 0.995631835818261310, 0.996313827892278070, 0.996940077662846650, 0.997509967173408010, + + }; diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c new file mode 100644 index 0000000..2f68584 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c @@ -0,0 +1,415 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_graphic_equalizer_example_q31.c +* +* Description: Example showing an audio graphic equalizer constructed +* out of Biquad filters. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GEQ5Band Graphic Audio Equalizer Example + * + * \par Description: + * \par + * This example demonstrates how a 5-band graphic equalizer can be constructed + * using the Biquad cascade functions. + * A graphic equalizer is used in audio applications to vary the tonal quality + * of the audio. + * + * \par Block Diagram: + * \par + * The design is based on a cascade of 5 filter sections. + * \image html GEQ_signalflow.gif + * Each filter section is 4th order and consists of a cascade of two Biquads. + * Each filter has a nominal gain of 0 dB (1.0 in linear units) and + * boosts or cuts signals within a specific frequency range. + * The edge frequencies between the 5 bands are 100, 500, 2000, and 6000 Hz. + * Each band has an adjustable boost or cut in the range of +/- 9 dB. + * For example, the band that extends from 500 to 2000 Hz has the response shown below: + * \par + * \image html GEQ_bandresponse.gif + * \par + * With 1 dB steps, each filter has a total of 19 different settings. + * The filter coefficients for all possible 19 settings were precomputed + * in MATLAB and stored in a table. With 5 different tables, there are + * a total of 5 x 19 = 95 different 4th order filters. + * All 95 responses are shown below: + * \par + * \image html GEQ_allbandresponse.gif + * \par + * Each 4th order filter has 10 coefficents for a grand total of 950 different filter + * coefficients that must be tabulated. The input and output data is in Q31 format. + * For better noise performance, the two low frequency bands are implemented using the high + * precision 32x64-bit Biquad filters. The remaining 3 high frequency bands use standard + * 32x32-bit Biquad filters. The input signal used in the example is a logarithmic chirp. + * \par + * \image html GEQ_inputchirp.gif + * \par + * The array bandGains specifies the gain in dB to apply in each band. + * For example, if bandGains={0, -3, 6, 4, -6}; then the output signal will be: + * \par + * \image html GEQ_outputchirp.gif + * \par + * \note The output chirp signal follows the gain or boost of each band. + * \par + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c testRefOutput_f32 points to the reference output data + * \li \c testOutput points to the test output data + * \li \c inputQ31 temporary input buffer + * \li \c outputQ31 temporary output buffer + * \li \c biquadStateBand1Q31 points to state buffer for band1 + * \li \c biquadStateBand2Q31 points to state buffer for band2 + * \li \c biquadStateBand3Q31 points to state buffer for band3 + * \li \c biquadStateBand4Q31 points to state buffer for band4 + * \li \c biquadStateBand5Q31 points to state buffer for band5 + * \li \c coeffTable points to coefficient buffer for all bands + * \li \c gainDB gain buffer which has gains applied for all the bands + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_biquad_cas_df1_32x64_init_q31() + * - arm_biquad_cas_df1_32x64_q31() + * - arm_biquad_cascade_df1_init_q31() + * - arm_biquad_cascade_df1_q31() + * - arm_scale_q31() + * - arm_scale_f32() + * - arm_float_to_q31() + * - arm_q31_to_float() + * + * Refer + * \link arm_graphic_equalizer_example_q31.c \endlink + * + */ + + +/** \example arm_graphic_equalizer_example_q31.c + */ + + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* Length of the overall data in the test */ +#define TESTLENGTH 320 + +/* Block size for the underlying processing */ +#define BLOCKSIZE 32 + +/* Total number of blocks to run */ +#define NUMBLOCKS (TESTLENGTH/BLOCKSIZE) + +/* Number of 2nd order Biquad stages per filter */ +#define NUMSTAGES 2 + +#define SNR_THRESHOLD_F32 98 + +/* ------------------------------------------------------------------- + * External Declarations for Input and Output buffers + * ------------------------------------------------------------------- */ + +extern float32_t testInput_f32[TESTLENGTH]; +static float32_t testOutput[TESTLENGTH]; + +extern float32_t testRefOutput_f32[TESTLENGTH]; + +/* ---------------------------------------------------------------------- +** Q31 state buffers for Band1, Band2, Band3, Band4, Band5 +** ------------------------------------------------------------------- */ + +static q63_t biquadStateBand1Q31[4 * 2]; +static q63_t biquadStateBand2Q31[4 * 2]; +static q31_t biquadStateBand3Q31[4 * 2]; +static q31_t biquadStateBand4Q31[4 * 2]; +static q31_t biquadStateBand5Q31[4 * 2]; + +/* ---------------------------------------------------------------------- +** Q31 input and output buffers +** ------------------------------------------------------------------- */ + +q31_t inputQ31[BLOCKSIZE]; +q31_t outputQ31[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +** Entire coefficient table. There are 10 coefficients per 4th order Biquad +** cascade filter. The first 10 coefficients correspond to the -9 dB gain +** setting of band 1; the next 10 coefficient correspond to the -8 dB gain +** setting of band 1; and so on. There are 10*19=190 coefficients in total +** for band 1 (gains = -9, -8, -7, ..., 9). After this come the 190 coefficients +** for band 2. +** +** The coefficients are in Q29 format and require a postShift of 2. +** ------------------------------------------------------------------- */ + +const q31_t coeffTable[950] = { + + /* Band 1, -9 dB gain */ + 535576962, -1071153923, 535576962, 1073741824, -536870912, 535576962, -1063501998, 527979313, 1060865294, -524146981, + /* Band 1, -8 dB gain */ + 535723226, -1071446451, 535723226, 1073741824, -536870912, 535723226, -1063568947, 527903217, 1061230578, -524503778, + 535868593, -1071737186, 535868593, 1073741824, -536870912, 535868593, -1063627467, 527819780, 1061585502, -524850686, + 536013181, -1072026363, 536013181, 1073741824, -536870912, 536013181, -1063677598, 527728935, 1061930361, -525187972, + 536157109, -1072314217, 536157109, 1073741824, -536870912, 536157109, -1063719372, 527630607, 1062265438, -525515897, + 536300492, -1072600983, 536300492, 1073741824, -536870912, 536300492, -1063752815, 527524720, 1062591011, -525834716, + 536443447, -1072886894, 536443447, 1073741824, -536870912, 536443447, -1063777945, 527411186, 1062907350, -526144676, + 536586091, -1073172183, 536586091, 1073741824, -536870912, 536586091, -1063794775, 527289917, 1063214717, -526446017, + 536728541, -1073457082, 536728541, 1073741824, -536870912, 536728541, -1063803308, 527160815, 1063513366, -526738975, + 536870912, -1073741824, 536870912, 1073741824, -536870912, 536870912, -1063803543, 527023777, 1063803543, -527023777, + 537013321, -1074026642, 537013321, 1073741824, -536870912, 537013321, -1063795470, 526878696, 1064085490, -527300648, + 537155884, -1074311768, 537155884, 1073741824, -536870912, 537155884, -1063779073, 526725455, 1064359439, -527569803, + 537298718, -1074597435, 537298718, 1073741824, -536870912, 537298718, -1063754328, 526563934, 1064625617, -527831454, + 537441939, -1074883878, 537441939, 1073741824, -536870912, 537441939, -1063721205, 526394005, 1064884245, -528085806, + 537585666, -1075171331, 537585666, 1073741824, -536870912, 537585666, -1063679666, 526215534, 1065135536, -528333059, + 537730015, -1075460030, 537730015, 1073741824, -536870912, 537730015, -1063629666, 526028380, 1065379699, -528573409, + 537875106, -1075750212, 537875106, 1073741824, -536870912, 537875106, -1063571152, 525832396, 1065616936, -528807045, + 538021057, -1076042114, 538021057, 1073741824, -536870912, 538021057, -1063504065, 525627429, 1065847444, -529034151, + 538167989, -1076335977, 538167989, 1073741824, -536870912, 538167989, -1063428338, 525413317, 1066071412, -529254907, + + /* Band 2, -9 dB gain */ + 531784976, -1055497692, 523873415, 1066213307, -529420241, 531784976, -1040357886, 509828014, 1028908252, -494627367, + /* Band 2, -8 dB gain */ + 532357636, -1056601982, 524400080, 1066115844, -529326645, 532357636, -1040623406, 509562600, 1030462237, -496062122, + 532927392, -1057707729, 524931110, 1066024274, -529239070, 532927392, -1040848253, 509262081, 1031969246, -497457090, + 533494678, -1058816094, 525467240, 1065939047, -529157961, 533494678, -1041032161, 508925950, 1033429976, -498812573, + 534059929, -1059928204, 526009170, 1065860582, -529083734, 534059929, -1041174868, 508553717, 1034845124, -500128887, + 534623580, -1061045148, 526557561, 1065789260, -529016764, 534623580, -1041276126, 508144920, 1036215393, -501406373, + 535186068, -1062167969, 527113032, 1065725420, -528957385, 535186068, -1041335703, 507699125, 1037541500, -502645399, + 535747827, -1063297666, 527676151, 1065669351, -528905879, 535747827, -1041353386, 507215934, 1038824183, -503846368, + 536309295, -1064435183, 528247436, 1065621289, -528862476, 536309295, -1041328990, 506694984, 1040064203, -505009724, + 536870912, -1065581413, 528827349, 1065581413, -528827349, 536870912, -1041262354, 506135953, 1041262354, -506135953, + 537433117, -1066737194, 529416295, 1065549847, -528800610, 537433117, -1041153346, 505538564, 1042419457, -507225588, + 537996352, -1067903307, 530014622, 1065526651, -528782316, 537996352, -1041001864, 504902578, 1043536370, -508279208, + 538561061, -1069080480, 530622620, 1065511830, -528772462, 538561061, -1040807833, 504227800, 1044613981, -509297437, + 539127690, -1070269387, 531240527, 1065505333, -528770987, 539127690, -1040571205, 503514074, 1045653211, -510280946, + 539696690, -1071470656, 531868525, 1065507054, -528777778, 539696690, -1040291951, 502761277, 1046655011, -511230450, + 540268512, -1072684867, 532506750, 1065516837, -528792672, 540268512, -1039970063, 501969320, 1047620358, -512146700, + 540843613, -1073912567, 533155297, 1065534483, -528815459, 540843613, -1039605542, 501138139, 1048550251, -513030484, + 541422451, -1075154268, 533814224, 1065559750, -528845892, 541422451, -1039198394, 500267687, 1049445708, -513882621, + 542005489, -1076410460, 534483561, 1065592362, -528883686, 542005489, -1038748624, 499357932, 1050307760, -514703956, + 518903861, -1001986830, 486725277, 1037235801, -502367695, 518903861, -945834422, 446371043, 902366163, -400700571, + 520899989, -1005630916, 488289126, 1036926846, -502147311, 520899989, -946490935, 445581846, 907921945, -404936158, + 522893209, -1009290002, 489869792, 1036650484, -501961419, 522893209, -947006359, 444685310, 913306106, -409075225, + 524884763, -1012968199, 491470256, 1036407567, -501810737, 524884763, -947377809, 443679533, 918521018, -413116221, + 526875910, -1016669649, 493093518, 1036198712, -501695739, 526875910, -947602324, 442562672, 923569247, -417057897, + 528867927, -1020398503, 494742575, 1036024293, -501616651, 528867927, -947676875, 441332970, 928453558, -420899319, + 530862111, -1024158905, 496420407, 1035884447, -501573457, 530862111, -947598385, 439988777, 933176909, -424639872, + 532859778, -1027954970, 498129955, 1035779077, -501565907, 532859778, -947363742, 438528571, 937742446, -428279254, + 534862260, -1031790763, 499874098, 1035707863, -501593525, 534862260, -946969823, 436950987, 942153486, -431817474, + 536870912, -1035670279, 501655630, 1035670279, -501655630, 536870912, -946413508, 435254839, 946413508, -435254839, + 538887107, -1039597419, 503477238, 1035665609, -501751354, 538887107, -945691703, 433439146, 950526127, -438591937, + 540912240, -1043575967, 505341475, 1035692963, -501879659, 540912240, -944801359, 431503152, 954495080, -441829621, + 542947726, -1047609569, 507250741, 1035751307, -502039364, 542947726, -943739490, 429446349, 958324201, -444968987, + 544995000, -1051701717, 509207261, 1035839473, -502229165, 544995000, -942503190, 427268492, 962017400, -448011351, + 547055523, -1055855728, 511213065, 1035956193, -502447657, 547055523, -941089647, 424969617, 965578640, -450958226, + 549130774, -1060074734, 513269973, 1036100110, -502693359, 549130774, -939496155, 422550049, 969011913, -453811298, + 551222259, -1064361672, 515379585, 1036269804, -502964731, 551222259, -937720119, 420010407, 972321228, -456572401, + 553331507, -1068719280, 517543273, 1036463810, -503260192, 553331507, -935759057, 417351601, 975510582, -459243495, + 555460072, -1073150100, 519762181, 1036680633, -503578144, 555460072, -933610600, 414574832, 978583948, -461826644, + 494084017, -851422604, 404056273, 930151631, -423619864, 494084017, -673714108, 339502486, 561843007, -265801750, + 498713542, -859177141, 406587077, 929211656, -423786402, 498713542, -673274906, 338185129, 573719128, -272222942, + 503369016, -867012190, 409148384, 928362985, -424054784, 503369016, -672533059, 336693984, 585290277, -278599028, + 508052536, -874935599, 411746438, 927604291, -424422151, 508052536, -671478538, 335026905, 596558312, -284920289, + 512766286, -882955583, 414387826, 926933782, -424885216, 512766286, -670100998, 333182045, 607525792, -291177811, + 517512534, -891080712, 417079474, 926349262, -425440318, 517512534, -668389789, 331157902, 618195914, -297363485, + 522293635, -899319903, 419828635, 925848177, -426083491, 522293635, -666333963, 328953368, 628572440, -303470012, + 527112032, -907682405, 422642886, 925427679, -426810526, 527112032, -663922286, 326567785, 638659631, -309490882, + 531970251, -916177781, 425530105, 925084675, -427617023, 531970251, -661143261, 324000998, 648462180, -315420352, + 536870912, -924815881, 428498454, 924815881, -428498454, 536870912, -657985147, 321253420, 657985147, -321253420, + 541816719, -933606817, 431556352, 924617870, -429450209, 541816719, -654435997, 318326093, 667233900, -326985786, + 546810467, -942560921, 434712438, 924487114, -430467639, 546810467, -650483688, 315220754, 676214053, -332613816, + 551855042, -951688708, 437975532, 924420027, -431546101, 551855042, -646115970, 311939896, 684931422, -338134495, + 556953421, -961000826, 441354588, 924413001, -432680993, 556953421, -641320513, 308486839, 693391970, -343545389, + 562108672, -970508005, 444858642, 924462435, -433867780, 562108672, -636084967, 304865786, 701601770, -348844597, + 567323959, -980220994, 448496743, 924564764, -435102022, 567323959, -630397020, 301081886, 709566963, -354030710, + 572602539, -990150500, 452277894, 924716482, -436379394, 572602539, -624244471, 297141281, 717293726, -359102767, + 577947763, -1000307125, 456210977, 924914158, -437695705, 577947763, -617615296, 293051155, 724788245, -364060214, + 583363084, -1010701292, 460304674, 925154455, -439046908, 583363084, -610497723, 288819761, 732056685, -368902865, + 387379495, -506912469, 196933274, 840112184, -347208270, 387379495, 506912469, 196933274, -840112184, -347208270, + 401658082, -532275898, 207149427, 833765363, -343175316, 401658082, 532275898, 207149427, -833765363, -343175316, + 416472483, -558722695, 217902617, 827270154, -339107319, 416472483, 558722695, 217902617, -827270154, -339107319, + 431841949, -586290861, 229212798, 820624988, -335007540, 431841949, 586290861, 229212798, -820624988, -335007540, + 447786335, -615019650, 241100489, 813828443, -330879528, 447786335, 615019650, 241100489, -813828443, -330879528, + 464326111, -644949597, 253586805, 806879270, -326727141, 464326111, 644949597, 253586805, -806879270, -326727141, + 481482377, -676122557, 266693475, 799776409, -322554559, 481482377, 676122557, 266693475, -799776409, -322554559, + 499276882, -708581728, 280442865, 792519013, -318366296, 499276882, 708581728, 280442865, -792519013, -318366296, + 517732032, -742371685, 294857996, 785106465, -314167221, 517732032, 742371685, 294857996, -785106465, -314167221, + 536870912, -777538408, 309962566, 777538408, -309962566, 536870912, 777538408, 309962566, -777538408, -309962566, + 556717294, -814129313, 325780968, 769814766, -305757943, 556717294, 814129313, 325780968, -769814766, -305757943, + 577295658, -852193284, 342338310, 761935777, -301559360, 577295658, 852193284, 342338310, -761935777, -301559360, + 598631206, -891780698, 359660433, 753902014, -297373230, 598631206, 891780698, 359660433, -753902014, -297373230, + 620749877, -932943463, 377773927, 745714425, -293206383, 620749877, 932943463, 377773927, -745714425, -293206383, + 643678365, -975735041, 396706151, 737374355, -289066077, 643678365, 975735041, 396706151, -737374355, -289066077, + 667444134, -1020210487, 416485252, 728883588, -284960004, 667444134, 1020210487, 416485252, -728883588, -284960004, + 692075438, -1066426476, 437140179, 720244375, -280896294, 692075438, 1066426476, 437140179, -720244375, -280896294, + 717601336, -1114441339, 458700704, 711459472, -276883515, 717601336, 1114441339, 458700704, -711459472, -276883515, + 744051710, -1164315096, 481197437, 702532174, -272930673, 744051710, 1164315096, 481197437, -702532174, -272930673 + +}; + +/* ---------------------------------------------------------------------- +** Desired gains, in dB, per band +** ------------------------------------------------------------------- */ + +int gainDB[5] = {0, -3, 6, 4, -6}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- + * Graphic equalizer Example + * ------------------------------------------------------------------- */ + +int32_t main(void) +{ + float32_t *inputF32, *outputF32; + arm_biquad_cas_df1_32x64_ins_q31 S1; + arm_biquad_cas_df1_32x64_ins_q31 S2; + arm_biquad_casd_df1_inst_q31 S3; + arm_biquad_casd_df1_inst_q31 S4; + arm_biquad_casd_df1_inst_q31 S5; + int i; + int32_t status; + + inputF32 = &testInput_f32[0]; + outputF32 = &testOutput[0]; + + /* Initialize the state and coefficient buffers for all Biquad sections */ + + arm_biquad_cas_df1_32x64_init_q31(&S1, NUMSTAGES, + (q31_t *) &coeffTable[190*0 + 10*(gainDB[0] + 9)], + &biquadStateBand1Q31[0], 2); + + arm_biquad_cas_df1_32x64_init_q31(&S2, NUMSTAGES, + (q31_t *) &coeffTable[190*1 + 10*(gainDB[1] + 9)], + &biquadStateBand2Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S3, NUMSTAGES, + (q31_t *) &coeffTable[190*2 + 10*(gainDB[2] + 9)], + &biquadStateBand3Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S4, NUMSTAGES, + (q31_t *) &coeffTable[190*3 + 10*(gainDB[3] + 9)], + &biquadStateBand4Q31[0], 2); + + arm_biquad_cascade_df1_init_q31(&S5, NUMSTAGES, + (q31_t *) &coeffTable[190*4 + 10*(gainDB[4] + 9)], + &biquadStateBand5Q31[0], 2); + + + /* Call the process functions and needs to change filter coefficients + for varying the gain of each band */ + + for(i=0; i < NUMBLOCKS; i++) + { + + /* ---------------------------------------------------------------------- + ** Convert block of input data from float to Q31 + ** ------------------------------------------------------------------- */ + + arm_float_to_q31(inputF32 + (i*BLOCKSIZE), inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale down by 1/8. This provides additional headroom so that the + ** graphic EQ can apply gain. + ** ------------------------------------------------------------------- */ + + arm_scale_q31(inputQ31, 0x7FFFFFFF, -3, inputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 32x64 process function for band1, band2 + ** ------------------------------------------------------------------- */ + + arm_biquad_cas_df1_32x64_q31(&S1, inputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cas_df1_32x64_q31(&S2, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Call the Q31 Biquad Cascade DF1 process function for band3, band4, band5 + ** ------------------------------------------------------------------- */ + + arm_biquad_cascade_df1_q31(&S3, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S4, outputQ31, outputQ31, BLOCKSIZE); + arm_biquad_cascade_df1_q31(&S5, outputQ31, outputQ31, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Convert Q31 result back to float + ** ------------------------------------------------------------------- */ + + arm_q31_to_float(outputQ31, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + + /* ---------------------------------------------------------------------- + ** Scale back up + ** ------------------------------------------------------------------- */ + + arm_scale_f32(outputF32 + (i * BLOCKSIZE), 8.0f, outputF32 + (i * BLOCKSIZE), BLOCKSIZE); + }; + + snr = arm_snr_f32(testRefOutput_f32, testOutput, TESTLENGTH); + + status = (snr < SNR_THRESHOLD_F32) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + +/** \endlink */ + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c new file mode 100644 index 0000000..3d3cbe5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + + +#endif diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt new file mode 100644 index 0000000..629bd60 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_linear_interp_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt new file mode 100644 index 0000000..00b18cd --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_linear_interp_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_linear_interp_example) + + +include(config) +configApp(arm_linear_interp_example ${ROOT}) + +target_sources(arm_linear_interp_example PRIVATE math_helper.c arm_linear_interp_data.c arm_linear_interp_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_linear_interp_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c new file mode 100644 index 0000000..5f01bf4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2020 ARM Limited. All rights reserved. +* +* $Date: 23. March 2020 +* $Revision: V1.7.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_data.c +* +* Description: Data file used for example. Generation method described +* below +* +* Target Processor: Cortex-M55/Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Table generated from following MATLAB Command +* x = -pi: 0.005 : (2*pi - 0.005); +* y = sin(x); +* where pi value is 3.141592653589793 +* --------------------------------------------------------------------*/ + +const float arm_linear_interep_table[1884] = { + -0.00000000000000012246, -0.00499997916669272461, -0.00999983333416657426, -0.01499943750632833778, -0.01999866669333321897, -0.02499739591471236352, -0.02999550020249558760, -0.03499285460433645967, + -0.03998933418663432049, -0.04498481403766028952, -0.04997916927067827531, -0.05497227502706801550, -0.05996400647944477580, -0.06495423883478267102, -0.06994284733753272643, -0.07492970727274264608, + -0.07991469396917287582, -0.08489768280241610787, -0.08987854919801102627, -0.09485716863455760650, -0.09983341664682836292, -0.10480716882888259367, -0.10977830083717481091, -0.11474668839366414241, + -0.11971220728891958374, -0.12467473338522781778, -0.12963414261969488650, -0.13459031100734822339, -0.13954311464423671540, -0.14449242971052655982, -0.14943813247359924445, -0.15438009929114335228, + -0.15931820661424622720, -0.16425233099048111574, -0.16918234906699605724, -0.17410813759359589081, -0.17902957342582445643, -0.18394653352804138380, -0.18885889497650065749, -0.19376653496242188246, + -0.19866933079506152171, -0.20356715990477816658, -0.20845989984609966661, -0.21334742830078226583, -0.21822962308086962802, -0.22310636213174564468, -0.22797752353518849211, -0.23284298551241677799, + -0.23770262642713491097, -0.24255632478857228063, -0.24740395925452304815, -0.25224540863437805438, -0.25708055189215500702, -0.26190926814952469881, -0.26673143668883125823, -0.27154693695611287207, + -0.27635564856411409806, -0.28115745129529429169, -0.28595222510483570000, -0.29073985012364278457, -0.29552020666133954618, -0.30029317520926179785, -0.30505863644344366481, -0.30981647122760291868, + -0.31456656061611770747, -0.31930878585700123162, -0.32404302839486853749, -0.32876916987390319980, -0.33348709214081440066, -0.33819667724779156615, -0.34289780745545156426, -0.34759036523578440425, + -0.35227423327508999851, -0.35694929447691170488, -0.36161543196496220842, -0.36627252908604768233, -0.37092046941298267848, -0.37555913674750113218, -0.38018841512316164932, -0.38480818880824513295, + -0.38941834230865052247, -0.39401876037078076287, -0.39860932798442311187, -0.40318993038562678244, -0.40776045305957026033, -0.41232078174342468024, -0.41687080242921104034, -0.42141040136664820182, + -0.42593946506599966728, -0.43045788030090881282, -0.43496553411123045629, -0.43946231380585343285, -0.44394810696551983975, -0.44842280144563440025, -0.45288628537906855387, -0.45733844717895566490, + -0.46177917554148295576, -0.46620835944867272671, -0.47062588817115835749, -0.47503165127095098308, -0.47942553860420311640, -0.48380744032396016951, -0.48817724688290742296, -0.49253484903610883494, + -0.49688013784373685766, -0.50121300467379792387, -0.50553334120484727521, -0.50984103942869607451, -0.51413599165311318906, -0.51841809050451703733, -0.52268722893065910906, -0.52694330020330160114, + -0.53118619792088350717, -0.53541581601118337641, -0.53963204873396963812, -0.54383479068364282139, -0.54802393679187377806, -0.55219938233022769491, -0.55636102291278377585, -0.56050875449874415501, + -0.56464247339503548240, -0.56876207625890007336, -0.57286746010048128497, -0.57695852228539701301, -0.58103516053730530633, -0.58509727294046220969, -0.58914475794226950356, -0.59317751435581278496, + -0.59719544136239222087, -0.60119843851404120016, -0.60518640573603954547, -0.60915924332941506769, -0.61311685197343401832, -0.61705913272808676773, -0.62098598703655971676, -0.62489731672769976978, + -0.62879302401846870474, -0.63267301151638644097, -0.63653718222196797871, -0.64038543953114723806, -0.64421768723769123888, -0.64803382953560739743, -0.65183377102153672311, -0.65561741669714024283, + -0.65938467197147310195, -0.66313544266334978339, -0.66686963500369800251, -0.67058715563790372016, -0.67428791162814527560, -0.67797181045571497382, -0.68163876002333423365, -0.68528866865745496906, + -0.68892144511055120049, -0.69253699856340145136, -0.69613523862735682268, -0.69971607534660351657, -0.70327941920041048274, -0.70682518110536607381, -0.71035327241760792827, -0.71386360493503686619, + -0.71735609089952279138, -0.72083064299909871409, -0.72428717437014267233, -0.72772559859955054939, -0.73114582972689612372, -0.73454778224657879537, -0.73793137110996287475, -0.74129651172750310462, + -0.74464311997085930184, -0.74797111217499967495, -0.75128040514029281738, -0.75457091613458637802, -0.75784256289527696104, -0.76109526363136648097, -0.76432893702550519510, -0.76754350223602707537, + -0.77073887889896930403, -0.77391498713008166632, -0.77707174752682406371, -0.78020908117035037144, -0.78332690962748341423, -0.78642515495267417691, -0.78950373968995057883, -0.79256258687485459102, + -0.79560162003636603067, -0.79862076319881414310, -0.80161994088377730439, -0.80459907811196917926, -0.80755810040511433190, -0.81049693378780995889, -0.81341550478937396651, -0.81631374044568350001, + -0.81919156830099826294, -0.82204891640977173495, -0.82488571333844995515, -0.82770188816725775993, -0.83049737049197047689, -0.83327209042567607078, -0.83602597860052074719, -0.83875896616944312090, + -0.84147098480789661590, -0.84416196671555643327, -0.84683184461801519483, -0.84948055176846437586, -0.85210802194936297038, -0.85471418947409338873, -0.85729898918860358847, -0.85986235647303466134, + -0.86240422724333842819, -0.86492453795287804752, -0.86742322559401685567, -0.86990022769969410632, -0.87235548234498638820, -0.87478892814865483185, -0.87720050427468176935, -0.87959015043378918630, + -0.88195780688494751498, -0.88430341443686910630, -0.88662691444948726893, -0.88892824883542254089, -0.89120736006143541630, -0.89346419114986364018, -0.89569868568004784581, -0.89791078778974076080, + -0.90010044217650508891, -0.90226759409909518261, -0.90441218937882594808, -0.90653417440092687318, -0.90863349611588339894, -0.91071010204076130456, -0.91276394026052121156, -0.91479495942931421393, + -0.91680310877176696138, -0.91878833808425064422, -0.92075059773613565639, -0.92268983867103304686, -0.92460601240802031686, -0.92649907104285411652, -0.92836896724916673218, -0.93021565427965069439, + -0.93203908596722639945, -0.93383921672619663035, -0.93561600155338597862, -0.93736939602926661053, -0.93909935631906760189, -0.94080583917387217152, -0.94248880193169759512, -0.94414820251856268474, + -0.94578399944953905898, -0.94739615182978875740, -0.94898461935558620084, -0.95054936231532616286, -0.95209034159051575408, -0.95360751865675374983, -0.95510085558469226541, -0.95657031504098599672, + -0.95801586028922502969, -0.95943745519085332774, -0.96083506420607267540, -0.96220865239473030162, -0.96355818541719306936, -0.96488362953520556697, -0.96618495161273409977, -0.96746211911679436124, + -0.96871510011826533759, -0.96994386329268711400, -0.97114837792104458103, -0.97232861389053459877, -0.97348454169531939417, -0.97461613243726408218, -0.97572335782665908788, -0.97680619018292724753, + -0.97786460243531625469, -0.97889856812357467497, -0.97990806139861430513, -0.98089305702315576774, -0.98185353037235978402, -0.98278945743444268146, -0.98370081481127658041, -0.98458757971897459260, + -0.98544972998846025458, -0.98628724406602152897, -0.98710010101385037284, -0.98788828051056520874, -0.98865176285171985082, -0.98939052895029533374, -0.99010456033717775259, -0.99079383916161978263, + -0.99145834819168643381, -0.99209807081468681655, -0.99271299103758847693, -0.99330309348741807618, -0.99386836341164486175, -0.99440878667855037154, -0.99492434977758092973, -0.99541503981968604275, + -0.99588084453764003090, -0.99632175228634944908, -0.99673775204314341014, -0.99712883340804969734, -0.99749498660405444550, -0.99783620247734694519, -0.99815247249754812664, -0.99844378875792394457, + -0.99871014397558299791, -0.99895153149165882844, -0.99916794527147601013, -0.99935937990470136150, -0.99952583060547905980, -0.99966729321255021201, -0.99978376418935699377, -0.99987524062413102310, + -0.99994172022996630211, -0.99998320134487606037, -0.99999968293183461032, -0.99999116457880310449, -0.99995764649874008256, -0.99989912952959558723, -0.99981561513429084709, -0.99970710540068152827, + -0.99957360304150510988, -0.99941511139431382649, -0.99923163442139051327, -0.99902317670964990715, -0.99878974347052396077, -0.99853134053983161333, -0.99824797437763246322, -0.99793965206806589663, + -0.99760638131917367399, -0.99724817046270708421, -0.99686502845391877781, -0.99645696487133927910, -0.99602398991653673388, -0.99556611441386244632, -0.99508334981018020660, -0.99457570817457985335, + -0.99404320219807595915, -0.99348584519329008469, -0.99290365109411848898, -0.99229663445538318634, -0.99166481045246857029, -0.99100819488094182841, -0.99032680415615803593, -0.98962065531284981734, + -0.98888976600470146483, -0.98813415450390762462, -0.98735383970071644022, -0.98654884110295737454, -0.98571917883555348894, -0.98486487364001817912, -0.98398594687393692304, -0.98308242051043293053, + -0.98215431713761847110, -0.98120165995802932635, -0.98022447278804547555, -0.97922278005729512795, -0.97819660680804465525, -0.97714597869457153756, -0.97607092198252420889, -0.97497146354826413894, + -0.97384763087819514737, -0.97269945206807539861, -0.97152695582231529681, -0.97033017145326005970, -0.96910912888045630531, -0.96786385862990509388, -0.96659439183329753931, -0.96530076022723765305, + -0.96398299615244809058, -0.96264113255296213101, -0.96127520297529989168, -0.95988524156762966566, -0.95847128307891416021, -0.95703336285804208039, -0.95557151685294383636, -0.95408578160969381710, + -0.95257619427159534453, -0.95104279257825341531, -0.94948561486463034509, -0.94790470006008820114, -0.94630008768741435965, -0.94467181786183496150, -0.94301993129001049354, -0.94134446926901937935, + -0.93964547368532491678, -0.93792298701372800451, -0.93617705231630599094, -0.93440771324133520270, -0.93261501402220048362, -0.93079899947628874646, -0.92895971500386931297, -0.92709720658695793372, + -0.92521152078816815134, -0.92330270474954678761, -0.92137080619139533066, -0.91941587341107711140, -0.91743795528180982490, -0.91543710125144361900, -0.91341336134122519397, -0.91136678614454669223, + -0.90929742682568159839, -0.90720533511850520725, -0.90509056332520076982, -0.90295316431495353804, -0.90079319152262726789, -0.89861069894742917619, -0.89640574115155979840, -0.89417837325884952371, + -0.89192865095337958703, -0.88965663047809040442, -0.88736236863337547565, -0.88504592277566129788, -0.88270735081597395677, -0.88034671121849061848, -0.87796406299907814308, -0.87555946572381770920, + -0.87313297950751633802, -0.87068466501220309617, -0.86821458344561253107, -0.86572279655965511669, -0.86320936664887359946, -0.86067435654888468921, -0.85811782963480887076, -0.85553984981968544954, + -0.85294048155287616186, -0.85031978981845190990, -0.84767784013356972661, -0.84501469854683375349, -0.84233043163664556019, -0.83962510650953781077, -0.83689879079849771593, -0.83415155266127583022, + -0.83138346077868308104, -0.82859458435287203226, -0.82578499310560804503, -0.82295475727652578346, -0.82010394762137406310, -0.81723263541024548928, -0.81434089242579588142, -0.81142879096144915341, + -0.80849640381958998159, -0.80554380430974481531, -0.80257106624674723339, -0.79957826394889397470, -0.79656547223608642483, -0.79353276642796100049, -0.79048022234200465697, -0.78740791629166062560, + -0.78431592508441982936, -0.78120432601990186239, -0.77807319688792120349, -0.77492261596654288258, -0.77175266202012560157, -0.76856341429735364201, -0.76535495252925345167, -0.76212735692720223746, + -0.75888070818092168146, -0.75561508745646188689, -0.75233057639417066920, -0.74902725710665341019, -0.74570521217671992265, -0.74236452465532121181, -0.73900527805947069382, -0.73562755637015875276, + -0.73223144403025131055, -0.72881702594237995907, -0.72538438746681943581, -0.72193361441935266498, -0.71846479306912613971, -0.71497801013649253665, -0.71147335279084422677, -0.70795090864843213119, + -0.70441076577017613936, -0.70085301265946364779, -0.69727773825993766277, -0.69368503195327169131, -0.69007498355693630554, -0.68644768332195305049, -0.68280322193063958114, -0.67914169049434047754, + -0.67546318055115084356, -0.67176778406362758211, -0.66805559341649090044, -0.66432670141431326982, -0.66058120127920061382, -0.65681918664846095091, -0.65304075157226471049, -0.64924599051129161520, + -0.64543499833437067981, -0.64160787031610766462, -0.63776470213450353608, -0.63390558986856326840, -0.63003062999589209969, -0.62613991939028512679, -0.62223355531930457651, -0.61831163544184919445, + -0.61437425780571164324, -0.61042152084512746324, -0.60645352337831459621, -0.60247036460500380528, -0.59847214410395643824, -0.59445896183047686190, -0.59043091811391257284, -0.58638811365514731389, + -0.58233064952408175596, -0.57825862715710785178, -0.57417214835457219824, -0.57007131527823284856, -0.56595623044870269069, -0.56182699674288816283, -0.55768371739141653354, -0.55352649597605652065, + -0.54935543642712658663, -0.54517064302089812688, -0.54097222037698844410, -0.53676027345574461869, -0.53253490755562105097, -0.52829622831054467991, -0.52404434168727598298, -0.51977935398275876278, + -0.51550137182146404946, -0.51121050215272290096, -0.50690685224805331899, -0.50259052969847872738, -0.49826164241183845682, -0.49392029861008907021, -0.48956660682659941530, -0.48520067590343696207, + -0.48082261498864814486, -0.47643253353352743584, -0.47203054128988253257, -0.46761674830728994223, -0.46319126493034507019, -0.45875420179590142844, -0.45430566983030634676, -0.44984578024662685847, + -0.44537464454187103424, -0.44089237449419821369, -0.43639908216012618380, -0.43189487987172925365, -0.42737988023382966762, -0.42285419612118396726, -0.41831794067565886142, -0.41377122730340420986, + -0.40921416967201718062, -0.40464688170770196640, -0.40006947759241939799, -0.39548207176103394866, -0.39088477889845207880, -0.38627771393675675027, -0.38166099205233156022, -0.37703472866298326505, + -0.37239903942505520051, -0.36775404023053764879, -0.36309984720416821347, -0.35843657670053008513, -0.35376434530114259092, -0.34908326981154819135, -0.34439346725838987373, -0.33969505488648726876, + -0.33498815015590455157, -0.33027287073901562264, -0.32554933451755990736, -0.32081765957969693437, -0.31607796421705369738, -0.31133036692176702109, -0.30657498638352281839, -0.30181194148658646581, + -0.29704135130683229082, -0.29226333510876589816, -0.28747801234254427571, -0.28268550264098690761, -0.27788592581658666525, -0.27307940185851381498, -0.26826605092961780530, -0.26344599336342072737, + -0.25861934966111072010, -0.25378624048852843620, -0.24894678667315245368, -0.24410110920107558341, -0.23924932921398228691, -0.23439156800611909981, -0.22952794702126408377, -0.22465858784968809059, + -0.21978361222511683115, -0.21490314202168656066, -0.21001729925089901441, -0.20512620605856862754, -0.20022998472177039320, -0.19532875764578278011, -0.19042264736102693101, -0.18551177652000533369, + -0.18059626789423280369, -0.17567624437116896585, -0.17075182895114521253, -0.16582314474429141193, -0.16089031496745564986, -0.15595346294112538699, -0.15101271208634373111, -0.14606818592162557069, + -0.14112000805986710250, -0.13616830220525713568, -0.13121319215018367732, -0.12625480177214090660, -0.12129325503062962643, -0.11632867596405992161, -0.11136118868664945936, -0.10639091738532231723, + -0.10141798631660174645, -0.09644251980350543318, -0.09146464223243663816, -0.08648447805007625222, -0.08150215176026900932, -0.07651778792091265546, -0.07153151114084313478, -0.06654344607672113554, + -0.06155371742991302270, -0.05656244994337508020, -0.05156976839853451289, -0.04657579761216946307, -0.04158066243329036626, -0.03658448774001610282, -0.03158739843645377854, -0.02658951944957526833, + -0.02159097572609583807, -0.01659189222934778080, -0.01159239393615815392, -0.00659260583372344670, -0.00159265291648670571, 0.00340733981698999704, 0.00840724736714873987, 0.01340694473656162643, + 0.01840630693305393001, 0.02340520897283157251, 0.02840352588360391117, 0.03340113270770895398, 0.03839790450523550280, 0.04339371635714930203, 0.04838844336841426758, 0.05338196067111569687, + 0.05837414342758021069, 0.06336486683349934479, 0.06835400612104790274, 0.07334143656200353689, 0.07832703347086542034, 0.08331067220796961603, 0.08829222818260772099, 0.09327157685613979288, + 0.09824859374510880317, 0.10322315442435085753, 0.10819513453010849713, 0.11316440976313804634, 0.11813085589181793189, 0.12309434875525272768, 0.12805476426637979470, 0.13301197841506973152, + 0.13796586727122742144, 0.14291630698788859721, 0.14786317380431862611, 0.15280634404910475865, 0.15774569414324876582, 0.16268110060325466359, 0.16761244004421843590, 0.17253958918291092961, + 0.17746242484086069413, 0.18238082394743185266, 0.18729466354290330576, 0.19220382078154110705, 0.19710817293466997846, 0.20200759739374196666, 0.20690197167339988149, 0.21179117341454209433, + 0.21667508038737973153, 0.22155357049449328488, 0.22642652177388328250, 0.23129381240202195880, 0.23615532069689712524, 0.24101092512105504184, 0.24586050428463715467, 0.25070393694841736076, + 0.25554110202683133490, 0.26037187859100452414, 0.26519614587177353648, 0.27001378326270797370, 0.27482467032312413169, 0.27962868678109636944, 0.28442571253646264928, 0.28921562766382935550, + 0.29399831241556773076, 0.29877364722480853620, 0.30354151270842943955, 0.30830178967004207014, 0.31305435910297030322, 0.31779910219322587972, 0.32253590032247908548, 0.32726463507102254713, + 0.33198518822073419532, 0.33669744175803123509, 0.34140127787682106320, 0.34609657898144485788, 0.35078322768961994749, 0.35546110683537274211, 0.36013009947196866767, 0.36479008887483416190, + 0.36944095854447722704, 0.37408259220939837908, 0.37871487382899815533, 0.38333768759647646185, 0.38795091794173042210, 0.39255444953424156740, 0.39714816728596030737, 0.40173195635418124105, + 0.40630570214441691368, 0.41086929031326063777, 0.41542260677124637214, 0.41996553768569905296, 0.42449796948358270443, 0.42901978885433855737, 0.43353088275271783880, 0.43803113840160834425, + 0.44252044329485257235, 0.44699868520006236228, 0.45146575216142326159, 0.45592153250249434215, 0.46036591482899841266, 0.46479878803160906697, 0.46922004128872724094, 0.47362956406925205144, + 0.47802724613534297582, 0.48241297754517775687, 0.48678664865569953868, 0.49114815012535872896, 0.49549737291684503582, 0.49983420829981556333, 0.50415854785361158275, 0.50847028346996991921, + 0.51276930735572390230, 0.51705551203550070838, 0.52132879035440660154, 0.52558903548070656786, 0.52983614090849351363, 0.53407000046035324470, 0.53829050829001767742, 0.54249755888501083323, + 0.54669104706928728366, 0.55087086800586004820, 0.55503691719942394034, 0.55918909049896592389, 0.56332728410037014033, 0.56745139454901150078, 0.57156131874234383794, 0.57565695393247651168, + 0.57973819772874324308, 0.58380494810026106745, 0.58785710337848284812, 0.59189456225973779979, 0.59591722380776435131, 0.59992498745623268341, 0.60391775301126071618, 0.60789542065391743986, + 0.61185789094271936239, 0.61580506481611496650, 0.61973684359496328256, 0.62365312898499980498, 0.62755382307929374885, 0.63143882836069553655, 0.63530804770427573569, 0.63916138437975222875, + 0.64299874205390883386, 0.64682002479300404474, 0.65062513706516744705, 0.65441398374279102779, 0.65818647010490505256, 0.66194250183954728151, 0.66568198504611930666, 0.66940482623773611692, + 0.67311093234356178527, 0.67680021071113694031, 0.68047256910869413637, 0.68412791572746478597, 0.68776615918397387972, 0.69138720852232482539, 0.69499097321647207437, 0.69857736317248630975, + 0.70214628873080553451, 0.70569766066847683383, 0.70923139020138625810, 0.71274738898647960195, 0.71624556912397063790, 0.71972584315953824774, 0.72318812408651222956, 0.72663232534805011209, + 0.73005836083929964708, 0.73346614490955241994, 0.73685559236438336050, 0.74022661846778314843, 0.74357913894427474233, 0.74691306998102069414, 0.75022832822991902813, 0.75352483080968579721, + 0.75680249530792831347, 0.76006123978320494494, 0.76330098276707347704, 0.76652164326612803880, 0.76972314076402448269, 0.77290539522349099855, 0.77606832708833239920, 0.77921185728541675353, + 0.78233590722665280470, 0.78544039881095495392, 0.78852525442619503249, 0.79159039695114352675, 0.79463574975739748041, 0.79766123671129407491, 0.80066678217581777055, 0.80365231101248835177, + 0.80661774858324053472, 0.80956302075228947501, 0.81248805388798428506, 0.81539277486464900591, 0.81827711106441036737, 0.82114099037901422395, 0.82398434121162578148, 0.82680709247862294031, + 0.82960917361137087589, 0.83239051455798740431, 0.83515104578509358202, 0.83789069827955253711, 0.84060940355019453385, 0.84330709362953004682, 0.84598370107544651475, 0.84863915897289776691, + 0.85127340093557457568, 0.85388636110756510611, 0.85647797416500115464, 0.85904817531769128713, 0.86159690031074054328, 0.86412408542615726237, 0.86662966748444436593, 0.86911358384618120354, + 0.87157577241358819009, 0.87401617163207945271, 0.87643472049180148886, 0.87883135852915883479, 0.88120602582832530114, 0.88355866302274232993, 0.88588921129660269660, 0.88819761238632033429, + 0.89048380858198861176, 0.89274774272882151394, 0.89498935822858360911, 0.89720859904100391802, 0.89940540968517768139, 0.90157973524095347262, 0.90373152135030576648, 0.90586071421869318598, + 0.90796726061640542493, 0.91005110787989218490, 0.91211220391308034383, 0.91415049718867658068, 0.91616593674945501213, 0.91815847220953161756, 0.92012805375562400911, 0.92207463214829554765, + 0.92399815872318802334, 0.92589858539223723888, 0.92777586464487560303, 0.92962994954921940316, 0.93146079375324264404, 0.93326835148593556557, 0.93505257755844939371, 0.93681342736522454917, + 0.93855085688510786479, 0.94026482268245192842, 0.94195528190820099201, 0.94362219230096244793, 0.94526551218806342813, 0.94688520048659219341, 0.94848121670442564479, 0.95005352094124184692, + 0.95160207388951612018, 0.95312683683550569747, 0.95462777166021639541, 0.95610484084035574082, 0.95755800744927122015, 0.95898723515787320792, 0.96039248823554335122, 0.96177373155102841018, + 0.96313093057331666813, 0.96446405137250368345, 0.96577306062063883463, 0.96705792559255909779, 0.96831861416670717002, 0.96955509482593427162, 0.97076733665828829345, 0.97195530935778684523, + 0.97311898322517387250, 0.97425832916866350608, 0.97537331870466648098, 0.97646392395850256651, 0.97753011766509712022, 0.97857187316966298685, 0.97958916442836685423, 0.98058196600898028805, + 0.98155025309151555657, 0.98249400146884580121, 0.98341318754731077423, 0.98430778834730647819, 0.98517778150385948432, 0.98602314526718615184, 0.98684385850323652623, 0.98763990069422247231, + 0.98841125193913059732, 0.98915789295421985283, 0.98987980507350392667, 0.99057697024921731455, 0.99124937105226695877, 0.99189699067266778876, 0.99251981291996316248, 0.99311782222362920969, + 0.99369100363346452021, 0.99423934281996362294, 0.99476282607467558794, 0.99526144031054608607, 0.99573517306224534895, 0.99618401248647925339, 0.99660794736228552892, 0.99700696709131431117, + 0.99738106169809326307, 0.99773022183027670895, 0.99805443875887944749, 0.99835370437849513259, 0.99862801120749888906, 0.99887735238823427419, 0.99910172168718480723, 0.99930111349512962260, + 0.99947552282728402417, 0.99962494532342371922, 0.99974937724799395333, 0.99984881549020332425, 0.99992325756410094240, 0.99997270160863860333, 0.99999714638771797226, 0.99999659129022078208, + 0.99997103633002448753, 0.99992048214600159906, 0.99984493000200436175, 0.99974438178683222578, 0.99961884001418532808, 0.99946830782260165371, 0.99929278897537787696, 0.99909228786047621362, + 0.99886680949041417588, 0.99861635950213900603, 0.99834094415688756641, 0.99804057034002902071, 0.99771524556089319358, 0.99736497795258272081, 0.99698977627176943450, 0.99658964989847598215, + 0.99616460883584057040, 0.99571466370986794203, 0.99523982576916258935, 0.99474010688464831187, 0.99421551954927123163, 0.99366607687768748747, 0.99309179260593527516, 0.99249268109109134439, + 0.99186875731091250774, 0.99122003686346060736, 0.99054653596671304872, 0.98984827145815734717, 0.98912526079436957627, 0.98837752205057904931, 0.98760507392021512629, 0.98680793571444103129, + 0.98598612736167012827, 0.98513966940706865216, 0.98426858301204134261, 0.98337288995370264466, 0.98245261262433225546, 0.98150777403081579386, 0.98053839779406870569, 0.97954450814844640227, + 0.97852612994113830069, 0.97748328863154654300, 0.97641601029064950534, 0.97532432160035020807, 0.97420824985280907171, 0.97306782294976124081, 0.97190306940182058515, 0.97071401832776471608, + 0.96950069945380856762, 0.96826314311286099112, 0.96700138024376580681, 0.96571544239052919956, 0.96440536170153046136, 0.96307117092871830089, 0.96171290342679316421, 0.96033059315237145892, + 0.95892427466313823192, 0.95749398311698219466, 0.95603975427111775875, 0.95456162448119030728, 0.95305963070036747720, 0.95153381047841534279, 0.94998420196076049926, 0.94841084388753493783, + 0.94681377559260859744, 0.94519303700260559609, 0.94354866863590625137, 0.94188071160163422402, 0.94018920759862834036, 0.93847419891440064799, 0.93673572842407859529, 0.93497383958933455439, + 0.93318857645729724748, 0.93137998365945207091, 0.92954810641052476594, 0.92769299050735110068, 0.92581468232773200810, 0.92391322882927429117, 0.92198867754821589582, 0.92004107659823930465, + 0.91807047466926661183, 0.91607692102624327379, 0.91406046550790653882, 0.91202115852553944375, 0.90995905106171026677, 0.90787419466899810239, 0.90576664146870400351, 0.90363644414954891193, + 0.90148365596635438024, 0.89930833073871296879, 0.89711052284964198922, 0.89489028724422425842, 0.89264767942823419755, 0.89038275546675049732, 0.88809557198275379530, 0.88578618615571291794, + 0.88345465572015269284, 0.88110103896421276826, 0.87872539472818933515, 0.87632778240306463680, 0.87390826192902193448, 0.87146689379394692843, 0.86900373903191607816, 0.86651885922166937970, + 0.86401231648507381689, 0.86148417348556682871, 0.85893449342659156098, 0.85636334005001668590, 0.85377077763454289894, 0.85115687099409531591, 0.84852168547620410166, 0.84586528696036911157, + 0.84318774185641620633, 0.84048911710283280563, 0.83776948016509722450, 0.83502889903399135640, 0.83226744222390069972, 0.82948517877110161667, 0.82668217823203571371, 0.82385851068156967791, + 0.82101424671124645371, 0.81814945742751654656, 0.81526421444996288734, 0.81235858990950959857, 0.80943265644661888114, 0.80648648720947491153, 0.80352015585215519344, 0.80053373653278914190, + 0.79752730391170367774, 0.79450093314955871904, 0.79145469990546535310, 0.78838868033509590383, 0.78530295108877989918, 0.78219758930958782628, 0.77907267263140256297, 0.77592827917697804185, + 0.77276448755598647899, 0.76958137686305472247, 0.76637902667578372551, 0.76315751705276135830, 0.75991692853156034282, 0.75665734212672508541, 0.75337883932774563078, 0.75008150209702162403, + 0.74676541286781195073, 0.74343065454217460708, 0.74007731048889391356, 0.73670546454139651527, 0.73331520099565583592, 0.72990660460808376442, 0.72647976059341234922, 0.72303475462256339146, + 0.71957167282050704671, 0.71609060176410799237, 0.71259162847996104784, 0.70907484044221602559, 0.70554032557039114693, 0.70198817222717391218, 0.69841846921621286715, 0.69483130577989704602, + 0.69122677159712608841, 0.68760495678106647865, 0.68396595187690023554, 0.68030984785955983529, 0.67663673613145614016, 0.67294670852019056184, 0.66923985727626122966, 0.66551627507075594714, + 0.66177605499303648884, 0.65801929054840968547, 0.65424607565579095958, 0.65045650464535575974, 0.64665067225618266811, 0.64282867363388296322, 0.63899060432822296640, 0.63513656029073550791, + 0.63126663787232040193, 0.62738093382083737204, 0.62347954527868487684, 0.61956256978037316241, 0.61563010525008554641, 0.61168224999923104246, 0.60771910272398499409, 0.60374076250282282530, + 0.59974732879404257790, 0.59573890143327967728, 0.59171558063100893055, 0.58767746697004086265, 0.58362466140300639506, 0.57955726524983441905, 0.57547538019521626840, 0.57137910828606597313, + 0.56726855192896752378, 0.56314381388761636238, 0.55900499728024832802, 0.55485220557706316225, 0.55068554259763680125, 0.54650511250832733978, 0.54231101981966889358, 0.53810336938376035487, + 0.53388226639164337861, 0.52964781637067259723, 0.52540012518187872992, 0.52113929901731992356, 0.51686544439742831969, 0.51257866816834640744, 0.50827907749925749226, 0.50396677987970384116, + 0.49964188311690155286, 0.49530449533304393706, 0.49095472496260045281, 0.48659268074960349004, 0.48221847174493104315, 0.47783220730358016981, 0.47343399708193417696, 0.46902395103501909324, + 0.46460217941375647754, 0.46016879276220612471, 0.45572390191480421917, 0.45126761799359005334, 0.44680005240542952638, 0.44232131683922926157, 0.43783152326314600522, 0.43333078392178486782, + 0.42881921133339495622, 0.42429691828705606849, 0.41976401783985833882, 0.41522062331407771918, 0.41066684829434035864, 0.40610280662478442926, 0.40152861240621368077, 0.39694437999324616584, + 0.39235022399145291772, 0.38774625925449479613, 0.38313260088125000724, 0.37850936421293840395, 0.37387666483023551667, 0.36923461855038458568, 0.36458334142430037783, 0.35992294973366972810, + 0.35525355998804170055, 0.35057528892191675007, 0.34588825349182744651, 0.34119257087341625656, 0.33648835845850372239, 0.33177573385215508583, 0.32705481486973969618, 0.32232571953398708731, + 0.31758856607203389544, 0.31284347291246999978, 0.30809055868237716913, 0.30332994220436321209, 0.29856174249359301864, 0.29378607875481060896, 0.28900307037936062704, 0.28421283694220295102, + 0.27941549819892491646, 0.27461117408274476892, 0.26979998470151522749, 0.26498205033471977643, 0.26015749143046751346, 0.25532642860247933836, 0.25048898262707436357, 0.24564527444014955249, + 0.24079542513415819194, 0.23593955595507989931, 0.23107778829939124021, 0.22621024371102996242, 0.22133704387835811955, 0.21645831063111725667, 0.21157416593738448407, 0.20668473190052233379, + 0.20179013075612792227, 0.19689048486897448020, 0.19198591672995404811, 0.18707654895301459308, 0.18216250427209446094, 0.17724390553805557946, 0.17232087571560969486, 0.16739353788024594061, + 0.16246201521515318822, 0.15752643100814200938, 0.15258690864856014335, 0.14764357162420929659, 0.14269654351825716843, 0.13774594800614961554, 0.13279190885251615506, 0.12783454990807766039, + 0.12287399510654904711, 0.11791036846154288875, 0.11294379406346635730, 0.10797439607642073112, 0.10300229873509640643, 0.09802762634166883871, 0.09305050326268833605, 0.08807105392597264215, + 0.08308940281749539747, 0.07810567447827571064, 0.07311999350126208164, 0.06813248452821923928, 0.06314327224661175908, 0.05815248138648638349, 0.05316023671735556344, 0.04816666304507556673, + 0.04317188520872811824, 0.03817602807749854305, 0.03317921654755580374, 0.02818157553892746553, 0.02318322999237843948, 0.01818430486628662066, 0.01318492513352068594, 0.00818521577831312665, + 0.00318530179313742355, -0.00181469182441765112, -0.00681464007477118605, -0.01181441795947778088, -0.01681390048435072240, -0.02181296266258772251, -0.02681147951789380687, -0.03180932608760837083, + -0.03680637742582747868, -0.04180250860652838518, -0.04679759472669089287, -0.05179151090942261254, -0.05678413230707906462, -0.06177533410438534184, -0.06676499152155691841, -0.07175297981741735054, + -0.07673917429251948807, -0.08172345029226112112, -0.08670568321000234058, -0.09168574849017877004, -0.09666352163141823939, -0.10163887818965149090, -0.10661169378122412055, -0.11158184408600446691, + -0.11654920485049420631, -0.12151365189093295271, -0.12647506109640369032, -0.13143330843193384849, -0.13638826994159863881, -0.14133982175161846628, -0.14628784007345638218, -0.15123220120691119317, + -0.15617278154321248551, -0.16110945756810918228, -0.16604210586495821156, -0.17097060311780823416, -0.17589482611448500893, -0.18081465174967009668, -0.18572995702797928663, -0.19064061906703580473, + -0.19554651510054482655, -0.20044752248136102346, -0.20534351868455516521, -0.21023438131047758604, -0.21511998808781651604, -0.22000021687665741177, -0.22487494567153470948, -0.22974405260448288457, + -0.23460741594808134924, -0.23946491411850023834, -0.24431642567853828485, -0.24916182934065958521, -0.25400100397002411956, -0.25883382858751863287, -0.26366018237277932812, -0.26847994466721347706, + -0.27329299497701375898, -0.27809921297617368197, -0.28289847850949351171, -0.28769067159558531221, -0.29247567242987065894, -0.29725336138757835203, -0.30202361902673330318, -0.30678632609114336871, + -0.31154136351337924360, -0.31628861241775330093, -0.32102795412329032665, -0.32575927014669442405, -0.33048244220531186599, -0.33519735222008639752, -0.33990388231851365042, -0.34460191483758617625, + -0.34929133232673625908, -0.35397201755076995733, -0.35864385349280092363, -0.36330672335717389965, -0.36796051057238560178, -0.37260509879399711375, -0.37724037190754533544, -0.38186621403144377362, + -0.38648250951988066815, -0.39108914296570845837, -0.39568599920333130671, -0.40027296331158268572, -0.40484992061659924589, -0.40941675669468591270, -0.41397335737517892973, -0.41851960874329868778, + -0.42305539714299816856, -0.42758060917980272864, -0.43209513172364766298, -0.43659885191170438867, -0.44109165715120285389, -0.44557343512224645288, -0.45004407378061850320, -0.45450346136058583646, + -0.45895148637769117572, -0.46338803763154118309, -0.46781300420858479283, -0.47222627548488838034, -0.47662774112889999545, -0.48101729110420810009, -0.48539481567229114667, -0.48976020539526338160, + -0.49411335113860904711, -0.49845414407391169798, -0.50278247568157319325, -0.50709823775352924624, -0.51140132239595281760, -0.51569162203195229033, -0.51996902940425959727, -0.52423343757791340813, + -0.52848473994293165834, -0.53272283021697686145, -0.53694760244801220672, -0.54115895101695243863, -0.54535677064030252392, -0.54954095637279054554, -0.55371140360999160368, -0.55786800809094105880, + -0.56201066590074388873, -0.56613927347317050121, -0.57025372759324721716, -0.57435392539983431970, -0.57843976438820066122, -0.58251114241258428184, -0.58656795768874714359, -0.59061010879651776317, + -0.59463749468232940387, -0.59865001466174472267, -0.60264756842197342301, -0.60663005602437913844, -0.61059737790697954374, -0.61454943488693414277, -0.61848612816302472872, -0.62240735931812363191, + -0.62631303032165663858, -0.63020304353205203185, -0.63407730169918252727, -0.63793570796679510693, -0.64177816587493419220, -0.64560457936235238208, -0.64941485276891164347, -0.65320889083797573083, + -0.65698659871878983818, -0.66074788196885403391, -0.66449264655628281773, -0.66822079886215701716, -0.67193224568286247234, -0.67562689423242239251, -0.67930465214481527969, -0.68296542747628530279, + -0.68660912870763923799, -0.69023566474653630376, -0.69384494492976445112, -0.69743687902550732804, -0.70101137723559914239, -0.70456835019777108720, -0.70810770898788422123, -0.71162936512215357876, + -0.71513323055935862360, -0.71861921770304615364, -0.72208723940371910555, -0.72553720896101603355, -0.72896904012587693256, -0.73238264710270173374, -0.73577794455149403419, -0.73915484758999416837, + -0.74251327179580250970, -0.74585313320848811713, -0.74917434833169005426, -0.75247683413520316531, -0.75576050805705463631, -0.75902528800556723354, -0.76227109236141132875, -0.76549783997964904181, + -0.76870545019175651191, -0.77189384280764572477, -0.77506293811766757695, -0.77821265689460439319, -0.78134292039565123034, -0.78445365036438186035, -0.78754476903271153354, -0.79061619912283220835, + -0.79366786384915377628, -0.79669968692021542189, -0.79971159254059875909, -0.80270350541282020629, -0.80567535073921381361, -0.80862705422380165565, -0.81155854207414879209, -0.81446974100321378742, + -0.81736057823117291843, -0.82023098148724815637, -0.82308087901150606136, -0.82591019955665734287, -0.82871887238983588109, -0.83150682729436709018, -0.83427399457152406903, -0.83702030504226743179, + -0.83974569004898047542, -0.84245008145717859005, -0.84513341165721778125, -0.84779561356598298616, -0.85043662062856495432, -0.85305636681992524917, -0.85565478664654404106, -0.85823181514806290426, + -0.86078738789890174576, -0.86332144100987662227, -0.86583391112979046778, -0.86832473544702148960, -0.87079385169109158049, -0.87324119813422318437, -0.87566671359288317245, -0.87807033742931006604, + -0.88045200955303482004, -0.88281167042237718157, -0.88514926104593882883, -0.88746472298407563795, -0.88975799835036006868, -0.89202902981302722996, -0.89427776059640884387, -0.89650413448235288794, + -0.89870809581162691693, -0.90088958948531416837, -0.90304856096618524308, -0.90518495628006578890, -0.90729872201718442248, -0.90938980533350777247, -0.91145815395206175591, -0.91350371616423864385, + -0.91552644083109002704, -0.91752627738460390550, -0.91950317582897100888, -0.92145708674183313125, -0.92338796127551925341, -0.92529575115826656617, -0.92718040869542739379, -0.92904188677066168456, + -0.93088013884711362511, -0.93269511896857837385, -0.93448678176064647882, -0.93625508243184163426, -0.93799997677473923030, -0.93972142116707157999, -0.94141937257281860241, -0.94309378854328340669, + -0.94474462721815444244, -0.94637184732654988650, -0.94797540818805281493, -0.94955526971372439249, -0.95111139240710917964, -0.95264373736522078850, -0.95415226627951510441, -0.95563694143684785320, + -0.95709772572041729166, -0.95853458261069279800, -0.95994747618632647601, -0.96133637112505265776, -0.96270123270457030884, -0.96404202680341100073, -0.96535871990179211721, -0.96665127908245462862, + -0.96791967203148676635, -0.96916386703913015577, -0.97038383300057517999, -0.97157953941673580456, -0.97275095639501407696, -0.97389805465004641860, -0.97502080550443648299, -0.97611918088947113858, + -0.97719315334582312893, -0.97824269602423696846, -0.97926778268620007228, -0.98026838770459978623, -0.98124448606436232012, -0.98219605336307969079, -0.98312306581161901242, -0.98402550023471724305, + -0.98490333407156094303, -0.98575654537634993524, -0.98658511281884597732, -0.98738901568490611282, -0.98816823387700059023, -0.98892274791471512785, -0.98965253893523819073, -0.99035758869383216929, + -0.99103787956429001405, -0.99169339453937521700, -0.99232411723124747116, -0.99293003187187267589, -0.99351112331341595585, -0.99406737702862180139, -0.99459877911117622329, -0.99510531627605480764, + -0.99558697585985489464, -0.99604374582111188108, -0.99647561474060075692, -0.99688257182162054448, -0.99726460689026596995, -0.99762171039567981712, -0.99795387341029329065, -0.99826108763004817170, + -0.99854334537460498478, -0.99880063958753495523, -0.99903296383649597967, -0.99924031231339405235, -0.99942267983452803826, -0.99958006184071934719, -0.99971245439742595362, -0.99981985419484109556, + -0.99990225854797520899, -0.99995966539672387352, -0.99999207330591877163, -0.99999948146536388194, -0.99998188968985557423, -0.99993929841918749446, -0.99987170871813890738, -0.99977912227644905041, + -0.99966154140877416800, -0.99951896905462955800, -0.99935140877831696304, -0.99915886476883430944, -0.99894134183977201236, -0.99869884542919173942, -0.99843138159949140764, -0.99813895703725263875, + -0.99782157905307422574, -0.99747925558138939017, -0.99711199518026705224, -0.99671980703119800182, -0.99630270093886552640, -0.99586068733090049587, -0.99539377725761979399, -0.99490198239175109407, + -0.99438531502814031526, -0.99384378808344475686, -0.99327741509580969037, -0.99268621022453029656, -0.99207018824969783743, -0.99142936457182928578, -0.99076375521148341008, -0.99007337680885953990, + -0.98935824662338167634, -0.98861838253326717041, -0.98785380303507996924, -0.98706452724326754211, -0.98625057488968337349, -0.98541196632309446812, -0.98454872250867075945, -0.98366086502746297171, + -0.98274841607586183034, -0.98181139846504350555, -0.98084983562039951277, -0.97986375158095095905, -0.97885317099874735725, -0.97781811913825045224, -0.97675862187570339223, -0.97567470569848213646, + -0.97456639770443476145, -0.97343372560120344783, -0.97227671770553181219, -0.97109540294255680681, -0.96988981084508585351, -0.96865997155285932241, -0.96740591581179447012, -0.96612767497322027399, + -0.96482528099309083913, -0.96349876643118781416, -0.96214816445030626468, -0.96077350881542522565, -0.95937483389286415392, -0.95795217464942283847, -0.95650556665150909819, -0.95503504606424649559, + -0.95354064965057394598, -0.95202241477032367722, -0.95048037937928853136, -0.94891458202827316804, -0.94732506186212961374, -0.94571185861877926637, -0.94407501262821902355, -0.94241456481151386626, + -0.94073055667977245609, -0.93902303033311051994, -0.93729202845959747048, -0.93553759433419036995, -0.93375977181765068558, -0.93195860535544849945, -0.93013413997665261856, -0.92828642129280103390, + -0.92641549549676571740, -0.92452140936159377116, -0.92260421023933991691, -0.92066394605988222111, -0.91870066532972438633, -0.91671441713078216651, -0.91470525111915690353, -0.91267321752389507505, + -0.91061836714572963469, -0.90854075135581380263, -0.90644042209443387303, -0.90431743186971202952, -0.90217183375629328435, -0.90000368139401865086, -0.89781302898658432721, -0.89559993130018611396, + -0.89336444366215139734, -0.89110662195955459008, -0.88882652263782058188, -0.88652420269931364594, -0.88419971970191224564, -0.88185313175757040760, -0.87948449753086399561, -0.87709387623752654850, + -0.87468132764296424586, -0.87224691206076765404, -0.86979069035119904729, -0.86731272391967317859, -0.86481307471522173014, -0.86229180522894477434, -0.85974897849244813486, -0.85718465807626731401, + -0.85459890808828042896, -0.85199179317210071982, -0.84936337850546672623, -0.84671372979860781705, -0.84404291329260350274, -0.84135099575772742675, -0.83863804449177770106, -0.83590412731839469629, + -0.83314931258536495395, -0.83037366916291421859, -0.82757726644198292831, -0.82476017433249360078, -0.82192246326160212089, -0.81906420417193759320, -0.81618546851982831658, -0.81328632827351565737, + -0.81036685591135471096, -0.80742712442000219575, -0.80446720729259302285, -0.80148717852690087859, -0.79848711262348970319, -0.79546708458385073648, -0.79242716990852768433, -0.78936744459522911743, + -0.78628798513692810257, -0.78318886851995150877, -0.78007017222205310425, -0.77693197421047766049, -0.77377435294001228883, -0.77059738735102401019, -0.76740115686748722190, -0.76418574139499750864, + -0.76095122131877424021, -0.75769767750165029074, -0.75442519128205276502, -0.75113384447196607230, -0.74782371935488911596, -0.74449489868377749513, -0.74114746567897449303, -0.73778150402613085213, + -0.73439709787411278086, -0.73099433183289752591, -0.72757329097145850838, -0.72413406081564013483, -0.72067672734601673223, -0.71720137699574493251, -0.71370809664840229036, -0.71019697363581579808, + -0.70666809573587785476, -0.70312155117035146645, -0.69955742860266734162, -0.69597581713570333406, -0.69237680630955966699, -0.68876048609931961320, -0.68512694691279985015, -0.68147627958829104511, + -0.67780857539228600572, -0.67412392601719872687, -0.67042242357907078087, -0.66670416061527193463, -0.66296923008218189288, -0.65921772535286937700, -0.65544974021475732595, -0.65166536886727777222, + -0.64786470591951750286, -0.64404784638785206319, -0.64021488569357121179, -0.63636591966049171898, -0.63250104451256550231, -0.62862035687146911034, -0.62472395375419165209, -0.62081193257060796054, + -0.61688439112104398454, -0.61294142759383130059, -0.60898314056285207663, -0.60500962898507726351, -0.60102099219808879926, -0.59701732991759859370, -0.59299874223495496750, -0.58896532961464087563, + -0.58491719289176158370, -0.58085443326952446164, -0.57677715231670834140, -0.57268545196512410378, -0.56857943450706882604, -0.56445920259276427533, -0.56032485922779384779, -0.55617650777052629607, + -0.55201425192953201826, -0.54783819576099013204, -0.54364844366608755521, -0.53944510038840820521, -0.53522827101131453809, -0.53099806095532275929, -0.52675457597546326838, -0.52249792215863943845, + -0.51822820592097507131, -0.51394553400515374797, -0.50965001347775029661, -0.50534175172655326769, -0.50102085645788385637, -0.49668743569389767201, -0.49234159776988828394, -0.48798345133157744469, + -0.48361310533239909581, -0.47923066903077560230, -0.47483625198738627082, -0.47042996406242826302, -0.46601191541286945963, -0.46158221648969754991, -0.45714097803515413299, -0.45268831107996920782, + -0.44822432694058478297, -0.44374913721637188058, -0.43926285378684049032, -0.43476558880884264013, -0.43025745471376780626, -0.42573856420473515927, -0.42120903025377121054, -0.41666896609898895765, + -0.41211848524175564989, -0.40755770144385583542, -0.40298672872464680328, -0.39840568135820858542, -0.39381467387048585405, -0.38921382103642837569, -0.38460323787711647725, -0.37998303965688906558, + -0.37535334188046098891, -0.37071426029003556879, -0.36606591086241091482, -0.36140840980608057720, -0.35674187355832848167, -0.35206641878231687004, -0.34738216236417329696, -0.34268922141006341597, + -0.33798771324326665200, -0.33327775540124238152, -0.32855946563269122773, -0.32383296189461174830, -0.31909836234935112786, -0.31435578536165070807, -0.30960534949568974117, -0.30484717351211659819, + -0.30008137636508314117, -0.29530807719926976951, -0.29052739534690708023, -0.28573945032479231010, -0.28094436183130161444, -0.27614224974339685037, -0.27133323411363174937, -0.26651743516714571092, + -0.26169497329866164836, -0.25686596906947500862, -0.25203054320444007175, -0.24718881658895158759, -0.24234091026592280427, -0.23748694543275927771, -0.23262704343832818488, -0.22776132577992797001, + -0.22288991410024580619, -0.21801293018431996962, -0.21313049595649438683, -0.20824273347737040640, -0.20334976494075546194, -0.19845171267060812692, -0.19354869911797917270, -0.18864084685795379226, + -0.18372827858658200006, -0.17881111711781472184, -0.17388948538043255687, -0.16896350641497262512, -0.16403330337065250011, -0.15909899950229147714, -0.15416071816722845544, -0.14921858282224129133, + -0.14427271702045540991, -0.13932324440825819001, -0.13437028872220715958, -0.12941397378593655354, -0.12445442350706158174, -0.11949176187408093452, -0.11452611295327697061, -0.10955760088561317112, + -0.10458634988363424423, -0.09961248422835543292, -0.09463612826615905305, -0.08965740640568498065, -0.08467644311472041774, -0.07969336291708821463, -0.07470829038953377688, -0.06972135015860976559, + -0.06473266689756400349, -0.05974236532321727799, -0.05475057019284905457, -0.04975740630107760437, -0.04476299847674015953, -0.03976747157977219421, -0.03477095049808595628, -0.02977356014444736479, + -0.02477542545335675514, -0.01977667137792019775, -0.01477742288672922490, -0.00977780496073574201, +}; + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c new file mode 100644 index 0000000..f812084 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2020 ARM Limited. All rights reserved. +* +* $Date: 23. March 2020 +* $Revision: V1.7.0 +* +* Project: CMSIS DSP Library +* Title: arm_linear_interp_example_f32.c +* +* Description: Example code demonstrating usage of sin function +* and uses linear interpolation to get higher precision +* +* Target Processor: Cortex-M55/Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup LinearInterpExample Linear Interpolate Example + * + * CMSIS DSP Software Library -- Linear Interpolate Example + * + * Description + * This example demonstrates usage of linear interpolate modules and fast math modules. + * Method 1 uses fast math sine function to calculate sine values using cubic interpolation and method 2 uses + * linear interpolation function and results are compared to reference output. + * Example shows linear interpolation function can be used to get higher precision compared to fast math sin calculation. + * + * \par Block Diagram: + * \par + * \image html linearInterpExampleMethod1.gif "Method 1: Sine caluclation using fast math" + * \par + * \image html linearInterpExampleMethod2.gif "Method 2: Sine caluclation using interpolation function" + * + * \par Variables Description: + * \par + * \li \c testInputSin_f32 points to the input values for sine calculation + * \li \c testRefSinOutput32_f32 points to the reference values caculated from sin() matlab function + * \li \c testOutput points to output buffer calculation from cubic interpolation + * \li \c testLinIntOutput points to output buffer calculation from linear interpolation + * \li \c snr1 Signal to noise ratio for reference and cubic interpolation output + * \li \c snr2 Signal to noise ratio for reference and linear interpolation output + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_sin_f32() + * - arm_linear_interp_f32() + * + * Refer + * \link arm_linear_interp_example_f32.c \endlink + * + */ + + +/** \example arm_linear_interp_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define SNR_THRESHOLD 90 +#define TEST_LENGTH_SAMPLES 10 +#define XSPACING (0.005f) + +/* ---------------------------------------------------------------------- +* Test input data for F32 SIN function +* Generated by the MATLAB rand() function +* randn('state', 0) +* xi = (((1/4.18318581819710)* randn(blockSize, 1) * 2* pi)); +* --------------------------------------------------------------------*/ +float32_t testInputSin_f32[TEST_LENGTH_SAMPLES] = +{ + -0.649716504673081170, -2.501723745497831200, + 0.188250329003310100, 0.432092748487532540, + -1.722010988459680800, 1.788766476323060600, + 1.786136060975809500, -0.056525543169408797, + 0.491596272728153760, 0.262309671126153390 +}; + +/*------------------------------------------------------------------------------ +* Reference out of SIN F32 function for Block Size = 10 +* Calculated from sin(testInputSin_f32) +*------------------------------------------------------------------------------*/ +float32_t testRefSinOutput32_f32[TEST_LENGTH_SAMPLES] = +{ + -0.604960695383043530, -0.597090287967934840, + 0.187140422442966500, 0.418772124875992690, + -0.988588831792106880, 0.976338412038794010, + 0.976903856413481100, -0.056495446835214236, + 0.472033731854734240, 0.259311907228582830 +}; + +/*------------------------------------------------------------------------------ +* Method 1: Test out Buffer Calculated from Cubic Interpolation +*------------------------------------------------------------------------------*/ +float32_t testOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* Method 2: Test out buffer Calculated from Linear Interpolation +*------------------------------------------------------------------------------*/ +float32_t testLinIntOutput[TEST_LENGTH_SAMPLES]; + +/*------------------------------------------------------------------------------ +* External table used for linear interpolation +*------------------------------------------------------------------------------*/ +extern const float arm_linear_interep_table[1884]; + +/* ---------------------------------------------------------------------- +* Global Variables for caluclating SNR's for Method1 & Method 2 +* ------------------------------------------------------------------- */ +float32_t snr1; +float32_t snr2; + +/* ---------------------------------------------------------------------------- +* Calculation of Sine values from Cubic Interpolation and Linear interpolation +* ---------------------------------------------------------------------------- */ +int32_t main(void) +{ + uint32_t i; + arm_status status; + + arm_linear_interp_instance_f32 S = {1884, -3.141592653589793238, XSPACING, (float*)&arm_linear_interep_table[0]}; + + /*------------------------------------------------------------------------------ + * Method 1: Test out Calculated from Cubic Interpolation + *------------------------------------------------------------------------------*/ + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testOutput[i] = arm_sin_f32(testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * Method 2: Test out Calculated from Cubic Interpolation and Linear interpolation + *------------------------------------------------------------------------------*/ + + for(i=0; i< TEST_LENGTH_SAMPLES; i++) + { + testLinIntOutput[i] = arm_linear_interp_f32(&S, testInputSin_f32[i]); + } + + /*------------------------------------------------------------------------------ + * SNR calculation for method 1 + *------------------------------------------------------------------------------*/ + snr1 = arm_snr_f32(testRefSinOutput32_f32, testOutput, 2); + + /*------------------------------------------------------------------------------ + * SNR calculation for method 2 + *------------------------------------------------------------------------------*/ + snr2 = arm_snr_f32(testRefSinOutput32_f32, testLinIntOutput, 2); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + status = (snr2 <= snr1) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c new file mode 100644 index 0000000..fce27d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 0000000..a4cf1aa --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_matrix_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt new file mode 100644 index 0000000..0b26942 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_matrix_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_matrix_example) + + +include(config) +configApp(arm_matrix_example ${ROOT}) + +target_sources(arm_matrix_example PRIVATE math_helper.c arm_matrix_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_matrix_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 0000000..c292610 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_matrix_example_f32.c +* +* Description: Example code demonstrating least square fit to data +* using matrix functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup MatrixExample Matrix Example + * + * \par Description: + * \par + * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse + * functions to apply least squares fitting to input data. Least squares fitting is + * the procedure for finding the best-fitting curve that minimizes the sum of the + * squares of the offsets (least square error) from a given set of data. + * + * \par Algorithm: + * \par + * The linear combination of parameters considered is as follows: + * \par + * A * X = B, where \c X is the unknown value and can be estimated + * from \c A & \c B. + * \par + * The least squares estimate \c X is given by the following equation: + * \par + * X = Inverse(AT * A) * AT * B + * + * \par Block Diagram: + * \par + * + * \par Variables Description: + * \par + * \li \c A_f32 input matrix in the linear combination equation + * \li \c B_f32 output matrix in the linear combination equation + * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_mat_init_f32() + * - arm_mat_trans_f32() + * - arm_mat_mult_f32() + * - arm_mat_inverse_f32() + * + * Refer + * \link arm_matrix_example_f32.c \endlink + * + */ + + +/** \example arm_matrix_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +#define SNR_THRESHOLD 90 + +/* -------------------------------------------------------------------------------- +* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize +* and tapSize +* --------------------------------------------------------------------------------- */ + +const float32_t B_f32[4] = +{ + 782.0, 7577.0, 470.0, 4505.0 +}; + +/* -------------------------------------------------------------------------------- +* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize +* -------------------------------------------------------------------------------- */ + +const float32_t A_f32[16] = +{ + /* Const, numTaps, blockSize, numTaps*blockSize */ + 1.0, 32.0, 4.0, 128.0, + 1.0, 32.0, 64.0, 2048.0, + 1.0, 16.0, 4.0, 64.0, + 1.0, 16.0, 64.0, 1024.0, +}; + + +/* ---------------------------------------------------------------------- +* Temporary buffers for storing intermediate values +* ------------------------------------------------------------------- */ +/* Transpose of A Buffer */ +float32_t AT_f32[16]; +/* (Transpose of A * A) Buffer */ +float32_t ATMA_f32[16]; +/* Inverse(Transpose of A * A) Buffer */ +float32_t ATMAI_f32[16]; +/* Test Output Buffer */ +float32_t X_f32[4]; + +/* ---------------------------------------------------------------------- +* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB +* ------------------------------------------------------------------- */ +const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875}; + +float32_t snr; + + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + + arm_matrix_instance_f32 A; /* Matrix A Instance */ + arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */ + arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */ + arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */ + arm_matrix_instance_f32 B; /* Matrix B instance */ + arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */ + + uint32_t srcRows, srcColumns; /* Temporary variables */ + arm_status status; + + /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32); + + /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32); + + /* calculation of A transpose */ + status = arm_mat_trans_f32(&A, &AT); + + + /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32); + + /* calculation of AT Multiply with A */ + status = arm_mat_mult_f32(&AT, &A, &ATMA); + + /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */ + srcRows = 4; + srcColumns = 4; + arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32); + + /* calculation of Inverse((Transpose(A) * A) */ + status = arm_mat_inverse_f32(&ATMA, &ATMAI); + + /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */ + status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA); + + /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32); + + /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */ + srcRows = 4; + srcColumns = 1; + arm_mat_init_f32(&X, srcRows, srcColumns, X_f32); + + /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */ + status = arm_mat_mult_f32(&ATMA, &B, &X); + + /* Comparison of reference with test output */ + snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4); + + /*------------------------------------------------------------------------------ + * Initialise status depending on SNR calculations + *------------------------------------------------------------------------------*/ + status = (snr < SNR_THRESHOLD) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c new file mode 100644 index 0000000..f62043d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c @@ -0,0 +1,473 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} +#endif + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt new file mode 100644 index 0000000..1180b89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_signal_converge_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt new file mode 100644 index 0000000..e516758 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_signal_convergence_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_signal_convergence_example) + + +include(config) +configApp(arm_signal_convergence_example ${ROOT}) + +target_sources(arm_signal_convergence_example PRIVATE math_helper.c arm_signal_converge_data.c arm_signal_converge_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_signal_convergence_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c new file mode 100644 index 0000000..ddb1278 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_data.c +* +* Description: Test input data for Floating point LMS Norm FIR filter +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +** Test input data for Floating point LMS Norm FIR filter +** Generated by the MATLAB randn() function +** ------------------------------------------------------------------- */ + +float32_t testInput_f32[1536] = +{ +-0.432565, -1.665584, 0.125332, 0.287676, -1.146471, 1.190915, 1.189164, -0.037633, +0.327292, 0.174639, -0.186709, 0.725791, -0.588317, 2.183186, -0.136396, 0.113931, +1.066768, 0.059281, -0.095648, -0.832349, 0.294411, -1.336182, 0.714325, 1.623562, +-0.691776, 0.857997, 1.254001, -1.593730, -1.440964, 0.571148, -0.399886, 0.689997, +0.815622, 0.711908, 1.290250, 0.668601, 1.190838, -1.202457, -0.019790, -0.156717, +-1.604086, 0.257304, -1.056473, 1.415141, -0.805090, 0.528743, 0.219321, -0.921902, +-2.170674, -0.059188, -1.010634, 0.614463, 0.507741, 1.692430, 0.591283, -0.643595, +0.380337, -1.009116, -0.019511, -0.048221, 0.000043, -0.317859, 1.095004, -1.873990, +0.428183, 0.895638, 0.730957, 0.577857, 0.040314, 0.677089, 0.568900, -0.255645, +-0.377469, -0.295887, -1.475135, -0.234004, 0.118445, 0.314809, 1.443508, -0.350975, +0.623234, 0.799049, 0.940890, -0.992092, 0.212035, 0.237882, -1.007763, -0.742045, +1.082295, -0.131500, 0.389880, 0.087987, -0.635465, -0.559573, 0.443653, -0.949904, +0.781182, 0.568961, -0.821714, -0.265607, -1.187777, -2.202321, 0.986337, -0.518635, +0.327368, 0.234057, 0.021466, -1.003944, -0.947146, -0.374429, -1.185886, -1.055903, +1.472480, 0.055744, -1.217317, -0.041227, -1.128344, -1.349278, -0.261102, 0.953465, +0.128644, 0.656468, -1.167819, -0.460605, -0.262440, -1.213152, -1.319437, 0.931218, +0.011245, -0.645146, 0.805729, 0.231626, -0.989760, 1.339586, 0.289502, 1.478917, +1.138028, -0.684139, -1.291936, -0.072926, -0.330599, -0.843628, 0.497770, 1.488490, +-0.546476, -0.846758, -0.246337, 0.663024, -0.854197, -1.201315, -0.119869, -0.065294, +0.485296, -0.595491, -0.149668, -0.434752, -0.079330, 1.535152, -0.606483, -1.347363, +0.469383, -0.903567, 0.035880, -0.627531, 0.535398, 0.552884, -0.203690, -2.054325, +0.132561, 1.592941, 1.018412, -1.580402, -0.078662, -0.681657, -1.024553, -1.234353, +0.288807, -0.429303, 0.055801, -0.367874, -0.464973, 0.370961, 0.728283, 2.112160, +-1.357298, -1.022610, 1.037834, -0.389800, -1.381266, 0.315543, 1.553243, 0.707894, +1.957385, 0.504542, 1.864529, -0.339812, -1.139779, -0.211123, 1.190245, -1.116209, +0.635274, -0.601412, 0.551185, -1.099840, 0.085991, -2.004563, -0.493088, 0.462048, +-0.321005, 1.236556, -0.631280, -2.325211, -1.231637, 1.055648, -0.113224, 0.379224, +0.944200, -2.120427, -0.644679, -0.704302, -1.018137, -0.182082, 1.521013, -0.038439, +1.227448, -0.696205, 0.007524, -0.782893, 0.586939, -0.251207, 0.480136, 0.668155, +-0.078321, 0.889173, 2.309287, 0.524639, -0.011787, 0.913141, 0.055941, -1.107070, +0.485498, -0.005005, -0.276218, 1.276452, 1.863401, -0.522559, 0.103424, -0.807649, +0.680439, -2.364590, 0.990115, 0.218899, 0.261662, 1.213444, -0.274667, -0.133134, +-1.270500, -1.663606, -0.703554, 0.280880, -0.541209, -1.333531, 1.072686, -0.712085, +-0.011286, -0.000817, -0.249436, 0.396575, -0.264013, -1.664011, -1.028975, 0.243095, +-1.256590, -0.347183, -0.941372, -1.174560, -1.021142, -0.401667, 0.173666, -0.116118, +1.064119, -0.245386, -1.517539, 0.009734, 0.071373, 0.316536, 0.499826, 1.278084, +-0.547816, 0.260808, -0.013177, -0.580264, 2.136308, -0.257617, -1.409528, 1.770101, +0.325546, -1.119040, 0.620350, 1.269782, -0.896043, 0.135175, -0.139040, -1.163395, +1.183720, -0.015430, 0.536219, -0.716429, -0.655559, 0.314363, 0.106814, 1.848216, +-0.275106, 2.212554, 1.508526, -1.945079, -1.680543, -0.573534, -0.185817, 0.008934, +0.836950, -0.722271, -0.721490, -0.201181, -0.020464, 0.278890, 1.058295, 0.621673, +-1.750615, 0.697348, 0.811486, 0.636345, 1.310080, 0.327098, -0.672993, -0.149327, +-2.449018, 0.473286, 0.116946, -0.591104, -0.654708, -1.080662, -0.047731, 0.379345, +-0.330361, -0.499898, -0.035979, -0.174760, -0.957265, 1.292548, 0.440910, 1.280941, +-0.497730, -1.118717, 0.807650, 0.041200, -0.756209, -0.089129, -2.008850, 1.083918, +-0.981191, -0.688489, 1.339479, -0.909243, -0.412858, -0.506163, 1.619748, 0.080901, +-1.081056, -1.124518, 1.735676, 1.937459, 1.635068, -1.255940, -0.213538, -0.198932, +0.307499, -0.572325, -0.977648, -0.446809, 1.082092, 2.372648, 0.229288, -0.266623, +0.701672, -0.487590, 1.862480, 1.106851, -1.227566, -0.669885, 1.340929, 0.388083, +0.393059, -1.707334, 0.227859, 0.685633, -0.636790, -1.002606, -0.185621, -1.054033, +-0.071539, 0.279198, 1.373275, 0.179841, -0.542017, 1.634191, 0.825215, 0.230761, +0.671634, -0.508078, 0.856352, 0.268503, 0.624975, -1.047338, 1.535670, 0.434426, +-1.917136, 0.469940, 1.274351, 0.638542, 1.380782, 1.319843, -0.909429, -2.305605, +1.788730, 0.390798, 0.020324, -0.405977, -1.534895, 0.221373, -1.374479, -0.839286, +-0.208643, 0.755913, 0.375734, -1.345413, 1.481876, 0.032736, 1.870453, -1.208991, +-0.782632, -0.767299, -0.107200, -0.977057, -0.963988, -2.379172, -0.838188, 0.257346, +-0.183834, -0.167615, -0.116989, 0.168488, -0.501206, -0.705076, 0.508165, -0.420922, +0.229133, -0.959497, -0.146043, 0.744538, -0.890496, 0.139062, -0.236144, -0.075459, +-0.358572, -2.077635, -0.143546, 1.393341, 0.651804, -0.377134, -0.661443, 0.248958, +-0.383516, -0.528480, 0.055388, 1.253769, -2.520004, 0.584856, -1.008064, 0.944285, +-2.423957, -0.223831, 0.058070, -0.424614, -0.202918, -1.513077, -1.126352, -0.815002, +0.366614, -0.586107, 1.537409, 0.140072, -1.862767, -0.454193, -0.652074, 0.103318, +-0.220632, -0.279043, -0.733662, -0.064534, -1.444004, 0.612340, -1.323503, -0.661577, +-0.146115, 0.248085, -0.076633, 1.738170, 1.621972, 0.626436, 0.091814, -0.807607, +-0.461337, -1.405969, -0.374530, -0.470911, 1.751296, 0.753225, 0.064989, -0.292764, +0.082823, 0.766191, 2.236850, 0.326887, 0.863304, 0.679387, 0.554758, 1.001630, +1.259365, 0.044151, -0.314138, 0.226708, 0.996692, 1.215912, -0.542702, 0.912228, +-0.172141, -0.335955, 0.541487, 0.932111, -0.570253, -1.498605, -0.050346, 0.553025, +0.083498, 1.577524, -0.330774, 0.795155, -0.784800, -1.263121, 0.666655, -1.392632, +-1.300562, -0.605022, -1.488565, 0.558543, -0.277354, -1.293685, -0.888435, -0.986520, +-0.071618, -2.414591, -0.694349, -1.391389, 0.329648, 0.598544, 0.147175, -0.101439, +-2.634981, 0.028053, -0.876310, -0.265477, -0.327578, -1.158247, 0.580053, 0.239756, +-0.350885, 0.892098, 1.578299, -1.108174, -0.025931, -1.110628, 0.750834, 0.500167, +-0.517261, -0.559209, -0.753371, 0.925813, -0.248520, -0.149835, -1.258415, 0.312620, +2.690277, 0.289696, -1.422803, 0.246786, -1.435773, 0.148573, -1.693073, 0.719188, +1.141773, 1.551936, 1.383630, -0.758092, 0.442663, 0.911098, -1.074086, 0.201762, +0.762863, -1.288187, -0.952962, 0.778175, -0.006331, 0.524487, 1.364272, 0.482039, +-0.787066, 0.751999, -0.166888, -0.816228, 2.094065, 0.080153, -0.937295, 0.635739, +1.682028, 0.593634, 0.790153, 0.105254, -0.158579, 0.870907, -0.194759, 0.075474, +-0.526635, -0.685484, -0.268388, -1.188346, 0.248579, 0.102452, -0.041007, -2.247582, +-0.510776, 0.249243, 0.369197, 0.179197, -0.037283, -1.603310, 0.339372, -0.131135, +0.485190, 0.598751, -0.086031, 0.325292, -0.335143, -0.322449, -0.382374, -0.953371, +0.233576, 1.235245, -0.578532, -0.501537, 0.722864, 0.039498, 1.541279, -1.701053, +-1.033741, -0.763708, 2.176426, 0.431612, -0.443765, 0.029996, -0.315671, 0.977846, +0.018295, 0.817963, 0.702341, -0.231271, -0.113690, 0.127941, -0.799410, -0.238612, +-0.089463, -1.023264, 0.937538, -1.131719, -0.710702, -1.169501, 1.065437, -0.680394, +-1.725773, 0.813200, 1.441867, 0.672272, 0.138665, -0.859534, -0.752251, 1.229615, +1.150754, -0.608025, 0.806158, 0.217133, -0.373461, -0.832030, 0.286866, -1.818892, +-1.573051, 2.015666, -0.071982, 2.628909, -0.243317, 0.173276, 0.923207, -0.178553, +-0.521705, 1.431962, -0.870117, 0.807542, -0.510635, 0.743514, 0.847898, -0.829901, +0.532994, 1.032848, -1.052024, 0.362114, -0.036787, -1.227636, -0.275099, -0.160435, +-1.083575, -1.954213, -0.909487, -0.005579, -1.723490, 1.263077, -0.600433, -2.063925, +0.110911, 1.487614, 0.053002, 0.161981, -0.026878, 0.173576, 0.882168, 0.182294, +0.755295, 0.508035, 0.131880, 0.280104, -0.982848, -0.944087, -0.013058, 0.354345, +-0.894709, 0.812111, 0.109537, 2.731644, 0.411079, -1.306862, 0.383806, 0.499504, +-0.510786, 0.234922, -0.597825, 0.020771, 0.419443, 1.191104, 0.771214, -2.644222, +0.285430, 0.826093, -0.008122, 0.858438, 0.774788, 1.305945, 1.231503, 0.958564, +-1.654548, -0.990396, 0.685236, -0.974870, -0.606726, 0.686794, 0.020049, 1.063801, +-1.341050, 0.479510, -1.633974, -1.442665, 0.293781, -0.140364, -1.130341, -0.292538, +-0.582536, -0.896348, 0.248601, -1.489663, 0.313509, -2.025084, 0.528990, 0.343471, +0.758193, -0.691940, 0.680179, -1.072541, 0.899772, -2.123092, 0.284712, -0.733323, +-0.773376, 0.151842, -0.336843, 0.970761, -0.107236, 1.013492, -0.475347, 0.068948, +0.398592, 1.116326, 0.620451, -0.287674, -1.371773, -0.685868, 0.331685, -0.997722, +0.291418, 1.107078, 0.244959, 0.164976, 0.406231, 1.215981, 1.448424, -1.025137, +0.205418, 0.588882, -0.264024, 2.495318, 0.855948, -0.850954, 0.811879, 0.700242, +0.759938, -1.712909, 1.537021, -1.609847, 1.109526, -1.109704, 0.385469, 0.965231, +0.818297, 0.037049, -0.926012, -0.111919, -0.803030, -1.665006, -0.901401, 0.588350, +0.554159, -0.415173, 0.061795, 0.457432, 0.199014, 0.257558, 2.080730, -2.277237, +0.339022, 0.289894, 0.662261, -0.580860, 0.887752, 0.171871, 0.848821, 0.963769, +1.321918, -0.064345, 1.317053, 0.228017, -1.429637, -0.149701, -0.504968, -1.729141, +-0.417472, -0.614969, 0.720777, 0.339364, 0.882845, 0.284245, -0.145541, -0.089646, +0.289161, 1.164831, 0.805729, -1.355643, 0.120893, -0.222178, 0.571732, -0.300140, +1.134277, -0.179356, -1.467067, 1.395346, 0.440836, 0.565384, -0.693623, 0.833869, +-2.237378, 1.097644, -0.001617, -1.614573, -1.228727, 0.207405, 0.220942, -1.006073, +-0.453067, 1.399453, -0.461964, 0.032716, 0.798783, 0.896816, 0.137892, -1.619146, +-1.646606, 0.428707, -0.737231, 0.564926, -1.384167, 0.460268, 0.629384, 0.379847, +-1.013330, -0.347243, 0.441912, -1.590240, -0.701417, -1.077601, 1.002220, 1.729481, +0.709032, -0.747897, 0.228862, -0.223497, -0.853275, 0.345627, 0.109764, -1.133039, +-0.683124, -0.277856, 0.654790, -1.248394, -0.597539, -0.481813, 0.983372, 1.762121, +1.427402, 0.911763, 0.326823, 0.069619, -1.499763, -0.418223, -0.021037, 0.228425, +-1.008196, -0.664622, 0.558177, -1.188542, -0.775481, 0.271042, 1.534976, -1.052283, +0.625559, -0.797626, -0.313522, -0.602210, 1.259060, 0.858484, -2.105292, -0.360937, +0.553557, -1.556384, -0.206666, -0.425568, 0.493778, -0.870908, 0.079828, -0.521619, +-1.413861, -0.384293, -0.457922, -0.291471, -0.301224, -1.588594, 1.094287, 1.324167, +-0.126480, -0.737164, 0.213719, -0.400529, 0.064938, -1.757996, 1.686748, 0.327400, +0.715967, 1.598648, -2.064741, -0.743632, 0.176185, 0.527839, -0.553153, 0.298280, +-1.226607, -0.189676, -0.301713, 0.956956, -0.533366, -0.901082, -0.892552, 0.278717, +-0.745807, 1.603464, 0.574270, 0.320655, -0.151383, 0.315762, 1.343703, -2.237832, +1.292906, -0.378459, 0.002521, 0.884641, 0.582450, -1.614244, -1.503666, 0.573586, +-0.910537, -1.631277, -0.359138, -0.397616, -1.161307, -1.109838, 0.290672, -1.910239, +1.314768, 0.665319, -0.275115, -0.023022, -0.907976, -1.043657, 0.373516, 0.901532, +1.278539, -0.128456, 0.612821, 1.956518, 2.266326, -0.373959, 2.238039, -0.159580, +-0.703281, 0.563477, -0.050296, 1.163593, 0.658808, -1.550089, -3.029118, 0.540578, +-1.008998, 0.908047, 1.582303, -0.979088, 1.007902, 0.158491, -0.586927, 1.574082, +-0.516649, 1.227800, 1.583876, -2.088950, 2.949545, 1.356125, 1.050068, -0.767170, +-0.257653, -1.371845, -1.267656, -0.894948, 0.589089, 1.842629, 1.347967, -0.491253, +-2.177568, 0.237000, -0.735411, -1.779419, 0.448030, 0.581214, 0.856607, -0.266263, +-0.417470, -0.205806, -0.174323, 0.217577, 1.684295, 0.119528, 0.650667, 2.080061, +-0.339225, 0.730113, 0.293969, -0.849109, -2.533858, -2.378941, -0.346276, -0.610937, +-0.408192, -1.415611, 0.227122, 0.207974, -0.719718, 0.757762, -1.643135, -1.056813, +-0.251662, -1.298441, 1.233255, 1.494625, 0.235938, -1.404359, 0.658791, -2.556613, +-0.534945, 3.202525, 0.439198, -1.149901, 0.886765, -0.283386, 1.035336, -0.364878, +1.341987, 1.008872, 0.213874, -0.299264, 0.255849, -0.190826, -0.079060, 0.699851, +-0.796540, -0.801284, -0.007599, -0.726810, -1.490902, 0.870335, -0.265675, -1.566695, +-0.394636, -0.143855, -2.334247, -1.357539, -1.815689, 1.108422, -0.142115, 1.112757, +0.559264, 0.478370, -0.679385, 0.284967, -1.332935, -0.723980, -0.663600, 0.198443, +-1.794868, -1.387673, 0.197768, 1.469328, 0.366493, -0.442775, -0.048563, 0.077709, +1.957910, -0.072848, 0.938810, -0.079608, -0.800959, 0.309424, 1.051826, -1.664211, +-1.090792, -0.191731, 0.463401, -0.924147, -0.649657, 0.622893, -1.335107, 1.047689, +0.863327, -0.642411, 0.660010, 1.294116, 0.314579, 0.859573, 0.128670, 0.016568, +-0.072801, -0.994310, -0.747358, -0.030814, 0.988355, -0.599017, 1.476644, -0.813801, +0.645040, -1.309919, -0.867425, -0.474233, 0.222417, 1.871323, 0.110001, -0.411341, +0.511242, -1.199117, -0.096361, 0.445817, -0.295825, -0.167996, 0.179543, 0.421118, +1.677678, 1.996949, 0.696964, -1.366382, 0.363045, -0.567044, -1.044154, 0.697139, +0.484026, -0.193751, -0.378095, -0.886374, -1.840197, -1.628195, -1.173789, -0.415411, +0.175088, 0.229433, -1.240889, 0.700004, 0.426877, 1.454803, -0.510186, -0.006657, +-0.525496, 0.717698, 1.088374, 0.500552, 2.771790, -0.160309, 0.429489, -1.966817, +-0.546019, -1.888395, -0.107952, -1.316144, -0.672632, -0.902365, -0.154798, 0.947242, +1.550375, 0.429040, -0.560795, 0.179304, -0.771509, -0.943390, -1.407569, -1.906131, +-0.065293, 0.672149, 0.206147, -0.008124, 0.020042, -0.558447, 1.886079, -0.219975, +-1.414395, -0.302811, -0.569574, -0.121495, -0.390171, -0.844287, -1.737757, -0.449520, +-1.547933, -0.095776, 0.907714, 2.369602, 0.519768, 0.410525, 1.052585, 0.428784, +1.295088, -0.186053, 0.130733, -0.657627, -0.759267, -0.595170, 0.812400, 0.069541, +-1.833687, 1.827363, 0.654075, -1.544769, -0.375109, 0.207688, -0.765615, -0.106355, +0.338769, 1.033461, -1.404822, -1.030570, -0.643372, 0.170787, 1.344839, 1.936273, +0.741336, 0.811980, -0.142808, -0.099858, -0.800131, 0.493249, 1.237574, 1.295951, +-0.278196, 0.217127, 0.630728, -0.548549, 0.229632, 0.355311, 0.521284, -0.615971, +1.345803, 0.974922, -2.377934, -1.092319, -0.325710, -2.012228, 1.567660, 0.233337, +0.646420, -1.129412, 0.197038, 1.696870, 0.726034, 0.792526, 0.603357, -0.058405, +-1.108666, 2.144229, -1.352821, 0.457021, 0.391175, 2.073013, -0.323318, 1.468132, +-0.502399, 0.209593, 0.754800, -0.948189, 0.613157, 1.760503, 0.088762, 2.595570, +-0.675470, 2.786804, -0.016827, 0.271651, -0.914102, -1.951371, -0.317418, 0.588333, +0.828996, -1.674851, -1.922293, -0.436662, 0.044974, 2.416609, -0.309892, 0.187583, +0.947699, -0.525703, -1.115605, -1.592320, 1.174844, 0.485144, 1.645480, -0.454233, +1.008768, 2.049403, 0.602020, 0.017860, -1.610426, 1.238752, 0.683587, -0.780716, +0.530979, 2.134498, 0.354361, 0.231700, 1.287980, -0.013488, -1.333345, -0.556343, +0.755597, -0.911854, 1.371684, 0.245580, 0.118845, 0.384690, -0.070152, -0.578309, +0.469308, 1.299687, 1.634798, -0.702809, 0.807253, -1.027451, 1.294496, 0.014930, +0.218705, 1.713188, -2.078805, 0.112917, -1.086491, -1.558311, 0.637406, -0.404576, +-0.403325, 0.084076, -0.435349, -0.562623, 0.878062, -0.814650, -0.258363, 0.493299, +-0.802694, -0.008329, 0.627571, 0.154382, 2.580735, -1.306246, 1.023526, 0.777795, +-0.833884, -0.586663, 0.065664, -0.012342, -0.076987, -1.558587, 1.702607, -0.468984, +0.094619, 0.287071, 0.919354, 0.510136, 0.245440, -1.400519, 0.969571, 1.593698, +-1.437917, -1.534230, -0.074710, 0.081459, -0.843240, -0.564640, -0.028207, -1.243702, +0.733039, 0.059580, 0.149144, 1.595857, -0.777250, 1.550277, 1.055002, -0.166654, +0.314484, 1.419571, 0.327348, 0.475653, 0.398754, -0.072770, 1.314784, 0.978279, +1.722114, -0.412302, 0.565133, 0.739851, 0.220138, 1.312807, 0.629152, -1.107987, +-0.447001, -0.725993, 0.354045, -0.506772, -2.103747, -0.664684, 1.450110, -0.329805, +2.701872, -1.634939, -0.536325, 0.547223, 1.492603, -0.455243, -0.496416, 1.235260, +0.040926, 0.748467, 1.230764, 0.304903, 1.077771, 0.765151, -1.319580, -0.509191, +0.555116, -1.957625, -0.760453, -2.443886, -0.659366, -0.114779, 0.300079, -0.583996, +-3.073745, 1.551042, -0.407369, 1.428095, -1.353242, 0.903970, 0.541671, -0.465020 +}; + + + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point LMS FIR filter +* FIR high pass filter with cutoff freq 9.6kHz (transition 9.6KHz to 11.52KHz) +** ------------------------------------------------------------------- */ +float32_t lmsNormCoeff_f32[32] = { +-0.004240, 0.002301, 0.008860, -0.000000, -0.019782, -0.010543, 0.032881, 0.034736, +-0.037374, -0.069586, 0.022397, 0.102169, 0.014185, -0.115908, -0.061648, 0.101018, +0.101018, -0.061648, -0.115908, 0.014185, 0.102169, 0.022397, -0.069586, -0.037374, +0.034736, 0.032881, -0.010543, -0.019782, -0.000000, 0.008860, 0.002301, -0.004240 + +}; + +/* ---------------------------------------------------------------------- +** Coefficients for 32-tap filter for Floating point FIR filter +* FIR low pass filter with cutoff freq 24Hz (transition 24Hz to 240Hz) +** ------------------------------------------------------------------- */ +const float32_t FIRCoeff_f32[32] = { +0.004502, 0.005074, 0.006707, 0.009356, 0.012933, 0.017303, 0.022298, 0.027717, +0.033338, 0.038930, 0.044258, 0.049098, 0.053243, 0.056519, 0.058784, 0.059941, +0.059941, 0.058784, 0.056519, 0.053243, 0.049098, 0.044258, 0.038930, 0.033338, +0.027717, 0.022298, 0.017303, 0.012933, 0.009356, 0.006707, 0.005074, 0.004502 + +}; + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c new file mode 100644 index 0000000..155c001 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_signal_converge_example_f32.c +* +* Description: Example code demonstrating convergence of an adaptive +* filter. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SignalConvergence Signal Convergence Example + * + * \par Description: + * \par + * Demonstrates the ability of an adaptive filter to "learn" the transfer function of + * a FIR lowpass filter using the Normalized LMS Filter, Finite Impulse + * Response (FIR) Filter, and Basic Math Functions. + * + * \par Algorithm: + * \par + * The figure below illustrates the signal flow in this example. Uniformly distributed white + * noise is passed through an FIR lowpass filter. The output of the FIR filter serves as the + * reference input of the adaptive filter (normalized LMS filter). The white noise is input + * to the adaptive filter. The adaptive filter learns the transfer function of the FIR filter. + * The filter outputs two signals: (1) the output of the internal adaptive FIR filter, and + * (2) the error signal which is the difference between the adaptive filter and the reference + * output of the FIR filter. Over time as the adaptive filter learns the transfer function + * of the FIR filter, the first output approaches the reference output of the FIR filter, + * and the error signal approaches zero. + * \par + * The adaptive filter converges properly even if the input signal has a large dynamic + * range (i.e., varies from small to large values). The coefficients of the adaptive filter + * are initially zero, and then converge over 1536 samples. The internal function test_signal_converge() + * implements the stopping condition. The function checks if all of the values of the error signal have a + * magnitude below a threshold DELTA. + * + * \par Block Diagram: + * \par + * \image html SignalFlow.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c firStateF32 points to FIR state buffer + * \li \c lmsStateF32 points to Normalised Least mean square FIR filter state buffer + * \li \c FIRCoeff_f32 points to coefficient buffer + * \li \c lmsNormCoeff_f32 points to Normalised Least mean square FIR filter coefficient buffer + * \li \c wire1, wir2, wire3 temporary buffers + * \li \c errOutput, err_signal temporary error buffers + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_lms_norm_init_f32() + * - arm_fir_init_f32() + * - arm_fir_f32() + * - arm_lms_norm_f32() + * - arm_scale_f32() + * - arm_abs_f32() + * - arm_sub_f32() + * - arm_min_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_signal_converge_example_f32.c \endlink + * + */ + + +/** \example arm_signal_converge_example_f32.c + */ + +#include "arm_math.h" +#include "math_helper.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +** Global defines for the simulation +* ------------------------------------------------------------------- */ + +#define TEST_LENGTH_SAMPLES 1536 +#define NUMTAPS 32 +#define BLOCKSIZE 32 +#define DELTA_ERROR 0.00009f +#define DELTA_COEFF 0.0001f +#define MU 0.5f + +#define NUMFRAMES (TEST_LENGTH_SAMPLES / BLOCKSIZE) + +/* ---------------------------------------------------------------------- +* Declare FIR state buffers and structure +* ------------------------------------------------------------------- */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +float32_t firStateF32[2 * BLOCKSIZE + NUMTAPS - 1]; +#else +float32_t firStateF32[NUMTAPS + BLOCKSIZE]; +#endif + +arm_fir_instance_f32 LPF_instance; + +/* ---------------------------------------------------------------------- +* Declare LMSNorm state buffers and structure +* ------------------------------------------------------------------- */ + +float32_t lmsStateF32[NUMTAPS + BLOCKSIZE]; +float32_t errOutput[TEST_LENGTH_SAMPLES]; +arm_lms_norm_instance_f32 lmsNorm_instance; + + +/* ---------------------------------------------------------------------- +* Function Declarations for Signal Convergence Example +* ------------------------------------------------------------------- */ + +arm_status test_signal_converge_example( void ); + + +/* ---------------------------------------------------------------------- +* Internal functions +* ------------------------------------------------------------------- */ +arm_status test_signal_converge(float32_t* err_signal, + uint32_t blockSize); + +void getinput(float32_t* input, + uint32_t fr_cnt, + uint32_t blockSize); + +/* ---------------------------------------------------------------------- +* External Declarations for FIR F32 module Test +* ------------------------------------------------------------------- */ +extern float32_t testInput_f32[TEST_LENGTH_SAMPLES]; +extern float32_t lmsNormCoeff_f32[32]; +extern const float32_t FIRCoeff_f32[32]; +extern arm_lms_norm_instance_f32 lmsNorm_instance; + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ + +float32_t wire1[BLOCKSIZE]; +float32_t wire2[BLOCKSIZE]; +float32_t wire3[BLOCKSIZE]; +float32_t err_signal[BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Signal converge test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + uint32_t i; + arm_status status; + uint32_t index; + float32_t minValue; + + /* Initialize the LMSNorm data structure */ + arm_lms_norm_init_f32(&lmsNorm_instance, NUMTAPS, lmsNormCoeff_f32, lmsStateF32, MU, BLOCKSIZE); + + /* Initialize the FIR data structure */ + arm_fir_init_f32(&LPF_instance, NUMTAPS, (float32_t *)FIRCoeff_f32, firStateF32, BLOCKSIZE); + + /* ---------------------------------------------------------------------- + * Loop over the frames of data and execute each of the processing + * functions in the system. + * ------------------------------------------------------------------- */ + + for(i=0; i < NUMFRAMES; i++) + { + /* Read the input data - uniformly distributed random noise - into wire1 */ + arm_copy_f32(testInput_f32 + (i * BLOCKSIZE), wire1, BLOCKSIZE); + + /* Execute the FIR processing function. Input wire1 and output wire2 */ + arm_fir_f32(&LPF_instance, wire1, wire2, BLOCKSIZE); + + /* Execute the LMS Norm processing function*/ + + arm_lms_norm_f32(&lmsNorm_instance, /* LMSNorm instance */ + wire1, /* Input signal */ + wire2, /* Reference Signal */ + wire3, /* Converged Signal */ + err_signal, /* Error Signal, this will become small as the signal converges */ + BLOCKSIZE); /* BlockSize */ + + /* apply overall gain */ + arm_scale_f32(wire3, 5, wire3, BLOCKSIZE); /* in-place buffer */ + } + + status = ARM_MATH_SUCCESS; + + /* ------------------------------------------------------------------------------- + * Test whether the error signal has reached towards 0. + * ----------------------------------------------------------------------------- */ + + arm_abs_f32(err_signal, err_signal, BLOCKSIZE); + arm_min_f32(err_signal, BLOCKSIZE, &minValue, &index); + + if (minValue > DELTA_ERROR) + { + status = ARM_MATH_TEST_FAILURE; + } + + /* ---------------------------------------------------------------------- + * Test whether the filter coefficients have converged. + * ------------------------------------------------------------------- */ + + arm_sub_f32((float32_t *)FIRCoeff_f32, lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + + arm_abs_f32(lmsNormCoeff_f32, lmsNormCoeff_f32, NUMTAPS); + arm_min_f32(lmsNormCoeff_f32, NUMTAPS, &minValue, &index); + + status = (minValue > DELTA_COEFF) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c new file mode 100644 index 0000000..c87c97d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c @@ -0,0 +1,472 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 b +* +* Project: CMSIS DSP Library +* +* Title: math_helper.c +* +* Description: Definition of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------- +* Include standard header files +* -------------------------------------------------------------------- */ +#include + +/* ---------------------------------------------------------------------- +* Include project header files +* -------------------------------------------------------------------- */ +#include "math_helper.h" + +/** + * @brief Caluclation of SNR + * @param[in] pRef Pointer to the reference buffer + * @param[in] pTest Pointer to the test buffer + * @param[in] buffSize total number of samples + * @return SNR + * The function Caluclates signal to noise ratio for the reference output + * and test output + */ + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize) +{ + float EnergySignal = 0.0, EnergyError = 0.0; + uint32_t i; + float SNR; + int temp; + int *test; + + for (i = 0; i < buffSize; i++) + { + /* Checking for a NAN value in pRef array */ + test = (int *)(&pRef[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + /* Checking for a NAN value in pTest array */ + test = (int *)(&pTest[i]); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + EnergySignal += pRef[i] * pRef[i]; + EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]); + } + + /* Checking for a NAN value in EnergyError */ + test = (int *)(&EnergyError); + temp = *test; + + if (temp == 0x7FC00000) + { + return(0); + } + + + SNR = 10 * log10 (EnergySignal / EnergyError); + + return (SNR); + +} + + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Converts float to fixed in q12.20 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to outputbuffer + * @param[in] numSamples number of samples in the input buffer + * @return none + * The function converts floating point values to fixed point(q12.20) values + */ + +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1048576.0f corresponds to pow(2, 20) */ + pOut[i] = (q31_t) (pIn[i] * 1048576.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 1.0) + { + pOut[i] = 0x000FFFFF; + } + } +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Compare MATLAB Reference Output and ARM Test output + * @param[in] pIn Pointer to Ref buffer + * @param[in] pOut Pointer to Test buffer + * @param[in] numSamples number of samples in the buffer + * @return maximum difference + */ + +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + int32_t diff, diffCrnt = 0; + uint32_t maxDiff = 0; + + for (i = 0; i < numSamples; i++) + { + diff = pIn[i] - pOut[i]; + diffCrnt = (diff > 0) ? diff : -diff; + + if (diffCrnt > maxDiff) + { + maxDiff = diffCrnt; + } + } + + return(maxDiff); +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q31 (q31_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + +/** + * @brief Provide guard bits for Input buffer + * @param[in,out] input_buf Pointer to input buffer + * @param[in] blockSize block Size + * @param[in] guard_bits guard bits + * @return none + * The function Provides the guard bits for the buffer + * to avoid overflow + */ + +void arm_provide_guard_bits_q7 (q7_t * input_buf, + uint32_t blockSize, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + input_buf[i] = input_buf[i] >> guard_bits; + } +} + + + +/** + * @brief Caluclates number of guard bits + * @param[in] num_adds number of additions + * @return guard bits + * The function Caluclates the number of guard bits + * depending on the numtaps + */ + +uint32_t arm_calc_guard_bits (uint32_t num_adds) +{ + uint32_t i = 1, j = 0; + + if (num_adds == 1) + { + return (0); + } + + while (i < num_adds) + { + i = i * 2; + j++; + } + + return (j); +} + +/** + * @brief Apply guard bits to buffer + * @param[in,out] pIn pointer to input buffer + * @param[in] numSamples number of samples in the input buffer + * @param[in] guard_bits guard bits + * @return none + */ + +void arm_apply_guard_bits (float32_t *pIn, + uint32_t numSamples, + uint32_t guard_bits) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + pIn[i] = pIn[i] * arm_calc_2pow(guard_bits); + } +} + +/** + * @brief Calculates pow(2, numShifts) + * @param[in] numShifts number of shifts + * @return pow(2, numShifts) + */ +uint32_t arm_calc_2pow(uint32_t numShifts) +{ + + uint32_t i, val = 1; + + for (i = 0; i < numShifts; i++) + { + val = val * 2; + } + + return(val); +} + + + +/** + * @brief Converts float to fixed q14 + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 16384.0f corresponds to pow(2, 14) */ + pOut[i] = (q15_t) (pIn[i] * 16384.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFF; + } + + } + +} + + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 1073741824.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 2.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/** + * @brief Converts float to fixed q30 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 1073741824.0f corresponds to pow(2, 30) */ + pOut[i] = (q31_t) (pIn[i] * 536870912.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 4.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + + +/** + * @brief Converts float to fixed q28 format + * @param[in] pIn pointer to input buffer + * @param[out] pOut pointer to output buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + /* 268435456.0f corresponds to pow(2, 28) */ + pOut[i] = (q31_t) (pIn[i] * 268435456.0f); + + pOut[i] += pIn[i] > 0 ? 0.5 : -0.5; + + if (pIn[i] == (float) 8.0) + { + pOut[i] = 0x7FFFFFFF; + } + } +} + +/* + +Conflicting with the new clip functions in CMSIS-DSP and not used +in the examples. + +*/ +#if 0 +/** + * @brief Clip the float values to +/- 1 + * @param[in,out] pIn input buffer + * @param[in] numSamples number of samples in the buffer + * @return none + * The function converts floating point values to fixed point values + */ + +void arm_clip_f32 (float *pIn, uint32_t numSamples) +{ + uint32_t i; + + for (i = 0; i < numSamples; i++) + { + if (pIn[i] > 1.0f) + { + pIn[i] = 1.0; + } + else if ( pIn[i] < -1.0f) + { + pIn[i] = -1.0; + } + + } +} + +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h new file mode 100644 index 0000000..a0dbdf7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* +* Title: math_helper.h +* +* Description: Prototypes of all helper functions required. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +#ifndef MATH_HELPER_H +#define MATH_HELPER_H + +float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize); +void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples); +void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits); +void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples); +void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples); +void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_guard_bits(uint32_t num_adds); +void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits); +uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples); +uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples); +uint32_t arm_calc_2pow(uint32_t guard_bits); +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt new file mode 100644 index 0000000..6b60d30 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_sin_cos_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt new file mode 100644 index 0000000..76c6649 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_sin_cos_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_sin_cos_example) + + +include(config) +configApp(arm_sin_cos_example ${ROOT}) + +target_sources(arm_sin_cos_example PRIVATE arm_sin_cos_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_sin_cos_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c new file mode 100644 index 0000000..41614fc --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_sin_cos_example_f32.c +* +* Description: Example code demonstrating sin and cos calculation of input signal. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SinCosExample SineCosine Example + * + * \par Description: + * \par + * Demonstrates the Pythagorean trignometric identity with the use of Cosine, Sine, Vector + * Multiplication, and Vector Addition functions. + * + * \par Algorithm: + * \par + * Mathematically, the Pythagorean trignometric identity is defined by the following equation: + * 
sin(x) * sin(x) + cos(x) * cos(x) = 1
+ * where \c x is the angle in radians. + * + * \par Block Diagram: + * \par + * \image html sinCos.gif + * + * \par Variables Description: + * \par + * \li \c testInput_f32 array of input angle in radians + * \li \c testOutput stores sum of the squares of sine and cosine values of input angle + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_cos_f32() + * - arm_sin_f32() + * - arm_mult_f32() + * - arm_add_f32() + * + * Refer + * \link arm_sin_cos_example_f32.c \endlink + * + */ + + +/** \example arm_sin_cos_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.0001f) + + +/* ---------------------------------------------------------------------- +* Test input data for Floating point sin_cos example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +const float32_t testInput_f32[MAX_BLOCKSIZE] = +{ + -1.244916875853235400, -4.793533929171324800, 0.360705030233248850, 0.827929644170887320, -3.299532218312426900, 3.427441903227623800, 3.422401784294607700, -0.108308165334010680, + 0.941943896490312180, 0.502609575000365850, -0.537345278736373500, 2.088817392965764500, -1.693168684143455700, 6.283185307179590700, -0.392545884746175080, 0.327893095115825040, + 3.070147440456292300, 0.170611405884662230, -0.275275082396073010, -2.395492805446796300, 0.847311163536506600, -3.845517018083148800, 2.055818378415868300, 4.672594161978930800, + -1.990923030266425800, 2.469305197656249500, 3.609002606064021000, -4.586736582331667500, -4.147080139136136300, 1.643756718868359500, -1.150866392366494800, 1.985805026477433800 + + +}; + +const float32_t testRefOutput_f32 = 1.000000000; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t testOutput; +float32_t cosOutput; +float32_t sinOutput; +float32_t cosSquareOutput; +float32_t sinSquareOutput; + +/* ---------------------------------------------------------------------- +* Max magnitude FFT Bin test +* ------------------------------------------------------------------- */ + +arm_status status; + +int32_t main(void) +{ + float32_t diff; + uint32_t i; + + for(i=0; i< blockSize; i++) + { + cosOutput = arm_cos_f32(testInput_f32[i]); + sinOutput = arm_sin_f32(testInput_f32[i]); + + arm_mult_f32(&cosOutput, &cosOutput, &cosSquareOutput, 1); + arm_mult_f32(&sinOutput, &sinOutput, &sinSquareOutput, 1); + + arm_add_f32(&cosSquareOutput, &sinSquareOutput, &testOutput, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(testRefOutput_f32 - testOutput); + + /* Comparison of sin_cos value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if ( status == ARM_MATH_TEST_FAILURE) + { + break; + } + } + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt new file mode 100644 index 0000000..cad7ae1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_svm_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt new file mode 100644 index 0000000..2fa5d18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_svm_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_svm_example) + + +include(config) +configApp(arm_svm_example ${ROOT}) + +target_sources(arm_svm_example PRIVATE arm_svm_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_svm_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c new file mode 100644 index 0000000..bcadcbc --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_svm_example/arm_svm_example_f32.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2019-2020 ARM Limited. All rights reserved. +* +* $Date: 09. December 2019 +* $Revision: V1.0.0 +* +* Project: CMSIS DSP Library +* Title: arm_svm_example_f32.c +* +* Description: Example code demonstrating how to use SVM functions. +* +* Target Processor: Cortex-M/Cortex-A +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup SVMExample SVM Example + * + * \par Description: + * \par + * Demonstrates the use of SVM functions. It is complementing the tutorial + * about classical ML with CMSIS-DSP and python scikit-learn: + * https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/implement-classical-ml-with-arm-cmsis-dsp-libraries + * + */ + + +/** \example arm_svm_example_f32.c + */ + +#include +#include +#include "arm_math.h" + +/* + The polynomial SVM instance containing all parameters. + Those parameters can be generated with the python library scikit-learn. + */ +arm_svm_polynomial_instance_f32 params; + +/* + Parameters generated by a training of the SVM classifier + using scikit-learn and some random input data. + */ +#define NB_SUPPORT_VECTORS 11 + +/* + Dimension of the vector space. A vector is your feature. + It could, for instance, be the pixels of a picture or the FFT of a signal. + */ +#define VECTOR_DIMENSION 2 + +const float32_t dualCoefficients[NB_SUPPORT_VECTORS]={-0.01628988f, -0.0971605f, + -0.02707579f, 0.0249406f, 0.00223095f, 0.04117345f, + 0.0262687f, 0.00800358f, 0.00581823f, 0.02346904f, 0.00862162f}; /* Dual coefficients */ + +const float32_t supportVectors[NB_SUPPORT_VECTORS*VECTOR_DIMENSION]={ 1.2510991f, 0.47782799f, + -0.32711859f, -1.49880648f, -0.08905047f, 1.31907242f, + 1.14059333f, 2.63443767f, -2.62561524f, 1.02120701f, + -1.2361353f, -2.53145187f, + 2.28308122f, -1.58185875f, 2.73955981f, 0.35759327f, + 0.56662986f, 2.79702016f, + -2.51380816f, 1.29295364f, -0.56658669f, -2.81944734f}; /* Support vectors */ + +/* + Class A is identified with value 0. + Class B is identified with value 1. + + This array is used by the SVM functions to do a conversion and ease the comparison + with the Python code where different values could be used. + */ +const int32_t classes[2]={0,1}; + + +int32_t main(void) +{ + /* Array of input data */ + float32_t in[VECTOR_DIMENSION]; + + /* Result of the classifier */ + int32_t result; + + + /* + Initialization of the SVM instance parameters. + Additional parameters (intercept, degree, coef0 and gamma) are also coming from Python. + */ + arm_svm_polynomial_init_f32(¶ms, + NB_SUPPORT_VECTORS, + VECTOR_DIMENSION, + -1.661719f, /* Intercept */ + dualCoefficients, + supportVectors, + classes, + 3, /* degree */ + 1.100000f, /* Coef0 */ + 0.500000f /* Gamma */ + ); + + + /* + Input data. + It is corresponding to a point inside the first class. + */ + in[0] = 0.4f; + in[1] = 0.1f; + + arm_svm_polynomial_predict_f32(¶ms, in, &result); + + /* Result should be 0 : First class */ +#if defined(SEMIHOSTING) + printf("Result = %d\n", result); +#endif + + /* + This input vector is corresponding to a point inside the second class. + */ + in[0] = 3.0f; + in[1] = 0.0f; + + arm_svm_polynomial_predict_f32(¶ms, in, &result); + + /* Result should be 1 : Second class */ +#if defined(SEMIHOSTING) + printf("Result = %d\n", result); +#endif + +#if !defined(SEMIHOSTING) + while (1); /* main function does not return */ +#endif +} + + + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt new file mode 100644 index 0000000..13dc783 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM0_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm0ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm0ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm0ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm0ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt new file mode 100644 index 0000000..55419ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM3_config.txt @@ -0,0 +1,8 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm3ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm3ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm3ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm3ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt new file mode 100644 index 0000000..fb9d24c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM4_FP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm4ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm4ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm4ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm4ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt new file mode 100644 index 0000000..4a65b1d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM55_FP_MVE_config.txt @@ -0,0 +1,25 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu0.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu0.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +# +cpu1.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu1.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +cpu1.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +cpu1.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +cpu1.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu1.MVE=2 # (int , init-time) default = '0x1' : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included +cpu1.SAU=0 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) +cpu1.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +cpu1.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +cpu1.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt new file mode 100644 index 0000000..82fc00c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/ARMCM7_SP_config.txt @@ -0,0 +1,9 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +armcortexm7ct.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +armcortexm7ct.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) +armcortexm7ct.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) +armcortexm7ct.min_sync_level=3 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) +armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +#------------------------------------------------------------------------------ diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 0000000..d4712e8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,10 @@ +CMSIS DSP_Lib example arm_variance_example. + +The example is available for different targets: + Cortex-M0 + Cortex-M3 + Cortex-M4 with FPU + Cortex-M7 with single precision FPU + Cortex-M55 with double precision FPU, Integer + Floating Point MVE + +The example is configured for Models Debugger diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt new file mode 100644 index 0000000..c7cdbd0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt @@ -0,0 +1,45 @@ +cmake_minimum_required (VERSION 3.14) +project (arm_variance_example VERSION 0.1) + + +# Needed to include the configBoot module +# Define the path to CMSIS-DSP (ROOT is defined on command line when using cmake) +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) +set(DSP ${ROOT}/CMSIS/DSP) + +# Add DSP folder to module path +list(APPEND CMAKE_MODULE_PATH ${DSP}) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_variance_example) + + +include(config) +configApp(arm_variance_example ${ROOT}) + +target_sources(arm_variance_example PRIVATE arm_variance_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_variance_example PRIVATE CMSISDSP) + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..f527fa1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,131 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66a364c --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..0392a89 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,135 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void) ; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Default_Handler(void); +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..3c5eda7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c new file mode 100644 index 0000000..90eee9d --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.c @@ -0,0 +1,141 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..9d983d2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,81 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0ab7e3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS Core Device Startup File for ARMCM55 Device + * @version V1.0.0 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..b76ebb7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.0.0 + * @date 23. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" + #endif + +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..7858499 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V2.0.2 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Default_Handler(void); +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +__NO_RETURN void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..75f9c18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 0000000..f40e018 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ + +#include +#include "arm_math.h" + +#if defined(SEMIHOSTING) +#include +#endif + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ + -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, + -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, + 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, + -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, + 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, + 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, + -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, + -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + +#if defined(SEMIHOSTING) + printf("START\n"); +#endif + + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + status = (diff > DELTA) ? ARM_MATH_TEST_FAILURE : ARM_MATH_SUCCESS; + + if (status != ARM_MATH_SUCCESS) + { +#if defined (SEMIHOSTING) + printf("FAILURE\n"); +#else + while (1); /* main function does not return */ +#endif + } + else + { +#if defined (SEMIHOSTING) + printf("SUCCESS\n"); +#else + while (1); /* main function does not return */ +#endif + } + +} + + /** \endlink */ + + diff --git a/Drivers/CMSIS/DSP/Include/arm_common_tables.h b/Drivers/CMSIS/DSP/Include/arm_common_tables.h new file mode 100644 index 0000000..3e72c80 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_common_tables.h @@ -0,0 +1,539 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math_types.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Q31 */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Fast vector sqrt */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + /* Accurate scalar sqrt */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) + extern const q31_t sqrt_initial_lut_q31[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) + extern const q15_t sqrt_initial_lut_q15[16]; + #endif + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h b/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h new file mode 100644 index 0000000..f9a63fe --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_common_tables_f16.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.h + * Description: Extern declaration for common tables + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_F16_H +#define _ARM_COMMON_TABLES_F16_H + +#include "arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + /* F16 */ + #if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + extern const float16_t twiddleCoefF16_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + extern const float16_t twiddleCoefF16_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + extern const float16_t twiddleCoefF16_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + extern const float16_t twiddleCoefF16_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + extern const float16_t twiddleCoefF16_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + extern const float16_t twiddleCoefF16_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + extern const float16_t twiddleCoefF16_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + extern const float16_t twiddleCoefF16_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + extern const float16_t twiddleCoefF16_4096[8192]; + #define twiddleCoefF16 twiddleCoefF16_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) + extern const float16_t twiddleCoefF16_rfft_32[32]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) + extern const float16_t twiddleCoefF16_rfft_64[64]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) + extern const float16_t twiddleCoefF16_rfft_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) + extern const float16_t twiddleCoefF16_rfft_256[256]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) + extern const float16_t twiddleCoefF16_rfft_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) + extern const float16_t twiddleCoefF16_rfft_1024[1024]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) + extern const float16_t twiddleCoefF16_rfft_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) + extern const float16_t twiddleCoefF16_rfft_4096[4096]; + #endif + + #endif /* ARMAC5 */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float16_t exp_tab_f16[8]; + extern const float16_t __logf_lut_f16[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_COMMON_TABLES_F16_H */ + + diff --git a/Drivers/CMSIS/DSP/Include/arm_const_structs.h b/Drivers/CMSIS/DSP/Include/arm_const_structs.h new file mode 100644 index 0000000..59026db --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_const_structs.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math_types.h" +#include "arm_common_tables.h" +#include "dsp/transform_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h b/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h new file mode 100644 index 0000000..0984d74 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_const_structs_f16.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f16() function. + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_F16_H +#define _ARM_CONST_STRUCTS_F16_H + +#include "arm_math_types_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" +#include "dsp/transform_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048; + #endif + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096; + #endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/Include/arm_helium_utils.h b/Drivers/CMSIS/DSP/Include/arm_helium_utils.h new file mode 100644 index 0000000..ae9037c --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_helium_utils.h @@ -0,0 +1,753 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + + +#ifdef __cplusplus +extern "C" +{ +#endif +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + + + + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df +#define INV_NEWTON_INIT_F32 0x7EF127EA + + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + + +/*************************************** + +Definitions available for f16 datatype with HW acceleration only + +***************************************/ +#if defined(ARM_FLOAT16_SUPPORTED) +#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in) +{ + float16x8_t tmpVec; + _Float16 acc; + + tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in); + in = vaddq_f16(tmpVec, in); + tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in); + in = vaddq_f16(tmpVec, in); + acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4); + + return acc; +} + +__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn) +{ + float16x8_t vecTmp, vecOut; + uint32_t tmp; + + vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn); + // TO TRACK : using canonical addition leads to unefficient code generation for f16 + // vecTmp = vecTmp + vecAccCpx0; + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + vecTmp = vaddq_f16(vecTmp, vecIn); + vecOut = vecTmp; + /* + * shift left, random tmp insertion in bottom + */ + vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32)); + /* + * Compute: + * DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1 + * re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3 + */ + vecOut = vaddq_f16(vecOut, vecTmp); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * return full vector + */ + return vecOut; +} + + +#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \ +{ \ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \ + Re = vgetq_lane(vecOut, 4); \ + Im = vgetq_lane(vecOut, 5); \ +} + +__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16( + float16x8_t vecIn, + float16_t *pOut) +{ + float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn); + /* + * Cmplx sum is in 4rd & 5th f16 elt + * use 32-bit extraction + */ + *(float32_t *) pOut = ((float32x4_t) vecOut)[2]; +} + + +#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */ + +/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */ +#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \ +{ \ + float16x8_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} + +#endif +#endif + +/*************************************** + +Definitions available for MVEI and MVEF only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit( + uint16_t srcRows, + uint16_t srcCols, + uint32_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint32_t *pDataDest) +{ + uint32_t i; + uint32_t const *pDataC; + uint32_t *pDataRow; + uint32_t *pDataDestR, *pDataDestRow; + uint32x4_t vecOffsRef, vecOffsCur; + uint32_t blkCnt; + uint32x4_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* 2x2, 3x3 and 4x4 specialization to be added */ + + vecOffsRef[0] = 0; + vecOffsRef[1] = 1; + vecOffsRef[2] = srcCols << 1; + vecOffsRef[3] = (srcCols << 1) + 1; + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + vecOffsCur = vaddq(vecOffsCur, (srcCols << 2)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + pDataDest[0] = pDataSrc[0]; + pDataDest[3] = pDataSrc[3]; + pDataDest[2] = pDataSrc[1]; + pDataDest[1] = pDataSrc[2]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 }; + uint16x8_t vecOffs1; + uint16x8_t vecIn1; + /* + * + * | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 | + * | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . | + * | 6 7 8 | | 2 5 8 | (row major) + * + */ + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33); + vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest) +{ + static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 }; + static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 }; + uint16x8_t vecOffs1, vecOffs2; + uint16x8_t vecIn1, vecIn2; + uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc; + + /* + * 4x4 Matrix transposition + * + * | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version + * | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13] + * | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15] + * | 12 13 14 15 | | 3 7 11 15 | + */ + + vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1); + vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2); + vecIn1 = vldrhq_u16(pDataSrcVec); + pDataSrcVec += 8; + vecIn2 = vldrhq_u16(pDataSrcVec); + + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1); + vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2); + + + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_trans_16bit_generic( + uint16_t srcRows, + uint16_t srcCols, + uint16_t * pDataSrc, + uint16_t * pDataDest) +{ + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint16_t const *pDataC; + uint16_t *pDataDestR; + uint16x8_t vecIn; + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + while(i > 0U) + { + pDataC = (uint16_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + srcCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs); + vstrhq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDest += srcRows; + i--; + } + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit( + uint16_t srcRows, + uint16_t srcCols, + uint16_t *pDataSrc, + uint16_t dstRows, + uint16_t dstCols, + uint16_t *pDataDest) +{ + static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 }; + int i; + uint16x8_t vecOffsRef, vecOffsCur; + uint16_t const *pDataC; + uint16_t *pDataRow; + uint16_t *pDataDestR, *pDataDestRow; + uint32_t blkCnt; + uint16x8_t vecIn; + +#ifdef ARM_MATH_MATRIX_CHECK + /* + * Check for matrix mismatch condition + */ + if ((srcRows != dstCols) || (srcCols != dstRows)) + { + /* + * Set status as ARM_MATH_SIZE_MISMATCH + */ + return ARM_MATH_SIZE_MISMATCH; + } +#else + (void)dstRows; + (void)dstCols; +#endif + + /* + * 2x2, 3x3 and 4x4 specialization to be added + */ + + + /* + * build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1] + */ + vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol); + vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM)) + + viwdupq_u16((uint32_t)0, (uint16_t) 2, 1); + + pDataRow = pDataSrc; + pDataDestRow = pDataDest; + i = srcCols; + do + { + pDataC = (uint16_t const *) pDataRow; + pDataDestR = pDataDestRow; + vecOffsCur = vecOffsRef; + + blkCnt = (srcRows * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq(pDataDestR, vecIn); + pDataDestR+= 8; // VEC_LANES_U16 + vecOffsCur = vaddq(vecOffsCur, (srcCols << 3)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (srcRows * CMPLX_DIM) & 0x7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur); + vstrhq_p(pDataDestR, vecIn, p0); + } + + pDataRow += CMPLX_DIM; + pDataDestRow += (srcRows * CMPLX_DIM); + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#endif /* MVEF and MVEI */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) +#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s32(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq_n_s16(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/Include/arm_math.h b/Drivers/CMSIS/DSP/Include/arm_math.h new file mode 100644 index 0000000..300c5cf --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math.h @@ -0,0 +1,236 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * \section intro Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * - Quaternion functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * The library is providing vectorized versions of most algorthms for Helium + * and of most f32 algorithms for Neon. + * + * When using a vectorized version, provide a little bit of padding after the end of + * a buffer (3 words) because the vectorized code may read a little bit after the end + * of a buffer. You don't have to modify your buffers but just ensure that the + * end of buffer + padding is not outside of a memory region. + * + * \section using Using the Library + * + * The library is released in source form. It is strongly advised to compile the library using -Ofast to + * have the best performances. + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file. If you don't want to include everything, you can also rely + * on headers in Include/dsp folder and use only what you need. + * + * \section example Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * \section toolchain Toolchain Support + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M4, M7, M33, M55, A32 are tested. + * + * + * \section preprocessor Preprocessor Macros + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16. + * + * - ARM_MATH_HELIUM_EXPERIMENTAL: + * + * Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined. + * Enable some vector versions which may have worse performance than scalar + * depending on the core / compiler configuration. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_MVE_FLOAT16: + * + * MVE Float16 implementations of some algorithms (Requires MVE extension). + * + * - DISABLEFLOAT16: + * + * Disable float16 algorithms when __fp16 is not supported for a + * specific compiler / core configuration. + * This is only valid for scalar. When vector architecture is + * supporting f16 then it can't be disabled. + * + * - ARM_MATH_AUTOVECTORIZE: + * + * With Helium or Neon, disable the use of vectorized code with C intrinsics + * and use pure C instead. The vectorization is then done by the compiler. + * + *
+ * \section pack CMSIS-DSP in ARM::CMSIS Pack + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files for using and building the lib + * |\b CMSIS\\DSP\\PrivateInclude | DSP_Lib private include files for building the lib | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * \section rev Revision History of CMSIS-DSP + * Please refer to \ref ChangeLog_pg. + */ + + + + + + + + + + + +/** + * @defgroup groupExamples Examples + */ + + + + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/interpolation_functions.h" +#include "dsp/bayes_functions.h" +#include "dsp/matrix_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/controller_functions.h" +#include "dsp/support_functions.h" +#include "dsp/distance_functions.h" +#include "dsp/svm_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/transform_functions.h" +#include "dsp/filtering_functions.h" +#include "dsp/quaternion_math_functions.h" + + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +//#define TABLE_SPACING_Q31 0x400000 +//#define TABLE_SPACING_Q15 0x80 + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/Drivers/CMSIS/DSP/Include/arm_math_f16.h b/Drivers/CMSIS/DSP/Include/arm_math_f16.h new file mode 100644 index 0000000..daf0c53 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math_f16.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * @file arm_math_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_F16_H +#define _ARM_MATH_F16_H + +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "arm_math_types_f16.h" +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/basic_math_functions_f16.h" +#include "dsp/interpolation_functions_f16.h" +#include "dsp/bayes_functions_f16.h" +#include "dsp/matrix_functions_f16.h" +#include "dsp/complex_math_functions_f16.h" +#include "dsp/statistics_functions_f16.h" +#include "dsp/controller_functions_f16.h" +#include "dsp/support_functions_f16.h" +#include "dsp/distance_functions_f16.h" +#include "dsp/svm_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" +#include "dsp/transform_functions_f16.h" +#include "dsp/filtering_functions_f16.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ + + diff --git a/Drivers/CMSIS/DSP/Include/arm_math_memory.h b/Drivers/CMSIS/DSP/Include/arm_math_memory.h new file mode 100644 index 0000000..7bd83dc --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math_memory.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file arm_math_memory.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_MEMORY_H_ + +#define _ARM_MATH_MEMORY_H_ + +#include "arm_math_types.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t const * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2) + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2) + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (q15_t)(val & 0x0FFFF); + (*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF); +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = (q15_t)(val & 0x0FFFF); + pQ15[1] = (q15_t)(val >> 16); +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4 ( + q7_t const * pQ7) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ7, 4); +#else + val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF); +#endif + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4) + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4) + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = (q7_t)(val & 0x0FF); + (*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF); + (*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF); + (*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF); + +#endif + *pQ7 += 4; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_MEMORY_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/arm_math_types.h b/Drivers/CMSIS/DSP/Include/arm_math_types.h new file mode 100644 index 0000000..c615e66 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math_types.h @@ -0,0 +1,616 @@ +/****************************************************************************** + * @file arm_math_types.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_H_ + +#define _ARM_MATH_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + #pragma GCC diagnostic ignored "-Wold-style-cast" + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) +#elif defined ( __APPLE_CC__ ) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#define __STATIC_INLINE static inline + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) + #if defined(_MSC_VER) && defined(_M_ARM64EC) + #include + #else + #include + #endif + #if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC + #if !defined(ARM_MATH_NEON_FLOAT16) + #define ARM_MATH_NEON_FLOAT16 + #endif + #endif +#endif + +#if !defined(ARM_MATH_AUTOVECTORIZE) + + +#if defined(__ARM_FEATURE_MVE) +#if __ARM_FEATURE_MVE + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif +#endif + +#if (__ARM_FEATURE_MVE & 2) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + +#endif /*defined(__ARM_FEATURE_MVE)*/ +#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined (ARM_MATH_HELIUM) + #if !defined(ARM_MATH_MVEF) + #define ARM_MATH_MVEF + #endif + + #if !defined(ARM_MATH_MVEI) + #define ARM_MATH_MVEI + #endif + + #if !defined(ARM_MATH_MVE_FLOAT16) + #define ARM_MATH_MVE_FLOAT16 + #endif +#endif + + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __APPLE_CC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __APPLE_CC__ ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ +#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2) + typedef float float32_t; +#endif + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + + + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + + + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + + + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */ + ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */ + } arm_status; + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_TYPES_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h b/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h new file mode 100644 index 0000000..744dc38 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_math_types_f16.h @@ -0,0 +1,163 @@ +/****************************************************************************** + * @file arm_math_types_f16.h + * @brief Public header file for f16 function of the CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_TYPES_F16_H +#define _ARM_MATH_TYPES_F16_H + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined( __CC_ARM ) + +/** + * @brief 16-bit floating-point type definition. + * This is already defined in arm_mve.h + * + * This is not fully supported on ARM AC5. + */ + +/* + +Check if the type __fp16 is available. +If it is not available, f16 version of the kernels +won't be built. + +*/ +#if !(__ARM_FEATURE_MVE & 2) + #if !defined(DISABLEFLOAT16) + #if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE) + typedef __fp16 float16_t; + #define ARM_FLOAT16_SUPPORTED + #endif + #endif +#else + /* When Vector float16, this flag is always defined and can't be disabled */ + #define ARM_FLOAT16_SUPPORTED +#endif + +#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/ + +#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16) + + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; + + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; + + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + + +#if defined(ARM_MATH_NEON_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; + + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; + + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if defined(__ICCARM__) + +#define F16INFINITY ((float16_t) INFINITY) + +#else + +#define F16INFINITY ((float16_t)__builtin_inf()) + +#endif + +#define F16_MAX ((float16_t)__FLT16_MAX__) +#define F16_MIN (-(_Float16)__FLT16_MAX__) + +#define F16_ABSMAX ((float16_t)__FLT16_MAX__) +#define F16_ABSMIN ((float16_t)0.0f16) + +#endif /* ARM_FLOAT16_SUPPORTED*/ +#endif /* !defined( __CC_ARM ) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_F16_H */ diff --git a/Drivers/CMSIS/DSP/Include/arm_mve_tables.h b/Drivers/CMSIS/DSP/Include/arm_mve_tables.h new file mode 100644 index 0000000..c4f8bf0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_mve_tables.h @@ -0,0 +1,231 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h b/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h new file mode 100644 index 0000000..dc95203 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_mve_tables_f16.h @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_F16_H + #define _ARM_MVE_TABLES_F16_H + +#include "arm_math_types_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]; +extern float16_t rearranged_twiddle_stride1_16_f16[8]; +extern float16_t rearranged_twiddle_stride2_16_f16[8]; +extern float16_t rearranged_twiddle_stride3_16_f16[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]; +extern float16_t rearranged_twiddle_stride1_64_f16[40]; +extern float16_t rearranged_twiddle_stride2_64_f16[40]; +extern float16_t rearranged_twiddle_stride3_64_f16[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]; +extern float16_t rearranged_twiddle_stride1_256_f16[168]; +extern float16_t rearranged_twiddle_stride2_256_f16[168]; +extern float16_t rearranged_twiddle_stride3_256_f16[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]; +extern float16_t rearranged_twiddle_stride1_1024_f16[680]; +extern float16_t rearranged_twiddle_stride2_1024_f16[680]; +extern float16_t rearranged_twiddle_stride3_1024_f16[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]; +extern float16_t rearranged_twiddle_stride1_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride2_4096_f16[2728]; +extern float16_t rearranged_twiddle_stride3_4096_f16[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#ifdef __cplusplus +} +#endif + +#endif /*_ARM_MVE_TABLES_F16_H*/ + diff --git a/Drivers/CMSIS/DSP/Include/arm_vec_math.h b/Drivers/CMSIS/DSP/Include/arm_vec_math.h new file mode 100644 index 0000000..d9134c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_vec_math.h @@ -0,0 +1,373 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math_types.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h b/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h new file mode 100644 index 0000000..91bd28a --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/arm_vec_math_f16.h @@ -0,0 +1,312 @@ +/****************************************************************************** + * @file arm_vec_math_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_F16_H +#define _ARM_VEC_MATH_F16_H + +#include "arm_math_types_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + +static const float16_t __logf_rng_f16=0.693147180f16; + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f16x8_t vrecip_medprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f16x8_t vrecip_hiprec_f16( + f16x8_t x) +{ + q15x8_t m; + f16x8_t b; + any16x8_t xinv; + f16x8_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x03c00 - (xinv.i & 0x07c00); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f16 - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f16x8_t vdiv_f16( + f16x8_t num, f16x8_t den) +{ + return vmulq(num, vrecip_hiprec_f16(den)); +} + + +/** + @brief Single-precision taylor dev. + @param[in] x f16 vector input + @param[in] coeffs f16 vector coeffs + @return destination f16 vector + */ + +__STATIC_INLINE float16x8_t vtaylor_polyq_f16( + float16x8_t x, + const float16_t * coeffs) +{ + float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]); + float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]); + float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]); + float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]); + float16x8_t x2 = vmulq(x, x); + float16x8_t x4 = vmulq(x2, x2); + float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4); + + return res; +} + +#define VMANT_EXP_F16(x) \ + any16x8_t r; \ + int16x8_t n; \ + \ + r.f = x; \ + n = r.i >> 10; \ + n = n - 15; \ + r.i = r.i - (n << 10);\ + \ + vecExpUnBiased = n; \ + vecTmpFlt1 = r.f; + +__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) +{ + q15x8_t vecExpUnBiased; + float16x8_t vecTmpFlt0, vecTmpFlt1; + float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + float16x8_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + VMANT_EXP_F16(vecIn); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]); + */ + vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]); + /* + * b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]); + */ + vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]); + /* + * c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]); + */ + vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]); + /* + * d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]); + */ + vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f16; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16); + // set log0 down to -inf + vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE float16x8_t vexpq_f16( + float16x8_t x) +{ + // Perform range reduction [-log(2),log(2)] + int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16)); + float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16)); + + // Polynomial Approximation + float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16); + + // Reconstruct + poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10))); + + poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14)); + return poly; +} + +__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) +{ + float16x8_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f16x8_t vpowq_f16( + f16x8_t val, + f16x8_t n) +{ + return vexpq_f16(vmulq_f16(n, vlogq_f16(val))); +} + +#define INV_NEWTON_INIT_F16 0x7773 + +__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) +{ + f16x8_t vecSx, vecW, vecTmp; + any16x8_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16); + vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f16x8_t vtanhq_f16( + f16x8_t val) +{ + f16x8_t x = + vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16)); + f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16)); + f16x8_t num = vsubq_n_f16(exp2x, 1.f16); + f16x8_t den = vaddq_n_f16(exp2x, 1.f16); + f16x8_t tanh = vmulq_f16(num, vrecip_f16(den)); + return tanh; +} + +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ARM FLOAT16 SUPPORTED */ + +#endif /* _ARM_VEC_MATH_F16_H */ + +/** + * + * End of file. + */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h b/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h new file mode 100644 index 0000000..dcc1f2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions.h @@ -0,0 +1,880 @@ +/****************************************************************************** + * @file basic_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_H_ +#define _BASIC_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMath Basic Math Functions + */ + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ +void arm_mult_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f64( + const float64_t * pSrc, + float64_t scale, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ +void arm_abs_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + +/** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ +void arm_dot_prod_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result); + + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_offset_f64( +const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ +void arm_negate_f64( +const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples); + + /** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h new file mode 100644 index 0000000..de9f58b --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/basic_math_functions_f16.h @@ -0,0 +1,168 @@ +/****************************************************************************** + * @file basic_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BASIC_MATH_FUNCTIONS_F16_H_ +#define _BASIC_MATH_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result); + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples); + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h b/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h new file mode 100644 index 0000000..824c50e --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/bayes_functions.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * @file bayes_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_H_ +#define _BAYES_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h new file mode 100644 index 0000000..5c4ae42 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/bayes_functions_f16.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * @file bayes_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _BAYES_FUNCTIONS_F16_H_ +#define _BAYES_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float16_t *theta; /**< Mean values for the Gaussians */ + const float16_t *sigma; /**< Variances for the Gaussians */ + const float16_t *classPriors; /**< Class prior probabilities */ + float16_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f16; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h b/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h new file mode 100644 index 0000000..1339eba --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions.h @@ -0,0 +1,345 @@ +/****************************************************************************** + * @file complex_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_H_ +#define _COMPLEX_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + +/** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ +void arm_cmplx_mult_cmplx_f64( +const float64_t * pSrcA, +const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h new file mode 100644 index 0000000..b17f931 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/complex_math_functions_f16.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * @file complex_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ +#define _COMPLEX_MATH_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h b/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h new file mode 100644 index 0000000..7c08c24 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/controller_functions.h @@ -0,0 +1,791 @@ +/****************************************************************************** + * @file controller_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_H_ +#define _CONTROLLER_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + +#define CONTROLLER_Q31_SHIFT (32 - 9) + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @defgroup groupController Controller Functions + */ + + + /** + * @ingroup groupController + */ + + /** + * @addtogroup SinCos + * @{ + */ + +/** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + /** + * @} end of SinCos group + */ + + /** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */ + q15_t A2; /**< The derived gain A1 = Kd. */ +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + +/** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h new file mode 100644 index 0000000..8fae483 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/controller_functions_f16.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * @file controller_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _CONTROLLER_FUNCTIONS_F16_H_ +#define _CONTROLLER_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h b/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h new file mode 100644 index 0000000..3123fc3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/distance_functions.h @@ -0,0 +1,341 @@ +/****************************************************************************** + * @file distance_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_H_ +#define _DISTANCE_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b); + +#endif + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h new file mode 100644 index 0000000..a7ceb3c --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/distance_functions_f16.h @@ -0,0 +1,180 @@ +/****************************************************************************** + * @file distance_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _DISTANCE_FUNCTIONS_F16_H_ +#define _DISTANCE_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) +/* Defined in minkowski_f32 */ +__attribute__((weak)) float __powisf2(float a, int b); +#endif + +#include "dsp/statistics_functions_f16.h" +#include "dsp/basic_math_functions_f16.h" + +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize); + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h b/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h new file mode 100644 index 0000000..489f214 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions.h @@ -0,0 +1,389 @@ +/****************************************************************************** + * @file fast_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_H_ +#define _FAST_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) + +#ifndef PI + #define PI 3.14159265358979f +#endif + + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + + /** + * @ingroup groupFastMath + */ + + +/** + @addtogroup sin + @{ + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + +/** + @} end of sin group + */ + +/** + @addtogroup cos + @{ + */ + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + +/** + @} end of cos group + */ + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief q31 vector of log values. + * @param[in] pSrc points to the input vector in q31 + * @param[out] pDst points to the output vector in q5.26 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q31(const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief q15 vector of log values. + * @param[in] pSrc points to the input vector in q15 + * @param[out] pDst points to the output vector in q4.11 + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_vlog_q15(const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + const float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + + + /** + * @} end of SQRT group + */ + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift); + + /** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift); + + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result); + + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + */ + arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + */ + arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h new file mode 100644 index 0000000..46ae06d --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/fast_math_functions_f16.h @@ -0,0 +1,125 @@ +/****************************************************************************** + * @file fast_math_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FAST_MATH_FUNCTIONS_F16_H_ +#define _FAST_MATH_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +/* For sqrt_f32 */ +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f16( + float16_t in, + float16_t * pOut) + { + float32_t r; + arm_status status; + status=arm_sqrt_f32((float32_t)in,&r); + *pOut=(float16_t)r; + return(status); + } + + +/** + @} end of SQRT group + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Floating-point vector of inverse values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant. + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + */ + arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h b/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h new file mode 100644 index 0000000..28a9568 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/filtering_functions.h @@ -0,0 +1,2529 @@ +/****************************************************************************** + * @file filtering_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_H_ +#define _FILTERING_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/support_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) + +/** + * @defgroup groupFilters Filtering Functions + */ + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f64; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * + * For the MVE version, the coefficient length must be a multiple of 16. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + * + * For the MVE version, the coefficient length must be a multiple of 8. + * You can pad with zeros if you have less coefficients. + * + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * + * For the MVE version, the coefficient length must be a multiple of 4. + * You can pad with zeros if you have less coefficients. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized version. + @return none +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + + + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h new file mode 100644 index 0000000..fd8b0bb --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/filtering_functions_f16.h @@ -0,0 +1,237 @@ +/****************************************************************************** + * @file filtering_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _FILTERING_FUNCTIONS_F16_H_ +#define _FILTERING_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f16; + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f16; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f16; +#endif + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f16; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f16; + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst); + + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h b/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h new file mode 100644 index 0000000..6e51f7c --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions.h @@ -0,0 +1,319 @@ +/****************************************************************************** + * @file interpolation_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_H_ +#define _INTERPOLATION_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + + + + /** + * @ingroup groupInterpolation + */ + + /** + * @addtogroup SplineInterpolate + * @{ + */ + + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + + /** + * @} end of SplineInterpolate group + */ + + + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x); + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ +q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues); + + /** + * @} end of LinearInterpolate group + */ + + + + + /** + * @ingroup groupInterpolation + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y); + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y); + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y); + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y); + /** + * @} end of BilinearInterpolate group + */ + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h new file mode 100644 index 0000000..8b6e6a9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/interpolation_functions_f16.h @@ -0,0 +1,107 @@ +/****************************************************************************** + * @file interpolation_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _INTERPOLATION_FUNCTIONS_F16_H_ +#define _INTERPOLATION_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +typedef struct +{ + uint32_t nValues; /**< nValues */ + float16_t x1; /**< x1 */ + float16_t xSpacing; /**< xSpacing */ + float16_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f16; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ +typedef struct +{ + uint16_t numRows;/**< number of rows in the data table. */ + uint16_t numCols;/**< number of columns in the data table. */ + float16_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f16; + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x); + + /** + * @} end of LinearInterpolate group + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y); + + + /** + * @} end of BilinearInterpolate group + */ +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h b/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h new file mode 100644 index 0000000..f3801a9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/matrix_functions.h @@ -0,0 +1,757 @@ +/****************************************************************************** + * @file matrix_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_H_ +#define _MATRIX_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q7 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q7_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q7; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q15 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q7 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q7( + const arm_matrix_instance_q7 * pSrc, + arm_matrix_instance_q7 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pVec, + float32_t *pDst); + + /** + * @brief Q7 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState); + + /** + * @brief Q7 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 *pSrcMat, + const q7_t *pVec, + q7_t *pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 *pSrcMat, + const q15_t *pVec, + q15_t *pDst); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState); + + /** + * @brief Q31 matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 *pSrcMat, + const q31_t *pVec, + q31_t *pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst); + + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * l, + arm_matrix_instance_f32 * d, + uint16_t * pp); + + /** + * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] l points to the instance of the output floating-point triangular matrix structure. + * @param[out] d points to the instance of the output floating-point diagonal matrix structure. + * @param[out] p points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * l, + arm_matrix_instance_f64 * d, + uint16_t * pp); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h new file mode 100644 index 0000000..3693ec4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/matrix_functions_f16.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * @file matrix_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _MATRIX_FUNCTIONS_F16_H_ +#define _MATRIX_FUNCTIONS_F16_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float16_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f16; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point complex matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + /** + * @brief Floating-point matrix and vector multiplication + * @param[in] pSrcMat points to the input matrix structure + * @param[in] pVec points to vector + * @param[out] pDst points to output vector + */ +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pVec, + float16_t *pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + + /** + * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition is returning a lower triangular matrix. + */ + arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * src, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/none.h b/Drivers/CMSIS/DSP/Include/dsp/none.h new file mode 100644 index 0000000..130386e --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/none.h @@ -0,0 +1,576 @@ +/****************************************************************************** + * @file none.h + * @brief Intrinsincs when no DSP extension available + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + +Definitions in this file are allowing to reuse some versions of the +CMSIS-DSP to build on a core (M0 for instance) or a host where +DSP extension are not available. + +Ideally a pure C version should have been used instead. +But those are not always available or use a restricted set +of intrinsics. + +*/ + +#ifndef _NONE_H_ +#define _NONE_H_ + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } + + /** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +#endif + +/** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h b/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h new file mode 100644 index 0000000..0c5d067 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/quaternion_math_functions.h @@ -0,0 +1,159 @@ +/****************************************************************************** + * @file quaternion_math_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _QUATERNION_MATH_FUNCTIONS_H_ +#define _QUATERNION_MATH_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupQuaternionMath Quaternion Math Functions + * Functions to operates on quaternions and convert between a + * rotation and quaternion representation. + */ + + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions); + + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions); + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ +void arm_quaternion_normalize_f32(const float32_t *inputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions); + + +/** + @brief Floating-point product of two quaternions. + @param[in] qa First quaternion + @param[in] qb Second quaternion + @param[out] r Product of two quaternions + @return none + */ +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r); + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa First array of quaternions + @param[in] qb Second array of quaternions + @param[out] r Elementwise product of quaternions + @param[in] nbQuaternions Number of quaternions in the array + @return none + */ +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *r, + uint32_t nbQuaternions); + +/** + * @brief Conversion of quaternion to equivalent rotation matrix. + * @param[in] pInputQuaternions points to an array of normalized quaternions + * @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + * @param[in] nbQuaternions in the array + * @return none. + * + * Format of rotation matrix + * \par + * The quaternion a + ib + jc + kd is converted into rotation matrix: + * a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac + * 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab + * 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2 + * + * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions); + +/** + * @brief Conversion of a rotation matrix to equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array of quaternions + * @param[in] nbQuaternions in the array + * @return none. +*/ +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h b/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h new file mode 100644 index 0000000..c5224c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/statistics_functions.h @@ -0,0 +1,977 @@ +/****************************************************************************** + * @file statistics_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_H_ +#define _STATISTICS_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/fast_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of absolute values of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + */ + void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + + /** + @brief Maximum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Maximum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Maximum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + + /** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult); + +/** + @brief Minimum value of a q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q31( + const q31_t *pSrc, + uint32_t blockSize, + q31_t *pResult); + + /** + @brief Minimum value of a q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q15( + const q15_t *pSrc, + uint32_t blockSize, + q15_t *pResult); + + /** + @brief Minimum value of a q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult); + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult); + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult); + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult); + +/** + @brief Mean square error between two single precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * pResult); + +/** + @brief Mean square error between two double precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * pResult); + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h new file mode 100644 index 0000000..124c0a0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/statistics_functions_f16.h @@ -0,0 +1,266 @@ +/****************************************************************************** + * @file statistics_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _STATISTICS_FUNCTIONS_F16_H_ +#define _STATISTICS_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of absolute values of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of absolute values of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + */ + void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + */ + void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize); + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer); + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA + ,const float16_t * pSrcB + ,uint32_t blockSize); + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult); + +/** + @brief Mean square error between two half precision float vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none +*/ + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * pResult); + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/support_functions.h b/Drivers/CMSIS/DSP/Include/dsp/support_functions.h new file mode 100644 index 0000000..9c77593 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/support_functions.h @@ -0,0 +1,453 @@ +/****************************************************************************** + * @file support_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_H_ +#define _SUPPORT_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup groupSupport Support Functions + */ + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + + + + + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h new file mode 100644 index 0000000..bc3f266 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/support_functions_f16.h @@ -0,0 +1,187 @@ +/****************************************************************************** + * @file support_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SUPPORT_FUNCTIONS_F16_H_ +#define _SUPPORT_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize); + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ +void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the q15 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize); + + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f32 input vector + * @param[out] pDst points to the f16 output vector + * @param[in] blockSize length of the input vector + */ +void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the f16 input vector + * @param[out] pDst points to the f32 output vector + * @param[in] blockSize length of the input vector + */ +void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize); + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float16_t arm_weighted_sum_f16(const float16_t *in + , const float16_t *weigths + , uint32_t blockSize); + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f16(const float16_t *in + , const float16_t *weights + , float16_t *out + , uint32_t nbVectors + , uint32_t vecDim); + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup typecast Typecasting + */ + +/** + @addtogroup typecast + @{ + */ + +/** + * @brief Interpret a f16 as an s16 value + * @param[in] x input value. + * @return return value. + * + * @par Description + * It is a typecast. No conversion of the float to int is done. + * The memcpy will be optimized out by the compiler. + * memcpy is used to prevent type punning issues. + * With gcc, -fno-builtins MUST not be used or the + * memcpy will not be optimized out. + */ +__STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x) +{ + int16_t res; + res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t)); + return(res); +} + +/** + * @brief Interpret an s16 as an f16 value + * @param[in] x input value. + * @return return value. + * + * @par Description + * It is a typecast. No conversion of the int to float is done. + * The memcpy will be optimized out by the compiler. + * memcpy is used to prevent type punning issues. + * With gcc, -fno-builtins MUST not be used or the + * memcpy will not be optimized out. + */ +__STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x) +{ + float16_t res; + res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t)); + return(res); +} + + +/** + @} end of typecast group + */ + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h b/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h new file mode 100644 index 0000000..f93e953 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/svm_defines.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * @file svm_defines.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_DEFINES_H_ +#define _SVM_DEFINES_H_ + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + +#endif diff --git a/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h b/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h new file mode 100644 index 0000000..3acc621 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/svm_functions.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * @file svm_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_H_ +#define _SVM_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + + + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independent constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h new file mode 100644 index 0000000..7c9fbab --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/svm_functions_f16.h @@ -0,0 +1,281 @@ +/****************************************************************************** + * @file svm_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _SVM_FUNCTIONS_F16_H_ +#define _SVM_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" +#include "dsp/svm_defines.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(ARM_FLOAT16_SUPPORTED) + +#define STEP(x) (x) <= 0 ? 0 : 1 + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f16; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float16_t coef0; /**< Polynomial constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f16; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f16; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float16_t intercept; /**< Intercept */ + const float16_t *dualCoefficients; /**< Dual coefficients */ + const float16_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float16_t coef0; /**< Independent constant */ + float16_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f16; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult); + + + +#endif /*defined(ARM_FLOAT16_SUPPORTED)*/ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h b/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h new file mode 100644 index 0000000..6270e10 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/transform_functions.h @@ -0,0 +1,735 @@ +/****************************************************************************** + * @file transform_functions.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_H_ +#define _TRANSFORM_FUNCTIONS_H_ + +#include "arm_math_types.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @defgroup groupTransforms Transform Functions + */ + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + + + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen); + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Instance structure for the Floating-point MFCC function. + */ +typedef struct + { + const float32_t *dctCoefs; /**< Internal DCT coefficients */ + const float32_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float32_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f32 rfft; +#endif + } arm_mfcc_instance_f32 ; + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ); + + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ); + +typedef struct + { + const q31_t *dctCoefs; /**< Internal DCT coefficients */ + const q31_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q31_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q31 rfft; +#endif + } arm_mfcc_instance_q31 ; + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ); + + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ); + +typedef struct + { + const q15_t *dctCoefs; /**< Internal DCT coefficients */ + const q15_t *filterCoefs; /**< Internal Mel filter coefficients */ + const q15_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_instance_q15 rfft; +#endif + } arm_mfcc_instance_q15 ; + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ); + + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + @return error status + */ + arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ); + + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h b/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h new file mode 100644 index 0000000..4d8cc22 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/transform_functions_f16.h @@ -0,0 +1,208 @@ +/****************************************************************************** + * @file transform_functions_f16.h + * @brief Public header file for CMSIS DSP Library + * @version V1.10.0 + * @date 08 July 2021 + * Target Processor: Cortex-M and Cortex-A cores + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#ifndef _TRANSFORM_FUNCTIONS_F16_H_ +#define _TRANSFORM_FUNCTIONS_F16_H_ + +#include "arm_math_types_f16.h" +#include "arm_math_memory.h" + +#include "dsp/none.h" +#include "dsp/utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +#if defined(ARM_FLOAT16_SUPPORTED) + + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float16_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f16; + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float16_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float16_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f16; + + + arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen); + + void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f16 ; + +arm_status arm_rfft_fast_init_f16 ( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, float16_t * pOut, + uint8_t ifftFlag); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc); + + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f16( + const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc); + + /** + * @brief Instance structure for the Floating-point MFCC function. + */ +typedef struct + { + const float16_t *dctCoefs; /**< Internal DCT coefficients */ + const float16_t *filterCoefs; /**< Internal Mel filter coefficients */ + const float16_t *windowCoefs; /**< Windowing coefficients */ + const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */ + const uint32_t *filterLengths; /**< Internal Mel filter lengths */ + uint32_t fftLen; /**< FFT length */ + uint32_t nbMelFilters; /**< Number of Mel filters */ + uint32_t nbDctOutputs; /**< Number of DCT outputs */ +#if defined(ARM_MFCC_CFFT_BASED) + /* Implementation of the MFCC is using a CFFT */ + arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */ +#else + /* Implementation of the MFCC is using a RFFT (default) */ + arm_rfft_fast_instance_f16 rfft; +#endif + } arm_mfcc_instance_f16 ; + +arm_status arm_mfcc_init_f16( + arm_mfcc_instance_f16 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float16_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float16_t *filterCoefs, + const float16_t *windowCoefs + ); + + +/** + @brief MFCC F16 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + @return none + */ + void arm_mfcc_f16( + const arm_mfcc_instance_f16 * S, + float16_t *pSrc, + float16_t *pDst, + float16_t *pTmp + ); + + +#endif /* defined(ARM_FLOAT16_SUPPORTED)*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */ diff --git a/Drivers/CMSIS/DSP/Include/dsp/utils.h b/Drivers/CMSIS/DSP/Include/dsp/utils.h new file mode 100644 index 0000000..7f5acb3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Include/dsp/utils.h @@ -0,0 +1,240 @@ +/****************************************************************************** + * @file arm_math_utils.h + * @brief Public header file for CMSIS DSP Library + * @version V1.9.0 + * @date 20. July 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_MATH_UTILS_H_ + +#define _ARM_MATH_UTILS_H_ + +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define INDEX_MASK 0x0000003F + + +#define SQ(x) ((x) * (x)) + +#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S)) + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_MATH_UTILS_H_ */ diff --git a/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h b/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h new file mode 100644 index 0000000..ec002b2 --- /dev/null +++ b/Drivers/CMSIS/DSP/PrivateInclude/arm_sorting.h @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file arm_sorting.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_SORTING_H_ +#define _ARM_SORTING_H_ + +#include "arm_math.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_bubble_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_quick_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_bitonic_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +#if defined(ARM_MATH_NEON) + +#define vtrn256_128q(a, b) \ +do { \ + float32x4_t vtrn128_temp = a.val[1]; \ + a.val[1] = b.val[0]; \ + b.val[0] = vtrn128_temp ; \ +} while (0) + +#define vtrn128_64q(a, b) \ +do { \ + float32x2_t ab, cd, ef, gh; \ + ab = vget_low_f32(a); \ + ef = vget_low_f32(b); \ + cd = vget_high_f32(a); \ + gh = vget_high_f32(b); \ + a = vcombine_f32(ab, ef); \ + b = vcombine_f32(cd, gh); \ +} while (0) + +#define vtrn256_64q(a, b) \ +do { \ + float32x2_t a_0, a_1, a_2, a_3; \ + float32x2_t b_0, b_1, b_2, b_3; \ + a_0 = vget_low_f32(a.val[0]); \ + a_1 = vget_high_f32(a.val[0]); \ + a_2 = vget_low_f32(a.val[1]); \ + a_3 = vget_high_f32(a.val[1]); \ + b_0 = vget_low_f32(b.val[0]); \ + b_1 = vget_high_f32(b.val[0]); \ + b_2 = vget_low_f32(b.val[1]); \ + b_3 = vget_high_f32(b.val[1]); \ + a.val[0] = vcombine_f32(a_0, b_0); \ + a.val[1] = vcombine_f32(a_2, b_2); \ + b.val[0] = vcombine_f32(a_1, b_1); \ + b.val[1] = vcombine_f32(a_3, b_3); \ +} while (0) + +#define vtrn128_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \ + (a) = vtrn32_tmp.val[0]; \ + (b) = vtrn32_tmp.val[1]; \ +} while (0) + +#define vtrn256_32q(a, b) \ +do { \ + float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \ + float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \ + a.val[0] = vtrn32_tmp_1.val[0]; \ + a.val[1] = vtrn32_tmp_2.val[0]; \ + b.val[0] = vtrn32_tmp_1.val[1]; \ + b.val[1] = vtrn32_tmp_2.val[1]; \ +} while (0) + +#define vminmaxq(a, b) \ + do { \ + float32x4_t minmax_tmp = (a); \ + (a) = vminq_f32((a), (b)); \ + (b) = vmaxq_f32(minmax_tmp, (b)); \ +} while (0) + +#define vminmax256q(a, b) \ + do { \ + float32x4x2_t minmax256_tmp = (a); \ + a.val[0] = vminq_f32(a.val[0], b.val[0]); \ + a.val[1] = vminq_f32(a.val[1], b.val[1]); \ + b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \ + b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \ +} while (0) + +#define vrev128q_f32(a) \ + vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a))) + +#define vrev256q_f32(a) \ + do { \ + float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \ + a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \ + a.val[1] = rev_tmp; \ +} while (0) + +#define vldrev128q_f32(a, p) \ + do { \ + a = vld1q_f32(p); \ + a = vrev128q_f32(a); \ +} while (0) + +#endif /* ARM_MATH_NEON */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_SORTING_H */ diff --git a/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h b/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h new file mode 100644 index 0000000..fdf6498 --- /dev/null +++ b/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_fft.h @@ -0,0 +1,325 @@ +/****************************************************************************** + * @file arm_vec_fft.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 07. January 2020 + ******************************************************************************/ +/* + * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FFT_H_ +#define _ARM_VEC_FFT_H_ + +#include "arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_CMPLX_ADD_A_ixB(A, B) vcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_A_ixB(A,B) vcaddq_rot270(A,B) +#define MVE_CMPLX_MULT_FLT_AxB(A,B) vcmlaq_rot90(vcmulq(A, B), A, B) +#define MVE_CMPLX_MULT_FLT_Conj_AxB(A,B) vcmlaq_rot270(vcmulq(A, B), A, B) + +#define MVE_CMPLX_MULT_FX_AxB(A,B,TyA) vqdmladhxq(vqdmlsdhq((TyA)vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB(A,B,TyA) vqdmladhq(vqdmlsdhxq((TyA)vuninitializedq_s32(), A, B), A, B) + +#define MVE_CMPLX_ADD_FX_A_ixB(A, B) vhcaddq_rot90(A,B) +#define MVE_CMPLX_SUB_FX_A_ixB(A,B) vhcaddq_rot270(A,B) + + +/** + @brief In-place 32 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_32_inpl_mve( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint64_t *src = (uint64_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint32x4_t one = vdupq_n_u32(1); + uint64x2_t inLow, inHigh; + uint64x2_t bitRevOff1Low, bitRevOff0Low; + uint64x2_t bitRevOff1High, bitRevOff0High; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + + blkCnt = bitRevLen / 8; + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + /* 64-bit index expansion */ + bitRevOff1Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + + + /* unrolled */ + bitRevTabOff = vldrhq_u32(pBitRevTab); + pBitRevTab += 4; + + bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one); + + inLow = vldrdq_gather_offset_u64(src, bitRevOff1Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff1High); + + vstrdq_scatter_offset_u64(src, bitRevOff1Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff1High, inLow); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + if (bitRevLen & 7) { + /* FFT size = 16 */ + inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low); + inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High); + + vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh); + vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow); + } +} + + + +/** + @brief In-place 16 bit reversal function for helium + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_inpl_mve( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) + +{ + uint32_t *src = (uint32_t *) pSrc; + int32_t blkCnt; /* loop counters */ + uint32x4_t bitRevTabOff; + uint16x8_t one = vdupq_n_u16(1); + uint32x4_t bitRevOff1Low, bitRevOff0Low; + uint32x4_t bitRevOff1High, bitRevOff0High; + uint32x4_t inLow, inHigh; + + /* load scheduling to increase gather load idx update / gather load distance */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + blkCnt = (bitRevLen / 16); + while (blkCnt > 0) { + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff1Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff1Low = vshrq_n_u16((uint16x8_t)bitRevOff1Low, 3); + bitRevOff1High = vshrq_n_u16((uint16x8_t)bitRevOff1High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + /* loop unrolling */ + bitRevTabOff = vldrhq_u16(pBitRevTab); + pBitRevTab += 8; + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff1Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff1High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff1High, inLow); + + blkCnt--; + } + + /* tail handling */ + blkCnt = bitRevLen & 0xf; + if (blkCnt == 8) { + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + } else if (blkCnt == 12) { + /* FFT 16 special case */ + mve_pred16_t p = vctp16q(4); + + bitRevTabOff = vldrhq_z_u16(pBitRevTab, p); + + inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low); + inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High); + + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh); + vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow); + + bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one); + bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3); + bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3); + + inLow = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0Low, p); + inHigh = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0High, p); + + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0Low, inHigh, p); + vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0High, inLow, p); + } +} + +/** + @brief Out-of-place 32 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 32-bit data type + @param[in] pSrc points to input buffer of unknown 32-bit data type + @param[in] fftLen FFT length + @return none +*/ +__STATIC_INLINE void arm_bitreversal_32_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint32_t *pDst32 = (uint32_t *) pDst; + + /* fwd indexes */ + idxOffs0 = vdupq_n_u32(0); + idxOffs1 = vdupq_n_u32(0); + idxOffs0[0] = 0; idxOffs0[2] = 4; + idxOffs1[0] = 8; idxOffs1[2] = 12; + + bitRevPos = (31 - __CLZ(fftLen)) + 5; + blkCnt = fftLen >> 2; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint64x2_t vecIn; + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs0); + idxOffs0 = idxOffs0 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs1); + idxOffs1 = idxOffs1 + 16; + vst1q(pDst32, (uint32x4_t) vecIn); + pDst32 += 4; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +/** + @brief Out-of-place 16 bit reversal function for helium + @param[out] pDst points to destination buffer of unknown 16-bit data type + @param[in] pSrc points to input buffer of unknown 16-bit data type + @param[in] fftLen FFT length + @return none +*/ + +__STATIC_INLINE void arm_bitreversal_16_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen) +{ + uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1; + uint32_t bitRevPos, blkCnt; + uint16_t *pDst16 = (uint16_t *) pDst; + uint32_t incrIdx = 0; + + /* fwd indexes */ + idxOffs0 = vidupq_wb_u32(&incrIdx, 4); // {0, 4, 8, 12} + idxOffs1 = vidupq_wb_u32(&incrIdx, 4); // {16, 20, 24, 28} + + bitRevPos = (31 - __CLZ(fftLen)) + 4; + blkCnt = fftLen >> 3; + + /* issued earlier to increase gather load idx update / gather load distance */ + /* bit-reverse fwd indexes */ + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + while (blkCnt > 0) { + uint32x4_t vecIn; + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs0); + idxOffs0 = idxOffs0 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos); + + vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs1); + idxOffs1 = idxOffs1 + 32; + vst1q(pDst16, (uint16x8_t) vecIn); + pDst16 += 8; + bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos); + + blkCnt--; + } +} + + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FFT_H_ */ diff --git a/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h b/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h new file mode 100644 index 0000000..b2a0690 --- /dev/null +++ b/Drivers/CMSIS/DSP/PrivateInclude/arm_vec_filtering.h @@ -0,0 +1,1586 @@ +/****************************************************************************** + * @file arm_vec_filtering.h + * @brief Private header file for CMSIS DSP Library + * @version V1.7.0 + * @date 30. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_FILTERING_H_ +#define _ARM_VEC_FILTERING_H_ + +#include "arm_math.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + acc2Vec = vdupq_n_f32(0.0f); \ + acc3Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_f32(acc2Vec, xVec, yVec); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_f32(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f32(acc2Vec, xVec, yVec, p0); \ + xVec = vldrwq_f32(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f32(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ + acc2 = vecAddAcrossF32Mve(acc2Vec); \ + acc3 = vecAddAcrossF32Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0);\ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX, *pSrcY; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + pSrcY = (float32_t const *) pY; \ + k = count >> 2; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + yVec = vldrwq_f32(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); \ + pSrcY += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = (count - 1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = (count - 1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + p0 = vctp32q(k+1); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + xVec = vldrwq_f32(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + } \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count)\ +{ \ + float32_t const *pSrcX; \ + const float32_t *pY1 = pY + 1; \ + f32x4_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f32(0.0f); \ + acc1Vec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + acc0Vec = vfmaq_f32(acc0Vec, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1Vec = vfmaq_f32(acc1Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + acc0Vec = vfmaq_m_f32(acc0Vec, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_f32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1Vec = vfmaq_m_f32(acc1Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF32Mve(acc0Vec); \ + acc1 = vecAddAcrossF32Mve(acc1Vec); \ +} + +#define MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count) \ +{ \ + float32_t const *pSrcX; \ + f32x4_t accVec, xVec, yVec; \ + uint32_t k; \ + \ + accVec = vdupq_n_f32(0.0f); \ + pSrcX = (float32_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + accVec = vfmaq_f32(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_f32(pY, decrIdxVec); \ + accVec = vfmaq_m_f32(accVec, xVec, yVec, p0); \ + } \ + acc = vecAddAcrossF32Mve(accVec); \ +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) + +#define MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX; \ + const q31_t *pY1 = pY + 1; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + pY1-=4; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrwq_gather_shifted_offset_s32(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); \ + pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + + + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q31_t const *pSrcX; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + pY-=4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vldrwq_gather_shifted_offset_s32(pY, decrIdxVec); \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x4U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vldrwq_s32(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 31); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrwq_s32(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ + acc2 = asrl(acc2, 31); \ + acc3 = asrl(acc3, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = count >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x4U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count)\ +{ \ + q31_t const *pSrcX, *pSrcY; \ + q31x4_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q31_t const *) pX; \ + pSrcY = (q31_t const *) pY; \ + k = (count-1) >> 2; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x4U; \ + mve_pred16_t p0 = vctp32q(k); \ + yVec = vld1q(pSrcY); pSrcY += 4; \ + xVec = vldrwq_s32(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp32q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 4; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 31); \ + acc1 = asrl(acc1, 31); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_s16(&pSrcY[-1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX, *pSrcY; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + pSrcY = (q15_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count)\ +{ \ + q15_t const *pSrcX; \ + const q15_t *pY1 = pY + 1; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + pY1-=8; \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrhq_gather_shifted_offset_s16(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc = vmlaldavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + acc = vmlaldavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = asrl(acc, 15); \ + acc = __SSAT(acc, 16); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq(acc2, xVec, yVec); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[2]); \ + acc2 = vmlaldavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrhq_s16(&pSrcX[3]); \ + acc3 = vmlaldavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc2 = asrl(acc2, 15); \ + acc3 = asrl(acc3, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ + acc2 = __SSAT(acc2, 16); \ + acc3 = __SSAT(acc3, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count) \ +{ \ + q15_t const *pSrcX; \ + q15x8_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q15_t const *) pX; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + pY-=8; \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vldrhq_gather_shifted_offset_s16(pY, decrIdxVec); \ + xVec = vldrhq_s16(&pSrcX[1]); \ + acc1 = vmlaldavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0 = vmlaldavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = asrl(acc0, 15); \ + acc1 = asrl(acc1, 15); \ + acc0 = __SSAT(acc0, 16); \ + acc1 = __SSAT(acc1, 16); \ +} + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_s8(&pSrcY[-1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec,p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc =(acc >> 7); \ + acc = __SSAT(acc, 8); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc2 = (acc2 >> 7); \ + acc3 = (acc3 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ + acc2 = __SSAT(acc2, 8); \ + acc3 = __SSAT(acc3, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX, *pSrcY; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + pSrcY = (q7_t const *) pY; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x10U; \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vld1q(pSrcY); pSrcY += 16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count)\ +{ \ + q7_t const *pSrcX; \ + const q7_t *pY1 = pY + 1; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + pY1-=16; \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + yVec = vldrbq_gather_offset_s8(pY1, decrIdxVec); \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#define MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc = vmladavaq(acc, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + acc = vmladavaq_p(acc, xVec, yVec, p0); \ + } \ + acc = __SSAT(acc >> 7, 8); \ +} + +#define MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq(acc2, xVec, yVec); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq(acc3, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[2]); \ + acc2 = vmladavaq_p(acc2, xVec, yVec, p0); \ + xVec = vldrbq_s8(&pSrcX[3]); \ + acc3 = vmladavaq_p(acc3, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ + acc2 = __SSAT(acc2 >> 7, 8); \ + acc3 = __SSAT(acc3 >> 7, 8); \ +} + +#define MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = count >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x10U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + } \ + acc0 = __SSAT(acc0 >> 7, 8); \ + acc1 = __SSAT(acc1 >> 7, 8); \ +} + + +#define MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count) \ +{ \ + q7_t const *pSrcX; \ + q7x16_t xVec, yVec; \ + uint32_t k; \ + \ + pSrcX = (q7_t const *) pX; \ + k = (count-1) >> 4; \ + \ + while (k > 0U) \ + { \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + pY-=16; \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq(acc1, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq(acc0, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = (count - 1) % 0x10U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + mve_pred16_t p0 = vctp8q(k); \ + yVec = vldrbq_gather_offset_s8(pY, decrIdxVec); \ + xVec = vldrbq_s8(&pSrcX[1]); \ + acc1 = vmladavaq_p(acc1, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp8q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 16; \ + acc0 = vmladavaq_p(acc0, xVec, yVec, p0); \ + \ + acc0 = (acc0 >> 7); \ + acc1 = (acc1 >> 7); \ + acc0 = __SSAT(acc0, 8); \ + acc1 = __SSAT(acc1, 8); \ +} + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_FILTERING_H_ */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c new file mode 100644 index 0000000..7ade747 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BasicMathFunctions.c + * Description: Combination of all basic math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_abs_f32.c" +#include "arm_abs_f64.c" +#include "arm_abs_q15.c" +#include "arm_abs_q31.c" +#include "arm_abs_q7.c" +#include "arm_add_f32.c" +#include "arm_add_f64.c" +#include "arm_add_q15.c" +#include "arm_add_q31.c" +#include "arm_add_q7.c" +#include "arm_and_u16.c" +#include "arm_and_u32.c" +#include "arm_and_u8.c" +#include "arm_dot_prod_f32.c" +#include "arm_dot_prod_f64.c" +#include "arm_dot_prod_q15.c" +#include "arm_dot_prod_q31.c" +#include "arm_dot_prod_q7.c" +#include "arm_mult_f32.c" +#include "arm_mult_f64.c" +#include "arm_mult_q15.c" +#include "arm_mult_q31.c" +#include "arm_mult_q7.c" +#include "arm_negate_f32.c" +#include "arm_negate_f64.c" +#include "arm_negate_q15.c" +#include "arm_negate_q31.c" +#include "arm_negate_q7.c" +#include "arm_not_u16.c" +#include "arm_not_u32.c" +#include "arm_not_u8.c" +#include "arm_offset_f32.c" +#include "arm_offset_f64.c" +#include "arm_offset_q15.c" +#include "arm_offset_q31.c" +#include "arm_offset_q7.c" +#include "arm_or_u16.c" +#include "arm_or_u32.c" +#include "arm_or_u8.c" +#include "arm_scale_f32.c" +#include "arm_scale_f64.c" +#include "arm_scale_q15.c" +#include "arm_scale_q31.c" +#include "arm_scale_q7.c" +#include "arm_shift_q15.c" +#include "arm_shift_q31.c" +#include "arm_shift_q7.c" +#include "arm_sub_f32.c" +#include "arm_sub_f64.c" +#include "arm_sub_q15.c" +#include "arm_sub_q31.c" +#include "arm_sub_q7.c" +#include "arm_xor_u16.c" +#include "arm_xor_u32.c" +#include "arm_xor_u8.c" +#include "arm_clip_f32.c" +#include "arm_clip_q31.c" +#include "arm_clip_q15.c" +#include "arm_clip_q7.c" diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c new file mode 100644 index 0000000..f185db4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctionsF16.c @@ -0,0 +1,37 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BasicMathFunctionsF16.c + * Description: Combination of all basic math function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_abs_f16.c" +#include "arm_add_f16.c" +#include "arm_dot_prod_f16.c" +#include "arm_mult_f16.c" +#include "arm_negate_f16.c" +#include "arm_offset_f16.c" +#include "arm_scale_f16.c" +#include "arm_sub_f16.c" +#include "arm_clip_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..37802a8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPBasicMath) + +include(configLib) +include(configDsp) + +file(GLOB SRCF64 "./*_f64.c") +file(GLOB SRCF32 "./*_f32.c") +file(GLOB SRCF16 "./*_f16.c") +file(GLOB SRCQ31 "./*_q31.c") +file(GLOB SRCQ15 "./*_q15.c") +file(GLOB SRCQ7 "./*_q7.c") + +file(GLOB SRCU32 "./*_u32.c") +file(GLOB SRCU16 "./*_u16.c") +file(GLOB SRCU8 "./*_u8.c") + +add_library(CMSISDSPBasicMath STATIC ${SRCF64}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCF32}) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCF16}) +endif() + +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ31}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ15}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCQ7}) + +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU32}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU16}) +target_sources(CMSISDSPBasicMath PRIVATE ${SRCU8}) + +configLib(CMSISDSPBasicMath ${ROOT}) +configDsp(CMSISDSPBasicMath ${ROOT}) + +### Includes +target_include_directories(CMSISDSPBasicMath PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c new file mode 100644 index 0000000..0d6568b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f16.c @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f16.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrc); + vstrhq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_abs_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f16(pSrc); + res = vabsq_f16(vec1); + vst1q_f16(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = (_Float16)fabsf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000..1e67f4e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f32.c + * Description: Floating-point vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAbs Vector Absolute Value + + Computes the absolute value of a vector on an element-by-element basis. + + 
+      pDst[n] = abs(pSrc[n]),   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vabsq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrc); + vstrwq_p(pDst, vabsq(vec1), p0); + } + +} + +#else +void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vabsq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c new file mode 100644 index 0000000..04a79f7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f64.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_f64.c + * Description: Floating-point vector absolute value + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" +#include + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Floating-point vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_abs_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute and store result in destination buffer. */ + *pDst++ = fabs(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000..7c38ef5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q15.c + * Description: Q15 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q15 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000..7043aa0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q31.c + * Description: Q31 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q31 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * Tail + */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) + int32x4_t vec1; + int32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + + vec1 = vld1q_s32(pSrc); + res = vqabsq_s32(vec1); + vst1q_s32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined (ARM_MATH_MVEI) */ +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000..bd79582 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_abs_q7.c + * Description: Q7 vector absolute value + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAbs + @{ + */ + +/** + @brief Q7 vector absolute value. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = |A| + * Calculate absolute and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqabsq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqabsq(vecSrc), p0); + } +} + +#else +void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = (in > 0) ? in : (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicAbs group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c new file mode 100644 index 0000000..2b2ae8f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f16.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_add_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000..9741e4a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,199 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicAdd Vector Addition + + Element-by-element addition of two vectors. + + 
+      pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vaddq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vaddq(vec1,vec2), p0); + } + +} + +#else +void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c new file mode 100644 index 0000000..2d77233 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_f64.c + * Description: Floating-point vector addition + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Floating-point vector addition. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_add_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000..0bf9d06 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q15.c + * Description: Q15 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q15 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Add and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QADD16(inA1, inB1)); + write_q15x2_ia (&pDst, __QADD16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000..a6783e7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q31.c + * Description: Q31 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q31 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqaddq(vecA, vecB), p0); + } +} + +#else +void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000..f58ff86 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,159 @@ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_add_q7.c + * Description: Q7 vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicAdd + @{ + */ + +/** + @brief Q7 vector addition. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqaddq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqaddq(vecA, vecB), p0); + } +} +#else +void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + +#if defined (ARM_MATH_DSP) + /* Add and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8 (read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of BasicAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c new file mode 100644 index 0000000..7a7427d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u16.c + * Description: uint16_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup And Vector bitwise AND + + Compute the logical bitwise AND. + + There are separate functions for uint32_t, uint16_t, and uint7_t data types. + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vandq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vandq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c new file mode 100644 index 0000000..ddf838c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u32.c + * Description: uint32_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vandq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vandq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c new file mode 100644 index 0000000..bd1a1ab --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_and_u8.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_and_u8.c + * Description: uint8_t bitwise AND + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup And + @{ + */ + +/** + @brief Compute the logical bitwise AND of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vandq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vandq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vandq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)&(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of And group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c new file mode 100644 index 0000000..f784a23 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f16.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f16.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f16x8_t curVec0, curVec1; + f16x8_t vecLow, vecHigh; + + vecLow = vdupq_n_f16(low); + vecHigh = vdupq_n_f16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_clip_f16(const float16_t * pSrc, + float16_t * pDst, + float16_t low, + float16_t high, + uint32_t numSamples) +{ + for (uint32_t i = 0; i < numSamples; i++) + { + if ((_Float16)pSrc[i] > (_Float16)high) + pDst[i] = high; + else if ((_Float16)pSrc[i] < (_Float16)low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + @} end of BasicClip group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c new file mode 100644 index 0000000..4cc2799 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_f32.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_f32.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicClip Elementwise clipping + + Element-by-element clipping of a value. + + The value is constrained between 2 bounds. + + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise floating-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + f32x4_t curVec0, curVec1; + f32x4_t vecLow, vecHigh; + + vecLow = vdupq_n_f32(low); + vecHigh = vdupq_n_f32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxnmq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminnmq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxnmq(curVec0, vecLow); + curVec0 = vminnmq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_f32(const float32_t * pSrc, + float32_t * pDst, + float32_t low, + float32_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicClip group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c new file mode 100644 index 0000000..0d67c37 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q15.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q15x8_t curVec0, curVec1; + q15x8_t vecLow, vecHigh; + + vecLow = vdupq_n_s16(low); + vecHigh = vdupq_n_s16(high); + + curVec0 = vld1q(pSrc); + pSrc += 8; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 4; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 8; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 8; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 8; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 4) << 4); + if (blkCnt >= 8) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 8; + curVec0 = vld1q(pSrc); + pSrc += 8; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt & 7); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrhq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q15(const q15_t * pSrc, + q15_t * pDst, + q15_t low, + q15_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c new file mode 100644 index 0000000..72b80d3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q31.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q31.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q31x4_t curVec0, curVec1; + q31x4_t vecLow, vecHigh; + + vecLow = vdupq_n_s32(low); + vecHigh = vdupq_n_s32(high); + + curVec0 = vld1q(pSrc); + pSrc += 4; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 3; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 4; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 4; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 4; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 3) << 3); + if (blkCnt >= 4) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 4; + curVec0 = vld1q(pSrc); + pSrc += 4; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt & 3); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrwq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q31(const q31_t * pSrc, + q31_t * pDst, + q31_t low, + q31_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c new file mode 100644 index 0000000..a41e0c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_clip_q7.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_clip_q7.c + * Description: Floating-point vector addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + + +/** + @addtogroup BasicClip + @{ + */ + +/** + @brief Elementwise fixed-point clipping + @param[in] pSrc points to input values + @param[out] pDst points to output clipped values + @param[in] low lower bound + @param[in] high higher bound + @param[in] numSamples number of samples to clip + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t blkCnt; + q7x16_t curVec0, curVec1; + q7x16_t vecLow, vecHigh; + + vecLow = vdupq_n_s8(low); + vecHigh = vdupq_n_s8(high); + + curVec0 = vld1q(pSrc); + pSrc += 16; + /* + * unrolled x 2 to allow + * vldr/vstr/vmin/vmax + * stall free interleaving + */ + blkCnt = numSamples >> 5; + while (blkCnt--) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec1 = vld1q(pSrc); + pSrc += 16; + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec1 = vmaxq(curVec1, vecLow); + curVec0 = vld1q(pSrc); + pSrc += 16; + curVec1 = vminq(curVec1, vecHigh); + vst1q(pDst, curVec1); + pDst += 16; + } + /* + * Tail handling + */ + blkCnt = numSamples - ((numSamples >> 5) << 5); + if (blkCnt >= 16) + { + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vst1q(pDst, curVec0); + pDst += 16; + curVec0 = vld1q(pSrc); + pSrc += 16; + } + + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp8q(blkCnt & 0xf); + curVec0 = vmaxq(curVec0, vecLow); + curVec0 = vminq(curVec0, vecHigh); + vstrbq_p(pDst, curVec0, p0); + } +} + +#else +void arm_clip_q7(const q7_t * pSrc, + q7_t * pDst, + q7_t low, + q7_t high, + uint32_t numSamples) +{ + uint32_t i; + for (i = 0; i < numSamples; i++) + { + if (pSrc[i] > high) + pDst[i] = high; + else if (pSrc[i] < low) + pDst[i] = low; + else + pDst[i] = pSrc[i]; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicClip group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c new file mode 100644 index 0000000..55c88df --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f16.c @@ -0,0 +1,184 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f16.c + * Description: Floating-point dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + f16x8_t vecA, vecB; + f16x8_t vecSum; + uint32_t blkCnt; + float16_t sum = 0.0f; + vecSum = vdupq_n_f16(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary return variable */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000..62b8657 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f32.c + * Description: Floating-point dot product + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicDotProd Vector Dot Product + + Computes the dot product of two vectors. + The vectors are multiplied element-by-element and then summed. + + 
+      sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + f32x4_t vecA, vecB; + f32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + * and advance vector source and destination pointers + */ + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecSum = vfmaq(vecSum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vecSum = vfmaq_m(vecSum, vecA, vecB, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum; + +} + +#else + +void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary return variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t accum = vdupq_n_f32(0); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + while (blkCnt > 0U) + { + /* C = A[0]*B[0] + A[1]*B[1] + A[2]*B[2] + ... + A[blockSize-1]*B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + accum = vmlaq_f32(accum, vec1, vec2); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + + /* Decrement the loop counter */ + blkCnt--; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(accum), vget_high_f32(accum))); +#else + tmp = vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c new file mode 100644 index 0000000..a4cd07c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f64.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_f64.c + * Description: Floating-point dot product + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of floating-point vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + */ + +void arm_dot_prod_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary return variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum; +} + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000..cb42609 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q15.c + * Description: Q15 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + results are added to a 64-bit accumulator in 34.30 format. + Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + there is no risk of overflow. + The return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + q63_t sum = 0LL; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmlaldavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} + +#else +void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* Calculate dot product and store result in a temporary buffer. */ + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); + sum = __SMLALD(read_q15x2_ia (&pSrcA), read_q15x2_ia (&pSrcB), sum); +#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLALD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 34.30 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000..b85da37 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q31.c + * Description: Q31 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q31 vectors. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[in] blockSize number of samples in each vector. + @param[out] result output result returned here. + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + are truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + There are 15 guard bits in the accumulator and there is no risk of overflow as long as + the length of the vectors is less than 2^16 elements. + The return result is in 16.48 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA; + q31x4_t vecB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vrmlaldavhaq_p(sum, vecA, vecB, p0); + } + + /* + * vrmlaldavhaq provides extra intermediate accumulator headroom. + * limiting the need of intermediate scaling + * Scalar variant uses 2.48 accu format by right shifting accumulators by 14. + * 16.48 output conversion is performed outside the loop by scaling accu. by 6 + */ + *result = asrl(sum, (14 - 8)); +} + +#else +void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ + sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 16.48 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000..2de4e27 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dot_prod_q7.c + * Description: Q7 dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicDotProd + @{ + */ + +/** + @brief Dot product of Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] result output result returned here + @return none + + @par Scaling and Overflow Behavior + The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + results are added to an accumulator in 18.14 format. + Nonsaturating additions are used and there is no danger of wrap around as long as + the vectors are less than 2^18 elements long. + The return result is in 18.14 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + q31_t sum = 0; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] + * Calculate dot product and then store the result in a temporary buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq(sum, vecA, vecB); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + sum = vmladavaq_p(sum, vecA, vecB, p0); + } + + *result = sum; +} +#else +void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary return variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t input1, input2; /* Temporary variables */ + q31_t inA1, inA2, inB1, inB2; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + +#if defined (ARM_MATH_DSP) + /* read 4 samples at a time from sourceA */ + input1 = read_q7x4_ia (&pSrcA); + /* read 4 samples at a time from sourceB */ + input2 = read_q7x4_ia (&pSrcB); + + /* extract two q7_t samples to q15_t samples */ + inA1 = __SXTB16(__ROR(input1, 8)); + /* extract reminaing two samples */ + inA2 = __SXTB16(input1); + /* extract two q7_t samples to q15_t samples */ + inB1 = __SXTB16(__ROR(input2, 8)); + /* extract reminaing two samples */ + inB2 = __SXTB16(input2); + + /* multiply and accumulate two samples at a time */ + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); +#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + + /* Calculate dot product and store result in a temporary buffer. */ +//#if defined (ARM_MATH_DSP) +// sum = __SMLAD(*pSrcA++, *pSrcB++, sum); +//#else + sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++); +//#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer in 18.14 format */ + *result = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicDotProd group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c new file mode 100644 index 0000000..c1115ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f16.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_mult_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) * (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000..4df04e9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f32.c + * Description: Floating-point vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicMult Vector Multiplication + + Element-by-element multiplication of two vectors. + + 
+      pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vmulq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vmulq(vec1,vec2), p0); + } + +} + +#else +void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply the inputs and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vmulq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c new file mode 100644 index 0000000..1a5afd9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_f64.c + * Description: Floating-point vector multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Floating-point vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_mult_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000..17951c7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q15.c + * Description: Q15 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q15 vector multiplication + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2, inB1, inB2; /* Temporary input variables */ + q15_t out1, out2, out3, out4; /* Temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + /* read 2 samples at a time from sourceA */ + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 samples at a time from sourceB */ + inB2 = read_q15x2_ia (&pSrcB); + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) (inA1 ) * (q15_t) (inB1 )); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 ) * (q15_t) (inB2 )); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT(mul1 >> 15, 16); + out2 = (q15_t) __SSAT(mul2 >> 15, 16); + out3 = (q15_t) __SSAT(mul3 >> 15, 16); + out4 = (q15_t) __SSAT(mul4 >> 15, 16); + + /* store result to destination */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(out2, out1, 16)); + write_q15x2_ia (&pDst, __PKHBT(out4, out3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pDst, __PKHBT(out3, out4, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000..63ad73c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q31.c + * Description: Q31 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q31 vector multiplication. + @param[in] pSrcA points to the first input vector. + @param[in] pSrcB points to the second input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t out; /* Temporary output variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply inputs and store result in destination buffer. */ + out = ((q63_t) *pSrcA++ * *pSrcB++) >> 32; + out = __SSAT(out, 31); + *pDst++ = out << 1U; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000..7be80db --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mult_q7.c + * Description: Q7 vector multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicMult + @{ + */ + +/** + @brief Q7 vector multiplication + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A * B + * Multiply the inputs and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqdmulhq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqdmulhq(vecA, vecB), p0); + } +} + +#else +void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * B */ + +#if defined (ARM_MATH_DSP) + /* Multiply inputs and store results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * B */ + + /* Multiply input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c new file mode 100644 index 0000000..187e511 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f16.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f16.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f16x8_t vec1; + f16x8_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_negate_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000..4f243cd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f32.c + * Description: Negates floating-point vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicNegate Vector Negate + + Negates the elements of a vector. + + 
+      pDst[n] = -pSrc[n],   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + f32x4_t vec1; + f32x4_t res; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = |A| */ + + /* Calculate absolute values and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vnegq(vec1); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + if (blkCnt > 0U) + { + /* C = |A| */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vnegq(vec1), p0); + } + +} + +#else +void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vnegq_f32(vec1); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c new file mode 100644 index 0000000..c8a7341 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f64.c @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_f64.c + * Description: Negates floating-point vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a floating-point vector. + @param[in] pSrc points to input vector. + @param[out] pDst points to output vector. + @param[in] blockSize number of samples in each vector. + @return none + */ + +void arm_negate_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000..43d5b0d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q15.c + * Description: Negates Q15 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q15 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Conditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (2 samples at a time). */ + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); + + in1 = read_q15x2_ia (&pSrc); + write_q15x2_ia (&pDst, __QSUB16(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000..3ee77ed --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q31.c + * Description: Negates Q31 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000..9fd3122 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_negate_q7.c + * Description: Negates Q7 vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicNegate + @{ + */ + +/** + @brief Negates the elements of a Q7 vector. + @param[in] pSrc points to the input vector. + @param[out] pDst points to the output vector. + @param[in] blockSize number of samples in each vector. + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = -A + * Negate and then store the results in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqnegq(vecSrc)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqnegq(vecSrc), p0); + } +} + +#else +void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q7_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t in1; /* Temporary input variable */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = -A */ + +#if defined (ARM_MATH_DSP) + /* Negate and store result in destination buffer (4 samples at a time). */ + in1 = read_q7x4_ia (&pSrc); + write_q7x4_ia (&pDst, __QSUB8(0, in1)); +#else + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; + + in = *pSrc++; + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = -A */ + + /* Negate and store result in destination buffer. */ + in = *pSrc++; + +#if defined (ARM_MATH_DSP) + *pDst++ = (q7_t) __QSUB8(0, in); +#else + *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicNegate group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c new file mode 100644 index 0000000..e553d28 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u16.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u16.c + * Description: uint16_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Not Vector bitwise NOT + + Compute the logical bitwise NOT. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u16(vecSrc) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vmvnq_u16(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t inV; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + inV = vld1q_u16(pSrc); + + vst1q_u16(pDst, vmvnq_u16(inV) ); + + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c new file mode 100644 index 0000000..f46284c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u32.c + * Description: uint32_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u32(vecSrc) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vmvnq_u32(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t inV; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inV = vld1q_u32(pSrc); + + vst1q_u32(pDst, vmvnq_u32(inV) ); + + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c new file mode 100644 index 0000000..e068283 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_not_u8.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_not_u8.c + * Description: uint8_t bitwise NOT + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Not + @{ + */ + +/** + @brief Compute the logical bitwise NOT of a fixed-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + + vst1q(pDst, vmvnq_u8(vecSrc) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vmvnq_u8(vecSrc), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t inV; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + inV = vld1q_u8(pSrc); + + vst1q_u8(pDst, vmvnq_u8(inV) ); + + pSrc += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = ~(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Not group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c new file mode 100644 index 0000000..9aeb1e7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f16.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f16.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_offset_f16( + const float16_t * pSrc, + float16_t offset, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) + (_Float16)offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000..a68df05 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f32.c + * Description: Floating-point vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicOffset Vector Offset + + Adds a constant offset to each element of a vector. + + 
+      pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.
+
+ + The functions support in-place computation allowing the source and + destination pointers to reference the same memory buffer. + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vaddq(vec1,offset); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vaddq(vec1, offset), p0); + } + + +} + +#else +void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vaddq_f32(vec1,vdupq_n_f32(offset)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c new file mode 100644 index 0000000..0b39da4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_f64.c + * Description: Floating-point vector offset + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_offset_f64( + const float64_t * pSrc, + float64_t offset, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000..211776d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q15.c + * Description: Q15 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vstrhq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + + +#else +void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (2 samples at a time). */ + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); + write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000..2f702b0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q31.c + * Description: Q31 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vstrwq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = __QADD(*pSrc++, offset); +#else + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000..b53229d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_offset_q7.c + * Description: Q7 vector offset + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicOffset + @{ + */ + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A + offset + * Add offset and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vst1q(pDst, vqaddq(vecSrc, offset)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vstrbq_p(pDst, vqaddq(vecSrc, offset), p0); + } +} + +#else +void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t offset_packed; /* Offset packed to 32 bit */ + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + +#if defined (ARM_MATH_DSP) + /* Add offset and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QADD8(read_q7x4_ia (&pSrc), offset_packed)); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicOffset group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c new file mode 100644 index 0000000..92d2803 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u16.c + * Description: uint16_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Or Vector bitwise inclusive OR + + Compute the logical bitwise OR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, vorrq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, vorrq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Or group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c new file mode 100644 index 0000000..14cc83b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u32.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u32.c + * Description: uint32_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, vorrq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, vorrq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c new file mode 100644 index 0000000..beee07b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_or_u8.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_or_u8.c + * Description: uint8_t bitwise inclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Or + @{ + */ + +/** + @brief Compute the logical bitwise OR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, vorrq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, vorrq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, vorrq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)|(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} +/** + @} end of Or group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c new file mode 100644 index 0000000..b4b1c33 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f16.c @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f16.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_f16( + const float16_t * pSrc, + float16_t scale, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q((float16_t const *) pSrc); + vstrhq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_scale_f16( + const float16_t *pSrc, + float16_t scale, + float16_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrc++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000..59bc813 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f32.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicScale Vector Scale + + Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + + 
+      pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.
+
+ + In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The algorithm used with fixed-point data is: + + 
+      pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.
+
+ + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + offset */ + + /* Add offset and then store the results in the destination buffer. */ + vec1 = vld1q(pSrc); + res = vmulq(vec1,scale); + vst1q(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q((float32_t const *) pSrc); + vstrwq_p(pDst, vmulq(vec1, scale), p0); + } + + +} + +#else +void arm_scale_f32( + const float32_t *pSrc, + float32_t scale, + float32_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ +#if defined(ARM_MATH_NEON_EXPERIMENTAL) + f32x4_t vec1; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale the input and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrc); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + float32_t in1, in2, in3, in4; + + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in1 = (*pSrc++) * scale; + + in2 = (*pSrc++) * scale; + + in3 = (*pSrc++) * scale; + + in4 = (*pSrc++) * scale; + + *pDst++ = in1; + *pDst++ = in2; + *pDst++ = in3; + *pDst++ = in4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c new file mode 100644 index 0000000..cb2452b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_f64.c + * Description: Multiplies a floating-point vector by a scalar + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_scale_f64( + const float64_t *pSrc, + float64_t scale, + float64_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000..fbad607 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q15.c + * Description: Multiplies a Q15 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt);; + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s16(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrhq_p(pDst, vecDst, p0); + } + +} + + +#else +void arm_scale_q15( + const q15_t *pSrc, + q15_t scaleFract, + int8_t shift, + q15_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 15 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pSrc); + inA2 = read_q15x2_ia (&pSrc); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16)); +#else + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000..4e28441 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q31.c + * Description: Multiplies a Q31 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s32(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrwq_p(pDst, vecDst, p0); + } +} + +#else +void arm_scale_q31( + const q31_t *pSrc, + q31_t scaleFract, + int8_t shift, + q31_t *pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in, out; /* Temporary variables */ + int8_t kShift = shift + 1; /* Shift to apply after scaling */ + int8_t sign = (kShift & 0x80); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read input from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the result */ + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in >> -kShift; /* apply shifting */ + *pDst++ = out; /* Store result destination */ + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + in = *pSrc++; + in = ((q63_t) in * scaleFract) >> 32; + out = in >> -kShift; + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000..5bb4580 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_scale_q7.c + * Description: Multiplies a Q7 vector by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicScale + @{ + */ + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.7 format. + These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + /* + * C = A * scale + * Scale the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vmulhq(vecSrc, vdupq_n_s8(scaleFract)); + vecDst = vqshlq_r(vecDst, shift + 1); + vstrbq_p(pDst, vecDst, p0); + } + +} + +#else +void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + int8_t kShift = 7 - shift; /* Shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ + q7_t out1, out2, out3, out4; /* Temporary output variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * scale */ + +#if defined (ARM_MATH_DSP) + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Scale inputs and store result in the temporary variable. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); +#else + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * scale */ + + /* Scale input and store result in destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000..2de3b2b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,251 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q15.c + * Description: Shifts the elements of a Q15 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15x8_t vecDst; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q15_t in1, in2; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in1 << shiftBits), 16), + __SSAT(((q31_t) in2 << shiftBits), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT(((q31_t) in2 << shiftBits), 16), + __SSAT(((q31_t) in1 << shiftBits), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* read 2 samples from source */ + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = __SSAT(((q31_t) *pSrc++ << shiftBits), 16); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000..5405c24 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q31.c + * Description: Shifts the elements of a Q31 vector by a specified number of bits + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ +/** + @defgroup BasicShift Vector Shift + + Shifts the elements of a fixed-point vector by a specified number of bits. + There are separate functions for Q7, Q15, and Q31 data types. + The underlying algorithm used is: + + 
+      pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.
+
+ + If shift is positive then the elements of the vector are shifted to the left. + If shift is negative then the elements of the vector are shifted to the right. + + The functions support in-place computation allowing the source and destination + pointers to reference the same memory buffer. + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31x4_t vecDst; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrc = vld1q((q31_t const *) pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrwq_p(pDst, vecDst, p0); + } +} + + +#else +void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in, out; /* Temporary variables */ + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + in = *pSrc++; + out = in << shiftBits; + if (in != (out >> shiftBits)) + out = 0x7FFFFFFF ^ (in >> 31); + *pDst++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store results in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = clip_q63_to_q31((q63_t) *pSrc++ << shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000..4f83edc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_shift_q7.c + * Description: Processing function for the Q7 Shifting + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicShift + @{ + */ + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits + @param[in] pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par onditions for optimum performance + Input and output buffers should be aligned by 32-bit + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t vecDst; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A (>> or <<) shiftBits + * Shift the input and then store the result in the destination buffer. + */ + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrc = vld1q(pSrc); + vecDst = vqshlq_r(vecSrc, shiftBits); + vstrbq_p(pDst, vecDst, p0); + } +} + +#else +void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q7_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7(__SSAT(((q15_t) in1 << shiftBits), 8), + __SSAT(((q15_t) in2 << shiftBits), 8), + __SSAT(((q15_t) in3 << shiftBits), 8), + __SSAT(((q15_t) in4 << shiftBits), 8) )); +#else + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + +#if defined (ARM_MATH_DSP) + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Pack and store result in destination buffer (in single write) */ + write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits), + (in2 >> -shiftBits), + (in3 >> -shiftBits), + (in4 >> -shiftBits) )); +#else + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); + *pDst++ = (*pSrc++ >> -shiftBits); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* If the shift value is positive then do right shift else left shift */ + if (sign == 0U) + { + while (blkCnt > 0U) + { + /* C = A << shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8); + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + while (blkCnt > 0U) + { + /* C = A >> shiftBits */ + + /* Shift input and store result in destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement loop counter */ + blkCnt--; + } + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicShift group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c new file mode 100644 index 0000000..836ad43 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f16.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions_f16.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f16x8_t vec1; + f16x8_t vec2; + f16x8_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp16q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrhq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +#if defined(ARM_FLOAT16_SUPPORTED) +void arm_sub_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (_Float16)(*pSrcA++) - (_Float16)(*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000..2a07c0c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f32.c + * Description: Floating-point vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup BasicSub Vector Subtraction + + Element-by-element subtraction of two vectors. + + 
+      pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.
+
+ + There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A + B */ + + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + res = vsubq(vec1, vec2); + vst1q(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + if (blkCnt > 0U) + { + /* C = A + B */ + mve_pred16_t p0 = vctp32q(blkCnt); + vec1 = vld1q(pSrcA); + vec2 = vld1q(pSrcB); + vstrwq_p(pDst, vsubq(vec1,vec2), p0); + } + +} + +#else +void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t vec1; + f32x4_t vec2; + f32x4_t res; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pSrcA); + vec2 = vld1q_f32(pSrcB); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pDst, res); + + /* Increment pointers */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c new file mode 100644 index 0000000..e409e2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_f64.c + * Description: Floating-point vector subtraction + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Floating-point vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_sub_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000..575bd9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q15.c + * Description: Q15 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q15 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecA; + q15x8_t vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + pDst += 8; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrhq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + + +#else +void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t inB1, inB2; +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from sourceA */ + inA1 = read_q15x2_ia (&pSrcA); + inA2 = read_q15x2_ia (&pSrcA); + /* read 2 times 2 samples at a time from sourceB */ + inB1 = read_q15x2_ia (&pSrcB); + inB2 = read_q15x2_ia (&pSrcB); + + /* Subtract and store 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, __QSUB16(inA1, inB1)); + write_q15x2_ia (&pDst, __QSUB16(inA2, inB2)); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); +#else + *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000..ed879a1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q31.c + * Description: Q31 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q31 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecA; + q31x4_t vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* + * C = A + B + * Add and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + pDst += 4; + } + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrwq_p(pDst, vqsubq(vecA, vecB), p0); + } +} + +#else +void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000..1de152e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sub_q7.c + * Description: Q7 vector subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup BasicSub + @{ + */ + +/** + @brief Q7 vector subtraction. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecA; + q7x16_t vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* + * C = A - B + * Subtract and then store the results in the destination buffer. + */ + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vst1q(pDst, vqsubq(vecA, vecB)); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + /* + * advance vector source and destination pointers + */ + pSrcA += 16; + pSrcB += 16; + pDst += 16; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + vstrbq_p(pDst, vqsubq(vecA, vecB), p0); + } +} +#else +void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A - B */ + +#if defined (ARM_MATH_DSP) + /* Subtract and store result in destination buffer (4 samples at a time). */ + write_q7x4_ia (&pDst, __QSUB8(read_q7x4_ia (&pSrcA), read_q7x4_ia (&pSrcB))); +#else + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A - B */ + + /* Subtract and store result in destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c new file mode 100644 index 0000000..54042ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u16.c @@ -0,0 +1,137 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u16.c + * Description: uint16_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @defgroup Xor Vector bitwise exclusive OR + + Compute the logical bitwise XOR. + + There are separate functions for uint32_t, uint16_t, and uint8_t data types. + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecSrcA, vecSrcB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u16(vecSrcA, vecSrcB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrhq_p(pDst, veorq_u16(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint16x8_t vecA, vecB; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecA = vld1q_u16(pSrcA); + vecB = vld1q_u16(pSrcB); + + vst1q_u16(pDst, veorq_u16(vecA, vecB) ); + + pSrcA += 8; + pSrcB += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c new file mode 100644 index 0000000..9d14908 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u32.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u32.c + * Description: uint32_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecSrcA, vecSrcB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u32(vecSrcA, vecSrcB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrwq_p(pDst, veorq_u32(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32x4_t vecA, vecB; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecA = vld1q_u32(pSrcA); + vecB = vld1q_u32(pSrcB); + + vst1q_u32(pDst, veorq_u32(vecA, vecB) ); + + pSrcA += 4; + pSrcB += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c new file mode 100644 index 0000000..d708cd4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_xor_u8.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_xor_u8.c + * Description: uint8_t bitwise exclusive OR + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/basic_math_functions.h" + +/** + @ingroup groupMath + */ + +/** + @addtogroup Xor + @{ + */ + +/** + @brief Compute the logical bitwise XOR of two fixed-point vectors. + @param[in] pSrcA points to input vector A + @param[in] pSrcB points to input vector B + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ + +void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecSrcA, vecSrcB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4; + + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vst1q(pDst, veorq_u8(vecSrcA, vecSrcB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; + + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + vstrbq_p(pDst, veorq_u8(vecSrcA, vecSrcB), p0); + } +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + uint8x16_t vecA, vecB; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + + while (blkCnt > 0U) + { + vecA = vld1q_u8(pSrcA); + vecB = vld1q_u8(pSrcB); + + vst1q_u8(pDst, veorq_u8(vecA, vecB) ); + + pSrcA += 16; + pSrcB += 16; + pDst += 16; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0xF; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + *pDst++ = (*pSrcA++)^(*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +#endif /* if defined(ARM_MATH_MVEI) */ +} + +/** + @} end of Xor group + */ diff --git a/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c b/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c new file mode 100644 index 0000000..4a553dc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctions.c @@ -0,0 +1,29 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_gaussian_naive_bayes_predict_f32.c" diff --git a/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c b/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c new file mode 100644 index 0000000..57ced8c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BayesFunctions/BayesFunctionsF16.c @@ -0,0 +1,27 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all bayes function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_gaussian_naive_bayes_predict_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt new file mode 100644 index 0000000..72a202d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BayesFunctions/CMakeLists.txt @@ -0,0 +1,23 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPBayes) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPBayes STATIC) + +target_sources(CMSISDSPBayes PRIVATE arm_gaussian_naive_bayes_predict_f32.c) + +configLib(CMSISDSPBayes ${ROOT}) +configDsp(CMSISDSPBayes ${ROOT}) + +### Includes +target_include_directories(CMSISDSPBayes PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPBayes PRIVATE arm_gaussian_naive_bayes_predict_f16.c) +endif() + diff --git a/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c b/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c new file mode 100644 index 0000000..e3b2ef6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f16.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f16 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB + ) +{ + uint32_t nbClass; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn = in; + float16_t result; + f16x8_t vsigma; + _Float16 tmp; + f16x8_t vacc1, vacc2; + uint32_t index; + float16_t *logclassPriors=pBufferB; + float16_t *pLogPrior = logclassPriors; + + arm_vlog_f16((float16_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f16(0.0f16); + vacc2 = vdupq_n_f16(0.0f16); + + uint32_t blkCnt =S->vectorDimension >> 3; + while (blkCnt > 0U) { + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI))); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 8; + pTheta += 8; + pSigma += 8; + blkCnt--; + } + + blkCnt = S->vectorDimension & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vinvSigma, vtmp; + + vsigma = vaddq_n_f16(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f16(vacc1, vacc1, vlogq_f16(vmulq_n_f16(vsigma, 2.0f16 * (_Float16)PI)), p0); + + vinvSigma = vrecip_medprec_f16(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f16(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc1); + tmp -= 0.5f16 * (_Float16)vecAddAcrossF16Mve(vacc2); + + *buffer = (_Float16)tmp + (_Float16)*pLogPrior++; + buffer++; + } + + arm_max_f16(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S, + const float16_t * in, + float16_t *pOutputProbabilities, + float16_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float16_t *pPrior = S->classPriors; + const float16_t *pTheta = S->theta; + const float16_t *pSigma = S->sigma; + float16_t *buffer = pOutputProbabilities; + const float16_t *pIn=in; + float16_t result; + _Float16 sigma; + _Float16 tmp; + _Float16 acc1,acc2; + uint32_t index; + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = (_Float16)*pSigma + (_Float16)S->epsilon; + acc1 += (_Float16)logf(2.0f * PI * (float32_t)sigma); + acc2 += ((_Float16)*pIn - (_Float16)*pTheta) * ((_Float16)*pIn - (_Float16)*pTheta) / (_Float16)sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f16 * (_Float16)acc1; + tmp -= 0.5f16 * (_Float16)acc2; + + + *buffer = (_Float16)tmp + (_Float16)logf((float32_t)*pPrior++); + buffer++; + } + + arm_max_f16(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c b/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c new file mode 100644 index 0000000..56331ff --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/BayesFunctions/arm_gaussian_naive_bayes_predict_f32.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_naive_gaussian_bayes_predict_f32 + * Description: Naive Gaussian Bayesian Estimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/bayes_functions.h" +#include +#include + +#define PI_F 3.1415926535897932384626433832795f +#define DPI_F (2.0f*3.1415926535897932384626433832795f) + +/** + * @addtogroup groupBayes + * @{ + */ + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] *S points to a naive bayes instance structure + * @param[in] *in points to the elements of the input vector. + * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities + * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses + * @return The predicted class + * + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB + ) +{ + uint32_t nbClass; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn = in; + float32_t result; + f32x4_t vsigma; + float32_t tmp; + f32x4_t vacc1, vacc2; + uint32_t index; + float32_t *logclassPriors=pBufferB; + float32_t *pLogPrior = logclassPriors; + + arm_vlog_f32((float32_t *) S->classPriors, logclassPriors, S->numberOfClasses); + + pTheta = S->theta; + pSigma = S->sigma; + + for (nbClass = 0; nbClass < S->numberOfClasses; nbClass++) { + pIn = in; + + vacc1 = vdupq_n_f32(0); + vacc2 = vdupq_n_f32(0); + + uint32_t blkCnt =S->vectorDimension >> 2; + while (blkCnt > 0U) { + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = vaddq(vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI))); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq(vacc2, vtmp, vinvSigma); + + pIn += 4; + pTheta += 4; + pSigma += 4; + blkCnt--; + } + + blkCnt = S->vectorDimension & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vinvSigma, vtmp; + + vsigma = vaddq_n_f32(vld1q(pSigma), S->epsilon); + vacc1 = + vaddq_m_f32(vacc1, vacc1, vlogq_f32(vmulq_n_f32(vsigma, 2.0f * PI)), p0); + + vinvSigma = vrecip_medprec_f32(vsigma); + + vtmp = vsubq(vld1q(pIn), vld1q(pTheta)); + /* squaring */ + vtmp = vmulq(vtmp, vtmp); + + vacc2 = vfmaq_m_f32(vacc2, vtmp, vinvSigma, p0); + + pTheta += blkCnt; + pSigma += blkCnt; + } + + tmp = -0.5f * vecAddAcrossF32Mve(vacc1); + tmp -= 0.5f * vecAddAcrossF32Mve(vacc2); + + *buffer = tmp + *pLogPrior++; + buffer++; + } + + arm_max_f32(pOutputProbabilities, S->numberOfClasses, &result, &index); + + return (index); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + + const float32_t *pPrior = S->classPriors; + + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + + const float32_t *pTheta1 = S->theta + S->vectorDimension; + const float32_t *pSigma1 = S->sigma + S->vectorDimension; + + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + + float32_t result; + float32_t sigma,sigma1; + float32_t tmp,tmp1; + uint32_t index; + uint32_t vecBlkCnt; + uint32_t classBlkCnt; + float32x4_t epsilonV; + float32x4_t sigmaV,sigmaV1; + float32x4_t tmpV,tmpVb,tmpV1; + float32x2_t tmpV2; + float32x4_t thetaV,thetaV1; + float32x4_t inV; + (void)pBufferB; + + epsilonV = vdupq_n_f32(S->epsilon); + + classBlkCnt = S->numberOfClasses >> 1; + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmp1 = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + tmpV1 = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + + sigmaV1 = vld1q_f32(pSigma1); + thetaV1 = vld1q_f32(pTheta1); + + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + sigmaV1 = vaddq_f32(sigmaV1, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vmulq_n_f32(sigmaV1,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV1); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV1)); + tmpV1 = vmlsq_n_f32(tmpV1,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + pTheta1 += 4; + pSigma1 += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + tmpV2 = vpadd_f32(vget_low_f32(tmpV1),vget_high_f32(tmpV1)); + tmp1 += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + sigma1 = *pSigma1 + S->epsilon; + + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + tmp1 -= 0.5f*logf(2.0f * PI_F * sigma1); + tmp1 -= 0.5f*(*pIn - *pTheta1) * (*pIn - *pTheta1) / sigma1; + + pIn++; + pTheta++; + pSigma++; + pTheta1++; + pSigma1++; + vecBlkCnt--; + } + + *buffer++ = tmp; + *buffer++ = tmp1; + + pSigma += S->vectorDimension; + pTheta += S->vectorDimension; + pSigma1 += S->vectorDimension; + pTheta1 += S->vectorDimension; + + classBlkCnt--; + } + + classBlkCnt = S->numberOfClasses & 1; + + while(classBlkCnt > 0) + { + + + pIn = in; + + tmp = logf(*pPrior++); + tmpV = vdupq_n_f32(0.0f); + + vecBlkCnt = S->vectorDimension >> 2; + while(vecBlkCnt > 0) + { + sigmaV = vld1q_f32(pSigma); + thetaV = vld1q_f32(pTheta); + inV = vld1q_f32(pIn); + + sigmaV = vaddq_f32(sigmaV, epsilonV); + + tmpVb = vmulq_n_f32(sigmaV,DPI_F); + tmpVb = vlogq_f32(tmpVb); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + tmpVb = vsubq_f32(inV,thetaV); + tmpVb = vmulq_f32(tmpVb,tmpVb); + tmpVb = vmulq_f32(tmpVb, vinvq_f32(sigmaV)); + tmpV = vmlsq_n_f32(tmpV,tmpVb,0.5f); + + pIn += 4; + pTheta += 4; + pSigma += 4; + + vecBlkCnt--; + } + tmpV2 = vpadd_f32(vget_low_f32(tmpV),vget_high_f32(tmpV)); + tmp += vget_lane_f32(tmpV2, 0) + vget_lane_f32(tmpV2, 1); + + vecBlkCnt = S->vectorDimension & 3; + while(vecBlkCnt > 0) + { + sigma = *pSigma + S->epsilon; + tmp -= 0.5f*logf(2.0f * PI_F * sigma); + tmp -= 0.5f*(*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + vecBlkCnt--; + } + + *buffer++ = tmp; + + classBlkCnt--; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#else + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pOutputProbabilities, + float32_t *pBufferB) +{ + uint32_t nbClass; + uint32_t nbDim; + const float32_t *pPrior = S->classPriors; + const float32_t *pTheta = S->theta; + const float32_t *pSigma = S->sigma; + float32_t *buffer = pOutputProbabilities; + const float32_t *pIn=in; + float32_t result; + float32_t sigma; + float32_t tmp; + float32_t acc1,acc2; + uint32_t index; + + (void)pBufferB; + + pTheta=S->theta; + pSigma=S->sigma; + + for(nbClass = 0; nbClass < S->numberOfClasses; nbClass++) + { + + + pIn = in; + + tmp = 0.0; + acc1 = 0.0f; + acc2 = 0.0f; + for(nbDim = 0; nbDim < S->vectorDimension; nbDim++) + { + sigma = *pSigma + S->epsilon; + acc1 += logf(2.0f * PI_F * sigma); + acc2 += (*pIn - *pTheta) * (*pIn - *pTheta) / sigma; + + pIn++; + pTheta++; + pSigma++; + } + + tmp = -0.5f * acc1; + tmp -= 0.5f * acc2; + + + *buffer = tmp + logf(*pPrior++); + buffer++; + } + + arm_max_f32(pOutputProbabilities,S->numberOfClasses,&result,&index); + + return(index); +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of groupBayes group + */ diff --git a/Drivers/CMSIS/DSP/Source/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/CMakeLists.txt new file mode 100644 index 0000000..3595285 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CMakeLists.txt @@ -0,0 +1,310 @@ +cmake_minimum_required (VERSION 3.14) +cmake_policy(SET CMP0077 NEW) +project(CMSISDSP) + +# DSP Sources +SET(DSP ${ROOT}/CMSIS/DSP) + +list(APPEND CMAKE_MODULE_PATH ${DSP}/Source) +list(APPEND CMAKE_MODULE_PATH ${DSP}) + + +include(configLib) + + +option(NEON "Neon acceleration" OFF) +option(NEONEXPERIMENTAL "Neon experimental acceleration" OFF) +option(HELIUMEXPERIMENTAL "Helium experimental acceleration" OFF) +option(LOOPUNROLL "Loop unrolling" ON) +option(ROUNDING "Rounding" OFF) +option(MATRIXCHECK "Matrix Checks" OFF) +option(HELIUM "Helium acceleration (MVEF and MVEI supported)" OFF) +option(MVEF "MVEF intrinsics supported" OFF) +option(MVEI "MVEI intrinsics supported" OFF) +option(MVEFLOAT16 "Float16 MVE intrinsics supported" OFF) +option(DISABLEFLOAT16 "Disable building float16 kernels" OFF) +option(HOST "Build for host" OFF) + +# Select which parts of the CMSIS-DSP must be compiled. +# There are some dependencies between the parts but they are not tracked +# by this cmake. So, enabling some functions may require to enable some +# other ones. +option(BASICMATH "Basic Math Functions" ON) +option(COMPLEXMATH "Complex Math Functions" ON) +option(CONTROLLER "Controller Functions" ON) +option(FASTMATH "Fast Math Functions" ON) +option(FILTERING "Filtering Functions" ON) +option(MATRIX "Matrix Functions" ON) +option(STATISTICS "Statistics Functions" ON) +option(SUPPORT "Support Functions" ON) +option(TRANSFORM "Transform Functions" ON) +option(SVM "Support Vector Machine Functions" ON) +option(BAYES "Bayesian Estimators" ON) +option(DISTANCE "Distance Functions" ON) +option(INTERPOLATION "Interpolation Functions" ON) +option(QUATERNIONMATH "Quaternion Math Functions" ON) + +# When OFF it is the default behavior : all tables are included. +option(CONFIGTABLE "Configuration of table allowed" OFF) + +# When CONFIGTABLE is ON, select if all interpolation tables must be included +option(ALLFAST "All interpolation tables included" OFF) +# When CONFIGTABLE is ON, select if all FFT tables must be included +option(ALLFFT "All fft tables included" OFF) + +# Features which require inclusion of a data table. +# Since some tables may be big, the corresponding feature can be +# disabled. +# Those options are taken into account only when CONFIGTABLE is ON +option(ARM_COS_F32 "cos f32" OFF) +option(ARM_COS_Q31 "cos q31" OFF) +option(ARM_COS_Q15 "cos q15" OFF) +option(ARM_SIN_F32 "sin f32" OFF) +option(ARM_SIN_Q31 "sin q31" OFF) +option(ARM_SIN_Q15 "sin q15" OFF) +option(ARM_SIN_COS_F32 "sin cos f32" OFF) +option(ARM_SIN_COS_Q31 "sin cos q31" OFF) + +option(ARM_LMS_NORM_Q31 "lms norm q31" OFF) +option(ARM_LMS_NORM_Q15 "lms norm q15" OFF) + +option(CFFT_F64_16 "cfft f64 16" OFF) +option(CFFT_F64_32 "cfft f64 32" OFF) +option(CFFT_F64_64 "cfft f64 64" OFF) +option(CFFT_F64_128 "cfft f64 128" OFF) +option(CFFT_F64_256 "cfft f64 256" OFF) +option(CFFT_F64_512 "cfft f64 512" OFF) +option(CFFT_F64_1024 "cfft f64 1024" OFF) +option(CFFT_F64_2048 "cfft f64 2048" OFF) +option(CFFT_F64_4096 "cfft f64 4096" OFF) + +option(CFFT_F32_16 "cfft f32 16" OFF) +option(CFFT_F32_32 "cfft f32 32" OFF) +option(CFFT_F32_64 "cfft f32 64" OFF) +option(CFFT_F32_128 "cfft f32 128" OFF) +option(CFFT_F32_256 "cfft f32 256" OFF) +option(CFFT_F32_512 "cfft f32 512" OFF) +option(CFFT_F32_1024 "cfft f32 1024" OFF) +option(CFFT_F32_2048 "cfft f32 2048" OFF) +option(CFFT_F32_4096 "cfft f32 4096" OFF) + +option(CFFT_Q31_16 "cfft q31 16" OFF) +option(CFFT_Q31_32 "cfft q31 32" OFF) +option(CFFT_Q31_64 "cfft q31 64" OFF) +option(CFFT_Q31_128 "cfft q31 128" OFF) +option(CFFT_Q31_256 "cfft q31 256" OFF) +option(CFFT_Q31_512 "cfft q31 512" OFF) +option(CFFT_Q31_1024 "cfft q31 1024" OFF) +option(CFFT_Q31_2048 "cfft q31 2048" OFF) +option(CFFT_Q31_4096 "cfft q31 4096" OFF) + +option(CFFT_Q15_16 "cfft q15 16" OFF) +option(CFFT_Q15_32 "cfft q15 32" OFF) +option(CFFT_Q15_64 "cfft q15 64" OFF) +option(CFFT_Q15_128 "cfft q15 128" OFF) +option(CFFT_Q15_256 "cfft q15 256" OFF) +option(CFFT_Q15_512 "cfft q15 512" OFF) +option(CFFT_Q15_1024 "cfft q15 1024" OFF) +option(CFFT_Q15_2048 "cfft q15 2048" OFF) +option(CFFT_Q15_4096 "cfft q15 4096" OFF) + +option(RFFT_FAST_F32_32 "rfft fast f32 32" OFF) +option(RFFT_FAST_F32_64 "rfft fast f32 64" OFF) +option(RFFT_FAST_F32_128 "rfft fast f32 128" OFF) +option(RFFT_FAST_F32_256 "rfft fast f32 256" OFF) +option(RFFT_FAST_F32_512 "rfft fast f32 512" OFF) +option(RFFT_FAST_F32_1024 "rfft fast f32 1024" OFF) +option(RFFT_FAST_F32_2048 "rfft fast f32 2048" OFF) +option(RFFT_FAST_F32_4096 "rfft fast f32 4096" OFF) + + +option(RFFT_F32_128 "rfft f32 128" OFF) +option(RFFT_F32_512 "rfft f32 512" OFF) +option(RFFT_F32_2048 "rfft f32 2048" OFF) +option(RFFT_F32_8192 "rfft f32 8192" OFF) + +option(RFFT_FAST_F64_32 "rfft fast f64 32" OFF) +option(RFFT_FAST_F64_64 "rfft fast f64 64" OFF) +option(RFFT_FAST_F64_128 "rfft fast f64 128" OFF) +option(RFFT_FAST_F64_256 "rfft fast f64 256" OFF) +option(RFFT_FAST_F64_512 "rfft fast f64 512" OFF) +option(RFFT_FAST_F64_1024 "rfft fast f64 1024" OFF) +option(RFFT_FAST_F64_2048 "rfft fast f64 2048" OFF) +option(RFFT_FAST_F64_4096 "rfft fast f64 4096" OFF) + + +option(RFFT_F64_128 "rfft f64 128" OFF) +option(RFFT_F64_512 "rfft f64 512" OFF) +option(RFFT_F64_2048 "rfft f64 2048" OFF) +option(RFFT_F64_8192 "rfft f64 8192" OFF) + +option(RFFT_FAST_F16_32 "rfft fast f16 32" OFF) +option(RFFT_FAST_F16_64 "rfft fast f16 64" OFF) +option(RFFT_FAST_F16_128 "rfft fast f16 128" OFF) +option(RFFT_FAST_F16_256 "rfft fast f16 256" OFF) +option(RFFT_FAST_F16_512 "rfft fast f16 512" OFF) +option(RFFT_FAST_F16_1024 "rfft fast f16 1024" OFF) +option(RFFT_FAST_F16_2048 "rfft fast f16 2048" OFF) +option(RFFT_FAST_F16_4096 "rfft fast f16 4096" OFF) + +option(RFFT_Q31_32 "rfft q31 32" OFF) +option(RFFT_Q31_64 "rfft q31 64" OFF) +option(RFFT_Q31_128 "rfft q31 128" OFF) +option(RFFT_Q31_256 "rfft q31 256" OFF) +option(RFFT_Q31_512 "rfft q31 512" OFF) +option(RFFT_Q31_1024 "rfft q31 1024" OFF) +option(RFFT_Q31_2048 "rfft q31 2048" OFF) +option(RFFT_Q31_4096 "rfft q31 4096" OFF) +option(RFFT_Q31_8192 "rfft q31 8192" OFF) + +option(RFFT_Q15_32 "rfft q15 32" OFF) +option(RFFT_Q15_64 "rfft q15 64" OFF) +option(RFFT_Q15_128 "rfft q15 128" OFF) +option(RFFT_Q15_256 "rfft q15 256" OFF) +option(RFFT_Q15_512 "rfft q15 512" OFF) +option(RFFT_Q15_1024 "rfft q15 1024" OFF) +option(RFFT_Q15_2048 "rfft q15 2048" OFF) +option(RFFT_Q15_4096 "rfft q15 4096" OFF) +option(RFFT_Q15_8192 "rfft q15 8192" OFF) + +option(DCT4_F32_128 "dct4 f32 128" OFF) +option(DCT4_F32_512 "dct4 f32 512" OFF) +option(DCT4_F32_2048 "dct4 f32 2048" OFF) +option(DCT4_F32_8192 "dct4 f32 8192" OFF) + +option(DCT4_Q31_128 "dct4 q31 128" OFF) +option(DCT4_Q31_512 "dct4 q31 512" OFF) +option(DCT4_Q31_2048 "dct4 q31 2048" OFF) +option(DCT4_Q31_8192 "dct4 q31 8192" OFF) + +option(DCT4_Q15_128 "dct4 q15 128" OFF) +option(DCT4_Q15_512 "dct4 q15 512" OFF) +option(DCT4_Q15_2048 "dct4 q15 2048" OFF) +option(DCT4_Q15_8192 "dct4 q15 8192" OFF) + +option(ARM_CFFT_RADIX2_Q15 "deprecated q15 radix2 cfft" OFF) +option(ARM_CFFT_RADIX4_Q15 "deprecated q15 radix4 cfft" OFF) + +option(ARM_CFFT_RADIX2_Q31 "deprecated q31 radix2 cfft" OFF) +option(ARM_CFFT_RADIX4_Q31 "deprecated q31 radix4 cfft" OFF) + +########################### +# +# CMSIS DSP +# +########################### + + + +add_library(CMSISDSP INTERFACE) + +if (BASICMATH) + add_subdirectory(BasicMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPBasicMath) +endif() + +if (COMPLEXMATH) + add_subdirectory(ComplexMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPComplexMath) +endif() + +if (QUATERNIONMATH) + add_subdirectory(QuaternionMathFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPQuaternionMath) +endif() + +if (CONTROLLER) + add_subdirectory(ControllerFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPController PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPController) +endif() + +if (FASTMATH) + add_subdirectory(FastMathFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFastMath) +endif() + +if (FILTERING) + add_subdirectory(FilteringFunctions) + # Fast tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPFiltering) +endif() + +if (MATRIX) + add_subdirectory(MatrixFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPMatrix) +endif() + +if (STATISTICS) + add_subdirectory(StatisticsFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPStatistics) +endif() + +if (SUPPORT) + add_subdirectory(SupportFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPSupport) +endif() + +if (TRANSFORM) + add_subdirectory(TransformFunctions) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPTransform) +endif() + +if (FILTERING OR CONTROLLER OR FASTMATH OR TRANSFORM OR SVM OR DISTANCE) + add_subdirectory(CommonTables) + if (TRANSFORM) + # FFT tables inclusion is allowed + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FFT_ALLOW_TABLES) + endif() + endif() + if (FILTERING OR CONTROLLER OR FASTMATH) + # Select which tables to include + if (CONFIGTABLE) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_FAST_ALLOW_TABLES) + endif() + endif() + target_link_libraries(CMSISDSP INTERFACE CMSISDSPCommon) + # Common project is adding ComputeLibrary tables used by SVM and Distance + # when NEon is ON. +endif() + +if (SVM) + add_subdirectory(SVMFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPSVM) +endif() + +if (BAYES) + add_subdirectory(BayesFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPBayes) +endif() + +if (DISTANCE) + add_subdirectory(DistanceFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPDistance) +endif() + +if (INTERPOLATION) + add_subdirectory(InterpolationFunctions) + target_link_libraries(CMSISDSP INTERFACE CMSISDSPInterpolation) +endif() + +### Includes +target_include_directories(CMSISDSP INTERFACE "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt new file mode 100644 index 0000000..b6e0ed4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/CMakeLists.txt @@ -0,0 +1,52 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPCommon) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPCommon STATIC arm_common_tables.c arm_common_tables_f16.c) + +configLib(CMSISDSPCommon ${ROOT}) +configDsp(CMSISDSPCommon ${ROOT}) + +if (CONFIGTABLE AND ALLFFT) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FFT_TABLES) +endif() + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_ALL_FAST_TABLES) +endif() + +include(fft) +fft(CMSISDSPCommon) + +include(interpol) +interpol(CMSISDSPCommon) + +target_sources(CMSISDSPCommon PRIVATE arm_const_structs.c) +target_sources(CMSISDSPCommon PRIVATE arm_const_structs_f16.c) + + +### Includes +target_include_directories(CMSISDSPCommon PUBLIC "${DSP}/Include") + +if (NEON OR NEONEXPERIMENTAL) + target_sources(CMSISDSPCommon PRIVATE "${DSP}/ComputeLibrary/Source/arm_cl_tables.c") +endif() + +if (HELIUM OR MVEF) + target_sources(CMSISDSPCommon PRIVATE "${DSP}/Source/CommonTables/arm_mve_tables.c") + target_sources(CMSISDSPCommon PRIVATE "${DSP}/Source/CommonTables/arm_mve_tables_f16.c") +endif() + + +if (WRAPPER) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_BITREV_1024) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_F32_4096) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_Q31_4096) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_Q15_4096) + if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) + target_compile_definitions(CMSISDSPCommon PUBLIC ARM_TABLE_TWIDDLECOEF_F16_4096) + endif() +endif() \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c new file mode 100644 index 0000000..1a387c3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c @@ -0,0 +1,31 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_common_tables.c" +#include "arm_const_structs.c" +#include "arm_mve_tables.c" diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c new file mode 100644 index 0000000..c3e79d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/CommonTablesF16.c @@ -0,0 +1,31 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CommonTables.c + * Description: Combination of all common table source files. + * + * $Date: 08. January 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_common_tables_f16.c" +#include "arm_const_structs_f16.c" +#include "arm_mve_tables_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000..b3cb89c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,70576 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types.h" +#include "arm_common_tables.h" + +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + +/** + @par + Pseudo code for Generation of Bit reversal Table is + @par + 
for (l = 1; l <= N/4; l++)
+  {
+    for (i = 0; i< logN2; i++)
+    {
+      a[i] = l & (1 << i);
+    }
+    for (j = 0; j < logN2; j++)
+    {
+      if (a[j] != 0)
+      y[l] += (1 << ((logN2 - 1) - j));
+    }
+    y[l] = y[l] >> 1;
+   }
+ @par + where N = 4096, logN2 = 12 + @par + N is the maximum FFT Size supported +*/ + +/** + @brief Table for bit reversal process +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) +const uint16_t armBitRevTable[1024] = { + 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, 0x080, 0x480, 0x280, + 0x680, 0x180, 0x580, 0x380, 0x780, 0x040, 0x440, 0x240, 0x640, 0x140, + 0x540, 0x340, 0x740, 0x0c0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, 0x5c0, 0x3c0, + 0x7c0, 0x020, 0x420, 0x220, 0x620, 0x120, 0x520, 0x320, 0x720, 0x0a0, + 0x4a0, 0x2a0, 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x060, 0x460, 0x260, + 0x660, 0x160, 0x560, 0x360, 0x760, 0x0e0, 0x4e0, 0x2e0, 0x6e0, 0x1e0, + 0x5e0, 0x3e0, 0x7e0, 0x010, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, + 0x710, 0x090, 0x490, 0x290, 0x690, 0x190, 0x590, 0x390, 0x790, 0x050, + 0x450, 0x250, 0x650, 0x150, 0x550, 0x350, 0x750, 0x0d0, 0x4d0, 0x2d0, + 0x6d0, 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x030, 0x430, 0x230, 0x630, 0x130, + 0x530, 0x330, 0x730, 0x0b0, 0x4b0, 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, + 0x7b0, 0x070, 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, 0x0f0, + 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, 0x7f0, 0x008, 0x408, 0x208, + 0x608, 0x108, 0x508, 0x308, 0x708, 0x088, 0x488, 0x288, 0x688, 0x188, + 0x588, 0x388, 0x788, 0x048, 0x448, 0x248, 0x648, 0x148, 0x548, 0x348, + 0x748, 0x0c8, 0x4c8, 0x2c8, 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x028, + 0x428, 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0x0a8, 0x4a8, 0x2a8, + 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, 0x068, 0x468, 0x268, 0x668, 0x168, + 0x568, 0x368, 0x768, 0x0e8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, 0x3e8, + 0x7e8, 0x018, 0x418, 0x218, 0x618, 0x118, 0x518, 0x318, 0x718, 0x098, + 0x498, 0x298, 0x698, 0x198, 0x598, 0x398, 0x798, 0x058, 0x458, 0x258, + 0x658, 0x158, 0x558, 0x358, 0x758, 0x0d8, 0x4d8, 0x2d8, 0x6d8, 0x1d8, + 0x5d8, 0x3d8, 0x7d8, 0x038, 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, + 0x738, 0x0b8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, 0x7b8, 0x078, + 0x478, 0x278, 0x678, 0x178, 0x578, 0x378, 0x778, 0x0f8, 0x4f8, 0x2f8, + 0x6f8, 0x1f8, 0x5f8, 0x3f8, 0x7f8, 0x004, 0x404, 0x204, 0x604, 0x104, + 0x504, 0x304, 0x704, 0x084, 0x484, 0x284, 0x684, 0x184, 0x584, 0x384, + 0x784, 0x044, 0x444, 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0x0c4, + 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, 0x024, 0x424, 0x224, + 0x624, 0x124, 0x524, 0x324, 0x724, 0x0a4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, + 0x5a4, 0x3a4, 0x7a4, 0x064, 0x464, 0x264, 0x664, 0x164, 0x564, 0x364, + 0x764, 0x0e4, 0x4e4, 0x2e4, 0x6e4, 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x014, + 0x414, 0x214, 0x614, 0x114, 0x514, 0x314, 0x714, 0x094, 0x494, 0x294, + 0x694, 0x194, 0x594, 0x394, 0x794, 0x054, 0x454, 0x254, 0x654, 0x154, + 0x554, 0x354, 0x754, 0x0d4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, + 0x7d4, 0x034, 0x434, 0x234, 0x634, 0x134, 0x534, 0x334, 0x734, 0x0b4, + 0x4b4, 0x2b4, 0x6b4, 0x1b4, 0x5b4, 0x3b4, 0x7b4, 0x074, 0x474, 0x274, + 0x674, 0x174, 0x574, 0x374, 0x774, 0x0f4, 0x4f4, 0x2f4, 0x6f4, 0x1f4, + 0x5f4, 0x3f4, 0x7f4, 0x00c, 0x40c, 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, + 0x70c, 0x08c, 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, 0x04c, + 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, 0x74c, 0x0cc, 0x4cc, 0x2cc, + 0x6cc, 0x1cc, 0x5cc, 0x3cc, 0x7cc, 0x02c, 0x42c, 0x22c, 0x62c, 0x12c, + 0x52c, 0x32c, 0x72c, 0x0ac, 0x4ac, 0x2ac, 0x6ac, 0x1ac, 0x5ac, 0x3ac, + 0x7ac, 0x06c, 0x46c, 0x26c, 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0x0ec, + 0x4ec, 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x01c, 0x41c, 0x21c, + 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, 0x09c, 0x49c, 0x29c, 0x69c, 0x19c, + 0x59c, 0x39c, 0x79c, 0x05c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, 0x35c, + 0x75c, 0x0dc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, 0x5dc, 0x3dc, 0x7dc, 0x03c, + 0x43c, 0x23c, 0x63c, 0x13c, 0x53c, 0x33c, 0x73c, 0x0bc, 0x4bc, 0x2bc, + 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x07c, 0x47c, 0x27c, 0x67c, 0x17c, + 0x57c, 0x37c, 0x77c, 0x0fc, 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, + 0x7fc, 0x002, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, 0x702, 0x082, + 0x482, 0x282, 0x682, 0x182, 0x582, 0x382, 0x782, 0x042, 0x442, 0x242, + 0x642, 0x142, 0x542, 0x342, 0x742, 0x0c2, 0x4c2, 0x2c2, 0x6c2, 0x1c2, + 0x5c2, 0x3c2, 0x7c2, 0x022, 0x422, 0x222, 0x622, 0x122, 0x522, 0x322, + 0x722, 0x0a2, 0x4a2, 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x062, + 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, 0x0e2, 0x4e2, 0x2e2, + 0x6e2, 0x1e2, 0x5e2, 0x3e2, 0x7e2, 0x012, 0x412, 0x212, 0x612, 0x112, + 0x512, 0x312, 0x712, 0x092, 0x492, 0x292, 0x692, 0x192, 0x592, 0x392, + 0x792, 0x052, 0x452, 0x252, 0x652, 0x152, 0x552, 0x352, 0x752, 0x0d2, + 0x4d2, 0x2d2, 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x032, 0x432, 0x232, + 0x632, 0x132, 0x532, 0x332, 0x732, 0x0b2, 0x4b2, 0x2b2, 0x6b2, 0x1b2, + 0x5b2, 0x3b2, 0x7b2, 0x072, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, + 0x772, 0x0f2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, 0x3f2, 0x7f2, 0x00a, + 0x40a, 0x20a, 0x60a, 0x10a, 0x50a, 0x30a, 0x70a, 0x08a, 0x48a, 0x28a, + 0x68a, 0x18a, 0x58a, 0x38a, 0x78a, 0x04a, 0x44a, 0x24a, 0x64a, 0x14a, + 0x54a, 0x34a, 0x74a, 0x0ca, 0x4ca, 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, + 0x7ca, 0x02a, 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, 0x0aa, + 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, 0x7aa, 0x06a, 0x46a, 0x26a, + 0x66a, 0x16a, 0x56a, 0x36a, 0x76a, 0x0ea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, + 0x5ea, 0x3ea, 0x7ea, 0x01a, 0x41a, 0x21a, 0x61a, 0x11a, 0x51a, 0x31a, + 0x71a, 0x09a, 0x49a, 0x29a, 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, + 0x45a, 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0x0da, 0x4da, 0x2da, + 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, 0x03a, 0x43a, 0x23a, 0x63a, 0x13a, + 0x53a, 0x33a, 0x73a, 0x0ba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, 0x3ba, + 0x7ba, 0x07a, 0x47a, 0x27a, 0x67a, 0x17a, 0x57a, 0x37a, 0x77a, 0x0fa, + 0x4fa, 0x2fa, 0x6fa, 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x006, 0x406, 0x206, + 0x606, 0x106, 0x506, 0x306, 0x706, 0x086, 0x486, 0x286, 0x686, 0x186, + 0x586, 0x386, 0x786, 0x046, 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, + 0x746, 0x0c6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, 0x7c6, 0x026, + 0x426, 0x226, 0x626, 0x126, 0x526, 0x326, 0x726, 0x0a6, 0x4a6, 0x2a6, + 0x6a6, 0x1a6, 0x5a6, 0x3a6, 0x7a6, 0x066, 0x466, 0x266, 0x666, 0x166, + 0x566, 0x366, 0x766, 0x0e6, 0x4e6, 0x2e6, 0x6e6, 0x1e6, 0x5e6, 0x3e6, + 0x7e6, 0x016, 0x416, 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x096, + 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, 0x056, 0x456, 0x256, + 0x656, 0x156, 0x556, 0x356, 0x756, 0x0d6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, + 0x5d6, 0x3d6, 0x7d6, 0x036, 0x436, 0x236, 0x636, 0x136, 0x536, 0x336, + 0x736, 0x0b6, 0x4b6, 0x2b6, 0x6b6, 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x076, + 0x476, 0x276, 0x676, 0x176, 0x576, 0x376, 0x776, 0x0f6, 0x4f6, 0x2f6, + 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0x00e, 0x40e, 0x20e, 0x60e, 0x10e, + 0x50e, 0x30e, 0x70e, 0x08e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, + 0x78e, 0x04e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, 0x34e, 0x74e, 0x0ce, + 0x4ce, 0x2ce, 0x6ce, 0x1ce, 0x5ce, 0x3ce, 0x7ce, 0x02e, 0x42e, 0x22e, + 0x62e, 0x12e, 0x52e, 0x32e, 0x72e, 0x0ae, 0x4ae, 0x2ae, 0x6ae, 0x1ae, + 0x5ae, 0x3ae, 0x7ae, 0x06e, 0x46e, 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, + 0x76e, 0x0ee, 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, 0x01e, + 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, 0x71e, 0x09e, 0x49e, 0x29e, + 0x69e, 0x19e, 0x59e, 0x39e, 0x79e, 0x05e, 0x45e, 0x25e, 0x65e, 0x15e, + 0x55e, 0x35e, 0x75e, 0x0de, 0x4de, 0x2de, 0x6de, 0x1de, 0x5de, 0x3de, + 0x7de, 0x03e, 0x43e, 0x23e, 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0x0be, + 0x4be, 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x07e, 0x47e, 0x27e, + 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, 0x0fe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, + 0x5fe, 0x3fe, 0x7fe, 0x001 +}; +#endif + +/** + @brief Double Precision Floating-point Twiddle factors Table Generation +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(double)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(double)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_16[32] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_32[64] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, //-0.19509, 0.98079' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, //-0.38268, 0.92388' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, //-0.55557, 0.83147' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //-0.70711, 0.70711' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, //-0.83147, 0.55557' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, //-0.92388, 0.38268' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, //-0.98079, 0.19509' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, //-0.98079,-0.19509' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, //-0.92388,-0.38268' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, //-0.83147,-0.55557' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //-0.70711,-0.70711' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, //-0.55557,-0.83147' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, //-0.38268,-0.92388' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, //-0.19509,-0.98079' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509,-0.98079' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268,-0.92388' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557,-0.83147' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711,-0.70711' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147,-0.55557' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388,-0.38268' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079,-0.19509' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_64[128] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + }; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_128[256] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988' + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518' + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918' + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079' + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003' + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694' + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154' + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388' + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399' + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192' + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773' + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147' + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321' + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301' + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095' + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711' + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156' + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439' + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957' + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557' + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141' + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714' + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756' + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268' + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689' + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028' + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298' + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509' + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673' + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017' + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068' + 0xbff0000000000000, 0x0000000000000000, // -1, 0' + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068' + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017' + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673' + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509' + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298' + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028' + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689' + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268' + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756' + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714' + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141' + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557' + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957' + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439' + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156' + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711' + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095' + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301' + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321' + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147' + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773' + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192' + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399' + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388' + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154' + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694' + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003' + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079' + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918' + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518' + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988' + 0x0000000000000000, 0xbff0000000000000, // 0, -1' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_256[512] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_512[1024] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, //-0.012272, 0.99992 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, //-0.024541, 0.9997 + 0xbfa2d865759455cd, 0x3feffa72effef75d, //-0.036807, 0.99932 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, //-0.049068, 0.9988 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, //-0.061321, 0.99812 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, //-0.073565, 0.99729 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //-0.085797, 0.99631 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, //-0.098017, 0.99518 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992,-0.012272 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997,-0.024541 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932,-0.036807 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988,-0.049068 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812,-0.061321 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729,-0.073565 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631,-0.085797 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518,-0.098017 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, //-0.098017, -0.99518 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //-0.085797, -0.99631 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, //-0.073565, -0.99729 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, //-0.061321, -0.99812 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, //-0.049068, -0.9988 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, //-0.036807, -0.99932 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, //-0.024541, -0.9997 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, //-0.012272, -0.99992 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_1024[2048] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_2048[4096] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) +/** + @par + Example code for Double Precision Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_4096[8192] = { + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, // 0.0092038, 0.99996 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, // 0.0076698, 0.99997 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, // 0.0061359, 0.99998 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, // 0.0046019, 0.99999 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0xbf5921faaee6472d, 0x3feffffd88586ee6, // -0.001534, 1 + 0xbf6921f8becca4ba, 0x3feffff621621d02, // -0.003068, 1 + 0xbf72d97822f996bc, 0x3fefffe9cb1e2e8d, //-0.0046019, 0.99999 + 0xbf7921f0fe670071, 0x3fefffd8858e8a92, //-0.0061359, 0.99998 + 0xbf7f6a65f9a2a3c5, 0x3fefffc250b5daef, //-0.0076698, 0.99997 + 0xbf82d96b0e509703, 0x3fefffa72c978c4f, //-0.0092038, 0.99996 + 0xbf85fda037ac05e0, 0x3fefff871937ce2f, // -0.010738, 0.99994 + 0xbf8921d1fcdec784, 0x3fefff62169b92db, // -0.012272, 0.99992 + 0xbf8c45ffe1e48ad9, 0x3fefff3824c88f6f, // -0.013805, 0.9999 + 0xbf8f6a296ab997ca, 0x3fefff0943c53bd1, // -0.015339, 0.99988 + 0xbf9147270dad7132, 0x3feffed57398d2b7, // -0.016873, 0.99986 + 0xbf92d936bbe30efd, 0x3feffe9cb44b51a1, // -0.018407, 0.99983 + 0xbf946b4381fce81c, 0x3feffe5f05e578db, // -0.01994, 0.9998 + 0xbf95fd4d21fab226, 0x3feffe1c6870cb77, // -0.021474, 0.99977 + 0xbf978f535ddc9f03, 0x3feffdd4dbf78f52, // -0.023008, 0.99974 + 0xbf992155f7a3667e, 0x3feffd886084cd0d, // -0.024541, 0.9997 + 0xbf9ab354b1504fca, 0x3feffd36f624500c, // -0.026075, 0.99966 + 0xbf9c454f4ce53b1c, 0x3feffce09ce2a679, // -0.027608, 0.99962 + 0xbf9dd7458c64ab39, 0x3feffc8554cd213a, // -0.029142, 0.99958 + 0xbf9f693731d1cf01, 0x3feffc251df1d3f8, // -0.030675, 0.99953 + 0xbfa07d91ff984580, 0x3feffbbff85f9515, // -0.032208, 0.99948 + 0xbfa14685db42c17e, 0x3feffb55e425fdae, // -0.033741, 0.99943 + 0xbfa20f770ceb11c6, 0x3feffae6e1556998, // -0.035274, 0.99938 + 0xbfa2d865759455cd, 0x3feffa72effef75d, // -0.036807, 0.99932 + 0xbfa3a150f6421afc, 0x3feff9fa10348837, // -0.03834, 0.99926 + 0xbfa46a396ff86179, 0x3feff97c4208c014, // -0.039873, 0.9992 + 0xbfa5331ec3bba0eb, 0x3feff8f9858f058b, // -0.041406, 0.99914 + 0xbfa5fc00d290cd43, 0x3feff871dadb81df, // -0.042938, 0.99908 + 0xbfa6c4df7d7d5b84, 0x3feff7e5420320f9, // -0.044471, 0.99901 + 0xbfa78dbaa5874685, 0x3feff753bb1b9164, // -0.046003, 0.99894 + 0xbfa856922bb513c1, 0x3feff6bd463b444d, // -0.047535, 0.99887 + 0xbfa91f65f10dd814, 0x3feff621e3796d7e, // -0.049068, 0.9988 + 0xbfa9e835d6993c87, 0x3feff58192ee0358, // -0.0506, 0.99872 + 0xbfaab101bd5f8317, 0x3feff4dc54b1bed3, // -0.052132, 0.99864 + 0xbfab79c986698b78, 0x3feff43228de1b77, // -0.053664, 0.99856 + 0xbfac428d12c0d7e3, 0x3feff3830f8d575c, // -0.055195, 0.99848 + 0xbfad0b4c436f91d0, 0x3feff2cf08da7321, // -0.056727, 0.99839 + 0xbfadd406f9808ec8, 0x3feff21614e131ed, // -0.058258, 0.9983 + 0xbfae9cbd15ff5527, 0x3feff15833be1965, // -0.05979, 0.99821 + 0xbfaf656e79f820e0, 0x3feff095658e71ad, // -0.061321, 0.99812 + 0xbfb0170d833bf421, 0x3fefefcdaa704562, // -0.062852, 0.99802 + 0xbfb07b614e463064, 0x3fefef0102826191, // -0.064383, 0.99793 + 0xbfb0dfb28ea201e6, 0x3fefee2f6de455ba, // -0.065913, 0.99783 + 0xbfb1440134d709b2, 0x3fefed58ecb673c4, // -0.067444, 0.99772 + 0xbfb1a84d316d4f8a, 0x3fefec7d7f19cffc, // -0.068974, 0.99762 + 0xbfb20c9674ed444c, 0x3fefeb9d2530410f, // -0.070505, 0.99751 + 0xbfb270dcefdfc45b, 0x3fefeab7df1c6005, // -0.072035, 0.9974 + 0xbfb2d52092ce19f6, 0x3fefe9cdad01883a, // -0.073565, 0.99729 + 0xbfb339614e41ffa5, 0x3fefe8de8f03d75c, // -0.075094, 0.99718 + 0xbfb39d9f12c5a299, 0x3fefe7ea85482d60, // -0.076624, 0.99706 + 0xbfb401d9d0e3a507, 0x3fefe6f18ff42c84, // -0.078153, 0.99694 + 0xbfb4661179272096, 0x3fefe5f3af2e3940, // -0.079682, 0.99682 + 0xbfb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // -0.081211, 0.9967 + 0xbfb52e774a4d4d0a, 0x3fefe3e92be9d886, // -0.08274, 0.99657 + 0xbfb592a554489bc8, 0x3fefe2dc89bbff08, // -0.084269, 0.99644 + 0xbfb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // -0.085797, 0.99631 + 0xbfb65af75dd0f87b, 0x3fefe0b485181be3, // -0.087326, 0.99618 + 0xbfb6bf1b3e79b129, 0x3fefdf9922f73307, // -0.088854, 0.99604 + 0xbfb7233b9d236e71, 0x3fefde78d68653fd, // -0.090381, 0.99591 + 0xbfb787586a5d5b21, 0x3fefdd539ff1f456, // -0.091909, 0.99577 + 0xbfb7eb7196b72ee4, 0x3fefdc297f674ba9, // -0.093436, 0.99563 + 0xbfb84f8712c130a0, 0x3fefdafa7514538c, // -0.094963, 0.99548 + 0xbfb8b398cf0c38e0, 0x3fefd9c68127c78c, // -0.09649, 0.99533 + 0xbfb917a6bc29b42c, 0x3fefd88da3d12526, // -0.098017, 0.99518 + 0xbfb97bb0caaba56f, 0x3fefd74fdd40abbf, // -0.099544, 0.99503 + 0xbfb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // -0.10107, 0.99488 + 0xbfba43b90e27f3c4, 0x3fefd4c59536fae4, // -0.1026, 0.99472 + 0xbfbaa7b724495c04, 0x3fefd37914220b84, // -0.10412, 0.99456 + 0xbfbb0bb11e1d5559, 0x3fefd227aa9bd53b, // -0.10565, 0.9944 + 0xbfbb6fa6ec38f64c, 0x3fefd0d158d86087, // -0.10717, 0.99424 + 0xbfbbd3987f31fa0e, 0x3fefcf761f0c77a3, // -0.1087, 0.99407 + 0xbfbc3785c79ec2d5, 0x3fefce15fd6da67b, // -0.11022, 0.99391 + 0xbfbc9b6eb6165c42, 0x3fefccb0f4323aa3, // -0.11175, 0.99374 + 0xbfbcff533b307dc1, 0x3fefcb4703914354, // -0.11327, 0.99356 + 0xbfbd633347858ce4, 0x3fefc9d82bc2915e, // -0.11479, 0.99339 + 0xbfbdc70ecbae9fc8, 0x3fefc8646cfeb721, // -0.11632, 0.99321 + 0xbfbe2ae5b8457f77, 0x3fefc6ebc77f0887, // -0.11784, 0.99303 + 0xbfbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // -0.11937, 0.99285 + 0xbfbef2858d27561b, 0x3fefc3ebc935454c, // -0.12089, 0.99267 + 0xbfbf564e56a9730e, 0x3fefc26470e19fd3, // -0.12241, 0.99248 + 0xbfbfba124b07ad85, 0x3fefc0d832bf043a, // -0.12393, 0.99229 + 0xbfc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // -0.12545, 0.9921 + 0xbfc040c5bb67747e, 0x3fefbdb106021816, // -0.12698, 0.99191 + 0xbfc072a047ba831d, 0x3fefbc1617e44186, // -0.1285, 0.99171 + 0xbfc0a4784ab8bf1d, 0x3fefba7644f068b5, // -0.13002, 0.99151 + 0xbfc0d64dbcb26786, 0x3fefb8d18d66adb7, // -0.13154, 0.99131 + 0xbfc1082095f820b0, 0x3fefb727f187f1c7, // -0.13306, 0.99111 + 0xbfc139f0cedaf576, 0x3fefb5797195d741, // -0.13458, 0.9909 + 0xbfc16bbe5fac5865, 0x3fefb3c60dd2c199, // -0.1361, 0.9907 + 0xbfc19d8940be24e7, 0x3fefb20dc681d54d, // -0.13762, 0.99049 + 0xbfc1cf516a62a077, 0x3fefb0509be6f7db, // -0.13914, 0.99027 + 0xbfc20116d4ec7bce, 0x3fefae8e8e46cfbb, // -0.14066, 0.99006 + 0xbfc232d978aed413, 0x3fefacc79de6c44f, // -0.14218, 0.98984 + 0xbfc264994dfd340a, 0x3fefaafbcb0cfddc, // -0.1437, 0.98962 + 0xbfc296564d2b953e, 0x3fefa92b1600657c, // -0.14521, 0.9894 + 0xbfc2c8106e8e613a, 0x3fefa7557f08a517, // -0.14673, 0.98918 + 0xbfc2f9c7aa7a72af, 0x3fefa57b066e2754, // -0.14825, 0.98895 + 0xbfc32b7bf94516a7, 0x3fefa39bac7a1791, // -0.14976, 0.98872 + 0xbfc35d2d53440db2, 0x3fefa1b7717661d5, // -0.15128, 0.98849 + 0xbfc38edbb0cd8d14, 0x3fef9fce55adb2c8, // -0.1528, 0.98826 + 0xbfc3c0870a383ff6, 0x3fef9de0596b77a3, // -0.15431, 0.98802 + 0xbfc3f22f57db4893, 0x3fef9bed7cfbde29, // -0.15583, 0.98778 + 0xbfc423d4920e4166, 0x3fef99f5c0abd496, // -0.15734, 0.98754 + 0xbfc45576b1293e5a, 0x3fef97f924c9099b, // -0.15886, 0.9873 + 0xbfc48715ad84cdf5, 0x3fef95f7a9a1ec47, // -0.16037, 0.98706 + 0xbfc4b8b17f79fa88, 0x3fef93f14f85ac08, // -0.16189, 0.98681 + 0xbfc4ea4a1f624b61, 0x3fef91e616c43891, // -0.1634, 0.98656 + 0xbfc51bdf8597c5f2, 0x3fef8fd5ffae41db, // -0.16491, 0.98631 + 0xbfc54d71aa74ef02, 0x3fef8dc10a95380d, // -0.16643, 0.98605 + 0xbfc57f008654cbde, 0x3fef8ba737cb4b78, // -0.16794, 0.9858 + 0xbfc5b08c1192e381, 0x3fef898887a36c84, // -0.16945, 0.98554 + 0xbfc5e214448b3fc6, 0x3fef8764fa714ba9, // -0.17096, 0.98528 + 0xbfc61399179a6e94, 0x3fef853c9089595e, // -0.17247, 0.98501 + 0xbfc6451a831d830d, 0x3fef830f4a40c60c, // -0.17398, 0.98475 + 0xbfc676987f7216b8, 0x3fef80dd27ed8204, // -0.17549, 0.98448 + 0xbfc6a81304f64ab2, 0x3fef7ea629e63d6e, // -0.177, 0.98421 + 0xbfc6d98a0c08c8da, 0x3fef7c6a50826840, // -0.17851, 0.98394 + 0xbfc70afd8d08c4ff, 0x3fef7a299c1a322a, // -0.18002, 0.98366 + 0xbfc73c6d8055fe0a, 0x3fef77e40d068a90, // -0.18153, 0.98339 + 0xbfc76dd9de50bf31, 0x3fef7599a3a12077, // -0.18304, 0.98311 + 0xbfc79f429f59e11d, 0x3fef734a60446279, // -0.18455, 0.98282 + 0xbfc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // -0.18606, 0.98254 + 0xbfc802092c1d744b, 0x3fef6e9d4d1262ca, // -0.18756, 0.98225 + 0xbfc83366e89c64c5, 0x3fef6c3f7df5bbb7, // -0.18907, 0.98196 + 0xbfc864c0e9b2b6cf, 0x3fef69dcd652f5de, // -0.19057, 0.98167 + 0xbfc8961727c41804, 0x3fef677556883cee, // -0.19208, 0.98138 + 0xbfc8c7699b34ca7e, 0x3fef6508fef47bd5, // -0.19359, 0.98108 + 0xbfc8f8b83c69a60a, 0x3fef6297cff75cb0, // -0.19509, 0.98079 + 0xbfc92a0303c8194f, 0x3fef6021c9f148c2, // -0.19659, 0.98048 + 0xbfc95b49e9b62af9, 0x3fef5da6ed43685d, // -0.1981, 0.98018 + 0xbfc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // -0.1996, 0.97988 + 0xbfc9bdcbf2dc4366, 0x3fef58a2b1789e84, // -0.2011, 0.97957 + 0xbfc9ef0706e35a35, 0x3fef56195321c090, // -0.20261, 0.97926 + 0xbfca203e1b1831da, 0x3fef538b1faf2d07, // -0.20411, 0.97895 + 0xbfca517127e3dabc, 0x3fef50f81785c6b9, // -0.20561, 0.97863 + 0xbfca82a025b00451, 0x3fef4e603b0b2f2d, // -0.20711, 0.97832 + 0xbfcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // -0.20861, 0.978 + 0xbfcae4f1d5f3b9ab, 0x3fef492206bcabb4, // -0.21011, 0.97768 + 0xbfcb16147941ca2a, 0x3fef467bafb7bbe0, // -0.21161, 0.97735 + 0xbfcb4732ef3d6722, 0x3fef43d085ff92dd, // -0.21311, 0.97703 + 0xbfcb784d30536cda, 0x3fef412089fd8adc, // -0.21461, 0.9767 + 0xbfcba96334f15dad, 0x3fef3e6bbc1bbc65, // -0.21611, 0.97637 + 0xbfcbda74f5856330, 0x3fef3bb21cc4fe47, // -0.2176, 0.97604 + 0xbfcc0b826a7e4f63, 0x3fef38f3ac64e589, // -0.2191, 0.9757 + 0xbfcc3c8b8c4b9dd7, 0x3fef36306b67c556, // -0.2206, 0.97536 + 0xbfcc6d90535d74dc, 0x3fef33685a3aaef0, // -0.22209, 0.97503 + 0xbfcc9e90b824a6a9, 0x3fef309b794b719f, // -0.22359, 0.97468 + 0xbfcccf8cb312b286, 0x3fef2dc9c9089a9d, // -0.22508, 0.97434 + 0xbfcd00843c99c5f9, 0x3fef2af349e17507, // -0.22658, 0.97399 + 0xbfcd31774d2cbdee, 0x3fef2817fc4609ce, // -0.22807, 0.97364 + 0xbfcd6265dd3f27e3, 0x3fef2537e0a71f9f, // -0.22957, 0.97329 + 0xbfcd934fe5454311, 0x3fef2252f7763ada, // -0.23106, 0.97294 + 0xbfcdc4355db40195, 0x3fef1f6941259d7a, // -0.23255, 0.97258 + 0xbfcdf5163f01099a, 0x3fef1c7abe284708, // -0.23404, 0.97223 + 0xbfce25f281a2b684, 0x3fef19876ef1f486, // -0.23553, 0.97187 + 0xbfce56ca1e101a1b, 0x3fef168f53f7205d, // -0.23702, 0.9715 + 0xbfce879d0cc0fdaf, 0x3fef13926dad024e, // -0.23851, 0.97114 + 0xbfceb86b462de348, 0x3fef1090bc898f5f, // -0.24, 0.97077 + 0xbfcee934c2d006c7, 0x3fef0d8a410379c5, // -0.24149, 0.9704 + 0xbfcf19f97b215f1a, 0x3fef0a7efb9230d7, // -0.24298, 0.97003 + 0xbfcf4ab9679c9f5c, 0x3fef076eecade0fa, // -0.24447, 0.96966 + 0xbfcf7b7480bd3801, 0x3fef045a14cf738c, // -0.24596, 0.96928 + 0xbfcfac2abeff57ff, 0x3fef014074708ed3, // -0.24744, 0.9689 + 0xbfcfdcdc1adfedf8, 0x3feefe220c0b95ec, // -0.24893, 0.96852 + 0xbfd006c4466e54af, 0x3feefafedc1ba8b7, // -0.25041, 0.96814 + 0xbfd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // -0.2519, 0.96775 + 0xbfd037694a928cac, 0x3feef4aa278b2032, // -0.25338, 0.96737 + 0xbfd04fb80e37fdae, 0x3feef178a3e473c2, // -0.25487, 0.96698 + 0xbfd068044deab002, 0x3feeee425aa6b09a, // -0.25635, 0.96658 + 0xbfd0804e05eb661e, 0x3feeeb074c50a544, // -0.25783, 0.96619 + 0xbfd09895327b465e, 0x3feee7c77961dc9e, // -0.25931, 0.96579 + 0xbfd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // -0.26079, 0.96539 + 0xbfd0c91bda4f158d, 0x3feee13987bbebdc, // -0.26227, 0.96499 + 0xbfd0e15b4e1749cd, 0x3feeddeb6a078651, // -0.26375, 0.96459 + 0xbfd0f998277733f7, 0x3feeda9889bfe86a, // -0.26523, 0.96418 + 0xbfd111d262b1f677, 0x3feed740e7684963, // -0.26671, 0.96378 + 0xbfd12a09fc0b1b12, 0x3feed3e483849c51, // -0.26819, 0.96337 + 0xbfd1423eefc69378, 0x3feed0835e999009, // -0.26967, 0.96295 + 0xbfd15a713a28b9d9, 0x3feecd1d792c8f10, // -0.27115, 0.96254 + 0xbfd172a0d7765177, 0x3feec9b2d3c3bf84, // -0.27262, 0.96212 + 0xbfd18acdc3f4873a, 0x3feec6436ee60309, // -0.2741, 0.9617 + 0xbfd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // -0.27557, 0.96128 + 0xbfd1bb1f7b999480, 0x3feebf5668eaf2ef, // -0.27705, 0.96086 + 0xbfd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // -0.27852, 0.96043 + 0xbfd1eb6643499fbb, 0x3feeb8566b810f2a, // -0.27999, 0.96 + 0xbfd2038583d727bd, 0x3feeb4cf515b8811, // -0.28146, 0.95957 + 0xbfd21ba1fd3d2623, 0x3feeb1437af9bb34, // -0.28294, 0.95914 + 0xbfd233bbabc3bb72, 0x3feeadb2e8e7a88e, // -0.28441, 0.9587 + 0xbfd24bd28bb37672, 0x3feeaa1d9bb20af3, // -0.28588, 0.95827 + 0xbfd263e6995554ba, 0x3feea68393e65800, // -0.28735, 0.95783 + 0xbfd27bf7d0f2c346, 0x3feea2e4d212c000, // -0.28882, 0.95738 + 0xbfd294062ed59f05, 0x3fee9f4156c62dda, // -0.29028, 0.95694 + 0xbfd2ac11af483572, 0x3fee9b99229046f8, // -0.29175, 0.95649 + 0xbfd2c41a4e954520, 0x3fee97ec36016b30, // -0.29322, 0.95605 + 0xbfd2dc200907fe51, 0x3fee943a91aab4b4, // -0.29469, 0.95559 + 0xbfd2f422daec0386, 0x3fee9084361df7f3, // -0.29615, 0.95514 + 0xbfd30c22c08d6a13, 0x3fee8cc923edc388, // -0.29762, 0.95469 + 0xbfd3241fb638baaf, 0x3fee89095bad6025, // -0.29908, 0.95423 + 0xbfd33c19b83af207, 0x3fee8544ddf0d075, // -0.30054, 0.95377 + 0xbfd35410c2e18152, 0x3fee817bab4cd10d, // -0.30201, 0.95331 + 0xbfd36c04d27a4edf, 0x3fee7dadc456d850, // -0.30347, 0.95284 + 0xbfd383f5e353b6aa, 0x3fee79db29a5165a, // -0.30493, 0.95238 + 0xbfd39be3f1bc8aef, 0x3fee7603dbce74e9, // -0.30639, 0.95191 + 0xbfd3b3cefa0414b7, 0x3fee7227db6a9744, // -0.30785, 0.95144 + 0xbfd3cbb6f87a146e, 0x3fee6e472911da27, // -0.30931, 0.95096 + 0xbfd3e39be96ec271, 0x3fee6a61c55d53a7, // -0.31077, 0.95049 + 0xbfd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // -0.31222, 0.95001 + 0xbfd4135c94176602, 0x3fee6288ec48e112, // -0.31368, 0.94953 + 0xbfd42b38466e2928, 0x3fee5e95781ebf1c, // -0.31514, 0.94905 + 0xbfd44310dc8936f0, 0x3fee5a9d550467d3, // -0.31659, 0.94856 + 0xbfd45ae652bb2800, 0x3fee56a083968eb1, // -0.31805, 0.94807 + 0xbfd472b8a5571054, 0x3fee529f04729ffc, // -0.3195, 0.94759 + 0xbfd48a87d0b07fd7, 0x3fee4e98d836c0af, // -0.32096, 0.94709 + 0xbfd4a253d11b82f3, 0x3fee4a8dff81ce5e, // -0.32241, 0.9466 + 0xbfd4ba1ca2eca31c, 0x3fee467e7af35f23, // -0.32386, 0.94611 + 0xbfd4d1e24278e76a, 0x3fee426a4b2bc17e, // -0.32531, 0.94561 + 0xbfd4e9a4ac15d520, 0x3fee3e5170cbfc46, // -0.32676, 0.94511 + 0xbfd50163dc197047, 0x3fee3a33ec75ce85, // -0.32821, 0.9446 + 0xbfd5191fceda3c35, 0x3fee3611becbaf69, // -0.32966, 0.9441 + 0xbfd530d880af3c24, 0x3fee31eae870ce25, // -0.33111, 0.94359 + 0xbfd5488dedeff3be, 0x3fee2dbf6a0911d9, // -0.33255, 0.94308 + 0xbfd5604012f467b4, 0x3fee298f4439197a, // -0.334, 0.94257 + 0xbfd577eeec151e47, 0x3fee255a77a63bb8, // -0.33545, 0.94206 + 0xbfd58f9a75ab1fdd, 0x3fee212104f686e5, // -0.33689, 0.94154 + 0xbfd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // -0.33833, 0.94103 + 0xbfd5bee78b9db3b6, 0x3fee18a02fdc66d9, // -0.33978, 0.94051 + 0xbfd5d68910aee686, 0x3fee1458cec1ad83, // -0.34122, 0.93998 + 0xbfd5ee27379ea693, 0x3fee100cca2980ac, // -0.34266, 0.93946 + 0xbfd605c1fcc88f63, 0x3fee0bbc22bd8349, // -0.3441, 0.93893 + 0xbfd61d595c88c203, 0x3fee0766d9280f54, // -0.34554, 0.9384 + 0xbfd634ed533be58e, 0x3fee030cee1435b8, // -0.34698, 0.93787 + 0xbfd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // -0.34842, 0.93734 + 0xbfd6640af6f03d9e, 0x3fedfa4b3621271d, // -0.34986, 0.9368 + 0xbfd67b949cad63ca, 0x3fedf5e36a9ba59c, // -0.35129, 0.93627 + 0xbfd6931acad55f51, 0x3fedf177004b2534, // -0.35273, 0.93573 + 0xbfd6aa9d7dc77e16, 0x3feded05f7de47da, // -0.35416, 0.93518 + 0xbfd6c21cb1e39771, 0x3fede890520465ce, // -0.3556, 0.93464 + 0xbfd6d998638a0cb5, 0x3fede4160f6d8d81, // -0.35703, 0.93409 + 0xbfd6f1108f1bc9c5, 0x3feddf9730ca837b, // -0.35846, 0.93354 + 0xbfd7088530fa459e, 0x3feddb13b6ccc23d, // -0.3599, 0.93299 + 0xbfd71ff6458782ec, 0x3fedd68ba2267a25, // -0.36133, 0.93244 + 0xbfd73763c9261092, 0x3fedd1fef38a915a, // -0.36276, 0.93188 + 0xbfd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // -0.36418, 0.93133 + 0xbfd766340f2418f6, 0x3fedc8d7cb410260, // -0.36561, 0.93077 + 0xbfd77d96ca4b73a6, 0x3fedc43d52fcb453, // -0.36704, 0.93021 + 0xbfd794f5e613dfae, 0x3fedbf9e4395759a, // -0.36847, 0.92964 + 0xbfd7ac515ee2b172, 0x3fedbafa9dc1b78d, // -0.36989, 0.92907 + 0xbfd7c3a9311dcce7, 0x3fedb6526238a09b, // -0.37132, 0.92851 + 0xbfd7dafd592ba621, 0x3fedb1a591b20c38, // -0.37274, 0.92794 + 0xbfd7f24dd37341e3, 0x3fedacf42ce68ab9, // -0.37416, 0.92736 + 0xbfd8099a9c5c362d, 0x3feda83e348f613b, // -0.37559, 0.92679 + 0xbfd820e3b04eaac4, 0x3feda383a9668988, // -0.37701, 0.92621 + 0xbfd838290bb359c8, 0x3fed9ec48c26b1f3, // -0.37843, 0.92563 + 0xbfd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // -0.37985, 0.92505 + 0xbfd866a88a792ea0, 0x3fed95389e50429b, // -0.38127, 0.92447 + 0xbfd87de2a6aea963, 0x3fed906bcf328d46, // -0.38268, 0.92388 + 0xbfd89518fbff098e, 0x3fed8b9a70ef9cb4, // -0.3841, 0.92329 + 0xbfd8ac4b86d5ed44, 0x3fed86c48445a450, // -0.38552, 0.9227 + 0xbfd8c37a439f884f, 0x3fed81ea09f38b63, // -0.38693, 0.92211 + 0xbfd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // -0.38835, 0.92151 + 0xbfd8f1cc44bea329, 0x3fed78276f5617c6, // -0.38976, 0.92092 + 0xbfd908ef81ef7bd1, 0x3fed733f508c0dff, // -0.39117, 0.92032 + 0xbfd9200ee2c9be97, 0x3fed6e52a71c8547, // -0.39258, 0.91972 + 0xbfd9372a63bc93d7, 0x3fed696173c9e68b, // -0.39399, 0.91911 + 0xbfd94e420137bce3, 0x3fed646bb7574de5, // -0.3954, 0.91851 + 0xbfd96555b7ab948f, 0x3fed5f7172888a7f, // -0.39681, 0.9179 + 0xbfd97c6583890fc2, 0x3fed5a72a6221e73, // -0.39822, 0.91729 + 0xbfd993716141bdfe, 0x3fed556f52e93eb1, // -0.39962, 0.91668 + 0xbfd9aa794d47c9ee, 0x3fed506779a3d2d9, // -0.40103, 0.91606 + 0xbfd9c17d440df9f2, 0x3fed4b5b1b187524, // -0.40243, 0.91545 + 0xbfd9d87d4207b0ab, 0x3fed464a380e7242, // -0.40384, 0.91483 + 0xbfd9ef7943a8ed8a, 0x3fed4134d14dc93a, // -0.40524, 0.91421 + 0xbfda067145664d57, 0x3fed3c1ae79f2b4e, // -0.40664, 0.91359 + 0xbfda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // -0.40804, 0.91296 + 0xbfda34553b0afee5, 0x3fed31d98e9e503a, // -0.40944, 0.91234 + 0xbfda4b4127dea1e4, 0x3fed2cb220e0ef9f, // -0.41084, 0.91171 + 0xbfda622906a70b63, 0x3fed2786335f52fc, // -0.41224, 0.91107 + 0xbfda790cd3dbf31a, 0x3fed2255c6e5a4e1, // -0.41364, 0.91044 + 0xbfda8fec8bf5b166, 0x3fed1d20dc40c15c, // -0.41503, 0.90981 + 0xbfdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // -0.41643, 0.90917 + 0xbfdabd9faebc3980, 0x3fed12a98fac410c, // -0.41782, 0.90853 + 0xbfdad473125cdc08, 0x3fed0d672f59d2b9, // -0.41922, 0.90789 + 0xbfdaeb4252ca07ab, 0x3fed082054168bac, // -0.42061, 0.90724 + 0xbfdb020d6c7f4009, 0x3fed02d4feb2bd92, // -0.422, 0.9066 + 0xbfdb18d45bf8aca6, 0x3fecfd852fff6ad4, // -0.42339, 0.90595 + 0xbfdb2f971db31972, 0x3fecf830e8ce467b, // -0.42478, 0.9053 + 0xbfdb4655ae2bf757, 0x3fecf2d829f1b40e, // -0.42617, 0.90464 + 0xbfdb5d1009e15cc0, 0x3feced7af43cc773, // -0.42756, 0.90399 + 0xbfdb73c62d520624, 0x3fece819488344ce, // -0.42894, 0.90333 + 0xbfdb8a7814fd5693, 0x3fece2b32799a060, // -0.43033, 0.90267 + 0xbfdba125bd63583e, 0x3fecdd489254fe65, // -0.43171, 0.90201 + 0xbfdbb7cf2304bd01, 0x3fecd7d9898b32f6, // -0.43309, 0.90135 + 0xbfdbce744262deee, 0x3fecd2660e12c1e6, // -0.43448, 0.90068 + 0xbfdbe51517ffc0d9, 0x3fecccee20c2de9f, // -0.43586, 0.90002 + 0xbfdbfbb1a05e0edc, 0x3fecc771c2736c09, // -0.43724, 0.89935 + 0xbfdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // -0.43862, 0.89867 + 0xbfdc28ddbb6cf145, 0x3fecbc6bb638d10b, // -0.43999, 0.898 + 0xbfdc3f6d47263129, 0x3fecb6e20a00da99, // -0.44137, 0.89732 + 0xbfdc55f877b23537, 0x3fecb153f02fb87d, // -0.44275, 0.89665 + 0xbfdc6c7f4997000a, 0x3fecabc169a0b901, // -0.44412, 0.89597 + 0xbfdc8301b95b40c2, 0x3feca62a772fd919, // -0.4455, 0.89528 + 0xbfdc997fc3865388, 0x3feca08f19b9c449, // -0.44687, 0.8946 + 0xbfdcaff964a0421d, 0x3fec9aef521bd480, // -0.44824, 0.89391 + 0xbfdcc66e9931c45d, 0x3fec954b213411f5, // -0.44961, 0.89322 + 0xbfdcdcdf5dc440ce, 0x3fec8fa287e13305, // -0.45098, 0.89253 + 0xbfdcf34baee1cd21, 0x3fec89f587029c13, // -0.45235, 0.89184 + 0xbfdd09b389152ec1, 0x3fec84441f785f61, // -0.45372, 0.89115 + 0xbfdd2016e8e9db5b, 0x3fec7e8e52233cf3, // -0.45508, 0.89045 + 0xbfdd3675caebf962, 0x3fec78d41fe4a267, // -0.45645, 0.88975 + 0xbfdd4cd02ba8609c, 0x3fec7315899eaad7, // -0.45781, 0.88905 + 0xbfdd632607ac9aa9, 0x3fec6d5290341eb2, // -0.45918, 0.88835 + 0xbfdd79775b86e389, 0x3fec678b3488739b, // -0.46054, 0.88764 + 0xbfdd8fc423c62a25, 0x3fec61bf777fcc48, // -0.4619, 0.88693 + 0xbfdda60c5cfa10d8, 0x3fec5bef59fef85a, // -0.46326, 0.88622 + 0xbfddbc5003b2edf8, 0x3fec561adceb743e, // -0.46462, 0.88551 + 0xbfddd28f1481cc58, 0x3fec5042012b6907, // -0.46598, 0.8848 + 0xbfdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // -0.46733, 0.88408 + 0xbfddfeff66a941de, 0x3fec44833141c004, // -0.46869, 0.88336 + 0xbfde1530a12779f4, 0x3fec3e9d3ee7d262, // -0.47004, 0.88264 + 0xbfde2b5d3806f63b, 0x3fec38b2f180bdb1, // -0.4714, 0.88192 + 0xbfde418527dc4ffa, 0x3fec32c449f60831, // -0.47275, 0.8812 + 0xbfde57a86d3cd824, 0x3fec2cd14931e3f1, // -0.4741, 0.88047 + 0xbfde6dc704be97e2, 0x3fec26d9f01f2eaf, // -0.47545, 0.87974 + 0xbfde83e0eaf85113, 0x3fec20de3fa971b0, // -0.4768, 0.87901 + 0xbfde99f61c817eda, 0x3fec1ade38bce19b, // -0.47815, 0.87828 + 0xbfdeb00695f25620, 0x3fec14d9dc465e58, // -0.47949, 0.87755 + 0xbfdec61253e3c61b, 0x3fec0ed12b3372e9, // -0.48084, 0.87681 + 0xbfdedc1952ef78d5, 0x3fec08c426725549, // -0.48218, 0.87607 + 0xbfdef21b8fafd3b5, 0x3fec02b2cef1e641, // -0.48353, 0.87533 + 0xbfdf081906bff7fd, 0x3febfc9d25a1b147, // -0.48487, 0.87459 + 0xbfdf1e11b4bbc35c, 0x3febf6832b71ec5b, // -0.48621, 0.87384 + 0xbfdf3405963fd068, 0x3febf064e15377dd, // -0.48755, 0.87309 + 0xbfdf49f4a7e97729, 0x3febea424837de6d, // -0.48889, 0.87235 + 0xbfdf5fdee656cda3, 0x3febe41b611154c1, // -0.49023, 0.8716 + 0xbfdf75c44e26a852, 0x3febddf02cd2b983, // -0.49156, 0.87084 + 0xbfdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // -0.4929, 0.87009 + 0xbfdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // -0.49423, 0.86933 + 0xbfdfb7575c24d2de, 0x3febcb54cb0d2327, // -0.49557, 0.86857 + 0xbfdfcd2947c1ff57, 0x3febc5186bf8361d, // -0.4969, 0.86781 + 0xbfdfe2f64be7120f, 0x3febbed7c49380ea, // -0.49823, 0.86705 + 0xbfdff8be6537615e, 0x3febb892d5d5dad5, // -0.49956, 0.86628 + 0xbfe00740c82b82e0, 0x3febb249a0b6c40d, // -0.50089, 0.86551 + 0xbfe0121fe4f56d2c, 0x3febabfc262e6586, // -0.50221, 0.86474 + 0xbfe01cfc874c3eb7, 0x3feba5aa673590d2, // -0.50354, 0.86397 + 0xbfe027d6ad83287e, 0x3feb9f5464c5bffc, // -0.50486, 0.8632 + 0xbfe032ae55edbd95, 0x3feb98fa1fd9155e, // -0.50619, 0.86242 + 0xbfe03d837edff370, 0x3feb929b996a5b7f, // -0.50751, 0.86165 + 0xbfe0485626ae221a, 0x3feb8c38d27504e9, // -0.50883, 0.86087 + 0xbfe053264bad0483, 0x3feb85d1cbf52c02, // -0.51015, 0.86009 + 0xbfe05df3ec31b8b6, 0x3feb7f6686e792ea, // -0.51147, 0.8593 + 0xbfe068bf0691c028, 0x3feb78f70449a34b, // -0.51279, 0.85852 + 0xbfe073879922ffed, 0x3feb728345196e3e, // -0.5141, 0.85773 + 0xbfe07e4da23bc102, 0x3feb6c0b4a55ac17, // -0.51542, 0.85694 + 0xbfe089112032b08c, 0x3feb658f14fdbc47, // -0.51673, 0.85615 + 0xbfe093d2115ee018, 0x3feb5f0ea611a532, // -0.51804, 0.85535 + 0xbfe09e907417c5e1, 0x3feb5889fe921405, // -0.51936, 0.85456 + 0xbfe0a94c46b53d0b, 0x3feb52011f805c92, // -0.52067, 0.85376 + 0xbfe0b405878f85ec, 0x3feb4b7409de7925, // -0.52198, 0.85296 + 0xbfe0bebc34ff4646, 0x3feb44e2beaf0a61, // -0.52328, 0.85216 + 0xbfe0c9704d5d898f, 0x3feb3e4d3ef55712, // -0.52459, 0.85136 + 0xbfe0d421cf03c12b, 0x3feb37b38bb54c09, // -0.5259, 0.85055 + 0xbfe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // -0.5272, 0.84974 + 0xbfe0e97d078fd23b, 0x3feb2a738eb51f33, // -0.5285, 0.84893 + 0xbfe0f426bb2a8e7d, 0x3feb23cd470013b4, // -0.5298, 0.84812 + 0xbfe0fecdd1770537, 0x3feb1d22cfdadcc6, // -0.5311, 0.84731 + 0xbfe1097248d0a956, 0x3feb16742a4ca2f5, // -0.5324, 0.84649 + 0xbfe114141f935545, 0x3feb0fc1575d33db, // -0.5337, 0.84567 + 0xbfe11eb3541b4b22, 0x3feb090a58150200, // -0.535, 0.84485 + 0xbfe1294fe4c5350a, 0x3feb024f2d7d24a9, // -0.53629, 0.84403 + 0xbfe133e9cfee254e, 0x3feafb8fd89f57b6, // -0.53759, 0.84321 + 0xbfe13e8113f396c1, 0x3feaf4cc5a85fb73, // -0.53888, 0.84238 + 0xbfe14915af336ceb, 0x3feaee04b43c1474, // -0.54017, 0.84155 + 0xbfe153a7a00bf453, 0x3feae738e6cd4b67, // -0.54146, 0.84073 + 0xbfe15e36e4dbe2bc, 0x3feae068f345ecef, // -0.54275, 0.83989 + 0xbfe168c37c025764, 0x3fead994dab2e979, // -0.54404, 0.83906 + 0xbfe1734d63dedb49, 0x3fead2bc9e21d511, // -0.54532, 0.83822 + 0xbfe17dd49ad16161, 0x3feacbe03ea0e73b, // -0.54661, 0.83739 + 0xbfe188591f3a46e5, 0x3feac4ffbd3efac8, // -0.54789, 0.83655 + 0xbfe192daef7a5386, 0x3feabe1b1b0b8dac, // -0.54918, 0.83571 + 0xbfe19d5a09f2b9b8, 0x3feab7325916c0d4, // -0.55046, 0.83486 + 0xbfe1a7d66d0516e6, 0x3feab045787157ff, // -0.55174, 0.83402 + 0xbfe1b250171373be, 0x3feaa9547a2cb98e, // -0.55302, 0.83317 + 0xbfe1bcc706804467, 0x3feaa25f5f5aee60, // -0.55429, 0.83232 + 0xbfe1c73b39ae68c8, 0x3fea9b66290ea1a3, // -0.55557, 0.83147 + 0xbfe1d1acaf012cc2, 0x3fea9468d85b20ae, // -0.55685, 0.83062 + 0xbfe1dc1b64dc4872, 0x3fea8d676e545ad2, // -0.55812, 0.82976 + 0xbfe1e68759a3e074, 0x3fea8661ec0ee133, // -0.55939, 0.8289 + 0xbfe1f0f08bbc861b, 0x3fea7f58529fe69d, // -0.56066, 0.82805 + 0xbfe1fb56f98b37b8, 0x3fea784aa31d3f55, // -0.56193, 0.82718 + 0xbfe205baa17560d6, 0x3fea7138de9d60f5, // -0.5632, 0.82632 + 0xbfe2101b81e0da78, 0x3fea6a230637623b, // -0.56447, 0.82546 + 0xbfe21a799933eb58, 0x3fea63091b02fae2, // -0.56573, 0.82459 + 0xbfe224d4e5d5482e, 0x3fea5beb1e188375, // -0.567, 0.82372 + 0xbfe22f2d662c13e1, 0x3fea54c91090f524, // -0.56826, 0.82285 + 0xbfe23983189fdfd5, 0x3fea4da2f385e997, // -0.56952, 0.82198 + 0xbfe243d5fb98ac1f, 0x3fea4678c8119ac8, // -0.57078, 0.8211 + 0xbfe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // -0.57204, 0.82023 + 0xbfe258734cbb7110, 0x3fea38184a593bc6, // -0.5733, 0.81935 + 0xbfe262bdb7b795a2, 0x3fea30e1fa4cbf81, // -0.57455, 0.81847 + 0xbfe26d054cdd12df, 0x3fea29a7a0462782, // -0.57581, 0.81758 + 0xbfe2774a0a961612, 0x3fea22693d62ccb9, // -0.57706, 0.8167 + 0xbfe2818bef4d3cba, 0x3fea1b26d2c0a75e, // -0.57831, 0.81581 + 0xbfe28bcaf96d94ba, 0x3fea13e0617e4ec7, // -0.57956, 0.81493 + 0xbfe2960727629ca8, 0x3fea0c95eabaf937, // -0.58081, 0.81404 + 0xbfe2a040779843fb, 0x3fea05476f967bb5, // -0.58206, 0.81314 + 0xbfe2aa76e87aeb58, 0x3fe9fdf4f13149de, // -0.58331, 0.81225 + 0xbfe2b4aa787764c4, 0x3fe9f69e70ac75bc, // -0.58455, 0.81135 + 0xbfe2bedb25faf3ea, 0x3fe9ef43ef29af94, // -0.5858, 0.81046 + 0xbfe2c908ef734e57, 0x3fe9e7e56dcb45bd, // -0.58704, 0.80956 + 0xbfe2d333d34e9bb7, 0x3fe9e082edb42472, // -0.58828, 0.80866 + 0xbfe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // -0.58952, 0.80775 + 0xbfe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // -0.59076, 0.80685 + 0xbfe2f1a30d86773a, 0x3fe9ca438080eadb, // -0.592, 0.80594 + 0xbfe2fbc24b441015, 0x3fe9c2d110f075c3, // -0.59323, 0.80503 + 0xbfe305de9b921a94, 0x3fe9bb5aa85f2098, // -0.59447, 0.80412 + 0xbfe30ff7fce17035, 0x3fe9b3e047f38741, // -0.5957, 0.80321 + 0xbfe31a0e6da35e44, 0x3fe9ac61f0d4e247, // -0.59693, 0.80229 + 0xbfe32421ec49a620, 0x3fe9a4dfa42b06b2, // -0.59816, 0.80138 + 0xbfe32e3277467d6b, 0x3fe99d59631e65d5, // -0.59939, 0.80046 + 0xbfe338400d0c8e57, 0x3fe995cf2ed80d22, // -0.60062, 0.79954 + 0xbfe3424aac0ef7d6, 0x3fe98e410881a600, // -0.60184, 0.79861 + 0xbfe34c5252c14de1, 0x3fe986aef1457594, // -0.60307, 0.79769 + 0xbfe35656ff9799ae, 0x3fe97f18ea4e5c9e, // -0.60429, 0.79676 + 0xbfe36058b10659f3, 0x3fe9777ef4c7d742, // -0.60551, 0.79584 + 0xbfe36a576582831b, 0x3fe96fe111ddfce0, // -0.60673, 0.79491 + 0xbfe374531b817f8d, 0x3fe9683f42bd7fe1, // -0.60795, 0.79398 + 0xbfe37e4bd1792fe2, 0x3fe960998893ad8c, // -0.60917, 0.79304 + 0xbfe3884185dfeb22, 0x3fe958efe48e6dd7, // -0.61038, 0.79211 + 0xbfe39234372c7f04, 0x3fe9514257dc4335, // -0.6116, 0.79117 + 0xbfe39c23e3d63029, 0x3fe94990e3ac4a6c, // -0.61281, 0.79023 + 0xbfe3a6108a54ba58, 0x3fe941db892e3a65, // -0.61402, 0.78929 + 0xbfe3affa292050b9, 0x3fe93a22499263fc, // -0.61523, 0.78835 + 0xbfe3b9e0beb19e18, 0x3fe932652609b1cf, // -0.61644, 0.7874 + 0xbfe3c3c44981c517, 0x3fe92aa41fc5a815, // -0.61765, 0.78646 + 0xbfe3cda4c80a6076, 0x3fe922df37f8646a, // -0.61885, 0.78551 + 0xbfe3d78238c58343, 0x3fe91b166fd49da2, // -0.62006, 0.78456 + 0xbfe3e15c9a2db922, 0x3fe91349c88da398, // -0.62126, 0.7836 + 0xbfe3eb33eabe0680, 0x3fe90b7943575efe, // -0.62246, 0.78265 + 0xbfe3f50828f1e8d2, 0x3fe903a4e1665133, // -0.62366, 0.78169 + 0xbfe3fed9534556d4, 0x3fe8fbcca3ef940d, // -0.62486, 0.78074 + 0xbfe408a76834c0c0, 0x3fe8f3f08c28d9ac, // -0.62606, 0.77978 + 0xbfe41272663d108c, 0x3fe8ec109b486c49, // -0.62725, 0.77882 + 0xbfe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // -0.62845, 0.77785 + 0xbfe425ff178e6bb1, 0x3fe8dc45331698cc, // -0.62964, 0.77689 + 0xbfe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // -0.63083, 0.77592 + 0xbfe4397f5b2a4380, 0x3fe8cc6a75184655, // -0.63202, 0.77495 + 0xbfe4433ad0117b1d, 0x3fe8c47758fa71cb, // -0.63321, 0.77398 + 0xbfe44cf325091dd6, 0x3fe8bc806b151741, // -0.63439, 0.77301 + 0xbfe456a858917046, 0x3fe8b485aca2a468, // -0.63558, 0.77204 + 0xbfe4605a692b32a2, 0x3fe8ac871ede1d88, // -0.63676, 0.77106 + 0xbfe46a095557a0f1, 0x3fe8a484c3031d50, // -0.63794, 0.77008 + 0xbfe473b51b987347, 0x3fe89c7e9a4dd4ab, // -0.63912, 0.7691 + 0xbfe47d5dba6fde01, 0x3fe89474a5fb0a84, // -0.6403, 0.76812 + 0xbfe48703306091fe, 0x3fe88c66e7481ba1, // -0.64148, 0.76714 + 0xbfe490a57bedbcdf, 0x3fe884555f72fa6b, // -0.64266, 0.76615 + 0xbfe49a449b9b0938, 0x3fe87c400fba2ebf, // -0.64383, 0.76517 + 0xbfe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // -0.645, 0.76418 + 0xbfe4ad79516722f0, 0x3fe86c0a1d9aa195, // -0.64618, 0.76319 + 0xbfe4b70ee48fb869, 0x3fe863e97db3d95a, // -0.64735, 0.7622 + 0xbfe4c0a145ec0004, 0x3fe85bc51ae958cc, // -0.64851, 0.7612 + 0xbfe4ca30740218a3, 0x3fe8539cf67c9029, // -0.64968, 0.76021 + 0xbfe4d3bc6d589f80, 0x3fe84b7111af83f9, // -0.65085, 0.75921 + 0xbfe4dd453076b064, 0x3fe843416dc4cce2, // -0.65201, 0.75821 + 0xbfe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // -0.65317, 0.75721 + 0xbfe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // -0.65433, 0.75621 + 0xbfe4f9cc25cca486, 0x3fe82a9c13f545ff, // -0.65549, 0.7552 + 0xbfe503480159ded2, 0x3fe8225d803964e5, // -0.65665, 0.75419 + 0xbfe50cc09f59a09b, 0x3fe81a1b33b57acc, // -0.65781, 0.75319 + 0xbfe51635fe5601d7, 0x3fe811d52faf94dc, // -0.65896, 0.75218 + 0xbfe51fa81cd99aa6, 0x3fe8098b756e52fa, // -0.66011, 0.75117 + 0xbfe52916f96f8388, 0x3fe8013e0638e795, // -0.66127, 0.75015 + 0xbfe5328292a35596, 0x3fe7f8ece3571771, // -0.66242, 0.74914 + 0xbfe53beae7012abe, 0x3fe7f0980e113978, // -0.66356, 0.74812 + 0xbfe5454ff5159dfb, 0x3fe7e83f87b03686, // -0.66471, 0.7471 + 0xbfe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // -0.66586, 0.74608 + 0xbfe5581038975137, 0x3fe7d7836cc33db2, // -0.667, 0.74506 + 0xbfe5616b6b204e6e, 0x3fe7cf1fdacbf179, // -0.66814, 0.74403 + 0xbfe56ac35197649e, 0x3fe7c6b89ce2d333, // -0.66928, 0.74301 + 0xbfe57417ea8bb75c, 0x3fe7be4db453a27c, // -0.67042, 0.74198 + 0xbfe57d69348cec9f, 0x3fe7b5df226aafb0, // -0.67156, 0.74095 + 0xbfe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // -0.67269, 0.73992 + 0xbfe59001d5f723df, 0x3fe7a4f707bf97d2, // -0.67383, 0.73889 + 0xbfe599492a81ffbc, 0x3fe79c7d8198e56e, // -0.67496, 0.73785 + 0xbfe5a28d2a5d7250, 0x3fe79400574f55e4, // -0.67609, 0.73682 + 0xbfe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // -0.67722, 0.73578 + 0xbfe5b50b264f7448, 0x3fe782fb1b90b35b, // -0.67835, 0.73474 + 0xbfe5be451f8bf980, 0x3fe77a730cbb9100, // -0.67948, 0.7337 + 0xbfe5c77bbe65018c, 0x3fe771e75f037261, // -0.6806, 0.73265 + 0xbfe5d0af016ed1d4, 0x3fe7695813b9b594, // -0.68172, 0.73161 + 0xbfe5d9dee73e345c, 0x3fe760c52c304764, // -0.68285, 0.73056 + 0xbfe5e30b6e6877f3, 0x3fe7582ea9b9a329, // -0.68397, 0.72951 + 0xbfe5ec3495837074, 0x3fe74f948da8d28d, // -0.68508, 0.72846 + 0xbfe5f55a5b2576f8, 0x3fe746f6d9516d59, // -0.6862, 0.72741 + 0xbfe5fe7cbde56a0f, 0x3fe73e558e079942, // -0.68732, 0.72636 + 0xbfe6079bbc5aadfa, 0x3fe735b0ad2009b2, // -0.68843, 0.7253 + 0xbfe610b7551d2cde, 0x3fe72d0837efff97, // -0.68954, 0.72425 + 0xbfe619cf86c55702, 0x3fe7245c2fcd492a, // -0.69065, 0.72319 + 0xbfe622e44fec22ff, 0x3fe71bac960e41bf, // -0.69176, 0.72213 + 0xbfe62bf5af2b0dfd, 0x3fe712f96c09d18d, // -0.69287, 0.72107 + 0xbfe63503a31c1be8, 0x3fe70a42b3176d7a, // -0.69397, 0.72 + 0xbfe63e0e2a59d7aa, 0x3fe701886c8f16e6, // -0.69508, 0.71894 + 0xbfe64715437f535b, 0x3fe6f8ca99c95b75, // -0.69618, 0.71787 + 0xbfe65018ed28287f, 0x3fe6f0093c1f54de, // -0.69728, 0.7168 + 0xbfe6591925f0783e, 0x3fe6e74454eaa8ae, // -0.69838, 0.71573 + 0xbfe66215ec74eb91, 0x3fe6de7be585881d, // -0.69947, 0.71466 + 0xbfe66b0f3f52b386, 0x3fe6d5afef4aafcc, // -0.70057, 0.71358 + 0xbfe674051d27896c, 0x3fe6cce07395679f, // -0.70166, 0.71251 + 0xbfe67cf78491af10, 0x3fe6c40d73c18275, // -0.70275, 0.71143 + 0xbfe685e6742feeef, 0x3fe6bb36f12b5e06, // -0.70385, 0.71035 + 0xbfe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // -0.70493, 0.70927 + 0xbfe697b9e686941c, 0x3fe6a97f692c82ea, // -0.70602, 0.70819 + 0xbfe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // -0.70711, 0.70711 + 0xbfe6a97f692c82ea, 0x3fe697b9e686941c, // -0.70819, 0.70602 + 0xbfe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // -0.70927, 0.70493 + 0xbfe6bb36f12b5e06, 0x3fe685e6742feeef, // -0.71035, 0.70385 + 0xbfe6c40d73c18275, 0x3fe67cf78491af10, // -0.71143, 0.70275 + 0xbfe6cce07395679f, 0x3fe674051d27896c, // -0.71251, 0.70166 + 0xbfe6d5afef4aafcc, 0x3fe66b0f3f52b386, // -0.71358, 0.70057 + 0xbfe6de7be585881d, 0x3fe66215ec74eb91, // -0.71466, 0.69947 + 0xbfe6e74454eaa8ae, 0x3fe6591925f0783e, // -0.71573, 0.69838 + 0xbfe6f0093c1f54de, 0x3fe65018ed28287f, // -0.7168, 0.69728 + 0xbfe6f8ca99c95b75, 0x3fe64715437f535b, // -0.71787, 0.69618 + 0xbfe701886c8f16e6, 0x3fe63e0e2a59d7aa, // -0.71894, 0.69508 + 0xbfe70a42b3176d7a, 0x3fe63503a31c1be8, // -0.72, 0.69397 + 0xbfe712f96c09d18d, 0x3fe62bf5af2b0dfd, // -0.72107, 0.69287 + 0xbfe71bac960e41bf, 0x3fe622e44fec22ff, // -0.72213, 0.69176 + 0xbfe7245c2fcd492a, 0x3fe619cf86c55702, // -0.72319, 0.69065 + 0xbfe72d0837efff97, 0x3fe610b7551d2cde, // -0.72425, 0.68954 + 0xbfe735b0ad2009b2, 0x3fe6079bbc5aadfa, // -0.7253, 0.68843 + 0xbfe73e558e079942, 0x3fe5fe7cbde56a0f, // -0.72636, 0.68732 + 0xbfe746f6d9516d59, 0x3fe5f55a5b2576f8, // -0.72741, 0.6862 + 0xbfe74f948da8d28d, 0x3fe5ec3495837074, // -0.72846, 0.68508 + 0xbfe7582ea9b9a329, 0x3fe5e30b6e6877f3, // -0.72951, 0.68397 + 0xbfe760c52c304764, 0x3fe5d9dee73e345c, // -0.73056, 0.68285 + 0xbfe7695813b9b594, 0x3fe5d0af016ed1d4, // -0.73161, 0.68172 + 0xbfe771e75f037261, 0x3fe5c77bbe65018c, // -0.73265, 0.6806 + 0xbfe77a730cbb9100, 0x3fe5be451f8bf980, // -0.7337, 0.67948 + 0xbfe782fb1b90b35b, 0x3fe5b50b264f7448, // -0.73474, 0.67835 + 0xbfe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // -0.73578, 0.67722 + 0xbfe79400574f55e4, 0x3fe5a28d2a5d7250, // -0.73682, 0.67609 + 0xbfe79c7d8198e56e, 0x3fe599492a81ffbc, // -0.73785, 0.67496 + 0xbfe7a4f707bf97d2, 0x3fe59001d5f723df, // -0.73889, 0.67383 + 0xbfe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // -0.73992, 0.67269 + 0xbfe7b5df226aafb0, 0x3fe57d69348cec9f, // -0.74095, 0.67156 + 0xbfe7be4db453a27c, 0x3fe57417ea8bb75c, // -0.74198, 0.67042 + 0xbfe7c6b89ce2d333, 0x3fe56ac35197649e, // -0.74301, 0.66928 + 0xbfe7cf1fdacbf179, 0x3fe5616b6b204e6e, // -0.74403, 0.66814 + 0xbfe7d7836cc33db2, 0x3fe5581038975137, // -0.74506, 0.667 + 0xbfe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // -0.74608, 0.66586 + 0xbfe7e83f87b03686, 0x3fe5454ff5159dfb, // -0.7471, 0.66471 + 0xbfe7f0980e113978, 0x3fe53beae7012abe, // -0.74812, 0.66356 + 0xbfe7f8ece3571771, 0x3fe5328292a35596, // -0.74914, 0.66242 + 0xbfe8013e0638e795, 0x3fe52916f96f8388, // -0.75015, 0.66127 + 0xbfe8098b756e52fa, 0x3fe51fa81cd99aa6, // -0.75117, 0.66011 + 0xbfe811d52faf94dc, 0x3fe51635fe5601d7, // -0.75218, 0.65896 + 0xbfe81a1b33b57acc, 0x3fe50cc09f59a09b, // -0.75319, 0.65781 + 0xbfe8225d803964e5, 0x3fe503480159ded2, // -0.75419, 0.65665 + 0xbfe82a9c13f545ff, 0x3fe4f9cc25cca486, // -0.7552, 0.65549 + 0xbfe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // -0.75621, 0.65433 + 0xbfe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // -0.75721, 0.65317 + 0xbfe843416dc4cce2, 0x3fe4dd453076b064, // -0.75821, 0.65201 + 0xbfe84b7111af83f9, 0x3fe4d3bc6d589f80, // -0.75921, 0.65085 + 0xbfe8539cf67c9029, 0x3fe4ca30740218a3, // -0.76021, 0.64968 + 0xbfe85bc51ae958cc, 0x3fe4c0a145ec0004, // -0.7612, 0.64851 + 0xbfe863e97db3d95a, 0x3fe4b70ee48fb869, // -0.7622, 0.64735 + 0xbfe86c0a1d9aa195, 0x3fe4ad79516722f0, // -0.76319, 0.64618 + 0xbfe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // -0.76418, 0.645 + 0xbfe87c400fba2ebf, 0x3fe49a449b9b0938, // -0.76517, 0.64383 + 0xbfe884555f72fa6b, 0x3fe490a57bedbcdf, // -0.76615, 0.64266 + 0xbfe88c66e7481ba1, 0x3fe48703306091fe, // -0.76714, 0.64148 + 0xbfe89474a5fb0a84, 0x3fe47d5dba6fde01, // -0.76812, 0.6403 + 0xbfe89c7e9a4dd4ab, 0x3fe473b51b987347, // -0.7691, 0.63912 + 0xbfe8a484c3031d50, 0x3fe46a095557a0f1, // -0.77008, 0.63794 + 0xbfe8ac871ede1d88, 0x3fe4605a692b32a2, // -0.77106, 0.63676 + 0xbfe8b485aca2a468, 0x3fe456a858917046, // -0.77204, 0.63558 + 0xbfe8bc806b151741, 0x3fe44cf325091dd6, // -0.77301, 0.63439 + 0xbfe8c47758fa71cb, 0x3fe4433ad0117b1d, // -0.77398, 0.63321 + 0xbfe8cc6a75184655, 0x3fe4397f5b2a4380, // -0.77495, 0.63202 + 0xbfe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // -0.77592, 0.63083 + 0xbfe8dc45331698cc, 0x3fe425ff178e6bb1, // -0.77689, 0.62964 + 0xbfe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // -0.77785, 0.62845 + 0xbfe8ec109b486c49, 0x3fe41272663d108c, // -0.77882, 0.62725 + 0xbfe8f3f08c28d9ac, 0x3fe408a76834c0c0, // -0.77978, 0.62606 + 0xbfe8fbcca3ef940d, 0x3fe3fed9534556d4, // -0.78074, 0.62486 + 0xbfe903a4e1665133, 0x3fe3f50828f1e8d2, // -0.78169, 0.62366 + 0xbfe90b7943575efe, 0x3fe3eb33eabe0680, // -0.78265, 0.62246 + 0xbfe91349c88da398, 0x3fe3e15c9a2db922, // -0.7836, 0.62126 + 0xbfe91b166fd49da2, 0x3fe3d78238c58343, // -0.78456, 0.62006 + 0xbfe922df37f8646a, 0x3fe3cda4c80a6076, // -0.78551, 0.61885 + 0xbfe92aa41fc5a815, 0x3fe3c3c44981c517, // -0.78646, 0.61765 + 0xbfe932652609b1cf, 0x3fe3b9e0beb19e18, // -0.7874, 0.61644 + 0xbfe93a22499263fc, 0x3fe3affa292050b9, // -0.78835, 0.61523 + 0xbfe941db892e3a65, 0x3fe3a6108a54ba58, // -0.78929, 0.61402 + 0xbfe94990e3ac4a6c, 0x3fe39c23e3d63029, // -0.79023, 0.61281 + 0xbfe9514257dc4335, 0x3fe39234372c7f04, // -0.79117, 0.6116 + 0xbfe958efe48e6dd7, 0x3fe3884185dfeb22, // -0.79211, 0.61038 + 0xbfe960998893ad8c, 0x3fe37e4bd1792fe2, // -0.79304, 0.60917 + 0xbfe9683f42bd7fe1, 0x3fe374531b817f8d, // -0.79398, 0.60795 + 0xbfe96fe111ddfce0, 0x3fe36a576582831b, // -0.79491, 0.60673 + 0xbfe9777ef4c7d742, 0x3fe36058b10659f3, // -0.79584, 0.60551 + 0xbfe97f18ea4e5c9e, 0x3fe35656ff9799ae, // -0.79676, 0.60429 + 0xbfe986aef1457594, 0x3fe34c5252c14de1, // -0.79769, 0.60307 + 0xbfe98e410881a600, 0x3fe3424aac0ef7d6, // -0.79861, 0.60184 + 0xbfe995cf2ed80d22, 0x3fe338400d0c8e57, // -0.79954, 0.60062 + 0xbfe99d59631e65d5, 0x3fe32e3277467d6b, // -0.80046, 0.59939 + 0xbfe9a4dfa42b06b2, 0x3fe32421ec49a620, // -0.80138, 0.59816 + 0xbfe9ac61f0d4e247, 0x3fe31a0e6da35e44, // -0.80229, 0.59693 + 0xbfe9b3e047f38741, 0x3fe30ff7fce17035, // -0.80321, 0.5957 + 0xbfe9bb5aa85f2098, 0x3fe305de9b921a94, // -0.80412, 0.59447 + 0xbfe9c2d110f075c3, 0x3fe2fbc24b441015, // -0.80503, 0.59323 + 0xbfe9ca438080eadb, 0x3fe2f1a30d86773a, // -0.80594, 0.592 + 0xbfe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // -0.80685, 0.59076 + 0xbfe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // -0.80775, 0.58952 + 0xbfe9e082edb42472, 0x3fe2d333d34e9bb7, // -0.80866, 0.58828 + 0xbfe9e7e56dcb45bd, 0x3fe2c908ef734e57, // -0.80956, 0.58704 + 0xbfe9ef43ef29af94, 0x3fe2bedb25faf3ea, // -0.81046, 0.5858 + 0xbfe9f69e70ac75bc, 0x3fe2b4aa787764c4, // -0.81135, 0.58455 + 0xbfe9fdf4f13149de, 0x3fe2aa76e87aeb58, // -0.81225, 0.58331 + 0xbfea05476f967bb5, 0x3fe2a040779843fb, // -0.81314, 0.58206 + 0xbfea0c95eabaf937, 0x3fe2960727629ca8, // -0.81404, 0.58081 + 0xbfea13e0617e4ec7, 0x3fe28bcaf96d94ba, // -0.81493, 0.57956 + 0xbfea1b26d2c0a75e, 0x3fe2818bef4d3cba, // -0.81581, 0.57831 + 0xbfea22693d62ccb9, 0x3fe2774a0a961612, // -0.8167, 0.57706 + 0xbfea29a7a0462782, 0x3fe26d054cdd12df, // -0.81758, 0.57581 + 0xbfea30e1fa4cbf81, 0x3fe262bdb7b795a2, // -0.81847, 0.57455 + 0xbfea38184a593bc6, 0x3fe258734cbb7110, // -0.81935, 0.5733 + 0xbfea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // -0.82023, 0.57204 + 0xbfea4678c8119ac8, 0x3fe243d5fb98ac1f, // -0.8211, 0.57078 + 0xbfea4da2f385e997, 0x3fe23983189fdfd5, // -0.82198, 0.56952 + 0xbfea54c91090f524, 0x3fe22f2d662c13e1, // -0.82285, 0.56826 + 0xbfea5beb1e188375, 0x3fe224d4e5d5482e, // -0.82372, 0.567 + 0xbfea63091b02fae2, 0x3fe21a799933eb58, // -0.82459, 0.56573 + 0xbfea6a230637623b, 0x3fe2101b81e0da78, // -0.82546, 0.56447 + 0xbfea7138de9d60f5, 0x3fe205baa17560d6, // -0.82632, 0.5632 + 0xbfea784aa31d3f55, 0x3fe1fb56f98b37b8, // -0.82718, 0.56193 + 0xbfea7f58529fe69d, 0x3fe1f0f08bbc861b, // -0.82805, 0.56066 + 0xbfea8661ec0ee133, 0x3fe1e68759a3e074, // -0.8289, 0.55939 + 0xbfea8d676e545ad2, 0x3fe1dc1b64dc4872, // -0.82976, 0.55812 + 0xbfea9468d85b20ae, 0x3fe1d1acaf012cc2, // -0.83062, 0.55685 + 0xbfea9b66290ea1a3, 0x3fe1c73b39ae68c8, // -0.83147, 0.55557 + 0xbfeaa25f5f5aee60, 0x3fe1bcc706804467, // -0.83232, 0.55429 + 0xbfeaa9547a2cb98e, 0x3fe1b250171373be, // -0.83317, 0.55302 + 0xbfeab045787157ff, 0x3fe1a7d66d0516e6, // -0.83402, 0.55174 + 0xbfeab7325916c0d4, 0x3fe19d5a09f2b9b8, // -0.83486, 0.55046 + 0xbfeabe1b1b0b8dac, 0x3fe192daef7a5386, // -0.83571, 0.54918 + 0xbfeac4ffbd3efac8, 0x3fe188591f3a46e5, // -0.83655, 0.54789 + 0xbfeacbe03ea0e73b, 0x3fe17dd49ad16161, // -0.83739, 0.54661 + 0xbfead2bc9e21d511, 0x3fe1734d63dedb49, // -0.83822, 0.54532 + 0xbfead994dab2e979, 0x3fe168c37c025764, // -0.83906, 0.54404 + 0xbfeae068f345ecef, 0x3fe15e36e4dbe2bc, // -0.83989, 0.54275 + 0xbfeae738e6cd4b67, 0x3fe153a7a00bf453, // -0.84073, 0.54146 + 0xbfeaee04b43c1474, 0x3fe14915af336ceb, // -0.84155, 0.54017 + 0xbfeaf4cc5a85fb73, 0x3fe13e8113f396c1, // -0.84238, 0.53888 + 0xbfeafb8fd89f57b6, 0x3fe133e9cfee254e, // -0.84321, 0.53759 + 0xbfeb024f2d7d24a9, 0x3fe1294fe4c5350a, // -0.84403, 0.53629 + 0xbfeb090a58150200, 0x3fe11eb3541b4b22, // -0.84485, 0.535 + 0xbfeb0fc1575d33db, 0x3fe114141f935545, // -0.84567, 0.5337 + 0xbfeb16742a4ca2f5, 0x3fe1097248d0a956, // -0.84649, 0.5324 + 0xbfeb1d22cfdadcc6, 0x3fe0fecdd1770537, // -0.84731, 0.5311 + 0xbfeb23cd470013b4, 0x3fe0f426bb2a8e7d, // -0.84812, 0.5298 + 0xbfeb2a738eb51f33, 0x3fe0e97d078fd23b, // -0.84893, 0.5285 + 0xbfeb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // -0.84974, 0.5272 + 0xbfeb37b38bb54c09, 0x3fe0d421cf03c12b, // -0.85055, 0.5259 + 0xbfeb3e4d3ef55712, 0x3fe0c9704d5d898f, // -0.85136, 0.52459 + 0xbfeb44e2beaf0a61, 0x3fe0bebc34ff4646, // -0.85216, 0.52328 + 0xbfeb4b7409de7925, 0x3fe0b405878f85ec, // -0.85296, 0.52198 + 0xbfeb52011f805c92, 0x3fe0a94c46b53d0b, // -0.85376, 0.52067 + 0xbfeb5889fe921405, 0x3fe09e907417c5e1, // -0.85456, 0.51936 + 0xbfeb5f0ea611a532, 0x3fe093d2115ee018, // -0.85535, 0.51804 + 0xbfeb658f14fdbc47, 0x3fe089112032b08c, // -0.85615, 0.51673 + 0xbfeb6c0b4a55ac17, 0x3fe07e4da23bc102, // -0.85694, 0.51542 + 0xbfeb728345196e3e, 0x3fe073879922ffed, // -0.85773, 0.5141 + 0xbfeb78f70449a34b, 0x3fe068bf0691c028, // -0.85852, 0.51279 + 0xbfeb7f6686e792ea, 0x3fe05df3ec31b8b6, // -0.8593, 0.51147 + 0xbfeb85d1cbf52c02, 0x3fe053264bad0483, // -0.86009, 0.51015 + 0xbfeb8c38d27504e9, 0x3fe0485626ae221a, // -0.86087, 0.50883 + 0xbfeb929b996a5b7f, 0x3fe03d837edff370, // -0.86165, 0.50751 + 0xbfeb98fa1fd9155e, 0x3fe032ae55edbd95, // -0.86242, 0.50619 + 0xbfeb9f5464c5bffc, 0x3fe027d6ad83287e, // -0.8632, 0.50486 + 0xbfeba5aa673590d2, 0x3fe01cfc874c3eb7, // -0.86397, 0.50354 + 0xbfebabfc262e6586, 0x3fe0121fe4f56d2c, // -0.86474, 0.50221 + 0xbfebb249a0b6c40d, 0x3fe00740c82b82e0, // -0.86551, 0.50089 + 0xbfebb892d5d5dad5, 0x3fdff8be6537615e, // -0.86628, 0.49956 + 0xbfebbed7c49380ea, 0x3fdfe2f64be7120f, // -0.86705, 0.49823 + 0xbfebc5186bf8361d, 0x3fdfcd2947c1ff57, // -0.86781, 0.4969 + 0xbfebcb54cb0d2327, 0x3fdfb7575c24d2de, // -0.86857, 0.49557 + 0xbfebd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // -0.86933, 0.49423 + 0xbfebd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // -0.87009, 0.4929 + 0xbfebddf02cd2b983, 0x3fdf75c44e26a852, // -0.87084, 0.49156 + 0xbfebe41b611154c1, 0x3fdf5fdee656cda3, // -0.8716, 0.49023 + 0xbfebea424837de6d, 0x3fdf49f4a7e97729, // -0.87235, 0.48889 + 0xbfebf064e15377dd, 0x3fdf3405963fd068, // -0.87309, 0.48755 + 0xbfebf6832b71ec5b, 0x3fdf1e11b4bbc35c, // -0.87384, 0.48621 + 0xbfebfc9d25a1b147, 0x3fdf081906bff7fd, // -0.87459, 0.48487 + 0xbfec02b2cef1e641, 0x3fdef21b8fafd3b5, // -0.87533, 0.48353 + 0xbfec08c426725549, 0x3fdedc1952ef78d5, // -0.87607, 0.48218 + 0xbfec0ed12b3372e9, 0x3fdec61253e3c61b, // -0.87681, 0.48084 + 0xbfec14d9dc465e58, 0x3fdeb00695f25620, // -0.87755, 0.47949 + 0xbfec1ade38bce19b, 0x3fde99f61c817eda, // -0.87828, 0.47815 + 0xbfec20de3fa971b0, 0x3fde83e0eaf85113, // -0.87901, 0.4768 + 0xbfec26d9f01f2eaf, 0x3fde6dc704be97e2, // -0.87974, 0.47545 + 0xbfec2cd14931e3f1, 0x3fde57a86d3cd824, // -0.88047, 0.4741 + 0xbfec32c449f60831, 0x3fde418527dc4ffa, // -0.8812, 0.47275 + 0xbfec38b2f180bdb1, 0x3fde2b5d3806f63b, // -0.88192, 0.4714 + 0xbfec3e9d3ee7d262, 0x3fde1530a12779f4, // -0.88264, 0.47004 + 0xbfec44833141c004, 0x3fddfeff66a941de, // -0.88336, 0.46869 + 0xbfec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // -0.88408, 0.46733 + 0xbfec5042012b6907, 0x3fddd28f1481cc58, // -0.8848, 0.46598 + 0xbfec561adceb743e, 0x3fddbc5003b2edf8, // -0.88551, 0.46462 + 0xbfec5bef59fef85a, 0x3fdda60c5cfa10d8, // -0.88622, 0.46326 + 0xbfec61bf777fcc48, 0x3fdd8fc423c62a25, // -0.88693, 0.4619 + 0xbfec678b3488739b, 0x3fdd79775b86e389, // -0.88764, 0.46054 + 0xbfec6d5290341eb2, 0x3fdd632607ac9aa9, // -0.88835, 0.45918 + 0xbfec7315899eaad7, 0x3fdd4cd02ba8609c, // -0.88905, 0.45781 + 0xbfec78d41fe4a267, 0x3fdd3675caebf962, // -0.88975, 0.45645 + 0xbfec7e8e52233cf3, 0x3fdd2016e8e9db5b, // -0.89045, 0.45508 + 0xbfec84441f785f61, 0x3fdd09b389152ec1, // -0.89115, 0.45372 + 0xbfec89f587029c13, 0x3fdcf34baee1cd21, // -0.89184, 0.45235 + 0xbfec8fa287e13305, 0x3fdcdcdf5dc440ce, // -0.89253, 0.45098 + 0xbfec954b213411f5, 0x3fdcc66e9931c45d, // -0.89322, 0.44961 + 0xbfec9aef521bd480, 0x3fdcaff964a0421d, // -0.89391, 0.44824 + 0xbfeca08f19b9c449, 0x3fdc997fc3865388, // -0.8946, 0.44687 + 0xbfeca62a772fd919, 0x3fdc8301b95b40c2, // -0.89528, 0.4455 + 0xbfecabc169a0b901, 0x3fdc6c7f4997000a, // -0.89597, 0.44412 + 0xbfecb153f02fb87d, 0x3fdc55f877b23537, // -0.89665, 0.44275 + 0xbfecb6e20a00da99, 0x3fdc3f6d47263129, // -0.89732, 0.44137 + 0xbfecbc6bb638d10b, 0x3fdc28ddbb6cf145, // -0.898, 0.43999 + 0xbfecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // -0.89867, 0.43862 + 0xbfecc771c2736c09, 0x3fdbfbb1a05e0edc, // -0.89935, 0.43724 + 0xbfecccee20c2de9f, 0x3fdbe51517ffc0d9, // -0.90002, 0.43586 + 0xbfecd2660e12c1e6, 0x3fdbce744262deee, // -0.90068, 0.43448 + 0xbfecd7d9898b32f6, 0x3fdbb7cf2304bd01, // -0.90135, 0.43309 + 0xbfecdd489254fe65, 0x3fdba125bd63583e, // -0.90201, 0.43171 + 0xbfece2b32799a060, 0x3fdb8a7814fd5693, // -0.90267, 0.43033 + 0xbfece819488344ce, 0x3fdb73c62d520624, // -0.90333, 0.42894 + 0xbfeced7af43cc773, 0x3fdb5d1009e15cc0, // -0.90399, 0.42756 + 0xbfecf2d829f1b40e, 0x3fdb4655ae2bf757, // -0.90464, 0.42617 + 0xbfecf830e8ce467b, 0x3fdb2f971db31972, // -0.9053, 0.42478 + 0xbfecfd852fff6ad4, 0x3fdb18d45bf8aca6, // -0.90595, 0.42339 + 0xbfed02d4feb2bd92, 0x3fdb020d6c7f4009, // -0.9066, 0.422 + 0xbfed082054168bac, 0x3fdaeb4252ca07ab, // -0.90724, 0.42061 + 0xbfed0d672f59d2b9, 0x3fdad473125cdc08, // -0.90789, 0.41922 + 0xbfed12a98fac410c, 0x3fdabd9faebc3980, // -0.90853, 0.41782 + 0xbfed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // -0.90917, 0.41643 + 0xbfed1d20dc40c15c, 0x3fda8fec8bf5b166, // -0.90981, 0.41503 + 0xbfed2255c6e5a4e1, 0x3fda790cd3dbf31a, // -0.91044, 0.41364 + 0xbfed2786335f52fc, 0x3fda622906a70b63, // -0.91107, 0.41224 + 0xbfed2cb220e0ef9f, 0x3fda4b4127dea1e4, // -0.91171, 0.41084 + 0xbfed31d98e9e503a, 0x3fda34553b0afee5, // -0.91234, 0.40944 + 0xbfed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // -0.91296, 0.40804 + 0xbfed3c1ae79f2b4e, 0x3fda067145664d57, // -0.91359, 0.40664 + 0xbfed4134d14dc93a, 0x3fd9ef7943a8ed8a, // -0.91421, 0.40524 + 0xbfed464a380e7242, 0x3fd9d87d4207b0ab, // -0.91483, 0.40384 + 0xbfed4b5b1b187524, 0x3fd9c17d440df9f2, // -0.91545, 0.40243 + 0xbfed506779a3d2d9, 0x3fd9aa794d47c9ee, // -0.91606, 0.40103 + 0xbfed556f52e93eb1, 0x3fd993716141bdfe, // -0.91668, 0.39962 + 0xbfed5a72a6221e73, 0x3fd97c6583890fc2, // -0.91729, 0.39822 + 0xbfed5f7172888a7f, 0x3fd96555b7ab948f, // -0.9179, 0.39681 + 0xbfed646bb7574de5, 0x3fd94e420137bce3, // -0.91851, 0.3954 + 0xbfed696173c9e68b, 0x3fd9372a63bc93d7, // -0.91911, 0.39399 + 0xbfed6e52a71c8547, 0x3fd9200ee2c9be97, // -0.91972, 0.39258 + 0xbfed733f508c0dff, 0x3fd908ef81ef7bd1, // -0.92032, 0.39117 + 0xbfed78276f5617c6, 0x3fd8f1cc44bea329, // -0.92092, 0.38976 + 0xbfed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // -0.92151, 0.38835 + 0xbfed81ea09f38b63, 0x3fd8c37a439f884f, // -0.92211, 0.38693 + 0xbfed86c48445a450, 0x3fd8ac4b86d5ed44, // -0.9227, 0.38552 + 0xbfed8b9a70ef9cb4, 0x3fd89518fbff098e, // -0.92329, 0.3841 + 0xbfed906bcf328d46, 0x3fd87de2a6aea963, // -0.92388, 0.38268 + 0xbfed95389e50429b, 0x3fd866a88a792ea0, // -0.92447, 0.38127 + 0xbfed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // -0.92505, 0.37985 + 0xbfed9ec48c26b1f3, 0x3fd838290bb359c8, // -0.92563, 0.37843 + 0xbfeda383a9668988, 0x3fd820e3b04eaac4, // -0.92621, 0.37701 + 0xbfeda83e348f613b, 0x3fd8099a9c5c362d, // -0.92679, 0.37559 + 0xbfedacf42ce68ab9, 0x3fd7f24dd37341e3, // -0.92736, 0.37416 + 0xbfedb1a591b20c38, 0x3fd7dafd592ba621, // -0.92794, 0.37274 + 0xbfedb6526238a09b, 0x3fd7c3a9311dcce7, // -0.92851, 0.37132 + 0xbfedbafa9dc1b78d, 0x3fd7ac515ee2b172, // -0.92907, 0.36989 + 0xbfedbf9e4395759a, 0x3fd794f5e613dfae, // -0.92964, 0.36847 + 0xbfedc43d52fcb453, 0x3fd77d96ca4b73a6, // -0.93021, 0.36704 + 0xbfedc8d7cb410260, 0x3fd766340f2418f6, // -0.93077, 0.36561 + 0xbfedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // -0.93133, 0.36418 + 0xbfedd1fef38a915a, 0x3fd73763c9261092, // -0.93188, 0.36276 + 0xbfedd68ba2267a25, 0x3fd71ff6458782ec, // -0.93244, 0.36133 + 0xbfeddb13b6ccc23d, 0x3fd7088530fa459e, // -0.93299, 0.3599 + 0xbfeddf9730ca837b, 0x3fd6f1108f1bc9c5, // -0.93354, 0.35846 + 0xbfede4160f6d8d81, 0x3fd6d998638a0cb5, // -0.93409, 0.35703 + 0xbfede890520465ce, 0x3fd6c21cb1e39771, // -0.93464, 0.3556 + 0xbfeded05f7de47da, 0x3fd6aa9d7dc77e16, // -0.93518, 0.35416 + 0xbfedf177004b2534, 0x3fd6931acad55f51, // -0.93573, 0.35273 + 0xbfedf5e36a9ba59c, 0x3fd67b949cad63ca, // -0.93627, 0.35129 + 0xbfedfa4b3621271d, 0x3fd6640af6f03d9e, // -0.9368, 0.34986 + 0xbfedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // -0.93734, 0.34842 + 0xbfee030cee1435b8, 0x3fd634ed533be58e, // -0.93787, 0.34698 + 0xbfee0766d9280f54, 0x3fd61d595c88c203, // -0.9384, 0.34554 + 0xbfee0bbc22bd8349, 0x3fd605c1fcc88f63, // -0.93893, 0.3441 + 0xbfee100cca2980ac, 0x3fd5ee27379ea693, // -0.93946, 0.34266 + 0xbfee1458cec1ad83, 0x3fd5d68910aee686, // -0.93998, 0.34122 + 0xbfee18a02fdc66d9, 0x3fd5bee78b9db3b6, // -0.94051, 0.33978 + 0xbfee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // -0.94103, 0.33833 + 0xbfee212104f686e5, 0x3fd58f9a75ab1fdd, // -0.94154, 0.33689 + 0xbfee255a77a63bb8, 0x3fd577eeec151e47, // -0.94206, 0.33545 + 0xbfee298f4439197a, 0x3fd5604012f467b4, // -0.94257, 0.334 + 0xbfee2dbf6a0911d9, 0x3fd5488dedeff3be, // -0.94308, 0.33255 + 0xbfee31eae870ce25, 0x3fd530d880af3c24, // -0.94359, 0.33111 + 0xbfee3611becbaf69, 0x3fd5191fceda3c35, // -0.9441, 0.32966 + 0xbfee3a33ec75ce85, 0x3fd50163dc197047, // -0.9446, 0.32821 + 0xbfee3e5170cbfc46, 0x3fd4e9a4ac15d520, // -0.94511, 0.32676 + 0xbfee426a4b2bc17e, 0x3fd4d1e24278e76a, // -0.94561, 0.32531 + 0xbfee467e7af35f23, 0x3fd4ba1ca2eca31c, // -0.94611, 0.32386 + 0xbfee4a8dff81ce5e, 0x3fd4a253d11b82f3, // -0.9466, 0.32241 + 0xbfee4e98d836c0af, 0x3fd48a87d0b07fd7, // -0.94709, 0.32096 + 0xbfee529f04729ffc, 0x3fd472b8a5571054, // -0.94759, 0.3195 + 0xbfee56a083968eb1, 0x3fd45ae652bb2800, // -0.94807, 0.31805 + 0xbfee5a9d550467d3, 0x3fd44310dc8936f0, // -0.94856, 0.31659 + 0xbfee5e95781ebf1c, 0x3fd42b38466e2928, // -0.94905, 0.31514 + 0xbfee6288ec48e112, 0x3fd4135c94176602, // -0.94953, 0.31368 + 0xbfee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // -0.95001, 0.31222 + 0xbfee6a61c55d53a7, 0x3fd3e39be96ec271, // -0.95049, 0.31077 + 0xbfee6e472911da27, 0x3fd3cbb6f87a146e, // -0.95096, 0.30931 + 0xbfee7227db6a9744, 0x3fd3b3cefa0414b7, // -0.95144, 0.30785 + 0xbfee7603dbce74e9, 0x3fd39be3f1bc8aef, // -0.95191, 0.30639 + 0xbfee79db29a5165a, 0x3fd383f5e353b6aa, // -0.95238, 0.30493 + 0xbfee7dadc456d850, 0x3fd36c04d27a4edf, // -0.95284, 0.30347 + 0xbfee817bab4cd10d, 0x3fd35410c2e18152, // -0.95331, 0.30201 + 0xbfee8544ddf0d075, 0x3fd33c19b83af207, // -0.95377, 0.30054 + 0xbfee89095bad6025, 0x3fd3241fb638baaf, // -0.95423, 0.29908 + 0xbfee8cc923edc388, 0x3fd30c22c08d6a13, // -0.95469, 0.29762 + 0xbfee9084361df7f3, 0x3fd2f422daec0386, // -0.95514, 0.29615 + 0xbfee943a91aab4b4, 0x3fd2dc200907fe51, // -0.95559, 0.29469 + 0xbfee97ec36016b30, 0x3fd2c41a4e954520, // -0.95605, 0.29322 + 0xbfee9b99229046f8, 0x3fd2ac11af483572, // -0.95649, 0.29175 + 0xbfee9f4156c62dda, 0x3fd294062ed59f05, // -0.95694, 0.29028 + 0xbfeea2e4d212c000, 0x3fd27bf7d0f2c346, // -0.95738, 0.28882 + 0xbfeea68393e65800, 0x3fd263e6995554ba, // -0.95783, 0.28735 + 0xbfeeaa1d9bb20af3, 0x3fd24bd28bb37672, // -0.95827, 0.28588 + 0xbfeeadb2e8e7a88e, 0x3fd233bbabc3bb72, // -0.9587, 0.28441 + 0xbfeeb1437af9bb34, 0x3fd21ba1fd3d2623, // -0.95914, 0.28294 + 0xbfeeb4cf515b8811, 0x3fd2038583d727bd, // -0.95957, 0.28146 + 0xbfeeb8566b810f2a, 0x3fd1eb6643499fbb, // -0.96, 0.27999 + 0xbfeebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // -0.96043, 0.27852 + 0xbfeebf5668eaf2ef, 0x3fd1bb1f7b999480, // -0.96086, 0.27705 + 0xbfeec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // -0.96128, 0.27557 + 0xbfeec6436ee60309, 0x3fd18acdc3f4873a, // -0.9617, 0.2741 + 0xbfeec9b2d3c3bf84, 0x3fd172a0d7765177, // -0.96212, 0.27262 + 0xbfeecd1d792c8f10, 0x3fd15a713a28b9d9, // -0.96254, 0.27115 + 0xbfeed0835e999009, 0x3fd1423eefc69378, // -0.96295, 0.26967 + 0xbfeed3e483849c51, 0x3fd12a09fc0b1b12, // -0.96337, 0.26819 + 0xbfeed740e7684963, 0x3fd111d262b1f677, // -0.96378, 0.26671 + 0xbfeeda9889bfe86a, 0x3fd0f998277733f7, // -0.96418, 0.26523 + 0xbfeeddeb6a078651, 0x3fd0e15b4e1749cd, // -0.96459, 0.26375 + 0xbfeee13987bbebdc, 0x3fd0c91bda4f158d, // -0.96499, 0.26227 + 0xbfeee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // -0.96539, 0.26079 + 0xbfeee7c77961dc9e, 0x3fd09895327b465e, // -0.96579, 0.25931 + 0xbfeeeb074c50a544, 0x3fd0804e05eb661e, // -0.96619, 0.25783 + 0xbfeeee425aa6b09a, 0x3fd068044deab002, // -0.96658, 0.25635 + 0xbfeef178a3e473c2, 0x3fd04fb80e37fdae, // -0.96698, 0.25487 + 0xbfeef4aa278b2032, 0x3fd037694a928cac, // -0.96737, 0.25338 + 0xbfeef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // -0.96775, 0.2519 + 0xbfeefafedc1ba8b7, 0x3fd006c4466e54af, // -0.96814, 0.25041 + 0xbfeefe220c0b95ec, 0x3fcfdcdc1adfedf8, // -0.96852, 0.24893 + 0xbfef014074708ed3, 0x3fcfac2abeff57ff, // -0.9689, 0.24744 + 0xbfef045a14cf738c, 0x3fcf7b7480bd3801, // -0.96928, 0.24596 + 0xbfef076eecade0fa, 0x3fcf4ab9679c9f5c, // -0.96966, 0.24447 + 0xbfef0a7efb9230d7, 0x3fcf19f97b215f1a, // -0.97003, 0.24298 + 0xbfef0d8a410379c5, 0x3fcee934c2d006c7, // -0.9704, 0.24149 + 0xbfef1090bc898f5f, 0x3fceb86b462de348, // -0.97077, 0.24 + 0xbfef13926dad024e, 0x3fce879d0cc0fdaf, // -0.97114, 0.23851 + 0xbfef168f53f7205d, 0x3fce56ca1e101a1b, // -0.9715, 0.23702 + 0xbfef19876ef1f486, 0x3fce25f281a2b684, // -0.97187, 0.23553 + 0xbfef1c7abe284708, 0x3fcdf5163f01099a, // -0.97223, 0.23404 + 0xbfef1f6941259d7a, 0x3fcdc4355db40195, // -0.97258, 0.23255 + 0xbfef2252f7763ada, 0x3fcd934fe5454311, // -0.97294, 0.23106 + 0xbfef2537e0a71f9f, 0x3fcd6265dd3f27e3, // -0.97329, 0.22957 + 0xbfef2817fc4609ce, 0x3fcd31774d2cbdee, // -0.97364, 0.22807 + 0xbfef2af349e17507, 0x3fcd00843c99c5f9, // -0.97399, 0.22658 + 0xbfef2dc9c9089a9d, 0x3fcccf8cb312b286, // -0.97434, 0.22508 + 0xbfef309b794b719f, 0x3fcc9e90b824a6a9, // -0.97468, 0.22359 + 0xbfef33685a3aaef0, 0x3fcc6d90535d74dc, // -0.97503, 0.22209 + 0xbfef36306b67c556, 0x3fcc3c8b8c4b9dd7, // -0.97536, 0.2206 + 0xbfef38f3ac64e589, 0x3fcc0b826a7e4f63, // -0.9757, 0.2191 + 0xbfef3bb21cc4fe47, 0x3fcbda74f5856330, // -0.97604, 0.2176 + 0xbfef3e6bbc1bbc65, 0x3fcba96334f15dad, // -0.97637, 0.21611 + 0xbfef412089fd8adc, 0x3fcb784d30536cda, // -0.9767, 0.21461 + 0xbfef43d085ff92dd, 0x3fcb4732ef3d6722, // -0.97703, 0.21311 + 0xbfef467bafb7bbe0, 0x3fcb16147941ca2a, // -0.97735, 0.21161 + 0xbfef492206bcabb4, 0x3fcae4f1d5f3b9ab, // -0.97768, 0.21011 + 0xbfef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // -0.978, 0.20861 + 0xbfef4e603b0b2f2d, 0x3fca82a025b00451, // -0.97832, 0.20711 + 0xbfef50f81785c6b9, 0x3fca517127e3dabc, // -0.97863, 0.20561 + 0xbfef538b1faf2d07, 0x3fca203e1b1831da, // -0.97895, 0.20411 + 0xbfef56195321c090, 0x3fc9ef0706e35a35, // -0.97926, 0.20261 + 0xbfef58a2b1789e84, 0x3fc9bdcbf2dc4366, // -0.97957, 0.2011 + 0xbfef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // -0.97988, 0.1996 + 0xbfef5da6ed43685d, 0x3fc95b49e9b62af9, // -0.98018, 0.1981 + 0xbfef6021c9f148c2, 0x3fc92a0303c8194f, // -0.98048, 0.19659 + 0xbfef6297cff75cb0, 0x3fc8f8b83c69a60a, // -0.98079, 0.19509 + 0xbfef6508fef47bd5, 0x3fc8c7699b34ca7e, // -0.98108, 0.19359 + 0xbfef677556883cee, 0x3fc8961727c41804, // -0.98138, 0.19208 + 0xbfef69dcd652f5de, 0x3fc864c0e9b2b6cf, // -0.98167, 0.19057 + 0xbfef6c3f7df5bbb7, 0x3fc83366e89c64c5, // -0.98196, 0.18907 + 0xbfef6e9d4d1262ca, 0x3fc802092c1d744b, // -0.98225, 0.18756 + 0xbfef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // -0.98254, 0.18606 + 0xbfef734a60446279, 0x3fc79f429f59e11d, // -0.98282, 0.18455 + 0xbfef7599a3a12077, 0x3fc76dd9de50bf31, // -0.98311, 0.18304 + 0xbfef77e40d068a90, 0x3fc73c6d8055fe0a, // -0.98339, 0.18153 + 0xbfef7a299c1a322a, 0x3fc70afd8d08c4ff, // -0.98366, 0.18002 + 0xbfef7c6a50826840, 0x3fc6d98a0c08c8da, // -0.98394, 0.17851 + 0xbfef7ea629e63d6e, 0x3fc6a81304f64ab2, // -0.98421, 0.177 + 0xbfef80dd27ed8204, 0x3fc676987f7216b8, // -0.98448, 0.17549 + 0xbfef830f4a40c60c, 0x3fc6451a831d830d, // -0.98475, 0.17398 + 0xbfef853c9089595e, 0x3fc61399179a6e94, // -0.98501, 0.17247 + 0xbfef8764fa714ba9, 0x3fc5e214448b3fc6, // -0.98528, 0.17096 + 0xbfef898887a36c84, 0x3fc5b08c1192e381, // -0.98554, 0.16945 + 0xbfef8ba737cb4b78, 0x3fc57f008654cbde, // -0.9858, 0.16794 + 0xbfef8dc10a95380d, 0x3fc54d71aa74ef02, // -0.98605, 0.16643 + 0xbfef8fd5ffae41db, 0x3fc51bdf8597c5f2, // -0.98631, 0.16491 + 0xbfef91e616c43891, 0x3fc4ea4a1f624b61, // -0.98656, 0.1634 + 0xbfef93f14f85ac08, 0x3fc4b8b17f79fa88, // -0.98681, 0.16189 + 0xbfef95f7a9a1ec47, 0x3fc48715ad84cdf5, // -0.98706, 0.16037 + 0xbfef97f924c9099b, 0x3fc45576b1293e5a, // -0.9873, 0.15886 + 0xbfef99f5c0abd496, 0x3fc423d4920e4166, // -0.98754, 0.15734 + 0xbfef9bed7cfbde29, 0x3fc3f22f57db4893, // -0.98778, 0.15583 + 0xbfef9de0596b77a3, 0x3fc3c0870a383ff6, // -0.98802, 0.15431 + 0xbfef9fce55adb2c8, 0x3fc38edbb0cd8d14, // -0.98826, 0.1528 + 0xbfefa1b7717661d5, 0x3fc35d2d53440db2, // -0.98849, 0.15128 + 0xbfefa39bac7a1791, 0x3fc32b7bf94516a7, // -0.98872, 0.14976 + 0xbfefa57b066e2754, 0x3fc2f9c7aa7a72af, // -0.98895, 0.14825 + 0xbfefa7557f08a517, 0x3fc2c8106e8e613a, // -0.98918, 0.14673 + 0xbfefa92b1600657c, 0x3fc296564d2b953e, // -0.9894, 0.14521 + 0xbfefaafbcb0cfddc, 0x3fc264994dfd340a, // -0.98962, 0.1437 + 0xbfefacc79de6c44f, 0x3fc232d978aed413, // -0.98984, 0.14218 + 0xbfefae8e8e46cfbb, 0x3fc20116d4ec7bce, // -0.99006, 0.14066 + 0xbfefb0509be6f7db, 0x3fc1cf516a62a077, // -0.99027, 0.13914 + 0xbfefb20dc681d54d, 0x3fc19d8940be24e7, // -0.99049, 0.13762 + 0xbfefb3c60dd2c199, 0x3fc16bbe5fac5865, // -0.9907, 0.1361 + 0xbfefb5797195d741, 0x3fc139f0cedaf576, // -0.9909, 0.13458 + 0xbfefb727f187f1c7, 0x3fc1082095f820b0, // -0.99111, 0.13306 + 0xbfefb8d18d66adb7, 0x3fc0d64dbcb26786, // -0.99131, 0.13154 + 0xbfefba7644f068b5, 0x3fc0a4784ab8bf1d, // -0.99151, 0.13002 + 0xbfefbc1617e44186, 0x3fc072a047ba831d, // -0.99171, 0.1285 + 0xbfefbdb106021816, 0x3fc040c5bb67747e, // -0.99191, 0.12698 + 0xbfefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // -0.9921, 0.12545 + 0xbfefc0d832bf043a, 0x3fbfba124b07ad85, // -0.99229, 0.12393 + 0xbfefc26470e19fd3, 0x3fbf564e56a9730e, // -0.99248, 0.12241 + 0xbfefc3ebc935454c, 0x3fbef2858d27561b, // -0.99267, 0.12089 + 0xbfefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // -0.99285, 0.11937 + 0xbfefc6ebc77f0887, 0x3fbe2ae5b8457f77, // -0.99303, 0.11784 + 0xbfefc8646cfeb721, 0x3fbdc70ecbae9fc8, // -0.99321, 0.11632 + 0xbfefc9d82bc2915e, 0x3fbd633347858ce4, // -0.99339, 0.11479 + 0xbfefcb4703914354, 0x3fbcff533b307dc1, // -0.99356, 0.11327 + 0xbfefccb0f4323aa3, 0x3fbc9b6eb6165c42, // -0.99374, 0.11175 + 0xbfefce15fd6da67b, 0x3fbc3785c79ec2d5, // -0.99391, 0.11022 + 0xbfefcf761f0c77a3, 0x3fbbd3987f31fa0e, // -0.99407, 0.1087 + 0xbfefd0d158d86087, 0x3fbb6fa6ec38f64c, // -0.99424, 0.10717 + 0xbfefd227aa9bd53b, 0x3fbb0bb11e1d5559, // -0.9944, 0.10565 + 0xbfefd37914220b84, 0x3fbaa7b724495c04, // -0.99456, 0.10412 + 0xbfefd4c59536fae4, 0x3fba43b90e27f3c4, // -0.99472, 0.1026 + 0xbfefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // -0.99488, 0.10107 + 0xbfefd74fdd40abbf, 0x3fb97bb0caaba56f, // -0.99503, 0.099544 + 0xbfefd88da3d12526, 0x3fb917a6bc29b42c, // -0.99518, 0.098017 + 0xbfefd9c68127c78c, 0x3fb8b398cf0c38e0, // -0.99533, 0.09649 + 0xbfefdafa7514538c, 0x3fb84f8712c130a0, // -0.99548, 0.094963 + 0xbfefdc297f674ba9, 0x3fb7eb7196b72ee4, // -0.99563, 0.093436 + 0xbfefdd539ff1f456, 0x3fb787586a5d5b21, // -0.99577, 0.091909 + 0xbfefde78d68653fd, 0x3fb7233b9d236e71, // -0.99591, 0.090381 + 0xbfefdf9922f73307, 0x3fb6bf1b3e79b129, // -0.99604, 0.088854 + 0xbfefe0b485181be3, 0x3fb65af75dd0f87b, // -0.99618, 0.087326 + 0xbfefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // -0.99631, 0.085797 + 0xbfefe2dc89bbff08, 0x3fb592a554489bc8, // -0.99644, 0.084269 + 0xbfefe3e92be9d886, 0x3fb52e774a4d4d0a, // -0.99657, 0.08274 + 0xbfefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // -0.9967, 0.081211 + 0xbfefe5f3af2e3940, 0x3fb4661179272096, // -0.99682, 0.079682 + 0xbfefe6f18ff42c84, 0x3fb401d9d0e3a507, // -0.99694, 0.078153 + 0xbfefe7ea85482d60, 0x3fb39d9f12c5a299, // -0.99706, 0.076624 + 0xbfefe8de8f03d75c, 0x3fb339614e41ffa5, // -0.99718, 0.075094 + 0xbfefe9cdad01883a, 0x3fb2d52092ce19f6, // -0.99729, 0.073565 + 0xbfefeab7df1c6005, 0x3fb270dcefdfc45b, // -0.9974, 0.072035 + 0xbfefeb9d2530410f, 0x3fb20c9674ed444c, // -0.99751, 0.070505 + 0xbfefec7d7f19cffc, 0x3fb1a84d316d4f8a, // -0.99762, 0.068974 + 0xbfefed58ecb673c4, 0x3fb1440134d709b2, // -0.99772, 0.067444 + 0xbfefee2f6de455ba, 0x3fb0dfb28ea201e6, // -0.99783, 0.065913 + 0xbfefef0102826191, 0x3fb07b614e463064, // -0.99793, 0.064383 + 0xbfefefcdaa704562, 0x3fb0170d833bf421, // -0.99802, 0.062852 + 0xbfeff095658e71ad, 0x3faf656e79f820e0, // -0.99812, 0.061321 + 0xbfeff15833be1965, 0x3fae9cbd15ff5527, // -0.99821, 0.05979 + 0xbfeff21614e131ed, 0x3fadd406f9808ec8, // -0.9983, 0.058258 + 0xbfeff2cf08da7321, 0x3fad0b4c436f91d0, // -0.99839, 0.056727 + 0xbfeff3830f8d575c, 0x3fac428d12c0d7e3, // -0.99848, 0.055195 + 0xbfeff43228de1b77, 0x3fab79c986698b78, // -0.99856, 0.053664 + 0xbfeff4dc54b1bed3, 0x3faab101bd5f8317, // -0.99864, 0.052132 + 0xbfeff58192ee0358, 0x3fa9e835d6993c87, // -0.99872, 0.0506 + 0xbfeff621e3796d7e, 0x3fa91f65f10dd814, // -0.9988, 0.049068 + 0xbfeff6bd463b444d, 0x3fa856922bb513c1, // -0.99887, 0.047535 + 0xbfeff753bb1b9164, 0x3fa78dbaa5874685, // -0.99894, 0.046003 + 0xbfeff7e5420320f9, 0x3fa6c4df7d7d5b84, // -0.99901, 0.044471 + 0xbfeff871dadb81df, 0x3fa5fc00d290cd43, // -0.99908, 0.042938 + 0xbfeff8f9858f058b, 0x3fa5331ec3bba0eb, // -0.99914, 0.041406 + 0xbfeff97c4208c014, 0x3fa46a396ff86179, // -0.9992, 0.039873 + 0xbfeff9fa10348837, 0x3fa3a150f6421afc, // -0.99926, 0.03834 + 0xbfeffa72effef75d, 0x3fa2d865759455cd, // -0.99932, 0.036807 + 0xbfeffae6e1556998, 0x3fa20f770ceb11c6, // -0.99938, 0.035274 + 0xbfeffb55e425fdae, 0x3fa14685db42c17e, // -0.99943, 0.033741 + 0xbfeffbbff85f9515, 0x3fa07d91ff984580, // -0.99948, 0.032208 + 0xbfeffc251df1d3f8, 0x3f9f693731d1cf01, // -0.99953, 0.030675 + 0xbfeffc8554cd213a, 0x3f9dd7458c64ab39, // -0.99958, 0.029142 + 0xbfeffce09ce2a679, 0x3f9c454f4ce53b1c, // -0.99962, 0.027608 + 0xbfeffd36f624500c, 0x3f9ab354b1504fca, // -0.99966, 0.026075 + 0xbfeffd886084cd0d, 0x3f992155f7a3667e, // -0.9997, 0.024541 + 0xbfeffdd4dbf78f52, 0x3f978f535ddc9f03, // -0.99974, 0.023008 + 0xbfeffe1c6870cb77, 0x3f95fd4d21fab226, // -0.99977, 0.021474 + 0xbfeffe5f05e578db, 0x3f946b4381fce81c, // -0.9998, 0.01994 + 0xbfeffe9cb44b51a1, 0x3f92d936bbe30efd, // -0.99983, 0.018407 + 0xbfeffed57398d2b7, 0x3f9147270dad7132, // -0.99986, 0.016873 + 0xbfefff0943c53bd1, 0x3f8f6a296ab997ca, // -0.99988, 0.015339 + 0xbfefff3824c88f6f, 0x3f8c45ffe1e48ad9, // -0.9999, 0.013805 + 0xbfefff62169b92db, 0x3f8921d1fcdec784, // -0.99992, 0.012272 + 0xbfefff871937ce2f, 0x3f85fda037ac05e0, // -0.99994, 0.010738 + 0xbfefffa72c978c4f, 0x3f82d96b0e509703, // -0.99996, 0.0092038 + 0xbfefffc250b5daef, 0x3f7f6a65f9a2a3c5, // -0.99997, 0.0076698 + 0xbfefffd8858e8a92, 0x3f7921f0fe670071, // -0.99998, 0.0061359 + 0xbfefffe9cb1e2e8d, 0x3f72d97822f996bc, // -0.99999, 0.0046019 + 0xbfeffff621621d02, 0x3f6921f8becca4ba, // -1, 0.003068 + 0xbfeffffd88586ee6, 0x3f5921faaee6472d, // -1, 0.001534 + 0xbff0000000000000, 0x0000000000000000, // -1, 0 + 0xbfeffffd88586ee6, 0xbf5921faaee6472d, // -1, -0.001534 + 0xbfeffff621621d02, 0xbf6921f8becca4ba, // -1, -0.003068 + 0xbfefffe9cb1e2e8d, 0xbf72d97822f996bc, // -0.99999,-0.0046019 + 0xbfefffd8858e8a92, 0xbf7921f0fe670071, // -0.99998,-0.0061359 + 0xbfefffc250b5daef, 0xbf7f6a65f9a2a3c5, // -0.99997,-0.0076698 + 0xbfefffa72c978c4f, 0xbf82d96b0e509703, // -0.99996,-0.0092038 + 0xbfefff871937ce2f, 0xbf85fda037ac05e0, // -0.99994, -0.010738 + 0xbfefff62169b92db, 0xbf8921d1fcdec784, // -0.99992, -0.012272 + 0xbfefff3824c88f6f, 0xbf8c45ffe1e48ad9, // -0.9999, -0.013805 + 0xbfefff0943c53bd1, 0xbf8f6a296ab997ca, // -0.99988, -0.015339 + 0xbfeffed57398d2b7, 0xbf9147270dad7132, // -0.99986, -0.016873 + 0xbfeffe9cb44b51a1, 0xbf92d936bbe30efd, // -0.99983, -0.018407 + 0xbfeffe5f05e578db, 0xbf946b4381fce81c, // -0.9998, -0.01994 + 0xbfeffe1c6870cb77, 0xbf95fd4d21fab226, // -0.99977, -0.021474 + 0xbfeffdd4dbf78f52, 0xbf978f535ddc9f03, // -0.99974, -0.023008 + 0xbfeffd886084cd0d, 0xbf992155f7a3667e, // -0.9997, -0.024541 + 0xbfeffd36f624500c, 0xbf9ab354b1504fca, // -0.99966, -0.026075 + 0xbfeffce09ce2a679, 0xbf9c454f4ce53b1c, // -0.99962, -0.027608 + 0xbfeffc8554cd213a, 0xbf9dd7458c64ab39, // -0.99958, -0.029142 + 0xbfeffc251df1d3f8, 0xbf9f693731d1cf01, // -0.99953, -0.030675 + 0xbfeffbbff85f9515, 0xbfa07d91ff984580, // -0.99948, -0.032208 + 0xbfeffb55e425fdae, 0xbfa14685db42c17e, // -0.99943, -0.033741 + 0xbfeffae6e1556998, 0xbfa20f770ceb11c6, // -0.99938, -0.035274 + 0xbfeffa72effef75d, 0xbfa2d865759455cd, // -0.99932, -0.036807 + 0xbfeff9fa10348837, 0xbfa3a150f6421afc, // -0.99926, -0.03834 + 0xbfeff97c4208c014, 0xbfa46a396ff86179, // -0.9992, -0.039873 + 0xbfeff8f9858f058b, 0xbfa5331ec3bba0eb, // -0.99914, -0.041406 + 0xbfeff871dadb81df, 0xbfa5fc00d290cd43, // -0.99908, -0.042938 + 0xbfeff7e5420320f9, 0xbfa6c4df7d7d5b84, // -0.99901, -0.044471 + 0xbfeff753bb1b9164, 0xbfa78dbaa5874685, // -0.99894, -0.046003 + 0xbfeff6bd463b444d, 0xbfa856922bb513c1, // -0.99887, -0.047535 + 0xbfeff621e3796d7e, 0xbfa91f65f10dd814, // -0.9988, -0.049068 + 0xbfeff58192ee0358, 0xbfa9e835d6993c87, // -0.99872, -0.0506 + 0xbfeff4dc54b1bed3, 0xbfaab101bd5f8317, // -0.99864, -0.052132 + 0xbfeff43228de1b77, 0xbfab79c986698b78, // -0.99856, -0.053664 + 0xbfeff3830f8d575c, 0xbfac428d12c0d7e3, // -0.99848, -0.055195 + 0xbfeff2cf08da7321, 0xbfad0b4c436f91d0, // -0.99839, -0.056727 + 0xbfeff21614e131ed, 0xbfadd406f9808ec8, // -0.9983, -0.058258 + 0xbfeff15833be1965, 0xbfae9cbd15ff5527, // -0.99821, -0.05979 + 0xbfeff095658e71ad, 0xbfaf656e79f820e0, // -0.99812, -0.061321 + 0xbfefefcdaa704562, 0xbfb0170d833bf421, // -0.99802, -0.062852 + 0xbfefef0102826191, 0xbfb07b614e463064, // -0.99793, -0.064383 + 0xbfefee2f6de455ba, 0xbfb0dfb28ea201e6, // -0.99783, -0.065913 + 0xbfefed58ecb673c4, 0xbfb1440134d709b2, // -0.99772, -0.067444 + 0xbfefec7d7f19cffc, 0xbfb1a84d316d4f8a, // -0.99762, -0.068974 + 0xbfefeb9d2530410f, 0xbfb20c9674ed444c, // -0.99751, -0.070505 + 0xbfefeab7df1c6005, 0xbfb270dcefdfc45b, // -0.9974, -0.072035 + 0xbfefe9cdad01883a, 0xbfb2d52092ce19f6, // -0.99729, -0.073565 + 0xbfefe8de8f03d75c, 0xbfb339614e41ffa5, // -0.99718, -0.075094 + 0xbfefe7ea85482d60, 0xbfb39d9f12c5a299, // -0.99706, -0.076624 + 0xbfefe6f18ff42c84, 0xbfb401d9d0e3a507, // -0.99694, -0.078153 + 0xbfefe5f3af2e3940, 0xbfb4661179272096, // -0.99682, -0.079682 + 0xbfefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // -0.9967, -0.081211 + 0xbfefe3e92be9d886, 0xbfb52e774a4d4d0a, // -0.99657, -0.08274 + 0xbfefe2dc89bbff08, 0xbfb592a554489bc8, // -0.99644, -0.084269 + 0xbfefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // -0.99631, -0.085797 + 0xbfefe0b485181be3, 0xbfb65af75dd0f87b, // -0.99618, -0.087326 + 0xbfefdf9922f73307, 0xbfb6bf1b3e79b129, // -0.99604, -0.088854 + 0xbfefde78d68653fd, 0xbfb7233b9d236e71, // -0.99591, -0.090381 + 0xbfefdd539ff1f456, 0xbfb787586a5d5b21, // -0.99577, -0.091909 + 0xbfefdc297f674ba9, 0xbfb7eb7196b72ee4, // -0.99563, -0.093436 + 0xbfefdafa7514538c, 0xbfb84f8712c130a0, // -0.99548, -0.094963 + 0xbfefd9c68127c78c, 0xbfb8b398cf0c38e0, // -0.99533, -0.09649 + 0xbfefd88da3d12526, 0xbfb917a6bc29b42c, // -0.99518, -0.098017 + 0xbfefd74fdd40abbf, 0xbfb97bb0caaba56f, // -0.99503, -0.099544 + 0xbfefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // -0.99488, -0.10107 + 0xbfefd4c59536fae4, 0xbfba43b90e27f3c4, // -0.99472, -0.1026 + 0xbfefd37914220b84, 0xbfbaa7b724495c04, // -0.99456, -0.10412 + 0xbfefd227aa9bd53b, 0xbfbb0bb11e1d5559, // -0.9944, -0.10565 + 0xbfefd0d158d86087, 0xbfbb6fa6ec38f64c, // -0.99424, -0.10717 + 0xbfefcf761f0c77a3, 0xbfbbd3987f31fa0e, // -0.99407, -0.1087 + 0xbfefce15fd6da67b, 0xbfbc3785c79ec2d5, // -0.99391, -0.11022 + 0xbfefccb0f4323aa3, 0xbfbc9b6eb6165c42, // -0.99374, -0.11175 + 0xbfefcb4703914354, 0xbfbcff533b307dc1, // -0.99356, -0.11327 + 0xbfefc9d82bc2915e, 0xbfbd633347858ce4, // -0.99339, -0.11479 + 0xbfefc8646cfeb721, 0xbfbdc70ecbae9fc8, // -0.99321, -0.11632 + 0xbfefc6ebc77f0887, 0xbfbe2ae5b8457f77, // -0.99303, -0.11784 + 0xbfefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // -0.99285, -0.11937 + 0xbfefc3ebc935454c, 0xbfbef2858d27561b, // -0.99267, -0.12089 + 0xbfefc26470e19fd3, 0xbfbf564e56a9730e, // -0.99248, -0.12241 + 0xbfefc0d832bf043a, 0xbfbfba124b07ad85, // -0.99229, -0.12393 + 0xbfefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // -0.9921, -0.12545 + 0xbfefbdb106021816, 0xbfc040c5bb67747e, // -0.99191, -0.12698 + 0xbfefbc1617e44186, 0xbfc072a047ba831d, // -0.99171, -0.1285 + 0xbfefba7644f068b5, 0xbfc0a4784ab8bf1d, // -0.99151, -0.13002 + 0xbfefb8d18d66adb7, 0xbfc0d64dbcb26786, // -0.99131, -0.13154 + 0xbfefb727f187f1c7, 0xbfc1082095f820b0, // -0.99111, -0.13306 + 0xbfefb5797195d741, 0xbfc139f0cedaf576, // -0.9909, -0.13458 + 0xbfefb3c60dd2c199, 0xbfc16bbe5fac5865, // -0.9907, -0.1361 + 0xbfefb20dc681d54d, 0xbfc19d8940be24e7, // -0.99049, -0.13762 + 0xbfefb0509be6f7db, 0xbfc1cf516a62a077, // -0.99027, -0.13914 + 0xbfefae8e8e46cfbb, 0xbfc20116d4ec7bce, // -0.99006, -0.14066 + 0xbfefacc79de6c44f, 0xbfc232d978aed413, // -0.98984, -0.14218 + 0xbfefaafbcb0cfddc, 0xbfc264994dfd340a, // -0.98962, -0.1437 + 0xbfefa92b1600657c, 0xbfc296564d2b953e, // -0.9894, -0.14521 + 0xbfefa7557f08a517, 0xbfc2c8106e8e613a, // -0.98918, -0.14673 + 0xbfefa57b066e2754, 0xbfc2f9c7aa7a72af, // -0.98895, -0.14825 + 0xbfefa39bac7a1791, 0xbfc32b7bf94516a7, // -0.98872, -0.14976 + 0xbfefa1b7717661d5, 0xbfc35d2d53440db2, // -0.98849, -0.15128 + 0xbfef9fce55adb2c8, 0xbfc38edbb0cd8d14, // -0.98826, -0.1528 + 0xbfef9de0596b77a3, 0xbfc3c0870a383ff6, // -0.98802, -0.15431 + 0xbfef9bed7cfbde29, 0xbfc3f22f57db4893, // -0.98778, -0.15583 + 0xbfef99f5c0abd496, 0xbfc423d4920e4166, // -0.98754, -0.15734 + 0xbfef97f924c9099b, 0xbfc45576b1293e5a, // -0.9873, -0.15886 + 0xbfef95f7a9a1ec47, 0xbfc48715ad84cdf5, // -0.98706, -0.16037 + 0xbfef93f14f85ac08, 0xbfc4b8b17f79fa88, // -0.98681, -0.16189 + 0xbfef91e616c43891, 0xbfc4ea4a1f624b61, // -0.98656, -0.1634 + 0xbfef8fd5ffae41db, 0xbfc51bdf8597c5f2, // -0.98631, -0.16491 + 0xbfef8dc10a95380d, 0xbfc54d71aa74ef02, // -0.98605, -0.16643 + 0xbfef8ba737cb4b78, 0xbfc57f008654cbde, // -0.9858, -0.16794 + 0xbfef898887a36c84, 0xbfc5b08c1192e381, // -0.98554, -0.16945 + 0xbfef8764fa714ba9, 0xbfc5e214448b3fc6, // -0.98528, -0.17096 + 0xbfef853c9089595e, 0xbfc61399179a6e94, // -0.98501, -0.17247 + 0xbfef830f4a40c60c, 0xbfc6451a831d830d, // -0.98475, -0.17398 + 0xbfef80dd27ed8204, 0xbfc676987f7216b8, // -0.98448, -0.17549 + 0xbfef7ea629e63d6e, 0xbfc6a81304f64ab2, // -0.98421, -0.177 + 0xbfef7c6a50826840, 0xbfc6d98a0c08c8da, // -0.98394, -0.17851 + 0xbfef7a299c1a322a, 0xbfc70afd8d08c4ff, // -0.98366, -0.18002 + 0xbfef77e40d068a90, 0xbfc73c6d8055fe0a, // -0.98339, -0.18153 + 0xbfef7599a3a12077, 0xbfc76dd9de50bf31, // -0.98311, -0.18304 + 0xbfef734a60446279, 0xbfc79f429f59e11d, // -0.98282, -0.18455 + 0xbfef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // -0.98254, -0.18606 + 0xbfef6e9d4d1262ca, 0xbfc802092c1d744b, // -0.98225, -0.18756 + 0xbfef6c3f7df5bbb7, 0xbfc83366e89c64c5, // -0.98196, -0.18907 + 0xbfef69dcd652f5de, 0xbfc864c0e9b2b6cf, // -0.98167, -0.19057 + 0xbfef677556883cee, 0xbfc8961727c41804, // -0.98138, -0.19208 + 0xbfef6508fef47bd5, 0xbfc8c7699b34ca7e, // -0.98108, -0.19359 + 0xbfef6297cff75cb0, 0xbfc8f8b83c69a60a, // -0.98079, -0.19509 + 0xbfef6021c9f148c2, 0xbfc92a0303c8194f, // -0.98048, -0.19659 + 0xbfef5da6ed43685d, 0xbfc95b49e9b62af9, // -0.98018, -0.1981 + 0xbfef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // -0.97988, -0.1996 + 0xbfef58a2b1789e84, 0xbfc9bdcbf2dc4366, // -0.97957, -0.2011 + 0xbfef56195321c090, 0xbfc9ef0706e35a35, // -0.97926, -0.20261 + 0xbfef538b1faf2d07, 0xbfca203e1b1831da, // -0.97895, -0.20411 + 0xbfef50f81785c6b9, 0xbfca517127e3dabc, // -0.97863, -0.20561 + 0xbfef4e603b0b2f2d, 0xbfca82a025b00451, // -0.97832, -0.20711 + 0xbfef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // -0.978, -0.20861 + 0xbfef492206bcabb4, 0xbfcae4f1d5f3b9ab, // -0.97768, -0.21011 + 0xbfef467bafb7bbe0, 0xbfcb16147941ca2a, // -0.97735, -0.21161 + 0xbfef43d085ff92dd, 0xbfcb4732ef3d6722, // -0.97703, -0.21311 + 0xbfef412089fd8adc, 0xbfcb784d30536cda, // -0.9767, -0.21461 + 0xbfef3e6bbc1bbc65, 0xbfcba96334f15dad, // -0.97637, -0.21611 + 0xbfef3bb21cc4fe47, 0xbfcbda74f5856330, // -0.97604, -0.2176 + 0xbfef38f3ac64e589, 0xbfcc0b826a7e4f63, // -0.9757, -0.2191 + 0xbfef36306b67c556, 0xbfcc3c8b8c4b9dd7, // -0.97536, -0.2206 + 0xbfef33685a3aaef0, 0xbfcc6d90535d74dc, // -0.97503, -0.22209 + 0xbfef309b794b719f, 0xbfcc9e90b824a6a9, // -0.97468, -0.22359 + 0xbfef2dc9c9089a9d, 0xbfcccf8cb312b286, // -0.97434, -0.22508 + 0xbfef2af349e17507, 0xbfcd00843c99c5f9, // -0.97399, -0.22658 + 0xbfef2817fc4609ce, 0xbfcd31774d2cbdee, // -0.97364, -0.22807 + 0xbfef2537e0a71f9f, 0xbfcd6265dd3f27e3, // -0.97329, -0.22957 + 0xbfef2252f7763ada, 0xbfcd934fe5454311, // -0.97294, -0.23106 + 0xbfef1f6941259d7a, 0xbfcdc4355db40195, // -0.97258, -0.23255 + 0xbfef1c7abe284708, 0xbfcdf5163f01099a, // -0.97223, -0.23404 + 0xbfef19876ef1f486, 0xbfce25f281a2b684, // -0.97187, -0.23553 + 0xbfef168f53f7205d, 0xbfce56ca1e101a1b, // -0.9715, -0.23702 + 0xbfef13926dad024e, 0xbfce879d0cc0fdaf, // -0.97114, -0.23851 + 0xbfef1090bc898f5f, 0xbfceb86b462de348, // -0.97077, -0.24 + 0xbfef0d8a410379c5, 0xbfcee934c2d006c7, // -0.9704, -0.24149 + 0xbfef0a7efb9230d7, 0xbfcf19f97b215f1a, // -0.97003, -0.24298 + 0xbfef076eecade0fa, 0xbfcf4ab9679c9f5c, // -0.96966, -0.24447 + 0xbfef045a14cf738c, 0xbfcf7b7480bd3801, // -0.96928, -0.24596 + 0xbfef014074708ed3, 0xbfcfac2abeff57ff, // -0.9689, -0.24744 + 0xbfeefe220c0b95ec, 0xbfcfdcdc1adfedf8, // -0.96852, -0.24893 + 0xbfeefafedc1ba8b7, 0xbfd006c4466e54af, // -0.96814, -0.25041 + 0xbfeef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // -0.96775, -0.2519 + 0xbfeef4aa278b2032, 0xbfd037694a928cac, // -0.96737, -0.25338 + 0xbfeef178a3e473c2, 0xbfd04fb80e37fdae, // -0.96698, -0.25487 + 0xbfeeee425aa6b09a, 0xbfd068044deab002, // -0.96658, -0.25635 + 0xbfeeeb074c50a544, 0xbfd0804e05eb661e, // -0.96619, -0.25783 + 0xbfeee7c77961dc9e, 0xbfd09895327b465e, // -0.96579, -0.25931 + 0xbfeee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // -0.96539, -0.26079 + 0xbfeee13987bbebdc, 0xbfd0c91bda4f158d, // -0.96499, -0.26227 + 0xbfeeddeb6a078651, 0xbfd0e15b4e1749cd, // -0.96459, -0.26375 + 0xbfeeda9889bfe86a, 0xbfd0f998277733f7, // -0.96418, -0.26523 + 0xbfeed740e7684963, 0xbfd111d262b1f677, // -0.96378, -0.26671 + 0xbfeed3e483849c51, 0xbfd12a09fc0b1b12, // -0.96337, -0.26819 + 0xbfeed0835e999009, 0xbfd1423eefc69378, // -0.96295, -0.26967 + 0xbfeecd1d792c8f10, 0xbfd15a713a28b9d9, // -0.96254, -0.27115 + 0xbfeec9b2d3c3bf84, 0xbfd172a0d7765177, // -0.96212, -0.27262 + 0xbfeec6436ee60309, 0xbfd18acdc3f4873a, // -0.9617, -0.2741 + 0xbfeec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // -0.96128, -0.27557 + 0xbfeebf5668eaf2ef, 0xbfd1bb1f7b999480, // -0.96086, -0.27705 + 0xbfeebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // -0.96043, -0.27852 + 0xbfeeb8566b810f2a, 0xbfd1eb6643499fbb, // -0.96, -0.27999 + 0xbfeeb4cf515b8811, 0xbfd2038583d727bd, // -0.95957, -0.28146 + 0xbfeeb1437af9bb34, 0xbfd21ba1fd3d2623, // -0.95914, -0.28294 + 0xbfeeadb2e8e7a88e, 0xbfd233bbabc3bb72, // -0.9587, -0.28441 + 0xbfeeaa1d9bb20af3, 0xbfd24bd28bb37672, // -0.95827, -0.28588 + 0xbfeea68393e65800, 0xbfd263e6995554ba, // -0.95783, -0.28735 + 0xbfeea2e4d212c000, 0xbfd27bf7d0f2c346, // -0.95738, -0.28882 + 0xbfee9f4156c62dda, 0xbfd294062ed59f05, // -0.95694, -0.29028 + 0xbfee9b99229046f8, 0xbfd2ac11af483572, // -0.95649, -0.29175 + 0xbfee97ec36016b30, 0xbfd2c41a4e954520, // -0.95605, -0.29322 + 0xbfee943a91aab4b4, 0xbfd2dc200907fe51, // -0.95559, -0.29469 + 0xbfee9084361df7f3, 0xbfd2f422daec0386, // -0.95514, -0.29615 + 0xbfee8cc923edc388, 0xbfd30c22c08d6a13, // -0.95469, -0.29762 + 0xbfee89095bad6025, 0xbfd3241fb638baaf, // -0.95423, -0.29908 + 0xbfee8544ddf0d075, 0xbfd33c19b83af207, // -0.95377, -0.30054 + 0xbfee817bab4cd10d, 0xbfd35410c2e18152, // -0.95331, -0.30201 + 0xbfee7dadc456d850, 0xbfd36c04d27a4edf, // -0.95284, -0.30347 + 0xbfee79db29a5165a, 0xbfd383f5e353b6aa, // -0.95238, -0.30493 + 0xbfee7603dbce74e9, 0xbfd39be3f1bc8aef, // -0.95191, -0.30639 + 0xbfee7227db6a9744, 0xbfd3b3cefa0414b7, // -0.95144, -0.30785 + 0xbfee6e472911da27, 0xbfd3cbb6f87a146e, // -0.95096, -0.30931 + 0xbfee6a61c55d53a7, 0xbfd3e39be96ec271, // -0.95049, -0.31077 + 0xbfee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // -0.95001, -0.31222 + 0xbfee6288ec48e112, 0xbfd4135c94176602, // -0.94953, -0.31368 + 0xbfee5e95781ebf1c, 0xbfd42b38466e2928, // -0.94905, -0.31514 + 0xbfee5a9d550467d3, 0xbfd44310dc8936f0, // -0.94856, -0.31659 + 0xbfee56a083968eb1, 0xbfd45ae652bb2800, // -0.94807, -0.31805 + 0xbfee529f04729ffc, 0xbfd472b8a5571054, // -0.94759, -0.3195 + 0xbfee4e98d836c0af, 0xbfd48a87d0b07fd7, // -0.94709, -0.32096 + 0xbfee4a8dff81ce5e, 0xbfd4a253d11b82f3, // -0.9466, -0.32241 + 0xbfee467e7af35f23, 0xbfd4ba1ca2eca31c, // -0.94611, -0.32386 + 0xbfee426a4b2bc17e, 0xbfd4d1e24278e76a, // -0.94561, -0.32531 + 0xbfee3e5170cbfc46, 0xbfd4e9a4ac15d520, // -0.94511, -0.32676 + 0xbfee3a33ec75ce85, 0xbfd50163dc197047, // -0.9446, -0.32821 + 0xbfee3611becbaf69, 0xbfd5191fceda3c35, // -0.9441, -0.32966 + 0xbfee31eae870ce25, 0xbfd530d880af3c24, // -0.94359, -0.33111 + 0xbfee2dbf6a0911d9, 0xbfd5488dedeff3be, // -0.94308, -0.33255 + 0xbfee298f4439197a, 0xbfd5604012f467b4, // -0.94257, -0.334 + 0xbfee255a77a63bb8, 0xbfd577eeec151e47, // -0.94206, -0.33545 + 0xbfee212104f686e5, 0xbfd58f9a75ab1fdd, // -0.94154, -0.33689 + 0xbfee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // -0.94103, -0.33833 + 0xbfee18a02fdc66d9, 0xbfd5bee78b9db3b6, // -0.94051, -0.33978 + 0xbfee1458cec1ad83, 0xbfd5d68910aee686, // -0.93998, -0.34122 + 0xbfee100cca2980ac, 0xbfd5ee27379ea693, // -0.93946, -0.34266 + 0xbfee0bbc22bd8349, 0xbfd605c1fcc88f63, // -0.93893, -0.3441 + 0xbfee0766d9280f54, 0xbfd61d595c88c203, // -0.9384, -0.34554 + 0xbfee030cee1435b8, 0xbfd634ed533be58e, // -0.93787, -0.34698 + 0xbfedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // -0.93734, -0.34842 + 0xbfedfa4b3621271d, 0xbfd6640af6f03d9e, // -0.9368, -0.34986 + 0xbfedf5e36a9ba59c, 0xbfd67b949cad63ca, // -0.93627, -0.35129 + 0xbfedf177004b2534, 0xbfd6931acad55f51, // -0.93573, -0.35273 + 0xbfeded05f7de47da, 0xbfd6aa9d7dc77e16, // -0.93518, -0.35416 + 0xbfede890520465ce, 0xbfd6c21cb1e39771, // -0.93464, -0.3556 + 0xbfede4160f6d8d81, 0xbfd6d998638a0cb5, // -0.93409, -0.35703 + 0xbfeddf9730ca837b, 0xbfd6f1108f1bc9c5, // -0.93354, -0.35846 + 0xbfeddb13b6ccc23d, 0xbfd7088530fa459e, // -0.93299, -0.3599 + 0xbfedd68ba2267a25, 0xbfd71ff6458782ec, // -0.93244, -0.36133 + 0xbfedd1fef38a915a, 0xbfd73763c9261092, // -0.93188, -0.36276 + 0xbfedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // -0.93133, -0.36418 + 0xbfedc8d7cb410260, 0xbfd766340f2418f6, // -0.93077, -0.36561 + 0xbfedc43d52fcb453, 0xbfd77d96ca4b73a6, // -0.93021, -0.36704 + 0xbfedbf9e4395759a, 0xbfd794f5e613dfae, // -0.92964, -0.36847 + 0xbfedbafa9dc1b78d, 0xbfd7ac515ee2b172, // -0.92907, -0.36989 + 0xbfedb6526238a09b, 0xbfd7c3a9311dcce7, // -0.92851, -0.37132 + 0xbfedb1a591b20c38, 0xbfd7dafd592ba621, // -0.92794, -0.37274 + 0xbfedacf42ce68ab9, 0xbfd7f24dd37341e3, // -0.92736, -0.37416 + 0xbfeda83e348f613b, 0xbfd8099a9c5c362d, // -0.92679, -0.37559 + 0xbfeda383a9668988, 0xbfd820e3b04eaac4, // -0.92621, -0.37701 + 0xbfed9ec48c26b1f3, 0xbfd838290bb359c8, // -0.92563, -0.37843 + 0xbfed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // -0.92505, -0.37985 + 0xbfed95389e50429b, 0xbfd866a88a792ea0, // -0.92447, -0.38127 + 0xbfed906bcf328d46, 0xbfd87de2a6aea963, // -0.92388, -0.38268 + 0xbfed8b9a70ef9cb4, 0xbfd89518fbff098e, // -0.92329, -0.3841 + 0xbfed86c48445a450, 0xbfd8ac4b86d5ed44, // -0.9227, -0.38552 + 0xbfed81ea09f38b63, 0xbfd8c37a439f884f, // -0.92211, -0.38693 + 0xbfed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // -0.92151, -0.38835 + 0xbfed78276f5617c6, 0xbfd8f1cc44bea329, // -0.92092, -0.38976 + 0xbfed733f508c0dff, 0xbfd908ef81ef7bd1, // -0.92032, -0.39117 + 0xbfed6e52a71c8547, 0xbfd9200ee2c9be97, // -0.91972, -0.39258 + 0xbfed696173c9e68b, 0xbfd9372a63bc93d7, // -0.91911, -0.39399 + 0xbfed646bb7574de5, 0xbfd94e420137bce3, // -0.91851, -0.3954 + 0xbfed5f7172888a7f, 0xbfd96555b7ab948f, // -0.9179, -0.39681 + 0xbfed5a72a6221e73, 0xbfd97c6583890fc2, // -0.91729, -0.39822 + 0xbfed556f52e93eb1, 0xbfd993716141bdfe, // -0.91668, -0.39962 + 0xbfed506779a3d2d9, 0xbfd9aa794d47c9ee, // -0.91606, -0.40103 + 0xbfed4b5b1b187524, 0xbfd9c17d440df9f2, // -0.91545, -0.40243 + 0xbfed464a380e7242, 0xbfd9d87d4207b0ab, // -0.91483, -0.40384 + 0xbfed4134d14dc93a, 0xbfd9ef7943a8ed8a, // -0.91421, -0.40524 + 0xbfed3c1ae79f2b4e, 0xbfda067145664d57, // -0.91359, -0.40664 + 0xbfed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // -0.91296, -0.40804 + 0xbfed31d98e9e503a, 0xbfda34553b0afee5, // -0.91234, -0.40944 + 0xbfed2cb220e0ef9f, 0xbfda4b4127dea1e4, // -0.91171, -0.41084 + 0xbfed2786335f52fc, 0xbfda622906a70b63, // -0.91107, -0.41224 + 0xbfed2255c6e5a4e1, 0xbfda790cd3dbf31a, // -0.91044, -0.41364 + 0xbfed1d20dc40c15c, 0xbfda8fec8bf5b166, // -0.90981, -0.41503 + 0xbfed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // -0.90917, -0.41643 + 0xbfed12a98fac410c, 0xbfdabd9faebc3980, // -0.90853, -0.41782 + 0xbfed0d672f59d2b9, 0xbfdad473125cdc08, // -0.90789, -0.41922 + 0xbfed082054168bac, 0xbfdaeb4252ca07ab, // -0.90724, -0.42061 + 0xbfed02d4feb2bd92, 0xbfdb020d6c7f4009, // -0.9066, -0.422 + 0xbfecfd852fff6ad4, 0xbfdb18d45bf8aca6, // -0.90595, -0.42339 + 0xbfecf830e8ce467b, 0xbfdb2f971db31972, // -0.9053, -0.42478 + 0xbfecf2d829f1b40e, 0xbfdb4655ae2bf757, // -0.90464, -0.42617 + 0xbfeced7af43cc773, 0xbfdb5d1009e15cc0, // -0.90399, -0.42756 + 0xbfece819488344ce, 0xbfdb73c62d520624, // -0.90333, -0.42894 + 0xbfece2b32799a060, 0xbfdb8a7814fd5693, // -0.90267, -0.43033 + 0xbfecdd489254fe65, 0xbfdba125bd63583e, // -0.90201, -0.43171 + 0xbfecd7d9898b32f6, 0xbfdbb7cf2304bd01, // -0.90135, -0.43309 + 0xbfecd2660e12c1e6, 0xbfdbce744262deee, // -0.90068, -0.43448 + 0xbfecccee20c2de9f, 0xbfdbe51517ffc0d9, // -0.90002, -0.43586 + 0xbfecc771c2736c09, 0xbfdbfbb1a05e0edc, // -0.89935, -0.43724 + 0xbfecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // -0.89867, -0.43862 + 0xbfecbc6bb638d10b, 0xbfdc28ddbb6cf145, // -0.898, -0.43999 + 0xbfecb6e20a00da99, 0xbfdc3f6d47263129, // -0.89732, -0.44137 + 0xbfecb153f02fb87d, 0xbfdc55f877b23537, // -0.89665, -0.44275 + 0xbfecabc169a0b901, 0xbfdc6c7f4997000a, // -0.89597, -0.44412 + 0xbfeca62a772fd919, 0xbfdc8301b95b40c2, // -0.89528, -0.4455 + 0xbfeca08f19b9c449, 0xbfdc997fc3865388, // -0.8946, -0.44687 + 0xbfec9aef521bd480, 0xbfdcaff964a0421d, // -0.89391, -0.44824 + 0xbfec954b213411f5, 0xbfdcc66e9931c45d, // -0.89322, -0.44961 + 0xbfec8fa287e13305, 0xbfdcdcdf5dc440ce, // -0.89253, -0.45098 + 0xbfec89f587029c13, 0xbfdcf34baee1cd21, // -0.89184, -0.45235 + 0xbfec84441f785f61, 0xbfdd09b389152ec1, // -0.89115, -0.45372 + 0xbfec7e8e52233cf3, 0xbfdd2016e8e9db5b, // -0.89045, -0.45508 + 0xbfec78d41fe4a267, 0xbfdd3675caebf962, // -0.88975, -0.45645 + 0xbfec7315899eaad7, 0xbfdd4cd02ba8609c, // -0.88905, -0.45781 + 0xbfec6d5290341eb2, 0xbfdd632607ac9aa9, // -0.88835, -0.45918 + 0xbfec678b3488739b, 0xbfdd79775b86e389, // -0.88764, -0.46054 + 0xbfec61bf777fcc48, 0xbfdd8fc423c62a25, // -0.88693, -0.4619 + 0xbfec5bef59fef85a, 0xbfdda60c5cfa10d8, // -0.88622, -0.46326 + 0xbfec561adceb743e, 0xbfddbc5003b2edf8, // -0.88551, -0.46462 + 0xbfec5042012b6907, 0xbfddd28f1481cc58, // -0.8848, -0.46598 + 0xbfec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // -0.88408, -0.46733 + 0xbfec44833141c004, 0xbfddfeff66a941de, // -0.88336, -0.46869 + 0xbfec3e9d3ee7d262, 0xbfde1530a12779f4, // -0.88264, -0.47004 + 0xbfec38b2f180bdb1, 0xbfde2b5d3806f63b, // -0.88192, -0.4714 + 0xbfec32c449f60831, 0xbfde418527dc4ffa, // -0.8812, -0.47275 + 0xbfec2cd14931e3f1, 0xbfde57a86d3cd824, // -0.88047, -0.4741 + 0xbfec26d9f01f2eaf, 0xbfde6dc704be97e2, // -0.87974, -0.47545 + 0xbfec20de3fa971b0, 0xbfde83e0eaf85113, // -0.87901, -0.4768 + 0xbfec1ade38bce19b, 0xbfde99f61c817eda, // -0.87828, -0.47815 + 0xbfec14d9dc465e58, 0xbfdeb00695f25620, // -0.87755, -0.47949 + 0xbfec0ed12b3372e9, 0xbfdec61253e3c61b, // -0.87681, -0.48084 + 0xbfec08c426725549, 0xbfdedc1952ef78d5, // -0.87607, -0.48218 + 0xbfec02b2cef1e641, 0xbfdef21b8fafd3b5, // -0.87533, -0.48353 + 0xbfebfc9d25a1b147, 0xbfdf081906bff7fd, // -0.87459, -0.48487 + 0xbfebf6832b71ec5b, 0xbfdf1e11b4bbc35c, // -0.87384, -0.48621 + 0xbfebf064e15377dd, 0xbfdf3405963fd068, // -0.87309, -0.48755 + 0xbfebea424837de6d, 0xbfdf49f4a7e97729, // -0.87235, -0.48889 + 0xbfebe41b611154c1, 0xbfdf5fdee656cda3, // -0.8716, -0.49023 + 0xbfebddf02cd2b983, 0xbfdf75c44e26a852, // -0.87084, -0.49156 + 0xbfebd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // -0.87009, -0.4929 + 0xbfebd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // -0.86933, -0.49423 + 0xbfebcb54cb0d2327, 0xbfdfb7575c24d2de, // -0.86857, -0.49557 + 0xbfebc5186bf8361d, 0xbfdfcd2947c1ff57, // -0.86781, -0.4969 + 0xbfebbed7c49380ea, 0xbfdfe2f64be7120f, // -0.86705, -0.49823 + 0xbfebb892d5d5dad5, 0xbfdff8be6537615e, // -0.86628, -0.49956 + 0xbfebb249a0b6c40d, 0xbfe00740c82b82e0, // -0.86551, -0.50089 + 0xbfebabfc262e6586, 0xbfe0121fe4f56d2c, // -0.86474, -0.50221 + 0xbfeba5aa673590d2, 0xbfe01cfc874c3eb7, // -0.86397, -0.50354 + 0xbfeb9f5464c5bffc, 0xbfe027d6ad83287e, // -0.8632, -0.50486 + 0xbfeb98fa1fd9155e, 0xbfe032ae55edbd95, // -0.86242, -0.50619 + 0xbfeb929b996a5b7f, 0xbfe03d837edff370, // -0.86165, -0.50751 + 0xbfeb8c38d27504e9, 0xbfe0485626ae221a, // -0.86087, -0.50883 + 0xbfeb85d1cbf52c02, 0xbfe053264bad0483, // -0.86009, -0.51015 + 0xbfeb7f6686e792ea, 0xbfe05df3ec31b8b6, // -0.8593, -0.51147 + 0xbfeb78f70449a34b, 0xbfe068bf0691c028, // -0.85852, -0.51279 + 0xbfeb728345196e3e, 0xbfe073879922ffed, // -0.85773, -0.5141 + 0xbfeb6c0b4a55ac17, 0xbfe07e4da23bc102, // -0.85694, -0.51542 + 0xbfeb658f14fdbc47, 0xbfe089112032b08c, // -0.85615, -0.51673 + 0xbfeb5f0ea611a532, 0xbfe093d2115ee018, // -0.85535, -0.51804 + 0xbfeb5889fe921405, 0xbfe09e907417c5e1, // -0.85456, -0.51936 + 0xbfeb52011f805c92, 0xbfe0a94c46b53d0b, // -0.85376, -0.52067 + 0xbfeb4b7409de7925, 0xbfe0b405878f85ec, // -0.85296, -0.52198 + 0xbfeb44e2beaf0a61, 0xbfe0bebc34ff4646, // -0.85216, -0.52328 + 0xbfeb3e4d3ef55712, 0xbfe0c9704d5d898f, // -0.85136, -0.52459 + 0xbfeb37b38bb54c09, 0xbfe0d421cf03c12b, // -0.85055, -0.5259 + 0xbfeb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // -0.84974, -0.5272 + 0xbfeb2a738eb51f33, 0xbfe0e97d078fd23b, // -0.84893, -0.5285 + 0xbfeb23cd470013b4, 0xbfe0f426bb2a8e7d, // -0.84812, -0.5298 + 0xbfeb1d22cfdadcc6, 0xbfe0fecdd1770537, // -0.84731, -0.5311 + 0xbfeb16742a4ca2f5, 0xbfe1097248d0a956, // -0.84649, -0.5324 + 0xbfeb0fc1575d33db, 0xbfe114141f935545, // -0.84567, -0.5337 + 0xbfeb090a58150200, 0xbfe11eb3541b4b22, // -0.84485, -0.535 + 0xbfeb024f2d7d24a9, 0xbfe1294fe4c5350a, // -0.84403, -0.53629 + 0xbfeafb8fd89f57b6, 0xbfe133e9cfee254e, // -0.84321, -0.53759 + 0xbfeaf4cc5a85fb73, 0xbfe13e8113f396c1, // -0.84238, -0.53888 + 0xbfeaee04b43c1474, 0xbfe14915af336ceb, // -0.84155, -0.54017 + 0xbfeae738e6cd4b67, 0xbfe153a7a00bf453, // -0.84073, -0.54146 + 0xbfeae068f345ecef, 0xbfe15e36e4dbe2bc, // -0.83989, -0.54275 + 0xbfead994dab2e979, 0xbfe168c37c025764, // -0.83906, -0.54404 + 0xbfead2bc9e21d511, 0xbfe1734d63dedb49, // -0.83822, -0.54532 + 0xbfeacbe03ea0e73b, 0xbfe17dd49ad16161, // -0.83739, -0.54661 + 0xbfeac4ffbd3efac8, 0xbfe188591f3a46e5, // -0.83655, -0.54789 + 0xbfeabe1b1b0b8dac, 0xbfe192daef7a5386, // -0.83571, -0.54918 + 0xbfeab7325916c0d4, 0xbfe19d5a09f2b9b8, // -0.83486, -0.55046 + 0xbfeab045787157ff, 0xbfe1a7d66d0516e6, // -0.83402, -0.55174 + 0xbfeaa9547a2cb98e, 0xbfe1b250171373be, // -0.83317, -0.55302 + 0xbfeaa25f5f5aee60, 0xbfe1bcc706804467, // -0.83232, -0.55429 + 0xbfea9b66290ea1a3, 0xbfe1c73b39ae68c8, // -0.83147, -0.55557 + 0xbfea9468d85b20ae, 0xbfe1d1acaf012cc2, // -0.83062, -0.55685 + 0xbfea8d676e545ad2, 0xbfe1dc1b64dc4872, // -0.82976, -0.55812 + 0xbfea8661ec0ee133, 0xbfe1e68759a3e074, // -0.8289, -0.55939 + 0xbfea7f58529fe69d, 0xbfe1f0f08bbc861b, // -0.82805, -0.56066 + 0xbfea784aa31d3f55, 0xbfe1fb56f98b37b8, // -0.82718, -0.56193 + 0xbfea7138de9d60f5, 0xbfe205baa17560d6, // -0.82632, -0.5632 + 0xbfea6a230637623b, 0xbfe2101b81e0da78, // -0.82546, -0.56447 + 0xbfea63091b02fae2, 0xbfe21a799933eb58, // -0.82459, -0.56573 + 0xbfea5beb1e188375, 0xbfe224d4e5d5482e, // -0.82372, -0.567 + 0xbfea54c91090f524, 0xbfe22f2d662c13e1, // -0.82285, -0.56826 + 0xbfea4da2f385e997, 0xbfe23983189fdfd5, // -0.82198, -0.56952 + 0xbfea4678c8119ac8, 0xbfe243d5fb98ac1f, // -0.8211, -0.57078 + 0xbfea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // -0.82023, -0.57204 + 0xbfea38184a593bc6, 0xbfe258734cbb7110, // -0.81935, -0.5733 + 0xbfea30e1fa4cbf81, 0xbfe262bdb7b795a2, // -0.81847, -0.57455 + 0xbfea29a7a0462782, 0xbfe26d054cdd12df, // -0.81758, -0.57581 + 0xbfea22693d62ccb9, 0xbfe2774a0a961612, // -0.8167, -0.57706 + 0xbfea1b26d2c0a75e, 0xbfe2818bef4d3cba, // -0.81581, -0.57831 + 0xbfea13e0617e4ec7, 0xbfe28bcaf96d94ba, // -0.81493, -0.57956 + 0xbfea0c95eabaf937, 0xbfe2960727629ca8, // -0.81404, -0.58081 + 0xbfea05476f967bb5, 0xbfe2a040779843fb, // -0.81314, -0.58206 + 0xbfe9fdf4f13149de, 0xbfe2aa76e87aeb58, // -0.81225, -0.58331 + 0xbfe9f69e70ac75bc, 0xbfe2b4aa787764c4, // -0.81135, -0.58455 + 0xbfe9ef43ef29af94, 0xbfe2bedb25faf3ea, // -0.81046, -0.5858 + 0xbfe9e7e56dcb45bd, 0xbfe2c908ef734e57, // -0.80956, -0.58704 + 0xbfe9e082edb42472, 0xbfe2d333d34e9bb7, // -0.80866, -0.58828 + 0xbfe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // -0.80775, -0.58952 + 0xbfe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // -0.80685, -0.59076 + 0xbfe9ca438080eadb, 0xbfe2f1a30d86773a, // -0.80594, -0.592 + 0xbfe9c2d110f075c3, 0xbfe2fbc24b441015, // -0.80503, -0.59323 + 0xbfe9bb5aa85f2098, 0xbfe305de9b921a94, // -0.80412, -0.59447 + 0xbfe9b3e047f38741, 0xbfe30ff7fce17035, // -0.80321, -0.5957 + 0xbfe9ac61f0d4e247, 0xbfe31a0e6da35e44, // -0.80229, -0.59693 + 0xbfe9a4dfa42b06b2, 0xbfe32421ec49a620, // -0.80138, -0.59816 + 0xbfe99d59631e65d5, 0xbfe32e3277467d6b, // -0.80046, -0.59939 + 0xbfe995cf2ed80d22, 0xbfe338400d0c8e57, // -0.79954, -0.60062 + 0xbfe98e410881a600, 0xbfe3424aac0ef7d6, // -0.79861, -0.60184 + 0xbfe986aef1457594, 0xbfe34c5252c14de1, // -0.79769, -0.60307 + 0xbfe97f18ea4e5c9e, 0xbfe35656ff9799ae, // -0.79676, -0.60429 + 0xbfe9777ef4c7d742, 0xbfe36058b10659f3, // -0.79584, -0.60551 + 0xbfe96fe111ddfce0, 0xbfe36a576582831b, // -0.79491, -0.60673 + 0xbfe9683f42bd7fe1, 0xbfe374531b817f8d, // -0.79398, -0.60795 + 0xbfe960998893ad8c, 0xbfe37e4bd1792fe2, // -0.79304, -0.60917 + 0xbfe958efe48e6dd7, 0xbfe3884185dfeb22, // -0.79211, -0.61038 + 0xbfe9514257dc4335, 0xbfe39234372c7f04, // -0.79117, -0.6116 + 0xbfe94990e3ac4a6c, 0xbfe39c23e3d63029, // -0.79023, -0.61281 + 0xbfe941db892e3a65, 0xbfe3a6108a54ba58, // -0.78929, -0.61402 + 0xbfe93a22499263fc, 0xbfe3affa292050b9, // -0.78835, -0.61523 + 0xbfe932652609b1cf, 0xbfe3b9e0beb19e18, // -0.7874, -0.61644 + 0xbfe92aa41fc5a815, 0xbfe3c3c44981c517, // -0.78646, -0.61765 + 0xbfe922df37f8646a, 0xbfe3cda4c80a6076, // -0.78551, -0.61885 + 0xbfe91b166fd49da2, 0xbfe3d78238c58343, // -0.78456, -0.62006 + 0xbfe91349c88da398, 0xbfe3e15c9a2db922, // -0.7836, -0.62126 + 0xbfe90b7943575efe, 0xbfe3eb33eabe0680, // -0.78265, -0.62246 + 0xbfe903a4e1665133, 0xbfe3f50828f1e8d2, // -0.78169, -0.62366 + 0xbfe8fbcca3ef940d, 0xbfe3fed9534556d4, // -0.78074, -0.62486 + 0xbfe8f3f08c28d9ac, 0xbfe408a76834c0c0, // -0.77978, -0.62606 + 0xbfe8ec109b486c49, 0xbfe41272663d108c, // -0.77882, -0.62725 + 0xbfe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // -0.77785, -0.62845 + 0xbfe8dc45331698cc, 0xbfe425ff178e6bb1, // -0.77689, -0.62964 + 0xbfe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // -0.77592, -0.63083 + 0xbfe8cc6a75184655, 0xbfe4397f5b2a4380, // -0.77495, -0.63202 + 0xbfe8c47758fa71cb, 0xbfe4433ad0117b1d, // -0.77398, -0.63321 + 0xbfe8bc806b151741, 0xbfe44cf325091dd6, // -0.77301, -0.63439 + 0xbfe8b485aca2a468, 0xbfe456a858917046, // -0.77204, -0.63558 + 0xbfe8ac871ede1d88, 0xbfe4605a692b32a2, // -0.77106, -0.63676 + 0xbfe8a484c3031d50, 0xbfe46a095557a0f1, // -0.77008, -0.63794 + 0xbfe89c7e9a4dd4ab, 0xbfe473b51b987347, // -0.7691, -0.63912 + 0xbfe89474a5fb0a84, 0xbfe47d5dba6fde01, // -0.76812, -0.6403 + 0xbfe88c66e7481ba1, 0xbfe48703306091fe, // -0.76714, -0.64148 + 0xbfe884555f72fa6b, 0xbfe490a57bedbcdf, // -0.76615, -0.64266 + 0xbfe87c400fba2ebf, 0xbfe49a449b9b0938, // -0.76517, -0.64383 + 0xbfe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // -0.76418, -0.645 + 0xbfe86c0a1d9aa195, 0xbfe4ad79516722f0, // -0.76319, -0.64618 + 0xbfe863e97db3d95a, 0xbfe4b70ee48fb869, // -0.7622, -0.64735 + 0xbfe85bc51ae958cc, 0xbfe4c0a145ec0004, // -0.7612, -0.64851 + 0xbfe8539cf67c9029, 0xbfe4ca30740218a3, // -0.76021, -0.64968 + 0xbfe84b7111af83f9, 0xbfe4d3bc6d589f80, // -0.75921, -0.65085 + 0xbfe843416dc4cce2, 0xbfe4dd453076b064, // -0.75821, -0.65201 + 0xbfe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // -0.75721, -0.65317 + 0xbfe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // -0.75621, -0.65433 + 0xbfe82a9c13f545ff, 0xbfe4f9cc25cca486, // -0.7552, -0.65549 + 0xbfe8225d803964e5, 0xbfe503480159ded2, // -0.75419, -0.65665 + 0xbfe81a1b33b57acc, 0xbfe50cc09f59a09b, // -0.75319, -0.65781 + 0xbfe811d52faf94dc, 0xbfe51635fe5601d7, // -0.75218, -0.65896 + 0xbfe8098b756e52fa, 0xbfe51fa81cd99aa6, // -0.75117, -0.66011 + 0xbfe8013e0638e795, 0xbfe52916f96f8388, // -0.75015, -0.66127 + 0xbfe7f8ece3571771, 0xbfe5328292a35596, // -0.74914, -0.66242 + 0xbfe7f0980e113978, 0xbfe53beae7012abe, // -0.74812, -0.66356 + 0xbfe7e83f87b03686, 0xbfe5454ff5159dfb, // -0.7471, -0.66471 + 0xbfe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // -0.74608, -0.66586 + 0xbfe7d7836cc33db2, 0xbfe5581038975137, // -0.74506, -0.667 + 0xbfe7cf1fdacbf179, 0xbfe5616b6b204e6e, // -0.74403, -0.66814 + 0xbfe7c6b89ce2d333, 0xbfe56ac35197649e, // -0.74301, -0.66928 + 0xbfe7be4db453a27c, 0xbfe57417ea8bb75c, // -0.74198, -0.67042 + 0xbfe7b5df226aafb0, 0xbfe57d69348cec9f, // -0.74095, -0.67156 + 0xbfe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // -0.73992, -0.67269 + 0xbfe7a4f707bf97d2, 0xbfe59001d5f723df, // -0.73889, -0.67383 + 0xbfe79c7d8198e56e, 0xbfe599492a81ffbc, // -0.73785, -0.67496 + 0xbfe79400574f55e4, 0xbfe5a28d2a5d7250, // -0.73682, -0.67609 + 0xbfe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // -0.73578, -0.67722 + 0xbfe782fb1b90b35b, 0xbfe5b50b264f7448, // -0.73474, -0.67835 + 0xbfe77a730cbb9100, 0xbfe5be451f8bf980, // -0.7337, -0.67948 + 0xbfe771e75f037261, 0xbfe5c77bbe65018c, // -0.73265, -0.6806 + 0xbfe7695813b9b594, 0xbfe5d0af016ed1d4, // -0.73161, -0.68172 + 0xbfe760c52c304764, 0xbfe5d9dee73e345c, // -0.73056, -0.68285 + 0xbfe7582ea9b9a329, 0xbfe5e30b6e6877f3, // -0.72951, -0.68397 + 0xbfe74f948da8d28d, 0xbfe5ec3495837074, // -0.72846, -0.68508 + 0xbfe746f6d9516d59, 0xbfe5f55a5b2576f8, // -0.72741, -0.6862 + 0xbfe73e558e079942, 0xbfe5fe7cbde56a0f, // -0.72636, -0.68732 + 0xbfe735b0ad2009b2, 0xbfe6079bbc5aadfa, // -0.7253, -0.68843 + 0xbfe72d0837efff97, 0xbfe610b7551d2cde, // -0.72425, -0.68954 + 0xbfe7245c2fcd492a, 0xbfe619cf86c55702, // -0.72319, -0.69065 + 0xbfe71bac960e41bf, 0xbfe622e44fec22ff, // -0.72213, -0.69176 + 0xbfe712f96c09d18d, 0xbfe62bf5af2b0dfd, // -0.72107, -0.69287 + 0xbfe70a42b3176d7a, 0xbfe63503a31c1be8, // -0.72, -0.69397 + 0xbfe701886c8f16e6, 0xbfe63e0e2a59d7aa, // -0.71894, -0.69508 + 0xbfe6f8ca99c95b75, 0xbfe64715437f535b, // -0.71787, -0.69618 + 0xbfe6f0093c1f54de, 0xbfe65018ed28287f, // -0.7168, -0.69728 + 0xbfe6e74454eaa8ae, 0xbfe6591925f0783e, // -0.71573, -0.69838 + 0xbfe6de7be585881d, 0xbfe66215ec74eb91, // -0.71466, -0.69947 + 0xbfe6d5afef4aafcc, 0xbfe66b0f3f52b386, // -0.71358, -0.70057 + 0xbfe6cce07395679f, 0xbfe674051d27896c, // -0.71251, -0.70166 + 0xbfe6c40d73c18275, 0xbfe67cf78491af10, // -0.71143, -0.70275 + 0xbfe6bb36f12b5e06, 0xbfe685e6742feeef, // -0.71035, -0.70385 + 0xbfe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // -0.70927, -0.70493 + 0xbfe6a97f692c82ea, 0xbfe697b9e686941c, // -0.70819, -0.70602 + 0xbfe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // -0.70711, -0.70711 + 0xbfe697b9e686941c, 0xbfe6a97f692c82ea, // -0.70602, -0.70819 + 0xbfe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // -0.70493, -0.70927 + 0xbfe685e6742feeef, 0xbfe6bb36f12b5e06, // -0.70385, -0.71035 + 0xbfe67cf78491af10, 0xbfe6c40d73c18275, // -0.70275, -0.71143 + 0xbfe674051d27896c, 0xbfe6cce07395679f, // -0.70166, -0.71251 + 0xbfe66b0f3f52b386, 0xbfe6d5afef4aafcc, // -0.70057, -0.71358 + 0xbfe66215ec74eb91, 0xbfe6de7be585881d, // -0.69947, -0.71466 + 0xbfe6591925f0783e, 0xbfe6e74454eaa8ae, // -0.69838, -0.71573 + 0xbfe65018ed28287f, 0xbfe6f0093c1f54de, // -0.69728, -0.7168 + 0xbfe64715437f535b, 0xbfe6f8ca99c95b75, // -0.69618, -0.71787 + 0xbfe63e0e2a59d7aa, 0xbfe701886c8f16e6, // -0.69508, -0.71894 + 0xbfe63503a31c1be8, 0xbfe70a42b3176d7a, // -0.69397, -0.72 + 0xbfe62bf5af2b0dfd, 0xbfe712f96c09d18d, // -0.69287, -0.72107 + 0xbfe622e44fec22ff, 0xbfe71bac960e41bf, // -0.69176, -0.72213 + 0xbfe619cf86c55702, 0xbfe7245c2fcd492a, // -0.69065, -0.72319 + 0xbfe610b7551d2cde, 0xbfe72d0837efff97, // -0.68954, -0.72425 + 0xbfe6079bbc5aadfa, 0xbfe735b0ad2009b2, // -0.68843, -0.7253 + 0xbfe5fe7cbde56a0f, 0xbfe73e558e079942, // -0.68732, -0.72636 + 0xbfe5f55a5b2576f8, 0xbfe746f6d9516d59, // -0.6862, -0.72741 + 0xbfe5ec3495837074, 0xbfe74f948da8d28d, // -0.68508, -0.72846 + 0xbfe5e30b6e6877f3, 0xbfe7582ea9b9a329, // -0.68397, -0.72951 + 0xbfe5d9dee73e345c, 0xbfe760c52c304764, // -0.68285, -0.73056 + 0xbfe5d0af016ed1d4, 0xbfe7695813b9b594, // -0.68172, -0.73161 + 0xbfe5c77bbe65018c, 0xbfe771e75f037261, // -0.6806, -0.73265 + 0xbfe5be451f8bf980, 0xbfe77a730cbb9100, // -0.67948, -0.7337 + 0xbfe5b50b264f7448, 0xbfe782fb1b90b35b, // -0.67835, -0.73474 + 0xbfe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // -0.67722, -0.73578 + 0xbfe5a28d2a5d7250, 0xbfe79400574f55e4, // -0.67609, -0.73682 + 0xbfe599492a81ffbc, 0xbfe79c7d8198e56e, // -0.67496, -0.73785 + 0xbfe59001d5f723df, 0xbfe7a4f707bf97d2, // -0.67383, -0.73889 + 0xbfe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // -0.67269, -0.73992 + 0xbfe57d69348cec9f, 0xbfe7b5df226aafb0, // -0.67156, -0.74095 + 0xbfe57417ea8bb75c, 0xbfe7be4db453a27c, // -0.67042, -0.74198 + 0xbfe56ac35197649e, 0xbfe7c6b89ce2d333, // -0.66928, -0.74301 + 0xbfe5616b6b204e6e, 0xbfe7cf1fdacbf179, // -0.66814, -0.74403 + 0xbfe5581038975137, 0xbfe7d7836cc33db2, // -0.667, -0.74506 + 0xbfe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // -0.66586, -0.74608 + 0xbfe5454ff5159dfb, 0xbfe7e83f87b03686, // -0.66471, -0.7471 + 0xbfe53beae7012abe, 0xbfe7f0980e113978, // -0.66356, -0.74812 + 0xbfe5328292a35596, 0xbfe7f8ece3571771, // -0.66242, -0.74914 + 0xbfe52916f96f8388, 0xbfe8013e0638e795, // -0.66127, -0.75015 + 0xbfe51fa81cd99aa6, 0xbfe8098b756e52fa, // -0.66011, -0.75117 + 0xbfe51635fe5601d7, 0xbfe811d52faf94dc, // -0.65896, -0.75218 + 0xbfe50cc09f59a09b, 0xbfe81a1b33b57acc, // -0.65781, -0.75319 + 0xbfe503480159ded2, 0xbfe8225d803964e5, // -0.65665, -0.75419 + 0xbfe4f9cc25cca486, 0xbfe82a9c13f545ff, // -0.65549, -0.7552 + 0xbfe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // -0.65433, -0.75621 + 0xbfe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // -0.65317, -0.75721 + 0xbfe4dd453076b064, 0xbfe843416dc4cce2, // -0.65201, -0.75821 + 0xbfe4d3bc6d589f80, 0xbfe84b7111af83f9, // -0.65085, -0.75921 + 0xbfe4ca30740218a3, 0xbfe8539cf67c9029, // -0.64968, -0.76021 + 0xbfe4c0a145ec0004, 0xbfe85bc51ae958cc, // -0.64851, -0.7612 + 0xbfe4b70ee48fb869, 0xbfe863e97db3d95a, // -0.64735, -0.7622 + 0xbfe4ad79516722f0, 0xbfe86c0a1d9aa195, // -0.64618, -0.76319 + 0xbfe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // -0.645, -0.76418 + 0xbfe49a449b9b0938, 0xbfe87c400fba2ebf, // -0.64383, -0.76517 + 0xbfe490a57bedbcdf, 0xbfe884555f72fa6b, // -0.64266, -0.76615 + 0xbfe48703306091fe, 0xbfe88c66e7481ba1, // -0.64148, -0.76714 + 0xbfe47d5dba6fde01, 0xbfe89474a5fb0a84, // -0.6403, -0.76812 + 0xbfe473b51b987347, 0xbfe89c7e9a4dd4ab, // -0.63912, -0.7691 + 0xbfe46a095557a0f1, 0xbfe8a484c3031d50, // -0.63794, -0.77008 + 0xbfe4605a692b32a2, 0xbfe8ac871ede1d88, // -0.63676, -0.77106 + 0xbfe456a858917046, 0xbfe8b485aca2a468, // -0.63558, -0.77204 + 0xbfe44cf325091dd6, 0xbfe8bc806b151741, // -0.63439, -0.77301 + 0xbfe4433ad0117b1d, 0xbfe8c47758fa71cb, // -0.63321, -0.77398 + 0xbfe4397f5b2a4380, 0xbfe8cc6a75184655, // -0.63202, -0.77495 + 0xbfe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // -0.63083, -0.77592 + 0xbfe425ff178e6bb1, 0xbfe8dc45331698cc, // -0.62964, -0.77689 + 0xbfe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // -0.62845, -0.77785 + 0xbfe41272663d108c, 0xbfe8ec109b486c49, // -0.62725, -0.77882 + 0xbfe408a76834c0c0, 0xbfe8f3f08c28d9ac, // -0.62606, -0.77978 + 0xbfe3fed9534556d4, 0xbfe8fbcca3ef940d, // -0.62486, -0.78074 + 0xbfe3f50828f1e8d2, 0xbfe903a4e1665133, // -0.62366, -0.78169 + 0xbfe3eb33eabe0680, 0xbfe90b7943575efe, // -0.62246, -0.78265 + 0xbfe3e15c9a2db922, 0xbfe91349c88da398, // -0.62126, -0.7836 + 0xbfe3d78238c58343, 0xbfe91b166fd49da2, // -0.62006, -0.78456 + 0xbfe3cda4c80a6076, 0xbfe922df37f8646a, // -0.61885, -0.78551 + 0xbfe3c3c44981c517, 0xbfe92aa41fc5a815, // -0.61765, -0.78646 + 0xbfe3b9e0beb19e18, 0xbfe932652609b1cf, // -0.61644, -0.7874 + 0xbfe3affa292050b9, 0xbfe93a22499263fc, // -0.61523, -0.78835 + 0xbfe3a6108a54ba58, 0xbfe941db892e3a65, // -0.61402, -0.78929 + 0xbfe39c23e3d63029, 0xbfe94990e3ac4a6c, // -0.61281, -0.79023 + 0xbfe39234372c7f04, 0xbfe9514257dc4335, // -0.6116, -0.79117 + 0xbfe3884185dfeb22, 0xbfe958efe48e6dd7, // -0.61038, -0.79211 + 0xbfe37e4bd1792fe2, 0xbfe960998893ad8c, // -0.60917, -0.79304 + 0xbfe374531b817f8d, 0xbfe9683f42bd7fe1, // -0.60795, -0.79398 + 0xbfe36a576582831b, 0xbfe96fe111ddfce0, // -0.60673, -0.79491 + 0xbfe36058b10659f3, 0xbfe9777ef4c7d742, // -0.60551, -0.79584 + 0xbfe35656ff9799ae, 0xbfe97f18ea4e5c9e, // -0.60429, -0.79676 + 0xbfe34c5252c14de1, 0xbfe986aef1457594, // -0.60307, -0.79769 + 0xbfe3424aac0ef7d6, 0xbfe98e410881a600, // -0.60184, -0.79861 + 0xbfe338400d0c8e57, 0xbfe995cf2ed80d22, // -0.60062, -0.79954 + 0xbfe32e3277467d6b, 0xbfe99d59631e65d5, // -0.59939, -0.80046 + 0xbfe32421ec49a620, 0xbfe9a4dfa42b06b2, // -0.59816, -0.80138 + 0xbfe31a0e6da35e44, 0xbfe9ac61f0d4e247, // -0.59693, -0.80229 + 0xbfe30ff7fce17035, 0xbfe9b3e047f38741, // -0.5957, -0.80321 + 0xbfe305de9b921a94, 0xbfe9bb5aa85f2098, // -0.59447, -0.80412 + 0xbfe2fbc24b441015, 0xbfe9c2d110f075c3, // -0.59323, -0.80503 + 0xbfe2f1a30d86773a, 0xbfe9ca438080eadb, // -0.592, -0.80594 + 0xbfe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // -0.59076, -0.80685 + 0xbfe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // -0.58952, -0.80775 + 0xbfe2d333d34e9bb7, 0xbfe9e082edb42472, // -0.58828, -0.80866 + 0xbfe2c908ef734e57, 0xbfe9e7e56dcb45bd, // -0.58704, -0.80956 + 0xbfe2bedb25faf3ea, 0xbfe9ef43ef29af94, // -0.5858, -0.81046 + 0xbfe2b4aa787764c4, 0xbfe9f69e70ac75bc, // -0.58455, -0.81135 + 0xbfe2aa76e87aeb58, 0xbfe9fdf4f13149de, // -0.58331, -0.81225 + 0xbfe2a040779843fb, 0xbfea05476f967bb5, // -0.58206, -0.81314 + 0xbfe2960727629ca8, 0xbfea0c95eabaf937, // -0.58081, -0.81404 + 0xbfe28bcaf96d94ba, 0xbfea13e0617e4ec7, // -0.57956, -0.81493 + 0xbfe2818bef4d3cba, 0xbfea1b26d2c0a75e, // -0.57831, -0.81581 + 0xbfe2774a0a961612, 0xbfea22693d62ccb9, // -0.57706, -0.8167 + 0xbfe26d054cdd12df, 0xbfea29a7a0462782, // -0.57581, -0.81758 + 0xbfe262bdb7b795a2, 0xbfea30e1fa4cbf81, // -0.57455, -0.81847 + 0xbfe258734cbb7110, 0xbfea38184a593bc6, // -0.5733, -0.81935 + 0xbfe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // -0.57204, -0.82023 + 0xbfe243d5fb98ac1f, 0xbfea4678c8119ac8, // -0.57078, -0.8211 + 0xbfe23983189fdfd5, 0xbfea4da2f385e997, // -0.56952, -0.82198 + 0xbfe22f2d662c13e1, 0xbfea54c91090f524, // -0.56826, -0.82285 + 0xbfe224d4e5d5482e, 0xbfea5beb1e188375, // -0.567, -0.82372 + 0xbfe21a799933eb58, 0xbfea63091b02fae2, // -0.56573, -0.82459 + 0xbfe2101b81e0da78, 0xbfea6a230637623b, // -0.56447, -0.82546 + 0xbfe205baa17560d6, 0xbfea7138de9d60f5, // -0.5632, -0.82632 + 0xbfe1fb56f98b37b8, 0xbfea784aa31d3f55, // -0.56193, -0.82718 + 0xbfe1f0f08bbc861b, 0xbfea7f58529fe69d, // -0.56066, -0.82805 + 0xbfe1e68759a3e074, 0xbfea8661ec0ee133, // -0.55939, -0.8289 + 0xbfe1dc1b64dc4872, 0xbfea8d676e545ad2, // -0.55812, -0.82976 + 0xbfe1d1acaf012cc2, 0xbfea9468d85b20ae, // -0.55685, -0.83062 + 0xbfe1c73b39ae68c8, 0xbfea9b66290ea1a3, // -0.55557, -0.83147 + 0xbfe1bcc706804467, 0xbfeaa25f5f5aee60, // -0.55429, -0.83232 + 0xbfe1b250171373be, 0xbfeaa9547a2cb98e, // -0.55302, -0.83317 + 0xbfe1a7d66d0516e6, 0xbfeab045787157ff, // -0.55174, -0.83402 + 0xbfe19d5a09f2b9b8, 0xbfeab7325916c0d4, // -0.55046, -0.83486 + 0xbfe192daef7a5386, 0xbfeabe1b1b0b8dac, // -0.54918, -0.83571 + 0xbfe188591f3a46e5, 0xbfeac4ffbd3efac8, // -0.54789, -0.83655 + 0xbfe17dd49ad16161, 0xbfeacbe03ea0e73b, // -0.54661, -0.83739 + 0xbfe1734d63dedb49, 0xbfead2bc9e21d511, // -0.54532, -0.83822 + 0xbfe168c37c025764, 0xbfead994dab2e979, // -0.54404, -0.83906 + 0xbfe15e36e4dbe2bc, 0xbfeae068f345ecef, // -0.54275, -0.83989 + 0xbfe153a7a00bf453, 0xbfeae738e6cd4b67, // -0.54146, -0.84073 + 0xbfe14915af336ceb, 0xbfeaee04b43c1474, // -0.54017, -0.84155 + 0xbfe13e8113f396c1, 0xbfeaf4cc5a85fb73, // -0.53888, -0.84238 + 0xbfe133e9cfee254e, 0xbfeafb8fd89f57b6, // -0.53759, -0.84321 + 0xbfe1294fe4c5350a, 0xbfeb024f2d7d24a9, // -0.53629, -0.84403 + 0xbfe11eb3541b4b22, 0xbfeb090a58150200, // -0.535, -0.84485 + 0xbfe114141f935545, 0xbfeb0fc1575d33db, // -0.5337, -0.84567 + 0xbfe1097248d0a956, 0xbfeb16742a4ca2f5, // -0.5324, -0.84649 + 0xbfe0fecdd1770537, 0xbfeb1d22cfdadcc6, // -0.5311, -0.84731 + 0xbfe0f426bb2a8e7d, 0xbfeb23cd470013b4, // -0.5298, -0.84812 + 0xbfe0e97d078fd23b, 0xbfeb2a738eb51f33, // -0.5285, -0.84893 + 0xbfe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // -0.5272, -0.84974 + 0xbfe0d421cf03c12b, 0xbfeb37b38bb54c09, // -0.5259, -0.85055 + 0xbfe0c9704d5d898f, 0xbfeb3e4d3ef55712, // -0.52459, -0.85136 + 0xbfe0bebc34ff4646, 0xbfeb44e2beaf0a61, // -0.52328, -0.85216 + 0xbfe0b405878f85ec, 0xbfeb4b7409de7925, // -0.52198, -0.85296 + 0xbfe0a94c46b53d0b, 0xbfeb52011f805c92, // -0.52067, -0.85376 + 0xbfe09e907417c5e1, 0xbfeb5889fe921405, // -0.51936, -0.85456 + 0xbfe093d2115ee018, 0xbfeb5f0ea611a532, // -0.51804, -0.85535 + 0xbfe089112032b08c, 0xbfeb658f14fdbc47, // -0.51673, -0.85615 + 0xbfe07e4da23bc102, 0xbfeb6c0b4a55ac17, // -0.51542, -0.85694 + 0xbfe073879922ffed, 0xbfeb728345196e3e, // -0.5141, -0.85773 + 0xbfe068bf0691c028, 0xbfeb78f70449a34b, // -0.51279, -0.85852 + 0xbfe05df3ec31b8b6, 0xbfeb7f6686e792ea, // -0.51147, -0.8593 + 0xbfe053264bad0483, 0xbfeb85d1cbf52c02, // -0.51015, -0.86009 + 0xbfe0485626ae221a, 0xbfeb8c38d27504e9, // -0.50883, -0.86087 + 0xbfe03d837edff370, 0xbfeb929b996a5b7f, // -0.50751, -0.86165 + 0xbfe032ae55edbd95, 0xbfeb98fa1fd9155e, // -0.50619, -0.86242 + 0xbfe027d6ad83287e, 0xbfeb9f5464c5bffc, // -0.50486, -0.8632 + 0xbfe01cfc874c3eb7, 0xbfeba5aa673590d2, // -0.50354, -0.86397 + 0xbfe0121fe4f56d2c, 0xbfebabfc262e6586, // -0.50221, -0.86474 + 0xbfe00740c82b82e0, 0xbfebb249a0b6c40d, // -0.50089, -0.86551 + 0xbfdff8be6537615e, 0xbfebb892d5d5dad5, // -0.49956, -0.86628 + 0xbfdfe2f64be7120f, 0xbfebbed7c49380ea, // -0.49823, -0.86705 + 0xbfdfcd2947c1ff57, 0xbfebc5186bf8361d, // -0.4969, -0.86781 + 0xbfdfb7575c24d2de, 0xbfebcb54cb0d2327, // -0.49557, -0.86857 + 0xbfdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // -0.49423, -0.86933 + 0xbfdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // -0.4929, -0.87009 + 0xbfdf75c44e26a852, 0xbfebddf02cd2b983, // -0.49156, -0.87084 + 0xbfdf5fdee656cda3, 0xbfebe41b611154c1, // -0.49023, -0.8716 + 0xbfdf49f4a7e97729, 0xbfebea424837de6d, // -0.48889, -0.87235 + 0xbfdf3405963fd068, 0xbfebf064e15377dd, // -0.48755, -0.87309 + 0xbfdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // -0.48621, -0.87384 + 0xbfdf081906bff7fd, 0xbfebfc9d25a1b147, // -0.48487, -0.87459 + 0xbfdef21b8fafd3b5, 0xbfec02b2cef1e641, // -0.48353, -0.87533 + 0xbfdedc1952ef78d5, 0xbfec08c426725549, // -0.48218, -0.87607 + 0xbfdec61253e3c61b, 0xbfec0ed12b3372e9, // -0.48084, -0.87681 + 0xbfdeb00695f25620, 0xbfec14d9dc465e58, // -0.47949, -0.87755 + 0xbfde99f61c817eda, 0xbfec1ade38bce19b, // -0.47815, -0.87828 + 0xbfde83e0eaf85113, 0xbfec20de3fa971b0, // -0.4768, -0.87901 + 0xbfde6dc704be97e2, 0xbfec26d9f01f2eaf, // -0.47545, -0.87974 + 0xbfde57a86d3cd824, 0xbfec2cd14931e3f1, // -0.4741, -0.88047 + 0xbfde418527dc4ffa, 0xbfec32c449f60831, // -0.47275, -0.8812 + 0xbfde2b5d3806f63b, 0xbfec38b2f180bdb1, // -0.4714, -0.88192 + 0xbfde1530a12779f4, 0xbfec3e9d3ee7d262, // -0.47004, -0.88264 + 0xbfddfeff66a941de, 0xbfec44833141c004, // -0.46869, -0.88336 + 0xbfdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // -0.46733, -0.88408 + 0xbfddd28f1481cc58, 0xbfec5042012b6907, // -0.46598, -0.8848 + 0xbfddbc5003b2edf8, 0xbfec561adceb743e, // -0.46462, -0.88551 + 0xbfdda60c5cfa10d8, 0xbfec5bef59fef85a, // -0.46326, -0.88622 + 0xbfdd8fc423c62a25, 0xbfec61bf777fcc48, // -0.4619, -0.88693 + 0xbfdd79775b86e389, 0xbfec678b3488739b, // -0.46054, -0.88764 + 0xbfdd632607ac9aa9, 0xbfec6d5290341eb2, // -0.45918, -0.88835 + 0xbfdd4cd02ba8609c, 0xbfec7315899eaad7, // -0.45781, -0.88905 + 0xbfdd3675caebf962, 0xbfec78d41fe4a267, // -0.45645, -0.88975 + 0xbfdd2016e8e9db5b, 0xbfec7e8e52233cf3, // -0.45508, -0.89045 + 0xbfdd09b389152ec1, 0xbfec84441f785f61, // -0.45372, -0.89115 + 0xbfdcf34baee1cd21, 0xbfec89f587029c13, // -0.45235, -0.89184 + 0xbfdcdcdf5dc440ce, 0xbfec8fa287e13305, // -0.45098, -0.89253 + 0xbfdcc66e9931c45d, 0xbfec954b213411f5, // -0.44961, -0.89322 + 0xbfdcaff964a0421d, 0xbfec9aef521bd480, // -0.44824, -0.89391 + 0xbfdc997fc3865388, 0xbfeca08f19b9c449, // -0.44687, -0.8946 + 0xbfdc8301b95b40c2, 0xbfeca62a772fd919, // -0.4455, -0.89528 + 0xbfdc6c7f4997000a, 0xbfecabc169a0b901, // -0.44412, -0.89597 + 0xbfdc55f877b23537, 0xbfecb153f02fb87d, // -0.44275, -0.89665 + 0xbfdc3f6d47263129, 0xbfecb6e20a00da99, // -0.44137, -0.89732 + 0xbfdc28ddbb6cf145, 0xbfecbc6bb638d10b, // -0.43999, -0.898 + 0xbfdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // -0.43862, -0.89867 + 0xbfdbfbb1a05e0edc, 0xbfecc771c2736c09, // -0.43724, -0.89935 + 0xbfdbe51517ffc0d9, 0xbfecccee20c2de9f, // -0.43586, -0.90002 + 0xbfdbce744262deee, 0xbfecd2660e12c1e6, // -0.43448, -0.90068 + 0xbfdbb7cf2304bd01, 0xbfecd7d9898b32f6, // -0.43309, -0.90135 + 0xbfdba125bd63583e, 0xbfecdd489254fe65, // -0.43171, -0.90201 + 0xbfdb8a7814fd5693, 0xbfece2b32799a060, // -0.43033, -0.90267 + 0xbfdb73c62d520624, 0xbfece819488344ce, // -0.42894, -0.90333 + 0xbfdb5d1009e15cc0, 0xbfeced7af43cc773, // -0.42756, -0.90399 + 0xbfdb4655ae2bf757, 0xbfecf2d829f1b40e, // -0.42617, -0.90464 + 0xbfdb2f971db31972, 0xbfecf830e8ce467b, // -0.42478, -0.9053 + 0xbfdb18d45bf8aca6, 0xbfecfd852fff6ad4, // -0.42339, -0.90595 + 0xbfdb020d6c7f4009, 0xbfed02d4feb2bd92, // -0.422, -0.9066 + 0xbfdaeb4252ca07ab, 0xbfed082054168bac, // -0.42061, -0.90724 + 0xbfdad473125cdc08, 0xbfed0d672f59d2b9, // -0.41922, -0.90789 + 0xbfdabd9faebc3980, 0xbfed12a98fac410c, // -0.41782, -0.90853 + 0xbfdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // -0.41643, -0.90917 + 0xbfda8fec8bf5b166, 0xbfed1d20dc40c15c, // -0.41503, -0.90981 + 0xbfda790cd3dbf31a, 0xbfed2255c6e5a4e1, // -0.41364, -0.91044 + 0xbfda622906a70b63, 0xbfed2786335f52fc, // -0.41224, -0.91107 + 0xbfda4b4127dea1e4, 0xbfed2cb220e0ef9f, // -0.41084, -0.91171 + 0xbfda34553b0afee5, 0xbfed31d98e9e503a, // -0.40944, -0.91234 + 0xbfda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // -0.40804, -0.91296 + 0xbfda067145664d57, 0xbfed3c1ae79f2b4e, // -0.40664, -0.91359 + 0xbfd9ef7943a8ed8a, 0xbfed4134d14dc93a, // -0.40524, -0.91421 + 0xbfd9d87d4207b0ab, 0xbfed464a380e7242, // -0.40384, -0.91483 + 0xbfd9c17d440df9f2, 0xbfed4b5b1b187524, // -0.40243, -0.91545 + 0xbfd9aa794d47c9ee, 0xbfed506779a3d2d9, // -0.40103, -0.91606 + 0xbfd993716141bdfe, 0xbfed556f52e93eb1, // -0.39962, -0.91668 + 0xbfd97c6583890fc2, 0xbfed5a72a6221e73, // -0.39822, -0.91729 + 0xbfd96555b7ab948f, 0xbfed5f7172888a7f, // -0.39681, -0.9179 + 0xbfd94e420137bce3, 0xbfed646bb7574de5, // -0.3954, -0.91851 + 0xbfd9372a63bc93d7, 0xbfed696173c9e68b, // -0.39399, -0.91911 + 0xbfd9200ee2c9be97, 0xbfed6e52a71c8547, // -0.39258, -0.91972 + 0xbfd908ef81ef7bd1, 0xbfed733f508c0dff, // -0.39117, -0.92032 + 0xbfd8f1cc44bea329, 0xbfed78276f5617c6, // -0.38976, -0.92092 + 0xbfd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // -0.38835, -0.92151 + 0xbfd8c37a439f884f, 0xbfed81ea09f38b63, // -0.38693, -0.92211 + 0xbfd8ac4b86d5ed44, 0xbfed86c48445a450, // -0.38552, -0.9227 + 0xbfd89518fbff098e, 0xbfed8b9a70ef9cb4, // -0.3841, -0.92329 + 0xbfd87de2a6aea963, 0xbfed906bcf328d46, // -0.38268, -0.92388 + 0xbfd866a88a792ea0, 0xbfed95389e50429b, // -0.38127, -0.92447 + 0xbfd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // -0.37985, -0.92505 + 0xbfd838290bb359c8, 0xbfed9ec48c26b1f3, // -0.37843, -0.92563 + 0xbfd820e3b04eaac4, 0xbfeda383a9668988, // -0.37701, -0.92621 + 0xbfd8099a9c5c362d, 0xbfeda83e348f613b, // -0.37559, -0.92679 + 0xbfd7f24dd37341e3, 0xbfedacf42ce68ab9, // -0.37416, -0.92736 + 0xbfd7dafd592ba621, 0xbfedb1a591b20c38, // -0.37274, -0.92794 + 0xbfd7c3a9311dcce7, 0xbfedb6526238a09b, // -0.37132, -0.92851 + 0xbfd7ac515ee2b172, 0xbfedbafa9dc1b78d, // -0.36989, -0.92907 + 0xbfd794f5e613dfae, 0xbfedbf9e4395759a, // -0.36847, -0.92964 + 0xbfd77d96ca4b73a6, 0xbfedc43d52fcb453, // -0.36704, -0.93021 + 0xbfd766340f2418f6, 0xbfedc8d7cb410260, // -0.36561, -0.93077 + 0xbfd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // -0.36418, -0.93133 + 0xbfd73763c9261092, 0xbfedd1fef38a915a, // -0.36276, -0.93188 + 0xbfd71ff6458782ec, 0xbfedd68ba2267a25, // -0.36133, -0.93244 + 0xbfd7088530fa459e, 0xbfeddb13b6ccc23d, // -0.3599, -0.93299 + 0xbfd6f1108f1bc9c5, 0xbfeddf9730ca837b, // -0.35846, -0.93354 + 0xbfd6d998638a0cb5, 0xbfede4160f6d8d81, // -0.35703, -0.93409 + 0xbfd6c21cb1e39771, 0xbfede890520465ce, // -0.3556, -0.93464 + 0xbfd6aa9d7dc77e16, 0xbfeded05f7de47da, // -0.35416, -0.93518 + 0xbfd6931acad55f51, 0xbfedf177004b2534, // -0.35273, -0.93573 + 0xbfd67b949cad63ca, 0xbfedf5e36a9ba59c, // -0.35129, -0.93627 + 0xbfd6640af6f03d9e, 0xbfedfa4b3621271d, // -0.34986, -0.9368 + 0xbfd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // -0.34842, -0.93734 + 0xbfd634ed533be58e, 0xbfee030cee1435b8, // -0.34698, -0.93787 + 0xbfd61d595c88c203, 0xbfee0766d9280f54, // -0.34554, -0.9384 + 0xbfd605c1fcc88f63, 0xbfee0bbc22bd8349, // -0.3441, -0.93893 + 0xbfd5ee27379ea693, 0xbfee100cca2980ac, // -0.34266, -0.93946 + 0xbfd5d68910aee686, 0xbfee1458cec1ad83, // -0.34122, -0.93998 + 0xbfd5bee78b9db3b6, 0xbfee18a02fdc66d9, // -0.33978, -0.94051 + 0xbfd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // -0.33833, -0.94103 + 0xbfd58f9a75ab1fdd, 0xbfee212104f686e5, // -0.33689, -0.94154 + 0xbfd577eeec151e47, 0xbfee255a77a63bb8, // -0.33545, -0.94206 + 0xbfd5604012f467b4, 0xbfee298f4439197a, // -0.334, -0.94257 + 0xbfd5488dedeff3be, 0xbfee2dbf6a0911d9, // -0.33255, -0.94308 + 0xbfd530d880af3c24, 0xbfee31eae870ce25, // -0.33111, -0.94359 + 0xbfd5191fceda3c35, 0xbfee3611becbaf69, // -0.32966, -0.9441 + 0xbfd50163dc197047, 0xbfee3a33ec75ce85, // -0.32821, -0.9446 + 0xbfd4e9a4ac15d520, 0xbfee3e5170cbfc46, // -0.32676, -0.94511 + 0xbfd4d1e24278e76a, 0xbfee426a4b2bc17e, // -0.32531, -0.94561 + 0xbfd4ba1ca2eca31c, 0xbfee467e7af35f23, // -0.32386, -0.94611 + 0xbfd4a253d11b82f3, 0xbfee4a8dff81ce5e, // -0.32241, -0.9466 + 0xbfd48a87d0b07fd7, 0xbfee4e98d836c0af, // -0.32096, -0.94709 + 0xbfd472b8a5571054, 0xbfee529f04729ffc, // -0.3195, -0.94759 + 0xbfd45ae652bb2800, 0xbfee56a083968eb1, // -0.31805, -0.94807 + 0xbfd44310dc8936f0, 0xbfee5a9d550467d3, // -0.31659, -0.94856 + 0xbfd42b38466e2928, 0xbfee5e95781ebf1c, // -0.31514, -0.94905 + 0xbfd4135c94176602, 0xbfee6288ec48e112, // -0.31368, -0.94953 + 0xbfd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // -0.31222, -0.95001 + 0xbfd3e39be96ec271, 0xbfee6a61c55d53a7, // -0.31077, -0.95049 + 0xbfd3cbb6f87a146e, 0xbfee6e472911da27, // -0.30931, -0.95096 + 0xbfd3b3cefa0414b7, 0xbfee7227db6a9744, // -0.30785, -0.95144 + 0xbfd39be3f1bc8aef, 0xbfee7603dbce74e9, // -0.30639, -0.95191 + 0xbfd383f5e353b6aa, 0xbfee79db29a5165a, // -0.30493, -0.95238 + 0xbfd36c04d27a4edf, 0xbfee7dadc456d850, // -0.30347, -0.95284 + 0xbfd35410c2e18152, 0xbfee817bab4cd10d, // -0.30201, -0.95331 + 0xbfd33c19b83af207, 0xbfee8544ddf0d075, // -0.30054, -0.95377 + 0xbfd3241fb638baaf, 0xbfee89095bad6025, // -0.29908, -0.95423 + 0xbfd30c22c08d6a13, 0xbfee8cc923edc388, // -0.29762, -0.95469 + 0xbfd2f422daec0386, 0xbfee9084361df7f3, // -0.29615, -0.95514 + 0xbfd2dc200907fe51, 0xbfee943a91aab4b4, // -0.29469, -0.95559 + 0xbfd2c41a4e954520, 0xbfee97ec36016b30, // -0.29322, -0.95605 + 0xbfd2ac11af483572, 0xbfee9b99229046f8, // -0.29175, -0.95649 + 0xbfd294062ed59f05, 0xbfee9f4156c62dda, // -0.29028, -0.95694 + 0xbfd27bf7d0f2c346, 0xbfeea2e4d212c000, // -0.28882, -0.95738 + 0xbfd263e6995554ba, 0xbfeea68393e65800, // -0.28735, -0.95783 + 0xbfd24bd28bb37672, 0xbfeeaa1d9bb20af3, // -0.28588, -0.95827 + 0xbfd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // -0.28441, -0.9587 + 0xbfd21ba1fd3d2623, 0xbfeeb1437af9bb34, // -0.28294, -0.95914 + 0xbfd2038583d727bd, 0xbfeeb4cf515b8811, // -0.28146, -0.95957 + 0xbfd1eb6643499fbb, 0xbfeeb8566b810f2a, // -0.27999, -0.96 + 0xbfd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // -0.27852, -0.96043 + 0xbfd1bb1f7b999480, 0xbfeebf5668eaf2ef, // -0.27705, -0.96086 + 0xbfd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // -0.27557, -0.96128 + 0xbfd18acdc3f4873a, 0xbfeec6436ee60309, // -0.2741, -0.9617 + 0xbfd172a0d7765177, 0xbfeec9b2d3c3bf84, // -0.27262, -0.96212 + 0xbfd15a713a28b9d9, 0xbfeecd1d792c8f10, // -0.27115, -0.96254 + 0xbfd1423eefc69378, 0xbfeed0835e999009, // -0.26967, -0.96295 + 0xbfd12a09fc0b1b12, 0xbfeed3e483849c51, // -0.26819, -0.96337 + 0xbfd111d262b1f677, 0xbfeed740e7684963, // -0.26671, -0.96378 + 0xbfd0f998277733f7, 0xbfeeda9889bfe86a, // -0.26523, -0.96418 + 0xbfd0e15b4e1749cd, 0xbfeeddeb6a078651, // -0.26375, -0.96459 + 0xbfd0c91bda4f158d, 0xbfeee13987bbebdc, // -0.26227, -0.96499 + 0xbfd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // -0.26079, -0.96539 + 0xbfd09895327b465e, 0xbfeee7c77961dc9e, // -0.25931, -0.96579 + 0xbfd0804e05eb661e, 0xbfeeeb074c50a544, // -0.25783, -0.96619 + 0xbfd068044deab002, 0xbfeeee425aa6b09a, // -0.25635, -0.96658 + 0xbfd04fb80e37fdae, 0xbfeef178a3e473c2, // -0.25487, -0.96698 + 0xbfd037694a928cac, 0xbfeef4aa278b2032, // -0.25338, -0.96737 + 0xbfd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // -0.2519, -0.96775 + 0xbfd006c4466e54af, 0xbfeefafedc1ba8b7, // -0.25041, -0.96814 + 0xbfcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // -0.24893, -0.96852 + 0xbfcfac2abeff57ff, 0xbfef014074708ed3, // -0.24744, -0.9689 + 0xbfcf7b7480bd3801, 0xbfef045a14cf738c, // -0.24596, -0.96928 + 0xbfcf4ab9679c9f5c, 0xbfef076eecade0fa, // -0.24447, -0.96966 + 0xbfcf19f97b215f1a, 0xbfef0a7efb9230d7, // -0.24298, -0.97003 + 0xbfcee934c2d006c7, 0xbfef0d8a410379c5, // -0.24149, -0.9704 + 0xbfceb86b462de348, 0xbfef1090bc898f5f, // -0.24, -0.97077 + 0xbfce879d0cc0fdaf, 0xbfef13926dad024e, // -0.23851, -0.97114 + 0xbfce56ca1e101a1b, 0xbfef168f53f7205d, // -0.23702, -0.9715 + 0xbfce25f281a2b684, 0xbfef19876ef1f486, // -0.23553, -0.97187 + 0xbfcdf5163f01099a, 0xbfef1c7abe284708, // -0.23404, -0.97223 + 0xbfcdc4355db40195, 0xbfef1f6941259d7a, // -0.23255, -0.97258 + 0xbfcd934fe5454311, 0xbfef2252f7763ada, // -0.23106, -0.97294 + 0xbfcd6265dd3f27e3, 0xbfef2537e0a71f9f, // -0.22957, -0.97329 + 0xbfcd31774d2cbdee, 0xbfef2817fc4609ce, // -0.22807, -0.97364 + 0xbfcd00843c99c5f9, 0xbfef2af349e17507, // -0.22658, -0.97399 + 0xbfcccf8cb312b286, 0xbfef2dc9c9089a9d, // -0.22508, -0.97434 + 0xbfcc9e90b824a6a9, 0xbfef309b794b719f, // -0.22359, -0.97468 + 0xbfcc6d90535d74dc, 0xbfef33685a3aaef0, // -0.22209, -0.97503 + 0xbfcc3c8b8c4b9dd7, 0xbfef36306b67c556, // -0.2206, -0.97536 + 0xbfcc0b826a7e4f63, 0xbfef38f3ac64e589, // -0.2191, -0.9757 + 0xbfcbda74f5856330, 0xbfef3bb21cc4fe47, // -0.2176, -0.97604 + 0xbfcba96334f15dad, 0xbfef3e6bbc1bbc65, // -0.21611, -0.97637 + 0xbfcb784d30536cda, 0xbfef412089fd8adc, // -0.21461, -0.9767 + 0xbfcb4732ef3d6722, 0xbfef43d085ff92dd, // -0.21311, -0.97703 + 0xbfcb16147941ca2a, 0xbfef467bafb7bbe0, // -0.21161, -0.97735 + 0xbfcae4f1d5f3b9ab, 0xbfef492206bcabb4, // -0.21011, -0.97768 + 0xbfcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // -0.20861, -0.978 + 0xbfca82a025b00451, 0xbfef4e603b0b2f2d, // -0.20711, -0.97832 + 0xbfca517127e3dabc, 0xbfef50f81785c6b9, // -0.20561, -0.97863 + 0xbfca203e1b1831da, 0xbfef538b1faf2d07, // -0.20411, -0.97895 + 0xbfc9ef0706e35a35, 0xbfef56195321c090, // -0.20261, -0.97926 + 0xbfc9bdcbf2dc4366, 0xbfef58a2b1789e84, // -0.2011, -0.97957 + 0xbfc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // -0.1996, -0.97988 + 0xbfc95b49e9b62af9, 0xbfef5da6ed43685d, // -0.1981, -0.98018 + 0xbfc92a0303c8194f, 0xbfef6021c9f148c2, // -0.19659, -0.98048 + 0xbfc8f8b83c69a60a, 0xbfef6297cff75cb0, // -0.19509, -0.98079 + 0xbfc8c7699b34ca7e, 0xbfef6508fef47bd5, // -0.19359, -0.98108 + 0xbfc8961727c41804, 0xbfef677556883cee, // -0.19208, -0.98138 + 0xbfc864c0e9b2b6cf, 0xbfef69dcd652f5de, // -0.19057, -0.98167 + 0xbfc83366e89c64c5, 0xbfef6c3f7df5bbb7, // -0.18907, -0.98196 + 0xbfc802092c1d744b, 0xbfef6e9d4d1262ca, // -0.18756, -0.98225 + 0xbfc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // -0.18606, -0.98254 + 0xbfc79f429f59e11d, 0xbfef734a60446279, // -0.18455, -0.98282 + 0xbfc76dd9de50bf31, 0xbfef7599a3a12077, // -0.18304, -0.98311 + 0xbfc73c6d8055fe0a, 0xbfef77e40d068a90, // -0.18153, -0.98339 + 0xbfc70afd8d08c4ff, 0xbfef7a299c1a322a, // -0.18002, -0.98366 + 0xbfc6d98a0c08c8da, 0xbfef7c6a50826840, // -0.17851, -0.98394 + 0xbfc6a81304f64ab2, 0xbfef7ea629e63d6e, // -0.177, -0.98421 + 0xbfc676987f7216b8, 0xbfef80dd27ed8204, // -0.17549, -0.98448 + 0xbfc6451a831d830d, 0xbfef830f4a40c60c, // -0.17398, -0.98475 + 0xbfc61399179a6e94, 0xbfef853c9089595e, // -0.17247, -0.98501 + 0xbfc5e214448b3fc6, 0xbfef8764fa714ba9, // -0.17096, -0.98528 + 0xbfc5b08c1192e381, 0xbfef898887a36c84, // -0.16945, -0.98554 + 0xbfc57f008654cbde, 0xbfef8ba737cb4b78, // -0.16794, -0.9858 + 0xbfc54d71aa74ef02, 0xbfef8dc10a95380d, // -0.16643, -0.98605 + 0xbfc51bdf8597c5f2, 0xbfef8fd5ffae41db, // -0.16491, -0.98631 + 0xbfc4ea4a1f624b61, 0xbfef91e616c43891, // -0.1634, -0.98656 + 0xbfc4b8b17f79fa88, 0xbfef93f14f85ac08, // -0.16189, -0.98681 + 0xbfc48715ad84cdf5, 0xbfef95f7a9a1ec47, // -0.16037, -0.98706 + 0xbfc45576b1293e5a, 0xbfef97f924c9099b, // -0.15886, -0.9873 + 0xbfc423d4920e4166, 0xbfef99f5c0abd496, // -0.15734, -0.98754 + 0xbfc3f22f57db4893, 0xbfef9bed7cfbde29, // -0.15583, -0.98778 + 0xbfc3c0870a383ff6, 0xbfef9de0596b77a3, // -0.15431, -0.98802 + 0xbfc38edbb0cd8d14, 0xbfef9fce55adb2c8, // -0.1528, -0.98826 + 0xbfc35d2d53440db2, 0xbfefa1b7717661d5, // -0.15128, -0.98849 + 0xbfc32b7bf94516a7, 0xbfefa39bac7a1791, // -0.14976, -0.98872 + 0xbfc2f9c7aa7a72af, 0xbfefa57b066e2754, // -0.14825, -0.98895 + 0xbfc2c8106e8e613a, 0xbfefa7557f08a517, // -0.14673, -0.98918 + 0xbfc296564d2b953e, 0xbfefa92b1600657c, // -0.14521, -0.9894 + 0xbfc264994dfd340a, 0xbfefaafbcb0cfddc, // -0.1437, -0.98962 + 0xbfc232d978aed413, 0xbfefacc79de6c44f, // -0.14218, -0.98984 + 0xbfc20116d4ec7bce, 0xbfefae8e8e46cfbb, // -0.14066, -0.99006 + 0xbfc1cf516a62a077, 0xbfefb0509be6f7db, // -0.13914, -0.99027 + 0xbfc19d8940be24e7, 0xbfefb20dc681d54d, // -0.13762, -0.99049 + 0xbfc16bbe5fac5865, 0xbfefb3c60dd2c199, // -0.1361, -0.9907 + 0xbfc139f0cedaf576, 0xbfefb5797195d741, // -0.13458, -0.9909 + 0xbfc1082095f820b0, 0xbfefb727f187f1c7, // -0.13306, -0.99111 + 0xbfc0d64dbcb26786, 0xbfefb8d18d66adb7, // -0.13154, -0.99131 + 0xbfc0a4784ab8bf1d, 0xbfefba7644f068b5, // -0.13002, -0.99151 + 0xbfc072a047ba831d, 0xbfefbc1617e44186, // -0.1285, -0.99171 + 0xbfc040c5bb67747e, 0xbfefbdb106021816, // -0.12698, -0.99191 + 0xbfc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // -0.12545, -0.9921 + 0xbfbfba124b07ad85, 0xbfefc0d832bf043a, // -0.12393, -0.99229 + 0xbfbf564e56a9730e, 0xbfefc26470e19fd3, // -0.12241, -0.99248 + 0xbfbef2858d27561b, 0xbfefc3ebc935454c, // -0.12089, -0.99267 + 0xbfbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // -0.11937, -0.99285 + 0xbfbe2ae5b8457f77, 0xbfefc6ebc77f0887, // -0.11784, -0.99303 + 0xbfbdc70ecbae9fc8, 0xbfefc8646cfeb721, // -0.11632, -0.99321 + 0xbfbd633347858ce4, 0xbfefc9d82bc2915e, // -0.11479, -0.99339 + 0xbfbcff533b307dc1, 0xbfefcb4703914354, // -0.11327, -0.99356 + 0xbfbc9b6eb6165c42, 0xbfefccb0f4323aa3, // -0.11175, -0.99374 + 0xbfbc3785c79ec2d5, 0xbfefce15fd6da67b, // -0.11022, -0.99391 + 0xbfbbd3987f31fa0e, 0xbfefcf761f0c77a3, // -0.1087, -0.99407 + 0xbfbb6fa6ec38f64c, 0xbfefd0d158d86087, // -0.10717, -0.99424 + 0xbfbb0bb11e1d5559, 0xbfefd227aa9bd53b, // -0.10565, -0.9944 + 0xbfbaa7b724495c04, 0xbfefd37914220b84, // -0.10412, -0.99456 + 0xbfba43b90e27f3c4, 0xbfefd4c59536fae4, // -0.1026, -0.99472 + 0xbfb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // -0.10107, -0.99488 + 0xbfb97bb0caaba56f, 0xbfefd74fdd40abbf, // -0.099544, -0.99503 + 0xbfb917a6bc29b42c, 0xbfefd88da3d12526, // -0.098017, -0.99518 + 0xbfb8b398cf0c38e0, 0xbfefd9c68127c78c, // -0.09649, -0.99533 + 0xbfb84f8712c130a0, 0xbfefdafa7514538c, // -0.094963, -0.99548 + 0xbfb7eb7196b72ee4, 0xbfefdc297f674ba9, // -0.093436, -0.99563 + 0xbfb787586a5d5b21, 0xbfefdd539ff1f456, // -0.091909, -0.99577 + 0xbfb7233b9d236e71, 0xbfefde78d68653fd, // -0.090381, -0.99591 + 0xbfb6bf1b3e79b129, 0xbfefdf9922f73307, // -0.088854, -0.99604 + 0xbfb65af75dd0f87b, 0xbfefe0b485181be3, // -0.087326, -0.99618 + 0xbfb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // -0.085797, -0.99631 + 0xbfb592a554489bc8, 0xbfefe2dc89bbff08, // -0.084269, -0.99644 + 0xbfb52e774a4d4d0a, 0xbfefe3e92be9d886, // -0.08274, -0.99657 + 0xbfb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // -0.081211, -0.9967 + 0xbfb4661179272096, 0xbfefe5f3af2e3940, // -0.079682, -0.99682 + 0xbfb401d9d0e3a507, 0xbfefe6f18ff42c84, // -0.078153, -0.99694 + 0xbfb39d9f12c5a299, 0xbfefe7ea85482d60, // -0.076624, -0.99706 + 0xbfb339614e41ffa5, 0xbfefe8de8f03d75c, // -0.075094, -0.99718 + 0xbfb2d52092ce19f6, 0xbfefe9cdad01883a, // -0.073565, -0.99729 + 0xbfb270dcefdfc45b, 0xbfefeab7df1c6005, // -0.072035, -0.9974 + 0xbfb20c9674ed444c, 0xbfefeb9d2530410f, // -0.070505, -0.99751 + 0xbfb1a84d316d4f8a, 0xbfefec7d7f19cffc, // -0.068974, -0.99762 + 0xbfb1440134d709b2, 0xbfefed58ecb673c4, // -0.067444, -0.99772 + 0xbfb0dfb28ea201e6, 0xbfefee2f6de455ba, // -0.065913, -0.99783 + 0xbfb07b614e463064, 0xbfefef0102826191, // -0.064383, -0.99793 + 0xbfb0170d833bf421, 0xbfefefcdaa704562, // -0.062852, -0.99802 + 0xbfaf656e79f820e0, 0xbfeff095658e71ad, // -0.061321, -0.99812 + 0xbfae9cbd15ff5527, 0xbfeff15833be1965, // -0.05979, -0.99821 + 0xbfadd406f9808ec8, 0xbfeff21614e131ed, // -0.058258, -0.9983 + 0xbfad0b4c436f91d0, 0xbfeff2cf08da7321, // -0.056727, -0.99839 + 0xbfac428d12c0d7e3, 0xbfeff3830f8d575c, // -0.055195, -0.99848 + 0xbfab79c986698b78, 0xbfeff43228de1b77, // -0.053664, -0.99856 + 0xbfaab101bd5f8317, 0xbfeff4dc54b1bed3, // -0.052132, -0.99864 + 0xbfa9e835d6993c87, 0xbfeff58192ee0358, // -0.0506, -0.99872 + 0xbfa91f65f10dd814, 0xbfeff621e3796d7e, // -0.049068, -0.9988 + 0xbfa856922bb513c1, 0xbfeff6bd463b444d, // -0.047535, -0.99887 + 0xbfa78dbaa5874685, 0xbfeff753bb1b9164, // -0.046003, -0.99894 + 0xbfa6c4df7d7d5b84, 0xbfeff7e5420320f9, // -0.044471, -0.99901 + 0xbfa5fc00d290cd43, 0xbfeff871dadb81df, // -0.042938, -0.99908 + 0xbfa5331ec3bba0eb, 0xbfeff8f9858f058b, // -0.041406, -0.99914 + 0xbfa46a396ff86179, 0xbfeff97c4208c014, // -0.039873, -0.9992 + 0xbfa3a150f6421afc, 0xbfeff9fa10348837, // -0.03834, -0.99926 + 0xbfa2d865759455cd, 0xbfeffa72effef75d, // -0.036807, -0.99932 + 0xbfa20f770ceb11c6, 0xbfeffae6e1556998, // -0.035274, -0.99938 + 0xbfa14685db42c17e, 0xbfeffb55e425fdae, // -0.033741, -0.99943 + 0xbfa07d91ff984580, 0xbfeffbbff85f9515, // -0.032208, -0.99948 + 0xbf9f693731d1cf01, 0xbfeffc251df1d3f8, // -0.030675, -0.99953 + 0xbf9dd7458c64ab39, 0xbfeffc8554cd213a, // -0.029142, -0.99958 + 0xbf9c454f4ce53b1c, 0xbfeffce09ce2a679, // -0.027608, -0.99962 + 0xbf9ab354b1504fca, 0xbfeffd36f624500c, // -0.026075, -0.99966 + 0xbf992155f7a3667e, 0xbfeffd886084cd0d, // -0.024541, -0.9997 + 0xbf978f535ddc9f03, 0xbfeffdd4dbf78f52, // -0.023008, -0.99974 + 0xbf95fd4d21fab226, 0xbfeffe1c6870cb77, // -0.021474, -0.99977 + 0xbf946b4381fce81c, 0xbfeffe5f05e578db, // -0.01994, -0.9998 + 0xbf92d936bbe30efd, 0xbfeffe9cb44b51a1, // -0.018407, -0.99983 + 0xbf9147270dad7132, 0xbfeffed57398d2b7, // -0.016873, -0.99986 + 0xbf8f6a296ab997ca, 0xbfefff0943c53bd1, // -0.015339, -0.99988 + 0xbf8c45ffe1e48ad9, 0xbfefff3824c88f6f, // -0.013805, -0.9999 + 0xbf8921d1fcdec784, 0xbfefff62169b92db, // -0.012272, -0.99992 + 0xbf85fda037ac05e0, 0xbfefff871937ce2f, // -0.010738, -0.99994 + 0xbf82d96b0e509703, 0xbfefffa72c978c4f, //-0.0092038, -0.99996 + 0xbf7f6a65f9a2a3c5, 0xbfefffc250b5daef, //-0.0076698, -0.99997 + 0xbf7921f0fe670071, 0xbfefffd8858e8a92, //-0.0061359, -0.99998 + 0xbf72d97822f996bc, 0xbfefffe9cb1e2e8d, //-0.0046019, -0.99999 + 0xbf6921f8becca4ba, 0xbfeffff621621d02, // -0.003068, -1 + 0xbf5921faaee6472d, 0xbfeffffd88586ee6, // -0.001534, -1 + 0x0000000000000000, 0xbff0000000000000, // 0, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, // 0.0046019, -0.99999 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, // 0.0061359, -0.99998 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, // 0.0076698, -0.99997 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, // 0.0092038, -0.99996 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + + +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_16[32] = { + 1.000000000f, 0.000000000f, + 0.923879533f, 0.382683432f, + 0.707106781f, 0.707106781f, + 0.382683432f, 0.923879533f, + 0.000000000f, 1.000000000f, + -0.382683432f, 0.923879533f, + -0.707106781f, 0.707106781f, + -0.923879533f, 0.382683432f, + -1.000000000f, 0.000000000f, + -0.923879533f, -0.382683432f, + -0.707106781f, -0.707106781f, + -0.382683432f, -0.923879533f, + -0.000000000f, -1.000000000f, + 0.382683432f, -0.923879533f, + 0.707106781f, -0.707106781f, + 0.923879533f, -0.382683432f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_32[64] = { + 1.000000000f, 0.000000000f, + 0.980785280f, 0.195090322f, + 0.923879533f, 0.382683432f, + 0.831469612f, 0.555570233f, + 0.707106781f, 0.707106781f, + 0.555570233f, 0.831469612f, + 0.382683432f, 0.923879533f, + 0.195090322f, 0.980785280f, + 0.000000000f, 1.000000000f, + -0.195090322f, 0.980785280f, + -0.382683432f, 0.923879533f, + -0.555570233f, 0.831469612f, + -0.707106781f, 0.707106781f, + -0.831469612f, 0.555570233f, + -0.923879533f, 0.382683432f, + -0.980785280f, 0.195090322f, + -1.000000000f, 0.000000000f, + -0.980785280f, -0.195090322f, + -0.923879533f, -0.382683432f, + -0.831469612f, -0.555570233f, + -0.707106781f, -0.707106781f, + -0.555570233f, -0.831469612f, + -0.382683432f, -0.923879533f, + -0.195090322f, -0.980785280f, + -0.000000000f, -1.000000000f, + 0.195090322f, -0.980785280f, + 0.382683432f, -0.923879533f, + 0.555570233f, -0.831469612f, + 0.707106781f, -0.707106781f, + 0.831469612f, -0.555570233f, + 0.923879533f, -0.382683432f, + 0.980785280f, -0.195090322f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i < N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_64[128] = { + 1.000000000f, 0.000000000f, + 0.995184727f, 0.098017140f, + 0.980785280f, 0.195090322f, + 0.956940336f, 0.290284677f, + 0.923879533f, 0.382683432f, + 0.881921264f, 0.471396737f, + 0.831469612f, 0.555570233f, + 0.773010453f, 0.634393284f, + 0.707106781f, 0.707106781f, + 0.634393284f, 0.773010453f, + 0.555570233f, 0.831469612f, + 0.471396737f, 0.881921264f, + 0.382683432f, 0.923879533f, + 0.290284677f, 0.956940336f, + 0.195090322f, 0.980785280f, + 0.098017140f, 0.995184727f, + 0.000000000f, 1.000000000f, + -0.098017140f, 0.995184727f, + -0.195090322f, 0.980785280f, + -0.290284677f, 0.956940336f, + -0.382683432f, 0.923879533f, + -0.471396737f, 0.881921264f, + -0.555570233f, 0.831469612f, + -0.634393284f, 0.773010453f, + -0.707106781f, 0.707106781f, + -0.773010453f, 0.634393284f, + -0.831469612f, 0.555570233f, + -0.881921264f, 0.471396737f, + -0.923879533f, 0.382683432f, + -0.956940336f, 0.290284677f, + -0.980785280f, 0.195090322f, + -0.995184727f, 0.098017140f, + -1.000000000f, 0.000000000f, + -0.995184727f, -0.098017140f, + -0.980785280f, -0.195090322f, + -0.956940336f, -0.290284677f, + -0.923879533f, -0.382683432f, + -0.881921264f, -0.471396737f, + -0.831469612f, -0.555570233f, + -0.773010453f, -0.634393284f, + -0.707106781f, -0.707106781f, + -0.634393284f, -0.773010453f, + -0.555570233f, -0.831469612f, + -0.471396737f, -0.881921264f, + -0.382683432f, -0.923879533f, + -0.290284677f, -0.956940336f, + -0.195090322f, -0.980785280f, + -0.098017140f, -0.995184727f, + -0.000000000f, -1.000000000f, + 0.098017140f, -0.995184727f, + 0.195090322f, -0.980785280f, + 0.290284677f, -0.956940336f, + 0.382683432f, -0.923879533f, + 0.471396737f, -0.881921264f, + 0.555570233f, -0.831469612f, + 0.634393284f, -0.773010453f, + 0.707106781f, -0.707106781f, + 0.773010453f, -0.634393284f, + 0.831469612f, -0.555570233f, + 0.881921264f, -0.471396737f, + 0.923879533f, -0.382683432f, + 0.956940336f, -0.290284677f, + 0.980785280f, -0.195090322f, + 0.995184727f, -0.098017140f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_128[256] = { + 1.000000000f, 0.000000000f, + 0.998795456f, 0.049067674f, + 0.995184727f, 0.098017140f, + 0.989176510f, 0.146730474f, + 0.980785280f, 0.195090322f, + 0.970031253f, 0.242980180f, + 0.956940336f, 0.290284677f, + 0.941544065f, 0.336889853f, + 0.923879533f, 0.382683432f, + 0.903989293f, 0.427555093f, + 0.881921264f, 0.471396737f, + 0.857728610f, 0.514102744f, + 0.831469612f, 0.555570233f, + 0.803207531f, 0.595699304f, + 0.773010453f, 0.634393284f, + 0.740951125f, 0.671558955f, + 0.707106781f, 0.707106781f, + 0.671558955f, 0.740951125f, + 0.634393284f, 0.773010453f, + 0.595699304f, 0.803207531f, + 0.555570233f, 0.831469612f, + 0.514102744f, 0.857728610f, + 0.471396737f, 0.881921264f, + 0.427555093f, 0.903989293f, + 0.382683432f, 0.923879533f, + 0.336889853f, 0.941544065f, + 0.290284677f, 0.956940336f, + 0.242980180f, 0.970031253f, + 0.195090322f, 0.980785280f, + 0.146730474f, 0.989176510f, + 0.098017140f, 0.995184727f, + 0.049067674f, 0.998795456f, + 0.000000000f, 1.000000000f, + -0.049067674f, 0.998795456f, + -0.098017140f, 0.995184727f, + -0.146730474f, 0.989176510f, + -0.195090322f, 0.980785280f, + -0.242980180f, 0.970031253f, + -0.290284677f, 0.956940336f, + -0.336889853f, 0.941544065f, + -0.382683432f, 0.923879533f, + -0.427555093f, 0.903989293f, + -0.471396737f, 0.881921264f, + -0.514102744f, 0.857728610f, + -0.555570233f, 0.831469612f, + -0.595699304f, 0.803207531f, + -0.634393284f, 0.773010453f, + -0.671558955f, 0.740951125f, + -0.707106781f, 0.707106781f, + -0.740951125f, 0.671558955f, + -0.773010453f, 0.634393284f, + -0.803207531f, 0.595699304f, + -0.831469612f, 0.555570233f, + -0.857728610f, 0.514102744f, + -0.881921264f, 0.471396737f, + -0.903989293f, 0.427555093f, + -0.923879533f, 0.382683432f, + -0.941544065f, 0.336889853f, + -0.956940336f, 0.290284677f, + -0.970031253f, 0.242980180f, + -0.980785280f, 0.195090322f, + -0.989176510f, 0.146730474f, + -0.995184727f, 0.098017140f, + -0.998795456f, 0.049067674f, + -1.000000000f, 0.000000000f, + -0.998795456f, -0.049067674f, + -0.995184727f, -0.098017140f, + -0.989176510f, -0.146730474f, + -0.980785280f, -0.195090322f, + -0.970031253f, -0.242980180f, + -0.956940336f, -0.290284677f, + -0.941544065f, -0.336889853f, + -0.923879533f, -0.382683432f, + -0.903989293f, -0.427555093f, + -0.881921264f, -0.471396737f, + -0.857728610f, -0.514102744f, + -0.831469612f, -0.555570233f, + -0.803207531f, -0.595699304f, + -0.773010453f, -0.634393284f, + -0.740951125f, -0.671558955f, + -0.707106781f, -0.707106781f, + -0.671558955f, -0.740951125f, + -0.634393284f, -0.773010453f, + -0.595699304f, -0.803207531f, + -0.555570233f, -0.831469612f, + -0.514102744f, -0.857728610f, + -0.471396737f, -0.881921264f, + -0.427555093f, -0.903989293f, + -0.382683432f, -0.923879533f, + -0.336889853f, -0.941544065f, + -0.290284677f, -0.956940336f, + -0.242980180f, -0.970031253f, + -0.195090322f, -0.980785280f, + -0.146730474f, -0.989176510f, + -0.098017140f, -0.995184727f, + -0.049067674f, -0.998795456f, + -0.000000000f, -1.000000000f, + 0.049067674f, -0.998795456f, + 0.098017140f, -0.995184727f, + 0.146730474f, -0.989176510f, + 0.195090322f, -0.980785280f, + 0.242980180f, -0.970031253f, + 0.290284677f, -0.956940336f, + 0.336889853f, -0.941544065f, + 0.382683432f, -0.923879533f, + 0.427555093f, -0.903989293f, + 0.471396737f, -0.881921264f, + 0.514102744f, -0.857728610f, + 0.555570233f, -0.831469612f, + 0.595699304f, -0.803207531f, + 0.634393284f, -0.773010453f, + 0.671558955f, -0.740951125f, + 0.707106781f, -0.707106781f, + 0.740951125f, -0.671558955f, + 0.773010453f, -0.634393284f, + 0.803207531f, -0.595699304f, + 0.831469612f, -0.555570233f, + 0.857728610f, -0.514102744f, + 0.881921264f, -0.471396737f, + 0.903989293f, -0.427555093f, + 0.923879533f, -0.382683432f, + 0.941544065f, -0.336889853f, + 0.956940336f, -0.290284677f, + 0.970031253f, -0.242980180f, + 0.980785280f, -0.195090322f, + 0.989176510f, -0.146730474f, + 0.995184727f, -0.098017140f, + 0.998795456f, -0.049067674f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for(i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_256[512] = { + 1.000000000f, 0.000000000f, + 0.999698819f, 0.024541229f, + 0.998795456f, 0.049067674f, + 0.997290457f, 0.073564564f, + 0.995184727f, 0.098017140f, + 0.992479535f, 0.122410675f, + 0.989176510f, 0.146730474f, + 0.985277642f, 0.170961889f, + 0.980785280f, 0.195090322f, + 0.975702130f, 0.219101240f, + 0.970031253f, 0.242980180f, + 0.963776066f, 0.266712757f, + 0.956940336f, 0.290284677f, + 0.949528181f, 0.313681740f, + 0.941544065f, 0.336889853f, + 0.932992799f, 0.359895037f, + 0.923879533f, 0.382683432f, + 0.914209756f, 0.405241314f, + 0.903989293f, 0.427555093f, + 0.893224301f, 0.449611330f, + 0.881921264f, 0.471396737f, + 0.870086991f, 0.492898192f, + 0.857728610f, 0.514102744f, + 0.844853565f, 0.534997620f, + 0.831469612f, 0.555570233f, + 0.817584813f, 0.575808191f, + 0.803207531f, 0.595699304f, + 0.788346428f, 0.615231591f, + 0.773010453f, 0.634393284f, + 0.757208847f, 0.653172843f, + 0.740951125f, 0.671558955f, + 0.724247083f, 0.689540545f, + 0.707106781f, 0.707106781f, + 0.689540545f, 0.724247083f, + 0.671558955f, 0.740951125f, + 0.653172843f, 0.757208847f, + 0.634393284f, 0.773010453f, + 0.615231591f, 0.788346428f, + 0.595699304f, 0.803207531f, + 0.575808191f, 0.817584813f, + 0.555570233f, 0.831469612f, + 0.534997620f, 0.844853565f, + 0.514102744f, 0.857728610f, + 0.492898192f, 0.870086991f, + 0.471396737f, 0.881921264f, + 0.449611330f, 0.893224301f, + 0.427555093f, 0.903989293f, + 0.405241314f, 0.914209756f, + 0.382683432f, 0.923879533f, + 0.359895037f, 0.932992799f, + 0.336889853f, 0.941544065f, + 0.313681740f, 0.949528181f, + 0.290284677f, 0.956940336f, + 0.266712757f, 0.963776066f, + 0.242980180f, 0.970031253f, + 0.219101240f, 0.975702130f, + 0.195090322f, 0.980785280f, + 0.170961889f, 0.985277642f, + 0.146730474f, 0.989176510f, + 0.122410675f, 0.992479535f, + 0.098017140f, 0.995184727f, + 0.073564564f, 0.997290457f, + 0.049067674f, 0.998795456f, + 0.024541229f, 0.999698819f, + 0.000000000f, 1.000000000f, + -0.024541229f, 0.999698819f, + -0.049067674f, 0.998795456f, + -0.073564564f, 0.997290457f, + -0.098017140f, 0.995184727f, + -0.122410675f, 0.992479535f, + -0.146730474f, 0.989176510f, + -0.170961889f, 0.985277642f, + -0.195090322f, 0.980785280f, + -0.219101240f, 0.975702130f, + -0.242980180f, 0.970031253f, + -0.266712757f, 0.963776066f, + -0.290284677f, 0.956940336f, + -0.313681740f, 0.949528181f, + -0.336889853f, 0.941544065f, + -0.359895037f, 0.932992799f, + -0.382683432f, 0.923879533f, + -0.405241314f, 0.914209756f, + -0.427555093f, 0.903989293f, + -0.449611330f, 0.893224301f, + -0.471396737f, 0.881921264f, + -0.492898192f, 0.870086991f, + -0.514102744f, 0.857728610f, + -0.534997620f, 0.844853565f, + -0.555570233f, 0.831469612f, + -0.575808191f, 0.817584813f, + -0.595699304f, 0.803207531f, + -0.615231591f, 0.788346428f, + -0.634393284f, 0.773010453f, + -0.653172843f, 0.757208847f, + -0.671558955f, 0.740951125f, + -0.689540545f, 0.724247083f, + -0.707106781f, 0.707106781f, + -0.724247083f, 0.689540545f, + -0.740951125f, 0.671558955f, + -0.757208847f, 0.653172843f, + -0.773010453f, 0.634393284f, + -0.788346428f, 0.615231591f, + -0.803207531f, 0.595699304f, + -0.817584813f, 0.575808191f, + -0.831469612f, 0.555570233f, + -0.844853565f, 0.534997620f, + -0.857728610f, 0.514102744f, + -0.870086991f, 0.492898192f, + -0.881921264f, 0.471396737f, + -0.893224301f, 0.449611330f, + -0.903989293f, 0.427555093f, + -0.914209756f, 0.405241314f, + -0.923879533f, 0.382683432f, + -0.932992799f, 0.359895037f, + -0.941544065f, 0.336889853f, + -0.949528181f, 0.313681740f, + -0.956940336f, 0.290284677f, + -0.963776066f, 0.266712757f, + -0.970031253f, 0.242980180f, + -0.975702130f, 0.219101240f, + -0.980785280f, 0.195090322f, + -0.985277642f, 0.170961889f, + -0.989176510f, 0.146730474f, + -0.992479535f, 0.122410675f, + -0.995184727f, 0.098017140f, + -0.997290457f, 0.073564564f, + -0.998795456f, 0.049067674f, + -0.999698819f, 0.024541229f, + -1.000000000f, 0.000000000f, + -0.999698819f, -0.024541229f, + -0.998795456f, -0.049067674f, + -0.997290457f, -0.073564564f, + -0.995184727f, -0.098017140f, + -0.992479535f, -0.122410675f, + -0.989176510f, -0.146730474f, + -0.985277642f, -0.170961889f, + -0.980785280f, -0.195090322f, + -0.975702130f, -0.219101240f, + -0.970031253f, -0.242980180f, + -0.963776066f, -0.266712757f, + -0.956940336f, -0.290284677f, + -0.949528181f, -0.313681740f, + -0.941544065f, -0.336889853f, + -0.932992799f, -0.359895037f, + -0.923879533f, -0.382683432f, + -0.914209756f, -0.405241314f, + -0.903989293f, -0.427555093f, + -0.893224301f, -0.449611330f, + -0.881921264f, -0.471396737f, + -0.870086991f, -0.492898192f, + -0.857728610f, -0.514102744f, + -0.844853565f, -0.534997620f, + -0.831469612f, -0.555570233f, + -0.817584813f, -0.575808191f, + -0.803207531f, -0.595699304f, + -0.788346428f, -0.615231591f, + -0.773010453f, -0.634393284f, + -0.757208847f, -0.653172843f, + -0.740951125f, -0.671558955f, + -0.724247083f, -0.689540545f, + -0.707106781f, -0.707106781f, + -0.689540545f, -0.724247083f, + -0.671558955f, -0.740951125f, + -0.653172843f, -0.757208847f, + -0.634393284f, -0.773010453f, + -0.615231591f, -0.788346428f, + -0.595699304f, -0.803207531f, + -0.575808191f, -0.817584813f, + -0.555570233f, -0.831469612f, + -0.534997620f, -0.844853565f, + -0.514102744f, -0.857728610f, + -0.492898192f, -0.870086991f, + -0.471396737f, -0.881921264f, + -0.449611330f, -0.893224301f, + -0.427555093f, -0.903989293f, + -0.405241314f, -0.914209756f, + -0.382683432f, -0.923879533f, + -0.359895037f, -0.932992799f, + -0.336889853f, -0.941544065f, + -0.313681740f, -0.949528181f, + -0.290284677f, -0.956940336f, + -0.266712757f, -0.963776066f, + -0.242980180f, -0.970031253f, + -0.219101240f, -0.975702130f, + -0.195090322f, -0.980785280f, + -0.170961889f, -0.985277642f, + -0.146730474f, -0.989176510f, + -0.122410675f, -0.992479535f, + -0.098017140f, -0.995184727f, + -0.073564564f, -0.997290457f, + -0.049067674f, -0.998795456f, + -0.024541229f, -0.999698819f, + -0.000000000f, -1.000000000f, + 0.024541229f, -0.999698819f, + 0.049067674f, -0.998795456f, + 0.073564564f, -0.997290457f, + 0.098017140f, -0.995184727f, + 0.122410675f, -0.992479535f, + 0.146730474f, -0.989176510f, + 0.170961889f, -0.985277642f, + 0.195090322f, -0.980785280f, + 0.219101240f, -0.975702130f, + 0.242980180f, -0.970031253f, + 0.266712757f, -0.963776066f, + 0.290284677f, -0.956940336f, + 0.313681740f, -0.949528181f, + 0.336889853f, -0.941544065f, + 0.359895037f, -0.932992799f, + 0.382683432f, -0.923879533f, + 0.405241314f, -0.914209756f, + 0.427555093f, -0.903989293f, + 0.449611330f, -0.893224301f, + 0.471396737f, -0.881921264f, + 0.492898192f, -0.870086991f, + 0.514102744f, -0.857728610f, + 0.534997620f, -0.844853565f, + 0.555570233f, -0.831469612f, + 0.575808191f, -0.817584813f, + 0.595699304f, -0.803207531f, + 0.615231591f, -0.788346428f, + 0.634393284f, -0.773010453f, + 0.653172843f, -0.757208847f, + 0.671558955f, -0.740951125f, + 0.689540545f, -0.724247083f, + 0.707106781f, -0.707106781f, + 0.724247083f, -0.689540545f, + 0.740951125f, -0.671558955f, + 0.757208847f, -0.653172843f, + 0.773010453f, -0.634393284f, + 0.788346428f, -0.615231591f, + 0.803207531f, -0.595699304f, + 0.817584813f, -0.575808191f, + 0.831469612f, -0.555570233f, + 0.844853565f, -0.534997620f, + 0.857728610f, -0.514102744f, + 0.870086991f, -0.492898192f, + 0.881921264f, -0.471396737f, + 0.893224301f, -0.449611330f, + 0.903989293f, -0.427555093f, + 0.914209756f, -0.405241314f, + 0.923879533f, -0.382683432f, + 0.932992799f, -0.359895037f, + 0.941544065f, -0.336889853f, + 0.949528181f, -0.313681740f, + 0.956940336f, -0.290284677f, + 0.963776066f, -0.266712757f, + 0.970031253f, -0.242980180f, + 0.975702130f, -0.219101240f, + 0.980785280f, -0.195090322f, + 0.985277642f, -0.170961889f, + 0.989176510f, -0.146730474f, + 0.992479535f, -0.122410675f, + 0.995184727f, -0.098017140f, + 0.997290457f, -0.073564564f, + 0.998795456f, -0.049067674f, + 0.999698819f, -0.024541229f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_512[1024] = { + 1.000000000f, 0.000000000f, + 0.999924702f, 0.012271538f, + 0.999698819f, 0.024541229f, + 0.999322385f, 0.036807223f, + 0.998795456f, 0.049067674f, + 0.998118113f, 0.061320736f, + 0.997290457f, 0.073564564f, + 0.996312612f, 0.085797312f, + 0.995184727f, 0.098017140f, + 0.993906970f, 0.110222207f, + 0.992479535f, 0.122410675f, + 0.990902635f, 0.134580709f, + 0.989176510f, 0.146730474f, + 0.987301418f, 0.158858143f, + 0.985277642f, 0.170961889f, + 0.983105487f, 0.183039888f, + 0.980785280f, 0.195090322f, + 0.978317371f, 0.207111376f, + 0.975702130f, 0.219101240f, + 0.972939952f, 0.231058108f, + 0.970031253f, 0.242980180f, + 0.966976471f, 0.254865660f, + 0.963776066f, 0.266712757f, + 0.960430519f, 0.278519689f, + 0.956940336f, 0.290284677f, + 0.953306040f, 0.302005949f, + 0.949528181f, 0.313681740f, + 0.945607325f, 0.325310292f, + 0.941544065f, 0.336889853f, + 0.937339012f, 0.348418680f, + 0.932992799f, 0.359895037f, + 0.928506080f, 0.371317194f, + 0.923879533f, 0.382683432f, + 0.919113852f, 0.393992040f, + 0.914209756f, 0.405241314f, + 0.909167983f, 0.416429560f, + 0.903989293f, 0.427555093f, + 0.898674466f, 0.438616239f, + 0.893224301f, 0.449611330f, + 0.887639620f, 0.460538711f, + 0.881921264f, 0.471396737f, + 0.876070094f, 0.482183772f, + 0.870086991f, 0.492898192f, + 0.863972856f, 0.503538384f, + 0.857728610f, 0.514102744f, + 0.851355193f, 0.524589683f, + 0.844853565f, 0.534997620f, + 0.838224706f, 0.545324988f, + 0.831469612f, 0.555570233f, + 0.824589303f, 0.565731811f, + 0.817584813f, 0.575808191f, + 0.810457198f, 0.585797857f, + 0.803207531f, 0.595699304f, + 0.795836905f, 0.605511041f, + 0.788346428f, 0.615231591f, + 0.780737229f, 0.624859488f, + 0.773010453f, 0.634393284f, + 0.765167266f, 0.643831543f, + 0.757208847f, 0.653172843f, + 0.749136395f, 0.662415778f, + 0.740951125f, 0.671558955f, + 0.732654272f, 0.680600998f, + 0.724247083f, 0.689540545f, + 0.715730825f, 0.698376249f, + 0.707106781f, 0.707106781f, + 0.698376249f, 0.715730825f, + 0.689540545f, 0.724247083f, + 0.680600998f, 0.732654272f, + 0.671558955f, 0.740951125f, + 0.662415778f, 0.749136395f, + 0.653172843f, 0.757208847f, + 0.643831543f, 0.765167266f, + 0.634393284f, 0.773010453f, + 0.624859488f, 0.780737229f, + 0.615231591f, 0.788346428f, + 0.605511041f, 0.795836905f, + 0.595699304f, 0.803207531f, + 0.585797857f, 0.810457198f, + 0.575808191f, 0.817584813f, + 0.565731811f, 0.824589303f, + 0.555570233f, 0.831469612f, + 0.545324988f, 0.838224706f, + 0.534997620f, 0.844853565f, + 0.524589683f, 0.851355193f, + 0.514102744f, 0.857728610f, + 0.503538384f, 0.863972856f, + 0.492898192f, 0.870086991f, + 0.482183772f, 0.876070094f, + 0.471396737f, 0.881921264f, + 0.460538711f, 0.887639620f, + 0.449611330f, 0.893224301f, + 0.438616239f, 0.898674466f, + 0.427555093f, 0.903989293f, + 0.416429560f, 0.909167983f, + 0.405241314f, 0.914209756f, + 0.393992040f, 0.919113852f, + 0.382683432f, 0.923879533f, + 0.371317194f, 0.928506080f, + 0.359895037f, 0.932992799f, + 0.348418680f, 0.937339012f, + 0.336889853f, 0.941544065f, + 0.325310292f, 0.945607325f, + 0.313681740f, 0.949528181f, + 0.302005949f, 0.953306040f, + 0.290284677f, 0.956940336f, + 0.278519689f, 0.960430519f, + 0.266712757f, 0.963776066f, + 0.254865660f, 0.966976471f, + 0.242980180f, 0.970031253f, + 0.231058108f, 0.972939952f, + 0.219101240f, 0.975702130f, + 0.207111376f, 0.978317371f, + 0.195090322f, 0.980785280f, + 0.183039888f, 0.983105487f, + 0.170961889f, 0.985277642f, + 0.158858143f, 0.987301418f, + 0.146730474f, 0.989176510f, + 0.134580709f, 0.990902635f, + 0.122410675f, 0.992479535f, + 0.110222207f, 0.993906970f, + 0.098017140f, 0.995184727f, + 0.085797312f, 0.996312612f, + 0.073564564f, 0.997290457f, + 0.061320736f, 0.998118113f, + 0.049067674f, 0.998795456f, + 0.036807223f, 0.999322385f, + 0.024541229f, 0.999698819f, + 0.012271538f, 0.999924702f, + 0.000000000f, 1.000000000f, + -0.012271538f, 0.999924702f, + -0.024541229f, 0.999698819f, + -0.036807223f, 0.999322385f, + -0.049067674f, 0.998795456f, + -0.061320736f, 0.998118113f, + -0.073564564f, 0.997290457f, + -0.085797312f, 0.996312612f, + -0.098017140f, 0.995184727f, + -0.110222207f, 0.993906970f, + -0.122410675f, 0.992479535f, + -0.134580709f, 0.990902635f, + -0.146730474f, 0.989176510f, + -0.158858143f, 0.987301418f, + -0.170961889f, 0.985277642f, + -0.183039888f, 0.983105487f, + -0.195090322f, 0.980785280f, + -0.207111376f, 0.978317371f, + -0.219101240f, 0.975702130f, + -0.231058108f, 0.972939952f, + -0.242980180f, 0.970031253f, + -0.254865660f, 0.966976471f, + -0.266712757f, 0.963776066f, + -0.278519689f, 0.960430519f, + -0.290284677f, 0.956940336f, + -0.302005949f, 0.953306040f, + -0.313681740f, 0.949528181f, + -0.325310292f, 0.945607325f, + -0.336889853f, 0.941544065f, + -0.348418680f, 0.937339012f, + -0.359895037f, 0.932992799f, + -0.371317194f, 0.928506080f, + -0.382683432f, 0.923879533f, + -0.393992040f, 0.919113852f, + -0.405241314f, 0.914209756f, + -0.416429560f, 0.909167983f, + -0.427555093f, 0.903989293f, + -0.438616239f, 0.898674466f, + -0.449611330f, 0.893224301f, + -0.460538711f, 0.887639620f, + -0.471396737f, 0.881921264f, + -0.482183772f, 0.876070094f, + -0.492898192f, 0.870086991f, + -0.503538384f, 0.863972856f, + -0.514102744f, 0.857728610f, + -0.524589683f, 0.851355193f, + -0.534997620f, 0.844853565f, + -0.545324988f, 0.838224706f, + -0.555570233f, 0.831469612f, + -0.565731811f, 0.824589303f, + -0.575808191f, 0.817584813f, + -0.585797857f, 0.810457198f, + -0.595699304f, 0.803207531f, + -0.605511041f, 0.795836905f, + -0.615231591f, 0.788346428f, + -0.624859488f, 0.780737229f, + -0.634393284f, 0.773010453f, + -0.643831543f, 0.765167266f, + -0.653172843f, 0.757208847f, + -0.662415778f, 0.749136395f, + -0.671558955f, 0.740951125f, + -0.680600998f, 0.732654272f, + -0.689540545f, 0.724247083f, + -0.698376249f, 0.715730825f, + -0.707106781f, 0.707106781f, + -0.715730825f, 0.698376249f, + -0.724247083f, 0.689540545f, + -0.732654272f, 0.680600998f, + -0.740951125f, 0.671558955f, + -0.749136395f, 0.662415778f, + -0.757208847f, 0.653172843f, + -0.765167266f, 0.643831543f, + -0.773010453f, 0.634393284f, + -0.780737229f, 0.624859488f, + -0.788346428f, 0.615231591f, + -0.795836905f, 0.605511041f, + -0.803207531f, 0.595699304f, + -0.810457198f, 0.585797857f, + -0.817584813f, 0.575808191f, + -0.824589303f, 0.565731811f, + -0.831469612f, 0.555570233f, + -0.838224706f, 0.545324988f, + -0.844853565f, 0.534997620f, + -0.851355193f, 0.524589683f, + -0.857728610f, 0.514102744f, + -0.863972856f, 0.503538384f, + -0.870086991f, 0.492898192f, + -0.876070094f, 0.482183772f, + -0.881921264f, 0.471396737f, + -0.887639620f, 0.460538711f, + -0.893224301f, 0.449611330f, + -0.898674466f, 0.438616239f, + -0.903989293f, 0.427555093f, + -0.909167983f, 0.416429560f, + -0.914209756f, 0.405241314f, + -0.919113852f, 0.393992040f, + -0.923879533f, 0.382683432f, + -0.928506080f, 0.371317194f, + -0.932992799f, 0.359895037f, + -0.937339012f, 0.348418680f, + -0.941544065f, 0.336889853f, + -0.945607325f, 0.325310292f, + -0.949528181f, 0.313681740f, + -0.953306040f, 0.302005949f, + -0.956940336f, 0.290284677f, + -0.960430519f, 0.278519689f, + -0.963776066f, 0.266712757f, + -0.966976471f, 0.254865660f, + -0.970031253f, 0.242980180f, + -0.972939952f, 0.231058108f, + -0.975702130f, 0.219101240f, + -0.978317371f, 0.207111376f, + -0.980785280f, 0.195090322f, + -0.983105487f, 0.183039888f, + -0.985277642f, 0.170961889f, + -0.987301418f, 0.158858143f, + -0.989176510f, 0.146730474f, + -0.990902635f, 0.134580709f, + -0.992479535f, 0.122410675f, + -0.993906970f, 0.110222207f, + -0.995184727f, 0.098017140f, + -0.996312612f, 0.085797312f, + -0.997290457f, 0.073564564f, + -0.998118113f, 0.061320736f, + -0.998795456f, 0.049067674f, + -0.999322385f, 0.036807223f, + -0.999698819f, 0.024541229f, + -0.999924702f, 0.012271538f, + -1.000000000f, 0.000000000f, + -0.999924702f, -0.012271538f, + -0.999698819f, -0.024541229f, + -0.999322385f, -0.036807223f, + -0.998795456f, -0.049067674f, + -0.998118113f, -0.061320736f, + -0.997290457f, -0.073564564f, + -0.996312612f, -0.085797312f, + -0.995184727f, -0.098017140f, + -0.993906970f, -0.110222207f, + -0.992479535f, -0.122410675f, + -0.990902635f, -0.134580709f, + -0.989176510f, -0.146730474f, + -0.987301418f, -0.158858143f, + -0.985277642f, -0.170961889f, + -0.983105487f, -0.183039888f, + -0.980785280f, -0.195090322f, + -0.978317371f, -0.207111376f, + -0.975702130f, -0.219101240f, + -0.972939952f, -0.231058108f, + -0.970031253f, -0.242980180f, + -0.966976471f, -0.254865660f, + -0.963776066f, -0.266712757f, + -0.960430519f, -0.278519689f, + -0.956940336f, -0.290284677f, + -0.953306040f, -0.302005949f, + -0.949528181f, -0.313681740f, + -0.945607325f, -0.325310292f, + -0.941544065f, -0.336889853f, + -0.937339012f, -0.348418680f, + -0.932992799f, -0.359895037f, + -0.928506080f, -0.371317194f, + -0.923879533f, -0.382683432f, + -0.919113852f, -0.393992040f, + -0.914209756f, -0.405241314f, + -0.909167983f, -0.416429560f, + -0.903989293f, -0.427555093f, + -0.898674466f, -0.438616239f, + -0.893224301f, -0.449611330f, + -0.887639620f, -0.460538711f, + -0.881921264f, -0.471396737f, + -0.876070094f, -0.482183772f, + -0.870086991f, -0.492898192f, + -0.863972856f, -0.503538384f, + -0.857728610f, -0.514102744f, + -0.851355193f, -0.524589683f, + -0.844853565f, -0.534997620f, + -0.838224706f, -0.545324988f, + -0.831469612f, -0.555570233f, + -0.824589303f, -0.565731811f, + -0.817584813f, -0.575808191f, + -0.810457198f, -0.585797857f, + -0.803207531f, -0.595699304f, + -0.795836905f, -0.605511041f, + -0.788346428f, -0.615231591f, + -0.780737229f, -0.624859488f, + -0.773010453f, -0.634393284f, + -0.765167266f, -0.643831543f, + -0.757208847f, -0.653172843f, + -0.749136395f, -0.662415778f, + -0.740951125f, -0.671558955f, + -0.732654272f, -0.680600998f, + -0.724247083f, -0.689540545f, + -0.715730825f, -0.698376249f, + -0.707106781f, -0.707106781f, + -0.698376249f, -0.715730825f, + -0.689540545f, -0.724247083f, + -0.680600998f, -0.732654272f, + -0.671558955f, -0.740951125f, + -0.662415778f, -0.749136395f, + -0.653172843f, -0.757208847f, + -0.643831543f, -0.765167266f, + -0.634393284f, -0.773010453f, + -0.624859488f, -0.780737229f, + -0.615231591f, -0.788346428f, + -0.605511041f, -0.795836905f, + -0.595699304f, -0.803207531f, + -0.585797857f, -0.810457198f, + -0.575808191f, -0.817584813f, + -0.565731811f, -0.824589303f, + -0.555570233f, -0.831469612f, + -0.545324988f, -0.838224706f, + -0.534997620f, -0.844853565f, + -0.524589683f, -0.851355193f, + -0.514102744f, -0.857728610f, + -0.503538384f, -0.863972856f, + -0.492898192f, -0.870086991f, + -0.482183772f, -0.876070094f, + -0.471396737f, -0.881921264f, + -0.460538711f, -0.887639620f, + -0.449611330f, -0.893224301f, + -0.438616239f, -0.898674466f, + -0.427555093f, -0.903989293f, + -0.416429560f, -0.909167983f, + -0.405241314f, -0.914209756f, + -0.393992040f, -0.919113852f, + -0.382683432f, -0.923879533f, + -0.371317194f, -0.928506080f, + -0.359895037f, -0.932992799f, + -0.348418680f, -0.937339012f, + -0.336889853f, -0.941544065f, + -0.325310292f, -0.945607325f, + -0.313681740f, -0.949528181f, + -0.302005949f, -0.953306040f, + -0.290284677f, -0.956940336f, + -0.278519689f, -0.960430519f, + -0.266712757f, -0.963776066f, + -0.254865660f, -0.966976471f, + -0.242980180f, -0.970031253f, + -0.231058108f, -0.972939952f, + -0.219101240f, -0.975702130f, + -0.207111376f, -0.978317371f, + -0.195090322f, -0.980785280f, + -0.183039888f, -0.983105487f, + -0.170961889f, -0.985277642f, + -0.158858143f, -0.987301418f, + -0.146730474f, -0.989176510f, + -0.134580709f, -0.990902635f, + -0.122410675f, -0.992479535f, + -0.110222207f, -0.993906970f, + -0.098017140f, -0.995184727f, + -0.085797312f, -0.996312612f, + -0.073564564f, -0.997290457f, + -0.061320736f, -0.998118113f, + -0.049067674f, -0.998795456f, + -0.036807223f, -0.999322385f, + -0.024541229f, -0.999698819f, + -0.012271538f, -0.999924702f, + -0.000000000f, -1.000000000f, + 0.012271538f, -0.999924702f, + 0.024541229f, -0.999698819f, + 0.036807223f, -0.999322385f, + 0.049067674f, -0.998795456f, + 0.061320736f, -0.998118113f, + 0.073564564f, -0.997290457f, + 0.085797312f, -0.996312612f, + 0.098017140f, -0.995184727f, + 0.110222207f, -0.993906970f, + 0.122410675f, -0.992479535f, + 0.134580709f, -0.990902635f, + 0.146730474f, -0.989176510f, + 0.158858143f, -0.987301418f, + 0.170961889f, -0.985277642f, + 0.183039888f, -0.983105487f, + 0.195090322f, -0.980785280f, + 0.207111376f, -0.978317371f, + 0.219101240f, -0.975702130f, + 0.231058108f, -0.972939952f, + 0.242980180f, -0.970031253f, + 0.254865660f, -0.966976471f, + 0.266712757f, -0.963776066f, + 0.278519689f, -0.960430519f, + 0.290284677f, -0.956940336f, + 0.302005949f, -0.953306040f, + 0.313681740f, -0.949528181f, + 0.325310292f, -0.945607325f, + 0.336889853f, -0.941544065f, + 0.348418680f, -0.937339012f, + 0.359895037f, -0.932992799f, + 0.371317194f, -0.928506080f, + 0.382683432f, -0.923879533f, + 0.393992040f, -0.919113852f, + 0.405241314f, -0.914209756f, + 0.416429560f, -0.909167983f, + 0.427555093f, -0.903989293f, + 0.438616239f, -0.898674466f, + 0.449611330f, -0.893224301f, + 0.460538711f, -0.887639620f, + 0.471396737f, -0.881921264f, + 0.482183772f, -0.876070094f, + 0.492898192f, -0.870086991f, + 0.503538384f, -0.863972856f, + 0.514102744f, -0.857728610f, + 0.524589683f, -0.851355193f, + 0.534997620f, -0.844853565f, + 0.545324988f, -0.838224706f, + 0.555570233f, -0.831469612f, + 0.565731811f, -0.824589303f, + 0.575808191f, -0.817584813f, + 0.585797857f, -0.810457198f, + 0.595699304f, -0.803207531f, + 0.605511041f, -0.795836905f, + 0.615231591f, -0.788346428f, + 0.624859488f, -0.780737229f, + 0.634393284f, -0.773010453f, + 0.643831543f, -0.765167266f, + 0.653172843f, -0.757208847f, + 0.662415778f, -0.749136395f, + 0.671558955f, -0.740951125f, + 0.680600998f, -0.732654272f, + 0.689540545f, -0.724247083f, + 0.698376249f, -0.715730825f, + 0.707106781f, -0.707106781f, + 0.715730825f, -0.698376249f, + 0.724247083f, -0.689540545f, + 0.732654272f, -0.680600998f, + 0.740951125f, -0.671558955f, + 0.749136395f, -0.662415778f, + 0.757208847f, -0.653172843f, + 0.765167266f, -0.643831543f, + 0.773010453f, -0.634393284f, + 0.780737229f, -0.624859488f, + 0.788346428f, -0.615231591f, + 0.795836905f, -0.605511041f, + 0.803207531f, -0.595699304f, + 0.810457198f, -0.585797857f, + 0.817584813f, -0.575808191f, + 0.824589303f, -0.565731811f, + 0.831469612f, -0.555570233f, + 0.838224706f, -0.545324988f, + 0.844853565f, -0.534997620f, + 0.851355193f, -0.524589683f, + 0.857728610f, -0.514102744f, + 0.863972856f, -0.503538384f, + 0.870086991f, -0.492898192f, + 0.876070094f, -0.482183772f, + 0.881921264f, -0.471396737f, + 0.887639620f, -0.460538711f, + 0.893224301f, -0.449611330f, + 0.898674466f, -0.438616239f, + 0.903989293f, -0.427555093f, + 0.909167983f, -0.416429560f, + 0.914209756f, -0.405241314f, + 0.919113852f, -0.393992040f, + 0.923879533f, -0.382683432f, + 0.928506080f, -0.371317194f, + 0.932992799f, -0.359895037f, + 0.937339012f, -0.348418680f, + 0.941544065f, -0.336889853f, + 0.945607325f, -0.325310292f, + 0.949528181f, -0.313681740f, + 0.953306040f, -0.302005949f, + 0.956940336f, -0.290284677f, + 0.960430519f, -0.278519689f, + 0.963776066f, -0.266712757f, + 0.966976471f, -0.254865660f, + 0.970031253f, -0.242980180f, + 0.972939952f, -0.231058108f, + 0.975702130f, -0.219101240f, + 0.978317371f, -0.207111376f, + 0.980785280f, -0.195090322f, + 0.983105487f, -0.183039888f, + 0.985277642f, -0.170961889f, + 0.987301418f, -0.158858143f, + 0.989176510f, -0.146730474f, + 0.990902635f, -0.134580709f, + 0.992479535f, -0.122410675f, + 0.993906970f, -0.110222207f, + 0.995184727f, -0.098017140f, + 0.996312612f, -0.085797312f, + 0.997290457f, -0.073564564f, + 0.998118113f, -0.061320736f, + 0.998795456f, -0.049067674f, + 0.999322385f, -0.036807223f, + 0.999698819f, -0.024541229f, + 0.999924702f, -0.012271538f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_1024[2048] = { + 1.000000000f, 0.000000000f, + 0.999981175f, 0.006135885f, + 0.999924702f, 0.012271538f, + 0.999830582f, 0.018406730f, + 0.999698819f, 0.024541229f, + 0.999529418f, 0.030674803f, + 0.999322385f, 0.036807223f, + 0.999077728f, 0.042938257f, + 0.998795456f, 0.049067674f, + 0.998475581f, 0.055195244f, + 0.998118113f, 0.061320736f, + 0.997723067f, 0.067443920f, + 0.997290457f, 0.073564564f, + 0.996820299f, 0.079682438f, + 0.996312612f, 0.085797312f, + 0.995767414f, 0.091908956f, + 0.995184727f, 0.098017140f, + 0.994564571f, 0.104121634f, + 0.993906970f, 0.110222207f, + 0.993211949f, 0.116318631f, + 0.992479535f, 0.122410675f, + 0.991709754f, 0.128498111f, + 0.990902635f, 0.134580709f, + 0.990058210f, 0.140658239f, + 0.989176510f, 0.146730474f, + 0.988257568f, 0.152797185f, + 0.987301418f, 0.158858143f, + 0.986308097f, 0.164913120f, + 0.985277642f, 0.170961889f, + 0.984210092f, 0.177004220f, + 0.983105487f, 0.183039888f, + 0.981963869f, 0.189068664f, + 0.980785280f, 0.195090322f, + 0.979569766f, 0.201104635f, + 0.978317371f, 0.207111376f, + 0.977028143f, 0.213110320f, + 0.975702130f, 0.219101240f, + 0.974339383f, 0.225083911f, + 0.972939952f, 0.231058108f, + 0.971503891f, 0.237023606f, + 0.970031253f, 0.242980180f, + 0.968522094f, 0.248927606f, + 0.966976471f, 0.254865660f, + 0.965394442f, 0.260794118f, + 0.963776066f, 0.266712757f, + 0.962121404f, 0.272621355f, + 0.960430519f, 0.278519689f, + 0.958703475f, 0.284407537f, + 0.956940336f, 0.290284677f, + 0.955141168f, 0.296150888f, + 0.953306040f, 0.302005949f, + 0.951435021f, 0.307849640f, + 0.949528181f, 0.313681740f, + 0.947585591f, 0.319502031f, + 0.945607325f, 0.325310292f, + 0.943593458f, 0.331106306f, + 0.941544065f, 0.336889853f, + 0.939459224f, 0.342660717f, + 0.937339012f, 0.348418680f, + 0.935183510f, 0.354163525f, + 0.932992799f, 0.359895037f, + 0.930766961f, 0.365612998f, + 0.928506080f, 0.371317194f, + 0.926210242f, 0.377007410f, + 0.923879533f, 0.382683432f, + 0.921514039f, 0.388345047f, + 0.919113852f, 0.393992040f, + 0.916679060f, 0.399624200f, + 0.914209756f, 0.405241314f, + 0.911706032f, 0.410843171f, + 0.909167983f, 0.416429560f, + 0.906595705f, 0.422000271f, + 0.903989293f, 0.427555093f, + 0.901348847f, 0.433093819f, + 0.898674466f, 0.438616239f, + 0.895966250f, 0.444122145f, + 0.893224301f, 0.449611330f, + 0.890448723f, 0.455083587f, + 0.887639620f, 0.460538711f, + 0.884797098f, 0.465976496f, + 0.881921264f, 0.471396737f, + 0.879012226f, 0.476799230f, + 0.876070094f, 0.482183772f, + 0.873094978f, 0.487550160f, + 0.870086991f, 0.492898192f, + 0.867046246f, 0.498227667f, + 0.863972856f, 0.503538384f, + 0.860866939f, 0.508830143f, + 0.857728610f, 0.514102744f, + 0.854557988f, 0.519355990f, + 0.851355193f, 0.524589683f, + 0.848120345f, 0.529803625f, + 0.844853565f, 0.534997620f, + 0.841554977f, 0.540171473f, + 0.838224706f, 0.545324988f, + 0.834862875f, 0.550457973f, + 0.831469612f, 0.555570233f, + 0.828045045f, 0.560661576f, + 0.824589303f, 0.565731811f, + 0.821102515f, 0.570780746f, + 0.817584813f, 0.575808191f, + 0.814036330f, 0.580813958f, + 0.810457198f, 0.585797857f, + 0.806847554f, 0.590759702f, + 0.803207531f, 0.595699304f, + 0.799537269f, 0.600616479f, + 0.795836905f, 0.605511041f, + 0.792106577f, 0.610382806f, + 0.788346428f, 0.615231591f, + 0.784556597f, 0.620057212f, + 0.780737229f, 0.624859488f, + 0.776888466f, 0.629638239f, + 0.773010453f, 0.634393284f, + 0.769103338f, 0.639124445f, + 0.765167266f, 0.643831543f, + 0.761202385f, 0.648514401f, + 0.757208847f, 0.653172843f, + 0.753186799f, 0.657806693f, + 0.749136395f, 0.662415778f, + 0.745057785f, 0.666999922f, + 0.740951125f, 0.671558955f, + 0.736816569f, 0.676092704f, + 0.732654272f, 0.680600998f, + 0.728464390f, 0.685083668f, + 0.724247083f, 0.689540545f, + 0.720002508f, 0.693971461f, + 0.715730825f, 0.698376249f, + 0.711432196f, 0.702754744f, + 0.707106781f, 0.707106781f, + 0.702754744f, 0.711432196f, + 0.698376249f, 0.715730825f, + 0.693971461f, 0.720002508f, + 0.689540545f, 0.724247083f, + 0.685083668f, 0.728464390f, + 0.680600998f, 0.732654272f, + 0.676092704f, 0.736816569f, + 0.671558955f, 0.740951125f, + 0.666999922f, 0.745057785f, + 0.662415778f, 0.749136395f, + 0.657806693f, 0.753186799f, + 0.653172843f, 0.757208847f, + 0.648514401f, 0.761202385f, + 0.643831543f, 0.765167266f, + 0.639124445f, 0.769103338f, + 0.634393284f, 0.773010453f, + 0.629638239f, 0.776888466f, + 0.624859488f, 0.780737229f, + 0.620057212f, 0.784556597f, + 0.615231591f, 0.788346428f, + 0.610382806f, 0.792106577f, + 0.605511041f, 0.795836905f, + 0.600616479f, 0.799537269f, + 0.595699304f, 0.803207531f, + 0.590759702f, 0.806847554f, + 0.585797857f, 0.810457198f, + 0.580813958f, 0.814036330f, + 0.575808191f, 0.817584813f, + 0.570780746f, 0.821102515f, + 0.565731811f, 0.824589303f, + 0.560661576f, 0.828045045f, + 0.555570233f, 0.831469612f, + 0.550457973f, 0.834862875f, + 0.545324988f, 0.838224706f, + 0.540171473f, 0.841554977f, + 0.534997620f, 0.844853565f, + 0.529803625f, 0.848120345f, + 0.524589683f, 0.851355193f, + 0.519355990f, 0.854557988f, + 0.514102744f, 0.857728610f, + 0.508830143f, 0.860866939f, + 0.503538384f, 0.863972856f, + 0.498227667f, 0.867046246f, + 0.492898192f, 0.870086991f, + 0.487550160f, 0.873094978f, + 0.482183772f, 0.876070094f, + 0.476799230f, 0.879012226f, + 0.471396737f, 0.881921264f, + 0.465976496f, 0.884797098f, + 0.460538711f, 0.887639620f, + 0.455083587f, 0.890448723f, + 0.449611330f, 0.893224301f, + 0.444122145f, 0.895966250f, + 0.438616239f, 0.898674466f, + 0.433093819f, 0.901348847f, + 0.427555093f, 0.903989293f, + 0.422000271f, 0.906595705f, + 0.416429560f, 0.909167983f, + 0.410843171f, 0.911706032f, + 0.405241314f, 0.914209756f, + 0.399624200f, 0.916679060f, + 0.393992040f, 0.919113852f, + 0.388345047f, 0.921514039f, + 0.382683432f, 0.923879533f, + 0.377007410f, 0.926210242f, + 0.371317194f, 0.928506080f, + 0.365612998f, 0.930766961f, + 0.359895037f, 0.932992799f, + 0.354163525f, 0.935183510f, + 0.348418680f, 0.937339012f, + 0.342660717f, 0.939459224f, + 0.336889853f, 0.941544065f, + 0.331106306f, 0.943593458f, + 0.325310292f, 0.945607325f, + 0.319502031f, 0.947585591f, + 0.313681740f, 0.949528181f, + 0.307849640f, 0.951435021f, + 0.302005949f, 0.953306040f, + 0.296150888f, 0.955141168f, + 0.290284677f, 0.956940336f, + 0.284407537f, 0.958703475f, + 0.278519689f, 0.960430519f, + 0.272621355f, 0.962121404f, + 0.266712757f, 0.963776066f, + 0.260794118f, 0.965394442f, + 0.254865660f, 0.966976471f, + 0.248927606f, 0.968522094f, + 0.242980180f, 0.970031253f, + 0.237023606f, 0.971503891f, + 0.231058108f, 0.972939952f, + 0.225083911f, 0.974339383f, + 0.219101240f, 0.975702130f, + 0.213110320f, 0.977028143f, + 0.207111376f, 0.978317371f, + 0.201104635f, 0.979569766f, + 0.195090322f, 0.980785280f, + 0.189068664f, 0.981963869f, + 0.183039888f, 0.983105487f, + 0.177004220f, 0.984210092f, + 0.170961889f, 0.985277642f, + 0.164913120f, 0.986308097f, + 0.158858143f, 0.987301418f, + 0.152797185f, 0.988257568f, + 0.146730474f, 0.989176510f, + 0.140658239f, 0.990058210f, + 0.134580709f, 0.990902635f, + 0.128498111f, 0.991709754f, + 0.122410675f, 0.992479535f, + 0.116318631f, 0.993211949f, + 0.110222207f, 0.993906970f, + 0.104121634f, 0.994564571f, + 0.098017140f, 0.995184727f, + 0.091908956f, 0.995767414f, + 0.085797312f, 0.996312612f, + 0.079682438f, 0.996820299f, + 0.073564564f, 0.997290457f, + 0.067443920f, 0.997723067f, + 0.061320736f, 0.998118113f, + 0.055195244f, 0.998475581f, + 0.049067674f, 0.998795456f, + 0.042938257f, 0.999077728f, + 0.036807223f, 0.999322385f, + 0.030674803f, 0.999529418f, + 0.024541229f, 0.999698819f, + 0.018406730f, 0.999830582f, + 0.012271538f, 0.999924702f, + 0.006135885f, 0.999981175f, + 0.000000000f, 1.000000000f, + -0.006135885f, 0.999981175f, + -0.012271538f, 0.999924702f, + -0.018406730f, 0.999830582f, + -0.024541229f, 0.999698819f, + -0.030674803f, 0.999529418f, + -0.036807223f, 0.999322385f, + -0.042938257f, 0.999077728f, + -0.049067674f, 0.998795456f, + -0.055195244f, 0.998475581f, + -0.061320736f, 0.998118113f, + -0.067443920f, 0.997723067f, + -0.073564564f, 0.997290457f, + -0.079682438f, 0.996820299f, + -0.085797312f, 0.996312612f, + -0.091908956f, 0.995767414f, + -0.098017140f, 0.995184727f, + -0.104121634f, 0.994564571f, + -0.110222207f, 0.993906970f, + -0.116318631f, 0.993211949f, + -0.122410675f, 0.992479535f, + -0.128498111f, 0.991709754f, + -0.134580709f, 0.990902635f, + -0.140658239f, 0.990058210f, + -0.146730474f, 0.989176510f, + -0.152797185f, 0.988257568f, + -0.158858143f, 0.987301418f, + -0.164913120f, 0.986308097f, + -0.170961889f, 0.985277642f, + -0.177004220f, 0.984210092f, + -0.183039888f, 0.983105487f, + -0.189068664f, 0.981963869f, + -0.195090322f, 0.980785280f, + -0.201104635f, 0.979569766f, + -0.207111376f, 0.978317371f, + -0.213110320f, 0.977028143f, + -0.219101240f, 0.975702130f, + -0.225083911f, 0.974339383f, + -0.231058108f, 0.972939952f, + -0.237023606f, 0.971503891f, + -0.242980180f, 0.970031253f, + -0.248927606f, 0.968522094f, + -0.254865660f, 0.966976471f, + -0.260794118f, 0.965394442f, + -0.266712757f, 0.963776066f, + -0.272621355f, 0.962121404f, + -0.278519689f, 0.960430519f, + -0.284407537f, 0.958703475f, + -0.290284677f, 0.956940336f, + -0.296150888f, 0.955141168f, + -0.302005949f, 0.953306040f, + -0.307849640f, 0.951435021f, + -0.313681740f, 0.949528181f, + -0.319502031f, 0.947585591f, + -0.325310292f, 0.945607325f, + -0.331106306f, 0.943593458f, + -0.336889853f, 0.941544065f, + -0.342660717f, 0.939459224f, + -0.348418680f, 0.937339012f, + -0.354163525f, 0.935183510f, + -0.359895037f, 0.932992799f, + -0.365612998f, 0.930766961f, + -0.371317194f, 0.928506080f, + -0.377007410f, 0.926210242f, + -0.382683432f, 0.923879533f, + -0.388345047f, 0.921514039f, + -0.393992040f, 0.919113852f, + -0.399624200f, 0.916679060f, + -0.405241314f, 0.914209756f, + -0.410843171f, 0.911706032f, + -0.416429560f, 0.909167983f, + -0.422000271f, 0.906595705f, + -0.427555093f, 0.903989293f, + -0.433093819f, 0.901348847f, + -0.438616239f, 0.898674466f, + -0.444122145f, 0.895966250f, + -0.449611330f, 0.893224301f, + -0.455083587f, 0.890448723f, + -0.460538711f, 0.887639620f, + -0.465976496f, 0.884797098f, + -0.471396737f, 0.881921264f, + -0.476799230f, 0.879012226f, + -0.482183772f, 0.876070094f, + -0.487550160f, 0.873094978f, + -0.492898192f, 0.870086991f, + -0.498227667f, 0.867046246f, + -0.503538384f, 0.863972856f, + -0.508830143f, 0.860866939f, + -0.514102744f, 0.857728610f, + -0.519355990f, 0.854557988f, + -0.524589683f, 0.851355193f, + -0.529803625f, 0.848120345f, + -0.534997620f, 0.844853565f, + -0.540171473f, 0.841554977f, + -0.545324988f, 0.838224706f, + -0.550457973f, 0.834862875f, + -0.555570233f, 0.831469612f, + -0.560661576f, 0.828045045f, + -0.565731811f, 0.824589303f, + -0.570780746f, 0.821102515f, + -0.575808191f, 0.817584813f, + -0.580813958f, 0.814036330f, + -0.585797857f, 0.810457198f, + -0.590759702f, 0.806847554f, + -0.595699304f, 0.803207531f, + -0.600616479f, 0.799537269f, + -0.605511041f, 0.795836905f, + -0.610382806f, 0.792106577f, + -0.615231591f, 0.788346428f, + -0.620057212f, 0.784556597f, + -0.624859488f, 0.780737229f, + -0.629638239f, 0.776888466f, + -0.634393284f, 0.773010453f, + -0.639124445f, 0.769103338f, + -0.643831543f, 0.765167266f, + -0.648514401f, 0.761202385f, + -0.653172843f, 0.757208847f, + -0.657806693f, 0.753186799f, + -0.662415778f, 0.749136395f, + -0.666999922f, 0.745057785f, + -0.671558955f, 0.740951125f, + -0.676092704f, 0.736816569f, + -0.680600998f, 0.732654272f, + -0.685083668f, 0.728464390f, + -0.689540545f, 0.724247083f, + -0.693971461f, 0.720002508f, + -0.698376249f, 0.715730825f, + -0.702754744f, 0.711432196f, + -0.707106781f, 0.707106781f, + -0.711432196f, 0.702754744f, + -0.715730825f, 0.698376249f, + -0.720002508f, 0.693971461f, + -0.724247083f, 0.689540545f, + -0.728464390f, 0.685083668f, + -0.732654272f, 0.680600998f, + -0.736816569f, 0.676092704f, + -0.740951125f, 0.671558955f, + -0.745057785f, 0.666999922f, + -0.749136395f, 0.662415778f, + -0.753186799f, 0.657806693f, + -0.757208847f, 0.653172843f, + -0.761202385f, 0.648514401f, + -0.765167266f, 0.643831543f, + -0.769103338f, 0.639124445f, + -0.773010453f, 0.634393284f, + -0.776888466f, 0.629638239f, + -0.780737229f, 0.624859488f, + -0.784556597f, 0.620057212f, + -0.788346428f, 0.615231591f, + -0.792106577f, 0.610382806f, + -0.795836905f, 0.605511041f, + -0.799537269f, 0.600616479f, + -0.803207531f, 0.595699304f, + -0.806847554f, 0.590759702f, + -0.810457198f, 0.585797857f, + -0.814036330f, 0.580813958f, + -0.817584813f, 0.575808191f, + -0.821102515f, 0.570780746f, + -0.824589303f, 0.565731811f, + -0.828045045f, 0.560661576f, + -0.831469612f, 0.555570233f, + -0.834862875f, 0.550457973f, + -0.838224706f, 0.545324988f, + -0.841554977f, 0.540171473f, + -0.844853565f, 0.534997620f, + -0.848120345f, 0.529803625f, + -0.851355193f, 0.524589683f, + -0.854557988f, 0.519355990f, + -0.857728610f, 0.514102744f, + -0.860866939f, 0.508830143f, + -0.863972856f, 0.503538384f, + -0.867046246f, 0.498227667f, + -0.870086991f, 0.492898192f, + -0.873094978f, 0.487550160f, + -0.876070094f, 0.482183772f, + -0.879012226f, 0.476799230f, + -0.881921264f, 0.471396737f, + -0.884797098f, 0.465976496f, + -0.887639620f, 0.460538711f, + -0.890448723f, 0.455083587f, + -0.893224301f, 0.449611330f, + -0.895966250f, 0.444122145f, + -0.898674466f, 0.438616239f, + -0.901348847f, 0.433093819f, + -0.903989293f, 0.427555093f, + -0.906595705f, 0.422000271f, + -0.909167983f, 0.416429560f, + -0.911706032f, 0.410843171f, + -0.914209756f, 0.405241314f, + -0.916679060f, 0.399624200f, + -0.919113852f, 0.393992040f, + -0.921514039f, 0.388345047f, + -0.923879533f, 0.382683432f, + -0.926210242f, 0.377007410f, + -0.928506080f, 0.371317194f, + -0.930766961f, 0.365612998f, + -0.932992799f, 0.359895037f, + -0.935183510f, 0.354163525f, + -0.937339012f, 0.348418680f, + -0.939459224f, 0.342660717f, + -0.941544065f, 0.336889853f, + -0.943593458f, 0.331106306f, + -0.945607325f, 0.325310292f, + -0.947585591f, 0.319502031f, + -0.949528181f, 0.313681740f, + -0.951435021f, 0.307849640f, + -0.953306040f, 0.302005949f, + -0.955141168f, 0.296150888f, + -0.956940336f, 0.290284677f, + -0.958703475f, 0.284407537f, + -0.960430519f, 0.278519689f, + -0.962121404f, 0.272621355f, + -0.963776066f, 0.266712757f, + -0.965394442f, 0.260794118f, + -0.966976471f, 0.254865660f, + -0.968522094f, 0.248927606f, + -0.970031253f, 0.242980180f, + -0.971503891f, 0.237023606f, + -0.972939952f, 0.231058108f, + -0.974339383f, 0.225083911f, + -0.975702130f, 0.219101240f, + -0.977028143f, 0.213110320f, + -0.978317371f, 0.207111376f, + -0.979569766f, 0.201104635f, + -0.980785280f, 0.195090322f, + -0.981963869f, 0.189068664f, + -0.983105487f, 0.183039888f, + -0.984210092f, 0.177004220f, + -0.985277642f, 0.170961889f, + -0.986308097f, 0.164913120f, + -0.987301418f, 0.158858143f, + -0.988257568f, 0.152797185f, + -0.989176510f, 0.146730474f, + -0.990058210f, 0.140658239f, + -0.990902635f, 0.134580709f, + -0.991709754f, 0.128498111f, + -0.992479535f, 0.122410675f, + -0.993211949f, 0.116318631f, + -0.993906970f, 0.110222207f, + -0.994564571f, 0.104121634f, + -0.995184727f, 0.098017140f, + -0.995767414f, 0.091908956f, + -0.996312612f, 0.085797312f, + -0.996820299f, 0.079682438f, + -0.997290457f, 0.073564564f, + -0.997723067f, 0.067443920f, + -0.998118113f, 0.061320736f, + -0.998475581f, 0.055195244f, + -0.998795456f, 0.049067674f, + -0.999077728f, 0.042938257f, + -0.999322385f, 0.036807223f, + -0.999529418f, 0.030674803f, + -0.999698819f, 0.024541229f, + -0.999830582f, 0.018406730f, + -0.999924702f, 0.012271538f, + -0.999981175f, 0.006135885f, + -1.000000000f, 0.000000000f, + -0.999981175f, -0.006135885f, + -0.999924702f, -0.012271538f, + -0.999830582f, -0.018406730f, + -0.999698819f, -0.024541229f, + -0.999529418f, -0.030674803f, + -0.999322385f, -0.036807223f, + -0.999077728f, -0.042938257f, + -0.998795456f, -0.049067674f, + -0.998475581f, -0.055195244f, + -0.998118113f, -0.061320736f, + -0.997723067f, -0.067443920f, + -0.997290457f, -0.073564564f, + -0.996820299f, -0.079682438f, + -0.996312612f, -0.085797312f, + -0.995767414f, -0.091908956f, + -0.995184727f, -0.098017140f, + -0.994564571f, -0.104121634f, + -0.993906970f, -0.110222207f, + -0.993211949f, -0.116318631f, + -0.992479535f, -0.122410675f, + -0.991709754f, -0.128498111f, + -0.990902635f, -0.134580709f, + -0.990058210f, -0.140658239f, + -0.989176510f, -0.146730474f, + -0.988257568f, -0.152797185f, + -0.987301418f, -0.158858143f, + -0.986308097f, -0.164913120f, + -0.985277642f, -0.170961889f, + -0.984210092f, -0.177004220f, + -0.983105487f, -0.183039888f, + -0.981963869f, -0.189068664f, + -0.980785280f, -0.195090322f, + -0.979569766f, -0.201104635f, + -0.978317371f, -0.207111376f, + -0.977028143f, -0.213110320f, + -0.975702130f, -0.219101240f, + -0.974339383f, -0.225083911f, + -0.972939952f, -0.231058108f, + -0.971503891f, -0.237023606f, + -0.970031253f, -0.242980180f, + -0.968522094f, -0.248927606f, + -0.966976471f, -0.254865660f, + -0.965394442f, -0.260794118f, + -0.963776066f, -0.266712757f, + -0.962121404f, -0.272621355f, + -0.960430519f, -0.278519689f, + -0.958703475f, -0.284407537f, + -0.956940336f, -0.290284677f, + -0.955141168f, -0.296150888f, + -0.953306040f, -0.302005949f, + -0.951435021f, -0.307849640f, + -0.949528181f, -0.313681740f, + -0.947585591f, -0.319502031f, + -0.945607325f, -0.325310292f, + -0.943593458f, -0.331106306f, + -0.941544065f, -0.336889853f, + -0.939459224f, -0.342660717f, + -0.937339012f, -0.348418680f, + -0.935183510f, -0.354163525f, + -0.932992799f, -0.359895037f, + -0.930766961f, -0.365612998f, + -0.928506080f, -0.371317194f, + -0.926210242f, -0.377007410f, + -0.923879533f, -0.382683432f, + -0.921514039f, -0.388345047f, + -0.919113852f, -0.393992040f, + -0.916679060f, -0.399624200f, + -0.914209756f, -0.405241314f, + -0.911706032f, -0.410843171f, + -0.909167983f, -0.416429560f, + -0.906595705f, -0.422000271f, + -0.903989293f, -0.427555093f, + -0.901348847f, -0.433093819f, + -0.898674466f, -0.438616239f, + -0.895966250f, -0.444122145f, + -0.893224301f, -0.449611330f, + -0.890448723f, -0.455083587f, + -0.887639620f, -0.460538711f, + -0.884797098f, -0.465976496f, + -0.881921264f, -0.471396737f, + -0.879012226f, -0.476799230f, + -0.876070094f, -0.482183772f, + -0.873094978f, -0.487550160f, + -0.870086991f, -0.492898192f, + -0.867046246f, -0.498227667f, + -0.863972856f, -0.503538384f, + -0.860866939f, -0.508830143f, + -0.857728610f, -0.514102744f, + -0.854557988f, -0.519355990f, + -0.851355193f, -0.524589683f, + -0.848120345f, -0.529803625f, + -0.844853565f, -0.534997620f, + -0.841554977f, -0.540171473f, + -0.838224706f, -0.545324988f, + -0.834862875f, -0.550457973f, + -0.831469612f, -0.555570233f, + -0.828045045f, -0.560661576f, + -0.824589303f, -0.565731811f, + -0.821102515f, -0.570780746f, + -0.817584813f, -0.575808191f, + -0.814036330f, -0.580813958f, + -0.810457198f, -0.585797857f, + -0.806847554f, -0.590759702f, + -0.803207531f, -0.595699304f, + -0.799537269f, -0.600616479f, + -0.795836905f, -0.605511041f, + -0.792106577f, -0.610382806f, + -0.788346428f, -0.615231591f, + -0.784556597f, -0.620057212f, + -0.780737229f, -0.624859488f, + -0.776888466f, -0.629638239f, + -0.773010453f, -0.634393284f, + -0.769103338f, -0.639124445f, + -0.765167266f, -0.643831543f, + -0.761202385f, -0.648514401f, + -0.757208847f, -0.653172843f, + -0.753186799f, -0.657806693f, + -0.749136395f, -0.662415778f, + -0.745057785f, -0.666999922f, + -0.740951125f, -0.671558955f, + -0.736816569f, -0.676092704f, + -0.732654272f, -0.680600998f, + -0.728464390f, -0.685083668f, + -0.724247083f, -0.689540545f, + -0.720002508f, -0.693971461f, + -0.715730825f, -0.698376249f, + -0.711432196f, -0.702754744f, + -0.707106781f, -0.707106781f, + -0.702754744f, -0.711432196f, + -0.698376249f, -0.715730825f, + -0.693971461f, -0.720002508f, + -0.689540545f, -0.724247083f, + -0.685083668f, -0.728464390f, + -0.680600998f, -0.732654272f, + -0.676092704f, -0.736816569f, + -0.671558955f, -0.740951125f, + -0.666999922f, -0.745057785f, + -0.662415778f, -0.749136395f, + -0.657806693f, -0.753186799f, + -0.653172843f, -0.757208847f, + -0.648514401f, -0.761202385f, + -0.643831543f, -0.765167266f, + -0.639124445f, -0.769103338f, + -0.634393284f, -0.773010453f, + -0.629638239f, -0.776888466f, + -0.624859488f, -0.780737229f, + -0.620057212f, -0.784556597f, + -0.615231591f, -0.788346428f, + -0.610382806f, -0.792106577f, + -0.605511041f, -0.795836905f, + -0.600616479f, -0.799537269f, + -0.595699304f, -0.803207531f, + -0.590759702f, -0.806847554f, + -0.585797857f, -0.810457198f, + -0.580813958f, -0.814036330f, + -0.575808191f, -0.817584813f, + -0.570780746f, -0.821102515f, + -0.565731811f, -0.824589303f, + -0.560661576f, -0.828045045f, + -0.555570233f, -0.831469612f, + -0.550457973f, -0.834862875f, + -0.545324988f, -0.838224706f, + -0.540171473f, -0.841554977f, + -0.534997620f, -0.844853565f, + -0.529803625f, -0.848120345f, + -0.524589683f, -0.851355193f, + -0.519355990f, -0.854557988f, + -0.514102744f, -0.857728610f, + -0.508830143f, -0.860866939f, + -0.503538384f, -0.863972856f, + -0.498227667f, -0.867046246f, + -0.492898192f, -0.870086991f, + -0.487550160f, -0.873094978f, + -0.482183772f, -0.876070094f, + -0.476799230f, -0.879012226f, + -0.471396737f, -0.881921264f, + -0.465976496f, -0.884797098f, + -0.460538711f, -0.887639620f, + -0.455083587f, -0.890448723f, + -0.449611330f, -0.893224301f, + -0.444122145f, -0.895966250f, + -0.438616239f, -0.898674466f, + -0.433093819f, -0.901348847f, + -0.427555093f, -0.903989293f, + -0.422000271f, -0.906595705f, + -0.416429560f, -0.909167983f, + -0.410843171f, -0.911706032f, + -0.405241314f, -0.914209756f, + -0.399624200f, -0.916679060f, + -0.393992040f, -0.919113852f, + -0.388345047f, -0.921514039f, + -0.382683432f, -0.923879533f, + -0.377007410f, -0.926210242f, + -0.371317194f, -0.928506080f, + -0.365612998f, -0.930766961f, + -0.359895037f, -0.932992799f, + -0.354163525f, -0.935183510f, + -0.348418680f, -0.937339012f, + -0.342660717f, -0.939459224f, + -0.336889853f, -0.941544065f, + -0.331106306f, -0.943593458f, + -0.325310292f, -0.945607325f, + -0.319502031f, -0.947585591f, + -0.313681740f, -0.949528181f, + -0.307849640f, -0.951435021f, + -0.302005949f, -0.953306040f, + -0.296150888f, -0.955141168f, + -0.290284677f, -0.956940336f, + -0.284407537f, -0.958703475f, + -0.278519689f, -0.960430519f, + -0.272621355f, -0.962121404f, + -0.266712757f, -0.963776066f, + -0.260794118f, -0.965394442f, + -0.254865660f, -0.966976471f, + -0.248927606f, -0.968522094f, + -0.242980180f, -0.970031253f, + -0.237023606f, -0.971503891f, + -0.231058108f, -0.972939952f, + -0.225083911f, -0.974339383f, + -0.219101240f, -0.975702130f, + -0.213110320f, -0.977028143f, + -0.207111376f, -0.978317371f, + -0.201104635f, -0.979569766f, + -0.195090322f, -0.980785280f, + -0.189068664f, -0.981963869f, + -0.183039888f, -0.983105487f, + -0.177004220f, -0.984210092f, + -0.170961889f, -0.985277642f, + -0.164913120f, -0.986308097f, + -0.158858143f, -0.987301418f, + -0.152797185f, -0.988257568f, + -0.146730474f, -0.989176510f, + -0.140658239f, -0.990058210f, + -0.134580709f, -0.990902635f, + -0.128498111f, -0.991709754f, + -0.122410675f, -0.992479535f, + -0.116318631f, -0.993211949f, + -0.110222207f, -0.993906970f, + -0.104121634f, -0.994564571f, + -0.098017140f, -0.995184727f, + -0.091908956f, -0.995767414f, + -0.085797312f, -0.996312612f, + -0.079682438f, -0.996820299f, + -0.073564564f, -0.997290457f, + -0.067443920f, -0.997723067f, + -0.061320736f, -0.998118113f, + -0.055195244f, -0.998475581f, + -0.049067674f, -0.998795456f, + -0.042938257f, -0.999077728f, + -0.036807223f, -0.999322385f, + -0.030674803f, -0.999529418f, + -0.024541229f, -0.999698819f, + -0.018406730f, -0.999830582f, + -0.012271538f, -0.999924702f, + -0.006135885f, -0.999981175f, + -0.000000000f, -1.000000000f, + 0.006135885f, -0.999981175f, + 0.012271538f, -0.999924702f, + 0.018406730f, -0.999830582f, + 0.024541229f, -0.999698819f, + 0.030674803f, -0.999529418f, + 0.036807223f, -0.999322385f, + 0.042938257f, -0.999077728f, + 0.049067674f, -0.998795456f, + 0.055195244f, -0.998475581f, + 0.061320736f, -0.998118113f, + 0.067443920f, -0.997723067f, + 0.073564564f, -0.997290457f, + 0.079682438f, -0.996820299f, + 0.085797312f, -0.996312612f, + 0.091908956f, -0.995767414f, + 0.098017140f, -0.995184727f, + 0.104121634f, -0.994564571f, + 0.110222207f, -0.993906970f, + 0.116318631f, -0.993211949f, + 0.122410675f, -0.992479535f, + 0.128498111f, -0.991709754f, + 0.134580709f, -0.990902635f, + 0.140658239f, -0.990058210f, + 0.146730474f, -0.989176510f, + 0.152797185f, -0.988257568f, + 0.158858143f, -0.987301418f, + 0.164913120f, -0.986308097f, + 0.170961889f, -0.985277642f, + 0.177004220f, -0.984210092f, + 0.183039888f, -0.983105487f, + 0.189068664f, -0.981963869f, + 0.195090322f, -0.980785280f, + 0.201104635f, -0.979569766f, + 0.207111376f, -0.978317371f, + 0.213110320f, -0.977028143f, + 0.219101240f, -0.975702130f, + 0.225083911f, -0.974339383f, + 0.231058108f, -0.972939952f, + 0.237023606f, -0.971503891f, + 0.242980180f, -0.970031253f, + 0.248927606f, -0.968522094f, + 0.254865660f, -0.966976471f, + 0.260794118f, -0.965394442f, + 0.266712757f, -0.963776066f, + 0.272621355f, -0.962121404f, + 0.278519689f, -0.960430519f, + 0.284407537f, -0.958703475f, + 0.290284677f, -0.956940336f, + 0.296150888f, -0.955141168f, + 0.302005949f, -0.953306040f, + 0.307849640f, -0.951435021f, + 0.313681740f, -0.949528181f, + 0.319502031f, -0.947585591f, + 0.325310292f, -0.945607325f, + 0.331106306f, -0.943593458f, + 0.336889853f, -0.941544065f, + 0.342660717f, -0.939459224f, + 0.348418680f, -0.937339012f, + 0.354163525f, -0.935183510f, + 0.359895037f, -0.932992799f, + 0.365612998f, -0.930766961f, + 0.371317194f, -0.928506080f, + 0.377007410f, -0.926210242f, + 0.382683432f, -0.923879533f, + 0.388345047f, -0.921514039f, + 0.393992040f, -0.919113852f, + 0.399624200f, -0.916679060f, + 0.405241314f, -0.914209756f, + 0.410843171f, -0.911706032f, + 0.416429560f, -0.909167983f, + 0.422000271f, -0.906595705f, + 0.427555093f, -0.903989293f, + 0.433093819f, -0.901348847f, + 0.438616239f, -0.898674466f, + 0.444122145f, -0.895966250f, + 0.449611330f, -0.893224301f, + 0.455083587f, -0.890448723f, + 0.460538711f, -0.887639620f, + 0.465976496f, -0.884797098f, + 0.471396737f, -0.881921264f, + 0.476799230f, -0.879012226f, + 0.482183772f, -0.876070094f, + 0.487550160f, -0.873094978f, + 0.492898192f, -0.870086991f, + 0.498227667f, -0.867046246f, + 0.503538384f, -0.863972856f, + 0.508830143f, -0.860866939f, + 0.514102744f, -0.857728610f, + 0.519355990f, -0.854557988f, + 0.524589683f, -0.851355193f, + 0.529803625f, -0.848120345f, + 0.534997620f, -0.844853565f, + 0.540171473f, -0.841554977f, + 0.545324988f, -0.838224706f, + 0.550457973f, -0.834862875f, + 0.555570233f, -0.831469612f, + 0.560661576f, -0.828045045f, + 0.565731811f, -0.824589303f, + 0.570780746f, -0.821102515f, + 0.575808191f, -0.817584813f, + 0.580813958f, -0.814036330f, + 0.585797857f, -0.810457198f, + 0.590759702f, -0.806847554f, + 0.595699304f, -0.803207531f, + 0.600616479f, -0.799537269f, + 0.605511041f, -0.795836905f, + 0.610382806f, -0.792106577f, + 0.615231591f, -0.788346428f, + 0.620057212f, -0.784556597f, + 0.624859488f, -0.780737229f, + 0.629638239f, -0.776888466f, + 0.634393284f, -0.773010453f, + 0.639124445f, -0.769103338f, + 0.643831543f, -0.765167266f, + 0.648514401f, -0.761202385f, + 0.653172843f, -0.757208847f, + 0.657806693f, -0.753186799f, + 0.662415778f, -0.749136395f, + 0.666999922f, -0.745057785f, + 0.671558955f, -0.740951125f, + 0.676092704f, -0.736816569f, + 0.680600998f, -0.732654272f, + 0.685083668f, -0.728464390f, + 0.689540545f, -0.724247083f, + 0.693971461f, -0.720002508f, + 0.698376249f, -0.715730825f, + 0.702754744f, -0.711432196f, + 0.707106781f, -0.707106781f, + 0.711432196f, -0.702754744f, + 0.715730825f, -0.698376249f, + 0.720002508f, -0.693971461f, + 0.724247083f, -0.689540545f, + 0.728464390f, -0.685083668f, + 0.732654272f, -0.680600998f, + 0.736816569f, -0.676092704f, + 0.740951125f, -0.671558955f, + 0.745057785f, -0.666999922f, + 0.749136395f, -0.662415778f, + 0.753186799f, -0.657806693f, + 0.757208847f, -0.653172843f, + 0.761202385f, -0.648514401f, + 0.765167266f, -0.643831543f, + 0.769103338f, -0.639124445f, + 0.773010453f, -0.634393284f, + 0.776888466f, -0.629638239f, + 0.780737229f, -0.624859488f, + 0.784556597f, -0.620057212f, + 0.788346428f, -0.615231591f, + 0.792106577f, -0.610382806f, + 0.795836905f, -0.605511041f, + 0.799537269f, -0.600616479f, + 0.803207531f, -0.595699304f, + 0.806847554f, -0.590759702f, + 0.810457198f, -0.585797857f, + 0.814036330f, -0.580813958f, + 0.817584813f, -0.575808191f, + 0.821102515f, -0.570780746f, + 0.824589303f, -0.565731811f, + 0.828045045f, -0.560661576f, + 0.831469612f, -0.555570233f, + 0.834862875f, -0.550457973f, + 0.838224706f, -0.545324988f, + 0.841554977f, -0.540171473f, + 0.844853565f, -0.534997620f, + 0.848120345f, -0.529803625f, + 0.851355193f, -0.524589683f, + 0.854557988f, -0.519355990f, + 0.857728610f, -0.514102744f, + 0.860866939f, -0.508830143f, + 0.863972856f, -0.503538384f, + 0.867046246f, -0.498227667f, + 0.870086991f, -0.492898192f, + 0.873094978f, -0.487550160f, + 0.876070094f, -0.482183772f, + 0.879012226f, -0.476799230f, + 0.881921264f, -0.471396737f, + 0.884797098f, -0.465976496f, + 0.887639620f, -0.460538711f, + 0.890448723f, -0.455083587f, + 0.893224301f, -0.449611330f, + 0.895966250f, -0.444122145f, + 0.898674466f, -0.438616239f, + 0.901348847f, -0.433093819f, + 0.903989293f, -0.427555093f, + 0.906595705f, -0.422000271f, + 0.909167983f, -0.416429560f, + 0.911706032f, -0.410843171f, + 0.914209756f, -0.405241314f, + 0.916679060f, -0.399624200f, + 0.919113852f, -0.393992040f, + 0.921514039f, -0.388345047f, + 0.923879533f, -0.382683432f, + 0.926210242f, -0.377007410f, + 0.928506080f, -0.371317194f, + 0.930766961f, -0.365612998f, + 0.932992799f, -0.359895037f, + 0.935183510f, -0.354163525f, + 0.937339012f, -0.348418680f, + 0.939459224f, -0.342660717f, + 0.941544065f, -0.336889853f, + 0.943593458f, -0.331106306f, + 0.945607325f, -0.325310292f, + 0.947585591f, -0.319502031f, + 0.949528181f, -0.313681740f, + 0.951435021f, -0.307849640f, + 0.953306040f, -0.302005949f, + 0.955141168f, -0.296150888f, + 0.956940336f, -0.290284677f, + 0.958703475f, -0.284407537f, + 0.960430519f, -0.278519689f, + 0.962121404f, -0.272621355f, + 0.963776066f, -0.266712757f, + 0.965394442f, -0.260794118f, + 0.966976471f, -0.254865660f, + 0.968522094f, -0.248927606f, + 0.970031253f, -0.242980180f, + 0.971503891f, -0.237023606f, + 0.972939952f, -0.231058108f, + 0.974339383f, -0.225083911f, + 0.975702130f, -0.219101240f, + 0.977028143f, -0.213110320f, + 0.978317371f, -0.207111376f, + 0.979569766f, -0.201104635f, + 0.980785280f, -0.195090322f, + 0.981963869f, -0.189068664f, + 0.983105487f, -0.183039888f, + 0.984210092f, -0.177004220f, + 0.985277642f, -0.170961889f, + 0.986308097f, -0.164913120f, + 0.987301418f, -0.158858143f, + 0.988257568f, -0.152797185f, + 0.989176510f, -0.146730474f, + 0.990058210f, -0.140658239f, + 0.990902635f, -0.134580709f, + 0.991709754f, -0.128498111f, + 0.992479535f, -0.122410675f, + 0.993211949f, -0.116318631f, + 0.993906970f, -0.110222207f, + 0.994564571f, -0.104121634f, + 0.995184727f, -0.098017140f, + 0.995767414f, -0.091908956f, + 0.996312612f, -0.085797312f, + 0.996820299f, -0.079682438f, + 0.997290457f, -0.073564564f, + 0.997723067f, -0.067443920f, + 0.998118113f, -0.061320736f, + 0.998475581f, -0.055195244f, + 0.998795456f, -0.049067674f, + 0.999077728f, -0.042938257f, + 0.999322385f, -0.036807223f, + 0.999529418f, -0.030674803f, + 0.999698819f, -0.024541229f, + 0.999830582f, -0.018406730f, + 0.999924702f, -0.012271538f, + 0.999981175f, -0.006135885f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_2048[4096] = { + 1.000000000f, 0.000000000f, + 0.999995294f, 0.003067957f, + 0.999981175f, 0.006135885f, + 0.999957645f, 0.009203755f, + 0.999924702f, 0.012271538f, + 0.999882347f, 0.015339206f, + 0.999830582f, 0.018406730f, + 0.999769405f, 0.021474080f, + 0.999698819f, 0.024541229f, + 0.999618822f, 0.027608146f, + 0.999529418f, 0.030674803f, + 0.999430605f, 0.033741172f, + 0.999322385f, 0.036807223f, + 0.999204759f, 0.039872928f, + 0.999077728f, 0.042938257f, + 0.998941293f, 0.046003182f, + 0.998795456f, 0.049067674f, + 0.998640218f, 0.052131705f, + 0.998475581f, 0.055195244f, + 0.998301545f, 0.058258265f, + 0.998118113f, 0.061320736f, + 0.997925286f, 0.064382631f, + 0.997723067f, 0.067443920f, + 0.997511456f, 0.070504573f, + 0.997290457f, 0.073564564f, + 0.997060070f, 0.076623861f, + 0.996820299f, 0.079682438f, + 0.996571146f, 0.082740265f, + 0.996312612f, 0.085797312f, + 0.996044701f, 0.088853553f, + 0.995767414f, 0.091908956f, + 0.995480755f, 0.094963495f, + 0.995184727f, 0.098017140f, + 0.994879331f, 0.101069863f, + 0.994564571f, 0.104121634f, + 0.994240449f, 0.107172425f, + 0.993906970f, 0.110222207f, + 0.993564136f, 0.113270952f, + 0.993211949f, 0.116318631f, + 0.992850414f, 0.119365215f, + 0.992479535f, 0.122410675f, + 0.992099313f, 0.125454983f, + 0.991709754f, 0.128498111f, + 0.991310860f, 0.131540029f, + 0.990902635f, 0.134580709f, + 0.990485084f, 0.137620122f, + 0.990058210f, 0.140658239f, + 0.989622017f, 0.143695033f, + 0.989176510f, 0.146730474f, + 0.988721692f, 0.149764535f, + 0.988257568f, 0.152797185f, + 0.987784142f, 0.155828398f, + 0.987301418f, 0.158858143f, + 0.986809402f, 0.161886394f, + 0.986308097f, 0.164913120f, + 0.985797509f, 0.167938295f, + 0.985277642f, 0.170961889f, + 0.984748502f, 0.173983873f, + 0.984210092f, 0.177004220f, + 0.983662419f, 0.180022901f, + 0.983105487f, 0.183039888f, + 0.982539302f, 0.186055152f, + 0.981963869f, 0.189068664f, + 0.981379193f, 0.192080397f, + 0.980785280f, 0.195090322f, + 0.980182136f, 0.198098411f, + 0.979569766f, 0.201104635f, + 0.978948175f, 0.204108966f, + 0.978317371f, 0.207111376f, + 0.977677358f, 0.210111837f, + 0.977028143f, 0.213110320f, + 0.976369731f, 0.216106797f, + 0.975702130f, 0.219101240f, + 0.975025345f, 0.222093621f, + 0.974339383f, 0.225083911f, + 0.973644250f, 0.228072083f, + 0.972939952f, 0.231058108f, + 0.972226497f, 0.234041959f, + 0.971503891f, 0.237023606f, + 0.970772141f, 0.240003022f, + 0.970031253f, 0.242980180f, + 0.969281235f, 0.245955050f, + 0.968522094f, 0.248927606f, + 0.967753837f, 0.251897818f, + 0.966976471f, 0.254865660f, + 0.966190003f, 0.257831102f, + 0.965394442f, 0.260794118f, + 0.964589793f, 0.263754679f, + 0.963776066f, 0.266712757f, + 0.962953267f, 0.269668326f, + 0.962121404f, 0.272621355f, + 0.961280486f, 0.275571819f, + 0.960430519f, 0.278519689f, + 0.959571513f, 0.281464938f, + 0.958703475f, 0.284407537f, + 0.957826413f, 0.287347460f, + 0.956940336f, 0.290284677f, + 0.956045251f, 0.293219163f, + 0.955141168f, 0.296150888f, + 0.954228095f, 0.299079826f, + 0.953306040f, 0.302005949f, + 0.952375013f, 0.304929230f, + 0.951435021f, 0.307849640f, + 0.950486074f, 0.310767153f, + 0.949528181f, 0.313681740f, + 0.948561350f, 0.316593376f, + 0.947585591f, 0.319502031f, + 0.946600913f, 0.322407679f, + 0.945607325f, 0.325310292f, + 0.944604837f, 0.328209844f, + 0.943593458f, 0.331106306f, + 0.942573198f, 0.333999651f, + 0.941544065f, 0.336889853f, + 0.940506071f, 0.339776884f, + 0.939459224f, 0.342660717f, + 0.938403534f, 0.345541325f, + 0.937339012f, 0.348418680f, + 0.936265667f, 0.351292756f, + 0.935183510f, 0.354163525f, + 0.934092550f, 0.357030961f, + 0.932992799f, 0.359895037f, + 0.931884266f, 0.362755724f, + 0.930766961f, 0.365612998f, + 0.929640896f, 0.368466830f, + 0.928506080f, 0.371317194f, + 0.927362526f, 0.374164063f, + 0.926210242f, 0.377007410f, + 0.925049241f, 0.379847209f, + 0.923879533f, 0.382683432f, + 0.922701128f, 0.385516054f, + 0.921514039f, 0.388345047f, + 0.920318277f, 0.391170384f, + 0.919113852f, 0.393992040f, + 0.917900776f, 0.396809987f, + 0.916679060f, 0.399624200f, + 0.915448716f, 0.402434651f, + 0.914209756f, 0.405241314f, + 0.912962190f, 0.408044163f, + 0.911706032f, 0.410843171f, + 0.910441292f, 0.413638312f, + 0.909167983f, 0.416429560f, + 0.907886116f, 0.419216888f, + 0.906595705f, 0.422000271f, + 0.905296759f, 0.424779681f, + 0.903989293f, 0.427555093f, + 0.902673318f, 0.430326481f, + 0.901348847f, 0.433093819f, + 0.900015892f, 0.435857080f, + 0.898674466f, 0.438616239f, + 0.897324581f, 0.441371269f, + 0.895966250f, 0.444122145f, + 0.894599486f, 0.446868840f, + 0.893224301f, 0.449611330f, + 0.891840709f, 0.452349587f, + 0.890448723f, 0.455083587f, + 0.889048356f, 0.457813304f, + 0.887639620f, 0.460538711f, + 0.886222530f, 0.463259784f, + 0.884797098f, 0.465976496f, + 0.883363339f, 0.468688822f, + 0.881921264f, 0.471396737f, + 0.880470889f, 0.474100215f, + 0.879012226f, 0.476799230f, + 0.877545290f, 0.479493758f, + 0.876070094f, 0.482183772f, + 0.874586652f, 0.484869248f, + 0.873094978f, 0.487550160f, + 0.871595087f, 0.490226483f, + 0.870086991f, 0.492898192f, + 0.868570706f, 0.495565262f, + 0.867046246f, 0.498227667f, + 0.865513624f, 0.500885383f, + 0.863972856f, 0.503538384f, + 0.862423956f, 0.506186645f, + 0.860866939f, 0.508830143f, + 0.859301818f, 0.511468850f, + 0.857728610f, 0.514102744f, + 0.856147328f, 0.516731799f, + 0.854557988f, 0.519355990f, + 0.852960605f, 0.521975293f, + 0.851355193f, 0.524589683f, + 0.849741768f, 0.527199135f, + 0.848120345f, 0.529803625f, + 0.846490939f, 0.532403128f, + 0.844853565f, 0.534997620f, + 0.843208240f, 0.537587076f, + 0.841554977f, 0.540171473f, + 0.839893794f, 0.542750785f, + 0.838224706f, 0.545324988f, + 0.836547727f, 0.547894059f, + 0.834862875f, 0.550457973f, + 0.833170165f, 0.553016706f, + 0.831469612f, 0.555570233f, + 0.829761234f, 0.558118531f, + 0.828045045f, 0.560661576f, + 0.826321063f, 0.563199344f, + 0.824589303f, 0.565731811f, + 0.822849781f, 0.568258953f, + 0.821102515f, 0.570780746f, + 0.819347520f, 0.573297167f, + 0.817584813f, 0.575808191f, + 0.815814411f, 0.578313796f, + 0.814036330f, 0.580813958f, + 0.812250587f, 0.583308653f, + 0.810457198f, 0.585797857f, + 0.808656182f, 0.588281548f, + 0.806847554f, 0.590759702f, + 0.805031331f, 0.593232295f, + 0.803207531f, 0.595699304f, + 0.801376172f, 0.598160707f, + 0.799537269f, 0.600616479f, + 0.797690841f, 0.603066599f, + 0.795836905f, 0.605511041f, + 0.793975478f, 0.607949785f, + 0.792106577f, 0.610382806f, + 0.790230221f, 0.612810082f, + 0.788346428f, 0.615231591f, + 0.786455214f, 0.617647308f, + 0.784556597f, 0.620057212f, + 0.782650596f, 0.622461279f, + 0.780737229f, 0.624859488f, + 0.778816512f, 0.627251815f, + 0.776888466f, 0.629638239f, + 0.774953107f, 0.632018736f, + 0.773010453f, 0.634393284f, + 0.771060524f, 0.636761861f, + 0.769103338f, 0.639124445f, + 0.767138912f, 0.641481013f, + 0.765167266f, 0.643831543f, + 0.763188417f, 0.646176013f, + 0.761202385f, 0.648514401f, + 0.759209189f, 0.650846685f, + 0.757208847f, 0.653172843f, + 0.755201377f, 0.655492853f, + 0.753186799f, 0.657806693f, + 0.751165132f, 0.660114342f, + 0.749136395f, 0.662415778f, + 0.747100606f, 0.664710978f, + 0.745057785f, 0.666999922f, + 0.743007952f, 0.669282588f, + 0.740951125f, 0.671558955f, + 0.738887324f, 0.673829000f, + 0.736816569f, 0.676092704f, + 0.734738878f, 0.678350043f, + 0.732654272f, 0.680600998f, + 0.730562769f, 0.682845546f, + 0.728464390f, 0.685083668f, + 0.726359155f, 0.687315341f, + 0.724247083f, 0.689540545f, + 0.722128194f, 0.691759258f, + 0.720002508f, 0.693971461f, + 0.717870045f, 0.696177131f, + 0.715730825f, 0.698376249f, + 0.713584869f, 0.700568794f, + 0.711432196f, 0.702754744f, + 0.709272826f, 0.704934080f, + 0.707106781f, 0.707106781f, + 0.704934080f, 0.709272826f, + 0.702754744f, 0.711432196f, + 0.700568794f, 0.713584869f, + 0.698376249f, 0.715730825f, + 0.696177131f, 0.717870045f, + 0.693971461f, 0.720002508f, + 0.691759258f, 0.722128194f, + 0.689540545f, 0.724247083f, + 0.687315341f, 0.726359155f, + 0.685083668f, 0.728464390f, + 0.682845546f, 0.730562769f, + 0.680600998f, 0.732654272f, + 0.678350043f, 0.734738878f, + 0.676092704f, 0.736816569f, + 0.673829000f, 0.738887324f, + 0.671558955f, 0.740951125f, + 0.669282588f, 0.743007952f, + 0.666999922f, 0.745057785f, + 0.664710978f, 0.747100606f, + 0.662415778f, 0.749136395f, + 0.660114342f, 0.751165132f, + 0.657806693f, 0.753186799f, + 0.655492853f, 0.755201377f, + 0.653172843f, 0.757208847f, + 0.650846685f, 0.759209189f, + 0.648514401f, 0.761202385f, + 0.646176013f, 0.763188417f, + 0.643831543f, 0.765167266f, + 0.641481013f, 0.767138912f, + 0.639124445f, 0.769103338f, + 0.636761861f, 0.771060524f, + 0.634393284f, 0.773010453f, + 0.632018736f, 0.774953107f, + 0.629638239f, 0.776888466f, + 0.627251815f, 0.778816512f, + 0.624859488f, 0.780737229f, + 0.622461279f, 0.782650596f, + 0.620057212f, 0.784556597f, + 0.617647308f, 0.786455214f, + 0.615231591f, 0.788346428f, + 0.612810082f, 0.790230221f, + 0.610382806f, 0.792106577f, + 0.607949785f, 0.793975478f, + 0.605511041f, 0.795836905f, + 0.603066599f, 0.797690841f, + 0.600616479f, 0.799537269f, + 0.598160707f, 0.801376172f, + 0.595699304f, 0.803207531f, + 0.593232295f, 0.805031331f, + 0.590759702f, 0.806847554f, + 0.588281548f, 0.808656182f, + 0.585797857f, 0.810457198f, + 0.583308653f, 0.812250587f, + 0.580813958f, 0.814036330f, + 0.578313796f, 0.815814411f, + 0.575808191f, 0.817584813f, + 0.573297167f, 0.819347520f, + 0.570780746f, 0.821102515f, + 0.568258953f, 0.822849781f, + 0.565731811f, 0.824589303f, + 0.563199344f, 0.826321063f, + 0.560661576f, 0.828045045f, + 0.558118531f, 0.829761234f, + 0.555570233f, 0.831469612f, + 0.553016706f, 0.833170165f, + 0.550457973f, 0.834862875f, + 0.547894059f, 0.836547727f, + 0.545324988f, 0.838224706f, + 0.542750785f, 0.839893794f, + 0.540171473f, 0.841554977f, + 0.537587076f, 0.843208240f, + 0.534997620f, 0.844853565f, + 0.532403128f, 0.846490939f, + 0.529803625f, 0.848120345f, + 0.527199135f, 0.849741768f, + 0.524589683f, 0.851355193f, + 0.521975293f, 0.852960605f, + 0.519355990f, 0.854557988f, + 0.516731799f, 0.856147328f, + 0.514102744f, 0.857728610f, + 0.511468850f, 0.859301818f, + 0.508830143f, 0.860866939f, + 0.506186645f, 0.862423956f, + 0.503538384f, 0.863972856f, + 0.500885383f, 0.865513624f, + 0.498227667f, 0.867046246f, + 0.495565262f, 0.868570706f, + 0.492898192f, 0.870086991f, + 0.490226483f, 0.871595087f, + 0.487550160f, 0.873094978f, + 0.484869248f, 0.874586652f, + 0.482183772f, 0.876070094f, + 0.479493758f, 0.877545290f, + 0.476799230f, 0.879012226f, + 0.474100215f, 0.880470889f, + 0.471396737f, 0.881921264f, + 0.468688822f, 0.883363339f, + 0.465976496f, 0.884797098f, + 0.463259784f, 0.886222530f, + 0.460538711f, 0.887639620f, + 0.457813304f, 0.889048356f, + 0.455083587f, 0.890448723f, + 0.452349587f, 0.891840709f, + 0.449611330f, 0.893224301f, + 0.446868840f, 0.894599486f, + 0.444122145f, 0.895966250f, + 0.441371269f, 0.897324581f, + 0.438616239f, 0.898674466f, + 0.435857080f, 0.900015892f, + 0.433093819f, 0.901348847f, + 0.430326481f, 0.902673318f, + 0.427555093f, 0.903989293f, + 0.424779681f, 0.905296759f, + 0.422000271f, 0.906595705f, + 0.419216888f, 0.907886116f, + 0.416429560f, 0.909167983f, + 0.413638312f, 0.910441292f, + 0.410843171f, 0.911706032f, + 0.408044163f, 0.912962190f, + 0.405241314f, 0.914209756f, + 0.402434651f, 0.915448716f, + 0.399624200f, 0.916679060f, + 0.396809987f, 0.917900776f, + 0.393992040f, 0.919113852f, + 0.391170384f, 0.920318277f, + 0.388345047f, 0.921514039f, + 0.385516054f, 0.922701128f, + 0.382683432f, 0.923879533f, + 0.379847209f, 0.925049241f, + 0.377007410f, 0.926210242f, + 0.374164063f, 0.927362526f, + 0.371317194f, 0.928506080f, + 0.368466830f, 0.929640896f, + 0.365612998f, 0.930766961f, + 0.362755724f, 0.931884266f, + 0.359895037f, 0.932992799f, + 0.357030961f, 0.934092550f, + 0.354163525f, 0.935183510f, + 0.351292756f, 0.936265667f, + 0.348418680f, 0.937339012f, + 0.345541325f, 0.938403534f, + 0.342660717f, 0.939459224f, + 0.339776884f, 0.940506071f, + 0.336889853f, 0.941544065f, + 0.333999651f, 0.942573198f, + 0.331106306f, 0.943593458f, + 0.328209844f, 0.944604837f, + 0.325310292f, 0.945607325f, + 0.322407679f, 0.946600913f, + 0.319502031f, 0.947585591f, + 0.316593376f, 0.948561350f, + 0.313681740f, 0.949528181f, + 0.310767153f, 0.950486074f, + 0.307849640f, 0.951435021f, + 0.304929230f, 0.952375013f, + 0.302005949f, 0.953306040f, + 0.299079826f, 0.954228095f, + 0.296150888f, 0.955141168f, + 0.293219163f, 0.956045251f, + 0.290284677f, 0.956940336f, + 0.287347460f, 0.957826413f, + 0.284407537f, 0.958703475f, + 0.281464938f, 0.959571513f, + 0.278519689f, 0.960430519f, + 0.275571819f, 0.961280486f, + 0.272621355f, 0.962121404f, + 0.269668326f, 0.962953267f, + 0.266712757f, 0.963776066f, + 0.263754679f, 0.964589793f, + 0.260794118f, 0.965394442f, + 0.257831102f, 0.966190003f, + 0.254865660f, 0.966976471f, + 0.251897818f, 0.967753837f, + 0.248927606f, 0.968522094f, + 0.245955050f, 0.969281235f, + 0.242980180f, 0.970031253f, + 0.240003022f, 0.970772141f, + 0.237023606f, 0.971503891f, + 0.234041959f, 0.972226497f, + 0.231058108f, 0.972939952f, + 0.228072083f, 0.973644250f, + 0.225083911f, 0.974339383f, + 0.222093621f, 0.975025345f, + 0.219101240f, 0.975702130f, + 0.216106797f, 0.976369731f, + 0.213110320f, 0.977028143f, + 0.210111837f, 0.977677358f, + 0.207111376f, 0.978317371f, + 0.204108966f, 0.978948175f, + 0.201104635f, 0.979569766f, + 0.198098411f, 0.980182136f, + 0.195090322f, 0.980785280f, + 0.192080397f, 0.981379193f, + 0.189068664f, 0.981963869f, + 0.186055152f, 0.982539302f, + 0.183039888f, 0.983105487f, + 0.180022901f, 0.983662419f, + 0.177004220f, 0.984210092f, + 0.173983873f, 0.984748502f, + 0.170961889f, 0.985277642f, + 0.167938295f, 0.985797509f, + 0.164913120f, 0.986308097f, + 0.161886394f, 0.986809402f, + 0.158858143f, 0.987301418f, + 0.155828398f, 0.987784142f, + 0.152797185f, 0.988257568f, + 0.149764535f, 0.988721692f, + 0.146730474f, 0.989176510f, + 0.143695033f, 0.989622017f, + 0.140658239f, 0.990058210f, + 0.137620122f, 0.990485084f, + 0.134580709f, 0.990902635f, + 0.131540029f, 0.991310860f, + 0.128498111f, 0.991709754f, + 0.125454983f, 0.992099313f, + 0.122410675f, 0.992479535f, + 0.119365215f, 0.992850414f, + 0.116318631f, 0.993211949f, + 0.113270952f, 0.993564136f, + 0.110222207f, 0.993906970f, + 0.107172425f, 0.994240449f, + 0.104121634f, 0.994564571f, + 0.101069863f, 0.994879331f, + 0.098017140f, 0.995184727f, + 0.094963495f, 0.995480755f, + 0.091908956f, 0.995767414f, + 0.088853553f, 0.996044701f, + 0.085797312f, 0.996312612f, + 0.082740265f, 0.996571146f, + 0.079682438f, 0.996820299f, + 0.076623861f, 0.997060070f, + 0.073564564f, 0.997290457f, + 0.070504573f, 0.997511456f, + 0.067443920f, 0.997723067f, + 0.064382631f, 0.997925286f, + 0.061320736f, 0.998118113f, + 0.058258265f, 0.998301545f, + 0.055195244f, 0.998475581f, + 0.052131705f, 0.998640218f, + 0.049067674f, 0.998795456f, + 0.046003182f, 0.998941293f, + 0.042938257f, 0.999077728f, + 0.039872928f, 0.999204759f, + 0.036807223f, 0.999322385f, + 0.033741172f, 0.999430605f, + 0.030674803f, 0.999529418f, + 0.027608146f, 0.999618822f, + 0.024541229f, 0.999698819f, + 0.021474080f, 0.999769405f, + 0.018406730f, 0.999830582f, + 0.015339206f, 0.999882347f, + 0.012271538f, 0.999924702f, + 0.009203755f, 0.999957645f, + 0.006135885f, 0.999981175f, + 0.003067957f, 0.999995294f, + 0.000000000f, 1.000000000f, + -0.003067957f, 0.999995294f, + -0.006135885f, 0.999981175f, + -0.009203755f, 0.999957645f, + -0.012271538f, 0.999924702f, + -0.015339206f, 0.999882347f, + -0.018406730f, 0.999830582f, + -0.021474080f, 0.999769405f, + -0.024541229f, 0.999698819f, + -0.027608146f, 0.999618822f, + -0.030674803f, 0.999529418f, + -0.033741172f, 0.999430605f, + -0.036807223f, 0.999322385f, + -0.039872928f, 0.999204759f, + -0.042938257f, 0.999077728f, + -0.046003182f, 0.998941293f, + -0.049067674f, 0.998795456f, + -0.052131705f, 0.998640218f, + -0.055195244f, 0.998475581f, + -0.058258265f, 0.998301545f, + -0.061320736f, 0.998118113f, + -0.064382631f, 0.997925286f, + -0.067443920f, 0.997723067f, + -0.070504573f, 0.997511456f, + -0.073564564f, 0.997290457f, + -0.076623861f, 0.997060070f, + -0.079682438f, 0.996820299f, + -0.082740265f, 0.996571146f, + -0.085797312f, 0.996312612f, + -0.088853553f, 0.996044701f, + -0.091908956f, 0.995767414f, + -0.094963495f, 0.995480755f, + -0.098017140f, 0.995184727f, + -0.101069863f, 0.994879331f, + -0.104121634f, 0.994564571f, + -0.107172425f, 0.994240449f, + -0.110222207f, 0.993906970f, + -0.113270952f, 0.993564136f, + -0.116318631f, 0.993211949f, + -0.119365215f, 0.992850414f, + -0.122410675f, 0.992479535f, + -0.125454983f, 0.992099313f, + -0.128498111f, 0.991709754f, + -0.131540029f, 0.991310860f, + -0.134580709f, 0.990902635f, + -0.137620122f, 0.990485084f, + -0.140658239f, 0.990058210f, + -0.143695033f, 0.989622017f, + -0.146730474f, 0.989176510f, + -0.149764535f, 0.988721692f, + -0.152797185f, 0.988257568f, + -0.155828398f, 0.987784142f, + -0.158858143f, 0.987301418f, + -0.161886394f, 0.986809402f, + -0.164913120f, 0.986308097f, + -0.167938295f, 0.985797509f, + -0.170961889f, 0.985277642f, + -0.173983873f, 0.984748502f, + -0.177004220f, 0.984210092f, + -0.180022901f, 0.983662419f, + -0.183039888f, 0.983105487f, + -0.186055152f, 0.982539302f, + -0.189068664f, 0.981963869f, + -0.192080397f, 0.981379193f, + -0.195090322f, 0.980785280f, + -0.198098411f, 0.980182136f, + -0.201104635f, 0.979569766f, + -0.204108966f, 0.978948175f, + -0.207111376f, 0.978317371f, + -0.210111837f, 0.977677358f, + -0.213110320f, 0.977028143f, + -0.216106797f, 0.976369731f, + -0.219101240f, 0.975702130f, + -0.222093621f, 0.975025345f, + -0.225083911f, 0.974339383f, + -0.228072083f, 0.973644250f, + -0.231058108f, 0.972939952f, + -0.234041959f, 0.972226497f, + -0.237023606f, 0.971503891f, + -0.240003022f, 0.970772141f, + -0.242980180f, 0.970031253f, + -0.245955050f, 0.969281235f, + -0.248927606f, 0.968522094f, + -0.251897818f, 0.967753837f, + -0.254865660f, 0.966976471f, + -0.257831102f, 0.966190003f, + -0.260794118f, 0.965394442f, + -0.263754679f, 0.964589793f, + -0.266712757f, 0.963776066f, + -0.269668326f, 0.962953267f, + -0.272621355f, 0.962121404f, + -0.275571819f, 0.961280486f, + -0.278519689f, 0.960430519f, + -0.281464938f, 0.959571513f, + -0.284407537f, 0.958703475f, + -0.287347460f, 0.957826413f, + -0.290284677f, 0.956940336f, + -0.293219163f, 0.956045251f, + -0.296150888f, 0.955141168f, + -0.299079826f, 0.954228095f, + -0.302005949f, 0.953306040f, + -0.304929230f, 0.952375013f, + -0.307849640f, 0.951435021f, + -0.310767153f, 0.950486074f, + -0.313681740f, 0.949528181f, + -0.316593376f, 0.948561350f, + -0.319502031f, 0.947585591f, + -0.322407679f, 0.946600913f, + -0.325310292f, 0.945607325f, + -0.328209844f, 0.944604837f, + -0.331106306f, 0.943593458f, + -0.333999651f, 0.942573198f, + -0.336889853f, 0.941544065f, + -0.339776884f, 0.940506071f, + -0.342660717f, 0.939459224f, + -0.345541325f, 0.938403534f, + -0.348418680f, 0.937339012f, + -0.351292756f, 0.936265667f, + -0.354163525f, 0.935183510f, + -0.357030961f, 0.934092550f, + -0.359895037f, 0.932992799f, + -0.362755724f, 0.931884266f, + -0.365612998f, 0.930766961f, + -0.368466830f, 0.929640896f, + -0.371317194f, 0.928506080f, + -0.374164063f, 0.927362526f, + -0.377007410f, 0.926210242f, + -0.379847209f, 0.925049241f, + -0.382683432f, 0.923879533f, + -0.385516054f, 0.922701128f, + -0.388345047f, 0.921514039f, + -0.391170384f, 0.920318277f, + -0.393992040f, 0.919113852f, + -0.396809987f, 0.917900776f, + -0.399624200f, 0.916679060f, + -0.402434651f, 0.915448716f, + -0.405241314f, 0.914209756f, + -0.408044163f, 0.912962190f, + -0.410843171f, 0.911706032f, + -0.413638312f, 0.910441292f, + -0.416429560f, 0.909167983f, + -0.419216888f, 0.907886116f, + -0.422000271f, 0.906595705f, + -0.424779681f, 0.905296759f, + -0.427555093f, 0.903989293f, + -0.430326481f, 0.902673318f, + -0.433093819f, 0.901348847f, + -0.435857080f, 0.900015892f, + -0.438616239f, 0.898674466f, + -0.441371269f, 0.897324581f, + -0.444122145f, 0.895966250f, + -0.446868840f, 0.894599486f, + -0.449611330f, 0.893224301f, + -0.452349587f, 0.891840709f, + -0.455083587f, 0.890448723f, + -0.457813304f, 0.889048356f, + -0.460538711f, 0.887639620f, + -0.463259784f, 0.886222530f, + -0.465976496f, 0.884797098f, + -0.468688822f, 0.883363339f, + -0.471396737f, 0.881921264f, + -0.474100215f, 0.880470889f, + -0.476799230f, 0.879012226f, + -0.479493758f, 0.877545290f, + -0.482183772f, 0.876070094f, + -0.484869248f, 0.874586652f, + -0.487550160f, 0.873094978f, + -0.490226483f, 0.871595087f, + -0.492898192f, 0.870086991f, + -0.495565262f, 0.868570706f, + -0.498227667f, 0.867046246f, + -0.500885383f, 0.865513624f, + -0.503538384f, 0.863972856f, + -0.506186645f, 0.862423956f, + -0.508830143f, 0.860866939f, + -0.511468850f, 0.859301818f, + -0.514102744f, 0.857728610f, + -0.516731799f, 0.856147328f, + -0.519355990f, 0.854557988f, + -0.521975293f, 0.852960605f, + -0.524589683f, 0.851355193f, + -0.527199135f, 0.849741768f, + -0.529803625f, 0.848120345f, + -0.532403128f, 0.846490939f, + -0.534997620f, 0.844853565f, + -0.537587076f, 0.843208240f, + -0.540171473f, 0.841554977f, + -0.542750785f, 0.839893794f, + -0.545324988f, 0.838224706f, + -0.547894059f, 0.836547727f, + -0.550457973f, 0.834862875f, + -0.553016706f, 0.833170165f, + -0.555570233f, 0.831469612f, + -0.558118531f, 0.829761234f, + -0.560661576f, 0.828045045f, + -0.563199344f, 0.826321063f, + -0.565731811f, 0.824589303f, + -0.568258953f, 0.822849781f, + -0.570780746f, 0.821102515f, + -0.573297167f, 0.819347520f, + -0.575808191f, 0.817584813f, + -0.578313796f, 0.815814411f, + -0.580813958f, 0.814036330f, + -0.583308653f, 0.812250587f, + -0.585797857f, 0.810457198f, + -0.588281548f, 0.808656182f, + -0.590759702f, 0.806847554f, + -0.593232295f, 0.805031331f, + -0.595699304f, 0.803207531f, + -0.598160707f, 0.801376172f, + -0.600616479f, 0.799537269f, + -0.603066599f, 0.797690841f, + -0.605511041f, 0.795836905f, + -0.607949785f, 0.793975478f, + -0.610382806f, 0.792106577f, + -0.612810082f, 0.790230221f, + -0.615231591f, 0.788346428f, + -0.617647308f, 0.786455214f, + -0.620057212f, 0.784556597f, + -0.622461279f, 0.782650596f, + -0.624859488f, 0.780737229f, + -0.627251815f, 0.778816512f, + -0.629638239f, 0.776888466f, + -0.632018736f, 0.774953107f, + -0.634393284f, 0.773010453f, + -0.636761861f, 0.771060524f, + -0.639124445f, 0.769103338f, + -0.641481013f, 0.767138912f, + -0.643831543f, 0.765167266f, + -0.646176013f, 0.763188417f, + -0.648514401f, 0.761202385f, + -0.650846685f, 0.759209189f, + -0.653172843f, 0.757208847f, + -0.655492853f, 0.755201377f, + -0.657806693f, 0.753186799f, + -0.660114342f, 0.751165132f, + -0.662415778f, 0.749136395f, + -0.664710978f, 0.747100606f, + -0.666999922f, 0.745057785f, + -0.669282588f, 0.743007952f, + -0.671558955f, 0.740951125f, + -0.673829000f, 0.738887324f, + -0.676092704f, 0.736816569f, + -0.678350043f, 0.734738878f, + -0.680600998f, 0.732654272f, + -0.682845546f, 0.730562769f, + -0.685083668f, 0.728464390f, + -0.687315341f, 0.726359155f, + -0.689540545f, 0.724247083f, + -0.691759258f, 0.722128194f, + -0.693971461f, 0.720002508f, + -0.696177131f, 0.717870045f, + -0.698376249f, 0.715730825f, + -0.700568794f, 0.713584869f, + -0.702754744f, 0.711432196f, + -0.704934080f, 0.709272826f, + -0.707106781f, 0.707106781f, + -0.709272826f, 0.704934080f, + -0.711432196f, 0.702754744f, + -0.713584869f, 0.700568794f, + -0.715730825f, 0.698376249f, + -0.717870045f, 0.696177131f, + -0.720002508f, 0.693971461f, + -0.722128194f, 0.691759258f, + -0.724247083f, 0.689540545f, + -0.726359155f, 0.687315341f, + -0.728464390f, 0.685083668f, + -0.730562769f, 0.682845546f, + -0.732654272f, 0.680600998f, + -0.734738878f, 0.678350043f, + -0.736816569f, 0.676092704f, + -0.738887324f, 0.673829000f, + -0.740951125f, 0.671558955f, + -0.743007952f, 0.669282588f, + -0.745057785f, 0.666999922f, + -0.747100606f, 0.664710978f, + -0.749136395f, 0.662415778f, + -0.751165132f, 0.660114342f, + -0.753186799f, 0.657806693f, + -0.755201377f, 0.655492853f, + -0.757208847f, 0.653172843f, + -0.759209189f, 0.650846685f, + -0.761202385f, 0.648514401f, + -0.763188417f, 0.646176013f, + -0.765167266f, 0.643831543f, + -0.767138912f, 0.641481013f, + -0.769103338f, 0.639124445f, + -0.771060524f, 0.636761861f, + -0.773010453f, 0.634393284f, + -0.774953107f, 0.632018736f, + -0.776888466f, 0.629638239f, + -0.778816512f, 0.627251815f, + -0.780737229f, 0.624859488f, + -0.782650596f, 0.622461279f, + -0.784556597f, 0.620057212f, + -0.786455214f, 0.617647308f, + -0.788346428f, 0.615231591f, + -0.790230221f, 0.612810082f, + -0.792106577f, 0.610382806f, + -0.793975478f, 0.607949785f, + -0.795836905f, 0.605511041f, + -0.797690841f, 0.603066599f, + -0.799537269f, 0.600616479f, + -0.801376172f, 0.598160707f, + -0.803207531f, 0.595699304f, + -0.805031331f, 0.593232295f, + -0.806847554f, 0.590759702f, + -0.808656182f, 0.588281548f, + -0.810457198f, 0.585797857f, + -0.812250587f, 0.583308653f, + -0.814036330f, 0.580813958f, + -0.815814411f, 0.578313796f, + -0.817584813f, 0.575808191f, + -0.819347520f, 0.573297167f, + -0.821102515f, 0.570780746f, + -0.822849781f, 0.568258953f, + -0.824589303f, 0.565731811f, + -0.826321063f, 0.563199344f, + -0.828045045f, 0.560661576f, + -0.829761234f, 0.558118531f, + -0.831469612f, 0.555570233f, + -0.833170165f, 0.553016706f, + -0.834862875f, 0.550457973f, + -0.836547727f, 0.547894059f, + -0.838224706f, 0.545324988f, + -0.839893794f, 0.542750785f, + -0.841554977f, 0.540171473f, + -0.843208240f, 0.537587076f, + -0.844853565f, 0.534997620f, + -0.846490939f, 0.532403128f, + -0.848120345f, 0.529803625f, + -0.849741768f, 0.527199135f, + -0.851355193f, 0.524589683f, + -0.852960605f, 0.521975293f, + -0.854557988f, 0.519355990f, + -0.856147328f, 0.516731799f, + -0.857728610f, 0.514102744f, + -0.859301818f, 0.511468850f, + -0.860866939f, 0.508830143f, + -0.862423956f, 0.506186645f, + -0.863972856f, 0.503538384f, + -0.865513624f, 0.500885383f, + -0.867046246f, 0.498227667f, + -0.868570706f, 0.495565262f, + -0.870086991f, 0.492898192f, + -0.871595087f, 0.490226483f, + -0.873094978f, 0.487550160f, + -0.874586652f, 0.484869248f, + -0.876070094f, 0.482183772f, + -0.877545290f, 0.479493758f, + -0.879012226f, 0.476799230f, + -0.880470889f, 0.474100215f, + -0.881921264f, 0.471396737f, + -0.883363339f, 0.468688822f, + -0.884797098f, 0.465976496f, + -0.886222530f, 0.463259784f, + -0.887639620f, 0.460538711f, + -0.889048356f, 0.457813304f, + -0.890448723f, 0.455083587f, + -0.891840709f, 0.452349587f, + -0.893224301f, 0.449611330f, + -0.894599486f, 0.446868840f, + -0.895966250f, 0.444122145f, + -0.897324581f, 0.441371269f, + -0.898674466f, 0.438616239f, + -0.900015892f, 0.435857080f, + -0.901348847f, 0.433093819f, + -0.902673318f, 0.430326481f, + -0.903989293f, 0.427555093f, + -0.905296759f, 0.424779681f, + -0.906595705f, 0.422000271f, + -0.907886116f, 0.419216888f, + -0.909167983f, 0.416429560f, + -0.910441292f, 0.413638312f, + -0.911706032f, 0.410843171f, + -0.912962190f, 0.408044163f, + -0.914209756f, 0.405241314f, + -0.915448716f, 0.402434651f, + -0.916679060f, 0.399624200f, + -0.917900776f, 0.396809987f, + -0.919113852f, 0.393992040f, + -0.920318277f, 0.391170384f, + -0.921514039f, 0.388345047f, + -0.922701128f, 0.385516054f, + -0.923879533f, 0.382683432f, + -0.925049241f, 0.379847209f, + -0.926210242f, 0.377007410f, + -0.927362526f, 0.374164063f, + -0.928506080f, 0.371317194f, + -0.929640896f, 0.368466830f, + -0.930766961f, 0.365612998f, + -0.931884266f, 0.362755724f, + -0.932992799f, 0.359895037f, + -0.934092550f, 0.357030961f, + -0.935183510f, 0.354163525f, + -0.936265667f, 0.351292756f, + -0.937339012f, 0.348418680f, + -0.938403534f, 0.345541325f, + -0.939459224f, 0.342660717f, + -0.940506071f, 0.339776884f, + -0.941544065f, 0.336889853f, + -0.942573198f, 0.333999651f, + -0.943593458f, 0.331106306f, + -0.944604837f, 0.328209844f, + -0.945607325f, 0.325310292f, + -0.946600913f, 0.322407679f, + -0.947585591f, 0.319502031f, + -0.948561350f, 0.316593376f, + -0.949528181f, 0.313681740f, + -0.950486074f, 0.310767153f, + -0.951435021f, 0.307849640f, + -0.952375013f, 0.304929230f, + -0.953306040f, 0.302005949f, + -0.954228095f, 0.299079826f, + -0.955141168f, 0.296150888f, + -0.956045251f, 0.293219163f, + -0.956940336f, 0.290284677f, + -0.957826413f, 0.287347460f, + -0.958703475f, 0.284407537f, + -0.959571513f, 0.281464938f, + -0.960430519f, 0.278519689f, + -0.961280486f, 0.275571819f, + -0.962121404f, 0.272621355f, + -0.962953267f, 0.269668326f, + -0.963776066f, 0.266712757f, + -0.964589793f, 0.263754679f, + -0.965394442f, 0.260794118f, + -0.966190003f, 0.257831102f, + -0.966976471f, 0.254865660f, + -0.967753837f, 0.251897818f, + -0.968522094f, 0.248927606f, + -0.969281235f, 0.245955050f, + -0.970031253f, 0.242980180f, + -0.970772141f, 0.240003022f, + -0.971503891f, 0.237023606f, + -0.972226497f, 0.234041959f, + -0.972939952f, 0.231058108f, + -0.973644250f, 0.228072083f, + -0.974339383f, 0.225083911f, + -0.975025345f, 0.222093621f, + -0.975702130f, 0.219101240f, + -0.976369731f, 0.216106797f, + -0.977028143f, 0.213110320f, + -0.977677358f, 0.210111837f, + -0.978317371f, 0.207111376f, + -0.978948175f, 0.204108966f, + -0.979569766f, 0.201104635f, + -0.980182136f, 0.198098411f, + -0.980785280f, 0.195090322f, + -0.981379193f, 0.192080397f, + -0.981963869f, 0.189068664f, + -0.982539302f, 0.186055152f, + -0.983105487f, 0.183039888f, + -0.983662419f, 0.180022901f, + -0.984210092f, 0.177004220f, + -0.984748502f, 0.173983873f, + -0.985277642f, 0.170961889f, + -0.985797509f, 0.167938295f, + -0.986308097f, 0.164913120f, + -0.986809402f, 0.161886394f, + -0.987301418f, 0.158858143f, + -0.987784142f, 0.155828398f, + -0.988257568f, 0.152797185f, + -0.988721692f, 0.149764535f, + -0.989176510f, 0.146730474f, + -0.989622017f, 0.143695033f, + -0.990058210f, 0.140658239f, + -0.990485084f, 0.137620122f, + -0.990902635f, 0.134580709f, + -0.991310860f, 0.131540029f, + -0.991709754f, 0.128498111f, + -0.992099313f, 0.125454983f, + -0.992479535f, 0.122410675f, + -0.992850414f, 0.119365215f, + -0.993211949f, 0.116318631f, + -0.993564136f, 0.113270952f, + -0.993906970f, 0.110222207f, + -0.994240449f, 0.107172425f, + -0.994564571f, 0.104121634f, + -0.994879331f, 0.101069863f, + -0.995184727f, 0.098017140f, + -0.995480755f, 0.094963495f, + -0.995767414f, 0.091908956f, + -0.996044701f, 0.088853553f, + -0.996312612f, 0.085797312f, + -0.996571146f, 0.082740265f, + -0.996820299f, 0.079682438f, + -0.997060070f, 0.076623861f, + -0.997290457f, 0.073564564f, + -0.997511456f, 0.070504573f, + -0.997723067f, 0.067443920f, + -0.997925286f, 0.064382631f, + -0.998118113f, 0.061320736f, + -0.998301545f, 0.058258265f, + -0.998475581f, 0.055195244f, + -0.998640218f, 0.052131705f, + -0.998795456f, 0.049067674f, + -0.998941293f, 0.046003182f, + -0.999077728f, 0.042938257f, + -0.999204759f, 0.039872928f, + -0.999322385f, 0.036807223f, + -0.999430605f, 0.033741172f, + -0.999529418f, 0.030674803f, + -0.999618822f, 0.027608146f, + -0.999698819f, 0.024541229f, + -0.999769405f, 0.021474080f, + -0.999830582f, 0.018406730f, + -0.999882347f, 0.015339206f, + -0.999924702f, 0.012271538f, + -0.999957645f, 0.009203755f, + -0.999981175f, 0.006135885f, + -0.999995294f, 0.003067957f, + -1.000000000f, 0.000000000f, + -0.999995294f, -0.003067957f, + -0.999981175f, -0.006135885f, + -0.999957645f, -0.009203755f, + -0.999924702f, -0.012271538f, + -0.999882347f, -0.015339206f, + -0.999830582f, -0.018406730f, + -0.999769405f, -0.021474080f, + -0.999698819f, -0.024541229f, + -0.999618822f, -0.027608146f, + -0.999529418f, -0.030674803f, + -0.999430605f, -0.033741172f, + -0.999322385f, -0.036807223f, + -0.999204759f, -0.039872928f, + -0.999077728f, -0.042938257f, + -0.998941293f, -0.046003182f, + -0.998795456f, -0.049067674f, + -0.998640218f, -0.052131705f, + -0.998475581f, -0.055195244f, + -0.998301545f, -0.058258265f, + -0.998118113f, -0.061320736f, + -0.997925286f, -0.064382631f, + -0.997723067f, -0.067443920f, + -0.997511456f, -0.070504573f, + -0.997290457f, -0.073564564f, + -0.997060070f, -0.076623861f, + -0.996820299f, -0.079682438f, + -0.996571146f, -0.082740265f, + -0.996312612f, -0.085797312f, + -0.996044701f, -0.088853553f, + -0.995767414f, -0.091908956f, + -0.995480755f, -0.094963495f, + -0.995184727f, -0.098017140f, + -0.994879331f, -0.101069863f, + -0.994564571f, -0.104121634f, + -0.994240449f, -0.107172425f, + -0.993906970f, -0.110222207f, + -0.993564136f, -0.113270952f, + -0.993211949f, -0.116318631f, + -0.992850414f, -0.119365215f, + -0.992479535f, -0.122410675f, + -0.992099313f, -0.125454983f, + -0.991709754f, -0.128498111f, + -0.991310860f, -0.131540029f, + -0.990902635f, -0.134580709f, + -0.990485084f, -0.137620122f, + -0.990058210f, -0.140658239f, + -0.989622017f, -0.143695033f, + -0.989176510f, -0.146730474f, + -0.988721692f, -0.149764535f, + -0.988257568f, -0.152797185f, + -0.987784142f, -0.155828398f, + -0.987301418f, -0.158858143f, + -0.986809402f, -0.161886394f, + -0.986308097f, -0.164913120f, + -0.985797509f, -0.167938295f, + -0.985277642f, -0.170961889f, + -0.984748502f, -0.173983873f, + -0.984210092f, -0.177004220f, + -0.983662419f, -0.180022901f, + -0.983105487f, -0.183039888f, + -0.982539302f, -0.186055152f, + -0.981963869f, -0.189068664f, + -0.981379193f, -0.192080397f, + -0.980785280f, -0.195090322f, + -0.980182136f, -0.198098411f, + -0.979569766f, -0.201104635f, + -0.978948175f, -0.204108966f, + -0.978317371f, -0.207111376f, + -0.977677358f, -0.210111837f, + -0.977028143f, -0.213110320f, + -0.976369731f, -0.216106797f, + -0.975702130f, -0.219101240f, + -0.975025345f, -0.222093621f, + -0.974339383f, -0.225083911f, + -0.973644250f, -0.228072083f, + -0.972939952f, -0.231058108f, + -0.972226497f, -0.234041959f, + -0.971503891f, -0.237023606f, + -0.970772141f, -0.240003022f, + -0.970031253f, -0.242980180f, + -0.969281235f, -0.245955050f, + -0.968522094f, -0.248927606f, + -0.967753837f, -0.251897818f, + -0.966976471f, -0.254865660f, + -0.966190003f, -0.257831102f, + -0.965394442f, -0.260794118f, + -0.964589793f, -0.263754679f, + -0.963776066f, -0.266712757f, + -0.962953267f, -0.269668326f, + -0.962121404f, -0.272621355f, + -0.961280486f, -0.275571819f, + -0.960430519f, -0.278519689f, + -0.959571513f, -0.281464938f, + -0.958703475f, -0.284407537f, + -0.957826413f, -0.287347460f, + -0.956940336f, -0.290284677f, + -0.956045251f, -0.293219163f, + -0.955141168f, -0.296150888f, + -0.954228095f, -0.299079826f, + -0.953306040f, -0.302005949f, + -0.952375013f, -0.304929230f, + -0.951435021f, -0.307849640f, + -0.950486074f, -0.310767153f, + -0.949528181f, -0.313681740f, + -0.948561350f, -0.316593376f, + -0.947585591f, -0.319502031f, + -0.946600913f, -0.322407679f, + -0.945607325f, -0.325310292f, + -0.944604837f, -0.328209844f, + -0.943593458f, -0.331106306f, + -0.942573198f, -0.333999651f, + -0.941544065f, -0.336889853f, + -0.940506071f, -0.339776884f, + -0.939459224f, -0.342660717f, + -0.938403534f, -0.345541325f, + -0.937339012f, -0.348418680f, + -0.936265667f, -0.351292756f, + -0.935183510f, -0.354163525f, + -0.934092550f, -0.357030961f, + -0.932992799f, -0.359895037f, + -0.931884266f, -0.362755724f, + -0.930766961f, -0.365612998f, + -0.929640896f, -0.368466830f, + -0.928506080f, -0.371317194f, + -0.927362526f, -0.374164063f, + -0.926210242f, -0.377007410f, + -0.925049241f, -0.379847209f, + -0.923879533f, -0.382683432f, + -0.922701128f, -0.385516054f, + -0.921514039f, -0.388345047f, + -0.920318277f, -0.391170384f, + -0.919113852f, -0.393992040f, + -0.917900776f, -0.396809987f, + -0.916679060f, -0.399624200f, + -0.915448716f, -0.402434651f, + -0.914209756f, -0.405241314f, + -0.912962190f, -0.408044163f, + -0.911706032f, -0.410843171f, + -0.910441292f, -0.413638312f, + -0.909167983f, -0.416429560f, + -0.907886116f, -0.419216888f, + -0.906595705f, -0.422000271f, + -0.905296759f, -0.424779681f, + -0.903989293f, -0.427555093f, + -0.902673318f, -0.430326481f, + -0.901348847f, -0.433093819f, + -0.900015892f, -0.435857080f, + -0.898674466f, -0.438616239f, + -0.897324581f, -0.441371269f, + -0.895966250f, -0.444122145f, + -0.894599486f, -0.446868840f, + -0.893224301f, -0.449611330f, + -0.891840709f, -0.452349587f, + -0.890448723f, -0.455083587f, + -0.889048356f, -0.457813304f, + -0.887639620f, -0.460538711f, + -0.886222530f, -0.463259784f, + -0.884797098f, -0.465976496f, + -0.883363339f, -0.468688822f, + -0.881921264f, -0.471396737f, + -0.880470889f, -0.474100215f, + -0.879012226f, -0.476799230f, + -0.877545290f, -0.479493758f, + -0.876070094f, -0.482183772f, + -0.874586652f, -0.484869248f, + -0.873094978f, -0.487550160f, + -0.871595087f, -0.490226483f, + -0.870086991f, -0.492898192f, + -0.868570706f, -0.495565262f, + -0.867046246f, -0.498227667f, + -0.865513624f, -0.500885383f, + -0.863972856f, -0.503538384f, + -0.862423956f, -0.506186645f, + -0.860866939f, -0.508830143f, + -0.859301818f, -0.511468850f, + -0.857728610f, -0.514102744f, + -0.856147328f, -0.516731799f, + -0.854557988f, -0.519355990f, + -0.852960605f, -0.521975293f, + -0.851355193f, -0.524589683f, + -0.849741768f, -0.527199135f, + -0.848120345f, -0.529803625f, + -0.846490939f, -0.532403128f, + -0.844853565f, -0.534997620f, + -0.843208240f, -0.537587076f, + -0.841554977f, -0.540171473f, + -0.839893794f, -0.542750785f, + -0.838224706f, -0.545324988f, + -0.836547727f, -0.547894059f, + -0.834862875f, -0.550457973f, + -0.833170165f, -0.553016706f, + -0.831469612f, -0.555570233f, + -0.829761234f, -0.558118531f, + -0.828045045f, -0.560661576f, + -0.826321063f, -0.563199344f, + -0.824589303f, -0.565731811f, + -0.822849781f, -0.568258953f, + -0.821102515f, -0.570780746f, + -0.819347520f, -0.573297167f, + -0.817584813f, -0.575808191f, + -0.815814411f, -0.578313796f, + -0.814036330f, -0.580813958f, + -0.812250587f, -0.583308653f, + -0.810457198f, -0.585797857f, + -0.808656182f, -0.588281548f, + -0.806847554f, -0.590759702f, + -0.805031331f, -0.593232295f, + -0.803207531f, -0.595699304f, + -0.801376172f, -0.598160707f, + -0.799537269f, -0.600616479f, + -0.797690841f, -0.603066599f, + -0.795836905f, -0.605511041f, + -0.793975478f, -0.607949785f, + -0.792106577f, -0.610382806f, + -0.790230221f, -0.612810082f, + -0.788346428f, -0.615231591f, + -0.786455214f, -0.617647308f, + -0.784556597f, -0.620057212f, + -0.782650596f, -0.622461279f, + -0.780737229f, -0.624859488f, + -0.778816512f, -0.627251815f, + -0.776888466f, -0.629638239f, + -0.774953107f, -0.632018736f, + -0.773010453f, -0.634393284f, + -0.771060524f, -0.636761861f, + -0.769103338f, -0.639124445f, + -0.767138912f, -0.641481013f, + -0.765167266f, -0.643831543f, + -0.763188417f, -0.646176013f, + -0.761202385f, -0.648514401f, + -0.759209189f, -0.650846685f, + -0.757208847f, -0.653172843f, + -0.755201377f, -0.655492853f, + -0.753186799f, -0.657806693f, + -0.751165132f, -0.660114342f, + -0.749136395f, -0.662415778f, + -0.747100606f, -0.664710978f, + -0.745057785f, -0.666999922f, + -0.743007952f, -0.669282588f, + -0.740951125f, -0.671558955f, + -0.738887324f, -0.673829000f, + -0.736816569f, -0.676092704f, + -0.734738878f, -0.678350043f, + -0.732654272f, -0.680600998f, + -0.730562769f, -0.682845546f, + -0.728464390f, -0.685083668f, + -0.726359155f, -0.687315341f, + -0.724247083f, -0.689540545f, + -0.722128194f, -0.691759258f, + -0.720002508f, -0.693971461f, + -0.717870045f, -0.696177131f, + -0.715730825f, -0.698376249f, + -0.713584869f, -0.700568794f, + -0.711432196f, -0.702754744f, + -0.709272826f, -0.704934080f, + -0.707106781f, -0.707106781f, + -0.704934080f, -0.709272826f, + -0.702754744f, -0.711432196f, + -0.700568794f, -0.713584869f, + -0.698376249f, -0.715730825f, + -0.696177131f, -0.717870045f, + -0.693971461f, -0.720002508f, + -0.691759258f, -0.722128194f, + -0.689540545f, -0.724247083f, + -0.687315341f, -0.726359155f, + -0.685083668f, -0.728464390f, + -0.682845546f, -0.730562769f, + -0.680600998f, -0.732654272f, + -0.678350043f, -0.734738878f, + -0.676092704f, -0.736816569f, + -0.673829000f, -0.738887324f, + -0.671558955f, -0.740951125f, + -0.669282588f, -0.743007952f, + -0.666999922f, -0.745057785f, + -0.664710978f, -0.747100606f, + -0.662415778f, -0.749136395f, + -0.660114342f, -0.751165132f, + -0.657806693f, -0.753186799f, + -0.655492853f, -0.755201377f, + -0.653172843f, -0.757208847f, + -0.650846685f, -0.759209189f, + -0.648514401f, -0.761202385f, + -0.646176013f, -0.763188417f, + -0.643831543f, -0.765167266f, + -0.641481013f, -0.767138912f, + -0.639124445f, -0.769103338f, + -0.636761861f, -0.771060524f, + -0.634393284f, -0.773010453f, + -0.632018736f, -0.774953107f, + -0.629638239f, -0.776888466f, + -0.627251815f, -0.778816512f, + -0.624859488f, -0.780737229f, + -0.622461279f, -0.782650596f, + -0.620057212f, -0.784556597f, + -0.617647308f, -0.786455214f, + -0.615231591f, -0.788346428f, + -0.612810082f, -0.790230221f, + -0.610382806f, -0.792106577f, + -0.607949785f, -0.793975478f, + -0.605511041f, -0.795836905f, + -0.603066599f, -0.797690841f, + -0.600616479f, -0.799537269f, + -0.598160707f, -0.801376172f, + -0.595699304f, -0.803207531f, + -0.593232295f, -0.805031331f, + -0.590759702f, -0.806847554f, + -0.588281548f, -0.808656182f, + -0.585797857f, -0.810457198f, + -0.583308653f, -0.812250587f, + -0.580813958f, -0.814036330f, + -0.578313796f, -0.815814411f, + -0.575808191f, -0.817584813f, + -0.573297167f, -0.819347520f, + -0.570780746f, -0.821102515f, + -0.568258953f, -0.822849781f, + -0.565731811f, -0.824589303f, + -0.563199344f, -0.826321063f, + -0.560661576f, -0.828045045f, + -0.558118531f, -0.829761234f, + -0.555570233f, -0.831469612f, + -0.553016706f, -0.833170165f, + -0.550457973f, -0.834862875f, + -0.547894059f, -0.836547727f, + -0.545324988f, -0.838224706f, + -0.542750785f, -0.839893794f, + -0.540171473f, -0.841554977f, + -0.537587076f, -0.843208240f, + -0.534997620f, -0.844853565f, + -0.532403128f, -0.846490939f, + -0.529803625f, -0.848120345f, + -0.527199135f, -0.849741768f, + -0.524589683f, -0.851355193f, + -0.521975293f, -0.852960605f, + -0.519355990f, -0.854557988f, + -0.516731799f, -0.856147328f, + -0.514102744f, -0.857728610f, + -0.511468850f, -0.859301818f, + -0.508830143f, -0.860866939f, + -0.506186645f, -0.862423956f, + -0.503538384f, -0.863972856f, + -0.500885383f, -0.865513624f, + -0.498227667f, -0.867046246f, + -0.495565262f, -0.868570706f, + -0.492898192f, -0.870086991f, + -0.490226483f, -0.871595087f, + -0.487550160f, -0.873094978f, + -0.484869248f, -0.874586652f, + -0.482183772f, -0.876070094f, + -0.479493758f, -0.877545290f, + -0.476799230f, -0.879012226f, + -0.474100215f, -0.880470889f, + -0.471396737f, -0.881921264f, + -0.468688822f, -0.883363339f, + -0.465976496f, -0.884797098f, + -0.463259784f, -0.886222530f, + -0.460538711f, -0.887639620f, + -0.457813304f, -0.889048356f, + -0.455083587f, -0.890448723f, + -0.452349587f, -0.891840709f, + -0.449611330f, -0.893224301f, + -0.446868840f, -0.894599486f, + -0.444122145f, -0.895966250f, + -0.441371269f, -0.897324581f, + -0.438616239f, -0.898674466f, + -0.435857080f, -0.900015892f, + -0.433093819f, -0.901348847f, + -0.430326481f, -0.902673318f, + -0.427555093f, -0.903989293f, + -0.424779681f, -0.905296759f, + -0.422000271f, -0.906595705f, + -0.419216888f, -0.907886116f, + -0.416429560f, -0.909167983f, + -0.413638312f, -0.910441292f, + -0.410843171f, -0.911706032f, + -0.408044163f, -0.912962190f, + -0.405241314f, -0.914209756f, + -0.402434651f, -0.915448716f, + -0.399624200f, -0.916679060f, + -0.396809987f, -0.917900776f, + -0.393992040f, -0.919113852f, + -0.391170384f, -0.920318277f, + -0.388345047f, -0.921514039f, + -0.385516054f, -0.922701128f, + -0.382683432f, -0.923879533f, + -0.379847209f, -0.925049241f, + -0.377007410f, -0.926210242f, + -0.374164063f, -0.927362526f, + -0.371317194f, -0.928506080f, + -0.368466830f, -0.929640896f, + -0.365612998f, -0.930766961f, + -0.362755724f, -0.931884266f, + -0.359895037f, -0.932992799f, + -0.357030961f, -0.934092550f, + -0.354163525f, -0.935183510f, + -0.351292756f, -0.936265667f, + -0.348418680f, -0.937339012f, + -0.345541325f, -0.938403534f, + -0.342660717f, -0.939459224f, + -0.339776884f, -0.940506071f, + -0.336889853f, -0.941544065f, + -0.333999651f, -0.942573198f, + -0.331106306f, -0.943593458f, + -0.328209844f, -0.944604837f, + -0.325310292f, -0.945607325f, + -0.322407679f, -0.946600913f, + -0.319502031f, -0.947585591f, + -0.316593376f, -0.948561350f, + -0.313681740f, -0.949528181f, + -0.310767153f, -0.950486074f, + -0.307849640f, -0.951435021f, + -0.304929230f, -0.952375013f, + -0.302005949f, -0.953306040f, + -0.299079826f, -0.954228095f, + -0.296150888f, -0.955141168f, + -0.293219163f, -0.956045251f, + -0.290284677f, -0.956940336f, + -0.287347460f, -0.957826413f, + -0.284407537f, -0.958703475f, + -0.281464938f, -0.959571513f, + -0.278519689f, -0.960430519f, + -0.275571819f, -0.961280486f, + -0.272621355f, -0.962121404f, + -0.269668326f, -0.962953267f, + -0.266712757f, -0.963776066f, + -0.263754679f, -0.964589793f, + -0.260794118f, -0.965394442f, + -0.257831102f, -0.966190003f, + -0.254865660f, -0.966976471f, + -0.251897818f, -0.967753837f, + -0.248927606f, -0.968522094f, + -0.245955050f, -0.969281235f, + -0.242980180f, -0.970031253f, + -0.240003022f, -0.970772141f, + -0.237023606f, -0.971503891f, + -0.234041959f, -0.972226497f, + -0.231058108f, -0.972939952f, + -0.228072083f, -0.973644250f, + -0.225083911f, -0.974339383f, + -0.222093621f, -0.975025345f, + -0.219101240f, -0.975702130f, + -0.216106797f, -0.976369731f, + -0.213110320f, -0.977028143f, + -0.210111837f, -0.977677358f, + -0.207111376f, -0.978317371f, + -0.204108966f, -0.978948175f, + -0.201104635f, -0.979569766f, + -0.198098411f, -0.980182136f, + -0.195090322f, -0.980785280f, + -0.192080397f, -0.981379193f, + -0.189068664f, -0.981963869f, + -0.186055152f, -0.982539302f, + -0.183039888f, -0.983105487f, + -0.180022901f, -0.983662419f, + -0.177004220f, -0.984210092f, + -0.173983873f, -0.984748502f, + -0.170961889f, -0.985277642f, + -0.167938295f, -0.985797509f, + -0.164913120f, -0.986308097f, + -0.161886394f, -0.986809402f, + -0.158858143f, -0.987301418f, + -0.155828398f, -0.987784142f, + -0.152797185f, -0.988257568f, + -0.149764535f, -0.988721692f, + -0.146730474f, -0.989176510f, + -0.143695033f, -0.989622017f, + -0.140658239f, -0.990058210f, + -0.137620122f, -0.990485084f, + -0.134580709f, -0.990902635f, + -0.131540029f, -0.991310860f, + -0.128498111f, -0.991709754f, + -0.125454983f, -0.992099313f, + -0.122410675f, -0.992479535f, + -0.119365215f, -0.992850414f, + -0.116318631f, -0.993211949f, + -0.113270952f, -0.993564136f, + -0.110222207f, -0.993906970f, + -0.107172425f, -0.994240449f, + -0.104121634f, -0.994564571f, + -0.101069863f, -0.994879331f, + -0.098017140f, -0.995184727f, + -0.094963495f, -0.995480755f, + -0.091908956f, -0.995767414f, + -0.088853553f, -0.996044701f, + -0.085797312f, -0.996312612f, + -0.082740265f, -0.996571146f, + -0.079682438f, -0.996820299f, + -0.076623861f, -0.997060070f, + -0.073564564f, -0.997290457f, + -0.070504573f, -0.997511456f, + -0.067443920f, -0.997723067f, + -0.064382631f, -0.997925286f, + -0.061320736f, -0.998118113f, + -0.058258265f, -0.998301545f, + -0.055195244f, -0.998475581f, + -0.052131705f, -0.998640218f, + -0.049067674f, -0.998795456f, + -0.046003182f, -0.998941293f, + -0.042938257f, -0.999077728f, + -0.039872928f, -0.999204759f, + -0.036807223f, -0.999322385f, + -0.033741172f, -0.999430605f, + -0.030674803f, -0.999529418f, + -0.027608146f, -0.999618822f, + -0.024541229f, -0.999698819f, + -0.021474080f, -0.999769405f, + -0.018406730f, -0.999830582f, + -0.015339206f, -0.999882347f, + -0.012271538f, -0.999924702f, + -0.009203755f, -0.999957645f, + -0.006135885f, -0.999981175f, + -0.003067957f, -0.999995294f, + -0.000000000f, -1.000000000f, + 0.003067957f, -0.999995294f, + 0.006135885f, -0.999981175f, + 0.009203755f, -0.999957645f, + 0.012271538f, -0.999924702f, + 0.015339206f, -0.999882347f, + 0.018406730f, -0.999830582f, + 0.021474080f, -0.999769405f, + 0.024541229f, -0.999698819f, + 0.027608146f, -0.999618822f, + 0.030674803f, -0.999529418f, + 0.033741172f, -0.999430605f, + 0.036807223f, -0.999322385f, + 0.039872928f, -0.999204759f, + 0.042938257f, -0.999077728f, + 0.046003182f, -0.998941293f, + 0.049067674f, -0.998795456f, + 0.052131705f, -0.998640218f, + 0.055195244f, -0.998475581f, + 0.058258265f, -0.998301545f, + 0.061320736f, -0.998118113f, + 0.064382631f, -0.997925286f, + 0.067443920f, -0.997723067f, + 0.070504573f, -0.997511456f, + 0.073564564f, -0.997290457f, + 0.076623861f, -0.997060070f, + 0.079682438f, -0.996820299f, + 0.082740265f, -0.996571146f, + 0.085797312f, -0.996312612f, + 0.088853553f, -0.996044701f, + 0.091908956f, -0.995767414f, + 0.094963495f, -0.995480755f, + 0.098017140f, -0.995184727f, + 0.101069863f, -0.994879331f, + 0.104121634f, -0.994564571f, + 0.107172425f, -0.994240449f, + 0.110222207f, -0.993906970f, + 0.113270952f, -0.993564136f, + 0.116318631f, -0.993211949f, + 0.119365215f, -0.992850414f, + 0.122410675f, -0.992479535f, + 0.125454983f, -0.992099313f, + 0.128498111f, -0.991709754f, + 0.131540029f, -0.991310860f, + 0.134580709f, -0.990902635f, + 0.137620122f, -0.990485084f, + 0.140658239f, -0.990058210f, + 0.143695033f, -0.989622017f, + 0.146730474f, -0.989176510f, + 0.149764535f, -0.988721692f, + 0.152797185f, -0.988257568f, + 0.155828398f, -0.987784142f, + 0.158858143f, -0.987301418f, + 0.161886394f, -0.986809402f, + 0.164913120f, -0.986308097f, + 0.167938295f, -0.985797509f, + 0.170961889f, -0.985277642f, + 0.173983873f, -0.984748502f, + 0.177004220f, -0.984210092f, + 0.180022901f, -0.983662419f, + 0.183039888f, -0.983105487f, + 0.186055152f, -0.982539302f, + 0.189068664f, -0.981963869f, + 0.192080397f, -0.981379193f, + 0.195090322f, -0.980785280f, + 0.198098411f, -0.980182136f, + 0.201104635f, -0.979569766f, + 0.204108966f, -0.978948175f, + 0.207111376f, -0.978317371f, + 0.210111837f, -0.977677358f, + 0.213110320f, -0.977028143f, + 0.216106797f, -0.976369731f, + 0.219101240f, -0.975702130f, + 0.222093621f, -0.975025345f, + 0.225083911f, -0.974339383f, + 0.228072083f, -0.973644250f, + 0.231058108f, -0.972939952f, + 0.234041959f, -0.972226497f, + 0.237023606f, -0.971503891f, + 0.240003022f, -0.970772141f, + 0.242980180f, -0.970031253f, + 0.245955050f, -0.969281235f, + 0.248927606f, -0.968522094f, + 0.251897818f, -0.967753837f, + 0.254865660f, -0.966976471f, + 0.257831102f, -0.966190003f, + 0.260794118f, -0.965394442f, + 0.263754679f, -0.964589793f, + 0.266712757f, -0.963776066f, + 0.269668326f, -0.962953267f, + 0.272621355f, -0.962121404f, + 0.275571819f, -0.961280486f, + 0.278519689f, -0.960430519f, + 0.281464938f, -0.959571513f, + 0.284407537f, -0.958703475f, + 0.287347460f, -0.957826413f, + 0.290284677f, -0.956940336f, + 0.293219163f, -0.956045251f, + 0.296150888f, -0.955141168f, + 0.299079826f, -0.954228095f, + 0.302005949f, -0.953306040f, + 0.304929230f, -0.952375013f, + 0.307849640f, -0.951435021f, + 0.310767153f, -0.950486074f, + 0.313681740f, -0.949528181f, + 0.316593376f, -0.948561350f, + 0.319502031f, -0.947585591f, + 0.322407679f, -0.946600913f, + 0.325310292f, -0.945607325f, + 0.328209844f, -0.944604837f, + 0.331106306f, -0.943593458f, + 0.333999651f, -0.942573198f, + 0.336889853f, -0.941544065f, + 0.339776884f, -0.940506071f, + 0.342660717f, -0.939459224f, + 0.345541325f, -0.938403534f, + 0.348418680f, -0.937339012f, + 0.351292756f, -0.936265667f, + 0.354163525f, -0.935183510f, + 0.357030961f, -0.934092550f, + 0.359895037f, -0.932992799f, + 0.362755724f, -0.931884266f, + 0.365612998f, -0.930766961f, + 0.368466830f, -0.929640896f, + 0.371317194f, -0.928506080f, + 0.374164063f, -0.927362526f, + 0.377007410f, -0.926210242f, + 0.379847209f, -0.925049241f, + 0.382683432f, -0.923879533f, + 0.385516054f, -0.922701128f, + 0.388345047f, -0.921514039f, + 0.391170384f, -0.920318277f, + 0.393992040f, -0.919113852f, + 0.396809987f, -0.917900776f, + 0.399624200f, -0.916679060f, + 0.402434651f, -0.915448716f, + 0.405241314f, -0.914209756f, + 0.408044163f, -0.912962190f, + 0.410843171f, -0.911706032f, + 0.413638312f, -0.910441292f, + 0.416429560f, -0.909167983f, + 0.419216888f, -0.907886116f, + 0.422000271f, -0.906595705f, + 0.424779681f, -0.905296759f, + 0.427555093f, -0.903989293f, + 0.430326481f, -0.902673318f, + 0.433093819f, -0.901348847f, + 0.435857080f, -0.900015892f, + 0.438616239f, -0.898674466f, + 0.441371269f, -0.897324581f, + 0.444122145f, -0.895966250f, + 0.446868840f, -0.894599486f, + 0.449611330f, -0.893224301f, + 0.452349587f, -0.891840709f, + 0.455083587f, -0.890448723f, + 0.457813304f, -0.889048356f, + 0.460538711f, -0.887639620f, + 0.463259784f, -0.886222530f, + 0.465976496f, -0.884797098f, + 0.468688822f, -0.883363339f, + 0.471396737f, -0.881921264f, + 0.474100215f, -0.880470889f, + 0.476799230f, -0.879012226f, + 0.479493758f, -0.877545290f, + 0.482183772f, -0.876070094f, + 0.484869248f, -0.874586652f, + 0.487550160f, -0.873094978f, + 0.490226483f, -0.871595087f, + 0.492898192f, -0.870086991f, + 0.495565262f, -0.868570706f, + 0.498227667f, -0.867046246f, + 0.500885383f, -0.865513624f, + 0.503538384f, -0.863972856f, + 0.506186645f, -0.862423956f, + 0.508830143f, -0.860866939f, + 0.511468850f, -0.859301818f, + 0.514102744f, -0.857728610f, + 0.516731799f, -0.856147328f, + 0.519355990f, -0.854557988f, + 0.521975293f, -0.852960605f, + 0.524589683f, -0.851355193f, + 0.527199135f, -0.849741768f, + 0.529803625f, -0.848120345f, + 0.532403128f, -0.846490939f, + 0.534997620f, -0.844853565f, + 0.537587076f, -0.843208240f, + 0.540171473f, -0.841554977f, + 0.542750785f, -0.839893794f, + 0.545324988f, -0.838224706f, + 0.547894059f, -0.836547727f, + 0.550457973f, -0.834862875f, + 0.553016706f, -0.833170165f, + 0.555570233f, -0.831469612f, + 0.558118531f, -0.829761234f, + 0.560661576f, -0.828045045f, + 0.563199344f, -0.826321063f, + 0.565731811f, -0.824589303f, + 0.568258953f, -0.822849781f, + 0.570780746f, -0.821102515f, + 0.573297167f, -0.819347520f, + 0.575808191f, -0.817584813f, + 0.578313796f, -0.815814411f, + 0.580813958f, -0.814036330f, + 0.583308653f, -0.812250587f, + 0.585797857f, -0.810457198f, + 0.588281548f, -0.808656182f, + 0.590759702f, -0.806847554f, + 0.593232295f, -0.805031331f, + 0.595699304f, -0.803207531f, + 0.598160707f, -0.801376172f, + 0.600616479f, -0.799537269f, + 0.603066599f, -0.797690841f, + 0.605511041f, -0.795836905f, + 0.607949785f, -0.793975478f, + 0.610382806f, -0.792106577f, + 0.612810082f, -0.790230221f, + 0.615231591f, -0.788346428f, + 0.617647308f, -0.786455214f, + 0.620057212f, -0.784556597f, + 0.622461279f, -0.782650596f, + 0.624859488f, -0.780737229f, + 0.627251815f, -0.778816512f, + 0.629638239f, -0.776888466f, + 0.632018736f, -0.774953107f, + 0.634393284f, -0.773010453f, + 0.636761861f, -0.771060524f, + 0.639124445f, -0.769103338f, + 0.641481013f, -0.767138912f, + 0.643831543f, -0.765167266f, + 0.646176013f, -0.763188417f, + 0.648514401f, -0.761202385f, + 0.650846685f, -0.759209189f, + 0.653172843f, -0.757208847f, + 0.655492853f, -0.755201377f, + 0.657806693f, -0.753186799f, + 0.660114342f, -0.751165132f, + 0.662415778f, -0.749136395f, + 0.664710978f, -0.747100606f, + 0.666999922f, -0.745057785f, + 0.669282588f, -0.743007952f, + 0.671558955f, -0.740951125f, + 0.673829000f, -0.738887324f, + 0.676092704f, -0.736816569f, + 0.678350043f, -0.734738878f, + 0.680600998f, -0.732654272f, + 0.682845546f, -0.730562769f, + 0.685083668f, -0.728464390f, + 0.687315341f, -0.726359155f, + 0.689540545f, -0.724247083f, + 0.691759258f, -0.722128194f, + 0.693971461f, -0.720002508f, + 0.696177131f, -0.717870045f, + 0.698376249f, -0.715730825f, + 0.700568794f, -0.713584869f, + 0.702754744f, -0.711432196f, + 0.704934080f, -0.709272826f, + 0.707106781f, -0.707106781f, + 0.709272826f, -0.704934080f, + 0.711432196f, -0.702754744f, + 0.713584869f, -0.700568794f, + 0.715730825f, -0.698376249f, + 0.717870045f, -0.696177131f, + 0.720002508f, -0.693971461f, + 0.722128194f, -0.691759258f, + 0.724247083f, -0.689540545f, + 0.726359155f, -0.687315341f, + 0.728464390f, -0.685083668f, + 0.730562769f, -0.682845546f, + 0.732654272f, -0.680600998f, + 0.734738878f, -0.678350043f, + 0.736816569f, -0.676092704f, + 0.738887324f, -0.673829000f, + 0.740951125f, -0.671558955f, + 0.743007952f, -0.669282588f, + 0.745057785f, -0.666999922f, + 0.747100606f, -0.664710978f, + 0.749136395f, -0.662415778f, + 0.751165132f, -0.660114342f, + 0.753186799f, -0.657806693f, + 0.755201377f, -0.655492853f, + 0.757208847f, -0.653172843f, + 0.759209189f, -0.650846685f, + 0.761202385f, -0.648514401f, + 0.763188417f, -0.646176013f, + 0.765167266f, -0.643831543f, + 0.767138912f, -0.641481013f, + 0.769103338f, -0.639124445f, + 0.771060524f, -0.636761861f, + 0.773010453f, -0.634393284f, + 0.774953107f, -0.632018736f, + 0.776888466f, -0.629638239f, + 0.778816512f, -0.627251815f, + 0.780737229f, -0.624859488f, + 0.782650596f, -0.622461279f, + 0.784556597f, -0.620057212f, + 0.786455214f, -0.617647308f, + 0.788346428f, -0.615231591f, + 0.790230221f, -0.612810082f, + 0.792106577f, -0.610382806f, + 0.793975478f, -0.607949785f, + 0.795836905f, -0.605511041f, + 0.797690841f, -0.603066599f, + 0.799537269f, -0.600616479f, + 0.801376172f, -0.598160707f, + 0.803207531f, -0.595699304f, + 0.805031331f, -0.593232295f, + 0.806847554f, -0.590759702f, + 0.808656182f, -0.588281548f, + 0.810457198f, -0.585797857f, + 0.812250587f, -0.583308653f, + 0.814036330f, -0.580813958f, + 0.815814411f, -0.578313796f, + 0.817584813f, -0.575808191f, + 0.819347520f, -0.573297167f, + 0.821102515f, -0.570780746f, + 0.822849781f, -0.568258953f, + 0.824589303f, -0.565731811f, + 0.826321063f, -0.563199344f, + 0.828045045f, -0.560661576f, + 0.829761234f, -0.558118531f, + 0.831469612f, -0.555570233f, + 0.833170165f, -0.553016706f, + 0.834862875f, -0.550457973f, + 0.836547727f, -0.547894059f, + 0.838224706f, -0.545324988f, + 0.839893794f, -0.542750785f, + 0.841554977f, -0.540171473f, + 0.843208240f, -0.537587076f, + 0.844853565f, -0.534997620f, + 0.846490939f, -0.532403128f, + 0.848120345f, -0.529803625f, + 0.849741768f, -0.527199135f, + 0.851355193f, -0.524589683f, + 0.852960605f, -0.521975293f, + 0.854557988f, -0.519355990f, + 0.856147328f, -0.516731799f, + 0.857728610f, -0.514102744f, + 0.859301818f, -0.511468850f, + 0.860866939f, -0.508830143f, + 0.862423956f, -0.506186645f, + 0.863972856f, -0.503538384f, + 0.865513624f, -0.500885383f, + 0.867046246f, -0.498227667f, + 0.868570706f, -0.495565262f, + 0.870086991f, -0.492898192f, + 0.871595087f, -0.490226483f, + 0.873094978f, -0.487550160f, + 0.874586652f, -0.484869248f, + 0.876070094f, -0.482183772f, + 0.877545290f, -0.479493758f, + 0.879012226f, -0.476799230f, + 0.880470889f, -0.474100215f, + 0.881921264f, -0.471396737f, + 0.883363339f, -0.468688822f, + 0.884797098f, -0.465976496f, + 0.886222530f, -0.463259784f, + 0.887639620f, -0.460538711f, + 0.889048356f, -0.457813304f, + 0.890448723f, -0.455083587f, + 0.891840709f, -0.452349587f, + 0.893224301f, -0.449611330f, + 0.894599486f, -0.446868840f, + 0.895966250f, -0.444122145f, + 0.897324581f, -0.441371269f, + 0.898674466f, -0.438616239f, + 0.900015892f, -0.435857080f, + 0.901348847f, -0.433093819f, + 0.902673318f, -0.430326481f, + 0.903989293f, -0.427555093f, + 0.905296759f, -0.424779681f, + 0.906595705f, -0.422000271f, + 0.907886116f, -0.419216888f, + 0.909167983f, -0.416429560f, + 0.910441292f, -0.413638312f, + 0.911706032f, -0.410843171f, + 0.912962190f, -0.408044163f, + 0.914209756f, -0.405241314f, + 0.915448716f, -0.402434651f, + 0.916679060f, -0.399624200f, + 0.917900776f, -0.396809987f, + 0.919113852f, -0.393992040f, + 0.920318277f, -0.391170384f, + 0.921514039f, -0.388345047f, + 0.922701128f, -0.385516054f, + 0.923879533f, -0.382683432f, + 0.925049241f, -0.379847209f, + 0.926210242f, -0.377007410f, + 0.927362526f, -0.374164063f, + 0.928506080f, -0.371317194f, + 0.929640896f, -0.368466830f, + 0.930766961f, -0.365612998f, + 0.931884266f, -0.362755724f, + 0.932992799f, -0.359895037f, + 0.934092550f, -0.357030961f, + 0.935183510f, -0.354163525f, + 0.936265667f, -0.351292756f, + 0.937339012f, -0.348418680f, + 0.938403534f, -0.345541325f, + 0.939459224f, -0.342660717f, + 0.940506071f, -0.339776884f, + 0.941544065f, -0.336889853f, + 0.942573198f, -0.333999651f, + 0.943593458f, -0.331106306f, + 0.944604837f, -0.328209844f, + 0.945607325f, -0.325310292f, + 0.946600913f, -0.322407679f, + 0.947585591f, -0.319502031f, + 0.948561350f, -0.316593376f, + 0.949528181f, -0.313681740f, + 0.950486074f, -0.310767153f, + 0.951435021f, -0.307849640f, + 0.952375013f, -0.304929230f, + 0.953306040f, -0.302005949f, + 0.954228095f, -0.299079826f, + 0.955141168f, -0.296150888f, + 0.956045251f, -0.293219163f, + 0.956940336f, -0.290284677f, + 0.957826413f, -0.287347460f, + 0.958703475f, -0.284407537f, + 0.959571513f, -0.281464938f, + 0.960430519f, -0.278519689f, + 0.961280486f, -0.275571819f, + 0.962121404f, -0.272621355f, + 0.962953267f, -0.269668326f, + 0.963776066f, -0.266712757f, + 0.964589793f, -0.263754679f, + 0.965394442f, -0.260794118f, + 0.966190003f, -0.257831102f, + 0.966976471f, -0.254865660f, + 0.967753837f, -0.251897818f, + 0.968522094f, -0.248927606f, + 0.969281235f, -0.245955050f, + 0.970031253f, -0.242980180f, + 0.970772141f, -0.240003022f, + 0.971503891f, -0.237023606f, + 0.972226497f, -0.234041959f, + 0.972939952f, -0.231058108f, + 0.973644250f, -0.228072083f, + 0.974339383f, -0.225083911f, + 0.975025345f, -0.222093621f, + 0.975702130f, -0.219101240f, + 0.976369731f, -0.216106797f, + 0.977028143f, -0.213110320f, + 0.977677358f, -0.210111837f, + 0.978317371f, -0.207111376f, + 0.978948175f, -0.204108966f, + 0.979569766f, -0.201104635f, + 0.980182136f, -0.198098411f, + 0.980785280f, -0.195090322f, + 0.981379193f, -0.192080397f, + 0.981963869f, -0.189068664f, + 0.982539302f, -0.186055152f, + 0.983105487f, -0.183039888f, + 0.983662419f, -0.180022901f, + 0.984210092f, -0.177004220f, + 0.984748502f, -0.173983873f, + 0.985277642f, -0.170961889f, + 0.985797509f, -0.167938295f, + 0.986308097f, -0.164913120f, + 0.986809402f, -0.161886394f, + 0.987301418f, -0.158858143f, + 0.987784142f, -0.155828398f, + 0.988257568f, -0.152797185f, + 0.988721692f, -0.149764535f, + 0.989176510f, -0.146730474f, + 0.989622017f, -0.143695033f, + 0.990058210f, -0.140658239f, + 0.990485084f, -0.137620122f, + 0.990902635f, -0.134580709f, + 0.991310860f, -0.131540029f, + 0.991709754f, -0.128498111f, + 0.992099313f, -0.125454983f, + 0.992479535f, -0.122410675f, + 0.992850414f, -0.119365215f, + 0.993211949f, -0.116318631f, + 0.993564136f, -0.113270952f, + 0.993906970f, -0.110222207f, + 0.994240449f, -0.107172425f, + 0.994564571f, -0.104121634f, + 0.994879331f, -0.101069863f, + 0.995184727f, -0.098017140f, + 0.995480755f, -0.094963495f, + 0.995767414f, -0.091908956f, + 0.996044701f, -0.088853553f, + 0.996312612f, -0.085797312f, + 0.996571146f, -0.082740265f, + 0.996820299f, -0.079682438f, + 0.997060070f, -0.076623861f, + 0.997290457f, -0.073564564f, + 0.997511456f, -0.070504573f, + 0.997723067f, -0.067443920f, + 0.997925286f, -0.064382631f, + 0.998118113f, -0.061320736f, + 0.998301545f, -0.058258265f, + 0.998475581f, -0.055195244f, + 0.998640218f, -0.052131705f, + 0.998795456f, -0.049067674f, + 0.998941293f, -0.046003182f, + 0.999077728f, -0.042938257f, + 0.999204759f, -0.039872928f, + 0.999322385f, -0.036807223f, + 0.999430605f, -0.033741172f, + 0.999529418f, -0.030674803f, + 0.999618822f, -0.027608146f, + 0.999698819f, -0.024541229f, + 0.999769405f, -0.021474080f, + 0.999830582f, -0.018406730f, + 0.999882347f, -0.015339206f, + 0.999924702f, -0.012271538f, + 0.999957645f, -0.009203755f, + 0.999981175f, -0.006135885f, + 0.999995294f, -0.003067957f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) +/** + @par + Example code for Floating-point Twiddle factors Generation: + @par + 
for (i = 0; i< N/; i++)
+  {
+ 	twiddleCoef[2*i]   = cos(i * 2*PI/(float)N);
+ 	twiddleCoef[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are in interleaved fashion +*/ +const float32_t twiddleCoef_4096[8192] = { + 1.000000000f, 0.000000000f, + 0.999998823f, 0.001533980f, + 0.999995294f, 0.003067957f, + 0.999989411f, 0.004601926f, + 0.999981175f, 0.006135885f, + 0.999970586f, 0.007669829f, + 0.999957645f, 0.009203755f, + 0.999942350f, 0.010737659f, + 0.999924702f, 0.012271538f, + 0.999904701f, 0.013805389f, + 0.999882347f, 0.015339206f, + 0.999857641f, 0.016872988f, + 0.999830582f, 0.018406730f, + 0.999801170f, 0.019940429f, + 0.999769405f, 0.021474080f, + 0.999735288f, 0.023007681f, + 0.999698819f, 0.024541229f, + 0.999659997f, 0.026074718f, + 0.999618822f, 0.027608146f, + 0.999575296f, 0.029141509f, + 0.999529418f, 0.030674803f, + 0.999481187f, 0.032208025f, + 0.999430605f, 0.033741172f, + 0.999377670f, 0.035274239f, + 0.999322385f, 0.036807223f, + 0.999264747f, 0.038340120f, + 0.999204759f, 0.039872928f, + 0.999142419f, 0.041405641f, + 0.999077728f, 0.042938257f, + 0.999010686f, 0.044470772f, + 0.998941293f, 0.046003182f, + 0.998869550f, 0.047535484f, + 0.998795456f, 0.049067674f, + 0.998719012f, 0.050599749f, + 0.998640218f, 0.052131705f, + 0.998559074f, 0.053663538f, + 0.998475581f, 0.055195244f, + 0.998389737f, 0.056726821f, + 0.998301545f, 0.058258265f, + 0.998211003f, 0.059789571f, + 0.998118113f, 0.061320736f, + 0.998022874f, 0.062851758f, + 0.997925286f, 0.064382631f, + 0.997825350f, 0.065913353f, + 0.997723067f, 0.067443920f, + 0.997618435f, 0.068974328f, + 0.997511456f, 0.070504573f, + 0.997402130f, 0.072034653f, + 0.997290457f, 0.073564564f, + 0.997176437f, 0.075094301f, + 0.997060070f, 0.076623861f, + 0.996941358f, 0.078153242f, + 0.996820299f, 0.079682438f, + 0.996696895f, 0.081211447f, + 0.996571146f, 0.082740265f, + 0.996443051f, 0.084268888f, + 0.996312612f, 0.085797312f, + 0.996179829f, 0.087325535f, + 0.996044701f, 0.088853553f, + 0.995907229f, 0.090381361f, + 0.995767414f, 0.091908956f, + 0.995625256f, 0.093436336f, + 0.995480755f, 0.094963495f, + 0.995333912f, 0.096490431f, + 0.995184727f, 0.098017140f, + 0.995033199f, 0.099543619f, + 0.994879331f, 0.101069863f, + 0.994723121f, 0.102595869f, + 0.994564571f, 0.104121634f, + 0.994403680f, 0.105647154f, + 0.994240449f, 0.107172425f, + 0.994074879f, 0.108697444f, + 0.993906970f, 0.110222207f, + 0.993736722f, 0.111746711f, + 0.993564136f, 0.113270952f, + 0.993389211f, 0.114794927f, + 0.993211949f, 0.116318631f, + 0.993032350f, 0.117842062f, + 0.992850414f, 0.119365215f, + 0.992666142f, 0.120888087f, + 0.992479535f, 0.122410675f, + 0.992290591f, 0.123932975f, + 0.992099313f, 0.125454983f, + 0.991905700f, 0.126976696f, + 0.991709754f, 0.128498111f, + 0.991511473f, 0.130019223f, + 0.991310860f, 0.131540029f, + 0.991107914f, 0.133060525f, + 0.990902635f, 0.134580709f, + 0.990695025f, 0.136100575f, + 0.990485084f, 0.137620122f, + 0.990272812f, 0.139139344f, + 0.990058210f, 0.140658239f, + 0.989841278f, 0.142176804f, + 0.989622017f, 0.143695033f, + 0.989400428f, 0.145212925f, + 0.989176510f, 0.146730474f, + 0.988950265f, 0.148247679f, + 0.988721692f, 0.149764535f, + 0.988490793f, 0.151281038f, + 0.988257568f, 0.152797185f, + 0.988022017f, 0.154312973f, + 0.987784142f, 0.155828398f, + 0.987543942f, 0.157343456f, + 0.987301418f, 0.158858143f, + 0.987056571f, 0.160372457f, + 0.986809402f, 0.161886394f, + 0.986559910f, 0.163399949f, + 0.986308097f, 0.164913120f, + 0.986053963f, 0.166425904f, + 0.985797509f, 0.167938295f, + 0.985538735f, 0.169450291f, + 0.985277642f, 0.170961889f, + 0.985014231f, 0.172473084f, + 0.984748502f, 0.173983873f, + 0.984480455f, 0.175494253f, + 0.984210092f, 0.177004220f, + 0.983937413f, 0.178513771f, + 0.983662419f, 0.180022901f, + 0.983385110f, 0.181531608f, + 0.983105487f, 0.183039888f, + 0.982823551f, 0.184547737f, + 0.982539302f, 0.186055152f, + 0.982252741f, 0.187562129f, + 0.981963869f, 0.189068664f, + 0.981672686f, 0.190574755f, + 0.981379193f, 0.192080397f, + 0.981083391f, 0.193585587f, + 0.980785280f, 0.195090322f, + 0.980484862f, 0.196594598f, + 0.980182136f, 0.198098411f, + 0.979877104f, 0.199601758f, + 0.979569766f, 0.201104635f, + 0.979260123f, 0.202607039f, + 0.978948175f, 0.204108966f, + 0.978633924f, 0.205610413f, + 0.978317371f, 0.207111376f, + 0.977998515f, 0.208611852f, + 0.977677358f, 0.210111837f, + 0.977353900f, 0.211611327f, + 0.977028143f, 0.213110320f, + 0.976700086f, 0.214608811f, + 0.976369731f, 0.216106797f, + 0.976037079f, 0.217604275f, + 0.975702130f, 0.219101240f, + 0.975364885f, 0.220597690f, + 0.975025345f, 0.222093621f, + 0.974683511f, 0.223589029f, + 0.974339383f, 0.225083911f, + 0.973992962f, 0.226578264f, + 0.973644250f, 0.228072083f, + 0.973293246f, 0.229565366f, + 0.972939952f, 0.231058108f, + 0.972584369f, 0.232550307f, + 0.972226497f, 0.234041959f, + 0.971866337f, 0.235533059f, + 0.971503891f, 0.237023606f, + 0.971139158f, 0.238513595f, + 0.970772141f, 0.240003022f, + 0.970402839f, 0.241491885f, + 0.970031253f, 0.242980180f, + 0.969657385f, 0.244467903f, + 0.969281235f, 0.245955050f, + 0.968902805f, 0.247441619f, + 0.968522094f, 0.248927606f, + 0.968139105f, 0.250413007f, + 0.967753837f, 0.251897818f, + 0.967366292f, 0.253382037f, + 0.966976471f, 0.254865660f, + 0.966584374f, 0.256348682f, + 0.966190003f, 0.257831102f, + 0.965793359f, 0.259312915f, + 0.965394442f, 0.260794118f, + 0.964993253f, 0.262274707f, + 0.964589793f, 0.263754679f, + 0.964184064f, 0.265234030f, + 0.963776066f, 0.266712757f, + 0.963365800f, 0.268190857f, + 0.962953267f, 0.269668326f, + 0.962538468f, 0.271145160f, + 0.962121404f, 0.272621355f, + 0.961702077f, 0.274096910f, + 0.961280486f, 0.275571819f, + 0.960856633f, 0.277046080f, + 0.960430519f, 0.278519689f, + 0.960002146f, 0.279992643f, + 0.959571513f, 0.281464938f, + 0.959138622f, 0.282936570f, + 0.958703475f, 0.284407537f, + 0.958266071f, 0.285877835f, + 0.957826413f, 0.287347460f, + 0.957384501f, 0.288816408f, + 0.956940336f, 0.290284677f, + 0.956493919f, 0.291752263f, + 0.956045251f, 0.293219163f, + 0.955594334f, 0.294685372f, + 0.955141168f, 0.296150888f, + 0.954685755f, 0.297615707f, + 0.954228095f, 0.299079826f, + 0.953768190f, 0.300543241f, + 0.953306040f, 0.302005949f, + 0.952841648f, 0.303467947f, + 0.952375013f, 0.304929230f, + 0.951906137f, 0.306389795f, + 0.951435021f, 0.307849640f, + 0.950961666f, 0.309308760f, + 0.950486074f, 0.310767153f, + 0.950008245f, 0.312224814f, + 0.949528181f, 0.313681740f, + 0.949045882f, 0.315137929f, + 0.948561350f, 0.316593376f, + 0.948074586f, 0.318048077f, + 0.947585591f, 0.319502031f, + 0.947094366f, 0.320955232f, + 0.946600913f, 0.322407679f, + 0.946105232f, 0.323859367f, + 0.945607325f, 0.325310292f, + 0.945107193f, 0.326760452f, + 0.944604837f, 0.328209844f, + 0.944100258f, 0.329658463f, + 0.943593458f, 0.331106306f, + 0.943084437f, 0.332553370f, + 0.942573198f, 0.333999651f, + 0.942059740f, 0.335445147f, + 0.941544065f, 0.336889853f, + 0.941026175f, 0.338333767f, + 0.940506071f, 0.339776884f, + 0.939983753f, 0.341219202f, + 0.939459224f, 0.342660717f, + 0.938932484f, 0.344101426f, + 0.938403534f, 0.345541325f, + 0.937872376f, 0.346980411f, + 0.937339012f, 0.348418680f, + 0.936803442f, 0.349856130f, + 0.936265667f, 0.351292756f, + 0.935725689f, 0.352728556f, + 0.935183510f, 0.354163525f, + 0.934639130f, 0.355597662f, + 0.934092550f, 0.357030961f, + 0.933543773f, 0.358463421f, + 0.932992799f, 0.359895037f, + 0.932439629f, 0.361325806f, + 0.931884266f, 0.362755724f, + 0.931326709f, 0.364184790f, + 0.930766961f, 0.365612998f, + 0.930205023f, 0.367040346f, + 0.929640896f, 0.368466830f, + 0.929074581f, 0.369892447f, + 0.928506080f, 0.371317194f, + 0.927935395f, 0.372741067f, + 0.927362526f, 0.374164063f, + 0.926787474f, 0.375586178f, + 0.926210242f, 0.377007410f, + 0.925630831f, 0.378427755f, + 0.925049241f, 0.379847209f, + 0.924465474f, 0.381265769f, + 0.923879533f, 0.382683432f, + 0.923291417f, 0.384100195f, + 0.922701128f, 0.385516054f, + 0.922108669f, 0.386931006f, + 0.921514039f, 0.388345047f, + 0.920917242f, 0.389758174f, + 0.920318277f, 0.391170384f, + 0.919717146f, 0.392581674f, + 0.919113852f, 0.393992040f, + 0.918508394f, 0.395401479f, + 0.917900776f, 0.396809987f, + 0.917290997f, 0.398217562f, + 0.916679060f, 0.399624200f, + 0.916064966f, 0.401029897f, + 0.915448716f, 0.402434651f, + 0.914830312f, 0.403838458f, + 0.914209756f, 0.405241314f, + 0.913587048f, 0.406643217f, + 0.912962190f, 0.408044163f, + 0.912335185f, 0.409444149f, + 0.911706032f, 0.410843171f, + 0.911074734f, 0.412241227f, + 0.910441292f, 0.413638312f, + 0.909805708f, 0.415034424f, + 0.909167983f, 0.416429560f, + 0.908528119f, 0.417823716f, + 0.907886116f, 0.419216888f, + 0.907241978f, 0.420609074f, + 0.906595705f, 0.422000271f, + 0.905947298f, 0.423390474f, + 0.905296759f, 0.424779681f, + 0.904644091f, 0.426167889f, + 0.903989293f, 0.427555093f, + 0.903332368f, 0.428941292f, + 0.902673318f, 0.430326481f, + 0.902012144f, 0.431710658f, + 0.901348847f, 0.433093819f, + 0.900683429f, 0.434475961f, + 0.900015892f, 0.435857080f, + 0.899346237f, 0.437237174f, + 0.898674466f, 0.438616239f, + 0.898000580f, 0.439994271f, + 0.897324581f, 0.441371269f, + 0.896646470f, 0.442747228f, + 0.895966250f, 0.444122145f, + 0.895283921f, 0.445496017f, + 0.894599486f, 0.446868840f, + 0.893912945f, 0.448240612f, + 0.893224301f, 0.449611330f, + 0.892533555f, 0.450980989f, + 0.891840709f, 0.452349587f, + 0.891145765f, 0.453717121f, + 0.890448723f, 0.455083587f, + 0.889749586f, 0.456448982f, + 0.889048356f, 0.457813304f, + 0.888345033f, 0.459176548f, + 0.887639620f, 0.460538711f, + 0.886932119f, 0.461899791f, + 0.886222530f, 0.463259784f, + 0.885510856f, 0.464618686f, + 0.884797098f, 0.465976496f, + 0.884081259f, 0.467333209f, + 0.883363339f, 0.468688822f, + 0.882643340f, 0.470043332f, + 0.881921264f, 0.471396737f, + 0.881197113f, 0.472749032f, + 0.880470889f, 0.474100215f, + 0.879742593f, 0.475450282f, + 0.879012226f, 0.476799230f, + 0.878279792f, 0.478147056f, + 0.877545290f, 0.479493758f, + 0.876808724f, 0.480839331f, + 0.876070094f, 0.482183772f, + 0.875329403f, 0.483527079f, + 0.874586652f, 0.484869248f, + 0.873841843f, 0.486210276f, + 0.873094978f, 0.487550160f, + 0.872346059f, 0.488888897f, + 0.871595087f, 0.490226483f, + 0.870842063f, 0.491562916f, + 0.870086991f, 0.492898192f, + 0.869329871f, 0.494232309f, + 0.868570706f, 0.495565262f, + 0.867809497f, 0.496897049f, + 0.867046246f, 0.498227667f, + 0.866280954f, 0.499557113f, + 0.865513624f, 0.500885383f, + 0.864744258f, 0.502212474f, + 0.863972856f, 0.503538384f, + 0.863199422f, 0.504863109f, + 0.862423956f, 0.506186645f, + 0.861646461f, 0.507508991f, + 0.860866939f, 0.508830143f, + 0.860085390f, 0.510150097f, + 0.859301818f, 0.511468850f, + 0.858516224f, 0.512786401f, + 0.857728610f, 0.514102744f, + 0.856938977f, 0.515417878f, + 0.856147328f, 0.516731799f, + 0.855353665f, 0.518044504f, + 0.854557988f, 0.519355990f, + 0.853760301f, 0.520666254f, + 0.852960605f, 0.521975293f, + 0.852158902f, 0.523283103f, + 0.851355193f, 0.524589683f, + 0.850549481f, 0.525895027f, + 0.849741768f, 0.527199135f, + 0.848932055f, 0.528502002f, + 0.848120345f, 0.529803625f, + 0.847306639f, 0.531104001f, + 0.846490939f, 0.532403128f, + 0.845673247f, 0.533701002f, + 0.844853565f, 0.534997620f, + 0.844031895f, 0.536292979f, + 0.843208240f, 0.537587076f, + 0.842382600f, 0.538879909f, + 0.841554977f, 0.540171473f, + 0.840725375f, 0.541461766f, + 0.839893794f, 0.542750785f, + 0.839060237f, 0.544038527f, + 0.838224706f, 0.545324988f, + 0.837387202f, 0.546610167f, + 0.836547727f, 0.547894059f, + 0.835706284f, 0.549176662f, + 0.834862875f, 0.550457973f, + 0.834017501f, 0.551737988f, + 0.833170165f, 0.553016706f, + 0.832320868f, 0.554294121f, + 0.831469612f, 0.555570233f, + 0.830616400f, 0.556845037f, + 0.829761234f, 0.558118531f, + 0.828904115f, 0.559390712f, + 0.828045045f, 0.560661576f, + 0.827184027f, 0.561931121f, + 0.826321063f, 0.563199344f, + 0.825456154f, 0.564466242f, + 0.824589303f, 0.565731811f, + 0.823720511f, 0.566996049f, + 0.822849781f, 0.568258953f, + 0.821977115f, 0.569520519f, + 0.821102515f, 0.570780746f, + 0.820225983f, 0.572039629f, + 0.819347520f, 0.573297167f, + 0.818467130f, 0.574553355f, + 0.817584813f, 0.575808191f, + 0.816700573f, 0.577061673f, + 0.815814411f, 0.578313796f, + 0.814926329f, 0.579564559f, + 0.814036330f, 0.580813958f, + 0.813144415f, 0.582061990f, + 0.812250587f, 0.583308653f, + 0.811354847f, 0.584553943f, + 0.810457198f, 0.585797857f, + 0.809557642f, 0.587040394f, + 0.808656182f, 0.588281548f, + 0.807752818f, 0.589521319f, + 0.806847554f, 0.590759702f, + 0.805940391f, 0.591996695f, + 0.805031331f, 0.593232295f, + 0.804120377f, 0.594466499f, + 0.803207531f, 0.595699304f, + 0.802292796f, 0.596930708f, + 0.801376172f, 0.598160707f, + 0.800457662f, 0.599389298f, + 0.799537269f, 0.600616479f, + 0.798614995f, 0.601842247f, + 0.797690841f, 0.603066599f, + 0.796764810f, 0.604289531f, + 0.795836905f, 0.605511041f, + 0.794907126f, 0.606731127f, + 0.793975478f, 0.607949785f, + 0.793041960f, 0.609167012f, + 0.792106577f, 0.610382806f, + 0.791169330f, 0.611597164f, + 0.790230221f, 0.612810082f, + 0.789289253f, 0.614021559f, + 0.788346428f, 0.615231591f, + 0.787401747f, 0.616440175f, + 0.786455214f, 0.617647308f, + 0.785506830f, 0.618852988f, + 0.784556597f, 0.620057212f, + 0.783604519f, 0.621259977f, + 0.782650596f, 0.622461279f, + 0.781694832f, 0.623661118f, + 0.780737229f, 0.624859488f, + 0.779777788f, 0.626056388f, + 0.778816512f, 0.627251815f, + 0.777853404f, 0.628445767f, + 0.776888466f, 0.629638239f, + 0.775921699f, 0.630829230f, + 0.774953107f, 0.632018736f, + 0.773982691f, 0.633206755f, + 0.773010453f, 0.634393284f, + 0.772036397f, 0.635578320f, + 0.771060524f, 0.636761861f, + 0.770082837f, 0.637943904f, + 0.769103338f, 0.639124445f, + 0.768122029f, 0.640303482f, + 0.767138912f, 0.641481013f, + 0.766153990f, 0.642657034f, + 0.765167266f, 0.643831543f, + 0.764178741f, 0.645004537f, + 0.763188417f, 0.646176013f, + 0.762196298f, 0.647345969f, + 0.761202385f, 0.648514401f, + 0.760206682f, 0.649681307f, + 0.759209189f, 0.650846685f, + 0.758209910f, 0.652010531f, + 0.757208847f, 0.653172843f, + 0.756206001f, 0.654333618f, + 0.755201377f, 0.655492853f, + 0.754194975f, 0.656650546f, + 0.753186799f, 0.657806693f, + 0.752176850f, 0.658961293f, + 0.751165132f, 0.660114342f, + 0.750151646f, 0.661265838f, + 0.749136395f, 0.662415778f, + 0.748119380f, 0.663564159f, + 0.747100606f, 0.664710978f, + 0.746080074f, 0.665856234f, + 0.745057785f, 0.666999922f, + 0.744033744f, 0.668142041f, + 0.743007952f, 0.669282588f, + 0.741980412f, 0.670421560f, + 0.740951125f, 0.671558955f, + 0.739920095f, 0.672694769f, + 0.738887324f, 0.673829000f, + 0.737852815f, 0.674961646f, + 0.736816569f, 0.676092704f, + 0.735778589f, 0.677222170f, + 0.734738878f, 0.678350043f, + 0.733697438f, 0.679476320f, + 0.732654272f, 0.680600998f, + 0.731609381f, 0.681724074f, + 0.730562769f, 0.682845546f, + 0.729514438f, 0.683965412f, + 0.728464390f, 0.685083668f, + 0.727412629f, 0.686200312f, + 0.726359155f, 0.687315341f, + 0.725303972f, 0.688428753f, + 0.724247083f, 0.689540545f, + 0.723188489f, 0.690650714f, + 0.722128194f, 0.691759258f, + 0.721066199f, 0.692866175f, + 0.720002508f, 0.693971461f, + 0.718937122f, 0.695075114f, + 0.717870045f, 0.696177131f, + 0.716801279f, 0.697277511f, + 0.715730825f, 0.698376249f, + 0.714658688f, 0.699473345f, + 0.713584869f, 0.700568794f, + 0.712509371f, 0.701662595f, + 0.711432196f, 0.702754744f, + 0.710353347f, 0.703845241f, + 0.709272826f, 0.704934080f, + 0.708190637f, 0.706021261f, + 0.707106781f, 0.707106781f, + 0.706021261f, 0.708190637f, + 0.704934080f, 0.709272826f, + 0.703845241f, 0.710353347f, + 0.702754744f, 0.711432196f, + 0.701662595f, 0.712509371f, + 0.700568794f, 0.713584869f, + 0.699473345f, 0.714658688f, + 0.698376249f, 0.715730825f, + 0.697277511f, 0.716801279f, + 0.696177131f, 0.717870045f, + 0.695075114f, 0.718937122f, + 0.693971461f, 0.720002508f, + 0.692866175f, 0.721066199f, + 0.691759258f, 0.722128194f, + 0.690650714f, 0.723188489f, + 0.689540545f, 0.724247083f, + 0.688428753f, 0.725303972f, + 0.687315341f, 0.726359155f, + 0.686200312f, 0.727412629f, + 0.685083668f, 0.728464390f, + 0.683965412f, 0.729514438f, + 0.682845546f, 0.730562769f, + 0.681724074f, 0.731609381f, + 0.680600998f, 0.732654272f, + 0.679476320f, 0.733697438f, + 0.678350043f, 0.734738878f, + 0.677222170f, 0.735778589f, + 0.676092704f, 0.736816569f, + 0.674961646f, 0.737852815f, + 0.673829000f, 0.738887324f, + 0.672694769f, 0.739920095f, + 0.671558955f, 0.740951125f, + 0.670421560f, 0.741980412f, + 0.669282588f, 0.743007952f, + 0.668142041f, 0.744033744f, + 0.666999922f, 0.745057785f, + 0.665856234f, 0.746080074f, + 0.664710978f, 0.747100606f, + 0.663564159f, 0.748119380f, + 0.662415778f, 0.749136395f, + 0.661265838f, 0.750151646f, + 0.660114342f, 0.751165132f, + 0.658961293f, 0.752176850f, + 0.657806693f, 0.753186799f, + 0.656650546f, 0.754194975f, + 0.655492853f, 0.755201377f, + 0.654333618f, 0.756206001f, + 0.653172843f, 0.757208847f, + 0.652010531f, 0.758209910f, + 0.650846685f, 0.759209189f, + 0.649681307f, 0.760206682f, + 0.648514401f, 0.761202385f, + 0.647345969f, 0.762196298f, + 0.646176013f, 0.763188417f, + 0.645004537f, 0.764178741f, + 0.643831543f, 0.765167266f, + 0.642657034f, 0.766153990f, + 0.641481013f, 0.767138912f, + 0.640303482f, 0.768122029f, + 0.639124445f, 0.769103338f, + 0.637943904f, 0.770082837f, + 0.636761861f, 0.771060524f, + 0.635578320f, 0.772036397f, + 0.634393284f, 0.773010453f, + 0.633206755f, 0.773982691f, + 0.632018736f, 0.774953107f, + 0.630829230f, 0.775921699f, + 0.629638239f, 0.776888466f, + 0.628445767f, 0.777853404f, + 0.627251815f, 0.778816512f, + 0.626056388f, 0.779777788f, + 0.624859488f, 0.780737229f, + 0.623661118f, 0.781694832f, + 0.622461279f, 0.782650596f, + 0.621259977f, 0.783604519f, + 0.620057212f, 0.784556597f, + 0.618852988f, 0.785506830f, + 0.617647308f, 0.786455214f, + 0.616440175f, 0.787401747f, + 0.615231591f, 0.788346428f, + 0.614021559f, 0.789289253f, + 0.612810082f, 0.790230221f, + 0.611597164f, 0.791169330f, + 0.610382806f, 0.792106577f, + 0.609167012f, 0.793041960f, + 0.607949785f, 0.793975478f, + 0.606731127f, 0.794907126f, + 0.605511041f, 0.795836905f, + 0.604289531f, 0.796764810f, + 0.603066599f, 0.797690841f, + 0.601842247f, 0.798614995f, + 0.600616479f, 0.799537269f, + 0.599389298f, 0.800457662f, + 0.598160707f, 0.801376172f, + 0.596930708f, 0.802292796f, + 0.595699304f, 0.803207531f, + 0.594466499f, 0.804120377f, + 0.593232295f, 0.805031331f, + 0.591996695f, 0.805940391f, + 0.590759702f, 0.806847554f, + 0.589521319f, 0.807752818f, + 0.588281548f, 0.808656182f, + 0.587040394f, 0.809557642f, + 0.585797857f, 0.810457198f, + 0.584553943f, 0.811354847f, + 0.583308653f, 0.812250587f, + 0.582061990f, 0.813144415f, + 0.580813958f, 0.814036330f, + 0.579564559f, 0.814926329f, + 0.578313796f, 0.815814411f, + 0.577061673f, 0.816700573f, + 0.575808191f, 0.817584813f, + 0.574553355f, 0.818467130f, + 0.573297167f, 0.819347520f, + 0.572039629f, 0.820225983f, + 0.570780746f, 0.821102515f, + 0.569520519f, 0.821977115f, + 0.568258953f, 0.822849781f, + 0.566996049f, 0.823720511f, + 0.565731811f, 0.824589303f, + 0.564466242f, 0.825456154f, + 0.563199344f, 0.826321063f, + 0.561931121f, 0.827184027f, + 0.560661576f, 0.828045045f, + 0.559390712f, 0.828904115f, + 0.558118531f, 0.829761234f, + 0.556845037f, 0.830616400f, + 0.555570233f, 0.831469612f, + 0.554294121f, 0.832320868f, + 0.553016706f, 0.833170165f, + 0.551737988f, 0.834017501f, + 0.550457973f, 0.834862875f, + 0.549176662f, 0.835706284f, + 0.547894059f, 0.836547727f, + 0.546610167f, 0.837387202f, + 0.545324988f, 0.838224706f, + 0.544038527f, 0.839060237f, + 0.542750785f, 0.839893794f, + 0.541461766f, 0.840725375f, + 0.540171473f, 0.841554977f, + 0.538879909f, 0.842382600f, + 0.537587076f, 0.843208240f, + 0.536292979f, 0.844031895f, + 0.534997620f, 0.844853565f, + 0.533701002f, 0.845673247f, + 0.532403128f, 0.846490939f, + 0.531104001f, 0.847306639f, + 0.529803625f, 0.848120345f, + 0.528502002f, 0.848932055f, + 0.527199135f, 0.849741768f, + 0.525895027f, 0.850549481f, + 0.524589683f, 0.851355193f, + 0.523283103f, 0.852158902f, + 0.521975293f, 0.852960605f, + 0.520666254f, 0.853760301f, + 0.519355990f, 0.854557988f, + 0.518044504f, 0.855353665f, + 0.516731799f, 0.856147328f, + 0.515417878f, 0.856938977f, + 0.514102744f, 0.857728610f, + 0.512786401f, 0.858516224f, + 0.511468850f, 0.859301818f, + 0.510150097f, 0.860085390f, + 0.508830143f, 0.860866939f, + 0.507508991f, 0.861646461f, + 0.506186645f, 0.862423956f, + 0.504863109f, 0.863199422f, + 0.503538384f, 0.863972856f, + 0.502212474f, 0.864744258f, + 0.500885383f, 0.865513624f, + 0.499557113f, 0.866280954f, + 0.498227667f, 0.867046246f, + 0.496897049f, 0.867809497f, + 0.495565262f, 0.868570706f, + 0.494232309f, 0.869329871f, + 0.492898192f, 0.870086991f, + 0.491562916f, 0.870842063f, + 0.490226483f, 0.871595087f, + 0.488888897f, 0.872346059f, + 0.487550160f, 0.873094978f, + 0.486210276f, 0.873841843f, + 0.484869248f, 0.874586652f, + 0.483527079f, 0.875329403f, + 0.482183772f, 0.876070094f, + 0.480839331f, 0.876808724f, + 0.479493758f, 0.877545290f, + 0.478147056f, 0.878279792f, + 0.476799230f, 0.879012226f, + 0.475450282f, 0.879742593f, + 0.474100215f, 0.880470889f, + 0.472749032f, 0.881197113f, + 0.471396737f, 0.881921264f, + 0.470043332f, 0.882643340f, + 0.468688822f, 0.883363339f, + 0.467333209f, 0.884081259f, + 0.465976496f, 0.884797098f, + 0.464618686f, 0.885510856f, + 0.463259784f, 0.886222530f, + 0.461899791f, 0.886932119f, + 0.460538711f, 0.887639620f, + 0.459176548f, 0.888345033f, + 0.457813304f, 0.889048356f, + 0.456448982f, 0.889749586f, + 0.455083587f, 0.890448723f, + 0.453717121f, 0.891145765f, + 0.452349587f, 0.891840709f, + 0.450980989f, 0.892533555f, + 0.449611330f, 0.893224301f, + 0.448240612f, 0.893912945f, + 0.446868840f, 0.894599486f, + 0.445496017f, 0.895283921f, + 0.444122145f, 0.895966250f, + 0.442747228f, 0.896646470f, + 0.441371269f, 0.897324581f, + 0.439994271f, 0.898000580f, + 0.438616239f, 0.898674466f, + 0.437237174f, 0.899346237f, + 0.435857080f, 0.900015892f, + 0.434475961f, 0.900683429f, + 0.433093819f, 0.901348847f, + 0.431710658f, 0.902012144f, + 0.430326481f, 0.902673318f, + 0.428941292f, 0.903332368f, + 0.427555093f, 0.903989293f, + 0.426167889f, 0.904644091f, + 0.424779681f, 0.905296759f, + 0.423390474f, 0.905947298f, + 0.422000271f, 0.906595705f, + 0.420609074f, 0.907241978f, + 0.419216888f, 0.907886116f, + 0.417823716f, 0.908528119f, + 0.416429560f, 0.909167983f, + 0.415034424f, 0.909805708f, + 0.413638312f, 0.910441292f, + 0.412241227f, 0.911074734f, + 0.410843171f, 0.911706032f, + 0.409444149f, 0.912335185f, + 0.408044163f, 0.912962190f, + 0.406643217f, 0.913587048f, + 0.405241314f, 0.914209756f, + 0.403838458f, 0.914830312f, + 0.402434651f, 0.915448716f, + 0.401029897f, 0.916064966f, + 0.399624200f, 0.916679060f, + 0.398217562f, 0.917290997f, + 0.396809987f, 0.917900776f, + 0.395401479f, 0.918508394f, + 0.393992040f, 0.919113852f, + 0.392581674f, 0.919717146f, + 0.391170384f, 0.920318277f, + 0.389758174f, 0.920917242f, + 0.388345047f, 0.921514039f, + 0.386931006f, 0.922108669f, + 0.385516054f, 0.922701128f, + 0.384100195f, 0.923291417f, + 0.382683432f, 0.923879533f, + 0.381265769f, 0.924465474f, + 0.379847209f, 0.925049241f, + 0.378427755f, 0.925630831f, + 0.377007410f, 0.926210242f, + 0.375586178f, 0.926787474f, + 0.374164063f, 0.927362526f, + 0.372741067f, 0.927935395f, + 0.371317194f, 0.928506080f, + 0.369892447f, 0.929074581f, + 0.368466830f, 0.929640896f, + 0.367040346f, 0.930205023f, + 0.365612998f, 0.930766961f, + 0.364184790f, 0.931326709f, + 0.362755724f, 0.931884266f, + 0.361325806f, 0.932439629f, + 0.359895037f, 0.932992799f, + 0.358463421f, 0.933543773f, + 0.357030961f, 0.934092550f, + 0.355597662f, 0.934639130f, + 0.354163525f, 0.935183510f, + 0.352728556f, 0.935725689f, + 0.351292756f, 0.936265667f, + 0.349856130f, 0.936803442f, + 0.348418680f, 0.937339012f, + 0.346980411f, 0.937872376f, + 0.345541325f, 0.938403534f, + 0.344101426f, 0.938932484f, + 0.342660717f, 0.939459224f, + 0.341219202f, 0.939983753f, + 0.339776884f, 0.940506071f, + 0.338333767f, 0.941026175f, + 0.336889853f, 0.941544065f, + 0.335445147f, 0.942059740f, + 0.333999651f, 0.942573198f, + 0.332553370f, 0.943084437f, + 0.331106306f, 0.943593458f, + 0.329658463f, 0.944100258f, + 0.328209844f, 0.944604837f, + 0.326760452f, 0.945107193f, + 0.325310292f, 0.945607325f, + 0.323859367f, 0.946105232f, + 0.322407679f, 0.946600913f, + 0.320955232f, 0.947094366f, + 0.319502031f, 0.947585591f, + 0.318048077f, 0.948074586f, + 0.316593376f, 0.948561350f, + 0.315137929f, 0.949045882f, + 0.313681740f, 0.949528181f, + 0.312224814f, 0.950008245f, + 0.310767153f, 0.950486074f, + 0.309308760f, 0.950961666f, + 0.307849640f, 0.951435021f, + 0.306389795f, 0.951906137f, + 0.304929230f, 0.952375013f, + 0.303467947f, 0.952841648f, + 0.302005949f, 0.953306040f, + 0.300543241f, 0.953768190f, + 0.299079826f, 0.954228095f, + 0.297615707f, 0.954685755f, + 0.296150888f, 0.955141168f, + 0.294685372f, 0.955594334f, + 0.293219163f, 0.956045251f, + 0.291752263f, 0.956493919f, + 0.290284677f, 0.956940336f, + 0.288816408f, 0.957384501f, + 0.287347460f, 0.957826413f, + 0.285877835f, 0.958266071f, + 0.284407537f, 0.958703475f, + 0.282936570f, 0.959138622f, + 0.281464938f, 0.959571513f, + 0.279992643f, 0.960002146f, + 0.278519689f, 0.960430519f, + 0.277046080f, 0.960856633f, + 0.275571819f, 0.961280486f, + 0.274096910f, 0.961702077f, + 0.272621355f, 0.962121404f, + 0.271145160f, 0.962538468f, + 0.269668326f, 0.962953267f, + 0.268190857f, 0.963365800f, + 0.266712757f, 0.963776066f, + 0.265234030f, 0.964184064f, + 0.263754679f, 0.964589793f, + 0.262274707f, 0.964993253f, + 0.260794118f, 0.965394442f, + 0.259312915f, 0.965793359f, + 0.257831102f, 0.966190003f, + 0.256348682f, 0.966584374f, + 0.254865660f, 0.966976471f, + 0.253382037f, 0.967366292f, + 0.251897818f, 0.967753837f, + 0.250413007f, 0.968139105f, + 0.248927606f, 0.968522094f, + 0.247441619f, 0.968902805f, + 0.245955050f, 0.969281235f, + 0.244467903f, 0.969657385f, + 0.242980180f, 0.970031253f, + 0.241491885f, 0.970402839f, + 0.240003022f, 0.970772141f, + 0.238513595f, 0.971139158f, + 0.237023606f, 0.971503891f, + 0.235533059f, 0.971866337f, + 0.234041959f, 0.972226497f, + 0.232550307f, 0.972584369f, + 0.231058108f, 0.972939952f, + 0.229565366f, 0.973293246f, + 0.228072083f, 0.973644250f, + 0.226578264f, 0.973992962f, + 0.225083911f, 0.974339383f, + 0.223589029f, 0.974683511f, + 0.222093621f, 0.975025345f, + 0.220597690f, 0.975364885f, + 0.219101240f, 0.975702130f, + 0.217604275f, 0.976037079f, + 0.216106797f, 0.976369731f, + 0.214608811f, 0.976700086f, + 0.213110320f, 0.977028143f, + 0.211611327f, 0.977353900f, + 0.210111837f, 0.977677358f, + 0.208611852f, 0.977998515f, + 0.207111376f, 0.978317371f, + 0.205610413f, 0.978633924f, + 0.204108966f, 0.978948175f, + 0.202607039f, 0.979260123f, + 0.201104635f, 0.979569766f, + 0.199601758f, 0.979877104f, + 0.198098411f, 0.980182136f, + 0.196594598f, 0.980484862f, + 0.195090322f, 0.980785280f, + 0.193585587f, 0.981083391f, + 0.192080397f, 0.981379193f, + 0.190574755f, 0.981672686f, + 0.189068664f, 0.981963869f, + 0.187562129f, 0.982252741f, + 0.186055152f, 0.982539302f, + 0.184547737f, 0.982823551f, + 0.183039888f, 0.983105487f, + 0.181531608f, 0.983385110f, + 0.180022901f, 0.983662419f, + 0.178513771f, 0.983937413f, + 0.177004220f, 0.984210092f, + 0.175494253f, 0.984480455f, + 0.173983873f, 0.984748502f, + 0.172473084f, 0.985014231f, + 0.170961889f, 0.985277642f, + 0.169450291f, 0.985538735f, + 0.167938295f, 0.985797509f, + 0.166425904f, 0.986053963f, + 0.164913120f, 0.986308097f, + 0.163399949f, 0.986559910f, + 0.161886394f, 0.986809402f, + 0.160372457f, 0.987056571f, + 0.158858143f, 0.987301418f, + 0.157343456f, 0.987543942f, + 0.155828398f, 0.987784142f, + 0.154312973f, 0.988022017f, + 0.152797185f, 0.988257568f, + 0.151281038f, 0.988490793f, + 0.149764535f, 0.988721692f, + 0.148247679f, 0.988950265f, + 0.146730474f, 0.989176510f, + 0.145212925f, 0.989400428f, + 0.143695033f, 0.989622017f, + 0.142176804f, 0.989841278f, + 0.140658239f, 0.990058210f, + 0.139139344f, 0.990272812f, + 0.137620122f, 0.990485084f, + 0.136100575f, 0.990695025f, + 0.134580709f, 0.990902635f, + 0.133060525f, 0.991107914f, + 0.131540029f, 0.991310860f, + 0.130019223f, 0.991511473f, + 0.128498111f, 0.991709754f, + 0.126976696f, 0.991905700f, + 0.125454983f, 0.992099313f, + 0.123932975f, 0.992290591f, + 0.122410675f, 0.992479535f, + 0.120888087f, 0.992666142f, + 0.119365215f, 0.992850414f, + 0.117842062f, 0.993032350f, + 0.116318631f, 0.993211949f, + 0.114794927f, 0.993389211f, + 0.113270952f, 0.993564136f, + 0.111746711f, 0.993736722f, + 0.110222207f, 0.993906970f, + 0.108697444f, 0.994074879f, + 0.107172425f, 0.994240449f, + 0.105647154f, 0.994403680f, + 0.104121634f, 0.994564571f, + 0.102595869f, 0.994723121f, + 0.101069863f, 0.994879331f, + 0.099543619f, 0.995033199f, + 0.098017140f, 0.995184727f, + 0.096490431f, 0.995333912f, + 0.094963495f, 0.995480755f, + 0.093436336f, 0.995625256f, + 0.091908956f, 0.995767414f, + 0.090381361f, 0.995907229f, + 0.088853553f, 0.996044701f, + 0.087325535f, 0.996179829f, + 0.085797312f, 0.996312612f, + 0.084268888f, 0.996443051f, + 0.082740265f, 0.996571146f, + 0.081211447f, 0.996696895f, + 0.079682438f, 0.996820299f, + 0.078153242f, 0.996941358f, + 0.076623861f, 0.997060070f, + 0.075094301f, 0.997176437f, + 0.073564564f, 0.997290457f, + 0.072034653f, 0.997402130f, + 0.070504573f, 0.997511456f, + 0.068974328f, 0.997618435f, + 0.067443920f, 0.997723067f, + 0.065913353f, 0.997825350f, + 0.064382631f, 0.997925286f, + 0.062851758f, 0.998022874f, + 0.061320736f, 0.998118113f, + 0.059789571f, 0.998211003f, + 0.058258265f, 0.998301545f, + 0.056726821f, 0.998389737f, + 0.055195244f, 0.998475581f, + 0.053663538f, 0.998559074f, + 0.052131705f, 0.998640218f, + 0.050599749f, 0.998719012f, + 0.049067674f, 0.998795456f, + 0.047535484f, 0.998869550f, + 0.046003182f, 0.998941293f, + 0.044470772f, 0.999010686f, + 0.042938257f, 0.999077728f, + 0.041405641f, 0.999142419f, + 0.039872928f, 0.999204759f, + 0.038340120f, 0.999264747f, + 0.036807223f, 0.999322385f, + 0.035274239f, 0.999377670f, + 0.033741172f, 0.999430605f, + 0.032208025f, 0.999481187f, + 0.030674803f, 0.999529418f, + 0.029141509f, 0.999575296f, + 0.027608146f, 0.999618822f, + 0.026074718f, 0.999659997f, + 0.024541229f, 0.999698819f, + 0.023007681f, 0.999735288f, + 0.021474080f, 0.999769405f, + 0.019940429f, 0.999801170f, + 0.018406730f, 0.999830582f, + 0.016872988f, 0.999857641f, + 0.015339206f, 0.999882347f, + 0.013805389f, 0.999904701f, + 0.012271538f, 0.999924702f, + 0.010737659f, 0.999942350f, + 0.009203755f, 0.999957645f, + 0.007669829f, 0.999970586f, + 0.006135885f, 0.999981175f, + 0.004601926f, 0.999989411f, + 0.003067957f, 0.999995294f, + 0.001533980f, 0.999998823f, + 0.000000000f, 1.000000000f, + -0.001533980f, 0.999998823f, + -0.003067957f, 0.999995294f, + -0.004601926f, 0.999989411f, + -0.006135885f, 0.999981175f, + -0.007669829f, 0.999970586f, + -0.009203755f, 0.999957645f, + -0.010737659f, 0.999942350f, + -0.012271538f, 0.999924702f, + -0.013805389f, 0.999904701f, + -0.015339206f, 0.999882347f, + -0.016872988f, 0.999857641f, + -0.018406730f, 0.999830582f, + -0.019940429f, 0.999801170f, + -0.021474080f, 0.999769405f, + -0.023007681f, 0.999735288f, + -0.024541229f, 0.999698819f, + -0.026074718f, 0.999659997f, + -0.027608146f, 0.999618822f, + -0.029141509f, 0.999575296f, + -0.030674803f, 0.999529418f, + -0.032208025f, 0.999481187f, + -0.033741172f, 0.999430605f, + -0.035274239f, 0.999377670f, + -0.036807223f, 0.999322385f, + -0.038340120f, 0.999264747f, + -0.039872928f, 0.999204759f, + -0.041405641f, 0.999142419f, + -0.042938257f, 0.999077728f, + -0.044470772f, 0.999010686f, + -0.046003182f, 0.998941293f, + -0.047535484f, 0.998869550f, + -0.049067674f, 0.998795456f, + -0.050599749f, 0.998719012f, + -0.052131705f, 0.998640218f, + -0.053663538f, 0.998559074f, + -0.055195244f, 0.998475581f, + -0.056726821f, 0.998389737f, + -0.058258265f, 0.998301545f, + -0.059789571f, 0.998211003f, + -0.061320736f, 0.998118113f, + -0.062851758f, 0.998022874f, + -0.064382631f, 0.997925286f, + -0.065913353f, 0.997825350f, + -0.067443920f, 0.997723067f, + -0.068974328f, 0.997618435f, + -0.070504573f, 0.997511456f, + -0.072034653f, 0.997402130f, + -0.073564564f, 0.997290457f, + -0.075094301f, 0.997176437f, + -0.076623861f, 0.997060070f, + -0.078153242f, 0.996941358f, + -0.079682438f, 0.996820299f, + -0.081211447f, 0.996696895f, + -0.082740265f, 0.996571146f, + -0.084268888f, 0.996443051f, + -0.085797312f, 0.996312612f, + -0.087325535f, 0.996179829f, + -0.088853553f, 0.996044701f, + -0.090381361f, 0.995907229f, + -0.091908956f, 0.995767414f, + -0.093436336f, 0.995625256f, + -0.094963495f, 0.995480755f, + -0.096490431f, 0.995333912f, + -0.098017140f, 0.995184727f, + -0.099543619f, 0.995033199f, + -0.101069863f, 0.994879331f, + -0.102595869f, 0.994723121f, + -0.104121634f, 0.994564571f, + -0.105647154f, 0.994403680f, + -0.107172425f, 0.994240449f, + -0.108697444f, 0.994074879f, + -0.110222207f, 0.993906970f, + -0.111746711f, 0.993736722f, + -0.113270952f, 0.993564136f, + -0.114794927f, 0.993389211f, + -0.116318631f, 0.993211949f, + -0.117842062f, 0.993032350f, + -0.119365215f, 0.992850414f, + -0.120888087f, 0.992666142f, + -0.122410675f, 0.992479535f, + -0.123932975f, 0.992290591f, + -0.125454983f, 0.992099313f, + -0.126976696f, 0.991905700f, + -0.128498111f, 0.991709754f, + -0.130019223f, 0.991511473f, + -0.131540029f, 0.991310860f, + -0.133060525f, 0.991107914f, + -0.134580709f, 0.990902635f, + -0.136100575f, 0.990695025f, + -0.137620122f, 0.990485084f, + -0.139139344f, 0.990272812f, + -0.140658239f, 0.990058210f, + -0.142176804f, 0.989841278f, + -0.143695033f, 0.989622017f, + -0.145212925f, 0.989400428f, + -0.146730474f, 0.989176510f, + -0.148247679f, 0.988950265f, + -0.149764535f, 0.988721692f, + -0.151281038f, 0.988490793f, + -0.152797185f, 0.988257568f, + -0.154312973f, 0.988022017f, + -0.155828398f, 0.987784142f, + -0.157343456f, 0.987543942f, + -0.158858143f, 0.987301418f, + -0.160372457f, 0.987056571f, + -0.161886394f, 0.986809402f, + -0.163399949f, 0.986559910f, + -0.164913120f, 0.986308097f, + -0.166425904f, 0.986053963f, + -0.167938295f, 0.985797509f, + -0.169450291f, 0.985538735f, + -0.170961889f, 0.985277642f, + -0.172473084f, 0.985014231f, + -0.173983873f, 0.984748502f, + -0.175494253f, 0.984480455f, + -0.177004220f, 0.984210092f, + -0.178513771f, 0.983937413f, + -0.180022901f, 0.983662419f, + -0.181531608f, 0.983385110f, + -0.183039888f, 0.983105487f, + -0.184547737f, 0.982823551f, + -0.186055152f, 0.982539302f, + -0.187562129f, 0.982252741f, + -0.189068664f, 0.981963869f, + -0.190574755f, 0.981672686f, + -0.192080397f, 0.981379193f, + -0.193585587f, 0.981083391f, + -0.195090322f, 0.980785280f, + -0.196594598f, 0.980484862f, + -0.198098411f, 0.980182136f, + -0.199601758f, 0.979877104f, + -0.201104635f, 0.979569766f, + -0.202607039f, 0.979260123f, + -0.204108966f, 0.978948175f, + -0.205610413f, 0.978633924f, + -0.207111376f, 0.978317371f, + -0.208611852f, 0.977998515f, + -0.210111837f, 0.977677358f, + -0.211611327f, 0.977353900f, + -0.213110320f, 0.977028143f, + -0.214608811f, 0.976700086f, + -0.216106797f, 0.976369731f, + -0.217604275f, 0.976037079f, + -0.219101240f, 0.975702130f, + -0.220597690f, 0.975364885f, + -0.222093621f, 0.975025345f, + -0.223589029f, 0.974683511f, + -0.225083911f, 0.974339383f, + -0.226578264f, 0.973992962f, + -0.228072083f, 0.973644250f, + -0.229565366f, 0.973293246f, + -0.231058108f, 0.972939952f, + -0.232550307f, 0.972584369f, + -0.234041959f, 0.972226497f, + -0.235533059f, 0.971866337f, + -0.237023606f, 0.971503891f, + -0.238513595f, 0.971139158f, + -0.240003022f, 0.970772141f, + -0.241491885f, 0.970402839f, + -0.242980180f, 0.970031253f, + -0.244467903f, 0.969657385f, + -0.245955050f, 0.969281235f, + -0.247441619f, 0.968902805f, + -0.248927606f, 0.968522094f, + -0.250413007f, 0.968139105f, + -0.251897818f, 0.967753837f, + -0.253382037f, 0.967366292f, + -0.254865660f, 0.966976471f, + -0.256348682f, 0.966584374f, + -0.257831102f, 0.966190003f, + -0.259312915f, 0.965793359f, + -0.260794118f, 0.965394442f, + -0.262274707f, 0.964993253f, + -0.263754679f, 0.964589793f, + -0.265234030f, 0.964184064f, + -0.266712757f, 0.963776066f, + -0.268190857f, 0.963365800f, + -0.269668326f, 0.962953267f, + -0.271145160f, 0.962538468f, + -0.272621355f, 0.962121404f, + -0.274096910f, 0.961702077f, + -0.275571819f, 0.961280486f, + -0.277046080f, 0.960856633f, + -0.278519689f, 0.960430519f, + -0.279992643f, 0.960002146f, + -0.281464938f, 0.959571513f, + -0.282936570f, 0.959138622f, + -0.284407537f, 0.958703475f, + -0.285877835f, 0.958266071f, + -0.287347460f, 0.957826413f, + -0.288816408f, 0.957384501f, + -0.290284677f, 0.956940336f, + -0.291752263f, 0.956493919f, + -0.293219163f, 0.956045251f, + -0.294685372f, 0.955594334f, + -0.296150888f, 0.955141168f, + -0.297615707f, 0.954685755f, + -0.299079826f, 0.954228095f, + -0.300543241f, 0.953768190f, + -0.302005949f, 0.953306040f, + -0.303467947f, 0.952841648f, + -0.304929230f, 0.952375013f, + -0.306389795f, 0.951906137f, + -0.307849640f, 0.951435021f, + -0.309308760f, 0.950961666f, + -0.310767153f, 0.950486074f, + -0.312224814f, 0.950008245f, + -0.313681740f, 0.949528181f, + -0.315137929f, 0.949045882f, + -0.316593376f, 0.948561350f, + -0.318048077f, 0.948074586f, + -0.319502031f, 0.947585591f, + -0.320955232f, 0.947094366f, + -0.322407679f, 0.946600913f, + -0.323859367f, 0.946105232f, + -0.325310292f, 0.945607325f, + -0.326760452f, 0.945107193f, + -0.328209844f, 0.944604837f, + -0.329658463f, 0.944100258f, + -0.331106306f, 0.943593458f, + -0.332553370f, 0.943084437f, + -0.333999651f, 0.942573198f, + -0.335445147f, 0.942059740f, + -0.336889853f, 0.941544065f, + -0.338333767f, 0.941026175f, + -0.339776884f, 0.940506071f, + -0.341219202f, 0.939983753f, + -0.342660717f, 0.939459224f, + -0.344101426f, 0.938932484f, + -0.345541325f, 0.938403534f, + -0.346980411f, 0.937872376f, + -0.348418680f, 0.937339012f, + -0.349856130f, 0.936803442f, + -0.351292756f, 0.936265667f, + -0.352728556f, 0.935725689f, + -0.354163525f, 0.935183510f, + -0.355597662f, 0.934639130f, + -0.357030961f, 0.934092550f, + -0.358463421f, 0.933543773f, + -0.359895037f, 0.932992799f, + -0.361325806f, 0.932439629f, + -0.362755724f, 0.931884266f, + -0.364184790f, 0.931326709f, + -0.365612998f, 0.930766961f, + -0.367040346f, 0.930205023f, + -0.368466830f, 0.929640896f, + -0.369892447f, 0.929074581f, + -0.371317194f, 0.928506080f, + -0.372741067f, 0.927935395f, + -0.374164063f, 0.927362526f, + -0.375586178f, 0.926787474f, + -0.377007410f, 0.926210242f, + -0.378427755f, 0.925630831f, + -0.379847209f, 0.925049241f, + -0.381265769f, 0.924465474f, + -0.382683432f, 0.923879533f, + -0.384100195f, 0.923291417f, + -0.385516054f, 0.922701128f, + -0.386931006f, 0.922108669f, + -0.388345047f, 0.921514039f, + -0.389758174f, 0.920917242f, + -0.391170384f, 0.920318277f, + -0.392581674f, 0.919717146f, + -0.393992040f, 0.919113852f, + -0.395401479f, 0.918508394f, + -0.396809987f, 0.917900776f, + -0.398217562f, 0.917290997f, + -0.399624200f, 0.916679060f, + -0.401029897f, 0.916064966f, + -0.402434651f, 0.915448716f, + -0.403838458f, 0.914830312f, + -0.405241314f, 0.914209756f, + -0.406643217f, 0.913587048f, + -0.408044163f, 0.912962190f, + -0.409444149f, 0.912335185f, + -0.410843171f, 0.911706032f, + -0.412241227f, 0.911074734f, + -0.413638312f, 0.910441292f, + -0.415034424f, 0.909805708f, + -0.416429560f, 0.909167983f, + -0.417823716f, 0.908528119f, + -0.419216888f, 0.907886116f, + -0.420609074f, 0.907241978f, + -0.422000271f, 0.906595705f, + -0.423390474f, 0.905947298f, + -0.424779681f, 0.905296759f, + -0.426167889f, 0.904644091f, + -0.427555093f, 0.903989293f, + -0.428941292f, 0.903332368f, + -0.430326481f, 0.902673318f, + -0.431710658f, 0.902012144f, + -0.433093819f, 0.901348847f, + -0.434475961f, 0.900683429f, + -0.435857080f, 0.900015892f, + -0.437237174f, 0.899346237f, + -0.438616239f, 0.898674466f, + -0.439994271f, 0.898000580f, + -0.441371269f, 0.897324581f, + -0.442747228f, 0.896646470f, + -0.444122145f, 0.895966250f, + -0.445496017f, 0.895283921f, + -0.446868840f, 0.894599486f, + -0.448240612f, 0.893912945f, + -0.449611330f, 0.893224301f, + -0.450980989f, 0.892533555f, + -0.452349587f, 0.891840709f, + -0.453717121f, 0.891145765f, + -0.455083587f, 0.890448723f, + -0.456448982f, 0.889749586f, + -0.457813304f, 0.889048356f, + -0.459176548f, 0.888345033f, + -0.460538711f, 0.887639620f, + -0.461899791f, 0.886932119f, + -0.463259784f, 0.886222530f, + -0.464618686f, 0.885510856f, + -0.465976496f, 0.884797098f, + -0.467333209f, 0.884081259f, + -0.468688822f, 0.883363339f, + -0.470043332f, 0.882643340f, + -0.471396737f, 0.881921264f, + -0.472749032f, 0.881197113f, + -0.474100215f, 0.880470889f, + -0.475450282f, 0.879742593f, + -0.476799230f, 0.879012226f, + -0.478147056f, 0.878279792f, + -0.479493758f, 0.877545290f, + -0.480839331f, 0.876808724f, + -0.482183772f, 0.876070094f, + -0.483527079f, 0.875329403f, + -0.484869248f, 0.874586652f, + -0.486210276f, 0.873841843f, + -0.487550160f, 0.873094978f, + -0.488888897f, 0.872346059f, + -0.490226483f, 0.871595087f, + -0.491562916f, 0.870842063f, + -0.492898192f, 0.870086991f, + -0.494232309f, 0.869329871f, + -0.495565262f, 0.868570706f, + -0.496897049f, 0.867809497f, + -0.498227667f, 0.867046246f, + -0.499557113f, 0.866280954f, + -0.500885383f, 0.865513624f, + -0.502212474f, 0.864744258f, + -0.503538384f, 0.863972856f, + -0.504863109f, 0.863199422f, + -0.506186645f, 0.862423956f, + -0.507508991f, 0.861646461f, + -0.508830143f, 0.860866939f, + -0.510150097f, 0.860085390f, + -0.511468850f, 0.859301818f, + -0.512786401f, 0.858516224f, + -0.514102744f, 0.857728610f, + -0.515417878f, 0.856938977f, + -0.516731799f, 0.856147328f, + -0.518044504f, 0.855353665f, + -0.519355990f, 0.854557988f, + -0.520666254f, 0.853760301f, + -0.521975293f, 0.852960605f, + -0.523283103f, 0.852158902f, + -0.524589683f, 0.851355193f, + -0.525895027f, 0.850549481f, + -0.527199135f, 0.849741768f, + -0.528502002f, 0.848932055f, + -0.529803625f, 0.848120345f, + -0.531104001f, 0.847306639f, + -0.532403128f, 0.846490939f, + -0.533701002f, 0.845673247f, + -0.534997620f, 0.844853565f, + -0.536292979f, 0.844031895f, + -0.537587076f, 0.843208240f, + -0.538879909f, 0.842382600f, + -0.540171473f, 0.841554977f, + -0.541461766f, 0.840725375f, + -0.542750785f, 0.839893794f, + -0.544038527f, 0.839060237f, + -0.545324988f, 0.838224706f, + -0.546610167f, 0.837387202f, + -0.547894059f, 0.836547727f, + -0.549176662f, 0.835706284f, + -0.550457973f, 0.834862875f, + -0.551737988f, 0.834017501f, + -0.553016706f, 0.833170165f, + -0.554294121f, 0.832320868f, + -0.555570233f, 0.831469612f, + -0.556845037f, 0.830616400f, + -0.558118531f, 0.829761234f, + -0.559390712f, 0.828904115f, + -0.560661576f, 0.828045045f, + -0.561931121f, 0.827184027f, + -0.563199344f, 0.826321063f, + -0.564466242f, 0.825456154f, + -0.565731811f, 0.824589303f, + -0.566996049f, 0.823720511f, + -0.568258953f, 0.822849781f, + -0.569520519f, 0.821977115f, + -0.570780746f, 0.821102515f, + -0.572039629f, 0.820225983f, + -0.573297167f, 0.819347520f, + -0.574553355f, 0.818467130f, + -0.575808191f, 0.817584813f, + -0.577061673f, 0.816700573f, + -0.578313796f, 0.815814411f, + -0.579564559f, 0.814926329f, + -0.580813958f, 0.814036330f, + -0.582061990f, 0.813144415f, + -0.583308653f, 0.812250587f, + -0.584553943f, 0.811354847f, + -0.585797857f, 0.810457198f, + -0.587040394f, 0.809557642f, + -0.588281548f, 0.808656182f, + -0.589521319f, 0.807752818f, + -0.590759702f, 0.806847554f, + -0.591996695f, 0.805940391f, + -0.593232295f, 0.805031331f, + -0.594466499f, 0.804120377f, + -0.595699304f, 0.803207531f, + -0.596930708f, 0.802292796f, + -0.598160707f, 0.801376172f, + -0.599389298f, 0.800457662f, + -0.600616479f, 0.799537269f, + -0.601842247f, 0.798614995f, + -0.603066599f, 0.797690841f, + -0.604289531f, 0.796764810f, + -0.605511041f, 0.795836905f, + -0.606731127f, 0.794907126f, + -0.607949785f, 0.793975478f, + -0.609167012f, 0.793041960f, + -0.610382806f, 0.792106577f, + -0.611597164f, 0.791169330f, + -0.612810082f, 0.790230221f, + -0.614021559f, 0.789289253f, + -0.615231591f, 0.788346428f, + -0.616440175f, 0.787401747f, + -0.617647308f, 0.786455214f, + -0.618852988f, 0.785506830f, + -0.620057212f, 0.784556597f, + -0.621259977f, 0.783604519f, + -0.622461279f, 0.782650596f, + -0.623661118f, 0.781694832f, + -0.624859488f, 0.780737229f, + -0.626056388f, 0.779777788f, + -0.627251815f, 0.778816512f, + -0.628445767f, 0.777853404f, + -0.629638239f, 0.776888466f, + -0.630829230f, 0.775921699f, + -0.632018736f, 0.774953107f, + -0.633206755f, 0.773982691f, + -0.634393284f, 0.773010453f, + -0.635578320f, 0.772036397f, + -0.636761861f, 0.771060524f, + -0.637943904f, 0.770082837f, + -0.639124445f, 0.769103338f, + -0.640303482f, 0.768122029f, + -0.641481013f, 0.767138912f, + -0.642657034f, 0.766153990f, + -0.643831543f, 0.765167266f, + -0.645004537f, 0.764178741f, + -0.646176013f, 0.763188417f, + -0.647345969f, 0.762196298f, + -0.648514401f, 0.761202385f, + -0.649681307f, 0.760206682f, + -0.650846685f, 0.759209189f, + -0.652010531f, 0.758209910f, + -0.653172843f, 0.757208847f, + -0.654333618f, 0.756206001f, + -0.655492853f, 0.755201377f, + -0.656650546f, 0.754194975f, + -0.657806693f, 0.753186799f, + -0.658961293f, 0.752176850f, + -0.660114342f, 0.751165132f, + -0.661265838f, 0.750151646f, + -0.662415778f, 0.749136395f, + -0.663564159f, 0.748119380f, + -0.664710978f, 0.747100606f, + -0.665856234f, 0.746080074f, + -0.666999922f, 0.745057785f, + -0.668142041f, 0.744033744f, + -0.669282588f, 0.743007952f, + -0.670421560f, 0.741980412f, + -0.671558955f, 0.740951125f, + -0.672694769f, 0.739920095f, + -0.673829000f, 0.738887324f, + -0.674961646f, 0.737852815f, + -0.676092704f, 0.736816569f, + -0.677222170f, 0.735778589f, + -0.678350043f, 0.734738878f, + -0.679476320f, 0.733697438f, + -0.680600998f, 0.732654272f, + -0.681724074f, 0.731609381f, + -0.682845546f, 0.730562769f, + -0.683965412f, 0.729514438f, + -0.685083668f, 0.728464390f, + -0.686200312f, 0.727412629f, + -0.687315341f, 0.726359155f, + -0.688428753f, 0.725303972f, + -0.689540545f, 0.724247083f, + -0.690650714f, 0.723188489f, + -0.691759258f, 0.722128194f, + -0.692866175f, 0.721066199f, + -0.693971461f, 0.720002508f, + -0.695075114f, 0.718937122f, + -0.696177131f, 0.717870045f, + -0.697277511f, 0.716801279f, + -0.698376249f, 0.715730825f, + -0.699473345f, 0.714658688f, + -0.700568794f, 0.713584869f, + -0.701662595f, 0.712509371f, + -0.702754744f, 0.711432196f, + -0.703845241f, 0.710353347f, + -0.704934080f, 0.709272826f, + -0.706021261f, 0.708190637f, + -0.707106781f, 0.707106781f, + -0.708190637f, 0.706021261f, + -0.709272826f, 0.704934080f, + -0.710353347f, 0.703845241f, + -0.711432196f, 0.702754744f, + -0.712509371f, 0.701662595f, + -0.713584869f, 0.700568794f, + -0.714658688f, 0.699473345f, + -0.715730825f, 0.698376249f, + -0.716801279f, 0.697277511f, + -0.717870045f, 0.696177131f, + -0.718937122f, 0.695075114f, + -0.720002508f, 0.693971461f, + -0.721066199f, 0.692866175f, + -0.722128194f, 0.691759258f, + -0.723188489f, 0.690650714f, + -0.724247083f, 0.689540545f, + -0.725303972f, 0.688428753f, + -0.726359155f, 0.687315341f, + -0.727412629f, 0.686200312f, + -0.728464390f, 0.685083668f, + -0.729514438f, 0.683965412f, + -0.730562769f, 0.682845546f, + -0.731609381f, 0.681724074f, + -0.732654272f, 0.680600998f, + -0.733697438f, 0.679476320f, + -0.734738878f, 0.678350043f, + -0.735778589f, 0.677222170f, + -0.736816569f, 0.676092704f, + -0.737852815f, 0.674961646f, + -0.738887324f, 0.673829000f, + -0.739920095f, 0.672694769f, + -0.740951125f, 0.671558955f, + -0.741980412f, 0.670421560f, + -0.743007952f, 0.669282588f, + -0.744033744f, 0.668142041f, + -0.745057785f, 0.666999922f, + -0.746080074f, 0.665856234f, + -0.747100606f, 0.664710978f, + -0.748119380f, 0.663564159f, + -0.749136395f, 0.662415778f, + -0.750151646f, 0.661265838f, + -0.751165132f, 0.660114342f, + -0.752176850f, 0.658961293f, + -0.753186799f, 0.657806693f, + -0.754194975f, 0.656650546f, + -0.755201377f, 0.655492853f, + -0.756206001f, 0.654333618f, + -0.757208847f, 0.653172843f, + -0.758209910f, 0.652010531f, + -0.759209189f, 0.650846685f, + -0.760206682f, 0.649681307f, + -0.761202385f, 0.648514401f, + -0.762196298f, 0.647345969f, + -0.763188417f, 0.646176013f, + -0.764178741f, 0.645004537f, + -0.765167266f, 0.643831543f, + -0.766153990f, 0.642657034f, + -0.767138912f, 0.641481013f, + -0.768122029f, 0.640303482f, + -0.769103338f, 0.639124445f, + -0.770082837f, 0.637943904f, + -0.771060524f, 0.636761861f, + -0.772036397f, 0.635578320f, + -0.773010453f, 0.634393284f, + -0.773982691f, 0.633206755f, + -0.774953107f, 0.632018736f, + -0.775921699f, 0.630829230f, + -0.776888466f, 0.629638239f, + -0.777853404f, 0.628445767f, + -0.778816512f, 0.627251815f, + -0.779777788f, 0.626056388f, + -0.780737229f, 0.624859488f, + -0.781694832f, 0.623661118f, + -0.782650596f, 0.622461279f, + -0.783604519f, 0.621259977f, + -0.784556597f, 0.620057212f, + -0.785506830f, 0.618852988f, + -0.786455214f, 0.617647308f, + -0.787401747f, 0.616440175f, + -0.788346428f, 0.615231591f, + -0.789289253f, 0.614021559f, + -0.790230221f, 0.612810082f, + -0.791169330f, 0.611597164f, + -0.792106577f, 0.610382806f, + -0.793041960f, 0.609167012f, + -0.793975478f, 0.607949785f, + -0.794907126f, 0.606731127f, + -0.795836905f, 0.605511041f, + -0.796764810f, 0.604289531f, + -0.797690841f, 0.603066599f, + -0.798614995f, 0.601842247f, + -0.799537269f, 0.600616479f, + -0.800457662f, 0.599389298f, + -0.801376172f, 0.598160707f, + -0.802292796f, 0.596930708f, + -0.803207531f, 0.595699304f, + -0.804120377f, 0.594466499f, + -0.805031331f, 0.593232295f, + -0.805940391f, 0.591996695f, + -0.806847554f, 0.590759702f, + -0.807752818f, 0.589521319f, + -0.808656182f, 0.588281548f, + -0.809557642f, 0.587040394f, + -0.810457198f, 0.585797857f, + -0.811354847f, 0.584553943f, + -0.812250587f, 0.583308653f, + -0.813144415f, 0.582061990f, + -0.814036330f, 0.580813958f, + -0.814926329f, 0.579564559f, + -0.815814411f, 0.578313796f, + -0.816700573f, 0.577061673f, + -0.817584813f, 0.575808191f, + -0.818467130f, 0.574553355f, + -0.819347520f, 0.573297167f, + -0.820225983f, 0.572039629f, + -0.821102515f, 0.570780746f, + -0.821977115f, 0.569520519f, + -0.822849781f, 0.568258953f, + -0.823720511f, 0.566996049f, + -0.824589303f, 0.565731811f, + -0.825456154f, 0.564466242f, + -0.826321063f, 0.563199344f, + -0.827184027f, 0.561931121f, + -0.828045045f, 0.560661576f, + -0.828904115f, 0.559390712f, + -0.829761234f, 0.558118531f, + -0.830616400f, 0.556845037f, + -0.831469612f, 0.555570233f, + -0.832320868f, 0.554294121f, + -0.833170165f, 0.553016706f, + -0.834017501f, 0.551737988f, + -0.834862875f, 0.550457973f, + -0.835706284f, 0.549176662f, + -0.836547727f, 0.547894059f, + -0.837387202f, 0.546610167f, + -0.838224706f, 0.545324988f, + -0.839060237f, 0.544038527f, + -0.839893794f, 0.542750785f, + -0.840725375f, 0.541461766f, + -0.841554977f, 0.540171473f, + -0.842382600f, 0.538879909f, + -0.843208240f, 0.537587076f, + -0.844031895f, 0.536292979f, + -0.844853565f, 0.534997620f, + -0.845673247f, 0.533701002f, + -0.846490939f, 0.532403128f, + -0.847306639f, 0.531104001f, + -0.848120345f, 0.529803625f, + -0.848932055f, 0.528502002f, + -0.849741768f, 0.527199135f, + -0.850549481f, 0.525895027f, + -0.851355193f, 0.524589683f, + -0.852158902f, 0.523283103f, + -0.852960605f, 0.521975293f, + -0.853760301f, 0.520666254f, + -0.854557988f, 0.519355990f, + -0.855353665f, 0.518044504f, + -0.856147328f, 0.516731799f, + -0.856938977f, 0.515417878f, + -0.857728610f, 0.514102744f, + -0.858516224f, 0.512786401f, + -0.859301818f, 0.511468850f, + -0.860085390f, 0.510150097f, + -0.860866939f, 0.508830143f, + -0.861646461f, 0.507508991f, + -0.862423956f, 0.506186645f, + -0.863199422f, 0.504863109f, + -0.863972856f, 0.503538384f, + -0.864744258f, 0.502212474f, + -0.865513624f, 0.500885383f, + -0.866280954f, 0.499557113f, + -0.867046246f, 0.498227667f, + -0.867809497f, 0.496897049f, + -0.868570706f, 0.495565262f, + -0.869329871f, 0.494232309f, + -0.870086991f, 0.492898192f, + -0.870842063f, 0.491562916f, + -0.871595087f, 0.490226483f, + -0.872346059f, 0.488888897f, + -0.873094978f, 0.487550160f, + -0.873841843f, 0.486210276f, + -0.874586652f, 0.484869248f, + -0.875329403f, 0.483527079f, + -0.876070094f, 0.482183772f, + -0.876808724f, 0.480839331f, + -0.877545290f, 0.479493758f, + -0.878279792f, 0.478147056f, + -0.879012226f, 0.476799230f, + -0.879742593f, 0.475450282f, + -0.880470889f, 0.474100215f, + -0.881197113f, 0.472749032f, + -0.881921264f, 0.471396737f, + -0.882643340f, 0.470043332f, + -0.883363339f, 0.468688822f, + -0.884081259f, 0.467333209f, + -0.884797098f, 0.465976496f, + -0.885510856f, 0.464618686f, + -0.886222530f, 0.463259784f, + -0.886932119f, 0.461899791f, + -0.887639620f, 0.460538711f, + -0.888345033f, 0.459176548f, + -0.889048356f, 0.457813304f, + -0.889749586f, 0.456448982f, + -0.890448723f, 0.455083587f, + -0.891145765f, 0.453717121f, + -0.891840709f, 0.452349587f, + -0.892533555f, 0.450980989f, + -0.893224301f, 0.449611330f, + -0.893912945f, 0.448240612f, + -0.894599486f, 0.446868840f, + -0.895283921f, 0.445496017f, + -0.895966250f, 0.444122145f, + -0.896646470f, 0.442747228f, + -0.897324581f, 0.441371269f, + -0.898000580f, 0.439994271f, + -0.898674466f, 0.438616239f, + -0.899346237f, 0.437237174f, + -0.900015892f, 0.435857080f, + -0.900683429f, 0.434475961f, + -0.901348847f, 0.433093819f, + -0.902012144f, 0.431710658f, + -0.902673318f, 0.430326481f, + -0.903332368f, 0.428941292f, + -0.903989293f, 0.427555093f, + -0.904644091f, 0.426167889f, + -0.905296759f, 0.424779681f, + -0.905947298f, 0.423390474f, + -0.906595705f, 0.422000271f, + -0.907241978f, 0.420609074f, + -0.907886116f, 0.419216888f, + -0.908528119f, 0.417823716f, + -0.909167983f, 0.416429560f, + -0.909805708f, 0.415034424f, + -0.910441292f, 0.413638312f, + -0.911074734f, 0.412241227f, + -0.911706032f, 0.410843171f, + -0.912335185f, 0.409444149f, + -0.912962190f, 0.408044163f, + -0.913587048f, 0.406643217f, + -0.914209756f, 0.405241314f, + -0.914830312f, 0.403838458f, + -0.915448716f, 0.402434651f, + -0.916064966f, 0.401029897f, + -0.916679060f, 0.399624200f, + -0.917290997f, 0.398217562f, + -0.917900776f, 0.396809987f, + -0.918508394f, 0.395401479f, + -0.919113852f, 0.393992040f, + -0.919717146f, 0.392581674f, + -0.920318277f, 0.391170384f, + -0.920917242f, 0.389758174f, + -0.921514039f, 0.388345047f, + -0.922108669f, 0.386931006f, + -0.922701128f, 0.385516054f, + -0.923291417f, 0.384100195f, + -0.923879533f, 0.382683432f, + -0.924465474f, 0.381265769f, + -0.925049241f, 0.379847209f, + -0.925630831f, 0.378427755f, + -0.926210242f, 0.377007410f, + -0.926787474f, 0.375586178f, + -0.927362526f, 0.374164063f, + -0.927935395f, 0.372741067f, + -0.928506080f, 0.371317194f, + -0.929074581f, 0.369892447f, + -0.929640896f, 0.368466830f, + -0.930205023f, 0.367040346f, + -0.930766961f, 0.365612998f, + -0.931326709f, 0.364184790f, + -0.931884266f, 0.362755724f, + -0.932439629f, 0.361325806f, + -0.932992799f, 0.359895037f, + -0.933543773f, 0.358463421f, + -0.934092550f, 0.357030961f, + -0.934639130f, 0.355597662f, + -0.935183510f, 0.354163525f, + -0.935725689f, 0.352728556f, + -0.936265667f, 0.351292756f, + -0.936803442f, 0.349856130f, + -0.937339012f, 0.348418680f, + -0.937872376f, 0.346980411f, + -0.938403534f, 0.345541325f, + -0.938932484f, 0.344101426f, + -0.939459224f, 0.342660717f, + -0.939983753f, 0.341219202f, + -0.940506071f, 0.339776884f, + -0.941026175f, 0.338333767f, + -0.941544065f, 0.336889853f, + -0.942059740f, 0.335445147f, + -0.942573198f, 0.333999651f, + -0.943084437f, 0.332553370f, + -0.943593458f, 0.331106306f, + -0.944100258f, 0.329658463f, + -0.944604837f, 0.328209844f, + -0.945107193f, 0.326760452f, + -0.945607325f, 0.325310292f, + -0.946105232f, 0.323859367f, + -0.946600913f, 0.322407679f, + -0.947094366f, 0.320955232f, + -0.947585591f, 0.319502031f, + -0.948074586f, 0.318048077f, + -0.948561350f, 0.316593376f, + -0.949045882f, 0.315137929f, + -0.949528181f, 0.313681740f, + -0.950008245f, 0.312224814f, + -0.950486074f, 0.310767153f, + -0.950961666f, 0.309308760f, + -0.951435021f, 0.307849640f, + -0.951906137f, 0.306389795f, + -0.952375013f, 0.304929230f, + -0.952841648f, 0.303467947f, + -0.953306040f, 0.302005949f, + -0.953768190f, 0.300543241f, + -0.954228095f, 0.299079826f, + -0.954685755f, 0.297615707f, + -0.955141168f, 0.296150888f, + -0.955594334f, 0.294685372f, + -0.956045251f, 0.293219163f, + -0.956493919f, 0.291752263f, + -0.956940336f, 0.290284677f, + -0.957384501f, 0.288816408f, + -0.957826413f, 0.287347460f, + -0.958266071f, 0.285877835f, + -0.958703475f, 0.284407537f, + -0.959138622f, 0.282936570f, + -0.959571513f, 0.281464938f, + -0.960002146f, 0.279992643f, + -0.960430519f, 0.278519689f, + -0.960856633f, 0.277046080f, + -0.961280486f, 0.275571819f, + -0.961702077f, 0.274096910f, + -0.962121404f, 0.272621355f, + -0.962538468f, 0.271145160f, + -0.962953267f, 0.269668326f, + -0.963365800f, 0.268190857f, + -0.963776066f, 0.266712757f, + -0.964184064f, 0.265234030f, + -0.964589793f, 0.263754679f, + -0.964993253f, 0.262274707f, + -0.965394442f, 0.260794118f, + -0.965793359f, 0.259312915f, + -0.966190003f, 0.257831102f, + -0.966584374f, 0.256348682f, + -0.966976471f, 0.254865660f, + -0.967366292f, 0.253382037f, + -0.967753837f, 0.251897818f, + -0.968139105f, 0.250413007f, + -0.968522094f, 0.248927606f, + -0.968902805f, 0.247441619f, + -0.969281235f, 0.245955050f, + -0.969657385f, 0.244467903f, + -0.970031253f, 0.242980180f, + -0.970402839f, 0.241491885f, + -0.970772141f, 0.240003022f, + -0.971139158f, 0.238513595f, + -0.971503891f, 0.237023606f, + -0.971866337f, 0.235533059f, + -0.972226497f, 0.234041959f, + -0.972584369f, 0.232550307f, + -0.972939952f, 0.231058108f, + -0.973293246f, 0.229565366f, + -0.973644250f, 0.228072083f, + -0.973992962f, 0.226578264f, + -0.974339383f, 0.225083911f, + -0.974683511f, 0.223589029f, + -0.975025345f, 0.222093621f, + -0.975364885f, 0.220597690f, + -0.975702130f, 0.219101240f, + -0.976037079f, 0.217604275f, + -0.976369731f, 0.216106797f, + -0.976700086f, 0.214608811f, + -0.977028143f, 0.213110320f, + -0.977353900f, 0.211611327f, + -0.977677358f, 0.210111837f, + -0.977998515f, 0.208611852f, + -0.978317371f, 0.207111376f, + -0.978633924f, 0.205610413f, + -0.978948175f, 0.204108966f, + -0.979260123f, 0.202607039f, + -0.979569766f, 0.201104635f, + -0.979877104f, 0.199601758f, + -0.980182136f, 0.198098411f, + -0.980484862f, 0.196594598f, + -0.980785280f, 0.195090322f, + -0.981083391f, 0.193585587f, + -0.981379193f, 0.192080397f, + -0.981672686f, 0.190574755f, + -0.981963869f, 0.189068664f, + -0.982252741f, 0.187562129f, + -0.982539302f, 0.186055152f, + -0.982823551f, 0.184547737f, + -0.983105487f, 0.183039888f, + -0.983385110f, 0.181531608f, + -0.983662419f, 0.180022901f, + -0.983937413f, 0.178513771f, + -0.984210092f, 0.177004220f, + -0.984480455f, 0.175494253f, + -0.984748502f, 0.173983873f, + -0.985014231f, 0.172473084f, + -0.985277642f, 0.170961889f, + -0.985538735f, 0.169450291f, + -0.985797509f, 0.167938295f, + -0.986053963f, 0.166425904f, + -0.986308097f, 0.164913120f, + -0.986559910f, 0.163399949f, + -0.986809402f, 0.161886394f, + -0.987056571f, 0.160372457f, + -0.987301418f, 0.158858143f, + -0.987543942f, 0.157343456f, + -0.987784142f, 0.155828398f, + -0.988022017f, 0.154312973f, + -0.988257568f, 0.152797185f, + -0.988490793f, 0.151281038f, + -0.988721692f, 0.149764535f, + -0.988950265f, 0.148247679f, + -0.989176510f, 0.146730474f, + -0.989400428f, 0.145212925f, + -0.989622017f, 0.143695033f, + -0.989841278f, 0.142176804f, + -0.990058210f, 0.140658239f, + -0.990272812f, 0.139139344f, + -0.990485084f, 0.137620122f, + -0.990695025f, 0.136100575f, + -0.990902635f, 0.134580709f, + -0.991107914f, 0.133060525f, + -0.991310860f, 0.131540029f, + -0.991511473f, 0.130019223f, + -0.991709754f, 0.128498111f, + -0.991905700f, 0.126976696f, + -0.992099313f, 0.125454983f, + -0.992290591f, 0.123932975f, + -0.992479535f, 0.122410675f, + -0.992666142f, 0.120888087f, + -0.992850414f, 0.119365215f, + -0.993032350f, 0.117842062f, + -0.993211949f, 0.116318631f, + -0.993389211f, 0.114794927f, + -0.993564136f, 0.113270952f, + -0.993736722f, 0.111746711f, + -0.993906970f, 0.110222207f, + -0.994074879f, 0.108697444f, + -0.994240449f, 0.107172425f, + -0.994403680f, 0.105647154f, + -0.994564571f, 0.104121634f, + -0.994723121f, 0.102595869f, + -0.994879331f, 0.101069863f, + -0.995033199f, 0.099543619f, + -0.995184727f, 0.098017140f, + -0.995333912f, 0.096490431f, + -0.995480755f, 0.094963495f, + -0.995625256f, 0.093436336f, + -0.995767414f, 0.091908956f, + -0.995907229f, 0.090381361f, + -0.996044701f, 0.088853553f, + -0.996179829f, 0.087325535f, + -0.996312612f, 0.085797312f, + -0.996443051f, 0.084268888f, + -0.996571146f, 0.082740265f, + -0.996696895f, 0.081211447f, + -0.996820299f, 0.079682438f, + -0.996941358f, 0.078153242f, + -0.997060070f, 0.076623861f, + -0.997176437f, 0.075094301f, + -0.997290457f, 0.073564564f, + -0.997402130f, 0.072034653f, + -0.997511456f, 0.070504573f, + -0.997618435f, 0.068974328f, + -0.997723067f, 0.067443920f, + -0.997825350f, 0.065913353f, + -0.997925286f, 0.064382631f, + -0.998022874f, 0.062851758f, + -0.998118113f, 0.061320736f, + -0.998211003f, 0.059789571f, + -0.998301545f, 0.058258265f, + -0.998389737f, 0.056726821f, + -0.998475581f, 0.055195244f, + -0.998559074f, 0.053663538f, + -0.998640218f, 0.052131705f, + -0.998719012f, 0.050599749f, + -0.998795456f, 0.049067674f, + -0.998869550f, 0.047535484f, + -0.998941293f, 0.046003182f, + -0.999010686f, 0.044470772f, + -0.999077728f, 0.042938257f, + -0.999142419f, 0.041405641f, + -0.999204759f, 0.039872928f, + -0.999264747f, 0.038340120f, + -0.999322385f, 0.036807223f, + -0.999377670f, 0.035274239f, + -0.999430605f, 0.033741172f, + -0.999481187f, 0.032208025f, + -0.999529418f, 0.030674803f, + -0.999575296f, 0.029141509f, + -0.999618822f, 0.027608146f, + -0.999659997f, 0.026074718f, + -0.999698819f, 0.024541229f, + -0.999735288f, 0.023007681f, + -0.999769405f, 0.021474080f, + -0.999801170f, 0.019940429f, + -0.999830582f, 0.018406730f, + -0.999857641f, 0.016872988f, + -0.999882347f, 0.015339206f, + -0.999904701f, 0.013805389f, + -0.999924702f, 0.012271538f, + -0.999942350f, 0.010737659f, + -0.999957645f, 0.009203755f, + -0.999970586f, 0.007669829f, + -0.999981175f, 0.006135885f, + -0.999989411f, 0.004601926f, + -0.999995294f, 0.003067957f, + -0.999998823f, 0.001533980f, + -1.000000000f, 0.000000000f, + -0.999998823f, -0.001533980f, + -0.999995294f, -0.003067957f, + -0.999989411f, -0.004601926f, + -0.999981175f, -0.006135885f, + -0.999970586f, -0.007669829f, + -0.999957645f, -0.009203755f, + -0.999942350f, -0.010737659f, + -0.999924702f, -0.012271538f, + -0.999904701f, -0.013805389f, + -0.999882347f, -0.015339206f, + -0.999857641f, -0.016872988f, + -0.999830582f, -0.018406730f, + -0.999801170f, -0.019940429f, + -0.999769405f, -0.021474080f, + -0.999735288f, -0.023007681f, + -0.999698819f, -0.024541229f, + -0.999659997f, -0.026074718f, + -0.999618822f, -0.027608146f, + -0.999575296f, -0.029141509f, + -0.999529418f, -0.030674803f, + -0.999481187f, -0.032208025f, + -0.999430605f, -0.033741172f, + -0.999377670f, -0.035274239f, + -0.999322385f, -0.036807223f, + -0.999264747f, -0.038340120f, + -0.999204759f, -0.039872928f, + -0.999142419f, -0.041405641f, + -0.999077728f, -0.042938257f, + -0.999010686f, -0.044470772f, + -0.998941293f, -0.046003182f, + -0.998869550f, -0.047535484f, + -0.998795456f, -0.049067674f, + -0.998719012f, -0.050599749f, + -0.998640218f, -0.052131705f, + -0.998559074f, -0.053663538f, + -0.998475581f, -0.055195244f, + -0.998389737f, -0.056726821f, + -0.998301545f, -0.058258265f, + -0.998211003f, -0.059789571f, + -0.998118113f, -0.061320736f, + -0.998022874f, -0.062851758f, + -0.997925286f, -0.064382631f, + -0.997825350f, -0.065913353f, + -0.997723067f, -0.067443920f, + -0.997618435f, -0.068974328f, + -0.997511456f, -0.070504573f, + -0.997402130f, -0.072034653f, + -0.997290457f, -0.073564564f, + -0.997176437f, -0.075094301f, + -0.997060070f, -0.076623861f, + -0.996941358f, -0.078153242f, + -0.996820299f, -0.079682438f, + -0.996696895f, -0.081211447f, + -0.996571146f, -0.082740265f, + -0.996443051f, -0.084268888f, + -0.996312612f, -0.085797312f, + -0.996179829f, -0.087325535f, + -0.996044701f, -0.088853553f, + -0.995907229f, -0.090381361f, + -0.995767414f, -0.091908956f, + -0.995625256f, -0.093436336f, + -0.995480755f, -0.094963495f, + -0.995333912f, -0.096490431f, + -0.995184727f, -0.098017140f, + -0.995033199f, -0.099543619f, + -0.994879331f, -0.101069863f, + -0.994723121f, -0.102595869f, + -0.994564571f, -0.104121634f, + -0.994403680f, -0.105647154f, + -0.994240449f, -0.107172425f, + -0.994074879f, -0.108697444f, + -0.993906970f, -0.110222207f, + -0.993736722f, -0.111746711f, + -0.993564136f, -0.113270952f, + -0.993389211f, -0.114794927f, + -0.993211949f, -0.116318631f, + -0.993032350f, -0.117842062f, + -0.992850414f, -0.119365215f, + -0.992666142f, -0.120888087f, + -0.992479535f, -0.122410675f, + -0.992290591f, -0.123932975f, + -0.992099313f, -0.125454983f, + -0.991905700f, -0.126976696f, + -0.991709754f, -0.128498111f, + -0.991511473f, -0.130019223f, + -0.991310860f, -0.131540029f, + -0.991107914f, -0.133060525f, + -0.990902635f, -0.134580709f, + -0.990695025f, -0.136100575f, + -0.990485084f, -0.137620122f, + -0.990272812f, -0.139139344f, + -0.990058210f, -0.140658239f, + -0.989841278f, -0.142176804f, + -0.989622017f, -0.143695033f, + -0.989400428f, -0.145212925f, + -0.989176510f, -0.146730474f, + -0.988950265f, -0.148247679f, + -0.988721692f, -0.149764535f, + -0.988490793f, -0.151281038f, + -0.988257568f, -0.152797185f, + -0.988022017f, -0.154312973f, + -0.987784142f, -0.155828398f, + -0.987543942f, -0.157343456f, + -0.987301418f, -0.158858143f, + -0.987056571f, -0.160372457f, + -0.986809402f, -0.161886394f, + -0.986559910f, -0.163399949f, + -0.986308097f, -0.164913120f, + -0.986053963f, -0.166425904f, + -0.985797509f, -0.167938295f, + -0.985538735f, -0.169450291f, + -0.985277642f, -0.170961889f, + -0.985014231f, -0.172473084f, + -0.984748502f, -0.173983873f, + -0.984480455f, -0.175494253f, + -0.984210092f, -0.177004220f, + -0.983937413f, -0.178513771f, + -0.983662419f, -0.180022901f, + -0.983385110f, -0.181531608f, + -0.983105487f, -0.183039888f, + -0.982823551f, -0.184547737f, + -0.982539302f, -0.186055152f, + -0.982252741f, -0.187562129f, + -0.981963869f, -0.189068664f, + -0.981672686f, -0.190574755f, + -0.981379193f, -0.192080397f, + -0.981083391f, -0.193585587f, + -0.980785280f, -0.195090322f, + -0.980484862f, -0.196594598f, + -0.980182136f, -0.198098411f, + -0.979877104f, -0.199601758f, + -0.979569766f, -0.201104635f, + -0.979260123f, -0.202607039f, + -0.978948175f, -0.204108966f, + -0.978633924f, -0.205610413f, + -0.978317371f, -0.207111376f, + -0.977998515f, -0.208611852f, + -0.977677358f, -0.210111837f, + -0.977353900f, -0.211611327f, + -0.977028143f, -0.213110320f, + -0.976700086f, -0.214608811f, + -0.976369731f, -0.216106797f, + -0.976037079f, -0.217604275f, + -0.975702130f, -0.219101240f, + -0.975364885f, -0.220597690f, + -0.975025345f, -0.222093621f, + -0.974683511f, -0.223589029f, + -0.974339383f, -0.225083911f, + -0.973992962f, -0.226578264f, + -0.973644250f, -0.228072083f, + -0.973293246f, -0.229565366f, + -0.972939952f, -0.231058108f, + -0.972584369f, -0.232550307f, + -0.972226497f, -0.234041959f, + -0.971866337f, -0.235533059f, + -0.971503891f, -0.237023606f, + -0.971139158f, -0.238513595f, + -0.970772141f, -0.240003022f, + -0.970402839f, -0.241491885f, + -0.970031253f, -0.242980180f, + -0.969657385f, -0.244467903f, + -0.969281235f, -0.245955050f, + -0.968902805f, -0.247441619f, + -0.968522094f, -0.248927606f, + -0.968139105f, -0.250413007f, + -0.967753837f, -0.251897818f, + -0.967366292f, -0.253382037f, + -0.966976471f, -0.254865660f, + -0.966584374f, -0.256348682f, + -0.966190003f, -0.257831102f, + -0.965793359f, -0.259312915f, + -0.965394442f, -0.260794118f, + -0.964993253f, -0.262274707f, + -0.964589793f, -0.263754679f, + -0.964184064f, -0.265234030f, + -0.963776066f, -0.266712757f, + -0.963365800f, -0.268190857f, + -0.962953267f, -0.269668326f, + -0.962538468f, -0.271145160f, + -0.962121404f, -0.272621355f, + -0.961702077f, -0.274096910f, + -0.961280486f, -0.275571819f, + -0.960856633f, -0.277046080f, + -0.960430519f, -0.278519689f, + -0.960002146f, -0.279992643f, + -0.959571513f, -0.281464938f, + -0.959138622f, -0.282936570f, + -0.958703475f, -0.284407537f, + -0.958266071f, -0.285877835f, + -0.957826413f, -0.287347460f, + -0.957384501f, -0.288816408f, + -0.956940336f, -0.290284677f, + -0.956493919f, -0.291752263f, + -0.956045251f, -0.293219163f, + -0.955594334f, -0.294685372f, + -0.955141168f, -0.296150888f, + -0.954685755f, -0.297615707f, + -0.954228095f, -0.299079826f, + -0.953768190f, -0.300543241f, + -0.953306040f, -0.302005949f, + -0.952841648f, -0.303467947f, + -0.952375013f, -0.304929230f, + -0.951906137f, -0.306389795f, + -0.951435021f, -0.307849640f, + -0.950961666f, -0.309308760f, + -0.950486074f, -0.310767153f, + -0.950008245f, -0.312224814f, + -0.949528181f, -0.313681740f, + -0.949045882f, -0.315137929f, + -0.948561350f, -0.316593376f, + -0.948074586f, -0.318048077f, + -0.947585591f, -0.319502031f, + -0.947094366f, -0.320955232f, + -0.946600913f, -0.322407679f, + -0.946105232f, -0.323859367f, + -0.945607325f, -0.325310292f, + -0.945107193f, -0.326760452f, + -0.944604837f, -0.328209844f, + -0.944100258f, -0.329658463f, + -0.943593458f, -0.331106306f, + -0.943084437f, -0.332553370f, + -0.942573198f, -0.333999651f, + -0.942059740f, -0.335445147f, + -0.941544065f, -0.336889853f, + -0.941026175f, -0.338333767f, + -0.940506071f, -0.339776884f, + -0.939983753f, -0.341219202f, + -0.939459224f, -0.342660717f, + -0.938932484f, -0.344101426f, + -0.938403534f, -0.345541325f, + -0.937872376f, -0.346980411f, + -0.937339012f, -0.348418680f, + -0.936803442f, -0.349856130f, + -0.936265667f, -0.351292756f, + -0.935725689f, -0.352728556f, + -0.935183510f, -0.354163525f, + -0.934639130f, -0.355597662f, + -0.934092550f, -0.357030961f, + -0.933543773f, -0.358463421f, + -0.932992799f, -0.359895037f, + -0.932439629f, -0.361325806f, + -0.931884266f, -0.362755724f, + -0.931326709f, -0.364184790f, + -0.930766961f, -0.365612998f, + -0.930205023f, -0.367040346f, + -0.929640896f, -0.368466830f, + -0.929074581f, -0.369892447f, + -0.928506080f, -0.371317194f, + -0.927935395f, -0.372741067f, + -0.927362526f, -0.374164063f, + -0.926787474f, -0.375586178f, + -0.926210242f, -0.377007410f, + -0.925630831f, -0.378427755f, + -0.925049241f, -0.379847209f, + -0.924465474f, -0.381265769f, + -0.923879533f, -0.382683432f, + -0.923291417f, -0.384100195f, + -0.922701128f, -0.385516054f, + -0.922108669f, -0.386931006f, + -0.921514039f, -0.388345047f, + -0.920917242f, -0.389758174f, + -0.920318277f, -0.391170384f, + -0.919717146f, -0.392581674f, + -0.919113852f, -0.393992040f, + -0.918508394f, -0.395401479f, + -0.917900776f, -0.396809987f, + -0.917290997f, -0.398217562f, + -0.916679060f, -0.399624200f, + -0.916064966f, -0.401029897f, + -0.915448716f, -0.402434651f, + -0.914830312f, -0.403838458f, + -0.914209756f, -0.405241314f, + -0.913587048f, -0.406643217f, + -0.912962190f, -0.408044163f, + -0.912335185f, -0.409444149f, + -0.911706032f, -0.410843171f, + -0.911074734f, -0.412241227f, + -0.910441292f, -0.413638312f, + -0.909805708f, -0.415034424f, + -0.909167983f, -0.416429560f, + -0.908528119f, -0.417823716f, + -0.907886116f, -0.419216888f, + -0.907241978f, -0.420609074f, + -0.906595705f, -0.422000271f, + -0.905947298f, -0.423390474f, + -0.905296759f, -0.424779681f, + -0.904644091f, -0.426167889f, + -0.903989293f, -0.427555093f, + -0.903332368f, -0.428941292f, + -0.902673318f, -0.430326481f, + -0.902012144f, -0.431710658f, + -0.901348847f, -0.433093819f, + -0.900683429f, -0.434475961f, + -0.900015892f, -0.435857080f, + -0.899346237f, -0.437237174f, + -0.898674466f, -0.438616239f, + -0.898000580f, -0.439994271f, + -0.897324581f, -0.441371269f, + -0.896646470f, -0.442747228f, + -0.895966250f, -0.444122145f, + -0.895283921f, -0.445496017f, + -0.894599486f, -0.446868840f, + -0.893912945f, -0.448240612f, + -0.893224301f, -0.449611330f, + -0.892533555f, -0.450980989f, + -0.891840709f, -0.452349587f, + -0.891145765f, -0.453717121f, + -0.890448723f, -0.455083587f, + -0.889749586f, -0.456448982f, + -0.889048356f, -0.457813304f, + -0.888345033f, -0.459176548f, + -0.887639620f, -0.460538711f, + -0.886932119f, -0.461899791f, + -0.886222530f, -0.463259784f, + -0.885510856f, -0.464618686f, + -0.884797098f, -0.465976496f, + -0.884081259f, -0.467333209f, + -0.883363339f, -0.468688822f, + -0.882643340f, -0.470043332f, + -0.881921264f, -0.471396737f, + -0.881197113f, -0.472749032f, + -0.880470889f, -0.474100215f, + -0.879742593f, -0.475450282f, + -0.879012226f, -0.476799230f, + -0.878279792f, -0.478147056f, + -0.877545290f, -0.479493758f, + -0.876808724f, -0.480839331f, + -0.876070094f, -0.482183772f, + -0.875329403f, -0.483527079f, + -0.874586652f, -0.484869248f, + -0.873841843f, -0.486210276f, + -0.873094978f, -0.487550160f, + -0.872346059f, -0.488888897f, + -0.871595087f, -0.490226483f, + -0.870842063f, -0.491562916f, + -0.870086991f, -0.492898192f, + -0.869329871f, -0.494232309f, + -0.868570706f, -0.495565262f, + -0.867809497f, -0.496897049f, + -0.867046246f, -0.498227667f, + -0.866280954f, -0.499557113f, + -0.865513624f, -0.500885383f, + -0.864744258f, -0.502212474f, + -0.863972856f, -0.503538384f, + -0.863199422f, -0.504863109f, + -0.862423956f, -0.506186645f, + -0.861646461f, -0.507508991f, + -0.860866939f, -0.508830143f, + -0.860085390f, -0.510150097f, + -0.859301818f, -0.511468850f, + -0.858516224f, -0.512786401f, + -0.857728610f, -0.514102744f, + -0.856938977f, -0.515417878f, + -0.856147328f, -0.516731799f, + -0.855353665f, -0.518044504f, + -0.854557988f, -0.519355990f, + -0.853760301f, -0.520666254f, + -0.852960605f, -0.521975293f, + -0.852158902f, -0.523283103f, + -0.851355193f, -0.524589683f, + -0.850549481f, -0.525895027f, + -0.849741768f, -0.527199135f, + -0.848932055f, -0.528502002f, + -0.848120345f, -0.529803625f, + -0.847306639f, -0.531104001f, + -0.846490939f, -0.532403128f, + -0.845673247f, -0.533701002f, + -0.844853565f, -0.534997620f, + -0.844031895f, -0.536292979f, + -0.843208240f, -0.537587076f, + -0.842382600f, -0.538879909f, + -0.841554977f, -0.540171473f, + -0.840725375f, -0.541461766f, + -0.839893794f, -0.542750785f, + -0.839060237f, -0.544038527f, + -0.838224706f, -0.545324988f, + -0.837387202f, -0.546610167f, + -0.836547727f, -0.547894059f, + -0.835706284f, -0.549176662f, + -0.834862875f, -0.550457973f, + -0.834017501f, -0.551737988f, + -0.833170165f, -0.553016706f, + -0.832320868f, -0.554294121f, + -0.831469612f, -0.555570233f, + -0.830616400f, -0.556845037f, + -0.829761234f, -0.558118531f, + -0.828904115f, -0.559390712f, + -0.828045045f, -0.560661576f, + -0.827184027f, -0.561931121f, + -0.826321063f, -0.563199344f, + -0.825456154f, -0.564466242f, + -0.824589303f, -0.565731811f, + -0.823720511f, -0.566996049f, + -0.822849781f, -0.568258953f, + -0.821977115f, -0.569520519f, + -0.821102515f, -0.570780746f, + -0.820225983f, -0.572039629f, + -0.819347520f, -0.573297167f, + -0.818467130f, -0.574553355f, + -0.817584813f, -0.575808191f, + -0.816700573f, -0.577061673f, + -0.815814411f, -0.578313796f, + -0.814926329f, -0.579564559f, + -0.814036330f, -0.580813958f, + -0.813144415f, -0.582061990f, + -0.812250587f, -0.583308653f, + -0.811354847f, -0.584553943f, + -0.810457198f, -0.585797857f, + -0.809557642f, -0.587040394f, + -0.808656182f, -0.588281548f, + -0.807752818f, -0.589521319f, + -0.806847554f, -0.590759702f, + -0.805940391f, -0.591996695f, + -0.805031331f, -0.593232295f, + -0.804120377f, -0.594466499f, + -0.803207531f, -0.595699304f, + -0.802292796f, -0.596930708f, + -0.801376172f, -0.598160707f, + -0.800457662f, -0.599389298f, + -0.799537269f, -0.600616479f, + -0.798614995f, -0.601842247f, + -0.797690841f, -0.603066599f, + -0.796764810f, -0.604289531f, + -0.795836905f, -0.605511041f, + -0.794907126f, -0.606731127f, + -0.793975478f, -0.607949785f, + -0.793041960f, -0.609167012f, + -0.792106577f, -0.610382806f, + -0.791169330f, -0.611597164f, + -0.790230221f, -0.612810082f, + -0.789289253f, -0.614021559f, + -0.788346428f, -0.615231591f, + -0.787401747f, -0.616440175f, + -0.786455214f, -0.617647308f, + -0.785506830f, -0.618852988f, + -0.784556597f, -0.620057212f, + -0.783604519f, -0.621259977f, + -0.782650596f, -0.622461279f, + -0.781694832f, -0.623661118f, + -0.780737229f, -0.624859488f, + -0.779777788f, -0.626056388f, + -0.778816512f, -0.627251815f, + -0.777853404f, -0.628445767f, + -0.776888466f, -0.629638239f, + -0.775921699f, -0.630829230f, + -0.774953107f, -0.632018736f, + -0.773982691f, -0.633206755f, + -0.773010453f, -0.634393284f, + -0.772036397f, -0.635578320f, + -0.771060524f, -0.636761861f, + -0.770082837f, -0.637943904f, + -0.769103338f, -0.639124445f, + -0.768122029f, -0.640303482f, + -0.767138912f, -0.641481013f, + -0.766153990f, -0.642657034f, + -0.765167266f, -0.643831543f, + -0.764178741f, -0.645004537f, + -0.763188417f, -0.646176013f, + -0.762196298f, -0.647345969f, + -0.761202385f, -0.648514401f, + -0.760206682f, -0.649681307f, + -0.759209189f, -0.650846685f, + -0.758209910f, -0.652010531f, + -0.757208847f, -0.653172843f, + -0.756206001f, -0.654333618f, + -0.755201377f, -0.655492853f, + -0.754194975f, -0.656650546f, + -0.753186799f, -0.657806693f, + -0.752176850f, -0.658961293f, + -0.751165132f, -0.660114342f, + -0.750151646f, -0.661265838f, + -0.749136395f, -0.662415778f, + -0.748119380f, -0.663564159f, + -0.747100606f, -0.664710978f, + -0.746080074f, -0.665856234f, + -0.745057785f, -0.666999922f, + -0.744033744f, -0.668142041f, + -0.743007952f, -0.669282588f, + -0.741980412f, -0.670421560f, + -0.740951125f, -0.671558955f, + -0.739920095f, -0.672694769f, + -0.738887324f, -0.673829000f, + -0.737852815f, -0.674961646f, + -0.736816569f, -0.676092704f, + -0.735778589f, -0.677222170f, + -0.734738878f, -0.678350043f, + -0.733697438f, -0.679476320f, + -0.732654272f, -0.680600998f, + -0.731609381f, -0.681724074f, + -0.730562769f, -0.682845546f, + -0.729514438f, -0.683965412f, + -0.728464390f, -0.685083668f, + -0.727412629f, -0.686200312f, + -0.726359155f, -0.687315341f, + -0.725303972f, -0.688428753f, + -0.724247083f, -0.689540545f, + -0.723188489f, -0.690650714f, + -0.722128194f, -0.691759258f, + -0.721066199f, -0.692866175f, + -0.720002508f, -0.693971461f, + -0.718937122f, -0.695075114f, + -0.717870045f, -0.696177131f, + -0.716801279f, -0.697277511f, + -0.715730825f, -0.698376249f, + -0.714658688f, -0.699473345f, + -0.713584869f, -0.700568794f, + -0.712509371f, -0.701662595f, + -0.711432196f, -0.702754744f, + -0.710353347f, -0.703845241f, + -0.709272826f, -0.704934080f, + -0.708190637f, -0.706021261f, + -0.707106781f, -0.707106781f, + -0.706021261f, -0.708190637f, + -0.704934080f, -0.709272826f, + -0.703845241f, -0.710353347f, + -0.702754744f, -0.711432196f, + -0.701662595f, -0.712509371f, + -0.700568794f, -0.713584869f, + -0.699473345f, -0.714658688f, + -0.698376249f, -0.715730825f, + -0.697277511f, -0.716801279f, + -0.696177131f, -0.717870045f, + -0.695075114f, -0.718937122f, + -0.693971461f, -0.720002508f, + -0.692866175f, -0.721066199f, + -0.691759258f, -0.722128194f, + -0.690650714f, -0.723188489f, + -0.689540545f, -0.724247083f, + -0.688428753f, -0.725303972f, + -0.687315341f, -0.726359155f, + -0.686200312f, -0.727412629f, + -0.685083668f, -0.728464390f, + -0.683965412f, -0.729514438f, + -0.682845546f, -0.730562769f, + -0.681724074f, -0.731609381f, + -0.680600998f, -0.732654272f, + -0.679476320f, -0.733697438f, + -0.678350043f, -0.734738878f, + -0.677222170f, -0.735778589f, + -0.676092704f, -0.736816569f, + -0.674961646f, -0.737852815f, + -0.673829000f, -0.738887324f, + -0.672694769f, -0.739920095f, + -0.671558955f, -0.740951125f, + -0.670421560f, -0.741980412f, + -0.669282588f, -0.743007952f, + -0.668142041f, -0.744033744f, + -0.666999922f, -0.745057785f, + -0.665856234f, -0.746080074f, + -0.664710978f, -0.747100606f, + -0.663564159f, -0.748119380f, + -0.662415778f, -0.749136395f, + -0.661265838f, -0.750151646f, + -0.660114342f, -0.751165132f, + -0.658961293f, -0.752176850f, + -0.657806693f, -0.753186799f, + -0.656650546f, -0.754194975f, + -0.655492853f, -0.755201377f, + -0.654333618f, -0.756206001f, + -0.653172843f, -0.757208847f, + -0.652010531f, -0.758209910f, + -0.650846685f, -0.759209189f, + -0.649681307f, -0.760206682f, + -0.648514401f, -0.761202385f, + -0.647345969f, -0.762196298f, + -0.646176013f, -0.763188417f, + -0.645004537f, -0.764178741f, + -0.643831543f, -0.765167266f, + -0.642657034f, -0.766153990f, + -0.641481013f, -0.767138912f, + -0.640303482f, -0.768122029f, + -0.639124445f, -0.769103338f, + -0.637943904f, -0.770082837f, + -0.636761861f, -0.771060524f, + -0.635578320f, -0.772036397f, + -0.634393284f, -0.773010453f, + -0.633206755f, -0.773982691f, + -0.632018736f, -0.774953107f, + -0.630829230f, -0.775921699f, + -0.629638239f, -0.776888466f, + -0.628445767f, -0.777853404f, + -0.627251815f, -0.778816512f, + -0.626056388f, -0.779777788f, + -0.624859488f, -0.780737229f, + -0.623661118f, -0.781694832f, + -0.622461279f, -0.782650596f, + -0.621259977f, -0.783604519f, + -0.620057212f, -0.784556597f, + -0.618852988f, -0.785506830f, + -0.617647308f, -0.786455214f, + -0.616440175f, -0.787401747f, + -0.615231591f, -0.788346428f, + -0.614021559f, -0.789289253f, + -0.612810082f, -0.790230221f, + -0.611597164f, -0.791169330f, + -0.610382806f, -0.792106577f, + -0.609167012f, -0.793041960f, + -0.607949785f, -0.793975478f, + -0.606731127f, -0.794907126f, + -0.605511041f, -0.795836905f, + -0.604289531f, -0.796764810f, + -0.603066599f, -0.797690841f, + -0.601842247f, -0.798614995f, + -0.600616479f, -0.799537269f, + -0.599389298f, -0.800457662f, + -0.598160707f, -0.801376172f, + -0.596930708f, -0.802292796f, + -0.595699304f, -0.803207531f, + -0.594466499f, -0.804120377f, + -0.593232295f, -0.805031331f, + -0.591996695f, -0.805940391f, + -0.590759702f, -0.806847554f, + -0.589521319f, -0.807752818f, + -0.588281548f, -0.808656182f, + -0.587040394f, -0.809557642f, + -0.585797857f, -0.810457198f, + -0.584553943f, -0.811354847f, + -0.583308653f, -0.812250587f, + -0.582061990f, -0.813144415f, + -0.580813958f, -0.814036330f, + -0.579564559f, -0.814926329f, + -0.578313796f, -0.815814411f, + -0.577061673f, -0.816700573f, + -0.575808191f, -0.817584813f, + -0.574553355f, -0.818467130f, + -0.573297167f, -0.819347520f, + -0.572039629f, -0.820225983f, + -0.570780746f, -0.821102515f, + -0.569520519f, -0.821977115f, + -0.568258953f, -0.822849781f, + -0.566996049f, -0.823720511f, + -0.565731811f, -0.824589303f, + -0.564466242f, -0.825456154f, + -0.563199344f, -0.826321063f, + -0.561931121f, -0.827184027f, + -0.560661576f, -0.828045045f, + -0.559390712f, -0.828904115f, + -0.558118531f, -0.829761234f, + -0.556845037f, -0.830616400f, + -0.555570233f, -0.831469612f, + -0.554294121f, -0.832320868f, + -0.553016706f, -0.833170165f, + -0.551737988f, -0.834017501f, + -0.550457973f, -0.834862875f, + -0.549176662f, -0.835706284f, + -0.547894059f, -0.836547727f, + -0.546610167f, -0.837387202f, + -0.545324988f, -0.838224706f, + -0.544038527f, -0.839060237f, + -0.542750785f, -0.839893794f, + -0.541461766f, -0.840725375f, + -0.540171473f, -0.841554977f, + -0.538879909f, -0.842382600f, + -0.537587076f, -0.843208240f, + -0.536292979f, -0.844031895f, + -0.534997620f, -0.844853565f, + -0.533701002f, -0.845673247f, + -0.532403128f, -0.846490939f, + -0.531104001f, -0.847306639f, + -0.529803625f, -0.848120345f, + -0.528502002f, -0.848932055f, + -0.527199135f, -0.849741768f, + -0.525895027f, -0.850549481f, + -0.524589683f, -0.851355193f, + -0.523283103f, -0.852158902f, + -0.521975293f, -0.852960605f, + -0.520666254f, -0.853760301f, + -0.519355990f, -0.854557988f, + -0.518044504f, -0.855353665f, + -0.516731799f, -0.856147328f, + -0.515417878f, -0.856938977f, + -0.514102744f, -0.857728610f, + -0.512786401f, -0.858516224f, + -0.511468850f, -0.859301818f, + -0.510150097f, -0.860085390f, + -0.508830143f, -0.860866939f, + -0.507508991f, -0.861646461f, + -0.506186645f, -0.862423956f, + -0.504863109f, -0.863199422f, + -0.503538384f, -0.863972856f, + -0.502212474f, -0.864744258f, + -0.500885383f, -0.865513624f, + -0.499557113f, -0.866280954f, + -0.498227667f, -0.867046246f, + -0.496897049f, -0.867809497f, + -0.495565262f, -0.868570706f, + -0.494232309f, -0.869329871f, + -0.492898192f, -0.870086991f, + -0.491562916f, -0.870842063f, + -0.490226483f, -0.871595087f, + -0.488888897f, -0.872346059f, + -0.487550160f, -0.873094978f, + -0.486210276f, -0.873841843f, + -0.484869248f, -0.874586652f, + -0.483527079f, -0.875329403f, + -0.482183772f, -0.876070094f, + -0.480839331f, -0.876808724f, + -0.479493758f, -0.877545290f, + -0.478147056f, -0.878279792f, + -0.476799230f, -0.879012226f, + -0.475450282f, -0.879742593f, + -0.474100215f, -0.880470889f, + -0.472749032f, -0.881197113f, + -0.471396737f, -0.881921264f, + -0.470043332f, -0.882643340f, + -0.468688822f, -0.883363339f, + -0.467333209f, -0.884081259f, + -0.465976496f, -0.884797098f, + -0.464618686f, -0.885510856f, + -0.463259784f, -0.886222530f, + -0.461899791f, -0.886932119f, + -0.460538711f, -0.887639620f, + -0.459176548f, -0.888345033f, + -0.457813304f, -0.889048356f, + -0.456448982f, -0.889749586f, + -0.455083587f, -0.890448723f, + -0.453717121f, -0.891145765f, + -0.452349587f, -0.891840709f, + -0.450980989f, -0.892533555f, + -0.449611330f, -0.893224301f, + -0.448240612f, -0.893912945f, + -0.446868840f, -0.894599486f, + -0.445496017f, -0.895283921f, + -0.444122145f, -0.895966250f, + -0.442747228f, -0.896646470f, + -0.441371269f, -0.897324581f, + -0.439994271f, -0.898000580f, + -0.438616239f, -0.898674466f, + -0.437237174f, -0.899346237f, + -0.435857080f, -0.900015892f, + -0.434475961f, -0.900683429f, + -0.433093819f, -0.901348847f, + -0.431710658f, -0.902012144f, + -0.430326481f, -0.902673318f, + -0.428941292f, -0.903332368f, + -0.427555093f, -0.903989293f, + -0.426167889f, -0.904644091f, + -0.424779681f, -0.905296759f, + -0.423390474f, -0.905947298f, + -0.422000271f, -0.906595705f, + -0.420609074f, -0.907241978f, + -0.419216888f, -0.907886116f, + -0.417823716f, -0.908528119f, + -0.416429560f, -0.909167983f, + -0.415034424f, -0.909805708f, + -0.413638312f, -0.910441292f, + -0.412241227f, -0.911074734f, + -0.410843171f, -0.911706032f, + -0.409444149f, -0.912335185f, + -0.408044163f, -0.912962190f, + -0.406643217f, -0.913587048f, + -0.405241314f, -0.914209756f, + -0.403838458f, -0.914830312f, + -0.402434651f, -0.915448716f, + -0.401029897f, -0.916064966f, + -0.399624200f, -0.916679060f, + -0.398217562f, -0.917290997f, + -0.396809987f, -0.917900776f, + -0.395401479f, -0.918508394f, + -0.393992040f, -0.919113852f, + -0.392581674f, -0.919717146f, + -0.391170384f, -0.920318277f, + -0.389758174f, -0.920917242f, + -0.388345047f, -0.921514039f, + -0.386931006f, -0.922108669f, + -0.385516054f, -0.922701128f, + -0.384100195f, -0.923291417f, + -0.382683432f, -0.923879533f, + -0.381265769f, -0.924465474f, + -0.379847209f, -0.925049241f, + -0.378427755f, -0.925630831f, + -0.377007410f, -0.926210242f, + -0.375586178f, -0.926787474f, + -0.374164063f, -0.927362526f, + -0.372741067f, -0.927935395f, + -0.371317194f, -0.928506080f, + -0.369892447f, -0.929074581f, + -0.368466830f, -0.929640896f, + -0.367040346f, -0.930205023f, + -0.365612998f, -0.930766961f, + -0.364184790f, -0.931326709f, + -0.362755724f, -0.931884266f, + -0.361325806f, -0.932439629f, + -0.359895037f, -0.932992799f, + -0.358463421f, -0.933543773f, + -0.357030961f, -0.934092550f, + -0.355597662f, -0.934639130f, + -0.354163525f, -0.935183510f, + -0.352728556f, -0.935725689f, + -0.351292756f, -0.936265667f, + -0.349856130f, -0.936803442f, + -0.348418680f, -0.937339012f, + -0.346980411f, -0.937872376f, + -0.345541325f, -0.938403534f, + -0.344101426f, -0.938932484f, + -0.342660717f, -0.939459224f, + -0.341219202f, -0.939983753f, + -0.339776884f, -0.940506071f, + -0.338333767f, -0.941026175f, + -0.336889853f, -0.941544065f, + -0.335445147f, -0.942059740f, + -0.333999651f, -0.942573198f, + -0.332553370f, -0.943084437f, + -0.331106306f, -0.943593458f, + -0.329658463f, -0.944100258f, + -0.328209844f, -0.944604837f, + -0.326760452f, -0.945107193f, + -0.325310292f, -0.945607325f, + -0.323859367f, -0.946105232f, + -0.322407679f, -0.946600913f, + -0.320955232f, -0.947094366f, + -0.319502031f, -0.947585591f, + -0.318048077f, -0.948074586f, + -0.316593376f, -0.948561350f, + -0.315137929f, -0.949045882f, + -0.313681740f, -0.949528181f, + -0.312224814f, -0.950008245f, + -0.310767153f, -0.950486074f, + -0.309308760f, -0.950961666f, + -0.307849640f, -0.951435021f, + -0.306389795f, -0.951906137f, + -0.304929230f, -0.952375013f, + -0.303467947f, -0.952841648f, + -0.302005949f, -0.953306040f, + -0.300543241f, -0.953768190f, + -0.299079826f, -0.954228095f, + -0.297615707f, -0.954685755f, + -0.296150888f, -0.955141168f, + -0.294685372f, -0.955594334f, + -0.293219163f, -0.956045251f, + -0.291752263f, -0.956493919f, + -0.290284677f, -0.956940336f, + -0.288816408f, -0.957384501f, + -0.287347460f, -0.957826413f, + -0.285877835f, -0.958266071f, + -0.284407537f, -0.958703475f, + -0.282936570f, -0.959138622f, + -0.281464938f, -0.959571513f, + -0.279992643f, -0.960002146f, + -0.278519689f, -0.960430519f, + -0.277046080f, -0.960856633f, + -0.275571819f, -0.961280486f, + -0.274096910f, -0.961702077f, + -0.272621355f, -0.962121404f, + -0.271145160f, -0.962538468f, + -0.269668326f, -0.962953267f, + -0.268190857f, -0.963365800f, + -0.266712757f, -0.963776066f, + -0.265234030f, -0.964184064f, + -0.263754679f, -0.964589793f, + -0.262274707f, -0.964993253f, + -0.260794118f, -0.965394442f, + -0.259312915f, -0.965793359f, + -0.257831102f, -0.966190003f, + -0.256348682f, -0.966584374f, + -0.254865660f, -0.966976471f, + -0.253382037f, -0.967366292f, + -0.251897818f, -0.967753837f, + -0.250413007f, -0.968139105f, + -0.248927606f, -0.968522094f, + -0.247441619f, -0.968902805f, + -0.245955050f, -0.969281235f, + -0.244467903f, -0.969657385f, + -0.242980180f, -0.970031253f, + -0.241491885f, -0.970402839f, + -0.240003022f, -0.970772141f, + -0.238513595f, -0.971139158f, + -0.237023606f, -0.971503891f, + -0.235533059f, -0.971866337f, + -0.234041959f, -0.972226497f, + -0.232550307f, -0.972584369f, + -0.231058108f, -0.972939952f, + -0.229565366f, -0.973293246f, + -0.228072083f, -0.973644250f, + -0.226578264f, -0.973992962f, + -0.225083911f, -0.974339383f, + -0.223589029f, -0.974683511f, + -0.222093621f, -0.975025345f, + -0.220597690f, -0.975364885f, + -0.219101240f, -0.975702130f, + -0.217604275f, -0.976037079f, + -0.216106797f, -0.976369731f, + -0.214608811f, -0.976700086f, + -0.213110320f, -0.977028143f, + -0.211611327f, -0.977353900f, + -0.210111837f, -0.977677358f, + -0.208611852f, -0.977998515f, + -0.207111376f, -0.978317371f, + -0.205610413f, -0.978633924f, + -0.204108966f, -0.978948175f, + -0.202607039f, -0.979260123f, + -0.201104635f, -0.979569766f, + -0.199601758f, -0.979877104f, + -0.198098411f, -0.980182136f, + -0.196594598f, -0.980484862f, + -0.195090322f, -0.980785280f, + -0.193585587f, -0.981083391f, + -0.192080397f, -0.981379193f, + -0.190574755f, -0.981672686f, + -0.189068664f, -0.981963869f, + -0.187562129f, -0.982252741f, + -0.186055152f, -0.982539302f, + -0.184547737f, -0.982823551f, + -0.183039888f, -0.983105487f, + -0.181531608f, -0.983385110f, + -0.180022901f, -0.983662419f, + -0.178513771f, -0.983937413f, + -0.177004220f, -0.984210092f, + -0.175494253f, -0.984480455f, + -0.173983873f, -0.984748502f, + -0.172473084f, -0.985014231f, + -0.170961889f, -0.985277642f, + -0.169450291f, -0.985538735f, + -0.167938295f, -0.985797509f, + -0.166425904f, -0.986053963f, + -0.164913120f, -0.986308097f, + -0.163399949f, -0.986559910f, + -0.161886394f, -0.986809402f, + -0.160372457f, -0.987056571f, + -0.158858143f, -0.987301418f, + -0.157343456f, -0.987543942f, + -0.155828398f, -0.987784142f, + -0.154312973f, -0.988022017f, + -0.152797185f, -0.988257568f, + -0.151281038f, -0.988490793f, + -0.149764535f, -0.988721692f, + -0.148247679f, -0.988950265f, + -0.146730474f, -0.989176510f, + -0.145212925f, -0.989400428f, + -0.143695033f, -0.989622017f, + -0.142176804f, -0.989841278f, + -0.140658239f, -0.990058210f, + -0.139139344f, -0.990272812f, + -0.137620122f, -0.990485084f, + -0.136100575f, -0.990695025f, + -0.134580709f, -0.990902635f, + -0.133060525f, -0.991107914f, + -0.131540029f, -0.991310860f, + -0.130019223f, -0.991511473f, + -0.128498111f, -0.991709754f, + -0.126976696f, -0.991905700f, + -0.125454983f, -0.992099313f, + -0.123932975f, -0.992290591f, + -0.122410675f, -0.992479535f, + -0.120888087f, -0.992666142f, + -0.119365215f, -0.992850414f, + -0.117842062f, -0.993032350f, + -0.116318631f, -0.993211949f, + -0.114794927f, -0.993389211f, + -0.113270952f, -0.993564136f, + -0.111746711f, -0.993736722f, + -0.110222207f, -0.993906970f, + -0.108697444f, -0.994074879f, + -0.107172425f, -0.994240449f, + -0.105647154f, -0.994403680f, + -0.104121634f, -0.994564571f, + -0.102595869f, -0.994723121f, + -0.101069863f, -0.994879331f, + -0.099543619f, -0.995033199f, + -0.098017140f, -0.995184727f, + -0.096490431f, -0.995333912f, + -0.094963495f, -0.995480755f, + -0.093436336f, -0.995625256f, + -0.091908956f, -0.995767414f, + -0.090381361f, -0.995907229f, + -0.088853553f, -0.996044701f, + -0.087325535f, -0.996179829f, + -0.085797312f, -0.996312612f, + -0.084268888f, -0.996443051f, + -0.082740265f, -0.996571146f, + -0.081211447f, -0.996696895f, + -0.079682438f, -0.996820299f, + -0.078153242f, -0.996941358f, + -0.076623861f, -0.997060070f, + -0.075094301f, -0.997176437f, + -0.073564564f, -0.997290457f, + -0.072034653f, -0.997402130f, + -0.070504573f, -0.997511456f, + -0.068974328f, -0.997618435f, + -0.067443920f, -0.997723067f, + -0.065913353f, -0.997825350f, + -0.064382631f, -0.997925286f, + -0.062851758f, -0.998022874f, + -0.061320736f, -0.998118113f, + -0.059789571f, -0.998211003f, + -0.058258265f, -0.998301545f, + -0.056726821f, -0.998389737f, + -0.055195244f, -0.998475581f, + -0.053663538f, -0.998559074f, + -0.052131705f, -0.998640218f, + -0.050599749f, -0.998719012f, + -0.049067674f, -0.998795456f, + -0.047535484f, -0.998869550f, + -0.046003182f, -0.998941293f, + -0.044470772f, -0.999010686f, + -0.042938257f, -0.999077728f, + -0.041405641f, -0.999142419f, + -0.039872928f, -0.999204759f, + -0.038340120f, -0.999264747f, + -0.036807223f, -0.999322385f, + -0.035274239f, -0.999377670f, + -0.033741172f, -0.999430605f, + -0.032208025f, -0.999481187f, + -0.030674803f, -0.999529418f, + -0.029141509f, -0.999575296f, + -0.027608146f, -0.999618822f, + -0.026074718f, -0.999659997f, + -0.024541229f, -0.999698819f, + -0.023007681f, -0.999735288f, + -0.021474080f, -0.999769405f, + -0.019940429f, -0.999801170f, + -0.018406730f, -0.999830582f, + -0.016872988f, -0.999857641f, + -0.015339206f, -0.999882347f, + -0.013805389f, -0.999904701f, + -0.012271538f, -0.999924702f, + -0.010737659f, -0.999942350f, + -0.009203755f, -0.999957645f, + -0.007669829f, -0.999970586f, + -0.006135885f, -0.999981175f, + -0.004601926f, -0.999989411f, + -0.003067957f, -0.999995294f, + -0.001533980f, -0.999998823f, + -0.000000000f, -1.000000000f, + 0.001533980f, -0.999998823f, + 0.003067957f, -0.999995294f, + 0.004601926f, -0.999989411f, + 0.006135885f, -0.999981175f, + 0.007669829f, -0.999970586f, + 0.009203755f, -0.999957645f, + 0.010737659f, -0.999942350f, + 0.012271538f, -0.999924702f, + 0.013805389f, -0.999904701f, + 0.015339206f, -0.999882347f, + 0.016872988f, -0.999857641f, + 0.018406730f, -0.999830582f, + 0.019940429f, -0.999801170f, + 0.021474080f, -0.999769405f, + 0.023007681f, -0.999735288f, + 0.024541229f, -0.999698819f, + 0.026074718f, -0.999659997f, + 0.027608146f, -0.999618822f, + 0.029141509f, -0.999575296f, + 0.030674803f, -0.999529418f, + 0.032208025f, -0.999481187f, + 0.033741172f, -0.999430605f, + 0.035274239f, -0.999377670f, + 0.036807223f, -0.999322385f, + 0.038340120f, -0.999264747f, + 0.039872928f, -0.999204759f, + 0.041405641f, -0.999142419f, + 0.042938257f, -0.999077728f, + 0.044470772f, -0.999010686f, + 0.046003182f, -0.998941293f, + 0.047535484f, -0.998869550f, + 0.049067674f, -0.998795456f, + 0.050599749f, -0.998719012f, + 0.052131705f, -0.998640218f, + 0.053663538f, -0.998559074f, + 0.055195244f, -0.998475581f, + 0.056726821f, -0.998389737f, + 0.058258265f, -0.998301545f, + 0.059789571f, -0.998211003f, + 0.061320736f, -0.998118113f, + 0.062851758f, -0.998022874f, + 0.064382631f, -0.997925286f, + 0.065913353f, -0.997825350f, + 0.067443920f, -0.997723067f, + 0.068974328f, -0.997618435f, + 0.070504573f, -0.997511456f, + 0.072034653f, -0.997402130f, + 0.073564564f, -0.997290457f, + 0.075094301f, -0.997176437f, + 0.076623861f, -0.997060070f, + 0.078153242f, -0.996941358f, + 0.079682438f, -0.996820299f, + 0.081211447f, -0.996696895f, + 0.082740265f, -0.996571146f, + 0.084268888f, -0.996443051f, + 0.085797312f, -0.996312612f, + 0.087325535f, -0.996179829f, + 0.088853553f, -0.996044701f, + 0.090381361f, -0.995907229f, + 0.091908956f, -0.995767414f, + 0.093436336f, -0.995625256f, + 0.094963495f, -0.995480755f, + 0.096490431f, -0.995333912f, + 0.098017140f, -0.995184727f, + 0.099543619f, -0.995033199f, + 0.101069863f, -0.994879331f, + 0.102595869f, -0.994723121f, + 0.104121634f, -0.994564571f, + 0.105647154f, -0.994403680f, + 0.107172425f, -0.994240449f, + 0.108697444f, -0.994074879f, + 0.110222207f, -0.993906970f, + 0.111746711f, -0.993736722f, + 0.113270952f, -0.993564136f, + 0.114794927f, -0.993389211f, + 0.116318631f, -0.993211949f, + 0.117842062f, -0.993032350f, + 0.119365215f, -0.992850414f, + 0.120888087f, -0.992666142f, + 0.122410675f, -0.992479535f, + 0.123932975f, -0.992290591f, + 0.125454983f, -0.992099313f, + 0.126976696f, -0.991905700f, + 0.128498111f, -0.991709754f, + 0.130019223f, -0.991511473f, + 0.131540029f, -0.991310860f, + 0.133060525f, -0.991107914f, + 0.134580709f, -0.990902635f, + 0.136100575f, -0.990695025f, + 0.137620122f, -0.990485084f, + 0.139139344f, -0.990272812f, + 0.140658239f, -0.990058210f, + 0.142176804f, -0.989841278f, + 0.143695033f, -0.989622017f, + 0.145212925f, -0.989400428f, + 0.146730474f, -0.989176510f, + 0.148247679f, -0.988950265f, + 0.149764535f, -0.988721692f, + 0.151281038f, -0.988490793f, + 0.152797185f, -0.988257568f, + 0.154312973f, -0.988022017f, + 0.155828398f, -0.987784142f, + 0.157343456f, -0.987543942f, + 0.158858143f, -0.987301418f, + 0.160372457f, -0.987056571f, + 0.161886394f, -0.986809402f, + 0.163399949f, -0.986559910f, + 0.164913120f, -0.986308097f, + 0.166425904f, -0.986053963f, + 0.167938295f, -0.985797509f, + 0.169450291f, -0.985538735f, + 0.170961889f, -0.985277642f, + 0.172473084f, -0.985014231f, + 0.173983873f, -0.984748502f, + 0.175494253f, -0.984480455f, + 0.177004220f, -0.984210092f, + 0.178513771f, -0.983937413f, + 0.180022901f, -0.983662419f, + 0.181531608f, -0.983385110f, + 0.183039888f, -0.983105487f, + 0.184547737f, -0.982823551f, + 0.186055152f, -0.982539302f, + 0.187562129f, -0.982252741f, + 0.189068664f, -0.981963869f, + 0.190574755f, -0.981672686f, + 0.192080397f, -0.981379193f, + 0.193585587f, -0.981083391f, + 0.195090322f, -0.980785280f, + 0.196594598f, -0.980484862f, + 0.198098411f, -0.980182136f, + 0.199601758f, -0.979877104f, + 0.201104635f, -0.979569766f, + 0.202607039f, -0.979260123f, + 0.204108966f, -0.978948175f, + 0.205610413f, -0.978633924f, + 0.207111376f, -0.978317371f, + 0.208611852f, -0.977998515f, + 0.210111837f, -0.977677358f, + 0.211611327f, -0.977353900f, + 0.213110320f, -0.977028143f, + 0.214608811f, -0.976700086f, + 0.216106797f, -0.976369731f, + 0.217604275f, -0.976037079f, + 0.219101240f, -0.975702130f, + 0.220597690f, -0.975364885f, + 0.222093621f, -0.975025345f, + 0.223589029f, -0.974683511f, + 0.225083911f, -0.974339383f, + 0.226578264f, -0.973992962f, + 0.228072083f, -0.973644250f, + 0.229565366f, -0.973293246f, + 0.231058108f, -0.972939952f, + 0.232550307f, -0.972584369f, + 0.234041959f, -0.972226497f, + 0.235533059f, -0.971866337f, + 0.237023606f, -0.971503891f, + 0.238513595f, -0.971139158f, + 0.240003022f, -0.970772141f, + 0.241491885f, -0.970402839f, + 0.242980180f, -0.970031253f, + 0.244467903f, -0.969657385f, + 0.245955050f, -0.969281235f, + 0.247441619f, -0.968902805f, + 0.248927606f, -0.968522094f, + 0.250413007f, -0.968139105f, + 0.251897818f, -0.967753837f, + 0.253382037f, -0.967366292f, + 0.254865660f, -0.966976471f, + 0.256348682f, -0.966584374f, + 0.257831102f, -0.966190003f, + 0.259312915f, -0.965793359f, + 0.260794118f, -0.965394442f, + 0.262274707f, -0.964993253f, + 0.263754679f, -0.964589793f, + 0.265234030f, -0.964184064f, + 0.266712757f, -0.963776066f, + 0.268190857f, -0.963365800f, + 0.269668326f, -0.962953267f, + 0.271145160f, -0.962538468f, + 0.272621355f, -0.962121404f, + 0.274096910f, -0.961702077f, + 0.275571819f, -0.961280486f, + 0.277046080f, -0.960856633f, + 0.278519689f, -0.960430519f, + 0.279992643f, -0.960002146f, + 0.281464938f, -0.959571513f, + 0.282936570f, -0.959138622f, + 0.284407537f, -0.958703475f, + 0.285877835f, -0.958266071f, + 0.287347460f, -0.957826413f, + 0.288816408f, -0.957384501f, + 0.290284677f, -0.956940336f, + 0.291752263f, -0.956493919f, + 0.293219163f, -0.956045251f, + 0.294685372f, -0.955594334f, + 0.296150888f, -0.955141168f, + 0.297615707f, -0.954685755f, + 0.299079826f, -0.954228095f, + 0.300543241f, -0.953768190f, + 0.302005949f, -0.953306040f, + 0.303467947f, -0.952841648f, + 0.304929230f, -0.952375013f, + 0.306389795f, -0.951906137f, + 0.307849640f, -0.951435021f, + 0.309308760f, -0.950961666f, + 0.310767153f, -0.950486074f, + 0.312224814f, -0.950008245f, + 0.313681740f, -0.949528181f, + 0.315137929f, -0.949045882f, + 0.316593376f, -0.948561350f, + 0.318048077f, -0.948074586f, + 0.319502031f, -0.947585591f, + 0.320955232f, -0.947094366f, + 0.322407679f, -0.946600913f, + 0.323859367f, -0.946105232f, + 0.325310292f, -0.945607325f, + 0.326760452f, -0.945107193f, + 0.328209844f, -0.944604837f, + 0.329658463f, -0.944100258f, + 0.331106306f, -0.943593458f, + 0.332553370f, -0.943084437f, + 0.333999651f, -0.942573198f, + 0.335445147f, -0.942059740f, + 0.336889853f, -0.941544065f, + 0.338333767f, -0.941026175f, + 0.339776884f, -0.940506071f, + 0.341219202f, -0.939983753f, + 0.342660717f, -0.939459224f, + 0.344101426f, -0.938932484f, + 0.345541325f, -0.938403534f, + 0.346980411f, -0.937872376f, + 0.348418680f, -0.937339012f, + 0.349856130f, -0.936803442f, + 0.351292756f, -0.936265667f, + 0.352728556f, -0.935725689f, + 0.354163525f, -0.935183510f, + 0.355597662f, -0.934639130f, + 0.357030961f, -0.934092550f, + 0.358463421f, -0.933543773f, + 0.359895037f, -0.932992799f, + 0.361325806f, -0.932439629f, + 0.362755724f, -0.931884266f, + 0.364184790f, -0.931326709f, + 0.365612998f, -0.930766961f, + 0.367040346f, -0.930205023f, + 0.368466830f, -0.929640896f, + 0.369892447f, -0.929074581f, + 0.371317194f, -0.928506080f, + 0.372741067f, -0.927935395f, + 0.374164063f, -0.927362526f, + 0.375586178f, -0.926787474f, + 0.377007410f, -0.926210242f, + 0.378427755f, -0.925630831f, + 0.379847209f, -0.925049241f, + 0.381265769f, -0.924465474f, + 0.382683432f, -0.923879533f, + 0.384100195f, -0.923291417f, + 0.385516054f, -0.922701128f, + 0.386931006f, -0.922108669f, + 0.388345047f, -0.921514039f, + 0.389758174f, -0.920917242f, + 0.391170384f, -0.920318277f, + 0.392581674f, -0.919717146f, + 0.393992040f, -0.919113852f, + 0.395401479f, -0.918508394f, + 0.396809987f, -0.917900776f, + 0.398217562f, -0.917290997f, + 0.399624200f, -0.916679060f, + 0.401029897f, -0.916064966f, + 0.402434651f, -0.915448716f, + 0.403838458f, -0.914830312f, + 0.405241314f, -0.914209756f, + 0.406643217f, -0.913587048f, + 0.408044163f, -0.912962190f, + 0.409444149f, -0.912335185f, + 0.410843171f, -0.911706032f, + 0.412241227f, -0.911074734f, + 0.413638312f, -0.910441292f, + 0.415034424f, -0.909805708f, + 0.416429560f, -0.909167983f, + 0.417823716f, -0.908528119f, + 0.419216888f, -0.907886116f, + 0.420609074f, -0.907241978f, + 0.422000271f, -0.906595705f, + 0.423390474f, -0.905947298f, + 0.424779681f, -0.905296759f, + 0.426167889f, -0.904644091f, + 0.427555093f, -0.903989293f, + 0.428941292f, -0.903332368f, + 0.430326481f, -0.902673318f, + 0.431710658f, -0.902012144f, + 0.433093819f, -0.901348847f, + 0.434475961f, -0.900683429f, + 0.435857080f, -0.900015892f, + 0.437237174f, -0.899346237f, + 0.438616239f, -0.898674466f, + 0.439994271f, -0.898000580f, + 0.441371269f, -0.897324581f, + 0.442747228f, -0.896646470f, + 0.444122145f, -0.895966250f, + 0.445496017f, -0.895283921f, + 0.446868840f, -0.894599486f, + 0.448240612f, -0.893912945f, + 0.449611330f, -0.893224301f, + 0.450980989f, -0.892533555f, + 0.452349587f, -0.891840709f, + 0.453717121f, -0.891145765f, + 0.455083587f, -0.890448723f, + 0.456448982f, -0.889749586f, + 0.457813304f, -0.889048356f, + 0.459176548f, -0.888345033f, + 0.460538711f, -0.887639620f, + 0.461899791f, -0.886932119f, + 0.463259784f, -0.886222530f, + 0.464618686f, -0.885510856f, + 0.465976496f, -0.884797098f, + 0.467333209f, -0.884081259f, + 0.468688822f, -0.883363339f, + 0.470043332f, -0.882643340f, + 0.471396737f, -0.881921264f, + 0.472749032f, -0.881197113f, + 0.474100215f, -0.880470889f, + 0.475450282f, -0.879742593f, + 0.476799230f, -0.879012226f, + 0.478147056f, -0.878279792f, + 0.479493758f, -0.877545290f, + 0.480839331f, -0.876808724f, + 0.482183772f, -0.876070094f, + 0.483527079f, -0.875329403f, + 0.484869248f, -0.874586652f, + 0.486210276f, -0.873841843f, + 0.487550160f, -0.873094978f, + 0.488888897f, -0.872346059f, + 0.490226483f, -0.871595087f, + 0.491562916f, -0.870842063f, + 0.492898192f, -0.870086991f, + 0.494232309f, -0.869329871f, + 0.495565262f, -0.868570706f, + 0.496897049f, -0.867809497f, + 0.498227667f, -0.867046246f, + 0.499557113f, -0.866280954f, + 0.500885383f, -0.865513624f, + 0.502212474f, -0.864744258f, + 0.503538384f, -0.863972856f, + 0.504863109f, -0.863199422f, + 0.506186645f, -0.862423956f, + 0.507508991f, -0.861646461f, + 0.508830143f, -0.860866939f, + 0.510150097f, -0.860085390f, + 0.511468850f, -0.859301818f, + 0.512786401f, -0.858516224f, + 0.514102744f, -0.857728610f, + 0.515417878f, -0.856938977f, + 0.516731799f, -0.856147328f, + 0.518044504f, -0.855353665f, + 0.519355990f, -0.854557988f, + 0.520666254f, -0.853760301f, + 0.521975293f, -0.852960605f, + 0.523283103f, -0.852158902f, + 0.524589683f, -0.851355193f, + 0.525895027f, -0.850549481f, + 0.527199135f, -0.849741768f, + 0.528502002f, -0.848932055f, + 0.529803625f, -0.848120345f, + 0.531104001f, -0.847306639f, + 0.532403128f, -0.846490939f, + 0.533701002f, -0.845673247f, + 0.534997620f, -0.844853565f, + 0.536292979f, -0.844031895f, + 0.537587076f, -0.843208240f, + 0.538879909f, -0.842382600f, + 0.540171473f, -0.841554977f, + 0.541461766f, -0.840725375f, + 0.542750785f, -0.839893794f, + 0.544038527f, -0.839060237f, + 0.545324988f, -0.838224706f, + 0.546610167f, -0.837387202f, + 0.547894059f, -0.836547727f, + 0.549176662f, -0.835706284f, + 0.550457973f, -0.834862875f, + 0.551737988f, -0.834017501f, + 0.553016706f, -0.833170165f, + 0.554294121f, -0.832320868f, + 0.555570233f, -0.831469612f, + 0.556845037f, -0.830616400f, + 0.558118531f, -0.829761234f, + 0.559390712f, -0.828904115f, + 0.560661576f, -0.828045045f, + 0.561931121f, -0.827184027f, + 0.563199344f, -0.826321063f, + 0.564466242f, -0.825456154f, + 0.565731811f, -0.824589303f, + 0.566996049f, -0.823720511f, + 0.568258953f, -0.822849781f, + 0.569520519f, -0.821977115f, + 0.570780746f, -0.821102515f, + 0.572039629f, -0.820225983f, + 0.573297167f, -0.819347520f, + 0.574553355f, -0.818467130f, + 0.575808191f, -0.817584813f, + 0.577061673f, -0.816700573f, + 0.578313796f, -0.815814411f, + 0.579564559f, -0.814926329f, + 0.580813958f, -0.814036330f, + 0.582061990f, -0.813144415f, + 0.583308653f, -0.812250587f, + 0.584553943f, -0.811354847f, + 0.585797857f, -0.810457198f, + 0.587040394f, -0.809557642f, + 0.588281548f, -0.808656182f, + 0.589521319f, -0.807752818f, + 0.590759702f, -0.806847554f, + 0.591996695f, -0.805940391f, + 0.593232295f, -0.805031331f, + 0.594466499f, -0.804120377f, + 0.595699304f, -0.803207531f, + 0.596930708f, -0.802292796f, + 0.598160707f, -0.801376172f, + 0.599389298f, -0.800457662f, + 0.600616479f, -0.799537269f, + 0.601842247f, -0.798614995f, + 0.603066599f, -0.797690841f, + 0.604289531f, -0.796764810f, + 0.605511041f, -0.795836905f, + 0.606731127f, -0.794907126f, + 0.607949785f, -0.793975478f, + 0.609167012f, -0.793041960f, + 0.610382806f, -0.792106577f, + 0.611597164f, -0.791169330f, + 0.612810082f, -0.790230221f, + 0.614021559f, -0.789289253f, + 0.615231591f, -0.788346428f, + 0.616440175f, -0.787401747f, + 0.617647308f, -0.786455214f, + 0.618852988f, -0.785506830f, + 0.620057212f, -0.784556597f, + 0.621259977f, -0.783604519f, + 0.622461279f, -0.782650596f, + 0.623661118f, -0.781694832f, + 0.624859488f, -0.780737229f, + 0.626056388f, -0.779777788f, + 0.627251815f, -0.778816512f, + 0.628445767f, -0.777853404f, + 0.629638239f, -0.776888466f, + 0.630829230f, -0.775921699f, + 0.632018736f, -0.774953107f, + 0.633206755f, -0.773982691f, + 0.634393284f, -0.773010453f, + 0.635578320f, -0.772036397f, + 0.636761861f, -0.771060524f, + 0.637943904f, -0.770082837f, + 0.639124445f, -0.769103338f, + 0.640303482f, -0.768122029f, + 0.641481013f, -0.767138912f, + 0.642657034f, -0.766153990f, + 0.643831543f, -0.765167266f, + 0.645004537f, -0.764178741f, + 0.646176013f, -0.763188417f, + 0.647345969f, -0.762196298f, + 0.648514401f, -0.761202385f, + 0.649681307f, -0.760206682f, + 0.650846685f, -0.759209189f, + 0.652010531f, -0.758209910f, + 0.653172843f, -0.757208847f, + 0.654333618f, -0.756206001f, + 0.655492853f, -0.755201377f, + 0.656650546f, -0.754194975f, + 0.657806693f, -0.753186799f, + 0.658961293f, -0.752176850f, + 0.660114342f, -0.751165132f, + 0.661265838f, -0.750151646f, + 0.662415778f, -0.749136395f, + 0.663564159f, -0.748119380f, + 0.664710978f, -0.747100606f, + 0.665856234f, -0.746080074f, + 0.666999922f, -0.745057785f, + 0.668142041f, -0.744033744f, + 0.669282588f, -0.743007952f, + 0.670421560f, -0.741980412f, + 0.671558955f, -0.740951125f, + 0.672694769f, -0.739920095f, + 0.673829000f, -0.738887324f, + 0.674961646f, -0.737852815f, + 0.676092704f, -0.736816569f, + 0.677222170f, -0.735778589f, + 0.678350043f, -0.734738878f, + 0.679476320f, -0.733697438f, + 0.680600998f, -0.732654272f, + 0.681724074f, -0.731609381f, + 0.682845546f, -0.730562769f, + 0.683965412f, -0.729514438f, + 0.685083668f, -0.728464390f, + 0.686200312f, -0.727412629f, + 0.687315341f, -0.726359155f, + 0.688428753f, -0.725303972f, + 0.689540545f, -0.724247083f, + 0.690650714f, -0.723188489f, + 0.691759258f, -0.722128194f, + 0.692866175f, -0.721066199f, + 0.693971461f, -0.720002508f, + 0.695075114f, -0.718937122f, + 0.696177131f, -0.717870045f, + 0.697277511f, -0.716801279f, + 0.698376249f, -0.715730825f, + 0.699473345f, -0.714658688f, + 0.700568794f, -0.713584869f, + 0.701662595f, -0.712509371f, + 0.702754744f, -0.711432196f, + 0.703845241f, -0.710353347f, + 0.704934080f, -0.709272826f, + 0.706021261f, -0.708190637f, + 0.707106781f, -0.707106781f, + 0.708190637f, -0.706021261f, + 0.709272826f, -0.704934080f, + 0.710353347f, -0.703845241f, + 0.711432196f, -0.702754744f, + 0.712509371f, -0.701662595f, + 0.713584869f, -0.700568794f, + 0.714658688f, -0.699473345f, + 0.715730825f, -0.698376249f, + 0.716801279f, -0.697277511f, + 0.717870045f, -0.696177131f, + 0.718937122f, -0.695075114f, + 0.720002508f, -0.693971461f, + 0.721066199f, -0.692866175f, + 0.722128194f, -0.691759258f, + 0.723188489f, -0.690650714f, + 0.724247083f, -0.689540545f, + 0.725303972f, -0.688428753f, + 0.726359155f, -0.687315341f, + 0.727412629f, -0.686200312f, + 0.728464390f, -0.685083668f, + 0.729514438f, -0.683965412f, + 0.730562769f, -0.682845546f, + 0.731609381f, -0.681724074f, + 0.732654272f, -0.680600998f, + 0.733697438f, -0.679476320f, + 0.734738878f, -0.678350043f, + 0.735778589f, -0.677222170f, + 0.736816569f, -0.676092704f, + 0.737852815f, -0.674961646f, + 0.738887324f, -0.673829000f, + 0.739920095f, -0.672694769f, + 0.740951125f, -0.671558955f, + 0.741980412f, -0.670421560f, + 0.743007952f, -0.669282588f, + 0.744033744f, -0.668142041f, + 0.745057785f, -0.666999922f, + 0.746080074f, -0.665856234f, + 0.747100606f, -0.664710978f, + 0.748119380f, -0.663564159f, + 0.749136395f, -0.662415778f, + 0.750151646f, -0.661265838f, + 0.751165132f, -0.660114342f, + 0.752176850f, -0.658961293f, + 0.753186799f, -0.657806693f, + 0.754194975f, -0.656650546f, + 0.755201377f, -0.655492853f, + 0.756206001f, -0.654333618f, + 0.757208847f, -0.653172843f, + 0.758209910f, -0.652010531f, + 0.759209189f, -0.650846685f, + 0.760206682f, -0.649681307f, + 0.761202385f, -0.648514401f, + 0.762196298f, -0.647345969f, + 0.763188417f, -0.646176013f, + 0.764178741f, -0.645004537f, + 0.765167266f, -0.643831543f, + 0.766153990f, -0.642657034f, + 0.767138912f, -0.641481013f, + 0.768122029f, -0.640303482f, + 0.769103338f, -0.639124445f, + 0.770082837f, -0.637943904f, + 0.771060524f, -0.636761861f, + 0.772036397f, -0.635578320f, + 0.773010453f, -0.634393284f, + 0.773982691f, -0.633206755f, + 0.774953107f, -0.632018736f, + 0.775921699f, -0.630829230f, + 0.776888466f, -0.629638239f, + 0.777853404f, -0.628445767f, + 0.778816512f, -0.627251815f, + 0.779777788f, -0.626056388f, + 0.780737229f, -0.624859488f, + 0.781694832f, -0.623661118f, + 0.782650596f, -0.622461279f, + 0.783604519f, -0.621259977f, + 0.784556597f, -0.620057212f, + 0.785506830f, -0.618852988f, + 0.786455214f, -0.617647308f, + 0.787401747f, -0.616440175f, + 0.788346428f, -0.615231591f, + 0.789289253f, -0.614021559f, + 0.790230221f, -0.612810082f, + 0.791169330f, -0.611597164f, + 0.792106577f, -0.610382806f, + 0.793041960f, -0.609167012f, + 0.793975478f, -0.607949785f, + 0.794907126f, -0.606731127f, + 0.795836905f, -0.605511041f, + 0.796764810f, -0.604289531f, + 0.797690841f, -0.603066599f, + 0.798614995f, -0.601842247f, + 0.799537269f, -0.600616479f, + 0.800457662f, -0.599389298f, + 0.801376172f, -0.598160707f, + 0.802292796f, -0.596930708f, + 0.803207531f, -0.595699304f, + 0.804120377f, -0.594466499f, + 0.805031331f, -0.593232295f, + 0.805940391f, -0.591996695f, + 0.806847554f, -0.590759702f, + 0.807752818f, -0.589521319f, + 0.808656182f, -0.588281548f, + 0.809557642f, -0.587040394f, + 0.810457198f, -0.585797857f, + 0.811354847f, -0.584553943f, + 0.812250587f, -0.583308653f, + 0.813144415f, -0.582061990f, + 0.814036330f, -0.580813958f, + 0.814926329f, -0.579564559f, + 0.815814411f, -0.578313796f, + 0.816700573f, -0.577061673f, + 0.817584813f, -0.575808191f, + 0.818467130f, -0.574553355f, + 0.819347520f, -0.573297167f, + 0.820225983f, -0.572039629f, + 0.821102515f, -0.570780746f, + 0.821977115f, -0.569520519f, + 0.822849781f, -0.568258953f, + 0.823720511f, -0.566996049f, + 0.824589303f, -0.565731811f, + 0.825456154f, -0.564466242f, + 0.826321063f, -0.563199344f, + 0.827184027f, -0.561931121f, + 0.828045045f, -0.560661576f, + 0.828904115f, -0.559390712f, + 0.829761234f, -0.558118531f, + 0.830616400f, -0.556845037f, + 0.831469612f, -0.555570233f, + 0.832320868f, -0.554294121f, + 0.833170165f, -0.553016706f, + 0.834017501f, -0.551737988f, + 0.834862875f, -0.550457973f, + 0.835706284f, -0.549176662f, + 0.836547727f, -0.547894059f, + 0.837387202f, -0.546610167f, + 0.838224706f, -0.545324988f, + 0.839060237f, -0.544038527f, + 0.839893794f, -0.542750785f, + 0.840725375f, -0.541461766f, + 0.841554977f, -0.540171473f, + 0.842382600f, -0.538879909f, + 0.843208240f, -0.537587076f, + 0.844031895f, -0.536292979f, + 0.844853565f, -0.534997620f, + 0.845673247f, -0.533701002f, + 0.846490939f, -0.532403128f, + 0.847306639f, -0.531104001f, + 0.848120345f, -0.529803625f, + 0.848932055f, -0.528502002f, + 0.849741768f, -0.527199135f, + 0.850549481f, -0.525895027f, + 0.851355193f, -0.524589683f, + 0.852158902f, -0.523283103f, + 0.852960605f, -0.521975293f, + 0.853760301f, -0.520666254f, + 0.854557988f, -0.519355990f, + 0.855353665f, -0.518044504f, + 0.856147328f, -0.516731799f, + 0.856938977f, -0.515417878f, + 0.857728610f, -0.514102744f, + 0.858516224f, -0.512786401f, + 0.859301818f, -0.511468850f, + 0.860085390f, -0.510150097f, + 0.860866939f, -0.508830143f, + 0.861646461f, -0.507508991f, + 0.862423956f, -0.506186645f, + 0.863199422f, -0.504863109f, + 0.863972856f, -0.503538384f, + 0.864744258f, -0.502212474f, + 0.865513624f, -0.500885383f, + 0.866280954f, -0.499557113f, + 0.867046246f, -0.498227667f, + 0.867809497f, -0.496897049f, + 0.868570706f, -0.495565262f, + 0.869329871f, -0.494232309f, + 0.870086991f, -0.492898192f, + 0.870842063f, -0.491562916f, + 0.871595087f, -0.490226483f, + 0.872346059f, -0.488888897f, + 0.873094978f, -0.487550160f, + 0.873841843f, -0.486210276f, + 0.874586652f, -0.484869248f, + 0.875329403f, -0.483527079f, + 0.876070094f, -0.482183772f, + 0.876808724f, -0.480839331f, + 0.877545290f, -0.479493758f, + 0.878279792f, -0.478147056f, + 0.879012226f, -0.476799230f, + 0.879742593f, -0.475450282f, + 0.880470889f, -0.474100215f, + 0.881197113f, -0.472749032f, + 0.881921264f, -0.471396737f, + 0.882643340f, -0.470043332f, + 0.883363339f, -0.468688822f, + 0.884081259f, -0.467333209f, + 0.884797098f, -0.465976496f, + 0.885510856f, -0.464618686f, + 0.886222530f, -0.463259784f, + 0.886932119f, -0.461899791f, + 0.887639620f, -0.460538711f, + 0.888345033f, -0.459176548f, + 0.889048356f, -0.457813304f, + 0.889749586f, -0.456448982f, + 0.890448723f, -0.455083587f, + 0.891145765f, -0.453717121f, + 0.891840709f, -0.452349587f, + 0.892533555f, -0.450980989f, + 0.893224301f, -0.449611330f, + 0.893912945f, -0.448240612f, + 0.894599486f, -0.446868840f, + 0.895283921f, -0.445496017f, + 0.895966250f, -0.444122145f, + 0.896646470f, -0.442747228f, + 0.897324581f, -0.441371269f, + 0.898000580f, -0.439994271f, + 0.898674466f, -0.438616239f, + 0.899346237f, -0.437237174f, + 0.900015892f, -0.435857080f, + 0.900683429f, -0.434475961f, + 0.901348847f, -0.433093819f, + 0.902012144f, -0.431710658f, + 0.902673318f, -0.430326481f, + 0.903332368f, -0.428941292f, + 0.903989293f, -0.427555093f, + 0.904644091f, -0.426167889f, + 0.905296759f, -0.424779681f, + 0.905947298f, -0.423390474f, + 0.906595705f, -0.422000271f, + 0.907241978f, -0.420609074f, + 0.907886116f, -0.419216888f, + 0.908528119f, -0.417823716f, + 0.909167983f, -0.416429560f, + 0.909805708f, -0.415034424f, + 0.910441292f, -0.413638312f, + 0.911074734f, -0.412241227f, + 0.911706032f, -0.410843171f, + 0.912335185f, -0.409444149f, + 0.912962190f, -0.408044163f, + 0.913587048f, -0.406643217f, + 0.914209756f, -0.405241314f, + 0.914830312f, -0.403838458f, + 0.915448716f, -0.402434651f, + 0.916064966f, -0.401029897f, + 0.916679060f, -0.399624200f, + 0.917290997f, -0.398217562f, + 0.917900776f, -0.396809987f, + 0.918508394f, -0.395401479f, + 0.919113852f, -0.393992040f, + 0.919717146f, -0.392581674f, + 0.920318277f, -0.391170384f, + 0.920917242f, -0.389758174f, + 0.921514039f, -0.388345047f, + 0.922108669f, -0.386931006f, + 0.922701128f, -0.385516054f, + 0.923291417f, -0.384100195f, + 0.923879533f, -0.382683432f, + 0.924465474f, -0.381265769f, + 0.925049241f, -0.379847209f, + 0.925630831f, -0.378427755f, + 0.926210242f, -0.377007410f, + 0.926787474f, -0.375586178f, + 0.927362526f, -0.374164063f, + 0.927935395f, -0.372741067f, + 0.928506080f, -0.371317194f, + 0.929074581f, -0.369892447f, + 0.929640896f, -0.368466830f, + 0.930205023f, -0.367040346f, + 0.930766961f, -0.365612998f, + 0.931326709f, -0.364184790f, + 0.931884266f, -0.362755724f, + 0.932439629f, -0.361325806f, + 0.932992799f, -0.359895037f, + 0.933543773f, -0.358463421f, + 0.934092550f, -0.357030961f, + 0.934639130f, -0.355597662f, + 0.935183510f, -0.354163525f, + 0.935725689f, -0.352728556f, + 0.936265667f, -0.351292756f, + 0.936803442f, -0.349856130f, + 0.937339012f, -0.348418680f, + 0.937872376f, -0.346980411f, + 0.938403534f, -0.345541325f, + 0.938932484f, -0.344101426f, + 0.939459224f, -0.342660717f, + 0.939983753f, -0.341219202f, + 0.940506071f, -0.339776884f, + 0.941026175f, -0.338333767f, + 0.941544065f, -0.336889853f, + 0.942059740f, -0.335445147f, + 0.942573198f, -0.333999651f, + 0.943084437f, -0.332553370f, + 0.943593458f, -0.331106306f, + 0.944100258f, -0.329658463f, + 0.944604837f, -0.328209844f, + 0.945107193f, -0.326760452f, + 0.945607325f, -0.325310292f, + 0.946105232f, -0.323859367f, + 0.946600913f, -0.322407679f, + 0.947094366f, -0.320955232f, + 0.947585591f, -0.319502031f, + 0.948074586f, -0.318048077f, + 0.948561350f, -0.316593376f, + 0.949045882f, -0.315137929f, + 0.949528181f, -0.313681740f, + 0.950008245f, -0.312224814f, + 0.950486074f, -0.310767153f, + 0.950961666f, -0.309308760f, + 0.951435021f, -0.307849640f, + 0.951906137f, -0.306389795f, + 0.952375013f, -0.304929230f, + 0.952841648f, -0.303467947f, + 0.953306040f, -0.302005949f, + 0.953768190f, -0.300543241f, + 0.954228095f, -0.299079826f, + 0.954685755f, -0.297615707f, + 0.955141168f, -0.296150888f, + 0.955594334f, -0.294685372f, + 0.956045251f, -0.293219163f, + 0.956493919f, -0.291752263f, + 0.956940336f, -0.290284677f, + 0.957384501f, -0.288816408f, + 0.957826413f, -0.287347460f, + 0.958266071f, -0.285877835f, + 0.958703475f, -0.284407537f, + 0.959138622f, -0.282936570f, + 0.959571513f, -0.281464938f, + 0.960002146f, -0.279992643f, + 0.960430519f, -0.278519689f, + 0.960856633f, -0.277046080f, + 0.961280486f, -0.275571819f, + 0.961702077f, -0.274096910f, + 0.962121404f, -0.272621355f, + 0.962538468f, -0.271145160f, + 0.962953267f, -0.269668326f, + 0.963365800f, -0.268190857f, + 0.963776066f, -0.266712757f, + 0.964184064f, -0.265234030f, + 0.964589793f, -0.263754679f, + 0.964993253f, -0.262274707f, + 0.965394442f, -0.260794118f, + 0.965793359f, -0.259312915f, + 0.966190003f, -0.257831102f, + 0.966584374f, -0.256348682f, + 0.966976471f, -0.254865660f, + 0.967366292f, -0.253382037f, + 0.967753837f, -0.251897818f, + 0.968139105f, -0.250413007f, + 0.968522094f, -0.248927606f, + 0.968902805f, -0.247441619f, + 0.969281235f, -0.245955050f, + 0.969657385f, -0.244467903f, + 0.970031253f, -0.242980180f, + 0.970402839f, -0.241491885f, + 0.970772141f, -0.240003022f, + 0.971139158f, -0.238513595f, + 0.971503891f, -0.237023606f, + 0.971866337f, -0.235533059f, + 0.972226497f, -0.234041959f, + 0.972584369f, -0.232550307f, + 0.972939952f, -0.231058108f, + 0.973293246f, -0.229565366f, + 0.973644250f, -0.228072083f, + 0.973992962f, -0.226578264f, + 0.974339383f, -0.225083911f, + 0.974683511f, -0.223589029f, + 0.975025345f, -0.222093621f, + 0.975364885f, -0.220597690f, + 0.975702130f, -0.219101240f, + 0.976037079f, -0.217604275f, + 0.976369731f, -0.216106797f, + 0.976700086f, -0.214608811f, + 0.977028143f, -0.213110320f, + 0.977353900f, -0.211611327f, + 0.977677358f, -0.210111837f, + 0.977998515f, -0.208611852f, + 0.978317371f, -0.207111376f, + 0.978633924f, -0.205610413f, + 0.978948175f, -0.204108966f, + 0.979260123f, -0.202607039f, + 0.979569766f, -0.201104635f, + 0.979877104f, -0.199601758f, + 0.980182136f, -0.198098411f, + 0.980484862f, -0.196594598f, + 0.980785280f, -0.195090322f, + 0.981083391f, -0.193585587f, + 0.981379193f, -0.192080397f, + 0.981672686f, -0.190574755f, + 0.981963869f, -0.189068664f, + 0.982252741f, -0.187562129f, + 0.982539302f, -0.186055152f, + 0.982823551f, -0.184547737f, + 0.983105487f, -0.183039888f, + 0.983385110f, -0.181531608f, + 0.983662419f, -0.180022901f, + 0.983937413f, -0.178513771f, + 0.984210092f, -0.177004220f, + 0.984480455f, -0.175494253f, + 0.984748502f, -0.173983873f, + 0.985014231f, -0.172473084f, + 0.985277642f, -0.170961889f, + 0.985538735f, -0.169450291f, + 0.985797509f, -0.167938295f, + 0.986053963f, -0.166425904f, + 0.986308097f, -0.164913120f, + 0.986559910f, -0.163399949f, + 0.986809402f, -0.161886394f, + 0.987056571f, -0.160372457f, + 0.987301418f, -0.158858143f, + 0.987543942f, -0.157343456f, + 0.987784142f, -0.155828398f, + 0.988022017f, -0.154312973f, + 0.988257568f, -0.152797185f, + 0.988490793f, -0.151281038f, + 0.988721692f, -0.149764535f, + 0.988950265f, -0.148247679f, + 0.989176510f, -0.146730474f, + 0.989400428f, -0.145212925f, + 0.989622017f, -0.143695033f, + 0.989841278f, -0.142176804f, + 0.990058210f, -0.140658239f, + 0.990272812f, -0.139139344f, + 0.990485084f, -0.137620122f, + 0.990695025f, -0.136100575f, + 0.990902635f, -0.134580709f, + 0.991107914f, -0.133060525f, + 0.991310860f, -0.131540029f, + 0.991511473f, -0.130019223f, + 0.991709754f, -0.128498111f, + 0.991905700f, -0.126976696f, + 0.992099313f, -0.125454983f, + 0.992290591f, -0.123932975f, + 0.992479535f, -0.122410675f, + 0.992666142f, -0.120888087f, + 0.992850414f, -0.119365215f, + 0.993032350f, -0.117842062f, + 0.993211949f, -0.116318631f, + 0.993389211f, -0.114794927f, + 0.993564136f, -0.113270952f, + 0.993736722f, -0.111746711f, + 0.993906970f, -0.110222207f, + 0.994074879f, -0.108697444f, + 0.994240449f, -0.107172425f, + 0.994403680f, -0.105647154f, + 0.994564571f, -0.104121634f, + 0.994723121f, -0.102595869f, + 0.994879331f, -0.101069863f, + 0.995033199f, -0.099543619f, + 0.995184727f, -0.098017140f, + 0.995333912f, -0.096490431f, + 0.995480755f, -0.094963495f, + 0.995625256f, -0.093436336f, + 0.995767414f, -0.091908956f, + 0.995907229f, -0.090381361f, + 0.996044701f, -0.088853553f, + 0.996179829f, -0.087325535f, + 0.996312612f, -0.085797312f, + 0.996443051f, -0.084268888f, + 0.996571146f, -0.082740265f, + 0.996696895f, -0.081211447f, + 0.996820299f, -0.079682438f, + 0.996941358f, -0.078153242f, + 0.997060070f, -0.076623861f, + 0.997176437f, -0.075094301f, + 0.997290457f, -0.073564564f, + 0.997402130f, -0.072034653f, + 0.997511456f, -0.070504573f, + 0.997618435f, -0.068974328f, + 0.997723067f, -0.067443920f, + 0.997825350f, -0.065913353f, + 0.997925286f, -0.064382631f, + 0.998022874f, -0.062851758f, + 0.998118113f, -0.061320736f, + 0.998211003f, -0.059789571f, + 0.998301545f, -0.058258265f, + 0.998389737f, -0.056726821f, + 0.998475581f, -0.055195244f, + 0.998559074f, -0.053663538f, + 0.998640218f, -0.052131705f, + 0.998719012f, -0.050599749f, + 0.998795456f, -0.049067674f, + 0.998869550f, -0.047535484f, + 0.998941293f, -0.046003182f, + 0.999010686f, -0.044470772f, + 0.999077728f, -0.042938257f, + 0.999142419f, -0.041405641f, + 0.999204759f, -0.039872928f, + 0.999264747f, -0.038340120f, + 0.999322385f, -0.036807223f, + 0.999377670f, -0.035274239f, + 0.999430605f, -0.033741172f, + 0.999481187f, -0.032208025f, + 0.999529418f, -0.030674803f, + 0.999575296f, -0.029141509f, + 0.999618822f, -0.027608146f, + 0.999659997f, -0.026074718f, + 0.999698819f, -0.024541229f, + 0.999735288f, -0.023007681f, + 0.999769405f, -0.021474080f, + 0.999801170f, -0.019940429f, + 0.999830582f, -0.018406730f, + 0.999857641f, -0.016872988f, + 0.999882347f, -0.015339206f, + 0.999904701f, -0.013805389f, + 0.999924702f, -0.012271538f, + 0.999942350f, -0.010737659f, + 0.999957645f, -0.009203755f, + 0.999970586f, -0.007669829f, + 0.999981175f, -0.006135885f, + 0.999989411f, -0.004601926f, + 0.999995294f, -0.003067957f, + 0.999998823f, -0.001533980f +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + +/** + @brief Q31 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
 for(i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_16_q31[24] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_32_q31[48] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, + (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, + (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, + (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, + (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, + (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, + (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, + (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xB8E31319, (q31_t)0x9592675B, + (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xE70747C3, (q31_t)0x8275A0C0 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_64_q31[96] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xF3742CA1, (q31_t)0x809DC970 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i < 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_128_q31[192] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF9B82683, (q31_t)0x80277872 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_256_q31[384] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_512_q31[768] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x539B2AEF, + (q31_t)0x60EC3830, (q31_t)0x5269126E, (q31_t)0x61F1003E, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x4FFB654D, + (q31_t)0x63EF328F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4869E664, + (q31_t)0x698C246C, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x447ACD50, + (q31_t)0x6C242960, (q31_t)0x4325C135, (q31_t)0x6CF934FB, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4073F21D, + (q31_t)0x6E96A99C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x382493B0, + (q31_t)0x7307C3D0, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x33DEF287, + (q31_t)0x7504D345, (q31_t)0x326E54C7, (q31_t)0x75A585CF, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x2F875262, + (q31_t)0x76D94988, (q31_t)0x2E110A62, (q31_t)0x776C4EDB, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x29A3C484, (q31_t)0x7909A92C, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x26A82185, + (q31_t)0x7A05EEAD, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2223A4C5, + (q31_t)0x7B5D039D, (q31_t)0x209F701C, (q31_t)0x7BC5E28F, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1D934FE5, + (q31_t)0x7C894BDD, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x145576B1, + (q31_t)0x7E5FE493, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x0FAB272B, + (q31_t)0x7F0991C3, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0AFB6805, + (q31_t)0x7F872BF3, (q31_t)0x096A9049, (q31_t)0x7FA736B4, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x01921D1F, + (q31_t)0x7FFD885A, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFCDBD541, + (q31_t)0x7FF62182, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF826A461, + (q31_t)0x7FC25596, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEEC60F31, + (q31_t)0x7ED5E5C6, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEA1DEBBB, + (q31_t)0x7E1D93E9, (q31_t)0xE8922621, (q31_t)0x7DD6668E, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE57D5FDA, + (q31_t)0x7D3980EC, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDC597781, + (q31_t)0x7AEF6323, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD7D946D7, + (q31_t)0x798A23B1, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD3670445, + (q31_t)0x77FAB988, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xCD91AB38, (q31_t)0x75A585CF, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCAB26FA9, + (q31_t)0x745F9DD1, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC67322CD, + (q31_t)0x72552C84, (q31_t)0xC50D1148, (q31_t)0x719E2CD2, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC247CD5A, + (q31_t)0x70231099, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBA32CA70, + (q31_t)0x6B4AF278, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB64BEACC, + (q31_t)0x68A69E81, (q31_t)0xB5049368, (q31_t)0x67BD0FBC, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB27E9D3B, + (q31_t)0x65DDFBD3, (q31_t)0xB140175B, (q31_t)0x64E88926, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAD96ED91, (q31_t)0x61F1003E, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAB35F5B5, + (q31_t)0x5FE3B38D, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA7BD22AB, + (q31_t)0x5CB420DF, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA462EEAC, + (q31_t)0x59646497, (q31_t)0xA34BDF20, (q31_t)0x5842DD54, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E0EFFC1, + (q31_t)0x5269126E, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B1776D9, + (q31_t)0x4EBFE8A4, (q31_t)0x9A22042C, (q31_t)0x4D8162C4, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9842F043, + (q31_t)0x4AFB6C97, (q31_t)0x9759617E, (q31_t)0x49B41533, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x94B50D87, (q31_t)0x45CD358F, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9306CB04, + (q31_t)0x4325C135, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x90A0FD4E, + (q31_t)0x3F1749B7, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8E61D32D, + (q31_t)0x3AF2EEB7, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x8BA0622F, (q31_t)0x354D9056, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8A5A7A30, + (q31_t)0x326E54C7, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x8893B124, + (q31_t)0x2E110A62, (q31_t)0x88054677, (q31_t)0x2C98FBBA, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x86F656D3, + (q31_t)0x29A3C484, (q31_t)0x8675DC4E, (q31_t)0x2826B928, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x85109CDC, (q31_t)0x23A6887E, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x843A1D70, + (q31_t)0x209F701C, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x831C314E, + (q31_t)0x1C0B826A, (q31_t)0x82C67F13, (q31_t)0x1A82A025, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82299971, + (q31_t)0x176DD9DE, (q31_t)0x81E26C16, (q31_t)0x15E21444, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + + */ +const q31_t twiddleCoef_1024_q31[1536] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5F5E0DB3, (q31_t)0x556040E2, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E50015D, + (q31_t)0x568A34A9, (q31_t)0x5DC79D7C, (q31_t)0x571DEEF9, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5C290ACC, (q31_t)0x58D40E8C, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B1035CF, + (q31_t)0x59F3DE12, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59646497, + (q31_t)0x5B9D1153, (q31_t)0x58D40E8C, (q31_t)0x5C290ACC, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57B0D256, + (q31_t)0x5D3E5236, (q31_t)0x571DEEF9, (q31_t)0x5DC79D7C, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x556040E2, (q31_t)0x5F5E0DB3, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x5433027D, + (q31_t)0x60686CCE, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x5269126E, + (q31_t)0x61F1003E, (q31_t)0x51CED46E, (q31_t)0x6271FA69, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x5097FC5E, + (q31_t)0x637114CC, (q31_t)0x4FFB654D, (q31_t)0x63EF328F, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4E210617, (q31_t)0x6563BF92, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4CE10034, + (q31_t)0x66573CBB, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4AFB6C97, + (q31_t)0x67BD0FBC, (q31_t)0x4A581C9D, (q31_t)0x683257AA, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x490F57EE, + (q31_t)0x6919E320, (q31_t)0x4869E664, (q31_t)0x698C246C, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x46756827, (q31_t)0x6ADCC964, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x452456BC, + (q31_t)0x6BB812D0, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x4325C135, + (q31_t)0x6CF934FB, (q31_t)0x427A41D0, (q31_t)0x6D6227FA, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4121589A, + (q31_t)0x6E30E349, (q31_t)0x4073F21D, (q31_t)0x6E96A99C, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3E680B2C, (q31_t)0x6FC19385, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D07C1D5, + (q31_t)0x708378FE, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3AF2EEB7, + (q31_t)0x719E2CD2, (q31_t)0x3A402DD1, (q31_t)0x71FA3948, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x38D8FE93, + (q31_t)0x72AF05A6, (q31_t)0x382493B0, (q31_t)0x7307C3D0, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x36041AD9, (q31_t)0x740B53FA, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x3496824F, + (q31_t)0x74B2C883, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x326E54C7, + (q31_t)0x75A585CF, (q31_t)0x31B54A5D, (q31_t)0x75F42C0A, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x3041C760, + (q31_t)0x768E0EA5, (q31_t)0x2F875262, (q31_t)0x76D94988, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2D553AFB, (q31_t)0x77B417DF, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2BDC4E6F, + (q31_t)0x78403328, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x29A3C484, + (q31_t)0x7909A92C, (q31_t)0x28E5714A, (q31_t)0x794A7C11, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27679DF4, + (q31_t)0x79C89F6D, (q31_t)0x26A82185, (q31_t)0x7A05EEAD, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x24677757, (q31_t)0x7AB6CBA3, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x22E541AE, + (q31_t)0x7B26CB4F, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x209F701C, + (q31_t)0x7BC5E28F, (q31_t)0x1FDCDC1A, (q31_t)0x7BF88830, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1E56CA1E, + (q31_t)0x7C5A3D4F, (q31_t)0x1D934FE5, (q31_t)0x7C894BDD, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x1B4732EF, (q31_t)0x7D0F4218, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x19BDCBF2, + (q31_t)0x7D628AC5, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x176DD9DE, + (q31_t)0x7DD6668E, (q31_t)0x16A81305, (q31_t)0x7DFA98A7, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x151BDF85, + (q31_t)0x7E3F57FE, (q31_t)0x145576B1, (q31_t)0x7E5FE493, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x120116D4, (q31_t)0x7EBA3A39, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x1072A047, + (q31_t)0x7EF0585F, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E1BC2E3, + (q31_t)0x7F3857F5, (q31_t)0x0D53DB92, (q31_t)0x7F4DE450, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0BC3AC35, + (q31_t)0x7F754E7F, (q31_t)0x0AFB6805, (q31_t)0x7F872BF3, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x08A2009A, (q31_t)0x7FB563B2, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x0710A344, + (q31_t)0x7FCE0C3E, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x04B6195D, + (q31_t)0x7FE9CBC0, (q31_t)0x03ED26E6, (q31_t)0x7FF09477, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x025B26D7, + (q31_t)0x7FFA72D1, (q31_t)0x01921D1F, (q31_t)0x7FFD885A, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFF36F078, (q31_t)0x7FFF6216, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFDA4D928, + (q31_t)0x7FFA72D1, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFB49E6A2, + (q31_t)0x7FE9CBC0, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF8EF5CBB, + (q31_t)0x7FCE0C3E, (q31_t)0xF826A461, (q31_t)0x7FC25596, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF43C53CA, + (q31_t)0x7F754E7F, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF1E43D1C, + (q31_t)0x7F3857F5, (q31_t)0xF11C789A, (q31_t)0x7F2191B4, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEF8D5FB8, + (q31_t)0x7EF0585F, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xEC71244F, (q31_t)0x7E7F3956, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEAE4207A, + (q31_t)0x7E3F57FE, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE8922621, + (q31_t)0x7DD6668E, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE642340D, + (q31_t)0x7D628AC5, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE330734C, (q31_t)0x7CB72724, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE1A935E1, + (q31_t)0x7C5A3D4F, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDF608FE3, + (q31_t)0x7BC5E28F, (q31_t)0xDE9E4C60, (q31_t)0x7B920B89, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDD1ABE51, + (q31_t)0x7B26CB4F, (q31_t)0xDC597781, (q31_t)0x7AEF6323, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xDA17BA4A, (q31_t)0x7A4210D8, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD898620C, + (q31_t)0x79C89F6D, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD65C3B7B, + (q31_t)0x7909A92C, (q31_t)0xD59E4EFE, (q31_t)0x78C7ABA1, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD423B190, + (q31_t)0x78403328, (q31_t)0xD3670445, (q31_t)0x77FAB988, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xD13397E1, (q31_t)0x77235F2D, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xCFBE389F, + (q31_t)0x768E0EA5, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCD91AB38, + (q31_t)0x75A585CF, (q31_t)0xCCD91D3D, (q31_t)0x7555BD4B, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCB697DB0, + (q31_t)0x74B2C883, (q31_t)0xCAB26FA9, (q31_t)0x745F9DD1, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC89061BA, (q31_t)0x735F6626, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC727016C, + (q31_t)0x72AF05A6, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC50D1148, + (q31_t)0x719E2CD2, (q31_t)0xC45AE1D7, (q31_t)0x71410804, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC2F83E2A, + (q31_t)0x708378FE, (q31_t)0xC247CD5A, (q31_t)0x70231099, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xC03A1368, (q31_t)0x6EFB5F12, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBEDEA765, + (q31_t)0x6E30E349, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBCDA3ECA, + (q31_t)0x6CF934FB, (q31_t)0xBC2F6513, (q31_t)0x6C8F351C, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBADBA943, + (q31_t)0x6BB812D0, (q31_t)0xBA32CA70, (q31_t)0x6B4AF278, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB83C3DD1, (q31_t)0x69FD614A, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB6F0A811, + (q31_t)0x6919E320, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB5049368, + (q31_t)0x67BD0FBC, (q31_t)0xB461FC70, (q31_t)0x6746C7D7, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB31EFFCB, + (q31_t)0x66573CBB, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAF6803A1, + (q31_t)0x637114CC, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xAD96ED91, + (q31_t)0x61F1003E, (q31_t)0xACFD7AE8, (q31_t)0x616F146B, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xABCCFD82, + (q31_t)0x60686CCE, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA975CB56, (q31_t)0x5E50015D, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA84F2DA9, + (q31_t)0x5D3E5236, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA69B9B68, + (q31_t)0x5B9D1153, (q31_t)0xA60C21ED, (q31_t)0x5B1035CF, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA4EFCA31, + (q31_t)0x59F3DE12, (q31_t)0xA462EEAC, (q31_t)0x59646497, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA2C1ADC9, (q31_t)0x57B0D256, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1AFFEA2, + (q31_t)0x568A34A9, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA01C4C72, + (q31_t)0x54CA0A4A, (q31_t)0x9F979331, (q31_t)0x5433027D, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9E90EB94, + (q31_t)0x53028517, (q31_t)0x9E0EFFC1, (q31_t)0x5269126E, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9C8EEB33, (q31_t)0x5097FC5E, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9B93A640, + (q31_t)0x4F5E08E3, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A22042C, + (q31_t)0x4D8162C4, (q31_t)0x99A8C344, (q31_t)0x4CE10034, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x98B93828, + (q31_t)0x4B9E038F, (q31_t)0x9842F043, (q31_t)0x4AFB6C97, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x96E61CDF, (q31_t)0x490F57EE, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x96029EB5, + (q31_t)0x47C3C22E, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x94B50D87, + (q31_t)0x45CD358F, (q31_t)0x9447ED2F, (q31_t)0x452456BC, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x9370CAE4, + (q31_t)0x43D09AEC, (q31_t)0x9306CB04, (q31_t)0x4325C135, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x91CF1CB6, (q31_t)0x4121589A, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x9104A0ED, + (q31_t)0x3FC5EC97, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x8FDCEF66, + (q31_t)0x3DB832A5, (q31_t)0x8F7C8701, (q31_t)0x3D07C1D5, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8EBEF7FB, + (q31_t)0x3BA51E29, (q31_t)0x8E61D32D, (q31_t)0x3AF2EEB7, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8D50FA59, (q31_t)0x38D8FE93, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CA099D9, + (q31_t)0x376F9E46, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BA0622F, + (q31_t)0x354D9056, (q31_t)0x8B4D377C, (q31_t)0x3496824F, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AAA42B4, + (q31_t)0x3326E2C2, (q31_t)0x8A5A7A30, (q31_t)0x326E54C7, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x8971F15A, (q31_t)0x3041C760, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x88DCA0D3, + (q31_t)0x2ECC681E, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x88054677, + (q31_t)0x2C98FBBA, (q31_t)0x87BFCCD7, (q31_t)0x2BDC4E6F, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8738545E, + (q31_t)0x2A61B101, (q31_t)0x86F656D3, (q31_t)0x29A3C484, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x86376092, (q31_t)0x27679DF4, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85BDEF27, + (q31_t)0x25E845B5, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x85109CDC, + (q31_t)0x23A6887E, (q31_t)0x84D934B0, (q31_t)0x22E541AE, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x846DF476, + (q31_t)0x2161B39F, (q31_t)0x843A1D70, (q31_t)0x209F701C, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x8348D8DB, + (q31_t)0x1CCF8CB3, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82C67F13, + (q31_t)0x1A82A025, (q31_t)0x829D753A, (q31_t)0x19BDCBF2, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x824F0208, + (q31_t)0x183366E8, (q31_t)0x82299971, (q31_t)0x176DD9DE, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x81C0A801, (q31_t)0x151BDF85, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x8180C6A9, + (q31_t)0x138EDBB0, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x812A1A39, + (q31_t)0x1139F0CE, (q31_t)0x810FA7A0, (q31_t)0x1072A047, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80DE6E4C, + (q31_t)0x0EE38765, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x808AB180, (q31_t)0x0BC3AC35, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80683143, + (q31_t)0x0A3308BC, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x803DAA69, + (q31_t)0x07D95B9E, (q31_t)0x8031F3C1, (q31_t)0x0710A344, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x801E3894, + (q31_t)0x057F0034, (q31_t)0x80163440, (q31_t)0x04B6195D, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x80058D2E, (q31_t)0x025B26D7, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x80009DE9, + (q31_t)0x00C90F88, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x800277A5, + (q31_t)0xFE6DE2E0, (q31_t)0x80058D2E, (q31_t)0xFDA4D928, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800F6B88, + (q31_t)0xFC12D919, (q31_t)0x80163440, (q31_t)0xFB49E6A2, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFF36F078, (q31_t)0x80009DE9 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_2048_q31[3072] = { + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFD885, + (q31_t)0x006487E3, (q31_t)0x7FFF6216, (q31_t)0x00C90F88, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFD885A, + (q31_t)0x01921D1F, (q31_t)0x7FFC250F, (q31_t)0x01F6A296, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF871A1, + (q31_t)0x02BFA9A4, (q31_t)0x7FF62182, (q31_t)0x03242ABF, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF09477, + (q31_t)0x03ED26E6, (q31_t)0x7FED5790, (q31_t)0x0451A176, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE5F108, + (q31_t)0x051A8E5C, (q31_t)0x7FE1C76B, (q31_t)0x057F0034, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FD8878D, + (q31_t)0x0647D97C, (q31_t)0x7FD37152, (q31_t)0x06AC406F, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FC85853, + (q31_t)0x077501BE, (q31_t)0x7FC25596, (q31_t)0x07D95B9E, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB563B2, + (q31_t)0x08A2009A, (q31_t)0x7FAE7494, (q31_t)0x09064B3A, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7F9FAA15, + (q31_t)0x09CECF89, (q31_t)0x7F97CEBC, (q31_t)0x0A3308BC, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F872BF3, + (q31_t)0x0AFB6805, (q31_t)0x7F7E648B, (q31_t)0x0B5F8D9F, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F6BE9D4, + (q31_t)0x0C27C389, (q31_t)0x7F62368F, (q31_t)0x0C8BD35E, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F4DE450, + (q31_t)0x0D53DB92, (q31_t)0x7F434563, (q31_t)0x0DB7D376, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F2D1C0E, + (q31_t)0x0E7FA99D, (q31_t)0x7F2191B4, (q31_t)0x0EE38765, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0991C3, + (q31_t)0x0FAB272B, (q31_t)0x7EFD1C3C, (q31_t)0x100EE8AD, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE34635, + (q31_t)0x10D64DBC, (q31_t)0x7ED5E5C6, (q31_t)0x1139F0CE, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EBA3A39, + (q31_t)0x120116D4, (q31_t)0x7EABEF2C, (q31_t)0x1264994E, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E8E6EB1, + (q31_t)0x132B7BF9, (q31_t)0x7E7F3956, (q31_t)0x138EDBB0, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E5FE493, + (q31_t)0x145576B1, (q31_t)0x7E4FC53E, (q31_t)0x14B8B17F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E2E9CDF, + (q31_t)0x157F0086, (q31_t)0x7E1D93E9, (q31_t)0x15E21444, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7DFA98A7, + (q31_t)0x16A81305, (q31_t)0x7DE8A670, (q31_t)0x170AFD8D, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DC3D90D, + (q31_t)0x17D0A7BB, (q31_t)0x7DB0FDF7, (q31_t)0x183366E8, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D8A5F3F, + (q31_t)0x18F8B83C, (q31_t)0x7D769BB5, (q31_t)0x195B49E9, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D4E2C7E, + (q31_t)0x1A203E1B, (q31_t)0x7D3980EC, (q31_t)0x1A82A025, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D0F4218, + (q31_t)0x1B4732EF, (q31_t)0x7CF9AEF0, (q31_t)0x1BA96334, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CCDA168, + (q31_t)0x1C6D9053, (q31_t)0x7CB72724, (q31_t)0x1CCF8CB3, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C894BDD, + (q31_t)0x1D934FE5, (q31_t)0x7C71EAF8, (q31_t)0x1DF5163F, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4242F2, + (q31_t)0x1EB86B46, (q31_t)0x7C29FBEE, (q31_t)0x1F19F97B, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7BF88830, + (q31_t)0x1FDCDC1A, (q31_t)0x7BDF5B94, (q31_t)0x203E300D, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BAC1D31, + (q31_t)0x21009C0B, (q31_t)0x7B920B89, (q31_t)0x2161B39F, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B5D039D, + (q31_t)0x2223A4C5, (q31_t)0x7B420D7A, (q31_t)0x22847DDF, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B0B3D2C, + (q31_t)0x2345EFF7, (q31_t)0x7AEF6323, (q31_t)0x23A6887E, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AB6CBA3, + (q31_t)0x24677757, (q31_t)0x7A9A0E4F, (q31_t)0x24C7CD32, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A5FB0D8, + (q31_t)0x2588349D, (q31_t)0x7A4210D8, (q31_t)0x25E845B5, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A05EEAD, + (q31_t)0x26A82185, (q31_t)0x79E76CA6, (q31_t)0x2707EBC6, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79A98715, + (q31_t)0x27C737D2, (q31_t)0x798A23B1, (q31_t)0x2826B928, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x794A7C11, + (q31_t)0x28E5714A, (q31_t)0x792A37FE, (q31_t)0x2944A7A2, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78E8CFB1, + (q31_t)0x2A02C7B8, (q31_t)0x78C7ABA1, (q31_t)0x2A61B101, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x78848413, + (q31_t)0x2B1F34EB, (q31_t)0x786280BF, (q31_t)0x2B7DCF17, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x781D9B64, + (q31_t)0x2C3AB2B9, (q31_t)0x77FAB988, (q31_t)0x2C98FBBA, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77B417DF, + (q31_t)0x2D553AFB, (q31_t)0x7790583D, (q31_t)0x2DB330C7, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x7747FBCE, + (q31_t)0x2E6EC792, (q31_t)0x77235F2D, (q31_t)0x2ECC681E, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76D94988, + (q31_t)0x2F875262, (q31_t)0x76B3D0B3, (q31_t)0x2FE49BA6, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x76680376, + (q31_t)0x309ED555, (q31_t)0x7641AF3C, (q31_t)0x30FBC54D, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x75F42C0A, + (q31_t)0x31B54A5D, (q31_t)0x75CCFD42, (q31_t)0x3211DF03, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x757DC5CA, + (q31_t)0x32CAAB6F, (q31_t)0x7555BD4B, (q31_t)0x3326E2C2, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x7504D345, + (q31_t)0x33DEF287, (q31_t)0x74DBF1EF, (q31_t)0x343ACA87, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x7489571B, + (q31_t)0x34F219A7, (q31_t)0x745F9DD1, (q31_t)0x354D9056, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x740B53FA, + (q31_t)0x36041AD9, (q31_t)0x73E0C3A3, (q31_t)0x365F2E3B, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x738ACC9E, + (q31_t)0x3714F02A, (q31_t)0x735F6626, (q31_t)0x376F9E46, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x7307C3D0, + (q31_t)0x382493B0, (q31_t)0x72DB8828, (q31_t)0x387EDA8E, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x72823C66, + (q31_t)0x3932FF87, (q31_t)0x72552C84, (q31_t)0x398CDD32, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x71FA3948, + (q31_t)0x3A402DD1, (q31_t)0x71CC5626, (q31_t)0x3A99A057, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x716FBD68, + (q31_t)0x3B4C18BA, (q31_t)0x71410804, (q31_t)0x3BA51E29, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70E2CBC6, + (q31_t)0x3C56BA70, (q31_t)0x70B34524, (q31_t)0x3CAF50DA, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x70536771, + (q31_t)0x3D600D2B, (q31_t)0x70231099, (q31_t)0x3DB832A5, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FC19385, + (q31_t)0x3E680B2C, (q31_t)0x6F906D84, (q31_t)0x3EBFBDCC, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F2D532C, + (q31_t)0x3F6EAEB8, (q31_t)0x6EFB5F12, (q31_t)0x3FC5EC97, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6E96A99C, + (q31_t)0x4073F21D, (q31_t)0x6E63E87F, (q31_t)0x40CAB957, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6DFD9A1B, + (q31_t)0x4177CFB0, (q31_t)0x6DCA0D14, (q31_t)0x41CE1E64, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D6227FA, + (q31_t)0x427A41D0, (q31_t)0x6D2DD027, (q31_t)0x42D0161E, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CC45697, + (q31_t)0x437B42E1, (q31_t)0x6C8F351C, (q31_t)0x43D09AEC, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C242960, + (q31_t)0x447ACD50, (q31_t)0x6BEE3F62, (q31_t)0x44CFA73F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B81A3CD, + (q31_t)0x4578DB93, (q31_t)0x6B4AF278, (q31_t)0x45CD358F, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6ADCC964, + (q31_t)0x46756827, (q31_t)0x6AA551E8, (q31_t)0x46C9405C, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A359DB9, + (q31_t)0x47706D93, (q31_t)0x69FD614A, (q31_t)0x47C3C22E, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x698C246C, + (q31_t)0x4869E664, (q31_t)0x69532442, (q31_t)0x48BCB598, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68E06129, + (q31_t)0x4961CD32, (q31_t)0x68A69E81, (q31_t)0x49B41533, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x683257AA, + (q31_t)0x4A581C9D, (q31_t)0x67F7D3C4, (q31_t)0x4AA9DBA1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x67820BB6, + (q31_t)0x4B4CCF4D, (q31_t)0x6746C7D7, (q31_t)0x4B9E038F, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66CF811F, + (q31_t)0x4C3FDFF3, (q31_t)0x66937E90, (q31_t)0x4C9087B1, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x661ABBC5, + (q31_t)0x4D31494B, (q31_t)0x65DDFBD3, (q31_t)0x4D8162C4, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x6563BF92, + (q31_t)0x4E210617, (q31_t)0x6526438E, (q31_t)0x4E708F8F, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64AA907F, + (q31_t)0x4F0F1126, (q31_t)0x646C59BF, (q31_t)0x4F5E08E3, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x63EF328F, + (q31_t)0x4FFB654D, (q31_t)0x63B0426D, (q31_t)0x5049C999, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x6331A9D4, + (q31_t)0x50E5FD6C, (q31_t)0x62F201AC, (q31_t)0x5133CC94, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6271FA69, + (q31_t)0x51CED46E, (q31_t)0x62319B9D, (q31_t)0x521C0CC1, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61B02876, + (q31_t)0x52B5E545, (q31_t)0x616F146B, (q31_t)0x53028517, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x60EC3830, + (q31_t)0x539B2AEF, (q31_t)0x60AA704F, (q31_t)0x53E73097, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x60262DD5, + (q31_t)0x547EA073, (q31_t)0x5FE3B38D, (q31_t)0x54CA0A4A, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F5E0DB3, + (q31_t)0x556040E2, (q31_t)0x5F1AE273, (q31_t)0x55AB0D46, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5E93DC1F, + (q31_t)0x56400757, (q31_t)0x5E50015D, (q31_t)0x568A34A9, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DC79D7C, + (q31_t)0x571DEEF9, (q31_t)0x5D8314B0, (q31_t)0x57677B9D, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5CF95638, + (q31_t)0x57F9F2F7, (q31_t)0x5CB420DF, (q31_t)0x5842DD54, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C290ACC, + (q31_t)0x58D40E8C, (q31_t)0x5BE32A67, (q31_t)0x591C550E, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B56BFBD, + (q31_t)0x59AC3CFD, (q31_t)0x5B1035CF, (q31_t)0x59F3DE12, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5A82799A, + (q31_t)0x5A82799A, (q31_t)0x5A3B47AA, (q31_t)0x5AC973B4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59AC3CFD, + (q31_t)0x5B56BFBD, (q31_t)0x59646497, (q31_t)0x5B9D1153, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58D40E8C, + (q31_t)0x5C290ACC, (q31_t)0x588B913F, (q31_t)0x5C6EB258, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x57F9F2F7, + (q31_t)0x5CF95638, (q31_t)0x57B0D256, (q31_t)0x5D3E5236, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x571DEEF9, + (q31_t)0x5DC79D7C, (q31_t)0x56D42C99, (q31_t)0x5E0BEC6E, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x56400757, + (q31_t)0x5E93DC1F, (q31_t)0x55F5A4D2, (q31_t)0x5ED77C89, + (q31_t)0x55AB0D46, (q31_t)0x5F1AE273, (q31_t)0x556040E2, + (q31_t)0x5F5E0DB3, (q31_t)0x55153FD4, (q31_t)0x5FA0FE1E, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x547EA073, + (q31_t)0x60262DD5, (q31_t)0x5433027D, (q31_t)0x60686CCE, + (q31_t)0x53E73097, (q31_t)0x60AA704F, (q31_t)0x539B2AEF, + (q31_t)0x60EC3830, (q31_t)0x534EF1B5, (q31_t)0x612DC446, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x52B5E545, + (q31_t)0x61B02876, (q31_t)0x5269126E, (q31_t)0x61F1003E, + (q31_t)0x521C0CC1, (q31_t)0x62319B9D, (q31_t)0x51CED46E, + (q31_t)0x6271FA69, (q31_t)0x518169A4, (q31_t)0x62B21C7B, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x50E5FD6C, + (q31_t)0x6331A9D4, (q31_t)0x5097FC5E, (q31_t)0x637114CC, + (q31_t)0x5049C999, (q31_t)0x63B0426D, (q31_t)0x4FFB654D, + (q31_t)0x63EF328F, (q31_t)0x4FACCFAB, (q31_t)0x642DE50D, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4F0F1126, + (q31_t)0x64AA907F, (q31_t)0x4EBFE8A4, (q31_t)0x64E88926, + (q31_t)0x4E708F8F, (q31_t)0x6526438E, (q31_t)0x4E210617, + (q31_t)0x6563BF92, (q31_t)0x4DD14C6E, (q31_t)0x65A0FD0B, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4D31494B, + (q31_t)0x661ABBC5, (q31_t)0x4CE10034, (q31_t)0x66573CBB, + (q31_t)0x4C9087B1, (q31_t)0x66937E90, (q31_t)0x4C3FDFF3, + (q31_t)0x66CF811F, (q31_t)0x4BEF092D, (q31_t)0x670B4443, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4B4CCF4D, + (q31_t)0x67820BB6, (q31_t)0x4AFB6C97, (q31_t)0x67BD0FBC, + (q31_t)0x4AA9DBA1, (q31_t)0x67F7D3C4, (q31_t)0x4A581C9D, + (q31_t)0x683257AA, (q31_t)0x4A062FBD, (q31_t)0x686C9B4B, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x4961CD32, + (q31_t)0x68E06129, (q31_t)0x490F57EE, (q31_t)0x6919E320, + (q31_t)0x48BCB598, (q31_t)0x69532442, (q31_t)0x4869E664, + (q31_t)0x698C246C, (q31_t)0x4816EA85, (q31_t)0x69C4E37A, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x47706D93, + (q31_t)0x6A359DB9, (q31_t)0x471CECE6, (q31_t)0x6A6D98A4, + (q31_t)0x46C9405C, (q31_t)0x6AA551E8, (q31_t)0x46756827, + (q31_t)0x6ADCC964, (q31_t)0x4621647C, (q31_t)0x6B13FEF5, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x4578DB93, + (q31_t)0x6B81A3CD, (q31_t)0x452456BC, (q31_t)0x6BB812D0, + (q31_t)0x44CFA73F, (q31_t)0x6BEE3F62, (q31_t)0x447ACD50, + (q31_t)0x6C242960, (q31_t)0x4425C923, (q31_t)0x6C59D0A9, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x437B42E1, + (q31_t)0x6CC45697, (q31_t)0x4325C135, (q31_t)0x6CF934FB, + (q31_t)0x42D0161E, (q31_t)0x6D2DD027, (q31_t)0x427A41D0, + (q31_t)0x6D6227FA, (q31_t)0x42244480, (q31_t)0x6D963C54, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x4177CFB0, + (q31_t)0x6DFD9A1B, (q31_t)0x4121589A, (q31_t)0x6E30E349, + (q31_t)0x40CAB957, (q31_t)0x6E63E87F, (q31_t)0x4073F21D, + (q31_t)0x6E96A99C, (q31_t)0x401D0320, (q31_t)0x6EC92682, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F6EAEB8, + (q31_t)0x6F2D532C, (q31_t)0x3F1749B7, (q31_t)0x6F5F02B1, + (q31_t)0x3EBFBDCC, (q31_t)0x6F906D84, (q31_t)0x3E680B2C, + (q31_t)0x6FC19385, (q31_t)0x3E10320D, (q31_t)0x6FF27496, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D600D2B, + (q31_t)0x70536771, (q31_t)0x3D07C1D5, (q31_t)0x708378FE, + (q31_t)0x3CAF50DA, (q31_t)0x70B34524, (q31_t)0x3C56BA70, + (q31_t)0x70E2CBC6, (q31_t)0x3BFDFECD, (q31_t)0x71120CC5, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3B4C18BA, + (q31_t)0x716FBD68, (q31_t)0x3AF2EEB7, (q31_t)0x719E2CD2, + (q31_t)0x3A99A057, (q31_t)0x71CC5626, (q31_t)0x3A402DD1, + (q31_t)0x71FA3948, (q31_t)0x39E6975D, (q31_t)0x7227D61C, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x3932FF87, + (q31_t)0x72823C66, (q31_t)0x38D8FE93, (q31_t)0x72AF05A6, + (q31_t)0x387EDA8E, (q31_t)0x72DB8828, (q31_t)0x382493B0, + (q31_t)0x7307C3D0, (q31_t)0x37CA2A30, (q31_t)0x7333B883, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x3714F02A, + (q31_t)0x738ACC9E, (q31_t)0x36BA2013, (q31_t)0x73B5EBD0, + (q31_t)0x365F2E3B, (q31_t)0x73E0C3A3, (q31_t)0x36041AD9, + (q31_t)0x740B53FA, (q31_t)0x35A8E624, (q31_t)0x74359CBD, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x34F219A7, + (q31_t)0x7489571B, (q31_t)0x3496824F, (q31_t)0x74B2C883, + (q31_t)0x343ACA87, (q31_t)0x74DBF1EF, (q31_t)0x33DEF287, + (q31_t)0x7504D345, (q31_t)0x3382FA88, (q31_t)0x752D6C6C, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x32CAAB6F, + (q31_t)0x757DC5CA, (q31_t)0x326E54C7, (q31_t)0x75A585CF, + (q31_t)0x3211DF03, (q31_t)0x75CCFD42, (q31_t)0x31B54A5D, + (q31_t)0x75F42C0A, (q31_t)0x3158970D, (q31_t)0x761B1211, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x309ED555, + (q31_t)0x76680376, (q31_t)0x3041C760, (q31_t)0x768E0EA5, + (q31_t)0x2FE49BA6, (q31_t)0x76B3D0B3, (q31_t)0x2F875262, + (q31_t)0x76D94988, (q31_t)0x2F29EBCC, (q31_t)0x76FE790E, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E6EC792, + (q31_t)0x7747FBCE, (q31_t)0x2E110A62, (q31_t)0x776C4EDB, + (q31_t)0x2DB330C7, (q31_t)0x7790583D, (q31_t)0x2D553AFB, + (q31_t)0x77B417DF, (q31_t)0x2CF72939, (q31_t)0x77D78DAA, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2C3AB2B9, + (q31_t)0x781D9B64, (q31_t)0x2BDC4E6F, (q31_t)0x78403328, + (q31_t)0x2B7DCF17, (q31_t)0x786280BF, (q31_t)0x2B1F34EB, + (q31_t)0x78848413, (q31_t)0x2AC08025, (q31_t)0x78A63D10, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x2A02C7B8, + (q31_t)0x78E8CFB1, (q31_t)0x29A3C484, (q31_t)0x7909A92C, + (q31_t)0x2944A7A2, (q31_t)0x792A37FE, (q31_t)0x28E5714A, + (q31_t)0x794A7C11, (q31_t)0x288621B9, (q31_t)0x796A7554, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27C737D2, + (q31_t)0x79A98715, (q31_t)0x27679DF4, (q31_t)0x79C89F6D, + (q31_t)0x2707EBC6, (q31_t)0x79E76CA6, (q31_t)0x26A82185, + (q31_t)0x7A05EEAD, (q31_t)0x26483F6C, (q31_t)0x7A24256E, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x2588349D, + (q31_t)0x7A5FB0D8, (q31_t)0x25280C5D, (q31_t)0x7A7D055B, + (q31_t)0x24C7CD32, (q31_t)0x7A9A0E4F, (q31_t)0x24677757, + (q31_t)0x7AB6CBA3, (q31_t)0x24070B07, (q31_t)0x7AD33D45, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x2345EFF7, + (q31_t)0x7B0B3D2C, (q31_t)0x22E541AE, (q31_t)0x7B26CB4F, + (q31_t)0x22847DDF, (q31_t)0x7B420D7A, (q31_t)0x2223A4C5, + (q31_t)0x7B5D039D, (q31_t)0x21C2B69C, (q31_t)0x7B77ADA8, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x21009C0B, + (q31_t)0x7BAC1D31, (q31_t)0x209F701C, (q31_t)0x7BC5E28F, + (q31_t)0x203E300D, (q31_t)0x7BDF5B94, (q31_t)0x1FDCDC1A, + (q31_t)0x7BF88830, (q31_t)0x1F7B7480, (q31_t)0x7C116853, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1EB86B46, + (q31_t)0x7C4242F2, (q31_t)0x1E56CA1E, (q31_t)0x7C5A3D4F, + (q31_t)0x1DF5163F, (q31_t)0x7C71EAF8, (q31_t)0x1D934FE5, + (q31_t)0x7C894BDD, (q31_t)0x1D31774D, (q31_t)0x7CA05FF1, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C6D9053, + (q31_t)0x7CCDA168, (q31_t)0x1C0B826A, (q31_t)0x7CE3CEB1, + (q31_t)0x1BA96334, (q31_t)0x7CF9AEF0, (q31_t)0x1B4732EF, + (q31_t)0x7D0F4218, (q31_t)0x1AE4F1D6, (q31_t)0x7D24881A, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x1A203E1B, + (q31_t)0x7D4E2C7E, (q31_t)0x19BDCBF2, (q31_t)0x7D628AC5, + (q31_t)0x195B49E9, (q31_t)0x7D769BB5, (q31_t)0x18F8B83C, + (q31_t)0x7D8A5F3F, (q31_t)0x18961727, (q31_t)0x7D9DD55A, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x17D0A7BB, + (q31_t)0x7DC3D90D, (q31_t)0x176DD9DE, (q31_t)0x7DD6668E, + (q31_t)0x170AFD8D, (q31_t)0x7DE8A670, (q31_t)0x16A81305, + (q31_t)0x7DFA98A7, (q31_t)0x16451A83, (q31_t)0x7E0C3D29, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x157F0086, + (q31_t)0x7E2E9CDF, (q31_t)0x151BDF85, (q31_t)0x7E3F57FE, + (q31_t)0x14B8B17F, (q31_t)0x7E4FC53E, (q31_t)0x145576B1, + (q31_t)0x7E5FE493, (q31_t)0x13F22F57, (q31_t)0x7E6FB5F3, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x132B7BF9, + (q31_t)0x7E8E6EB1, (q31_t)0x12C8106E, (q31_t)0x7E9D55FC, + (q31_t)0x1264994E, (q31_t)0x7EABEF2C, (q31_t)0x120116D4, + (q31_t)0x7EBA3A39, (q31_t)0x119D8940, (q31_t)0x7EC8371A, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x10D64DBC, + (q31_t)0x7EE34635, (q31_t)0x1072A047, (q31_t)0x7EF0585F, + (q31_t)0x100EE8AD, (q31_t)0x7EFD1C3C, (q31_t)0x0FAB272B, + (q31_t)0x7F0991C3, (q31_t)0x0F475BFE, (q31_t)0x7F15B8EE, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0E7FA99D, + (q31_t)0x7F2D1C0E, (q31_t)0x0E1BC2E3, (q31_t)0x7F3857F5, + (q31_t)0x0DB7D376, (q31_t)0x7F434563, (q31_t)0x0D53DB92, + (q31_t)0x7F4DE450, (q31_t)0x0CEFDB75, (q31_t)0x7F5834B6, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0C27C389, + (q31_t)0x7F6BE9D4, (q31_t)0x0BC3AC35, (q31_t)0x7F754E7F, + (q31_t)0x0B5F8D9F, (q31_t)0x7F7E648B, (q31_t)0x0AFB6805, + (q31_t)0x7F872BF3, (q31_t)0x0A973BA5, (q31_t)0x7F8FA4AF, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x09CECF89, + (q31_t)0x7F9FAA15, (q31_t)0x096A9049, (q31_t)0x7FA736B4, + (q31_t)0x09064B3A, (q31_t)0x7FAE7494, (q31_t)0x08A2009A, + (q31_t)0x7FB563B2, (q31_t)0x083DB0A7, (q31_t)0x7FBC040A, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x077501BE, + (q31_t)0x7FC85853, (q31_t)0x0710A344, (q31_t)0x7FCE0C3E, + (q31_t)0x06AC406F, (q31_t)0x7FD37152, (q31_t)0x0647D97C, + (q31_t)0x7FD8878D, (q31_t)0x05E36EA9, (q31_t)0x7FDD4EEC, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x051A8E5C, + (q31_t)0x7FE5F108, (q31_t)0x04B6195D, (q31_t)0x7FE9CBC0, + (q31_t)0x0451A176, (q31_t)0x7FED5790, (q31_t)0x03ED26E6, + (q31_t)0x7FF09477, (q31_t)0x0388A9E9, (q31_t)0x7FF38273, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x02BFA9A4, + (q31_t)0x7FF871A1, (q31_t)0x025B26D7, (q31_t)0x7FFA72D1, + (q31_t)0x01F6A296, (q31_t)0x7FFC250F, (q31_t)0x01921D1F, + (q31_t)0x7FFD885A, (q31_t)0x012D96B0, (q31_t)0x7FFE9CB2, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x006487E3, + (q31_t)0x7FFFD885, (q31_t)0x00000000, (q31_t)0x7FFFFFFF, + (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF36F078, + (q31_t)0x7FFF6216, (q31_t)0xFED2694F, (q31_t)0x7FFE9CB2, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE095D69, + (q31_t)0x7FFC250F, (q31_t)0xFDA4D928, (q31_t)0x7FFA72D1, + (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFCDBD541, + (q31_t)0x7FF62182, (q31_t)0xFC775616, (q31_t)0x7FF38273, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBAE5E89, + (q31_t)0x7FED5790, (q31_t)0xFB49E6A2, (q31_t)0x7FE9CBC0, + (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFA80FFCB, + (q31_t)0x7FE1C76B, (q31_t)0xFA1C9156, (q31_t)0x7FDD4EEC, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF953BF90, + (q31_t)0x7FD37152, (q31_t)0xF8EF5CBB, (q31_t)0x7FCE0C3E, + (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF826A461, + (q31_t)0x7FC25596, (q31_t)0xF7C24F58, (q31_t)0x7FBC040A, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF6F9B4C5, + (q31_t)0x7FAE7494, (q31_t)0xF6956FB6, (q31_t)0x7FA736B4, + (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5CCF743, + (q31_t)0x7F97CEBC, (q31_t)0xF568C45A, (q31_t)0x7F8FA4AF, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4A07260, + (q31_t)0x7F7E648B, (q31_t)0xF43C53CA, (q31_t)0x7F754E7F, + (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3742CA1, + (q31_t)0x7F62368F, (q31_t)0xF310248A, (q31_t)0x7F5834B6, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF2482C89, + (q31_t)0x7F434563, (q31_t)0xF1E43D1C, (q31_t)0x7F3857F5, + (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF11C789A, + (q31_t)0x7F2191B4, (q31_t)0xF0B8A401, (q31_t)0x7F15B8EE, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xEFF11752, + (q31_t)0x7EFD1C3C, (q31_t)0xEF8D5FB8, (q31_t)0x7EF0585F, + (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEC60F31, + (q31_t)0x7ED5E5C6, (q31_t)0xEE6276BF, (q31_t)0x7EC8371A, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xED9B66B2, + (q31_t)0x7EABEF2C, (q31_t)0xED37EF91, (q31_t)0x7E9D55FC, + (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xEC71244F, + (q31_t)0x7E7F3956, (q31_t)0xEC0DD0A8, (q31_t)0x7E6FB5F3, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB474E80, + (q31_t)0x7E4FC53E, (q31_t)0xEAE4207A, (q31_t)0x7E3F57FE, + (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA1DEBBB, + (q31_t)0x7E1D93E9, (q31_t)0xE9BAE57C, (q31_t)0x7E0C3D29, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE8F50273, + (q31_t)0x7DE8A670, (q31_t)0xE8922621, (q31_t)0x7DD6668E, + (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7CC9917, + (q31_t)0x7DB0FDF7, (q31_t)0xE769E8D8, (q31_t)0x7D9DD55A, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6A4B616, + (q31_t)0x7D769BB5, (q31_t)0xE642340D, (q31_t)0x7D628AC5, + (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE57D5FDA, + (q31_t)0x7D3980EC, (q31_t)0xE51B0E2A, (q31_t)0x7D24881A, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE4569CCB, + (q31_t)0x7CF9AEF0, (q31_t)0xE3F47D95, (q31_t)0x7CE3CEB1, + (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE330734C, + (q31_t)0x7CB72724, (q31_t)0xE2CE88B2, (q31_t)0x7CA05FF1, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE20AE9C1, + (q31_t)0x7C71EAF8, (q31_t)0xE1A935E1, (q31_t)0x7C5A3D4F, + (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE0E60684, + (q31_t)0x7C29FBEE, (q31_t)0xE0848B7F, (q31_t)0x7C116853, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFC1CFF2, + (q31_t)0x7BDF5B94, (q31_t)0xDF608FE3, (q31_t)0x7BC5E28F, + (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDE9E4C60, + (q31_t)0x7B920B89, (q31_t)0xDE3D4963, (q31_t)0x7B77ADA8, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDD7B8220, + (q31_t)0x7B420D7A, (q31_t)0xDD1ABE51, (q31_t)0x7B26CB4F, + (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC597781, + (q31_t)0x7AEF6323, (q31_t)0xDBF8F4F8, (q31_t)0x7AD33D45, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB3832CD, + (q31_t)0x7A9A0E4F, (q31_t)0xDAD7F3A2, (q31_t)0x7A7D055B, + (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA17BA4A, + (q31_t)0x7A4210D8, (q31_t)0xD9B7C093, (q31_t)0x7A24256E, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD8F81439, + (q31_t)0x79E76CA6, (q31_t)0xD898620C, (q31_t)0x79C89F6D, + (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD7D946D7, + (q31_t)0x798A23B1, (q31_t)0xD779DE46, (q31_t)0x796A7554, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6BB585D, + (q31_t)0x792A37FE, (q31_t)0xD65C3B7B, (q31_t)0x7909A92C, + (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD59E4EFE, + (q31_t)0x78C7ABA1, (q31_t)0xD53F7FDA, (q31_t)0x78A63D10, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD48230E8, + (q31_t)0x786280BF, (q31_t)0xD423B190, (q31_t)0x78403328, + (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3670445, + (q31_t)0x77FAB988, (q31_t)0xD308D6C6, (q31_t)0x77D78DAA, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD24CCF38, + (q31_t)0x7790583D, (q31_t)0xD1EEF59E, (q31_t)0x776C4EDB, + (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD13397E1, + (q31_t)0x77235F2D, (q31_t)0xD0D61433, (q31_t)0x76FE790E, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD01B6459, + (q31_t)0x76B3D0B3, (q31_t)0xCFBE389F, (q31_t)0x768E0EA5, + (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF043AB2, + (q31_t)0x7641AF3C, (q31_t)0xCEA768F2, (q31_t)0x761B1211, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCDEE20FC, + (q31_t)0x75CCFD42, (q31_t)0xCD91AB38, (q31_t)0x75A585CF, + (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCCD91D3D, + (q31_t)0x7555BD4B, (q31_t)0xCC7D0577, (q31_t)0x752D6C6C, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBC53578, + (q31_t)0x74DBF1EF, (q31_t)0xCB697DB0, (q31_t)0x74B2C883, + (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAB26FA9, + (q31_t)0x745F9DD1, (q31_t)0xCA5719DB, (q31_t)0x74359CBD, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9A0D1C4, + (q31_t)0x73E0C3A3, (q31_t)0xC945DFEC, (q31_t)0x73B5EBD0, + (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC89061BA, + (q31_t)0x735F6626, (q31_t)0xC835D5D0, (q31_t)0x7333B883, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7812571, + (q31_t)0x72DB8828, (q31_t)0xC727016C, (q31_t)0x72AF05A6, + (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC67322CD, + (q31_t)0x72552C84, (q31_t)0xC61968A2, (q31_t)0x7227D61C, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC5665FA8, + (q31_t)0x71CC5626, (q31_t)0xC50D1148, (q31_t)0x719E2CD2, + (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC45AE1D7, + (q31_t)0x71410804, (q31_t)0xC4020132, (q31_t)0x71120CC5, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC350AF25, + (q31_t)0x70B34524, (q31_t)0xC2F83E2A, (q31_t)0x708378FE, + (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC247CD5A, + (q31_t)0x70231099, (q31_t)0xC1EFCDF2, (q31_t)0x6FF27496, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC1404233, + (q31_t)0x6F906D84, (q31_t)0xC0E8B648, (q31_t)0x6F5F02B1, + (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC03A1368, + (q31_t)0x6EFB5F12, (q31_t)0xBFE2FCDF, (q31_t)0x6EC92682, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF3546A8, + (q31_t)0x6E63E87F, (q31_t)0xBEDEA765, (q31_t)0x6E30E349, + (q31_t)0xBE88304F, (q31_t)0x6DFD9A1B, (q31_t)0xBE31E19B, + (q31_t)0x6DCA0D14, (q31_t)0xBDDBBB7F, (q31_t)0x6D963C54, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBD2FE9E1, + (q31_t)0x6D2DD027, (q31_t)0xBCDA3ECA, (q31_t)0x6CF934FB, + (q31_t)0xBC84BD1E, (q31_t)0x6CC45697, (q31_t)0xBC2F6513, + (q31_t)0x6C8F351C, (q31_t)0xBBDA36DC, (q31_t)0x6C59D0A9, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBB3058C0, + (q31_t)0x6BEE3F62, (q31_t)0xBADBA943, (q31_t)0x6BB812D0, + (q31_t)0xBA87246C, (q31_t)0x6B81A3CD, (q31_t)0xBA32CA70, + (q31_t)0x6B4AF278, (q31_t)0xB9DE9B83, (q31_t)0x6B13FEF5, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB936BFA3, + (q31_t)0x6AA551E8, (q31_t)0xB8E31319, (q31_t)0x6A6D98A4, + (q31_t)0xB88F926C, (q31_t)0x6A359DB9, (q31_t)0xB83C3DD1, + (q31_t)0x69FD614A, (q31_t)0xB7E9157A, (q31_t)0x69C4E37A, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB7434A67, + (q31_t)0x69532442, (q31_t)0xB6F0A811, (q31_t)0x6919E320, + (q31_t)0xB69E32CD, (q31_t)0x68E06129, (q31_t)0xB64BEACC, + (q31_t)0x68A69E81, (q31_t)0xB5F9D042, (q31_t)0x686C9B4B, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB556245E, + (q31_t)0x67F7D3C4, (q31_t)0xB5049368, (q31_t)0x67BD0FBC, + (q31_t)0xB4B330B2, (q31_t)0x67820BB6, (q31_t)0xB461FC70, + (q31_t)0x6746C7D7, (q31_t)0xB410F6D2, (q31_t)0x670B4443, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB36F784E, + (q31_t)0x66937E90, (q31_t)0xB31EFFCB, (q31_t)0x66573CBB, + (q31_t)0xB2CEB6B5, (q31_t)0x661ABBC5, (q31_t)0xB27E9D3B, + (q31_t)0x65DDFBD3, (q31_t)0xB22EB392, (q31_t)0x65A0FD0B, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB18F7070, + (q31_t)0x6526438E, (q31_t)0xB140175B, (q31_t)0x64E88926, + (q31_t)0xB0F0EEDA, (q31_t)0x64AA907F, (q31_t)0xB0A1F71C, + (q31_t)0x646C59BF, (q31_t)0xB0533055, (q31_t)0x642DE50D, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAFB63667, + (q31_t)0x63B0426D, (q31_t)0xAF6803A1, (q31_t)0x637114CC, + (q31_t)0xAF1A0293, (q31_t)0x6331A9D4, (q31_t)0xAECC336B, + (q31_t)0x62F201AC, (q31_t)0xAE7E965B, (q31_t)0x62B21C7B, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xADE3F33E, + (q31_t)0x62319B9D, (q31_t)0xAD96ED91, (q31_t)0x61F1003E, + (q31_t)0xAD4A1ABA, (q31_t)0x61B02876, (q31_t)0xACFD7AE8, + (q31_t)0x616F146B, (q31_t)0xACB10E4A, (q31_t)0x612DC446, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAC18CF68, + (q31_t)0x60AA704F, (q31_t)0xABCCFD82, (q31_t)0x60686CCE, + (q31_t)0xAB815F8C, (q31_t)0x60262DD5, (q31_t)0xAB35F5B5, + (q31_t)0x5FE3B38D, (q31_t)0xAAEAC02B, (q31_t)0x5FA0FE1E, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA54F2B9, + (q31_t)0x5F1AE273, (q31_t)0xAA0A5B2D, (q31_t)0x5ED77C89, + (q31_t)0xA9BFF8A8, (q31_t)0x5E93DC1F, (q31_t)0xA975CB56, + (q31_t)0x5E50015D, (q31_t)0xA92BD366, (q31_t)0x5E0BEC6E, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA8988463, + (q31_t)0x5D8314B0, (q31_t)0xA84F2DA9, (q31_t)0x5D3E5236, + (q31_t)0xA8060D08, (q31_t)0x5CF95638, (q31_t)0xA7BD22AB, + (q31_t)0x5CB420DF, (q31_t)0xA7746EC0, (q31_t)0x5C6EB258, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA6E3AAF2, + (q31_t)0x5BE32A67, (q31_t)0xA69B9B68, (q31_t)0x5B9D1153, + (q31_t)0xA653C302, (q31_t)0x5B56BFBD, (q31_t)0xA60C21ED, + (q31_t)0x5B1035CF, (q31_t)0xA5C4B855, (q31_t)0x5AC973B4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA5368C4B, + (q31_t)0x5A3B47AA, (q31_t)0xA4EFCA31, (q31_t)0x59F3DE12, + (q31_t)0xA4A94042, (q31_t)0x59AC3CFD, (q31_t)0xA462EEAC, + (q31_t)0x59646497, (q31_t)0xA41CD598, (q31_t)0x591C550E, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA3914DA7, + (q31_t)0x588B913F, (q31_t)0xA34BDF20, (q31_t)0x5842DD54, + (q31_t)0xA306A9C7, (q31_t)0x57F9F2F7, (q31_t)0xA2C1ADC9, + (q31_t)0x57B0D256, (q31_t)0xA27CEB4F, (q31_t)0x57677B9D, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA1F41391, + (q31_t)0x56D42C99, (q31_t)0xA1AFFEA2, (q31_t)0x568A34A9, + (q31_t)0xA16C23E1, (q31_t)0x56400757, (q31_t)0xA1288376, + (q31_t)0x55F5A4D2, (q31_t)0xA0E51D8C, (q31_t)0x55AB0D46, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA05F01E1, + (q31_t)0x55153FD4, (q31_t)0xA01C4C72, (q31_t)0x54CA0A4A, + (q31_t)0x9FD9D22A, (q31_t)0x547EA073, (q31_t)0x9F979331, + (q31_t)0x5433027D, (q31_t)0x9F558FB0, (q31_t)0x53E73097, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9ED23BB9, + (q31_t)0x534EF1B5, (q31_t)0x9E90EB94, (q31_t)0x53028517, + (q31_t)0x9E4FD789, (q31_t)0x52B5E545, (q31_t)0x9E0EFFC1, + (q31_t)0x5269126E, (q31_t)0x9DCE6462, (q31_t)0x521C0CC1, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D4DE384, + (q31_t)0x518169A4, (q31_t)0x9D0DFE53, (q31_t)0x5133CC94, + (q31_t)0x9CCE562B, (q31_t)0x50E5FD6C, (q31_t)0x9C8EEB33, + (q31_t)0x5097FC5E, (q31_t)0x9C4FBD92, (q31_t)0x5049C999, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9BD21AF2, + (q31_t)0x4FACCFAB, (q31_t)0x9B93A640, (q31_t)0x4F5E08E3, + (q31_t)0x9B556F80, (q31_t)0x4F0F1126, (q31_t)0x9B1776D9, + (q31_t)0x4EBFE8A4, (q31_t)0x9AD9BC71, (q31_t)0x4E708F8F, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A5F02F5, + (q31_t)0x4DD14C6E, (q31_t)0x9A22042C, (q31_t)0x4D8162C4, + (q31_t)0x99E5443A, (q31_t)0x4D31494B, (q31_t)0x99A8C344, + (q31_t)0x4CE10034, (q31_t)0x996C816F, (q31_t)0x4C9087B1, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x98F4BBBC, + (q31_t)0x4BEF092D, (q31_t)0x98B93828, (q31_t)0x4B9E038F, + (q31_t)0x987DF449, (q31_t)0x4B4CCF4D, (q31_t)0x9842F043, + (q31_t)0x4AFB6C97, (q31_t)0x98082C3B, (q31_t)0x4AA9DBA1, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x979364B5, + (q31_t)0x4A062FBD, (q31_t)0x9759617E, (q31_t)0x49B41533, + (q31_t)0x971F9ED6, (q31_t)0x4961CD32, (q31_t)0x96E61CDF, + (q31_t)0x490F57EE, (q31_t)0x96ACDBBD, (q31_t)0x48BCB598, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x963B1C85, + (q31_t)0x4816EA85, (q31_t)0x96029EB5, (q31_t)0x47C3C22E, + (q31_t)0x95CA6246, (q31_t)0x47706D93, (q31_t)0x9592675B, + (q31_t)0x471CECE6, (q31_t)0x955AAE17, (q31_t)0x46C9405C, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x94EC010B, + (q31_t)0x4621647C, (q31_t)0x94B50D87, (q31_t)0x45CD358F, + (q31_t)0x947E5C32, (q31_t)0x4578DB93, (q31_t)0x9447ED2F, + (q31_t)0x452456BC, (q31_t)0x9411C09D, (q31_t)0x44CFA73F, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x93A62F56, + (q31_t)0x4425C923, (q31_t)0x9370CAE4, (q31_t)0x43D09AEC, + (q31_t)0x933BA968, (q31_t)0x437B42E1, (q31_t)0x9306CB04, + (q31_t)0x4325C135, (q31_t)0x92D22FD8, (q31_t)0x42D0161E, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9269C3AC, + (q31_t)0x42244480, (q31_t)0x9235F2EB, (q31_t)0x41CE1E64, + (q31_t)0x920265E4, (q31_t)0x4177CFB0, (q31_t)0x91CF1CB6, + (q31_t)0x4121589A, (q31_t)0x919C1780, (q31_t)0x40CAB957, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x9136D97D, + (q31_t)0x401D0320, (q31_t)0x9104A0ED, (q31_t)0x3FC5EC97, + (q31_t)0x90D2ACD3, (q31_t)0x3F6EAEB8, (q31_t)0x90A0FD4E, + (q31_t)0x3F1749B7, (q31_t)0x906F927B, (q31_t)0x3EBFBDCC, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x900D8B69, + (q31_t)0x3E10320D, (q31_t)0x8FDCEF66, (q31_t)0x3DB832A5, + (q31_t)0x8FAC988E, (q31_t)0x3D600D2B, (q31_t)0x8F7C8701, + (q31_t)0x3D07C1D5, (q31_t)0x8F4CBADB, (q31_t)0x3CAF50DA, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8EEDF33B, + (q31_t)0x3BFDFECD, (q31_t)0x8EBEF7FB, (q31_t)0x3BA51E29, + (q31_t)0x8E904298, (q31_t)0x3B4C18BA, (q31_t)0x8E61D32D, + (q31_t)0x3AF2EEB7, (q31_t)0x8E33A9D9, (q31_t)0x3A99A057, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DD829E4, + (q31_t)0x39E6975D, (q31_t)0x8DAAD37B, (q31_t)0x398CDD32, + (q31_t)0x8D7DC399, (q31_t)0x3932FF87, (q31_t)0x8D50FA59, + (q31_t)0x38D8FE93, (q31_t)0x8D2477D8, (q31_t)0x387EDA8E, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CCC477D, + (q31_t)0x37CA2A30, (q31_t)0x8CA099D9, (q31_t)0x376F9E46, + (q31_t)0x8C753361, (q31_t)0x3714F02A, (q31_t)0x8C4A142F, + (q31_t)0x36BA2013, (q31_t)0x8C1F3C5C, (q31_t)0x365F2E3B, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BCA6342, + (q31_t)0x35A8E624, (q31_t)0x8BA0622F, (q31_t)0x354D9056, + (q31_t)0x8B76A8E4, (q31_t)0x34F219A7, (q31_t)0x8B4D377C, + (q31_t)0x3496824F, (q31_t)0x8B240E10, (q31_t)0x343ACA87, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AD29393, + (q31_t)0x3382FA88, (q31_t)0x8AAA42B4, (q31_t)0x3326E2C2, + (q31_t)0x8A823A35, (q31_t)0x32CAAB6F, (q31_t)0x8A5A7A30, + (q31_t)0x326E54C7, (q31_t)0x8A3302BD, (q31_t)0x3211DF03, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89E4EDEE, + (q31_t)0x3158970D, (q31_t)0x89BE50C3, (q31_t)0x30FBC54D, + (q31_t)0x8997FC89, (q31_t)0x309ED555, (q31_t)0x8971F15A, + (q31_t)0x3041C760, (q31_t)0x894C2F4C, (q31_t)0x2FE49BA6, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x890186F1, + (q31_t)0x2F29EBCC, (q31_t)0x88DCA0D3, (q31_t)0x2ECC681E, + (q31_t)0x88B80431, (q31_t)0x2E6EC792, (q31_t)0x8893B124, + (q31_t)0x2E110A62, (q31_t)0x886FA7C2, (q31_t)0x2DB330C7, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x88287255, + (q31_t)0x2CF72939, (q31_t)0x88054677, (q31_t)0x2C98FBBA, + (q31_t)0x87E2649B, (q31_t)0x2C3AB2B9, (q31_t)0x87BFCCD7, + (q31_t)0x2BDC4E6F, (q31_t)0x879D7F40, (q31_t)0x2B7DCF17, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x8759C2EF, + (q31_t)0x2AC08025, (q31_t)0x8738545E, (q31_t)0x2A61B101, + (q31_t)0x8717304E, (q31_t)0x2A02C7B8, (q31_t)0x86F656D3, + (q31_t)0x29A3C484, (q31_t)0x86D5C802, (q31_t)0x2944A7A2, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x86958AAB, + (q31_t)0x288621B9, (q31_t)0x8675DC4E, (q31_t)0x2826B928, + (q31_t)0x865678EA, (q31_t)0x27C737D2, (q31_t)0x86376092, + (q31_t)0x27679DF4, (q31_t)0x86189359, (q31_t)0x2707EBC6, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85DBDA91, + (q31_t)0x26483F6C, (q31_t)0x85BDEF27, (q31_t)0x25E845B5, + (q31_t)0x85A04F28, (q31_t)0x2588349D, (q31_t)0x8582FAA4, + (q31_t)0x25280C5D, (q31_t)0x8565F1B0, (q31_t)0x24C7CD32, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x852CC2BA, + (q31_t)0x24070B07, (q31_t)0x85109CDC, (q31_t)0x23A6887E, + (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84D934B0, + (q31_t)0x22E541AE, (q31_t)0x84BDF285, (q31_t)0x22847DDF, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84885257, + (q31_t)0x21C2B69C, (q31_t)0x846DF476, (q31_t)0x2161B39F, + (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x843A1D70, + (q31_t)0x209F701C, (q31_t)0x8420A46B, (q31_t)0x203E300D, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83EE97AC, + (q31_t)0x1F7B7480, (q31_t)0x83D60411, (q31_t)0x1F19F97B, + (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83A5C2B0, + (q31_t)0x1E56CA1E, (q31_t)0x838E1507, (q31_t)0x1DF5163F, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x835FA00E, + (q31_t)0x1D31774D, (q31_t)0x8348D8DB, (q31_t)0x1CCF8CB3, + (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x831C314E, + (q31_t)0x1C0B826A, (q31_t)0x8306510F, (q31_t)0x1BA96334, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82DB77E5, + (q31_t)0x1AE4F1D6, (q31_t)0x82C67F13, (q31_t)0x1A82A025, + (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x829D753A, + (q31_t)0x19BDCBF2, (q31_t)0x8289644A, (q31_t)0x195B49E9, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x82622AA5, + (q31_t)0x18961727, (q31_t)0x824F0208, (q31_t)0x183366E8, + (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x82299971, + (q31_t)0x176DD9DE, (q31_t)0x8217598F, (q31_t)0x170AFD8D, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81F3C2D7, + (q31_t)0x16451A83, (q31_t)0x81E26C16, (q31_t)0x15E21444, + (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C0A801, + (q31_t)0x151BDF85, (q31_t)0x81B03AC1, (q31_t)0x14B8B17F, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x81904A0C, + (q31_t)0x13F22F57, (q31_t)0x8180C6A9, (q31_t)0x138EDBB0, + (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x8162AA03, + (q31_t)0x12C8106E, (q31_t)0x815410D3, (q31_t)0x1264994E, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x8137C8E6, + (q31_t)0x119D8940, (q31_t)0x812A1A39, (q31_t)0x1139F0CE, + (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x810FA7A0, + (q31_t)0x1072A047, (q31_t)0x8102E3C3, (q31_t)0x100EE8AD, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80EA4712, + (q31_t)0x0F475BFE, (q31_t)0x80DE6E4C, (q31_t)0x0EE38765, + (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80C7A80A, + (q31_t)0x0E1BC2E3, (q31_t)0x80BCBA9C, (q31_t)0x0DB7D376, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80A7CB49, + (q31_t)0x0CEFDB75, (q31_t)0x809DC970, (q31_t)0x0C8BD35E, + (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808AB180, + (q31_t)0x0BC3AC35, (q31_t)0x80819B74, (q31_t)0x0B5F8D9F, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80705B50, + (q31_t)0x0A973BA5, (q31_t)0x80683143, (q31_t)0x0A3308BC, + (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x8058C94C, + (q31_t)0x096A9049, (q31_t)0x80518B6B, (q31_t)0x09064B3A, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x8043FBF6, + (q31_t)0x083DB0A7, (q31_t)0x803DAA69, (q31_t)0x07D95B9E, + (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8031F3C1, + (q31_t)0x0710A344, (q31_t)0x802C8EAD, (q31_t)0x06AC406F, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x8022B113, + (q31_t)0x05E36EA9, (q31_t)0x801E3894, (q31_t)0x057F0034, + (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x80163440, + (q31_t)0x04B6195D, (q31_t)0x8012A86F, (q31_t)0x0451A176, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800C7D8C, + (q31_t)0x0388A9E9, (q31_t)0x8009DE7D, (q31_t)0x03242ABF, + (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x80058D2E, + (q31_t)0x025B26D7, (q31_t)0x8003DAF0, (q31_t)0x01F6A296, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001634D, + (q31_t)0x012D96B0, (q31_t)0x80009DE9, (q31_t)0x00C90F88, + (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x80000000, + (q31_t)0x00000000, (q31_t)0x8000277A, (q31_t)0xFF9B781D, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8001634D, + (q31_t)0xFED2694F, (q31_t)0x800277A5, (q31_t)0xFE6DE2E0, + (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x80058D2E, + (q31_t)0xFDA4D928, (q31_t)0x80078E5E, (q31_t)0xFD40565B, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800C7D8C, + (q31_t)0xFC775616, (q31_t)0x800F6B88, (q31_t)0xFC12D919, + (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x80163440, + (q31_t)0xFB49E6A2, (q31_t)0x801A0EF7, (q31_t)0xFAE571A4, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x8022B113, + (q31_t)0xFA1C9156, (q31_t)0x80277872, (q31_t)0xF9B82683, + (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x8031F3C1, + (q31_t)0xF8EF5CBB, (q31_t)0x8037A7AC, (q31_t)0xF88AFE41, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8043FBF6, + (q31_t)0xF7C24F58, (q31_t)0x804A9C4D, (q31_t)0xF75DFF65, + (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x8058C94C, + (q31_t)0xF6956FB6, (q31_t)0x806055EA, (q31_t)0xF6313076, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x80705B50, + (q31_t)0xF568C45A, (q31_t)0x8078D40D, (q31_t)0xF50497FA, + (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x808AB180, + (q31_t)0xF43C53CA, (q31_t)0x8094162B, (q31_t)0xF3D83C76, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A7CB49, + (q31_t)0xF310248A, (q31_t)0x80B21BAF, (q31_t)0xF2AC246D, + (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C7A80A, + (q31_t)0xF1E43D1C, (q31_t)0x80D2E3F1, (q31_t)0xF1805662, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80EA4712, + (q31_t)0xF0B8A401, (q31_t)0x80F66E3C, (q31_t)0xF054D8D4, + (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x810FA7A0, + (q31_t)0xEF8D5FB8, (q31_t)0x811CB9CA, (q31_t)0xEF29B243, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8137C8E6, + (q31_t)0xEE6276BF, (q31_t)0x8145C5C6, (q31_t)0xEDFEE92B, + (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x8162AA03, + (q31_t)0xED37EF91, (q31_t)0x8171914E, (q31_t)0xECD48406, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81904A0C, + (q31_t)0xEC0DD0A8, (q31_t)0x81A01B6C, (q31_t)0xEBAA894E, + (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81C0A801, + (q31_t)0xEAE4207A, (q31_t)0x81D16320, (q31_t)0xEA80FF79, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81F3C2D7, + (q31_t)0xE9BAE57C, (q31_t)0x82056758, (q31_t)0xE957ECFB, + (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82299971, + (q31_t)0xE8922621, (q31_t)0x823C26F2, (q31_t)0xE82F5844, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82622AA5, + (q31_t)0xE769E8D8, (q31_t)0x8275A0C0, (q31_t)0xE70747C3, + (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x829D753A, + (q31_t)0xE642340D, (q31_t)0x82B1D381, (q31_t)0xE5DFC1E4, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82DB77E5, + (q31_t)0xE51B0E2A, (q31_t)0x82F0BDE8, (q31_t)0xE4B8CD10, + (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x831C314E, + (q31_t)0xE3F47D95, (q31_t)0x83325E97, (q31_t)0xE3926FAC, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835FA00E, + (q31_t)0xE2CE88B2, (q31_t)0x8376B422, (q31_t)0xE26CB01A, + (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x83A5C2B0, + (q31_t)0xE1A935E1, (q31_t)0x83BDBD0D, (q31_t)0xE14794B9, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83EE97AC, + (q31_t)0xE0848B7F, (q31_t)0x840777CF, (q31_t)0xE02323E5, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x843A1D70, + (q31_t)0xDF608FE3, (q31_t)0x8453E2CE, (q31_t)0xDEFF63F4, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x84885257, + (q31_t)0xDE3D4963, (q31_t)0x84A2FC62, (q31_t)0xDDDC5B3A, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84D934B0, + (q31_t)0xDD1ABE51, (q31_t)0x84F4C2D3, (q31_t)0xDCBA1008, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x852CC2BA, + (q31_t)0xDBF8F4F8, (q31_t)0x8549345C, (q31_t)0xDB9888A8, + (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x8582FAA4, + (q31_t)0xDAD7F3A2, (q31_t)0x85A04F28, (q31_t)0xDA77CB62, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85DBDA91, + (q31_t)0xD9B7C093, (q31_t)0x85FA1152, (q31_t)0xD957DE7A, + (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x86376092, + (q31_t)0xD898620C, (q31_t)0x865678EA, (q31_t)0xD838C82D, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x86958AAB, + (q31_t)0xD779DE46, (q31_t)0x86B583EE, (q31_t)0xD71A8EB5, + (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86F656D3, + (q31_t)0xD65C3B7B, (q31_t)0x8717304E, (q31_t)0xD5FD3847, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x8759C2EF, + (q31_t)0xD53F7FDA, (q31_t)0x877B7BEC, (q31_t)0xD4E0CB14, + (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87BFCCD7, + (q31_t)0xD423B190, (q31_t)0x87E2649B, (q31_t)0xD3C54D46, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x88287255, + (q31_t)0xD308D6C6, (q31_t)0x884BE820, (q31_t)0xD2AAC504, + (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8893B124, + (q31_t)0xD1EEF59E, (q31_t)0x88B80431, (q31_t)0xD191386D, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x890186F1, + (q31_t)0xD0D61433, (q31_t)0x8926B677, (q31_t)0xD078AD9D, + (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x8971F15A, + (q31_t)0xCFBE389F, (q31_t)0x8997FC89, (q31_t)0xCF612AAA, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89E4EDEE, + (q31_t)0xCEA768F2, (q31_t)0x8A0BD3F5, (q31_t)0xCE4AB5A2, + (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A5A7A30, + (q31_t)0xCD91AB38, (q31_t)0x8A823A35, (q31_t)0xCD355490, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8AD29393, + (q31_t)0xCC7D0577, (q31_t)0x8AFB2CBA, (q31_t)0xCC210D78, + (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B4D377C, + (q31_t)0xCB697DB0, (q31_t)0x8B76A8E4, (q31_t)0xCB0DE658, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BCA6342, + (q31_t)0xCA5719DB, (q31_t)0x8BF4AC05, (q31_t)0xC9FBE527, + (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C4A142F, + (q31_t)0xC945DFEC, (q31_t)0x8C753361, (q31_t)0xC8EB0FD6, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CCC477D, + (q31_t)0xC835D5D0, (q31_t)0x8CF83C30, (q31_t)0xC7DB6C50, + (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D50FA59, + (q31_t)0xC727016C, (q31_t)0x8D7DC399, (q31_t)0xC6CD0079, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DD829E4, + (q31_t)0xC61968A2, (q31_t)0x8E05C6B7, (q31_t)0xC5BFD22E, + (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E61D32D, + (q31_t)0xC50D1148, (q31_t)0x8E904298, (q31_t)0xC4B3E746, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8EEDF33B, + (q31_t)0xC4020132, (q31_t)0x8F1D343A, (q31_t)0xC3A9458F, + (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F7C8701, + (q31_t)0xC2F83E2A, (q31_t)0x8FAC988E, (q31_t)0xC29FF2D4, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x900D8B69, + (q31_t)0xC1EFCDF2, (q31_t)0x903E6C7A, (q31_t)0xC197F4D3, + (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90A0FD4E, + (q31_t)0xC0E8B648, (q31_t)0x90D2ACD3, (q31_t)0xC0915147, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x9136D97D, + (q31_t)0xBFE2FCDF, (q31_t)0x91695663, (q31_t)0xBF8C0DE2, + (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91CF1CB6, + (q31_t)0xBEDEA765, (q31_t)0x920265E4, (q31_t)0xBE88304F, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x9269C3AC, + (q31_t)0xBDDBBB7F, (q31_t)0x929DD805, (q31_t)0xBD85BE2F, + (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x9306CB04, + (q31_t)0xBCDA3ECA, (q31_t)0x933BA968, (q31_t)0xBC84BD1E, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x93A62F56, + (q31_t)0xBBDA36DC, (q31_t)0x93DBD69F, (q31_t)0xBB8532AF, + (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x9447ED2F, + (q31_t)0xBADBA943, (q31_t)0x947E5C32, (q31_t)0xBA87246C, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94EC010B, + (q31_t)0xB9DE9B83, (q31_t)0x9523369B, (q31_t)0xB98A97D8, + (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x9592675B, + (q31_t)0xB8E31319, (q31_t)0x95CA6246, (q31_t)0xB88F926C, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x963B1C85, + (q31_t)0xB7E9157A, (q31_t)0x9673DB94, (q31_t)0xB796199B, + (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96E61CDF, + (q31_t)0xB6F0A811, (q31_t)0x971F9ED6, (q31_t)0xB69E32CD, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x979364B5, + (q31_t)0xB5F9D042, (q31_t)0x97CDA855, (q31_t)0xB5A7E362, + (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9842F043, + (q31_t)0xB5049368, (q31_t)0x987DF449, (q31_t)0xB4B330B2, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98F4BBBC, + (q31_t)0xB410F6D2, (q31_t)0x99307EE0, (q31_t)0xB3C0200C, + (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x99A8C344, + (q31_t)0xB31EFFCB, (q31_t)0x99E5443A, (q31_t)0xB2CEB6B5, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A5F02F5, + (q31_t)0xB22EB392, (q31_t)0x9A9C406D, (q31_t)0xB1DEF9E8, + (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9B1776D9, + (q31_t)0xB140175B, (q31_t)0x9B556F80, (q31_t)0xB0F0EEDA, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BD21AF2, + (q31_t)0xB0533055, (q31_t)0x9C10CD70, (q31_t)0xB0049AB2, + (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C8EEB33, + (q31_t)0xAF6803A1, (q31_t)0x9CCE562B, (q31_t)0xAF1A0293, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D4DE384, + (q31_t)0xAE7E965B, (q31_t)0x9D8E0596, (q31_t)0xAE312B91, + (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9E0EFFC1, + (q31_t)0xAD96ED91, (q31_t)0x9E4FD789, (q31_t)0xAD4A1ABA, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9ED23BB9, + (q31_t)0xACB10E4A, (q31_t)0x9F13C7D0, (q31_t)0xAC64D510, + (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F979331, + (q31_t)0xABCCFD82, (q31_t)0x9FD9D22A, (q31_t)0xAB815F8C, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA05F01E1, + (q31_t)0xAAEAC02B, (q31_t)0xA0A1F24C, (q31_t)0xAA9FBF1D, + (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA1288376, + (q31_t)0xAA0A5B2D, (q31_t)0xA16C23E1, (q31_t)0xA9BFF8A8, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1F41391, + (q31_t)0xA92BD366, (q31_t)0xA2386283, (q31_t)0xA8E21106, + (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA2C1ADC9, + (q31_t)0xA84F2DA9, (q31_t)0xA306A9C7, (q31_t)0xA8060D08, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA3914DA7, + (q31_t)0xA7746EC0, (q31_t)0xA3D6F533, (q31_t)0xA72BF173, + (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA462EEAC, + (q31_t)0xA69B9B68, (q31_t)0xA4A94042, (q31_t)0xA653C302, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA5368C4B, + (q31_t)0xA5C4B855, (q31_t)0xA57D8666, (q31_t)0xA57D8666, + (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA60C21ED, + (q31_t)0xA4EFCA31, (q31_t)0xA653C302, (q31_t)0xA4A94042, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6E3AAF2, + (q31_t)0xA41CD598, (q31_t)0xA72BF173, (q31_t)0xA3D6F533, + (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA7BD22AB, + (q31_t)0xA34BDF20, (q31_t)0xA8060D08, (q31_t)0xA306A9C7, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA8988463, + (q31_t)0xA27CEB4F, (q31_t)0xA8E21106, (q31_t)0xA2386283, + (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA975CB56, + (q31_t)0xA1AFFEA2, (q31_t)0xA9BFF8A8, (q31_t)0xA16C23E1, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA54F2B9, + (q31_t)0xA0E51D8C, (q31_t)0xAA9FBF1D, (q31_t)0xA0A1F24C, + (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB35F5B5, + (q31_t)0xA01C4C72, (q31_t)0xAB815F8C, (q31_t)0x9FD9D22A, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xAC18CF68, + (q31_t)0x9F558FB0, (q31_t)0xAC64D510, (q31_t)0x9F13C7D0, + (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACFD7AE8, + (q31_t)0x9E90EB94, (q31_t)0xAD4A1ABA, (q31_t)0x9E4FD789, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADE3F33E, + (q31_t)0x9DCE6462, (q31_t)0xAE312B91, (q31_t)0x9D8E0596, + (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAECC336B, + (q31_t)0x9D0DFE53, (q31_t)0xAF1A0293, (q31_t)0x9CCE562B, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAFB63667, + (q31_t)0x9C4FBD92, (q31_t)0xB0049AB2, (q31_t)0x9C10CD70, + (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB0A1F71C, + (q31_t)0x9B93A640, (q31_t)0xB0F0EEDA, (q31_t)0x9B556F80, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB18F7070, + (q31_t)0x9AD9BC71, (q31_t)0xB1DEF9E8, (q31_t)0x9A9C406D, + (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB27E9D3B, + (q31_t)0x9A22042C, (q31_t)0xB2CEB6B5, (q31_t)0x99E5443A, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB36F784E, + (q31_t)0x996C816F, (q31_t)0xB3C0200C, (q31_t)0x99307EE0, + (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB461FC70, + (q31_t)0x98B93828, (q31_t)0xB4B330B2, (q31_t)0x987DF449, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB556245E, + (q31_t)0x98082C3B, (q31_t)0xB5A7E362, (q31_t)0x97CDA855, + (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB64BEACC, + (q31_t)0x9759617E, (q31_t)0xB69E32CD, (q31_t)0x971F9ED6, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB7434A67, + (q31_t)0x96ACDBBD, (q31_t)0xB796199B, (q31_t)0x9673DB94, + (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB83C3DD1, + (q31_t)0x96029EB5, (q31_t)0xB88F926C, (q31_t)0x95CA6246, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB936BFA3, + (q31_t)0x955AAE17, (q31_t)0xB98A97D8, (q31_t)0x9523369B, + (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA32CA70, + (q31_t)0x94B50D87, (q31_t)0xBA87246C, (q31_t)0x947E5C32, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB3058C0, + (q31_t)0x9411C09D, (q31_t)0xBB8532AF, (q31_t)0x93DBD69F, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC2F6513, + (q31_t)0x9370CAE4, (q31_t)0xBC84BD1E, (q31_t)0x933BA968, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD2FE9E1, + (q31_t)0x92D22FD8, (q31_t)0xBD85BE2F, (q31_t)0x929DD805, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE31E19B, + (q31_t)0x9235F2EB, (q31_t)0xBE88304F, (q31_t)0x920265E4, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF3546A8, + (q31_t)0x919C1780, (q31_t)0xBF8C0DE2, (q31_t)0x91695663, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC03A1368, + (q31_t)0x9104A0ED, (q31_t)0xC0915147, (q31_t)0x90D2ACD3, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1404233, + (q31_t)0x906F927B, (q31_t)0xC197F4D3, (q31_t)0x903E6C7A, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC247CD5A, + (q31_t)0x8FDCEF66, (q31_t)0xC29FF2D4, (q31_t)0x8FAC988E, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC350AF25, + (q31_t)0x8F4CBADB, (q31_t)0xC3A9458F, (q31_t)0x8F1D343A, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC45AE1D7, + (q31_t)0x8EBEF7FB, (q31_t)0xC4B3E746, (q31_t)0x8E904298, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC5665FA8, + (q31_t)0x8E33A9D9, (q31_t)0xC5BFD22E, (q31_t)0x8E05C6B7, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC67322CD, + (q31_t)0x8DAAD37B, (q31_t)0xC6CD0079, (q31_t)0x8D7DC399, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7812571, + (q31_t)0x8D2477D8, (q31_t)0xC7DB6C50, (q31_t)0x8CF83C30, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC89061BA, + (q31_t)0x8CA099D9, (q31_t)0xC8EB0FD6, (q31_t)0x8C753361, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC9A0D1C4, + (q31_t)0x8C1F3C5C, (q31_t)0xC9FBE527, (q31_t)0x8BF4AC05, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCAB26FA9, + (q31_t)0x8BA0622F, (q31_t)0xCB0DE658, (q31_t)0x8B76A8E4, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCBC53578, + (q31_t)0x8B240E10, (q31_t)0xCC210D78, (q31_t)0x8AFB2CBA, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCD91D3D, + (q31_t)0x8AAA42B4, (q31_t)0xCD355490, (q31_t)0x8A823A35, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDEE20FC, + (q31_t)0x8A3302BD, (q31_t)0xCE4AB5A2, (q31_t)0x8A0BD3F5, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCF043AB2, + (q31_t)0x89BE50C3, (q31_t)0xCF612AAA, (q31_t)0x8997FC89, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xD01B6459, + (q31_t)0x894C2F4C, (q31_t)0xD078AD9D, (q31_t)0x8926B677, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD13397E1, + (q31_t)0x88DCA0D3, (q31_t)0xD191386D, (q31_t)0x88B80431, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD24CCF38, + (q31_t)0x886FA7C2, (q31_t)0xD2AAC504, (q31_t)0x884BE820, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD3670445, + (q31_t)0x88054677, (q31_t)0xD3C54D46, (q31_t)0x87E2649B, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD48230E8, + (q31_t)0x879D7F40, (q31_t)0xD4E0CB14, (q31_t)0x877B7BEC, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD59E4EFE, + (q31_t)0x8738545E, (q31_t)0xD5FD3847, (q31_t)0x8717304E, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD6BB585D, + (q31_t)0x86D5C802, (q31_t)0xD71A8EB5, (q31_t)0x86B583EE, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7D946D7, + (q31_t)0x8675DC4E, (q31_t)0xD838C82D, (q31_t)0x865678EA, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8F81439, + (q31_t)0x86189359, (q31_t)0xD957DE7A, (q31_t)0x85FA1152, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xDA17BA4A, + (q31_t)0x85BDEF27, (q31_t)0xDA77CB62, (q31_t)0x85A04F28, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB3832CD, + (q31_t)0x8565F1B0, (q31_t)0xDB9888A8, (q31_t)0x8549345C, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC597781, + (q31_t)0x85109CDC, (q31_t)0xDCBA1008, (q31_t)0x84F4C2D3, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD7B8220, + (q31_t)0x84BDF285, (q31_t)0xDDDC5B3A, (q31_t)0x84A2FC62, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE9E4C60, + (q31_t)0x846DF476, (q31_t)0xDEFF63F4, (q31_t)0x8453E2CE, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDFC1CFF2, + (q31_t)0x8420A46B, (q31_t)0xE02323E5, (q31_t)0x840777CF, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0E60684, + (q31_t)0x83D60411, (q31_t)0xE14794B9, (q31_t)0x83BDBD0D, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE20AE9C1, + (q31_t)0x838E1507, (q31_t)0xE26CB01A, (q31_t)0x8376B422, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE330734C, + (q31_t)0x8348D8DB, (q31_t)0xE3926FAC, (q31_t)0x83325E97, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4569CCB, + (q31_t)0x8306510F, (q31_t)0xE4B8CD10, (q31_t)0x82F0BDE8, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE57D5FDA, + (q31_t)0x82C67F13, (q31_t)0xE5DFC1E4, (q31_t)0x82B1D381, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6A4B616, + (q31_t)0x8289644A, (q31_t)0xE70747C3, (q31_t)0x8275A0C0, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE7CC9917, + (q31_t)0x824F0208, (q31_t)0xE82F5844, (q31_t)0x823C26F2, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8F50273, + (q31_t)0x8217598F, (q31_t)0xE957ECFB, (q31_t)0x82056758, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xEA1DEBBB, + (q31_t)0x81E26C16, (q31_t)0xEA80FF79, (q31_t)0x81D16320, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB474E80, + (q31_t)0x81B03AC1, (q31_t)0xEBAA894E, (q31_t)0x81A01B6C, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC71244F, + (q31_t)0x8180C6A9, (q31_t)0xECD48406, (q31_t)0x8171914E, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED9B66B2, + (q31_t)0x815410D3, (q31_t)0xEDFEE92B, (q31_t)0x8145C5C6, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEEC60F31, + (q31_t)0x812A1A39, (q31_t)0xEF29B243, (q31_t)0x811CB9CA, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFF11752, + (q31_t)0x8102E3C3, (q31_t)0xF054D8D4, (q31_t)0x80F66E3C, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF11C789A, + (q31_t)0x80DE6E4C, (q31_t)0xF1805662, (q31_t)0x80D2E3F1, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF2482C89, + (q31_t)0x80BCBA9C, (q31_t)0xF2AC246D, (q31_t)0x80B21BAF, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF3742CA1, + (q31_t)0x809DC970, (q31_t)0xF3D83C76, (q31_t)0x8094162B, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF4A07260, + (q31_t)0x80819B74, (q31_t)0xF50497FA, (q31_t)0x8078D40D, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF5CCF743, + (q31_t)0x80683143, (q31_t)0xF6313076, (q31_t)0x806055EA, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6F9B4C5, + (q31_t)0x80518B6B, (q31_t)0xF75DFF65, (q31_t)0x804A9C4D, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF826A461, + (q31_t)0x803DAA69, (q31_t)0xF88AFE41, (q31_t)0x8037A7AC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF953BF90, + (q31_t)0x802C8EAD, (q31_t)0xF9B82683, (q31_t)0x80277872, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA80FFCB, + (q31_t)0x801E3894, (q31_t)0xFAE571A4, (q31_t)0x801A0EF7, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFBAE5E89, + (q31_t)0x8012A86F, (q31_t)0xFC12D919, (q31_t)0x800F6B88, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCDBD541, + (q31_t)0x8009DE7D, (q31_t)0xFD40565B, (q31_t)0x80078E5E, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFE095D69, + (q31_t)0x8003DAF0, (q31_t)0xFE6DE2E0, (q31_t)0x800277A5, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF36F078, + (q31_t)0x80009DE9, (q31_t)0xFF9B781D, (q31_t)0x8000277A +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) +/** + @par + Example code for Q31 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefQ31[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefQ31[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to Q31(Fixed point 1.31): + round(twiddleCoefQ31(i) * pow(2, 31)) + */ +const q31_t twiddleCoef_4096_q31[6144] = +{ + (q31_t)0x7FFFFFFF, (q31_t)0x00000000, (q31_t)0x7FFFF621, + (q31_t)0x003243F5, (q31_t)0x7FFFD885, (q31_t)0x006487E3, + (q31_t)0x7FFFA72C, (q31_t)0x0096CBC1, (q31_t)0x7FFF6216, + (q31_t)0x00C90F88, (q31_t)0x7FFF0942, (q31_t)0x00FB532F, + (q31_t)0x7FFE9CB2, (q31_t)0x012D96B0, (q31_t)0x7FFE1C64, + (q31_t)0x015FDA03, (q31_t)0x7FFD885A, (q31_t)0x01921D1F, + (q31_t)0x7FFCE093, (q31_t)0x01C45FFE, (q31_t)0x7FFC250F, + (q31_t)0x01F6A296, (q31_t)0x7FFB55CE, (q31_t)0x0228E4E1, + (q31_t)0x7FFA72D1, (q31_t)0x025B26D7, (q31_t)0x7FF97C17, + (q31_t)0x028D6870, (q31_t)0x7FF871A1, (q31_t)0x02BFA9A4, + (q31_t)0x7FF7536F, (q31_t)0x02F1EA6B, (q31_t)0x7FF62182, + (q31_t)0x03242ABF, (q31_t)0x7FF4DBD8, (q31_t)0x03566A96, + (q31_t)0x7FF38273, (q31_t)0x0388A9E9, (q31_t)0x7FF21553, + (q31_t)0x03BAE8B1, (q31_t)0x7FF09477, (q31_t)0x03ED26E6, + (q31_t)0x7FEEFFE1, (q31_t)0x041F647F, (q31_t)0x7FED5790, + (q31_t)0x0451A176, (q31_t)0x7FEB9B85, (q31_t)0x0483DDC3, + (q31_t)0x7FE9CBC0, (q31_t)0x04B6195D, (q31_t)0x7FE7E840, + (q31_t)0x04E8543D, (q31_t)0x7FE5F108, (q31_t)0x051A8E5C, + (q31_t)0x7FE3E616, (q31_t)0x054CC7B0, (q31_t)0x7FE1C76B, + (q31_t)0x057F0034, (q31_t)0x7FDF9508, (q31_t)0x05B137DF, + (q31_t)0x7FDD4EEC, (q31_t)0x05E36EA9, (q31_t)0x7FDAF518, + (q31_t)0x0615A48A, (q31_t)0x7FD8878D, (q31_t)0x0647D97C, + (q31_t)0x7FD6064B, (q31_t)0x067A0D75, (q31_t)0x7FD37152, + (q31_t)0x06AC406F, (q31_t)0x7FD0C8A3, (q31_t)0x06DE7261, + (q31_t)0x7FCE0C3E, (q31_t)0x0710A344, (q31_t)0x7FCB3C23, + (q31_t)0x0742D310, (q31_t)0x7FC85853, (q31_t)0x077501BE, + (q31_t)0x7FC560CF, (q31_t)0x07A72F45, (q31_t)0x7FC25596, + (q31_t)0x07D95B9E, (q31_t)0x7FBF36A9, (q31_t)0x080B86C1, + (q31_t)0x7FBC040A, (q31_t)0x083DB0A7, (q31_t)0x7FB8BDB7, + (q31_t)0x086FD947, (q31_t)0x7FB563B2, (q31_t)0x08A2009A, + (q31_t)0x7FB1F5FC, (q31_t)0x08D42698, (q31_t)0x7FAE7494, + (q31_t)0x09064B3A, (q31_t)0x7FAADF7C, (q31_t)0x09386E77, + (q31_t)0x7FA736B4, (q31_t)0x096A9049, (q31_t)0x7FA37A3C, + (q31_t)0x099CB0A7, (q31_t)0x7F9FAA15, (q31_t)0x09CECF89, + (q31_t)0x7F9BC63F, (q31_t)0x0A00ECE8, (q31_t)0x7F97CEBC, + (q31_t)0x0A3308BC, (q31_t)0x7F93C38C, (q31_t)0x0A6522FE, + (q31_t)0x7F8FA4AF, (q31_t)0x0A973BA5, (q31_t)0x7F8B7226, + (q31_t)0x0AC952AA, (q31_t)0x7F872BF3, (q31_t)0x0AFB6805, + (q31_t)0x7F82D214, (q31_t)0x0B2D7BAE, (q31_t)0x7F7E648B, + (q31_t)0x0B5F8D9F, (q31_t)0x7F79E35A, (q31_t)0x0B919DCE, + (q31_t)0x7F754E7F, (q31_t)0x0BC3AC35, (q31_t)0x7F70A5FD, + (q31_t)0x0BF5B8CB, (q31_t)0x7F6BE9D4, (q31_t)0x0C27C389, + (q31_t)0x7F671A04, (q31_t)0x0C59CC67, (q31_t)0x7F62368F, + (q31_t)0x0C8BD35E, (q31_t)0x7F5D3F75, (q31_t)0x0CBDD865, + (q31_t)0x7F5834B6, (q31_t)0x0CEFDB75, (q31_t)0x7F531654, + (q31_t)0x0D21DC87, (q31_t)0x7F4DE450, (q31_t)0x0D53DB92, + (q31_t)0x7F489EAA, (q31_t)0x0D85D88F, (q31_t)0x7F434563, + (q31_t)0x0DB7D376, (q31_t)0x7F3DD87C, (q31_t)0x0DE9CC3F, + (q31_t)0x7F3857F5, (q31_t)0x0E1BC2E3, (q31_t)0x7F32C3D0, + (q31_t)0x0E4DB75B, (q31_t)0x7F2D1C0E, (q31_t)0x0E7FA99D, + (q31_t)0x7F2760AF, (q31_t)0x0EB199A3, (q31_t)0x7F2191B4, + (q31_t)0x0EE38765, (q31_t)0x7F1BAF1E, (q31_t)0x0F1572DC, + (q31_t)0x7F15B8EE, (q31_t)0x0F475BFE, (q31_t)0x7F0FAF24, + (q31_t)0x0F7942C6, (q31_t)0x7F0991C3, (q31_t)0x0FAB272B, + (q31_t)0x7F0360CB, (q31_t)0x0FDD0925, (q31_t)0x7EFD1C3C, + (q31_t)0x100EE8AD, (q31_t)0x7EF6C418, (q31_t)0x1040C5BB, + (q31_t)0x7EF0585F, (q31_t)0x1072A047, (q31_t)0x7EE9D913, + (q31_t)0x10A4784A, (q31_t)0x7EE34635, (q31_t)0x10D64DBC, + (q31_t)0x7EDC9FC6, (q31_t)0x11082096, (q31_t)0x7ED5E5C6, + (q31_t)0x1139F0CE, (q31_t)0x7ECF1837, (q31_t)0x116BBE5F, + (q31_t)0x7EC8371A, (q31_t)0x119D8940, (q31_t)0x7EC1426F, + (q31_t)0x11CF516A, (q31_t)0x7EBA3A39, (q31_t)0x120116D4, + (q31_t)0x7EB31E77, (q31_t)0x1232D978, (q31_t)0x7EABEF2C, + (q31_t)0x1264994E, (q31_t)0x7EA4AC58, (q31_t)0x1296564D, + (q31_t)0x7E9D55FC, (q31_t)0x12C8106E, (q31_t)0x7E95EC19, + (q31_t)0x12F9C7AA, (q31_t)0x7E8E6EB1, (q31_t)0x132B7BF9, + (q31_t)0x7E86DDC5, (q31_t)0x135D2D53, (q31_t)0x7E7F3956, + (q31_t)0x138EDBB0, (q31_t)0x7E778165, (q31_t)0x13C0870A, + (q31_t)0x7E6FB5F3, (q31_t)0x13F22F57, (q31_t)0x7E67D702, + (q31_t)0x1423D492, (q31_t)0x7E5FE493, (q31_t)0x145576B1, + (q31_t)0x7E57DEA6, (q31_t)0x148715AD, (q31_t)0x7E4FC53E, + (q31_t)0x14B8B17F, (q31_t)0x7E47985B, (q31_t)0x14EA4A1F, + (q31_t)0x7E3F57FE, (q31_t)0x151BDF85, (q31_t)0x7E37042A, + (q31_t)0x154D71AA, (q31_t)0x7E2E9CDF, (q31_t)0x157F0086, + (q31_t)0x7E26221E, (q31_t)0x15B08C11, (q31_t)0x7E1D93E9, + (q31_t)0x15E21444, (q31_t)0x7E14F242, (q31_t)0x16139917, + (q31_t)0x7E0C3D29, (q31_t)0x16451A83, (q31_t)0x7E03749F, + (q31_t)0x1676987F, (q31_t)0x7DFA98A7, (q31_t)0x16A81305, + (q31_t)0x7DF1A942, (q31_t)0x16D98A0C, (q31_t)0x7DE8A670, + (q31_t)0x170AFD8D, (q31_t)0x7DDF9034, (q31_t)0x173C6D80, + (q31_t)0x7DD6668E, (q31_t)0x176DD9DE, (q31_t)0x7DCD2981, + (q31_t)0x179F429F, (q31_t)0x7DC3D90D, (q31_t)0x17D0A7BB, + (q31_t)0x7DBA7534, (q31_t)0x1802092C, (q31_t)0x7DB0FDF7, + (q31_t)0x183366E8, (q31_t)0x7DA77359, (q31_t)0x1864C0E9, + (q31_t)0x7D9DD55A, (q31_t)0x18961727, (q31_t)0x7D9423FB, + (q31_t)0x18C7699B, (q31_t)0x7D8A5F3F, (q31_t)0x18F8B83C, + (q31_t)0x7D808727, (q31_t)0x192A0303, (q31_t)0x7D769BB5, + (q31_t)0x195B49E9, (q31_t)0x7D6C9CE9, (q31_t)0x198C8CE6, + (q31_t)0x7D628AC5, (q31_t)0x19BDCBF2, (q31_t)0x7D58654C, + (q31_t)0x19EF0706, (q31_t)0x7D4E2C7E, (q31_t)0x1A203E1B, + (q31_t)0x7D43E05E, (q31_t)0x1A517127, (q31_t)0x7D3980EC, + (q31_t)0x1A82A025, (q31_t)0x7D2F0E2A, (q31_t)0x1AB3CB0C, + (q31_t)0x7D24881A, (q31_t)0x1AE4F1D6, (q31_t)0x7D19EEBE, + (q31_t)0x1B161479, (q31_t)0x7D0F4218, (q31_t)0x1B4732EF, + (q31_t)0x7D048228, (q31_t)0x1B784D30, (q31_t)0x7CF9AEF0, + (q31_t)0x1BA96334, (q31_t)0x7CEEC873, (q31_t)0x1BDA74F5, + (q31_t)0x7CE3CEB1, (q31_t)0x1C0B826A, (q31_t)0x7CD8C1AD, + (q31_t)0x1C3C8B8C, (q31_t)0x7CCDA168, (q31_t)0x1C6D9053, + (q31_t)0x7CC26DE5, (q31_t)0x1C9E90B8, (q31_t)0x7CB72724, + (q31_t)0x1CCF8CB3, (q31_t)0x7CABCD27, (q31_t)0x1D00843C, + (q31_t)0x7CA05FF1, (q31_t)0x1D31774D, (q31_t)0x7C94DF82, + (q31_t)0x1D6265DD, (q31_t)0x7C894BDD, (q31_t)0x1D934FE5, + (q31_t)0x7C7DA504, (q31_t)0x1DC4355D, (q31_t)0x7C71EAF8, + (q31_t)0x1DF5163F, (q31_t)0x7C661DBB, (q31_t)0x1E25F281, + (q31_t)0x7C5A3D4F, (q31_t)0x1E56CA1E, (q31_t)0x7C4E49B6, + (q31_t)0x1E879D0C, (q31_t)0x7C4242F2, (q31_t)0x1EB86B46, + (q31_t)0x7C362904, (q31_t)0x1EE934C2, (q31_t)0x7C29FBEE, + (q31_t)0x1F19F97B, (q31_t)0x7C1DBBB2, (q31_t)0x1F4AB967, + (q31_t)0x7C116853, (q31_t)0x1F7B7480, (q31_t)0x7C0501D1, + (q31_t)0x1FAC2ABF, (q31_t)0x7BF88830, (q31_t)0x1FDCDC1A, + (q31_t)0x7BEBFB70, (q31_t)0x200D888C, (q31_t)0x7BDF5B94, + (q31_t)0x203E300D, (q31_t)0x7BD2A89E, (q31_t)0x206ED295, + (q31_t)0x7BC5E28F, (q31_t)0x209F701C, (q31_t)0x7BB9096A, + (q31_t)0x20D0089B, (q31_t)0x7BAC1D31, (q31_t)0x21009C0B, + (q31_t)0x7B9F1DE5, (q31_t)0x21312A65, (q31_t)0x7B920B89, + (q31_t)0x2161B39F, (q31_t)0x7B84E61E, (q31_t)0x219237B4, + (q31_t)0x7B77ADA8, (q31_t)0x21C2B69C, (q31_t)0x7B6A6227, + (q31_t)0x21F3304E, (q31_t)0x7B5D039D, (q31_t)0x2223A4C5, + (q31_t)0x7B4F920E, (q31_t)0x225413F8, (q31_t)0x7B420D7A, + (q31_t)0x22847DDF, (q31_t)0x7B3475E4, (q31_t)0x22B4E274, + (q31_t)0x7B26CB4F, (q31_t)0x22E541AE, (q31_t)0x7B190DBB, + (q31_t)0x23159B87, (q31_t)0x7B0B3D2C, (q31_t)0x2345EFF7, + (q31_t)0x7AFD59A3, (q31_t)0x23763EF7, (q31_t)0x7AEF6323, + (q31_t)0x23A6887E, (q31_t)0x7AE159AE, (q31_t)0x23D6CC86, + (q31_t)0x7AD33D45, (q31_t)0x24070B07, (q31_t)0x7AC50DEB, + (q31_t)0x243743FA, (q31_t)0x7AB6CBA3, (q31_t)0x24677757, + (q31_t)0x7AA8766E, (q31_t)0x2497A517, (q31_t)0x7A9A0E4F, + (q31_t)0x24C7CD32, (q31_t)0x7A8B9348, (q31_t)0x24F7EFA1, + (q31_t)0x7A7D055B, (q31_t)0x25280C5D, (q31_t)0x7A6E648A, + (q31_t)0x2558235E, (q31_t)0x7A5FB0D8, (q31_t)0x2588349D, + (q31_t)0x7A50EA46, (q31_t)0x25B84012, (q31_t)0x7A4210D8, + (q31_t)0x25E845B5, (q31_t)0x7A33248F, (q31_t)0x26184581, + (q31_t)0x7A24256E, (q31_t)0x26483F6C, (q31_t)0x7A151377, + (q31_t)0x26783370, (q31_t)0x7A05EEAD, (q31_t)0x26A82185, + (q31_t)0x79F6B711, (q31_t)0x26D809A5, (q31_t)0x79E76CA6, + (q31_t)0x2707EBC6, (q31_t)0x79D80F6F, (q31_t)0x2737C7E3, + (q31_t)0x79C89F6D, (q31_t)0x27679DF4, (q31_t)0x79B91CA4, + (q31_t)0x27976DF1, (q31_t)0x79A98715, (q31_t)0x27C737D2, + (q31_t)0x7999DEC3, (q31_t)0x27F6FB92, (q31_t)0x798A23B1, + (q31_t)0x2826B928, (q31_t)0x797A55E0, (q31_t)0x2856708C, + (q31_t)0x796A7554, (q31_t)0x288621B9, (q31_t)0x795A820E, + (q31_t)0x28B5CCA5, (q31_t)0x794A7C11, (q31_t)0x28E5714A, + (q31_t)0x793A6360, (q31_t)0x29150FA1, (q31_t)0x792A37FE, + (q31_t)0x2944A7A2, (q31_t)0x7919F9EB, (q31_t)0x29743945, + (q31_t)0x7909A92C, (q31_t)0x29A3C484, (q31_t)0x78F945C3, + (q31_t)0x29D34958, (q31_t)0x78E8CFB1, (q31_t)0x2A02C7B8, + (q31_t)0x78D846FB, (q31_t)0x2A323F9D, (q31_t)0x78C7ABA1, + (q31_t)0x2A61B101, (q31_t)0x78B6FDA8, (q31_t)0x2A911BDB, + (q31_t)0x78A63D10, (q31_t)0x2AC08025, (q31_t)0x789569DE, + (q31_t)0x2AEFDDD8, (q31_t)0x78848413, (q31_t)0x2B1F34EB, + (q31_t)0x78738BB3, (q31_t)0x2B4E8558, (q31_t)0x786280BF, + (q31_t)0x2B7DCF17, (q31_t)0x7851633B, (q31_t)0x2BAD1221, + (q31_t)0x78403328, (q31_t)0x2BDC4E6F, (q31_t)0x782EF08B, + (q31_t)0x2C0B83F9, (q31_t)0x781D9B64, (q31_t)0x2C3AB2B9, + (q31_t)0x780C33B8, (q31_t)0x2C69DAA6, (q31_t)0x77FAB988, + (q31_t)0x2C98FBBA, (q31_t)0x77E92CD8, (q31_t)0x2CC815ED, + (q31_t)0x77D78DAA, (q31_t)0x2CF72939, (q31_t)0x77C5DC01, + (q31_t)0x2D263595, (q31_t)0x77B417DF, (q31_t)0x2D553AFB, + (q31_t)0x77A24148, (q31_t)0x2D843963, (q31_t)0x7790583D, + (q31_t)0x2DB330C7, (q31_t)0x777E5CC3, (q31_t)0x2DE2211E, + (q31_t)0x776C4EDB, (q31_t)0x2E110A62, (q31_t)0x775A2E88, + (q31_t)0x2E3FEC8B, (q31_t)0x7747FBCE, (q31_t)0x2E6EC792, + (q31_t)0x7735B6AE, (q31_t)0x2E9D9B70, (q31_t)0x77235F2D, + (q31_t)0x2ECC681E, (q31_t)0x7710F54B, (q31_t)0x2EFB2D94, + (q31_t)0x76FE790E, (q31_t)0x2F29EBCC, (q31_t)0x76EBEA77, + (q31_t)0x2F58A2BD, (q31_t)0x76D94988, (q31_t)0x2F875262, + (q31_t)0x76C69646, (q31_t)0x2FB5FAB2, (q31_t)0x76B3D0B3, + (q31_t)0x2FE49BA6, (q31_t)0x76A0F8D2, (q31_t)0x30133538, + (q31_t)0x768E0EA5, (q31_t)0x3041C760, (q31_t)0x767B1230, + (q31_t)0x30705217, (q31_t)0x76680376, (q31_t)0x309ED555, + (q31_t)0x7654E279, (q31_t)0x30CD5114, (q31_t)0x7641AF3C, + (q31_t)0x30FBC54D, (q31_t)0x762E69C3, (q31_t)0x312A31F8, + (q31_t)0x761B1211, (q31_t)0x3158970D, (q31_t)0x7607A827, + (q31_t)0x3186F487, (q31_t)0x75F42C0A, (q31_t)0x31B54A5D, + (q31_t)0x75E09DBD, (q31_t)0x31E39889, (q31_t)0x75CCFD42, + (q31_t)0x3211DF03, (q31_t)0x75B94A9C, (q31_t)0x32401DC5, + (q31_t)0x75A585CF, (q31_t)0x326E54C7, (q31_t)0x7591AEDD, + (q31_t)0x329C8402, (q31_t)0x757DC5CA, (q31_t)0x32CAAB6F, + (q31_t)0x7569CA98, (q31_t)0x32F8CB07, (q31_t)0x7555BD4B, + (q31_t)0x3326E2C2, (q31_t)0x75419DE6, (q31_t)0x3354F29A, + (q31_t)0x752D6C6C, (q31_t)0x3382FA88, (q31_t)0x751928E0, + (q31_t)0x33B0FA84, (q31_t)0x7504D345, (q31_t)0x33DEF287, + (q31_t)0x74F06B9E, (q31_t)0x340CE28A, (q31_t)0x74DBF1EF, + (q31_t)0x343ACA87, (q31_t)0x74C7663A, (q31_t)0x3468AA76, + (q31_t)0x74B2C883, (q31_t)0x3496824F, (q31_t)0x749E18CD, + (q31_t)0x34C4520D, (q31_t)0x7489571B, (q31_t)0x34F219A7, + (q31_t)0x74748371, (q31_t)0x351FD917, (q31_t)0x745F9DD1, + (q31_t)0x354D9056, (q31_t)0x744AA63E, (q31_t)0x357B3F5D, + (q31_t)0x74359CBD, (q31_t)0x35A8E624, (q31_t)0x74208150, + (q31_t)0x35D684A5, (q31_t)0x740B53FA, (q31_t)0x36041AD9, + (q31_t)0x73F614C0, (q31_t)0x3631A8B7, (q31_t)0x73E0C3A3, + (q31_t)0x365F2E3B, (q31_t)0x73CB60A7, (q31_t)0x368CAB5C, + (q31_t)0x73B5EBD0, (q31_t)0x36BA2013, (q31_t)0x73A06522, + (q31_t)0x36E78C5A, (q31_t)0x738ACC9E, (q31_t)0x3714F02A, + (q31_t)0x73752249, (q31_t)0x37424B7A, (q31_t)0x735F6626, + (q31_t)0x376F9E46, (q31_t)0x73499838, (q31_t)0x379CE884, + (q31_t)0x7333B883, (q31_t)0x37CA2A30, (q31_t)0x731DC709, + (q31_t)0x37F76340, (q31_t)0x7307C3D0, (q31_t)0x382493B0, + (q31_t)0x72F1AED8, (q31_t)0x3851BB76, (q31_t)0x72DB8828, + (q31_t)0x387EDA8E, (q31_t)0x72C54FC0, (q31_t)0x38ABF0EF, + (q31_t)0x72AF05A6, (q31_t)0x38D8FE93, (q31_t)0x7298A9DC, + (q31_t)0x39060372, (q31_t)0x72823C66, (q31_t)0x3932FF87, + (q31_t)0x726BBD48, (q31_t)0x395FF2C9, (q31_t)0x72552C84, + (q31_t)0x398CDD32, (q31_t)0x723E8A1F, (q31_t)0x39B9BEBB, + (q31_t)0x7227D61C, (q31_t)0x39E6975D, (q31_t)0x7211107D, + (q31_t)0x3A136712, (q31_t)0x71FA3948, (q31_t)0x3A402DD1, + (q31_t)0x71E3507F, (q31_t)0x3A6CEB95, (q31_t)0x71CC5626, + (q31_t)0x3A99A057, (q31_t)0x71B54A40, (q31_t)0x3AC64C0F, + (q31_t)0x719E2CD2, (q31_t)0x3AF2EEB7, (q31_t)0x7186FDDE, + (q31_t)0x3B1F8847, (q31_t)0x716FBD68, (q31_t)0x3B4C18BA, + (q31_t)0x71586B73, (q31_t)0x3B78A007, (q31_t)0x71410804, + (q31_t)0x3BA51E29, (q31_t)0x7129931E, (q31_t)0x3BD19317, + (q31_t)0x71120CC5, (q31_t)0x3BFDFECD, (q31_t)0x70FA74FB, + (q31_t)0x3C2A6142, (q31_t)0x70E2CBC6, (q31_t)0x3C56BA70, + (q31_t)0x70CB1127, (q31_t)0x3C830A4F, (q31_t)0x70B34524, + (q31_t)0x3CAF50DA, (q31_t)0x709B67C0, (q31_t)0x3CDB8E09, + (q31_t)0x708378FE, (q31_t)0x3D07C1D5, (q31_t)0x706B78E3, + (q31_t)0x3D33EC39, (q31_t)0x70536771, (q31_t)0x3D600D2B, + (q31_t)0x703B44AC, (q31_t)0x3D8C24A7, (q31_t)0x70231099, + (q31_t)0x3DB832A5, (q31_t)0x700ACB3B, (q31_t)0x3DE4371F, + (q31_t)0x6FF27496, (q31_t)0x3E10320D, (q31_t)0x6FDA0CAD, + (q31_t)0x3E3C2369, (q31_t)0x6FC19385, (q31_t)0x3E680B2C, + (q31_t)0x6FA90920, (q31_t)0x3E93E94F, (q31_t)0x6F906D84, + (q31_t)0x3EBFBDCC, (q31_t)0x6F77C0B3, (q31_t)0x3EEB889C, + (q31_t)0x6F5F02B1, (q31_t)0x3F1749B7, (q31_t)0x6F463383, + (q31_t)0x3F430118, (q31_t)0x6F2D532C, (q31_t)0x3F6EAEB8, + (q31_t)0x6F1461AF, (q31_t)0x3F9A528F, (q31_t)0x6EFB5F12, + (q31_t)0x3FC5EC97, (q31_t)0x6EE24B57, (q31_t)0x3FF17CCA, + (q31_t)0x6EC92682, (q31_t)0x401D0320, (q31_t)0x6EAFF098, + (q31_t)0x40487F93, (q31_t)0x6E96A99C, (q31_t)0x4073F21D, + (q31_t)0x6E7D5193, (q31_t)0x409F5AB6, (q31_t)0x6E63E87F, + (q31_t)0x40CAB957, (q31_t)0x6E4A6E65, (q31_t)0x40F60DFB, + (q31_t)0x6E30E349, (q31_t)0x4121589A, (q31_t)0x6E17472F, + (q31_t)0x414C992E, (q31_t)0x6DFD9A1B, (q31_t)0x4177CFB0, + (q31_t)0x6DE3DC11, (q31_t)0x41A2FC1A, (q31_t)0x6DCA0D14, + (q31_t)0x41CE1E64, (q31_t)0x6DB02D29, (q31_t)0x41F93688, + (q31_t)0x6D963C54, (q31_t)0x42244480, (q31_t)0x6D7C3A98, + (q31_t)0x424F4845, (q31_t)0x6D6227FA, (q31_t)0x427A41D0, + (q31_t)0x6D48047E, (q31_t)0x42A5311A, (q31_t)0x6D2DD027, + (q31_t)0x42D0161E, (q31_t)0x6D138AFA, (q31_t)0x42FAF0D4, + (q31_t)0x6CF934FB, (q31_t)0x4325C135, (q31_t)0x6CDECE2E, + (q31_t)0x4350873C, (q31_t)0x6CC45697, (q31_t)0x437B42E1, + (q31_t)0x6CA9CE3A, (q31_t)0x43A5F41E, (q31_t)0x6C8F351C, + (q31_t)0x43D09AEC, (q31_t)0x6C748B3F, (q31_t)0x43FB3745, + (q31_t)0x6C59D0A9, (q31_t)0x4425C923, (q31_t)0x6C3F055D, + (q31_t)0x4450507E, (q31_t)0x6C242960, (q31_t)0x447ACD50, + (q31_t)0x6C093CB6, (q31_t)0x44A53F93, (q31_t)0x6BEE3F62, + (q31_t)0x44CFA73F, (q31_t)0x6BD3316A, (q31_t)0x44FA044F, + (q31_t)0x6BB812D0, (q31_t)0x452456BC, (q31_t)0x6B9CE39B, + (q31_t)0x454E9E80, (q31_t)0x6B81A3CD, (q31_t)0x4578DB93, + (q31_t)0x6B66536A, (q31_t)0x45A30DF0, (q31_t)0x6B4AF278, + (q31_t)0x45CD358F, (q31_t)0x6B2F80FA, (q31_t)0x45F7526B, + (q31_t)0x6B13FEF5, (q31_t)0x4621647C, (q31_t)0x6AF86C6C, + (q31_t)0x464B6BBD, (q31_t)0x6ADCC964, (q31_t)0x46756827, + (q31_t)0x6AC115E1, (q31_t)0x469F59B4, (q31_t)0x6AA551E8, + (q31_t)0x46C9405C, (q31_t)0x6A897D7D, (q31_t)0x46F31C1A, + (q31_t)0x6A6D98A4, (q31_t)0x471CECE6, (q31_t)0x6A51A361, + (q31_t)0x4746B2BC, (q31_t)0x6A359DB9, (q31_t)0x47706D93, + (q31_t)0x6A1987B0, (q31_t)0x479A1D66, (q31_t)0x69FD614A, + (q31_t)0x47C3C22E, (q31_t)0x69E12A8C, (q31_t)0x47ED5BE6, + (q31_t)0x69C4E37A, (q31_t)0x4816EA85, (q31_t)0x69A88C18, + (q31_t)0x48406E07, (q31_t)0x698C246C, (q31_t)0x4869E664, + (q31_t)0x696FAC78, (q31_t)0x48935397, (q31_t)0x69532442, + (q31_t)0x48BCB598, (q31_t)0x69368BCE, (q31_t)0x48E60C62, + (q31_t)0x6919E320, (q31_t)0x490F57EE, (q31_t)0x68FD2A3D, + (q31_t)0x49389836, (q31_t)0x68E06129, (q31_t)0x4961CD32, + (q31_t)0x68C387E9, (q31_t)0x498AF6DE, (q31_t)0x68A69E81, + (q31_t)0x49B41533, (q31_t)0x6889A4F5, (q31_t)0x49DD282A, + (q31_t)0x686C9B4B, (q31_t)0x4A062FBD, (q31_t)0x684F8186, + (q31_t)0x4A2F2BE5, (q31_t)0x683257AA, (q31_t)0x4A581C9D, + (q31_t)0x68151DBE, (q31_t)0x4A8101DE, (q31_t)0x67F7D3C4, + (q31_t)0x4AA9DBA1, (q31_t)0x67DA79C2, (q31_t)0x4AD2A9E1, + (q31_t)0x67BD0FBC, (q31_t)0x4AFB6C97, (q31_t)0x679F95B7, + (q31_t)0x4B2423BD, (q31_t)0x67820BB6, (q31_t)0x4B4CCF4D, + (q31_t)0x676471C0, (q31_t)0x4B756F3F, (q31_t)0x6746C7D7, + (q31_t)0x4B9E038F, (q31_t)0x67290E02, (q31_t)0x4BC68C36, + (q31_t)0x670B4443, (q31_t)0x4BEF092D, (q31_t)0x66ED6AA1, + (q31_t)0x4C177A6E, (q31_t)0x66CF811F, (q31_t)0x4C3FDFF3, + (q31_t)0x66B187C3, (q31_t)0x4C6839B6, (q31_t)0x66937E90, + (q31_t)0x4C9087B1, (q31_t)0x6675658C, (q31_t)0x4CB8C9DD, + (q31_t)0x66573CBB, (q31_t)0x4CE10034, (q31_t)0x66390422, + (q31_t)0x4D092AB0, (q31_t)0x661ABBC5, (q31_t)0x4D31494B, + (q31_t)0x65FC63A9, (q31_t)0x4D595BFE, (q31_t)0x65DDFBD3, + (q31_t)0x4D8162C4, (q31_t)0x65BF8447, (q31_t)0x4DA95D96, + (q31_t)0x65A0FD0B, (q31_t)0x4DD14C6E, (q31_t)0x65826622, + (q31_t)0x4DF92F45, (q31_t)0x6563BF92, (q31_t)0x4E210617, + (q31_t)0x6545095F, (q31_t)0x4E48D0DC, (q31_t)0x6526438E, + (q31_t)0x4E708F8F, (q31_t)0x65076E24, (q31_t)0x4E984229, + (q31_t)0x64E88926, (q31_t)0x4EBFE8A4, (q31_t)0x64C99498, + (q31_t)0x4EE782FA, (q31_t)0x64AA907F, (q31_t)0x4F0F1126, + (q31_t)0x648B7CDF, (q31_t)0x4F369320, (q31_t)0x646C59BF, + (q31_t)0x4F5E08E3, (q31_t)0x644D2722, (q31_t)0x4F857268, + (q31_t)0x642DE50D, (q31_t)0x4FACCFAB, (q31_t)0x640E9385, + (q31_t)0x4FD420A3, (q31_t)0x63EF328F, (q31_t)0x4FFB654D, + (q31_t)0x63CFC230, (q31_t)0x50229DA0, (q31_t)0x63B0426D, + (q31_t)0x5049C999, (q31_t)0x6390B34A, (q31_t)0x5070E92F, + (q31_t)0x637114CC, (q31_t)0x5097FC5E, (q31_t)0x635166F8, + (q31_t)0x50BF031F, (q31_t)0x6331A9D4, (q31_t)0x50E5FD6C, + (q31_t)0x6311DD63, (q31_t)0x510CEB40, (q31_t)0x62F201AC, + (q31_t)0x5133CC94, (q31_t)0x62D216B2, (q31_t)0x515AA162, + (q31_t)0x62B21C7B, (q31_t)0x518169A4, (q31_t)0x6292130C, + (q31_t)0x51A82555, (q31_t)0x6271FA69, (q31_t)0x51CED46E, + (q31_t)0x6251D297, (q31_t)0x51F576E9, (q31_t)0x62319B9D, + (q31_t)0x521C0CC1, (q31_t)0x6211557D, (q31_t)0x524295EF, + (q31_t)0x61F1003E, (q31_t)0x5269126E, (q31_t)0x61D09BE5, + (q31_t)0x528F8237, (q31_t)0x61B02876, (q31_t)0x52B5E545, + (q31_t)0x618FA5F6, (q31_t)0x52DC3B92, (q31_t)0x616F146B, + (q31_t)0x53028517, (q31_t)0x614E73D9, (q31_t)0x5328C1D0, + (q31_t)0x612DC446, (q31_t)0x534EF1B5, (q31_t)0x610D05B7, + (q31_t)0x537514C1, (q31_t)0x60EC3830, (q31_t)0x539B2AEF, + (q31_t)0x60CB5BB6, (q31_t)0x53C13438, (q31_t)0x60AA704F, + (q31_t)0x53E73097, (q31_t)0x60897600, (q31_t)0x540D2005, + (q31_t)0x60686CCE, (q31_t)0x5433027D, (q31_t)0x604754BE, + (q31_t)0x5458D7F9, (q31_t)0x60262DD5, (q31_t)0x547EA073, + (q31_t)0x6004F818, (q31_t)0x54A45BE5, (q31_t)0x5FE3B38D, + (q31_t)0x54CA0A4A, (q31_t)0x5FC26038, (q31_t)0x54EFAB9C, + (q31_t)0x5FA0FE1E, (q31_t)0x55153FD4, (q31_t)0x5F7F8D46, + (q31_t)0x553AC6ED, (q31_t)0x5F5E0DB3, (q31_t)0x556040E2, + (q31_t)0x5F3C7F6B, (q31_t)0x5585ADAC, (q31_t)0x5F1AE273, + (q31_t)0x55AB0D46, (q31_t)0x5EF936D1, (q31_t)0x55D05FAA, + (q31_t)0x5ED77C89, (q31_t)0x55F5A4D2, (q31_t)0x5EB5B3A1, + (q31_t)0x561ADCB8, (q31_t)0x5E93DC1F, (q31_t)0x56400757, + (q31_t)0x5E71F606, (q31_t)0x566524AA, (q31_t)0x5E50015D, + (q31_t)0x568A34A9, (q31_t)0x5E2DFE28, (q31_t)0x56AF3750, + (q31_t)0x5E0BEC6E, (q31_t)0x56D42C99, (q31_t)0x5DE9CC32, + (q31_t)0x56F9147E, (q31_t)0x5DC79D7C, (q31_t)0x571DEEF9, + (q31_t)0x5DA5604E, (q31_t)0x5742BC05, (q31_t)0x5D8314B0, + (q31_t)0x57677B9D, (q31_t)0x5D60BAA6, (q31_t)0x578C2DB9, + (q31_t)0x5D3E5236, (q31_t)0x57B0D256, (q31_t)0x5D1BDB65, + (q31_t)0x57D5696C, (q31_t)0x5CF95638, (q31_t)0x57F9F2F7, + (q31_t)0x5CD6C2B4, (q31_t)0x581E6EF1, (q31_t)0x5CB420DF, + (q31_t)0x5842DD54, (q31_t)0x5C9170BF, (q31_t)0x58673E1B, + (q31_t)0x5C6EB258, (q31_t)0x588B913F, (q31_t)0x5C4BE5B0, + (q31_t)0x58AFD6BC, (q31_t)0x5C290ACC, (q31_t)0x58D40E8C, + (q31_t)0x5C0621B2, (q31_t)0x58F838A9, (q31_t)0x5BE32A67, + (q31_t)0x591C550E, (q31_t)0x5BC024F0, (q31_t)0x594063B4, + (q31_t)0x5B9D1153, (q31_t)0x59646497, (q31_t)0x5B79EF96, + (q31_t)0x598857B1, (q31_t)0x5B56BFBD, (q31_t)0x59AC3CFD, + (q31_t)0x5B3381CE, (q31_t)0x59D01474, (q31_t)0x5B1035CF, + (q31_t)0x59F3DE12, (q31_t)0x5AECDBC4, (q31_t)0x5A1799D0, + (q31_t)0x5AC973B4, (q31_t)0x5A3B47AA, (q31_t)0x5AA5FDA4, + (q31_t)0x5A5EE79A, (q31_t)0x5A82799A, (q31_t)0x5A82799A, + (q31_t)0x5A5EE79A, (q31_t)0x5AA5FDA4, (q31_t)0x5A3B47AA, + (q31_t)0x5AC973B4, (q31_t)0x5A1799D0, (q31_t)0x5AECDBC4, + (q31_t)0x59F3DE12, (q31_t)0x5B1035CF, (q31_t)0x59D01474, + (q31_t)0x5B3381CE, (q31_t)0x59AC3CFD, (q31_t)0x5B56BFBD, + (q31_t)0x598857B1, (q31_t)0x5B79EF96, (q31_t)0x59646497, + (q31_t)0x5B9D1153, (q31_t)0x594063B4, (q31_t)0x5BC024F0, + (q31_t)0x591C550E, (q31_t)0x5BE32A67, (q31_t)0x58F838A9, + (q31_t)0x5C0621B2, (q31_t)0x58D40E8C, (q31_t)0x5C290ACC, + (q31_t)0x58AFD6BC, (q31_t)0x5C4BE5B0, (q31_t)0x588B913F, + (q31_t)0x5C6EB258, (q31_t)0x58673E1B, (q31_t)0x5C9170BF, + (q31_t)0x5842DD54, (q31_t)0x5CB420DF, (q31_t)0x581E6EF1, + (q31_t)0x5CD6C2B4, (q31_t)0x57F9F2F7, (q31_t)0x5CF95638, + (q31_t)0x57D5696C, (q31_t)0x5D1BDB65, (q31_t)0x57B0D256, + (q31_t)0x5D3E5236, (q31_t)0x578C2DB9, (q31_t)0x5D60BAA6, + (q31_t)0x57677B9D, (q31_t)0x5D8314B0, (q31_t)0x5742BC05, + (q31_t)0x5DA5604E, (q31_t)0x571DEEF9, (q31_t)0x5DC79D7C, + (q31_t)0x56F9147E, (q31_t)0x5DE9CC32, (q31_t)0x56D42C99, + (q31_t)0x5E0BEC6E, (q31_t)0x56AF3750, (q31_t)0x5E2DFE28, + (q31_t)0x568A34A9, (q31_t)0x5E50015D, (q31_t)0x566524AA, + (q31_t)0x5E71F606, (q31_t)0x56400757, (q31_t)0x5E93DC1F, + (q31_t)0x561ADCB8, (q31_t)0x5EB5B3A1, (q31_t)0x55F5A4D2, + (q31_t)0x5ED77C89, (q31_t)0x55D05FAA, (q31_t)0x5EF936D1, + (q31_t)0x55AB0D46, (q31_t)0x5F1AE273, (q31_t)0x5585ADAC, + (q31_t)0x5F3C7F6B, (q31_t)0x556040E2, (q31_t)0x5F5E0DB3, + (q31_t)0x553AC6ED, (q31_t)0x5F7F8D46, (q31_t)0x55153FD4, + (q31_t)0x5FA0FE1E, (q31_t)0x54EFAB9C, (q31_t)0x5FC26038, + (q31_t)0x54CA0A4A, (q31_t)0x5FE3B38D, (q31_t)0x54A45BE5, + (q31_t)0x6004F818, (q31_t)0x547EA073, (q31_t)0x60262DD5, + (q31_t)0x5458D7F9, (q31_t)0x604754BE, (q31_t)0x5433027D, + (q31_t)0x60686CCE, (q31_t)0x540D2005, (q31_t)0x60897600, + (q31_t)0x53E73097, (q31_t)0x60AA704F, (q31_t)0x53C13438, + (q31_t)0x60CB5BB6, (q31_t)0x539B2AEF, (q31_t)0x60EC3830, + (q31_t)0x537514C1, (q31_t)0x610D05B7, (q31_t)0x534EF1B5, + (q31_t)0x612DC446, (q31_t)0x5328C1D0, (q31_t)0x614E73D9, + (q31_t)0x53028517, (q31_t)0x616F146B, (q31_t)0x52DC3B92, + (q31_t)0x618FA5F6, (q31_t)0x52B5E545, (q31_t)0x61B02876, + (q31_t)0x528F8237, (q31_t)0x61D09BE5, (q31_t)0x5269126E, + (q31_t)0x61F1003E, (q31_t)0x524295EF, (q31_t)0x6211557D, + (q31_t)0x521C0CC1, (q31_t)0x62319B9D, (q31_t)0x51F576E9, + (q31_t)0x6251D297, (q31_t)0x51CED46E, (q31_t)0x6271FA69, + (q31_t)0x51A82555, (q31_t)0x6292130C, (q31_t)0x518169A4, + (q31_t)0x62B21C7B, (q31_t)0x515AA162, (q31_t)0x62D216B2, + (q31_t)0x5133CC94, (q31_t)0x62F201AC, (q31_t)0x510CEB40, + (q31_t)0x6311DD63, (q31_t)0x50E5FD6C, (q31_t)0x6331A9D4, + (q31_t)0x50BF031F, (q31_t)0x635166F8, (q31_t)0x5097FC5E, + (q31_t)0x637114CC, (q31_t)0x5070E92F, (q31_t)0x6390B34A, + (q31_t)0x5049C999, (q31_t)0x63B0426D, (q31_t)0x50229DA0, + (q31_t)0x63CFC230, (q31_t)0x4FFB654D, (q31_t)0x63EF328F, + (q31_t)0x4FD420A3, (q31_t)0x640E9385, (q31_t)0x4FACCFAB, + (q31_t)0x642DE50D, (q31_t)0x4F857268, (q31_t)0x644D2722, + (q31_t)0x4F5E08E3, (q31_t)0x646C59BF, (q31_t)0x4F369320, + (q31_t)0x648B7CDF, (q31_t)0x4F0F1126, (q31_t)0x64AA907F, + (q31_t)0x4EE782FA, (q31_t)0x64C99498, (q31_t)0x4EBFE8A4, + (q31_t)0x64E88926, (q31_t)0x4E984229, (q31_t)0x65076E24, + (q31_t)0x4E708F8F, (q31_t)0x6526438E, (q31_t)0x4E48D0DC, + (q31_t)0x6545095F, (q31_t)0x4E210617, (q31_t)0x6563BF92, + (q31_t)0x4DF92F45, (q31_t)0x65826622, (q31_t)0x4DD14C6E, + (q31_t)0x65A0FD0B, (q31_t)0x4DA95D96, (q31_t)0x65BF8447, + (q31_t)0x4D8162C4, (q31_t)0x65DDFBD3, (q31_t)0x4D595BFE, + (q31_t)0x65FC63A9, (q31_t)0x4D31494B, (q31_t)0x661ABBC5, + (q31_t)0x4D092AB0, (q31_t)0x66390422, (q31_t)0x4CE10034, + (q31_t)0x66573CBB, (q31_t)0x4CB8C9DD, (q31_t)0x6675658C, + (q31_t)0x4C9087B1, (q31_t)0x66937E90, (q31_t)0x4C6839B6, + (q31_t)0x66B187C3, (q31_t)0x4C3FDFF3, (q31_t)0x66CF811F, + (q31_t)0x4C177A6E, (q31_t)0x66ED6AA1, (q31_t)0x4BEF092D, + (q31_t)0x670B4443, (q31_t)0x4BC68C36, (q31_t)0x67290E02, + (q31_t)0x4B9E038F, (q31_t)0x6746C7D7, (q31_t)0x4B756F3F, + (q31_t)0x676471C0, (q31_t)0x4B4CCF4D, (q31_t)0x67820BB6, + (q31_t)0x4B2423BD, (q31_t)0x679F95B7, (q31_t)0x4AFB6C97, + (q31_t)0x67BD0FBC, (q31_t)0x4AD2A9E1, (q31_t)0x67DA79C2, + (q31_t)0x4AA9DBA1, (q31_t)0x67F7D3C4, (q31_t)0x4A8101DE, + (q31_t)0x68151DBE, (q31_t)0x4A581C9D, (q31_t)0x683257AA, + (q31_t)0x4A2F2BE5, (q31_t)0x684F8186, (q31_t)0x4A062FBD, + (q31_t)0x686C9B4B, (q31_t)0x49DD282A, (q31_t)0x6889A4F5, + (q31_t)0x49B41533, (q31_t)0x68A69E81, (q31_t)0x498AF6DE, + (q31_t)0x68C387E9, (q31_t)0x4961CD32, (q31_t)0x68E06129, + (q31_t)0x49389836, (q31_t)0x68FD2A3D, (q31_t)0x490F57EE, + (q31_t)0x6919E320, (q31_t)0x48E60C62, (q31_t)0x69368BCE, + (q31_t)0x48BCB598, (q31_t)0x69532442, (q31_t)0x48935397, + (q31_t)0x696FAC78, (q31_t)0x4869E664, (q31_t)0x698C246C, + (q31_t)0x48406E07, (q31_t)0x69A88C18, (q31_t)0x4816EA85, + (q31_t)0x69C4E37A, (q31_t)0x47ED5BE6, (q31_t)0x69E12A8C, + (q31_t)0x47C3C22E, (q31_t)0x69FD614A, (q31_t)0x479A1D66, + (q31_t)0x6A1987B0, (q31_t)0x47706D93, (q31_t)0x6A359DB9, + (q31_t)0x4746B2BC, (q31_t)0x6A51A361, (q31_t)0x471CECE6, + (q31_t)0x6A6D98A4, (q31_t)0x46F31C1A, (q31_t)0x6A897D7D, + (q31_t)0x46C9405C, (q31_t)0x6AA551E8, (q31_t)0x469F59B4, + (q31_t)0x6AC115E1, (q31_t)0x46756827, (q31_t)0x6ADCC964, + (q31_t)0x464B6BBD, (q31_t)0x6AF86C6C, (q31_t)0x4621647C, + (q31_t)0x6B13FEF5, (q31_t)0x45F7526B, (q31_t)0x6B2F80FA, + (q31_t)0x45CD358F, (q31_t)0x6B4AF278, (q31_t)0x45A30DF0, + (q31_t)0x6B66536A, (q31_t)0x4578DB93, (q31_t)0x6B81A3CD, + (q31_t)0x454E9E80, (q31_t)0x6B9CE39B, (q31_t)0x452456BC, + (q31_t)0x6BB812D0, (q31_t)0x44FA044F, (q31_t)0x6BD3316A, + (q31_t)0x44CFA73F, (q31_t)0x6BEE3F62, (q31_t)0x44A53F93, + (q31_t)0x6C093CB6, (q31_t)0x447ACD50, (q31_t)0x6C242960, + (q31_t)0x4450507E, (q31_t)0x6C3F055D, (q31_t)0x4425C923, + (q31_t)0x6C59D0A9, (q31_t)0x43FB3745, (q31_t)0x6C748B3F, + (q31_t)0x43D09AEC, (q31_t)0x6C8F351C, (q31_t)0x43A5F41E, + (q31_t)0x6CA9CE3A, (q31_t)0x437B42E1, (q31_t)0x6CC45697, + (q31_t)0x4350873C, (q31_t)0x6CDECE2E, (q31_t)0x4325C135, + (q31_t)0x6CF934FB, (q31_t)0x42FAF0D4, (q31_t)0x6D138AFA, + (q31_t)0x42D0161E, (q31_t)0x6D2DD027, (q31_t)0x42A5311A, + (q31_t)0x6D48047E, (q31_t)0x427A41D0, (q31_t)0x6D6227FA, + (q31_t)0x424F4845, (q31_t)0x6D7C3A98, (q31_t)0x42244480, + (q31_t)0x6D963C54, (q31_t)0x41F93688, (q31_t)0x6DB02D29, + (q31_t)0x41CE1E64, (q31_t)0x6DCA0D14, (q31_t)0x41A2FC1A, + (q31_t)0x6DE3DC11, (q31_t)0x4177CFB0, (q31_t)0x6DFD9A1B, + (q31_t)0x414C992E, (q31_t)0x6E17472F, (q31_t)0x4121589A, + (q31_t)0x6E30E349, (q31_t)0x40F60DFB, (q31_t)0x6E4A6E65, + (q31_t)0x40CAB957, (q31_t)0x6E63E87F, (q31_t)0x409F5AB6, + (q31_t)0x6E7D5193, (q31_t)0x4073F21D, (q31_t)0x6E96A99C, + (q31_t)0x40487F93, (q31_t)0x6EAFF098, (q31_t)0x401D0320, + (q31_t)0x6EC92682, (q31_t)0x3FF17CCA, (q31_t)0x6EE24B57, + (q31_t)0x3FC5EC97, (q31_t)0x6EFB5F12, (q31_t)0x3F9A528F, + (q31_t)0x6F1461AF, (q31_t)0x3F6EAEB8, (q31_t)0x6F2D532C, + (q31_t)0x3F430118, (q31_t)0x6F463383, (q31_t)0x3F1749B7, + (q31_t)0x6F5F02B1, (q31_t)0x3EEB889C, (q31_t)0x6F77C0B3, + (q31_t)0x3EBFBDCC, (q31_t)0x6F906D84, (q31_t)0x3E93E94F, + (q31_t)0x6FA90920, (q31_t)0x3E680B2C, (q31_t)0x6FC19385, + (q31_t)0x3E3C2369, (q31_t)0x6FDA0CAD, (q31_t)0x3E10320D, + (q31_t)0x6FF27496, (q31_t)0x3DE4371F, (q31_t)0x700ACB3B, + (q31_t)0x3DB832A5, (q31_t)0x70231099, (q31_t)0x3D8C24A7, + (q31_t)0x703B44AC, (q31_t)0x3D600D2B, (q31_t)0x70536771, + (q31_t)0x3D33EC39, (q31_t)0x706B78E3, (q31_t)0x3D07C1D5, + (q31_t)0x708378FE, (q31_t)0x3CDB8E09, (q31_t)0x709B67C0, + (q31_t)0x3CAF50DA, (q31_t)0x70B34524, (q31_t)0x3C830A4F, + (q31_t)0x70CB1127, (q31_t)0x3C56BA70, (q31_t)0x70E2CBC6, + (q31_t)0x3C2A6142, (q31_t)0x70FA74FB, (q31_t)0x3BFDFECD, + (q31_t)0x71120CC5, (q31_t)0x3BD19317, (q31_t)0x7129931E, + (q31_t)0x3BA51E29, (q31_t)0x71410804, (q31_t)0x3B78A007, + (q31_t)0x71586B73, (q31_t)0x3B4C18BA, (q31_t)0x716FBD68, + (q31_t)0x3B1F8847, (q31_t)0x7186FDDE, (q31_t)0x3AF2EEB7, + (q31_t)0x719E2CD2, (q31_t)0x3AC64C0F, (q31_t)0x71B54A40, + (q31_t)0x3A99A057, (q31_t)0x71CC5626, (q31_t)0x3A6CEB95, + (q31_t)0x71E3507F, (q31_t)0x3A402DD1, (q31_t)0x71FA3948, + (q31_t)0x3A136712, (q31_t)0x7211107D, (q31_t)0x39E6975D, + (q31_t)0x7227D61C, (q31_t)0x39B9BEBB, (q31_t)0x723E8A1F, + (q31_t)0x398CDD32, (q31_t)0x72552C84, (q31_t)0x395FF2C9, + (q31_t)0x726BBD48, (q31_t)0x3932FF87, (q31_t)0x72823C66, + (q31_t)0x39060372, (q31_t)0x7298A9DC, (q31_t)0x38D8FE93, + (q31_t)0x72AF05A6, (q31_t)0x38ABF0EF, (q31_t)0x72C54FC0, + (q31_t)0x387EDA8E, (q31_t)0x72DB8828, (q31_t)0x3851BB76, + (q31_t)0x72F1AED8, (q31_t)0x382493B0, (q31_t)0x7307C3D0, + (q31_t)0x37F76340, (q31_t)0x731DC709, (q31_t)0x37CA2A30, + (q31_t)0x7333B883, (q31_t)0x379CE884, (q31_t)0x73499838, + (q31_t)0x376F9E46, (q31_t)0x735F6626, (q31_t)0x37424B7A, + (q31_t)0x73752249, (q31_t)0x3714F02A, (q31_t)0x738ACC9E, + (q31_t)0x36E78C5A, (q31_t)0x73A06522, (q31_t)0x36BA2013, + (q31_t)0x73B5EBD0, (q31_t)0x368CAB5C, (q31_t)0x73CB60A7, + (q31_t)0x365F2E3B, (q31_t)0x73E0C3A3, (q31_t)0x3631A8B7, + (q31_t)0x73F614C0, (q31_t)0x36041AD9, (q31_t)0x740B53FA, + (q31_t)0x35D684A5, (q31_t)0x74208150, (q31_t)0x35A8E624, + (q31_t)0x74359CBD, (q31_t)0x357B3F5D, (q31_t)0x744AA63E, + (q31_t)0x354D9056, (q31_t)0x745F9DD1, (q31_t)0x351FD917, + (q31_t)0x74748371, (q31_t)0x34F219A7, (q31_t)0x7489571B, + (q31_t)0x34C4520D, (q31_t)0x749E18CD, (q31_t)0x3496824F, + (q31_t)0x74B2C883, (q31_t)0x3468AA76, (q31_t)0x74C7663A, + (q31_t)0x343ACA87, (q31_t)0x74DBF1EF, (q31_t)0x340CE28A, + (q31_t)0x74F06B9E, (q31_t)0x33DEF287, (q31_t)0x7504D345, + (q31_t)0x33B0FA84, (q31_t)0x751928E0, (q31_t)0x3382FA88, + (q31_t)0x752D6C6C, (q31_t)0x3354F29A, (q31_t)0x75419DE6, + (q31_t)0x3326E2C2, (q31_t)0x7555BD4B, (q31_t)0x32F8CB07, + (q31_t)0x7569CA98, (q31_t)0x32CAAB6F, (q31_t)0x757DC5CA, + (q31_t)0x329C8402, (q31_t)0x7591AEDD, (q31_t)0x326E54C7, + (q31_t)0x75A585CF, (q31_t)0x32401DC5, (q31_t)0x75B94A9C, + (q31_t)0x3211DF03, (q31_t)0x75CCFD42, (q31_t)0x31E39889, + (q31_t)0x75E09DBD, (q31_t)0x31B54A5D, (q31_t)0x75F42C0A, + (q31_t)0x3186F487, (q31_t)0x7607A827, (q31_t)0x3158970D, + (q31_t)0x761B1211, (q31_t)0x312A31F8, (q31_t)0x762E69C3, + (q31_t)0x30FBC54D, (q31_t)0x7641AF3C, (q31_t)0x30CD5114, + (q31_t)0x7654E279, (q31_t)0x309ED555, (q31_t)0x76680376, + (q31_t)0x30705217, (q31_t)0x767B1230, (q31_t)0x3041C760, + (q31_t)0x768E0EA5, (q31_t)0x30133538, (q31_t)0x76A0F8D2, + (q31_t)0x2FE49BA6, (q31_t)0x76B3D0B3, (q31_t)0x2FB5FAB2, + (q31_t)0x76C69646, (q31_t)0x2F875262, (q31_t)0x76D94988, + (q31_t)0x2F58A2BD, (q31_t)0x76EBEA77, (q31_t)0x2F29EBCC, + (q31_t)0x76FE790E, (q31_t)0x2EFB2D94, (q31_t)0x7710F54B, + (q31_t)0x2ECC681E, (q31_t)0x77235F2D, (q31_t)0x2E9D9B70, + (q31_t)0x7735B6AE, (q31_t)0x2E6EC792, (q31_t)0x7747FBCE, + (q31_t)0x2E3FEC8B, (q31_t)0x775A2E88, (q31_t)0x2E110A62, + (q31_t)0x776C4EDB, (q31_t)0x2DE2211E, (q31_t)0x777E5CC3, + (q31_t)0x2DB330C7, (q31_t)0x7790583D, (q31_t)0x2D843963, + (q31_t)0x77A24148, (q31_t)0x2D553AFB, (q31_t)0x77B417DF, + (q31_t)0x2D263595, (q31_t)0x77C5DC01, (q31_t)0x2CF72939, + (q31_t)0x77D78DAA, (q31_t)0x2CC815ED, (q31_t)0x77E92CD8, + (q31_t)0x2C98FBBA, (q31_t)0x77FAB988, (q31_t)0x2C69DAA6, + (q31_t)0x780C33B8, (q31_t)0x2C3AB2B9, (q31_t)0x781D9B64, + (q31_t)0x2C0B83F9, (q31_t)0x782EF08B, (q31_t)0x2BDC4E6F, + (q31_t)0x78403328, (q31_t)0x2BAD1221, (q31_t)0x7851633B, + (q31_t)0x2B7DCF17, (q31_t)0x786280BF, (q31_t)0x2B4E8558, + (q31_t)0x78738BB3, (q31_t)0x2B1F34EB, (q31_t)0x78848413, + (q31_t)0x2AEFDDD8, (q31_t)0x789569DE, (q31_t)0x2AC08025, + (q31_t)0x78A63D10, (q31_t)0x2A911BDB, (q31_t)0x78B6FDA8, + (q31_t)0x2A61B101, (q31_t)0x78C7ABA1, (q31_t)0x2A323F9D, + (q31_t)0x78D846FB, (q31_t)0x2A02C7B8, (q31_t)0x78E8CFB1, + (q31_t)0x29D34958, (q31_t)0x78F945C3, (q31_t)0x29A3C484, + (q31_t)0x7909A92C, (q31_t)0x29743945, (q31_t)0x7919F9EB, + (q31_t)0x2944A7A2, (q31_t)0x792A37FE, (q31_t)0x29150FA1, + (q31_t)0x793A6360, (q31_t)0x28E5714A, (q31_t)0x794A7C11, + (q31_t)0x28B5CCA5, (q31_t)0x795A820E, (q31_t)0x288621B9, + (q31_t)0x796A7554, (q31_t)0x2856708C, (q31_t)0x797A55E0, + (q31_t)0x2826B928, (q31_t)0x798A23B1, (q31_t)0x27F6FB92, + (q31_t)0x7999DEC3, (q31_t)0x27C737D2, (q31_t)0x79A98715, + (q31_t)0x27976DF1, (q31_t)0x79B91CA4, (q31_t)0x27679DF4, + (q31_t)0x79C89F6D, (q31_t)0x2737C7E3, (q31_t)0x79D80F6F, + (q31_t)0x2707EBC6, (q31_t)0x79E76CA6, (q31_t)0x26D809A5, + (q31_t)0x79F6B711, (q31_t)0x26A82185, (q31_t)0x7A05EEAD, + (q31_t)0x26783370, (q31_t)0x7A151377, (q31_t)0x26483F6C, + (q31_t)0x7A24256E, (q31_t)0x26184581, (q31_t)0x7A33248F, + (q31_t)0x25E845B5, (q31_t)0x7A4210D8, (q31_t)0x25B84012, + (q31_t)0x7A50EA46, (q31_t)0x2588349D, (q31_t)0x7A5FB0D8, + (q31_t)0x2558235E, (q31_t)0x7A6E648A, (q31_t)0x25280C5D, + (q31_t)0x7A7D055B, (q31_t)0x24F7EFA1, (q31_t)0x7A8B9348, + (q31_t)0x24C7CD32, (q31_t)0x7A9A0E4F, (q31_t)0x2497A517, + (q31_t)0x7AA8766E, (q31_t)0x24677757, (q31_t)0x7AB6CBA3, + (q31_t)0x243743FA, (q31_t)0x7AC50DEB, (q31_t)0x24070B07, + (q31_t)0x7AD33D45, (q31_t)0x23D6CC86, (q31_t)0x7AE159AE, + (q31_t)0x23A6887E, (q31_t)0x7AEF6323, (q31_t)0x23763EF7, + (q31_t)0x7AFD59A3, (q31_t)0x2345EFF7, (q31_t)0x7B0B3D2C, + (q31_t)0x23159B87, (q31_t)0x7B190DBB, (q31_t)0x22E541AE, + (q31_t)0x7B26CB4F, (q31_t)0x22B4E274, (q31_t)0x7B3475E4, + (q31_t)0x22847DDF, (q31_t)0x7B420D7A, (q31_t)0x225413F8, + (q31_t)0x7B4F920E, (q31_t)0x2223A4C5, (q31_t)0x7B5D039D, + (q31_t)0x21F3304E, (q31_t)0x7B6A6227, (q31_t)0x21C2B69C, + (q31_t)0x7B77ADA8, (q31_t)0x219237B4, (q31_t)0x7B84E61E, + (q31_t)0x2161B39F, (q31_t)0x7B920B89, (q31_t)0x21312A65, + (q31_t)0x7B9F1DE5, (q31_t)0x21009C0B, (q31_t)0x7BAC1D31, + (q31_t)0x20D0089B, (q31_t)0x7BB9096A, (q31_t)0x209F701C, + (q31_t)0x7BC5E28F, (q31_t)0x206ED295, (q31_t)0x7BD2A89E, + (q31_t)0x203E300D, (q31_t)0x7BDF5B94, (q31_t)0x200D888C, + (q31_t)0x7BEBFB70, (q31_t)0x1FDCDC1A, (q31_t)0x7BF88830, + (q31_t)0x1FAC2ABF, (q31_t)0x7C0501D1, (q31_t)0x1F7B7480, + (q31_t)0x7C116853, (q31_t)0x1F4AB967, (q31_t)0x7C1DBBB2, + (q31_t)0x1F19F97B, (q31_t)0x7C29FBEE, (q31_t)0x1EE934C2, + (q31_t)0x7C362904, (q31_t)0x1EB86B46, (q31_t)0x7C4242F2, + (q31_t)0x1E879D0C, (q31_t)0x7C4E49B6, (q31_t)0x1E56CA1E, + (q31_t)0x7C5A3D4F, (q31_t)0x1E25F281, (q31_t)0x7C661DBB, + (q31_t)0x1DF5163F, (q31_t)0x7C71EAF8, (q31_t)0x1DC4355D, + (q31_t)0x7C7DA504, (q31_t)0x1D934FE5, (q31_t)0x7C894BDD, + (q31_t)0x1D6265DD, (q31_t)0x7C94DF82, (q31_t)0x1D31774D, + (q31_t)0x7CA05FF1, (q31_t)0x1D00843C, (q31_t)0x7CABCD27, + (q31_t)0x1CCF8CB3, (q31_t)0x7CB72724, (q31_t)0x1C9E90B8, + (q31_t)0x7CC26DE5, (q31_t)0x1C6D9053, (q31_t)0x7CCDA168, + (q31_t)0x1C3C8B8C, (q31_t)0x7CD8C1AD, (q31_t)0x1C0B826A, + (q31_t)0x7CE3CEB1, (q31_t)0x1BDA74F5, (q31_t)0x7CEEC873, + (q31_t)0x1BA96334, (q31_t)0x7CF9AEF0, (q31_t)0x1B784D30, + (q31_t)0x7D048228, (q31_t)0x1B4732EF, (q31_t)0x7D0F4218, + (q31_t)0x1B161479, (q31_t)0x7D19EEBE, (q31_t)0x1AE4F1D6, + (q31_t)0x7D24881A, (q31_t)0x1AB3CB0C, (q31_t)0x7D2F0E2A, + (q31_t)0x1A82A025, (q31_t)0x7D3980EC, (q31_t)0x1A517127, + (q31_t)0x7D43E05E, (q31_t)0x1A203E1B, (q31_t)0x7D4E2C7E, + (q31_t)0x19EF0706, (q31_t)0x7D58654C, (q31_t)0x19BDCBF2, + (q31_t)0x7D628AC5, (q31_t)0x198C8CE6, (q31_t)0x7D6C9CE9, + (q31_t)0x195B49E9, (q31_t)0x7D769BB5, (q31_t)0x192A0303, + (q31_t)0x7D808727, (q31_t)0x18F8B83C, (q31_t)0x7D8A5F3F, + (q31_t)0x18C7699B, (q31_t)0x7D9423FB, (q31_t)0x18961727, + (q31_t)0x7D9DD55A, (q31_t)0x1864C0E9, (q31_t)0x7DA77359, + (q31_t)0x183366E8, (q31_t)0x7DB0FDF7, (q31_t)0x1802092C, + (q31_t)0x7DBA7534, (q31_t)0x17D0A7BB, (q31_t)0x7DC3D90D, + (q31_t)0x179F429F, (q31_t)0x7DCD2981, (q31_t)0x176DD9DE, + (q31_t)0x7DD6668E, (q31_t)0x173C6D80, (q31_t)0x7DDF9034, + (q31_t)0x170AFD8D, (q31_t)0x7DE8A670, (q31_t)0x16D98A0C, + (q31_t)0x7DF1A942, (q31_t)0x16A81305, (q31_t)0x7DFA98A7, + (q31_t)0x1676987F, (q31_t)0x7E03749F, (q31_t)0x16451A83, + (q31_t)0x7E0C3D29, (q31_t)0x16139917, (q31_t)0x7E14F242, + (q31_t)0x15E21444, (q31_t)0x7E1D93E9, (q31_t)0x15B08C11, + (q31_t)0x7E26221E, (q31_t)0x157F0086, (q31_t)0x7E2E9CDF, + (q31_t)0x154D71AA, (q31_t)0x7E37042A, (q31_t)0x151BDF85, + (q31_t)0x7E3F57FE, (q31_t)0x14EA4A1F, (q31_t)0x7E47985B, + (q31_t)0x14B8B17F, (q31_t)0x7E4FC53E, (q31_t)0x148715AD, + (q31_t)0x7E57DEA6, (q31_t)0x145576B1, (q31_t)0x7E5FE493, + (q31_t)0x1423D492, (q31_t)0x7E67D702, (q31_t)0x13F22F57, + (q31_t)0x7E6FB5F3, (q31_t)0x13C0870A, (q31_t)0x7E778165, + (q31_t)0x138EDBB0, (q31_t)0x7E7F3956, (q31_t)0x135D2D53, + (q31_t)0x7E86DDC5, (q31_t)0x132B7BF9, (q31_t)0x7E8E6EB1, + (q31_t)0x12F9C7AA, (q31_t)0x7E95EC19, (q31_t)0x12C8106E, + (q31_t)0x7E9D55FC, (q31_t)0x1296564D, (q31_t)0x7EA4AC58, + (q31_t)0x1264994E, (q31_t)0x7EABEF2C, (q31_t)0x1232D978, + (q31_t)0x7EB31E77, (q31_t)0x120116D4, (q31_t)0x7EBA3A39, + (q31_t)0x11CF516A, (q31_t)0x7EC1426F, (q31_t)0x119D8940, + (q31_t)0x7EC8371A, (q31_t)0x116BBE5F, (q31_t)0x7ECF1837, + (q31_t)0x1139F0CE, (q31_t)0x7ED5E5C6, (q31_t)0x11082096, + (q31_t)0x7EDC9FC6, (q31_t)0x10D64DBC, (q31_t)0x7EE34635, + (q31_t)0x10A4784A, (q31_t)0x7EE9D913, (q31_t)0x1072A047, + (q31_t)0x7EF0585F, (q31_t)0x1040C5BB, (q31_t)0x7EF6C418, + (q31_t)0x100EE8AD, (q31_t)0x7EFD1C3C, (q31_t)0x0FDD0925, + (q31_t)0x7F0360CB, (q31_t)0x0FAB272B, (q31_t)0x7F0991C3, + (q31_t)0x0F7942C6, (q31_t)0x7F0FAF24, (q31_t)0x0F475BFE, + (q31_t)0x7F15B8EE, (q31_t)0x0F1572DC, (q31_t)0x7F1BAF1E, + (q31_t)0x0EE38765, (q31_t)0x7F2191B4, (q31_t)0x0EB199A3, + (q31_t)0x7F2760AF, (q31_t)0x0E7FA99D, (q31_t)0x7F2D1C0E, + (q31_t)0x0E4DB75B, (q31_t)0x7F32C3D0, (q31_t)0x0E1BC2E3, + (q31_t)0x7F3857F5, (q31_t)0x0DE9CC3F, (q31_t)0x7F3DD87C, + (q31_t)0x0DB7D376, (q31_t)0x7F434563, (q31_t)0x0D85D88F, + (q31_t)0x7F489EAA, (q31_t)0x0D53DB92, (q31_t)0x7F4DE450, + (q31_t)0x0D21DC87, (q31_t)0x7F531654, (q31_t)0x0CEFDB75, + (q31_t)0x7F5834B6, (q31_t)0x0CBDD865, (q31_t)0x7F5D3F75, + (q31_t)0x0C8BD35E, (q31_t)0x7F62368F, (q31_t)0x0C59CC67, + (q31_t)0x7F671A04, (q31_t)0x0C27C389, (q31_t)0x7F6BE9D4, + (q31_t)0x0BF5B8CB, (q31_t)0x7F70A5FD, (q31_t)0x0BC3AC35, + (q31_t)0x7F754E7F, (q31_t)0x0B919DCE, (q31_t)0x7F79E35A, + (q31_t)0x0B5F8D9F, (q31_t)0x7F7E648B, (q31_t)0x0B2D7BAE, + (q31_t)0x7F82D214, (q31_t)0x0AFB6805, (q31_t)0x7F872BF3, + (q31_t)0x0AC952AA, (q31_t)0x7F8B7226, (q31_t)0x0A973BA5, + (q31_t)0x7F8FA4AF, (q31_t)0x0A6522FE, (q31_t)0x7F93C38C, + (q31_t)0x0A3308BC, (q31_t)0x7F97CEBC, (q31_t)0x0A00ECE8, + (q31_t)0x7F9BC63F, (q31_t)0x09CECF89, (q31_t)0x7F9FAA15, + (q31_t)0x099CB0A7, (q31_t)0x7FA37A3C, (q31_t)0x096A9049, + (q31_t)0x7FA736B4, (q31_t)0x09386E77, (q31_t)0x7FAADF7C, + (q31_t)0x09064B3A, (q31_t)0x7FAE7494, (q31_t)0x08D42698, + (q31_t)0x7FB1F5FC, (q31_t)0x08A2009A, (q31_t)0x7FB563B2, + (q31_t)0x086FD947, (q31_t)0x7FB8BDB7, (q31_t)0x083DB0A7, + (q31_t)0x7FBC040A, (q31_t)0x080B86C1, (q31_t)0x7FBF36A9, + (q31_t)0x07D95B9E, (q31_t)0x7FC25596, (q31_t)0x07A72F45, + (q31_t)0x7FC560CF, (q31_t)0x077501BE, (q31_t)0x7FC85853, + (q31_t)0x0742D310, (q31_t)0x7FCB3C23, (q31_t)0x0710A344, + (q31_t)0x7FCE0C3E, (q31_t)0x06DE7261, (q31_t)0x7FD0C8A3, + (q31_t)0x06AC406F, (q31_t)0x7FD37152, (q31_t)0x067A0D75, + (q31_t)0x7FD6064B, (q31_t)0x0647D97C, (q31_t)0x7FD8878D, + (q31_t)0x0615A48A, (q31_t)0x7FDAF518, (q31_t)0x05E36EA9, + (q31_t)0x7FDD4EEC, (q31_t)0x05B137DF, (q31_t)0x7FDF9508, + (q31_t)0x057F0034, (q31_t)0x7FE1C76B, (q31_t)0x054CC7B0, + (q31_t)0x7FE3E616, (q31_t)0x051A8E5C, (q31_t)0x7FE5F108, + (q31_t)0x04E8543D, (q31_t)0x7FE7E840, (q31_t)0x04B6195D, + (q31_t)0x7FE9CBC0, (q31_t)0x0483DDC3, (q31_t)0x7FEB9B85, + (q31_t)0x0451A176, (q31_t)0x7FED5790, (q31_t)0x041F647F, + (q31_t)0x7FEEFFE1, (q31_t)0x03ED26E6, (q31_t)0x7FF09477, + (q31_t)0x03BAE8B1, (q31_t)0x7FF21553, (q31_t)0x0388A9E9, + (q31_t)0x7FF38273, (q31_t)0x03566A96, (q31_t)0x7FF4DBD8, + (q31_t)0x03242ABF, (q31_t)0x7FF62182, (q31_t)0x02F1EA6B, + (q31_t)0x7FF7536F, (q31_t)0x02BFA9A4, (q31_t)0x7FF871A1, + (q31_t)0x028D6870, (q31_t)0x7FF97C17, (q31_t)0x025B26D7, + (q31_t)0x7FFA72D1, (q31_t)0x0228E4E1, (q31_t)0x7FFB55CE, + (q31_t)0x01F6A296, (q31_t)0x7FFC250F, (q31_t)0x01C45FFE, + (q31_t)0x7FFCE093, (q31_t)0x01921D1F, (q31_t)0x7FFD885A, + (q31_t)0x015FDA03, (q31_t)0x7FFE1C64, (q31_t)0x012D96B0, + (q31_t)0x7FFE9CB2, (q31_t)0x00FB532F, (q31_t)0x7FFF0942, + (q31_t)0x00C90F88, (q31_t)0x7FFF6216, (q31_t)0x0096CBC1, + (q31_t)0x7FFFA72C, (q31_t)0x006487E3, (q31_t)0x7FFFD885, + (q31_t)0x003243F5, (q31_t)0x7FFFF621, (q31_t)0x00000000, + (q31_t)0x7FFFFFFF, (q31_t)0xFFCDBC0A, (q31_t)0x7FFFF621, + (q31_t)0xFF9B781D, (q31_t)0x7FFFD885, (q31_t)0xFF69343E, + (q31_t)0x7FFFA72C, (q31_t)0xFF36F078, (q31_t)0x7FFF6216, + (q31_t)0xFF04ACD0, (q31_t)0x7FFF0942, (q31_t)0xFED2694F, + (q31_t)0x7FFE9CB2, (q31_t)0xFEA025FC, (q31_t)0x7FFE1C64, + (q31_t)0xFE6DE2E0, (q31_t)0x7FFD885A, (q31_t)0xFE3BA001, + (q31_t)0x7FFCE093, (q31_t)0xFE095D69, (q31_t)0x7FFC250F, + (q31_t)0xFDD71B1E, (q31_t)0x7FFB55CE, (q31_t)0xFDA4D928, + (q31_t)0x7FFA72D1, (q31_t)0xFD72978F, (q31_t)0x7FF97C17, + (q31_t)0xFD40565B, (q31_t)0x7FF871A1, (q31_t)0xFD0E1594, + (q31_t)0x7FF7536F, (q31_t)0xFCDBD541, (q31_t)0x7FF62182, + (q31_t)0xFCA99569, (q31_t)0x7FF4DBD8, (q31_t)0xFC775616, + (q31_t)0x7FF38273, (q31_t)0xFC45174E, (q31_t)0x7FF21553, + (q31_t)0xFC12D919, (q31_t)0x7FF09477, (q31_t)0xFBE09B80, + (q31_t)0x7FEEFFE1, (q31_t)0xFBAE5E89, (q31_t)0x7FED5790, + (q31_t)0xFB7C223C, (q31_t)0x7FEB9B85, (q31_t)0xFB49E6A2, + (q31_t)0x7FE9CBC0, (q31_t)0xFB17ABC2, (q31_t)0x7FE7E840, + (q31_t)0xFAE571A4, (q31_t)0x7FE5F108, (q31_t)0xFAB3384F, + (q31_t)0x7FE3E616, (q31_t)0xFA80FFCB, (q31_t)0x7FE1C76B, + (q31_t)0xFA4EC820, (q31_t)0x7FDF9508, (q31_t)0xFA1C9156, + (q31_t)0x7FDD4EEC, (q31_t)0xF9EA5B75, (q31_t)0x7FDAF518, + (q31_t)0xF9B82683, (q31_t)0x7FD8878D, (q31_t)0xF985F28A, + (q31_t)0x7FD6064B, (q31_t)0xF953BF90, (q31_t)0x7FD37152, + (q31_t)0xF9218D9E, (q31_t)0x7FD0C8A3, (q31_t)0xF8EF5CBB, + (q31_t)0x7FCE0C3E, (q31_t)0xF8BD2CEF, (q31_t)0x7FCB3C23, + (q31_t)0xF88AFE41, (q31_t)0x7FC85853, (q31_t)0xF858D0BA, + (q31_t)0x7FC560CF, (q31_t)0xF826A461, (q31_t)0x7FC25596, + (q31_t)0xF7F4793E, (q31_t)0x7FBF36A9, (q31_t)0xF7C24F58, + (q31_t)0x7FBC040A, (q31_t)0xF79026B8, (q31_t)0x7FB8BDB7, + (q31_t)0xF75DFF65, (q31_t)0x7FB563B2, (q31_t)0xF72BD967, + (q31_t)0x7FB1F5FC, (q31_t)0xF6F9B4C5, (q31_t)0x7FAE7494, + (q31_t)0xF6C79188, (q31_t)0x7FAADF7C, (q31_t)0xF6956FB6, + (q31_t)0x7FA736B4, (q31_t)0xF6634F58, (q31_t)0x7FA37A3C, + (q31_t)0xF6313076, (q31_t)0x7F9FAA15, (q31_t)0xF5FF1317, + (q31_t)0x7F9BC63F, (q31_t)0xF5CCF743, (q31_t)0x7F97CEBC, + (q31_t)0xF59ADD01, (q31_t)0x7F93C38C, (q31_t)0xF568C45A, + (q31_t)0x7F8FA4AF, (q31_t)0xF536AD55, (q31_t)0x7F8B7226, + (q31_t)0xF50497FA, (q31_t)0x7F872BF3, (q31_t)0xF4D28451, + (q31_t)0x7F82D214, (q31_t)0xF4A07260, (q31_t)0x7F7E648B, + (q31_t)0xF46E6231, (q31_t)0x7F79E35A, (q31_t)0xF43C53CA, + (q31_t)0x7F754E7F, (q31_t)0xF40A4734, (q31_t)0x7F70A5FD, + (q31_t)0xF3D83C76, (q31_t)0x7F6BE9D4, (q31_t)0xF3A63398, + (q31_t)0x7F671A04, (q31_t)0xF3742CA1, (q31_t)0x7F62368F, + (q31_t)0xF342279A, (q31_t)0x7F5D3F75, (q31_t)0xF310248A, + (q31_t)0x7F5834B6, (q31_t)0xF2DE2378, (q31_t)0x7F531654, + (q31_t)0xF2AC246D, (q31_t)0x7F4DE450, (q31_t)0xF27A2770, + (q31_t)0x7F489EAA, (q31_t)0xF2482C89, (q31_t)0x7F434563, + (q31_t)0xF21633C0, (q31_t)0x7F3DD87C, (q31_t)0xF1E43D1C, + (q31_t)0x7F3857F5, (q31_t)0xF1B248A5, (q31_t)0x7F32C3D0, + (q31_t)0xF1805662, (q31_t)0x7F2D1C0E, (q31_t)0xF14E665C, + (q31_t)0x7F2760AF, (q31_t)0xF11C789A, (q31_t)0x7F2191B4, + (q31_t)0xF0EA8D23, (q31_t)0x7F1BAF1E, (q31_t)0xF0B8A401, + (q31_t)0x7F15B8EE, (q31_t)0xF086BD39, (q31_t)0x7F0FAF24, + (q31_t)0xF054D8D4, (q31_t)0x7F0991C3, (q31_t)0xF022F6DA, + (q31_t)0x7F0360CB, (q31_t)0xEFF11752, (q31_t)0x7EFD1C3C, + (q31_t)0xEFBF3A44, (q31_t)0x7EF6C418, (q31_t)0xEF8D5FB8, + (q31_t)0x7EF0585F, (q31_t)0xEF5B87B5, (q31_t)0x7EE9D913, + (q31_t)0xEF29B243, (q31_t)0x7EE34635, (q31_t)0xEEF7DF6A, + (q31_t)0x7EDC9FC6, (q31_t)0xEEC60F31, (q31_t)0x7ED5E5C6, + (q31_t)0xEE9441A0, (q31_t)0x7ECF1837, (q31_t)0xEE6276BF, + (q31_t)0x7EC8371A, (q31_t)0xEE30AE95, (q31_t)0x7EC1426F, + (q31_t)0xEDFEE92B, (q31_t)0x7EBA3A39, (q31_t)0xEDCD2687, + (q31_t)0x7EB31E77, (q31_t)0xED9B66B2, (q31_t)0x7EABEF2C, + (q31_t)0xED69A9B2, (q31_t)0x7EA4AC58, (q31_t)0xED37EF91, + (q31_t)0x7E9D55FC, (q31_t)0xED063855, (q31_t)0x7E95EC19, + (q31_t)0xECD48406, (q31_t)0x7E8E6EB1, (q31_t)0xECA2D2AC, + (q31_t)0x7E86DDC5, (q31_t)0xEC71244F, (q31_t)0x7E7F3956, + (q31_t)0xEC3F78F5, (q31_t)0x7E778165, (q31_t)0xEC0DD0A8, + (q31_t)0x7E6FB5F3, (q31_t)0xEBDC2B6D, (q31_t)0x7E67D702, + (q31_t)0xEBAA894E, (q31_t)0x7E5FE493, (q31_t)0xEB78EA52, + (q31_t)0x7E57DEA6, (q31_t)0xEB474E80, (q31_t)0x7E4FC53E, + (q31_t)0xEB15B5E0, (q31_t)0x7E47985B, (q31_t)0xEAE4207A, + (q31_t)0x7E3F57FE, (q31_t)0xEAB28E55, (q31_t)0x7E37042A, + (q31_t)0xEA80FF79, (q31_t)0x7E2E9CDF, (q31_t)0xEA4F73EE, + (q31_t)0x7E26221E, (q31_t)0xEA1DEBBB, (q31_t)0x7E1D93E9, + (q31_t)0xE9EC66E8, (q31_t)0x7E14F242, (q31_t)0xE9BAE57C, + (q31_t)0x7E0C3D29, (q31_t)0xE9896780, (q31_t)0x7E03749F, + (q31_t)0xE957ECFB, (q31_t)0x7DFA98A7, (q31_t)0xE92675F4, + (q31_t)0x7DF1A942, (q31_t)0xE8F50273, (q31_t)0x7DE8A670, + (q31_t)0xE8C3927F, (q31_t)0x7DDF9034, (q31_t)0xE8922621, + (q31_t)0x7DD6668E, (q31_t)0xE860BD60, (q31_t)0x7DCD2981, + (q31_t)0xE82F5844, (q31_t)0x7DC3D90D, (q31_t)0xE7FDF6D3, + (q31_t)0x7DBA7534, (q31_t)0xE7CC9917, (q31_t)0x7DB0FDF7, + (q31_t)0xE79B3F16, (q31_t)0x7DA77359, (q31_t)0xE769E8D8, + (q31_t)0x7D9DD55A, (q31_t)0xE7389664, (q31_t)0x7D9423FB, + (q31_t)0xE70747C3, (q31_t)0x7D8A5F3F, (q31_t)0xE6D5FCFC, + (q31_t)0x7D808727, (q31_t)0xE6A4B616, (q31_t)0x7D769BB5, + (q31_t)0xE6737319, (q31_t)0x7D6C9CE9, (q31_t)0xE642340D, + (q31_t)0x7D628AC5, (q31_t)0xE610F8F9, (q31_t)0x7D58654C, + (q31_t)0xE5DFC1E4, (q31_t)0x7D4E2C7E, (q31_t)0xE5AE8ED8, + (q31_t)0x7D43E05E, (q31_t)0xE57D5FDA, (q31_t)0x7D3980EC, + (q31_t)0xE54C34F3, (q31_t)0x7D2F0E2A, (q31_t)0xE51B0E2A, + (q31_t)0x7D24881A, (q31_t)0xE4E9EB86, (q31_t)0x7D19EEBE, + (q31_t)0xE4B8CD10, (q31_t)0x7D0F4218, (q31_t)0xE487B2CF, + (q31_t)0x7D048228, (q31_t)0xE4569CCB, (q31_t)0x7CF9AEF0, + (q31_t)0xE4258B0A, (q31_t)0x7CEEC873, (q31_t)0xE3F47D95, + (q31_t)0x7CE3CEB1, (q31_t)0xE3C37473, (q31_t)0x7CD8C1AD, + (q31_t)0xE3926FAC, (q31_t)0x7CCDA168, (q31_t)0xE3616F47, + (q31_t)0x7CC26DE5, (q31_t)0xE330734C, (q31_t)0x7CB72724, + (q31_t)0xE2FF7BC3, (q31_t)0x7CABCD27, (q31_t)0xE2CE88B2, + (q31_t)0x7CA05FF1, (q31_t)0xE29D9A22, (q31_t)0x7C94DF82, + (q31_t)0xE26CB01A, (q31_t)0x7C894BDD, (q31_t)0xE23BCAA2, + (q31_t)0x7C7DA504, (q31_t)0xE20AE9C1, (q31_t)0x7C71EAF8, + (q31_t)0xE1DA0D7E, (q31_t)0x7C661DBB, (q31_t)0xE1A935E1, + (q31_t)0x7C5A3D4F, (q31_t)0xE17862F3, (q31_t)0x7C4E49B6, + (q31_t)0xE14794B9, (q31_t)0x7C4242F2, (q31_t)0xE116CB3D, + (q31_t)0x7C362904, (q31_t)0xE0E60684, (q31_t)0x7C29FBEE, + (q31_t)0xE0B54698, (q31_t)0x7C1DBBB2, (q31_t)0xE0848B7F, + (q31_t)0x7C116853, (q31_t)0xE053D541, (q31_t)0x7C0501D1, + (q31_t)0xE02323E5, (q31_t)0x7BF88830, (q31_t)0xDFF27773, + (q31_t)0x7BEBFB70, (q31_t)0xDFC1CFF2, (q31_t)0x7BDF5B94, + (q31_t)0xDF912D6A, (q31_t)0x7BD2A89E, (q31_t)0xDF608FE3, + (q31_t)0x7BC5E28F, (q31_t)0xDF2FF764, (q31_t)0x7BB9096A, + (q31_t)0xDEFF63F4, (q31_t)0x7BAC1D31, (q31_t)0xDECED59B, + (q31_t)0x7B9F1DE5, (q31_t)0xDE9E4C60, (q31_t)0x7B920B89, + (q31_t)0xDE6DC84B, (q31_t)0x7B84E61E, (q31_t)0xDE3D4963, + (q31_t)0x7B77ADA8, (q31_t)0xDE0CCFB1, (q31_t)0x7B6A6227, + (q31_t)0xDDDC5B3A, (q31_t)0x7B5D039D, (q31_t)0xDDABEC07, + (q31_t)0x7B4F920E, (q31_t)0xDD7B8220, (q31_t)0x7B420D7A, + (q31_t)0xDD4B1D8B, (q31_t)0x7B3475E4, (q31_t)0xDD1ABE51, + (q31_t)0x7B26CB4F, (q31_t)0xDCEA6478, (q31_t)0x7B190DBB, + (q31_t)0xDCBA1008, (q31_t)0x7B0B3D2C, (q31_t)0xDC89C108, + (q31_t)0x7AFD59A3, (q31_t)0xDC597781, (q31_t)0x7AEF6323, + (q31_t)0xDC293379, (q31_t)0x7AE159AE, (q31_t)0xDBF8F4F8, + (q31_t)0x7AD33D45, (q31_t)0xDBC8BC05, (q31_t)0x7AC50DEB, + (q31_t)0xDB9888A8, (q31_t)0x7AB6CBA3, (q31_t)0xDB685AE8, + (q31_t)0x7AA8766E, (q31_t)0xDB3832CD, (q31_t)0x7A9A0E4F, + (q31_t)0xDB08105E, (q31_t)0x7A8B9348, (q31_t)0xDAD7F3A2, + (q31_t)0x7A7D055B, (q31_t)0xDAA7DCA1, (q31_t)0x7A6E648A, + (q31_t)0xDA77CB62, (q31_t)0x7A5FB0D8, (q31_t)0xDA47BFED, + (q31_t)0x7A50EA46, (q31_t)0xDA17BA4A, (q31_t)0x7A4210D8, + (q31_t)0xD9E7BA7E, (q31_t)0x7A33248F, (q31_t)0xD9B7C093, + (q31_t)0x7A24256E, (q31_t)0xD987CC8F, (q31_t)0x7A151377, + (q31_t)0xD957DE7A, (q31_t)0x7A05EEAD, (q31_t)0xD927F65B, + (q31_t)0x79F6B711, (q31_t)0xD8F81439, (q31_t)0x79E76CA6, + (q31_t)0xD8C8381C, (q31_t)0x79D80F6F, (q31_t)0xD898620C, + (q31_t)0x79C89F6D, (q31_t)0xD868920F, (q31_t)0x79B91CA4, + (q31_t)0xD838C82D, (q31_t)0x79A98715, (q31_t)0xD809046D, + (q31_t)0x7999DEC3, (q31_t)0xD7D946D7, (q31_t)0x798A23B1, + (q31_t)0xD7A98F73, (q31_t)0x797A55E0, (q31_t)0xD779DE46, + (q31_t)0x796A7554, (q31_t)0xD74A335A, (q31_t)0x795A820E, + (q31_t)0xD71A8EB5, (q31_t)0x794A7C11, (q31_t)0xD6EAF05E, + (q31_t)0x793A6360, (q31_t)0xD6BB585D, (q31_t)0x792A37FE, + (q31_t)0xD68BC6BA, (q31_t)0x7919F9EB, (q31_t)0xD65C3B7B, + (q31_t)0x7909A92C, (q31_t)0xD62CB6A7, (q31_t)0x78F945C3, + (q31_t)0xD5FD3847, (q31_t)0x78E8CFB1, (q31_t)0xD5CDC062, + (q31_t)0x78D846FB, (q31_t)0xD59E4EFE, (q31_t)0x78C7ABA1, + (q31_t)0xD56EE424, (q31_t)0x78B6FDA8, (q31_t)0xD53F7FDA, + (q31_t)0x78A63D10, (q31_t)0xD5102227, (q31_t)0x789569DE, + (q31_t)0xD4E0CB14, (q31_t)0x78848413, (q31_t)0xD4B17AA7, + (q31_t)0x78738BB3, (q31_t)0xD48230E8, (q31_t)0x786280BF, + (q31_t)0xD452EDDE, (q31_t)0x7851633B, (q31_t)0xD423B190, + (q31_t)0x78403328, (q31_t)0xD3F47C06, (q31_t)0x782EF08B, + (q31_t)0xD3C54D46, (q31_t)0x781D9B64, (q31_t)0xD3962559, + (q31_t)0x780C33B8, (q31_t)0xD3670445, (q31_t)0x77FAB988, + (q31_t)0xD337EA12, (q31_t)0x77E92CD8, (q31_t)0xD308D6C6, + (q31_t)0x77D78DAA, (q31_t)0xD2D9CA6A, (q31_t)0x77C5DC01, + (q31_t)0xD2AAC504, (q31_t)0x77B417DF, (q31_t)0xD27BC69C, + (q31_t)0x77A24148, (q31_t)0xD24CCF38, (q31_t)0x7790583D, + (q31_t)0xD21DDEE1, (q31_t)0x777E5CC3, (q31_t)0xD1EEF59E, + (q31_t)0x776C4EDB, (q31_t)0xD1C01374, (q31_t)0x775A2E88, + (q31_t)0xD191386D, (q31_t)0x7747FBCE, (q31_t)0xD162648F, + (q31_t)0x7735B6AE, (q31_t)0xD13397E1, (q31_t)0x77235F2D, + (q31_t)0xD104D26B, (q31_t)0x7710F54B, (q31_t)0xD0D61433, + (q31_t)0x76FE790E, (q31_t)0xD0A75D42, (q31_t)0x76EBEA77, + (q31_t)0xD078AD9D, (q31_t)0x76D94988, (q31_t)0xD04A054D, + (q31_t)0x76C69646, (q31_t)0xD01B6459, (q31_t)0x76B3D0B3, + (q31_t)0xCFECCAC7, (q31_t)0x76A0F8D2, (q31_t)0xCFBE389F, + (q31_t)0x768E0EA5, (q31_t)0xCF8FADE8, (q31_t)0x767B1230, + (q31_t)0xCF612AAA, (q31_t)0x76680376, (q31_t)0xCF32AEEB, + (q31_t)0x7654E279, (q31_t)0xCF043AB2, (q31_t)0x7641AF3C, + (q31_t)0xCED5CE08, (q31_t)0x762E69C3, (q31_t)0xCEA768F2, + (q31_t)0x761B1211, (q31_t)0xCE790B78, (q31_t)0x7607A827, + (q31_t)0xCE4AB5A2, (q31_t)0x75F42C0A, (q31_t)0xCE1C6776, + (q31_t)0x75E09DBD, (q31_t)0xCDEE20FC, (q31_t)0x75CCFD42, + (q31_t)0xCDBFE23A, (q31_t)0x75B94A9C, (q31_t)0xCD91AB38, + (q31_t)0x75A585CF, (q31_t)0xCD637BFD, (q31_t)0x7591AEDD, + (q31_t)0xCD355490, (q31_t)0x757DC5CA, (q31_t)0xCD0734F8, + (q31_t)0x7569CA98, (q31_t)0xCCD91D3D, (q31_t)0x7555BD4B, + (q31_t)0xCCAB0D65, (q31_t)0x75419DE6, (q31_t)0xCC7D0577, + (q31_t)0x752D6C6C, (q31_t)0xCC4F057B, (q31_t)0x751928E0, + (q31_t)0xCC210D78, (q31_t)0x7504D345, (q31_t)0xCBF31D75, + (q31_t)0x74F06B9E, (q31_t)0xCBC53578, (q31_t)0x74DBF1EF, + (q31_t)0xCB975589, (q31_t)0x74C7663A, (q31_t)0xCB697DB0, + (q31_t)0x74B2C883, (q31_t)0xCB3BADF2, (q31_t)0x749E18CD, + (q31_t)0xCB0DE658, (q31_t)0x7489571B, (q31_t)0xCAE026E8, + (q31_t)0x74748371, (q31_t)0xCAB26FA9, (q31_t)0x745F9DD1, + (q31_t)0xCA84C0A2, (q31_t)0x744AA63E, (q31_t)0xCA5719DB, + (q31_t)0x74359CBD, (q31_t)0xCA297B5A, (q31_t)0x74208150, + (q31_t)0xC9FBE527, (q31_t)0x740B53FA, (q31_t)0xC9CE5748, + (q31_t)0x73F614C0, (q31_t)0xC9A0D1C4, (q31_t)0x73E0C3A3, + (q31_t)0xC97354A3, (q31_t)0x73CB60A7, (q31_t)0xC945DFEC, + (q31_t)0x73B5EBD0, (q31_t)0xC91873A5, (q31_t)0x73A06522, + (q31_t)0xC8EB0FD6, (q31_t)0x738ACC9E, (q31_t)0xC8BDB485, + (q31_t)0x73752249, (q31_t)0xC89061BA, (q31_t)0x735F6626, + (q31_t)0xC863177B, (q31_t)0x73499838, (q31_t)0xC835D5D0, + (q31_t)0x7333B883, (q31_t)0xC8089CBF, (q31_t)0x731DC709, + (q31_t)0xC7DB6C50, (q31_t)0x7307C3D0, (q31_t)0xC7AE4489, + (q31_t)0x72F1AED8, (q31_t)0xC7812571, (q31_t)0x72DB8828, + (q31_t)0xC7540F10, (q31_t)0x72C54FC0, (q31_t)0xC727016C, + (q31_t)0x72AF05A6, (q31_t)0xC6F9FC8D, (q31_t)0x7298A9DC, + (q31_t)0xC6CD0079, (q31_t)0x72823C66, (q31_t)0xC6A00D36, + (q31_t)0x726BBD48, (q31_t)0xC67322CD, (q31_t)0x72552C84, + (q31_t)0xC6464144, (q31_t)0x723E8A1F, (q31_t)0xC61968A2, + (q31_t)0x7227D61C, (q31_t)0xC5EC98ED, (q31_t)0x7211107D, + (q31_t)0xC5BFD22E, (q31_t)0x71FA3948, (q31_t)0xC593146A, + (q31_t)0x71E3507F, (q31_t)0xC5665FA8, (q31_t)0x71CC5626, + (q31_t)0xC539B3F0, (q31_t)0x71B54A40, (q31_t)0xC50D1148, + (q31_t)0x719E2CD2, (q31_t)0xC4E077B8, (q31_t)0x7186FDDE, + (q31_t)0xC4B3E746, (q31_t)0x716FBD68, (q31_t)0xC4875FF8, + (q31_t)0x71586B73, (q31_t)0xC45AE1D7, (q31_t)0x71410804, + (q31_t)0xC42E6CE8, (q31_t)0x7129931E, (q31_t)0xC4020132, + (q31_t)0x71120CC5, (q31_t)0xC3D59EBD, (q31_t)0x70FA74FB, + (q31_t)0xC3A9458F, (q31_t)0x70E2CBC6, (q31_t)0xC37CF5B0, + (q31_t)0x70CB1127, (q31_t)0xC350AF25, (q31_t)0x70B34524, + (q31_t)0xC32471F6, (q31_t)0x709B67C0, (q31_t)0xC2F83E2A, + (q31_t)0x708378FE, (q31_t)0xC2CC13C7, (q31_t)0x706B78E3, + (q31_t)0xC29FF2D4, (q31_t)0x70536771, (q31_t)0xC273DB58, + (q31_t)0x703B44AC, (q31_t)0xC247CD5A, (q31_t)0x70231099, + (q31_t)0xC21BC8E0, (q31_t)0x700ACB3B, (q31_t)0xC1EFCDF2, + (q31_t)0x6FF27496, (q31_t)0xC1C3DC96, (q31_t)0x6FDA0CAD, + (q31_t)0xC197F4D3, (q31_t)0x6FC19385, (q31_t)0xC16C16B0, + (q31_t)0x6FA90920, (q31_t)0xC1404233, (q31_t)0x6F906D84, + (q31_t)0xC1147763, (q31_t)0x6F77C0B3, (q31_t)0xC0E8B648, + (q31_t)0x6F5F02B1, (q31_t)0xC0BCFEE7, (q31_t)0x6F463383, + (q31_t)0xC0915147, (q31_t)0x6F2D532C, (q31_t)0xC065AD70, + (q31_t)0x6F1461AF, (q31_t)0xC03A1368, (q31_t)0x6EFB5F12, + (q31_t)0xC00E8335, (q31_t)0x6EE24B57, (q31_t)0xBFE2FCDF, + (q31_t)0x6EC92682, (q31_t)0xBFB7806C, (q31_t)0x6EAFF098, + (q31_t)0xBF8C0DE2, (q31_t)0x6E96A99C, (q31_t)0xBF60A54A, + (q31_t)0x6E7D5193, (q31_t)0xBF3546A8, (q31_t)0x6E63E87F, + (q31_t)0xBF09F204, (q31_t)0x6E4A6E65, (q31_t)0xBEDEA765, + (q31_t)0x6E30E349, (q31_t)0xBEB366D1, (q31_t)0x6E17472F, + (q31_t)0xBE88304F, (q31_t)0x6DFD9A1B, (q31_t)0xBE5D03E5, + (q31_t)0x6DE3DC11, (q31_t)0xBE31E19B, (q31_t)0x6DCA0D14, + (q31_t)0xBE06C977, (q31_t)0x6DB02D29, (q31_t)0xBDDBBB7F, + (q31_t)0x6D963C54, (q31_t)0xBDB0B7BA, (q31_t)0x6D7C3A98, + (q31_t)0xBD85BE2F, (q31_t)0x6D6227FA, (q31_t)0xBD5ACEE5, + (q31_t)0x6D48047E, (q31_t)0xBD2FE9E1, (q31_t)0x6D2DD027, + (q31_t)0xBD050F2C, (q31_t)0x6D138AFA, (q31_t)0xBCDA3ECA, + (q31_t)0x6CF934FB, (q31_t)0xBCAF78C3, (q31_t)0x6CDECE2E, + (q31_t)0xBC84BD1E, (q31_t)0x6CC45697, (q31_t)0xBC5A0BE1, + (q31_t)0x6CA9CE3A, (q31_t)0xBC2F6513, (q31_t)0x6C8F351C, + (q31_t)0xBC04C8BA, (q31_t)0x6C748B3F, (q31_t)0xBBDA36DC, + (q31_t)0x6C59D0A9, (q31_t)0xBBAFAF81, (q31_t)0x6C3F055D, + (q31_t)0xBB8532AF, (q31_t)0x6C242960, (q31_t)0xBB5AC06C, + (q31_t)0x6C093CB6, (q31_t)0xBB3058C0, (q31_t)0x6BEE3F62, + (q31_t)0xBB05FBB0, (q31_t)0x6BD3316A, (q31_t)0xBADBA943, + (q31_t)0x6BB812D0, (q31_t)0xBAB1617F, (q31_t)0x6B9CE39B, + (q31_t)0xBA87246C, (q31_t)0x6B81A3CD, (q31_t)0xBA5CF210, + (q31_t)0x6B66536A, (q31_t)0xBA32CA70, (q31_t)0x6B4AF278, + (q31_t)0xBA08AD94, (q31_t)0x6B2F80FA, (q31_t)0xB9DE9B83, + (q31_t)0x6B13FEF5, (q31_t)0xB9B49442, (q31_t)0x6AF86C6C, + (q31_t)0xB98A97D8, (q31_t)0x6ADCC964, (q31_t)0xB960A64B, + (q31_t)0x6AC115E1, (q31_t)0xB936BFA3, (q31_t)0x6AA551E8, + (q31_t)0xB90CE3E6, (q31_t)0x6A897D7D, (q31_t)0xB8E31319, + (q31_t)0x6A6D98A4, (q31_t)0xB8B94D44, (q31_t)0x6A51A361, + (q31_t)0xB88F926C, (q31_t)0x6A359DB9, (q31_t)0xB865E299, + (q31_t)0x6A1987B0, (q31_t)0xB83C3DD1, (q31_t)0x69FD614A, + (q31_t)0xB812A419, (q31_t)0x69E12A8C, (q31_t)0xB7E9157A, + (q31_t)0x69C4E37A, (q31_t)0xB7BF91F8, (q31_t)0x69A88C18, + (q31_t)0xB796199B, (q31_t)0x698C246C, (q31_t)0xB76CAC68, + (q31_t)0x696FAC78, (q31_t)0xB7434A67, (q31_t)0x69532442, + (q31_t)0xB719F39D, (q31_t)0x69368BCE, (q31_t)0xB6F0A811, + (q31_t)0x6919E320, (q31_t)0xB6C767CA, (q31_t)0x68FD2A3D, + (q31_t)0xB69E32CD, (q31_t)0x68E06129, (q31_t)0xB6750921, + (q31_t)0x68C387E9, (q31_t)0xB64BEACC, (q31_t)0x68A69E81, + (q31_t)0xB622D7D5, (q31_t)0x6889A4F5, (q31_t)0xB5F9D042, + (q31_t)0x686C9B4B, (q31_t)0xB5D0D41A, (q31_t)0x684F8186, + (q31_t)0xB5A7E362, (q31_t)0x683257AA, (q31_t)0xB57EFE21, + (q31_t)0x68151DBE, (q31_t)0xB556245E, (q31_t)0x67F7D3C4, + (q31_t)0xB52D561E, (q31_t)0x67DA79C2, (q31_t)0xB5049368, + (q31_t)0x67BD0FBC, (q31_t)0xB4DBDC42, (q31_t)0x679F95B7, + (q31_t)0xB4B330B2, (q31_t)0x67820BB6, (q31_t)0xB48A90C0, + (q31_t)0x676471C0, (q31_t)0xB461FC70, (q31_t)0x6746C7D7, + (q31_t)0xB43973C9, (q31_t)0x67290E02, (q31_t)0xB410F6D2, + (q31_t)0x670B4443, (q31_t)0xB3E88591, (q31_t)0x66ED6AA1, + (q31_t)0xB3C0200C, (q31_t)0x66CF811F, (q31_t)0xB397C649, + (q31_t)0x66B187C3, (q31_t)0xB36F784E, (q31_t)0x66937E90, + (q31_t)0xB3473622, (q31_t)0x6675658C, (q31_t)0xB31EFFCB, + (q31_t)0x66573CBB, (q31_t)0xB2F6D54F, (q31_t)0x66390422, + (q31_t)0xB2CEB6B5, (q31_t)0x661ABBC5, (q31_t)0xB2A6A401, + (q31_t)0x65FC63A9, (q31_t)0xB27E9D3B, (q31_t)0x65DDFBD3, + (q31_t)0xB256A26A, (q31_t)0x65BF8447, (q31_t)0xB22EB392, + (q31_t)0x65A0FD0B, (q31_t)0xB206D0BA, (q31_t)0x65826622, + (q31_t)0xB1DEF9E8, (q31_t)0x6563BF92, (q31_t)0xB1B72F23, + (q31_t)0x6545095F, (q31_t)0xB18F7070, (q31_t)0x6526438E, + (q31_t)0xB167BDD6, (q31_t)0x65076E24, (q31_t)0xB140175B, + (q31_t)0x64E88926, (q31_t)0xB1187D05, (q31_t)0x64C99498, + (q31_t)0xB0F0EEDA, (q31_t)0x64AA907F, (q31_t)0xB0C96CDF, + (q31_t)0x648B7CDF, (q31_t)0xB0A1F71C, (q31_t)0x646C59BF, + (q31_t)0xB07A8D97, (q31_t)0x644D2722, (q31_t)0xB0533055, + (q31_t)0x642DE50D, (q31_t)0xB02BDF5C, (q31_t)0x640E9385, + (q31_t)0xB0049AB2, (q31_t)0x63EF328F, (q31_t)0xAFDD625F, + (q31_t)0x63CFC230, (q31_t)0xAFB63667, (q31_t)0x63B0426D, + (q31_t)0xAF8F16D0, (q31_t)0x6390B34A, (q31_t)0xAF6803A1, + (q31_t)0x637114CC, (q31_t)0xAF40FCE0, (q31_t)0x635166F8, + (q31_t)0xAF1A0293, (q31_t)0x6331A9D4, (q31_t)0xAEF314BF, + (q31_t)0x6311DD63, (q31_t)0xAECC336B, (q31_t)0x62F201AC, + (q31_t)0xAEA55E9D, (q31_t)0x62D216B2, (q31_t)0xAE7E965B, + (q31_t)0x62B21C7B, (q31_t)0xAE57DAAA, (q31_t)0x6292130C, + (q31_t)0xAE312B91, (q31_t)0x6271FA69, (q31_t)0xAE0A8916, + (q31_t)0x6251D297, (q31_t)0xADE3F33E, (q31_t)0x62319B9D, + (q31_t)0xADBD6A10, (q31_t)0x6211557D, (q31_t)0xAD96ED91, + (q31_t)0x61F1003E, (q31_t)0xAD707DC8, (q31_t)0x61D09BE5, + (q31_t)0xAD4A1ABA, (q31_t)0x61B02876, (q31_t)0xAD23C46D, + (q31_t)0x618FA5F6, (q31_t)0xACFD7AE8, (q31_t)0x616F146B, + (q31_t)0xACD73E30, (q31_t)0x614E73D9, (q31_t)0xACB10E4A, + (q31_t)0x612DC446, (q31_t)0xAC8AEB3E, (q31_t)0x610D05B7, + (q31_t)0xAC64D510, (q31_t)0x60EC3830, (q31_t)0xAC3ECBC7, + (q31_t)0x60CB5BB6, (q31_t)0xAC18CF68, (q31_t)0x60AA704F, + (q31_t)0xABF2DFFA, (q31_t)0x60897600, (q31_t)0xABCCFD82, + (q31_t)0x60686CCE, (q31_t)0xABA72806, (q31_t)0x604754BE, + (q31_t)0xAB815F8C, (q31_t)0x60262DD5, (q31_t)0xAB5BA41A, + (q31_t)0x6004F818, (q31_t)0xAB35F5B5, (q31_t)0x5FE3B38D, + (q31_t)0xAB105464, (q31_t)0x5FC26038, (q31_t)0xAAEAC02B, + (q31_t)0x5FA0FE1E, (q31_t)0xAAC53912, (q31_t)0x5F7F8D46, + (q31_t)0xAA9FBF1D, (q31_t)0x5F5E0DB3, (q31_t)0xAA7A5253, + (q31_t)0x5F3C7F6B, (q31_t)0xAA54F2B9, (q31_t)0x5F1AE273, + (q31_t)0xAA2FA055, (q31_t)0x5EF936D1, (q31_t)0xAA0A5B2D, + (q31_t)0x5ED77C89, (q31_t)0xA9E52347, (q31_t)0x5EB5B3A1, + (q31_t)0xA9BFF8A8, (q31_t)0x5E93DC1F, (q31_t)0xA99ADB56, + (q31_t)0x5E71F606, (q31_t)0xA975CB56, (q31_t)0x5E50015D, + (q31_t)0xA950C8AF, (q31_t)0x5E2DFE28, (q31_t)0xA92BD366, + (q31_t)0x5E0BEC6E, (q31_t)0xA906EB81, (q31_t)0x5DE9CC32, + (q31_t)0xA8E21106, (q31_t)0x5DC79D7C, (q31_t)0xA8BD43FA, + (q31_t)0x5DA5604E, (q31_t)0xA8988463, (q31_t)0x5D8314B0, + (q31_t)0xA873D246, (q31_t)0x5D60BAA6, (q31_t)0xA84F2DA9, + (q31_t)0x5D3E5236, (q31_t)0xA82A9693, (q31_t)0x5D1BDB65, + (q31_t)0xA8060D08, (q31_t)0x5CF95638, (q31_t)0xA7E1910E, + (q31_t)0x5CD6C2B4, (q31_t)0xA7BD22AB, (q31_t)0x5CB420DF, + (q31_t)0xA798C1E4, (q31_t)0x5C9170BF, (q31_t)0xA7746EC0, + (q31_t)0x5C6EB258, (q31_t)0xA7502943, (q31_t)0x5C4BE5B0, + (q31_t)0xA72BF173, (q31_t)0x5C290ACC, (q31_t)0xA707C756, + (q31_t)0x5C0621B2, (q31_t)0xA6E3AAF2, (q31_t)0x5BE32A67, + (q31_t)0xA6BF9C4B, (q31_t)0x5BC024F0, (q31_t)0xA69B9B68, + (q31_t)0x5B9D1153, (q31_t)0xA677A84E, (q31_t)0x5B79EF96, + (q31_t)0xA653C302, (q31_t)0x5B56BFBD, (q31_t)0xA62FEB8B, + (q31_t)0x5B3381CE, (q31_t)0xA60C21ED, (q31_t)0x5B1035CF, + (q31_t)0xA5E8662F, (q31_t)0x5AECDBC4, (q31_t)0xA5C4B855, + (q31_t)0x5AC973B4, (q31_t)0xA5A11865, (q31_t)0x5AA5FDA4, + (q31_t)0xA57D8666, (q31_t)0x5A82799A, (q31_t)0xA55A025B, + (q31_t)0x5A5EE79A, (q31_t)0xA5368C4B, (q31_t)0x5A3B47AA, + (q31_t)0xA513243B, (q31_t)0x5A1799D0, (q31_t)0xA4EFCA31, + (q31_t)0x59F3DE12, (q31_t)0xA4CC7E31, (q31_t)0x59D01474, + (q31_t)0xA4A94042, (q31_t)0x59AC3CFD, (q31_t)0xA4861069, + (q31_t)0x598857B1, (q31_t)0xA462EEAC, (q31_t)0x59646497, + (q31_t)0xA43FDB0F, (q31_t)0x594063B4, (q31_t)0xA41CD598, + (q31_t)0x591C550E, (q31_t)0xA3F9DE4D, (q31_t)0x58F838A9, + (q31_t)0xA3D6F533, (q31_t)0x58D40E8C, (q31_t)0xA3B41A4F, + (q31_t)0x58AFD6BC, (q31_t)0xA3914DA7, (q31_t)0x588B913F, + (q31_t)0xA36E8F40, (q31_t)0x58673E1B, (q31_t)0xA34BDF20, + (q31_t)0x5842DD54, (q31_t)0xA3293D4B, (q31_t)0x581E6EF1, + (q31_t)0xA306A9C7, (q31_t)0x57F9F2F7, (q31_t)0xA2E4249A, + (q31_t)0x57D5696C, (q31_t)0xA2C1ADC9, (q31_t)0x57B0D256, + (q31_t)0xA29F4559, (q31_t)0x578C2DB9, (q31_t)0xA27CEB4F, + (q31_t)0x57677B9D, (q31_t)0xA25A9FB1, (q31_t)0x5742BC05, + (q31_t)0xA2386283, (q31_t)0x571DEEF9, (q31_t)0xA21633CD, + (q31_t)0x56F9147E, (q31_t)0xA1F41391, (q31_t)0x56D42C99, + (q31_t)0xA1D201D7, (q31_t)0x56AF3750, (q31_t)0xA1AFFEA2, + (q31_t)0x568A34A9, (q31_t)0xA18E09F9, (q31_t)0x566524AA, + (q31_t)0xA16C23E1, (q31_t)0x56400757, (q31_t)0xA14A4C5E, + (q31_t)0x561ADCB8, (q31_t)0xA1288376, (q31_t)0x55F5A4D2, + (q31_t)0xA106C92E, (q31_t)0x55D05FAA, (q31_t)0xA0E51D8C, + (q31_t)0x55AB0D46, (q31_t)0xA0C38094, (q31_t)0x5585ADAC, + (q31_t)0xA0A1F24C, (q31_t)0x556040E2, (q31_t)0xA08072BA, + (q31_t)0x553AC6ED, (q31_t)0xA05F01E1, (q31_t)0x55153FD4, + (q31_t)0xA03D9FC7, (q31_t)0x54EFAB9C, (q31_t)0xA01C4C72, + (q31_t)0x54CA0A4A, (q31_t)0x9FFB07E7, (q31_t)0x54A45BE5, + (q31_t)0x9FD9D22A, (q31_t)0x547EA073, (q31_t)0x9FB8AB41, + (q31_t)0x5458D7F9, (q31_t)0x9F979331, (q31_t)0x5433027D, + (q31_t)0x9F7689FF, (q31_t)0x540D2005, (q31_t)0x9F558FB0, + (q31_t)0x53E73097, (q31_t)0x9F34A449, (q31_t)0x53C13438, + (q31_t)0x9F13C7D0, (q31_t)0x539B2AEF, (q31_t)0x9EF2FA48, + (q31_t)0x537514C1, (q31_t)0x9ED23BB9, (q31_t)0x534EF1B5, + (q31_t)0x9EB18C26, (q31_t)0x5328C1D0, (q31_t)0x9E90EB94, + (q31_t)0x53028517, (q31_t)0x9E705A09, (q31_t)0x52DC3B92, + (q31_t)0x9E4FD789, (q31_t)0x52B5E545, (q31_t)0x9E2F641A, + (q31_t)0x528F8237, (q31_t)0x9E0EFFC1, (q31_t)0x5269126E, + (q31_t)0x9DEEAA82, (q31_t)0x524295EF, (q31_t)0x9DCE6462, + (q31_t)0x521C0CC1, (q31_t)0x9DAE2D68, (q31_t)0x51F576E9, + (q31_t)0x9D8E0596, (q31_t)0x51CED46E, (q31_t)0x9D6DECF4, + (q31_t)0x51A82555, (q31_t)0x9D4DE384, (q31_t)0x518169A4, + (q31_t)0x9D2DE94D, (q31_t)0x515AA162, (q31_t)0x9D0DFE53, + (q31_t)0x5133CC94, (q31_t)0x9CEE229C, (q31_t)0x510CEB40, + (q31_t)0x9CCE562B, (q31_t)0x50E5FD6C, (q31_t)0x9CAE9907, + (q31_t)0x50BF031F, (q31_t)0x9C8EEB33, (q31_t)0x5097FC5E, + (q31_t)0x9C6F4CB5, (q31_t)0x5070E92F, (q31_t)0x9C4FBD92, + (q31_t)0x5049C999, (q31_t)0x9C303DCF, (q31_t)0x50229DA0, + (q31_t)0x9C10CD70, (q31_t)0x4FFB654D, (q31_t)0x9BF16C7A, + (q31_t)0x4FD420A3, (q31_t)0x9BD21AF2, (q31_t)0x4FACCFAB, + (q31_t)0x9BB2D8DD, (q31_t)0x4F857268, (q31_t)0x9B93A640, + (q31_t)0x4F5E08E3, (q31_t)0x9B748320, (q31_t)0x4F369320, + (q31_t)0x9B556F80, (q31_t)0x4F0F1126, (q31_t)0x9B366B67, + (q31_t)0x4EE782FA, (q31_t)0x9B1776D9, (q31_t)0x4EBFE8A4, + (q31_t)0x9AF891DB, (q31_t)0x4E984229, (q31_t)0x9AD9BC71, + (q31_t)0x4E708F8F, (q31_t)0x9ABAF6A0, (q31_t)0x4E48D0DC, + (q31_t)0x9A9C406D, (q31_t)0x4E210617, (q31_t)0x9A7D99DD, + (q31_t)0x4DF92F45, (q31_t)0x9A5F02F5, (q31_t)0x4DD14C6E, + (q31_t)0x9A407BB8, (q31_t)0x4DA95D96, (q31_t)0x9A22042C, + (q31_t)0x4D8162C4, (q31_t)0x9A039C56, (q31_t)0x4D595BFE, + (q31_t)0x99E5443A, (q31_t)0x4D31494B, (q31_t)0x99C6FBDE, + (q31_t)0x4D092AB0, (q31_t)0x99A8C344, (q31_t)0x4CE10034, + (q31_t)0x998A9A73, (q31_t)0x4CB8C9DD, (q31_t)0x996C816F, + (q31_t)0x4C9087B1, (q31_t)0x994E783C, (q31_t)0x4C6839B6, + (q31_t)0x99307EE0, (q31_t)0x4C3FDFF3, (q31_t)0x9912955E, + (q31_t)0x4C177A6E, (q31_t)0x98F4BBBC, (q31_t)0x4BEF092D, + (q31_t)0x98D6F1FE, (q31_t)0x4BC68C36, (q31_t)0x98B93828, + (q31_t)0x4B9E038F, (q31_t)0x989B8E3F, (q31_t)0x4B756F3F, + (q31_t)0x987DF449, (q31_t)0x4B4CCF4D, (q31_t)0x98606A48, + (q31_t)0x4B2423BD, (q31_t)0x9842F043, (q31_t)0x4AFB6C97, + (q31_t)0x9825863D, (q31_t)0x4AD2A9E1, (q31_t)0x98082C3B, + (q31_t)0x4AA9DBA1, (q31_t)0x97EAE241, (q31_t)0x4A8101DE, + (q31_t)0x97CDA855, (q31_t)0x4A581C9D, (q31_t)0x97B07E7A, + (q31_t)0x4A2F2BE5, (q31_t)0x979364B5, (q31_t)0x4A062FBD, + (q31_t)0x97765B0A, (q31_t)0x49DD282A, (q31_t)0x9759617E, + (q31_t)0x49B41533, (q31_t)0x973C7816, (q31_t)0x498AF6DE, + (q31_t)0x971F9ED6, (q31_t)0x4961CD32, (q31_t)0x9702D5C2, + (q31_t)0x49389836, (q31_t)0x96E61CDF, (q31_t)0x490F57EE, + (q31_t)0x96C97431, (q31_t)0x48E60C62, (q31_t)0x96ACDBBD, + (q31_t)0x48BCB598, (q31_t)0x96905387, (q31_t)0x48935397, + (q31_t)0x9673DB94, (q31_t)0x4869E664, (q31_t)0x965773E7, + (q31_t)0x48406E07, (q31_t)0x963B1C85, (q31_t)0x4816EA85, + (q31_t)0x961ED573, (q31_t)0x47ED5BE6, (q31_t)0x96029EB5, + (q31_t)0x47C3C22E, (q31_t)0x95E6784F, (q31_t)0x479A1D66, + (q31_t)0x95CA6246, (q31_t)0x47706D93, (q31_t)0x95AE5C9E, + (q31_t)0x4746B2BC, (q31_t)0x9592675B, (q31_t)0x471CECE6, + (q31_t)0x95768282, (q31_t)0x46F31C1A, (q31_t)0x955AAE17, + (q31_t)0x46C9405C, (q31_t)0x953EEA1E, (q31_t)0x469F59B4, + (q31_t)0x9523369B, (q31_t)0x46756827, (q31_t)0x95079393, + (q31_t)0x464B6BBD, (q31_t)0x94EC010B, (q31_t)0x4621647C, + (q31_t)0x94D07F05, (q31_t)0x45F7526B, (q31_t)0x94B50D87, + (q31_t)0x45CD358F, (q31_t)0x9499AC95, (q31_t)0x45A30DF0, + (q31_t)0x947E5C32, (q31_t)0x4578DB93, (q31_t)0x94631C64, + (q31_t)0x454E9E80, (q31_t)0x9447ED2F, (q31_t)0x452456BC, + (q31_t)0x942CCE95, (q31_t)0x44FA044F, (q31_t)0x9411C09D, + (q31_t)0x44CFA73F, (q31_t)0x93F6C34A, (q31_t)0x44A53F93, + (q31_t)0x93DBD69F, (q31_t)0x447ACD50, (q31_t)0x93C0FAA2, + (q31_t)0x4450507E, (q31_t)0x93A62F56, (q31_t)0x4425C923, + (q31_t)0x938B74C0, (q31_t)0x43FB3745, (q31_t)0x9370CAE4, + (q31_t)0x43D09AEC, (q31_t)0x935631C5, (q31_t)0x43A5F41E, + (q31_t)0x933BA968, (q31_t)0x437B42E1, (q31_t)0x932131D1, + (q31_t)0x4350873C, (q31_t)0x9306CB04, (q31_t)0x4325C135, + (q31_t)0x92EC7505, (q31_t)0x42FAF0D4, (q31_t)0x92D22FD8, + (q31_t)0x42D0161E, (q31_t)0x92B7FB82, (q31_t)0x42A5311A, + (q31_t)0x929DD805, (q31_t)0x427A41D0, (q31_t)0x9283C567, + (q31_t)0x424F4845, (q31_t)0x9269C3AC, (q31_t)0x42244480, + (q31_t)0x924FD2D6, (q31_t)0x41F93688, (q31_t)0x9235F2EB, + (q31_t)0x41CE1E64, (q31_t)0x921C23EE, (q31_t)0x41A2FC1A, + (q31_t)0x920265E4, (q31_t)0x4177CFB0, (q31_t)0x91E8B8D0, + (q31_t)0x414C992E, (q31_t)0x91CF1CB6, (q31_t)0x4121589A, + (q31_t)0x91B5919A, (q31_t)0x40F60DFB, (q31_t)0x919C1780, + (q31_t)0x40CAB957, (q31_t)0x9182AE6C, (q31_t)0x409F5AB6, + (q31_t)0x91695663, (q31_t)0x4073F21D, (q31_t)0x91500F67, + (q31_t)0x40487F93, (q31_t)0x9136D97D, (q31_t)0x401D0320, + (q31_t)0x911DB4A8, (q31_t)0x3FF17CCA, (q31_t)0x9104A0ED, + (q31_t)0x3FC5EC97, (q31_t)0x90EB9E50, (q31_t)0x3F9A528F, + (q31_t)0x90D2ACD3, (q31_t)0x3F6EAEB8, (q31_t)0x90B9CC7C, + (q31_t)0x3F430118, (q31_t)0x90A0FD4E, (q31_t)0x3F1749B7, + (q31_t)0x90883F4C, (q31_t)0x3EEB889C, (q31_t)0x906F927B, + (q31_t)0x3EBFBDCC, (q31_t)0x9056F6DF, (q31_t)0x3E93E94F, + (q31_t)0x903E6C7A, (q31_t)0x3E680B2C, (q31_t)0x9025F352, + (q31_t)0x3E3C2369, (q31_t)0x900D8B69, (q31_t)0x3E10320D, + (q31_t)0x8FF534C4, (q31_t)0x3DE4371F, (q31_t)0x8FDCEF66, + (q31_t)0x3DB832A5, (q31_t)0x8FC4BB53, (q31_t)0x3D8C24A7, + (q31_t)0x8FAC988E, (q31_t)0x3D600D2B, (q31_t)0x8F94871D, + (q31_t)0x3D33EC39, (q31_t)0x8F7C8701, (q31_t)0x3D07C1D5, + (q31_t)0x8F64983F, (q31_t)0x3CDB8E09, (q31_t)0x8F4CBADB, + (q31_t)0x3CAF50DA, (q31_t)0x8F34EED8, (q31_t)0x3C830A4F, + (q31_t)0x8F1D343A, (q31_t)0x3C56BA70, (q31_t)0x8F058B04, + (q31_t)0x3C2A6142, (q31_t)0x8EEDF33B, (q31_t)0x3BFDFECD, + (q31_t)0x8ED66CE1, (q31_t)0x3BD19317, (q31_t)0x8EBEF7FB, + (q31_t)0x3BA51E29, (q31_t)0x8EA7948C, (q31_t)0x3B78A007, + (q31_t)0x8E904298, (q31_t)0x3B4C18BA, (q31_t)0x8E790222, + (q31_t)0x3B1F8847, (q31_t)0x8E61D32D, (q31_t)0x3AF2EEB7, + (q31_t)0x8E4AB5BF, (q31_t)0x3AC64C0F, (q31_t)0x8E33A9D9, + (q31_t)0x3A99A057, (q31_t)0x8E1CAF80, (q31_t)0x3A6CEB95, + (q31_t)0x8E05C6B7, (q31_t)0x3A402DD1, (q31_t)0x8DEEEF82, + (q31_t)0x3A136712, (q31_t)0x8DD829E4, (q31_t)0x39E6975D, + (q31_t)0x8DC175E0, (q31_t)0x39B9BEBB, (q31_t)0x8DAAD37B, + (q31_t)0x398CDD32, (q31_t)0x8D9442B7, (q31_t)0x395FF2C9, + (q31_t)0x8D7DC399, (q31_t)0x3932FF87, (q31_t)0x8D675623, + (q31_t)0x39060372, (q31_t)0x8D50FA59, (q31_t)0x38D8FE93, + (q31_t)0x8D3AB03F, (q31_t)0x38ABF0EF, (q31_t)0x8D2477D8, + (q31_t)0x387EDA8E, (q31_t)0x8D0E5127, (q31_t)0x3851BB76, + (q31_t)0x8CF83C30, (q31_t)0x382493B0, (q31_t)0x8CE238F6, + (q31_t)0x37F76340, (q31_t)0x8CCC477D, (q31_t)0x37CA2A30, + (q31_t)0x8CB667C7, (q31_t)0x379CE884, (q31_t)0x8CA099D9, + (q31_t)0x376F9E46, (q31_t)0x8C8ADDB6, (q31_t)0x37424B7A, + (q31_t)0x8C753361, (q31_t)0x3714F02A, (q31_t)0x8C5F9ADD, + (q31_t)0x36E78C5A, (q31_t)0x8C4A142F, (q31_t)0x36BA2013, + (q31_t)0x8C349F58, (q31_t)0x368CAB5C, (q31_t)0x8C1F3C5C, + (q31_t)0x365F2E3B, (q31_t)0x8C09EB40, (q31_t)0x3631A8B7, + (q31_t)0x8BF4AC05, (q31_t)0x36041AD9, (q31_t)0x8BDF7EAF, + (q31_t)0x35D684A5, (q31_t)0x8BCA6342, (q31_t)0x35A8E624, + (q31_t)0x8BB559C1, (q31_t)0x357B3F5D, (q31_t)0x8BA0622F, + (q31_t)0x354D9056, (q31_t)0x8B8B7C8F, (q31_t)0x351FD917, + (q31_t)0x8B76A8E4, (q31_t)0x34F219A7, (q31_t)0x8B61E732, + (q31_t)0x34C4520D, (q31_t)0x8B4D377C, (q31_t)0x3496824F, + (q31_t)0x8B3899C5, (q31_t)0x3468AA76, (q31_t)0x8B240E10, + (q31_t)0x343ACA87, (q31_t)0x8B0F9461, (q31_t)0x340CE28A, + (q31_t)0x8AFB2CBA, (q31_t)0x33DEF287, (q31_t)0x8AE6D71F, + (q31_t)0x33B0FA84, (q31_t)0x8AD29393, (q31_t)0x3382FA88, + (q31_t)0x8ABE6219, (q31_t)0x3354F29A, (q31_t)0x8AAA42B4, + (q31_t)0x3326E2C2, (q31_t)0x8A963567, (q31_t)0x32F8CB07, + (q31_t)0x8A823A35, (q31_t)0x32CAAB6F, (q31_t)0x8A6E5122, + (q31_t)0x329C8402, (q31_t)0x8A5A7A30, (q31_t)0x326E54C7, + (q31_t)0x8A46B563, (q31_t)0x32401DC5, (q31_t)0x8A3302BD, + (q31_t)0x3211DF03, (q31_t)0x8A1F6242, (q31_t)0x31E39889, + (q31_t)0x8A0BD3F5, (q31_t)0x31B54A5D, (q31_t)0x89F857D8, + (q31_t)0x3186F487, (q31_t)0x89E4EDEE, (q31_t)0x3158970D, + (q31_t)0x89D1963C, (q31_t)0x312A31F8, (q31_t)0x89BE50C3, + (q31_t)0x30FBC54D, (q31_t)0x89AB1D86, (q31_t)0x30CD5114, + (q31_t)0x8997FC89, (q31_t)0x309ED555, (q31_t)0x8984EDCF, + (q31_t)0x30705217, (q31_t)0x8971F15A, (q31_t)0x3041C760, + (q31_t)0x895F072D, (q31_t)0x30133538, (q31_t)0x894C2F4C, + (q31_t)0x2FE49BA6, (q31_t)0x893969B9, (q31_t)0x2FB5FAB2, + (q31_t)0x8926B677, (q31_t)0x2F875262, (q31_t)0x89141589, + (q31_t)0x2F58A2BD, (q31_t)0x890186F1, (q31_t)0x2F29EBCC, + (q31_t)0x88EF0AB4, (q31_t)0x2EFB2D94, (q31_t)0x88DCA0D3, + (q31_t)0x2ECC681E, (q31_t)0x88CA4951, (q31_t)0x2E9D9B70, + (q31_t)0x88B80431, (q31_t)0x2E6EC792, (q31_t)0x88A5D177, + (q31_t)0x2E3FEC8B, (q31_t)0x8893B124, (q31_t)0x2E110A62, + (q31_t)0x8881A33C, (q31_t)0x2DE2211E, (q31_t)0x886FA7C2, + (q31_t)0x2DB330C7, (q31_t)0x885DBEB7, (q31_t)0x2D843963, + (q31_t)0x884BE820, (q31_t)0x2D553AFB, (q31_t)0x883A23FE, + (q31_t)0x2D263595, (q31_t)0x88287255, (q31_t)0x2CF72939, + (q31_t)0x8816D327, (q31_t)0x2CC815ED, (q31_t)0x88054677, + (q31_t)0x2C98FBBA, (q31_t)0x87F3CC47, (q31_t)0x2C69DAA6, + (q31_t)0x87E2649B, (q31_t)0x2C3AB2B9, (q31_t)0x87D10F75, + (q31_t)0x2C0B83F9, (q31_t)0x87BFCCD7, (q31_t)0x2BDC4E6F, + (q31_t)0x87AE9CC5, (q31_t)0x2BAD1221, (q31_t)0x879D7F40, + (q31_t)0x2B7DCF17, (q31_t)0x878C744C, (q31_t)0x2B4E8558, + (q31_t)0x877B7BEC, (q31_t)0x2B1F34EB, (q31_t)0x876A9621, + (q31_t)0x2AEFDDD8, (q31_t)0x8759C2EF, (q31_t)0x2AC08025, + (q31_t)0x87490257, (q31_t)0x2A911BDB, (q31_t)0x8738545E, + (q31_t)0x2A61B101, (q31_t)0x8727B904, (q31_t)0x2A323F9D, + (q31_t)0x8717304E, (q31_t)0x2A02C7B8, (q31_t)0x8706BA3C, + (q31_t)0x29D34958, (q31_t)0x86F656D3, (q31_t)0x29A3C484, + (q31_t)0x86E60614, (q31_t)0x29743945, (q31_t)0x86D5C802, + (q31_t)0x2944A7A2, (q31_t)0x86C59C9F, (q31_t)0x29150FA1, + (q31_t)0x86B583EE, (q31_t)0x28E5714A, (q31_t)0x86A57DF1, + (q31_t)0x28B5CCA5, (q31_t)0x86958AAB, (q31_t)0x288621B9, + (q31_t)0x8685AA1F, (q31_t)0x2856708C, (q31_t)0x8675DC4E, + (q31_t)0x2826B928, (q31_t)0x8666213C, (q31_t)0x27F6FB92, + (q31_t)0x865678EA, (q31_t)0x27C737D2, (q31_t)0x8646E35B, + (q31_t)0x27976DF1, (q31_t)0x86376092, (q31_t)0x27679DF4, + (q31_t)0x8627F090, (q31_t)0x2737C7E3, (q31_t)0x86189359, + (q31_t)0x2707EBC6, (q31_t)0x860948EE, (q31_t)0x26D809A5, + (q31_t)0x85FA1152, (q31_t)0x26A82185, (q31_t)0x85EAEC88, + (q31_t)0x26783370, (q31_t)0x85DBDA91, (q31_t)0x26483F6C, + (q31_t)0x85CCDB70, (q31_t)0x26184581, (q31_t)0x85BDEF27, + (q31_t)0x25E845B5, (q31_t)0x85AF15B9, (q31_t)0x25B84012, + (q31_t)0x85A04F28, (q31_t)0x2588349D, (q31_t)0x85919B75, + (q31_t)0x2558235E, (q31_t)0x8582FAA4, (q31_t)0x25280C5D, + (q31_t)0x85746CB7, (q31_t)0x24F7EFA1, (q31_t)0x8565F1B0, + (q31_t)0x24C7CD32, (q31_t)0x85578991, (q31_t)0x2497A517, + (q31_t)0x8549345C, (q31_t)0x24677757, (q31_t)0x853AF214, + (q31_t)0x243743FA, (q31_t)0x852CC2BA, (q31_t)0x24070B07, + (q31_t)0x851EA652, (q31_t)0x23D6CC86, (q31_t)0x85109CDC, + (q31_t)0x23A6887E, (q31_t)0x8502A65C, (q31_t)0x23763EF7, + (q31_t)0x84F4C2D3, (q31_t)0x2345EFF7, (q31_t)0x84E6F244, + (q31_t)0x23159B87, (q31_t)0x84D934B0, (q31_t)0x22E541AE, + (q31_t)0x84CB8A1B, (q31_t)0x22B4E274, (q31_t)0x84BDF285, + (q31_t)0x22847DDF, (q31_t)0x84B06DF1, (q31_t)0x225413F8, + (q31_t)0x84A2FC62, (q31_t)0x2223A4C5, (q31_t)0x84959DD9, + (q31_t)0x21F3304E, (q31_t)0x84885257, (q31_t)0x21C2B69C, + (q31_t)0x847B19E1, (q31_t)0x219237B4, (q31_t)0x846DF476, + (q31_t)0x2161B39F, (q31_t)0x8460E21A, (q31_t)0x21312A65, + (q31_t)0x8453E2CE, (q31_t)0x21009C0B, (q31_t)0x8446F695, + (q31_t)0x20D0089B, (q31_t)0x843A1D70, (q31_t)0x209F701C, + (q31_t)0x842D5761, (q31_t)0x206ED295, (q31_t)0x8420A46B, + (q31_t)0x203E300D, (q31_t)0x8414048F, (q31_t)0x200D888C, + (q31_t)0x840777CF, (q31_t)0x1FDCDC1A, (q31_t)0x83FAFE2E, + (q31_t)0x1FAC2ABF, (q31_t)0x83EE97AC, (q31_t)0x1F7B7480, + (q31_t)0x83E2444D, (q31_t)0x1F4AB967, (q31_t)0x83D60411, + (q31_t)0x1F19F97B, (q31_t)0x83C9D6FB, (q31_t)0x1EE934C2, + (q31_t)0x83BDBD0D, (q31_t)0x1EB86B46, (q31_t)0x83B1B649, + (q31_t)0x1E879D0C, (q31_t)0x83A5C2B0, (q31_t)0x1E56CA1E, + (q31_t)0x8399E244, (q31_t)0x1E25F281, (q31_t)0x838E1507, + (q31_t)0x1DF5163F, (q31_t)0x83825AFB, (q31_t)0x1DC4355D, + (q31_t)0x8376B422, (q31_t)0x1D934FE5, (q31_t)0x836B207D, + (q31_t)0x1D6265DD, (q31_t)0x835FA00E, (q31_t)0x1D31774D, + (q31_t)0x835432D8, (q31_t)0x1D00843C, (q31_t)0x8348D8DB, + (q31_t)0x1CCF8CB3, (q31_t)0x833D921A, (q31_t)0x1C9E90B8, + (q31_t)0x83325E97, (q31_t)0x1C6D9053, (q31_t)0x83273E52, + (q31_t)0x1C3C8B8C, (q31_t)0x831C314E, (q31_t)0x1C0B826A, + (q31_t)0x8311378C, (q31_t)0x1BDA74F5, (q31_t)0x8306510F, + (q31_t)0x1BA96334, (q31_t)0x82FB7DD8, (q31_t)0x1B784D30, + (q31_t)0x82F0BDE8, (q31_t)0x1B4732EF, (q31_t)0x82E61141, + (q31_t)0x1B161479, (q31_t)0x82DB77E5, (q31_t)0x1AE4F1D6, + (q31_t)0x82D0F1D5, (q31_t)0x1AB3CB0C, (q31_t)0x82C67F13, + (q31_t)0x1A82A025, (q31_t)0x82BC1FA1, (q31_t)0x1A517127, + (q31_t)0x82B1D381, (q31_t)0x1A203E1B, (q31_t)0x82A79AB3, + (q31_t)0x19EF0706, (q31_t)0x829D753A, (q31_t)0x19BDCBF2, + (q31_t)0x82936316, (q31_t)0x198C8CE6, (q31_t)0x8289644A, + (q31_t)0x195B49E9, (q31_t)0x827F78D8, (q31_t)0x192A0303, + (q31_t)0x8275A0C0, (q31_t)0x18F8B83C, (q31_t)0x826BDC04, + (q31_t)0x18C7699B, (q31_t)0x82622AA5, (q31_t)0x18961727, + (q31_t)0x82588CA6, (q31_t)0x1864C0E9, (q31_t)0x824F0208, + (q31_t)0x183366E8, (q31_t)0x82458ACB, (q31_t)0x1802092C, + (q31_t)0x823C26F2, (q31_t)0x17D0A7BB, (q31_t)0x8232D67E, + (q31_t)0x179F429F, (q31_t)0x82299971, (q31_t)0x176DD9DE, + (q31_t)0x82206FCB, (q31_t)0x173C6D80, (q31_t)0x8217598F, + (q31_t)0x170AFD8D, (q31_t)0x820E56BE, (q31_t)0x16D98A0C, + (q31_t)0x82056758, (q31_t)0x16A81305, (q31_t)0x81FC8B60, + (q31_t)0x1676987F, (q31_t)0x81F3C2D7, (q31_t)0x16451A83, + (q31_t)0x81EB0DBD, (q31_t)0x16139917, (q31_t)0x81E26C16, + (q31_t)0x15E21444, (q31_t)0x81D9DDE1, (q31_t)0x15B08C11, + (q31_t)0x81D16320, (q31_t)0x157F0086, (q31_t)0x81C8FBD5, + (q31_t)0x154D71AA, (q31_t)0x81C0A801, (q31_t)0x151BDF85, + (q31_t)0x81B867A4, (q31_t)0x14EA4A1F, (q31_t)0x81B03AC1, + (q31_t)0x14B8B17F, (q31_t)0x81A82159, (q31_t)0x148715AD, + (q31_t)0x81A01B6C, (q31_t)0x145576B1, (q31_t)0x819828FD, + (q31_t)0x1423D492, (q31_t)0x81904A0C, (q31_t)0x13F22F57, + (q31_t)0x81887E9A, (q31_t)0x13C0870A, (q31_t)0x8180C6A9, + (q31_t)0x138EDBB0, (q31_t)0x8179223A, (q31_t)0x135D2D53, + (q31_t)0x8171914E, (q31_t)0x132B7BF9, (q31_t)0x816A13E6, + (q31_t)0x12F9C7AA, (q31_t)0x8162AA03, (q31_t)0x12C8106E, + (q31_t)0x815B53A8, (q31_t)0x1296564D, (q31_t)0x815410D3, + (q31_t)0x1264994E, (q31_t)0x814CE188, (q31_t)0x1232D978, + (q31_t)0x8145C5C6, (q31_t)0x120116D4, (q31_t)0x813EBD90, + (q31_t)0x11CF516A, (q31_t)0x8137C8E6, (q31_t)0x119D8940, + (q31_t)0x8130E7C8, (q31_t)0x116BBE5F, (q31_t)0x812A1A39, + (q31_t)0x1139F0CE, (q31_t)0x81236039, (q31_t)0x11082096, + (q31_t)0x811CB9CA, (q31_t)0x10D64DBC, (q31_t)0x811626EC, + (q31_t)0x10A4784A, (q31_t)0x810FA7A0, (q31_t)0x1072A047, + (q31_t)0x81093BE8, (q31_t)0x1040C5BB, (q31_t)0x8102E3C3, + (q31_t)0x100EE8AD, (q31_t)0x80FC9F35, (q31_t)0x0FDD0925, + (q31_t)0x80F66E3C, (q31_t)0x0FAB272B, (q31_t)0x80F050DB, + (q31_t)0x0F7942C6, (q31_t)0x80EA4712, (q31_t)0x0F475BFE, + (q31_t)0x80E450E2, (q31_t)0x0F1572DC, (q31_t)0x80DE6E4C, + (q31_t)0x0EE38765, (q31_t)0x80D89F51, (q31_t)0x0EB199A3, + (q31_t)0x80D2E3F1, (q31_t)0x0E7FA99D, (q31_t)0x80CD3C2F, + (q31_t)0x0E4DB75B, (q31_t)0x80C7A80A, (q31_t)0x0E1BC2E3, + (q31_t)0x80C22783, (q31_t)0x0DE9CC3F, (q31_t)0x80BCBA9C, + (q31_t)0x0DB7D376, (q31_t)0x80B76155, (q31_t)0x0D85D88F, + (q31_t)0x80B21BAF, (q31_t)0x0D53DB92, (q31_t)0x80ACE9AB, + (q31_t)0x0D21DC87, (q31_t)0x80A7CB49, (q31_t)0x0CEFDB75, + (q31_t)0x80A2C08B, (q31_t)0x0CBDD865, (q31_t)0x809DC970, + (q31_t)0x0C8BD35E, (q31_t)0x8098E5FB, (q31_t)0x0C59CC67, + (q31_t)0x8094162B, (q31_t)0x0C27C389, (q31_t)0x808F5A02, + (q31_t)0x0BF5B8CB, (q31_t)0x808AB180, (q31_t)0x0BC3AC35, + (q31_t)0x80861CA5, (q31_t)0x0B919DCE, (q31_t)0x80819B74, + (q31_t)0x0B5F8D9F, (q31_t)0x807D2DEB, (q31_t)0x0B2D7BAE, + (q31_t)0x8078D40D, (q31_t)0x0AFB6805, (q31_t)0x80748DD9, + (q31_t)0x0AC952AA, (q31_t)0x80705B50, (q31_t)0x0A973BA5, + (q31_t)0x806C3C73, (q31_t)0x0A6522FE, (q31_t)0x80683143, + (q31_t)0x0A3308BC, (q31_t)0x806439C0, (q31_t)0x0A00ECE8, + (q31_t)0x806055EA, (q31_t)0x09CECF89, (q31_t)0x805C85C3, + (q31_t)0x099CB0A7, (q31_t)0x8058C94C, (q31_t)0x096A9049, + (q31_t)0x80552083, (q31_t)0x09386E77, (q31_t)0x80518B6B, + (q31_t)0x09064B3A, (q31_t)0x804E0A03, (q31_t)0x08D42698, + (q31_t)0x804A9C4D, (q31_t)0x08A2009A, (q31_t)0x80474248, + (q31_t)0x086FD947, (q31_t)0x8043FBF6, (q31_t)0x083DB0A7, + (q31_t)0x8040C956, (q31_t)0x080B86C1, (q31_t)0x803DAA69, + (q31_t)0x07D95B9E, (q31_t)0x803A9F31, (q31_t)0x07A72F45, + (q31_t)0x8037A7AC, (q31_t)0x077501BE, (q31_t)0x8034C3DC, + (q31_t)0x0742D310, (q31_t)0x8031F3C1, (q31_t)0x0710A344, + (q31_t)0x802F375C, (q31_t)0x06DE7261, (q31_t)0x802C8EAD, + (q31_t)0x06AC406F, (q31_t)0x8029F9B4, (q31_t)0x067A0D75, + (q31_t)0x80277872, (q31_t)0x0647D97C, (q31_t)0x80250AE7, + (q31_t)0x0615A48A, (q31_t)0x8022B113, (q31_t)0x05E36EA9, + (q31_t)0x80206AF8, (q31_t)0x05B137DF, (q31_t)0x801E3894, + (q31_t)0x057F0034, (q31_t)0x801C19E9, (q31_t)0x054CC7B0, + (q31_t)0x801A0EF7, (q31_t)0x051A8E5C, (q31_t)0x801817BF, + (q31_t)0x04E8543D, (q31_t)0x80163440, (q31_t)0x04B6195D, + (q31_t)0x8014647A, (q31_t)0x0483DDC3, (q31_t)0x8012A86F, + (q31_t)0x0451A176, (q31_t)0x8011001E, (q31_t)0x041F647F, + (q31_t)0x800F6B88, (q31_t)0x03ED26E6, (q31_t)0x800DEAAC, + (q31_t)0x03BAE8B1, (q31_t)0x800C7D8C, (q31_t)0x0388A9E9, + (q31_t)0x800B2427, (q31_t)0x03566A96, (q31_t)0x8009DE7D, + (q31_t)0x03242ABF, (q31_t)0x8008AC90, (q31_t)0x02F1EA6B, + (q31_t)0x80078E5E, (q31_t)0x02BFA9A4, (q31_t)0x800683E8, + (q31_t)0x028D6870, (q31_t)0x80058D2E, (q31_t)0x025B26D7, + (q31_t)0x8004AA31, (q31_t)0x0228E4E1, (q31_t)0x8003DAF0, + (q31_t)0x01F6A296, (q31_t)0x80031F6C, (q31_t)0x01C45FFE, + (q31_t)0x800277A5, (q31_t)0x01921D1F, (q31_t)0x8001E39B, + (q31_t)0x015FDA03, (q31_t)0x8001634D, (q31_t)0x012D96B0, + (q31_t)0x8000F6BD, (q31_t)0x00FB532F, (q31_t)0x80009DE9, + (q31_t)0x00C90F88, (q31_t)0x800058D3, (q31_t)0x0096CBC1, + (q31_t)0x8000277A, (q31_t)0x006487E3, (q31_t)0x800009DE, + (q31_t)0x003243F5, (q31_t)0x80000000, (q31_t)0x00000000, + (q31_t)0x800009DE, (q31_t)0xFFCDBC0A, (q31_t)0x8000277A, + (q31_t)0xFF9B781D, (q31_t)0x800058D3, (q31_t)0xFF69343E, + (q31_t)0x80009DE9, (q31_t)0xFF36F078, (q31_t)0x8000F6BD, + (q31_t)0xFF04ACD0, (q31_t)0x8001634D, (q31_t)0xFED2694F, + (q31_t)0x8001E39B, (q31_t)0xFEA025FC, (q31_t)0x800277A5, + (q31_t)0xFE6DE2E0, (q31_t)0x80031F6C, (q31_t)0xFE3BA001, + (q31_t)0x8003DAF0, (q31_t)0xFE095D69, (q31_t)0x8004AA31, + (q31_t)0xFDD71B1E, (q31_t)0x80058D2E, (q31_t)0xFDA4D928, + (q31_t)0x800683E8, (q31_t)0xFD72978F, (q31_t)0x80078E5E, + (q31_t)0xFD40565B, (q31_t)0x8008AC90, (q31_t)0xFD0E1594, + (q31_t)0x8009DE7D, (q31_t)0xFCDBD541, (q31_t)0x800B2427, + (q31_t)0xFCA99569, (q31_t)0x800C7D8C, (q31_t)0xFC775616, + (q31_t)0x800DEAAC, (q31_t)0xFC45174E, (q31_t)0x800F6B88, + (q31_t)0xFC12D919, (q31_t)0x8011001E, (q31_t)0xFBE09B80, + (q31_t)0x8012A86F, (q31_t)0xFBAE5E89, (q31_t)0x8014647A, + (q31_t)0xFB7C223C, (q31_t)0x80163440, (q31_t)0xFB49E6A2, + (q31_t)0x801817BF, (q31_t)0xFB17ABC2, (q31_t)0x801A0EF7, + (q31_t)0xFAE571A4, (q31_t)0x801C19E9, (q31_t)0xFAB3384F, + (q31_t)0x801E3894, (q31_t)0xFA80FFCB, (q31_t)0x80206AF8, + (q31_t)0xFA4EC820, (q31_t)0x8022B113, (q31_t)0xFA1C9156, + (q31_t)0x80250AE7, (q31_t)0xF9EA5B75, (q31_t)0x80277872, + (q31_t)0xF9B82683, (q31_t)0x8029F9B4, (q31_t)0xF985F28A, + (q31_t)0x802C8EAD, (q31_t)0xF953BF90, (q31_t)0x802F375C, + (q31_t)0xF9218D9E, (q31_t)0x8031F3C1, (q31_t)0xF8EF5CBB, + (q31_t)0x8034C3DC, (q31_t)0xF8BD2CEF, (q31_t)0x8037A7AC, + (q31_t)0xF88AFE41, (q31_t)0x803A9F31, (q31_t)0xF858D0BA, + (q31_t)0x803DAA69, (q31_t)0xF826A461, (q31_t)0x8040C956, + (q31_t)0xF7F4793E, (q31_t)0x8043FBF6, (q31_t)0xF7C24F58, + (q31_t)0x80474248, (q31_t)0xF79026B8, (q31_t)0x804A9C4D, + (q31_t)0xF75DFF65, (q31_t)0x804E0A03, (q31_t)0xF72BD967, + (q31_t)0x80518B6B, (q31_t)0xF6F9B4C5, (q31_t)0x80552083, + (q31_t)0xF6C79188, (q31_t)0x8058C94C, (q31_t)0xF6956FB6, + (q31_t)0x805C85C3, (q31_t)0xF6634F58, (q31_t)0x806055EA, + (q31_t)0xF6313076, (q31_t)0x806439C0, (q31_t)0xF5FF1317, + (q31_t)0x80683143, (q31_t)0xF5CCF743, (q31_t)0x806C3C73, + (q31_t)0xF59ADD01, (q31_t)0x80705B50, (q31_t)0xF568C45A, + (q31_t)0x80748DD9, (q31_t)0xF536AD55, (q31_t)0x8078D40D, + (q31_t)0xF50497FA, (q31_t)0x807D2DEB, (q31_t)0xF4D28451, + (q31_t)0x80819B74, (q31_t)0xF4A07260, (q31_t)0x80861CA5, + (q31_t)0xF46E6231, (q31_t)0x808AB180, (q31_t)0xF43C53CA, + (q31_t)0x808F5A02, (q31_t)0xF40A4734, (q31_t)0x8094162B, + (q31_t)0xF3D83C76, (q31_t)0x8098E5FB, (q31_t)0xF3A63398, + (q31_t)0x809DC970, (q31_t)0xF3742CA1, (q31_t)0x80A2C08B, + (q31_t)0xF342279A, (q31_t)0x80A7CB49, (q31_t)0xF310248A, + (q31_t)0x80ACE9AB, (q31_t)0xF2DE2378, (q31_t)0x80B21BAF, + (q31_t)0xF2AC246D, (q31_t)0x80B76155, (q31_t)0xF27A2770, + (q31_t)0x80BCBA9C, (q31_t)0xF2482C89, (q31_t)0x80C22783, + (q31_t)0xF21633C0, (q31_t)0x80C7A80A, (q31_t)0xF1E43D1C, + (q31_t)0x80CD3C2F, (q31_t)0xF1B248A5, (q31_t)0x80D2E3F1, + (q31_t)0xF1805662, (q31_t)0x80D89F51, (q31_t)0xF14E665C, + (q31_t)0x80DE6E4C, (q31_t)0xF11C789A, (q31_t)0x80E450E2, + (q31_t)0xF0EA8D23, (q31_t)0x80EA4712, (q31_t)0xF0B8A401, + (q31_t)0x80F050DB, (q31_t)0xF086BD39, (q31_t)0x80F66E3C, + (q31_t)0xF054D8D4, (q31_t)0x80FC9F35, (q31_t)0xF022F6DA, + (q31_t)0x8102E3C3, (q31_t)0xEFF11752, (q31_t)0x81093BE8, + (q31_t)0xEFBF3A44, (q31_t)0x810FA7A0, (q31_t)0xEF8D5FB8, + (q31_t)0x811626EC, (q31_t)0xEF5B87B5, (q31_t)0x811CB9CA, + (q31_t)0xEF29B243, (q31_t)0x81236039, (q31_t)0xEEF7DF6A, + (q31_t)0x812A1A39, (q31_t)0xEEC60F31, (q31_t)0x8130E7C8, + (q31_t)0xEE9441A0, (q31_t)0x8137C8E6, (q31_t)0xEE6276BF, + (q31_t)0x813EBD90, (q31_t)0xEE30AE95, (q31_t)0x8145C5C6, + (q31_t)0xEDFEE92B, (q31_t)0x814CE188, (q31_t)0xEDCD2687, + (q31_t)0x815410D3, (q31_t)0xED9B66B2, (q31_t)0x815B53A8, + (q31_t)0xED69A9B2, (q31_t)0x8162AA03, (q31_t)0xED37EF91, + (q31_t)0x816A13E6, (q31_t)0xED063855, (q31_t)0x8171914E, + (q31_t)0xECD48406, (q31_t)0x8179223A, (q31_t)0xECA2D2AC, + (q31_t)0x8180C6A9, (q31_t)0xEC71244F, (q31_t)0x81887E9A, + (q31_t)0xEC3F78F5, (q31_t)0x81904A0C, (q31_t)0xEC0DD0A8, + (q31_t)0x819828FD, (q31_t)0xEBDC2B6D, (q31_t)0x81A01B6C, + (q31_t)0xEBAA894E, (q31_t)0x81A82159, (q31_t)0xEB78EA52, + (q31_t)0x81B03AC1, (q31_t)0xEB474E80, (q31_t)0x81B867A4, + (q31_t)0xEB15B5E0, (q31_t)0x81C0A801, (q31_t)0xEAE4207A, + (q31_t)0x81C8FBD5, (q31_t)0xEAB28E55, (q31_t)0x81D16320, + (q31_t)0xEA80FF79, (q31_t)0x81D9DDE1, (q31_t)0xEA4F73EE, + (q31_t)0x81E26C16, (q31_t)0xEA1DEBBB, (q31_t)0x81EB0DBD, + (q31_t)0xE9EC66E8, (q31_t)0x81F3C2D7, (q31_t)0xE9BAE57C, + (q31_t)0x81FC8B60, (q31_t)0xE9896780, (q31_t)0x82056758, + (q31_t)0xE957ECFB, (q31_t)0x820E56BE, (q31_t)0xE92675F4, + (q31_t)0x8217598F, (q31_t)0xE8F50273, (q31_t)0x82206FCB, + (q31_t)0xE8C3927F, (q31_t)0x82299971, (q31_t)0xE8922621, + (q31_t)0x8232D67E, (q31_t)0xE860BD60, (q31_t)0x823C26F2, + (q31_t)0xE82F5844, (q31_t)0x82458ACB, (q31_t)0xE7FDF6D3, + (q31_t)0x824F0208, (q31_t)0xE7CC9917, (q31_t)0x82588CA6, + (q31_t)0xE79B3F16, (q31_t)0x82622AA5, (q31_t)0xE769E8D8, + (q31_t)0x826BDC04, (q31_t)0xE7389664, (q31_t)0x8275A0C0, + (q31_t)0xE70747C3, (q31_t)0x827F78D8, (q31_t)0xE6D5FCFC, + (q31_t)0x8289644A, (q31_t)0xE6A4B616, (q31_t)0x82936316, + (q31_t)0xE6737319, (q31_t)0x829D753A, (q31_t)0xE642340D, + (q31_t)0x82A79AB3, (q31_t)0xE610F8F9, (q31_t)0x82B1D381, + (q31_t)0xE5DFC1E4, (q31_t)0x82BC1FA1, (q31_t)0xE5AE8ED8, + (q31_t)0x82C67F13, (q31_t)0xE57D5FDA, (q31_t)0x82D0F1D5, + (q31_t)0xE54C34F3, (q31_t)0x82DB77E5, (q31_t)0xE51B0E2A, + (q31_t)0x82E61141, (q31_t)0xE4E9EB86, (q31_t)0x82F0BDE8, + (q31_t)0xE4B8CD10, (q31_t)0x82FB7DD8, (q31_t)0xE487B2CF, + (q31_t)0x8306510F, (q31_t)0xE4569CCB, (q31_t)0x8311378C, + (q31_t)0xE4258B0A, (q31_t)0x831C314E, (q31_t)0xE3F47D95, + (q31_t)0x83273E52, (q31_t)0xE3C37473, (q31_t)0x83325E97, + (q31_t)0xE3926FAC, (q31_t)0x833D921A, (q31_t)0xE3616F47, + (q31_t)0x8348D8DB, (q31_t)0xE330734C, (q31_t)0x835432D8, + (q31_t)0xE2FF7BC3, (q31_t)0x835FA00E, (q31_t)0xE2CE88B2, + (q31_t)0x836B207D, (q31_t)0xE29D9A22, (q31_t)0x8376B422, + (q31_t)0xE26CB01A, (q31_t)0x83825AFB, (q31_t)0xE23BCAA2, + (q31_t)0x838E1507, (q31_t)0xE20AE9C1, (q31_t)0x8399E244, + (q31_t)0xE1DA0D7E, (q31_t)0x83A5C2B0, (q31_t)0xE1A935E1, + (q31_t)0x83B1B649, (q31_t)0xE17862F3, (q31_t)0x83BDBD0D, + (q31_t)0xE14794B9, (q31_t)0x83C9D6FB, (q31_t)0xE116CB3D, + (q31_t)0x83D60411, (q31_t)0xE0E60684, (q31_t)0x83E2444D, + (q31_t)0xE0B54698, (q31_t)0x83EE97AC, (q31_t)0xE0848B7F, + (q31_t)0x83FAFE2E, (q31_t)0xE053D541, (q31_t)0x840777CF, + (q31_t)0xE02323E5, (q31_t)0x8414048F, (q31_t)0xDFF27773, + (q31_t)0x8420A46B, (q31_t)0xDFC1CFF2, (q31_t)0x842D5761, + (q31_t)0xDF912D6A, (q31_t)0x843A1D70, (q31_t)0xDF608FE3, + (q31_t)0x8446F695, (q31_t)0xDF2FF764, (q31_t)0x8453E2CE, + (q31_t)0xDEFF63F4, (q31_t)0x8460E21A, (q31_t)0xDECED59B, + (q31_t)0x846DF476, (q31_t)0xDE9E4C60, (q31_t)0x847B19E1, + (q31_t)0xDE6DC84B, (q31_t)0x84885257, (q31_t)0xDE3D4963, + (q31_t)0x84959DD9, (q31_t)0xDE0CCFB1, (q31_t)0x84A2FC62, + (q31_t)0xDDDC5B3A, (q31_t)0x84B06DF1, (q31_t)0xDDABEC07, + (q31_t)0x84BDF285, (q31_t)0xDD7B8220, (q31_t)0x84CB8A1B, + (q31_t)0xDD4B1D8B, (q31_t)0x84D934B0, (q31_t)0xDD1ABE51, + (q31_t)0x84E6F244, (q31_t)0xDCEA6478, (q31_t)0x84F4C2D3, + (q31_t)0xDCBA1008, (q31_t)0x8502A65C, (q31_t)0xDC89C108, + (q31_t)0x85109CDC, (q31_t)0xDC597781, (q31_t)0x851EA652, + (q31_t)0xDC293379, (q31_t)0x852CC2BA, (q31_t)0xDBF8F4F8, + (q31_t)0x853AF214, (q31_t)0xDBC8BC05, (q31_t)0x8549345C, + (q31_t)0xDB9888A8, (q31_t)0x85578991, (q31_t)0xDB685AE8, + (q31_t)0x8565F1B0, (q31_t)0xDB3832CD, (q31_t)0x85746CB7, + (q31_t)0xDB08105E, (q31_t)0x8582FAA4, (q31_t)0xDAD7F3A2, + (q31_t)0x85919B75, (q31_t)0xDAA7DCA1, (q31_t)0x85A04F28, + (q31_t)0xDA77CB62, (q31_t)0x85AF15B9, (q31_t)0xDA47BFED, + (q31_t)0x85BDEF27, (q31_t)0xDA17BA4A, (q31_t)0x85CCDB70, + (q31_t)0xD9E7BA7E, (q31_t)0x85DBDA91, (q31_t)0xD9B7C093, + (q31_t)0x85EAEC88, (q31_t)0xD987CC8F, (q31_t)0x85FA1152, + (q31_t)0xD957DE7A, (q31_t)0x860948EE, (q31_t)0xD927F65B, + (q31_t)0x86189359, (q31_t)0xD8F81439, (q31_t)0x8627F090, + (q31_t)0xD8C8381C, (q31_t)0x86376092, (q31_t)0xD898620C, + (q31_t)0x8646E35B, (q31_t)0xD868920F, (q31_t)0x865678EA, + (q31_t)0xD838C82D, (q31_t)0x8666213C, (q31_t)0xD809046D, + (q31_t)0x8675DC4E, (q31_t)0xD7D946D7, (q31_t)0x8685AA1F, + (q31_t)0xD7A98F73, (q31_t)0x86958AAB, (q31_t)0xD779DE46, + (q31_t)0x86A57DF1, (q31_t)0xD74A335A, (q31_t)0x86B583EE, + (q31_t)0xD71A8EB5, (q31_t)0x86C59C9F, (q31_t)0xD6EAF05E, + (q31_t)0x86D5C802, (q31_t)0xD6BB585D, (q31_t)0x86E60614, + (q31_t)0xD68BC6BA, (q31_t)0x86F656D3, (q31_t)0xD65C3B7B, + (q31_t)0x8706BA3C, (q31_t)0xD62CB6A7, (q31_t)0x8717304E, + (q31_t)0xD5FD3847, (q31_t)0x8727B904, (q31_t)0xD5CDC062, + (q31_t)0x8738545E, (q31_t)0xD59E4EFE, (q31_t)0x87490257, + (q31_t)0xD56EE424, (q31_t)0x8759C2EF, (q31_t)0xD53F7FDA, + (q31_t)0x876A9621, (q31_t)0xD5102227, (q31_t)0x877B7BEC, + (q31_t)0xD4E0CB14, (q31_t)0x878C744C, (q31_t)0xD4B17AA7, + (q31_t)0x879D7F40, (q31_t)0xD48230E8, (q31_t)0x87AE9CC5, + (q31_t)0xD452EDDE, (q31_t)0x87BFCCD7, (q31_t)0xD423B190, + (q31_t)0x87D10F75, (q31_t)0xD3F47C06, (q31_t)0x87E2649B, + (q31_t)0xD3C54D46, (q31_t)0x87F3CC47, (q31_t)0xD3962559, + (q31_t)0x88054677, (q31_t)0xD3670445, (q31_t)0x8816D327, + (q31_t)0xD337EA12, (q31_t)0x88287255, (q31_t)0xD308D6C6, + (q31_t)0x883A23FE, (q31_t)0xD2D9CA6A, (q31_t)0x884BE820, + (q31_t)0xD2AAC504, (q31_t)0x885DBEB7, (q31_t)0xD27BC69C, + (q31_t)0x886FA7C2, (q31_t)0xD24CCF38, (q31_t)0x8881A33C, + (q31_t)0xD21DDEE1, (q31_t)0x8893B124, (q31_t)0xD1EEF59E, + (q31_t)0x88A5D177, (q31_t)0xD1C01374, (q31_t)0x88B80431, + (q31_t)0xD191386D, (q31_t)0x88CA4951, (q31_t)0xD162648F, + (q31_t)0x88DCA0D3, (q31_t)0xD13397E1, (q31_t)0x88EF0AB4, + (q31_t)0xD104D26B, (q31_t)0x890186F1, (q31_t)0xD0D61433, + (q31_t)0x89141589, (q31_t)0xD0A75D42, (q31_t)0x8926B677, + (q31_t)0xD078AD9D, (q31_t)0x893969B9, (q31_t)0xD04A054D, + (q31_t)0x894C2F4C, (q31_t)0xD01B6459, (q31_t)0x895F072D, + (q31_t)0xCFECCAC7, (q31_t)0x8971F15A, (q31_t)0xCFBE389F, + (q31_t)0x8984EDCF, (q31_t)0xCF8FADE8, (q31_t)0x8997FC89, + (q31_t)0xCF612AAA, (q31_t)0x89AB1D86, (q31_t)0xCF32AEEB, + (q31_t)0x89BE50C3, (q31_t)0xCF043AB2, (q31_t)0x89D1963C, + (q31_t)0xCED5CE08, (q31_t)0x89E4EDEE, (q31_t)0xCEA768F2, + (q31_t)0x89F857D8, (q31_t)0xCE790B78, (q31_t)0x8A0BD3F5, + (q31_t)0xCE4AB5A2, (q31_t)0x8A1F6242, (q31_t)0xCE1C6776, + (q31_t)0x8A3302BD, (q31_t)0xCDEE20FC, (q31_t)0x8A46B563, + (q31_t)0xCDBFE23A, (q31_t)0x8A5A7A30, (q31_t)0xCD91AB38, + (q31_t)0x8A6E5122, (q31_t)0xCD637BFD, (q31_t)0x8A823A35, + (q31_t)0xCD355490, (q31_t)0x8A963567, (q31_t)0xCD0734F8, + (q31_t)0x8AAA42B4, (q31_t)0xCCD91D3D, (q31_t)0x8ABE6219, + (q31_t)0xCCAB0D65, (q31_t)0x8AD29393, (q31_t)0xCC7D0577, + (q31_t)0x8AE6D71F, (q31_t)0xCC4F057B, (q31_t)0x8AFB2CBA, + (q31_t)0xCC210D78, (q31_t)0x8B0F9461, (q31_t)0xCBF31D75, + (q31_t)0x8B240E10, (q31_t)0xCBC53578, (q31_t)0x8B3899C5, + (q31_t)0xCB975589, (q31_t)0x8B4D377C, (q31_t)0xCB697DB0, + (q31_t)0x8B61E732, (q31_t)0xCB3BADF2, (q31_t)0x8B76A8E4, + (q31_t)0xCB0DE658, (q31_t)0x8B8B7C8F, (q31_t)0xCAE026E8, + (q31_t)0x8BA0622F, (q31_t)0xCAB26FA9, (q31_t)0x8BB559C1, + (q31_t)0xCA84C0A2, (q31_t)0x8BCA6342, (q31_t)0xCA5719DB, + (q31_t)0x8BDF7EAF, (q31_t)0xCA297B5A, (q31_t)0x8BF4AC05, + (q31_t)0xC9FBE527, (q31_t)0x8C09EB40, (q31_t)0xC9CE5748, + (q31_t)0x8C1F3C5C, (q31_t)0xC9A0D1C4, (q31_t)0x8C349F58, + (q31_t)0xC97354A3, (q31_t)0x8C4A142F, (q31_t)0xC945DFEC, + (q31_t)0x8C5F9ADD, (q31_t)0xC91873A5, (q31_t)0x8C753361, + (q31_t)0xC8EB0FD6, (q31_t)0x8C8ADDB6, (q31_t)0xC8BDB485, + (q31_t)0x8CA099D9, (q31_t)0xC89061BA, (q31_t)0x8CB667C7, + (q31_t)0xC863177B, (q31_t)0x8CCC477D, (q31_t)0xC835D5D0, + (q31_t)0x8CE238F6, (q31_t)0xC8089CBF, (q31_t)0x8CF83C30, + (q31_t)0xC7DB6C50, (q31_t)0x8D0E5127, (q31_t)0xC7AE4489, + (q31_t)0x8D2477D8, (q31_t)0xC7812571, (q31_t)0x8D3AB03F, + (q31_t)0xC7540F10, (q31_t)0x8D50FA59, (q31_t)0xC727016C, + (q31_t)0x8D675623, (q31_t)0xC6F9FC8D, (q31_t)0x8D7DC399, + (q31_t)0xC6CD0079, (q31_t)0x8D9442B7, (q31_t)0xC6A00D36, + (q31_t)0x8DAAD37B, (q31_t)0xC67322CD, (q31_t)0x8DC175E0, + (q31_t)0xC6464144, (q31_t)0x8DD829E4, (q31_t)0xC61968A2, + (q31_t)0x8DEEEF82, (q31_t)0xC5EC98ED, (q31_t)0x8E05C6B7, + (q31_t)0xC5BFD22E, (q31_t)0x8E1CAF80, (q31_t)0xC593146A, + (q31_t)0x8E33A9D9, (q31_t)0xC5665FA8, (q31_t)0x8E4AB5BF, + (q31_t)0xC539B3F0, (q31_t)0x8E61D32D, (q31_t)0xC50D1148, + (q31_t)0x8E790222, (q31_t)0xC4E077B8, (q31_t)0x8E904298, + (q31_t)0xC4B3E746, (q31_t)0x8EA7948C, (q31_t)0xC4875FF8, + (q31_t)0x8EBEF7FB, (q31_t)0xC45AE1D7, (q31_t)0x8ED66CE1, + (q31_t)0xC42E6CE8, (q31_t)0x8EEDF33B, (q31_t)0xC4020132, + (q31_t)0x8F058B04, (q31_t)0xC3D59EBD, (q31_t)0x8F1D343A, + (q31_t)0xC3A9458F, (q31_t)0x8F34EED8, (q31_t)0xC37CF5B0, + (q31_t)0x8F4CBADB, (q31_t)0xC350AF25, (q31_t)0x8F64983F, + (q31_t)0xC32471F6, (q31_t)0x8F7C8701, (q31_t)0xC2F83E2A, + (q31_t)0x8F94871D, (q31_t)0xC2CC13C7, (q31_t)0x8FAC988E, + (q31_t)0xC29FF2D4, (q31_t)0x8FC4BB53, (q31_t)0xC273DB58, + (q31_t)0x8FDCEF66, (q31_t)0xC247CD5A, (q31_t)0x8FF534C4, + (q31_t)0xC21BC8E0, (q31_t)0x900D8B69, (q31_t)0xC1EFCDF2, + (q31_t)0x9025F352, (q31_t)0xC1C3DC96, (q31_t)0x903E6C7A, + (q31_t)0xC197F4D3, (q31_t)0x9056F6DF, (q31_t)0xC16C16B0, + (q31_t)0x906F927B, (q31_t)0xC1404233, (q31_t)0x90883F4C, + (q31_t)0xC1147763, (q31_t)0x90A0FD4E, (q31_t)0xC0E8B648, + (q31_t)0x90B9CC7C, (q31_t)0xC0BCFEE7, (q31_t)0x90D2ACD3, + (q31_t)0xC0915147, (q31_t)0x90EB9E50, (q31_t)0xC065AD70, + (q31_t)0x9104A0ED, (q31_t)0xC03A1368, (q31_t)0x911DB4A8, + (q31_t)0xC00E8335, (q31_t)0x9136D97D, (q31_t)0xBFE2FCDF, + (q31_t)0x91500F67, (q31_t)0xBFB7806C, (q31_t)0x91695663, + (q31_t)0xBF8C0DE2, (q31_t)0x9182AE6C, (q31_t)0xBF60A54A, + (q31_t)0x919C1780, (q31_t)0xBF3546A8, (q31_t)0x91B5919A, + (q31_t)0xBF09F204, (q31_t)0x91CF1CB6, (q31_t)0xBEDEA765, + (q31_t)0x91E8B8D0, (q31_t)0xBEB366D1, (q31_t)0x920265E4, + (q31_t)0xBE88304F, (q31_t)0x921C23EE, (q31_t)0xBE5D03E5, + (q31_t)0x9235F2EB, (q31_t)0xBE31E19B, (q31_t)0x924FD2D6, + (q31_t)0xBE06C977, (q31_t)0x9269C3AC, (q31_t)0xBDDBBB7F, + (q31_t)0x9283C567, (q31_t)0xBDB0B7BA, (q31_t)0x929DD805, + (q31_t)0xBD85BE2F, (q31_t)0x92B7FB82, (q31_t)0xBD5ACEE5, + (q31_t)0x92D22FD8, (q31_t)0xBD2FE9E1, (q31_t)0x92EC7505, + (q31_t)0xBD050F2C, (q31_t)0x9306CB04, (q31_t)0xBCDA3ECA, + (q31_t)0x932131D1, (q31_t)0xBCAF78C3, (q31_t)0x933BA968, + (q31_t)0xBC84BD1E, (q31_t)0x935631C5, (q31_t)0xBC5A0BE1, + (q31_t)0x9370CAE4, (q31_t)0xBC2F6513, (q31_t)0x938B74C0, + (q31_t)0xBC04C8BA, (q31_t)0x93A62F56, (q31_t)0xBBDA36DC, + (q31_t)0x93C0FAA2, (q31_t)0xBBAFAF81, (q31_t)0x93DBD69F, + (q31_t)0xBB8532AF, (q31_t)0x93F6C34A, (q31_t)0xBB5AC06C, + (q31_t)0x9411C09D, (q31_t)0xBB3058C0, (q31_t)0x942CCE95, + (q31_t)0xBB05FBB0, (q31_t)0x9447ED2F, (q31_t)0xBADBA943, + (q31_t)0x94631C64, (q31_t)0xBAB1617F, (q31_t)0x947E5C32, + (q31_t)0xBA87246C, (q31_t)0x9499AC95, (q31_t)0xBA5CF210, + (q31_t)0x94B50D87, (q31_t)0xBA32CA70, (q31_t)0x94D07F05, + (q31_t)0xBA08AD94, (q31_t)0x94EC010B, (q31_t)0xB9DE9B83, + (q31_t)0x95079393, (q31_t)0xB9B49442, (q31_t)0x9523369B, + (q31_t)0xB98A97D8, (q31_t)0x953EEA1E, (q31_t)0xB960A64B, + (q31_t)0x955AAE17, (q31_t)0xB936BFA3, (q31_t)0x95768282, + (q31_t)0xB90CE3E6, (q31_t)0x9592675B, (q31_t)0xB8E31319, + (q31_t)0x95AE5C9E, (q31_t)0xB8B94D44, (q31_t)0x95CA6246, + (q31_t)0xB88F926C, (q31_t)0x95E6784F, (q31_t)0xB865E299, + (q31_t)0x96029EB5, (q31_t)0xB83C3DD1, (q31_t)0x961ED573, + (q31_t)0xB812A419, (q31_t)0x963B1C85, (q31_t)0xB7E9157A, + (q31_t)0x965773E7, (q31_t)0xB7BF91F8, (q31_t)0x9673DB94, + (q31_t)0xB796199B, (q31_t)0x96905387, (q31_t)0xB76CAC68, + (q31_t)0x96ACDBBD, (q31_t)0xB7434A67, (q31_t)0x96C97431, + (q31_t)0xB719F39D, (q31_t)0x96E61CDF, (q31_t)0xB6F0A811, + (q31_t)0x9702D5C2, (q31_t)0xB6C767CA, (q31_t)0x971F9ED6, + (q31_t)0xB69E32CD, (q31_t)0x973C7816, (q31_t)0xB6750921, + (q31_t)0x9759617E, (q31_t)0xB64BEACC, (q31_t)0x97765B0A, + (q31_t)0xB622D7D5, (q31_t)0x979364B5, (q31_t)0xB5F9D042, + (q31_t)0x97B07E7A, (q31_t)0xB5D0D41A, (q31_t)0x97CDA855, + (q31_t)0xB5A7E362, (q31_t)0x97EAE241, (q31_t)0xB57EFE21, + (q31_t)0x98082C3B, (q31_t)0xB556245E, (q31_t)0x9825863D, + (q31_t)0xB52D561E, (q31_t)0x9842F043, (q31_t)0xB5049368, + (q31_t)0x98606A48, (q31_t)0xB4DBDC42, (q31_t)0x987DF449, + (q31_t)0xB4B330B2, (q31_t)0x989B8E3F, (q31_t)0xB48A90C0, + (q31_t)0x98B93828, (q31_t)0xB461FC70, (q31_t)0x98D6F1FE, + (q31_t)0xB43973C9, (q31_t)0x98F4BBBC, (q31_t)0xB410F6D2, + (q31_t)0x9912955E, (q31_t)0xB3E88591, (q31_t)0x99307EE0, + (q31_t)0xB3C0200C, (q31_t)0x994E783C, (q31_t)0xB397C649, + (q31_t)0x996C816F, (q31_t)0xB36F784E, (q31_t)0x998A9A73, + (q31_t)0xB3473622, (q31_t)0x99A8C344, (q31_t)0xB31EFFCB, + (q31_t)0x99C6FBDE, (q31_t)0xB2F6D54F, (q31_t)0x99E5443A, + (q31_t)0xB2CEB6B5, (q31_t)0x9A039C56, (q31_t)0xB2A6A401, + (q31_t)0x9A22042C, (q31_t)0xB27E9D3B, (q31_t)0x9A407BB8, + (q31_t)0xB256A26A, (q31_t)0x9A5F02F5, (q31_t)0xB22EB392, + (q31_t)0x9A7D99DD, (q31_t)0xB206D0BA, (q31_t)0x9A9C406D, + (q31_t)0xB1DEF9E8, (q31_t)0x9ABAF6A0, (q31_t)0xB1B72F23, + (q31_t)0x9AD9BC71, (q31_t)0xB18F7070, (q31_t)0x9AF891DB, + (q31_t)0xB167BDD6, (q31_t)0x9B1776D9, (q31_t)0xB140175B, + (q31_t)0x9B366B67, (q31_t)0xB1187D05, (q31_t)0x9B556F80, + (q31_t)0xB0F0EEDA, (q31_t)0x9B748320, (q31_t)0xB0C96CDF, + (q31_t)0x9B93A640, (q31_t)0xB0A1F71C, (q31_t)0x9BB2D8DD, + (q31_t)0xB07A8D97, (q31_t)0x9BD21AF2, (q31_t)0xB0533055, + (q31_t)0x9BF16C7A, (q31_t)0xB02BDF5C, (q31_t)0x9C10CD70, + (q31_t)0xB0049AB2, (q31_t)0x9C303DCF, (q31_t)0xAFDD625F, + (q31_t)0x9C4FBD92, (q31_t)0xAFB63667, (q31_t)0x9C6F4CB5, + (q31_t)0xAF8F16D0, (q31_t)0x9C8EEB33, (q31_t)0xAF6803A1, + (q31_t)0x9CAE9907, (q31_t)0xAF40FCE0, (q31_t)0x9CCE562B, + (q31_t)0xAF1A0293, (q31_t)0x9CEE229C, (q31_t)0xAEF314BF, + (q31_t)0x9D0DFE53, (q31_t)0xAECC336B, (q31_t)0x9D2DE94D, + (q31_t)0xAEA55E9D, (q31_t)0x9D4DE384, (q31_t)0xAE7E965B, + (q31_t)0x9D6DECF4, (q31_t)0xAE57DAAA, (q31_t)0x9D8E0596, + (q31_t)0xAE312B91, (q31_t)0x9DAE2D68, (q31_t)0xAE0A8916, + (q31_t)0x9DCE6462, (q31_t)0xADE3F33E, (q31_t)0x9DEEAA82, + (q31_t)0xADBD6A10, (q31_t)0x9E0EFFC1, (q31_t)0xAD96ED91, + (q31_t)0x9E2F641A, (q31_t)0xAD707DC8, (q31_t)0x9E4FD789, + (q31_t)0xAD4A1ABA, (q31_t)0x9E705A09, (q31_t)0xAD23C46D, + (q31_t)0x9E90EB94, (q31_t)0xACFD7AE8, (q31_t)0x9EB18C26, + (q31_t)0xACD73E30, (q31_t)0x9ED23BB9, (q31_t)0xACB10E4A, + (q31_t)0x9EF2FA48, (q31_t)0xAC8AEB3E, (q31_t)0x9F13C7D0, + (q31_t)0xAC64D510, (q31_t)0x9F34A449, (q31_t)0xAC3ECBC7, + (q31_t)0x9F558FB0, (q31_t)0xAC18CF68, (q31_t)0x9F7689FF, + (q31_t)0xABF2DFFA, (q31_t)0x9F979331, (q31_t)0xABCCFD82, + (q31_t)0x9FB8AB41, (q31_t)0xABA72806, (q31_t)0x9FD9D22A, + (q31_t)0xAB815F8C, (q31_t)0x9FFB07E7, (q31_t)0xAB5BA41A, + (q31_t)0xA01C4C72, (q31_t)0xAB35F5B5, (q31_t)0xA03D9FC7, + (q31_t)0xAB105464, (q31_t)0xA05F01E1, (q31_t)0xAAEAC02B, + (q31_t)0xA08072BA, (q31_t)0xAAC53912, (q31_t)0xA0A1F24C, + (q31_t)0xAA9FBF1D, (q31_t)0xA0C38094, (q31_t)0xAA7A5253, + (q31_t)0xA0E51D8C, (q31_t)0xAA54F2B9, (q31_t)0xA106C92E, + (q31_t)0xAA2FA055, (q31_t)0xA1288376, (q31_t)0xAA0A5B2D, + (q31_t)0xA14A4C5E, (q31_t)0xA9E52347, (q31_t)0xA16C23E1, + (q31_t)0xA9BFF8A8, (q31_t)0xA18E09F9, (q31_t)0xA99ADB56, + (q31_t)0xA1AFFEA2, (q31_t)0xA975CB56, (q31_t)0xA1D201D7, + (q31_t)0xA950C8AF, (q31_t)0xA1F41391, (q31_t)0xA92BD366, + (q31_t)0xA21633CD, (q31_t)0xA906EB81, (q31_t)0xA2386283, + (q31_t)0xA8E21106, (q31_t)0xA25A9FB1, (q31_t)0xA8BD43FA, + (q31_t)0xA27CEB4F, (q31_t)0xA8988463, (q31_t)0xA29F4559, + (q31_t)0xA873D246, (q31_t)0xA2C1ADC9, (q31_t)0xA84F2DA9, + (q31_t)0xA2E4249A, (q31_t)0xA82A9693, (q31_t)0xA306A9C7, + (q31_t)0xA8060D08, (q31_t)0xA3293D4B, (q31_t)0xA7E1910E, + (q31_t)0xA34BDF20, (q31_t)0xA7BD22AB, (q31_t)0xA36E8F40, + (q31_t)0xA798C1E4, (q31_t)0xA3914DA7, (q31_t)0xA7746EC0, + (q31_t)0xA3B41A4F, (q31_t)0xA7502943, (q31_t)0xA3D6F533, + (q31_t)0xA72BF173, (q31_t)0xA3F9DE4D, (q31_t)0xA707C756, + (q31_t)0xA41CD598, (q31_t)0xA6E3AAF2, (q31_t)0xA43FDB0F, + (q31_t)0xA6BF9C4B, (q31_t)0xA462EEAC, (q31_t)0xA69B9B68, + (q31_t)0xA4861069, (q31_t)0xA677A84E, (q31_t)0xA4A94042, + (q31_t)0xA653C302, (q31_t)0xA4CC7E31, (q31_t)0xA62FEB8B, + (q31_t)0xA4EFCA31, (q31_t)0xA60C21ED, (q31_t)0xA513243B, + (q31_t)0xA5E8662F, (q31_t)0xA5368C4B, (q31_t)0xA5C4B855, + (q31_t)0xA55A025B, (q31_t)0xA5A11865, (q31_t)0xA57D8666, + (q31_t)0xA57D8666, (q31_t)0xA5A11865, (q31_t)0xA55A025B, + (q31_t)0xA5C4B855, (q31_t)0xA5368C4B, (q31_t)0xA5E8662F, + (q31_t)0xA513243B, (q31_t)0xA60C21ED, (q31_t)0xA4EFCA31, + (q31_t)0xA62FEB8B, (q31_t)0xA4CC7E31, (q31_t)0xA653C302, + (q31_t)0xA4A94042, (q31_t)0xA677A84E, (q31_t)0xA4861069, + (q31_t)0xA69B9B68, (q31_t)0xA462EEAC, (q31_t)0xA6BF9C4B, + (q31_t)0xA43FDB0F, (q31_t)0xA6E3AAF2, (q31_t)0xA41CD598, + (q31_t)0xA707C756, (q31_t)0xA3F9DE4D, (q31_t)0xA72BF173, + (q31_t)0xA3D6F533, (q31_t)0xA7502943, (q31_t)0xA3B41A4F, + (q31_t)0xA7746EC0, (q31_t)0xA3914DA7, (q31_t)0xA798C1E4, + (q31_t)0xA36E8F40, (q31_t)0xA7BD22AB, (q31_t)0xA34BDF20, + (q31_t)0xA7E1910E, (q31_t)0xA3293D4B, (q31_t)0xA8060D08, + (q31_t)0xA306A9C7, (q31_t)0xA82A9693, (q31_t)0xA2E4249A, + (q31_t)0xA84F2DA9, (q31_t)0xA2C1ADC9, (q31_t)0xA873D246, + (q31_t)0xA29F4559, (q31_t)0xA8988463, (q31_t)0xA27CEB4F, + (q31_t)0xA8BD43FA, (q31_t)0xA25A9FB1, (q31_t)0xA8E21106, + (q31_t)0xA2386283, (q31_t)0xA906EB81, (q31_t)0xA21633CD, + (q31_t)0xA92BD366, (q31_t)0xA1F41391, (q31_t)0xA950C8AF, + (q31_t)0xA1D201D7, (q31_t)0xA975CB56, (q31_t)0xA1AFFEA2, + (q31_t)0xA99ADB56, (q31_t)0xA18E09F9, (q31_t)0xA9BFF8A8, + (q31_t)0xA16C23E1, (q31_t)0xA9E52347, (q31_t)0xA14A4C5E, + (q31_t)0xAA0A5B2D, (q31_t)0xA1288376, (q31_t)0xAA2FA055, + (q31_t)0xA106C92E, (q31_t)0xAA54F2B9, (q31_t)0xA0E51D8C, + (q31_t)0xAA7A5253, (q31_t)0xA0C38094, (q31_t)0xAA9FBF1D, + (q31_t)0xA0A1F24C, (q31_t)0xAAC53912, (q31_t)0xA08072BA, + (q31_t)0xAAEAC02B, (q31_t)0xA05F01E1, (q31_t)0xAB105464, + (q31_t)0xA03D9FC7, (q31_t)0xAB35F5B5, (q31_t)0xA01C4C72, + (q31_t)0xAB5BA41A, (q31_t)0x9FFB07E7, (q31_t)0xAB815F8C, + (q31_t)0x9FD9D22A, (q31_t)0xABA72806, (q31_t)0x9FB8AB41, + (q31_t)0xABCCFD82, (q31_t)0x9F979331, (q31_t)0xABF2DFFA, + (q31_t)0x9F7689FF, (q31_t)0xAC18CF68, (q31_t)0x9F558FB0, + (q31_t)0xAC3ECBC7, (q31_t)0x9F34A449, (q31_t)0xAC64D510, + (q31_t)0x9F13C7D0, (q31_t)0xAC8AEB3E, (q31_t)0x9EF2FA48, + (q31_t)0xACB10E4A, (q31_t)0x9ED23BB9, (q31_t)0xACD73E30, + (q31_t)0x9EB18C26, (q31_t)0xACFD7AE8, (q31_t)0x9E90EB94, + (q31_t)0xAD23C46D, (q31_t)0x9E705A09, (q31_t)0xAD4A1ABA, + (q31_t)0x9E4FD789, (q31_t)0xAD707DC8, (q31_t)0x9E2F641A, + (q31_t)0xAD96ED91, (q31_t)0x9E0EFFC1, (q31_t)0xADBD6A10, + (q31_t)0x9DEEAA82, (q31_t)0xADE3F33E, (q31_t)0x9DCE6462, + (q31_t)0xAE0A8916, (q31_t)0x9DAE2D68, (q31_t)0xAE312B91, + (q31_t)0x9D8E0596, (q31_t)0xAE57DAAA, (q31_t)0x9D6DECF4, + (q31_t)0xAE7E965B, (q31_t)0x9D4DE384, (q31_t)0xAEA55E9D, + (q31_t)0x9D2DE94D, (q31_t)0xAECC336B, (q31_t)0x9D0DFE53, + (q31_t)0xAEF314BF, (q31_t)0x9CEE229C, (q31_t)0xAF1A0293, + (q31_t)0x9CCE562B, (q31_t)0xAF40FCE0, (q31_t)0x9CAE9907, + (q31_t)0xAF6803A1, (q31_t)0x9C8EEB33, (q31_t)0xAF8F16D0, + (q31_t)0x9C6F4CB5, (q31_t)0xAFB63667, (q31_t)0x9C4FBD92, + (q31_t)0xAFDD625F, (q31_t)0x9C303DCF, (q31_t)0xB0049AB2, + (q31_t)0x9C10CD70, (q31_t)0xB02BDF5C, (q31_t)0x9BF16C7A, + (q31_t)0xB0533055, (q31_t)0x9BD21AF2, (q31_t)0xB07A8D97, + (q31_t)0x9BB2D8DD, (q31_t)0xB0A1F71C, (q31_t)0x9B93A640, + (q31_t)0xB0C96CDF, (q31_t)0x9B748320, (q31_t)0xB0F0EEDA, + (q31_t)0x9B556F80, (q31_t)0xB1187D05, (q31_t)0x9B366B67, + (q31_t)0xB140175B, (q31_t)0x9B1776D9, (q31_t)0xB167BDD6, + (q31_t)0x9AF891DB, (q31_t)0xB18F7070, (q31_t)0x9AD9BC71, + (q31_t)0xB1B72F23, (q31_t)0x9ABAF6A0, (q31_t)0xB1DEF9E8, + (q31_t)0x9A9C406D, (q31_t)0xB206D0BA, (q31_t)0x9A7D99DD, + (q31_t)0xB22EB392, (q31_t)0x9A5F02F5, (q31_t)0xB256A26A, + (q31_t)0x9A407BB8, (q31_t)0xB27E9D3B, (q31_t)0x9A22042C, + (q31_t)0xB2A6A401, (q31_t)0x9A039C56, (q31_t)0xB2CEB6B5, + (q31_t)0x99E5443A, (q31_t)0xB2F6D54F, (q31_t)0x99C6FBDE, + (q31_t)0xB31EFFCB, (q31_t)0x99A8C344, (q31_t)0xB3473622, + (q31_t)0x998A9A73, (q31_t)0xB36F784E, (q31_t)0x996C816F, + (q31_t)0xB397C649, (q31_t)0x994E783C, (q31_t)0xB3C0200C, + (q31_t)0x99307EE0, (q31_t)0xB3E88591, (q31_t)0x9912955E, + (q31_t)0xB410F6D2, (q31_t)0x98F4BBBC, (q31_t)0xB43973C9, + (q31_t)0x98D6F1FE, (q31_t)0xB461FC70, (q31_t)0x98B93828, + (q31_t)0xB48A90C0, (q31_t)0x989B8E3F, (q31_t)0xB4B330B2, + (q31_t)0x987DF449, (q31_t)0xB4DBDC42, (q31_t)0x98606A48, + (q31_t)0xB5049368, (q31_t)0x9842F043, (q31_t)0xB52D561E, + (q31_t)0x9825863D, (q31_t)0xB556245E, (q31_t)0x98082C3B, + (q31_t)0xB57EFE21, (q31_t)0x97EAE241, (q31_t)0xB5A7E362, + (q31_t)0x97CDA855, (q31_t)0xB5D0D41A, (q31_t)0x97B07E7A, + (q31_t)0xB5F9D042, (q31_t)0x979364B5, (q31_t)0xB622D7D5, + (q31_t)0x97765B0A, (q31_t)0xB64BEACC, (q31_t)0x9759617E, + (q31_t)0xB6750921, (q31_t)0x973C7816, (q31_t)0xB69E32CD, + (q31_t)0x971F9ED6, (q31_t)0xB6C767CA, (q31_t)0x9702D5C2, + (q31_t)0xB6F0A811, (q31_t)0x96E61CDF, (q31_t)0xB719F39D, + (q31_t)0x96C97431, (q31_t)0xB7434A67, (q31_t)0x96ACDBBD, + (q31_t)0xB76CAC68, (q31_t)0x96905387, (q31_t)0xB796199B, + (q31_t)0x9673DB94, (q31_t)0xB7BF91F8, (q31_t)0x965773E7, + (q31_t)0xB7E9157A, (q31_t)0x963B1C85, (q31_t)0xB812A419, + (q31_t)0x961ED573, (q31_t)0xB83C3DD1, (q31_t)0x96029EB5, + (q31_t)0xB865E299, (q31_t)0x95E6784F, (q31_t)0xB88F926C, + (q31_t)0x95CA6246, (q31_t)0xB8B94D44, (q31_t)0x95AE5C9E, + (q31_t)0xB8E31319, (q31_t)0x9592675B, (q31_t)0xB90CE3E6, + (q31_t)0x95768282, (q31_t)0xB936BFA3, (q31_t)0x955AAE17, + (q31_t)0xB960A64B, (q31_t)0x953EEA1E, (q31_t)0xB98A97D8, + (q31_t)0x9523369B, (q31_t)0xB9B49442, (q31_t)0x95079393, + (q31_t)0xB9DE9B83, (q31_t)0x94EC010B, (q31_t)0xBA08AD94, + (q31_t)0x94D07F05, (q31_t)0xBA32CA70, (q31_t)0x94B50D87, + (q31_t)0xBA5CF210, (q31_t)0x9499AC95, (q31_t)0xBA87246C, + (q31_t)0x947E5C32, (q31_t)0xBAB1617F, (q31_t)0x94631C64, + (q31_t)0xBADBA943, (q31_t)0x9447ED2F, (q31_t)0xBB05FBB0, + (q31_t)0x942CCE95, (q31_t)0xBB3058C0, (q31_t)0x9411C09D, + (q31_t)0xBB5AC06C, (q31_t)0x93F6C34A, (q31_t)0xBB8532AF, + (q31_t)0x93DBD69F, (q31_t)0xBBAFAF81, (q31_t)0x93C0FAA2, + (q31_t)0xBBDA36DC, (q31_t)0x93A62F56, (q31_t)0xBC04C8BA, + (q31_t)0x938B74C0, (q31_t)0xBC2F6513, (q31_t)0x9370CAE4, + (q31_t)0xBC5A0BE1, (q31_t)0x935631C5, (q31_t)0xBC84BD1E, + (q31_t)0x933BA968, (q31_t)0xBCAF78C3, (q31_t)0x932131D1, + (q31_t)0xBCDA3ECA, (q31_t)0x9306CB04, (q31_t)0xBD050F2C, + (q31_t)0x92EC7505, (q31_t)0xBD2FE9E1, (q31_t)0x92D22FD8, + (q31_t)0xBD5ACEE5, (q31_t)0x92B7FB82, (q31_t)0xBD85BE2F, + (q31_t)0x929DD805, (q31_t)0xBDB0B7BA, (q31_t)0x9283C567, + (q31_t)0xBDDBBB7F, (q31_t)0x9269C3AC, (q31_t)0xBE06C977, + (q31_t)0x924FD2D6, (q31_t)0xBE31E19B, (q31_t)0x9235F2EB, + (q31_t)0xBE5D03E5, (q31_t)0x921C23EE, (q31_t)0xBE88304F, + (q31_t)0x920265E4, (q31_t)0xBEB366D1, (q31_t)0x91E8B8D0, + (q31_t)0xBEDEA765, (q31_t)0x91CF1CB6, (q31_t)0xBF09F204, + (q31_t)0x91B5919A, (q31_t)0xBF3546A8, (q31_t)0x919C1780, + (q31_t)0xBF60A54A, (q31_t)0x9182AE6C, (q31_t)0xBF8C0DE2, + (q31_t)0x91695663, (q31_t)0xBFB7806C, (q31_t)0x91500F67, + (q31_t)0xBFE2FCDF, (q31_t)0x9136D97D, (q31_t)0xC00E8335, + (q31_t)0x911DB4A8, (q31_t)0xC03A1368, (q31_t)0x9104A0ED, + (q31_t)0xC065AD70, (q31_t)0x90EB9E50, (q31_t)0xC0915147, + (q31_t)0x90D2ACD3, (q31_t)0xC0BCFEE7, (q31_t)0x90B9CC7C, + (q31_t)0xC0E8B648, (q31_t)0x90A0FD4E, (q31_t)0xC1147763, + (q31_t)0x90883F4C, (q31_t)0xC1404233, (q31_t)0x906F927B, + (q31_t)0xC16C16B0, (q31_t)0x9056F6DF, (q31_t)0xC197F4D3, + (q31_t)0x903E6C7A, (q31_t)0xC1C3DC96, (q31_t)0x9025F352, + (q31_t)0xC1EFCDF2, (q31_t)0x900D8B69, (q31_t)0xC21BC8E0, + (q31_t)0x8FF534C4, (q31_t)0xC247CD5A, (q31_t)0x8FDCEF66, + (q31_t)0xC273DB58, (q31_t)0x8FC4BB53, (q31_t)0xC29FF2D4, + (q31_t)0x8FAC988E, (q31_t)0xC2CC13C7, (q31_t)0x8F94871D, + (q31_t)0xC2F83E2A, (q31_t)0x8F7C8701, (q31_t)0xC32471F6, + (q31_t)0x8F64983F, (q31_t)0xC350AF25, (q31_t)0x8F4CBADB, + (q31_t)0xC37CF5B0, (q31_t)0x8F34EED8, (q31_t)0xC3A9458F, + (q31_t)0x8F1D343A, (q31_t)0xC3D59EBD, (q31_t)0x8F058B04, + (q31_t)0xC4020132, (q31_t)0x8EEDF33B, (q31_t)0xC42E6CE8, + (q31_t)0x8ED66CE1, (q31_t)0xC45AE1D7, (q31_t)0x8EBEF7FB, + (q31_t)0xC4875FF8, (q31_t)0x8EA7948C, (q31_t)0xC4B3E746, + (q31_t)0x8E904298, (q31_t)0xC4E077B8, (q31_t)0x8E790222, + (q31_t)0xC50D1148, (q31_t)0x8E61D32D, (q31_t)0xC539B3F0, + (q31_t)0x8E4AB5BF, (q31_t)0xC5665FA8, (q31_t)0x8E33A9D9, + (q31_t)0xC593146A, (q31_t)0x8E1CAF80, (q31_t)0xC5BFD22E, + (q31_t)0x8E05C6B7, (q31_t)0xC5EC98ED, (q31_t)0x8DEEEF82, + (q31_t)0xC61968A2, (q31_t)0x8DD829E4, (q31_t)0xC6464144, + (q31_t)0x8DC175E0, (q31_t)0xC67322CD, (q31_t)0x8DAAD37B, + (q31_t)0xC6A00D36, (q31_t)0x8D9442B7, (q31_t)0xC6CD0079, + (q31_t)0x8D7DC399, (q31_t)0xC6F9FC8D, (q31_t)0x8D675623, + (q31_t)0xC727016C, (q31_t)0x8D50FA59, (q31_t)0xC7540F10, + (q31_t)0x8D3AB03F, (q31_t)0xC7812571, (q31_t)0x8D2477D8, + (q31_t)0xC7AE4489, (q31_t)0x8D0E5127, (q31_t)0xC7DB6C50, + (q31_t)0x8CF83C30, (q31_t)0xC8089CBF, (q31_t)0x8CE238F6, + (q31_t)0xC835D5D0, (q31_t)0x8CCC477D, (q31_t)0xC863177B, + (q31_t)0x8CB667C7, (q31_t)0xC89061BA, (q31_t)0x8CA099D9, + (q31_t)0xC8BDB485, (q31_t)0x8C8ADDB6, (q31_t)0xC8EB0FD6, + (q31_t)0x8C753361, (q31_t)0xC91873A5, (q31_t)0x8C5F9ADD, + (q31_t)0xC945DFEC, (q31_t)0x8C4A142F, (q31_t)0xC97354A3, + (q31_t)0x8C349F58, (q31_t)0xC9A0D1C4, (q31_t)0x8C1F3C5C, + (q31_t)0xC9CE5748, (q31_t)0x8C09EB40, (q31_t)0xC9FBE527, + (q31_t)0x8BF4AC05, (q31_t)0xCA297B5A, (q31_t)0x8BDF7EAF, + (q31_t)0xCA5719DB, (q31_t)0x8BCA6342, (q31_t)0xCA84C0A2, + (q31_t)0x8BB559C1, (q31_t)0xCAB26FA9, (q31_t)0x8BA0622F, + (q31_t)0xCAE026E8, (q31_t)0x8B8B7C8F, (q31_t)0xCB0DE658, + (q31_t)0x8B76A8E4, (q31_t)0xCB3BADF2, (q31_t)0x8B61E732, + (q31_t)0xCB697DB0, (q31_t)0x8B4D377C, (q31_t)0xCB975589, + (q31_t)0x8B3899C5, (q31_t)0xCBC53578, (q31_t)0x8B240E10, + (q31_t)0xCBF31D75, (q31_t)0x8B0F9461, (q31_t)0xCC210D78, + (q31_t)0x8AFB2CBA, (q31_t)0xCC4F057B, (q31_t)0x8AE6D71F, + (q31_t)0xCC7D0577, (q31_t)0x8AD29393, (q31_t)0xCCAB0D65, + (q31_t)0x8ABE6219, (q31_t)0xCCD91D3D, (q31_t)0x8AAA42B4, + (q31_t)0xCD0734F8, (q31_t)0x8A963567, (q31_t)0xCD355490, + (q31_t)0x8A823A35, (q31_t)0xCD637BFD, (q31_t)0x8A6E5122, + (q31_t)0xCD91AB38, (q31_t)0x8A5A7A30, (q31_t)0xCDBFE23A, + (q31_t)0x8A46B563, (q31_t)0xCDEE20FC, (q31_t)0x8A3302BD, + (q31_t)0xCE1C6776, (q31_t)0x8A1F6242, (q31_t)0xCE4AB5A2, + (q31_t)0x8A0BD3F5, (q31_t)0xCE790B78, (q31_t)0x89F857D8, + (q31_t)0xCEA768F2, (q31_t)0x89E4EDEE, (q31_t)0xCED5CE08, + (q31_t)0x89D1963C, (q31_t)0xCF043AB2, (q31_t)0x89BE50C3, + (q31_t)0xCF32AEEB, (q31_t)0x89AB1D86, (q31_t)0xCF612AAA, + (q31_t)0x8997FC89, (q31_t)0xCF8FADE8, (q31_t)0x8984EDCF, + (q31_t)0xCFBE389F, (q31_t)0x8971F15A, (q31_t)0xCFECCAC7, + (q31_t)0x895F072D, (q31_t)0xD01B6459, (q31_t)0x894C2F4C, + (q31_t)0xD04A054D, (q31_t)0x893969B9, (q31_t)0xD078AD9D, + (q31_t)0x8926B677, (q31_t)0xD0A75D42, (q31_t)0x89141589, + (q31_t)0xD0D61433, (q31_t)0x890186F1, (q31_t)0xD104D26B, + (q31_t)0x88EF0AB4, (q31_t)0xD13397E1, (q31_t)0x88DCA0D3, + (q31_t)0xD162648F, (q31_t)0x88CA4951, (q31_t)0xD191386D, + (q31_t)0x88B80431, (q31_t)0xD1C01374, (q31_t)0x88A5D177, + (q31_t)0xD1EEF59E, (q31_t)0x8893B124, (q31_t)0xD21DDEE1, + (q31_t)0x8881A33C, (q31_t)0xD24CCF38, (q31_t)0x886FA7C2, + (q31_t)0xD27BC69C, (q31_t)0x885DBEB7, (q31_t)0xD2AAC504, + (q31_t)0x884BE820, (q31_t)0xD2D9CA6A, (q31_t)0x883A23FE, + (q31_t)0xD308D6C6, (q31_t)0x88287255, (q31_t)0xD337EA12, + (q31_t)0x8816D327, (q31_t)0xD3670445, (q31_t)0x88054677, + (q31_t)0xD3962559, (q31_t)0x87F3CC47, (q31_t)0xD3C54D46, + (q31_t)0x87E2649B, (q31_t)0xD3F47C06, (q31_t)0x87D10F75, + (q31_t)0xD423B190, (q31_t)0x87BFCCD7, (q31_t)0xD452EDDE, + (q31_t)0x87AE9CC5, (q31_t)0xD48230E8, (q31_t)0x879D7F40, + (q31_t)0xD4B17AA7, (q31_t)0x878C744C, (q31_t)0xD4E0CB14, + (q31_t)0x877B7BEC, (q31_t)0xD5102227, (q31_t)0x876A9621, + (q31_t)0xD53F7FDA, (q31_t)0x8759C2EF, (q31_t)0xD56EE424, + (q31_t)0x87490257, (q31_t)0xD59E4EFE, (q31_t)0x8738545E, + (q31_t)0xD5CDC062, (q31_t)0x8727B904, (q31_t)0xD5FD3847, + (q31_t)0x8717304E, (q31_t)0xD62CB6A7, (q31_t)0x8706BA3C, + (q31_t)0xD65C3B7B, (q31_t)0x86F656D3, (q31_t)0xD68BC6BA, + (q31_t)0x86E60614, (q31_t)0xD6BB585D, (q31_t)0x86D5C802, + (q31_t)0xD6EAF05E, (q31_t)0x86C59C9F, (q31_t)0xD71A8EB5, + (q31_t)0x86B583EE, (q31_t)0xD74A335A, (q31_t)0x86A57DF1, + (q31_t)0xD779DE46, (q31_t)0x86958AAB, (q31_t)0xD7A98F73, + (q31_t)0x8685AA1F, (q31_t)0xD7D946D7, (q31_t)0x8675DC4E, + (q31_t)0xD809046D, (q31_t)0x8666213C, (q31_t)0xD838C82D, + (q31_t)0x865678EA, (q31_t)0xD868920F, (q31_t)0x8646E35B, + (q31_t)0xD898620C, (q31_t)0x86376092, (q31_t)0xD8C8381C, + (q31_t)0x8627F090, (q31_t)0xD8F81439, (q31_t)0x86189359, + (q31_t)0xD927F65B, (q31_t)0x860948EE, (q31_t)0xD957DE7A, + (q31_t)0x85FA1152, (q31_t)0xD987CC8F, (q31_t)0x85EAEC88, + (q31_t)0xD9B7C093, (q31_t)0x85DBDA91, (q31_t)0xD9E7BA7E, + (q31_t)0x85CCDB70, (q31_t)0xDA17BA4A, (q31_t)0x85BDEF27, + (q31_t)0xDA47BFED, (q31_t)0x85AF15B9, (q31_t)0xDA77CB62, + (q31_t)0x85A04F28, (q31_t)0xDAA7DCA1, (q31_t)0x85919B75, + (q31_t)0xDAD7F3A2, (q31_t)0x8582FAA4, (q31_t)0xDB08105E, + (q31_t)0x85746CB7, (q31_t)0xDB3832CD, (q31_t)0x8565F1B0, + (q31_t)0xDB685AE8, (q31_t)0x85578991, (q31_t)0xDB9888A8, + (q31_t)0x8549345C, (q31_t)0xDBC8BC05, (q31_t)0x853AF214, + (q31_t)0xDBF8F4F8, (q31_t)0x852CC2BA, (q31_t)0xDC293379, + (q31_t)0x851EA652, (q31_t)0xDC597781, (q31_t)0x85109CDC, + (q31_t)0xDC89C108, (q31_t)0x8502A65C, (q31_t)0xDCBA1008, + (q31_t)0x84F4C2D3, (q31_t)0xDCEA6478, (q31_t)0x84E6F244, + (q31_t)0xDD1ABE51, (q31_t)0x84D934B0, (q31_t)0xDD4B1D8B, + (q31_t)0x84CB8A1B, (q31_t)0xDD7B8220, (q31_t)0x84BDF285, + (q31_t)0xDDABEC07, (q31_t)0x84B06DF1, (q31_t)0xDDDC5B3A, + (q31_t)0x84A2FC62, (q31_t)0xDE0CCFB1, (q31_t)0x84959DD9, + (q31_t)0xDE3D4963, (q31_t)0x84885257, (q31_t)0xDE6DC84B, + (q31_t)0x847B19E1, (q31_t)0xDE9E4C60, (q31_t)0x846DF476, + (q31_t)0xDECED59B, (q31_t)0x8460E21A, (q31_t)0xDEFF63F4, + (q31_t)0x8453E2CE, (q31_t)0xDF2FF764, (q31_t)0x8446F695, + (q31_t)0xDF608FE3, (q31_t)0x843A1D70, (q31_t)0xDF912D6A, + (q31_t)0x842D5761, (q31_t)0xDFC1CFF2, (q31_t)0x8420A46B, + (q31_t)0xDFF27773, (q31_t)0x8414048F, (q31_t)0xE02323E5, + (q31_t)0x840777CF, (q31_t)0xE053D541, (q31_t)0x83FAFE2E, + (q31_t)0xE0848B7F, (q31_t)0x83EE97AC, (q31_t)0xE0B54698, + (q31_t)0x83E2444D, (q31_t)0xE0E60684, (q31_t)0x83D60411, + (q31_t)0xE116CB3D, (q31_t)0x83C9D6FB, (q31_t)0xE14794B9, + (q31_t)0x83BDBD0D, (q31_t)0xE17862F3, (q31_t)0x83B1B649, + (q31_t)0xE1A935E1, (q31_t)0x83A5C2B0, (q31_t)0xE1DA0D7E, + (q31_t)0x8399E244, (q31_t)0xE20AE9C1, (q31_t)0x838E1507, + (q31_t)0xE23BCAA2, (q31_t)0x83825AFB, (q31_t)0xE26CB01A, + (q31_t)0x8376B422, (q31_t)0xE29D9A22, (q31_t)0x836B207D, + (q31_t)0xE2CE88B2, (q31_t)0x835FA00E, (q31_t)0xE2FF7BC3, + (q31_t)0x835432D8, (q31_t)0xE330734C, (q31_t)0x8348D8DB, + (q31_t)0xE3616F47, (q31_t)0x833D921A, (q31_t)0xE3926FAC, + (q31_t)0x83325E97, (q31_t)0xE3C37473, (q31_t)0x83273E52, + (q31_t)0xE3F47D95, (q31_t)0x831C314E, (q31_t)0xE4258B0A, + (q31_t)0x8311378C, (q31_t)0xE4569CCB, (q31_t)0x8306510F, + (q31_t)0xE487B2CF, (q31_t)0x82FB7DD8, (q31_t)0xE4B8CD10, + (q31_t)0x82F0BDE8, (q31_t)0xE4E9EB86, (q31_t)0x82E61141, + (q31_t)0xE51B0E2A, (q31_t)0x82DB77E5, (q31_t)0xE54C34F3, + (q31_t)0x82D0F1D5, (q31_t)0xE57D5FDA, (q31_t)0x82C67F13, + (q31_t)0xE5AE8ED8, (q31_t)0x82BC1FA1, (q31_t)0xE5DFC1E4, + (q31_t)0x82B1D381, (q31_t)0xE610F8F9, (q31_t)0x82A79AB3, + (q31_t)0xE642340D, (q31_t)0x829D753A, (q31_t)0xE6737319, + (q31_t)0x82936316, (q31_t)0xE6A4B616, (q31_t)0x8289644A, + (q31_t)0xE6D5FCFC, (q31_t)0x827F78D8, (q31_t)0xE70747C3, + (q31_t)0x8275A0C0, (q31_t)0xE7389664, (q31_t)0x826BDC04, + (q31_t)0xE769E8D8, (q31_t)0x82622AA5, (q31_t)0xE79B3F16, + (q31_t)0x82588CA6, (q31_t)0xE7CC9917, (q31_t)0x824F0208, + (q31_t)0xE7FDF6D3, (q31_t)0x82458ACB, (q31_t)0xE82F5844, + (q31_t)0x823C26F2, (q31_t)0xE860BD60, (q31_t)0x8232D67E, + (q31_t)0xE8922621, (q31_t)0x82299971, (q31_t)0xE8C3927F, + (q31_t)0x82206FCB, (q31_t)0xE8F50273, (q31_t)0x8217598F, + (q31_t)0xE92675F4, (q31_t)0x820E56BE, (q31_t)0xE957ECFB, + (q31_t)0x82056758, (q31_t)0xE9896780, (q31_t)0x81FC8B60, + (q31_t)0xE9BAE57C, (q31_t)0x81F3C2D7, (q31_t)0xE9EC66E8, + (q31_t)0x81EB0DBD, (q31_t)0xEA1DEBBB, (q31_t)0x81E26C16, + (q31_t)0xEA4F73EE, (q31_t)0x81D9DDE1, (q31_t)0xEA80FF79, + (q31_t)0x81D16320, (q31_t)0xEAB28E55, (q31_t)0x81C8FBD5, + (q31_t)0xEAE4207A, (q31_t)0x81C0A801, (q31_t)0xEB15B5E0, + (q31_t)0x81B867A4, (q31_t)0xEB474E80, (q31_t)0x81B03AC1, + (q31_t)0xEB78EA52, (q31_t)0x81A82159, (q31_t)0xEBAA894E, + (q31_t)0x81A01B6C, (q31_t)0xEBDC2B6D, (q31_t)0x819828FD, + (q31_t)0xEC0DD0A8, (q31_t)0x81904A0C, (q31_t)0xEC3F78F5, + (q31_t)0x81887E9A, (q31_t)0xEC71244F, (q31_t)0x8180C6A9, + (q31_t)0xECA2D2AC, (q31_t)0x8179223A, (q31_t)0xECD48406, + (q31_t)0x8171914E, (q31_t)0xED063855, (q31_t)0x816A13E6, + (q31_t)0xED37EF91, (q31_t)0x8162AA03, (q31_t)0xED69A9B2, + (q31_t)0x815B53A8, (q31_t)0xED9B66B2, (q31_t)0x815410D3, + (q31_t)0xEDCD2687, (q31_t)0x814CE188, (q31_t)0xEDFEE92B, + (q31_t)0x8145C5C6, (q31_t)0xEE30AE95, (q31_t)0x813EBD90, + (q31_t)0xEE6276BF, (q31_t)0x8137C8E6, (q31_t)0xEE9441A0, + (q31_t)0x8130E7C8, (q31_t)0xEEC60F31, (q31_t)0x812A1A39, + (q31_t)0xEEF7DF6A, (q31_t)0x81236039, (q31_t)0xEF29B243, + (q31_t)0x811CB9CA, (q31_t)0xEF5B87B5, (q31_t)0x811626EC, + (q31_t)0xEF8D5FB8, (q31_t)0x810FA7A0, (q31_t)0xEFBF3A44, + (q31_t)0x81093BE8, (q31_t)0xEFF11752, (q31_t)0x8102E3C3, + (q31_t)0xF022F6DA, (q31_t)0x80FC9F35, (q31_t)0xF054D8D4, + (q31_t)0x80F66E3C, (q31_t)0xF086BD39, (q31_t)0x80F050DB, + (q31_t)0xF0B8A401, (q31_t)0x80EA4712, (q31_t)0xF0EA8D23, + (q31_t)0x80E450E2, (q31_t)0xF11C789A, (q31_t)0x80DE6E4C, + (q31_t)0xF14E665C, (q31_t)0x80D89F51, (q31_t)0xF1805662, + (q31_t)0x80D2E3F1, (q31_t)0xF1B248A5, (q31_t)0x80CD3C2F, + (q31_t)0xF1E43D1C, (q31_t)0x80C7A80A, (q31_t)0xF21633C0, + (q31_t)0x80C22783, (q31_t)0xF2482C89, (q31_t)0x80BCBA9C, + (q31_t)0xF27A2770, (q31_t)0x80B76155, (q31_t)0xF2AC246D, + (q31_t)0x80B21BAF, (q31_t)0xF2DE2378, (q31_t)0x80ACE9AB, + (q31_t)0xF310248A, (q31_t)0x80A7CB49, (q31_t)0xF342279A, + (q31_t)0x80A2C08B, (q31_t)0xF3742CA1, (q31_t)0x809DC970, + (q31_t)0xF3A63398, (q31_t)0x8098E5FB, (q31_t)0xF3D83C76, + (q31_t)0x8094162B, (q31_t)0xF40A4734, (q31_t)0x808F5A02, + (q31_t)0xF43C53CA, (q31_t)0x808AB180, (q31_t)0xF46E6231, + (q31_t)0x80861CA5, (q31_t)0xF4A07260, (q31_t)0x80819B74, + (q31_t)0xF4D28451, (q31_t)0x807D2DEB, (q31_t)0xF50497FA, + (q31_t)0x8078D40D, (q31_t)0xF536AD55, (q31_t)0x80748DD9, + (q31_t)0xF568C45A, (q31_t)0x80705B50, (q31_t)0xF59ADD01, + (q31_t)0x806C3C73, (q31_t)0xF5CCF743, (q31_t)0x80683143, + (q31_t)0xF5FF1317, (q31_t)0x806439C0, (q31_t)0xF6313076, + (q31_t)0x806055EA, (q31_t)0xF6634F58, (q31_t)0x805C85C3, + (q31_t)0xF6956FB6, (q31_t)0x8058C94C, (q31_t)0xF6C79188, + (q31_t)0x80552083, (q31_t)0xF6F9B4C5, (q31_t)0x80518B6B, + (q31_t)0xF72BD967, (q31_t)0x804E0A03, (q31_t)0xF75DFF65, + (q31_t)0x804A9C4D, (q31_t)0xF79026B8, (q31_t)0x80474248, + (q31_t)0xF7C24F58, (q31_t)0x8043FBF6, (q31_t)0xF7F4793E, + (q31_t)0x8040C956, (q31_t)0xF826A461, (q31_t)0x803DAA69, + (q31_t)0xF858D0BA, (q31_t)0x803A9F31, (q31_t)0xF88AFE41, + (q31_t)0x8037A7AC, (q31_t)0xF8BD2CEF, (q31_t)0x8034C3DC, + (q31_t)0xF8EF5CBB, (q31_t)0x8031F3C1, (q31_t)0xF9218D9E, + (q31_t)0x802F375C, (q31_t)0xF953BF90, (q31_t)0x802C8EAD, + (q31_t)0xF985F28A, (q31_t)0x8029F9B4, (q31_t)0xF9B82683, + (q31_t)0x80277872, (q31_t)0xF9EA5B75, (q31_t)0x80250AE7, + (q31_t)0xFA1C9156, (q31_t)0x8022B113, (q31_t)0xFA4EC820, + (q31_t)0x80206AF8, (q31_t)0xFA80FFCB, (q31_t)0x801E3894, + (q31_t)0xFAB3384F, (q31_t)0x801C19E9, (q31_t)0xFAE571A4, + (q31_t)0x801A0EF7, (q31_t)0xFB17ABC2, (q31_t)0x801817BF, + (q31_t)0xFB49E6A2, (q31_t)0x80163440, (q31_t)0xFB7C223C, + (q31_t)0x8014647A, (q31_t)0xFBAE5E89, (q31_t)0x8012A86F, + (q31_t)0xFBE09B80, (q31_t)0x8011001E, (q31_t)0xFC12D919, + (q31_t)0x800F6B88, (q31_t)0xFC45174E, (q31_t)0x800DEAAC, + (q31_t)0xFC775616, (q31_t)0x800C7D8C, (q31_t)0xFCA99569, + (q31_t)0x800B2427, (q31_t)0xFCDBD541, (q31_t)0x8009DE7D, + (q31_t)0xFD0E1594, (q31_t)0x8008AC90, (q31_t)0xFD40565B, + (q31_t)0x80078E5E, (q31_t)0xFD72978F, (q31_t)0x800683E8, + (q31_t)0xFDA4D928, (q31_t)0x80058D2E, (q31_t)0xFDD71B1E, + (q31_t)0x8004AA31, (q31_t)0xFE095D69, (q31_t)0x8003DAF0, + (q31_t)0xFE3BA001, (q31_t)0x80031F6C, (q31_t)0xFE6DE2E0, + (q31_t)0x800277A5, (q31_t)0xFEA025FC, (q31_t)0x8001E39B, + (q31_t)0xFED2694F, (q31_t)0x8001634D, (q31_t)0xFF04ACD0, + (q31_t)0x8000F6BD, (q31_t)0xFF36F078, (q31_t)0x80009DE9, + (q31_t)0xFF69343E, (q31_t)0x800058D3, (q31_t)0xFF9B781D, + (q31_t)0x8000277A, (q31_t)0xFFCDBC0A, (q31_t)0x800009DE +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @brief q15 Twiddle factors Table +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
fori = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 16, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_16_q15[24] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xCF04, (q15_t)0x89BE +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 32, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_32_q15[48] = { + (q15_t)0x7FFF, (q15_t)0x0000, + (q15_t)0x7D8A, (q15_t)0x18F8, + (q15_t)0x7641, (q15_t)0x30FB, + (q15_t)0x6A6D, (q15_t)0x471C, + (q15_t)0x5A82, (q15_t)0x5A82, + (q15_t)0x471C, (q15_t)0x6A6D, + (q15_t)0x30FB, (q15_t)0x7641, + (q15_t)0x18F8, (q15_t)0x7D8A, + (q15_t)0x0000, (q15_t)0x7FFF, + (q15_t)0xE707, (q15_t)0x7D8A, + (q15_t)0xCF04, (q15_t)0x7641, + (q15_t)0xB8E3, (q15_t)0x6A6D, + (q15_t)0xA57D, (q15_t)0x5A82, + (q15_t)0x9592, (q15_t)0x471C, + (q15_t)0x89BE, (q15_t)0x30FB, + (q15_t)0x8275, (q15_t)0x18F8, + (q15_t)0x8000, (q15_t)0x0000, + (q15_t)0x8275, (q15_t)0xE707, + (q15_t)0x89BE, (q15_t)0xCF04, + (q15_t)0x9592, (q15_t)0xB8E3, + (q15_t)0xA57D, (q15_t)0xA57D, + (q15_t)0xB8E3, (q15_t)0x9592, + (q15_t)0xCF04, (q15_t)0x89BE, + (q15_t)0xE707, (q15_t)0x8275 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 64, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_64_q15[96] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7F62, (q15_t)0x0C8B, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7A7D, (q15_t)0x2528, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x70E2, (q15_t)0x3C56, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x62F2, (q15_t)0x5133, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5133, (q15_t)0x62F2, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x3C56, (q15_t)0x70E2, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2528, (q15_t)0x7A7D, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x0C8B, (q15_t)0x7F62, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF374, (q15_t)0x7F62, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xDAD7, (q15_t)0x7A7D, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC3A9, (q15_t)0x70E2, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xAECC, (q15_t)0x62F2, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0x9D0D, (q15_t)0x5133, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x8F1D, (q15_t)0x3C56, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8582, (q15_t)0x2528, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x809D, (q15_t)0x0C8B, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x809D, (q15_t)0xF374, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8582, (q15_t)0xDAD7, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8F1D, (q15_t)0xC3A9, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9D0D, (q15_t)0xAECC, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAECC, (q15_t)0x9D0D, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xC3A9, (q15_t)0x8F1D, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xDAD7, (q15_t)0x8582, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xF374, (q15_t)0x809D +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 128, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_128_q15[192] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FD8, (q15_t)0x0647, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7E9D, (q15_t)0x12C8, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7C29, (q15_t)0x1F19, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7884, (q15_t)0x2B1F, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x73B5, (q15_t)0x36BA, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6DCA, (q15_t)0x41CE, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x66CF, (q15_t)0x4C3F, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x5ED7, (q15_t)0x55F5, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x55F5, (q15_t)0x5ED7, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4C3F, (q15_t)0x66CF, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x41CE, (q15_t)0x6DCA, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x36BA, (q15_t)0x73B5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2B1F, (q15_t)0x7884, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x1F19, (q15_t)0x7C29, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x12C8, (q15_t)0x7E9D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0647, (q15_t)0x7FD8, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xF9B8, (q15_t)0x7FD8, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xED37, (q15_t)0x7E9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE0E6, (q15_t)0x7C29, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD4E0, (q15_t)0x7884, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xC945, (q15_t)0x73B5, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xBE31, (q15_t)0x6DCA, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB3C0, (q15_t)0x66CF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAA0A, (q15_t)0x5ED7, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA128, (q15_t)0x55F5, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9930, (q15_t)0x4C3F, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9235, (q15_t)0x41CE, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8C4A, (q15_t)0x36BA, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x877B, (q15_t)0x2B1F, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x83D6, (q15_t)0x1F19, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8162, (q15_t)0x12C8, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8027, (q15_t)0x0647, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8027, (q15_t)0xF9B8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x8162, (q15_t)0xED37, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x83D6, (q15_t)0xE0E6, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x877B, (q15_t)0xD4E0, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8C4A, (q15_t)0xC945, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x9235, (q15_t)0xBE31, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9930, (q15_t)0xB3C0, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0xA128, (q15_t)0xAA0A, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xAA0A, (q15_t)0xA128, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB3C0, (q15_t)0x9930, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBE31, (q15_t)0x9235, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC945, (q15_t)0x8C4A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD4E0, (q15_t)0x877B, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xE0E6, (q15_t)0x83D6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xED37, (q15_t)0x8162, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF9B8, (q15_t)0x8027 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 256, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_256_q15[384] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FF6, (q15_t)0x0324, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FA7, (q15_t)0x096A, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F09, (q15_t)0x0FAB, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E1D, (q15_t)0x15E2, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7CE3, (q15_t)0x1C0B, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7B5D, (q15_t)0x2223, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x798A, (q15_t)0x2826, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x776C, (q15_t)0x2E11, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x7504, (q15_t)0x33DE, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7255, (q15_t)0x398C, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x6F5F, (q15_t)0x3F17, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6C24, (q15_t)0x447A, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x68A6, (q15_t)0x49B4, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x64E8, (q15_t)0x4EBF, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x60EC, (q15_t)0x539B, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5CB4, (q15_t)0x5842, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5842, (q15_t)0x5CB4, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x539B, (q15_t)0x60EC, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4EBF, (q15_t)0x64E8, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x49B4, (q15_t)0x68A6, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x447A, (q15_t)0x6C24, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x3F17, (q15_t)0x6F5F, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x398C, (q15_t)0x7255, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x33DE, (q15_t)0x7504, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2E11, (q15_t)0x776C, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2826, (q15_t)0x798A, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2223, (q15_t)0x7B5D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1C0B, (q15_t)0x7CE3, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x15E2, (q15_t)0x7E1D, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x0FAB, (q15_t)0x7F09, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x096A, (q15_t)0x7FA7, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0324, (q15_t)0x7FF6, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFCDB, (q15_t)0x7FF6, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF695, (q15_t)0x7FA7, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF054, (q15_t)0x7F09, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEA1D, (q15_t)0x7E1D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE3F4, (q15_t)0x7CE3, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDDDC, (q15_t)0x7B5D, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD7D9, (q15_t)0x798A, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD1EE, (q15_t)0x776C, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCC21, (q15_t)0x7504, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC673, (q15_t)0x7255, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC0E8, (q15_t)0x6F5F, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBB85, (q15_t)0x6C24, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB64B, (q15_t)0x68A6, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB140, (q15_t)0x64E8, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAC64, (q15_t)0x60EC, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA7BD, (q15_t)0x5CB4, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA34B, (q15_t)0x5842, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0x9F13, (q15_t)0x539B, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9B17, (q15_t)0x4EBF, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9759, (q15_t)0x49B4, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x93DB, (q15_t)0x447A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x90A0, (q15_t)0x3F17, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8DAA, (q15_t)0x398C, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8AFB, (q15_t)0x33DE, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8893, (q15_t)0x2E11, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8675, (q15_t)0x2826, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x84A2, (q15_t)0x2223, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x831C, (q15_t)0x1C0B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x81E2, (q15_t)0x15E2, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x80F6, (q15_t)0x0FAB, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8058, (q15_t)0x096A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8009, (q15_t)0x0324, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8009, (q15_t)0xFCDB, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8058, (q15_t)0xF695, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80F6, (q15_t)0xF054, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81E2, (q15_t)0xEA1D, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x831C, (q15_t)0xE3F4, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x84A2, (q15_t)0xDDDC, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8675, (q15_t)0xD7D9, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8893, (q15_t)0xD1EE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8AFB, (q15_t)0xCC21, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8DAA, (q15_t)0xC673, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x90A0, (q15_t)0xC0E8, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x93DB, (q15_t)0xBB85, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9759, (q15_t)0xB64B, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9B17, (q15_t)0xB140, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9F13, (q15_t)0xAC64, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA34B, (q15_t)0xA7BD, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA7BD, (q15_t)0xA34B, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAC64, (q15_t)0x9F13, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB140, (q15_t)0x9B17, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB64B, (q15_t)0x9759, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBB85, (q15_t)0x93DB, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xC0E8, (q15_t)0x90A0, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC673, (q15_t)0x8DAA, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCC21, (q15_t)0x8AFB, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD1EE, (q15_t)0x8893, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD7D9, (q15_t)0x8675, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDDDC, (q15_t)0x84A2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE3F4, (q15_t)0x831C, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xEA1D, (q15_t)0x81E2, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xF054, (q15_t)0x80F6, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF695, (q15_t)0x8058, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFCDB, (q15_t)0x8009 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 512, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_512_q15[768] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFD, (q15_t)0x0192, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FE9, (q15_t)0x04B6, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FC2, (q15_t)0x07D9, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F87, (q15_t)0x0AFB, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F38, (q15_t)0x0E1B, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7ED5, (q15_t)0x1139, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E5F, (q15_t)0x1455, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DD6, (q15_t)0x176D, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D39, (q15_t)0x1A82, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7C89, (q15_t)0x1D93, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BC5, (q15_t)0x209F, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7AEF, (q15_t)0x23A6, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A05, (q15_t)0x26A8, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x7909, (q15_t)0x29A3, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x77FA, (q15_t)0x2C98, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x76D9, (q15_t)0x2F87, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75A5, (q15_t)0x326E, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x745F, (q15_t)0x354D, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x7307, (q15_t)0x3824, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x719E, (q15_t)0x3AF2, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7023, (q15_t)0x3DB8, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6E96, (q15_t)0x4073, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6CF9, (q15_t)0x4325, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6B4A, (q15_t)0x45CD, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x698C, (q15_t)0x4869, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x67BD, (q15_t)0x4AFB, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x65DD, (q15_t)0x4D81, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x63EF, (q15_t)0x4FFB, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x61F1, (q15_t)0x5269, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x5FE3, (q15_t)0x54CA, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5DC7, (q15_t)0x571D, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5B9D, (q15_t)0x5964, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5964, (q15_t)0x5B9D, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x571D, (q15_t)0x5DC7, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x54CA, (q15_t)0x5FE3, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5269, (q15_t)0x61F1, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x4FFB, (q15_t)0x63EF, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4D81, (q15_t)0x65DD, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4AFB, (q15_t)0x67BD, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4869, (q15_t)0x698C, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x45CD, (q15_t)0x6B4A, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4325, (q15_t)0x6CF9, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4073, (q15_t)0x6E96, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3DB8, (q15_t)0x7023, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3AF2, (q15_t)0x719E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3824, (q15_t)0x7307, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x354D, (q15_t)0x745F, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x326E, (q15_t)0x75A5, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x2F87, (q15_t)0x76D9, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2C98, (q15_t)0x77FA, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x29A3, (q15_t)0x7909, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x26A8, (q15_t)0x7A05, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x23A6, (q15_t)0x7AEF, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x209F, (q15_t)0x7BC5, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1D93, (q15_t)0x7C89, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1A82, (q15_t)0x7D39, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x176D, (q15_t)0x7DD6, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x1455, (q15_t)0x7E5F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1139, (q15_t)0x7ED5, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0E1B, (q15_t)0x7F38, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0AFB, (q15_t)0x7F87, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x07D9, (q15_t)0x7FC2, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x04B6, (q15_t)0x7FE9, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x0192, (q15_t)0x7FFD, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFE6D, (q15_t)0x7FFD, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFB49, (q15_t)0x7FE9, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF826, (q15_t)0x7FC2, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF504, (q15_t)0x7F87, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF1E4, (q15_t)0x7F38, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEEC6, (q15_t)0x7ED5, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEBAA, (q15_t)0x7E5F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE892, (q15_t)0x7DD6, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE57D, (q15_t)0x7D39, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE26C, (q15_t)0x7C89, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xDF60, (q15_t)0x7BC5, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDC59, (q15_t)0x7AEF, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xD957, (q15_t)0x7A05, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD65C, (q15_t)0x7909, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD367, (q15_t)0x77FA, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD078, (q15_t)0x76D9, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCD91, (q15_t)0x75A5, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCAB2, (q15_t)0x745F, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC7DB, (q15_t)0x7307, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC50D, (q15_t)0x719E, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC247, (q15_t)0x7023, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xBF8C, (q15_t)0x6E96, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBCDA, (q15_t)0x6CF9, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBA32, (q15_t)0x6B4A, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB796, (q15_t)0x698C, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB504, (q15_t)0x67BD, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB27E, (q15_t)0x65DD, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB004, (q15_t)0x63EF, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAD96, (q15_t)0x61F1, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAB35, (q15_t)0x5FE3, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA8E2, (q15_t)0x5DC7, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA69B, (q15_t)0x5B9D, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA462, (q15_t)0x5964, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA238, (q15_t)0x571D, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA01C, (q15_t)0x54CA, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E0E, (q15_t)0x5269, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C10, (q15_t)0x4FFB, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A22, (q15_t)0x4D81, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9842, (q15_t)0x4AFB, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x9673, (q15_t)0x4869, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x94B5, (q15_t)0x45CD, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9306, (q15_t)0x4325, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9169, (q15_t)0x4073, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x8FDC, (q15_t)0x3DB8, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8E61, (q15_t)0x3AF2, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8CF8, (q15_t)0x3824, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BA0, (q15_t)0x354D, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8A5A, (q15_t)0x326E, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8926, (q15_t)0x2F87, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8805, (q15_t)0x2C98, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x86F6, (q15_t)0x29A3, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x85FA, (q15_t)0x26A8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8510, (q15_t)0x23A6, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x843A, (q15_t)0x209F, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x8376, (q15_t)0x1D93, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82C6, (q15_t)0x1A82, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8229, (q15_t)0x176D, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81A0, (q15_t)0x1455, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x812A, (q15_t)0x1139, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80C7, (q15_t)0x0E1B, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8078, (q15_t)0x0AFB, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x803D, (q15_t)0x07D9, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8016, (q15_t)0x04B6, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8002, (q15_t)0x0192, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8002, (q15_t)0xFE6D, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x8016, (q15_t)0xFB49, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x803D, (q15_t)0xF826, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8078, (q15_t)0xF504, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80C7, (q15_t)0xF1E4, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x812A, (q15_t)0xEEC6, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x81A0, (q15_t)0xEBAA, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8229, (q15_t)0xE892, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x82C6, (q15_t)0xE57D, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8376, (q15_t)0xE26C, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x843A, (q15_t)0xDF60, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x8510, (q15_t)0xDC59, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85FA, (q15_t)0xD957, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86F6, (q15_t)0xD65C, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x8805, (q15_t)0xD367, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x8926, (q15_t)0xD078, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A5A, (q15_t)0xCD91, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8BA0, (q15_t)0xCAB2, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CF8, (q15_t)0xC7DB, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E61, (q15_t)0xC50D, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8FDC, (q15_t)0xC247, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9169, (q15_t)0xBF8C, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9306, (q15_t)0xBCDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x94B5, (q15_t)0xBA32, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9673, (q15_t)0xB796, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9842, (q15_t)0xB504, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x9A22, (q15_t)0xB27E, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9C10, (q15_t)0xB004, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9E0E, (q15_t)0xAD96, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0xA01C, (q15_t)0xAB35, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA238, (q15_t)0xA8E2, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA462, (q15_t)0xA69B, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA69B, (q15_t)0xA462, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA8E2, (q15_t)0xA238, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAB35, (q15_t)0xA01C, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAD96, (q15_t)0x9E0E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xB004, (q15_t)0x9C10, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB27E, (q15_t)0x9A22, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB504, (q15_t)0x9842, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB796, (q15_t)0x9673, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xBA32, (q15_t)0x94B5, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBCDA, (q15_t)0x9306, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBF8C, (q15_t)0x9169, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC247, (q15_t)0x8FDC, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC50D, (q15_t)0x8E61, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC7DB, (q15_t)0x8CF8, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xCAB2, (q15_t)0x8BA0, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCD91, (q15_t)0x8A5A, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xD078, (q15_t)0x8926, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD367, (q15_t)0x8805, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD65C, (q15_t)0x86F6, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD957, (q15_t)0x85FA, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDC59, (q15_t)0x8510, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDF60, (q15_t)0x843A, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE26C, (q15_t)0x8376, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE57D, (q15_t)0x82C6, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE892, (q15_t)0x8229, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEBAA, (q15_t)0x81A0, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEEC6, (q15_t)0x812A, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF1E4, (q15_t)0x80C7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF504, (q15_t)0x8078, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF826, (q15_t)0x803D, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFB49, (q15_t)0x8016, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFE6D, (q15_t)0x8002 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 1024, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + + */ +const q15_t twiddleCoef_1024_q15[1536] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x00C9, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFA, (q15_t)0x025B, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF0, (q15_t)0x03ED, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE1, (q15_t)0x057F, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FCE, (q15_t)0x0710, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FB5, (q15_t)0x08A2, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F97, (q15_t)0x0A33, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F75, (q15_t)0x0BC3, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F4D, (q15_t)0x0D53, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F21, (q15_t)0x0EE3, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EF0, (q15_t)0x1072, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EBA, (q15_t)0x1201, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E7F, (q15_t)0x138E, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E3F, (q15_t)0x151B, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7DFA, (q15_t)0x16A8, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DB0, (q15_t)0x1833, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D62, (q15_t)0x19BD, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D0F, (q15_t)0x1B47, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CB7, (q15_t)0x1CCF, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C5A, (q15_t)0x1E56, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7BF8, (q15_t)0x1FDC, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7B92, (q15_t)0x2161, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B26, (q15_t)0x22E5, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AB6, (q15_t)0x2467, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A42, (q15_t)0x25E8, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79C8, (q15_t)0x2767, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x794A, (q15_t)0x28E5, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78C7, (q15_t)0x2A61, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7840, (q15_t)0x2BDC, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77B4, (q15_t)0x2D55, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7723, (q15_t)0x2ECC, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x768E, (q15_t)0x3041, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x75F4, (q15_t)0x31B5, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7555, (q15_t)0x3326, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74B2, (q15_t)0x3496, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x740B, (q15_t)0x3604, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x735F, (q15_t)0x376F, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72AF, (q15_t)0x38D8, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x71FA, (q15_t)0x3A40, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7141, (q15_t)0x3BA5, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x7083, (q15_t)0x3D07, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FC1, (q15_t)0x3E68, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6EFB, (q15_t)0x3FC5, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E30, (q15_t)0x4121, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D62, (q15_t)0x427A, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6C8F, (q15_t)0x43D0, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BB8, (q15_t)0x4524, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6ADC, (q15_t)0x4675, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x69FD, (q15_t)0x47C3, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6919, (q15_t)0x490F, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6832, (q15_t)0x4A58, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6746, (q15_t)0x4B9E, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6657, (q15_t)0x4CE1, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x6563, (q15_t)0x4E21, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x646C, (q15_t)0x4F5E, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x6371, (q15_t)0x5097, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x6271, (q15_t)0x51CE, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x616F, (q15_t)0x5302, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x6068, (q15_t)0x5433, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5F5E, (q15_t)0x5560, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E50, (q15_t)0x568A, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D3E, (q15_t)0x57B0, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C29, (q15_t)0x58D4, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B10, (q15_t)0x59F3, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x59F3, (q15_t)0x5B10, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x58D4, (q15_t)0x5C29, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57B0, (q15_t)0x5D3E, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x568A, (q15_t)0x5E50, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x5560, (q15_t)0x5F5E, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x5433, (q15_t)0x6068, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5302, (q15_t)0x616F, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x51CE, (q15_t)0x6271, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x5097, (q15_t)0x6371, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4F5E, (q15_t)0x646C, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E21, (q15_t)0x6563, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4CE1, (q15_t)0x6657, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4B9E, (q15_t)0x6746, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4A58, (q15_t)0x6832, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x490F, (q15_t)0x6919, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x47C3, (q15_t)0x69FD, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x4675, (q15_t)0x6ADC, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4524, (q15_t)0x6BB8, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x43D0, (q15_t)0x6C8F, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x427A, (q15_t)0x6D62, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4121, (q15_t)0x6E30, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x3FC5, (q15_t)0x6EFB, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3E68, (q15_t)0x6FC1, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D07, (q15_t)0x7083, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BA5, (q15_t)0x7141, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A40, (q15_t)0x71FA, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x38D8, (q15_t)0x72AF, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x376F, (q15_t)0x735F, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x3604, (q15_t)0x740B, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x3496, (q15_t)0x74B2, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3326, (q15_t)0x7555, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x31B5, (q15_t)0x75F4, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x3041, (q15_t)0x768E, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2ECC, (q15_t)0x7723, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2D55, (q15_t)0x77B4, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2BDC, (q15_t)0x7840, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2A61, (q15_t)0x78C7, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x28E5, (q15_t)0x794A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x2767, (q15_t)0x79C8, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x25E8, (q15_t)0x7A42, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x2467, (q15_t)0x7AB6, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x22E5, (q15_t)0x7B26, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x2161, (q15_t)0x7B92, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x1FDC, (q15_t)0x7BF8, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1E56, (q15_t)0x7C5A, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1CCF, (q15_t)0x7CB7, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1B47, (q15_t)0x7D0F, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x19BD, (q15_t)0x7D62, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1833, (q15_t)0x7DB0, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x16A8, (q15_t)0x7DFA, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x151B, (q15_t)0x7E3F, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x138E, (q15_t)0x7E7F, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1201, (q15_t)0x7EBA, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1072, (q15_t)0x7EF0, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0EE3, (q15_t)0x7F21, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0D53, (q15_t)0x7F4D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0BC3, (q15_t)0x7F75, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A33, (q15_t)0x7F97, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x08A2, (q15_t)0x7FB5, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0710, (q15_t)0x7FCE, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x057F, (q15_t)0x7FE1, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x03ED, (q15_t)0x7FF0, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x025B, (q15_t)0x7FFA, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x00C9, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF36, (q15_t)0x7FFF, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFDA4, (q15_t)0x7FFA, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC12, (q15_t)0x7FF0, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFA80, (q15_t)0x7FE1, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF8EF, (q15_t)0x7FCE, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF75D, (q15_t)0x7FB5, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF5CC, (q15_t)0x7F97, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF43C, (q15_t)0x7F75, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF2AC, (q15_t)0x7F4D, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF11C, (q15_t)0x7F21, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEF8D, (q15_t)0x7EF0, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEDFE, (q15_t)0x7EBA, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xEC71, (q15_t)0x7E7F, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEAE4, (q15_t)0x7E3F, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE957, (q15_t)0x7DFA, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE7CC, (q15_t)0x7DB0, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE642, (q15_t)0x7D62, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE4B8, (q15_t)0x7D0F, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE330, (q15_t)0x7CB7, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE1A9, (q15_t)0x7C5A, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE023, (q15_t)0x7BF8, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDE9E, (q15_t)0x7B92, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD1A, (q15_t)0x7B26, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDB98, (q15_t)0x7AB6, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA17, (q15_t)0x7A42, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD898, (q15_t)0x79C8, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD71A, (q15_t)0x794A, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD59E, (q15_t)0x78C7, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD423, (q15_t)0x7840, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD2AA, (q15_t)0x77B4, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD133, (q15_t)0x7723, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xCFBE, (q15_t)0x768E, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCE4A, (q15_t)0x75F4, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCCD9, (q15_t)0x7555, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCB69, (q15_t)0x74B2, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xC9FB, (q15_t)0x740B, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC890, (q15_t)0x735F, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC727, (q15_t)0x72AF, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC5BF, (q15_t)0x71FA, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC45A, (q15_t)0x7141, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC2F8, (q15_t)0x7083, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC197, (q15_t)0x6FC1, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC03A, (q15_t)0x6EFB, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBEDE, (q15_t)0x6E30, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBD85, (q15_t)0x6D62, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC2F, (q15_t)0x6C8F, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBADB, (q15_t)0x6BB8, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB98A, (q15_t)0x6ADC, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB83C, (q15_t)0x69FD, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB6F0, (q15_t)0x6919, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5A7, (q15_t)0x6832, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB461, (q15_t)0x6746, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB31E, (q15_t)0x6657, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB1DE, (q15_t)0x6563, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0A1, (q15_t)0x646C, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAF68, (q15_t)0x6371, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE31, (q15_t)0x6271, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xACFD, (q15_t)0x616F, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xABCC, (q15_t)0x6068, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAA9F, (q15_t)0x5F5E, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA975, (q15_t)0x5E50, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA84F, (q15_t)0x5D3E, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA72B, (q15_t)0x5C29, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA60C, (q15_t)0x5B10, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA4EF, (q15_t)0x59F3, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA3D6, (q15_t)0x58D4, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA2C1, (q15_t)0x57B0, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1AF, (q15_t)0x568A, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0A1, (q15_t)0x5560, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9F97, (q15_t)0x5433, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9E90, (q15_t)0x5302, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9D8E, (q15_t)0x51CE, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9C8E, (q15_t)0x5097, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9B93, (q15_t)0x4F5E, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9A9C, (q15_t)0x4E21, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99A8, (q15_t)0x4CE1, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98B9, (q15_t)0x4B9E, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x97CD, (q15_t)0x4A58, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x96E6, (q15_t)0x490F, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9602, (q15_t)0x47C3, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9523, (q15_t)0x4675, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9447, (q15_t)0x4524, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x9370, (q15_t)0x43D0, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x929D, (q15_t)0x427A, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x91CF, (q15_t)0x4121, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9104, (q15_t)0x3FC5, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x903E, (q15_t)0x3E68, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8F7C, (q15_t)0x3D07, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EBE, (q15_t)0x3BA5, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E05, (q15_t)0x3A40, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D50, (q15_t)0x38D8, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CA0, (q15_t)0x376F, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8BF4, (q15_t)0x3604, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B4D, (q15_t)0x3496, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AAA, (q15_t)0x3326, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A0B, (q15_t)0x31B5, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8971, (q15_t)0x3041, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x88DC, (q15_t)0x2ECC, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x884B, (q15_t)0x2D55, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87BF, (q15_t)0x2BDC, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8738, (q15_t)0x2A61, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86B5, (q15_t)0x28E5, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8637, (q15_t)0x2767, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85BD, (q15_t)0x25E8, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8549, (q15_t)0x2467, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84D9, (q15_t)0x22E5, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x846D, (q15_t)0x2161, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8407, (q15_t)0x1FDC, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83A5, (q15_t)0x1E56, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x8348, (q15_t)0x1CCF, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x82F0, (q15_t)0x1B47, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x829D, (q15_t)0x19BD, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x824F, (q15_t)0x1833, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8205, (q15_t)0x16A8, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81C0, (q15_t)0x151B, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8180, (q15_t)0x138E, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8145, (q15_t)0x1201, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x810F, (q15_t)0x1072, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80DE, (q15_t)0x0EE3, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80B2, (q15_t)0x0D53, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x808A, (q15_t)0x0BC3, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8068, (q15_t)0x0A33, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x804A, (q15_t)0x08A2, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8031, (q15_t)0x0710, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x801E, (q15_t)0x057F, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x800F, (q15_t)0x03ED, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8005, (q15_t)0x025B, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8000, (q15_t)0x00C9, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF36, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8005, (q15_t)0xFDA4, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800F, (q15_t)0xFC12, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801E, (q15_t)0xFA80, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8031, (q15_t)0xF8EF, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x804A, (q15_t)0xF75D, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8068, (q15_t)0xF5CC, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x808A, (q15_t)0xF43C, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80B2, (q15_t)0xF2AC, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80DE, (q15_t)0xF11C, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x810F, (q15_t)0xEF8D, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8145, (q15_t)0xEDFE, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8180, (q15_t)0xEC71, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81C0, (q15_t)0xEAE4, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x8205, (q15_t)0xE957, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x824F, (q15_t)0xE7CC, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x829D, (q15_t)0xE642, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82F0, (q15_t)0xE4B8, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8348, (q15_t)0xE330, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x83A5, (q15_t)0xE1A9, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x8407, (q15_t)0xE023, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x846D, (q15_t)0xDE9E, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84D9, (q15_t)0xDD1A, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x8549, (q15_t)0xDB98, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85BD, (q15_t)0xDA17, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8637, (q15_t)0xD898, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x86B5, (q15_t)0xD71A, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8738, (q15_t)0xD59E, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x87BF, (q15_t)0xD423, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x884B, (q15_t)0xD2AA, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88DC, (q15_t)0xD133, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8971, (q15_t)0xCFBE, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x8A0B, (q15_t)0xCE4A, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8AAA, (q15_t)0xCCD9, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B4D, (q15_t)0xCB69, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BF4, (q15_t)0xC9FB, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8CA0, (q15_t)0xC890, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D50, (q15_t)0xC727, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8E05, (q15_t)0xC5BF, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8EBE, (q15_t)0xC45A, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F7C, (q15_t)0xC2F8, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x903E, (q15_t)0xC197, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x9104, (q15_t)0xC03A, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x91CF, (q15_t)0xBEDE, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x929D, (q15_t)0xBD85, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9370, (q15_t)0xBC2F, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9447, (q15_t)0xBADB, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x9523, (q15_t)0xB98A, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x9602, (q15_t)0xB83C, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96E6, (q15_t)0xB6F0, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x97CD, (q15_t)0xB5A7, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x98B9, (q15_t)0xB461, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x99A8, (q15_t)0xB31E, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A9C, (q15_t)0xB1DE, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B93, (q15_t)0xB0A1, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C8E, (q15_t)0xAF68, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D8E, (q15_t)0xAE31, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E90, (q15_t)0xACFD, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F97, (q15_t)0xABCC, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA0A1, (q15_t)0xAA9F, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA1AF, (q15_t)0xA975, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA2C1, (q15_t)0xA84F, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA3D6, (q15_t)0xA72B, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4EF, (q15_t)0xA60C, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA60C, (q15_t)0xA4EF, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA72B, (q15_t)0xA3D6, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA84F, (q15_t)0xA2C1, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA975, (q15_t)0xA1AF, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA9F, (q15_t)0xA0A1, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xABCC, (q15_t)0x9F97, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACFD, (q15_t)0x9E90, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xAE31, (q15_t)0x9D8E, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF68, (q15_t)0x9C8E, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB0A1, (q15_t)0x9B93, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB1DE, (q15_t)0x9A9C, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB31E, (q15_t)0x99A8, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB461, (q15_t)0x98B9, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB5A7, (q15_t)0x97CD, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB6F0, (q15_t)0x96E6, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB83C, (q15_t)0x9602, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB98A, (q15_t)0x9523, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBADB, (q15_t)0x9447, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBC2F, (q15_t)0x9370, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD85, (q15_t)0x929D, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBEDE, (q15_t)0x91CF, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xC03A, (q15_t)0x9104, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC197, (q15_t)0x903E, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC2F8, (q15_t)0x8F7C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC45A, (q15_t)0x8EBE, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC5BF, (q15_t)0x8E05, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC727, (q15_t)0x8D50, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC890, (q15_t)0x8CA0, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9FB, (q15_t)0x8BF4, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB69, (q15_t)0x8B4D, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCCD9, (q15_t)0x8AAA, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCE4A, (q15_t)0x8A0B, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCFBE, (q15_t)0x8971, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD133, (q15_t)0x88DC, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD2AA, (q15_t)0x884B, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD423, (q15_t)0x87BF, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD59E, (q15_t)0x8738, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD71A, (q15_t)0x86B5, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD898, (q15_t)0x8637, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xDA17, (q15_t)0x85BD, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB98, (q15_t)0x8549, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDD1A, (q15_t)0x84D9, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE9E, (q15_t)0x846D, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xE023, (q15_t)0x8407, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE1A9, (q15_t)0x83A5, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE330, (q15_t)0x8348, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE4B8, (q15_t)0x82F0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE642, (q15_t)0x829D, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE7CC, (q15_t)0x824F, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE957, (q15_t)0x8205, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEAE4, (q15_t)0x81C0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC71, (q15_t)0x8180, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xEDFE, (q15_t)0x8145, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF8D, (q15_t)0x810F, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF11C, (q15_t)0x80DE, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF2AC, (q15_t)0x80B2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF43C, (q15_t)0x808A, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF5CC, (q15_t)0x8068, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF75D, (q15_t)0x804A, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF8EF, (q15_t)0x8031, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA80, (q15_t)0x801E, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFC12, (q15_t)0x800F, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFDA4, (q15_t)0x8005, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFF36, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 2048, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_2048_q15[3072] = { + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0064, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFE, (q15_t)0x012D, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01F6, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF8, (q15_t)0x02BF, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF3, (q15_t)0x0388, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FED, (q15_t)0x0451, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE5, (q15_t)0x051A, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDD, (q15_t)0x05E3, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD3, (q15_t)0x06AC, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FC8, (q15_t)0x0775, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBC, (q15_t)0x083D, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FAE, (q15_t)0x0906, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7F9F, (q15_t)0x09CE, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F8F, (q15_t)0x0A97, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F7E, (q15_t)0x0B5F, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F6B, (q15_t)0x0C27, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F58, (q15_t)0x0CEF, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F43, (q15_t)0x0DB7, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F2D, (q15_t)0x0E7F, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F15, (q15_t)0x0F47, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7EFD, (q15_t)0x100E, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE3, (q15_t)0x10D6, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7EC8, (q15_t)0x119D, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EAB, (q15_t)0x1264, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E8E, (q15_t)0x132B, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E6F, (q15_t)0x13F2, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E4F, (q15_t)0x14B8, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E2E, (q15_t)0x157F, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E0C, (q15_t)0x1645, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DE8, (q15_t)0x170A, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DC3, (q15_t)0x17D0, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7D9D, (q15_t)0x1896, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D76, (q15_t)0x195B, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D4E, (q15_t)0x1A20, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D24, (q15_t)0x1AE4, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7CF9, (q15_t)0x1BA9, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CCD, (q15_t)0x1C6D, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CA0, (q15_t)0x1D31, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C71, (q15_t)0x1DF5, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C42, (q15_t)0x1EB8, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C11, (q15_t)0x1F7B, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BDF, (q15_t)0x203E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BAC, (q15_t)0x2100, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B77, (q15_t)0x21C2, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B42, (q15_t)0x2284, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B0B, (q15_t)0x2345, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AD3, (q15_t)0x2407, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7A9A, (q15_t)0x24C7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A5F, (q15_t)0x2588, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A24, (q15_t)0x2648, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79E7, (q15_t)0x2707, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79A9, (q15_t)0x27C7, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x796A, (q15_t)0x2886, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x792A, (q15_t)0x2944, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78E8, (q15_t)0x2A02, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78A6, (q15_t)0x2AC0, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7862, (q15_t)0x2B7D, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x781D, (q15_t)0x2C3A, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77D7, (q15_t)0x2CF7, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x7790, (q15_t)0x2DB3, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x7747, (q15_t)0x2E6E, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x76FE, (q15_t)0x2F29, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76B3, (q15_t)0x2FE4, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x7668, (q15_t)0x309E, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x761B, (q15_t)0x3158, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75CC, (q15_t)0x3211, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x757D, (q15_t)0x32CA, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x752D, (q15_t)0x3382, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74DB, (q15_t)0x343A, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x7489, (q15_t)0x34F2, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x7435, (q15_t)0x35A8, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73E0, (q15_t)0x365F, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x738A, (q15_t)0x3714, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7333, (q15_t)0x37CA, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72DB, (q15_t)0x387E, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7282, (q15_t)0x3932, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x7227, (q15_t)0x39E6, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71CC, (q15_t)0x3A99, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x716F, (q15_t)0x3B4C, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7112, (q15_t)0x3BFD, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70B3, (q15_t)0x3CAF, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x7053, (q15_t)0x3D60, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x6FF2, (q15_t)0x3E10, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6F90, (q15_t)0x3EBF, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F2D, (q15_t)0x3F6E, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EC9, (q15_t)0x401D, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E63, (q15_t)0x40CA, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6DFD, (q15_t)0x4177, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6D96, (q15_t)0x4224, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D2D, (q15_t)0x42D0, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CC4, (q15_t)0x437B, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C59, (q15_t)0x4425, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6BEE, (q15_t)0x44CF, + (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B81, (q15_t)0x4578, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B13, (q15_t)0x4621, + (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AA5, (q15_t)0x46C9, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A35, (q15_t)0x4770, + (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69C4, (q15_t)0x4816, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x6953, (q15_t)0x48BC, + (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68E0, (q15_t)0x4961, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x686C, (q15_t)0x4A06, + (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x67F7, (q15_t)0x4AA9, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x6782, (q15_t)0x4B4C, + (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x670B, (q15_t)0x4BEF, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x6693, (q15_t)0x4C90, + (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x661A, (q15_t)0x4D31, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65A0, (q15_t)0x4DD1, + (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6526, (q15_t)0x4E70, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64AA, (q15_t)0x4F0F, + (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x642D, (q15_t)0x4FAC, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63B0, (q15_t)0x5049, + (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6331, (q15_t)0x50E5, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62B2, (q15_t)0x5181, + (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6231, (q15_t)0x521C, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61B0, (q15_t)0x52B5, + (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x612D, (q15_t)0x534E, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60AA, (q15_t)0x53E7, + (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6026, (q15_t)0x547E, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FA0, (q15_t)0x5515, + (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F1A, (q15_t)0x55AB, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5E93, (q15_t)0x5640, + (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E0B, (q15_t)0x56D4, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5D83, (q15_t)0x5767, + (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5CF9, (q15_t)0x57F9, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C6E, (q15_t)0x588B, + (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5BE3, (q15_t)0x591C, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B56, (q15_t)0x59AC, + (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AC9, (q15_t)0x5A3B, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A3B, (q15_t)0x5AC9, + (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59AC, (q15_t)0x5B56, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x591C, (q15_t)0x5BE3, + (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x588B, (q15_t)0x5C6E, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x57F9, (q15_t)0x5CF9, + (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x5767, (q15_t)0x5D83, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56D4, (q15_t)0x5E0B, + (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5640, (q15_t)0x5E93, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55AB, (q15_t)0x5F1A, + (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x5515, (q15_t)0x5FA0, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x547E, (q15_t)0x6026, + (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x53E7, (q15_t)0x60AA, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x534E, (q15_t)0x612D, + (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52B5, (q15_t)0x61B0, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x521C, (q15_t)0x6231, + (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x5181, (q15_t)0x62B2, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x50E5, (q15_t)0x6331, + (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5049, (q15_t)0x63B0, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FAC, (q15_t)0x642D, + (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F0F, (q15_t)0x64AA, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E70, (q15_t)0x6526, + (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DD1, (q15_t)0x65A0, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D31, (q15_t)0x661A, + (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4C90, (q15_t)0x6693, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4BEF, (q15_t)0x670B, + (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B4C, (q15_t)0x6782, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AA9, (q15_t)0x67F7, + (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A06, (q15_t)0x686C, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x4961, (q15_t)0x68E0, + (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48BC, (q15_t)0x6953, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4816, (q15_t)0x69C4, + (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x4770, (q15_t)0x6A35, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46C9, (q15_t)0x6AA5, + (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x4621, (q15_t)0x6B13, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x4578, (q15_t)0x6B81, + (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44CF, (q15_t)0x6BEE, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4425, (q15_t)0x6C59, + (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x437B, (q15_t)0x6CC4, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42D0, (q15_t)0x6D2D, + (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x4224, (q15_t)0x6D96, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x4177, (q15_t)0x6DFD, + (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40CA, (q15_t)0x6E63, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x401D, (q15_t)0x6EC9, + (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F6E, (q15_t)0x6F2D, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EBF, (q15_t)0x6F90, + (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E10, (q15_t)0x6FF2, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D60, (q15_t)0x7053, + (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CAF, (q15_t)0x70B3, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3BFD, (q15_t)0x7112, + (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B4C, (q15_t)0x716F, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3A99, (q15_t)0x71CC, + (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x39E6, (q15_t)0x7227, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x3932, (q15_t)0x7282, + (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x387E, (q15_t)0x72DB, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37CA, (q15_t)0x7333, + (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3714, (q15_t)0x738A, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x365F, (q15_t)0x73E0, + (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35A8, (q15_t)0x7435, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x34F2, (q15_t)0x7489, + (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x343A, (q15_t)0x74DB, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x3382, (q15_t)0x752D, + (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32CA, (q15_t)0x757D, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3211, (q15_t)0x75CC, + (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3158, (q15_t)0x761B, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x309E, (q15_t)0x7668, + (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x2FE4, (q15_t)0x76B3, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F29, (q15_t)0x76FE, + (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E6E, (q15_t)0x7747, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DB3, (q15_t)0x7790, + (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2CF7, (q15_t)0x77D7, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C3A, (q15_t)0x781D, + (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2B7D, (q15_t)0x7862, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AC0, (q15_t)0x78A6, + (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A02, (q15_t)0x78E8, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2944, (q15_t)0x792A, + (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x2886, (q15_t)0x796A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27C7, (q15_t)0x79A9, + (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2707, (q15_t)0x79E7, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2648, (q15_t)0x7A24, + (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x2588, (q15_t)0x7A5F, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24C7, (q15_t)0x7A9A, + (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2407, (q15_t)0x7AD3, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2345, (q15_t)0x7B0B, + (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x2284, (q15_t)0x7B42, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21C2, (q15_t)0x7B77, + (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2100, (q15_t)0x7BAC, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x203E, (q15_t)0x7BDF, + (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1F7B, (q15_t)0x7C11, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EB8, (q15_t)0x7C42, + (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1DF5, (q15_t)0x7C71, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D31, (q15_t)0x7CA0, + (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C6D, (q15_t)0x7CCD, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BA9, (q15_t)0x7CF9, + (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1AE4, (q15_t)0x7D24, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A20, (q15_t)0x7D4E, + (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x195B, (q15_t)0x7D76, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x1896, (q15_t)0x7D9D, + (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x17D0, (q15_t)0x7DC3, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x170A, (q15_t)0x7DE8, + (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1645, (q15_t)0x7E0C, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x157F, (q15_t)0x7E2E, + (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14B8, (q15_t)0x7E4F, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x13F2, (q15_t)0x7E6F, + (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x132B, (q15_t)0x7E8E, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1264, (q15_t)0x7EAB, + (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x119D, (q15_t)0x7EC8, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x10D6, (q15_t)0x7EE3, + (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x100E, (q15_t)0x7EFD, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F47, (q15_t)0x7F15, + (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0E7F, (q15_t)0x7F2D, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DB7, (q15_t)0x7F43, + (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0CEF, (q15_t)0x7F58, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C27, (q15_t)0x7F6B, + (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B5F, (q15_t)0x7F7E, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0A97, (q15_t)0x7F8F, + (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x09CE, (q15_t)0x7F9F, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0906, (q15_t)0x7FAE, + (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x083D, (q15_t)0x7FBC, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x0775, (q15_t)0x7FC8, + (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06AC, (q15_t)0x7FD3, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x05E3, (q15_t)0x7FDD, + (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x051A, (q15_t)0x7FE5, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0451, (q15_t)0x7FED, + (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x0388, (q15_t)0x7FF3, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02BF, (q15_t)0x7FF8, + (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x01F6, (q15_t)0x7FFC, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x012D, (q15_t)0x7FFE, + (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFF9B, (q15_t)0x7FFF, + (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFED2, (q15_t)0x7FFE, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE09, (q15_t)0x7FFC, + (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD40, (q15_t)0x7FF8, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFC77, (q15_t)0x7FF3, + (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBAE, (q15_t)0x7FED, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFAE5, (q15_t)0x7FE5, + (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA1C, (q15_t)0x7FDD, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF953, (q15_t)0x7FD3, + (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF88A, (q15_t)0x7FC8, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7C2, (q15_t)0x7FBC, + (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF6F9, (q15_t)0x7FAE, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF631, (q15_t)0x7F9F, + (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF568, (q15_t)0x7F8F, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4A0, (q15_t)0x7F7E, + (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF3D8, (q15_t)0x7F6B, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF310, (q15_t)0x7F58, + (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF248, (q15_t)0x7F43, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF180, (q15_t)0x7F2D, + (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0B8, (q15_t)0x7F15, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xEFF1, (q15_t)0x7EFD, + (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF29, (q15_t)0x7EE3, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE62, (q15_t)0x7EC8, + (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xED9B, (q15_t)0x7EAB, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xECD4, (q15_t)0x7E8E, + (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC0D, (q15_t)0x7E6F, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB47, (q15_t)0x7E4F, + (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEA80, (q15_t)0x7E2E, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9BA, (q15_t)0x7E0C, + (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE8F5, (q15_t)0x7DE8, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE82F, (q15_t)0x7DC3, + (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE769, (q15_t)0x7D9D, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6A4, (q15_t)0x7D76, + (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE5DF, (q15_t)0x7D4E, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE51B, (q15_t)0x7D24, + (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE456, (q15_t)0x7CF9, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE392, (q15_t)0x7CCD, + (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2CE, (q15_t)0x7CA0, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE20A, (q15_t)0x7C71, + (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE147, (q15_t)0x7C42, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE084, (q15_t)0x7C11, + (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFC1, (q15_t)0x7BDF, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDEFF, (q15_t)0x7BAC, + (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE3D, (q15_t)0x7B77, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDD7B, (q15_t)0x7B42, + (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCBA, (q15_t)0x7B0B, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDBF8, (q15_t)0x7AD3, + (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB38, (q15_t)0x7A9A, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDA77, (q15_t)0x7A5F, + (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9B7, (q15_t)0x7A24, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD8F8, (q15_t)0x79E7, + (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD838, (q15_t)0x79A9, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD779, (q15_t)0x796A, + (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6BB, (q15_t)0x792A, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD5FD, (q15_t)0x78E8, + (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD53F, (q15_t)0x78A6, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD482, (q15_t)0x7862, + (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3C5, (q15_t)0x781D, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD308, (q15_t)0x77D7, + (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD24C, (q15_t)0x7790, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD191, (q15_t)0x7747, + (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD0D6, (q15_t)0x76FE, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD01B, (q15_t)0x76B3, + (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF61, (q15_t)0x7668, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCEA7, (q15_t)0x761B, + (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCDEE, (q15_t)0x75CC, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD35, (q15_t)0x757D, + (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCC7D, (q15_t)0x752D, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBC5, (q15_t)0x74DB, + (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB0D, (q15_t)0x7489, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA57, (q15_t)0x7435, + (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9A0, (q15_t)0x73E0, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC8EB, (q15_t)0x738A, + (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC835, (q15_t)0x7333, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC781, (q15_t)0x72DB, + (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6CD, (q15_t)0x7282, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC619, (q15_t)0x7227, + (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC566, (q15_t)0x71CC, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4B3, (q15_t)0x716F, + (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC402, (q15_t)0x7112, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC350, (q15_t)0x70B3, + (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC29F, (q15_t)0x7053, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC1EF, (q15_t)0x6FF2, + (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC140, (q15_t)0x6F90, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC091, (q15_t)0x6F2D, + (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xBFE2, (q15_t)0x6EC9, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF35, (q15_t)0x6E63, + (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBE88, (q15_t)0x6DFD, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBDDB, (q15_t)0x6D96, + (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD2F, (q15_t)0x6D2D, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBC84, (q15_t)0x6CC4, + (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBBDA, (q15_t)0x6C59, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB30, (q15_t)0x6BEE, + (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBA87, (q15_t)0x6B81, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xB9DE, (q15_t)0x6B13, + (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB936, (q15_t)0x6AA5, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB88F, (q15_t)0x6A35, + (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB7E9, (q15_t)0x69C4, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB743, (q15_t)0x6953, + (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB69E, (q15_t)0x68E0, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB5F9, (q15_t)0x686C, + (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB556, (q15_t)0x67F7, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4B3, (q15_t)0x6782, + (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB410, (q15_t)0x670B, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB36F, (q15_t)0x6693, + (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2CE, (q15_t)0x661A, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB22E, (q15_t)0x65A0, + (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB18F, (q15_t)0x6526, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB0F0, (q15_t)0x64AA, + (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB053, (q15_t)0x642D, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFB6, (q15_t)0x63B0, + (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF1A, (q15_t)0x6331, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAE7E, (q15_t)0x62B2, + (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xADE3, (q15_t)0x6231, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD4A, (q15_t)0x61B0, + (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACB1, (q15_t)0x612D, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC18, (q15_t)0x60AA, + (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xAB81, (q15_t)0x6026, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAAEA, (q15_t)0x5FA0, + (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA54, (q15_t)0x5F1A, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9BF, (q15_t)0x5E93, + (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA92B, (q15_t)0x5E0B, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA898, (q15_t)0x5D83, + (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA806, (q15_t)0x5CF9, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA774, (q15_t)0x5C6E, + (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA6E3, (q15_t)0x5BE3, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA653, (q15_t)0x5B56, + (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5C4, (q15_t)0x5AC9, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA536, (q15_t)0x5A3B, + (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4A9, (q15_t)0x59AC, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA41C, (q15_t)0x591C, + (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA391, (q15_t)0x588B, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA306, (q15_t)0x57F9, + (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA27C, (q15_t)0x5767, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA1F4, (q15_t)0x56D4, + (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA16C, (q15_t)0x5640, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA0E5, (q15_t)0x55AB, + (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA05F, (q15_t)0x5515, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FD9, (q15_t)0x547E, + (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F55, (q15_t)0x53E7, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9ED2, (q15_t)0x534E, + (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E4F, (q15_t)0x52B5, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DCE, (q15_t)0x521C, + (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D4D, (q15_t)0x5181, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CCE, (q15_t)0x50E5, + (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C4F, (q15_t)0x5049, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BD2, (q15_t)0x4FAC, + (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B55, (q15_t)0x4F0F, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AD9, (q15_t)0x4E70, + (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A5F, (q15_t)0x4DD1, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x99E5, (q15_t)0x4D31, + (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x996C, (q15_t)0x4C90, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x98F4, (q15_t)0x4BEF, + (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x987D, (q15_t)0x4B4C, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9808, (q15_t)0x4AA9, + (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x9793, (q15_t)0x4A06, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x971F, (q15_t)0x4961, + (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96AC, (q15_t)0x48BC, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x963B, (q15_t)0x4816, + (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95CA, (q15_t)0x4770, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x955A, (q15_t)0x46C9, + (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x94EC, (q15_t)0x4621, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x947E, (q15_t)0x4578, + (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x9411, (q15_t)0x44CF, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93A6, (q15_t)0x4425, + (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x933B, (q15_t)0x437B, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92D2, (q15_t)0x42D0, + (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9269, (q15_t)0x4224, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x9202, (q15_t)0x4177, + (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x919C, (q15_t)0x40CA, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9136, (q15_t)0x401D, + (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90D2, (q15_t)0x3F6E, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x906F, (q15_t)0x3EBF, + (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x900D, (q15_t)0x3E10, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FAC, (q15_t)0x3D60, + (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F4C, (q15_t)0x3CAF, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8EED, (q15_t)0x3BFD, + (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8E90, (q15_t)0x3B4C, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E33, (q15_t)0x3A99, + (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DD8, (q15_t)0x39E6, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D7D, (q15_t)0x3932, + (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D24, (q15_t)0x387E, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CCC, (q15_t)0x37CA, + (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C75, (q15_t)0x3714, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C1F, (q15_t)0x365F, + (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BCA, (q15_t)0x35A8, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B76, (q15_t)0x34F2, + (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B24, (q15_t)0x343A, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AD2, (q15_t)0x3382, + (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A82, (q15_t)0x32CA, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A33, (q15_t)0x3211, + (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89E4, (q15_t)0x3158, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x8997, (q15_t)0x309E, + (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x894C, (q15_t)0x2FE4, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8901, (q15_t)0x2F29, + (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88B8, (q15_t)0x2E6E, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x886F, (q15_t)0x2DB3, + (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x8828, (q15_t)0x2CF7, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87E2, (q15_t)0x2C3A, + (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x879D, (q15_t)0x2B7D, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x8759, (q15_t)0x2AC0, + (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8717, (q15_t)0x2A02, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86D5, (q15_t)0x2944, + (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x8695, (q15_t)0x2886, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8656, (q15_t)0x27C7, + (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8618, (q15_t)0x2707, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85DB, (q15_t)0x2648, + (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85A0, (q15_t)0x2588, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8565, (q15_t)0x24C7, + (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x852C, (q15_t)0x2407, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x84F4, (q15_t)0x2345, + (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84BD, (q15_t)0x2284, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8488, (q15_t)0x21C2, + (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8453, (q15_t)0x2100, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x8420, (q15_t)0x203E, + (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83EE, (q15_t)0x1F7B, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83BD, (q15_t)0x1EB8, + (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x838E, (q15_t)0x1DF5, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x835F, (q15_t)0x1D31, + (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x8332, (q15_t)0x1C6D, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8306, (q15_t)0x1BA9, + (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82DB, (q15_t)0x1AE4, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82B1, (q15_t)0x1A20, + (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8289, (q15_t)0x195B, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x8262, (q15_t)0x1896, + (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x823C, (q15_t)0x17D0, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8217, (q15_t)0x170A, + (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81F3, (q15_t)0x1645, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D1, (q15_t)0x157F, + (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B0, (q15_t)0x14B8, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8190, (q15_t)0x13F2, + (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8171, (q15_t)0x132B, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x8154, (q15_t)0x1264, + (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x8137, (q15_t)0x119D, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x811C, (q15_t)0x10D6, + (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8102, (q15_t)0x100E, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80EA, (q15_t)0x0F47, + (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D2, (q15_t)0x0E7F, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80BC, (q15_t)0x0DB7, + (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80A7, (q15_t)0x0CEF, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8094, (q15_t)0x0C27, + (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8081, (q15_t)0x0B5F, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8070, (q15_t)0x0A97, + (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8060, (q15_t)0x09CE, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8051, (q15_t)0x0906, + (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8043, (q15_t)0x083D, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x8037, (q15_t)0x0775, + (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802C, (q15_t)0x06AC, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8022, (q15_t)0x05E3, + (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801A, (q15_t)0x051A, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8012, (q15_t)0x0451, + (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800C, (q15_t)0x0388, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8007, (q15_t)0x02BF, + (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8003, (q15_t)0x01F6, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x012D, + (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0064, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFF9B, + (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8001, (q15_t)0xFED2, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE09, + (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8007, (q15_t)0xFD40, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800C, (q15_t)0xFC77, + (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8012, (q15_t)0xFBAE, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x801A, (q15_t)0xFAE5, + (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8022, (q15_t)0xFA1C, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x802C, (q15_t)0xF953, + (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8037, (q15_t)0xF88A, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8043, (q15_t)0xF7C2, + (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x8051, (q15_t)0xF6F9, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x8060, (q15_t)0xF631, + (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x8070, (q15_t)0xF568, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x8081, (q15_t)0xF4A0, + (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x8094, (q15_t)0xF3D8, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A7, (q15_t)0xF310, + (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80BC, (q15_t)0xF248, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80D2, (q15_t)0xF180, + (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80EA, (q15_t)0xF0B8, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x8102, (q15_t)0xEFF1, + (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x811C, (q15_t)0xEF29, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8137, (q15_t)0xEE62, + (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x8154, (q15_t)0xED9B, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x8171, (q15_t)0xECD4, + (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8190, (q15_t)0xEC0D, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81B0, (q15_t)0xEB47, + (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81D1, (q15_t)0xEA80, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81F3, (q15_t)0xE9BA, + (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x8217, (q15_t)0xE8F5, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x823C, (q15_t)0xE82F, + (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8262, (q15_t)0xE769, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x8289, (q15_t)0xE6A4, + (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82B1, (q15_t)0xE5DF, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82DB, (q15_t)0xE51B, + (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x8306, (q15_t)0xE456, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8332, (q15_t)0xE392, + (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x835F, (q15_t)0xE2CE, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x838E, (q15_t)0xE20A, + (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83BD, (q15_t)0xE147, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83EE, (q15_t)0xE084, + (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8420, (q15_t)0xDFC1, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8453, (q15_t)0xDEFF, + (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x8488, (q15_t)0xDE3D, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84BD, (q15_t)0xDD7B, + (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84F4, (q15_t)0xDCBA, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x852C, (q15_t)0xDBF8, + (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8565, (q15_t)0xDB38, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x85A0, (q15_t)0xDA77, + (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85DB, (q15_t)0xD9B7, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8618, (q15_t)0xD8F8, + (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8656, (q15_t)0xD838, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8695, (q15_t)0xD779, + (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86D5, (q15_t)0xD6BB, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8717, (q15_t)0xD5FD, + (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8759, (q15_t)0xD53F, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x879D, (q15_t)0xD482, + (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87E2, (q15_t)0xD3C5, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8828, (q15_t)0xD308, + (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x886F, (q15_t)0xD24C, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88B8, (q15_t)0xD191, + (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x8901, (q15_t)0xD0D6, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x894C, (q15_t)0xD01B, + (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8997, (q15_t)0xCF61, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89E4, (q15_t)0xCEA7, + (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A33, (q15_t)0xCDEE, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A82, (q15_t)0xCD35, + (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8AD2, (q15_t)0xCC7D, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B24, (q15_t)0xCBC5, + (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B76, (q15_t)0xCB0D, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BCA, (q15_t)0xCA57, + (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C1F, (q15_t)0xC9A0, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C75, (q15_t)0xC8EB, + (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CCC, (q15_t)0xC835, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D24, (q15_t)0xC781, + (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D7D, (q15_t)0xC6CD, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DD8, (q15_t)0xC619, + (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E33, (q15_t)0xC566, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E90, (q15_t)0xC4B3, + (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8EED, (q15_t)0xC402, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F4C, (q15_t)0xC350, + (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8FAC, (q15_t)0xC29F, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x900D, (q15_t)0xC1EF, + (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x906F, (q15_t)0xC140, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90D2, (q15_t)0xC091, + (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x9136, (q15_t)0xBFE2, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x919C, (q15_t)0xBF35, + (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x9202, (q15_t)0xBE88, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x9269, (q15_t)0xBDDB, + (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92D2, (q15_t)0xBD2F, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x933B, (q15_t)0xBC84, + (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x93A6, (q15_t)0xBBDA, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x9411, (q15_t)0xBB30, + (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x947E, (q15_t)0xBA87, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94EC, (q15_t)0xB9DE, + (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x955A, (q15_t)0xB936, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95CA, (q15_t)0xB88F, + (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x963B, (q15_t)0xB7E9, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x96AC, (q15_t)0xB743, + (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x971F, (q15_t)0xB69E, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9793, (q15_t)0xB5F9, + (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x9808, (q15_t)0xB556, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x987D, (q15_t)0xB4B3, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98F4, (q15_t)0xB410, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x996C, (q15_t)0xB36F, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99E5, (q15_t)0xB2CE, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A5F, (q15_t)0xB22E, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9AD9, (q15_t)0xB18F, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B55, (q15_t)0xB0F0, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BD2, (q15_t)0xB053, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C4F, (q15_t)0xAFB6, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CCE, (q15_t)0xAF1A, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D4D, (q15_t)0xAE7E, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DCE, (q15_t)0xADE3, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E4F, (q15_t)0xAD4A, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9ED2, (q15_t)0xACB1, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F55, (q15_t)0xAC18, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FD9, (q15_t)0xAB81, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA05F, (q15_t)0xAAEA, + (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0E5, (q15_t)0xAA54, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA16C, (q15_t)0xA9BF, + (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1F4, (q15_t)0xA92B, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA27C, (q15_t)0xA898, + (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA306, (q15_t)0xA806, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA391, (q15_t)0xA774, + (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA41C, (q15_t)0xA6E3, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA4A9, (q15_t)0xA653, + (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA536, (q15_t)0xA5C4, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5C4, (q15_t)0xA536, + (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA653, (q15_t)0xA4A9, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6E3, (q15_t)0xA41C, + (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA774, (q15_t)0xA391, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA806, (q15_t)0xA306, + (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA898, (q15_t)0xA27C, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA92B, (q15_t)0xA1F4, + (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA9BF, (q15_t)0xA16C, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA54, (q15_t)0xA0E5, + (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAEA, (q15_t)0xA05F, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB81, (q15_t)0x9FD9, + (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xAC18, (q15_t)0x9F55, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xACB1, (q15_t)0x9ED2, + (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD4A, (q15_t)0x9E4F, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADE3, (q15_t)0x9DCE, + (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE7E, (q15_t)0x9D4D, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAF1A, (q15_t)0x9CCE, + (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAFB6, (q15_t)0x9C4F, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB053, (q15_t)0x9BD2, + (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0F0, (q15_t)0x9B55, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB18F, (q15_t)0x9AD9, + (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB22E, (q15_t)0x9A5F, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2CE, (q15_t)0x99E5, + (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB36F, (q15_t)0x996C, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB410, (q15_t)0x98F4, + (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB4B3, (q15_t)0x987D, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB556, (q15_t)0x9808, + (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5F9, (q15_t)0x9793, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB69E, (q15_t)0x971F, + (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB743, (q15_t)0x96AC, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7E9, (q15_t)0x963B, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB88F, (q15_t)0x95CA, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB936, (q15_t)0x955A, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9DE, (q15_t)0x94EC, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA87, (q15_t)0x947E, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB30, (q15_t)0x9411, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBDA, (q15_t)0x93A6, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC84, (q15_t)0x933B, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD2F, (q15_t)0x92D2, + (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDDB, (q15_t)0x9269, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE88, (q15_t)0x9202, + (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF35, (q15_t)0x919C, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFE2, (q15_t)0x9136, + (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC091, (q15_t)0x90D2, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC140, (q15_t)0x906F, + (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1EF, (q15_t)0x900D, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC29F, (q15_t)0x8FAC, + (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC350, (q15_t)0x8F4C, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC402, (q15_t)0x8EED, + (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC4B3, (q15_t)0x8E90, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC566, (q15_t)0x8E33, + (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC619, (q15_t)0x8DD8, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6CD, (q15_t)0x8D7D, + (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC781, (q15_t)0x8D24, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC835, (q15_t)0x8CCC, + (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8EB, (q15_t)0x8C75, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC9A0, (q15_t)0x8C1F, + (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA57, (q15_t)0x8BCA, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCB0D, (q15_t)0x8B76, + (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCBC5, (q15_t)0x8B24, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC7D, (q15_t)0x8AD2, + (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD35, (q15_t)0x8A82, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDEE, (q15_t)0x8A33, + (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCEA7, (q15_t)0x89E4, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF61, (q15_t)0x8997, + (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xD01B, (q15_t)0x894C, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0D6, (q15_t)0x8901, + (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD191, (q15_t)0x88B8, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD24C, (q15_t)0x886F, + (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD308, (q15_t)0x8828, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD3C5, (q15_t)0x87E2, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD482, (q15_t)0x879D, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD53F, (q15_t)0x8759, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5FD, (q15_t)0x8717, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD6BB, (q15_t)0x86D5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD779, (q15_t)0x8695, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD838, (q15_t)0x8656, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8F8, (q15_t)0x8618, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD9B7, (q15_t)0x85DB, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA77, (q15_t)0x85A0, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB38, (q15_t)0x8565, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBF8, (q15_t)0x852C, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDCBA, (q15_t)0x84F4, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD7B, (q15_t)0x84BD, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE3D, (q15_t)0x8488, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDEFF, (q15_t)0x8453, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDFC1, (q15_t)0x8420, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE084, (q15_t)0x83EE, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE147, (q15_t)0x83BD, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE20A, (q15_t)0x838E, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE2CE, (q15_t)0x835F, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE392, (q15_t)0x8332, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE456, (q15_t)0x8306, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE51B, (q15_t)0x82DB, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5DF, (q15_t)0x82B1, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE6A4, (q15_t)0x8289, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE769, (q15_t)0x8262, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE82F, (q15_t)0x823C, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8F5, (q15_t)0x8217, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE9BA, (q15_t)0x81F3, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA80, (q15_t)0x81D1, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB47, (q15_t)0x81B0, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEC0D, (q15_t)0x8190, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECD4, (q15_t)0x8171, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED9B, (q15_t)0x8154, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE62, (q15_t)0x8137, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEF29, (q15_t)0x811C, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFF1, (q15_t)0x8102, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF0B8, (q15_t)0x80EA, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF180, (q15_t)0x80D2, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF248, (q15_t)0x80BC, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF310, (q15_t)0x80A7, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3D8, (q15_t)0x8094, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF4A0, (q15_t)0x8081, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF568, (q15_t)0x8070, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF631, (q15_t)0x8060, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6F9, (q15_t)0x8051, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF7C2, (q15_t)0x8043, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF88A, (q15_t)0x8037, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF953, (q15_t)0x802C, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xFA1C, (q15_t)0x8022, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAE5, (q15_t)0x801A, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFBAE, (q15_t)0x8012, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC77, (q15_t)0x800C, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD40, (q15_t)0x8007, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFE09, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFED2, (q15_t)0x8001, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) +/** + @par + Example code for q15 Twiddle factors Generation:: + @par + 
for (i = 0; i< 3N/4; i++)
+  {
+     twiddleCoefq15[2*i]   = cos(i * 2*PI/(float)N);
+     twiddleCoefq15[2*i+1] = sin(i * 2*PI/(float)N);
+  }
+ @par + where N = 4096, PI = 3.14159265358979 + @par + Cos and Sin values are interleaved fashion + @par + Convert Floating point to q15(Fixed point 1.15): + round(twiddleCoefq15(i) * pow(2, 15)) + */ +const q15_t twiddleCoef_4096_q15[6144] = +{ + (q15_t)0x7FFF, (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0x0032, + (q15_t)0x7FFF, (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0096, + (q15_t)0x7FFF, (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x00FB, + (q15_t)0x7FFE, (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x015F, + (q15_t)0x7FFD, (q15_t)0x0192, (q15_t)0x7FFC, (q15_t)0x01C4, + (q15_t)0x7FFC, (q15_t)0x01F6, (q15_t)0x7FFB, (q15_t)0x0228, + (q15_t)0x7FFA, (q15_t)0x025B, (q15_t)0x7FF9, (q15_t)0x028D, + (q15_t)0x7FF8, (q15_t)0x02BF, (q15_t)0x7FF7, (q15_t)0x02F1, + (q15_t)0x7FF6, (q15_t)0x0324, (q15_t)0x7FF4, (q15_t)0x0356, + (q15_t)0x7FF3, (q15_t)0x0388, (q15_t)0x7FF2, (q15_t)0x03BA, + (q15_t)0x7FF0, (q15_t)0x03ED, (q15_t)0x7FEE, (q15_t)0x041F, + (q15_t)0x7FED, (q15_t)0x0451, (q15_t)0x7FEB, (q15_t)0x0483, + (q15_t)0x7FE9, (q15_t)0x04B6, (q15_t)0x7FE7, (q15_t)0x04E8, + (q15_t)0x7FE5, (q15_t)0x051A, (q15_t)0x7FE3, (q15_t)0x054C, + (q15_t)0x7FE1, (q15_t)0x057F, (q15_t)0x7FDF, (q15_t)0x05B1, + (q15_t)0x7FDD, (q15_t)0x05E3, (q15_t)0x7FDA, (q15_t)0x0615, + (q15_t)0x7FD8, (q15_t)0x0647, (q15_t)0x7FD6, (q15_t)0x067A, + (q15_t)0x7FD3, (q15_t)0x06AC, (q15_t)0x7FD0, (q15_t)0x06DE, + (q15_t)0x7FCE, (q15_t)0x0710, (q15_t)0x7FCB, (q15_t)0x0742, + (q15_t)0x7FC8, (q15_t)0x0775, (q15_t)0x7FC5, (q15_t)0x07A7, + (q15_t)0x7FC2, (q15_t)0x07D9, (q15_t)0x7FBF, (q15_t)0x080B, + (q15_t)0x7FBC, (q15_t)0x083D, (q15_t)0x7FB8, (q15_t)0x086F, + (q15_t)0x7FB5, (q15_t)0x08A2, (q15_t)0x7FB1, (q15_t)0x08D4, + (q15_t)0x7FAE, (q15_t)0x0906, (q15_t)0x7FAA, (q15_t)0x0938, + (q15_t)0x7FA7, (q15_t)0x096A, (q15_t)0x7FA3, (q15_t)0x099C, + (q15_t)0x7F9F, (q15_t)0x09CE, (q15_t)0x7F9B, (q15_t)0x0A00, + (q15_t)0x7F97, (q15_t)0x0A33, (q15_t)0x7F93, (q15_t)0x0A65, + (q15_t)0x7F8F, (q15_t)0x0A97, (q15_t)0x7F8B, (q15_t)0x0AC9, + (q15_t)0x7F87, (q15_t)0x0AFB, (q15_t)0x7F82, (q15_t)0x0B2D, + (q15_t)0x7F7E, (q15_t)0x0B5F, (q15_t)0x7F79, (q15_t)0x0B91, + (q15_t)0x7F75, (q15_t)0x0BC3, (q15_t)0x7F70, (q15_t)0x0BF5, + (q15_t)0x7F6B, (q15_t)0x0C27, (q15_t)0x7F67, (q15_t)0x0C59, + (q15_t)0x7F62, (q15_t)0x0C8B, (q15_t)0x7F5D, (q15_t)0x0CBD, + (q15_t)0x7F58, (q15_t)0x0CEF, (q15_t)0x7F53, (q15_t)0x0D21, + (q15_t)0x7F4D, (q15_t)0x0D53, (q15_t)0x7F48, (q15_t)0x0D85, + (q15_t)0x7F43, (q15_t)0x0DB7, (q15_t)0x7F3D, (q15_t)0x0DE9, + (q15_t)0x7F38, (q15_t)0x0E1B, (q15_t)0x7F32, (q15_t)0x0E4D, + (q15_t)0x7F2D, (q15_t)0x0E7F, (q15_t)0x7F27, (q15_t)0x0EB1, + (q15_t)0x7F21, (q15_t)0x0EE3, (q15_t)0x7F1B, (q15_t)0x0F15, + (q15_t)0x7F15, (q15_t)0x0F47, (q15_t)0x7F0F, (q15_t)0x0F79, + (q15_t)0x7F09, (q15_t)0x0FAB, (q15_t)0x7F03, (q15_t)0x0FDD, + (q15_t)0x7EFD, (q15_t)0x100E, (q15_t)0x7EF6, (q15_t)0x1040, + (q15_t)0x7EF0, (q15_t)0x1072, (q15_t)0x7EE9, (q15_t)0x10A4, + (q15_t)0x7EE3, (q15_t)0x10D6, (q15_t)0x7EDC, (q15_t)0x1108, + (q15_t)0x7ED5, (q15_t)0x1139, (q15_t)0x7ECF, (q15_t)0x116B, + (q15_t)0x7EC8, (q15_t)0x119D, (q15_t)0x7EC1, (q15_t)0x11CF, + (q15_t)0x7EBA, (q15_t)0x1201, (q15_t)0x7EB3, (q15_t)0x1232, + (q15_t)0x7EAB, (q15_t)0x1264, (q15_t)0x7EA4, (q15_t)0x1296, + (q15_t)0x7E9D, (q15_t)0x12C8, (q15_t)0x7E95, (q15_t)0x12F9, + (q15_t)0x7E8E, (q15_t)0x132B, (q15_t)0x7E86, (q15_t)0x135D, + (q15_t)0x7E7F, (q15_t)0x138E, (q15_t)0x7E77, (q15_t)0x13C0, + (q15_t)0x7E6F, (q15_t)0x13F2, (q15_t)0x7E67, (q15_t)0x1423, + (q15_t)0x7E5F, (q15_t)0x1455, (q15_t)0x7E57, (q15_t)0x1487, + (q15_t)0x7E4F, (q15_t)0x14B8, (q15_t)0x7E47, (q15_t)0x14EA, + (q15_t)0x7E3F, (q15_t)0x151B, (q15_t)0x7E37, (q15_t)0x154D, + (q15_t)0x7E2E, (q15_t)0x157F, (q15_t)0x7E26, (q15_t)0x15B0, + (q15_t)0x7E1D, (q15_t)0x15E2, (q15_t)0x7E14, (q15_t)0x1613, + (q15_t)0x7E0C, (q15_t)0x1645, (q15_t)0x7E03, (q15_t)0x1676, + (q15_t)0x7DFA, (q15_t)0x16A8, (q15_t)0x7DF1, (q15_t)0x16D9, + (q15_t)0x7DE8, (q15_t)0x170A, (q15_t)0x7DDF, (q15_t)0x173C, + (q15_t)0x7DD6, (q15_t)0x176D, (q15_t)0x7DCD, (q15_t)0x179F, + (q15_t)0x7DC3, (q15_t)0x17D0, (q15_t)0x7DBA, (q15_t)0x1802, + (q15_t)0x7DB0, (q15_t)0x1833, (q15_t)0x7DA7, (q15_t)0x1864, + (q15_t)0x7D9D, (q15_t)0x1896, (q15_t)0x7D94, (q15_t)0x18C7, + (q15_t)0x7D8A, (q15_t)0x18F8, (q15_t)0x7D80, (q15_t)0x192A, + (q15_t)0x7D76, (q15_t)0x195B, (q15_t)0x7D6C, (q15_t)0x198C, + (q15_t)0x7D62, (q15_t)0x19BD, (q15_t)0x7D58, (q15_t)0x19EF, + (q15_t)0x7D4E, (q15_t)0x1A20, (q15_t)0x7D43, (q15_t)0x1A51, + (q15_t)0x7D39, (q15_t)0x1A82, (q15_t)0x7D2F, (q15_t)0x1AB3, + (q15_t)0x7D24, (q15_t)0x1AE4, (q15_t)0x7D19, (q15_t)0x1B16, + (q15_t)0x7D0F, (q15_t)0x1B47, (q15_t)0x7D04, (q15_t)0x1B78, + (q15_t)0x7CF9, (q15_t)0x1BA9, (q15_t)0x7CEE, (q15_t)0x1BDA, + (q15_t)0x7CE3, (q15_t)0x1C0B, (q15_t)0x7CD8, (q15_t)0x1C3C, + (q15_t)0x7CCD, (q15_t)0x1C6D, (q15_t)0x7CC2, (q15_t)0x1C9E, + (q15_t)0x7CB7, (q15_t)0x1CCF, (q15_t)0x7CAB, (q15_t)0x1D00, + (q15_t)0x7CA0, (q15_t)0x1D31, (q15_t)0x7C94, (q15_t)0x1D62, + (q15_t)0x7C89, (q15_t)0x1D93, (q15_t)0x7C7D, (q15_t)0x1DC4, + (q15_t)0x7C71, (q15_t)0x1DF5, (q15_t)0x7C66, (q15_t)0x1E25, + (q15_t)0x7C5A, (q15_t)0x1E56, (q15_t)0x7C4E, (q15_t)0x1E87, + (q15_t)0x7C42, (q15_t)0x1EB8, (q15_t)0x7C36, (q15_t)0x1EE9, + (q15_t)0x7C29, (q15_t)0x1F19, (q15_t)0x7C1D, (q15_t)0x1F4A, + (q15_t)0x7C11, (q15_t)0x1F7B, (q15_t)0x7C05, (q15_t)0x1FAC, + (q15_t)0x7BF8, (q15_t)0x1FDC, (q15_t)0x7BEB, (q15_t)0x200D, + (q15_t)0x7BDF, (q15_t)0x203E, (q15_t)0x7BD2, (q15_t)0x206E, + (q15_t)0x7BC5, (q15_t)0x209F, (q15_t)0x7BB9, (q15_t)0x20D0, + (q15_t)0x7BAC, (q15_t)0x2100, (q15_t)0x7B9F, (q15_t)0x2131, + (q15_t)0x7B92, (q15_t)0x2161, (q15_t)0x7B84, (q15_t)0x2192, + (q15_t)0x7B77, (q15_t)0x21C2, (q15_t)0x7B6A, (q15_t)0x21F3, + (q15_t)0x7B5D, (q15_t)0x2223, (q15_t)0x7B4F, (q15_t)0x2254, + (q15_t)0x7B42, (q15_t)0x2284, (q15_t)0x7B34, (q15_t)0x22B4, + (q15_t)0x7B26, (q15_t)0x22E5, (q15_t)0x7B19, (q15_t)0x2315, + (q15_t)0x7B0B, (q15_t)0x2345, (q15_t)0x7AFD, (q15_t)0x2376, + (q15_t)0x7AEF, (q15_t)0x23A6, (q15_t)0x7AE1, (q15_t)0x23D6, + (q15_t)0x7AD3, (q15_t)0x2407, (q15_t)0x7AC5, (q15_t)0x2437, + (q15_t)0x7AB6, (q15_t)0x2467, (q15_t)0x7AA8, (q15_t)0x2497, + (q15_t)0x7A9A, (q15_t)0x24C7, (q15_t)0x7A8B, (q15_t)0x24F7, + (q15_t)0x7A7D, (q15_t)0x2528, (q15_t)0x7A6E, (q15_t)0x2558, + (q15_t)0x7A5F, (q15_t)0x2588, (q15_t)0x7A50, (q15_t)0x25B8, + (q15_t)0x7A42, (q15_t)0x25E8, (q15_t)0x7A33, (q15_t)0x2618, + (q15_t)0x7A24, (q15_t)0x2648, (q15_t)0x7A15, (q15_t)0x2678, + (q15_t)0x7A05, (q15_t)0x26A8, (q15_t)0x79F6, (q15_t)0x26D8, + (q15_t)0x79E7, (q15_t)0x2707, (q15_t)0x79D8, (q15_t)0x2737, + (q15_t)0x79C8, (q15_t)0x2767, (q15_t)0x79B9, (q15_t)0x2797, + (q15_t)0x79A9, (q15_t)0x27C7, (q15_t)0x7999, (q15_t)0x27F6, + (q15_t)0x798A, (q15_t)0x2826, (q15_t)0x797A, (q15_t)0x2856, + (q15_t)0x796A, (q15_t)0x2886, (q15_t)0x795A, (q15_t)0x28B5, + (q15_t)0x794A, (q15_t)0x28E5, (q15_t)0x793A, (q15_t)0x2915, + (q15_t)0x792A, (q15_t)0x2944, (q15_t)0x7919, (q15_t)0x2974, + (q15_t)0x7909, (q15_t)0x29A3, (q15_t)0x78F9, (q15_t)0x29D3, + (q15_t)0x78E8, (q15_t)0x2A02, (q15_t)0x78D8, (q15_t)0x2A32, + (q15_t)0x78C7, (q15_t)0x2A61, (q15_t)0x78B6, (q15_t)0x2A91, + (q15_t)0x78A6, (q15_t)0x2AC0, (q15_t)0x7895, (q15_t)0x2AEF, + (q15_t)0x7884, (q15_t)0x2B1F, (q15_t)0x7873, (q15_t)0x2B4E, + (q15_t)0x7862, (q15_t)0x2B7D, (q15_t)0x7851, (q15_t)0x2BAD, + (q15_t)0x7840, (q15_t)0x2BDC, (q15_t)0x782E, (q15_t)0x2C0B, + (q15_t)0x781D, (q15_t)0x2C3A, (q15_t)0x780C, (q15_t)0x2C69, + (q15_t)0x77FA, (q15_t)0x2C98, (q15_t)0x77E9, (q15_t)0x2CC8, + (q15_t)0x77D7, (q15_t)0x2CF7, (q15_t)0x77C5, (q15_t)0x2D26, + (q15_t)0x77B4, (q15_t)0x2D55, (q15_t)0x77A2, (q15_t)0x2D84, + (q15_t)0x7790, (q15_t)0x2DB3, (q15_t)0x777E, (q15_t)0x2DE2, + (q15_t)0x776C, (q15_t)0x2E11, (q15_t)0x775A, (q15_t)0x2E3F, + (q15_t)0x7747, (q15_t)0x2E6E, (q15_t)0x7735, (q15_t)0x2E9D, + (q15_t)0x7723, (q15_t)0x2ECC, (q15_t)0x7710, (q15_t)0x2EFB, + (q15_t)0x76FE, (q15_t)0x2F29, (q15_t)0x76EB, (q15_t)0x2F58, + (q15_t)0x76D9, (q15_t)0x2F87, (q15_t)0x76C6, (q15_t)0x2FB5, + (q15_t)0x76B3, (q15_t)0x2FE4, (q15_t)0x76A0, (q15_t)0x3013, + (q15_t)0x768E, (q15_t)0x3041, (q15_t)0x767B, (q15_t)0x3070, + (q15_t)0x7668, (q15_t)0x309E, (q15_t)0x7654, (q15_t)0x30CD, + (q15_t)0x7641, (q15_t)0x30FB, (q15_t)0x762E, (q15_t)0x312A, + (q15_t)0x761B, (q15_t)0x3158, (q15_t)0x7607, (q15_t)0x3186, + (q15_t)0x75F4, (q15_t)0x31B5, (q15_t)0x75E0, (q15_t)0x31E3, + (q15_t)0x75CC, (q15_t)0x3211, (q15_t)0x75B9, (q15_t)0x3240, + (q15_t)0x75A5, (q15_t)0x326E, (q15_t)0x7591, (q15_t)0x329C, + (q15_t)0x757D, (q15_t)0x32CA, (q15_t)0x7569, (q15_t)0x32F8, + (q15_t)0x7555, (q15_t)0x3326, (q15_t)0x7541, (q15_t)0x3354, + (q15_t)0x752D, (q15_t)0x3382, (q15_t)0x7519, (q15_t)0x33B0, + (q15_t)0x7504, (q15_t)0x33DE, (q15_t)0x74F0, (q15_t)0x340C, + (q15_t)0x74DB, (q15_t)0x343A, (q15_t)0x74C7, (q15_t)0x3468, + (q15_t)0x74B2, (q15_t)0x3496, (q15_t)0x749E, (q15_t)0x34C4, + (q15_t)0x7489, (q15_t)0x34F2, (q15_t)0x7474, (q15_t)0x351F, + (q15_t)0x745F, (q15_t)0x354D, (q15_t)0x744A, (q15_t)0x357B, + (q15_t)0x7435, (q15_t)0x35A8, (q15_t)0x7420, (q15_t)0x35D6, + (q15_t)0x740B, (q15_t)0x3604, (q15_t)0x73F6, (q15_t)0x3631, + (q15_t)0x73E0, (q15_t)0x365F, (q15_t)0x73CB, (q15_t)0x368C, + (q15_t)0x73B5, (q15_t)0x36BA, (q15_t)0x73A0, (q15_t)0x36E7, + (q15_t)0x738A, (q15_t)0x3714, (q15_t)0x7375, (q15_t)0x3742, + (q15_t)0x735F, (q15_t)0x376F, (q15_t)0x7349, (q15_t)0x379C, + (q15_t)0x7333, (q15_t)0x37CA, (q15_t)0x731D, (q15_t)0x37F7, + (q15_t)0x7307, (q15_t)0x3824, (q15_t)0x72F1, (q15_t)0x3851, + (q15_t)0x72DB, (q15_t)0x387E, (q15_t)0x72C5, (q15_t)0x38AB, + (q15_t)0x72AF, (q15_t)0x38D8, (q15_t)0x7298, (q15_t)0x3906, + (q15_t)0x7282, (q15_t)0x3932, (q15_t)0x726B, (q15_t)0x395F, + (q15_t)0x7255, (q15_t)0x398C, (q15_t)0x723E, (q15_t)0x39B9, + (q15_t)0x7227, (q15_t)0x39E6, (q15_t)0x7211, (q15_t)0x3A13, + (q15_t)0x71FA, (q15_t)0x3A40, (q15_t)0x71E3, (q15_t)0x3A6C, + (q15_t)0x71CC, (q15_t)0x3A99, (q15_t)0x71B5, (q15_t)0x3AC6, + (q15_t)0x719E, (q15_t)0x3AF2, (q15_t)0x7186, (q15_t)0x3B1F, + (q15_t)0x716F, (q15_t)0x3B4C, (q15_t)0x7158, (q15_t)0x3B78, + (q15_t)0x7141, (q15_t)0x3BA5, (q15_t)0x7129, (q15_t)0x3BD1, + (q15_t)0x7112, (q15_t)0x3BFD, (q15_t)0x70FA, (q15_t)0x3C2A, + (q15_t)0x70E2, (q15_t)0x3C56, (q15_t)0x70CB, (q15_t)0x3C83, + (q15_t)0x70B3, (q15_t)0x3CAF, (q15_t)0x709B, (q15_t)0x3CDB, + (q15_t)0x7083, (q15_t)0x3D07, (q15_t)0x706B, (q15_t)0x3D33, + (q15_t)0x7053, (q15_t)0x3D60, (q15_t)0x703B, (q15_t)0x3D8C, + (q15_t)0x7023, (q15_t)0x3DB8, (q15_t)0x700A, (q15_t)0x3DE4, + (q15_t)0x6FF2, (q15_t)0x3E10, (q15_t)0x6FDA, (q15_t)0x3E3C, + (q15_t)0x6FC1, (q15_t)0x3E68, (q15_t)0x6FA9, (q15_t)0x3E93, + (q15_t)0x6F90, (q15_t)0x3EBF, (q15_t)0x6F77, (q15_t)0x3EEB, + (q15_t)0x6F5F, (q15_t)0x3F17, (q15_t)0x6F46, (q15_t)0x3F43, + (q15_t)0x6F2D, (q15_t)0x3F6E, (q15_t)0x6F14, (q15_t)0x3F9A, + (q15_t)0x6EFB, (q15_t)0x3FC5, (q15_t)0x6EE2, (q15_t)0x3FF1, + (q15_t)0x6EC9, (q15_t)0x401D, (q15_t)0x6EAF, (q15_t)0x4048, + (q15_t)0x6E96, (q15_t)0x4073, (q15_t)0x6E7D, (q15_t)0x409F, + (q15_t)0x6E63, (q15_t)0x40CA, (q15_t)0x6E4A, (q15_t)0x40F6, + (q15_t)0x6E30, (q15_t)0x4121, (q15_t)0x6E17, (q15_t)0x414C, + (q15_t)0x6DFD, (q15_t)0x4177, (q15_t)0x6DE3, (q15_t)0x41A2, + (q15_t)0x6DCA, (q15_t)0x41CE, (q15_t)0x6DB0, (q15_t)0x41F9, + (q15_t)0x6D96, (q15_t)0x4224, (q15_t)0x6D7C, (q15_t)0x424F, + (q15_t)0x6D62, (q15_t)0x427A, (q15_t)0x6D48, (q15_t)0x42A5, + (q15_t)0x6D2D, (q15_t)0x42D0, (q15_t)0x6D13, (q15_t)0x42FA, + (q15_t)0x6CF9, (q15_t)0x4325, (q15_t)0x6CDE, (q15_t)0x4350, + (q15_t)0x6CC4, (q15_t)0x437B, (q15_t)0x6CA9, (q15_t)0x43A5, + (q15_t)0x6C8F, (q15_t)0x43D0, (q15_t)0x6C74, (q15_t)0x43FB, + (q15_t)0x6C59, (q15_t)0x4425, (q15_t)0x6C3F, (q15_t)0x4450, + (q15_t)0x6C24, (q15_t)0x447A, (q15_t)0x6C09, (q15_t)0x44A5, + (q15_t)0x6BEE, (q15_t)0x44CF, (q15_t)0x6BD3, (q15_t)0x44FA, + (q15_t)0x6BB8, (q15_t)0x4524, (q15_t)0x6B9C, (q15_t)0x454E, + (q15_t)0x6B81, (q15_t)0x4578, (q15_t)0x6B66, (q15_t)0x45A3, + (q15_t)0x6B4A, (q15_t)0x45CD, (q15_t)0x6B2F, (q15_t)0x45F7, + (q15_t)0x6B13, (q15_t)0x4621, (q15_t)0x6AF8, (q15_t)0x464B, + (q15_t)0x6ADC, (q15_t)0x4675, (q15_t)0x6AC1, (q15_t)0x469F, + (q15_t)0x6AA5, (q15_t)0x46C9, (q15_t)0x6A89, (q15_t)0x46F3, + (q15_t)0x6A6D, (q15_t)0x471C, (q15_t)0x6A51, (q15_t)0x4746, + (q15_t)0x6A35, (q15_t)0x4770, (q15_t)0x6A19, (q15_t)0x479A, + (q15_t)0x69FD, (q15_t)0x47C3, (q15_t)0x69E1, (q15_t)0x47ED, + (q15_t)0x69C4, (q15_t)0x4816, (q15_t)0x69A8, (q15_t)0x4840, + (q15_t)0x698C, (q15_t)0x4869, (q15_t)0x696F, (q15_t)0x4893, + (q15_t)0x6953, (q15_t)0x48BC, (q15_t)0x6936, (q15_t)0x48E6, + (q15_t)0x6919, (q15_t)0x490F, (q15_t)0x68FD, (q15_t)0x4938, + (q15_t)0x68E0, (q15_t)0x4961, (q15_t)0x68C3, (q15_t)0x498A, + (q15_t)0x68A6, (q15_t)0x49B4, (q15_t)0x6889, (q15_t)0x49DD, + (q15_t)0x686C, (q15_t)0x4A06, (q15_t)0x684F, (q15_t)0x4A2F, + (q15_t)0x6832, (q15_t)0x4A58, (q15_t)0x6815, (q15_t)0x4A81, + (q15_t)0x67F7, (q15_t)0x4AA9, (q15_t)0x67DA, (q15_t)0x4AD2, + (q15_t)0x67BD, (q15_t)0x4AFB, (q15_t)0x679F, (q15_t)0x4B24, + (q15_t)0x6782, (q15_t)0x4B4C, (q15_t)0x6764, (q15_t)0x4B75, + (q15_t)0x6746, (q15_t)0x4B9E, (q15_t)0x6729, (q15_t)0x4BC6, + (q15_t)0x670B, (q15_t)0x4BEF, (q15_t)0x66ED, (q15_t)0x4C17, + (q15_t)0x66CF, (q15_t)0x4C3F, (q15_t)0x66B1, (q15_t)0x4C68, + (q15_t)0x6693, (q15_t)0x4C90, (q15_t)0x6675, (q15_t)0x4CB8, + (q15_t)0x6657, (q15_t)0x4CE1, (q15_t)0x6639, (q15_t)0x4D09, + (q15_t)0x661A, (q15_t)0x4D31, (q15_t)0x65FC, (q15_t)0x4D59, + (q15_t)0x65DD, (q15_t)0x4D81, (q15_t)0x65BF, (q15_t)0x4DA9, + (q15_t)0x65A0, (q15_t)0x4DD1, (q15_t)0x6582, (q15_t)0x4DF9, + (q15_t)0x6563, (q15_t)0x4E21, (q15_t)0x6545, (q15_t)0x4E48, + (q15_t)0x6526, (q15_t)0x4E70, (q15_t)0x6507, (q15_t)0x4E98, + (q15_t)0x64E8, (q15_t)0x4EBF, (q15_t)0x64C9, (q15_t)0x4EE7, + (q15_t)0x64AA, (q15_t)0x4F0F, (q15_t)0x648B, (q15_t)0x4F36, + (q15_t)0x646C, (q15_t)0x4F5E, (q15_t)0x644D, (q15_t)0x4F85, + (q15_t)0x642D, (q15_t)0x4FAC, (q15_t)0x640E, (q15_t)0x4FD4, + (q15_t)0x63EF, (q15_t)0x4FFB, (q15_t)0x63CF, (q15_t)0x5022, + (q15_t)0x63B0, (q15_t)0x5049, (q15_t)0x6390, (q15_t)0x5070, + (q15_t)0x6371, (q15_t)0x5097, (q15_t)0x6351, (q15_t)0x50BF, + (q15_t)0x6331, (q15_t)0x50E5, (q15_t)0x6311, (q15_t)0x510C, + (q15_t)0x62F2, (q15_t)0x5133, (q15_t)0x62D2, (q15_t)0x515A, + (q15_t)0x62B2, (q15_t)0x5181, (q15_t)0x6292, (q15_t)0x51A8, + (q15_t)0x6271, (q15_t)0x51CE, (q15_t)0x6251, (q15_t)0x51F5, + (q15_t)0x6231, (q15_t)0x521C, (q15_t)0x6211, (q15_t)0x5242, + (q15_t)0x61F1, (q15_t)0x5269, (q15_t)0x61D0, (q15_t)0x528F, + (q15_t)0x61B0, (q15_t)0x52B5, (q15_t)0x618F, (q15_t)0x52DC, + (q15_t)0x616F, (q15_t)0x5302, (q15_t)0x614E, (q15_t)0x5328, + (q15_t)0x612D, (q15_t)0x534E, (q15_t)0x610D, (q15_t)0x5375, + (q15_t)0x60EC, (q15_t)0x539B, (q15_t)0x60CB, (q15_t)0x53C1, + (q15_t)0x60AA, (q15_t)0x53E7, (q15_t)0x6089, (q15_t)0x540D, + (q15_t)0x6068, (q15_t)0x5433, (q15_t)0x6047, (q15_t)0x5458, + (q15_t)0x6026, (q15_t)0x547E, (q15_t)0x6004, (q15_t)0x54A4, + (q15_t)0x5FE3, (q15_t)0x54CA, (q15_t)0x5FC2, (q15_t)0x54EF, + (q15_t)0x5FA0, (q15_t)0x5515, (q15_t)0x5F7F, (q15_t)0x553A, + (q15_t)0x5F5E, (q15_t)0x5560, (q15_t)0x5F3C, (q15_t)0x5585, + (q15_t)0x5F1A, (q15_t)0x55AB, (q15_t)0x5EF9, (q15_t)0x55D0, + (q15_t)0x5ED7, (q15_t)0x55F5, (q15_t)0x5EB5, (q15_t)0x561A, + (q15_t)0x5E93, (q15_t)0x5640, (q15_t)0x5E71, (q15_t)0x5665, + (q15_t)0x5E50, (q15_t)0x568A, (q15_t)0x5E2D, (q15_t)0x56AF, + (q15_t)0x5E0B, (q15_t)0x56D4, (q15_t)0x5DE9, (q15_t)0x56F9, + (q15_t)0x5DC7, (q15_t)0x571D, (q15_t)0x5DA5, (q15_t)0x5742, + (q15_t)0x5D83, (q15_t)0x5767, (q15_t)0x5D60, (q15_t)0x578C, + (q15_t)0x5D3E, (q15_t)0x57B0, (q15_t)0x5D1B, (q15_t)0x57D5, + (q15_t)0x5CF9, (q15_t)0x57F9, (q15_t)0x5CD6, (q15_t)0x581E, + (q15_t)0x5CB4, (q15_t)0x5842, (q15_t)0x5C91, (q15_t)0x5867, + (q15_t)0x5C6E, (q15_t)0x588B, (q15_t)0x5C4B, (q15_t)0x58AF, + (q15_t)0x5C29, (q15_t)0x58D4, (q15_t)0x5C06, (q15_t)0x58F8, + (q15_t)0x5BE3, (q15_t)0x591C, (q15_t)0x5BC0, (q15_t)0x5940, + (q15_t)0x5B9D, (q15_t)0x5964, (q15_t)0x5B79, (q15_t)0x5988, + (q15_t)0x5B56, (q15_t)0x59AC, (q15_t)0x5B33, (q15_t)0x59D0, + (q15_t)0x5B10, (q15_t)0x59F3, (q15_t)0x5AEC, (q15_t)0x5A17, + (q15_t)0x5AC9, (q15_t)0x5A3B, (q15_t)0x5AA5, (q15_t)0x5A5E, + (q15_t)0x5A82, (q15_t)0x5A82, (q15_t)0x5A5E, (q15_t)0x5AA5, + (q15_t)0x5A3B, (q15_t)0x5AC9, (q15_t)0x5A17, (q15_t)0x5AEC, + (q15_t)0x59F3, (q15_t)0x5B10, (q15_t)0x59D0, (q15_t)0x5B33, + (q15_t)0x59AC, (q15_t)0x5B56, (q15_t)0x5988, (q15_t)0x5B79, + (q15_t)0x5964, (q15_t)0x5B9D, (q15_t)0x5940, (q15_t)0x5BC0, + (q15_t)0x591C, (q15_t)0x5BE3, (q15_t)0x58F8, (q15_t)0x5C06, + (q15_t)0x58D4, (q15_t)0x5C29, (q15_t)0x58AF, (q15_t)0x5C4B, + (q15_t)0x588B, (q15_t)0x5C6E, (q15_t)0x5867, (q15_t)0x5C91, + (q15_t)0x5842, (q15_t)0x5CB4, (q15_t)0x581E, (q15_t)0x5CD6, + (q15_t)0x57F9, (q15_t)0x5CF9, (q15_t)0x57D5, (q15_t)0x5D1B, + (q15_t)0x57B0, (q15_t)0x5D3E, (q15_t)0x578C, (q15_t)0x5D60, + (q15_t)0x5767, (q15_t)0x5D83, (q15_t)0x5742, (q15_t)0x5DA5, + (q15_t)0x571D, (q15_t)0x5DC7, (q15_t)0x56F9, (q15_t)0x5DE9, + (q15_t)0x56D4, (q15_t)0x5E0B, (q15_t)0x56AF, (q15_t)0x5E2D, + (q15_t)0x568A, (q15_t)0x5E50, (q15_t)0x5665, (q15_t)0x5E71, + (q15_t)0x5640, (q15_t)0x5E93, (q15_t)0x561A, (q15_t)0x5EB5, + (q15_t)0x55F5, (q15_t)0x5ED7, (q15_t)0x55D0, (q15_t)0x5EF9, + (q15_t)0x55AB, (q15_t)0x5F1A, (q15_t)0x5585, (q15_t)0x5F3C, + (q15_t)0x5560, (q15_t)0x5F5E, (q15_t)0x553A, (q15_t)0x5F7F, + (q15_t)0x5515, (q15_t)0x5FA0, (q15_t)0x54EF, (q15_t)0x5FC2, + (q15_t)0x54CA, (q15_t)0x5FE3, (q15_t)0x54A4, (q15_t)0x6004, + (q15_t)0x547E, (q15_t)0x6026, (q15_t)0x5458, (q15_t)0x6047, + (q15_t)0x5433, (q15_t)0x6068, (q15_t)0x540D, (q15_t)0x6089, + (q15_t)0x53E7, (q15_t)0x60AA, (q15_t)0x53C1, (q15_t)0x60CB, + (q15_t)0x539B, (q15_t)0x60EC, (q15_t)0x5375, (q15_t)0x610D, + (q15_t)0x534E, (q15_t)0x612D, (q15_t)0x5328, (q15_t)0x614E, + (q15_t)0x5302, (q15_t)0x616F, (q15_t)0x52DC, (q15_t)0x618F, + (q15_t)0x52B5, (q15_t)0x61B0, (q15_t)0x528F, (q15_t)0x61D0, + (q15_t)0x5269, (q15_t)0x61F1, (q15_t)0x5242, (q15_t)0x6211, + (q15_t)0x521C, (q15_t)0x6231, (q15_t)0x51F5, (q15_t)0x6251, + (q15_t)0x51CE, (q15_t)0x6271, (q15_t)0x51A8, (q15_t)0x6292, + (q15_t)0x5181, (q15_t)0x62B2, (q15_t)0x515A, (q15_t)0x62D2, + (q15_t)0x5133, (q15_t)0x62F2, (q15_t)0x510C, (q15_t)0x6311, + (q15_t)0x50E5, (q15_t)0x6331, (q15_t)0x50BF, (q15_t)0x6351, + (q15_t)0x5097, (q15_t)0x6371, (q15_t)0x5070, (q15_t)0x6390, + (q15_t)0x5049, (q15_t)0x63B0, (q15_t)0x5022, (q15_t)0x63CF, + (q15_t)0x4FFB, (q15_t)0x63EF, (q15_t)0x4FD4, (q15_t)0x640E, + (q15_t)0x4FAC, (q15_t)0x642D, (q15_t)0x4F85, (q15_t)0x644D, + (q15_t)0x4F5E, (q15_t)0x646C, (q15_t)0x4F36, (q15_t)0x648B, + (q15_t)0x4F0F, (q15_t)0x64AA, (q15_t)0x4EE7, (q15_t)0x64C9, + (q15_t)0x4EBF, (q15_t)0x64E8, (q15_t)0x4E98, (q15_t)0x6507, + (q15_t)0x4E70, (q15_t)0x6526, (q15_t)0x4E48, (q15_t)0x6545, + (q15_t)0x4E21, (q15_t)0x6563, (q15_t)0x4DF9, (q15_t)0x6582, + (q15_t)0x4DD1, (q15_t)0x65A0, (q15_t)0x4DA9, (q15_t)0x65BF, + (q15_t)0x4D81, (q15_t)0x65DD, (q15_t)0x4D59, (q15_t)0x65FC, + (q15_t)0x4D31, (q15_t)0x661A, (q15_t)0x4D09, (q15_t)0x6639, + (q15_t)0x4CE1, (q15_t)0x6657, (q15_t)0x4CB8, (q15_t)0x6675, + (q15_t)0x4C90, (q15_t)0x6693, (q15_t)0x4C68, (q15_t)0x66B1, + (q15_t)0x4C3F, (q15_t)0x66CF, (q15_t)0x4C17, (q15_t)0x66ED, + (q15_t)0x4BEF, (q15_t)0x670B, (q15_t)0x4BC6, (q15_t)0x6729, + (q15_t)0x4B9E, (q15_t)0x6746, (q15_t)0x4B75, (q15_t)0x6764, + (q15_t)0x4B4C, (q15_t)0x6782, (q15_t)0x4B24, (q15_t)0x679F, + (q15_t)0x4AFB, (q15_t)0x67BD, (q15_t)0x4AD2, (q15_t)0x67DA, + (q15_t)0x4AA9, (q15_t)0x67F7, (q15_t)0x4A81, (q15_t)0x6815, + (q15_t)0x4A58, (q15_t)0x6832, (q15_t)0x4A2F, (q15_t)0x684F, + (q15_t)0x4A06, (q15_t)0x686C, (q15_t)0x49DD, (q15_t)0x6889, + (q15_t)0x49B4, (q15_t)0x68A6, (q15_t)0x498A, (q15_t)0x68C3, + (q15_t)0x4961, (q15_t)0x68E0, (q15_t)0x4938, (q15_t)0x68FD, + (q15_t)0x490F, (q15_t)0x6919, (q15_t)0x48E6, (q15_t)0x6936, + (q15_t)0x48BC, (q15_t)0x6953, (q15_t)0x4893, (q15_t)0x696F, + (q15_t)0x4869, (q15_t)0x698C, (q15_t)0x4840, (q15_t)0x69A8, + (q15_t)0x4816, (q15_t)0x69C4, (q15_t)0x47ED, (q15_t)0x69E1, + (q15_t)0x47C3, (q15_t)0x69FD, (q15_t)0x479A, (q15_t)0x6A19, + (q15_t)0x4770, (q15_t)0x6A35, (q15_t)0x4746, (q15_t)0x6A51, + (q15_t)0x471C, (q15_t)0x6A6D, (q15_t)0x46F3, (q15_t)0x6A89, + (q15_t)0x46C9, (q15_t)0x6AA5, (q15_t)0x469F, (q15_t)0x6AC1, + (q15_t)0x4675, (q15_t)0x6ADC, (q15_t)0x464B, (q15_t)0x6AF8, + (q15_t)0x4621, (q15_t)0x6B13, (q15_t)0x45F7, (q15_t)0x6B2F, + (q15_t)0x45CD, (q15_t)0x6B4A, (q15_t)0x45A3, (q15_t)0x6B66, + (q15_t)0x4578, (q15_t)0x6B81, (q15_t)0x454E, (q15_t)0x6B9C, + (q15_t)0x4524, (q15_t)0x6BB8, (q15_t)0x44FA, (q15_t)0x6BD3, + (q15_t)0x44CF, (q15_t)0x6BEE, (q15_t)0x44A5, (q15_t)0x6C09, + (q15_t)0x447A, (q15_t)0x6C24, (q15_t)0x4450, (q15_t)0x6C3F, + (q15_t)0x4425, (q15_t)0x6C59, (q15_t)0x43FB, (q15_t)0x6C74, + (q15_t)0x43D0, (q15_t)0x6C8F, (q15_t)0x43A5, (q15_t)0x6CA9, + (q15_t)0x437B, (q15_t)0x6CC4, (q15_t)0x4350, (q15_t)0x6CDE, + (q15_t)0x4325, (q15_t)0x6CF9, (q15_t)0x42FA, (q15_t)0x6D13, + (q15_t)0x42D0, (q15_t)0x6D2D, (q15_t)0x42A5, (q15_t)0x6D48, + (q15_t)0x427A, (q15_t)0x6D62, (q15_t)0x424F, (q15_t)0x6D7C, + (q15_t)0x4224, (q15_t)0x6D96, (q15_t)0x41F9, (q15_t)0x6DB0, + (q15_t)0x41CE, (q15_t)0x6DCA, (q15_t)0x41A2, (q15_t)0x6DE3, + (q15_t)0x4177, (q15_t)0x6DFD, (q15_t)0x414C, (q15_t)0x6E17, + (q15_t)0x4121, (q15_t)0x6E30, (q15_t)0x40F6, (q15_t)0x6E4A, + (q15_t)0x40CA, (q15_t)0x6E63, (q15_t)0x409F, (q15_t)0x6E7D, + (q15_t)0x4073, (q15_t)0x6E96, (q15_t)0x4048, (q15_t)0x6EAF, + (q15_t)0x401D, (q15_t)0x6EC9, (q15_t)0x3FF1, (q15_t)0x6EE2, + (q15_t)0x3FC5, (q15_t)0x6EFB, (q15_t)0x3F9A, (q15_t)0x6F14, + (q15_t)0x3F6E, (q15_t)0x6F2D, (q15_t)0x3F43, (q15_t)0x6F46, + (q15_t)0x3F17, (q15_t)0x6F5F, (q15_t)0x3EEB, (q15_t)0x6F77, + (q15_t)0x3EBF, (q15_t)0x6F90, (q15_t)0x3E93, (q15_t)0x6FA9, + (q15_t)0x3E68, (q15_t)0x6FC1, (q15_t)0x3E3C, (q15_t)0x6FDA, + (q15_t)0x3E10, (q15_t)0x6FF2, (q15_t)0x3DE4, (q15_t)0x700A, + (q15_t)0x3DB8, (q15_t)0x7023, (q15_t)0x3D8C, (q15_t)0x703B, + (q15_t)0x3D60, (q15_t)0x7053, (q15_t)0x3D33, (q15_t)0x706B, + (q15_t)0x3D07, (q15_t)0x7083, (q15_t)0x3CDB, (q15_t)0x709B, + (q15_t)0x3CAF, (q15_t)0x70B3, (q15_t)0x3C83, (q15_t)0x70CB, + (q15_t)0x3C56, (q15_t)0x70E2, (q15_t)0x3C2A, (q15_t)0x70FA, + (q15_t)0x3BFD, (q15_t)0x7112, (q15_t)0x3BD1, (q15_t)0x7129, + (q15_t)0x3BA5, (q15_t)0x7141, (q15_t)0x3B78, (q15_t)0x7158, + (q15_t)0x3B4C, (q15_t)0x716F, (q15_t)0x3B1F, (q15_t)0x7186, + (q15_t)0x3AF2, (q15_t)0x719E, (q15_t)0x3AC6, (q15_t)0x71B5, + (q15_t)0x3A99, (q15_t)0x71CC, (q15_t)0x3A6C, (q15_t)0x71E3, + (q15_t)0x3A40, (q15_t)0x71FA, (q15_t)0x3A13, (q15_t)0x7211, + (q15_t)0x39E6, (q15_t)0x7227, (q15_t)0x39B9, (q15_t)0x723E, + (q15_t)0x398C, (q15_t)0x7255, (q15_t)0x395F, (q15_t)0x726B, + (q15_t)0x3932, (q15_t)0x7282, (q15_t)0x3906, (q15_t)0x7298, + (q15_t)0x38D8, (q15_t)0x72AF, (q15_t)0x38AB, (q15_t)0x72C5, + (q15_t)0x387E, (q15_t)0x72DB, (q15_t)0x3851, (q15_t)0x72F1, + (q15_t)0x3824, (q15_t)0x7307, (q15_t)0x37F7, (q15_t)0x731D, + (q15_t)0x37CA, (q15_t)0x7333, (q15_t)0x379C, (q15_t)0x7349, + (q15_t)0x376F, (q15_t)0x735F, (q15_t)0x3742, (q15_t)0x7375, + (q15_t)0x3714, (q15_t)0x738A, (q15_t)0x36E7, (q15_t)0x73A0, + (q15_t)0x36BA, (q15_t)0x73B5, (q15_t)0x368C, (q15_t)0x73CB, + (q15_t)0x365F, (q15_t)0x73E0, (q15_t)0x3631, (q15_t)0x73F6, + (q15_t)0x3604, (q15_t)0x740B, (q15_t)0x35D6, (q15_t)0x7420, + (q15_t)0x35A8, (q15_t)0x7435, (q15_t)0x357B, (q15_t)0x744A, + (q15_t)0x354D, (q15_t)0x745F, (q15_t)0x351F, (q15_t)0x7474, + (q15_t)0x34F2, (q15_t)0x7489, (q15_t)0x34C4, (q15_t)0x749E, + (q15_t)0x3496, (q15_t)0x74B2, (q15_t)0x3468, (q15_t)0x74C7, + (q15_t)0x343A, (q15_t)0x74DB, (q15_t)0x340C, (q15_t)0x74F0, + (q15_t)0x33DE, (q15_t)0x7504, (q15_t)0x33B0, (q15_t)0x7519, + (q15_t)0x3382, (q15_t)0x752D, (q15_t)0x3354, (q15_t)0x7541, + (q15_t)0x3326, (q15_t)0x7555, (q15_t)0x32F8, (q15_t)0x7569, + (q15_t)0x32CA, (q15_t)0x757D, (q15_t)0x329C, (q15_t)0x7591, + (q15_t)0x326E, (q15_t)0x75A5, (q15_t)0x3240, (q15_t)0x75B9, + (q15_t)0x3211, (q15_t)0x75CC, (q15_t)0x31E3, (q15_t)0x75E0, + (q15_t)0x31B5, (q15_t)0x75F4, (q15_t)0x3186, (q15_t)0x7607, + (q15_t)0x3158, (q15_t)0x761B, (q15_t)0x312A, (q15_t)0x762E, + (q15_t)0x30FB, (q15_t)0x7641, (q15_t)0x30CD, (q15_t)0x7654, + (q15_t)0x309E, (q15_t)0x7668, (q15_t)0x3070, (q15_t)0x767B, + (q15_t)0x3041, (q15_t)0x768E, (q15_t)0x3013, (q15_t)0x76A0, + (q15_t)0x2FE4, (q15_t)0x76B3, (q15_t)0x2FB5, (q15_t)0x76C6, + (q15_t)0x2F87, (q15_t)0x76D9, (q15_t)0x2F58, (q15_t)0x76EB, + (q15_t)0x2F29, (q15_t)0x76FE, (q15_t)0x2EFB, (q15_t)0x7710, + (q15_t)0x2ECC, (q15_t)0x7723, (q15_t)0x2E9D, (q15_t)0x7735, + (q15_t)0x2E6E, (q15_t)0x7747, (q15_t)0x2E3F, (q15_t)0x775A, + (q15_t)0x2E11, (q15_t)0x776C, (q15_t)0x2DE2, (q15_t)0x777E, + (q15_t)0x2DB3, (q15_t)0x7790, (q15_t)0x2D84, (q15_t)0x77A2, + (q15_t)0x2D55, (q15_t)0x77B4, (q15_t)0x2D26, (q15_t)0x77C5, + (q15_t)0x2CF7, (q15_t)0x77D7, (q15_t)0x2CC8, (q15_t)0x77E9, + (q15_t)0x2C98, (q15_t)0x77FA, (q15_t)0x2C69, (q15_t)0x780C, + (q15_t)0x2C3A, (q15_t)0x781D, (q15_t)0x2C0B, (q15_t)0x782E, + (q15_t)0x2BDC, (q15_t)0x7840, (q15_t)0x2BAD, (q15_t)0x7851, + (q15_t)0x2B7D, (q15_t)0x7862, (q15_t)0x2B4E, (q15_t)0x7873, + (q15_t)0x2B1F, (q15_t)0x7884, (q15_t)0x2AEF, (q15_t)0x7895, + (q15_t)0x2AC0, (q15_t)0x78A6, (q15_t)0x2A91, (q15_t)0x78B6, + (q15_t)0x2A61, (q15_t)0x78C7, (q15_t)0x2A32, (q15_t)0x78D8, + (q15_t)0x2A02, (q15_t)0x78E8, (q15_t)0x29D3, (q15_t)0x78F9, + (q15_t)0x29A3, (q15_t)0x7909, (q15_t)0x2974, (q15_t)0x7919, + (q15_t)0x2944, (q15_t)0x792A, (q15_t)0x2915, (q15_t)0x793A, + (q15_t)0x28E5, (q15_t)0x794A, (q15_t)0x28B5, (q15_t)0x795A, + (q15_t)0x2886, (q15_t)0x796A, (q15_t)0x2856, (q15_t)0x797A, + (q15_t)0x2826, (q15_t)0x798A, (q15_t)0x27F6, (q15_t)0x7999, + (q15_t)0x27C7, (q15_t)0x79A9, (q15_t)0x2797, (q15_t)0x79B9, + (q15_t)0x2767, (q15_t)0x79C8, (q15_t)0x2737, (q15_t)0x79D8, + (q15_t)0x2707, (q15_t)0x79E7, (q15_t)0x26D8, (q15_t)0x79F6, + (q15_t)0x26A8, (q15_t)0x7A05, (q15_t)0x2678, (q15_t)0x7A15, + (q15_t)0x2648, (q15_t)0x7A24, (q15_t)0x2618, (q15_t)0x7A33, + (q15_t)0x25E8, (q15_t)0x7A42, (q15_t)0x25B8, (q15_t)0x7A50, + (q15_t)0x2588, (q15_t)0x7A5F, (q15_t)0x2558, (q15_t)0x7A6E, + (q15_t)0x2528, (q15_t)0x7A7D, (q15_t)0x24F7, (q15_t)0x7A8B, + (q15_t)0x24C7, (q15_t)0x7A9A, (q15_t)0x2497, (q15_t)0x7AA8, + (q15_t)0x2467, (q15_t)0x7AB6, (q15_t)0x2437, (q15_t)0x7AC5, + (q15_t)0x2407, (q15_t)0x7AD3, (q15_t)0x23D6, (q15_t)0x7AE1, + (q15_t)0x23A6, (q15_t)0x7AEF, (q15_t)0x2376, (q15_t)0x7AFD, + (q15_t)0x2345, (q15_t)0x7B0B, (q15_t)0x2315, (q15_t)0x7B19, + (q15_t)0x22E5, (q15_t)0x7B26, (q15_t)0x22B4, (q15_t)0x7B34, + (q15_t)0x2284, (q15_t)0x7B42, (q15_t)0x2254, (q15_t)0x7B4F, + (q15_t)0x2223, (q15_t)0x7B5D, (q15_t)0x21F3, (q15_t)0x7B6A, + (q15_t)0x21C2, (q15_t)0x7B77, (q15_t)0x2192, (q15_t)0x7B84, + (q15_t)0x2161, (q15_t)0x7B92, (q15_t)0x2131, (q15_t)0x7B9F, + (q15_t)0x2100, (q15_t)0x7BAC, (q15_t)0x20D0, (q15_t)0x7BB9, + (q15_t)0x209F, (q15_t)0x7BC5, (q15_t)0x206E, (q15_t)0x7BD2, + (q15_t)0x203E, (q15_t)0x7BDF, (q15_t)0x200D, (q15_t)0x7BEB, + (q15_t)0x1FDC, (q15_t)0x7BF8, (q15_t)0x1FAC, (q15_t)0x7C05, + (q15_t)0x1F7B, (q15_t)0x7C11, (q15_t)0x1F4A, (q15_t)0x7C1D, + (q15_t)0x1F19, (q15_t)0x7C29, (q15_t)0x1EE9, (q15_t)0x7C36, + (q15_t)0x1EB8, (q15_t)0x7C42, (q15_t)0x1E87, (q15_t)0x7C4E, + (q15_t)0x1E56, (q15_t)0x7C5A, (q15_t)0x1E25, (q15_t)0x7C66, + (q15_t)0x1DF5, (q15_t)0x7C71, (q15_t)0x1DC4, (q15_t)0x7C7D, + (q15_t)0x1D93, (q15_t)0x7C89, (q15_t)0x1D62, (q15_t)0x7C94, + (q15_t)0x1D31, (q15_t)0x7CA0, (q15_t)0x1D00, (q15_t)0x7CAB, + (q15_t)0x1CCF, (q15_t)0x7CB7, (q15_t)0x1C9E, (q15_t)0x7CC2, + (q15_t)0x1C6D, (q15_t)0x7CCD, (q15_t)0x1C3C, (q15_t)0x7CD8, + (q15_t)0x1C0B, (q15_t)0x7CE3, (q15_t)0x1BDA, (q15_t)0x7CEE, + (q15_t)0x1BA9, (q15_t)0x7CF9, (q15_t)0x1B78, (q15_t)0x7D04, + (q15_t)0x1B47, (q15_t)0x7D0F, (q15_t)0x1B16, (q15_t)0x7D19, + (q15_t)0x1AE4, (q15_t)0x7D24, (q15_t)0x1AB3, (q15_t)0x7D2F, + (q15_t)0x1A82, (q15_t)0x7D39, (q15_t)0x1A51, (q15_t)0x7D43, + (q15_t)0x1A20, (q15_t)0x7D4E, (q15_t)0x19EF, (q15_t)0x7D58, + (q15_t)0x19BD, (q15_t)0x7D62, (q15_t)0x198C, (q15_t)0x7D6C, + (q15_t)0x195B, (q15_t)0x7D76, (q15_t)0x192A, (q15_t)0x7D80, + (q15_t)0x18F8, (q15_t)0x7D8A, (q15_t)0x18C7, (q15_t)0x7D94, + (q15_t)0x1896, (q15_t)0x7D9D, (q15_t)0x1864, (q15_t)0x7DA7, + (q15_t)0x1833, (q15_t)0x7DB0, (q15_t)0x1802, (q15_t)0x7DBA, + (q15_t)0x17D0, (q15_t)0x7DC3, (q15_t)0x179F, (q15_t)0x7DCD, + (q15_t)0x176D, (q15_t)0x7DD6, (q15_t)0x173C, (q15_t)0x7DDF, + (q15_t)0x170A, (q15_t)0x7DE8, (q15_t)0x16D9, (q15_t)0x7DF1, + (q15_t)0x16A8, (q15_t)0x7DFA, (q15_t)0x1676, (q15_t)0x7E03, + (q15_t)0x1645, (q15_t)0x7E0C, (q15_t)0x1613, (q15_t)0x7E14, + (q15_t)0x15E2, (q15_t)0x7E1D, (q15_t)0x15B0, (q15_t)0x7E26, + (q15_t)0x157F, (q15_t)0x7E2E, (q15_t)0x154D, (q15_t)0x7E37, + (q15_t)0x151B, (q15_t)0x7E3F, (q15_t)0x14EA, (q15_t)0x7E47, + (q15_t)0x14B8, (q15_t)0x7E4F, (q15_t)0x1487, (q15_t)0x7E57, + (q15_t)0x1455, (q15_t)0x7E5F, (q15_t)0x1423, (q15_t)0x7E67, + (q15_t)0x13F2, (q15_t)0x7E6F, (q15_t)0x13C0, (q15_t)0x7E77, + (q15_t)0x138E, (q15_t)0x7E7F, (q15_t)0x135D, (q15_t)0x7E86, + (q15_t)0x132B, (q15_t)0x7E8E, (q15_t)0x12F9, (q15_t)0x7E95, + (q15_t)0x12C8, (q15_t)0x7E9D, (q15_t)0x1296, (q15_t)0x7EA4, + (q15_t)0x1264, (q15_t)0x7EAB, (q15_t)0x1232, (q15_t)0x7EB3, + (q15_t)0x1201, (q15_t)0x7EBA, (q15_t)0x11CF, (q15_t)0x7EC1, + (q15_t)0x119D, (q15_t)0x7EC8, (q15_t)0x116B, (q15_t)0x7ECF, + (q15_t)0x1139, (q15_t)0x7ED5, (q15_t)0x1108, (q15_t)0x7EDC, + (q15_t)0x10D6, (q15_t)0x7EE3, (q15_t)0x10A4, (q15_t)0x7EE9, + (q15_t)0x1072, (q15_t)0x7EF0, (q15_t)0x1040, (q15_t)0x7EF6, + (q15_t)0x100E, (q15_t)0x7EFD, (q15_t)0x0FDD, (q15_t)0x7F03, + (q15_t)0x0FAB, (q15_t)0x7F09, (q15_t)0x0F79, (q15_t)0x7F0F, + (q15_t)0x0F47, (q15_t)0x7F15, (q15_t)0x0F15, (q15_t)0x7F1B, + (q15_t)0x0EE3, (q15_t)0x7F21, (q15_t)0x0EB1, (q15_t)0x7F27, + (q15_t)0x0E7F, (q15_t)0x7F2D, (q15_t)0x0E4D, (q15_t)0x7F32, + (q15_t)0x0E1B, (q15_t)0x7F38, (q15_t)0x0DE9, (q15_t)0x7F3D, + (q15_t)0x0DB7, (q15_t)0x7F43, (q15_t)0x0D85, (q15_t)0x7F48, + (q15_t)0x0D53, (q15_t)0x7F4D, (q15_t)0x0D21, (q15_t)0x7F53, + (q15_t)0x0CEF, (q15_t)0x7F58, (q15_t)0x0CBD, (q15_t)0x7F5D, + (q15_t)0x0C8B, (q15_t)0x7F62, (q15_t)0x0C59, (q15_t)0x7F67, + (q15_t)0x0C27, (q15_t)0x7F6B, (q15_t)0x0BF5, (q15_t)0x7F70, + (q15_t)0x0BC3, (q15_t)0x7F75, (q15_t)0x0B91, (q15_t)0x7F79, + (q15_t)0x0B5F, (q15_t)0x7F7E, (q15_t)0x0B2D, (q15_t)0x7F82, + (q15_t)0x0AFB, (q15_t)0x7F87, (q15_t)0x0AC9, (q15_t)0x7F8B, + (q15_t)0x0A97, (q15_t)0x7F8F, (q15_t)0x0A65, (q15_t)0x7F93, + (q15_t)0x0A33, (q15_t)0x7F97, (q15_t)0x0A00, (q15_t)0x7F9B, + (q15_t)0x09CE, (q15_t)0x7F9F, (q15_t)0x099C, (q15_t)0x7FA3, + (q15_t)0x096A, (q15_t)0x7FA7, (q15_t)0x0938, (q15_t)0x7FAA, + (q15_t)0x0906, (q15_t)0x7FAE, (q15_t)0x08D4, (q15_t)0x7FB1, + (q15_t)0x08A2, (q15_t)0x7FB5, (q15_t)0x086F, (q15_t)0x7FB8, + (q15_t)0x083D, (q15_t)0x7FBC, (q15_t)0x080B, (q15_t)0x7FBF, + (q15_t)0x07D9, (q15_t)0x7FC2, (q15_t)0x07A7, (q15_t)0x7FC5, + (q15_t)0x0775, (q15_t)0x7FC8, (q15_t)0x0742, (q15_t)0x7FCB, + (q15_t)0x0710, (q15_t)0x7FCE, (q15_t)0x06DE, (q15_t)0x7FD0, + (q15_t)0x06AC, (q15_t)0x7FD3, (q15_t)0x067A, (q15_t)0x7FD6, + (q15_t)0x0647, (q15_t)0x7FD8, (q15_t)0x0615, (q15_t)0x7FDA, + (q15_t)0x05E3, (q15_t)0x7FDD, (q15_t)0x05B1, (q15_t)0x7FDF, + (q15_t)0x057F, (q15_t)0x7FE1, (q15_t)0x054C, (q15_t)0x7FE3, + (q15_t)0x051A, (q15_t)0x7FE5, (q15_t)0x04E8, (q15_t)0x7FE7, + (q15_t)0x04B6, (q15_t)0x7FE9, (q15_t)0x0483, (q15_t)0x7FEB, + (q15_t)0x0451, (q15_t)0x7FED, (q15_t)0x041F, (q15_t)0x7FEE, + (q15_t)0x03ED, (q15_t)0x7FF0, (q15_t)0x03BA, (q15_t)0x7FF2, + (q15_t)0x0388, (q15_t)0x7FF3, (q15_t)0x0356, (q15_t)0x7FF4, + (q15_t)0x0324, (q15_t)0x7FF6, (q15_t)0x02F1, (q15_t)0x7FF7, + (q15_t)0x02BF, (q15_t)0x7FF8, (q15_t)0x028D, (q15_t)0x7FF9, + (q15_t)0x025B, (q15_t)0x7FFA, (q15_t)0x0228, (q15_t)0x7FFB, + (q15_t)0x01F6, (q15_t)0x7FFC, (q15_t)0x01C4, (q15_t)0x7FFC, + (q15_t)0x0192, (q15_t)0x7FFD, (q15_t)0x015F, (q15_t)0x7FFE, + (q15_t)0x012D, (q15_t)0x7FFE, (q15_t)0x00FB, (q15_t)0x7FFF, + (q15_t)0x00C9, (q15_t)0x7FFF, (q15_t)0x0096, (q15_t)0x7FFF, + (q15_t)0x0064, (q15_t)0x7FFF, (q15_t)0x0032, (q15_t)0x7FFF, + (q15_t)0x0000, (q15_t)0x7FFF, (q15_t)0xFFCD, (q15_t)0x7FFF, + (q15_t)0xFF9B, (q15_t)0x7FFF, (q15_t)0xFF69, (q15_t)0x7FFF, + (q15_t)0xFF36, (q15_t)0x7FFF, (q15_t)0xFF04, (q15_t)0x7FFF, + (q15_t)0xFED2, (q15_t)0x7FFE, (q15_t)0xFEA0, (q15_t)0x7FFE, + (q15_t)0xFE6D, (q15_t)0x7FFD, (q15_t)0xFE3B, (q15_t)0x7FFC, + (q15_t)0xFE09, (q15_t)0x7FFC, (q15_t)0xFDD7, (q15_t)0x7FFB, + (q15_t)0xFDA4, (q15_t)0x7FFA, (q15_t)0xFD72, (q15_t)0x7FF9, + (q15_t)0xFD40, (q15_t)0x7FF8, (q15_t)0xFD0E, (q15_t)0x7FF7, + (q15_t)0xFCDB, (q15_t)0x7FF6, (q15_t)0xFCA9, (q15_t)0x7FF4, + (q15_t)0xFC77, (q15_t)0x7FF3, (q15_t)0xFC45, (q15_t)0x7FF2, + (q15_t)0xFC12, (q15_t)0x7FF0, (q15_t)0xFBE0, (q15_t)0x7FEE, + (q15_t)0xFBAE, (q15_t)0x7FED, (q15_t)0xFB7C, (q15_t)0x7FEB, + (q15_t)0xFB49, (q15_t)0x7FE9, (q15_t)0xFB17, (q15_t)0x7FE7, + (q15_t)0xFAE5, (q15_t)0x7FE5, (q15_t)0xFAB3, (q15_t)0x7FE3, + (q15_t)0xFA80, (q15_t)0x7FE1, (q15_t)0xFA4E, (q15_t)0x7FDF, + (q15_t)0xFA1C, (q15_t)0x7FDD, (q15_t)0xF9EA, (q15_t)0x7FDA, + (q15_t)0xF9B8, (q15_t)0x7FD8, (q15_t)0xF985, (q15_t)0x7FD6, + (q15_t)0xF953, (q15_t)0x7FD3, (q15_t)0xF921, (q15_t)0x7FD0, + (q15_t)0xF8EF, (q15_t)0x7FCE, (q15_t)0xF8BD, (q15_t)0x7FCB, + (q15_t)0xF88A, (q15_t)0x7FC8, (q15_t)0xF858, (q15_t)0x7FC5, + (q15_t)0xF826, (q15_t)0x7FC2, (q15_t)0xF7F4, (q15_t)0x7FBF, + (q15_t)0xF7C2, (q15_t)0x7FBC, (q15_t)0xF790, (q15_t)0x7FB8, + (q15_t)0xF75D, (q15_t)0x7FB5, (q15_t)0xF72B, (q15_t)0x7FB1, + (q15_t)0xF6F9, (q15_t)0x7FAE, (q15_t)0xF6C7, (q15_t)0x7FAA, + (q15_t)0xF695, (q15_t)0x7FA7, (q15_t)0xF663, (q15_t)0x7FA3, + (q15_t)0xF631, (q15_t)0x7F9F, (q15_t)0xF5FF, (q15_t)0x7F9B, + (q15_t)0xF5CC, (q15_t)0x7F97, (q15_t)0xF59A, (q15_t)0x7F93, + (q15_t)0xF568, (q15_t)0x7F8F, (q15_t)0xF536, (q15_t)0x7F8B, + (q15_t)0xF504, (q15_t)0x7F87, (q15_t)0xF4D2, (q15_t)0x7F82, + (q15_t)0xF4A0, (q15_t)0x7F7E, (q15_t)0xF46E, (q15_t)0x7F79, + (q15_t)0xF43C, (q15_t)0x7F75, (q15_t)0xF40A, (q15_t)0x7F70, + (q15_t)0xF3D8, (q15_t)0x7F6B, (q15_t)0xF3A6, (q15_t)0x7F67, + (q15_t)0xF374, (q15_t)0x7F62, (q15_t)0xF342, (q15_t)0x7F5D, + (q15_t)0xF310, (q15_t)0x7F58, (q15_t)0xF2DE, (q15_t)0x7F53, + (q15_t)0xF2AC, (q15_t)0x7F4D, (q15_t)0xF27A, (q15_t)0x7F48, + (q15_t)0xF248, (q15_t)0x7F43, (q15_t)0xF216, (q15_t)0x7F3D, + (q15_t)0xF1E4, (q15_t)0x7F38, (q15_t)0xF1B2, (q15_t)0x7F32, + (q15_t)0xF180, (q15_t)0x7F2D, (q15_t)0xF14E, (q15_t)0x7F27, + (q15_t)0xF11C, (q15_t)0x7F21, (q15_t)0xF0EA, (q15_t)0x7F1B, + (q15_t)0xF0B8, (q15_t)0x7F15, (q15_t)0xF086, (q15_t)0x7F0F, + (q15_t)0xF054, (q15_t)0x7F09, (q15_t)0xF022, (q15_t)0x7F03, + (q15_t)0xEFF1, (q15_t)0x7EFD, (q15_t)0xEFBF, (q15_t)0x7EF6, + (q15_t)0xEF8D, (q15_t)0x7EF0, (q15_t)0xEF5B, (q15_t)0x7EE9, + (q15_t)0xEF29, (q15_t)0x7EE3, (q15_t)0xEEF7, (q15_t)0x7EDC, + (q15_t)0xEEC6, (q15_t)0x7ED5, (q15_t)0xEE94, (q15_t)0x7ECF, + (q15_t)0xEE62, (q15_t)0x7EC8, (q15_t)0xEE30, (q15_t)0x7EC1, + (q15_t)0xEDFE, (q15_t)0x7EBA, (q15_t)0xEDCD, (q15_t)0x7EB3, + (q15_t)0xED9B, (q15_t)0x7EAB, (q15_t)0xED69, (q15_t)0x7EA4, + (q15_t)0xED37, (q15_t)0x7E9D, (q15_t)0xED06, (q15_t)0x7E95, + (q15_t)0xECD4, (q15_t)0x7E8E, (q15_t)0xECA2, (q15_t)0x7E86, + (q15_t)0xEC71, (q15_t)0x7E7F, (q15_t)0xEC3F, (q15_t)0x7E77, + (q15_t)0xEC0D, (q15_t)0x7E6F, (q15_t)0xEBDC, (q15_t)0x7E67, + (q15_t)0xEBAA, (q15_t)0x7E5F, (q15_t)0xEB78, (q15_t)0x7E57, + (q15_t)0xEB47, (q15_t)0x7E4F, (q15_t)0xEB15, (q15_t)0x7E47, + (q15_t)0xEAE4, (q15_t)0x7E3F, (q15_t)0xEAB2, (q15_t)0x7E37, + (q15_t)0xEA80, (q15_t)0x7E2E, (q15_t)0xEA4F, (q15_t)0x7E26, + (q15_t)0xEA1D, (q15_t)0x7E1D, (q15_t)0xE9EC, (q15_t)0x7E14, + (q15_t)0xE9BA, (q15_t)0x7E0C, (q15_t)0xE989, (q15_t)0x7E03, + (q15_t)0xE957, (q15_t)0x7DFA, (q15_t)0xE926, (q15_t)0x7DF1, + (q15_t)0xE8F5, (q15_t)0x7DE8, (q15_t)0xE8C3, (q15_t)0x7DDF, + (q15_t)0xE892, (q15_t)0x7DD6, (q15_t)0xE860, (q15_t)0x7DCD, + (q15_t)0xE82F, (q15_t)0x7DC3, (q15_t)0xE7FD, (q15_t)0x7DBA, + (q15_t)0xE7CC, (q15_t)0x7DB0, (q15_t)0xE79B, (q15_t)0x7DA7, + (q15_t)0xE769, (q15_t)0x7D9D, (q15_t)0xE738, (q15_t)0x7D94, + (q15_t)0xE707, (q15_t)0x7D8A, (q15_t)0xE6D5, (q15_t)0x7D80, + (q15_t)0xE6A4, (q15_t)0x7D76, (q15_t)0xE673, (q15_t)0x7D6C, + (q15_t)0xE642, (q15_t)0x7D62, (q15_t)0xE610, (q15_t)0x7D58, + (q15_t)0xE5DF, (q15_t)0x7D4E, (q15_t)0xE5AE, (q15_t)0x7D43, + (q15_t)0xE57D, (q15_t)0x7D39, (q15_t)0xE54C, (q15_t)0x7D2F, + (q15_t)0xE51B, (q15_t)0x7D24, (q15_t)0xE4E9, (q15_t)0x7D19, + (q15_t)0xE4B8, (q15_t)0x7D0F, (q15_t)0xE487, (q15_t)0x7D04, + (q15_t)0xE456, (q15_t)0x7CF9, (q15_t)0xE425, (q15_t)0x7CEE, + (q15_t)0xE3F4, (q15_t)0x7CE3, (q15_t)0xE3C3, (q15_t)0x7CD8, + (q15_t)0xE392, (q15_t)0x7CCD, (q15_t)0xE361, (q15_t)0x7CC2, + (q15_t)0xE330, (q15_t)0x7CB7, (q15_t)0xE2FF, (q15_t)0x7CAB, + (q15_t)0xE2CE, (q15_t)0x7CA0, (q15_t)0xE29D, (q15_t)0x7C94, + (q15_t)0xE26C, (q15_t)0x7C89, (q15_t)0xE23B, (q15_t)0x7C7D, + (q15_t)0xE20A, (q15_t)0x7C71, (q15_t)0xE1DA, (q15_t)0x7C66, + (q15_t)0xE1A9, (q15_t)0x7C5A, (q15_t)0xE178, (q15_t)0x7C4E, + (q15_t)0xE147, (q15_t)0x7C42, (q15_t)0xE116, (q15_t)0x7C36, + (q15_t)0xE0E6, (q15_t)0x7C29, (q15_t)0xE0B5, (q15_t)0x7C1D, + (q15_t)0xE084, (q15_t)0x7C11, (q15_t)0xE053, (q15_t)0x7C05, + (q15_t)0xE023, (q15_t)0x7BF8, (q15_t)0xDFF2, (q15_t)0x7BEB, + (q15_t)0xDFC1, (q15_t)0x7BDF, (q15_t)0xDF91, (q15_t)0x7BD2, + (q15_t)0xDF60, (q15_t)0x7BC5, (q15_t)0xDF2F, (q15_t)0x7BB9, + (q15_t)0xDEFF, (q15_t)0x7BAC, (q15_t)0xDECE, (q15_t)0x7B9F, + (q15_t)0xDE9E, (q15_t)0x7B92, (q15_t)0xDE6D, (q15_t)0x7B84, + (q15_t)0xDE3D, (q15_t)0x7B77, (q15_t)0xDE0C, (q15_t)0x7B6A, + (q15_t)0xDDDC, (q15_t)0x7B5D, (q15_t)0xDDAB, (q15_t)0x7B4F, + (q15_t)0xDD7B, (q15_t)0x7B42, (q15_t)0xDD4B, (q15_t)0x7B34, + (q15_t)0xDD1A, (q15_t)0x7B26, (q15_t)0xDCEA, (q15_t)0x7B19, + (q15_t)0xDCBA, (q15_t)0x7B0B, (q15_t)0xDC89, (q15_t)0x7AFD, + (q15_t)0xDC59, (q15_t)0x7AEF, (q15_t)0xDC29, (q15_t)0x7AE1, + (q15_t)0xDBF8, (q15_t)0x7AD3, (q15_t)0xDBC8, (q15_t)0x7AC5, + (q15_t)0xDB98, (q15_t)0x7AB6, (q15_t)0xDB68, (q15_t)0x7AA8, + (q15_t)0xDB38, (q15_t)0x7A9A, (q15_t)0xDB08, (q15_t)0x7A8B, + (q15_t)0xDAD7, (q15_t)0x7A7D, (q15_t)0xDAA7, (q15_t)0x7A6E, + (q15_t)0xDA77, (q15_t)0x7A5F, (q15_t)0xDA47, (q15_t)0x7A50, + (q15_t)0xDA17, (q15_t)0x7A42, (q15_t)0xD9E7, (q15_t)0x7A33, + (q15_t)0xD9B7, (q15_t)0x7A24, (q15_t)0xD987, (q15_t)0x7A15, + (q15_t)0xD957, (q15_t)0x7A05, (q15_t)0xD927, (q15_t)0x79F6, + (q15_t)0xD8F8, (q15_t)0x79E7, (q15_t)0xD8C8, (q15_t)0x79D8, + (q15_t)0xD898, (q15_t)0x79C8, (q15_t)0xD868, (q15_t)0x79B9, + (q15_t)0xD838, (q15_t)0x79A9, (q15_t)0xD809, (q15_t)0x7999, + (q15_t)0xD7D9, (q15_t)0x798A, (q15_t)0xD7A9, (q15_t)0x797A, + (q15_t)0xD779, (q15_t)0x796A, (q15_t)0xD74A, (q15_t)0x795A, + (q15_t)0xD71A, (q15_t)0x794A, (q15_t)0xD6EA, (q15_t)0x793A, + (q15_t)0xD6BB, (q15_t)0x792A, (q15_t)0xD68B, (q15_t)0x7919, + (q15_t)0xD65C, (q15_t)0x7909, (q15_t)0xD62C, (q15_t)0x78F9, + (q15_t)0xD5FD, (q15_t)0x78E8, (q15_t)0xD5CD, (q15_t)0x78D8, + (q15_t)0xD59E, (q15_t)0x78C7, (q15_t)0xD56E, (q15_t)0x78B6, + (q15_t)0xD53F, (q15_t)0x78A6, (q15_t)0xD510, (q15_t)0x7895, + (q15_t)0xD4E0, (q15_t)0x7884, (q15_t)0xD4B1, (q15_t)0x7873, + (q15_t)0xD482, (q15_t)0x7862, (q15_t)0xD452, (q15_t)0x7851, + (q15_t)0xD423, (q15_t)0x7840, (q15_t)0xD3F4, (q15_t)0x782E, + (q15_t)0xD3C5, (q15_t)0x781D, (q15_t)0xD396, (q15_t)0x780C, + (q15_t)0xD367, (q15_t)0x77FA, (q15_t)0xD337, (q15_t)0x77E9, + (q15_t)0xD308, (q15_t)0x77D7, (q15_t)0xD2D9, (q15_t)0x77C5, + (q15_t)0xD2AA, (q15_t)0x77B4, (q15_t)0xD27B, (q15_t)0x77A2, + (q15_t)0xD24C, (q15_t)0x7790, (q15_t)0xD21D, (q15_t)0x777E, + (q15_t)0xD1EE, (q15_t)0x776C, (q15_t)0xD1C0, (q15_t)0x775A, + (q15_t)0xD191, (q15_t)0x7747, (q15_t)0xD162, (q15_t)0x7735, + (q15_t)0xD133, (q15_t)0x7723, (q15_t)0xD104, (q15_t)0x7710, + (q15_t)0xD0D6, (q15_t)0x76FE, (q15_t)0xD0A7, (q15_t)0x76EB, + (q15_t)0xD078, (q15_t)0x76D9, (q15_t)0xD04A, (q15_t)0x76C6, + (q15_t)0xD01B, (q15_t)0x76B3, (q15_t)0xCFEC, (q15_t)0x76A0, + (q15_t)0xCFBE, (q15_t)0x768E, (q15_t)0xCF8F, (q15_t)0x767B, + (q15_t)0xCF61, (q15_t)0x7668, (q15_t)0xCF32, (q15_t)0x7654, + (q15_t)0xCF04, (q15_t)0x7641, (q15_t)0xCED5, (q15_t)0x762E, + (q15_t)0xCEA7, (q15_t)0x761B, (q15_t)0xCE79, (q15_t)0x7607, + (q15_t)0xCE4A, (q15_t)0x75F4, (q15_t)0xCE1C, (q15_t)0x75E0, + (q15_t)0xCDEE, (q15_t)0x75CC, (q15_t)0xCDBF, (q15_t)0x75B9, + (q15_t)0xCD91, (q15_t)0x75A5, (q15_t)0xCD63, (q15_t)0x7591, + (q15_t)0xCD35, (q15_t)0x757D, (q15_t)0xCD07, (q15_t)0x7569, + (q15_t)0xCCD9, (q15_t)0x7555, (q15_t)0xCCAB, (q15_t)0x7541, + (q15_t)0xCC7D, (q15_t)0x752D, (q15_t)0xCC4F, (q15_t)0x7519, + (q15_t)0xCC21, (q15_t)0x7504, (q15_t)0xCBF3, (q15_t)0x74F0, + (q15_t)0xCBC5, (q15_t)0x74DB, (q15_t)0xCB97, (q15_t)0x74C7, + (q15_t)0xCB69, (q15_t)0x74B2, (q15_t)0xCB3B, (q15_t)0x749E, + (q15_t)0xCB0D, (q15_t)0x7489, (q15_t)0xCAE0, (q15_t)0x7474, + (q15_t)0xCAB2, (q15_t)0x745F, (q15_t)0xCA84, (q15_t)0x744A, + (q15_t)0xCA57, (q15_t)0x7435, (q15_t)0xCA29, (q15_t)0x7420, + (q15_t)0xC9FB, (q15_t)0x740B, (q15_t)0xC9CE, (q15_t)0x73F6, + (q15_t)0xC9A0, (q15_t)0x73E0, (q15_t)0xC973, (q15_t)0x73CB, + (q15_t)0xC945, (q15_t)0x73B5, (q15_t)0xC918, (q15_t)0x73A0, + (q15_t)0xC8EB, (q15_t)0x738A, (q15_t)0xC8BD, (q15_t)0x7375, + (q15_t)0xC890, (q15_t)0x735F, (q15_t)0xC863, (q15_t)0x7349, + (q15_t)0xC835, (q15_t)0x7333, (q15_t)0xC808, (q15_t)0x731D, + (q15_t)0xC7DB, (q15_t)0x7307, (q15_t)0xC7AE, (q15_t)0x72F1, + (q15_t)0xC781, (q15_t)0x72DB, (q15_t)0xC754, (q15_t)0x72C5, + (q15_t)0xC727, (q15_t)0x72AF, (q15_t)0xC6F9, (q15_t)0x7298, + (q15_t)0xC6CD, (q15_t)0x7282, (q15_t)0xC6A0, (q15_t)0x726B, + (q15_t)0xC673, (q15_t)0x7255, (q15_t)0xC646, (q15_t)0x723E, + (q15_t)0xC619, (q15_t)0x7227, (q15_t)0xC5EC, (q15_t)0x7211, + (q15_t)0xC5BF, (q15_t)0x71FA, (q15_t)0xC593, (q15_t)0x71E3, + (q15_t)0xC566, (q15_t)0x71CC, (q15_t)0xC539, (q15_t)0x71B5, + (q15_t)0xC50D, (q15_t)0x719E, (q15_t)0xC4E0, (q15_t)0x7186, + (q15_t)0xC4B3, (q15_t)0x716F, (q15_t)0xC487, (q15_t)0x7158, + (q15_t)0xC45A, (q15_t)0x7141, (q15_t)0xC42E, (q15_t)0x7129, + (q15_t)0xC402, (q15_t)0x7112, (q15_t)0xC3D5, (q15_t)0x70FA, + (q15_t)0xC3A9, (q15_t)0x70E2, (q15_t)0xC37C, (q15_t)0x70CB, + (q15_t)0xC350, (q15_t)0x70B3, (q15_t)0xC324, (q15_t)0x709B, + (q15_t)0xC2F8, (q15_t)0x7083, (q15_t)0xC2CC, (q15_t)0x706B, + (q15_t)0xC29F, (q15_t)0x7053, (q15_t)0xC273, (q15_t)0x703B, + (q15_t)0xC247, (q15_t)0x7023, (q15_t)0xC21B, (q15_t)0x700A, + (q15_t)0xC1EF, (q15_t)0x6FF2, (q15_t)0xC1C3, (q15_t)0x6FDA, + (q15_t)0xC197, (q15_t)0x6FC1, (q15_t)0xC16C, (q15_t)0x6FA9, + (q15_t)0xC140, (q15_t)0x6F90, (q15_t)0xC114, (q15_t)0x6F77, + (q15_t)0xC0E8, (q15_t)0x6F5F, (q15_t)0xC0BC, (q15_t)0x6F46, + (q15_t)0xC091, (q15_t)0x6F2D, (q15_t)0xC065, (q15_t)0x6F14, + (q15_t)0xC03A, (q15_t)0x6EFB, (q15_t)0xC00E, (q15_t)0x6EE2, + (q15_t)0xBFE2, (q15_t)0x6EC9, (q15_t)0xBFB7, (q15_t)0x6EAF, + (q15_t)0xBF8C, (q15_t)0x6E96, (q15_t)0xBF60, (q15_t)0x6E7D, + (q15_t)0xBF35, (q15_t)0x6E63, (q15_t)0xBF09, (q15_t)0x6E4A, + (q15_t)0xBEDE, (q15_t)0x6E30, (q15_t)0xBEB3, (q15_t)0x6E17, + (q15_t)0xBE88, (q15_t)0x6DFD, (q15_t)0xBE5D, (q15_t)0x6DE3, + (q15_t)0xBE31, (q15_t)0x6DCA, (q15_t)0xBE06, (q15_t)0x6DB0, + (q15_t)0xBDDB, (q15_t)0x6D96, (q15_t)0xBDB0, (q15_t)0x6D7C, + (q15_t)0xBD85, (q15_t)0x6D62, (q15_t)0xBD5A, (q15_t)0x6D48, + (q15_t)0xBD2F, (q15_t)0x6D2D, (q15_t)0xBD05, (q15_t)0x6D13, + (q15_t)0xBCDA, (q15_t)0x6CF9, (q15_t)0xBCAF, (q15_t)0x6CDE, + (q15_t)0xBC84, (q15_t)0x6CC4, (q15_t)0xBC5A, (q15_t)0x6CA9, + (q15_t)0xBC2F, (q15_t)0x6C8F, (q15_t)0xBC04, (q15_t)0x6C74, + (q15_t)0xBBDA, (q15_t)0x6C59, (q15_t)0xBBAF, (q15_t)0x6C3F, + (q15_t)0xBB85, (q15_t)0x6C24, (q15_t)0xBB5A, (q15_t)0x6C09, + (q15_t)0xBB30, (q15_t)0x6BEE, (q15_t)0xBB05, (q15_t)0x6BD3, + (q15_t)0xBADB, (q15_t)0x6BB8, (q15_t)0xBAB1, (q15_t)0x6B9C, + (q15_t)0xBA87, (q15_t)0x6B81, (q15_t)0xBA5C, (q15_t)0x6B66, + (q15_t)0xBA32, (q15_t)0x6B4A, (q15_t)0xBA08, (q15_t)0x6B2F, + (q15_t)0xB9DE, (q15_t)0x6B13, (q15_t)0xB9B4, (q15_t)0x6AF8, + (q15_t)0xB98A, (q15_t)0x6ADC, (q15_t)0xB960, (q15_t)0x6AC1, + (q15_t)0xB936, (q15_t)0x6AA5, (q15_t)0xB90C, (q15_t)0x6A89, + (q15_t)0xB8E3, (q15_t)0x6A6D, (q15_t)0xB8B9, (q15_t)0x6A51, + (q15_t)0xB88F, (q15_t)0x6A35, (q15_t)0xB865, (q15_t)0x6A19, + (q15_t)0xB83C, (q15_t)0x69FD, (q15_t)0xB812, (q15_t)0x69E1, + (q15_t)0xB7E9, (q15_t)0x69C4, (q15_t)0xB7BF, (q15_t)0x69A8, + (q15_t)0xB796, (q15_t)0x698C, (q15_t)0xB76C, (q15_t)0x696F, + (q15_t)0xB743, (q15_t)0x6953, (q15_t)0xB719, (q15_t)0x6936, + (q15_t)0xB6F0, (q15_t)0x6919, (q15_t)0xB6C7, (q15_t)0x68FD, + (q15_t)0xB69E, (q15_t)0x68E0, (q15_t)0xB675, (q15_t)0x68C3, + (q15_t)0xB64B, (q15_t)0x68A6, (q15_t)0xB622, (q15_t)0x6889, + (q15_t)0xB5F9, (q15_t)0x686C, (q15_t)0xB5D0, (q15_t)0x684F, + (q15_t)0xB5A7, (q15_t)0x6832, (q15_t)0xB57E, (q15_t)0x6815, + (q15_t)0xB556, (q15_t)0x67F7, (q15_t)0xB52D, (q15_t)0x67DA, + (q15_t)0xB504, (q15_t)0x67BD, (q15_t)0xB4DB, (q15_t)0x679F, + (q15_t)0xB4B3, (q15_t)0x6782, (q15_t)0xB48A, (q15_t)0x6764, + (q15_t)0xB461, (q15_t)0x6746, (q15_t)0xB439, (q15_t)0x6729, + (q15_t)0xB410, (q15_t)0x670B, (q15_t)0xB3E8, (q15_t)0x66ED, + (q15_t)0xB3C0, (q15_t)0x66CF, (q15_t)0xB397, (q15_t)0x66B1, + (q15_t)0xB36F, (q15_t)0x6693, (q15_t)0xB347, (q15_t)0x6675, + (q15_t)0xB31E, (q15_t)0x6657, (q15_t)0xB2F6, (q15_t)0x6639, + (q15_t)0xB2CE, (q15_t)0x661A, (q15_t)0xB2A6, (q15_t)0x65FC, + (q15_t)0xB27E, (q15_t)0x65DD, (q15_t)0xB256, (q15_t)0x65BF, + (q15_t)0xB22E, (q15_t)0x65A0, (q15_t)0xB206, (q15_t)0x6582, + (q15_t)0xB1DE, (q15_t)0x6563, (q15_t)0xB1B7, (q15_t)0x6545, + (q15_t)0xB18F, (q15_t)0x6526, (q15_t)0xB167, (q15_t)0x6507, + (q15_t)0xB140, (q15_t)0x64E8, (q15_t)0xB118, (q15_t)0x64C9, + (q15_t)0xB0F0, (q15_t)0x64AA, (q15_t)0xB0C9, (q15_t)0x648B, + (q15_t)0xB0A1, (q15_t)0x646C, (q15_t)0xB07A, (q15_t)0x644D, + (q15_t)0xB053, (q15_t)0x642D, (q15_t)0xB02B, (q15_t)0x640E, + (q15_t)0xB004, (q15_t)0x63EF, (q15_t)0xAFDD, (q15_t)0x63CF, + (q15_t)0xAFB6, (q15_t)0x63B0, (q15_t)0xAF8F, (q15_t)0x6390, + (q15_t)0xAF68, (q15_t)0x6371, (q15_t)0xAF40, (q15_t)0x6351, + (q15_t)0xAF1A, (q15_t)0x6331, (q15_t)0xAEF3, (q15_t)0x6311, + (q15_t)0xAECC, (q15_t)0x62F2, (q15_t)0xAEA5, (q15_t)0x62D2, + (q15_t)0xAE7E, (q15_t)0x62B2, (q15_t)0xAE57, (q15_t)0x6292, + (q15_t)0xAE31, (q15_t)0x6271, (q15_t)0xAE0A, (q15_t)0x6251, + (q15_t)0xADE3, (q15_t)0x6231, (q15_t)0xADBD, (q15_t)0x6211, + (q15_t)0xAD96, (q15_t)0x61F1, (q15_t)0xAD70, (q15_t)0x61D0, + (q15_t)0xAD4A, (q15_t)0x61B0, (q15_t)0xAD23, (q15_t)0x618F, + (q15_t)0xACFD, (q15_t)0x616F, (q15_t)0xACD7, (q15_t)0x614E, + (q15_t)0xACB1, (q15_t)0x612D, (q15_t)0xAC8A, (q15_t)0x610D, + (q15_t)0xAC64, (q15_t)0x60EC, (q15_t)0xAC3E, (q15_t)0x60CB, + (q15_t)0xAC18, (q15_t)0x60AA, (q15_t)0xABF2, (q15_t)0x6089, + (q15_t)0xABCC, (q15_t)0x6068, (q15_t)0xABA7, (q15_t)0x6047, + (q15_t)0xAB81, (q15_t)0x6026, (q15_t)0xAB5B, (q15_t)0x6004, + (q15_t)0xAB35, (q15_t)0x5FE3, (q15_t)0xAB10, (q15_t)0x5FC2, + (q15_t)0xAAEA, (q15_t)0x5FA0, (q15_t)0xAAC5, (q15_t)0x5F7F, + (q15_t)0xAA9F, (q15_t)0x5F5E, (q15_t)0xAA7A, (q15_t)0x5F3C, + (q15_t)0xAA54, (q15_t)0x5F1A, (q15_t)0xAA2F, (q15_t)0x5EF9, + (q15_t)0xAA0A, (q15_t)0x5ED7, (q15_t)0xA9E5, (q15_t)0x5EB5, + (q15_t)0xA9BF, (q15_t)0x5E93, (q15_t)0xA99A, (q15_t)0x5E71, + (q15_t)0xA975, (q15_t)0x5E50, (q15_t)0xA950, (q15_t)0x5E2D, + (q15_t)0xA92B, (q15_t)0x5E0B, (q15_t)0xA906, (q15_t)0x5DE9, + (q15_t)0xA8E2, (q15_t)0x5DC7, (q15_t)0xA8BD, (q15_t)0x5DA5, + (q15_t)0xA898, (q15_t)0x5D83, (q15_t)0xA873, (q15_t)0x5D60, + (q15_t)0xA84F, (q15_t)0x5D3E, (q15_t)0xA82A, (q15_t)0x5D1B, + (q15_t)0xA806, (q15_t)0x5CF9, (q15_t)0xA7E1, (q15_t)0x5CD6, + (q15_t)0xA7BD, (q15_t)0x5CB4, (q15_t)0xA798, (q15_t)0x5C91, + (q15_t)0xA774, (q15_t)0x5C6E, (q15_t)0xA750, (q15_t)0x5C4B, + (q15_t)0xA72B, (q15_t)0x5C29, (q15_t)0xA707, (q15_t)0x5C06, + (q15_t)0xA6E3, (q15_t)0x5BE3, (q15_t)0xA6BF, (q15_t)0x5BC0, + (q15_t)0xA69B, (q15_t)0x5B9D, (q15_t)0xA677, (q15_t)0x5B79, + (q15_t)0xA653, (q15_t)0x5B56, (q15_t)0xA62F, (q15_t)0x5B33, + (q15_t)0xA60C, (q15_t)0x5B10, (q15_t)0xA5E8, (q15_t)0x5AEC, + (q15_t)0xA5C4, (q15_t)0x5AC9, (q15_t)0xA5A1, (q15_t)0x5AA5, + (q15_t)0xA57D, (q15_t)0x5A82, (q15_t)0xA55A, (q15_t)0x5A5E, + (q15_t)0xA536, (q15_t)0x5A3B, (q15_t)0xA513, (q15_t)0x5A17, + (q15_t)0xA4EF, (q15_t)0x59F3, (q15_t)0xA4CC, (q15_t)0x59D0, + (q15_t)0xA4A9, (q15_t)0x59AC, (q15_t)0xA486, (q15_t)0x5988, + (q15_t)0xA462, (q15_t)0x5964, (q15_t)0xA43F, (q15_t)0x5940, + (q15_t)0xA41C, (q15_t)0x591C, (q15_t)0xA3F9, (q15_t)0x58F8, + (q15_t)0xA3D6, (q15_t)0x58D4, (q15_t)0xA3B4, (q15_t)0x58AF, + (q15_t)0xA391, (q15_t)0x588B, (q15_t)0xA36E, (q15_t)0x5867, + (q15_t)0xA34B, (q15_t)0x5842, (q15_t)0xA329, (q15_t)0x581E, + (q15_t)0xA306, (q15_t)0x57F9, (q15_t)0xA2E4, (q15_t)0x57D5, + (q15_t)0xA2C1, (q15_t)0x57B0, (q15_t)0xA29F, (q15_t)0x578C, + (q15_t)0xA27C, (q15_t)0x5767, (q15_t)0xA25A, (q15_t)0x5742, + (q15_t)0xA238, (q15_t)0x571D, (q15_t)0xA216, (q15_t)0x56F9, + (q15_t)0xA1F4, (q15_t)0x56D4, (q15_t)0xA1D2, (q15_t)0x56AF, + (q15_t)0xA1AF, (q15_t)0x568A, (q15_t)0xA18E, (q15_t)0x5665, + (q15_t)0xA16C, (q15_t)0x5640, (q15_t)0xA14A, (q15_t)0x561A, + (q15_t)0xA128, (q15_t)0x55F5, (q15_t)0xA106, (q15_t)0x55D0, + (q15_t)0xA0E5, (q15_t)0x55AB, (q15_t)0xA0C3, (q15_t)0x5585, + (q15_t)0xA0A1, (q15_t)0x5560, (q15_t)0xA080, (q15_t)0x553A, + (q15_t)0xA05F, (q15_t)0x5515, (q15_t)0xA03D, (q15_t)0x54EF, + (q15_t)0xA01C, (q15_t)0x54CA, (q15_t)0x9FFB, (q15_t)0x54A4, + (q15_t)0x9FD9, (q15_t)0x547E, (q15_t)0x9FB8, (q15_t)0x5458, + (q15_t)0x9F97, (q15_t)0x5433, (q15_t)0x9F76, (q15_t)0x540D, + (q15_t)0x9F55, (q15_t)0x53E7, (q15_t)0x9F34, (q15_t)0x53C1, + (q15_t)0x9F13, (q15_t)0x539B, (q15_t)0x9EF2, (q15_t)0x5375, + (q15_t)0x9ED2, (q15_t)0x534E, (q15_t)0x9EB1, (q15_t)0x5328, + (q15_t)0x9E90, (q15_t)0x5302, (q15_t)0x9E70, (q15_t)0x52DC, + (q15_t)0x9E4F, (q15_t)0x52B5, (q15_t)0x9E2F, (q15_t)0x528F, + (q15_t)0x9E0E, (q15_t)0x5269, (q15_t)0x9DEE, (q15_t)0x5242, + (q15_t)0x9DCE, (q15_t)0x521C, (q15_t)0x9DAE, (q15_t)0x51F5, + (q15_t)0x9D8E, (q15_t)0x51CE, (q15_t)0x9D6D, (q15_t)0x51A8, + (q15_t)0x9D4D, (q15_t)0x5181, (q15_t)0x9D2D, (q15_t)0x515A, + (q15_t)0x9D0D, (q15_t)0x5133, (q15_t)0x9CEE, (q15_t)0x510C, + (q15_t)0x9CCE, (q15_t)0x50E5, (q15_t)0x9CAE, (q15_t)0x50BF, + (q15_t)0x9C8E, (q15_t)0x5097, (q15_t)0x9C6F, (q15_t)0x5070, + (q15_t)0x9C4F, (q15_t)0x5049, (q15_t)0x9C30, (q15_t)0x5022, + (q15_t)0x9C10, (q15_t)0x4FFB, (q15_t)0x9BF1, (q15_t)0x4FD4, + (q15_t)0x9BD2, (q15_t)0x4FAC, (q15_t)0x9BB2, (q15_t)0x4F85, + (q15_t)0x9B93, (q15_t)0x4F5E, (q15_t)0x9B74, (q15_t)0x4F36, + (q15_t)0x9B55, (q15_t)0x4F0F, (q15_t)0x9B36, (q15_t)0x4EE7, + (q15_t)0x9B17, (q15_t)0x4EBF, (q15_t)0x9AF8, (q15_t)0x4E98, + (q15_t)0x9AD9, (q15_t)0x4E70, (q15_t)0x9ABA, (q15_t)0x4E48, + (q15_t)0x9A9C, (q15_t)0x4E21, (q15_t)0x9A7D, (q15_t)0x4DF9, + (q15_t)0x9A5F, (q15_t)0x4DD1, (q15_t)0x9A40, (q15_t)0x4DA9, + (q15_t)0x9A22, (q15_t)0x4D81, (q15_t)0x9A03, (q15_t)0x4D59, + (q15_t)0x99E5, (q15_t)0x4D31, (q15_t)0x99C6, (q15_t)0x4D09, + (q15_t)0x99A8, (q15_t)0x4CE1, (q15_t)0x998A, (q15_t)0x4CB8, + (q15_t)0x996C, (q15_t)0x4C90, (q15_t)0x994E, (q15_t)0x4C68, + (q15_t)0x9930, (q15_t)0x4C3F, (q15_t)0x9912, (q15_t)0x4C17, + (q15_t)0x98F4, (q15_t)0x4BEF, (q15_t)0x98D6, (q15_t)0x4BC6, + (q15_t)0x98B9, (q15_t)0x4B9E, (q15_t)0x989B, (q15_t)0x4B75, + (q15_t)0x987D, (q15_t)0x4B4C, (q15_t)0x9860, (q15_t)0x4B24, + (q15_t)0x9842, (q15_t)0x4AFB, (q15_t)0x9825, (q15_t)0x4AD2, + (q15_t)0x9808, (q15_t)0x4AA9, (q15_t)0x97EA, (q15_t)0x4A81, + (q15_t)0x97CD, (q15_t)0x4A58, (q15_t)0x97B0, (q15_t)0x4A2F, + (q15_t)0x9793, (q15_t)0x4A06, (q15_t)0x9776, (q15_t)0x49DD, + (q15_t)0x9759, (q15_t)0x49B4, (q15_t)0x973C, (q15_t)0x498A, + (q15_t)0x971F, (q15_t)0x4961, (q15_t)0x9702, (q15_t)0x4938, + (q15_t)0x96E6, (q15_t)0x490F, (q15_t)0x96C9, (q15_t)0x48E6, + (q15_t)0x96AC, (q15_t)0x48BC, (q15_t)0x9690, (q15_t)0x4893, + (q15_t)0x9673, (q15_t)0x4869, (q15_t)0x9657, (q15_t)0x4840, + (q15_t)0x963B, (q15_t)0x4816, (q15_t)0x961E, (q15_t)0x47ED, + (q15_t)0x9602, (q15_t)0x47C3, (q15_t)0x95E6, (q15_t)0x479A, + (q15_t)0x95CA, (q15_t)0x4770, (q15_t)0x95AE, (q15_t)0x4746, + (q15_t)0x9592, (q15_t)0x471C, (q15_t)0x9576, (q15_t)0x46F3, + (q15_t)0x955A, (q15_t)0x46C9, (q15_t)0x953E, (q15_t)0x469F, + (q15_t)0x9523, (q15_t)0x4675, (q15_t)0x9507, (q15_t)0x464B, + (q15_t)0x94EC, (q15_t)0x4621, (q15_t)0x94D0, (q15_t)0x45F7, + (q15_t)0x94B5, (q15_t)0x45CD, (q15_t)0x9499, (q15_t)0x45A3, + (q15_t)0x947E, (q15_t)0x4578, (q15_t)0x9463, (q15_t)0x454E, + (q15_t)0x9447, (q15_t)0x4524, (q15_t)0x942C, (q15_t)0x44FA, + (q15_t)0x9411, (q15_t)0x44CF, (q15_t)0x93F6, (q15_t)0x44A5, + (q15_t)0x93DB, (q15_t)0x447A, (q15_t)0x93C0, (q15_t)0x4450, + (q15_t)0x93A6, (q15_t)0x4425, (q15_t)0x938B, (q15_t)0x43FB, + (q15_t)0x9370, (q15_t)0x43D0, (q15_t)0x9356, (q15_t)0x43A5, + (q15_t)0x933B, (q15_t)0x437B, (q15_t)0x9321, (q15_t)0x4350, + (q15_t)0x9306, (q15_t)0x4325, (q15_t)0x92EC, (q15_t)0x42FA, + (q15_t)0x92D2, (q15_t)0x42D0, (q15_t)0x92B7, (q15_t)0x42A5, + (q15_t)0x929D, (q15_t)0x427A, (q15_t)0x9283, (q15_t)0x424F, + (q15_t)0x9269, (q15_t)0x4224, (q15_t)0x924F, (q15_t)0x41F9, + (q15_t)0x9235, (q15_t)0x41CE, (q15_t)0x921C, (q15_t)0x41A2, + (q15_t)0x9202, (q15_t)0x4177, (q15_t)0x91E8, (q15_t)0x414C, + (q15_t)0x91CF, (q15_t)0x4121, (q15_t)0x91B5, (q15_t)0x40F6, + (q15_t)0x919C, (q15_t)0x40CA, (q15_t)0x9182, (q15_t)0x409F, + (q15_t)0x9169, (q15_t)0x4073, (q15_t)0x9150, (q15_t)0x4048, + (q15_t)0x9136, (q15_t)0x401D, (q15_t)0x911D, (q15_t)0x3FF1, + (q15_t)0x9104, (q15_t)0x3FC5, (q15_t)0x90EB, (q15_t)0x3F9A, + (q15_t)0x90D2, (q15_t)0x3F6E, (q15_t)0x90B9, (q15_t)0x3F43, + (q15_t)0x90A0, (q15_t)0x3F17, (q15_t)0x9088, (q15_t)0x3EEB, + (q15_t)0x906F, (q15_t)0x3EBF, (q15_t)0x9056, (q15_t)0x3E93, + (q15_t)0x903E, (q15_t)0x3E68, (q15_t)0x9025, (q15_t)0x3E3C, + (q15_t)0x900D, (q15_t)0x3E10, (q15_t)0x8FF5, (q15_t)0x3DE4, + (q15_t)0x8FDC, (q15_t)0x3DB8, (q15_t)0x8FC4, (q15_t)0x3D8C, + (q15_t)0x8FAC, (q15_t)0x3D60, (q15_t)0x8F94, (q15_t)0x3D33, + (q15_t)0x8F7C, (q15_t)0x3D07, (q15_t)0x8F64, (q15_t)0x3CDB, + (q15_t)0x8F4C, (q15_t)0x3CAF, (q15_t)0x8F34, (q15_t)0x3C83, + (q15_t)0x8F1D, (q15_t)0x3C56, (q15_t)0x8F05, (q15_t)0x3C2A, + (q15_t)0x8EED, (q15_t)0x3BFD, (q15_t)0x8ED6, (q15_t)0x3BD1, + (q15_t)0x8EBE, (q15_t)0x3BA5, (q15_t)0x8EA7, (q15_t)0x3B78, + (q15_t)0x8E90, (q15_t)0x3B4C, (q15_t)0x8E79, (q15_t)0x3B1F, + (q15_t)0x8E61, (q15_t)0x3AF2, (q15_t)0x8E4A, (q15_t)0x3AC6, + (q15_t)0x8E33, (q15_t)0x3A99, (q15_t)0x8E1C, (q15_t)0x3A6C, + (q15_t)0x8E05, (q15_t)0x3A40, (q15_t)0x8DEE, (q15_t)0x3A13, + (q15_t)0x8DD8, (q15_t)0x39E6, (q15_t)0x8DC1, (q15_t)0x39B9, + (q15_t)0x8DAA, (q15_t)0x398C, (q15_t)0x8D94, (q15_t)0x395F, + (q15_t)0x8D7D, (q15_t)0x3932, (q15_t)0x8D67, (q15_t)0x3906, + (q15_t)0x8D50, (q15_t)0x38D8, (q15_t)0x8D3A, (q15_t)0x38AB, + (q15_t)0x8D24, (q15_t)0x387E, (q15_t)0x8D0E, (q15_t)0x3851, + (q15_t)0x8CF8, (q15_t)0x3824, (q15_t)0x8CE2, (q15_t)0x37F7, + (q15_t)0x8CCC, (q15_t)0x37CA, (q15_t)0x8CB6, (q15_t)0x379C, + (q15_t)0x8CA0, (q15_t)0x376F, (q15_t)0x8C8A, (q15_t)0x3742, + (q15_t)0x8C75, (q15_t)0x3714, (q15_t)0x8C5F, (q15_t)0x36E7, + (q15_t)0x8C4A, (q15_t)0x36BA, (q15_t)0x8C34, (q15_t)0x368C, + (q15_t)0x8C1F, (q15_t)0x365F, (q15_t)0x8C09, (q15_t)0x3631, + (q15_t)0x8BF4, (q15_t)0x3604, (q15_t)0x8BDF, (q15_t)0x35D6, + (q15_t)0x8BCA, (q15_t)0x35A8, (q15_t)0x8BB5, (q15_t)0x357B, + (q15_t)0x8BA0, (q15_t)0x354D, (q15_t)0x8B8B, (q15_t)0x351F, + (q15_t)0x8B76, (q15_t)0x34F2, (q15_t)0x8B61, (q15_t)0x34C4, + (q15_t)0x8B4D, (q15_t)0x3496, (q15_t)0x8B38, (q15_t)0x3468, + (q15_t)0x8B24, (q15_t)0x343A, (q15_t)0x8B0F, (q15_t)0x340C, + (q15_t)0x8AFB, (q15_t)0x33DE, (q15_t)0x8AE6, (q15_t)0x33B0, + (q15_t)0x8AD2, (q15_t)0x3382, (q15_t)0x8ABE, (q15_t)0x3354, + (q15_t)0x8AAA, (q15_t)0x3326, (q15_t)0x8A96, (q15_t)0x32F8, + (q15_t)0x8A82, (q15_t)0x32CA, (q15_t)0x8A6E, (q15_t)0x329C, + (q15_t)0x8A5A, (q15_t)0x326E, (q15_t)0x8A46, (q15_t)0x3240, + (q15_t)0x8A33, (q15_t)0x3211, (q15_t)0x8A1F, (q15_t)0x31E3, + (q15_t)0x8A0B, (q15_t)0x31B5, (q15_t)0x89F8, (q15_t)0x3186, + (q15_t)0x89E4, (q15_t)0x3158, (q15_t)0x89D1, (q15_t)0x312A, + (q15_t)0x89BE, (q15_t)0x30FB, (q15_t)0x89AB, (q15_t)0x30CD, + (q15_t)0x8997, (q15_t)0x309E, (q15_t)0x8984, (q15_t)0x3070, + (q15_t)0x8971, (q15_t)0x3041, (q15_t)0x895F, (q15_t)0x3013, + (q15_t)0x894C, (q15_t)0x2FE4, (q15_t)0x8939, (q15_t)0x2FB5, + (q15_t)0x8926, (q15_t)0x2F87, (q15_t)0x8914, (q15_t)0x2F58, + (q15_t)0x8901, (q15_t)0x2F29, (q15_t)0x88EF, (q15_t)0x2EFB, + (q15_t)0x88DC, (q15_t)0x2ECC, (q15_t)0x88CA, (q15_t)0x2E9D, + (q15_t)0x88B8, (q15_t)0x2E6E, (q15_t)0x88A5, (q15_t)0x2E3F, + (q15_t)0x8893, (q15_t)0x2E11, (q15_t)0x8881, (q15_t)0x2DE2, + (q15_t)0x886F, (q15_t)0x2DB3, (q15_t)0x885D, (q15_t)0x2D84, + (q15_t)0x884B, (q15_t)0x2D55, (q15_t)0x883A, (q15_t)0x2D26, + (q15_t)0x8828, (q15_t)0x2CF7, (q15_t)0x8816, (q15_t)0x2CC8, + (q15_t)0x8805, (q15_t)0x2C98, (q15_t)0x87F3, (q15_t)0x2C69, + (q15_t)0x87E2, (q15_t)0x2C3A, (q15_t)0x87D1, (q15_t)0x2C0B, + (q15_t)0x87BF, (q15_t)0x2BDC, (q15_t)0x87AE, (q15_t)0x2BAD, + (q15_t)0x879D, (q15_t)0x2B7D, (q15_t)0x878C, (q15_t)0x2B4E, + (q15_t)0x877B, (q15_t)0x2B1F, (q15_t)0x876A, (q15_t)0x2AEF, + (q15_t)0x8759, (q15_t)0x2AC0, (q15_t)0x8749, (q15_t)0x2A91, + (q15_t)0x8738, (q15_t)0x2A61, (q15_t)0x8727, (q15_t)0x2A32, + (q15_t)0x8717, (q15_t)0x2A02, (q15_t)0x8706, (q15_t)0x29D3, + (q15_t)0x86F6, (q15_t)0x29A3, (q15_t)0x86E6, (q15_t)0x2974, + (q15_t)0x86D5, (q15_t)0x2944, (q15_t)0x86C5, (q15_t)0x2915, + (q15_t)0x86B5, (q15_t)0x28E5, (q15_t)0x86A5, (q15_t)0x28B5, + (q15_t)0x8695, (q15_t)0x2886, (q15_t)0x8685, (q15_t)0x2856, + (q15_t)0x8675, (q15_t)0x2826, (q15_t)0x8666, (q15_t)0x27F6, + (q15_t)0x8656, (q15_t)0x27C7, (q15_t)0x8646, (q15_t)0x2797, + (q15_t)0x8637, (q15_t)0x2767, (q15_t)0x8627, (q15_t)0x2737, + (q15_t)0x8618, (q15_t)0x2707, (q15_t)0x8609, (q15_t)0x26D8, + (q15_t)0x85FA, (q15_t)0x26A8, (q15_t)0x85EA, (q15_t)0x2678, + (q15_t)0x85DB, (q15_t)0x2648, (q15_t)0x85CC, (q15_t)0x2618, + (q15_t)0x85BD, (q15_t)0x25E8, (q15_t)0x85AF, (q15_t)0x25B8, + (q15_t)0x85A0, (q15_t)0x2588, (q15_t)0x8591, (q15_t)0x2558, + (q15_t)0x8582, (q15_t)0x2528, (q15_t)0x8574, (q15_t)0x24F7, + (q15_t)0x8565, (q15_t)0x24C7, (q15_t)0x8557, (q15_t)0x2497, + (q15_t)0x8549, (q15_t)0x2467, (q15_t)0x853A, (q15_t)0x2437, + (q15_t)0x852C, (q15_t)0x2407, (q15_t)0x851E, (q15_t)0x23D6, + (q15_t)0x8510, (q15_t)0x23A6, (q15_t)0x8502, (q15_t)0x2376, + (q15_t)0x84F4, (q15_t)0x2345, (q15_t)0x84E6, (q15_t)0x2315, + (q15_t)0x84D9, (q15_t)0x22E5, (q15_t)0x84CB, (q15_t)0x22B4, + (q15_t)0x84BD, (q15_t)0x2284, (q15_t)0x84B0, (q15_t)0x2254, + (q15_t)0x84A2, (q15_t)0x2223, (q15_t)0x8495, (q15_t)0x21F3, + (q15_t)0x8488, (q15_t)0x21C2, (q15_t)0x847B, (q15_t)0x2192, + (q15_t)0x846D, (q15_t)0x2161, (q15_t)0x8460, (q15_t)0x2131, + (q15_t)0x8453, (q15_t)0x2100, (q15_t)0x8446, (q15_t)0x20D0, + (q15_t)0x843A, (q15_t)0x209F, (q15_t)0x842D, (q15_t)0x206E, + (q15_t)0x8420, (q15_t)0x203E, (q15_t)0x8414, (q15_t)0x200D, + (q15_t)0x8407, (q15_t)0x1FDC, (q15_t)0x83FA, (q15_t)0x1FAC, + (q15_t)0x83EE, (q15_t)0x1F7B, (q15_t)0x83E2, (q15_t)0x1F4A, + (q15_t)0x83D6, (q15_t)0x1F19, (q15_t)0x83C9, (q15_t)0x1EE9, + (q15_t)0x83BD, (q15_t)0x1EB8, (q15_t)0x83B1, (q15_t)0x1E87, + (q15_t)0x83A5, (q15_t)0x1E56, (q15_t)0x8399, (q15_t)0x1E25, + (q15_t)0x838E, (q15_t)0x1DF5, (q15_t)0x8382, (q15_t)0x1DC4, + (q15_t)0x8376, (q15_t)0x1D93, (q15_t)0x836B, (q15_t)0x1D62, + (q15_t)0x835F, (q15_t)0x1D31, (q15_t)0x8354, (q15_t)0x1D00, + (q15_t)0x8348, (q15_t)0x1CCF, (q15_t)0x833D, (q15_t)0x1C9E, + (q15_t)0x8332, (q15_t)0x1C6D, (q15_t)0x8327, (q15_t)0x1C3C, + (q15_t)0x831C, (q15_t)0x1C0B, (q15_t)0x8311, (q15_t)0x1BDA, + (q15_t)0x8306, (q15_t)0x1BA9, (q15_t)0x82FB, (q15_t)0x1B78, + (q15_t)0x82F0, (q15_t)0x1B47, (q15_t)0x82E6, (q15_t)0x1B16, + (q15_t)0x82DB, (q15_t)0x1AE4, (q15_t)0x82D0, (q15_t)0x1AB3, + (q15_t)0x82C6, (q15_t)0x1A82, (q15_t)0x82BC, (q15_t)0x1A51, + (q15_t)0x82B1, (q15_t)0x1A20, (q15_t)0x82A7, (q15_t)0x19EF, + (q15_t)0x829D, (q15_t)0x19BD, (q15_t)0x8293, (q15_t)0x198C, + (q15_t)0x8289, (q15_t)0x195B, (q15_t)0x827F, (q15_t)0x192A, + (q15_t)0x8275, (q15_t)0x18F8, (q15_t)0x826B, (q15_t)0x18C7, + (q15_t)0x8262, (q15_t)0x1896, (q15_t)0x8258, (q15_t)0x1864, + (q15_t)0x824F, (q15_t)0x1833, (q15_t)0x8245, (q15_t)0x1802, + (q15_t)0x823C, (q15_t)0x17D0, (q15_t)0x8232, (q15_t)0x179F, + (q15_t)0x8229, (q15_t)0x176D, (q15_t)0x8220, (q15_t)0x173C, + (q15_t)0x8217, (q15_t)0x170A, (q15_t)0x820E, (q15_t)0x16D9, + (q15_t)0x8205, (q15_t)0x16A8, (q15_t)0x81FC, (q15_t)0x1676, + (q15_t)0x81F3, (q15_t)0x1645, (q15_t)0x81EB, (q15_t)0x1613, + (q15_t)0x81E2, (q15_t)0x15E2, (q15_t)0x81D9, (q15_t)0x15B0, + (q15_t)0x81D1, (q15_t)0x157F, (q15_t)0x81C8, (q15_t)0x154D, + (q15_t)0x81C0, (q15_t)0x151B, (q15_t)0x81B8, (q15_t)0x14EA, + (q15_t)0x81B0, (q15_t)0x14B8, (q15_t)0x81A8, (q15_t)0x1487, + (q15_t)0x81A0, (q15_t)0x1455, (q15_t)0x8198, (q15_t)0x1423, + (q15_t)0x8190, (q15_t)0x13F2, (q15_t)0x8188, (q15_t)0x13C0, + (q15_t)0x8180, (q15_t)0x138E, (q15_t)0x8179, (q15_t)0x135D, + (q15_t)0x8171, (q15_t)0x132B, (q15_t)0x816A, (q15_t)0x12F9, + (q15_t)0x8162, (q15_t)0x12C8, (q15_t)0x815B, (q15_t)0x1296, + (q15_t)0x8154, (q15_t)0x1264, (q15_t)0x814C, (q15_t)0x1232, + (q15_t)0x8145, (q15_t)0x1201, (q15_t)0x813E, (q15_t)0x11CF, + (q15_t)0x8137, (q15_t)0x119D, (q15_t)0x8130, (q15_t)0x116B, + (q15_t)0x812A, (q15_t)0x1139, (q15_t)0x8123, (q15_t)0x1108, + (q15_t)0x811C, (q15_t)0x10D6, (q15_t)0x8116, (q15_t)0x10A4, + (q15_t)0x810F, (q15_t)0x1072, (q15_t)0x8109, (q15_t)0x1040, + (q15_t)0x8102, (q15_t)0x100E, (q15_t)0x80FC, (q15_t)0x0FDD, + (q15_t)0x80F6, (q15_t)0x0FAB, (q15_t)0x80F0, (q15_t)0x0F79, + (q15_t)0x80EA, (q15_t)0x0F47, (q15_t)0x80E4, (q15_t)0x0F15, + (q15_t)0x80DE, (q15_t)0x0EE3, (q15_t)0x80D8, (q15_t)0x0EB1, + (q15_t)0x80D2, (q15_t)0x0E7F, (q15_t)0x80CD, (q15_t)0x0E4D, + (q15_t)0x80C7, (q15_t)0x0E1B, (q15_t)0x80C2, (q15_t)0x0DE9, + (q15_t)0x80BC, (q15_t)0x0DB7, (q15_t)0x80B7, (q15_t)0x0D85, + (q15_t)0x80B2, (q15_t)0x0D53, (q15_t)0x80AC, (q15_t)0x0D21, + (q15_t)0x80A7, (q15_t)0x0CEF, (q15_t)0x80A2, (q15_t)0x0CBD, + (q15_t)0x809D, (q15_t)0x0C8B, (q15_t)0x8098, (q15_t)0x0C59, + (q15_t)0x8094, (q15_t)0x0C27, (q15_t)0x808F, (q15_t)0x0BF5, + (q15_t)0x808A, (q15_t)0x0BC3, (q15_t)0x8086, (q15_t)0x0B91, + (q15_t)0x8081, (q15_t)0x0B5F, (q15_t)0x807D, (q15_t)0x0B2D, + (q15_t)0x8078, (q15_t)0x0AFB, (q15_t)0x8074, (q15_t)0x0AC9, + (q15_t)0x8070, (q15_t)0x0A97, (q15_t)0x806C, (q15_t)0x0A65, + (q15_t)0x8068, (q15_t)0x0A33, (q15_t)0x8064, (q15_t)0x0A00, + (q15_t)0x8060, (q15_t)0x09CE, (q15_t)0x805C, (q15_t)0x099C, + (q15_t)0x8058, (q15_t)0x096A, (q15_t)0x8055, (q15_t)0x0938, + (q15_t)0x8051, (q15_t)0x0906, (q15_t)0x804E, (q15_t)0x08D4, + (q15_t)0x804A, (q15_t)0x08A2, (q15_t)0x8047, (q15_t)0x086F, + (q15_t)0x8043, (q15_t)0x083D, (q15_t)0x8040, (q15_t)0x080B, + (q15_t)0x803D, (q15_t)0x07D9, (q15_t)0x803A, (q15_t)0x07A7, + (q15_t)0x8037, (q15_t)0x0775, (q15_t)0x8034, (q15_t)0x0742, + (q15_t)0x8031, (q15_t)0x0710, (q15_t)0x802F, (q15_t)0x06DE, + (q15_t)0x802C, (q15_t)0x06AC, (q15_t)0x8029, (q15_t)0x067A, + (q15_t)0x8027, (q15_t)0x0647, (q15_t)0x8025, (q15_t)0x0615, + (q15_t)0x8022, (q15_t)0x05E3, (q15_t)0x8020, (q15_t)0x05B1, + (q15_t)0x801E, (q15_t)0x057F, (q15_t)0x801C, (q15_t)0x054C, + (q15_t)0x801A, (q15_t)0x051A, (q15_t)0x8018, (q15_t)0x04E8, + (q15_t)0x8016, (q15_t)0x04B6, (q15_t)0x8014, (q15_t)0x0483, + (q15_t)0x8012, (q15_t)0x0451, (q15_t)0x8011, (q15_t)0x041F, + (q15_t)0x800F, (q15_t)0x03ED, (q15_t)0x800D, (q15_t)0x03BA, + (q15_t)0x800C, (q15_t)0x0388, (q15_t)0x800B, (q15_t)0x0356, + (q15_t)0x8009, (q15_t)0x0324, (q15_t)0x8008, (q15_t)0x02F1, + (q15_t)0x8007, (q15_t)0x02BF, (q15_t)0x8006, (q15_t)0x028D, + (q15_t)0x8005, (q15_t)0x025B, (q15_t)0x8004, (q15_t)0x0228, + (q15_t)0x8003, (q15_t)0x01F6, (q15_t)0x8003, (q15_t)0x01C4, + (q15_t)0x8002, (q15_t)0x0192, (q15_t)0x8001, (q15_t)0x015F, + (q15_t)0x8001, (q15_t)0x012D, (q15_t)0x8000, (q15_t)0x00FB, + (q15_t)0x8000, (q15_t)0x00C9, (q15_t)0x8000, (q15_t)0x0096, + (q15_t)0x8000, (q15_t)0x0064, (q15_t)0x8000, (q15_t)0x0032, + (q15_t)0x8000, (q15_t)0x0000, (q15_t)0x8000, (q15_t)0xFFCD, + (q15_t)0x8000, (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFF69, + (q15_t)0x8000, (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF04, + (q15_t)0x8001, (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFEA0, + (q15_t)0x8002, (q15_t)0xFE6D, (q15_t)0x8003, (q15_t)0xFE3B, + (q15_t)0x8003, (q15_t)0xFE09, (q15_t)0x8004, (q15_t)0xFDD7, + (q15_t)0x8005, (q15_t)0xFDA4, (q15_t)0x8006, (q15_t)0xFD72, + (q15_t)0x8007, (q15_t)0xFD40, (q15_t)0x8008, (q15_t)0xFD0E, + (q15_t)0x8009, (q15_t)0xFCDB, (q15_t)0x800B, (q15_t)0xFCA9, + (q15_t)0x800C, (q15_t)0xFC77, (q15_t)0x800D, (q15_t)0xFC45, + (q15_t)0x800F, (q15_t)0xFC12, (q15_t)0x8011, (q15_t)0xFBE0, + (q15_t)0x8012, (q15_t)0xFBAE, (q15_t)0x8014, (q15_t)0xFB7C, + (q15_t)0x8016, (q15_t)0xFB49, (q15_t)0x8018, (q15_t)0xFB17, + (q15_t)0x801A, (q15_t)0xFAE5, (q15_t)0x801C, (q15_t)0xFAB3, + (q15_t)0x801E, (q15_t)0xFA80, (q15_t)0x8020, (q15_t)0xFA4E, + (q15_t)0x8022, (q15_t)0xFA1C, (q15_t)0x8025, (q15_t)0xF9EA, + (q15_t)0x8027, (q15_t)0xF9B8, (q15_t)0x8029, (q15_t)0xF985, + (q15_t)0x802C, (q15_t)0xF953, (q15_t)0x802F, (q15_t)0xF921, + (q15_t)0x8031, (q15_t)0xF8EF, (q15_t)0x8034, (q15_t)0xF8BD, + (q15_t)0x8037, (q15_t)0xF88A, (q15_t)0x803A, (q15_t)0xF858, + (q15_t)0x803D, (q15_t)0xF826, (q15_t)0x8040, (q15_t)0xF7F4, + (q15_t)0x8043, (q15_t)0xF7C2, (q15_t)0x8047, (q15_t)0xF790, + (q15_t)0x804A, (q15_t)0xF75D, (q15_t)0x804E, (q15_t)0xF72B, + (q15_t)0x8051, (q15_t)0xF6F9, (q15_t)0x8055, (q15_t)0xF6C7, + (q15_t)0x8058, (q15_t)0xF695, (q15_t)0x805C, (q15_t)0xF663, + (q15_t)0x8060, (q15_t)0xF631, (q15_t)0x8064, (q15_t)0xF5FF, + (q15_t)0x8068, (q15_t)0xF5CC, (q15_t)0x806C, (q15_t)0xF59A, + (q15_t)0x8070, (q15_t)0xF568, (q15_t)0x8074, (q15_t)0xF536, + (q15_t)0x8078, (q15_t)0xF504, (q15_t)0x807D, (q15_t)0xF4D2, + (q15_t)0x8081, (q15_t)0xF4A0, (q15_t)0x8086, (q15_t)0xF46E, + (q15_t)0x808A, (q15_t)0xF43C, (q15_t)0x808F, (q15_t)0xF40A, + (q15_t)0x8094, (q15_t)0xF3D8, (q15_t)0x8098, (q15_t)0xF3A6, + (q15_t)0x809D, (q15_t)0xF374, (q15_t)0x80A2, (q15_t)0xF342, + (q15_t)0x80A7, (q15_t)0xF310, (q15_t)0x80AC, (q15_t)0xF2DE, + (q15_t)0x80B2, (q15_t)0xF2AC, (q15_t)0x80B7, (q15_t)0xF27A, + (q15_t)0x80BC, (q15_t)0xF248, (q15_t)0x80C2, (q15_t)0xF216, + (q15_t)0x80C7, (q15_t)0xF1E4, (q15_t)0x80CD, (q15_t)0xF1B2, + (q15_t)0x80D2, (q15_t)0xF180, (q15_t)0x80D8, (q15_t)0xF14E, + (q15_t)0x80DE, (q15_t)0xF11C, (q15_t)0x80E4, (q15_t)0xF0EA, + (q15_t)0x80EA, (q15_t)0xF0B8, (q15_t)0x80F0, (q15_t)0xF086, + (q15_t)0x80F6, (q15_t)0xF054, (q15_t)0x80FC, (q15_t)0xF022, + (q15_t)0x8102, (q15_t)0xEFF1, (q15_t)0x8109, (q15_t)0xEFBF, + (q15_t)0x810F, (q15_t)0xEF8D, (q15_t)0x8116, (q15_t)0xEF5B, + (q15_t)0x811C, (q15_t)0xEF29, (q15_t)0x8123, (q15_t)0xEEF7, + (q15_t)0x812A, (q15_t)0xEEC6, (q15_t)0x8130, (q15_t)0xEE94, + (q15_t)0x8137, (q15_t)0xEE62, (q15_t)0x813E, (q15_t)0xEE30, + (q15_t)0x8145, (q15_t)0xEDFE, (q15_t)0x814C, (q15_t)0xEDCD, + (q15_t)0x8154, (q15_t)0xED9B, (q15_t)0x815B, (q15_t)0xED69, + (q15_t)0x8162, (q15_t)0xED37, (q15_t)0x816A, (q15_t)0xED06, + (q15_t)0x8171, (q15_t)0xECD4, (q15_t)0x8179, (q15_t)0xECA2, + (q15_t)0x8180, (q15_t)0xEC71, (q15_t)0x8188, (q15_t)0xEC3F, + (q15_t)0x8190, (q15_t)0xEC0D, (q15_t)0x8198, (q15_t)0xEBDC, + (q15_t)0x81A0, (q15_t)0xEBAA, (q15_t)0x81A8, (q15_t)0xEB78, + (q15_t)0x81B0, (q15_t)0xEB47, (q15_t)0x81B8, (q15_t)0xEB15, + (q15_t)0x81C0, (q15_t)0xEAE4, (q15_t)0x81C8, (q15_t)0xEAB2, + (q15_t)0x81D1, (q15_t)0xEA80, (q15_t)0x81D9, (q15_t)0xEA4F, + (q15_t)0x81E2, (q15_t)0xEA1D, (q15_t)0x81EB, (q15_t)0xE9EC, + (q15_t)0x81F3, (q15_t)0xE9BA, (q15_t)0x81FC, (q15_t)0xE989, + (q15_t)0x8205, (q15_t)0xE957, (q15_t)0x820E, (q15_t)0xE926, + (q15_t)0x8217, (q15_t)0xE8F5, (q15_t)0x8220, (q15_t)0xE8C3, + (q15_t)0x8229, (q15_t)0xE892, (q15_t)0x8232, (q15_t)0xE860, + (q15_t)0x823C, (q15_t)0xE82F, (q15_t)0x8245, (q15_t)0xE7FD, + (q15_t)0x824F, (q15_t)0xE7CC, (q15_t)0x8258, (q15_t)0xE79B, + (q15_t)0x8262, (q15_t)0xE769, (q15_t)0x826B, (q15_t)0xE738, + (q15_t)0x8275, (q15_t)0xE707, (q15_t)0x827F, (q15_t)0xE6D5, + (q15_t)0x8289, (q15_t)0xE6A4, (q15_t)0x8293, (q15_t)0xE673, + (q15_t)0x829D, (q15_t)0xE642, (q15_t)0x82A7, (q15_t)0xE610, + (q15_t)0x82B1, (q15_t)0xE5DF, (q15_t)0x82BC, (q15_t)0xE5AE, + (q15_t)0x82C6, (q15_t)0xE57D, (q15_t)0x82D0, (q15_t)0xE54C, + (q15_t)0x82DB, (q15_t)0xE51B, (q15_t)0x82E6, (q15_t)0xE4E9, + (q15_t)0x82F0, (q15_t)0xE4B8, (q15_t)0x82FB, (q15_t)0xE487, + (q15_t)0x8306, (q15_t)0xE456, (q15_t)0x8311, (q15_t)0xE425, + (q15_t)0x831C, (q15_t)0xE3F4, (q15_t)0x8327, (q15_t)0xE3C3, + (q15_t)0x8332, (q15_t)0xE392, (q15_t)0x833D, (q15_t)0xE361, + (q15_t)0x8348, (q15_t)0xE330, (q15_t)0x8354, (q15_t)0xE2FF, + (q15_t)0x835F, (q15_t)0xE2CE, (q15_t)0x836B, (q15_t)0xE29D, + (q15_t)0x8376, (q15_t)0xE26C, (q15_t)0x8382, (q15_t)0xE23B, + (q15_t)0x838E, (q15_t)0xE20A, (q15_t)0x8399, (q15_t)0xE1DA, + (q15_t)0x83A5, (q15_t)0xE1A9, (q15_t)0x83B1, (q15_t)0xE178, + (q15_t)0x83BD, (q15_t)0xE147, (q15_t)0x83C9, (q15_t)0xE116, + (q15_t)0x83D6, (q15_t)0xE0E6, (q15_t)0x83E2, (q15_t)0xE0B5, + (q15_t)0x83EE, (q15_t)0xE084, (q15_t)0x83FA, (q15_t)0xE053, + (q15_t)0x8407, (q15_t)0xE023, (q15_t)0x8414, (q15_t)0xDFF2, + (q15_t)0x8420, (q15_t)0xDFC1, (q15_t)0x842D, (q15_t)0xDF91, + (q15_t)0x843A, (q15_t)0xDF60, (q15_t)0x8446, (q15_t)0xDF2F, + (q15_t)0x8453, (q15_t)0xDEFF, (q15_t)0x8460, (q15_t)0xDECE, + (q15_t)0x846D, (q15_t)0xDE9E, (q15_t)0x847B, (q15_t)0xDE6D, + (q15_t)0x8488, (q15_t)0xDE3D, (q15_t)0x8495, (q15_t)0xDE0C, + (q15_t)0x84A2, (q15_t)0xDDDC, (q15_t)0x84B0, (q15_t)0xDDAB, + (q15_t)0x84BD, (q15_t)0xDD7B, (q15_t)0x84CB, (q15_t)0xDD4B, + (q15_t)0x84D9, (q15_t)0xDD1A, (q15_t)0x84E6, (q15_t)0xDCEA, + (q15_t)0x84F4, (q15_t)0xDCBA, (q15_t)0x8502, (q15_t)0xDC89, + (q15_t)0x8510, (q15_t)0xDC59, (q15_t)0x851E, (q15_t)0xDC29, + (q15_t)0x852C, (q15_t)0xDBF8, (q15_t)0x853A, (q15_t)0xDBC8, + (q15_t)0x8549, (q15_t)0xDB98, (q15_t)0x8557, (q15_t)0xDB68, + (q15_t)0x8565, (q15_t)0xDB38, (q15_t)0x8574, (q15_t)0xDB08, + (q15_t)0x8582, (q15_t)0xDAD7, (q15_t)0x8591, (q15_t)0xDAA7, + (q15_t)0x85A0, (q15_t)0xDA77, (q15_t)0x85AF, (q15_t)0xDA47, + (q15_t)0x85BD, (q15_t)0xDA17, (q15_t)0x85CC, (q15_t)0xD9E7, + (q15_t)0x85DB, (q15_t)0xD9B7, (q15_t)0x85EA, (q15_t)0xD987, + (q15_t)0x85FA, (q15_t)0xD957, (q15_t)0x8609, (q15_t)0xD927, + (q15_t)0x8618, (q15_t)0xD8F8, (q15_t)0x8627, (q15_t)0xD8C8, + (q15_t)0x8637, (q15_t)0xD898, (q15_t)0x8646, (q15_t)0xD868, + (q15_t)0x8656, (q15_t)0xD838, (q15_t)0x8666, (q15_t)0xD809, + (q15_t)0x8675, (q15_t)0xD7D9, (q15_t)0x8685, (q15_t)0xD7A9, + (q15_t)0x8695, (q15_t)0xD779, (q15_t)0x86A5, (q15_t)0xD74A, + (q15_t)0x86B5, (q15_t)0xD71A, (q15_t)0x86C5, (q15_t)0xD6EA, + (q15_t)0x86D5, (q15_t)0xD6BB, (q15_t)0x86E6, (q15_t)0xD68B, + (q15_t)0x86F6, (q15_t)0xD65C, (q15_t)0x8706, (q15_t)0xD62C, + (q15_t)0x8717, (q15_t)0xD5FD, (q15_t)0x8727, (q15_t)0xD5CD, + (q15_t)0x8738, (q15_t)0xD59E, (q15_t)0x8749, (q15_t)0xD56E, + (q15_t)0x8759, (q15_t)0xD53F, (q15_t)0x876A, (q15_t)0xD510, + (q15_t)0x877B, (q15_t)0xD4E0, (q15_t)0x878C, (q15_t)0xD4B1, + (q15_t)0x879D, (q15_t)0xD482, (q15_t)0x87AE, (q15_t)0xD452, + (q15_t)0x87BF, (q15_t)0xD423, (q15_t)0x87D1, (q15_t)0xD3F4, + (q15_t)0x87E2, (q15_t)0xD3C5, (q15_t)0x87F3, (q15_t)0xD396, + (q15_t)0x8805, (q15_t)0xD367, (q15_t)0x8816, (q15_t)0xD337, + (q15_t)0x8828, (q15_t)0xD308, (q15_t)0x883A, (q15_t)0xD2D9, + (q15_t)0x884B, (q15_t)0xD2AA, (q15_t)0x885D, (q15_t)0xD27B, + (q15_t)0x886F, (q15_t)0xD24C, (q15_t)0x8881, (q15_t)0xD21D, + (q15_t)0x8893, (q15_t)0xD1EE, (q15_t)0x88A5, (q15_t)0xD1C0, + (q15_t)0x88B8, (q15_t)0xD191, (q15_t)0x88CA, (q15_t)0xD162, + (q15_t)0x88DC, (q15_t)0xD133, (q15_t)0x88EF, (q15_t)0xD104, + (q15_t)0x8901, (q15_t)0xD0D6, (q15_t)0x8914, (q15_t)0xD0A7, + (q15_t)0x8926, (q15_t)0xD078, (q15_t)0x8939, (q15_t)0xD04A, + (q15_t)0x894C, (q15_t)0xD01B, (q15_t)0x895F, (q15_t)0xCFEC, + (q15_t)0x8971, (q15_t)0xCFBE, (q15_t)0x8984, (q15_t)0xCF8F, + (q15_t)0x8997, (q15_t)0xCF61, (q15_t)0x89AB, (q15_t)0xCF32, + (q15_t)0x89BE, (q15_t)0xCF04, (q15_t)0x89D1, (q15_t)0xCED5, + (q15_t)0x89E4, (q15_t)0xCEA7, (q15_t)0x89F8, (q15_t)0xCE79, + (q15_t)0x8A0B, (q15_t)0xCE4A, (q15_t)0x8A1F, (q15_t)0xCE1C, + (q15_t)0x8A33, (q15_t)0xCDEE, (q15_t)0x8A46, (q15_t)0xCDBF, + (q15_t)0x8A5A, (q15_t)0xCD91, (q15_t)0x8A6E, (q15_t)0xCD63, + (q15_t)0x8A82, (q15_t)0xCD35, (q15_t)0x8A96, (q15_t)0xCD07, + (q15_t)0x8AAA, (q15_t)0xCCD9, (q15_t)0x8ABE, (q15_t)0xCCAB, + (q15_t)0x8AD2, (q15_t)0xCC7D, (q15_t)0x8AE6, (q15_t)0xCC4F, + (q15_t)0x8AFB, (q15_t)0xCC21, (q15_t)0x8B0F, (q15_t)0xCBF3, + (q15_t)0x8B24, (q15_t)0xCBC5, (q15_t)0x8B38, (q15_t)0xCB97, + (q15_t)0x8B4D, (q15_t)0xCB69, (q15_t)0x8B61, (q15_t)0xCB3B, + (q15_t)0x8B76, (q15_t)0xCB0D, (q15_t)0x8B8B, (q15_t)0xCAE0, + (q15_t)0x8BA0, (q15_t)0xCAB2, (q15_t)0x8BB5, (q15_t)0xCA84, + (q15_t)0x8BCA, (q15_t)0xCA57, (q15_t)0x8BDF, (q15_t)0xCA29, + (q15_t)0x8BF4, (q15_t)0xC9FB, (q15_t)0x8C09, (q15_t)0xC9CE, + (q15_t)0x8C1F, (q15_t)0xC9A0, (q15_t)0x8C34, (q15_t)0xC973, + (q15_t)0x8C4A, (q15_t)0xC945, (q15_t)0x8C5F, (q15_t)0xC918, + (q15_t)0x8C75, (q15_t)0xC8EB, (q15_t)0x8C8A, (q15_t)0xC8BD, + (q15_t)0x8CA0, (q15_t)0xC890, (q15_t)0x8CB6, (q15_t)0xC863, + (q15_t)0x8CCC, (q15_t)0xC835, (q15_t)0x8CE2, (q15_t)0xC808, + (q15_t)0x8CF8, (q15_t)0xC7DB, (q15_t)0x8D0E, (q15_t)0xC7AE, + (q15_t)0x8D24, (q15_t)0xC781, (q15_t)0x8D3A, (q15_t)0xC754, + (q15_t)0x8D50, (q15_t)0xC727, (q15_t)0x8D67, (q15_t)0xC6F9, + (q15_t)0x8D7D, (q15_t)0xC6CD, (q15_t)0x8D94, (q15_t)0xC6A0, + (q15_t)0x8DAA, (q15_t)0xC673, (q15_t)0x8DC1, (q15_t)0xC646, + (q15_t)0x8DD8, (q15_t)0xC619, (q15_t)0x8DEE, (q15_t)0xC5EC, + (q15_t)0x8E05, (q15_t)0xC5BF, (q15_t)0x8E1C, (q15_t)0xC593, + (q15_t)0x8E33, (q15_t)0xC566, (q15_t)0x8E4A, (q15_t)0xC539, + (q15_t)0x8E61, (q15_t)0xC50D, (q15_t)0x8E79, (q15_t)0xC4E0, + (q15_t)0x8E90, (q15_t)0xC4B3, (q15_t)0x8EA7, (q15_t)0xC487, + (q15_t)0x8EBE, (q15_t)0xC45A, (q15_t)0x8ED6, (q15_t)0xC42E, + (q15_t)0x8EED, (q15_t)0xC402, (q15_t)0x8F05, (q15_t)0xC3D5, + (q15_t)0x8F1D, (q15_t)0xC3A9, (q15_t)0x8F34, (q15_t)0xC37C, + (q15_t)0x8F4C, (q15_t)0xC350, (q15_t)0x8F64, (q15_t)0xC324, + (q15_t)0x8F7C, (q15_t)0xC2F8, (q15_t)0x8F94, (q15_t)0xC2CC, + (q15_t)0x8FAC, (q15_t)0xC29F, (q15_t)0x8FC4, (q15_t)0xC273, + (q15_t)0x8FDC, (q15_t)0xC247, (q15_t)0x8FF5, (q15_t)0xC21B, + (q15_t)0x900D, (q15_t)0xC1EF, (q15_t)0x9025, (q15_t)0xC1C3, + (q15_t)0x903E, (q15_t)0xC197, (q15_t)0x9056, (q15_t)0xC16C, + (q15_t)0x906F, (q15_t)0xC140, (q15_t)0x9088, (q15_t)0xC114, + (q15_t)0x90A0, (q15_t)0xC0E8, (q15_t)0x90B9, (q15_t)0xC0BC, + (q15_t)0x90D2, (q15_t)0xC091, (q15_t)0x90EB, (q15_t)0xC065, + (q15_t)0x9104, (q15_t)0xC03A, (q15_t)0x911D, (q15_t)0xC00E, + (q15_t)0x9136, (q15_t)0xBFE2, (q15_t)0x9150, (q15_t)0xBFB7, + (q15_t)0x9169, (q15_t)0xBF8C, (q15_t)0x9182, (q15_t)0xBF60, + (q15_t)0x919C, (q15_t)0xBF35, (q15_t)0x91B5, (q15_t)0xBF09, + (q15_t)0x91CF, (q15_t)0xBEDE, (q15_t)0x91E8, (q15_t)0xBEB3, + (q15_t)0x9202, (q15_t)0xBE88, (q15_t)0x921C, (q15_t)0xBE5D, + (q15_t)0x9235, (q15_t)0xBE31, (q15_t)0x924F, (q15_t)0xBE06, + (q15_t)0x9269, (q15_t)0xBDDB, (q15_t)0x9283, (q15_t)0xBDB0, + (q15_t)0x929D, (q15_t)0xBD85, (q15_t)0x92B7, (q15_t)0xBD5A, + (q15_t)0x92D2, (q15_t)0xBD2F, (q15_t)0x92EC, (q15_t)0xBD05, + (q15_t)0x9306, (q15_t)0xBCDA, (q15_t)0x9321, (q15_t)0xBCAF, + (q15_t)0x933B, (q15_t)0xBC84, (q15_t)0x9356, (q15_t)0xBC5A, + (q15_t)0x9370, (q15_t)0xBC2F, (q15_t)0x938B, (q15_t)0xBC04, + (q15_t)0x93A6, (q15_t)0xBBDA, (q15_t)0x93C0, (q15_t)0xBBAF, + (q15_t)0x93DB, (q15_t)0xBB85, (q15_t)0x93F6, (q15_t)0xBB5A, + (q15_t)0x9411, (q15_t)0xBB30, (q15_t)0x942C, (q15_t)0xBB05, + (q15_t)0x9447, (q15_t)0xBADB, (q15_t)0x9463, (q15_t)0xBAB1, + (q15_t)0x947E, (q15_t)0xBA87, (q15_t)0x9499, (q15_t)0xBA5C, + (q15_t)0x94B5, (q15_t)0xBA32, (q15_t)0x94D0, (q15_t)0xBA08, + (q15_t)0x94EC, (q15_t)0xB9DE, (q15_t)0x9507, (q15_t)0xB9B4, + (q15_t)0x9523, (q15_t)0xB98A, (q15_t)0x953E, (q15_t)0xB960, + (q15_t)0x955A, (q15_t)0xB936, (q15_t)0x9576, (q15_t)0xB90C, + (q15_t)0x9592, (q15_t)0xB8E3, (q15_t)0x95AE, (q15_t)0xB8B9, + (q15_t)0x95CA, (q15_t)0xB88F, (q15_t)0x95E6, (q15_t)0xB865, + (q15_t)0x9602, (q15_t)0xB83C, (q15_t)0x961E, (q15_t)0xB812, + (q15_t)0x963B, (q15_t)0xB7E9, (q15_t)0x9657, (q15_t)0xB7BF, + (q15_t)0x9673, (q15_t)0xB796, (q15_t)0x9690, (q15_t)0xB76C, + (q15_t)0x96AC, (q15_t)0xB743, (q15_t)0x96C9, (q15_t)0xB719, + (q15_t)0x96E6, (q15_t)0xB6F0, (q15_t)0x9702, (q15_t)0xB6C7, + (q15_t)0x971F, (q15_t)0xB69E, (q15_t)0x973C, (q15_t)0xB675, + (q15_t)0x9759, (q15_t)0xB64B, (q15_t)0x9776, (q15_t)0xB622, + (q15_t)0x9793, (q15_t)0xB5F9, (q15_t)0x97B0, (q15_t)0xB5D0, + (q15_t)0x97CD, (q15_t)0xB5A7, (q15_t)0x97EA, (q15_t)0xB57E, + (q15_t)0x9808, (q15_t)0xB556, (q15_t)0x9825, (q15_t)0xB52D, + (q15_t)0x9842, (q15_t)0xB504, (q15_t)0x9860, (q15_t)0xB4DB, + (q15_t)0x987D, (q15_t)0xB4B3, (q15_t)0x989B, (q15_t)0xB48A, + (q15_t)0x98B9, (q15_t)0xB461, (q15_t)0x98D6, (q15_t)0xB439, + (q15_t)0x98F4, (q15_t)0xB410, (q15_t)0x9912, (q15_t)0xB3E8, + (q15_t)0x9930, (q15_t)0xB3C0, (q15_t)0x994E, (q15_t)0xB397, + (q15_t)0x996C, (q15_t)0xB36F, (q15_t)0x998A, (q15_t)0xB347, + (q15_t)0x99A8, (q15_t)0xB31E, (q15_t)0x99C6, (q15_t)0xB2F6, + (q15_t)0x99E5, (q15_t)0xB2CE, (q15_t)0x9A03, (q15_t)0xB2A6, + (q15_t)0x9A22, (q15_t)0xB27E, (q15_t)0x9A40, (q15_t)0xB256, + (q15_t)0x9A5F, (q15_t)0xB22E, (q15_t)0x9A7D, (q15_t)0xB206, + (q15_t)0x9A9C, (q15_t)0xB1DE, (q15_t)0x9ABA, (q15_t)0xB1B7, + (q15_t)0x9AD9, (q15_t)0xB18F, (q15_t)0x9AF8, (q15_t)0xB167, + (q15_t)0x9B17, (q15_t)0xB140, (q15_t)0x9B36, (q15_t)0xB118, + (q15_t)0x9B55, (q15_t)0xB0F0, (q15_t)0x9B74, (q15_t)0xB0C9, + (q15_t)0x9B93, (q15_t)0xB0A1, (q15_t)0x9BB2, (q15_t)0xB07A, + (q15_t)0x9BD2, (q15_t)0xB053, (q15_t)0x9BF1, (q15_t)0xB02B, + (q15_t)0x9C10, (q15_t)0xB004, (q15_t)0x9C30, (q15_t)0xAFDD, + (q15_t)0x9C4F, (q15_t)0xAFB6, (q15_t)0x9C6F, (q15_t)0xAF8F, + (q15_t)0x9C8E, (q15_t)0xAF68, (q15_t)0x9CAE, (q15_t)0xAF40, + (q15_t)0x9CCE, (q15_t)0xAF1A, (q15_t)0x9CEE, (q15_t)0xAEF3, + (q15_t)0x9D0D, (q15_t)0xAECC, (q15_t)0x9D2D, (q15_t)0xAEA5, + (q15_t)0x9D4D, (q15_t)0xAE7E, (q15_t)0x9D6D, (q15_t)0xAE57, + (q15_t)0x9D8E, (q15_t)0xAE31, (q15_t)0x9DAE, (q15_t)0xAE0A, + (q15_t)0x9DCE, (q15_t)0xADE3, (q15_t)0x9DEE, (q15_t)0xADBD, + (q15_t)0x9E0E, (q15_t)0xAD96, (q15_t)0x9E2F, (q15_t)0xAD70, + (q15_t)0x9E4F, (q15_t)0xAD4A, (q15_t)0x9E70, (q15_t)0xAD23, + (q15_t)0x9E90, (q15_t)0xACFD, (q15_t)0x9EB1, (q15_t)0xACD7, + (q15_t)0x9ED2, (q15_t)0xACB1, (q15_t)0x9EF2, (q15_t)0xAC8A, + (q15_t)0x9F13, (q15_t)0xAC64, (q15_t)0x9F34, (q15_t)0xAC3E, + (q15_t)0x9F55, (q15_t)0xAC18, (q15_t)0x9F76, (q15_t)0xABF2, + (q15_t)0x9F97, (q15_t)0xABCC, (q15_t)0x9FB8, (q15_t)0xABA7, + (q15_t)0x9FD9, (q15_t)0xAB81, (q15_t)0x9FFB, (q15_t)0xAB5B, + (q15_t)0xA01C, (q15_t)0xAB35, (q15_t)0xA03D, (q15_t)0xAB10, + (q15_t)0xA05F, (q15_t)0xAAEA, (q15_t)0xA080, (q15_t)0xAAC5, + (q15_t)0xA0A1, (q15_t)0xAA9F, (q15_t)0xA0C3, (q15_t)0xAA7A, + (q15_t)0xA0E5, (q15_t)0xAA54, (q15_t)0xA106, (q15_t)0xAA2F, + (q15_t)0xA128, (q15_t)0xAA0A, (q15_t)0xA14A, (q15_t)0xA9E5, + (q15_t)0xA16C, (q15_t)0xA9BF, (q15_t)0xA18E, (q15_t)0xA99A, + (q15_t)0xA1AF, (q15_t)0xA975, (q15_t)0xA1D2, (q15_t)0xA950, + (q15_t)0xA1F4, (q15_t)0xA92B, (q15_t)0xA216, (q15_t)0xA906, + (q15_t)0xA238, (q15_t)0xA8E2, (q15_t)0xA25A, (q15_t)0xA8BD, + (q15_t)0xA27C, (q15_t)0xA898, (q15_t)0xA29F, (q15_t)0xA873, + (q15_t)0xA2C1, (q15_t)0xA84F, (q15_t)0xA2E4, (q15_t)0xA82A, + (q15_t)0xA306, (q15_t)0xA806, (q15_t)0xA329, (q15_t)0xA7E1, + (q15_t)0xA34B, (q15_t)0xA7BD, (q15_t)0xA36E, (q15_t)0xA798, + (q15_t)0xA391, (q15_t)0xA774, (q15_t)0xA3B4, (q15_t)0xA750, + (q15_t)0xA3D6, (q15_t)0xA72B, (q15_t)0xA3F9, (q15_t)0xA707, + (q15_t)0xA41C, (q15_t)0xA6E3, (q15_t)0xA43F, (q15_t)0xA6BF, + (q15_t)0xA462, (q15_t)0xA69B, (q15_t)0xA486, (q15_t)0xA677, + (q15_t)0xA4A9, (q15_t)0xA653, (q15_t)0xA4CC, (q15_t)0xA62F, + (q15_t)0xA4EF, (q15_t)0xA60C, (q15_t)0xA513, (q15_t)0xA5E8, + (q15_t)0xA536, (q15_t)0xA5C4, (q15_t)0xA55A, (q15_t)0xA5A1, + (q15_t)0xA57D, (q15_t)0xA57D, (q15_t)0xA5A1, (q15_t)0xA55A, + (q15_t)0xA5C4, (q15_t)0xA536, (q15_t)0xA5E8, (q15_t)0xA513, + (q15_t)0xA60C, (q15_t)0xA4EF, (q15_t)0xA62F, (q15_t)0xA4CC, + (q15_t)0xA653, (q15_t)0xA4A9, (q15_t)0xA677, (q15_t)0xA486, + (q15_t)0xA69B, (q15_t)0xA462, (q15_t)0xA6BF, (q15_t)0xA43F, + (q15_t)0xA6E3, (q15_t)0xA41C, (q15_t)0xA707, (q15_t)0xA3F9, + (q15_t)0xA72B, (q15_t)0xA3D6, (q15_t)0xA750, (q15_t)0xA3B4, + (q15_t)0xA774, (q15_t)0xA391, (q15_t)0xA798, (q15_t)0xA36E, + (q15_t)0xA7BD, (q15_t)0xA34B, (q15_t)0xA7E1, (q15_t)0xA329, + (q15_t)0xA806, (q15_t)0xA306, (q15_t)0xA82A, (q15_t)0xA2E4, + (q15_t)0xA84F, (q15_t)0xA2C1, (q15_t)0xA873, (q15_t)0xA29F, + (q15_t)0xA898, (q15_t)0xA27C, (q15_t)0xA8BD, (q15_t)0xA25A, + (q15_t)0xA8E2, (q15_t)0xA238, (q15_t)0xA906, (q15_t)0xA216, + (q15_t)0xA92B, (q15_t)0xA1F4, (q15_t)0xA950, (q15_t)0xA1D2, + (q15_t)0xA975, (q15_t)0xA1AF, (q15_t)0xA99A, (q15_t)0xA18E, + (q15_t)0xA9BF, (q15_t)0xA16C, (q15_t)0xA9E5, (q15_t)0xA14A, + (q15_t)0xAA0A, (q15_t)0xA128, (q15_t)0xAA2F, (q15_t)0xA106, + (q15_t)0xAA54, (q15_t)0xA0E5, (q15_t)0xAA7A, (q15_t)0xA0C3, + (q15_t)0xAA9F, (q15_t)0xA0A1, (q15_t)0xAAC5, (q15_t)0xA080, + (q15_t)0xAAEA, (q15_t)0xA05F, (q15_t)0xAB10, (q15_t)0xA03D, + (q15_t)0xAB35, (q15_t)0xA01C, (q15_t)0xAB5B, (q15_t)0x9FFB, + (q15_t)0xAB81, (q15_t)0x9FD9, (q15_t)0xABA7, (q15_t)0x9FB8, + (q15_t)0xABCC, (q15_t)0x9F97, (q15_t)0xABF2, (q15_t)0x9F76, + (q15_t)0xAC18, (q15_t)0x9F55, (q15_t)0xAC3E, (q15_t)0x9F34, + (q15_t)0xAC64, (q15_t)0x9F13, (q15_t)0xAC8A, (q15_t)0x9EF2, + (q15_t)0xACB1, (q15_t)0x9ED2, (q15_t)0xACD7, (q15_t)0x9EB1, + (q15_t)0xACFD, (q15_t)0x9E90, (q15_t)0xAD23, (q15_t)0x9E70, + (q15_t)0xAD4A, (q15_t)0x9E4F, (q15_t)0xAD70, (q15_t)0x9E2F, + (q15_t)0xAD96, (q15_t)0x9E0E, (q15_t)0xADBD, (q15_t)0x9DEE, + (q15_t)0xADE3, (q15_t)0x9DCE, (q15_t)0xAE0A, (q15_t)0x9DAE, + (q15_t)0xAE31, (q15_t)0x9D8E, (q15_t)0xAE57, (q15_t)0x9D6D, + (q15_t)0xAE7E, (q15_t)0x9D4D, (q15_t)0xAEA5, (q15_t)0x9D2D, + (q15_t)0xAECC, (q15_t)0x9D0D, (q15_t)0xAEF3, (q15_t)0x9CEE, + (q15_t)0xAF1A, (q15_t)0x9CCE, (q15_t)0xAF40, (q15_t)0x9CAE, + (q15_t)0xAF68, (q15_t)0x9C8E, (q15_t)0xAF8F, (q15_t)0x9C6F, + (q15_t)0xAFB6, (q15_t)0x9C4F, (q15_t)0xAFDD, (q15_t)0x9C30, + (q15_t)0xB004, (q15_t)0x9C10, (q15_t)0xB02B, (q15_t)0x9BF1, + (q15_t)0xB053, (q15_t)0x9BD2, (q15_t)0xB07A, (q15_t)0x9BB2, + (q15_t)0xB0A1, (q15_t)0x9B93, (q15_t)0xB0C9, (q15_t)0x9B74, + (q15_t)0xB0F0, (q15_t)0x9B55, (q15_t)0xB118, (q15_t)0x9B36, + (q15_t)0xB140, (q15_t)0x9B17, (q15_t)0xB167, (q15_t)0x9AF8, + (q15_t)0xB18F, (q15_t)0x9AD9, (q15_t)0xB1B7, (q15_t)0x9ABA, + (q15_t)0xB1DE, (q15_t)0x9A9C, (q15_t)0xB206, (q15_t)0x9A7D, + (q15_t)0xB22E, (q15_t)0x9A5F, (q15_t)0xB256, (q15_t)0x9A40, + (q15_t)0xB27E, (q15_t)0x9A22, (q15_t)0xB2A6, (q15_t)0x9A03, + (q15_t)0xB2CE, (q15_t)0x99E5, (q15_t)0xB2F6, (q15_t)0x99C6, + (q15_t)0xB31E, (q15_t)0x99A8, (q15_t)0xB347, (q15_t)0x998A, + (q15_t)0xB36F, (q15_t)0x996C, (q15_t)0xB397, (q15_t)0x994E, + (q15_t)0xB3C0, (q15_t)0x9930, (q15_t)0xB3E8, (q15_t)0x9912, + (q15_t)0xB410, (q15_t)0x98F4, (q15_t)0xB439, (q15_t)0x98D6, + (q15_t)0xB461, (q15_t)0x98B9, (q15_t)0xB48A, (q15_t)0x989B, + (q15_t)0xB4B3, (q15_t)0x987D, (q15_t)0xB4DB, (q15_t)0x9860, + (q15_t)0xB504, (q15_t)0x9842, (q15_t)0xB52D, (q15_t)0x9825, + (q15_t)0xB556, (q15_t)0x9808, (q15_t)0xB57E, (q15_t)0x97EA, + (q15_t)0xB5A7, (q15_t)0x97CD, (q15_t)0xB5D0, (q15_t)0x97B0, + (q15_t)0xB5F9, (q15_t)0x9793, (q15_t)0xB622, (q15_t)0x9776, + (q15_t)0xB64B, (q15_t)0x9759, (q15_t)0xB675, (q15_t)0x973C, + (q15_t)0xB69E, (q15_t)0x971F, (q15_t)0xB6C7, (q15_t)0x9702, + (q15_t)0xB6F0, (q15_t)0x96E6, (q15_t)0xB719, (q15_t)0x96C9, + (q15_t)0xB743, (q15_t)0x96AC, (q15_t)0xB76C, (q15_t)0x9690, + (q15_t)0xB796, (q15_t)0x9673, (q15_t)0xB7BF, (q15_t)0x9657, + (q15_t)0xB7E9, (q15_t)0x963B, (q15_t)0xB812, (q15_t)0x961E, + (q15_t)0xB83C, (q15_t)0x9602, (q15_t)0xB865, (q15_t)0x95E6, + (q15_t)0xB88F, (q15_t)0x95CA, (q15_t)0xB8B9, (q15_t)0x95AE, + (q15_t)0xB8E3, (q15_t)0x9592, (q15_t)0xB90C, (q15_t)0x9576, + (q15_t)0xB936, (q15_t)0x955A, (q15_t)0xB960, (q15_t)0x953E, + (q15_t)0xB98A, (q15_t)0x9523, (q15_t)0xB9B4, (q15_t)0x9507, + (q15_t)0xB9DE, (q15_t)0x94EC, (q15_t)0xBA08, (q15_t)0x94D0, + (q15_t)0xBA32, (q15_t)0x94B5, (q15_t)0xBA5C, (q15_t)0x9499, + (q15_t)0xBA87, (q15_t)0x947E, (q15_t)0xBAB1, (q15_t)0x9463, + (q15_t)0xBADB, (q15_t)0x9447, (q15_t)0xBB05, (q15_t)0x942C, + (q15_t)0xBB30, (q15_t)0x9411, (q15_t)0xBB5A, (q15_t)0x93F6, + (q15_t)0xBB85, (q15_t)0x93DB, (q15_t)0xBBAF, (q15_t)0x93C0, + (q15_t)0xBBDA, (q15_t)0x93A6, (q15_t)0xBC04, (q15_t)0x938B, + (q15_t)0xBC2F, (q15_t)0x9370, (q15_t)0xBC5A, (q15_t)0x9356, + (q15_t)0xBC84, (q15_t)0x933B, (q15_t)0xBCAF, (q15_t)0x9321, + (q15_t)0xBCDA, (q15_t)0x9306, (q15_t)0xBD05, (q15_t)0x92EC, + (q15_t)0xBD2F, (q15_t)0x92D2, (q15_t)0xBD5A, (q15_t)0x92B7, + (q15_t)0xBD85, (q15_t)0x929D, (q15_t)0xBDB0, (q15_t)0x9283, + (q15_t)0xBDDB, (q15_t)0x9269, (q15_t)0xBE06, (q15_t)0x924F, + (q15_t)0xBE31, (q15_t)0x9235, (q15_t)0xBE5D, (q15_t)0x921C, + (q15_t)0xBE88, (q15_t)0x9202, (q15_t)0xBEB3, (q15_t)0x91E8, + (q15_t)0xBEDE, (q15_t)0x91CF, (q15_t)0xBF09, (q15_t)0x91B5, + (q15_t)0xBF35, (q15_t)0x919C, (q15_t)0xBF60, (q15_t)0x9182, + (q15_t)0xBF8C, (q15_t)0x9169, (q15_t)0xBFB7, (q15_t)0x9150, + (q15_t)0xBFE2, (q15_t)0x9136, (q15_t)0xC00E, (q15_t)0x911D, + (q15_t)0xC03A, (q15_t)0x9104, (q15_t)0xC065, (q15_t)0x90EB, + (q15_t)0xC091, (q15_t)0x90D2, (q15_t)0xC0BC, (q15_t)0x90B9, + (q15_t)0xC0E8, (q15_t)0x90A0, (q15_t)0xC114, (q15_t)0x9088, + (q15_t)0xC140, (q15_t)0x906F, (q15_t)0xC16C, (q15_t)0x9056, + (q15_t)0xC197, (q15_t)0x903E, (q15_t)0xC1C3, (q15_t)0x9025, + (q15_t)0xC1EF, (q15_t)0x900D, (q15_t)0xC21B, (q15_t)0x8FF5, + (q15_t)0xC247, (q15_t)0x8FDC, (q15_t)0xC273, (q15_t)0x8FC4, + (q15_t)0xC29F, (q15_t)0x8FAC, (q15_t)0xC2CC, (q15_t)0x8F94, + (q15_t)0xC2F8, (q15_t)0x8F7C, (q15_t)0xC324, (q15_t)0x8F64, + (q15_t)0xC350, (q15_t)0x8F4C, (q15_t)0xC37C, (q15_t)0x8F34, + (q15_t)0xC3A9, (q15_t)0x8F1D, (q15_t)0xC3D5, (q15_t)0x8F05, + (q15_t)0xC402, (q15_t)0x8EED, (q15_t)0xC42E, (q15_t)0x8ED6, + (q15_t)0xC45A, (q15_t)0x8EBE, (q15_t)0xC487, (q15_t)0x8EA7, + (q15_t)0xC4B3, (q15_t)0x8E90, (q15_t)0xC4E0, (q15_t)0x8E79, + (q15_t)0xC50D, (q15_t)0x8E61, (q15_t)0xC539, (q15_t)0x8E4A, + (q15_t)0xC566, (q15_t)0x8E33, (q15_t)0xC593, (q15_t)0x8E1C, + (q15_t)0xC5BF, (q15_t)0x8E05, (q15_t)0xC5EC, (q15_t)0x8DEE, + (q15_t)0xC619, (q15_t)0x8DD8, (q15_t)0xC646, (q15_t)0x8DC1, + (q15_t)0xC673, (q15_t)0x8DAA, (q15_t)0xC6A0, (q15_t)0x8D94, + (q15_t)0xC6CD, (q15_t)0x8D7D, (q15_t)0xC6F9, (q15_t)0x8D67, + (q15_t)0xC727, (q15_t)0x8D50, (q15_t)0xC754, (q15_t)0x8D3A, + (q15_t)0xC781, (q15_t)0x8D24, (q15_t)0xC7AE, (q15_t)0x8D0E, + (q15_t)0xC7DB, (q15_t)0x8CF8, (q15_t)0xC808, (q15_t)0x8CE2, + (q15_t)0xC835, (q15_t)0x8CCC, (q15_t)0xC863, (q15_t)0x8CB6, + (q15_t)0xC890, (q15_t)0x8CA0, (q15_t)0xC8BD, (q15_t)0x8C8A, + (q15_t)0xC8EB, (q15_t)0x8C75, (q15_t)0xC918, (q15_t)0x8C5F, + (q15_t)0xC945, (q15_t)0x8C4A, (q15_t)0xC973, (q15_t)0x8C34, + (q15_t)0xC9A0, (q15_t)0x8C1F, (q15_t)0xC9CE, (q15_t)0x8C09, + (q15_t)0xC9FB, (q15_t)0x8BF4, (q15_t)0xCA29, (q15_t)0x8BDF, + (q15_t)0xCA57, (q15_t)0x8BCA, (q15_t)0xCA84, (q15_t)0x8BB5, + (q15_t)0xCAB2, (q15_t)0x8BA0, (q15_t)0xCAE0, (q15_t)0x8B8B, + (q15_t)0xCB0D, (q15_t)0x8B76, (q15_t)0xCB3B, (q15_t)0x8B61, + (q15_t)0xCB69, (q15_t)0x8B4D, (q15_t)0xCB97, (q15_t)0x8B38, + (q15_t)0xCBC5, (q15_t)0x8B24, (q15_t)0xCBF3, (q15_t)0x8B0F, + (q15_t)0xCC21, (q15_t)0x8AFB, (q15_t)0xCC4F, (q15_t)0x8AE6, + (q15_t)0xCC7D, (q15_t)0x8AD2, (q15_t)0xCCAB, (q15_t)0x8ABE, + (q15_t)0xCCD9, (q15_t)0x8AAA, (q15_t)0xCD07, (q15_t)0x8A96, + (q15_t)0xCD35, (q15_t)0x8A82, (q15_t)0xCD63, (q15_t)0x8A6E, + (q15_t)0xCD91, (q15_t)0x8A5A, (q15_t)0xCDBF, (q15_t)0x8A46, + (q15_t)0xCDEE, (q15_t)0x8A33, (q15_t)0xCE1C, (q15_t)0x8A1F, + (q15_t)0xCE4A, (q15_t)0x8A0B, (q15_t)0xCE79, (q15_t)0x89F8, + (q15_t)0xCEA7, (q15_t)0x89E4, (q15_t)0xCED5, (q15_t)0x89D1, + (q15_t)0xCF04, (q15_t)0x89BE, (q15_t)0xCF32, (q15_t)0x89AB, + (q15_t)0xCF61, (q15_t)0x8997, (q15_t)0xCF8F, (q15_t)0x8984, + (q15_t)0xCFBE, (q15_t)0x8971, (q15_t)0xCFEC, (q15_t)0x895F, + (q15_t)0xD01B, (q15_t)0x894C, (q15_t)0xD04A, (q15_t)0x8939, + (q15_t)0xD078, (q15_t)0x8926, (q15_t)0xD0A7, (q15_t)0x8914, + (q15_t)0xD0D6, (q15_t)0x8901, (q15_t)0xD104, (q15_t)0x88EF, + (q15_t)0xD133, (q15_t)0x88DC, (q15_t)0xD162, (q15_t)0x88CA, + (q15_t)0xD191, (q15_t)0x88B8, (q15_t)0xD1C0, (q15_t)0x88A5, + (q15_t)0xD1EE, (q15_t)0x8893, (q15_t)0xD21D, (q15_t)0x8881, + (q15_t)0xD24C, (q15_t)0x886F, (q15_t)0xD27B, (q15_t)0x885D, + (q15_t)0xD2AA, (q15_t)0x884B, (q15_t)0xD2D9, (q15_t)0x883A, + (q15_t)0xD308, (q15_t)0x8828, (q15_t)0xD337, (q15_t)0x8816, + (q15_t)0xD367, (q15_t)0x8805, (q15_t)0xD396, (q15_t)0x87F3, + (q15_t)0xD3C5, (q15_t)0x87E2, (q15_t)0xD3F4, (q15_t)0x87D1, + (q15_t)0xD423, (q15_t)0x87BF, (q15_t)0xD452, (q15_t)0x87AE, + (q15_t)0xD482, (q15_t)0x879D, (q15_t)0xD4B1, (q15_t)0x878C, + (q15_t)0xD4E0, (q15_t)0x877B, (q15_t)0xD510, (q15_t)0x876A, + (q15_t)0xD53F, (q15_t)0x8759, (q15_t)0xD56E, (q15_t)0x8749, + (q15_t)0xD59E, (q15_t)0x8738, (q15_t)0xD5CD, (q15_t)0x8727, + (q15_t)0xD5FD, (q15_t)0x8717, (q15_t)0xD62C, (q15_t)0x8706, + (q15_t)0xD65C, (q15_t)0x86F6, (q15_t)0xD68B, (q15_t)0x86E6, + (q15_t)0xD6BB, (q15_t)0x86D5, (q15_t)0xD6EA, (q15_t)0x86C5, + (q15_t)0xD71A, (q15_t)0x86B5, (q15_t)0xD74A, (q15_t)0x86A5, + (q15_t)0xD779, (q15_t)0x8695, (q15_t)0xD7A9, (q15_t)0x8685, + (q15_t)0xD7D9, (q15_t)0x8675, (q15_t)0xD809, (q15_t)0x8666, + (q15_t)0xD838, (q15_t)0x8656, (q15_t)0xD868, (q15_t)0x8646, + (q15_t)0xD898, (q15_t)0x8637, (q15_t)0xD8C8, (q15_t)0x8627, + (q15_t)0xD8F8, (q15_t)0x8618, (q15_t)0xD927, (q15_t)0x8609, + (q15_t)0xD957, (q15_t)0x85FA, (q15_t)0xD987, (q15_t)0x85EA, + (q15_t)0xD9B7, (q15_t)0x85DB, (q15_t)0xD9E7, (q15_t)0x85CC, + (q15_t)0xDA17, (q15_t)0x85BD, (q15_t)0xDA47, (q15_t)0x85AF, + (q15_t)0xDA77, (q15_t)0x85A0, (q15_t)0xDAA7, (q15_t)0x8591, + (q15_t)0xDAD7, (q15_t)0x8582, (q15_t)0xDB08, (q15_t)0x8574, + (q15_t)0xDB38, (q15_t)0x8565, (q15_t)0xDB68, (q15_t)0x8557, + (q15_t)0xDB98, (q15_t)0x8549, (q15_t)0xDBC8, (q15_t)0x853A, + (q15_t)0xDBF8, (q15_t)0x852C, (q15_t)0xDC29, (q15_t)0x851E, + (q15_t)0xDC59, (q15_t)0x8510, (q15_t)0xDC89, (q15_t)0x8502, + (q15_t)0xDCBA, (q15_t)0x84F4, (q15_t)0xDCEA, (q15_t)0x84E6, + (q15_t)0xDD1A, (q15_t)0x84D9, (q15_t)0xDD4B, (q15_t)0x84CB, + (q15_t)0xDD7B, (q15_t)0x84BD, (q15_t)0xDDAB, (q15_t)0x84B0, + (q15_t)0xDDDC, (q15_t)0x84A2, (q15_t)0xDE0C, (q15_t)0x8495, + (q15_t)0xDE3D, (q15_t)0x8488, (q15_t)0xDE6D, (q15_t)0x847B, + (q15_t)0xDE9E, (q15_t)0x846D, (q15_t)0xDECE, (q15_t)0x8460, + (q15_t)0xDEFF, (q15_t)0x8453, (q15_t)0xDF2F, (q15_t)0x8446, + (q15_t)0xDF60, (q15_t)0x843A, (q15_t)0xDF91, (q15_t)0x842D, + (q15_t)0xDFC1, (q15_t)0x8420, (q15_t)0xDFF2, (q15_t)0x8414, + (q15_t)0xE023, (q15_t)0x8407, (q15_t)0xE053, (q15_t)0x83FA, + (q15_t)0xE084, (q15_t)0x83EE, (q15_t)0xE0B5, (q15_t)0x83E2, + (q15_t)0xE0E6, (q15_t)0x83D6, (q15_t)0xE116, (q15_t)0x83C9, + (q15_t)0xE147, (q15_t)0x83BD, (q15_t)0xE178, (q15_t)0x83B1, + (q15_t)0xE1A9, (q15_t)0x83A5, (q15_t)0xE1DA, (q15_t)0x8399, + (q15_t)0xE20A, (q15_t)0x838E, (q15_t)0xE23B, (q15_t)0x8382, + (q15_t)0xE26C, (q15_t)0x8376, (q15_t)0xE29D, (q15_t)0x836B, + (q15_t)0xE2CE, (q15_t)0x835F, (q15_t)0xE2FF, (q15_t)0x8354, + (q15_t)0xE330, (q15_t)0x8348, (q15_t)0xE361, (q15_t)0x833D, + (q15_t)0xE392, (q15_t)0x8332, (q15_t)0xE3C3, (q15_t)0x8327, + (q15_t)0xE3F4, (q15_t)0x831C, (q15_t)0xE425, (q15_t)0x8311, + (q15_t)0xE456, (q15_t)0x8306, (q15_t)0xE487, (q15_t)0x82FB, + (q15_t)0xE4B8, (q15_t)0x82F0, (q15_t)0xE4E9, (q15_t)0x82E6, + (q15_t)0xE51B, (q15_t)0x82DB, (q15_t)0xE54C, (q15_t)0x82D0, + (q15_t)0xE57D, (q15_t)0x82C6, (q15_t)0xE5AE, (q15_t)0x82BC, + (q15_t)0xE5DF, (q15_t)0x82B1, (q15_t)0xE610, (q15_t)0x82A7, + (q15_t)0xE642, (q15_t)0x829D, (q15_t)0xE673, (q15_t)0x8293, + (q15_t)0xE6A4, (q15_t)0x8289, (q15_t)0xE6D5, (q15_t)0x827F, + (q15_t)0xE707, (q15_t)0x8275, (q15_t)0xE738, (q15_t)0x826B, + (q15_t)0xE769, (q15_t)0x8262, (q15_t)0xE79B, (q15_t)0x8258, + (q15_t)0xE7CC, (q15_t)0x824F, (q15_t)0xE7FD, (q15_t)0x8245, + (q15_t)0xE82F, (q15_t)0x823C, (q15_t)0xE860, (q15_t)0x8232, + (q15_t)0xE892, (q15_t)0x8229, (q15_t)0xE8C3, (q15_t)0x8220, + (q15_t)0xE8F5, (q15_t)0x8217, (q15_t)0xE926, (q15_t)0x820E, + (q15_t)0xE957, (q15_t)0x8205, (q15_t)0xE989, (q15_t)0x81FC, + (q15_t)0xE9BA, (q15_t)0x81F3, (q15_t)0xE9EC, (q15_t)0x81EB, + (q15_t)0xEA1D, (q15_t)0x81E2, (q15_t)0xEA4F, (q15_t)0x81D9, + (q15_t)0xEA80, (q15_t)0x81D1, (q15_t)0xEAB2, (q15_t)0x81C8, + (q15_t)0xEAE4, (q15_t)0x81C0, (q15_t)0xEB15, (q15_t)0x81B8, + (q15_t)0xEB47, (q15_t)0x81B0, (q15_t)0xEB78, (q15_t)0x81A8, + (q15_t)0xEBAA, (q15_t)0x81A0, (q15_t)0xEBDC, (q15_t)0x8198, + (q15_t)0xEC0D, (q15_t)0x8190, (q15_t)0xEC3F, (q15_t)0x8188, + (q15_t)0xEC71, (q15_t)0x8180, (q15_t)0xECA2, (q15_t)0x8179, + (q15_t)0xECD4, (q15_t)0x8171, (q15_t)0xED06, (q15_t)0x816A, + (q15_t)0xED37, (q15_t)0x8162, (q15_t)0xED69, (q15_t)0x815B, + (q15_t)0xED9B, (q15_t)0x8154, (q15_t)0xEDCD, (q15_t)0x814C, + (q15_t)0xEDFE, (q15_t)0x8145, (q15_t)0xEE30, (q15_t)0x813E, + (q15_t)0xEE62, (q15_t)0x8137, (q15_t)0xEE94, (q15_t)0x8130, + (q15_t)0xEEC6, (q15_t)0x812A, (q15_t)0xEEF7, (q15_t)0x8123, + (q15_t)0xEF29, (q15_t)0x811C, (q15_t)0xEF5B, (q15_t)0x8116, + (q15_t)0xEF8D, (q15_t)0x810F, (q15_t)0xEFBF, (q15_t)0x8109, + (q15_t)0xEFF1, (q15_t)0x8102, (q15_t)0xF022, (q15_t)0x80FC, + (q15_t)0xF054, (q15_t)0x80F6, (q15_t)0xF086, (q15_t)0x80F0, + (q15_t)0xF0B8, (q15_t)0x80EA, (q15_t)0xF0EA, (q15_t)0x80E4, + (q15_t)0xF11C, (q15_t)0x80DE, (q15_t)0xF14E, (q15_t)0x80D8, + (q15_t)0xF180, (q15_t)0x80D2, (q15_t)0xF1B2, (q15_t)0x80CD, + (q15_t)0xF1E4, (q15_t)0x80C7, (q15_t)0xF216, (q15_t)0x80C2, + (q15_t)0xF248, (q15_t)0x80BC, (q15_t)0xF27A, (q15_t)0x80B7, + (q15_t)0xF2AC, (q15_t)0x80B2, (q15_t)0xF2DE, (q15_t)0x80AC, + (q15_t)0xF310, (q15_t)0x80A7, (q15_t)0xF342, (q15_t)0x80A2, + (q15_t)0xF374, (q15_t)0x809D, (q15_t)0xF3A6, (q15_t)0x8098, + (q15_t)0xF3D8, (q15_t)0x8094, (q15_t)0xF40A, (q15_t)0x808F, + (q15_t)0xF43C, (q15_t)0x808A, (q15_t)0xF46E, (q15_t)0x8086, + (q15_t)0xF4A0, (q15_t)0x8081, (q15_t)0xF4D2, (q15_t)0x807D, + (q15_t)0xF504, (q15_t)0x8078, (q15_t)0xF536, (q15_t)0x8074, + (q15_t)0xF568, (q15_t)0x8070, (q15_t)0xF59A, (q15_t)0x806C, + (q15_t)0xF5CC, (q15_t)0x8068, (q15_t)0xF5FF, (q15_t)0x8064, + (q15_t)0xF631, (q15_t)0x8060, (q15_t)0xF663, (q15_t)0x805C, + (q15_t)0xF695, (q15_t)0x8058, (q15_t)0xF6C7, (q15_t)0x8055, + (q15_t)0xF6F9, (q15_t)0x8051, (q15_t)0xF72B, (q15_t)0x804E, + (q15_t)0xF75D, (q15_t)0x804A, (q15_t)0xF790, (q15_t)0x8047, + (q15_t)0xF7C2, (q15_t)0x8043, (q15_t)0xF7F4, (q15_t)0x8040, + (q15_t)0xF826, (q15_t)0x803D, (q15_t)0xF858, (q15_t)0x803A, + (q15_t)0xF88A, (q15_t)0x8037, (q15_t)0xF8BD, (q15_t)0x8034, + (q15_t)0xF8EF, (q15_t)0x8031, (q15_t)0xF921, (q15_t)0x802F, + (q15_t)0xF953, (q15_t)0x802C, (q15_t)0xF985, (q15_t)0x8029, + (q15_t)0xF9B8, (q15_t)0x8027, (q15_t)0xF9EA, (q15_t)0x8025, + (q15_t)0xFA1C, (q15_t)0x8022, (q15_t)0xFA4E, (q15_t)0x8020, + (q15_t)0xFA80, (q15_t)0x801E, (q15_t)0xFAB3, (q15_t)0x801C, + (q15_t)0xFAE5, (q15_t)0x801A, (q15_t)0xFB17, (q15_t)0x8018, + (q15_t)0xFB49, (q15_t)0x8016, (q15_t)0xFB7C, (q15_t)0x8014, + (q15_t)0xFBAE, (q15_t)0x8012, (q15_t)0xFBE0, (q15_t)0x8011, + (q15_t)0xFC12, (q15_t)0x800F, (q15_t)0xFC45, (q15_t)0x800D, + (q15_t)0xFC77, (q15_t)0x800C, (q15_t)0xFCA9, (q15_t)0x800B, + (q15_t)0xFCDB, (q15_t)0x8009, (q15_t)0xFD0E, (q15_t)0x8008, + (q15_t)0xFD40, (q15_t)0x8007, (q15_t)0xFD72, (q15_t)0x8006, + (q15_t)0xFDA4, (q15_t)0x8005, (q15_t)0xFDD7, (q15_t)0x8004, + (q15_t)0xFE09, (q15_t)0x8003, (q15_t)0xFE3B, (q15_t)0x8003, + (q15_t)0xFE6D, (q15_t)0x8002, (q15_t)0xFEA0, (q15_t)0x8001, + (q15_t)0xFED2, (q15_t)0x8001, (q15_t)0xFF04, (q15_t)0x8000, + (q15_t)0xFF36, (q15_t)0x8000, (q15_t)0xFF69, (q15_t)0x8000, + (q15_t)0xFF9B, (q15_t)0x8000, (q15_t)0xFFCD, (q15_t)0x8000 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +/** + @} end of CFFT_CIFFT group +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + +const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) +const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) +const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) +const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) +const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) +const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) +const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) +const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) +const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, + 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, + 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, + 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, + 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, + 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, + 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, + 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, + 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, + 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, + 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, + 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, + 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, + 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, + 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, + 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, + 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, + 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, + 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, + 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, + 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, + 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, + 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, + 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, + 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, + 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, + 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, + 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, + 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, + 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, + 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, + 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, + 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, + 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, + 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, + 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, + 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, + 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, + 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, + 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, + 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, + 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, + 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, + 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, + 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, + 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, + 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, + 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, + 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, + 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, + 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, + 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, + 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, + 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, + 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, + 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, + 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, + 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, + 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, + 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, + 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, + 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, + 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, + 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, + 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, + 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, + 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, + 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, + 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, + 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, + 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, + 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, + 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, + 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, + 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, + 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + +const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH] = +{ + /* 8x2, size 20 */ + 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + +const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH] = +{ + /* 8x4, size 48 */ + 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208, + 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208, + 152,224, 176,208, 184,232, 216,240, 200,224, 232,240 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + +const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH] = +{ + /* radix 8, size 56 */ + 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200, + 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400, + 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480, + 368,424, 376,488, 440,496 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + +const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] = +{ + /* 8x2, size 208 */ + 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768, + 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520, + 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776, + 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320, + 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400, + 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584, + 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600, + 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608, + 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864, + 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808, + 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832, + 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008, + 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + +const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] = +{ + /* 8x4, size 440 */ + 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640, + 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768, + 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384, + 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984, + 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608, + 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736, + 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864, + 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992, + 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104, + 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720, + 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160, + 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936, + 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048, + 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808, + 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544, + 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880, + 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496, + 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120, + 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552, + 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824, + 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672, + 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016, + 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640, + 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432, + 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936, + 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960, + 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648, + 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936, + 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928, + 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840, + 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888, + 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032, + 1960,1968, 2008,2032, 1992,2016, 2024,2032 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + +const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] = +{ + /* radix 8, size 448 */ + 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576, + 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152, + 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216, + 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280, + 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344, + 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408, + 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472, + 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544, + 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120, + 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696, + 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272, + 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848, + 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416, + 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992, + 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576, + 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152, + 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728, + 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808, + 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384, + 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960, + 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536, + 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136, + 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224, + 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328, + 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416, + 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520, + 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616, + 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744, + 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872, + 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000, + 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176, + 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368, + 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560, + 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888, + 3448,3952, 3512,4016, 3576,4080 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + +const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH] = +{ + /* 8x2, size 1800 */ + 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048, + 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048, + 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696, + 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648, + 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248, + 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200, + 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800, + 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752, + 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352, + 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304, + 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936, + 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856, + 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488, + 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408, + 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040, + 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960, + 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592, + 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096, + 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544, + 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080, + 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400, + 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120, + 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656, + 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168, + 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696, + 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208, + 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736, + 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272, + 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480, + 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312, + 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848, + 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280, + 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888, + 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288, + 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928, + 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464, + 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592, + 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504, + 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040, + 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136, + 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088, + 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816, + 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576, + 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664, + 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264, + 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800, + 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304, + 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840, + 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376, + 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392, + 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344, + 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944, + 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480, + 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016, + 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032, + 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984, + 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584, + 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632, + 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632, + 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168, + 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704, + 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208, + 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744, + 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248, + 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784, + 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320, + 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824, + 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360, + 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896, + 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400, + 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936, + 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440, + 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976, + 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512, + 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016, + 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552, + 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088, + 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592, + 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128, + 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160, + 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176, + 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712, + 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216, + 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752, + 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416, + 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304, + 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624, + 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296, + 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680, + 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208, + 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400, + 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808, + 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688, + 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976, + 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160, + 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344, + 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728, + 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736, + 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928, + 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872, + 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672, + 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208, + 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456, + 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248, + 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784, + 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448, + 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824, + 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240, + 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504, + 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168, + 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264, + 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456, + 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552, + 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312, + 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576, + 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248, + 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504, + 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360, + 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624, + 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384, + 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264, + 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664, + 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520, + 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280, + 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536, + 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048, + 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752, + 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992, + 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280, + 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856, + 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024, + 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624, + 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104, + 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664, + 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280, + 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688, + 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952, + 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456, + 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864, + 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784, + 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048, + 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728, + 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096, + 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112, + 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984, + 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160, + 8112,8136, 8120,8168, 8136,8160, 8152,8176 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + +const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH] = +{ + /* 8x2, size 3808 */ + 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024, + 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824, + 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752, + 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680, + 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576, + 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376, + 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304, + 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232, + 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048, + 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928, + 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856, + 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784, + 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712, + 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480, + 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408, + 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336, + 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264, + 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064, + 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960, + 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792, + 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496, + 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328, + 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032, + 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928, + 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856, + 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560, + 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392, + 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096, + 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240, + 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600, + 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432, + 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136, + 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968, + 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640, + 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392, + 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176, + 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008, + 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712, + 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096, + 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712, + 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480, + 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248, + 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080, + 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784, + 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248, + 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288, + 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128, + 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824, + 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656, + 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328, + 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400, + 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864, + 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280, + 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400, + 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168, + 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904, + 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552, + 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440, + 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272, + 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976, + 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288, + 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480, + 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168, + 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016, + 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848, + 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520, + 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440, + 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056, + 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320, + 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592, + 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208, + 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096, + 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592, + 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632, + 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472, + 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168, + 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360, + 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672, + 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240, + 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208, + 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624, + 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208, + 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448, + 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744, + 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328, + 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280, + 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216, + 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784, + 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600, + 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320, + 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480, + 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856, + 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368, + 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360, + 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248, + 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896, + 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632, + 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400, + 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520, + 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936, + 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400, + 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472, + 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256, + 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976, + 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640, + 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512, + 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520, + 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048, + 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408, + 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552, + 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288, + 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088, + 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672, + 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592, + 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560, + 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128, + 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440, + 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664, + 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328, + 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168, + 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712, + 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704, + 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592, + 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240, + 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416, + 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240, + 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296, + 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776, + 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680, + 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280, + 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568, + 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816, + 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448, + 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352, + 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336, + 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856, + 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720, + 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392, + 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600, + 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928, + 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488, + 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432, + 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368, + 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968, + 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752, + 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472, + 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608, + 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008, + 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488, + 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544, + 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376, + 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048, + 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760, + 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584, + 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640, + 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120, + 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528, + 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624, + 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408, + 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160, + 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792, + 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664, + 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680, + 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200, + 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560, + 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736, + 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320, + 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448, + 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760, + 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464, + 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392, + 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576, + 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896, + 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688, + 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432, + 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736, + 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968, + 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376, + 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472, + 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424, + 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008, + 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536, + 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512, + 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736, + 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048, + 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728, + 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584, + 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248, + 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408, + 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112, + 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040, + 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616, + 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640, + 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664, + 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688, + 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616, + 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312, + 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336, + 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392, + 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656, + 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408, + 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192, + 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584, + 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760, + 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208, + 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816, + 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664, + 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816, + 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328, + 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296, + 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400, + 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480, + 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304, + 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912, + 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296, + 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360, + 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464, + 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440, + 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344, + 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800, + 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464, + 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968, + 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368, + 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440, + 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488, + 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528, + 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400, + 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440, + 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552, + 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056, + 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424, + 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760, + 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008, + 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408, + 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648, + 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120, + 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440, + 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656, + 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552, + 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160, + 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720, + 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760, + 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672, + 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624, + 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728, + 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736, + 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608, + 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512, + 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760, + 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296, + 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664, + 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712, + 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816, + 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824, + 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696, + 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832, + 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544, + 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584, + 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496, + 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688, + 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920, + 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344, + 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576, + 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400, + 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448, + 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696, + 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816, + 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344, + 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976, + 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416, + 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496, + 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488, + 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536, + 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592, + 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736, + 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664, + 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064, + 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464, + 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816, + 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768, + 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576, + 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592, + 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536, + 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664, + 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616, + 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704, + 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728, + 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488, + 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384, + 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560, + 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392, + 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528, + 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464, + 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304, + 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632, + 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808, + 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704, + 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832, + 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712, + 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848, + 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600, + 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640, + 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728, + 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928, + 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384, + 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616, + 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656, + 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504, + 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528, + 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776, + 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880, + 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024, + 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232, + 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024, + 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544, + 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872, + 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016, + 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160, + 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304, + 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008, + 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152, + 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296, + 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632, + 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768, + 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760, + 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184, + 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856, + 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000, + 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160, + 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264, + 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048, + 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184, + 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264, + 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208, + 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352, + 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368, + 16328,16352, 16360,16368 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + +const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH] = +{ + /* radix 8, size 4032 */ + 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512, + 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184, + 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600, + 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016, + 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432, + 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848, + 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264, + 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680, + 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160, + 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672, + 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088, + 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760, + 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176, + 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592, + 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008, + 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424, + 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840, + 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224, + 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800, + 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216, + 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632, + 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952, + 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272, + 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848, + 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168, + 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488, + 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808, + 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384, + 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768, + 1592,28864, 1608,4800, 1616,8896, 1624,12992, 1632,17088, 1640,21184, + 1648,25280, 1656,29376, 1672,5312, 1680,9408, 1688,13504, 1696,17600, + 1704,21696, 1712,25792, 1720,29888, 1736,5824, 1744,9920, 1752,14016, + 1760,18112, 1768,22208, 1776,26304, 1784,30400, 1792,2240, 1800,6336, + 1808,10432, 1816,14528, 1824,18624, 1832,22720, 1840,26816, 1848,30912, + 1856,2752, 1864,6848, 1872,10944, 1880,15040, 1888,19136, 1896,23232, + 1904,27328, 1912,31424, 1920,3264, 1928,7360, 1936,11456, 1944,15552, + 1952,19648, 1960,23744, 1968,27840, 1976,31936, 1984,3776, 1992,7872, + 2000,11968, 2008,16064, 2016,20160, 2024,24256, 2032,28352, 2040,32448, + 2056,4352, 2064,8448, 2072,12544, 2080,16640, 2088,20736, 2096,24832, + 2104,28928, 2120,4864, 2128,8960, 2136,13056, 2144,17152, 2152,21248, + 2160,25344, 2168,29440, 2184,5376, 2192,9472, 2200,13568, 2208,17664, + 2216,21760, 2224,25856, 2232,29952, 2248,5888, 2256,9984, 2264,14080, + 2272,18176, 2280,22272, 2288,26368, 2296,30464, 2312,6400, 2320,10496, + 2328,14592, 2336,18688, 2344,22784, 2352,26880, 2360,30976, 2368,2816, + 2376,6912, 2384,11008, 2392,15104, 2400,19200, 2408,23296, 2416,27392, + 2424,31488, 2432,3328, 2440,7424, 2448,11520, 2456,15616, 2464,19712, + 2472,23808, 2480,27904, 2488,32000, 2496,3840, 2504,7936, 2512,12032, + 2520,16128, 2528,20224, 2536,24320, 2544,28416, 2552,32512, 2568,4416, + 2576,8512, 2584,12608, 2592,16704, 2600,20800, 2608,24896, 2616,28992, + 2632,4928, 2640,9024, 2648,13120, 2656,17216, 2664,21312, 2672,25408, + 2680,29504, 2696,5440, 2704,9536, 2712,13632, 2720,17728, 2728,21824, + 2736,25920, 2744,30016, 2760,5952, 2768,10048, 2776,14144, 2784,18240, + 2792,22336, 2800,26432, 2808,30528, 2824,6464, 2832,10560, 2840,14656, + 2848,18752, 2856,22848, 2864,26944, 2872,31040, 2888,6976, 2896,11072, + 2904,15168, 2912,19264, 2920,23360, 2928,27456, 2936,31552, 2944,3392, + 2952,7488, 2960,11584, 2968,15680, 2976,19776, 2984,23872, 2992,27968, + 3000,32064, 3008,3904, 3016,8000, 3024,12096, 3032,16192, 3040,20288, + 3048,24384, 3056,28480, 3064,32576, 3080,4480, 3088,8576, 3096,12672, + 3104,16768, 3112,20864, 3120,24960, 3128,29056, 3144,4992, 3152,9088, + 3160,13184, 3168,17280, 3176,21376, 3184,25472, 3192,29568, 3208,5504, + 3216,9600, 3224,13696, 3232,17792, 3240,21888, 3248,25984, 3256,30080, + 3272,6016, 3280,10112, 3288,14208, 3296,18304, 3304,22400, 3312,26496, + 3320,30592, 3336,6528, 3344,10624, 3352,14720, 3360,18816, 3368,22912, + 3376,27008, 3384,31104, 3400,7040, 3408,11136, 3416,15232, 3424,19328, + 3432,23424, 3440,27520, 3448,31616, 3464,7552, 3472,11648, 3480,15744, + 3488,19840, 3496,23936, 3504,28032, 3512,32128, 3520,3968, 3528,8064, + 3536,12160, 3544,16256, 3552,20352, 3560,24448, 3568,28544, 3576,32640, + 3592,4544, 3600,8640, 3608,12736, 3616,16832, 3624,20928, 3632,25024, + 3640,29120, 3656,5056, 3664,9152, 3672,13248, 3680,17344, 3688,21440, + 3696,25536, 3704,29632, 3720,5568, 3728,9664, 3736,13760, 3744,17856, + 3752,21952, 3760,26048, 3768,30144, 3784,6080, 3792,10176, 3800,14272, + 3808,18368, 3816,22464, 3824,26560, 3832,30656, 3848,6592, 3856,10688, + 3864,14784, 3872,18880, 3880,22976, 3888,27072, 3896,31168, 3912,7104, + 3920,11200, 3928,15296, 3936,19392, 3944,23488, 3952,27584, 3960,31680, + 3976,7616, 3984,11712, 3992,15808, 4000,19904, 4008,24000, 4016,28096, + 4024,32192, 4040,8128, 4048,12224, 4056,16320, 4064,20416, 4072,24512, + 4080,28608, 4088,32704, 4112,8200, 4120,12296, 4128,16392, 4136,20488, + 4144,24584, 4152,28680, 4168,4616, 4176,8712, 4184,12808, 4192,16904, + 4200,21000, 4208,25096, 4216,29192, 4232,5128, 4240,9224, 4248,13320, + 4256,17416, 4264,21512, 4272,25608, 4280,29704, 4296,5640, 4304,9736, + 4312,13832, 4320,17928, 4328,22024, 4336,26120, 4344,30216, 4360,6152, + 4368,10248, 4376,14344, 4384,18440, 4392,22536, 4400,26632, 4408,30728, + 4424,6664, 4432,10760, 4440,14856, 4448,18952, 4456,23048, 4464,27144, + 4472,31240, 4488,7176, 4496,11272, 4504,15368, 4512,19464, 4520,23560, + 4528,27656, 4536,31752, 4552,7688, 4560,11784, 4568,15880, 4576,19976, + 4584,24072, 4592,28168, 4600,32264, 4624,8264, 4632,12360, 4640,16456, + 4648,20552, 4656,24648, 4664,28744, 4688,8776, 4696,12872, 4704,16968, + 4712,21064, 4720,25160, 4728,29256, 4744,5192, 4752,9288, 4760,13384, + 4768,17480, 4776,21576, 4784,25672, 4792,29768, 4808,5704, 4816,9800, + 4824,13896, 4832,17992, 4840,22088, 4848,26184, 4856,30280, 4872,6216, + 4880,10312, 4888,14408, 4896,18504, 4904,22600, 4912,26696, 4920,30792, + 4936,6728, 4944,10824, 4952,14920, 4960,19016, 4968,23112, 4976,27208, + 4984,31304, 5000,7240, 5008,11336, 5016,15432, 5024,19528, 5032,23624, + 5040,27720, 5048,31816, 5064,7752, 5072,11848, 5080,15944, 5088,20040, + 5096,24136, 5104,28232, 5112,32328, 5136,8328, 5144,12424, 5152,16520, + 5160,20616, 5168,24712, 5176,28808, 5200,8840, 5208,12936, 5216,17032, + 5224,21128, 5232,25224, 5240,29320, 5264,9352, 5272,13448, 5280,17544, + 5288,21640, 5296,25736, 5304,29832, 5320,5768, 5328,9864, 5336,13960, + 5344,18056, 5352,22152, 5360,26248, 5368,30344, 5384,6280, 5392,10376, + 5400,14472, 5408,18568, 5416,22664, 5424,26760, 5432,30856, 5448,6792, + 5456,10888, 5464,14984, 5472,19080, 5480,23176, 5488,27272, 5496,31368, + 5512,7304, 5520,11400, 5528,15496, 5536,19592, 5544,23688, 5552,27784, + 5560,31880, 5576,7816, 5584,11912, 5592,16008, 5600,20104, 5608,24200, + 5616,28296, 5624,32392, 5648,8392, 5656,12488, 5664,16584, 5672,20680, + 5680,24776, 5688,28872, 5712,8904, 5720,13000, 5728,17096, 5736,21192, + 5744,25288, 5752,29384, 5776,9416, 5784,13512, 5792,17608, 5800,21704, + 5808,25800, 5816,29896, 5840,9928, 5848,14024, 5856,18120, 5864,22216, + 5872,26312, 5880,30408, 5896,6344, 5904,10440, 5912,14536, 5920,18632, + 5928,22728, 5936,26824, 5944,30920, 5960,6856, 5968,10952, 5976,15048, + 5984,19144, 5992,23240, 6000,27336, 6008,31432, 6024,7368, 6032,11464, + 6040,15560, 6048,19656, 6056,23752, 6064,27848, 6072,31944, 6088,7880, + 6096,11976, 6104,16072, 6112,20168, 6120,24264, 6128,28360, 6136,32456, + 6160,8456, 6168,12552, 6176,16648, 6184,20744, 6192,24840, 6200,28936, + 6224,8968, 6232,13064, 6240,17160, 6248,21256, 6256,25352, 6264,29448, + 6288,9480, 6296,13576, 6304,17672, 6312,21768, 6320,25864, 6328,29960, + 6352,9992, 6360,14088, 6368,18184, 6376,22280, 6384,26376, 6392,30472, + 6416,10504, 6424,14600, 6432,18696, 6440,22792, 6448,26888, 6456,30984, + 6472,6920, 6480,11016, 6488,15112, 6496,19208, 6504,23304, 6512,27400, + 6520,31496, 6536,7432, 6544,11528, 6552,15624, 6560,19720, 6568,23816, + 6576,27912, 6584,32008, 6600,7944, 6608,12040, 6616,16136, 6624,20232, + 6632,24328, 6640,28424, 6648,32520, 6672,8520, 6680,12616, 6688,16712, + 6696,20808, 6704,24904, 6712,29000, 6736,9032, 6744,13128, 6752,17224, + 6760,21320, 6768,25416, 6776,29512, 6800,9544, 6808,13640, 6816,17736, + 6824,21832, 6832,25928, 6840,30024, 6864,10056, 6872,14152, 6880,18248, + 6888,22344, 6896,26440, 6904,30536, 6928,10568, 6936,14664, 6944,18760, + 6952,22856, 6960,26952, 6968,31048, 6992,11080, 7000,15176, 7008,19272, + 7016,23368, 7024,27464, 7032,31560, 7048,7496, 7056,11592, 7064,15688, + 7072,19784, 7080,23880, 7088,27976, 7096,32072, 7112,8008, 7120,12104, + 7128,16200, 7136,20296, 7144,24392, 7152,28488, 7160,32584, 7184,8584, + 7192,12680, 7200,16776, 7208,20872, 7216,24968, 7224,29064, 7248,9096, + 7256,13192, 7264,17288, 7272,21384, 7280,25480, 7288,29576, 7312,9608, + 7320,13704, 7328,17800, 7336,21896, 7344,25992, 7352,30088, 7376,10120, + 7384,14216, 7392,18312, 7400,22408, 7408,26504, 7416,30600, 7440,10632, + 7448,14728, 7456,18824, 7464,22920, 7472,27016, 7480,31112, 7504,11144, + 7512,15240, 7520,19336, 7528,23432, 7536,27528, 7544,31624, 7568,11656, + 7576,15752, 7584,19848, 7592,23944, 7600,28040, 7608,32136, 7624,8072, + 7632,12168, 7640,16264, 7648,20360, 7656,24456, 7664,28552, 7672,32648, + 7696,8648, 7704,12744, 7712,16840, 7720,20936, 7728,25032, 7736,29128, + 7760,9160, 7768,13256, 7776,17352, 7784,21448, 7792,25544, 7800,29640, + 7824,9672, 7832,13768, 7840,17864, 7848,21960, 7856,26056, 7864,30152, + 7888,10184, 7896,14280, 7904,18376, 7912,22472, 7920,26568, 7928,30664, + 7952,10696, 7960,14792, 7968,18888, 7976,22984, 7984,27080, 7992,31176, + 8016,11208, 8024,15304, 8032,19400, 8040,23496, 8048,27592, 8056,31688, + 8080,11720, 8088,15816, 8096,19912, 8104,24008, 8112,28104, 8120,32200, + 8144,12232, 8152,16328, 8160,20424, 8168,24520, 8176,28616, 8184,32712, + 8216,12304, 8224,16400, 8232,20496, 8240,24592, 8248,28688, 8272,8720, + 8280,12816, 8288,16912, 8296,21008, 8304,25104, 8312,29200, 8336,9232, + 8344,13328, 8352,17424, 8360,21520, 8368,25616, 8376,29712, 8400,9744, + 8408,13840, 8416,17936, 8424,22032, 8432,26128, 8440,30224, 8464,10256, + 8472,14352, 8480,18448, 8488,22544, 8496,26640, 8504,30736, 8528,10768, + 8536,14864, 8544,18960, 8552,23056, 8560,27152, 8568,31248, 8592,11280, + 8600,15376, 8608,19472, 8616,23568, 8624,27664, 8632,31760, 8656,11792, + 8664,15888, 8672,19984, 8680,24080, 8688,28176, 8696,32272, 8728,12368, + 8736,16464, 8744,20560, 8752,24656, 8760,28752, 8792,12880, 8800,16976, + 8808,21072, 8816,25168, 8824,29264, 8848,9296, 8856,13392, 8864,17488, + 8872,21584, 8880,25680, 8888,29776, 8912,9808, 8920,13904, 8928,18000, + 8936,22096, 8944,26192, 8952,30288, 8976,10320, 8984,14416, 8992,18512, + 9000,22608, 9008,26704, 9016,30800, 9040,10832, 9048,14928, 9056,19024, + 9064,23120, 9072,27216, 9080,31312, 9104,11344, 9112,15440, 9120,19536, + 9128,23632, 9136,27728, 9144,31824, 9168,11856, 9176,15952, 9184,20048, + 9192,24144, 9200,28240, 9208,32336, 9240,12432, 9248,16528, 9256,20624, + 9264,24720, 9272,28816, 9304,12944, 9312,17040, 9320,21136, 9328,25232, + 9336,29328, 9368,13456, 9376,17552, 9384,21648, 9392,25744, 9400,29840, + 9424,9872, 9432,13968, 9440,18064, 9448,22160, 9456,26256, 9464,30352, + 9488,10384, 9496,14480, 9504,18576, 9512,22672, 9520,26768, 9528,30864, + 9552,10896, 9560,14992, 9568,19088, 9576,23184, 9584,27280, 9592,31376, + 9616,11408, 9624,15504, 9632,19600, 9640,23696, 9648,27792, 9656,31888, + 9680,11920, 9688,16016, 9696,20112, 9704,24208, 9712,28304, 9720,32400, + 9752,12496, 9760,16592, 9768,20688, 9776,24784, 9784,28880, 9816,13008, + 9824,17104, 9832,21200, 9840,25296, 9848,29392, 9880,13520, 9888,17616, + 9896,21712, 9904,25808, 9912,29904, 9944,14032, 9952,18128, 9960,22224, + 9968,26320, 9976,30416, 10000,10448, 10008,14544, 10016,18640, 10024,22736, + 10032,26832, 10040,30928, 10064,10960, 10072,15056, 10080,19152, + 10088,23248, 10096,27344, 10104,31440, 10128,11472, 10136,15568, + 10144,19664, 10152,23760, 10160,27856, 10168,31952, 10192,11984, + 10200,16080, 10208,20176, 10216,24272, 10224,28368, 10232,32464, + 10264,12560, 10272,16656, 10280,20752, 10288,24848, 10296,28944, + 10328,13072, 10336,17168, 10344,21264, 10352,25360, 10360,29456, + 10392,13584, 10400,17680, 10408,21776, 10416,25872, 10424,29968, + 10456,14096, 10464,18192, 10472,22288, 10480,26384, 10488,30480, + 10520,14608, 10528,18704, 10536,22800, 10544,26896, 10552,30992, + 10576,11024, 10584,15120, 10592,19216, 10600,23312, 10608,27408, + 10616,31504, 10640,11536, 10648,15632, 10656,19728, 10664,23824, + 10672,27920, 10680,32016, 10704,12048, 10712,16144, 10720,20240, + 10728,24336, 10736,28432, 10744,32528, 10776,12624, 10784,16720, + 10792,20816, 10800,24912, 10808,29008, 10840,13136, 10848,17232, + 10856,21328, 10864,25424, 10872,29520, 10904,13648, 10912,17744, + 10920,21840, 10928,25936, 10936,30032, 10968,14160, 10976,18256, + 10984,22352, 10992,26448, 11000,30544, 11032,14672, 11040,18768, + 11048,22864, 11056,26960, 11064,31056, 11096,15184, 11104,19280, + 11112,23376, 11120,27472, 11128,31568, 11152,11600, 11160,15696, + 11168,19792, 11176,23888, 11184,27984, 11192,32080, 11216,12112, + 11224,16208, 11232,20304, 11240,24400, 11248,28496, 11256,32592, + 11288,12688, 11296,16784, 11304,20880, 11312,24976, 11320,29072, + 11352,13200, 11360,17296, 11368,21392, 11376,25488, 11384,29584, + 11416,13712, 11424,17808, 11432,21904, 11440,26000, 11448,30096, + 11480,14224, 11488,18320, 11496,22416, 11504,26512, 11512,30608, + 11544,14736, 11552,18832, 11560,22928, 11568,27024, 11576,31120, + 11608,15248, 11616,19344, 11624,23440, 11632,27536, 11640,31632, + 11672,15760, 11680,19856, 11688,23952, 11696,28048, 11704,32144, + 11728,12176, 11736,16272, 11744,20368, 11752,24464, 11760,28560, + 11768,32656, 11800,12752, 11808,16848, 11816,20944, 11824,25040, + 11832,29136, 11864,13264, 11872,17360, 11880,21456, 11888,25552, + 11896,29648, 11928,13776, 11936,17872, 11944,21968, 11952,26064, + 11960,30160, 11992,14288, 12000,18384, 12008,22480, 12016,26576, + 12024,30672, 12056,14800, 12064,18896, 12072,22992, 12080,27088, + 12088,31184, 12120,15312, 12128,19408, 12136,23504, 12144,27600, + 12152,31696, 12184,15824, 12192,19920, 12200,24016, 12208,28112, + 12216,32208, 12248,16336, 12256,20432, 12264,24528, 12272,28624, + 12280,32720, 12320,16408, 12328,20504, 12336,24600, 12344,28696, + 12376,12824, 12384,16920, 12392,21016, 12400,25112, 12408,29208, + 12440,13336, 12448,17432, 12456,21528, 12464,25624, 12472,29720, + 12504,13848, 12512,17944, 12520,22040, 12528,26136, 12536,30232, + 12568,14360, 12576,18456, 12584,22552, 12592,26648, 12600,30744, + 12632,14872, 12640,18968, 12648,23064, 12656,27160, 12664,31256, + 12696,15384, 12704,19480, 12712,23576, 12720,27672, 12728,31768, + 12760,15896, 12768,19992, 12776,24088, 12784,28184, 12792,32280, + 12832,16472, 12840,20568, 12848,24664, 12856,28760, 12896,16984, + 12904,21080, 12912,25176, 12920,29272, 12952,13400, 12960,17496, + 12968,21592, 12976,25688, 12984,29784, 13016,13912, 13024,18008, + 13032,22104, 13040,26200, 13048,30296, 13080,14424, 13088,18520, + 13096,22616, 13104,26712, 13112,30808, 13144,14936, 13152,19032, + 13160,23128, 13168,27224, 13176,31320, 13208,15448, 13216,19544, + 13224,23640, 13232,27736, 13240,31832, 13272,15960, 13280,20056, + 13288,24152, 13296,28248, 13304,32344, 13344,16536, 13352,20632, + 13360,24728, 13368,28824, 13408,17048, 13416,21144, 13424,25240, + 13432,29336, 13472,17560, 13480,21656, 13488,25752, 13496,29848, + 13528,13976, 13536,18072, 13544,22168, 13552,26264, 13560,30360, + 13592,14488, 13600,18584, 13608,22680, 13616,26776, 13624,30872, + 13656,15000, 13664,19096, 13672,23192, 13680,27288, 13688,31384, + 13720,15512, 13728,19608, 13736,23704, 13744,27800, 13752,31896, + 13784,16024, 13792,20120, 13800,24216, 13808,28312, 13816,32408, + 13856,16600, 13864,20696, 13872,24792, 13880,28888, 13920,17112, + 13928,21208, 13936,25304, 13944,29400, 13984,17624, 13992,21720, + 14000,25816, 14008,29912, 14048,18136, 14056,22232, 14064,26328, + 14072,30424, 14104,14552, 14112,18648, 14120,22744, 14128,26840, + 14136,30936, 14168,15064, 14176,19160, 14184,23256, 14192,27352, + 14200,31448, 14232,15576, 14240,19672, 14248,23768, 14256,27864, + 14264,31960, 14296,16088, 14304,20184, 14312,24280, 14320,28376, + 14328,32472, 14368,16664, 14376,20760, 14384,24856, 14392,28952, + 14432,17176, 14440,21272, 14448,25368, 14456,29464, 14496,17688, + 14504,21784, 14512,25880, 14520,29976, 14560,18200, 14568,22296, + 14576,26392, 14584,30488, 14624,18712, 14632,22808, 14640,26904, + 14648,31000, 14680,15128, 14688,19224, 14696,23320, 14704,27416, + 14712,31512, 14744,15640, 14752,19736, 14760,23832, 14768,27928, + 14776,32024, 14808,16152, 14816,20248, 14824,24344, 14832,28440, + 14840,32536, 14880,16728, 14888,20824, 14896,24920, 14904,29016, + 14944,17240, 14952,21336, 14960,25432, 14968,29528, 15008,17752, + 15016,21848, 15024,25944, 15032,30040, 15072,18264, 15080,22360, + 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968, + 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576, + 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088, + 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600, + 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304, + 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912, + 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520, + 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128, + 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864, + 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376, + 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952, + 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560, + 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168, + 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904, + 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512, + 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120, + 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728, + 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024, + 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632, + 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240, + 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976, + 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584, + 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192, + 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088, + 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696, + 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304, + 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040, + 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648, + 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256, + 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152, + 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856, + 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592, + 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200, + 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808, + 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416, + 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312, + 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240, + 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848, + 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456, + 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192, + 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864, + 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792, + 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496, + 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328, + 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936, + 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544, + 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440, + 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368, + 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072, + 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904, + 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512, + 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408, + 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112, + 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040, + 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968, + 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576, + 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472, + 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176, + 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104, + 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032, + 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736, + 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224, + 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152, + 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080, + 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784, + 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776, + 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800, + 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728, + 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656, + 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360, + 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768, + 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696, + 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400, + 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328, + 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416, + 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760, + 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464, + 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392, + 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480, + 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920, + 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848, + 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552, + 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960, + 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080, + 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104, + 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096, + 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536, + 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656, + 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680, + 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088, + 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208, + 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648, + 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648, + 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768, + 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208, + 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808, + 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248, + 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368, + 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384, + 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824, + 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424, + 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376, + 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496, + 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024, + 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464, + 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576, + 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528, + 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640, + 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688, + 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216, + 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752, + 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312, + 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864, + 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928, + 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504, + 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632, + 32248,32696 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + +const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH] = +{ + /* radix 4, size 12 */ + 8,64, 16,32, 24,96, 40,80, 56,112, 88,104 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) +const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH] = +{ + /* 4x2, size 24 */ + 8,128, 16,64, 24,192, 40,160, 48,96, 56,224, 72,144, + 88,208, 104,176, 120,240, 152,200, 184,232 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) +const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH] = +{ + /* radix 4, size 56 */ + 8,256, 16,128, 24,384, 32,64, 40,320, 48,192, 56,448, 72,288, 80,160, 88,416, 104,352, + 112,224, 120,480, 136,272, 152,400, 168,336, 176,208, 184,464, 200,304, 216,432, + 232,368, 248,496, 280,392, 296,328, 312,456, 344,424, 376,488, 440,472 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) +const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH] = +{ + /* 4x2, size 112 */ + 8,512, 16,256, 24,768, 32,128, 40,640, 48,384, 56,896, 72,576, 80,320, 88,832, 96,192, + 104,704, 112,448, 120,960, 136,544, 144,288, 152,800, 168,672, 176,416, 184,928, 200,608, + 208,352, 216,864, 232,736, 240,480, 248,992, 264,528, 280,784, 296,656, 304,400, 312,912, + 328,592, 344,848, 360,720, 368,464, 376,976, 392,560, 408,816, 424,688, 440,944, 456,624, + 472,880, 488,752, 504,1008, 536,776, 552,648, 568,904, 600,840, 616,712, 632,968, + 664,808, 696,936, 728,872, 760,1000, 824,920, 888,984 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) +const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH] = +{ + /* radix 4, size 240 */ + 8,1024, 16,512, 24,1536, 32,256, 40,1280, 48,768, 56,1792, 64,128, 72,1152, 80,640, + 88,1664, 96,384, 104,1408, 112,896, 120,1920, 136,1088, 144,576, 152,1600, 160,320, + 168,1344, 176,832, 184,1856, 200,1216, 208,704, 216,1728, 224,448, 232,1472, 240,960, + 248,1984, 264,1056, 272,544, 280,1568, 296,1312, 304,800, 312,1824, 328,1184, 336,672, + 344,1696, 352,416, 360,1440, 368,928, 376,1952, 392,1120, 400,608, 408,1632, 424,1376, + 432,864, 440,1888, 456,1248, 464,736, 472,1760, 488,1504, 496,992, 504,2016, 520,1040, + 536,1552, 552,1296, 560,784, 568,1808, 584,1168, 592,656, 600,1680, 616,1424, 624,912, + 632,1936, 648,1104, 664,1616, 680,1360, 688,848, 696,1872, 712,1232, 728,1744, 744,1488, + 752,976, 760,2000, 776,1072, 792,1584, 808,1328, 824,1840, 840,1200, 856,1712, 872,1456, + 880,944, 888,1968, 904,1136, 920,1648, 936,1392, 952,1904, 968,1264, 984,1776, 1000,1520, + 1016,2032, 1048,1544, 1064,1288, 1080,1800, 1096,1160, 1112,1672, 1128,1416, 1144,1928, + 1176,1608, 1192,1352, 1208,1864, 1240,1736, 1256,1480, 1272,1992, 1304,1576, 1336,1832, + 1368,1704, 1384,1448, 1400,1960, 1432,1640, 1464,1896, 1496,1768, 1528,2024, 1592,1816, + 1624,1688, 1656,1944, 1720,1880, 1784,2008, 1912,1976 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) +const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH] = +{ + /* 4x2, size 480 */ + 8,2048, 16,1024, 24,3072, 32,512, 40,2560, 48,1536, 56,3584, 64,256, 72,2304, 80,1280, + 88,3328, 96,768, 104,2816, 112,1792, 120,3840, 136,2176, 144,1152, 152,3200, 160,640, + 168,2688, 176,1664, 184,3712, 192,384, 200,2432, 208,1408, 216,3456, 224,896, 232,2944, + 240,1920, 248,3968, 264,2112, 272,1088, 280,3136, 288,576, 296,2624, 304,1600, 312,3648, + 328,2368, 336,1344, 344,3392, 352,832, 360,2880, 368,1856, 376,3904, 392,2240, 400,1216, + 408,3264, 416,704, 424,2752, 432,1728, 440,3776, 456,2496, 464,1472, 472,3520, 480,960, + 488,3008, 496,1984, 504,4032, 520,2080, 528,1056, 536,3104, 552,2592, 560,1568, 568,3616, + 584,2336, 592,1312, 600,3360, 608,800, 616,2848, 624,1824, 632,3872, 648,2208, 656,1184, + 664,3232, 680,2720, 688,1696, 696,3744, 712,2464, 720,1440, 728,3488, 736,928, 744,2976, + 752,1952, 760,4000, 776,2144, 784,1120, 792,3168, 808,2656, 816,1632, 824,3680, 840,2400, + 848,1376, 856,3424, 872,2912, 880,1888, 888,3936, 904,2272, 912,1248, 920,3296, 936,2784, + 944,1760, 952,3808, 968,2528, 976,1504, 984,3552, 1000,3040, 1008,2016, 1016,4064, + 1032,2064, 1048,3088, 1064,2576, 1072,1552, 1080,3600, 1096,2320, 1104,1296, 1112,3344, + 1128,2832, 1136,1808, 1144,3856, 1160,2192, 1176,3216, 1192,2704, 1200,1680, 1208,3728, + 1224,2448, 1232,1424, 1240,3472, 1256,2960, 1264,1936, 1272,3984, 1288,2128, 1304,3152, + 1320,2640, 1328,1616, 1336,3664, 1352,2384, 1368,3408, 1384,2896, 1392,1872, 1400,3920, + 1416,2256, 1432,3280, 1448,2768, 1456,1744, 1464,3792, 1480,2512, 1496,3536, 1512,3024, + 1520,2000, 1528,4048, 1544,2096, 1560,3120, 1576,2608, 1592,3632, 1608,2352, 1624,3376, + 1640,2864, 1648,1840, 1656,3888, 1672,2224, 1688,3248, 1704,2736, 1720,3760, 1736,2480, + 1752,3504, 1768,2992, 1776,1968, 1784,4016, 1800,2160, 1816,3184, 1832,2672, 1848,3696, + 1864,2416, 1880,3440, 1896,2928, 1912,3952, 1928,2288, 1944,3312, 1960,2800, 1976,3824, + 1992,2544, 2008,3568, 2024,3056, 2040,4080, 2072,3080, 2088,2568, 2104,3592, 2120,2312, + 2136,3336, 2152,2824, 2168,3848, 2200,3208, 2216,2696, 2232,3720, 2248,2440, 2264,3464, + 2280,2952, 2296,3976, 2328,3144, 2344,2632, 2360,3656, 2392,3400, 2408,2888, 2424,3912, + 2456,3272, 2472,2760, 2488,3784, 2520,3528, 2536,3016, 2552,4040, 2584,3112, 2616,3624, + 2648,3368, 2664,2856, 2680,3880, 2712,3240, 2744,3752, 2776,3496, 2792,2984, 2808,4008, + 2840,3176, 2872,3688, 2904,3432, 2936,3944, 2968,3304, 3000,3816, 3032,3560, 3064,4072, + 3128,3608, 3160,3352, 3192,3864, 3256,3736, 3288,3480, 3320,3992, 3384,3672, 3448,3928, + 3512,3800, 3576,4056, 3704,3896, 3832,4024 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) +const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH] = +{ + /* radix 4, size 992 */ + 8,4096, 16,2048, 24,6144, 32,1024, 40,5120, 48,3072, 56,7168, 64,512, 72,4608, + 80,2560, 88,6656, 96,1536, 104,5632, 112,3584, 120,7680, 128,256, 136,4352, + 144,2304, 152,6400, 160,1280, 168,5376, 176,3328, 184,7424, 192,768, 200,4864, + 208,2816, 216,6912, 224,1792, 232,5888, 240,3840, 248,7936, 264,4224, 272,2176, + 280,6272, 288,1152, 296,5248, 304,3200, 312,7296, 320,640, 328,4736, 336,2688, + 344,6784, 352,1664, 360,5760, 368,3712, 376,7808, 392,4480, 400,2432, 408,6528, + 416,1408, 424,5504, 432,3456, 440,7552, 448,896, 456,4992, 464,2944, 472,7040, + 480,1920, 488,6016, 496,3968, 504,8064, 520,4160, 528,2112, 536,6208, 544,1088, + 552,5184, 560,3136, 568,7232, 584,4672, 592,2624, 600,6720, 608,1600, 616,5696, + 624,3648, 632,7744, 648,4416, 656,2368, 664,6464, 672,1344, 680,5440, 688,3392, + 696,7488, 704,832, 712,4928, 720,2880, 728,6976, 736,1856, 744,5952, 752,3904, + 760,8000, 776,4288, 784,2240, 792,6336, 800,1216, 808,5312, 816,3264, 824,7360, + 840,4800, 848,2752, 856,6848, 864,1728, 872,5824, 880,3776, 888,7872, 904,4544, + 912,2496, 920,6592, 928,1472, 936,5568, 944,3520, 952,7616, 968,5056, 976,3008, + 984,7104, 992,1984, 1000,6080, 1008,4032, 1016,8128, 1032,4128, 1040,2080, + 1048,6176, 1064,5152, 1072,3104, 1080,7200, 1096,4640, 1104,2592, 1112,6688, + 1120,1568, 1128,5664, 1136,3616, 1144,7712, 1160,4384, 1168,2336, 1176,6432, + 1184,1312, 1192,5408, 1200,3360, 1208,7456, 1224,4896, 1232,2848, 1240,6944, + 1248,1824, 1256,5920, 1264,3872, 1272,7968, 1288,4256, 1296,2208, 1304,6304, + 1320,5280, 1328,3232, 1336,7328, 1352,4768, 1360,2720, 1368,6816, 1376,1696, + 1384,5792, 1392,3744, 1400,7840, 1416,4512, 1424,2464, 1432,6560, 1448,5536, + 1456,3488, 1464,7584, 1480,5024, 1488,2976, 1496,7072, 1504,1952, 1512,6048, + 1520,4000, 1528,8096, 1544,4192, 1552,2144, 1560,6240, 1576,5216, 1584,3168, + 1592,7264, 1608,4704, 1616,2656, 1624,6752, 1640,5728, 1648,3680, 1656,7776, + 1672,4448, 1680,2400, 1688,6496, 1704,5472, 1712,3424, 1720,7520, 1736,4960, + 1744,2912, 1752,7008, 1760,1888, 1768,5984, 1776,3936, 1784,8032, 1800,4320, + 1808,2272, 1816,6368, 1832,5344, 1840,3296, 1848,7392, 1864,4832, 1872,2784, + 1880,6880, 1896,5856, 1904,3808, 1912,7904, 1928,4576, 1936,2528, 1944,6624, + 1960,5600, 1968,3552, 1976,7648, 1992,5088, 2000,3040, 2008,7136, 2024,6112, + 2032,4064, 2040,8160, 2056,4112, 2072,6160, 2088,5136, 2096,3088, 2104,7184, + 2120,4624, 2128,2576, 2136,6672, 2152,5648, 2160,3600, 2168,7696, 2184,4368, + 2192,2320, 2200,6416, 2216,5392, 2224,3344, 2232,7440, 2248,4880, 2256,2832, + 2264,6928, 2280,5904, 2288,3856, 2296,7952, 2312,4240, 2328,6288, 2344,5264, + 2352,3216, 2360,7312, 2376,4752, 2384,2704, 2392,6800, 2408,5776, 2416,3728, + 2424,7824, 2440,4496, 2456,6544, 2472,5520, 2480,3472, 2488,7568, 2504,5008, + 2512,2960, 2520,7056, 2536,6032, 2544,3984, 2552,8080, 2568,4176, 2584,6224, + 2600,5200, 2608,3152, 2616,7248, 2632,4688, 2648,6736, 2664,5712, 2672,3664, + 2680,7760, 2696,4432, 2712,6480, 2728,5456, 2736,3408, 2744,7504, 2760,4944, + 2768,2896, 2776,6992, 2792,5968, 2800,3920, 2808,8016, 2824,4304, 2840,6352, + 2856,5328, 2864,3280, 2872,7376, 2888,4816, 2904,6864, 2920,5840, 2928,3792, + 2936,7888, 2952,4560, 2968,6608, 2984,5584, 2992,3536, 3000,7632, 3016,5072, + 3032,7120, 3048,6096, 3056,4048, 3064,8144, 3080,4144, 3096,6192, 3112,5168, + 3128,7216, 3144,4656, 3160,6704, 3176,5680, 3184,3632, 3192,7728, 3208,4400, + 3224,6448, 3240,5424, 3248,3376, 3256,7472, 3272,4912, 3288,6960, 3304,5936, + 3312,3888, 3320,7984, 3336,4272, 3352,6320, 3368,5296, 3384,7344, 3400,4784, + 3416,6832, 3432,5808, 3440,3760, 3448,7856, 3464,4528, 3480,6576, 3496,5552, + 3512,7600, 3528,5040, 3544,7088, 3560,6064, 3568,4016, 3576,8112, 3592,4208, + 3608,6256, 3624,5232, 3640,7280, 3656,4720, 3672,6768, 3688,5744, 3704,7792, + 3720,4464, 3736,6512, 3752,5488, 3768,7536, 3784,4976, 3800,7024, 3816,6000, + 3824,3952, 3832,8048, 3848,4336, 3864,6384, 3880,5360, 3896,7408, 3912,4848, + 3928,6896, 3944,5872, 3960,7920, 3976,4592, 3992,6640, 4008,5616, 4024,7664, + 4040,5104, 4056,7152, 4072,6128, 4088,8176, 4120,6152, 4136,5128, 4152,7176, + 4168,4616, 4184,6664, 4200,5640, 4216,7688, 4232,4360, 4248,6408, 4264,5384, + 4280,7432, 4296,4872, 4312,6920, 4328,5896, 4344,7944, 4376,6280, 4392,5256, + 4408,7304, 4424,4744, 4440,6792, 4456,5768, 4472,7816, 4504,6536, 4520,5512, + 4536,7560, 4552,5000, 4568,7048, 4584,6024, 4600,8072, 4632,6216, 4648,5192, + 4664,7240, 4696,6728, 4712,5704, 4728,7752, 4760,6472, 4776,5448, 4792,7496, + 4808,4936, 4824,6984, 4840,5960, 4856,8008, 4888,6344, 4904,5320, 4920,7368, + 4952,6856, 4968,5832, 4984,7880, 5016,6600, 5032,5576, 5048,7624, 5080,7112, + 5096,6088, 5112,8136, 5144,6184, 5176,7208, 5208,6696, 5224,5672, 5240,7720, + 5272,6440, 5288,5416, 5304,7464, 5336,6952, 5352,5928, 5368,7976, 5400,6312, + 5432,7336, 5464,6824, 5480,5800, 5496,7848, 5528,6568, 5560,7592, 5592,7080, + 5608,6056, 5624,8104, 5656,6248, 5688,7272, 5720,6760, 5752,7784, 5784,6504, + 5816,7528, 5848,7016, 5864,5992, 5880,8040, 5912,6376, 5944,7400, 5976,6888, + 6008,7912, 6040,6632, 6072,7656, 6104,7144, 6136,8168, 6200,7192, 6232,6680, + 6264,7704, 6296,6424, 6328,7448, 6360,6936, 6392,7960, 6456,7320, 6488,6808, + 6520,7832, 6584,7576, 6616,7064, 6648,8088, 6712,7256, 6776,7768, 6840,7512, + 6872,7000, 6904,8024, 6968,7384, 7032,7896, 7096,7640, 7160,8152, 7288,7736, + 7352,7480, 7416,7992, 7544,7864, 7672,8120, 7928,8056 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) +const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH] = +{ + /* 4x2, size 1984 */ + 8,8192, 16,4096, 24,12288, 32,2048, 40,10240, 48,6144, 56,14336, 64,1024, + 72,9216, 80,5120, 88,13312, 96,3072, 104,11264, 112,7168, 120,15360, 128,512, + 136,8704, 144,4608, 152,12800, 160,2560, 168,10752, 176,6656, 184,14848, + 192,1536, 200,9728, 208,5632, 216,13824, 224,3584, 232,11776, 240,7680, + 248,15872, 264,8448, 272,4352, 280,12544, 288,2304, 296,10496, 304,6400, + 312,14592, 320,1280, 328,9472, 336,5376, 344,13568, 352,3328, 360,11520, + 368,7424, 376,15616, 384,768, 392,8960, 400,4864, 408,13056, 416,2816, + 424,11008, 432,6912, 440,15104, 448,1792, 456,9984, 464,5888, 472,14080, + 480,3840, 488,12032, 496,7936, 504,16128, 520,8320, 528,4224, 536,12416, + 544,2176, 552,10368, 560,6272, 568,14464, 576,1152, 584,9344, 592,5248, + 600,13440, 608,3200, 616,11392, 624,7296, 632,15488, 648,8832, 656,4736, + 664,12928, 672,2688, 680,10880, 688,6784, 696,14976, 704,1664, 712,9856, + 720,5760, 728,13952, 736,3712, 744,11904, 752,7808, 760,16000, 776,8576, + 784,4480, 792,12672, 800,2432, 808,10624, 816,6528, 824,14720, 832,1408, + 840,9600, 848,5504, 856,13696, 864,3456, 872,11648, 880,7552, 888,15744, + 904,9088, 912,4992, 920,13184, 928,2944, 936,11136, 944,7040, 952,15232, + 960,1920, 968,10112, 976,6016, 984,14208, 992,3968, 1000,12160, 1008,8064, + 1016,16256, 1032,8256, 1040,4160, 1048,12352, 1056,2112, 1064,10304, 1072,6208, + 1080,14400, 1096,9280, 1104,5184, 1112,13376, 1120,3136, 1128,11328, 1136,7232, + 1144,15424, 1160,8768, 1168,4672, 1176,12864, 1184,2624, 1192,10816, 1200,6720, + 1208,14912, 1216,1600, 1224,9792, 1232,5696, 1240,13888, 1248,3648, 1256,11840, + 1264,7744, 1272,15936, 1288,8512, 1296,4416, 1304,12608, 1312,2368, 1320,10560, + 1328,6464, 1336,14656, 1352,9536, 1360,5440, 1368,13632, 1376,3392, 1384,11584, + 1392,7488, 1400,15680, 1416,9024, 1424,4928, 1432,13120, 1440,2880, 1448,11072, + 1456,6976, 1464,15168, 1472,1856, 1480,10048, 1488,5952, 1496,14144, 1504,3904, + 1512,12096, 1520,8000, 1528,16192, 1544,8384, 1552,4288, 1560,12480, 1568,2240, + 1576,10432, 1584,6336, 1592,14528, 1608,9408, 1616,5312, 1624,13504, 1632,3264, + 1640,11456, 1648,7360, 1656,15552, 1672,8896, 1680,4800, 1688,12992, 1696,2752, + 1704,10944, 1712,6848, 1720,15040, 1736,9920, 1744,5824, 1752,14016, 1760,3776, + 1768,11968, 1776,7872, 1784,16064, 1800,8640, 1808,4544, 1816,12736, 1824,2496, + 1832,10688, 1840,6592, 1848,14784, 1864,9664, 1872,5568, 1880,13760, 1888,3520, + 1896,11712, 1904,7616, 1912,15808, 1928,9152, 1936,5056, 1944,13248, 1952,3008, + 1960,11200, 1968,7104, 1976,15296, 1992,10176, 2000,6080, 2008,14272, 2016,4032, + 2024,12224, 2032,8128, 2040,16320, 2056,8224, 2064,4128, 2072,12320, 2088,10272, + 2096,6176, 2104,14368, 2120,9248, 2128,5152, 2136,13344, 2144,3104, 2152,11296, + 2160,7200, 2168,15392, 2184,8736, 2192,4640, 2200,12832, 2208,2592, 2216,10784, + 2224,6688, 2232,14880, 2248,9760, 2256,5664, 2264,13856, 2272,3616, 2280,11808, + 2288,7712, 2296,15904, 2312,8480, 2320,4384, 2328,12576, 2344,10528, 2352,6432, + 2360,14624, 2376,9504, 2384,5408, 2392,13600, 2400,3360, 2408,11552, 2416,7456, + 2424,15648, 2440,8992, 2448,4896, 2456,13088, 2464,2848, 2472,11040, 2480,6944, + 2488,15136, 2504,10016, 2512,5920, 2520,14112, 2528,3872, 2536,12064, 2544,7968, + 2552,16160, 2568,8352, 2576,4256, 2584,12448, 2600,10400, 2608,6304, 2616,14496, + 2632,9376, 2640,5280, 2648,13472, 2656,3232, 2664,11424, 2672,7328, 2680,15520, + 2696,8864, 2704,4768, 2712,12960, 2728,10912, 2736,6816, 2744,15008, 2760,9888, + 2768,5792, 2776,13984, 2784,3744, 2792,11936, 2800,7840, 2808,16032, 2824,8608, + 2832,4512, 2840,12704, 2856,10656, 2864,6560, 2872,14752, 2888,9632, 2896,5536, + 2904,13728, 2912,3488, 2920,11680, 2928,7584, 2936,15776, 2952,9120, 2960,5024, + 2968,13216, 2984,11168, 2992,7072, 3000,15264, 3016,10144, 3024,6048, + 3032,14240, 3040,4000, 3048,12192, 3056,8096, 3064,16288, 3080,8288, 3088,4192, + 3096,12384, 3112,10336, 3120,6240, 3128,14432, 3144,9312, 3152,5216, 3160,13408, + 3176,11360, 3184,7264, 3192,15456, 3208,8800, 3216,4704, 3224,12896, 3240,10848, + 3248,6752, 3256,14944, 3272,9824, 3280,5728, 3288,13920, 3296,3680, 3304,11872, + 3312,7776, 3320,15968, 3336,8544, 3344,4448, 3352,12640, 3368,10592, 3376,6496, + 3384,14688, 3400,9568, 3408,5472, 3416,13664, 3432,11616, 3440,7520, 3448,15712, + 3464,9056, 3472,4960, 3480,13152, 3496,11104, 3504,7008, 3512,15200, 3528,10080, + 3536,5984, 3544,14176, 3552,3936, 3560,12128, 3568,8032, 3576,16224, 3592,8416, + 3600,4320, 3608,12512, 3624,10464, 3632,6368, 3640,14560, 3656,9440, 3664,5344, + 3672,13536, 3688,11488, 3696,7392, 3704,15584, 3720,8928, 3728,4832, 3736,13024, + 3752,10976, 3760,6880, 3768,15072, 3784,9952, 3792,5856, 3800,14048, 3816,12000, + 3824,7904, 3832,16096, 3848,8672, 3856,4576, 3864,12768, 3880,10720, 3888,6624, + 3896,14816, 3912,9696, 3920,5600, 3928,13792, 3944,11744, 3952,7648, 3960,15840, + 3976,9184, 3984,5088, 3992,13280, 4008,11232, 4016,7136, 4024,15328, 4040,10208, + 4048,6112, 4056,14304, 4072,12256, 4080,8160, 4088,16352, 4104,8208, 4120,12304, + 4136,10256, 4144,6160, 4152,14352, 4168,9232, 4176,5136, 4184,13328, 4200,11280, + 4208,7184, 4216,15376, 4232,8720, 4240,4624, 4248,12816, 4264,10768, 4272,6672, + 4280,14864, 4296,9744, 4304,5648, 4312,13840, 4328,11792, 4336,7696, 4344,15888, + 4360,8464, 4376,12560, 4392,10512, 4400,6416, 4408,14608, 4424,9488, 4432,5392, + 4440,13584, 4456,11536, 4464,7440, 4472,15632, 4488,8976, 4496,4880, 4504,13072, + 4520,11024, 4528,6928, 4536,15120, 4552,10000, 4560,5904, 4568,14096, + 4584,12048, 4592,7952, 4600,16144, 4616,8336, 4632,12432, 4648,10384, 4656,6288, + 4664,14480, 4680,9360, 4688,5264, 4696,13456, 4712,11408, 4720,7312, 4728,15504, + 4744,8848, 4760,12944, 4776,10896, 4784,6800, 4792,14992, 4808,9872, 4816,5776, + 4824,13968, 4840,11920, 4848,7824, 4856,16016, 4872,8592, 4888,12688, + 4904,10640, 4912,6544, 4920,14736, 4936,9616, 4944,5520, 4952,13712, 4968,11664, + 4976,7568, 4984,15760, 5000,9104, 5016,13200, 5032,11152, 5040,7056, 5048,15248, + 5064,10128, 5072,6032, 5080,14224, 5096,12176, 5104,8080, 5112,16272, 5128,8272, + 5144,12368, 5160,10320, 5168,6224, 5176,14416, 5192,9296, 5208,13392, + 5224,11344, 5232,7248, 5240,15440, 5256,8784, 5272,12880, 5288,10832, 5296,6736, + 5304,14928, 5320,9808, 5328,5712, 5336,13904, 5352,11856, 5360,7760, 5368,15952, + 5384,8528, 5400,12624, 5416,10576, 5424,6480, 5432,14672, 5448,9552, 5464,13648, + 5480,11600, 5488,7504, 5496,15696, 5512,9040, 5528,13136, 5544,11088, 5552,6992, + 5560,15184, 5576,10064, 5584,5968, 5592,14160, 5608,12112, 5616,8016, + 5624,16208, 5640,8400, 5656,12496, 5672,10448, 5680,6352, 5688,14544, 5704,9424, + 5720,13520, 5736,11472, 5744,7376, 5752,15568, 5768,8912, 5784,13008, + 5800,10960, 5808,6864, 5816,15056, 5832,9936, 5848,14032, 5864,11984, 5872,7888, + 5880,16080, 5896,8656, 5912,12752, 5928,10704, 5936,6608, 5944,14800, 5960,9680, + 5976,13776, 5992,11728, 6000,7632, 6008,15824, 6024,9168, 6040,13264, + 6056,11216, 6064,7120, 6072,15312, 6088,10192, 6104,14288, 6120,12240, + 6128,8144, 6136,16336, 6152,8240, 6168,12336, 6184,10288, 6200,14384, 6216,9264, + 6232,13360, 6248,11312, 6256,7216, 6264,15408, 6280,8752, 6296,12848, + 6312,10800, 6320,6704, 6328,14896, 6344,9776, 6360,13872, 6376,11824, 6384,7728, + 6392,15920, 6408,8496, 6424,12592, 6440,10544, 6456,14640, 6472,9520, + 6488,13616, 6504,11568, 6512,7472, 6520,15664, 6536,9008, 6552,13104, + 6568,11056, 6576,6960, 6584,15152, 6600,10032, 6616,14128, 6632,12080, + 6640,7984, 6648,16176, 6664,8368, 6680,12464, 6696,10416, 6712,14512, 6728,9392, + 6744,13488, 6760,11440, 6768,7344, 6776,15536, 6792,8880, 6808,12976, + 6824,10928, 6840,15024, 6856,9904, 6872,14000, 6888,11952, 6896,7856, + 6904,16048, 6920,8624, 6936,12720, 6952,10672, 6968,14768, 6984,9648, + 7000,13744, 7016,11696, 7024,7600, 7032,15792, 7048,9136, 7064,13232, + 7080,11184, 7096,15280, 7112,10160, 7128,14256, 7144,12208, 7152,8112, + 7160,16304, 7176,8304, 7192,12400, 7208,10352, 7224,14448, 7240,9328, + 7256,13424, 7272,11376, 7288,15472, 7304,8816, 7320,12912, 7336,10864, + 7352,14960, 7368,9840, 7384,13936, 7400,11888, 7408,7792, 7416,15984, 7432,8560, + 7448,12656, 7464,10608, 7480,14704, 7496,9584, 7512,13680, 7528,11632, + 7544,15728, 7560,9072, 7576,13168, 7592,11120, 7608,15216, 7624,10096, + 7640,14192, 7656,12144, 7664,8048, 7672,16240, 7688,8432, 7704,12528, + 7720,10480, 7736,14576, 7752,9456, 7768,13552, 7784,11504, 7800,15600, + 7816,8944, 7832,13040, 7848,10992, 7864,15088, 7880,9968, 7896,14064, + 7912,12016, 7928,16112, 7944,8688, 7960,12784, 7976,10736, 7992,14832, + 8008,9712, 8024,13808, 8040,11760, 8056,15856, 8072,9200, 8088,13296, + 8104,11248, 8120,15344, 8136,10224, 8152,14320, 8168,12272, 8184,16368, + 8216,12296, 8232,10248, 8248,14344, 8264,9224, 8280,13320, 8296,11272, + 8312,15368, 8328,8712, 8344,12808, 8360,10760, 8376,14856, 8392,9736, + 8408,13832, 8424,11784, 8440,15880, 8472,12552, 8488,10504, 8504,14600, + 8520,9480, 8536,13576, 8552,11528, 8568,15624, 8584,8968, 8600,13064, + 8616,11016, 8632,15112, 8648,9992, 8664,14088, 8680,12040, 8696,16136, + 8728,12424, 8744,10376, 8760,14472, 8776,9352, 8792,13448, 8808,11400, + 8824,15496, 8856,12936, 8872,10888, 8888,14984, 8904,9864, 8920,13960, + 8936,11912, 8952,16008, 8984,12680, 9000,10632, 9016,14728, 9032,9608, + 9048,13704, 9064,11656, 9080,15752, 9112,13192, 9128,11144, 9144,15240, + 9160,10120, 9176,14216, 9192,12168, 9208,16264, 9240,12360, 9256,10312, + 9272,14408, 9304,13384, 9320,11336, 9336,15432, 9368,12872, 9384,10824, + 9400,14920, 9416,9800, 9432,13896, 9448,11848, 9464,15944, 9496,12616, + 9512,10568, 9528,14664, 9560,13640, 9576,11592, 9592,15688, 9624,13128, + 9640,11080, 9656,15176, 9672,10056, 9688,14152, 9704,12104, 9720,16200, + 9752,12488, 9768,10440, 9784,14536, 9816,13512, 9832,11464, 9848,15560, + 9880,13000, 9896,10952, 9912,15048, 9944,14024, 9960,11976, 9976,16072, + 10008,12744, 10024,10696, 10040,14792, 10072,13768, 10088,11720, 10104,15816, + 10136,13256, 10152,11208, 10168,15304, 10200,14280, 10216,12232, 10232,16328, + 10264,12328, 10296,14376, 10328,13352, 10344,11304, 10360,15400, 10392,12840, + 10408,10792, 10424,14888, 10456,13864, 10472,11816, 10488,15912, 10520,12584, + 10552,14632, 10584,13608, 10600,11560, 10616,15656, 10648,13096, 10664,11048, + 10680,15144, 10712,14120, 10728,12072, 10744,16168, 10776,12456, 10808,14504, + 10840,13480, 10856,11432, 10872,15528, 10904,12968, 10936,15016, 10968,13992, + 10984,11944, 11000,16040, 11032,12712, 11064,14760, 11096,13736, 11112,11688, + 11128,15784, 11160,13224, 11192,15272, 11224,14248, 11240,12200, 11256,16296, + 11288,12392, 11320,14440, 11352,13416, 11384,15464, 11416,12904, 11448,14952, + 11480,13928, 11496,11880, 11512,15976, 11544,12648, 11576,14696, 11608,13672, + 11640,15720, 11672,13160, 11704,15208, 11736,14184, 11752,12136, 11768,16232, + 11800,12520, 11832,14568, 11864,13544, 11896,15592, 11928,13032, 11960,15080, + 11992,14056, 12024,16104, 12056,12776, 12088,14824, 12120,13800, 12152,15848, + 12184,13288, 12216,15336, 12248,14312, 12280,16360, 12344,14360, 12376,13336, + 12408,15384, 12440,12824, 12472,14872, 12504,13848, 12536,15896, 12600,14616, + 12632,13592, 12664,15640, 12696,13080, 12728,15128, 12760,14104, 12792,16152, + 12856,14488, 12888,13464, 12920,15512, 12984,15000, 13016,13976, 13048,16024, + 13112,14744, 13144,13720, 13176,15768, 13240,15256, 13272,14232, 13304,16280, + 13368,14424, 13432,15448, 13496,14936, 13528,13912, 13560,15960, 13624,14680, + 13688,15704, 13752,15192, 13784,14168, 13816,16216, 13880,14552, 13944,15576, + 14008,15064, 14072,16088, 14136,14808, 14200,15832, 14264,15320, 14328,16344, + 14456,15416, 14520,14904, 14584,15928, 14712,15672, 14776,15160, 14840,16184, + 14968,15544, 15096,16056, 15224,15800, 15352,16312, 15608,15992, 15864,16248 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) +const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH] = +{ + /* radix 4, size 4032 */ + 8,16384, 16,8192, 24,24576, 32,4096, 40,20480, 48,12288, 56,28672, 64,2048, + 72,18432, 80,10240, 88,26624, 96,6144, 104,22528, 112,14336, 120,30720, + 128,1024, 136,17408, 144,9216, 152,25600, 160,5120, 168,21504, 176,13312, + 184,29696, 192,3072, 200,19456, 208,11264, 216,27648, 224,7168, 232,23552, + 240,15360, 248,31744, 256,512, 264,16896, 272,8704, 280,25088, 288,4608, + 296,20992, 304,12800, 312,29184, 320,2560, 328,18944, 336,10752, 344,27136, + 352,6656, 360,23040, 368,14848, 376,31232, 384,1536, 392,17920, 400,9728, + 408,26112, 416,5632, 424,22016, 432,13824, 440,30208, 448,3584, 456,19968, + 464,11776, 472,28160, 480,7680, 488,24064, 496,15872, 504,32256, 520,16640, + 528,8448, 536,24832, 544,4352, 552,20736, 560,12544, 568,28928, 576,2304, + 584,18688, 592,10496, 600,26880, 608,6400, 616,22784, 624,14592, 632,30976, + 640,1280, 648,17664, 656,9472, 664,25856, 672,5376, 680,21760, 688,13568, + 696,29952, 704,3328, 712,19712, 720,11520, 728,27904, 736,7424, 744,23808, + 752,15616, 760,32000, 776,17152, 784,8960, 792,25344, 800,4864, 808,21248, + 816,13056, 824,29440, 832,2816, 840,19200, 848,11008, 856,27392, 864,6912, + 872,23296, 880,15104, 888,31488, 896,1792, 904,18176, 912,9984, 920,26368, + 928,5888, 936,22272, 944,14080, 952,30464, 960,3840, 968,20224, 976,12032, + 984,28416, 992,7936, 1000,24320, 1008,16128, 1016,32512, 1032,16512, 1040,8320, + 1048,24704, 1056,4224, 1064,20608, 1072,12416, 1080,28800, 1088,2176, + 1096,18560, 1104,10368, 1112,26752, 1120,6272, 1128,22656, 1136,14464, + 1144,30848, 1160,17536, 1168,9344, 1176,25728, 1184,5248, 1192,21632, + 1200,13440, 1208,29824, 1216,3200, 1224,19584, 1232,11392, 1240,27776, + 1248,7296, 1256,23680, 1264,15488, 1272,31872, 1288,17024, 1296,8832, + 1304,25216, 1312,4736, 1320,21120, 1328,12928, 1336,29312, 1344,2688, + 1352,19072, 1360,10880, 1368,27264, 1376,6784, 1384,23168, 1392,14976, + 1400,31360, 1408,1664, 1416,18048, 1424,9856, 1432,26240, 1440,5760, 1448,22144, + 1456,13952, 1464,30336, 1472,3712, 1480,20096, 1488,11904, 1496,28288, + 1504,7808, 1512,24192, 1520,16000, 1528,32384, 1544,16768, 1552,8576, + 1560,24960, 1568,4480, 1576,20864, 1584,12672, 1592,29056, 1600,2432, + 1608,18816, 1616,10624, 1624,27008, 1632,6528, 1640,22912, 1648,14720, + 1656,31104, 1672,17792, 1680,9600, 1688,25984, 1696,5504, 1704,21888, + 1712,13696, 1720,30080, 1728,3456, 1736,19840, 1744,11648, 1752,28032, + 1760,7552, 1768,23936, 1776,15744, 1784,32128, 1800,17280, 1808,9088, + 1816,25472, 1824,4992, 1832,21376, 1840,13184, 1848,29568, 1856,2944, + 1864,19328, 1872,11136, 1880,27520, 1888,7040, 1896,23424, 1904,15232, + 1912,31616, 1928,18304, 1936,10112, 1944,26496, 1952,6016, 1960,22400, + 1968,14208, 1976,30592, 1984,3968, 1992,20352, 2000,12160, 2008,28544, + 2016,8064, 2024,24448, 2032,16256, 2040,32640, 2056,16448, 2064,8256, + 2072,24640, 2080,4160, 2088,20544, 2096,12352, 2104,28736, 2120,18496, + 2128,10304, 2136,26688, 2144,6208, 2152,22592, 2160,14400, 2168,30784, + 2184,17472, 2192,9280, 2200,25664, 2208,5184, 2216,21568, 2224,13376, + 2232,29760, 2240,3136, 2248,19520, 2256,11328, 2264,27712, 2272,7232, + 2280,23616, 2288,15424, 2296,31808, 2312,16960, 2320,8768, 2328,25152, + 2336,4672, 2344,21056, 2352,12864, 2360,29248, 2368,2624, 2376,19008, + 2384,10816, 2392,27200, 2400,6720, 2408,23104, 2416,14912, 2424,31296, + 2440,17984, 2448,9792, 2456,26176, 2464,5696, 2472,22080, 2480,13888, + 2488,30272, 2496,3648, 2504,20032, 2512,11840, 2520,28224, 2528,7744, + 2536,24128, 2544,15936, 2552,32320, 2568,16704, 2576,8512, 2584,24896, + 2592,4416, 2600,20800, 2608,12608, 2616,28992, 2632,18752, 2640,10560, + 2648,26944, 2656,6464, 2664,22848, 2672,14656, 2680,31040, 2696,17728, + 2704,9536, 2712,25920, 2720,5440, 2728,21824, 2736,13632, 2744,30016, 2752,3392, + 2760,19776, 2768,11584, 2776,27968, 2784,7488, 2792,23872, 2800,15680, + 2808,32064, 2824,17216, 2832,9024, 2840,25408, 2848,4928, 2856,21312, + 2864,13120, 2872,29504, 2888,19264, 2896,11072, 2904,27456, 2912,6976, + 2920,23360, 2928,15168, 2936,31552, 2952,18240, 2960,10048, 2968,26432, + 2976,5952, 2984,22336, 2992,14144, 3000,30528, 3008,3904, 3016,20288, + 3024,12096, 3032,28480, 3040,8000, 3048,24384, 3056,16192, 3064,32576, + 3080,16576, 3088,8384, 3096,24768, 3104,4288, 3112,20672, 3120,12480, + 3128,28864, 3144,18624, 3152,10432, 3160,26816, 3168,6336, 3176,22720, + 3184,14528, 3192,30912, 3208,17600, 3216,9408, 3224,25792, 3232,5312, + 3240,21696, 3248,13504, 3256,29888, 3272,19648, 3280,11456, 3288,27840, + 3296,7360, 3304,23744, 3312,15552, 3320,31936, 3336,17088, 3344,8896, + 3352,25280, 3360,4800, 3368,21184, 3376,12992, 3384,29376, 3400,19136, + 3408,10944, 3416,27328, 3424,6848, 3432,23232, 3440,15040, 3448,31424, + 3464,18112, 3472,9920, 3480,26304, 3488,5824, 3496,22208, 3504,14016, + 3512,30400, 3520,3776, 3528,20160, 3536,11968, 3544,28352, 3552,7872, + 3560,24256, 3568,16064, 3576,32448, 3592,16832, 3600,8640, 3608,25024, + 3616,4544, 3624,20928, 3632,12736, 3640,29120, 3656,18880, 3664,10688, + 3672,27072, 3680,6592, 3688,22976, 3696,14784, 3704,31168, 3720,17856, + 3728,9664, 3736,26048, 3744,5568, 3752,21952, 3760,13760, 3768,30144, + 3784,19904, 3792,11712, 3800,28096, 3808,7616, 3816,24000, 3824,15808, + 3832,32192, 3848,17344, 3856,9152, 3864,25536, 3872,5056, 3880,21440, + 3888,13248, 3896,29632, 3912,19392, 3920,11200, 3928,27584, 3936,7104, + 3944,23488, 3952,15296, 3960,31680, 3976,18368, 3984,10176, 3992,26560, + 4000,6080, 4008,22464, 4016,14272, 4024,30656, 4040,20416, 4048,12224, + 4056,28608, 4064,8128, 4072,24512, 4080,16320, 4088,32704, 4104,16416, + 4112,8224, 4120,24608, 4136,20512, 4144,12320, 4152,28704, 4168,18464, + 4176,10272, 4184,26656, 4192,6176, 4200,22560, 4208,14368, 4216,30752, + 4232,17440, 4240,9248, 4248,25632, 4256,5152, 4264,21536, 4272,13344, + 4280,29728, 4296,19488, 4304,11296, 4312,27680, 4320,7200, 4328,23584, + 4336,15392, 4344,31776, 4360,16928, 4368,8736, 4376,25120, 4384,4640, + 4392,21024, 4400,12832, 4408,29216, 4424,18976, 4432,10784, 4440,27168, + 4448,6688, 4456,23072, 4464,14880, 4472,31264, 4488,17952, 4496,9760, + 4504,26144, 4512,5664, 4520,22048, 4528,13856, 4536,30240, 4552,20000, + 4560,11808, 4568,28192, 4576,7712, 4584,24096, 4592,15904, 4600,32288, + 4616,16672, 4624,8480, 4632,24864, 4648,20768, 4656,12576, 4664,28960, + 4680,18720, 4688,10528, 4696,26912, 4704,6432, 4712,22816, 4720,14624, + 4728,31008, 4744,17696, 4752,9504, 4760,25888, 4768,5408, 4776,21792, + 4784,13600, 4792,29984, 4808,19744, 4816,11552, 4824,27936, 4832,7456, + 4840,23840, 4848,15648, 4856,32032, 4872,17184, 4880,8992, 4888,25376, + 4904,21280, 4912,13088, 4920,29472, 4936,19232, 4944,11040, 4952,27424, + 4960,6944, 4968,23328, 4976,15136, 4984,31520, 5000,18208, 5008,10016, + 5016,26400, 5024,5920, 5032,22304, 5040,14112, 5048,30496, 5064,20256, + 5072,12064, 5080,28448, 5088,7968, 5096,24352, 5104,16160, 5112,32544, + 5128,16544, 5136,8352, 5144,24736, 5160,20640, 5168,12448, 5176,28832, + 5192,18592, 5200,10400, 5208,26784, 5216,6304, 5224,22688, 5232,14496, + 5240,30880, 5256,17568, 5264,9376, 5272,25760, 5288,21664, 5296,13472, + 5304,29856, 5320,19616, 5328,11424, 5336,27808, 5344,7328, 5352,23712, + 5360,15520, 5368,31904, 5384,17056, 5392,8864, 5400,25248, 5416,21152, + 5424,12960, 5432,29344, 5448,19104, 5456,10912, 5464,27296, 5472,6816, + 5480,23200, 5488,15008, 5496,31392, 5512,18080, 5520,9888, 5528,26272, + 5536,5792, 5544,22176, 5552,13984, 5560,30368, 5576,20128, 5584,11936, + 5592,28320, 5600,7840, 5608,24224, 5616,16032, 5624,32416, 5640,16800, + 5648,8608, 5656,24992, 5672,20896, 5680,12704, 5688,29088, 5704,18848, + 5712,10656, 5720,27040, 5728,6560, 5736,22944, 5744,14752, 5752,31136, + 5768,17824, 5776,9632, 5784,26016, 5800,21920, 5808,13728, 5816,30112, + 5832,19872, 5840,11680, 5848,28064, 5856,7584, 5864,23968, 5872,15776, + 5880,32160, 5896,17312, 5904,9120, 5912,25504, 5928,21408, 5936,13216, + 5944,29600, 5960,19360, 5968,11168, 5976,27552, 5984,7072, 5992,23456, + 6000,15264, 6008,31648, 6024,18336, 6032,10144, 6040,26528, 6056,22432, + 6064,14240, 6072,30624, 6088,20384, 6096,12192, 6104,28576, 6112,8096, + 6120,24480, 6128,16288, 6136,32672, 6152,16480, 6160,8288, 6168,24672, + 6184,20576, 6192,12384, 6200,28768, 6216,18528, 6224,10336, 6232,26720, + 6248,22624, 6256,14432, 6264,30816, 6280,17504, 6288,9312, 6296,25696, + 6312,21600, 6320,13408, 6328,29792, 6344,19552, 6352,11360, 6360,27744, + 6368,7264, 6376,23648, 6384,15456, 6392,31840, 6408,16992, 6416,8800, + 6424,25184, 6440,21088, 6448,12896, 6456,29280, 6472,19040, 6480,10848, + 6488,27232, 6496,6752, 6504,23136, 6512,14944, 6520,31328, 6536,18016, + 6544,9824, 6552,26208, 6568,22112, 6576,13920, 6584,30304, 6600,20064, + 6608,11872, 6616,28256, 6624,7776, 6632,24160, 6640,15968, 6648,32352, + 6664,16736, 6672,8544, 6680,24928, 6696,20832, 6704,12640, 6712,29024, + 6728,18784, 6736,10592, 6744,26976, 6760,22880, 6768,14688, 6776,31072, + 6792,17760, 6800,9568, 6808,25952, 6824,21856, 6832,13664, 6840,30048, + 6856,19808, 6864,11616, 6872,28000, 6880,7520, 6888,23904, 6896,15712, + 6904,32096, 6920,17248, 6928,9056, 6936,25440, 6952,21344, 6960,13152, + 6968,29536, 6984,19296, 6992,11104, 7000,27488, 7016,23392, 7024,15200, + 7032,31584, 7048,18272, 7056,10080, 7064,26464, 7080,22368, 7088,14176, + 7096,30560, 7112,20320, 7120,12128, 7128,28512, 7136,8032, 7144,24416, + 7152,16224, 7160,32608, 7176,16608, 7184,8416, 7192,24800, 7208,20704, + 7216,12512, 7224,28896, 7240,18656, 7248,10464, 7256,26848, 7272,22752, + 7280,14560, 7288,30944, 7304,17632, 7312,9440, 7320,25824, 7336,21728, + 7344,13536, 7352,29920, 7368,19680, 7376,11488, 7384,27872, 7400,23776, + 7408,15584, 7416,31968, 7432,17120, 7440,8928, 7448,25312, 7464,21216, + 7472,13024, 7480,29408, 7496,19168, 7504,10976, 7512,27360, 7528,23264, + 7536,15072, 7544,31456, 7560,18144, 7568,9952, 7576,26336, 7592,22240, + 7600,14048, 7608,30432, 7624,20192, 7632,12000, 7640,28384, 7648,7904, + 7656,24288, 7664,16096, 7672,32480, 7688,16864, 7696,8672, 7704,25056, + 7720,20960, 7728,12768, 7736,29152, 7752,18912, 7760,10720, 7768,27104, + 7784,23008, 7792,14816, 7800,31200, 7816,17888, 7824,9696, 7832,26080, + 7848,21984, 7856,13792, 7864,30176, 7880,19936, 7888,11744, 7896,28128, + 7912,24032, 7920,15840, 7928,32224, 7944,17376, 7952,9184, 7960,25568, + 7976,21472, 7984,13280, 7992,29664, 8008,19424, 8016,11232, 8024,27616, + 8040,23520, 8048,15328, 8056,31712, 8072,18400, 8080,10208, 8088,26592, + 8104,22496, 8112,14304, 8120,30688, 8136,20448, 8144,12256, 8152,28640, + 8168,24544, 8176,16352, 8184,32736, 8200,16400, 8216,24592, 8232,20496, + 8240,12304, 8248,28688, 8264,18448, 8272,10256, 8280,26640, 8296,22544, + 8304,14352, 8312,30736, 8328,17424, 8336,9232, 8344,25616, 8360,21520, + 8368,13328, 8376,29712, 8392,19472, 8400,11280, 8408,27664, 8424,23568, + 8432,15376, 8440,31760, 8456,16912, 8464,8720, 8472,25104, 8488,21008, + 8496,12816, 8504,29200, 8520,18960, 8528,10768, 8536,27152, 8552,23056, + 8560,14864, 8568,31248, 8584,17936, 8592,9744, 8600,26128, 8616,22032, + 8624,13840, 8632,30224, 8648,19984, 8656,11792, 8664,28176, 8680,24080, + 8688,15888, 8696,32272, 8712,16656, 8728,24848, 8744,20752, 8752,12560, + 8760,28944, 8776,18704, 8784,10512, 8792,26896, 8808,22800, 8816,14608, + 8824,30992, 8840,17680, 8848,9488, 8856,25872, 8872,21776, 8880,13584, + 8888,29968, 8904,19728, 8912,11536, 8920,27920, 8936,23824, 8944,15632, + 8952,32016, 8968,17168, 8984,25360, 9000,21264, 9008,13072, 9016,29456, + 9032,19216, 9040,11024, 9048,27408, 9064,23312, 9072,15120, 9080,31504, + 9096,18192, 9104,10000, 9112,26384, 9128,22288, 9136,14096, 9144,30480, + 9160,20240, 9168,12048, 9176,28432, 9192,24336, 9200,16144, 9208,32528, + 9224,16528, 9240,24720, 9256,20624, 9264,12432, 9272,28816, 9288,18576, + 9296,10384, 9304,26768, 9320,22672, 9328,14480, 9336,30864, 9352,17552, + 9368,25744, 9384,21648, 9392,13456, 9400,29840, 9416,19600, 9424,11408, + 9432,27792, 9448,23696, 9456,15504, 9464,31888, 9480,17040, 9496,25232, + 9512,21136, 9520,12944, 9528,29328, 9544,19088, 9552,10896, 9560,27280, + 9576,23184, 9584,14992, 9592,31376, 9608,18064, 9616,9872, 9624,26256, + 9640,22160, 9648,13968, 9656,30352, 9672,20112, 9680,11920, 9688,28304, + 9704,24208, 9712,16016, 9720,32400, 9736,16784, 9752,24976, 9768,20880, + 9776,12688, 9784,29072, 9800,18832, 9808,10640, 9816,27024, 9832,22928, + 9840,14736, 9848,31120, 9864,17808, 9880,26000, 9896,21904, 9904,13712, + 9912,30096, 9928,19856, 9936,11664, 9944,28048, 9960,23952, 9968,15760, + 9976,32144, 9992,17296, 10008,25488, 10024,21392, 10032,13200, 10040,29584, + 10056,19344, 10064,11152, 10072,27536, 10088,23440, 10096,15248, 10104,31632, + 10120,18320, 10136,26512, 10152,22416, 10160,14224, 10168,30608, 10184,20368, + 10192,12176, 10200,28560, 10216,24464, 10224,16272, 10232,32656, 10248,16464, + 10264,24656, 10280,20560, 10288,12368, 10296,28752, 10312,18512, 10328,26704, + 10344,22608, 10352,14416, 10360,30800, 10376,17488, 10392,25680, 10408,21584, + 10416,13392, 10424,29776, 10440,19536, 10448,11344, 10456,27728, 10472,23632, + 10480,15440, 10488,31824, 10504,16976, 10520,25168, 10536,21072, 10544,12880, + 10552,29264, 10568,19024, 10576,10832, 10584,27216, 10600,23120, 10608,14928, + 10616,31312, 10632,18000, 10648,26192, 10664,22096, 10672,13904, 10680,30288, + 10696,20048, 10704,11856, 10712,28240, 10728,24144, 10736,15952, 10744,32336, + 10760,16720, 10776,24912, 10792,20816, 10800,12624, 10808,29008, 10824,18768, + 10840,26960, 10856,22864, 10864,14672, 10872,31056, 10888,17744, 10904,25936, + 10920,21840, 10928,13648, 10936,30032, 10952,19792, 10960,11600, 10968,27984, + 10984,23888, 10992,15696, 11000,32080, 11016,17232, 11032,25424, 11048,21328, + 11056,13136, 11064,29520, 11080,19280, 11096,27472, 11112,23376, 11120,15184, + 11128,31568, 11144,18256, 11160,26448, 11176,22352, 11184,14160, 11192,30544, + 11208,20304, 11216,12112, 11224,28496, 11240,24400, 11248,16208, 11256,32592, + 11272,16592, 11288,24784, 11304,20688, 11312,12496, 11320,28880, 11336,18640, + 11352,26832, 11368,22736, 11376,14544, 11384,30928, 11400,17616, 11416,25808, + 11432,21712, 11440,13520, 11448,29904, 11464,19664, 11480,27856, 11496,23760, + 11504,15568, 11512,31952, 11528,17104, 11544,25296, 11560,21200, 11568,13008, + 11576,29392, 11592,19152, 11608,27344, 11624,23248, 11632,15056, 11640,31440, + 11656,18128, 11672,26320, 11688,22224, 11696,14032, 11704,30416, 11720,20176, + 11728,11984, 11736,28368, 11752,24272, 11760,16080, 11768,32464, 11784,16848, + 11800,25040, 11816,20944, 11824,12752, 11832,29136, 11848,18896, 11864,27088, + 11880,22992, 11888,14800, 11896,31184, 11912,17872, 11928,26064, 11944,21968, + 11952,13776, 11960,30160, 11976,19920, 11992,28112, 12008,24016, 12016,15824, + 12024,32208, 12040,17360, 12056,25552, 12072,21456, 12080,13264, 12088,29648, + 12104,19408, 12120,27600, 12136,23504, 12144,15312, 12152,31696, 12168,18384, + 12184,26576, 12200,22480, 12208,14288, 12216,30672, 12232,20432, 12248,28624, + 12264,24528, 12272,16336, 12280,32720, 12296,16432, 12312,24624, 12328,20528, + 12344,28720, 12360,18480, 12376,26672, 12392,22576, 12400,14384, 12408,30768, + 12424,17456, 12440,25648, 12456,21552, 12464,13360, 12472,29744, 12488,19504, + 12504,27696, 12520,23600, 12528,15408, 12536,31792, 12552,16944, 12568,25136, + 12584,21040, 12592,12848, 12600,29232, 12616,18992, 12632,27184, 12648,23088, + 12656,14896, 12664,31280, 12680,17968, 12696,26160, 12712,22064, 12720,13872, + 12728,30256, 12744,20016, 12760,28208, 12776,24112, 12784,15920, 12792,32304, + 12808,16688, 12824,24880, 12840,20784, 12856,28976, 12872,18736, 12888,26928, + 12904,22832, 12912,14640, 12920,31024, 12936,17712, 12952,25904, 12968,21808, + 12976,13616, 12984,30000, 13000,19760, 13016,27952, 13032,23856, 13040,15664, + 13048,32048, 13064,17200, 13080,25392, 13096,21296, 13112,29488, 13128,19248, + 13144,27440, 13160,23344, 13168,15152, 13176,31536, 13192,18224, 13208,26416, + 13224,22320, 13232,14128, 13240,30512, 13256,20272, 13272,28464, 13288,24368, + 13296,16176, 13304,32560, 13320,16560, 13336,24752, 13352,20656, 13368,28848, + 13384,18608, 13400,26800, 13416,22704, 13424,14512, 13432,30896, 13448,17584, + 13464,25776, 13480,21680, 13496,29872, 13512,19632, 13528,27824, 13544,23728, + 13552,15536, 13560,31920, 13576,17072, 13592,25264, 13608,21168, 13624,29360, + 13640,19120, 13656,27312, 13672,23216, 13680,15024, 13688,31408, 13704,18096, + 13720,26288, 13736,22192, 13744,14000, 13752,30384, 13768,20144, 13784,28336, + 13800,24240, 13808,16048, 13816,32432, 13832,16816, 13848,25008, 13864,20912, + 13880,29104, 13896,18864, 13912,27056, 13928,22960, 13936,14768, 13944,31152, + 13960,17840, 13976,26032, 13992,21936, 14008,30128, 14024,19888, 14040,28080, + 14056,23984, 14064,15792, 14072,32176, 14088,17328, 14104,25520, 14120,21424, + 14136,29616, 14152,19376, 14168,27568, 14184,23472, 14192,15280, 14200,31664, + 14216,18352, 14232,26544, 14248,22448, 14264,30640, 14280,20400, 14296,28592, + 14312,24496, 14320,16304, 14328,32688, 14344,16496, 14360,24688, 14376,20592, + 14392,28784, 14408,18544, 14424,26736, 14440,22640, 14456,30832, 14472,17520, + 14488,25712, 14504,21616, 14520,29808, 14536,19568, 14552,27760, 14568,23664, + 14576,15472, 14584,31856, 14600,17008, 14616,25200, 14632,21104, 14648,29296, + 14664,19056, 14680,27248, 14696,23152, 14704,14960, 14712,31344, 14728,18032, + 14744,26224, 14760,22128, 14776,30320, 14792,20080, 14808,28272, 14824,24176, + 14832,15984, 14840,32368, 14856,16752, 14872,24944, 14888,20848, 14904,29040, + 14920,18800, 14936,26992, 14952,22896, 14968,31088, 14984,17776, 15000,25968, + 15016,21872, 15032,30064, 15048,19824, 15064,28016, 15080,23920, 15088,15728, + 15096,32112, 15112,17264, 15128,25456, 15144,21360, 15160,29552, 15176,19312, + 15192,27504, 15208,23408, 15224,31600, 15240,18288, 15256,26480, 15272,22384, + 15288,30576, 15304,20336, 15320,28528, 15336,24432, 15344,16240, 15352,32624, + 15368,16624, 15384,24816, 15400,20720, 15416,28912, 15432,18672, 15448,26864, + 15464,22768, 15480,30960, 15496,17648, 15512,25840, 15528,21744, 15544,29936, + 15560,19696, 15576,27888, 15592,23792, 15608,31984, 15624,17136, 15640,25328, + 15656,21232, 15672,29424, 15688,19184, 15704,27376, 15720,23280, 15736,31472, + 15752,18160, 15768,26352, 15784,22256, 15800,30448, 15816,20208, 15832,28400, + 15848,24304, 15856,16112, 15864,32496, 15880,16880, 15896,25072, 15912,20976, + 15928,29168, 15944,18928, 15960,27120, 15976,23024, 15992,31216, 16008,17904, + 16024,26096, 16040,22000, 16056,30192, 16072,19952, 16088,28144, 16104,24048, + 16120,32240, 16136,17392, 16152,25584, 16168,21488, 16184,29680, 16200,19440, + 16216,27632, 16232,23536, 16248,31728, 16264,18416, 16280,26608, 16296,22512, + 16312,30704, 16328,20464, 16344,28656, 16360,24560, 16376,32752, 16408,24584, + 16424,20488, 16440,28680, 16456,18440, 16472,26632, 16488,22536, 16504,30728, + 16520,17416, 16536,25608, 16552,21512, 16568,29704, 16584,19464, 16600,27656, + 16616,23560, 16632,31752, 16648,16904, 16664,25096, 16680,21000, 16696,29192, + 16712,18952, 16728,27144, 16744,23048, 16760,31240, 16776,17928, 16792,26120, + 16808,22024, 16824,30216, 16840,19976, 16856,28168, 16872,24072, 16888,32264, + 16920,24840, 16936,20744, 16952,28936, 16968,18696, 16984,26888, 17000,22792, + 17016,30984, 17032,17672, 17048,25864, 17064,21768, 17080,29960, 17096,19720, + 17112,27912, 17128,23816, 17144,32008, 17176,25352, 17192,21256, 17208,29448, + 17224,19208, 17240,27400, 17256,23304, 17272,31496, 17288,18184, 17304,26376, + 17320,22280, 17336,30472, 17352,20232, 17368,28424, 17384,24328, 17400,32520, + 17432,24712, 17448,20616, 17464,28808, 17480,18568, 17496,26760, 17512,22664, + 17528,30856, 17560,25736, 17576,21640, 17592,29832, 17608,19592, 17624,27784, + 17640,23688, 17656,31880, 17688,25224, 17704,21128, 17720,29320, 17736,19080, + 17752,27272, 17768,23176, 17784,31368, 17800,18056, 17816,26248, 17832,22152, + 17848,30344, 17864,20104, 17880,28296, 17896,24200, 17912,32392, 17944,24968, + 17960,20872, 17976,29064, 17992,18824, 18008,27016, 18024,22920, 18040,31112, + 18072,25992, 18088,21896, 18104,30088, 18120,19848, 18136,28040, 18152,23944, + 18168,32136, 18200,25480, 18216,21384, 18232,29576, 18248,19336, 18264,27528, + 18280,23432, 18296,31624, 18328,26504, 18344,22408, 18360,30600, 18376,20360, + 18392,28552, 18408,24456, 18424,32648, 18456,24648, 18472,20552, 18488,28744, + 18520,26696, 18536,22600, 18552,30792, 18584,25672, 18600,21576, 18616,29768, + 18632,19528, 18648,27720, 18664,23624, 18680,31816, 18712,25160, 18728,21064, + 18744,29256, 18760,19016, 18776,27208, 18792,23112, 18808,31304, 18840,26184, + 18856,22088, 18872,30280, 18888,20040, 18904,28232, 18920,24136, 18936,32328, + 18968,24904, 18984,20808, 19000,29000, 19032,26952, 19048,22856, 19064,31048, + 19096,25928, 19112,21832, 19128,30024, 19144,19784, 19160,27976, 19176,23880, + 19192,32072, 19224,25416, 19240,21320, 19256,29512, 19288,27464, 19304,23368, + 19320,31560, 19352,26440, 19368,22344, 19384,30536, 19400,20296, 19416,28488, + 19432,24392, 19448,32584, 19480,24776, 19496,20680, 19512,28872, 19544,26824, + 19560,22728, 19576,30920, 19608,25800, 19624,21704, 19640,29896, 19672,27848, + 19688,23752, 19704,31944, 19736,25288, 19752,21192, 19768,29384, 19800,27336, + 19816,23240, 19832,31432, 19864,26312, 19880,22216, 19896,30408, 19912,20168, + 19928,28360, 19944,24264, 19960,32456, 19992,25032, 20008,20936, 20024,29128, + 20056,27080, 20072,22984, 20088,31176, 20120,26056, 20136,21960, 20152,30152, + 20184,28104, 20200,24008, 20216,32200, 20248,25544, 20264,21448, 20280,29640, + 20312,27592, 20328,23496, 20344,31688, 20376,26568, 20392,22472, 20408,30664, + 20440,28616, 20456,24520, 20472,32712, 20504,24616, 20536,28712, 20568,26664, + 20584,22568, 20600,30760, 20632,25640, 20648,21544, 20664,29736, 20696,27688, + 20712,23592, 20728,31784, 20760,25128, 20776,21032, 20792,29224, 20824,27176, + 20840,23080, 20856,31272, 20888,26152, 20904,22056, 20920,30248, 20952,28200, + 20968,24104, 20984,32296, 21016,24872, 21048,28968, 21080,26920, 21096,22824, + 21112,31016, 21144,25896, 21160,21800, 21176,29992, 21208,27944, 21224,23848, + 21240,32040, 21272,25384, 21304,29480, 21336,27432, 21352,23336, 21368,31528, + 21400,26408, 21416,22312, 21432,30504, 21464,28456, 21480,24360, 21496,32552, + 21528,24744, 21560,28840, 21592,26792, 21608,22696, 21624,30888, 21656,25768, + 21688,29864, 21720,27816, 21736,23720, 21752,31912, 21784,25256, 21816,29352, + 21848,27304, 21864,23208, 21880,31400, 21912,26280, 21928,22184, 21944,30376, + 21976,28328, 21992,24232, 22008,32424, 22040,25000, 22072,29096, 22104,27048, + 22120,22952, 22136,31144, 22168,26024, 22200,30120, 22232,28072, 22248,23976, + 22264,32168, 22296,25512, 22328,29608, 22360,27560, 22376,23464, 22392,31656, + 22424,26536, 22456,30632, 22488,28584, 22504,24488, 22520,32680, 22552,24680, + 22584,28776, 22616,26728, 22648,30824, 22680,25704, 22712,29800, 22744,27752, + 22760,23656, 22776,31848, 22808,25192, 22840,29288, 22872,27240, 22888,23144, + 22904,31336, 22936,26216, 22968,30312, 23000,28264, 23016,24168, 23032,32360, + 23064,24936, 23096,29032, 23128,26984, 23160,31080, 23192,25960, 23224,30056, + 23256,28008, 23272,23912, 23288,32104, 23320,25448, 23352,29544, 23384,27496, + 23416,31592, 23448,26472, 23480,30568, 23512,28520, 23528,24424, 23544,32616, + 23576,24808, 23608,28904, 23640,26856, 23672,30952, 23704,25832, 23736,29928, + 23768,27880, 23800,31976, 23832,25320, 23864,29416, 23896,27368, 23928,31464, + 23960,26344, 23992,30440, 24024,28392, 24040,24296, 24056,32488, 24088,25064, + 24120,29160, 24152,27112, 24184,31208, 24216,26088, 24248,30184, 24280,28136, + 24312,32232, 24344,25576, 24376,29672, 24408,27624, 24440,31720, 24472,26600, + 24504,30696, 24536,28648, 24568,32744, 24632,28696, 24664,26648, 24696,30744, + 24728,25624, 24760,29720, 24792,27672, 24824,31768, 24856,25112, 24888,29208, + 24920,27160, 24952,31256, 24984,26136, 25016,30232, 25048,28184, 25080,32280, + 25144,28952, 25176,26904, 25208,31000, 25240,25880, 25272,29976, 25304,27928, + 25336,32024, 25400,29464, 25432,27416, 25464,31512, 25496,26392, 25528,30488, + 25560,28440, 25592,32536, 25656,28824, 25688,26776, 25720,30872, 25784,29848, + 25816,27800, 25848,31896, 25912,29336, 25944,27288, 25976,31384, 26008,26264, + 26040,30360, 26072,28312, 26104,32408, 26168,29080, 26200,27032, 26232,31128, + 26296,30104, 26328,28056, 26360,32152, 26424,29592, 26456,27544, 26488,31640, + 26552,30616, 26584,28568, 26616,32664, 26680,28760, 26744,30808, 26808,29784, + 26840,27736, 26872,31832, 26936,29272, 26968,27224, 27000,31320, 27064,30296, + 27096,28248, 27128,32344, 27192,29016, 27256,31064, 27320,30040, 27352,27992, + 27384,32088, 27448,29528, 27512,31576, 27576,30552, 27608,28504, 27640,32600, + 27704,28888, 27768,30936, 27832,29912, 27896,31960, 27960,29400, 28024,31448, + 28088,30424, 28120,28376, 28152,32472, 28216,29144, 28280,31192, 28344,30168, + 28408,32216, 28472,29656, 28536,31704, 28600,30680, 28664,32728, 28792,30776, + 28856,29752, 28920,31800, 28984,29240, 29048,31288, 29112,30264, 29176,32312, + 29304,31032, 29368,30008, 29432,32056, 29560,31544, 29624,30520, 29688,32568, + 29816,30904, 29944,31928, 30072,31416, 30136,30392, 30200,32440, 30328,31160, + 30456,32184, 30584,31672, 30712,32696, 30968,31864, 31096,31352, 31224,32376, + 31480,32120, 31736,32632, 32248,32504 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) +/** + @par + Example code for Double Precision Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const uint64_t twiddleCoefF64_rfft_32[32] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, //0.19509, 0.98079 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, //0.38268, 0.92388 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, //0.55557, 0.83147 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, //0.70711, 0.70711 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, //0.83147, 0.55557 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, //0.92388, 0.38268 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, //0.98079, 0.19509 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, //0.98079,-0.19509 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, //0.92388,-0.38268 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, //0.83147,-0.55557 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, //0.70711,-0.70711 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, //0.55557,-0.83147 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, //0.38268,-0.92388 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, //0.19509,-0.98079 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) +const uint64_t twiddleCoefF64_rfft_64[64] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) +const uint64_t twiddleCoefF64_rfft_128[128] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) +const uint64_t twiddleCoefF64_rfft_256[256] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997 + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) +const uint64_t twiddleCoefF64_rfft_512[512] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, //0.012272, 0.99992' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, //0.024541, 0.9997' + 0x3fa2d865759455cd, 0x3feffa72effef75d, //0.036807, 0.99932' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, //0.049068, 0.9988' + 0x3faf656e79f820e0, 0x3feff095658e71ad, //0.061321, 0.99812' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, //0.073565, 0.99729' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, //0.085797, 0.99631' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, //0.098017, 0.99518' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992,-0.012272' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997,-0.024541' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932,-0.036807' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988,-0.049068' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812,-0.061321' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729,-0.073565' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631,-0.085797' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518,-0.098017' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, //0.098017, -0.99518' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, //0.085797, -0.99631' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, //0.073565, -0.99729' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, //0.061321, -0.99812' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, //0.049068, -0.9988' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, //0.036807, -0.99932' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, //0.024541, -0.9997' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, //0.012272, -0.99992' + + +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) +const uint64_t twiddleCoefF64_rfft_1024[1024] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1' + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998' + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992' + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983' + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997' + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953' + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932' + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908' + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988' + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848' + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812' + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772' + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729' + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682' + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631' + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577' + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518' + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456' + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391' + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321' + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248' + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171' + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909' + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006' + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918' + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826' + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873' + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631' + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528' + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421' + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311' + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196' + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079' + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957' + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832' + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703' + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757' + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434' + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294' + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715' + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003' + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852' + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698' + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539' + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378' + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212' + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043' + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587' + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694' + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514' + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331' + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144' + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953' + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759' + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561' + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359' + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154' + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946' + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734' + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518' + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299' + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077' + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851' + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621' + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388' + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151' + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911' + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668' + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421' + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171' + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917' + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066' + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399' + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135' + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867' + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597' + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322' + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045' + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764' + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848' + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192' + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901' + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607' + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309' + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009' + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705' + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397' + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087' + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773' + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456' + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136' + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812' + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485' + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155' + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822' + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486' + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147' + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805' + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459' + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211' + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758' + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404' + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046' + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685' + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321' + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954' + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584' + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211' + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835' + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456' + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074' + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689' + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301' + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691' + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517' + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612' + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721' + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319' + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914' + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506' + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095' + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682' + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265' + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846' + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425' + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72' + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573' + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143' + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711' + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275' + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838' + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397' + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954' + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508' + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806' + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609' + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156' + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667' + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242' + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781' + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317' + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851' + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383' + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912' + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439' + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964' + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486' + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006' + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523' + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038' + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551' + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062' + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957' + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076' + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858' + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081' + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581' + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078' + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573' + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066' + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557' + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046' + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532' + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017' + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535' + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298' + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459' + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936' + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141' + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883' + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354' + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823' + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929' + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755' + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218' + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768' + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714' + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598' + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054' + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508' + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961' + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412' + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862' + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309' + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756' + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422' + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643' + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084' + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524' + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962' + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399' + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835' + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268' + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701' + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132' + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561' + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599' + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416' + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842' + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266' + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689' + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111' + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531' + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195' + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368' + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785' + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201' + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615' + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028' + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441' + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852' + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262' + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671' + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079' + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487' + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893' + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298' + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702' + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106' + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508' + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191' + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311' + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711' + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011' + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509' + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907' + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304' + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177' + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096' + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491' + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886' + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528' + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673' + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066' + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458' + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285' + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241' + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632' + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022' + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412' + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017' + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909' + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797' + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682' + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565' + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444' + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321' + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195' + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068' + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938' + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807' + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675' + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541' + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407' + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272' + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359' + 0x3ff0000000000000, 0x0000000000000000, // 1, 0' + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359' + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272' + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407' + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541' + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675' + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807' + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938' + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068' + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195' + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321' + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444' + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565' + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682' + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797' + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909' + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017' + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412' + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022' + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632' + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241' + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285' + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458' + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066' + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673' + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528' + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886' + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491' + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096' + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177' + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304' + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907' + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509' + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011' + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711' + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311' + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191' + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508' + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106' + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702' + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298' + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893' + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487' + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079' + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671' + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262' + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852' + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441' + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028' + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615' + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201' + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785' + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368' + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195' + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531' + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111' + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689' + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266' + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842' + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416' + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599' + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561' + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132' + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701' + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268' + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835' + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399' + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962' + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524' + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084' + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643' + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422' + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756' + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309' + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862' + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412' + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961' + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508' + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054' + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598' + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714' + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768' + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218' + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755' + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929' + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823' + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354' + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883' + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141' + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936' + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459' + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298' + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535' + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017' + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532' + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046' + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557' + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066' + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573' + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078' + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581' + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081' + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858' + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076' + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957' + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062' + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551' + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038' + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523' + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006' + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486' + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964' + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439' + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912' + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383' + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851' + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317' + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781' + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242' + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667' + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156' + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609' + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806' + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508' + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954' + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397' + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838' + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275' + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711' + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143' + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573' + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72' + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425' + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846' + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265' + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682' + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095' + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506' + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914' + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319' + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721' + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612' + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517' + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691' + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301' + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689' + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074' + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456' + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835' + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211' + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584' + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954' + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321' + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685' + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046' + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404' + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758' + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211' + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459' + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805' + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147' + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486' + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822' + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155' + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485' + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812' + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136' + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456' + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773' + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087' + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397' + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705' + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009' + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309' + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607' + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901' + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192' + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848' + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764' + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045' + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322' + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597' + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867' + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135' + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399' + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066' + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917' + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171' + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421' + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668' + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911' + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151' + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388' + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621' + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851' + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077' + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299' + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518' + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734' + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946' + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154' + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359' + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561' + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759' + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953' + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144' + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331' + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514' + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694' + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587' + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043' + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212' + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378' + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539' + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698' + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852' + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003' + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715' + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294' + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434' + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757' + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703' + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832' + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957' + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079' + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196' + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311' + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421' + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528' + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631' + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873' + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826' + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918' + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006' + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909' + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171' + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248' + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321' + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391' + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456' + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518' + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577' + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631' + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682' + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729' + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772' + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812' + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848' + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988' + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908' + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932' + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953' + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997' + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983' + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992' + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998' +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) +const uint64_t twiddleCoefF64_rfft_2048[2048] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) +const uint64_t twiddleCoefF64_rfft_4096[4096] = { + 0x0000000000000000, 0x3ff0000000000000, // 0, 1 + 0x3f5921faaee6472d, 0x3feffffd88586ee6, // 0.001534, 1 + 0x3f6921f8becca4ba, 0x3feffff621621d02, // 0.003068, 1 + 0x3f72d97822f996bc, 0x3fefffe9cb1e2e8d, //0.0046019, 0.99999 + 0x3f7921f0fe670071, 0x3fefffd8858e8a92, //0.0061359, 0.99998 + 0x3f7f6a65f9a2a3c5, 0x3fefffc250b5daef, //0.0076698, 0.99997 + 0x3f82d96b0e509703, 0x3fefffa72c978c4f, //0.0092038, 0.99996 + 0x3f85fda037ac05e0, 0x3fefff871937ce2f, // 0.010738, 0.99994 + 0x3f8921d1fcdec784, 0x3fefff62169b92db, // 0.012272, 0.99992 + 0x3f8c45ffe1e48ad9, 0x3fefff3824c88f6f, // 0.013805, 0.9999 + 0x3f8f6a296ab997ca, 0x3fefff0943c53bd1, // 0.015339, 0.99988 + 0x3f9147270dad7132, 0x3feffed57398d2b7, // 0.016873, 0.99986 + 0x3f92d936bbe30efd, 0x3feffe9cb44b51a1, // 0.018407, 0.99983 + 0x3f946b4381fce81c, 0x3feffe5f05e578db, // 0.01994, 0.9998 + 0x3f95fd4d21fab226, 0x3feffe1c6870cb77, // 0.021474, 0.99977 + 0x3f978f535ddc9f03, 0x3feffdd4dbf78f52, // 0.023008, 0.99974 + 0x3f992155f7a3667e, 0x3feffd886084cd0d, // 0.024541, 0.9997 + 0x3f9ab354b1504fca, 0x3feffd36f624500c, // 0.026075, 0.99966 + 0x3f9c454f4ce53b1c, 0x3feffce09ce2a679, // 0.027608, 0.99962 + 0x3f9dd7458c64ab39, 0x3feffc8554cd213a, // 0.029142, 0.99958 + 0x3f9f693731d1cf01, 0x3feffc251df1d3f8, // 0.030675, 0.99953 + 0x3fa07d91ff984580, 0x3feffbbff85f9515, // 0.032208, 0.99948 + 0x3fa14685db42c17e, 0x3feffb55e425fdae, // 0.033741, 0.99943 + 0x3fa20f770ceb11c6, 0x3feffae6e1556998, // 0.035274, 0.99938 + 0x3fa2d865759455cd, 0x3feffa72effef75d, // 0.036807, 0.99932 + 0x3fa3a150f6421afc, 0x3feff9fa10348837, // 0.03834, 0.99926 + 0x3fa46a396ff86179, 0x3feff97c4208c014, // 0.039873, 0.9992 + 0x3fa5331ec3bba0eb, 0x3feff8f9858f058b, // 0.041406, 0.99914 + 0x3fa5fc00d290cd43, 0x3feff871dadb81df, // 0.042938, 0.99908 + 0x3fa6c4df7d7d5b84, 0x3feff7e5420320f9, // 0.044471, 0.99901 + 0x3fa78dbaa5874685, 0x3feff753bb1b9164, // 0.046003, 0.99894 + 0x3fa856922bb513c1, 0x3feff6bd463b444d, // 0.047535, 0.99887 + 0x3fa91f65f10dd814, 0x3feff621e3796d7e, // 0.049068, 0.9988 + 0x3fa9e835d6993c87, 0x3feff58192ee0358, // 0.0506, 0.99872 + 0x3faab101bd5f8317, 0x3feff4dc54b1bed3, // 0.052132, 0.99864 + 0x3fab79c986698b78, 0x3feff43228de1b77, // 0.053664, 0.99856 + 0x3fac428d12c0d7e3, 0x3feff3830f8d575c, // 0.055195, 0.99848 + 0x3fad0b4c436f91d0, 0x3feff2cf08da7321, // 0.056727, 0.99839 + 0x3fadd406f9808ec8, 0x3feff21614e131ed, // 0.058258, 0.9983 + 0x3fae9cbd15ff5527, 0x3feff15833be1965, // 0.05979, 0.99821 + 0x3faf656e79f820e0, 0x3feff095658e71ad, // 0.061321, 0.99812 + 0x3fb0170d833bf421, 0x3fefefcdaa704562, // 0.062852, 0.99802 + 0x3fb07b614e463064, 0x3fefef0102826191, // 0.064383, 0.99793 + 0x3fb0dfb28ea201e6, 0x3fefee2f6de455ba, // 0.065913, 0.99783 + 0x3fb1440134d709b2, 0x3fefed58ecb673c4, // 0.067444, 0.99772 + 0x3fb1a84d316d4f8a, 0x3fefec7d7f19cffc, // 0.068974, 0.99762 + 0x3fb20c9674ed444c, 0x3fefeb9d2530410f, // 0.070505, 0.99751 + 0x3fb270dcefdfc45b, 0x3fefeab7df1c6005, // 0.072035, 0.9974 + 0x3fb2d52092ce19f6, 0x3fefe9cdad01883a, // 0.073565, 0.99729 + 0x3fb339614e41ffa5, 0x3fefe8de8f03d75c, // 0.075094, 0.99718 + 0x3fb39d9f12c5a299, 0x3fefe7ea85482d60, // 0.076624, 0.99706 + 0x3fb401d9d0e3a507, 0x3fefe6f18ff42c84, // 0.078153, 0.99694 + 0x3fb4661179272096, 0x3fefe5f3af2e3940, // 0.079682, 0.99682 + 0x3fb4ca45fc1ba8b6, 0x3fefe4f0e31d7a4a, // 0.081211, 0.9967 + 0x3fb52e774a4d4d0a, 0x3fefe3e92be9d886, // 0.08274, 0.99657 + 0x3fb592a554489bc8, 0x3fefe2dc89bbff08, // 0.084269, 0.99644 + 0x3fb5f6d00a9aa419, 0x3fefe1cafcbd5b09, // 0.085797, 0.99631 + 0x3fb65af75dd0f87b, 0x3fefe0b485181be3, // 0.087326, 0.99618 + 0x3fb6bf1b3e79b129, 0x3fefdf9922f73307, // 0.088854, 0.99604 + 0x3fb7233b9d236e71, 0x3fefde78d68653fd, // 0.090381, 0.99591 + 0x3fb787586a5d5b21, 0x3fefdd539ff1f456, // 0.091909, 0.99577 + 0x3fb7eb7196b72ee4, 0x3fefdc297f674ba9, // 0.093436, 0.99563 + 0x3fb84f8712c130a0, 0x3fefdafa7514538c, // 0.094963, 0.99548 + 0x3fb8b398cf0c38e0, 0x3fefd9c68127c78c, // 0.09649, 0.99533 + 0x3fb917a6bc29b42c, 0x3fefd88da3d12526, // 0.098017, 0.99518 + 0x3fb97bb0caaba56f, 0x3fefd74fdd40abbf, // 0.099544, 0.99503 + 0x3fb9dfb6eb24a85c, 0x3fefd60d2da75c9e, // 0.10107, 0.99488 + 0x3fba43b90e27f3c4, 0x3fefd4c59536fae4, // 0.1026, 0.99472 + 0x3fbaa7b724495c04, 0x3fefd37914220b84, // 0.10412, 0.99456 + 0x3fbb0bb11e1d5559, 0x3fefd227aa9bd53b, // 0.10565, 0.9944 + 0x3fbb6fa6ec38f64c, 0x3fefd0d158d86087, // 0.10717, 0.99424 + 0x3fbbd3987f31fa0e, 0x3fefcf761f0c77a3, // 0.1087, 0.99407 + 0x3fbc3785c79ec2d5, 0x3fefce15fd6da67b, // 0.11022, 0.99391 + 0x3fbc9b6eb6165c42, 0x3fefccb0f4323aa3, // 0.11175, 0.99374 + 0x3fbcff533b307dc1, 0x3fefcb4703914354, // 0.11327, 0.99356 + 0x3fbd633347858ce4, 0x3fefc9d82bc2915e, // 0.11479, 0.99339 + 0x3fbdc70ecbae9fc8, 0x3fefc8646cfeb721, // 0.11632, 0.99321 + 0x3fbe2ae5b8457f77, 0x3fefc6ebc77f0887, // 0.11784, 0.99303 + 0x3fbe8eb7fde4aa3e, 0x3fefc56e3b7d9af6, // 0.11937, 0.99285 + 0x3fbef2858d27561b, 0x3fefc3ebc935454c, // 0.12089, 0.99267 + 0x3fbf564e56a9730e, 0x3fefc26470e19fd3, // 0.12241, 0.99248 + 0x3fbfba124b07ad85, 0x3fefc0d832bf043a, // 0.12393, 0.99229 + 0x3fc00ee8ad6fb85b, 0x3fefbf470f0a8d88, // 0.12545, 0.9921 + 0x3fc040c5bb67747e, 0x3fefbdb106021816, // 0.12698, 0.99191 + 0x3fc072a047ba831d, 0x3fefbc1617e44186, // 0.1285, 0.99171 + 0x3fc0a4784ab8bf1d, 0x3fefba7644f068b5, // 0.13002, 0.99151 + 0x3fc0d64dbcb26786, 0x3fefb8d18d66adb7, // 0.13154, 0.99131 + 0x3fc1082095f820b0, 0x3fefb727f187f1c7, // 0.13306, 0.99111 + 0x3fc139f0cedaf576, 0x3fefb5797195d741, // 0.13458, 0.9909 + 0x3fc16bbe5fac5865, 0x3fefb3c60dd2c199, // 0.1361, 0.9907 + 0x3fc19d8940be24e7, 0x3fefb20dc681d54d, // 0.13762, 0.99049 + 0x3fc1cf516a62a077, 0x3fefb0509be6f7db, // 0.13914, 0.99027 + 0x3fc20116d4ec7bce, 0x3fefae8e8e46cfbb, // 0.14066, 0.99006 + 0x3fc232d978aed413, 0x3fefacc79de6c44f, // 0.14218, 0.98984 + 0x3fc264994dfd340a, 0x3fefaafbcb0cfddc, // 0.1437, 0.98962 + 0x3fc296564d2b953e, 0x3fefa92b1600657c, // 0.14521, 0.9894 + 0x3fc2c8106e8e613a, 0x3fefa7557f08a517, // 0.14673, 0.98918 + 0x3fc2f9c7aa7a72af, 0x3fefa57b066e2754, // 0.14825, 0.98895 + 0x3fc32b7bf94516a7, 0x3fefa39bac7a1791, // 0.14976, 0.98872 + 0x3fc35d2d53440db2, 0x3fefa1b7717661d5, // 0.15128, 0.98849 + 0x3fc38edbb0cd8d14, 0x3fef9fce55adb2c8, // 0.1528, 0.98826 + 0x3fc3c0870a383ff6, 0x3fef9de0596b77a3, // 0.15431, 0.98802 + 0x3fc3f22f57db4893, 0x3fef9bed7cfbde29, // 0.15583, 0.98778 + 0x3fc423d4920e4166, 0x3fef99f5c0abd496, // 0.15734, 0.98754 + 0x3fc45576b1293e5a, 0x3fef97f924c9099b, // 0.15886, 0.9873 + 0x3fc48715ad84cdf5, 0x3fef95f7a9a1ec47, // 0.16037, 0.98706 + 0x3fc4b8b17f79fa88, 0x3fef93f14f85ac08, // 0.16189, 0.98681 + 0x3fc4ea4a1f624b61, 0x3fef91e616c43891, // 0.1634, 0.98656 + 0x3fc51bdf8597c5f2, 0x3fef8fd5ffae41db, // 0.16491, 0.98631 + 0x3fc54d71aa74ef02, 0x3fef8dc10a95380d, // 0.16643, 0.98605 + 0x3fc57f008654cbde, 0x3fef8ba737cb4b78, // 0.16794, 0.9858 + 0x3fc5b08c1192e381, 0x3fef898887a36c84, // 0.16945, 0.98554 + 0x3fc5e214448b3fc6, 0x3fef8764fa714ba9, // 0.17096, 0.98528 + 0x3fc61399179a6e94, 0x3fef853c9089595e, // 0.17247, 0.98501 + 0x3fc6451a831d830d, 0x3fef830f4a40c60c, // 0.17398, 0.98475 + 0x3fc676987f7216b8, 0x3fef80dd27ed8204, // 0.17549, 0.98448 + 0x3fc6a81304f64ab2, 0x3fef7ea629e63d6e, // 0.177, 0.98421 + 0x3fc6d98a0c08c8da, 0x3fef7c6a50826840, // 0.17851, 0.98394 + 0x3fc70afd8d08c4ff, 0x3fef7a299c1a322a, // 0.18002, 0.98366 + 0x3fc73c6d8055fe0a, 0x3fef77e40d068a90, // 0.18153, 0.98339 + 0x3fc76dd9de50bf31, 0x3fef7599a3a12077, // 0.18304, 0.98311 + 0x3fc79f429f59e11d, 0x3fef734a60446279, // 0.18455, 0.98282 + 0x3fc7d0a7bbd2cb1b, 0x3fef70f6434b7eb7, // 0.18606, 0.98254 + 0x3fc802092c1d744b, 0x3fef6e9d4d1262ca, // 0.18756, 0.98225 + 0x3fc83366e89c64c5, 0x3fef6c3f7df5bbb7, // 0.18907, 0.98196 + 0x3fc864c0e9b2b6cf, 0x3fef69dcd652f5de, // 0.19057, 0.98167 + 0x3fc8961727c41804, 0x3fef677556883cee, // 0.19208, 0.98138 + 0x3fc8c7699b34ca7e, 0x3fef6508fef47bd5, // 0.19359, 0.98108 + 0x3fc8f8b83c69a60a, 0x3fef6297cff75cb0, // 0.19509, 0.98079 + 0x3fc92a0303c8194f, 0x3fef6021c9f148c2, // 0.19659, 0.98048 + 0x3fc95b49e9b62af9, 0x3fef5da6ed43685d, // 0.1981, 0.98018 + 0x3fc98c8ce69a7aec, 0x3fef5b273a4fa2d9, // 0.1996, 0.97988 + 0x3fc9bdcbf2dc4366, 0x3fef58a2b1789e84, // 0.2011, 0.97957 + 0x3fc9ef0706e35a35, 0x3fef56195321c090, // 0.20261, 0.97926 + 0x3fca203e1b1831da, 0x3fef538b1faf2d07, // 0.20411, 0.97895 + 0x3fca517127e3dabc, 0x3fef50f81785c6b9, // 0.20561, 0.97863 + 0x3fca82a025b00451, 0x3fef4e603b0b2f2d, // 0.20711, 0.97832 + 0x3fcab3cb0ce6fe44, 0x3fef4bc38aa5c694, // 0.20861, 0.978 + 0x3fcae4f1d5f3b9ab, 0x3fef492206bcabb4, // 0.21011, 0.97768 + 0x3fcb16147941ca2a, 0x3fef467bafb7bbe0, // 0.21161, 0.97735 + 0x3fcb4732ef3d6722, 0x3fef43d085ff92dd, // 0.21311, 0.97703 + 0x3fcb784d30536cda, 0x3fef412089fd8adc, // 0.21461, 0.9767 + 0x3fcba96334f15dad, 0x3fef3e6bbc1bbc65, // 0.21611, 0.97637 + 0x3fcbda74f5856330, 0x3fef3bb21cc4fe47, // 0.2176, 0.97604 + 0x3fcc0b826a7e4f63, 0x3fef38f3ac64e589, // 0.2191, 0.9757 + 0x3fcc3c8b8c4b9dd7, 0x3fef36306b67c556, // 0.2206, 0.97536 + 0x3fcc6d90535d74dc, 0x3fef33685a3aaef0, // 0.22209, 0.97503 + 0x3fcc9e90b824a6a9, 0x3fef309b794b719f, // 0.22359, 0.97468 + 0x3fcccf8cb312b286, 0x3fef2dc9c9089a9d, // 0.22508, 0.97434 + 0x3fcd00843c99c5f9, 0x3fef2af349e17507, // 0.22658, 0.97399 + 0x3fcd31774d2cbdee, 0x3fef2817fc4609ce, // 0.22807, 0.97364 + 0x3fcd6265dd3f27e3, 0x3fef2537e0a71f9f, // 0.22957, 0.97329 + 0x3fcd934fe5454311, 0x3fef2252f7763ada, // 0.23106, 0.97294 + 0x3fcdc4355db40195, 0x3fef1f6941259d7a, // 0.23255, 0.97258 + 0x3fcdf5163f01099a, 0x3fef1c7abe284708, // 0.23404, 0.97223 + 0x3fce25f281a2b684, 0x3fef19876ef1f486, // 0.23553, 0.97187 + 0x3fce56ca1e101a1b, 0x3fef168f53f7205d, // 0.23702, 0.9715 + 0x3fce879d0cc0fdaf, 0x3fef13926dad024e, // 0.23851, 0.97114 + 0x3fceb86b462de348, 0x3fef1090bc898f5f, // 0.24, 0.97077 + 0x3fcee934c2d006c7, 0x3fef0d8a410379c5, // 0.24149, 0.9704 + 0x3fcf19f97b215f1a, 0x3fef0a7efb9230d7, // 0.24298, 0.97003 + 0x3fcf4ab9679c9f5c, 0x3fef076eecade0fa, // 0.24447, 0.96966 + 0x3fcf7b7480bd3801, 0x3fef045a14cf738c, // 0.24596, 0.96928 + 0x3fcfac2abeff57ff, 0x3fef014074708ed3, // 0.24744, 0.9689 + 0x3fcfdcdc1adfedf8, 0x3feefe220c0b95ec, // 0.24893, 0.96852 + 0x3fd006c4466e54af, 0x3feefafedc1ba8b7, // 0.25041, 0.96814 + 0x3fd01f1806b9fdd2, 0x3feef7d6e51ca3c0, // 0.2519, 0.96775 + 0x3fd037694a928cac, 0x3feef4aa278b2032, // 0.25338, 0.96737 + 0x3fd04fb80e37fdae, 0x3feef178a3e473c2, // 0.25487, 0.96698 + 0x3fd068044deab002, 0x3feeee425aa6b09a, // 0.25635, 0.96658 + 0x3fd0804e05eb661e, 0x3feeeb074c50a544, // 0.25783, 0.96619 + 0x3fd09895327b465e, 0x3feee7c77961dc9e, // 0.25931, 0.96579 + 0x3fd0b0d9cfdbdb90, 0x3feee482e25a9dbc, // 0.26079, 0.96539 + 0x3fd0c91bda4f158d, 0x3feee13987bbebdc, // 0.26227, 0.96499 + 0x3fd0e15b4e1749cd, 0x3feeddeb6a078651, // 0.26375, 0.96459 + 0x3fd0f998277733f7, 0x3feeda9889bfe86a, // 0.26523, 0.96418 + 0x3fd111d262b1f677, 0x3feed740e7684963, // 0.26671, 0.96378 + 0x3fd12a09fc0b1b12, 0x3feed3e483849c51, // 0.26819, 0.96337 + 0x3fd1423eefc69378, 0x3feed0835e999009, // 0.26967, 0.96295 + 0x3fd15a713a28b9d9, 0x3feecd1d792c8f10, // 0.27115, 0.96254 + 0x3fd172a0d7765177, 0x3feec9b2d3c3bf84, // 0.27262, 0.96212 + 0x3fd18acdc3f4873a, 0x3feec6436ee60309, // 0.2741, 0.9617 + 0x3fd1a2f7fbe8f243, 0x3feec2cf4b1af6b2, // 0.27557, 0.96128 + 0x3fd1bb1f7b999480, 0x3feebf5668eaf2ef, // 0.27705, 0.96086 + 0x3fd1d3443f4cdb3d, 0x3feebbd8c8df0b74, // 0.27852, 0.96043 + 0x3fd1eb6643499fbb, 0x3feeb8566b810f2a, // 0.27999, 0.96 + 0x3fd2038583d727bd, 0x3feeb4cf515b8811, // 0.28146, 0.95957 + 0x3fd21ba1fd3d2623, 0x3feeb1437af9bb34, // 0.28294, 0.95914 + 0x3fd233bbabc3bb72, 0x3feeadb2e8e7a88e, // 0.28441, 0.9587 + 0x3fd24bd28bb37672, 0x3feeaa1d9bb20af3, // 0.28588, 0.95827 + 0x3fd263e6995554ba, 0x3feea68393e65800, // 0.28735, 0.95783 + 0x3fd27bf7d0f2c346, 0x3feea2e4d212c000, // 0.28882, 0.95738 + 0x3fd294062ed59f05, 0x3fee9f4156c62dda, // 0.29028, 0.95694 + 0x3fd2ac11af483572, 0x3fee9b99229046f8, // 0.29175, 0.95649 + 0x3fd2c41a4e954520, 0x3fee97ec36016b30, // 0.29322, 0.95605 + 0x3fd2dc200907fe51, 0x3fee943a91aab4b4, // 0.29469, 0.95559 + 0x3fd2f422daec0386, 0x3fee9084361df7f3, // 0.29615, 0.95514 + 0x3fd30c22c08d6a13, 0x3fee8cc923edc388, // 0.29762, 0.95469 + 0x3fd3241fb638baaf, 0x3fee89095bad6025, // 0.29908, 0.95423 + 0x3fd33c19b83af207, 0x3fee8544ddf0d075, // 0.30054, 0.95377 + 0x3fd35410c2e18152, 0x3fee817bab4cd10d, // 0.30201, 0.95331 + 0x3fd36c04d27a4edf, 0x3fee7dadc456d850, // 0.30347, 0.95284 + 0x3fd383f5e353b6aa, 0x3fee79db29a5165a, // 0.30493, 0.95238 + 0x3fd39be3f1bc8aef, 0x3fee7603dbce74e9, // 0.30639, 0.95191 + 0x3fd3b3cefa0414b7, 0x3fee7227db6a9744, // 0.30785, 0.95144 + 0x3fd3cbb6f87a146e, 0x3fee6e472911da27, // 0.30931, 0.95096 + 0x3fd3e39be96ec271, 0x3fee6a61c55d53a7, // 0.31077, 0.95049 + 0x3fd3fb7dc932cfa4, 0x3fee6677b0e6d31e, // 0.31222, 0.95001 + 0x3fd4135c94176602, 0x3fee6288ec48e112, // 0.31368, 0.94953 + 0x3fd42b38466e2928, 0x3fee5e95781ebf1c, // 0.31514, 0.94905 + 0x3fd44310dc8936f0, 0x3fee5a9d550467d3, // 0.31659, 0.94856 + 0x3fd45ae652bb2800, 0x3fee56a083968eb1, // 0.31805, 0.94807 + 0x3fd472b8a5571054, 0x3fee529f04729ffc, // 0.3195, 0.94759 + 0x3fd48a87d0b07fd7, 0x3fee4e98d836c0af, // 0.32096, 0.94709 + 0x3fd4a253d11b82f3, 0x3fee4a8dff81ce5e, // 0.32241, 0.9466 + 0x3fd4ba1ca2eca31c, 0x3fee467e7af35f23, // 0.32386, 0.94611 + 0x3fd4d1e24278e76a, 0x3fee426a4b2bc17e, // 0.32531, 0.94561 + 0x3fd4e9a4ac15d520, 0x3fee3e5170cbfc46, // 0.32676, 0.94511 + 0x3fd50163dc197047, 0x3fee3a33ec75ce85, // 0.32821, 0.9446 + 0x3fd5191fceda3c35, 0x3fee3611becbaf69, // 0.32966, 0.9441 + 0x3fd530d880af3c24, 0x3fee31eae870ce25, // 0.33111, 0.94359 + 0x3fd5488dedeff3be, 0x3fee2dbf6a0911d9, // 0.33255, 0.94308 + 0x3fd5604012f467b4, 0x3fee298f4439197a, // 0.334, 0.94257 + 0x3fd577eeec151e47, 0x3fee255a77a63bb8, // 0.33545, 0.94206 + 0x3fd58f9a75ab1fdd, 0x3fee212104f686e5, // 0.33689, 0.94154 + 0x3fd5a742ac0ff78d, 0x3fee1ce2ecd0c0d8, // 0.33833, 0.94103 + 0x3fd5bee78b9db3b6, 0x3fee18a02fdc66d9, // 0.33978, 0.94051 + 0x3fd5d68910aee686, 0x3fee1458cec1ad83, // 0.34122, 0.93998 + 0x3fd5ee27379ea693, 0x3fee100cca2980ac, // 0.34266, 0.93946 + 0x3fd605c1fcc88f63, 0x3fee0bbc22bd8349, // 0.3441, 0.93893 + 0x3fd61d595c88c203, 0x3fee0766d9280f54, // 0.34554, 0.9384 + 0x3fd634ed533be58e, 0x3fee030cee1435b8, // 0.34698, 0.93787 + 0x3fd64c7ddd3f27c6, 0x3fedfeae622dbe2b, // 0.34842, 0.93734 + 0x3fd6640af6f03d9e, 0x3fedfa4b3621271d, // 0.34986, 0.9368 + 0x3fd67b949cad63ca, 0x3fedf5e36a9ba59c, // 0.35129, 0.93627 + 0x3fd6931acad55f51, 0x3fedf177004b2534, // 0.35273, 0.93573 + 0x3fd6aa9d7dc77e16, 0x3feded05f7de47da, // 0.35416, 0.93518 + 0x3fd6c21cb1e39771, 0x3fede890520465ce, // 0.3556, 0.93464 + 0x3fd6d998638a0cb5, 0x3fede4160f6d8d81, // 0.35703, 0.93409 + 0x3fd6f1108f1bc9c5, 0x3feddf9730ca837b, // 0.35846, 0.93354 + 0x3fd7088530fa459e, 0x3feddb13b6ccc23d, // 0.3599, 0.93299 + 0x3fd71ff6458782ec, 0x3fedd68ba2267a25, // 0.36133, 0.93244 + 0x3fd73763c9261092, 0x3fedd1fef38a915a, // 0.36276, 0.93188 + 0x3fd74ecdb8390a3e, 0x3fedcd6dabaca3a5, // 0.36418, 0.93133 + 0x3fd766340f2418f6, 0x3fedc8d7cb410260, // 0.36561, 0.93077 + 0x3fd77d96ca4b73a6, 0x3fedc43d52fcb453, // 0.36704, 0.93021 + 0x3fd794f5e613dfae, 0x3fedbf9e4395759a, // 0.36847, 0.92964 + 0x3fd7ac515ee2b172, 0x3fedbafa9dc1b78d, // 0.36989, 0.92907 + 0x3fd7c3a9311dcce7, 0x3fedb6526238a09b, // 0.37132, 0.92851 + 0x3fd7dafd592ba621, 0x3fedb1a591b20c38, // 0.37274, 0.92794 + 0x3fd7f24dd37341e3, 0x3fedacf42ce68ab9, // 0.37416, 0.92736 + 0x3fd8099a9c5c362d, 0x3feda83e348f613b, // 0.37559, 0.92679 + 0x3fd820e3b04eaac4, 0x3feda383a9668988, // 0.37701, 0.92621 + 0x3fd838290bb359c8, 0x3fed9ec48c26b1f3, // 0.37843, 0.92563 + 0x3fd84f6aaaf3903f, 0x3fed9a00dd8b3d46, // 0.37985, 0.92505 + 0x3fd866a88a792ea0, 0x3fed95389e50429b, // 0.38127, 0.92447 + 0x3fd87de2a6aea963, 0x3fed906bcf328d46, // 0.38268, 0.92388 + 0x3fd89518fbff098e, 0x3fed8b9a70ef9cb4, // 0.3841, 0.92329 + 0x3fd8ac4b86d5ed44, 0x3fed86c48445a450, // 0.38552, 0.9227 + 0x3fd8c37a439f884f, 0x3fed81ea09f38b63, // 0.38693, 0.92211 + 0x3fd8daa52ec8a4af, 0x3fed7d0b02b8ecf9, // 0.38835, 0.92151 + 0x3fd8f1cc44bea329, 0x3fed78276f5617c6, // 0.38976, 0.92092 + 0x3fd908ef81ef7bd1, 0x3fed733f508c0dff, // 0.39117, 0.92032 + 0x3fd9200ee2c9be97, 0x3fed6e52a71c8547, // 0.39258, 0.91972 + 0x3fd9372a63bc93d7, 0x3fed696173c9e68b, // 0.39399, 0.91911 + 0x3fd94e420137bce3, 0x3fed646bb7574de5, // 0.3954, 0.91851 + 0x3fd96555b7ab948f, 0x3fed5f7172888a7f, // 0.39681, 0.9179 + 0x3fd97c6583890fc2, 0x3fed5a72a6221e73, // 0.39822, 0.91729 + 0x3fd993716141bdfe, 0x3fed556f52e93eb1, // 0.39962, 0.91668 + 0x3fd9aa794d47c9ee, 0x3fed506779a3d2d9, // 0.40103, 0.91606 + 0x3fd9c17d440df9f2, 0x3fed4b5b1b187524, // 0.40243, 0.91545 + 0x3fd9d87d4207b0ab, 0x3fed464a380e7242, // 0.40384, 0.91483 + 0x3fd9ef7943a8ed8a, 0x3fed4134d14dc93a, // 0.40524, 0.91421 + 0x3fda067145664d57, 0x3fed3c1ae79f2b4e, // 0.40664, 0.91359 + 0x3fda1d6543b50ac0, 0x3fed36fc7bcbfbdc, // 0.40804, 0.91296 + 0x3fda34553b0afee5, 0x3fed31d98e9e503a, // 0.40944, 0.91234 + 0x3fda4b4127dea1e4, 0x3fed2cb220e0ef9f, // 0.41084, 0.91171 + 0x3fda622906a70b63, 0x3fed2786335f52fc, // 0.41224, 0.91107 + 0x3fda790cd3dbf31a, 0x3fed2255c6e5a4e1, // 0.41364, 0.91044 + 0x3fda8fec8bf5b166, 0x3fed1d20dc40c15c, // 0.41503, 0.90981 + 0x3fdaa6c82b6d3fc9, 0x3fed17e7743e35dc, // 0.41643, 0.90917 + 0x3fdabd9faebc3980, 0x3fed12a98fac410c, // 0.41782, 0.90853 + 0x3fdad473125cdc08, 0x3fed0d672f59d2b9, // 0.41922, 0.90789 + 0x3fdaeb4252ca07ab, 0x3fed082054168bac, // 0.42061, 0.90724 + 0x3fdb020d6c7f4009, 0x3fed02d4feb2bd92, // 0.422, 0.9066 + 0x3fdb18d45bf8aca6, 0x3fecfd852fff6ad4, // 0.42339, 0.90595 + 0x3fdb2f971db31972, 0x3fecf830e8ce467b, // 0.42478, 0.9053 + 0x3fdb4655ae2bf757, 0x3fecf2d829f1b40e, // 0.42617, 0.90464 + 0x3fdb5d1009e15cc0, 0x3feced7af43cc773, // 0.42756, 0.90399 + 0x3fdb73c62d520624, 0x3fece819488344ce, // 0.42894, 0.90333 + 0x3fdb8a7814fd5693, 0x3fece2b32799a060, // 0.43033, 0.90267 + 0x3fdba125bd63583e, 0x3fecdd489254fe65, // 0.43171, 0.90201 + 0x3fdbb7cf2304bd01, 0x3fecd7d9898b32f6, // 0.43309, 0.90135 + 0x3fdbce744262deee, 0x3fecd2660e12c1e6, // 0.43448, 0.90068 + 0x3fdbe51517ffc0d9, 0x3fecccee20c2de9f, // 0.43586, 0.90002 + 0x3fdbfbb1a05e0edc, 0x3fecc771c2736c09, // 0.43724, 0.89935 + 0x3fdc1249d8011ee7, 0x3fecc1f0f3fcfc5c, // 0.43862, 0.89867 + 0x3fdc28ddbb6cf145, 0x3fecbc6bb638d10b, // 0.43999, 0.898 + 0x3fdc3f6d47263129, 0x3fecb6e20a00da99, // 0.44137, 0.89732 + 0x3fdc55f877b23537, 0x3fecb153f02fb87d, // 0.44275, 0.89665 + 0x3fdc6c7f4997000a, 0x3fecabc169a0b901, // 0.44412, 0.89597 + 0x3fdc8301b95b40c2, 0x3feca62a772fd919, // 0.4455, 0.89528 + 0x3fdc997fc3865388, 0x3feca08f19b9c449, // 0.44687, 0.8946 + 0x3fdcaff964a0421d, 0x3fec9aef521bd480, // 0.44824, 0.89391 + 0x3fdcc66e9931c45d, 0x3fec954b213411f5, // 0.44961, 0.89322 + 0x3fdcdcdf5dc440ce, 0x3fec8fa287e13305, // 0.45098, 0.89253 + 0x3fdcf34baee1cd21, 0x3fec89f587029c13, // 0.45235, 0.89184 + 0x3fdd09b389152ec1, 0x3fec84441f785f61, // 0.45372, 0.89115 + 0x3fdd2016e8e9db5b, 0x3fec7e8e52233cf3, // 0.45508, 0.89045 + 0x3fdd3675caebf962, 0x3fec78d41fe4a267, // 0.45645, 0.88975 + 0x3fdd4cd02ba8609c, 0x3fec7315899eaad7, // 0.45781, 0.88905 + 0x3fdd632607ac9aa9, 0x3fec6d5290341eb2, // 0.45918, 0.88835 + 0x3fdd79775b86e389, 0x3fec678b3488739b, // 0.46054, 0.88764 + 0x3fdd8fc423c62a25, 0x3fec61bf777fcc48, // 0.4619, 0.88693 + 0x3fdda60c5cfa10d8, 0x3fec5bef59fef85a, // 0.46326, 0.88622 + 0x3fddbc5003b2edf8, 0x3fec561adceb743e, // 0.46462, 0.88551 + 0x3fddd28f1481cc58, 0x3fec5042012b6907, // 0.46598, 0.8848 + 0x3fdde8c98bf86bd6, 0x3fec4a64c7a5ac4c, // 0.46733, 0.88408 + 0x3fddfeff66a941de, 0x3fec44833141c004, // 0.46869, 0.88336 + 0x3fde1530a12779f4, 0x3fec3e9d3ee7d262, // 0.47004, 0.88264 + 0x3fde2b5d3806f63b, 0x3fec38b2f180bdb1, // 0.4714, 0.88192 + 0x3fde418527dc4ffa, 0x3fec32c449f60831, // 0.47275, 0.8812 + 0x3fde57a86d3cd824, 0x3fec2cd14931e3f1, // 0.4741, 0.88047 + 0x3fde6dc704be97e2, 0x3fec26d9f01f2eaf, // 0.47545, 0.87974 + 0x3fde83e0eaf85113, 0x3fec20de3fa971b0, // 0.4768, 0.87901 + 0x3fde99f61c817eda, 0x3fec1ade38bce19b, // 0.47815, 0.87828 + 0x3fdeb00695f25620, 0x3fec14d9dc465e58, // 0.47949, 0.87755 + 0x3fdec61253e3c61b, 0x3fec0ed12b3372e9, // 0.48084, 0.87681 + 0x3fdedc1952ef78d5, 0x3fec08c426725549, // 0.48218, 0.87607 + 0x3fdef21b8fafd3b5, 0x3fec02b2cef1e641, // 0.48353, 0.87533 + 0x3fdf081906bff7fd, 0x3febfc9d25a1b147, // 0.48487, 0.87459 + 0x3fdf1e11b4bbc35c, 0x3febf6832b71ec5b, // 0.48621, 0.87384 + 0x3fdf3405963fd068, 0x3febf064e15377dd, // 0.48755, 0.87309 + 0x3fdf49f4a7e97729, 0x3febea424837de6d, // 0.48889, 0.87235 + 0x3fdf5fdee656cda3, 0x3febe41b611154c1, // 0.49023, 0.8716 + 0x3fdf75c44e26a852, 0x3febddf02cd2b983, // 0.49156, 0.87084 + 0x3fdf8ba4dbf89aba, 0x3febd7c0ac6f952a, // 0.4929, 0.87009 + 0x3fdfa1808c6cf7e0, 0x3febd18ce0dc19d6, // 0.49423, 0.86933 + 0x3fdfb7575c24d2de, 0x3febcb54cb0d2327, // 0.49557, 0.86857 + 0x3fdfcd2947c1ff57, 0x3febc5186bf8361d, // 0.4969, 0.86781 + 0x3fdfe2f64be7120f, 0x3febbed7c49380ea, // 0.49823, 0.86705 + 0x3fdff8be6537615e, 0x3febb892d5d5dad5, // 0.49956, 0.86628 + 0x3fe00740c82b82e0, 0x3febb249a0b6c40d, // 0.50089, 0.86551 + 0x3fe0121fe4f56d2c, 0x3febabfc262e6586, // 0.50221, 0.86474 + 0x3fe01cfc874c3eb7, 0x3feba5aa673590d2, // 0.50354, 0.86397 + 0x3fe027d6ad83287e, 0x3feb9f5464c5bffc, // 0.50486, 0.8632 + 0x3fe032ae55edbd95, 0x3feb98fa1fd9155e, // 0.50619, 0.86242 + 0x3fe03d837edff370, 0x3feb929b996a5b7f, // 0.50751, 0.86165 + 0x3fe0485626ae221a, 0x3feb8c38d27504e9, // 0.50883, 0.86087 + 0x3fe053264bad0483, 0x3feb85d1cbf52c02, // 0.51015, 0.86009 + 0x3fe05df3ec31b8b6, 0x3feb7f6686e792ea, // 0.51147, 0.8593 + 0x3fe068bf0691c028, 0x3feb78f70449a34b, // 0.51279, 0.85852 + 0x3fe073879922ffed, 0x3feb728345196e3e, // 0.5141, 0.85773 + 0x3fe07e4da23bc102, 0x3feb6c0b4a55ac17, // 0.51542, 0.85694 + 0x3fe089112032b08c, 0x3feb658f14fdbc47, // 0.51673, 0.85615 + 0x3fe093d2115ee018, 0x3feb5f0ea611a532, // 0.51804, 0.85535 + 0x3fe09e907417c5e1, 0x3feb5889fe921405, // 0.51936, 0.85456 + 0x3fe0a94c46b53d0b, 0x3feb52011f805c92, // 0.52067, 0.85376 + 0x3fe0b405878f85ec, 0x3feb4b7409de7925, // 0.52198, 0.85296 + 0x3fe0bebc34ff4646, 0x3feb44e2beaf0a61, // 0.52328, 0.85216 + 0x3fe0c9704d5d898f, 0x3feb3e4d3ef55712, // 0.52459, 0.85136 + 0x3fe0d421cf03c12b, 0x3feb37b38bb54c09, // 0.5259, 0.85055 + 0x3fe0ded0b84bc4b5, 0x3feb3115a5f37bf4, // 0.5272, 0.84974 + 0x3fe0e97d078fd23b, 0x3feb2a738eb51f33, // 0.5285, 0.84893 + 0x3fe0f426bb2a8e7d, 0x3feb23cd470013b4, // 0.5298, 0.84812 + 0x3fe0fecdd1770537, 0x3feb1d22cfdadcc6, // 0.5311, 0.84731 + 0x3fe1097248d0a956, 0x3feb16742a4ca2f5, // 0.5324, 0.84649 + 0x3fe114141f935545, 0x3feb0fc1575d33db, // 0.5337, 0.84567 + 0x3fe11eb3541b4b22, 0x3feb090a58150200, // 0.535, 0.84485 + 0x3fe1294fe4c5350a, 0x3feb024f2d7d24a9, // 0.53629, 0.84403 + 0x3fe133e9cfee254e, 0x3feafb8fd89f57b6, // 0.53759, 0.84321 + 0x3fe13e8113f396c1, 0x3feaf4cc5a85fb73, // 0.53888, 0.84238 + 0x3fe14915af336ceb, 0x3feaee04b43c1474, // 0.54017, 0.84155 + 0x3fe153a7a00bf453, 0x3feae738e6cd4b67, // 0.54146, 0.84073 + 0x3fe15e36e4dbe2bc, 0x3feae068f345ecef, // 0.54275, 0.83989 + 0x3fe168c37c025764, 0x3fead994dab2e979, // 0.54404, 0.83906 + 0x3fe1734d63dedb49, 0x3fead2bc9e21d511, // 0.54532, 0.83822 + 0x3fe17dd49ad16161, 0x3feacbe03ea0e73b, // 0.54661, 0.83739 + 0x3fe188591f3a46e5, 0x3feac4ffbd3efac8, // 0.54789, 0.83655 + 0x3fe192daef7a5386, 0x3feabe1b1b0b8dac, // 0.54918, 0.83571 + 0x3fe19d5a09f2b9b8, 0x3feab7325916c0d4, // 0.55046, 0.83486 + 0x3fe1a7d66d0516e6, 0x3feab045787157ff, // 0.55174, 0.83402 + 0x3fe1b250171373be, 0x3feaa9547a2cb98e, // 0.55302, 0.83317 + 0x3fe1bcc706804467, 0x3feaa25f5f5aee60, // 0.55429, 0.83232 + 0x3fe1c73b39ae68c8, 0x3fea9b66290ea1a3, // 0.55557, 0.83147 + 0x3fe1d1acaf012cc2, 0x3fea9468d85b20ae, // 0.55685, 0.83062 + 0x3fe1dc1b64dc4872, 0x3fea8d676e545ad2, // 0.55812, 0.82976 + 0x3fe1e68759a3e074, 0x3fea8661ec0ee133, // 0.55939, 0.8289 + 0x3fe1f0f08bbc861b, 0x3fea7f58529fe69d, // 0.56066, 0.82805 + 0x3fe1fb56f98b37b8, 0x3fea784aa31d3f55, // 0.56193, 0.82718 + 0x3fe205baa17560d6, 0x3fea7138de9d60f5, // 0.5632, 0.82632 + 0x3fe2101b81e0da78, 0x3fea6a230637623b, // 0.56447, 0.82546 + 0x3fe21a799933eb58, 0x3fea63091b02fae2, // 0.56573, 0.82459 + 0x3fe224d4e5d5482e, 0x3fea5beb1e188375, // 0.567, 0.82372 + 0x3fe22f2d662c13e1, 0x3fea54c91090f524, // 0.56826, 0.82285 + 0x3fe23983189fdfd5, 0x3fea4da2f385e997, // 0.56952, 0.82198 + 0x3fe243d5fb98ac1f, 0x3fea4678c8119ac8, // 0.57078, 0.8211 + 0x3fe24e260d7ee7c9, 0x3fea3f4a8f4ee2d2, // 0.57204, 0.82023 + 0x3fe258734cbb7110, 0x3fea38184a593bc6, // 0.5733, 0.81935 + 0x3fe262bdb7b795a2, 0x3fea30e1fa4cbf81, // 0.57455, 0.81847 + 0x3fe26d054cdd12df, 0x3fea29a7a0462782, // 0.57581, 0.81758 + 0x3fe2774a0a961612, 0x3fea22693d62ccb9, // 0.57706, 0.8167 + 0x3fe2818bef4d3cba, 0x3fea1b26d2c0a75e, // 0.57831, 0.81581 + 0x3fe28bcaf96d94ba, 0x3fea13e0617e4ec7, // 0.57956, 0.81493 + 0x3fe2960727629ca8, 0x3fea0c95eabaf937, // 0.58081, 0.81404 + 0x3fe2a040779843fb, 0x3fea05476f967bb5, // 0.58206, 0.81314 + 0x3fe2aa76e87aeb58, 0x3fe9fdf4f13149de, // 0.58331, 0.81225 + 0x3fe2b4aa787764c4, 0x3fe9f69e70ac75bc, // 0.58455, 0.81135 + 0x3fe2bedb25faf3ea, 0x3fe9ef43ef29af94, // 0.5858, 0.81046 + 0x3fe2c908ef734e57, 0x3fe9e7e56dcb45bd, // 0.58704, 0.80956 + 0x3fe2d333d34e9bb7, 0x3fe9e082edb42472, // 0.58828, 0.80866 + 0x3fe2dd5bcffb7616, 0x3fe9d91c7007d5a6, // 0.58952, 0.80775 + 0x3fe2e780e3e8ea16, 0x3fe9d1b1f5ea80d6, // 0.59076, 0.80685 + 0x3fe2f1a30d86773a, 0x3fe9ca438080eadb, // 0.592, 0.80594 + 0x3fe2fbc24b441015, 0x3fe9c2d110f075c3, // 0.59323, 0.80503 + 0x3fe305de9b921a94, 0x3fe9bb5aa85f2098, // 0.59447, 0.80412 + 0x3fe30ff7fce17035, 0x3fe9b3e047f38741, // 0.5957, 0.80321 + 0x3fe31a0e6da35e44, 0x3fe9ac61f0d4e247, // 0.59693, 0.80229 + 0x3fe32421ec49a620, 0x3fe9a4dfa42b06b2, // 0.59816, 0.80138 + 0x3fe32e3277467d6b, 0x3fe99d59631e65d5, // 0.59939, 0.80046 + 0x3fe338400d0c8e57, 0x3fe995cf2ed80d22, // 0.60062, 0.79954 + 0x3fe3424aac0ef7d6, 0x3fe98e410881a600, // 0.60184, 0.79861 + 0x3fe34c5252c14de1, 0x3fe986aef1457594, // 0.60307, 0.79769 + 0x3fe35656ff9799ae, 0x3fe97f18ea4e5c9e, // 0.60429, 0.79676 + 0x3fe36058b10659f3, 0x3fe9777ef4c7d742, // 0.60551, 0.79584 + 0x3fe36a576582831b, 0x3fe96fe111ddfce0, // 0.60673, 0.79491 + 0x3fe374531b817f8d, 0x3fe9683f42bd7fe1, // 0.60795, 0.79398 + 0x3fe37e4bd1792fe2, 0x3fe960998893ad8c, // 0.60917, 0.79304 + 0x3fe3884185dfeb22, 0x3fe958efe48e6dd7, // 0.61038, 0.79211 + 0x3fe39234372c7f04, 0x3fe9514257dc4335, // 0.6116, 0.79117 + 0x3fe39c23e3d63029, 0x3fe94990e3ac4a6c, // 0.61281, 0.79023 + 0x3fe3a6108a54ba58, 0x3fe941db892e3a65, // 0.61402, 0.78929 + 0x3fe3affa292050b9, 0x3fe93a22499263fc, // 0.61523, 0.78835 + 0x3fe3b9e0beb19e18, 0x3fe932652609b1cf, // 0.61644, 0.7874 + 0x3fe3c3c44981c517, 0x3fe92aa41fc5a815, // 0.61765, 0.78646 + 0x3fe3cda4c80a6076, 0x3fe922df37f8646a, // 0.61885, 0.78551 + 0x3fe3d78238c58343, 0x3fe91b166fd49da2, // 0.62006, 0.78456 + 0x3fe3e15c9a2db922, 0x3fe91349c88da398, // 0.62126, 0.7836 + 0x3fe3eb33eabe0680, 0x3fe90b7943575efe, // 0.62246, 0.78265 + 0x3fe3f50828f1e8d2, 0x3fe903a4e1665133, // 0.62366, 0.78169 + 0x3fe3fed9534556d4, 0x3fe8fbcca3ef940d, // 0.62486, 0.78074 + 0x3fe408a76834c0c0, 0x3fe8f3f08c28d9ac, // 0.62606, 0.77978 + 0x3fe41272663d108c, 0x3fe8ec109b486c49, // 0.62725, 0.77882 + 0x3fe41c3a4bdbaa26, 0x3fe8e42cd2852e0a, // 0.62845, 0.77785 + 0x3fe425ff178e6bb1, 0x3fe8dc45331698cc, // 0.62964, 0.77689 + 0x3fe42fc0c7d3adbb, 0x3fe8d459be34bdfa, // 0.63083, 0.77592 + 0x3fe4397f5b2a4380, 0x3fe8cc6a75184655, // 0.63202, 0.77495 + 0x3fe4433ad0117b1d, 0x3fe8c47758fa71cb, // 0.63321, 0.77398 + 0x3fe44cf325091dd6, 0x3fe8bc806b151741, // 0.63439, 0.77301 + 0x3fe456a858917046, 0x3fe8b485aca2a468, // 0.63558, 0.77204 + 0x3fe4605a692b32a2, 0x3fe8ac871ede1d88, // 0.63676, 0.77106 + 0x3fe46a095557a0f1, 0x3fe8a484c3031d50, // 0.63794, 0.77008 + 0x3fe473b51b987347, 0x3fe89c7e9a4dd4ab, // 0.63912, 0.7691 + 0x3fe47d5dba6fde01, 0x3fe89474a5fb0a84, // 0.6403, 0.76812 + 0x3fe48703306091fe, 0x3fe88c66e7481ba1, // 0.64148, 0.76714 + 0x3fe490a57bedbcdf, 0x3fe884555f72fa6b, // 0.64266, 0.76615 + 0x3fe49a449b9b0938, 0x3fe87c400fba2ebf, // 0.64383, 0.76517 + 0x3fe4a3e08dec9ed6, 0x3fe87426f95cd5bd, // 0.645, 0.76418 + 0x3fe4ad79516722f0, 0x3fe86c0a1d9aa195, // 0.64618, 0.76319 + 0x3fe4b70ee48fb869, 0x3fe863e97db3d95a, // 0.64735, 0.7622 + 0x3fe4c0a145ec0004, 0x3fe85bc51ae958cc, // 0.64851, 0.7612 + 0x3fe4ca30740218a3, 0x3fe8539cf67c9029, // 0.64968, 0.76021 + 0x3fe4d3bc6d589f80, 0x3fe84b7111af83f9, // 0.65085, 0.75921 + 0x3fe4dd453076b064, 0x3fe843416dc4cce2, // 0.65201, 0.75821 + 0x3fe4e6cabbe3e5e9, 0x3fe83b0e0bff976e, // 0.65317, 0.75721 + 0x3fe4f04d0e2859aa, 0x3fe832d6eda3a3e0, // 0.65433, 0.75621 + 0x3fe4f9cc25cca486, 0x3fe82a9c13f545ff, // 0.65549, 0.7552 + 0x3fe503480159ded2, 0x3fe8225d803964e5, // 0.65665, 0.75419 + 0x3fe50cc09f59a09b, 0x3fe81a1b33b57acc, // 0.65781, 0.75319 + 0x3fe51635fe5601d7, 0x3fe811d52faf94dc, // 0.65896, 0.75218 + 0x3fe51fa81cd99aa6, 0x3fe8098b756e52fa, // 0.66011, 0.75117 + 0x3fe52916f96f8388, 0x3fe8013e0638e795, // 0.66127, 0.75015 + 0x3fe5328292a35596, 0x3fe7f8ece3571771, // 0.66242, 0.74914 + 0x3fe53beae7012abe, 0x3fe7f0980e113978, // 0.66356, 0.74812 + 0x3fe5454ff5159dfb, 0x3fe7e83f87b03686, // 0.66471, 0.7471 + 0x3fe54eb1bb6dcb8f, 0x3fe7dfe3517d8937, // 0.66586, 0.74608 + 0x3fe5581038975137, 0x3fe7d7836cc33db2, // 0.667, 0.74506 + 0x3fe5616b6b204e6e, 0x3fe7cf1fdacbf179, // 0.66814, 0.74403 + 0x3fe56ac35197649e, 0x3fe7c6b89ce2d333, // 0.66928, 0.74301 + 0x3fe57417ea8bb75c, 0x3fe7be4db453a27c, // 0.67042, 0.74198 + 0x3fe57d69348cec9f, 0x3fe7b5df226aafb0, // 0.67156, 0.74095 + 0x3fe586b72e2b2cfd, 0x3fe7ad6ce874dbb6, // 0.67269, 0.73992 + 0x3fe59001d5f723df, 0x3fe7a4f707bf97d2, // 0.67383, 0.73889 + 0x3fe599492a81ffbc, 0x3fe79c7d8198e56e, // 0.67496, 0.73785 + 0x3fe5a28d2a5d7250, 0x3fe79400574f55e4, // 0.67609, 0.73682 + 0x3fe5abcdd41bb0d8, 0x3fe78b7f8a320a52, // 0.67722, 0.73578 + 0x3fe5b50b264f7448, 0x3fe782fb1b90b35b, // 0.67835, 0.73474 + 0x3fe5be451f8bf980, 0x3fe77a730cbb9100, // 0.67948, 0.7337 + 0x3fe5c77bbe65018c, 0x3fe771e75f037261, // 0.6806, 0.73265 + 0x3fe5d0af016ed1d4, 0x3fe7695813b9b594, // 0.68172, 0.73161 + 0x3fe5d9dee73e345c, 0x3fe760c52c304764, // 0.68285, 0.73056 + 0x3fe5e30b6e6877f3, 0x3fe7582ea9b9a329, // 0.68397, 0.72951 + 0x3fe5ec3495837074, 0x3fe74f948da8d28d, // 0.68508, 0.72846 + 0x3fe5f55a5b2576f8, 0x3fe746f6d9516d59, // 0.6862, 0.72741 + 0x3fe5fe7cbde56a0f, 0x3fe73e558e079942, // 0.68732, 0.72636 + 0x3fe6079bbc5aadfa, 0x3fe735b0ad2009b2, // 0.68843, 0.7253 + 0x3fe610b7551d2cde, 0x3fe72d0837efff97, // 0.68954, 0.72425 + 0x3fe619cf86c55702, 0x3fe7245c2fcd492a, // 0.69065, 0.72319 + 0x3fe622e44fec22ff, 0x3fe71bac960e41bf, // 0.69176, 0.72213 + 0x3fe62bf5af2b0dfd, 0x3fe712f96c09d18d, // 0.69287, 0.72107 + 0x3fe63503a31c1be8, 0x3fe70a42b3176d7a, // 0.69397, 0.72 + 0x3fe63e0e2a59d7aa, 0x3fe701886c8f16e6, // 0.69508, 0.71894 + 0x3fe64715437f535b, 0x3fe6f8ca99c95b75, // 0.69618, 0.71787 + 0x3fe65018ed28287f, 0x3fe6f0093c1f54de, // 0.69728, 0.7168 + 0x3fe6591925f0783e, 0x3fe6e74454eaa8ae, // 0.69838, 0.71573 + 0x3fe66215ec74eb91, 0x3fe6de7be585881d, // 0.69947, 0.71466 + 0x3fe66b0f3f52b386, 0x3fe6d5afef4aafcc, // 0.70057, 0.71358 + 0x3fe674051d27896c, 0x3fe6cce07395679f, // 0.70166, 0.71251 + 0x3fe67cf78491af10, 0x3fe6c40d73c18275, // 0.70275, 0.71143 + 0x3fe685e6742feeef, 0x3fe6bb36f12b5e06, // 0.70385, 0.71035 + 0x3fe68ed1eaa19c71, 0x3fe6b25ced2fe29c, // 0.70493, 0.70927 + 0x3fe697b9e686941c, 0x3fe6a97f692c82ea, // 0.70602, 0.70819 + 0x3fe6a09e667f3bcc, 0x3fe6a09e667f3bcc, // 0.70711, 0.70711 + 0x3fe6a97f692c82ea, 0x3fe697b9e686941c, // 0.70819, 0.70602 + 0x3fe6b25ced2fe29c, 0x3fe68ed1eaa19c71, // 0.70927, 0.70493 + 0x3fe6bb36f12b5e06, 0x3fe685e6742feeef, // 0.71035, 0.70385 + 0x3fe6c40d73c18275, 0x3fe67cf78491af10, // 0.71143, 0.70275 + 0x3fe6cce07395679f, 0x3fe674051d27896c, // 0.71251, 0.70166 + 0x3fe6d5afef4aafcc, 0x3fe66b0f3f52b386, // 0.71358, 0.70057 + 0x3fe6de7be585881d, 0x3fe66215ec74eb91, // 0.71466, 0.69947 + 0x3fe6e74454eaa8ae, 0x3fe6591925f0783e, // 0.71573, 0.69838 + 0x3fe6f0093c1f54de, 0x3fe65018ed28287f, // 0.7168, 0.69728 + 0x3fe6f8ca99c95b75, 0x3fe64715437f535b, // 0.71787, 0.69618 + 0x3fe701886c8f16e6, 0x3fe63e0e2a59d7aa, // 0.71894, 0.69508 + 0x3fe70a42b3176d7a, 0x3fe63503a31c1be8, // 0.72, 0.69397 + 0x3fe712f96c09d18d, 0x3fe62bf5af2b0dfd, // 0.72107, 0.69287 + 0x3fe71bac960e41bf, 0x3fe622e44fec22ff, // 0.72213, 0.69176 + 0x3fe7245c2fcd492a, 0x3fe619cf86c55702, // 0.72319, 0.69065 + 0x3fe72d0837efff97, 0x3fe610b7551d2cde, // 0.72425, 0.68954 + 0x3fe735b0ad2009b2, 0x3fe6079bbc5aadfa, // 0.7253, 0.68843 + 0x3fe73e558e079942, 0x3fe5fe7cbde56a0f, // 0.72636, 0.68732 + 0x3fe746f6d9516d59, 0x3fe5f55a5b2576f8, // 0.72741, 0.6862 + 0x3fe74f948da8d28d, 0x3fe5ec3495837074, // 0.72846, 0.68508 + 0x3fe7582ea9b9a329, 0x3fe5e30b6e6877f3, // 0.72951, 0.68397 + 0x3fe760c52c304764, 0x3fe5d9dee73e345c, // 0.73056, 0.68285 + 0x3fe7695813b9b594, 0x3fe5d0af016ed1d4, // 0.73161, 0.68172 + 0x3fe771e75f037261, 0x3fe5c77bbe65018c, // 0.73265, 0.6806 + 0x3fe77a730cbb9100, 0x3fe5be451f8bf980, // 0.7337, 0.67948 + 0x3fe782fb1b90b35b, 0x3fe5b50b264f7448, // 0.73474, 0.67835 + 0x3fe78b7f8a320a52, 0x3fe5abcdd41bb0d8, // 0.73578, 0.67722 + 0x3fe79400574f55e4, 0x3fe5a28d2a5d7250, // 0.73682, 0.67609 + 0x3fe79c7d8198e56e, 0x3fe599492a81ffbc, // 0.73785, 0.67496 + 0x3fe7a4f707bf97d2, 0x3fe59001d5f723df, // 0.73889, 0.67383 + 0x3fe7ad6ce874dbb6, 0x3fe586b72e2b2cfd, // 0.73992, 0.67269 + 0x3fe7b5df226aafb0, 0x3fe57d69348cec9f, // 0.74095, 0.67156 + 0x3fe7be4db453a27c, 0x3fe57417ea8bb75c, // 0.74198, 0.67042 + 0x3fe7c6b89ce2d333, 0x3fe56ac35197649e, // 0.74301, 0.66928 + 0x3fe7cf1fdacbf179, 0x3fe5616b6b204e6e, // 0.74403, 0.66814 + 0x3fe7d7836cc33db2, 0x3fe5581038975137, // 0.74506, 0.667 + 0x3fe7dfe3517d8937, 0x3fe54eb1bb6dcb8f, // 0.74608, 0.66586 + 0x3fe7e83f87b03686, 0x3fe5454ff5159dfb, // 0.7471, 0.66471 + 0x3fe7f0980e113978, 0x3fe53beae7012abe, // 0.74812, 0.66356 + 0x3fe7f8ece3571771, 0x3fe5328292a35596, // 0.74914, 0.66242 + 0x3fe8013e0638e795, 0x3fe52916f96f8388, // 0.75015, 0.66127 + 0x3fe8098b756e52fa, 0x3fe51fa81cd99aa6, // 0.75117, 0.66011 + 0x3fe811d52faf94dc, 0x3fe51635fe5601d7, // 0.75218, 0.65896 + 0x3fe81a1b33b57acc, 0x3fe50cc09f59a09b, // 0.75319, 0.65781 + 0x3fe8225d803964e5, 0x3fe503480159ded2, // 0.75419, 0.65665 + 0x3fe82a9c13f545ff, 0x3fe4f9cc25cca486, // 0.7552, 0.65549 + 0x3fe832d6eda3a3e0, 0x3fe4f04d0e2859aa, // 0.75621, 0.65433 + 0x3fe83b0e0bff976e, 0x3fe4e6cabbe3e5e9, // 0.75721, 0.65317 + 0x3fe843416dc4cce2, 0x3fe4dd453076b064, // 0.75821, 0.65201 + 0x3fe84b7111af83f9, 0x3fe4d3bc6d589f80, // 0.75921, 0.65085 + 0x3fe8539cf67c9029, 0x3fe4ca30740218a3, // 0.76021, 0.64968 + 0x3fe85bc51ae958cc, 0x3fe4c0a145ec0004, // 0.7612, 0.64851 + 0x3fe863e97db3d95a, 0x3fe4b70ee48fb869, // 0.7622, 0.64735 + 0x3fe86c0a1d9aa195, 0x3fe4ad79516722f0, // 0.76319, 0.64618 + 0x3fe87426f95cd5bd, 0x3fe4a3e08dec9ed6, // 0.76418, 0.645 + 0x3fe87c400fba2ebf, 0x3fe49a449b9b0938, // 0.76517, 0.64383 + 0x3fe884555f72fa6b, 0x3fe490a57bedbcdf, // 0.76615, 0.64266 + 0x3fe88c66e7481ba1, 0x3fe48703306091fe, // 0.76714, 0.64148 + 0x3fe89474a5fb0a84, 0x3fe47d5dba6fde01, // 0.76812, 0.6403 + 0x3fe89c7e9a4dd4ab, 0x3fe473b51b987347, // 0.7691, 0.63912 + 0x3fe8a484c3031d50, 0x3fe46a095557a0f1, // 0.77008, 0.63794 + 0x3fe8ac871ede1d88, 0x3fe4605a692b32a2, // 0.77106, 0.63676 + 0x3fe8b485aca2a468, 0x3fe456a858917046, // 0.77204, 0.63558 + 0x3fe8bc806b151741, 0x3fe44cf325091dd6, // 0.77301, 0.63439 + 0x3fe8c47758fa71cb, 0x3fe4433ad0117b1d, // 0.77398, 0.63321 + 0x3fe8cc6a75184655, 0x3fe4397f5b2a4380, // 0.77495, 0.63202 + 0x3fe8d459be34bdfa, 0x3fe42fc0c7d3adbb, // 0.77592, 0.63083 + 0x3fe8dc45331698cc, 0x3fe425ff178e6bb1, // 0.77689, 0.62964 + 0x3fe8e42cd2852e0a, 0x3fe41c3a4bdbaa26, // 0.77785, 0.62845 + 0x3fe8ec109b486c49, 0x3fe41272663d108c, // 0.77882, 0.62725 + 0x3fe8f3f08c28d9ac, 0x3fe408a76834c0c0, // 0.77978, 0.62606 + 0x3fe8fbcca3ef940d, 0x3fe3fed9534556d4, // 0.78074, 0.62486 + 0x3fe903a4e1665133, 0x3fe3f50828f1e8d2, // 0.78169, 0.62366 + 0x3fe90b7943575efe, 0x3fe3eb33eabe0680, // 0.78265, 0.62246 + 0x3fe91349c88da398, 0x3fe3e15c9a2db922, // 0.7836, 0.62126 + 0x3fe91b166fd49da2, 0x3fe3d78238c58343, // 0.78456, 0.62006 + 0x3fe922df37f8646a, 0x3fe3cda4c80a6076, // 0.78551, 0.61885 + 0x3fe92aa41fc5a815, 0x3fe3c3c44981c517, // 0.78646, 0.61765 + 0x3fe932652609b1cf, 0x3fe3b9e0beb19e18, // 0.7874, 0.61644 + 0x3fe93a22499263fc, 0x3fe3affa292050b9, // 0.78835, 0.61523 + 0x3fe941db892e3a65, 0x3fe3a6108a54ba58, // 0.78929, 0.61402 + 0x3fe94990e3ac4a6c, 0x3fe39c23e3d63029, // 0.79023, 0.61281 + 0x3fe9514257dc4335, 0x3fe39234372c7f04, // 0.79117, 0.6116 + 0x3fe958efe48e6dd7, 0x3fe3884185dfeb22, // 0.79211, 0.61038 + 0x3fe960998893ad8c, 0x3fe37e4bd1792fe2, // 0.79304, 0.60917 + 0x3fe9683f42bd7fe1, 0x3fe374531b817f8d, // 0.79398, 0.60795 + 0x3fe96fe111ddfce0, 0x3fe36a576582831b, // 0.79491, 0.60673 + 0x3fe9777ef4c7d742, 0x3fe36058b10659f3, // 0.79584, 0.60551 + 0x3fe97f18ea4e5c9e, 0x3fe35656ff9799ae, // 0.79676, 0.60429 + 0x3fe986aef1457594, 0x3fe34c5252c14de1, // 0.79769, 0.60307 + 0x3fe98e410881a600, 0x3fe3424aac0ef7d6, // 0.79861, 0.60184 + 0x3fe995cf2ed80d22, 0x3fe338400d0c8e57, // 0.79954, 0.60062 + 0x3fe99d59631e65d5, 0x3fe32e3277467d6b, // 0.80046, 0.59939 + 0x3fe9a4dfa42b06b2, 0x3fe32421ec49a620, // 0.80138, 0.59816 + 0x3fe9ac61f0d4e247, 0x3fe31a0e6da35e44, // 0.80229, 0.59693 + 0x3fe9b3e047f38741, 0x3fe30ff7fce17035, // 0.80321, 0.5957 + 0x3fe9bb5aa85f2098, 0x3fe305de9b921a94, // 0.80412, 0.59447 + 0x3fe9c2d110f075c3, 0x3fe2fbc24b441015, // 0.80503, 0.59323 + 0x3fe9ca438080eadb, 0x3fe2f1a30d86773a, // 0.80594, 0.592 + 0x3fe9d1b1f5ea80d6, 0x3fe2e780e3e8ea16, // 0.80685, 0.59076 + 0x3fe9d91c7007d5a6, 0x3fe2dd5bcffb7616, // 0.80775, 0.58952 + 0x3fe9e082edb42472, 0x3fe2d333d34e9bb7, // 0.80866, 0.58828 + 0x3fe9e7e56dcb45bd, 0x3fe2c908ef734e57, // 0.80956, 0.58704 + 0x3fe9ef43ef29af94, 0x3fe2bedb25faf3ea, // 0.81046, 0.5858 + 0x3fe9f69e70ac75bc, 0x3fe2b4aa787764c4, // 0.81135, 0.58455 + 0x3fe9fdf4f13149de, 0x3fe2aa76e87aeb58, // 0.81225, 0.58331 + 0x3fea05476f967bb5, 0x3fe2a040779843fb, // 0.81314, 0.58206 + 0x3fea0c95eabaf937, 0x3fe2960727629ca8, // 0.81404, 0.58081 + 0x3fea13e0617e4ec7, 0x3fe28bcaf96d94ba, // 0.81493, 0.57956 + 0x3fea1b26d2c0a75e, 0x3fe2818bef4d3cba, // 0.81581, 0.57831 + 0x3fea22693d62ccb9, 0x3fe2774a0a961612, // 0.8167, 0.57706 + 0x3fea29a7a0462782, 0x3fe26d054cdd12df, // 0.81758, 0.57581 + 0x3fea30e1fa4cbf81, 0x3fe262bdb7b795a2, // 0.81847, 0.57455 + 0x3fea38184a593bc6, 0x3fe258734cbb7110, // 0.81935, 0.5733 + 0x3fea3f4a8f4ee2d2, 0x3fe24e260d7ee7c9, // 0.82023, 0.57204 + 0x3fea4678c8119ac8, 0x3fe243d5fb98ac1f, // 0.8211, 0.57078 + 0x3fea4da2f385e997, 0x3fe23983189fdfd5, // 0.82198, 0.56952 + 0x3fea54c91090f524, 0x3fe22f2d662c13e1, // 0.82285, 0.56826 + 0x3fea5beb1e188375, 0x3fe224d4e5d5482e, // 0.82372, 0.567 + 0x3fea63091b02fae2, 0x3fe21a799933eb58, // 0.82459, 0.56573 + 0x3fea6a230637623b, 0x3fe2101b81e0da78, // 0.82546, 0.56447 + 0x3fea7138de9d60f5, 0x3fe205baa17560d6, // 0.82632, 0.5632 + 0x3fea784aa31d3f55, 0x3fe1fb56f98b37b8, // 0.82718, 0.56193 + 0x3fea7f58529fe69d, 0x3fe1f0f08bbc861b, // 0.82805, 0.56066 + 0x3fea8661ec0ee133, 0x3fe1e68759a3e074, // 0.8289, 0.55939 + 0x3fea8d676e545ad2, 0x3fe1dc1b64dc4872, // 0.82976, 0.55812 + 0x3fea9468d85b20ae, 0x3fe1d1acaf012cc2, // 0.83062, 0.55685 + 0x3fea9b66290ea1a3, 0x3fe1c73b39ae68c8, // 0.83147, 0.55557 + 0x3feaa25f5f5aee60, 0x3fe1bcc706804467, // 0.83232, 0.55429 + 0x3feaa9547a2cb98e, 0x3fe1b250171373be, // 0.83317, 0.55302 + 0x3feab045787157ff, 0x3fe1a7d66d0516e6, // 0.83402, 0.55174 + 0x3feab7325916c0d4, 0x3fe19d5a09f2b9b8, // 0.83486, 0.55046 + 0x3feabe1b1b0b8dac, 0x3fe192daef7a5386, // 0.83571, 0.54918 + 0x3feac4ffbd3efac8, 0x3fe188591f3a46e5, // 0.83655, 0.54789 + 0x3feacbe03ea0e73b, 0x3fe17dd49ad16161, // 0.83739, 0.54661 + 0x3fead2bc9e21d511, 0x3fe1734d63dedb49, // 0.83822, 0.54532 + 0x3fead994dab2e979, 0x3fe168c37c025764, // 0.83906, 0.54404 + 0x3feae068f345ecef, 0x3fe15e36e4dbe2bc, // 0.83989, 0.54275 + 0x3feae738e6cd4b67, 0x3fe153a7a00bf453, // 0.84073, 0.54146 + 0x3feaee04b43c1474, 0x3fe14915af336ceb, // 0.84155, 0.54017 + 0x3feaf4cc5a85fb73, 0x3fe13e8113f396c1, // 0.84238, 0.53888 + 0x3feafb8fd89f57b6, 0x3fe133e9cfee254e, // 0.84321, 0.53759 + 0x3feb024f2d7d24a9, 0x3fe1294fe4c5350a, // 0.84403, 0.53629 + 0x3feb090a58150200, 0x3fe11eb3541b4b22, // 0.84485, 0.535 + 0x3feb0fc1575d33db, 0x3fe114141f935545, // 0.84567, 0.5337 + 0x3feb16742a4ca2f5, 0x3fe1097248d0a956, // 0.84649, 0.5324 + 0x3feb1d22cfdadcc6, 0x3fe0fecdd1770537, // 0.84731, 0.5311 + 0x3feb23cd470013b4, 0x3fe0f426bb2a8e7d, // 0.84812, 0.5298 + 0x3feb2a738eb51f33, 0x3fe0e97d078fd23b, // 0.84893, 0.5285 + 0x3feb3115a5f37bf4, 0x3fe0ded0b84bc4b5, // 0.84974, 0.5272 + 0x3feb37b38bb54c09, 0x3fe0d421cf03c12b, // 0.85055, 0.5259 + 0x3feb3e4d3ef55712, 0x3fe0c9704d5d898f, // 0.85136, 0.52459 + 0x3feb44e2beaf0a61, 0x3fe0bebc34ff4646, // 0.85216, 0.52328 + 0x3feb4b7409de7925, 0x3fe0b405878f85ec, // 0.85296, 0.52198 + 0x3feb52011f805c92, 0x3fe0a94c46b53d0b, // 0.85376, 0.52067 + 0x3feb5889fe921405, 0x3fe09e907417c5e1, // 0.85456, 0.51936 + 0x3feb5f0ea611a532, 0x3fe093d2115ee018, // 0.85535, 0.51804 + 0x3feb658f14fdbc47, 0x3fe089112032b08c, // 0.85615, 0.51673 + 0x3feb6c0b4a55ac17, 0x3fe07e4da23bc102, // 0.85694, 0.51542 + 0x3feb728345196e3e, 0x3fe073879922ffed, // 0.85773, 0.5141 + 0x3feb78f70449a34b, 0x3fe068bf0691c028, // 0.85852, 0.51279 + 0x3feb7f6686e792ea, 0x3fe05df3ec31b8b6, // 0.8593, 0.51147 + 0x3feb85d1cbf52c02, 0x3fe053264bad0483, // 0.86009, 0.51015 + 0x3feb8c38d27504e9, 0x3fe0485626ae221a, // 0.86087, 0.50883 + 0x3feb929b996a5b7f, 0x3fe03d837edff370, // 0.86165, 0.50751 + 0x3feb98fa1fd9155e, 0x3fe032ae55edbd95, // 0.86242, 0.50619 + 0x3feb9f5464c5bffc, 0x3fe027d6ad83287e, // 0.8632, 0.50486 + 0x3feba5aa673590d2, 0x3fe01cfc874c3eb7, // 0.86397, 0.50354 + 0x3febabfc262e6586, 0x3fe0121fe4f56d2c, // 0.86474, 0.50221 + 0x3febb249a0b6c40d, 0x3fe00740c82b82e0, // 0.86551, 0.50089 + 0x3febb892d5d5dad5, 0x3fdff8be6537615e, // 0.86628, 0.49956 + 0x3febbed7c49380ea, 0x3fdfe2f64be7120f, // 0.86705, 0.49823 + 0x3febc5186bf8361d, 0x3fdfcd2947c1ff57, // 0.86781, 0.4969 + 0x3febcb54cb0d2327, 0x3fdfb7575c24d2de, // 0.86857, 0.49557 + 0x3febd18ce0dc19d6, 0x3fdfa1808c6cf7e0, // 0.86933, 0.49423 + 0x3febd7c0ac6f952a, 0x3fdf8ba4dbf89aba, // 0.87009, 0.4929 + 0x3febddf02cd2b983, 0x3fdf75c44e26a852, // 0.87084, 0.49156 + 0x3febe41b611154c1, 0x3fdf5fdee656cda3, // 0.8716, 0.49023 + 0x3febea424837de6d, 0x3fdf49f4a7e97729, // 0.87235, 0.48889 + 0x3febf064e15377dd, 0x3fdf3405963fd068, // 0.87309, 0.48755 + 0x3febf6832b71ec5b, 0x3fdf1e11b4bbc35c, // 0.87384, 0.48621 + 0x3febfc9d25a1b147, 0x3fdf081906bff7fd, // 0.87459, 0.48487 + 0x3fec02b2cef1e641, 0x3fdef21b8fafd3b5, // 0.87533, 0.48353 + 0x3fec08c426725549, 0x3fdedc1952ef78d5, // 0.87607, 0.48218 + 0x3fec0ed12b3372e9, 0x3fdec61253e3c61b, // 0.87681, 0.48084 + 0x3fec14d9dc465e58, 0x3fdeb00695f25620, // 0.87755, 0.47949 + 0x3fec1ade38bce19b, 0x3fde99f61c817eda, // 0.87828, 0.47815 + 0x3fec20de3fa971b0, 0x3fde83e0eaf85113, // 0.87901, 0.4768 + 0x3fec26d9f01f2eaf, 0x3fde6dc704be97e2, // 0.87974, 0.47545 + 0x3fec2cd14931e3f1, 0x3fde57a86d3cd824, // 0.88047, 0.4741 + 0x3fec32c449f60831, 0x3fde418527dc4ffa, // 0.8812, 0.47275 + 0x3fec38b2f180bdb1, 0x3fde2b5d3806f63b, // 0.88192, 0.4714 + 0x3fec3e9d3ee7d262, 0x3fde1530a12779f4, // 0.88264, 0.47004 + 0x3fec44833141c004, 0x3fddfeff66a941de, // 0.88336, 0.46869 + 0x3fec4a64c7a5ac4c, 0x3fdde8c98bf86bd6, // 0.88408, 0.46733 + 0x3fec5042012b6907, 0x3fddd28f1481cc58, // 0.8848, 0.46598 + 0x3fec561adceb743e, 0x3fddbc5003b2edf8, // 0.88551, 0.46462 + 0x3fec5bef59fef85a, 0x3fdda60c5cfa10d8, // 0.88622, 0.46326 + 0x3fec61bf777fcc48, 0x3fdd8fc423c62a25, // 0.88693, 0.4619 + 0x3fec678b3488739b, 0x3fdd79775b86e389, // 0.88764, 0.46054 + 0x3fec6d5290341eb2, 0x3fdd632607ac9aa9, // 0.88835, 0.45918 + 0x3fec7315899eaad7, 0x3fdd4cd02ba8609c, // 0.88905, 0.45781 + 0x3fec78d41fe4a267, 0x3fdd3675caebf962, // 0.88975, 0.45645 + 0x3fec7e8e52233cf3, 0x3fdd2016e8e9db5b, // 0.89045, 0.45508 + 0x3fec84441f785f61, 0x3fdd09b389152ec1, // 0.89115, 0.45372 + 0x3fec89f587029c13, 0x3fdcf34baee1cd21, // 0.89184, 0.45235 + 0x3fec8fa287e13305, 0x3fdcdcdf5dc440ce, // 0.89253, 0.45098 + 0x3fec954b213411f5, 0x3fdcc66e9931c45d, // 0.89322, 0.44961 + 0x3fec9aef521bd480, 0x3fdcaff964a0421d, // 0.89391, 0.44824 + 0x3feca08f19b9c449, 0x3fdc997fc3865388, // 0.8946, 0.44687 + 0x3feca62a772fd919, 0x3fdc8301b95b40c2, // 0.89528, 0.4455 + 0x3fecabc169a0b901, 0x3fdc6c7f4997000a, // 0.89597, 0.44412 + 0x3fecb153f02fb87d, 0x3fdc55f877b23537, // 0.89665, 0.44275 + 0x3fecb6e20a00da99, 0x3fdc3f6d47263129, // 0.89732, 0.44137 + 0x3fecbc6bb638d10b, 0x3fdc28ddbb6cf145, // 0.898, 0.43999 + 0x3fecc1f0f3fcfc5c, 0x3fdc1249d8011ee7, // 0.89867, 0.43862 + 0x3fecc771c2736c09, 0x3fdbfbb1a05e0edc, // 0.89935, 0.43724 + 0x3fecccee20c2de9f, 0x3fdbe51517ffc0d9, // 0.90002, 0.43586 + 0x3fecd2660e12c1e6, 0x3fdbce744262deee, // 0.90068, 0.43448 + 0x3fecd7d9898b32f6, 0x3fdbb7cf2304bd01, // 0.90135, 0.43309 + 0x3fecdd489254fe65, 0x3fdba125bd63583e, // 0.90201, 0.43171 + 0x3fece2b32799a060, 0x3fdb8a7814fd5693, // 0.90267, 0.43033 + 0x3fece819488344ce, 0x3fdb73c62d520624, // 0.90333, 0.42894 + 0x3feced7af43cc773, 0x3fdb5d1009e15cc0, // 0.90399, 0.42756 + 0x3fecf2d829f1b40e, 0x3fdb4655ae2bf757, // 0.90464, 0.42617 + 0x3fecf830e8ce467b, 0x3fdb2f971db31972, // 0.9053, 0.42478 + 0x3fecfd852fff6ad4, 0x3fdb18d45bf8aca6, // 0.90595, 0.42339 + 0x3fed02d4feb2bd92, 0x3fdb020d6c7f4009, // 0.9066, 0.422 + 0x3fed082054168bac, 0x3fdaeb4252ca07ab, // 0.90724, 0.42061 + 0x3fed0d672f59d2b9, 0x3fdad473125cdc08, // 0.90789, 0.41922 + 0x3fed12a98fac410c, 0x3fdabd9faebc3980, // 0.90853, 0.41782 + 0x3fed17e7743e35dc, 0x3fdaa6c82b6d3fc9, // 0.90917, 0.41643 + 0x3fed1d20dc40c15c, 0x3fda8fec8bf5b166, // 0.90981, 0.41503 + 0x3fed2255c6e5a4e1, 0x3fda790cd3dbf31a, // 0.91044, 0.41364 + 0x3fed2786335f52fc, 0x3fda622906a70b63, // 0.91107, 0.41224 + 0x3fed2cb220e0ef9f, 0x3fda4b4127dea1e4, // 0.91171, 0.41084 + 0x3fed31d98e9e503a, 0x3fda34553b0afee5, // 0.91234, 0.40944 + 0x3fed36fc7bcbfbdc, 0x3fda1d6543b50ac0, // 0.91296, 0.40804 + 0x3fed3c1ae79f2b4e, 0x3fda067145664d57, // 0.91359, 0.40664 + 0x3fed4134d14dc93a, 0x3fd9ef7943a8ed8a, // 0.91421, 0.40524 + 0x3fed464a380e7242, 0x3fd9d87d4207b0ab, // 0.91483, 0.40384 + 0x3fed4b5b1b187524, 0x3fd9c17d440df9f2, // 0.91545, 0.40243 + 0x3fed506779a3d2d9, 0x3fd9aa794d47c9ee, // 0.91606, 0.40103 + 0x3fed556f52e93eb1, 0x3fd993716141bdfe, // 0.91668, 0.39962 + 0x3fed5a72a6221e73, 0x3fd97c6583890fc2, // 0.91729, 0.39822 + 0x3fed5f7172888a7f, 0x3fd96555b7ab948f, // 0.9179, 0.39681 + 0x3fed646bb7574de5, 0x3fd94e420137bce3, // 0.91851, 0.3954 + 0x3fed696173c9e68b, 0x3fd9372a63bc93d7, // 0.91911, 0.39399 + 0x3fed6e52a71c8547, 0x3fd9200ee2c9be97, // 0.91972, 0.39258 + 0x3fed733f508c0dff, 0x3fd908ef81ef7bd1, // 0.92032, 0.39117 + 0x3fed78276f5617c6, 0x3fd8f1cc44bea329, // 0.92092, 0.38976 + 0x3fed7d0b02b8ecf9, 0x3fd8daa52ec8a4af, // 0.92151, 0.38835 + 0x3fed81ea09f38b63, 0x3fd8c37a439f884f, // 0.92211, 0.38693 + 0x3fed86c48445a450, 0x3fd8ac4b86d5ed44, // 0.9227, 0.38552 + 0x3fed8b9a70ef9cb4, 0x3fd89518fbff098e, // 0.92329, 0.3841 + 0x3fed906bcf328d46, 0x3fd87de2a6aea963, // 0.92388, 0.38268 + 0x3fed95389e50429b, 0x3fd866a88a792ea0, // 0.92447, 0.38127 + 0x3fed9a00dd8b3d46, 0x3fd84f6aaaf3903f, // 0.92505, 0.37985 + 0x3fed9ec48c26b1f3, 0x3fd838290bb359c8, // 0.92563, 0.37843 + 0x3feda383a9668988, 0x3fd820e3b04eaac4, // 0.92621, 0.37701 + 0x3feda83e348f613b, 0x3fd8099a9c5c362d, // 0.92679, 0.37559 + 0x3fedacf42ce68ab9, 0x3fd7f24dd37341e3, // 0.92736, 0.37416 + 0x3fedb1a591b20c38, 0x3fd7dafd592ba621, // 0.92794, 0.37274 + 0x3fedb6526238a09b, 0x3fd7c3a9311dcce7, // 0.92851, 0.37132 + 0x3fedbafa9dc1b78d, 0x3fd7ac515ee2b172, // 0.92907, 0.36989 + 0x3fedbf9e4395759a, 0x3fd794f5e613dfae, // 0.92964, 0.36847 + 0x3fedc43d52fcb453, 0x3fd77d96ca4b73a6, // 0.93021, 0.36704 + 0x3fedc8d7cb410260, 0x3fd766340f2418f6, // 0.93077, 0.36561 + 0x3fedcd6dabaca3a5, 0x3fd74ecdb8390a3e, // 0.93133, 0.36418 + 0x3fedd1fef38a915a, 0x3fd73763c9261092, // 0.93188, 0.36276 + 0x3fedd68ba2267a25, 0x3fd71ff6458782ec, // 0.93244, 0.36133 + 0x3feddb13b6ccc23d, 0x3fd7088530fa459e, // 0.93299, 0.3599 + 0x3feddf9730ca837b, 0x3fd6f1108f1bc9c5, // 0.93354, 0.35846 + 0x3fede4160f6d8d81, 0x3fd6d998638a0cb5, // 0.93409, 0.35703 + 0x3fede890520465ce, 0x3fd6c21cb1e39771, // 0.93464, 0.3556 + 0x3feded05f7de47da, 0x3fd6aa9d7dc77e16, // 0.93518, 0.35416 + 0x3fedf177004b2534, 0x3fd6931acad55f51, // 0.93573, 0.35273 + 0x3fedf5e36a9ba59c, 0x3fd67b949cad63ca, // 0.93627, 0.35129 + 0x3fedfa4b3621271d, 0x3fd6640af6f03d9e, // 0.9368, 0.34986 + 0x3fedfeae622dbe2b, 0x3fd64c7ddd3f27c6, // 0.93734, 0.34842 + 0x3fee030cee1435b8, 0x3fd634ed533be58e, // 0.93787, 0.34698 + 0x3fee0766d9280f54, 0x3fd61d595c88c203, // 0.9384, 0.34554 + 0x3fee0bbc22bd8349, 0x3fd605c1fcc88f63, // 0.93893, 0.3441 + 0x3fee100cca2980ac, 0x3fd5ee27379ea693, // 0.93946, 0.34266 + 0x3fee1458cec1ad83, 0x3fd5d68910aee686, // 0.93998, 0.34122 + 0x3fee18a02fdc66d9, 0x3fd5bee78b9db3b6, // 0.94051, 0.33978 + 0x3fee1ce2ecd0c0d8, 0x3fd5a742ac0ff78d, // 0.94103, 0.33833 + 0x3fee212104f686e5, 0x3fd58f9a75ab1fdd, // 0.94154, 0.33689 + 0x3fee255a77a63bb8, 0x3fd577eeec151e47, // 0.94206, 0.33545 + 0x3fee298f4439197a, 0x3fd5604012f467b4, // 0.94257, 0.334 + 0x3fee2dbf6a0911d9, 0x3fd5488dedeff3be, // 0.94308, 0.33255 + 0x3fee31eae870ce25, 0x3fd530d880af3c24, // 0.94359, 0.33111 + 0x3fee3611becbaf69, 0x3fd5191fceda3c35, // 0.9441, 0.32966 + 0x3fee3a33ec75ce85, 0x3fd50163dc197047, // 0.9446, 0.32821 + 0x3fee3e5170cbfc46, 0x3fd4e9a4ac15d520, // 0.94511, 0.32676 + 0x3fee426a4b2bc17e, 0x3fd4d1e24278e76a, // 0.94561, 0.32531 + 0x3fee467e7af35f23, 0x3fd4ba1ca2eca31c, // 0.94611, 0.32386 + 0x3fee4a8dff81ce5e, 0x3fd4a253d11b82f3, // 0.9466, 0.32241 + 0x3fee4e98d836c0af, 0x3fd48a87d0b07fd7, // 0.94709, 0.32096 + 0x3fee529f04729ffc, 0x3fd472b8a5571054, // 0.94759, 0.3195 + 0x3fee56a083968eb1, 0x3fd45ae652bb2800, // 0.94807, 0.31805 + 0x3fee5a9d550467d3, 0x3fd44310dc8936f0, // 0.94856, 0.31659 + 0x3fee5e95781ebf1c, 0x3fd42b38466e2928, // 0.94905, 0.31514 + 0x3fee6288ec48e112, 0x3fd4135c94176602, // 0.94953, 0.31368 + 0x3fee6677b0e6d31e, 0x3fd3fb7dc932cfa4, // 0.95001, 0.31222 + 0x3fee6a61c55d53a7, 0x3fd3e39be96ec271, // 0.95049, 0.31077 + 0x3fee6e472911da27, 0x3fd3cbb6f87a146e, // 0.95096, 0.30931 + 0x3fee7227db6a9744, 0x3fd3b3cefa0414b7, // 0.95144, 0.30785 + 0x3fee7603dbce74e9, 0x3fd39be3f1bc8aef, // 0.95191, 0.30639 + 0x3fee79db29a5165a, 0x3fd383f5e353b6aa, // 0.95238, 0.30493 + 0x3fee7dadc456d850, 0x3fd36c04d27a4edf, // 0.95284, 0.30347 + 0x3fee817bab4cd10d, 0x3fd35410c2e18152, // 0.95331, 0.30201 + 0x3fee8544ddf0d075, 0x3fd33c19b83af207, // 0.95377, 0.30054 + 0x3fee89095bad6025, 0x3fd3241fb638baaf, // 0.95423, 0.29908 + 0x3fee8cc923edc388, 0x3fd30c22c08d6a13, // 0.95469, 0.29762 + 0x3fee9084361df7f3, 0x3fd2f422daec0386, // 0.95514, 0.29615 + 0x3fee943a91aab4b4, 0x3fd2dc200907fe51, // 0.95559, 0.29469 + 0x3fee97ec36016b30, 0x3fd2c41a4e954520, // 0.95605, 0.29322 + 0x3fee9b99229046f8, 0x3fd2ac11af483572, // 0.95649, 0.29175 + 0x3fee9f4156c62dda, 0x3fd294062ed59f05, // 0.95694, 0.29028 + 0x3feea2e4d212c000, 0x3fd27bf7d0f2c346, // 0.95738, 0.28882 + 0x3feea68393e65800, 0x3fd263e6995554ba, // 0.95783, 0.28735 + 0x3feeaa1d9bb20af3, 0x3fd24bd28bb37672, // 0.95827, 0.28588 + 0x3feeadb2e8e7a88e, 0x3fd233bbabc3bb72, // 0.9587, 0.28441 + 0x3feeb1437af9bb34, 0x3fd21ba1fd3d2623, // 0.95914, 0.28294 + 0x3feeb4cf515b8811, 0x3fd2038583d727bd, // 0.95957, 0.28146 + 0x3feeb8566b810f2a, 0x3fd1eb6643499fbb, // 0.96, 0.27999 + 0x3feebbd8c8df0b74, 0x3fd1d3443f4cdb3d, // 0.96043, 0.27852 + 0x3feebf5668eaf2ef, 0x3fd1bb1f7b999480, // 0.96086, 0.27705 + 0x3feec2cf4b1af6b2, 0x3fd1a2f7fbe8f243, // 0.96128, 0.27557 + 0x3feec6436ee60309, 0x3fd18acdc3f4873a, // 0.9617, 0.2741 + 0x3feec9b2d3c3bf84, 0x3fd172a0d7765177, // 0.96212, 0.27262 + 0x3feecd1d792c8f10, 0x3fd15a713a28b9d9, // 0.96254, 0.27115 + 0x3feed0835e999009, 0x3fd1423eefc69378, // 0.96295, 0.26967 + 0x3feed3e483849c51, 0x3fd12a09fc0b1b12, // 0.96337, 0.26819 + 0x3feed740e7684963, 0x3fd111d262b1f677, // 0.96378, 0.26671 + 0x3feeda9889bfe86a, 0x3fd0f998277733f7, // 0.96418, 0.26523 + 0x3feeddeb6a078651, 0x3fd0e15b4e1749cd, // 0.96459, 0.26375 + 0x3feee13987bbebdc, 0x3fd0c91bda4f158d, // 0.96499, 0.26227 + 0x3feee482e25a9dbc, 0x3fd0b0d9cfdbdb90, // 0.96539, 0.26079 + 0x3feee7c77961dc9e, 0x3fd09895327b465e, // 0.96579, 0.25931 + 0x3feeeb074c50a544, 0x3fd0804e05eb661e, // 0.96619, 0.25783 + 0x3feeee425aa6b09a, 0x3fd068044deab002, // 0.96658, 0.25635 + 0x3feef178a3e473c2, 0x3fd04fb80e37fdae, // 0.96698, 0.25487 + 0x3feef4aa278b2032, 0x3fd037694a928cac, // 0.96737, 0.25338 + 0x3feef7d6e51ca3c0, 0x3fd01f1806b9fdd2, // 0.96775, 0.2519 + 0x3feefafedc1ba8b7, 0x3fd006c4466e54af, // 0.96814, 0.25041 + 0x3feefe220c0b95ec, 0x3fcfdcdc1adfedf8, // 0.96852, 0.24893 + 0x3fef014074708ed3, 0x3fcfac2abeff57ff, // 0.9689, 0.24744 + 0x3fef045a14cf738c, 0x3fcf7b7480bd3801, // 0.96928, 0.24596 + 0x3fef076eecade0fa, 0x3fcf4ab9679c9f5c, // 0.96966, 0.24447 + 0x3fef0a7efb9230d7, 0x3fcf19f97b215f1a, // 0.97003, 0.24298 + 0x3fef0d8a410379c5, 0x3fcee934c2d006c7, // 0.9704, 0.24149 + 0x3fef1090bc898f5f, 0x3fceb86b462de348, // 0.97077, 0.24 + 0x3fef13926dad024e, 0x3fce879d0cc0fdaf, // 0.97114, 0.23851 + 0x3fef168f53f7205d, 0x3fce56ca1e101a1b, // 0.9715, 0.23702 + 0x3fef19876ef1f486, 0x3fce25f281a2b684, // 0.97187, 0.23553 + 0x3fef1c7abe284708, 0x3fcdf5163f01099a, // 0.97223, 0.23404 + 0x3fef1f6941259d7a, 0x3fcdc4355db40195, // 0.97258, 0.23255 + 0x3fef2252f7763ada, 0x3fcd934fe5454311, // 0.97294, 0.23106 + 0x3fef2537e0a71f9f, 0x3fcd6265dd3f27e3, // 0.97329, 0.22957 + 0x3fef2817fc4609ce, 0x3fcd31774d2cbdee, // 0.97364, 0.22807 + 0x3fef2af349e17507, 0x3fcd00843c99c5f9, // 0.97399, 0.22658 + 0x3fef2dc9c9089a9d, 0x3fcccf8cb312b286, // 0.97434, 0.22508 + 0x3fef309b794b719f, 0x3fcc9e90b824a6a9, // 0.97468, 0.22359 + 0x3fef33685a3aaef0, 0x3fcc6d90535d74dc, // 0.97503, 0.22209 + 0x3fef36306b67c556, 0x3fcc3c8b8c4b9dd7, // 0.97536, 0.2206 + 0x3fef38f3ac64e589, 0x3fcc0b826a7e4f63, // 0.9757, 0.2191 + 0x3fef3bb21cc4fe47, 0x3fcbda74f5856330, // 0.97604, 0.2176 + 0x3fef3e6bbc1bbc65, 0x3fcba96334f15dad, // 0.97637, 0.21611 + 0x3fef412089fd8adc, 0x3fcb784d30536cda, // 0.9767, 0.21461 + 0x3fef43d085ff92dd, 0x3fcb4732ef3d6722, // 0.97703, 0.21311 + 0x3fef467bafb7bbe0, 0x3fcb16147941ca2a, // 0.97735, 0.21161 + 0x3fef492206bcabb4, 0x3fcae4f1d5f3b9ab, // 0.97768, 0.21011 + 0x3fef4bc38aa5c694, 0x3fcab3cb0ce6fe44, // 0.978, 0.20861 + 0x3fef4e603b0b2f2d, 0x3fca82a025b00451, // 0.97832, 0.20711 + 0x3fef50f81785c6b9, 0x3fca517127e3dabc, // 0.97863, 0.20561 + 0x3fef538b1faf2d07, 0x3fca203e1b1831da, // 0.97895, 0.20411 + 0x3fef56195321c090, 0x3fc9ef0706e35a35, // 0.97926, 0.20261 + 0x3fef58a2b1789e84, 0x3fc9bdcbf2dc4366, // 0.97957, 0.2011 + 0x3fef5b273a4fa2d9, 0x3fc98c8ce69a7aec, // 0.97988, 0.1996 + 0x3fef5da6ed43685d, 0x3fc95b49e9b62af9, // 0.98018, 0.1981 + 0x3fef6021c9f148c2, 0x3fc92a0303c8194f, // 0.98048, 0.19659 + 0x3fef6297cff75cb0, 0x3fc8f8b83c69a60a, // 0.98079, 0.19509 + 0x3fef6508fef47bd5, 0x3fc8c7699b34ca7e, // 0.98108, 0.19359 + 0x3fef677556883cee, 0x3fc8961727c41804, // 0.98138, 0.19208 + 0x3fef69dcd652f5de, 0x3fc864c0e9b2b6cf, // 0.98167, 0.19057 + 0x3fef6c3f7df5bbb7, 0x3fc83366e89c64c5, // 0.98196, 0.18907 + 0x3fef6e9d4d1262ca, 0x3fc802092c1d744b, // 0.98225, 0.18756 + 0x3fef70f6434b7eb7, 0x3fc7d0a7bbd2cb1b, // 0.98254, 0.18606 + 0x3fef734a60446279, 0x3fc79f429f59e11d, // 0.98282, 0.18455 + 0x3fef7599a3a12077, 0x3fc76dd9de50bf31, // 0.98311, 0.18304 + 0x3fef77e40d068a90, 0x3fc73c6d8055fe0a, // 0.98339, 0.18153 + 0x3fef7a299c1a322a, 0x3fc70afd8d08c4ff, // 0.98366, 0.18002 + 0x3fef7c6a50826840, 0x3fc6d98a0c08c8da, // 0.98394, 0.17851 + 0x3fef7ea629e63d6e, 0x3fc6a81304f64ab2, // 0.98421, 0.177 + 0x3fef80dd27ed8204, 0x3fc676987f7216b8, // 0.98448, 0.17549 + 0x3fef830f4a40c60c, 0x3fc6451a831d830d, // 0.98475, 0.17398 + 0x3fef853c9089595e, 0x3fc61399179a6e94, // 0.98501, 0.17247 + 0x3fef8764fa714ba9, 0x3fc5e214448b3fc6, // 0.98528, 0.17096 + 0x3fef898887a36c84, 0x3fc5b08c1192e381, // 0.98554, 0.16945 + 0x3fef8ba737cb4b78, 0x3fc57f008654cbde, // 0.9858, 0.16794 + 0x3fef8dc10a95380d, 0x3fc54d71aa74ef02, // 0.98605, 0.16643 + 0x3fef8fd5ffae41db, 0x3fc51bdf8597c5f2, // 0.98631, 0.16491 + 0x3fef91e616c43891, 0x3fc4ea4a1f624b61, // 0.98656, 0.1634 + 0x3fef93f14f85ac08, 0x3fc4b8b17f79fa88, // 0.98681, 0.16189 + 0x3fef95f7a9a1ec47, 0x3fc48715ad84cdf5, // 0.98706, 0.16037 + 0x3fef97f924c9099b, 0x3fc45576b1293e5a, // 0.9873, 0.15886 + 0x3fef99f5c0abd496, 0x3fc423d4920e4166, // 0.98754, 0.15734 + 0x3fef9bed7cfbde29, 0x3fc3f22f57db4893, // 0.98778, 0.15583 + 0x3fef9de0596b77a3, 0x3fc3c0870a383ff6, // 0.98802, 0.15431 + 0x3fef9fce55adb2c8, 0x3fc38edbb0cd8d14, // 0.98826, 0.1528 + 0x3fefa1b7717661d5, 0x3fc35d2d53440db2, // 0.98849, 0.15128 + 0x3fefa39bac7a1791, 0x3fc32b7bf94516a7, // 0.98872, 0.14976 + 0x3fefa57b066e2754, 0x3fc2f9c7aa7a72af, // 0.98895, 0.14825 + 0x3fefa7557f08a517, 0x3fc2c8106e8e613a, // 0.98918, 0.14673 + 0x3fefa92b1600657c, 0x3fc296564d2b953e, // 0.9894, 0.14521 + 0x3fefaafbcb0cfddc, 0x3fc264994dfd340a, // 0.98962, 0.1437 + 0x3fefacc79de6c44f, 0x3fc232d978aed413, // 0.98984, 0.14218 + 0x3fefae8e8e46cfbb, 0x3fc20116d4ec7bce, // 0.99006, 0.14066 + 0x3fefb0509be6f7db, 0x3fc1cf516a62a077, // 0.99027, 0.13914 + 0x3fefb20dc681d54d, 0x3fc19d8940be24e7, // 0.99049, 0.13762 + 0x3fefb3c60dd2c199, 0x3fc16bbe5fac5865, // 0.9907, 0.1361 + 0x3fefb5797195d741, 0x3fc139f0cedaf576, // 0.9909, 0.13458 + 0x3fefb727f187f1c7, 0x3fc1082095f820b0, // 0.99111, 0.13306 + 0x3fefb8d18d66adb7, 0x3fc0d64dbcb26786, // 0.99131, 0.13154 + 0x3fefba7644f068b5, 0x3fc0a4784ab8bf1d, // 0.99151, 0.13002 + 0x3fefbc1617e44186, 0x3fc072a047ba831d, // 0.99171, 0.1285 + 0x3fefbdb106021816, 0x3fc040c5bb67747e, // 0.99191, 0.12698 + 0x3fefbf470f0a8d88, 0x3fc00ee8ad6fb85b, // 0.9921, 0.12545 + 0x3fefc0d832bf043a, 0x3fbfba124b07ad85, // 0.99229, 0.12393 + 0x3fefc26470e19fd3, 0x3fbf564e56a9730e, // 0.99248, 0.12241 + 0x3fefc3ebc935454c, 0x3fbef2858d27561b, // 0.99267, 0.12089 + 0x3fefc56e3b7d9af6, 0x3fbe8eb7fde4aa3e, // 0.99285, 0.11937 + 0x3fefc6ebc77f0887, 0x3fbe2ae5b8457f77, // 0.99303, 0.11784 + 0x3fefc8646cfeb721, 0x3fbdc70ecbae9fc8, // 0.99321, 0.11632 + 0x3fefc9d82bc2915e, 0x3fbd633347858ce4, // 0.99339, 0.11479 + 0x3fefcb4703914354, 0x3fbcff533b307dc1, // 0.99356, 0.11327 + 0x3fefccb0f4323aa3, 0x3fbc9b6eb6165c42, // 0.99374, 0.11175 + 0x3fefce15fd6da67b, 0x3fbc3785c79ec2d5, // 0.99391, 0.11022 + 0x3fefcf761f0c77a3, 0x3fbbd3987f31fa0e, // 0.99407, 0.1087 + 0x3fefd0d158d86087, 0x3fbb6fa6ec38f64c, // 0.99424, 0.10717 + 0x3fefd227aa9bd53b, 0x3fbb0bb11e1d5559, // 0.9944, 0.10565 + 0x3fefd37914220b84, 0x3fbaa7b724495c04, // 0.99456, 0.10412 + 0x3fefd4c59536fae4, 0x3fba43b90e27f3c4, // 0.99472, 0.1026 + 0x3fefd60d2da75c9e, 0x3fb9dfb6eb24a85c, // 0.99488, 0.10107 + 0x3fefd74fdd40abbf, 0x3fb97bb0caaba56f, // 0.99503, 0.099544 + 0x3fefd88da3d12526, 0x3fb917a6bc29b42c, // 0.99518, 0.098017 + 0x3fefd9c68127c78c, 0x3fb8b398cf0c38e0, // 0.99533, 0.09649 + 0x3fefdafa7514538c, 0x3fb84f8712c130a0, // 0.99548, 0.094963 + 0x3fefdc297f674ba9, 0x3fb7eb7196b72ee4, // 0.99563, 0.093436 + 0x3fefdd539ff1f456, 0x3fb787586a5d5b21, // 0.99577, 0.091909 + 0x3fefde78d68653fd, 0x3fb7233b9d236e71, // 0.99591, 0.090381 + 0x3fefdf9922f73307, 0x3fb6bf1b3e79b129, // 0.99604, 0.088854 + 0x3fefe0b485181be3, 0x3fb65af75dd0f87b, // 0.99618, 0.087326 + 0x3fefe1cafcbd5b09, 0x3fb5f6d00a9aa419, // 0.99631, 0.085797 + 0x3fefe2dc89bbff08, 0x3fb592a554489bc8, // 0.99644, 0.084269 + 0x3fefe3e92be9d886, 0x3fb52e774a4d4d0a, // 0.99657, 0.08274 + 0x3fefe4f0e31d7a4a, 0x3fb4ca45fc1ba8b6, // 0.9967, 0.081211 + 0x3fefe5f3af2e3940, 0x3fb4661179272096, // 0.99682, 0.079682 + 0x3fefe6f18ff42c84, 0x3fb401d9d0e3a507, // 0.99694, 0.078153 + 0x3fefe7ea85482d60, 0x3fb39d9f12c5a299, // 0.99706, 0.076624 + 0x3fefe8de8f03d75c, 0x3fb339614e41ffa5, // 0.99718, 0.075094 + 0x3fefe9cdad01883a, 0x3fb2d52092ce19f6, // 0.99729, 0.073565 + 0x3fefeab7df1c6005, 0x3fb270dcefdfc45b, // 0.9974, 0.072035 + 0x3fefeb9d2530410f, 0x3fb20c9674ed444c, // 0.99751, 0.070505 + 0x3fefec7d7f19cffc, 0x3fb1a84d316d4f8a, // 0.99762, 0.068974 + 0x3fefed58ecb673c4, 0x3fb1440134d709b2, // 0.99772, 0.067444 + 0x3fefee2f6de455ba, 0x3fb0dfb28ea201e6, // 0.99783, 0.065913 + 0x3fefef0102826191, 0x3fb07b614e463064, // 0.99793, 0.064383 + 0x3fefefcdaa704562, 0x3fb0170d833bf421, // 0.99802, 0.062852 + 0x3feff095658e71ad, 0x3faf656e79f820e0, // 0.99812, 0.061321 + 0x3feff15833be1965, 0x3fae9cbd15ff5527, // 0.99821, 0.05979 + 0x3feff21614e131ed, 0x3fadd406f9808ec8, // 0.9983, 0.058258 + 0x3feff2cf08da7321, 0x3fad0b4c436f91d0, // 0.99839, 0.056727 + 0x3feff3830f8d575c, 0x3fac428d12c0d7e3, // 0.99848, 0.055195 + 0x3feff43228de1b77, 0x3fab79c986698b78, // 0.99856, 0.053664 + 0x3feff4dc54b1bed3, 0x3faab101bd5f8317, // 0.99864, 0.052132 + 0x3feff58192ee0358, 0x3fa9e835d6993c87, // 0.99872, 0.0506 + 0x3feff621e3796d7e, 0x3fa91f65f10dd814, // 0.9988, 0.049068 + 0x3feff6bd463b444d, 0x3fa856922bb513c1, // 0.99887, 0.047535 + 0x3feff753bb1b9164, 0x3fa78dbaa5874685, // 0.99894, 0.046003 + 0x3feff7e5420320f9, 0x3fa6c4df7d7d5b84, // 0.99901, 0.044471 + 0x3feff871dadb81df, 0x3fa5fc00d290cd43, // 0.99908, 0.042938 + 0x3feff8f9858f058b, 0x3fa5331ec3bba0eb, // 0.99914, 0.041406 + 0x3feff97c4208c014, 0x3fa46a396ff86179, // 0.9992, 0.039873 + 0x3feff9fa10348837, 0x3fa3a150f6421afc, // 0.99926, 0.03834 + 0x3feffa72effef75d, 0x3fa2d865759455cd, // 0.99932, 0.036807 + 0x3feffae6e1556998, 0x3fa20f770ceb11c6, // 0.99938, 0.035274 + 0x3feffb55e425fdae, 0x3fa14685db42c17e, // 0.99943, 0.033741 + 0x3feffbbff85f9515, 0x3fa07d91ff984580, // 0.99948, 0.032208 + 0x3feffc251df1d3f8, 0x3f9f693731d1cf01, // 0.99953, 0.030675 + 0x3feffc8554cd213a, 0x3f9dd7458c64ab39, // 0.99958, 0.029142 + 0x3feffce09ce2a679, 0x3f9c454f4ce53b1c, // 0.99962, 0.027608 + 0x3feffd36f624500c, 0x3f9ab354b1504fca, // 0.99966, 0.026075 + 0x3feffd886084cd0d, 0x3f992155f7a3667e, // 0.9997, 0.024541 + 0x3feffdd4dbf78f52, 0x3f978f535ddc9f03, // 0.99974, 0.023008 + 0x3feffe1c6870cb77, 0x3f95fd4d21fab226, // 0.99977, 0.021474 + 0x3feffe5f05e578db, 0x3f946b4381fce81c, // 0.9998, 0.01994 + 0x3feffe9cb44b51a1, 0x3f92d936bbe30efd, // 0.99983, 0.018407 + 0x3feffed57398d2b7, 0x3f9147270dad7132, // 0.99986, 0.016873 + 0x3fefff0943c53bd1, 0x3f8f6a296ab997ca, // 0.99988, 0.015339 + 0x3fefff3824c88f6f, 0x3f8c45ffe1e48ad9, // 0.9999, 0.013805 + 0x3fefff62169b92db, 0x3f8921d1fcdec784, // 0.99992, 0.012272 + 0x3fefff871937ce2f, 0x3f85fda037ac05e0, // 0.99994, 0.010738 + 0x3fefffa72c978c4f, 0x3f82d96b0e509703, // 0.99996, 0.0092038 + 0x3fefffc250b5daef, 0x3f7f6a65f9a2a3c5, // 0.99997, 0.0076698 + 0x3fefffd8858e8a92, 0x3f7921f0fe670071, // 0.99998, 0.0061359 + 0x3fefffe9cb1e2e8d, 0x3f72d97822f996bc, // 0.99999, 0.0046019 + 0x3feffff621621d02, 0x3f6921f8becca4ba, // 1, 0.003068 + 0x3feffffd88586ee6, 0x3f5921faaee6472d, // 1, 0.001534 + 0x3ff0000000000000, 0x0000000000000000, // 1, 0 + 0x3feffffd88586ee6, 0xbf5921faaee6472d, // 1, -0.001534 + 0x3feffff621621d02, 0xbf6921f8becca4ba, // 1, -0.003068 + 0x3fefffe9cb1e2e8d, 0xbf72d97822f996bc, // 0.99999,-0.0046019 + 0x3fefffd8858e8a92, 0xbf7921f0fe670071, // 0.99998,-0.0061359 + 0x3fefffc250b5daef, 0xbf7f6a65f9a2a3c5, // 0.99997,-0.0076698 + 0x3fefffa72c978c4f, 0xbf82d96b0e509703, // 0.99996,-0.0092038 + 0x3fefff871937ce2f, 0xbf85fda037ac05e0, // 0.99994, -0.010738 + 0x3fefff62169b92db, 0xbf8921d1fcdec784, // 0.99992, -0.012272 + 0x3fefff3824c88f6f, 0xbf8c45ffe1e48ad9, // 0.9999, -0.013805 + 0x3fefff0943c53bd1, 0xbf8f6a296ab997ca, // 0.99988, -0.015339 + 0x3feffed57398d2b7, 0xbf9147270dad7132, // 0.99986, -0.016873 + 0x3feffe9cb44b51a1, 0xbf92d936bbe30efd, // 0.99983, -0.018407 + 0x3feffe5f05e578db, 0xbf946b4381fce81c, // 0.9998, -0.01994 + 0x3feffe1c6870cb77, 0xbf95fd4d21fab226, // 0.99977, -0.021474 + 0x3feffdd4dbf78f52, 0xbf978f535ddc9f03, // 0.99974, -0.023008 + 0x3feffd886084cd0d, 0xbf992155f7a3667e, // 0.9997, -0.024541 + 0x3feffd36f624500c, 0xbf9ab354b1504fca, // 0.99966, -0.026075 + 0x3feffce09ce2a679, 0xbf9c454f4ce53b1c, // 0.99962, -0.027608 + 0x3feffc8554cd213a, 0xbf9dd7458c64ab39, // 0.99958, -0.029142 + 0x3feffc251df1d3f8, 0xbf9f693731d1cf01, // 0.99953, -0.030675 + 0x3feffbbff85f9515, 0xbfa07d91ff984580, // 0.99948, -0.032208 + 0x3feffb55e425fdae, 0xbfa14685db42c17e, // 0.99943, -0.033741 + 0x3feffae6e1556998, 0xbfa20f770ceb11c6, // 0.99938, -0.035274 + 0x3feffa72effef75d, 0xbfa2d865759455cd, // 0.99932, -0.036807 + 0x3feff9fa10348837, 0xbfa3a150f6421afc, // 0.99926, -0.03834 + 0x3feff97c4208c014, 0xbfa46a396ff86179, // 0.9992, -0.039873 + 0x3feff8f9858f058b, 0xbfa5331ec3bba0eb, // 0.99914, -0.041406 + 0x3feff871dadb81df, 0xbfa5fc00d290cd43, // 0.99908, -0.042938 + 0x3feff7e5420320f9, 0xbfa6c4df7d7d5b84, // 0.99901, -0.044471 + 0x3feff753bb1b9164, 0xbfa78dbaa5874685, // 0.99894, -0.046003 + 0x3feff6bd463b444d, 0xbfa856922bb513c1, // 0.99887, -0.047535 + 0x3feff621e3796d7e, 0xbfa91f65f10dd814, // 0.9988, -0.049068 + 0x3feff58192ee0358, 0xbfa9e835d6993c87, // 0.99872, -0.0506 + 0x3feff4dc54b1bed3, 0xbfaab101bd5f8317, // 0.99864, -0.052132 + 0x3feff43228de1b77, 0xbfab79c986698b78, // 0.99856, -0.053664 + 0x3feff3830f8d575c, 0xbfac428d12c0d7e3, // 0.99848, -0.055195 + 0x3feff2cf08da7321, 0xbfad0b4c436f91d0, // 0.99839, -0.056727 + 0x3feff21614e131ed, 0xbfadd406f9808ec8, // 0.9983, -0.058258 + 0x3feff15833be1965, 0xbfae9cbd15ff5527, // 0.99821, -0.05979 + 0x3feff095658e71ad, 0xbfaf656e79f820e0, // 0.99812, -0.061321 + 0x3fefefcdaa704562, 0xbfb0170d833bf421, // 0.99802, -0.062852 + 0x3fefef0102826191, 0xbfb07b614e463064, // 0.99793, -0.064383 + 0x3fefee2f6de455ba, 0xbfb0dfb28ea201e6, // 0.99783, -0.065913 + 0x3fefed58ecb673c4, 0xbfb1440134d709b2, // 0.99772, -0.067444 + 0x3fefec7d7f19cffc, 0xbfb1a84d316d4f8a, // 0.99762, -0.068974 + 0x3fefeb9d2530410f, 0xbfb20c9674ed444c, // 0.99751, -0.070505 + 0x3fefeab7df1c6005, 0xbfb270dcefdfc45b, // 0.9974, -0.072035 + 0x3fefe9cdad01883a, 0xbfb2d52092ce19f6, // 0.99729, -0.073565 + 0x3fefe8de8f03d75c, 0xbfb339614e41ffa5, // 0.99718, -0.075094 + 0x3fefe7ea85482d60, 0xbfb39d9f12c5a299, // 0.99706, -0.076624 + 0x3fefe6f18ff42c84, 0xbfb401d9d0e3a507, // 0.99694, -0.078153 + 0x3fefe5f3af2e3940, 0xbfb4661179272096, // 0.99682, -0.079682 + 0x3fefe4f0e31d7a4a, 0xbfb4ca45fc1ba8b6, // 0.9967, -0.081211 + 0x3fefe3e92be9d886, 0xbfb52e774a4d4d0a, // 0.99657, -0.08274 + 0x3fefe2dc89bbff08, 0xbfb592a554489bc8, // 0.99644, -0.084269 + 0x3fefe1cafcbd5b09, 0xbfb5f6d00a9aa419, // 0.99631, -0.085797 + 0x3fefe0b485181be3, 0xbfb65af75dd0f87b, // 0.99618, -0.087326 + 0x3fefdf9922f73307, 0xbfb6bf1b3e79b129, // 0.99604, -0.088854 + 0x3fefde78d68653fd, 0xbfb7233b9d236e71, // 0.99591, -0.090381 + 0x3fefdd539ff1f456, 0xbfb787586a5d5b21, // 0.99577, -0.091909 + 0x3fefdc297f674ba9, 0xbfb7eb7196b72ee4, // 0.99563, -0.093436 + 0x3fefdafa7514538c, 0xbfb84f8712c130a0, // 0.99548, -0.094963 + 0x3fefd9c68127c78c, 0xbfb8b398cf0c38e0, // 0.99533, -0.09649 + 0x3fefd88da3d12526, 0xbfb917a6bc29b42c, // 0.99518, -0.098017 + 0x3fefd74fdd40abbf, 0xbfb97bb0caaba56f, // 0.99503, -0.099544 + 0x3fefd60d2da75c9e, 0xbfb9dfb6eb24a85c, // 0.99488, -0.10107 + 0x3fefd4c59536fae4, 0xbfba43b90e27f3c4, // 0.99472, -0.1026 + 0x3fefd37914220b84, 0xbfbaa7b724495c04, // 0.99456, -0.10412 + 0x3fefd227aa9bd53b, 0xbfbb0bb11e1d5559, // 0.9944, -0.10565 + 0x3fefd0d158d86087, 0xbfbb6fa6ec38f64c, // 0.99424, -0.10717 + 0x3fefcf761f0c77a3, 0xbfbbd3987f31fa0e, // 0.99407, -0.1087 + 0x3fefce15fd6da67b, 0xbfbc3785c79ec2d5, // 0.99391, -0.11022 + 0x3fefccb0f4323aa3, 0xbfbc9b6eb6165c42, // 0.99374, -0.11175 + 0x3fefcb4703914354, 0xbfbcff533b307dc1, // 0.99356, -0.11327 + 0x3fefc9d82bc2915e, 0xbfbd633347858ce4, // 0.99339, -0.11479 + 0x3fefc8646cfeb721, 0xbfbdc70ecbae9fc8, // 0.99321, -0.11632 + 0x3fefc6ebc77f0887, 0xbfbe2ae5b8457f77, // 0.99303, -0.11784 + 0x3fefc56e3b7d9af6, 0xbfbe8eb7fde4aa3e, // 0.99285, -0.11937 + 0x3fefc3ebc935454c, 0xbfbef2858d27561b, // 0.99267, -0.12089 + 0x3fefc26470e19fd3, 0xbfbf564e56a9730e, // 0.99248, -0.12241 + 0x3fefc0d832bf043a, 0xbfbfba124b07ad85, // 0.99229, -0.12393 + 0x3fefbf470f0a8d88, 0xbfc00ee8ad6fb85b, // 0.9921, -0.12545 + 0x3fefbdb106021816, 0xbfc040c5bb67747e, // 0.99191, -0.12698 + 0x3fefbc1617e44186, 0xbfc072a047ba831d, // 0.99171, -0.1285 + 0x3fefba7644f068b5, 0xbfc0a4784ab8bf1d, // 0.99151, -0.13002 + 0x3fefb8d18d66adb7, 0xbfc0d64dbcb26786, // 0.99131, -0.13154 + 0x3fefb727f187f1c7, 0xbfc1082095f820b0, // 0.99111, -0.13306 + 0x3fefb5797195d741, 0xbfc139f0cedaf576, // 0.9909, -0.13458 + 0x3fefb3c60dd2c199, 0xbfc16bbe5fac5865, // 0.9907, -0.1361 + 0x3fefb20dc681d54d, 0xbfc19d8940be24e7, // 0.99049, -0.13762 + 0x3fefb0509be6f7db, 0xbfc1cf516a62a077, // 0.99027, -0.13914 + 0x3fefae8e8e46cfbb, 0xbfc20116d4ec7bce, // 0.99006, -0.14066 + 0x3fefacc79de6c44f, 0xbfc232d978aed413, // 0.98984, -0.14218 + 0x3fefaafbcb0cfddc, 0xbfc264994dfd340a, // 0.98962, -0.1437 + 0x3fefa92b1600657c, 0xbfc296564d2b953e, // 0.9894, -0.14521 + 0x3fefa7557f08a517, 0xbfc2c8106e8e613a, // 0.98918, -0.14673 + 0x3fefa57b066e2754, 0xbfc2f9c7aa7a72af, // 0.98895, -0.14825 + 0x3fefa39bac7a1791, 0xbfc32b7bf94516a7, // 0.98872, -0.14976 + 0x3fefa1b7717661d5, 0xbfc35d2d53440db2, // 0.98849, -0.15128 + 0x3fef9fce55adb2c8, 0xbfc38edbb0cd8d14, // 0.98826, -0.1528 + 0x3fef9de0596b77a3, 0xbfc3c0870a383ff6, // 0.98802, -0.15431 + 0x3fef9bed7cfbde29, 0xbfc3f22f57db4893, // 0.98778, -0.15583 + 0x3fef99f5c0abd496, 0xbfc423d4920e4166, // 0.98754, -0.15734 + 0x3fef97f924c9099b, 0xbfc45576b1293e5a, // 0.9873, -0.15886 + 0x3fef95f7a9a1ec47, 0xbfc48715ad84cdf5, // 0.98706, -0.16037 + 0x3fef93f14f85ac08, 0xbfc4b8b17f79fa88, // 0.98681, -0.16189 + 0x3fef91e616c43891, 0xbfc4ea4a1f624b61, // 0.98656, -0.1634 + 0x3fef8fd5ffae41db, 0xbfc51bdf8597c5f2, // 0.98631, -0.16491 + 0x3fef8dc10a95380d, 0xbfc54d71aa74ef02, // 0.98605, -0.16643 + 0x3fef8ba737cb4b78, 0xbfc57f008654cbde, // 0.9858, -0.16794 + 0x3fef898887a36c84, 0xbfc5b08c1192e381, // 0.98554, -0.16945 + 0x3fef8764fa714ba9, 0xbfc5e214448b3fc6, // 0.98528, -0.17096 + 0x3fef853c9089595e, 0xbfc61399179a6e94, // 0.98501, -0.17247 + 0x3fef830f4a40c60c, 0xbfc6451a831d830d, // 0.98475, -0.17398 + 0x3fef80dd27ed8204, 0xbfc676987f7216b8, // 0.98448, -0.17549 + 0x3fef7ea629e63d6e, 0xbfc6a81304f64ab2, // 0.98421, -0.177 + 0x3fef7c6a50826840, 0xbfc6d98a0c08c8da, // 0.98394, -0.17851 + 0x3fef7a299c1a322a, 0xbfc70afd8d08c4ff, // 0.98366, -0.18002 + 0x3fef77e40d068a90, 0xbfc73c6d8055fe0a, // 0.98339, -0.18153 + 0x3fef7599a3a12077, 0xbfc76dd9de50bf31, // 0.98311, -0.18304 + 0x3fef734a60446279, 0xbfc79f429f59e11d, // 0.98282, -0.18455 + 0x3fef70f6434b7eb7, 0xbfc7d0a7bbd2cb1b, // 0.98254, -0.18606 + 0x3fef6e9d4d1262ca, 0xbfc802092c1d744b, // 0.98225, -0.18756 + 0x3fef6c3f7df5bbb7, 0xbfc83366e89c64c5, // 0.98196, -0.18907 + 0x3fef69dcd652f5de, 0xbfc864c0e9b2b6cf, // 0.98167, -0.19057 + 0x3fef677556883cee, 0xbfc8961727c41804, // 0.98138, -0.19208 + 0x3fef6508fef47bd5, 0xbfc8c7699b34ca7e, // 0.98108, -0.19359 + 0x3fef6297cff75cb0, 0xbfc8f8b83c69a60a, // 0.98079, -0.19509 + 0x3fef6021c9f148c2, 0xbfc92a0303c8194f, // 0.98048, -0.19659 + 0x3fef5da6ed43685d, 0xbfc95b49e9b62af9, // 0.98018, -0.1981 + 0x3fef5b273a4fa2d9, 0xbfc98c8ce69a7aec, // 0.97988, -0.1996 + 0x3fef58a2b1789e84, 0xbfc9bdcbf2dc4366, // 0.97957, -0.2011 + 0x3fef56195321c090, 0xbfc9ef0706e35a35, // 0.97926, -0.20261 + 0x3fef538b1faf2d07, 0xbfca203e1b1831da, // 0.97895, -0.20411 + 0x3fef50f81785c6b9, 0xbfca517127e3dabc, // 0.97863, -0.20561 + 0x3fef4e603b0b2f2d, 0xbfca82a025b00451, // 0.97832, -0.20711 + 0x3fef4bc38aa5c694, 0xbfcab3cb0ce6fe44, // 0.978, -0.20861 + 0x3fef492206bcabb4, 0xbfcae4f1d5f3b9ab, // 0.97768, -0.21011 + 0x3fef467bafb7bbe0, 0xbfcb16147941ca2a, // 0.97735, -0.21161 + 0x3fef43d085ff92dd, 0xbfcb4732ef3d6722, // 0.97703, -0.21311 + 0x3fef412089fd8adc, 0xbfcb784d30536cda, // 0.9767, -0.21461 + 0x3fef3e6bbc1bbc65, 0xbfcba96334f15dad, // 0.97637, -0.21611 + 0x3fef3bb21cc4fe47, 0xbfcbda74f5856330, // 0.97604, -0.2176 + 0x3fef38f3ac64e589, 0xbfcc0b826a7e4f63, // 0.9757, -0.2191 + 0x3fef36306b67c556, 0xbfcc3c8b8c4b9dd7, // 0.97536, -0.2206 + 0x3fef33685a3aaef0, 0xbfcc6d90535d74dc, // 0.97503, -0.22209 + 0x3fef309b794b719f, 0xbfcc9e90b824a6a9, // 0.97468, -0.22359 + 0x3fef2dc9c9089a9d, 0xbfcccf8cb312b286, // 0.97434, -0.22508 + 0x3fef2af349e17507, 0xbfcd00843c99c5f9, // 0.97399, -0.22658 + 0x3fef2817fc4609ce, 0xbfcd31774d2cbdee, // 0.97364, -0.22807 + 0x3fef2537e0a71f9f, 0xbfcd6265dd3f27e3, // 0.97329, -0.22957 + 0x3fef2252f7763ada, 0xbfcd934fe5454311, // 0.97294, -0.23106 + 0x3fef1f6941259d7a, 0xbfcdc4355db40195, // 0.97258, -0.23255 + 0x3fef1c7abe284708, 0xbfcdf5163f01099a, // 0.97223, -0.23404 + 0x3fef19876ef1f486, 0xbfce25f281a2b684, // 0.97187, -0.23553 + 0x3fef168f53f7205d, 0xbfce56ca1e101a1b, // 0.9715, -0.23702 + 0x3fef13926dad024e, 0xbfce879d0cc0fdaf, // 0.97114, -0.23851 + 0x3fef1090bc898f5f, 0xbfceb86b462de348, // 0.97077, -0.24 + 0x3fef0d8a410379c5, 0xbfcee934c2d006c7, // 0.9704, -0.24149 + 0x3fef0a7efb9230d7, 0xbfcf19f97b215f1a, // 0.97003, -0.24298 + 0x3fef076eecade0fa, 0xbfcf4ab9679c9f5c, // 0.96966, -0.24447 + 0x3fef045a14cf738c, 0xbfcf7b7480bd3801, // 0.96928, -0.24596 + 0x3fef014074708ed3, 0xbfcfac2abeff57ff, // 0.9689, -0.24744 + 0x3feefe220c0b95ec, 0xbfcfdcdc1adfedf8, // 0.96852, -0.24893 + 0x3feefafedc1ba8b7, 0xbfd006c4466e54af, // 0.96814, -0.25041 + 0x3feef7d6e51ca3c0, 0xbfd01f1806b9fdd2, // 0.96775, -0.2519 + 0x3feef4aa278b2032, 0xbfd037694a928cac, // 0.96737, -0.25338 + 0x3feef178a3e473c2, 0xbfd04fb80e37fdae, // 0.96698, -0.25487 + 0x3feeee425aa6b09a, 0xbfd068044deab002, // 0.96658, -0.25635 + 0x3feeeb074c50a544, 0xbfd0804e05eb661e, // 0.96619, -0.25783 + 0x3feee7c77961dc9e, 0xbfd09895327b465e, // 0.96579, -0.25931 + 0x3feee482e25a9dbc, 0xbfd0b0d9cfdbdb90, // 0.96539, -0.26079 + 0x3feee13987bbebdc, 0xbfd0c91bda4f158d, // 0.96499, -0.26227 + 0x3feeddeb6a078651, 0xbfd0e15b4e1749cd, // 0.96459, -0.26375 + 0x3feeda9889bfe86a, 0xbfd0f998277733f7, // 0.96418, -0.26523 + 0x3feed740e7684963, 0xbfd111d262b1f677, // 0.96378, -0.26671 + 0x3feed3e483849c51, 0xbfd12a09fc0b1b12, // 0.96337, -0.26819 + 0x3feed0835e999009, 0xbfd1423eefc69378, // 0.96295, -0.26967 + 0x3feecd1d792c8f10, 0xbfd15a713a28b9d9, // 0.96254, -0.27115 + 0x3feec9b2d3c3bf84, 0xbfd172a0d7765177, // 0.96212, -0.27262 + 0x3feec6436ee60309, 0xbfd18acdc3f4873a, // 0.9617, -0.2741 + 0x3feec2cf4b1af6b2, 0xbfd1a2f7fbe8f243, // 0.96128, -0.27557 + 0x3feebf5668eaf2ef, 0xbfd1bb1f7b999480, // 0.96086, -0.27705 + 0x3feebbd8c8df0b74, 0xbfd1d3443f4cdb3d, // 0.96043, -0.27852 + 0x3feeb8566b810f2a, 0xbfd1eb6643499fbb, // 0.96, -0.27999 + 0x3feeb4cf515b8811, 0xbfd2038583d727bd, // 0.95957, -0.28146 + 0x3feeb1437af9bb34, 0xbfd21ba1fd3d2623, // 0.95914, -0.28294 + 0x3feeadb2e8e7a88e, 0xbfd233bbabc3bb72, // 0.9587, -0.28441 + 0x3feeaa1d9bb20af3, 0xbfd24bd28bb37672, // 0.95827, -0.28588 + 0x3feea68393e65800, 0xbfd263e6995554ba, // 0.95783, -0.28735 + 0x3feea2e4d212c000, 0xbfd27bf7d0f2c346, // 0.95738, -0.28882 + 0x3fee9f4156c62dda, 0xbfd294062ed59f05, // 0.95694, -0.29028 + 0x3fee9b99229046f8, 0xbfd2ac11af483572, // 0.95649, -0.29175 + 0x3fee97ec36016b30, 0xbfd2c41a4e954520, // 0.95605, -0.29322 + 0x3fee943a91aab4b4, 0xbfd2dc200907fe51, // 0.95559, -0.29469 + 0x3fee9084361df7f3, 0xbfd2f422daec0386, // 0.95514, -0.29615 + 0x3fee8cc923edc388, 0xbfd30c22c08d6a13, // 0.95469, -0.29762 + 0x3fee89095bad6025, 0xbfd3241fb638baaf, // 0.95423, -0.29908 + 0x3fee8544ddf0d075, 0xbfd33c19b83af207, // 0.95377, -0.30054 + 0x3fee817bab4cd10d, 0xbfd35410c2e18152, // 0.95331, -0.30201 + 0x3fee7dadc456d850, 0xbfd36c04d27a4edf, // 0.95284, -0.30347 + 0x3fee79db29a5165a, 0xbfd383f5e353b6aa, // 0.95238, -0.30493 + 0x3fee7603dbce74e9, 0xbfd39be3f1bc8aef, // 0.95191, -0.30639 + 0x3fee7227db6a9744, 0xbfd3b3cefa0414b7, // 0.95144, -0.30785 + 0x3fee6e472911da27, 0xbfd3cbb6f87a146e, // 0.95096, -0.30931 + 0x3fee6a61c55d53a7, 0xbfd3e39be96ec271, // 0.95049, -0.31077 + 0x3fee6677b0e6d31e, 0xbfd3fb7dc932cfa4, // 0.95001, -0.31222 + 0x3fee6288ec48e112, 0xbfd4135c94176602, // 0.94953, -0.31368 + 0x3fee5e95781ebf1c, 0xbfd42b38466e2928, // 0.94905, -0.31514 + 0x3fee5a9d550467d3, 0xbfd44310dc8936f0, // 0.94856, -0.31659 + 0x3fee56a083968eb1, 0xbfd45ae652bb2800, // 0.94807, -0.31805 + 0x3fee529f04729ffc, 0xbfd472b8a5571054, // 0.94759, -0.3195 + 0x3fee4e98d836c0af, 0xbfd48a87d0b07fd7, // 0.94709, -0.32096 + 0x3fee4a8dff81ce5e, 0xbfd4a253d11b82f3, // 0.9466, -0.32241 + 0x3fee467e7af35f23, 0xbfd4ba1ca2eca31c, // 0.94611, -0.32386 + 0x3fee426a4b2bc17e, 0xbfd4d1e24278e76a, // 0.94561, -0.32531 + 0x3fee3e5170cbfc46, 0xbfd4e9a4ac15d520, // 0.94511, -0.32676 + 0x3fee3a33ec75ce85, 0xbfd50163dc197047, // 0.9446, -0.32821 + 0x3fee3611becbaf69, 0xbfd5191fceda3c35, // 0.9441, -0.32966 + 0x3fee31eae870ce25, 0xbfd530d880af3c24, // 0.94359, -0.33111 + 0x3fee2dbf6a0911d9, 0xbfd5488dedeff3be, // 0.94308, -0.33255 + 0x3fee298f4439197a, 0xbfd5604012f467b4, // 0.94257, -0.334 + 0x3fee255a77a63bb8, 0xbfd577eeec151e47, // 0.94206, -0.33545 + 0x3fee212104f686e5, 0xbfd58f9a75ab1fdd, // 0.94154, -0.33689 + 0x3fee1ce2ecd0c0d8, 0xbfd5a742ac0ff78d, // 0.94103, -0.33833 + 0x3fee18a02fdc66d9, 0xbfd5bee78b9db3b6, // 0.94051, -0.33978 + 0x3fee1458cec1ad83, 0xbfd5d68910aee686, // 0.93998, -0.34122 + 0x3fee100cca2980ac, 0xbfd5ee27379ea693, // 0.93946, -0.34266 + 0x3fee0bbc22bd8349, 0xbfd605c1fcc88f63, // 0.93893, -0.3441 + 0x3fee0766d9280f54, 0xbfd61d595c88c203, // 0.9384, -0.34554 + 0x3fee030cee1435b8, 0xbfd634ed533be58e, // 0.93787, -0.34698 + 0x3fedfeae622dbe2b, 0xbfd64c7ddd3f27c6, // 0.93734, -0.34842 + 0x3fedfa4b3621271d, 0xbfd6640af6f03d9e, // 0.9368, -0.34986 + 0x3fedf5e36a9ba59c, 0xbfd67b949cad63ca, // 0.93627, -0.35129 + 0x3fedf177004b2534, 0xbfd6931acad55f51, // 0.93573, -0.35273 + 0x3feded05f7de47da, 0xbfd6aa9d7dc77e16, // 0.93518, -0.35416 + 0x3fede890520465ce, 0xbfd6c21cb1e39771, // 0.93464, -0.3556 + 0x3fede4160f6d8d81, 0xbfd6d998638a0cb5, // 0.93409, -0.35703 + 0x3feddf9730ca837b, 0xbfd6f1108f1bc9c5, // 0.93354, -0.35846 + 0x3feddb13b6ccc23d, 0xbfd7088530fa459e, // 0.93299, -0.3599 + 0x3fedd68ba2267a25, 0xbfd71ff6458782ec, // 0.93244, -0.36133 + 0x3fedd1fef38a915a, 0xbfd73763c9261092, // 0.93188, -0.36276 + 0x3fedcd6dabaca3a5, 0xbfd74ecdb8390a3e, // 0.93133, -0.36418 + 0x3fedc8d7cb410260, 0xbfd766340f2418f6, // 0.93077, -0.36561 + 0x3fedc43d52fcb453, 0xbfd77d96ca4b73a6, // 0.93021, -0.36704 + 0x3fedbf9e4395759a, 0xbfd794f5e613dfae, // 0.92964, -0.36847 + 0x3fedbafa9dc1b78d, 0xbfd7ac515ee2b172, // 0.92907, -0.36989 + 0x3fedb6526238a09b, 0xbfd7c3a9311dcce7, // 0.92851, -0.37132 + 0x3fedb1a591b20c38, 0xbfd7dafd592ba621, // 0.92794, -0.37274 + 0x3fedacf42ce68ab9, 0xbfd7f24dd37341e3, // 0.92736, -0.37416 + 0x3feda83e348f613b, 0xbfd8099a9c5c362d, // 0.92679, -0.37559 + 0x3feda383a9668988, 0xbfd820e3b04eaac4, // 0.92621, -0.37701 + 0x3fed9ec48c26b1f3, 0xbfd838290bb359c8, // 0.92563, -0.37843 + 0x3fed9a00dd8b3d46, 0xbfd84f6aaaf3903f, // 0.92505, -0.37985 + 0x3fed95389e50429b, 0xbfd866a88a792ea0, // 0.92447, -0.38127 + 0x3fed906bcf328d46, 0xbfd87de2a6aea963, // 0.92388, -0.38268 + 0x3fed8b9a70ef9cb4, 0xbfd89518fbff098e, // 0.92329, -0.3841 + 0x3fed86c48445a450, 0xbfd8ac4b86d5ed44, // 0.9227, -0.38552 + 0x3fed81ea09f38b63, 0xbfd8c37a439f884f, // 0.92211, -0.38693 + 0x3fed7d0b02b8ecf9, 0xbfd8daa52ec8a4af, // 0.92151, -0.38835 + 0x3fed78276f5617c6, 0xbfd8f1cc44bea329, // 0.92092, -0.38976 + 0x3fed733f508c0dff, 0xbfd908ef81ef7bd1, // 0.92032, -0.39117 + 0x3fed6e52a71c8547, 0xbfd9200ee2c9be97, // 0.91972, -0.39258 + 0x3fed696173c9e68b, 0xbfd9372a63bc93d7, // 0.91911, -0.39399 + 0x3fed646bb7574de5, 0xbfd94e420137bce3, // 0.91851, -0.3954 + 0x3fed5f7172888a7f, 0xbfd96555b7ab948f, // 0.9179, -0.39681 + 0x3fed5a72a6221e73, 0xbfd97c6583890fc2, // 0.91729, -0.39822 + 0x3fed556f52e93eb1, 0xbfd993716141bdfe, // 0.91668, -0.39962 + 0x3fed506779a3d2d9, 0xbfd9aa794d47c9ee, // 0.91606, -0.40103 + 0x3fed4b5b1b187524, 0xbfd9c17d440df9f2, // 0.91545, -0.40243 + 0x3fed464a380e7242, 0xbfd9d87d4207b0ab, // 0.91483, -0.40384 + 0x3fed4134d14dc93a, 0xbfd9ef7943a8ed8a, // 0.91421, -0.40524 + 0x3fed3c1ae79f2b4e, 0xbfda067145664d57, // 0.91359, -0.40664 + 0x3fed36fc7bcbfbdc, 0xbfda1d6543b50ac0, // 0.91296, -0.40804 + 0x3fed31d98e9e503a, 0xbfda34553b0afee5, // 0.91234, -0.40944 + 0x3fed2cb220e0ef9f, 0xbfda4b4127dea1e4, // 0.91171, -0.41084 + 0x3fed2786335f52fc, 0xbfda622906a70b63, // 0.91107, -0.41224 + 0x3fed2255c6e5a4e1, 0xbfda790cd3dbf31a, // 0.91044, -0.41364 + 0x3fed1d20dc40c15c, 0xbfda8fec8bf5b166, // 0.90981, -0.41503 + 0x3fed17e7743e35dc, 0xbfdaa6c82b6d3fc9, // 0.90917, -0.41643 + 0x3fed12a98fac410c, 0xbfdabd9faebc3980, // 0.90853, -0.41782 + 0x3fed0d672f59d2b9, 0xbfdad473125cdc08, // 0.90789, -0.41922 + 0x3fed082054168bac, 0xbfdaeb4252ca07ab, // 0.90724, -0.42061 + 0x3fed02d4feb2bd92, 0xbfdb020d6c7f4009, // 0.9066, -0.422 + 0x3fecfd852fff6ad4, 0xbfdb18d45bf8aca6, // 0.90595, -0.42339 + 0x3fecf830e8ce467b, 0xbfdb2f971db31972, // 0.9053, -0.42478 + 0x3fecf2d829f1b40e, 0xbfdb4655ae2bf757, // 0.90464, -0.42617 + 0x3feced7af43cc773, 0xbfdb5d1009e15cc0, // 0.90399, -0.42756 + 0x3fece819488344ce, 0xbfdb73c62d520624, // 0.90333, -0.42894 + 0x3fece2b32799a060, 0xbfdb8a7814fd5693, // 0.90267, -0.43033 + 0x3fecdd489254fe65, 0xbfdba125bd63583e, // 0.90201, -0.43171 + 0x3fecd7d9898b32f6, 0xbfdbb7cf2304bd01, // 0.90135, -0.43309 + 0x3fecd2660e12c1e6, 0xbfdbce744262deee, // 0.90068, -0.43448 + 0x3fecccee20c2de9f, 0xbfdbe51517ffc0d9, // 0.90002, -0.43586 + 0x3fecc771c2736c09, 0xbfdbfbb1a05e0edc, // 0.89935, -0.43724 + 0x3fecc1f0f3fcfc5c, 0xbfdc1249d8011ee7, // 0.89867, -0.43862 + 0x3fecbc6bb638d10b, 0xbfdc28ddbb6cf145, // 0.898, -0.43999 + 0x3fecb6e20a00da99, 0xbfdc3f6d47263129, // 0.89732, -0.44137 + 0x3fecb153f02fb87d, 0xbfdc55f877b23537, // 0.89665, -0.44275 + 0x3fecabc169a0b901, 0xbfdc6c7f4997000a, // 0.89597, -0.44412 + 0x3feca62a772fd919, 0xbfdc8301b95b40c2, // 0.89528, -0.4455 + 0x3feca08f19b9c449, 0xbfdc997fc3865388, // 0.8946, -0.44687 + 0x3fec9aef521bd480, 0xbfdcaff964a0421d, // 0.89391, -0.44824 + 0x3fec954b213411f5, 0xbfdcc66e9931c45d, // 0.89322, -0.44961 + 0x3fec8fa287e13305, 0xbfdcdcdf5dc440ce, // 0.89253, -0.45098 + 0x3fec89f587029c13, 0xbfdcf34baee1cd21, // 0.89184, -0.45235 + 0x3fec84441f785f61, 0xbfdd09b389152ec1, // 0.89115, -0.45372 + 0x3fec7e8e52233cf3, 0xbfdd2016e8e9db5b, // 0.89045, -0.45508 + 0x3fec78d41fe4a267, 0xbfdd3675caebf962, // 0.88975, -0.45645 + 0x3fec7315899eaad7, 0xbfdd4cd02ba8609c, // 0.88905, -0.45781 + 0x3fec6d5290341eb2, 0xbfdd632607ac9aa9, // 0.88835, -0.45918 + 0x3fec678b3488739b, 0xbfdd79775b86e389, // 0.88764, -0.46054 + 0x3fec61bf777fcc48, 0xbfdd8fc423c62a25, // 0.88693, -0.4619 + 0x3fec5bef59fef85a, 0xbfdda60c5cfa10d8, // 0.88622, -0.46326 + 0x3fec561adceb743e, 0xbfddbc5003b2edf8, // 0.88551, -0.46462 + 0x3fec5042012b6907, 0xbfddd28f1481cc58, // 0.8848, -0.46598 + 0x3fec4a64c7a5ac4c, 0xbfdde8c98bf86bd6, // 0.88408, -0.46733 + 0x3fec44833141c004, 0xbfddfeff66a941de, // 0.88336, -0.46869 + 0x3fec3e9d3ee7d262, 0xbfde1530a12779f4, // 0.88264, -0.47004 + 0x3fec38b2f180bdb1, 0xbfde2b5d3806f63b, // 0.88192, -0.4714 + 0x3fec32c449f60831, 0xbfde418527dc4ffa, // 0.8812, -0.47275 + 0x3fec2cd14931e3f1, 0xbfde57a86d3cd824, // 0.88047, -0.4741 + 0x3fec26d9f01f2eaf, 0xbfde6dc704be97e2, // 0.87974, -0.47545 + 0x3fec20de3fa971b0, 0xbfde83e0eaf85113, // 0.87901, -0.4768 + 0x3fec1ade38bce19b, 0xbfde99f61c817eda, // 0.87828, -0.47815 + 0x3fec14d9dc465e58, 0xbfdeb00695f25620, // 0.87755, -0.47949 + 0x3fec0ed12b3372e9, 0xbfdec61253e3c61b, // 0.87681, -0.48084 + 0x3fec08c426725549, 0xbfdedc1952ef78d5, // 0.87607, -0.48218 + 0x3fec02b2cef1e641, 0xbfdef21b8fafd3b5, // 0.87533, -0.48353 + 0x3febfc9d25a1b147, 0xbfdf081906bff7fd, // 0.87459, -0.48487 + 0x3febf6832b71ec5b, 0xbfdf1e11b4bbc35c, // 0.87384, -0.48621 + 0x3febf064e15377dd, 0xbfdf3405963fd068, // 0.87309, -0.48755 + 0x3febea424837de6d, 0xbfdf49f4a7e97729, // 0.87235, -0.48889 + 0x3febe41b611154c1, 0xbfdf5fdee656cda3, // 0.8716, -0.49023 + 0x3febddf02cd2b983, 0xbfdf75c44e26a852, // 0.87084, -0.49156 + 0x3febd7c0ac6f952a, 0xbfdf8ba4dbf89aba, // 0.87009, -0.4929 + 0x3febd18ce0dc19d6, 0xbfdfa1808c6cf7e0, // 0.86933, -0.49423 + 0x3febcb54cb0d2327, 0xbfdfb7575c24d2de, // 0.86857, -0.49557 + 0x3febc5186bf8361d, 0xbfdfcd2947c1ff57, // 0.86781, -0.4969 + 0x3febbed7c49380ea, 0xbfdfe2f64be7120f, // 0.86705, -0.49823 + 0x3febb892d5d5dad5, 0xbfdff8be6537615e, // 0.86628, -0.49956 + 0x3febb249a0b6c40d, 0xbfe00740c82b82e0, // 0.86551, -0.50089 + 0x3febabfc262e6586, 0xbfe0121fe4f56d2c, // 0.86474, -0.50221 + 0x3feba5aa673590d2, 0xbfe01cfc874c3eb7, // 0.86397, -0.50354 + 0x3feb9f5464c5bffc, 0xbfe027d6ad83287e, // 0.8632, -0.50486 + 0x3feb98fa1fd9155e, 0xbfe032ae55edbd95, // 0.86242, -0.50619 + 0x3feb929b996a5b7f, 0xbfe03d837edff370, // 0.86165, -0.50751 + 0x3feb8c38d27504e9, 0xbfe0485626ae221a, // 0.86087, -0.50883 + 0x3feb85d1cbf52c02, 0xbfe053264bad0483, // 0.86009, -0.51015 + 0x3feb7f6686e792ea, 0xbfe05df3ec31b8b6, // 0.8593, -0.51147 + 0x3feb78f70449a34b, 0xbfe068bf0691c028, // 0.85852, -0.51279 + 0x3feb728345196e3e, 0xbfe073879922ffed, // 0.85773, -0.5141 + 0x3feb6c0b4a55ac17, 0xbfe07e4da23bc102, // 0.85694, -0.51542 + 0x3feb658f14fdbc47, 0xbfe089112032b08c, // 0.85615, -0.51673 + 0x3feb5f0ea611a532, 0xbfe093d2115ee018, // 0.85535, -0.51804 + 0x3feb5889fe921405, 0xbfe09e907417c5e1, // 0.85456, -0.51936 + 0x3feb52011f805c92, 0xbfe0a94c46b53d0b, // 0.85376, -0.52067 + 0x3feb4b7409de7925, 0xbfe0b405878f85ec, // 0.85296, -0.52198 + 0x3feb44e2beaf0a61, 0xbfe0bebc34ff4646, // 0.85216, -0.52328 + 0x3feb3e4d3ef55712, 0xbfe0c9704d5d898f, // 0.85136, -0.52459 + 0x3feb37b38bb54c09, 0xbfe0d421cf03c12b, // 0.85055, -0.5259 + 0x3feb3115a5f37bf4, 0xbfe0ded0b84bc4b5, // 0.84974, -0.5272 + 0x3feb2a738eb51f33, 0xbfe0e97d078fd23b, // 0.84893, -0.5285 + 0x3feb23cd470013b4, 0xbfe0f426bb2a8e7d, // 0.84812, -0.5298 + 0x3feb1d22cfdadcc6, 0xbfe0fecdd1770537, // 0.84731, -0.5311 + 0x3feb16742a4ca2f5, 0xbfe1097248d0a956, // 0.84649, -0.5324 + 0x3feb0fc1575d33db, 0xbfe114141f935545, // 0.84567, -0.5337 + 0x3feb090a58150200, 0xbfe11eb3541b4b22, // 0.84485, -0.535 + 0x3feb024f2d7d24a9, 0xbfe1294fe4c5350a, // 0.84403, -0.53629 + 0x3feafb8fd89f57b6, 0xbfe133e9cfee254e, // 0.84321, -0.53759 + 0x3feaf4cc5a85fb73, 0xbfe13e8113f396c1, // 0.84238, -0.53888 + 0x3feaee04b43c1474, 0xbfe14915af336ceb, // 0.84155, -0.54017 + 0x3feae738e6cd4b67, 0xbfe153a7a00bf453, // 0.84073, -0.54146 + 0x3feae068f345ecef, 0xbfe15e36e4dbe2bc, // 0.83989, -0.54275 + 0x3fead994dab2e979, 0xbfe168c37c025764, // 0.83906, -0.54404 + 0x3fead2bc9e21d511, 0xbfe1734d63dedb49, // 0.83822, -0.54532 + 0x3feacbe03ea0e73b, 0xbfe17dd49ad16161, // 0.83739, -0.54661 + 0x3feac4ffbd3efac8, 0xbfe188591f3a46e5, // 0.83655, -0.54789 + 0x3feabe1b1b0b8dac, 0xbfe192daef7a5386, // 0.83571, -0.54918 + 0x3feab7325916c0d4, 0xbfe19d5a09f2b9b8, // 0.83486, -0.55046 + 0x3feab045787157ff, 0xbfe1a7d66d0516e6, // 0.83402, -0.55174 + 0x3feaa9547a2cb98e, 0xbfe1b250171373be, // 0.83317, -0.55302 + 0x3feaa25f5f5aee60, 0xbfe1bcc706804467, // 0.83232, -0.55429 + 0x3fea9b66290ea1a3, 0xbfe1c73b39ae68c8, // 0.83147, -0.55557 + 0x3fea9468d85b20ae, 0xbfe1d1acaf012cc2, // 0.83062, -0.55685 + 0x3fea8d676e545ad2, 0xbfe1dc1b64dc4872, // 0.82976, -0.55812 + 0x3fea8661ec0ee133, 0xbfe1e68759a3e074, // 0.8289, -0.55939 + 0x3fea7f58529fe69d, 0xbfe1f0f08bbc861b, // 0.82805, -0.56066 + 0x3fea784aa31d3f55, 0xbfe1fb56f98b37b8, // 0.82718, -0.56193 + 0x3fea7138de9d60f5, 0xbfe205baa17560d6, // 0.82632, -0.5632 + 0x3fea6a230637623b, 0xbfe2101b81e0da78, // 0.82546, -0.56447 + 0x3fea63091b02fae2, 0xbfe21a799933eb58, // 0.82459, -0.56573 + 0x3fea5beb1e188375, 0xbfe224d4e5d5482e, // 0.82372, -0.567 + 0x3fea54c91090f524, 0xbfe22f2d662c13e1, // 0.82285, -0.56826 + 0x3fea4da2f385e997, 0xbfe23983189fdfd5, // 0.82198, -0.56952 + 0x3fea4678c8119ac8, 0xbfe243d5fb98ac1f, // 0.8211, -0.57078 + 0x3fea3f4a8f4ee2d2, 0xbfe24e260d7ee7c9, // 0.82023, -0.57204 + 0x3fea38184a593bc6, 0xbfe258734cbb7110, // 0.81935, -0.5733 + 0x3fea30e1fa4cbf81, 0xbfe262bdb7b795a2, // 0.81847, -0.57455 + 0x3fea29a7a0462782, 0xbfe26d054cdd12df, // 0.81758, -0.57581 + 0x3fea22693d62ccb9, 0xbfe2774a0a961612, // 0.8167, -0.57706 + 0x3fea1b26d2c0a75e, 0xbfe2818bef4d3cba, // 0.81581, -0.57831 + 0x3fea13e0617e4ec7, 0xbfe28bcaf96d94ba, // 0.81493, -0.57956 + 0x3fea0c95eabaf937, 0xbfe2960727629ca8, // 0.81404, -0.58081 + 0x3fea05476f967bb5, 0xbfe2a040779843fb, // 0.81314, -0.58206 + 0x3fe9fdf4f13149de, 0xbfe2aa76e87aeb58, // 0.81225, -0.58331 + 0x3fe9f69e70ac75bc, 0xbfe2b4aa787764c4, // 0.81135, -0.58455 + 0x3fe9ef43ef29af94, 0xbfe2bedb25faf3ea, // 0.81046, -0.5858 + 0x3fe9e7e56dcb45bd, 0xbfe2c908ef734e57, // 0.80956, -0.58704 + 0x3fe9e082edb42472, 0xbfe2d333d34e9bb7, // 0.80866, -0.58828 + 0x3fe9d91c7007d5a6, 0xbfe2dd5bcffb7616, // 0.80775, -0.58952 + 0x3fe9d1b1f5ea80d6, 0xbfe2e780e3e8ea16, // 0.80685, -0.59076 + 0x3fe9ca438080eadb, 0xbfe2f1a30d86773a, // 0.80594, -0.592 + 0x3fe9c2d110f075c3, 0xbfe2fbc24b441015, // 0.80503, -0.59323 + 0x3fe9bb5aa85f2098, 0xbfe305de9b921a94, // 0.80412, -0.59447 + 0x3fe9b3e047f38741, 0xbfe30ff7fce17035, // 0.80321, -0.5957 + 0x3fe9ac61f0d4e247, 0xbfe31a0e6da35e44, // 0.80229, -0.59693 + 0x3fe9a4dfa42b06b2, 0xbfe32421ec49a620, // 0.80138, -0.59816 + 0x3fe99d59631e65d5, 0xbfe32e3277467d6b, // 0.80046, -0.59939 + 0x3fe995cf2ed80d22, 0xbfe338400d0c8e57, // 0.79954, -0.60062 + 0x3fe98e410881a600, 0xbfe3424aac0ef7d6, // 0.79861, -0.60184 + 0x3fe986aef1457594, 0xbfe34c5252c14de1, // 0.79769, -0.60307 + 0x3fe97f18ea4e5c9e, 0xbfe35656ff9799ae, // 0.79676, -0.60429 + 0x3fe9777ef4c7d742, 0xbfe36058b10659f3, // 0.79584, -0.60551 + 0x3fe96fe111ddfce0, 0xbfe36a576582831b, // 0.79491, -0.60673 + 0x3fe9683f42bd7fe1, 0xbfe374531b817f8d, // 0.79398, -0.60795 + 0x3fe960998893ad8c, 0xbfe37e4bd1792fe2, // 0.79304, -0.60917 + 0x3fe958efe48e6dd7, 0xbfe3884185dfeb22, // 0.79211, -0.61038 + 0x3fe9514257dc4335, 0xbfe39234372c7f04, // 0.79117, -0.6116 + 0x3fe94990e3ac4a6c, 0xbfe39c23e3d63029, // 0.79023, -0.61281 + 0x3fe941db892e3a65, 0xbfe3a6108a54ba58, // 0.78929, -0.61402 + 0x3fe93a22499263fc, 0xbfe3affa292050b9, // 0.78835, -0.61523 + 0x3fe932652609b1cf, 0xbfe3b9e0beb19e18, // 0.7874, -0.61644 + 0x3fe92aa41fc5a815, 0xbfe3c3c44981c517, // 0.78646, -0.61765 + 0x3fe922df37f8646a, 0xbfe3cda4c80a6076, // 0.78551, -0.61885 + 0x3fe91b166fd49da2, 0xbfe3d78238c58343, // 0.78456, -0.62006 + 0x3fe91349c88da398, 0xbfe3e15c9a2db922, // 0.7836, -0.62126 + 0x3fe90b7943575efe, 0xbfe3eb33eabe0680, // 0.78265, -0.62246 + 0x3fe903a4e1665133, 0xbfe3f50828f1e8d2, // 0.78169, -0.62366 + 0x3fe8fbcca3ef940d, 0xbfe3fed9534556d4, // 0.78074, -0.62486 + 0x3fe8f3f08c28d9ac, 0xbfe408a76834c0c0, // 0.77978, -0.62606 + 0x3fe8ec109b486c49, 0xbfe41272663d108c, // 0.77882, -0.62725 + 0x3fe8e42cd2852e0a, 0xbfe41c3a4bdbaa26, // 0.77785, -0.62845 + 0x3fe8dc45331698cc, 0xbfe425ff178e6bb1, // 0.77689, -0.62964 + 0x3fe8d459be34bdfa, 0xbfe42fc0c7d3adbb, // 0.77592, -0.63083 + 0x3fe8cc6a75184655, 0xbfe4397f5b2a4380, // 0.77495, -0.63202 + 0x3fe8c47758fa71cb, 0xbfe4433ad0117b1d, // 0.77398, -0.63321 + 0x3fe8bc806b151741, 0xbfe44cf325091dd6, // 0.77301, -0.63439 + 0x3fe8b485aca2a468, 0xbfe456a858917046, // 0.77204, -0.63558 + 0x3fe8ac871ede1d88, 0xbfe4605a692b32a2, // 0.77106, -0.63676 + 0x3fe8a484c3031d50, 0xbfe46a095557a0f1, // 0.77008, -0.63794 + 0x3fe89c7e9a4dd4ab, 0xbfe473b51b987347, // 0.7691, -0.63912 + 0x3fe89474a5fb0a84, 0xbfe47d5dba6fde01, // 0.76812, -0.6403 + 0x3fe88c66e7481ba1, 0xbfe48703306091fe, // 0.76714, -0.64148 + 0x3fe884555f72fa6b, 0xbfe490a57bedbcdf, // 0.76615, -0.64266 + 0x3fe87c400fba2ebf, 0xbfe49a449b9b0938, // 0.76517, -0.64383 + 0x3fe87426f95cd5bd, 0xbfe4a3e08dec9ed6, // 0.76418, -0.645 + 0x3fe86c0a1d9aa195, 0xbfe4ad79516722f0, // 0.76319, -0.64618 + 0x3fe863e97db3d95a, 0xbfe4b70ee48fb869, // 0.7622, -0.64735 + 0x3fe85bc51ae958cc, 0xbfe4c0a145ec0004, // 0.7612, -0.64851 + 0x3fe8539cf67c9029, 0xbfe4ca30740218a3, // 0.76021, -0.64968 + 0x3fe84b7111af83f9, 0xbfe4d3bc6d589f80, // 0.75921, -0.65085 + 0x3fe843416dc4cce2, 0xbfe4dd453076b064, // 0.75821, -0.65201 + 0x3fe83b0e0bff976e, 0xbfe4e6cabbe3e5e9, // 0.75721, -0.65317 + 0x3fe832d6eda3a3e0, 0xbfe4f04d0e2859aa, // 0.75621, -0.65433 + 0x3fe82a9c13f545ff, 0xbfe4f9cc25cca486, // 0.7552, -0.65549 + 0x3fe8225d803964e5, 0xbfe503480159ded2, // 0.75419, -0.65665 + 0x3fe81a1b33b57acc, 0xbfe50cc09f59a09b, // 0.75319, -0.65781 + 0x3fe811d52faf94dc, 0xbfe51635fe5601d7, // 0.75218, -0.65896 + 0x3fe8098b756e52fa, 0xbfe51fa81cd99aa6, // 0.75117, -0.66011 + 0x3fe8013e0638e795, 0xbfe52916f96f8388, // 0.75015, -0.66127 + 0x3fe7f8ece3571771, 0xbfe5328292a35596, // 0.74914, -0.66242 + 0x3fe7f0980e113978, 0xbfe53beae7012abe, // 0.74812, -0.66356 + 0x3fe7e83f87b03686, 0xbfe5454ff5159dfb, // 0.7471, -0.66471 + 0x3fe7dfe3517d8937, 0xbfe54eb1bb6dcb8f, // 0.74608, -0.66586 + 0x3fe7d7836cc33db2, 0xbfe5581038975137, // 0.74506, -0.667 + 0x3fe7cf1fdacbf179, 0xbfe5616b6b204e6e, // 0.74403, -0.66814 + 0x3fe7c6b89ce2d333, 0xbfe56ac35197649e, // 0.74301, -0.66928 + 0x3fe7be4db453a27c, 0xbfe57417ea8bb75c, // 0.74198, -0.67042 + 0x3fe7b5df226aafb0, 0xbfe57d69348cec9f, // 0.74095, -0.67156 + 0x3fe7ad6ce874dbb6, 0xbfe586b72e2b2cfd, // 0.73992, -0.67269 + 0x3fe7a4f707bf97d2, 0xbfe59001d5f723df, // 0.73889, -0.67383 + 0x3fe79c7d8198e56e, 0xbfe599492a81ffbc, // 0.73785, -0.67496 + 0x3fe79400574f55e4, 0xbfe5a28d2a5d7250, // 0.73682, -0.67609 + 0x3fe78b7f8a320a52, 0xbfe5abcdd41bb0d8, // 0.73578, -0.67722 + 0x3fe782fb1b90b35b, 0xbfe5b50b264f7448, // 0.73474, -0.67835 + 0x3fe77a730cbb9100, 0xbfe5be451f8bf980, // 0.7337, -0.67948 + 0x3fe771e75f037261, 0xbfe5c77bbe65018c, // 0.73265, -0.6806 + 0x3fe7695813b9b594, 0xbfe5d0af016ed1d4, // 0.73161, -0.68172 + 0x3fe760c52c304764, 0xbfe5d9dee73e345c, // 0.73056, -0.68285 + 0x3fe7582ea9b9a329, 0xbfe5e30b6e6877f3, // 0.72951, -0.68397 + 0x3fe74f948da8d28d, 0xbfe5ec3495837074, // 0.72846, -0.68508 + 0x3fe746f6d9516d59, 0xbfe5f55a5b2576f8, // 0.72741, -0.6862 + 0x3fe73e558e079942, 0xbfe5fe7cbde56a0f, // 0.72636, -0.68732 + 0x3fe735b0ad2009b2, 0xbfe6079bbc5aadfa, // 0.7253, -0.68843 + 0x3fe72d0837efff97, 0xbfe610b7551d2cde, // 0.72425, -0.68954 + 0x3fe7245c2fcd492a, 0xbfe619cf86c55702, // 0.72319, -0.69065 + 0x3fe71bac960e41bf, 0xbfe622e44fec22ff, // 0.72213, -0.69176 + 0x3fe712f96c09d18d, 0xbfe62bf5af2b0dfd, // 0.72107, -0.69287 + 0x3fe70a42b3176d7a, 0xbfe63503a31c1be8, // 0.72, -0.69397 + 0x3fe701886c8f16e6, 0xbfe63e0e2a59d7aa, // 0.71894, -0.69508 + 0x3fe6f8ca99c95b75, 0xbfe64715437f535b, // 0.71787, -0.69618 + 0x3fe6f0093c1f54de, 0xbfe65018ed28287f, // 0.7168, -0.69728 + 0x3fe6e74454eaa8ae, 0xbfe6591925f0783e, // 0.71573, -0.69838 + 0x3fe6de7be585881d, 0xbfe66215ec74eb91, // 0.71466, -0.69947 + 0x3fe6d5afef4aafcc, 0xbfe66b0f3f52b386, // 0.71358, -0.70057 + 0x3fe6cce07395679f, 0xbfe674051d27896c, // 0.71251, -0.70166 + 0x3fe6c40d73c18275, 0xbfe67cf78491af10, // 0.71143, -0.70275 + 0x3fe6bb36f12b5e06, 0xbfe685e6742feeef, // 0.71035, -0.70385 + 0x3fe6b25ced2fe29c, 0xbfe68ed1eaa19c71, // 0.70927, -0.70493 + 0x3fe6a97f692c82ea, 0xbfe697b9e686941c, // 0.70819, -0.70602 + 0x3fe6a09e667f3bcc, 0xbfe6a09e667f3bcc, // 0.70711, -0.70711 + 0x3fe697b9e686941c, 0xbfe6a97f692c82ea, // 0.70602, -0.70819 + 0x3fe68ed1eaa19c71, 0xbfe6b25ced2fe29c, // 0.70493, -0.70927 + 0x3fe685e6742feeef, 0xbfe6bb36f12b5e06, // 0.70385, -0.71035 + 0x3fe67cf78491af10, 0xbfe6c40d73c18275, // 0.70275, -0.71143 + 0x3fe674051d27896c, 0xbfe6cce07395679f, // 0.70166, -0.71251 + 0x3fe66b0f3f52b386, 0xbfe6d5afef4aafcc, // 0.70057, -0.71358 + 0x3fe66215ec74eb91, 0xbfe6de7be585881d, // 0.69947, -0.71466 + 0x3fe6591925f0783e, 0xbfe6e74454eaa8ae, // 0.69838, -0.71573 + 0x3fe65018ed28287f, 0xbfe6f0093c1f54de, // 0.69728, -0.7168 + 0x3fe64715437f535b, 0xbfe6f8ca99c95b75, // 0.69618, -0.71787 + 0x3fe63e0e2a59d7aa, 0xbfe701886c8f16e6, // 0.69508, -0.71894 + 0x3fe63503a31c1be8, 0xbfe70a42b3176d7a, // 0.69397, -0.72 + 0x3fe62bf5af2b0dfd, 0xbfe712f96c09d18d, // 0.69287, -0.72107 + 0x3fe622e44fec22ff, 0xbfe71bac960e41bf, // 0.69176, -0.72213 + 0x3fe619cf86c55702, 0xbfe7245c2fcd492a, // 0.69065, -0.72319 + 0x3fe610b7551d2cde, 0xbfe72d0837efff97, // 0.68954, -0.72425 + 0x3fe6079bbc5aadfa, 0xbfe735b0ad2009b2, // 0.68843, -0.7253 + 0x3fe5fe7cbde56a0f, 0xbfe73e558e079942, // 0.68732, -0.72636 + 0x3fe5f55a5b2576f8, 0xbfe746f6d9516d59, // 0.6862, -0.72741 + 0x3fe5ec3495837074, 0xbfe74f948da8d28d, // 0.68508, -0.72846 + 0x3fe5e30b6e6877f3, 0xbfe7582ea9b9a329, // 0.68397, -0.72951 + 0x3fe5d9dee73e345c, 0xbfe760c52c304764, // 0.68285, -0.73056 + 0x3fe5d0af016ed1d4, 0xbfe7695813b9b594, // 0.68172, -0.73161 + 0x3fe5c77bbe65018c, 0xbfe771e75f037261, // 0.6806, -0.73265 + 0x3fe5be451f8bf980, 0xbfe77a730cbb9100, // 0.67948, -0.7337 + 0x3fe5b50b264f7448, 0xbfe782fb1b90b35b, // 0.67835, -0.73474 + 0x3fe5abcdd41bb0d8, 0xbfe78b7f8a320a52, // 0.67722, -0.73578 + 0x3fe5a28d2a5d7250, 0xbfe79400574f55e4, // 0.67609, -0.73682 + 0x3fe599492a81ffbc, 0xbfe79c7d8198e56e, // 0.67496, -0.73785 + 0x3fe59001d5f723df, 0xbfe7a4f707bf97d2, // 0.67383, -0.73889 + 0x3fe586b72e2b2cfd, 0xbfe7ad6ce874dbb6, // 0.67269, -0.73992 + 0x3fe57d69348cec9f, 0xbfe7b5df226aafb0, // 0.67156, -0.74095 + 0x3fe57417ea8bb75c, 0xbfe7be4db453a27c, // 0.67042, -0.74198 + 0x3fe56ac35197649e, 0xbfe7c6b89ce2d333, // 0.66928, -0.74301 + 0x3fe5616b6b204e6e, 0xbfe7cf1fdacbf179, // 0.66814, -0.74403 + 0x3fe5581038975137, 0xbfe7d7836cc33db2, // 0.667, -0.74506 + 0x3fe54eb1bb6dcb8f, 0xbfe7dfe3517d8937, // 0.66586, -0.74608 + 0x3fe5454ff5159dfb, 0xbfe7e83f87b03686, // 0.66471, -0.7471 + 0x3fe53beae7012abe, 0xbfe7f0980e113978, // 0.66356, -0.74812 + 0x3fe5328292a35596, 0xbfe7f8ece3571771, // 0.66242, -0.74914 + 0x3fe52916f96f8388, 0xbfe8013e0638e795, // 0.66127, -0.75015 + 0x3fe51fa81cd99aa6, 0xbfe8098b756e52fa, // 0.66011, -0.75117 + 0x3fe51635fe5601d7, 0xbfe811d52faf94dc, // 0.65896, -0.75218 + 0x3fe50cc09f59a09b, 0xbfe81a1b33b57acc, // 0.65781, -0.75319 + 0x3fe503480159ded2, 0xbfe8225d803964e5, // 0.65665, -0.75419 + 0x3fe4f9cc25cca486, 0xbfe82a9c13f545ff, // 0.65549, -0.7552 + 0x3fe4f04d0e2859aa, 0xbfe832d6eda3a3e0, // 0.65433, -0.75621 + 0x3fe4e6cabbe3e5e9, 0xbfe83b0e0bff976e, // 0.65317, -0.75721 + 0x3fe4dd453076b064, 0xbfe843416dc4cce2, // 0.65201, -0.75821 + 0x3fe4d3bc6d589f80, 0xbfe84b7111af83f9, // 0.65085, -0.75921 + 0x3fe4ca30740218a3, 0xbfe8539cf67c9029, // 0.64968, -0.76021 + 0x3fe4c0a145ec0004, 0xbfe85bc51ae958cc, // 0.64851, -0.7612 + 0x3fe4b70ee48fb869, 0xbfe863e97db3d95a, // 0.64735, -0.7622 + 0x3fe4ad79516722f0, 0xbfe86c0a1d9aa195, // 0.64618, -0.76319 + 0x3fe4a3e08dec9ed6, 0xbfe87426f95cd5bd, // 0.645, -0.76418 + 0x3fe49a449b9b0938, 0xbfe87c400fba2ebf, // 0.64383, -0.76517 + 0x3fe490a57bedbcdf, 0xbfe884555f72fa6b, // 0.64266, -0.76615 + 0x3fe48703306091fe, 0xbfe88c66e7481ba1, // 0.64148, -0.76714 + 0x3fe47d5dba6fde01, 0xbfe89474a5fb0a84, // 0.6403, -0.76812 + 0x3fe473b51b987347, 0xbfe89c7e9a4dd4ab, // 0.63912, -0.7691 + 0x3fe46a095557a0f1, 0xbfe8a484c3031d50, // 0.63794, -0.77008 + 0x3fe4605a692b32a2, 0xbfe8ac871ede1d88, // 0.63676, -0.77106 + 0x3fe456a858917046, 0xbfe8b485aca2a468, // 0.63558, -0.77204 + 0x3fe44cf325091dd6, 0xbfe8bc806b151741, // 0.63439, -0.77301 + 0x3fe4433ad0117b1d, 0xbfe8c47758fa71cb, // 0.63321, -0.77398 + 0x3fe4397f5b2a4380, 0xbfe8cc6a75184655, // 0.63202, -0.77495 + 0x3fe42fc0c7d3adbb, 0xbfe8d459be34bdfa, // 0.63083, -0.77592 + 0x3fe425ff178e6bb1, 0xbfe8dc45331698cc, // 0.62964, -0.77689 + 0x3fe41c3a4bdbaa26, 0xbfe8e42cd2852e0a, // 0.62845, -0.77785 + 0x3fe41272663d108c, 0xbfe8ec109b486c49, // 0.62725, -0.77882 + 0x3fe408a76834c0c0, 0xbfe8f3f08c28d9ac, // 0.62606, -0.77978 + 0x3fe3fed9534556d4, 0xbfe8fbcca3ef940d, // 0.62486, -0.78074 + 0x3fe3f50828f1e8d2, 0xbfe903a4e1665133, // 0.62366, -0.78169 + 0x3fe3eb33eabe0680, 0xbfe90b7943575efe, // 0.62246, -0.78265 + 0x3fe3e15c9a2db922, 0xbfe91349c88da398, // 0.62126, -0.7836 + 0x3fe3d78238c58343, 0xbfe91b166fd49da2, // 0.62006, -0.78456 + 0x3fe3cda4c80a6076, 0xbfe922df37f8646a, // 0.61885, -0.78551 + 0x3fe3c3c44981c517, 0xbfe92aa41fc5a815, // 0.61765, -0.78646 + 0x3fe3b9e0beb19e18, 0xbfe932652609b1cf, // 0.61644, -0.7874 + 0x3fe3affa292050b9, 0xbfe93a22499263fc, // 0.61523, -0.78835 + 0x3fe3a6108a54ba58, 0xbfe941db892e3a65, // 0.61402, -0.78929 + 0x3fe39c23e3d63029, 0xbfe94990e3ac4a6c, // 0.61281, -0.79023 + 0x3fe39234372c7f04, 0xbfe9514257dc4335, // 0.6116, -0.79117 + 0x3fe3884185dfeb22, 0xbfe958efe48e6dd7, // 0.61038, -0.79211 + 0x3fe37e4bd1792fe2, 0xbfe960998893ad8c, // 0.60917, -0.79304 + 0x3fe374531b817f8d, 0xbfe9683f42bd7fe1, // 0.60795, -0.79398 + 0x3fe36a576582831b, 0xbfe96fe111ddfce0, // 0.60673, -0.79491 + 0x3fe36058b10659f3, 0xbfe9777ef4c7d742, // 0.60551, -0.79584 + 0x3fe35656ff9799ae, 0xbfe97f18ea4e5c9e, // 0.60429, -0.79676 + 0x3fe34c5252c14de1, 0xbfe986aef1457594, // 0.60307, -0.79769 + 0x3fe3424aac0ef7d6, 0xbfe98e410881a600, // 0.60184, -0.79861 + 0x3fe338400d0c8e57, 0xbfe995cf2ed80d22, // 0.60062, -0.79954 + 0x3fe32e3277467d6b, 0xbfe99d59631e65d5, // 0.59939, -0.80046 + 0x3fe32421ec49a620, 0xbfe9a4dfa42b06b2, // 0.59816, -0.80138 + 0x3fe31a0e6da35e44, 0xbfe9ac61f0d4e247, // 0.59693, -0.80229 + 0x3fe30ff7fce17035, 0xbfe9b3e047f38741, // 0.5957, -0.80321 + 0x3fe305de9b921a94, 0xbfe9bb5aa85f2098, // 0.59447, -0.80412 + 0x3fe2fbc24b441015, 0xbfe9c2d110f075c3, // 0.59323, -0.80503 + 0x3fe2f1a30d86773a, 0xbfe9ca438080eadb, // 0.592, -0.80594 + 0x3fe2e780e3e8ea16, 0xbfe9d1b1f5ea80d6, // 0.59076, -0.80685 + 0x3fe2dd5bcffb7616, 0xbfe9d91c7007d5a6, // 0.58952, -0.80775 + 0x3fe2d333d34e9bb7, 0xbfe9e082edb42472, // 0.58828, -0.80866 + 0x3fe2c908ef734e57, 0xbfe9e7e56dcb45bd, // 0.58704, -0.80956 + 0x3fe2bedb25faf3ea, 0xbfe9ef43ef29af94, // 0.5858, -0.81046 + 0x3fe2b4aa787764c4, 0xbfe9f69e70ac75bc, // 0.58455, -0.81135 + 0x3fe2aa76e87aeb58, 0xbfe9fdf4f13149de, // 0.58331, -0.81225 + 0x3fe2a040779843fb, 0xbfea05476f967bb5, // 0.58206, -0.81314 + 0x3fe2960727629ca8, 0xbfea0c95eabaf937, // 0.58081, -0.81404 + 0x3fe28bcaf96d94ba, 0xbfea13e0617e4ec7, // 0.57956, -0.81493 + 0x3fe2818bef4d3cba, 0xbfea1b26d2c0a75e, // 0.57831, -0.81581 + 0x3fe2774a0a961612, 0xbfea22693d62ccb9, // 0.57706, -0.8167 + 0x3fe26d054cdd12df, 0xbfea29a7a0462782, // 0.57581, -0.81758 + 0x3fe262bdb7b795a2, 0xbfea30e1fa4cbf81, // 0.57455, -0.81847 + 0x3fe258734cbb7110, 0xbfea38184a593bc6, // 0.5733, -0.81935 + 0x3fe24e260d7ee7c9, 0xbfea3f4a8f4ee2d2, // 0.57204, -0.82023 + 0x3fe243d5fb98ac1f, 0xbfea4678c8119ac8, // 0.57078, -0.8211 + 0x3fe23983189fdfd5, 0xbfea4da2f385e997, // 0.56952, -0.82198 + 0x3fe22f2d662c13e1, 0xbfea54c91090f524, // 0.56826, -0.82285 + 0x3fe224d4e5d5482e, 0xbfea5beb1e188375, // 0.567, -0.82372 + 0x3fe21a799933eb58, 0xbfea63091b02fae2, // 0.56573, -0.82459 + 0x3fe2101b81e0da78, 0xbfea6a230637623b, // 0.56447, -0.82546 + 0x3fe205baa17560d6, 0xbfea7138de9d60f5, // 0.5632, -0.82632 + 0x3fe1fb56f98b37b8, 0xbfea784aa31d3f55, // 0.56193, -0.82718 + 0x3fe1f0f08bbc861b, 0xbfea7f58529fe69d, // 0.56066, -0.82805 + 0x3fe1e68759a3e074, 0xbfea8661ec0ee133, // 0.55939, -0.8289 + 0x3fe1dc1b64dc4872, 0xbfea8d676e545ad2, // 0.55812, -0.82976 + 0x3fe1d1acaf012cc2, 0xbfea9468d85b20ae, // 0.55685, -0.83062 + 0x3fe1c73b39ae68c8, 0xbfea9b66290ea1a3, // 0.55557, -0.83147 + 0x3fe1bcc706804467, 0xbfeaa25f5f5aee60, // 0.55429, -0.83232 + 0x3fe1b250171373be, 0xbfeaa9547a2cb98e, // 0.55302, -0.83317 + 0x3fe1a7d66d0516e6, 0xbfeab045787157ff, // 0.55174, -0.83402 + 0x3fe19d5a09f2b9b8, 0xbfeab7325916c0d4, // 0.55046, -0.83486 + 0x3fe192daef7a5386, 0xbfeabe1b1b0b8dac, // 0.54918, -0.83571 + 0x3fe188591f3a46e5, 0xbfeac4ffbd3efac8, // 0.54789, -0.83655 + 0x3fe17dd49ad16161, 0xbfeacbe03ea0e73b, // 0.54661, -0.83739 + 0x3fe1734d63dedb49, 0xbfead2bc9e21d511, // 0.54532, -0.83822 + 0x3fe168c37c025764, 0xbfead994dab2e979, // 0.54404, -0.83906 + 0x3fe15e36e4dbe2bc, 0xbfeae068f345ecef, // 0.54275, -0.83989 + 0x3fe153a7a00bf453, 0xbfeae738e6cd4b67, // 0.54146, -0.84073 + 0x3fe14915af336ceb, 0xbfeaee04b43c1474, // 0.54017, -0.84155 + 0x3fe13e8113f396c1, 0xbfeaf4cc5a85fb73, // 0.53888, -0.84238 + 0x3fe133e9cfee254e, 0xbfeafb8fd89f57b6, // 0.53759, -0.84321 + 0x3fe1294fe4c5350a, 0xbfeb024f2d7d24a9, // 0.53629, -0.84403 + 0x3fe11eb3541b4b22, 0xbfeb090a58150200, // 0.535, -0.84485 + 0x3fe114141f935545, 0xbfeb0fc1575d33db, // 0.5337, -0.84567 + 0x3fe1097248d0a956, 0xbfeb16742a4ca2f5, // 0.5324, -0.84649 + 0x3fe0fecdd1770537, 0xbfeb1d22cfdadcc6, // 0.5311, -0.84731 + 0x3fe0f426bb2a8e7d, 0xbfeb23cd470013b4, // 0.5298, -0.84812 + 0x3fe0e97d078fd23b, 0xbfeb2a738eb51f33, // 0.5285, -0.84893 + 0x3fe0ded0b84bc4b5, 0xbfeb3115a5f37bf4, // 0.5272, -0.84974 + 0x3fe0d421cf03c12b, 0xbfeb37b38bb54c09, // 0.5259, -0.85055 + 0x3fe0c9704d5d898f, 0xbfeb3e4d3ef55712, // 0.52459, -0.85136 + 0x3fe0bebc34ff4646, 0xbfeb44e2beaf0a61, // 0.52328, -0.85216 + 0x3fe0b405878f85ec, 0xbfeb4b7409de7925, // 0.52198, -0.85296 + 0x3fe0a94c46b53d0b, 0xbfeb52011f805c92, // 0.52067, -0.85376 + 0x3fe09e907417c5e1, 0xbfeb5889fe921405, // 0.51936, -0.85456 + 0x3fe093d2115ee018, 0xbfeb5f0ea611a532, // 0.51804, -0.85535 + 0x3fe089112032b08c, 0xbfeb658f14fdbc47, // 0.51673, -0.85615 + 0x3fe07e4da23bc102, 0xbfeb6c0b4a55ac17, // 0.51542, -0.85694 + 0x3fe073879922ffed, 0xbfeb728345196e3e, // 0.5141, -0.85773 + 0x3fe068bf0691c028, 0xbfeb78f70449a34b, // 0.51279, -0.85852 + 0x3fe05df3ec31b8b6, 0xbfeb7f6686e792ea, // 0.51147, -0.8593 + 0x3fe053264bad0483, 0xbfeb85d1cbf52c02, // 0.51015, -0.86009 + 0x3fe0485626ae221a, 0xbfeb8c38d27504e9, // 0.50883, -0.86087 + 0x3fe03d837edff370, 0xbfeb929b996a5b7f, // 0.50751, -0.86165 + 0x3fe032ae55edbd95, 0xbfeb98fa1fd9155e, // 0.50619, -0.86242 + 0x3fe027d6ad83287e, 0xbfeb9f5464c5bffc, // 0.50486, -0.8632 + 0x3fe01cfc874c3eb7, 0xbfeba5aa673590d2, // 0.50354, -0.86397 + 0x3fe0121fe4f56d2c, 0xbfebabfc262e6586, // 0.50221, -0.86474 + 0x3fe00740c82b82e0, 0xbfebb249a0b6c40d, // 0.50089, -0.86551 + 0x3fdff8be6537615e, 0xbfebb892d5d5dad5, // 0.49956, -0.86628 + 0x3fdfe2f64be7120f, 0xbfebbed7c49380ea, // 0.49823, -0.86705 + 0x3fdfcd2947c1ff57, 0xbfebc5186bf8361d, // 0.4969, -0.86781 + 0x3fdfb7575c24d2de, 0xbfebcb54cb0d2327, // 0.49557, -0.86857 + 0x3fdfa1808c6cf7e0, 0xbfebd18ce0dc19d6, // 0.49423, -0.86933 + 0x3fdf8ba4dbf89aba, 0xbfebd7c0ac6f952a, // 0.4929, -0.87009 + 0x3fdf75c44e26a852, 0xbfebddf02cd2b983, // 0.49156, -0.87084 + 0x3fdf5fdee656cda3, 0xbfebe41b611154c1, // 0.49023, -0.8716 + 0x3fdf49f4a7e97729, 0xbfebea424837de6d, // 0.48889, -0.87235 + 0x3fdf3405963fd068, 0xbfebf064e15377dd, // 0.48755, -0.87309 + 0x3fdf1e11b4bbc35c, 0xbfebf6832b71ec5b, // 0.48621, -0.87384 + 0x3fdf081906bff7fd, 0xbfebfc9d25a1b147, // 0.48487, -0.87459 + 0x3fdef21b8fafd3b5, 0xbfec02b2cef1e641, // 0.48353, -0.87533 + 0x3fdedc1952ef78d5, 0xbfec08c426725549, // 0.48218, -0.87607 + 0x3fdec61253e3c61b, 0xbfec0ed12b3372e9, // 0.48084, -0.87681 + 0x3fdeb00695f25620, 0xbfec14d9dc465e58, // 0.47949, -0.87755 + 0x3fde99f61c817eda, 0xbfec1ade38bce19b, // 0.47815, -0.87828 + 0x3fde83e0eaf85113, 0xbfec20de3fa971b0, // 0.4768, -0.87901 + 0x3fde6dc704be97e2, 0xbfec26d9f01f2eaf, // 0.47545, -0.87974 + 0x3fde57a86d3cd824, 0xbfec2cd14931e3f1, // 0.4741, -0.88047 + 0x3fde418527dc4ffa, 0xbfec32c449f60831, // 0.47275, -0.8812 + 0x3fde2b5d3806f63b, 0xbfec38b2f180bdb1, // 0.4714, -0.88192 + 0x3fde1530a12779f4, 0xbfec3e9d3ee7d262, // 0.47004, -0.88264 + 0x3fddfeff66a941de, 0xbfec44833141c004, // 0.46869, -0.88336 + 0x3fdde8c98bf86bd6, 0xbfec4a64c7a5ac4c, // 0.46733, -0.88408 + 0x3fddd28f1481cc58, 0xbfec5042012b6907, // 0.46598, -0.8848 + 0x3fddbc5003b2edf8, 0xbfec561adceb743e, // 0.46462, -0.88551 + 0x3fdda60c5cfa10d8, 0xbfec5bef59fef85a, // 0.46326, -0.88622 + 0x3fdd8fc423c62a25, 0xbfec61bf777fcc48, // 0.4619, -0.88693 + 0x3fdd79775b86e389, 0xbfec678b3488739b, // 0.46054, -0.88764 + 0x3fdd632607ac9aa9, 0xbfec6d5290341eb2, // 0.45918, -0.88835 + 0x3fdd4cd02ba8609c, 0xbfec7315899eaad7, // 0.45781, -0.88905 + 0x3fdd3675caebf962, 0xbfec78d41fe4a267, // 0.45645, -0.88975 + 0x3fdd2016e8e9db5b, 0xbfec7e8e52233cf3, // 0.45508, -0.89045 + 0x3fdd09b389152ec1, 0xbfec84441f785f61, // 0.45372, -0.89115 + 0x3fdcf34baee1cd21, 0xbfec89f587029c13, // 0.45235, -0.89184 + 0x3fdcdcdf5dc440ce, 0xbfec8fa287e13305, // 0.45098, -0.89253 + 0x3fdcc66e9931c45d, 0xbfec954b213411f5, // 0.44961, -0.89322 + 0x3fdcaff964a0421d, 0xbfec9aef521bd480, // 0.44824, -0.89391 + 0x3fdc997fc3865388, 0xbfeca08f19b9c449, // 0.44687, -0.8946 + 0x3fdc8301b95b40c2, 0xbfeca62a772fd919, // 0.4455, -0.89528 + 0x3fdc6c7f4997000a, 0xbfecabc169a0b901, // 0.44412, -0.89597 + 0x3fdc55f877b23537, 0xbfecb153f02fb87d, // 0.44275, -0.89665 + 0x3fdc3f6d47263129, 0xbfecb6e20a00da99, // 0.44137, -0.89732 + 0x3fdc28ddbb6cf145, 0xbfecbc6bb638d10b, // 0.43999, -0.898 + 0x3fdc1249d8011ee7, 0xbfecc1f0f3fcfc5c, // 0.43862, -0.89867 + 0x3fdbfbb1a05e0edc, 0xbfecc771c2736c09, // 0.43724, -0.89935 + 0x3fdbe51517ffc0d9, 0xbfecccee20c2de9f, // 0.43586, -0.90002 + 0x3fdbce744262deee, 0xbfecd2660e12c1e6, // 0.43448, -0.90068 + 0x3fdbb7cf2304bd01, 0xbfecd7d9898b32f6, // 0.43309, -0.90135 + 0x3fdba125bd63583e, 0xbfecdd489254fe65, // 0.43171, -0.90201 + 0x3fdb8a7814fd5693, 0xbfece2b32799a060, // 0.43033, -0.90267 + 0x3fdb73c62d520624, 0xbfece819488344ce, // 0.42894, -0.90333 + 0x3fdb5d1009e15cc0, 0xbfeced7af43cc773, // 0.42756, -0.90399 + 0x3fdb4655ae2bf757, 0xbfecf2d829f1b40e, // 0.42617, -0.90464 + 0x3fdb2f971db31972, 0xbfecf830e8ce467b, // 0.42478, -0.9053 + 0x3fdb18d45bf8aca6, 0xbfecfd852fff6ad4, // 0.42339, -0.90595 + 0x3fdb020d6c7f4009, 0xbfed02d4feb2bd92, // 0.422, -0.9066 + 0x3fdaeb4252ca07ab, 0xbfed082054168bac, // 0.42061, -0.90724 + 0x3fdad473125cdc08, 0xbfed0d672f59d2b9, // 0.41922, -0.90789 + 0x3fdabd9faebc3980, 0xbfed12a98fac410c, // 0.41782, -0.90853 + 0x3fdaa6c82b6d3fc9, 0xbfed17e7743e35dc, // 0.41643, -0.90917 + 0x3fda8fec8bf5b166, 0xbfed1d20dc40c15c, // 0.41503, -0.90981 + 0x3fda790cd3dbf31a, 0xbfed2255c6e5a4e1, // 0.41364, -0.91044 + 0x3fda622906a70b63, 0xbfed2786335f52fc, // 0.41224, -0.91107 + 0x3fda4b4127dea1e4, 0xbfed2cb220e0ef9f, // 0.41084, -0.91171 + 0x3fda34553b0afee5, 0xbfed31d98e9e503a, // 0.40944, -0.91234 + 0x3fda1d6543b50ac0, 0xbfed36fc7bcbfbdc, // 0.40804, -0.91296 + 0x3fda067145664d57, 0xbfed3c1ae79f2b4e, // 0.40664, -0.91359 + 0x3fd9ef7943a8ed8a, 0xbfed4134d14dc93a, // 0.40524, -0.91421 + 0x3fd9d87d4207b0ab, 0xbfed464a380e7242, // 0.40384, -0.91483 + 0x3fd9c17d440df9f2, 0xbfed4b5b1b187524, // 0.40243, -0.91545 + 0x3fd9aa794d47c9ee, 0xbfed506779a3d2d9, // 0.40103, -0.91606 + 0x3fd993716141bdfe, 0xbfed556f52e93eb1, // 0.39962, -0.91668 + 0x3fd97c6583890fc2, 0xbfed5a72a6221e73, // 0.39822, -0.91729 + 0x3fd96555b7ab948f, 0xbfed5f7172888a7f, // 0.39681, -0.9179 + 0x3fd94e420137bce3, 0xbfed646bb7574de5, // 0.3954, -0.91851 + 0x3fd9372a63bc93d7, 0xbfed696173c9e68b, // 0.39399, -0.91911 + 0x3fd9200ee2c9be97, 0xbfed6e52a71c8547, // 0.39258, -0.91972 + 0x3fd908ef81ef7bd1, 0xbfed733f508c0dff, // 0.39117, -0.92032 + 0x3fd8f1cc44bea329, 0xbfed78276f5617c6, // 0.38976, -0.92092 + 0x3fd8daa52ec8a4af, 0xbfed7d0b02b8ecf9, // 0.38835, -0.92151 + 0x3fd8c37a439f884f, 0xbfed81ea09f38b63, // 0.38693, -0.92211 + 0x3fd8ac4b86d5ed44, 0xbfed86c48445a450, // 0.38552, -0.9227 + 0x3fd89518fbff098e, 0xbfed8b9a70ef9cb4, // 0.3841, -0.92329 + 0x3fd87de2a6aea963, 0xbfed906bcf328d46, // 0.38268, -0.92388 + 0x3fd866a88a792ea0, 0xbfed95389e50429b, // 0.38127, -0.92447 + 0x3fd84f6aaaf3903f, 0xbfed9a00dd8b3d46, // 0.37985, -0.92505 + 0x3fd838290bb359c8, 0xbfed9ec48c26b1f3, // 0.37843, -0.92563 + 0x3fd820e3b04eaac4, 0xbfeda383a9668988, // 0.37701, -0.92621 + 0x3fd8099a9c5c362d, 0xbfeda83e348f613b, // 0.37559, -0.92679 + 0x3fd7f24dd37341e3, 0xbfedacf42ce68ab9, // 0.37416, -0.92736 + 0x3fd7dafd592ba621, 0xbfedb1a591b20c38, // 0.37274, -0.92794 + 0x3fd7c3a9311dcce7, 0xbfedb6526238a09b, // 0.37132, -0.92851 + 0x3fd7ac515ee2b172, 0xbfedbafa9dc1b78d, // 0.36989, -0.92907 + 0x3fd794f5e613dfae, 0xbfedbf9e4395759a, // 0.36847, -0.92964 + 0x3fd77d96ca4b73a6, 0xbfedc43d52fcb453, // 0.36704, -0.93021 + 0x3fd766340f2418f6, 0xbfedc8d7cb410260, // 0.36561, -0.93077 + 0x3fd74ecdb8390a3e, 0xbfedcd6dabaca3a5, // 0.36418, -0.93133 + 0x3fd73763c9261092, 0xbfedd1fef38a915a, // 0.36276, -0.93188 + 0x3fd71ff6458782ec, 0xbfedd68ba2267a25, // 0.36133, -0.93244 + 0x3fd7088530fa459e, 0xbfeddb13b6ccc23d, // 0.3599, -0.93299 + 0x3fd6f1108f1bc9c5, 0xbfeddf9730ca837b, // 0.35846, -0.93354 + 0x3fd6d998638a0cb5, 0xbfede4160f6d8d81, // 0.35703, -0.93409 + 0x3fd6c21cb1e39771, 0xbfede890520465ce, // 0.3556, -0.93464 + 0x3fd6aa9d7dc77e16, 0xbfeded05f7de47da, // 0.35416, -0.93518 + 0x3fd6931acad55f51, 0xbfedf177004b2534, // 0.35273, -0.93573 + 0x3fd67b949cad63ca, 0xbfedf5e36a9ba59c, // 0.35129, -0.93627 + 0x3fd6640af6f03d9e, 0xbfedfa4b3621271d, // 0.34986, -0.9368 + 0x3fd64c7ddd3f27c6, 0xbfedfeae622dbe2b, // 0.34842, -0.93734 + 0x3fd634ed533be58e, 0xbfee030cee1435b8, // 0.34698, -0.93787 + 0x3fd61d595c88c203, 0xbfee0766d9280f54, // 0.34554, -0.9384 + 0x3fd605c1fcc88f63, 0xbfee0bbc22bd8349, // 0.3441, -0.93893 + 0x3fd5ee27379ea693, 0xbfee100cca2980ac, // 0.34266, -0.93946 + 0x3fd5d68910aee686, 0xbfee1458cec1ad83, // 0.34122, -0.93998 + 0x3fd5bee78b9db3b6, 0xbfee18a02fdc66d9, // 0.33978, -0.94051 + 0x3fd5a742ac0ff78d, 0xbfee1ce2ecd0c0d8, // 0.33833, -0.94103 + 0x3fd58f9a75ab1fdd, 0xbfee212104f686e5, // 0.33689, -0.94154 + 0x3fd577eeec151e47, 0xbfee255a77a63bb8, // 0.33545, -0.94206 + 0x3fd5604012f467b4, 0xbfee298f4439197a, // 0.334, -0.94257 + 0x3fd5488dedeff3be, 0xbfee2dbf6a0911d9, // 0.33255, -0.94308 + 0x3fd530d880af3c24, 0xbfee31eae870ce25, // 0.33111, -0.94359 + 0x3fd5191fceda3c35, 0xbfee3611becbaf69, // 0.32966, -0.9441 + 0x3fd50163dc197047, 0xbfee3a33ec75ce85, // 0.32821, -0.9446 + 0x3fd4e9a4ac15d520, 0xbfee3e5170cbfc46, // 0.32676, -0.94511 + 0x3fd4d1e24278e76a, 0xbfee426a4b2bc17e, // 0.32531, -0.94561 + 0x3fd4ba1ca2eca31c, 0xbfee467e7af35f23, // 0.32386, -0.94611 + 0x3fd4a253d11b82f3, 0xbfee4a8dff81ce5e, // 0.32241, -0.9466 + 0x3fd48a87d0b07fd7, 0xbfee4e98d836c0af, // 0.32096, -0.94709 + 0x3fd472b8a5571054, 0xbfee529f04729ffc, // 0.3195, -0.94759 + 0x3fd45ae652bb2800, 0xbfee56a083968eb1, // 0.31805, -0.94807 + 0x3fd44310dc8936f0, 0xbfee5a9d550467d3, // 0.31659, -0.94856 + 0x3fd42b38466e2928, 0xbfee5e95781ebf1c, // 0.31514, -0.94905 + 0x3fd4135c94176602, 0xbfee6288ec48e112, // 0.31368, -0.94953 + 0x3fd3fb7dc932cfa4, 0xbfee6677b0e6d31e, // 0.31222, -0.95001 + 0x3fd3e39be96ec271, 0xbfee6a61c55d53a7, // 0.31077, -0.95049 + 0x3fd3cbb6f87a146e, 0xbfee6e472911da27, // 0.30931, -0.95096 + 0x3fd3b3cefa0414b7, 0xbfee7227db6a9744, // 0.30785, -0.95144 + 0x3fd39be3f1bc8aef, 0xbfee7603dbce74e9, // 0.30639, -0.95191 + 0x3fd383f5e353b6aa, 0xbfee79db29a5165a, // 0.30493, -0.95238 + 0x3fd36c04d27a4edf, 0xbfee7dadc456d850, // 0.30347, -0.95284 + 0x3fd35410c2e18152, 0xbfee817bab4cd10d, // 0.30201, -0.95331 + 0x3fd33c19b83af207, 0xbfee8544ddf0d075, // 0.30054, -0.95377 + 0x3fd3241fb638baaf, 0xbfee89095bad6025, // 0.29908, -0.95423 + 0x3fd30c22c08d6a13, 0xbfee8cc923edc388, // 0.29762, -0.95469 + 0x3fd2f422daec0386, 0xbfee9084361df7f3, // 0.29615, -0.95514 + 0x3fd2dc200907fe51, 0xbfee943a91aab4b4, // 0.29469, -0.95559 + 0x3fd2c41a4e954520, 0xbfee97ec36016b30, // 0.29322, -0.95605 + 0x3fd2ac11af483572, 0xbfee9b99229046f8, // 0.29175, -0.95649 + 0x3fd294062ed59f05, 0xbfee9f4156c62dda, // 0.29028, -0.95694 + 0x3fd27bf7d0f2c346, 0xbfeea2e4d212c000, // 0.28882, -0.95738 + 0x3fd263e6995554ba, 0xbfeea68393e65800, // 0.28735, -0.95783 + 0x3fd24bd28bb37672, 0xbfeeaa1d9bb20af3, // 0.28588, -0.95827 + 0x3fd233bbabc3bb72, 0xbfeeadb2e8e7a88e, // 0.28441, -0.9587 + 0x3fd21ba1fd3d2623, 0xbfeeb1437af9bb34, // 0.28294, -0.95914 + 0x3fd2038583d727bd, 0xbfeeb4cf515b8811, // 0.28146, -0.95957 + 0x3fd1eb6643499fbb, 0xbfeeb8566b810f2a, // 0.27999, -0.96 + 0x3fd1d3443f4cdb3d, 0xbfeebbd8c8df0b74, // 0.27852, -0.96043 + 0x3fd1bb1f7b999480, 0xbfeebf5668eaf2ef, // 0.27705, -0.96086 + 0x3fd1a2f7fbe8f243, 0xbfeec2cf4b1af6b2, // 0.27557, -0.96128 + 0x3fd18acdc3f4873a, 0xbfeec6436ee60309, // 0.2741, -0.9617 + 0x3fd172a0d7765177, 0xbfeec9b2d3c3bf84, // 0.27262, -0.96212 + 0x3fd15a713a28b9d9, 0xbfeecd1d792c8f10, // 0.27115, -0.96254 + 0x3fd1423eefc69378, 0xbfeed0835e999009, // 0.26967, -0.96295 + 0x3fd12a09fc0b1b12, 0xbfeed3e483849c51, // 0.26819, -0.96337 + 0x3fd111d262b1f677, 0xbfeed740e7684963, // 0.26671, -0.96378 + 0x3fd0f998277733f7, 0xbfeeda9889bfe86a, // 0.26523, -0.96418 + 0x3fd0e15b4e1749cd, 0xbfeeddeb6a078651, // 0.26375, -0.96459 + 0x3fd0c91bda4f158d, 0xbfeee13987bbebdc, // 0.26227, -0.96499 + 0x3fd0b0d9cfdbdb90, 0xbfeee482e25a9dbc, // 0.26079, -0.96539 + 0x3fd09895327b465e, 0xbfeee7c77961dc9e, // 0.25931, -0.96579 + 0x3fd0804e05eb661e, 0xbfeeeb074c50a544, // 0.25783, -0.96619 + 0x3fd068044deab002, 0xbfeeee425aa6b09a, // 0.25635, -0.96658 + 0x3fd04fb80e37fdae, 0xbfeef178a3e473c2, // 0.25487, -0.96698 + 0x3fd037694a928cac, 0xbfeef4aa278b2032, // 0.25338, -0.96737 + 0x3fd01f1806b9fdd2, 0xbfeef7d6e51ca3c0, // 0.2519, -0.96775 + 0x3fd006c4466e54af, 0xbfeefafedc1ba8b7, // 0.25041, -0.96814 + 0x3fcfdcdc1adfedf8, 0xbfeefe220c0b95ec, // 0.24893, -0.96852 + 0x3fcfac2abeff57ff, 0xbfef014074708ed3, // 0.24744, -0.9689 + 0x3fcf7b7480bd3801, 0xbfef045a14cf738c, // 0.24596, -0.96928 + 0x3fcf4ab9679c9f5c, 0xbfef076eecade0fa, // 0.24447, -0.96966 + 0x3fcf19f97b215f1a, 0xbfef0a7efb9230d7, // 0.24298, -0.97003 + 0x3fcee934c2d006c7, 0xbfef0d8a410379c5, // 0.24149, -0.9704 + 0x3fceb86b462de348, 0xbfef1090bc898f5f, // 0.24, -0.97077 + 0x3fce879d0cc0fdaf, 0xbfef13926dad024e, // 0.23851, -0.97114 + 0x3fce56ca1e101a1b, 0xbfef168f53f7205d, // 0.23702, -0.9715 + 0x3fce25f281a2b684, 0xbfef19876ef1f486, // 0.23553, -0.97187 + 0x3fcdf5163f01099a, 0xbfef1c7abe284708, // 0.23404, -0.97223 + 0x3fcdc4355db40195, 0xbfef1f6941259d7a, // 0.23255, -0.97258 + 0x3fcd934fe5454311, 0xbfef2252f7763ada, // 0.23106, -0.97294 + 0x3fcd6265dd3f27e3, 0xbfef2537e0a71f9f, // 0.22957, -0.97329 + 0x3fcd31774d2cbdee, 0xbfef2817fc4609ce, // 0.22807, -0.97364 + 0x3fcd00843c99c5f9, 0xbfef2af349e17507, // 0.22658, -0.97399 + 0x3fcccf8cb312b286, 0xbfef2dc9c9089a9d, // 0.22508, -0.97434 + 0x3fcc9e90b824a6a9, 0xbfef309b794b719f, // 0.22359, -0.97468 + 0x3fcc6d90535d74dc, 0xbfef33685a3aaef0, // 0.22209, -0.97503 + 0x3fcc3c8b8c4b9dd7, 0xbfef36306b67c556, // 0.2206, -0.97536 + 0x3fcc0b826a7e4f63, 0xbfef38f3ac64e589, // 0.2191, -0.9757 + 0x3fcbda74f5856330, 0xbfef3bb21cc4fe47, // 0.2176, -0.97604 + 0x3fcba96334f15dad, 0xbfef3e6bbc1bbc65, // 0.21611, -0.97637 + 0x3fcb784d30536cda, 0xbfef412089fd8adc, // 0.21461, -0.9767 + 0x3fcb4732ef3d6722, 0xbfef43d085ff92dd, // 0.21311, -0.97703 + 0x3fcb16147941ca2a, 0xbfef467bafb7bbe0, // 0.21161, -0.97735 + 0x3fcae4f1d5f3b9ab, 0xbfef492206bcabb4, // 0.21011, -0.97768 + 0x3fcab3cb0ce6fe44, 0xbfef4bc38aa5c694, // 0.20861, -0.978 + 0x3fca82a025b00451, 0xbfef4e603b0b2f2d, // 0.20711, -0.97832 + 0x3fca517127e3dabc, 0xbfef50f81785c6b9, // 0.20561, -0.97863 + 0x3fca203e1b1831da, 0xbfef538b1faf2d07, // 0.20411, -0.97895 + 0x3fc9ef0706e35a35, 0xbfef56195321c090, // 0.20261, -0.97926 + 0x3fc9bdcbf2dc4366, 0xbfef58a2b1789e84, // 0.2011, -0.97957 + 0x3fc98c8ce69a7aec, 0xbfef5b273a4fa2d9, // 0.1996, -0.97988 + 0x3fc95b49e9b62af9, 0xbfef5da6ed43685d, // 0.1981, -0.98018 + 0x3fc92a0303c8194f, 0xbfef6021c9f148c2, // 0.19659, -0.98048 + 0x3fc8f8b83c69a60a, 0xbfef6297cff75cb0, // 0.19509, -0.98079 + 0x3fc8c7699b34ca7e, 0xbfef6508fef47bd5, // 0.19359, -0.98108 + 0x3fc8961727c41804, 0xbfef677556883cee, // 0.19208, -0.98138 + 0x3fc864c0e9b2b6cf, 0xbfef69dcd652f5de, // 0.19057, -0.98167 + 0x3fc83366e89c64c5, 0xbfef6c3f7df5bbb7, // 0.18907, -0.98196 + 0x3fc802092c1d744b, 0xbfef6e9d4d1262ca, // 0.18756, -0.98225 + 0x3fc7d0a7bbd2cb1b, 0xbfef70f6434b7eb7, // 0.18606, -0.98254 + 0x3fc79f429f59e11d, 0xbfef734a60446279, // 0.18455, -0.98282 + 0x3fc76dd9de50bf31, 0xbfef7599a3a12077, // 0.18304, -0.98311 + 0x3fc73c6d8055fe0a, 0xbfef77e40d068a90, // 0.18153, -0.98339 + 0x3fc70afd8d08c4ff, 0xbfef7a299c1a322a, // 0.18002, -0.98366 + 0x3fc6d98a0c08c8da, 0xbfef7c6a50826840, // 0.17851, -0.98394 + 0x3fc6a81304f64ab2, 0xbfef7ea629e63d6e, // 0.177, -0.98421 + 0x3fc676987f7216b8, 0xbfef80dd27ed8204, // 0.17549, -0.98448 + 0x3fc6451a831d830d, 0xbfef830f4a40c60c, // 0.17398, -0.98475 + 0x3fc61399179a6e94, 0xbfef853c9089595e, // 0.17247, -0.98501 + 0x3fc5e214448b3fc6, 0xbfef8764fa714ba9, // 0.17096, -0.98528 + 0x3fc5b08c1192e381, 0xbfef898887a36c84, // 0.16945, -0.98554 + 0x3fc57f008654cbde, 0xbfef8ba737cb4b78, // 0.16794, -0.9858 + 0x3fc54d71aa74ef02, 0xbfef8dc10a95380d, // 0.16643, -0.98605 + 0x3fc51bdf8597c5f2, 0xbfef8fd5ffae41db, // 0.16491, -0.98631 + 0x3fc4ea4a1f624b61, 0xbfef91e616c43891, // 0.1634, -0.98656 + 0x3fc4b8b17f79fa88, 0xbfef93f14f85ac08, // 0.16189, -0.98681 + 0x3fc48715ad84cdf5, 0xbfef95f7a9a1ec47, // 0.16037, -0.98706 + 0x3fc45576b1293e5a, 0xbfef97f924c9099b, // 0.15886, -0.9873 + 0x3fc423d4920e4166, 0xbfef99f5c0abd496, // 0.15734, -0.98754 + 0x3fc3f22f57db4893, 0xbfef9bed7cfbde29, // 0.15583, -0.98778 + 0x3fc3c0870a383ff6, 0xbfef9de0596b77a3, // 0.15431, -0.98802 + 0x3fc38edbb0cd8d14, 0xbfef9fce55adb2c8, // 0.1528, -0.98826 + 0x3fc35d2d53440db2, 0xbfefa1b7717661d5, // 0.15128, -0.98849 + 0x3fc32b7bf94516a7, 0xbfefa39bac7a1791, // 0.14976, -0.98872 + 0x3fc2f9c7aa7a72af, 0xbfefa57b066e2754, // 0.14825, -0.98895 + 0x3fc2c8106e8e613a, 0xbfefa7557f08a517, // 0.14673, -0.98918 + 0x3fc296564d2b953e, 0xbfefa92b1600657c, // 0.14521, -0.9894 + 0x3fc264994dfd340a, 0xbfefaafbcb0cfddc, // 0.1437, -0.98962 + 0x3fc232d978aed413, 0xbfefacc79de6c44f, // 0.14218, -0.98984 + 0x3fc20116d4ec7bce, 0xbfefae8e8e46cfbb, // 0.14066, -0.99006 + 0x3fc1cf516a62a077, 0xbfefb0509be6f7db, // 0.13914, -0.99027 + 0x3fc19d8940be24e7, 0xbfefb20dc681d54d, // 0.13762, -0.99049 + 0x3fc16bbe5fac5865, 0xbfefb3c60dd2c199, // 0.1361, -0.9907 + 0x3fc139f0cedaf576, 0xbfefb5797195d741, // 0.13458, -0.9909 + 0x3fc1082095f820b0, 0xbfefb727f187f1c7, // 0.13306, -0.99111 + 0x3fc0d64dbcb26786, 0xbfefb8d18d66adb7, // 0.13154, -0.99131 + 0x3fc0a4784ab8bf1d, 0xbfefba7644f068b5, // 0.13002, -0.99151 + 0x3fc072a047ba831d, 0xbfefbc1617e44186, // 0.1285, -0.99171 + 0x3fc040c5bb67747e, 0xbfefbdb106021816, // 0.12698, -0.99191 + 0x3fc00ee8ad6fb85b, 0xbfefbf470f0a8d88, // 0.12545, -0.9921 + 0x3fbfba124b07ad85, 0xbfefc0d832bf043a, // 0.12393, -0.99229 + 0x3fbf564e56a9730e, 0xbfefc26470e19fd3, // 0.12241, -0.99248 + 0x3fbef2858d27561b, 0xbfefc3ebc935454c, // 0.12089, -0.99267 + 0x3fbe8eb7fde4aa3e, 0xbfefc56e3b7d9af6, // 0.11937, -0.99285 + 0x3fbe2ae5b8457f77, 0xbfefc6ebc77f0887, // 0.11784, -0.99303 + 0x3fbdc70ecbae9fc8, 0xbfefc8646cfeb721, // 0.11632, -0.99321 + 0x3fbd633347858ce4, 0xbfefc9d82bc2915e, // 0.11479, -0.99339 + 0x3fbcff533b307dc1, 0xbfefcb4703914354, // 0.11327, -0.99356 + 0x3fbc9b6eb6165c42, 0xbfefccb0f4323aa3, // 0.11175, -0.99374 + 0x3fbc3785c79ec2d5, 0xbfefce15fd6da67b, // 0.11022, -0.99391 + 0x3fbbd3987f31fa0e, 0xbfefcf761f0c77a3, // 0.1087, -0.99407 + 0x3fbb6fa6ec38f64c, 0xbfefd0d158d86087, // 0.10717, -0.99424 + 0x3fbb0bb11e1d5559, 0xbfefd227aa9bd53b, // 0.10565, -0.9944 + 0x3fbaa7b724495c04, 0xbfefd37914220b84, // 0.10412, -0.99456 + 0x3fba43b90e27f3c4, 0xbfefd4c59536fae4, // 0.1026, -0.99472 + 0x3fb9dfb6eb24a85c, 0xbfefd60d2da75c9e, // 0.10107, -0.99488 + 0x3fb97bb0caaba56f, 0xbfefd74fdd40abbf, // 0.099544, -0.99503 + 0x3fb917a6bc29b42c, 0xbfefd88da3d12526, // 0.098017, -0.99518 + 0x3fb8b398cf0c38e0, 0xbfefd9c68127c78c, // 0.09649, -0.99533 + 0x3fb84f8712c130a0, 0xbfefdafa7514538c, // 0.094963, -0.99548 + 0x3fb7eb7196b72ee4, 0xbfefdc297f674ba9, // 0.093436, -0.99563 + 0x3fb787586a5d5b21, 0xbfefdd539ff1f456, // 0.091909, -0.99577 + 0x3fb7233b9d236e71, 0xbfefde78d68653fd, // 0.090381, -0.99591 + 0x3fb6bf1b3e79b129, 0xbfefdf9922f73307, // 0.088854, -0.99604 + 0x3fb65af75dd0f87b, 0xbfefe0b485181be3, // 0.087326, -0.99618 + 0x3fb5f6d00a9aa419, 0xbfefe1cafcbd5b09, // 0.085797, -0.99631 + 0x3fb592a554489bc8, 0xbfefe2dc89bbff08, // 0.084269, -0.99644 + 0x3fb52e774a4d4d0a, 0xbfefe3e92be9d886, // 0.08274, -0.99657 + 0x3fb4ca45fc1ba8b6, 0xbfefe4f0e31d7a4a, // 0.081211, -0.9967 + 0x3fb4661179272096, 0xbfefe5f3af2e3940, // 0.079682, -0.99682 + 0x3fb401d9d0e3a507, 0xbfefe6f18ff42c84, // 0.078153, -0.99694 + 0x3fb39d9f12c5a299, 0xbfefe7ea85482d60, // 0.076624, -0.99706 + 0x3fb339614e41ffa5, 0xbfefe8de8f03d75c, // 0.075094, -0.99718 + 0x3fb2d52092ce19f6, 0xbfefe9cdad01883a, // 0.073565, -0.99729 + 0x3fb270dcefdfc45b, 0xbfefeab7df1c6005, // 0.072035, -0.9974 + 0x3fb20c9674ed444c, 0xbfefeb9d2530410f, // 0.070505, -0.99751 + 0x3fb1a84d316d4f8a, 0xbfefec7d7f19cffc, // 0.068974, -0.99762 + 0x3fb1440134d709b2, 0xbfefed58ecb673c4, // 0.067444, -0.99772 + 0x3fb0dfb28ea201e6, 0xbfefee2f6de455ba, // 0.065913, -0.99783 + 0x3fb07b614e463064, 0xbfefef0102826191, // 0.064383, -0.99793 + 0x3fb0170d833bf421, 0xbfefefcdaa704562, // 0.062852, -0.99802 + 0x3faf656e79f820e0, 0xbfeff095658e71ad, // 0.061321, -0.99812 + 0x3fae9cbd15ff5527, 0xbfeff15833be1965, // 0.05979, -0.99821 + 0x3fadd406f9808ec8, 0xbfeff21614e131ed, // 0.058258, -0.9983 + 0x3fad0b4c436f91d0, 0xbfeff2cf08da7321, // 0.056727, -0.99839 + 0x3fac428d12c0d7e3, 0xbfeff3830f8d575c, // 0.055195, -0.99848 + 0x3fab79c986698b78, 0xbfeff43228de1b77, // 0.053664, -0.99856 + 0x3faab101bd5f8317, 0xbfeff4dc54b1bed3, // 0.052132, -0.99864 + 0x3fa9e835d6993c87, 0xbfeff58192ee0358, // 0.0506, -0.99872 + 0x3fa91f65f10dd814, 0xbfeff621e3796d7e, // 0.049068, -0.9988 + 0x3fa856922bb513c1, 0xbfeff6bd463b444d, // 0.047535, -0.99887 + 0x3fa78dbaa5874685, 0xbfeff753bb1b9164, // 0.046003, -0.99894 + 0x3fa6c4df7d7d5b84, 0xbfeff7e5420320f9, // 0.044471, -0.99901 + 0x3fa5fc00d290cd43, 0xbfeff871dadb81df, // 0.042938, -0.99908 + 0x3fa5331ec3bba0eb, 0xbfeff8f9858f058b, // 0.041406, -0.99914 + 0x3fa46a396ff86179, 0xbfeff97c4208c014, // 0.039873, -0.9992 + 0x3fa3a150f6421afc, 0xbfeff9fa10348837, // 0.03834, -0.99926 + 0x3fa2d865759455cd, 0xbfeffa72effef75d, // 0.036807, -0.99932 + 0x3fa20f770ceb11c6, 0xbfeffae6e1556998, // 0.035274, -0.99938 + 0x3fa14685db42c17e, 0xbfeffb55e425fdae, // 0.033741, -0.99943 + 0x3fa07d91ff984580, 0xbfeffbbff85f9515, // 0.032208, -0.99948 + 0x3f9f693731d1cf01, 0xbfeffc251df1d3f8, // 0.030675, -0.99953 + 0x3f9dd7458c64ab39, 0xbfeffc8554cd213a, // 0.029142, -0.99958 + 0x3f9c454f4ce53b1c, 0xbfeffce09ce2a679, // 0.027608, -0.99962 + 0x3f9ab354b1504fca, 0xbfeffd36f624500c, // 0.026075, -0.99966 + 0x3f992155f7a3667e, 0xbfeffd886084cd0d, // 0.024541, -0.9997 + 0x3f978f535ddc9f03, 0xbfeffdd4dbf78f52, // 0.023008, -0.99974 + 0x3f95fd4d21fab226, 0xbfeffe1c6870cb77, // 0.021474, -0.99977 + 0x3f946b4381fce81c, 0xbfeffe5f05e578db, // 0.01994, -0.9998 + 0x3f92d936bbe30efd, 0xbfeffe9cb44b51a1, // 0.018407, -0.99983 + 0x3f9147270dad7132, 0xbfeffed57398d2b7, // 0.016873, -0.99986 + 0x3f8f6a296ab997ca, 0xbfefff0943c53bd1, // 0.015339, -0.99988 + 0x3f8c45ffe1e48ad9, 0xbfefff3824c88f6f, // 0.013805, -0.9999 + 0x3f8921d1fcdec784, 0xbfefff62169b92db, // 0.012272, -0.99992 + 0x3f85fda037ac05e0, 0xbfefff871937ce2f, // 0.010738, -0.99994 + 0x3f82d96b0e509703, 0xbfefffa72c978c4f, //0.0092038, -0.99996 + 0x3f7f6a65f9a2a3c5, 0xbfefffc250b5daef, //0.0076698, -0.99997 + 0x3f7921f0fe670071, 0xbfefffd8858e8a92, //0.0061359, -0.99998 + 0x3f72d97822f996bc, 0xbfefffe9cb1e2e8d, //0.0046019, -0.99999 + 0x3f6921f8becca4ba, 0xbfeffff621621d02, // 0.003068, -1 + 0x3f5921faaee6472d, 0xbfeffffd88586ee6, // 0.001534, -1 +}; + +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float32_t twiddleCoef_rfft_32[32] = { + 0.000000000f, 1.000000000f, + 0.195090322f, 0.980785280f, + 0.382683432f, 0.923879533f, + 0.555570233f, 0.831469612f, + 0.707106781f, 0.707106781f, + 0.831469612f, 0.555570233f, + 0.923879533f, 0.382683432f, + 0.980785280f, 0.195090322f, + 1.000000000f, 0.000000000f, + 0.980785280f, -0.195090322f, + 0.923879533f, -0.382683432f, + 0.831469612f, -0.555570233f, + 0.707106781f, -0.707106781f, + 0.555570233f, -0.831469612f, + 0.382683432f, -0.923879533f, + 0.195090322f, -0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) +const float32_t twiddleCoef_rfft_64[64] = { + 0.000000000000000f, 1.000000000000000f, + 0.098017140329561f, 0.995184726672197f, + 0.195090322016128f, 0.980785280403230f, + 0.290284677254462f, 0.956940335732209f, + 0.382683432365090f, 0.923879532511287f, + 0.471396736825998f, 0.881921264348355f, + 0.555570233019602f, 0.831469612302545f, + 0.634393284163645f, 0.773010453362737f, + 0.707106781186547f, 0.707106781186548f, + 0.773010453362737f, 0.634393284163645f, + 0.831469612302545f, 0.555570233019602f, + 0.881921264348355f, 0.471396736825998f, + 0.923879532511287f, 0.382683432365090f, + 0.956940335732209f, 0.290284677254462f, + 0.980785280403230f, 0.195090322016128f, + 0.995184726672197f, 0.098017140329561f, + 1.000000000000000f, 0.000000000000000f, + 0.995184726672197f, -0.098017140329561f, + 0.980785280403230f, -0.195090322016128f, + 0.956940335732209f, -0.290284677254462f, + 0.923879532511287f, -0.382683432365090f, + 0.881921264348355f, -0.471396736825998f, + 0.831469612302545f, -0.555570233019602f, + 0.773010453362737f, -0.634393284163645f, + 0.707106781186548f, -0.707106781186547f, + 0.634393284163645f, -0.773010453362737f, + 0.555570233019602f, -0.831469612302545f, + 0.471396736825998f, -0.881921264348355f, + 0.382683432365090f, -0.923879532511287f, + 0.290284677254462f, -0.956940335732209f, + 0.195090322016129f, -0.980785280403230f, + 0.098017140329561f, -0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) +const float32_t twiddleCoef_rfft_128[128] = { + 0.000000000f, 1.000000000f, + 0.049067674f, 0.998795456f, + 0.098017140f, 0.995184727f, + 0.146730474f, 0.989176510f, + 0.195090322f, 0.980785280f, + 0.242980180f, 0.970031253f, + 0.290284677f, 0.956940336f, + 0.336889853f, 0.941544065f, + 0.382683432f, 0.923879533f, + 0.427555093f, 0.903989293f, + 0.471396737f, 0.881921264f, + 0.514102744f, 0.857728610f, + 0.555570233f, 0.831469612f, + 0.595699304f, 0.803207531f, + 0.634393284f, 0.773010453f, + 0.671558955f, 0.740951125f, + 0.707106781f, 0.707106781f, + 0.740951125f, 0.671558955f, + 0.773010453f, 0.634393284f, + 0.803207531f, 0.595699304f, + 0.831469612f, 0.555570233f, + 0.857728610f, 0.514102744f, + 0.881921264f, 0.471396737f, + 0.903989293f, 0.427555093f, + 0.923879533f, 0.382683432f, + 0.941544065f, 0.336889853f, + 0.956940336f, 0.290284677f, + 0.970031253f, 0.242980180f, + 0.980785280f, 0.195090322f, + 0.989176510f, 0.146730474f, + 0.995184727f, 0.098017140f, + 0.998795456f, 0.049067674f, + 1.000000000f, 0.000000000f, + 0.998795456f, -0.049067674f, + 0.995184727f, -0.098017140f, + 0.989176510f, -0.146730474f, + 0.980785280f, -0.195090322f, + 0.970031253f, -0.242980180f, + 0.956940336f, -0.290284677f, + 0.941544065f, -0.336889853f, + 0.923879533f, -0.382683432f, + 0.903989293f, -0.427555093f, + 0.881921264f, -0.471396737f, + 0.857728610f, -0.514102744f, + 0.831469612f, -0.555570233f, + 0.803207531f, -0.595699304f, + 0.773010453f, -0.634393284f, + 0.740951125f, -0.671558955f, + 0.707106781f, -0.707106781f, + 0.671558955f, -0.740951125f, + 0.634393284f, -0.773010453f, + 0.595699304f, -0.803207531f, + 0.555570233f, -0.831469612f, + 0.514102744f, -0.857728610f, + 0.471396737f, -0.881921264f, + 0.427555093f, -0.903989293f, + 0.382683432f, -0.923879533f, + 0.336889853f, -0.941544065f, + 0.290284677f, -0.956940336f, + 0.242980180f, -0.970031253f, + 0.195090322f, -0.980785280f, + 0.146730474f, -0.989176510f, + 0.098017140f, -0.995184727f, + 0.049067674f, -0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) +const float32_t twiddleCoef_rfft_256[256] = { + 0.000000000f, 1.000000000f, + 0.024541229f, 0.999698819f, + 0.049067674f, 0.998795456f, + 0.073564564f, 0.997290457f, + 0.098017140f, 0.995184727f, + 0.122410675f, 0.992479535f, + 0.146730474f, 0.989176510f, + 0.170961889f, 0.985277642f, + 0.195090322f, 0.980785280f, + 0.219101240f, 0.975702130f, + 0.242980180f, 0.970031253f, + 0.266712757f, 0.963776066f, + 0.290284677f, 0.956940336f, + 0.313681740f, 0.949528181f, + 0.336889853f, 0.941544065f, + 0.359895037f, 0.932992799f, + 0.382683432f, 0.923879533f, + 0.405241314f, 0.914209756f, + 0.427555093f, 0.903989293f, + 0.449611330f, 0.893224301f, + 0.471396737f, 0.881921264f, + 0.492898192f, 0.870086991f, + 0.514102744f, 0.857728610f, + 0.534997620f, 0.844853565f, + 0.555570233f, 0.831469612f, + 0.575808191f, 0.817584813f, + 0.595699304f, 0.803207531f, + 0.615231591f, 0.788346428f, + 0.634393284f, 0.773010453f, + 0.653172843f, 0.757208847f, + 0.671558955f, 0.740951125f, + 0.689540545f, 0.724247083f, + 0.707106781f, 0.707106781f, + 0.724247083f, 0.689540545f, + 0.740951125f, 0.671558955f, + 0.757208847f, 0.653172843f, + 0.773010453f, 0.634393284f, + 0.788346428f, 0.615231591f, + 0.803207531f, 0.595699304f, + 0.817584813f, 0.575808191f, + 0.831469612f, 0.555570233f, + 0.844853565f, 0.534997620f, + 0.857728610f, 0.514102744f, + 0.870086991f, 0.492898192f, + 0.881921264f, 0.471396737f, + 0.893224301f, 0.449611330f, + 0.903989293f, 0.427555093f, + 0.914209756f, 0.405241314f, + 0.923879533f, 0.382683432f, + 0.932992799f, 0.359895037f, + 0.941544065f, 0.336889853f, + 0.949528181f, 0.313681740f, + 0.956940336f, 0.290284677f, + 0.963776066f, 0.266712757f, + 0.970031253f, 0.242980180f, + 0.975702130f, 0.219101240f, + 0.980785280f, 0.195090322f, + 0.985277642f, 0.170961889f, + 0.989176510f, 0.146730474f, + 0.992479535f, 0.122410675f, + 0.995184727f, 0.098017140f, + 0.997290457f, 0.073564564f, + 0.998795456f, 0.049067674f, + 0.999698819f, 0.024541229f, + 1.000000000f, 0.000000000f, + 0.999698819f, -0.024541229f, + 0.998795456f, -0.049067674f, + 0.997290457f, -0.073564564f, + 0.995184727f, -0.098017140f, + 0.992479535f, -0.122410675f, + 0.989176510f, -0.146730474f, + 0.985277642f, -0.170961889f, + 0.980785280f, -0.195090322f, + 0.975702130f, -0.219101240f, + 0.970031253f, -0.242980180f, + 0.963776066f, -0.266712757f, + 0.956940336f, -0.290284677f, + 0.949528181f, -0.313681740f, + 0.941544065f, -0.336889853f, + 0.932992799f, -0.359895037f, + 0.923879533f, -0.382683432f, + 0.914209756f, -0.405241314f, + 0.903989293f, -0.427555093f, + 0.893224301f, -0.449611330f, + 0.881921264f, -0.471396737f, + 0.870086991f, -0.492898192f, + 0.857728610f, -0.514102744f, + 0.844853565f, -0.534997620f, + 0.831469612f, -0.555570233f, + 0.817584813f, -0.575808191f, + 0.803207531f, -0.595699304f, + 0.788346428f, -0.615231591f, + 0.773010453f, -0.634393284f, + 0.757208847f, -0.653172843f, + 0.740951125f, -0.671558955f, + 0.724247083f, -0.689540545f, + 0.707106781f, -0.707106781f, + 0.689540545f, -0.724247083f, + 0.671558955f, -0.740951125f, + 0.653172843f, -0.757208847f, + 0.634393284f, -0.773010453f, + 0.615231591f, -0.788346428f, + 0.595699304f, -0.803207531f, + 0.575808191f, -0.817584813f, + 0.555570233f, -0.831469612f, + 0.534997620f, -0.844853565f, + 0.514102744f, -0.857728610f, + 0.492898192f, -0.870086991f, + 0.471396737f, -0.881921264f, + 0.449611330f, -0.893224301f, + 0.427555093f, -0.903989293f, + 0.405241314f, -0.914209756f, + 0.382683432f, -0.923879533f, + 0.359895037f, -0.932992799f, + 0.336889853f, -0.941544065f, + 0.313681740f, -0.949528181f, + 0.290284677f, -0.956940336f, + 0.266712757f, -0.963776066f, + 0.242980180f, -0.970031253f, + 0.219101240f, -0.975702130f, + 0.195090322f, -0.980785280f, + 0.170961889f, -0.985277642f, + 0.146730474f, -0.989176510f, + 0.122410675f, -0.992479535f, + 0.098017140f, -0.995184727f, + 0.073564564f, -0.997290457f, + 0.049067674f, -0.998795456f, + 0.024541229f, -0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) +const float32_t twiddleCoef_rfft_512[512] = { + 0.000000000f, 1.000000000f, + 0.012271538f, 0.999924702f, + 0.024541229f, 0.999698819f, + 0.036807223f, 0.999322385f, + 0.049067674f, 0.998795456f, + 0.061320736f, 0.998118113f, + 0.073564564f, 0.997290457f, + 0.085797312f, 0.996312612f, + 0.098017140f, 0.995184727f, + 0.110222207f, 0.993906970f, + 0.122410675f, 0.992479535f, + 0.134580709f, 0.990902635f, + 0.146730474f, 0.989176510f, + 0.158858143f, 0.987301418f, + 0.170961889f, 0.985277642f, + 0.183039888f, 0.983105487f, + 0.195090322f, 0.980785280f, + 0.207111376f, 0.978317371f, + 0.219101240f, 0.975702130f, + 0.231058108f, 0.972939952f, + 0.242980180f, 0.970031253f, + 0.254865660f, 0.966976471f, + 0.266712757f, 0.963776066f, + 0.278519689f, 0.960430519f, + 0.290284677f, 0.956940336f, + 0.302005949f, 0.953306040f, + 0.313681740f, 0.949528181f, + 0.325310292f, 0.945607325f, + 0.336889853f, 0.941544065f, + 0.348418680f, 0.937339012f, + 0.359895037f, 0.932992799f, + 0.371317194f, 0.928506080f, + 0.382683432f, 0.923879533f, + 0.393992040f, 0.919113852f, + 0.405241314f, 0.914209756f, + 0.416429560f, 0.909167983f, + 0.427555093f, 0.903989293f, + 0.438616239f, 0.898674466f, + 0.449611330f, 0.893224301f, + 0.460538711f, 0.887639620f, + 0.471396737f, 0.881921264f, + 0.482183772f, 0.876070094f, + 0.492898192f, 0.870086991f, + 0.503538384f, 0.863972856f, + 0.514102744f, 0.857728610f, + 0.524589683f, 0.851355193f, + 0.534997620f, 0.844853565f, + 0.545324988f, 0.838224706f, + 0.555570233f, 0.831469612f, + 0.565731811f, 0.824589303f, + 0.575808191f, 0.817584813f, + 0.585797857f, 0.810457198f, + 0.595699304f, 0.803207531f, + 0.605511041f, 0.795836905f, + 0.615231591f, 0.788346428f, + 0.624859488f, 0.780737229f, + 0.634393284f, 0.773010453f, + 0.643831543f, 0.765167266f, + 0.653172843f, 0.757208847f, + 0.662415778f, 0.749136395f, + 0.671558955f, 0.740951125f, + 0.680600998f, 0.732654272f, + 0.689540545f, 0.724247083f, + 0.698376249f, 0.715730825f, + 0.707106781f, 0.707106781f, + 0.715730825f, 0.698376249f, + 0.724247083f, 0.689540545f, + 0.732654272f, 0.680600998f, + 0.740951125f, 0.671558955f, + 0.749136395f, 0.662415778f, + 0.757208847f, 0.653172843f, + 0.765167266f, 0.643831543f, + 0.773010453f, 0.634393284f, + 0.780737229f, 0.624859488f, + 0.788346428f, 0.615231591f, + 0.795836905f, 0.605511041f, + 0.803207531f, 0.595699304f, + 0.810457198f, 0.585797857f, + 0.817584813f, 0.575808191f, + 0.824589303f, 0.565731811f, + 0.831469612f, 0.555570233f, + 0.838224706f, 0.545324988f, + 0.844853565f, 0.534997620f, + 0.851355193f, 0.524589683f, + 0.857728610f, 0.514102744f, + 0.863972856f, 0.503538384f, + 0.870086991f, 0.492898192f, + 0.876070094f, 0.482183772f, + 0.881921264f, 0.471396737f, + 0.887639620f, 0.460538711f, + 0.893224301f, 0.449611330f, + 0.898674466f, 0.438616239f, + 0.903989293f, 0.427555093f, + 0.909167983f, 0.416429560f, + 0.914209756f, 0.405241314f, + 0.919113852f, 0.393992040f, + 0.923879533f, 0.382683432f, + 0.928506080f, 0.371317194f, + 0.932992799f, 0.359895037f, + 0.937339012f, 0.348418680f, + 0.941544065f, 0.336889853f, + 0.945607325f, 0.325310292f, + 0.949528181f, 0.313681740f, + 0.953306040f, 0.302005949f, + 0.956940336f, 0.290284677f, + 0.960430519f, 0.278519689f, + 0.963776066f, 0.266712757f, + 0.966976471f, 0.254865660f, + 0.970031253f, 0.242980180f, + 0.972939952f, 0.231058108f, + 0.975702130f, 0.219101240f, + 0.978317371f, 0.207111376f, + 0.980785280f, 0.195090322f, + 0.983105487f, 0.183039888f, + 0.985277642f, 0.170961889f, + 0.987301418f, 0.158858143f, + 0.989176510f, 0.146730474f, + 0.990902635f, 0.134580709f, + 0.992479535f, 0.122410675f, + 0.993906970f, 0.110222207f, + 0.995184727f, 0.098017140f, + 0.996312612f, 0.085797312f, + 0.997290457f, 0.073564564f, + 0.998118113f, 0.061320736f, + 0.998795456f, 0.049067674f, + 0.999322385f, 0.036807223f, + 0.999698819f, 0.024541229f, + 0.999924702f, 0.012271538f, + 1.000000000f, 0.000000000f, + 0.999924702f, -0.012271538f, + 0.999698819f, -0.024541229f, + 0.999322385f, -0.036807223f, + 0.998795456f, -0.049067674f, + 0.998118113f, -0.061320736f, + 0.997290457f, -0.073564564f, + 0.996312612f, -0.085797312f, + 0.995184727f, -0.098017140f, + 0.993906970f, -0.110222207f, + 0.992479535f, -0.122410675f, + 0.990902635f, -0.134580709f, + 0.989176510f, -0.146730474f, + 0.987301418f, -0.158858143f, + 0.985277642f, -0.170961889f, + 0.983105487f, -0.183039888f, + 0.980785280f, -0.195090322f, + 0.978317371f, -0.207111376f, + 0.975702130f, -0.219101240f, + 0.972939952f, -0.231058108f, + 0.970031253f, -0.242980180f, + 0.966976471f, -0.254865660f, + 0.963776066f, -0.266712757f, + 0.960430519f, -0.278519689f, + 0.956940336f, -0.290284677f, + 0.953306040f, -0.302005949f, + 0.949528181f, -0.313681740f, + 0.945607325f, -0.325310292f, + 0.941544065f, -0.336889853f, + 0.937339012f, -0.348418680f, + 0.932992799f, -0.359895037f, + 0.928506080f, -0.371317194f, + 0.923879533f, -0.382683432f, + 0.919113852f, -0.393992040f, + 0.914209756f, -0.405241314f, + 0.909167983f, -0.416429560f, + 0.903989293f, -0.427555093f, + 0.898674466f, -0.438616239f, + 0.893224301f, -0.449611330f, + 0.887639620f, -0.460538711f, + 0.881921264f, -0.471396737f, + 0.876070094f, -0.482183772f, + 0.870086991f, -0.492898192f, + 0.863972856f, -0.503538384f, + 0.857728610f, -0.514102744f, + 0.851355193f, -0.524589683f, + 0.844853565f, -0.534997620f, + 0.838224706f, -0.545324988f, + 0.831469612f, -0.555570233f, + 0.824589303f, -0.565731811f, + 0.817584813f, -0.575808191f, + 0.810457198f, -0.585797857f, + 0.803207531f, -0.595699304f, + 0.795836905f, -0.605511041f, + 0.788346428f, -0.615231591f, + 0.780737229f, -0.624859488f, + 0.773010453f, -0.634393284f, + 0.765167266f, -0.643831543f, + 0.757208847f, -0.653172843f, + 0.749136395f, -0.662415778f, + 0.740951125f, -0.671558955f, + 0.732654272f, -0.680600998f, + 0.724247083f, -0.689540545f, + 0.715730825f, -0.698376249f, + 0.707106781f, -0.707106781f, + 0.698376249f, -0.715730825f, + 0.689540545f, -0.724247083f, + 0.680600998f, -0.732654272f, + 0.671558955f, -0.740951125f, + 0.662415778f, -0.749136395f, + 0.653172843f, -0.757208847f, + 0.643831543f, -0.765167266f, + 0.634393284f, -0.773010453f, + 0.624859488f, -0.780737229f, + 0.615231591f, -0.788346428f, + 0.605511041f, -0.795836905f, + 0.595699304f, -0.803207531f, + 0.585797857f, -0.810457198f, + 0.575808191f, -0.817584813f, + 0.565731811f, -0.824589303f, + 0.555570233f, -0.831469612f, + 0.545324988f, -0.838224706f, + 0.534997620f, -0.844853565f, + 0.524589683f, -0.851355193f, + 0.514102744f, -0.857728610f, + 0.503538384f, -0.863972856f, + 0.492898192f, -0.870086991f, + 0.482183772f, -0.876070094f, + 0.471396737f, -0.881921264f, + 0.460538711f, -0.887639620f, + 0.449611330f, -0.893224301f, + 0.438616239f, -0.898674466f, + 0.427555093f, -0.903989293f, + 0.416429560f, -0.909167983f, + 0.405241314f, -0.914209756f, + 0.393992040f, -0.919113852f, + 0.382683432f, -0.923879533f, + 0.371317194f, -0.928506080f, + 0.359895037f, -0.932992799f, + 0.348418680f, -0.937339012f, + 0.336889853f, -0.941544065f, + 0.325310292f, -0.945607325f, + 0.313681740f, -0.949528181f, + 0.302005949f, -0.953306040f, + 0.290284677f, -0.956940336f, + 0.278519689f, -0.960430519f, + 0.266712757f, -0.963776066f, + 0.254865660f, -0.966976471f, + 0.242980180f, -0.970031253f, + 0.231058108f, -0.972939952f, + 0.219101240f, -0.975702130f, + 0.207111376f, -0.978317371f, + 0.195090322f, -0.980785280f, + 0.183039888f, -0.983105487f, + 0.170961889f, -0.985277642f, + 0.158858143f, -0.987301418f, + 0.146730474f, -0.989176510f, + 0.134580709f, -0.990902635f, + 0.122410675f, -0.992479535f, + 0.110222207f, -0.993906970f, + 0.098017140f, -0.995184727f, + 0.085797312f, -0.996312612f, + 0.073564564f, -0.997290457f, + 0.061320736f, -0.998118113f, + 0.049067674f, -0.998795456f, + 0.036807223f, -0.999322385f, + 0.024541229f, -0.999698819f, + 0.012271538f, -0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) +const float32_t twiddleCoef_rfft_1024[1024] = { + 0.000000000f, 1.000000000f, + 0.006135885f, 0.999981175f, + 0.012271538f, 0.999924702f, + 0.018406730f, 0.999830582f, + 0.024541229f, 0.999698819f, + 0.030674803f, 0.999529418f, + 0.036807223f, 0.999322385f, + 0.042938257f, 0.999077728f, + 0.049067674f, 0.998795456f, + 0.055195244f, 0.998475581f, + 0.061320736f, 0.998118113f, + 0.067443920f, 0.997723067f, + 0.073564564f, 0.997290457f, + 0.079682438f, 0.996820299f, + 0.085797312f, 0.996312612f, + 0.091908956f, 0.995767414f, + 0.098017140f, 0.995184727f, + 0.104121634f, 0.994564571f, + 0.110222207f, 0.993906970f, + 0.116318631f, 0.993211949f, + 0.122410675f, 0.992479535f, + 0.128498111f, 0.991709754f, + 0.134580709f, 0.990902635f, + 0.140658239f, 0.990058210f, + 0.146730474f, 0.989176510f, + 0.152797185f, 0.988257568f, + 0.158858143f, 0.987301418f, + 0.164913120f, 0.986308097f, + 0.170961889f, 0.985277642f, + 0.177004220f, 0.984210092f, + 0.183039888f, 0.983105487f, + 0.189068664f, 0.981963869f, + 0.195090322f, 0.980785280f, + 0.201104635f, 0.979569766f, + 0.207111376f, 0.978317371f, + 0.213110320f, 0.977028143f, + 0.219101240f, 0.975702130f, + 0.225083911f, 0.974339383f, + 0.231058108f, 0.972939952f, + 0.237023606f, 0.971503891f, + 0.242980180f, 0.970031253f, + 0.248927606f, 0.968522094f, + 0.254865660f, 0.966976471f, + 0.260794118f, 0.965394442f, + 0.266712757f, 0.963776066f, + 0.272621355f, 0.962121404f, + 0.278519689f, 0.960430519f, + 0.284407537f, 0.958703475f, + 0.290284677f, 0.956940336f, + 0.296150888f, 0.955141168f, + 0.302005949f, 0.953306040f, + 0.307849640f, 0.951435021f, + 0.313681740f, 0.949528181f, + 0.319502031f, 0.947585591f, + 0.325310292f, 0.945607325f, + 0.331106306f, 0.943593458f, + 0.336889853f, 0.941544065f, + 0.342660717f, 0.939459224f, + 0.348418680f, 0.937339012f, + 0.354163525f, 0.935183510f, + 0.359895037f, 0.932992799f, + 0.365612998f, 0.930766961f, + 0.371317194f, 0.928506080f, + 0.377007410f, 0.926210242f, + 0.382683432f, 0.923879533f, + 0.388345047f, 0.921514039f, + 0.393992040f, 0.919113852f, + 0.399624200f, 0.916679060f, + 0.405241314f, 0.914209756f, + 0.410843171f, 0.911706032f, + 0.416429560f, 0.909167983f, + 0.422000271f, 0.906595705f, + 0.427555093f, 0.903989293f, + 0.433093819f, 0.901348847f, + 0.438616239f, 0.898674466f, + 0.444122145f, 0.895966250f, + 0.449611330f, 0.893224301f, + 0.455083587f, 0.890448723f, + 0.460538711f, 0.887639620f, + 0.465976496f, 0.884797098f, + 0.471396737f, 0.881921264f, + 0.476799230f, 0.879012226f, + 0.482183772f, 0.876070094f, + 0.487550160f, 0.873094978f, + 0.492898192f, 0.870086991f, + 0.498227667f, 0.867046246f, + 0.503538384f, 0.863972856f, + 0.508830143f, 0.860866939f, + 0.514102744f, 0.857728610f, + 0.519355990f, 0.854557988f, + 0.524589683f, 0.851355193f, + 0.529803625f, 0.848120345f, + 0.534997620f, 0.844853565f, + 0.540171473f, 0.841554977f, + 0.545324988f, 0.838224706f, + 0.550457973f, 0.834862875f, + 0.555570233f, 0.831469612f, + 0.560661576f, 0.828045045f, + 0.565731811f, 0.824589303f, + 0.570780746f, 0.821102515f, + 0.575808191f, 0.817584813f, + 0.580813958f, 0.814036330f, + 0.585797857f, 0.810457198f, + 0.590759702f, 0.806847554f, + 0.595699304f, 0.803207531f, + 0.600616479f, 0.799537269f, + 0.605511041f, 0.795836905f, + 0.610382806f, 0.792106577f, + 0.615231591f, 0.788346428f, + 0.620057212f, 0.784556597f, + 0.624859488f, 0.780737229f, + 0.629638239f, 0.776888466f, + 0.634393284f, 0.773010453f, + 0.639124445f, 0.769103338f, + 0.643831543f, 0.765167266f, + 0.648514401f, 0.761202385f, + 0.653172843f, 0.757208847f, + 0.657806693f, 0.753186799f, + 0.662415778f, 0.749136395f, + 0.666999922f, 0.745057785f, + 0.671558955f, 0.740951125f, + 0.676092704f, 0.736816569f, + 0.680600998f, 0.732654272f, + 0.685083668f, 0.728464390f, + 0.689540545f, 0.724247083f, + 0.693971461f, 0.720002508f, + 0.698376249f, 0.715730825f, + 0.702754744f, 0.711432196f, + 0.707106781f, 0.707106781f, + 0.711432196f, 0.702754744f, + 0.715730825f, 0.698376249f, + 0.720002508f, 0.693971461f, + 0.724247083f, 0.689540545f, + 0.728464390f, 0.685083668f, + 0.732654272f, 0.680600998f, + 0.736816569f, 0.676092704f, + 0.740951125f, 0.671558955f, + 0.745057785f, 0.666999922f, + 0.749136395f, 0.662415778f, + 0.753186799f, 0.657806693f, + 0.757208847f, 0.653172843f, + 0.761202385f, 0.648514401f, + 0.765167266f, 0.643831543f, + 0.769103338f, 0.639124445f, + 0.773010453f, 0.634393284f, + 0.776888466f, 0.629638239f, + 0.780737229f, 0.624859488f, + 0.784556597f, 0.620057212f, + 0.788346428f, 0.615231591f, + 0.792106577f, 0.610382806f, + 0.795836905f, 0.605511041f, + 0.799537269f, 0.600616479f, + 0.803207531f, 0.595699304f, + 0.806847554f, 0.590759702f, + 0.810457198f, 0.585797857f, + 0.814036330f, 0.580813958f, + 0.817584813f, 0.575808191f, + 0.821102515f, 0.570780746f, + 0.824589303f, 0.565731811f, + 0.828045045f, 0.560661576f, + 0.831469612f, 0.555570233f, + 0.834862875f, 0.550457973f, + 0.838224706f, 0.545324988f, + 0.841554977f, 0.540171473f, + 0.844853565f, 0.534997620f, + 0.848120345f, 0.529803625f, + 0.851355193f, 0.524589683f, + 0.854557988f, 0.519355990f, + 0.857728610f, 0.514102744f, + 0.860866939f, 0.508830143f, + 0.863972856f, 0.503538384f, + 0.867046246f, 0.498227667f, + 0.870086991f, 0.492898192f, + 0.873094978f, 0.487550160f, + 0.876070094f, 0.482183772f, + 0.879012226f, 0.476799230f, + 0.881921264f, 0.471396737f, + 0.884797098f, 0.465976496f, + 0.887639620f, 0.460538711f, + 0.890448723f, 0.455083587f, + 0.893224301f, 0.449611330f, + 0.895966250f, 0.444122145f, + 0.898674466f, 0.438616239f, + 0.901348847f, 0.433093819f, + 0.903989293f, 0.427555093f, + 0.906595705f, 0.422000271f, + 0.909167983f, 0.416429560f, + 0.911706032f, 0.410843171f, + 0.914209756f, 0.405241314f, + 0.916679060f, 0.399624200f, + 0.919113852f, 0.393992040f, + 0.921514039f, 0.388345047f, + 0.923879533f, 0.382683432f, + 0.926210242f, 0.377007410f, + 0.928506080f, 0.371317194f, + 0.930766961f, 0.365612998f, + 0.932992799f, 0.359895037f, + 0.935183510f, 0.354163525f, + 0.937339012f, 0.348418680f, + 0.939459224f, 0.342660717f, + 0.941544065f, 0.336889853f, + 0.943593458f, 0.331106306f, + 0.945607325f, 0.325310292f, + 0.947585591f, 0.319502031f, + 0.949528181f, 0.313681740f, + 0.951435021f, 0.307849640f, + 0.953306040f, 0.302005949f, + 0.955141168f, 0.296150888f, + 0.956940336f, 0.290284677f, + 0.958703475f, 0.284407537f, + 0.960430519f, 0.278519689f, + 0.962121404f, 0.272621355f, + 0.963776066f, 0.266712757f, + 0.965394442f, 0.260794118f, + 0.966976471f, 0.254865660f, + 0.968522094f, 0.248927606f, + 0.970031253f, 0.242980180f, + 0.971503891f, 0.237023606f, + 0.972939952f, 0.231058108f, + 0.974339383f, 0.225083911f, + 0.975702130f, 0.219101240f, + 0.977028143f, 0.213110320f, + 0.978317371f, 0.207111376f, + 0.979569766f, 0.201104635f, + 0.980785280f, 0.195090322f, + 0.981963869f, 0.189068664f, + 0.983105487f, 0.183039888f, + 0.984210092f, 0.177004220f, + 0.985277642f, 0.170961889f, + 0.986308097f, 0.164913120f, + 0.987301418f, 0.158858143f, + 0.988257568f, 0.152797185f, + 0.989176510f, 0.146730474f, + 0.990058210f, 0.140658239f, + 0.990902635f, 0.134580709f, + 0.991709754f, 0.128498111f, + 0.992479535f, 0.122410675f, + 0.993211949f, 0.116318631f, + 0.993906970f, 0.110222207f, + 0.994564571f, 0.104121634f, + 0.995184727f, 0.098017140f, + 0.995767414f, 0.091908956f, + 0.996312612f, 0.085797312f, + 0.996820299f, 0.079682438f, + 0.997290457f, 0.073564564f, + 0.997723067f, 0.067443920f, + 0.998118113f, 0.061320736f, + 0.998475581f, 0.055195244f, + 0.998795456f, 0.049067674f, + 0.999077728f, 0.042938257f, + 0.999322385f, 0.036807223f, + 0.999529418f, 0.030674803f, + 0.999698819f, 0.024541229f, + 0.999830582f, 0.018406730f, + 0.999924702f, 0.012271538f, + 0.999981175f, 0.006135885f, + 1.000000000f, 0.000000000f, + 0.999981175f, -0.006135885f, + 0.999924702f, -0.012271538f, + 0.999830582f, -0.018406730f, + 0.999698819f, -0.024541229f, + 0.999529418f, -0.030674803f, + 0.999322385f, -0.036807223f, + 0.999077728f, -0.042938257f, + 0.998795456f, -0.049067674f, + 0.998475581f, -0.055195244f, + 0.998118113f, -0.061320736f, + 0.997723067f, -0.067443920f, + 0.997290457f, -0.073564564f, + 0.996820299f, -0.079682438f, + 0.996312612f, -0.085797312f, + 0.995767414f, -0.091908956f, + 0.995184727f, -0.098017140f, + 0.994564571f, -0.104121634f, + 0.993906970f, -0.110222207f, + 0.993211949f, -0.116318631f, + 0.992479535f, -0.122410675f, + 0.991709754f, -0.128498111f, + 0.990902635f, -0.134580709f, + 0.990058210f, -0.140658239f, + 0.989176510f, -0.146730474f, + 0.988257568f, -0.152797185f, + 0.987301418f, -0.158858143f, + 0.986308097f, -0.164913120f, + 0.985277642f, -0.170961889f, + 0.984210092f, -0.177004220f, + 0.983105487f, -0.183039888f, + 0.981963869f, -0.189068664f, + 0.980785280f, -0.195090322f, + 0.979569766f, -0.201104635f, + 0.978317371f, -0.207111376f, + 0.977028143f, -0.213110320f, + 0.975702130f, -0.219101240f, + 0.974339383f, -0.225083911f, + 0.972939952f, -0.231058108f, + 0.971503891f, -0.237023606f, + 0.970031253f, -0.242980180f, + 0.968522094f, -0.248927606f, + 0.966976471f, -0.254865660f, + 0.965394442f, -0.260794118f, + 0.963776066f, -0.266712757f, + 0.962121404f, -0.272621355f, + 0.960430519f, -0.278519689f, + 0.958703475f, -0.284407537f, + 0.956940336f, -0.290284677f, + 0.955141168f, -0.296150888f, + 0.953306040f, -0.302005949f, + 0.951435021f, -0.307849640f, + 0.949528181f, -0.313681740f, + 0.947585591f, -0.319502031f, + 0.945607325f, -0.325310292f, + 0.943593458f, -0.331106306f, + 0.941544065f, -0.336889853f, + 0.939459224f, -0.342660717f, + 0.937339012f, -0.348418680f, + 0.935183510f, -0.354163525f, + 0.932992799f, -0.359895037f, + 0.930766961f, -0.365612998f, + 0.928506080f, -0.371317194f, + 0.926210242f, -0.377007410f, + 0.923879533f, -0.382683432f, + 0.921514039f, -0.388345047f, + 0.919113852f, -0.393992040f, + 0.916679060f, -0.399624200f, + 0.914209756f, -0.405241314f, + 0.911706032f, -0.410843171f, + 0.909167983f, -0.416429560f, + 0.906595705f, -0.422000271f, + 0.903989293f, -0.427555093f, + 0.901348847f, -0.433093819f, + 0.898674466f, -0.438616239f, + 0.895966250f, -0.444122145f, + 0.893224301f, -0.449611330f, + 0.890448723f, -0.455083587f, + 0.887639620f, -0.460538711f, + 0.884797098f, -0.465976496f, + 0.881921264f, -0.471396737f, + 0.879012226f, -0.476799230f, + 0.876070094f, -0.482183772f, + 0.873094978f, -0.487550160f, + 0.870086991f, -0.492898192f, + 0.867046246f, -0.498227667f, + 0.863972856f, -0.503538384f, + 0.860866939f, -0.508830143f, + 0.857728610f, -0.514102744f, + 0.854557988f, -0.519355990f, + 0.851355193f, -0.524589683f, + 0.848120345f, -0.529803625f, + 0.844853565f, -0.534997620f, + 0.841554977f, -0.540171473f, + 0.838224706f, -0.545324988f, + 0.834862875f, -0.550457973f, + 0.831469612f, -0.555570233f, + 0.828045045f, -0.560661576f, + 0.824589303f, -0.565731811f, + 0.821102515f, -0.570780746f, + 0.817584813f, -0.575808191f, + 0.814036330f, -0.580813958f, + 0.810457198f, -0.585797857f, + 0.806847554f, -0.590759702f, + 0.803207531f, -0.595699304f, + 0.799537269f, -0.600616479f, + 0.795836905f, -0.605511041f, + 0.792106577f, -0.610382806f, + 0.788346428f, -0.615231591f, + 0.784556597f, -0.620057212f, + 0.780737229f, -0.624859488f, + 0.776888466f, -0.629638239f, + 0.773010453f, -0.634393284f, + 0.769103338f, -0.639124445f, + 0.765167266f, -0.643831543f, + 0.761202385f, -0.648514401f, + 0.757208847f, -0.653172843f, + 0.753186799f, -0.657806693f, + 0.749136395f, -0.662415778f, + 0.745057785f, -0.666999922f, + 0.740951125f, -0.671558955f, + 0.736816569f, -0.676092704f, + 0.732654272f, -0.680600998f, + 0.728464390f, -0.685083668f, + 0.724247083f, -0.689540545f, + 0.720002508f, -0.693971461f, + 0.715730825f, -0.698376249f, + 0.711432196f, -0.702754744f, + 0.707106781f, -0.707106781f, + 0.702754744f, -0.711432196f, + 0.698376249f, -0.715730825f, + 0.693971461f, -0.720002508f, + 0.689540545f, -0.724247083f, + 0.685083668f, -0.728464390f, + 0.680600998f, -0.732654272f, + 0.676092704f, -0.736816569f, + 0.671558955f, -0.740951125f, + 0.666999922f, -0.745057785f, + 0.662415778f, -0.749136395f, + 0.657806693f, -0.753186799f, + 0.653172843f, -0.757208847f, + 0.648514401f, -0.761202385f, + 0.643831543f, -0.765167266f, + 0.639124445f, -0.769103338f, + 0.634393284f, -0.773010453f, + 0.629638239f, -0.776888466f, + 0.624859488f, -0.780737229f, + 0.620057212f, -0.784556597f, + 0.615231591f, -0.788346428f, + 0.610382806f, -0.792106577f, + 0.605511041f, -0.795836905f, + 0.600616479f, -0.799537269f, + 0.595699304f, -0.803207531f, + 0.590759702f, -0.806847554f, + 0.585797857f, -0.810457198f, + 0.580813958f, -0.814036330f, + 0.575808191f, -0.817584813f, + 0.570780746f, -0.821102515f, + 0.565731811f, -0.824589303f, + 0.560661576f, -0.828045045f, + 0.555570233f, -0.831469612f, + 0.550457973f, -0.834862875f, + 0.545324988f, -0.838224706f, + 0.540171473f, -0.841554977f, + 0.534997620f, -0.844853565f, + 0.529803625f, -0.848120345f, + 0.524589683f, -0.851355193f, + 0.519355990f, -0.854557988f, + 0.514102744f, -0.857728610f, + 0.508830143f, -0.860866939f, + 0.503538384f, -0.863972856f, + 0.498227667f, -0.867046246f, + 0.492898192f, -0.870086991f, + 0.487550160f, -0.873094978f, + 0.482183772f, -0.876070094f, + 0.476799230f, -0.879012226f, + 0.471396737f, -0.881921264f, + 0.465976496f, -0.884797098f, + 0.460538711f, -0.887639620f, + 0.455083587f, -0.890448723f, + 0.449611330f, -0.893224301f, + 0.444122145f, -0.895966250f, + 0.438616239f, -0.898674466f, + 0.433093819f, -0.901348847f, + 0.427555093f, -0.903989293f, + 0.422000271f, -0.906595705f, + 0.416429560f, -0.909167983f, + 0.410843171f, -0.911706032f, + 0.405241314f, -0.914209756f, + 0.399624200f, -0.916679060f, + 0.393992040f, -0.919113852f, + 0.388345047f, -0.921514039f, + 0.382683432f, -0.923879533f, + 0.377007410f, -0.926210242f, + 0.371317194f, -0.928506080f, + 0.365612998f, -0.930766961f, + 0.359895037f, -0.932992799f, + 0.354163525f, -0.935183510f, + 0.348418680f, -0.937339012f, + 0.342660717f, -0.939459224f, + 0.336889853f, -0.941544065f, + 0.331106306f, -0.943593458f, + 0.325310292f, -0.945607325f, + 0.319502031f, -0.947585591f, + 0.313681740f, -0.949528181f, + 0.307849640f, -0.951435021f, + 0.302005949f, -0.953306040f, + 0.296150888f, -0.955141168f, + 0.290284677f, -0.956940336f, + 0.284407537f, -0.958703475f, + 0.278519689f, -0.960430519f, + 0.272621355f, -0.962121404f, + 0.266712757f, -0.963776066f, + 0.260794118f, -0.965394442f, + 0.254865660f, -0.966976471f, + 0.248927606f, -0.968522094f, + 0.242980180f, -0.970031253f, + 0.237023606f, -0.971503891f, + 0.231058108f, -0.972939952f, + 0.225083911f, -0.974339383f, + 0.219101240f, -0.975702130f, + 0.213110320f, -0.977028143f, + 0.207111376f, -0.978317371f, + 0.201104635f, -0.979569766f, + 0.195090322f, -0.980785280f, + 0.189068664f, -0.981963869f, + 0.183039888f, -0.983105487f, + 0.177004220f, -0.984210092f, + 0.170961889f, -0.985277642f, + 0.164913120f, -0.986308097f, + 0.158858143f, -0.987301418f, + 0.152797185f, -0.988257568f, + 0.146730474f, -0.989176510f, + 0.140658239f, -0.990058210f, + 0.134580709f, -0.990902635f, + 0.128498111f, -0.991709754f, + 0.122410675f, -0.992479535f, + 0.116318631f, -0.993211949f, + 0.110222207f, -0.993906970f, + 0.104121634f, -0.994564571f, + 0.098017140f, -0.995184727f, + 0.091908956f, -0.995767414f, + 0.085797312f, -0.996312612f, + 0.079682438f, -0.996820299f, + 0.073564564f, -0.997290457f, + 0.067443920f, -0.997723067f, + 0.061320736f, -0.998118113f, + 0.055195244f, -0.998475581f, + 0.049067674f, -0.998795456f, + 0.042938257f, -0.999077728f, + 0.036807223f, -0.999322385f, + 0.030674803f, -0.999529418f, + 0.024541229f, -0.999698819f, + 0.018406730f, -0.999830582f, + 0.012271538f, -0.999924702f, + 0.006135885f, -0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) +const float32_t twiddleCoef_rfft_2048[2048] = { + 0.000000000f, 1.000000000f, + 0.003067957f, 0.999995294f, + 0.006135885f, 0.999981175f, + 0.009203755f, 0.999957645f, + 0.012271538f, 0.999924702f, + 0.015339206f, 0.999882347f, + 0.018406730f, 0.999830582f, + 0.021474080f, 0.999769405f, + 0.024541229f, 0.999698819f, + 0.027608146f, 0.999618822f, + 0.030674803f, 0.999529418f, + 0.033741172f, 0.999430605f, + 0.036807223f, 0.999322385f, + 0.039872928f, 0.999204759f, + 0.042938257f, 0.999077728f, + 0.046003182f, 0.998941293f, + 0.049067674f, 0.998795456f, + 0.052131705f, 0.998640218f, + 0.055195244f, 0.998475581f, + 0.058258265f, 0.998301545f, + 0.061320736f, 0.998118113f, + 0.064382631f, 0.997925286f, + 0.067443920f, 0.997723067f, + 0.070504573f, 0.997511456f, + 0.073564564f, 0.997290457f, + 0.076623861f, 0.997060070f, + 0.079682438f, 0.996820299f, + 0.082740265f, 0.996571146f, + 0.085797312f, 0.996312612f, + 0.088853553f, 0.996044701f, + 0.091908956f, 0.995767414f, + 0.094963495f, 0.995480755f, + 0.098017140f, 0.995184727f, + 0.101069863f, 0.994879331f, + 0.104121634f, 0.994564571f, + 0.107172425f, 0.994240449f, + 0.110222207f, 0.993906970f, + 0.113270952f, 0.993564136f, + 0.116318631f, 0.993211949f, + 0.119365215f, 0.992850414f, + 0.122410675f, 0.992479535f, + 0.125454983f, 0.992099313f, + 0.128498111f, 0.991709754f, + 0.131540029f, 0.991310860f, + 0.134580709f, 0.990902635f, + 0.137620122f, 0.990485084f, + 0.140658239f, 0.990058210f, + 0.143695033f, 0.989622017f, + 0.146730474f, 0.989176510f, + 0.149764535f, 0.988721692f, + 0.152797185f, 0.988257568f, + 0.155828398f, 0.987784142f, + 0.158858143f, 0.987301418f, + 0.161886394f, 0.986809402f, + 0.164913120f, 0.986308097f, + 0.167938295f, 0.985797509f, + 0.170961889f, 0.985277642f, + 0.173983873f, 0.984748502f, + 0.177004220f, 0.984210092f, + 0.180022901f, 0.983662419f, + 0.183039888f, 0.983105487f, + 0.186055152f, 0.982539302f, + 0.189068664f, 0.981963869f, + 0.192080397f, 0.981379193f, + 0.195090322f, 0.980785280f, + 0.198098411f, 0.980182136f, + 0.201104635f, 0.979569766f, + 0.204108966f, 0.978948175f, + 0.207111376f, 0.978317371f, + 0.210111837f, 0.977677358f, + 0.213110320f, 0.977028143f, + 0.216106797f, 0.976369731f, + 0.219101240f, 0.975702130f, + 0.222093621f, 0.975025345f, + 0.225083911f, 0.974339383f, + 0.228072083f, 0.973644250f, + 0.231058108f, 0.972939952f, + 0.234041959f, 0.972226497f, + 0.237023606f, 0.971503891f, + 0.240003022f, 0.970772141f, + 0.242980180f, 0.970031253f, + 0.245955050f, 0.969281235f, + 0.248927606f, 0.968522094f, + 0.251897818f, 0.967753837f, + 0.254865660f, 0.966976471f, + 0.257831102f, 0.966190003f, + 0.260794118f, 0.965394442f, + 0.263754679f, 0.964589793f, + 0.266712757f, 0.963776066f, + 0.269668326f, 0.962953267f, + 0.272621355f, 0.962121404f, + 0.275571819f, 0.961280486f, + 0.278519689f, 0.960430519f, + 0.281464938f, 0.959571513f, + 0.284407537f, 0.958703475f, + 0.287347460f, 0.957826413f, + 0.290284677f, 0.956940336f, + 0.293219163f, 0.956045251f, + 0.296150888f, 0.955141168f, + 0.299079826f, 0.954228095f, + 0.302005949f, 0.953306040f, + 0.304929230f, 0.952375013f, + 0.307849640f, 0.951435021f, + 0.310767153f, 0.950486074f, + 0.313681740f, 0.949528181f, + 0.316593376f, 0.948561350f, + 0.319502031f, 0.947585591f, + 0.322407679f, 0.946600913f, + 0.325310292f, 0.945607325f, + 0.328209844f, 0.944604837f, + 0.331106306f, 0.943593458f, + 0.333999651f, 0.942573198f, + 0.336889853f, 0.941544065f, + 0.339776884f, 0.940506071f, + 0.342660717f, 0.939459224f, + 0.345541325f, 0.938403534f, + 0.348418680f, 0.937339012f, + 0.351292756f, 0.936265667f, + 0.354163525f, 0.935183510f, + 0.357030961f, 0.934092550f, + 0.359895037f, 0.932992799f, + 0.362755724f, 0.931884266f, + 0.365612998f, 0.930766961f, + 0.368466830f, 0.929640896f, + 0.371317194f, 0.928506080f, + 0.374164063f, 0.927362526f, + 0.377007410f, 0.926210242f, + 0.379847209f, 0.925049241f, + 0.382683432f, 0.923879533f, + 0.385516054f, 0.922701128f, + 0.388345047f, 0.921514039f, + 0.391170384f, 0.920318277f, + 0.393992040f, 0.919113852f, + 0.396809987f, 0.917900776f, + 0.399624200f, 0.916679060f, + 0.402434651f, 0.915448716f, + 0.405241314f, 0.914209756f, + 0.408044163f, 0.912962190f, + 0.410843171f, 0.911706032f, + 0.413638312f, 0.910441292f, + 0.416429560f, 0.909167983f, + 0.419216888f, 0.907886116f, + 0.422000271f, 0.906595705f, + 0.424779681f, 0.905296759f, + 0.427555093f, 0.903989293f, + 0.430326481f, 0.902673318f, + 0.433093819f, 0.901348847f, + 0.435857080f, 0.900015892f, + 0.438616239f, 0.898674466f, + 0.441371269f, 0.897324581f, + 0.444122145f, 0.895966250f, + 0.446868840f, 0.894599486f, + 0.449611330f, 0.893224301f, + 0.452349587f, 0.891840709f, + 0.455083587f, 0.890448723f, + 0.457813304f, 0.889048356f, + 0.460538711f, 0.887639620f, + 0.463259784f, 0.886222530f, + 0.465976496f, 0.884797098f, + 0.468688822f, 0.883363339f, + 0.471396737f, 0.881921264f, + 0.474100215f, 0.880470889f, + 0.476799230f, 0.879012226f, + 0.479493758f, 0.877545290f, + 0.482183772f, 0.876070094f, + 0.484869248f, 0.874586652f, + 0.487550160f, 0.873094978f, + 0.490226483f, 0.871595087f, + 0.492898192f, 0.870086991f, + 0.495565262f, 0.868570706f, + 0.498227667f, 0.867046246f, + 0.500885383f, 0.865513624f, + 0.503538384f, 0.863972856f, + 0.506186645f, 0.862423956f, + 0.508830143f, 0.860866939f, + 0.511468850f, 0.859301818f, + 0.514102744f, 0.857728610f, + 0.516731799f, 0.856147328f, + 0.519355990f, 0.854557988f, + 0.521975293f, 0.852960605f, + 0.524589683f, 0.851355193f, + 0.527199135f, 0.849741768f, + 0.529803625f, 0.848120345f, + 0.532403128f, 0.846490939f, + 0.534997620f, 0.844853565f, + 0.537587076f, 0.843208240f, + 0.540171473f, 0.841554977f, + 0.542750785f, 0.839893794f, + 0.545324988f, 0.838224706f, + 0.547894059f, 0.836547727f, + 0.550457973f, 0.834862875f, + 0.553016706f, 0.833170165f, + 0.555570233f, 0.831469612f, + 0.558118531f, 0.829761234f, + 0.560661576f, 0.828045045f, + 0.563199344f, 0.826321063f, + 0.565731811f, 0.824589303f, + 0.568258953f, 0.822849781f, + 0.570780746f, 0.821102515f, + 0.573297167f, 0.819347520f, + 0.575808191f, 0.817584813f, + 0.578313796f, 0.815814411f, + 0.580813958f, 0.814036330f, + 0.583308653f, 0.812250587f, + 0.585797857f, 0.810457198f, + 0.588281548f, 0.808656182f, + 0.590759702f, 0.806847554f, + 0.593232295f, 0.805031331f, + 0.595699304f, 0.803207531f, + 0.598160707f, 0.801376172f, + 0.600616479f, 0.799537269f, + 0.603066599f, 0.797690841f, + 0.605511041f, 0.795836905f, + 0.607949785f, 0.793975478f, + 0.610382806f, 0.792106577f, + 0.612810082f, 0.790230221f, + 0.615231591f, 0.788346428f, + 0.617647308f, 0.786455214f, + 0.620057212f, 0.784556597f, + 0.622461279f, 0.782650596f, + 0.624859488f, 0.780737229f, + 0.627251815f, 0.778816512f, + 0.629638239f, 0.776888466f, + 0.632018736f, 0.774953107f, + 0.634393284f, 0.773010453f, + 0.636761861f, 0.771060524f, + 0.639124445f, 0.769103338f, + 0.641481013f, 0.767138912f, + 0.643831543f, 0.765167266f, + 0.646176013f, 0.763188417f, + 0.648514401f, 0.761202385f, + 0.650846685f, 0.759209189f, + 0.653172843f, 0.757208847f, + 0.655492853f, 0.755201377f, + 0.657806693f, 0.753186799f, + 0.660114342f, 0.751165132f, + 0.662415778f, 0.749136395f, + 0.664710978f, 0.747100606f, + 0.666999922f, 0.745057785f, + 0.669282588f, 0.743007952f, + 0.671558955f, 0.740951125f, + 0.673829000f, 0.738887324f, + 0.676092704f, 0.736816569f, + 0.678350043f, 0.734738878f, + 0.680600998f, 0.732654272f, + 0.682845546f, 0.730562769f, + 0.685083668f, 0.728464390f, + 0.687315341f, 0.726359155f, + 0.689540545f, 0.724247083f, + 0.691759258f, 0.722128194f, + 0.693971461f, 0.720002508f, + 0.696177131f, 0.717870045f, + 0.698376249f, 0.715730825f, + 0.700568794f, 0.713584869f, + 0.702754744f, 0.711432196f, + 0.704934080f, 0.709272826f, + 0.707106781f, 0.707106781f, + 0.709272826f, 0.704934080f, + 0.711432196f, 0.702754744f, + 0.713584869f, 0.700568794f, + 0.715730825f, 0.698376249f, + 0.717870045f, 0.696177131f, + 0.720002508f, 0.693971461f, + 0.722128194f, 0.691759258f, + 0.724247083f, 0.689540545f, + 0.726359155f, 0.687315341f, + 0.728464390f, 0.685083668f, + 0.730562769f, 0.682845546f, + 0.732654272f, 0.680600998f, + 0.734738878f, 0.678350043f, + 0.736816569f, 0.676092704f, + 0.738887324f, 0.673829000f, + 0.740951125f, 0.671558955f, + 0.743007952f, 0.669282588f, + 0.745057785f, 0.666999922f, + 0.747100606f, 0.664710978f, + 0.749136395f, 0.662415778f, + 0.751165132f, 0.660114342f, + 0.753186799f, 0.657806693f, + 0.755201377f, 0.655492853f, + 0.757208847f, 0.653172843f, + 0.759209189f, 0.650846685f, + 0.761202385f, 0.648514401f, + 0.763188417f, 0.646176013f, + 0.765167266f, 0.643831543f, + 0.767138912f, 0.641481013f, + 0.769103338f, 0.639124445f, + 0.771060524f, 0.636761861f, + 0.773010453f, 0.634393284f, + 0.774953107f, 0.632018736f, + 0.776888466f, 0.629638239f, + 0.778816512f, 0.627251815f, + 0.780737229f, 0.624859488f, + 0.782650596f, 0.622461279f, + 0.784556597f, 0.620057212f, + 0.786455214f, 0.617647308f, + 0.788346428f, 0.615231591f, + 0.790230221f, 0.612810082f, + 0.792106577f, 0.610382806f, + 0.793975478f, 0.607949785f, + 0.795836905f, 0.605511041f, + 0.797690841f, 0.603066599f, + 0.799537269f, 0.600616479f, + 0.801376172f, 0.598160707f, + 0.803207531f, 0.595699304f, + 0.805031331f, 0.593232295f, + 0.806847554f, 0.590759702f, + 0.808656182f, 0.588281548f, + 0.810457198f, 0.585797857f, + 0.812250587f, 0.583308653f, + 0.814036330f, 0.580813958f, + 0.815814411f, 0.578313796f, + 0.817584813f, 0.575808191f, + 0.819347520f, 0.573297167f, + 0.821102515f, 0.570780746f, + 0.822849781f, 0.568258953f, + 0.824589303f, 0.565731811f, + 0.826321063f, 0.563199344f, + 0.828045045f, 0.560661576f, + 0.829761234f, 0.558118531f, + 0.831469612f, 0.555570233f, + 0.833170165f, 0.553016706f, + 0.834862875f, 0.550457973f, + 0.836547727f, 0.547894059f, + 0.838224706f, 0.545324988f, + 0.839893794f, 0.542750785f, + 0.841554977f, 0.540171473f, + 0.843208240f, 0.537587076f, + 0.844853565f, 0.534997620f, + 0.846490939f, 0.532403128f, + 0.848120345f, 0.529803625f, + 0.849741768f, 0.527199135f, + 0.851355193f, 0.524589683f, + 0.852960605f, 0.521975293f, + 0.854557988f, 0.519355990f, + 0.856147328f, 0.516731799f, + 0.857728610f, 0.514102744f, + 0.859301818f, 0.511468850f, + 0.860866939f, 0.508830143f, + 0.862423956f, 0.506186645f, + 0.863972856f, 0.503538384f, + 0.865513624f, 0.500885383f, + 0.867046246f, 0.498227667f, + 0.868570706f, 0.495565262f, + 0.870086991f, 0.492898192f, + 0.871595087f, 0.490226483f, + 0.873094978f, 0.487550160f, + 0.874586652f, 0.484869248f, + 0.876070094f, 0.482183772f, + 0.877545290f, 0.479493758f, + 0.879012226f, 0.476799230f, + 0.880470889f, 0.474100215f, + 0.881921264f, 0.471396737f, + 0.883363339f, 0.468688822f, + 0.884797098f, 0.465976496f, + 0.886222530f, 0.463259784f, + 0.887639620f, 0.460538711f, + 0.889048356f, 0.457813304f, + 0.890448723f, 0.455083587f, + 0.891840709f, 0.452349587f, + 0.893224301f, 0.449611330f, + 0.894599486f, 0.446868840f, + 0.895966250f, 0.444122145f, + 0.897324581f, 0.441371269f, + 0.898674466f, 0.438616239f, + 0.900015892f, 0.435857080f, + 0.901348847f, 0.433093819f, + 0.902673318f, 0.430326481f, + 0.903989293f, 0.427555093f, + 0.905296759f, 0.424779681f, + 0.906595705f, 0.422000271f, + 0.907886116f, 0.419216888f, + 0.909167983f, 0.416429560f, + 0.910441292f, 0.413638312f, + 0.911706032f, 0.410843171f, + 0.912962190f, 0.408044163f, + 0.914209756f, 0.405241314f, + 0.915448716f, 0.402434651f, + 0.916679060f, 0.399624200f, + 0.917900776f, 0.396809987f, + 0.919113852f, 0.393992040f, + 0.920318277f, 0.391170384f, + 0.921514039f, 0.388345047f, + 0.922701128f, 0.385516054f, + 0.923879533f, 0.382683432f, + 0.925049241f, 0.379847209f, + 0.926210242f, 0.377007410f, + 0.927362526f, 0.374164063f, + 0.928506080f, 0.371317194f, + 0.929640896f, 0.368466830f, + 0.930766961f, 0.365612998f, + 0.931884266f, 0.362755724f, + 0.932992799f, 0.359895037f, + 0.934092550f, 0.357030961f, + 0.935183510f, 0.354163525f, + 0.936265667f, 0.351292756f, + 0.937339012f, 0.348418680f, + 0.938403534f, 0.345541325f, + 0.939459224f, 0.342660717f, + 0.940506071f, 0.339776884f, + 0.941544065f, 0.336889853f, + 0.942573198f, 0.333999651f, + 0.943593458f, 0.331106306f, + 0.944604837f, 0.328209844f, + 0.945607325f, 0.325310292f, + 0.946600913f, 0.322407679f, + 0.947585591f, 0.319502031f, + 0.948561350f, 0.316593376f, + 0.949528181f, 0.313681740f, + 0.950486074f, 0.310767153f, + 0.951435021f, 0.307849640f, + 0.952375013f, 0.304929230f, + 0.953306040f, 0.302005949f, + 0.954228095f, 0.299079826f, + 0.955141168f, 0.296150888f, + 0.956045251f, 0.293219163f, + 0.956940336f, 0.290284677f, + 0.957826413f, 0.287347460f, + 0.958703475f, 0.284407537f, + 0.959571513f, 0.281464938f, + 0.960430519f, 0.278519689f, + 0.961280486f, 0.275571819f, + 0.962121404f, 0.272621355f, + 0.962953267f, 0.269668326f, + 0.963776066f, 0.266712757f, + 0.964589793f, 0.263754679f, + 0.965394442f, 0.260794118f, + 0.966190003f, 0.257831102f, + 0.966976471f, 0.254865660f, + 0.967753837f, 0.251897818f, + 0.968522094f, 0.248927606f, + 0.969281235f, 0.245955050f, + 0.970031253f, 0.242980180f, + 0.970772141f, 0.240003022f, + 0.971503891f, 0.237023606f, + 0.972226497f, 0.234041959f, + 0.972939952f, 0.231058108f, + 0.973644250f, 0.228072083f, + 0.974339383f, 0.225083911f, + 0.975025345f, 0.222093621f, + 0.975702130f, 0.219101240f, + 0.976369731f, 0.216106797f, + 0.977028143f, 0.213110320f, + 0.977677358f, 0.210111837f, + 0.978317371f, 0.207111376f, + 0.978948175f, 0.204108966f, + 0.979569766f, 0.201104635f, + 0.980182136f, 0.198098411f, + 0.980785280f, 0.195090322f, + 0.981379193f, 0.192080397f, + 0.981963869f, 0.189068664f, + 0.982539302f, 0.186055152f, + 0.983105487f, 0.183039888f, + 0.983662419f, 0.180022901f, + 0.984210092f, 0.177004220f, + 0.984748502f, 0.173983873f, + 0.985277642f, 0.170961889f, + 0.985797509f, 0.167938295f, + 0.986308097f, 0.164913120f, + 0.986809402f, 0.161886394f, + 0.987301418f, 0.158858143f, + 0.987784142f, 0.155828398f, + 0.988257568f, 0.152797185f, + 0.988721692f, 0.149764535f, + 0.989176510f, 0.146730474f, + 0.989622017f, 0.143695033f, + 0.990058210f, 0.140658239f, + 0.990485084f, 0.137620122f, + 0.990902635f, 0.134580709f, + 0.991310860f, 0.131540029f, + 0.991709754f, 0.128498111f, + 0.992099313f, 0.125454983f, + 0.992479535f, 0.122410675f, + 0.992850414f, 0.119365215f, + 0.993211949f, 0.116318631f, + 0.993564136f, 0.113270952f, + 0.993906970f, 0.110222207f, + 0.994240449f, 0.107172425f, + 0.994564571f, 0.104121634f, + 0.994879331f, 0.101069863f, + 0.995184727f, 0.098017140f, + 0.995480755f, 0.094963495f, + 0.995767414f, 0.091908956f, + 0.996044701f, 0.088853553f, + 0.996312612f, 0.085797312f, + 0.996571146f, 0.082740265f, + 0.996820299f, 0.079682438f, + 0.997060070f, 0.076623861f, + 0.997290457f, 0.073564564f, + 0.997511456f, 0.070504573f, + 0.997723067f, 0.067443920f, + 0.997925286f, 0.064382631f, + 0.998118113f, 0.061320736f, + 0.998301545f, 0.058258265f, + 0.998475581f, 0.055195244f, + 0.998640218f, 0.052131705f, + 0.998795456f, 0.049067674f, + 0.998941293f, 0.046003182f, + 0.999077728f, 0.042938257f, + 0.999204759f, 0.039872928f, + 0.999322385f, 0.036807223f, + 0.999430605f, 0.033741172f, + 0.999529418f, 0.030674803f, + 0.999618822f, 0.027608146f, + 0.999698819f, 0.024541229f, + 0.999769405f, 0.021474080f, + 0.999830582f, 0.018406730f, + 0.999882347f, 0.015339206f, + 0.999924702f, 0.012271538f, + 0.999957645f, 0.009203755f, + 0.999981175f, 0.006135885f, + 0.999995294f, 0.003067957f, + 1.000000000f, 0.000000000f, + 0.999995294f, -0.003067957f, + 0.999981175f, -0.006135885f, + 0.999957645f, -0.009203755f, + 0.999924702f, -0.012271538f, + 0.999882347f, -0.015339206f, + 0.999830582f, -0.018406730f, + 0.999769405f, -0.021474080f, + 0.999698819f, -0.024541229f, + 0.999618822f, -0.027608146f, + 0.999529418f, -0.030674803f, + 0.999430605f, -0.033741172f, + 0.999322385f, -0.036807223f, + 0.999204759f, -0.039872928f, + 0.999077728f, -0.042938257f, + 0.998941293f, -0.046003182f, + 0.998795456f, -0.049067674f, + 0.998640218f, -0.052131705f, + 0.998475581f, -0.055195244f, + 0.998301545f, -0.058258265f, + 0.998118113f, -0.061320736f, + 0.997925286f, -0.064382631f, + 0.997723067f, -0.067443920f, + 0.997511456f, -0.070504573f, + 0.997290457f, -0.073564564f, + 0.997060070f, -0.076623861f, + 0.996820299f, -0.079682438f, + 0.996571146f, -0.082740265f, + 0.996312612f, -0.085797312f, + 0.996044701f, -0.088853553f, + 0.995767414f, -0.091908956f, + 0.995480755f, -0.094963495f, + 0.995184727f, -0.098017140f, + 0.994879331f, -0.101069863f, + 0.994564571f, -0.104121634f, + 0.994240449f, -0.107172425f, + 0.993906970f, -0.110222207f, + 0.993564136f, -0.113270952f, + 0.993211949f, -0.116318631f, + 0.992850414f, -0.119365215f, + 0.992479535f, -0.122410675f, + 0.992099313f, -0.125454983f, + 0.991709754f, -0.128498111f, + 0.991310860f, -0.131540029f, + 0.990902635f, -0.134580709f, + 0.990485084f, -0.137620122f, + 0.990058210f, -0.140658239f, + 0.989622017f, -0.143695033f, + 0.989176510f, -0.146730474f, + 0.988721692f, -0.149764535f, + 0.988257568f, -0.152797185f, + 0.987784142f, -0.155828398f, + 0.987301418f, -0.158858143f, + 0.986809402f, -0.161886394f, + 0.986308097f, -0.164913120f, + 0.985797509f, -0.167938295f, + 0.985277642f, -0.170961889f, + 0.984748502f, -0.173983873f, + 0.984210092f, -0.177004220f, + 0.983662419f, -0.180022901f, + 0.983105487f, -0.183039888f, + 0.982539302f, -0.186055152f, + 0.981963869f, -0.189068664f, + 0.981379193f, -0.192080397f, + 0.980785280f, -0.195090322f, + 0.980182136f, -0.198098411f, + 0.979569766f, -0.201104635f, + 0.978948175f, -0.204108966f, + 0.978317371f, -0.207111376f, + 0.977677358f, -0.210111837f, + 0.977028143f, -0.213110320f, + 0.976369731f, -0.216106797f, + 0.975702130f, -0.219101240f, + 0.975025345f, -0.222093621f, + 0.974339383f, -0.225083911f, + 0.973644250f, -0.228072083f, + 0.972939952f, -0.231058108f, + 0.972226497f, -0.234041959f, + 0.971503891f, -0.237023606f, + 0.970772141f, -0.240003022f, + 0.970031253f, -0.242980180f, + 0.969281235f, -0.245955050f, + 0.968522094f, -0.248927606f, + 0.967753837f, -0.251897818f, + 0.966976471f, -0.254865660f, + 0.966190003f, -0.257831102f, + 0.965394442f, -0.260794118f, + 0.964589793f, -0.263754679f, + 0.963776066f, -0.266712757f, + 0.962953267f, -0.269668326f, + 0.962121404f, -0.272621355f, + 0.961280486f, -0.275571819f, + 0.960430519f, -0.278519689f, + 0.959571513f, -0.281464938f, + 0.958703475f, -0.284407537f, + 0.957826413f, -0.287347460f, + 0.956940336f, -0.290284677f, + 0.956045251f, -0.293219163f, + 0.955141168f, -0.296150888f, + 0.954228095f, -0.299079826f, + 0.953306040f, -0.302005949f, + 0.952375013f, -0.304929230f, + 0.951435021f, -0.307849640f, + 0.950486074f, -0.310767153f, + 0.949528181f, -0.313681740f, + 0.948561350f, -0.316593376f, + 0.947585591f, -0.319502031f, + 0.946600913f, -0.322407679f, + 0.945607325f, -0.325310292f, + 0.944604837f, -0.328209844f, + 0.943593458f, -0.331106306f, + 0.942573198f, -0.333999651f, + 0.941544065f, -0.336889853f, + 0.940506071f, -0.339776884f, + 0.939459224f, -0.342660717f, + 0.938403534f, -0.345541325f, + 0.937339012f, -0.348418680f, + 0.936265667f, -0.351292756f, + 0.935183510f, -0.354163525f, + 0.934092550f, -0.357030961f, + 0.932992799f, -0.359895037f, + 0.931884266f, -0.362755724f, + 0.930766961f, -0.365612998f, + 0.929640896f, -0.368466830f, + 0.928506080f, -0.371317194f, + 0.927362526f, -0.374164063f, + 0.926210242f, -0.377007410f, + 0.925049241f, -0.379847209f, + 0.923879533f, -0.382683432f, + 0.922701128f, -0.385516054f, + 0.921514039f, -0.388345047f, + 0.920318277f, -0.391170384f, + 0.919113852f, -0.393992040f, + 0.917900776f, -0.396809987f, + 0.916679060f, -0.399624200f, + 0.915448716f, -0.402434651f, + 0.914209756f, -0.405241314f, + 0.912962190f, -0.408044163f, + 0.911706032f, -0.410843171f, + 0.910441292f, -0.413638312f, + 0.909167983f, -0.416429560f, + 0.907886116f, -0.419216888f, + 0.906595705f, -0.422000271f, + 0.905296759f, -0.424779681f, + 0.903989293f, -0.427555093f, + 0.902673318f, -0.430326481f, + 0.901348847f, -0.433093819f, + 0.900015892f, -0.435857080f, + 0.898674466f, -0.438616239f, + 0.897324581f, -0.441371269f, + 0.895966250f, -0.444122145f, + 0.894599486f, -0.446868840f, + 0.893224301f, -0.449611330f, + 0.891840709f, -0.452349587f, + 0.890448723f, -0.455083587f, + 0.889048356f, -0.457813304f, + 0.887639620f, -0.460538711f, + 0.886222530f, -0.463259784f, + 0.884797098f, -0.465976496f, + 0.883363339f, -0.468688822f, + 0.881921264f, -0.471396737f, + 0.880470889f, -0.474100215f, + 0.879012226f, -0.476799230f, + 0.877545290f, -0.479493758f, + 0.876070094f, -0.482183772f, + 0.874586652f, -0.484869248f, + 0.873094978f, -0.487550160f, + 0.871595087f, -0.490226483f, + 0.870086991f, -0.492898192f, + 0.868570706f, -0.495565262f, + 0.867046246f, -0.498227667f, + 0.865513624f, -0.500885383f, + 0.863972856f, -0.503538384f, + 0.862423956f, -0.506186645f, + 0.860866939f, -0.508830143f, + 0.859301818f, -0.511468850f, + 0.857728610f, -0.514102744f, + 0.856147328f, -0.516731799f, + 0.854557988f, -0.519355990f, + 0.852960605f, -0.521975293f, + 0.851355193f, -0.524589683f, + 0.849741768f, -0.527199135f, + 0.848120345f, -0.529803625f, + 0.846490939f, -0.532403128f, + 0.844853565f, -0.534997620f, + 0.843208240f, -0.537587076f, + 0.841554977f, -0.540171473f, + 0.839893794f, -0.542750785f, + 0.838224706f, -0.545324988f, + 0.836547727f, -0.547894059f, + 0.834862875f, -0.550457973f, + 0.833170165f, -0.553016706f, + 0.831469612f, -0.555570233f, + 0.829761234f, -0.558118531f, + 0.828045045f, -0.560661576f, + 0.826321063f, -0.563199344f, + 0.824589303f, -0.565731811f, + 0.822849781f, -0.568258953f, + 0.821102515f, -0.570780746f, + 0.819347520f, -0.573297167f, + 0.817584813f, -0.575808191f, + 0.815814411f, -0.578313796f, + 0.814036330f, -0.580813958f, + 0.812250587f, -0.583308653f, + 0.810457198f, -0.585797857f, + 0.808656182f, -0.588281548f, + 0.806847554f, -0.590759702f, + 0.805031331f, -0.593232295f, + 0.803207531f, -0.595699304f, + 0.801376172f, -0.598160707f, + 0.799537269f, -0.600616479f, + 0.797690841f, -0.603066599f, + 0.795836905f, -0.605511041f, + 0.793975478f, -0.607949785f, + 0.792106577f, -0.610382806f, + 0.790230221f, -0.612810082f, + 0.788346428f, -0.615231591f, + 0.786455214f, -0.617647308f, + 0.784556597f, -0.620057212f, + 0.782650596f, -0.622461279f, + 0.780737229f, -0.624859488f, + 0.778816512f, -0.627251815f, + 0.776888466f, -0.629638239f, + 0.774953107f, -0.632018736f, + 0.773010453f, -0.634393284f, + 0.771060524f, -0.636761861f, + 0.769103338f, -0.639124445f, + 0.767138912f, -0.641481013f, + 0.765167266f, -0.643831543f, + 0.763188417f, -0.646176013f, + 0.761202385f, -0.648514401f, + 0.759209189f, -0.650846685f, + 0.757208847f, -0.653172843f, + 0.755201377f, -0.655492853f, + 0.753186799f, -0.657806693f, + 0.751165132f, -0.660114342f, + 0.749136395f, -0.662415778f, + 0.747100606f, -0.664710978f, + 0.745057785f, -0.666999922f, + 0.743007952f, -0.669282588f, + 0.740951125f, -0.671558955f, + 0.738887324f, -0.673829000f, + 0.736816569f, -0.676092704f, + 0.734738878f, -0.678350043f, + 0.732654272f, -0.680600998f, + 0.730562769f, -0.682845546f, + 0.728464390f, -0.685083668f, + 0.726359155f, -0.687315341f, + 0.724247083f, -0.689540545f, + 0.722128194f, -0.691759258f, + 0.720002508f, -0.693971461f, + 0.717870045f, -0.696177131f, + 0.715730825f, -0.698376249f, + 0.713584869f, -0.700568794f, + 0.711432196f, -0.702754744f, + 0.709272826f, -0.704934080f, + 0.707106781f, -0.707106781f, + 0.704934080f, -0.709272826f, + 0.702754744f, -0.711432196f, + 0.700568794f, -0.713584869f, + 0.698376249f, -0.715730825f, + 0.696177131f, -0.717870045f, + 0.693971461f, -0.720002508f, + 0.691759258f, -0.722128194f, + 0.689540545f, -0.724247083f, + 0.687315341f, -0.726359155f, + 0.685083668f, -0.728464390f, + 0.682845546f, -0.730562769f, + 0.680600998f, -0.732654272f, + 0.678350043f, -0.734738878f, + 0.676092704f, -0.736816569f, + 0.673829000f, -0.738887324f, + 0.671558955f, -0.740951125f, + 0.669282588f, -0.743007952f, + 0.666999922f, -0.745057785f, + 0.664710978f, -0.747100606f, + 0.662415778f, -0.749136395f, + 0.660114342f, -0.751165132f, + 0.657806693f, -0.753186799f, + 0.655492853f, -0.755201377f, + 0.653172843f, -0.757208847f, + 0.650846685f, -0.759209189f, + 0.648514401f, -0.761202385f, + 0.646176013f, -0.763188417f, + 0.643831543f, -0.765167266f, + 0.641481013f, -0.767138912f, + 0.639124445f, -0.769103338f, + 0.636761861f, -0.771060524f, + 0.634393284f, -0.773010453f, + 0.632018736f, -0.774953107f, + 0.629638239f, -0.776888466f, + 0.627251815f, -0.778816512f, + 0.624859488f, -0.780737229f, + 0.622461279f, -0.782650596f, + 0.620057212f, -0.784556597f, + 0.617647308f, -0.786455214f, + 0.615231591f, -0.788346428f, + 0.612810082f, -0.790230221f, + 0.610382806f, -0.792106577f, + 0.607949785f, -0.793975478f, + 0.605511041f, -0.795836905f, + 0.603066599f, -0.797690841f, + 0.600616479f, -0.799537269f, + 0.598160707f, -0.801376172f, + 0.595699304f, -0.803207531f, + 0.593232295f, -0.805031331f, + 0.590759702f, -0.806847554f, + 0.588281548f, -0.808656182f, + 0.585797857f, -0.810457198f, + 0.583308653f, -0.812250587f, + 0.580813958f, -0.814036330f, + 0.578313796f, -0.815814411f, + 0.575808191f, -0.817584813f, + 0.573297167f, -0.819347520f, + 0.570780746f, -0.821102515f, + 0.568258953f, -0.822849781f, + 0.565731811f, -0.824589303f, + 0.563199344f, -0.826321063f, + 0.560661576f, -0.828045045f, + 0.558118531f, -0.829761234f, + 0.555570233f, -0.831469612f, + 0.553016706f, -0.833170165f, + 0.550457973f, -0.834862875f, + 0.547894059f, -0.836547727f, + 0.545324988f, -0.838224706f, + 0.542750785f, -0.839893794f, + 0.540171473f, -0.841554977f, + 0.537587076f, -0.843208240f, + 0.534997620f, -0.844853565f, + 0.532403128f, -0.846490939f, + 0.529803625f, -0.848120345f, + 0.527199135f, -0.849741768f, + 0.524589683f, -0.851355193f, + 0.521975293f, -0.852960605f, + 0.519355990f, -0.854557988f, + 0.516731799f, -0.856147328f, + 0.514102744f, -0.857728610f, + 0.511468850f, -0.859301818f, + 0.508830143f, -0.860866939f, + 0.506186645f, -0.862423956f, + 0.503538384f, -0.863972856f, + 0.500885383f, -0.865513624f, + 0.498227667f, -0.867046246f, + 0.495565262f, -0.868570706f, + 0.492898192f, -0.870086991f, + 0.490226483f, -0.871595087f, + 0.487550160f, -0.873094978f, + 0.484869248f, -0.874586652f, + 0.482183772f, -0.876070094f, + 0.479493758f, -0.877545290f, + 0.476799230f, -0.879012226f, + 0.474100215f, -0.880470889f, + 0.471396737f, -0.881921264f, + 0.468688822f, -0.883363339f, + 0.465976496f, -0.884797098f, + 0.463259784f, -0.886222530f, + 0.460538711f, -0.887639620f, + 0.457813304f, -0.889048356f, + 0.455083587f, -0.890448723f, + 0.452349587f, -0.891840709f, + 0.449611330f, -0.893224301f, + 0.446868840f, -0.894599486f, + 0.444122145f, -0.895966250f, + 0.441371269f, -0.897324581f, + 0.438616239f, -0.898674466f, + 0.435857080f, -0.900015892f, + 0.433093819f, -0.901348847f, + 0.430326481f, -0.902673318f, + 0.427555093f, -0.903989293f, + 0.424779681f, -0.905296759f, + 0.422000271f, -0.906595705f, + 0.419216888f, -0.907886116f, + 0.416429560f, -0.909167983f, + 0.413638312f, -0.910441292f, + 0.410843171f, -0.911706032f, + 0.408044163f, -0.912962190f, + 0.405241314f, -0.914209756f, + 0.402434651f, -0.915448716f, + 0.399624200f, -0.916679060f, + 0.396809987f, -0.917900776f, + 0.393992040f, -0.919113852f, + 0.391170384f, -0.920318277f, + 0.388345047f, -0.921514039f, + 0.385516054f, -0.922701128f, + 0.382683432f, -0.923879533f, + 0.379847209f, -0.925049241f, + 0.377007410f, -0.926210242f, + 0.374164063f, -0.927362526f, + 0.371317194f, -0.928506080f, + 0.368466830f, -0.929640896f, + 0.365612998f, -0.930766961f, + 0.362755724f, -0.931884266f, + 0.359895037f, -0.932992799f, + 0.357030961f, -0.934092550f, + 0.354163525f, -0.935183510f, + 0.351292756f, -0.936265667f, + 0.348418680f, -0.937339012f, + 0.345541325f, -0.938403534f, + 0.342660717f, -0.939459224f, + 0.339776884f, -0.940506071f, + 0.336889853f, -0.941544065f, + 0.333999651f, -0.942573198f, + 0.331106306f, -0.943593458f, + 0.328209844f, -0.944604837f, + 0.325310292f, -0.945607325f, + 0.322407679f, -0.946600913f, + 0.319502031f, -0.947585591f, + 0.316593376f, -0.948561350f, + 0.313681740f, -0.949528181f, + 0.310767153f, -0.950486074f, + 0.307849640f, -0.951435021f, + 0.304929230f, -0.952375013f, + 0.302005949f, -0.953306040f, + 0.299079826f, -0.954228095f, + 0.296150888f, -0.955141168f, + 0.293219163f, -0.956045251f, + 0.290284677f, -0.956940336f, + 0.287347460f, -0.957826413f, + 0.284407537f, -0.958703475f, + 0.281464938f, -0.959571513f, + 0.278519689f, -0.960430519f, + 0.275571819f, -0.961280486f, + 0.272621355f, -0.962121404f, + 0.269668326f, -0.962953267f, + 0.266712757f, -0.963776066f, + 0.263754679f, -0.964589793f, + 0.260794118f, -0.965394442f, + 0.257831102f, -0.966190003f, + 0.254865660f, -0.966976471f, + 0.251897818f, -0.967753837f, + 0.248927606f, -0.968522094f, + 0.245955050f, -0.969281235f, + 0.242980180f, -0.970031253f, + 0.240003022f, -0.970772141f, + 0.237023606f, -0.971503891f, + 0.234041959f, -0.972226497f, + 0.231058108f, -0.972939952f, + 0.228072083f, -0.973644250f, + 0.225083911f, -0.974339383f, + 0.222093621f, -0.975025345f, + 0.219101240f, -0.975702130f, + 0.216106797f, -0.976369731f, + 0.213110320f, -0.977028143f, + 0.210111837f, -0.977677358f, + 0.207111376f, -0.978317371f, + 0.204108966f, -0.978948175f, + 0.201104635f, -0.979569766f, + 0.198098411f, -0.980182136f, + 0.195090322f, -0.980785280f, + 0.192080397f, -0.981379193f, + 0.189068664f, -0.981963869f, + 0.186055152f, -0.982539302f, + 0.183039888f, -0.983105487f, + 0.180022901f, -0.983662419f, + 0.177004220f, -0.984210092f, + 0.173983873f, -0.984748502f, + 0.170961889f, -0.985277642f, + 0.167938295f, -0.985797509f, + 0.164913120f, -0.986308097f, + 0.161886394f, -0.986809402f, + 0.158858143f, -0.987301418f, + 0.155828398f, -0.987784142f, + 0.152797185f, -0.988257568f, + 0.149764535f, -0.988721692f, + 0.146730474f, -0.989176510f, + 0.143695033f, -0.989622017f, + 0.140658239f, -0.990058210f, + 0.137620122f, -0.990485084f, + 0.134580709f, -0.990902635f, + 0.131540029f, -0.991310860f, + 0.128498111f, -0.991709754f, + 0.125454983f, -0.992099313f, + 0.122410675f, -0.992479535f, + 0.119365215f, -0.992850414f, + 0.116318631f, -0.993211949f, + 0.113270952f, -0.993564136f, + 0.110222207f, -0.993906970f, + 0.107172425f, -0.994240449f, + 0.104121634f, -0.994564571f, + 0.101069863f, -0.994879331f, + 0.098017140f, -0.995184727f, + 0.094963495f, -0.995480755f, + 0.091908956f, -0.995767414f, + 0.088853553f, -0.996044701f, + 0.085797312f, -0.996312612f, + 0.082740265f, -0.996571146f, + 0.079682438f, -0.996820299f, + 0.076623861f, -0.997060070f, + 0.073564564f, -0.997290457f, + 0.070504573f, -0.997511456f, + 0.067443920f, -0.997723067f, + 0.064382631f, -0.997925286f, + 0.061320736f, -0.998118113f, + 0.058258265f, -0.998301545f, + 0.055195244f, -0.998475581f, + 0.052131705f, -0.998640218f, + 0.049067674f, -0.998795456f, + 0.046003182f, -0.998941293f, + 0.042938257f, -0.999077728f, + 0.039872928f, -0.999204759f, + 0.036807223f, -0.999322385f, + 0.033741172f, -0.999430605f, + 0.030674803f, -0.999529418f, + 0.027608146f, -0.999618822f, + 0.024541229f, -0.999698819f, + 0.021474080f, -0.999769405f, + 0.018406730f, -0.999830582f, + 0.015339206f, -0.999882347f, + 0.012271538f, -0.999924702f, + 0.009203755f, -0.999957645f, + 0.006135885f, -0.999981175f, + 0.003067957f, -0.999995294f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) +const float32_t twiddleCoef_rfft_4096[4096] = { + 0.000000000f, 1.000000000f, + 0.001533980f, 0.999998823f, + 0.003067957f, 0.999995294f, + 0.004601926f, 0.999989411f, + 0.006135885f, 0.999981175f, + 0.007669829f, 0.999970586f, + 0.009203755f, 0.999957645f, + 0.010737659f, 0.999942350f, + 0.012271538f, 0.999924702f, + 0.013805389f, 0.999904701f, + 0.015339206f, 0.999882347f, + 0.016872988f, 0.999857641f, + 0.018406730f, 0.999830582f, + 0.019940429f, 0.999801170f, + 0.021474080f, 0.999769405f, + 0.023007681f, 0.999735288f, + 0.024541229f, 0.999698819f, + 0.026074718f, 0.999659997f, + 0.027608146f, 0.999618822f, + 0.029141509f, 0.999575296f, + 0.030674803f, 0.999529418f, + 0.032208025f, 0.999481187f, + 0.033741172f, 0.999430605f, + 0.035274239f, 0.999377670f, + 0.036807223f, 0.999322385f, + 0.038340120f, 0.999264747f, + 0.039872928f, 0.999204759f, + 0.041405641f, 0.999142419f, + 0.042938257f, 0.999077728f, + 0.044470772f, 0.999010686f, + 0.046003182f, 0.998941293f, + 0.047535484f, 0.998869550f, + 0.049067674f, 0.998795456f, + 0.050599749f, 0.998719012f, + 0.052131705f, 0.998640218f, + 0.053663538f, 0.998559074f, + 0.055195244f, 0.998475581f, + 0.056726821f, 0.998389737f, + 0.058258265f, 0.998301545f, + 0.059789571f, 0.998211003f, + 0.061320736f, 0.998118113f, + 0.062851758f, 0.998022874f, + 0.064382631f, 0.997925286f, + 0.065913353f, 0.997825350f, + 0.067443920f, 0.997723067f, + 0.068974328f, 0.997618435f, + 0.070504573f, 0.997511456f, + 0.072034653f, 0.997402130f, + 0.073564564f, 0.997290457f, + 0.075094301f, 0.997176437f, + 0.076623861f, 0.997060070f, + 0.078153242f, 0.996941358f, + 0.079682438f, 0.996820299f, + 0.081211447f, 0.996696895f, + 0.082740265f, 0.996571146f, + 0.084268888f, 0.996443051f, + 0.085797312f, 0.996312612f, + 0.087325535f, 0.996179829f, + 0.088853553f, 0.996044701f, + 0.090381361f, 0.995907229f, + 0.091908956f, 0.995767414f, + 0.093436336f, 0.995625256f, + 0.094963495f, 0.995480755f, + 0.096490431f, 0.995333912f, + 0.098017140f, 0.995184727f, + 0.099543619f, 0.995033199f, + 0.101069863f, 0.994879331f, + 0.102595869f, 0.994723121f, + 0.104121634f, 0.994564571f, + 0.105647154f, 0.994403680f, + 0.107172425f, 0.994240449f, + 0.108697444f, 0.994074879f, + 0.110222207f, 0.993906970f, + 0.111746711f, 0.993736722f, + 0.113270952f, 0.993564136f, + 0.114794927f, 0.993389211f, + 0.116318631f, 0.993211949f, + 0.117842062f, 0.993032350f, + 0.119365215f, 0.992850414f, + 0.120888087f, 0.992666142f, + 0.122410675f, 0.992479535f, + 0.123932975f, 0.992290591f, + 0.125454983f, 0.992099313f, + 0.126976696f, 0.991905700f, + 0.128498111f, 0.991709754f, + 0.130019223f, 0.991511473f, + 0.131540029f, 0.991310860f, + 0.133060525f, 0.991107914f, + 0.134580709f, 0.990902635f, + 0.136100575f, 0.990695025f, + 0.137620122f, 0.990485084f, + 0.139139344f, 0.990272812f, + 0.140658239f, 0.990058210f, + 0.142176804f, 0.989841278f, + 0.143695033f, 0.989622017f, + 0.145212925f, 0.989400428f, + 0.146730474f, 0.989176510f, + 0.148247679f, 0.988950265f, + 0.149764535f, 0.988721692f, + 0.151281038f, 0.988490793f, + 0.152797185f, 0.988257568f, + 0.154312973f, 0.988022017f, + 0.155828398f, 0.987784142f, + 0.157343456f, 0.987543942f, + 0.158858143f, 0.987301418f, + 0.160372457f, 0.987056571f, + 0.161886394f, 0.986809402f, + 0.163399949f, 0.986559910f, + 0.164913120f, 0.986308097f, + 0.166425904f, 0.986053963f, + 0.167938295f, 0.985797509f, + 0.169450291f, 0.985538735f, + 0.170961889f, 0.985277642f, + 0.172473084f, 0.985014231f, + 0.173983873f, 0.984748502f, + 0.175494253f, 0.984480455f, + 0.177004220f, 0.984210092f, + 0.178513771f, 0.983937413f, + 0.180022901f, 0.983662419f, + 0.181531608f, 0.983385110f, + 0.183039888f, 0.983105487f, + 0.184547737f, 0.982823551f, + 0.186055152f, 0.982539302f, + 0.187562129f, 0.982252741f, + 0.189068664f, 0.981963869f, + 0.190574755f, 0.981672686f, + 0.192080397f, 0.981379193f, + 0.193585587f, 0.981083391f, + 0.195090322f, 0.980785280f, + 0.196594598f, 0.980484862f, + 0.198098411f, 0.980182136f, + 0.199601758f, 0.979877104f, + 0.201104635f, 0.979569766f, + 0.202607039f, 0.979260123f, + 0.204108966f, 0.978948175f, + 0.205610413f, 0.978633924f, + 0.207111376f, 0.978317371f, + 0.208611852f, 0.977998515f, + 0.210111837f, 0.977677358f, + 0.211611327f, 0.977353900f, + 0.213110320f, 0.977028143f, + 0.214608811f, 0.976700086f, + 0.216106797f, 0.976369731f, + 0.217604275f, 0.976037079f, + 0.219101240f, 0.975702130f, + 0.220597690f, 0.975364885f, + 0.222093621f, 0.975025345f, + 0.223589029f, 0.974683511f, + 0.225083911f, 0.974339383f, + 0.226578264f, 0.973992962f, + 0.228072083f, 0.973644250f, + 0.229565366f, 0.973293246f, + 0.231058108f, 0.972939952f, + 0.232550307f, 0.972584369f, + 0.234041959f, 0.972226497f, + 0.235533059f, 0.971866337f, + 0.237023606f, 0.971503891f, + 0.238513595f, 0.971139158f, + 0.240003022f, 0.970772141f, + 0.241491885f, 0.970402839f, + 0.242980180f, 0.970031253f, + 0.244467903f, 0.969657385f, + 0.245955050f, 0.969281235f, + 0.247441619f, 0.968902805f, + 0.248927606f, 0.968522094f, + 0.250413007f, 0.968139105f, + 0.251897818f, 0.967753837f, + 0.253382037f, 0.967366292f, + 0.254865660f, 0.966976471f, + 0.256348682f, 0.966584374f, + 0.257831102f, 0.966190003f, + 0.259312915f, 0.965793359f, + 0.260794118f, 0.965394442f, + 0.262274707f, 0.964993253f, + 0.263754679f, 0.964589793f, + 0.265234030f, 0.964184064f, + 0.266712757f, 0.963776066f, + 0.268190857f, 0.963365800f, + 0.269668326f, 0.962953267f, + 0.271145160f, 0.962538468f, + 0.272621355f, 0.962121404f, + 0.274096910f, 0.961702077f, + 0.275571819f, 0.961280486f, + 0.277046080f, 0.960856633f, + 0.278519689f, 0.960430519f, + 0.279992643f, 0.960002146f, + 0.281464938f, 0.959571513f, + 0.282936570f, 0.959138622f, + 0.284407537f, 0.958703475f, + 0.285877835f, 0.958266071f, + 0.287347460f, 0.957826413f, + 0.288816408f, 0.957384501f, + 0.290284677f, 0.956940336f, + 0.291752263f, 0.956493919f, + 0.293219163f, 0.956045251f, + 0.294685372f, 0.955594334f, + 0.296150888f, 0.955141168f, + 0.297615707f, 0.954685755f, + 0.299079826f, 0.954228095f, + 0.300543241f, 0.953768190f, + 0.302005949f, 0.953306040f, + 0.303467947f, 0.952841648f, + 0.304929230f, 0.952375013f, + 0.306389795f, 0.951906137f, + 0.307849640f, 0.951435021f, + 0.309308760f, 0.950961666f, + 0.310767153f, 0.950486074f, + 0.312224814f, 0.950008245f, + 0.313681740f, 0.949528181f, + 0.315137929f, 0.949045882f, + 0.316593376f, 0.948561350f, + 0.318048077f, 0.948074586f, + 0.319502031f, 0.947585591f, + 0.320955232f, 0.947094366f, + 0.322407679f, 0.946600913f, + 0.323859367f, 0.946105232f, + 0.325310292f, 0.945607325f, + 0.326760452f, 0.945107193f, + 0.328209844f, 0.944604837f, + 0.329658463f, 0.944100258f, + 0.331106306f, 0.943593458f, + 0.332553370f, 0.943084437f, + 0.333999651f, 0.942573198f, + 0.335445147f, 0.942059740f, + 0.336889853f, 0.941544065f, + 0.338333767f, 0.941026175f, + 0.339776884f, 0.940506071f, + 0.341219202f, 0.939983753f, + 0.342660717f, 0.939459224f, + 0.344101426f, 0.938932484f, + 0.345541325f, 0.938403534f, + 0.346980411f, 0.937872376f, + 0.348418680f, 0.937339012f, + 0.349856130f, 0.936803442f, + 0.351292756f, 0.936265667f, + 0.352728556f, 0.935725689f, + 0.354163525f, 0.935183510f, + 0.355597662f, 0.934639130f, + 0.357030961f, 0.934092550f, + 0.358463421f, 0.933543773f, + 0.359895037f, 0.932992799f, + 0.361325806f, 0.932439629f, + 0.362755724f, 0.931884266f, + 0.364184790f, 0.931326709f, + 0.365612998f, 0.930766961f, + 0.367040346f, 0.930205023f, + 0.368466830f, 0.929640896f, + 0.369892447f, 0.929074581f, + 0.371317194f, 0.928506080f, + 0.372741067f, 0.927935395f, + 0.374164063f, 0.927362526f, + 0.375586178f, 0.926787474f, + 0.377007410f, 0.926210242f, + 0.378427755f, 0.925630831f, + 0.379847209f, 0.925049241f, + 0.381265769f, 0.924465474f, + 0.382683432f, 0.923879533f, + 0.384100195f, 0.923291417f, + 0.385516054f, 0.922701128f, + 0.386931006f, 0.922108669f, + 0.388345047f, 0.921514039f, + 0.389758174f, 0.920917242f, + 0.391170384f, 0.920318277f, + 0.392581674f, 0.919717146f, + 0.393992040f, 0.919113852f, + 0.395401479f, 0.918508394f, + 0.396809987f, 0.917900776f, + 0.398217562f, 0.917290997f, + 0.399624200f, 0.916679060f, + 0.401029897f, 0.916064966f, + 0.402434651f, 0.915448716f, + 0.403838458f, 0.914830312f, + 0.405241314f, 0.914209756f, + 0.406643217f, 0.913587048f, + 0.408044163f, 0.912962190f, + 0.409444149f, 0.912335185f, + 0.410843171f, 0.911706032f, + 0.412241227f, 0.911074734f, + 0.413638312f, 0.910441292f, + 0.415034424f, 0.909805708f, + 0.416429560f, 0.909167983f, + 0.417823716f, 0.908528119f, + 0.419216888f, 0.907886116f, + 0.420609074f, 0.907241978f, + 0.422000271f, 0.906595705f, + 0.423390474f, 0.905947298f, + 0.424779681f, 0.905296759f, + 0.426167889f, 0.904644091f, + 0.427555093f, 0.903989293f, + 0.428941292f, 0.903332368f, + 0.430326481f, 0.902673318f, + 0.431710658f, 0.902012144f, + 0.433093819f, 0.901348847f, + 0.434475961f, 0.900683429f, + 0.435857080f, 0.900015892f, + 0.437237174f, 0.899346237f, + 0.438616239f, 0.898674466f, + 0.439994271f, 0.898000580f, + 0.441371269f, 0.897324581f, + 0.442747228f, 0.896646470f, + 0.444122145f, 0.895966250f, + 0.445496017f, 0.895283921f, + 0.446868840f, 0.894599486f, + 0.448240612f, 0.893912945f, + 0.449611330f, 0.893224301f, + 0.450980989f, 0.892533555f, + 0.452349587f, 0.891840709f, + 0.453717121f, 0.891145765f, + 0.455083587f, 0.890448723f, + 0.456448982f, 0.889749586f, + 0.457813304f, 0.889048356f, + 0.459176548f, 0.888345033f, + 0.460538711f, 0.887639620f, + 0.461899791f, 0.886932119f, + 0.463259784f, 0.886222530f, + 0.464618686f, 0.885510856f, + 0.465976496f, 0.884797098f, + 0.467333209f, 0.884081259f, + 0.468688822f, 0.883363339f, + 0.470043332f, 0.882643340f, + 0.471396737f, 0.881921264f, + 0.472749032f, 0.881197113f, + 0.474100215f, 0.880470889f, + 0.475450282f, 0.879742593f, + 0.476799230f, 0.879012226f, + 0.478147056f, 0.878279792f, + 0.479493758f, 0.877545290f, + 0.480839331f, 0.876808724f, + 0.482183772f, 0.876070094f, + 0.483527079f, 0.875329403f, + 0.484869248f, 0.874586652f, + 0.486210276f, 0.873841843f, + 0.487550160f, 0.873094978f, + 0.488888897f, 0.872346059f, + 0.490226483f, 0.871595087f, + 0.491562916f, 0.870842063f, + 0.492898192f, 0.870086991f, + 0.494232309f, 0.869329871f, + 0.495565262f, 0.868570706f, + 0.496897049f, 0.867809497f, + 0.498227667f, 0.867046246f, + 0.499557113f, 0.866280954f, + 0.500885383f, 0.865513624f, + 0.502212474f, 0.864744258f, + 0.503538384f, 0.863972856f, + 0.504863109f, 0.863199422f, + 0.506186645f, 0.862423956f, + 0.507508991f, 0.861646461f, + 0.508830143f, 0.860866939f, + 0.510150097f, 0.860085390f, + 0.511468850f, 0.859301818f, + 0.512786401f, 0.858516224f, + 0.514102744f, 0.857728610f, + 0.515417878f, 0.856938977f, + 0.516731799f, 0.856147328f, + 0.518044504f, 0.855353665f, + 0.519355990f, 0.854557988f, + 0.520666254f, 0.853760301f, + 0.521975293f, 0.852960605f, + 0.523283103f, 0.852158902f, + 0.524589683f, 0.851355193f, + 0.525895027f, 0.850549481f, + 0.527199135f, 0.849741768f, + 0.528502002f, 0.848932055f, + 0.529803625f, 0.848120345f, + 0.531104001f, 0.847306639f, + 0.532403128f, 0.846490939f, + 0.533701002f, 0.845673247f, + 0.534997620f, 0.844853565f, + 0.536292979f, 0.844031895f, + 0.537587076f, 0.843208240f, + 0.538879909f, 0.842382600f, + 0.540171473f, 0.841554977f, + 0.541461766f, 0.840725375f, + 0.542750785f, 0.839893794f, + 0.544038527f, 0.839060237f, + 0.545324988f, 0.838224706f, + 0.546610167f, 0.837387202f, + 0.547894059f, 0.836547727f, + 0.549176662f, 0.835706284f, + 0.550457973f, 0.834862875f, + 0.551737988f, 0.834017501f, + 0.553016706f, 0.833170165f, + 0.554294121f, 0.832320868f, + 0.555570233f, 0.831469612f, + 0.556845037f, 0.830616400f, + 0.558118531f, 0.829761234f, + 0.559390712f, 0.828904115f, + 0.560661576f, 0.828045045f, + 0.561931121f, 0.827184027f, + 0.563199344f, 0.826321063f, + 0.564466242f, 0.825456154f, + 0.565731811f, 0.824589303f, + 0.566996049f, 0.823720511f, + 0.568258953f, 0.822849781f, + 0.569520519f, 0.821977115f, + 0.570780746f, 0.821102515f, + 0.572039629f, 0.820225983f, + 0.573297167f, 0.819347520f, + 0.574553355f, 0.818467130f, + 0.575808191f, 0.817584813f, + 0.577061673f, 0.816700573f, + 0.578313796f, 0.815814411f, + 0.579564559f, 0.814926329f, + 0.580813958f, 0.814036330f, + 0.582061990f, 0.813144415f, + 0.583308653f, 0.812250587f, + 0.584553943f, 0.811354847f, + 0.585797857f, 0.810457198f, + 0.587040394f, 0.809557642f, + 0.588281548f, 0.808656182f, + 0.589521319f, 0.807752818f, + 0.590759702f, 0.806847554f, + 0.591996695f, 0.805940391f, + 0.593232295f, 0.805031331f, + 0.594466499f, 0.804120377f, + 0.595699304f, 0.803207531f, + 0.596930708f, 0.802292796f, + 0.598160707f, 0.801376172f, + 0.599389298f, 0.800457662f, + 0.600616479f, 0.799537269f, + 0.601842247f, 0.798614995f, + 0.603066599f, 0.797690841f, + 0.604289531f, 0.796764810f, + 0.605511041f, 0.795836905f, + 0.606731127f, 0.794907126f, + 0.607949785f, 0.793975478f, + 0.609167012f, 0.793041960f, + 0.610382806f, 0.792106577f, + 0.611597164f, 0.791169330f, + 0.612810082f, 0.790230221f, + 0.614021559f, 0.789289253f, + 0.615231591f, 0.788346428f, + 0.616440175f, 0.787401747f, + 0.617647308f, 0.786455214f, + 0.618852988f, 0.785506830f, + 0.620057212f, 0.784556597f, + 0.621259977f, 0.783604519f, + 0.622461279f, 0.782650596f, + 0.623661118f, 0.781694832f, + 0.624859488f, 0.780737229f, + 0.626056388f, 0.779777788f, + 0.627251815f, 0.778816512f, + 0.628445767f, 0.777853404f, + 0.629638239f, 0.776888466f, + 0.630829230f, 0.775921699f, + 0.632018736f, 0.774953107f, + 0.633206755f, 0.773982691f, + 0.634393284f, 0.773010453f, + 0.635578320f, 0.772036397f, + 0.636761861f, 0.771060524f, + 0.637943904f, 0.770082837f, + 0.639124445f, 0.769103338f, + 0.640303482f, 0.768122029f, + 0.641481013f, 0.767138912f, + 0.642657034f, 0.766153990f, + 0.643831543f, 0.765167266f, + 0.645004537f, 0.764178741f, + 0.646176013f, 0.763188417f, + 0.647345969f, 0.762196298f, + 0.648514401f, 0.761202385f, + 0.649681307f, 0.760206682f, + 0.650846685f, 0.759209189f, + 0.652010531f, 0.758209910f, + 0.653172843f, 0.757208847f, + 0.654333618f, 0.756206001f, + 0.655492853f, 0.755201377f, + 0.656650546f, 0.754194975f, + 0.657806693f, 0.753186799f, + 0.658961293f, 0.752176850f, + 0.660114342f, 0.751165132f, + 0.661265838f, 0.750151646f, + 0.662415778f, 0.749136395f, + 0.663564159f, 0.748119380f, + 0.664710978f, 0.747100606f, + 0.665856234f, 0.746080074f, + 0.666999922f, 0.745057785f, + 0.668142041f, 0.744033744f, + 0.669282588f, 0.743007952f, + 0.670421560f, 0.741980412f, + 0.671558955f, 0.740951125f, + 0.672694769f, 0.739920095f, + 0.673829000f, 0.738887324f, + 0.674961646f, 0.737852815f, + 0.676092704f, 0.736816569f, + 0.677222170f, 0.735778589f, + 0.678350043f, 0.734738878f, + 0.679476320f, 0.733697438f, + 0.680600998f, 0.732654272f, + 0.681724074f, 0.731609381f, + 0.682845546f, 0.730562769f, + 0.683965412f, 0.729514438f, + 0.685083668f, 0.728464390f, + 0.686200312f, 0.727412629f, + 0.687315341f, 0.726359155f, + 0.688428753f, 0.725303972f, + 0.689540545f, 0.724247083f, + 0.690650714f, 0.723188489f, + 0.691759258f, 0.722128194f, + 0.692866175f, 0.721066199f, + 0.693971461f, 0.720002508f, + 0.695075114f, 0.718937122f, + 0.696177131f, 0.717870045f, + 0.697277511f, 0.716801279f, + 0.698376249f, 0.715730825f, + 0.699473345f, 0.714658688f, + 0.700568794f, 0.713584869f, + 0.701662595f, 0.712509371f, + 0.702754744f, 0.711432196f, + 0.703845241f, 0.710353347f, + 0.704934080f, 0.709272826f, + 0.706021261f, 0.708190637f, + 0.707106781f, 0.707106781f, + 0.708190637f, 0.706021261f, + 0.709272826f, 0.704934080f, + 0.710353347f, 0.703845241f, + 0.711432196f, 0.702754744f, + 0.712509371f, 0.701662595f, + 0.713584869f, 0.700568794f, + 0.714658688f, 0.699473345f, + 0.715730825f, 0.698376249f, + 0.716801279f, 0.697277511f, + 0.717870045f, 0.696177131f, + 0.718937122f, 0.695075114f, + 0.720002508f, 0.693971461f, + 0.721066199f, 0.692866175f, + 0.722128194f, 0.691759258f, + 0.723188489f, 0.690650714f, + 0.724247083f, 0.689540545f, + 0.725303972f, 0.688428753f, + 0.726359155f, 0.687315341f, + 0.727412629f, 0.686200312f, + 0.728464390f, 0.685083668f, + 0.729514438f, 0.683965412f, + 0.730562769f, 0.682845546f, + 0.731609381f, 0.681724074f, + 0.732654272f, 0.680600998f, + 0.733697438f, 0.679476320f, + 0.734738878f, 0.678350043f, + 0.735778589f, 0.677222170f, + 0.736816569f, 0.676092704f, + 0.737852815f, 0.674961646f, + 0.738887324f, 0.673829000f, + 0.739920095f, 0.672694769f, + 0.740951125f, 0.671558955f, + 0.741980412f, 0.670421560f, + 0.743007952f, 0.669282588f, + 0.744033744f, 0.668142041f, + 0.745057785f, 0.666999922f, + 0.746080074f, 0.665856234f, + 0.747100606f, 0.664710978f, + 0.748119380f, 0.663564159f, + 0.749136395f, 0.662415778f, + 0.750151646f, 0.661265838f, + 0.751165132f, 0.660114342f, + 0.752176850f, 0.658961293f, + 0.753186799f, 0.657806693f, + 0.754194975f, 0.656650546f, + 0.755201377f, 0.655492853f, + 0.756206001f, 0.654333618f, + 0.757208847f, 0.653172843f, + 0.758209910f, 0.652010531f, + 0.759209189f, 0.650846685f, + 0.760206682f, 0.649681307f, + 0.761202385f, 0.648514401f, + 0.762196298f, 0.647345969f, + 0.763188417f, 0.646176013f, + 0.764178741f, 0.645004537f, + 0.765167266f, 0.643831543f, + 0.766153990f, 0.642657034f, + 0.767138912f, 0.641481013f, + 0.768122029f, 0.640303482f, + 0.769103338f, 0.639124445f, + 0.770082837f, 0.637943904f, + 0.771060524f, 0.636761861f, + 0.772036397f, 0.635578320f, + 0.773010453f, 0.634393284f, + 0.773982691f, 0.633206755f, + 0.774953107f, 0.632018736f, + 0.775921699f, 0.630829230f, + 0.776888466f, 0.629638239f, + 0.777853404f, 0.628445767f, + 0.778816512f, 0.627251815f, + 0.779777788f, 0.626056388f, + 0.780737229f, 0.624859488f, + 0.781694832f, 0.623661118f, + 0.782650596f, 0.622461279f, + 0.783604519f, 0.621259977f, + 0.784556597f, 0.620057212f, + 0.785506830f, 0.618852988f, + 0.786455214f, 0.617647308f, + 0.787401747f, 0.616440175f, + 0.788346428f, 0.615231591f, + 0.789289253f, 0.614021559f, + 0.790230221f, 0.612810082f, + 0.791169330f, 0.611597164f, + 0.792106577f, 0.610382806f, + 0.793041960f, 0.609167012f, + 0.793975478f, 0.607949785f, + 0.794907126f, 0.606731127f, + 0.795836905f, 0.605511041f, + 0.796764810f, 0.604289531f, + 0.797690841f, 0.603066599f, + 0.798614995f, 0.601842247f, + 0.799537269f, 0.600616479f, + 0.800457662f, 0.599389298f, + 0.801376172f, 0.598160707f, + 0.802292796f, 0.596930708f, + 0.803207531f, 0.595699304f, + 0.804120377f, 0.594466499f, + 0.805031331f, 0.593232295f, + 0.805940391f, 0.591996695f, + 0.806847554f, 0.590759702f, + 0.807752818f, 0.589521319f, + 0.808656182f, 0.588281548f, + 0.809557642f, 0.587040394f, + 0.810457198f, 0.585797857f, + 0.811354847f, 0.584553943f, + 0.812250587f, 0.583308653f, + 0.813144415f, 0.582061990f, + 0.814036330f, 0.580813958f, + 0.814926329f, 0.579564559f, + 0.815814411f, 0.578313796f, + 0.816700573f, 0.577061673f, + 0.817584813f, 0.575808191f, + 0.818467130f, 0.574553355f, + 0.819347520f, 0.573297167f, + 0.820225983f, 0.572039629f, + 0.821102515f, 0.570780746f, + 0.821977115f, 0.569520519f, + 0.822849781f, 0.568258953f, + 0.823720511f, 0.566996049f, + 0.824589303f, 0.565731811f, + 0.825456154f, 0.564466242f, + 0.826321063f, 0.563199344f, + 0.827184027f, 0.561931121f, + 0.828045045f, 0.560661576f, + 0.828904115f, 0.559390712f, + 0.829761234f, 0.558118531f, + 0.830616400f, 0.556845037f, + 0.831469612f, 0.555570233f, + 0.832320868f, 0.554294121f, + 0.833170165f, 0.553016706f, + 0.834017501f, 0.551737988f, + 0.834862875f, 0.550457973f, + 0.835706284f, 0.549176662f, + 0.836547727f, 0.547894059f, + 0.837387202f, 0.546610167f, + 0.838224706f, 0.545324988f, + 0.839060237f, 0.544038527f, + 0.839893794f, 0.542750785f, + 0.840725375f, 0.541461766f, + 0.841554977f, 0.540171473f, + 0.842382600f, 0.538879909f, + 0.843208240f, 0.537587076f, + 0.844031895f, 0.536292979f, + 0.844853565f, 0.534997620f, + 0.845673247f, 0.533701002f, + 0.846490939f, 0.532403128f, + 0.847306639f, 0.531104001f, + 0.848120345f, 0.529803625f, + 0.848932055f, 0.528502002f, + 0.849741768f, 0.527199135f, + 0.850549481f, 0.525895027f, + 0.851355193f, 0.524589683f, + 0.852158902f, 0.523283103f, + 0.852960605f, 0.521975293f, + 0.853760301f, 0.520666254f, + 0.854557988f, 0.519355990f, + 0.855353665f, 0.518044504f, + 0.856147328f, 0.516731799f, + 0.856938977f, 0.515417878f, + 0.857728610f, 0.514102744f, + 0.858516224f, 0.512786401f, + 0.859301818f, 0.511468850f, + 0.860085390f, 0.510150097f, + 0.860866939f, 0.508830143f, + 0.861646461f, 0.507508991f, + 0.862423956f, 0.506186645f, + 0.863199422f, 0.504863109f, + 0.863972856f, 0.503538384f, + 0.864744258f, 0.502212474f, + 0.865513624f, 0.500885383f, + 0.866280954f, 0.499557113f, + 0.867046246f, 0.498227667f, + 0.867809497f, 0.496897049f, + 0.868570706f, 0.495565262f, + 0.869329871f, 0.494232309f, + 0.870086991f, 0.492898192f, + 0.870842063f, 0.491562916f, + 0.871595087f, 0.490226483f, + 0.872346059f, 0.488888897f, + 0.873094978f, 0.487550160f, + 0.873841843f, 0.486210276f, + 0.874586652f, 0.484869248f, + 0.875329403f, 0.483527079f, + 0.876070094f, 0.482183772f, + 0.876808724f, 0.480839331f, + 0.877545290f, 0.479493758f, + 0.878279792f, 0.478147056f, + 0.879012226f, 0.476799230f, + 0.879742593f, 0.475450282f, + 0.880470889f, 0.474100215f, + 0.881197113f, 0.472749032f, + 0.881921264f, 0.471396737f, + 0.882643340f, 0.470043332f, + 0.883363339f, 0.468688822f, + 0.884081259f, 0.467333209f, + 0.884797098f, 0.465976496f, + 0.885510856f, 0.464618686f, + 0.886222530f, 0.463259784f, + 0.886932119f, 0.461899791f, + 0.887639620f, 0.460538711f, + 0.888345033f, 0.459176548f, + 0.889048356f, 0.457813304f, + 0.889749586f, 0.456448982f, + 0.890448723f, 0.455083587f, + 0.891145765f, 0.453717121f, + 0.891840709f, 0.452349587f, + 0.892533555f, 0.450980989f, + 0.893224301f, 0.449611330f, + 0.893912945f, 0.448240612f, + 0.894599486f, 0.446868840f, + 0.895283921f, 0.445496017f, + 0.895966250f, 0.444122145f, + 0.896646470f, 0.442747228f, + 0.897324581f, 0.441371269f, + 0.898000580f, 0.439994271f, + 0.898674466f, 0.438616239f, + 0.899346237f, 0.437237174f, + 0.900015892f, 0.435857080f, + 0.900683429f, 0.434475961f, + 0.901348847f, 0.433093819f, + 0.902012144f, 0.431710658f, + 0.902673318f, 0.430326481f, + 0.903332368f, 0.428941292f, + 0.903989293f, 0.427555093f, + 0.904644091f, 0.426167889f, + 0.905296759f, 0.424779681f, + 0.905947298f, 0.423390474f, + 0.906595705f, 0.422000271f, + 0.907241978f, 0.420609074f, + 0.907886116f, 0.419216888f, + 0.908528119f, 0.417823716f, + 0.909167983f, 0.416429560f, + 0.909805708f, 0.415034424f, + 0.910441292f, 0.413638312f, + 0.911074734f, 0.412241227f, + 0.911706032f, 0.410843171f, + 0.912335185f, 0.409444149f, + 0.912962190f, 0.408044163f, + 0.913587048f, 0.406643217f, + 0.914209756f, 0.405241314f, + 0.914830312f, 0.403838458f, + 0.915448716f, 0.402434651f, + 0.916064966f, 0.401029897f, + 0.916679060f, 0.399624200f, + 0.917290997f, 0.398217562f, + 0.917900776f, 0.396809987f, + 0.918508394f, 0.395401479f, + 0.919113852f, 0.393992040f, + 0.919717146f, 0.392581674f, + 0.920318277f, 0.391170384f, + 0.920917242f, 0.389758174f, + 0.921514039f, 0.388345047f, + 0.922108669f, 0.386931006f, + 0.922701128f, 0.385516054f, + 0.923291417f, 0.384100195f, + 0.923879533f, 0.382683432f, + 0.924465474f, 0.381265769f, + 0.925049241f, 0.379847209f, + 0.925630831f, 0.378427755f, + 0.926210242f, 0.377007410f, + 0.926787474f, 0.375586178f, + 0.927362526f, 0.374164063f, + 0.927935395f, 0.372741067f, + 0.928506080f, 0.371317194f, + 0.929074581f, 0.369892447f, + 0.929640896f, 0.368466830f, + 0.930205023f, 0.367040346f, + 0.930766961f, 0.365612998f, + 0.931326709f, 0.364184790f, + 0.931884266f, 0.362755724f, + 0.932439629f, 0.361325806f, + 0.932992799f, 0.359895037f, + 0.933543773f, 0.358463421f, + 0.934092550f, 0.357030961f, + 0.934639130f, 0.355597662f, + 0.935183510f, 0.354163525f, + 0.935725689f, 0.352728556f, + 0.936265667f, 0.351292756f, + 0.936803442f, 0.349856130f, + 0.937339012f, 0.348418680f, + 0.937872376f, 0.346980411f, + 0.938403534f, 0.345541325f, + 0.938932484f, 0.344101426f, + 0.939459224f, 0.342660717f, + 0.939983753f, 0.341219202f, + 0.940506071f, 0.339776884f, + 0.941026175f, 0.338333767f, + 0.941544065f, 0.336889853f, + 0.942059740f, 0.335445147f, + 0.942573198f, 0.333999651f, + 0.943084437f, 0.332553370f, + 0.943593458f, 0.331106306f, + 0.944100258f, 0.329658463f, + 0.944604837f, 0.328209844f, + 0.945107193f, 0.326760452f, + 0.945607325f, 0.325310292f, + 0.946105232f, 0.323859367f, + 0.946600913f, 0.322407679f, + 0.947094366f, 0.320955232f, + 0.947585591f, 0.319502031f, + 0.948074586f, 0.318048077f, + 0.948561350f, 0.316593376f, + 0.949045882f, 0.315137929f, + 0.949528181f, 0.313681740f, + 0.950008245f, 0.312224814f, + 0.950486074f, 0.310767153f, + 0.950961666f, 0.309308760f, + 0.951435021f, 0.307849640f, + 0.951906137f, 0.306389795f, + 0.952375013f, 0.304929230f, + 0.952841648f, 0.303467947f, + 0.953306040f, 0.302005949f, + 0.953768190f, 0.300543241f, + 0.954228095f, 0.299079826f, + 0.954685755f, 0.297615707f, + 0.955141168f, 0.296150888f, + 0.955594334f, 0.294685372f, + 0.956045251f, 0.293219163f, + 0.956493919f, 0.291752263f, + 0.956940336f, 0.290284677f, + 0.957384501f, 0.288816408f, + 0.957826413f, 0.287347460f, + 0.958266071f, 0.285877835f, + 0.958703475f, 0.284407537f, + 0.959138622f, 0.282936570f, + 0.959571513f, 0.281464938f, + 0.960002146f, 0.279992643f, + 0.960430519f, 0.278519689f, + 0.960856633f, 0.277046080f, + 0.961280486f, 0.275571819f, + 0.961702077f, 0.274096910f, + 0.962121404f, 0.272621355f, + 0.962538468f, 0.271145160f, + 0.962953267f, 0.269668326f, + 0.963365800f, 0.268190857f, + 0.963776066f, 0.266712757f, + 0.964184064f, 0.265234030f, + 0.964589793f, 0.263754679f, + 0.964993253f, 0.262274707f, + 0.965394442f, 0.260794118f, + 0.965793359f, 0.259312915f, + 0.966190003f, 0.257831102f, + 0.966584374f, 0.256348682f, + 0.966976471f, 0.254865660f, + 0.967366292f, 0.253382037f, + 0.967753837f, 0.251897818f, + 0.968139105f, 0.250413007f, + 0.968522094f, 0.248927606f, + 0.968902805f, 0.247441619f, + 0.969281235f, 0.245955050f, + 0.969657385f, 0.244467903f, + 0.970031253f, 0.242980180f, + 0.970402839f, 0.241491885f, + 0.970772141f, 0.240003022f, + 0.971139158f, 0.238513595f, + 0.971503891f, 0.237023606f, + 0.971866337f, 0.235533059f, + 0.972226497f, 0.234041959f, + 0.972584369f, 0.232550307f, + 0.972939952f, 0.231058108f, + 0.973293246f, 0.229565366f, + 0.973644250f, 0.228072083f, + 0.973992962f, 0.226578264f, + 0.974339383f, 0.225083911f, + 0.974683511f, 0.223589029f, + 0.975025345f, 0.222093621f, + 0.975364885f, 0.220597690f, + 0.975702130f, 0.219101240f, + 0.976037079f, 0.217604275f, + 0.976369731f, 0.216106797f, + 0.976700086f, 0.214608811f, + 0.977028143f, 0.213110320f, + 0.977353900f, 0.211611327f, + 0.977677358f, 0.210111837f, + 0.977998515f, 0.208611852f, + 0.978317371f, 0.207111376f, + 0.978633924f, 0.205610413f, + 0.978948175f, 0.204108966f, + 0.979260123f, 0.202607039f, + 0.979569766f, 0.201104635f, + 0.979877104f, 0.199601758f, + 0.980182136f, 0.198098411f, + 0.980484862f, 0.196594598f, + 0.980785280f, 0.195090322f, + 0.981083391f, 0.193585587f, + 0.981379193f, 0.192080397f, + 0.981672686f, 0.190574755f, + 0.981963869f, 0.189068664f, + 0.982252741f, 0.187562129f, + 0.982539302f, 0.186055152f, + 0.982823551f, 0.184547737f, + 0.983105487f, 0.183039888f, + 0.983385110f, 0.181531608f, + 0.983662419f, 0.180022901f, + 0.983937413f, 0.178513771f, + 0.984210092f, 0.177004220f, + 0.984480455f, 0.175494253f, + 0.984748502f, 0.173983873f, + 0.985014231f, 0.172473084f, + 0.985277642f, 0.170961889f, + 0.985538735f, 0.169450291f, + 0.985797509f, 0.167938295f, + 0.986053963f, 0.166425904f, + 0.986308097f, 0.164913120f, + 0.986559910f, 0.163399949f, + 0.986809402f, 0.161886394f, + 0.987056571f, 0.160372457f, + 0.987301418f, 0.158858143f, + 0.987543942f, 0.157343456f, + 0.987784142f, 0.155828398f, + 0.988022017f, 0.154312973f, + 0.988257568f, 0.152797185f, + 0.988490793f, 0.151281038f, + 0.988721692f, 0.149764535f, + 0.988950265f, 0.148247679f, + 0.989176510f, 0.146730474f, + 0.989400428f, 0.145212925f, + 0.989622017f, 0.143695033f, + 0.989841278f, 0.142176804f, + 0.990058210f, 0.140658239f, + 0.990272812f, 0.139139344f, + 0.990485084f, 0.137620122f, + 0.990695025f, 0.136100575f, + 0.990902635f, 0.134580709f, + 0.991107914f, 0.133060525f, + 0.991310860f, 0.131540029f, + 0.991511473f, 0.130019223f, + 0.991709754f, 0.128498111f, + 0.991905700f, 0.126976696f, + 0.992099313f, 0.125454983f, + 0.992290591f, 0.123932975f, + 0.992479535f, 0.122410675f, + 0.992666142f, 0.120888087f, + 0.992850414f, 0.119365215f, + 0.993032350f, 0.117842062f, + 0.993211949f, 0.116318631f, + 0.993389211f, 0.114794927f, + 0.993564136f, 0.113270952f, + 0.993736722f, 0.111746711f, + 0.993906970f, 0.110222207f, + 0.994074879f, 0.108697444f, + 0.994240449f, 0.107172425f, + 0.994403680f, 0.105647154f, + 0.994564571f, 0.104121634f, + 0.994723121f, 0.102595869f, + 0.994879331f, 0.101069863f, + 0.995033199f, 0.099543619f, + 0.995184727f, 0.098017140f, + 0.995333912f, 0.096490431f, + 0.995480755f, 0.094963495f, + 0.995625256f, 0.093436336f, + 0.995767414f, 0.091908956f, + 0.995907229f, 0.090381361f, + 0.996044701f, 0.088853553f, + 0.996179829f, 0.087325535f, + 0.996312612f, 0.085797312f, + 0.996443051f, 0.084268888f, + 0.996571146f, 0.082740265f, + 0.996696895f, 0.081211447f, + 0.996820299f, 0.079682438f, + 0.996941358f, 0.078153242f, + 0.997060070f, 0.076623861f, + 0.997176437f, 0.075094301f, + 0.997290457f, 0.073564564f, + 0.997402130f, 0.072034653f, + 0.997511456f, 0.070504573f, + 0.997618435f, 0.068974328f, + 0.997723067f, 0.067443920f, + 0.997825350f, 0.065913353f, + 0.997925286f, 0.064382631f, + 0.998022874f, 0.062851758f, + 0.998118113f, 0.061320736f, + 0.998211003f, 0.059789571f, + 0.998301545f, 0.058258265f, + 0.998389737f, 0.056726821f, + 0.998475581f, 0.055195244f, + 0.998559074f, 0.053663538f, + 0.998640218f, 0.052131705f, + 0.998719012f, 0.050599749f, + 0.998795456f, 0.049067674f, + 0.998869550f, 0.047535484f, + 0.998941293f, 0.046003182f, + 0.999010686f, 0.044470772f, + 0.999077728f, 0.042938257f, + 0.999142419f, 0.041405641f, + 0.999204759f, 0.039872928f, + 0.999264747f, 0.038340120f, + 0.999322385f, 0.036807223f, + 0.999377670f, 0.035274239f, + 0.999430605f, 0.033741172f, + 0.999481187f, 0.032208025f, + 0.999529418f, 0.030674803f, + 0.999575296f, 0.029141509f, + 0.999618822f, 0.027608146f, + 0.999659997f, 0.026074718f, + 0.999698819f, 0.024541229f, + 0.999735288f, 0.023007681f, + 0.999769405f, 0.021474080f, + 0.999801170f, 0.019940429f, + 0.999830582f, 0.018406730f, + 0.999857641f, 0.016872988f, + 0.999882347f, 0.015339206f, + 0.999904701f, 0.013805389f, + 0.999924702f, 0.012271538f, + 0.999942350f, 0.010737659f, + 0.999957645f, 0.009203755f, + 0.999970586f, 0.007669829f, + 0.999981175f, 0.006135885f, + 0.999989411f, 0.004601926f, + 0.999995294f, 0.003067957f, + 0.999998823f, 0.001533980f, + 1.000000000f, 0.000000000f, + 0.999998823f, -0.001533980f, + 0.999995294f, -0.003067957f, + 0.999989411f, -0.004601926f, + 0.999981175f, -0.006135885f, + 0.999970586f, -0.007669829f, + 0.999957645f, -0.009203755f, + 0.999942350f, -0.010737659f, + 0.999924702f, -0.012271538f, + 0.999904701f, -0.013805389f, + 0.999882347f, -0.015339206f, + 0.999857641f, -0.016872988f, + 0.999830582f, -0.018406730f, + 0.999801170f, -0.019940429f, + 0.999769405f, -0.021474080f, + 0.999735288f, -0.023007681f, + 0.999698819f, -0.024541229f, + 0.999659997f, -0.026074718f, + 0.999618822f, -0.027608146f, + 0.999575296f, -0.029141509f, + 0.999529418f, -0.030674803f, + 0.999481187f, -0.032208025f, + 0.999430605f, -0.033741172f, + 0.999377670f, -0.035274239f, + 0.999322385f, -0.036807223f, + 0.999264747f, -0.038340120f, + 0.999204759f, -0.039872928f, + 0.999142419f, -0.041405641f, + 0.999077728f, -0.042938257f, + 0.999010686f, -0.044470772f, + 0.998941293f, -0.046003182f, + 0.998869550f, -0.047535484f, + 0.998795456f, -0.049067674f, + 0.998719012f, -0.050599749f, + 0.998640218f, -0.052131705f, + 0.998559074f, -0.053663538f, + 0.998475581f, -0.055195244f, + 0.998389737f, -0.056726821f, + 0.998301545f, -0.058258265f, + 0.998211003f, -0.059789571f, + 0.998118113f, -0.061320736f, + 0.998022874f, -0.062851758f, + 0.997925286f, -0.064382631f, + 0.997825350f, -0.065913353f, + 0.997723067f, -0.067443920f, + 0.997618435f, -0.068974328f, + 0.997511456f, -0.070504573f, + 0.997402130f, -0.072034653f, + 0.997290457f, -0.073564564f, + 0.997176437f, -0.075094301f, + 0.997060070f, -0.076623861f, + 0.996941358f, -0.078153242f, + 0.996820299f, -0.079682438f, + 0.996696895f, -0.081211447f, + 0.996571146f, -0.082740265f, + 0.996443051f, -0.084268888f, + 0.996312612f, -0.085797312f, + 0.996179829f, -0.087325535f, + 0.996044701f, -0.088853553f, + 0.995907229f, -0.090381361f, + 0.995767414f, -0.091908956f, + 0.995625256f, -0.093436336f, + 0.995480755f, -0.094963495f, + 0.995333912f, -0.096490431f, + 0.995184727f, -0.098017140f, + 0.995033199f, -0.099543619f, + 0.994879331f, -0.101069863f, + 0.994723121f, -0.102595869f, + 0.994564571f, -0.104121634f, + 0.994403680f, -0.105647154f, + 0.994240449f, -0.107172425f, + 0.994074879f, -0.108697444f, + 0.993906970f, -0.110222207f, + 0.993736722f, -0.111746711f, + 0.993564136f, -0.113270952f, + 0.993389211f, -0.114794927f, + 0.993211949f, -0.116318631f, + 0.993032350f, -0.117842062f, + 0.992850414f, -0.119365215f, + 0.992666142f, -0.120888087f, + 0.992479535f, -0.122410675f, + 0.992290591f, -0.123932975f, + 0.992099313f, -0.125454983f, + 0.991905700f, -0.126976696f, + 0.991709754f, -0.128498111f, + 0.991511473f, -0.130019223f, + 0.991310860f, -0.131540029f, + 0.991107914f, -0.133060525f, + 0.990902635f, -0.134580709f, + 0.990695025f, -0.136100575f, + 0.990485084f, -0.137620122f, + 0.990272812f, -0.139139344f, + 0.990058210f, -0.140658239f, + 0.989841278f, -0.142176804f, + 0.989622017f, -0.143695033f, + 0.989400428f, -0.145212925f, + 0.989176510f, -0.146730474f, + 0.988950265f, -0.148247679f, + 0.988721692f, -0.149764535f, + 0.988490793f, -0.151281038f, + 0.988257568f, -0.152797185f, + 0.988022017f, -0.154312973f, + 0.987784142f, -0.155828398f, + 0.987543942f, -0.157343456f, + 0.987301418f, -0.158858143f, + 0.987056571f, -0.160372457f, + 0.986809402f, -0.161886394f, + 0.986559910f, -0.163399949f, + 0.986308097f, -0.164913120f, + 0.986053963f, -0.166425904f, + 0.985797509f, -0.167938295f, + 0.985538735f, -0.169450291f, + 0.985277642f, -0.170961889f, + 0.985014231f, -0.172473084f, + 0.984748502f, -0.173983873f, + 0.984480455f, -0.175494253f, + 0.984210092f, -0.177004220f, + 0.983937413f, -0.178513771f, + 0.983662419f, -0.180022901f, + 0.983385110f, -0.181531608f, + 0.983105487f, -0.183039888f, + 0.982823551f, -0.184547737f, + 0.982539302f, -0.186055152f, + 0.982252741f, -0.187562129f, + 0.981963869f, -0.189068664f, + 0.981672686f, -0.190574755f, + 0.981379193f, -0.192080397f, + 0.981083391f, -0.193585587f, + 0.980785280f, -0.195090322f, + 0.980484862f, -0.196594598f, + 0.980182136f, -0.198098411f, + 0.979877104f, -0.199601758f, + 0.979569766f, -0.201104635f, + 0.979260123f, -0.202607039f, + 0.978948175f, -0.204108966f, + 0.978633924f, -0.205610413f, + 0.978317371f, -0.207111376f, + 0.977998515f, -0.208611852f, + 0.977677358f, -0.210111837f, + 0.977353900f, -0.211611327f, + 0.977028143f, -0.213110320f, + 0.976700086f, -0.214608811f, + 0.976369731f, -0.216106797f, + 0.976037079f, -0.217604275f, + 0.975702130f, -0.219101240f, + 0.975364885f, -0.220597690f, + 0.975025345f, -0.222093621f, + 0.974683511f, -0.223589029f, + 0.974339383f, -0.225083911f, + 0.973992962f, -0.226578264f, + 0.973644250f, -0.228072083f, + 0.973293246f, -0.229565366f, + 0.972939952f, -0.231058108f, + 0.972584369f, -0.232550307f, + 0.972226497f, -0.234041959f, + 0.971866337f, -0.235533059f, + 0.971503891f, -0.237023606f, + 0.971139158f, -0.238513595f, + 0.970772141f, -0.240003022f, + 0.970402839f, -0.241491885f, + 0.970031253f, -0.242980180f, + 0.969657385f, -0.244467903f, + 0.969281235f, -0.245955050f, + 0.968902805f, -0.247441619f, + 0.968522094f, -0.248927606f, + 0.968139105f, -0.250413007f, + 0.967753837f, -0.251897818f, + 0.967366292f, -0.253382037f, + 0.966976471f, -0.254865660f, + 0.966584374f, -0.256348682f, + 0.966190003f, -0.257831102f, + 0.965793359f, -0.259312915f, + 0.965394442f, -0.260794118f, + 0.964993253f, -0.262274707f, + 0.964589793f, -0.263754679f, + 0.964184064f, -0.265234030f, + 0.963776066f, -0.266712757f, + 0.963365800f, -0.268190857f, + 0.962953267f, -0.269668326f, + 0.962538468f, -0.271145160f, + 0.962121404f, -0.272621355f, + 0.961702077f, -0.274096910f, + 0.961280486f, -0.275571819f, + 0.960856633f, -0.277046080f, + 0.960430519f, -0.278519689f, + 0.960002146f, -0.279992643f, + 0.959571513f, -0.281464938f, + 0.959138622f, -0.282936570f, + 0.958703475f, -0.284407537f, + 0.958266071f, -0.285877835f, + 0.957826413f, -0.287347460f, + 0.957384501f, -0.288816408f, + 0.956940336f, -0.290284677f, + 0.956493919f, -0.291752263f, + 0.956045251f, -0.293219163f, + 0.955594334f, -0.294685372f, + 0.955141168f, -0.296150888f, + 0.954685755f, -0.297615707f, + 0.954228095f, -0.299079826f, + 0.953768190f, -0.300543241f, + 0.953306040f, -0.302005949f, + 0.952841648f, -0.303467947f, + 0.952375013f, -0.304929230f, + 0.951906137f, -0.306389795f, + 0.951435021f, -0.307849640f, + 0.950961666f, -0.309308760f, + 0.950486074f, -0.310767153f, + 0.950008245f, -0.312224814f, + 0.949528181f, -0.313681740f, + 0.949045882f, -0.315137929f, + 0.948561350f, -0.316593376f, + 0.948074586f, -0.318048077f, + 0.947585591f, -0.319502031f, + 0.947094366f, -0.320955232f, + 0.946600913f, -0.322407679f, + 0.946105232f, -0.323859367f, + 0.945607325f, -0.325310292f, + 0.945107193f, -0.326760452f, + 0.944604837f, -0.328209844f, + 0.944100258f, -0.329658463f, + 0.943593458f, -0.331106306f, + 0.943084437f, -0.332553370f, + 0.942573198f, -0.333999651f, + 0.942059740f, -0.335445147f, + 0.941544065f, -0.336889853f, + 0.941026175f, -0.338333767f, + 0.940506071f, -0.339776884f, + 0.939983753f, -0.341219202f, + 0.939459224f, -0.342660717f, + 0.938932484f, -0.344101426f, + 0.938403534f, -0.345541325f, + 0.937872376f, -0.346980411f, + 0.937339012f, -0.348418680f, + 0.936803442f, -0.349856130f, + 0.936265667f, -0.351292756f, + 0.935725689f, -0.352728556f, + 0.935183510f, -0.354163525f, + 0.934639130f, -0.355597662f, + 0.934092550f, -0.357030961f, + 0.933543773f, -0.358463421f, + 0.932992799f, -0.359895037f, + 0.932439629f, -0.361325806f, + 0.931884266f, -0.362755724f, + 0.931326709f, -0.364184790f, + 0.930766961f, -0.365612998f, + 0.930205023f, -0.367040346f, + 0.929640896f, -0.368466830f, + 0.929074581f, -0.369892447f, + 0.928506080f, -0.371317194f, + 0.927935395f, -0.372741067f, + 0.927362526f, -0.374164063f, + 0.926787474f, -0.375586178f, + 0.926210242f, -0.377007410f, + 0.925630831f, -0.378427755f, + 0.925049241f, -0.379847209f, + 0.924465474f, -0.381265769f, + 0.923879533f, -0.382683432f, + 0.923291417f, -0.384100195f, + 0.922701128f, -0.385516054f, + 0.922108669f, -0.386931006f, + 0.921514039f, -0.388345047f, + 0.920917242f, -0.389758174f, + 0.920318277f, -0.391170384f, + 0.919717146f, -0.392581674f, + 0.919113852f, -0.393992040f, + 0.918508394f, -0.395401479f, + 0.917900776f, -0.396809987f, + 0.917290997f, -0.398217562f, + 0.916679060f, -0.399624200f, + 0.916064966f, -0.401029897f, + 0.915448716f, -0.402434651f, + 0.914830312f, -0.403838458f, + 0.914209756f, -0.405241314f, + 0.913587048f, -0.406643217f, + 0.912962190f, -0.408044163f, + 0.912335185f, -0.409444149f, + 0.911706032f, -0.410843171f, + 0.911074734f, -0.412241227f, + 0.910441292f, -0.413638312f, + 0.909805708f, -0.415034424f, + 0.909167983f, -0.416429560f, + 0.908528119f, -0.417823716f, + 0.907886116f, -0.419216888f, + 0.907241978f, -0.420609074f, + 0.906595705f, -0.422000271f, + 0.905947298f, -0.423390474f, + 0.905296759f, -0.424779681f, + 0.904644091f, -0.426167889f, + 0.903989293f, -0.427555093f, + 0.903332368f, -0.428941292f, + 0.902673318f, -0.430326481f, + 0.902012144f, -0.431710658f, + 0.901348847f, -0.433093819f, + 0.900683429f, -0.434475961f, + 0.900015892f, -0.435857080f, + 0.899346237f, -0.437237174f, + 0.898674466f, -0.438616239f, + 0.898000580f, -0.439994271f, + 0.897324581f, -0.441371269f, + 0.896646470f, -0.442747228f, + 0.895966250f, -0.444122145f, + 0.895283921f, -0.445496017f, + 0.894599486f, -0.446868840f, + 0.893912945f, -0.448240612f, + 0.893224301f, -0.449611330f, + 0.892533555f, -0.450980989f, + 0.891840709f, -0.452349587f, + 0.891145765f, -0.453717121f, + 0.890448723f, -0.455083587f, + 0.889749586f, -0.456448982f, + 0.889048356f, -0.457813304f, + 0.888345033f, -0.459176548f, + 0.887639620f, -0.460538711f, + 0.886932119f, -0.461899791f, + 0.886222530f, -0.463259784f, + 0.885510856f, -0.464618686f, + 0.884797098f, -0.465976496f, + 0.884081259f, -0.467333209f, + 0.883363339f, -0.468688822f, + 0.882643340f, -0.470043332f, + 0.881921264f, -0.471396737f, + 0.881197113f, -0.472749032f, + 0.880470889f, -0.474100215f, + 0.879742593f, -0.475450282f, + 0.879012226f, -0.476799230f, + 0.878279792f, -0.478147056f, + 0.877545290f, -0.479493758f, + 0.876808724f, -0.480839331f, + 0.876070094f, -0.482183772f, + 0.875329403f, -0.483527079f, + 0.874586652f, -0.484869248f, + 0.873841843f, -0.486210276f, + 0.873094978f, -0.487550160f, + 0.872346059f, -0.488888897f, + 0.871595087f, -0.490226483f, + 0.870842063f, -0.491562916f, + 0.870086991f, -0.492898192f, + 0.869329871f, -0.494232309f, + 0.868570706f, -0.495565262f, + 0.867809497f, -0.496897049f, + 0.867046246f, -0.498227667f, + 0.866280954f, -0.499557113f, + 0.865513624f, -0.500885383f, + 0.864744258f, -0.502212474f, + 0.863972856f, -0.503538384f, + 0.863199422f, -0.504863109f, + 0.862423956f, -0.506186645f, + 0.861646461f, -0.507508991f, + 0.860866939f, -0.508830143f, + 0.860085390f, -0.510150097f, + 0.859301818f, -0.511468850f, + 0.858516224f, -0.512786401f, + 0.857728610f, -0.514102744f, + 0.856938977f, -0.515417878f, + 0.856147328f, -0.516731799f, + 0.855353665f, -0.518044504f, + 0.854557988f, -0.519355990f, + 0.853760301f, -0.520666254f, + 0.852960605f, -0.521975293f, + 0.852158902f, -0.523283103f, + 0.851355193f, -0.524589683f, + 0.850549481f, -0.525895027f, + 0.849741768f, -0.527199135f, + 0.848932055f, -0.528502002f, + 0.848120345f, -0.529803625f, + 0.847306639f, -0.531104001f, + 0.846490939f, -0.532403128f, + 0.845673247f, -0.533701002f, + 0.844853565f, -0.534997620f, + 0.844031895f, -0.536292979f, + 0.843208240f, -0.537587076f, + 0.842382600f, -0.538879909f, + 0.841554977f, -0.540171473f, + 0.840725375f, -0.541461766f, + 0.839893794f, -0.542750785f, + 0.839060237f, -0.544038527f, + 0.838224706f, -0.545324988f, + 0.837387202f, -0.546610167f, + 0.836547727f, -0.547894059f, + 0.835706284f, -0.549176662f, + 0.834862875f, -0.550457973f, + 0.834017501f, -0.551737988f, + 0.833170165f, -0.553016706f, + 0.832320868f, -0.554294121f, + 0.831469612f, -0.555570233f, + 0.830616400f, -0.556845037f, + 0.829761234f, -0.558118531f, + 0.828904115f, -0.559390712f, + 0.828045045f, -0.560661576f, + 0.827184027f, -0.561931121f, + 0.826321063f, -0.563199344f, + 0.825456154f, -0.564466242f, + 0.824589303f, -0.565731811f, + 0.823720511f, -0.566996049f, + 0.822849781f, -0.568258953f, + 0.821977115f, -0.569520519f, + 0.821102515f, -0.570780746f, + 0.820225983f, -0.572039629f, + 0.819347520f, -0.573297167f, + 0.818467130f, -0.574553355f, + 0.817584813f, -0.575808191f, + 0.816700573f, -0.577061673f, + 0.815814411f, -0.578313796f, + 0.814926329f, -0.579564559f, + 0.814036330f, -0.580813958f, + 0.813144415f, -0.582061990f, + 0.812250587f, -0.583308653f, + 0.811354847f, -0.584553943f, + 0.810457198f, -0.585797857f, + 0.809557642f, -0.587040394f, + 0.808656182f, -0.588281548f, + 0.807752818f, -0.589521319f, + 0.806847554f, -0.590759702f, + 0.805940391f, -0.591996695f, + 0.805031331f, -0.593232295f, + 0.804120377f, -0.594466499f, + 0.803207531f, -0.595699304f, + 0.802292796f, -0.596930708f, + 0.801376172f, -0.598160707f, + 0.800457662f, -0.599389298f, + 0.799537269f, -0.600616479f, + 0.798614995f, -0.601842247f, + 0.797690841f, -0.603066599f, + 0.796764810f, -0.604289531f, + 0.795836905f, -0.605511041f, + 0.794907126f, -0.606731127f, + 0.793975478f, -0.607949785f, + 0.793041960f, -0.609167012f, + 0.792106577f, -0.610382806f, + 0.791169330f, -0.611597164f, + 0.790230221f, -0.612810082f, + 0.789289253f, -0.614021559f, + 0.788346428f, -0.615231591f, + 0.787401747f, -0.616440175f, + 0.786455214f, -0.617647308f, + 0.785506830f, -0.618852988f, + 0.784556597f, -0.620057212f, + 0.783604519f, -0.621259977f, + 0.782650596f, -0.622461279f, + 0.781694832f, -0.623661118f, + 0.780737229f, -0.624859488f, + 0.779777788f, -0.626056388f, + 0.778816512f, -0.627251815f, + 0.777853404f, -0.628445767f, + 0.776888466f, -0.629638239f, + 0.775921699f, -0.630829230f, + 0.774953107f, -0.632018736f, + 0.773982691f, -0.633206755f, + 0.773010453f, -0.634393284f, + 0.772036397f, -0.635578320f, + 0.771060524f, -0.636761861f, + 0.770082837f, -0.637943904f, + 0.769103338f, -0.639124445f, + 0.768122029f, -0.640303482f, + 0.767138912f, -0.641481013f, + 0.766153990f, -0.642657034f, + 0.765167266f, -0.643831543f, + 0.764178741f, -0.645004537f, + 0.763188417f, -0.646176013f, + 0.762196298f, -0.647345969f, + 0.761202385f, -0.648514401f, + 0.760206682f, -0.649681307f, + 0.759209189f, -0.650846685f, + 0.758209910f, -0.652010531f, + 0.757208847f, -0.653172843f, + 0.756206001f, -0.654333618f, + 0.755201377f, -0.655492853f, + 0.754194975f, -0.656650546f, + 0.753186799f, -0.657806693f, + 0.752176850f, -0.658961293f, + 0.751165132f, -0.660114342f, + 0.750151646f, -0.661265838f, + 0.749136395f, -0.662415778f, + 0.748119380f, -0.663564159f, + 0.747100606f, -0.664710978f, + 0.746080074f, -0.665856234f, + 0.745057785f, -0.666999922f, + 0.744033744f, -0.668142041f, + 0.743007952f, -0.669282588f, + 0.741980412f, -0.670421560f, + 0.740951125f, -0.671558955f, + 0.739920095f, -0.672694769f, + 0.738887324f, -0.673829000f, + 0.737852815f, -0.674961646f, + 0.736816569f, -0.676092704f, + 0.735778589f, -0.677222170f, + 0.734738878f, -0.678350043f, + 0.733697438f, -0.679476320f, + 0.732654272f, -0.680600998f, + 0.731609381f, -0.681724074f, + 0.730562769f, -0.682845546f, + 0.729514438f, -0.683965412f, + 0.728464390f, -0.685083668f, + 0.727412629f, -0.686200312f, + 0.726359155f, -0.687315341f, + 0.725303972f, -0.688428753f, + 0.724247083f, -0.689540545f, + 0.723188489f, -0.690650714f, + 0.722128194f, -0.691759258f, + 0.721066199f, -0.692866175f, + 0.720002508f, -0.693971461f, + 0.718937122f, -0.695075114f, + 0.717870045f, -0.696177131f, + 0.716801279f, -0.697277511f, + 0.715730825f, -0.698376249f, + 0.714658688f, -0.699473345f, + 0.713584869f, -0.700568794f, + 0.712509371f, -0.701662595f, + 0.711432196f, -0.702754744f, + 0.710353347f, -0.703845241f, + 0.709272826f, -0.704934080f, + 0.708190637f, -0.706021261f, + 0.707106781f, -0.707106781f, + 0.706021261f, -0.708190637f, + 0.704934080f, -0.709272826f, + 0.703845241f, -0.710353347f, + 0.702754744f, -0.711432196f, + 0.701662595f, -0.712509371f, + 0.700568794f, -0.713584869f, + 0.699473345f, -0.714658688f, + 0.698376249f, -0.715730825f, + 0.697277511f, -0.716801279f, + 0.696177131f, -0.717870045f, + 0.695075114f, -0.718937122f, + 0.693971461f, -0.720002508f, + 0.692866175f, -0.721066199f, + 0.691759258f, -0.722128194f, + 0.690650714f, -0.723188489f, + 0.689540545f, -0.724247083f, + 0.688428753f, -0.725303972f, + 0.687315341f, -0.726359155f, + 0.686200312f, -0.727412629f, + 0.685083668f, -0.728464390f, + 0.683965412f, -0.729514438f, + 0.682845546f, -0.730562769f, + 0.681724074f, -0.731609381f, + 0.680600998f, -0.732654272f, + 0.679476320f, -0.733697438f, + 0.678350043f, -0.734738878f, + 0.677222170f, -0.735778589f, + 0.676092704f, -0.736816569f, + 0.674961646f, -0.737852815f, + 0.673829000f, -0.738887324f, + 0.672694769f, -0.739920095f, + 0.671558955f, -0.740951125f, + 0.670421560f, -0.741980412f, + 0.669282588f, -0.743007952f, + 0.668142041f, -0.744033744f, + 0.666999922f, -0.745057785f, + 0.665856234f, -0.746080074f, + 0.664710978f, -0.747100606f, + 0.663564159f, -0.748119380f, + 0.662415778f, -0.749136395f, + 0.661265838f, -0.750151646f, + 0.660114342f, -0.751165132f, + 0.658961293f, -0.752176850f, + 0.657806693f, -0.753186799f, + 0.656650546f, -0.754194975f, + 0.655492853f, -0.755201377f, + 0.654333618f, -0.756206001f, + 0.653172843f, -0.757208847f, + 0.652010531f, -0.758209910f, + 0.650846685f, -0.759209189f, + 0.649681307f, -0.760206682f, + 0.648514401f, -0.761202385f, + 0.647345969f, -0.762196298f, + 0.646176013f, -0.763188417f, + 0.645004537f, -0.764178741f, + 0.643831543f, -0.765167266f, + 0.642657034f, -0.766153990f, + 0.641481013f, -0.767138912f, + 0.640303482f, -0.768122029f, + 0.639124445f, -0.769103338f, + 0.637943904f, -0.770082837f, + 0.636761861f, -0.771060524f, + 0.635578320f, -0.772036397f, + 0.634393284f, -0.773010453f, + 0.633206755f, -0.773982691f, + 0.632018736f, -0.774953107f, + 0.630829230f, -0.775921699f, + 0.629638239f, -0.776888466f, + 0.628445767f, -0.777853404f, + 0.627251815f, -0.778816512f, + 0.626056388f, -0.779777788f, + 0.624859488f, -0.780737229f, + 0.623661118f, -0.781694832f, + 0.622461279f, -0.782650596f, + 0.621259977f, -0.783604519f, + 0.620057212f, -0.784556597f, + 0.618852988f, -0.785506830f, + 0.617647308f, -0.786455214f, + 0.616440175f, -0.787401747f, + 0.615231591f, -0.788346428f, + 0.614021559f, -0.789289253f, + 0.612810082f, -0.790230221f, + 0.611597164f, -0.791169330f, + 0.610382806f, -0.792106577f, + 0.609167012f, -0.793041960f, + 0.607949785f, -0.793975478f, + 0.606731127f, -0.794907126f, + 0.605511041f, -0.795836905f, + 0.604289531f, -0.796764810f, + 0.603066599f, -0.797690841f, + 0.601842247f, -0.798614995f, + 0.600616479f, -0.799537269f, + 0.599389298f, -0.800457662f, + 0.598160707f, -0.801376172f, + 0.596930708f, -0.802292796f, + 0.595699304f, -0.803207531f, + 0.594466499f, -0.804120377f, + 0.593232295f, -0.805031331f, + 0.591996695f, -0.805940391f, + 0.590759702f, -0.806847554f, + 0.589521319f, -0.807752818f, + 0.588281548f, -0.808656182f, + 0.587040394f, -0.809557642f, + 0.585797857f, -0.810457198f, + 0.584553943f, -0.811354847f, + 0.583308653f, -0.812250587f, + 0.582061990f, -0.813144415f, + 0.580813958f, -0.814036330f, + 0.579564559f, -0.814926329f, + 0.578313796f, -0.815814411f, + 0.577061673f, -0.816700573f, + 0.575808191f, -0.817584813f, + 0.574553355f, -0.818467130f, + 0.573297167f, -0.819347520f, + 0.572039629f, -0.820225983f, + 0.570780746f, -0.821102515f, + 0.569520519f, -0.821977115f, + 0.568258953f, -0.822849781f, + 0.566996049f, -0.823720511f, + 0.565731811f, -0.824589303f, + 0.564466242f, -0.825456154f, + 0.563199344f, -0.826321063f, + 0.561931121f, -0.827184027f, + 0.560661576f, -0.828045045f, + 0.559390712f, -0.828904115f, + 0.558118531f, -0.829761234f, + 0.556845037f, -0.830616400f, + 0.555570233f, -0.831469612f, + 0.554294121f, -0.832320868f, + 0.553016706f, -0.833170165f, + 0.551737988f, -0.834017501f, + 0.550457973f, -0.834862875f, + 0.549176662f, -0.835706284f, + 0.547894059f, -0.836547727f, + 0.546610167f, -0.837387202f, + 0.545324988f, -0.838224706f, + 0.544038527f, -0.839060237f, + 0.542750785f, -0.839893794f, + 0.541461766f, -0.840725375f, + 0.540171473f, -0.841554977f, + 0.538879909f, -0.842382600f, + 0.537587076f, -0.843208240f, + 0.536292979f, -0.844031895f, + 0.534997620f, -0.844853565f, + 0.533701002f, -0.845673247f, + 0.532403128f, -0.846490939f, + 0.531104001f, -0.847306639f, + 0.529803625f, -0.848120345f, + 0.528502002f, -0.848932055f, + 0.527199135f, -0.849741768f, + 0.525895027f, -0.850549481f, + 0.524589683f, -0.851355193f, + 0.523283103f, -0.852158902f, + 0.521975293f, -0.852960605f, + 0.520666254f, -0.853760301f, + 0.519355990f, -0.854557988f, + 0.518044504f, -0.855353665f, + 0.516731799f, -0.856147328f, + 0.515417878f, -0.856938977f, + 0.514102744f, -0.857728610f, + 0.512786401f, -0.858516224f, + 0.511468850f, -0.859301818f, + 0.510150097f, -0.860085390f, + 0.508830143f, -0.860866939f, + 0.507508991f, -0.861646461f, + 0.506186645f, -0.862423956f, + 0.504863109f, -0.863199422f, + 0.503538384f, -0.863972856f, + 0.502212474f, -0.864744258f, + 0.500885383f, -0.865513624f, + 0.499557113f, -0.866280954f, + 0.498227667f, -0.867046246f, + 0.496897049f, -0.867809497f, + 0.495565262f, -0.868570706f, + 0.494232309f, -0.869329871f, + 0.492898192f, -0.870086991f, + 0.491562916f, -0.870842063f, + 0.490226483f, -0.871595087f, + 0.488888897f, -0.872346059f, + 0.487550160f, -0.873094978f, + 0.486210276f, -0.873841843f, + 0.484869248f, -0.874586652f, + 0.483527079f, -0.875329403f, + 0.482183772f, -0.876070094f, + 0.480839331f, -0.876808724f, + 0.479493758f, -0.877545290f, + 0.478147056f, -0.878279792f, + 0.476799230f, -0.879012226f, + 0.475450282f, -0.879742593f, + 0.474100215f, -0.880470889f, + 0.472749032f, -0.881197113f, + 0.471396737f, -0.881921264f, + 0.470043332f, -0.882643340f, + 0.468688822f, -0.883363339f, + 0.467333209f, -0.884081259f, + 0.465976496f, -0.884797098f, + 0.464618686f, -0.885510856f, + 0.463259784f, -0.886222530f, + 0.461899791f, -0.886932119f, + 0.460538711f, -0.887639620f, + 0.459176548f, -0.888345033f, + 0.457813304f, -0.889048356f, + 0.456448982f, -0.889749586f, + 0.455083587f, -0.890448723f, + 0.453717121f, -0.891145765f, + 0.452349587f, -0.891840709f, + 0.450980989f, -0.892533555f, + 0.449611330f, -0.893224301f, + 0.448240612f, -0.893912945f, + 0.446868840f, -0.894599486f, + 0.445496017f, -0.895283921f, + 0.444122145f, -0.895966250f, + 0.442747228f, -0.896646470f, + 0.441371269f, -0.897324581f, + 0.439994271f, -0.898000580f, + 0.438616239f, -0.898674466f, + 0.437237174f, -0.899346237f, + 0.435857080f, -0.900015892f, + 0.434475961f, -0.900683429f, + 0.433093819f, -0.901348847f, + 0.431710658f, -0.902012144f, + 0.430326481f, -0.902673318f, + 0.428941292f, -0.903332368f, + 0.427555093f, -0.903989293f, + 0.426167889f, -0.904644091f, + 0.424779681f, -0.905296759f, + 0.423390474f, -0.905947298f, + 0.422000271f, -0.906595705f, + 0.420609074f, -0.907241978f, + 0.419216888f, -0.907886116f, + 0.417823716f, -0.908528119f, + 0.416429560f, -0.909167983f, + 0.415034424f, -0.909805708f, + 0.413638312f, -0.910441292f, + 0.412241227f, -0.911074734f, + 0.410843171f, -0.911706032f, + 0.409444149f, -0.912335185f, + 0.408044163f, -0.912962190f, + 0.406643217f, -0.913587048f, + 0.405241314f, -0.914209756f, + 0.403838458f, -0.914830312f, + 0.402434651f, -0.915448716f, + 0.401029897f, -0.916064966f, + 0.399624200f, -0.916679060f, + 0.398217562f, -0.917290997f, + 0.396809987f, -0.917900776f, + 0.395401479f, -0.918508394f, + 0.393992040f, -0.919113852f, + 0.392581674f, -0.919717146f, + 0.391170384f, -0.920318277f, + 0.389758174f, -0.920917242f, + 0.388345047f, -0.921514039f, + 0.386931006f, -0.922108669f, + 0.385516054f, -0.922701128f, + 0.384100195f, -0.923291417f, + 0.382683432f, -0.923879533f, + 0.381265769f, -0.924465474f, + 0.379847209f, -0.925049241f, + 0.378427755f, -0.925630831f, + 0.377007410f, -0.926210242f, + 0.375586178f, -0.926787474f, + 0.374164063f, -0.927362526f, + 0.372741067f, -0.927935395f, + 0.371317194f, -0.928506080f, + 0.369892447f, -0.929074581f, + 0.368466830f, -0.929640896f, + 0.367040346f, -0.930205023f, + 0.365612998f, -0.930766961f, + 0.364184790f, -0.931326709f, + 0.362755724f, -0.931884266f, + 0.361325806f, -0.932439629f, + 0.359895037f, -0.932992799f, + 0.358463421f, -0.933543773f, + 0.357030961f, -0.934092550f, + 0.355597662f, -0.934639130f, + 0.354163525f, -0.935183510f, + 0.352728556f, -0.935725689f, + 0.351292756f, -0.936265667f, + 0.349856130f, -0.936803442f, + 0.348418680f, -0.937339012f, + 0.346980411f, -0.937872376f, + 0.345541325f, -0.938403534f, + 0.344101426f, -0.938932484f, + 0.342660717f, -0.939459224f, + 0.341219202f, -0.939983753f, + 0.339776884f, -0.940506071f, + 0.338333767f, -0.941026175f, + 0.336889853f, -0.941544065f, + 0.335445147f, -0.942059740f, + 0.333999651f, -0.942573198f, + 0.332553370f, -0.943084437f, + 0.331106306f, -0.943593458f, + 0.329658463f, -0.944100258f, + 0.328209844f, -0.944604837f, + 0.326760452f, -0.945107193f, + 0.325310292f, -0.945607325f, + 0.323859367f, -0.946105232f, + 0.322407679f, -0.946600913f, + 0.320955232f, -0.947094366f, + 0.319502031f, -0.947585591f, + 0.318048077f, -0.948074586f, + 0.316593376f, -0.948561350f, + 0.315137929f, -0.949045882f, + 0.313681740f, -0.949528181f, + 0.312224814f, -0.950008245f, + 0.310767153f, -0.950486074f, + 0.309308760f, -0.950961666f, + 0.307849640f, -0.951435021f, + 0.306389795f, -0.951906137f, + 0.304929230f, -0.952375013f, + 0.303467947f, -0.952841648f, + 0.302005949f, -0.953306040f, + 0.300543241f, -0.953768190f, + 0.299079826f, -0.954228095f, + 0.297615707f, -0.954685755f, + 0.296150888f, -0.955141168f, + 0.294685372f, -0.955594334f, + 0.293219163f, -0.956045251f, + 0.291752263f, -0.956493919f, + 0.290284677f, -0.956940336f, + 0.288816408f, -0.957384501f, + 0.287347460f, -0.957826413f, + 0.285877835f, -0.958266071f, + 0.284407537f, -0.958703475f, + 0.282936570f, -0.959138622f, + 0.281464938f, -0.959571513f, + 0.279992643f, -0.960002146f, + 0.278519689f, -0.960430519f, + 0.277046080f, -0.960856633f, + 0.275571819f, -0.961280486f, + 0.274096910f, -0.961702077f, + 0.272621355f, -0.962121404f, + 0.271145160f, -0.962538468f, + 0.269668326f, -0.962953267f, + 0.268190857f, -0.963365800f, + 0.266712757f, -0.963776066f, + 0.265234030f, -0.964184064f, + 0.263754679f, -0.964589793f, + 0.262274707f, -0.964993253f, + 0.260794118f, -0.965394442f, + 0.259312915f, -0.965793359f, + 0.257831102f, -0.966190003f, + 0.256348682f, -0.966584374f, + 0.254865660f, -0.966976471f, + 0.253382037f, -0.967366292f, + 0.251897818f, -0.967753837f, + 0.250413007f, -0.968139105f, + 0.248927606f, -0.968522094f, + 0.247441619f, -0.968902805f, + 0.245955050f, -0.969281235f, + 0.244467903f, -0.969657385f, + 0.242980180f, -0.970031253f, + 0.241491885f, -0.970402839f, + 0.240003022f, -0.970772141f, + 0.238513595f, -0.971139158f, + 0.237023606f, -0.971503891f, + 0.235533059f, -0.971866337f, + 0.234041959f, -0.972226497f, + 0.232550307f, -0.972584369f, + 0.231058108f, -0.972939952f, + 0.229565366f, -0.973293246f, + 0.228072083f, -0.973644250f, + 0.226578264f, -0.973992962f, + 0.225083911f, -0.974339383f, + 0.223589029f, -0.974683511f, + 0.222093621f, -0.975025345f, + 0.220597690f, -0.975364885f, + 0.219101240f, -0.975702130f, + 0.217604275f, -0.976037079f, + 0.216106797f, -0.976369731f, + 0.214608811f, -0.976700086f, + 0.213110320f, -0.977028143f, + 0.211611327f, -0.977353900f, + 0.210111837f, -0.977677358f, + 0.208611852f, -0.977998515f, + 0.207111376f, -0.978317371f, + 0.205610413f, -0.978633924f, + 0.204108966f, -0.978948175f, + 0.202607039f, -0.979260123f, + 0.201104635f, -0.979569766f, + 0.199601758f, -0.979877104f, + 0.198098411f, -0.980182136f, + 0.196594598f, -0.980484862f, + 0.195090322f, -0.980785280f, + 0.193585587f, -0.981083391f, + 0.192080397f, -0.981379193f, + 0.190574755f, -0.981672686f, + 0.189068664f, -0.981963869f, + 0.187562129f, -0.982252741f, + 0.186055152f, -0.982539302f, + 0.184547737f, -0.982823551f, + 0.183039888f, -0.983105487f, + 0.181531608f, -0.983385110f, + 0.180022901f, -0.983662419f, + 0.178513771f, -0.983937413f, + 0.177004220f, -0.984210092f, + 0.175494253f, -0.984480455f, + 0.173983873f, -0.984748502f, + 0.172473084f, -0.985014231f, + 0.170961889f, -0.985277642f, + 0.169450291f, -0.985538735f, + 0.167938295f, -0.985797509f, + 0.166425904f, -0.986053963f, + 0.164913120f, -0.986308097f, + 0.163399949f, -0.986559910f, + 0.161886394f, -0.986809402f, + 0.160372457f, -0.987056571f, + 0.158858143f, -0.987301418f, + 0.157343456f, -0.987543942f, + 0.155828398f, -0.987784142f, + 0.154312973f, -0.988022017f, + 0.152797185f, -0.988257568f, + 0.151281038f, -0.988490793f, + 0.149764535f, -0.988721692f, + 0.148247679f, -0.988950265f, + 0.146730474f, -0.989176510f, + 0.145212925f, -0.989400428f, + 0.143695033f, -0.989622017f, + 0.142176804f, -0.989841278f, + 0.140658239f, -0.990058210f, + 0.139139344f, -0.990272812f, + 0.137620122f, -0.990485084f, + 0.136100575f, -0.990695025f, + 0.134580709f, -0.990902635f, + 0.133060525f, -0.991107914f, + 0.131540029f, -0.991310860f, + 0.130019223f, -0.991511473f, + 0.128498111f, -0.991709754f, + 0.126976696f, -0.991905700f, + 0.125454983f, -0.992099313f, + 0.123932975f, -0.992290591f, + 0.122410675f, -0.992479535f, + 0.120888087f, -0.992666142f, + 0.119365215f, -0.992850414f, + 0.117842062f, -0.993032350f, + 0.116318631f, -0.993211949f, + 0.114794927f, -0.993389211f, + 0.113270952f, -0.993564136f, + 0.111746711f, -0.993736722f, + 0.110222207f, -0.993906970f, + 0.108697444f, -0.994074879f, + 0.107172425f, -0.994240449f, + 0.105647154f, -0.994403680f, + 0.104121634f, -0.994564571f, + 0.102595869f, -0.994723121f, + 0.101069863f, -0.994879331f, + 0.099543619f, -0.995033199f, + 0.098017140f, -0.995184727f, + 0.096490431f, -0.995333912f, + 0.094963495f, -0.995480755f, + 0.093436336f, -0.995625256f, + 0.091908956f, -0.995767414f, + 0.090381361f, -0.995907229f, + 0.088853553f, -0.996044701f, + 0.087325535f, -0.996179829f, + 0.085797312f, -0.996312612f, + 0.084268888f, -0.996443051f, + 0.082740265f, -0.996571146f, + 0.081211447f, -0.996696895f, + 0.079682438f, -0.996820299f, + 0.078153242f, -0.996941358f, + 0.076623861f, -0.997060070f, + 0.075094301f, -0.997176437f, + 0.073564564f, -0.997290457f, + 0.072034653f, -0.997402130f, + 0.070504573f, -0.997511456f, + 0.068974328f, -0.997618435f, + 0.067443920f, -0.997723067f, + 0.065913353f, -0.997825350f, + 0.064382631f, -0.997925286f, + 0.062851758f, -0.998022874f, + 0.061320736f, -0.998118113f, + 0.059789571f, -0.998211003f, + 0.058258265f, -0.998301545f, + 0.056726821f, -0.998389737f, + 0.055195244f, -0.998475581f, + 0.053663538f, -0.998559074f, + 0.052131705f, -0.998640218f, + 0.050599749f, -0.998719012f, + 0.049067674f, -0.998795456f, + 0.047535484f, -0.998869550f, + 0.046003182f, -0.998941293f, + 0.044470772f, -0.999010686f, + 0.042938257f, -0.999077728f, + 0.041405641f, -0.999142419f, + 0.039872928f, -0.999204759f, + 0.038340120f, -0.999264747f, + 0.036807223f, -0.999322385f, + 0.035274239f, -0.999377670f, + 0.033741172f, -0.999430605f, + 0.032208025f, -0.999481187f, + 0.030674803f, -0.999529418f, + 0.029141509f, -0.999575296f, + 0.027608146f, -0.999618822f, + 0.026074718f, -0.999659997f, + 0.024541229f, -0.999698819f, + 0.023007681f, -0.999735288f, + 0.021474080f, -0.999769405f, + 0.019940429f, -0.999801170f, + 0.018406730f, -0.999830582f, + 0.016872988f, -0.999857641f, + 0.015339206f, -0.999882347f, + 0.013805389f, -0.999904701f, + 0.012271538f, -0.999924702f, + 0.010737659f, -0.999942350f, + 0.009203755f, -0.999957645f, + 0.007669829f, -0.999970586f, + 0.006135885f, -0.999981175f, + 0.004601926f, -0.999989411f, + 0.003067957f, -0.999995294f, + 0.001533980f, -0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +/** + @ingroup RealFFT + */ + +/** + @addtogroup RealFFT_Table Real FFT Tables + @{ + */ + +/** + @par + Generation of realCoefA array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) +const float32_t realCoefA[8192] = { + 0.500000000000000f, -0.500000000000000f, 0.499616503715515f, -0.499999850988388f, + 0.499233007431030f, -0.499999403953552f, 0.498849511146545f, -0.499998688697815f, + 0.498466014862061f, -0.499997645616531f, 0.498082518577576f, -0.499996334314346f, + 0.497699022293091f, -0.499994695186615f, 0.497315555810928f, -0.499992787837982f, + 0.496932059526443f, -0.499990582466125f, 0.496548563241959f, -0.499988079071045f, + 0.496165096759796f, -0.499985307455063f, 0.495781600475311f, -0.499982208013535f, + 0.495398133993149f, -0.499978810548782f, 0.495014637708664f, -0.499975144863129f, + 0.494631171226501f, -0.499971181154251f, 0.494247704744339f, -0.499966919422150f, + 0.493864238262177f, -0.499962359666824f, 0.493480771780014f, -0.499957501888275f, + 0.493097305297852f, -0.499952346086502f, 0.492713838815689f, -0.499946922063828f, + 0.492330402135849f, -0.499941170215607f, 0.491946935653687f, -0.499935150146484f, + 0.491563498973846f, -0.499928832054138f, 0.491180062294006f, -0.499922215938568f, + 0.490796625614166f, -0.499915301799774f, 0.490413218736649f, -0.499908089637756f, + 0.490029782056808f, -0.499900579452515f, 0.489646375179291f, -0.499892801046371f, + 0.489262968301773f, -0.499884694814682f, 0.488879561424255f, -0.499876320362091f, + 0.488496154546738f, -0.499867647886276f, 0.488112777471542f, -0.499858677387238f, + 0.487729400396347f, -0.499849408864975f, 0.487346023321152f, -0.499839842319489f, + 0.486962646245956f, -0.499830007553101f, 0.486579269170761f, -0.499819844961166f, + 0.486195921897888f, -0.499809414148331f, 0.485812574625015f, -0.499798685312271f, + 0.485429257154465f, -0.499787658452988f, 0.485045909881592f, -0.499776333570480f, + 0.484662592411041f, -0.499764710664749f, 0.484279274940491f, -0.499752789735794f, + 0.483895987272263f, -0.499740600585938f, 0.483512699604034f, -0.499728083610535f, + 0.483129411935806f, -0.499715298414230f, 0.482746154069901f, -0.499702215194702f, + 0.482362866401672f, -0.499688833951950f, 0.481979638338089f, -0.499675154685974f, + 0.481596380472183f, -0.499661177396774f, 0.481213152408600f, -0.499646931886673f, + 0.480829954147339f, -0.499632388353348f, 0.480446726083755f, -0.499617516994476f, + 0.480063527822495f, -0.499602377414703f, 0.479680359363556f, -0.499586939811707f, + 0.479297190904617f, -0.499571204185486f, 0.478914022445679f, -0.499555170536041f, + 0.478530883789063f, -0.499538868665695f, 0.478147745132446f, -0.499522238969803f, + 0.477764606475830f, -0.499505341053009f, 0.477381497621536f, -0.499488145112991f, + 0.476998418569565f, -0.499470651149750f, 0.476615339517593f, -0.499452859163284f, + 0.476232260465622f, -0.499434769153595f, 0.475849211215973f, -0.499416410923004f, + 0.475466161966324f, -0.499397724866867f, 0.475083142518997f, -0.499378770589828f, + 0.474700123071671f, -0.499359518289566f, 0.474317133426666f, -0.499339967966080f, + 0.473934143781662f, -0.499320119619370f, 0.473551183938980f, -0.499299973249435f, + 0.473168224096298f, -0.499279528856277f, 0.472785294055939f, -0.499258816242218f, + 0.472402364015579f, -0.499237775802612f, 0.472019463777542f, -0.499216467142105f, + 0.471636593341827f, -0.499194860458374f, 0.471253722906113f, -0.499172955751419f, + 0.470870882272720f, -0.499150782823563f, 0.470488041639328f, -0.499128282070160f, + 0.470105201005936f, -0.499105513095856f, 0.469722419977188f, -0.499082416296005f, + 0.469339638948441f, -0.499059051275253f, 0.468956857919693f, -0.499035388231277f, + 0.468574106693268f, -0.499011427164078f, 0.468191385269165f, -0.498987197875977f, + 0.467808693647385f, -0.498962640762329f, 0.467426002025604f, -0.498937815427780f, + 0.467043310403824f, -0.498912662267685f, 0.466660678386688f, -0.498887240886688f, + 0.466278046369553f, -0.498861521482468f, 0.465895414352417f, -0.498835533857346f, + 0.465512841939926f, -0.498809218406677f, 0.465130269527435f, -0.498782604932785f, + 0.464747726917267f, -0.498755723237991f, 0.464365184307098f, -0.498728543519974f, + 0.463982671499252f, -0.498701065778732f, 0.463600188493729f, -0.498673290014267f, + 0.463217705488205f, -0.498645216226578f, 0.462835282087326f, -0.498616874217987f, + 0.462452858686447f, -0.498588204383850f, 0.462070435285568f, -0.498559266328812f, + 0.461688071489334f, -0.498530030250549f, 0.461305707693100f, -0.498500496149063f, + 0.460923373699188f, -0.498470664024353f, 0.460541069507599f, -0.498440563678741f, + 0.460158795118332f, -0.498410135507584f, 0.459776520729065f, -0.498379439115524f, + 0.459394276142120f, -0.498348444700241f, 0.459012061357498f, -0.498317152261734f, + 0.458629876375198f, -0.498285561800003f, 0.458247691392899f, -0.498253703117371f, + 0.457865566015244f, -0.498221516609192f, 0.457483440637589f, -0.498189061880112f, + 0.457101345062256f, -0.498156309127808f, 0.456719279289246f, -0.498123258352280f, + 0.456337243318558f, -0.498089909553528f, 0.455955207347870f, -0.498056292533875f, + 0.455573230981827f, -0.498022347688675f, 0.455191254615784f, -0.497988134622574f, + 0.454809308052063f, -0.497953623533249f, 0.454427421092987f, -0.497918814420700f, + 0.454045534133911f, -0.497883707284927f, 0.453663676977158f, -0.497848302125931f, + 0.453281819820404f, -0.497812628746033f, 0.452900022268295f, -0.497776657342911f, + 0.452518254518509f, -0.497740387916565f, 0.452136516571045f, -0.497703820466995f, + 0.451754778623581f, -0.497666954994202f, 0.451373100280762f, -0.497629791498184f, + 0.450991421937943f, -0.497592359781265f, 0.450609803199768f, -0.497554630041122f, + 0.450228184461594f, -0.497516602277756f, 0.449846625328064f, -0.497478276491165f, + 0.449465066194534f, -0.497439652681351f, 0.449083566665649f, -0.497400760650635f, + 0.448702067136765f, -0.497361570596695f, 0.448320597410202f, -0.497322082519531f, + 0.447939187288284f, -0.497282296419144f, 0.447557777166367f, -0.497242212295532f, + 0.447176426649094f, -0.497201830148697f, 0.446795076131821f, -0.497161179780960f, + 0.446413785219193f, -0.497120231389999f, 0.446032524108887f, -0.497078984975815f, + 0.445651292800903f, -0.497037440538406f, 0.445270061492920f, -0.496995598077774f, + 0.444888889789581f, -0.496953487396240f, 0.444507747888565f, -0.496911078691483f, + 0.444126635789871f, -0.496868371963501f, 0.443745553493500f, -0.496825367212296f, + 0.443364530801773f, -0.496782064437866f, 0.442983508110046f, -0.496738493442535f, + 0.442602545022964f, -0.496694594621658f, 0.442221581935883f, -0.496650427579880f, + 0.441840678453445f, -0.496605962514877f, 0.441459804773331f, -0.496561229228973f, + 0.441078960895538f, -0.496516168117523f, 0.440698176622391f, -0.496470838785172f, + 0.440317392349243f, -0.496425211429596f, 0.439936667680740f, -0.496379286050797f, + 0.439555943012238f, -0.496333062648773f, 0.439175277948380f, -0.496286571025848f, + 0.438794672489166f, -0.496239781379700f, 0.438414067029953f, -0.496192663908005f, + 0.438033521175385f, -0.496145308017731f, 0.437653005123138f, -0.496097624301910f, + 0.437272518873215f, -0.496049642562866f, 0.436892062425613f, -0.496001392602921f, + 0.436511665582657f, -0.495952844619751f, 0.436131268739700f, -0.495903998613358f, + 0.435750931501389f, -0.495854884386063f, 0.435370653867722f, -0.495805442333221f, + 0.434990376234055f, -0.495755732059479f, 0.434610158205032f, -0.495705723762512f, + 0.434229999780655f, -0.495655417442322f, 0.433849841356277f, -0.495604842901230f, + 0.433469742536545f, -0.495553970336914f, 0.433089673519135f, -0.495502769947052f, + 0.432709634304047f, -0.495451331138611f, 0.432329654693604f, -0.495399564504623f, + 0.431949704885483f, -0.495347499847412f, 0.431569814682007f, -0.495295166969299f, + 0.431189924478531f, -0.495242536067963f, 0.430810123682022f, -0.495189607143402f, + 0.430430322885513f, -0.495136409997940f, 0.430050581693649f, -0.495082914829254f, + 0.429670870304108f, -0.495029091835022f, 0.429291218519211f, -0.494975030422211f, + 0.428911596536636f, -0.494920641183853f, 0.428532034158707f, -0.494865983724594f, + 0.428152471780777f, -0.494810998439789f, 0.427772998809814f, -0.494755744934082f, + 0.427393525838852f, -0.494700223207474f, 0.427014142274857f, -0.494644373655319f, + 0.426634758710861f, -0.494588255882263f, 0.426255434751511f, -0.494531840085983f, + 0.425876170396805f, -0.494475126266479f, 0.425496935844421f, -0.494418144226074f, + 0.425117731094360f, -0.494360834360123f, 0.424738585948944f, -0.494303256273270f, + 0.424359470605850f, -0.494245409965515f, 0.423980414867401f, -0.494187235832214f, + 0.423601418733597f, -0.494128793478012f, 0.423222452402115f, -0.494070053100586f, + 0.422843515872955f, -0.494011014699936f, 0.422464638948441f, -0.493951678276062f, + 0.422085791826248f, -0.493892073631287f, 0.421707004308701f, -0.493832170963287f, + 0.421328276395798f, -0.493771970272064f, 0.420949578285217f, -0.493711471557617f, + 0.420570939779282f, -0.493650704622269f, 0.420192331075668f, -0.493589639663696f, + 0.419813781976700f, -0.493528276681900f, 0.419435262680054f, -0.493466645479202f, + 0.419056802988052f, -0.493404686450958f, 0.418678402900696f, -0.493342459201813f, + 0.418300032615662f, -0.493279963731766f, 0.417921721935272f, -0.493217140436172f, + 0.417543441057205f, -0.493154048919678f, 0.417165219783783f, -0.493090659379959f, + 0.416787058115005f, -0.493026971817017f, 0.416408926248550f, -0.492963016033173f, + 0.416030853986740f, -0.492898762226105f, 0.415652841329575f, -0.492834210395813f, + 0.415274858474731f, -0.492769360542297f, 0.414896935224533f, -0.492704242467880f, + 0.414519041776657f, -0.492638826370239f, 0.414141237735748f, -0.492573112249374f, + 0.413763463497162f, -0.492507129907608f, 0.413385748863220f, -0.492440819740295f, + 0.413008064031601f, -0.492374241352081f, 0.412630438804626f, -0.492307394742966f, + 0.412252873182297f, -0.492240220308304f, 0.411875367164612f, -0.492172777652740f, + 0.411497890949249f, -0.492105036973953f, 0.411120474338531f, -0.492037028074265f, + 0.410743117332459f, -0.491968721151352f, 0.410365819931030f, -0.491900116205215f, + 0.409988552331924f, -0.491831213235855f, 0.409611344337463f, -0.491762012243271f, + 0.409234195947647f, -0.491692543029785f, 0.408857107162476f, -0.491622805595398f, + 0.408480048179626f, -0.491552740335464f, 0.408103078603745f, -0.491482406854630f, + 0.407726138830185f, -0.491411775350571f, 0.407349258661270f, -0.491340845823288f, + 0.406972438097000f, -0.491269648075104f, 0.406595647335052f, -0.491198152303696f, + 0.406218945980072f, -0.491126358509064f, 0.405842274427414f, -0.491054296493530f, + 0.405465662479401f, -0.490981936454773f, 0.405089110136032f, -0.490909278392792f, + 0.404712617397308f, -0.490836352109909f, 0.404336184263229f, -0.490763127803802f, + 0.403959810733795f, -0.490689605474472f, 0.403583467006683f, -0.490615785121918f, + 0.403207212686539f, -0.490541696548462f, 0.402830988168716f, -0.490467309951782f, + 0.402454853057861f, -0.490392625331879f, 0.402078747749329f, -0.490317672491074f, + 0.401702702045441f, -0.490242421627045f, 0.401326715946198f, -0.490166902542114f, + 0.400950789451599f, -0.490091055631638f, 0.400574922561646f, -0.490014940500259f, + 0.400199115276337f, -0.489938557147980f, 0.399823367595673f, -0.489861875772476f, + 0.399447679519653f, -0.489784896373749f, 0.399072051048279f, -0.489707618951797f, + 0.398696482181549f, -0.489630073308945f, 0.398320972919464f, -0.489552229642868f, + 0.397945523262024f, -0.489474087953568f, 0.397570133209229f, -0.489395678043365f, + 0.397194802761078f, -0.489316970109940f, 0.396819531917572f, -0.489237964153290f, + 0.396444320678711f, -0.489158689975739f, 0.396069169044495f, -0.489079117774963f, + 0.395694077014923f, -0.488999247550964f, 0.395319044589996f, -0.488919109106064f, + 0.394944071769714f, -0.488838672637939f, 0.394569188356400f, -0.488757967948914f, + 0.394194334745407f, -0.488676935434341f, 0.393819570541382f, -0.488595664501190f, + 0.393444836139679f, -0.488514065742493f, 0.393070191144943f, -0.488432198762894f, + 0.392695605754852f, -0.488350033760071f, 0.392321079969406f, -0.488267600536346f, + 0.391946613788605f, -0.488184869289398f, 0.391572207212448f, -0.488101840019226f, + 0.391197860240936f, -0.488018542528152f, 0.390823602676392f, -0.487934947013855f, + 0.390449374914169f, -0.487851053476334f, 0.390075236558914f, -0.487766891717911f, + 0.389701157808304f, -0.487682431936264f, 0.389327138662338f, -0.487597703933716f, + 0.388953179121017f, -0.487512677907944f, 0.388579308986664f, -0.487427353858948f, + 0.388205498456955f, -0.487341761589050f, 0.387831717729568f, -0.487255871295929f, + 0.387458056211472f, -0.487169682979584f, 0.387084424495697f, -0.487083226442337f, + 0.386710882186890f, -0.486996471881866f, 0.386337369680405f, -0.486909449100494f, + 0.385963946580887f, -0.486822128295898f, 0.385590612888336f, -0.486734509468079f, + 0.385217308998108f, -0.486646622419357f, 0.384844094514847f, -0.486558437347412f, + 0.384470939636230f, -0.486469984054565f, 0.384097874164581f, -0.486381232738495f, + 0.383724838495255f, -0.486292183399200f, 0.383351892232895f, -0.486202865839005f, + 0.382979035377502f, -0.486113250255585f, 0.382606208324432f, -0.486023366451263f, + 0.382233470678329f, -0.485933154821396f, 0.381860792636871f, -0.485842704772949f, + 0.381488204002380f, -0.485751956701279f, 0.381115674972534f, -0.485660910606384f, + 0.380743205547333f, -0.485569566488266f, 0.380370795726776f, -0.485477954149246f, + 0.379998475313187f, -0.485386073589325f, 0.379626244306564f, -0.485293895006180f, + 0.379254043102264f, -0.485201418399811f, 0.378881961107254f, -0.485108673572540f, + 0.378509908914566f, -0.485015630722046f, 0.378137946128845f, -0.484922289848328f, + 0.377766042947769f, -0.484828680753708f, 0.377394229173660f, -0.484734803438187f, + 0.377022475004196f, -0.484640628099442f, 0.376650810241699f, -0.484546154737473f, + 0.376279205083847f, -0.484451413154602f, 0.375907659530640f, -0.484356373548508f, + 0.375536203384399f, -0.484261035919189f, 0.375164806842804f, -0.484165430068970f, + 0.374793499708176f, -0.484069555997849f, 0.374422252178192f, -0.483973383903503f, + 0.374051094055176f, -0.483876913785934f, 0.373679995536804f, -0.483780175447464f, + 0.373308986425400f, -0.483683139085770f, 0.372938036918640f, -0.483585834503174f, + 0.372567176818848f, -0.483488231897354f, 0.372196376323700f, -0.483390361070633f, + 0.371825665235519f, -0.483292192220688f, 0.371455013751984f, -0.483193725347519f, + 0.371084451675415f, -0.483094990253448f, 0.370713949203491f, -0.482995986938477f, + 0.370343536138535f, -0.482896685600281f, 0.369973212480545f, -0.482797086238861f, + 0.369602948427200f, -0.482697218656540f, 0.369232743978500f, -0.482597053050995f, + 0.368862658739090f, -0.482496619224548f, 0.368492603302002f, -0.482395917177200f, + 0.368122667074203f, -0.482294887304306f, 0.367752790451050f, -0.482193619012833f, + 0.367382973432541f, -0.482092022895813f, 0.367013275623322f, -0.481990188360214f, + 0.366643607616425f, -0.481888025999069f, 0.366274058818817f, -0.481785595417023f, + 0.365904569625854f, -0.481682896614075f, 0.365535169839859f, -0.481579899787903f, + 0.365165829658508f, -0.481476634740829f, 0.364796578884125f, -0.481373071670532f, + 0.364427417516708f, -0.481269240379334f, 0.364058345556259f, -0.481165111064911f, + 0.363689333200455f, -0.481060713529587f, 0.363320380449295f, -0.480956017971039f, + 0.362951546907425f, -0.480851024389267f, 0.362582772970200f, -0.480745792388916f, + 0.362214088439941f, -0.480640232563019f, 0.361845493316650f, -0.480534434318542f, + 0.361476957798004f, -0.480428308248520f, 0.361108511686325f, -0.480321943759918f, + 0.360740154981613f, -0.480215251445770f, 0.360371887683868f, -0.480108320713043f, + 0.360003679990768f, -0.480001062154770f, 0.359635561704636f, -0.479893565177917f, + 0.359267532825470f, -0.479785770177841f, 0.358899593353271f, -0.479677677154541f, + 0.358531713485718f, -0.479569315910339f, 0.358163923025131f, -0.479460656642914f, + 0.357796221971512f, -0.479351729154587f, 0.357428610324860f, -0.479242533445358f, + 0.357061088085175f, -0.479133039712906f, 0.356693625450134f, -0.479023247957230f, + 0.356326282024384f, -0.478913217782974f, 0.355958998203278f, -0.478802859783173f, + 0.355591803789139f, -0.478692263364792f, 0.355224698781967f, -0.478581339120865f, + 0.354857653379440f, -0.478470176458359f, 0.354490727186203f, -0.478358715772629f, + 0.354123860597610f, -0.478246957063675f, 0.353757113218308f, -0.478134930133820f, + 0.353390425443649f, -0.478022634983063f, 0.353023827075958f, -0.477910041809082f, + 0.352657318115234f, -0.477797180414200f, 0.352290898561478f, -0.477684020996094f, + 0.351924568414688f, -0.477570593357086f, 0.351558297872543f, -0.477456867694855f, + 0.351192146539688f, -0.477342873811722f, 0.350826084613800f, -0.477228611707687f, + 0.350460082292557f, -0.477114051580429f, 0.350094199180603f, -0.476999223232269f, + 0.349728375673294f, -0.476884096860886f, 0.349362671375275f, -0.476768702268600f, + 0.348997026681900f, -0.476653009653091f, 0.348631471395493f, -0.476537048816681f, + 0.348266035318375f, -0.476420819759369f, 0.347900658845901f, -0.476304292678833f, + 0.347535371780396f, -0.476187497377396f, 0.347170203924179f, -0.476070433855057f, + 0.346805095672607f, -0.475953072309494f, 0.346440106630325f, -0.475835442543030f, + 0.346075177192688f, -0.475717514753342f, 0.345710366964340f, -0.475599318742752f, + 0.345345616340637f, -0.475480824708939f, 0.344980984926224f, -0.475362062454224f, + 0.344616413116455f, -0.475243031978607f, 0.344251960515976f, -0.475123733282089f, + 0.343887597322464f, -0.475004136562347f, 0.343523323535919f, -0.474884241819382f, + 0.343159139156342f, -0.474764078855515f, 0.342795044183731f, -0.474643647670746f, + 0.342431038618088f, -0.474522948265076f, 0.342067122459412f, -0.474401950836182f, + 0.341703325510025f, -0.474280685186386f, 0.341339588165283f, -0.474159121513367f, + 0.340975970029831f, -0.474037289619446f, 0.340612411499023f, -0.473915189504623f, + 0.340248972177505f, -0.473792791366577f, 0.339885622262955f, -0.473670125007629f, + 0.339522391557693f, -0.473547190427780f, 0.339159220457077f, -0.473423957824707f, + 0.338796168565750f, -0.473300457000732f, 0.338433176279068f, -0.473176687955856f, + 0.338070303201675f, -0.473052620887756f, 0.337707549333572f, -0.472928285598755f, + 0.337344855070114f, -0.472803652286530f, 0.336982280015945f, -0.472678780555725f, + 0.336619764566422f, -0.472553610801697f, 0.336257368326187f, -0.472428143024445f, + 0.335895091295242f, -0.472302407026291f, 0.335532873868942f, -0.472176402807236f, + 0.335170775651932f, -0.472050130367279f, 0.334808766841888f, -0.471923559904099f, + 0.334446847438812f, -0.471796721220016f, 0.334085017442703f, -0.471669614315033f, + 0.333723306655884f, -0.471542209386826f, 0.333361685276031f, -0.471414536237717f, + 0.333000183105469f, -0.471286594867706f, 0.332638740539551f, -0.471158385276794f, + 0.332277417182922f, -0.471029877662659f, 0.331916213035584f, -0.470901101827621f, + 0.331555068492889f, -0.470772027969360f, 0.331194043159485f, -0.470642685890198f, + 0.330833107233047f, -0.470513075590134f, 0.330472290515900f, -0.470383197069168f, + 0.330111563205719f, -0.470253020524979f, 0.329750925302505f, -0.470122605562210f, + 0.329390406608582f, -0.469991862773895f, 0.329029977321625f, -0.469860881567001f, + 0.328669637441635f, -0.469729602336884f, 0.328309416770935f, -0.469598054885864f, + 0.327949285507202f, -0.469466239213943f, 0.327589273452759f, -0.469334155321121f, + 0.327229350805283f, -0.469201773405075f, 0.326869517564774f, -0.469069123268127f, + 0.326509803533554f, -0.468936175107956f, 0.326150178909302f, -0.468802988529205f, + 0.325790673494339f, -0.468669503927231f, 0.325431257486343f, -0.468535751104355f, + 0.325071930885315f, -0.468401730060577f, 0.324712723493576f, -0.468267410993576f, + 0.324353635311127f, -0.468132823705673f, 0.323994606733322f, -0.467997968196869f, + 0.323635727167130f, -0.467862844467163f, 0.323276937007904f, -0.467727422714233f, + 0.322918236255646f, -0.467591762542725f, 0.322559654712677f, -0.467455804347992f, + 0.322201162576675f, -0.467319577932358f, 0.321842789649963f, -0.467183053493500f, + 0.321484506130219f, -0.467046260833740f, 0.321126341819763f, -0.466909229755402f, + 0.320768296718597f, -0.466771900653839f, 0.320410341024399f, -0.466634273529053f, + 0.320052474737167f, -0.466496407985687f, 0.319694727659225f, -0.466358244419098f, + 0.319337099790573f, -0.466219812631607f, 0.318979561328888f, -0.466081112623215f, + 0.318622142076492f, -0.465942144393921f, 0.318264812231064f, -0.465802878141403f, + 0.317907601594925f, -0.465663343667984f, 0.317550510168076f, -0.465523540973663f, + 0.317193508148193f, -0.465383470058441f, 0.316836595535278f, -0.465243130922318f, + 0.316479831933975f, -0.465102523565292f, 0.316123157739639f, -0.464961618185043f, + 0.315766572952271f, -0.464820444583893f, 0.315410137176514f, -0.464679002761841f, + 0.315053790807724f, -0.464537292718887f, 0.314697533845901f, -0.464395314455032f, + 0.314341396093369f, -0.464253038167953f, 0.313985377550125f, -0.464110493659973f, + 0.313629478216171f, -0.463967710733414f, 0.313273668289185f, -0.463824629783630f, + 0.312917977571487f, -0.463681250810623f, 0.312562376260757f, -0.463537633419037f, + 0.312206923961639f, -0.463393747806549f, 0.311851561069489f, -0.463249564170837f, + 0.311496287584305f, -0.463105112314224f, 0.311141163110733f, -0.462960392236710f, + 0.310786128044128f, -0.462815403938293f, 0.310431212186813f, -0.462670147418976f, + 0.310076385736465f, -0.462524622678757f, 0.309721708297729f, -0.462378799915314f, + 0.309367120265961f, -0.462232738733292f, 0.309012651443481f, -0.462086379528046f, + 0.308658272027969f, -0.461939752101898f, 0.308304041624069f, -0.461792886257172f, + 0.307949900627136f, -0.461645722389221f, 0.307595878839493f, -0.461498260498047f, + 0.307241976261139f, -0.461350560188293f, 0.306888192892075f, -0.461202591657639f, + 0.306534498929977f, -0.461054325103760f, 0.306180924177170f, -0.460905820131302f, + 0.305827468633652f, -0.460757017135620f, 0.305474132299423f, -0.460607945919037f, + 0.305120915174484f, -0.460458606481552f, 0.304767817258835f, -0.460309028625488f, + 0.304414808750153f, -0.460159152746201f, 0.304061919450760f, -0.460008978843689f, + 0.303709149360657f, -0.459858566522598f, 0.303356528282166f, -0.459707885980606f, + 0.303003966808319f, -0.459556937217712f, 0.302651554346085f, -0.459405690431595f, + 0.302299261093140f, -0.459254205226898f, 0.301947087049484f, -0.459102421998978f, + 0.301595002412796f, -0.458950400352478f, 0.301243066787720f, -0.458798080682755f, + 0.300891220569611f, -0.458645492792130f, 0.300539493560791f, -0.458492636680603f, + 0.300187885761261f, -0.458339542150497f, 0.299836426973343f, -0.458186149597168f, + 0.299485057592392f, -0.458032488822937f, 0.299133807420731f, -0.457878559827805f, + 0.298782676458359f, -0.457724362611771f, 0.298431664705276f, -0.457569897174835f, + 0.298080772161484f, -0.457415163516998f, 0.297729998826981f, -0.457260161638260f, + 0.297379344701767f, -0.457104891538620f, 0.297028809785843f, -0.456949323415756f, + 0.296678394079208f, -0.456793516874313f, 0.296328097581863f, -0.456637442111969f, + 0.295977920293808f, -0.456481099128723f, 0.295627862215042f, -0.456324487924576f, + 0.295277923345566f, -0.456167578697205f, 0.294928103685379f, -0.456010431051254f, + 0.294578403234482f, -0.455853015184402f, 0.294228851795197f, -0.455695331096649f, + 0.293879389762878f, -0.455537378787994f, 0.293530046939850f, -0.455379128456116f, + 0.293180853128433f, -0.455220639705658f, 0.292831748723984f, -0.455061882734299f, + 0.292482793331146f, -0.454902857542038f, 0.292133957147598f, -0.454743564128876f, + 0.291785210371017f, -0.454584002494812f, 0.291436612606049f, -0.454424172639847f, + 0.291088134050369f, -0.454264044761658f, 0.290739774703979f, -0.454103678464890f, + 0.290391564369202f, -0.453943043947220f, 0.290043443441391f, -0.453782171010971f, + 0.289695471525192f, -0.453621000051498f, 0.289347589015961f, -0.453459560871124f, + 0.288999855518341f, -0.453297853469849f, 0.288652241230011f, -0.453135877847672f, + 0.288304775953293f, -0.452973634004593f, 0.287957400083542f, -0.452811151742935f, + 0.287610173225403f, -0.452648371458054f, 0.287263035774231f, -0.452485352754593f, + 0.286916047334671f, -0.452322036027908f, 0.286569178104401f, -0.452158480882645f, + 0.286222457885742f, -0.451994657516479f, 0.285875827074051f, -0.451830536127090f, + 0.285529345273972f, -0.451666176319122f, 0.285182982683182f, -0.451501548290253f, + 0.284836769104004f, -0.451336652040482f, 0.284490644931793f, -0.451171487569809f, + 0.284144669771194f, -0.451006084680557f, 0.283798813819885f, -0.450840383768082f, + 0.283453077077866f, -0.450674414634705f, 0.283107489347458f, -0.450508207082748f, + 0.282762020826340f, -0.450341701507568f, 0.282416671514511f, -0.450174957513809f, + 0.282071471214294f, -0.450007945299149f, 0.281726360321045f, -0.449840664863586f, + 0.281381398439407f, -0.449673116207123f, 0.281036585569382f, -0.449505299329758f, + 0.280691891908646f, -0.449337244033813f, 0.280347317457199f, -0.449168890714645f, + 0.280002862215042f, -0.449000298976898f, 0.279658555984497f, -0.448831409215927f, + 0.279314368963242f, -0.448662281036377f, 0.278970301151276f, -0.448492884635925f, + 0.278626382350922f, -0.448323249816895f, 0.278282582759857f, -0.448153316974640f, + 0.277938932180405f, -0.447983115911484f, 0.277595400810242f, -0.447812676429749f, + 0.277251988649368f, -0.447641968727112f, 0.276908725500107f, -0.447470992803574f, + 0.276565581560135f, -0.447299748659134f, 0.276222556829453f, -0.447128236293793f, + 0.275879681110382f, -0.446956485509872f, 0.275536954402924f, -0.446784436702728f, + 0.275194346904755f, -0.446612149477005f, 0.274851858615875f, -0.446439594030380f, + 0.274509519338608f, -0.446266770362854f, 0.274167299270630f, -0.446093708276749f, + 0.273825198411942f, -0.445920348167419f, 0.273483246564865f, -0.445746749639511f, + 0.273141443729401f, -0.445572882890701f, 0.272799760103226f, -0.445398747920990f, + 0.272458195686340f, -0.445224374532700f, 0.272116780281067f, -0.445049703121185f, + 0.271775513887405f, -0.444874793291092f, 0.271434366703033f, -0.444699615240097f, + 0.271093338727951f, -0.444524168968201f, 0.270752459764481f, -0.444348484277725f, + 0.270411729812622f, -0.444172531366348f, 0.270071119070053f, -0.443996280431747f, + 0.269730657339096f, -0.443819820880890f, 0.269390314817429f, -0.443643063306808f, + 0.269050091505051f, -0.443466067314148f, 0.268710047006607f, -0.443288803100586f, + 0.268370121717453f, -0.443111270666122f, 0.268030315637589f, -0.442933470010757f, + 0.267690658569336f, -0.442755430936813f, 0.267351150512695f, -0.442577123641968f, + 0.267011761665344f, -0.442398548126221f, 0.266672492027283f, -0.442219734191895f, + 0.266333401203156f, -0.442040622234344f, 0.265994429588318f, -0.441861271858215f, + 0.265655577182770f, -0.441681683063507f, 0.265316903591156f, -0.441501796245575f, + 0.264978319406509f, -0.441321671009064f, 0.264639914035797f, -0.441141277551651f, + 0.264301627874374f, -0.440960645675659f, 0.263963490724564f, -0.440779715776443f, + 0.263625472784042f, -0.440598547458649f, 0.263287603855133f, -0.440417140722275f, + 0.262949883937836f, -0.440235435962677f, 0.262612313032150f, -0.440053492784500f, + 0.262274861335754f, -0.439871311187744f, 0.261937558650970f, -0.439688831567764f, + 0.261600375175476f, -0.439506113529205f, 0.261263370513916f, -0.439323127269745f, + 0.260926485061646f, -0.439139902591705f, 0.260589718818665f, -0.438956409692764f, + 0.260253131389618f, -0.438772648572922f, 0.259916663169861f, -0.438588619232178f, + 0.259580343961716f, -0.438404351472855f, 0.259244143962860f, -0.438219845294952f, + 0.258908122777939f, -0.438035041093826f, 0.258572220802307f, -0.437849998474121f, + 0.258236467838287f, -0.437664687633514f, 0.257900834083557f, -0.437479138374329f, + 0.257565379142761f, -0.437293320894241f, 0.257230043411255f, -0.437107264995575f, + 0.256894856691360f, -0.436920911073685f, 0.256559818983078f, -0.436734348535538f, + 0.256224930286407f, -0.436547487974167f, 0.255890160799026f, -0.436360388994217f, + 0.255555540323257f, -0.436173021793365f, 0.255221068859100f, -0.435985416173935f, + 0.254886746406555f, -0.435797542333603f, 0.254552572965622f, -0.435609430074692f, + 0.254218548536301f, -0.435421019792557f, 0.253884643316269f, -0.435232400894165f, + 0.253550916910172f, -0.435043483972549f, 0.253217309713364f, -0.434854328632355f, + 0.252883851528168f, -0.434664934873581f, 0.252550542354584f, -0.434475272893906f, + 0.252217382192612f, -0.434285342693329f, 0.251884341239929f, -0.434095174074173f, + 0.251551479101181f, -0.433904737234116f, 0.251218736171722f, -0.433714061975479f, + 0.250886172056198f, -0.433523118495941f, 0.250553727149963f, -0.433331936597824f, + 0.250221431255341f, -0.433140486478806f, 0.249889299273491f, -0.432948768138886f, + 0.249557301402092f, -0.432756811380386f, 0.249225467443466f, -0.432564586400986f, + 0.248893767595291f, -0.432372123003006f, 0.248562216758728f, -0.432179391384125f, + 0.248230814933777f, -0.431986421346664f, 0.247899547219276f, -0.431793183088303f, + 0.247568443417549f, -0.431599706411362f, 0.247237488627434f, -0.431405961513519f, + 0.246906682848930f, -0.431211978197098f, 0.246576011180878f, -0.431017726659775f, + 0.246245503425598f, -0.430823236703873f, 0.245915144681931f, -0.430628478527069f, + 0.245584934949875f, -0.430433481931686f, 0.245254859328270f, -0.430238217115402f, + 0.244924947619438f, -0.430042684078217f, 0.244595184922218f, -0.429846942424774f, + 0.244265571236610f, -0.429650902748108f, 0.243936106562614f, -0.429454624652863f, + 0.243606805801392f, -0.429258108139038f, 0.243277639150620f, -0.429061323404312f, + 0.242948621511459f, -0.428864300251007f, 0.242619767785072f, -0.428667008876801f, + 0.242291063070297f, -0.428469479084015f, 0.241962507367134f, -0.428271710872650f, + 0.241634100675583f, -0.428073674440384f, 0.241305842995644f, -0.427875369787216f, + 0.240977749228477f, -0.427676826715469f, 0.240649804472923f, -0.427478045225143f, + 0.240322008728981f, -0.427278995513916f, 0.239994361996651f, -0.427079707384110f, + 0.239666879177094f, -0.426880151033401f, 0.239339530467987f, -0.426680356264114f, + 0.239012360572815f, -0.426480293273926f, 0.238685324788094f, -0.426279991865158f, + 0.238358452916145f, -0.426079452037811f, 0.238031730055809f, -0.425878643989563f, + 0.237705156207085f, -0.425677597522736f, 0.237378746271133f, -0.425476282835007f, + 0.237052485346794f, -0.425274729728699f, 0.236726388335228f, -0.425072938203812f, + 0.236400425434113f, -0.424870878458023f, 0.236074641346931f, -0.424668580293655f, + 0.235749006271362f, -0.424466013908386f, 0.235423520207405f, -0.424263238906860f, + 0.235098183155060f, -0.424060165882111f, 0.234773010015488f, -0.423856884241104f, + 0.234448000788689f, -0.423653304576874f, 0.234123140573502f, -0.423449516296387f, + 0.233798429369926f, -0.423245459794998f, 0.233473882079124f, -0.423041164875031f, + 0.233149498701096f, -0.422836631536484f, 0.232825264334679f, -0.422631829977036f, + 0.232501193881035f, -0.422426789999008f, 0.232177272439003f, -0.422221481800079f, + 0.231853514909744f, -0.422015935182571f, 0.231529906392097f, -0.421810150146484f, + 0.231206461787224f, -0.421604126691818f, 0.230883181095123f, -0.421397835016251f, + 0.230560049414635f, -0.421191304922104f, 0.230237081646919f, -0.420984506607056f, + 0.229914262890816f, -0.420777499675751f, 0.229591608047485f, -0.420570224523544f, + 0.229269117116928f, -0.420362681150436f, 0.228946775197983f, -0.420154929161072f, + 0.228624612092972f, -0.419946908950806f, 0.228302597999573f, -0.419738620519638f, + 0.227980732917786f, -0.419530123472214f, 0.227659046649933f, -0.419321358203888f, + 0.227337509393692f, -0.419112354516983f, 0.227016136050224f, -0.418903112411499f, + 0.226694911718369f, -0.418693602085114f, 0.226373866200447f, -0.418483853340149f, + 0.226052969694138f, -0.418273866176605f, 0.225732237100601f, -0.418063640594482f, + 0.225411668419838f, -0.417853146791458f, 0.225091263651848f, -0.417642414569855f, + 0.224771007895470f, -0.417431443929672f, 0.224450930953026f, -0.417220205068588f, + 0.224131003022194f, -0.417008757591248f, 0.223811239004135f, -0.416797041893005f, + 0.223491653800011f, -0.416585087776184f, 0.223172217607498f, -0.416372895240784f, + 0.222852945327759f, -0.416160434484482f, 0.222533836960793f, -0.415947735309601f, + 0.222214877605438f, -0.415734797716141f, 0.221896097064018f, -0.415521621704102f, + 0.221577480435371f, -0.415308207273483f, 0.221259027719498f, -0.415094524621964f, + 0.220940738916397f, -0.414880603551865f, 0.220622614026070f, -0.414666473865509f, + 0.220304638147354f, -0.414452046155930f, 0.219986841082573f, -0.414237409830093f, + 0.219669207930565f, -0.414022535085678f, 0.219351738691330f, -0.413807392120361f, + 0.219034433364868f, -0.413592010736465f, 0.218717306852341f, -0.413376390933990f, + 0.218400329351425f, -0.413160532712936f, 0.218083515763283f, -0.412944436073303f, + 0.217766880989075f, -0.412728071212769f, 0.217450410127640f, -0.412511497735977f, + 0.217134088277817f, -0.412294656038284f, 0.216817945241928f, -0.412077575922012f, + 0.216501981019974f, -0.411860257387161f, 0.216186165809631f, -0.411642700433731f, + 0.215870529413223f, -0.411424905061722f, 0.215555042028427f, -0.411206841468811f, + 0.215239733457565f, -0.410988569259644f, 0.214924603700638f, -0.410770028829575f, + 0.214609622955322f, -0.410551249980927f, 0.214294821023941f, -0.410332232713699f, + 0.213980183005333f, -0.410112977027893f, 0.213665723800659f, -0.409893482923508f, + 0.213351413607597f, -0.409673750400543f, 0.213037282228470f, -0.409453779459000f, + 0.212723329663277f, -0.409233570098877f, 0.212409526109695f, -0.409013092517853f, + 0.212095901370049f, -0.408792406320572f, 0.211782455444336f, -0.408571451902390f, + 0.211469158530235f, -0.408350288867950f, 0.211156040430069f, -0.408128857612610f, + 0.210843101143837f, -0.407907217741013f, 0.210530325770378f, -0.407685309648514f, + 0.210217714309692f, -0.407463163137436f, 0.209905281662941f, -0.407240778207779f, + 0.209593027830124f, -0.407018154859543f, 0.209280923008919f, -0.406795293092728f, + 0.208969011902809f, -0.406572192907333f, 0.208657249808311f, -0.406348884105682f, + 0.208345666527748f, -0.406125307083130f, 0.208034262061119f, -0.405901491641998f, + 0.207723021507263f, -0.405677437782288f, 0.207411959767342f, -0.405453115701675f, + 0.207101076841354f, -0.405228585004807f, 0.206790357828140f, -0.405003815889359f, + 0.206479802727699f, -0.404778808355331f, 0.206169426441193f, -0.404553562402725f, + 0.205859228968620f, -0.404328078031540f, 0.205549195408821f, -0.404102355241776f, + 0.205239340662956f, -0.403876423835754f, 0.204929664731026f, -0.403650224208832f, + 0.204620152711868f, -0.403423786163330f, 0.204310819506645f, -0.403197109699249f, + 0.204001650214195f, -0.402970194816589f, 0.203692659735680f, -0.402743041515350f, + 0.203383848071098f, -0.402515679597855f, 0.203075215220451f, -0.402288049459457f, + 0.202766746282578f, -0.402060180902481f, 0.202458456158638f, -0.401832103729248f, + 0.202150344848633f, -0.401603758335114f, 0.201842412352562f, -0.401375204324722f, + 0.201534643769264f, -0.401146411895752f, 0.201227053999901f, -0.400917351245880f, + 0.200919643044472f, -0.400688081979752f, 0.200612410902977f, -0.400458574295044f, + 0.200305357575417f, -0.400228828191757f, 0.199998468160629f, -0.399998843669891f, + 0.199691757559776f, -0.399768620729446f, 0.199385225772858f, -0.399538189172745f, + 0.199078872799873f, -0.399307489395142f, 0.198772698640823f, -0.399076581001282f, + 0.198466703295708f, -0.398845434188843f, 0.198160871863365f, -0.398614019155502f, + 0.197855234146118f, -0.398382395505905f, 0.197549775242805f, -0.398150533437729f, + 0.197244480252266f, -0.397918462753296f, 0.196939364075661f, -0.397686123847961f, + 0.196634441614151f, -0.397453576326370f, 0.196329683065414f, -0.397220760583878f, + 0.196025103330612f, -0.396987736225128f, 0.195720717310905f, -0.396754473447800f, + 0.195416495203972f, -0.396520972251892f, 0.195112451910973f, -0.396287262439728f, + 0.194808602333069f, -0.396053284406662f, 0.194504916667938f, -0.395819097757339f, + 0.194201424717903f, -0.395584672689438f, 0.193898096680641f, -0.395350009202957f, + 0.193594962358475f, -0.395115107297897f, 0.193292006850243f, -0.394879996776581f, + 0.192989215254784f, -0.394644618034363f, 0.192686617374420f, -0.394409030675888f, + 0.192384198307991f, -0.394173204898834f, 0.192081972956657f, -0.393937170505524f, + 0.191779911518097f, -0.393700867891312f, 0.191478043794632f, -0.393464356660843f, + 0.191176339983940f, -0.393227607011795f, 0.190874829888344f, -0.392990618944168f, + 0.190573498606682f, -0.392753422260284f, 0.190272361040115f, -0.392515957355499f, + 0.189971387386322f, -0.392278283834457f, 0.189670607447624f, -0.392040401697159f, + 0.189370006322861f, -0.391802251338959f, 0.189069598913193f, -0.391563892364502f, + 0.188769355416298f, -0.391325294971466f, 0.188469305634499f, -0.391086459159851f, + 0.188169434666634f, -0.390847414731979f, 0.187869757413864f, -0.390608131885529f, + 0.187570258975029f, -0.390368610620499f, 0.187270939350128f, -0.390128880739212f, + 0.186971798539162f, -0.389888882637024f, 0.186672851443291f, -0.389648675918579f, + 0.186374098062515f, -0.389408260583878f, 0.186075508594513f, -0.389167606830597f, + 0.185777112841606f, -0.388926714658737f, 0.185478910803795f, -0.388685584068298f, + 0.185180887579918f, -0.388444244861603f, 0.184883043169975f, -0.388202667236328f, + 0.184585392475128f, -0.387960851192474f, 0.184287920594215f, -0.387718826532364f, + 0.183990627527237f, -0.387476563453674f, 0.183693528175354f, -0.387234061956406f, + 0.183396622538567f, -0.386991351842880f, 0.183099895715714f, -0.386748403310776f, + 0.182803362607956f, -0.386505216360092f, 0.182507008314133f, -0.386261820793152f, + 0.182210832834244f, -0.386018186807632f, 0.181914865970612f, -0.385774344205856f, + 0.181619063019753f, -0.385530263185501f, 0.181323468685150f, -0.385285943746567f, + 0.181028053164482f, -0.385041415691376f, 0.180732816457748f, -0.384796649217606f, + 0.180437773466110f, -0.384551674127579f, 0.180142924189568f, -0.384306460618973f, + 0.179848253726959f, -0.384061008691788f, 0.179553776979446f, -0.383815348148346f, + 0.179259493947029f, -0.383569449186325f, 0.178965389728546f, -0.383323341608047f, + 0.178671479225159f, -0.383076995611191f, 0.178377762436867f, -0.382830440998077f, + 0.178084224462509f, -0.382583618164063f, 0.177790880203247f, -0.382336616516113f, + 0.177497729659081f, -0.382089376449585f, 0.177204772830009f, -0.381841897964478f, + 0.176911994814873f, -0.381594210863113f, 0.176619410514832f, -0.381346285343170f, + 0.176327019929886f, -0.381098151206970f, 0.176034808158875f, -0.380849778652191f, + 0.175742805004120f, -0.380601197481155f, 0.175450980663300f, -0.380352377891541f, + 0.175159350037575f, -0.380103349685669f, 0.174867913126946f, -0.379854083061218f, + 0.174576655030251f, -0.379604607820511f, 0.174285605549812f, -0.379354894161224f, + 0.173994734883308f, -0.379104942083359f, 0.173704057931900f, -0.378854811191559f, + 0.173413574695587f, -0.378604412078857f, 0.173123285174370f, -0.378353834152222f, + 0.172833189368248f, -0.378102988004684f, 0.172543287277222f, -0.377851963043213f, + 0.172253578901291f, -0.377600699663162f, 0.171964049339294f, -0.377349197864532f, + 0.171674728393555f, -0.377097487449646f, 0.171385586261749f, -0.376845568418503f, + 0.171096652746201f, -0.376593410968781f, 0.170807912945747f, -0.376341015100479f, + 0.170519351959229f, -0.376088410615921f, 0.170230999588966f, -0.375835597515106f, + 0.169942826032639f, -0.375582575798035f, 0.169654861092567f, -0.375329315662384f, + 0.169367074966431f, -0.375075817108154f, 0.169079497456551f, -0.374822109937668f, + 0.168792113661766f, -0.374568194150925f, 0.168504923582077f, -0.374314039945602f, + 0.168217927217484f, -0.374059677124023f, 0.167931124567986f, -0.373805105686188f, + 0.167644515633583f, -0.373550295829773f, 0.167358100414276f, -0.373295277357101f, + 0.167071878910065f, -0.373040050268173f, 0.166785866022110f, -0.372784584760666f, + 0.166500031948090f, -0.372528880834579f, 0.166214406490326f, -0.372272998094559f, + 0.165928974747658f, -0.372016876935959f, 0.165643751621246f, -0.371760547161102f, + 0.165358707308769f, -0.371503978967667f, 0.165073871612549f, -0.371247202157974f, + 0.164789214730263f, -0.370990216732025f, 0.164504766464233f, -0.370732992887497f, + 0.164220526814461f, -0.370475560426712f, 0.163936465978622f, -0.370217919349670f, + 0.163652613759041f, -0.369960039854050f, 0.163368955254555f, -0.369701951742172f, + 0.163085505366325f, -0.369443655014038f, 0.162802234292030f, -0.369185149669647f, + 0.162519171833992f, -0.368926405906677f, 0.162236317992210f, -0.368667453527451f, + 0.161953642964363f, -0.368408292531967f, 0.161671176552773f, -0.368148893117905f, + 0.161388918757439f, -0.367889285087585f, 0.161106839776039f, -0.367629468441010f, + 0.160824984312058f, -0.367369443178177f, 0.160543307662010f, -0.367109179496765f, + 0.160261839628220f, -0.366848707199097f, 0.159980565309525f, -0.366588026285172f, + 0.159699499607086f, -0.366327136754990f, 0.159418627619743f, -0.366066008806229f, + 0.159137964248657f, -0.365804702043533f, 0.158857494592667f, -0.365543156862259f, + 0.158577233552933f, -0.365281373262405f, 0.158297166228294f, -0.365019410848618f, + 0.158017292618752f, -0.364757210016251f, 0.157737627625465f, -0.364494800567627f, + 0.157458171248436f, -0.364232182502747f, 0.157178908586502f, -0.363969355821610f, + 0.156899839639664f, -0.363706320524216f, 0.156620979309082f, -0.363443046808243f, + 0.156342327594757f, -0.363179564476013f, 0.156063869595528f, -0.362915903329849f, + 0.155785620212555f, -0.362651973962784f, 0.155507579445839f, -0.362387865781784f, + 0.155229732394218f, -0.362123548984528f, 0.154952079057693f, -0.361858993768692f, + 0.154674649238586f, -0.361594229936600f, 0.154397398233414f, -0.361329287290573f, + 0.154120370745659f, -0.361064106225967f, 0.153843536973000f, -0.360798716545105f, + 0.153566911816597f, -0.360533088445663f, 0.153290495276451f, -0.360267281532288f, + 0.153014272451401f, -0.360001266002655f, 0.152738258242607f, -0.359735012054443f, + 0.152462437748909f, -0.359468549489975f, 0.152186840772629f, -0.359201908111572f, + 0.151911437511444f, -0.358935028314590f, 0.151636242866516f, -0.358667939901352f, + 0.151361241936684f, -0.358400642871857f, 0.151086464524269f, -0.358133137226105f, + 0.150811880826950f, -0.357865422964096f, 0.150537505745888f, -0.357597470283508f, + 0.150263324379921f, -0.357329338788986f, 0.149989366531372f, -0.357060998678207f, + 0.149715602397919f, -0.356792420148849f, 0.149442046880722f, -0.356523662805557f, + 0.149168699979782f, -0.356254696846008f, 0.148895561695099f, -0.355985492467880f, + 0.148622632026672f, -0.355716109275818f, 0.148349896073341f, -0.355446487665176f, + 0.148077383637428f, -0.355176687240601f, 0.147805064916611f, -0.354906648397446f, + 0.147532954812050f, -0.354636400938034f, 0.147261068224907f, -0.354365974664688f, + 0.146989375352860f, -0.354095309972763f, 0.146717891097069f, -0.353824466466904f, + 0.146446615457535f, -0.353553384542465f, 0.146175548434258f, -0.353282123804092f, + 0.145904675126076f, -0.353010624647141f, 0.145634025335312f, -0.352738946676254f, + 0.145363584160805f, -0.352467030286789f, 0.145093351602554f, -0.352194935083389f, + 0.144823327660561f, -0.351922631263733f, 0.144553512334824f, -0.351650089025497f, + 0.144283905625343f, -0.351377367973328f, 0.144014507532120f, -0.351104438304901f, + 0.143745318055153f, -0.350831300020218f, 0.143476337194443f, -0.350557953119278f, + 0.143207564949989f, -0.350284397602081f, 0.142939001321793f, -0.350010633468628f, + 0.142670661211014f, -0.349736660718918f, 0.142402514815331f, -0.349462509155273f, + 0.142134591937065f, -0.349188119173050f, 0.141866862773895f, -0.348913550376892f, + 0.141599357128143f, -0.348638743162155f, 0.141332060098648f, -0.348363757133484f, + 0.141064971685410f, -0.348088562488556f, 0.140798106789589f, -0.347813159227371f, + 0.140531435608864f, -0.347537547349930f, 0.140264987945557f, -0.347261756658554f, + 0.139998748898506f, -0.346985727548599f, 0.139732718467712f, -0.346709519624710f, + 0.139466896653175f, -0.346433073282242f, 0.139201298356056f, -0.346156448125839f, + 0.138935908675194f, -0.345879614353180f, 0.138670727610588f, -0.345602601766586f, + 0.138405755162239f, -0.345325350761414f, 0.138141006231308f, -0.345047920942307f, + 0.137876465916634f, -0.344770282506943f, 0.137612134218216f, -0.344492435455322f, + 0.137348011136055f, -0.344214379787445f, 0.137084111571312f, -0.343936115503311f, + 0.136820420622826f, -0.343657672405243f, 0.136556953191757f, -0.343379020690918f, + 0.136293679475784f, -0.343100160360336f, 0.136030644178391f, -0.342821091413498f, + 0.135767802596092f, -0.342541843652725f, 0.135505184531212f, -0.342262357473373f, + 0.135242775082588f, -0.341982692480087f, 0.134980589151382f, -0.341702848672867f, + 0.134718611836433f, -0.341422766447067f, 0.134456858038902f, -0.341142505407333f, + 0.134195312857628f, -0.340862035751343f, 0.133933976292610f, -0.340581357479095f, + 0.133672863245010f, -0.340300500392914f, 0.133411958813667f, -0.340019434690475f, + 0.133151277899742f, -0.339738160371780f, 0.132890805602074f, -0.339456677436829f, + 0.132630556821823f, -0.339175015687943f, 0.132370531558990f, -0.338893145322800f, + 0.132110700011253f, -0.338611096143723f, 0.131851106882095f, -0.338328808546066f, + 0.131591722369194f, -0.338046342134476f, 0.131332546472549f, -0.337763696908951f, + 0.131073594093323f, -0.337480813264847f, 0.130814850330353f, -0.337197750806808f, + 0.130556344985962f, -0.336914509534836f, 0.130298033356667f, -0.336631029844284f, + 0.130039945244789f, -0.336347371339798f, 0.129782080650330f, -0.336063534021378f, + 0.129524439573288f, -0.335779488086700f, 0.129267007112503f, -0.335495233535767f, + 0.129009798169136f, -0.335210770368576f, 0.128752797842026f, -0.334926128387451f, + 0.128496021032333f, -0.334641307592392f, 0.128239467740059f, -0.334356248378754f, + 0.127983123064041f, -0.334071010351181f, 0.127727001905441f, -0.333785593509674f, + 0.127471104264259f, -0.333499968051910f, 0.127215430140495f, -0.333214133977890f, + 0.126959964632988f, -0.332928121089935f, 0.126704722642899f, -0.332641899585724f, + 0.126449704170227f, -0.332355499267578f, 0.126194894313812f, -0.332068890333176f, + 0.125940307974815f, -0.331782072782516f, 0.125685945153236f, -0.331495076417923f, + 0.125431805849075f, -0.331207901239395f, 0.125177875161171f, -0.330920487642288f, + 0.124924175441265f, -0.330632925033569f, 0.124670691788197f, -0.330345153808594f, + 0.124417431652546f, -0.330057173967361f, 0.124164395034313f, -0.329769015312195f, + 0.123911574482918f, -0.329480648040771f, 0.123658977448940f, -0.329192101955414f, + 0.123406603932381f, -0.328903347253799f, 0.123154446482658f, -0.328614413738251f, + 0.122902512550354f, -0.328325271606445f, 0.122650802135468f, -0.328035950660706f, + 0.122399315237999f, -0.327746421098709f, 0.122148044407368f, -0.327456712722778f, + 0.121896997094154f, -0.327166795730591f, 0.121646173298359f, -0.326876699924469f, + 0.121395580470562f, -0.326586425304413f, 0.121145196259022f, -0.326295942068100f, + 0.120895043015480f, -0.326005280017853f, 0.120645113289356f, -0.325714409351349f, + 0.120395407080650f, -0.325423330068588f, 0.120145916938782f, -0.325132101774216f, + 0.119896657764912f, -0.324840664863586f, 0.119647622108459f, -0.324549019336700f, + 0.119398809969425f, -0.324257194995880f, 0.119150213897228f, -0.323965191841125f, + 0.118901848793030f, -0.323672980070114f, 0.118653707206249f, -0.323380589485168f, + 0.118405789136887f, -0.323088020086288f, 0.118158094584942f, -0.322795242071152f, + 0.117910631000996f, -0.322502255439758f, 0.117663383483887f, -0.322209119796753f, + 0.117416366934776f, -0.321915775537491f, 0.117169573903084f, -0.321622252464294f, + 0.116923004388809f, -0.321328520774841f, 0.116676658391953f, -0.321034610271454f, + 0.116430543363094f, -0.320740520954132f, 0.116184651851654f, -0.320446223020554f, + 0.115938983857632f, -0.320151746273041f, 0.115693546831608f, -0.319857090711594f, + 0.115448333323002f, -0.319562226533890f, 0.115203343331814f, -0.319267183542252f, + 0.114958584308624f, -0.318971961736679f, 0.114714048802853f, -0.318676531314850f, + 0.114469736814499f, -0.318380922079086f, 0.114225655794144f, -0.318085134029388f, + 0.113981798291206f, -0.317789167165756f, 0.113738171756268f, -0.317492991685867f, + 0.113494776189327f, -0.317196637392044f, 0.113251596689224f, -0.316900104284287f, + 0.113008655607700f, -0.316603392362595f, 0.112765938043594f, -0.316306471824646f, + 0.112523443996906f, -0.316009372472763f, 0.112281180918217f, -0.315712094306946f, + 0.112039148807526f, -0.315414607524872f, 0.111797347664833f, -0.315116971731186f, + 0.111555770039558f, -0.314819127321243f, 0.111314415931702f, -0.314521104097366f, + 0.111073300242424f, -0.314222872257233f, 0.110832408070564f, -0.313924491405487f, + 0.110591746866703f, -0.313625901937485f, 0.110351309180260f, -0.313327133655548f, + 0.110111102461815f, -0.313028186559677f, 0.109871134161949f, -0.312729060649872f, + 0.109631389379501f, -0.312429755926132f, 0.109391868114471f, -0.312130242586136f, + 0.109152585268021f, -0.311830550432205f, 0.108913525938988f, -0.311530679464340f, + 0.108674705028534f, -0.311230629682541f, 0.108436107635498f, -0.310930401086807f, + 0.108197741210461f, -0.310629993677139f, 0.107959605753422f, -0.310329377651215f, + 0.107721701264381f, -0.310028612613678f, 0.107484027743340f, -0.309727638959885f, + 0.107246585190296f, -0.309426486492157f, 0.107009373605251f, -0.309125155210495f, + 0.106772392988205f, -0.308823645114899f, 0.106535643339157f, -0.308521956205368f, + 0.106299124658108f, -0.308220088481903f, 0.106062836945057f, -0.307918041944504f, + 0.105826787650585f, -0.307615786790848f, 0.105590961873531f, -0.307313382625580f, + 0.105355374515057f, -0.307010769844055f, 0.105120018124580f, -0.306708008050919f, + 0.104884892702103f, -0.306405037641525f, 0.104649998247623f, -0.306101888418198f, + 0.104415334761143f, -0.305798590183258f, 0.104180909693241f, -0.305495083332062f, + 0.103946708142757f, -0.305191397666931f, 0.103712752461433f, -0.304887533187866f, + 0.103479020297527f, -0.304583519697189f, 0.103245526552200f, -0.304279297590256f, + 0.103012263774872f, -0.303974896669388f, 0.102779231965542f, -0.303670316934586f, + 0.102546438574791f, -0.303365558385849f, 0.102313876152039f, -0.303060621023178f, + 0.102081544697285f, -0.302755534648895f, 0.101849451661110f, -0.302450239658356f, + 0.101617597043514f, -0.302144765853882f, 0.101385973393917f, -0.301839113235474f, + 0.101154580712318f, -0.301533311605453f, 0.100923426449299f, -0.301227301359177f, + 0.100692503154278f, -0.300921112298965f, 0.100461818277836f, -0.300614774227142f, + 0.100231364369392f, -0.300308227539063f, 0.100001148879528f, -0.300001531839371f, + 0.099771171808243f, -0.299694657325745f, 0.099541425704956f, -0.299387603998184f, + 0.099311910569668f, -0.299080342054367f, 0.099082641303539f, -0.298772931098938f, + 0.098853603005409f, -0.298465341329575f, 0.098624803125858f, -0.298157602548599f, + 0.098396234214306f, -0.297849655151367f, 0.098167903721333f, -0.297541528940201f, + 0.097939811646938f, -0.297233253717422f, 0.097711957991123f, -0.296924799680710f, + 0.097484335303307f, -0.296616137027740f, 0.097256951034069f, -0.296307325363159f, + 0.097029805183411f, -0.295998334884644f, 0.096802897751331f, -0.295689195394516f, + 0.096576221287251f, -0.295379847288132f, 0.096349790692329f, -0.295070350170136f, + 0.096123591065407f, -0.294760644435883f, 0.095897629857063f, -0.294450789690018f, + 0.095671907067299f, -0.294140785932541f, 0.095446422696114f, -0.293830573558807f, + 0.095221176743507f, -0.293520182371140f, 0.094996169209480f, -0.293209642171860f, + 0.094771400094032f, -0.292898923158646f, 0.094546869397163f, -0.292588025331497f, + 0.094322577118874f, -0.292276978492737f, 0.094098523259163f, -0.291965723037720f, + 0.093874707818031f, -0.291654318571091f, 0.093651130795479f, -0.291342735290527f, + 0.093427792191505f, -0.291031002998352f, 0.093204692006111f, -0.290719062089920f, + 0.092981837689877f, -0.290406972169876f, 0.092759214341640f, -0.290094703435898f, + 0.092536836862564f, -0.289782285690308f, 0.092314697802067f, -0.289469659328461f, + 0.092092797160149f, -0.289156883955002f, 0.091871134936810f, -0.288843959569931f, + 0.091649711132050f, -0.288530826568604f, 0.091428533196449f, -0.288217544555664f, + 0.091207593679428f, -0.287904083728790f, 0.090986892580986f, -0.287590473890305f, + 0.090766437351704f, -0.287276685237885f, 0.090546220541000f, -0.286962717771530f, + 0.090326242148876f, -0.286648571491241f, 0.090106502175331f, -0.286334276199341f, + 0.089887008070946f, -0.286019802093506f, 0.089667752385139f, -0.285705178976059f, + 0.089448742568493f, -0.285390377044678f, 0.089229971170425f, -0.285075396299362f, + 0.089011445641518f, -0.284760266542435f, 0.088793158531189f, -0.284444957971573f, + 0.088575109839439f, -0.284129470586777f, 0.088357307016850f, -0.283813834190369f, + 0.088139742612839f, -0.283498018980026f, 0.087922424077988f, -0.283182054758072f, + 0.087705351412296f, -0.282865911722183f, 0.087488517165184f, -0.282549589872360f, + 0.087271921336651f, -0.282233119010925f, 0.087055571377277f, -0.281916469335556f, + 0.086839467287064f, -0.281599670648575f, 0.086623609066010f, -0.281282693147659f, + 0.086407989263535f, -0.280965566635132f, 0.086192607879639f, -0.280648261308670f, + 0.085977479815483f, -0.280330777168274f, 0.085762590169907f, -0.280013144016266f, + 0.085547938942909f, -0.279695361852646f, 0.085333541035652f, -0.279377400875092f, + 0.085119381546974f, -0.279059261083603f, 0.084905467927456f, -0.278740972280502f, + 0.084691800177097f, -0.278422504663467f, 0.084478378295898f, -0.278103888034821f, + 0.084265194833279f, -0.277785122394562f, 0.084052257239819f, -0.277466177940369f, + 0.083839565515518f, -0.277147054672241f, 0.083627119660378f, -0.276827782392502f, + 0.083414919674397f, -0.276508361101151f, 0.083202958106995f, -0.276188760995865f, + 0.082991249859333f, -0.275868982076645f, 0.082779780030251f, -0.275549083948135f, + 0.082568563520908f, -0.275228977203369f, 0.082357585430145f, -0.274908751249313f, + 0.082146860659122f, -0.274588316679001f, 0.081936374306679f, -0.274267762899399f, + 0.081726133823395f, -0.273947030305862f, 0.081516146659851f, -0.273626148700714f, + 0.081306397914886f, -0.273305088281631f, 0.081096902489662f, -0.272983878850937f, + 0.080887645483017f, -0.272662490606308f, 0.080678641796112f, -0.272340953350067f, + 0.080469883978367f, -0.272019267082214f, 0.080261372029781f, -0.271697402000427f, + 0.080053105950356f, -0.271375387907028f, 0.079845085740089f, -0.271053224802017f, + 0.079637311398983f, -0.270730882883072f, 0.079429790377617f, -0.270408391952515f, + 0.079222507774830f, -0.270085722208023f, 0.079015478491783f, -0.269762933254242f, + 0.078808702528477f, -0.269439965486526f, 0.078602164983749f, -0.269116818904877f, + 0.078395880758762f, -0.268793523311615f, 0.078189842402935f, -0.268470078706741f, + 0.077984049916267f, -0.268146485090256f, 0.077778510749340f, -0.267822742462158f, + 0.077573217451572f, -0.267498821020126f, 0.077368170022964f, -0.267174720764160f, + 0.077163375914097f, -0.266850501298904f, 0.076958827674389f, -0.266526103019714f, + 0.076754532754421f, -0.266201555728912f, 0.076550483703613f, -0.265876859426498f, + 0.076346680521965f, -0.265552014112473f, 0.076143130660057f, -0.265226989984512f, + 0.075939826667309f, -0.264901816844940f, 0.075736775994301f, -0.264576494693756f, + 0.075533971190453f, -0.264250993728638f, 0.075331419706345f, -0.263925373554230f, + 0.075129114091396f, -0.263599574565887f, 0.074927061796188f, -0.263273626565933f, + 0.074725262820721f, -0.262947499752045f, 0.074523709714413f, -0.262621253728867f, + 0.074322402477264f, -0.262294828891754f, 0.074121348559856f, -0.261968284845352f, + 0.073920547962189f, -0.261641561985016f, 0.073720000684261f, -0.261314690113068f, + 0.073519699275494f, -0.260987639427185f, 0.073319651186466f, -0.260660469532013f, + 0.073119848966599f, -0.260333120822906f, 0.072920300066471f, -0.260005623102188f, + 0.072721004486084f, -0.259678006172180f, 0.072521962225437f, -0.259350210428238f, + 0.072323165833950f, -0.259022265672684f, 0.072124622762203f, -0.258694142103195f, + 0.071926333010197f, -0.258365899324417f, 0.071728296577930f, -0.258037507534027f, + 0.071530513465405f, -0.257708936929703f, 0.071332976222038f, -0.257380217313766f, + 0.071135692298412f, -0.257051378488541f, 0.070938661694527f, -0.256722360849380f, + 0.070741884410381f, -0.256393194198608f, 0.070545360445976f, -0.256063878536224f, + 0.070349089801311f, -0.255734413862228f, 0.070153072476387f, -0.255404800176620f, + 0.069957308471203f, -0.255075037479401f, 0.069761790335178f, -0.254745125770569f, + 0.069566532969475f, -0.254415065050125f, 0.069371521472931f, -0.254084855318069f, + 0.069176770746708f, -0.253754496574402f, 0.068982265889645f, -0.253423988819122f, + 0.068788021802902f, -0.253093332052231f, 0.068594031035900f, -0.252762526273727f, + 0.068400286138058f, -0.252431541681290f, 0.068206802010536f, -0.252100437879562f, + 0.068013571202755f, -0.251769185066223f, 0.067820593714714f, -0.251437783241272f, + 0.067627869546413f, -0.251106232404709f, 0.067435398697853f, -0.250774532556534f, + 0.067243188619614f, -0.250442683696747f, 0.067051224410534f, -0.250110685825348f, + 0.066859520971775f, -0.249778553843498f, 0.066668070852757f, -0.249446272850037f, + 0.066476874053478f, -0.249113827943802f, 0.066285938024521f, -0.248781248927116f, + 0.066095255315304f, -0.248448520898819f, 0.065904818475246f, -0.248115643858910f, + 0.065714649856091f, -0.247782632708550f, 0.065524727106094f, -0.247449472546577f, + 0.065335065126419f, -0.247116148471832f, 0.065145656466484f, -0.246782705187798f, + 0.064956501126289f, -0.246449097990990f, 0.064767606556416f, -0.246115356683731f, + 0.064578965306282f, -0.245781451463699f, 0.064390584826469f, -0.245447427034378f, + 0.064202457666397f, -0.245113238692284f, 0.064014583826065f, -0.244778916239738f, + 0.063826970756054f, -0.244444444775581f, 0.063639611005783f, -0.244109839200974f, + 0.063452512025833f, -0.243775084614754f, 0.063265666365623f, -0.243440181016922f, + 0.063079081475735f, -0.243105143308640f, 0.062892749905586f, -0.242769956588745f, + 0.062706671655178f, -0.242434620857239f, 0.062520854175091f, -0.242099151015282f, + 0.062335297465324f, -0.241763532161713f, 0.062149997800589f, -0.241427779197693f, + 0.061964951455593f, -0.241091892123222f, 0.061780165880919f, -0.240755841135979f, + 0.061595637351274f, -0.240419670939446f, 0.061411365866661f, -0.240083336830139f, + 0.061227355152369f, -0.239746883511543f, 0.061043601483107f, -0.239410281181335f, + 0.060860104858875f, -0.239073529839516f, 0.060676865279675f, -0.238736644387245f, + 0.060493886470795f, -0.238399609923363f, 0.060311164706945f, -0.238062441349030f, + 0.060128703713417f, -0.237725138664246f, 0.059946499764919f, -0.237387686967850f, + 0.059764556586742f, -0.237050101161003f, 0.059582870453596f, -0.236712381243706f, + 0.059401445090771f, -0.236374512314796f, 0.059220276772976f, -0.236036509275436f, + 0.059039369225502f, -0.235698372125626f, 0.058858718723059f, -0.235360085964203f, + 0.058678328990936f, -0.235021665692329f, 0.058498200029135f, -0.234683111310005f, + 0.058318331837654f, -0.234344407916069f, 0.058138720691204f, -0.234005570411682f, + 0.057959370315075f, -0.233666598796844f, 0.057780280709267f, -0.233327493071556f, + 0.057601451873779f, -0.232988253235817f, 0.057422880083323f, -0.232648864388466f, + 0.057244572788477f, -0.232309341430664f, 0.057066522538662f, -0.231969684362412f, + 0.056888736784458f, -0.231629893183708f, 0.056711208075285f, -0.231289967894554f, + 0.056533940136433f, -0.230949893593788f, 0.056356932967901f, -0.230609700083733f, + 0.056180190294981f, -0.230269357562065f, 0.056003704667091f, -0.229928880929947f, + 0.055827483534813f, -0.229588270187378f, 0.055651523172855f, -0.229247525334358f, + 0.055475823581219f, -0.228906646370888f, 0.055300384759903f, -0.228565633296967f, + 0.055125206708908f, -0.228224486112595f, 0.054950293153524f, -0.227883204817772f, + 0.054775636643171f, -0.227541789412498f, 0.054601248353720f, -0.227200239896774f, + 0.054427117109299f, -0.226858556270599f, 0.054253250360489f, -0.226516738533974f, + 0.054079644382000f, -0.226174786686897f, 0.053906302899122f, -0.225832715630531f, + 0.053733222186565f, -0.225490495562553f, 0.053560405969620f, -0.225148141384125f, + 0.053387850522995f, -0.224805667996407f, 0.053215555846691f, -0.224463045597076f, + 0.053043525665998f, -0.224120303988457f, 0.052871759980917f, -0.223777428269386f, + 0.052700258791447f, -0.223434418439865f, 0.052529018372297f, -0.223091274499893f, + 0.052358038723469f, -0.222748011350632f, 0.052187327295542f, -0.222404599189758f, + 0.052016876637936f, -0.222061067819595f, 0.051846686750650f, -0.221717402338982f, + 0.051676765084267f, -0.221373617649078f, 0.051507104188204f, -0.221029683947563f, + 0.051337707787752f, -0.220685631036758f, 0.051168579608202f, -0.220341444015503f, + 0.050999708473682f, -0.219997137784958f, 0.050831105560064f, -0.219652697443962f, + 0.050662767142057f, -0.219308122992516f, 0.050494693219662f, -0.218963414430618f, + 0.050326880067587f, -0.218618586659431f, 0.050159335136414f, -0.218273624777794f, + 0.049992054700851f, -0.217928543686867f, 0.049825038760900f, -0.217583328485489f, + 0.049658283591270f, -0.217237979173660f, 0.049491796642542f, -0.216892510652542f, + 0.049325577914715f, -0.216546908020973f, 0.049159619957209f, -0.216201186180115f, + 0.048993926495314f, -0.215855330228806f, 0.048828501254320f, -0.215509355068207f, + 0.048663340508938f, -0.215163245797157f, 0.048498444259167f, -0.214817002415657f, + 0.048333816230297f, -0.214470639824867f, 0.048169452697039f, -0.214124158024788f, + 0.048005353659391f, -0.213777542114258f, 0.047841522842646f, -0.213430806994438f, + 0.047677956521511f, -0.213083937764168f, 0.047514654695988f, -0.212736949324608f, + 0.047351621091366f, -0.212389841675758f, 0.047188851982355f, -0.212042599916458f, + 0.047026351094246f, -0.211695238947868f, 0.046864114701748f, -0.211347743868828f, + 0.046702146530151f, -0.211000129580498f, 0.046540446579456f, -0.210652396082878f, + 0.046379011124372f, -0.210304543375969f, 0.046217843890190f, -0.209956556558609f, + 0.046056941151619f, -0.209608450531960f, 0.045896306633949f, -0.209260210394859f, + 0.045735940337181f, -0.208911851048470f, 0.045575842261314f, -0.208563387393951f, + 0.045416008681059f, -0.208214774727821f, 0.045256443321705f, -0.207866057753563f, + 0.045097146183252f, -0.207517206668854f, 0.044938117265701f, -0.207168251276016f, + 0.044779352843761f, -0.206819161772728f, 0.044620860368013f, -0.206469938158989f, + 0.044462632387877f, -0.206120610237122f, 0.044304672628641f, -0.205771163105965f, + 0.044146984815598f, -0.205421581864357f, 0.043989561498165f, -0.205071896314621f, + 0.043832406401634f, -0.204722076654434f, 0.043675523251295f, -0.204372137784958f, + 0.043518904596567f, -0.204022079706192f, 0.043362557888031f, -0.203671902418137f, + 0.043206475675106f, -0.203321605920792f, 0.043050665408373f, -0.202971190214157f, + 0.042895123362541f, -0.202620655298233f, 0.042739849537611f, -0.202270001173019f, + 0.042584843933582f, -0.201919227838516f, 0.042430106550455f, -0.201568335294724f, + 0.042275641113520f, -0.201217323541641f, 0.042121443897486f, -0.200866192579269f, + 0.041967518627644f, -0.200514942407608f, 0.041813857853413f, -0.200163587927818f, + 0.041660469025373f, -0.199812099337578f, 0.041507352143526f, -0.199460506439209f, + 0.041354499757290f, -0.199108779430389f, 0.041201923042536f, -0.198756948113441f, + 0.041049610823393f, -0.198404997587204f, 0.040897574275732f, -0.198052927851677f, + 0.040745802223682f, -0.197700738906860f, 0.040594302117825f, -0.197348430752754f, + 0.040443073958158f, -0.196996018290520f, 0.040292114019394f, -0.196643486618996f, + 0.040141426026821f, -0.196290835738182f, 0.039991009980440f, -0.195938065648079f, + 0.039840862154961f, -0.195585191249847f, 0.039690986275673f, -0.195232197642326f, + 0.039541378617287f, -0.194879084825516f, 0.039392042905092f, -0.194525867700577f, + 0.039242979139090f, -0.194172516465187f, 0.039094187319279f, -0.193819075822830f, + 0.038945667445660f, -0.193465501070023f, 0.038797415792942f, -0.193111822009087f, + 0.038649436086416f, -0.192758023738861f, 0.038501728326082f, -0.192404121160507f, + 0.038354292511940f, -0.192050099372864f, 0.038207128643990f, -0.191695958375931f, + 0.038060232996941f, -0.191341713070869f, 0.037913613021374f, -0.190987363457680f, + 0.037767261266708f, -0.190632879734039f, 0.037621185183525f, -0.190278306603432f, + 0.037475381046534f, -0.189923599362373f, 0.037329845130444f, -0.189568802714348f, + 0.037184584885836f, -0.189213871955872f, 0.037039596587420f, -0.188858851790428f, + 0.036894880235195f, -0.188503712415695f, 0.036750435829163f, -0.188148453831673f, + 0.036606263369322f, -0.187793090939522f, 0.036462362855673f, -0.187437608838081f, + 0.036318738013506f, -0.187082037329674f, 0.036175385117531f, -0.186726331710815f, + 0.036032304167747f, -0.186370536684990f, 0.035889495164156f, -0.186014622449875f, + 0.035746958106756f, -0.185658603906631f, 0.035604696720839f, -0.185302466154099f, + 0.035462711006403f, -0.184946224093437f, 0.035320993512869f, -0.184589877724648f, + 0.035179551690817f, -0.184233412146568f, 0.035038381814957f, -0.183876842260361f, + 0.034897487610579f, -0.183520168066025f, 0.034756865352392f, -0.183163389563560f, + 0.034616518765688f, -0.182806491851807f, 0.034476444125175f, -0.182449504733086f, + 0.034336645156145f, -0.182092398405075f, 0.034197118133307f, -0.181735187768936f, + 0.034057866781950f, -0.181377857923508f, 0.033918887376785f, -0.181020438671112f, + 0.033780183643103f, -0.180662900209427f, 0.033641755580902f, -0.180305257439613f, + 0.033503599464893f, -0.179947525262833f, 0.033365719020367f, -0.179589673876762f, + 0.033228114247322f, -0.179231703281403f, 0.033090781420469f, -0.178873643279076f, + 0.032953724265099f, -0.178515478968620f, 0.032816942781210f, -0.178157210350037f, + 0.032680433243513f, -0.177798837423325f, 0.032544203102589f, -0.177440345287323f, + 0.032408244907856f, -0.177081763744354f, 0.032272562384605f, -0.176723077893257f, + 0.032137155532837f, -0.176364272832870f, 0.032002024352551f, -0.176005378365517f, + 0.031867165118456f, -0.175646379590034f, 0.031732585281134f, -0.175287276506424f, + 0.031598277390003f, -0.174928069114685f, 0.031464248895645f, -0.174568757414818f, + 0.031330492347479f, -0.174209341406822f, 0.031197015196085f, -0.173849821090698f, + 0.031063811853528f, -0.173490211367607f, 0.030930884182453f, -0.173130482435226f, + 0.030798232182860f, -0.172770664095879f, 0.030665857717395f, -0.172410741448402f, + 0.030533758923411f, -0.172050714492798f, 0.030401935800910f, -0.171690583229065f, + 0.030270388349891f, -0.171330362558365f, 0.030139118432999f, -0.170970037579536f, + 0.030008124187589f, -0.170609608292580f, 0.029877405613661f, -0.170249074697495f, + 0.029746964573860f, -0.169888436794281f, 0.029616801068187f, -0.169527709484100f, + 0.029486913233995f, -0.169166877865791f, 0.029357301071286f, -0.168805956840515f, + 0.029227968305349f, -0.168444931507111f, 0.029098909348249f, -0.168083801865578f, + 0.028970129787922f, -0.167722567915916f, 0.028841627761722f, -0.167361244559288f, + 0.028713401407003f, -0.166999831795692f, 0.028585452586412f, -0.166638299822807f, + 0.028457781299949f, -0.166276678442955f, 0.028330387547612f, -0.165914967656136f, + 0.028203271329403f, -0.165553152561188f, 0.028076432645321f, -0.165191248059273f, + 0.027949871495366f, -0.164829224348068f, 0.027823587879539f, -0.164467126131058f, + 0.027697581797838f, -0.164104923605919f, 0.027571853250265f, -0.163742616772652f, + 0.027446404099464f, -0.163380220532417f, 0.027321230620146f, -0.163017734885216f, + 0.027196336537600f, -0.162655144929886f, 0.027071721851826f, -0.162292465567589f, + 0.026947384700179f, -0.161929681897163f, 0.026823325082660f, -0.161566808819771f, + 0.026699542999268f, -0.161203846335411f, 0.026576040312648f, -0.160840779542923f, + 0.026452817022800f, -0.160477623343468f, 0.026329871267080f, -0.160114362835884f, + 0.026207204908133f, -0.159751012921333f, 0.026084816083312f, -0.159387573599815f, + 0.025962706655264f, -0.159024044871330f, 0.025840876623988f, -0.158660411834717f, + 0.025719324126840f, -0.158296689391136f, 0.025598052889109f, -0.157932877540588f, + 0.025477059185505f, -0.157568961381912f, 0.025356344878674f, -0.157204970717430f, + 0.025235909968615f, -0.156840875744820f, 0.025115754455328f, -0.156476691365242f, + 0.024995878338814f, -0.156112402677536f, 0.024876279756427f, -0.155748039484024f, + 0.024756962433457f, -0.155383571982384f, 0.024637924507260f, -0.155019029974937f, + 0.024519165977836f, -0.154654383659363f, 0.024400688707829f, -0.154289647936821f, + 0.024282488971949f, -0.153924822807312f, 0.024164570495486f, -0.153559908270836f, + 0.024046931415796f, -0.153194904327393f, 0.023929571732879f, -0.152829796075821f, + 0.023812493309379f, -0.152464613318443f, 0.023695694282651f, -0.152099341154099f, + 0.023579176515341f, -0.151733979582787f, 0.023462938144803f, -0.151368513703346f, + 0.023346979171038f, -0.151002973318100f, 0.023231301456690f, -0.150637343525887f, + 0.023115905001760f, -0.150271624326706f, 0.023000787943602f, -0.149905815720558f, + 0.022885952144861f, -0.149539917707443f, 0.022771397605538f, -0.149173930287361f, + 0.022657122462988f, -0.148807853460312f, 0.022543128579855f, -0.148441687226295f, + 0.022429415956140f, -0.148075446486473f, 0.022315984591842f, -0.147709101438522f, + 0.022202832624316f, -0.147342681884766f, 0.022089963778853f, -0.146976172924042f, + 0.021977374330163f, -0.146609574556351f, 0.021865066140890f, -0.146242901682854f, + 0.021753041073680f, -0.145876124501228f, 0.021641295403242f, -0.145509272813797f, + 0.021529832854867f, -0.145142331719399f, 0.021418649703264f, -0.144775316119194f, + 0.021307749673724f, -0.144408211112022f, 0.021197130903602f, -0.144041016697884f, + 0.021086793392897f, -0.143673732876778f, 0.020976737141609f, -0.143306359648705f, + 0.020866964012384f, -0.142938911914825f, 0.020757472142577f, -0.142571389675140f, + 0.020648263394833f, -0.142203763127327f, 0.020539334043860f, -0.141836062073708f, + 0.020430689677596f, -0.141468286514282f, 0.020322324708104f, -0.141100421547890f, + 0.020214242860675f, -0.140732467174530f, 0.020106444135308f, -0.140364438295364f, + 0.019998926669359f, -0.139996320009232f, 0.019891692325473f, -0.139628127217293f, + 0.019784741103649f, -0.139259845018387f, 0.019678071141243f, -0.138891488313675f, + 0.019571684300900f, -0.138523042201996f, 0.019465578719974f, -0.138154521584511f, + 0.019359756261110f, -0.137785911560059f, 0.019254218786955f, -0.137417227029800f, + 0.019148962572217f, -0.137048453092575f, 0.019043987616897f, -0.136679604649544f, + 0.018939297646284f, -0.136310681700706f, 0.018834890797734f, -0.135941669344902f, + 0.018730765208602f, -0.135572582483292f, 0.018626924604177f, -0.135203406214714f, + 0.018523367121816f, -0.134834155440331f, 0.018420090898871f, -0.134464830160141f, + 0.018317099660635f, -0.134095430374146f, 0.018214391544461f, -0.133725941181183f, + 0.018111966550350f, -0.133356377482414f, 0.018009826540947f, -0.132986739277840f, + 0.017907967790961f, -0.132617011666298f, 0.017806394025683f, -0.132247209548950f, + 0.017705103382468f, -0.131877332925797f, 0.017604095861316f, -0.131507381796837f, + 0.017503373324871f, -0.131137356162071f, 0.017402933910489f, -0.130767241120338f, + 0.017302779480815f, -0.130397051572800f, 0.017202908173203f, -0.130026802420616f, + 0.017103319987655f, -0.129656463861465f, 0.017004016786814f, -0.129286035895348f, + 0.016904998570681f, -0.128915548324585f, 0.016806263476610f, -0.128544986248016f, + 0.016707813367248f, -0.128174334764481f, 0.016609646379948f, -0.127803623676300f, + 0.016511764377356f, -0.127432823181152f, 0.016414167359471f, -0.127061963081360f, + 0.016316853463650f, -0.126691013574600f, 0.016219824552536f, -0.126320004463196f, + 0.016123080626130f, -0.125948905944824f, 0.016026621684432f, -0.125577747821808f, + 0.015930447727442f, -0.125206500291824f, 0.015834558755159f, -0.124835193157196f, + 0.015738952904940f, -0.124463804066181f, 0.015643632039428f, -0.124092340469360f, + 0.015548598021269f, -0.123720809817314f, 0.015453847125173f, -0.123349204659462f, + 0.015359382145107f, -0.122977524995804f, 0.015265202149749f, -0.122605770826340f, + 0.015171307139099f, -0.122233949601650f, 0.015077698044479f, -0.121862053871155f, + 0.014984373003244f, -0.121490091085434f, 0.014891333878040f, -0.121118053793907f, + 0.014798580668867f, -0.120745941996574f, 0.014706112444401f, -0.120373763144016f, + 0.014613929204643f, -0.120001509785652f, 0.014522032812238f, -0.119629189372063f, + 0.014430420473218f, -0.119256794452667f, 0.014339094981551f, -0.118884332478046f, + 0.014248054474592f, -0.118511803448200f, 0.014157299883664f, -0.118139199912548f, + 0.014066831208766f, -0.117766529321671f, 0.013976648449898f, -0.117393791675568f, + 0.013886751607060f, -0.117020979523659f, 0.013797140680254f, -0.116648100316525f, + 0.013707815669477f, -0.116275154054165f, 0.013618776574731f, -0.115902140736580f, + 0.013530024327338f, -0.115529052913189f, 0.013441557064652f, -0.115155905485153f, + 0.013353376649320f, -0.114782683551311f, 0.013265483081341f, -0.114409394562244f, + 0.013177875429392f, -0.114036038517952f, 0.013090553693473f, -0.113662622869015f, + 0.013003518804908f, -0.113289132714272f, 0.012916770763695f, -0.112915575504303f, + 0.012830308638513f, -0.112541958689690f, 0.012744133360684f, -0.112168267369270f, + 0.012658244930208f, -0.111794516444206f, 0.012572642415762f, -0.111420698463917f, + 0.012487327679992f, -0.111046813428402f, 0.012402298860252f, -0.110672861337662f, + 0.012317557819188f, -0.110298842191696f, 0.012233102694154f, -0.109924763441086f, + 0.012148935347795f, -0.109550617635250f, 0.012065053917468f, -0.109176412224770f, + 0.011981460265815f, -0.108802139759064f, 0.011898153461516f, -0.108427800238132f, + 0.011815134435892f, -0.108053401112556f, 0.011732402257621f, -0.107678934931755f, + 0.011649956926703f, -0.107304409146309f, 0.011567799374461f, -0.106929816305637f, + 0.011485928669572f, -0.106555156409740f, 0.011404345743358f, -0.106180444359779f, + 0.011323049664497f, -0.105805665254593f, 0.011242041364312f, -0.105430819094181f, + 0.011161320842803f, -0.105055920779705f, 0.011080888099968f, -0.104680955410004f, + 0.011000742204487f, -0.104305922985077f, 0.010920885019004f, -0.103930838406086f, + 0.010841314680874f, -0.103555686771870f, 0.010762032121420f, -0.103180475533009f, + 0.010683037340641f, -0.102805204689503f, 0.010604331269860f, -0.102429874241352f, + 0.010525912046432f, -0.102054484188557f, 0.010447781533003f, -0.101679034531116f, + 0.010369938798249f, -0.101303517818451f, 0.010292383842170f, -0.100927948951721f, + 0.010215117596090f, -0.100552320480347f, 0.010138138197362f, -0.100176624953747f, + 0.010061448439956f, -0.099800877273083f, 0.009985045529902f, -0.099425069987774f, + 0.009908932261169f, -0.099049203097820f, 0.009833106771111f, -0.098673284053802f, + 0.009757569059730f, -0.098297297954559f, 0.009682320058346f, -0.097921259701252f, + 0.009607359766960f, -0.097545161843300f, 0.009532688185573f, -0.097169004380703f, + 0.009458304382861f, -0.096792794764042f, 0.009384209290147f, -0.096416525542736f, + 0.009310402907431f, -0.096040196716785f, 0.009236886166036f, -0.095663815736771f, + 0.009163657203317f, -0.095287375152111f, 0.009090716950595f, -0.094910882413387f, + 0.009018065407872f, -0.094534330070019f, 0.008945702575147f, -0.094157725572586f, + 0.008873629383743f, -0.093781061470509f, 0.008801844902337f, -0.093404345214367f, + 0.008730349130929f, -0.093027576804161f, 0.008659142069519f, -0.092650748789310f, + 0.008588224649429f, -0.092273868620396f, 0.008517595939338f, -0.091896936297417f, + 0.008447255939245f, -0.091519944369793f, 0.008377205580473f, -0.091142900288105f, + 0.008307444863021f, -0.090765804052353f, 0.008237972855568f, -0.090388655662537f, + 0.008168790489435f, -0.090011447668076f, 0.008099896833301f, -0.089634194970131f, + 0.008031292818487f, -0.089256882667542f, 0.007962978444993f, -0.088879525661469f, + 0.007894953712821f, -0.088502109050751f, 0.007827218621969f, -0.088124647736549f, + 0.007759772241116f, -0.087747126817703f, 0.007692615967244f, -0.087369553744793f, + 0.007625748869032f, -0.086991935968399f, 0.007559171877801f, -0.086614266037941f, + 0.007492884527892f, -0.086236543953419f, 0.007426886819303f, -0.085858769714832f, + 0.007361178752035f, -0.085480943322182f, 0.007295760791749f, -0.085103072226048f, + 0.007230632472783f, -0.084725148975849f, 0.007165793795139f, -0.084347173571587f, + 0.007101245224476f, -0.083969146013260f, 0.007036986760795f, -0.083591073751450f, + 0.006973018404096f, -0.083212949335575f, 0.006909339688718f, -0.082834780216217f, + 0.006845951545984f, -0.082456558942795f, 0.006782853044569f, -0.082078292965889f, + 0.006720044650137f, -0.081699974834919f, 0.006657526828349f, -0.081321612000465f, + 0.006595299113542f, -0.080943197011948f, 0.006533361505717f, -0.080564737319946f, + 0.006471714470536f, -0.080186225473881f, 0.006410357542336f, -0.079807676374912f, + 0.006349290721118f, -0.079429075121880f, 0.006288514938205f, -0.079050421714783f, + 0.006228029262275f, -0.078671731054783f, 0.006167833693326f, -0.078292988240719f, + 0.006107929162681f, -0.077914200723171f, 0.006048315204680f, -0.077535368502140f, + 0.005988991353661f, -0.077156484127045f, 0.005929958540946f, -0.076777562499046f, + 0.005871216300875f, -0.076398596167564f, 0.005812764633447f, -0.076019577682018f, + 0.005754603538662f, -0.075640521943569f, 0.005696733482182f, -0.075261414051056f, + 0.005639153998345f, -0.074882268905640f, 0.005581865552813f, -0.074503071606159f, + 0.005524867679924f, -0.074123837053776f, 0.005468160845339f, -0.073744557797909f, + 0.005411745049059f, -0.073365233838558f, 0.005355620291084f, -0.072985872626305f, + 0.005299786105752f, -0.072606459259987f, 0.005244242958724f, -0.072227008640766f, + 0.005188991315663f, -0.071847513318062f, 0.005134030245245f, -0.071467980742455f, + 0.005079360678792f, -0.071088403463364f, 0.005024982150644f, -0.070708781480789f, + 0.004970894660801f, -0.070329122245312f, 0.004917098674923f, -0.069949418306351f, + 0.004863593727350f, -0.069569669663906f, 0.004810380283743f, -0.069189883768559f, + 0.004757457878441f, -0.068810060620308f, 0.004704826977104f, -0.068430192768574f, + 0.004652487114072f, -0.068050287663937f, 0.004600439220667f, -0.067670337855816f, + 0.004548682365566f, -0.067290350794792f, 0.004497217014432f, -0.066910326480865f, + 0.004446043167263f, -0.066530264914036f, 0.004395160824060f, -0.066150158643723f, + 0.004344569984823f, -0.065770015120506f, 0.004294271115214f, -0.065389834344387f, + 0.004244263283908f, -0.065009608864784f, 0.004194547422230f, -0.064629353582859f, + 0.004145123064518f, -0.064249053597450f, 0.004095990676433f, -0.063868723809719f, + 0.004047149792314f, -0.063488349318504f, 0.003998600877821f, -0.063107937574387f, + 0.003950343467295f, -0.062727488577366f, 0.003902378026396f, -0.062347009778023f, + 0.003854704322293f, -0.061966486275196f, 0.003807322587818f, -0.061585929244757f, + 0.003760232590139f, -0.061205338686705f, 0.003713434794918f, -0.060824707150459f, + 0.003666928736493f, -0.060444042086601f, 0.003620714880526f, -0.060063343495131f, + 0.003574792761356f, -0.059682607650757f, 0.003529162844643f, -0.059301838278770f, + 0.003483824897557f, -0.058921031653881f, 0.003438779152930f, -0.058540191501379f, + 0.003394025377929f, -0.058159314095974f, 0.003349563805386f, -0.057778406888247f, + 0.003305394435301f, -0.057397462427616f, 0.003261517267674f, -0.057016488164663f, + 0.003217932302505f, -0.056635476648808f, 0.003174639539793f, -0.056254431605339f, + 0.003131638979539f, -0.055873356759548f, 0.003088930854574f, -0.055492244660854f, + 0.003046514932066f, -0.055111102759838f, 0.003004391444847f, -0.054729927331209f, + 0.002962560392916f, -0.054348722100258f, 0.002921021543443f, -0.053967483341694f, + 0.002879775362089f, -0.053586211055517f, 0.002838821383193f, -0.053204908967018f, + 0.002798160072416f, -0.052823577076197f, 0.002757790964097f, -0.052442211657763f, + 0.002717714523897f, -0.052060816437006f, 0.002677930751815f, -0.051679391413927f, + 0.002638439415023f, -0.051297932863235f, 0.002599240746349f, -0.050916448235512f, + 0.002560334512964f, -0.050534930080175f, 0.002521721180528f, -0.050153385847807f, + 0.002483400283381f, -0.049771808087826f, 0.002445372054353f, -0.049390204250813f, + 0.002407636726275f, -0.049008570611477f, 0.002370193833485f, -0.048626907169819f, + 0.002333043841645f, -0.048245213925838f, 0.002296186750755f, -0.047863494604826f, + 0.002259622327983f, -0.047481749206781f, 0.002223350573331f, -0.047099970281124f, + 0.002187371719629f, -0.046718169003725f, 0.002151685766876f, -0.046336337924004f, + 0.002116292715073f, -0.045954477041960f, 0.002081192564219f, -0.045572593808174f, + 0.002046385314316f, -0.045190680772066f, 0.002011870965362f, -0.044808741658926f, + 0.001977649517357f, -0.044426776468754f, 0.001943721086718f, -0.044044785201550f, + 0.001910085673444f, -0.043662767857313f, 0.001876743277535f, -0.043280724436045f, + 0.001843693898991f, -0.042898654937744f, 0.001810937537812f, -0.042516563087702f, + 0.001778474310413f, -0.042134445160627f, 0.001746304216795f, -0.041752301156521f, + 0.001714427140541f, -0.041370131075382f, 0.001682843198068f, -0.040987938642502f, + 0.001651552389376f, -0.040605723857880f, 0.001620554830879f, -0.040223482996225f, + 0.001589850406162f, -0.039841219782829f, 0.001559439115226f, -0.039458930492401f, + 0.001529321074486f, -0.039076622575521f, 0.001499496400356f, -0.038694288581610f, + 0.001469964860007f, -0.038311932235956f, 0.001440726569854f, -0.037929553538561f, + 0.001411781646311f, -0.037547148764133f, 0.001383129972965f, -0.037164725363255f, + 0.001354771666229f, -0.036782283335924f, 0.001326706726104f, -0.036399815231562f, + 0.001298935036175f, -0.036017324775457f, 0.001271456829272f, -0.035634815692902f, + 0.001244271872565f, -0.035252287983894f, 0.001217380515300f, -0.034869734197855f, + 0.001190782408230f, -0.034487165510654f, 0.001164477784187f, -0.034104570746422f, + 0.001138466643170f, -0.033721961081028f, 0.001112748985179f, -0.033339329063892f, + 0.001087324810214f, -0.032956674695015f, 0.001062194118276f, -0.032574005424976f, + 0.001037356909364f, -0.032191313803196f, 0.001012813183479f, -0.031808607280254f, + 0.000988563057035f, -0.031425878405571f, 0.000964606530033f, -0.031043132767081f, + 0.000940943544265f, -0.030660368502140f, 0.000917574157938f, -0.030277585610747f, + 0.000894498312846f, -0.029894785955548f, 0.000871716125403f, -0.029511967673898f, + 0.000849227537401f, -0.029129132628441f, 0.000827032607049f, -0.028746278956532f, + 0.000805131276138f, -0.028363410383463f, 0.000783523661084f, -0.027980525046587f, + 0.000762209703680f, -0.027597622945905f, 0.000741189462133f, -0.027214704081416f, + 0.000720462878235f, -0.026831768453121f, 0.000700030010194f, -0.026448817923665f, + 0.000679890916217f, -0.026065852493048f, 0.000660045538098f, -0.025682870298624f, + 0.000640493875835f, -0.025299875065684f, 0.000621235987637f, -0.024916863068938f, + 0.000602271873504f, -0.024533838033676f, 0.000583601591643f, -0.024150796234608f, + 0.000565225025639f, -0.023767741397023f, 0.000547142291907f, -0.023384673520923f, + 0.000529353390448f, -0.023001590743661f, 0.000511858321261f, -0.022618494927883f, + 0.000494657084346f, -0.022235386073589f, 0.000477749679703f, -0.021852264180779f, + 0.000461136136437f, -0.021469129249454f, 0.000444816454547f, -0.021085981279612f, + 0.000428790634032f, -0.020702820271254f, 0.000413058703998f, -0.020319648087025f, + 0.000397620693548f, -0.019936462864280f, 0.000382476573577f, -0.019553268328309f, + 0.000367626344087f, -0.019170060753822f, 0.000353070063284f, -0.018786842003465f, + 0.000338807702065f, -0.018403612077236f, 0.000324839289533f, -0.018020370975137f, + 0.000311164796585f, -0.017637118697166f, 0.000297784281429f, -0.017253857105970f, + 0.000284697714960f, -0.016870586201549f, 0.000271905126283f, -0.016487304121256f, + 0.000259406515397f, -0.016104012727737f, 0.000247201882303f, -0.015720712020993f, + 0.000235291256104f, -0.015337402001023f, 0.000223674607696f, -0.014954082667828f, + 0.000212351980736f, -0.014570754021406f, 0.000201323360670f, -0.014187417924404f, + 0.000190588747500f, -0.013804072514176f, 0.000180148170330f, -0.013420719653368f, + 0.000170001629158f, -0.013037359341979f, 0.000160149123985f, -0.012653990648687f, + 0.000150590654812f, -0.012270614504814f, 0.000141326236189f, -0.011887230910361f, + 0.000132355868118f, -0.011503840796649f, 0.000123679565149f, -0.011120444163680f, + 0.000115297327284f, -0.010737040080130f, 0.000107209154521f, -0.010353630408645f, + 0.000099415054137f, -0.009970214217901f, 0.000091915040684f, -0.009586792439222f, + 0.000084709099610f, -0.009203365072608f, 0.000077797252743f, -0.008819932118058f, + 0.000071179500083f, -0.008436493575573f, 0.000064855834353f, -0.008053051307797f, + 0.000058826273744f, -0.007669602986425f, 0.000053090810979f, -0.007286150939763f, + 0.000047649456974f, -0.006902694236487f, 0.000042502211727f, -0.006519233807921f, + 0.000037649078877f, -0.006135769188404f, 0.000033090062061f, -0.005752300843596f, + 0.000028825161280f, -0.005368829704821f, 0.000024854381991f, -0.004985354840755f, + 0.000021177724193f, -0.004601877182722f, 0.000017795191525f, -0.004218397196382f, + 0.000014706784896f, -0.003834914416075f, 0.000011912506125f, -0.003451429307461f, + 0.000009412358850f, -0.003067942336202f, 0.000007206342616f, -0.002684453502297f, + 0.000005294459243f, -0.002300963038579f, 0.000003676709639f, -0.001917471294291f, + 0.000002353095169f, -0.001533978385851f, 0.000001323616516f, -0.001150484546088f, + 0.000000588274133f, -0.000766990066040f, 0.000000147068562f, -0.000383495149435f, + 0.000000000000000f, -0.000000000000023f, 0.000000147068562f, 0.000383495149435f, + 0.000000588274133f, 0.000766990066040f, 0.000001323616516f, 0.001150484546088f, + 0.000002353095169f, 0.001533978385851f, 0.000003676709639f, 0.001917471294291f, + 0.000005294459243f, 0.002300963038579f, 0.000007206342616f, 0.002684453502297f, + 0.000009412358850f, 0.003067942336202f, 0.000011912506125f, 0.003451429307461f, + 0.000014706784896f, 0.003834914416075f, 0.000017795191525f, 0.004218397196382f, + 0.000021177724193f, 0.004601877182722f, 0.000024854381991f, 0.004985354840755f, + 0.000028825161280f, 0.005368829704821f, 0.000033090062061f, 0.005752300843596f, + 0.000037649078877f, 0.006135769188404f, 0.000042502211727f, 0.006519233807921f, + 0.000047649456974f, 0.006902694236487f, 0.000053090810979f, 0.007286150939763f, + 0.000058826273744f, 0.007669602986425f, 0.000064855834353f, 0.008053051307797f, + 0.000071179500083f, 0.008436493575573f, 0.000077797252743f, 0.008819932118058f, + 0.000084709099610f, 0.009203365072608f, 0.000091915040684f, 0.009586792439222f, + 0.000099415054137f, 0.009970214217901f, 0.000107209154521f, 0.010353630408645f, + 0.000115297327284f, 0.010737040080130f, 0.000123679565149f, 0.011120444163680f, + 0.000132355868118f, 0.011503840796649f, 0.000141326236189f, 0.011887230910361f, + 0.000150590654812f, 0.012270614504814f, 0.000160149123985f, 0.012653990648687f, + 0.000170001629158f, 0.013037359341979f, 0.000180148170330f, 0.013420719653368f, + 0.000190588747500f, 0.013804072514176f, 0.000201323360670f, 0.014187417924404f, + 0.000212351980736f, 0.014570754021406f, 0.000223674607696f, 0.014954082667828f, + 0.000235291256104f, 0.015337402001023f, 0.000247201882303f, 0.015720712020993f, + 0.000259406515397f, 0.016104012727737f, 0.000271905126283f, 0.016487304121256f, + 0.000284697714960f, 0.016870586201549f, 0.000297784281429f, 0.017253857105970f, + 0.000311164796585f, 0.017637118697166f, 0.000324839289533f, 0.018020370975137f, + 0.000338807702065f, 0.018403612077236f, 0.000353070063284f, 0.018786842003465f, + 0.000367626344087f, 0.019170060753822f, 0.000382476573577f, 0.019553268328309f, + 0.000397620693548f, 0.019936462864280f, 0.000413058703998f, 0.020319648087025f, + 0.000428790634032f, 0.020702820271254f, 0.000444816454547f, 0.021085981279612f, + 0.000461136136437f, 0.021469129249454f, 0.000477749679703f, 0.021852264180779f, + 0.000494657084346f, 0.022235386073589f, 0.000511858321261f, 0.022618494927883f, + 0.000529353390448f, 0.023001590743661f, 0.000547142291907f, 0.023384673520923f, + 0.000565225025639f, 0.023767741397023f, 0.000583601591643f, 0.024150796234608f, + 0.000602271873504f, 0.024533838033676f, 0.000621235987637f, 0.024916863068938f, + 0.000640493875835f, 0.025299875065684f, 0.000660045538098f, 0.025682870298624f, + 0.000679890916217f, 0.026065852493048f, 0.000700030010194f, 0.026448817923665f, + 0.000720462878235f, 0.026831768453121f, 0.000741189462133f, 0.027214704081416f, + 0.000762209703680f, 0.027597622945905f, 0.000783523661084f, 0.027980525046587f, + 0.000805131276138f, 0.028363410383463f, 0.000827032607049f, 0.028746278956532f, + 0.000849227537401f, 0.029129132628441f, 0.000871716125403f, 0.029511967673898f, + 0.000894498312846f, 0.029894785955548f, 0.000917574157938f, 0.030277585610747f, + 0.000940943544265f, 0.030660368502140f, 0.000964606530033f, 0.031043132767081f, + 0.000988563057035f, 0.031425878405571f, 0.001012813183479f, 0.031808607280254f, + 0.001037356909364f, 0.032191313803196f, 0.001062194118276f, 0.032574005424976f, + 0.001087324810214f, 0.032956674695015f, 0.001112748985179f, 0.033339329063892f, + 0.001138466643170f, 0.033721961081028f, 0.001164477784187f, 0.034104570746422f, + 0.001190782408230f, 0.034487165510654f, 0.001217380515300f, 0.034869734197855f, + 0.001244271872565f, 0.035252287983894f, 0.001271456829272f, 0.035634815692902f, + 0.001298935036175f, 0.036017324775457f, 0.001326706726104f, 0.036399815231562f, + 0.001354771666229f, 0.036782283335924f, 0.001383129972965f, 0.037164725363255f, + 0.001411781646311f, 0.037547148764133f, 0.001440726569854f, 0.037929553538561f, + 0.001469964860007f, 0.038311932235956f, 0.001499496400356f, 0.038694288581610f, + 0.001529321074486f, 0.039076622575521f, 0.001559439115226f, 0.039458930492401f, + 0.001589850406162f, 0.039841219782829f, 0.001620554830879f, 0.040223482996225f, + 0.001651552389376f, 0.040605723857880f, 0.001682843198068f, 0.040987938642502f, + 0.001714427140541f, 0.041370131075382f, 0.001746304216795f, 0.041752301156521f, + 0.001778474310413f, 0.042134445160627f, 0.001810937537812f, 0.042516563087702f, + 0.001843693898991f, 0.042898654937744f, 0.001876743277535f, 0.043280724436045f, + 0.001910085673444f, 0.043662767857313f, 0.001943721086718f, 0.044044785201550f, + 0.001977649517357f, 0.044426776468754f, 0.002011870965362f, 0.044808741658926f, + 0.002046385314316f, 0.045190680772066f, 0.002081192564219f, 0.045572593808174f, + 0.002116292715073f, 0.045954477041960f, 0.002151685766876f, 0.046336337924004f, + 0.002187371719629f, 0.046718169003725f, 0.002223350573331f, 0.047099970281124f, + 0.002259622327983f, 0.047481749206781f, 0.002296186750755f, 0.047863494604826f, + 0.002333043841645f, 0.048245213925838f, 0.002370193833485f, 0.048626907169819f, + 0.002407636726275f, 0.049008570611477f, 0.002445372054353f, 0.049390204250813f, + 0.002483400283381f, 0.049771808087826f, 0.002521721180528f, 0.050153385847807f, + 0.002560334512964f, 0.050534930080175f, 0.002599240746349f, 0.050916448235512f, + 0.002638439415023f, 0.051297932863235f, 0.002677930751815f, 0.051679391413927f, + 0.002717714523897f, 0.052060816437006f, 0.002757790964097f, 0.052442211657763f, + 0.002798160072416f, 0.052823577076197f, 0.002838821383193f, 0.053204908967018f, + 0.002879775362089f, 0.053586211055517f, 0.002921021543443f, 0.053967483341694f, + 0.002962560392916f, 0.054348722100258f, 0.003004391444847f, 0.054729927331209f, + 0.003046514932066f, 0.055111102759838f, 0.003088930854574f, 0.055492244660854f, + 0.003131638979539f, 0.055873356759548f, 0.003174639539793f, 0.056254431605339f, + 0.003217932302505f, 0.056635476648808f, 0.003261517267674f, 0.057016488164663f, + 0.003305394435301f, 0.057397462427616f, 0.003349563805386f, 0.057778406888247f, + 0.003394025377929f, 0.058159314095974f, 0.003438779152930f, 0.058540191501379f, + 0.003483824897557f, 0.058921031653881f, 0.003529162844643f, 0.059301838278770f, + 0.003574792761356f, 0.059682607650757f, 0.003620714880526f, 0.060063343495131f, + 0.003666928736493f, 0.060444042086601f, 0.003713434794918f, 0.060824707150459f, + 0.003760232590139f, 0.061205338686705f, 0.003807322587818f, 0.061585929244757f, + 0.003854704322293f, 0.061966486275196f, 0.003902378026396f, 0.062347009778023f, + 0.003950343467295f, 0.062727488577366f, 0.003998600877821f, 0.063107937574387f, + 0.004047149792314f, 0.063488349318504f, 0.004095990676433f, 0.063868723809719f, + 0.004145123064518f, 0.064249053597450f, 0.004194547422230f, 0.064629353582859f, + 0.004244263283908f, 0.065009608864784f, 0.004294271115214f, 0.065389834344387f, + 0.004344569984823f, 0.065770015120506f, 0.004395160824060f, 0.066150158643723f, + 0.004446043167263f, 0.066530264914036f, 0.004497217014432f, 0.066910326480865f, + 0.004548682365566f, 0.067290350794792f, 0.004600439220667f, 0.067670337855816f, + 0.004652487114072f, 0.068050287663937f, 0.004704826977104f, 0.068430192768574f, + 0.004757457878441f, 0.068810060620308f, 0.004810380283743f, 0.069189883768559f, + 0.004863593727350f, 0.069569669663906f, 0.004917098674923f, 0.069949418306351f, + 0.004970894660801f, 0.070329122245312f, 0.005024982150644f, 0.070708781480789f, + 0.005079360678792f, 0.071088403463364f, 0.005134030245245f, 0.071467980742455f, + 0.005188991315663f, 0.071847513318062f, 0.005244242958724f, 0.072227008640766f, + 0.005299786105752f, 0.072606459259987f, 0.005355620291084f, 0.072985872626305f, + 0.005411745049059f, 0.073365233838558f, 0.005468160845339f, 0.073744557797909f, + 0.005524867679924f, 0.074123837053776f, 0.005581865552813f, 0.074503071606159f, + 0.005639153998345f, 0.074882268905640f, 0.005696733482182f, 0.075261414051056f, + 0.005754603538662f, 0.075640521943569f, 0.005812764633447f, 0.076019577682018f, + 0.005871216300875f, 0.076398596167564f, 0.005929958540946f, 0.076777562499046f, + 0.005988991353661f, 0.077156484127045f, 0.006048315204680f, 0.077535368502140f, + 0.006107929162681f, 0.077914200723171f, 0.006167833693326f, 0.078292988240719f, + 0.006228029262275f, 0.078671731054783f, 0.006288514938205f, 0.079050421714783f, + 0.006349290721118f, 0.079429075121880f, 0.006410357542336f, 0.079807676374912f, + 0.006471714470536f, 0.080186225473881f, 0.006533361505717f, 0.080564737319946f, + 0.006595299113542f, 0.080943197011948f, 0.006657526828349f, 0.081321612000465f, + 0.006720044650137f, 0.081699974834919f, 0.006782853044569f, 0.082078292965889f, + 0.006845951545984f, 0.082456558942795f, 0.006909339688718f, 0.082834780216217f, + 0.006973018404096f, 0.083212949335575f, 0.007036986760795f, 0.083591073751450f, + 0.007101245224476f, 0.083969146013260f, 0.007165793795139f, 0.084347173571587f, + 0.007230632472783f, 0.084725148975849f, 0.007295760791749f, 0.085103072226048f, + 0.007361178752035f, 0.085480943322182f, 0.007426886819303f, 0.085858769714832f, + 0.007492884527892f, 0.086236543953419f, 0.007559171877801f, 0.086614266037941f, + 0.007625748869032f, 0.086991935968399f, 0.007692615967244f, 0.087369553744793f, + 0.007759772241116f, 0.087747126817703f, 0.007827218621969f, 0.088124647736549f, + 0.007894953712821f, 0.088502109050751f, 0.007962978444993f, 0.088879525661469f, + 0.008031292818487f, 0.089256882667542f, 0.008099896833301f, 0.089634194970131f, + 0.008168790489435f, 0.090011447668076f, 0.008237972855568f, 0.090388655662537f, + 0.008307444863021f, 0.090765804052353f, 0.008377205580473f, 0.091142900288105f, + 0.008447255939245f, 0.091519944369793f, 0.008517595939338f, 0.091896936297417f, + 0.008588224649429f, 0.092273868620396f, 0.008659142069519f, 0.092650748789310f, + 0.008730349130929f, 0.093027576804161f, 0.008801844902337f, 0.093404345214367f, + 0.008873629383743f, 0.093781061470509f, 0.008945702575147f, 0.094157725572586f, + 0.009018065407872f, 0.094534330070019f, 0.009090716950595f, 0.094910882413387f, + 0.009163657203317f, 0.095287375152111f, 0.009236886166036f, 0.095663815736771f, + 0.009310402907431f, 0.096040196716785f, 0.009384209290147f, 0.096416525542736f, + 0.009458304382861f, 0.096792794764042f, 0.009532688185573f, 0.097169004380703f, + 0.009607359766960f, 0.097545161843300f, 0.009682320058346f, 0.097921259701252f, + 0.009757569059730f, 0.098297297954559f, 0.009833106771111f, 0.098673284053802f, + 0.009908932261169f, 0.099049203097820f, 0.009985045529902f, 0.099425069987774f, + 0.010061448439956f, 0.099800877273083f, 0.010138138197362f, 0.100176624953747f, + 0.010215117596090f, 0.100552320480347f, 0.010292383842170f, 0.100927948951721f, + 0.010369938798249f, 0.101303517818451f, 0.010447781533003f, 0.101679034531116f, + 0.010525912046432f, 0.102054484188557f, 0.010604331269860f, 0.102429874241352f, + 0.010683037340641f, 0.102805204689503f, 0.010762032121420f, 0.103180475533009f, + 0.010841314680874f, 0.103555686771870f, 0.010920885019004f, 0.103930838406086f, + 0.011000742204487f, 0.104305922985077f, 0.011080888099968f, 0.104680955410004f, + 0.011161320842803f, 0.105055920779705f, 0.011242041364312f, 0.105430819094181f, + 0.011323049664497f, 0.105805665254593f, 0.011404345743358f, 0.106180444359779f, + 0.011485928669572f, 0.106555156409740f, 0.011567799374461f, 0.106929816305637f, + 0.011649956926703f, 0.107304409146309f, 0.011732402257621f, 0.107678934931755f, + 0.011815134435892f, 0.108053401112556f, 0.011898153461516f, 0.108427800238132f, + 0.011981460265815f, 0.108802139759064f, 0.012065053917468f, 0.109176412224770f, + 0.012148935347795f, 0.109550617635250f, 0.012233102694154f, 0.109924763441086f, + 0.012317557819188f, 0.110298842191696f, 0.012402298860252f, 0.110672861337662f, + 0.012487327679992f, 0.111046813428402f, 0.012572642415762f, 0.111420698463917f, + 0.012658244930208f, 0.111794516444206f, 0.012744133360684f, 0.112168267369270f, + 0.012830308638513f, 0.112541958689690f, 0.012916770763695f, 0.112915575504303f, + 0.013003518804908f, 0.113289132714272f, 0.013090553693473f, 0.113662622869015f, + 0.013177875429392f, 0.114036038517952f, 0.013265483081341f, 0.114409394562244f, + 0.013353376649320f, 0.114782683551311f, 0.013441557064652f, 0.115155905485153f, + 0.013530024327338f, 0.115529052913189f, 0.013618776574731f, 0.115902140736580f, + 0.013707815669477f, 0.116275154054165f, 0.013797140680254f, 0.116648100316525f, + 0.013886751607060f, 0.117020979523659f, 0.013976648449898f, 0.117393791675568f, + 0.014066831208766f, 0.117766529321671f, 0.014157299883664f, 0.118139199912548f, + 0.014248054474592f, 0.118511803448200f, 0.014339094981551f, 0.118884332478046f, + 0.014430420473218f, 0.119256794452667f, 0.014522032812238f, 0.119629189372063f, + 0.014613929204643f, 0.120001509785652f, 0.014706112444401f, 0.120373763144016f, + 0.014798580668867f, 0.120745941996574f, 0.014891333878040f, 0.121118053793907f, + 0.014984373003244f, 0.121490091085434f, 0.015077698044479f, 0.121862053871155f, + 0.015171307139099f, 0.122233949601650f, 0.015265202149749f, 0.122605770826340f, + 0.015359382145107f, 0.122977524995804f, 0.015453847125173f, 0.123349204659462f, + 0.015548598021269f, 0.123720809817314f, 0.015643632039428f, 0.124092340469360f, + 0.015738952904940f, 0.124463804066181f, 0.015834558755159f, 0.124835193157196f, + 0.015930447727442f, 0.125206500291824f, 0.016026621684432f, 0.125577747821808f, + 0.016123080626130f, 0.125948905944824f, 0.016219824552536f, 0.126320004463196f, + 0.016316853463650f, 0.126691013574600f, 0.016414167359471f, 0.127061963081360f, + 0.016511764377356f, 0.127432823181152f, 0.016609646379948f, 0.127803623676300f, + 0.016707813367248f, 0.128174334764481f, 0.016806263476610f, 0.128544986248016f, + 0.016904998570681f, 0.128915548324585f, 0.017004016786814f, 0.129286035895348f, + 0.017103319987655f, 0.129656463861465f, 0.017202908173203f, 0.130026802420616f, + 0.017302779480815f, 0.130397051572800f, 0.017402933910489f, 0.130767241120338f, + 0.017503373324871f, 0.131137356162071f, 0.017604095861316f, 0.131507381796837f, + 0.017705103382468f, 0.131877332925797f, 0.017806394025683f, 0.132247209548950f, + 0.017907967790961f, 0.132617011666298f, 0.018009826540947f, 0.132986739277840f, + 0.018111966550350f, 0.133356377482414f, 0.018214391544461f, 0.133725941181183f, + 0.018317099660635f, 0.134095430374146f, 0.018420090898871f, 0.134464830160141f, + 0.018523367121816f, 0.134834155440331f, 0.018626924604177f, 0.135203406214714f, + 0.018730765208602f, 0.135572582483292f, 0.018834890797734f, 0.135941669344902f, + 0.018939297646284f, 0.136310681700706f, 0.019043987616897f, 0.136679604649544f, + 0.019148962572217f, 0.137048453092575f, 0.019254218786955f, 0.137417227029800f, + 0.019359756261110f, 0.137785911560059f, 0.019465578719974f, 0.138154521584511f, + 0.019571684300900f, 0.138523042201996f, 0.019678071141243f, 0.138891488313675f, + 0.019784741103649f, 0.139259845018387f, 0.019891692325473f, 0.139628127217293f, + 0.019998926669359f, 0.139996320009232f, 0.020106444135308f, 0.140364438295364f, + 0.020214242860675f, 0.140732467174530f, 0.020322324708104f, 0.141100421547890f, + 0.020430689677596f, 0.141468286514282f, 0.020539334043860f, 0.141836062073708f, + 0.020648263394833f, 0.142203763127327f, 0.020757472142577f, 0.142571389675140f, + 0.020866964012384f, 0.142938911914825f, 0.020976737141609f, 0.143306359648705f, + 0.021086793392897f, 0.143673732876778f, 0.021197130903602f, 0.144041016697884f, + 0.021307749673724f, 0.144408211112022f, 0.021418649703264f, 0.144775316119194f, + 0.021529832854867f, 0.145142331719399f, 0.021641295403242f, 0.145509272813797f, + 0.021753041073680f, 0.145876124501228f, 0.021865066140890f, 0.146242901682854f, + 0.021977374330163f, 0.146609574556351f, 0.022089963778853f, 0.146976172924042f, + 0.022202832624316f, 0.147342681884766f, 0.022315984591842f, 0.147709101438522f, + 0.022429415956140f, 0.148075446486473f, 0.022543128579855f, 0.148441687226295f, + 0.022657122462988f, 0.148807853460312f, 0.022771397605538f, 0.149173930287361f, + 0.022885952144861f, 0.149539917707443f, 0.023000787943602f, 0.149905815720558f, + 0.023115905001760f, 0.150271624326706f, 0.023231301456690f, 0.150637343525887f, + 0.023346979171038f, 0.151002973318100f, 0.023462938144803f, 0.151368513703346f, + 0.023579176515341f, 0.151733979582787f, 0.023695694282651f, 0.152099341154099f, + 0.023812493309379f, 0.152464613318443f, 0.023929571732879f, 0.152829796075821f, + 0.024046931415796f, 0.153194904327393f, 0.024164570495486f, 0.153559908270836f, + 0.024282488971949f, 0.153924822807312f, 0.024400688707829f, 0.154289647936821f, + 0.024519165977836f, 0.154654383659363f, 0.024637924507260f, 0.155019029974937f, + 0.024756962433457f, 0.155383571982384f, 0.024876279756427f, 0.155748039484024f, + 0.024995878338814f, 0.156112402677536f, 0.025115754455328f, 0.156476691365242f, + 0.025235909968615f, 0.156840875744820f, 0.025356344878674f, 0.157204970717430f, + 0.025477059185505f, 0.157568961381912f, 0.025598052889109f, 0.157932877540588f, + 0.025719324126840f, 0.158296689391136f, 0.025840876623988f, 0.158660411834717f, + 0.025962706655264f, 0.159024044871330f, 0.026084816083312f, 0.159387573599815f, + 0.026207204908133f, 0.159751012921333f, 0.026329871267080f, 0.160114362835884f, + 0.026452817022800f, 0.160477623343468f, 0.026576040312648f, 0.160840779542923f, + 0.026699542999268f, 0.161203846335411f, 0.026823325082660f, 0.161566808819771f, + 0.026947384700179f, 0.161929681897163f, 0.027071721851826f, 0.162292465567589f, + 0.027196336537600f, 0.162655144929886f, 0.027321230620146f, 0.163017734885216f, + 0.027446404099464f, 0.163380220532417f, 0.027571853250265f, 0.163742616772652f, + 0.027697581797838f, 0.164104923605919f, 0.027823587879539f, 0.164467126131058f, + 0.027949871495366f, 0.164829224348068f, 0.028076432645321f, 0.165191248059273f, + 0.028203271329403f, 0.165553152561188f, 0.028330387547612f, 0.165914967656136f, + 0.028457781299949f, 0.166276678442955f, 0.028585452586412f, 0.166638299822807f, + 0.028713401407003f, 0.166999831795692f, 0.028841627761722f, 0.167361244559288f, + 0.028970129787922f, 0.167722567915916f, 0.029098909348249f, 0.168083801865578f, + 0.029227968305349f, 0.168444931507111f, 0.029357301071286f, 0.168805956840515f, + 0.029486913233995f, 0.169166877865791f, 0.029616801068187f, 0.169527709484100f, + 0.029746964573860f, 0.169888436794281f, 0.029877405613661f, 0.170249074697495f, + 0.030008124187589f, 0.170609608292580f, 0.030139118432999f, 0.170970037579536f, + 0.030270388349891f, 0.171330362558365f, 0.030401935800910f, 0.171690583229065f, + 0.030533758923411f, 0.172050714492798f, 0.030665857717395f, 0.172410741448402f, + 0.030798232182860f, 0.172770664095879f, 0.030930884182453f, 0.173130482435226f, + 0.031063811853528f, 0.173490211367607f, 0.031197015196085f, 0.173849821090698f, + 0.031330492347479f, 0.174209341406822f, 0.031464248895645f, 0.174568757414818f, + 0.031598277390003f, 0.174928069114685f, 0.031732585281134f, 0.175287276506424f, + 0.031867165118456f, 0.175646379590034f, 0.032002024352551f, 0.176005378365517f, + 0.032137155532837f, 0.176364272832870f, 0.032272562384605f, 0.176723077893257f, + 0.032408244907856f, 0.177081763744354f, 0.032544203102589f, 0.177440345287323f, + 0.032680433243513f, 0.177798837423325f, 0.032816942781210f, 0.178157210350037f, + 0.032953724265099f, 0.178515478968620f, 0.033090781420469f, 0.178873643279076f, + 0.033228114247322f, 0.179231703281403f, 0.033365719020367f, 0.179589673876762f, + 0.033503599464893f, 0.179947525262833f, 0.033641755580902f, 0.180305257439613f, + 0.033780183643103f, 0.180662900209427f, 0.033918887376785f, 0.181020438671112f, + 0.034057866781950f, 0.181377857923508f, 0.034197118133307f, 0.181735187768936f, + 0.034336645156145f, 0.182092398405075f, 0.034476444125175f, 0.182449504733086f, + 0.034616518765688f, 0.182806491851807f, 0.034756865352392f, 0.183163389563560f, + 0.034897487610579f, 0.183520168066025f, 0.035038381814957f, 0.183876842260361f, + 0.035179551690817f, 0.184233412146568f, 0.035320993512869f, 0.184589877724648f, + 0.035462711006403f, 0.184946224093437f, 0.035604696720839f, 0.185302466154099f, + 0.035746958106756f, 0.185658603906631f, 0.035889495164156f, 0.186014622449875f, + 0.036032304167747f, 0.186370536684990f, 0.036175385117531f, 0.186726331710815f, + 0.036318738013506f, 0.187082037329674f, 0.036462362855673f, 0.187437608838081f, + 0.036606263369322f, 0.187793090939522f, 0.036750435829163f, 0.188148453831673f, + 0.036894880235195f, 0.188503712415695f, 0.037039596587420f, 0.188858851790428f, + 0.037184584885836f, 0.189213871955872f, 0.037329845130444f, 0.189568802714348f, + 0.037475381046534f, 0.189923599362373f, 0.037621185183525f, 0.190278306603432f, + 0.037767261266708f, 0.190632879734039f, 0.037913613021374f, 0.190987363457680f, + 0.038060232996941f, 0.191341713070869f, 0.038207128643990f, 0.191695958375931f, + 0.038354292511940f, 0.192050099372864f, 0.038501728326082f, 0.192404121160507f, + 0.038649436086416f, 0.192758023738861f, 0.038797415792942f, 0.193111822009087f, + 0.038945667445660f, 0.193465501070023f, 0.039094187319279f, 0.193819075822830f, + 0.039242979139090f, 0.194172516465187f, 0.039392042905092f, 0.194525867700577f, + 0.039541378617287f, 0.194879084825516f, 0.039690986275673f, 0.195232197642326f, + 0.039840862154961f, 0.195585191249847f, 0.039991009980440f, 0.195938065648079f, + 0.040141426026821f, 0.196290835738182f, 0.040292114019394f, 0.196643486618996f, + 0.040443073958158f, 0.196996018290520f, 0.040594302117825f, 0.197348430752754f, + 0.040745802223682f, 0.197700738906860f, 0.040897574275732f, 0.198052927851677f, + 0.041049610823393f, 0.198404997587204f, 0.041201923042536f, 0.198756948113441f, + 0.041354499757290f, 0.199108779430389f, 0.041507352143526f, 0.199460506439209f, + 0.041660469025373f, 0.199812099337578f, 0.041813857853413f, 0.200163587927818f, + 0.041967518627644f, 0.200514942407608f, 0.042121443897486f, 0.200866192579269f, + 0.042275641113520f, 0.201217323541641f, 0.042430106550455f, 0.201568335294724f, + 0.042584843933582f, 0.201919227838516f, 0.042739849537611f, 0.202270001173019f, + 0.042895123362541f, 0.202620655298233f, 0.043050665408373f, 0.202971190214157f, + 0.043206475675106f, 0.203321605920792f, 0.043362557888031f, 0.203671902418137f, + 0.043518904596567f, 0.204022079706192f, 0.043675523251295f, 0.204372137784958f, + 0.043832406401634f, 0.204722076654434f, 0.043989561498165f, 0.205071896314621f, + 0.044146984815598f, 0.205421581864357f, 0.044304672628641f, 0.205771163105965f, + 0.044462632387877f, 0.206120610237122f, 0.044620860368013f, 0.206469938158989f, + 0.044779352843761f, 0.206819161772728f, 0.044938117265701f, 0.207168251276016f, + 0.045097146183252f, 0.207517206668854f, 0.045256443321705f, 0.207866057753563f, + 0.045416008681059f, 0.208214774727821f, 0.045575842261314f, 0.208563387393951f, + 0.045735940337181f, 0.208911851048470f, 0.045896306633949f, 0.209260210394859f, + 0.046056941151619f, 0.209608450531960f, 0.046217843890190f, 0.209956556558609f, + 0.046379011124372f, 0.210304543375969f, 0.046540446579456f, 0.210652396082878f, + 0.046702146530151f, 0.211000129580498f, 0.046864114701748f, 0.211347743868828f, + 0.047026351094246f, 0.211695238947868f, 0.047188851982355f, 0.212042599916458f, + 0.047351621091366f, 0.212389841675758f, 0.047514654695988f, 0.212736949324608f, + 0.047677956521511f, 0.213083937764168f, 0.047841522842646f, 0.213430806994438f, + 0.048005353659391f, 0.213777542114258f, 0.048169452697039f, 0.214124158024788f, + 0.048333816230297f, 0.214470639824867f, 0.048498444259167f, 0.214817002415657f, + 0.048663340508938f, 0.215163245797157f, 0.048828501254320f, 0.215509355068207f, + 0.048993926495314f, 0.215855330228806f, 0.049159619957209f, 0.216201186180115f, + 0.049325577914715f, 0.216546908020973f, 0.049491796642542f, 0.216892510652542f, + 0.049658283591270f, 0.217237979173660f, 0.049825038760900f, 0.217583328485489f, + 0.049992054700851f, 0.217928543686867f, 0.050159335136414f, 0.218273624777794f, + 0.050326880067587f, 0.218618586659431f, 0.050494693219662f, 0.218963414430618f, + 0.050662767142057f, 0.219308122992516f, 0.050831105560064f, 0.219652697443962f, + 0.050999708473682f, 0.219997137784958f, 0.051168579608202f, 0.220341444015503f, + 0.051337707787752f, 0.220685631036758f, 0.051507104188204f, 0.221029683947563f, + 0.051676765084267f, 0.221373617649078f, 0.051846686750650f, 0.221717402338982f, + 0.052016876637936f, 0.222061067819595f, 0.052187327295542f, 0.222404599189758f, + 0.052358038723469f, 0.222748011350632f, 0.052529018372297f, 0.223091274499893f, + 0.052700258791447f, 0.223434418439865f, 0.052871759980917f, 0.223777428269386f, + 0.053043525665998f, 0.224120303988457f, 0.053215555846691f, 0.224463045597076f, + 0.053387850522995f, 0.224805667996407f, 0.053560405969620f, 0.225148141384125f, + 0.053733222186565f, 0.225490495562553f, 0.053906302899122f, 0.225832715630531f, + 0.054079644382000f, 0.226174786686897f, 0.054253250360489f, 0.226516738533974f, + 0.054427117109299f, 0.226858556270599f, 0.054601248353720f, 0.227200239896774f, + 0.054775636643171f, 0.227541789412498f, 0.054950293153524f, 0.227883204817772f, + 0.055125206708908f, 0.228224486112595f, 0.055300384759903f, 0.228565633296967f, + 0.055475823581219f, 0.228906646370888f, 0.055651523172855f, 0.229247525334358f, + 0.055827483534813f, 0.229588270187378f, 0.056003704667091f, 0.229928880929947f, + 0.056180190294981f, 0.230269357562065f, 0.056356932967901f, 0.230609700083733f, + 0.056533940136433f, 0.230949893593788f, 0.056711208075285f, 0.231289967894554f, + 0.056888736784458f, 0.231629893183708f, 0.057066522538662f, 0.231969684362412f, + 0.057244572788477f, 0.232309341430664f, 0.057422880083323f, 0.232648864388466f, + 0.057601451873779f, 0.232988253235817f, 0.057780280709267f, 0.233327493071556f, + 0.057959370315075f, 0.233666598796844f, 0.058138720691204f, 0.234005570411682f, + 0.058318331837654f, 0.234344407916069f, 0.058498200029135f, 0.234683111310005f, + 0.058678328990936f, 0.235021665692329f, 0.058858718723059f, 0.235360085964203f, + 0.059039369225502f, 0.235698372125626f, 0.059220276772976f, 0.236036509275436f, + 0.059401445090771f, 0.236374512314796f, 0.059582870453596f, 0.236712381243706f, + 0.059764556586742f, 0.237050101161003f, 0.059946499764919f, 0.237387686967850f, + 0.060128703713417f, 0.237725138664246f, 0.060311164706945f, 0.238062441349030f, + 0.060493886470795f, 0.238399609923363f, 0.060676865279675f, 0.238736644387245f, + 0.060860104858875f, 0.239073529839516f, 0.061043601483107f, 0.239410281181335f, + 0.061227355152369f, 0.239746883511543f, 0.061411365866661f, 0.240083336830139f, + 0.061595637351274f, 0.240419670939446f, 0.061780165880919f, 0.240755841135979f, + 0.061964951455593f, 0.241091892123222f, 0.062149997800589f, 0.241427779197693f, + 0.062335297465324f, 0.241763532161713f, 0.062520854175091f, 0.242099151015282f, + 0.062706671655178f, 0.242434620857239f, 0.062892749905586f, 0.242769956588745f, + 0.063079081475735f, 0.243105143308640f, 0.063265666365623f, 0.243440181016922f, + 0.063452512025833f, 0.243775084614754f, 0.063639611005783f, 0.244109839200974f, + 0.063826970756054f, 0.244444444775581f, 0.064014583826065f, 0.244778916239738f, + 0.064202457666397f, 0.245113238692284f, 0.064390584826469f, 0.245447427034378f, + 0.064578965306282f, 0.245781451463699f, 0.064767606556416f, 0.246115356683731f, + 0.064956501126289f, 0.246449097990990f, 0.065145656466484f, 0.246782705187798f, + 0.065335065126419f, 0.247116148471832f, 0.065524727106094f, 0.247449472546577f, + 0.065714649856091f, 0.247782632708550f, 0.065904818475246f, 0.248115643858910f, + 0.066095255315304f, 0.248448520898819f, 0.066285938024521f, 0.248781248927116f, + 0.066476874053478f, 0.249113827943802f, 0.066668070852757f, 0.249446272850037f, + 0.066859520971775f, 0.249778553843498f, 0.067051224410534f, 0.250110685825348f, + 0.067243188619614f, 0.250442683696747f, 0.067435398697853f, 0.250774532556534f, + 0.067627869546413f, 0.251106232404709f, 0.067820593714714f, 0.251437783241272f, + 0.068013571202755f, 0.251769185066223f, 0.068206802010536f, 0.252100437879562f, + 0.068400286138058f, 0.252431541681290f, 0.068594031035900f, 0.252762526273727f, + 0.068788021802902f, 0.253093332052231f, 0.068982265889645f, 0.253423988819122f, + 0.069176770746708f, 0.253754496574402f, 0.069371521472931f, 0.254084855318069f, + 0.069566532969475f, 0.254415065050125f, 0.069761790335178f, 0.254745125770569f, + 0.069957308471203f, 0.255075037479401f, 0.070153072476387f, 0.255404800176620f, + 0.070349089801311f, 0.255734413862228f, 0.070545360445976f, 0.256063878536224f, + 0.070741884410381f, 0.256393194198608f, 0.070938661694527f, 0.256722360849380f, + 0.071135692298412f, 0.257051378488541f, 0.071332976222038f, 0.257380217313766f, + 0.071530513465405f, 0.257708936929703f, 0.071728296577930f, 0.258037507534027f, + 0.071926333010197f, 0.258365899324417f, 0.072124622762203f, 0.258694142103195f, + 0.072323165833950f, 0.259022265672684f, 0.072521962225437f, 0.259350210428238f, + 0.072721004486084f, 0.259678006172180f, 0.072920300066471f, 0.260005623102188f, + 0.073119848966599f, 0.260333120822906f, 0.073319651186466f, 0.260660469532013f, + 0.073519699275494f, 0.260987639427185f, 0.073720000684261f, 0.261314690113068f, + 0.073920547962189f, 0.261641561985016f, 0.074121348559856f, 0.261968284845352f, + 0.074322402477264f, 0.262294828891754f, 0.074523709714413f, 0.262621253728867f, + 0.074725262820721f, 0.262947499752045f, 0.074927061796188f, 0.263273626565933f, + 0.075129114091396f, 0.263599574565887f, 0.075331419706345f, 0.263925373554230f, + 0.075533971190453f, 0.264250993728638f, 0.075736775994301f, 0.264576494693756f, + 0.075939826667309f, 0.264901816844940f, 0.076143130660057f, 0.265226989984512f, + 0.076346680521965f, 0.265552014112473f, 0.076550483703613f, 0.265876859426498f, + 0.076754532754421f, 0.266201555728912f, 0.076958827674389f, 0.266526103019714f, + 0.077163375914097f, 0.266850501298904f, 0.077368170022964f, 0.267174720764160f, + 0.077573217451572f, 0.267498821020126f, 0.077778510749340f, 0.267822742462158f, + 0.077984049916267f, 0.268146485090256f, 0.078189842402935f, 0.268470078706741f, + 0.078395880758762f, 0.268793523311615f, 0.078602164983749f, 0.269116818904877f, + 0.078808702528477f, 0.269439965486526f, 0.079015478491783f, 0.269762933254242f, + 0.079222507774830f, 0.270085722208023f, 0.079429790377617f, 0.270408391952515f, + 0.079637311398983f, 0.270730882883072f, 0.079845085740089f, 0.271053224802017f, + 0.080053105950356f, 0.271375387907028f, 0.080261372029781f, 0.271697402000427f, + 0.080469883978367f, 0.272019267082214f, 0.080678641796112f, 0.272340953350067f, + 0.080887645483017f, 0.272662490606308f, 0.081096902489662f, 0.272983878850937f, + 0.081306397914886f, 0.273305088281631f, 0.081516146659851f, 0.273626148700714f, + 0.081726133823395f, 0.273947030305862f, 0.081936374306679f, 0.274267762899399f, + 0.082146860659122f, 0.274588316679001f, 0.082357585430145f, 0.274908751249313f, + 0.082568563520908f, 0.275228977203369f, 0.082779780030251f, 0.275549083948135f, + 0.082991249859333f, 0.275868982076645f, 0.083202958106995f, 0.276188760995865f, + 0.083414919674397f, 0.276508361101151f, 0.083627119660378f, 0.276827782392502f, + 0.083839565515518f, 0.277147054672241f, 0.084052257239819f, 0.277466177940369f, + 0.084265194833279f, 0.277785122394562f, 0.084478378295898f, 0.278103888034821f, + 0.084691800177097f, 0.278422504663467f, 0.084905467927456f, 0.278740972280502f, + 0.085119381546974f, 0.279059261083603f, 0.085333541035652f, 0.279377400875092f, + 0.085547938942909f, 0.279695361852646f, 0.085762590169907f, 0.280013144016266f, + 0.085977479815483f, 0.280330777168274f, 0.086192607879639f, 0.280648261308670f, + 0.086407989263535f, 0.280965566635132f, 0.086623609066010f, 0.281282693147659f, + 0.086839467287064f, 0.281599670648575f, 0.087055571377277f, 0.281916469335556f, + 0.087271921336651f, 0.282233119010925f, 0.087488517165184f, 0.282549589872360f, + 0.087705351412296f, 0.282865911722183f, 0.087922424077988f, 0.283182054758072f, + 0.088139742612839f, 0.283498018980026f, 0.088357307016850f, 0.283813834190369f, + 0.088575109839439f, 0.284129470586777f, 0.088793158531189f, 0.284444957971573f, + 0.089011445641518f, 0.284760266542435f, 0.089229971170425f, 0.285075396299362f, + 0.089448742568493f, 0.285390377044678f, 0.089667752385139f, 0.285705178976059f, + 0.089887008070946f, 0.286019802093506f, 0.090106502175331f, 0.286334276199341f, + 0.090326242148876f, 0.286648571491241f, 0.090546220541000f, 0.286962717771530f, + 0.090766437351704f, 0.287276685237885f, 0.090986892580986f, 0.287590473890305f, + 0.091207593679428f, 0.287904083728790f, 0.091428533196449f, 0.288217544555664f, + 0.091649711132050f, 0.288530826568604f, 0.091871134936810f, 0.288843959569931f, + 0.092092797160149f, 0.289156883955002f, 0.092314697802067f, 0.289469659328461f, + 0.092536836862564f, 0.289782285690308f, 0.092759214341640f, 0.290094703435898f, + 0.092981837689877f, 0.290406972169876f, 0.093204692006111f, 0.290719062089920f, + 0.093427792191505f, 0.291031002998352f, 0.093651130795479f, 0.291342735290527f, + 0.093874707818031f, 0.291654318571091f, 0.094098523259163f, 0.291965723037720f, + 0.094322577118874f, 0.292276978492737f, 0.094546869397163f, 0.292588025331497f, + 0.094771400094032f, 0.292898923158646f, 0.094996169209480f, 0.293209642171860f, + 0.095221176743507f, 0.293520182371140f, 0.095446422696114f, 0.293830573558807f, + 0.095671907067299f, 0.294140785932541f, 0.095897629857063f, 0.294450789690018f, + 0.096123591065407f, 0.294760644435883f, 0.096349790692329f, 0.295070350170136f, + 0.096576221287251f, 0.295379847288132f, 0.096802897751331f, 0.295689195394516f, + 0.097029805183411f, 0.295998334884644f, 0.097256951034069f, 0.296307325363159f, + 0.097484335303307f, 0.296616137027740f, 0.097711957991123f, 0.296924799680710f, + 0.097939811646938f, 0.297233253717422f, 0.098167903721333f, 0.297541528940201f, + 0.098396234214306f, 0.297849655151367f, 0.098624803125858f, 0.298157602548599f, + 0.098853603005409f, 0.298465341329575f, 0.099082641303539f, 0.298772931098938f, + 0.099311910569668f, 0.299080342054367f, 0.099541425704956f, 0.299387603998184f, + 0.099771171808243f, 0.299694657325745f, 0.100001148879528f, 0.300001531839371f, + 0.100231364369392f, 0.300308227539063f, 0.100461818277836f, 0.300614774227142f, + 0.100692503154278f, 0.300921112298965f, 0.100923426449299f, 0.301227301359177f, + 0.101154580712318f, 0.301533311605453f, 0.101385973393917f, 0.301839113235474f, + 0.101617597043514f, 0.302144765853882f, 0.101849451661110f, 0.302450239658356f, + 0.102081544697285f, 0.302755534648895f, 0.102313876152039f, 0.303060621023178f, + 0.102546438574791f, 0.303365558385849f, 0.102779231965542f, 0.303670316934586f, + 0.103012263774872f, 0.303974896669388f, 0.103245526552200f, 0.304279297590256f, + 0.103479020297527f, 0.304583519697189f, 0.103712752461433f, 0.304887533187866f, + 0.103946708142757f, 0.305191397666931f, 0.104180909693241f, 0.305495083332062f, + 0.104415334761143f, 0.305798590183258f, 0.104649998247623f, 0.306101888418198f, + 0.104884892702103f, 0.306405037641525f, 0.105120018124580f, 0.306708008050919f, + 0.105355374515057f, 0.307010769844055f, 0.105590961873531f, 0.307313382625580f, + 0.105826787650585f, 0.307615786790848f, 0.106062836945057f, 0.307918041944504f, + 0.106299124658108f, 0.308220088481903f, 0.106535643339157f, 0.308521956205368f, + 0.106772392988205f, 0.308823645114899f, 0.107009373605251f, 0.309125155210495f, + 0.107246585190296f, 0.309426486492157f, 0.107484027743340f, 0.309727638959885f, + 0.107721701264381f, 0.310028612613678f, 0.107959605753422f, 0.310329377651215f, + 0.108197741210461f, 0.310629993677139f, 0.108436107635498f, 0.310930401086807f, + 0.108674705028534f, 0.311230629682541f, 0.108913525938988f, 0.311530679464340f, + 0.109152585268021f, 0.311830550432205f, 0.109391868114471f, 0.312130242586136f, + 0.109631389379501f, 0.312429755926132f, 0.109871134161949f, 0.312729060649872f, + 0.110111102461815f, 0.313028186559677f, 0.110351309180260f, 0.313327133655548f, + 0.110591746866703f, 0.313625901937485f, 0.110832408070564f, 0.313924491405487f, + 0.111073300242424f, 0.314222872257233f, 0.111314415931702f, 0.314521104097366f, + 0.111555770039558f, 0.314819127321243f, 0.111797347664833f, 0.315116971731186f, + 0.112039148807526f, 0.315414607524872f, 0.112281180918217f, 0.315712094306946f, + 0.112523443996906f, 0.316009372472763f, 0.112765938043594f, 0.316306471824646f, + 0.113008655607700f, 0.316603392362595f, 0.113251596689224f, 0.316900104284287f, + 0.113494776189327f, 0.317196637392044f, 0.113738171756268f, 0.317492991685867f, + 0.113981798291206f, 0.317789167165756f, 0.114225655794144f, 0.318085134029388f, + 0.114469736814499f, 0.318380922079086f, 0.114714048802853f, 0.318676531314850f, + 0.114958584308624f, 0.318971961736679f, 0.115203343331814f, 0.319267183542252f, + 0.115448333323002f, 0.319562226533890f, 0.115693546831608f, 0.319857090711594f, + 0.115938983857632f, 0.320151746273041f, 0.116184651851654f, 0.320446223020554f, + 0.116430543363094f, 0.320740520954132f, 0.116676658391953f, 0.321034610271454f, + 0.116923004388809f, 0.321328520774841f, 0.117169573903084f, 0.321622252464294f, + 0.117416366934776f, 0.321915775537491f, 0.117663383483887f, 0.322209119796753f, + 0.117910631000996f, 0.322502255439758f, 0.118158094584942f, 0.322795242071152f, + 0.118405789136887f, 0.323088020086288f, 0.118653707206249f, 0.323380589485168f, + 0.118901848793030f, 0.323672980070114f, 0.119150213897228f, 0.323965191841125f, + 0.119398809969425f, 0.324257194995880f, 0.119647622108459f, 0.324549019336700f, + 0.119896657764912f, 0.324840664863586f, 0.120145916938782f, 0.325132101774216f, + 0.120395407080650f, 0.325423330068588f, 0.120645113289356f, 0.325714409351349f, + 0.120895043015480f, 0.326005280017853f, 0.121145196259022f, 0.326295942068100f, + 0.121395580470562f, 0.326586425304413f, 0.121646173298359f, 0.326876699924469f, + 0.121896997094154f, 0.327166795730591f, 0.122148044407368f, 0.327456712722778f, + 0.122399315237999f, 0.327746421098709f, 0.122650802135468f, 0.328035950660706f, + 0.122902512550354f, 0.328325271606445f, 0.123154446482658f, 0.328614413738251f, + 0.123406603932381f, 0.328903347253799f, 0.123658977448940f, 0.329192101955414f, + 0.123911574482918f, 0.329480648040771f, 0.124164395034313f, 0.329769015312195f, + 0.124417431652546f, 0.330057173967361f, 0.124670691788197f, 0.330345153808594f, + 0.124924175441265f, 0.330632925033569f, 0.125177875161171f, 0.330920487642288f, + 0.125431805849075f, 0.331207901239395f, 0.125685945153236f, 0.331495076417923f, + 0.125940307974815f, 0.331782072782516f, 0.126194894313812f, 0.332068890333176f, + 0.126449704170227f, 0.332355499267578f, 0.126704722642899f, 0.332641899585724f, + 0.126959964632988f, 0.332928121089935f, 0.127215430140495f, 0.333214133977890f, + 0.127471104264259f, 0.333499968051910f, 0.127727001905441f, 0.333785593509674f, + 0.127983123064041f, 0.334071010351181f, 0.128239467740059f, 0.334356248378754f, + 0.128496021032333f, 0.334641307592392f, 0.128752797842026f, 0.334926128387451f, + 0.129009798169136f, 0.335210770368576f, 0.129267007112503f, 0.335495233535767f, + 0.129524439573288f, 0.335779488086700f, 0.129782080650330f, 0.336063534021378f, + 0.130039945244789f, 0.336347371339798f, 0.130298033356667f, 0.336631029844284f, + 0.130556344985962f, 0.336914509534836f, 0.130814850330353f, 0.337197750806808f, + 0.131073594093323f, 0.337480813264847f, 0.131332546472549f, 0.337763696908951f, + 0.131591722369194f, 0.338046342134476f, 0.131851106882095f, 0.338328808546066f, + 0.132110700011253f, 0.338611096143723f, 0.132370531558990f, 0.338893145322800f, + 0.132630556821823f, 0.339175015687943f, 0.132890805602074f, 0.339456677436829f, + 0.133151277899742f, 0.339738160371780f, 0.133411958813667f, 0.340019434690475f, + 0.133672863245010f, 0.340300500392914f, 0.133933976292610f, 0.340581357479095f, + 0.134195312857628f, 0.340862035751343f, 0.134456858038902f, 0.341142505407333f, + 0.134718611836433f, 0.341422766447067f, 0.134980589151382f, 0.341702848672867f, + 0.135242775082588f, 0.341982692480087f, 0.135505184531212f, 0.342262357473373f, + 0.135767802596092f, 0.342541843652725f, 0.136030644178391f, 0.342821091413498f, + 0.136293679475784f, 0.343100160360336f, 0.136556953191757f, 0.343379020690918f, + 0.136820420622826f, 0.343657672405243f, 0.137084111571312f, 0.343936115503311f, + 0.137348011136055f, 0.344214379787445f, 0.137612134218216f, 0.344492435455322f, + 0.137876465916634f, 0.344770282506943f, 0.138141006231308f, 0.345047920942307f, + 0.138405755162239f, 0.345325350761414f, 0.138670727610588f, 0.345602601766586f, + 0.138935908675194f, 0.345879614353180f, 0.139201298356056f, 0.346156448125839f, + 0.139466896653175f, 0.346433073282242f, 0.139732718467712f, 0.346709519624710f, + 0.139998748898506f, 0.346985727548599f, 0.140264987945557f, 0.347261756658554f, + 0.140531435608864f, 0.347537547349930f, 0.140798106789589f, 0.347813159227371f, + 0.141064971685410f, 0.348088562488556f, 0.141332060098648f, 0.348363757133484f, + 0.141599357128143f, 0.348638743162155f, 0.141866862773895f, 0.348913550376892f, + 0.142134591937065f, 0.349188119173050f, 0.142402514815331f, 0.349462509155273f, + 0.142670661211014f, 0.349736660718918f, 0.142939001321793f, 0.350010633468628f, + 0.143207564949989f, 0.350284397602081f, 0.143476337194443f, 0.350557953119278f, + 0.143745318055153f, 0.350831300020218f, 0.144014507532120f, 0.351104438304901f, + 0.144283905625343f, 0.351377367973328f, 0.144553512334824f, 0.351650089025497f, + 0.144823327660561f, 0.351922631263733f, 0.145093351602554f, 0.352194935083389f, + 0.145363584160805f, 0.352467030286789f, 0.145634025335312f, 0.352738946676254f, + 0.145904675126076f, 0.353010624647141f, 0.146175548434258f, 0.353282123804092f, + 0.146446615457535f, 0.353553384542465f, 0.146717891097069f, 0.353824466466904f, + 0.146989375352860f, 0.354095309972763f, 0.147261068224907f, 0.354365974664688f, + 0.147532954812050f, 0.354636400938034f, 0.147805064916611f, 0.354906648397446f, + 0.148077383637428f, 0.355176687240601f, 0.148349896073341f, 0.355446487665176f, + 0.148622632026672f, 0.355716109275818f, 0.148895561695099f, 0.355985492467880f, + 0.149168699979782f, 0.356254696846008f, 0.149442046880722f, 0.356523662805557f, + 0.149715602397919f, 0.356792420148849f, 0.149989366531372f, 0.357060998678207f, + 0.150263324379921f, 0.357329338788986f, 0.150537505745888f, 0.357597470283508f, + 0.150811880826950f, 0.357865422964096f, 0.151086464524269f, 0.358133137226105f, + 0.151361241936684f, 0.358400642871857f, 0.151636242866516f, 0.358667939901352f, + 0.151911437511444f, 0.358935028314590f, 0.152186840772629f, 0.359201908111572f, + 0.152462437748909f, 0.359468549489975f, 0.152738258242607f, 0.359735012054443f, + 0.153014272451401f, 0.360001266002655f, 0.153290495276451f, 0.360267281532288f, + 0.153566911816597f, 0.360533088445663f, 0.153843536973000f, 0.360798716545105f, + 0.154120370745659f, 0.361064106225967f, 0.154397398233414f, 0.361329287290573f, + 0.154674649238586f, 0.361594229936600f, 0.154952079057693f, 0.361858993768692f, + 0.155229732394218f, 0.362123548984528f, 0.155507579445839f, 0.362387865781784f, + 0.155785620212555f, 0.362651973962784f, 0.156063869595528f, 0.362915903329849f, + 0.156342327594757f, 0.363179564476013f, 0.156620979309082f, 0.363443046808243f, + 0.156899839639664f, 0.363706320524216f, 0.157178908586502f, 0.363969355821610f, + 0.157458171248436f, 0.364232182502747f, 0.157737627625465f, 0.364494800567627f, + 0.158017292618752f, 0.364757210016251f, 0.158297166228294f, 0.365019410848618f, + 0.158577233552933f, 0.365281373262405f, 0.158857494592667f, 0.365543156862259f, + 0.159137964248657f, 0.365804702043533f, 0.159418627619743f, 0.366066008806229f, + 0.159699499607086f, 0.366327136754990f, 0.159980565309525f, 0.366588026285172f, + 0.160261839628220f, 0.366848707199097f, 0.160543307662010f, 0.367109179496765f, + 0.160824984312058f, 0.367369443178177f, 0.161106839776039f, 0.367629468441010f, + 0.161388918757439f, 0.367889285087585f, 0.161671176552773f, 0.368148893117905f, + 0.161953642964363f, 0.368408292531967f, 0.162236317992210f, 0.368667453527451f, + 0.162519171833992f, 0.368926405906677f, 0.162802234292030f, 0.369185149669647f, + 0.163085505366325f, 0.369443655014038f, 0.163368955254555f, 0.369701951742172f, + 0.163652613759041f, 0.369960039854050f, 0.163936465978622f, 0.370217919349670f, + 0.164220526814461f, 0.370475560426712f, 0.164504766464233f, 0.370732992887497f, + 0.164789214730263f, 0.370990216732025f, 0.165073871612549f, 0.371247202157974f, + 0.165358707308769f, 0.371503978967667f, 0.165643751621246f, 0.371760547161102f, + 0.165928974747658f, 0.372016876935959f, 0.166214406490326f, 0.372272998094559f, + 0.166500031948090f, 0.372528880834579f, 0.166785866022110f, 0.372784584760666f, + 0.167071878910065f, 0.373040050268173f, 0.167358100414276f, 0.373295277357101f, + 0.167644515633583f, 0.373550295829773f, 0.167931124567986f, 0.373805105686188f, + 0.168217927217484f, 0.374059677124023f, 0.168504923582077f, 0.374314039945602f, + 0.168792113661766f, 0.374568194150925f, 0.169079497456551f, 0.374822109937668f, + 0.169367074966431f, 0.375075817108154f, 0.169654861092567f, 0.375329315662384f, + 0.169942826032639f, 0.375582575798035f, 0.170230999588966f, 0.375835597515106f, + 0.170519351959229f, 0.376088410615921f, 0.170807912945747f, 0.376341015100479f, + 0.171096652746201f, 0.376593410968781f, 0.171385586261749f, 0.376845568418503f, + 0.171674728393555f, 0.377097487449646f, 0.171964049339294f, 0.377349197864532f, + 0.172253578901291f, 0.377600699663162f, 0.172543287277222f, 0.377851963043213f, + 0.172833189368248f, 0.378102988004684f, 0.173123285174370f, 0.378353834152222f, + 0.173413574695587f, 0.378604412078857f, 0.173704057931900f, 0.378854811191559f, + 0.173994734883308f, 0.379104942083359f, 0.174285605549812f, 0.379354894161224f, + 0.174576655030251f, 0.379604607820511f, 0.174867913126946f, 0.379854083061218f, + 0.175159350037575f, 0.380103349685669f, 0.175450980663300f, 0.380352377891541f, + 0.175742805004120f, 0.380601197481155f, 0.176034808158875f, 0.380849778652191f, + 0.176327019929886f, 0.381098151206970f, 0.176619410514832f, 0.381346285343170f, + 0.176911994814873f, 0.381594210863113f, 0.177204772830009f, 0.381841897964478f, + 0.177497729659081f, 0.382089376449585f, 0.177790880203247f, 0.382336616516113f, + 0.178084224462509f, 0.382583618164063f, 0.178377762436867f, 0.382830440998077f, + 0.178671479225159f, 0.383076995611191f, 0.178965389728546f, 0.383323341608047f, + 0.179259493947029f, 0.383569449186325f, 0.179553776979446f, 0.383815348148346f, + 0.179848253726959f, 0.384061008691788f, 0.180142924189568f, 0.384306460618973f, + 0.180437773466110f, 0.384551674127579f, 0.180732816457748f, 0.384796649217606f, + 0.181028053164482f, 0.385041415691376f, 0.181323468685150f, 0.385285943746567f, + 0.181619063019753f, 0.385530263185501f, 0.181914865970612f, 0.385774344205856f, + 0.182210832834244f, 0.386018186807632f, 0.182507008314133f, 0.386261820793152f, + 0.182803362607956f, 0.386505216360092f, 0.183099895715714f, 0.386748403310776f, + 0.183396622538567f, 0.386991351842880f, 0.183693528175354f, 0.387234061956406f, + 0.183990627527237f, 0.387476563453674f, 0.184287920594215f, 0.387718826532364f, + 0.184585392475128f, 0.387960851192474f, 0.184883043169975f, 0.388202667236328f, + 0.185180887579918f, 0.388444244861603f, 0.185478910803795f, 0.388685584068298f, + 0.185777112841606f, 0.388926714658737f, 0.186075508594513f, 0.389167606830597f, + 0.186374098062515f, 0.389408260583878f, 0.186672851443291f, 0.389648675918579f, + 0.186971798539162f, 0.389888882637024f, 0.187270939350128f, 0.390128880739212f, + 0.187570258975029f, 0.390368610620499f, 0.187869757413864f, 0.390608131885529f, + 0.188169434666634f, 0.390847414731979f, 0.188469305634499f, 0.391086459159851f, + 0.188769355416298f, 0.391325294971466f, 0.189069598913193f, 0.391563892364502f, + 0.189370006322861f, 0.391802251338959f, 0.189670607447624f, 0.392040401697159f, + 0.189971387386322f, 0.392278283834457f, 0.190272361040115f, 0.392515957355499f, + 0.190573498606682f, 0.392753422260284f, 0.190874829888344f, 0.392990618944168f, + 0.191176339983940f, 0.393227607011795f, 0.191478043794632f, 0.393464356660843f, + 0.191779911518097f, 0.393700867891312f, 0.192081972956657f, 0.393937170505524f, + 0.192384198307991f, 0.394173204898834f, 0.192686617374420f, 0.394409030675888f, + 0.192989215254784f, 0.394644618034363f, 0.193292006850243f, 0.394879996776581f, + 0.193594962358475f, 0.395115107297897f, 0.193898096680641f, 0.395350009202957f, + 0.194201424717903f, 0.395584672689438f, 0.194504916667938f, 0.395819097757339f, + 0.194808602333069f, 0.396053284406662f, 0.195112451910973f, 0.396287262439728f, + 0.195416495203972f, 0.396520972251892f, 0.195720717310905f, 0.396754473447800f, + 0.196025103330612f, 0.396987736225128f, 0.196329683065414f, 0.397220760583878f, + 0.196634441614151f, 0.397453576326370f, 0.196939364075661f, 0.397686123847961f, + 0.197244480252266f, 0.397918462753296f, 0.197549775242805f, 0.398150533437729f, + 0.197855234146118f, 0.398382395505905f, 0.198160871863365f, 0.398614019155502f, + 0.198466703295708f, 0.398845434188843f, 0.198772698640823f, 0.399076581001282f, + 0.199078872799873f, 0.399307489395142f, 0.199385225772858f, 0.399538189172745f, + 0.199691757559776f, 0.399768620729446f, 0.199998468160629f, 0.399998843669891f, + 0.200305357575417f, 0.400228828191757f, 0.200612410902977f, 0.400458574295044f, + 0.200919643044472f, 0.400688081979752f, 0.201227053999901f, 0.400917351245880f, + 0.201534643769264f, 0.401146411895752f, 0.201842412352562f, 0.401375204324722f, + 0.202150344848633f, 0.401603758335114f, 0.202458456158638f, 0.401832103729248f, + 0.202766746282578f, 0.402060180902481f, 0.203075215220451f, 0.402288049459457f, + 0.203383848071098f, 0.402515679597855f, 0.203692659735680f, 0.402743041515350f, + 0.204001650214195f, 0.402970194816589f, 0.204310819506645f, 0.403197109699249f, + 0.204620152711868f, 0.403423786163330f, 0.204929664731026f, 0.403650224208832f, + 0.205239340662956f, 0.403876423835754f, 0.205549195408821f, 0.404102355241776f, + 0.205859228968620f, 0.404328078031540f, 0.206169426441193f, 0.404553562402725f, + 0.206479802727699f, 0.404778808355331f, 0.206790357828140f, 0.405003815889359f, + 0.207101076841354f, 0.405228585004807f, 0.207411959767342f, 0.405453115701675f, + 0.207723021507263f, 0.405677437782288f, 0.208034262061119f, 0.405901491641998f, + 0.208345666527748f, 0.406125307083130f, 0.208657249808311f, 0.406348884105682f, + 0.208969011902809f, 0.406572192907333f, 0.209280923008919f, 0.406795293092728f, + 0.209593027830124f, 0.407018154859543f, 0.209905281662941f, 0.407240778207779f, + 0.210217714309692f, 0.407463163137436f, 0.210530325770378f, 0.407685309648514f, + 0.210843101143837f, 0.407907217741013f, 0.211156040430069f, 0.408128857612610f, + 0.211469158530235f, 0.408350288867950f, 0.211782455444336f, 0.408571451902390f, + 0.212095901370049f, 0.408792406320572f, 0.212409526109695f, 0.409013092517853f, + 0.212723329663277f, 0.409233570098877f, 0.213037282228470f, 0.409453779459000f, + 0.213351413607597f, 0.409673750400543f, 0.213665723800659f, 0.409893482923508f, + 0.213980183005333f, 0.410112977027893f, 0.214294821023941f, 0.410332232713699f, + 0.214609622955322f, 0.410551249980927f, 0.214924603700638f, 0.410770028829575f, + 0.215239733457565f, 0.410988569259644f, 0.215555042028427f, 0.411206841468811f, + 0.215870529413223f, 0.411424905061722f, 0.216186165809631f, 0.411642700433731f, + 0.216501981019974f, 0.411860257387161f, 0.216817945241928f, 0.412077575922012f, + 0.217134088277817f, 0.412294656038284f, 0.217450410127640f, 0.412511497735977f, + 0.217766880989075f, 0.412728071212769f, 0.218083515763283f, 0.412944436073303f, + 0.218400329351425f, 0.413160532712936f, 0.218717306852341f, 0.413376390933990f, + 0.219034433364868f, 0.413592010736465f, 0.219351738691330f, 0.413807392120361f, + 0.219669207930565f, 0.414022535085678f, 0.219986841082573f, 0.414237409830093f, + 0.220304638147354f, 0.414452046155930f, 0.220622614026070f, 0.414666473865509f, + 0.220940738916397f, 0.414880603551865f, 0.221259027719498f, 0.415094524621964f, + 0.221577480435371f, 0.415308207273483f, 0.221896097064018f, 0.415521621704102f, + 0.222214877605438f, 0.415734797716141f, 0.222533836960793f, 0.415947735309601f, + 0.222852945327759f, 0.416160434484482f, 0.223172217607498f, 0.416372895240784f, + 0.223491653800011f, 0.416585087776184f, 0.223811239004135f, 0.416797041893005f, + 0.224131003022194f, 0.417008757591248f, 0.224450930953026f, 0.417220205068588f, + 0.224771007895470f, 0.417431443929672f, 0.225091263651848f, 0.417642414569855f, + 0.225411668419838f, 0.417853146791458f, 0.225732237100601f, 0.418063640594482f, + 0.226052969694138f, 0.418273866176605f, 0.226373866200447f, 0.418483853340149f, + 0.226694911718369f, 0.418693602085114f, 0.227016136050224f, 0.418903112411499f, + 0.227337509393692f, 0.419112354516983f, 0.227659046649933f, 0.419321358203888f, + 0.227980732917786f, 0.419530123472214f, 0.228302597999573f, 0.419738620519638f, + 0.228624612092972f, 0.419946908950806f, 0.228946775197983f, 0.420154929161072f, + 0.229269117116928f, 0.420362681150436f, 0.229591608047485f, 0.420570224523544f, + 0.229914262890816f, 0.420777499675751f, 0.230237081646919f, 0.420984506607056f, + 0.230560049414635f, 0.421191304922104f, 0.230883181095123f, 0.421397835016251f, + 0.231206461787224f, 0.421604126691818f, 0.231529906392097f, 0.421810150146484f, + 0.231853514909744f, 0.422015935182571f, 0.232177272439003f, 0.422221481800079f, + 0.232501193881035f, 0.422426789999008f, 0.232825264334679f, 0.422631829977036f, + 0.233149498701096f, 0.422836631536484f, 0.233473882079124f, 0.423041164875031f, + 0.233798429369926f, 0.423245459794998f, 0.234123140573502f, 0.423449516296387f, + 0.234448000788689f, 0.423653304576874f, 0.234773010015488f, 0.423856884241104f, + 0.235098183155060f, 0.424060165882111f, 0.235423520207405f, 0.424263238906860f, + 0.235749006271362f, 0.424466013908386f, 0.236074641346931f, 0.424668580293655f, + 0.236400425434113f, 0.424870878458023f, 0.236726388335228f, 0.425072938203812f, + 0.237052485346794f, 0.425274729728699f, 0.237378746271133f, 0.425476282835007f, + 0.237705156207085f, 0.425677597522736f, 0.238031730055809f, 0.425878643989563f, + 0.238358452916145f, 0.426079452037811f, 0.238685324788094f, 0.426279991865158f, + 0.239012360572815f, 0.426480293273926f, 0.239339530467987f, 0.426680356264114f, + 0.239666879177094f, 0.426880151033401f, 0.239994361996651f, 0.427079707384110f, + 0.240322008728981f, 0.427278995513916f, 0.240649804472923f, 0.427478045225143f, + 0.240977749228477f, 0.427676826715469f, 0.241305842995644f, 0.427875369787216f, + 0.241634100675583f, 0.428073674440384f, 0.241962507367134f, 0.428271710872650f, + 0.242291063070297f, 0.428469479084015f, 0.242619767785072f, 0.428667008876801f, + 0.242948621511459f, 0.428864300251007f, 0.243277639150620f, 0.429061323404312f, + 0.243606805801392f, 0.429258108139038f, 0.243936106562614f, 0.429454624652863f, + 0.244265571236610f, 0.429650902748108f, 0.244595184922218f, 0.429846942424774f, + 0.244924947619438f, 0.430042684078217f, 0.245254859328270f, 0.430238217115402f, + 0.245584934949875f, 0.430433481931686f, 0.245915144681931f, 0.430628478527069f, + 0.246245503425598f, 0.430823236703873f, 0.246576011180878f, 0.431017726659775f, + 0.246906682848930f, 0.431211978197098f, 0.247237488627434f, 0.431405961513519f, + 0.247568443417549f, 0.431599706411362f, 0.247899547219276f, 0.431793183088303f, + 0.248230814933777f, 0.431986421346664f, 0.248562216758728f, 0.432179391384125f, + 0.248893767595291f, 0.432372123003006f, 0.249225467443466f, 0.432564586400986f, + 0.249557301402092f, 0.432756811380386f, 0.249889299273491f, 0.432948768138886f, + 0.250221431255341f, 0.433140486478806f, 0.250553727149963f, 0.433331936597824f, + 0.250886172056198f, 0.433523118495941f, 0.251218736171722f, 0.433714061975479f, + 0.251551479101181f, 0.433904737234116f, 0.251884341239929f, 0.434095174074173f, + 0.252217382192612f, 0.434285342693329f, 0.252550542354584f, 0.434475272893906f, + 0.252883851528168f, 0.434664934873581f, 0.253217309713364f, 0.434854328632355f, + 0.253550916910172f, 0.435043483972549f, 0.253884643316269f, 0.435232400894165f, + 0.254218548536301f, 0.435421019792557f, 0.254552572965622f, 0.435609430074692f, + 0.254886746406555f, 0.435797542333603f, 0.255221068859100f, 0.435985416173935f, + 0.255555540323257f, 0.436173021793365f, 0.255890160799026f, 0.436360388994217f, + 0.256224930286407f, 0.436547487974167f, 0.256559818983078f, 0.436734348535538f, + 0.256894856691360f, 0.436920911073685f, 0.257230043411255f, 0.437107264995575f, + 0.257565379142761f, 0.437293320894241f, 0.257900834083557f, 0.437479138374329f, + 0.258236467838287f, 0.437664687633514f, 0.258572220802307f, 0.437849998474121f, + 0.258908122777939f, 0.438035041093826f, 0.259244143962860f, 0.438219845294952f, + 0.259580343961716f, 0.438404351472855f, 0.259916663169861f, 0.438588619232178f, + 0.260253131389618f, 0.438772648572922f, 0.260589718818665f, 0.438956409692764f, + 0.260926485061646f, 0.439139902591705f, 0.261263370513916f, 0.439323127269745f, + 0.261600375175476f, 0.439506113529205f, 0.261937558650970f, 0.439688831567764f, + 0.262274861335754f, 0.439871311187744f, 0.262612313032150f, 0.440053492784500f, + 0.262949883937836f, 0.440235435962677f, 0.263287603855133f, 0.440417140722275f, + 0.263625472784042f, 0.440598547458649f, 0.263963490724564f, 0.440779715776443f, + 0.264301627874374f, 0.440960645675659f, 0.264639914035797f, 0.441141277551651f, + 0.264978319406509f, 0.441321671009064f, 0.265316903591156f, 0.441501796245575f, + 0.265655577182770f, 0.441681683063507f, 0.265994429588318f, 0.441861271858215f, + 0.266333401203156f, 0.442040622234344f, 0.266672492027283f, 0.442219734191895f, + 0.267011761665344f, 0.442398548126221f, 0.267351150512695f, 0.442577123641968f, + 0.267690658569336f, 0.442755430936813f, 0.268030315637589f, 0.442933470010757f, + 0.268370121717453f, 0.443111270666122f, 0.268710047006607f, 0.443288803100586f, + 0.269050091505051f, 0.443466067314148f, 0.269390314817429f, 0.443643063306808f, + 0.269730657339096f, 0.443819820880890f, 0.270071119070053f, 0.443996280431747f, + 0.270411729812622f, 0.444172531366348f, 0.270752459764481f, 0.444348484277725f, + 0.271093338727951f, 0.444524168968201f, 0.271434366703033f, 0.444699615240097f, + 0.271775513887405f, 0.444874793291092f, 0.272116780281067f, 0.445049703121185f, + 0.272458195686340f, 0.445224374532700f, 0.272799760103226f, 0.445398747920990f, + 0.273141443729401f, 0.445572882890701f, 0.273483246564865f, 0.445746749639511f, + 0.273825198411942f, 0.445920348167419f, 0.274167299270630f, 0.446093708276749f, + 0.274509519338608f, 0.446266770362854f, 0.274851858615875f, 0.446439594030380f, + 0.275194346904755f, 0.446612149477005f, 0.275536954402924f, 0.446784436702728f, + 0.275879681110382f, 0.446956485509872f, 0.276222556829453f, 0.447128236293793f, + 0.276565581560135f, 0.447299748659134f, 0.276908725500107f, 0.447470992803574f, + 0.277251988649368f, 0.447641968727112f, 0.277595400810242f, 0.447812676429749f, + 0.277938932180405f, 0.447983115911484f, 0.278282582759857f, 0.448153316974640f, + 0.278626382350922f, 0.448323249816895f, 0.278970301151276f, 0.448492884635925f, + 0.279314368963242f, 0.448662281036377f, 0.279658555984497f, 0.448831409215927f, + 0.280002862215042f, 0.449000298976898f, 0.280347317457199f, 0.449168890714645f, + 0.280691891908646f, 0.449337244033813f, 0.281036585569382f, 0.449505299329758f, + 0.281381398439407f, 0.449673116207123f, 0.281726360321045f, 0.449840664863586f, + 0.282071471214294f, 0.450007945299149f, 0.282416671514511f, 0.450174957513809f, + 0.282762020826340f, 0.450341701507568f, 0.283107489347458f, 0.450508207082748f, + 0.283453077077866f, 0.450674414634705f, 0.283798813819885f, 0.450840383768082f, + 0.284144669771194f, 0.451006084680557f, 0.284490644931793f, 0.451171487569809f, + 0.284836769104004f, 0.451336652040482f, 0.285182982683182f, 0.451501548290253f, + 0.285529345273972f, 0.451666176319122f, 0.285875827074051f, 0.451830536127090f, + 0.286222457885742f, 0.451994657516479f, 0.286569178104401f, 0.452158480882645f, + 0.286916047334671f, 0.452322036027908f, 0.287263035774231f, 0.452485352754593f, + 0.287610173225403f, 0.452648371458054f, 0.287957400083542f, 0.452811151742935f, + 0.288304775953293f, 0.452973634004593f, 0.288652241230011f, 0.453135877847672f, + 0.288999855518341f, 0.453297853469849f, 0.289347589015961f, 0.453459560871124f, + 0.289695471525192f, 0.453621000051498f, 0.290043443441391f, 0.453782171010971f, + 0.290391564369202f, 0.453943043947220f, 0.290739774703979f, 0.454103678464890f, + 0.291088134050369f, 0.454264044761658f, 0.291436612606049f, 0.454424172639847f, + 0.291785210371017f, 0.454584002494812f, 0.292133957147598f, 0.454743564128876f, + 0.292482793331146f, 0.454902857542038f, 0.292831748723984f, 0.455061882734299f, + 0.293180853128433f, 0.455220639705658f, 0.293530046939850f, 0.455379128456116f, + 0.293879389762878f, 0.455537378787994f, 0.294228851795197f, 0.455695331096649f, + 0.294578403234482f, 0.455853015184402f, 0.294928103685379f, 0.456010431051254f, + 0.295277923345566f, 0.456167578697205f, 0.295627862215042f, 0.456324487924576f, + 0.295977920293808f, 0.456481099128723f, 0.296328097581863f, 0.456637442111969f, + 0.296678394079208f, 0.456793516874313f, 0.297028809785843f, 0.456949323415756f, + 0.297379344701767f, 0.457104891538620f, 0.297729998826981f, 0.457260161638260f, + 0.298080772161484f, 0.457415163516998f, 0.298431664705276f, 0.457569897174835f, + 0.298782676458359f, 0.457724362611771f, 0.299133807420731f, 0.457878559827805f, + 0.299485057592392f, 0.458032488822937f, 0.299836426973343f, 0.458186149597168f, + 0.300187885761261f, 0.458339542150497f, 0.300539493560791f, 0.458492636680603f, + 0.300891220569611f, 0.458645492792130f, 0.301243066787720f, 0.458798080682755f, + 0.301595002412796f, 0.458950400352478f, 0.301947087049484f, 0.459102421998978f, + 0.302299261093140f, 0.459254205226898f, 0.302651554346085f, 0.459405690431595f, + 0.303003966808319f, 0.459556937217712f, 0.303356528282166f, 0.459707885980606f, + 0.303709149360657f, 0.459858566522598f, 0.304061919450760f, 0.460008978843689f, + 0.304414808750153f, 0.460159152746201f, 0.304767817258835f, 0.460309028625488f, + 0.305120915174484f, 0.460458606481552f, 0.305474132299423f, 0.460607945919037f, + 0.305827468633652f, 0.460757017135620f, 0.306180924177170f, 0.460905820131302f, + 0.306534498929977f, 0.461054325103760f, 0.306888192892075f, 0.461202591657639f, + 0.307241976261139f, 0.461350560188293f, 0.307595878839493f, 0.461498260498047f, + 0.307949900627136f, 0.461645722389221f, 0.308304041624069f, 0.461792886257172f, + 0.308658272027969f, 0.461939752101898f, 0.309012651443481f, 0.462086379528046f, + 0.309367120265961f, 0.462232738733292f, 0.309721708297729f, 0.462378799915314f, + 0.310076385736465f, 0.462524622678757f, 0.310431212186813f, 0.462670147418976f, + 0.310786128044128f, 0.462815403938293f, 0.311141163110733f, 0.462960392236710f, + 0.311496287584305f, 0.463105112314224f, 0.311851561069489f, 0.463249564170837f, + 0.312206923961639f, 0.463393747806549f, 0.312562376260757f, 0.463537633419037f, + 0.312917977571487f, 0.463681250810623f, 0.313273668289185f, 0.463824629783630f, + 0.313629478216171f, 0.463967710733414f, 0.313985377550125f, 0.464110493659973f, + 0.314341396093369f, 0.464253038167953f, 0.314697533845901f, 0.464395314455032f, + 0.315053790807724f, 0.464537292718887f, 0.315410137176514f, 0.464679002761841f, + 0.315766572952271f, 0.464820444583893f, 0.316123157739639f, 0.464961618185043f, + 0.316479831933975f, 0.465102523565292f, 0.316836595535278f, 0.465243130922318f, + 0.317193508148193f, 0.465383470058441f, 0.317550510168076f, 0.465523540973663f, + 0.317907601594925f, 0.465663343667984f, 0.318264812231064f, 0.465802878141403f, + 0.318622142076492f, 0.465942144393921f, 0.318979561328888f, 0.466081112623215f, + 0.319337099790573f, 0.466219812631607f, 0.319694727659225f, 0.466358244419098f, + 0.320052474737167f, 0.466496407985687f, 0.320410341024399f, 0.466634273529053f, + 0.320768296718597f, 0.466771900653839f, 0.321126341819763f, 0.466909229755402f, + 0.321484506130219f, 0.467046260833740f, 0.321842789649963f, 0.467183053493500f, + 0.322201162576675f, 0.467319577932358f, 0.322559654712677f, 0.467455804347992f, + 0.322918236255646f, 0.467591762542725f, 0.323276937007904f, 0.467727422714233f, + 0.323635727167130f, 0.467862844467163f, 0.323994606733322f, 0.467997968196869f, + 0.324353635311127f, 0.468132823705673f, 0.324712723493576f, 0.468267410993576f, + 0.325071930885315f, 0.468401730060577f, 0.325431257486343f, 0.468535751104355f, + 0.325790673494339f, 0.468669503927231f, 0.326150178909302f, 0.468802988529205f, + 0.326509803533554f, 0.468936175107956f, 0.326869517564774f, 0.469069123268127f, + 0.327229350805283f, 0.469201773405075f, 0.327589273452759f, 0.469334155321121f, + 0.327949285507202f, 0.469466239213943f, 0.328309416770935f, 0.469598054885864f, + 0.328669637441635f, 0.469729602336884f, 0.329029977321625f, 0.469860881567001f, + 0.329390406608582f, 0.469991862773895f, 0.329750925302505f, 0.470122605562210f, + 0.330111563205719f, 0.470253020524979f, 0.330472290515900f, 0.470383197069168f, + 0.330833107233047f, 0.470513075590134f, 0.331194043159485f, 0.470642685890198f, + 0.331555068492889f, 0.470772027969360f, 0.331916213035584f, 0.470901101827621f, + 0.332277417182922f, 0.471029877662659f, 0.332638740539551f, 0.471158385276794f, + 0.333000183105469f, 0.471286594867706f, 0.333361685276031f, 0.471414536237717f, + 0.333723306655884f, 0.471542209386826f, 0.334085017442703f, 0.471669614315033f, + 0.334446847438812f, 0.471796721220016f, 0.334808766841888f, 0.471923559904099f, + 0.335170775651932f, 0.472050130367279f, 0.335532873868942f, 0.472176402807236f, + 0.335895091295242f, 0.472302407026291f, 0.336257368326187f, 0.472428143024445f, + 0.336619764566422f, 0.472553610801697f, 0.336982280015945f, 0.472678780555725f, + 0.337344855070114f, 0.472803652286530f, 0.337707549333572f, 0.472928285598755f, + 0.338070303201675f, 0.473052620887756f, 0.338433176279068f, 0.473176687955856f, + 0.338796168565750f, 0.473300457000732f, 0.339159220457077f, 0.473423957824707f, + 0.339522391557693f, 0.473547190427780f, 0.339885622262955f, 0.473670125007629f, + 0.340248972177505f, 0.473792791366577f, 0.340612411499023f, 0.473915189504623f, + 0.340975970029831f, 0.474037289619446f, 0.341339588165283f, 0.474159121513367f, + 0.341703325510025f, 0.474280685186386f, 0.342067122459412f, 0.474401950836182f, + 0.342431038618088f, 0.474522948265076f, 0.342795044183731f, 0.474643647670746f, + 0.343159139156342f, 0.474764078855515f, 0.343523323535919f, 0.474884241819382f, + 0.343887597322464f, 0.475004136562347f, 0.344251960515976f, 0.475123733282089f, + 0.344616413116455f, 0.475243031978607f, 0.344980984926224f, 0.475362062454224f, + 0.345345616340637f, 0.475480824708939f, 0.345710366964340f, 0.475599318742752f, + 0.346075177192688f, 0.475717514753342f, 0.346440106630325f, 0.475835442543030f, + 0.346805095672607f, 0.475953072309494f, 0.347170203924179f, 0.476070433855057f, + 0.347535371780396f, 0.476187497377396f, 0.347900658845901f, 0.476304292678833f, + 0.348266035318375f, 0.476420819759369f, 0.348631471395493f, 0.476537048816681f, + 0.348997026681900f, 0.476653009653091f, 0.349362671375275f, 0.476768702268600f, + 0.349728375673294f, 0.476884096860886f, 0.350094199180603f, 0.476999223232269f, + 0.350460082292557f, 0.477114051580429f, 0.350826084613800f, 0.477228611707687f, + 0.351192146539688f, 0.477342873811722f, 0.351558297872543f, 0.477456867694855f, + 0.351924568414688f, 0.477570593357086f, 0.352290898561478f, 0.477684020996094f, + 0.352657318115234f, 0.477797180414200f, 0.353023827075958f, 0.477910041809082f, + 0.353390425443649f, 0.478022634983063f, 0.353757113218308f, 0.478134930133820f, + 0.354123860597610f, 0.478246957063675f, 0.354490727186203f, 0.478358715772629f, + 0.354857653379440f, 0.478470176458359f, 0.355224698781967f, 0.478581339120865f, + 0.355591803789139f, 0.478692263364792f, 0.355958998203278f, 0.478802859783173f, + 0.356326282024384f, 0.478913217782974f, 0.356693625450134f, 0.479023247957230f, + 0.357061088085175f, 0.479133039712906f, 0.357428610324860f, 0.479242533445358f, + 0.357796221971512f, 0.479351729154587f, 0.358163923025131f, 0.479460656642914f, + 0.358531713485718f, 0.479569315910339f, 0.358899593353271f, 0.479677677154541f, + 0.359267532825470f, 0.479785770177841f, 0.359635561704636f, 0.479893565177917f, + 0.360003679990768f, 0.480001062154770f, 0.360371887683868f, 0.480108320713043f, + 0.360740154981613f, 0.480215251445770f, 0.361108511686325f, 0.480321943759918f, + 0.361476957798004f, 0.480428308248520f, 0.361845493316650f, 0.480534434318542f, + 0.362214088439941f, 0.480640232563019f, 0.362582772970200f, 0.480745792388916f, + 0.362951546907425f, 0.480851024389267f, 0.363320380449295f, 0.480956017971039f, + 0.363689333200455f, 0.481060713529587f, 0.364058345556259f, 0.481165111064911f, + 0.364427417516708f, 0.481269240379334f, 0.364796578884125f, 0.481373071670532f, + 0.365165829658508f, 0.481476634740829f, 0.365535169839859f, 0.481579899787903f, + 0.365904569625854f, 0.481682896614075f, 0.366274058818817f, 0.481785595417023f, + 0.366643607616425f, 0.481888025999069f, 0.367013275623322f, 0.481990188360214f, + 0.367382973432541f, 0.482092022895813f, 0.367752790451050f, 0.482193619012833f, + 0.368122667074203f, 0.482294887304306f, 0.368492603302002f, 0.482395917177200f, + 0.368862658739090f, 0.482496619224548f, 0.369232743978500f, 0.482597053050995f, + 0.369602948427200f, 0.482697218656540f, 0.369973212480545f, 0.482797086238861f, + 0.370343536138535f, 0.482896685600281f, 0.370713949203491f, 0.482995986938477f, + 0.371084451675415f, 0.483094990253448f, 0.371455013751984f, 0.483193725347519f, + 0.371825665235519f, 0.483292192220688f, 0.372196376323700f, 0.483390361070633f, + 0.372567176818848f, 0.483488231897354f, 0.372938036918640f, 0.483585834503174f, + 0.373308986425400f, 0.483683139085770f, 0.373679995536804f, 0.483780175447464f, + 0.374051094055176f, 0.483876913785934f, 0.374422252178192f, 0.483973383903503f, + 0.374793499708176f, 0.484069555997849f, 0.375164806842804f, 0.484165430068970f, + 0.375536203384399f, 0.484261035919189f, 0.375907659530640f, 0.484356373548508f, + 0.376279205083847f, 0.484451413154602f, 0.376650810241699f, 0.484546154737473f, + 0.377022475004196f, 0.484640628099442f, 0.377394229173660f, 0.484734803438187f, + 0.377766042947769f, 0.484828680753708f, 0.378137946128845f, 0.484922289848328f, + 0.378509908914566f, 0.485015630722046f, 0.378881961107254f, 0.485108673572540f, + 0.379254043102264f, 0.485201418399811f, 0.379626244306564f, 0.485293895006180f, + 0.379998475313187f, 0.485386073589325f, 0.380370795726776f, 0.485477954149246f, + 0.380743205547333f, 0.485569566488266f, 0.381115674972534f, 0.485660910606384f, + 0.381488204002380f, 0.485751956701279f, 0.381860792636871f, 0.485842704772949f, + 0.382233470678329f, 0.485933154821396f, 0.382606208324432f, 0.486023366451263f, + 0.382979035377502f, 0.486113250255585f, 0.383351892232895f, 0.486202865839005f, + 0.383724838495255f, 0.486292183399200f, 0.384097874164581f, 0.486381232738495f, + 0.384470939636230f, 0.486469984054565f, 0.384844094514847f, 0.486558437347412f, + 0.385217308998108f, 0.486646622419357f, 0.385590612888336f, 0.486734509468079f, + 0.385963946580887f, 0.486822128295898f, 0.386337369680405f, 0.486909449100494f, + 0.386710882186890f, 0.486996471881866f, 0.387084424495697f, 0.487083226442337f, + 0.387458056211472f, 0.487169682979584f, 0.387831717729568f, 0.487255871295929f, + 0.388205498456955f, 0.487341761589050f, 0.388579308986664f, 0.487427353858948f, + 0.388953179121017f, 0.487512677907944f, 0.389327138662338f, 0.487597703933716f, + 0.389701157808304f, 0.487682431936264f, 0.390075236558914f, 0.487766891717911f, + 0.390449374914169f, 0.487851053476334f, 0.390823602676392f, 0.487934947013855f, + 0.391197860240936f, 0.488018542528152f, 0.391572207212448f, 0.488101840019226f, + 0.391946613788605f, 0.488184869289398f, 0.392321079969406f, 0.488267600536346f, + 0.392695605754852f, 0.488350033760071f, 0.393070191144943f, 0.488432198762894f, + 0.393444836139679f, 0.488514065742493f, 0.393819570541382f, 0.488595664501190f, + 0.394194334745407f, 0.488676935434341f, 0.394569188356400f, 0.488757967948914f, + 0.394944071769714f, 0.488838672637939f, 0.395319044589996f, 0.488919109106064f, + 0.395694077014923f, 0.488999247550964f, 0.396069169044495f, 0.489079117774963f, + 0.396444320678711f, 0.489158689975739f, 0.396819531917572f, 0.489237964153290f, + 0.397194802761078f, 0.489316970109940f, 0.397570133209229f, 0.489395678043365f, + 0.397945523262024f, 0.489474087953568f, 0.398320972919464f, 0.489552229642868f, + 0.398696482181549f, 0.489630073308945f, 0.399072051048279f, 0.489707618951797f, + 0.399447679519653f, 0.489784896373749f, 0.399823367595673f, 0.489861875772476f, + 0.400199115276337f, 0.489938557147980f, 0.400574922561646f, 0.490014940500259f, + 0.400950789451599f, 0.490091055631638f, 0.401326715946198f, 0.490166902542114f, + 0.401702702045441f, 0.490242421627045f, 0.402078747749329f, 0.490317672491074f, + 0.402454853057861f, 0.490392625331879f, 0.402830988168716f, 0.490467309951782f, + 0.403207212686539f, 0.490541696548462f, 0.403583467006683f, 0.490615785121918f, + 0.403959810733795f, 0.490689605474472f, 0.404336184263229f, 0.490763127803802f, + 0.404712617397308f, 0.490836352109909f, 0.405089110136032f, 0.490909278392792f, + 0.405465662479401f, 0.490981936454773f, 0.405842274427414f, 0.491054296493530f, + 0.406218945980072f, 0.491126358509064f, 0.406595647335052f, 0.491198152303696f, + 0.406972438097000f, 0.491269648075104f, 0.407349258661270f, 0.491340845823288f, + 0.407726138830185f, 0.491411775350571f, 0.408103078603745f, 0.491482406854630f, + 0.408480048179626f, 0.491552740335464f, 0.408857107162476f, 0.491622805595398f, + 0.409234195947647f, 0.491692543029785f, 0.409611344337463f, 0.491762012243271f, + 0.409988552331924f, 0.491831213235855f, 0.410365819931030f, 0.491900116205215f, + 0.410743117332459f, 0.491968721151352f, 0.411120474338531f, 0.492037028074265f, + 0.411497890949249f, 0.492105036973953f, 0.411875367164612f, 0.492172777652740f, + 0.412252873182297f, 0.492240220308304f, 0.412630438804626f, 0.492307394742966f, + 0.413008064031601f, 0.492374241352081f, 0.413385748863220f, 0.492440819740295f, + 0.413763463497162f, 0.492507129907608f, 0.414141237735748f, 0.492573112249374f, + 0.414519041776657f, 0.492638826370239f, 0.414896935224533f, 0.492704242467880f, + 0.415274858474731f, 0.492769360542297f, 0.415652841329575f, 0.492834210395813f, + 0.416030853986740f, 0.492898762226105f, 0.416408926248550f, 0.492963016033173f, + 0.416787058115005f, 0.493026971817017f, 0.417165219783783f, 0.493090659379959f, + 0.417543441057205f, 0.493154048919678f, 0.417921721935272f, 0.493217140436172f, + 0.418300032615662f, 0.493279963731766f, 0.418678402900696f, 0.493342459201813f, + 0.419056802988052f, 0.493404686450958f, 0.419435262680054f, 0.493466645479202f, + 0.419813781976700f, 0.493528276681900f, 0.420192331075668f, 0.493589639663696f, + 0.420570939779282f, 0.493650704622269f, 0.420949578285217f, 0.493711471557617f, + 0.421328276395798f, 0.493771970272064f, 0.421707004308701f, 0.493832170963287f, + 0.422085791826248f, 0.493892073631287f, 0.422464638948441f, 0.493951678276062f, + 0.422843515872955f, 0.494011014699936f, 0.423222452402115f, 0.494070053100586f, + 0.423601418733597f, 0.494128793478012f, 0.423980414867401f, 0.494187235832214f, + 0.424359470605850f, 0.494245409965515f, 0.424738585948944f, 0.494303256273270f, + 0.425117731094360f, 0.494360834360123f, 0.425496935844421f, 0.494418144226074f, + 0.425876170396805f, 0.494475126266479f, 0.426255434751511f, 0.494531840085983f, + 0.426634758710861f, 0.494588255882263f, 0.427014142274857f, 0.494644373655319f, + 0.427393525838852f, 0.494700223207474f, 0.427772998809814f, 0.494755744934082f, + 0.428152471780777f, 0.494810998439789f, 0.428532034158707f, 0.494865983724594f, + 0.428911596536636f, 0.494920641183853f, 0.429291218519211f, 0.494975030422211f, + 0.429670870304108f, 0.495029091835022f, 0.430050581693649f, 0.495082914829254f, + 0.430430322885513f, 0.495136409997940f, 0.430810123682022f, 0.495189607143402f, + 0.431189924478531f, 0.495242536067963f, 0.431569814682007f, 0.495295166969299f, + 0.431949704885483f, 0.495347499847412f, 0.432329654693604f, 0.495399564504623f, + 0.432709634304047f, 0.495451331138611f, 0.433089673519135f, 0.495502769947052f, + 0.433469742536545f, 0.495553970336914f, 0.433849841356277f, 0.495604842901230f, + 0.434229999780655f, 0.495655417442322f, 0.434610158205032f, 0.495705723762512f, + 0.434990376234055f, 0.495755732059479f, 0.435370653867722f, 0.495805442333221f, + 0.435750931501389f, 0.495854884386063f, 0.436131268739700f, 0.495903998613358f, + 0.436511665582657f, 0.495952844619751f, 0.436892062425613f, 0.496001392602921f, + 0.437272518873215f, 0.496049642562866f, 0.437653005123138f, 0.496097624301910f, + 0.438033521175385f, 0.496145308017731f, 0.438414067029953f, 0.496192663908005f, + 0.438794672489166f, 0.496239781379700f, 0.439175277948380f, 0.496286571025848f, + 0.439555943012238f, 0.496333062648773f, 0.439936667680740f, 0.496379286050797f, + 0.440317392349243f, 0.496425211429596f, 0.440698176622391f, 0.496470838785172f, + 0.441078960895538f, 0.496516168117523f, 0.441459804773331f, 0.496561229228973f, + 0.441840678453445f, 0.496605962514877f, 0.442221581935883f, 0.496650427579880f, + 0.442602545022964f, 0.496694594621658f, 0.442983508110046f, 0.496738493442535f, + 0.443364530801773f, 0.496782064437866f, 0.443745553493500f, 0.496825367212296f, + 0.444126635789871f, 0.496868371963501f, 0.444507747888565f, 0.496911078691483f, + 0.444888889789581f, 0.496953487396240f, 0.445270061492920f, 0.496995598077774f, + 0.445651292800903f, 0.497037440538406f, 0.446032524108887f, 0.497078984975815f, + 0.446413785219193f, 0.497120231389999f, 0.446795076131821f, 0.497161179780960f, + 0.447176426649094f, 0.497201830148697f, 0.447557777166367f, 0.497242212295532f, + 0.447939187288284f, 0.497282296419144f, 0.448320597410202f, 0.497322082519531f, + 0.448702067136765f, 0.497361570596695f, 0.449083566665649f, 0.497400760650635f, + 0.449465066194534f, 0.497439652681351f, 0.449846625328064f, 0.497478276491165f, + 0.450228184461594f, 0.497516602277756f, 0.450609803199768f, 0.497554630041122f, + 0.450991421937943f, 0.497592359781265f, 0.451373100280762f, 0.497629791498184f, + 0.451754778623581f, 0.497666954994202f, 0.452136516571045f, 0.497703820466995f, + 0.452518254518509f, 0.497740387916565f, 0.452900022268295f, 0.497776657342911f, + 0.453281819820404f, 0.497812628746033f, 0.453663676977158f, 0.497848302125931f, + 0.454045534133911f, 0.497883707284927f, 0.454427421092987f, 0.497918814420700f, + 0.454809308052063f, 0.497953623533249f, 0.455191254615784f, 0.497988134622574f, + 0.455573230981827f, 0.498022347688675f, 0.455955207347870f, 0.498056292533875f, + 0.456337243318558f, 0.498089909553528f, 0.456719279289246f, 0.498123258352280f, + 0.457101345062256f, 0.498156309127808f, 0.457483440637589f, 0.498189061880112f, + 0.457865566015244f, 0.498221516609192f, 0.458247691392899f, 0.498253703117371f, + 0.458629876375198f, 0.498285561800003f, 0.459012061357498f, 0.498317152261734f, + 0.459394276142120f, 0.498348444700241f, 0.459776520729065f, 0.498379439115524f, + 0.460158795118332f, 0.498410135507584f, 0.460541069507599f, 0.498440563678741f, + 0.460923373699188f, 0.498470664024353f, 0.461305707693100f, 0.498500496149063f, + 0.461688071489334f, 0.498530030250549f, 0.462070435285568f, 0.498559266328812f, + 0.462452858686447f, 0.498588204383850f, 0.462835282087326f, 0.498616874217987f, + 0.463217705488205f, 0.498645216226578f, 0.463600188493729f, 0.498673290014267f, + 0.463982671499252f, 0.498701065778732f, 0.464365184307098f, 0.498728543519974f, + 0.464747726917267f, 0.498755723237991f, 0.465130269527435f, 0.498782604932785f, + 0.465512841939926f, 0.498809218406677f, 0.465895414352417f, 0.498835533857346f, + 0.466278046369553f, 0.498861521482468f, 0.466660678386688f, 0.498887240886688f, + 0.467043310403824f, 0.498912662267685f, 0.467426002025604f, 0.498937815427780f, + 0.467808693647385f, 0.498962640762329f, 0.468191385269165f, 0.498987197875977f, + 0.468574106693268f, 0.499011427164078f, 0.468956857919693f, 0.499035388231277f, + 0.469339638948441f, 0.499059051275253f, 0.469722419977188f, 0.499082416296005f, + 0.470105201005936f, 0.499105513095856f, 0.470488041639328f, 0.499128282070160f, + 0.470870882272720f, 0.499150782823563f, 0.471253722906113f, 0.499172955751419f, + 0.471636593341827f, 0.499194860458374f, 0.472019463777542f, 0.499216467142105f, + 0.472402364015579f, 0.499237775802612f, 0.472785294055939f, 0.499258816242218f, + 0.473168224096298f, 0.499279528856277f, 0.473551183938980f, 0.499299973249435f, + 0.473934143781662f, 0.499320119619370f, 0.474317133426666f, 0.499339967966080f, + 0.474700123071671f, 0.499359518289566f, 0.475083142518997f, 0.499378770589828f, + 0.475466161966324f, 0.499397724866867f, 0.475849211215973f, 0.499416410923004f, + 0.476232260465622f, 0.499434769153595f, 0.476615339517593f, 0.499452859163284f, + 0.476998418569565f, 0.499470651149750f, 0.477381497621536f, 0.499488145112991f, + 0.477764606475830f, 0.499505341053009f, 0.478147745132446f, 0.499522238969803f, + 0.478530883789063f, 0.499538868665695f, 0.478914022445679f, 0.499555170536041f, + 0.479297190904617f, 0.499571204185486f, 0.479680359363556f, 0.499586939811707f, + 0.480063527822495f, 0.499602377414703f, 0.480446726083755f, 0.499617516994476f, + 0.480829954147339f, 0.499632388353348f, 0.481213152408600f, 0.499646931886673f, + 0.481596380472183f, 0.499661177396774f, 0.481979638338089f, 0.499675154685974f, + 0.482362866401672f, 0.499688833951950f, 0.482746154069901f, 0.499702215194702f, + 0.483129411935806f, 0.499715298414230f, 0.483512699604034f, 0.499728083610535f, + 0.483895987272263f, 0.499740600585938f, 0.484279274940491f, 0.499752789735794f, + 0.484662592411041f, 0.499764710664749f, 0.485045909881592f, 0.499776333570480f, + 0.485429257154465f, 0.499787658452988f, 0.485812574625015f, 0.499798685312271f, + 0.486195921897888f, 0.499809414148331f, 0.486579269170761f, 0.499819844961166f, + 0.486962646245956f, 0.499830007553101f, 0.487346023321152f, 0.499839842319489f, + 0.487729400396347f, 0.499849408864975f, 0.488112777471542f, 0.499858677387238f, + 0.488496154546738f, 0.499867647886276f, 0.488879561424255f, 0.499876320362091f, + 0.489262968301773f, 0.499884694814682f, 0.489646375179291f, 0.499892801046371f, + 0.490029782056808f, 0.499900579452515f, 0.490413218736649f, 0.499908089637756f, + 0.490796625614166f, 0.499915301799774f, 0.491180062294006f, 0.499922215938568f, + 0.491563498973846f, 0.499928832054138f, 0.491946935653687f, 0.499935150146484f, + 0.492330402135849f, 0.499941170215607f, 0.492713838815689f, 0.499946922063828f, + 0.493097305297852f, 0.499952346086502f, 0.493480771780014f, 0.499957501888275f, + 0.493864238262177f, 0.499962359666824f, 0.494247704744339f, 0.499966919422150f, + 0.494631171226501f, 0.499971181154251f, 0.495014637708664f, 0.499975144863129f, + 0.495398133993149f, 0.499978810548782f, 0.495781600475311f, 0.499982208013535f, + 0.496165096759796f, 0.499985307455063f, 0.496548563241959f, 0.499988079071045f, + 0.496932059526443f, 0.499990582466125f, 0.497315555810928f, 0.499992787837982f, + 0.497699022293091f, 0.499994695186615f, 0.498082518577576f, 0.499996334314346f, + 0.498466014862061f, 0.499997645616531f, 0.498849511146545f, 0.499998688697815f, + 0.499233007431030f, 0.499999403953552f, 0.499616503715515f, 0.499999850988388f, +}; + + +/** + @par + Generation of realCoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ */ + +const float32_t realCoefB[8192] = { + 0.500000000000000f, 0.500000000000000f, 0.500383496284485f, 0.499999850988388f, + 0.500766992568970f, 0.499999403953552f, 0.501150488853455f, 0.499998688697815f, + 0.501533985137939f, 0.499997645616531f, 0.501917481422424f, 0.499996334314346f, + 0.502300977706909f, 0.499994695186615f, 0.502684473991394f, 0.499992787837982f, + 0.503067970275879f, 0.499990582466125f, 0.503451406955719f, 0.499988079071045f, + 0.503834903240204f, 0.499985307455063f, 0.504218399524689f, 0.499982208013535f, + 0.504601895809174f, 0.499978810548782f, 0.504985332489014f, 0.499975144863129f, + 0.505368828773499f, 0.499971181154251f, 0.505752325057983f, 0.499966919422150f, + 0.506135761737823f, 0.499962359666824f, 0.506519258022308f, 0.499957501888275f, + 0.506902694702148f, 0.499952346086502f, 0.507286131381989f, 0.499946922063828f, + 0.507669627666473f, 0.499941170215607f, 0.508053064346313f, 0.499935150146484f, + 0.508436501026154f, 0.499928832054138f, 0.508819937705994f, 0.499922215938568f, + 0.509203374385834f, 0.499915301799774f, 0.509586811065674f, 0.499908089637756f, + 0.509970188140869f, 0.499900579452515f, 0.510353624820709f, 0.499892801046371f, + 0.510737061500549f, 0.499884694814682f, 0.511120438575745f, 0.499876320362091f, + 0.511503815650940f, 0.499867647886276f, 0.511887252330780f, 0.499858677387238f, + 0.512270629405975f, 0.499849408864975f, 0.512654006481171f, 0.499839842319489f, + 0.513037383556366f, 0.499830007553101f, 0.513420701026917f, 0.499819844961166f, + 0.513804078102112f, 0.499809414148331f, 0.514187395572662f, 0.499798685312271f, + 0.514570772647858f, 0.499787658452988f, 0.514954090118408f, 0.499776333570480f, + 0.515337407588959f, 0.499764710664749f, 0.515720725059509f, 0.499752789735794f, + 0.516103982925415f, 0.499740600585938f, 0.516487300395966f, 0.499728083610535f, + 0.516870558261871f, 0.499715298414230f, 0.517253875732422f, 0.499702215194702f, + 0.517637133598328f, 0.499688833951950f, 0.518020391464233f, 0.499675154685974f, + 0.518403589725494f, 0.499661177396774f, 0.518786847591400f, 0.499646931886673f, + 0.519170045852661f, 0.499632388353348f, 0.519553244113922f, 0.499617516994476f, + 0.519936442375183f, 0.499602377414703f, 0.520319640636444f, 0.499586939811707f, + 0.520702838897705f, 0.499571204185486f, 0.521085977554321f, 0.499555170536041f, + 0.521469116210938f, 0.499538868665695f, 0.521852254867554f, 0.499522238969803f, + 0.522235393524170f, 0.499505341053009f, 0.522618472576141f, 0.499488145112991f, + 0.523001611232758f, 0.499470651149750f, 0.523384690284729f, 0.499452859163284f, + 0.523767769336700f, 0.499434769153595f, 0.524150788784027f, 0.499416410923004f, + 0.524533808231354f, 0.499397724866867f, 0.524916887283325f, 0.499378770589828f, + 0.525299847126007f, 0.499359518289566f, 0.525682866573334f, 0.499339967966080f, + 0.526065826416016f, 0.499320119619370f, 0.526448845863342f, 0.499299973249435f, + 0.526831746101379f, 0.499279528856277f, 0.527214705944061f, 0.499258816242218f, + 0.527597606182098f, 0.499237775802612f, 0.527980506420136f, 0.499216467142105f, + 0.528363406658173f, 0.499194860458374f, 0.528746306896210f, 0.499172955751419f, + 0.529129147529602f, 0.499150782823563f, 0.529511988162994f, 0.499128282070160f, + 0.529894769191742f, 0.499105513095856f, 0.530277609825134f, 0.499082416296005f, + 0.530660390853882f, 0.499059051275253f, 0.531043112277985f, 0.499035388231277f, + 0.531425893306732f, 0.499011427164078f, 0.531808614730835f, 0.498987197875977f, + 0.532191336154938f, 0.498962640762329f, 0.532573997974396f, 0.498937815427780f, + 0.532956659793854f, 0.498912662267685f, 0.533339321613312f, 0.498887240886688f, + 0.533721983432770f, 0.498861521482468f, 0.534104585647583f, 0.498835533857346f, + 0.534487187862396f, 0.498809218406677f, 0.534869730472565f, 0.498782604932785f, + 0.535252273082733f, 0.498755723237991f, 0.535634815692902f, 0.498728543519974f, + 0.536017298698425f, 0.498701065778732f, 0.536399841308594f, 0.498673290014267f, + 0.536782264709473f, 0.498645216226578f, 0.537164747714996f, 0.498616874217987f, + 0.537547171115875f, 0.498588204383850f, 0.537929534912109f, 0.498559266328812f, + 0.538311958312988f, 0.498530030250549f, 0.538694262504578f, 0.498500496149063f, + 0.539076626300812f, 0.498470664024353f, 0.539458930492401f, 0.498440563678741f, + 0.539841234683990f, 0.498410135507584f, 0.540223479270935f, 0.498379439115524f, + 0.540605723857880f, 0.498348444700241f, 0.540987968444824f, 0.498317152261734f, + 0.541370153427124f, 0.498285561800003f, 0.541752278804779f, 0.498253703117371f, + 0.542134463787079f, 0.498221516609192f, 0.542516589164734f, 0.498189061880112f, + 0.542898654937744f, 0.498156309127808f, 0.543280720710754f, 0.498123258352280f, + 0.543662786483765f, 0.498089909553528f, 0.544044792652130f, 0.498056292533875f, + 0.544426798820496f, 0.498022347688675f, 0.544808745384216f, 0.497988134622574f, + 0.545190691947937f, 0.497953623533249f, 0.545572578907013f, 0.497918814420700f, + 0.545954465866089f, 0.497883707284927f, 0.546336352825165f, 0.497848302125931f, + 0.546718180179596f, 0.497812628746033f, 0.547099947929382f, 0.497776657342911f, + 0.547481775283813f, 0.497740387916565f, 0.547863483428955f, 0.497703820466995f, + 0.548245191574097f, 0.497666954994202f, 0.548626899719238f, 0.497629791498184f, + 0.549008548259735f, 0.497592359781265f, 0.549390196800232f, 0.497554630041122f, + 0.549771785736084f, 0.497516602277756f, 0.550153374671936f, 0.497478276491165f, + 0.550534904003143f, 0.497439652681351f, 0.550916433334351f, 0.497400760650635f, + 0.551297962665558f, 0.497361570596695f, 0.551679372787476f, 0.497322082519531f, + 0.552060842514038f, 0.497282296419144f, 0.552442193031311f, 0.497242212295532f, + 0.552823603153229f, 0.497201830148697f, 0.553204894065857f, 0.497161179780960f, + 0.553586184978485f, 0.497120231389999f, 0.553967475891113f, 0.497078984975815f, + 0.554348707199097f, 0.497037440538406f, 0.554729938507080f, 0.496995598077774f, + 0.555111110210419f, 0.496953487396240f, 0.555492222309113f, 0.496911078691483f, + 0.555873334407806f, 0.496868371963501f, 0.556254446506500f, 0.496825367212296f, + 0.556635499000549f, 0.496782064437866f, 0.557016491889954f, 0.496738493442535f, + 0.557397484779358f, 0.496694594621658f, 0.557778418064117f, 0.496650427579880f, + 0.558159291744232f, 0.496605962514877f, 0.558540165424347f, 0.496561229228973f, + 0.558921039104462f, 0.496516168117523f, 0.559301853179932f, 0.496470838785172f, + 0.559682607650757f, 0.496425211429596f, 0.560063362121582f, 0.496379286050797f, + 0.560444056987762f, 0.496333062648773f, 0.560824692249298f, 0.496286571025848f, + 0.561205327510834f, 0.496239781379700f, 0.561585903167725f, 0.496192663908005f, + 0.561966478824615f, 0.496145308017731f, 0.562346994876862f, 0.496097624301910f, + 0.562727510929108f, 0.496049642562866f, 0.563107967376709f, 0.496001392602921f, + 0.563488364219666f, 0.495952844619751f, 0.563868701457977f, 0.495903998613358f, + 0.564249038696289f, 0.495854884386063f, 0.564629375934601f, 0.495805442333221f, + 0.565009593963623f, 0.495755732059479f, 0.565389811992645f, 0.495705723762512f, + 0.565770030021667f, 0.495655417442322f, 0.566150128841400f, 0.495604842901230f, + 0.566530287265778f, 0.495553970336914f, 0.566910326480865f, 0.495502769947052f, + 0.567290365695953f, 0.495451331138611f, 0.567670345306396f, 0.495399564504623f, + 0.568050265312195f, 0.495347499847412f, 0.568430185317993f, 0.495295166969299f, + 0.568810045719147f, 0.495242536067963f, 0.569189906120300f, 0.495189607143402f, + 0.569569647312164f, 0.495136409997940f, 0.569949388504028f, 0.495082914829254f, + 0.570329129695892f, 0.495029091835022f, 0.570708811283112f, 0.494975030422211f, + 0.571088373661041f, 0.494920641183853f, 0.571467995643616f, 0.494865983724594f, + 0.571847498416901f, 0.494810998439789f, 0.572227001190186f, 0.494755744934082f, + 0.572606444358826f, 0.494700223207474f, 0.572985887527466f, 0.494644373655319f, + 0.573365211486816f, 0.494588255882263f, 0.573744535446167f, 0.494531840085983f, + 0.574123859405518f, 0.494475126266479f, 0.574503064155579f, 0.494418144226074f, + 0.574882268905640f, 0.494360834360123f, 0.575261414051056f, 0.494303256273270f, + 0.575640499591827f, 0.494245409965515f, 0.576019585132599f, 0.494187235832214f, + 0.576398611068726f, 0.494128793478012f, 0.576777577400208f, 0.494070053100586f, + 0.577156484127045f, 0.494011014699936f, 0.577535390853882f, 0.493951678276062f, + 0.577914178371429f, 0.493892073631287f, 0.578292965888977f, 0.493832170963287f, + 0.578671753406525f, 0.493771970272064f, 0.579050421714783f, 0.493711471557617f, + 0.579429090023041f, 0.493650704622269f, 0.579807698726654f, 0.493589639663696f, + 0.580186247825623f, 0.493528276681900f, 0.580564737319946f, 0.493466645479202f, + 0.580943167209625f, 0.493404686450958f, 0.581321597099304f, 0.493342459201813f, + 0.581699967384338f, 0.493279963731766f, 0.582078278064728f, 0.493217140436172f, + 0.582456588745117f, 0.493154048919678f, 0.582834780216217f, 0.493090659379959f, + 0.583212971687317f, 0.493026971817017f, 0.583591103553772f, 0.492963016033173f, + 0.583969175815582f, 0.492898762226105f, 0.584347188472748f, 0.492834210395813f, + 0.584725141525269f, 0.492769360542297f, 0.585103094577789f, 0.492704242467880f, + 0.585480928421021f, 0.492638826370239f, 0.585858762264252f, 0.492573112249374f, + 0.586236536502838f, 0.492507129907608f, 0.586614251136780f, 0.492440819740295f, + 0.586991965770721f, 0.492374241352081f, 0.587369561195374f, 0.492307394742966f, + 0.587747097015381f, 0.492240220308304f, 0.588124632835388f, 0.492172777652740f, + 0.588502109050751f, 0.492105036973953f, 0.588879525661469f, 0.492037028074265f, + 0.589256882667542f, 0.491968721151352f, 0.589634180068970f, 0.491900116205215f, + 0.590011477470398f, 0.491831213235855f, 0.590388655662537f, 0.491762012243271f, + 0.590765833854675f, 0.491692543029785f, 0.591142892837524f, 0.491622805595398f, + 0.591519951820374f, 0.491552740335464f, 0.591896951198578f, 0.491482406854630f, + 0.592273890972137f, 0.491411775350571f, 0.592650771141052f, 0.491340845823288f, + 0.593027591705322f, 0.491269648075104f, 0.593404352664948f, 0.491198152303696f, + 0.593781054019928f, 0.491126358509064f, 0.594157755374908f, 0.491054296493530f, + 0.594534337520599f, 0.490981936454773f, 0.594910860061646f, 0.490909278392792f, + 0.595287382602692f, 0.490836352109909f, 0.595663845539093f, 0.490763127803802f, + 0.596040189266205f, 0.490689605474472f, 0.596416532993317f, 0.490615785121918f, + 0.596792817115784f, 0.490541696548462f, 0.597168982028961f, 0.490467309951782f, + 0.597545146942139f, 0.490392625331879f, 0.597921252250671f, 0.490317672491074f, + 0.598297297954559f, 0.490242421627045f, 0.598673284053802f, 0.490166902542114f, + 0.599049210548401f, 0.490091055631638f, 0.599425077438354f, 0.490014940500259f, + 0.599800884723663f, 0.489938557147980f, 0.600176632404327f, 0.489861875772476f, + 0.600552320480347f, 0.489784896373749f, 0.600927948951721f, 0.489707618951797f, + 0.601303517818451f, 0.489630073308945f, 0.601679027080536f, 0.489552229642868f, + 0.602054476737976f, 0.489474087953568f, 0.602429866790771f, 0.489395678043365f, + 0.602805197238922f, 0.489316970109940f, 0.603180468082428f, 0.489237964153290f, + 0.603555679321289f, 0.489158689975739f, 0.603930830955505f, 0.489079117774963f, + 0.604305922985077f, 0.488999247550964f, 0.604680955410004f, 0.488919109106064f, + 0.605055928230286f, 0.488838672637939f, 0.605430841445923f, 0.488757967948914f, + 0.605805635452271f, 0.488676935434341f, 0.606180429458618f, 0.488595664501190f, + 0.606555163860321f, 0.488514065742493f, 0.606929838657379f, 0.488432198762894f, + 0.607304394245148f, 0.488350033760071f, 0.607678949832916f, 0.488267600536346f, + 0.608053386211395f, 0.488184869289398f, 0.608427822589874f, 0.488101840019226f, + 0.608802139759064f, 0.488018542528152f, 0.609176397323608f, 0.487934947013855f, + 0.609550595283508f, 0.487851053476334f, 0.609924793243408f, 0.487766891717911f, + 0.610298871994019f, 0.487682431936264f, 0.610672831535339f, 0.487597703933716f, + 0.611046791076660f, 0.487512677907944f, 0.611420691013336f, 0.487427353858948f, + 0.611794531345367f, 0.487341761589050f, 0.612168252468109f, 0.487255871295929f, + 0.612541973590851f, 0.487169682979584f, 0.612915575504303f, 0.487083226442337f, + 0.613289117813110f, 0.486996471881866f, 0.613662600517273f, 0.486909449100494f, + 0.614036023616791f, 0.486822128295898f, 0.614409387111664f, 0.486734509468079f, + 0.614782691001892f, 0.486646622419357f, 0.615155875682831f, 0.486558437347412f, + 0.615529060363770f, 0.486469984054565f, 0.615902125835419f, 0.486381232738495f, + 0.616275131702423f, 0.486292183399200f, 0.616648077964783f, 0.486202865839005f, + 0.617020964622498f, 0.486113250255585f, 0.617393791675568f, 0.486023366451263f, + 0.617766559123993f, 0.485933154821396f, 0.618139207363129f, 0.485842704772949f, + 0.618511795997620f, 0.485751956701279f, 0.618884325027466f, 0.485660910606384f, + 0.619256794452667f, 0.485569566488266f, 0.619629204273224f, 0.485477954149246f, + 0.620001494884491f, 0.485386073589325f, 0.620373785495758f, 0.485293895006180f, + 0.620745956897736f, 0.485201418399811f, 0.621118068695068f, 0.485108673572540f, + 0.621490061283112f, 0.485015630722046f, 0.621862053871155f, 0.484922289848328f, + 0.622233927249908f, 0.484828680753708f, 0.622605800628662f, 0.484734803438187f, + 0.622977554798126f, 0.484640628099442f, 0.623349189758301f, 0.484546154737473f, + 0.623720824718475f, 0.484451413154602f, 0.624092340469360f, 0.484356373548508f, + 0.624463796615601f, 0.484261035919189f, 0.624835193157196f, 0.484165430068970f, + 0.625206530094147f, 0.484069555997849f, 0.625577747821808f, 0.483973383903503f, + 0.625948905944824f, 0.483876913785934f, 0.626320004463196f, 0.483780175447464f, + 0.626691043376923f, 0.483683139085770f, 0.627061963081360f, 0.483585834503174f, + 0.627432823181152f, 0.483488231897354f, 0.627803623676300f, 0.483390361070633f, + 0.628174364566803f, 0.483292192220688f, 0.628544986248016f, 0.483193725347519f, + 0.628915548324585f, 0.483094990253448f, 0.629286050796509f, 0.482995986938477f, + 0.629656434059143f, 0.482896685600281f, 0.630026817321777f, 0.482797086238861f, + 0.630397081375122f, 0.482697218656540f, 0.630767226219177f, 0.482597053050995f, + 0.631137371063232f, 0.482496619224548f, 0.631507396697998f, 0.482395917177200f, + 0.631877362728119f, 0.482294887304306f, 0.632247209548950f, 0.482193619012833f, + 0.632616996765137f, 0.482092022895813f, 0.632986724376678f, 0.481990188360214f, + 0.633356392383575f, 0.481888025999069f, 0.633725941181183f, 0.481785595417023f, + 0.634095430374146f, 0.481682896614075f, 0.634464859962463f, 0.481579899787903f, + 0.634834170341492f, 0.481476634740829f, 0.635203421115875f, 0.481373071670532f, + 0.635572552680969f, 0.481269240379334f, 0.635941684246063f, 0.481165111064911f, + 0.636310696601868f, 0.481060713529587f, 0.636679589748383f, 0.480956017971039f, + 0.637048482894897f, 0.480851024389267f, 0.637417197227478f, 0.480745792388916f, + 0.637785911560059f, 0.480640232563019f, 0.638154506683350f, 0.480534434318542f, + 0.638523042201996f, 0.480428308248520f, 0.638891458511353f, 0.480321943759918f, + 0.639259815216064f, 0.480215251445770f, 0.639628112316132f, 0.480108320713043f, + 0.639996349811554f, 0.480001062154770f, 0.640364408493042f, 0.479893565177917f, + 0.640732467174530f, 0.479785770177841f, 0.641100406646729f, 0.479677677154541f, + 0.641468286514282f, 0.479569315910339f, 0.641836047172546f, 0.479460656642914f, + 0.642203748226166f, 0.479351729154587f, 0.642571389675140f, 0.479242533445358f, + 0.642938911914825f, 0.479133039712906f, 0.643306374549866f, 0.479023247957230f, + 0.643673717975616f, 0.478913217782974f, 0.644041001796722f, 0.478802859783173f, + 0.644408226013184f, 0.478692263364792f, 0.644775331020355f, 0.478581339120865f, + 0.645142316818237f, 0.478470176458359f, 0.645509302616119f, 0.478358715772629f, + 0.645876109600067f, 0.478246957063675f, 0.646242916584015f, 0.478134930133820f, + 0.646609604358673f, 0.478022634983063f, 0.646976172924042f, 0.477910041809082f, + 0.647342681884766f, 0.477797180414200f, 0.647709131240845f, 0.477684020996094f, + 0.648075461387634f, 0.477570593357086f, 0.648441672325134f, 0.477456867694855f, + 0.648807883262634f, 0.477342873811722f, 0.649173915386200f, 0.477228611707687f, + 0.649539887905121f, 0.477114051580429f, 0.649905800819397f, 0.476999223232269f, + 0.650271594524384f, 0.476884096860886f, 0.650637328624725f, 0.476768702268600f, + 0.651003003120422f, 0.476653009653091f, 0.651368498802185f, 0.476537048816681f, + 0.651733994483948f, 0.476420819759369f, 0.652099311351776f, 0.476304292678833f, + 0.652464628219604f, 0.476187497377396f, 0.652829825878143f, 0.476070433855057f, + 0.653194904327393f, 0.475953072309494f, 0.653559923171997f, 0.475835442543030f, + 0.653924822807312f, 0.475717514753342f, 0.654289662837982f, 0.475599318742752f, + 0.654654383659363f, 0.475480824708939f, 0.655019044876099f, 0.475362062454224f, + 0.655383586883545f, 0.475243031978607f, 0.655748009681702f, 0.475123733282089f, + 0.656112432479858f, 0.475004136562347f, 0.656476676464081f, 0.474884241819382f, + 0.656840860843658f, 0.474764078855515f, 0.657204985618591f, 0.474643647670746f, + 0.657568991184235f, 0.474522948265076f, 0.657932877540588f, 0.474401950836182f, + 0.658296704292297f, 0.474280685186386f, 0.658660411834717f, 0.474159121513367f, + 0.659024059772491f, 0.474037289619446f, 0.659387588500977f, 0.473915189504623f, + 0.659750998020172f, 0.473792791366577f, 0.660114347934723f, 0.473670125007629f, + 0.660477638244629f, 0.473547190427780f, 0.660840749740601f, 0.473423957824707f, + 0.661203861236572f, 0.473300457000732f, 0.661566793918610f, 0.473176687955856f, + 0.661929666996002f, 0.473052620887756f, 0.662292480468750f, 0.472928285598755f, + 0.662655174732208f, 0.472803652286530f, 0.663017749786377f, 0.472678780555725f, + 0.663380205631256f, 0.472553610801697f, 0.663742601871490f, 0.472428143024445f, + 0.664104938507080f, 0.472302407026291f, 0.664467096328735f, 0.472176402807236f, + 0.664829254150391f, 0.472050130367279f, 0.665191233158112f, 0.471923559904099f, + 0.665553152561188f, 0.471796721220016f, 0.665914952754974f, 0.471669614315033f, + 0.666276693344116f, 0.471542209386826f, 0.666638314723969f, 0.471414536237717f, + 0.666999816894531f, 0.471286594867706f, 0.667361259460449f, 0.471158385276794f, + 0.667722582817078f, 0.471029877662659f, 0.668083786964417f, 0.470901101827621f, + 0.668444931507111f, 0.470772027969360f, 0.668805956840515f, 0.470642685890198f, + 0.669166862964630f, 0.470513075590134f, 0.669527709484100f, 0.470383197069168f, + 0.669888436794281f, 0.470253020524979f, 0.670249044895172f, 0.470122605562210f, + 0.670609593391418f, 0.469991862773895f, 0.670970022678375f, 0.469860881567001f, + 0.671330332756042f, 0.469729602336884f, 0.671690583229065f, 0.469598054885864f, + 0.672050714492798f, 0.469466239213943f, 0.672410726547241f, 0.469334155321121f, + 0.672770678997040f, 0.469201773405075f, 0.673130512237549f, 0.469069123268127f, + 0.673490226268768f, 0.468936175107956f, 0.673849821090698f, 0.468802988529205f, + 0.674209356307983f, 0.468669503927231f, 0.674568772315979f, 0.468535751104355f, + 0.674928069114685f, 0.468401730060577f, 0.675287246704102f, 0.468267410993576f, + 0.675646364688873f, 0.468132823705673f, 0.676005363464355f, 0.467997968196869f, + 0.676364302635193f, 0.467862844467163f, 0.676723062992096f, 0.467727422714233f, + 0.677081763744354f, 0.467591762542725f, 0.677440345287323f, 0.467455804347992f, + 0.677798807621002f, 0.467319577932358f, 0.678157210350037f, 0.467183053493500f, + 0.678515493869781f, 0.467046260833740f, 0.678873658180237f, 0.466909229755402f, + 0.679231703281403f, 0.466771900653839f, 0.679589688777924f, 0.466634273529053f, + 0.679947495460510f, 0.466496407985687f, 0.680305242538452f, 0.466358244419098f, + 0.680662930011749f, 0.466219812631607f, 0.681020438671112f, 0.466081112623215f, + 0.681377887725830f, 0.465942144393921f, 0.681735157966614f, 0.465802878141403f, + 0.682092368602753f, 0.465663343667984f, 0.682449519634247f, 0.465523540973663f, + 0.682806491851807f, 0.465383470058441f, 0.683163404464722f, 0.465243130922318f, + 0.683520197868347f, 0.465102523565292f, 0.683876872062683f, 0.464961618185043f, + 0.684233427047729f, 0.464820444583893f, 0.684589862823486f, 0.464679002761841f, + 0.684946238994598f, 0.464537292718887f, 0.685302436351776f, 0.464395314455032f, + 0.685658574104309f, 0.464253038167953f, 0.686014592647552f, 0.464110493659973f, + 0.686370551586151f, 0.463967710733414f, 0.686726331710815f, 0.463824629783630f, + 0.687082052230835f, 0.463681250810623f, 0.687437593936920f, 0.463537633419037f, + 0.687793076038361f, 0.463393747806549f, 0.688148438930511f, 0.463249564170837f, + 0.688503682613373f, 0.463105112314224f, 0.688858866691589f, 0.462960392236710f, + 0.689213871955872f, 0.462815403938293f, 0.689568817615509f, 0.462670147418976f, + 0.689923584461212f, 0.462524622678757f, 0.690278291702271f, 0.462378799915314f, + 0.690632879734039f, 0.462232738733292f, 0.690987348556519f, 0.462086379528046f, + 0.691341698169708f, 0.461939752101898f, 0.691695988178253f, 0.461792886257172f, + 0.692050099372864f, 0.461645722389221f, 0.692404091358185f, 0.461498260498047f, + 0.692758023738861f, 0.461350560188293f, 0.693111836910248f, 0.461202591657639f, + 0.693465530872345f, 0.461054325103760f, 0.693819046020508f, 0.460905820131302f, + 0.694172501564026f, 0.460757017135620f, 0.694525837898254f, 0.460607945919037f, + 0.694879114627838f, 0.460458606481552f, 0.695232212543488f, 0.460309028625488f, + 0.695585191249847f, 0.460159152746201f, 0.695938050746918f, 0.460008978843689f, + 0.696290850639343f, 0.459858566522598f, 0.696643471717834f, 0.459707885980606f, + 0.696996033191681f, 0.459556937217712f, 0.697348415851593f, 0.459405690431595f, + 0.697700738906860f, 0.459254205226898f, 0.698052942752838f, 0.459102421998978f, + 0.698404967784882f, 0.458950400352478f, 0.698756933212280f, 0.458798080682755f, + 0.699108779430389f, 0.458645492792130f, 0.699460506439209f, 0.458492636680603f, + 0.699812114238739f, 0.458339542150497f, 0.700163602828979f, 0.458186149597168f, + 0.700514972209930f, 0.458032488822937f, 0.700866222381592f, 0.457878559827805f, + 0.701217353343964f, 0.457724362611771f, 0.701568365097046f, 0.457569897174835f, + 0.701919257640839f, 0.457415163516998f, 0.702270030975342f, 0.457260161638260f, + 0.702620685100555f, 0.457104891538620f, 0.702971220016479f, 0.456949323415756f, + 0.703321635723114f, 0.456793516874313f, 0.703671932220459f, 0.456637442111969f, + 0.704022109508514f, 0.456481099128723f, 0.704372167587280f, 0.456324487924576f, + 0.704722046852112f, 0.456167578697205f, 0.705071866512299f, 0.456010431051254f, + 0.705421566963196f, 0.455853015184402f, 0.705771148204803f, 0.455695331096649f, + 0.706120610237122f, 0.455537378787994f, 0.706469953060150f, 0.455379128456116f, + 0.706819176673889f, 0.455220639705658f, 0.707168221473694f, 0.455061882734299f, + 0.707517206668854f, 0.454902857542038f, 0.707866072654724f, 0.454743564128876f, + 0.708214759826660f, 0.454584002494812f, 0.708563387393951f, 0.454424172639847f, + 0.708911836147308f, 0.454264044761658f, 0.709260225296021f, 0.454103678464890f, + 0.709608435630798f, 0.453943043947220f, 0.709956526756287f, 0.453782171010971f, + 0.710304558277130f, 0.453621000051498f, 0.710652410984039f, 0.453459560871124f, + 0.711000144481659f, 0.453297853469849f, 0.711347758769989f, 0.453135877847672f, + 0.711695253849030f, 0.452973634004593f, 0.712042629718781f, 0.452811151742935f, + 0.712389826774597f, 0.452648371458054f, 0.712736964225769f, 0.452485352754593f, + 0.713083922863007f, 0.452322036027908f, 0.713430821895599f, 0.452158480882645f, + 0.713777542114258f, 0.451994657516479f, 0.714124143123627f, 0.451830536127090f, + 0.714470624923706f, 0.451666176319122f, 0.714816987514496f, 0.451501548290253f, + 0.715163230895996f, 0.451336652040482f, 0.715509355068207f, 0.451171487569809f, + 0.715855300426483f, 0.451006084680557f, 0.716201186180115f, 0.450840383768082f, + 0.716546893119812f, 0.450674414634705f, 0.716892480850220f, 0.450508207082748f, + 0.717238008975983f, 0.450341701507568f, 0.717583298683167f, 0.450174957513809f, + 0.717928528785706f, 0.450007945299149f, 0.718273639678955f, 0.449840664863586f, + 0.718618571758270f, 0.449673116207123f, 0.718963444232941f, 0.449505299329758f, + 0.719308137893677f, 0.449337244033813f, 0.719652712345123f, 0.449168890714645f, + 0.719997107982636f, 0.449000298976898f, 0.720341444015503f, 0.448831409215927f, + 0.720685660839081f, 0.448662281036377f, 0.721029698848724f, 0.448492884635925f, + 0.721373617649078f, 0.448323249816895f, 0.721717417240143f, 0.448153316974640f, + 0.722061097621918f, 0.447983115911484f, 0.722404599189758f, 0.447812676429749f, + 0.722747981548309f, 0.447641968727112f, 0.723091304302216f, 0.447470992803574f, + 0.723434448242188f, 0.447299748659134f, 0.723777413368225f, 0.447128236293793f, + 0.724120318889618f, 0.446956485509872f, 0.724463045597076f, 0.446784436702728f, + 0.724805653095245f, 0.446612149477005f, 0.725148141384125f, 0.446439594030380f, + 0.725490510463715f, 0.446266770362854f, 0.725832700729370f, 0.446093708276749f, + 0.726174771785736f, 0.445920348167419f, 0.726516723632813f, 0.445746749639511f, + 0.726858556270599f, 0.445572882890701f, 0.727200269699097f, 0.445398747920990f, + 0.727541804313660f, 0.445224374532700f, 0.727883219718933f, 0.445049703121185f, + 0.728224515914917f, 0.444874793291092f, 0.728565633296967f, 0.444699615240097f, + 0.728906631469727f, 0.444524168968201f, 0.729247510433197f, 0.444348484277725f, + 0.729588270187378f, 0.444172531366348f, 0.729928910732269f, 0.443996280431747f, + 0.730269372463226f, 0.443819820880890f, 0.730609714984894f, 0.443643063306808f, + 0.730949878692627f, 0.443466067314148f, 0.731289982795715f, 0.443288803100586f, + 0.731629908084869f, 0.443111270666122f, 0.731969714164734f, 0.442933470010757f, + 0.732309341430664f, 0.442755430936813f, 0.732648849487305f, 0.442577123641968f, + 0.732988238334656f, 0.442398548126221f, 0.733327507972717f, 0.442219734191895f, + 0.733666598796844f, 0.442040622234344f, 0.734005570411682f, 0.441861271858215f, + 0.734344422817230f, 0.441681683063507f, 0.734683096408844f, 0.441501796245575f, + 0.735021650791168f, 0.441321671009064f, 0.735360085964203f, 0.441141277551651f, + 0.735698342323303f, 0.440960645675659f, 0.736036539077759f, 0.440779715776443f, + 0.736374497413635f, 0.440598547458649f, 0.736712396144867f, 0.440417140722275f, + 0.737050116062164f, 0.440235435962677f, 0.737387716770172f, 0.440053492784500f, + 0.737725138664246f, 0.439871311187744f, 0.738062441349030f, 0.439688831567764f, + 0.738399624824524f, 0.439506113529205f, 0.738736629486084f, 0.439323127269745f, + 0.739073514938354f, 0.439139902591705f, 0.739410281181335f, 0.438956409692764f, + 0.739746868610382f, 0.438772648572922f, 0.740083336830139f, 0.438588619232178f, + 0.740419685840607f, 0.438404351472855f, 0.740755856037140f, 0.438219845294952f, + 0.741091907024384f, 0.438035041093826f, 0.741427779197693f, 0.437849998474121f, + 0.741763532161713f, 0.437664687633514f, 0.742099165916443f, 0.437479138374329f, + 0.742434620857239f, 0.437293320894241f, 0.742769956588745f, 0.437107264995575f, + 0.743105113506317f, 0.436920911073685f, 0.743440151214600f, 0.436734348535538f, + 0.743775069713593f, 0.436547487974167f, 0.744109809398651f, 0.436360388994217f, + 0.744444429874420f, 0.436173021793365f, 0.744778931140900f, 0.435985416173935f, + 0.745113253593445f, 0.435797542333603f, 0.745447397232056f, 0.435609430074692f, + 0.745781481266022f, 0.435421019792557f, 0.746115326881409f, 0.435232400894165f, + 0.746449112892151f, 0.435043483972549f, 0.746782720088959f, 0.434854328632355f, + 0.747116148471832f, 0.434664934873581f, 0.747449457645416f, 0.434475272893906f, + 0.747782647609711f, 0.434285342693329f, 0.748115658760071f, 0.434095174074173f, + 0.748448550701141f, 0.433904737234116f, 0.748781263828278f, 0.433714061975479f, + 0.749113857746124f, 0.433523118495941f, 0.749446272850037f, 0.433331936597824f, + 0.749778568744659f, 0.433140486478806f, 0.750110685825348f, 0.432948768138886f, + 0.750442683696747f, 0.432756811380386f, 0.750774562358856f, 0.432564586400986f, + 0.751106262207031f, 0.432372123003006f, 0.751437783241272f, 0.432179391384125f, + 0.751769185066223f, 0.431986421346664f, 0.752100467681885f, 0.431793183088303f, + 0.752431571483612f, 0.431599706411362f, 0.752762496471405f, 0.431405961513519f, + 0.753093302249908f, 0.431211978197098f, 0.753423988819122f, 0.431017726659775f, + 0.753754496574402f, 0.430823236703873f, 0.754084885120392f, 0.430628478527069f, + 0.754415094852448f, 0.430433481931686f, 0.754745125770569f, 0.430238217115402f, + 0.755075037479401f, 0.430042684078217f, 0.755404829978943f, 0.429846942424774f, + 0.755734443664551f, 0.429650902748108f, 0.756063878536224f, 0.429454624652863f, + 0.756393194198608f, 0.429258108139038f, 0.756722390651703f, 0.429061323404312f, + 0.757051348686218f, 0.428864300251007f, 0.757380247116089f, 0.428667008876801f, + 0.757708966732025f, 0.428469479084015f, 0.758037507534027f, 0.428271710872650f, + 0.758365929126740f, 0.428073674440384f, 0.758694171905518f, 0.427875369787216f, + 0.759022235870361f, 0.427676826715469f, 0.759350180625916f, 0.427478045225143f, + 0.759678006172180f, 0.427278995513916f, 0.760005652904511f, 0.427079707384110f, + 0.760333120822906f, 0.426880151033401f, 0.760660469532013f, 0.426680356264114f, + 0.760987639427185f, 0.426480293273926f, 0.761314690113068f, 0.426279991865158f, + 0.761641561985016f, 0.426079452037811f, 0.761968255043030f, 0.425878643989563f, + 0.762294828891754f, 0.425677597522736f, 0.762621283531189f, 0.425476282835007f, + 0.762947499752045f, 0.425274729728699f, 0.763273596763611f, 0.425072938203812f, + 0.763599574565887f, 0.424870878458023f, 0.763925373554230f, 0.424668580293655f, + 0.764250993728638f, 0.424466013908386f, 0.764576494693756f, 0.424263238906860f, + 0.764901816844940f, 0.424060165882111f, 0.765226960182190f, 0.423856884241104f, + 0.765551984310150f, 0.423653304576874f, 0.765876889228821f, 0.423449516296387f, + 0.766201555728912f, 0.423245459794998f, 0.766526103019714f, 0.423041164875031f, + 0.766850471496582f, 0.422836631536484f, 0.767174720764160f, 0.422631829977036f, + 0.767498791217804f, 0.422426789999008f, 0.767822742462158f, 0.422221481800079f, + 0.768146514892578f, 0.422015935182571f, 0.768470108509064f, 0.421810150146484f, + 0.768793523311615f, 0.421604126691818f, 0.769116818904877f, 0.421397835016251f, + 0.769439935684204f, 0.421191304922104f, 0.769762933254242f, 0.420984506607056f, + 0.770085752010345f, 0.420777499675751f, 0.770408391952515f, 0.420570224523544f, + 0.770730912685394f, 0.420362681150436f, 0.771053194999695f, 0.420154929161072f, + 0.771375417709351f, 0.419946908950806f, 0.771697402000427f, 0.419738620519638f, + 0.772019267082214f, 0.419530123472214f, 0.772340953350067f, 0.419321358203888f, + 0.772662520408630f, 0.419112354516983f, 0.772983849048615f, 0.418903112411499f, + 0.773305058479309f, 0.418693602085114f, 0.773626148700714f, 0.418483853340149f, + 0.773947000503540f, 0.418273866176605f, 0.774267733097076f, 0.418063640594482f, + 0.774588346481323f, 0.417853146791458f, 0.774908721446991f, 0.417642414569855f, + 0.775228977203369f, 0.417431443929672f, 0.775549054145813f, 0.417220205068588f, + 0.775869011878967f, 0.417008757591248f, 0.776188731193542f, 0.416797041893005f, + 0.776508331298828f, 0.416585087776184f, 0.776827812194824f, 0.416372895240784f, + 0.777147054672241f, 0.416160434484482f, 0.777466177940369f, 0.415947735309601f, + 0.777785122394562f, 0.415734797716141f, 0.778103888034821f, 0.415521621704102f, + 0.778422534465790f, 0.415308207273483f, 0.778741002082825f, 0.415094524621964f, + 0.779059290885925f, 0.414880603551865f, 0.779377400875092f, 0.414666473865509f, + 0.779695332050323f, 0.414452046155930f, 0.780013144016266f, 0.414237409830093f, + 0.780330777168274f, 0.414022535085678f, 0.780648231506348f, 0.413807392120361f, + 0.780965566635132f, 0.413592010736465f, 0.781282722949982f, 0.413376390933990f, + 0.781599700450897f, 0.413160532712936f, 0.781916499137878f, 0.412944436073303f, + 0.782233119010925f, 0.412728071212769f, 0.782549619674683f, 0.412511497735977f, + 0.782865881919861f, 0.412294656038284f, 0.783182024955750f, 0.412077575922012f, + 0.783498048782349f, 0.411860257387161f, 0.783813834190369f, 0.411642700433731f, + 0.784129500389099f, 0.411424905061722f, 0.784444928169250f, 0.411206841468811f, + 0.784760236740112f, 0.410988569259644f, 0.785075426101685f, 0.410770028829575f, + 0.785390377044678f, 0.410551249980927f, 0.785705149173737f, 0.410332232713699f, + 0.786019802093506f, 0.410112977027893f, 0.786334276199341f, 0.409893482923508f, + 0.786648571491241f, 0.409673750400543f, 0.786962687969208f, 0.409453779459000f, + 0.787276685237885f, 0.409233570098877f, 0.787590444087982f, 0.409013092517853f, + 0.787904083728790f, 0.408792406320572f, 0.788217544555664f, 0.408571451902390f, + 0.788530826568604f, 0.408350288867950f, 0.788843929767609f, 0.408128857612610f, + 0.789156913757324f, 0.407907217741013f, 0.789469659328461f, 0.407685309648514f, + 0.789782285690308f, 0.407463163137436f, 0.790094733238220f, 0.407240778207779f, + 0.790407001972198f, 0.407018154859543f, 0.790719091892242f, 0.406795293092728f, + 0.791031002998352f, 0.406572192907333f, 0.791342735290527f, 0.406348884105682f, + 0.791654348373413f, 0.406125307083130f, 0.791965723037720f, 0.405901491641998f, + 0.792276978492737f, 0.405677437782288f, 0.792588055133820f, 0.405453115701675f, + 0.792898952960968f, 0.405228585004807f, 0.793209671974182f, 0.405003815889359f, + 0.793520212173462f, 0.404778808355331f, 0.793830573558807f, 0.404553562402725f, + 0.794140756130219f, 0.404328078031540f, 0.794450819492340f, 0.404102355241776f, + 0.794760644435883f, 0.403876423835754f, 0.795070350170136f, 0.403650224208832f, + 0.795379877090454f, 0.403423786163330f, 0.795689165592194f, 0.403197109699249f, + 0.795998334884644f, 0.402970194816589f, 0.796307325363159f, 0.402743041515350f, + 0.796616137027740f, 0.402515679597855f, 0.796924769878387f, 0.402288049459457f, + 0.797233223915100f, 0.402060180902481f, 0.797541558742523f, 0.401832103729248f, + 0.797849655151367f, 0.401603758335114f, 0.798157572746277f, 0.401375204324722f, + 0.798465371131897f, 0.401146411895752f, 0.798772931098938f, 0.400917351245880f, + 0.799080371856689f, 0.400688081979752f, 0.799387574195862f, 0.400458574295044f, + 0.799694657325745f, 0.400228828191757f, 0.800001561641693f, 0.399998843669891f, + 0.800308227539063f, 0.399768620729446f, 0.800614774227142f, 0.399538189172745f, + 0.800921142101288f, 0.399307489395142f, 0.801227271556854f, 0.399076581001282f, + 0.801533281803131f, 0.398845434188843f, 0.801839113235474f, 0.398614019155502f, + 0.802144765853882f, 0.398382395505905f, 0.802450239658356f, 0.398150533437729f, + 0.802755534648895f, 0.397918462753296f, 0.803060650825500f, 0.397686123847961f, + 0.803365588188171f, 0.397453576326370f, 0.803670346736908f, 0.397220760583878f, + 0.803974866867065f, 0.396987736225128f, 0.804279267787933f, 0.396754473447800f, + 0.804583489894867f, 0.396520972251892f, 0.804887533187866f, 0.396287262439728f, + 0.805191397666931f, 0.396053284406662f, 0.805495083332062f, 0.395819097757339f, + 0.805798590183258f, 0.395584672689438f, 0.806101918220520f, 0.395350009202957f, + 0.806405067443848f, 0.395115107297897f, 0.806707978248596f, 0.394879996776581f, + 0.807010769844055f, 0.394644618034363f, 0.807313382625580f, 0.394409030675888f, + 0.807615816593170f, 0.394173204898834f, 0.807918012142181f, 0.393937170505524f, + 0.808220088481903f, 0.393700867891312f, 0.808521986007690f, 0.393464356660843f, + 0.808823645114899f, 0.393227607011795f, 0.809125185012817f, 0.392990618944168f, + 0.809426486492157f, 0.392753422260284f, 0.809727668762207f, 0.392515957355499f, + 0.810028612613678f, 0.392278283834457f, 0.810329377651215f, 0.392040401697159f, + 0.810629963874817f, 0.391802251338959f, 0.810930430889130f, 0.391563892364502f, + 0.811230659484863f, 0.391325294971466f, 0.811530709266663f, 0.391086459159851f, + 0.811830580234528f, 0.390847414731979f, 0.812130272388458f, 0.390608131885529f, + 0.812429726123810f, 0.390368610620499f, 0.812729060649872f, 0.390128880739212f, + 0.813028216362000f, 0.389888882637024f, 0.813327133655548f, 0.389648675918579f, + 0.813625931739807f, 0.389408260583878f, 0.813924491405487f, 0.389167606830597f, + 0.814222872257233f, 0.388926714658737f, 0.814521074295044f, 0.388685584068298f, + 0.814819097518921f, 0.388444244861603f, 0.815116941928864f, 0.388202667236328f, + 0.815414607524872f, 0.387960851192474f, 0.815712094306946f, 0.387718826532364f, + 0.816009342670441f, 0.387476563453674f, 0.816306471824646f, 0.387234061956406f, + 0.816603362560272f, 0.386991351842880f, 0.816900074481964f, 0.386748403310776f, + 0.817196667194366f, 0.386505216360092f, 0.817493021488190f, 0.386261820793152f, + 0.817789137363434f, 0.386018186807632f, 0.818085134029388f, 0.385774344205856f, + 0.818380951881409f, 0.385530263185501f, 0.818676531314850f, 0.385285943746567f, + 0.818971931934357f, 0.385041415691376f, 0.819267153739929f, 0.384796649217606f, + 0.819562196731567f, 0.384551674127579f, 0.819857060909271f, 0.384306460618973f, + 0.820151746273041f, 0.384061008691788f, 0.820446193218231f, 0.383815348148346f, + 0.820740520954132f, 0.383569449186325f, 0.821034610271454f, 0.383323341608047f, + 0.821328520774841f, 0.383076995611191f, 0.821622252464294f, 0.382830440998077f, + 0.821915745735168f, 0.382583618164063f, 0.822209119796753f, 0.382336616516113f, + 0.822502255439758f, 0.382089376449585f, 0.822795212268829f, 0.381841897964478f, + 0.823087990283966f, 0.381594210863113f, 0.823380589485168f, 0.381346285343170f, + 0.823673009872437f, 0.381098151206970f, 0.823965191841125f, 0.380849778652191f, + 0.824257194995880f, 0.380601197481155f, 0.824549019336700f, 0.380352377891541f, + 0.824840664863586f, 0.380103349685669f, 0.825132071971893f, 0.379854083061218f, + 0.825423359870911f, 0.379604607820511f, 0.825714409351349f, 0.379354894161224f, + 0.826005280017853f, 0.379104942083359f, 0.826295912265778f, 0.378854811191559f, + 0.826586425304413f, 0.378604412078857f, 0.826876699924469f, 0.378353834152222f, + 0.827166795730591f, 0.378102988004684f, 0.827456712722778f, 0.377851963043213f, + 0.827746450901031f, 0.377600699663162f, 0.828035950660706f, 0.377349197864532f, + 0.828325271606445f, 0.377097487449646f, 0.828614413738251f, 0.376845568418503f, + 0.828903317451477f, 0.376593410968781f, 0.829192101955414f, 0.376341015100479f, + 0.829480648040771f, 0.376088410615921f, 0.829769015312195f, 0.375835597515106f, + 0.830057144165039f, 0.375582575798035f, 0.830345153808594f, 0.375329315662384f, + 0.830632925033569f, 0.375075817108154f, 0.830920517444611f, 0.374822109937668f, + 0.831207871437073f, 0.374568194150925f, 0.831495106220245f, 0.374314039945602f, + 0.831782102584839f, 0.374059677124023f, 0.832068860530853f, 0.373805105686188f, + 0.832355499267578f, 0.373550295829773f, 0.832641899585724f, 0.373295277357101f, + 0.832928121089935f, 0.373040050268173f, 0.833214163780212f, 0.372784584760666f, + 0.833499968051910f, 0.372528880834579f, 0.833785593509674f, 0.372272998094559f, + 0.834071040153503f, 0.372016876935959f, 0.834356248378754f, 0.371760547161102f, + 0.834641277790070f, 0.371503978967667f, 0.834926128387451f, 0.371247202157974f, + 0.835210800170898f, 0.370990216732025f, 0.835495233535767f, 0.370732992887497f, + 0.835779488086700f, 0.370475560426712f, 0.836063504219055f, 0.370217919349670f, + 0.836347401142120f, 0.369960039854050f, 0.836631059646606f, 0.369701951742172f, + 0.836914479732513f, 0.369443655014038f, 0.837197780609131f, 0.369185149669647f, + 0.837480843067169f, 0.368926405906677f, 0.837763667106628f, 0.368667453527451f, + 0.838046371936798f, 0.368408292531967f, 0.838328838348389f, 0.368148893117905f, + 0.838611066341400f, 0.367889285087585f, 0.838893175125122f, 0.367629468441010f, + 0.839175045490265f, 0.367369443178177f, 0.839456677436829f, 0.367109179496765f, + 0.839738130569458f, 0.366848707199097f, 0.840019404888153f, 0.366588026285172f, + 0.840300500392914f, 0.366327136754990f, 0.840581357479095f, 0.366066008806229f, + 0.840862035751343f, 0.365804702043533f, 0.841142535209656f, 0.365543156862259f, + 0.841422796249390f, 0.365281373262405f, 0.841702818870544f, 0.365019410848618f, + 0.841982722282410f, 0.364757210016251f, 0.842262387275696f, 0.364494800567627f, + 0.842541813850403f, 0.364232182502747f, 0.842821121215820f, 0.363969355821610f, + 0.843100130558014f, 0.363706320524216f, 0.843379020690918f, 0.363443046808243f, + 0.843657672405243f, 0.363179564476013f, 0.843936145305634f, 0.362915903329849f, + 0.844214379787445f, 0.362651973962784f, 0.844492435455322f, 0.362387865781784f, + 0.844770252704620f, 0.362123548984528f, 0.845047891139984f, 0.361858993768692f, + 0.845325350761414f, 0.361594229936600f, 0.845602571964264f, 0.361329287290573f, + 0.845879614353180f, 0.361064106225967f, 0.846156477928162f, 0.360798716545105f, + 0.846433103084564f, 0.360533088445663f, 0.846709489822388f, 0.360267281532288f, + 0.846985757350922f, 0.360001266002655f, 0.847261726856232f, 0.359735012054443f, + 0.847537577152252f, 0.359468549489975f, 0.847813189029694f, 0.359201908111572f, + 0.848088562488556f, 0.358935028314590f, 0.848363757133484f, 0.358667939901352f, + 0.848638772964478f, 0.358400642871857f, 0.848913550376892f, 0.358133137226105f, + 0.849188148975372f, 0.357865422964096f, 0.849462509155273f, 0.357597470283508f, + 0.849736690521240f, 0.357329338788986f, 0.850010633468628f, 0.357060998678207f, + 0.850284397602081f, 0.356792420148849f, 0.850557923316956f, 0.356523662805557f, + 0.850831270217896f, 0.356254696846008f, 0.851104438304901f, 0.355985492467880f, + 0.851377367973328f, 0.355716109275818f, 0.851650118827820f, 0.355446487665176f, + 0.851922631263733f, 0.355176687240601f, 0.852194905281067f, 0.354906648397446f, + 0.852467060089111f, 0.354636400938034f, 0.852738916873932f, 0.354365974664688f, + 0.853010654449463f, 0.354095309972763f, 0.853282094001770f, 0.353824466466904f, + 0.853553414344788f, 0.353553384542465f, 0.853824436664581f, 0.353282123804092f, + 0.854095339775085f, 0.353010624647141f, 0.854365944862366f, 0.352738946676254f, + 0.854636430740356f, 0.352467030286789f, 0.854906618595123f, 0.352194935083389f, + 0.855176687240601f, 0.351922631263733f, 0.855446517467499f, 0.351650089025497f, + 0.855716109275818f, 0.351377367973328f, 0.855985522270203f, 0.351104438304901f, + 0.856254696846008f, 0.350831300020218f, 0.856523692607880f, 0.350557953119278f, + 0.856792449951172f, 0.350284397602081f, 0.857060968875885f, 0.350010633468628f, + 0.857329368591309f, 0.349736660718918f, 0.857597470283508f, 0.349462509155273f, + 0.857865393161774f, 0.349188119173050f, 0.858133137226105f, 0.348913550376892f, + 0.858400642871857f, 0.348638743162155f, 0.858667910099030f, 0.348363757133484f, + 0.858934998512268f, 0.348088562488556f, 0.859201908111572f, 0.347813159227371f, + 0.859468579292297f, 0.347537547349930f, 0.859735012054443f, 0.347261756658554f, + 0.860001266002655f, 0.346985727548599f, 0.860267281532288f, 0.346709519624710f, + 0.860533118247986f, 0.346433073282242f, 0.860798716545105f, 0.346156448125839f, + 0.861064076423645f, 0.345879614353180f, 0.861329257488251f, 0.345602601766586f, + 0.861594259738922f, 0.345325350761414f, 0.861859023571014f, 0.345047920942307f, + 0.862123548984528f, 0.344770282506943f, 0.862387895584106f, 0.344492435455322f, + 0.862652003765106f, 0.344214379787445f, 0.862915873527527f, 0.343936115503311f, + 0.863179564476013f, 0.343657672405243f, 0.863443076610565f, 0.343379020690918f, + 0.863706290721893f, 0.343100160360336f, 0.863969385623932f, 0.342821091413498f, + 0.864232182502747f, 0.342541843652725f, 0.864494800567627f, 0.342262357473373f, + 0.864757239818573f, 0.341982692480087f, 0.865019381046295f, 0.341702848672867f, + 0.865281403064728f, 0.341422766447067f, 0.865543127059937f, 0.341142505407333f, + 0.865804672241211f, 0.340862035751343f, 0.866066038608551f, 0.340581357479095f, + 0.866327106952667f, 0.340300500392914f, 0.866588056087494f, 0.340019434690475f, + 0.866848707199097f, 0.339738160371780f, 0.867109179496765f, 0.339456677436829f, + 0.867369413375854f, 0.339175015687943f, 0.867629468441010f, 0.338893145322800f, + 0.867889285087585f, 0.338611096143723f, 0.868148922920227f, 0.338328808546066f, + 0.868408262729645f, 0.338046342134476f, 0.868667483329773f, 0.337763696908951f, + 0.868926405906677f, 0.337480813264847f, 0.869185149669647f, 0.337197750806808f, + 0.869443655014038f, 0.336914509534836f, 0.869701981544495f, 0.336631029844284f, + 0.869960069656372f, 0.336347371339798f, 0.870217919349670f, 0.336063534021378f, + 0.870475590229034f, 0.335779488086700f, 0.870733022689819f, 0.335495233535767f, + 0.870990216732025f, 0.335210770368576f, 0.871247172355652f, 0.334926128387451f, + 0.871503949165344f, 0.334641307592392f, 0.871760547161102f, 0.334356248378754f, + 0.872016847133636f, 0.334071010351181f, 0.872272968292236f, 0.333785593509674f, + 0.872528910636902f, 0.333499968051910f, 0.872784554958344f, 0.333214133977890f, + 0.873040020465851f, 0.332928121089935f, 0.873295307159424f, 0.332641899585724f, + 0.873550295829773f, 0.332355499267578f, 0.873805105686188f, 0.332068890333176f, + 0.874059677124023f, 0.331782072782516f, 0.874314069747925f, 0.331495076417923f, + 0.874568223953247f, 0.331207901239395f, 0.874822139739990f, 0.330920487642288f, + 0.875075817108154f, 0.330632925033569f, 0.875329315662384f, 0.330345153808594f, + 0.875582575798035f, 0.330057173967361f, 0.875835597515106f, 0.329769015312195f, + 0.876088440418243f, 0.329480648040771f, 0.876341044902802f, 0.329192101955414f, + 0.876593410968781f, 0.328903347253799f, 0.876845538616180f, 0.328614413738251f, + 0.877097487449646f, 0.328325271606445f, 0.877349197864532f, 0.328035950660706f, + 0.877600669860840f, 0.327746421098709f, 0.877851963043213f, 0.327456712722778f, + 0.878103017807007f, 0.327166795730591f, 0.878353834152222f, 0.326876699924469f, + 0.878604412078857f, 0.326586425304413f, 0.878854811191559f, 0.326295942068100f, + 0.879104971885681f, 0.326005280017853f, 0.879354894161224f, 0.325714409351349f, + 0.879604578018188f, 0.325423330068588f, 0.879854083061218f, 0.325132101774216f, + 0.880103349685669f, 0.324840664863586f, 0.880352377891541f, 0.324549019336700f, + 0.880601167678833f, 0.324257194995880f, 0.880849778652191f, 0.323965191841125f, + 0.881098151206970f, 0.323672980070114f, 0.881346285343170f, 0.323380589485168f, + 0.881594181060791f, 0.323088020086288f, 0.881841897964478f, 0.322795242071152f, + 0.882089376449585f, 0.322502255439758f, 0.882336616516113f, 0.322209119796753f, + 0.882583618164063f, 0.321915775537491f, 0.882830440998077f, 0.321622252464294f, + 0.883076965808868f, 0.321328520774841f, 0.883323311805725f, 0.321034610271454f, + 0.883569478988647f, 0.320740520954132f, 0.883815348148346f, 0.320446223020554f, + 0.884061038494110f, 0.320151746273041f, 0.884306430816650f, 0.319857090711594f, + 0.884551644325256f, 0.319562226533890f, 0.884796679019928f, 0.319267183542252f, + 0.885041415691376f, 0.318971961736679f, 0.885285973548889f, 0.318676531314850f, + 0.885530233383179f, 0.318380922079086f, 0.885774314403534f, 0.318085134029388f, + 0.886018216609955f, 0.317789167165756f, 0.886261820793152f, 0.317492991685867f, + 0.886505246162415f, 0.317196637392044f, 0.886748373508453f, 0.316900104284287f, + 0.886991322040558f, 0.316603392362595f, 0.887234091758728f, 0.316306471824646f, + 0.887476563453674f, 0.316009372472763f, 0.887718796730042f, 0.315712094306946f, + 0.887960851192474f, 0.315414607524872f, 0.888202667236328f, 0.315116971731186f, + 0.888444244861603f, 0.314819127321243f, 0.888685584068298f, 0.314521104097366f, + 0.888926684856415f, 0.314222872257233f, 0.889167606830597f, 0.313924491405487f, + 0.889408230781555f, 0.313625901937485f, 0.889648675918579f, 0.313327133655548f, + 0.889888882637024f, 0.313028186559677f, 0.890128850936890f, 0.312729060649872f, + 0.890368640422821f, 0.312429755926132f, 0.890608131885529f, 0.312130242586136f, + 0.890847444534302f, 0.311830550432205f, 0.891086459159851f, 0.311530679464340f, + 0.891325294971466f, 0.311230629682541f, 0.891563892364502f, 0.310930401086807f, + 0.891802251338959f, 0.310629993677139f, 0.892040371894836f, 0.310329377651215f, + 0.892278313636780f, 0.310028612613678f, 0.892515957355499f, 0.309727638959885f, + 0.892753422260284f, 0.309426486492157f, 0.892990648746490f, 0.309125155210495f, + 0.893227577209473f, 0.308823645114899f, 0.893464326858521f, 0.308521956205368f, + 0.893700897693634f, 0.308220088481903f, 0.893937170505524f, 0.307918041944504f, + 0.894173204898834f, 0.307615786790848f, 0.894409060478210f, 0.307313382625580f, + 0.894644618034363f, 0.307010769844055f, 0.894879996776581f, 0.306708008050919f, + 0.895115137100220f, 0.306405037641525f, 0.895349979400635f, 0.306101888418198f, + 0.895584642887115f, 0.305798590183258f, 0.895819067955017f, 0.305495083332062f, + 0.896053314208984f, 0.305191397666931f, 0.896287262439728f, 0.304887533187866f, + 0.896520972251892f, 0.304583519697189f, 0.896754503250122f, 0.304279297590256f, + 0.896987736225128f, 0.303974896669388f, 0.897220790386200f, 0.303670316934586f, + 0.897453546524048f, 0.303365558385849f, 0.897686123847961f, 0.303060621023178f, + 0.897918462753296f, 0.302755534648895f, 0.898150563240051f, 0.302450239658356f, + 0.898382425308228f, 0.302144765853882f, 0.898614048957825f, 0.301839113235474f, + 0.898845434188843f, 0.301533311605453f, 0.899076581001282f, 0.301227301359177f, + 0.899307489395142f, 0.300921112298965f, 0.899538159370422f, 0.300614774227142f, + 0.899768650531769f, 0.300308227539063f, 0.899998843669891f, 0.300001531839371f, + 0.900228857994080f, 0.299694657325745f, 0.900458574295044f, 0.299387603998184f, + 0.900688111782074f, 0.299080342054367f, 0.900917351245880f, 0.298772931098938f, + 0.901146411895752f, 0.298465341329575f, 0.901375174522400f, 0.298157602548599f, + 0.901603758335114f, 0.297849655151367f, 0.901832103729248f, 0.297541528940201f, + 0.902060210704803f, 0.297233253717422f, 0.902288019657135f, 0.296924799680710f, + 0.902515649795532f, 0.296616137027740f, 0.902743041515350f, 0.296307325363159f, + 0.902970194816589f, 0.295998334884644f, 0.903197109699249f, 0.295689195394516f, + 0.903423786163330f, 0.295379847288132f, 0.903650224208832f, 0.295070350170136f, + 0.903876423835754f, 0.294760644435883f, 0.904102385044098f, 0.294450789690018f, + 0.904328107833862f, 0.294140785932541f, 0.904553592205048f, 0.293830573558807f, + 0.904778838157654f, 0.293520182371140f, 0.905003845691681f, 0.293209642171860f, + 0.905228614807129f, 0.292898923158646f, 0.905453145503998f, 0.292588025331497f, + 0.905677437782288f, 0.292276978492737f, 0.905901491641998f, 0.291965723037720f, + 0.906125307083130f, 0.291654318571091f, 0.906348884105682f, 0.291342735290527f, + 0.906572222709656f, 0.291031002998352f, 0.906795322895050f, 0.290719062089920f, + 0.907018184661865f, 0.290406972169876f, 0.907240808010101f, 0.290094703435898f, + 0.907463192939758f, 0.289782285690308f, 0.907685279846191f, 0.289469659328461f, + 0.907907187938690f, 0.289156883955002f, 0.908128857612610f, 0.288843959569931f, + 0.908350288867950f, 0.288530826568604f, 0.908571481704712f, 0.288217544555664f, + 0.908792436122894f, 0.287904083728790f, 0.909013092517853f, 0.287590473890305f, + 0.909233570098877f, 0.287276685237885f, 0.909453809261322f, 0.286962717771530f, + 0.909673750400543f, 0.286648571491241f, 0.909893512725830f, 0.286334276199341f, + 0.910112977027893f, 0.286019802093506f, 0.910332262516022f, 0.285705178976059f, + 0.910551249980927f, 0.285390377044678f, 0.910769999027252f, 0.285075396299362f, + 0.910988569259644f, 0.284760266542435f, 0.911206841468811f, 0.284444957971573f, + 0.911424875259399f, 0.284129470586777f, 0.911642670631409f, 0.283813834190369f, + 0.911860227584839f, 0.283498018980026f, 0.912077546119690f, 0.283182054758072f, + 0.912294626235962f, 0.282865911722183f, 0.912511467933655f, 0.282549589872360f, + 0.912728071212769f, 0.282233119010925f, 0.912944436073303f, 0.281916469335556f, + 0.913160502910614f, 0.281599670648575f, 0.913376390933990f, 0.281282693147659f, + 0.913592040538788f, 0.280965566635132f, 0.913807392120361f, 0.280648261308670f, + 0.914022505283356f, 0.280330777168274f, 0.914237439632416f, 0.280013144016266f, + 0.914452075958252f, 0.279695361852646f, 0.914666473865509f, 0.279377400875092f, + 0.914880633354187f, 0.279059261083603f, 0.915094554424286f, 0.278740972280502f, + 0.915308177471161f, 0.278422504663467f, 0.915521621704102f, 0.278103888034821f, + 0.915734827518463f, 0.277785122394562f, 0.915947735309601f, 0.277466177940369f, + 0.916160404682159f, 0.277147054672241f, 0.916372895240784f, 0.276827782392502f, + 0.916585087776184f, 0.276508361101151f, 0.916797041893005f, 0.276188760995865f, + 0.917008757591248f, 0.275868982076645f, 0.917220234870911f, 0.275549083948135f, + 0.917431414127350f, 0.275228977203369f, 0.917642414569855f, 0.274908751249313f, + 0.917853116989136f, 0.274588316679001f, 0.918063640594482f, 0.274267762899399f, + 0.918273866176605f, 0.273947030305862f, 0.918483853340149f, 0.273626148700714f, + 0.918693602085114f, 0.273305088281631f, 0.918903112411499f, 0.272983878850937f, + 0.919112324714661f, 0.272662490606308f, 0.919321358203888f, 0.272340953350067f, + 0.919530093669891f, 0.272019267082214f, 0.919738650321960f, 0.271697402000427f, + 0.919946908950806f, 0.271375387907028f, 0.920154929161072f, 0.271053224802017f, + 0.920362710952759f, 0.270730882883072f, 0.920570194721222f, 0.270408391952515f, + 0.920777499675751f, 0.270085722208023f, 0.920984506607056f, 0.269762933254242f, + 0.921191275119781f, 0.269439965486526f, 0.921397805213928f, 0.269116818904877f, + 0.921604096889496f, 0.268793523311615f, 0.921810150146484f, 0.268470078706741f, + 0.922015964984894f, 0.268146485090256f, 0.922221481800079f, 0.267822742462158f, + 0.922426760196686f, 0.267498821020126f, 0.922631800174713f, 0.267174720764160f, + 0.922836601734161f, 0.266850501298904f, 0.923041164875031f, 0.266526103019714f, + 0.923245489597321f, 0.266201555728912f, 0.923449516296387f, 0.265876859426498f, + 0.923653304576874f, 0.265552014112473f, 0.923856854438782f, 0.265226989984512f, + 0.924060165882111f, 0.264901816844940f, 0.924263238906860f, 0.264576494693756f, + 0.924466013908386f, 0.264250993728638f, 0.924668610095978f, 0.263925373554230f, + 0.924870908260345f, 0.263599574565887f, 0.925072908401489f, 0.263273626565933f, + 0.925274729728699f, 0.262947499752045f, 0.925476312637329f, 0.262621253728867f, + 0.925677597522736f, 0.262294828891754f, 0.925878643989563f, 0.261968284845352f, + 0.926079452037811f, 0.261641561985016f, 0.926280021667480f, 0.261314690113068f, + 0.926480293273926f, 0.260987639427185f, 0.926680326461792f, 0.260660469532013f, + 0.926880121231079f, 0.260333120822906f, 0.927079677581787f, 0.260005623102188f, + 0.927278995513916f, 0.259678006172180f, 0.927478015422821f, 0.259350210428238f, + 0.927676856517792f, 0.259022265672684f, 0.927875399589539f, 0.258694142103195f, + 0.928073644638062f, 0.258365899324417f, 0.928271710872650f, 0.258037507534027f, + 0.928469479084015f, 0.257708936929703f, 0.928667008876801f, 0.257380217313766f, + 0.928864300251007f, 0.257051378488541f, 0.929061353206635f, 0.256722360849380f, + 0.929258108139038f, 0.256393194198608f, 0.929454624652863f, 0.256063878536224f, + 0.929650902748108f, 0.255734413862228f, 0.929846942424774f, 0.255404800176620f, + 0.930042684078217f, 0.255075037479401f, 0.930238187313080f, 0.254745125770569f, + 0.930433452129364f, 0.254415065050125f, 0.930628478527069f, 0.254084855318069f, + 0.930823206901550f, 0.253754496574402f, 0.931017756462097f, 0.253423988819122f, + 0.931211948394775f, 0.253093332052231f, 0.931405961513519f, 0.252762526273727f, + 0.931599736213684f, 0.252431541681290f, 0.931793212890625f, 0.252100437879562f, + 0.931986451148987f, 0.251769185066223f, 0.932179391384125f, 0.251437783241272f, + 0.932372152805328f, 0.251106232404709f, 0.932564616203308f, 0.250774532556534f, + 0.932756841182709f, 0.250442683696747f, 0.932948768138886f, 0.250110685825348f, + 0.933140456676483f, 0.249778553843498f, 0.933331906795502f, 0.249446272850037f, + 0.933523118495941f, 0.249113827943802f, 0.933714091777802f, 0.248781248927116f, + 0.933904767036438f, 0.248448520898819f, 0.934095203876495f, 0.248115643858910f, + 0.934285342693329f, 0.247782632708550f, 0.934475243091583f, 0.247449472546577f, + 0.934664964675903f, 0.247116148471832f, 0.934854328632355f, 0.246782705187798f, + 0.935043513774872f, 0.246449097990990f, 0.935232400894165f, 0.246115356683731f, + 0.935421049594879f, 0.245781451463699f, 0.935609400272369f, 0.245447427034378f, + 0.935797572135925f, 0.245113238692284f, 0.935985386371613f, 0.244778916239738f, + 0.936173021793365f, 0.244444444775581f, 0.936360359191895f, 0.244109839200974f, + 0.936547517776489f, 0.243775084614754f, 0.936734318733215f, 0.243440181016922f, + 0.936920940876007f, 0.243105143308640f, 0.937107264995575f, 0.242769956588745f, + 0.937293350696564f, 0.242434620857239f, 0.937479138374329f, 0.242099151015282f, + 0.937664687633514f, 0.241763532161713f, 0.937849998474121f, 0.241427779197693f, + 0.938035070896149f, 0.241091892123222f, 0.938219845294952f, 0.240755841135979f, + 0.938404381275177f, 0.240419670939446f, 0.938588619232178f, 0.240083336830139f, + 0.938772618770599f, 0.239746883511543f, 0.938956379890442f, 0.239410281181335f, + 0.939139902591705f, 0.239073529839516f, 0.939323127269745f, 0.238736644387245f, + 0.939506113529205f, 0.238399609923363f, 0.939688861370087f, 0.238062441349030f, + 0.939871311187744f, 0.237725138664246f, 0.940053522586823f, 0.237387686967850f, + 0.940235435962677f, 0.237050101161003f, 0.940417110919952f, 0.236712381243706f, + 0.940598547458649f, 0.236374512314796f, 0.940779745578766f, 0.236036509275436f, + 0.940960645675659f, 0.235698372125626f, 0.941141307353973f, 0.235360085964203f, + 0.941321671009064f, 0.235021665692329f, 0.941501796245575f, 0.234683111310005f, + 0.941681683063507f, 0.234344407916069f, 0.941861271858215f, 0.234005570411682f, + 0.942040622234344f, 0.233666598796844f, 0.942219734191895f, 0.233327493071556f, + 0.942398548126221f, 0.232988253235817f, 0.942577123641968f, 0.232648864388466f, + 0.942755401134491f, 0.232309341430664f, 0.942933499813080f, 0.231969684362412f, + 0.943111240863800f, 0.231629893183708f, 0.943288803100586f, 0.231289967894554f, + 0.943466067314148f, 0.230949893593788f, 0.943643093109131f, 0.230609700083733f, + 0.943819820880890f, 0.230269357562065f, 0.943996310234070f, 0.229928880929947f, + 0.944172501564026f, 0.229588270187378f, 0.944348454475403f, 0.229247525334358f, + 0.944524168968201f, 0.228906646370888f, 0.944699645042419f, 0.228565633296967f, + 0.944874763488770f, 0.228224486112595f, 0.945049703121185f, 0.227883204817772f, + 0.945224344730377f, 0.227541789412498f, 0.945398747920990f, 0.227200239896774f, + 0.945572853088379f, 0.226858556270599f, 0.945746779441834f, 0.226516738533974f, + 0.945920348167419f, 0.226174786686897f, 0.946093678474426f, 0.225832715630531f, + 0.946266770362854f, 0.225490495562553f, 0.946439623832703f, 0.225148141384125f, + 0.946612179279327f, 0.224805667996407f, 0.946784436702728f, 0.224463045597076f, + 0.946956455707550f, 0.224120303988457f, 0.947128236293793f, 0.223777428269386f, + 0.947299718856812f, 0.223434418439865f, 0.947470963001251f, 0.223091274499893f, + 0.947641968727112f, 0.222748011350632f, 0.947812676429749f, 0.222404599189758f, + 0.947983145713806f, 0.222061067819595f, 0.948153316974640f, 0.221717402338982f, + 0.948323249816895f, 0.221373617649078f, 0.948492884635925f, 0.221029683947563f, + 0.948662281036377f, 0.220685631036758f, 0.948831439018250f, 0.220341444015503f, + 0.949000298976898f, 0.219997137784958f, 0.949168920516968f, 0.219652697443962f, + 0.949337244033813f, 0.219308122992516f, 0.949505329132080f, 0.218963414430618f, + 0.949673116207123f, 0.218618586659431f, 0.949840664863586f, 0.218273624777794f, + 0.950007975101471f, 0.217928543686867f, 0.950174987316132f, 0.217583328485489f, + 0.950341701507568f, 0.217237979173660f, 0.950508177280426f, 0.216892510652542f, + 0.950674414634705f, 0.216546908020973f, 0.950840353965759f, 0.216201186180115f, + 0.951006054878235f, 0.215855330228806f, 0.951171517372131f, 0.215509355068207f, + 0.951336681842804f, 0.215163245797157f, 0.951501548290253f, 0.214817002415657f, + 0.951666176319122f, 0.214470639824867f, 0.951830565929413f, 0.214124158024788f, + 0.951994657516479f, 0.213777542114258f, 0.952158451080322f, 0.213430806994438f, + 0.952322065830231f, 0.213083937764168f, 0.952485322952271f, 0.212736949324608f, + 0.952648401260376f, 0.212389841675758f, 0.952811121940613f, 0.212042599916458f, + 0.952973663806915f, 0.211695238947868f, 0.953135907649994f, 0.211347743868828f, + 0.953297853469849f, 0.211000129580498f, 0.953459560871124f, 0.210652396082878f, + 0.953620970249176f, 0.210304543375969f, 0.953782141208649f, 0.209956556558609f, + 0.953943073749542f, 0.209608450531960f, 0.954103708267212f, 0.209260210394859f, + 0.954264044761658f, 0.208911851048470f, 0.954424142837524f, 0.208563387393951f, + 0.954584002494812f, 0.208214774727821f, 0.954743564128876f, 0.207866057753563f, + 0.954902827739716f, 0.207517206668854f, 0.955061912536621f, 0.207168251276016f, + 0.955220639705658f, 0.206819161772728f, 0.955379128456116f, 0.206469938158989f, + 0.955537378787994f, 0.206120610237122f, 0.955695331096649f, 0.205771163105965f, + 0.955853044986725f, 0.205421581864357f, 0.956010460853577f, 0.205071896314621f, + 0.956167578697205f, 0.204722076654434f, 0.956324458122253f, 0.204372137784958f, + 0.956481099128723f, 0.204022079706192f, 0.956637442111969f, 0.203671902418137f, + 0.956793546676636f, 0.203321605920792f, 0.956949353218079f, 0.202971190214157f, + 0.957104861736298f, 0.202620655298233f, 0.957260131835938f, 0.202270001173019f, + 0.957415163516998f, 0.201919227838516f, 0.957569897174835f, 0.201568335294724f, + 0.957724332809448f, 0.201217323541641f, 0.957878530025482f, 0.200866192579269f, + 0.958032488822937f, 0.200514942407608f, 0.958186149597168f, 0.200163587927818f, + 0.958339512348175f, 0.199812099337578f, 0.958492636680603f, 0.199460506439209f, + 0.958645522594452f, 0.199108779430389f, 0.958798050880432f, 0.198756948113441f, + 0.958950400352478f, 0.198404997587204f, 0.959102451801300f, 0.198052927851677f, + 0.959254205226898f, 0.197700738906860f, 0.959405720233917f, 0.197348430752754f, + 0.959556937217712f, 0.196996018290520f, 0.959707856178284f, 0.196643486618996f, + 0.959858596324921f, 0.196290835738182f, 0.960008978843689f, 0.195938065648079f, + 0.960159122943878f, 0.195585191249847f, 0.960309028625488f, 0.195232197642326f, + 0.960458636283875f, 0.194879084825516f, 0.960607945919037f, 0.194525867700577f, + 0.960757017135620f, 0.194172516465187f, 0.960905790328979f, 0.193819075822830f, + 0.961054325103760f, 0.193465501070023f, 0.961202561855316f, 0.193111822009087f, + 0.961350560188293f, 0.192758023738861f, 0.961498260498047f, 0.192404121160507f, + 0.961645722389221f, 0.192050099372864f, 0.961792886257172f, 0.191695958375931f, + 0.961939752101898f, 0.191341713070869f, 0.962086379528046f, 0.190987363457680f, + 0.962232708930969f, 0.190632879734039f, 0.962378799915314f, 0.190278306603432f, + 0.962524592876434f, 0.189923599362373f, 0.962670147418976f, 0.189568802714348f, + 0.962815403938293f, 0.189213871955872f, 0.962960422039032f, 0.188858851790428f, + 0.963105142116547f, 0.188503712415695f, 0.963249564170837f, 0.188148453831673f, + 0.963393747806549f, 0.187793090939522f, 0.963537633419037f, 0.187437608838081f, + 0.963681280612946f, 0.187082037329674f, 0.963824629783630f, 0.186726331710815f, + 0.963967680931091f, 0.186370536684990f, 0.964110493659973f, 0.186014622449875f, + 0.964253067970276f, 0.185658603906631f, 0.964395284652710f, 0.185302466154099f, + 0.964537262916565f, 0.184946224093437f, 0.964679002761841f, 0.184589877724648f, + 0.964820444583893f, 0.184233412146568f, 0.964961588382721f, 0.183876842260361f, + 0.965102493762970f, 0.183520168066025f, 0.965243160724640f, 0.183163389563560f, + 0.965383470058441f, 0.182806491851807f, 0.965523540973663f, 0.182449504733086f, + 0.965663373470306f, 0.182092398405075f, 0.965802907943726f, 0.181735187768936f, + 0.965942144393921f, 0.181377857923508f, 0.966081082820892f, 0.181020438671112f, + 0.966219842433929f, 0.180662900209427f, 0.966358244419098f, 0.180305257439613f, + 0.966496407985687f, 0.179947525262833f, 0.966634273529053f, 0.179589673876762f, + 0.966771900653839f, 0.179231703281403f, 0.966909229755402f, 0.178873643279076f, + 0.967046260833740f, 0.178515478968620f, 0.967183053493500f, 0.178157210350037f, + 0.967319548130035f, 0.177798837423325f, 0.967455804347992f, 0.177440345287323f, + 0.967591762542725f, 0.177081763744354f, 0.967727422714233f, 0.176723077893257f, + 0.967862844467163f, 0.176364272832870f, 0.967997968196869f, 0.176005378365517f, + 0.968132853507996f, 0.175646379590034f, 0.968267440795898f, 0.175287276506424f, + 0.968401730060577f, 0.174928069114685f, 0.968535780906677f, 0.174568757414818f, + 0.968669533729553f, 0.174209341406822f, 0.968802988529205f, 0.173849821090698f, + 0.968936204910278f, 0.173490211367607f, 0.969069123268127f, 0.173130482435226f, + 0.969201743602753f, 0.172770664095879f, 0.969334125518799f, 0.172410741448402f, + 0.969466269016266f, 0.172050714492798f, 0.969598054885864f, 0.171690583229065f, + 0.969729602336884f, 0.171330362558365f, 0.969860911369324f, 0.170970037579536f, + 0.969991862773895f, 0.170609608292580f, 0.970122575759888f, 0.170249074697495f, + 0.970253050327301f, 0.169888436794281f, 0.970383226871490f, 0.169527709484100f, + 0.970513105392456f, 0.169166877865791f, 0.970642685890198f, 0.168805956840515f, + 0.970772027969360f, 0.168444931507111f, 0.970901072025299f, 0.168083801865578f, + 0.971029877662659f, 0.167722567915916f, 0.971158385276794f, 0.167361244559288f, + 0.971286594867706f, 0.166999831795692f, 0.971414566040039f, 0.166638299822807f, + 0.971542239189148f, 0.166276678442955f, 0.971669614315033f, 0.165914967656136f, + 0.971796751022339f, 0.165553152561188f, 0.971923589706421f, 0.165191248059273f, + 0.972050130367279f, 0.164829224348068f, 0.972176432609558f, 0.164467126131058f, + 0.972302436828613f, 0.164104923605919f, 0.972428143024445f, 0.163742616772652f, + 0.972553610801697f, 0.163380220532417f, 0.972678780555725f, 0.163017734885216f, + 0.972803652286530f, 0.162655144929886f, 0.972928285598755f, 0.162292465567589f, + 0.973052620887756f, 0.161929681897163f, 0.973176658153534f, 0.161566808819771f, + 0.973300457000732f, 0.161203846335411f, 0.973423957824707f, 0.160840779542923f, + 0.973547160625458f, 0.160477623343468f, 0.973670125007629f, 0.160114362835884f, + 0.973792791366577f, 0.159751012921333f, 0.973915159702301f, 0.159387573599815f, + 0.974037289619446f, 0.159024044871330f, 0.974159121513367f, 0.158660411834717f, + 0.974280655384064f, 0.158296689391136f, 0.974401950836182f, 0.157932877540588f, + 0.974522948265076f, 0.157568961381912f, 0.974643647670746f, 0.157204970717430f, + 0.974764108657837f, 0.156840875744820f, 0.974884271621704f, 0.156476691365242f, + 0.975004136562347f, 0.156112402677536f, 0.975123703479767f, 0.155748039484024f, + 0.975243031978607f, 0.155383571982384f, 0.975362062454224f, 0.155019029974937f, + 0.975480854511261f, 0.154654383659363f, 0.975599288940430f, 0.154289647936821f, + 0.975717484951019f, 0.153924822807312f, 0.975835442543030f, 0.153559908270836f, + 0.975953042507172f, 0.153194904327393f, 0.976070404052734f, 0.152829796075821f, + 0.976187527179718f, 0.152464613318443f, 0.976304292678833f, 0.152099341154099f, + 0.976420819759369f, 0.151733979582787f, 0.976537048816681f, 0.151368513703346f, + 0.976653039455414f, 0.151002973318100f, 0.976768672466278f, 0.150637343525887f, + 0.976884067058563f, 0.150271624326706f, 0.976999223232269f, 0.149905815720558f, + 0.977114021778107f, 0.149539917707443f, 0.977228581905365f, 0.149173930287361f, + 0.977342903614044f, 0.148807853460312f, 0.977456867694855f, 0.148441687226295f, + 0.977570593357086f, 0.148075446486473f, 0.977684020996094f, 0.147709101438522f, + 0.977797150611877f, 0.147342681884766f, 0.977910041809082f, 0.146976172924042f, + 0.978022634983063f, 0.146609574556351f, 0.978134930133820f, 0.146242901682854f, + 0.978246986865997f, 0.145876124501228f, 0.978358685970306f, 0.145509272813797f, + 0.978470146656036f, 0.145142331719399f, 0.978581368923187f, 0.144775316119194f, + 0.978692233562469f, 0.144408211112022f, 0.978802859783173f, 0.144041016697884f, + 0.978913187980652f, 0.143673732876778f, 0.979023277759552f, 0.143306359648705f, + 0.979133009910584f, 0.142938911914825f, 0.979242503643036f, 0.142571389675140f, + 0.979351758956909f, 0.142203763127327f, 0.979460656642914f, 0.141836062073708f, + 0.979569315910339f, 0.141468286514282f, 0.979677677154541f, 0.141100421547890f, + 0.979785740375519f, 0.140732467174530f, 0.979893565177917f, 0.140364438295364f, + 0.980001091957092f, 0.139996320009232f, 0.980108320713043f, 0.139628127217293f, + 0.980215251445770f, 0.139259845018387f, 0.980321943759918f, 0.138891488313675f, + 0.980428338050842f, 0.138523042201996f, 0.980534434318542f, 0.138154521584511f, + 0.980640232563019f, 0.137785911560059f, 0.980745792388916f, 0.137417227029800f, + 0.980851054191589f, 0.137048453092575f, 0.980956017971039f, 0.136679604649544f, + 0.981060683727264f, 0.136310681700706f, 0.981165111064911f, 0.135941669344902f, + 0.981269240379334f, 0.135572582483292f, 0.981373071670532f, 0.135203406214714f, + 0.981476604938507f, 0.134834155440331f, 0.981579899787903f, 0.134464830160141f, + 0.981682896614075f, 0.134095430374146f, 0.981785595417023f, 0.133725941181183f, + 0.981888055801392f, 0.133356377482414f, 0.981990158557892f, 0.132986739277840f, + 0.982092022895813f, 0.132617011666298f, 0.982193589210510f, 0.132247209548950f, + 0.982294917106628f, 0.131877332925797f, 0.982395887374878f, 0.131507381796837f, + 0.982496619224548f, 0.131137356162071f, 0.982597053050995f, 0.130767241120338f, + 0.982697248458862f, 0.130397051572800f, 0.982797086238861f, 0.130026802420616f, + 0.982896685600281f, 0.129656463861465f, 0.982995986938477f, 0.129286035895348f, + 0.983094990253448f, 0.128915548324585f, 0.983193755149841f, 0.128544986248016f, + 0.983292162418365f, 0.128174334764481f, 0.983390331268311f, 0.127803623676300f, + 0.983488261699677f, 0.127432823181152f, 0.983585834503174f, 0.127061963081360f, + 0.983683168888092f, 0.126691013574600f, 0.983780145645142f, 0.126320004463196f, + 0.983876943588257f, 0.125948905944824f, 0.983973383903503f, 0.125577747821808f, + 0.984069526195526f, 0.125206500291824f, 0.984165430068970f, 0.124835193157196f, + 0.984261035919189f, 0.124463804066181f, 0.984356343746185f, 0.124092340469360f, + 0.984451413154602f, 0.123720809817314f, 0.984546124935150f, 0.123349204659462f, + 0.984640598297119f, 0.122977524995804f, 0.984734773635864f, 0.122605770826340f, + 0.984828710556030f, 0.122233949601650f, 0.984922289848328f, 0.121862053871155f, + 0.985015630722046f, 0.121490091085434f, 0.985108673572540f, 0.121118053793907f, + 0.985201418399811f, 0.120745941996574f, 0.985293865203857f, 0.120373763144016f, + 0.985386073589325f, 0.120001509785652f, 0.985477983951569f, 0.119629189372063f, + 0.985569596290588f, 0.119256794452667f, 0.985660910606384f, 0.118884332478046f, + 0.985751926898956f, 0.118511803448200f, 0.985842704772949f, 0.118139199912548f, + 0.985933184623718f, 0.117766529321671f, 0.986023366451263f, 0.117393791675568f, + 0.986113250255585f, 0.117020979523659f, 0.986202836036682f, 0.116648100316525f, + 0.986292183399200f, 0.116275154054165f, 0.986381232738495f, 0.115902140736580f, + 0.986469984054565f, 0.115529052913189f, 0.986558437347412f, 0.115155905485153f, + 0.986646652221680f, 0.114782683551311f, 0.986734509468079f, 0.114409394562244f, + 0.986822128295898f, 0.114036038517952f, 0.986909449100494f, 0.113662622869015f, + 0.986996471881866f, 0.113289132714272f, 0.987083256244659f, 0.112915575504303f, + 0.987169682979584f, 0.112541958689690f, 0.987255871295929f, 0.112168267369270f, + 0.987341761589050f, 0.111794516444206f, 0.987427353858948f, 0.111420698463917f, + 0.987512648105621f, 0.111046813428402f, 0.987597703933716f, 0.110672861337662f, + 0.987682461738586f, 0.110298842191696f, 0.987766921520233f, 0.109924763441086f, + 0.987851083278656f, 0.109550617635250f, 0.987934947013855f, 0.109176412224770f, + 0.988018512725830f, 0.108802139759064f, 0.988101840019226f, 0.108427800238132f, + 0.988184869289398f, 0.108053401112556f, 0.988267600536346f, 0.107678934931755f, + 0.988350033760071f, 0.107304409146309f, 0.988432228565216f, 0.106929816305637f, + 0.988514065742493f, 0.106555156409740f, 0.988595664501190f, 0.106180444359779f, + 0.988676965236664f, 0.105805665254593f, 0.988757967948914f, 0.105430819094181f, + 0.988838672637939f, 0.105055920779705f, 0.988919138908386f, 0.104680955410004f, + 0.988999247550964f, 0.104305922985077f, 0.989079117774963f, 0.103930838406086f, + 0.989158689975739f, 0.103555686771870f, 0.989237964153290f, 0.103180475533009f, + 0.989316940307617f, 0.102805204689503f, 0.989395678043365f, 0.102429874241352f, + 0.989474058151245f, 0.102054484188557f, 0.989552199840546f, 0.101679034531116f, + 0.989630043506622f, 0.101303517818451f, 0.989707589149475f, 0.100927948951721f, + 0.989784896373749f, 0.100552320480347f, 0.989861845970154f, 0.100176624953747f, + 0.989938557147980f, 0.099800877273083f, 0.990014970302582f, 0.099425069987774f, + 0.990091085433960f, 0.099049203097820f, 0.990166902542114f, 0.098673284053802f, + 0.990242421627045f, 0.098297297954559f, 0.990317702293396f, 0.097921259701252f, + 0.990392625331879f, 0.097545161843300f, 0.990467309951782f, 0.097169004380703f, + 0.990541696548462f, 0.096792794764042f, 0.990615785121918f, 0.096416525542736f, + 0.990689575672150f, 0.096040196716785f, 0.990763127803802f, 0.095663815736771f, + 0.990836322307587f, 0.095287375152111f, 0.990909278392792f, 0.094910882413387f, + 0.990981936454773f, 0.094534330070019f, 0.991054296493530f, 0.094157725572586f, + 0.991126358509064f, 0.093781061470509f, 0.991198182106018f, 0.093404345214367f, + 0.991269648075104f, 0.093027576804161f, 0.991340875625610f, 0.092650748789310f, + 0.991411805152893f, 0.092273868620396f, 0.991482377052307f, 0.091896936297417f, + 0.991552770137787f, 0.091519944369793f, 0.991622805595398f, 0.091142900288105f, + 0.991692543029785f, 0.090765804052353f, 0.991762042045593f, 0.090388655662537f, + 0.991831183433533f, 0.090011447668076f, 0.991900086402893f, 0.089634194970131f, + 0.991968691349030f, 0.089256882667542f, 0.992036998271942f, 0.088879525661469f, + 0.992105066776276f, 0.088502109050751f, 0.992172777652740f, 0.088124647736549f, + 0.992240250110626f, 0.087747126817703f, 0.992307364940643f, 0.087369553744793f, + 0.992374241352081f, 0.086991935968399f, 0.992440819740295f, 0.086614266037941f, + 0.992507100105286f, 0.086236543953419f, 0.992573142051697f, 0.085858769714832f, + 0.992638826370239f, 0.085480943322182f, 0.992704212665558f, 0.085103072226048f, + 0.992769360542297f, 0.084725148975849f, 0.992834210395813f, 0.084347173571587f, + 0.992898762226105f, 0.083969146013260f, 0.992963016033173f, 0.083591073751450f, + 0.993026971817017f, 0.083212949335575f, 0.993090689182281f, 0.082834780216217f, + 0.993154048919678f, 0.082456558942795f, 0.993217170238495f, 0.082078292965889f, + 0.993279933929443f, 0.081699974834919f, 0.993342459201813f, 0.081321612000465f, + 0.993404686450958f, 0.080943197011948f, 0.993466615676880f, 0.080564737319946f, + 0.993528306484222f, 0.080186225473881f, 0.993589639663696f, 0.079807676374912f, + 0.993650734424591f, 0.079429075121880f, 0.993711471557617f, 0.079050421714783f, + 0.993771970272064f, 0.078671731054783f, 0.993832170963287f, 0.078292988240719f, + 0.993892073631287f, 0.077914200723171f, 0.993951678276062f, 0.077535368502140f, + 0.994010984897614f, 0.077156484127045f, 0.994070053100586f, 0.076777562499046f, + 0.994128763675690f, 0.076398596167564f, 0.994187235832214f, 0.076019577682018f, + 0.994245409965515f, 0.075640521943569f, 0.994303286075592f, 0.075261414051056f, + 0.994360864162445f, 0.074882268905640f, 0.994418144226074f, 0.074503071606159f, + 0.994475126266479f, 0.074123837053776f, 0.994531810283661f, 0.073744557797909f, + 0.994588255882263f, 0.073365233838558f, 0.994644403457642f, 0.072985872626305f, + 0.994700193405151f, 0.072606459259987f, 0.994755744934082f, 0.072227008640766f, + 0.994810998439789f, 0.071847513318062f, 0.994865953922272f, 0.071467980742455f, + 0.994920611381531f, 0.071088403463364f, 0.994975030422211f, 0.070708781480789f, + 0.995029091835022f, 0.070329122245312f, 0.995082914829254f, 0.069949418306351f, + 0.995136380195618f, 0.069569669663906f, 0.995189607143402f, 0.069189883768559f, + 0.995242536067963f, 0.068810060620308f, 0.995295166969299f, 0.068430192768574f, + 0.995347499847412f, 0.068050287663937f, 0.995399534702301f, 0.067670337855816f, + 0.995451331138611f, 0.067290350794792f, 0.995502769947052f, 0.066910326480865f, + 0.995553970336914f, 0.066530264914036f, 0.995604813098907f, 0.066150158643723f, + 0.995655417442322f, 0.065770015120506f, 0.995705723762512f, 0.065389834344387f, + 0.995755732059479f, 0.065009608864784f, 0.995805442333221f, 0.064629353582859f, + 0.995854854583740f, 0.064249053597450f, 0.995904028415680f, 0.063868723809719f, + 0.995952844619751f, 0.063488349318504f, 0.996001422405243f, 0.063107937574387f, + 0.996049642562866f, 0.062727488577366f, 0.996097624301910f, 0.062347009778023f, + 0.996145308017731f, 0.061966486275196f, 0.996192693710327f, 0.061585929244757f, + 0.996239781379700f, 0.061205338686705f, 0.996286571025848f, 0.060824707150459f, + 0.996333062648773f, 0.060444042086601f, 0.996379256248474f, 0.060063343495131f, + 0.996425211429596f, 0.059682607650757f, 0.996470808982849f, 0.059301838278770f, + 0.996516168117523f, 0.058921031653881f, 0.996561229228973f, 0.058540191501379f, + 0.996605992317200f, 0.058159314095974f, 0.996650457382202f, 0.057778406888247f, + 0.996694624423981f, 0.057397462427616f, 0.996738493442535f, 0.057016488164663f, + 0.996782064437866f, 0.056635476648808f, 0.996825337409973f, 0.056254431605339f, + 0.996868371963501f, 0.055873356759548f, 0.996911048889160f, 0.055492244660854f, + 0.996953487396240f, 0.055111102759838f, 0.996995627880096f, 0.054729927331209f, + 0.997037410736084f, 0.054348722100258f, 0.997078955173492f, 0.053967483341694f, + 0.997120201587677f, 0.053586211055517f, 0.997161149978638f, 0.053204908967018f, + 0.997201859951019f, 0.052823577076197f, 0.997242212295532f, 0.052442211657763f, + 0.997282266616821f, 0.052060816437006f, 0.997322082519531f, 0.051679391413927f, + 0.997361540794373f, 0.051297932863235f, 0.997400760650635f, 0.050916448235512f, + 0.997439682483673f, 0.050534930080175f, 0.997478306293488f, 0.050153385847807f, + 0.997516572475433f, 0.049771808087826f, 0.997554600238800f, 0.049390204250813f, + 0.997592389583588f, 0.049008570611477f, 0.997629821300507f, 0.048626907169819f, + 0.997666954994202f, 0.048245213925838f, 0.997703790664673f, 0.047863494604826f, + 0.997740387916565f, 0.047481749206781f, 0.997776627540588f, 0.047099970281124f, + 0.997812628746033f, 0.046718169003725f, 0.997848331928253f, 0.046336337924004f, + 0.997883677482605f, 0.045954477041960f, 0.997918784618378f, 0.045572593808174f, + 0.997953593730927f, 0.045190680772066f, 0.997988104820251f, 0.044808741658926f, + 0.998022377490997f, 0.044426776468754f, 0.998056292533875f, 0.044044785201550f, + 0.998089909553528f, 0.043662767857313f, 0.998123228549957f, 0.043280724436045f, + 0.998156309127808f, 0.042898654937744f, 0.998189091682434f, 0.042516563087702f, + 0.998221516609192f, 0.042134445160627f, 0.998253703117371f, 0.041752301156521f, + 0.998285591602325f, 0.041370131075382f, 0.998317182064056f, 0.040987938642502f, + 0.998348474502563f, 0.040605723857880f, 0.998379468917847f, 0.040223482996225f, + 0.998410165309906f, 0.039841219782829f, 0.998440563678741f, 0.039458930492401f, + 0.998470664024353f, 0.039076622575521f, 0.998500525951386f, 0.038694288581610f, + 0.998530030250549f, 0.038311932235956f, 0.998559296131134f, 0.037929553538561f, + 0.998588204383850f, 0.037547148764133f, 0.998616874217987f, 0.037164725363255f, + 0.998645246028900f, 0.036782283335924f, 0.998673319816589f, 0.036399815231562f, + 0.998701035976410f, 0.036017324775457f, 0.998728513717651f, 0.035634815692902f, + 0.998755753040314f, 0.035252287983894f, 0.998782634735107f, 0.034869734197855f, + 0.998809218406677f, 0.034487165510654f, 0.998835504055023f, 0.034104570746422f, + 0.998861551284790f, 0.033721961081028f, 0.998887240886688f, 0.033339329063892f, + 0.998912692070007f, 0.032956674695015f, 0.998937785625458f, 0.032574005424976f, + 0.998962640762329f, 0.032191313803196f, 0.998987197875977f, 0.031808607280254f, + 0.999011456966400f, 0.031425878405571f, 0.999035418033600f, 0.031043132767081f, + 0.999059081077576f, 0.030660368502140f, 0.999082446098328f, 0.030277585610747f, + 0.999105513095856f, 0.029894785955548f, 0.999128282070160f, 0.029511967673898f, + 0.999150753021240f, 0.029129132628441f, 0.999172985553741f, 0.028746278956532f, + 0.999194860458374f, 0.028363410383463f, 0.999216496944427f, 0.027980525046587f, + 0.999237775802612f, 0.027597622945905f, 0.999258816242218f, 0.027214704081416f, + 0.999279558658600f, 0.026831768453121f, 0.999299943447113f, 0.026448817923665f, + 0.999320089817047f, 0.026065852493048f, 0.999339938163757f, 0.025682870298624f, + 0.999359488487244f, 0.025299875065684f, 0.999378740787506f, 0.024916863068938f, + 0.999397754669189f, 0.024533838033676f, 0.999416410923004f, 0.024150796234608f, + 0.999434769153595f, 0.023767741397023f, 0.999452829360962f, 0.023384673520923f, + 0.999470651149750f, 0.023001590743661f, 0.999488115310669f, 0.022618494927883f, + 0.999505341053009f, 0.022235386073589f, 0.999522268772125f, 0.021852264180779f, + 0.999538838863373f, 0.021469129249454f, 0.999555170536041f, 0.021085981279612f, + 0.999571204185486f, 0.020702820271254f, 0.999586939811707f, 0.020319648087025f, + 0.999602377414703f, 0.019936462864280f, 0.999617516994476f, 0.019553268328309f, + 0.999632358551025f, 0.019170060753822f, 0.999646902084351f, 0.018786842003465f, + 0.999661207199097f, 0.018403612077236f, 0.999675154685974f, 0.018020370975137f, + 0.999688863754272f, 0.017637118697166f, 0.999702215194702f, 0.017253857105970f, + 0.999715328216553f, 0.016870586201549f, 0.999728083610535f, 0.016487304121256f, + 0.999740600585938f, 0.016104012727737f, 0.999752819538116f, 0.015720712020993f, + 0.999764680862427f, 0.015337402001023f, 0.999776303768158f, 0.014954082667828f, + 0.999787628650665f, 0.014570754021406f, 0.999798655509949f, 0.014187417924404f, + 0.999809384346008f, 0.013804072514176f, 0.999819874763489f, 0.013420719653368f, + 0.999830007553101f, 0.013037359341979f, 0.999839842319489f, 0.012653990648687f, + 0.999849438667297f, 0.012270614504814f, 0.999858677387238f, 0.011887230910361f, + 0.999867618083954f, 0.011503840796649f, 0.999876320362091f, 0.011120444163680f, + 0.999884724617004f, 0.010737040080130f, 0.999892771244049f, 0.010353630408645f, + 0.999900579452515f, 0.009970214217901f, 0.999908089637756f, 0.009586792439222f, + 0.999915301799774f, 0.009203365072608f, 0.999922215938568f, 0.008819932118058f, + 0.999928832054138f, 0.008436493575573f, 0.999935150146484f, 0.008053051307797f, + 0.999941170215607f, 0.007669602986425f, 0.999946892261505f, 0.007286150939763f, + 0.999952375888824f, 0.006902694236487f, 0.999957501888275f, 0.006519233807921f, + 0.999962329864502f, 0.006135769188404f, 0.999966919422150f, 0.005752300843596f, + 0.999971151351929f, 0.005368829704821f, 0.999975144863129f, 0.004985354840755f, + 0.999978840351105f, 0.004601877182722f, 0.999982178211212f, 0.004218397196382f, + 0.999985277652740f, 0.003834914416075f, 0.999988079071045f, 0.003451429307461f, + 0.999990582466125f, 0.003067942336202f, 0.999992787837982f, 0.002684453502297f, + 0.999994695186615f, 0.002300963038579f, 0.999996304512024f, 0.001917471294291f, + 0.999997675418854f, 0.001533978385851f, 0.999998688697815f, 0.001150484546088f, + 0.999999403953552f, 0.000766990066040f, 0.999999880790710f, 0.000383495149435f, + 1.000000000000000f, 0.000000000000023f, 0.999999880790710f, -0.000383495149435f, + 0.999999403953552f, -0.000766990066040f, 0.999998688697815f, -0.001150484546088f, + 0.999997675418854f, -0.001533978385851f, 0.999996304512024f, -0.001917471294291f, + 0.999994695186615f, -0.002300963038579f, 0.999992787837982f, -0.002684453502297f, + 0.999990582466125f, -0.003067942336202f, 0.999988079071045f, -0.003451429307461f, + 0.999985277652740f, -0.003834914416075f, 0.999982178211212f, -0.004218397196382f, + 0.999978840351105f, -0.004601877182722f, 0.999975144863129f, -0.004985354840755f, + 0.999971151351929f, -0.005368829704821f, 0.999966919422150f, -0.005752300843596f, + 0.999962329864502f, -0.006135769188404f, 0.999957501888275f, -0.006519233807921f, + 0.999952375888824f, -0.006902694236487f, 0.999946892261505f, -0.007286150939763f, + 0.999941170215607f, -0.007669602986425f, 0.999935150146484f, -0.008053051307797f, + 0.999928832054138f, -0.008436493575573f, 0.999922215938568f, -0.008819932118058f, + 0.999915301799774f, -0.009203365072608f, 0.999908089637756f, -0.009586792439222f, + 0.999900579452515f, -0.009970214217901f, 0.999892771244049f, -0.010353630408645f, + 0.999884724617004f, -0.010737040080130f, 0.999876320362091f, -0.011120444163680f, + 0.999867618083954f, -0.011503840796649f, 0.999858677387238f, -0.011887230910361f, + 0.999849438667297f, -0.012270614504814f, 0.999839842319489f, -0.012653990648687f, + 0.999830007553101f, -0.013037359341979f, 0.999819874763489f, -0.013420719653368f, + 0.999809384346008f, -0.013804072514176f, 0.999798655509949f, -0.014187417924404f, + 0.999787628650665f, -0.014570754021406f, 0.999776303768158f, -0.014954082667828f, + 0.999764680862427f, -0.015337402001023f, 0.999752819538116f, -0.015720712020993f, + 0.999740600585938f, -0.016104012727737f, 0.999728083610535f, -0.016487304121256f, + 0.999715328216553f, -0.016870586201549f, 0.999702215194702f, -0.017253857105970f, + 0.999688863754272f, -0.017637118697166f, 0.999675154685974f, -0.018020370975137f, + 0.999661207199097f, -0.018403612077236f, 0.999646902084351f, -0.018786842003465f, + 0.999632358551025f, -0.019170060753822f, 0.999617516994476f, -0.019553268328309f, + 0.999602377414703f, -0.019936462864280f, 0.999586939811707f, -0.020319648087025f, + 0.999571204185486f, -0.020702820271254f, 0.999555170536041f, -0.021085981279612f, + 0.999538838863373f, -0.021469129249454f, 0.999522268772125f, -0.021852264180779f, + 0.999505341053009f, -0.022235386073589f, 0.999488115310669f, -0.022618494927883f, + 0.999470651149750f, -0.023001590743661f, 0.999452829360962f, -0.023384673520923f, + 0.999434769153595f, -0.023767741397023f, 0.999416410923004f, -0.024150796234608f, + 0.999397754669189f, -0.024533838033676f, 0.999378740787506f, -0.024916863068938f, + 0.999359488487244f, -0.025299875065684f, 0.999339938163757f, -0.025682870298624f, + 0.999320089817047f, -0.026065852493048f, 0.999299943447113f, -0.026448817923665f, + 0.999279558658600f, -0.026831768453121f, 0.999258816242218f, -0.027214704081416f, + 0.999237775802612f, -0.027597622945905f, 0.999216496944427f, -0.027980525046587f, + 0.999194860458374f, -0.028363410383463f, 0.999172985553741f, -0.028746278956532f, + 0.999150753021240f, -0.029129132628441f, 0.999128282070160f, -0.029511967673898f, + 0.999105513095856f, -0.029894785955548f, 0.999082446098328f, -0.030277585610747f, + 0.999059081077576f, -0.030660368502140f, 0.999035418033600f, -0.031043132767081f, + 0.999011456966400f, -0.031425878405571f, 0.998987197875977f, -0.031808607280254f, + 0.998962640762329f, -0.032191313803196f, 0.998937785625458f, -0.032574005424976f, + 0.998912692070007f, -0.032956674695015f, 0.998887240886688f, -0.033339329063892f, + 0.998861551284790f, -0.033721961081028f, 0.998835504055023f, -0.034104570746422f, + 0.998809218406677f, -0.034487165510654f, 0.998782634735107f, -0.034869734197855f, + 0.998755753040314f, -0.035252287983894f, 0.998728513717651f, -0.035634815692902f, + 0.998701035976410f, -0.036017324775457f, 0.998673319816589f, -0.036399815231562f, + 0.998645246028900f, -0.036782283335924f, 0.998616874217987f, -0.037164725363255f, + 0.998588204383850f, -0.037547148764133f, 0.998559296131134f, -0.037929553538561f, + 0.998530030250549f, -0.038311932235956f, 0.998500525951386f, -0.038694288581610f, + 0.998470664024353f, -0.039076622575521f, 0.998440563678741f, -0.039458930492401f, + 0.998410165309906f, -0.039841219782829f, 0.998379468917847f, -0.040223482996225f, + 0.998348474502563f, -0.040605723857880f, 0.998317182064056f, -0.040987938642502f, + 0.998285591602325f, -0.041370131075382f, 0.998253703117371f, -0.041752301156521f, + 0.998221516609192f, -0.042134445160627f, 0.998189091682434f, -0.042516563087702f, + 0.998156309127808f, -0.042898654937744f, 0.998123228549957f, -0.043280724436045f, + 0.998089909553528f, -0.043662767857313f, 0.998056292533875f, -0.044044785201550f, + 0.998022377490997f, -0.044426776468754f, 0.997988104820251f, -0.044808741658926f, + 0.997953593730927f, -0.045190680772066f, 0.997918784618378f, -0.045572593808174f, + 0.997883677482605f, -0.045954477041960f, 0.997848331928253f, -0.046336337924004f, + 0.997812628746033f, -0.046718169003725f, 0.997776627540588f, -0.047099970281124f, + 0.997740387916565f, -0.047481749206781f, 0.997703790664673f, -0.047863494604826f, + 0.997666954994202f, -0.048245213925838f, 0.997629821300507f, -0.048626907169819f, + 0.997592389583588f, -0.049008570611477f, 0.997554600238800f, -0.049390204250813f, + 0.997516572475433f, -0.049771808087826f, 0.997478306293488f, -0.050153385847807f, + 0.997439682483673f, -0.050534930080175f, 0.997400760650635f, -0.050916448235512f, + 0.997361540794373f, -0.051297932863235f, 0.997322082519531f, -0.051679391413927f, + 0.997282266616821f, -0.052060816437006f, 0.997242212295532f, -0.052442211657763f, + 0.997201859951019f, -0.052823577076197f, 0.997161149978638f, -0.053204908967018f, + 0.997120201587677f, -0.053586211055517f, 0.997078955173492f, -0.053967483341694f, + 0.997037410736084f, -0.054348722100258f, 0.996995627880096f, -0.054729927331209f, + 0.996953487396240f, -0.055111102759838f, 0.996911048889160f, -0.055492244660854f, + 0.996868371963501f, -0.055873356759548f, 0.996825337409973f, -0.056254431605339f, + 0.996782064437866f, -0.056635476648808f, 0.996738493442535f, -0.057016488164663f, + 0.996694624423981f, -0.057397462427616f, 0.996650457382202f, -0.057778406888247f, + 0.996605992317200f, -0.058159314095974f, 0.996561229228973f, -0.058540191501379f, + 0.996516168117523f, -0.058921031653881f, 0.996470808982849f, -0.059301838278770f, + 0.996425211429596f, -0.059682607650757f, 0.996379256248474f, -0.060063343495131f, + 0.996333062648773f, -0.060444042086601f, 0.996286571025848f, -0.060824707150459f, + 0.996239781379700f, -0.061205338686705f, 0.996192693710327f, -0.061585929244757f, + 0.996145308017731f, -0.061966486275196f, 0.996097624301910f, -0.062347009778023f, + 0.996049642562866f, -0.062727488577366f, 0.996001422405243f, -0.063107937574387f, + 0.995952844619751f, -0.063488349318504f, 0.995904028415680f, -0.063868723809719f, + 0.995854854583740f, -0.064249053597450f, 0.995805442333221f, -0.064629353582859f, + 0.995755732059479f, -0.065009608864784f, 0.995705723762512f, -0.065389834344387f, + 0.995655417442322f, -0.065770015120506f, 0.995604813098907f, -0.066150158643723f, + 0.995553970336914f, -0.066530264914036f, 0.995502769947052f, -0.066910326480865f, + 0.995451331138611f, -0.067290350794792f, 0.995399534702301f, -0.067670337855816f, + 0.995347499847412f, -0.068050287663937f, 0.995295166969299f, -0.068430192768574f, + 0.995242536067963f, -0.068810060620308f, 0.995189607143402f, -0.069189883768559f, + 0.995136380195618f, -0.069569669663906f, 0.995082914829254f, -0.069949418306351f, + 0.995029091835022f, -0.070329122245312f, 0.994975030422211f, -0.070708781480789f, + 0.994920611381531f, -0.071088403463364f, 0.994865953922272f, -0.071467980742455f, + 0.994810998439789f, -0.071847513318062f, 0.994755744934082f, -0.072227008640766f, + 0.994700193405151f, -0.072606459259987f, 0.994644403457642f, -0.072985872626305f, + 0.994588255882263f, -0.073365233838558f, 0.994531810283661f, -0.073744557797909f, + 0.994475126266479f, -0.074123837053776f, 0.994418144226074f, -0.074503071606159f, + 0.994360864162445f, -0.074882268905640f, 0.994303286075592f, -0.075261414051056f, + 0.994245409965515f, -0.075640521943569f, 0.994187235832214f, -0.076019577682018f, + 0.994128763675690f, -0.076398596167564f, 0.994070053100586f, -0.076777562499046f, + 0.994010984897614f, -0.077156484127045f, 0.993951678276062f, -0.077535368502140f, + 0.993892073631287f, -0.077914200723171f, 0.993832170963287f, -0.078292988240719f, + 0.993771970272064f, -0.078671731054783f, 0.993711471557617f, -0.079050421714783f, + 0.993650734424591f, -0.079429075121880f, 0.993589639663696f, -0.079807676374912f, + 0.993528306484222f, -0.080186225473881f, 0.993466615676880f, -0.080564737319946f, + 0.993404686450958f, -0.080943197011948f, 0.993342459201813f, -0.081321612000465f, + 0.993279933929443f, -0.081699974834919f, 0.993217170238495f, -0.082078292965889f, + 0.993154048919678f, -0.082456558942795f, 0.993090689182281f, -0.082834780216217f, + 0.993026971817017f, -0.083212949335575f, 0.992963016033173f, -0.083591073751450f, + 0.992898762226105f, -0.083969146013260f, 0.992834210395813f, -0.084347173571587f, + 0.992769360542297f, -0.084725148975849f, 0.992704212665558f, -0.085103072226048f, + 0.992638826370239f, -0.085480943322182f, 0.992573142051697f, -0.085858769714832f, + 0.992507100105286f, -0.086236543953419f, 0.992440819740295f, -0.086614266037941f, + 0.992374241352081f, -0.086991935968399f, 0.992307364940643f, -0.087369553744793f, + 0.992240250110626f, -0.087747126817703f, 0.992172777652740f, -0.088124647736549f, + 0.992105066776276f, -0.088502109050751f, 0.992036998271942f, -0.088879525661469f, + 0.991968691349030f, -0.089256882667542f, 0.991900086402893f, -0.089634194970131f, + 0.991831183433533f, -0.090011447668076f, 0.991762042045593f, -0.090388655662537f, + 0.991692543029785f, -0.090765804052353f, 0.991622805595398f, -0.091142900288105f, + 0.991552770137787f, -0.091519944369793f, 0.991482377052307f, -0.091896936297417f, + 0.991411805152893f, -0.092273868620396f, 0.991340875625610f, -0.092650748789310f, + 0.991269648075104f, -0.093027576804161f, 0.991198182106018f, -0.093404345214367f, + 0.991126358509064f, -0.093781061470509f, 0.991054296493530f, -0.094157725572586f, + 0.990981936454773f, -0.094534330070019f, 0.990909278392792f, -0.094910882413387f, + 0.990836322307587f, -0.095287375152111f, 0.990763127803802f, -0.095663815736771f, + 0.990689575672150f, -0.096040196716785f, 0.990615785121918f, -0.096416525542736f, + 0.990541696548462f, -0.096792794764042f, 0.990467309951782f, -0.097169004380703f, + 0.990392625331879f, -0.097545161843300f, 0.990317702293396f, -0.097921259701252f, + 0.990242421627045f, -0.098297297954559f, 0.990166902542114f, -0.098673284053802f, + 0.990091085433960f, -0.099049203097820f, 0.990014970302582f, -0.099425069987774f, + 0.989938557147980f, -0.099800877273083f, 0.989861845970154f, -0.100176624953747f, + 0.989784896373749f, -0.100552320480347f, 0.989707589149475f, -0.100927948951721f, + 0.989630043506622f, -0.101303517818451f, 0.989552199840546f, -0.101679034531116f, + 0.989474058151245f, -0.102054484188557f, 0.989395678043365f, -0.102429874241352f, + 0.989316940307617f, -0.102805204689503f, 0.989237964153290f, -0.103180475533009f, + 0.989158689975739f, -0.103555686771870f, 0.989079117774963f, -0.103930838406086f, + 0.988999247550964f, -0.104305922985077f, 0.988919138908386f, -0.104680955410004f, + 0.988838672637939f, -0.105055920779705f, 0.988757967948914f, -0.105430819094181f, + 0.988676965236664f, -0.105805665254593f, 0.988595664501190f, -0.106180444359779f, + 0.988514065742493f, -0.106555156409740f, 0.988432228565216f, -0.106929816305637f, + 0.988350033760071f, -0.107304409146309f, 0.988267600536346f, -0.107678934931755f, + 0.988184869289398f, -0.108053401112556f, 0.988101840019226f, -0.108427800238132f, + 0.988018512725830f, -0.108802139759064f, 0.987934947013855f, -0.109176412224770f, + 0.987851083278656f, -0.109550617635250f, 0.987766921520233f, -0.109924763441086f, + 0.987682461738586f, -0.110298842191696f, 0.987597703933716f, -0.110672861337662f, + 0.987512648105621f, -0.111046813428402f, 0.987427353858948f, -0.111420698463917f, + 0.987341761589050f, -0.111794516444206f, 0.987255871295929f, -0.112168267369270f, + 0.987169682979584f, -0.112541958689690f, 0.987083256244659f, -0.112915575504303f, + 0.986996471881866f, -0.113289132714272f, 0.986909449100494f, -0.113662622869015f, + 0.986822128295898f, -0.114036038517952f, 0.986734509468079f, -0.114409394562244f, + 0.986646652221680f, -0.114782683551311f, 0.986558437347412f, -0.115155905485153f, + 0.986469984054565f, -0.115529052913189f, 0.986381232738495f, -0.115902140736580f, + 0.986292183399200f, -0.116275154054165f, 0.986202836036682f, -0.116648100316525f, + 0.986113250255585f, -0.117020979523659f, 0.986023366451263f, -0.117393791675568f, + 0.985933184623718f, -0.117766529321671f, 0.985842704772949f, -0.118139199912548f, + 0.985751926898956f, -0.118511803448200f, 0.985660910606384f, -0.118884332478046f, + 0.985569596290588f, -0.119256794452667f, 0.985477983951569f, -0.119629189372063f, + 0.985386073589325f, -0.120001509785652f, 0.985293865203857f, -0.120373763144016f, + 0.985201418399811f, -0.120745941996574f, 0.985108673572540f, -0.121118053793907f, + 0.985015630722046f, -0.121490091085434f, 0.984922289848328f, -0.121862053871155f, + 0.984828710556030f, -0.122233949601650f, 0.984734773635864f, -0.122605770826340f, + 0.984640598297119f, -0.122977524995804f, 0.984546124935150f, -0.123349204659462f, + 0.984451413154602f, -0.123720809817314f, 0.984356343746185f, -0.124092340469360f, + 0.984261035919189f, -0.124463804066181f, 0.984165430068970f, -0.124835193157196f, + 0.984069526195526f, -0.125206500291824f, 0.983973383903503f, -0.125577747821808f, + 0.983876943588257f, -0.125948905944824f, 0.983780145645142f, -0.126320004463196f, + 0.983683168888092f, -0.126691013574600f, 0.983585834503174f, -0.127061963081360f, + 0.983488261699677f, -0.127432823181152f, 0.983390331268311f, -0.127803623676300f, + 0.983292162418365f, -0.128174334764481f, 0.983193755149841f, -0.128544986248016f, + 0.983094990253448f, -0.128915548324585f, 0.982995986938477f, -0.129286035895348f, + 0.982896685600281f, -0.129656463861465f, 0.982797086238861f, -0.130026802420616f, + 0.982697248458862f, -0.130397051572800f, 0.982597053050995f, -0.130767241120338f, + 0.982496619224548f, -0.131137356162071f, 0.982395887374878f, -0.131507381796837f, + 0.982294917106628f, -0.131877332925797f, 0.982193589210510f, -0.132247209548950f, + 0.982092022895813f, -0.132617011666298f, 0.981990158557892f, -0.132986739277840f, + 0.981888055801392f, -0.133356377482414f, 0.981785595417023f, -0.133725941181183f, + 0.981682896614075f, -0.134095430374146f, 0.981579899787903f, -0.134464830160141f, + 0.981476604938507f, -0.134834155440331f, 0.981373071670532f, -0.135203406214714f, + 0.981269240379334f, -0.135572582483292f, 0.981165111064911f, -0.135941669344902f, + 0.981060683727264f, -0.136310681700706f, 0.980956017971039f, -0.136679604649544f, + 0.980851054191589f, -0.137048453092575f, 0.980745792388916f, -0.137417227029800f, + 0.980640232563019f, -0.137785911560059f, 0.980534434318542f, -0.138154521584511f, + 0.980428338050842f, -0.138523042201996f, 0.980321943759918f, -0.138891488313675f, + 0.980215251445770f, -0.139259845018387f, 0.980108320713043f, -0.139628127217293f, + 0.980001091957092f, -0.139996320009232f, 0.979893565177917f, -0.140364438295364f, + 0.979785740375519f, -0.140732467174530f, 0.979677677154541f, -0.141100421547890f, + 0.979569315910339f, -0.141468286514282f, 0.979460656642914f, -0.141836062073708f, + 0.979351758956909f, -0.142203763127327f, 0.979242503643036f, -0.142571389675140f, + 0.979133009910584f, -0.142938911914825f, 0.979023277759552f, -0.143306359648705f, + 0.978913187980652f, -0.143673732876778f, 0.978802859783173f, -0.144041016697884f, + 0.978692233562469f, -0.144408211112022f, 0.978581368923187f, -0.144775316119194f, + 0.978470146656036f, -0.145142331719399f, 0.978358685970306f, -0.145509272813797f, + 0.978246986865997f, -0.145876124501228f, 0.978134930133820f, -0.146242901682854f, + 0.978022634983063f, -0.146609574556351f, 0.977910041809082f, -0.146976172924042f, + 0.977797150611877f, -0.147342681884766f, 0.977684020996094f, -0.147709101438522f, + 0.977570593357086f, -0.148075446486473f, 0.977456867694855f, -0.148441687226295f, + 0.977342903614044f, -0.148807853460312f, 0.977228581905365f, -0.149173930287361f, + 0.977114021778107f, -0.149539917707443f, 0.976999223232269f, -0.149905815720558f, + 0.976884067058563f, -0.150271624326706f, 0.976768672466278f, -0.150637343525887f, + 0.976653039455414f, -0.151002973318100f, 0.976537048816681f, -0.151368513703346f, + 0.976420819759369f, -0.151733979582787f, 0.976304292678833f, -0.152099341154099f, + 0.976187527179718f, -0.152464613318443f, 0.976070404052734f, -0.152829796075821f, + 0.975953042507172f, -0.153194904327393f, 0.975835442543030f, -0.153559908270836f, + 0.975717484951019f, -0.153924822807312f, 0.975599288940430f, -0.154289647936821f, + 0.975480854511261f, -0.154654383659363f, 0.975362062454224f, -0.155019029974937f, + 0.975243031978607f, -0.155383571982384f, 0.975123703479767f, -0.155748039484024f, + 0.975004136562347f, -0.156112402677536f, 0.974884271621704f, -0.156476691365242f, + 0.974764108657837f, -0.156840875744820f, 0.974643647670746f, -0.157204970717430f, + 0.974522948265076f, -0.157568961381912f, 0.974401950836182f, -0.157932877540588f, + 0.974280655384064f, -0.158296689391136f, 0.974159121513367f, -0.158660411834717f, + 0.974037289619446f, -0.159024044871330f, 0.973915159702301f, -0.159387573599815f, + 0.973792791366577f, -0.159751012921333f, 0.973670125007629f, -0.160114362835884f, + 0.973547160625458f, -0.160477623343468f, 0.973423957824707f, -0.160840779542923f, + 0.973300457000732f, -0.161203846335411f, 0.973176658153534f, -0.161566808819771f, + 0.973052620887756f, -0.161929681897163f, 0.972928285598755f, -0.162292465567589f, + 0.972803652286530f, -0.162655144929886f, 0.972678780555725f, -0.163017734885216f, + 0.972553610801697f, -0.163380220532417f, 0.972428143024445f, -0.163742616772652f, + 0.972302436828613f, -0.164104923605919f, 0.972176432609558f, -0.164467126131058f, + 0.972050130367279f, -0.164829224348068f, 0.971923589706421f, -0.165191248059273f, + 0.971796751022339f, -0.165553152561188f, 0.971669614315033f, -0.165914967656136f, + 0.971542239189148f, -0.166276678442955f, 0.971414566040039f, -0.166638299822807f, + 0.971286594867706f, -0.166999831795692f, 0.971158385276794f, -0.167361244559288f, + 0.971029877662659f, -0.167722567915916f, 0.970901072025299f, -0.168083801865578f, + 0.970772027969360f, -0.168444931507111f, 0.970642685890198f, -0.168805956840515f, + 0.970513105392456f, -0.169166877865791f, 0.970383226871490f, -0.169527709484100f, + 0.970253050327301f, -0.169888436794281f, 0.970122575759888f, -0.170249074697495f, + 0.969991862773895f, -0.170609608292580f, 0.969860911369324f, -0.170970037579536f, + 0.969729602336884f, -0.171330362558365f, 0.969598054885864f, -0.171690583229065f, + 0.969466269016266f, -0.172050714492798f, 0.969334125518799f, -0.172410741448402f, + 0.969201743602753f, -0.172770664095879f, 0.969069123268127f, -0.173130482435226f, + 0.968936204910278f, -0.173490211367607f, 0.968802988529205f, -0.173849821090698f, + 0.968669533729553f, -0.174209341406822f, 0.968535780906677f, -0.174568757414818f, + 0.968401730060577f, -0.174928069114685f, 0.968267440795898f, -0.175287276506424f, + 0.968132853507996f, -0.175646379590034f, 0.967997968196869f, -0.176005378365517f, + 0.967862844467163f, -0.176364272832870f, 0.967727422714233f, -0.176723077893257f, + 0.967591762542725f, -0.177081763744354f, 0.967455804347992f, -0.177440345287323f, + 0.967319548130035f, -0.177798837423325f, 0.967183053493500f, -0.178157210350037f, + 0.967046260833740f, -0.178515478968620f, 0.966909229755402f, -0.178873643279076f, + 0.966771900653839f, -0.179231703281403f, 0.966634273529053f, -0.179589673876762f, + 0.966496407985687f, -0.179947525262833f, 0.966358244419098f, -0.180305257439613f, + 0.966219842433929f, -0.180662900209427f, 0.966081082820892f, -0.181020438671112f, + 0.965942144393921f, -0.181377857923508f, 0.965802907943726f, -0.181735187768936f, + 0.965663373470306f, -0.182092398405075f, 0.965523540973663f, -0.182449504733086f, + 0.965383470058441f, -0.182806491851807f, 0.965243160724640f, -0.183163389563560f, + 0.965102493762970f, -0.183520168066025f, 0.964961588382721f, -0.183876842260361f, + 0.964820444583893f, -0.184233412146568f, 0.964679002761841f, -0.184589877724648f, + 0.964537262916565f, -0.184946224093437f, 0.964395284652710f, -0.185302466154099f, + 0.964253067970276f, -0.185658603906631f, 0.964110493659973f, -0.186014622449875f, + 0.963967680931091f, -0.186370536684990f, 0.963824629783630f, -0.186726331710815f, + 0.963681280612946f, -0.187082037329674f, 0.963537633419037f, -0.187437608838081f, + 0.963393747806549f, -0.187793090939522f, 0.963249564170837f, -0.188148453831673f, + 0.963105142116547f, -0.188503712415695f, 0.962960422039032f, -0.188858851790428f, + 0.962815403938293f, -0.189213871955872f, 0.962670147418976f, -0.189568802714348f, + 0.962524592876434f, -0.189923599362373f, 0.962378799915314f, -0.190278306603432f, + 0.962232708930969f, -0.190632879734039f, 0.962086379528046f, -0.190987363457680f, + 0.961939752101898f, -0.191341713070869f, 0.961792886257172f, -0.191695958375931f, + 0.961645722389221f, -0.192050099372864f, 0.961498260498047f, -0.192404121160507f, + 0.961350560188293f, -0.192758023738861f, 0.961202561855316f, -0.193111822009087f, + 0.961054325103760f, -0.193465501070023f, 0.960905790328979f, -0.193819075822830f, + 0.960757017135620f, -0.194172516465187f, 0.960607945919037f, -0.194525867700577f, + 0.960458636283875f, -0.194879084825516f, 0.960309028625488f, -0.195232197642326f, + 0.960159122943878f, -0.195585191249847f, 0.960008978843689f, -0.195938065648079f, + 0.959858596324921f, -0.196290835738182f, 0.959707856178284f, -0.196643486618996f, + 0.959556937217712f, -0.196996018290520f, 0.959405720233917f, -0.197348430752754f, + 0.959254205226898f, -0.197700738906860f, 0.959102451801300f, -0.198052927851677f, + 0.958950400352478f, -0.198404997587204f, 0.958798050880432f, -0.198756948113441f, + 0.958645522594452f, -0.199108779430389f, 0.958492636680603f, -0.199460506439209f, + 0.958339512348175f, -0.199812099337578f, 0.958186149597168f, -0.200163587927818f, + 0.958032488822937f, -0.200514942407608f, 0.957878530025482f, -0.200866192579269f, + 0.957724332809448f, -0.201217323541641f, 0.957569897174835f, -0.201568335294724f, + 0.957415163516998f, -0.201919227838516f, 0.957260131835938f, -0.202270001173019f, + 0.957104861736298f, -0.202620655298233f, 0.956949353218079f, -0.202971190214157f, + 0.956793546676636f, -0.203321605920792f, 0.956637442111969f, -0.203671902418137f, + 0.956481099128723f, -0.204022079706192f, 0.956324458122253f, -0.204372137784958f, + 0.956167578697205f, -0.204722076654434f, 0.956010460853577f, -0.205071896314621f, + 0.955853044986725f, -0.205421581864357f, 0.955695331096649f, -0.205771163105965f, + 0.955537378787994f, -0.206120610237122f, 0.955379128456116f, -0.206469938158989f, + 0.955220639705658f, -0.206819161772728f, 0.955061912536621f, -0.207168251276016f, + 0.954902827739716f, -0.207517206668854f, 0.954743564128876f, -0.207866057753563f, + 0.954584002494812f, -0.208214774727821f, 0.954424142837524f, -0.208563387393951f, + 0.954264044761658f, -0.208911851048470f, 0.954103708267212f, -0.209260210394859f, + 0.953943073749542f, -0.209608450531960f, 0.953782141208649f, -0.209956556558609f, + 0.953620970249176f, -0.210304543375969f, 0.953459560871124f, -0.210652396082878f, + 0.953297853469849f, -0.211000129580498f, 0.953135907649994f, -0.211347743868828f, + 0.952973663806915f, -0.211695238947868f, 0.952811121940613f, -0.212042599916458f, + 0.952648401260376f, -0.212389841675758f, 0.952485322952271f, -0.212736949324608f, + 0.952322065830231f, -0.213083937764168f, 0.952158451080322f, -0.213430806994438f, + 0.951994657516479f, -0.213777542114258f, 0.951830565929413f, -0.214124158024788f, + 0.951666176319122f, -0.214470639824867f, 0.951501548290253f, -0.214817002415657f, + 0.951336681842804f, -0.215163245797157f, 0.951171517372131f, -0.215509355068207f, + 0.951006054878235f, -0.215855330228806f, 0.950840353965759f, -0.216201186180115f, + 0.950674414634705f, -0.216546908020973f, 0.950508177280426f, -0.216892510652542f, + 0.950341701507568f, -0.217237979173660f, 0.950174987316132f, -0.217583328485489f, + 0.950007975101471f, -0.217928543686867f, 0.949840664863586f, -0.218273624777794f, + 0.949673116207123f, -0.218618586659431f, 0.949505329132080f, -0.218963414430618f, + 0.949337244033813f, -0.219308122992516f, 0.949168920516968f, -0.219652697443962f, + 0.949000298976898f, -0.219997137784958f, 0.948831439018250f, -0.220341444015503f, + 0.948662281036377f, -0.220685631036758f, 0.948492884635925f, -0.221029683947563f, + 0.948323249816895f, -0.221373617649078f, 0.948153316974640f, -0.221717402338982f, + 0.947983145713806f, -0.222061067819595f, 0.947812676429749f, -0.222404599189758f, + 0.947641968727112f, -0.222748011350632f, 0.947470963001251f, -0.223091274499893f, + 0.947299718856812f, -0.223434418439865f, 0.947128236293793f, -0.223777428269386f, + 0.946956455707550f, -0.224120303988457f, 0.946784436702728f, -0.224463045597076f, + 0.946612179279327f, -0.224805667996407f, 0.946439623832703f, -0.225148141384125f, + 0.946266770362854f, -0.225490495562553f, 0.946093678474426f, -0.225832715630531f, + 0.945920348167419f, -0.226174786686897f, 0.945746779441834f, -0.226516738533974f, + 0.945572853088379f, -0.226858556270599f, 0.945398747920990f, -0.227200239896774f, + 0.945224344730377f, -0.227541789412498f, 0.945049703121185f, -0.227883204817772f, + 0.944874763488770f, -0.228224486112595f, 0.944699645042419f, -0.228565633296967f, + 0.944524168968201f, -0.228906646370888f, 0.944348454475403f, -0.229247525334358f, + 0.944172501564026f, -0.229588270187378f, 0.943996310234070f, -0.229928880929947f, + 0.943819820880890f, -0.230269357562065f, 0.943643093109131f, -0.230609700083733f, + 0.943466067314148f, -0.230949893593788f, 0.943288803100586f, -0.231289967894554f, + 0.943111240863800f, -0.231629893183708f, 0.942933499813080f, -0.231969684362412f, + 0.942755401134491f, -0.232309341430664f, 0.942577123641968f, -0.232648864388466f, + 0.942398548126221f, -0.232988253235817f, 0.942219734191895f, -0.233327493071556f, + 0.942040622234344f, -0.233666598796844f, 0.941861271858215f, -0.234005570411682f, + 0.941681683063507f, -0.234344407916069f, 0.941501796245575f, -0.234683111310005f, + 0.941321671009064f, -0.235021665692329f, 0.941141307353973f, -0.235360085964203f, + 0.940960645675659f, -0.235698372125626f, 0.940779745578766f, -0.236036509275436f, + 0.940598547458649f, -0.236374512314796f, 0.940417110919952f, -0.236712381243706f, + 0.940235435962677f, -0.237050101161003f, 0.940053522586823f, -0.237387686967850f, + 0.939871311187744f, -0.237725138664246f, 0.939688861370087f, -0.238062441349030f, + 0.939506113529205f, -0.238399609923363f, 0.939323127269745f, -0.238736644387245f, + 0.939139902591705f, -0.239073529839516f, 0.938956379890442f, -0.239410281181335f, + 0.938772618770599f, -0.239746883511543f, 0.938588619232178f, -0.240083336830139f, + 0.938404381275177f, -0.240419670939446f, 0.938219845294952f, -0.240755841135979f, + 0.938035070896149f, -0.241091892123222f, 0.937849998474121f, -0.241427779197693f, + 0.937664687633514f, -0.241763532161713f, 0.937479138374329f, -0.242099151015282f, + 0.937293350696564f, -0.242434620857239f, 0.937107264995575f, -0.242769956588745f, + 0.936920940876007f, -0.243105143308640f, 0.936734318733215f, -0.243440181016922f, + 0.936547517776489f, -0.243775084614754f, 0.936360359191895f, -0.244109839200974f, + 0.936173021793365f, -0.244444444775581f, 0.935985386371613f, -0.244778916239738f, + 0.935797572135925f, -0.245113238692284f, 0.935609400272369f, -0.245447427034378f, + 0.935421049594879f, -0.245781451463699f, 0.935232400894165f, -0.246115356683731f, + 0.935043513774872f, -0.246449097990990f, 0.934854328632355f, -0.246782705187798f, + 0.934664964675903f, -0.247116148471832f, 0.934475243091583f, -0.247449472546577f, + 0.934285342693329f, -0.247782632708550f, 0.934095203876495f, -0.248115643858910f, + 0.933904767036438f, -0.248448520898819f, 0.933714091777802f, -0.248781248927116f, + 0.933523118495941f, -0.249113827943802f, 0.933331906795502f, -0.249446272850037f, + 0.933140456676483f, -0.249778553843498f, 0.932948768138886f, -0.250110685825348f, + 0.932756841182709f, -0.250442683696747f, 0.932564616203308f, -0.250774532556534f, + 0.932372152805328f, -0.251106232404709f, 0.932179391384125f, -0.251437783241272f, + 0.931986451148987f, -0.251769185066223f, 0.931793212890625f, -0.252100437879562f, + 0.931599736213684f, -0.252431541681290f, 0.931405961513519f, -0.252762526273727f, + 0.931211948394775f, -0.253093332052231f, 0.931017756462097f, -0.253423988819122f, + 0.930823206901550f, -0.253754496574402f, 0.930628478527069f, -0.254084855318069f, + 0.930433452129364f, -0.254415065050125f, 0.930238187313080f, -0.254745125770569f, + 0.930042684078217f, -0.255075037479401f, 0.929846942424774f, -0.255404800176620f, + 0.929650902748108f, -0.255734413862228f, 0.929454624652863f, -0.256063878536224f, + 0.929258108139038f, -0.256393194198608f, 0.929061353206635f, -0.256722360849380f, + 0.928864300251007f, -0.257051378488541f, 0.928667008876801f, -0.257380217313766f, + 0.928469479084015f, -0.257708936929703f, 0.928271710872650f, -0.258037507534027f, + 0.928073644638062f, -0.258365899324417f, 0.927875399589539f, -0.258694142103195f, + 0.927676856517792f, -0.259022265672684f, 0.927478015422821f, -0.259350210428238f, + 0.927278995513916f, -0.259678006172180f, 0.927079677581787f, -0.260005623102188f, + 0.926880121231079f, -0.260333120822906f, 0.926680326461792f, -0.260660469532013f, + 0.926480293273926f, -0.260987639427185f, 0.926280021667480f, -0.261314690113068f, + 0.926079452037811f, -0.261641561985016f, 0.925878643989563f, -0.261968284845352f, + 0.925677597522736f, -0.262294828891754f, 0.925476312637329f, -0.262621253728867f, + 0.925274729728699f, -0.262947499752045f, 0.925072908401489f, -0.263273626565933f, + 0.924870908260345f, -0.263599574565887f, 0.924668610095978f, -0.263925373554230f, + 0.924466013908386f, -0.264250993728638f, 0.924263238906860f, -0.264576494693756f, + 0.924060165882111f, -0.264901816844940f, 0.923856854438782f, -0.265226989984512f, + 0.923653304576874f, -0.265552014112473f, 0.923449516296387f, -0.265876859426498f, + 0.923245489597321f, -0.266201555728912f, 0.923041164875031f, -0.266526103019714f, + 0.922836601734161f, -0.266850501298904f, 0.922631800174713f, -0.267174720764160f, + 0.922426760196686f, -0.267498821020126f, 0.922221481800079f, -0.267822742462158f, + 0.922015964984894f, -0.268146485090256f, 0.921810150146484f, -0.268470078706741f, + 0.921604096889496f, -0.268793523311615f, 0.921397805213928f, -0.269116818904877f, + 0.921191275119781f, -0.269439965486526f, 0.920984506607056f, -0.269762933254242f, + 0.920777499675751f, -0.270085722208023f, 0.920570194721222f, -0.270408391952515f, + 0.920362710952759f, -0.270730882883072f, 0.920154929161072f, -0.271053224802017f, + 0.919946908950806f, -0.271375387907028f, 0.919738650321960f, -0.271697402000427f, + 0.919530093669891f, -0.272019267082214f, 0.919321358203888f, -0.272340953350067f, + 0.919112324714661f, -0.272662490606308f, 0.918903112411499f, -0.272983878850937f, + 0.918693602085114f, -0.273305088281631f, 0.918483853340149f, -0.273626148700714f, + 0.918273866176605f, -0.273947030305862f, 0.918063640594482f, -0.274267762899399f, + 0.917853116989136f, -0.274588316679001f, 0.917642414569855f, -0.274908751249313f, + 0.917431414127350f, -0.275228977203369f, 0.917220234870911f, -0.275549083948135f, + 0.917008757591248f, -0.275868982076645f, 0.916797041893005f, -0.276188760995865f, + 0.916585087776184f, -0.276508361101151f, 0.916372895240784f, -0.276827782392502f, + 0.916160404682159f, -0.277147054672241f, 0.915947735309601f, -0.277466177940369f, + 0.915734827518463f, -0.277785122394562f, 0.915521621704102f, -0.278103888034821f, + 0.915308177471161f, -0.278422504663467f, 0.915094554424286f, -0.278740972280502f, + 0.914880633354187f, -0.279059261083603f, 0.914666473865509f, -0.279377400875092f, + 0.914452075958252f, -0.279695361852646f, 0.914237439632416f, -0.280013144016266f, + 0.914022505283356f, -0.280330777168274f, 0.913807392120361f, -0.280648261308670f, + 0.913592040538788f, -0.280965566635132f, 0.913376390933990f, -0.281282693147659f, + 0.913160502910614f, -0.281599670648575f, 0.912944436073303f, -0.281916469335556f, + 0.912728071212769f, -0.282233119010925f, 0.912511467933655f, -0.282549589872360f, + 0.912294626235962f, -0.282865911722183f, 0.912077546119690f, -0.283182054758072f, + 0.911860227584839f, -0.283498018980026f, 0.911642670631409f, -0.283813834190369f, + 0.911424875259399f, -0.284129470586777f, 0.911206841468811f, -0.284444957971573f, + 0.910988569259644f, -0.284760266542435f, 0.910769999027252f, -0.285075396299362f, + 0.910551249980927f, -0.285390377044678f, 0.910332262516022f, -0.285705178976059f, + 0.910112977027893f, -0.286019802093506f, 0.909893512725830f, -0.286334276199341f, + 0.909673750400543f, -0.286648571491241f, 0.909453809261322f, -0.286962717771530f, + 0.909233570098877f, -0.287276685237885f, 0.909013092517853f, -0.287590473890305f, + 0.908792436122894f, -0.287904083728790f, 0.908571481704712f, -0.288217544555664f, + 0.908350288867950f, -0.288530826568604f, 0.908128857612610f, -0.288843959569931f, + 0.907907187938690f, -0.289156883955002f, 0.907685279846191f, -0.289469659328461f, + 0.907463192939758f, -0.289782285690308f, 0.907240808010101f, -0.290094703435898f, + 0.907018184661865f, -0.290406972169876f, 0.906795322895050f, -0.290719062089920f, + 0.906572222709656f, -0.291031002998352f, 0.906348884105682f, -0.291342735290527f, + 0.906125307083130f, -0.291654318571091f, 0.905901491641998f, -0.291965723037720f, + 0.905677437782288f, -0.292276978492737f, 0.905453145503998f, -0.292588025331497f, + 0.905228614807129f, -0.292898923158646f, 0.905003845691681f, -0.293209642171860f, + 0.904778838157654f, -0.293520182371140f, 0.904553592205048f, -0.293830573558807f, + 0.904328107833862f, -0.294140785932541f, 0.904102385044098f, -0.294450789690018f, + 0.903876423835754f, -0.294760644435883f, 0.903650224208832f, -0.295070350170136f, + 0.903423786163330f, -0.295379847288132f, 0.903197109699249f, -0.295689195394516f, + 0.902970194816589f, -0.295998334884644f, 0.902743041515350f, -0.296307325363159f, + 0.902515649795532f, -0.296616137027740f, 0.902288019657135f, -0.296924799680710f, + 0.902060210704803f, -0.297233253717422f, 0.901832103729248f, -0.297541528940201f, + 0.901603758335114f, -0.297849655151367f, 0.901375174522400f, -0.298157602548599f, + 0.901146411895752f, -0.298465341329575f, 0.900917351245880f, -0.298772931098938f, + 0.900688111782074f, -0.299080342054367f, 0.900458574295044f, -0.299387603998184f, + 0.900228857994080f, -0.299694657325745f, 0.899998843669891f, -0.300001531839371f, + 0.899768650531769f, -0.300308227539063f, 0.899538159370422f, -0.300614774227142f, + 0.899307489395142f, -0.300921112298965f, 0.899076581001282f, -0.301227301359177f, + 0.898845434188843f, -0.301533311605453f, 0.898614048957825f, -0.301839113235474f, + 0.898382425308228f, -0.302144765853882f, 0.898150563240051f, -0.302450239658356f, + 0.897918462753296f, -0.302755534648895f, 0.897686123847961f, -0.303060621023178f, + 0.897453546524048f, -0.303365558385849f, 0.897220790386200f, -0.303670316934586f, + 0.896987736225128f, -0.303974896669388f, 0.896754503250122f, -0.304279297590256f, + 0.896520972251892f, -0.304583519697189f, 0.896287262439728f, -0.304887533187866f, + 0.896053314208984f, -0.305191397666931f, 0.895819067955017f, -0.305495083332062f, + 0.895584642887115f, -0.305798590183258f, 0.895349979400635f, -0.306101888418198f, + 0.895115137100220f, -0.306405037641525f, 0.894879996776581f, -0.306708008050919f, + 0.894644618034363f, -0.307010769844055f, 0.894409060478210f, -0.307313382625580f, + 0.894173204898834f, -0.307615786790848f, 0.893937170505524f, -0.307918041944504f, + 0.893700897693634f, -0.308220088481903f, 0.893464326858521f, -0.308521956205368f, + 0.893227577209473f, -0.308823645114899f, 0.892990648746490f, -0.309125155210495f, + 0.892753422260284f, -0.309426486492157f, 0.892515957355499f, -0.309727638959885f, + 0.892278313636780f, -0.310028612613678f, 0.892040371894836f, -0.310329377651215f, + 0.891802251338959f, -0.310629993677139f, 0.891563892364502f, -0.310930401086807f, + 0.891325294971466f, -0.311230629682541f, 0.891086459159851f, -0.311530679464340f, + 0.890847444534302f, -0.311830550432205f, 0.890608131885529f, -0.312130242586136f, + 0.890368640422821f, -0.312429755926132f, 0.890128850936890f, -0.312729060649872f, + 0.889888882637024f, -0.313028186559677f, 0.889648675918579f, -0.313327133655548f, + 0.889408230781555f, -0.313625901937485f, 0.889167606830597f, -0.313924491405487f, + 0.888926684856415f, -0.314222872257233f, 0.888685584068298f, -0.314521104097366f, + 0.888444244861603f, -0.314819127321243f, 0.888202667236328f, -0.315116971731186f, + 0.887960851192474f, -0.315414607524872f, 0.887718796730042f, -0.315712094306946f, + 0.887476563453674f, -0.316009372472763f, 0.887234091758728f, -0.316306471824646f, + 0.886991322040558f, -0.316603392362595f, 0.886748373508453f, -0.316900104284287f, + 0.886505246162415f, -0.317196637392044f, 0.886261820793152f, -0.317492991685867f, + 0.886018216609955f, -0.317789167165756f, 0.885774314403534f, -0.318085134029388f, + 0.885530233383179f, -0.318380922079086f, 0.885285973548889f, -0.318676531314850f, + 0.885041415691376f, -0.318971961736679f, 0.884796679019928f, -0.319267183542252f, + 0.884551644325256f, -0.319562226533890f, 0.884306430816650f, -0.319857090711594f, + 0.884061038494110f, -0.320151746273041f, 0.883815348148346f, -0.320446223020554f, + 0.883569478988647f, -0.320740520954132f, 0.883323311805725f, -0.321034610271454f, + 0.883076965808868f, -0.321328520774841f, 0.882830440998077f, -0.321622252464294f, + 0.882583618164063f, -0.321915775537491f, 0.882336616516113f, -0.322209119796753f, + 0.882089376449585f, -0.322502255439758f, 0.881841897964478f, -0.322795242071152f, + 0.881594181060791f, -0.323088020086288f, 0.881346285343170f, -0.323380589485168f, + 0.881098151206970f, -0.323672980070114f, 0.880849778652191f, -0.323965191841125f, + 0.880601167678833f, -0.324257194995880f, 0.880352377891541f, -0.324549019336700f, + 0.880103349685669f, -0.324840664863586f, 0.879854083061218f, -0.325132101774216f, + 0.879604578018188f, -0.325423330068588f, 0.879354894161224f, -0.325714409351349f, + 0.879104971885681f, -0.326005280017853f, 0.878854811191559f, -0.326295942068100f, + 0.878604412078857f, -0.326586425304413f, 0.878353834152222f, -0.326876699924469f, + 0.878103017807007f, -0.327166795730591f, 0.877851963043213f, -0.327456712722778f, + 0.877600669860840f, -0.327746421098709f, 0.877349197864532f, -0.328035950660706f, + 0.877097487449646f, -0.328325271606445f, 0.876845538616180f, -0.328614413738251f, + 0.876593410968781f, -0.328903347253799f, 0.876341044902802f, -0.329192101955414f, + 0.876088440418243f, -0.329480648040771f, 0.875835597515106f, -0.329769015312195f, + 0.875582575798035f, -0.330057173967361f, 0.875329315662384f, -0.330345153808594f, + 0.875075817108154f, -0.330632925033569f, 0.874822139739990f, -0.330920487642288f, + 0.874568223953247f, -0.331207901239395f, 0.874314069747925f, -0.331495076417923f, + 0.874059677124023f, -0.331782072782516f, 0.873805105686188f, -0.332068890333176f, + 0.873550295829773f, -0.332355499267578f, 0.873295307159424f, -0.332641899585724f, + 0.873040020465851f, -0.332928121089935f, 0.872784554958344f, -0.333214133977890f, + 0.872528910636902f, -0.333499968051910f, 0.872272968292236f, -0.333785593509674f, + 0.872016847133636f, -0.334071010351181f, 0.871760547161102f, -0.334356248378754f, + 0.871503949165344f, -0.334641307592392f, 0.871247172355652f, -0.334926128387451f, + 0.870990216732025f, -0.335210770368576f, 0.870733022689819f, -0.335495233535767f, + 0.870475590229034f, -0.335779488086700f, 0.870217919349670f, -0.336063534021378f, + 0.869960069656372f, -0.336347371339798f, 0.869701981544495f, -0.336631029844284f, + 0.869443655014038f, -0.336914509534836f, 0.869185149669647f, -0.337197750806808f, + 0.868926405906677f, -0.337480813264847f, 0.868667483329773f, -0.337763696908951f, + 0.868408262729645f, -0.338046342134476f, 0.868148922920227f, -0.338328808546066f, + 0.867889285087585f, -0.338611096143723f, 0.867629468441010f, -0.338893145322800f, + 0.867369413375854f, -0.339175015687943f, 0.867109179496765f, -0.339456677436829f, + 0.866848707199097f, -0.339738160371780f, 0.866588056087494f, -0.340019434690475f, + 0.866327106952667f, -0.340300500392914f, 0.866066038608551f, -0.340581357479095f, + 0.865804672241211f, -0.340862035751343f, 0.865543127059937f, -0.341142505407333f, + 0.865281403064728f, -0.341422766447067f, 0.865019381046295f, -0.341702848672867f, + 0.864757239818573f, -0.341982692480087f, 0.864494800567627f, -0.342262357473373f, + 0.864232182502747f, -0.342541843652725f, 0.863969385623932f, -0.342821091413498f, + 0.863706290721893f, -0.343100160360336f, 0.863443076610565f, -0.343379020690918f, + 0.863179564476013f, -0.343657672405243f, 0.862915873527527f, -0.343936115503311f, + 0.862652003765106f, -0.344214379787445f, 0.862387895584106f, -0.344492435455322f, + 0.862123548984528f, -0.344770282506943f, 0.861859023571014f, -0.345047920942307f, + 0.861594259738922f, -0.345325350761414f, 0.861329257488251f, -0.345602601766586f, + 0.861064076423645f, -0.345879614353180f, 0.860798716545105f, -0.346156448125839f, + 0.860533118247986f, -0.346433073282242f, 0.860267281532288f, -0.346709519624710f, + 0.860001266002655f, -0.346985727548599f, 0.859735012054443f, -0.347261756658554f, + 0.859468579292297f, -0.347537547349930f, 0.859201908111572f, -0.347813159227371f, + 0.858934998512268f, -0.348088562488556f, 0.858667910099030f, -0.348363757133484f, + 0.858400642871857f, -0.348638743162155f, 0.858133137226105f, -0.348913550376892f, + 0.857865393161774f, -0.349188119173050f, 0.857597470283508f, -0.349462509155273f, + 0.857329368591309f, -0.349736660718918f, 0.857060968875885f, -0.350010633468628f, + 0.856792449951172f, -0.350284397602081f, 0.856523692607880f, -0.350557953119278f, + 0.856254696846008f, -0.350831300020218f, 0.855985522270203f, -0.351104438304901f, + 0.855716109275818f, -0.351377367973328f, 0.855446517467499f, -0.351650089025497f, + 0.855176687240601f, -0.351922631263733f, 0.854906618595123f, -0.352194935083389f, + 0.854636430740356f, -0.352467030286789f, 0.854365944862366f, -0.352738946676254f, + 0.854095339775085f, -0.353010624647141f, 0.853824436664581f, -0.353282123804092f, + 0.853553414344788f, -0.353553384542465f, 0.853282094001770f, -0.353824466466904f, + 0.853010654449463f, -0.354095309972763f, 0.852738916873932f, -0.354365974664688f, + 0.852467060089111f, -0.354636400938034f, 0.852194905281067f, -0.354906648397446f, + 0.851922631263733f, -0.355176687240601f, 0.851650118827820f, -0.355446487665176f, + 0.851377367973328f, -0.355716109275818f, 0.851104438304901f, -0.355985492467880f, + 0.850831270217896f, -0.356254696846008f, 0.850557923316956f, -0.356523662805557f, + 0.850284397602081f, -0.356792420148849f, 0.850010633468628f, -0.357060998678207f, + 0.849736690521240f, -0.357329338788986f, 0.849462509155273f, -0.357597470283508f, + 0.849188148975372f, -0.357865422964096f, 0.848913550376892f, -0.358133137226105f, + 0.848638772964478f, -0.358400642871857f, 0.848363757133484f, -0.358667939901352f, + 0.848088562488556f, -0.358935028314590f, 0.847813189029694f, -0.359201908111572f, + 0.847537577152252f, -0.359468549489975f, 0.847261726856232f, -0.359735012054443f, + 0.846985757350922f, -0.360001266002655f, 0.846709489822388f, -0.360267281532288f, + 0.846433103084564f, -0.360533088445663f, 0.846156477928162f, -0.360798716545105f, + 0.845879614353180f, -0.361064106225967f, 0.845602571964264f, -0.361329287290573f, + 0.845325350761414f, -0.361594229936600f, 0.845047891139984f, -0.361858993768692f, + 0.844770252704620f, -0.362123548984528f, 0.844492435455322f, -0.362387865781784f, + 0.844214379787445f, -0.362651973962784f, 0.843936145305634f, -0.362915903329849f, + 0.843657672405243f, -0.363179564476013f, 0.843379020690918f, -0.363443046808243f, + 0.843100130558014f, -0.363706320524216f, 0.842821121215820f, -0.363969355821610f, + 0.842541813850403f, -0.364232182502747f, 0.842262387275696f, -0.364494800567627f, + 0.841982722282410f, -0.364757210016251f, 0.841702818870544f, -0.365019410848618f, + 0.841422796249390f, -0.365281373262405f, 0.841142535209656f, -0.365543156862259f, + 0.840862035751343f, -0.365804702043533f, 0.840581357479095f, -0.366066008806229f, + 0.840300500392914f, -0.366327136754990f, 0.840019404888153f, -0.366588026285172f, + 0.839738130569458f, -0.366848707199097f, 0.839456677436829f, -0.367109179496765f, + 0.839175045490265f, -0.367369443178177f, 0.838893175125122f, -0.367629468441010f, + 0.838611066341400f, -0.367889285087585f, 0.838328838348389f, -0.368148893117905f, + 0.838046371936798f, -0.368408292531967f, 0.837763667106628f, -0.368667453527451f, + 0.837480843067169f, -0.368926405906677f, 0.837197780609131f, -0.369185149669647f, + 0.836914479732513f, -0.369443655014038f, 0.836631059646606f, -0.369701951742172f, + 0.836347401142120f, -0.369960039854050f, 0.836063504219055f, -0.370217919349670f, + 0.835779488086700f, -0.370475560426712f, 0.835495233535767f, -0.370732992887497f, + 0.835210800170898f, -0.370990216732025f, 0.834926128387451f, -0.371247202157974f, + 0.834641277790070f, -0.371503978967667f, 0.834356248378754f, -0.371760547161102f, + 0.834071040153503f, -0.372016876935959f, 0.833785593509674f, -0.372272998094559f, + 0.833499968051910f, -0.372528880834579f, 0.833214163780212f, -0.372784584760666f, + 0.832928121089935f, -0.373040050268173f, 0.832641899585724f, -0.373295277357101f, + 0.832355499267578f, -0.373550295829773f, 0.832068860530853f, -0.373805105686188f, + 0.831782102584839f, -0.374059677124023f, 0.831495106220245f, -0.374314039945602f, + 0.831207871437073f, -0.374568194150925f, 0.830920517444611f, -0.374822109937668f, + 0.830632925033569f, -0.375075817108154f, 0.830345153808594f, -0.375329315662384f, + 0.830057144165039f, -0.375582575798035f, 0.829769015312195f, -0.375835597515106f, + 0.829480648040771f, -0.376088410615921f, 0.829192101955414f, -0.376341015100479f, + 0.828903317451477f, -0.376593410968781f, 0.828614413738251f, -0.376845568418503f, + 0.828325271606445f, -0.377097487449646f, 0.828035950660706f, -0.377349197864532f, + 0.827746450901031f, -0.377600699663162f, 0.827456712722778f, -0.377851963043213f, + 0.827166795730591f, -0.378102988004684f, 0.826876699924469f, -0.378353834152222f, + 0.826586425304413f, -0.378604412078857f, 0.826295912265778f, -0.378854811191559f, + 0.826005280017853f, -0.379104942083359f, 0.825714409351349f, -0.379354894161224f, + 0.825423359870911f, -0.379604607820511f, 0.825132071971893f, -0.379854083061218f, + 0.824840664863586f, -0.380103349685669f, 0.824549019336700f, -0.380352377891541f, + 0.824257194995880f, -0.380601197481155f, 0.823965191841125f, -0.380849778652191f, + 0.823673009872437f, -0.381098151206970f, 0.823380589485168f, -0.381346285343170f, + 0.823087990283966f, -0.381594210863113f, 0.822795212268829f, -0.381841897964478f, + 0.822502255439758f, -0.382089376449585f, 0.822209119796753f, -0.382336616516113f, + 0.821915745735168f, -0.382583618164063f, 0.821622252464294f, -0.382830440998077f, + 0.821328520774841f, -0.383076995611191f, 0.821034610271454f, -0.383323341608047f, + 0.820740520954132f, -0.383569449186325f, 0.820446193218231f, -0.383815348148346f, + 0.820151746273041f, -0.384061008691788f, 0.819857060909271f, -0.384306460618973f, + 0.819562196731567f, -0.384551674127579f, 0.819267153739929f, -0.384796649217606f, + 0.818971931934357f, -0.385041415691376f, 0.818676531314850f, -0.385285943746567f, + 0.818380951881409f, -0.385530263185501f, 0.818085134029388f, -0.385774344205856f, + 0.817789137363434f, -0.386018186807632f, 0.817493021488190f, -0.386261820793152f, + 0.817196667194366f, -0.386505216360092f, 0.816900074481964f, -0.386748403310776f, + 0.816603362560272f, -0.386991351842880f, 0.816306471824646f, -0.387234061956406f, + 0.816009342670441f, -0.387476563453674f, 0.815712094306946f, -0.387718826532364f, + 0.815414607524872f, -0.387960851192474f, 0.815116941928864f, -0.388202667236328f, + 0.814819097518921f, -0.388444244861603f, 0.814521074295044f, -0.388685584068298f, + 0.814222872257233f, -0.388926714658737f, 0.813924491405487f, -0.389167606830597f, + 0.813625931739807f, -0.389408260583878f, 0.813327133655548f, -0.389648675918579f, + 0.813028216362000f, -0.389888882637024f, 0.812729060649872f, -0.390128880739212f, + 0.812429726123810f, -0.390368610620499f, 0.812130272388458f, -0.390608131885529f, + 0.811830580234528f, -0.390847414731979f, 0.811530709266663f, -0.391086459159851f, + 0.811230659484863f, -0.391325294971466f, 0.810930430889130f, -0.391563892364502f, + 0.810629963874817f, -0.391802251338959f, 0.810329377651215f, -0.392040401697159f, + 0.810028612613678f, -0.392278283834457f, 0.809727668762207f, -0.392515957355499f, + 0.809426486492157f, -0.392753422260284f, 0.809125185012817f, -0.392990618944168f, + 0.808823645114899f, -0.393227607011795f, 0.808521986007690f, -0.393464356660843f, + 0.808220088481903f, -0.393700867891312f, 0.807918012142181f, -0.393937170505524f, + 0.807615816593170f, -0.394173204898834f, 0.807313382625580f, -0.394409030675888f, + 0.807010769844055f, -0.394644618034363f, 0.806707978248596f, -0.394879996776581f, + 0.806405067443848f, -0.395115107297897f, 0.806101918220520f, -0.395350009202957f, + 0.805798590183258f, -0.395584672689438f, 0.805495083332062f, -0.395819097757339f, + 0.805191397666931f, -0.396053284406662f, 0.804887533187866f, -0.396287262439728f, + 0.804583489894867f, -0.396520972251892f, 0.804279267787933f, -0.396754473447800f, + 0.803974866867065f, -0.396987736225128f, 0.803670346736908f, -0.397220760583878f, + 0.803365588188171f, -0.397453576326370f, 0.803060650825500f, -0.397686123847961f, + 0.802755534648895f, -0.397918462753296f, 0.802450239658356f, -0.398150533437729f, + 0.802144765853882f, -0.398382395505905f, 0.801839113235474f, -0.398614019155502f, + 0.801533281803131f, -0.398845434188843f, 0.801227271556854f, -0.399076581001282f, + 0.800921142101288f, -0.399307489395142f, 0.800614774227142f, -0.399538189172745f, + 0.800308227539063f, -0.399768620729446f, 0.800001561641693f, -0.399998843669891f, + 0.799694657325745f, -0.400228828191757f, 0.799387574195862f, -0.400458574295044f, + 0.799080371856689f, -0.400688081979752f, 0.798772931098938f, -0.400917351245880f, + 0.798465371131897f, -0.401146411895752f, 0.798157572746277f, -0.401375204324722f, + 0.797849655151367f, -0.401603758335114f, 0.797541558742523f, -0.401832103729248f, + 0.797233223915100f, -0.402060180902481f, 0.796924769878387f, -0.402288049459457f, + 0.796616137027740f, -0.402515679597855f, 0.796307325363159f, -0.402743041515350f, + 0.795998334884644f, -0.402970194816589f, 0.795689165592194f, -0.403197109699249f, + 0.795379877090454f, -0.403423786163330f, 0.795070350170136f, -0.403650224208832f, + 0.794760644435883f, -0.403876423835754f, 0.794450819492340f, -0.404102355241776f, + 0.794140756130219f, -0.404328078031540f, 0.793830573558807f, -0.404553562402725f, + 0.793520212173462f, -0.404778808355331f, 0.793209671974182f, -0.405003815889359f, + 0.792898952960968f, -0.405228585004807f, 0.792588055133820f, -0.405453115701675f, + 0.792276978492737f, -0.405677437782288f, 0.791965723037720f, -0.405901491641998f, + 0.791654348373413f, -0.406125307083130f, 0.791342735290527f, -0.406348884105682f, + 0.791031002998352f, -0.406572192907333f, 0.790719091892242f, -0.406795293092728f, + 0.790407001972198f, -0.407018154859543f, 0.790094733238220f, -0.407240778207779f, + 0.789782285690308f, -0.407463163137436f, 0.789469659328461f, -0.407685309648514f, + 0.789156913757324f, -0.407907217741013f, 0.788843929767609f, -0.408128857612610f, + 0.788530826568604f, -0.408350288867950f, 0.788217544555664f, -0.408571451902390f, + 0.787904083728790f, -0.408792406320572f, 0.787590444087982f, -0.409013092517853f, + 0.787276685237885f, -0.409233570098877f, 0.786962687969208f, -0.409453779459000f, + 0.786648571491241f, -0.409673750400543f, 0.786334276199341f, -0.409893482923508f, + 0.786019802093506f, -0.410112977027893f, 0.785705149173737f, -0.410332232713699f, + 0.785390377044678f, -0.410551249980927f, 0.785075426101685f, -0.410770028829575f, + 0.784760236740112f, -0.410988569259644f, 0.784444928169250f, -0.411206841468811f, + 0.784129500389099f, -0.411424905061722f, 0.783813834190369f, -0.411642700433731f, + 0.783498048782349f, -0.411860257387161f, 0.783182024955750f, -0.412077575922012f, + 0.782865881919861f, -0.412294656038284f, 0.782549619674683f, -0.412511497735977f, + 0.782233119010925f, -0.412728071212769f, 0.781916499137878f, -0.412944436073303f, + 0.781599700450897f, -0.413160532712936f, 0.781282722949982f, -0.413376390933990f, + 0.780965566635132f, -0.413592010736465f, 0.780648231506348f, -0.413807392120361f, + 0.780330777168274f, -0.414022535085678f, 0.780013144016266f, -0.414237409830093f, + 0.779695332050323f, -0.414452046155930f, 0.779377400875092f, -0.414666473865509f, + 0.779059290885925f, -0.414880603551865f, 0.778741002082825f, -0.415094524621964f, + 0.778422534465790f, -0.415308207273483f, 0.778103888034821f, -0.415521621704102f, + 0.777785122394562f, -0.415734797716141f, 0.777466177940369f, -0.415947735309601f, + 0.777147054672241f, -0.416160434484482f, 0.776827812194824f, -0.416372895240784f, + 0.776508331298828f, -0.416585087776184f, 0.776188731193542f, -0.416797041893005f, + 0.775869011878967f, -0.417008757591248f, 0.775549054145813f, -0.417220205068588f, + 0.775228977203369f, -0.417431443929672f, 0.774908721446991f, -0.417642414569855f, + 0.774588346481323f, -0.417853146791458f, 0.774267733097076f, -0.418063640594482f, + 0.773947000503540f, -0.418273866176605f, 0.773626148700714f, -0.418483853340149f, + 0.773305058479309f, -0.418693602085114f, 0.772983849048615f, -0.418903112411499f, + 0.772662520408630f, -0.419112354516983f, 0.772340953350067f, -0.419321358203888f, + 0.772019267082214f, -0.419530123472214f, 0.771697402000427f, -0.419738620519638f, + 0.771375417709351f, -0.419946908950806f, 0.771053194999695f, -0.420154929161072f, + 0.770730912685394f, -0.420362681150436f, 0.770408391952515f, -0.420570224523544f, + 0.770085752010345f, -0.420777499675751f, 0.769762933254242f, -0.420984506607056f, + 0.769439935684204f, -0.421191304922104f, 0.769116818904877f, -0.421397835016251f, + 0.768793523311615f, -0.421604126691818f, 0.768470108509064f, -0.421810150146484f, + 0.768146514892578f, -0.422015935182571f, 0.767822742462158f, -0.422221481800079f, + 0.767498791217804f, -0.422426789999008f, 0.767174720764160f, -0.422631829977036f, + 0.766850471496582f, -0.422836631536484f, 0.766526103019714f, -0.423041164875031f, + 0.766201555728912f, -0.423245459794998f, 0.765876889228821f, -0.423449516296387f, + 0.765551984310150f, -0.423653304576874f, 0.765226960182190f, -0.423856884241104f, + 0.764901816844940f, -0.424060165882111f, 0.764576494693756f, -0.424263238906860f, + 0.764250993728638f, -0.424466013908386f, 0.763925373554230f, -0.424668580293655f, + 0.763599574565887f, -0.424870878458023f, 0.763273596763611f, -0.425072938203812f, + 0.762947499752045f, -0.425274729728699f, 0.762621283531189f, -0.425476282835007f, + 0.762294828891754f, -0.425677597522736f, 0.761968255043030f, -0.425878643989563f, + 0.761641561985016f, -0.426079452037811f, 0.761314690113068f, -0.426279991865158f, + 0.760987639427185f, -0.426480293273926f, 0.760660469532013f, -0.426680356264114f, + 0.760333120822906f, -0.426880151033401f, 0.760005652904511f, -0.427079707384110f, + 0.759678006172180f, -0.427278995513916f, 0.759350180625916f, -0.427478045225143f, + 0.759022235870361f, -0.427676826715469f, 0.758694171905518f, -0.427875369787216f, + 0.758365929126740f, -0.428073674440384f, 0.758037507534027f, -0.428271710872650f, + 0.757708966732025f, -0.428469479084015f, 0.757380247116089f, -0.428667008876801f, + 0.757051348686218f, -0.428864300251007f, 0.756722390651703f, -0.429061323404312f, + 0.756393194198608f, -0.429258108139038f, 0.756063878536224f, -0.429454624652863f, + 0.755734443664551f, -0.429650902748108f, 0.755404829978943f, -0.429846942424774f, + 0.755075037479401f, -0.430042684078217f, 0.754745125770569f, -0.430238217115402f, + 0.754415094852448f, -0.430433481931686f, 0.754084885120392f, -0.430628478527069f, + 0.753754496574402f, -0.430823236703873f, 0.753423988819122f, -0.431017726659775f, + 0.753093302249908f, -0.431211978197098f, 0.752762496471405f, -0.431405961513519f, + 0.752431571483612f, -0.431599706411362f, 0.752100467681885f, -0.431793183088303f, + 0.751769185066223f, -0.431986421346664f, 0.751437783241272f, -0.432179391384125f, + 0.751106262207031f, -0.432372123003006f, 0.750774562358856f, -0.432564586400986f, + 0.750442683696747f, -0.432756811380386f, 0.750110685825348f, -0.432948768138886f, + 0.749778568744659f, -0.433140486478806f, 0.749446272850037f, -0.433331936597824f, + 0.749113857746124f, -0.433523118495941f, 0.748781263828278f, -0.433714061975479f, + 0.748448550701141f, -0.433904737234116f, 0.748115658760071f, -0.434095174074173f, + 0.747782647609711f, -0.434285342693329f, 0.747449457645416f, -0.434475272893906f, + 0.747116148471832f, -0.434664934873581f, 0.746782720088959f, -0.434854328632355f, + 0.746449112892151f, -0.435043483972549f, 0.746115326881409f, -0.435232400894165f, + 0.745781481266022f, -0.435421019792557f, 0.745447397232056f, -0.435609430074692f, + 0.745113253593445f, -0.435797542333603f, 0.744778931140900f, -0.435985416173935f, + 0.744444429874420f, -0.436173021793365f, 0.744109809398651f, -0.436360388994217f, + 0.743775069713593f, -0.436547487974167f, 0.743440151214600f, -0.436734348535538f, + 0.743105113506317f, -0.436920911073685f, 0.742769956588745f, -0.437107264995575f, + 0.742434620857239f, -0.437293320894241f, 0.742099165916443f, -0.437479138374329f, + 0.741763532161713f, -0.437664687633514f, 0.741427779197693f, -0.437849998474121f, + 0.741091907024384f, -0.438035041093826f, 0.740755856037140f, -0.438219845294952f, + 0.740419685840607f, -0.438404351472855f, 0.740083336830139f, -0.438588619232178f, + 0.739746868610382f, -0.438772648572922f, 0.739410281181335f, -0.438956409692764f, + 0.739073514938354f, -0.439139902591705f, 0.738736629486084f, -0.439323127269745f, + 0.738399624824524f, -0.439506113529205f, 0.738062441349030f, -0.439688831567764f, + 0.737725138664246f, -0.439871311187744f, 0.737387716770172f, -0.440053492784500f, + 0.737050116062164f, -0.440235435962677f, 0.736712396144867f, -0.440417140722275f, + 0.736374497413635f, -0.440598547458649f, 0.736036539077759f, -0.440779715776443f, + 0.735698342323303f, -0.440960645675659f, 0.735360085964203f, -0.441141277551651f, + 0.735021650791168f, -0.441321671009064f, 0.734683096408844f, -0.441501796245575f, + 0.734344422817230f, -0.441681683063507f, 0.734005570411682f, -0.441861271858215f, + 0.733666598796844f, -0.442040622234344f, 0.733327507972717f, -0.442219734191895f, + 0.732988238334656f, -0.442398548126221f, 0.732648849487305f, -0.442577123641968f, + 0.732309341430664f, -0.442755430936813f, 0.731969714164734f, -0.442933470010757f, + 0.731629908084869f, -0.443111270666122f, 0.731289982795715f, -0.443288803100586f, + 0.730949878692627f, -0.443466067314148f, 0.730609714984894f, -0.443643063306808f, + 0.730269372463226f, -0.443819820880890f, 0.729928910732269f, -0.443996280431747f, + 0.729588270187378f, -0.444172531366348f, 0.729247510433197f, -0.444348484277725f, + 0.728906631469727f, -0.444524168968201f, 0.728565633296967f, -0.444699615240097f, + 0.728224515914917f, -0.444874793291092f, 0.727883219718933f, -0.445049703121185f, + 0.727541804313660f, -0.445224374532700f, 0.727200269699097f, -0.445398747920990f, + 0.726858556270599f, -0.445572882890701f, 0.726516723632813f, -0.445746749639511f, + 0.726174771785736f, -0.445920348167419f, 0.725832700729370f, -0.446093708276749f, + 0.725490510463715f, -0.446266770362854f, 0.725148141384125f, -0.446439594030380f, + 0.724805653095245f, -0.446612149477005f, 0.724463045597076f, -0.446784436702728f, + 0.724120318889618f, -0.446956485509872f, 0.723777413368225f, -0.447128236293793f, + 0.723434448242188f, -0.447299748659134f, 0.723091304302216f, -0.447470992803574f, + 0.722747981548309f, -0.447641968727112f, 0.722404599189758f, -0.447812676429749f, + 0.722061097621918f, -0.447983115911484f, 0.721717417240143f, -0.448153316974640f, + 0.721373617649078f, -0.448323249816895f, 0.721029698848724f, -0.448492884635925f, + 0.720685660839081f, -0.448662281036377f, 0.720341444015503f, -0.448831409215927f, + 0.719997107982636f, -0.449000298976898f, 0.719652712345123f, -0.449168890714645f, + 0.719308137893677f, -0.449337244033813f, 0.718963444232941f, -0.449505299329758f, + 0.718618571758270f, -0.449673116207123f, 0.718273639678955f, -0.449840664863586f, + 0.717928528785706f, -0.450007945299149f, 0.717583298683167f, -0.450174957513809f, + 0.717238008975983f, -0.450341701507568f, 0.716892480850220f, -0.450508207082748f, + 0.716546893119812f, -0.450674414634705f, 0.716201186180115f, -0.450840383768082f, + 0.715855300426483f, -0.451006084680557f, 0.715509355068207f, -0.451171487569809f, + 0.715163230895996f, -0.451336652040482f, 0.714816987514496f, -0.451501548290253f, + 0.714470624923706f, -0.451666176319122f, 0.714124143123627f, -0.451830536127090f, + 0.713777542114258f, -0.451994657516479f, 0.713430821895599f, -0.452158480882645f, + 0.713083922863007f, -0.452322036027908f, 0.712736964225769f, -0.452485352754593f, + 0.712389826774597f, -0.452648371458054f, 0.712042629718781f, -0.452811151742935f, + 0.711695253849030f, -0.452973634004593f, 0.711347758769989f, -0.453135877847672f, + 0.711000144481659f, -0.453297853469849f, 0.710652410984039f, -0.453459560871124f, + 0.710304558277130f, -0.453621000051498f, 0.709956526756287f, -0.453782171010971f, + 0.709608435630798f, -0.453943043947220f, 0.709260225296021f, -0.454103678464890f, + 0.708911836147308f, -0.454264044761658f, 0.708563387393951f, -0.454424172639847f, + 0.708214759826660f, -0.454584002494812f, 0.707866072654724f, -0.454743564128876f, + 0.707517206668854f, -0.454902857542038f, 0.707168221473694f, -0.455061882734299f, + 0.706819176673889f, -0.455220639705658f, 0.706469953060150f, -0.455379128456116f, + 0.706120610237122f, -0.455537378787994f, 0.705771148204803f, -0.455695331096649f, + 0.705421566963196f, -0.455853015184402f, 0.705071866512299f, -0.456010431051254f, + 0.704722046852112f, -0.456167578697205f, 0.704372167587280f, -0.456324487924576f, + 0.704022109508514f, -0.456481099128723f, 0.703671932220459f, -0.456637442111969f, + 0.703321635723114f, -0.456793516874313f, 0.702971220016479f, -0.456949323415756f, + 0.702620685100555f, -0.457104891538620f, 0.702270030975342f, -0.457260161638260f, + 0.701919257640839f, -0.457415163516998f, 0.701568365097046f, -0.457569897174835f, + 0.701217353343964f, -0.457724362611771f, 0.700866222381592f, -0.457878559827805f, + 0.700514972209930f, -0.458032488822937f, 0.700163602828979f, -0.458186149597168f, + 0.699812114238739f, -0.458339542150497f, 0.699460506439209f, -0.458492636680603f, + 0.699108779430389f, -0.458645492792130f, 0.698756933212280f, -0.458798080682755f, + 0.698404967784882f, -0.458950400352478f, 0.698052942752838f, -0.459102421998978f, + 0.697700738906860f, -0.459254205226898f, 0.697348415851593f, -0.459405690431595f, + 0.696996033191681f, -0.459556937217712f, 0.696643471717834f, -0.459707885980606f, + 0.696290850639343f, -0.459858566522598f, 0.695938050746918f, -0.460008978843689f, + 0.695585191249847f, -0.460159152746201f, 0.695232212543488f, -0.460309028625488f, + 0.694879114627838f, -0.460458606481552f, 0.694525837898254f, -0.460607945919037f, + 0.694172501564026f, -0.460757017135620f, 0.693819046020508f, -0.460905820131302f, + 0.693465530872345f, -0.461054325103760f, 0.693111836910248f, -0.461202591657639f, + 0.692758023738861f, -0.461350560188293f, 0.692404091358185f, -0.461498260498047f, + 0.692050099372864f, -0.461645722389221f, 0.691695988178253f, -0.461792886257172f, + 0.691341698169708f, -0.461939752101898f, 0.690987348556519f, -0.462086379528046f, + 0.690632879734039f, -0.462232738733292f, 0.690278291702271f, -0.462378799915314f, + 0.689923584461212f, -0.462524622678757f, 0.689568817615509f, -0.462670147418976f, + 0.689213871955872f, -0.462815403938293f, 0.688858866691589f, -0.462960392236710f, + 0.688503682613373f, -0.463105112314224f, 0.688148438930511f, -0.463249564170837f, + 0.687793076038361f, -0.463393747806549f, 0.687437593936920f, -0.463537633419037f, + 0.687082052230835f, -0.463681250810623f, 0.686726331710815f, -0.463824629783630f, + 0.686370551586151f, -0.463967710733414f, 0.686014592647552f, -0.464110493659973f, + 0.685658574104309f, -0.464253038167953f, 0.685302436351776f, -0.464395314455032f, + 0.684946238994598f, -0.464537292718887f, 0.684589862823486f, -0.464679002761841f, + 0.684233427047729f, -0.464820444583893f, 0.683876872062683f, -0.464961618185043f, + 0.683520197868347f, -0.465102523565292f, 0.683163404464722f, -0.465243130922318f, + 0.682806491851807f, -0.465383470058441f, 0.682449519634247f, -0.465523540973663f, + 0.682092368602753f, -0.465663343667984f, 0.681735157966614f, -0.465802878141403f, + 0.681377887725830f, -0.465942144393921f, 0.681020438671112f, -0.466081112623215f, + 0.680662930011749f, -0.466219812631607f, 0.680305242538452f, -0.466358244419098f, + 0.679947495460510f, -0.466496407985687f, 0.679589688777924f, -0.466634273529053f, + 0.679231703281403f, -0.466771900653839f, 0.678873658180237f, -0.466909229755402f, + 0.678515493869781f, -0.467046260833740f, 0.678157210350037f, -0.467183053493500f, + 0.677798807621002f, -0.467319577932358f, 0.677440345287323f, -0.467455804347992f, + 0.677081763744354f, -0.467591762542725f, 0.676723062992096f, -0.467727422714233f, + 0.676364302635193f, -0.467862844467163f, 0.676005363464355f, -0.467997968196869f, + 0.675646364688873f, -0.468132823705673f, 0.675287246704102f, -0.468267410993576f, + 0.674928069114685f, -0.468401730060577f, 0.674568772315979f, -0.468535751104355f, + 0.674209356307983f, -0.468669503927231f, 0.673849821090698f, -0.468802988529205f, + 0.673490226268768f, -0.468936175107956f, 0.673130512237549f, -0.469069123268127f, + 0.672770678997040f, -0.469201773405075f, 0.672410726547241f, -0.469334155321121f, + 0.672050714492798f, -0.469466239213943f, 0.671690583229065f, -0.469598054885864f, + 0.671330332756042f, -0.469729602336884f, 0.670970022678375f, -0.469860881567001f, + 0.670609593391418f, -0.469991862773895f, 0.670249044895172f, -0.470122605562210f, + 0.669888436794281f, -0.470253020524979f, 0.669527709484100f, -0.470383197069168f, + 0.669166862964630f, -0.470513075590134f, 0.668805956840515f, -0.470642685890198f, + 0.668444931507111f, -0.470772027969360f, 0.668083786964417f, -0.470901101827621f, + 0.667722582817078f, -0.471029877662659f, 0.667361259460449f, -0.471158385276794f, + 0.666999816894531f, -0.471286594867706f, 0.666638314723969f, -0.471414536237717f, + 0.666276693344116f, -0.471542209386826f, 0.665914952754974f, -0.471669614315033f, + 0.665553152561188f, -0.471796721220016f, 0.665191233158112f, -0.471923559904099f, + 0.664829254150391f, -0.472050130367279f, 0.664467096328735f, -0.472176402807236f, + 0.664104938507080f, -0.472302407026291f, 0.663742601871490f, -0.472428143024445f, + 0.663380205631256f, -0.472553610801697f, 0.663017749786377f, -0.472678780555725f, + 0.662655174732208f, -0.472803652286530f, 0.662292480468750f, -0.472928285598755f, + 0.661929666996002f, -0.473052620887756f, 0.661566793918610f, -0.473176687955856f, + 0.661203861236572f, -0.473300457000732f, 0.660840749740601f, -0.473423957824707f, + 0.660477638244629f, -0.473547190427780f, 0.660114347934723f, -0.473670125007629f, + 0.659750998020172f, -0.473792791366577f, 0.659387588500977f, -0.473915189504623f, + 0.659024059772491f, -0.474037289619446f, 0.658660411834717f, -0.474159121513367f, + 0.658296704292297f, -0.474280685186386f, 0.657932877540588f, -0.474401950836182f, + 0.657568991184235f, -0.474522948265076f, 0.657204985618591f, -0.474643647670746f, + 0.656840860843658f, -0.474764078855515f, 0.656476676464081f, -0.474884241819382f, + 0.656112432479858f, -0.475004136562347f, 0.655748009681702f, -0.475123733282089f, + 0.655383586883545f, -0.475243031978607f, 0.655019044876099f, -0.475362062454224f, + 0.654654383659363f, -0.475480824708939f, 0.654289662837982f, -0.475599318742752f, + 0.653924822807312f, -0.475717514753342f, 0.653559923171997f, -0.475835442543030f, + 0.653194904327393f, -0.475953072309494f, 0.652829825878143f, -0.476070433855057f, + 0.652464628219604f, -0.476187497377396f, 0.652099311351776f, -0.476304292678833f, + 0.651733994483948f, -0.476420819759369f, 0.651368498802185f, -0.476537048816681f, + 0.651003003120422f, -0.476653009653091f, 0.650637328624725f, -0.476768702268600f, + 0.650271594524384f, -0.476884096860886f, 0.649905800819397f, -0.476999223232269f, + 0.649539887905121f, -0.477114051580429f, 0.649173915386200f, -0.477228611707687f, + 0.648807883262634f, -0.477342873811722f, 0.648441672325134f, -0.477456867694855f, + 0.648075461387634f, -0.477570593357086f, 0.647709131240845f, -0.477684020996094f, + 0.647342681884766f, -0.477797180414200f, 0.646976172924042f, -0.477910041809082f, + 0.646609604358673f, -0.478022634983063f, 0.646242916584015f, -0.478134930133820f, + 0.645876109600067f, -0.478246957063675f, 0.645509302616119f, -0.478358715772629f, + 0.645142316818237f, -0.478470176458359f, 0.644775331020355f, -0.478581339120865f, + 0.644408226013184f, -0.478692263364792f, 0.644041001796722f, -0.478802859783173f, + 0.643673717975616f, -0.478913217782974f, 0.643306374549866f, -0.479023247957230f, + 0.642938911914825f, -0.479133039712906f, 0.642571389675140f, -0.479242533445358f, + 0.642203748226166f, -0.479351729154587f, 0.641836047172546f, -0.479460656642914f, + 0.641468286514282f, -0.479569315910339f, 0.641100406646729f, -0.479677677154541f, + 0.640732467174530f, -0.479785770177841f, 0.640364408493042f, -0.479893565177917f, + 0.639996349811554f, -0.480001062154770f, 0.639628112316132f, -0.480108320713043f, + 0.639259815216064f, -0.480215251445770f, 0.638891458511353f, -0.480321943759918f, + 0.638523042201996f, -0.480428308248520f, 0.638154506683350f, -0.480534434318542f, + 0.637785911560059f, -0.480640232563019f, 0.637417197227478f, -0.480745792388916f, + 0.637048482894897f, -0.480851024389267f, 0.636679589748383f, -0.480956017971039f, + 0.636310696601868f, -0.481060713529587f, 0.635941684246063f, -0.481165111064911f, + 0.635572552680969f, -0.481269240379334f, 0.635203421115875f, -0.481373071670532f, + 0.634834170341492f, -0.481476634740829f, 0.634464859962463f, -0.481579899787903f, + 0.634095430374146f, -0.481682896614075f, 0.633725941181183f, -0.481785595417023f, + 0.633356392383575f, -0.481888025999069f, 0.632986724376678f, -0.481990188360214f, + 0.632616996765137f, -0.482092022895813f, 0.632247209548950f, -0.482193619012833f, + 0.631877362728119f, -0.482294887304306f, 0.631507396697998f, -0.482395917177200f, + 0.631137371063232f, -0.482496619224548f, 0.630767226219177f, -0.482597053050995f, + 0.630397081375122f, -0.482697218656540f, 0.630026817321777f, -0.482797086238861f, + 0.629656434059143f, -0.482896685600281f, 0.629286050796509f, -0.482995986938477f, + 0.628915548324585f, -0.483094990253448f, 0.628544986248016f, -0.483193725347519f, + 0.628174364566803f, -0.483292192220688f, 0.627803623676300f, -0.483390361070633f, + 0.627432823181152f, -0.483488231897354f, 0.627061963081360f, -0.483585834503174f, + 0.626691043376923f, -0.483683139085770f, 0.626320004463196f, -0.483780175447464f, + 0.625948905944824f, -0.483876913785934f, 0.625577747821808f, -0.483973383903503f, + 0.625206530094147f, -0.484069555997849f, 0.624835193157196f, -0.484165430068970f, + 0.624463796615601f, -0.484261035919189f, 0.624092340469360f, -0.484356373548508f, + 0.623720824718475f, -0.484451413154602f, 0.623349189758301f, -0.484546154737473f, + 0.622977554798126f, -0.484640628099442f, 0.622605800628662f, -0.484734803438187f, + 0.622233927249908f, -0.484828680753708f, 0.621862053871155f, -0.484922289848328f, + 0.621490061283112f, -0.485015630722046f, 0.621118068695068f, -0.485108673572540f, + 0.620745956897736f, -0.485201418399811f, 0.620373785495758f, -0.485293895006180f, + 0.620001494884491f, -0.485386073589325f, 0.619629204273224f, -0.485477954149246f, + 0.619256794452667f, -0.485569566488266f, 0.618884325027466f, -0.485660910606384f, + 0.618511795997620f, -0.485751956701279f, 0.618139207363129f, -0.485842704772949f, + 0.617766559123993f, -0.485933154821396f, 0.617393791675568f, -0.486023366451263f, + 0.617020964622498f, -0.486113250255585f, 0.616648077964783f, -0.486202865839005f, + 0.616275131702423f, -0.486292183399200f, 0.615902125835419f, -0.486381232738495f, + 0.615529060363770f, -0.486469984054565f, 0.615155875682831f, -0.486558437347412f, + 0.614782691001892f, -0.486646622419357f, 0.614409387111664f, -0.486734509468079f, + 0.614036023616791f, -0.486822128295898f, 0.613662600517273f, -0.486909449100494f, + 0.613289117813110f, -0.486996471881866f, 0.612915575504303f, -0.487083226442337f, + 0.612541973590851f, -0.487169682979584f, 0.612168252468109f, -0.487255871295929f, + 0.611794531345367f, -0.487341761589050f, 0.611420691013336f, -0.487427353858948f, + 0.611046791076660f, -0.487512677907944f, 0.610672831535339f, -0.487597703933716f, + 0.610298871994019f, -0.487682431936264f, 0.609924793243408f, -0.487766891717911f, + 0.609550595283508f, -0.487851053476334f, 0.609176397323608f, -0.487934947013855f, + 0.608802139759064f, -0.488018542528152f, 0.608427822589874f, -0.488101840019226f, + 0.608053386211395f, -0.488184869289398f, 0.607678949832916f, -0.488267600536346f, + 0.607304394245148f, -0.488350033760071f, 0.606929838657379f, -0.488432198762894f, + 0.606555163860321f, -0.488514065742493f, 0.606180429458618f, -0.488595664501190f, + 0.605805635452271f, -0.488676935434341f, 0.605430841445923f, -0.488757967948914f, + 0.605055928230286f, -0.488838672637939f, 0.604680955410004f, -0.488919109106064f, + 0.604305922985077f, -0.488999247550964f, 0.603930830955505f, -0.489079117774963f, + 0.603555679321289f, -0.489158689975739f, 0.603180468082428f, -0.489237964153290f, + 0.602805197238922f, -0.489316970109940f, 0.602429866790771f, -0.489395678043365f, + 0.602054476737976f, -0.489474087953568f, 0.601679027080536f, -0.489552229642868f, + 0.601303517818451f, -0.489630073308945f, 0.600927948951721f, -0.489707618951797f, + 0.600552320480347f, -0.489784896373749f, 0.600176632404327f, -0.489861875772476f, + 0.599800884723663f, -0.489938557147980f, 0.599425077438354f, -0.490014940500259f, + 0.599049210548401f, -0.490091055631638f, 0.598673284053802f, -0.490166902542114f, + 0.598297297954559f, -0.490242421627045f, 0.597921252250671f, -0.490317672491074f, + 0.597545146942139f, -0.490392625331879f, 0.597168982028961f, -0.490467309951782f, + 0.596792817115784f, -0.490541696548462f, 0.596416532993317f, -0.490615785121918f, + 0.596040189266205f, -0.490689605474472f, 0.595663845539093f, -0.490763127803802f, + 0.595287382602692f, -0.490836352109909f, 0.594910860061646f, -0.490909278392792f, + 0.594534337520599f, -0.490981936454773f, 0.594157755374908f, -0.491054296493530f, + 0.593781054019928f, -0.491126358509064f, 0.593404352664948f, -0.491198152303696f, + 0.593027591705322f, -0.491269648075104f, 0.592650771141052f, -0.491340845823288f, + 0.592273890972137f, -0.491411775350571f, 0.591896951198578f, -0.491482406854630f, + 0.591519951820374f, -0.491552740335464f, 0.591142892837524f, -0.491622805595398f, + 0.590765833854675f, -0.491692543029785f, 0.590388655662537f, -0.491762012243271f, + 0.590011477470398f, -0.491831213235855f, 0.589634180068970f, -0.491900116205215f, + 0.589256882667542f, -0.491968721151352f, 0.588879525661469f, -0.492037028074265f, + 0.588502109050751f, -0.492105036973953f, 0.588124632835388f, -0.492172777652740f, + 0.587747097015381f, -0.492240220308304f, 0.587369561195374f, -0.492307394742966f, + 0.586991965770721f, -0.492374241352081f, 0.586614251136780f, -0.492440819740295f, + 0.586236536502838f, -0.492507129907608f, 0.585858762264252f, -0.492573112249374f, + 0.585480928421021f, -0.492638826370239f, 0.585103094577789f, -0.492704242467880f, + 0.584725141525269f, -0.492769360542297f, 0.584347188472748f, -0.492834210395813f, + 0.583969175815582f, -0.492898762226105f, 0.583591103553772f, -0.492963016033173f, + 0.583212971687317f, -0.493026971817017f, 0.582834780216217f, -0.493090659379959f, + 0.582456588745117f, -0.493154048919678f, 0.582078278064728f, -0.493217140436172f, + 0.581699967384338f, -0.493279963731766f, 0.581321597099304f, -0.493342459201813f, + 0.580943167209625f, -0.493404686450958f, 0.580564737319946f, -0.493466645479202f, + 0.580186247825623f, -0.493528276681900f, 0.579807698726654f, -0.493589639663696f, + 0.579429090023041f, -0.493650704622269f, 0.579050421714783f, -0.493711471557617f, + 0.578671753406525f, -0.493771970272064f, 0.578292965888977f, -0.493832170963287f, + 0.577914178371429f, -0.493892073631287f, 0.577535390853882f, -0.493951678276062f, + 0.577156484127045f, -0.494011014699936f, 0.576777577400208f, -0.494070053100586f, + 0.576398611068726f, -0.494128793478012f, 0.576019585132599f, -0.494187235832214f, + 0.575640499591827f, -0.494245409965515f, 0.575261414051056f, -0.494303256273270f, + 0.574882268905640f, -0.494360834360123f, 0.574503064155579f, -0.494418144226074f, + 0.574123859405518f, -0.494475126266479f, 0.573744535446167f, -0.494531840085983f, + 0.573365211486816f, -0.494588255882263f, 0.572985887527466f, -0.494644373655319f, + 0.572606444358826f, -0.494700223207474f, 0.572227001190186f, -0.494755744934082f, + 0.571847498416901f, -0.494810998439789f, 0.571467995643616f, -0.494865983724594f, + 0.571088373661041f, -0.494920641183853f, 0.570708811283112f, -0.494975030422211f, + 0.570329129695892f, -0.495029091835022f, 0.569949388504028f, -0.495082914829254f, + 0.569569647312164f, -0.495136409997940f, 0.569189906120300f, -0.495189607143402f, + 0.568810045719147f, -0.495242536067963f, 0.568430185317993f, -0.495295166969299f, + 0.568050265312195f, -0.495347499847412f, 0.567670345306396f, -0.495399564504623f, + 0.567290365695953f, -0.495451331138611f, 0.566910326480865f, -0.495502769947052f, + 0.566530287265778f, -0.495553970336914f, 0.566150128841400f, -0.495604842901230f, + 0.565770030021667f, -0.495655417442322f, 0.565389811992645f, -0.495705723762512f, + 0.565009593963623f, -0.495755732059479f, 0.564629375934601f, -0.495805442333221f, + 0.564249038696289f, -0.495854884386063f, 0.563868701457977f, -0.495903998613358f, + 0.563488364219666f, -0.495952844619751f, 0.563107967376709f, -0.496001392602921f, + 0.562727510929108f, -0.496049642562866f, 0.562346994876862f, -0.496097624301910f, + 0.561966478824615f, -0.496145308017731f, 0.561585903167725f, -0.496192663908005f, + 0.561205327510834f, -0.496239781379700f, 0.560824692249298f, -0.496286571025848f, + 0.560444056987762f, -0.496333062648773f, 0.560063362121582f, -0.496379286050797f, + 0.559682607650757f, -0.496425211429596f, 0.559301853179932f, -0.496470838785172f, + 0.558921039104462f, -0.496516168117523f, 0.558540165424347f, -0.496561229228973f, + 0.558159291744232f, -0.496605962514877f, 0.557778418064117f, -0.496650427579880f, + 0.557397484779358f, -0.496694594621658f, 0.557016491889954f, -0.496738493442535f, + 0.556635499000549f, -0.496782064437866f, 0.556254446506500f, -0.496825367212296f, + 0.555873334407806f, -0.496868371963501f, 0.555492222309113f, -0.496911078691483f, + 0.555111110210419f, -0.496953487396240f, 0.554729938507080f, -0.496995598077774f, + 0.554348707199097f, -0.497037440538406f, 0.553967475891113f, -0.497078984975815f, + 0.553586184978485f, -0.497120231389999f, 0.553204894065857f, -0.497161179780960f, + 0.552823603153229f, -0.497201830148697f, 0.552442193031311f, -0.497242212295532f, + 0.552060842514038f, -0.497282296419144f, 0.551679372787476f, -0.497322082519531f, + 0.551297962665558f, -0.497361570596695f, 0.550916433334351f, -0.497400760650635f, + 0.550534904003143f, -0.497439652681351f, 0.550153374671936f, -0.497478276491165f, + 0.549771785736084f, -0.497516602277756f, 0.549390196800232f, -0.497554630041122f, + 0.549008548259735f, -0.497592359781265f, 0.548626899719238f, -0.497629791498184f, + 0.548245191574097f, -0.497666954994202f, 0.547863483428955f, -0.497703820466995f, + 0.547481775283813f, -0.497740387916565f, 0.547099947929382f, -0.497776657342911f, + 0.546718180179596f, -0.497812628746033f, 0.546336352825165f, -0.497848302125931f, + 0.545954465866089f, -0.497883707284927f, 0.545572578907013f, -0.497918814420700f, + 0.545190691947937f, -0.497953623533249f, 0.544808745384216f, -0.497988134622574f, + 0.544426798820496f, -0.498022347688675f, 0.544044792652130f, -0.498056292533875f, + 0.543662786483765f, -0.498089909553528f, 0.543280720710754f, -0.498123258352280f, + 0.542898654937744f, -0.498156309127808f, 0.542516589164734f, -0.498189061880112f, + 0.542134463787079f, -0.498221516609192f, 0.541752278804779f, -0.498253703117371f, + 0.541370153427124f, -0.498285561800003f, 0.540987968444824f, -0.498317152261734f, + 0.540605723857880f, -0.498348444700241f, 0.540223479270935f, -0.498379439115524f, + 0.539841234683990f, -0.498410135507584f, 0.539458930492401f, -0.498440563678741f, + 0.539076626300812f, -0.498470664024353f, 0.538694262504578f, -0.498500496149063f, + 0.538311958312988f, -0.498530030250549f, 0.537929534912109f, -0.498559266328812f, + 0.537547171115875f, -0.498588204383850f, 0.537164747714996f, -0.498616874217987f, + 0.536782264709473f, -0.498645216226578f, 0.536399841308594f, -0.498673290014267f, + 0.536017298698425f, -0.498701065778732f, 0.535634815692902f, -0.498728543519974f, + 0.535252273082733f, -0.498755723237991f, 0.534869730472565f, -0.498782604932785f, + 0.534487187862396f, -0.498809218406677f, 0.534104585647583f, -0.498835533857346f, + 0.533721983432770f, -0.498861521482468f, 0.533339321613312f, -0.498887240886688f, + 0.532956659793854f, -0.498912662267685f, 0.532573997974396f, -0.498937815427780f, + 0.532191336154938f, -0.498962640762329f, 0.531808614730835f, -0.498987197875977f, + 0.531425893306732f, -0.499011427164078f, 0.531043112277985f, -0.499035388231277f, + 0.530660390853882f, -0.499059051275253f, 0.530277609825134f, -0.499082416296005f, + 0.529894769191742f, -0.499105513095856f, 0.529511988162994f, -0.499128282070160f, + 0.529129147529602f, -0.499150782823563f, 0.528746306896210f, -0.499172955751419f, + 0.528363406658173f, -0.499194860458374f, 0.527980506420136f, -0.499216467142105f, + 0.527597606182098f, -0.499237775802612f, 0.527214705944061f, -0.499258816242218f, + 0.526831746101379f, -0.499279528856277f, 0.526448845863342f, -0.499299973249435f, + 0.526065826416016f, -0.499320119619370f, 0.525682866573334f, -0.499339967966080f, + 0.525299847126007f, -0.499359518289566f, 0.524916887283325f, -0.499378770589828f, + 0.524533808231354f, -0.499397724866867f, 0.524150788784027f, -0.499416410923004f, + 0.523767769336700f, -0.499434769153595f, 0.523384690284729f, -0.499452859163284f, + 0.523001611232758f, -0.499470651149750f, 0.522618472576141f, -0.499488145112991f, + 0.522235393524170f, -0.499505341053009f, 0.521852254867554f, -0.499522238969803f, + 0.521469116210938f, -0.499538868665695f, 0.521085977554321f, -0.499555170536041f, + 0.520702838897705f, -0.499571204185486f, 0.520319640636444f, -0.499586939811707f, + 0.519936442375183f, -0.499602377414703f, 0.519553244113922f, -0.499617516994476f, + 0.519170045852661f, -0.499632388353348f, 0.518786847591400f, -0.499646931886673f, + 0.518403589725494f, -0.499661177396774f, 0.518020391464233f, -0.499675154685974f, + 0.517637133598328f, -0.499688833951950f, 0.517253875732422f, -0.499702215194702f, + 0.516870558261871f, -0.499715298414230f, 0.516487300395966f, -0.499728083610535f, + 0.516103982925415f, -0.499740600585938f, 0.515720725059509f, -0.499752789735794f, + 0.515337407588959f, -0.499764710664749f, 0.514954090118408f, -0.499776333570480f, + 0.514570772647858f, -0.499787658452988f, 0.514187395572662f, -0.499798685312271f, + 0.513804078102112f, -0.499809414148331f, 0.513420701026917f, -0.499819844961166f, + 0.513037383556366f, -0.499830007553101f, 0.512654006481171f, -0.499839842319489f, + 0.512270629405975f, -0.499849408864975f, 0.511887252330780f, -0.499858677387238f, + 0.511503815650940f, -0.499867647886276f, 0.511120438575745f, -0.499876320362091f, + 0.510737061500549f, -0.499884694814682f, 0.510353624820709f, -0.499892801046371f, + 0.509970188140869f, -0.499900579452515f, 0.509586811065674f, -0.499908089637756f, + 0.509203374385834f, -0.499915301799774f, 0.508819937705994f, -0.499922215938568f, + 0.508436501026154f, -0.499928832054138f, 0.508053064346313f, -0.499935150146484f, + 0.507669627666473f, -0.499941170215607f, 0.507286131381989f, -0.499946922063828f, + 0.506902694702148f, -0.499952346086502f, 0.506519258022308f, -0.499957501888275f, + 0.506135761737823f, -0.499962359666824f, 0.505752325057983f, -0.499966919422150f, + 0.505368828773499f, -0.499971181154251f, 0.504985332489014f, -0.499975144863129f, + 0.504601895809174f, -0.499978810548782f, 0.504218399524689f, -0.499982208013535f, + 0.503834903240204f, -0.499985307455063f, 0.503451406955719f, -0.499988079071045f, + 0.503067970275879f, -0.499990582466125f, 0.502684473991394f, -0.499992787837982f, + 0.502300977706909f, -0.499994695186615f, 0.501917481422424f, -0.499996334314346f, + 0.501533985137939f, -0.499997645616531f, 0.501150488853455f, -0.499998688697815f, + 0.500766992568970f, -0.499999403953552f, 0.500383496284485f, -0.499999850988388f, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) +/** + @par + Generation fixed-point realCoefAQ31 array in Q31 format: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pATable[i] * pow(2, 31)) +*/ +const q31_t realCoefAQ31[8192] = { + (q31_t)0x40000000, (q31_t)0xc0000000, (q31_t)0x3ff36f02, (q31_t)0xc000013c, + (q31_t)0x3fe6de05, (q31_t)0xc00004ef, (q31_t)0x3fda4d09, (q31_t)0xc0000b1a, + (q31_t)0x3fcdbc0f, (q31_t)0xc00013bd, (q31_t)0x3fc12b16, (q31_t)0xc0001ed8, + (q31_t)0x3fb49a1f, (q31_t)0xc0002c6a, (q31_t)0x3fa8092c, (q31_t)0xc0003c74, + (q31_t)0x3f9b783c, (q31_t)0xc0004ef5, (q31_t)0x3f8ee750, (q31_t)0xc00063ee, + (q31_t)0x3f825668, (q31_t)0xc0007b5f, (q31_t)0x3f75c585, (q31_t)0xc0009547, + (q31_t)0x3f6934a8, (q31_t)0xc000b1a7, (q31_t)0x3f5ca3d0, (q31_t)0xc000d07e, + (q31_t)0x3f5012fe, (q31_t)0xc000f1ce, (q31_t)0x3f438234, (q31_t)0xc0011594, + (q31_t)0x3f36f170, (q31_t)0xc0013bd3, (q31_t)0x3f2a60b4, (q31_t)0xc0016489, + (q31_t)0x3f1dd001, (q31_t)0xc0018fb6, (q31_t)0x3f113f56, (q31_t)0xc001bd5c, + (q31_t)0x3f04aeb5, (q31_t)0xc001ed78, (q31_t)0x3ef81e1d, (q31_t)0xc002200d, + (q31_t)0x3eeb8d8f, (q31_t)0xc0025519, (q31_t)0x3edefd0c, (q31_t)0xc0028c9c, + (q31_t)0x3ed26c94, (q31_t)0xc002c697, (q31_t)0x3ec5dc28, (q31_t)0xc003030a, + (q31_t)0x3eb94bc8, (q31_t)0xc00341f4, (q31_t)0x3eacbb74, (q31_t)0xc0038356, + (q31_t)0x3ea02b2e, (q31_t)0xc003c72f, (q31_t)0x3e939af5, (q31_t)0xc0040d80, + (q31_t)0x3e870aca, (q31_t)0xc0045648, (q31_t)0x3e7a7aae, (q31_t)0xc004a188, + (q31_t)0x3e6deaa1, (q31_t)0xc004ef3f, (q31_t)0x3e615aa3, (q31_t)0xc0053f6e, + (q31_t)0x3e54cab5, (q31_t)0xc0059214, (q31_t)0x3e483ad8, (q31_t)0xc005e731, + (q31_t)0x3e3bab0b, (q31_t)0xc0063ec6, (q31_t)0x3e2f1b50, (q31_t)0xc00698d3, + (q31_t)0x3e228ba7, (q31_t)0xc006f556, (q31_t)0x3e15fc11, (q31_t)0xc0075452, + (q31_t)0x3e096c8d, (q31_t)0xc007b5c4, (q31_t)0x3dfcdd1d, (q31_t)0xc00819ae, + (q31_t)0x3df04dc0, (q31_t)0xc008800f, (q31_t)0x3de3be78, (q31_t)0xc008e8e8, + (q31_t)0x3dd72f45, (q31_t)0xc0095438, (q31_t)0x3dcaa027, (q31_t)0xc009c1ff, + (q31_t)0x3dbe111e, (q31_t)0xc00a323d, (q31_t)0x3db1822c, (q31_t)0xc00aa4f3, + (q31_t)0x3da4f351, (q31_t)0xc00b1a20, (q31_t)0x3d98648d, (q31_t)0xc00b91c4, + (q31_t)0x3d8bd5e1, (q31_t)0xc00c0be0, (q31_t)0x3d7f474d, (q31_t)0xc00c8872, + (q31_t)0x3d72b8d2, (q31_t)0xc00d077c, (q31_t)0x3d662a70, (q31_t)0xc00d88fd, + (q31_t)0x3d599c28, (q31_t)0xc00e0cf5, (q31_t)0x3d4d0df9, (q31_t)0xc00e9364, + (q31_t)0x3d407fe6, (q31_t)0xc00f1c4a, (q31_t)0x3d33f1ed, (q31_t)0xc00fa7a8, + (q31_t)0x3d276410, (q31_t)0xc010357c, (q31_t)0x3d1ad650, (q31_t)0xc010c5c7, + (q31_t)0x3d0e48ab, (q31_t)0xc011588a, (q31_t)0x3d01bb24, (q31_t)0xc011edc3, + (q31_t)0x3cf52dbb, (q31_t)0xc0128574, (q31_t)0x3ce8a06f, (q31_t)0xc0131f9b, + (q31_t)0x3cdc1342, (q31_t)0xc013bc39, (q31_t)0x3ccf8634, (q31_t)0xc0145b4e, + (q31_t)0x3cc2f945, (q31_t)0xc014fcda, (q31_t)0x3cb66c77, (q31_t)0xc015a0dd, + (q31_t)0x3ca9dfc8, (q31_t)0xc0164757, (q31_t)0x3c9d533b, (q31_t)0xc016f047, + (q31_t)0x3c90c6cf, (q31_t)0xc0179bae, (q31_t)0x3c843a85, (q31_t)0xc018498c, + (q31_t)0x3c77ae5e, (q31_t)0xc018f9e1, (q31_t)0x3c6b2259, (q31_t)0xc019acac, + (q31_t)0x3c5e9678, (q31_t)0xc01a61ee, (q31_t)0x3c520aba, (q31_t)0xc01b19a7, + (q31_t)0x3c457f21, (q31_t)0xc01bd3d6, (q31_t)0x3c38f3ac, (q31_t)0xc01c907c, + (q31_t)0x3c2c685d, (q31_t)0xc01d4f99, (q31_t)0x3c1fdd34, (q31_t)0xc01e112b, + (q31_t)0x3c135231, (q31_t)0xc01ed535, (q31_t)0x3c06c754, (q31_t)0xc01f9bb5, + (q31_t)0x3bfa3c9f, (q31_t)0xc02064ab, (q31_t)0x3bedb212, (q31_t)0xc0213018, + (q31_t)0x3be127ac, (q31_t)0xc021fdfb, (q31_t)0x3bd49d70, (q31_t)0xc022ce54, + (q31_t)0x3bc8135c, (q31_t)0xc023a124, (q31_t)0x3bbb8973, (q31_t)0xc024766a, + (q31_t)0x3baeffb3, (q31_t)0xc0254e27, (q31_t)0x3ba2761e, (q31_t)0xc0262859, + (q31_t)0x3b95ecb4, (q31_t)0xc0270502, (q31_t)0x3b896375, (q31_t)0xc027e421, + (q31_t)0x3b7cda63, (q31_t)0xc028c5b6, (q31_t)0x3b70517d, (q31_t)0xc029a9c1, + (q31_t)0x3b63c8c4, (q31_t)0xc02a9042, (q31_t)0x3b574039, (q31_t)0xc02b7939, + (q31_t)0x3b4ab7db, (q31_t)0xc02c64a6, (q31_t)0x3b3e2fac, (q31_t)0xc02d5289, + (q31_t)0x3b31a7ac, (q31_t)0xc02e42e2, (q31_t)0x3b251fdc, (q31_t)0xc02f35b1, + (q31_t)0x3b18983b, (q31_t)0xc0302af5, (q31_t)0x3b0c10cb, (q31_t)0xc03122b0, + (q31_t)0x3aff898c, (q31_t)0xc0321ce0, (q31_t)0x3af3027e, (q31_t)0xc0331986, + (q31_t)0x3ae67ba2, (q31_t)0xc03418a2, (q31_t)0x3ad9f4f8, (q31_t)0xc0351a33, + (q31_t)0x3acd6e81, (q31_t)0xc0361e3a, (q31_t)0x3ac0e83d, (q31_t)0xc03724b6, + (q31_t)0x3ab4622d, (q31_t)0xc0382da8, (q31_t)0x3aa7dc52, (q31_t)0xc0393910, + (q31_t)0x3a9b56ab, (q31_t)0xc03a46ed, (q31_t)0x3a8ed139, (q31_t)0xc03b573f, + (q31_t)0x3a824bfd, (q31_t)0xc03c6a07, (q31_t)0x3a75c6f8, (q31_t)0xc03d7f44, + (q31_t)0x3a694229, (q31_t)0xc03e96f6, (q31_t)0x3a5cbd91, (q31_t)0xc03fb11d, + (q31_t)0x3a503930, (q31_t)0xc040cdba, (q31_t)0x3a43b508, (q31_t)0xc041eccc, + (q31_t)0x3a373119, (q31_t)0xc0430e53, (q31_t)0x3a2aad62, (q31_t)0xc044324f, + (q31_t)0x3a1e29e5, (q31_t)0xc04558c0, (q31_t)0x3a11a6a3, (q31_t)0xc04681a6, + (q31_t)0x3a05239a, (q31_t)0xc047ad01, (q31_t)0x39f8a0cd, (q31_t)0xc048dad1, + (q31_t)0x39ec1e3b, (q31_t)0xc04a0b16, (q31_t)0x39df9be6, (q31_t)0xc04b3dcf, + (q31_t)0x39d319cc, (q31_t)0xc04c72fe, (q31_t)0x39c697f0, (q31_t)0xc04daaa1, + (q31_t)0x39ba1651, (q31_t)0xc04ee4b8, (q31_t)0x39ad94f0, (q31_t)0xc0502145, + (q31_t)0x39a113cd, (q31_t)0xc0516045, (q31_t)0x399492ea, (q31_t)0xc052a1bb, + (q31_t)0x39881245, (q31_t)0xc053e5a5, (q31_t)0x397b91e1, (q31_t)0xc0552c03, + (q31_t)0x396f11bc, (q31_t)0xc05674d6, (q31_t)0x396291d9, (q31_t)0xc057c01d, + (q31_t)0x39561237, (q31_t)0xc0590dd8, (q31_t)0x394992d7, (q31_t)0xc05a5e07, + (q31_t)0x393d13b8, (q31_t)0xc05bb0ab, (q31_t)0x393094dd, (q31_t)0xc05d05c3, + (q31_t)0x39241645, (q31_t)0xc05e5d4e, (q31_t)0x391797f0, (q31_t)0xc05fb74e, + (q31_t)0x390b19e0, (q31_t)0xc06113c2, (q31_t)0x38fe9c15, (q31_t)0xc06272aa, + (q31_t)0x38f21e8e, (q31_t)0xc063d405, (q31_t)0x38e5a14d, (q31_t)0xc06537d4, + (q31_t)0x38d92452, (q31_t)0xc0669e18, (q31_t)0x38cca79e, (q31_t)0xc06806ce, + (q31_t)0x38c02b31, (q31_t)0xc06971f9, (q31_t)0x38b3af0c, (q31_t)0xc06adf97, + (q31_t)0x38a7332e, (q31_t)0xc06c4fa8, (q31_t)0x389ab799, (q31_t)0xc06dc22e, + (q31_t)0x388e3c4d, (q31_t)0xc06f3726, (q31_t)0x3881c14b, (q31_t)0xc070ae92, + (q31_t)0x38754692, (q31_t)0xc0722871, (q31_t)0x3868cc24, (q31_t)0xc073a4c3, + (q31_t)0x385c5201, (q31_t)0xc0752389, (q31_t)0x384fd829, (q31_t)0xc076a4c2, + (q31_t)0x38435e9d, (q31_t)0xc078286e, (q31_t)0x3836e55d, (q31_t)0xc079ae8c, + (q31_t)0x382a6c6a, (q31_t)0xc07b371e, (q31_t)0x381df3c5, (q31_t)0xc07cc223, + (q31_t)0x38117b6d, (q31_t)0xc07e4f9b, (q31_t)0x38050364, (q31_t)0xc07fdf85, + (q31_t)0x37f88ba9, (q31_t)0xc08171e2, (q31_t)0x37ec143e, (q31_t)0xc08306b2, + (q31_t)0x37df9d22, (q31_t)0xc0849df4, (q31_t)0x37d32657, (q31_t)0xc08637a9, + (q31_t)0x37c6afdc, (q31_t)0xc087d3d0, (q31_t)0x37ba39b3, (q31_t)0xc089726a, + (q31_t)0x37adc3db, (q31_t)0xc08b1376, (q31_t)0x37a14e55, (q31_t)0xc08cb6f5, + (q31_t)0x3794d922, (q31_t)0xc08e5ce5, (q31_t)0x37886442, (q31_t)0xc0900548, + (q31_t)0x377befb5, (q31_t)0xc091b01d, (q31_t)0x376f7b7d, (q31_t)0xc0935d64, + (q31_t)0x37630799, (q31_t)0xc0950d1d, (q31_t)0x3756940a, (q31_t)0xc096bf48, + (q31_t)0x374a20d0, (q31_t)0xc09873e4, (q31_t)0x373daded, (q31_t)0xc09a2af3, + (q31_t)0x37313b60, (q31_t)0xc09be473, (q31_t)0x3724c92a, (q31_t)0xc09da065, + (q31_t)0x3718574b, (q31_t)0xc09f5ec8, (q31_t)0x370be5c4, (q31_t)0xc0a11f9d, + (q31_t)0x36ff7496, (q31_t)0xc0a2e2e3, (q31_t)0x36f303c0, (q31_t)0xc0a4a89b, + (q31_t)0x36e69344, (q31_t)0xc0a670c4, (q31_t)0x36da2321, (q31_t)0xc0a83b5e, + (q31_t)0x36cdb359, (q31_t)0xc0aa086a, (q31_t)0x36c143ec, (q31_t)0xc0abd7e6, + (q31_t)0x36b4d4d9, (q31_t)0xc0ada9d4, (q31_t)0x36a86623, (q31_t)0xc0af7e33, + (q31_t)0x369bf7c9, (q31_t)0xc0b15502, (q31_t)0x368f89cb, (q31_t)0xc0b32e42, + (q31_t)0x36831c2b, (q31_t)0xc0b509f3, (q31_t)0x3676aee8, (q31_t)0xc0b6e815, + (q31_t)0x366a4203, (q31_t)0xc0b8c8a7, (q31_t)0x365dd57d, (q31_t)0xc0baabaa, + (q31_t)0x36516956, (q31_t)0xc0bc911d, (q31_t)0x3644fd8f, (q31_t)0xc0be7901, + (q31_t)0x36389228, (q31_t)0xc0c06355, (q31_t)0x362c2721, (q31_t)0xc0c25019, + (q31_t)0x361fbc7b, (q31_t)0xc0c43f4d, (q31_t)0x36135237, (q31_t)0xc0c630f2, + (q31_t)0x3606e854, (q31_t)0xc0c82506, (q31_t)0x35fa7ed4, (q31_t)0xc0ca1b8a, + (q31_t)0x35ee15b7, (q31_t)0xc0cc147f, (q31_t)0x35e1acfd, (q31_t)0xc0ce0fe3, + (q31_t)0x35d544a7, (q31_t)0xc0d00db6, (q31_t)0x35c8dcb6, (q31_t)0xc0d20dfa, + (q31_t)0x35bc7529, (q31_t)0xc0d410ad, (q31_t)0x35b00e02, (q31_t)0xc0d615cf, + (q31_t)0x35a3a740, (q31_t)0xc0d81d61, (q31_t)0x359740e5, (q31_t)0xc0da2762, + (q31_t)0x358adaf0, (q31_t)0xc0dc33d2, (q31_t)0x357e7563, (q31_t)0xc0de42b2, + (q31_t)0x3572103d, (q31_t)0xc0e05401, (q31_t)0x3565ab80, (q31_t)0xc0e267be, + (q31_t)0x3559472b, (q31_t)0xc0e47deb, (q31_t)0x354ce33f, (q31_t)0xc0e69686, + (q31_t)0x35407fbd, (q31_t)0xc0e8b190, (q31_t)0x35341ca5, (q31_t)0xc0eacf09, + (q31_t)0x3527b9f7, (q31_t)0xc0eceef1, (q31_t)0x351b57b5, (q31_t)0xc0ef1147, + (q31_t)0x350ef5de, (q31_t)0xc0f1360b, (q31_t)0x35029473, (q31_t)0xc0f35d3e, + (q31_t)0x34f63374, (q31_t)0xc0f586df, (q31_t)0x34e9d2e3, (q31_t)0xc0f7b2ee, + (q31_t)0x34dd72be, (q31_t)0xc0f9e16b, (q31_t)0x34d11308, (q31_t)0xc0fc1257, + (q31_t)0x34c4b3c0, (q31_t)0xc0fe45b0, (q31_t)0x34b854e7, (q31_t)0xc1007b77, + (q31_t)0x34abf67e, (q31_t)0xc102b3ac, (q31_t)0x349f9884, (q31_t)0xc104ee4f, + (q31_t)0x34933afa, (q31_t)0xc1072b5f, (q31_t)0x3486dde1, (q31_t)0xc1096add, + (q31_t)0x347a8139, (q31_t)0xc10bacc8, (q31_t)0x346e2504, (q31_t)0xc10df120, + (q31_t)0x3461c940, (q31_t)0xc11037e6, (q31_t)0x34556def, (q31_t)0xc1128119, + (q31_t)0x34491311, (q31_t)0xc114ccb9, (q31_t)0x343cb8a7, (q31_t)0xc1171ac6, + (q31_t)0x34305eb0, (q31_t)0xc1196b3f, (q31_t)0x3424052f, (q31_t)0xc11bbe26, + (q31_t)0x3417ac22, (q31_t)0xc11e1379, (q31_t)0x340b538b, (q31_t)0xc1206b39, + (q31_t)0x33fefb6a, (q31_t)0xc122c566, (q31_t)0x33f2a3bf, (q31_t)0xc12521ff, + (q31_t)0x33e64c8c, (q31_t)0xc1278104, (q31_t)0x33d9f5cf, (q31_t)0xc129e276, + (q31_t)0x33cd9f8b, (q31_t)0xc12c4653, (q31_t)0x33c149bf, (q31_t)0xc12eac9d, + (q31_t)0x33b4f46c, (q31_t)0xc1311553, (q31_t)0x33a89f92, (q31_t)0xc1338075, + (q31_t)0x339c4b32, (q31_t)0xc135ee02, (q31_t)0x338ff74d, (q31_t)0xc1385dfb, + (q31_t)0x3383a3e2, (q31_t)0xc13ad060, (q31_t)0x337750f2, (q31_t)0xc13d4530, + (q31_t)0x336afe7e, (q31_t)0xc13fbc6c, (q31_t)0x335eac86, (q31_t)0xc1423613, + (q31_t)0x33525b0b, (q31_t)0xc144b225, (q31_t)0x33460a0d, (q31_t)0xc14730a3, + (q31_t)0x3339b98d, (q31_t)0xc149b18b, (q31_t)0x332d698a, (q31_t)0xc14c34df, + (q31_t)0x33211a07, (q31_t)0xc14eba9d, (q31_t)0x3314cb02, (q31_t)0xc15142c6, + (q31_t)0x33087c7d, (q31_t)0xc153cd5a, (q31_t)0x32fc2e77, (q31_t)0xc1565a58, + (q31_t)0x32efe0f2, (q31_t)0xc158e9c1, (q31_t)0x32e393ef, (q31_t)0xc15b7b94, + (q31_t)0x32d7476c, (q31_t)0xc15e0fd1, (q31_t)0x32cafb6b, (q31_t)0xc160a678, + (q31_t)0x32beafed, (q31_t)0xc1633f8a, (q31_t)0x32b264f2, (q31_t)0xc165db05, + (q31_t)0x32a61a7a, (q31_t)0xc16878eb, (q31_t)0x3299d085, (q31_t)0xc16b193a, + (q31_t)0x328d8715, (q31_t)0xc16dbbf3, (q31_t)0x32813e2a, (q31_t)0xc1706115, + (q31_t)0x3274f5c3, (q31_t)0xc17308a1, (q31_t)0x3268ade3, (q31_t)0xc175b296, + (q31_t)0x325c6688, (q31_t)0xc1785ef4, (q31_t)0x32501fb5, (q31_t)0xc17b0dbb, + (q31_t)0x3243d968, (q31_t)0xc17dbeec, (q31_t)0x323793a3, (q31_t)0xc1807285, + (q31_t)0x322b4e66, (q31_t)0xc1832888, (q31_t)0x321f09b1, (q31_t)0xc185e0f3, + (q31_t)0x3212c585, (q31_t)0xc1889bc6, (q31_t)0x320681e3, (q31_t)0xc18b5903, + (q31_t)0x31fa3ecb, (q31_t)0xc18e18a7, (q31_t)0x31edfc3d, (q31_t)0xc190dab4, + (q31_t)0x31e1ba3a, (q31_t)0xc1939f29, (q31_t)0x31d578c2, (q31_t)0xc1966606, + (q31_t)0x31c937d6, (q31_t)0xc1992f4c, (q31_t)0x31bcf777, (q31_t)0xc19bfaf9, + (q31_t)0x31b0b7a4, (q31_t)0xc19ec90d, (q31_t)0x31a4785e, (q31_t)0xc1a1998a, + (q31_t)0x319839a6, (q31_t)0xc1a46c6e, (q31_t)0x318bfb7d, (q31_t)0xc1a741b9, + (q31_t)0x317fbde2, (q31_t)0xc1aa196c, (q31_t)0x317380d6, (q31_t)0xc1acf386, + (q31_t)0x31674459, (q31_t)0xc1afd007, (q31_t)0x315b086d, (q31_t)0xc1b2aef0, + (q31_t)0x314ecd11, (q31_t)0xc1b5903f, (q31_t)0x31429247, (q31_t)0xc1b873f5, + (q31_t)0x3136580d, (q31_t)0xc1bb5a11, (q31_t)0x312a1e66, (q31_t)0xc1be4294, + (q31_t)0x311de551, (q31_t)0xc1c12d7e, (q31_t)0x3111accf, (q31_t)0xc1c41ace, + (q31_t)0x310574e0, (q31_t)0xc1c70a84, (q31_t)0x30f93d86, (q31_t)0xc1c9fca0, + (q31_t)0x30ed06bf, (q31_t)0xc1ccf122, (q31_t)0x30e0d08d, (q31_t)0xc1cfe80a, + (q31_t)0x30d49af1, (q31_t)0xc1d2e158, (q31_t)0x30c865ea, (q31_t)0xc1d5dd0c, + (q31_t)0x30bc317a, (q31_t)0xc1d8db25, (q31_t)0x30affda0, (q31_t)0xc1dbdba3, + (q31_t)0x30a3ca5d, (q31_t)0xc1dede87, (q31_t)0x309797b2, (q31_t)0xc1e1e3d0, + (q31_t)0x308b659f, (q31_t)0xc1e4eb7e, (q31_t)0x307f3424, (q31_t)0xc1e7f591, + (q31_t)0x30730342, (q31_t)0xc1eb0209, (q31_t)0x3066d2fa, (q31_t)0xc1ee10e5, + (q31_t)0x305aa34c, (q31_t)0xc1f12227, (q31_t)0x304e7438, (q31_t)0xc1f435cc, + (q31_t)0x304245c0, (q31_t)0xc1f74bd6, (q31_t)0x303617e2, (q31_t)0xc1fa6445, + (q31_t)0x3029eaa1, (q31_t)0xc1fd7f17, (q31_t)0x301dbdfb, (q31_t)0xc2009c4e, + (q31_t)0x301191f3, (q31_t)0xc203bbe8, (q31_t)0x30056687, (q31_t)0xc206dde6, + (q31_t)0x2ff93bba, (q31_t)0xc20a0248, (q31_t)0x2fed118a, (q31_t)0xc20d290d, + (q31_t)0x2fe0e7f9, (q31_t)0xc2105236, (q31_t)0x2fd4bf08, (q31_t)0xc2137dc2, + (q31_t)0x2fc896b5, (q31_t)0xc216abb1, (q31_t)0x2fbc6f03, (q31_t)0xc219dc03, + (q31_t)0x2fb047f2, (q31_t)0xc21d0eb8, (q31_t)0x2fa42181, (q31_t)0xc22043d0, + (q31_t)0x2f97fbb2, (q31_t)0xc2237b4b, (q31_t)0x2f8bd685, (q31_t)0xc226b528, + (q31_t)0x2f7fb1fa, (q31_t)0xc229f167, (q31_t)0x2f738e12, (q31_t)0xc22d3009, + (q31_t)0x2f676ace, (q31_t)0xc230710d, (q31_t)0x2f5b482d, (q31_t)0xc233b473, + (q31_t)0x2f4f2630, (q31_t)0xc236fa3b, (q31_t)0x2f4304d8, (q31_t)0xc23a4265, + (q31_t)0x2f36e426, (q31_t)0xc23d8cf1, (q31_t)0x2f2ac419, (q31_t)0xc240d9de, + (q31_t)0x2f1ea4b2, (q31_t)0xc244292c, (q31_t)0x2f1285f2, (q31_t)0xc2477adc, + (q31_t)0x2f0667d9, (q31_t)0xc24aceed, (q31_t)0x2efa4a67, (q31_t)0xc24e255e, + (q31_t)0x2eee2d9d, (q31_t)0xc2517e31, (q31_t)0x2ee2117c, (q31_t)0xc254d965, + (q31_t)0x2ed5f604, (q31_t)0xc25836f9, (q31_t)0x2ec9db35, (q31_t)0xc25b96ee, + (q31_t)0x2ebdc110, (q31_t)0xc25ef943, (q31_t)0x2eb1a796, (q31_t)0xc2625df8, + (q31_t)0x2ea58ec6, (q31_t)0xc265c50e, (q31_t)0x2e9976a1, (q31_t)0xc2692e83, + (q31_t)0x2e8d5f29, (q31_t)0xc26c9a58, (q31_t)0x2e81485c, (q31_t)0xc270088e, + (q31_t)0x2e75323c, (q31_t)0xc2737922, (q31_t)0x2e691cc9, (q31_t)0xc276ec16, + (q31_t)0x2e5d0804, (q31_t)0xc27a616a, (q31_t)0x2e50f3ed, (q31_t)0xc27dd91c, + (q31_t)0x2e44e084, (q31_t)0xc281532e, (q31_t)0x2e38cdcb, (q31_t)0xc284cf9f, + (q31_t)0x2e2cbbc1, (q31_t)0xc2884e6e, (q31_t)0x2e20aa67, (q31_t)0xc28bcf9c, + (q31_t)0x2e1499bd, (q31_t)0xc28f5329, (q31_t)0x2e0889c4, (q31_t)0xc292d914, + (q31_t)0x2dfc7a7c, (q31_t)0xc296615d, (q31_t)0x2df06be6, (q31_t)0xc299ec05, + (q31_t)0x2de45e03, (q31_t)0xc29d790a, (q31_t)0x2dd850d2, (q31_t)0xc2a1086d, + (q31_t)0x2dcc4454, (q31_t)0xc2a49a2e, (q31_t)0x2dc0388a, (q31_t)0xc2a82e4d, + (q31_t)0x2db42d74, (q31_t)0xc2abc4c9, (q31_t)0x2da82313, (q31_t)0xc2af5da2, + (q31_t)0x2d9c1967, (q31_t)0xc2b2f8d8, (q31_t)0x2d901070, (q31_t)0xc2b6966c, + (q31_t)0x2d84082f, (q31_t)0xc2ba365c, (q31_t)0x2d7800a5, (q31_t)0xc2bdd8a9, + (q31_t)0x2d6bf9d1, (q31_t)0xc2c17d52, (q31_t)0x2d5ff3b5, (q31_t)0xc2c52459, + (q31_t)0x2d53ee51, (q31_t)0xc2c8cdbb, (q31_t)0x2d47e9a5, (q31_t)0xc2cc7979, + (q31_t)0x2d3be5b1, (q31_t)0xc2d02794, (q31_t)0x2d2fe277, (q31_t)0xc2d3d80a, + (q31_t)0x2d23dff7, (q31_t)0xc2d78add, (q31_t)0x2d17de31, (q31_t)0xc2db400a, + (q31_t)0x2d0bdd25, (q31_t)0xc2def794, (q31_t)0x2cffdcd4, (q31_t)0xc2e2b178, + (q31_t)0x2cf3dd3f, (q31_t)0xc2e66db8, (q31_t)0x2ce7de66, (q31_t)0xc2ea2c53, + (q31_t)0x2cdbe04a, (q31_t)0xc2eded49, (q31_t)0x2ccfe2ea, (q31_t)0xc2f1b099, + (q31_t)0x2cc3e648, (q31_t)0xc2f57644, (q31_t)0x2cb7ea63, (q31_t)0xc2f93e4a, + (q31_t)0x2cabef3d, (q31_t)0xc2fd08a9, (q31_t)0x2c9ff4d6, (q31_t)0xc300d563, + (q31_t)0x2c93fb2e, (q31_t)0xc304a477, (q31_t)0x2c880245, (q31_t)0xc30875e5, + (q31_t)0x2c7c0a1d, (q31_t)0xc30c49ad, (q31_t)0x2c7012b5, (q31_t)0xc3101fce, + (q31_t)0x2c641c0e, (q31_t)0xc313f848, (q31_t)0x2c582629, (q31_t)0xc317d31c, + (q31_t)0x2c4c3106, (q31_t)0xc31bb049, (q31_t)0x2c403ca5, (q31_t)0xc31f8fcf, + (q31_t)0x2c344908, (q31_t)0xc32371ae, (q31_t)0x2c28562d, (q31_t)0xc32755e5, + (q31_t)0x2c1c6417, (q31_t)0xc32b3c75, (q31_t)0x2c1072c4, (q31_t)0xc32f255e, + (q31_t)0x2c048237, (q31_t)0xc333109e, (q31_t)0x2bf8926f, (q31_t)0xc336fe37, + (q31_t)0x2beca36c, (q31_t)0xc33aee27, (q31_t)0x2be0b52f, (q31_t)0xc33ee070, + (q31_t)0x2bd4c7ba, (q31_t)0xc342d510, (q31_t)0x2bc8db0b, (q31_t)0xc346cc07, + (q31_t)0x2bbcef23, (q31_t)0xc34ac556, (q31_t)0x2bb10404, (q31_t)0xc34ec0fc, + (q31_t)0x2ba519ad, (q31_t)0xc352bef9, (q31_t)0x2b99301f, (q31_t)0xc356bf4d, + (q31_t)0x2b8d475b, (q31_t)0xc35ac1f7, (q31_t)0x2b815f60, (q31_t)0xc35ec6f8, + (q31_t)0x2b75782f, (q31_t)0xc362ce50, (q31_t)0x2b6991ca, (q31_t)0xc366d7fd, + (q31_t)0x2b5dac2f, (q31_t)0xc36ae401, (q31_t)0x2b51c760, (q31_t)0xc36ef25b, + (q31_t)0x2b45e35d, (q31_t)0xc373030a, (q31_t)0x2b3a0027, (q31_t)0xc377160f, + (q31_t)0x2b2e1dbe, (q31_t)0xc37b2b6a, (q31_t)0x2b223c22, (q31_t)0xc37f4319, + (q31_t)0x2b165b54, (q31_t)0xc3835d1e, (q31_t)0x2b0a7b54, (q31_t)0xc3877978, + (q31_t)0x2afe9c24, (q31_t)0xc38b9827, (q31_t)0x2af2bdc3, (q31_t)0xc38fb92a, + (q31_t)0x2ae6e031, (q31_t)0xc393dc82, (q31_t)0x2adb0370, (q31_t)0xc398022f, + (q31_t)0x2acf277f, (q31_t)0xc39c2a2f, (q31_t)0x2ac34c60, (q31_t)0xc3a05484, + (q31_t)0x2ab77212, (q31_t)0xc3a4812c, (q31_t)0x2aab9896, (q31_t)0xc3a8b028, + (q31_t)0x2a9fbfed, (q31_t)0xc3ace178, (q31_t)0x2a93e817, (q31_t)0xc3b1151b, + (q31_t)0x2a881114, (q31_t)0xc3b54b11, (q31_t)0x2a7c3ae5, (q31_t)0xc3b9835a, + (q31_t)0x2a70658a, (q31_t)0xc3bdbdf6, (q31_t)0x2a649105, (q31_t)0xc3c1fae5, + (q31_t)0x2a58bd54, (q31_t)0xc3c63a26, (q31_t)0x2a4cea79, (q31_t)0xc3ca7bba, + (q31_t)0x2a411874, (q31_t)0xc3cebfa0, (q31_t)0x2a354746, (q31_t)0xc3d305d8, + (q31_t)0x2a2976ef, (q31_t)0xc3d74e62, (q31_t)0x2a1da770, (q31_t)0xc3db993e, + (q31_t)0x2a11d8c8, (q31_t)0xc3dfe66c, (q31_t)0x2a060af9, (q31_t)0xc3e435ea, + (q31_t)0x29fa3e03, (q31_t)0xc3e887bb, (q31_t)0x29ee71e6, (q31_t)0xc3ecdbdc, + (q31_t)0x29e2a6a3, (q31_t)0xc3f1324e, (q31_t)0x29d6dc3b, (q31_t)0xc3f58b10, + (q31_t)0x29cb12ad, (q31_t)0xc3f9e624, (q31_t)0x29bf49fa, (q31_t)0xc3fe4388, + (q31_t)0x29b38223, (q31_t)0xc402a33c, (q31_t)0x29a7bb28, (q31_t)0xc4070540, + (q31_t)0x299bf509, (q31_t)0xc40b6994, (q31_t)0x29902fc7, (q31_t)0xc40fd037, + (q31_t)0x29846b63, (q31_t)0xc414392b, (q31_t)0x2978a7dd, (q31_t)0xc418a46d, + (q31_t)0x296ce535, (q31_t)0xc41d11ff, (q31_t)0x2961236c, (q31_t)0xc42181e0, + (q31_t)0x29556282, (q31_t)0xc425f410, (q31_t)0x2949a278, (q31_t)0xc42a688f, + (q31_t)0x293de34e, (q31_t)0xc42edf5c, (q31_t)0x29322505, (q31_t)0xc4335877, + (q31_t)0x2926679c, (q31_t)0xc437d3e1, (q31_t)0x291aab16, (q31_t)0xc43c5199, + (q31_t)0x290eef71, (q31_t)0xc440d19e, (q31_t)0x290334af, (q31_t)0xc44553f2, + (q31_t)0x28f77acf, (q31_t)0xc449d892, (q31_t)0x28ebc1d3, (q31_t)0xc44e5f80, + (q31_t)0x28e009ba, (q31_t)0xc452e8bc, (q31_t)0x28d45286, (q31_t)0xc4577444, + (q31_t)0x28c89c37, (q31_t)0xc45c0219, (q31_t)0x28bce6cd, (q31_t)0xc460923b, + (q31_t)0x28b13248, (q31_t)0xc46524a9, (q31_t)0x28a57ea9, (q31_t)0xc469b963, + (q31_t)0x2899cbf1, (q31_t)0xc46e5069, (q31_t)0x288e1a20, (q31_t)0xc472e9bc, + (q31_t)0x28826936, (q31_t)0xc477855a, (q31_t)0x2876b934, (q31_t)0xc47c2344, + (q31_t)0x286b0a1a, (q31_t)0xc480c379, (q31_t)0x285f5be9, (q31_t)0xc48565f9, + (q31_t)0x2853aea1, (q31_t)0xc48a0ac4, (q31_t)0x28480243, (q31_t)0xc48eb1db, + (q31_t)0x283c56cf, (q31_t)0xc4935b3c, (q31_t)0x2830ac45, (q31_t)0xc49806e7, + (q31_t)0x282502a7, (q31_t)0xc49cb4dd, (q31_t)0x281959f4, (q31_t)0xc4a1651c, + (q31_t)0x280db22d, (q31_t)0xc4a617a6, (q31_t)0x28020b52, (q31_t)0xc4aacc7a, + (q31_t)0x27f66564, (q31_t)0xc4af8397, (q31_t)0x27eac063, (q31_t)0xc4b43cfd, + (q31_t)0x27df1c50, (q31_t)0xc4b8f8ad, (q31_t)0x27d3792b, (q31_t)0xc4bdb6a6, + (q31_t)0x27c7d6f4, (q31_t)0xc4c276e8, (q31_t)0x27bc35ad, (q31_t)0xc4c73972, + (q31_t)0x27b09555, (q31_t)0xc4cbfe45, (q31_t)0x27a4f5ed, (q31_t)0xc4d0c560, + (q31_t)0x27995776, (q31_t)0xc4d58ec3, (q31_t)0x278db9ef, (q31_t)0xc4da5a6f, + (q31_t)0x27821d59, (q31_t)0xc4df2862, (q31_t)0x277681b6, (q31_t)0xc4e3f89c, + (q31_t)0x276ae704, (q31_t)0xc4e8cb1e, (q31_t)0x275f4d45, (q31_t)0xc4ed9fe7, + (q31_t)0x2753b479, (q31_t)0xc4f276f7, (q31_t)0x27481ca1, (q31_t)0xc4f7504e, + (q31_t)0x273c85bc, (q31_t)0xc4fc2bec, (q31_t)0x2730efcc, (q31_t)0xc50109d0, + (q31_t)0x27255ad1, (q31_t)0xc505e9fb, (q31_t)0x2719c6cb, (q31_t)0xc50acc6b, + (q31_t)0x270e33bb, (q31_t)0xc50fb121, (q31_t)0x2702a1a1, (q31_t)0xc514981d, + (q31_t)0x26f7107e, (q31_t)0xc519815f, (q31_t)0x26eb8052, (q31_t)0xc51e6ce6, + (q31_t)0x26dff11d, (q31_t)0xc5235ab2, (q31_t)0x26d462e1, (q31_t)0xc5284ac3, + (q31_t)0x26c8d59c, (q31_t)0xc52d3d18, (q31_t)0x26bd4951, (q31_t)0xc53231b3, + (q31_t)0x26b1bdff, (q31_t)0xc5372891, (q31_t)0x26a633a6, (q31_t)0xc53c21b4, + (q31_t)0x269aaa48, (q31_t)0xc5411d1b, (q31_t)0x268f21e5, (q31_t)0xc5461ac6, + (q31_t)0x26839a7c, (q31_t)0xc54b1ab4, (q31_t)0x26781410, (q31_t)0xc5501ce5, + (q31_t)0x266c8e9f, (q31_t)0xc555215a, (q31_t)0x26610a2a, (q31_t)0xc55a2812, + (q31_t)0x265586b3, (q31_t)0xc55f310d, (q31_t)0x264a0438, (q31_t)0xc5643c4a, + (q31_t)0x263e82bc, (q31_t)0xc56949ca, (q31_t)0x2633023e, (q31_t)0xc56e598c, + (q31_t)0x262782be, (q31_t)0xc5736b90, (q31_t)0x261c043d, (q31_t)0xc5787fd6, + (q31_t)0x261086bc, (q31_t)0xc57d965d, (q31_t)0x26050a3b, (q31_t)0xc582af26, + (q31_t)0x25f98ebb, (q31_t)0xc587ca31, (q31_t)0x25ee143b, (q31_t)0xc58ce77c, + (q31_t)0x25e29abc, (q31_t)0xc5920708, (q31_t)0x25d72240, (q31_t)0xc59728d5, + (q31_t)0x25cbaac5, (q31_t)0xc59c4ce3, (q31_t)0x25c0344d, (q31_t)0xc5a17330, + (q31_t)0x25b4bed8, (q31_t)0xc5a69bbe, (q31_t)0x25a94a67, (q31_t)0xc5abc68c, + (q31_t)0x259dd6f9, (q31_t)0xc5b0f399, (q31_t)0x25926490, (q31_t)0xc5b622e6, + (q31_t)0x2586f32c, (q31_t)0xc5bb5472, (q31_t)0x257b82cd, (q31_t)0xc5c0883d, + (q31_t)0x25701374, (q31_t)0xc5c5be47, (q31_t)0x2564a521, (q31_t)0xc5caf690, + (q31_t)0x255937d5, (q31_t)0xc5d03118, (q31_t)0x254dcb8f, (q31_t)0xc5d56ddd, + (q31_t)0x25426051, (q31_t)0xc5daace1, (q31_t)0x2536f61b, (q31_t)0xc5dfee22, + (q31_t)0x252b8cee, (q31_t)0xc5e531a1, (q31_t)0x252024c9, (q31_t)0xc5ea775e, + (q31_t)0x2514bdad, (q31_t)0xc5efbf58, (q31_t)0x2509579b, (q31_t)0xc5f5098f, + (q31_t)0x24fdf294, (q31_t)0xc5fa5603, (q31_t)0x24f28e96, (q31_t)0xc5ffa4b3, + (q31_t)0x24e72ba4, (q31_t)0xc604f5a0, (q31_t)0x24dbc9bd, (q31_t)0xc60a48c9, + (q31_t)0x24d068e2, (q31_t)0xc60f9e2e, (q31_t)0x24c50914, (q31_t)0xc614f5cf, + (q31_t)0x24b9aa52, (q31_t)0xc61a4fac, (q31_t)0x24ae4c9d, (q31_t)0xc61fabc4, + (q31_t)0x24a2eff6, (q31_t)0xc6250a18, (q31_t)0x2497945d, (q31_t)0xc62a6aa6, + (q31_t)0x248c39d3, (q31_t)0xc62fcd6f, (q31_t)0x2480e057, (q31_t)0xc6353273, + (q31_t)0x247587eb, (q31_t)0xc63a99b1, (q31_t)0x246a308f, (q31_t)0xc6400329, + (q31_t)0x245eda43, (q31_t)0xc6456edb, (q31_t)0x24538507, (q31_t)0xc64adcc7, + (q31_t)0x244830dd, (q31_t)0xc6504ced, (q31_t)0x243cddc4, (q31_t)0xc655bf4c, + (q31_t)0x24318bbe, (q31_t)0xc65b33e4, (q31_t)0x24263ac9, (q31_t)0xc660aab5, + (q31_t)0x241aeae8, (q31_t)0xc66623be, (q31_t)0x240f9c1a, (q31_t)0xc66b9f01, + (q31_t)0x24044e60, (q31_t)0xc6711c7b, (q31_t)0x23f901ba, (q31_t)0xc6769c2e, + (q31_t)0x23edb628, (q31_t)0xc67c1e18, (q31_t)0x23e26bac, (q31_t)0xc681a23a, + (q31_t)0x23d72245, (q31_t)0xc6872894, (q31_t)0x23cbd9f4, (q31_t)0xc68cb124, + (q31_t)0x23c092b9, (q31_t)0xc6923bec, (q31_t)0x23b54c95, (q31_t)0xc697c8eb, + (q31_t)0x23aa0788, (q31_t)0xc69d5820, (q31_t)0x239ec393, (q31_t)0xc6a2e98b, + (q31_t)0x239380b6, (q31_t)0xc6a87d2d, (q31_t)0x23883ef2, (q31_t)0xc6ae1304, + (q31_t)0x237cfe47, (q31_t)0xc6b3ab12, (q31_t)0x2371beb5, (q31_t)0xc6b94554, + (q31_t)0x2366803c, (q31_t)0xc6bee1cd, (q31_t)0x235b42df, (q31_t)0xc6c4807a, + (q31_t)0x2350069b, (q31_t)0xc6ca215c, (q31_t)0x2344cb73, (q31_t)0xc6cfc472, + (q31_t)0x23399167, (q31_t)0xc6d569be, (q31_t)0x232e5876, (q31_t)0xc6db113d, + (q31_t)0x232320a2, (q31_t)0xc6e0baf0, (q31_t)0x2317e9eb, (q31_t)0xc6e666d7, + (q31_t)0x230cb451, (q31_t)0xc6ec14f2, (q31_t)0x23017fd5, (q31_t)0xc6f1c540, + (q31_t)0x22f64c77, (q31_t)0xc6f777c1, (q31_t)0x22eb1a37, (q31_t)0xc6fd2c75, + (q31_t)0x22dfe917, (q31_t)0xc702e35c, (q31_t)0x22d4b916, (q31_t)0xc7089c75, + (q31_t)0x22c98a35, (q31_t)0xc70e57c0, (q31_t)0x22be5c74, (q31_t)0xc714153e, + (q31_t)0x22b32fd4, (q31_t)0xc719d4ed, (q31_t)0x22a80456, (q31_t)0xc71f96ce, + (q31_t)0x229cd9f8, (q31_t)0xc7255ae0, (q31_t)0x2291b0bd, (q31_t)0xc72b2123, + (q31_t)0x228688a4, (q31_t)0xc730e997, (q31_t)0x227b61af, (q31_t)0xc736b43c, + (q31_t)0x22703bdc, (q31_t)0xc73c8111, (q31_t)0x2265172e, (q31_t)0xc7425016, + (q31_t)0x2259f3a3, (q31_t)0xc748214c, (q31_t)0x224ed13d, (q31_t)0xc74df4b1, + (q31_t)0x2243affc, (q31_t)0xc753ca46, (q31_t)0x22388fe1, (q31_t)0xc759a20a, + (q31_t)0x222d70eb, (q31_t)0xc75f7bfe, (q31_t)0x2222531c, (q31_t)0xc7655820, + (q31_t)0x22173674, (q31_t)0xc76b3671, (q31_t)0x220c1af3, (q31_t)0xc77116f0, + (q31_t)0x22010099, (q31_t)0xc776f99d, (q31_t)0x21f5e768, (q31_t)0xc77cde79, + (q31_t)0x21eacf5f, (q31_t)0xc782c582, (q31_t)0x21dfb87f, (q31_t)0xc788aeb9, + (q31_t)0x21d4a2c8, (q31_t)0xc78e9a1d, (q31_t)0x21c98e3b, (q31_t)0xc79487ae, + (q31_t)0x21be7ad8, (q31_t)0xc79a776c, (q31_t)0x21b368a0, (q31_t)0xc7a06957, + (q31_t)0x21a85793, (q31_t)0xc7a65d6e, (q31_t)0x219d47b1, (q31_t)0xc7ac53b1, + (q31_t)0x219238fb, (q31_t)0xc7b24c20, (q31_t)0x21872b72, (q31_t)0xc7b846ba, + (q31_t)0x217c1f15, (q31_t)0xc7be4381, (q31_t)0x217113e5, (q31_t)0xc7c44272, + (q31_t)0x216609e3, (q31_t)0xc7ca438f, (q31_t)0x215b0110, (q31_t)0xc7d046d6, + (q31_t)0x214ff96a, (q31_t)0xc7d64c47, (q31_t)0x2144f2f3, (q31_t)0xc7dc53e3, + (q31_t)0x2139edac, (q31_t)0xc7e25daa, (q31_t)0x212ee995, (q31_t)0xc7e8699a, + (q31_t)0x2123e6ad, (q31_t)0xc7ee77b3, (q31_t)0x2118e4f6, (q31_t)0xc7f487f6, + (q31_t)0x210de470, (q31_t)0xc7fa9a62, (q31_t)0x2102e51c, (q31_t)0xc800aef7, + (q31_t)0x20f7e6f9, (q31_t)0xc806c5b5, (q31_t)0x20ecea09, (q31_t)0xc80cde9b, + (q31_t)0x20e1ee4b, (q31_t)0xc812f9a9, (q31_t)0x20d6f3c1, (q31_t)0xc81916df, + (q31_t)0x20cbfa6a, (q31_t)0xc81f363d, (q31_t)0x20c10247, (q31_t)0xc82557c3, + (q31_t)0x20b60b58, (q31_t)0xc82b7b70, (q31_t)0x20ab159e, (q31_t)0xc831a143, + (q31_t)0x20a0211a, (q31_t)0xc837c93e, (q31_t)0x20952dcb, (q31_t)0xc83df35f, + (q31_t)0x208a3bb2, (q31_t)0xc8441fa6, (q31_t)0x207f4acf, (q31_t)0xc84a4e14, + (q31_t)0x20745b24, (q31_t)0xc8507ea7, (q31_t)0x20696cb0, (q31_t)0xc856b160, + (q31_t)0x205e7f74, (q31_t)0xc85ce63e, (q31_t)0x2053936f, (q31_t)0xc8631d42, + (q31_t)0x2048a8a4, (q31_t)0xc869566a, (q31_t)0x203dbf11, (q31_t)0xc86f91b7, + (q31_t)0x2032d6b8, (q31_t)0xc875cf28, (q31_t)0x2027ef99, (q31_t)0xc87c0ebd, + (q31_t)0x201d09b4, (q31_t)0xc8825077, (q31_t)0x2012250a, (q31_t)0xc8889454, + (q31_t)0x2007419b, (q31_t)0xc88eda54, (q31_t)0x1ffc5f67, (q31_t)0xc8952278, + (q31_t)0x1ff17e70, (q31_t)0xc89b6cbf, (q31_t)0x1fe69eb4, (q31_t)0xc8a1b928, + (q31_t)0x1fdbc036, (q31_t)0xc8a807b4, (q31_t)0x1fd0e2f5, (q31_t)0xc8ae5862, + (q31_t)0x1fc606f1, (q31_t)0xc8b4ab32, (q31_t)0x1fbb2c2c, (q31_t)0xc8bb0023, + (q31_t)0x1fb052a5, (q31_t)0xc8c15736, (q31_t)0x1fa57a5d, (q31_t)0xc8c7b06b, + (q31_t)0x1f9aa354, (q31_t)0xc8ce0bc0, (q31_t)0x1f8fcd8b, (q31_t)0xc8d46936, + (q31_t)0x1f84f902, (q31_t)0xc8dac8cd, (q31_t)0x1f7a25ba, (q31_t)0xc8e12a84, + (q31_t)0x1f6f53b3, (q31_t)0xc8e78e5b, (q31_t)0x1f6482ed, (q31_t)0xc8edf452, + (q31_t)0x1f59b369, (q31_t)0xc8f45c68, (q31_t)0x1f4ee527, (q31_t)0xc8fac69e, + (q31_t)0x1f441828, (q31_t)0xc90132f2, (q31_t)0x1f394c6b, (q31_t)0xc907a166, + (q31_t)0x1f2e81f3, (q31_t)0xc90e11f7, (q31_t)0x1f23b8be, (q31_t)0xc91484a8, + (q31_t)0x1f18f0ce, (q31_t)0xc91af976, (q31_t)0x1f0e2a22, (q31_t)0xc9217062, + (q31_t)0x1f0364bc, (q31_t)0xc927e96b, (q31_t)0x1ef8a09b, (q31_t)0xc92e6492, + (q31_t)0x1eedddc0, (q31_t)0xc934e1d6, (q31_t)0x1ee31c2b, (q31_t)0xc93b6137, + (q31_t)0x1ed85bdd, (q31_t)0xc941e2b4, (q31_t)0x1ecd9cd7, (q31_t)0xc948664d, + (q31_t)0x1ec2df18, (q31_t)0xc94eec03, (q31_t)0x1eb822a1, (q31_t)0xc95573d4, + (q31_t)0x1ead6773, (q31_t)0xc95bfdc1, (q31_t)0x1ea2ad8d, (q31_t)0xc96289c9, + (q31_t)0x1e97f4f1, (q31_t)0xc96917ec, (q31_t)0x1e8d3d9e, (q31_t)0xc96fa82a, + (q31_t)0x1e828796, (q31_t)0xc9763a83, (q31_t)0x1e77d2d8, (q31_t)0xc97ccef5, + (q31_t)0x1e6d1f65, (q31_t)0xc9836582, (q31_t)0x1e626d3e, (q31_t)0xc989fe29, + (q31_t)0x1e57bc62, (q31_t)0xc99098e9, (q31_t)0x1e4d0cd2, (q31_t)0xc99735c2, + (q31_t)0x1e425e8f, (q31_t)0xc99dd4b4, (q31_t)0x1e37b199, (q31_t)0xc9a475bf, + (q31_t)0x1e2d05f1, (q31_t)0xc9ab18e3, (q31_t)0x1e225b96, (q31_t)0xc9b1be1e, + (q31_t)0x1e17b28a, (q31_t)0xc9b86572, (q31_t)0x1e0d0acc, (q31_t)0xc9bf0edd, + (q31_t)0x1e02645d, (q31_t)0xc9c5ba60, (q31_t)0x1df7bf3e, (q31_t)0xc9cc67fa, + (q31_t)0x1ded1b6e, (q31_t)0xc9d317ab, (q31_t)0x1de278ef, (q31_t)0xc9d9c973, + (q31_t)0x1dd7d7c1, (q31_t)0xc9e07d51, (q31_t)0x1dcd37e4, (q31_t)0xc9e73346, + (q31_t)0x1dc29958, (q31_t)0xc9edeb50, (q31_t)0x1db7fc1e, (q31_t)0xc9f4a570, + (q31_t)0x1dad6036, (q31_t)0xc9fb61a5, (q31_t)0x1da2c5a2, (q31_t)0xca021fef, + (q31_t)0x1d982c60, (q31_t)0xca08e04f, (q31_t)0x1d8d9472, (q31_t)0xca0fa2c3, + (q31_t)0x1d82fdd8, (q31_t)0xca16674b, (q31_t)0x1d786892, (q31_t)0xca1d2de7, + (q31_t)0x1d6dd4a2, (q31_t)0xca23f698, (q31_t)0x1d634206, (q31_t)0xca2ac15b, + (q31_t)0x1d58b0c0, (q31_t)0xca318e32, (q31_t)0x1d4e20d0, (q31_t)0xca385d1d, + (q31_t)0x1d439236, (q31_t)0xca3f2e19, (q31_t)0x1d3904f4, (q31_t)0xca460129, + (q31_t)0x1d2e7908, (q31_t)0xca4cd64b, (q31_t)0x1d23ee74, (q31_t)0xca53ad7e, + (q31_t)0x1d196538, (q31_t)0xca5a86c4, (q31_t)0x1d0edd55, (q31_t)0xca61621b, + (q31_t)0x1d0456ca, (q31_t)0xca683f83, (q31_t)0x1cf9d199, (q31_t)0xca6f1efc, + (q31_t)0x1cef4dc2, (q31_t)0xca760086, (q31_t)0x1ce4cb44, (q31_t)0xca7ce420, + (q31_t)0x1cda4a21, (q31_t)0xca83c9ca, (q31_t)0x1ccfca59, (q31_t)0xca8ab184, + (q31_t)0x1cc54bec, (q31_t)0xca919b4e, (q31_t)0x1cbacedb, (q31_t)0xca988727, + (q31_t)0x1cb05326, (q31_t)0xca9f750f, (q31_t)0x1ca5d8cd, (q31_t)0xcaa66506, + (q31_t)0x1c9b5fd2, (q31_t)0xcaad570c, (q31_t)0x1c90e834, (q31_t)0xcab44b1f, + (q31_t)0x1c8671f3, (q31_t)0xcabb4141, (q31_t)0x1c7bfd11, (q31_t)0xcac23971, + (q31_t)0x1c71898d, (q31_t)0xcac933ae, (q31_t)0x1c671768, (q31_t)0xcad02ff8, + (q31_t)0x1c5ca6a2, (q31_t)0xcad72e4f, (q31_t)0x1c52373c, (q31_t)0xcade2eb3, + (q31_t)0x1c47c936, (q31_t)0xcae53123, (q31_t)0x1c3d5c91, (q31_t)0xcaec35a0, + (q31_t)0x1c32f14d, (q31_t)0xcaf33c28, (q31_t)0x1c28876a, (q31_t)0xcafa44bc, + (q31_t)0x1c1e1ee9, (q31_t)0xcb014f5b, (q31_t)0x1c13b7c9, (q31_t)0xcb085c05, + (q31_t)0x1c09520d, (q31_t)0xcb0f6aba, (q31_t)0x1bfeedb3, (q31_t)0xcb167b79, + (q31_t)0x1bf48abd, (q31_t)0xcb1d8e43, (q31_t)0x1bea292b, (q31_t)0xcb24a316, + (q31_t)0x1bdfc8fc, (q31_t)0xcb2bb9f4, (q31_t)0x1bd56a32, (q31_t)0xcb32d2da, + (q31_t)0x1bcb0cce, (q31_t)0xcb39edca, (q31_t)0x1bc0b0ce, (q31_t)0xcb410ac3, + (q31_t)0x1bb65634, (q31_t)0xcb4829c4, (q31_t)0x1babfd01, (q31_t)0xcb4f4acd, + (q31_t)0x1ba1a534, (q31_t)0xcb566ddf, (q31_t)0x1b974ece, (q31_t)0xcb5d92f8, + (q31_t)0x1b8cf9cf, (q31_t)0xcb64ba19, (q31_t)0x1b82a638, (q31_t)0xcb6be341, + (q31_t)0x1b785409, (q31_t)0xcb730e70, (q31_t)0x1b6e0342, (q31_t)0xcb7a3ba5, + (q31_t)0x1b63b3e5, (q31_t)0xcb816ae1, (q31_t)0x1b5965f1, (q31_t)0xcb889c23, + (q31_t)0x1b4f1967, (q31_t)0xcb8fcf6b, (q31_t)0x1b44ce46, (q31_t)0xcb9704b9, + (q31_t)0x1b3a8491, (q31_t)0xcb9e3c0b, (q31_t)0x1b303c46, (q31_t)0xcba57563, + (q31_t)0x1b25f566, (q31_t)0xcbacb0bf, (q31_t)0x1b1baff2, (q31_t)0xcbb3ee20, + (q31_t)0x1b116beb, (q31_t)0xcbbb2d85, (q31_t)0x1b072950, (q31_t)0xcbc26eee, + (q31_t)0x1afce821, (q31_t)0xcbc9b25a, (q31_t)0x1af2a860, (q31_t)0xcbd0f7ca, + (q31_t)0x1ae86a0d, (q31_t)0xcbd83f3d, (q31_t)0x1ade2d28, (q31_t)0xcbdf88b3, + (q31_t)0x1ad3f1b1, (q31_t)0xcbe6d42b, (q31_t)0x1ac9b7a9, (q31_t)0xcbee21a5, + (q31_t)0x1abf7f11, (q31_t)0xcbf57121, (q31_t)0x1ab547e8, (q31_t)0xcbfcc29f, + (q31_t)0x1aab122f, (q31_t)0xcc04161e, (q31_t)0x1aa0dde7, (q31_t)0xcc0b6b9e, + (q31_t)0x1a96ab0f, (q31_t)0xcc12c31f, (q31_t)0x1a8c79a9, (q31_t)0xcc1a1ca0, + (q31_t)0x1a8249b4, (q31_t)0xcc217822, (q31_t)0x1a781b31, (q31_t)0xcc28d5a3, + (q31_t)0x1a6dee21, (q31_t)0xcc303524, (q31_t)0x1a63c284, (q31_t)0xcc3796a5, + (q31_t)0x1a599859, (q31_t)0xcc3efa25, (q31_t)0x1a4f6fa3, (q31_t)0xcc465fa3, + (q31_t)0x1a454860, (q31_t)0xcc4dc720, (q31_t)0x1a3b2292, (q31_t)0xcc55309b, + (q31_t)0x1a30fe38, (q31_t)0xcc5c9c14, (q31_t)0x1a26db54, (q31_t)0xcc64098b, + (q31_t)0x1a1cb9e5, (q31_t)0xcc6b78ff, (q31_t)0x1a1299ec, (q31_t)0xcc72ea70, + (q31_t)0x1a087b69, (q31_t)0xcc7a5dde, (q31_t)0x19fe5e5e, (q31_t)0xcc81d349, + (q31_t)0x19f442c9, (q31_t)0xcc894aaf, (q31_t)0x19ea28ac, (q31_t)0xcc90c412, + (q31_t)0x19e01006, (q31_t)0xcc983f70, (q31_t)0x19d5f8d9, (q31_t)0xcc9fbcca, + (q31_t)0x19cbe325, (q31_t)0xcca73c1e, (q31_t)0x19c1cee9, (q31_t)0xccaebd6e, + (q31_t)0x19b7bc27, (q31_t)0xccb640b8, (q31_t)0x19adaadf, (q31_t)0xccbdc5fc, + (q31_t)0x19a39b11, (q31_t)0xccc54d3a, (q31_t)0x19998cbe, (q31_t)0xccccd671, + (q31_t)0x198f7fe6, (q31_t)0xccd461a2, (q31_t)0x19857489, (q31_t)0xccdbeecc, + (q31_t)0x197b6aa8, (q31_t)0xcce37def, (q31_t)0x19716243, (q31_t)0xcceb0f0a, + (q31_t)0x19675b5a, (q31_t)0xccf2a21d, (q31_t)0x195d55ef, (q31_t)0xccfa3729, + (q31_t)0x19535201, (q31_t)0xcd01ce2b, (q31_t)0x19494f90, (q31_t)0xcd096725, + (q31_t)0x193f4e9e, (q31_t)0xcd110216, (q31_t)0x19354f2a, (q31_t)0xcd189efe, + (q31_t)0x192b5135, (q31_t)0xcd203ddc, (q31_t)0x192154bf, (q31_t)0xcd27deb0, + (q31_t)0x191759c9, (q31_t)0xcd2f817b, (q31_t)0x190d6053, (q31_t)0xcd37263a, + (q31_t)0x1903685d, (q31_t)0xcd3eccef, (q31_t)0x18f971e8, (q31_t)0xcd467599, + (q31_t)0x18ef7cf4, (q31_t)0xcd4e2037, (q31_t)0x18e58982, (q31_t)0xcd55ccca, + (q31_t)0x18db9792, (q31_t)0xcd5d7b50, (q31_t)0x18d1a724, (q31_t)0xcd652bcb, + (q31_t)0x18c7b838, (q31_t)0xcd6cde39, (q31_t)0x18bdcad0, (q31_t)0xcd74929a, + (q31_t)0x18b3deeb, (q31_t)0xcd7c48ee, (q31_t)0x18a9f48a, (q31_t)0xcd840134, + (q31_t)0x18a00bae, (q31_t)0xcd8bbb6d, (q31_t)0x18962456, (q31_t)0xcd937798, + (q31_t)0x188c3e83, (q31_t)0xcd9b35b4, (q31_t)0x18825a35, (q31_t)0xcda2f5c2, + (q31_t)0x1878776d, (q31_t)0xcdaab7c0, (q31_t)0x186e962b, (q31_t)0xcdb27bb0, + (q31_t)0x1864b670, (q31_t)0xcdba4190, (q31_t)0x185ad83c, (q31_t)0xcdc20960, + (q31_t)0x1850fb8e, (q31_t)0xcdc9d320, (q31_t)0x18472069, (q31_t)0xcdd19ed0, + (q31_t)0x183d46cc, (q31_t)0xcdd96c6f, (q31_t)0x18336eb7, (q31_t)0xcde13bfd, + (q31_t)0x1829982b, (q31_t)0xcde90d79, (q31_t)0x181fc328, (q31_t)0xcdf0e0e4, + (q31_t)0x1815efae, (q31_t)0xcdf8b63d, (q31_t)0x180c1dbf, (q31_t)0xce008d84, + (q31_t)0x18024d59, (q31_t)0xce0866b8, (q31_t)0x17f87e7f, (q31_t)0xce1041d9, + (q31_t)0x17eeb130, (q31_t)0xce181ee8, (q31_t)0x17e4e56c, (q31_t)0xce1ffde2, + (q31_t)0x17db1b34, (q31_t)0xce27dec9, (q31_t)0x17d15288, (q31_t)0xce2fc19c, + (q31_t)0x17c78b68, (q31_t)0xce37a65b, (q31_t)0x17bdc5d6, (q31_t)0xce3f8d05, + (q31_t)0x17b401d1, (q31_t)0xce47759a, (q31_t)0x17aa3f5a, (q31_t)0xce4f6019, + (q31_t)0x17a07e70, (q31_t)0xce574c84, (q31_t)0x1796bf16, (q31_t)0xce5f3ad8, + (q31_t)0x178d014a, (q31_t)0xce672b16, (q31_t)0x1783450d, (q31_t)0xce6f1d3d, + (q31_t)0x17798a60, (q31_t)0xce77114e, (q31_t)0x176fd143, (q31_t)0xce7f0748, + (q31_t)0x176619b6, (q31_t)0xce86ff2a, (q31_t)0x175c63ba, (q31_t)0xce8ef8f4, + (q31_t)0x1752af4f, (q31_t)0xce96f4a7, (q31_t)0x1748fc75, (q31_t)0xce9ef241, + (q31_t)0x173f4b2e, (q31_t)0xcea6f1c2, (q31_t)0x17359b78, (q31_t)0xceaef32b, + (q31_t)0x172bed55, (q31_t)0xceb6f67a, (q31_t)0x172240c5, (q31_t)0xcebefbb0, + (q31_t)0x171895c9, (q31_t)0xcec702cb, (q31_t)0x170eec60, (q31_t)0xcecf0bcd, + (q31_t)0x1705448b, (q31_t)0xced716b4, (q31_t)0x16fb9e4b, (q31_t)0xcedf2380, + (q31_t)0x16f1f99f, (q31_t)0xcee73231, (q31_t)0x16e85689, (q31_t)0xceef42c7, + (q31_t)0x16deb508, (q31_t)0xcef75541, (q31_t)0x16d5151d, (q31_t)0xceff699f, + (q31_t)0x16cb76c9, (q31_t)0xcf077fe1, (q31_t)0x16c1da0b, (q31_t)0xcf0f9805, + (q31_t)0x16b83ee4, (q31_t)0xcf17b20d, (q31_t)0x16aea555, (q31_t)0xcf1fcdf8, + (q31_t)0x16a50d5d, (q31_t)0xcf27ebc5, (q31_t)0x169b76fe, (q31_t)0xcf300b74, + (q31_t)0x1691e237, (q31_t)0xcf382d05, (q31_t)0x16884f09, (q31_t)0xcf405077, + (q31_t)0x167ebd74, (q31_t)0xcf4875ca, (q31_t)0x16752d79, (q31_t)0xcf509cfe, + (q31_t)0x166b9f18, (q31_t)0xcf58c613, (q31_t)0x16621251, (q31_t)0xcf60f108, + (q31_t)0x16588725, (q31_t)0xcf691ddd, (q31_t)0x164efd94, (q31_t)0xcf714c91, + (q31_t)0x1645759f, (q31_t)0xcf797d24, (q31_t)0x163bef46, (q31_t)0xcf81af97, + (q31_t)0x16326a88, (q31_t)0xcf89e3e8, (q31_t)0x1628e767, (q31_t)0xcf921a17, + (q31_t)0x161f65e4, (q31_t)0xcf9a5225, (q31_t)0x1615e5fd, (q31_t)0xcfa28c10, + (q31_t)0x160c67b4, (q31_t)0xcfaac7d8, (q31_t)0x1602eb0a, (q31_t)0xcfb3057d, + (q31_t)0x15f96ffd, (q31_t)0xcfbb4500, (q31_t)0x15eff690, (q31_t)0xcfc3865e, + (q31_t)0x15e67ec1, (q31_t)0xcfcbc999, (q31_t)0x15dd0892, (q31_t)0xcfd40eaf, + (q31_t)0x15d39403, (q31_t)0xcfdc55a1, (q31_t)0x15ca2115, (q31_t)0xcfe49e6d, + (q31_t)0x15c0afc6, (q31_t)0xcfece915, (q31_t)0x15b74019, (q31_t)0xcff53597, + (q31_t)0x15add20d, (q31_t)0xcffd83f4, (q31_t)0x15a465a3, (q31_t)0xd005d42a, + (q31_t)0x159afadb, (q31_t)0xd00e2639, (q31_t)0x159191b5, (q31_t)0xd0167a22, + (q31_t)0x15882a32, (q31_t)0xd01ecfe4, (q31_t)0x157ec452, (q31_t)0xd027277e, + (q31_t)0x15756016, (q31_t)0xd02f80f1, (q31_t)0x156bfd7d, (q31_t)0xd037dc3b, + (q31_t)0x15629c89, (q31_t)0xd040395d, (q31_t)0x15593d3a, (q31_t)0xd0489856, + (q31_t)0x154fdf8f, (q31_t)0xd050f926, (q31_t)0x15468389, (q31_t)0xd0595bcd, + (q31_t)0x153d292a, (q31_t)0xd061c04a, (q31_t)0x1533d070, (q31_t)0xd06a269d, + (q31_t)0x152a795d, (q31_t)0xd0728ec6, (q31_t)0x152123f0, (q31_t)0xd07af8c4, + (q31_t)0x1517d02b, (q31_t)0xd0836497, (q31_t)0x150e7e0d, (q31_t)0xd08bd23f, + (q31_t)0x15052d97, (q31_t)0xd09441bb, (q31_t)0x14fbdec9, (q31_t)0xd09cb30b, + (q31_t)0x14f291a4, (q31_t)0xd0a5262f, (q31_t)0x14e94627, (q31_t)0xd0ad9b26, + (q31_t)0x14dffc54, (q31_t)0xd0b611f1, (q31_t)0x14d6b42b, (q31_t)0xd0be8a8d, + (q31_t)0x14cd6dab, (q31_t)0xd0c704fd, (q31_t)0x14c428d6, (q31_t)0xd0cf813e, + (q31_t)0x14bae5ab, (q31_t)0xd0d7ff51, (q31_t)0x14b1a42c, (q31_t)0xd0e07f36, + (q31_t)0x14a86458, (q31_t)0xd0e900ec, (q31_t)0x149f2630, (q31_t)0xd0f18472, + (q31_t)0x1495e9b3, (q31_t)0xd0fa09c9, (q31_t)0x148caee4, (q31_t)0xd10290f0, + (q31_t)0x148375c1, (q31_t)0xd10b19e7, (q31_t)0x147a3e4b, (q31_t)0xd113a4ad, + (q31_t)0x14710883, (q31_t)0xd11c3142, (q31_t)0x1467d469, (q31_t)0xd124bfa6, + (q31_t)0x145ea1fd, (q31_t)0xd12d4fd9, (q31_t)0x14557140, (q31_t)0xd135e1d9, + (q31_t)0x144c4232, (q31_t)0xd13e75a8, (q31_t)0x144314d3, (q31_t)0xd1470b44, + (q31_t)0x1439e923, (q31_t)0xd14fa2ad, (q31_t)0x1430bf24, (q31_t)0xd1583be2, + (q31_t)0x142796d5, (q31_t)0xd160d6e5, (q31_t)0x141e7037, (q31_t)0xd16973b3, + (q31_t)0x14154b4a, (q31_t)0xd172124d, (q31_t)0x140c280e, (q31_t)0xd17ab2b3, + (q31_t)0x14030684, (q31_t)0xd18354e4, (q31_t)0x13f9e6ad, (q31_t)0xd18bf8e0, + (q31_t)0x13f0c887, (q31_t)0xd1949ea6, (q31_t)0x13e7ac15, (q31_t)0xd19d4636, + (q31_t)0x13de9156, (q31_t)0xd1a5ef90, (q31_t)0x13d5784a, (q31_t)0xd1ae9ab4, + (q31_t)0x13cc60f2, (q31_t)0xd1b747a0, (q31_t)0x13c34b4f, (q31_t)0xd1bff656, + (q31_t)0x13ba3760, (q31_t)0xd1c8a6d4, (q31_t)0x13b12526, (q31_t)0xd1d1591a, + (q31_t)0x13a814a2, (q31_t)0xd1da0d28, (q31_t)0x139f05d3, (q31_t)0xd1e2c2fd, + (q31_t)0x1395f8ba, (q31_t)0xd1eb7a9a, (q31_t)0x138ced57, (q31_t)0xd1f433fd, + (q31_t)0x1383e3ab, (q31_t)0xd1fcef27, (q31_t)0x137adbb6, (q31_t)0xd205ac17, + (q31_t)0x1371d579, (q31_t)0xd20e6acc, (q31_t)0x1368d0f3, (q31_t)0xd2172b48, + (q31_t)0x135fce26, (q31_t)0xd21fed88, (q31_t)0x1356cd11, (q31_t)0xd228b18d, + (q31_t)0x134dcdb4, (q31_t)0xd2317756, (q31_t)0x1344d011, (q31_t)0xd23a3ee4, + (q31_t)0x133bd427, (q31_t)0xd2430835, (q31_t)0x1332d9f7, (q31_t)0xd24bd34a, + (q31_t)0x1329e181, (q31_t)0xd254a021, (q31_t)0x1320eac6, (q31_t)0xd25d6ebc, + (q31_t)0x1317f5c6, (q31_t)0xd2663f19, (q31_t)0x130f0280, (q31_t)0xd26f1138, + (q31_t)0x130610f7, (q31_t)0xd277e518, (q31_t)0x12fd2129, (q31_t)0xd280babb, + (q31_t)0x12f43318, (q31_t)0xd289921e, (q31_t)0x12eb46c3, (q31_t)0xd2926b41, + (q31_t)0x12e25c2b, (q31_t)0xd29b4626, (q31_t)0x12d97350, (q31_t)0xd2a422ca, + (q31_t)0x12d08c33, (q31_t)0xd2ad012e, (q31_t)0x12c7a6d4, (q31_t)0xd2b5e151, + (q31_t)0x12bec333, (q31_t)0xd2bec333, (q31_t)0x12b5e151, (q31_t)0xd2c7a6d4, + (q31_t)0x12ad012e, (q31_t)0xd2d08c33, (q31_t)0x12a422ca, (q31_t)0xd2d97350, + (q31_t)0x129b4626, (q31_t)0xd2e25c2b, (q31_t)0x12926b41, (q31_t)0xd2eb46c3, + (q31_t)0x1289921e, (q31_t)0xd2f43318, (q31_t)0x1280babb, (q31_t)0xd2fd2129, + (q31_t)0x1277e518, (q31_t)0xd30610f7, (q31_t)0x126f1138, (q31_t)0xd30f0280, + (q31_t)0x12663f19, (q31_t)0xd317f5c6, (q31_t)0x125d6ebc, (q31_t)0xd320eac6, + (q31_t)0x1254a021, (q31_t)0xd329e181, (q31_t)0x124bd34a, (q31_t)0xd332d9f7, + (q31_t)0x12430835, (q31_t)0xd33bd427, (q31_t)0x123a3ee4, (q31_t)0xd344d011, + (q31_t)0x12317756, (q31_t)0xd34dcdb4, (q31_t)0x1228b18d, (q31_t)0xd356cd11, + (q31_t)0x121fed88, (q31_t)0xd35fce26, (q31_t)0x12172b48, (q31_t)0xd368d0f3, + (q31_t)0x120e6acc, (q31_t)0xd371d579, (q31_t)0x1205ac17, (q31_t)0xd37adbb6, + (q31_t)0x11fcef27, (q31_t)0xd383e3ab, (q31_t)0x11f433fd, (q31_t)0xd38ced57, + (q31_t)0x11eb7a9a, (q31_t)0xd395f8ba, (q31_t)0x11e2c2fd, (q31_t)0xd39f05d3, + (q31_t)0x11da0d28, (q31_t)0xd3a814a2, (q31_t)0x11d1591a, (q31_t)0xd3b12526, + (q31_t)0x11c8a6d4, (q31_t)0xd3ba3760, (q31_t)0x11bff656, (q31_t)0xd3c34b4f, + (q31_t)0x11b747a0, (q31_t)0xd3cc60f2, (q31_t)0x11ae9ab4, (q31_t)0xd3d5784a, + (q31_t)0x11a5ef90, (q31_t)0xd3de9156, (q31_t)0x119d4636, (q31_t)0xd3e7ac15, + (q31_t)0x11949ea6, (q31_t)0xd3f0c887, (q31_t)0x118bf8e0, (q31_t)0xd3f9e6ad, + (q31_t)0x118354e4, (q31_t)0xd4030684, (q31_t)0x117ab2b3, (q31_t)0xd40c280e, + (q31_t)0x1172124d, (q31_t)0xd4154b4a, (q31_t)0x116973b3, (q31_t)0xd41e7037, + (q31_t)0x1160d6e5, (q31_t)0xd42796d5, (q31_t)0x11583be2, (q31_t)0xd430bf24, + (q31_t)0x114fa2ad, (q31_t)0xd439e923, (q31_t)0x11470b44, (q31_t)0xd44314d3, + (q31_t)0x113e75a8, (q31_t)0xd44c4232, (q31_t)0x1135e1d9, (q31_t)0xd4557140, + (q31_t)0x112d4fd9, (q31_t)0xd45ea1fd, (q31_t)0x1124bfa6, (q31_t)0xd467d469, + (q31_t)0x111c3142, (q31_t)0xd4710883, (q31_t)0x1113a4ad, (q31_t)0xd47a3e4b, + (q31_t)0x110b19e7, (q31_t)0xd48375c1, (q31_t)0x110290f0, (q31_t)0xd48caee4, + (q31_t)0x10fa09c9, (q31_t)0xd495e9b3, (q31_t)0x10f18472, (q31_t)0xd49f2630, + (q31_t)0x10e900ec, (q31_t)0xd4a86458, (q31_t)0x10e07f36, (q31_t)0xd4b1a42c, + (q31_t)0x10d7ff51, (q31_t)0xd4bae5ab, (q31_t)0x10cf813e, (q31_t)0xd4c428d6, + (q31_t)0x10c704fd, (q31_t)0xd4cd6dab, (q31_t)0x10be8a8d, (q31_t)0xd4d6b42b, + (q31_t)0x10b611f1, (q31_t)0xd4dffc54, (q31_t)0x10ad9b26, (q31_t)0xd4e94627, + (q31_t)0x10a5262f, (q31_t)0xd4f291a4, (q31_t)0x109cb30b, (q31_t)0xd4fbdec9, + (q31_t)0x109441bb, (q31_t)0xd5052d97, (q31_t)0x108bd23f, (q31_t)0xd50e7e0d, + (q31_t)0x10836497, (q31_t)0xd517d02b, (q31_t)0x107af8c4, (q31_t)0xd52123f0, + (q31_t)0x10728ec6, (q31_t)0xd52a795d, (q31_t)0x106a269d, (q31_t)0xd533d070, + (q31_t)0x1061c04a, (q31_t)0xd53d292a, (q31_t)0x10595bcd, (q31_t)0xd5468389, + (q31_t)0x1050f926, (q31_t)0xd54fdf8f, (q31_t)0x10489856, (q31_t)0xd5593d3a, + (q31_t)0x1040395d, (q31_t)0xd5629c89, (q31_t)0x1037dc3b, (q31_t)0xd56bfd7d, + (q31_t)0x102f80f1, (q31_t)0xd5756016, (q31_t)0x1027277e, (q31_t)0xd57ec452, + (q31_t)0x101ecfe4, (q31_t)0xd5882a32, (q31_t)0x10167a22, (q31_t)0xd59191b5, + (q31_t)0x100e2639, (q31_t)0xd59afadb, (q31_t)0x1005d42a, (q31_t)0xd5a465a3, + (q31_t)0xffd83f4, (q31_t)0xd5add20d, (q31_t)0xff53597, (q31_t)0xd5b74019, + (q31_t)0xfece915, (q31_t)0xd5c0afc6, (q31_t)0xfe49e6d, (q31_t)0xd5ca2115, + (q31_t)0xfdc55a1, (q31_t)0xd5d39403, (q31_t)0xfd40eaf, (q31_t)0xd5dd0892, + (q31_t)0xfcbc999, (q31_t)0xd5e67ec1, (q31_t)0xfc3865e, (q31_t)0xd5eff690, + (q31_t)0xfbb4500, (q31_t)0xd5f96ffd, (q31_t)0xfb3057d, (q31_t)0xd602eb0a, + (q31_t)0xfaac7d8, (q31_t)0xd60c67b4, (q31_t)0xfa28c10, (q31_t)0xd615e5fd, + (q31_t)0xf9a5225, (q31_t)0xd61f65e4, (q31_t)0xf921a17, (q31_t)0xd628e767, + (q31_t)0xf89e3e8, (q31_t)0xd6326a88, (q31_t)0xf81af97, (q31_t)0xd63bef46, + (q31_t)0xf797d24, (q31_t)0xd645759f, (q31_t)0xf714c91, (q31_t)0xd64efd94, + (q31_t)0xf691ddd, (q31_t)0xd6588725, (q31_t)0xf60f108, (q31_t)0xd6621251, + (q31_t)0xf58c613, (q31_t)0xd66b9f18, (q31_t)0xf509cfe, (q31_t)0xd6752d79, + (q31_t)0xf4875ca, (q31_t)0xd67ebd74, (q31_t)0xf405077, (q31_t)0xd6884f09, + (q31_t)0xf382d05, (q31_t)0xd691e237, (q31_t)0xf300b74, (q31_t)0xd69b76fe, + (q31_t)0xf27ebc5, (q31_t)0xd6a50d5d, (q31_t)0xf1fcdf8, (q31_t)0xd6aea555, + (q31_t)0xf17b20d, (q31_t)0xd6b83ee4, (q31_t)0xf0f9805, (q31_t)0xd6c1da0b, + (q31_t)0xf077fe1, (q31_t)0xd6cb76c9, (q31_t)0xeff699f, (q31_t)0xd6d5151d, + (q31_t)0xef75541, (q31_t)0xd6deb508, (q31_t)0xeef42c7, (q31_t)0xd6e85689, + (q31_t)0xee73231, (q31_t)0xd6f1f99f, (q31_t)0xedf2380, (q31_t)0xd6fb9e4b, + (q31_t)0xed716b4, (q31_t)0xd705448b, (q31_t)0xecf0bcd, (q31_t)0xd70eec60, + (q31_t)0xec702cb, (q31_t)0xd71895c9, (q31_t)0xebefbb0, (q31_t)0xd72240c5, + (q31_t)0xeb6f67a, (q31_t)0xd72bed55, (q31_t)0xeaef32b, (q31_t)0xd7359b78, + (q31_t)0xea6f1c2, (q31_t)0xd73f4b2e, (q31_t)0xe9ef241, (q31_t)0xd748fc75, + (q31_t)0xe96f4a7, (q31_t)0xd752af4f, (q31_t)0xe8ef8f4, (q31_t)0xd75c63ba, + (q31_t)0xe86ff2a, (q31_t)0xd76619b6, (q31_t)0xe7f0748, (q31_t)0xd76fd143, + (q31_t)0xe77114e, (q31_t)0xd7798a60, (q31_t)0xe6f1d3d, (q31_t)0xd783450d, + (q31_t)0xe672b16, (q31_t)0xd78d014a, (q31_t)0xe5f3ad8, (q31_t)0xd796bf16, + (q31_t)0xe574c84, (q31_t)0xd7a07e70, (q31_t)0xe4f6019, (q31_t)0xd7aa3f5a, + (q31_t)0xe47759a, (q31_t)0xd7b401d1, (q31_t)0xe3f8d05, (q31_t)0xd7bdc5d6, + (q31_t)0xe37a65b, (q31_t)0xd7c78b68, (q31_t)0xe2fc19c, (q31_t)0xd7d15288, + (q31_t)0xe27dec9, (q31_t)0xd7db1b34, (q31_t)0xe1ffde2, (q31_t)0xd7e4e56c, + (q31_t)0xe181ee8, (q31_t)0xd7eeb130, (q31_t)0xe1041d9, (q31_t)0xd7f87e7f, + (q31_t)0xe0866b8, (q31_t)0xd8024d59, (q31_t)0xe008d84, (q31_t)0xd80c1dbf, + (q31_t)0xdf8b63d, (q31_t)0xd815efae, (q31_t)0xdf0e0e4, (q31_t)0xd81fc328, + (q31_t)0xde90d79, (q31_t)0xd829982b, (q31_t)0xde13bfd, (q31_t)0xd8336eb7, + (q31_t)0xdd96c6f, (q31_t)0xd83d46cc, (q31_t)0xdd19ed0, (q31_t)0xd8472069, + (q31_t)0xdc9d320, (q31_t)0xd850fb8e, (q31_t)0xdc20960, (q31_t)0xd85ad83c, + (q31_t)0xdba4190, (q31_t)0xd864b670, (q31_t)0xdb27bb0, (q31_t)0xd86e962b, + (q31_t)0xdaab7c0, (q31_t)0xd878776d, (q31_t)0xda2f5c2, (q31_t)0xd8825a35, + (q31_t)0xd9b35b4, (q31_t)0xd88c3e83, (q31_t)0xd937798, (q31_t)0xd8962456, + (q31_t)0xd8bbb6d, (q31_t)0xd8a00bae, (q31_t)0xd840134, (q31_t)0xd8a9f48a, + (q31_t)0xd7c48ee, (q31_t)0xd8b3deeb, (q31_t)0xd74929a, (q31_t)0xd8bdcad0, + (q31_t)0xd6cde39, (q31_t)0xd8c7b838, (q31_t)0xd652bcb, (q31_t)0xd8d1a724, + (q31_t)0xd5d7b50, (q31_t)0xd8db9792, (q31_t)0xd55ccca, (q31_t)0xd8e58982, + (q31_t)0xd4e2037, (q31_t)0xd8ef7cf4, (q31_t)0xd467599, (q31_t)0xd8f971e8, + (q31_t)0xd3eccef, (q31_t)0xd903685d, (q31_t)0xd37263a, (q31_t)0xd90d6053, + (q31_t)0xd2f817b, (q31_t)0xd91759c9, (q31_t)0xd27deb0, (q31_t)0xd92154bf, + (q31_t)0xd203ddc, (q31_t)0xd92b5135, (q31_t)0xd189efe, (q31_t)0xd9354f2a, + (q31_t)0xd110216, (q31_t)0xd93f4e9e, (q31_t)0xd096725, (q31_t)0xd9494f90, + (q31_t)0xd01ce2b, (q31_t)0xd9535201, (q31_t)0xcfa3729, (q31_t)0xd95d55ef, + (q31_t)0xcf2a21d, (q31_t)0xd9675b5a, (q31_t)0xceb0f0a, (q31_t)0xd9716243, + (q31_t)0xce37def, (q31_t)0xd97b6aa8, (q31_t)0xcdbeecc, (q31_t)0xd9857489, + (q31_t)0xcd461a2, (q31_t)0xd98f7fe6, (q31_t)0xcccd671, (q31_t)0xd9998cbe, + (q31_t)0xcc54d3a, (q31_t)0xd9a39b11, (q31_t)0xcbdc5fc, (q31_t)0xd9adaadf, + (q31_t)0xcb640b8, (q31_t)0xd9b7bc27, (q31_t)0xcaebd6e, (q31_t)0xd9c1cee9, + (q31_t)0xca73c1e, (q31_t)0xd9cbe325, (q31_t)0xc9fbcca, (q31_t)0xd9d5f8d9, + (q31_t)0xc983f70, (q31_t)0xd9e01006, (q31_t)0xc90c412, (q31_t)0xd9ea28ac, + (q31_t)0xc894aaf, (q31_t)0xd9f442c9, (q31_t)0xc81d349, (q31_t)0xd9fe5e5e, + (q31_t)0xc7a5dde, (q31_t)0xda087b69, (q31_t)0xc72ea70, (q31_t)0xda1299ec, + (q31_t)0xc6b78ff, (q31_t)0xda1cb9e5, (q31_t)0xc64098b, (q31_t)0xda26db54, + (q31_t)0xc5c9c14, (q31_t)0xda30fe38, (q31_t)0xc55309b, (q31_t)0xda3b2292, + (q31_t)0xc4dc720, (q31_t)0xda454860, (q31_t)0xc465fa3, (q31_t)0xda4f6fa3, + (q31_t)0xc3efa25, (q31_t)0xda599859, (q31_t)0xc3796a5, (q31_t)0xda63c284, + (q31_t)0xc303524, (q31_t)0xda6dee21, (q31_t)0xc28d5a3, (q31_t)0xda781b31, + (q31_t)0xc217822, (q31_t)0xda8249b4, (q31_t)0xc1a1ca0, (q31_t)0xda8c79a9, + (q31_t)0xc12c31f, (q31_t)0xda96ab0f, (q31_t)0xc0b6b9e, (q31_t)0xdaa0dde7, + (q31_t)0xc04161e, (q31_t)0xdaab122f, (q31_t)0xbfcc29f, (q31_t)0xdab547e8, + (q31_t)0xbf57121, (q31_t)0xdabf7f11, (q31_t)0xbee21a5, (q31_t)0xdac9b7a9, + (q31_t)0xbe6d42b, (q31_t)0xdad3f1b1, (q31_t)0xbdf88b3, (q31_t)0xdade2d28, + (q31_t)0xbd83f3d, (q31_t)0xdae86a0d, (q31_t)0xbd0f7ca, (q31_t)0xdaf2a860, + (q31_t)0xbc9b25a, (q31_t)0xdafce821, (q31_t)0xbc26eee, (q31_t)0xdb072950, + (q31_t)0xbbb2d85, (q31_t)0xdb116beb, (q31_t)0xbb3ee20, (q31_t)0xdb1baff2, + (q31_t)0xbacb0bf, (q31_t)0xdb25f566, (q31_t)0xba57563, (q31_t)0xdb303c46, + (q31_t)0xb9e3c0b, (q31_t)0xdb3a8491, (q31_t)0xb9704b9, (q31_t)0xdb44ce46, + (q31_t)0xb8fcf6b, (q31_t)0xdb4f1967, (q31_t)0xb889c23, (q31_t)0xdb5965f1, + (q31_t)0xb816ae1, (q31_t)0xdb63b3e5, (q31_t)0xb7a3ba5, (q31_t)0xdb6e0342, + (q31_t)0xb730e70, (q31_t)0xdb785409, (q31_t)0xb6be341, (q31_t)0xdb82a638, + (q31_t)0xb64ba19, (q31_t)0xdb8cf9cf, (q31_t)0xb5d92f8, (q31_t)0xdb974ece, + (q31_t)0xb566ddf, (q31_t)0xdba1a534, (q31_t)0xb4f4acd, (q31_t)0xdbabfd01, + (q31_t)0xb4829c4, (q31_t)0xdbb65634, (q31_t)0xb410ac3, (q31_t)0xdbc0b0ce, + (q31_t)0xb39edca, (q31_t)0xdbcb0cce, (q31_t)0xb32d2da, (q31_t)0xdbd56a32, + (q31_t)0xb2bb9f4, (q31_t)0xdbdfc8fc, (q31_t)0xb24a316, (q31_t)0xdbea292b, + (q31_t)0xb1d8e43, (q31_t)0xdbf48abd, (q31_t)0xb167b79, (q31_t)0xdbfeedb3, + (q31_t)0xb0f6aba, (q31_t)0xdc09520d, (q31_t)0xb085c05, (q31_t)0xdc13b7c9, + (q31_t)0xb014f5b, (q31_t)0xdc1e1ee9, (q31_t)0xafa44bc, (q31_t)0xdc28876a, + (q31_t)0xaf33c28, (q31_t)0xdc32f14d, (q31_t)0xaec35a0, (q31_t)0xdc3d5c91, + (q31_t)0xae53123, (q31_t)0xdc47c936, (q31_t)0xade2eb3, (q31_t)0xdc52373c, + (q31_t)0xad72e4f, (q31_t)0xdc5ca6a2, (q31_t)0xad02ff8, (q31_t)0xdc671768, + (q31_t)0xac933ae, (q31_t)0xdc71898d, (q31_t)0xac23971, (q31_t)0xdc7bfd11, + (q31_t)0xabb4141, (q31_t)0xdc8671f3, (q31_t)0xab44b1f, (q31_t)0xdc90e834, + (q31_t)0xaad570c, (q31_t)0xdc9b5fd2, (q31_t)0xaa66506, (q31_t)0xdca5d8cd, + (q31_t)0xa9f750f, (q31_t)0xdcb05326, (q31_t)0xa988727, (q31_t)0xdcbacedb, + (q31_t)0xa919b4e, (q31_t)0xdcc54bec, (q31_t)0xa8ab184, (q31_t)0xdccfca59, + (q31_t)0xa83c9ca, (q31_t)0xdcda4a21, (q31_t)0xa7ce420, (q31_t)0xdce4cb44, + (q31_t)0xa760086, (q31_t)0xdcef4dc2, (q31_t)0xa6f1efc, (q31_t)0xdcf9d199, + (q31_t)0xa683f83, (q31_t)0xdd0456ca, (q31_t)0xa61621b, (q31_t)0xdd0edd55, + (q31_t)0xa5a86c4, (q31_t)0xdd196538, (q31_t)0xa53ad7e, (q31_t)0xdd23ee74, + (q31_t)0xa4cd64b, (q31_t)0xdd2e7908, (q31_t)0xa460129, (q31_t)0xdd3904f4, + (q31_t)0xa3f2e19, (q31_t)0xdd439236, (q31_t)0xa385d1d, (q31_t)0xdd4e20d0, + (q31_t)0xa318e32, (q31_t)0xdd58b0c0, (q31_t)0xa2ac15b, (q31_t)0xdd634206, + (q31_t)0xa23f698, (q31_t)0xdd6dd4a2, (q31_t)0xa1d2de7, (q31_t)0xdd786892, + (q31_t)0xa16674b, (q31_t)0xdd82fdd8, (q31_t)0xa0fa2c3, (q31_t)0xdd8d9472, + (q31_t)0xa08e04f, (q31_t)0xdd982c60, (q31_t)0xa021fef, (q31_t)0xdda2c5a2, + (q31_t)0x9fb61a5, (q31_t)0xddad6036, (q31_t)0x9f4a570, (q31_t)0xddb7fc1e, + (q31_t)0x9edeb50, (q31_t)0xddc29958, (q31_t)0x9e73346, (q31_t)0xddcd37e4, + (q31_t)0x9e07d51, (q31_t)0xddd7d7c1, (q31_t)0x9d9c973, (q31_t)0xdde278ef, + (q31_t)0x9d317ab, (q31_t)0xdded1b6e, (q31_t)0x9cc67fa, (q31_t)0xddf7bf3e, + (q31_t)0x9c5ba60, (q31_t)0xde02645d, (q31_t)0x9bf0edd, (q31_t)0xde0d0acc, + (q31_t)0x9b86572, (q31_t)0xde17b28a, (q31_t)0x9b1be1e, (q31_t)0xde225b96, + (q31_t)0x9ab18e3, (q31_t)0xde2d05f1, (q31_t)0x9a475bf, (q31_t)0xde37b199, + (q31_t)0x99dd4b4, (q31_t)0xde425e8f, (q31_t)0x99735c2, (q31_t)0xde4d0cd2, + (q31_t)0x99098e9, (q31_t)0xde57bc62, (q31_t)0x989fe29, (q31_t)0xde626d3e, + (q31_t)0x9836582, (q31_t)0xde6d1f65, (q31_t)0x97ccef5, (q31_t)0xde77d2d8, + (q31_t)0x9763a83, (q31_t)0xde828796, (q31_t)0x96fa82a, (q31_t)0xde8d3d9e, + (q31_t)0x96917ec, (q31_t)0xde97f4f1, (q31_t)0x96289c9, (q31_t)0xdea2ad8d, + (q31_t)0x95bfdc1, (q31_t)0xdead6773, (q31_t)0x95573d4, (q31_t)0xdeb822a1, + (q31_t)0x94eec03, (q31_t)0xdec2df18, (q31_t)0x948664d, (q31_t)0xdecd9cd7, + (q31_t)0x941e2b4, (q31_t)0xded85bdd, (q31_t)0x93b6137, (q31_t)0xdee31c2b, + (q31_t)0x934e1d6, (q31_t)0xdeedddc0, (q31_t)0x92e6492, (q31_t)0xdef8a09b, + (q31_t)0x927e96b, (q31_t)0xdf0364bc, (q31_t)0x9217062, (q31_t)0xdf0e2a22, + (q31_t)0x91af976, (q31_t)0xdf18f0ce, (q31_t)0x91484a8, (q31_t)0xdf23b8be, + (q31_t)0x90e11f7, (q31_t)0xdf2e81f3, (q31_t)0x907a166, (q31_t)0xdf394c6b, + (q31_t)0x90132f2, (q31_t)0xdf441828, (q31_t)0x8fac69e, (q31_t)0xdf4ee527, + (q31_t)0x8f45c68, (q31_t)0xdf59b369, (q31_t)0x8edf452, (q31_t)0xdf6482ed, + (q31_t)0x8e78e5b, (q31_t)0xdf6f53b3, (q31_t)0x8e12a84, (q31_t)0xdf7a25ba, + (q31_t)0x8dac8cd, (q31_t)0xdf84f902, (q31_t)0x8d46936, (q31_t)0xdf8fcd8b, + (q31_t)0x8ce0bc0, (q31_t)0xdf9aa354, (q31_t)0x8c7b06b, (q31_t)0xdfa57a5d, + (q31_t)0x8c15736, (q31_t)0xdfb052a5, (q31_t)0x8bb0023, (q31_t)0xdfbb2c2c, + (q31_t)0x8b4ab32, (q31_t)0xdfc606f1, (q31_t)0x8ae5862, (q31_t)0xdfd0e2f5, + (q31_t)0x8a807b4, (q31_t)0xdfdbc036, (q31_t)0x8a1b928, (q31_t)0xdfe69eb4, + (q31_t)0x89b6cbf, (q31_t)0xdff17e70, (q31_t)0x8952278, (q31_t)0xdffc5f67, + (q31_t)0x88eda54, (q31_t)0xe007419b, (q31_t)0x8889454, (q31_t)0xe012250a, + (q31_t)0x8825077, (q31_t)0xe01d09b4, (q31_t)0x87c0ebd, (q31_t)0xe027ef99, + (q31_t)0x875cf28, (q31_t)0xe032d6b8, (q31_t)0x86f91b7, (q31_t)0xe03dbf11, + (q31_t)0x869566a, (q31_t)0xe048a8a4, (q31_t)0x8631d42, (q31_t)0xe053936f, + (q31_t)0x85ce63e, (q31_t)0xe05e7f74, (q31_t)0x856b160, (q31_t)0xe0696cb0, + (q31_t)0x8507ea7, (q31_t)0xe0745b24, (q31_t)0x84a4e14, (q31_t)0xe07f4acf, + (q31_t)0x8441fa6, (q31_t)0xe08a3bb2, (q31_t)0x83df35f, (q31_t)0xe0952dcb, + (q31_t)0x837c93e, (q31_t)0xe0a0211a, (q31_t)0x831a143, (q31_t)0xe0ab159e, + (q31_t)0x82b7b70, (q31_t)0xe0b60b58, (q31_t)0x82557c3, (q31_t)0xe0c10247, + (q31_t)0x81f363d, (q31_t)0xe0cbfa6a, (q31_t)0x81916df, (q31_t)0xe0d6f3c1, + (q31_t)0x812f9a9, (q31_t)0xe0e1ee4b, (q31_t)0x80cde9b, (q31_t)0xe0ecea09, + (q31_t)0x806c5b5, (q31_t)0xe0f7e6f9, (q31_t)0x800aef7, (q31_t)0xe102e51c, + (q31_t)0x7fa9a62, (q31_t)0xe10de470, (q31_t)0x7f487f6, (q31_t)0xe118e4f6, + (q31_t)0x7ee77b3, (q31_t)0xe123e6ad, (q31_t)0x7e8699a, (q31_t)0xe12ee995, + (q31_t)0x7e25daa, (q31_t)0xe139edac, (q31_t)0x7dc53e3, (q31_t)0xe144f2f3, + (q31_t)0x7d64c47, (q31_t)0xe14ff96a, (q31_t)0x7d046d6, (q31_t)0xe15b0110, + (q31_t)0x7ca438f, (q31_t)0xe16609e3, (q31_t)0x7c44272, (q31_t)0xe17113e5, + (q31_t)0x7be4381, (q31_t)0xe17c1f15, (q31_t)0x7b846ba, (q31_t)0xe1872b72, + (q31_t)0x7b24c20, (q31_t)0xe19238fb, (q31_t)0x7ac53b1, (q31_t)0xe19d47b1, + (q31_t)0x7a65d6e, (q31_t)0xe1a85793, (q31_t)0x7a06957, (q31_t)0xe1b368a0, + (q31_t)0x79a776c, (q31_t)0xe1be7ad8, (q31_t)0x79487ae, (q31_t)0xe1c98e3b, + (q31_t)0x78e9a1d, (q31_t)0xe1d4a2c8, (q31_t)0x788aeb9, (q31_t)0xe1dfb87f, + (q31_t)0x782c582, (q31_t)0xe1eacf5f, (q31_t)0x77cde79, (q31_t)0xe1f5e768, + (q31_t)0x776f99d, (q31_t)0xe2010099, (q31_t)0x77116f0, (q31_t)0xe20c1af3, + (q31_t)0x76b3671, (q31_t)0xe2173674, (q31_t)0x7655820, (q31_t)0xe222531c, + (q31_t)0x75f7bfe, (q31_t)0xe22d70eb, (q31_t)0x759a20a, (q31_t)0xe2388fe1, + (q31_t)0x753ca46, (q31_t)0xe243affc, (q31_t)0x74df4b1, (q31_t)0xe24ed13d, + (q31_t)0x748214c, (q31_t)0xe259f3a3, (q31_t)0x7425016, (q31_t)0xe265172e, + (q31_t)0x73c8111, (q31_t)0xe2703bdc, (q31_t)0x736b43c, (q31_t)0xe27b61af, + (q31_t)0x730e997, (q31_t)0xe28688a4, (q31_t)0x72b2123, (q31_t)0xe291b0bd, + (q31_t)0x7255ae0, (q31_t)0xe29cd9f8, (q31_t)0x71f96ce, (q31_t)0xe2a80456, + (q31_t)0x719d4ed, (q31_t)0xe2b32fd4, (q31_t)0x714153e, (q31_t)0xe2be5c74, + (q31_t)0x70e57c0, (q31_t)0xe2c98a35, (q31_t)0x7089c75, (q31_t)0xe2d4b916, + (q31_t)0x702e35c, (q31_t)0xe2dfe917, (q31_t)0x6fd2c75, (q31_t)0xe2eb1a37, + (q31_t)0x6f777c1, (q31_t)0xe2f64c77, (q31_t)0x6f1c540, (q31_t)0xe3017fd5, + (q31_t)0x6ec14f2, (q31_t)0xe30cb451, (q31_t)0x6e666d7, (q31_t)0xe317e9eb, + (q31_t)0x6e0baf0, (q31_t)0xe32320a2, (q31_t)0x6db113d, (q31_t)0xe32e5876, + (q31_t)0x6d569be, (q31_t)0xe3399167, (q31_t)0x6cfc472, (q31_t)0xe344cb73, + (q31_t)0x6ca215c, (q31_t)0xe350069b, (q31_t)0x6c4807a, (q31_t)0xe35b42df, + (q31_t)0x6bee1cd, (q31_t)0xe366803c, (q31_t)0x6b94554, (q31_t)0xe371beb5, + (q31_t)0x6b3ab12, (q31_t)0xe37cfe47, (q31_t)0x6ae1304, (q31_t)0xe3883ef2, + (q31_t)0x6a87d2d, (q31_t)0xe39380b6, (q31_t)0x6a2e98b, (q31_t)0xe39ec393, + (q31_t)0x69d5820, (q31_t)0xe3aa0788, (q31_t)0x697c8eb, (q31_t)0xe3b54c95, + (q31_t)0x6923bec, (q31_t)0xe3c092b9, (q31_t)0x68cb124, (q31_t)0xe3cbd9f4, + (q31_t)0x6872894, (q31_t)0xe3d72245, (q31_t)0x681a23a, (q31_t)0xe3e26bac, + (q31_t)0x67c1e18, (q31_t)0xe3edb628, (q31_t)0x6769c2e, (q31_t)0xe3f901ba, + (q31_t)0x6711c7b, (q31_t)0xe4044e60, (q31_t)0x66b9f01, (q31_t)0xe40f9c1a, + (q31_t)0x66623be, (q31_t)0xe41aeae8, (q31_t)0x660aab5, (q31_t)0xe4263ac9, + (q31_t)0x65b33e4, (q31_t)0xe4318bbe, (q31_t)0x655bf4c, (q31_t)0xe43cddc4, + (q31_t)0x6504ced, (q31_t)0xe44830dd, (q31_t)0x64adcc7, (q31_t)0xe4538507, + (q31_t)0x6456edb, (q31_t)0xe45eda43, (q31_t)0x6400329, (q31_t)0xe46a308f, + (q31_t)0x63a99b1, (q31_t)0xe47587eb, (q31_t)0x6353273, (q31_t)0xe480e057, + (q31_t)0x62fcd6f, (q31_t)0xe48c39d3, (q31_t)0x62a6aa6, (q31_t)0xe497945d, + (q31_t)0x6250a18, (q31_t)0xe4a2eff6, (q31_t)0x61fabc4, (q31_t)0xe4ae4c9d, + (q31_t)0x61a4fac, (q31_t)0xe4b9aa52, (q31_t)0x614f5cf, (q31_t)0xe4c50914, + (q31_t)0x60f9e2e, (q31_t)0xe4d068e2, (q31_t)0x60a48c9, (q31_t)0xe4dbc9bd, + (q31_t)0x604f5a0, (q31_t)0xe4e72ba4, (q31_t)0x5ffa4b3, (q31_t)0xe4f28e96, + (q31_t)0x5fa5603, (q31_t)0xe4fdf294, (q31_t)0x5f5098f, (q31_t)0xe509579b, + (q31_t)0x5efbf58, (q31_t)0xe514bdad, (q31_t)0x5ea775e, (q31_t)0xe52024c9, + (q31_t)0x5e531a1, (q31_t)0xe52b8cee, (q31_t)0x5dfee22, (q31_t)0xe536f61b, + (q31_t)0x5daace1, (q31_t)0xe5426051, (q31_t)0x5d56ddd, (q31_t)0xe54dcb8f, + (q31_t)0x5d03118, (q31_t)0xe55937d5, (q31_t)0x5caf690, (q31_t)0xe564a521, + (q31_t)0x5c5be47, (q31_t)0xe5701374, (q31_t)0x5c0883d, (q31_t)0xe57b82cd, + (q31_t)0x5bb5472, (q31_t)0xe586f32c, (q31_t)0x5b622e6, (q31_t)0xe5926490, + (q31_t)0x5b0f399, (q31_t)0xe59dd6f9, (q31_t)0x5abc68c, (q31_t)0xe5a94a67, + (q31_t)0x5a69bbe, (q31_t)0xe5b4bed8, (q31_t)0x5a17330, (q31_t)0xe5c0344d, + (q31_t)0x59c4ce3, (q31_t)0xe5cbaac5, (q31_t)0x59728d5, (q31_t)0xe5d72240, + (q31_t)0x5920708, (q31_t)0xe5e29abc, (q31_t)0x58ce77c, (q31_t)0xe5ee143b, + (q31_t)0x587ca31, (q31_t)0xe5f98ebb, (q31_t)0x582af26, (q31_t)0xe6050a3b, + (q31_t)0x57d965d, (q31_t)0xe61086bc, (q31_t)0x5787fd6, (q31_t)0xe61c043d, + (q31_t)0x5736b90, (q31_t)0xe62782be, (q31_t)0x56e598c, (q31_t)0xe633023e, + (q31_t)0x56949ca, (q31_t)0xe63e82bc, (q31_t)0x5643c4a, (q31_t)0xe64a0438, + (q31_t)0x55f310d, (q31_t)0xe65586b3, (q31_t)0x55a2812, (q31_t)0xe6610a2a, + (q31_t)0x555215a, (q31_t)0xe66c8e9f, (q31_t)0x5501ce5, (q31_t)0xe6781410, + (q31_t)0x54b1ab4, (q31_t)0xe6839a7c, (q31_t)0x5461ac6, (q31_t)0xe68f21e5, + (q31_t)0x5411d1b, (q31_t)0xe69aaa48, (q31_t)0x53c21b4, (q31_t)0xe6a633a6, + (q31_t)0x5372891, (q31_t)0xe6b1bdff, (q31_t)0x53231b3, (q31_t)0xe6bd4951, + (q31_t)0x52d3d18, (q31_t)0xe6c8d59c, (q31_t)0x5284ac3, (q31_t)0xe6d462e1, + (q31_t)0x5235ab2, (q31_t)0xe6dff11d, (q31_t)0x51e6ce6, (q31_t)0xe6eb8052, + (q31_t)0x519815f, (q31_t)0xe6f7107e, (q31_t)0x514981d, (q31_t)0xe702a1a1, + (q31_t)0x50fb121, (q31_t)0xe70e33bb, (q31_t)0x50acc6b, (q31_t)0xe719c6cb, + (q31_t)0x505e9fb, (q31_t)0xe7255ad1, (q31_t)0x50109d0, (q31_t)0xe730efcc, + (q31_t)0x4fc2bec, (q31_t)0xe73c85bc, (q31_t)0x4f7504e, (q31_t)0xe7481ca1, + (q31_t)0x4f276f7, (q31_t)0xe753b479, (q31_t)0x4ed9fe7, (q31_t)0xe75f4d45, + (q31_t)0x4e8cb1e, (q31_t)0xe76ae704, (q31_t)0x4e3f89c, (q31_t)0xe77681b6, + (q31_t)0x4df2862, (q31_t)0xe7821d59, (q31_t)0x4da5a6f, (q31_t)0xe78db9ef, + (q31_t)0x4d58ec3, (q31_t)0xe7995776, (q31_t)0x4d0c560, (q31_t)0xe7a4f5ed, + (q31_t)0x4cbfe45, (q31_t)0xe7b09555, (q31_t)0x4c73972, (q31_t)0xe7bc35ad, + (q31_t)0x4c276e8, (q31_t)0xe7c7d6f4, (q31_t)0x4bdb6a6, (q31_t)0xe7d3792b, + (q31_t)0x4b8f8ad, (q31_t)0xe7df1c50, (q31_t)0x4b43cfd, (q31_t)0xe7eac063, + (q31_t)0x4af8397, (q31_t)0xe7f66564, (q31_t)0x4aacc7a, (q31_t)0xe8020b52, + (q31_t)0x4a617a6, (q31_t)0xe80db22d, (q31_t)0x4a1651c, (q31_t)0xe81959f4, + (q31_t)0x49cb4dd, (q31_t)0xe82502a7, (q31_t)0x49806e7, (q31_t)0xe830ac45, + (q31_t)0x4935b3c, (q31_t)0xe83c56cf, (q31_t)0x48eb1db, (q31_t)0xe8480243, + (q31_t)0x48a0ac4, (q31_t)0xe853aea1, (q31_t)0x48565f9, (q31_t)0xe85f5be9, + (q31_t)0x480c379, (q31_t)0xe86b0a1a, (q31_t)0x47c2344, (q31_t)0xe876b934, + (q31_t)0x477855a, (q31_t)0xe8826936, (q31_t)0x472e9bc, (q31_t)0xe88e1a20, + (q31_t)0x46e5069, (q31_t)0xe899cbf1, (q31_t)0x469b963, (q31_t)0xe8a57ea9, + (q31_t)0x46524a9, (q31_t)0xe8b13248, (q31_t)0x460923b, (q31_t)0xe8bce6cd, + (q31_t)0x45c0219, (q31_t)0xe8c89c37, (q31_t)0x4577444, (q31_t)0xe8d45286, + (q31_t)0x452e8bc, (q31_t)0xe8e009ba, (q31_t)0x44e5f80, (q31_t)0xe8ebc1d3, + (q31_t)0x449d892, (q31_t)0xe8f77acf, (q31_t)0x44553f2, (q31_t)0xe90334af, + (q31_t)0x440d19e, (q31_t)0xe90eef71, (q31_t)0x43c5199, (q31_t)0xe91aab16, + (q31_t)0x437d3e1, (q31_t)0xe926679c, (q31_t)0x4335877, (q31_t)0xe9322505, + (q31_t)0x42edf5c, (q31_t)0xe93de34e, (q31_t)0x42a688f, (q31_t)0xe949a278, + (q31_t)0x425f410, (q31_t)0xe9556282, (q31_t)0x42181e0, (q31_t)0xe961236c, + (q31_t)0x41d11ff, (q31_t)0xe96ce535, (q31_t)0x418a46d, (q31_t)0xe978a7dd, + (q31_t)0x414392b, (q31_t)0xe9846b63, (q31_t)0x40fd037, (q31_t)0xe9902fc7, + (q31_t)0x40b6994, (q31_t)0xe99bf509, (q31_t)0x4070540, (q31_t)0xe9a7bb28, + (q31_t)0x402a33c, (q31_t)0xe9b38223, (q31_t)0x3fe4388, (q31_t)0xe9bf49fa, + (q31_t)0x3f9e624, (q31_t)0xe9cb12ad, (q31_t)0x3f58b10, (q31_t)0xe9d6dc3b, + (q31_t)0x3f1324e, (q31_t)0xe9e2a6a3, (q31_t)0x3ecdbdc, (q31_t)0xe9ee71e6, + (q31_t)0x3e887bb, (q31_t)0xe9fa3e03, (q31_t)0x3e435ea, (q31_t)0xea060af9, + (q31_t)0x3dfe66c, (q31_t)0xea11d8c8, (q31_t)0x3db993e, (q31_t)0xea1da770, + (q31_t)0x3d74e62, (q31_t)0xea2976ef, (q31_t)0x3d305d8, (q31_t)0xea354746, + (q31_t)0x3cebfa0, (q31_t)0xea411874, (q31_t)0x3ca7bba, (q31_t)0xea4cea79, + (q31_t)0x3c63a26, (q31_t)0xea58bd54, (q31_t)0x3c1fae5, (q31_t)0xea649105, + (q31_t)0x3bdbdf6, (q31_t)0xea70658a, (q31_t)0x3b9835a, (q31_t)0xea7c3ae5, + (q31_t)0x3b54b11, (q31_t)0xea881114, (q31_t)0x3b1151b, (q31_t)0xea93e817, + (q31_t)0x3ace178, (q31_t)0xea9fbfed, (q31_t)0x3a8b028, (q31_t)0xeaab9896, + (q31_t)0x3a4812c, (q31_t)0xeab77212, (q31_t)0x3a05484, (q31_t)0xeac34c60, + (q31_t)0x39c2a2f, (q31_t)0xeacf277f, (q31_t)0x398022f, (q31_t)0xeadb0370, + (q31_t)0x393dc82, (q31_t)0xeae6e031, (q31_t)0x38fb92a, (q31_t)0xeaf2bdc3, + (q31_t)0x38b9827, (q31_t)0xeafe9c24, (q31_t)0x3877978, (q31_t)0xeb0a7b54, + (q31_t)0x3835d1e, (q31_t)0xeb165b54, (q31_t)0x37f4319, (q31_t)0xeb223c22, + (q31_t)0x37b2b6a, (q31_t)0xeb2e1dbe, (q31_t)0x377160f, (q31_t)0xeb3a0027, + (q31_t)0x373030a, (q31_t)0xeb45e35d, (q31_t)0x36ef25b, (q31_t)0xeb51c760, + (q31_t)0x36ae401, (q31_t)0xeb5dac2f, (q31_t)0x366d7fd, (q31_t)0xeb6991ca, + (q31_t)0x362ce50, (q31_t)0xeb75782f, (q31_t)0x35ec6f8, (q31_t)0xeb815f60, + (q31_t)0x35ac1f7, (q31_t)0xeb8d475b, (q31_t)0x356bf4d, (q31_t)0xeb99301f, + (q31_t)0x352bef9, (q31_t)0xeba519ad, (q31_t)0x34ec0fc, (q31_t)0xebb10404, + (q31_t)0x34ac556, (q31_t)0xebbcef23, (q31_t)0x346cc07, (q31_t)0xebc8db0b, + (q31_t)0x342d510, (q31_t)0xebd4c7ba, (q31_t)0x33ee070, (q31_t)0xebe0b52f, + (q31_t)0x33aee27, (q31_t)0xebeca36c, (q31_t)0x336fe37, (q31_t)0xebf8926f, + (q31_t)0x333109e, (q31_t)0xec048237, (q31_t)0x32f255e, (q31_t)0xec1072c4, + (q31_t)0x32b3c75, (q31_t)0xec1c6417, (q31_t)0x32755e5, (q31_t)0xec28562d, + (q31_t)0x32371ae, (q31_t)0xec344908, (q31_t)0x31f8fcf, (q31_t)0xec403ca5, + (q31_t)0x31bb049, (q31_t)0xec4c3106, (q31_t)0x317d31c, (q31_t)0xec582629, + (q31_t)0x313f848, (q31_t)0xec641c0e, (q31_t)0x3101fce, (q31_t)0xec7012b5, + (q31_t)0x30c49ad, (q31_t)0xec7c0a1d, (q31_t)0x30875e5, (q31_t)0xec880245, + (q31_t)0x304a477, (q31_t)0xec93fb2e, (q31_t)0x300d563, (q31_t)0xec9ff4d6, + (q31_t)0x2fd08a9, (q31_t)0xecabef3d, (q31_t)0x2f93e4a, (q31_t)0xecb7ea63, + (q31_t)0x2f57644, (q31_t)0xecc3e648, (q31_t)0x2f1b099, (q31_t)0xeccfe2ea, + (q31_t)0x2eded49, (q31_t)0xecdbe04a, (q31_t)0x2ea2c53, (q31_t)0xece7de66, + (q31_t)0x2e66db8, (q31_t)0xecf3dd3f, (q31_t)0x2e2b178, (q31_t)0xecffdcd4, + (q31_t)0x2def794, (q31_t)0xed0bdd25, (q31_t)0x2db400a, (q31_t)0xed17de31, + (q31_t)0x2d78add, (q31_t)0xed23dff7, (q31_t)0x2d3d80a, (q31_t)0xed2fe277, + (q31_t)0x2d02794, (q31_t)0xed3be5b1, (q31_t)0x2cc7979, (q31_t)0xed47e9a5, + (q31_t)0x2c8cdbb, (q31_t)0xed53ee51, (q31_t)0x2c52459, (q31_t)0xed5ff3b5, + (q31_t)0x2c17d52, (q31_t)0xed6bf9d1, (q31_t)0x2bdd8a9, (q31_t)0xed7800a5, + (q31_t)0x2ba365c, (q31_t)0xed84082f, (q31_t)0x2b6966c, (q31_t)0xed901070, + (q31_t)0x2b2f8d8, (q31_t)0xed9c1967, (q31_t)0x2af5da2, (q31_t)0xeda82313, + (q31_t)0x2abc4c9, (q31_t)0xedb42d74, (q31_t)0x2a82e4d, (q31_t)0xedc0388a, + (q31_t)0x2a49a2e, (q31_t)0xedcc4454, (q31_t)0x2a1086d, (q31_t)0xedd850d2, + (q31_t)0x29d790a, (q31_t)0xede45e03, (q31_t)0x299ec05, (q31_t)0xedf06be6, + (q31_t)0x296615d, (q31_t)0xedfc7a7c, (q31_t)0x292d914, (q31_t)0xee0889c4, + (q31_t)0x28f5329, (q31_t)0xee1499bd, (q31_t)0x28bcf9c, (q31_t)0xee20aa67, + (q31_t)0x2884e6e, (q31_t)0xee2cbbc1, (q31_t)0x284cf9f, (q31_t)0xee38cdcb, + (q31_t)0x281532e, (q31_t)0xee44e084, (q31_t)0x27dd91c, (q31_t)0xee50f3ed, + (q31_t)0x27a616a, (q31_t)0xee5d0804, (q31_t)0x276ec16, (q31_t)0xee691cc9, + (q31_t)0x2737922, (q31_t)0xee75323c, (q31_t)0x270088e, (q31_t)0xee81485c, + (q31_t)0x26c9a58, (q31_t)0xee8d5f29, (q31_t)0x2692e83, (q31_t)0xee9976a1, + (q31_t)0x265c50e, (q31_t)0xeea58ec6, (q31_t)0x2625df8, (q31_t)0xeeb1a796, + (q31_t)0x25ef943, (q31_t)0xeebdc110, (q31_t)0x25b96ee, (q31_t)0xeec9db35, + (q31_t)0x25836f9, (q31_t)0xeed5f604, (q31_t)0x254d965, (q31_t)0xeee2117c, + (q31_t)0x2517e31, (q31_t)0xeeee2d9d, (q31_t)0x24e255e, (q31_t)0xeefa4a67, + (q31_t)0x24aceed, (q31_t)0xef0667d9, (q31_t)0x2477adc, (q31_t)0xef1285f2, + (q31_t)0x244292c, (q31_t)0xef1ea4b2, (q31_t)0x240d9de, (q31_t)0xef2ac419, + (q31_t)0x23d8cf1, (q31_t)0xef36e426, (q31_t)0x23a4265, (q31_t)0xef4304d8, + (q31_t)0x236fa3b, (q31_t)0xef4f2630, (q31_t)0x233b473, (q31_t)0xef5b482d, + (q31_t)0x230710d, (q31_t)0xef676ace, (q31_t)0x22d3009, (q31_t)0xef738e12, + (q31_t)0x229f167, (q31_t)0xef7fb1fa, (q31_t)0x226b528, (q31_t)0xef8bd685, + (q31_t)0x2237b4b, (q31_t)0xef97fbb2, (q31_t)0x22043d0, (q31_t)0xefa42181, + (q31_t)0x21d0eb8, (q31_t)0xefb047f2, (q31_t)0x219dc03, (q31_t)0xefbc6f03, + (q31_t)0x216abb1, (q31_t)0xefc896b5, (q31_t)0x2137dc2, (q31_t)0xefd4bf08, + (q31_t)0x2105236, (q31_t)0xefe0e7f9, (q31_t)0x20d290d, (q31_t)0xefed118a, + (q31_t)0x20a0248, (q31_t)0xeff93bba, (q31_t)0x206dde6, (q31_t)0xf0056687, + (q31_t)0x203bbe8, (q31_t)0xf01191f3, (q31_t)0x2009c4e, (q31_t)0xf01dbdfb, + (q31_t)0x1fd7f17, (q31_t)0xf029eaa1, (q31_t)0x1fa6445, (q31_t)0xf03617e2, + (q31_t)0x1f74bd6, (q31_t)0xf04245c0, (q31_t)0x1f435cc, (q31_t)0xf04e7438, + (q31_t)0x1f12227, (q31_t)0xf05aa34c, (q31_t)0x1ee10e5, (q31_t)0xf066d2fa, + (q31_t)0x1eb0209, (q31_t)0xf0730342, (q31_t)0x1e7f591, (q31_t)0xf07f3424, + (q31_t)0x1e4eb7e, (q31_t)0xf08b659f, (q31_t)0x1e1e3d0, (q31_t)0xf09797b2, + (q31_t)0x1dede87, (q31_t)0xf0a3ca5d, (q31_t)0x1dbdba3, (q31_t)0xf0affda0, + (q31_t)0x1d8db25, (q31_t)0xf0bc317a, (q31_t)0x1d5dd0c, (q31_t)0xf0c865ea, + (q31_t)0x1d2e158, (q31_t)0xf0d49af1, (q31_t)0x1cfe80a, (q31_t)0xf0e0d08d, + (q31_t)0x1ccf122, (q31_t)0xf0ed06bf, (q31_t)0x1c9fca0, (q31_t)0xf0f93d86, + (q31_t)0x1c70a84, (q31_t)0xf10574e0, (q31_t)0x1c41ace, (q31_t)0xf111accf, + (q31_t)0x1c12d7e, (q31_t)0xf11de551, (q31_t)0x1be4294, (q31_t)0xf12a1e66, + (q31_t)0x1bb5a11, (q31_t)0xf136580d, (q31_t)0x1b873f5, (q31_t)0xf1429247, + (q31_t)0x1b5903f, (q31_t)0xf14ecd11, (q31_t)0x1b2aef0, (q31_t)0xf15b086d, + (q31_t)0x1afd007, (q31_t)0xf1674459, (q31_t)0x1acf386, (q31_t)0xf17380d6, + (q31_t)0x1aa196c, (q31_t)0xf17fbde2, (q31_t)0x1a741b9, (q31_t)0xf18bfb7d, + (q31_t)0x1a46c6e, (q31_t)0xf19839a6, (q31_t)0x1a1998a, (q31_t)0xf1a4785e, + (q31_t)0x19ec90d, (q31_t)0xf1b0b7a4, (q31_t)0x19bfaf9, (q31_t)0xf1bcf777, + (q31_t)0x1992f4c, (q31_t)0xf1c937d6, (q31_t)0x1966606, (q31_t)0xf1d578c2, + (q31_t)0x1939f29, (q31_t)0xf1e1ba3a, (q31_t)0x190dab4, (q31_t)0xf1edfc3d, + (q31_t)0x18e18a7, (q31_t)0xf1fa3ecb, (q31_t)0x18b5903, (q31_t)0xf20681e3, + (q31_t)0x1889bc6, (q31_t)0xf212c585, (q31_t)0x185e0f3, (q31_t)0xf21f09b1, + (q31_t)0x1832888, (q31_t)0xf22b4e66, (q31_t)0x1807285, (q31_t)0xf23793a3, + (q31_t)0x17dbeec, (q31_t)0xf243d968, (q31_t)0x17b0dbb, (q31_t)0xf2501fb5, + (q31_t)0x1785ef4, (q31_t)0xf25c6688, (q31_t)0x175b296, (q31_t)0xf268ade3, + (q31_t)0x17308a1, (q31_t)0xf274f5c3, (q31_t)0x1706115, (q31_t)0xf2813e2a, + (q31_t)0x16dbbf3, (q31_t)0xf28d8715, (q31_t)0x16b193a, (q31_t)0xf299d085, + (q31_t)0x16878eb, (q31_t)0xf2a61a7a, (q31_t)0x165db05, (q31_t)0xf2b264f2, + (q31_t)0x1633f8a, (q31_t)0xf2beafed, (q31_t)0x160a678, (q31_t)0xf2cafb6b, + (q31_t)0x15e0fd1, (q31_t)0xf2d7476c, (q31_t)0x15b7b94, (q31_t)0xf2e393ef, + (q31_t)0x158e9c1, (q31_t)0xf2efe0f2, (q31_t)0x1565a58, (q31_t)0xf2fc2e77, + (q31_t)0x153cd5a, (q31_t)0xf3087c7d, (q31_t)0x15142c6, (q31_t)0xf314cb02, + (q31_t)0x14eba9d, (q31_t)0xf3211a07, (q31_t)0x14c34df, (q31_t)0xf32d698a, + (q31_t)0x149b18b, (q31_t)0xf339b98d, (q31_t)0x14730a3, (q31_t)0xf3460a0d, + (q31_t)0x144b225, (q31_t)0xf3525b0b, (q31_t)0x1423613, (q31_t)0xf35eac86, + (q31_t)0x13fbc6c, (q31_t)0xf36afe7e, (q31_t)0x13d4530, (q31_t)0xf37750f2, + (q31_t)0x13ad060, (q31_t)0xf383a3e2, (q31_t)0x1385dfb, (q31_t)0xf38ff74d, + (q31_t)0x135ee02, (q31_t)0xf39c4b32, (q31_t)0x1338075, (q31_t)0xf3a89f92, + (q31_t)0x1311553, (q31_t)0xf3b4f46c, (q31_t)0x12eac9d, (q31_t)0xf3c149bf, + (q31_t)0x12c4653, (q31_t)0xf3cd9f8b, (q31_t)0x129e276, (q31_t)0xf3d9f5cf, + (q31_t)0x1278104, (q31_t)0xf3e64c8c, (q31_t)0x12521ff, (q31_t)0xf3f2a3bf, + (q31_t)0x122c566, (q31_t)0xf3fefb6a, (q31_t)0x1206b39, (q31_t)0xf40b538b, + (q31_t)0x11e1379, (q31_t)0xf417ac22, (q31_t)0x11bbe26, (q31_t)0xf424052f, + (q31_t)0x1196b3f, (q31_t)0xf4305eb0, (q31_t)0x1171ac6, (q31_t)0xf43cb8a7, + (q31_t)0x114ccb9, (q31_t)0xf4491311, (q31_t)0x1128119, (q31_t)0xf4556def, + (q31_t)0x11037e6, (q31_t)0xf461c940, (q31_t)0x10df120, (q31_t)0xf46e2504, + (q31_t)0x10bacc8, (q31_t)0xf47a8139, (q31_t)0x1096add, (q31_t)0xf486dde1, + (q31_t)0x1072b5f, (q31_t)0xf4933afa, (q31_t)0x104ee4f, (q31_t)0xf49f9884, + (q31_t)0x102b3ac, (q31_t)0xf4abf67e, (q31_t)0x1007b77, (q31_t)0xf4b854e7, + (q31_t)0xfe45b0, (q31_t)0xf4c4b3c0, (q31_t)0xfc1257, (q31_t)0xf4d11308, + (q31_t)0xf9e16b, (q31_t)0xf4dd72be, (q31_t)0xf7b2ee, (q31_t)0xf4e9d2e3, + (q31_t)0xf586df, (q31_t)0xf4f63374, (q31_t)0xf35d3e, (q31_t)0xf5029473, + (q31_t)0xf1360b, (q31_t)0xf50ef5de, (q31_t)0xef1147, (q31_t)0xf51b57b5, + (q31_t)0xeceef1, (q31_t)0xf527b9f7, (q31_t)0xeacf09, (q31_t)0xf5341ca5, + (q31_t)0xe8b190, (q31_t)0xf5407fbd, (q31_t)0xe69686, (q31_t)0xf54ce33f, + (q31_t)0xe47deb, (q31_t)0xf559472b, (q31_t)0xe267be, (q31_t)0xf565ab80, + (q31_t)0xe05401, (q31_t)0xf572103d, (q31_t)0xde42b2, (q31_t)0xf57e7563, + (q31_t)0xdc33d2, (q31_t)0xf58adaf0, (q31_t)0xda2762, (q31_t)0xf59740e5, + (q31_t)0xd81d61, (q31_t)0xf5a3a740, (q31_t)0xd615cf, (q31_t)0xf5b00e02, + (q31_t)0xd410ad, (q31_t)0xf5bc7529, (q31_t)0xd20dfa, (q31_t)0xf5c8dcb6, + (q31_t)0xd00db6, (q31_t)0xf5d544a7, (q31_t)0xce0fe3, (q31_t)0xf5e1acfd, + (q31_t)0xcc147f, (q31_t)0xf5ee15b7, (q31_t)0xca1b8a, (q31_t)0xf5fa7ed4, + (q31_t)0xc82506, (q31_t)0xf606e854, (q31_t)0xc630f2, (q31_t)0xf6135237, + (q31_t)0xc43f4d, (q31_t)0xf61fbc7b, (q31_t)0xc25019, (q31_t)0xf62c2721, + (q31_t)0xc06355, (q31_t)0xf6389228, (q31_t)0xbe7901, (q31_t)0xf644fd8f, + (q31_t)0xbc911d, (q31_t)0xf6516956, (q31_t)0xbaabaa, (q31_t)0xf65dd57d, + (q31_t)0xb8c8a7, (q31_t)0xf66a4203, (q31_t)0xb6e815, (q31_t)0xf676aee8, + (q31_t)0xb509f3, (q31_t)0xf6831c2b, (q31_t)0xb32e42, (q31_t)0xf68f89cb, + (q31_t)0xb15502, (q31_t)0xf69bf7c9, (q31_t)0xaf7e33, (q31_t)0xf6a86623, + (q31_t)0xada9d4, (q31_t)0xf6b4d4d9, (q31_t)0xabd7e6, (q31_t)0xf6c143ec, + (q31_t)0xaa086a, (q31_t)0xf6cdb359, (q31_t)0xa83b5e, (q31_t)0xf6da2321, + (q31_t)0xa670c4, (q31_t)0xf6e69344, (q31_t)0xa4a89b, (q31_t)0xf6f303c0, + (q31_t)0xa2e2e3, (q31_t)0xf6ff7496, (q31_t)0xa11f9d, (q31_t)0xf70be5c4, + (q31_t)0x9f5ec8, (q31_t)0xf718574b, (q31_t)0x9da065, (q31_t)0xf724c92a, + (q31_t)0x9be473, (q31_t)0xf7313b60, (q31_t)0x9a2af3, (q31_t)0xf73daded, + (q31_t)0x9873e4, (q31_t)0xf74a20d0, (q31_t)0x96bf48, (q31_t)0xf756940a, + (q31_t)0x950d1d, (q31_t)0xf7630799, (q31_t)0x935d64, (q31_t)0xf76f7b7d, + (q31_t)0x91b01d, (q31_t)0xf77befb5, (q31_t)0x900548, (q31_t)0xf7886442, + (q31_t)0x8e5ce5, (q31_t)0xf794d922, (q31_t)0x8cb6f5, (q31_t)0xf7a14e55, + (q31_t)0x8b1376, (q31_t)0xf7adc3db, (q31_t)0x89726a, (q31_t)0xf7ba39b3, + (q31_t)0x87d3d0, (q31_t)0xf7c6afdc, (q31_t)0x8637a9, (q31_t)0xf7d32657, + (q31_t)0x849df4, (q31_t)0xf7df9d22, (q31_t)0x8306b2, (q31_t)0xf7ec143e, + (q31_t)0x8171e2, (q31_t)0xf7f88ba9, (q31_t)0x7fdf85, (q31_t)0xf8050364, + (q31_t)0x7e4f9b, (q31_t)0xf8117b6d, (q31_t)0x7cc223, (q31_t)0xf81df3c5, + (q31_t)0x7b371e, (q31_t)0xf82a6c6a, (q31_t)0x79ae8c, (q31_t)0xf836e55d, + (q31_t)0x78286e, (q31_t)0xf8435e9d, (q31_t)0x76a4c2, (q31_t)0xf84fd829, + (q31_t)0x752389, (q31_t)0xf85c5201, (q31_t)0x73a4c3, (q31_t)0xf868cc24, + (q31_t)0x722871, (q31_t)0xf8754692, (q31_t)0x70ae92, (q31_t)0xf881c14b, + (q31_t)0x6f3726, (q31_t)0xf88e3c4d, (q31_t)0x6dc22e, (q31_t)0xf89ab799, + (q31_t)0x6c4fa8, (q31_t)0xf8a7332e, (q31_t)0x6adf97, (q31_t)0xf8b3af0c, + (q31_t)0x6971f9, (q31_t)0xf8c02b31, (q31_t)0x6806ce, (q31_t)0xf8cca79e, + (q31_t)0x669e18, (q31_t)0xf8d92452, (q31_t)0x6537d4, (q31_t)0xf8e5a14d, + (q31_t)0x63d405, (q31_t)0xf8f21e8e, (q31_t)0x6272aa, (q31_t)0xf8fe9c15, + (q31_t)0x6113c2, (q31_t)0xf90b19e0, (q31_t)0x5fb74e, (q31_t)0xf91797f0, + (q31_t)0x5e5d4e, (q31_t)0xf9241645, (q31_t)0x5d05c3, (q31_t)0xf93094dd, + (q31_t)0x5bb0ab, (q31_t)0xf93d13b8, (q31_t)0x5a5e07, (q31_t)0xf94992d7, + (q31_t)0x590dd8, (q31_t)0xf9561237, (q31_t)0x57c01d, (q31_t)0xf96291d9, + (q31_t)0x5674d6, (q31_t)0xf96f11bc, (q31_t)0x552c03, (q31_t)0xf97b91e1, + (q31_t)0x53e5a5, (q31_t)0xf9881245, (q31_t)0x52a1bb, (q31_t)0xf99492ea, + (q31_t)0x516045, (q31_t)0xf9a113cd, (q31_t)0x502145, (q31_t)0xf9ad94f0, + (q31_t)0x4ee4b8, (q31_t)0xf9ba1651, (q31_t)0x4daaa1, (q31_t)0xf9c697f0, + (q31_t)0x4c72fe, (q31_t)0xf9d319cc, (q31_t)0x4b3dcf, (q31_t)0xf9df9be6, + (q31_t)0x4a0b16, (q31_t)0xf9ec1e3b, (q31_t)0x48dad1, (q31_t)0xf9f8a0cd, + (q31_t)0x47ad01, (q31_t)0xfa05239a, (q31_t)0x4681a6, (q31_t)0xfa11a6a3, + (q31_t)0x4558c0, (q31_t)0xfa1e29e5, (q31_t)0x44324f, (q31_t)0xfa2aad62, + (q31_t)0x430e53, (q31_t)0xfa373119, (q31_t)0x41eccc, (q31_t)0xfa43b508, + (q31_t)0x40cdba, (q31_t)0xfa503930, (q31_t)0x3fb11d, (q31_t)0xfa5cbd91, + (q31_t)0x3e96f6, (q31_t)0xfa694229, (q31_t)0x3d7f44, (q31_t)0xfa75c6f8, + (q31_t)0x3c6a07, (q31_t)0xfa824bfd, (q31_t)0x3b573f, (q31_t)0xfa8ed139, + (q31_t)0x3a46ed, (q31_t)0xfa9b56ab, (q31_t)0x393910, (q31_t)0xfaa7dc52, + (q31_t)0x382da8, (q31_t)0xfab4622d, (q31_t)0x3724b6, (q31_t)0xfac0e83d, + (q31_t)0x361e3a, (q31_t)0xfacd6e81, (q31_t)0x351a33, (q31_t)0xfad9f4f8, + (q31_t)0x3418a2, (q31_t)0xfae67ba2, (q31_t)0x331986, (q31_t)0xfaf3027e, + (q31_t)0x321ce0, (q31_t)0xfaff898c, (q31_t)0x3122b0, (q31_t)0xfb0c10cb, + (q31_t)0x302af5, (q31_t)0xfb18983b, (q31_t)0x2f35b1, (q31_t)0xfb251fdc, + (q31_t)0x2e42e2, (q31_t)0xfb31a7ac, (q31_t)0x2d5289, (q31_t)0xfb3e2fac, + (q31_t)0x2c64a6, (q31_t)0xfb4ab7db, (q31_t)0x2b7939, (q31_t)0xfb574039, + (q31_t)0x2a9042, (q31_t)0xfb63c8c4, (q31_t)0x29a9c1, (q31_t)0xfb70517d, + (q31_t)0x28c5b6, (q31_t)0xfb7cda63, (q31_t)0x27e421, (q31_t)0xfb896375, + (q31_t)0x270502, (q31_t)0xfb95ecb4, (q31_t)0x262859, (q31_t)0xfba2761e, + (q31_t)0x254e27, (q31_t)0xfbaeffb3, (q31_t)0x24766a, (q31_t)0xfbbb8973, + (q31_t)0x23a124, (q31_t)0xfbc8135c, (q31_t)0x22ce54, (q31_t)0xfbd49d70, + (q31_t)0x21fdfb, (q31_t)0xfbe127ac, (q31_t)0x213018, (q31_t)0xfbedb212, + (q31_t)0x2064ab, (q31_t)0xfbfa3c9f, (q31_t)0x1f9bb5, (q31_t)0xfc06c754, + (q31_t)0x1ed535, (q31_t)0xfc135231, (q31_t)0x1e112b, (q31_t)0xfc1fdd34, + (q31_t)0x1d4f99, (q31_t)0xfc2c685d, (q31_t)0x1c907c, (q31_t)0xfc38f3ac, + (q31_t)0x1bd3d6, (q31_t)0xfc457f21, (q31_t)0x1b19a7, (q31_t)0xfc520aba, + (q31_t)0x1a61ee, (q31_t)0xfc5e9678, (q31_t)0x19acac, (q31_t)0xfc6b2259, + (q31_t)0x18f9e1, (q31_t)0xfc77ae5e, (q31_t)0x18498c, (q31_t)0xfc843a85, + (q31_t)0x179bae, (q31_t)0xfc90c6cf, (q31_t)0x16f047, (q31_t)0xfc9d533b, + (q31_t)0x164757, (q31_t)0xfca9dfc8, (q31_t)0x15a0dd, (q31_t)0xfcb66c77, + (q31_t)0x14fcda, (q31_t)0xfcc2f945, (q31_t)0x145b4e, (q31_t)0xfccf8634, + (q31_t)0x13bc39, (q31_t)0xfcdc1342, (q31_t)0x131f9b, (q31_t)0xfce8a06f, + (q31_t)0x128574, (q31_t)0xfcf52dbb, (q31_t)0x11edc3, (q31_t)0xfd01bb24, + (q31_t)0x11588a, (q31_t)0xfd0e48ab, (q31_t)0x10c5c7, (q31_t)0xfd1ad650, + (q31_t)0x10357c, (q31_t)0xfd276410, (q31_t)0xfa7a8, (q31_t)0xfd33f1ed, + (q31_t)0xf1c4a, (q31_t)0xfd407fe6, (q31_t)0xe9364, (q31_t)0xfd4d0df9, + (q31_t)0xe0cf5, (q31_t)0xfd599c28, (q31_t)0xd88fd, (q31_t)0xfd662a70, + (q31_t)0xd077c, (q31_t)0xfd72b8d2, (q31_t)0xc8872, (q31_t)0xfd7f474d, + (q31_t)0xc0be0, (q31_t)0xfd8bd5e1, (q31_t)0xb91c4, (q31_t)0xfd98648d, + (q31_t)0xb1a20, (q31_t)0xfda4f351, (q31_t)0xaa4f3, (q31_t)0xfdb1822c, + (q31_t)0xa323d, (q31_t)0xfdbe111e, (q31_t)0x9c1ff, (q31_t)0xfdcaa027, + (q31_t)0x95438, (q31_t)0xfdd72f45, (q31_t)0x8e8e8, (q31_t)0xfde3be78, + (q31_t)0x8800f, (q31_t)0xfdf04dc0, (q31_t)0x819ae, (q31_t)0xfdfcdd1d, + (q31_t)0x7b5c4, (q31_t)0xfe096c8d, (q31_t)0x75452, (q31_t)0xfe15fc11, + (q31_t)0x6f556, (q31_t)0xfe228ba7, (q31_t)0x698d3, (q31_t)0xfe2f1b50, + (q31_t)0x63ec6, (q31_t)0xfe3bab0b, (q31_t)0x5e731, (q31_t)0xfe483ad8, + (q31_t)0x59214, (q31_t)0xfe54cab5, (q31_t)0x53f6e, (q31_t)0xfe615aa3, + (q31_t)0x4ef3f, (q31_t)0xfe6deaa1, (q31_t)0x4a188, (q31_t)0xfe7a7aae, + (q31_t)0x45648, (q31_t)0xfe870aca, (q31_t)0x40d80, (q31_t)0xfe939af5, + (q31_t)0x3c72f, (q31_t)0xfea02b2e, (q31_t)0x38356, (q31_t)0xfeacbb74, + (q31_t)0x341f4, (q31_t)0xfeb94bc8, (q31_t)0x3030a, (q31_t)0xfec5dc28, + (q31_t)0x2c697, (q31_t)0xfed26c94, (q31_t)0x28c9c, (q31_t)0xfedefd0c, + (q31_t)0x25519, (q31_t)0xfeeb8d8f, (q31_t)0x2200d, (q31_t)0xfef81e1d, + (q31_t)0x1ed78, (q31_t)0xff04aeb5, (q31_t)0x1bd5c, (q31_t)0xff113f56, + (q31_t)0x18fb6, (q31_t)0xff1dd001, (q31_t)0x16489, (q31_t)0xff2a60b4, + (q31_t)0x13bd3, (q31_t)0xff36f170, (q31_t)0x11594, (q31_t)0xff438234, + (q31_t)0xf1ce, (q31_t)0xff5012fe, (q31_t)0xd07e, (q31_t)0xff5ca3d0, + (q31_t)0xb1a7, (q31_t)0xff6934a8, (q31_t)0x9547, (q31_t)0xff75c585, + (q31_t)0x7b5f, (q31_t)0xff825668, (q31_t)0x63ee, (q31_t)0xff8ee750, + (q31_t)0x4ef5, (q31_t)0xff9b783c, (q31_t)0x3c74, (q31_t)0xffa8092c, + (q31_t)0x2c6a, (q31_t)0xffb49a1f, (q31_t)0x1ed8, (q31_t)0xffc12b16, + (q31_t)0x13bd, (q31_t)0xffcdbc0f, (q31_t)0xb1a, (q31_t)0xffda4d09, + (q31_t)0x4ef, (q31_t)0xffe6de05, (q31_t)0x13c, (q31_t)0xfff36f02, + (q31_t)0x0, (q31_t)0x0, (q31_t)0x13c, (q31_t)0xc90fe, + (q31_t)0x4ef, (q31_t)0x1921fb, (q31_t)0xb1a, (q31_t)0x25b2f7, + (q31_t)0x13bd, (q31_t)0x3243f1, (q31_t)0x1ed8, (q31_t)0x3ed4ea, + (q31_t)0x2c6a, (q31_t)0x4b65e1, (q31_t)0x3c74, (q31_t)0x57f6d4, + (q31_t)0x4ef5, (q31_t)0x6487c4, (q31_t)0x63ee, (q31_t)0x7118b0, + (q31_t)0x7b5f, (q31_t)0x7da998, (q31_t)0x9547, (q31_t)0x8a3a7b, + (q31_t)0xb1a7, (q31_t)0x96cb58, (q31_t)0xd07e, (q31_t)0xa35c30, + (q31_t)0xf1ce, (q31_t)0xafed02, (q31_t)0x11594, (q31_t)0xbc7dcc, + (q31_t)0x13bd3, (q31_t)0xc90e90, (q31_t)0x16489, (q31_t)0xd59f4c, + (q31_t)0x18fb6, (q31_t)0xe22fff, (q31_t)0x1bd5c, (q31_t)0xeec0aa, + (q31_t)0x1ed78, (q31_t)0xfb514b, (q31_t)0x2200d, (q31_t)0x107e1e3, + (q31_t)0x25519, (q31_t)0x1147271, (q31_t)0x28c9c, (q31_t)0x12102f4, + (q31_t)0x2c697, (q31_t)0x12d936c, (q31_t)0x3030a, (q31_t)0x13a23d8, + (q31_t)0x341f4, (q31_t)0x146b438, (q31_t)0x38356, (q31_t)0x153448c, + (q31_t)0x3c72f, (q31_t)0x15fd4d2, (q31_t)0x40d80, (q31_t)0x16c650b, + (q31_t)0x45648, (q31_t)0x178f536, (q31_t)0x4a188, (q31_t)0x1858552, + (q31_t)0x4ef3f, (q31_t)0x192155f, (q31_t)0x53f6e, (q31_t)0x19ea55d, + (q31_t)0x59214, (q31_t)0x1ab354b, (q31_t)0x5e731, (q31_t)0x1b7c528, + (q31_t)0x63ec6, (q31_t)0x1c454f5, (q31_t)0x698d3, (q31_t)0x1d0e4b0, + (q31_t)0x6f556, (q31_t)0x1dd7459, (q31_t)0x75452, (q31_t)0x1ea03ef, + (q31_t)0x7b5c4, (q31_t)0x1f69373, (q31_t)0x819ae, (q31_t)0x20322e3, + (q31_t)0x8800f, (q31_t)0x20fb240, (q31_t)0x8e8e8, (q31_t)0x21c4188, + (q31_t)0x95438, (q31_t)0x228d0bb, (q31_t)0x9c1ff, (q31_t)0x2355fd9, + (q31_t)0xa323d, (q31_t)0x241eee2, (q31_t)0xaa4f3, (q31_t)0x24e7dd4, + (q31_t)0xb1a20, (q31_t)0x25b0caf, (q31_t)0xb91c4, (q31_t)0x2679b73, + (q31_t)0xc0be0, (q31_t)0x2742a1f, (q31_t)0xc8872, (q31_t)0x280b8b3, + (q31_t)0xd077c, (q31_t)0x28d472e, (q31_t)0xd88fd, (q31_t)0x299d590, + (q31_t)0xe0cf5, (q31_t)0x2a663d8, (q31_t)0xe9364, (q31_t)0x2b2f207, + (q31_t)0xf1c4a, (q31_t)0x2bf801a, (q31_t)0xfa7a8, (q31_t)0x2cc0e13, + (q31_t)0x10357c, (q31_t)0x2d89bf0, (q31_t)0x10c5c7, (q31_t)0x2e529b0, + (q31_t)0x11588a, (q31_t)0x2f1b755, (q31_t)0x11edc3, (q31_t)0x2fe44dc, + (q31_t)0x128574, (q31_t)0x30ad245, (q31_t)0x131f9b, (q31_t)0x3175f91, + (q31_t)0x13bc39, (q31_t)0x323ecbe, (q31_t)0x145b4e, (q31_t)0x33079cc, + (q31_t)0x14fcda, (q31_t)0x33d06bb, (q31_t)0x15a0dd, (q31_t)0x3499389, + (q31_t)0x164757, (q31_t)0x3562038, (q31_t)0x16f047, (q31_t)0x362acc5, + (q31_t)0x179bae, (q31_t)0x36f3931, (q31_t)0x18498c, (q31_t)0x37bc57b, + (q31_t)0x18f9e1, (q31_t)0x38851a2, (q31_t)0x19acac, (q31_t)0x394dda7, + (q31_t)0x1a61ee, (q31_t)0x3a16988, (q31_t)0x1b19a7, (q31_t)0x3adf546, + (q31_t)0x1bd3d6, (q31_t)0x3ba80df, (q31_t)0x1c907c, (q31_t)0x3c70c54, + (q31_t)0x1d4f99, (q31_t)0x3d397a3, (q31_t)0x1e112b, (q31_t)0x3e022cc, + (q31_t)0x1ed535, (q31_t)0x3ecadcf, (q31_t)0x1f9bb5, (q31_t)0x3f938ac, + (q31_t)0x2064ab, (q31_t)0x405c361, (q31_t)0x213018, (q31_t)0x4124dee, + (q31_t)0x21fdfb, (q31_t)0x41ed854, (q31_t)0x22ce54, (q31_t)0x42b6290, + (q31_t)0x23a124, (q31_t)0x437eca4, (q31_t)0x24766a, (q31_t)0x444768d, + (q31_t)0x254e27, (q31_t)0x451004d, (q31_t)0x262859, (q31_t)0x45d89e2, + (q31_t)0x270502, (q31_t)0x46a134c, (q31_t)0x27e421, (q31_t)0x4769c8b, + (q31_t)0x28c5b6, (q31_t)0x483259d, (q31_t)0x29a9c1, (q31_t)0x48fae83, + (q31_t)0x2a9042, (q31_t)0x49c373c, (q31_t)0x2b7939, (q31_t)0x4a8bfc7, + (q31_t)0x2c64a6, (q31_t)0x4b54825, (q31_t)0x2d5289, (q31_t)0x4c1d054, + (q31_t)0x2e42e2, (q31_t)0x4ce5854, (q31_t)0x2f35b1, (q31_t)0x4dae024, + (q31_t)0x302af5, (q31_t)0x4e767c5, (q31_t)0x3122b0, (q31_t)0x4f3ef35, + (q31_t)0x321ce0, (q31_t)0x5007674, (q31_t)0x331986, (q31_t)0x50cfd82, + (q31_t)0x3418a2, (q31_t)0x519845e, (q31_t)0x351a33, (q31_t)0x5260b08, + (q31_t)0x361e3a, (q31_t)0x532917f, (q31_t)0x3724b6, (q31_t)0x53f17c3, + (q31_t)0x382da8, (q31_t)0x54b9dd3, (q31_t)0x393910, (q31_t)0x55823ae, + (q31_t)0x3a46ed, (q31_t)0x564a955, (q31_t)0x3b573f, (q31_t)0x5712ec7, + (q31_t)0x3c6a07, (q31_t)0x57db403, (q31_t)0x3d7f44, (q31_t)0x58a3908, + (q31_t)0x3e96f6, (q31_t)0x596bdd7, (q31_t)0x3fb11d, (q31_t)0x5a3426f, + (q31_t)0x40cdba, (q31_t)0x5afc6d0, (q31_t)0x41eccc, (q31_t)0x5bc4af8, + (q31_t)0x430e53, (q31_t)0x5c8cee7, (q31_t)0x44324f, (q31_t)0x5d5529e, + (q31_t)0x4558c0, (q31_t)0x5e1d61b, (q31_t)0x4681a6, (q31_t)0x5ee595d, + (q31_t)0x47ad01, (q31_t)0x5fadc66, (q31_t)0x48dad1, (q31_t)0x6075f33, + (q31_t)0x4a0b16, (q31_t)0x613e1c5, (q31_t)0x4b3dcf, (q31_t)0x620641a, + (q31_t)0x4c72fe, (q31_t)0x62ce634, (q31_t)0x4daaa1, (q31_t)0x6396810, + (q31_t)0x4ee4b8, (q31_t)0x645e9af, (q31_t)0x502145, (q31_t)0x6526b10, + (q31_t)0x516045, (q31_t)0x65eec33, (q31_t)0x52a1bb, (q31_t)0x66b6d16, + (q31_t)0x53e5a5, (q31_t)0x677edbb, (q31_t)0x552c03, (q31_t)0x6846e1f, + (q31_t)0x5674d6, (q31_t)0x690ee44, (q31_t)0x57c01d, (q31_t)0x69d6e27, + (q31_t)0x590dd8, (q31_t)0x6a9edc9, (q31_t)0x5a5e07, (q31_t)0x6b66d29, + (q31_t)0x5bb0ab, (q31_t)0x6c2ec48, (q31_t)0x5d05c3, (q31_t)0x6cf6b23, + (q31_t)0x5e5d4e, (q31_t)0x6dbe9bb, (q31_t)0x5fb74e, (q31_t)0x6e86810, + (q31_t)0x6113c2, (q31_t)0x6f4e620, (q31_t)0x6272aa, (q31_t)0x70163eb, + (q31_t)0x63d405, (q31_t)0x70de172, (q31_t)0x6537d4, (q31_t)0x71a5eb3, + (q31_t)0x669e18, (q31_t)0x726dbae, (q31_t)0x6806ce, (q31_t)0x7335862, + (q31_t)0x6971f9, (q31_t)0x73fd4cf, (q31_t)0x6adf97, (q31_t)0x74c50f4, + (q31_t)0x6c4fa8, (q31_t)0x758ccd2, (q31_t)0x6dc22e, (q31_t)0x7654867, + (q31_t)0x6f3726, (q31_t)0x771c3b3, (q31_t)0x70ae92, (q31_t)0x77e3eb5, + (q31_t)0x722871, (q31_t)0x78ab96e, (q31_t)0x73a4c3, (q31_t)0x79733dc, + (q31_t)0x752389, (q31_t)0x7a3adff, (q31_t)0x76a4c2, (q31_t)0x7b027d7, + (q31_t)0x78286e, (q31_t)0x7bca163, (q31_t)0x79ae8c, (q31_t)0x7c91aa3, + (q31_t)0x7b371e, (q31_t)0x7d59396, (q31_t)0x7cc223, (q31_t)0x7e20c3b, + (q31_t)0x7e4f9b, (q31_t)0x7ee8493, (q31_t)0x7fdf85, (q31_t)0x7fafc9c, + (q31_t)0x8171e2, (q31_t)0x8077457, (q31_t)0x8306b2, (q31_t)0x813ebc2, + (q31_t)0x849df4, (q31_t)0x82062de, (q31_t)0x8637a9, (q31_t)0x82cd9a9, + (q31_t)0x87d3d0, (q31_t)0x8395024, (q31_t)0x89726a, (q31_t)0x845c64d, + (q31_t)0x8b1376, (q31_t)0x8523c25, (q31_t)0x8cb6f5, (q31_t)0x85eb1ab, + (q31_t)0x8e5ce5, (q31_t)0x86b26de, (q31_t)0x900548, (q31_t)0x8779bbe, + (q31_t)0x91b01d, (q31_t)0x884104b, (q31_t)0x935d64, (q31_t)0x8908483, + (q31_t)0x950d1d, (q31_t)0x89cf867, (q31_t)0x96bf48, (q31_t)0x8a96bf6, + (q31_t)0x9873e4, (q31_t)0x8b5df30, (q31_t)0x9a2af3, (q31_t)0x8c25213, + (q31_t)0x9be473, (q31_t)0x8cec4a0, (q31_t)0x9da065, (q31_t)0x8db36d6, + (q31_t)0x9f5ec8, (q31_t)0x8e7a8b5, (q31_t)0xa11f9d, (q31_t)0x8f41a3c, + (q31_t)0xa2e2e3, (q31_t)0x9008b6a, (q31_t)0xa4a89b, (q31_t)0x90cfc40, + (q31_t)0xa670c4, (q31_t)0x9196cbc, (q31_t)0xa83b5e, (q31_t)0x925dcdf, + (q31_t)0xaa086a, (q31_t)0x9324ca7, (q31_t)0xabd7e6, (q31_t)0x93ebc14, + (q31_t)0xada9d4, (q31_t)0x94b2b27, (q31_t)0xaf7e33, (q31_t)0x95799dd, + (q31_t)0xb15502, (q31_t)0x9640837, (q31_t)0xb32e42, (q31_t)0x9707635, + (q31_t)0xb509f3, (q31_t)0x97ce3d5, (q31_t)0xb6e815, (q31_t)0x9895118, + (q31_t)0xb8c8a7, (q31_t)0x995bdfd, (q31_t)0xbaabaa, (q31_t)0x9a22a83, + (q31_t)0xbc911d, (q31_t)0x9ae96aa, (q31_t)0xbe7901, (q31_t)0x9bb0271, + (q31_t)0xc06355, (q31_t)0x9c76dd8, (q31_t)0xc25019, (q31_t)0x9d3d8df, + (q31_t)0xc43f4d, (q31_t)0x9e04385, (q31_t)0xc630f2, (q31_t)0x9ecadc9, + (q31_t)0xc82506, (q31_t)0x9f917ac, (q31_t)0xca1b8a, (q31_t)0xa05812c, + (q31_t)0xcc147f, (q31_t)0xa11ea49, (q31_t)0xce0fe3, (q31_t)0xa1e5303, + (q31_t)0xd00db6, (q31_t)0xa2abb59, (q31_t)0xd20dfa, (q31_t)0xa37234a, + (q31_t)0xd410ad, (q31_t)0xa438ad7, (q31_t)0xd615cf, (q31_t)0xa4ff1fe, + (q31_t)0xd81d61, (q31_t)0xa5c58c0, (q31_t)0xda2762, (q31_t)0xa68bf1b, + (q31_t)0xdc33d2, (q31_t)0xa752510, (q31_t)0xde42b2, (q31_t)0xa818a9d, + (q31_t)0xe05401, (q31_t)0xa8defc3, (q31_t)0xe267be, (q31_t)0xa9a5480, + (q31_t)0xe47deb, (q31_t)0xaa6b8d5, (q31_t)0xe69686, (q31_t)0xab31cc1, + (q31_t)0xe8b190, (q31_t)0xabf8043, (q31_t)0xeacf09, (q31_t)0xacbe35b, + (q31_t)0xeceef1, (q31_t)0xad84609, (q31_t)0xef1147, (q31_t)0xae4a84b, + (q31_t)0xf1360b, (q31_t)0xaf10a22, (q31_t)0xf35d3e, (q31_t)0xafd6b8d, + (q31_t)0xf586df, (q31_t)0xb09cc8c, (q31_t)0xf7b2ee, (q31_t)0xb162d1d, + (q31_t)0xf9e16b, (q31_t)0xb228d42, (q31_t)0xfc1257, (q31_t)0xb2eecf8, + (q31_t)0xfe45b0, (q31_t)0xb3b4c40, (q31_t)0x1007b77, (q31_t)0xb47ab19, + (q31_t)0x102b3ac, (q31_t)0xb540982, (q31_t)0x104ee4f, (q31_t)0xb60677c, + (q31_t)0x1072b5f, (q31_t)0xb6cc506, (q31_t)0x1096add, (q31_t)0xb79221f, + (q31_t)0x10bacc8, (q31_t)0xb857ec7, (q31_t)0x10df120, (q31_t)0xb91dafc, + (q31_t)0x11037e6, (q31_t)0xb9e36c0, (q31_t)0x1128119, (q31_t)0xbaa9211, + (q31_t)0x114ccb9, (q31_t)0xbb6ecef, (q31_t)0x1171ac6, (q31_t)0xbc34759, + (q31_t)0x1196b3f, (q31_t)0xbcfa150, (q31_t)0x11bbe26, (q31_t)0xbdbfad1, + (q31_t)0x11e1379, (q31_t)0xbe853de, (q31_t)0x1206b39, (q31_t)0xbf4ac75, + (q31_t)0x122c566, (q31_t)0xc010496, (q31_t)0x12521ff, (q31_t)0xc0d5c41, + (q31_t)0x1278104, (q31_t)0xc19b374, (q31_t)0x129e276, (q31_t)0xc260a31, + (q31_t)0x12c4653, (q31_t)0xc326075, (q31_t)0x12eac9d, (q31_t)0xc3eb641, + (q31_t)0x1311553, (q31_t)0xc4b0b94, (q31_t)0x1338075, (q31_t)0xc57606e, + (q31_t)0x135ee02, (q31_t)0xc63b4ce, (q31_t)0x1385dfb, (q31_t)0xc7008b3, + (q31_t)0x13ad060, (q31_t)0xc7c5c1e, (q31_t)0x13d4530, (q31_t)0xc88af0e, + (q31_t)0x13fbc6c, (q31_t)0xc950182, (q31_t)0x1423613, (q31_t)0xca1537a, + (q31_t)0x144b225, (q31_t)0xcada4f5, (q31_t)0x14730a3, (q31_t)0xcb9f5f3, + (q31_t)0x149b18b, (q31_t)0xcc64673, (q31_t)0x14c34df, (q31_t)0xcd29676, + (q31_t)0x14eba9d, (q31_t)0xcdee5f9, (q31_t)0x15142c6, (q31_t)0xceb34fe, + (q31_t)0x153cd5a, (q31_t)0xcf78383, (q31_t)0x1565a58, (q31_t)0xd03d189, + (q31_t)0x158e9c1, (q31_t)0xd101f0e, (q31_t)0x15b7b94, (q31_t)0xd1c6c11, + (q31_t)0x15e0fd1, (q31_t)0xd28b894, (q31_t)0x160a678, (q31_t)0xd350495, + (q31_t)0x1633f8a, (q31_t)0xd415013, (q31_t)0x165db05, (q31_t)0xd4d9b0e, + (q31_t)0x16878eb, (q31_t)0xd59e586, (q31_t)0x16b193a, (q31_t)0xd662f7b, + (q31_t)0x16dbbf3, (q31_t)0xd7278eb, (q31_t)0x1706115, (q31_t)0xd7ec1d6, + (q31_t)0x17308a1, (q31_t)0xd8b0a3d, (q31_t)0x175b296, (q31_t)0xd97521d, + (q31_t)0x1785ef4, (q31_t)0xda39978, (q31_t)0x17b0dbb, (q31_t)0xdafe04b, + (q31_t)0x17dbeec, (q31_t)0xdbc2698, (q31_t)0x1807285, (q31_t)0xdc86c5d, + (q31_t)0x1832888, (q31_t)0xdd4b19a, (q31_t)0x185e0f3, (q31_t)0xde0f64f, + (q31_t)0x1889bc6, (q31_t)0xded3a7b, (q31_t)0x18b5903, (q31_t)0xdf97e1d, + (q31_t)0x18e18a7, (q31_t)0xe05c135, (q31_t)0x190dab4, (q31_t)0xe1203c3, + (q31_t)0x1939f29, (q31_t)0xe1e45c6, (q31_t)0x1966606, (q31_t)0xe2a873e, + (q31_t)0x1992f4c, (q31_t)0xe36c82a, (q31_t)0x19bfaf9, (q31_t)0xe430889, + (q31_t)0x19ec90d, (q31_t)0xe4f485c, (q31_t)0x1a1998a, (q31_t)0xe5b87a2, + (q31_t)0x1a46c6e, (q31_t)0xe67c65a, (q31_t)0x1a741b9, (q31_t)0xe740483, + (q31_t)0x1aa196c, (q31_t)0xe80421e, (q31_t)0x1acf386, (q31_t)0xe8c7f2a, + (q31_t)0x1afd007, (q31_t)0xe98bba7, (q31_t)0x1b2aef0, (q31_t)0xea4f793, + (q31_t)0x1b5903f, (q31_t)0xeb132ef, (q31_t)0x1b873f5, (q31_t)0xebd6db9, + (q31_t)0x1bb5a11, (q31_t)0xec9a7f3, (q31_t)0x1be4294, (q31_t)0xed5e19a, + (q31_t)0x1c12d7e, (q31_t)0xee21aaf, (q31_t)0x1c41ace, (q31_t)0xeee5331, + (q31_t)0x1c70a84, (q31_t)0xefa8b20, (q31_t)0x1c9fca0, (q31_t)0xf06c27a, + (q31_t)0x1ccf122, (q31_t)0xf12f941, (q31_t)0x1cfe80a, (q31_t)0xf1f2f73, + (q31_t)0x1d2e158, (q31_t)0xf2b650f, (q31_t)0x1d5dd0c, (q31_t)0xf379a16, + (q31_t)0x1d8db25, (q31_t)0xf43ce86, (q31_t)0x1dbdba3, (q31_t)0xf500260, + (q31_t)0x1dede87, (q31_t)0xf5c35a3, (q31_t)0x1e1e3d0, (q31_t)0xf68684e, + (q31_t)0x1e4eb7e, (q31_t)0xf749a61, (q31_t)0x1e7f591, (q31_t)0xf80cbdc, + (q31_t)0x1eb0209, (q31_t)0xf8cfcbe, (q31_t)0x1ee10e5, (q31_t)0xf992d06, + (q31_t)0x1f12227, (q31_t)0xfa55cb4, (q31_t)0x1f435cc, (q31_t)0xfb18bc8, + (q31_t)0x1f74bd6, (q31_t)0xfbdba40, (q31_t)0x1fa6445, (q31_t)0xfc9e81e, + (q31_t)0x1fd7f17, (q31_t)0xfd6155f, (q31_t)0x2009c4e, (q31_t)0xfe24205, + (q31_t)0x203bbe8, (q31_t)0xfee6e0d, (q31_t)0x206dde6, (q31_t)0xffa9979, + (q31_t)0x20a0248, (q31_t)0x1006c446, (q31_t)0x20d290d, (q31_t)0x1012ee76, + (q31_t)0x2105236, (q31_t)0x101f1807, (q31_t)0x2137dc2, (q31_t)0x102b40f8, + (q31_t)0x216abb1, (q31_t)0x1037694b, (q31_t)0x219dc03, (q31_t)0x104390fd, + (q31_t)0x21d0eb8, (q31_t)0x104fb80e, (q31_t)0x22043d0, (q31_t)0x105bde7f, + (q31_t)0x2237b4b, (q31_t)0x1068044e, (q31_t)0x226b528, (q31_t)0x1074297b, + (q31_t)0x229f167, (q31_t)0x10804e06, (q31_t)0x22d3009, (q31_t)0x108c71ee, + (q31_t)0x230710d, (q31_t)0x10989532, (q31_t)0x233b473, (q31_t)0x10a4b7d3, + (q31_t)0x236fa3b, (q31_t)0x10b0d9d0, (q31_t)0x23a4265, (q31_t)0x10bcfb28, + (q31_t)0x23d8cf1, (q31_t)0x10c91bda, (q31_t)0x240d9de, (q31_t)0x10d53be7, + (q31_t)0x244292c, (q31_t)0x10e15b4e, (q31_t)0x2477adc, (q31_t)0x10ed7a0e, + (q31_t)0x24aceed, (q31_t)0x10f99827, (q31_t)0x24e255e, (q31_t)0x1105b599, + (q31_t)0x2517e31, (q31_t)0x1111d263, (q31_t)0x254d965, (q31_t)0x111dee84, + (q31_t)0x25836f9, (q31_t)0x112a09fc, (q31_t)0x25b96ee, (q31_t)0x113624cb, + (q31_t)0x25ef943, (q31_t)0x11423ef0, (q31_t)0x2625df8, (q31_t)0x114e586a, + (q31_t)0x265c50e, (q31_t)0x115a713a, (q31_t)0x2692e83, (q31_t)0x1166895f, + (q31_t)0x26c9a58, (q31_t)0x1172a0d7, (q31_t)0x270088e, (q31_t)0x117eb7a4, + (q31_t)0x2737922, (q31_t)0x118acdc4, (q31_t)0x276ec16, (q31_t)0x1196e337, + (q31_t)0x27a616a, (q31_t)0x11a2f7fc, (q31_t)0x27dd91c, (q31_t)0x11af0c13, + (q31_t)0x281532e, (q31_t)0x11bb1f7c, (q31_t)0x284cf9f, (q31_t)0x11c73235, + (q31_t)0x2884e6e, (q31_t)0x11d3443f, (q31_t)0x28bcf9c, (q31_t)0x11df5599, + (q31_t)0x28f5329, (q31_t)0x11eb6643, (q31_t)0x292d914, (q31_t)0x11f7763c, + (q31_t)0x296615d, (q31_t)0x12038584, (q31_t)0x299ec05, (q31_t)0x120f941a, + (q31_t)0x29d790a, (q31_t)0x121ba1fd, (q31_t)0x2a1086d, (q31_t)0x1227af2e, + (q31_t)0x2a49a2e, (q31_t)0x1233bbac, (q31_t)0x2a82e4d, (q31_t)0x123fc776, + (q31_t)0x2abc4c9, (q31_t)0x124bd28c, (q31_t)0x2af5da2, (q31_t)0x1257dced, + (q31_t)0x2b2f8d8, (q31_t)0x1263e699, (q31_t)0x2b6966c, (q31_t)0x126fef90, + (q31_t)0x2ba365c, (q31_t)0x127bf7d1, (q31_t)0x2bdd8a9, (q31_t)0x1287ff5b, + (q31_t)0x2c17d52, (q31_t)0x1294062f, (q31_t)0x2c52459, (q31_t)0x12a00c4b, + (q31_t)0x2c8cdbb, (q31_t)0x12ac11af, (q31_t)0x2cc7979, (q31_t)0x12b8165b, + (q31_t)0x2d02794, (q31_t)0x12c41a4f, (q31_t)0x2d3d80a, (q31_t)0x12d01d89, + (q31_t)0x2d78add, (q31_t)0x12dc2009, (q31_t)0x2db400a, (q31_t)0x12e821cf, + (q31_t)0x2def794, (q31_t)0x12f422db, (q31_t)0x2e2b178, (q31_t)0x1300232c, + (q31_t)0x2e66db8, (q31_t)0x130c22c1, (q31_t)0x2ea2c53, (q31_t)0x1318219a, + (q31_t)0x2eded49, (q31_t)0x13241fb6, (q31_t)0x2f1b099, (q31_t)0x13301d16, + (q31_t)0x2f57644, (q31_t)0x133c19b8, (q31_t)0x2f93e4a, (q31_t)0x1348159d, + (q31_t)0x2fd08a9, (q31_t)0x135410c3, (q31_t)0x300d563, (q31_t)0x13600b2a, + (q31_t)0x304a477, (q31_t)0x136c04d2, (q31_t)0x30875e5, (q31_t)0x1377fdbb, + (q31_t)0x30c49ad, (q31_t)0x1383f5e3, (q31_t)0x3101fce, (q31_t)0x138fed4b, + (q31_t)0x313f848, (q31_t)0x139be3f2, (q31_t)0x317d31c, (q31_t)0x13a7d9d7, + (q31_t)0x31bb049, (q31_t)0x13b3cefa, (q31_t)0x31f8fcf, (q31_t)0x13bfc35b, + (q31_t)0x32371ae, (q31_t)0x13cbb6f8, (q31_t)0x32755e5, (q31_t)0x13d7a9d3, + (q31_t)0x32b3c75, (q31_t)0x13e39be9, (q31_t)0x32f255e, (q31_t)0x13ef8d3c, + (q31_t)0x333109e, (q31_t)0x13fb7dc9, (q31_t)0x336fe37, (q31_t)0x14076d91, + (q31_t)0x33aee27, (q31_t)0x14135c94, (q31_t)0x33ee070, (q31_t)0x141f4ad1, + (q31_t)0x342d510, (q31_t)0x142b3846, (q31_t)0x346cc07, (q31_t)0x143724f5, + (q31_t)0x34ac556, (q31_t)0x144310dd, (q31_t)0x34ec0fc, (q31_t)0x144efbfc, + (q31_t)0x352bef9, (q31_t)0x145ae653, (q31_t)0x356bf4d, (q31_t)0x1466cfe1, + (q31_t)0x35ac1f7, (q31_t)0x1472b8a5, (q31_t)0x35ec6f8, (q31_t)0x147ea0a0, + (q31_t)0x362ce50, (q31_t)0x148a87d1, (q31_t)0x366d7fd, (q31_t)0x14966e36, + (q31_t)0x36ae401, (q31_t)0x14a253d1, (q31_t)0x36ef25b, (q31_t)0x14ae38a0, + (q31_t)0x373030a, (q31_t)0x14ba1ca3, (q31_t)0x377160f, (q31_t)0x14c5ffd9, + (q31_t)0x37b2b6a, (q31_t)0x14d1e242, (q31_t)0x37f4319, (q31_t)0x14ddc3de, + (q31_t)0x3835d1e, (q31_t)0x14e9a4ac, (q31_t)0x3877978, (q31_t)0x14f584ac, + (q31_t)0x38b9827, (q31_t)0x150163dc, (q31_t)0x38fb92a, (q31_t)0x150d423d, + (q31_t)0x393dc82, (q31_t)0x15191fcf, (q31_t)0x398022f, (q31_t)0x1524fc90, + (q31_t)0x39c2a2f, (q31_t)0x1530d881, (q31_t)0x3a05484, (q31_t)0x153cb3a0, + (q31_t)0x3a4812c, (q31_t)0x15488dee, (q31_t)0x3a8b028, (q31_t)0x1554676a, + (q31_t)0x3ace178, (q31_t)0x15604013, (q31_t)0x3b1151b, (q31_t)0x156c17e9, + (q31_t)0x3b54b11, (q31_t)0x1577eeec, (q31_t)0x3b9835a, (q31_t)0x1583c51b, + (q31_t)0x3bdbdf6, (q31_t)0x158f9a76, (q31_t)0x3c1fae5, (q31_t)0x159b6efb, + (q31_t)0x3c63a26, (q31_t)0x15a742ac, (q31_t)0x3ca7bba, (q31_t)0x15b31587, + (q31_t)0x3cebfa0, (q31_t)0x15bee78c, (q31_t)0x3d305d8, (q31_t)0x15cab8ba, + (q31_t)0x3d74e62, (q31_t)0x15d68911, (q31_t)0x3db993e, (q31_t)0x15e25890, + (q31_t)0x3dfe66c, (q31_t)0x15ee2738, (q31_t)0x3e435ea, (q31_t)0x15f9f507, + (q31_t)0x3e887bb, (q31_t)0x1605c1fd, (q31_t)0x3ecdbdc, (q31_t)0x16118e1a, + (q31_t)0x3f1324e, (q31_t)0x161d595d, (q31_t)0x3f58b10, (q31_t)0x162923c5, + (q31_t)0x3f9e624, (q31_t)0x1634ed53, (q31_t)0x3fe4388, (q31_t)0x1640b606, + (q31_t)0x402a33c, (q31_t)0x164c7ddd, (q31_t)0x4070540, (q31_t)0x165844d8, + (q31_t)0x40b6994, (q31_t)0x16640af7, (q31_t)0x40fd037, (q31_t)0x166fd039, + (q31_t)0x414392b, (q31_t)0x167b949d, (q31_t)0x418a46d, (q31_t)0x16875823, + (q31_t)0x41d11ff, (q31_t)0x16931acb, (q31_t)0x42181e0, (q31_t)0x169edc94, + (q31_t)0x425f410, (q31_t)0x16aa9d7e, (q31_t)0x42a688f, (q31_t)0x16b65d88, + (q31_t)0x42edf5c, (q31_t)0x16c21cb2, (q31_t)0x4335877, (q31_t)0x16cddafb, + (q31_t)0x437d3e1, (q31_t)0x16d99864, (q31_t)0x43c5199, (q31_t)0x16e554ea, + (q31_t)0x440d19e, (q31_t)0x16f1108f, (q31_t)0x44553f2, (q31_t)0x16fccb51, + (q31_t)0x449d892, (q31_t)0x17088531, (q31_t)0x44e5f80, (q31_t)0x17143e2d, + (q31_t)0x452e8bc, (q31_t)0x171ff646, (q31_t)0x4577444, (q31_t)0x172bad7a, + (q31_t)0x45c0219, (q31_t)0x173763c9, (q31_t)0x460923b, (q31_t)0x17431933, + (q31_t)0x46524a9, (q31_t)0x174ecdb8, (q31_t)0x469b963, (q31_t)0x175a8157, + (q31_t)0x46e5069, (q31_t)0x1766340f, (q31_t)0x472e9bc, (q31_t)0x1771e5e0, + (q31_t)0x477855a, (q31_t)0x177d96ca, (q31_t)0x47c2344, (q31_t)0x178946cc, + (q31_t)0x480c379, (q31_t)0x1794f5e6, (q31_t)0x48565f9, (q31_t)0x17a0a417, + (q31_t)0x48a0ac4, (q31_t)0x17ac515f, (q31_t)0x48eb1db, (q31_t)0x17b7fdbd, + (q31_t)0x4935b3c, (q31_t)0x17c3a931, (q31_t)0x49806e7, (q31_t)0x17cf53bb, + (q31_t)0x49cb4dd, (q31_t)0x17dafd59, (q31_t)0x4a1651c, (q31_t)0x17e6a60c, + (q31_t)0x4a617a6, (q31_t)0x17f24dd3, (q31_t)0x4aacc7a, (q31_t)0x17fdf4ae, + (q31_t)0x4af8397, (q31_t)0x18099a9c, (q31_t)0x4b43cfd, (q31_t)0x18153f9d, + (q31_t)0x4b8f8ad, (q31_t)0x1820e3b0, (q31_t)0x4bdb6a6, (q31_t)0x182c86d5, + (q31_t)0x4c276e8, (q31_t)0x1838290c, (q31_t)0x4c73972, (q31_t)0x1843ca53, + (q31_t)0x4cbfe45, (q31_t)0x184f6aab, (q31_t)0x4d0c560, (q31_t)0x185b0a13, + (q31_t)0x4d58ec3, (q31_t)0x1866a88a, (q31_t)0x4da5a6f, (q31_t)0x18724611, + (q31_t)0x4df2862, (q31_t)0x187de2a7, (q31_t)0x4e3f89c, (q31_t)0x18897e4a, + (q31_t)0x4e8cb1e, (q31_t)0x189518fc, (q31_t)0x4ed9fe7, (q31_t)0x18a0b2bb, + (q31_t)0x4f276f7, (q31_t)0x18ac4b87, (q31_t)0x4f7504e, (q31_t)0x18b7e35f, + (q31_t)0x4fc2bec, (q31_t)0x18c37a44, (q31_t)0x50109d0, (q31_t)0x18cf1034, + (q31_t)0x505e9fb, (q31_t)0x18daa52f, (q31_t)0x50acc6b, (q31_t)0x18e63935, + (q31_t)0x50fb121, (q31_t)0x18f1cc45, (q31_t)0x514981d, (q31_t)0x18fd5e5f, + (q31_t)0x519815f, (q31_t)0x1908ef82, (q31_t)0x51e6ce6, (q31_t)0x19147fae, + (q31_t)0x5235ab2, (q31_t)0x19200ee3, (q31_t)0x5284ac3, (q31_t)0x192b9d1f, + (q31_t)0x52d3d18, (q31_t)0x19372a64, (q31_t)0x53231b3, (q31_t)0x1942b6af, + (q31_t)0x5372891, (q31_t)0x194e4201, (q31_t)0x53c21b4, (q31_t)0x1959cc5a, + (q31_t)0x5411d1b, (q31_t)0x196555b8, (q31_t)0x5461ac6, (q31_t)0x1970de1b, + (q31_t)0x54b1ab4, (q31_t)0x197c6584, (q31_t)0x5501ce5, (q31_t)0x1987ebf0, + (q31_t)0x555215a, (q31_t)0x19937161, (q31_t)0x55a2812, (q31_t)0x199ef5d6, + (q31_t)0x55f310d, (q31_t)0x19aa794d, (q31_t)0x5643c4a, (q31_t)0x19b5fbc8, + (q31_t)0x56949ca, (q31_t)0x19c17d44, (q31_t)0x56e598c, (q31_t)0x19ccfdc2, + (q31_t)0x5736b90, (q31_t)0x19d87d42, (q31_t)0x5787fd6, (q31_t)0x19e3fbc3, + (q31_t)0x57d965d, (q31_t)0x19ef7944, (q31_t)0x582af26, (q31_t)0x19faf5c5, + (q31_t)0x587ca31, (q31_t)0x1a067145, (q31_t)0x58ce77c, (q31_t)0x1a11ebc5, + (q31_t)0x5920708, (q31_t)0x1a1d6544, (q31_t)0x59728d5, (q31_t)0x1a28ddc0, + (q31_t)0x59c4ce3, (q31_t)0x1a34553b, (q31_t)0x5a17330, (q31_t)0x1a3fcbb3, + (q31_t)0x5a69bbe, (q31_t)0x1a4b4128, (q31_t)0x5abc68c, (q31_t)0x1a56b599, + (q31_t)0x5b0f399, (q31_t)0x1a622907, (q31_t)0x5b622e6, (q31_t)0x1a6d9b70, + (q31_t)0x5bb5472, (q31_t)0x1a790cd4, (q31_t)0x5c0883d, (q31_t)0x1a847d33, + (q31_t)0x5c5be47, (q31_t)0x1a8fec8c, (q31_t)0x5caf690, (q31_t)0x1a9b5adf, + (q31_t)0x5d03118, (q31_t)0x1aa6c82b, (q31_t)0x5d56ddd, (q31_t)0x1ab23471, + (q31_t)0x5daace1, (q31_t)0x1abd9faf, (q31_t)0x5dfee22, (q31_t)0x1ac909e5, + (q31_t)0x5e531a1, (q31_t)0x1ad47312, (q31_t)0x5ea775e, (q31_t)0x1adfdb37, + (q31_t)0x5efbf58, (q31_t)0x1aeb4253, (q31_t)0x5f5098f, (q31_t)0x1af6a865, + (q31_t)0x5fa5603, (q31_t)0x1b020d6c, (q31_t)0x5ffa4b3, (q31_t)0x1b0d716a, + (q31_t)0x604f5a0, (q31_t)0x1b18d45c, (q31_t)0x60a48c9, (q31_t)0x1b243643, + (q31_t)0x60f9e2e, (q31_t)0x1b2f971e, (q31_t)0x614f5cf, (q31_t)0x1b3af6ec, + (q31_t)0x61a4fac, (q31_t)0x1b4655ae, (q31_t)0x61fabc4, (q31_t)0x1b51b363, + (q31_t)0x6250a18, (q31_t)0x1b5d100a, (q31_t)0x62a6aa6, (q31_t)0x1b686ba3, + (q31_t)0x62fcd6f, (q31_t)0x1b73c62d, (q31_t)0x6353273, (q31_t)0x1b7f1fa9, + (q31_t)0x63a99b1, (q31_t)0x1b8a7815, (q31_t)0x6400329, (q31_t)0x1b95cf71, + (q31_t)0x6456edb, (q31_t)0x1ba125bd, (q31_t)0x64adcc7, (q31_t)0x1bac7af9, + (q31_t)0x6504ced, (q31_t)0x1bb7cf23, (q31_t)0x655bf4c, (q31_t)0x1bc3223c, + (q31_t)0x65b33e4, (q31_t)0x1bce7442, (q31_t)0x660aab5, (q31_t)0x1bd9c537, + (q31_t)0x66623be, (q31_t)0x1be51518, (q31_t)0x66b9f01, (q31_t)0x1bf063e6, + (q31_t)0x6711c7b, (q31_t)0x1bfbb1a0, (q31_t)0x6769c2e, (q31_t)0x1c06fe46, + (q31_t)0x67c1e18, (q31_t)0x1c1249d8, (q31_t)0x681a23a, (q31_t)0x1c1d9454, + (q31_t)0x6872894, (q31_t)0x1c28ddbb, (q31_t)0x68cb124, (q31_t)0x1c34260c, + (q31_t)0x6923bec, (q31_t)0x1c3f6d47, (q31_t)0x697c8eb, (q31_t)0x1c4ab36b, + (q31_t)0x69d5820, (q31_t)0x1c55f878, (q31_t)0x6a2e98b, (q31_t)0x1c613c6d, + (q31_t)0x6a87d2d, (q31_t)0x1c6c7f4a, (q31_t)0x6ae1304, (q31_t)0x1c77c10e, + (q31_t)0x6b3ab12, (q31_t)0x1c8301b9, (q31_t)0x6b94554, (q31_t)0x1c8e414b, + (q31_t)0x6bee1cd, (q31_t)0x1c997fc4, (q31_t)0x6c4807a, (q31_t)0x1ca4bd21, + (q31_t)0x6ca215c, (q31_t)0x1caff965, (q31_t)0x6cfc472, (q31_t)0x1cbb348d, + (q31_t)0x6d569be, (q31_t)0x1cc66e99, (q31_t)0x6db113d, (q31_t)0x1cd1a78a, + (q31_t)0x6e0baf0, (q31_t)0x1cdcdf5e, (q31_t)0x6e666d7, (q31_t)0x1ce81615, + (q31_t)0x6ec14f2, (q31_t)0x1cf34baf, (q31_t)0x6f1c540, (q31_t)0x1cfe802b, + (q31_t)0x6f777c1, (q31_t)0x1d09b389, (q31_t)0x6fd2c75, (q31_t)0x1d14e5c9, + (q31_t)0x702e35c, (q31_t)0x1d2016e9, (q31_t)0x7089c75, (q31_t)0x1d2b46ea, + (q31_t)0x70e57c0, (q31_t)0x1d3675cb, (q31_t)0x714153e, (q31_t)0x1d41a38c, + (q31_t)0x719d4ed, (q31_t)0x1d4cd02c, (q31_t)0x71f96ce, (q31_t)0x1d57fbaa, + (q31_t)0x7255ae0, (q31_t)0x1d632608, (q31_t)0x72b2123, (q31_t)0x1d6e4f43, + (q31_t)0x730e997, (q31_t)0x1d79775c, (q31_t)0x736b43c, (q31_t)0x1d849e51, + (q31_t)0x73c8111, (q31_t)0x1d8fc424, (q31_t)0x7425016, (q31_t)0x1d9ae8d2, + (q31_t)0x748214c, (q31_t)0x1da60c5d, (q31_t)0x74df4b1, (q31_t)0x1db12ec3, + (q31_t)0x753ca46, (q31_t)0x1dbc5004, (q31_t)0x759a20a, (q31_t)0x1dc7701f, + (q31_t)0x75f7bfe, (q31_t)0x1dd28f15, (q31_t)0x7655820, (q31_t)0x1dddace4, + (q31_t)0x76b3671, (q31_t)0x1de8c98c, (q31_t)0x77116f0, (q31_t)0x1df3e50d, + (q31_t)0x776f99d, (q31_t)0x1dfeff67, (q31_t)0x77cde79, (q31_t)0x1e0a1898, + (q31_t)0x782c582, (q31_t)0x1e1530a1, (q31_t)0x788aeb9, (q31_t)0x1e204781, + (q31_t)0x78e9a1d, (q31_t)0x1e2b5d38, (q31_t)0x79487ae, (q31_t)0x1e3671c5, + (q31_t)0x79a776c, (q31_t)0x1e418528, (q31_t)0x7a06957, (q31_t)0x1e4c9760, + (q31_t)0x7a65d6e, (q31_t)0x1e57a86d, (q31_t)0x7ac53b1, (q31_t)0x1e62b84f, + (q31_t)0x7b24c20, (q31_t)0x1e6dc705, (q31_t)0x7b846ba, (q31_t)0x1e78d48e, + (q31_t)0x7be4381, (q31_t)0x1e83e0eb, (q31_t)0x7c44272, (q31_t)0x1e8eec1b, + (q31_t)0x7ca438f, (q31_t)0x1e99f61d, (q31_t)0x7d046d6, (q31_t)0x1ea4fef0, + (q31_t)0x7d64c47, (q31_t)0x1eb00696, (q31_t)0x7dc53e3, (q31_t)0x1ebb0d0d, + (q31_t)0x7e25daa, (q31_t)0x1ec61254, (q31_t)0x7e8699a, (q31_t)0x1ed1166b, + (q31_t)0x7ee77b3, (q31_t)0x1edc1953, (q31_t)0x7f487f6, (q31_t)0x1ee71b0a, + (q31_t)0x7fa9a62, (q31_t)0x1ef21b90, (q31_t)0x800aef7, (q31_t)0x1efd1ae4, + (q31_t)0x806c5b5, (q31_t)0x1f081907, (q31_t)0x80cde9b, (q31_t)0x1f1315f7, + (q31_t)0x812f9a9, (q31_t)0x1f1e11b5, (q31_t)0x81916df, (q31_t)0x1f290c3f, + (q31_t)0x81f363d, (q31_t)0x1f340596, (q31_t)0x82557c3, (q31_t)0x1f3efdb9, + (q31_t)0x82b7b70, (q31_t)0x1f49f4a8, (q31_t)0x831a143, (q31_t)0x1f54ea62, + (q31_t)0x837c93e, (q31_t)0x1f5fdee6, (q31_t)0x83df35f, (q31_t)0x1f6ad235, + (q31_t)0x8441fa6, (q31_t)0x1f75c44e, (q31_t)0x84a4e14, (q31_t)0x1f80b531, + (q31_t)0x8507ea7, (q31_t)0x1f8ba4dc, (q31_t)0x856b160, (q31_t)0x1f969350, + (q31_t)0x85ce63e, (q31_t)0x1fa1808c, (q31_t)0x8631d42, (q31_t)0x1fac6c91, + (q31_t)0x869566a, (q31_t)0x1fb7575c, (q31_t)0x86f91b7, (q31_t)0x1fc240ef, + (q31_t)0x875cf28, (q31_t)0x1fcd2948, (q31_t)0x87c0ebd, (q31_t)0x1fd81067, + (q31_t)0x8825077, (q31_t)0x1fe2f64c, (q31_t)0x8889454, (q31_t)0x1feddaf6, + (q31_t)0x88eda54, (q31_t)0x1ff8be65, (q31_t)0x8952278, (q31_t)0x2003a099, + (q31_t)0x89b6cbf, (q31_t)0x200e8190, (q31_t)0x8a1b928, (q31_t)0x2019614c, + (q31_t)0x8a807b4, (q31_t)0x20243fca, (q31_t)0x8ae5862, (q31_t)0x202f1d0b, + (q31_t)0x8b4ab32, (q31_t)0x2039f90f, (q31_t)0x8bb0023, (q31_t)0x2044d3d4, + (q31_t)0x8c15736, (q31_t)0x204fad5b, (q31_t)0x8c7b06b, (q31_t)0x205a85a3, + (q31_t)0x8ce0bc0, (q31_t)0x20655cac, (q31_t)0x8d46936, (q31_t)0x20703275, + (q31_t)0x8dac8cd, (q31_t)0x207b06fe, (q31_t)0x8e12a84, (q31_t)0x2085da46, + (q31_t)0x8e78e5b, (q31_t)0x2090ac4d, (q31_t)0x8edf452, (q31_t)0x209b7d13, + (q31_t)0x8f45c68, (q31_t)0x20a64c97, (q31_t)0x8fac69e, (q31_t)0x20b11ad9, + (q31_t)0x90132f2, (q31_t)0x20bbe7d8, (q31_t)0x907a166, (q31_t)0x20c6b395, + (q31_t)0x90e11f7, (q31_t)0x20d17e0d, (q31_t)0x91484a8, (q31_t)0x20dc4742, + (q31_t)0x91af976, (q31_t)0x20e70f32, (q31_t)0x9217062, (q31_t)0x20f1d5de, + (q31_t)0x927e96b, (q31_t)0x20fc9b44, (q31_t)0x92e6492, (q31_t)0x21075f65, + (q31_t)0x934e1d6, (q31_t)0x21122240, (q31_t)0x93b6137, (q31_t)0x211ce3d5, + (q31_t)0x941e2b4, (q31_t)0x2127a423, (q31_t)0x948664d, (q31_t)0x21326329, + (q31_t)0x94eec03, (q31_t)0x213d20e8, (q31_t)0x95573d4, (q31_t)0x2147dd5f, + (q31_t)0x95bfdc1, (q31_t)0x2152988d, (q31_t)0x96289c9, (q31_t)0x215d5273, + (q31_t)0x96917ec, (q31_t)0x21680b0f, (q31_t)0x96fa82a, (q31_t)0x2172c262, + (q31_t)0x9763a83, (q31_t)0x217d786a, (q31_t)0x97ccef5, (q31_t)0x21882d28, + (q31_t)0x9836582, (q31_t)0x2192e09b, (q31_t)0x989fe29, (q31_t)0x219d92c2, + (q31_t)0x99098e9, (q31_t)0x21a8439e, (q31_t)0x99735c2, (q31_t)0x21b2f32e, + (q31_t)0x99dd4b4, (q31_t)0x21bda171, (q31_t)0x9a475bf, (q31_t)0x21c84e67, + (q31_t)0x9ab18e3, (q31_t)0x21d2fa0f, (q31_t)0x9b1be1e, (q31_t)0x21dda46a, + (q31_t)0x9b86572, (q31_t)0x21e84d76, (q31_t)0x9bf0edd, (q31_t)0x21f2f534, + (q31_t)0x9c5ba60, (q31_t)0x21fd9ba3, (q31_t)0x9cc67fa, (q31_t)0x220840c2, + (q31_t)0x9d317ab, (q31_t)0x2212e492, (q31_t)0x9d9c973, (q31_t)0x221d8711, + (q31_t)0x9e07d51, (q31_t)0x2228283f, (q31_t)0x9e73346, (q31_t)0x2232c81c, + (q31_t)0x9edeb50, (q31_t)0x223d66a8, (q31_t)0x9f4a570, (q31_t)0x224803e2, + (q31_t)0x9fb61a5, (q31_t)0x22529fca, (q31_t)0xa021fef, (q31_t)0x225d3a5e, + (q31_t)0xa08e04f, (q31_t)0x2267d3a0, (q31_t)0xa0fa2c3, (q31_t)0x22726b8e, + (q31_t)0xa16674b, (q31_t)0x227d0228, (q31_t)0xa1d2de7, (q31_t)0x2287976e, + (q31_t)0xa23f698, (q31_t)0x22922b5e, (q31_t)0xa2ac15b, (q31_t)0x229cbdfa, + (q31_t)0xa318e32, (q31_t)0x22a74f40, (q31_t)0xa385d1d, (q31_t)0x22b1df30, + (q31_t)0xa3f2e19, (q31_t)0x22bc6dca, (q31_t)0xa460129, (q31_t)0x22c6fb0c, + (q31_t)0xa4cd64b, (q31_t)0x22d186f8, (q31_t)0xa53ad7e, (q31_t)0x22dc118c, + (q31_t)0xa5a86c4, (q31_t)0x22e69ac8, (q31_t)0xa61621b, (q31_t)0x22f122ab, + (q31_t)0xa683f83, (q31_t)0x22fba936, (q31_t)0xa6f1efc, (q31_t)0x23062e67, + (q31_t)0xa760086, (q31_t)0x2310b23e, (q31_t)0xa7ce420, (q31_t)0x231b34bc, + (q31_t)0xa83c9ca, (q31_t)0x2325b5df, (q31_t)0xa8ab184, (q31_t)0x233035a7, + (q31_t)0xa919b4e, (q31_t)0x233ab414, (q31_t)0xa988727, (q31_t)0x23453125, + (q31_t)0xa9f750f, (q31_t)0x234facda, (q31_t)0xaa66506, (q31_t)0x235a2733, + (q31_t)0xaad570c, (q31_t)0x2364a02e, (q31_t)0xab44b1f, (q31_t)0x236f17cc, + (q31_t)0xabb4141, (q31_t)0x23798e0d, (q31_t)0xac23971, (q31_t)0x238402ef, + (q31_t)0xac933ae, (q31_t)0x238e7673, (q31_t)0xad02ff8, (q31_t)0x2398e898, + (q31_t)0xad72e4f, (q31_t)0x23a3595e, (q31_t)0xade2eb3, (q31_t)0x23adc8c4, + (q31_t)0xae53123, (q31_t)0x23b836ca, (q31_t)0xaec35a0, (q31_t)0x23c2a36f, + (q31_t)0xaf33c28, (q31_t)0x23cd0eb3, (q31_t)0xafa44bc, (q31_t)0x23d77896, + (q31_t)0xb014f5b, (q31_t)0x23e1e117, (q31_t)0xb085c05, (q31_t)0x23ec4837, + (q31_t)0xb0f6aba, (q31_t)0x23f6adf3, (q31_t)0xb167b79, (q31_t)0x2401124d, + (q31_t)0xb1d8e43, (q31_t)0x240b7543, (q31_t)0xb24a316, (q31_t)0x2415d6d5, + (q31_t)0xb2bb9f4, (q31_t)0x24203704, (q31_t)0xb32d2da, (q31_t)0x242a95ce, + (q31_t)0xb39edca, (q31_t)0x2434f332, (q31_t)0xb410ac3, (q31_t)0x243f4f32, + (q31_t)0xb4829c4, (q31_t)0x2449a9cc, (q31_t)0xb4f4acd, (q31_t)0x245402ff, + (q31_t)0xb566ddf, (q31_t)0x245e5acc, (q31_t)0xb5d92f8, (q31_t)0x2468b132, + (q31_t)0xb64ba19, (q31_t)0x24730631, (q31_t)0xb6be341, (q31_t)0x247d59c8, + (q31_t)0xb730e70, (q31_t)0x2487abf7, (q31_t)0xb7a3ba5, (q31_t)0x2491fcbe, + (q31_t)0xb816ae1, (q31_t)0x249c4c1b, (q31_t)0xb889c23, (q31_t)0x24a69a0f, + (q31_t)0xb8fcf6b, (q31_t)0x24b0e699, (q31_t)0xb9704b9, (q31_t)0x24bb31ba, + (q31_t)0xb9e3c0b, (q31_t)0x24c57b6f, (q31_t)0xba57563, (q31_t)0x24cfc3ba, + (q31_t)0xbacb0bf, (q31_t)0x24da0a9a, (q31_t)0xbb3ee20, (q31_t)0x24e4500e, + (q31_t)0xbbb2d85, (q31_t)0x24ee9415, (q31_t)0xbc26eee, (q31_t)0x24f8d6b0, + (q31_t)0xbc9b25a, (q31_t)0x250317df, (q31_t)0xbd0f7ca, (q31_t)0x250d57a0, + (q31_t)0xbd83f3d, (q31_t)0x251795f3, (q31_t)0xbdf88b3, (q31_t)0x2521d2d8, + (q31_t)0xbe6d42b, (q31_t)0x252c0e4f, (q31_t)0xbee21a5, (q31_t)0x25364857, + (q31_t)0xbf57121, (q31_t)0x254080ef, (q31_t)0xbfcc29f, (q31_t)0x254ab818, + (q31_t)0xc04161e, (q31_t)0x2554edd1, (q31_t)0xc0b6b9e, (q31_t)0x255f2219, + (q31_t)0xc12c31f, (q31_t)0x256954f1, (q31_t)0xc1a1ca0, (q31_t)0x25738657, + (q31_t)0xc217822, (q31_t)0x257db64c, (q31_t)0xc28d5a3, (q31_t)0x2587e4cf, + (q31_t)0xc303524, (q31_t)0x259211df, (q31_t)0xc3796a5, (q31_t)0x259c3d7c, + (q31_t)0xc3efa25, (q31_t)0x25a667a7, (q31_t)0xc465fa3, (q31_t)0x25b0905d, + (q31_t)0xc4dc720, (q31_t)0x25bab7a0, (q31_t)0xc55309b, (q31_t)0x25c4dd6e, + (q31_t)0xc5c9c14, (q31_t)0x25cf01c8, (q31_t)0xc64098b, (q31_t)0x25d924ac, + (q31_t)0xc6b78ff, (q31_t)0x25e3461b, (q31_t)0xc72ea70, (q31_t)0x25ed6614, + (q31_t)0xc7a5dde, (q31_t)0x25f78497, (q31_t)0xc81d349, (q31_t)0x2601a1a2, + (q31_t)0xc894aaf, (q31_t)0x260bbd37, (q31_t)0xc90c412, (q31_t)0x2615d754, + (q31_t)0xc983f70, (q31_t)0x261feffa, (q31_t)0xc9fbcca, (q31_t)0x262a0727, + (q31_t)0xca73c1e, (q31_t)0x26341cdb, (q31_t)0xcaebd6e, (q31_t)0x263e3117, + (q31_t)0xcb640b8, (q31_t)0x264843d9, (q31_t)0xcbdc5fc, (q31_t)0x26525521, + (q31_t)0xcc54d3a, (q31_t)0x265c64ef, (q31_t)0xcccd671, (q31_t)0x26667342, + (q31_t)0xcd461a2, (q31_t)0x2670801a, (q31_t)0xcdbeecc, (q31_t)0x267a8b77, + (q31_t)0xce37def, (q31_t)0x26849558, (q31_t)0xceb0f0a, (q31_t)0x268e9dbd, + (q31_t)0xcf2a21d, (q31_t)0x2698a4a6, (q31_t)0xcfa3729, (q31_t)0x26a2aa11, + (q31_t)0xd01ce2b, (q31_t)0x26acadff, (q31_t)0xd096725, (q31_t)0x26b6b070, + (q31_t)0xd110216, (q31_t)0x26c0b162, (q31_t)0xd189efe, (q31_t)0x26cab0d6, + (q31_t)0xd203ddc, (q31_t)0x26d4aecb, (q31_t)0xd27deb0, (q31_t)0x26deab41, + (q31_t)0xd2f817b, (q31_t)0x26e8a637, (q31_t)0xd37263a, (q31_t)0x26f29fad, + (q31_t)0xd3eccef, (q31_t)0x26fc97a3, (q31_t)0xd467599, (q31_t)0x27068e18, + (q31_t)0xd4e2037, (q31_t)0x2710830c, (q31_t)0xd55ccca, (q31_t)0x271a767e, + (q31_t)0xd5d7b50, (q31_t)0x2724686e, (q31_t)0xd652bcb, (q31_t)0x272e58dc, + (q31_t)0xd6cde39, (q31_t)0x273847c8, (q31_t)0xd74929a, (q31_t)0x27423530, + (q31_t)0xd7c48ee, (q31_t)0x274c2115, (q31_t)0xd840134, (q31_t)0x27560b76, + (q31_t)0xd8bbb6d, (q31_t)0x275ff452, (q31_t)0xd937798, (q31_t)0x2769dbaa, + (q31_t)0xd9b35b4, (q31_t)0x2773c17d, (q31_t)0xda2f5c2, (q31_t)0x277da5cb, + (q31_t)0xdaab7c0, (q31_t)0x27878893, (q31_t)0xdb27bb0, (q31_t)0x279169d5, + (q31_t)0xdba4190, (q31_t)0x279b4990, (q31_t)0xdc20960, (q31_t)0x27a527c4, + (q31_t)0xdc9d320, (q31_t)0x27af0472, (q31_t)0xdd19ed0, (q31_t)0x27b8df97, + (q31_t)0xdd96c6f, (q31_t)0x27c2b934, (q31_t)0xde13bfd, (q31_t)0x27cc9149, + (q31_t)0xde90d79, (q31_t)0x27d667d5, (q31_t)0xdf0e0e4, (q31_t)0x27e03cd8, + (q31_t)0xdf8b63d, (q31_t)0x27ea1052, (q31_t)0xe008d84, (q31_t)0x27f3e241, + (q31_t)0xe0866b8, (q31_t)0x27fdb2a7, (q31_t)0xe1041d9, (q31_t)0x28078181, + (q31_t)0xe181ee8, (q31_t)0x28114ed0, (q31_t)0xe1ffde2, (q31_t)0x281b1a94, + (q31_t)0xe27dec9, (q31_t)0x2824e4cc, (q31_t)0xe2fc19c, (q31_t)0x282ead78, + (q31_t)0xe37a65b, (q31_t)0x28387498, (q31_t)0xe3f8d05, (q31_t)0x28423a2a, + (q31_t)0xe47759a, (q31_t)0x284bfe2f, (q31_t)0xe4f6019, (q31_t)0x2855c0a6, + (q31_t)0xe574c84, (q31_t)0x285f8190, (q31_t)0xe5f3ad8, (q31_t)0x286940ea, + (q31_t)0xe672b16, (q31_t)0x2872feb6, (q31_t)0xe6f1d3d, (q31_t)0x287cbaf3, + (q31_t)0xe77114e, (q31_t)0x288675a0, (q31_t)0xe7f0748, (q31_t)0x28902ebd, + (q31_t)0xe86ff2a, (q31_t)0x2899e64a, (q31_t)0xe8ef8f4, (q31_t)0x28a39c46, + (q31_t)0xe96f4a7, (q31_t)0x28ad50b1, (q31_t)0xe9ef241, (q31_t)0x28b7038b, + (q31_t)0xea6f1c2, (q31_t)0x28c0b4d2, (q31_t)0xeaef32b, (q31_t)0x28ca6488, + (q31_t)0xeb6f67a, (q31_t)0x28d412ab, (q31_t)0xebefbb0, (q31_t)0x28ddbf3b, + (q31_t)0xec702cb, (q31_t)0x28e76a37, (q31_t)0xecf0bcd, (q31_t)0x28f113a0, + (q31_t)0xed716b4, (q31_t)0x28fabb75, (q31_t)0xedf2380, (q31_t)0x290461b5, + (q31_t)0xee73231, (q31_t)0x290e0661, (q31_t)0xeef42c7, (q31_t)0x2917a977, + (q31_t)0xef75541, (q31_t)0x29214af8, (q31_t)0xeff699f, (q31_t)0x292aeae3, + (q31_t)0xf077fe1, (q31_t)0x29348937, (q31_t)0xf0f9805, (q31_t)0x293e25f5, + (q31_t)0xf17b20d, (q31_t)0x2947c11c, (q31_t)0xf1fcdf8, (q31_t)0x29515aab, + (q31_t)0xf27ebc5, (q31_t)0x295af2a3, (q31_t)0xf300b74, (q31_t)0x29648902, + (q31_t)0xf382d05, (q31_t)0x296e1dc9, (q31_t)0xf405077, (q31_t)0x2977b0f7, + (q31_t)0xf4875ca, (q31_t)0x2981428c, (q31_t)0xf509cfe, (q31_t)0x298ad287, + (q31_t)0xf58c613, (q31_t)0x299460e8, (q31_t)0xf60f108, (q31_t)0x299dedaf, + (q31_t)0xf691ddd, (q31_t)0x29a778db, (q31_t)0xf714c91, (q31_t)0x29b1026c, + (q31_t)0xf797d24, (q31_t)0x29ba8a61, (q31_t)0xf81af97, (q31_t)0x29c410ba, + (q31_t)0xf89e3e8, (q31_t)0x29cd9578, (q31_t)0xf921a17, (q31_t)0x29d71899, + (q31_t)0xf9a5225, (q31_t)0x29e09a1c, (q31_t)0xfa28c10, (q31_t)0x29ea1a03, + (q31_t)0xfaac7d8, (q31_t)0x29f3984c, (q31_t)0xfb3057d, (q31_t)0x29fd14f6, + (q31_t)0xfbb4500, (q31_t)0x2a069003, (q31_t)0xfc3865e, (q31_t)0x2a100970, + (q31_t)0xfcbc999, (q31_t)0x2a19813f, (q31_t)0xfd40eaf, (q31_t)0x2a22f76e, + (q31_t)0xfdc55a1, (q31_t)0x2a2c6bfd, (q31_t)0xfe49e6d, (q31_t)0x2a35deeb, + (q31_t)0xfece915, (q31_t)0x2a3f503a, (q31_t)0xff53597, (q31_t)0x2a48bfe7, + (q31_t)0xffd83f4, (q31_t)0x2a522df3, (q31_t)0x1005d42a, (q31_t)0x2a5b9a5d, + (q31_t)0x100e2639, (q31_t)0x2a650525, (q31_t)0x10167a22, (q31_t)0x2a6e6e4b, + (q31_t)0x101ecfe4, (q31_t)0x2a77d5ce, (q31_t)0x1027277e, (q31_t)0x2a813bae, + (q31_t)0x102f80f1, (q31_t)0x2a8a9fea, (q31_t)0x1037dc3b, (q31_t)0x2a940283, + (q31_t)0x1040395d, (q31_t)0x2a9d6377, (q31_t)0x10489856, (q31_t)0x2aa6c2c6, + (q31_t)0x1050f926, (q31_t)0x2ab02071, (q31_t)0x10595bcd, (q31_t)0x2ab97c77, + (q31_t)0x1061c04a, (q31_t)0x2ac2d6d6, (q31_t)0x106a269d, (q31_t)0x2acc2f90, + (q31_t)0x10728ec6, (q31_t)0x2ad586a3, (q31_t)0x107af8c4, (q31_t)0x2adedc10, + (q31_t)0x10836497, (q31_t)0x2ae82fd5, (q31_t)0x108bd23f, (q31_t)0x2af181f3, + (q31_t)0x109441bb, (q31_t)0x2afad269, (q31_t)0x109cb30b, (q31_t)0x2b042137, + (q31_t)0x10a5262f, (q31_t)0x2b0d6e5c, (q31_t)0x10ad9b26, (q31_t)0x2b16b9d9, + (q31_t)0x10b611f1, (q31_t)0x2b2003ac, (q31_t)0x10be8a8d, (q31_t)0x2b294bd5, + (q31_t)0x10c704fd, (q31_t)0x2b329255, (q31_t)0x10cf813e, (q31_t)0x2b3bd72a, + (q31_t)0x10d7ff51, (q31_t)0x2b451a55, (q31_t)0x10e07f36, (q31_t)0x2b4e5bd4, + (q31_t)0x10e900ec, (q31_t)0x2b579ba8, (q31_t)0x10f18472, (q31_t)0x2b60d9d0, + (q31_t)0x10fa09c9, (q31_t)0x2b6a164d, (q31_t)0x110290f0, (q31_t)0x2b73511c, + (q31_t)0x110b19e7, (q31_t)0x2b7c8a3f, (q31_t)0x1113a4ad, (q31_t)0x2b85c1b5, + (q31_t)0x111c3142, (q31_t)0x2b8ef77d, (q31_t)0x1124bfa6, (q31_t)0x2b982b97, + (q31_t)0x112d4fd9, (q31_t)0x2ba15e03, (q31_t)0x1135e1d9, (q31_t)0x2baa8ec0, + (q31_t)0x113e75a8, (q31_t)0x2bb3bdce, (q31_t)0x11470b44, (q31_t)0x2bbceb2d, + (q31_t)0x114fa2ad, (q31_t)0x2bc616dd, (q31_t)0x11583be2, (q31_t)0x2bcf40dc, + (q31_t)0x1160d6e5, (q31_t)0x2bd8692b, (q31_t)0x116973b3, (q31_t)0x2be18fc9, + (q31_t)0x1172124d, (q31_t)0x2beab4b6, (q31_t)0x117ab2b3, (q31_t)0x2bf3d7f2, + (q31_t)0x118354e4, (q31_t)0x2bfcf97c, (q31_t)0x118bf8e0, (q31_t)0x2c061953, + (q31_t)0x11949ea6, (q31_t)0x2c0f3779, (q31_t)0x119d4636, (q31_t)0x2c1853eb, + (q31_t)0x11a5ef90, (q31_t)0x2c216eaa, (q31_t)0x11ae9ab4, (q31_t)0x2c2a87b6, + (q31_t)0x11b747a0, (q31_t)0x2c339f0e, (q31_t)0x11bff656, (q31_t)0x2c3cb4b1, + (q31_t)0x11c8a6d4, (q31_t)0x2c45c8a0, (q31_t)0x11d1591a, (q31_t)0x2c4edada, + (q31_t)0x11da0d28, (q31_t)0x2c57eb5e, (q31_t)0x11e2c2fd, (q31_t)0x2c60fa2d, + (q31_t)0x11eb7a9a, (q31_t)0x2c6a0746, (q31_t)0x11f433fd, (q31_t)0x2c7312a9, + (q31_t)0x11fcef27, (q31_t)0x2c7c1c55, (q31_t)0x1205ac17, (q31_t)0x2c85244a, + (q31_t)0x120e6acc, (q31_t)0x2c8e2a87, (q31_t)0x12172b48, (q31_t)0x2c972f0d, + (q31_t)0x121fed88, (q31_t)0x2ca031da, (q31_t)0x1228b18d, (q31_t)0x2ca932ef, + (q31_t)0x12317756, (q31_t)0x2cb2324c, (q31_t)0x123a3ee4, (q31_t)0x2cbb2fef, + (q31_t)0x12430835, (q31_t)0x2cc42bd9, (q31_t)0x124bd34a, (q31_t)0x2ccd2609, + (q31_t)0x1254a021, (q31_t)0x2cd61e7f, (q31_t)0x125d6ebc, (q31_t)0x2cdf153a, + (q31_t)0x12663f19, (q31_t)0x2ce80a3a, (q31_t)0x126f1138, (q31_t)0x2cf0fd80, + (q31_t)0x1277e518, (q31_t)0x2cf9ef09, (q31_t)0x1280babb, (q31_t)0x2d02ded7, + (q31_t)0x1289921e, (q31_t)0x2d0bcce8, (q31_t)0x12926b41, (q31_t)0x2d14b93d, + (q31_t)0x129b4626, (q31_t)0x2d1da3d5, (q31_t)0x12a422ca, (q31_t)0x2d268cb0, + (q31_t)0x12ad012e, (q31_t)0x2d2f73cd, (q31_t)0x12b5e151, (q31_t)0x2d38592c, + (q31_t)0x12bec333, (q31_t)0x2d413ccd, (q31_t)0x12c7a6d4, (q31_t)0x2d4a1eaf, + (q31_t)0x12d08c33, (q31_t)0x2d52fed2, (q31_t)0x12d97350, (q31_t)0x2d5bdd36, + (q31_t)0x12e25c2b, (q31_t)0x2d64b9da, (q31_t)0x12eb46c3, (q31_t)0x2d6d94bf, + (q31_t)0x12f43318, (q31_t)0x2d766de2, (q31_t)0x12fd2129, (q31_t)0x2d7f4545, + (q31_t)0x130610f7, (q31_t)0x2d881ae8, (q31_t)0x130f0280, (q31_t)0x2d90eec8, + (q31_t)0x1317f5c6, (q31_t)0x2d99c0e7, (q31_t)0x1320eac6, (q31_t)0x2da29144, + (q31_t)0x1329e181, (q31_t)0x2dab5fdf, (q31_t)0x1332d9f7, (q31_t)0x2db42cb6, + (q31_t)0x133bd427, (q31_t)0x2dbcf7cb, (q31_t)0x1344d011, (q31_t)0x2dc5c11c, + (q31_t)0x134dcdb4, (q31_t)0x2dce88aa, (q31_t)0x1356cd11, (q31_t)0x2dd74e73, + (q31_t)0x135fce26, (q31_t)0x2de01278, (q31_t)0x1368d0f3, (q31_t)0x2de8d4b8, + (q31_t)0x1371d579, (q31_t)0x2df19534, (q31_t)0x137adbb6, (q31_t)0x2dfa53e9, + (q31_t)0x1383e3ab, (q31_t)0x2e0310d9, (q31_t)0x138ced57, (q31_t)0x2e0bcc03, + (q31_t)0x1395f8ba, (q31_t)0x2e148566, (q31_t)0x139f05d3, (q31_t)0x2e1d3d03, + (q31_t)0x13a814a2, (q31_t)0x2e25f2d8, (q31_t)0x13b12526, (q31_t)0x2e2ea6e6, + (q31_t)0x13ba3760, (q31_t)0x2e37592c, (q31_t)0x13c34b4f, (q31_t)0x2e4009aa, + (q31_t)0x13cc60f2, (q31_t)0x2e48b860, (q31_t)0x13d5784a, (q31_t)0x2e51654c, + (q31_t)0x13de9156, (q31_t)0x2e5a1070, (q31_t)0x13e7ac15, (q31_t)0x2e62b9ca, + (q31_t)0x13f0c887, (q31_t)0x2e6b615a, (q31_t)0x13f9e6ad, (q31_t)0x2e740720, + (q31_t)0x14030684, (q31_t)0x2e7cab1c, (q31_t)0x140c280e, (q31_t)0x2e854d4d, + (q31_t)0x14154b4a, (q31_t)0x2e8dedb3, (q31_t)0x141e7037, (q31_t)0x2e968c4d, + (q31_t)0x142796d5, (q31_t)0x2e9f291b, (q31_t)0x1430bf24, (q31_t)0x2ea7c41e, + (q31_t)0x1439e923, (q31_t)0x2eb05d53, (q31_t)0x144314d3, (q31_t)0x2eb8f4bc, + (q31_t)0x144c4232, (q31_t)0x2ec18a58, (q31_t)0x14557140, (q31_t)0x2eca1e27, + (q31_t)0x145ea1fd, (q31_t)0x2ed2b027, (q31_t)0x1467d469, (q31_t)0x2edb405a, + (q31_t)0x14710883, (q31_t)0x2ee3cebe, (q31_t)0x147a3e4b, (q31_t)0x2eec5b53, + (q31_t)0x148375c1, (q31_t)0x2ef4e619, (q31_t)0x148caee4, (q31_t)0x2efd6f10, + (q31_t)0x1495e9b3, (q31_t)0x2f05f637, (q31_t)0x149f2630, (q31_t)0x2f0e7b8e, + (q31_t)0x14a86458, (q31_t)0x2f16ff14, (q31_t)0x14b1a42c, (q31_t)0x2f1f80ca, + (q31_t)0x14bae5ab, (q31_t)0x2f2800af, (q31_t)0x14c428d6, (q31_t)0x2f307ec2, + (q31_t)0x14cd6dab, (q31_t)0x2f38fb03, (q31_t)0x14d6b42b, (q31_t)0x2f417573, + (q31_t)0x14dffc54, (q31_t)0x2f49ee0f, (q31_t)0x14e94627, (q31_t)0x2f5264da, + (q31_t)0x14f291a4, (q31_t)0x2f5ad9d1, (q31_t)0x14fbdec9, (q31_t)0x2f634cf5, + (q31_t)0x15052d97, (q31_t)0x2f6bbe45, (q31_t)0x150e7e0d, (q31_t)0x2f742dc1, + (q31_t)0x1517d02b, (q31_t)0x2f7c9b69, (q31_t)0x152123f0, (q31_t)0x2f85073c, + (q31_t)0x152a795d, (q31_t)0x2f8d713a, (q31_t)0x1533d070, (q31_t)0x2f95d963, + (q31_t)0x153d292a, (q31_t)0x2f9e3fb6, (q31_t)0x15468389, (q31_t)0x2fa6a433, + (q31_t)0x154fdf8f, (q31_t)0x2faf06da, (q31_t)0x15593d3a, (q31_t)0x2fb767aa, + (q31_t)0x15629c89, (q31_t)0x2fbfc6a3, (q31_t)0x156bfd7d, (q31_t)0x2fc823c5, + (q31_t)0x15756016, (q31_t)0x2fd07f0f, (q31_t)0x157ec452, (q31_t)0x2fd8d882, + (q31_t)0x15882a32, (q31_t)0x2fe1301c, (q31_t)0x159191b5, (q31_t)0x2fe985de, + (q31_t)0x159afadb, (q31_t)0x2ff1d9c7, (q31_t)0x15a465a3, (q31_t)0x2ffa2bd6, + (q31_t)0x15add20d, (q31_t)0x30027c0c, (q31_t)0x15b74019, (q31_t)0x300aca69, + (q31_t)0x15c0afc6, (q31_t)0x301316eb, (q31_t)0x15ca2115, (q31_t)0x301b6193, + (q31_t)0x15d39403, (q31_t)0x3023aa5f, (q31_t)0x15dd0892, (q31_t)0x302bf151, + (q31_t)0x15e67ec1, (q31_t)0x30343667, (q31_t)0x15eff690, (q31_t)0x303c79a2, + (q31_t)0x15f96ffd, (q31_t)0x3044bb00, (q31_t)0x1602eb0a, (q31_t)0x304cfa83, + (q31_t)0x160c67b4, (q31_t)0x30553828, (q31_t)0x1615e5fd, (q31_t)0x305d73f0, + (q31_t)0x161f65e4, (q31_t)0x3065addb, (q31_t)0x1628e767, (q31_t)0x306de5e9, + (q31_t)0x16326a88, (q31_t)0x30761c18, (q31_t)0x163bef46, (q31_t)0x307e5069, + (q31_t)0x1645759f, (q31_t)0x308682dc, (q31_t)0x164efd94, (q31_t)0x308eb36f, + (q31_t)0x16588725, (q31_t)0x3096e223, (q31_t)0x16621251, (q31_t)0x309f0ef8, + (q31_t)0x166b9f18, (q31_t)0x30a739ed, (q31_t)0x16752d79, (q31_t)0x30af6302, + (q31_t)0x167ebd74, (q31_t)0x30b78a36, (q31_t)0x16884f09, (q31_t)0x30bfaf89, + (q31_t)0x1691e237, (q31_t)0x30c7d2fb, (q31_t)0x169b76fe, (q31_t)0x30cff48c, + (q31_t)0x16a50d5d, (q31_t)0x30d8143b, (q31_t)0x16aea555, (q31_t)0x30e03208, + (q31_t)0x16b83ee4, (q31_t)0x30e84df3, (q31_t)0x16c1da0b, (q31_t)0x30f067fb, + (q31_t)0x16cb76c9, (q31_t)0x30f8801f, (q31_t)0x16d5151d, (q31_t)0x31009661, + (q31_t)0x16deb508, (q31_t)0x3108aabf, (q31_t)0x16e85689, (q31_t)0x3110bd39, + (q31_t)0x16f1f99f, (q31_t)0x3118cdcf, (q31_t)0x16fb9e4b, (q31_t)0x3120dc80, + (q31_t)0x1705448b, (q31_t)0x3128e94c, (q31_t)0x170eec60, (q31_t)0x3130f433, + (q31_t)0x171895c9, (q31_t)0x3138fd35, (q31_t)0x172240c5, (q31_t)0x31410450, + (q31_t)0x172bed55, (q31_t)0x31490986, (q31_t)0x17359b78, (q31_t)0x31510cd5, + (q31_t)0x173f4b2e, (q31_t)0x31590e3e, (q31_t)0x1748fc75, (q31_t)0x31610dbf, + (q31_t)0x1752af4f, (q31_t)0x31690b59, (q31_t)0x175c63ba, (q31_t)0x3171070c, + (q31_t)0x176619b6, (q31_t)0x317900d6, (q31_t)0x176fd143, (q31_t)0x3180f8b8, + (q31_t)0x17798a60, (q31_t)0x3188eeb2, (q31_t)0x1783450d, (q31_t)0x3190e2c3, + (q31_t)0x178d014a, (q31_t)0x3198d4ea, (q31_t)0x1796bf16, (q31_t)0x31a0c528, + (q31_t)0x17a07e70, (q31_t)0x31a8b37c, (q31_t)0x17aa3f5a, (q31_t)0x31b09fe7, + (q31_t)0x17b401d1, (q31_t)0x31b88a66, (q31_t)0x17bdc5d6, (q31_t)0x31c072fb, + (q31_t)0x17c78b68, (q31_t)0x31c859a5, (q31_t)0x17d15288, (q31_t)0x31d03e64, + (q31_t)0x17db1b34, (q31_t)0x31d82137, (q31_t)0x17e4e56c, (q31_t)0x31e0021e, + (q31_t)0x17eeb130, (q31_t)0x31e7e118, (q31_t)0x17f87e7f, (q31_t)0x31efbe27, + (q31_t)0x18024d59, (q31_t)0x31f79948, (q31_t)0x180c1dbf, (q31_t)0x31ff727c, + (q31_t)0x1815efae, (q31_t)0x320749c3, (q31_t)0x181fc328, (q31_t)0x320f1f1c, + (q31_t)0x1829982b, (q31_t)0x3216f287, (q31_t)0x18336eb7, (q31_t)0x321ec403, + (q31_t)0x183d46cc, (q31_t)0x32269391, (q31_t)0x18472069, (q31_t)0x322e6130, + (q31_t)0x1850fb8e, (q31_t)0x32362ce0, (q31_t)0x185ad83c, (q31_t)0x323df6a0, + (q31_t)0x1864b670, (q31_t)0x3245be70, (q31_t)0x186e962b, (q31_t)0x324d8450, + (q31_t)0x1878776d, (q31_t)0x32554840, (q31_t)0x18825a35, (q31_t)0x325d0a3e, + (q31_t)0x188c3e83, (q31_t)0x3264ca4c, (q31_t)0x18962456, (q31_t)0x326c8868, + (q31_t)0x18a00bae, (q31_t)0x32744493, (q31_t)0x18a9f48a, (q31_t)0x327bfecc, + (q31_t)0x18b3deeb, (q31_t)0x3283b712, (q31_t)0x18bdcad0, (q31_t)0x328b6d66, + (q31_t)0x18c7b838, (q31_t)0x329321c7, (q31_t)0x18d1a724, (q31_t)0x329ad435, + (q31_t)0x18db9792, (q31_t)0x32a284b0, (q31_t)0x18e58982, (q31_t)0x32aa3336, + (q31_t)0x18ef7cf4, (q31_t)0x32b1dfc9, (q31_t)0x18f971e8, (q31_t)0x32b98a67, + (q31_t)0x1903685d, (q31_t)0x32c13311, (q31_t)0x190d6053, (q31_t)0x32c8d9c6, + (q31_t)0x191759c9, (q31_t)0x32d07e85, (q31_t)0x192154bf, (q31_t)0x32d82150, + (q31_t)0x192b5135, (q31_t)0x32dfc224, (q31_t)0x19354f2a, (q31_t)0x32e76102, + (q31_t)0x193f4e9e, (q31_t)0x32eefdea, (q31_t)0x19494f90, (q31_t)0x32f698db, + (q31_t)0x19535201, (q31_t)0x32fe31d5, (q31_t)0x195d55ef, (q31_t)0x3305c8d7, + (q31_t)0x19675b5a, (q31_t)0x330d5de3, (q31_t)0x19716243, (q31_t)0x3314f0f6, + (q31_t)0x197b6aa8, (q31_t)0x331c8211, (q31_t)0x19857489, (q31_t)0x33241134, + (q31_t)0x198f7fe6, (q31_t)0x332b9e5e, (q31_t)0x19998cbe, (q31_t)0x3333298f, + (q31_t)0x19a39b11, (q31_t)0x333ab2c6, (q31_t)0x19adaadf, (q31_t)0x33423a04, + (q31_t)0x19b7bc27, (q31_t)0x3349bf48, (q31_t)0x19c1cee9, (q31_t)0x33514292, + (q31_t)0x19cbe325, (q31_t)0x3358c3e2, (q31_t)0x19d5f8d9, (q31_t)0x33604336, + (q31_t)0x19e01006, (q31_t)0x3367c090, (q31_t)0x19ea28ac, (q31_t)0x336f3bee, + (q31_t)0x19f442c9, (q31_t)0x3376b551, (q31_t)0x19fe5e5e, (q31_t)0x337e2cb7, + (q31_t)0x1a087b69, (q31_t)0x3385a222, (q31_t)0x1a1299ec, (q31_t)0x338d1590, + (q31_t)0x1a1cb9e5, (q31_t)0x33948701, (q31_t)0x1a26db54, (q31_t)0x339bf675, + (q31_t)0x1a30fe38, (q31_t)0x33a363ec, (q31_t)0x1a3b2292, (q31_t)0x33aacf65, + (q31_t)0x1a454860, (q31_t)0x33b238e0, (q31_t)0x1a4f6fa3, (q31_t)0x33b9a05d, + (q31_t)0x1a599859, (q31_t)0x33c105db, (q31_t)0x1a63c284, (q31_t)0x33c8695b, + (q31_t)0x1a6dee21, (q31_t)0x33cfcadc, (q31_t)0x1a781b31, (q31_t)0x33d72a5d, + (q31_t)0x1a8249b4, (q31_t)0x33de87de, (q31_t)0x1a8c79a9, (q31_t)0x33e5e360, + (q31_t)0x1a96ab0f, (q31_t)0x33ed3ce1, (q31_t)0x1aa0dde7, (q31_t)0x33f49462, + (q31_t)0x1aab122f, (q31_t)0x33fbe9e2, (q31_t)0x1ab547e8, (q31_t)0x34033d61, + (q31_t)0x1abf7f11, (q31_t)0x340a8edf, (q31_t)0x1ac9b7a9, (q31_t)0x3411de5b, + (q31_t)0x1ad3f1b1, (q31_t)0x34192bd5, (q31_t)0x1ade2d28, (q31_t)0x3420774d, + (q31_t)0x1ae86a0d, (q31_t)0x3427c0c3, (q31_t)0x1af2a860, (q31_t)0x342f0836, + (q31_t)0x1afce821, (q31_t)0x34364da6, (q31_t)0x1b072950, (q31_t)0x343d9112, + (q31_t)0x1b116beb, (q31_t)0x3444d27b, (q31_t)0x1b1baff2, (q31_t)0x344c11e0, + (q31_t)0x1b25f566, (q31_t)0x34534f41, (q31_t)0x1b303c46, (q31_t)0x345a8a9d, + (q31_t)0x1b3a8491, (q31_t)0x3461c3f5, (q31_t)0x1b44ce46, (q31_t)0x3468fb47, + (q31_t)0x1b4f1967, (q31_t)0x34703095, (q31_t)0x1b5965f1, (q31_t)0x347763dd, + (q31_t)0x1b63b3e5, (q31_t)0x347e951f, (q31_t)0x1b6e0342, (q31_t)0x3485c45b, + (q31_t)0x1b785409, (q31_t)0x348cf190, (q31_t)0x1b82a638, (q31_t)0x34941cbf, + (q31_t)0x1b8cf9cf, (q31_t)0x349b45e7, (q31_t)0x1b974ece, (q31_t)0x34a26d08, + (q31_t)0x1ba1a534, (q31_t)0x34a99221, (q31_t)0x1babfd01, (q31_t)0x34b0b533, + (q31_t)0x1bb65634, (q31_t)0x34b7d63c, (q31_t)0x1bc0b0ce, (q31_t)0x34bef53d, + (q31_t)0x1bcb0cce, (q31_t)0x34c61236, (q31_t)0x1bd56a32, (q31_t)0x34cd2d26, + (q31_t)0x1bdfc8fc, (q31_t)0x34d4460c, (q31_t)0x1bea292b, (q31_t)0x34db5cea, + (q31_t)0x1bf48abd, (q31_t)0x34e271bd, (q31_t)0x1bfeedb3, (q31_t)0x34e98487, + (q31_t)0x1c09520d, (q31_t)0x34f09546, (q31_t)0x1c13b7c9, (q31_t)0x34f7a3fb, + (q31_t)0x1c1e1ee9, (q31_t)0x34feb0a5, (q31_t)0x1c28876a, (q31_t)0x3505bb44, + (q31_t)0x1c32f14d, (q31_t)0x350cc3d8, (q31_t)0x1c3d5c91, (q31_t)0x3513ca60, + (q31_t)0x1c47c936, (q31_t)0x351acedd, (q31_t)0x1c52373c, (q31_t)0x3521d14d, + (q31_t)0x1c5ca6a2, (q31_t)0x3528d1b1, (q31_t)0x1c671768, (q31_t)0x352fd008, + (q31_t)0x1c71898d, (q31_t)0x3536cc52, (q31_t)0x1c7bfd11, (q31_t)0x353dc68f, + (q31_t)0x1c8671f3, (q31_t)0x3544bebf, (q31_t)0x1c90e834, (q31_t)0x354bb4e1, + (q31_t)0x1c9b5fd2, (q31_t)0x3552a8f4, (q31_t)0x1ca5d8cd, (q31_t)0x35599afa, + (q31_t)0x1cb05326, (q31_t)0x35608af1, (q31_t)0x1cbacedb, (q31_t)0x356778d9, + (q31_t)0x1cc54bec, (q31_t)0x356e64b2, (q31_t)0x1ccfca59, (q31_t)0x35754e7c, + (q31_t)0x1cda4a21, (q31_t)0x357c3636, (q31_t)0x1ce4cb44, (q31_t)0x35831be0, + (q31_t)0x1cef4dc2, (q31_t)0x3589ff7a, (q31_t)0x1cf9d199, (q31_t)0x3590e104, + (q31_t)0x1d0456ca, (q31_t)0x3597c07d, (q31_t)0x1d0edd55, (q31_t)0x359e9de5, + (q31_t)0x1d196538, (q31_t)0x35a5793c, (q31_t)0x1d23ee74, (q31_t)0x35ac5282, + (q31_t)0x1d2e7908, (q31_t)0x35b329b5, (q31_t)0x1d3904f4, (q31_t)0x35b9fed7, + (q31_t)0x1d439236, (q31_t)0x35c0d1e7, (q31_t)0x1d4e20d0, (q31_t)0x35c7a2e3, + (q31_t)0x1d58b0c0, (q31_t)0x35ce71ce, (q31_t)0x1d634206, (q31_t)0x35d53ea5, + (q31_t)0x1d6dd4a2, (q31_t)0x35dc0968, (q31_t)0x1d786892, (q31_t)0x35e2d219, + (q31_t)0x1d82fdd8, (q31_t)0x35e998b5, (q31_t)0x1d8d9472, (q31_t)0x35f05d3d, + (q31_t)0x1d982c60, (q31_t)0x35f71fb1, (q31_t)0x1da2c5a2, (q31_t)0x35fde011, + (q31_t)0x1dad6036, (q31_t)0x36049e5b, (q31_t)0x1db7fc1e, (q31_t)0x360b5a90, + (q31_t)0x1dc29958, (q31_t)0x361214b0, (q31_t)0x1dcd37e4, (q31_t)0x3618ccba, + (q31_t)0x1dd7d7c1, (q31_t)0x361f82af, (q31_t)0x1de278ef, (q31_t)0x3626368d, + (q31_t)0x1ded1b6e, (q31_t)0x362ce855, (q31_t)0x1df7bf3e, (q31_t)0x36339806, + (q31_t)0x1e02645d, (q31_t)0x363a45a0, (q31_t)0x1e0d0acc, (q31_t)0x3640f123, + (q31_t)0x1e17b28a, (q31_t)0x36479a8e, (q31_t)0x1e225b96, (q31_t)0x364e41e2, + (q31_t)0x1e2d05f1, (q31_t)0x3654e71d, (q31_t)0x1e37b199, (q31_t)0x365b8a41, + (q31_t)0x1e425e8f, (q31_t)0x36622b4c, (q31_t)0x1e4d0cd2, (q31_t)0x3668ca3e, + (q31_t)0x1e57bc62, (q31_t)0x366f6717, (q31_t)0x1e626d3e, (q31_t)0x367601d7, + (q31_t)0x1e6d1f65, (q31_t)0x367c9a7e, (q31_t)0x1e77d2d8, (q31_t)0x3683310b, + (q31_t)0x1e828796, (q31_t)0x3689c57d, (q31_t)0x1e8d3d9e, (q31_t)0x369057d6, + (q31_t)0x1e97f4f1, (q31_t)0x3696e814, (q31_t)0x1ea2ad8d, (q31_t)0x369d7637, + (q31_t)0x1ead6773, (q31_t)0x36a4023f, (q31_t)0x1eb822a1, (q31_t)0x36aa8c2c, + (q31_t)0x1ec2df18, (q31_t)0x36b113fd, (q31_t)0x1ecd9cd7, (q31_t)0x36b799b3, + (q31_t)0x1ed85bdd, (q31_t)0x36be1d4c, (q31_t)0x1ee31c2b, (q31_t)0x36c49ec9, + (q31_t)0x1eedddc0, (q31_t)0x36cb1e2a, (q31_t)0x1ef8a09b, (q31_t)0x36d19b6e, + (q31_t)0x1f0364bc, (q31_t)0x36d81695, (q31_t)0x1f0e2a22, (q31_t)0x36de8f9e, + (q31_t)0x1f18f0ce, (q31_t)0x36e5068a, (q31_t)0x1f23b8be, (q31_t)0x36eb7b58, + (q31_t)0x1f2e81f3, (q31_t)0x36f1ee09, (q31_t)0x1f394c6b, (q31_t)0x36f85e9a, + (q31_t)0x1f441828, (q31_t)0x36fecd0e, (q31_t)0x1f4ee527, (q31_t)0x37053962, + (q31_t)0x1f59b369, (q31_t)0x370ba398, (q31_t)0x1f6482ed, (q31_t)0x37120bae, + (q31_t)0x1f6f53b3, (q31_t)0x371871a5, (q31_t)0x1f7a25ba, (q31_t)0x371ed57c, + (q31_t)0x1f84f902, (q31_t)0x37253733, (q31_t)0x1f8fcd8b, (q31_t)0x372b96ca, + (q31_t)0x1f9aa354, (q31_t)0x3731f440, (q31_t)0x1fa57a5d, (q31_t)0x37384f95, + (q31_t)0x1fb052a5, (q31_t)0x373ea8ca, (q31_t)0x1fbb2c2c, (q31_t)0x3744ffdd, + (q31_t)0x1fc606f1, (q31_t)0x374b54ce, (q31_t)0x1fd0e2f5, (q31_t)0x3751a79e, + (q31_t)0x1fdbc036, (q31_t)0x3757f84c, (q31_t)0x1fe69eb4, (q31_t)0x375e46d8, + (q31_t)0x1ff17e70, (q31_t)0x37649341, (q31_t)0x1ffc5f67, (q31_t)0x376add88, + (q31_t)0x2007419b, (q31_t)0x377125ac, (q31_t)0x2012250a, (q31_t)0x37776bac, + (q31_t)0x201d09b4, (q31_t)0x377daf89, (q31_t)0x2027ef99, (q31_t)0x3783f143, + (q31_t)0x2032d6b8, (q31_t)0x378a30d8, (q31_t)0x203dbf11, (q31_t)0x37906e49, + (q31_t)0x2048a8a4, (q31_t)0x3796a996, (q31_t)0x2053936f, (q31_t)0x379ce2be, + (q31_t)0x205e7f74, (q31_t)0x37a319c2, (q31_t)0x20696cb0, (q31_t)0x37a94ea0, + (q31_t)0x20745b24, (q31_t)0x37af8159, (q31_t)0x207f4acf, (q31_t)0x37b5b1ec, + (q31_t)0x208a3bb2, (q31_t)0x37bbe05a, (q31_t)0x20952dcb, (q31_t)0x37c20ca1, + (q31_t)0x20a0211a, (q31_t)0x37c836c2, (q31_t)0x20ab159e, (q31_t)0x37ce5ebd, + (q31_t)0x20b60b58, (q31_t)0x37d48490, (q31_t)0x20c10247, (q31_t)0x37daa83d, + (q31_t)0x20cbfa6a, (q31_t)0x37e0c9c3, (q31_t)0x20d6f3c1, (q31_t)0x37e6e921, + (q31_t)0x20e1ee4b, (q31_t)0x37ed0657, (q31_t)0x20ecea09, (q31_t)0x37f32165, + (q31_t)0x20f7e6f9, (q31_t)0x37f93a4b, (q31_t)0x2102e51c, (q31_t)0x37ff5109, + (q31_t)0x210de470, (q31_t)0x3805659e, (q31_t)0x2118e4f6, (q31_t)0x380b780a, + (q31_t)0x2123e6ad, (q31_t)0x3811884d, (q31_t)0x212ee995, (q31_t)0x38179666, + (q31_t)0x2139edac, (q31_t)0x381da256, (q31_t)0x2144f2f3, (q31_t)0x3823ac1d, + (q31_t)0x214ff96a, (q31_t)0x3829b3b9, (q31_t)0x215b0110, (q31_t)0x382fb92a, + (q31_t)0x216609e3, (q31_t)0x3835bc71, (q31_t)0x217113e5, (q31_t)0x383bbd8e, + (q31_t)0x217c1f15, (q31_t)0x3841bc7f, (q31_t)0x21872b72, (q31_t)0x3847b946, + (q31_t)0x219238fb, (q31_t)0x384db3e0, (q31_t)0x219d47b1, (q31_t)0x3853ac4f, + (q31_t)0x21a85793, (q31_t)0x3859a292, (q31_t)0x21b368a0, (q31_t)0x385f96a9, + (q31_t)0x21be7ad8, (q31_t)0x38658894, (q31_t)0x21c98e3b, (q31_t)0x386b7852, + (q31_t)0x21d4a2c8, (q31_t)0x387165e3, (q31_t)0x21dfb87f, (q31_t)0x38775147, + (q31_t)0x21eacf5f, (q31_t)0x387d3a7e, (q31_t)0x21f5e768, (q31_t)0x38832187, + (q31_t)0x22010099, (q31_t)0x38890663, (q31_t)0x220c1af3, (q31_t)0x388ee910, + (q31_t)0x22173674, (q31_t)0x3894c98f, (q31_t)0x2222531c, (q31_t)0x389aa7e0, + (q31_t)0x222d70eb, (q31_t)0x38a08402, (q31_t)0x22388fe1, (q31_t)0x38a65df6, + (q31_t)0x2243affc, (q31_t)0x38ac35ba, (q31_t)0x224ed13d, (q31_t)0x38b20b4f, + (q31_t)0x2259f3a3, (q31_t)0x38b7deb4, (q31_t)0x2265172e, (q31_t)0x38bdafea, + (q31_t)0x22703bdc, (q31_t)0x38c37eef, (q31_t)0x227b61af, (q31_t)0x38c94bc4, + (q31_t)0x228688a4, (q31_t)0x38cf1669, (q31_t)0x2291b0bd, (q31_t)0x38d4dedd, + (q31_t)0x229cd9f8, (q31_t)0x38daa520, (q31_t)0x22a80456, (q31_t)0x38e06932, + (q31_t)0x22b32fd4, (q31_t)0x38e62b13, (q31_t)0x22be5c74, (q31_t)0x38ebeac2, + (q31_t)0x22c98a35, (q31_t)0x38f1a840, (q31_t)0x22d4b916, (q31_t)0x38f7638b, + (q31_t)0x22dfe917, (q31_t)0x38fd1ca4, (q31_t)0x22eb1a37, (q31_t)0x3902d38b, + (q31_t)0x22f64c77, (q31_t)0x3908883f, (q31_t)0x23017fd5, (q31_t)0x390e3ac0, + (q31_t)0x230cb451, (q31_t)0x3913eb0e, (q31_t)0x2317e9eb, (q31_t)0x39199929, + (q31_t)0x232320a2, (q31_t)0x391f4510, (q31_t)0x232e5876, (q31_t)0x3924eec3, + (q31_t)0x23399167, (q31_t)0x392a9642, (q31_t)0x2344cb73, (q31_t)0x39303b8e, + (q31_t)0x2350069b, (q31_t)0x3935dea4, (q31_t)0x235b42df, (q31_t)0x393b7f86, + (q31_t)0x2366803c, (q31_t)0x39411e33, (q31_t)0x2371beb5, (q31_t)0x3946baac, + (q31_t)0x237cfe47, (q31_t)0x394c54ee, (q31_t)0x23883ef2, (q31_t)0x3951ecfc, + (q31_t)0x239380b6, (q31_t)0x395782d3, (q31_t)0x239ec393, (q31_t)0x395d1675, + (q31_t)0x23aa0788, (q31_t)0x3962a7e0, (q31_t)0x23b54c95, (q31_t)0x39683715, + (q31_t)0x23c092b9, (q31_t)0x396dc414, (q31_t)0x23cbd9f4, (q31_t)0x39734edc, + (q31_t)0x23d72245, (q31_t)0x3978d76c, (q31_t)0x23e26bac, (q31_t)0x397e5dc6, + (q31_t)0x23edb628, (q31_t)0x3983e1e8, (q31_t)0x23f901ba, (q31_t)0x398963d2, + (q31_t)0x24044e60, (q31_t)0x398ee385, (q31_t)0x240f9c1a, (q31_t)0x399460ff, + (q31_t)0x241aeae8, (q31_t)0x3999dc42, (q31_t)0x24263ac9, (q31_t)0x399f554b, + (q31_t)0x24318bbe, (q31_t)0x39a4cc1c, (q31_t)0x243cddc4, (q31_t)0x39aa40b4, + (q31_t)0x244830dd, (q31_t)0x39afb313, (q31_t)0x24538507, (q31_t)0x39b52339, + (q31_t)0x245eda43, (q31_t)0x39ba9125, (q31_t)0x246a308f, (q31_t)0x39bffcd7, + (q31_t)0x247587eb, (q31_t)0x39c5664f, (q31_t)0x2480e057, (q31_t)0x39cacd8d, + (q31_t)0x248c39d3, (q31_t)0x39d03291, (q31_t)0x2497945d, (q31_t)0x39d5955a, + (q31_t)0x24a2eff6, (q31_t)0x39daf5e8, (q31_t)0x24ae4c9d, (q31_t)0x39e0543c, + (q31_t)0x24b9aa52, (q31_t)0x39e5b054, (q31_t)0x24c50914, (q31_t)0x39eb0a31, + (q31_t)0x24d068e2, (q31_t)0x39f061d2, (q31_t)0x24dbc9bd, (q31_t)0x39f5b737, + (q31_t)0x24e72ba4, (q31_t)0x39fb0a60, (q31_t)0x24f28e96, (q31_t)0x3a005b4d, + (q31_t)0x24fdf294, (q31_t)0x3a05a9fd, (q31_t)0x2509579b, (q31_t)0x3a0af671, + (q31_t)0x2514bdad, (q31_t)0x3a1040a8, (q31_t)0x252024c9, (q31_t)0x3a1588a2, + (q31_t)0x252b8cee, (q31_t)0x3a1ace5f, (q31_t)0x2536f61b, (q31_t)0x3a2011de, + (q31_t)0x25426051, (q31_t)0x3a25531f, (q31_t)0x254dcb8f, (q31_t)0x3a2a9223, + (q31_t)0x255937d5, (q31_t)0x3a2fcee8, (q31_t)0x2564a521, (q31_t)0x3a350970, + (q31_t)0x25701374, (q31_t)0x3a3a41b9, (q31_t)0x257b82cd, (q31_t)0x3a3f77c3, + (q31_t)0x2586f32c, (q31_t)0x3a44ab8e, (q31_t)0x25926490, (q31_t)0x3a49dd1a, + (q31_t)0x259dd6f9, (q31_t)0x3a4f0c67, (q31_t)0x25a94a67, (q31_t)0x3a543974, + (q31_t)0x25b4bed8, (q31_t)0x3a596442, (q31_t)0x25c0344d, (q31_t)0x3a5e8cd0, + (q31_t)0x25cbaac5, (q31_t)0x3a63b31d, (q31_t)0x25d72240, (q31_t)0x3a68d72b, + (q31_t)0x25e29abc, (q31_t)0x3a6df8f8, (q31_t)0x25ee143b, (q31_t)0x3a731884, + (q31_t)0x25f98ebb, (q31_t)0x3a7835cf, (q31_t)0x26050a3b, (q31_t)0x3a7d50da, + (q31_t)0x261086bc, (q31_t)0x3a8269a3, (q31_t)0x261c043d, (q31_t)0x3a87802a, + (q31_t)0x262782be, (q31_t)0x3a8c9470, (q31_t)0x2633023e, (q31_t)0x3a91a674, + (q31_t)0x263e82bc, (q31_t)0x3a96b636, (q31_t)0x264a0438, (q31_t)0x3a9bc3b6, + (q31_t)0x265586b3, (q31_t)0x3aa0cef3, (q31_t)0x26610a2a, (q31_t)0x3aa5d7ee, + (q31_t)0x266c8e9f, (q31_t)0x3aaadea6, (q31_t)0x26781410, (q31_t)0x3aafe31b, + (q31_t)0x26839a7c, (q31_t)0x3ab4e54c, (q31_t)0x268f21e5, (q31_t)0x3ab9e53a, + (q31_t)0x269aaa48, (q31_t)0x3abee2e5, (q31_t)0x26a633a6, (q31_t)0x3ac3de4c, + (q31_t)0x26b1bdff, (q31_t)0x3ac8d76f, (q31_t)0x26bd4951, (q31_t)0x3acdce4d, + (q31_t)0x26c8d59c, (q31_t)0x3ad2c2e8, (q31_t)0x26d462e1, (q31_t)0x3ad7b53d, + (q31_t)0x26dff11d, (q31_t)0x3adca54e, (q31_t)0x26eb8052, (q31_t)0x3ae1931a, + (q31_t)0x26f7107e, (q31_t)0x3ae67ea1, (q31_t)0x2702a1a1, (q31_t)0x3aeb67e3, + (q31_t)0x270e33bb, (q31_t)0x3af04edf, (q31_t)0x2719c6cb, (q31_t)0x3af53395, + (q31_t)0x27255ad1, (q31_t)0x3afa1605, (q31_t)0x2730efcc, (q31_t)0x3afef630, + (q31_t)0x273c85bc, (q31_t)0x3b03d414, (q31_t)0x27481ca1, (q31_t)0x3b08afb2, + (q31_t)0x2753b479, (q31_t)0x3b0d8909, (q31_t)0x275f4d45, (q31_t)0x3b126019, + (q31_t)0x276ae704, (q31_t)0x3b1734e2, (q31_t)0x277681b6, (q31_t)0x3b1c0764, + (q31_t)0x27821d59, (q31_t)0x3b20d79e, (q31_t)0x278db9ef, (q31_t)0x3b25a591, + (q31_t)0x27995776, (q31_t)0x3b2a713d, (q31_t)0x27a4f5ed, (q31_t)0x3b2f3aa0, + (q31_t)0x27b09555, (q31_t)0x3b3401bb, (q31_t)0x27bc35ad, (q31_t)0x3b38c68e, + (q31_t)0x27c7d6f4, (q31_t)0x3b3d8918, (q31_t)0x27d3792b, (q31_t)0x3b42495a, + (q31_t)0x27df1c50, (q31_t)0x3b470753, (q31_t)0x27eac063, (q31_t)0x3b4bc303, + (q31_t)0x27f66564, (q31_t)0x3b507c69, (q31_t)0x28020b52, (q31_t)0x3b553386, + (q31_t)0x280db22d, (q31_t)0x3b59e85a, (q31_t)0x281959f4, (q31_t)0x3b5e9ae4, + (q31_t)0x282502a7, (q31_t)0x3b634b23, (q31_t)0x2830ac45, (q31_t)0x3b67f919, + (q31_t)0x283c56cf, (q31_t)0x3b6ca4c4, (q31_t)0x28480243, (q31_t)0x3b714e25, + (q31_t)0x2853aea1, (q31_t)0x3b75f53c, (q31_t)0x285f5be9, (q31_t)0x3b7a9a07, + (q31_t)0x286b0a1a, (q31_t)0x3b7f3c87, (q31_t)0x2876b934, (q31_t)0x3b83dcbc, + (q31_t)0x28826936, (q31_t)0x3b887aa6, (q31_t)0x288e1a20, (q31_t)0x3b8d1644, + (q31_t)0x2899cbf1, (q31_t)0x3b91af97, (q31_t)0x28a57ea9, (q31_t)0x3b96469d, + (q31_t)0x28b13248, (q31_t)0x3b9adb57, (q31_t)0x28bce6cd, (q31_t)0x3b9f6dc5, + (q31_t)0x28c89c37, (q31_t)0x3ba3fde7, (q31_t)0x28d45286, (q31_t)0x3ba88bbc, + (q31_t)0x28e009ba, (q31_t)0x3bad1744, (q31_t)0x28ebc1d3, (q31_t)0x3bb1a080, + (q31_t)0x28f77acf, (q31_t)0x3bb6276e, (q31_t)0x290334af, (q31_t)0x3bbaac0e, + (q31_t)0x290eef71, (q31_t)0x3bbf2e62, (q31_t)0x291aab16, (q31_t)0x3bc3ae67, + (q31_t)0x2926679c, (q31_t)0x3bc82c1f, (q31_t)0x29322505, (q31_t)0x3bcca789, + (q31_t)0x293de34e, (q31_t)0x3bd120a4, (q31_t)0x2949a278, (q31_t)0x3bd59771, + (q31_t)0x29556282, (q31_t)0x3bda0bf0, (q31_t)0x2961236c, (q31_t)0x3bde7e20, + (q31_t)0x296ce535, (q31_t)0x3be2ee01, (q31_t)0x2978a7dd, (q31_t)0x3be75b93, + (q31_t)0x29846b63, (q31_t)0x3bebc6d5, (q31_t)0x29902fc7, (q31_t)0x3bf02fc9, + (q31_t)0x299bf509, (q31_t)0x3bf4966c, (q31_t)0x29a7bb28, (q31_t)0x3bf8fac0, + (q31_t)0x29b38223, (q31_t)0x3bfd5cc4, (q31_t)0x29bf49fa, (q31_t)0x3c01bc78, + (q31_t)0x29cb12ad, (q31_t)0x3c0619dc, (q31_t)0x29d6dc3b, (q31_t)0x3c0a74f0, + (q31_t)0x29e2a6a3, (q31_t)0x3c0ecdb2, (q31_t)0x29ee71e6, (q31_t)0x3c132424, + (q31_t)0x29fa3e03, (q31_t)0x3c177845, (q31_t)0x2a060af9, (q31_t)0x3c1bca16, + (q31_t)0x2a11d8c8, (q31_t)0x3c201994, (q31_t)0x2a1da770, (q31_t)0x3c2466c2, + (q31_t)0x2a2976ef, (q31_t)0x3c28b19e, (q31_t)0x2a354746, (q31_t)0x3c2cfa28, + (q31_t)0x2a411874, (q31_t)0x3c314060, (q31_t)0x2a4cea79, (q31_t)0x3c358446, + (q31_t)0x2a58bd54, (q31_t)0x3c39c5da, (q31_t)0x2a649105, (q31_t)0x3c3e051b, + (q31_t)0x2a70658a, (q31_t)0x3c42420a, (q31_t)0x2a7c3ae5, (q31_t)0x3c467ca6, + (q31_t)0x2a881114, (q31_t)0x3c4ab4ef, (q31_t)0x2a93e817, (q31_t)0x3c4eeae5, + (q31_t)0x2a9fbfed, (q31_t)0x3c531e88, (q31_t)0x2aab9896, (q31_t)0x3c574fd8, + (q31_t)0x2ab77212, (q31_t)0x3c5b7ed4, (q31_t)0x2ac34c60, (q31_t)0x3c5fab7c, + (q31_t)0x2acf277f, (q31_t)0x3c63d5d1, (q31_t)0x2adb0370, (q31_t)0x3c67fdd1, + (q31_t)0x2ae6e031, (q31_t)0x3c6c237e, (q31_t)0x2af2bdc3, (q31_t)0x3c7046d6, + (q31_t)0x2afe9c24, (q31_t)0x3c7467d9, (q31_t)0x2b0a7b54, (q31_t)0x3c788688, + (q31_t)0x2b165b54, (q31_t)0x3c7ca2e2, (q31_t)0x2b223c22, (q31_t)0x3c80bce7, + (q31_t)0x2b2e1dbe, (q31_t)0x3c84d496, (q31_t)0x2b3a0027, (q31_t)0x3c88e9f1, + (q31_t)0x2b45e35d, (q31_t)0x3c8cfcf6, (q31_t)0x2b51c760, (q31_t)0x3c910da5, + (q31_t)0x2b5dac2f, (q31_t)0x3c951bff, (q31_t)0x2b6991ca, (q31_t)0x3c992803, + (q31_t)0x2b75782f, (q31_t)0x3c9d31b0, (q31_t)0x2b815f60, (q31_t)0x3ca13908, + (q31_t)0x2b8d475b, (q31_t)0x3ca53e09, (q31_t)0x2b99301f, (q31_t)0x3ca940b3, + (q31_t)0x2ba519ad, (q31_t)0x3cad4107, (q31_t)0x2bb10404, (q31_t)0x3cb13f04, + (q31_t)0x2bbcef23, (q31_t)0x3cb53aaa, (q31_t)0x2bc8db0b, (q31_t)0x3cb933f9, + (q31_t)0x2bd4c7ba, (q31_t)0x3cbd2af0, (q31_t)0x2be0b52f, (q31_t)0x3cc11f90, + (q31_t)0x2beca36c, (q31_t)0x3cc511d9, (q31_t)0x2bf8926f, (q31_t)0x3cc901c9, + (q31_t)0x2c048237, (q31_t)0x3cccef62, (q31_t)0x2c1072c4, (q31_t)0x3cd0daa2, + (q31_t)0x2c1c6417, (q31_t)0x3cd4c38b, (q31_t)0x2c28562d, (q31_t)0x3cd8aa1b, + (q31_t)0x2c344908, (q31_t)0x3cdc8e52, (q31_t)0x2c403ca5, (q31_t)0x3ce07031, + (q31_t)0x2c4c3106, (q31_t)0x3ce44fb7, (q31_t)0x2c582629, (q31_t)0x3ce82ce4, + (q31_t)0x2c641c0e, (q31_t)0x3cec07b8, (q31_t)0x2c7012b5, (q31_t)0x3cefe032, + (q31_t)0x2c7c0a1d, (q31_t)0x3cf3b653, (q31_t)0x2c880245, (q31_t)0x3cf78a1b, + (q31_t)0x2c93fb2e, (q31_t)0x3cfb5b89, (q31_t)0x2c9ff4d6, (q31_t)0x3cff2a9d, + (q31_t)0x2cabef3d, (q31_t)0x3d02f757, (q31_t)0x2cb7ea63, (q31_t)0x3d06c1b6, + (q31_t)0x2cc3e648, (q31_t)0x3d0a89bc, (q31_t)0x2ccfe2ea, (q31_t)0x3d0e4f67, + (q31_t)0x2cdbe04a, (q31_t)0x3d1212b7, (q31_t)0x2ce7de66, (q31_t)0x3d15d3ad, + (q31_t)0x2cf3dd3f, (q31_t)0x3d199248, (q31_t)0x2cffdcd4, (q31_t)0x3d1d4e88, + (q31_t)0x2d0bdd25, (q31_t)0x3d21086c, (q31_t)0x2d17de31, (q31_t)0x3d24bff6, + (q31_t)0x2d23dff7, (q31_t)0x3d287523, (q31_t)0x2d2fe277, (q31_t)0x3d2c27f6, + (q31_t)0x2d3be5b1, (q31_t)0x3d2fd86c, (q31_t)0x2d47e9a5, (q31_t)0x3d338687, + (q31_t)0x2d53ee51, (q31_t)0x3d373245, (q31_t)0x2d5ff3b5, (q31_t)0x3d3adba7, + (q31_t)0x2d6bf9d1, (q31_t)0x3d3e82ae, (q31_t)0x2d7800a5, (q31_t)0x3d422757, + (q31_t)0x2d84082f, (q31_t)0x3d45c9a4, (q31_t)0x2d901070, (q31_t)0x3d496994, + (q31_t)0x2d9c1967, (q31_t)0x3d4d0728, (q31_t)0x2da82313, (q31_t)0x3d50a25e, + (q31_t)0x2db42d74, (q31_t)0x3d543b37, (q31_t)0x2dc0388a, (q31_t)0x3d57d1b3, + (q31_t)0x2dcc4454, (q31_t)0x3d5b65d2, (q31_t)0x2dd850d2, (q31_t)0x3d5ef793, + (q31_t)0x2de45e03, (q31_t)0x3d6286f6, (q31_t)0x2df06be6, (q31_t)0x3d6613fb, + (q31_t)0x2dfc7a7c, (q31_t)0x3d699ea3, (q31_t)0x2e0889c4, (q31_t)0x3d6d26ec, + (q31_t)0x2e1499bd, (q31_t)0x3d70acd7, (q31_t)0x2e20aa67, (q31_t)0x3d743064, + (q31_t)0x2e2cbbc1, (q31_t)0x3d77b192, (q31_t)0x2e38cdcb, (q31_t)0x3d7b3061, + (q31_t)0x2e44e084, (q31_t)0x3d7eacd2, (q31_t)0x2e50f3ed, (q31_t)0x3d8226e4, + (q31_t)0x2e5d0804, (q31_t)0x3d859e96, (q31_t)0x2e691cc9, (q31_t)0x3d8913ea, + (q31_t)0x2e75323c, (q31_t)0x3d8c86de, (q31_t)0x2e81485c, (q31_t)0x3d8ff772, + (q31_t)0x2e8d5f29, (q31_t)0x3d9365a8, (q31_t)0x2e9976a1, (q31_t)0x3d96d17d, + (q31_t)0x2ea58ec6, (q31_t)0x3d9a3af2, (q31_t)0x2eb1a796, (q31_t)0x3d9da208, + (q31_t)0x2ebdc110, (q31_t)0x3da106bd, (q31_t)0x2ec9db35, (q31_t)0x3da46912, + (q31_t)0x2ed5f604, (q31_t)0x3da7c907, (q31_t)0x2ee2117c, (q31_t)0x3dab269b, + (q31_t)0x2eee2d9d, (q31_t)0x3dae81cf, (q31_t)0x2efa4a67, (q31_t)0x3db1daa2, + (q31_t)0x2f0667d9, (q31_t)0x3db53113, (q31_t)0x2f1285f2, (q31_t)0x3db88524, + (q31_t)0x2f1ea4b2, (q31_t)0x3dbbd6d4, (q31_t)0x2f2ac419, (q31_t)0x3dbf2622, + (q31_t)0x2f36e426, (q31_t)0x3dc2730f, (q31_t)0x2f4304d8, (q31_t)0x3dc5bd9b, + (q31_t)0x2f4f2630, (q31_t)0x3dc905c5, (q31_t)0x2f5b482d, (q31_t)0x3dcc4b8d, + (q31_t)0x2f676ace, (q31_t)0x3dcf8ef3, (q31_t)0x2f738e12, (q31_t)0x3dd2cff7, + (q31_t)0x2f7fb1fa, (q31_t)0x3dd60e99, (q31_t)0x2f8bd685, (q31_t)0x3dd94ad8, + (q31_t)0x2f97fbb2, (q31_t)0x3ddc84b5, (q31_t)0x2fa42181, (q31_t)0x3ddfbc30, + (q31_t)0x2fb047f2, (q31_t)0x3de2f148, (q31_t)0x2fbc6f03, (q31_t)0x3de623fd, + (q31_t)0x2fc896b5, (q31_t)0x3de9544f, (q31_t)0x2fd4bf08, (q31_t)0x3dec823e, + (q31_t)0x2fe0e7f9, (q31_t)0x3defadca, (q31_t)0x2fed118a, (q31_t)0x3df2d6f3, + (q31_t)0x2ff93bba, (q31_t)0x3df5fdb8, (q31_t)0x30056687, (q31_t)0x3df9221a, + (q31_t)0x301191f3, (q31_t)0x3dfc4418, (q31_t)0x301dbdfb, (q31_t)0x3dff63b2, + (q31_t)0x3029eaa1, (q31_t)0x3e0280e9, (q31_t)0x303617e2, (q31_t)0x3e059bbb, + (q31_t)0x304245c0, (q31_t)0x3e08b42a, (q31_t)0x304e7438, (q31_t)0x3e0bca34, + (q31_t)0x305aa34c, (q31_t)0x3e0eddd9, (q31_t)0x3066d2fa, (q31_t)0x3e11ef1b, + (q31_t)0x30730342, (q31_t)0x3e14fdf7, (q31_t)0x307f3424, (q31_t)0x3e180a6f, + (q31_t)0x308b659f, (q31_t)0x3e1b1482, (q31_t)0x309797b2, (q31_t)0x3e1e1c30, + (q31_t)0x30a3ca5d, (q31_t)0x3e212179, (q31_t)0x30affda0, (q31_t)0x3e24245d, + (q31_t)0x30bc317a, (q31_t)0x3e2724db, (q31_t)0x30c865ea, (q31_t)0x3e2a22f4, + (q31_t)0x30d49af1, (q31_t)0x3e2d1ea8, (q31_t)0x30e0d08d, (q31_t)0x3e3017f6, + (q31_t)0x30ed06bf, (q31_t)0x3e330ede, (q31_t)0x30f93d86, (q31_t)0x3e360360, + (q31_t)0x310574e0, (q31_t)0x3e38f57c, (q31_t)0x3111accf, (q31_t)0x3e3be532, + (q31_t)0x311de551, (q31_t)0x3e3ed282, (q31_t)0x312a1e66, (q31_t)0x3e41bd6c, + (q31_t)0x3136580d, (q31_t)0x3e44a5ef, (q31_t)0x31429247, (q31_t)0x3e478c0b, + (q31_t)0x314ecd11, (q31_t)0x3e4a6fc1, (q31_t)0x315b086d, (q31_t)0x3e4d5110, + (q31_t)0x31674459, (q31_t)0x3e502ff9, (q31_t)0x317380d6, (q31_t)0x3e530c7a, + (q31_t)0x317fbde2, (q31_t)0x3e55e694, (q31_t)0x318bfb7d, (q31_t)0x3e58be47, + (q31_t)0x319839a6, (q31_t)0x3e5b9392, (q31_t)0x31a4785e, (q31_t)0x3e5e6676, + (q31_t)0x31b0b7a4, (q31_t)0x3e6136f3, (q31_t)0x31bcf777, (q31_t)0x3e640507, + (q31_t)0x31c937d6, (q31_t)0x3e66d0b4, (q31_t)0x31d578c2, (q31_t)0x3e6999fa, + (q31_t)0x31e1ba3a, (q31_t)0x3e6c60d7, (q31_t)0x31edfc3d, (q31_t)0x3e6f254c, + (q31_t)0x31fa3ecb, (q31_t)0x3e71e759, (q31_t)0x320681e3, (q31_t)0x3e74a6fd, + (q31_t)0x3212c585, (q31_t)0x3e77643a, (q31_t)0x321f09b1, (q31_t)0x3e7a1f0d, + (q31_t)0x322b4e66, (q31_t)0x3e7cd778, (q31_t)0x323793a3, (q31_t)0x3e7f8d7b, + (q31_t)0x3243d968, (q31_t)0x3e824114, (q31_t)0x32501fb5, (q31_t)0x3e84f245, + (q31_t)0x325c6688, (q31_t)0x3e87a10c, (q31_t)0x3268ade3, (q31_t)0x3e8a4d6a, + (q31_t)0x3274f5c3, (q31_t)0x3e8cf75f, (q31_t)0x32813e2a, (q31_t)0x3e8f9eeb, + (q31_t)0x328d8715, (q31_t)0x3e92440d, (q31_t)0x3299d085, (q31_t)0x3e94e6c6, + (q31_t)0x32a61a7a, (q31_t)0x3e978715, (q31_t)0x32b264f2, (q31_t)0x3e9a24fb, + (q31_t)0x32beafed, (q31_t)0x3e9cc076, (q31_t)0x32cafb6b, (q31_t)0x3e9f5988, + (q31_t)0x32d7476c, (q31_t)0x3ea1f02f, (q31_t)0x32e393ef, (q31_t)0x3ea4846c, + (q31_t)0x32efe0f2, (q31_t)0x3ea7163f, (q31_t)0x32fc2e77, (q31_t)0x3ea9a5a8, + (q31_t)0x33087c7d, (q31_t)0x3eac32a6, (q31_t)0x3314cb02, (q31_t)0x3eaebd3a, + (q31_t)0x33211a07, (q31_t)0x3eb14563, (q31_t)0x332d698a, (q31_t)0x3eb3cb21, + (q31_t)0x3339b98d, (q31_t)0x3eb64e75, (q31_t)0x33460a0d, (q31_t)0x3eb8cf5d, + (q31_t)0x33525b0b, (q31_t)0x3ebb4ddb, (q31_t)0x335eac86, (q31_t)0x3ebdc9ed, + (q31_t)0x336afe7e, (q31_t)0x3ec04394, (q31_t)0x337750f2, (q31_t)0x3ec2bad0, + (q31_t)0x3383a3e2, (q31_t)0x3ec52fa0, (q31_t)0x338ff74d, (q31_t)0x3ec7a205, + (q31_t)0x339c4b32, (q31_t)0x3eca11fe, (q31_t)0x33a89f92, (q31_t)0x3ecc7f8b, + (q31_t)0x33b4f46c, (q31_t)0x3eceeaad, (q31_t)0x33c149bf, (q31_t)0x3ed15363, + (q31_t)0x33cd9f8b, (q31_t)0x3ed3b9ad, (q31_t)0x33d9f5cf, (q31_t)0x3ed61d8a, + (q31_t)0x33e64c8c, (q31_t)0x3ed87efc, (q31_t)0x33f2a3bf, (q31_t)0x3edade01, + (q31_t)0x33fefb6a, (q31_t)0x3edd3a9a, (q31_t)0x340b538b, (q31_t)0x3edf94c7, + (q31_t)0x3417ac22, (q31_t)0x3ee1ec87, (q31_t)0x3424052f, (q31_t)0x3ee441da, + (q31_t)0x34305eb0, (q31_t)0x3ee694c1, (q31_t)0x343cb8a7, (q31_t)0x3ee8e53a, + (q31_t)0x34491311, (q31_t)0x3eeb3347, (q31_t)0x34556def, (q31_t)0x3eed7ee7, + (q31_t)0x3461c940, (q31_t)0x3eefc81a, (q31_t)0x346e2504, (q31_t)0x3ef20ee0, + (q31_t)0x347a8139, (q31_t)0x3ef45338, (q31_t)0x3486dde1, (q31_t)0x3ef69523, + (q31_t)0x34933afa, (q31_t)0x3ef8d4a1, (q31_t)0x349f9884, (q31_t)0x3efb11b1, + (q31_t)0x34abf67e, (q31_t)0x3efd4c54, (q31_t)0x34b854e7, (q31_t)0x3eff8489, + (q31_t)0x34c4b3c0, (q31_t)0x3f01ba50, (q31_t)0x34d11308, (q31_t)0x3f03eda9, + (q31_t)0x34dd72be, (q31_t)0x3f061e95, (q31_t)0x34e9d2e3, (q31_t)0x3f084d12, + (q31_t)0x34f63374, (q31_t)0x3f0a7921, (q31_t)0x35029473, (q31_t)0x3f0ca2c2, + (q31_t)0x350ef5de, (q31_t)0x3f0ec9f5, (q31_t)0x351b57b5, (q31_t)0x3f10eeb9, + (q31_t)0x3527b9f7, (q31_t)0x3f13110f, (q31_t)0x35341ca5, (q31_t)0x3f1530f7, + (q31_t)0x35407fbd, (q31_t)0x3f174e70, (q31_t)0x354ce33f, (q31_t)0x3f19697a, + (q31_t)0x3559472b, (q31_t)0x3f1b8215, (q31_t)0x3565ab80, (q31_t)0x3f1d9842, + (q31_t)0x3572103d, (q31_t)0x3f1fabff, (q31_t)0x357e7563, (q31_t)0x3f21bd4e, + (q31_t)0x358adaf0, (q31_t)0x3f23cc2e, (q31_t)0x359740e5, (q31_t)0x3f25d89e, + (q31_t)0x35a3a740, (q31_t)0x3f27e29f, (q31_t)0x35b00e02, (q31_t)0x3f29ea31, + (q31_t)0x35bc7529, (q31_t)0x3f2bef53, (q31_t)0x35c8dcb6, (q31_t)0x3f2df206, + (q31_t)0x35d544a7, (q31_t)0x3f2ff24a, (q31_t)0x35e1acfd, (q31_t)0x3f31f01d, + (q31_t)0x35ee15b7, (q31_t)0x3f33eb81, (q31_t)0x35fa7ed4, (q31_t)0x3f35e476, + (q31_t)0x3606e854, (q31_t)0x3f37dafa, (q31_t)0x36135237, (q31_t)0x3f39cf0e, + (q31_t)0x361fbc7b, (q31_t)0x3f3bc0b3, (q31_t)0x362c2721, (q31_t)0x3f3dafe7, + (q31_t)0x36389228, (q31_t)0x3f3f9cab, (q31_t)0x3644fd8f, (q31_t)0x3f4186ff, + (q31_t)0x36516956, (q31_t)0x3f436ee3, (q31_t)0x365dd57d, (q31_t)0x3f455456, + (q31_t)0x366a4203, (q31_t)0x3f473759, (q31_t)0x3676aee8, (q31_t)0x3f4917eb, + (q31_t)0x36831c2b, (q31_t)0x3f4af60d, (q31_t)0x368f89cb, (q31_t)0x3f4cd1be, + (q31_t)0x369bf7c9, (q31_t)0x3f4eaafe, (q31_t)0x36a86623, (q31_t)0x3f5081cd, + (q31_t)0x36b4d4d9, (q31_t)0x3f52562c, (q31_t)0x36c143ec, (q31_t)0x3f54281a, + (q31_t)0x36cdb359, (q31_t)0x3f55f796, (q31_t)0x36da2321, (q31_t)0x3f57c4a2, + (q31_t)0x36e69344, (q31_t)0x3f598f3c, (q31_t)0x36f303c0, (q31_t)0x3f5b5765, + (q31_t)0x36ff7496, (q31_t)0x3f5d1d1d, (q31_t)0x370be5c4, (q31_t)0x3f5ee063, + (q31_t)0x3718574b, (q31_t)0x3f60a138, (q31_t)0x3724c92a, (q31_t)0x3f625f9b, + (q31_t)0x37313b60, (q31_t)0x3f641b8d, (q31_t)0x373daded, (q31_t)0x3f65d50d, + (q31_t)0x374a20d0, (q31_t)0x3f678c1c, (q31_t)0x3756940a, (q31_t)0x3f6940b8, + (q31_t)0x37630799, (q31_t)0x3f6af2e3, (q31_t)0x376f7b7d, (q31_t)0x3f6ca29c, + (q31_t)0x377befb5, (q31_t)0x3f6e4fe3, (q31_t)0x37886442, (q31_t)0x3f6ffab8, + (q31_t)0x3794d922, (q31_t)0x3f71a31b, (q31_t)0x37a14e55, (q31_t)0x3f73490b, + (q31_t)0x37adc3db, (q31_t)0x3f74ec8a, (q31_t)0x37ba39b3, (q31_t)0x3f768d96, + (q31_t)0x37c6afdc, (q31_t)0x3f782c30, (q31_t)0x37d32657, (q31_t)0x3f79c857, + (q31_t)0x37df9d22, (q31_t)0x3f7b620c, (q31_t)0x37ec143e, (q31_t)0x3f7cf94e, + (q31_t)0x37f88ba9, (q31_t)0x3f7e8e1e, (q31_t)0x38050364, (q31_t)0x3f80207b, + (q31_t)0x38117b6d, (q31_t)0x3f81b065, (q31_t)0x381df3c5, (q31_t)0x3f833ddd, + (q31_t)0x382a6c6a, (q31_t)0x3f84c8e2, (q31_t)0x3836e55d, (q31_t)0x3f865174, + (q31_t)0x38435e9d, (q31_t)0x3f87d792, (q31_t)0x384fd829, (q31_t)0x3f895b3e, + (q31_t)0x385c5201, (q31_t)0x3f8adc77, (q31_t)0x3868cc24, (q31_t)0x3f8c5b3d, + (q31_t)0x38754692, (q31_t)0x3f8dd78f, (q31_t)0x3881c14b, (q31_t)0x3f8f516e, + (q31_t)0x388e3c4d, (q31_t)0x3f90c8da, (q31_t)0x389ab799, (q31_t)0x3f923dd2, + (q31_t)0x38a7332e, (q31_t)0x3f93b058, (q31_t)0x38b3af0c, (q31_t)0x3f952069, + (q31_t)0x38c02b31, (q31_t)0x3f968e07, (q31_t)0x38cca79e, (q31_t)0x3f97f932, + (q31_t)0x38d92452, (q31_t)0x3f9961e8, (q31_t)0x38e5a14d, (q31_t)0x3f9ac82c, + (q31_t)0x38f21e8e, (q31_t)0x3f9c2bfb, (q31_t)0x38fe9c15, (q31_t)0x3f9d8d56, + (q31_t)0x390b19e0, (q31_t)0x3f9eec3e, (q31_t)0x391797f0, (q31_t)0x3fa048b2, + (q31_t)0x39241645, (q31_t)0x3fa1a2b2, (q31_t)0x393094dd, (q31_t)0x3fa2fa3d, + (q31_t)0x393d13b8, (q31_t)0x3fa44f55, (q31_t)0x394992d7, (q31_t)0x3fa5a1f9, + (q31_t)0x39561237, (q31_t)0x3fa6f228, (q31_t)0x396291d9, (q31_t)0x3fa83fe3, + (q31_t)0x396f11bc, (q31_t)0x3fa98b2a, (q31_t)0x397b91e1, (q31_t)0x3faad3fd, + (q31_t)0x39881245, (q31_t)0x3fac1a5b, (q31_t)0x399492ea, (q31_t)0x3fad5e45, + (q31_t)0x39a113cd, (q31_t)0x3fae9fbb, (q31_t)0x39ad94f0, (q31_t)0x3fafdebb, + (q31_t)0x39ba1651, (q31_t)0x3fb11b48, (q31_t)0x39c697f0, (q31_t)0x3fb2555f, + (q31_t)0x39d319cc, (q31_t)0x3fb38d02, (q31_t)0x39df9be6, (q31_t)0x3fb4c231, + (q31_t)0x39ec1e3b, (q31_t)0x3fb5f4ea, (q31_t)0x39f8a0cd, (q31_t)0x3fb7252f, + (q31_t)0x3a05239a, (q31_t)0x3fb852ff, (q31_t)0x3a11a6a3, (q31_t)0x3fb97e5a, + (q31_t)0x3a1e29e5, (q31_t)0x3fbaa740, (q31_t)0x3a2aad62, (q31_t)0x3fbbcdb1, + (q31_t)0x3a373119, (q31_t)0x3fbcf1ad, (q31_t)0x3a43b508, (q31_t)0x3fbe1334, + (q31_t)0x3a503930, (q31_t)0x3fbf3246, (q31_t)0x3a5cbd91, (q31_t)0x3fc04ee3, + (q31_t)0x3a694229, (q31_t)0x3fc1690a, (q31_t)0x3a75c6f8, (q31_t)0x3fc280bc, + (q31_t)0x3a824bfd, (q31_t)0x3fc395f9, (q31_t)0x3a8ed139, (q31_t)0x3fc4a8c1, + (q31_t)0x3a9b56ab, (q31_t)0x3fc5b913, (q31_t)0x3aa7dc52, (q31_t)0x3fc6c6f0, + (q31_t)0x3ab4622d, (q31_t)0x3fc7d258, (q31_t)0x3ac0e83d, (q31_t)0x3fc8db4a, + (q31_t)0x3acd6e81, (q31_t)0x3fc9e1c6, (q31_t)0x3ad9f4f8, (q31_t)0x3fcae5cd, + (q31_t)0x3ae67ba2, (q31_t)0x3fcbe75e, (q31_t)0x3af3027e, (q31_t)0x3fcce67a, + (q31_t)0x3aff898c, (q31_t)0x3fcde320, (q31_t)0x3b0c10cb, (q31_t)0x3fcedd50, + (q31_t)0x3b18983b, (q31_t)0x3fcfd50b, (q31_t)0x3b251fdc, (q31_t)0x3fd0ca4f, + (q31_t)0x3b31a7ac, (q31_t)0x3fd1bd1e, (q31_t)0x3b3e2fac, (q31_t)0x3fd2ad77, + (q31_t)0x3b4ab7db, (q31_t)0x3fd39b5a, (q31_t)0x3b574039, (q31_t)0x3fd486c7, + (q31_t)0x3b63c8c4, (q31_t)0x3fd56fbe, (q31_t)0x3b70517d, (q31_t)0x3fd6563f, + (q31_t)0x3b7cda63, (q31_t)0x3fd73a4a, (q31_t)0x3b896375, (q31_t)0x3fd81bdf, + (q31_t)0x3b95ecb4, (q31_t)0x3fd8fafe, (q31_t)0x3ba2761e, (q31_t)0x3fd9d7a7, + (q31_t)0x3baeffb3, (q31_t)0x3fdab1d9, (q31_t)0x3bbb8973, (q31_t)0x3fdb8996, + (q31_t)0x3bc8135c, (q31_t)0x3fdc5edc, (q31_t)0x3bd49d70, (q31_t)0x3fdd31ac, + (q31_t)0x3be127ac, (q31_t)0x3fde0205, (q31_t)0x3bedb212, (q31_t)0x3fdecfe8, + (q31_t)0x3bfa3c9f, (q31_t)0x3fdf9b55, (q31_t)0x3c06c754, (q31_t)0x3fe0644b, + (q31_t)0x3c135231, (q31_t)0x3fe12acb, (q31_t)0x3c1fdd34, (q31_t)0x3fe1eed5, + (q31_t)0x3c2c685d, (q31_t)0x3fe2b067, (q31_t)0x3c38f3ac, (q31_t)0x3fe36f84, + (q31_t)0x3c457f21, (q31_t)0x3fe42c2a, (q31_t)0x3c520aba, (q31_t)0x3fe4e659, + (q31_t)0x3c5e9678, (q31_t)0x3fe59e12, (q31_t)0x3c6b2259, (q31_t)0x3fe65354, + (q31_t)0x3c77ae5e, (q31_t)0x3fe7061f, (q31_t)0x3c843a85, (q31_t)0x3fe7b674, + (q31_t)0x3c90c6cf, (q31_t)0x3fe86452, (q31_t)0x3c9d533b, (q31_t)0x3fe90fb9, + (q31_t)0x3ca9dfc8, (q31_t)0x3fe9b8a9, (q31_t)0x3cb66c77, (q31_t)0x3fea5f23, + (q31_t)0x3cc2f945, (q31_t)0x3feb0326, (q31_t)0x3ccf8634, (q31_t)0x3feba4b2, + (q31_t)0x3cdc1342, (q31_t)0x3fec43c7, (q31_t)0x3ce8a06f, (q31_t)0x3fece065, + (q31_t)0x3cf52dbb, (q31_t)0x3fed7a8c, (q31_t)0x3d01bb24, (q31_t)0x3fee123d, + (q31_t)0x3d0e48ab, (q31_t)0x3feea776, (q31_t)0x3d1ad650, (q31_t)0x3fef3a39, + (q31_t)0x3d276410, (q31_t)0x3fefca84, (q31_t)0x3d33f1ed, (q31_t)0x3ff05858, + (q31_t)0x3d407fe6, (q31_t)0x3ff0e3b6, (q31_t)0x3d4d0df9, (q31_t)0x3ff16c9c, + (q31_t)0x3d599c28, (q31_t)0x3ff1f30b, (q31_t)0x3d662a70, (q31_t)0x3ff27703, + (q31_t)0x3d72b8d2, (q31_t)0x3ff2f884, (q31_t)0x3d7f474d, (q31_t)0x3ff3778e, + (q31_t)0x3d8bd5e1, (q31_t)0x3ff3f420, (q31_t)0x3d98648d, (q31_t)0x3ff46e3c, + (q31_t)0x3da4f351, (q31_t)0x3ff4e5e0, (q31_t)0x3db1822c, (q31_t)0x3ff55b0d, + (q31_t)0x3dbe111e, (q31_t)0x3ff5cdc3, (q31_t)0x3dcaa027, (q31_t)0x3ff63e01, + (q31_t)0x3dd72f45, (q31_t)0x3ff6abc8, (q31_t)0x3de3be78, (q31_t)0x3ff71718, + (q31_t)0x3df04dc0, (q31_t)0x3ff77ff1, (q31_t)0x3dfcdd1d, (q31_t)0x3ff7e652, + (q31_t)0x3e096c8d, (q31_t)0x3ff84a3c, (q31_t)0x3e15fc11, (q31_t)0x3ff8abae, + (q31_t)0x3e228ba7, (q31_t)0x3ff90aaa, (q31_t)0x3e2f1b50, (q31_t)0x3ff9672d, + (q31_t)0x3e3bab0b, (q31_t)0x3ff9c13a, (q31_t)0x3e483ad8, (q31_t)0x3ffa18cf, + (q31_t)0x3e54cab5, (q31_t)0x3ffa6dec, (q31_t)0x3e615aa3, (q31_t)0x3ffac092, + (q31_t)0x3e6deaa1, (q31_t)0x3ffb10c1, (q31_t)0x3e7a7aae, (q31_t)0x3ffb5e78, + (q31_t)0x3e870aca, (q31_t)0x3ffba9b8, (q31_t)0x3e939af5, (q31_t)0x3ffbf280, + (q31_t)0x3ea02b2e, (q31_t)0x3ffc38d1, (q31_t)0x3eacbb74, (q31_t)0x3ffc7caa, + (q31_t)0x3eb94bc8, (q31_t)0x3ffcbe0c, (q31_t)0x3ec5dc28, (q31_t)0x3ffcfcf6, + (q31_t)0x3ed26c94, (q31_t)0x3ffd3969, (q31_t)0x3edefd0c, (q31_t)0x3ffd7364, + (q31_t)0x3eeb8d8f, (q31_t)0x3ffdaae7, (q31_t)0x3ef81e1d, (q31_t)0x3ffddff3, + (q31_t)0x3f04aeb5, (q31_t)0x3ffe1288, (q31_t)0x3f113f56, (q31_t)0x3ffe42a4, + (q31_t)0x3f1dd001, (q31_t)0x3ffe704a, (q31_t)0x3f2a60b4, (q31_t)0x3ffe9b77, + (q31_t)0x3f36f170, (q31_t)0x3ffec42d, (q31_t)0x3f438234, (q31_t)0x3ffeea6c, + (q31_t)0x3f5012fe, (q31_t)0x3fff0e32, (q31_t)0x3f5ca3d0, (q31_t)0x3fff2f82, + (q31_t)0x3f6934a8, (q31_t)0x3fff4e59, (q31_t)0x3f75c585, (q31_t)0x3fff6ab9, + (q31_t)0x3f825668, (q31_t)0x3fff84a1, (q31_t)0x3f8ee750, (q31_t)0x3fff9c12, + (q31_t)0x3f9b783c, (q31_t)0x3fffb10b, (q31_t)0x3fa8092c, (q31_t)0x3fffc38c, + (q31_t)0x3fb49a1f, (q31_t)0x3fffd396, (q31_t)0x3fc12b16, (q31_t)0x3fffe128, + (q31_t)0x3fcdbc0f, (q31_t)0x3fffec43, (q31_t)0x3fda4d09, (q31_t)0x3ffff4e6, + (q31_t)0x3fe6de05, (q31_t)0x3ffffb11, (q31_t)0x3ff36f02, (q31_t)0x3ffffec4, +}; + + +/** + @par + Generation of realCoefBQ31 array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q31 format + round(pBTable[i] * pow(2, 31)) + */ + +const q31_t realCoefBQ31[8192] = { + (q31_t)0x40000000, (q31_t)0x40000000, (q31_t)0x400c90fe, (q31_t)0x3ffffec4, + (q31_t)0x401921fb, (q31_t)0x3ffffb11, (q31_t)0x4025b2f7, (q31_t)0x3ffff4e6, + (q31_t)0x403243f1, (q31_t)0x3fffec43, (q31_t)0x403ed4ea, (q31_t)0x3fffe128, + (q31_t)0x404b65e1, (q31_t)0x3fffd396, (q31_t)0x4057f6d4, (q31_t)0x3fffc38c, + (q31_t)0x406487c4, (q31_t)0x3fffb10b, (q31_t)0x407118b0, (q31_t)0x3fff9c12, + (q31_t)0x407da998, (q31_t)0x3fff84a1, (q31_t)0x408a3a7b, (q31_t)0x3fff6ab9, + (q31_t)0x4096cb58, (q31_t)0x3fff4e59, (q31_t)0x40a35c30, (q31_t)0x3fff2f82, + (q31_t)0x40afed02, (q31_t)0x3fff0e32, (q31_t)0x40bc7dcc, (q31_t)0x3ffeea6c, + (q31_t)0x40c90e90, (q31_t)0x3ffec42d, (q31_t)0x40d59f4c, (q31_t)0x3ffe9b77, + (q31_t)0x40e22fff, (q31_t)0x3ffe704a, (q31_t)0x40eec0aa, (q31_t)0x3ffe42a4, + (q31_t)0x40fb514b, (q31_t)0x3ffe1288, (q31_t)0x4107e1e3, (q31_t)0x3ffddff3, + (q31_t)0x41147271, (q31_t)0x3ffdaae7, (q31_t)0x412102f4, (q31_t)0x3ffd7364, + (q31_t)0x412d936c, (q31_t)0x3ffd3969, (q31_t)0x413a23d8, (q31_t)0x3ffcfcf6, + (q31_t)0x4146b438, (q31_t)0x3ffcbe0c, (q31_t)0x4153448c, (q31_t)0x3ffc7caa, + (q31_t)0x415fd4d2, (q31_t)0x3ffc38d1, (q31_t)0x416c650b, (q31_t)0x3ffbf280, + (q31_t)0x4178f536, (q31_t)0x3ffba9b8, (q31_t)0x41858552, (q31_t)0x3ffb5e78, + (q31_t)0x4192155f, (q31_t)0x3ffb10c1, (q31_t)0x419ea55d, (q31_t)0x3ffac092, + (q31_t)0x41ab354b, (q31_t)0x3ffa6dec, (q31_t)0x41b7c528, (q31_t)0x3ffa18cf, + (q31_t)0x41c454f5, (q31_t)0x3ff9c13a, (q31_t)0x41d0e4b0, (q31_t)0x3ff9672d, + (q31_t)0x41dd7459, (q31_t)0x3ff90aaa, (q31_t)0x41ea03ef, (q31_t)0x3ff8abae, + (q31_t)0x41f69373, (q31_t)0x3ff84a3c, (q31_t)0x420322e3, (q31_t)0x3ff7e652, + (q31_t)0x420fb240, (q31_t)0x3ff77ff1, (q31_t)0x421c4188, (q31_t)0x3ff71718, + (q31_t)0x4228d0bb, (q31_t)0x3ff6abc8, (q31_t)0x42355fd9, (q31_t)0x3ff63e01, + (q31_t)0x4241eee2, (q31_t)0x3ff5cdc3, (q31_t)0x424e7dd4, (q31_t)0x3ff55b0d, + (q31_t)0x425b0caf, (q31_t)0x3ff4e5e0, (q31_t)0x42679b73, (q31_t)0x3ff46e3c, + (q31_t)0x42742a1f, (q31_t)0x3ff3f420, (q31_t)0x4280b8b3, (q31_t)0x3ff3778e, + (q31_t)0x428d472e, (q31_t)0x3ff2f884, (q31_t)0x4299d590, (q31_t)0x3ff27703, + (q31_t)0x42a663d8, (q31_t)0x3ff1f30b, (q31_t)0x42b2f207, (q31_t)0x3ff16c9c, + (q31_t)0x42bf801a, (q31_t)0x3ff0e3b6, (q31_t)0x42cc0e13, (q31_t)0x3ff05858, + (q31_t)0x42d89bf0, (q31_t)0x3fefca84, (q31_t)0x42e529b0, (q31_t)0x3fef3a39, + (q31_t)0x42f1b755, (q31_t)0x3feea776, (q31_t)0x42fe44dc, (q31_t)0x3fee123d, + (q31_t)0x430ad245, (q31_t)0x3fed7a8c, (q31_t)0x43175f91, (q31_t)0x3fece065, + (q31_t)0x4323ecbe, (q31_t)0x3fec43c7, (q31_t)0x433079cc, (q31_t)0x3feba4b2, + (q31_t)0x433d06bb, (q31_t)0x3feb0326, (q31_t)0x43499389, (q31_t)0x3fea5f23, + (q31_t)0x43562038, (q31_t)0x3fe9b8a9, (q31_t)0x4362acc5, (q31_t)0x3fe90fb9, + (q31_t)0x436f3931, (q31_t)0x3fe86452, (q31_t)0x437bc57b, (q31_t)0x3fe7b674, + (q31_t)0x438851a2, (q31_t)0x3fe7061f, (q31_t)0x4394dda7, (q31_t)0x3fe65354, + (q31_t)0x43a16988, (q31_t)0x3fe59e12, (q31_t)0x43adf546, (q31_t)0x3fe4e659, + (q31_t)0x43ba80df, (q31_t)0x3fe42c2a, (q31_t)0x43c70c54, (q31_t)0x3fe36f84, + (q31_t)0x43d397a3, (q31_t)0x3fe2b067, (q31_t)0x43e022cc, (q31_t)0x3fe1eed5, + (q31_t)0x43ecadcf, (q31_t)0x3fe12acb, (q31_t)0x43f938ac, (q31_t)0x3fe0644b, + (q31_t)0x4405c361, (q31_t)0x3fdf9b55, (q31_t)0x44124dee, (q31_t)0x3fdecfe8, + (q31_t)0x441ed854, (q31_t)0x3fde0205, (q31_t)0x442b6290, (q31_t)0x3fdd31ac, + (q31_t)0x4437eca4, (q31_t)0x3fdc5edc, (q31_t)0x4444768d, (q31_t)0x3fdb8996, + (q31_t)0x4451004d, (q31_t)0x3fdab1d9, (q31_t)0x445d89e2, (q31_t)0x3fd9d7a7, + (q31_t)0x446a134c, (q31_t)0x3fd8fafe, (q31_t)0x44769c8b, (q31_t)0x3fd81bdf, + (q31_t)0x4483259d, (q31_t)0x3fd73a4a, (q31_t)0x448fae83, (q31_t)0x3fd6563f, + (q31_t)0x449c373c, (q31_t)0x3fd56fbe, (q31_t)0x44a8bfc7, (q31_t)0x3fd486c7, + (q31_t)0x44b54825, (q31_t)0x3fd39b5a, (q31_t)0x44c1d054, (q31_t)0x3fd2ad77, + (q31_t)0x44ce5854, (q31_t)0x3fd1bd1e, (q31_t)0x44dae024, (q31_t)0x3fd0ca4f, + (q31_t)0x44e767c5, (q31_t)0x3fcfd50b, (q31_t)0x44f3ef35, (q31_t)0x3fcedd50, + (q31_t)0x45007674, (q31_t)0x3fcde320, (q31_t)0x450cfd82, (q31_t)0x3fcce67a, + (q31_t)0x4519845e, (q31_t)0x3fcbe75e, (q31_t)0x45260b08, (q31_t)0x3fcae5cd, + (q31_t)0x4532917f, (q31_t)0x3fc9e1c6, (q31_t)0x453f17c3, (q31_t)0x3fc8db4a, + (q31_t)0x454b9dd3, (q31_t)0x3fc7d258, (q31_t)0x455823ae, (q31_t)0x3fc6c6f0, + (q31_t)0x4564a955, (q31_t)0x3fc5b913, (q31_t)0x45712ec7, (q31_t)0x3fc4a8c1, + (q31_t)0x457db403, (q31_t)0x3fc395f9, (q31_t)0x458a3908, (q31_t)0x3fc280bc, + (q31_t)0x4596bdd7, (q31_t)0x3fc1690a, (q31_t)0x45a3426f, (q31_t)0x3fc04ee3, + (q31_t)0x45afc6d0, (q31_t)0x3fbf3246, (q31_t)0x45bc4af8, (q31_t)0x3fbe1334, + (q31_t)0x45c8cee7, (q31_t)0x3fbcf1ad, (q31_t)0x45d5529e, (q31_t)0x3fbbcdb1, + (q31_t)0x45e1d61b, (q31_t)0x3fbaa740, (q31_t)0x45ee595d, (q31_t)0x3fb97e5a, + (q31_t)0x45fadc66, (q31_t)0x3fb852ff, (q31_t)0x46075f33, (q31_t)0x3fb7252f, + (q31_t)0x4613e1c5, (q31_t)0x3fb5f4ea, (q31_t)0x4620641a, (q31_t)0x3fb4c231, + (q31_t)0x462ce634, (q31_t)0x3fb38d02, (q31_t)0x46396810, (q31_t)0x3fb2555f, + (q31_t)0x4645e9af, (q31_t)0x3fb11b48, (q31_t)0x46526b10, (q31_t)0x3fafdebb, + (q31_t)0x465eec33, (q31_t)0x3fae9fbb, (q31_t)0x466b6d16, (q31_t)0x3fad5e45, + (q31_t)0x4677edbb, (q31_t)0x3fac1a5b, (q31_t)0x46846e1f, (q31_t)0x3faad3fd, + (q31_t)0x4690ee44, (q31_t)0x3fa98b2a, (q31_t)0x469d6e27, (q31_t)0x3fa83fe3, + (q31_t)0x46a9edc9, (q31_t)0x3fa6f228, (q31_t)0x46b66d29, (q31_t)0x3fa5a1f9, + (q31_t)0x46c2ec48, (q31_t)0x3fa44f55, (q31_t)0x46cf6b23, (q31_t)0x3fa2fa3d, + (q31_t)0x46dbe9bb, (q31_t)0x3fa1a2b2, (q31_t)0x46e86810, (q31_t)0x3fa048b2, + (q31_t)0x46f4e620, (q31_t)0x3f9eec3e, (q31_t)0x470163eb, (q31_t)0x3f9d8d56, + (q31_t)0x470de172, (q31_t)0x3f9c2bfb, (q31_t)0x471a5eb3, (q31_t)0x3f9ac82c, + (q31_t)0x4726dbae, (q31_t)0x3f9961e8, (q31_t)0x47335862, (q31_t)0x3f97f932, + (q31_t)0x473fd4cf, (q31_t)0x3f968e07, (q31_t)0x474c50f4, (q31_t)0x3f952069, + (q31_t)0x4758ccd2, (q31_t)0x3f93b058, (q31_t)0x47654867, (q31_t)0x3f923dd2, + (q31_t)0x4771c3b3, (q31_t)0x3f90c8da, (q31_t)0x477e3eb5, (q31_t)0x3f8f516e, + (q31_t)0x478ab96e, (q31_t)0x3f8dd78f, (q31_t)0x479733dc, (q31_t)0x3f8c5b3d, + (q31_t)0x47a3adff, (q31_t)0x3f8adc77, (q31_t)0x47b027d7, (q31_t)0x3f895b3e, + (q31_t)0x47bca163, (q31_t)0x3f87d792, (q31_t)0x47c91aa3, (q31_t)0x3f865174, + (q31_t)0x47d59396, (q31_t)0x3f84c8e2, (q31_t)0x47e20c3b, (q31_t)0x3f833ddd, + (q31_t)0x47ee8493, (q31_t)0x3f81b065, (q31_t)0x47fafc9c, (q31_t)0x3f80207b, + (q31_t)0x48077457, (q31_t)0x3f7e8e1e, (q31_t)0x4813ebc2, (q31_t)0x3f7cf94e, + (q31_t)0x482062de, (q31_t)0x3f7b620c, (q31_t)0x482cd9a9, (q31_t)0x3f79c857, + (q31_t)0x48395024, (q31_t)0x3f782c30, (q31_t)0x4845c64d, (q31_t)0x3f768d96, + (q31_t)0x48523c25, (q31_t)0x3f74ec8a, (q31_t)0x485eb1ab, (q31_t)0x3f73490b, + (q31_t)0x486b26de, (q31_t)0x3f71a31b, (q31_t)0x48779bbe, (q31_t)0x3f6ffab8, + (q31_t)0x4884104b, (q31_t)0x3f6e4fe3, (q31_t)0x48908483, (q31_t)0x3f6ca29c, + (q31_t)0x489cf867, (q31_t)0x3f6af2e3, (q31_t)0x48a96bf6, (q31_t)0x3f6940b8, + (q31_t)0x48b5df30, (q31_t)0x3f678c1c, (q31_t)0x48c25213, (q31_t)0x3f65d50d, + (q31_t)0x48cec4a0, (q31_t)0x3f641b8d, (q31_t)0x48db36d6, (q31_t)0x3f625f9b, + (q31_t)0x48e7a8b5, (q31_t)0x3f60a138, (q31_t)0x48f41a3c, (q31_t)0x3f5ee063, + (q31_t)0x49008b6a, (q31_t)0x3f5d1d1d, (q31_t)0x490cfc40, (q31_t)0x3f5b5765, + (q31_t)0x49196cbc, (q31_t)0x3f598f3c, (q31_t)0x4925dcdf, (q31_t)0x3f57c4a2, + (q31_t)0x49324ca7, (q31_t)0x3f55f796, (q31_t)0x493ebc14, (q31_t)0x3f54281a, + (q31_t)0x494b2b27, (q31_t)0x3f52562c, (q31_t)0x495799dd, (q31_t)0x3f5081cd, + (q31_t)0x49640837, (q31_t)0x3f4eaafe, (q31_t)0x49707635, (q31_t)0x3f4cd1be, + (q31_t)0x497ce3d5, (q31_t)0x3f4af60d, (q31_t)0x49895118, (q31_t)0x3f4917eb, + (q31_t)0x4995bdfd, (q31_t)0x3f473759, (q31_t)0x49a22a83, (q31_t)0x3f455456, + (q31_t)0x49ae96aa, (q31_t)0x3f436ee3, (q31_t)0x49bb0271, (q31_t)0x3f4186ff, + (q31_t)0x49c76dd8, (q31_t)0x3f3f9cab, (q31_t)0x49d3d8df, (q31_t)0x3f3dafe7, + (q31_t)0x49e04385, (q31_t)0x3f3bc0b3, (q31_t)0x49ecadc9, (q31_t)0x3f39cf0e, + (q31_t)0x49f917ac, (q31_t)0x3f37dafa, (q31_t)0x4a05812c, (q31_t)0x3f35e476, + (q31_t)0x4a11ea49, (q31_t)0x3f33eb81, (q31_t)0x4a1e5303, (q31_t)0x3f31f01d, + (q31_t)0x4a2abb59, (q31_t)0x3f2ff24a, (q31_t)0x4a37234a, (q31_t)0x3f2df206, + (q31_t)0x4a438ad7, (q31_t)0x3f2bef53, (q31_t)0x4a4ff1fe, (q31_t)0x3f29ea31, + (q31_t)0x4a5c58c0, (q31_t)0x3f27e29f, (q31_t)0x4a68bf1b, (q31_t)0x3f25d89e, + (q31_t)0x4a752510, (q31_t)0x3f23cc2e, (q31_t)0x4a818a9d, (q31_t)0x3f21bd4e, + (q31_t)0x4a8defc3, (q31_t)0x3f1fabff, (q31_t)0x4a9a5480, (q31_t)0x3f1d9842, + (q31_t)0x4aa6b8d5, (q31_t)0x3f1b8215, (q31_t)0x4ab31cc1, (q31_t)0x3f19697a, + (q31_t)0x4abf8043, (q31_t)0x3f174e70, (q31_t)0x4acbe35b, (q31_t)0x3f1530f7, + (q31_t)0x4ad84609, (q31_t)0x3f13110f, (q31_t)0x4ae4a84b, (q31_t)0x3f10eeb9, + (q31_t)0x4af10a22, (q31_t)0x3f0ec9f5, (q31_t)0x4afd6b8d, (q31_t)0x3f0ca2c2, + (q31_t)0x4b09cc8c, (q31_t)0x3f0a7921, (q31_t)0x4b162d1d, (q31_t)0x3f084d12, + (q31_t)0x4b228d42, (q31_t)0x3f061e95, (q31_t)0x4b2eecf8, (q31_t)0x3f03eda9, + (q31_t)0x4b3b4c40, (q31_t)0x3f01ba50, (q31_t)0x4b47ab19, (q31_t)0x3eff8489, + (q31_t)0x4b540982, (q31_t)0x3efd4c54, (q31_t)0x4b60677c, (q31_t)0x3efb11b1, + (q31_t)0x4b6cc506, (q31_t)0x3ef8d4a1, (q31_t)0x4b79221f, (q31_t)0x3ef69523, + (q31_t)0x4b857ec7, (q31_t)0x3ef45338, (q31_t)0x4b91dafc, (q31_t)0x3ef20ee0, + (q31_t)0x4b9e36c0, (q31_t)0x3eefc81a, (q31_t)0x4baa9211, (q31_t)0x3eed7ee7, + (q31_t)0x4bb6ecef, (q31_t)0x3eeb3347, (q31_t)0x4bc34759, (q31_t)0x3ee8e53a, + (q31_t)0x4bcfa150, (q31_t)0x3ee694c1, (q31_t)0x4bdbfad1, (q31_t)0x3ee441da, + (q31_t)0x4be853de, (q31_t)0x3ee1ec87, (q31_t)0x4bf4ac75, (q31_t)0x3edf94c7, + (q31_t)0x4c010496, (q31_t)0x3edd3a9a, (q31_t)0x4c0d5c41, (q31_t)0x3edade01, + (q31_t)0x4c19b374, (q31_t)0x3ed87efc, (q31_t)0x4c260a31, (q31_t)0x3ed61d8a, + (q31_t)0x4c326075, (q31_t)0x3ed3b9ad, (q31_t)0x4c3eb641, (q31_t)0x3ed15363, + (q31_t)0x4c4b0b94, (q31_t)0x3eceeaad, (q31_t)0x4c57606e, (q31_t)0x3ecc7f8b, + (q31_t)0x4c63b4ce, (q31_t)0x3eca11fe, (q31_t)0x4c7008b3, (q31_t)0x3ec7a205, + (q31_t)0x4c7c5c1e, (q31_t)0x3ec52fa0, (q31_t)0x4c88af0e, (q31_t)0x3ec2bad0, + (q31_t)0x4c950182, (q31_t)0x3ec04394, (q31_t)0x4ca1537a, (q31_t)0x3ebdc9ed, + (q31_t)0x4cada4f5, (q31_t)0x3ebb4ddb, (q31_t)0x4cb9f5f3, (q31_t)0x3eb8cf5d, + (q31_t)0x4cc64673, (q31_t)0x3eb64e75, (q31_t)0x4cd29676, (q31_t)0x3eb3cb21, + (q31_t)0x4cdee5f9, (q31_t)0x3eb14563, (q31_t)0x4ceb34fe, (q31_t)0x3eaebd3a, + (q31_t)0x4cf78383, (q31_t)0x3eac32a6, (q31_t)0x4d03d189, (q31_t)0x3ea9a5a8, + (q31_t)0x4d101f0e, (q31_t)0x3ea7163f, (q31_t)0x4d1c6c11, (q31_t)0x3ea4846c, + (q31_t)0x4d28b894, (q31_t)0x3ea1f02f, (q31_t)0x4d350495, (q31_t)0x3e9f5988, + (q31_t)0x4d415013, (q31_t)0x3e9cc076, (q31_t)0x4d4d9b0e, (q31_t)0x3e9a24fb, + (q31_t)0x4d59e586, (q31_t)0x3e978715, (q31_t)0x4d662f7b, (q31_t)0x3e94e6c6, + (q31_t)0x4d7278eb, (q31_t)0x3e92440d, (q31_t)0x4d7ec1d6, (q31_t)0x3e8f9eeb, + (q31_t)0x4d8b0a3d, (q31_t)0x3e8cf75f, (q31_t)0x4d97521d, (q31_t)0x3e8a4d6a, + (q31_t)0x4da39978, (q31_t)0x3e87a10c, (q31_t)0x4dafe04b, (q31_t)0x3e84f245, + (q31_t)0x4dbc2698, (q31_t)0x3e824114, (q31_t)0x4dc86c5d, (q31_t)0x3e7f8d7b, + (q31_t)0x4dd4b19a, (q31_t)0x3e7cd778, (q31_t)0x4de0f64f, (q31_t)0x3e7a1f0d, + (q31_t)0x4ded3a7b, (q31_t)0x3e77643a, (q31_t)0x4df97e1d, (q31_t)0x3e74a6fd, + (q31_t)0x4e05c135, (q31_t)0x3e71e759, (q31_t)0x4e1203c3, (q31_t)0x3e6f254c, + (q31_t)0x4e1e45c6, (q31_t)0x3e6c60d7, (q31_t)0x4e2a873e, (q31_t)0x3e6999fa, + (q31_t)0x4e36c82a, (q31_t)0x3e66d0b4, (q31_t)0x4e430889, (q31_t)0x3e640507, + (q31_t)0x4e4f485c, (q31_t)0x3e6136f3, (q31_t)0x4e5b87a2, (q31_t)0x3e5e6676, + (q31_t)0x4e67c65a, (q31_t)0x3e5b9392, (q31_t)0x4e740483, (q31_t)0x3e58be47, + (q31_t)0x4e80421e, (q31_t)0x3e55e694, (q31_t)0x4e8c7f2a, (q31_t)0x3e530c7a, + (q31_t)0x4e98bba7, (q31_t)0x3e502ff9, (q31_t)0x4ea4f793, (q31_t)0x3e4d5110, + (q31_t)0x4eb132ef, (q31_t)0x3e4a6fc1, (q31_t)0x4ebd6db9, (q31_t)0x3e478c0b, + (q31_t)0x4ec9a7f3, (q31_t)0x3e44a5ef, (q31_t)0x4ed5e19a, (q31_t)0x3e41bd6c, + (q31_t)0x4ee21aaf, (q31_t)0x3e3ed282, (q31_t)0x4eee5331, (q31_t)0x3e3be532, + (q31_t)0x4efa8b20, (q31_t)0x3e38f57c, (q31_t)0x4f06c27a, (q31_t)0x3e360360, + (q31_t)0x4f12f941, (q31_t)0x3e330ede, (q31_t)0x4f1f2f73, (q31_t)0x3e3017f6, + (q31_t)0x4f2b650f, (q31_t)0x3e2d1ea8, (q31_t)0x4f379a16, (q31_t)0x3e2a22f4, + (q31_t)0x4f43ce86, (q31_t)0x3e2724db, (q31_t)0x4f500260, (q31_t)0x3e24245d, + (q31_t)0x4f5c35a3, (q31_t)0x3e212179, (q31_t)0x4f68684e, (q31_t)0x3e1e1c30, + (q31_t)0x4f749a61, (q31_t)0x3e1b1482, (q31_t)0x4f80cbdc, (q31_t)0x3e180a6f, + (q31_t)0x4f8cfcbe, (q31_t)0x3e14fdf7, (q31_t)0x4f992d06, (q31_t)0x3e11ef1b, + (q31_t)0x4fa55cb4, (q31_t)0x3e0eddd9, (q31_t)0x4fb18bc8, (q31_t)0x3e0bca34, + (q31_t)0x4fbdba40, (q31_t)0x3e08b42a, (q31_t)0x4fc9e81e, (q31_t)0x3e059bbb, + (q31_t)0x4fd6155f, (q31_t)0x3e0280e9, (q31_t)0x4fe24205, (q31_t)0x3dff63b2, + (q31_t)0x4fee6e0d, (q31_t)0x3dfc4418, (q31_t)0x4ffa9979, (q31_t)0x3df9221a, + (q31_t)0x5006c446, (q31_t)0x3df5fdb8, (q31_t)0x5012ee76, (q31_t)0x3df2d6f3, + (q31_t)0x501f1807, (q31_t)0x3defadca, (q31_t)0x502b40f8, (q31_t)0x3dec823e, + (q31_t)0x5037694b, (q31_t)0x3de9544f, (q31_t)0x504390fd, (q31_t)0x3de623fd, + (q31_t)0x504fb80e, (q31_t)0x3de2f148, (q31_t)0x505bde7f, (q31_t)0x3ddfbc30, + (q31_t)0x5068044e, (q31_t)0x3ddc84b5, (q31_t)0x5074297b, (q31_t)0x3dd94ad8, + (q31_t)0x50804e06, (q31_t)0x3dd60e99, (q31_t)0x508c71ee, (q31_t)0x3dd2cff7, + (q31_t)0x50989532, (q31_t)0x3dcf8ef3, (q31_t)0x50a4b7d3, (q31_t)0x3dcc4b8d, + (q31_t)0x50b0d9d0, (q31_t)0x3dc905c5, (q31_t)0x50bcfb28, (q31_t)0x3dc5bd9b, + (q31_t)0x50c91bda, (q31_t)0x3dc2730f, (q31_t)0x50d53be7, (q31_t)0x3dbf2622, + (q31_t)0x50e15b4e, (q31_t)0x3dbbd6d4, (q31_t)0x50ed7a0e, (q31_t)0x3db88524, + (q31_t)0x50f99827, (q31_t)0x3db53113, (q31_t)0x5105b599, (q31_t)0x3db1daa2, + (q31_t)0x5111d263, (q31_t)0x3dae81cf, (q31_t)0x511dee84, (q31_t)0x3dab269b, + (q31_t)0x512a09fc, (q31_t)0x3da7c907, (q31_t)0x513624cb, (q31_t)0x3da46912, + (q31_t)0x51423ef0, (q31_t)0x3da106bd, (q31_t)0x514e586a, (q31_t)0x3d9da208, + (q31_t)0x515a713a, (q31_t)0x3d9a3af2, (q31_t)0x5166895f, (q31_t)0x3d96d17d, + (q31_t)0x5172a0d7, (q31_t)0x3d9365a8, (q31_t)0x517eb7a4, (q31_t)0x3d8ff772, + (q31_t)0x518acdc4, (q31_t)0x3d8c86de, (q31_t)0x5196e337, (q31_t)0x3d8913ea, + (q31_t)0x51a2f7fc, (q31_t)0x3d859e96, (q31_t)0x51af0c13, (q31_t)0x3d8226e4, + (q31_t)0x51bb1f7c, (q31_t)0x3d7eacd2, (q31_t)0x51c73235, (q31_t)0x3d7b3061, + (q31_t)0x51d3443f, (q31_t)0x3d77b192, (q31_t)0x51df5599, (q31_t)0x3d743064, + (q31_t)0x51eb6643, (q31_t)0x3d70acd7, (q31_t)0x51f7763c, (q31_t)0x3d6d26ec, + (q31_t)0x52038584, (q31_t)0x3d699ea3, (q31_t)0x520f941a, (q31_t)0x3d6613fb, + (q31_t)0x521ba1fd, (q31_t)0x3d6286f6, (q31_t)0x5227af2e, (q31_t)0x3d5ef793, + (q31_t)0x5233bbac, (q31_t)0x3d5b65d2, (q31_t)0x523fc776, (q31_t)0x3d57d1b3, + (q31_t)0x524bd28c, (q31_t)0x3d543b37, (q31_t)0x5257dced, (q31_t)0x3d50a25e, + (q31_t)0x5263e699, (q31_t)0x3d4d0728, (q31_t)0x526fef90, (q31_t)0x3d496994, + (q31_t)0x527bf7d1, (q31_t)0x3d45c9a4, (q31_t)0x5287ff5b, (q31_t)0x3d422757, + (q31_t)0x5294062f, (q31_t)0x3d3e82ae, (q31_t)0x52a00c4b, (q31_t)0x3d3adba7, + (q31_t)0x52ac11af, (q31_t)0x3d373245, (q31_t)0x52b8165b, (q31_t)0x3d338687, + (q31_t)0x52c41a4f, (q31_t)0x3d2fd86c, (q31_t)0x52d01d89, (q31_t)0x3d2c27f6, + (q31_t)0x52dc2009, (q31_t)0x3d287523, (q31_t)0x52e821cf, (q31_t)0x3d24bff6, + (q31_t)0x52f422db, (q31_t)0x3d21086c, (q31_t)0x5300232c, (q31_t)0x3d1d4e88, + (q31_t)0x530c22c1, (q31_t)0x3d199248, (q31_t)0x5318219a, (q31_t)0x3d15d3ad, + (q31_t)0x53241fb6, (q31_t)0x3d1212b7, (q31_t)0x53301d16, (q31_t)0x3d0e4f67, + (q31_t)0x533c19b8, (q31_t)0x3d0a89bc, (q31_t)0x5348159d, (q31_t)0x3d06c1b6, + (q31_t)0x535410c3, (q31_t)0x3d02f757, (q31_t)0x53600b2a, (q31_t)0x3cff2a9d, + (q31_t)0x536c04d2, (q31_t)0x3cfb5b89, (q31_t)0x5377fdbb, (q31_t)0x3cf78a1b, + (q31_t)0x5383f5e3, (q31_t)0x3cf3b653, (q31_t)0x538fed4b, (q31_t)0x3cefe032, + (q31_t)0x539be3f2, (q31_t)0x3cec07b8, (q31_t)0x53a7d9d7, (q31_t)0x3ce82ce4, + (q31_t)0x53b3cefa, (q31_t)0x3ce44fb7, (q31_t)0x53bfc35b, (q31_t)0x3ce07031, + (q31_t)0x53cbb6f8, (q31_t)0x3cdc8e52, (q31_t)0x53d7a9d3, (q31_t)0x3cd8aa1b, + (q31_t)0x53e39be9, (q31_t)0x3cd4c38b, (q31_t)0x53ef8d3c, (q31_t)0x3cd0daa2, + (q31_t)0x53fb7dc9, (q31_t)0x3cccef62, (q31_t)0x54076d91, (q31_t)0x3cc901c9, + (q31_t)0x54135c94, (q31_t)0x3cc511d9, (q31_t)0x541f4ad1, (q31_t)0x3cc11f90, + (q31_t)0x542b3846, (q31_t)0x3cbd2af0, (q31_t)0x543724f5, (q31_t)0x3cb933f9, + (q31_t)0x544310dd, (q31_t)0x3cb53aaa, (q31_t)0x544efbfc, (q31_t)0x3cb13f04, + (q31_t)0x545ae653, (q31_t)0x3cad4107, (q31_t)0x5466cfe1, (q31_t)0x3ca940b3, + (q31_t)0x5472b8a5, (q31_t)0x3ca53e09, (q31_t)0x547ea0a0, (q31_t)0x3ca13908, + (q31_t)0x548a87d1, (q31_t)0x3c9d31b0, (q31_t)0x54966e36, (q31_t)0x3c992803, + (q31_t)0x54a253d1, (q31_t)0x3c951bff, (q31_t)0x54ae38a0, (q31_t)0x3c910da5, + (q31_t)0x54ba1ca3, (q31_t)0x3c8cfcf6, (q31_t)0x54c5ffd9, (q31_t)0x3c88e9f1, + (q31_t)0x54d1e242, (q31_t)0x3c84d496, (q31_t)0x54ddc3de, (q31_t)0x3c80bce7, + (q31_t)0x54e9a4ac, (q31_t)0x3c7ca2e2, (q31_t)0x54f584ac, (q31_t)0x3c788688, + (q31_t)0x550163dc, (q31_t)0x3c7467d9, (q31_t)0x550d423d, (q31_t)0x3c7046d6, + (q31_t)0x55191fcf, (q31_t)0x3c6c237e, (q31_t)0x5524fc90, (q31_t)0x3c67fdd1, + (q31_t)0x5530d881, (q31_t)0x3c63d5d1, (q31_t)0x553cb3a0, (q31_t)0x3c5fab7c, + (q31_t)0x55488dee, (q31_t)0x3c5b7ed4, (q31_t)0x5554676a, (q31_t)0x3c574fd8, + (q31_t)0x55604013, (q31_t)0x3c531e88, (q31_t)0x556c17e9, (q31_t)0x3c4eeae5, + (q31_t)0x5577eeec, (q31_t)0x3c4ab4ef, (q31_t)0x5583c51b, (q31_t)0x3c467ca6, + (q31_t)0x558f9a76, (q31_t)0x3c42420a, (q31_t)0x559b6efb, (q31_t)0x3c3e051b, + (q31_t)0x55a742ac, (q31_t)0x3c39c5da, (q31_t)0x55b31587, (q31_t)0x3c358446, + (q31_t)0x55bee78c, (q31_t)0x3c314060, (q31_t)0x55cab8ba, (q31_t)0x3c2cfa28, + (q31_t)0x55d68911, (q31_t)0x3c28b19e, (q31_t)0x55e25890, (q31_t)0x3c2466c2, + (q31_t)0x55ee2738, (q31_t)0x3c201994, (q31_t)0x55f9f507, (q31_t)0x3c1bca16, + (q31_t)0x5605c1fd, (q31_t)0x3c177845, (q31_t)0x56118e1a, (q31_t)0x3c132424, + (q31_t)0x561d595d, (q31_t)0x3c0ecdb2, (q31_t)0x562923c5, (q31_t)0x3c0a74f0, + (q31_t)0x5634ed53, (q31_t)0x3c0619dc, (q31_t)0x5640b606, (q31_t)0x3c01bc78, + (q31_t)0x564c7ddd, (q31_t)0x3bfd5cc4, (q31_t)0x565844d8, (q31_t)0x3bf8fac0, + (q31_t)0x56640af7, (q31_t)0x3bf4966c, (q31_t)0x566fd039, (q31_t)0x3bf02fc9, + (q31_t)0x567b949d, (q31_t)0x3bebc6d5, (q31_t)0x56875823, (q31_t)0x3be75b93, + (q31_t)0x56931acb, (q31_t)0x3be2ee01, (q31_t)0x569edc94, (q31_t)0x3bde7e20, + (q31_t)0x56aa9d7e, (q31_t)0x3bda0bf0, (q31_t)0x56b65d88, (q31_t)0x3bd59771, + (q31_t)0x56c21cb2, (q31_t)0x3bd120a4, (q31_t)0x56cddafb, (q31_t)0x3bcca789, + (q31_t)0x56d99864, (q31_t)0x3bc82c1f, (q31_t)0x56e554ea, (q31_t)0x3bc3ae67, + (q31_t)0x56f1108f, (q31_t)0x3bbf2e62, (q31_t)0x56fccb51, (q31_t)0x3bbaac0e, + (q31_t)0x57088531, (q31_t)0x3bb6276e, (q31_t)0x57143e2d, (q31_t)0x3bb1a080, + (q31_t)0x571ff646, (q31_t)0x3bad1744, (q31_t)0x572bad7a, (q31_t)0x3ba88bbc, + (q31_t)0x573763c9, (q31_t)0x3ba3fde7, (q31_t)0x57431933, (q31_t)0x3b9f6dc5, + (q31_t)0x574ecdb8, (q31_t)0x3b9adb57, (q31_t)0x575a8157, (q31_t)0x3b96469d, + (q31_t)0x5766340f, (q31_t)0x3b91af97, (q31_t)0x5771e5e0, (q31_t)0x3b8d1644, + (q31_t)0x577d96ca, (q31_t)0x3b887aa6, (q31_t)0x578946cc, (q31_t)0x3b83dcbc, + (q31_t)0x5794f5e6, (q31_t)0x3b7f3c87, (q31_t)0x57a0a417, (q31_t)0x3b7a9a07, + (q31_t)0x57ac515f, (q31_t)0x3b75f53c, (q31_t)0x57b7fdbd, (q31_t)0x3b714e25, + (q31_t)0x57c3a931, (q31_t)0x3b6ca4c4, (q31_t)0x57cf53bb, (q31_t)0x3b67f919, + (q31_t)0x57dafd59, (q31_t)0x3b634b23, (q31_t)0x57e6a60c, (q31_t)0x3b5e9ae4, + (q31_t)0x57f24dd3, (q31_t)0x3b59e85a, (q31_t)0x57fdf4ae, (q31_t)0x3b553386, + (q31_t)0x58099a9c, (q31_t)0x3b507c69, (q31_t)0x58153f9d, (q31_t)0x3b4bc303, + (q31_t)0x5820e3b0, (q31_t)0x3b470753, (q31_t)0x582c86d5, (q31_t)0x3b42495a, + (q31_t)0x5838290c, (q31_t)0x3b3d8918, (q31_t)0x5843ca53, (q31_t)0x3b38c68e, + (q31_t)0x584f6aab, (q31_t)0x3b3401bb, (q31_t)0x585b0a13, (q31_t)0x3b2f3aa0, + (q31_t)0x5866a88a, (q31_t)0x3b2a713d, (q31_t)0x58724611, (q31_t)0x3b25a591, + (q31_t)0x587de2a7, (q31_t)0x3b20d79e, (q31_t)0x58897e4a, (q31_t)0x3b1c0764, + (q31_t)0x589518fc, (q31_t)0x3b1734e2, (q31_t)0x58a0b2bb, (q31_t)0x3b126019, + (q31_t)0x58ac4b87, (q31_t)0x3b0d8909, (q31_t)0x58b7e35f, (q31_t)0x3b08afb2, + (q31_t)0x58c37a44, (q31_t)0x3b03d414, (q31_t)0x58cf1034, (q31_t)0x3afef630, + (q31_t)0x58daa52f, (q31_t)0x3afa1605, (q31_t)0x58e63935, (q31_t)0x3af53395, + (q31_t)0x58f1cc45, (q31_t)0x3af04edf, (q31_t)0x58fd5e5f, (q31_t)0x3aeb67e3, + (q31_t)0x5908ef82, (q31_t)0x3ae67ea1, (q31_t)0x59147fae, (q31_t)0x3ae1931a, + (q31_t)0x59200ee3, (q31_t)0x3adca54e, (q31_t)0x592b9d1f, (q31_t)0x3ad7b53d, + (q31_t)0x59372a64, (q31_t)0x3ad2c2e8, (q31_t)0x5942b6af, (q31_t)0x3acdce4d, + (q31_t)0x594e4201, (q31_t)0x3ac8d76f, (q31_t)0x5959cc5a, (q31_t)0x3ac3de4c, + (q31_t)0x596555b8, (q31_t)0x3abee2e5, (q31_t)0x5970de1b, (q31_t)0x3ab9e53a, + (q31_t)0x597c6584, (q31_t)0x3ab4e54c, (q31_t)0x5987ebf0, (q31_t)0x3aafe31b, + (q31_t)0x59937161, (q31_t)0x3aaadea6, (q31_t)0x599ef5d6, (q31_t)0x3aa5d7ee, + (q31_t)0x59aa794d, (q31_t)0x3aa0cef3, (q31_t)0x59b5fbc8, (q31_t)0x3a9bc3b6, + (q31_t)0x59c17d44, (q31_t)0x3a96b636, (q31_t)0x59ccfdc2, (q31_t)0x3a91a674, + (q31_t)0x59d87d42, (q31_t)0x3a8c9470, (q31_t)0x59e3fbc3, (q31_t)0x3a87802a, + (q31_t)0x59ef7944, (q31_t)0x3a8269a3, (q31_t)0x59faf5c5, (q31_t)0x3a7d50da, + (q31_t)0x5a067145, (q31_t)0x3a7835cf, (q31_t)0x5a11ebc5, (q31_t)0x3a731884, + (q31_t)0x5a1d6544, (q31_t)0x3a6df8f8, (q31_t)0x5a28ddc0, (q31_t)0x3a68d72b, + (q31_t)0x5a34553b, (q31_t)0x3a63b31d, (q31_t)0x5a3fcbb3, (q31_t)0x3a5e8cd0, + (q31_t)0x5a4b4128, (q31_t)0x3a596442, (q31_t)0x5a56b599, (q31_t)0x3a543974, + (q31_t)0x5a622907, (q31_t)0x3a4f0c67, (q31_t)0x5a6d9b70, (q31_t)0x3a49dd1a, + (q31_t)0x5a790cd4, (q31_t)0x3a44ab8e, (q31_t)0x5a847d33, (q31_t)0x3a3f77c3, + (q31_t)0x5a8fec8c, (q31_t)0x3a3a41b9, (q31_t)0x5a9b5adf, (q31_t)0x3a350970, + (q31_t)0x5aa6c82b, (q31_t)0x3a2fcee8, (q31_t)0x5ab23471, (q31_t)0x3a2a9223, + (q31_t)0x5abd9faf, (q31_t)0x3a25531f, (q31_t)0x5ac909e5, (q31_t)0x3a2011de, + (q31_t)0x5ad47312, (q31_t)0x3a1ace5f, (q31_t)0x5adfdb37, (q31_t)0x3a1588a2, + (q31_t)0x5aeb4253, (q31_t)0x3a1040a8, (q31_t)0x5af6a865, (q31_t)0x3a0af671, + (q31_t)0x5b020d6c, (q31_t)0x3a05a9fd, (q31_t)0x5b0d716a, (q31_t)0x3a005b4d, + (q31_t)0x5b18d45c, (q31_t)0x39fb0a60, (q31_t)0x5b243643, (q31_t)0x39f5b737, + (q31_t)0x5b2f971e, (q31_t)0x39f061d2, (q31_t)0x5b3af6ec, (q31_t)0x39eb0a31, + (q31_t)0x5b4655ae, (q31_t)0x39e5b054, (q31_t)0x5b51b363, (q31_t)0x39e0543c, + (q31_t)0x5b5d100a, (q31_t)0x39daf5e8, (q31_t)0x5b686ba3, (q31_t)0x39d5955a, + (q31_t)0x5b73c62d, (q31_t)0x39d03291, (q31_t)0x5b7f1fa9, (q31_t)0x39cacd8d, + (q31_t)0x5b8a7815, (q31_t)0x39c5664f, (q31_t)0x5b95cf71, (q31_t)0x39bffcd7, + (q31_t)0x5ba125bd, (q31_t)0x39ba9125, (q31_t)0x5bac7af9, (q31_t)0x39b52339, + (q31_t)0x5bb7cf23, (q31_t)0x39afb313, (q31_t)0x5bc3223c, (q31_t)0x39aa40b4, + (q31_t)0x5bce7442, (q31_t)0x39a4cc1c, (q31_t)0x5bd9c537, (q31_t)0x399f554b, + (q31_t)0x5be51518, (q31_t)0x3999dc42, (q31_t)0x5bf063e6, (q31_t)0x399460ff, + (q31_t)0x5bfbb1a0, (q31_t)0x398ee385, (q31_t)0x5c06fe46, (q31_t)0x398963d2, + (q31_t)0x5c1249d8, (q31_t)0x3983e1e8, (q31_t)0x5c1d9454, (q31_t)0x397e5dc6, + (q31_t)0x5c28ddbb, (q31_t)0x3978d76c, (q31_t)0x5c34260c, (q31_t)0x39734edc, + (q31_t)0x5c3f6d47, (q31_t)0x396dc414, (q31_t)0x5c4ab36b, (q31_t)0x39683715, + (q31_t)0x5c55f878, (q31_t)0x3962a7e0, (q31_t)0x5c613c6d, (q31_t)0x395d1675, + (q31_t)0x5c6c7f4a, (q31_t)0x395782d3, (q31_t)0x5c77c10e, (q31_t)0x3951ecfc, + (q31_t)0x5c8301b9, (q31_t)0x394c54ee, (q31_t)0x5c8e414b, (q31_t)0x3946baac, + (q31_t)0x5c997fc4, (q31_t)0x39411e33, (q31_t)0x5ca4bd21, (q31_t)0x393b7f86, + (q31_t)0x5caff965, (q31_t)0x3935dea4, (q31_t)0x5cbb348d, (q31_t)0x39303b8e, + (q31_t)0x5cc66e99, (q31_t)0x392a9642, (q31_t)0x5cd1a78a, (q31_t)0x3924eec3, + (q31_t)0x5cdcdf5e, (q31_t)0x391f4510, (q31_t)0x5ce81615, (q31_t)0x39199929, + (q31_t)0x5cf34baf, (q31_t)0x3913eb0e, (q31_t)0x5cfe802b, (q31_t)0x390e3ac0, + (q31_t)0x5d09b389, (q31_t)0x3908883f, (q31_t)0x5d14e5c9, (q31_t)0x3902d38b, + (q31_t)0x5d2016e9, (q31_t)0x38fd1ca4, (q31_t)0x5d2b46ea, (q31_t)0x38f7638b, + (q31_t)0x5d3675cb, (q31_t)0x38f1a840, (q31_t)0x5d41a38c, (q31_t)0x38ebeac2, + (q31_t)0x5d4cd02c, (q31_t)0x38e62b13, (q31_t)0x5d57fbaa, (q31_t)0x38e06932, + (q31_t)0x5d632608, (q31_t)0x38daa520, (q31_t)0x5d6e4f43, (q31_t)0x38d4dedd, + (q31_t)0x5d79775c, (q31_t)0x38cf1669, (q31_t)0x5d849e51, (q31_t)0x38c94bc4, + (q31_t)0x5d8fc424, (q31_t)0x38c37eef, (q31_t)0x5d9ae8d2, (q31_t)0x38bdafea, + (q31_t)0x5da60c5d, (q31_t)0x38b7deb4, (q31_t)0x5db12ec3, (q31_t)0x38b20b4f, + (q31_t)0x5dbc5004, (q31_t)0x38ac35ba, (q31_t)0x5dc7701f, (q31_t)0x38a65df6, + (q31_t)0x5dd28f15, (q31_t)0x38a08402, (q31_t)0x5dddace4, (q31_t)0x389aa7e0, + (q31_t)0x5de8c98c, (q31_t)0x3894c98f, (q31_t)0x5df3e50d, (q31_t)0x388ee910, + (q31_t)0x5dfeff67, (q31_t)0x38890663, (q31_t)0x5e0a1898, (q31_t)0x38832187, + (q31_t)0x5e1530a1, (q31_t)0x387d3a7e, (q31_t)0x5e204781, (q31_t)0x38775147, + (q31_t)0x5e2b5d38, (q31_t)0x387165e3, (q31_t)0x5e3671c5, (q31_t)0x386b7852, + (q31_t)0x5e418528, (q31_t)0x38658894, (q31_t)0x5e4c9760, (q31_t)0x385f96a9, + (q31_t)0x5e57a86d, (q31_t)0x3859a292, (q31_t)0x5e62b84f, (q31_t)0x3853ac4f, + (q31_t)0x5e6dc705, (q31_t)0x384db3e0, (q31_t)0x5e78d48e, (q31_t)0x3847b946, + (q31_t)0x5e83e0eb, (q31_t)0x3841bc7f, (q31_t)0x5e8eec1b, (q31_t)0x383bbd8e, + (q31_t)0x5e99f61d, (q31_t)0x3835bc71, (q31_t)0x5ea4fef0, (q31_t)0x382fb92a, + (q31_t)0x5eb00696, (q31_t)0x3829b3b9, (q31_t)0x5ebb0d0d, (q31_t)0x3823ac1d, + (q31_t)0x5ec61254, (q31_t)0x381da256, (q31_t)0x5ed1166b, (q31_t)0x38179666, + (q31_t)0x5edc1953, (q31_t)0x3811884d, (q31_t)0x5ee71b0a, (q31_t)0x380b780a, + (q31_t)0x5ef21b90, (q31_t)0x3805659e, (q31_t)0x5efd1ae4, (q31_t)0x37ff5109, + (q31_t)0x5f081907, (q31_t)0x37f93a4b, (q31_t)0x5f1315f7, (q31_t)0x37f32165, + (q31_t)0x5f1e11b5, (q31_t)0x37ed0657, (q31_t)0x5f290c3f, (q31_t)0x37e6e921, + (q31_t)0x5f340596, (q31_t)0x37e0c9c3, (q31_t)0x5f3efdb9, (q31_t)0x37daa83d, + (q31_t)0x5f49f4a8, (q31_t)0x37d48490, (q31_t)0x5f54ea62, (q31_t)0x37ce5ebd, + (q31_t)0x5f5fdee6, (q31_t)0x37c836c2, (q31_t)0x5f6ad235, (q31_t)0x37c20ca1, + (q31_t)0x5f75c44e, (q31_t)0x37bbe05a, (q31_t)0x5f80b531, (q31_t)0x37b5b1ec, + (q31_t)0x5f8ba4dc, (q31_t)0x37af8159, (q31_t)0x5f969350, (q31_t)0x37a94ea0, + (q31_t)0x5fa1808c, (q31_t)0x37a319c2, (q31_t)0x5fac6c91, (q31_t)0x379ce2be, + (q31_t)0x5fb7575c, (q31_t)0x3796a996, (q31_t)0x5fc240ef, (q31_t)0x37906e49, + (q31_t)0x5fcd2948, (q31_t)0x378a30d8, (q31_t)0x5fd81067, (q31_t)0x3783f143, + (q31_t)0x5fe2f64c, (q31_t)0x377daf89, (q31_t)0x5feddaf6, (q31_t)0x37776bac, + (q31_t)0x5ff8be65, (q31_t)0x377125ac, (q31_t)0x6003a099, (q31_t)0x376add88, + (q31_t)0x600e8190, (q31_t)0x37649341, (q31_t)0x6019614c, (q31_t)0x375e46d8, + (q31_t)0x60243fca, (q31_t)0x3757f84c, (q31_t)0x602f1d0b, (q31_t)0x3751a79e, + (q31_t)0x6039f90f, (q31_t)0x374b54ce, (q31_t)0x6044d3d4, (q31_t)0x3744ffdd, + (q31_t)0x604fad5b, (q31_t)0x373ea8ca, (q31_t)0x605a85a3, (q31_t)0x37384f95, + (q31_t)0x60655cac, (q31_t)0x3731f440, (q31_t)0x60703275, (q31_t)0x372b96ca, + (q31_t)0x607b06fe, (q31_t)0x37253733, (q31_t)0x6085da46, (q31_t)0x371ed57c, + (q31_t)0x6090ac4d, (q31_t)0x371871a5, (q31_t)0x609b7d13, (q31_t)0x37120bae, + (q31_t)0x60a64c97, (q31_t)0x370ba398, (q31_t)0x60b11ad9, (q31_t)0x37053962, + (q31_t)0x60bbe7d8, (q31_t)0x36fecd0e, (q31_t)0x60c6b395, (q31_t)0x36f85e9a, + (q31_t)0x60d17e0d, (q31_t)0x36f1ee09, (q31_t)0x60dc4742, (q31_t)0x36eb7b58, + (q31_t)0x60e70f32, (q31_t)0x36e5068a, (q31_t)0x60f1d5de, (q31_t)0x36de8f9e, + (q31_t)0x60fc9b44, (q31_t)0x36d81695, (q31_t)0x61075f65, (q31_t)0x36d19b6e, + (q31_t)0x61122240, (q31_t)0x36cb1e2a, (q31_t)0x611ce3d5, (q31_t)0x36c49ec9, + (q31_t)0x6127a423, (q31_t)0x36be1d4c, (q31_t)0x61326329, (q31_t)0x36b799b3, + (q31_t)0x613d20e8, (q31_t)0x36b113fd, (q31_t)0x6147dd5f, (q31_t)0x36aa8c2c, + (q31_t)0x6152988d, (q31_t)0x36a4023f, (q31_t)0x615d5273, (q31_t)0x369d7637, + (q31_t)0x61680b0f, (q31_t)0x3696e814, (q31_t)0x6172c262, (q31_t)0x369057d6, + (q31_t)0x617d786a, (q31_t)0x3689c57d, (q31_t)0x61882d28, (q31_t)0x3683310b, + (q31_t)0x6192e09b, (q31_t)0x367c9a7e, (q31_t)0x619d92c2, (q31_t)0x367601d7, + (q31_t)0x61a8439e, (q31_t)0x366f6717, (q31_t)0x61b2f32e, (q31_t)0x3668ca3e, + (q31_t)0x61bda171, (q31_t)0x36622b4c, (q31_t)0x61c84e67, (q31_t)0x365b8a41, + (q31_t)0x61d2fa0f, (q31_t)0x3654e71d, (q31_t)0x61dda46a, (q31_t)0x364e41e2, + (q31_t)0x61e84d76, (q31_t)0x36479a8e, (q31_t)0x61f2f534, (q31_t)0x3640f123, + (q31_t)0x61fd9ba3, (q31_t)0x363a45a0, (q31_t)0x620840c2, (q31_t)0x36339806, + (q31_t)0x6212e492, (q31_t)0x362ce855, (q31_t)0x621d8711, (q31_t)0x3626368d, + (q31_t)0x6228283f, (q31_t)0x361f82af, (q31_t)0x6232c81c, (q31_t)0x3618ccba, + (q31_t)0x623d66a8, (q31_t)0x361214b0, (q31_t)0x624803e2, (q31_t)0x360b5a90, + (q31_t)0x62529fca, (q31_t)0x36049e5b, (q31_t)0x625d3a5e, (q31_t)0x35fde011, + (q31_t)0x6267d3a0, (q31_t)0x35f71fb1, (q31_t)0x62726b8e, (q31_t)0x35f05d3d, + (q31_t)0x627d0228, (q31_t)0x35e998b5, (q31_t)0x6287976e, (q31_t)0x35e2d219, + (q31_t)0x62922b5e, (q31_t)0x35dc0968, (q31_t)0x629cbdfa, (q31_t)0x35d53ea5, + (q31_t)0x62a74f40, (q31_t)0x35ce71ce, (q31_t)0x62b1df30, (q31_t)0x35c7a2e3, + (q31_t)0x62bc6dca, (q31_t)0x35c0d1e7, (q31_t)0x62c6fb0c, (q31_t)0x35b9fed7, + (q31_t)0x62d186f8, (q31_t)0x35b329b5, (q31_t)0x62dc118c, (q31_t)0x35ac5282, + (q31_t)0x62e69ac8, (q31_t)0x35a5793c, (q31_t)0x62f122ab, (q31_t)0x359e9de5, + (q31_t)0x62fba936, (q31_t)0x3597c07d, (q31_t)0x63062e67, (q31_t)0x3590e104, + (q31_t)0x6310b23e, (q31_t)0x3589ff7a, (q31_t)0x631b34bc, (q31_t)0x35831be0, + (q31_t)0x6325b5df, (q31_t)0x357c3636, (q31_t)0x633035a7, (q31_t)0x35754e7c, + (q31_t)0x633ab414, (q31_t)0x356e64b2, (q31_t)0x63453125, (q31_t)0x356778d9, + (q31_t)0x634facda, (q31_t)0x35608af1, (q31_t)0x635a2733, (q31_t)0x35599afa, + (q31_t)0x6364a02e, (q31_t)0x3552a8f4, (q31_t)0x636f17cc, (q31_t)0x354bb4e1, + (q31_t)0x63798e0d, (q31_t)0x3544bebf, (q31_t)0x638402ef, (q31_t)0x353dc68f, + (q31_t)0x638e7673, (q31_t)0x3536cc52, (q31_t)0x6398e898, (q31_t)0x352fd008, + (q31_t)0x63a3595e, (q31_t)0x3528d1b1, (q31_t)0x63adc8c4, (q31_t)0x3521d14d, + (q31_t)0x63b836ca, (q31_t)0x351acedd, (q31_t)0x63c2a36f, (q31_t)0x3513ca60, + (q31_t)0x63cd0eb3, (q31_t)0x350cc3d8, (q31_t)0x63d77896, (q31_t)0x3505bb44, + (q31_t)0x63e1e117, (q31_t)0x34feb0a5, (q31_t)0x63ec4837, (q31_t)0x34f7a3fb, + (q31_t)0x63f6adf3, (q31_t)0x34f09546, (q31_t)0x6401124d, (q31_t)0x34e98487, + (q31_t)0x640b7543, (q31_t)0x34e271bd, (q31_t)0x6415d6d5, (q31_t)0x34db5cea, + (q31_t)0x64203704, (q31_t)0x34d4460c, (q31_t)0x642a95ce, (q31_t)0x34cd2d26, + (q31_t)0x6434f332, (q31_t)0x34c61236, (q31_t)0x643f4f32, (q31_t)0x34bef53d, + (q31_t)0x6449a9cc, (q31_t)0x34b7d63c, (q31_t)0x645402ff, (q31_t)0x34b0b533, + (q31_t)0x645e5acc, (q31_t)0x34a99221, (q31_t)0x6468b132, (q31_t)0x34a26d08, + (q31_t)0x64730631, (q31_t)0x349b45e7, (q31_t)0x647d59c8, (q31_t)0x34941cbf, + (q31_t)0x6487abf7, (q31_t)0x348cf190, (q31_t)0x6491fcbe, (q31_t)0x3485c45b, + (q31_t)0x649c4c1b, (q31_t)0x347e951f, (q31_t)0x64a69a0f, (q31_t)0x347763dd, + (q31_t)0x64b0e699, (q31_t)0x34703095, (q31_t)0x64bb31ba, (q31_t)0x3468fb47, + (q31_t)0x64c57b6f, (q31_t)0x3461c3f5, (q31_t)0x64cfc3ba, (q31_t)0x345a8a9d, + (q31_t)0x64da0a9a, (q31_t)0x34534f41, (q31_t)0x64e4500e, (q31_t)0x344c11e0, + (q31_t)0x64ee9415, (q31_t)0x3444d27b, (q31_t)0x64f8d6b0, (q31_t)0x343d9112, + (q31_t)0x650317df, (q31_t)0x34364da6, (q31_t)0x650d57a0, (q31_t)0x342f0836, + (q31_t)0x651795f3, (q31_t)0x3427c0c3, (q31_t)0x6521d2d8, (q31_t)0x3420774d, + (q31_t)0x652c0e4f, (q31_t)0x34192bd5, (q31_t)0x65364857, (q31_t)0x3411de5b, + (q31_t)0x654080ef, (q31_t)0x340a8edf, (q31_t)0x654ab818, (q31_t)0x34033d61, + (q31_t)0x6554edd1, (q31_t)0x33fbe9e2, (q31_t)0x655f2219, (q31_t)0x33f49462, + (q31_t)0x656954f1, (q31_t)0x33ed3ce1, (q31_t)0x65738657, (q31_t)0x33e5e360, + (q31_t)0x657db64c, (q31_t)0x33de87de, (q31_t)0x6587e4cf, (q31_t)0x33d72a5d, + (q31_t)0x659211df, (q31_t)0x33cfcadc, (q31_t)0x659c3d7c, (q31_t)0x33c8695b, + (q31_t)0x65a667a7, (q31_t)0x33c105db, (q31_t)0x65b0905d, (q31_t)0x33b9a05d, + (q31_t)0x65bab7a0, (q31_t)0x33b238e0, (q31_t)0x65c4dd6e, (q31_t)0x33aacf65, + (q31_t)0x65cf01c8, (q31_t)0x33a363ec, (q31_t)0x65d924ac, (q31_t)0x339bf675, + (q31_t)0x65e3461b, (q31_t)0x33948701, (q31_t)0x65ed6614, (q31_t)0x338d1590, + (q31_t)0x65f78497, (q31_t)0x3385a222, (q31_t)0x6601a1a2, (q31_t)0x337e2cb7, + (q31_t)0x660bbd37, (q31_t)0x3376b551, (q31_t)0x6615d754, (q31_t)0x336f3bee, + (q31_t)0x661feffa, (q31_t)0x3367c090, (q31_t)0x662a0727, (q31_t)0x33604336, + (q31_t)0x66341cdb, (q31_t)0x3358c3e2, (q31_t)0x663e3117, (q31_t)0x33514292, + (q31_t)0x664843d9, (q31_t)0x3349bf48, (q31_t)0x66525521, (q31_t)0x33423a04, + (q31_t)0x665c64ef, (q31_t)0x333ab2c6, (q31_t)0x66667342, (q31_t)0x3333298f, + (q31_t)0x6670801a, (q31_t)0x332b9e5e, (q31_t)0x667a8b77, (q31_t)0x33241134, + (q31_t)0x66849558, (q31_t)0x331c8211, (q31_t)0x668e9dbd, (q31_t)0x3314f0f6, + (q31_t)0x6698a4a6, (q31_t)0x330d5de3, (q31_t)0x66a2aa11, (q31_t)0x3305c8d7, + (q31_t)0x66acadff, (q31_t)0x32fe31d5, (q31_t)0x66b6b070, (q31_t)0x32f698db, + (q31_t)0x66c0b162, (q31_t)0x32eefdea, (q31_t)0x66cab0d6, (q31_t)0x32e76102, + (q31_t)0x66d4aecb, (q31_t)0x32dfc224, (q31_t)0x66deab41, (q31_t)0x32d82150, + (q31_t)0x66e8a637, (q31_t)0x32d07e85, (q31_t)0x66f29fad, (q31_t)0x32c8d9c6, + (q31_t)0x66fc97a3, (q31_t)0x32c13311, (q31_t)0x67068e18, (q31_t)0x32b98a67, + (q31_t)0x6710830c, (q31_t)0x32b1dfc9, (q31_t)0x671a767e, (q31_t)0x32aa3336, + (q31_t)0x6724686e, (q31_t)0x32a284b0, (q31_t)0x672e58dc, (q31_t)0x329ad435, + (q31_t)0x673847c8, (q31_t)0x329321c7, (q31_t)0x67423530, (q31_t)0x328b6d66, + (q31_t)0x674c2115, (q31_t)0x3283b712, (q31_t)0x67560b76, (q31_t)0x327bfecc, + (q31_t)0x675ff452, (q31_t)0x32744493, (q31_t)0x6769dbaa, (q31_t)0x326c8868, + (q31_t)0x6773c17d, (q31_t)0x3264ca4c, (q31_t)0x677da5cb, (q31_t)0x325d0a3e, + (q31_t)0x67878893, (q31_t)0x32554840, (q31_t)0x679169d5, (q31_t)0x324d8450, + (q31_t)0x679b4990, (q31_t)0x3245be70, (q31_t)0x67a527c4, (q31_t)0x323df6a0, + (q31_t)0x67af0472, (q31_t)0x32362ce0, (q31_t)0x67b8df97, (q31_t)0x322e6130, + (q31_t)0x67c2b934, (q31_t)0x32269391, (q31_t)0x67cc9149, (q31_t)0x321ec403, + (q31_t)0x67d667d5, (q31_t)0x3216f287, (q31_t)0x67e03cd8, (q31_t)0x320f1f1c, + (q31_t)0x67ea1052, (q31_t)0x320749c3, (q31_t)0x67f3e241, (q31_t)0x31ff727c, + (q31_t)0x67fdb2a7, (q31_t)0x31f79948, (q31_t)0x68078181, (q31_t)0x31efbe27, + (q31_t)0x68114ed0, (q31_t)0x31e7e118, (q31_t)0x681b1a94, (q31_t)0x31e0021e, + (q31_t)0x6824e4cc, (q31_t)0x31d82137, (q31_t)0x682ead78, (q31_t)0x31d03e64, + (q31_t)0x68387498, (q31_t)0x31c859a5, (q31_t)0x68423a2a, (q31_t)0x31c072fb, + (q31_t)0x684bfe2f, (q31_t)0x31b88a66, (q31_t)0x6855c0a6, (q31_t)0x31b09fe7, + (q31_t)0x685f8190, (q31_t)0x31a8b37c, (q31_t)0x686940ea, (q31_t)0x31a0c528, + (q31_t)0x6872feb6, (q31_t)0x3198d4ea, (q31_t)0x687cbaf3, (q31_t)0x3190e2c3, + (q31_t)0x688675a0, (q31_t)0x3188eeb2, (q31_t)0x68902ebd, (q31_t)0x3180f8b8, + (q31_t)0x6899e64a, (q31_t)0x317900d6, (q31_t)0x68a39c46, (q31_t)0x3171070c, + (q31_t)0x68ad50b1, (q31_t)0x31690b59, (q31_t)0x68b7038b, (q31_t)0x31610dbf, + (q31_t)0x68c0b4d2, (q31_t)0x31590e3e, (q31_t)0x68ca6488, (q31_t)0x31510cd5, + (q31_t)0x68d412ab, (q31_t)0x31490986, (q31_t)0x68ddbf3b, (q31_t)0x31410450, + (q31_t)0x68e76a37, (q31_t)0x3138fd35, (q31_t)0x68f113a0, (q31_t)0x3130f433, + (q31_t)0x68fabb75, (q31_t)0x3128e94c, (q31_t)0x690461b5, (q31_t)0x3120dc80, + (q31_t)0x690e0661, (q31_t)0x3118cdcf, (q31_t)0x6917a977, (q31_t)0x3110bd39, + (q31_t)0x69214af8, (q31_t)0x3108aabf, (q31_t)0x692aeae3, (q31_t)0x31009661, + (q31_t)0x69348937, (q31_t)0x30f8801f, (q31_t)0x693e25f5, (q31_t)0x30f067fb, + (q31_t)0x6947c11c, (q31_t)0x30e84df3, (q31_t)0x69515aab, (q31_t)0x30e03208, + (q31_t)0x695af2a3, (q31_t)0x30d8143b, (q31_t)0x69648902, (q31_t)0x30cff48c, + (q31_t)0x696e1dc9, (q31_t)0x30c7d2fb, (q31_t)0x6977b0f7, (q31_t)0x30bfaf89, + (q31_t)0x6981428c, (q31_t)0x30b78a36, (q31_t)0x698ad287, (q31_t)0x30af6302, + (q31_t)0x699460e8, (q31_t)0x30a739ed, (q31_t)0x699dedaf, (q31_t)0x309f0ef8, + (q31_t)0x69a778db, (q31_t)0x3096e223, (q31_t)0x69b1026c, (q31_t)0x308eb36f, + (q31_t)0x69ba8a61, (q31_t)0x308682dc, (q31_t)0x69c410ba, (q31_t)0x307e5069, + (q31_t)0x69cd9578, (q31_t)0x30761c18, (q31_t)0x69d71899, (q31_t)0x306de5e9, + (q31_t)0x69e09a1c, (q31_t)0x3065addb, (q31_t)0x69ea1a03, (q31_t)0x305d73f0, + (q31_t)0x69f3984c, (q31_t)0x30553828, (q31_t)0x69fd14f6, (q31_t)0x304cfa83, + (q31_t)0x6a069003, (q31_t)0x3044bb00, (q31_t)0x6a100970, (q31_t)0x303c79a2, + (q31_t)0x6a19813f, (q31_t)0x30343667, (q31_t)0x6a22f76e, (q31_t)0x302bf151, + (q31_t)0x6a2c6bfd, (q31_t)0x3023aa5f, (q31_t)0x6a35deeb, (q31_t)0x301b6193, + (q31_t)0x6a3f503a, (q31_t)0x301316eb, (q31_t)0x6a48bfe7, (q31_t)0x300aca69, + (q31_t)0x6a522df3, (q31_t)0x30027c0c, (q31_t)0x6a5b9a5d, (q31_t)0x2ffa2bd6, + (q31_t)0x6a650525, (q31_t)0x2ff1d9c7, (q31_t)0x6a6e6e4b, (q31_t)0x2fe985de, + (q31_t)0x6a77d5ce, (q31_t)0x2fe1301c, (q31_t)0x6a813bae, (q31_t)0x2fd8d882, + (q31_t)0x6a8a9fea, (q31_t)0x2fd07f0f, (q31_t)0x6a940283, (q31_t)0x2fc823c5, + (q31_t)0x6a9d6377, (q31_t)0x2fbfc6a3, (q31_t)0x6aa6c2c6, (q31_t)0x2fb767aa, + (q31_t)0x6ab02071, (q31_t)0x2faf06da, (q31_t)0x6ab97c77, (q31_t)0x2fa6a433, + (q31_t)0x6ac2d6d6, (q31_t)0x2f9e3fb6, (q31_t)0x6acc2f90, (q31_t)0x2f95d963, + (q31_t)0x6ad586a3, (q31_t)0x2f8d713a, (q31_t)0x6adedc10, (q31_t)0x2f85073c, + (q31_t)0x6ae82fd5, (q31_t)0x2f7c9b69, (q31_t)0x6af181f3, (q31_t)0x2f742dc1, + (q31_t)0x6afad269, (q31_t)0x2f6bbe45, (q31_t)0x6b042137, (q31_t)0x2f634cf5, + (q31_t)0x6b0d6e5c, (q31_t)0x2f5ad9d1, (q31_t)0x6b16b9d9, (q31_t)0x2f5264da, + (q31_t)0x6b2003ac, (q31_t)0x2f49ee0f, (q31_t)0x6b294bd5, (q31_t)0x2f417573, + (q31_t)0x6b329255, (q31_t)0x2f38fb03, (q31_t)0x6b3bd72a, (q31_t)0x2f307ec2, + (q31_t)0x6b451a55, (q31_t)0x2f2800af, (q31_t)0x6b4e5bd4, (q31_t)0x2f1f80ca, + (q31_t)0x6b579ba8, (q31_t)0x2f16ff14, (q31_t)0x6b60d9d0, (q31_t)0x2f0e7b8e, + (q31_t)0x6b6a164d, (q31_t)0x2f05f637, (q31_t)0x6b73511c, (q31_t)0x2efd6f10, + (q31_t)0x6b7c8a3f, (q31_t)0x2ef4e619, (q31_t)0x6b85c1b5, (q31_t)0x2eec5b53, + (q31_t)0x6b8ef77d, (q31_t)0x2ee3cebe, (q31_t)0x6b982b97, (q31_t)0x2edb405a, + (q31_t)0x6ba15e03, (q31_t)0x2ed2b027, (q31_t)0x6baa8ec0, (q31_t)0x2eca1e27, + (q31_t)0x6bb3bdce, (q31_t)0x2ec18a58, (q31_t)0x6bbceb2d, (q31_t)0x2eb8f4bc, + (q31_t)0x6bc616dd, (q31_t)0x2eb05d53, (q31_t)0x6bcf40dc, (q31_t)0x2ea7c41e, + (q31_t)0x6bd8692b, (q31_t)0x2e9f291b, (q31_t)0x6be18fc9, (q31_t)0x2e968c4d, + (q31_t)0x6beab4b6, (q31_t)0x2e8dedb3, (q31_t)0x6bf3d7f2, (q31_t)0x2e854d4d, + (q31_t)0x6bfcf97c, (q31_t)0x2e7cab1c, (q31_t)0x6c061953, (q31_t)0x2e740720, + (q31_t)0x6c0f3779, (q31_t)0x2e6b615a, (q31_t)0x6c1853eb, (q31_t)0x2e62b9ca, + (q31_t)0x6c216eaa, (q31_t)0x2e5a1070, (q31_t)0x6c2a87b6, (q31_t)0x2e51654c, + (q31_t)0x6c339f0e, (q31_t)0x2e48b860, (q31_t)0x6c3cb4b1, (q31_t)0x2e4009aa, + (q31_t)0x6c45c8a0, (q31_t)0x2e37592c, (q31_t)0x6c4edada, (q31_t)0x2e2ea6e6, + (q31_t)0x6c57eb5e, (q31_t)0x2e25f2d8, (q31_t)0x6c60fa2d, (q31_t)0x2e1d3d03, + (q31_t)0x6c6a0746, (q31_t)0x2e148566, (q31_t)0x6c7312a9, (q31_t)0x2e0bcc03, + (q31_t)0x6c7c1c55, (q31_t)0x2e0310d9, (q31_t)0x6c85244a, (q31_t)0x2dfa53e9, + (q31_t)0x6c8e2a87, (q31_t)0x2df19534, (q31_t)0x6c972f0d, (q31_t)0x2de8d4b8, + (q31_t)0x6ca031da, (q31_t)0x2de01278, (q31_t)0x6ca932ef, (q31_t)0x2dd74e73, + (q31_t)0x6cb2324c, (q31_t)0x2dce88aa, (q31_t)0x6cbb2fef, (q31_t)0x2dc5c11c, + (q31_t)0x6cc42bd9, (q31_t)0x2dbcf7cb, (q31_t)0x6ccd2609, (q31_t)0x2db42cb6, + (q31_t)0x6cd61e7f, (q31_t)0x2dab5fdf, (q31_t)0x6cdf153a, (q31_t)0x2da29144, + (q31_t)0x6ce80a3a, (q31_t)0x2d99c0e7, (q31_t)0x6cf0fd80, (q31_t)0x2d90eec8, + (q31_t)0x6cf9ef09, (q31_t)0x2d881ae8, (q31_t)0x6d02ded7, (q31_t)0x2d7f4545, + (q31_t)0x6d0bcce8, (q31_t)0x2d766de2, (q31_t)0x6d14b93d, (q31_t)0x2d6d94bf, + (q31_t)0x6d1da3d5, (q31_t)0x2d64b9da, (q31_t)0x6d268cb0, (q31_t)0x2d5bdd36, + (q31_t)0x6d2f73cd, (q31_t)0x2d52fed2, (q31_t)0x6d38592c, (q31_t)0x2d4a1eaf, + (q31_t)0x6d413ccd, (q31_t)0x2d413ccd, (q31_t)0x6d4a1eaf, (q31_t)0x2d38592c, + (q31_t)0x6d52fed2, (q31_t)0x2d2f73cd, (q31_t)0x6d5bdd36, (q31_t)0x2d268cb0, + (q31_t)0x6d64b9da, (q31_t)0x2d1da3d5, (q31_t)0x6d6d94bf, (q31_t)0x2d14b93d, + (q31_t)0x6d766de2, (q31_t)0x2d0bcce8, (q31_t)0x6d7f4545, (q31_t)0x2d02ded7, + (q31_t)0x6d881ae8, (q31_t)0x2cf9ef09, (q31_t)0x6d90eec8, (q31_t)0x2cf0fd80, + (q31_t)0x6d99c0e7, (q31_t)0x2ce80a3a, (q31_t)0x6da29144, (q31_t)0x2cdf153a, + (q31_t)0x6dab5fdf, (q31_t)0x2cd61e7f, (q31_t)0x6db42cb6, (q31_t)0x2ccd2609, + (q31_t)0x6dbcf7cb, (q31_t)0x2cc42bd9, (q31_t)0x6dc5c11c, (q31_t)0x2cbb2fef, + (q31_t)0x6dce88aa, (q31_t)0x2cb2324c, (q31_t)0x6dd74e73, (q31_t)0x2ca932ef, + (q31_t)0x6de01278, (q31_t)0x2ca031da, (q31_t)0x6de8d4b8, (q31_t)0x2c972f0d, + (q31_t)0x6df19534, (q31_t)0x2c8e2a87, (q31_t)0x6dfa53e9, (q31_t)0x2c85244a, + (q31_t)0x6e0310d9, (q31_t)0x2c7c1c55, (q31_t)0x6e0bcc03, (q31_t)0x2c7312a9, + (q31_t)0x6e148566, (q31_t)0x2c6a0746, (q31_t)0x6e1d3d03, (q31_t)0x2c60fa2d, + (q31_t)0x6e25f2d8, (q31_t)0x2c57eb5e, (q31_t)0x6e2ea6e6, (q31_t)0x2c4edada, + (q31_t)0x6e37592c, (q31_t)0x2c45c8a0, (q31_t)0x6e4009aa, (q31_t)0x2c3cb4b1, + (q31_t)0x6e48b860, (q31_t)0x2c339f0e, (q31_t)0x6e51654c, (q31_t)0x2c2a87b6, + (q31_t)0x6e5a1070, (q31_t)0x2c216eaa, (q31_t)0x6e62b9ca, (q31_t)0x2c1853eb, + (q31_t)0x6e6b615a, (q31_t)0x2c0f3779, (q31_t)0x6e740720, (q31_t)0x2c061953, + (q31_t)0x6e7cab1c, (q31_t)0x2bfcf97c, (q31_t)0x6e854d4d, (q31_t)0x2bf3d7f2, + (q31_t)0x6e8dedb3, (q31_t)0x2beab4b6, (q31_t)0x6e968c4d, (q31_t)0x2be18fc9, + (q31_t)0x6e9f291b, (q31_t)0x2bd8692b, (q31_t)0x6ea7c41e, (q31_t)0x2bcf40dc, + (q31_t)0x6eb05d53, (q31_t)0x2bc616dd, (q31_t)0x6eb8f4bc, (q31_t)0x2bbceb2d, + (q31_t)0x6ec18a58, (q31_t)0x2bb3bdce, (q31_t)0x6eca1e27, (q31_t)0x2baa8ec0, + (q31_t)0x6ed2b027, (q31_t)0x2ba15e03, (q31_t)0x6edb405a, (q31_t)0x2b982b97, + (q31_t)0x6ee3cebe, (q31_t)0x2b8ef77d, (q31_t)0x6eec5b53, (q31_t)0x2b85c1b5, + (q31_t)0x6ef4e619, (q31_t)0x2b7c8a3f, (q31_t)0x6efd6f10, (q31_t)0x2b73511c, + (q31_t)0x6f05f637, (q31_t)0x2b6a164d, (q31_t)0x6f0e7b8e, (q31_t)0x2b60d9d0, + (q31_t)0x6f16ff14, (q31_t)0x2b579ba8, (q31_t)0x6f1f80ca, (q31_t)0x2b4e5bd4, + (q31_t)0x6f2800af, (q31_t)0x2b451a55, (q31_t)0x6f307ec2, (q31_t)0x2b3bd72a, + (q31_t)0x6f38fb03, (q31_t)0x2b329255, (q31_t)0x6f417573, (q31_t)0x2b294bd5, + (q31_t)0x6f49ee0f, (q31_t)0x2b2003ac, (q31_t)0x6f5264da, (q31_t)0x2b16b9d9, + (q31_t)0x6f5ad9d1, (q31_t)0x2b0d6e5c, (q31_t)0x6f634cf5, (q31_t)0x2b042137, + (q31_t)0x6f6bbe45, (q31_t)0x2afad269, (q31_t)0x6f742dc1, (q31_t)0x2af181f3, + (q31_t)0x6f7c9b69, (q31_t)0x2ae82fd5, (q31_t)0x6f85073c, (q31_t)0x2adedc10, + (q31_t)0x6f8d713a, (q31_t)0x2ad586a3, (q31_t)0x6f95d963, (q31_t)0x2acc2f90, + (q31_t)0x6f9e3fb6, (q31_t)0x2ac2d6d6, (q31_t)0x6fa6a433, (q31_t)0x2ab97c77, + (q31_t)0x6faf06da, (q31_t)0x2ab02071, (q31_t)0x6fb767aa, (q31_t)0x2aa6c2c6, + (q31_t)0x6fbfc6a3, (q31_t)0x2a9d6377, (q31_t)0x6fc823c5, (q31_t)0x2a940283, + (q31_t)0x6fd07f0f, (q31_t)0x2a8a9fea, (q31_t)0x6fd8d882, (q31_t)0x2a813bae, + (q31_t)0x6fe1301c, (q31_t)0x2a77d5ce, (q31_t)0x6fe985de, (q31_t)0x2a6e6e4b, + (q31_t)0x6ff1d9c7, (q31_t)0x2a650525, (q31_t)0x6ffa2bd6, (q31_t)0x2a5b9a5d, + (q31_t)0x70027c0c, (q31_t)0x2a522df3, (q31_t)0x700aca69, (q31_t)0x2a48bfe7, + (q31_t)0x701316eb, (q31_t)0x2a3f503a, (q31_t)0x701b6193, (q31_t)0x2a35deeb, + (q31_t)0x7023aa5f, (q31_t)0x2a2c6bfd, (q31_t)0x702bf151, (q31_t)0x2a22f76e, + (q31_t)0x70343667, (q31_t)0x2a19813f, (q31_t)0x703c79a2, (q31_t)0x2a100970, + (q31_t)0x7044bb00, (q31_t)0x2a069003, (q31_t)0x704cfa83, (q31_t)0x29fd14f6, + (q31_t)0x70553828, (q31_t)0x29f3984c, (q31_t)0x705d73f0, (q31_t)0x29ea1a03, + (q31_t)0x7065addb, (q31_t)0x29e09a1c, (q31_t)0x706de5e9, (q31_t)0x29d71899, + (q31_t)0x70761c18, (q31_t)0x29cd9578, (q31_t)0x707e5069, (q31_t)0x29c410ba, + (q31_t)0x708682dc, (q31_t)0x29ba8a61, (q31_t)0x708eb36f, (q31_t)0x29b1026c, + (q31_t)0x7096e223, (q31_t)0x29a778db, (q31_t)0x709f0ef8, (q31_t)0x299dedaf, + (q31_t)0x70a739ed, (q31_t)0x299460e8, (q31_t)0x70af6302, (q31_t)0x298ad287, + (q31_t)0x70b78a36, (q31_t)0x2981428c, (q31_t)0x70bfaf89, (q31_t)0x2977b0f7, + (q31_t)0x70c7d2fb, (q31_t)0x296e1dc9, (q31_t)0x70cff48c, (q31_t)0x29648902, + (q31_t)0x70d8143b, (q31_t)0x295af2a3, (q31_t)0x70e03208, (q31_t)0x29515aab, + (q31_t)0x70e84df3, (q31_t)0x2947c11c, (q31_t)0x70f067fb, (q31_t)0x293e25f5, + (q31_t)0x70f8801f, (q31_t)0x29348937, (q31_t)0x71009661, (q31_t)0x292aeae3, + (q31_t)0x7108aabf, (q31_t)0x29214af8, (q31_t)0x7110bd39, (q31_t)0x2917a977, + (q31_t)0x7118cdcf, (q31_t)0x290e0661, (q31_t)0x7120dc80, (q31_t)0x290461b5, + (q31_t)0x7128e94c, (q31_t)0x28fabb75, (q31_t)0x7130f433, (q31_t)0x28f113a0, + (q31_t)0x7138fd35, (q31_t)0x28e76a37, (q31_t)0x71410450, (q31_t)0x28ddbf3b, + (q31_t)0x71490986, (q31_t)0x28d412ab, (q31_t)0x71510cd5, (q31_t)0x28ca6488, + (q31_t)0x71590e3e, (q31_t)0x28c0b4d2, (q31_t)0x71610dbf, (q31_t)0x28b7038b, + (q31_t)0x71690b59, (q31_t)0x28ad50b1, (q31_t)0x7171070c, (q31_t)0x28a39c46, + (q31_t)0x717900d6, (q31_t)0x2899e64a, (q31_t)0x7180f8b8, (q31_t)0x28902ebd, + (q31_t)0x7188eeb2, (q31_t)0x288675a0, (q31_t)0x7190e2c3, (q31_t)0x287cbaf3, + (q31_t)0x7198d4ea, (q31_t)0x2872feb6, (q31_t)0x71a0c528, (q31_t)0x286940ea, + (q31_t)0x71a8b37c, (q31_t)0x285f8190, (q31_t)0x71b09fe7, (q31_t)0x2855c0a6, + (q31_t)0x71b88a66, (q31_t)0x284bfe2f, (q31_t)0x71c072fb, (q31_t)0x28423a2a, + (q31_t)0x71c859a5, (q31_t)0x28387498, (q31_t)0x71d03e64, (q31_t)0x282ead78, + (q31_t)0x71d82137, (q31_t)0x2824e4cc, (q31_t)0x71e0021e, (q31_t)0x281b1a94, + (q31_t)0x71e7e118, (q31_t)0x28114ed0, (q31_t)0x71efbe27, (q31_t)0x28078181, + (q31_t)0x71f79948, (q31_t)0x27fdb2a7, (q31_t)0x71ff727c, (q31_t)0x27f3e241, + (q31_t)0x720749c3, (q31_t)0x27ea1052, (q31_t)0x720f1f1c, (q31_t)0x27e03cd8, + (q31_t)0x7216f287, (q31_t)0x27d667d5, (q31_t)0x721ec403, (q31_t)0x27cc9149, + (q31_t)0x72269391, (q31_t)0x27c2b934, (q31_t)0x722e6130, (q31_t)0x27b8df97, + (q31_t)0x72362ce0, (q31_t)0x27af0472, (q31_t)0x723df6a0, (q31_t)0x27a527c4, + (q31_t)0x7245be70, (q31_t)0x279b4990, (q31_t)0x724d8450, (q31_t)0x279169d5, + (q31_t)0x72554840, (q31_t)0x27878893, (q31_t)0x725d0a3e, (q31_t)0x277da5cb, + (q31_t)0x7264ca4c, (q31_t)0x2773c17d, (q31_t)0x726c8868, (q31_t)0x2769dbaa, + (q31_t)0x72744493, (q31_t)0x275ff452, (q31_t)0x727bfecc, (q31_t)0x27560b76, + (q31_t)0x7283b712, (q31_t)0x274c2115, (q31_t)0x728b6d66, (q31_t)0x27423530, + (q31_t)0x729321c7, (q31_t)0x273847c8, (q31_t)0x729ad435, (q31_t)0x272e58dc, + (q31_t)0x72a284b0, (q31_t)0x2724686e, (q31_t)0x72aa3336, (q31_t)0x271a767e, + (q31_t)0x72b1dfc9, (q31_t)0x2710830c, (q31_t)0x72b98a67, (q31_t)0x27068e18, + (q31_t)0x72c13311, (q31_t)0x26fc97a3, (q31_t)0x72c8d9c6, (q31_t)0x26f29fad, + (q31_t)0x72d07e85, (q31_t)0x26e8a637, (q31_t)0x72d82150, (q31_t)0x26deab41, + (q31_t)0x72dfc224, (q31_t)0x26d4aecb, (q31_t)0x72e76102, (q31_t)0x26cab0d6, + (q31_t)0x72eefdea, (q31_t)0x26c0b162, (q31_t)0x72f698db, (q31_t)0x26b6b070, + (q31_t)0x72fe31d5, (q31_t)0x26acadff, (q31_t)0x7305c8d7, (q31_t)0x26a2aa11, + (q31_t)0x730d5de3, (q31_t)0x2698a4a6, (q31_t)0x7314f0f6, (q31_t)0x268e9dbd, + (q31_t)0x731c8211, (q31_t)0x26849558, (q31_t)0x73241134, (q31_t)0x267a8b77, + (q31_t)0x732b9e5e, (q31_t)0x2670801a, (q31_t)0x7333298f, (q31_t)0x26667342, + (q31_t)0x733ab2c6, (q31_t)0x265c64ef, (q31_t)0x73423a04, (q31_t)0x26525521, + (q31_t)0x7349bf48, (q31_t)0x264843d9, (q31_t)0x73514292, (q31_t)0x263e3117, + (q31_t)0x7358c3e2, (q31_t)0x26341cdb, (q31_t)0x73604336, (q31_t)0x262a0727, + (q31_t)0x7367c090, (q31_t)0x261feffa, (q31_t)0x736f3bee, (q31_t)0x2615d754, + (q31_t)0x7376b551, (q31_t)0x260bbd37, (q31_t)0x737e2cb7, (q31_t)0x2601a1a2, + (q31_t)0x7385a222, (q31_t)0x25f78497, (q31_t)0x738d1590, (q31_t)0x25ed6614, + (q31_t)0x73948701, (q31_t)0x25e3461b, (q31_t)0x739bf675, (q31_t)0x25d924ac, + (q31_t)0x73a363ec, (q31_t)0x25cf01c8, (q31_t)0x73aacf65, (q31_t)0x25c4dd6e, + (q31_t)0x73b238e0, (q31_t)0x25bab7a0, (q31_t)0x73b9a05d, (q31_t)0x25b0905d, + (q31_t)0x73c105db, (q31_t)0x25a667a7, (q31_t)0x73c8695b, (q31_t)0x259c3d7c, + (q31_t)0x73cfcadc, (q31_t)0x259211df, (q31_t)0x73d72a5d, (q31_t)0x2587e4cf, + (q31_t)0x73de87de, (q31_t)0x257db64c, (q31_t)0x73e5e360, (q31_t)0x25738657, + (q31_t)0x73ed3ce1, (q31_t)0x256954f1, (q31_t)0x73f49462, (q31_t)0x255f2219, + (q31_t)0x73fbe9e2, (q31_t)0x2554edd1, (q31_t)0x74033d61, (q31_t)0x254ab818, + (q31_t)0x740a8edf, (q31_t)0x254080ef, (q31_t)0x7411de5b, (q31_t)0x25364857, + (q31_t)0x74192bd5, (q31_t)0x252c0e4f, (q31_t)0x7420774d, (q31_t)0x2521d2d8, + (q31_t)0x7427c0c3, (q31_t)0x251795f3, (q31_t)0x742f0836, (q31_t)0x250d57a0, + (q31_t)0x74364da6, (q31_t)0x250317df, (q31_t)0x743d9112, (q31_t)0x24f8d6b0, + (q31_t)0x7444d27b, (q31_t)0x24ee9415, (q31_t)0x744c11e0, (q31_t)0x24e4500e, + (q31_t)0x74534f41, (q31_t)0x24da0a9a, (q31_t)0x745a8a9d, (q31_t)0x24cfc3ba, + (q31_t)0x7461c3f5, (q31_t)0x24c57b6f, (q31_t)0x7468fb47, (q31_t)0x24bb31ba, + (q31_t)0x74703095, (q31_t)0x24b0e699, (q31_t)0x747763dd, (q31_t)0x24a69a0f, + (q31_t)0x747e951f, (q31_t)0x249c4c1b, (q31_t)0x7485c45b, (q31_t)0x2491fcbe, + (q31_t)0x748cf190, (q31_t)0x2487abf7, (q31_t)0x74941cbf, (q31_t)0x247d59c8, + (q31_t)0x749b45e7, (q31_t)0x24730631, (q31_t)0x74a26d08, (q31_t)0x2468b132, + (q31_t)0x74a99221, (q31_t)0x245e5acc, (q31_t)0x74b0b533, (q31_t)0x245402ff, + (q31_t)0x74b7d63c, (q31_t)0x2449a9cc, (q31_t)0x74bef53d, (q31_t)0x243f4f32, + (q31_t)0x74c61236, (q31_t)0x2434f332, (q31_t)0x74cd2d26, (q31_t)0x242a95ce, + (q31_t)0x74d4460c, (q31_t)0x24203704, (q31_t)0x74db5cea, (q31_t)0x2415d6d5, + (q31_t)0x74e271bd, (q31_t)0x240b7543, (q31_t)0x74e98487, (q31_t)0x2401124d, + (q31_t)0x74f09546, (q31_t)0x23f6adf3, (q31_t)0x74f7a3fb, (q31_t)0x23ec4837, + (q31_t)0x74feb0a5, (q31_t)0x23e1e117, (q31_t)0x7505bb44, (q31_t)0x23d77896, + (q31_t)0x750cc3d8, (q31_t)0x23cd0eb3, (q31_t)0x7513ca60, (q31_t)0x23c2a36f, + (q31_t)0x751acedd, (q31_t)0x23b836ca, (q31_t)0x7521d14d, (q31_t)0x23adc8c4, + (q31_t)0x7528d1b1, (q31_t)0x23a3595e, (q31_t)0x752fd008, (q31_t)0x2398e898, + (q31_t)0x7536cc52, (q31_t)0x238e7673, (q31_t)0x753dc68f, (q31_t)0x238402ef, + (q31_t)0x7544bebf, (q31_t)0x23798e0d, (q31_t)0x754bb4e1, (q31_t)0x236f17cc, + (q31_t)0x7552a8f4, (q31_t)0x2364a02e, (q31_t)0x75599afa, (q31_t)0x235a2733, + (q31_t)0x75608af1, (q31_t)0x234facda, (q31_t)0x756778d9, (q31_t)0x23453125, + (q31_t)0x756e64b2, (q31_t)0x233ab414, (q31_t)0x75754e7c, (q31_t)0x233035a7, + (q31_t)0x757c3636, (q31_t)0x2325b5df, (q31_t)0x75831be0, (q31_t)0x231b34bc, + (q31_t)0x7589ff7a, (q31_t)0x2310b23e, (q31_t)0x7590e104, (q31_t)0x23062e67, + (q31_t)0x7597c07d, (q31_t)0x22fba936, (q31_t)0x759e9de5, (q31_t)0x22f122ab, + (q31_t)0x75a5793c, (q31_t)0x22e69ac8, (q31_t)0x75ac5282, (q31_t)0x22dc118c, + (q31_t)0x75b329b5, (q31_t)0x22d186f8, (q31_t)0x75b9fed7, (q31_t)0x22c6fb0c, + (q31_t)0x75c0d1e7, (q31_t)0x22bc6dca, (q31_t)0x75c7a2e3, (q31_t)0x22b1df30, + (q31_t)0x75ce71ce, (q31_t)0x22a74f40, (q31_t)0x75d53ea5, (q31_t)0x229cbdfa, + (q31_t)0x75dc0968, (q31_t)0x22922b5e, (q31_t)0x75e2d219, (q31_t)0x2287976e, + (q31_t)0x75e998b5, (q31_t)0x227d0228, (q31_t)0x75f05d3d, (q31_t)0x22726b8e, + (q31_t)0x75f71fb1, (q31_t)0x2267d3a0, (q31_t)0x75fde011, (q31_t)0x225d3a5e, + (q31_t)0x76049e5b, (q31_t)0x22529fca, (q31_t)0x760b5a90, (q31_t)0x224803e2, + (q31_t)0x761214b0, (q31_t)0x223d66a8, (q31_t)0x7618ccba, (q31_t)0x2232c81c, + (q31_t)0x761f82af, (q31_t)0x2228283f, (q31_t)0x7626368d, (q31_t)0x221d8711, + (q31_t)0x762ce855, (q31_t)0x2212e492, (q31_t)0x76339806, (q31_t)0x220840c2, + (q31_t)0x763a45a0, (q31_t)0x21fd9ba3, (q31_t)0x7640f123, (q31_t)0x21f2f534, + (q31_t)0x76479a8e, (q31_t)0x21e84d76, (q31_t)0x764e41e2, (q31_t)0x21dda46a, + (q31_t)0x7654e71d, (q31_t)0x21d2fa0f, (q31_t)0x765b8a41, (q31_t)0x21c84e67, + (q31_t)0x76622b4c, (q31_t)0x21bda171, (q31_t)0x7668ca3e, (q31_t)0x21b2f32e, + (q31_t)0x766f6717, (q31_t)0x21a8439e, (q31_t)0x767601d7, (q31_t)0x219d92c2, + (q31_t)0x767c9a7e, (q31_t)0x2192e09b, (q31_t)0x7683310b, (q31_t)0x21882d28, + (q31_t)0x7689c57d, (q31_t)0x217d786a, (q31_t)0x769057d6, (q31_t)0x2172c262, + (q31_t)0x7696e814, (q31_t)0x21680b0f, (q31_t)0x769d7637, (q31_t)0x215d5273, + (q31_t)0x76a4023f, (q31_t)0x2152988d, (q31_t)0x76aa8c2c, (q31_t)0x2147dd5f, + (q31_t)0x76b113fd, (q31_t)0x213d20e8, (q31_t)0x76b799b3, (q31_t)0x21326329, + (q31_t)0x76be1d4c, (q31_t)0x2127a423, (q31_t)0x76c49ec9, (q31_t)0x211ce3d5, + (q31_t)0x76cb1e2a, (q31_t)0x21122240, (q31_t)0x76d19b6e, (q31_t)0x21075f65, + (q31_t)0x76d81695, (q31_t)0x20fc9b44, (q31_t)0x76de8f9e, (q31_t)0x20f1d5de, + (q31_t)0x76e5068a, (q31_t)0x20e70f32, (q31_t)0x76eb7b58, (q31_t)0x20dc4742, + (q31_t)0x76f1ee09, (q31_t)0x20d17e0d, (q31_t)0x76f85e9a, (q31_t)0x20c6b395, + (q31_t)0x76fecd0e, (q31_t)0x20bbe7d8, (q31_t)0x77053962, (q31_t)0x20b11ad9, + (q31_t)0x770ba398, (q31_t)0x20a64c97, (q31_t)0x77120bae, (q31_t)0x209b7d13, + (q31_t)0x771871a5, (q31_t)0x2090ac4d, (q31_t)0x771ed57c, (q31_t)0x2085da46, + (q31_t)0x77253733, (q31_t)0x207b06fe, (q31_t)0x772b96ca, (q31_t)0x20703275, + (q31_t)0x7731f440, (q31_t)0x20655cac, (q31_t)0x77384f95, (q31_t)0x205a85a3, + (q31_t)0x773ea8ca, (q31_t)0x204fad5b, (q31_t)0x7744ffdd, (q31_t)0x2044d3d4, + (q31_t)0x774b54ce, (q31_t)0x2039f90f, (q31_t)0x7751a79e, (q31_t)0x202f1d0b, + (q31_t)0x7757f84c, (q31_t)0x20243fca, (q31_t)0x775e46d8, (q31_t)0x2019614c, + (q31_t)0x77649341, (q31_t)0x200e8190, (q31_t)0x776add88, (q31_t)0x2003a099, + (q31_t)0x777125ac, (q31_t)0x1ff8be65, (q31_t)0x77776bac, (q31_t)0x1feddaf6, + (q31_t)0x777daf89, (q31_t)0x1fe2f64c, (q31_t)0x7783f143, (q31_t)0x1fd81067, + (q31_t)0x778a30d8, (q31_t)0x1fcd2948, (q31_t)0x77906e49, (q31_t)0x1fc240ef, + (q31_t)0x7796a996, (q31_t)0x1fb7575c, (q31_t)0x779ce2be, (q31_t)0x1fac6c91, + (q31_t)0x77a319c2, (q31_t)0x1fa1808c, (q31_t)0x77a94ea0, (q31_t)0x1f969350, + (q31_t)0x77af8159, (q31_t)0x1f8ba4dc, (q31_t)0x77b5b1ec, (q31_t)0x1f80b531, + (q31_t)0x77bbe05a, (q31_t)0x1f75c44e, (q31_t)0x77c20ca1, (q31_t)0x1f6ad235, + (q31_t)0x77c836c2, (q31_t)0x1f5fdee6, (q31_t)0x77ce5ebd, (q31_t)0x1f54ea62, + (q31_t)0x77d48490, (q31_t)0x1f49f4a8, (q31_t)0x77daa83d, (q31_t)0x1f3efdb9, + (q31_t)0x77e0c9c3, (q31_t)0x1f340596, (q31_t)0x77e6e921, (q31_t)0x1f290c3f, + (q31_t)0x77ed0657, (q31_t)0x1f1e11b5, (q31_t)0x77f32165, (q31_t)0x1f1315f7, + (q31_t)0x77f93a4b, (q31_t)0x1f081907, (q31_t)0x77ff5109, (q31_t)0x1efd1ae4, + (q31_t)0x7805659e, (q31_t)0x1ef21b90, (q31_t)0x780b780a, (q31_t)0x1ee71b0a, + (q31_t)0x7811884d, (q31_t)0x1edc1953, (q31_t)0x78179666, (q31_t)0x1ed1166b, + (q31_t)0x781da256, (q31_t)0x1ec61254, (q31_t)0x7823ac1d, (q31_t)0x1ebb0d0d, + (q31_t)0x7829b3b9, (q31_t)0x1eb00696, (q31_t)0x782fb92a, (q31_t)0x1ea4fef0, + (q31_t)0x7835bc71, (q31_t)0x1e99f61d, (q31_t)0x783bbd8e, (q31_t)0x1e8eec1b, + (q31_t)0x7841bc7f, (q31_t)0x1e83e0eb, (q31_t)0x7847b946, (q31_t)0x1e78d48e, + (q31_t)0x784db3e0, (q31_t)0x1e6dc705, (q31_t)0x7853ac4f, (q31_t)0x1e62b84f, + (q31_t)0x7859a292, (q31_t)0x1e57a86d, (q31_t)0x785f96a9, (q31_t)0x1e4c9760, + (q31_t)0x78658894, (q31_t)0x1e418528, (q31_t)0x786b7852, (q31_t)0x1e3671c5, + (q31_t)0x787165e3, (q31_t)0x1e2b5d38, (q31_t)0x78775147, (q31_t)0x1e204781, + (q31_t)0x787d3a7e, (q31_t)0x1e1530a1, (q31_t)0x78832187, (q31_t)0x1e0a1898, + (q31_t)0x78890663, (q31_t)0x1dfeff67, (q31_t)0x788ee910, (q31_t)0x1df3e50d, + (q31_t)0x7894c98f, (q31_t)0x1de8c98c, (q31_t)0x789aa7e0, (q31_t)0x1dddace4, + (q31_t)0x78a08402, (q31_t)0x1dd28f15, (q31_t)0x78a65df6, (q31_t)0x1dc7701f, + (q31_t)0x78ac35ba, (q31_t)0x1dbc5004, (q31_t)0x78b20b4f, (q31_t)0x1db12ec3, + (q31_t)0x78b7deb4, (q31_t)0x1da60c5d, (q31_t)0x78bdafea, (q31_t)0x1d9ae8d2, + (q31_t)0x78c37eef, (q31_t)0x1d8fc424, (q31_t)0x78c94bc4, (q31_t)0x1d849e51, + (q31_t)0x78cf1669, (q31_t)0x1d79775c, (q31_t)0x78d4dedd, (q31_t)0x1d6e4f43, + (q31_t)0x78daa520, (q31_t)0x1d632608, (q31_t)0x78e06932, (q31_t)0x1d57fbaa, + (q31_t)0x78e62b13, (q31_t)0x1d4cd02c, (q31_t)0x78ebeac2, (q31_t)0x1d41a38c, + (q31_t)0x78f1a840, (q31_t)0x1d3675cb, (q31_t)0x78f7638b, (q31_t)0x1d2b46ea, + (q31_t)0x78fd1ca4, (q31_t)0x1d2016e9, (q31_t)0x7902d38b, (q31_t)0x1d14e5c9, + (q31_t)0x7908883f, (q31_t)0x1d09b389, (q31_t)0x790e3ac0, (q31_t)0x1cfe802b, + (q31_t)0x7913eb0e, (q31_t)0x1cf34baf, (q31_t)0x79199929, (q31_t)0x1ce81615, + (q31_t)0x791f4510, (q31_t)0x1cdcdf5e, (q31_t)0x7924eec3, (q31_t)0x1cd1a78a, + (q31_t)0x792a9642, (q31_t)0x1cc66e99, (q31_t)0x79303b8e, (q31_t)0x1cbb348d, + (q31_t)0x7935dea4, (q31_t)0x1caff965, (q31_t)0x793b7f86, (q31_t)0x1ca4bd21, + (q31_t)0x79411e33, (q31_t)0x1c997fc4, (q31_t)0x7946baac, (q31_t)0x1c8e414b, + (q31_t)0x794c54ee, (q31_t)0x1c8301b9, (q31_t)0x7951ecfc, (q31_t)0x1c77c10e, + (q31_t)0x795782d3, (q31_t)0x1c6c7f4a, (q31_t)0x795d1675, (q31_t)0x1c613c6d, + (q31_t)0x7962a7e0, (q31_t)0x1c55f878, (q31_t)0x79683715, (q31_t)0x1c4ab36b, + (q31_t)0x796dc414, (q31_t)0x1c3f6d47, (q31_t)0x79734edc, (q31_t)0x1c34260c, + (q31_t)0x7978d76c, (q31_t)0x1c28ddbb, (q31_t)0x797e5dc6, (q31_t)0x1c1d9454, + (q31_t)0x7983e1e8, (q31_t)0x1c1249d8, (q31_t)0x798963d2, (q31_t)0x1c06fe46, + (q31_t)0x798ee385, (q31_t)0x1bfbb1a0, (q31_t)0x799460ff, (q31_t)0x1bf063e6, + (q31_t)0x7999dc42, (q31_t)0x1be51518, (q31_t)0x799f554b, (q31_t)0x1bd9c537, + (q31_t)0x79a4cc1c, (q31_t)0x1bce7442, (q31_t)0x79aa40b4, (q31_t)0x1bc3223c, + (q31_t)0x79afb313, (q31_t)0x1bb7cf23, (q31_t)0x79b52339, (q31_t)0x1bac7af9, + (q31_t)0x79ba9125, (q31_t)0x1ba125bd, (q31_t)0x79bffcd7, (q31_t)0x1b95cf71, + (q31_t)0x79c5664f, (q31_t)0x1b8a7815, (q31_t)0x79cacd8d, (q31_t)0x1b7f1fa9, + (q31_t)0x79d03291, (q31_t)0x1b73c62d, (q31_t)0x79d5955a, (q31_t)0x1b686ba3, + (q31_t)0x79daf5e8, (q31_t)0x1b5d100a, (q31_t)0x79e0543c, (q31_t)0x1b51b363, + (q31_t)0x79e5b054, (q31_t)0x1b4655ae, (q31_t)0x79eb0a31, (q31_t)0x1b3af6ec, + (q31_t)0x79f061d2, (q31_t)0x1b2f971e, (q31_t)0x79f5b737, (q31_t)0x1b243643, + (q31_t)0x79fb0a60, (q31_t)0x1b18d45c, (q31_t)0x7a005b4d, (q31_t)0x1b0d716a, + (q31_t)0x7a05a9fd, (q31_t)0x1b020d6c, (q31_t)0x7a0af671, (q31_t)0x1af6a865, + (q31_t)0x7a1040a8, (q31_t)0x1aeb4253, (q31_t)0x7a1588a2, (q31_t)0x1adfdb37, + (q31_t)0x7a1ace5f, (q31_t)0x1ad47312, (q31_t)0x7a2011de, (q31_t)0x1ac909e5, + (q31_t)0x7a25531f, (q31_t)0x1abd9faf, (q31_t)0x7a2a9223, (q31_t)0x1ab23471, + (q31_t)0x7a2fcee8, (q31_t)0x1aa6c82b, (q31_t)0x7a350970, (q31_t)0x1a9b5adf, + (q31_t)0x7a3a41b9, (q31_t)0x1a8fec8c, (q31_t)0x7a3f77c3, (q31_t)0x1a847d33, + (q31_t)0x7a44ab8e, (q31_t)0x1a790cd4, (q31_t)0x7a49dd1a, (q31_t)0x1a6d9b70, + (q31_t)0x7a4f0c67, (q31_t)0x1a622907, (q31_t)0x7a543974, (q31_t)0x1a56b599, + (q31_t)0x7a596442, (q31_t)0x1a4b4128, (q31_t)0x7a5e8cd0, (q31_t)0x1a3fcbb3, + (q31_t)0x7a63b31d, (q31_t)0x1a34553b, (q31_t)0x7a68d72b, (q31_t)0x1a28ddc0, + (q31_t)0x7a6df8f8, (q31_t)0x1a1d6544, (q31_t)0x7a731884, (q31_t)0x1a11ebc5, + (q31_t)0x7a7835cf, (q31_t)0x1a067145, (q31_t)0x7a7d50da, (q31_t)0x19faf5c5, + (q31_t)0x7a8269a3, (q31_t)0x19ef7944, (q31_t)0x7a87802a, (q31_t)0x19e3fbc3, + (q31_t)0x7a8c9470, (q31_t)0x19d87d42, (q31_t)0x7a91a674, (q31_t)0x19ccfdc2, + (q31_t)0x7a96b636, (q31_t)0x19c17d44, (q31_t)0x7a9bc3b6, (q31_t)0x19b5fbc8, + (q31_t)0x7aa0cef3, (q31_t)0x19aa794d, (q31_t)0x7aa5d7ee, (q31_t)0x199ef5d6, + (q31_t)0x7aaadea6, (q31_t)0x19937161, (q31_t)0x7aafe31b, (q31_t)0x1987ebf0, + (q31_t)0x7ab4e54c, (q31_t)0x197c6584, (q31_t)0x7ab9e53a, (q31_t)0x1970de1b, + (q31_t)0x7abee2e5, (q31_t)0x196555b8, (q31_t)0x7ac3de4c, (q31_t)0x1959cc5a, + (q31_t)0x7ac8d76f, (q31_t)0x194e4201, (q31_t)0x7acdce4d, (q31_t)0x1942b6af, + (q31_t)0x7ad2c2e8, (q31_t)0x19372a64, (q31_t)0x7ad7b53d, (q31_t)0x192b9d1f, + (q31_t)0x7adca54e, (q31_t)0x19200ee3, (q31_t)0x7ae1931a, (q31_t)0x19147fae, + (q31_t)0x7ae67ea1, (q31_t)0x1908ef82, (q31_t)0x7aeb67e3, (q31_t)0x18fd5e5f, + (q31_t)0x7af04edf, (q31_t)0x18f1cc45, (q31_t)0x7af53395, (q31_t)0x18e63935, + (q31_t)0x7afa1605, (q31_t)0x18daa52f, (q31_t)0x7afef630, (q31_t)0x18cf1034, + (q31_t)0x7b03d414, (q31_t)0x18c37a44, (q31_t)0x7b08afb2, (q31_t)0x18b7e35f, + (q31_t)0x7b0d8909, (q31_t)0x18ac4b87, (q31_t)0x7b126019, (q31_t)0x18a0b2bb, + (q31_t)0x7b1734e2, (q31_t)0x189518fc, (q31_t)0x7b1c0764, (q31_t)0x18897e4a, + (q31_t)0x7b20d79e, (q31_t)0x187de2a7, (q31_t)0x7b25a591, (q31_t)0x18724611, + (q31_t)0x7b2a713d, (q31_t)0x1866a88a, (q31_t)0x7b2f3aa0, (q31_t)0x185b0a13, + (q31_t)0x7b3401bb, (q31_t)0x184f6aab, (q31_t)0x7b38c68e, (q31_t)0x1843ca53, + (q31_t)0x7b3d8918, (q31_t)0x1838290c, (q31_t)0x7b42495a, (q31_t)0x182c86d5, + (q31_t)0x7b470753, (q31_t)0x1820e3b0, (q31_t)0x7b4bc303, (q31_t)0x18153f9d, + (q31_t)0x7b507c69, (q31_t)0x18099a9c, (q31_t)0x7b553386, (q31_t)0x17fdf4ae, + (q31_t)0x7b59e85a, (q31_t)0x17f24dd3, (q31_t)0x7b5e9ae4, (q31_t)0x17e6a60c, + (q31_t)0x7b634b23, (q31_t)0x17dafd59, (q31_t)0x7b67f919, (q31_t)0x17cf53bb, + (q31_t)0x7b6ca4c4, (q31_t)0x17c3a931, (q31_t)0x7b714e25, (q31_t)0x17b7fdbd, + (q31_t)0x7b75f53c, (q31_t)0x17ac515f, (q31_t)0x7b7a9a07, (q31_t)0x17a0a417, + (q31_t)0x7b7f3c87, (q31_t)0x1794f5e6, (q31_t)0x7b83dcbc, (q31_t)0x178946cc, + (q31_t)0x7b887aa6, (q31_t)0x177d96ca, (q31_t)0x7b8d1644, (q31_t)0x1771e5e0, + (q31_t)0x7b91af97, (q31_t)0x1766340f, (q31_t)0x7b96469d, (q31_t)0x175a8157, + (q31_t)0x7b9adb57, (q31_t)0x174ecdb8, (q31_t)0x7b9f6dc5, (q31_t)0x17431933, + (q31_t)0x7ba3fde7, (q31_t)0x173763c9, (q31_t)0x7ba88bbc, (q31_t)0x172bad7a, + (q31_t)0x7bad1744, (q31_t)0x171ff646, (q31_t)0x7bb1a080, (q31_t)0x17143e2d, + (q31_t)0x7bb6276e, (q31_t)0x17088531, (q31_t)0x7bbaac0e, (q31_t)0x16fccb51, + (q31_t)0x7bbf2e62, (q31_t)0x16f1108f, (q31_t)0x7bc3ae67, (q31_t)0x16e554ea, + (q31_t)0x7bc82c1f, (q31_t)0x16d99864, (q31_t)0x7bcca789, (q31_t)0x16cddafb, + (q31_t)0x7bd120a4, (q31_t)0x16c21cb2, (q31_t)0x7bd59771, (q31_t)0x16b65d88, + (q31_t)0x7bda0bf0, (q31_t)0x16aa9d7e, (q31_t)0x7bde7e20, (q31_t)0x169edc94, + (q31_t)0x7be2ee01, (q31_t)0x16931acb, (q31_t)0x7be75b93, (q31_t)0x16875823, + (q31_t)0x7bebc6d5, (q31_t)0x167b949d, (q31_t)0x7bf02fc9, (q31_t)0x166fd039, + (q31_t)0x7bf4966c, (q31_t)0x16640af7, (q31_t)0x7bf8fac0, (q31_t)0x165844d8, + (q31_t)0x7bfd5cc4, (q31_t)0x164c7ddd, (q31_t)0x7c01bc78, (q31_t)0x1640b606, + (q31_t)0x7c0619dc, (q31_t)0x1634ed53, (q31_t)0x7c0a74f0, (q31_t)0x162923c5, + (q31_t)0x7c0ecdb2, (q31_t)0x161d595d, (q31_t)0x7c132424, (q31_t)0x16118e1a, + (q31_t)0x7c177845, (q31_t)0x1605c1fd, (q31_t)0x7c1bca16, (q31_t)0x15f9f507, + (q31_t)0x7c201994, (q31_t)0x15ee2738, (q31_t)0x7c2466c2, (q31_t)0x15e25890, + (q31_t)0x7c28b19e, (q31_t)0x15d68911, (q31_t)0x7c2cfa28, (q31_t)0x15cab8ba, + (q31_t)0x7c314060, (q31_t)0x15bee78c, (q31_t)0x7c358446, (q31_t)0x15b31587, + (q31_t)0x7c39c5da, (q31_t)0x15a742ac, (q31_t)0x7c3e051b, (q31_t)0x159b6efb, + (q31_t)0x7c42420a, (q31_t)0x158f9a76, (q31_t)0x7c467ca6, (q31_t)0x1583c51b, + (q31_t)0x7c4ab4ef, (q31_t)0x1577eeec, (q31_t)0x7c4eeae5, (q31_t)0x156c17e9, + (q31_t)0x7c531e88, (q31_t)0x15604013, (q31_t)0x7c574fd8, (q31_t)0x1554676a, + (q31_t)0x7c5b7ed4, (q31_t)0x15488dee, (q31_t)0x7c5fab7c, (q31_t)0x153cb3a0, + (q31_t)0x7c63d5d1, (q31_t)0x1530d881, (q31_t)0x7c67fdd1, (q31_t)0x1524fc90, + (q31_t)0x7c6c237e, (q31_t)0x15191fcf, (q31_t)0x7c7046d6, (q31_t)0x150d423d, + (q31_t)0x7c7467d9, (q31_t)0x150163dc, (q31_t)0x7c788688, (q31_t)0x14f584ac, + (q31_t)0x7c7ca2e2, (q31_t)0x14e9a4ac, (q31_t)0x7c80bce7, (q31_t)0x14ddc3de, + (q31_t)0x7c84d496, (q31_t)0x14d1e242, (q31_t)0x7c88e9f1, (q31_t)0x14c5ffd9, + (q31_t)0x7c8cfcf6, (q31_t)0x14ba1ca3, (q31_t)0x7c910da5, (q31_t)0x14ae38a0, + (q31_t)0x7c951bff, (q31_t)0x14a253d1, (q31_t)0x7c992803, (q31_t)0x14966e36, + (q31_t)0x7c9d31b0, (q31_t)0x148a87d1, (q31_t)0x7ca13908, (q31_t)0x147ea0a0, + (q31_t)0x7ca53e09, (q31_t)0x1472b8a5, (q31_t)0x7ca940b3, (q31_t)0x1466cfe1, + (q31_t)0x7cad4107, (q31_t)0x145ae653, (q31_t)0x7cb13f04, (q31_t)0x144efbfc, + (q31_t)0x7cb53aaa, (q31_t)0x144310dd, (q31_t)0x7cb933f9, (q31_t)0x143724f5, + (q31_t)0x7cbd2af0, (q31_t)0x142b3846, (q31_t)0x7cc11f90, (q31_t)0x141f4ad1, + (q31_t)0x7cc511d9, (q31_t)0x14135c94, (q31_t)0x7cc901c9, (q31_t)0x14076d91, + (q31_t)0x7cccef62, (q31_t)0x13fb7dc9, (q31_t)0x7cd0daa2, (q31_t)0x13ef8d3c, + (q31_t)0x7cd4c38b, (q31_t)0x13e39be9, (q31_t)0x7cd8aa1b, (q31_t)0x13d7a9d3, + (q31_t)0x7cdc8e52, (q31_t)0x13cbb6f8, (q31_t)0x7ce07031, (q31_t)0x13bfc35b, + (q31_t)0x7ce44fb7, (q31_t)0x13b3cefa, (q31_t)0x7ce82ce4, (q31_t)0x13a7d9d7, + (q31_t)0x7cec07b8, (q31_t)0x139be3f2, (q31_t)0x7cefe032, (q31_t)0x138fed4b, + (q31_t)0x7cf3b653, (q31_t)0x1383f5e3, (q31_t)0x7cf78a1b, (q31_t)0x1377fdbb, + (q31_t)0x7cfb5b89, (q31_t)0x136c04d2, (q31_t)0x7cff2a9d, (q31_t)0x13600b2a, + (q31_t)0x7d02f757, (q31_t)0x135410c3, (q31_t)0x7d06c1b6, (q31_t)0x1348159d, + (q31_t)0x7d0a89bc, (q31_t)0x133c19b8, (q31_t)0x7d0e4f67, (q31_t)0x13301d16, + (q31_t)0x7d1212b7, (q31_t)0x13241fb6, (q31_t)0x7d15d3ad, (q31_t)0x1318219a, + (q31_t)0x7d199248, (q31_t)0x130c22c1, (q31_t)0x7d1d4e88, (q31_t)0x1300232c, + (q31_t)0x7d21086c, (q31_t)0x12f422db, (q31_t)0x7d24bff6, (q31_t)0x12e821cf, + (q31_t)0x7d287523, (q31_t)0x12dc2009, (q31_t)0x7d2c27f6, (q31_t)0x12d01d89, + (q31_t)0x7d2fd86c, (q31_t)0x12c41a4f, (q31_t)0x7d338687, (q31_t)0x12b8165b, + (q31_t)0x7d373245, (q31_t)0x12ac11af, (q31_t)0x7d3adba7, (q31_t)0x12a00c4b, + (q31_t)0x7d3e82ae, (q31_t)0x1294062f, (q31_t)0x7d422757, (q31_t)0x1287ff5b, + (q31_t)0x7d45c9a4, (q31_t)0x127bf7d1, (q31_t)0x7d496994, (q31_t)0x126fef90, + (q31_t)0x7d4d0728, (q31_t)0x1263e699, (q31_t)0x7d50a25e, (q31_t)0x1257dced, + (q31_t)0x7d543b37, (q31_t)0x124bd28c, (q31_t)0x7d57d1b3, (q31_t)0x123fc776, + (q31_t)0x7d5b65d2, (q31_t)0x1233bbac, (q31_t)0x7d5ef793, (q31_t)0x1227af2e, + (q31_t)0x7d6286f6, (q31_t)0x121ba1fd, (q31_t)0x7d6613fb, (q31_t)0x120f941a, + (q31_t)0x7d699ea3, (q31_t)0x12038584, (q31_t)0x7d6d26ec, (q31_t)0x11f7763c, + (q31_t)0x7d70acd7, (q31_t)0x11eb6643, (q31_t)0x7d743064, (q31_t)0x11df5599, + (q31_t)0x7d77b192, (q31_t)0x11d3443f, (q31_t)0x7d7b3061, (q31_t)0x11c73235, + (q31_t)0x7d7eacd2, (q31_t)0x11bb1f7c, (q31_t)0x7d8226e4, (q31_t)0x11af0c13, + (q31_t)0x7d859e96, (q31_t)0x11a2f7fc, (q31_t)0x7d8913ea, (q31_t)0x1196e337, + (q31_t)0x7d8c86de, (q31_t)0x118acdc4, (q31_t)0x7d8ff772, (q31_t)0x117eb7a4, + (q31_t)0x7d9365a8, (q31_t)0x1172a0d7, (q31_t)0x7d96d17d, (q31_t)0x1166895f, + (q31_t)0x7d9a3af2, (q31_t)0x115a713a, (q31_t)0x7d9da208, (q31_t)0x114e586a, + (q31_t)0x7da106bd, (q31_t)0x11423ef0, (q31_t)0x7da46912, (q31_t)0x113624cb, + (q31_t)0x7da7c907, (q31_t)0x112a09fc, (q31_t)0x7dab269b, (q31_t)0x111dee84, + (q31_t)0x7dae81cf, (q31_t)0x1111d263, (q31_t)0x7db1daa2, (q31_t)0x1105b599, + (q31_t)0x7db53113, (q31_t)0x10f99827, (q31_t)0x7db88524, (q31_t)0x10ed7a0e, + (q31_t)0x7dbbd6d4, (q31_t)0x10e15b4e, (q31_t)0x7dbf2622, (q31_t)0x10d53be7, + (q31_t)0x7dc2730f, (q31_t)0x10c91bda, (q31_t)0x7dc5bd9b, (q31_t)0x10bcfb28, + (q31_t)0x7dc905c5, (q31_t)0x10b0d9d0, (q31_t)0x7dcc4b8d, (q31_t)0x10a4b7d3, + (q31_t)0x7dcf8ef3, (q31_t)0x10989532, (q31_t)0x7dd2cff7, (q31_t)0x108c71ee, + (q31_t)0x7dd60e99, (q31_t)0x10804e06, (q31_t)0x7dd94ad8, (q31_t)0x1074297b, + (q31_t)0x7ddc84b5, (q31_t)0x1068044e, (q31_t)0x7ddfbc30, (q31_t)0x105bde7f, + (q31_t)0x7de2f148, (q31_t)0x104fb80e, (q31_t)0x7de623fd, (q31_t)0x104390fd, + (q31_t)0x7de9544f, (q31_t)0x1037694b, (q31_t)0x7dec823e, (q31_t)0x102b40f8, + (q31_t)0x7defadca, (q31_t)0x101f1807, (q31_t)0x7df2d6f3, (q31_t)0x1012ee76, + (q31_t)0x7df5fdb8, (q31_t)0x1006c446, (q31_t)0x7df9221a, (q31_t)0xffa9979, + (q31_t)0x7dfc4418, (q31_t)0xfee6e0d, (q31_t)0x7dff63b2, (q31_t)0xfe24205, + (q31_t)0x7e0280e9, (q31_t)0xfd6155f, (q31_t)0x7e059bbb, (q31_t)0xfc9e81e, + (q31_t)0x7e08b42a, (q31_t)0xfbdba40, (q31_t)0x7e0bca34, (q31_t)0xfb18bc8, + (q31_t)0x7e0eddd9, (q31_t)0xfa55cb4, (q31_t)0x7e11ef1b, (q31_t)0xf992d06, + (q31_t)0x7e14fdf7, (q31_t)0xf8cfcbe, (q31_t)0x7e180a6f, (q31_t)0xf80cbdc, + (q31_t)0x7e1b1482, (q31_t)0xf749a61, (q31_t)0x7e1e1c30, (q31_t)0xf68684e, + (q31_t)0x7e212179, (q31_t)0xf5c35a3, (q31_t)0x7e24245d, (q31_t)0xf500260, + (q31_t)0x7e2724db, (q31_t)0xf43ce86, (q31_t)0x7e2a22f4, (q31_t)0xf379a16, + (q31_t)0x7e2d1ea8, (q31_t)0xf2b650f, (q31_t)0x7e3017f6, (q31_t)0xf1f2f73, + (q31_t)0x7e330ede, (q31_t)0xf12f941, (q31_t)0x7e360360, (q31_t)0xf06c27a, + (q31_t)0x7e38f57c, (q31_t)0xefa8b20, (q31_t)0x7e3be532, (q31_t)0xeee5331, + (q31_t)0x7e3ed282, (q31_t)0xee21aaf, (q31_t)0x7e41bd6c, (q31_t)0xed5e19a, + (q31_t)0x7e44a5ef, (q31_t)0xec9a7f3, (q31_t)0x7e478c0b, (q31_t)0xebd6db9, + (q31_t)0x7e4a6fc1, (q31_t)0xeb132ef, (q31_t)0x7e4d5110, (q31_t)0xea4f793, + (q31_t)0x7e502ff9, (q31_t)0xe98bba7, (q31_t)0x7e530c7a, (q31_t)0xe8c7f2a, + (q31_t)0x7e55e694, (q31_t)0xe80421e, (q31_t)0x7e58be47, (q31_t)0xe740483, + (q31_t)0x7e5b9392, (q31_t)0xe67c65a, (q31_t)0x7e5e6676, (q31_t)0xe5b87a2, + (q31_t)0x7e6136f3, (q31_t)0xe4f485c, (q31_t)0x7e640507, (q31_t)0xe430889, + (q31_t)0x7e66d0b4, (q31_t)0xe36c82a, (q31_t)0x7e6999fa, (q31_t)0xe2a873e, + (q31_t)0x7e6c60d7, (q31_t)0xe1e45c6, (q31_t)0x7e6f254c, (q31_t)0xe1203c3, + (q31_t)0x7e71e759, (q31_t)0xe05c135, (q31_t)0x7e74a6fd, (q31_t)0xdf97e1d, + (q31_t)0x7e77643a, (q31_t)0xded3a7b, (q31_t)0x7e7a1f0d, (q31_t)0xde0f64f, + (q31_t)0x7e7cd778, (q31_t)0xdd4b19a, (q31_t)0x7e7f8d7b, (q31_t)0xdc86c5d, + (q31_t)0x7e824114, (q31_t)0xdbc2698, (q31_t)0x7e84f245, (q31_t)0xdafe04b, + (q31_t)0x7e87a10c, (q31_t)0xda39978, (q31_t)0x7e8a4d6a, (q31_t)0xd97521d, + (q31_t)0x7e8cf75f, (q31_t)0xd8b0a3d, (q31_t)0x7e8f9eeb, (q31_t)0xd7ec1d6, + (q31_t)0x7e92440d, (q31_t)0xd7278eb, (q31_t)0x7e94e6c6, (q31_t)0xd662f7b, + (q31_t)0x7e978715, (q31_t)0xd59e586, (q31_t)0x7e9a24fb, (q31_t)0xd4d9b0e, + (q31_t)0x7e9cc076, (q31_t)0xd415013, (q31_t)0x7e9f5988, (q31_t)0xd350495, + (q31_t)0x7ea1f02f, (q31_t)0xd28b894, (q31_t)0x7ea4846c, (q31_t)0xd1c6c11, + (q31_t)0x7ea7163f, (q31_t)0xd101f0e, (q31_t)0x7ea9a5a8, (q31_t)0xd03d189, + (q31_t)0x7eac32a6, (q31_t)0xcf78383, (q31_t)0x7eaebd3a, (q31_t)0xceb34fe, + (q31_t)0x7eb14563, (q31_t)0xcdee5f9, (q31_t)0x7eb3cb21, (q31_t)0xcd29676, + (q31_t)0x7eb64e75, (q31_t)0xcc64673, (q31_t)0x7eb8cf5d, (q31_t)0xcb9f5f3, + (q31_t)0x7ebb4ddb, (q31_t)0xcada4f5, (q31_t)0x7ebdc9ed, (q31_t)0xca1537a, + (q31_t)0x7ec04394, (q31_t)0xc950182, (q31_t)0x7ec2bad0, (q31_t)0xc88af0e, + (q31_t)0x7ec52fa0, (q31_t)0xc7c5c1e, (q31_t)0x7ec7a205, (q31_t)0xc7008b3, + (q31_t)0x7eca11fe, (q31_t)0xc63b4ce, (q31_t)0x7ecc7f8b, (q31_t)0xc57606e, + (q31_t)0x7eceeaad, (q31_t)0xc4b0b94, (q31_t)0x7ed15363, (q31_t)0xc3eb641, + (q31_t)0x7ed3b9ad, (q31_t)0xc326075, (q31_t)0x7ed61d8a, (q31_t)0xc260a31, + (q31_t)0x7ed87efc, (q31_t)0xc19b374, (q31_t)0x7edade01, (q31_t)0xc0d5c41, + (q31_t)0x7edd3a9a, (q31_t)0xc010496, (q31_t)0x7edf94c7, (q31_t)0xbf4ac75, + (q31_t)0x7ee1ec87, (q31_t)0xbe853de, (q31_t)0x7ee441da, (q31_t)0xbdbfad1, + (q31_t)0x7ee694c1, (q31_t)0xbcfa150, (q31_t)0x7ee8e53a, (q31_t)0xbc34759, + (q31_t)0x7eeb3347, (q31_t)0xbb6ecef, (q31_t)0x7eed7ee7, (q31_t)0xbaa9211, + (q31_t)0x7eefc81a, (q31_t)0xb9e36c0, (q31_t)0x7ef20ee0, (q31_t)0xb91dafc, + (q31_t)0x7ef45338, (q31_t)0xb857ec7, (q31_t)0x7ef69523, (q31_t)0xb79221f, + (q31_t)0x7ef8d4a1, (q31_t)0xb6cc506, (q31_t)0x7efb11b1, (q31_t)0xb60677c, + (q31_t)0x7efd4c54, (q31_t)0xb540982, (q31_t)0x7eff8489, (q31_t)0xb47ab19, + (q31_t)0x7f01ba50, (q31_t)0xb3b4c40, (q31_t)0x7f03eda9, (q31_t)0xb2eecf8, + (q31_t)0x7f061e95, (q31_t)0xb228d42, (q31_t)0x7f084d12, (q31_t)0xb162d1d, + (q31_t)0x7f0a7921, (q31_t)0xb09cc8c, (q31_t)0x7f0ca2c2, (q31_t)0xafd6b8d, + (q31_t)0x7f0ec9f5, (q31_t)0xaf10a22, (q31_t)0x7f10eeb9, (q31_t)0xae4a84b, + (q31_t)0x7f13110f, (q31_t)0xad84609, (q31_t)0x7f1530f7, (q31_t)0xacbe35b, + (q31_t)0x7f174e70, (q31_t)0xabf8043, (q31_t)0x7f19697a, (q31_t)0xab31cc1, + (q31_t)0x7f1b8215, (q31_t)0xaa6b8d5, (q31_t)0x7f1d9842, (q31_t)0xa9a5480, + (q31_t)0x7f1fabff, (q31_t)0xa8defc3, (q31_t)0x7f21bd4e, (q31_t)0xa818a9d, + (q31_t)0x7f23cc2e, (q31_t)0xa752510, (q31_t)0x7f25d89e, (q31_t)0xa68bf1b, + (q31_t)0x7f27e29f, (q31_t)0xa5c58c0, (q31_t)0x7f29ea31, (q31_t)0xa4ff1fe, + (q31_t)0x7f2bef53, (q31_t)0xa438ad7, (q31_t)0x7f2df206, (q31_t)0xa37234a, + (q31_t)0x7f2ff24a, (q31_t)0xa2abb59, (q31_t)0x7f31f01d, (q31_t)0xa1e5303, + (q31_t)0x7f33eb81, (q31_t)0xa11ea49, (q31_t)0x7f35e476, (q31_t)0xa05812c, + (q31_t)0x7f37dafa, (q31_t)0x9f917ac, (q31_t)0x7f39cf0e, (q31_t)0x9ecadc9, + (q31_t)0x7f3bc0b3, (q31_t)0x9e04385, (q31_t)0x7f3dafe7, (q31_t)0x9d3d8df, + (q31_t)0x7f3f9cab, (q31_t)0x9c76dd8, (q31_t)0x7f4186ff, (q31_t)0x9bb0271, + (q31_t)0x7f436ee3, (q31_t)0x9ae96aa, (q31_t)0x7f455456, (q31_t)0x9a22a83, + (q31_t)0x7f473759, (q31_t)0x995bdfd, (q31_t)0x7f4917eb, (q31_t)0x9895118, + (q31_t)0x7f4af60d, (q31_t)0x97ce3d5, (q31_t)0x7f4cd1be, (q31_t)0x9707635, + (q31_t)0x7f4eaafe, (q31_t)0x9640837, (q31_t)0x7f5081cd, (q31_t)0x95799dd, + (q31_t)0x7f52562c, (q31_t)0x94b2b27, (q31_t)0x7f54281a, (q31_t)0x93ebc14, + (q31_t)0x7f55f796, (q31_t)0x9324ca7, (q31_t)0x7f57c4a2, (q31_t)0x925dcdf, + (q31_t)0x7f598f3c, (q31_t)0x9196cbc, (q31_t)0x7f5b5765, (q31_t)0x90cfc40, + (q31_t)0x7f5d1d1d, (q31_t)0x9008b6a, (q31_t)0x7f5ee063, (q31_t)0x8f41a3c, + (q31_t)0x7f60a138, (q31_t)0x8e7a8b5, (q31_t)0x7f625f9b, (q31_t)0x8db36d6, + (q31_t)0x7f641b8d, (q31_t)0x8cec4a0, (q31_t)0x7f65d50d, (q31_t)0x8c25213, + (q31_t)0x7f678c1c, (q31_t)0x8b5df30, (q31_t)0x7f6940b8, (q31_t)0x8a96bf6, + (q31_t)0x7f6af2e3, (q31_t)0x89cf867, (q31_t)0x7f6ca29c, (q31_t)0x8908483, + (q31_t)0x7f6e4fe3, (q31_t)0x884104b, (q31_t)0x7f6ffab8, (q31_t)0x8779bbe, + (q31_t)0x7f71a31b, (q31_t)0x86b26de, (q31_t)0x7f73490b, (q31_t)0x85eb1ab, + (q31_t)0x7f74ec8a, (q31_t)0x8523c25, (q31_t)0x7f768d96, (q31_t)0x845c64d, + (q31_t)0x7f782c30, (q31_t)0x8395024, (q31_t)0x7f79c857, (q31_t)0x82cd9a9, + (q31_t)0x7f7b620c, (q31_t)0x82062de, (q31_t)0x7f7cf94e, (q31_t)0x813ebc2, + (q31_t)0x7f7e8e1e, (q31_t)0x8077457, (q31_t)0x7f80207b, (q31_t)0x7fafc9c, + (q31_t)0x7f81b065, (q31_t)0x7ee8493, (q31_t)0x7f833ddd, (q31_t)0x7e20c3b, + (q31_t)0x7f84c8e2, (q31_t)0x7d59396, (q31_t)0x7f865174, (q31_t)0x7c91aa3, + (q31_t)0x7f87d792, (q31_t)0x7bca163, (q31_t)0x7f895b3e, (q31_t)0x7b027d7, + (q31_t)0x7f8adc77, (q31_t)0x7a3adff, (q31_t)0x7f8c5b3d, (q31_t)0x79733dc, + (q31_t)0x7f8dd78f, (q31_t)0x78ab96e, (q31_t)0x7f8f516e, (q31_t)0x77e3eb5, + (q31_t)0x7f90c8da, (q31_t)0x771c3b3, (q31_t)0x7f923dd2, (q31_t)0x7654867, + (q31_t)0x7f93b058, (q31_t)0x758ccd2, (q31_t)0x7f952069, (q31_t)0x74c50f4, + (q31_t)0x7f968e07, (q31_t)0x73fd4cf, (q31_t)0x7f97f932, (q31_t)0x7335862, + (q31_t)0x7f9961e8, (q31_t)0x726dbae, (q31_t)0x7f9ac82c, (q31_t)0x71a5eb3, + (q31_t)0x7f9c2bfb, (q31_t)0x70de172, (q31_t)0x7f9d8d56, (q31_t)0x70163eb, + (q31_t)0x7f9eec3e, (q31_t)0x6f4e620, (q31_t)0x7fa048b2, (q31_t)0x6e86810, + (q31_t)0x7fa1a2b2, (q31_t)0x6dbe9bb, (q31_t)0x7fa2fa3d, (q31_t)0x6cf6b23, + (q31_t)0x7fa44f55, (q31_t)0x6c2ec48, (q31_t)0x7fa5a1f9, (q31_t)0x6b66d29, + (q31_t)0x7fa6f228, (q31_t)0x6a9edc9, (q31_t)0x7fa83fe3, (q31_t)0x69d6e27, + (q31_t)0x7fa98b2a, (q31_t)0x690ee44, (q31_t)0x7faad3fd, (q31_t)0x6846e1f, + (q31_t)0x7fac1a5b, (q31_t)0x677edbb, (q31_t)0x7fad5e45, (q31_t)0x66b6d16, + (q31_t)0x7fae9fbb, (q31_t)0x65eec33, (q31_t)0x7fafdebb, (q31_t)0x6526b10, + (q31_t)0x7fb11b48, (q31_t)0x645e9af, (q31_t)0x7fb2555f, (q31_t)0x6396810, + (q31_t)0x7fb38d02, (q31_t)0x62ce634, (q31_t)0x7fb4c231, (q31_t)0x620641a, + (q31_t)0x7fb5f4ea, (q31_t)0x613e1c5, (q31_t)0x7fb7252f, (q31_t)0x6075f33, + (q31_t)0x7fb852ff, (q31_t)0x5fadc66, (q31_t)0x7fb97e5a, (q31_t)0x5ee595d, + (q31_t)0x7fbaa740, (q31_t)0x5e1d61b, (q31_t)0x7fbbcdb1, (q31_t)0x5d5529e, + (q31_t)0x7fbcf1ad, (q31_t)0x5c8cee7, (q31_t)0x7fbe1334, (q31_t)0x5bc4af8, + (q31_t)0x7fbf3246, (q31_t)0x5afc6d0, (q31_t)0x7fc04ee3, (q31_t)0x5a3426f, + (q31_t)0x7fc1690a, (q31_t)0x596bdd7, (q31_t)0x7fc280bc, (q31_t)0x58a3908, + (q31_t)0x7fc395f9, (q31_t)0x57db403, (q31_t)0x7fc4a8c1, (q31_t)0x5712ec7, + (q31_t)0x7fc5b913, (q31_t)0x564a955, (q31_t)0x7fc6c6f0, (q31_t)0x55823ae, + (q31_t)0x7fc7d258, (q31_t)0x54b9dd3, (q31_t)0x7fc8db4a, (q31_t)0x53f17c3, + (q31_t)0x7fc9e1c6, (q31_t)0x532917f, (q31_t)0x7fcae5cd, (q31_t)0x5260b08, + (q31_t)0x7fcbe75e, (q31_t)0x519845e, (q31_t)0x7fcce67a, (q31_t)0x50cfd82, + (q31_t)0x7fcde320, (q31_t)0x5007674, (q31_t)0x7fcedd50, (q31_t)0x4f3ef35, + (q31_t)0x7fcfd50b, (q31_t)0x4e767c5, (q31_t)0x7fd0ca4f, (q31_t)0x4dae024, + (q31_t)0x7fd1bd1e, (q31_t)0x4ce5854, (q31_t)0x7fd2ad77, (q31_t)0x4c1d054, + (q31_t)0x7fd39b5a, (q31_t)0x4b54825, (q31_t)0x7fd486c7, (q31_t)0x4a8bfc7, + (q31_t)0x7fd56fbe, (q31_t)0x49c373c, (q31_t)0x7fd6563f, (q31_t)0x48fae83, + (q31_t)0x7fd73a4a, (q31_t)0x483259d, (q31_t)0x7fd81bdf, (q31_t)0x4769c8b, + (q31_t)0x7fd8fafe, (q31_t)0x46a134c, (q31_t)0x7fd9d7a7, (q31_t)0x45d89e2, + (q31_t)0x7fdab1d9, (q31_t)0x451004d, (q31_t)0x7fdb8996, (q31_t)0x444768d, + (q31_t)0x7fdc5edc, (q31_t)0x437eca4, (q31_t)0x7fdd31ac, (q31_t)0x42b6290, + (q31_t)0x7fde0205, (q31_t)0x41ed854, (q31_t)0x7fdecfe8, (q31_t)0x4124dee, + (q31_t)0x7fdf9b55, (q31_t)0x405c361, (q31_t)0x7fe0644b, (q31_t)0x3f938ac, + (q31_t)0x7fe12acb, (q31_t)0x3ecadcf, (q31_t)0x7fe1eed5, (q31_t)0x3e022cc, + (q31_t)0x7fe2b067, (q31_t)0x3d397a3, (q31_t)0x7fe36f84, (q31_t)0x3c70c54, + (q31_t)0x7fe42c2a, (q31_t)0x3ba80df, (q31_t)0x7fe4e659, (q31_t)0x3adf546, + (q31_t)0x7fe59e12, (q31_t)0x3a16988, (q31_t)0x7fe65354, (q31_t)0x394dda7, + (q31_t)0x7fe7061f, (q31_t)0x38851a2, (q31_t)0x7fe7b674, (q31_t)0x37bc57b, + (q31_t)0x7fe86452, (q31_t)0x36f3931, (q31_t)0x7fe90fb9, (q31_t)0x362acc5, + (q31_t)0x7fe9b8a9, (q31_t)0x3562038, (q31_t)0x7fea5f23, (q31_t)0x3499389, + (q31_t)0x7feb0326, (q31_t)0x33d06bb, (q31_t)0x7feba4b2, (q31_t)0x33079cc, + (q31_t)0x7fec43c7, (q31_t)0x323ecbe, (q31_t)0x7fece065, (q31_t)0x3175f91, + (q31_t)0x7fed7a8c, (q31_t)0x30ad245, (q31_t)0x7fee123d, (q31_t)0x2fe44dc, + (q31_t)0x7feea776, (q31_t)0x2f1b755, (q31_t)0x7fef3a39, (q31_t)0x2e529b0, + (q31_t)0x7fefca84, (q31_t)0x2d89bf0, (q31_t)0x7ff05858, (q31_t)0x2cc0e13, + (q31_t)0x7ff0e3b6, (q31_t)0x2bf801a, (q31_t)0x7ff16c9c, (q31_t)0x2b2f207, + (q31_t)0x7ff1f30b, (q31_t)0x2a663d8, (q31_t)0x7ff27703, (q31_t)0x299d590, + (q31_t)0x7ff2f884, (q31_t)0x28d472e, (q31_t)0x7ff3778e, (q31_t)0x280b8b3, + (q31_t)0x7ff3f420, (q31_t)0x2742a1f, (q31_t)0x7ff46e3c, (q31_t)0x2679b73, + (q31_t)0x7ff4e5e0, (q31_t)0x25b0caf, (q31_t)0x7ff55b0d, (q31_t)0x24e7dd4, + (q31_t)0x7ff5cdc3, (q31_t)0x241eee2, (q31_t)0x7ff63e01, (q31_t)0x2355fd9, + (q31_t)0x7ff6abc8, (q31_t)0x228d0bb, (q31_t)0x7ff71718, (q31_t)0x21c4188, + (q31_t)0x7ff77ff1, (q31_t)0x20fb240, (q31_t)0x7ff7e652, (q31_t)0x20322e3, + (q31_t)0x7ff84a3c, (q31_t)0x1f69373, (q31_t)0x7ff8abae, (q31_t)0x1ea03ef, + (q31_t)0x7ff90aaa, (q31_t)0x1dd7459, (q31_t)0x7ff9672d, (q31_t)0x1d0e4b0, + (q31_t)0x7ff9c13a, (q31_t)0x1c454f5, (q31_t)0x7ffa18cf, (q31_t)0x1b7c528, + (q31_t)0x7ffa6dec, (q31_t)0x1ab354b, (q31_t)0x7ffac092, (q31_t)0x19ea55d, + (q31_t)0x7ffb10c1, (q31_t)0x192155f, (q31_t)0x7ffb5e78, (q31_t)0x1858552, + (q31_t)0x7ffba9b8, (q31_t)0x178f536, (q31_t)0x7ffbf280, (q31_t)0x16c650b, + (q31_t)0x7ffc38d1, (q31_t)0x15fd4d2, (q31_t)0x7ffc7caa, (q31_t)0x153448c, + (q31_t)0x7ffcbe0c, (q31_t)0x146b438, (q31_t)0x7ffcfcf6, (q31_t)0x13a23d8, + (q31_t)0x7ffd3969, (q31_t)0x12d936c, (q31_t)0x7ffd7364, (q31_t)0x12102f4, + (q31_t)0x7ffdaae7, (q31_t)0x1147271, (q31_t)0x7ffddff3, (q31_t)0x107e1e3, + (q31_t)0x7ffe1288, (q31_t)0xfb514b, (q31_t)0x7ffe42a4, (q31_t)0xeec0aa, + (q31_t)0x7ffe704a, (q31_t)0xe22fff, (q31_t)0x7ffe9b77, (q31_t)0xd59f4c, + (q31_t)0x7ffec42d, (q31_t)0xc90e90, (q31_t)0x7ffeea6c, (q31_t)0xbc7dcc, + (q31_t)0x7fff0e32, (q31_t)0xafed02, (q31_t)0x7fff2f82, (q31_t)0xa35c30, + (q31_t)0x7fff4e59, (q31_t)0x96cb58, (q31_t)0x7fff6ab9, (q31_t)0x8a3a7b, + (q31_t)0x7fff84a1, (q31_t)0x7da998, (q31_t)0x7fff9c12, (q31_t)0x7118b0, + (q31_t)0x7fffb10b, (q31_t)0x6487c4, (q31_t)0x7fffc38c, (q31_t)0x57f6d4, + (q31_t)0x7fffd396, (q31_t)0x4b65e1, (q31_t)0x7fffe128, (q31_t)0x3ed4ea, + (q31_t)0x7fffec43, (q31_t)0x3243f1, (q31_t)0x7ffff4e6, (q31_t)0x25b2f7, + (q31_t)0x7ffffb11, (q31_t)0x1921fb, (q31_t)0x7ffffec4, (q31_t)0xc90fe, + (q31_t)0x7fffffff, (q31_t)0x0, (q31_t)0x7ffffec4, (q31_t)0xfff36f02, + (q31_t)0x7ffffb11, (q31_t)0xffe6de05, (q31_t)0x7ffff4e6, (q31_t)0xffda4d09, + (q31_t)0x7fffec43, (q31_t)0xffcdbc0f, (q31_t)0x7fffe128, (q31_t)0xffc12b16, + (q31_t)0x7fffd396, (q31_t)0xffb49a1f, (q31_t)0x7fffc38c, (q31_t)0xffa8092c, + (q31_t)0x7fffb10b, (q31_t)0xff9b783c, (q31_t)0x7fff9c12, (q31_t)0xff8ee750, + (q31_t)0x7fff84a1, (q31_t)0xff825668, (q31_t)0x7fff6ab9, (q31_t)0xff75c585, + (q31_t)0x7fff4e59, (q31_t)0xff6934a8, (q31_t)0x7fff2f82, (q31_t)0xff5ca3d0, + (q31_t)0x7fff0e32, (q31_t)0xff5012fe, (q31_t)0x7ffeea6c, (q31_t)0xff438234, + (q31_t)0x7ffec42d, (q31_t)0xff36f170, (q31_t)0x7ffe9b77, (q31_t)0xff2a60b4, + (q31_t)0x7ffe704a, (q31_t)0xff1dd001, (q31_t)0x7ffe42a4, (q31_t)0xff113f56, + (q31_t)0x7ffe1288, (q31_t)0xff04aeb5, (q31_t)0x7ffddff3, (q31_t)0xfef81e1d, + (q31_t)0x7ffdaae7, (q31_t)0xfeeb8d8f, (q31_t)0x7ffd7364, (q31_t)0xfedefd0c, + (q31_t)0x7ffd3969, (q31_t)0xfed26c94, (q31_t)0x7ffcfcf6, (q31_t)0xfec5dc28, + (q31_t)0x7ffcbe0c, (q31_t)0xfeb94bc8, (q31_t)0x7ffc7caa, (q31_t)0xfeacbb74, + (q31_t)0x7ffc38d1, (q31_t)0xfea02b2e, (q31_t)0x7ffbf280, (q31_t)0xfe939af5, + (q31_t)0x7ffba9b8, (q31_t)0xfe870aca, (q31_t)0x7ffb5e78, (q31_t)0xfe7a7aae, + (q31_t)0x7ffb10c1, (q31_t)0xfe6deaa1, (q31_t)0x7ffac092, (q31_t)0xfe615aa3, + (q31_t)0x7ffa6dec, (q31_t)0xfe54cab5, (q31_t)0x7ffa18cf, (q31_t)0xfe483ad8, + (q31_t)0x7ff9c13a, (q31_t)0xfe3bab0b, (q31_t)0x7ff9672d, (q31_t)0xfe2f1b50, + (q31_t)0x7ff90aaa, (q31_t)0xfe228ba7, (q31_t)0x7ff8abae, (q31_t)0xfe15fc11, + (q31_t)0x7ff84a3c, (q31_t)0xfe096c8d, (q31_t)0x7ff7e652, (q31_t)0xfdfcdd1d, + (q31_t)0x7ff77ff1, (q31_t)0xfdf04dc0, (q31_t)0x7ff71718, (q31_t)0xfde3be78, + (q31_t)0x7ff6abc8, (q31_t)0xfdd72f45, (q31_t)0x7ff63e01, (q31_t)0xfdcaa027, + (q31_t)0x7ff5cdc3, (q31_t)0xfdbe111e, (q31_t)0x7ff55b0d, (q31_t)0xfdb1822c, + (q31_t)0x7ff4e5e0, (q31_t)0xfda4f351, (q31_t)0x7ff46e3c, (q31_t)0xfd98648d, + (q31_t)0x7ff3f420, (q31_t)0xfd8bd5e1, (q31_t)0x7ff3778e, (q31_t)0xfd7f474d, + (q31_t)0x7ff2f884, (q31_t)0xfd72b8d2, (q31_t)0x7ff27703, (q31_t)0xfd662a70, + (q31_t)0x7ff1f30b, (q31_t)0xfd599c28, (q31_t)0x7ff16c9c, (q31_t)0xfd4d0df9, + (q31_t)0x7ff0e3b6, (q31_t)0xfd407fe6, (q31_t)0x7ff05858, (q31_t)0xfd33f1ed, + (q31_t)0x7fefca84, (q31_t)0xfd276410, (q31_t)0x7fef3a39, (q31_t)0xfd1ad650, + (q31_t)0x7feea776, (q31_t)0xfd0e48ab, (q31_t)0x7fee123d, (q31_t)0xfd01bb24, + (q31_t)0x7fed7a8c, (q31_t)0xfcf52dbb, (q31_t)0x7fece065, (q31_t)0xfce8a06f, + (q31_t)0x7fec43c7, (q31_t)0xfcdc1342, (q31_t)0x7feba4b2, (q31_t)0xfccf8634, + (q31_t)0x7feb0326, (q31_t)0xfcc2f945, (q31_t)0x7fea5f23, (q31_t)0xfcb66c77, + (q31_t)0x7fe9b8a9, (q31_t)0xfca9dfc8, (q31_t)0x7fe90fb9, (q31_t)0xfc9d533b, + (q31_t)0x7fe86452, (q31_t)0xfc90c6cf, (q31_t)0x7fe7b674, (q31_t)0xfc843a85, + (q31_t)0x7fe7061f, (q31_t)0xfc77ae5e, (q31_t)0x7fe65354, (q31_t)0xfc6b2259, + (q31_t)0x7fe59e12, (q31_t)0xfc5e9678, (q31_t)0x7fe4e659, (q31_t)0xfc520aba, + (q31_t)0x7fe42c2a, (q31_t)0xfc457f21, (q31_t)0x7fe36f84, (q31_t)0xfc38f3ac, + (q31_t)0x7fe2b067, (q31_t)0xfc2c685d, (q31_t)0x7fe1eed5, (q31_t)0xfc1fdd34, + (q31_t)0x7fe12acb, (q31_t)0xfc135231, (q31_t)0x7fe0644b, (q31_t)0xfc06c754, + (q31_t)0x7fdf9b55, (q31_t)0xfbfa3c9f, (q31_t)0x7fdecfe8, (q31_t)0xfbedb212, + (q31_t)0x7fde0205, (q31_t)0xfbe127ac, (q31_t)0x7fdd31ac, (q31_t)0xfbd49d70, + (q31_t)0x7fdc5edc, (q31_t)0xfbc8135c, (q31_t)0x7fdb8996, (q31_t)0xfbbb8973, + (q31_t)0x7fdab1d9, (q31_t)0xfbaeffb3, (q31_t)0x7fd9d7a7, (q31_t)0xfba2761e, + (q31_t)0x7fd8fafe, (q31_t)0xfb95ecb4, (q31_t)0x7fd81bdf, (q31_t)0xfb896375, + (q31_t)0x7fd73a4a, (q31_t)0xfb7cda63, (q31_t)0x7fd6563f, (q31_t)0xfb70517d, + (q31_t)0x7fd56fbe, (q31_t)0xfb63c8c4, (q31_t)0x7fd486c7, (q31_t)0xfb574039, + (q31_t)0x7fd39b5a, (q31_t)0xfb4ab7db, (q31_t)0x7fd2ad77, (q31_t)0xfb3e2fac, + (q31_t)0x7fd1bd1e, (q31_t)0xfb31a7ac, (q31_t)0x7fd0ca4f, (q31_t)0xfb251fdc, + (q31_t)0x7fcfd50b, (q31_t)0xfb18983b, (q31_t)0x7fcedd50, (q31_t)0xfb0c10cb, + (q31_t)0x7fcde320, (q31_t)0xfaff898c, (q31_t)0x7fcce67a, (q31_t)0xfaf3027e, + (q31_t)0x7fcbe75e, (q31_t)0xfae67ba2, (q31_t)0x7fcae5cd, (q31_t)0xfad9f4f8, + (q31_t)0x7fc9e1c6, (q31_t)0xfacd6e81, (q31_t)0x7fc8db4a, (q31_t)0xfac0e83d, + (q31_t)0x7fc7d258, (q31_t)0xfab4622d, (q31_t)0x7fc6c6f0, (q31_t)0xfaa7dc52, + (q31_t)0x7fc5b913, (q31_t)0xfa9b56ab, (q31_t)0x7fc4a8c1, (q31_t)0xfa8ed139, + (q31_t)0x7fc395f9, (q31_t)0xfa824bfd, (q31_t)0x7fc280bc, (q31_t)0xfa75c6f8, + (q31_t)0x7fc1690a, (q31_t)0xfa694229, (q31_t)0x7fc04ee3, (q31_t)0xfa5cbd91, + (q31_t)0x7fbf3246, (q31_t)0xfa503930, (q31_t)0x7fbe1334, (q31_t)0xfa43b508, + (q31_t)0x7fbcf1ad, (q31_t)0xfa373119, (q31_t)0x7fbbcdb1, (q31_t)0xfa2aad62, + (q31_t)0x7fbaa740, (q31_t)0xfa1e29e5, (q31_t)0x7fb97e5a, (q31_t)0xfa11a6a3, + (q31_t)0x7fb852ff, (q31_t)0xfa05239a, (q31_t)0x7fb7252f, (q31_t)0xf9f8a0cd, + (q31_t)0x7fb5f4ea, (q31_t)0xf9ec1e3b, (q31_t)0x7fb4c231, (q31_t)0xf9df9be6, + (q31_t)0x7fb38d02, (q31_t)0xf9d319cc, (q31_t)0x7fb2555f, (q31_t)0xf9c697f0, + (q31_t)0x7fb11b48, (q31_t)0xf9ba1651, (q31_t)0x7fafdebb, (q31_t)0xf9ad94f0, + (q31_t)0x7fae9fbb, (q31_t)0xf9a113cd, (q31_t)0x7fad5e45, (q31_t)0xf99492ea, + (q31_t)0x7fac1a5b, (q31_t)0xf9881245, (q31_t)0x7faad3fd, (q31_t)0xf97b91e1, + (q31_t)0x7fa98b2a, (q31_t)0xf96f11bc, (q31_t)0x7fa83fe3, (q31_t)0xf96291d9, + (q31_t)0x7fa6f228, (q31_t)0xf9561237, (q31_t)0x7fa5a1f9, (q31_t)0xf94992d7, + (q31_t)0x7fa44f55, (q31_t)0xf93d13b8, (q31_t)0x7fa2fa3d, (q31_t)0xf93094dd, + (q31_t)0x7fa1a2b2, (q31_t)0xf9241645, (q31_t)0x7fa048b2, (q31_t)0xf91797f0, + (q31_t)0x7f9eec3e, (q31_t)0xf90b19e0, (q31_t)0x7f9d8d56, (q31_t)0xf8fe9c15, + (q31_t)0x7f9c2bfb, (q31_t)0xf8f21e8e, (q31_t)0x7f9ac82c, (q31_t)0xf8e5a14d, + (q31_t)0x7f9961e8, (q31_t)0xf8d92452, (q31_t)0x7f97f932, (q31_t)0xf8cca79e, + (q31_t)0x7f968e07, (q31_t)0xf8c02b31, (q31_t)0x7f952069, (q31_t)0xf8b3af0c, + (q31_t)0x7f93b058, (q31_t)0xf8a7332e, (q31_t)0x7f923dd2, (q31_t)0xf89ab799, + (q31_t)0x7f90c8da, (q31_t)0xf88e3c4d, (q31_t)0x7f8f516e, (q31_t)0xf881c14b, + (q31_t)0x7f8dd78f, (q31_t)0xf8754692, (q31_t)0x7f8c5b3d, (q31_t)0xf868cc24, + (q31_t)0x7f8adc77, (q31_t)0xf85c5201, (q31_t)0x7f895b3e, (q31_t)0xf84fd829, + (q31_t)0x7f87d792, (q31_t)0xf8435e9d, (q31_t)0x7f865174, (q31_t)0xf836e55d, + (q31_t)0x7f84c8e2, (q31_t)0xf82a6c6a, (q31_t)0x7f833ddd, (q31_t)0xf81df3c5, + (q31_t)0x7f81b065, (q31_t)0xf8117b6d, (q31_t)0x7f80207b, (q31_t)0xf8050364, + (q31_t)0x7f7e8e1e, (q31_t)0xf7f88ba9, (q31_t)0x7f7cf94e, (q31_t)0xf7ec143e, + (q31_t)0x7f7b620c, (q31_t)0xf7df9d22, (q31_t)0x7f79c857, (q31_t)0xf7d32657, + (q31_t)0x7f782c30, (q31_t)0xf7c6afdc, (q31_t)0x7f768d96, (q31_t)0xf7ba39b3, + (q31_t)0x7f74ec8a, (q31_t)0xf7adc3db, (q31_t)0x7f73490b, (q31_t)0xf7a14e55, + (q31_t)0x7f71a31b, (q31_t)0xf794d922, (q31_t)0x7f6ffab8, (q31_t)0xf7886442, + (q31_t)0x7f6e4fe3, (q31_t)0xf77befb5, (q31_t)0x7f6ca29c, (q31_t)0xf76f7b7d, + (q31_t)0x7f6af2e3, (q31_t)0xf7630799, (q31_t)0x7f6940b8, (q31_t)0xf756940a, + (q31_t)0x7f678c1c, (q31_t)0xf74a20d0, (q31_t)0x7f65d50d, (q31_t)0xf73daded, + (q31_t)0x7f641b8d, (q31_t)0xf7313b60, (q31_t)0x7f625f9b, (q31_t)0xf724c92a, + (q31_t)0x7f60a138, (q31_t)0xf718574b, (q31_t)0x7f5ee063, (q31_t)0xf70be5c4, + (q31_t)0x7f5d1d1d, (q31_t)0xf6ff7496, (q31_t)0x7f5b5765, (q31_t)0xf6f303c0, + (q31_t)0x7f598f3c, (q31_t)0xf6e69344, (q31_t)0x7f57c4a2, (q31_t)0xf6da2321, + (q31_t)0x7f55f796, (q31_t)0xf6cdb359, (q31_t)0x7f54281a, (q31_t)0xf6c143ec, + (q31_t)0x7f52562c, (q31_t)0xf6b4d4d9, (q31_t)0x7f5081cd, (q31_t)0xf6a86623, + (q31_t)0x7f4eaafe, (q31_t)0xf69bf7c9, (q31_t)0x7f4cd1be, (q31_t)0xf68f89cb, + (q31_t)0x7f4af60d, (q31_t)0xf6831c2b, (q31_t)0x7f4917eb, (q31_t)0xf676aee8, + (q31_t)0x7f473759, (q31_t)0xf66a4203, (q31_t)0x7f455456, (q31_t)0xf65dd57d, + (q31_t)0x7f436ee3, (q31_t)0xf6516956, (q31_t)0x7f4186ff, (q31_t)0xf644fd8f, + (q31_t)0x7f3f9cab, (q31_t)0xf6389228, (q31_t)0x7f3dafe7, (q31_t)0xf62c2721, + (q31_t)0x7f3bc0b3, (q31_t)0xf61fbc7b, (q31_t)0x7f39cf0e, (q31_t)0xf6135237, + (q31_t)0x7f37dafa, (q31_t)0xf606e854, (q31_t)0x7f35e476, (q31_t)0xf5fa7ed4, + (q31_t)0x7f33eb81, (q31_t)0xf5ee15b7, (q31_t)0x7f31f01d, (q31_t)0xf5e1acfd, + (q31_t)0x7f2ff24a, (q31_t)0xf5d544a7, (q31_t)0x7f2df206, (q31_t)0xf5c8dcb6, + (q31_t)0x7f2bef53, (q31_t)0xf5bc7529, (q31_t)0x7f29ea31, (q31_t)0xf5b00e02, + (q31_t)0x7f27e29f, (q31_t)0xf5a3a740, (q31_t)0x7f25d89e, (q31_t)0xf59740e5, + (q31_t)0x7f23cc2e, (q31_t)0xf58adaf0, (q31_t)0x7f21bd4e, (q31_t)0xf57e7563, + (q31_t)0x7f1fabff, (q31_t)0xf572103d, (q31_t)0x7f1d9842, (q31_t)0xf565ab80, + (q31_t)0x7f1b8215, (q31_t)0xf559472b, (q31_t)0x7f19697a, (q31_t)0xf54ce33f, + (q31_t)0x7f174e70, (q31_t)0xf5407fbd, (q31_t)0x7f1530f7, (q31_t)0xf5341ca5, + (q31_t)0x7f13110f, (q31_t)0xf527b9f7, (q31_t)0x7f10eeb9, (q31_t)0xf51b57b5, + (q31_t)0x7f0ec9f5, (q31_t)0xf50ef5de, (q31_t)0x7f0ca2c2, (q31_t)0xf5029473, + (q31_t)0x7f0a7921, (q31_t)0xf4f63374, (q31_t)0x7f084d12, (q31_t)0xf4e9d2e3, + (q31_t)0x7f061e95, (q31_t)0xf4dd72be, (q31_t)0x7f03eda9, (q31_t)0xf4d11308, + (q31_t)0x7f01ba50, (q31_t)0xf4c4b3c0, (q31_t)0x7eff8489, (q31_t)0xf4b854e7, + (q31_t)0x7efd4c54, (q31_t)0xf4abf67e, (q31_t)0x7efb11b1, (q31_t)0xf49f9884, + (q31_t)0x7ef8d4a1, (q31_t)0xf4933afa, (q31_t)0x7ef69523, (q31_t)0xf486dde1, + (q31_t)0x7ef45338, (q31_t)0xf47a8139, (q31_t)0x7ef20ee0, (q31_t)0xf46e2504, + (q31_t)0x7eefc81a, (q31_t)0xf461c940, (q31_t)0x7eed7ee7, (q31_t)0xf4556def, + (q31_t)0x7eeb3347, (q31_t)0xf4491311, (q31_t)0x7ee8e53a, (q31_t)0xf43cb8a7, + (q31_t)0x7ee694c1, (q31_t)0xf4305eb0, (q31_t)0x7ee441da, (q31_t)0xf424052f, + (q31_t)0x7ee1ec87, (q31_t)0xf417ac22, (q31_t)0x7edf94c7, (q31_t)0xf40b538b, + (q31_t)0x7edd3a9a, (q31_t)0xf3fefb6a, (q31_t)0x7edade01, (q31_t)0xf3f2a3bf, + (q31_t)0x7ed87efc, (q31_t)0xf3e64c8c, (q31_t)0x7ed61d8a, (q31_t)0xf3d9f5cf, + (q31_t)0x7ed3b9ad, (q31_t)0xf3cd9f8b, (q31_t)0x7ed15363, (q31_t)0xf3c149bf, + (q31_t)0x7eceeaad, (q31_t)0xf3b4f46c, (q31_t)0x7ecc7f8b, (q31_t)0xf3a89f92, + (q31_t)0x7eca11fe, (q31_t)0xf39c4b32, (q31_t)0x7ec7a205, (q31_t)0xf38ff74d, + (q31_t)0x7ec52fa0, (q31_t)0xf383a3e2, (q31_t)0x7ec2bad0, (q31_t)0xf37750f2, + (q31_t)0x7ec04394, (q31_t)0xf36afe7e, (q31_t)0x7ebdc9ed, (q31_t)0xf35eac86, + (q31_t)0x7ebb4ddb, (q31_t)0xf3525b0b, (q31_t)0x7eb8cf5d, (q31_t)0xf3460a0d, + (q31_t)0x7eb64e75, (q31_t)0xf339b98d, (q31_t)0x7eb3cb21, (q31_t)0xf32d698a, + (q31_t)0x7eb14563, (q31_t)0xf3211a07, (q31_t)0x7eaebd3a, (q31_t)0xf314cb02, + (q31_t)0x7eac32a6, (q31_t)0xf3087c7d, (q31_t)0x7ea9a5a8, (q31_t)0xf2fc2e77, + (q31_t)0x7ea7163f, (q31_t)0xf2efe0f2, (q31_t)0x7ea4846c, (q31_t)0xf2e393ef, + (q31_t)0x7ea1f02f, (q31_t)0xf2d7476c, (q31_t)0x7e9f5988, (q31_t)0xf2cafb6b, + (q31_t)0x7e9cc076, (q31_t)0xf2beafed, (q31_t)0x7e9a24fb, (q31_t)0xf2b264f2, + (q31_t)0x7e978715, (q31_t)0xf2a61a7a, (q31_t)0x7e94e6c6, (q31_t)0xf299d085, + (q31_t)0x7e92440d, (q31_t)0xf28d8715, (q31_t)0x7e8f9eeb, (q31_t)0xf2813e2a, + (q31_t)0x7e8cf75f, (q31_t)0xf274f5c3, (q31_t)0x7e8a4d6a, (q31_t)0xf268ade3, + (q31_t)0x7e87a10c, (q31_t)0xf25c6688, (q31_t)0x7e84f245, (q31_t)0xf2501fb5, + (q31_t)0x7e824114, (q31_t)0xf243d968, (q31_t)0x7e7f8d7b, (q31_t)0xf23793a3, + (q31_t)0x7e7cd778, (q31_t)0xf22b4e66, (q31_t)0x7e7a1f0d, (q31_t)0xf21f09b1, + (q31_t)0x7e77643a, (q31_t)0xf212c585, (q31_t)0x7e74a6fd, (q31_t)0xf20681e3, + (q31_t)0x7e71e759, (q31_t)0xf1fa3ecb, (q31_t)0x7e6f254c, (q31_t)0xf1edfc3d, + (q31_t)0x7e6c60d7, (q31_t)0xf1e1ba3a, (q31_t)0x7e6999fa, (q31_t)0xf1d578c2, + (q31_t)0x7e66d0b4, (q31_t)0xf1c937d6, (q31_t)0x7e640507, (q31_t)0xf1bcf777, + (q31_t)0x7e6136f3, (q31_t)0xf1b0b7a4, (q31_t)0x7e5e6676, (q31_t)0xf1a4785e, + (q31_t)0x7e5b9392, (q31_t)0xf19839a6, (q31_t)0x7e58be47, (q31_t)0xf18bfb7d, + (q31_t)0x7e55e694, (q31_t)0xf17fbde2, (q31_t)0x7e530c7a, (q31_t)0xf17380d6, + (q31_t)0x7e502ff9, (q31_t)0xf1674459, (q31_t)0x7e4d5110, (q31_t)0xf15b086d, + (q31_t)0x7e4a6fc1, (q31_t)0xf14ecd11, (q31_t)0x7e478c0b, (q31_t)0xf1429247, + (q31_t)0x7e44a5ef, (q31_t)0xf136580d, (q31_t)0x7e41bd6c, (q31_t)0xf12a1e66, + (q31_t)0x7e3ed282, (q31_t)0xf11de551, (q31_t)0x7e3be532, (q31_t)0xf111accf, + (q31_t)0x7e38f57c, (q31_t)0xf10574e0, (q31_t)0x7e360360, (q31_t)0xf0f93d86, + (q31_t)0x7e330ede, (q31_t)0xf0ed06bf, (q31_t)0x7e3017f6, (q31_t)0xf0e0d08d, + (q31_t)0x7e2d1ea8, (q31_t)0xf0d49af1, (q31_t)0x7e2a22f4, (q31_t)0xf0c865ea, + (q31_t)0x7e2724db, (q31_t)0xf0bc317a, (q31_t)0x7e24245d, (q31_t)0xf0affda0, + (q31_t)0x7e212179, (q31_t)0xf0a3ca5d, (q31_t)0x7e1e1c30, (q31_t)0xf09797b2, + (q31_t)0x7e1b1482, (q31_t)0xf08b659f, (q31_t)0x7e180a6f, (q31_t)0xf07f3424, + (q31_t)0x7e14fdf7, (q31_t)0xf0730342, (q31_t)0x7e11ef1b, (q31_t)0xf066d2fa, + (q31_t)0x7e0eddd9, (q31_t)0xf05aa34c, (q31_t)0x7e0bca34, (q31_t)0xf04e7438, + (q31_t)0x7e08b42a, (q31_t)0xf04245c0, (q31_t)0x7e059bbb, (q31_t)0xf03617e2, + (q31_t)0x7e0280e9, (q31_t)0xf029eaa1, (q31_t)0x7dff63b2, (q31_t)0xf01dbdfb, + (q31_t)0x7dfc4418, (q31_t)0xf01191f3, (q31_t)0x7df9221a, (q31_t)0xf0056687, + (q31_t)0x7df5fdb8, (q31_t)0xeff93bba, (q31_t)0x7df2d6f3, (q31_t)0xefed118a, + (q31_t)0x7defadca, (q31_t)0xefe0e7f9, (q31_t)0x7dec823e, (q31_t)0xefd4bf08, + (q31_t)0x7de9544f, (q31_t)0xefc896b5, (q31_t)0x7de623fd, (q31_t)0xefbc6f03, + (q31_t)0x7de2f148, (q31_t)0xefb047f2, (q31_t)0x7ddfbc30, (q31_t)0xefa42181, + (q31_t)0x7ddc84b5, (q31_t)0xef97fbb2, (q31_t)0x7dd94ad8, (q31_t)0xef8bd685, + (q31_t)0x7dd60e99, (q31_t)0xef7fb1fa, (q31_t)0x7dd2cff7, (q31_t)0xef738e12, + (q31_t)0x7dcf8ef3, (q31_t)0xef676ace, (q31_t)0x7dcc4b8d, (q31_t)0xef5b482d, + (q31_t)0x7dc905c5, (q31_t)0xef4f2630, (q31_t)0x7dc5bd9b, (q31_t)0xef4304d8, + (q31_t)0x7dc2730f, (q31_t)0xef36e426, (q31_t)0x7dbf2622, (q31_t)0xef2ac419, + (q31_t)0x7dbbd6d4, (q31_t)0xef1ea4b2, (q31_t)0x7db88524, (q31_t)0xef1285f2, + (q31_t)0x7db53113, (q31_t)0xef0667d9, (q31_t)0x7db1daa2, (q31_t)0xeefa4a67, + (q31_t)0x7dae81cf, (q31_t)0xeeee2d9d, (q31_t)0x7dab269b, (q31_t)0xeee2117c, + (q31_t)0x7da7c907, (q31_t)0xeed5f604, (q31_t)0x7da46912, (q31_t)0xeec9db35, + (q31_t)0x7da106bd, (q31_t)0xeebdc110, (q31_t)0x7d9da208, (q31_t)0xeeb1a796, + (q31_t)0x7d9a3af2, (q31_t)0xeea58ec6, (q31_t)0x7d96d17d, (q31_t)0xee9976a1, + (q31_t)0x7d9365a8, (q31_t)0xee8d5f29, (q31_t)0x7d8ff772, (q31_t)0xee81485c, + (q31_t)0x7d8c86de, (q31_t)0xee75323c, (q31_t)0x7d8913ea, (q31_t)0xee691cc9, + (q31_t)0x7d859e96, (q31_t)0xee5d0804, (q31_t)0x7d8226e4, (q31_t)0xee50f3ed, + (q31_t)0x7d7eacd2, (q31_t)0xee44e084, (q31_t)0x7d7b3061, (q31_t)0xee38cdcb, + (q31_t)0x7d77b192, (q31_t)0xee2cbbc1, (q31_t)0x7d743064, (q31_t)0xee20aa67, + (q31_t)0x7d70acd7, (q31_t)0xee1499bd, (q31_t)0x7d6d26ec, (q31_t)0xee0889c4, + (q31_t)0x7d699ea3, (q31_t)0xedfc7a7c, (q31_t)0x7d6613fb, (q31_t)0xedf06be6, + (q31_t)0x7d6286f6, (q31_t)0xede45e03, (q31_t)0x7d5ef793, (q31_t)0xedd850d2, + (q31_t)0x7d5b65d2, (q31_t)0xedcc4454, (q31_t)0x7d57d1b3, (q31_t)0xedc0388a, + (q31_t)0x7d543b37, (q31_t)0xedb42d74, (q31_t)0x7d50a25e, (q31_t)0xeda82313, + (q31_t)0x7d4d0728, (q31_t)0xed9c1967, (q31_t)0x7d496994, (q31_t)0xed901070, + (q31_t)0x7d45c9a4, (q31_t)0xed84082f, (q31_t)0x7d422757, (q31_t)0xed7800a5, + (q31_t)0x7d3e82ae, (q31_t)0xed6bf9d1, (q31_t)0x7d3adba7, (q31_t)0xed5ff3b5, + (q31_t)0x7d373245, (q31_t)0xed53ee51, (q31_t)0x7d338687, (q31_t)0xed47e9a5, + (q31_t)0x7d2fd86c, (q31_t)0xed3be5b1, (q31_t)0x7d2c27f6, (q31_t)0xed2fe277, + (q31_t)0x7d287523, (q31_t)0xed23dff7, (q31_t)0x7d24bff6, (q31_t)0xed17de31, + (q31_t)0x7d21086c, (q31_t)0xed0bdd25, (q31_t)0x7d1d4e88, (q31_t)0xecffdcd4, + (q31_t)0x7d199248, (q31_t)0xecf3dd3f, (q31_t)0x7d15d3ad, (q31_t)0xece7de66, + (q31_t)0x7d1212b7, (q31_t)0xecdbe04a, (q31_t)0x7d0e4f67, (q31_t)0xeccfe2ea, + (q31_t)0x7d0a89bc, (q31_t)0xecc3e648, (q31_t)0x7d06c1b6, (q31_t)0xecb7ea63, + (q31_t)0x7d02f757, (q31_t)0xecabef3d, (q31_t)0x7cff2a9d, (q31_t)0xec9ff4d6, + (q31_t)0x7cfb5b89, (q31_t)0xec93fb2e, (q31_t)0x7cf78a1b, (q31_t)0xec880245, + (q31_t)0x7cf3b653, (q31_t)0xec7c0a1d, (q31_t)0x7cefe032, (q31_t)0xec7012b5, + (q31_t)0x7cec07b8, (q31_t)0xec641c0e, (q31_t)0x7ce82ce4, (q31_t)0xec582629, + (q31_t)0x7ce44fb7, (q31_t)0xec4c3106, (q31_t)0x7ce07031, (q31_t)0xec403ca5, + (q31_t)0x7cdc8e52, (q31_t)0xec344908, (q31_t)0x7cd8aa1b, (q31_t)0xec28562d, + (q31_t)0x7cd4c38b, (q31_t)0xec1c6417, (q31_t)0x7cd0daa2, (q31_t)0xec1072c4, + (q31_t)0x7cccef62, (q31_t)0xec048237, (q31_t)0x7cc901c9, (q31_t)0xebf8926f, + (q31_t)0x7cc511d9, (q31_t)0xebeca36c, (q31_t)0x7cc11f90, (q31_t)0xebe0b52f, + (q31_t)0x7cbd2af0, (q31_t)0xebd4c7ba, (q31_t)0x7cb933f9, (q31_t)0xebc8db0b, + (q31_t)0x7cb53aaa, (q31_t)0xebbcef23, (q31_t)0x7cb13f04, (q31_t)0xebb10404, + (q31_t)0x7cad4107, (q31_t)0xeba519ad, (q31_t)0x7ca940b3, (q31_t)0xeb99301f, + (q31_t)0x7ca53e09, (q31_t)0xeb8d475b, (q31_t)0x7ca13908, (q31_t)0xeb815f60, + (q31_t)0x7c9d31b0, (q31_t)0xeb75782f, (q31_t)0x7c992803, (q31_t)0xeb6991ca, + (q31_t)0x7c951bff, (q31_t)0xeb5dac2f, (q31_t)0x7c910da5, (q31_t)0xeb51c760, + (q31_t)0x7c8cfcf6, (q31_t)0xeb45e35d, (q31_t)0x7c88e9f1, (q31_t)0xeb3a0027, + (q31_t)0x7c84d496, (q31_t)0xeb2e1dbe, (q31_t)0x7c80bce7, (q31_t)0xeb223c22, + (q31_t)0x7c7ca2e2, (q31_t)0xeb165b54, (q31_t)0x7c788688, (q31_t)0xeb0a7b54, + (q31_t)0x7c7467d9, (q31_t)0xeafe9c24, (q31_t)0x7c7046d6, (q31_t)0xeaf2bdc3, + (q31_t)0x7c6c237e, (q31_t)0xeae6e031, (q31_t)0x7c67fdd1, (q31_t)0xeadb0370, + (q31_t)0x7c63d5d1, (q31_t)0xeacf277f, (q31_t)0x7c5fab7c, (q31_t)0xeac34c60, + (q31_t)0x7c5b7ed4, (q31_t)0xeab77212, (q31_t)0x7c574fd8, (q31_t)0xeaab9896, + (q31_t)0x7c531e88, (q31_t)0xea9fbfed, (q31_t)0x7c4eeae5, (q31_t)0xea93e817, + (q31_t)0x7c4ab4ef, (q31_t)0xea881114, (q31_t)0x7c467ca6, (q31_t)0xea7c3ae5, + (q31_t)0x7c42420a, (q31_t)0xea70658a, (q31_t)0x7c3e051b, (q31_t)0xea649105, + (q31_t)0x7c39c5da, (q31_t)0xea58bd54, (q31_t)0x7c358446, (q31_t)0xea4cea79, + (q31_t)0x7c314060, (q31_t)0xea411874, (q31_t)0x7c2cfa28, (q31_t)0xea354746, + (q31_t)0x7c28b19e, (q31_t)0xea2976ef, (q31_t)0x7c2466c2, (q31_t)0xea1da770, + (q31_t)0x7c201994, (q31_t)0xea11d8c8, (q31_t)0x7c1bca16, (q31_t)0xea060af9, + (q31_t)0x7c177845, (q31_t)0xe9fa3e03, (q31_t)0x7c132424, (q31_t)0xe9ee71e6, + (q31_t)0x7c0ecdb2, (q31_t)0xe9e2a6a3, (q31_t)0x7c0a74f0, (q31_t)0xe9d6dc3b, + (q31_t)0x7c0619dc, (q31_t)0xe9cb12ad, (q31_t)0x7c01bc78, (q31_t)0xe9bf49fa, + (q31_t)0x7bfd5cc4, (q31_t)0xe9b38223, (q31_t)0x7bf8fac0, (q31_t)0xe9a7bb28, + (q31_t)0x7bf4966c, (q31_t)0xe99bf509, (q31_t)0x7bf02fc9, (q31_t)0xe9902fc7, + (q31_t)0x7bebc6d5, (q31_t)0xe9846b63, (q31_t)0x7be75b93, (q31_t)0xe978a7dd, + (q31_t)0x7be2ee01, (q31_t)0xe96ce535, (q31_t)0x7bde7e20, (q31_t)0xe961236c, + (q31_t)0x7bda0bf0, (q31_t)0xe9556282, (q31_t)0x7bd59771, (q31_t)0xe949a278, + (q31_t)0x7bd120a4, (q31_t)0xe93de34e, (q31_t)0x7bcca789, (q31_t)0xe9322505, + (q31_t)0x7bc82c1f, (q31_t)0xe926679c, (q31_t)0x7bc3ae67, (q31_t)0xe91aab16, + (q31_t)0x7bbf2e62, (q31_t)0xe90eef71, (q31_t)0x7bbaac0e, (q31_t)0xe90334af, + (q31_t)0x7bb6276e, (q31_t)0xe8f77acf, (q31_t)0x7bb1a080, (q31_t)0xe8ebc1d3, + (q31_t)0x7bad1744, (q31_t)0xe8e009ba, (q31_t)0x7ba88bbc, (q31_t)0xe8d45286, + (q31_t)0x7ba3fde7, (q31_t)0xe8c89c37, (q31_t)0x7b9f6dc5, (q31_t)0xe8bce6cd, + (q31_t)0x7b9adb57, (q31_t)0xe8b13248, (q31_t)0x7b96469d, (q31_t)0xe8a57ea9, + (q31_t)0x7b91af97, (q31_t)0xe899cbf1, (q31_t)0x7b8d1644, (q31_t)0xe88e1a20, + (q31_t)0x7b887aa6, (q31_t)0xe8826936, (q31_t)0x7b83dcbc, (q31_t)0xe876b934, + (q31_t)0x7b7f3c87, (q31_t)0xe86b0a1a, (q31_t)0x7b7a9a07, (q31_t)0xe85f5be9, + (q31_t)0x7b75f53c, (q31_t)0xe853aea1, (q31_t)0x7b714e25, (q31_t)0xe8480243, + (q31_t)0x7b6ca4c4, (q31_t)0xe83c56cf, (q31_t)0x7b67f919, (q31_t)0xe830ac45, + (q31_t)0x7b634b23, (q31_t)0xe82502a7, (q31_t)0x7b5e9ae4, (q31_t)0xe81959f4, + (q31_t)0x7b59e85a, (q31_t)0xe80db22d, (q31_t)0x7b553386, (q31_t)0xe8020b52, + (q31_t)0x7b507c69, (q31_t)0xe7f66564, (q31_t)0x7b4bc303, (q31_t)0xe7eac063, + (q31_t)0x7b470753, (q31_t)0xe7df1c50, (q31_t)0x7b42495a, (q31_t)0xe7d3792b, + (q31_t)0x7b3d8918, (q31_t)0xe7c7d6f4, (q31_t)0x7b38c68e, (q31_t)0xe7bc35ad, + (q31_t)0x7b3401bb, (q31_t)0xe7b09555, (q31_t)0x7b2f3aa0, (q31_t)0xe7a4f5ed, + (q31_t)0x7b2a713d, (q31_t)0xe7995776, (q31_t)0x7b25a591, (q31_t)0xe78db9ef, + (q31_t)0x7b20d79e, (q31_t)0xe7821d59, (q31_t)0x7b1c0764, (q31_t)0xe77681b6, + (q31_t)0x7b1734e2, (q31_t)0xe76ae704, (q31_t)0x7b126019, (q31_t)0xe75f4d45, + (q31_t)0x7b0d8909, (q31_t)0xe753b479, (q31_t)0x7b08afb2, (q31_t)0xe7481ca1, + (q31_t)0x7b03d414, (q31_t)0xe73c85bc, (q31_t)0x7afef630, (q31_t)0xe730efcc, + (q31_t)0x7afa1605, (q31_t)0xe7255ad1, (q31_t)0x7af53395, (q31_t)0xe719c6cb, + (q31_t)0x7af04edf, (q31_t)0xe70e33bb, (q31_t)0x7aeb67e3, (q31_t)0xe702a1a1, + (q31_t)0x7ae67ea1, (q31_t)0xe6f7107e, (q31_t)0x7ae1931a, (q31_t)0xe6eb8052, + (q31_t)0x7adca54e, (q31_t)0xe6dff11d, (q31_t)0x7ad7b53d, (q31_t)0xe6d462e1, + (q31_t)0x7ad2c2e8, (q31_t)0xe6c8d59c, (q31_t)0x7acdce4d, (q31_t)0xe6bd4951, + (q31_t)0x7ac8d76f, (q31_t)0xe6b1bdff, (q31_t)0x7ac3de4c, (q31_t)0xe6a633a6, + (q31_t)0x7abee2e5, (q31_t)0xe69aaa48, (q31_t)0x7ab9e53a, (q31_t)0xe68f21e5, + (q31_t)0x7ab4e54c, (q31_t)0xe6839a7c, (q31_t)0x7aafe31b, (q31_t)0xe6781410, + (q31_t)0x7aaadea6, (q31_t)0xe66c8e9f, (q31_t)0x7aa5d7ee, (q31_t)0xe6610a2a, + (q31_t)0x7aa0cef3, (q31_t)0xe65586b3, (q31_t)0x7a9bc3b6, (q31_t)0xe64a0438, + (q31_t)0x7a96b636, (q31_t)0xe63e82bc, (q31_t)0x7a91a674, (q31_t)0xe633023e, + (q31_t)0x7a8c9470, (q31_t)0xe62782be, (q31_t)0x7a87802a, (q31_t)0xe61c043d, + (q31_t)0x7a8269a3, (q31_t)0xe61086bc, (q31_t)0x7a7d50da, (q31_t)0xe6050a3b, + (q31_t)0x7a7835cf, (q31_t)0xe5f98ebb, (q31_t)0x7a731884, (q31_t)0xe5ee143b, + (q31_t)0x7a6df8f8, (q31_t)0xe5e29abc, (q31_t)0x7a68d72b, (q31_t)0xe5d72240, + (q31_t)0x7a63b31d, (q31_t)0xe5cbaac5, (q31_t)0x7a5e8cd0, (q31_t)0xe5c0344d, + (q31_t)0x7a596442, (q31_t)0xe5b4bed8, (q31_t)0x7a543974, (q31_t)0xe5a94a67, + (q31_t)0x7a4f0c67, (q31_t)0xe59dd6f9, (q31_t)0x7a49dd1a, (q31_t)0xe5926490, + (q31_t)0x7a44ab8e, (q31_t)0xe586f32c, (q31_t)0x7a3f77c3, (q31_t)0xe57b82cd, + (q31_t)0x7a3a41b9, (q31_t)0xe5701374, (q31_t)0x7a350970, (q31_t)0xe564a521, + (q31_t)0x7a2fcee8, (q31_t)0xe55937d5, (q31_t)0x7a2a9223, (q31_t)0xe54dcb8f, + (q31_t)0x7a25531f, (q31_t)0xe5426051, (q31_t)0x7a2011de, (q31_t)0xe536f61b, + (q31_t)0x7a1ace5f, (q31_t)0xe52b8cee, (q31_t)0x7a1588a2, (q31_t)0xe52024c9, + (q31_t)0x7a1040a8, (q31_t)0xe514bdad, (q31_t)0x7a0af671, (q31_t)0xe509579b, + (q31_t)0x7a05a9fd, (q31_t)0xe4fdf294, (q31_t)0x7a005b4d, (q31_t)0xe4f28e96, + (q31_t)0x79fb0a60, (q31_t)0xe4e72ba4, (q31_t)0x79f5b737, (q31_t)0xe4dbc9bd, + (q31_t)0x79f061d2, (q31_t)0xe4d068e2, (q31_t)0x79eb0a31, (q31_t)0xe4c50914, + (q31_t)0x79e5b054, (q31_t)0xe4b9aa52, (q31_t)0x79e0543c, (q31_t)0xe4ae4c9d, + (q31_t)0x79daf5e8, (q31_t)0xe4a2eff6, (q31_t)0x79d5955a, (q31_t)0xe497945d, + (q31_t)0x79d03291, (q31_t)0xe48c39d3, (q31_t)0x79cacd8d, (q31_t)0xe480e057, + (q31_t)0x79c5664f, (q31_t)0xe47587eb, (q31_t)0x79bffcd7, (q31_t)0xe46a308f, + (q31_t)0x79ba9125, (q31_t)0xe45eda43, (q31_t)0x79b52339, (q31_t)0xe4538507, + (q31_t)0x79afb313, (q31_t)0xe44830dd, (q31_t)0x79aa40b4, (q31_t)0xe43cddc4, + (q31_t)0x79a4cc1c, (q31_t)0xe4318bbe, (q31_t)0x799f554b, (q31_t)0xe4263ac9, + (q31_t)0x7999dc42, (q31_t)0xe41aeae8, (q31_t)0x799460ff, (q31_t)0xe40f9c1a, + (q31_t)0x798ee385, (q31_t)0xe4044e60, (q31_t)0x798963d2, (q31_t)0xe3f901ba, + (q31_t)0x7983e1e8, (q31_t)0xe3edb628, (q31_t)0x797e5dc6, (q31_t)0xe3e26bac, + (q31_t)0x7978d76c, (q31_t)0xe3d72245, (q31_t)0x79734edc, (q31_t)0xe3cbd9f4, + (q31_t)0x796dc414, (q31_t)0xe3c092b9, (q31_t)0x79683715, (q31_t)0xe3b54c95, + (q31_t)0x7962a7e0, (q31_t)0xe3aa0788, (q31_t)0x795d1675, (q31_t)0xe39ec393, + (q31_t)0x795782d3, (q31_t)0xe39380b6, (q31_t)0x7951ecfc, (q31_t)0xe3883ef2, + (q31_t)0x794c54ee, (q31_t)0xe37cfe47, (q31_t)0x7946baac, (q31_t)0xe371beb5, + (q31_t)0x79411e33, (q31_t)0xe366803c, (q31_t)0x793b7f86, (q31_t)0xe35b42df, + (q31_t)0x7935dea4, (q31_t)0xe350069b, (q31_t)0x79303b8e, (q31_t)0xe344cb73, + (q31_t)0x792a9642, (q31_t)0xe3399167, (q31_t)0x7924eec3, (q31_t)0xe32e5876, + (q31_t)0x791f4510, (q31_t)0xe32320a2, (q31_t)0x79199929, (q31_t)0xe317e9eb, + (q31_t)0x7913eb0e, (q31_t)0xe30cb451, (q31_t)0x790e3ac0, (q31_t)0xe3017fd5, + (q31_t)0x7908883f, (q31_t)0xe2f64c77, (q31_t)0x7902d38b, (q31_t)0xe2eb1a37, + (q31_t)0x78fd1ca4, (q31_t)0xe2dfe917, (q31_t)0x78f7638b, (q31_t)0xe2d4b916, + (q31_t)0x78f1a840, (q31_t)0xe2c98a35, (q31_t)0x78ebeac2, (q31_t)0xe2be5c74, + (q31_t)0x78e62b13, (q31_t)0xe2b32fd4, (q31_t)0x78e06932, (q31_t)0xe2a80456, + (q31_t)0x78daa520, (q31_t)0xe29cd9f8, (q31_t)0x78d4dedd, (q31_t)0xe291b0bd, + (q31_t)0x78cf1669, (q31_t)0xe28688a4, (q31_t)0x78c94bc4, (q31_t)0xe27b61af, + (q31_t)0x78c37eef, (q31_t)0xe2703bdc, (q31_t)0x78bdafea, (q31_t)0xe265172e, + (q31_t)0x78b7deb4, (q31_t)0xe259f3a3, (q31_t)0x78b20b4f, (q31_t)0xe24ed13d, + (q31_t)0x78ac35ba, (q31_t)0xe243affc, (q31_t)0x78a65df6, (q31_t)0xe2388fe1, + (q31_t)0x78a08402, (q31_t)0xe22d70eb, (q31_t)0x789aa7e0, (q31_t)0xe222531c, + (q31_t)0x7894c98f, (q31_t)0xe2173674, (q31_t)0x788ee910, (q31_t)0xe20c1af3, + (q31_t)0x78890663, (q31_t)0xe2010099, (q31_t)0x78832187, (q31_t)0xe1f5e768, + (q31_t)0x787d3a7e, (q31_t)0xe1eacf5f, (q31_t)0x78775147, (q31_t)0xe1dfb87f, + (q31_t)0x787165e3, (q31_t)0xe1d4a2c8, (q31_t)0x786b7852, (q31_t)0xe1c98e3b, + (q31_t)0x78658894, (q31_t)0xe1be7ad8, (q31_t)0x785f96a9, (q31_t)0xe1b368a0, + (q31_t)0x7859a292, (q31_t)0xe1a85793, (q31_t)0x7853ac4f, (q31_t)0xe19d47b1, + (q31_t)0x784db3e0, (q31_t)0xe19238fb, (q31_t)0x7847b946, (q31_t)0xe1872b72, + (q31_t)0x7841bc7f, (q31_t)0xe17c1f15, (q31_t)0x783bbd8e, (q31_t)0xe17113e5, + (q31_t)0x7835bc71, (q31_t)0xe16609e3, (q31_t)0x782fb92a, (q31_t)0xe15b0110, + (q31_t)0x7829b3b9, (q31_t)0xe14ff96a, (q31_t)0x7823ac1d, (q31_t)0xe144f2f3, + (q31_t)0x781da256, (q31_t)0xe139edac, (q31_t)0x78179666, (q31_t)0xe12ee995, + (q31_t)0x7811884d, (q31_t)0xe123e6ad, (q31_t)0x780b780a, (q31_t)0xe118e4f6, + (q31_t)0x7805659e, (q31_t)0xe10de470, (q31_t)0x77ff5109, (q31_t)0xe102e51c, + (q31_t)0x77f93a4b, (q31_t)0xe0f7e6f9, (q31_t)0x77f32165, (q31_t)0xe0ecea09, + (q31_t)0x77ed0657, (q31_t)0xe0e1ee4b, (q31_t)0x77e6e921, (q31_t)0xe0d6f3c1, + (q31_t)0x77e0c9c3, (q31_t)0xe0cbfa6a, (q31_t)0x77daa83d, (q31_t)0xe0c10247, + (q31_t)0x77d48490, (q31_t)0xe0b60b58, (q31_t)0x77ce5ebd, (q31_t)0xe0ab159e, + (q31_t)0x77c836c2, (q31_t)0xe0a0211a, (q31_t)0x77c20ca1, (q31_t)0xe0952dcb, + (q31_t)0x77bbe05a, (q31_t)0xe08a3bb2, (q31_t)0x77b5b1ec, (q31_t)0xe07f4acf, + (q31_t)0x77af8159, (q31_t)0xe0745b24, (q31_t)0x77a94ea0, (q31_t)0xe0696cb0, + (q31_t)0x77a319c2, (q31_t)0xe05e7f74, (q31_t)0x779ce2be, (q31_t)0xe053936f, + (q31_t)0x7796a996, (q31_t)0xe048a8a4, (q31_t)0x77906e49, (q31_t)0xe03dbf11, + (q31_t)0x778a30d8, (q31_t)0xe032d6b8, (q31_t)0x7783f143, (q31_t)0xe027ef99, + (q31_t)0x777daf89, (q31_t)0xe01d09b4, (q31_t)0x77776bac, (q31_t)0xe012250a, + (q31_t)0x777125ac, (q31_t)0xe007419b, (q31_t)0x776add88, (q31_t)0xdffc5f67, + (q31_t)0x77649341, (q31_t)0xdff17e70, (q31_t)0x775e46d8, (q31_t)0xdfe69eb4, + (q31_t)0x7757f84c, (q31_t)0xdfdbc036, (q31_t)0x7751a79e, (q31_t)0xdfd0e2f5, + (q31_t)0x774b54ce, (q31_t)0xdfc606f1, (q31_t)0x7744ffdd, (q31_t)0xdfbb2c2c, + (q31_t)0x773ea8ca, (q31_t)0xdfb052a5, (q31_t)0x77384f95, (q31_t)0xdfa57a5d, + (q31_t)0x7731f440, (q31_t)0xdf9aa354, (q31_t)0x772b96ca, (q31_t)0xdf8fcd8b, + (q31_t)0x77253733, (q31_t)0xdf84f902, (q31_t)0x771ed57c, (q31_t)0xdf7a25ba, + (q31_t)0x771871a5, (q31_t)0xdf6f53b3, (q31_t)0x77120bae, (q31_t)0xdf6482ed, + (q31_t)0x770ba398, (q31_t)0xdf59b369, (q31_t)0x77053962, (q31_t)0xdf4ee527, + (q31_t)0x76fecd0e, (q31_t)0xdf441828, (q31_t)0x76f85e9a, (q31_t)0xdf394c6b, + (q31_t)0x76f1ee09, (q31_t)0xdf2e81f3, (q31_t)0x76eb7b58, (q31_t)0xdf23b8be, + (q31_t)0x76e5068a, (q31_t)0xdf18f0ce, (q31_t)0x76de8f9e, (q31_t)0xdf0e2a22, + (q31_t)0x76d81695, (q31_t)0xdf0364bc, (q31_t)0x76d19b6e, (q31_t)0xdef8a09b, + (q31_t)0x76cb1e2a, (q31_t)0xdeedddc0, (q31_t)0x76c49ec9, (q31_t)0xdee31c2b, + (q31_t)0x76be1d4c, (q31_t)0xded85bdd, (q31_t)0x76b799b3, (q31_t)0xdecd9cd7, + (q31_t)0x76b113fd, (q31_t)0xdec2df18, (q31_t)0x76aa8c2c, (q31_t)0xdeb822a1, + (q31_t)0x76a4023f, (q31_t)0xdead6773, (q31_t)0x769d7637, (q31_t)0xdea2ad8d, + (q31_t)0x7696e814, (q31_t)0xde97f4f1, (q31_t)0x769057d6, (q31_t)0xde8d3d9e, + (q31_t)0x7689c57d, (q31_t)0xde828796, (q31_t)0x7683310b, (q31_t)0xde77d2d8, + (q31_t)0x767c9a7e, (q31_t)0xde6d1f65, (q31_t)0x767601d7, (q31_t)0xde626d3e, + (q31_t)0x766f6717, (q31_t)0xde57bc62, (q31_t)0x7668ca3e, (q31_t)0xde4d0cd2, + (q31_t)0x76622b4c, (q31_t)0xde425e8f, (q31_t)0x765b8a41, (q31_t)0xde37b199, + (q31_t)0x7654e71d, (q31_t)0xde2d05f1, (q31_t)0x764e41e2, (q31_t)0xde225b96, + (q31_t)0x76479a8e, (q31_t)0xde17b28a, (q31_t)0x7640f123, (q31_t)0xde0d0acc, + (q31_t)0x763a45a0, (q31_t)0xde02645d, (q31_t)0x76339806, (q31_t)0xddf7bf3e, + (q31_t)0x762ce855, (q31_t)0xdded1b6e, (q31_t)0x7626368d, (q31_t)0xdde278ef, + (q31_t)0x761f82af, (q31_t)0xddd7d7c1, (q31_t)0x7618ccba, (q31_t)0xddcd37e4, + (q31_t)0x761214b0, (q31_t)0xddc29958, (q31_t)0x760b5a90, (q31_t)0xddb7fc1e, + (q31_t)0x76049e5b, (q31_t)0xddad6036, (q31_t)0x75fde011, (q31_t)0xdda2c5a2, + (q31_t)0x75f71fb1, (q31_t)0xdd982c60, (q31_t)0x75f05d3d, (q31_t)0xdd8d9472, + (q31_t)0x75e998b5, (q31_t)0xdd82fdd8, (q31_t)0x75e2d219, (q31_t)0xdd786892, + (q31_t)0x75dc0968, (q31_t)0xdd6dd4a2, (q31_t)0x75d53ea5, (q31_t)0xdd634206, + (q31_t)0x75ce71ce, (q31_t)0xdd58b0c0, (q31_t)0x75c7a2e3, (q31_t)0xdd4e20d0, + (q31_t)0x75c0d1e7, (q31_t)0xdd439236, (q31_t)0x75b9fed7, (q31_t)0xdd3904f4, + (q31_t)0x75b329b5, (q31_t)0xdd2e7908, (q31_t)0x75ac5282, (q31_t)0xdd23ee74, + (q31_t)0x75a5793c, (q31_t)0xdd196538, (q31_t)0x759e9de5, (q31_t)0xdd0edd55, + (q31_t)0x7597c07d, (q31_t)0xdd0456ca, (q31_t)0x7590e104, (q31_t)0xdcf9d199, + (q31_t)0x7589ff7a, (q31_t)0xdcef4dc2, (q31_t)0x75831be0, (q31_t)0xdce4cb44, + (q31_t)0x757c3636, (q31_t)0xdcda4a21, (q31_t)0x75754e7c, (q31_t)0xdccfca59, + (q31_t)0x756e64b2, (q31_t)0xdcc54bec, (q31_t)0x756778d9, (q31_t)0xdcbacedb, + (q31_t)0x75608af1, (q31_t)0xdcb05326, (q31_t)0x75599afa, (q31_t)0xdca5d8cd, + (q31_t)0x7552a8f4, (q31_t)0xdc9b5fd2, (q31_t)0x754bb4e1, (q31_t)0xdc90e834, + (q31_t)0x7544bebf, (q31_t)0xdc8671f3, (q31_t)0x753dc68f, (q31_t)0xdc7bfd11, + (q31_t)0x7536cc52, (q31_t)0xdc71898d, (q31_t)0x752fd008, (q31_t)0xdc671768, + (q31_t)0x7528d1b1, (q31_t)0xdc5ca6a2, (q31_t)0x7521d14d, (q31_t)0xdc52373c, + (q31_t)0x751acedd, (q31_t)0xdc47c936, (q31_t)0x7513ca60, (q31_t)0xdc3d5c91, + (q31_t)0x750cc3d8, (q31_t)0xdc32f14d, (q31_t)0x7505bb44, (q31_t)0xdc28876a, + (q31_t)0x74feb0a5, (q31_t)0xdc1e1ee9, (q31_t)0x74f7a3fb, (q31_t)0xdc13b7c9, + (q31_t)0x74f09546, (q31_t)0xdc09520d, (q31_t)0x74e98487, (q31_t)0xdbfeedb3, + (q31_t)0x74e271bd, (q31_t)0xdbf48abd, (q31_t)0x74db5cea, (q31_t)0xdbea292b, + (q31_t)0x74d4460c, (q31_t)0xdbdfc8fc, (q31_t)0x74cd2d26, (q31_t)0xdbd56a32, + (q31_t)0x74c61236, (q31_t)0xdbcb0cce, (q31_t)0x74bef53d, (q31_t)0xdbc0b0ce, + (q31_t)0x74b7d63c, (q31_t)0xdbb65634, (q31_t)0x74b0b533, (q31_t)0xdbabfd01, + (q31_t)0x74a99221, (q31_t)0xdba1a534, (q31_t)0x74a26d08, (q31_t)0xdb974ece, + (q31_t)0x749b45e7, (q31_t)0xdb8cf9cf, (q31_t)0x74941cbf, (q31_t)0xdb82a638, + (q31_t)0x748cf190, (q31_t)0xdb785409, (q31_t)0x7485c45b, (q31_t)0xdb6e0342, + (q31_t)0x747e951f, (q31_t)0xdb63b3e5, (q31_t)0x747763dd, (q31_t)0xdb5965f1, + (q31_t)0x74703095, (q31_t)0xdb4f1967, (q31_t)0x7468fb47, (q31_t)0xdb44ce46, + (q31_t)0x7461c3f5, (q31_t)0xdb3a8491, (q31_t)0x745a8a9d, (q31_t)0xdb303c46, + (q31_t)0x74534f41, (q31_t)0xdb25f566, (q31_t)0x744c11e0, (q31_t)0xdb1baff2, + (q31_t)0x7444d27b, (q31_t)0xdb116beb, (q31_t)0x743d9112, (q31_t)0xdb072950, + (q31_t)0x74364da6, (q31_t)0xdafce821, (q31_t)0x742f0836, (q31_t)0xdaf2a860, + (q31_t)0x7427c0c3, (q31_t)0xdae86a0d, (q31_t)0x7420774d, (q31_t)0xdade2d28, + (q31_t)0x74192bd5, (q31_t)0xdad3f1b1, (q31_t)0x7411de5b, (q31_t)0xdac9b7a9, + (q31_t)0x740a8edf, (q31_t)0xdabf7f11, (q31_t)0x74033d61, (q31_t)0xdab547e8, + (q31_t)0x73fbe9e2, (q31_t)0xdaab122f, (q31_t)0x73f49462, (q31_t)0xdaa0dde7, + (q31_t)0x73ed3ce1, (q31_t)0xda96ab0f, (q31_t)0x73e5e360, (q31_t)0xda8c79a9, + (q31_t)0x73de87de, (q31_t)0xda8249b4, (q31_t)0x73d72a5d, (q31_t)0xda781b31, + (q31_t)0x73cfcadc, (q31_t)0xda6dee21, (q31_t)0x73c8695b, (q31_t)0xda63c284, + (q31_t)0x73c105db, (q31_t)0xda599859, (q31_t)0x73b9a05d, (q31_t)0xda4f6fa3, + (q31_t)0x73b238e0, (q31_t)0xda454860, (q31_t)0x73aacf65, (q31_t)0xda3b2292, + (q31_t)0x73a363ec, (q31_t)0xda30fe38, (q31_t)0x739bf675, (q31_t)0xda26db54, + (q31_t)0x73948701, (q31_t)0xda1cb9e5, (q31_t)0x738d1590, (q31_t)0xda1299ec, + (q31_t)0x7385a222, (q31_t)0xda087b69, (q31_t)0x737e2cb7, (q31_t)0xd9fe5e5e, + (q31_t)0x7376b551, (q31_t)0xd9f442c9, (q31_t)0x736f3bee, (q31_t)0xd9ea28ac, + (q31_t)0x7367c090, (q31_t)0xd9e01006, (q31_t)0x73604336, (q31_t)0xd9d5f8d9, + (q31_t)0x7358c3e2, (q31_t)0xd9cbe325, (q31_t)0x73514292, (q31_t)0xd9c1cee9, + (q31_t)0x7349bf48, (q31_t)0xd9b7bc27, (q31_t)0x73423a04, (q31_t)0xd9adaadf, + (q31_t)0x733ab2c6, (q31_t)0xd9a39b11, (q31_t)0x7333298f, (q31_t)0xd9998cbe, + (q31_t)0x732b9e5e, (q31_t)0xd98f7fe6, (q31_t)0x73241134, (q31_t)0xd9857489, + (q31_t)0x731c8211, (q31_t)0xd97b6aa8, (q31_t)0x7314f0f6, (q31_t)0xd9716243, + (q31_t)0x730d5de3, (q31_t)0xd9675b5a, (q31_t)0x7305c8d7, (q31_t)0xd95d55ef, + (q31_t)0x72fe31d5, (q31_t)0xd9535201, (q31_t)0x72f698db, (q31_t)0xd9494f90, + (q31_t)0x72eefdea, (q31_t)0xd93f4e9e, (q31_t)0x72e76102, (q31_t)0xd9354f2a, + (q31_t)0x72dfc224, (q31_t)0xd92b5135, (q31_t)0x72d82150, (q31_t)0xd92154bf, + (q31_t)0x72d07e85, (q31_t)0xd91759c9, (q31_t)0x72c8d9c6, (q31_t)0xd90d6053, + (q31_t)0x72c13311, (q31_t)0xd903685d, (q31_t)0x72b98a67, (q31_t)0xd8f971e8, + (q31_t)0x72b1dfc9, (q31_t)0xd8ef7cf4, (q31_t)0x72aa3336, (q31_t)0xd8e58982, + (q31_t)0x72a284b0, (q31_t)0xd8db9792, (q31_t)0x729ad435, (q31_t)0xd8d1a724, + (q31_t)0x729321c7, (q31_t)0xd8c7b838, (q31_t)0x728b6d66, (q31_t)0xd8bdcad0, + (q31_t)0x7283b712, (q31_t)0xd8b3deeb, (q31_t)0x727bfecc, (q31_t)0xd8a9f48a, + (q31_t)0x72744493, (q31_t)0xd8a00bae, (q31_t)0x726c8868, (q31_t)0xd8962456, + (q31_t)0x7264ca4c, (q31_t)0xd88c3e83, (q31_t)0x725d0a3e, (q31_t)0xd8825a35, + (q31_t)0x72554840, (q31_t)0xd878776d, (q31_t)0x724d8450, (q31_t)0xd86e962b, + (q31_t)0x7245be70, (q31_t)0xd864b670, (q31_t)0x723df6a0, (q31_t)0xd85ad83c, + (q31_t)0x72362ce0, (q31_t)0xd850fb8e, (q31_t)0x722e6130, (q31_t)0xd8472069, + (q31_t)0x72269391, (q31_t)0xd83d46cc, (q31_t)0x721ec403, (q31_t)0xd8336eb7, + (q31_t)0x7216f287, (q31_t)0xd829982b, (q31_t)0x720f1f1c, (q31_t)0xd81fc328, + (q31_t)0x720749c3, (q31_t)0xd815efae, (q31_t)0x71ff727c, (q31_t)0xd80c1dbf, + (q31_t)0x71f79948, (q31_t)0xd8024d59, (q31_t)0x71efbe27, (q31_t)0xd7f87e7f, + (q31_t)0x71e7e118, (q31_t)0xd7eeb130, (q31_t)0x71e0021e, (q31_t)0xd7e4e56c, + (q31_t)0x71d82137, (q31_t)0xd7db1b34, (q31_t)0x71d03e64, (q31_t)0xd7d15288, + (q31_t)0x71c859a5, (q31_t)0xd7c78b68, (q31_t)0x71c072fb, (q31_t)0xd7bdc5d6, + (q31_t)0x71b88a66, (q31_t)0xd7b401d1, (q31_t)0x71b09fe7, (q31_t)0xd7aa3f5a, + (q31_t)0x71a8b37c, (q31_t)0xd7a07e70, (q31_t)0x71a0c528, (q31_t)0xd796bf16, + (q31_t)0x7198d4ea, (q31_t)0xd78d014a, (q31_t)0x7190e2c3, (q31_t)0xd783450d, + (q31_t)0x7188eeb2, (q31_t)0xd7798a60, (q31_t)0x7180f8b8, (q31_t)0xd76fd143, + (q31_t)0x717900d6, (q31_t)0xd76619b6, (q31_t)0x7171070c, (q31_t)0xd75c63ba, + (q31_t)0x71690b59, (q31_t)0xd752af4f, (q31_t)0x71610dbf, (q31_t)0xd748fc75, + (q31_t)0x71590e3e, (q31_t)0xd73f4b2e, (q31_t)0x71510cd5, (q31_t)0xd7359b78, + (q31_t)0x71490986, (q31_t)0xd72bed55, (q31_t)0x71410450, (q31_t)0xd72240c5, + (q31_t)0x7138fd35, (q31_t)0xd71895c9, (q31_t)0x7130f433, (q31_t)0xd70eec60, + (q31_t)0x7128e94c, (q31_t)0xd705448b, (q31_t)0x7120dc80, (q31_t)0xd6fb9e4b, + (q31_t)0x7118cdcf, (q31_t)0xd6f1f99f, (q31_t)0x7110bd39, (q31_t)0xd6e85689, + (q31_t)0x7108aabf, (q31_t)0xd6deb508, (q31_t)0x71009661, (q31_t)0xd6d5151d, + (q31_t)0x70f8801f, (q31_t)0xd6cb76c9, (q31_t)0x70f067fb, (q31_t)0xd6c1da0b, + (q31_t)0x70e84df3, (q31_t)0xd6b83ee4, (q31_t)0x70e03208, (q31_t)0xd6aea555, + (q31_t)0x70d8143b, (q31_t)0xd6a50d5d, (q31_t)0x70cff48c, (q31_t)0xd69b76fe, + (q31_t)0x70c7d2fb, (q31_t)0xd691e237, (q31_t)0x70bfaf89, (q31_t)0xd6884f09, + (q31_t)0x70b78a36, (q31_t)0xd67ebd74, (q31_t)0x70af6302, (q31_t)0xd6752d79, + (q31_t)0x70a739ed, (q31_t)0xd66b9f18, (q31_t)0x709f0ef8, (q31_t)0xd6621251, + (q31_t)0x7096e223, (q31_t)0xd6588725, (q31_t)0x708eb36f, (q31_t)0xd64efd94, + (q31_t)0x708682dc, (q31_t)0xd645759f, (q31_t)0x707e5069, (q31_t)0xd63bef46, + (q31_t)0x70761c18, (q31_t)0xd6326a88, (q31_t)0x706de5e9, (q31_t)0xd628e767, + (q31_t)0x7065addb, (q31_t)0xd61f65e4, (q31_t)0x705d73f0, (q31_t)0xd615e5fd, + (q31_t)0x70553828, (q31_t)0xd60c67b4, (q31_t)0x704cfa83, (q31_t)0xd602eb0a, + (q31_t)0x7044bb00, (q31_t)0xd5f96ffd, (q31_t)0x703c79a2, (q31_t)0xd5eff690, + (q31_t)0x70343667, (q31_t)0xd5e67ec1, (q31_t)0x702bf151, (q31_t)0xd5dd0892, + (q31_t)0x7023aa5f, (q31_t)0xd5d39403, (q31_t)0x701b6193, (q31_t)0xd5ca2115, + (q31_t)0x701316eb, (q31_t)0xd5c0afc6, (q31_t)0x700aca69, (q31_t)0xd5b74019, + (q31_t)0x70027c0c, (q31_t)0xd5add20d, (q31_t)0x6ffa2bd6, (q31_t)0xd5a465a3, + (q31_t)0x6ff1d9c7, (q31_t)0xd59afadb, (q31_t)0x6fe985de, (q31_t)0xd59191b5, + (q31_t)0x6fe1301c, (q31_t)0xd5882a32, (q31_t)0x6fd8d882, (q31_t)0xd57ec452, + (q31_t)0x6fd07f0f, (q31_t)0xd5756016, (q31_t)0x6fc823c5, (q31_t)0xd56bfd7d, + (q31_t)0x6fbfc6a3, (q31_t)0xd5629c89, (q31_t)0x6fb767aa, (q31_t)0xd5593d3a, + (q31_t)0x6faf06da, (q31_t)0xd54fdf8f, (q31_t)0x6fa6a433, (q31_t)0xd5468389, + (q31_t)0x6f9e3fb6, (q31_t)0xd53d292a, (q31_t)0x6f95d963, (q31_t)0xd533d070, + (q31_t)0x6f8d713a, (q31_t)0xd52a795d, (q31_t)0x6f85073c, (q31_t)0xd52123f0, + (q31_t)0x6f7c9b69, (q31_t)0xd517d02b, (q31_t)0x6f742dc1, (q31_t)0xd50e7e0d, + (q31_t)0x6f6bbe45, (q31_t)0xd5052d97, (q31_t)0x6f634cf5, (q31_t)0xd4fbdec9, + (q31_t)0x6f5ad9d1, (q31_t)0xd4f291a4, (q31_t)0x6f5264da, (q31_t)0xd4e94627, + (q31_t)0x6f49ee0f, (q31_t)0xd4dffc54, (q31_t)0x6f417573, (q31_t)0xd4d6b42b, + (q31_t)0x6f38fb03, (q31_t)0xd4cd6dab, (q31_t)0x6f307ec2, (q31_t)0xd4c428d6, + (q31_t)0x6f2800af, (q31_t)0xd4bae5ab, (q31_t)0x6f1f80ca, (q31_t)0xd4b1a42c, + (q31_t)0x6f16ff14, (q31_t)0xd4a86458, (q31_t)0x6f0e7b8e, (q31_t)0xd49f2630, + (q31_t)0x6f05f637, (q31_t)0xd495e9b3, (q31_t)0x6efd6f10, (q31_t)0xd48caee4, + (q31_t)0x6ef4e619, (q31_t)0xd48375c1, (q31_t)0x6eec5b53, (q31_t)0xd47a3e4b, + (q31_t)0x6ee3cebe, (q31_t)0xd4710883, (q31_t)0x6edb405a, (q31_t)0xd467d469, + (q31_t)0x6ed2b027, (q31_t)0xd45ea1fd, (q31_t)0x6eca1e27, (q31_t)0xd4557140, + (q31_t)0x6ec18a58, (q31_t)0xd44c4232, (q31_t)0x6eb8f4bc, (q31_t)0xd44314d3, + (q31_t)0x6eb05d53, (q31_t)0xd439e923, (q31_t)0x6ea7c41e, (q31_t)0xd430bf24, + (q31_t)0x6e9f291b, (q31_t)0xd42796d5, (q31_t)0x6e968c4d, (q31_t)0xd41e7037, + (q31_t)0x6e8dedb3, (q31_t)0xd4154b4a, (q31_t)0x6e854d4d, (q31_t)0xd40c280e, + (q31_t)0x6e7cab1c, (q31_t)0xd4030684, (q31_t)0x6e740720, (q31_t)0xd3f9e6ad, + (q31_t)0x6e6b615a, (q31_t)0xd3f0c887, (q31_t)0x6e62b9ca, (q31_t)0xd3e7ac15, + (q31_t)0x6e5a1070, (q31_t)0xd3de9156, (q31_t)0x6e51654c, (q31_t)0xd3d5784a, + (q31_t)0x6e48b860, (q31_t)0xd3cc60f2, (q31_t)0x6e4009aa, (q31_t)0xd3c34b4f, + (q31_t)0x6e37592c, (q31_t)0xd3ba3760, (q31_t)0x6e2ea6e6, (q31_t)0xd3b12526, + (q31_t)0x6e25f2d8, (q31_t)0xd3a814a2, (q31_t)0x6e1d3d03, (q31_t)0xd39f05d3, + (q31_t)0x6e148566, (q31_t)0xd395f8ba, (q31_t)0x6e0bcc03, (q31_t)0xd38ced57, + (q31_t)0x6e0310d9, (q31_t)0xd383e3ab, (q31_t)0x6dfa53e9, (q31_t)0xd37adbb6, + (q31_t)0x6df19534, (q31_t)0xd371d579, (q31_t)0x6de8d4b8, (q31_t)0xd368d0f3, + (q31_t)0x6de01278, (q31_t)0xd35fce26, (q31_t)0x6dd74e73, (q31_t)0xd356cd11, + (q31_t)0x6dce88aa, (q31_t)0xd34dcdb4, (q31_t)0x6dc5c11c, (q31_t)0xd344d011, + (q31_t)0x6dbcf7cb, (q31_t)0xd33bd427, (q31_t)0x6db42cb6, (q31_t)0xd332d9f7, + (q31_t)0x6dab5fdf, (q31_t)0xd329e181, (q31_t)0x6da29144, (q31_t)0xd320eac6, + (q31_t)0x6d99c0e7, (q31_t)0xd317f5c6, (q31_t)0x6d90eec8, (q31_t)0xd30f0280, + (q31_t)0x6d881ae8, (q31_t)0xd30610f7, (q31_t)0x6d7f4545, (q31_t)0xd2fd2129, + (q31_t)0x6d766de2, (q31_t)0xd2f43318, (q31_t)0x6d6d94bf, (q31_t)0xd2eb46c3, + (q31_t)0x6d64b9da, (q31_t)0xd2e25c2b, (q31_t)0x6d5bdd36, (q31_t)0xd2d97350, + (q31_t)0x6d52fed2, (q31_t)0xd2d08c33, (q31_t)0x6d4a1eaf, (q31_t)0xd2c7a6d4, + (q31_t)0x6d413ccd, (q31_t)0xd2bec333, (q31_t)0x6d38592c, (q31_t)0xd2b5e151, + (q31_t)0x6d2f73cd, (q31_t)0xd2ad012e, (q31_t)0x6d268cb0, (q31_t)0xd2a422ca, + (q31_t)0x6d1da3d5, (q31_t)0xd29b4626, (q31_t)0x6d14b93d, (q31_t)0xd2926b41, + (q31_t)0x6d0bcce8, (q31_t)0xd289921e, (q31_t)0x6d02ded7, (q31_t)0xd280babb, + (q31_t)0x6cf9ef09, (q31_t)0xd277e518, (q31_t)0x6cf0fd80, (q31_t)0xd26f1138, + (q31_t)0x6ce80a3a, (q31_t)0xd2663f19, (q31_t)0x6cdf153a, (q31_t)0xd25d6ebc, + (q31_t)0x6cd61e7f, (q31_t)0xd254a021, (q31_t)0x6ccd2609, (q31_t)0xd24bd34a, + (q31_t)0x6cc42bd9, (q31_t)0xd2430835, (q31_t)0x6cbb2fef, (q31_t)0xd23a3ee4, + (q31_t)0x6cb2324c, (q31_t)0xd2317756, (q31_t)0x6ca932ef, (q31_t)0xd228b18d, + (q31_t)0x6ca031da, (q31_t)0xd21fed88, (q31_t)0x6c972f0d, (q31_t)0xd2172b48, + (q31_t)0x6c8e2a87, (q31_t)0xd20e6acc, (q31_t)0x6c85244a, (q31_t)0xd205ac17, + (q31_t)0x6c7c1c55, (q31_t)0xd1fcef27, (q31_t)0x6c7312a9, (q31_t)0xd1f433fd, + (q31_t)0x6c6a0746, (q31_t)0xd1eb7a9a, (q31_t)0x6c60fa2d, (q31_t)0xd1e2c2fd, + (q31_t)0x6c57eb5e, (q31_t)0xd1da0d28, (q31_t)0x6c4edada, (q31_t)0xd1d1591a, + (q31_t)0x6c45c8a0, (q31_t)0xd1c8a6d4, (q31_t)0x6c3cb4b1, (q31_t)0xd1bff656, + (q31_t)0x6c339f0e, (q31_t)0xd1b747a0, (q31_t)0x6c2a87b6, (q31_t)0xd1ae9ab4, + (q31_t)0x6c216eaa, (q31_t)0xd1a5ef90, (q31_t)0x6c1853eb, (q31_t)0xd19d4636, + (q31_t)0x6c0f3779, (q31_t)0xd1949ea6, (q31_t)0x6c061953, (q31_t)0xd18bf8e0, + (q31_t)0x6bfcf97c, (q31_t)0xd18354e4, (q31_t)0x6bf3d7f2, (q31_t)0xd17ab2b3, + (q31_t)0x6beab4b6, (q31_t)0xd172124d, (q31_t)0x6be18fc9, (q31_t)0xd16973b3, + (q31_t)0x6bd8692b, (q31_t)0xd160d6e5, (q31_t)0x6bcf40dc, (q31_t)0xd1583be2, + (q31_t)0x6bc616dd, (q31_t)0xd14fa2ad, (q31_t)0x6bbceb2d, (q31_t)0xd1470b44, + (q31_t)0x6bb3bdce, (q31_t)0xd13e75a8, (q31_t)0x6baa8ec0, (q31_t)0xd135e1d9, + (q31_t)0x6ba15e03, (q31_t)0xd12d4fd9, (q31_t)0x6b982b97, (q31_t)0xd124bfa6, + (q31_t)0x6b8ef77d, (q31_t)0xd11c3142, (q31_t)0x6b85c1b5, (q31_t)0xd113a4ad, + (q31_t)0x6b7c8a3f, (q31_t)0xd10b19e7, (q31_t)0x6b73511c, (q31_t)0xd10290f0, + (q31_t)0x6b6a164d, (q31_t)0xd0fa09c9, (q31_t)0x6b60d9d0, (q31_t)0xd0f18472, + (q31_t)0x6b579ba8, (q31_t)0xd0e900ec, (q31_t)0x6b4e5bd4, (q31_t)0xd0e07f36, + (q31_t)0x6b451a55, (q31_t)0xd0d7ff51, (q31_t)0x6b3bd72a, (q31_t)0xd0cf813e, + (q31_t)0x6b329255, (q31_t)0xd0c704fd, (q31_t)0x6b294bd5, (q31_t)0xd0be8a8d, + (q31_t)0x6b2003ac, (q31_t)0xd0b611f1, (q31_t)0x6b16b9d9, (q31_t)0xd0ad9b26, + (q31_t)0x6b0d6e5c, (q31_t)0xd0a5262f, (q31_t)0x6b042137, (q31_t)0xd09cb30b, + (q31_t)0x6afad269, (q31_t)0xd09441bb, (q31_t)0x6af181f3, (q31_t)0xd08bd23f, + (q31_t)0x6ae82fd5, (q31_t)0xd0836497, (q31_t)0x6adedc10, (q31_t)0xd07af8c4, + (q31_t)0x6ad586a3, (q31_t)0xd0728ec6, (q31_t)0x6acc2f90, (q31_t)0xd06a269d, + (q31_t)0x6ac2d6d6, (q31_t)0xd061c04a, (q31_t)0x6ab97c77, (q31_t)0xd0595bcd, + (q31_t)0x6ab02071, (q31_t)0xd050f926, (q31_t)0x6aa6c2c6, (q31_t)0xd0489856, + (q31_t)0x6a9d6377, (q31_t)0xd040395d, (q31_t)0x6a940283, (q31_t)0xd037dc3b, + (q31_t)0x6a8a9fea, (q31_t)0xd02f80f1, (q31_t)0x6a813bae, (q31_t)0xd027277e, + (q31_t)0x6a77d5ce, (q31_t)0xd01ecfe4, (q31_t)0x6a6e6e4b, (q31_t)0xd0167a22, + (q31_t)0x6a650525, (q31_t)0xd00e2639, (q31_t)0x6a5b9a5d, (q31_t)0xd005d42a, + (q31_t)0x6a522df3, (q31_t)0xcffd83f4, (q31_t)0x6a48bfe7, (q31_t)0xcff53597, + (q31_t)0x6a3f503a, (q31_t)0xcfece915, (q31_t)0x6a35deeb, (q31_t)0xcfe49e6d, + (q31_t)0x6a2c6bfd, (q31_t)0xcfdc55a1, (q31_t)0x6a22f76e, (q31_t)0xcfd40eaf, + (q31_t)0x6a19813f, (q31_t)0xcfcbc999, (q31_t)0x6a100970, (q31_t)0xcfc3865e, + (q31_t)0x6a069003, (q31_t)0xcfbb4500, (q31_t)0x69fd14f6, (q31_t)0xcfb3057d, + (q31_t)0x69f3984c, (q31_t)0xcfaac7d8, (q31_t)0x69ea1a03, (q31_t)0xcfa28c10, + (q31_t)0x69e09a1c, (q31_t)0xcf9a5225, (q31_t)0x69d71899, (q31_t)0xcf921a17, + (q31_t)0x69cd9578, (q31_t)0xcf89e3e8, (q31_t)0x69c410ba, (q31_t)0xcf81af97, + (q31_t)0x69ba8a61, (q31_t)0xcf797d24, (q31_t)0x69b1026c, (q31_t)0xcf714c91, + (q31_t)0x69a778db, (q31_t)0xcf691ddd, (q31_t)0x699dedaf, (q31_t)0xcf60f108, + (q31_t)0x699460e8, (q31_t)0xcf58c613, (q31_t)0x698ad287, (q31_t)0xcf509cfe, + (q31_t)0x6981428c, (q31_t)0xcf4875ca, (q31_t)0x6977b0f7, (q31_t)0xcf405077, + (q31_t)0x696e1dc9, (q31_t)0xcf382d05, (q31_t)0x69648902, (q31_t)0xcf300b74, + (q31_t)0x695af2a3, (q31_t)0xcf27ebc5, (q31_t)0x69515aab, (q31_t)0xcf1fcdf8, + (q31_t)0x6947c11c, (q31_t)0xcf17b20d, (q31_t)0x693e25f5, (q31_t)0xcf0f9805, + (q31_t)0x69348937, (q31_t)0xcf077fe1, (q31_t)0x692aeae3, (q31_t)0xceff699f, + (q31_t)0x69214af8, (q31_t)0xcef75541, (q31_t)0x6917a977, (q31_t)0xceef42c7, + (q31_t)0x690e0661, (q31_t)0xcee73231, (q31_t)0x690461b5, (q31_t)0xcedf2380, + (q31_t)0x68fabb75, (q31_t)0xced716b4, (q31_t)0x68f113a0, (q31_t)0xcecf0bcd, + (q31_t)0x68e76a37, (q31_t)0xcec702cb, (q31_t)0x68ddbf3b, (q31_t)0xcebefbb0, + (q31_t)0x68d412ab, (q31_t)0xceb6f67a, (q31_t)0x68ca6488, (q31_t)0xceaef32b, + (q31_t)0x68c0b4d2, (q31_t)0xcea6f1c2, (q31_t)0x68b7038b, (q31_t)0xce9ef241, + (q31_t)0x68ad50b1, (q31_t)0xce96f4a7, (q31_t)0x68a39c46, (q31_t)0xce8ef8f4, + (q31_t)0x6899e64a, (q31_t)0xce86ff2a, (q31_t)0x68902ebd, (q31_t)0xce7f0748, + (q31_t)0x688675a0, (q31_t)0xce77114e, (q31_t)0x687cbaf3, (q31_t)0xce6f1d3d, + (q31_t)0x6872feb6, (q31_t)0xce672b16, (q31_t)0x686940ea, (q31_t)0xce5f3ad8, + (q31_t)0x685f8190, (q31_t)0xce574c84, (q31_t)0x6855c0a6, (q31_t)0xce4f6019, + (q31_t)0x684bfe2f, (q31_t)0xce47759a, (q31_t)0x68423a2a, (q31_t)0xce3f8d05, + (q31_t)0x68387498, (q31_t)0xce37a65b, (q31_t)0x682ead78, (q31_t)0xce2fc19c, + (q31_t)0x6824e4cc, (q31_t)0xce27dec9, (q31_t)0x681b1a94, (q31_t)0xce1ffde2, + (q31_t)0x68114ed0, (q31_t)0xce181ee8, (q31_t)0x68078181, (q31_t)0xce1041d9, + (q31_t)0x67fdb2a7, (q31_t)0xce0866b8, (q31_t)0x67f3e241, (q31_t)0xce008d84, + (q31_t)0x67ea1052, (q31_t)0xcdf8b63d, (q31_t)0x67e03cd8, (q31_t)0xcdf0e0e4, + (q31_t)0x67d667d5, (q31_t)0xcde90d79, (q31_t)0x67cc9149, (q31_t)0xcde13bfd, + (q31_t)0x67c2b934, (q31_t)0xcdd96c6f, (q31_t)0x67b8df97, (q31_t)0xcdd19ed0, + (q31_t)0x67af0472, (q31_t)0xcdc9d320, (q31_t)0x67a527c4, (q31_t)0xcdc20960, + (q31_t)0x679b4990, (q31_t)0xcdba4190, (q31_t)0x679169d5, (q31_t)0xcdb27bb0, + (q31_t)0x67878893, (q31_t)0xcdaab7c0, (q31_t)0x677da5cb, (q31_t)0xcda2f5c2, + (q31_t)0x6773c17d, (q31_t)0xcd9b35b4, (q31_t)0x6769dbaa, (q31_t)0xcd937798, + (q31_t)0x675ff452, (q31_t)0xcd8bbb6d, (q31_t)0x67560b76, (q31_t)0xcd840134, + (q31_t)0x674c2115, (q31_t)0xcd7c48ee, (q31_t)0x67423530, (q31_t)0xcd74929a, + (q31_t)0x673847c8, (q31_t)0xcd6cde39, (q31_t)0x672e58dc, (q31_t)0xcd652bcb, + (q31_t)0x6724686e, (q31_t)0xcd5d7b50, (q31_t)0x671a767e, (q31_t)0xcd55ccca, + (q31_t)0x6710830c, (q31_t)0xcd4e2037, (q31_t)0x67068e18, (q31_t)0xcd467599, + (q31_t)0x66fc97a3, (q31_t)0xcd3eccef, (q31_t)0x66f29fad, (q31_t)0xcd37263a, + (q31_t)0x66e8a637, (q31_t)0xcd2f817b, (q31_t)0x66deab41, (q31_t)0xcd27deb0, + (q31_t)0x66d4aecb, (q31_t)0xcd203ddc, (q31_t)0x66cab0d6, (q31_t)0xcd189efe, + (q31_t)0x66c0b162, (q31_t)0xcd110216, (q31_t)0x66b6b070, (q31_t)0xcd096725, + (q31_t)0x66acadff, (q31_t)0xcd01ce2b, (q31_t)0x66a2aa11, (q31_t)0xccfa3729, + (q31_t)0x6698a4a6, (q31_t)0xccf2a21d, (q31_t)0x668e9dbd, (q31_t)0xcceb0f0a, + (q31_t)0x66849558, (q31_t)0xcce37def, (q31_t)0x667a8b77, (q31_t)0xccdbeecc, + (q31_t)0x6670801a, (q31_t)0xccd461a2, (q31_t)0x66667342, (q31_t)0xccccd671, + (q31_t)0x665c64ef, (q31_t)0xccc54d3a, (q31_t)0x66525521, (q31_t)0xccbdc5fc, + (q31_t)0x664843d9, (q31_t)0xccb640b8, (q31_t)0x663e3117, (q31_t)0xccaebd6e, + (q31_t)0x66341cdb, (q31_t)0xcca73c1e, (q31_t)0x662a0727, (q31_t)0xcc9fbcca, + (q31_t)0x661feffa, (q31_t)0xcc983f70, (q31_t)0x6615d754, (q31_t)0xcc90c412, + (q31_t)0x660bbd37, (q31_t)0xcc894aaf, (q31_t)0x6601a1a2, (q31_t)0xcc81d349, + (q31_t)0x65f78497, (q31_t)0xcc7a5dde, (q31_t)0x65ed6614, (q31_t)0xcc72ea70, + (q31_t)0x65e3461b, (q31_t)0xcc6b78ff, (q31_t)0x65d924ac, (q31_t)0xcc64098b, + (q31_t)0x65cf01c8, (q31_t)0xcc5c9c14, (q31_t)0x65c4dd6e, (q31_t)0xcc55309b, + (q31_t)0x65bab7a0, (q31_t)0xcc4dc720, (q31_t)0x65b0905d, (q31_t)0xcc465fa3, + (q31_t)0x65a667a7, (q31_t)0xcc3efa25, (q31_t)0x659c3d7c, (q31_t)0xcc3796a5, + (q31_t)0x659211df, (q31_t)0xcc303524, (q31_t)0x6587e4cf, (q31_t)0xcc28d5a3, + (q31_t)0x657db64c, (q31_t)0xcc217822, (q31_t)0x65738657, (q31_t)0xcc1a1ca0, + (q31_t)0x656954f1, (q31_t)0xcc12c31f, (q31_t)0x655f2219, (q31_t)0xcc0b6b9e, + (q31_t)0x6554edd1, (q31_t)0xcc04161e, (q31_t)0x654ab818, (q31_t)0xcbfcc29f, + (q31_t)0x654080ef, (q31_t)0xcbf57121, (q31_t)0x65364857, (q31_t)0xcbee21a5, + (q31_t)0x652c0e4f, (q31_t)0xcbe6d42b, (q31_t)0x6521d2d8, (q31_t)0xcbdf88b3, + (q31_t)0x651795f3, (q31_t)0xcbd83f3d, (q31_t)0x650d57a0, (q31_t)0xcbd0f7ca, + (q31_t)0x650317df, (q31_t)0xcbc9b25a, (q31_t)0x64f8d6b0, (q31_t)0xcbc26eee, + (q31_t)0x64ee9415, (q31_t)0xcbbb2d85, (q31_t)0x64e4500e, (q31_t)0xcbb3ee20, + (q31_t)0x64da0a9a, (q31_t)0xcbacb0bf, (q31_t)0x64cfc3ba, (q31_t)0xcba57563, + (q31_t)0x64c57b6f, (q31_t)0xcb9e3c0b, (q31_t)0x64bb31ba, (q31_t)0xcb9704b9, + (q31_t)0x64b0e699, (q31_t)0xcb8fcf6b, (q31_t)0x64a69a0f, (q31_t)0xcb889c23, + (q31_t)0x649c4c1b, (q31_t)0xcb816ae1, (q31_t)0x6491fcbe, (q31_t)0xcb7a3ba5, + (q31_t)0x6487abf7, (q31_t)0xcb730e70, (q31_t)0x647d59c8, (q31_t)0xcb6be341, + (q31_t)0x64730631, (q31_t)0xcb64ba19, (q31_t)0x6468b132, (q31_t)0xcb5d92f8, + (q31_t)0x645e5acc, (q31_t)0xcb566ddf, (q31_t)0x645402ff, (q31_t)0xcb4f4acd, + (q31_t)0x6449a9cc, (q31_t)0xcb4829c4, (q31_t)0x643f4f32, (q31_t)0xcb410ac3, + (q31_t)0x6434f332, (q31_t)0xcb39edca, (q31_t)0x642a95ce, (q31_t)0xcb32d2da, + (q31_t)0x64203704, (q31_t)0xcb2bb9f4, (q31_t)0x6415d6d5, (q31_t)0xcb24a316, + (q31_t)0x640b7543, (q31_t)0xcb1d8e43, (q31_t)0x6401124d, (q31_t)0xcb167b79, + (q31_t)0x63f6adf3, (q31_t)0xcb0f6aba, (q31_t)0x63ec4837, (q31_t)0xcb085c05, + (q31_t)0x63e1e117, (q31_t)0xcb014f5b, (q31_t)0x63d77896, (q31_t)0xcafa44bc, + (q31_t)0x63cd0eb3, (q31_t)0xcaf33c28, (q31_t)0x63c2a36f, (q31_t)0xcaec35a0, + (q31_t)0x63b836ca, (q31_t)0xcae53123, (q31_t)0x63adc8c4, (q31_t)0xcade2eb3, + (q31_t)0x63a3595e, (q31_t)0xcad72e4f, (q31_t)0x6398e898, (q31_t)0xcad02ff8, + (q31_t)0x638e7673, (q31_t)0xcac933ae, (q31_t)0x638402ef, (q31_t)0xcac23971, + (q31_t)0x63798e0d, (q31_t)0xcabb4141, (q31_t)0x636f17cc, (q31_t)0xcab44b1f, + (q31_t)0x6364a02e, (q31_t)0xcaad570c, (q31_t)0x635a2733, (q31_t)0xcaa66506, + (q31_t)0x634facda, (q31_t)0xca9f750f, (q31_t)0x63453125, (q31_t)0xca988727, + (q31_t)0x633ab414, (q31_t)0xca919b4e, (q31_t)0x633035a7, (q31_t)0xca8ab184, + (q31_t)0x6325b5df, (q31_t)0xca83c9ca, (q31_t)0x631b34bc, (q31_t)0xca7ce420, + (q31_t)0x6310b23e, (q31_t)0xca760086, (q31_t)0x63062e67, (q31_t)0xca6f1efc, + (q31_t)0x62fba936, (q31_t)0xca683f83, (q31_t)0x62f122ab, (q31_t)0xca61621b, + (q31_t)0x62e69ac8, (q31_t)0xca5a86c4, (q31_t)0x62dc118c, (q31_t)0xca53ad7e, + (q31_t)0x62d186f8, (q31_t)0xca4cd64b, (q31_t)0x62c6fb0c, (q31_t)0xca460129, + (q31_t)0x62bc6dca, (q31_t)0xca3f2e19, (q31_t)0x62b1df30, (q31_t)0xca385d1d, + (q31_t)0x62a74f40, (q31_t)0xca318e32, (q31_t)0x629cbdfa, (q31_t)0xca2ac15b, + (q31_t)0x62922b5e, (q31_t)0xca23f698, (q31_t)0x6287976e, (q31_t)0xca1d2de7, + (q31_t)0x627d0228, (q31_t)0xca16674b, (q31_t)0x62726b8e, (q31_t)0xca0fa2c3, + (q31_t)0x6267d3a0, (q31_t)0xca08e04f, (q31_t)0x625d3a5e, (q31_t)0xca021fef, + (q31_t)0x62529fca, (q31_t)0xc9fb61a5, (q31_t)0x624803e2, (q31_t)0xc9f4a570, + (q31_t)0x623d66a8, (q31_t)0xc9edeb50, (q31_t)0x6232c81c, (q31_t)0xc9e73346, + (q31_t)0x6228283f, (q31_t)0xc9e07d51, (q31_t)0x621d8711, (q31_t)0xc9d9c973, + (q31_t)0x6212e492, (q31_t)0xc9d317ab, (q31_t)0x620840c2, (q31_t)0xc9cc67fa, + (q31_t)0x61fd9ba3, (q31_t)0xc9c5ba60, (q31_t)0x61f2f534, (q31_t)0xc9bf0edd, + (q31_t)0x61e84d76, (q31_t)0xc9b86572, (q31_t)0x61dda46a, (q31_t)0xc9b1be1e, + (q31_t)0x61d2fa0f, (q31_t)0xc9ab18e3, (q31_t)0x61c84e67, (q31_t)0xc9a475bf, + (q31_t)0x61bda171, (q31_t)0xc99dd4b4, (q31_t)0x61b2f32e, (q31_t)0xc99735c2, + (q31_t)0x61a8439e, (q31_t)0xc99098e9, (q31_t)0x619d92c2, (q31_t)0xc989fe29, + (q31_t)0x6192e09b, (q31_t)0xc9836582, (q31_t)0x61882d28, (q31_t)0xc97ccef5, + (q31_t)0x617d786a, (q31_t)0xc9763a83, (q31_t)0x6172c262, (q31_t)0xc96fa82a, + (q31_t)0x61680b0f, (q31_t)0xc96917ec, (q31_t)0x615d5273, (q31_t)0xc96289c9, + (q31_t)0x6152988d, (q31_t)0xc95bfdc1, (q31_t)0x6147dd5f, (q31_t)0xc95573d4, + (q31_t)0x613d20e8, (q31_t)0xc94eec03, (q31_t)0x61326329, (q31_t)0xc948664d, + (q31_t)0x6127a423, (q31_t)0xc941e2b4, (q31_t)0x611ce3d5, (q31_t)0xc93b6137, + (q31_t)0x61122240, (q31_t)0xc934e1d6, (q31_t)0x61075f65, (q31_t)0xc92e6492, + (q31_t)0x60fc9b44, (q31_t)0xc927e96b, (q31_t)0x60f1d5de, (q31_t)0xc9217062, + (q31_t)0x60e70f32, (q31_t)0xc91af976, (q31_t)0x60dc4742, (q31_t)0xc91484a8, + (q31_t)0x60d17e0d, (q31_t)0xc90e11f7, (q31_t)0x60c6b395, (q31_t)0xc907a166, + (q31_t)0x60bbe7d8, (q31_t)0xc90132f2, (q31_t)0x60b11ad9, (q31_t)0xc8fac69e, + (q31_t)0x60a64c97, (q31_t)0xc8f45c68, (q31_t)0x609b7d13, (q31_t)0xc8edf452, + (q31_t)0x6090ac4d, (q31_t)0xc8e78e5b, (q31_t)0x6085da46, (q31_t)0xc8e12a84, + (q31_t)0x607b06fe, (q31_t)0xc8dac8cd, (q31_t)0x60703275, (q31_t)0xc8d46936, + (q31_t)0x60655cac, (q31_t)0xc8ce0bc0, (q31_t)0x605a85a3, (q31_t)0xc8c7b06b, + (q31_t)0x604fad5b, (q31_t)0xc8c15736, (q31_t)0x6044d3d4, (q31_t)0xc8bb0023, + (q31_t)0x6039f90f, (q31_t)0xc8b4ab32, (q31_t)0x602f1d0b, (q31_t)0xc8ae5862, + (q31_t)0x60243fca, (q31_t)0xc8a807b4, (q31_t)0x6019614c, (q31_t)0xc8a1b928, + (q31_t)0x600e8190, (q31_t)0xc89b6cbf, (q31_t)0x6003a099, (q31_t)0xc8952278, + (q31_t)0x5ff8be65, (q31_t)0xc88eda54, (q31_t)0x5feddaf6, (q31_t)0xc8889454, + (q31_t)0x5fe2f64c, (q31_t)0xc8825077, (q31_t)0x5fd81067, (q31_t)0xc87c0ebd, + (q31_t)0x5fcd2948, (q31_t)0xc875cf28, (q31_t)0x5fc240ef, (q31_t)0xc86f91b7, + (q31_t)0x5fb7575c, (q31_t)0xc869566a, (q31_t)0x5fac6c91, (q31_t)0xc8631d42, + (q31_t)0x5fa1808c, (q31_t)0xc85ce63e, (q31_t)0x5f969350, (q31_t)0xc856b160, + (q31_t)0x5f8ba4dc, (q31_t)0xc8507ea7, (q31_t)0x5f80b531, (q31_t)0xc84a4e14, + (q31_t)0x5f75c44e, (q31_t)0xc8441fa6, (q31_t)0x5f6ad235, (q31_t)0xc83df35f, + (q31_t)0x5f5fdee6, (q31_t)0xc837c93e, (q31_t)0x5f54ea62, (q31_t)0xc831a143, + (q31_t)0x5f49f4a8, (q31_t)0xc82b7b70, (q31_t)0x5f3efdb9, (q31_t)0xc82557c3, + (q31_t)0x5f340596, (q31_t)0xc81f363d, (q31_t)0x5f290c3f, (q31_t)0xc81916df, + (q31_t)0x5f1e11b5, (q31_t)0xc812f9a9, (q31_t)0x5f1315f7, (q31_t)0xc80cde9b, + (q31_t)0x5f081907, (q31_t)0xc806c5b5, (q31_t)0x5efd1ae4, (q31_t)0xc800aef7, + (q31_t)0x5ef21b90, (q31_t)0xc7fa9a62, (q31_t)0x5ee71b0a, (q31_t)0xc7f487f6, + (q31_t)0x5edc1953, (q31_t)0xc7ee77b3, (q31_t)0x5ed1166b, (q31_t)0xc7e8699a, + (q31_t)0x5ec61254, (q31_t)0xc7e25daa, (q31_t)0x5ebb0d0d, (q31_t)0xc7dc53e3, + (q31_t)0x5eb00696, (q31_t)0xc7d64c47, (q31_t)0x5ea4fef0, (q31_t)0xc7d046d6, + (q31_t)0x5e99f61d, (q31_t)0xc7ca438f, (q31_t)0x5e8eec1b, (q31_t)0xc7c44272, + (q31_t)0x5e83e0eb, (q31_t)0xc7be4381, (q31_t)0x5e78d48e, (q31_t)0xc7b846ba, + (q31_t)0x5e6dc705, (q31_t)0xc7b24c20, (q31_t)0x5e62b84f, (q31_t)0xc7ac53b1, + (q31_t)0x5e57a86d, (q31_t)0xc7a65d6e, (q31_t)0x5e4c9760, (q31_t)0xc7a06957, + (q31_t)0x5e418528, (q31_t)0xc79a776c, (q31_t)0x5e3671c5, (q31_t)0xc79487ae, + (q31_t)0x5e2b5d38, (q31_t)0xc78e9a1d, (q31_t)0x5e204781, (q31_t)0xc788aeb9, + (q31_t)0x5e1530a1, (q31_t)0xc782c582, (q31_t)0x5e0a1898, (q31_t)0xc77cde79, + (q31_t)0x5dfeff67, (q31_t)0xc776f99d, (q31_t)0x5df3e50d, (q31_t)0xc77116f0, + (q31_t)0x5de8c98c, (q31_t)0xc76b3671, (q31_t)0x5dddace4, (q31_t)0xc7655820, + (q31_t)0x5dd28f15, (q31_t)0xc75f7bfe, (q31_t)0x5dc7701f, (q31_t)0xc759a20a, + (q31_t)0x5dbc5004, (q31_t)0xc753ca46, (q31_t)0x5db12ec3, (q31_t)0xc74df4b1, + (q31_t)0x5da60c5d, (q31_t)0xc748214c, (q31_t)0x5d9ae8d2, (q31_t)0xc7425016, + (q31_t)0x5d8fc424, (q31_t)0xc73c8111, (q31_t)0x5d849e51, (q31_t)0xc736b43c, + (q31_t)0x5d79775c, (q31_t)0xc730e997, (q31_t)0x5d6e4f43, (q31_t)0xc72b2123, + (q31_t)0x5d632608, (q31_t)0xc7255ae0, (q31_t)0x5d57fbaa, (q31_t)0xc71f96ce, + (q31_t)0x5d4cd02c, (q31_t)0xc719d4ed, (q31_t)0x5d41a38c, (q31_t)0xc714153e, + (q31_t)0x5d3675cb, (q31_t)0xc70e57c0, (q31_t)0x5d2b46ea, (q31_t)0xc7089c75, + (q31_t)0x5d2016e9, (q31_t)0xc702e35c, (q31_t)0x5d14e5c9, (q31_t)0xc6fd2c75, + (q31_t)0x5d09b389, (q31_t)0xc6f777c1, (q31_t)0x5cfe802b, (q31_t)0xc6f1c540, + (q31_t)0x5cf34baf, (q31_t)0xc6ec14f2, (q31_t)0x5ce81615, (q31_t)0xc6e666d7, + (q31_t)0x5cdcdf5e, (q31_t)0xc6e0baf0, (q31_t)0x5cd1a78a, (q31_t)0xc6db113d, + (q31_t)0x5cc66e99, (q31_t)0xc6d569be, (q31_t)0x5cbb348d, (q31_t)0xc6cfc472, + (q31_t)0x5caff965, (q31_t)0xc6ca215c, (q31_t)0x5ca4bd21, (q31_t)0xc6c4807a, + (q31_t)0x5c997fc4, (q31_t)0xc6bee1cd, (q31_t)0x5c8e414b, (q31_t)0xc6b94554, + (q31_t)0x5c8301b9, (q31_t)0xc6b3ab12, (q31_t)0x5c77c10e, (q31_t)0xc6ae1304, + (q31_t)0x5c6c7f4a, (q31_t)0xc6a87d2d, (q31_t)0x5c613c6d, (q31_t)0xc6a2e98b, + (q31_t)0x5c55f878, (q31_t)0xc69d5820, (q31_t)0x5c4ab36b, (q31_t)0xc697c8eb, + (q31_t)0x5c3f6d47, (q31_t)0xc6923bec, (q31_t)0x5c34260c, (q31_t)0xc68cb124, + (q31_t)0x5c28ddbb, (q31_t)0xc6872894, (q31_t)0x5c1d9454, (q31_t)0xc681a23a, + (q31_t)0x5c1249d8, (q31_t)0xc67c1e18, (q31_t)0x5c06fe46, (q31_t)0xc6769c2e, + (q31_t)0x5bfbb1a0, (q31_t)0xc6711c7b, (q31_t)0x5bf063e6, (q31_t)0xc66b9f01, + (q31_t)0x5be51518, (q31_t)0xc66623be, (q31_t)0x5bd9c537, (q31_t)0xc660aab5, + (q31_t)0x5bce7442, (q31_t)0xc65b33e4, (q31_t)0x5bc3223c, (q31_t)0xc655bf4c, + (q31_t)0x5bb7cf23, (q31_t)0xc6504ced, (q31_t)0x5bac7af9, (q31_t)0xc64adcc7, + (q31_t)0x5ba125bd, (q31_t)0xc6456edb, (q31_t)0x5b95cf71, (q31_t)0xc6400329, + (q31_t)0x5b8a7815, (q31_t)0xc63a99b1, (q31_t)0x5b7f1fa9, (q31_t)0xc6353273, + (q31_t)0x5b73c62d, (q31_t)0xc62fcd6f, (q31_t)0x5b686ba3, (q31_t)0xc62a6aa6, + (q31_t)0x5b5d100a, (q31_t)0xc6250a18, (q31_t)0x5b51b363, (q31_t)0xc61fabc4, + (q31_t)0x5b4655ae, (q31_t)0xc61a4fac, (q31_t)0x5b3af6ec, (q31_t)0xc614f5cf, + (q31_t)0x5b2f971e, (q31_t)0xc60f9e2e, (q31_t)0x5b243643, (q31_t)0xc60a48c9, + (q31_t)0x5b18d45c, (q31_t)0xc604f5a0, (q31_t)0x5b0d716a, (q31_t)0xc5ffa4b3, + (q31_t)0x5b020d6c, (q31_t)0xc5fa5603, (q31_t)0x5af6a865, (q31_t)0xc5f5098f, + (q31_t)0x5aeb4253, (q31_t)0xc5efbf58, (q31_t)0x5adfdb37, (q31_t)0xc5ea775e, + (q31_t)0x5ad47312, (q31_t)0xc5e531a1, (q31_t)0x5ac909e5, (q31_t)0xc5dfee22, + (q31_t)0x5abd9faf, (q31_t)0xc5daace1, (q31_t)0x5ab23471, (q31_t)0xc5d56ddd, + (q31_t)0x5aa6c82b, (q31_t)0xc5d03118, (q31_t)0x5a9b5adf, (q31_t)0xc5caf690, + (q31_t)0x5a8fec8c, (q31_t)0xc5c5be47, (q31_t)0x5a847d33, (q31_t)0xc5c0883d, + (q31_t)0x5a790cd4, (q31_t)0xc5bb5472, (q31_t)0x5a6d9b70, (q31_t)0xc5b622e6, + (q31_t)0x5a622907, (q31_t)0xc5b0f399, (q31_t)0x5a56b599, (q31_t)0xc5abc68c, + (q31_t)0x5a4b4128, (q31_t)0xc5a69bbe, (q31_t)0x5a3fcbb3, (q31_t)0xc5a17330, + (q31_t)0x5a34553b, (q31_t)0xc59c4ce3, (q31_t)0x5a28ddc0, (q31_t)0xc59728d5, + (q31_t)0x5a1d6544, (q31_t)0xc5920708, (q31_t)0x5a11ebc5, (q31_t)0xc58ce77c, + (q31_t)0x5a067145, (q31_t)0xc587ca31, (q31_t)0x59faf5c5, (q31_t)0xc582af26, + (q31_t)0x59ef7944, (q31_t)0xc57d965d, (q31_t)0x59e3fbc3, (q31_t)0xc5787fd6, + (q31_t)0x59d87d42, (q31_t)0xc5736b90, (q31_t)0x59ccfdc2, (q31_t)0xc56e598c, + (q31_t)0x59c17d44, (q31_t)0xc56949ca, (q31_t)0x59b5fbc8, (q31_t)0xc5643c4a, + (q31_t)0x59aa794d, (q31_t)0xc55f310d, (q31_t)0x599ef5d6, (q31_t)0xc55a2812, + (q31_t)0x59937161, (q31_t)0xc555215a, (q31_t)0x5987ebf0, (q31_t)0xc5501ce5, + (q31_t)0x597c6584, (q31_t)0xc54b1ab4, (q31_t)0x5970de1b, (q31_t)0xc5461ac6, + (q31_t)0x596555b8, (q31_t)0xc5411d1b, (q31_t)0x5959cc5a, (q31_t)0xc53c21b4, + (q31_t)0x594e4201, (q31_t)0xc5372891, (q31_t)0x5942b6af, (q31_t)0xc53231b3, + (q31_t)0x59372a64, (q31_t)0xc52d3d18, (q31_t)0x592b9d1f, (q31_t)0xc5284ac3, + (q31_t)0x59200ee3, (q31_t)0xc5235ab2, (q31_t)0x59147fae, (q31_t)0xc51e6ce6, + (q31_t)0x5908ef82, (q31_t)0xc519815f, (q31_t)0x58fd5e5f, (q31_t)0xc514981d, + (q31_t)0x58f1cc45, (q31_t)0xc50fb121, (q31_t)0x58e63935, (q31_t)0xc50acc6b, + (q31_t)0x58daa52f, (q31_t)0xc505e9fb, (q31_t)0x58cf1034, (q31_t)0xc50109d0, + (q31_t)0x58c37a44, (q31_t)0xc4fc2bec, (q31_t)0x58b7e35f, (q31_t)0xc4f7504e, + (q31_t)0x58ac4b87, (q31_t)0xc4f276f7, (q31_t)0x58a0b2bb, (q31_t)0xc4ed9fe7, + (q31_t)0x589518fc, (q31_t)0xc4e8cb1e, (q31_t)0x58897e4a, (q31_t)0xc4e3f89c, + (q31_t)0x587de2a7, (q31_t)0xc4df2862, (q31_t)0x58724611, (q31_t)0xc4da5a6f, + (q31_t)0x5866a88a, (q31_t)0xc4d58ec3, (q31_t)0x585b0a13, (q31_t)0xc4d0c560, + (q31_t)0x584f6aab, (q31_t)0xc4cbfe45, (q31_t)0x5843ca53, (q31_t)0xc4c73972, + (q31_t)0x5838290c, (q31_t)0xc4c276e8, (q31_t)0x582c86d5, (q31_t)0xc4bdb6a6, + (q31_t)0x5820e3b0, (q31_t)0xc4b8f8ad, (q31_t)0x58153f9d, (q31_t)0xc4b43cfd, + (q31_t)0x58099a9c, (q31_t)0xc4af8397, (q31_t)0x57fdf4ae, (q31_t)0xc4aacc7a, + (q31_t)0x57f24dd3, (q31_t)0xc4a617a6, (q31_t)0x57e6a60c, (q31_t)0xc4a1651c, + (q31_t)0x57dafd59, (q31_t)0xc49cb4dd, (q31_t)0x57cf53bb, (q31_t)0xc49806e7, + (q31_t)0x57c3a931, (q31_t)0xc4935b3c, (q31_t)0x57b7fdbd, (q31_t)0xc48eb1db, + (q31_t)0x57ac515f, (q31_t)0xc48a0ac4, (q31_t)0x57a0a417, (q31_t)0xc48565f9, + (q31_t)0x5794f5e6, (q31_t)0xc480c379, (q31_t)0x578946cc, (q31_t)0xc47c2344, + (q31_t)0x577d96ca, (q31_t)0xc477855a, (q31_t)0x5771e5e0, (q31_t)0xc472e9bc, + (q31_t)0x5766340f, (q31_t)0xc46e5069, (q31_t)0x575a8157, (q31_t)0xc469b963, + (q31_t)0x574ecdb8, (q31_t)0xc46524a9, (q31_t)0x57431933, (q31_t)0xc460923b, + (q31_t)0x573763c9, (q31_t)0xc45c0219, (q31_t)0x572bad7a, (q31_t)0xc4577444, + (q31_t)0x571ff646, (q31_t)0xc452e8bc, (q31_t)0x57143e2d, (q31_t)0xc44e5f80, + (q31_t)0x57088531, (q31_t)0xc449d892, (q31_t)0x56fccb51, (q31_t)0xc44553f2, + (q31_t)0x56f1108f, (q31_t)0xc440d19e, (q31_t)0x56e554ea, (q31_t)0xc43c5199, + (q31_t)0x56d99864, (q31_t)0xc437d3e1, (q31_t)0x56cddafb, (q31_t)0xc4335877, + (q31_t)0x56c21cb2, (q31_t)0xc42edf5c, (q31_t)0x56b65d88, (q31_t)0xc42a688f, + (q31_t)0x56aa9d7e, (q31_t)0xc425f410, (q31_t)0x569edc94, (q31_t)0xc42181e0, + (q31_t)0x56931acb, (q31_t)0xc41d11ff, (q31_t)0x56875823, (q31_t)0xc418a46d, + (q31_t)0x567b949d, (q31_t)0xc414392b, (q31_t)0x566fd039, (q31_t)0xc40fd037, + (q31_t)0x56640af7, (q31_t)0xc40b6994, (q31_t)0x565844d8, (q31_t)0xc4070540, + (q31_t)0x564c7ddd, (q31_t)0xc402a33c, (q31_t)0x5640b606, (q31_t)0xc3fe4388, + (q31_t)0x5634ed53, (q31_t)0xc3f9e624, (q31_t)0x562923c5, (q31_t)0xc3f58b10, + (q31_t)0x561d595d, (q31_t)0xc3f1324e, (q31_t)0x56118e1a, (q31_t)0xc3ecdbdc, + (q31_t)0x5605c1fd, (q31_t)0xc3e887bb, (q31_t)0x55f9f507, (q31_t)0xc3e435ea, + (q31_t)0x55ee2738, (q31_t)0xc3dfe66c, (q31_t)0x55e25890, (q31_t)0xc3db993e, + (q31_t)0x55d68911, (q31_t)0xc3d74e62, (q31_t)0x55cab8ba, (q31_t)0xc3d305d8, + (q31_t)0x55bee78c, (q31_t)0xc3cebfa0, (q31_t)0x55b31587, (q31_t)0xc3ca7bba, + (q31_t)0x55a742ac, (q31_t)0xc3c63a26, (q31_t)0x559b6efb, (q31_t)0xc3c1fae5, + (q31_t)0x558f9a76, (q31_t)0xc3bdbdf6, (q31_t)0x5583c51b, (q31_t)0xc3b9835a, + (q31_t)0x5577eeec, (q31_t)0xc3b54b11, (q31_t)0x556c17e9, (q31_t)0xc3b1151b, + (q31_t)0x55604013, (q31_t)0xc3ace178, (q31_t)0x5554676a, (q31_t)0xc3a8b028, + (q31_t)0x55488dee, (q31_t)0xc3a4812c, (q31_t)0x553cb3a0, (q31_t)0xc3a05484, + (q31_t)0x5530d881, (q31_t)0xc39c2a2f, (q31_t)0x5524fc90, (q31_t)0xc398022f, + (q31_t)0x55191fcf, (q31_t)0xc393dc82, (q31_t)0x550d423d, (q31_t)0xc38fb92a, + (q31_t)0x550163dc, (q31_t)0xc38b9827, (q31_t)0x54f584ac, (q31_t)0xc3877978, + (q31_t)0x54e9a4ac, (q31_t)0xc3835d1e, (q31_t)0x54ddc3de, (q31_t)0xc37f4319, + (q31_t)0x54d1e242, (q31_t)0xc37b2b6a, (q31_t)0x54c5ffd9, (q31_t)0xc377160f, + (q31_t)0x54ba1ca3, (q31_t)0xc373030a, (q31_t)0x54ae38a0, (q31_t)0xc36ef25b, + (q31_t)0x54a253d1, (q31_t)0xc36ae401, (q31_t)0x54966e36, (q31_t)0xc366d7fd, + (q31_t)0x548a87d1, (q31_t)0xc362ce50, (q31_t)0x547ea0a0, (q31_t)0xc35ec6f8, + (q31_t)0x5472b8a5, (q31_t)0xc35ac1f7, (q31_t)0x5466cfe1, (q31_t)0xc356bf4d, + (q31_t)0x545ae653, (q31_t)0xc352bef9, (q31_t)0x544efbfc, (q31_t)0xc34ec0fc, + (q31_t)0x544310dd, (q31_t)0xc34ac556, (q31_t)0x543724f5, (q31_t)0xc346cc07, + (q31_t)0x542b3846, (q31_t)0xc342d510, (q31_t)0x541f4ad1, (q31_t)0xc33ee070, + (q31_t)0x54135c94, (q31_t)0xc33aee27, (q31_t)0x54076d91, (q31_t)0xc336fe37, + (q31_t)0x53fb7dc9, (q31_t)0xc333109e, (q31_t)0x53ef8d3c, (q31_t)0xc32f255e, + (q31_t)0x53e39be9, (q31_t)0xc32b3c75, (q31_t)0x53d7a9d3, (q31_t)0xc32755e5, + (q31_t)0x53cbb6f8, (q31_t)0xc32371ae, (q31_t)0x53bfc35b, (q31_t)0xc31f8fcf, + (q31_t)0x53b3cefa, (q31_t)0xc31bb049, (q31_t)0x53a7d9d7, (q31_t)0xc317d31c, + (q31_t)0x539be3f2, (q31_t)0xc313f848, (q31_t)0x538fed4b, (q31_t)0xc3101fce, + (q31_t)0x5383f5e3, (q31_t)0xc30c49ad, (q31_t)0x5377fdbb, (q31_t)0xc30875e5, + (q31_t)0x536c04d2, (q31_t)0xc304a477, (q31_t)0x53600b2a, (q31_t)0xc300d563, + (q31_t)0x535410c3, (q31_t)0xc2fd08a9, (q31_t)0x5348159d, (q31_t)0xc2f93e4a, + (q31_t)0x533c19b8, (q31_t)0xc2f57644, (q31_t)0x53301d16, (q31_t)0xc2f1b099, + (q31_t)0x53241fb6, (q31_t)0xc2eded49, (q31_t)0x5318219a, (q31_t)0xc2ea2c53, + (q31_t)0x530c22c1, (q31_t)0xc2e66db8, (q31_t)0x5300232c, (q31_t)0xc2e2b178, + (q31_t)0x52f422db, (q31_t)0xc2def794, (q31_t)0x52e821cf, (q31_t)0xc2db400a, + (q31_t)0x52dc2009, (q31_t)0xc2d78add, (q31_t)0x52d01d89, (q31_t)0xc2d3d80a, + (q31_t)0x52c41a4f, (q31_t)0xc2d02794, (q31_t)0x52b8165b, (q31_t)0xc2cc7979, + (q31_t)0x52ac11af, (q31_t)0xc2c8cdbb, (q31_t)0x52a00c4b, (q31_t)0xc2c52459, + (q31_t)0x5294062f, (q31_t)0xc2c17d52, (q31_t)0x5287ff5b, (q31_t)0xc2bdd8a9, + (q31_t)0x527bf7d1, (q31_t)0xc2ba365c, (q31_t)0x526fef90, (q31_t)0xc2b6966c, + (q31_t)0x5263e699, (q31_t)0xc2b2f8d8, (q31_t)0x5257dced, (q31_t)0xc2af5da2, + (q31_t)0x524bd28c, (q31_t)0xc2abc4c9, (q31_t)0x523fc776, (q31_t)0xc2a82e4d, + (q31_t)0x5233bbac, (q31_t)0xc2a49a2e, (q31_t)0x5227af2e, (q31_t)0xc2a1086d, + (q31_t)0x521ba1fd, (q31_t)0xc29d790a, (q31_t)0x520f941a, (q31_t)0xc299ec05, + (q31_t)0x52038584, (q31_t)0xc296615d, (q31_t)0x51f7763c, (q31_t)0xc292d914, + (q31_t)0x51eb6643, (q31_t)0xc28f5329, (q31_t)0x51df5599, (q31_t)0xc28bcf9c, + (q31_t)0x51d3443f, (q31_t)0xc2884e6e, (q31_t)0x51c73235, (q31_t)0xc284cf9f, + (q31_t)0x51bb1f7c, (q31_t)0xc281532e, (q31_t)0x51af0c13, (q31_t)0xc27dd91c, + (q31_t)0x51a2f7fc, (q31_t)0xc27a616a, (q31_t)0x5196e337, (q31_t)0xc276ec16, + (q31_t)0x518acdc4, (q31_t)0xc2737922, (q31_t)0x517eb7a4, (q31_t)0xc270088e, + (q31_t)0x5172a0d7, (q31_t)0xc26c9a58, (q31_t)0x5166895f, (q31_t)0xc2692e83, + (q31_t)0x515a713a, (q31_t)0xc265c50e, (q31_t)0x514e586a, (q31_t)0xc2625df8, + (q31_t)0x51423ef0, (q31_t)0xc25ef943, (q31_t)0x513624cb, (q31_t)0xc25b96ee, + (q31_t)0x512a09fc, (q31_t)0xc25836f9, (q31_t)0x511dee84, (q31_t)0xc254d965, + (q31_t)0x5111d263, (q31_t)0xc2517e31, (q31_t)0x5105b599, (q31_t)0xc24e255e, + (q31_t)0x50f99827, (q31_t)0xc24aceed, (q31_t)0x50ed7a0e, (q31_t)0xc2477adc, + (q31_t)0x50e15b4e, (q31_t)0xc244292c, (q31_t)0x50d53be7, (q31_t)0xc240d9de, + (q31_t)0x50c91bda, (q31_t)0xc23d8cf1, (q31_t)0x50bcfb28, (q31_t)0xc23a4265, + (q31_t)0x50b0d9d0, (q31_t)0xc236fa3b, (q31_t)0x50a4b7d3, (q31_t)0xc233b473, + (q31_t)0x50989532, (q31_t)0xc230710d, (q31_t)0x508c71ee, (q31_t)0xc22d3009, + (q31_t)0x50804e06, (q31_t)0xc229f167, (q31_t)0x5074297b, (q31_t)0xc226b528, + (q31_t)0x5068044e, (q31_t)0xc2237b4b, (q31_t)0x505bde7f, (q31_t)0xc22043d0, + (q31_t)0x504fb80e, (q31_t)0xc21d0eb8, (q31_t)0x504390fd, (q31_t)0xc219dc03, + (q31_t)0x5037694b, (q31_t)0xc216abb1, (q31_t)0x502b40f8, (q31_t)0xc2137dc2, + (q31_t)0x501f1807, (q31_t)0xc2105236, (q31_t)0x5012ee76, (q31_t)0xc20d290d, + (q31_t)0x5006c446, (q31_t)0xc20a0248, (q31_t)0x4ffa9979, (q31_t)0xc206dde6, + (q31_t)0x4fee6e0d, (q31_t)0xc203bbe8, (q31_t)0x4fe24205, (q31_t)0xc2009c4e, + (q31_t)0x4fd6155f, (q31_t)0xc1fd7f17, (q31_t)0x4fc9e81e, (q31_t)0xc1fa6445, + (q31_t)0x4fbdba40, (q31_t)0xc1f74bd6, (q31_t)0x4fb18bc8, (q31_t)0xc1f435cc, + (q31_t)0x4fa55cb4, (q31_t)0xc1f12227, (q31_t)0x4f992d06, (q31_t)0xc1ee10e5, + (q31_t)0x4f8cfcbe, (q31_t)0xc1eb0209, (q31_t)0x4f80cbdc, (q31_t)0xc1e7f591, + (q31_t)0x4f749a61, (q31_t)0xc1e4eb7e, (q31_t)0x4f68684e, (q31_t)0xc1e1e3d0, + (q31_t)0x4f5c35a3, (q31_t)0xc1dede87, (q31_t)0x4f500260, (q31_t)0xc1dbdba3, + (q31_t)0x4f43ce86, (q31_t)0xc1d8db25, (q31_t)0x4f379a16, (q31_t)0xc1d5dd0c, + (q31_t)0x4f2b650f, (q31_t)0xc1d2e158, (q31_t)0x4f1f2f73, (q31_t)0xc1cfe80a, + (q31_t)0x4f12f941, (q31_t)0xc1ccf122, (q31_t)0x4f06c27a, (q31_t)0xc1c9fca0, + (q31_t)0x4efa8b20, (q31_t)0xc1c70a84, (q31_t)0x4eee5331, (q31_t)0xc1c41ace, + (q31_t)0x4ee21aaf, (q31_t)0xc1c12d7e, (q31_t)0x4ed5e19a, (q31_t)0xc1be4294, + (q31_t)0x4ec9a7f3, (q31_t)0xc1bb5a11, (q31_t)0x4ebd6db9, (q31_t)0xc1b873f5, + (q31_t)0x4eb132ef, (q31_t)0xc1b5903f, (q31_t)0x4ea4f793, (q31_t)0xc1b2aef0, + (q31_t)0x4e98bba7, (q31_t)0xc1afd007, (q31_t)0x4e8c7f2a, (q31_t)0xc1acf386, + (q31_t)0x4e80421e, (q31_t)0xc1aa196c, (q31_t)0x4e740483, (q31_t)0xc1a741b9, + (q31_t)0x4e67c65a, (q31_t)0xc1a46c6e, (q31_t)0x4e5b87a2, (q31_t)0xc1a1998a, + (q31_t)0x4e4f485c, (q31_t)0xc19ec90d, (q31_t)0x4e430889, (q31_t)0xc19bfaf9, + (q31_t)0x4e36c82a, (q31_t)0xc1992f4c, (q31_t)0x4e2a873e, (q31_t)0xc1966606, + (q31_t)0x4e1e45c6, (q31_t)0xc1939f29, (q31_t)0x4e1203c3, (q31_t)0xc190dab4, + (q31_t)0x4e05c135, (q31_t)0xc18e18a7, (q31_t)0x4df97e1d, (q31_t)0xc18b5903, + (q31_t)0x4ded3a7b, (q31_t)0xc1889bc6, (q31_t)0x4de0f64f, (q31_t)0xc185e0f3, + (q31_t)0x4dd4b19a, (q31_t)0xc1832888, (q31_t)0x4dc86c5d, (q31_t)0xc1807285, + (q31_t)0x4dbc2698, (q31_t)0xc17dbeec, (q31_t)0x4dafe04b, (q31_t)0xc17b0dbb, + (q31_t)0x4da39978, (q31_t)0xc1785ef4, (q31_t)0x4d97521d, (q31_t)0xc175b296, + (q31_t)0x4d8b0a3d, (q31_t)0xc17308a1, (q31_t)0x4d7ec1d6, (q31_t)0xc1706115, + (q31_t)0x4d7278eb, (q31_t)0xc16dbbf3, (q31_t)0x4d662f7b, (q31_t)0xc16b193a, + (q31_t)0x4d59e586, (q31_t)0xc16878eb, (q31_t)0x4d4d9b0e, (q31_t)0xc165db05, + (q31_t)0x4d415013, (q31_t)0xc1633f8a, (q31_t)0x4d350495, (q31_t)0xc160a678, + (q31_t)0x4d28b894, (q31_t)0xc15e0fd1, (q31_t)0x4d1c6c11, (q31_t)0xc15b7b94, + (q31_t)0x4d101f0e, (q31_t)0xc158e9c1, (q31_t)0x4d03d189, (q31_t)0xc1565a58, + (q31_t)0x4cf78383, (q31_t)0xc153cd5a, (q31_t)0x4ceb34fe, (q31_t)0xc15142c6, + (q31_t)0x4cdee5f9, (q31_t)0xc14eba9d, (q31_t)0x4cd29676, (q31_t)0xc14c34df, + (q31_t)0x4cc64673, (q31_t)0xc149b18b, (q31_t)0x4cb9f5f3, (q31_t)0xc14730a3, + (q31_t)0x4cada4f5, (q31_t)0xc144b225, (q31_t)0x4ca1537a, (q31_t)0xc1423613, + (q31_t)0x4c950182, (q31_t)0xc13fbc6c, (q31_t)0x4c88af0e, (q31_t)0xc13d4530, + (q31_t)0x4c7c5c1e, (q31_t)0xc13ad060, (q31_t)0x4c7008b3, (q31_t)0xc1385dfb, + (q31_t)0x4c63b4ce, (q31_t)0xc135ee02, (q31_t)0x4c57606e, (q31_t)0xc1338075, + (q31_t)0x4c4b0b94, (q31_t)0xc1311553, (q31_t)0x4c3eb641, (q31_t)0xc12eac9d, + (q31_t)0x4c326075, (q31_t)0xc12c4653, (q31_t)0x4c260a31, (q31_t)0xc129e276, + (q31_t)0x4c19b374, (q31_t)0xc1278104, (q31_t)0x4c0d5c41, (q31_t)0xc12521ff, + (q31_t)0x4c010496, (q31_t)0xc122c566, (q31_t)0x4bf4ac75, (q31_t)0xc1206b39, + (q31_t)0x4be853de, (q31_t)0xc11e1379, (q31_t)0x4bdbfad1, (q31_t)0xc11bbe26, + (q31_t)0x4bcfa150, (q31_t)0xc1196b3f, (q31_t)0x4bc34759, (q31_t)0xc1171ac6, + (q31_t)0x4bb6ecef, (q31_t)0xc114ccb9, (q31_t)0x4baa9211, (q31_t)0xc1128119, + (q31_t)0x4b9e36c0, (q31_t)0xc11037e6, (q31_t)0x4b91dafc, (q31_t)0xc10df120, + (q31_t)0x4b857ec7, (q31_t)0xc10bacc8, (q31_t)0x4b79221f, (q31_t)0xc1096add, + (q31_t)0x4b6cc506, (q31_t)0xc1072b5f, (q31_t)0x4b60677c, (q31_t)0xc104ee4f, + (q31_t)0x4b540982, (q31_t)0xc102b3ac, (q31_t)0x4b47ab19, (q31_t)0xc1007b77, + (q31_t)0x4b3b4c40, (q31_t)0xc0fe45b0, (q31_t)0x4b2eecf8, (q31_t)0xc0fc1257, + (q31_t)0x4b228d42, (q31_t)0xc0f9e16b, (q31_t)0x4b162d1d, (q31_t)0xc0f7b2ee, + (q31_t)0x4b09cc8c, (q31_t)0xc0f586df, (q31_t)0x4afd6b8d, (q31_t)0xc0f35d3e, + (q31_t)0x4af10a22, (q31_t)0xc0f1360b, (q31_t)0x4ae4a84b, (q31_t)0xc0ef1147, + (q31_t)0x4ad84609, (q31_t)0xc0eceef1, (q31_t)0x4acbe35b, (q31_t)0xc0eacf09, + (q31_t)0x4abf8043, (q31_t)0xc0e8b190, (q31_t)0x4ab31cc1, (q31_t)0xc0e69686, + (q31_t)0x4aa6b8d5, (q31_t)0xc0e47deb, (q31_t)0x4a9a5480, (q31_t)0xc0e267be, + (q31_t)0x4a8defc3, (q31_t)0xc0e05401, (q31_t)0x4a818a9d, (q31_t)0xc0de42b2, + (q31_t)0x4a752510, (q31_t)0xc0dc33d2, (q31_t)0x4a68bf1b, (q31_t)0xc0da2762, + (q31_t)0x4a5c58c0, (q31_t)0xc0d81d61, (q31_t)0x4a4ff1fe, (q31_t)0xc0d615cf, + (q31_t)0x4a438ad7, (q31_t)0xc0d410ad, (q31_t)0x4a37234a, (q31_t)0xc0d20dfa, + (q31_t)0x4a2abb59, (q31_t)0xc0d00db6, (q31_t)0x4a1e5303, (q31_t)0xc0ce0fe3, + (q31_t)0x4a11ea49, (q31_t)0xc0cc147f, (q31_t)0x4a05812c, (q31_t)0xc0ca1b8a, + (q31_t)0x49f917ac, (q31_t)0xc0c82506, (q31_t)0x49ecadc9, (q31_t)0xc0c630f2, + (q31_t)0x49e04385, (q31_t)0xc0c43f4d, (q31_t)0x49d3d8df, (q31_t)0xc0c25019, + (q31_t)0x49c76dd8, (q31_t)0xc0c06355, (q31_t)0x49bb0271, (q31_t)0xc0be7901, + (q31_t)0x49ae96aa, (q31_t)0xc0bc911d, (q31_t)0x49a22a83, (q31_t)0xc0baabaa, + (q31_t)0x4995bdfd, (q31_t)0xc0b8c8a7, (q31_t)0x49895118, (q31_t)0xc0b6e815, + (q31_t)0x497ce3d5, (q31_t)0xc0b509f3, (q31_t)0x49707635, (q31_t)0xc0b32e42, + (q31_t)0x49640837, (q31_t)0xc0b15502, (q31_t)0x495799dd, (q31_t)0xc0af7e33, + (q31_t)0x494b2b27, (q31_t)0xc0ada9d4, (q31_t)0x493ebc14, (q31_t)0xc0abd7e6, + (q31_t)0x49324ca7, (q31_t)0xc0aa086a, (q31_t)0x4925dcdf, (q31_t)0xc0a83b5e, + (q31_t)0x49196cbc, (q31_t)0xc0a670c4, (q31_t)0x490cfc40, (q31_t)0xc0a4a89b, + (q31_t)0x49008b6a, (q31_t)0xc0a2e2e3, (q31_t)0x48f41a3c, (q31_t)0xc0a11f9d, + (q31_t)0x48e7a8b5, (q31_t)0xc09f5ec8, (q31_t)0x48db36d6, (q31_t)0xc09da065, + (q31_t)0x48cec4a0, (q31_t)0xc09be473, (q31_t)0x48c25213, (q31_t)0xc09a2af3, + (q31_t)0x48b5df30, (q31_t)0xc09873e4, (q31_t)0x48a96bf6, (q31_t)0xc096bf48, + (q31_t)0x489cf867, (q31_t)0xc0950d1d, (q31_t)0x48908483, (q31_t)0xc0935d64, + (q31_t)0x4884104b, (q31_t)0xc091b01d, (q31_t)0x48779bbe, (q31_t)0xc0900548, + (q31_t)0x486b26de, (q31_t)0xc08e5ce5, (q31_t)0x485eb1ab, (q31_t)0xc08cb6f5, + (q31_t)0x48523c25, (q31_t)0xc08b1376, (q31_t)0x4845c64d, (q31_t)0xc089726a, + (q31_t)0x48395024, (q31_t)0xc087d3d0, (q31_t)0x482cd9a9, (q31_t)0xc08637a9, + (q31_t)0x482062de, (q31_t)0xc0849df4, (q31_t)0x4813ebc2, (q31_t)0xc08306b2, + (q31_t)0x48077457, (q31_t)0xc08171e2, (q31_t)0x47fafc9c, (q31_t)0xc07fdf85, + (q31_t)0x47ee8493, (q31_t)0xc07e4f9b, (q31_t)0x47e20c3b, (q31_t)0xc07cc223, + (q31_t)0x47d59396, (q31_t)0xc07b371e, (q31_t)0x47c91aa3, (q31_t)0xc079ae8c, + (q31_t)0x47bca163, (q31_t)0xc078286e, (q31_t)0x47b027d7, (q31_t)0xc076a4c2, + (q31_t)0x47a3adff, (q31_t)0xc0752389, (q31_t)0x479733dc, (q31_t)0xc073a4c3, + (q31_t)0x478ab96e, (q31_t)0xc0722871, (q31_t)0x477e3eb5, (q31_t)0xc070ae92, + (q31_t)0x4771c3b3, (q31_t)0xc06f3726, (q31_t)0x47654867, (q31_t)0xc06dc22e, + (q31_t)0x4758ccd2, (q31_t)0xc06c4fa8, (q31_t)0x474c50f4, (q31_t)0xc06adf97, + (q31_t)0x473fd4cf, (q31_t)0xc06971f9, (q31_t)0x47335862, (q31_t)0xc06806ce, + (q31_t)0x4726dbae, (q31_t)0xc0669e18, (q31_t)0x471a5eb3, (q31_t)0xc06537d4, + (q31_t)0x470de172, (q31_t)0xc063d405, (q31_t)0x470163eb, (q31_t)0xc06272aa, + (q31_t)0x46f4e620, (q31_t)0xc06113c2, (q31_t)0x46e86810, (q31_t)0xc05fb74e, + (q31_t)0x46dbe9bb, (q31_t)0xc05e5d4e, (q31_t)0x46cf6b23, (q31_t)0xc05d05c3, + (q31_t)0x46c2ec48, (q31_t)0xc05bb0ab, (q31_t)0x46b66d29, (q31_t)0xc05a5e07, + (q31_t)0x46a9edc9, (q31_t)0xc0590dd8, (q31_t)0x469d6e27, (q31_t)0xc057c01d, + (q31_t)0x4690ee44, (q31_t)0xc05674d6, (q31_t)0x46846e1f, (q31_t)0xc0552c03, + (q31_t)0x4677edbb, (q31_t)0xc053e5a5, (q31_t)0x466b6d16, (q31_t)0xc052a1bb, + (q31_t)0x465eec33, (q31_t)0xc0516045, (q31_t)0x46526b10, (q31_t)0xc0502145, + (q31_t)0x4645e9af, (q31_t)0xc04ee4b8, (q31_t)0x46396810, (q31_t)0xc04daaa1, + (q31_t)0x462ce634, (q31_t)0xc04c72fe, (q31_t)0x4620641a, (q31_t)0xc04b3dcf, + (q31_t)0x4613e1c5, (q31_t)0xc04a0b16, (q31_t)0x46075f33, (q31_t)0xc048dad1, + (q31_t)0x45fadc66, (q31_t)0xc047ad01, (q31_t)0x45ee595d, (q31_t)0xc04681a6, + (q31_t)0x45e1d61b, (q31_t)0xc04558c0, (q31_t)0x45d5529e, (q31_t)0xc044324f, + (q31_t)0x45c8cee7, (q31_t)0xc0430e53, (q31_t)0x45bc4af8, (q31_t)0xc041eccc, + (q31_t)0x45afc6d0, (q31_t)0xc040cdba, (q31_t)0x45a3426f, (q31_t)0xc03fb11d, + (q31_t)0x4596bdd7, (q31_t)0xc03e96f6, (q31_t)0x458a3908, (q31_t)0xc03d7f44, + (q31_t)0x457db403, (q31_t)0xc03c6a07, (q31_t)0x45712ec7, (q31_t)0xc03b573f, + (q31_t)0x4564a955, (q31_t)0xc03a46ed, (q31_t)0x455823ae, (q31_t)0xc0393910, + (q31_t)0x454b9dd3, (q31_t)0xc0382da8, (q31_t)0x453f17c3, (q31_t)0xc03724b6, + (q31_t)0x4532917f, (q31_t)0xc0361e3a, (q31_t)0x45260b08, (q31_t)0xc0351a33, + (q31_t)0x4519845e, (q31_t)0xc03418a2, (q31_t)0x450cfd82, (q31_t)0xc0331986, + (q31_t)0x45007674, (q31_t)0xc0321ce0, (q31_t)0x44f3ef35, (q31_t)0xc03122b0, + (q31_t)0x44e767c5, (q31_t)0xc0302af5, (q31_t)0x44dae024, (q31_t)0xc02f35b1, + (q31_t)0x44ce5854, (q31_t)0xc02e42e2, (q31_t)0x44c1d054, (q31_t)0xc02d5289, + (q31_t)0x44b54825, (q31_t)0xc02c64a6, (q31_t)0x44a8bfc7, (q31_t)0xc02b7939, + (q31_t)0x449c373c, (q31_t)0xc02a9042, (q31_t)0x448fae83, (q31_t)0xc029a9c1, + (q31_t)0x4483259d, (q31_t)0xc028c5b6, (q31_t)0x44769c8b, (q31_t)0xc027e421, + (q31_t)0x446a134c, (q31_t)0xc0270502, (q31_t)0x445d89e2, (q31_t)0xc0262859, + (q31_t)0x4451004d, (q31_t)0xc0254e27, (q31_t)0x4444768d, (q31_t)0xc024766a, + (q31_t)0x4437eca4, (q31_t)0xc023a124, (q31_t)0x442b6290, (q31_t)0xc022ce54, + (q31_t)0x441ed854, (q31_t)0xc021fdfb, (q31_t)0x44124dee, (q31_t)0xc0213018, + (q31_t)0x4405c361, (q31_t)0xc02064ab, (q31_t)0x43f938ac, (q31_t)0xc01f9bb5, + (q31_t)0x43ecadcf, (q31_t)0xc01ed535, (q31_t)0x43e022cc, (q31_t)0xc01e112b, + (q31_t)0x43d397a3, (q31_t)0xc01d4f99, (q31_t)0x43c70c54, (q31_t)0xc01c907c, + (q31_t)0x43ba80df, (q31_t)0xc01bd3d6, (q31_t)0x43adf546, (q31_t)0xc01b19a7, + (q31_t)0x43a16988, (q31_t)0xc01a61ee, (q31_t)0x4394dda7, (q31_t)0xc019acac, + (q31_t)0x438851a2, (q31_t)0xc018f9e1, (q31_t)0x437bc57b, (q31_t)0xc018498c, + (q31_t)0x436f3931, (q31_t)0xc0179bae, (q31_t)0x4362acc5, (q31_t)0xc016f047, + (q31_t)0x43562038, (q31_t)0xc0164757, (q31_t)0x43499389, (q31_t)0xc015a0dd, + (q31_t)0x433d06bb, (q31_t)0xc014fcda, (q31_t)0x433079cc, (q31_t)0xc0145b4e, + (q31_t)0x4323ecbe, (q31_t)0xc013bc39, (q31_t)0x43175f91, (q31_t)0xc0131f9b, + (q31_t)0x430ad245, (q31_t)0xc0128574, (q31_t)0x42fe44dc, (q31_t)0xc011edc3, + (q31_t)0x42f1b755, (q31_t)0xc011588a, (q31_t)0x42e529b0, (q31_t)0xc010c5c7, + (q31_t)0x42d89bf0, (q31_t)0xc010357c, (q31_t)0x42cc0e13, (q31_t)0xc00fa7a8, + (q31_t)0x42bf801a, (q31_t)0xc00f1c4a, (q31_t)0x42b2f207, (q31_t)0xc00e9364, + (q31_t)0x42a663d8, (q31_t)0xc00e0cf5, (q31_t)0x4299d590, (q31_t)0xc00d88fd, + (q31_t)0x428d472e, (q31_t)0xc00d077c, (q31_t)0x4280b8b3, (q31_t)0xc00c8872, + (q31_t)0x42742a1f, (q31_t)0xc00c0be0, (q31_t)0x42679b73, (q31_t)0xc00b91c4, + (q31_t)0x425b0caf, (q31_t)0xc00b1a20, (q31_t)0x424e7dd4, (q31_t)0xc00aa4f3, + (q31_t)0x4241eee2, (q31_t)0xc00a323d, (q31_t)0x42355fd9, (q31_t)0xc009c1ff, + (q31_t)0x4228d0bb, (q31_t)0xc0095438, (q31_t)0x421c4188, (q31_t)0xc008e8e8, + (q31_t)0x420fb240, (q31_t)0xc008800f, (q31_t)0x420322e3, (q31_t)0xc00819ae, + (q31_t)0x41f69373, (q31_t)0xc007b5c4, (q31_t)0x41ea03ef, (q31_t)0xc0075452, + (q31_t)0x41dd7459, (q31_t)0xc006f556, (q31_t)0x41d0e4b0, (q31_t)0xc00698d3, + (q31_t)0x41c454f5, (q31_t)0xc0063ec6, (q31_t)0x41b7c528, (q31_t)0xc005e731, + (q31_t)0x41ab354b, (q31_t)0xc0059214, (q31_t)0x419ea55d, (q31_t)0xc0053f6e, + (q31_t)0x4192155f, (q31_t)0xc004ef3f, (q31_t)0x41858552, (q31_t)0xc004a188, + (q31_t)0x4178f536, (q31_t)0xc0045648, (q31_t)0x416c650b, (q31_t)0xc0040d80, + (q31_t)0x415fd4d2, (q31_t)0xc003c72f, (q31_t)0x4153448c, (q31_t)0xc0038356, + (q31_t)0x4146b438, (q31_t)0xc00341f4, (q31_t)0x413a23d8, (q31_t)0xc003030a, + (q31_t)0x412d936c, (q31_t)0xc002c697, (q31_t)0x412102f4, (q31_t)0xc0028c9c, + (q31_t)0x41147271, (q31_t)0xc0025519, (q31_t)0x4107e1e3, (q31_t)0xc002200d, + (q31_t)0x40fb514b, (q31_t)0xc001ed78, (q31_t)0x40eec0aa, (q31_t)0xc001bd5c, + (q31_t)0x40e22fff, (q31_t)0xc0018fb6, (q31_t)0x40d59f4c, (q31_t)0xc0016489, + (q31_t)0x40c90e90, (q31_t)0xc0013bd3, (q31_t)0x40bc7dcc, (q31_t)0xc0011594, + (q31_t)0x40afed02, (q31_t)0xc000f1ce, (q31_t)0x40a35c30, (q31_t)0xc000d07e, + (q31_t)0x4096cb58, (q31_t)0xc000b1a7, (q31_t)0x408a3a7b, (q31_t)0xc0009547, + (q31_t)0x407da998, (q31_t)0xc0007b5f, (q31_t)0x407118b0, (q31_t)0xc00063ee, + (q31_t)0x406487c4, (q31_t)0xc0004ef5, (q31_t)0x4057f6d4, (q31_t)0xc0003c74, + (q31_t)0x404b65e1, (q31_t)0xc0002c6a, (q31_t)0x403ed4ea, (q31_t)0xc0001ed8, + (q31_t)0x403243f1, (q31_t)0xc00013bd, (q31_t)0x4025b2f7, (q31_t)0xc0000b1a, + (q31_t)0x401921fb, (q31_t)0xc00004ef, (q31_t)0x400c90fe, (q31_t)0xc000013c, +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) +/** + @par + Generation fixed-point realCoefAQ15 array in Q15 format: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pATable[2 * i]     = 0.5 * ( 1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+     pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pATable[i] * pow(2, 15)) + */ +const q15_t __ALIGNED(4) realCoefAQ15[8192] = { + (q15_t)0x4000, (q15_t)0xc000, (q15_t)0x3ff3, (q15_t)0xc000, (q15_t)0x3fe7, (q15_t)0xc000, (q15_t)0x3fda, (q15_t)0xc000, + (q15_t)0x3fce, (q15_t)0xc000, (q15_t)0x3fc1, (q15_t)0xc000, (q15_t)0x3fb5, (q15_t)0xc000, (q15_t)0x3fa8, (q15_t)0xc000, + (q15_t)0x3f9b, (q15_t)0xc000, (q15_t)0x3f8f, (q15_t)0xc000, (q15_t)0x3f82, (q15_t)0xc000, (q15_t)0x3f76, (q15_t)0xc001, + (q15_t)0x3f69, (q15_t)0xc001, (q15_t)0x3f5d, (q15_t)0xc001, (q15_t)0x3f50, (q15_t)0xc001, (q15_t)0x3f44, (q15_t)0xc001, + (q15_t)0x3f37, (q15_t)0xc001, (q15_t)0x3f2a, (q15_t)0xc001, (q15_t)0x3f1e, (q15_t)0xc002, (q15_t)0x3f11, (q15_t)0xc002, + (q15_t)0x3f05, (q15_t)0xc002, (q15_t)0x3ef8, (q15_t)0xc002, (q15_t)0x3eec, (q15_t)0xc002, (q15_t)0x3edf, (q15_t)0xc003, + (q15_t)0x3ed2, (q15_t)0xc003, (q15_t)0x3ec6, (q15_t)0xc003, (q15_t)0x3eb9, (q15_t)0xc003, (q15_t)0x3ead, (q15_t)0xc004, + (q15_t)0x3ea0, (q15_t)0xc004, (q15_t)0x3e94, (q15_t)0xc004, (q15_t)0x3e87, (q15_t)0xc004, (q15_t)0x3e7a, (q15_t)0xc005, + (q15_t)0x3e6e, (q15_t)0xc005, (q15_t)0x3e61, (q15_t)0xc005, (q15_t)0x3e55, (q15_t)0xc006, (q15_t)0x3e48, (q15_t)0xc006, + (q15_t)0x3e3c, (q15_t)0xc006, (q15_t)0x3e2f, (q15_t)0xc007, (q15_t)0x3e23, (q15_t)0xc007, (q15_t)0x3e16, (q15_t)0xc007, + (q15_t)0x3e09, (q15_t)0xc008, (q15_t)0x3dfd, (q15_t)0xc008, (q15_t)0x3df0, (q15_t)0xc009, (q15_t)0x3de4, (q15_t)0xc009, + (q15_t)0x3dd7, (q15_t)0xc009, (q15_t)0x3dcb, (q15_t)0xc00a, (q15_t)0x3dbe, (q15_t)0xc00a, (q15_t)0x3db2, (q15_t)0xc00b, + (q15_t)0x3da5, (q15_t)0xc00b, (q15_t)0x3d98, (q15_t)0xc00c, (q15_t)0x3d8c, (q15_t)0xc00c, (q15_t)0x3d7f, (q15_t)0xc00d, + (q15_t)0x3d73, (q15_t)0xc00d, (q15_t)0x3d66, (q15_t)0xc00e, (q15_t)0x3d5a, (q15_t)0xc00e, (q15_t)0x3d4d, (q15_t)0xc00f, + (q15_t)0x3d40, (q15_t)0xc00f, (q15_t)0x3d34, (q15_t)0xc010, (q15_t)0x3d27, (q15_t)0xc010, (q15_t)0x3d1b, (q15_t)0xc011, + (q15_t)0x3d0e, (q15_t)0xc011, (q15_t)0x3d02, (q15_t)0xc012, (q15_t)0x3cf5, (q15_t)0xc013, (q15_t)0x3ce9, (q15_t)0xc013, + (q15_t)0x3cdc, (q15_t)0xc014, (q15_t)0x3cd0, (q15_t)0xc014, (q15_t)0x3cc3, (q15_t)0xc015, (q15_t)0x3cb6, (q15_t)0xc016, + (q15_t)0x3caa, (q15_t)0xc016, (q15_t)0x3c9d, (q15_t)0xc017, (q15_t)0x3c91, (q15_t)0xc018, (q15_t)0x3c84, (q15_t)0xc018, + (q15_t)0x3c78, (q15_t)0xc019, (q15_t)0x3c6b, (q15_t)0xc01a, (q15_t)0x3c5f, (q15_t)0xc01a, (q15_t)0x3c52, (q15_t)0xc01b, + (q15_t)0x3c45, (q15_t)0xc01c, (q15_t)0x3c39, (q15_t)0xc01d, (q15_t)0x3c2c, (q15_t)0xc01d, (q15_t)0x3c20, (q15_t)0xc01e, + (q15_t)0x3c13, (q15_t)0xc01f, (q15_t)0x3c07, (q15_t)0xc020, (q15_t)0x3bfa, (q15_t)0xc020, (q15_t)0x3bee, (q15_t)0xc021, + (q15_t)0x3be1, (q15_t)0xc022, (q15_t)0x3bd5, (q15_t)0xc023, (q15_t)0x3bc8, (q15_t)0xc024, (q15_t)0x3bbc, (q15_t)0xc024, + (q15_t)0x3baf, (q15_t)0xc025, (q15_t)0x3ba2, (q15_t)0xc026, (q15_t)0x3b96, (q15_t)0xc027, (q15_t)0x3b89, (q15_t)0xc028, + (q15_t)0x3b7d, (q15_t)0xc029, (q15_t)0x3b70, (q15_t)0xc02a, (q15_t)0x3b64, (q15_t)0xc02b, (q15_t)0x3b57, (q15_t)0xc02b, + (q15_t)0x3b4b, (q15_t)0xc02c, (q15_t)0x3b3e, (q15_t)0xc02d, (q15_t)0x3b32, (q15_t)0xc02e, (q15_t)0x3b25, (q15_t)0xc02f, + (q15_t)0x3b19, (q15_t)0xc030, (q15_t)0x3b0c, (q15_t)0xc031, (q15_t)0x3b00, (q15_t)0xc032, (q15_t)0x3af3, (q15_t)0xc033, + (q15_t)0x3ae6, (q15_t)0xc034, (q15_t)0x3ada, (q15_t)0xc035, (q15_t)0x3acd, (q15_t)0xc036, (q15_t)0x3ac1, (q15_t)0xc037, + (q15_t)0x3ab4, (q15_t)0xc038, (q15_t)0x3aa8, (q15_t)0xc039, (q15_t)0x3a9b, (q15_t)0xc03a, (q15_t)0x3a8f, (q15_t)0xc03b, + (q15_t)0x3a82, (q15_t)0xc03c, (q15_t)0x3a76, (q15_t)0xc03d, (q15_t)0x3a69, (q15_t)0xc03f, (q15_t)0x3a5d, (q15_t)0xc040, + (q15_t)0x3a50, (q15_t)0xc041, (q15_t)0x3a44, (q15_t)0xc042, (q15_t)0x3a37, (q15_t)0xc043, (q15_t)0x3a2b, (q15_t)0xc044, + (q15_t)0x3a1e, (q15_t)0xc045, (q15_t)0x3a12, (q15_t)0xc047, (q15_t)0x3a05, (q15_t)0xc048, (q15_t)0x39f9, (q15_t)0xc049, + (q15_t)0x39ec, (q15_t)0xc04a, (q15_t)0x39e0, (q15_t)0xc04b, (q15_t)0x39d3, (q15_t)0xc04c, (q15_t)0x39c7, (q15_t)0xc04e, + (q15_t)0x39ba, (q15_t)0xc04f, (q15_t)0x39ae, (q15_t)0xc050, (q15_t)0x39a1, (q15_t)0xc051, (q15_t)0x3995, (q15_t)0xc053, + (q15_t)0x3988, (q15_t)0xc054, (q15_t)0x397c, (q15_t)0xc055, (q15_t)0x396f, (q15_t)0xc056, (q15_t)0x3963, (q15_t)0xc058, + (q15_t)0x3956, (q15_t)0xc059, (q15_t)0x394a, (q15_t)0xc05a, (q15_t)0x393d, (q15_t)0xc05c, (q15_t)0x3931, (q15_t)0xc05d, + (q15_t)0x3924, (q15_t)0xc05e, (q15_t)0x3918, (q15_t)0xc060, (q15_t)0x390b, (q15_t)0xc061, (q15_t)0x38ff, (q15_t)0xc062, + (q15_t)0x38f2, (q15_t)0xc064, (q15_t)0x38e6, (q15_t)0xc065, (q15_t)0x38d9, (q15_t)0xc067, (q15_t)0x38cd, (q15_t)0xc068, + (q15_t)0x38c0, (q15_t)0xc069, (q15_t)0x38b4, (q15_t)0xc06b, (q15_t)0x38a7, (q15_t)0xc06c, (q15_t)0x389b, (q15_t)0xc06e, + (q15_t)0x388e, (q15_t)0xc06f, (q15_t)0x3882, (q15_t)0xc071, (q15_t)0x3875, (q15_t)0xc072, (q15_t)0x3869, (q15_t)0xc074, + (q15_t)0x385c, (q15_t)0xc075, (q15_t)0x3850, (q15_t)0xc077, (q15_t)0x3843, (q15_t)0xc078, (q15_t)0x3837, (q15_t)0xc07a, + (q15_t)0x382a, (q15_t)0xc07b, (q15_t)0x381e, (q15_t)0xc07d, (q15_t)0x3811, (q15_t)0xc07e, (q15_t)0x3805, (q15_t)0xc080, + (q15_t)0x37f9, (q15_t)0xc081, (q15_t)0x37ec, (q15_t)0xc083, (q15_t)0x37e0, (q15_t)0xc085, (q15_t)0x37d3, (q15_t)0xc086, + (q15_t)0x37c7, (q15_t)0xc088, (q15_t)0x37ba, (q15_t)0xc089, (q15_t)0x37ae, (q15_t)0xc08b, (q15_t)0x37a1, (q15_t)0xc08d, + (q15_t)0x3795, (q15_t)0xc08e, (q15_t)0x3788, (q15_t)0xc090, (q15_t)0x377c, (q15_t)0xc092, (q15_t)0x376f, (q15_t)0xc093, + (q15_t)0x3763, (q15_t)0xc095, (q15_t)0x3757, (q15_t)0xc097, (q15_t)0x374a, (q15_t)0xc098, (q15_t)0x373e, (q15_t)0xc09a, + (q15_t)0x3731, (q15_t)0xc09c, (q15_t)0x3725, (q15_t)0xc09e, (q15_t)0x3718, (q15_t)0xc09f, (q15_t)0x370c, (q15_t)0xc0a1, + (q15_t)0x36ff, (q15_t)0xc0a3, (q15_t)0x36f3, (q15_t)0xc0a5, (q15_t)0x36e7, (q15_t)0xc0a6, (q15_t)0x36da, (q15_t)0xc0a8, + (q15_t)0x36ce, (q15_t)0xc0aa, (q15_t)0x36c1, (q15_t)0xc0ac, (q15_t)0x36b5, (q15_t)0xc0ae, (q15_t)0x36a8, (q15_t)0xc0af, + (q15_t)0x369c, (q15_t)0xc0b1, (q15_t)0x3690, (q15_t)0xc0b3, (q15_t)0x3683, (q15_t)0xc0b5, (q15_t)0x3677, (q15_t)0xc0b7, + (q15_t)0x366a, (q15_t)0xc0b9, (q15_t)0x365e, (q15_t)0xc0bb, (q15_t)0x3651, (q15_t)0xc0bd, (q15_t)0x3645, (q15_t)0xc0be, + (q15_t)0x3639, (q15_t)0xc0c0, (q15_t)0x362c, (q15_t)0xc0c2, (q15_t)0x3620, (q15_t)0xc0c4, (q15_t)0x3613, (q15_t)0xc0c6, + (q15_t)0x3607, (q15_t)0xc0c8, (q15_t)0x35fa, (q15_t)0xc0ca, (q15_t)0x35ee, (q15_t)0xc0cc, (q15_t)0x35e2, (q15_t)0xc0ce, + (q15_t)0x35d5, (q15_t)0xc0d0, (q15_t)0x35c9, (q15_t)0xc0d2, (q15_t)0x35bc, (q15_t)0xc0d4, (q15_t)0x35b0, (q15_t)0xc0d6, + (q15_t)0x35a4, (q15_t)0xc0d8, (q15_t)0x3597, (q15_t)0xc0da, (q15_t)0x358b, (q15_t)0xc0dc, (q15_t)0x357e, (q15_t)0xc0de, + (q15_t)0x3572, (q15_t)0xc0e0, (q15_t)0x3566, (q15_t)0xc0e2, (q15_t)0x3559, (q15_t)0xc0e4, (q15_t)0x354d, (q15_t)0xc0e7, + (q15_t)0x3540, (q15_t)0xc0e9, (q15_t)0x3534, (q15_t)0xc0eb, (q15_t)0x3528, (q15_t)0xc0ed, (q15_t)0x351b, (q15_t)0xc0ef, + (q15_t)0x350f, (q15_t)0xc0f1, (q15_t)0x3503, (q15_t)0xc0f3, (q15_t)0x34f6, (q15_t)0xc0f6, (q15_t)0x34ea, (q15_t)0xc0f8, + (q15_t)0x34dd, (q15_t)0xc0fa, (q15_t)0x34d1, (q15_t)0xc0fc, (q15_t)0x34c5, (q15_t)0xc0fe, (q15_t)0x34b8, (q15_t)0xc100, + (q15_t)0x34ac, (q15_t)0xc103, (q15_t)0x34a0, (q15_t)0xc105, (q15_t)0x3493, (q15_t)0xc107, (q15_t)0x3487, (q15_t)0xc109, + (q15_t)0x347b, (q15_t)0xc10c, (q15_t)0x346e, (q15_t)0xc10e, (q15_t)0x3462, (q15_t)0xc110, (q15_t)0x3455, (q15_t)0xc113, + (q15_t)0x3449, (q15_t)0xc115, (q15_t)0x343d, (q15_t)0xc117, (q15_t)0x3430, (q15_t)0xc119, (q15_t)0x3424, (q15_t)0xc11c, + (q15_t)0x3418, (q15_t)0xc11e, (q15_t)0x340b, (q15_t)0xc120, (q15_t)0x33ff, (q15_t)0xc123, (q15_t)0x33f3, (q15_t)0xc125, + (q15_t)0x33e6, (q15_t)0xc128, (q15_t)0x33da, (q15_t)0xc12a, (q15_t)0x33ce, (q15_t)0xc12c, (q15_t)0x33c1, (q15_t)0xc12f, + (q15_t)0x33b5, (q15_t)0xc131, (q15_t)0x33a9, (q15_t)0xc134, (q15_t)0x339c, (q15_t)0xc136, (q15_t)0x3390, (q15_t)0xc138, + (q15_t)0x3384, (q15_t)0xc13b, (q15_t)0x3377, (q15_t)0xc13d, (q15_t)0x336b, (q15_t)0xc140, (q15_t)0x335f, (q15_t)0xc142, + (q15_t)0x3352, (q15_t)0xc145, (q15_t)0x3346, (q15_t)0xc147, (q15_t)0x333a, (q15_t)0xc14a, (q15_t)0x332d, (q15_t)0xc14c, + (q15_t)0x3321, (q15_t)0xc14f, (q15_t)0x3315, (q15_t)0xc151, (q15_t)0x3308, (q15_t)0xc154, (q15_t)0x32fc, (q15_t)0xc156, + (q15_t)0x32f0, (q15_t)0xc159, (q15_t)0x32e4, (q15_t)0xc15b, (q15_t)0x32d7, (q15_t)0xc15e, (q15_t)0x32cb, (q15_t)0xc161, + (q15_t)0x32bf, (q15_t)0xc163, (q15_t)0x32b2, (q15_t)0xc166, (q15_t)0x32a6, (q15_t)0xc168, (q15_t)0x329a, (q15_t)0xc16b, + (q15_t)0x328e, (q15_t)0xc16e, (q15_t)0x3281, (q15_t)0xc170, (q15_t)0x3275, (q15_t)0xc173, (q15_t)0x3269, (q15_t)0xc176, + (q15_t)0x325c, (q15_t)0xc178, (q15_t)0x3250, (q15_t)0xc17b, (q15_t)0x3244, (q15_t)0xc17e, (q15_t)0x3238, (q15_t)0xc180, + (q15_t)0x322b, (q15_t)0xc183, (q15_t)0x321f, (q15_t)0xc186, (q15_t)0x3213, (q15_t)0xc189, (q15_t)0x3207, (q15_t)0xc18b, + (q15_t)0x31fa, (q15_t)0xc18e, (q15_t)0x31ee, (q15_t)0xc191, (q15_t)0x31e2, (q15_t)0xc194, (q15_t)0x31d5, (q15_t)0xc196, + (q15_t)0x31c9, (q15_t)0xc199, (q15_t)0x31bd, (q15_t)0xc19c, (q15_t)0x31b1, (q15_t)0xc19f, (q15_t)0x31a4, (q15_t)0xc1a2, + (q15_t)0x3198, (q15_t)0xc1a4, (q15_t)0x318c, (q15_t)0xc1a7, (q15_t)0x3180, (q15_t)0xc1aa, (q15_t)0x3174, (q15_t)0xc1ad, + (q15_t)0x3167, (q15_t)0xc1b0, (q15_t)0x315b, (q15_t)0xc1b3, (q15_t)0x314f, (q15_t)0xc1b6, (q15_t)0x3143, (q15_t)0xc1b8, + (q15_t)0x3136, (q15_t)0xc1bb, (q15_t)0x312a, (q15_t)0xc1be, (q15_t)0x311e, (q15_t)0xc1c1, (q15_t)0x3112, (q15_t)0xc1c4, + (q15_t)0x3105, (q15_t)0xc1c7, (q15_t)0x30f9, (q15_t)0xc1ca, (q15_t)0x30ed, (q15_t)0xc1cd, (q15_t)0x30e1, (q15_t)0xc1d0, + (q15_t)0x30d5, (q15_t)0xc1d3, (q15_t)0x30c8, (q15_t)0xc1d6, (q15_t)0x30bc, (q15_t)0xc1d9, (q15_t)0x30b0, (q15_t)0xc1dc, + (q15_t)0x30a4, (q15_t)0xc1df, (q15_t)0x3098, (q15_t)0xc1e2, (q15_t)0x308b, (q15_t)0xc1e5, (q15_t)0x307f, (q15_t)0xc1e8, + (q15_t)0x3073, (q15_t)0xc1eb, (q15_t)0x3067, (q15_t)0xc1ee, (q15_t)0x305b, (q15_t)0xc1f1, (q15_t)0x304e, (q15_t)0xc1f4, + (q15_t)0x3042, (q15_t)0xc1f7, (q15_t)0x3036, (q15_t)0xc1fa, (q15_t)0x302a, (q15_t)0xc1fd, (q15_t)0x301e, (q15_t)0xc201, + (q15_t)0x3012, (q15_t)0xc204, (q15_t)0x3005, (q15_t)0xc207, (q15_t)0x2ff9, (q15_t)0xc20a, (q15_t)0x2fed, (q15_t)0xc20d, + (q15_t)0x2fe1, (q15_t)0xc210, (q15_t)0x2fd5, (q15_t)0xc213, (q15_t)0x2fc9, (q15_t)0xc217, (q15_t)0x2fbc, (q15_t)0xc21a, + (q15_t)0x2fb0, (q15_t)0xc21d, (q15_t)0x2fa4, (q15_t)0xc220, (q15_t)0x2f98, (q15_t)0xc223, (q15_t)0x2f8c, (q15_t)0xc227, + (q15_t)0x2f80, (q15_t)0xc22a, (q15_t)0x2f74, (q15_t)0xc22d, (q15_t)0x2f67, (q15_t)0xc230, (q15_t)0x2f5b, (q15_t)0xc234, + (q15_t)0x2f4f, (q15_t)0xc237, (q15_t)0x2f43, (q15_t)0xc23a, (q15_t)0x2f37, (q15_t)0xc23e, (q15_t)0x2f2b, (q15_t)0xc241, + (q15_t)0x2f1f, (q15_t)0xc244, (q15_t)0x2f13, (q15_t)0xc247, (q15_t)0x2f06, (q15_t)0xc24b, (q15_t)0x2efa, (q15_t)0xc24e, + (q15_t)0x2eee, (q15_t)0xc251, (q15_t)0x2ee2, (q15_t)0xc255, (q15_t)0x2ed6, (q15_t)0xc258, (q15_t)0x2eca, (q15_t)0xc25c, + (q15_t)0x2ebe, (q15_t)0xc25f, (q15_t)0x2eb2, (q15_t)0xc262, (q15_t)0x2ea6, (q15_t)0xc266, (q15_t)0x2e99, (q15_t)0xc269, + (q15_t)0x2e8d, (q15_t)0xc26d, (q15_t)0x2e81, (q15_t)0xc270, (q15_t)0x2e75, (q15_t)0xc273, (q15_t)0x2e69, (q15_t)0xc277, + (q15_t)0x2e5d, (q15_t)0xc27a, (q15_t)0x2e51, (q15_t)0xc27e, (q15_t)0x2e45, (q15_t)0xc281, (q15_t)0x2e39, (q15_t)0xc285, + (q15_t)0x2e2d, (q15_t)0xc288, (q15_t)0x2e21, (q15_t)0xc28c, (q15_t)0x2e15, (q15_t)0xc28f, (q15_t)0x2e09, (q15_t)0xc293, + (q15_t)0x2dfc, (q15_t)0xc296, (q15_t)0x2df0, (q15_t)0xc29a, (q15_t)0x2de4, (q15_t)0xc29d, (q15_t)0x2dd8, (q15_t)0xc2a1, + (q15_t)0x2dcc, (q15_t)0xc2a5, (q15_t)0x2dc0, (q15_t)0xc2a8, (q15_t)0x2db4, (q15_t)0xc2ac, (q15_t)0x2da8, (q15_t)0xc2af, + (q15_t)0x2d9c, (q15_t)0xc2b3, (q15_t)0x2d90, (q15_t)0xc2b7, (q15_t)0x2d84, (q15_t)0xc2ba, (q15_t)0x2d78, (q15_t)0xc2be, + (q15_t)0x2d6c, (q15_t)0xc2c1, (q15_t)0x2d60, (q15_t)0xc2c5, (q15_t)0x2d54, (q15_t)0xc2c9, (q15_t)0x2d48, (q15_t)0xc2cc, + (q15_t)0x2d3c, (q15_t)0xc2d0, (q15_t)0x2d30, (q15_t)0xc2d4, (q15_t)0x2d24, (q15_t)0xc2d8, (q15_t)0x2d18, (q15_t)0xc2db, + (q15_t)0x2d0c, (q15_t)0xc2df, (q15_t)0x2d00, (q15_t)0xc2e3, (q15_t)0x2cf4, (q15_t)0xc2e6, (q15_t)0x2ce8, (q15_t)0xc2ea, + (q15_t)0x2cdc, (q15_t)0xc2ee, (q15_t)0x2cd0, (q15_t)0xc2f2, (q15_t)0x2cc4, (q15_t)0xc2f5, (q15_t)0x2cb8, (q15_t)0xc2f9, + (q15_t)0x2cac, (q15_t)0xc2fd, (q15_t)0x2ca0, (q15_t)0xc301, (q15_t)0x2c94, (q15_t)0xc305, (q15_t)0x2c88, (q15_t)0xc308, + (q15_t)0x2c7c, (q15_t)0xc30c, (q15_t)0x2c70, (q15_t)0xc310, (q15_t)0x2c64, (q15_t)0xc314, (q15_t)0x2c58, (q15_t)0xc318, + (q15_t)0x2c4c, (q15_t)0xc31c, (q15_t)0x2c40, (q15_t)0xc320, (q15_t)0x2c34, (q15_t)0xc323, (q15_t)0x2c28, (q15_t)0xc327, + (q15_t)0x2c1c, (q15_t)0xc32b, (q15_t)0x2c10, (q15_t)0xc32f, (q15_t)0x2c05, (q15_t)0xc333, (q15_t)0x2bf9, (q15_t)0xc337, + (q15_t)0x2bed, (q15_t)0xc33b, (q15_t)0x2be1, (q15_t)0xc33f, (q15_t)0x2bd5, (q15_t)0xc343, (q15_t)0x2bc9, (q15_t)0xc347, + (q15_t)0x2bbd, (q15_t)0xc34b, (q15_t)0x2bb1, (q15_t)0xc34f, (q15_t)0x2ba5, (q15_t)0xc353, (q15_t)0x2b99, (q15_t)0xc357, + (q15_t)0x2b8d, (q15_t)0xc35b, (q15_t)0x2b81, (q15_t)0xc35f, (q15_t)0x2b75, (q15_t)0xc363, (q15_t)0x2b6a, (q15_t)0xc367, + (q15_t)0x2b5e, (q15_t)0xc36b, (q15_t)0x2b52, (q15_t)0xc36f, (q15_t)0x2b46, (q15_t)0xc373, (q15_t)0x2b3a, (q15_t)0xc377, + (q15_t)0x2b2e, (q15_t)0xc37b, (q15_t)0x2b22, (q15_t)0xc37f, (q15_t)0x2b16, (q15_t)0xc383, (q15_t)0x2b0a, (q15_t)0xc387, + (q15_t)0x2aff, (q15_t)0xc38c, (q15_t)0x2af3, (q15_t)0xc390, (q15_t)0x2ae7, (q15_t)0xc394, (q15_t)0x2adb, (q15_t)0xc398, + (q15_t)0x2acf, (q15_t)0xc39c, (q15_t)0x2ac3, (q15_t)0xc3a0, (q15_t)0x2ab7, (q15_t)0xc3a5, (q15_t)0x2aac, (q15_t)0xc3a9, + (q15_t)0x2aa0, (q15_t)0xc3ad, (q15_t)0x2a94, (q15_t)0xc3b1, (q15_t)0x2a88, (q15_t)0xc3b5, (q15_t)0x2a7c, (q15_t)0xc3ba, + (q15_t)0x2a70, (q15_t)0xc3be, (q15_t)0x2a65, (q15_t)0xc3c2, (q15_t)0x2a59, (q15_t)0xc3c6, (q15_t)0x2a4d, (q15_t)0xc3ca, + (q15_t)0x2a41, (q15_t)0xc3cf, (q15_t)0x2a35, (q15_t)0xc3d3, (q15_t)0x2a29, (q15_t)0xc3d7, (q15_t)0x2a1e, (q15_t)0xc3dc, + (q15_t)0x2a12, (q15_t)0xc3e0, (q15_t)0x2a06, (q15_t)0xc3e4, (q15_t)0x29fa, (q15_t)0xc3e9, (q15_t)0x29ee, (q15_t)0xc3ed, + (q15_t)0x29e3, (q15_t)0xc3f1, (q15_t)0x29d7, (q15_t)0xc3f6, (q15_t)0x29cb, (q15_t)0xc3fa, (q15_t)0x29bf, (q15_t)0xc3fe, + (q15_t)0x29b4, (q15_t)0xc403, (q15_t)0x29a8, (q15_t)0xc407, (q15_t)0x299c, (q15_t)0xc40b, (q15_t)0x2990, (q15_t)0xc410, + (q15_t)0x2984, (q15_t)0xc414, (q15_t)0x2979, (q15_t)0xc419, (q15_t)0x296d, (q15_t)0xc41d, (q15_t)0x2961, (q15_t)0xc422, + (q15_t)0x2955, (q15_t)0xc426, (q15_t)0x294a, (q15_t)0xc42a, (q15_t)0x293e, (q15_t)0xc42f, (q15_t)0x2932, (q15_t)0xc433, + (q15_t)0x2926, (q15_t)0xc438, (q15_t)0x291b, (q15_t)0xc43c, (q15_t)0x290f, (q15_t)0xc441, (q15_t)0x2903, (q15_t)0xc445, + (q15_t)0x28f7, (q15_t)0xc44a, (q15_t)0x28ec, (q15_t)0xc44e, (q15_t)0x28e0, (q15_t)0xc453, (q15_t)0x28d4, (q15_t)0xc457, + (q15_t)0x28c9, (q15_t)0xc45c, (q15_t)0x28bd, (q15_t)0xc461, (q15_t)0x28b1, (q15_t)0xc465, (q15_t)0x28a5, (q15_t)0xc46a, + (q15_t)0x289a, (q15_t)0xc46e, (q15_t)0x288e, (q15_t)0xc473, (q15_t)0x2882, (q15_t)0xc478, (q15_t)0x2877, (q15_t)0xc47c, + (q15_t)0x286b, (q15_t)0xc481, (q15_t)0x285f, (q15_t)0xc485, (q15_t)0x2854, (q15_t)0xc48a, (q15_t)0x2848, (q15_t)0xc48f, + (q15_t)0x283c, (q15_t)0xc493, (q15_t)0x2831, (q15_t)0xc498, (q15_t)0x2825, (q15_t)0xc49d, (q15_t)0x2819, (q15_t)0xc4a1, + (q15_t)0x280e, (q15_t)0xc4a6, (q15_t)0x2802, (q15_t)0xc4ab, (q15_t)0x27f6, (q15_t)0xc4b0, (q15_t)0x27eb, (q15_t)0xc4b4, + (q15_t)0x27df, (q15_t)0xc4b9, (q15_t)0x27d3, (q15_t)0xc4be, (q15_t)0x27c8, (q15_t)0xc4c2, (q15_t)0x27bc, (q15_t)0xc4c7, + (q15_t)0x27b1, (q15_t)0xc4cc, (q15_t)0x27a5, (q15_t)0xc4d1, (q15_t)0x2799, (q15_t)0xc4d6, (q15_t)0x278e, (q15_t)0xc4da, + (q15_t)0x2782, (q15_t)0xc4df, (q15_t)0x2777, (q15_t)0xc4e4, (q15_t)0x276b, (q15_t)0xc4e9, (q15_t)0x275f, (q15_t)0xc4ee, + (q15_t)0x2754, (q15_t)0xc4f2, (q15_t)0x2748, (q15_t)0xc4f7, (q15_t)0x273d, (q15_t)0xc4fc, (q15_t)0x2731, (q15_t)0xc501, + (q15_t)0x2725, (q15_t)0xc506, (q15_t)0x271a, (q15_t)0xc50b, (q15_t)0x270e, (q15_t)0xc510, (q15_t)0x2703, (q15_t)0xc515, + (q15_t)0x26f7, (q15_t)0xc51a, (q15_t)0x26ec, (q15_t)0xc51e, (q15_t)0x26e0, (q15_t)0xc523, (q15_t)0x26d4, (q15_t)0xc528, + (q15_t)0x26c9, (q15_t)0xc52d, (q15_t)0x26bd, (q15_t)0xc532, (q15_t)0x26b2, (q15_t)0xc537, (q15_t)0x26a6, (q15_t)0xc53c, + (q15_t)0x269b, (q15_t)0xc541, (q15_t)0x268f, (q15_t)0xc546, (q15_t)0x2684, (q15_t)0xc54b, (q15_t)0x2678, (q15_t)0xc550, + (q15_t)0x266d, (q15_t)0xc555, (q15_t)0x2661, (q15_t)0xc55a, (q15_t)0x2656, (q15_t)0xc55f, (q15_t)0x264a, (q15_t)0xc564, + (q15_t)0x263f, (q15_t)0xc569, (q15_t)0x2633, (q15_t)0xc56e, (q15_t)0x2628, (q15_t)0xc573, (q15_t)0x261c, (q15_t)0xc578, + (q15_t)0x2611, (q15_t)0xc57e, (q15_t)0x2605, (q15_t)0xc583, (q15_t)0x25fa, (q15_t)0xc588, (q15_t)0x25ee, (q15_t)0xc58d, + (q15_t)0x25e3, (q15_t)0xc592, (q15_t)0x25d7, (q15_t)0xc597, (q15_t)0x25cc, (q15_t)0xc59c, (q15_t)0x25c0, (q15_t)0xc5a1, + (q15_t)0x25b5, (q15_t)0xc5a7, (q15_t)0x25a9, (q15_t)0xc5ac, (q15_t)0x259e, (q15_t)0xc5b1, (q15_t)0x2592, (q15_t)0xc5b6, + (q15_t)0x2587, (q15_t)0xc5bb, (q15_t)0x257c, (q15_t)0xc5c1, (q15_t)0x2570, (q15_t)0xc5c6, (q15_t)0x2565, (q15_t)0xc5cb, + (q15_t)0x2559, (q15_t)0xc5d0, (q15_t)0x254e, (q15_t)0xc5d5, (q15_t)0x2542, (q15_t)0xc5db, (q15_t)0x2537, (q15_t)0xc5e0, + (q15_t)0x252c, (q15_t)0xc5e5, (q15_t)0x2520, (q15_t)0xc5ea, (q15_t)0x2515, (q15_t)0xc5f0, (q15_t)0x2509, (q15_t)0xc5f5, + (q15_t)0x24fe, (q15_t)0xc5fa, (q15_t)0x24f3, (q15_t)0xc600, (q15_t)0x24e7, (q15_t)0xc605, (q15_t)0x24dc, (q15_t)0xc60a, + (q15_t)0x24d0, (q15_t)0xc610, (q15_t)0x24c5, (q15_t)0xc615, (q15_t)0x24ba, (q15_t)0xc61a, (q15_t)0x24ae, (q15_t)0xc620, + (q15_t)0x24a3, (q15_t)0xc625, (q15_t)0x2498, (q15_t)0xc62a, (q15_t)0x248c, (q15_t)0xc630, (q15_t)0x2481, (q15_t)0xc635, + (q15_t)0x2476, (q15_t)0xc63b, (q15_t)0x246a, (q15_t)0xc640, (q15_t)0x245f, (q15_t)0xc645, (q15_t)0x2454, (q15_t)0xc64b, + (q15_t)0x2448, (q15_t)0xc650, (q15_t)0x243d, (q15_t)0xc656, (q15_t)0x2432, (q15_t)0xc65b, (q15_t)0x2426, (q15_t)0xc661, + (q15_t)0x241b, (q15_t)0xc666, (q15_t)0x2410, (q15_t)0xc66c, (q15_t)0x2404, (q15_t)0xc671, (q15_t)0x23f9, (q15_t)0xc677, + (q15_t)0x23ee, (q15_t)0xc67c, (q15_t)0x23e2, (q15_t)0xc682, (q15_t)0x23d7, (q15_t)0xc687, (q15_t)0x23cc, (q15_t)0xc68d, + (q15_t)0x23c1, (q15_t)0xc692, (q15_t)0x23b5, (q15_t)0xc698, (q15_t)0x23aa, (q15_t)0xc69d, (q15_t)0x239f, (q15_t)0xc6a3, + (q15_t)0x2394, (q15_t)0xc6a8, (q15_t)0x2388, (q15_t)0xc6ae, (q15_t)0x237d, (q15_t)0xc6b4, (q15_t)0x2372, (q15_t)0xc6b9, + (q15_t)0x2367, (q15_t)0xc6bf, (q15_t)0x235b, (q15_t)0xc6c5, (q15_t)0x2350, (q15_t)0xc6ca, (q15_t)0x2345, (q15_t)0xc6d0, + (q15_t)0x233a, (q15_t)0xc6d5, (q15_t)0x232e, (q15_t)0xc6db, (q15_t)0x2323, (q15_t)0xc6e1, (q15_t)0x2318, (q15_t)0xc6e6, + (q15_t)0x230d, (q15_t)0xc6ec, (q15_t)0x2301, (q15_t)0xc6f2, (q15_t)0x22f6, (q15_t)0xc6f7, (q15_t)0x22eb, (q15_t)0xc6fd, + (q15_t)0x22e0, (q15_t)0xc703, (q15_t)0x22d5, (q15_t)0xc709, (q15_t)0x22ca, (q15_t)0xc70e, (q15_t)0x22be, (q15_t)0xc714, + (q15_t)0x22b3, (q15_t)0xc71a, (q15_t)0x22a8, (q15_t)0xc720, (q15_t)0x229d, (q15_t)0xc725, (q15_t)0x2292, (q15_t)0xc72b, + (q15_t)0x2287, (q15_t)0xc731, (q15_t)0x227b, (q15_t)0xc737, (q15_t)0x2270, (q15_t)0xc73d, (q15_t)0x2265, (q15_t)0xc742, + (q15_t)0x225a, (q15_t)0xc748, (q15_t)0x224f, (q15_t)0xc74e, (q15_t)0x2244, (q15_t)0xc754, (q15_t)0x2239, (q15_t)0xc75a, + (q15_t)0x222d, (q15_t)0xc75f, (q15_t)0x2222, (q15_t)0xc765, (q15_t)0x2217, (q15_t)0xc76b, (q15_t)0x220c, (q15_t)0xc771, + (q15_t)0x2201, (q15_t)0xc777, (q15_t)0x21f6, (q15_t)0xc77d, (q15_t)0x21eb, (q15_t)0xc783, (q15_t)0x21e0, (q15_t)0xc789, + (q15_t)0x21d5, (q15_t)0xc78f, (q15_t)0x21ca, (q15_t)0xc795, (q15_t)0x21be, (q15_t)0xc79a, (q15_t)0x21b3, (q15_t)0xc7a0, + (q15_t)0x21a8, (q15_t)0xc7a6, (q15_t)0x219d, (q15_t)0xc7ac, (q15_t)0x2192, (q15_t)0xc7b2, (q15_t)0x2187, (q15_t)0xc7b8, + (q15_t)0x217c, (q15_t)0xc7be, (q15_t)0x2171, (q15_t)0xc7c4, (q15_t)0x2166, (q15_t)0xc7ca, (q15_t)0x215b, (q15_t)0xc7d0, + (q15_t)0x2150, (q15_t)0xc7d6, (q15_t)0x2145, (q15_t)0xc7dc, (q15_t)0x213a, (q15_t)0xc7e2, (q15_t)0x212f, (q15_t)0xc7e8, + (q15_t)0x2124, (q15_t)0xc7ee, (q15_t)0x2119, (q15_t)0xc7f5, (q15_t)0x210e, (q15_t)0xc7fb, (q15_t)0x2103, (q15_t)0xc801, + (q15_t)0x20f8, (q15_t)0xc807, (q15_t)0x20ed, (q15_t)0xc80d, (q15_t)0x20e2, (q15_t)0xc813, (q15_t)0x20d7, (q15_t)0xc819, + (q15_t)0x20cc, (q15_t)0xc81f, (q15_t)0x20c1, (q15_t)0xc825, (q15_t)0x20b6, (q15_t)0xc82b, (q15_t)0x20ab, (q15_t)0xc832, + (q15_t)0x20a0, (q15_t)0xc838, (q15_t)0x2095, (q15_t)0xc83e, (q15_t)0x208a, (q15_t)0xc844, (q15_t)0x207f, (q15_t)0xc84a, + (q15_t)0x2074, (q15_t)0xc850, (q15_t)0x2069, (q15_t)0xc857, (q15_t)0x205e, (q15_t)0xc85d, (q15_t)0x2054, (q15_t)0xc863, + (q15_t)0x2049, (q15_t)0xc869, (q15_t)0x203e, (q15_t)0xc870, (q15_t)0x2033, (q15_t)0xc876, (q15_t)0x2028, (q15_t)0xc87c, + (q15_t)0x201d, (q15_t)0xc882, (q15_t)0x2012, (q15_t)0xc889, (q15_t)0x2007, (q15_t)0xc88f, (q15_t)0x1ffc, (q15_t)0xc895, + (q15_t)0x1ff1, (q15_t)0xc89b, (q15_t)0x1fe7, (q15_t)0xc8a2, (q15_t)0x1fdc, (q15_t)0xc8a8, (q15_t)0x1fd1, (q15_t)0xc8ae, + (q15_t)0x1fc6, (q15_t)0xc8b5, (q15_t)0x1fbb, (q15_t)0xc8bb, (q15_t)0x1fb0, (q15_t)0xc8c1, (q15_t)0x1fa5, (q15_t)0xc8c8, + (q15_t)0x1f9b, (q15_t)0xc8ce, (q15_t)0x1f90, (q15_t)0xc8d4, (q15_t)0x1f85, (q15_t)0xc8db, (q15_t)0x1f7a, (q15_t)0xc8e1, + (q15_t)0x1f6f, (q15_t)0xc8e8, (q15_t)0x1f65, (q15_t)0xc8ee, (q15_t)0x1f5a, (q15_t)0xc8f4, (q15_t)0x1f4f, (q15_t)0xc8fb, + (q15_t)0x1f44, (q15_t)0xc901, (q15_t)0x1f39, (q15_t)0xc908, (q15_t)0x1f2f, (q15_t)0xc90e, (q15_t)0x1f24, (q15_t)0xc915, + (q15_t)0x1f19, (q15_t)0xc91b, (q15_t)0x1f0e, (q15_t)0xc921, (q15_t)0x1f03, (q15_t)0xc928, (q15_t)0x1ef9, (q15_t)0xc92e, + (q15_t)0x1eee, (q15_t)0xc935, (q15_t)0x1ee3, (q15_t)0xc93b, (q15_t)0x1ed8, (q15_t)0xc942, (q15_t)0x1ece, (q15_t)0xc948, + (q15_t)0x1ec3, (q15_t)0xc94f, (q15_t)0x1eb8, (q15_t)0xc955, (q15_t)0x1ead, (q15_t)0xc95c, (q15_t)0x1ea3, (q15_t)0xc963, + (q15_t)0x1e98, (q15_t)0xc969, (q15_t)0x1e8d, (q15_t)0xc970, (q15_t)0x1e83, (q15_t)0xc976, (q15_t)0x1e78, (q15_t)0xc97d, + (q15_t)0x1e6d, (q15_t)0xc983, (q15_t)0x1e62, (q15_t)0xc98a, (q15_t)0x1e58, (q15_t)0xc991, (q15_t)0x1e4d, (q15_t)0xc997, + (q15_t)0x1e42, (q15_t)0xc99e, (q15_t)0x1e38, (q15_t)0xc9a4, (q15_t)0x1e2d, (q15_t)0xc9ab, (q15_t)0x1e22, (q15_t)0xc9b2, + (q15_t)0x1e18, (q15_t)0xc9b8, (q15_t)0x1e0d, (q15_t)0xc9bf, (q15_t)0x1e02, (q15_t)0xc9c6, (q15_t)0x1df8, (q15_t)0xc9cc, + (q15_t)0x1ded, (q15_t)0xc9d3, (q15_t)0x1de2, (q15_t)0xc9da, (q15_t)0x1dd8, (q15_t)0xc9e0, (q15_t)0x1dcd, (q15_t)0xc9e7, + (q15_t)0x1dc3, (q15_t)0xc9ee, (q15_t)0x1db8, (q15_t)0xc9f5, (q15_t)0x1dad, (q15_t)0xc9fb, (q15_t)0x1da3, (q15_t)0xca02, + (q15_t)0x1d98, (q15_t)0xca09, (q15_t)0x1d8e, (q15_t)0xca10, (q15_t)0x1d83, (q15_t)0xca16, (q15_t)0x1d78, (q15_t)0xca1d, + (q15_t)0x1d6e, (q15_t)0xca24, (q15_t)0x1d63, (q15_t)0xca2b, (q15_t)0x1d59, (q15_t)0xca32, (q15_t)0x1d4e, (q15_t)0xca38, + (q15_t)0x1d44, (q15_t)0xca3f, (q15_t)0x1d39, (q15_t)0xca46, (q15_t)0x1d2e, (q15_t)0xca4d, (q15_t)0x1d24, (q15_t)0xca54, + (q15_t)0x1d19, (q15_t)0xca5b, (q15_t)0x1d0f, (q15_t)0xca61, (q15_t)0x1d04, (q15_t)0xca68, (q15_t)0x1cfa, (q15_t)0xca6f, + (q15_t)0x1cef, (q15_t)0xca76, (q15_t)0x1ce5, (q15_t)0xca7d, (q15_t)0x1cda, (q15_t)0xca84, (q15_t)0x1cd0, (q15_t)0xca8b, + (q15_t)0x1cc5, (q15_t)0xca92, (q15_t)0x1cbb, (q15_t)0xca99, (q15_t)0x1cb0, (q15_t)0xca9f, (q15_t)0x1ca6, (q15_t)0xcaa6, + (q15_t)0x1c9b, (q15_t)0xcaad, (q15_t)0x1c91, (q15_t)0xcab4, (q15_t)0x1c86, (q15_t)0xcabb, (q15_t)0x1c7c, (q15_t)0xcac2, + (q15_t)0x1c72, (q15_t)0xcac9, (q15_t)0x1c67, (q15_t)0xcad0, (q15_t)0x1c5d, (q15_t)0xcad7, (q15_t)0x1c52, (q15_t)0xcade, + (q15_t)0x1c48, (q15_t)0xcae5, (q15_t)0x1c3d, (q15_t)0xcaec, (q15_t)0x1c33, (q15_t)0xcaf3, (q15_t)0x1c29, (q15_t)0xcafa, + (q15_t)0x1c1e, (q15_t)0xcb01, (q15_t)0x1c14, (q15_t)0xcb08, (q15_t)0x1c09, (q15_t)0xcb0f, (q15_t)0x1bff, (q15_t)0xcb16, + (q15_t)0x1bf5, (q15_t)0xcb1e, (q15_t)0x1bea, (q15_t)0xcb25, (q15_t)0x1be0, (q15_t)0xcb2c, (q15_t)0x1bd5, (q15_t)0xcb33, + (q15_t)0x1bcb, (q15_t)0xcb3a, (q15_t)0x1bc1, (q15_t)0xcb41, (q15_t)0x1bb6, (q15_t)0xcb48, (q15_t)0x1bac, (q15_t)0xcb4f, + (q15_t)0x1ba2, (q15_t)0xcb56, (q15_t)0x1b97, (q15_t)0xcb5e, (q15_t)0x1b8d, (q15_t)0xcb65, (q15_t)0x1b83, (q15_t)0xcb6c, + (q15_t)0x1b78, (q15_t)0xcb73, (q15_t)0x1b6e, (q15_t)0xcb7a, (q15_t)0x1b64, (q15_t)0xcb81, (q15_t)0x1b59, (q15_t)0xcb89, + (q15_t)0x1b4f, (q15_t)0xcb90, (q15_t)0x1b45, (q15_t)0xcb97, (q15_t)0x1b3b, (q15_t)0xcb9e, (q15_t)0x1b30, (q15_t)0xcba5, + (q15_t)0x1b26, (q15_t)0xcbad, (q15_t)0x1b1c, (q15_t)0xcbb4, (q15_t)0x1b11, (q15_t)0xcbbb, (q15_t)0x1b07, (q15_t)0xcbc2, + (q15_t)0x1afd, (q15_t)0xcbca, (q15_t)0x1af3, (q15_t)0xcbd1, (q15_t)0x1ae8, (q15_t)0xcbd8, (q15_t)0x1ade, (q15_t)0xcbe0, + (q15_t)0x1ad4, (q15_t)0xcbe7, (q15_t)0x1aca, (q15_t)0xcbee, (q15_t)0x1abf, (q15_t)0xcbf5, (q15_t)0x1ab5, (q15_t)0xcbfd, + (q15_t)0x1aab, (q15_t)0xcc04, (q15_t)0x1aa1, (q15_t)0xcc0b, (q15_t)0x1a97, (q15_t)0xcc13, (q15_t)0x1a8c, (q15_t)0xcc1a, + (q15_t)0x1a82, (q15_t)0xcc21, (q15_t)0x1a78, (q15_t)0xcc29, (q15_t)0x1a6e, (q15_t)0xcc30, (q15_t)0x1a64, (q15_t)0xcc38, + (q15_t)0x1a5a, (q15_t)0xcc3f, (q15_t)0x1a4f, (q15_t)0xcc46, (q15_t)0x1a45, (q15_t)0xcc4e, (q15_t)0x1a3b, (q15_t)0xcc55, + (q15_t)0x1a31, (q15_t)0xcc5d, (q15_t)0x1a27, (q15_t)0xcc64, (q15_t)0x1a1d, (q15_t)0xcc6b, (q15_t)0x1a13, (q15_t)0xcc73, + (q15_t)0x1a08, (q15_t)0xcc7a, (q15_t)0x19fe, (q15_t)0xcc82, (q15_t)0x19f4, (q15_t)0xcc89, (q15_t)0x19ea, (q15_t)0xcc91, + (q15_t)0x19e0, (q15_t)0xcc98, (q15_t)0x19d6, (q15_t)0xcca0, (q15_t)0x19cc, (q15_t)0xcca7, (q15_t)0x19c2, (q15_t)0xccaf, + (q15_t)0x19b8, (q15_t)0xccb6, (q15_t)0x19ae, (q15_t)0xccbe, (q15_t)0x19a4, (q15_t)0xccc5, (q15_t)0x199a, (q15_t)0xcccd, + (q15_t)0x198f, (q15_t)0xccd4, (q15_t)0x1985, (q15_t)0xccdc, (q15_t)0x197b, (q15_t)0xcce3, (q15_t)0x1971, (q15_t)0xcceb, + (q15_t)0x1967, (q15_t)0xccf3, (q15_t)0x195d, (q15_t)0xccfa, (q15_t)0x1953, (q15_t)0xcd02, (q15_t)0x1949, (q15_t)0xcd09, + (q15_t)0x193f, (q15_t)0xcd11, (q15_t)0x1935, (q15_t)0xcd19, (q15_t)0x192b, (q15_t)0xcd20, (q15_t)0x1921, (q15_t)0xcd28, + (q15_t)0x1917, (q15_t)0xcd30, (q15_t)0x190d, (q15_t)0xcd37, (q15_t)0x1903, (q15_t)0xcd3f, (q15_t)0x18f9, (q15_t)0xcd46, + (q15_t)0x18ef, (q15_t)0xcd4e, (q15_t)0x18e6, (q15_t)0xcd56, (q15_t)0x18dc, (q15_t)0xcd5d, (q15_t)0x18d2, (q15_t)0xcd65, + (q15_t)0x18c8, (q15_t)0xcd6d, (q15_t)0x18be, (q15_t)0xcd75, (q15_t)0x18b4, (q15_t)0xcd7c, (q15_t)0x18aa, (q15_t)0xcd84, + (q15_t)0x18a0, (q15_t)0xcd8c, (q15_t)0x1896, (q15_t)0xcd93, (q15_t)0x188c, (q15_t)0xcd9b, (q15_t)0x1882, (q15_t)0xcda3, + (q15_t)0x1878, (q15_t)0xcdab, (q15_t)0x186f, (q15_t)0xcdb2, (q15_t)0x1865, (q15_t)0xcdba, (q15_t)0x185b, (q15_t)0xcdc2, + (q15_t)0x1851, (q15_t)0xcdca, (q15_t)0x1847, (q15_t)0xcdd2, (q15_t)0x183d, (q15_t)0xcdd9, (q15_t)0x1833, (q15_t)0xcde1, + (q15_t)0x182a, (q15_t)0xcde9, (q15_t)0x1820, (q15_t)0xcdf1, (q15_t)0x1816, (q15_t)0xcdf9, (q15_t)0x180c, (q15_t)0xce01, + (q15_t)0x1802, (q15_t)0xce08, (q15_t)0x17f8, (q15_t)0xce10, (q15_t)0x17ef, (q15_t)0xce18, (q15_t)0x17e5, (q15_t)0xce20, + (q15_t)0x17db, (q15_t)0xce28, (q15_t)0x17d1, (q15_t)0xce30, (q15_t)0x17c8, (q15_t)0xce38, (q15_t)0x17be, (q15_t)0xce40, + (q15_t)0x17b4, (q15_t)0xce47, (q15_t)0x17aa, (q15_t)0xce4f, (q15_t)0x17a0, (q15_t)0xce57, (q15_t)0x1797, (q15_t)0xce5f, + (q15_t)0x178d, (q15_t)0xce67, (q15_t)0x1783, (q15_t)0xce6f, (q15_t)0x177a, (q15_t)0xce77, (q15_t)0x1770, (q15_t)0xce7f, + (q15_t)0x1766, (q15_t)0xce87, (q15_t)0x175c, (q15_t)0xce8f, (q15_t)0x1753, (q15_t)0xce97, (q15_t)0x1749, (q15_t)0xce9f, + (q15_t)0x173f, (q15_t)0xcea7, (q15_t)0x1736, (q15_t)0xceaf, (q15_t)0x172c, (q15_t)0xceb7, (q15_t)0x1722, (q15_t)0xcebf, + (q15_t)0x1719, (q15_t)0xcec7, (q15_t)0x170f, (q15_t)0xcecf, (q15_t)0x1705, (q15_t)0xced7, (q15_t)0x16fc, (q15_t)0xcedf, + (q15_t)0x16f2, (q15_t)0xcee7, (q15_t)0x16e8, (q15_t)0xceef, (q15_t)0x16df, (q15_t)0xcef7, (q15_t)0x16d5, (q15_t)0xceff, + (q15_t)0x16cb, (q15_t)0xcf07, (q15_t)0x16c2, (q15_t)0xcf10, (q15_t)0x16b8, (q15_t)0xcf18, (q15_t)0x16af, (q15_t)0xcf20, + (q15_t)0x16a5, (q15_t)0xcf28, (q15_t)0x169b, (q15_t)0xcf30, (q15_t)0x1692, (q15_t)0xcf38, (q15_t)0x1688, (q15_t)0xcf40, + (q15_t)0x167f, (q15_t)0xcf48, (q15_t)0x1675, (q15_t)0xcf51, (q15_t)0x166c, (q15_t)0xcf59, (q15_t)0x1662, (q15_t)0xcf61, + (q15_t)0x1659, (q15_t)0xcf69, (q15_t)0x164f, (q15_t)0xcf71, (q15_t)0x1645, (q15_t)0xcf79, (q15_t)0x163c, (q15_t)0xcf82, + (q15_t)0x1632, (q15_t)0xcf8a, (q15_t)0x1629, (q15_t)0xcf92, (q15_t)0x161f, (q15_t)0xcf9a, (q15_t)0x1616, (q15_t)0xcfa3, + (q15_t)0x160c, (q15_t)0xcfab, (q15_t)0x1603, (q15_t)0xcfb3, (q15_t)0x15f9, (q15_t)0xcfbb, (q15_t)0x15f0, (q15_t)0xcfc4, + (q15_t)0x15e6, (q15_t)0xcfcc, (q15_t)0x15dd, (q15_t)0xcfd4, (q15_t)0x15d4, (q15_t)0xcfdc, (q15_t)0x15ca, (q15_t)0xcfe5, + (q15_t)0x15c1, (q15_t)0xcfed, (q15_t)0x15b7, (q15_t)0xcff5, (q15_t)0x15ae, (q15_t)0xcffe, (q15_t)0x15a4, (q15_t)0xd006, + (q15_t)0x159b, (q15_t)0xd00e, (q15_t)0x1592, (q15_t)0xd016, (q15_t)0x1588, (q15_t)0xd01f, (q15_t)0x157f, (q15_t)0xd027, + (q15_t)0x1575, (q15_t)0xd030, (q15_t)0x156c, (q15_t)0xd038, (q15_t)0x1563, (q15_t)0xd040, (q15_t)0x1559, (q15_t)0xd049, + (q15_t)0x1550, (q15_t)0xd051, (q15_t)0x1547, (q15_t)0xd059, (q15_t)0x153d, (q15_t)0xd062, (q15_t)0x1534, (q15_t)0xd06a, + (q15_t)0x152a, (q15_t)0xd073, (q15_t)0x1521, (q15_t)0xd07b, (q15_t)0x1518, (q15_t)0xd083, (q15_t)0x150e, (q15_t)0xd08c, + (q15_t)0x1505, (q15_t)0xd094, (q15_t)0x14fc, (q15_t)0xd09d, (q15_t)0x14f3, (q15_t)0xd0a5, (q15_t)0x14e9, (q15_t)0xd0ae, + (q15_t)0x14e0, (q15_t)0xd0b6, (q15_t)0x14d7, (q15_t)0xd0bf, (q15_t)0x14cd, (q15_t)0xd0c7, (q15_t)0x14c4, (q15_t)0xd0d0, + (q15_t)0x14bb, (q15_t)0xd0d8, (q15_t)0x14b2, (q15_t)0xd0e0, (q15_t)0x14a8, (q15_t)0xd0e9, (q15_t)0x149f, (q15_t)0xd0f2, + (q15_t)0x1496, (q15_t)0xd0fa, (q15_t)0x148d, (q15_t)0xd103, (q15_t)0x1483, (q15_t)0xd10b, (q15_t)0x147a, (q15_t)0xd114, + (q15_t)0x1471, (q15_t)0xd11c, (q15_t)0x1468, (q15_t)0xd125, (q15_t)0x145f, (q15_t)0xd12d, (q15_t)0x1455, (q15_t)0xd136, + (q15_t)0x144c, (q15_t)0xd13e, (q15_t)0x1443, (q15_t)0xd147, (q15_t)0x143a, (q15_t)0xd150, (q15_t)0x1431, (q15_t)0xd158, + (q15_t)0x1428, (q15_t)0xd161, (q15_t)0x141e, (q15_t)0xd169, (q15_t)0x1415, (q15_t)0xd172, (q15_t)0x140c, (q15_t)0xd17b, + (q15_t)0x1403, (q15_t)0xd183, (q15_t)0x13fa, (q15_t)0xd18c, (q15_t)0x13f1, (q15_t)0xd195, (q15_t)0x13e8, (q15_t)0xd19d, + (q15_t)0x13df, (q15_t)0xd1a6, (q15_t)0x13d5, (q15_t)0xd1af, (q15_t)0x13cc, (q15_t)0xd1b7, (q15_t)0x13c3, (q15_t)0xd1c0, + (q15_t)0x13ba, (q15_t)0xd1c9, (q15_t)0x13b1, (q15_t)0xd1d1, (q15_t)0x13a8, (q15_t)0xd1da, (q15_t)0x139f, (q15_t)0xd1e3, + (q15_t)0x1396, (q15_t)0xd1eb, (q15_t)0x138d, (q15_t)0xd1f4, (q15_t)0x1384, (q15_t)0xd1fd, (q15_t)0x137b, (q15_t)0xd206, + (q15_t)0x1372, (q15_t)0xd20e, (q15_t)0x1369, (q15_t)0xd217, (q15_t)0x1360, (q15_t)0xd220, (q15_t)0x1357, (q15_t)0xd229, + (q15_t)0x134e, (q15_t)0xd231, (q15_t)0x1345, (q15_t)0xd23a, (q15_t)0x133c, (q15_t)0xd243, (q15_t)0x1333, (q15_t)0xd24c, + (q15_t)0x132a, (q15_t)0xd255, (q15_t)0x1321, (q15_t)0xd25d, (q15_t)0x1318, (q15_t)0xd266, (q15_t)0x130f, (q15_t)0xd26f, + (q15_t)0x1306, (q15_t)0xd278, (q15_t)0x12fd, (q15_t)0xd281, (q15_t)0x12f4, (q15_t)0xd28a, (q15_t)0x12eb, (q15_t)0xd292, + (q15_t)0x12e2, (q15_t)0xd29b, (q15_t)0x12d9, (q15_t)0xd2a4, (q15_t)0x12d1, (q15_t)0xd2ad, (q15_t)0x12c8, (q15_t)0xd2b6, + (q15_t)0x12bf, (q15_t)0xd2bf, (q15_t)0x12b6, (q15_t)0xd2c8, (q15_t)0x12ad, (q15_t)0xd2d1, (q15_t)0x12a4, (q15_t)0xd2d9, + (q15_t)0x129b, (q15_t)0xd2e2, (q15_t)0x1292, (q15_t)0xd2eb, (q15_t)0x128a, (q15_t)0xd2f4, (q15_t)0x1281, (q15_t)0xd2fd, + (q15_t)0x1278, (q15_t)0xd306, (q15_t)0x126f, (q15_t)0xd30f, (q15_t)0x1266, (q15_t)0xd318, (q15_t)0x125d, (q15_t)0xd321, + (q15_t)0x1255, (q15_t)0xd32a, (q15_t)0x124c, (q15_t)0xd333, (q15_t)0x1243, (q15_t)0xd33c, (q15_t)0x123a, (q15_t)0xd345, + (q15_t)0x1231, (q15_t)0xd34e, (q15_t)0x1229, (q15_t)0xd357, (q15_t)0x1220, (q15_t)0xd360, (q15_t)0x1217, (q15_t)0xd369, + (q15_t)0x120e, (q15_t)0xd372, (q15_t)0x1206, (q15_t)0xd37b, (q15_t)0x11fd, (q15_t)0xd384, (q15_t)0x11f4, (q15_t)0xd38d, + (q15_t)0x11eb, (q15_t)0xd396, (q15_t)0x11e3, (q15_t)0xd39f, (q15_t)0x11da, (q15_t)0xd3a8, (q15_t)0x11d1, (q15_t)0xd3b1, + (q15_t)0x11c9, (q15_t)0xd3ba, (q15_t)0x11c0, (q15_t)0xd3c3, (q15_t)0x11b7, (q15_t)0xd3cc, (q15_t)0x11af, (q15_t)0xd3d5, + (q15_t)0x11a6, (q15_t)0xd3df, (q15_t)0x119d, (q15_t)0xd3e8, (q15_t)0x1195, (q15_t)0xd3f1, (q15_t)0x118c, (q15_t)0xd3fa, + (q15_t)0x1183, (q15_t)0xd403, (q15_t)0x117b, (q15_t)0xd40c, (q15_t)0x1172, (q15_t)0xd415, (q15_t)0x1169, (q15_t)0xd41e, + (q15_t)0x1161, (q15_t)0xd428, (q15_t)0x1158, (q15_t)0xd431, (q15_t)0x1150, (q15_t)0xd43a, (q15_t)0x1147, (q15_t)0xd443, + (q15_t)0x113e, (q15_t)0xd44c, (q15_t)0x1136, (q15_t)0xd455, (q15_t)0x112d, (q15_t)0xd45f, (q15_t)0x1125, (q15_t)0xd468, + (q15_t)0x111c, (q15_t)0xd471, (q15_t)0x1114, (q15_t)0xd47a, (q15_t)0x110b, (q15_t)0xd483, (q15_t)0x1103, (q15_t)0xd48d, + (q15_t)0x10fa, (q15_t)0xd496, (q15_t)0x10f2, (q15_t)0xd49f, (q15_t)0x10e9, (q15_t)0xd4a8, (q15_t)0x10e0, (q15_t)0xd4b2, + (q15_t)0x10d8, (q15_t)0xd4bb, (q15_t)0x10d0, (q15_t)0xd4c4, (q15_t)0x10c7, (q15_t)0xd4cd, (q15_t)0x10bf, (q15_t)0xd4d7, + (q15_t)0x10b6, (q15_t)0xd4e0, (q15_t)0x10ae, (q15_t)0xd4e9, (q15_t)0x10a5, (q15_t)0xd4f3, (q15_t)0x109d, (q15_t)0xd4fc, + (q15_t)0x1094, (q15_t)0xd505, (q15_t)0x108c, (q15_t)0xd50e, (q15_t)0x1083, (q15_t)0xd518, (q15_t)0x107b, (q15_t)0xd521, + (q15_t)0x1073, (q15_t)0xd52a, (q15_t)0x106a, (q15_t)0xd534, (q15_t)0x1062, (q15_t)0xd53d, (q15_t)0x1059, (q15_t)0xd547, + (q15_t)0x1051, (q15_t)0xd550, (q15_t)0x1049, (q15_t)0xd559, (q15_t)0x1040, (q15_t)0xd563, (q15_t)0x1038, (q15_t)0xd56c, + (q15_t)0x1030, (q15_t)0xd575, (q15_t)0x1027, (q15_t)0xd57f, (q15_t)0x101f, (q15_t)0xd588, (q15_t)0x1016, (q15_t)0xd592, + (q15_t)0x100e, (q15_t)0xd59b, (q15_t)0x1006, (q15_t)0xd5a4, (q15_t)0xffe, (q15_t)0xd5ae, (q15_t)0xff5, (q15_t)0xd5b7, + (q15_t)0xfed, (q15_t)0xd5c1, (q15_t)0xfe5, (q15_t)0xd5ca, (q15_t)0xfdc, (q15_t)0xd5d4, (q15_t)0xfd4, (q15_t)0xd5dd, + (q15_t)0xfcc, (q15_t)0xd5e6, (q15_t)0xfc4, (q15_t)0xd5f0, (q15_t)0xfbb, (q15_t)0xd5f9, (q15_t)0xfb3, (q15_t)0xd603, + (q15_t)0xfab, (q15_t)0xd60c, (q15_t)0xfa3, (q15_t)0xd616, (q15_t)0xf9a, (q15_t)0xd61f, (q15_t)0xf92, (q15_t)0xd629, + (q15_t)0xf8a, (q15_t)0xd632, (q15_t)0xf82, (q15_t)0xd63c, (q15_t)0xf79, (q15_t)0xd645, (q15_t)0xf71, (q15_t)0xd64f, + (q15_t)0xf69, (q15_t)0xd659, (q15_t)0xf61, (q15_t)0xd662, (q15_t)0xf59, (q15_t)0xd66c, (q15_t)0xf51, (q15_t)0xd675, + (q15_t)0xf48, (q15_t)0xd67f, (q15_t)0xf40, (q15_t)0xd688, (q15_t)0xf38, (q15_t)0xd692, (q15_t)0xf30, (q15_t)0xd69b, + (q15_t)0xf28, (q15_t)0xd6a5, (q15_t)0xf20, (q15_t)0xd6af, (q15_t)0xf18, (q15_t)0xd6b8, (q15_t)0xf10, (q15_t)0xd6c2, + (q15_t)0xf07, (q15_t)0xd6cb, (q15_t)0xeff, (q15_t)0xd6d5, (q15_t)0xef7, (q15_t)0xd6df, (q15_t)0xeef, (q15_t)0xd6e8, + (q15_t)0xee7, (q15_t)0xd6f2, (q15_t)0xedf, (q15_t)0xd6fc, (q15_t)0xed7, (q15_t)0xd705, (q15_t)0xecf, (q15_t)0xd70f, + (q15_t)0xec7, (q15_t)0xd719, (q15_t)0xebf, (q15_t)0xd722, (q15_t)0xeb7, (q15_t)0xd72c, (q15_t)0xeaf, (q15_t)0xd736, + (q15_t)0xea7, (q15_t)0xd73f, (q15_t)0xe9f, (q15_t)0xd749, (q15_t)0xe97, (q15_t)0xd753, (q15_t)0xe8f, (q15_t)0xd75c, + (q15_t)0xe87, (q15_t)0xd766, (q15_t)0xe7f, (q15_t)0xd770, (q15_t)0xe77, (q15_t)0xd77a, (q15_t)0xe6f, (q15_t)0xd783, + (q15_t)0xe67, (q15_t)0xd78d, (q15_t)0xe5f, (q15_t)0xd797, (q15_t)0xe57, (q15_t)0xd7a0, (q15_t)0xe4f, (q15_t)0xd7aa, + (q15_t)0xe47, (q15_t)0xd7b4, (q15_t)0xe40, (q15_t)0xd7be, (q15_t)0xe38, (q15_t)0xd7c8, (q15_t)0xe30, (q15_t)0xd7d1, + (q15_t)0xe28, (q15_t)0xd7db, (q15_t)0xe20, (q15_t)0xd7e5, (q15_t)0xe18, (q15_t)0xd7ef, (q15_t)0xe10, (q15_t)0xd7f8, + (q15_t)0xe08, (q15_t)0xd802, (q15_t)0xe01, (q15_t)0xd80c, (q15_t)0xdf9, (q15_t)0xd816, (q15_t)0xdf1, (q15_t)0xd820, + (q15_t)0xde9, (q15_t)0xd82a, (q15_t)0xde1, (q15_t)0xd833, (q15_t)0xdd9, (q15_t)0xd83d, (q15_t)0xdd2, (q15_t)0xd847, + (q15_t)0xdca, (q15_t)0xd851, (q15_t)0xdc2, (q15_t)0xd85b, (q15_t)0xdba, (q15_t)0xd865, (q15_t)0xdb2, (q15_t)0xd86f, + (q15_t)0xdab, (q15_t)0xd878, (q15_t)0xda3, (q15_t)0xd882, (q15_t)0xd9b, (q15_t)0xd88c, (q15_t)0xd93, (q15_t)0xd896, + (q15_t)0xd8c, (q15_t)0xd8a0, (q15_t)0xd84, (q15_t)0xd8aa, (q15_t)0xd7c, (q15_t)0xd8b4, (q15_t)0xd75, (q15_t)0xd8be, + (q15_t)0xd6d, (q15_t)0xd8c8, (q15_t)0xd65, (q15_t)0xd8d2, (q15_t)0xd5d, (q15_t)0xd8dc, (q15_t)0xd56, (q15_t)0xd8e6, + (q15_t)0xd4e, (q15_t)0xd8ef, (q15_t)0xd46, (q15_t)0xd8f9, (q15_t)0xd3f, (q15_t)0xd903, (q15_t)0xd37, (q15_t)0xd90d, + (q15_t)0xd30, (q15_t)0xd917, (q15_t)0xd28, (q15_t)0xd921, (q15_t)0xd20, (q15_t)0xd92b, (q15_t)0xd19, (q15_t)0xd935, + (q15_t)0xd11, (q15_t)0xd93f, (q15_t)0xd09, (q15_t)0xd949, (q15_t)0xd02, (q15_t)0xd953, (q15_t)0xcfa, (q15_t)0xd95d, + (q15_t)0xcf3, (q15_t)0xd967, (q15_t)0xceb, (q15_t)0xd971, (q15_t)0xce3, (q15_t)0xd97b, (q15_t)0xcdc, (q15_t)0xd985, + (q15_t)0xcd4, (q15_t)0xd98f, (q15_t)0xccd, (q15_t)0xd99a, (q15_t)0xcc5, (q15_t)0xd9a4, (q15_t)0xcbe, (q15_t)0xd9ae, + (q15_t)0xcb6, (q15_t)0xd9b8, (q15_t)0xcaf, (q15_t)0xd9c2, (q15_t)0xca7, (q15_t)0xd9cc, (q15_t)0xca0, (q15_t)0xd9d6, + (q15_t)0xc98, (q15_t)0xd9e0, (q15_t)0xc91, (q15_t)0xd9ea, (q15_t)0xc89, (q15_t)0xd9f4, (q15_t)0xc82, (q15_t)0xd9fe, + (q15_t)0xc7a, (q15_t)0xda08, (q15_t)0xc73, (q15_t)0xda13, (q15_t)0xc6b, (q15_t)0xda1d, (q15_t)0xc64, (q15_t)0xda27, + (q15_t)0xc5d, (q15_t)0xda31, (q15_t)0xc55, (q15_t)0xda3b, (q15_t)0xc4e, (q15_t)0xda45, (q15_t)0xc46, (q15_t)0xda4f, + (q15_t)0xc3f, (q15_t)0xda5a, (q15_t)0xc38, (q15_t)0xda64, (q15_t)0xc30, (q15_t)0xda6e, (q15_t)0xc29, (q15_t)0xda78, + (q15_t)0xc21, (q15_t)0xda82, (q15_t)0xc1a, (q15_t)0xda8c, (q15_t)0xc13, (q15_t)0xda97, (q15_t)0xc0b, (q15_t)0xdaa1, + (q15_t)0xc04, (q15_t)0xdaab, (q15_t)0xbfd, (q15_t)0xdab5, (q15_t)0xbf5, (q15_t)0xdabf, (q15_t)0xbee, (q15_t)0xdaca, + (q15_t)0xbe7, (q15_t)0xdad4, (q15_t)0xbe0, (q15_t)0xdade, (q15_t)0xbd8, (q15_t)0xdae8, (q15_t)0xbd1, (q15_t)0xdaf3, + (q15_t)0xbca, (q15_t)0xdafd, (q15_t)0xbc2, (q15_t)0xdb07, (q15_t)0xbbb, (q15_t)0xdb11, (q15_t)0xbb4, (q15_t)0xdb1c, + (q15_t)0xbad, (q15_t)0xdb26, (q15_t)0xba5, (q15_t)0xdb30, (q15_t)0xb9e, (q15_t)0xdb3b, (q15_t)0xb97, (q15_t)0xdb45, + (q15_t)0xb90, (q15_t)0xdb4f, (q15_t)0xb89, (q15_t)0xdb59, (q15_t)0xb81, (q15_t)0xdb64, (q15_t)0xb7a, (q15_t)0xdb6e, + (q15_t)0xb73, (q15_t)0xdb78, (q15_t)0xb6c, (q15_t)0xdb83, (q15_t)0xb65, (q15_t)0xdb8d, (q15_t)0xb5e, (q15_t)0xdb97, + (q15_t)0xb56, (q15_t)0xdba2, (q15_t)0xb4f, (q15_t)0xdbac, (q15_t)0xb48, (q15_t)0xdbb6, (q15_t)0xb41, (q15_t)0xdbc1, + (q15_t)0xb3a, (q15_t)0xdbcb, (q15_t)0xb33, (q15_t)0xdbd5, (q15_t)0xb2c, (q15_t)0xdbe0, (q15_t)0xb25, (q15_t)0xdbea, + (q15_t)0xb1e, (q15_t)0xdbf5, (q15_t)0xb16, (q15_t)0xdbff, (q15_t)0xb0f, (q15_t)0xdc09, (q15_t)0xb08, (q15_t)0xdc14, + (q15_t)0xb01, (q15_t)0xdc1e, (q15_t)0xafa, (q15_t)0xdc29, (q15_t)0xaf3, (q15_t)0xdc33, (q15_t)0xaec, (q15_t)0xdc3d, + (q15_t)0xae5, (q15_t)0xdc48, (q15_t)0xade, (q15_t)0xdc52, (q15_t)0xad7, (q15_t)0xdc5d, (q15_t)0xad0, (q15_t)0xdc67, + (q15_t)0xac9, (q15_t)0xdc72, (q15_t)0xac2, (q15_t)0xdc7c, (q15_t)0xabb, (q15_t)0xdc86, (q15_t)0xab4, (q15_t)0xdc91, + (q15_t)0xaad, (q15_t)0xdc9b, (q15_t)0xaa6, (q15_t)0xdca6, (q15_t)0xa9f, (q15_t)0xdcb0, (q15_t)0xa99, (q15_t)0xdcbb, + (q15_t)0xa92, (q15_t)0xdcc5, (q15_t)0xa8b, (q15_t)0xdcd0, (q15_t)0xa84, (q15_t)0xdcda, (q15_t)0xa7d, (q15_t)0xdce5, + (q15_t)0xa76, (q15_t)0xdcef, (q15_t)0xa6f, (q15_t)0xdcfa, (q15_t)0xa68, (q15_t)0xdd04, (q15_t)0xa61, (q15_t)0xdd0f, + (q15_t)0xa5b, (q15_t)0xdd19, (q15_t)0xa54, (q15_t)0xdd24, (q15_t)0xa4d, (q15_t)0xdd2e, (q15_t)0xa46, (q15_t)0xdd39, + (q15_t)0xa3f, (q15_t)0xdd44, (q15_t)0xa38, (q15_t)0xdd4e, (q15_t)0xa32, (q15_t)0xdd59, (q15_t)0xa2b, (q15_t)0xdd63, + (q15_t)0xa24, (q15_t)0xdd6e, (q15_t)0xa1d, (q15_t)0xdd78, (q15_t)0xa16, (q15_t)0xdd83, (q15_t)0xa10, (q15_t)0xdd8e, + (q15_t)0xa09, (q15_t)0xdd98, (q15_t)0xa02, (q15_t)0xdda3, (q15_t)0x9fb, (q15_t)0xddad, (q15_t)0x9f5, (q15_t)0xddb8, + (q15_t)0x9ee, (q15_t)0xddc3, (q15_t)0x9e7, (q15_t)0xddcd, (q15_t)0x9e0, (q15_t)0xddd8, (q15_t)0x9da, (q15_t)0xdde2, + (q15_t)0x9d3, (q15_t)0xdded, (q15_t)0x9cc, (q15_t)0xddf8, (q15_t)0x9c6, (q15_t)0xde02, (q15_t)0x9bf, (q15_t)0xde0d, + (q15_t)0x9b8, (q15_t)0xde18, (q15_t)0x9b2, (q15_t)0xde22, (q15_t)0x9ab, (q15_t)0xde2d, (q15_t)0x9a4, (q15_t)0xde38, + (q15_t)0x99e, (q15_t)0xde42, (q15_t)0x997, (q15_t)0xde4d, (q15_t)0x991, (q15_t)0xde58, (q15_t)0x98a, (q15_t)0xde62, + (q15_t)0x983, (q15_t)0xde6d, (q15_t)0x97d, (q15_t)0xde78, (q15_t)0x976, (q15_t)0xde83, (q15_t)0x970, (q15_t)0xde8d, + (q15_t)0x969, (q15_t)0xde98, (q15_t)0x963, (q15_t)0xdea3, (q15_t)0x95c, (q15_t)0xdead, (q15_t)0x955, (q15_t)0xdeb8, + (q15_t)0x94f, (q15_t)0xdec3, (q15_t)0x948, (q15_t)0xdece, (q15_t)0x942, (q15_t)0xded8, (q15_t)0x93b, (q15_t)0xdee3, + (q15_t)0x935, (q15_t)0xdeee, (q15_t)0x92e, (q15_t)0xdef9, (q15_t)0x928, (q15_t)0xdf03, (q15_t)0x921, (q15_t)0xdf0e, + (q15_t)0x91b, (q15_t)0xdf19, (q15_t)0x915, (q15_t)0xdf24, (q15_t)0x90e, (q15_t)0xdf2f, (q15_t)0x908, (q15_t)0xdf39, + (q15_t)0x901, (q15_t)0xdf44, (q15_t)0x8fb, (q15_t)0xdf4f, (q15_t)0x8f4, (q15_t)0xdf5a, (q15_t)0x8ee, (q15_t)0xdf65, + (q15_t)0x8e8, (q15_t)0xdf6f, (q15_t)0x8e1, (q15_t)0xdf7a, (q15_t)0x8db, (q15_t)0xdf85, (q15_t)0x8d4, (q15_t)0xdf90, + (q15_t)0x8ce, (q15_t)0xdf9b, (q15_t)0x8c8, (q15_t)0xdfa5, (q15_t)0x8c1, (q15_t)0xdfb0, (q15_t)0x8bb, (q15_t)0xdfbb, + (q15_t)0x8b5, (q15_t)0xdfc6, (q15_t)0x8ae, (q15_t)0xdfd1, (q15_t)0x8a8, (q15_t)0xdfdc, (q15_t)0x8a2, (q15_t)0xdfe7, + (q15_t)0x89b, (q15_t)0xdff1, (q15_t)0x895, (q15_t)0xdffc, (q15_t)0x88f, (q15_t)0xe007, (q15_t)0x889, (q15_t)0xe012, + (q15_t)0x882, (q15_t)0xe01d, (q15_t)0x87c, (q15_t)0xe028, (q15_t)0x876, (q15_t)0xe033, (q15_t)0x870, (q15_t)0xe03e, + (q15_t)0x869, (q15_t)0xe049, (q15_t)0x863, (q15_t)0xe054, (q15_t)0x85d, (q15_t)0xe05e, (q15_t)0x857, (q15_t)0xe069, + (q15_t)0x850, (q15_t)0xe074, (q15_t)0x84a, (q15_t)0xe07f, (q15_t)0x844, (q15_t)0xe08a, (q15_t)0x83e, (q15_t)0xe095, + (q15_t)0x838, (q15_t)0xe0a0, (q15_t)0x832, (q15_t)0xe0ab, (q15_t)0x82b, (q15_t)0xe0b6, (q15_t)0x825, (q15_t)0xe0c1, + (q15_t)0x81f, (q15_t)0xe0cc, (q15_t)0x819, (q15_t)0xe0d7, (q15_t)0x813, (q15_t)0xe0e2, (q15_t)0x80d, (q15_t)0xe0ed, + (q15_t)0x807, (q15_t)0xe0f8, (q15_t)0x801, (q15_t)0xe103, (q15_t)0x7fb, (q15_t)0xe10e, (q15_t)0x7f5, (q15_t)0xe119, + (q15_t)0x7ee, (q15_t)0xe124, (q15_t)0x7e8, (q15_t)0xe12f, (q15_t)0x7e2, (q15_t)0xe13a, (q15_t)0x7dc, (q15_t)0xe145, + (q15_t)0x7d6, (q15_t)0xe150, (q15_t)0x7d0, (q15_t)0xe15b, (q15_t)0x7ca, (q15_t)0xe166, (q15_t)0x7c4, (q15_t)0xe171, + (q15_t)0x7be, (q15_t)0xe17c, (q15_t)0x7b8, (q15_t)0xe187, (q15_t)0x7b2, (q15_t)0xe192, (q15_t)0x7ac, (q15_t)0xe19d, + (q15_t)0x7a6, (q15_t)0xe1a8, (q15_t)0x7a0, (q15_t)0xe1b3, (q15_t)0x79a, (q15_t)0xe1be, (q15_t)0x795, (q15_t)0xe1ca, + (q15_t)0x78f, (q15_t)0xe1d5, (q15_t)0x789, (q15_t)0xe1e0, (q15_t)0x783, (q15_t)0xe1eb, (q15_t)0x77d, (q15_t)0xe1f6, + (q15_t)0x777, (q15_t)0xe201, (q15_t)0x771, (q15_t)0xe20c, (q15_t)0x76b, (q15_t)0xe217, (q15_t)0x765, (q15_t)0xe222, + (q15_t)0x75f, (q15_t)0xe22d, (q15_t)0x75a, (q15_t)0xe239, (q15_t)0x754, (q15_t)0xe244, (q15_t)0x74e, (q15_t)0xe24f, + (q15_t)0x748, (q15_t)0xe25a, (q15_t)0x742, (q15_t)0xe265, (q15_t)0x73d, (q15_t)0xe270, (q15_t)0x737, (q15_t)0xe27b, + (q15_t)0x731, (q15_t)0xe287, (q15_t)0x72b, (q15_t)0xe292, (q15_t)0x725, (q15_t)0xe29d, (q15_t)0x720, (q15_t)0xe2a8, + (q15_t)0x71a, (q15_t)0xe2b3, (q15_t)0x714, (q15_t)0xe2be, (q15_t)0x70e, (q15_t)0xe2ca, (q15_t)0x709, (q15_t)0xe2d5, + (q15_t)0x703, (q15_t)0xe2e0, (q15_t)0x6fd, (q15_t)0xe2eb, (q15_t)0x6f7, (q15_t)0xe2f6, (q15_t)0x6f2, (q15_t)0xe301, + (q15_t)0x6ec, (q15_t)0xe30d, (q15_t)0x6e6, (q15_t)0xe318, (q15_t)0x6e1, (q15_t)0xe323, (q15_t)0x6db, (q15_t)0xe32e, + (q15_t)0x6d5, (q15_t)0xe33a, (q15_t)0x6d0, (q15_t)0xe345, (q15_t)0x6ca, (q15_t)0xe350, (q15_t)0x6c5, (q15_t)0xe35b, + (q15_t)0x6bf, (q15_t)0xe367, (q15_t)0x6b9, (q15_t)0xe372, (q15_t)0x6b4, (q15_t)0xe37d, (q15_t)0x6ae, (q15_t)0xe388, + (q15_t)0x6a8, (q15_t)0xe394, (q15_t)0x6a3, (q15_t)0xe39f, (q15_t)0x69d, (q15_t)0xe3aa, (q15_t)0x698, (q15_t)0xe3b5, + (q15_t)0x692, (q15_t)0xe3c1, (q15_t)0x68d, (q15_t)0xe3cc, (q15_t)0x687, (q15_t)0xe3d7, (q15_t)0x682, (q15_t)0xe3e2, + (q15_t)0x67c, (q15_t)0xe3ee, (q15_t)0x677, (q15_t)0xe3f9, (q15_t)0x671, (q15_t)0xe404, (q15_t)0x66c, (q15_t)0xe410, + (q15_t)0x666, (q15_t)0xe41b, (q15_t)0x661, (q15_t)0xe426, (q15_t)0x65b, (q15_t)0xe432, (q15_t)0x656, (q15_t)0xe43d, + (q15_t)0x650, (q15_t)0xe448, (q15_t)0x64b, (q15_t)0xe454, (q15_t)0x645, (q15_t)0xe45f, (q15_t)0x640, (q15_t)0xe46a, + (q15_t)0x63b, (q15_t)0xe476, (q15_t)0x635, (q15_t)0xe481, (q15_t)0x630, (q15_t)0xe48c, (q15_t)0x62a, (q15_t)0xe498, + (q15_t)0x625, (q15_t)0xe4a3, (q15_t)0x620, (q15_t)0xe4ae, (q15_t)0x61a, (q15_t)0xe4ba, (q15_t)0x615, (q15_t)0xe4c5, + (q15_t)0x610, (q15_t)0xe4d0, (q15_t)0x60a, (q15_t)0xe4dc, (q15_t)0x605, (q15_t)0xe4e7, (q15_t)0x600, (q15_t)0xe4f3, + (q15_t)0x5fa, (q15_t)0xe4fe, (q15_t)0x5f5, (q15_t)0xe509, (q15_t)0x5f0, (q15_t)0xe515, (q15_t)0x5ea, (q15_t)0xe520, + (q15_t)0x5e5, (q15_t)0xe52c, (q15_t)0x5e0, (q15_t)0xe537, (q15_t)0x5db, (q15_t)0xe542, (q15_t)0x5d5, (q15_t)0xe54e, + (q15_t)0x5d0, (q15_t)0xe559, (q15_t)0x5cb, (q15_t)0xe565, (q15_t)0x5c6, (q15_t)0xe570, (q15_t)0x5c1, (q15_t)0xe57c, + (q15_t)0x5bb, (q15_t)0xe587, (q15_t)0x5b6, (q15_t)0xe592, (q15_t)0x5b1, (q15_t)0xe59e, (q15_t)0x5ac, (q15_t)0xe5a9, + (q15_t)0x5a7, (q15_t)0xe5b5, (q15_t)0x5a1, (q15_t)0xe5c0, (q15_t)0x59c, (q15_t)0xe5cc, (q15_t)0x597, (q15_t)0xe5d7, + (q15_t)0x592, (q15_t)0xe5e3, (q15_t)0x58d, (q15_t)0xe5ee, (q15_t)0x588, (q15_t)0xe5fa, (q15_t)0x583, (q15_t)0xe605, + (q15_t)0x57e, (q15_t)0xe611, (q15_t)0x578, (q15_t)0xe61c, (q15_t)0x573, (q15_t)0xe628, (q15_t)0x56e, (q15_t)0xe633, + (q15_t)0x569, (q15_t)0xe63f, (q15_t)0x564, (q15_t)0xe64a, (q15_t)0x55f, (q15_t)0xe656, (q15_t)0x55a, (q15_t)0xe661, + (q15_t)0x555, (q15_t)0xe66d, (q15_t)0x550, (q15_t)0xe678, (q15_t)0x54b, (q15_t)0xe684, (q15_t)0x546, (q15_t)0xe68f, + (q15_t)0x541, (q15_t)0xe69b, (q15_t)0x53c, (q15_t)0xe6a6, (q15_t)0x537, (q15_t)0xe6b2, (q15_t)0x532, (q15_t)0xe6bd, + (q15_t)0x52d, (q15_t)0xe6c9, (q15_t)0x528, (q15_t)0xe6d4, (q15_t)0x523, (q15_t)0xe6e0, (q15_t)0x51e, (q15_t)0xe6ec, + (q15_t)0x51a, (q15_t)0xe6f7, (q15_t)0x515, (q15_t)0xe703, (q15_t)0x510, (q15_t)0xe70e, (q15_t)0x50b, (q15_t)0xe71a, + (q15_t)0x506, (q15_t)0xe725, (q15_t)0x501, (q15_t)0xe731, (q15_t)0x4fc, (q15_t)0xe73d, (q15_t)0x4f7, (q15_t)0xe748, + (q15_t)0x4f2, (q15_t)0xe754, (q15_t)0x4ee, (q15_t)0xe75f, (q15_t)0x4e9, (q15_t)0xe76b, (q15_t)0x4e4, (q15_t)0xe777, + (q15_t)0x4df, (q15_t)0xe782, (q15_t)0x4da, (q15_t)0xe78e, (q15_t)0x4d6, (q15_t)0xe799, (q15_t)0x4d1, (q15_t)0xe7a5, + (q15_t)0x4cc, (q15_t)0xe7b1, (q15_t)0x4c7, (q15_t)0xe7bc, (q15_t)0x4c2, (q15_t)0xe7c8, (q15_t)0x4be, (q15_t)0xe7d3, + (q15_t)0x4b9, (q15_t)0xe7df, (q15_t)0x4b4, (q15_t)0xe7eb, (q15_t)0x4b0, (q15_t)0xe7f6, (q15_t)0x4ab, (q15_t)0xe802, + (q15_t)0x4a6, (q15_t)0xe80e, (q15_t)0x4a1, (q15_t)0xe819, (q15_t)0x49d, (q15_t)0xe825, (q15_t)0x498, (q15_t)0xe831, + (q15_t)0x493, (q15_t)0xe83c, (q15_t)0x48f, (q15_t)0xe848, (q15_t)0x48a, (q15_t)0xe854, (q15_t)0x485, (q15_t)0xe85f, + (q15_t)0x481, (q15_t)0xe86b, (q15_t)0x47c, (q15_t)0xe877, (q15_t)0x478, (q15_t)0xe882, (q15_t)0x473, (q15_t)0xe88e, + (q15_t)0x46e, (q15_t)0xe89a, (q15_t)0x46a, (q15_t)0xe8a5, (q15_t)0x465, (q15_t)0xe8b1, (q15_t)0x461, (q15_t)0xe8bd, + (q15_t)0x45c, (q15_t)0xe8c9, (q15_t)0x457, (q15_t)0xe8d4, (q15_t)0x453, (q15_t)0xe8e0, (q15_t)0x44e, (q15_t)0xe8ec, + (q15_t)0x44a, (q15_t)0xe8f7, (q15_t)0x445, (q15_t)0xe903, (q15_t)0x441, (q15_t)0xe90f, (q15_t)0x43c, (q15_t)0xe91b, + (q15_t)0x438, (q15_t)0xe926, (q15_t)0x433, (q15_t)0xe932, (q15_t)0x42f, (q15_t)0xe93e, (q15_t)0x42a, (q15_t)0xe94a, + (q15_t)0x426, (q15_t)0xe955, (q15_t)0x422, (q15_t)0xe961, (q15_t)0x41d, (q15_t)0xe96d, (q15_t)0x419, (q15_t)0xe979, + (q15_t)0x414, (q15_t)0xe984, (q15_t)0x410, (q15_t)0xe990, (q15_t)0x40b, (q15_t)0xe99c, (q15_t)0x407, (q15_t)0xe9a8, + (q15_t)0x403, (q15_t)0xe9b4, (q15_t)0x3fe, (q15_t)0xe9bf, (q15_t)0x3fa, (q15_t)0xe9cb, (q15_t)0x3f6, (q15_t)0xe9d7, + (q15_t)0x3f1, (q15_t)0xe9e3, (q15_t)0x3ed, (q15_t)0xe9ee, (q15_t)0x3e9, (q15_t)0xe9fa, (q15_t)0x3e4, (q15_t)0xea06, + (q15_t)0x3e0, (q15_t)0xea12, (q15_t)0x3dc, (q15_t)0xea1e, (q15_t)0x3d7, (q15_t)0xea29, (q15_t)0x3d3, (q15_t)0xea35, + (q15_t)0x3cf, (q15_t)0xea41, (q15_t)0x3ca, (q15_t)0xea4d, (q15_t)0x3c6, (q15_t)0xea59, (q15_t)0x3c2, (q15_t)0xea65, + (q15_t)0x3be, (q15_t)0xea70, (q15_t)0x3ba, (q15_t)0xea7c, (q15_t)0x3b5, (q15_t)0xea88, (q15_t)0x3b1, (q15_t)0xea94, + (q15_t)0x3ad, (q15_t)0xeaa0, (q15_t)0x3a9, (q15_t)0xeaac, (q15_t)0x3a5, (q15_t)0xeab7, (q15_t)0x3a0, (q15_t)0xeac3, + (q15_t)0x39c, (q15_t)0xeacf, (q15_t)0x398, (q15_t)0xeadb, (q15_t)0x394, (q15_t)0xeae7, (q15_t)0x390, (q15_t)0xeaf3, + (q15_t)0x38c, (q15_t)0xeaff, (q15_t)0x387, (q15_t)0xeb0a, (q15_t)0x383, (q15_t)0xeb16, (q15_t)0x37f, (q15_t)0xeb22, + (q15_t)0x37b, (q15_t)0xeb2e, (q15_t)0x377, (q15_t)0xeb3a, (q15_t)0x373, (q15_t)0xeb46, (q15_t)0x36f, (q15_t)0xeb52, + (q15_t)0x36b, (q15_t)0xeb5e, (q15_t)0x367, (q15_t)0xeb6a, (q15_t)0x363, (q15_t)0xeb75, (q15_t)0x35f, (q15_t)0xeb81, + (q15_t)0x35b, (q15_t)0xeb8d, (q15_t)0x357, (q15_t)0xeb99, (q15_t)0x353, (q15_t)0xeba5, (q15_t)0x34f, (q15_t)0xebb1, + (q15_t)0x34b, (q15_t)0xebbd, (q15_t)0x347, (q15_t)0xebc9, (q15_t)0x343, (q15_t)0xebd5, (q15_t)0x33f, (q15_t)0xebe1, + (q15_t)0x33b, (q15_t)0xebed, (q15_t)0x337, (q15_t)0xebf9, (q15_t)0x333, (q15_t)0xec05, (q15_t)0x32f, (q15_t)0xec10, + (q15_t)0x32b, (q15_t)0xec1c, (q15_t)0x327, (q15_t)0xec28, (q15_t)0x323, (q15_t)0xec34, (q15_t)0x320, (q15_t)0xec40, + (q15_t)0x31c, (q15_t)0xec4c, (q15_t)0x318, (q15_t)0xec58, (q15_t)0x314, (q15_t)0xec64, (q15_t)0x310, (q15_t)0xec70, + (q15_t)0x30c, (q15_t)0xec7c, (q15_t)0x308, (q15_t)0xec88, (q15_t)0x305, (q15_t)0xec94, (q15_t)0x301, (q15_t)0xeca0, + (q15_t)0x2fd, (q15_t)0xecac, (q15_t)0x2f9, (q15_t)0xecb8, (q15_t)0x2f5, (q15_t)0xecc4, (q15_t)0x2f2, (q15_t)0xecd0, + (q15_t)0x2ee, (q15_t)0xecdc, (q15_t)0x2ea, (q15_t)0xece8, (q15_t)0x2e6, (q15_t)0xecf4, (q15_t)0x2e3, (q15_t)0xed00, + (q15_t)0x2df, (q15_t)0xed0c, (q15_t)0x2db, (q15_t)0xed18, (q15_t)0x2d8, (q15_t)0xed24, (q15_t)0x2d4, (q15_t)0xed30, + (q15_t)0x2d0, (q15_t)0xed3c, (q15_t)0x2cc, (q15_t)0xed48, (q15_t)0x2c9, (q15_t)0xed54, (q15_t)0x2c5, (q15_t)0xed60, + (q15_t)0x2c1, (q15_t)0xed6c, (q15_t)0x2be, (q15_t)0xed78, (q15_t)0x2ba, (q15_t)0xed84, (q15_t)0x2b7, (q15_t)0xed90, + (q15_t)0x2b3, (q15_t)0xed9c, (q15_t)0x2af, (q15_t)0xeda8, (q15_t)0x2ac, (q15_t)0xedb4, (q15_t)0x2a8, (q15_t)0xedc0, + (q15_t)0x2a5, (q15_t)0xedcc, (q15_t)0x2a1, (q15_t)0xedd8, (q15_t)0x29d, (q15_t)0xede4, (q15_t)0x29a, (q15_t)0xedf0, + (q15_t)0x296, (q15_t)0xedfc, (q15_t)0x293, (q15_t)0xee09, (q15_t)0x28f, (q15_t)0xee15, (q15_t)0x28c, (q15_t)0xee21, + (q15_t)0x288, (q15_t)0xee2d, (q15_t)0x285, (q15_t)0xee39, (q15_t)0x281, (q15_t)0xee45, (q15_t)0x27e, (q15_t)0xee51, + (q15_t)0x27a, (q15_t)0xee5d, (q15_t)0x277, (q15_t)0xee69, (q15_t)0x273, (q15_t)0xee75, (q15_t)0x270, (q15_t)0xee81, + (q15_t)0x26d, (q15_t)0xee8d, (q15_t)0x269, (q15_t)0xee99, (q15_t)0x266, (q15_t)0xeea6, (q15_t)0x262, (q15_t)0xeeb2, + (q15_t)0x25f, (q15_t)0xeebe, (q15_t)0x25c, (q15_t)0xeeca, (q15_t)0x258, (q15_t)0xeed6, (q15_t)0x255, (q15_t)0xeee2, + (q15_t)0x251, (q15_t)0xeeee, (q15_t)0x24e, (q15_t)0xeefa, (q15_t)0x24b, (q15_t)0xef06, (q15_t)0x247, (q15_t)0xef13, + (q15_t)0x244, (q15_t)0xef1f, (q15_t)0x241, (q15_t)0xef2b, (q15_t)0x23e, (q15_t)0xef37, (q15_t)0x23a, (q15_t)0xef43, + (q15_t)0x237, (q15_t)0xef4f, (q15_t)0x234, (q15_t)0xef5b, (q15_t)0x230, (q15_t)0xef67, (q15_t)0x22d, (q15_t)0xef74, + (q15_t)0x22a, (q15_t)0xef80, (q15_t)0x227, (q15_t)0xef8c, (q15_t)0x223, (q15_t)0xef98, (q15_t)0x220, (q15_t)0xefa4, + (q15_t)0x21d, (q15_t)0xefb0, (q15_t)0x21a, (q15_t)0xefbc, (q15_t)0x217, (q15_t)0xefc9, (q15_t)0x213, (q15_t)0xefd5, + (q15_t)0x210, (q15_t)0xefe1, (q15_t)0x20d, (q15_t)0xefed, (q15_t)0x20a, (q15_t)0xeff9, (q15_t)0x207, (q15_t)0xf005, + (q15_t)0x204, (q15_t)0xf012, (q15_t)0x201, (q15_t)0xf01e, (q15_t)0x1fd, (q15_t)0xf02a, (q15_t)0x1fa, (q15_t)0xf036, + (q15_t)0x1f7, (q15_t)0xf042, (q15_t)0x1f4, (q15_t)0xf04e, (q15_t)0x1f1, (q15_t)0xf05b, (q15_t)0x1ee, (q15_t)0xf067, + (q15_t)0x1eb, (q15_t)0xf073, (q15_t)0x1e8, (q15_t)0xf07f, (q15_t)0x1e5, (q15_t)0xf08b, (q15_t)0x1e2, (q15_t)0xf098, + (q15_t)0x1df, (q15_t)0xf0a4, (q15_t)0x1dc, (q15_t)0xf0b0, (q15_t)0x1d9, (q15_t)0xf0bc, (q15_t)0x1d6, (q15_t)0xf0c8, + (q15_t)0x1d3, (q15_t)0xf0d5, (q15_t)0x1d0, (q15_t)0xf0e1, (q15_t)0x1cd, (q15_t)0xf0ed, (q15_t)0x1ca, (q15_t)0xf0f9, + (q15_t)0x1c7, (q15_t)0xf105, (q15_t)0x1c4, (q15_t)0xf112, (q15_t)0x1c1, (q15_t)0xf11e, (q15_t)0x1be, (q15_t)0xf12a, + (q15_t)0x1bb, (q15_t)0xf136, (q15_t)0x1b8, (q15_t)0xf143, (q15_t)0x1b6, (q15_t)0xf14f, (q15_t)0x1b3, (q15_t)0xf15b, + (q15_t)0x1b0, (q15_t)0xf167, (q15_t)0x1ad, (q15_t)0xf174, (q15_t)0x1aa, (q15_t)0xf180, (q15_t)0x1a7, (q15_t)0xf18c, + (q15_t)0x1a4, (q15_t)0xf198, (q15_t)0x1a2, (q15_t)0xf1a4, (q15_t)0x19f, (q15_t)0xf1b1, (q15_t)0x19c, (q15_t)0xf1bd, + (q15_t)0x199, (q15_t)0xf1c9, (q15_t)0x196, (q15_t)0xf1d5, (q15_t)0x194, (q15_t)0xf1e2, (q15_t)0x191, (q15_t)0xf1ee, + (q15_t)0x18e, (q15_t)0xf1fa, (q15_t)0x18b, (q15_t)0xf207, (q15_t)0x189, (q15_t)0xf213, (q15_t)0x186, (q15_t)0xf21f, + (q15_t)0x183, (q15_t)0xf22b, (q15_t)0x180, (q15_t)0xf238, (q15_t)0x17e, (q15_t)0xf244, (q15_t)0x17b, (q15_t)0xf250, + (q15_t)0x178, (q15_t)0xf25c, (q15_t)0x176, (q15_t)0xf269, (q15_t)0x173, (q15_t)0xf275, (q15_t)0x170, (q15_t)0xf281, + (q15_t)0x16e, (q15_t)0xf28e, (q15_t)0x16b, (q15_t)0xf29a, (q15_t)0x168, (q15_t)0xf2a6, (q15_t)0x166, (q15_t)0xf2b2, + (q15_t)0x163, (q15_t)0xf2bf, (q15_t)0x161, (q15_t)0xf2cb, (q15_t)0x15e, (q15_t)0xf2d7, (q15_t)0x15b, (q15_t)0xf2e4, + (q15_t)0x159, (q15_t)0xf2f0, (q15_t)0x156, (q15_t)0xf2fc, (q15_t)0x154, (q15_t)0xf308, (q15_t)0x151, (q15_t)0xf315, + (q15_t)0x14f, (q15_t)0xf321, (q15_t)0x14c, (q15_t)0xf32d, (q15_t)0x14a, (q15_t)0xf33a, (q15_t)0x147, (q15_t)0xf346, + (q15_t)0x145, (q15_t)0xf352, (q15_t)0x142, (q15_t)0xf35f, (q15_t)0x140, (q15_t)0xf36b, (q15_t)0x13d, (q15_t)0xf377, + (q15_t)0x13b, (q15_t)0xf384, (q15_t)0x138, (q15_t)0xf390, (q15_t)0x136, (q15_t)0xf39c, (q15_t)0x134, (q15_t)0xf3a9, + (q15_t)0x131, (q15_t)0xf3b5, (q15_t)0x12f, (q15_t)0xf3c1, (q15_t)0x12c, (q15_t)0xf3ce, (q15_t)0x12a, (q15_t)0xf3da, + (q15_t)0x128, (q15_t)0xf3e6, (q15_t)0x125, (q15_t)0xf3f3, (q15_t)0x123, (q15_t)0xf3ff, (q15_t)0x120, (q15_t)0xf40b, + (q15_t)0x11e, (q15_t)0xf418, (q15_t)0x11c, (q15_t)0xf424, (q15_t)0x119, (q15_t)0xf430, (q15_t)0x117, (q15_t)0xf43d, + (q15_t)0x115, (q15_t)0xf449, (q15_t)0x113, (q15_t)0xf455, (q15_t)0x110, (q15_t)0xf462, (q15_t)0x10e, (q15_t)0xf46e, + (q15_t)0x10c, (q15_t)0xf47b, (q15_t)0x109, (q15_t)0xf487, (q15_t)0x107, (q15_t)0xf493, (q15_t)0x105, (q15_t)0xf4a0, + (q15_t)0x103, (q15_t)0xf4ac, (q15_t)0x100, (q15_t)0xf4b8, (q15_t)0xfe, (q15_t)0xf4c5, (q15_t)0xfc, (q15_t)0xf4d1, + (q15_t)0xfa, (q15_t)0xf4dd, (q15_t)0xf8, (q15_t)0xf4ea, (q15_t)0xf6, (q15_t)0xf4f6, (q15_t)0xf3, (q15_t)0xf503, + (q15_t)0xf1, (q15_t)0xf50f, (q15_t)0xef, (q15_t)0xf51b, (q15_t)0xed, (q15_t)0xf528, (q15_t)0xeb, (q15_t)0xf534, + (q15_t)0xe9, (q15_t)0xf540, (q15_t)0xe7, (q15_t)0xf54d, (q15_t)0xe4, (q15_t)0xf559, (q15_t)0xe2, (q15_t)0xf566, + (q15_t)0xe0, (q15_t)0xf572, (q15_t)0xde, (q15_t)0xf57e, (q15_t)0xdc, (q15_t)0xf58b, (q15_t)0xda, (q15_t)0xf597, + (q15_t)0xd8, (q15_t)0xf5a4, (q15_t)0xd6, (q15_t)0xf5b0, (q15_t)0xd4, (q15_t)0xf5bc, (q15_t)0xd2, (q15_t)0xf5c9, + (q15_t)0xd0, (q15_t)0xf5d5, (q15_t)0xce, (q15_t)0xf5e2, (q15_t)0xcc, (q15_t)0xf5ee, (q15_t)0xca, (q15_t)0xf5fa, + (q15_t)0xc8, (q15_t)0xf607, (q15_t)0xc6, (q15_t)0xf613, (q15_t)0xc4, (q15_t)0xf620, (q15_t)0xc2, (q15_t)0xf62c, + (q15_t)0xc0, (q15_t)0xf639, (q15_t)0xbe, (q15_t)0xf645, (q15_t)0xbd, (q15_t)0xf651, (q15_t)0xbb, (q15_t)0xf65e, + (q15_t)0xb9, (q15_t)0xf66a, (q15_t)0xb7, (q15_t)0xf677, (q15_t)0xb5, (q15_t)0xf683, (q15_t)0xb3, (q15_t)0xf690, + (q15_t)0xb1, (q15_t)0xf69c, (q15_t)0xaf, (q15_t)0xf6a8, (q15_t)0xae, (q15_t)0xf6b5, (q15_t)0xac, (q15_t)0xf6c1, + (q15_t)0xaa, (q15_t)0xf6ce, (q15_t)0xa8, (q15_t)0xf6da, (q15_t)0xa6, (q15_t)0xf6e7, (q15_t)0xa5, (q15_t)0xf6f3, + (q15_t)0xa3, (q15_t)0xf6ff, (q15_t)0xa1, (q15_t)0xf70c, (q15_t)0x9f, (q15_t)0xf718, (q15_t)0x9e, (q15_t)0xf725, + (q15_t)0x9c, (q15_t)0xf731, (q15_t)0x9a, (q15_t)0xf73e, (q15_t)0x98, (q15_t)0xf74a, (q15_t)0x97, (q15_t)0xf757, + (q15_t)0x95, (q15_t)0xf763, (q15_t)0x93, (q15_t)0xf76f, (q15_t)0x92, (q15_t)0xf77c, (q15_t)0x90, (q15_t)0xf788, + (q15_t)0x8e, (q15_t)0xf795, (q15_t)0x8d, (q15_t)0xf7a1, (q15_t)0x8b, (q15_t)0xf7ae, (q15_t)0x89, (q15_t)0xf7ba, + (q15_t)0x88, (q15_t)0xf7c7, (q15_t)0x86, (q15_t)0xf7d3, (q15_t)0x85, (q15_t)0xf7e0, (q15_t)0x83, (q15_t)0xf7ec, + (q15_t)0x81, (q15_t)0xf7f9, (q15_t)0x80, (q15_t)0xf805, (q15_t)0x7e, (q15_t)0xf811, (q15_t)0x7d, (q15_t)0xf81e, + (q15_t)0x7b, (q15_t)0xf82a, (q15_t)0x7a, (q15_t)0xf837, (q15_t)0x78, (q15_t)0xf843, (q15_t)0x77, (q15_t)0xf850, + (q15_t)0x75, (q15_t)0xf85c, (q15_t)0x74, (q15_t)0xf869, (q15_t)0x72, (q15_t)0xf875, (q15_t)0x71, (q15_t)0xf882, + (q15_t)0x6f, (q15_t)0xf88e, (q15_t)0x6e, (q15_t)0xf89b, (q15_t)0x6c, (q15_t)0xf8a7, (q15_t)0x6b, (q15_t)0xf8b4, + (q15_t)0x69, (q15_t)0xf8c0, (q15_t)0x68, (q15_t)0xf8cd, (q15_t)0x67, (q15_t)0xf8d9, (q15_t)0x65, (q15_t)0xf8e6, + (q15_t)0x64, (q15_t)0xf8f2, (q15_t)0x62, (q15_t)0xf8ff, (q15_t)0x61, (q15_t)0xf90b, (q15_t)0x60, (q15_t)0xf918, + (q15_t)0x5e, (q15_t)0xf924, (q15_t)0x5d, (q15_t)0xf931, (q15_t)0x5c, (q15_t)0xf93d, (q15_t)0x5a, (q15_t)0xf94a, + (q15_t)0x59, (q15_t)0xf956, (q15_t)0x58, (q15_t)0xf963, (q15_t)0x56, (q15_t)0xf96f, (q15_t)0x55, (q15_t)0xf97c, + (q15_t)0x54, (q15_t)0xf988, (q15_t)0x53, (q15_t)0xf995, (q15_t)0x51, (q15_t)0xf9a1, (q15_t)0x50, (q15_t)0xf9ae, + (q15_t)0x4f, (q15_t)0xf9ba, (q15_t)0x4e, (q15_t)0xf9c7, (q15_t)0x4c, (q15_t)0xf9d3, (q15_t)0x4b, (q15_t)0xf9e0, + (q15_t)0x4a, (q15_t)0xf9ec, (q15_t)0x49, (q15_t)0xf9f9, (q15_t)0x48, (q15_t)0xfa05, (q15_t)0x47, (q15_t)0xfa12, + (q15_t)0x45, (q15_t)0xfa1e, (q15_t)0x44, (q15_t)0xfa2b, (q15_t)0x43, (q15_t)0xfa37, (q15_t)0x42, (q15_t)0xfa44, + (q15_t)0x41, (q15_t)0xfa50, (q15_t)0x40, (q15_t)0xfa5d, (q15_t)0x3f, (q15_t)0xfa69, (q15_t)0x3d, (q15_t)0xfa76, + (q15_t)0x3c, (q15_t)0xfa82, (q15_t)0x3b, (q15_t)0xfa8f, (q15_t)0x3a, (q15_t)0xfa9b, (q15_t)0x39, (q15_t)0xfaa8, + (q15_t)0x38, (q15_t)0xfab4, (q15_t)0x37, (q15_t)0xfac1, (q15_t)0x36, (q15_t)0xfacd, (q15_t)0x35, (q15_t)0xfada, + (q15_t)0x34, (q15_t)0xfae6, (q15_t)0x33, (q15_t)0xfaf3, (q15_t)0x32, (q15_t)0xfb00, (q15_t)0x31, (q15_t)0xfb0c, + (q15_t)0x30, (q15_t)0xfb19, (q15_t)0x2f, (q15_t)0xfb25, (q15_t)0x2e, (q15_t)0xfb32, (q15_t)0x2d, (q15_t)0xfb3e, + (q15_t)0x2c, (q15_t)0xfb4b, (q15_t)0x2b, (q15_t)0xfb57, (q15_t)0x2b, (q15_t)0xfb64, (q15_t)0x2a, (q15_t)0xfb70, + (q15_t)0x29, (q15_t)0xfb7d, (q15_t)0x28, (q15_t)0xfb89, (q15_t)0x27, (q15_t)0xfb96, (q15_t)0x26, (q15_t)0xfba2, + (q15_t)0x25, (q15_t)0xfbaf, (q15_t)0x24, (q15_t)0xfbbc, (q15_t)0x24, (q15_t)0xfbc8, (q15_t)0x23, (q15_t)0xfbd5, + (q15_t)0x22, (q15_t)0xfbe1, (q15_t)0x21, (q15_t)0xfbee, (q15_t)0x20, (q15_t)0xfbfa, (q15_t)0x20, (q15_t)0xfc07, + (q15_t)0x1f, (q15_t)0xfc13, (q15_t)0x1e, (q15_t)0xfc20, (q15_t)0x1d, (q15_t)0xfc2c, (q15_t)0x1d, (q15_t)0xfc39, + (q15_t)0x1c, (q15_t)0xfc45, (q15_t)0x1b, (q15_t)0xfc52, (q15_t)0x1a, (q15_t)0xfc5f, (q15_t)0x1a, (q15_t)0xfc6b, + (q15_t)0x19, (q15_t)0xfc78, (q15_t)0x18, (q15_t)0xfc84, (q15_t)0x18, (q15_t)0xfc91, (q15_t)0x17, (q15_t)0xfc9d, + (q15_t)0x16, (q15_t)0xfcaa, (q15_t)0x16, (q15_t)0xfcb6, (q15_t)0x15, (q15_t)0xfcc3, (q15_t)0x14, (q15_t)0xfcd0, + (q15_t)0x14, (q15_t)0xfcdc, (q15_t)0x13, (q15_t)0xfce9, (q15_t)0x13, (q15_t)0xfcf5, (q15_t)0x12, (q15_t)0xfd02, + (q15_t)0x11, (q15_t)0xfd0e, (q15_t)0x11, (q15_t)0xfd1b, (q15_t)0x10, (q15_t)0xfd27, (q15_t)0x10, (q15_t)0xfd34, + (q15_t)0xf, (q15_t)0xfd40, (q15_t)0xf, (q15_t)0xfd4d, (q15_t)0xe, (q15_t)0xfd5a, (q15_t)0xe, (q15_t)0xfd66, + (q15_t)0xd, (q15_t)0xfd73, (q15_t)0xd, (q15_t)0xfd7f, (q15_t)0xc, (q15_t)0xfd8c, (q15_t)0xc, (q15_t)0xfd98, + (q15_t)0xb, (q15_t)0xfda5, (q15_t)0xb, (q15_t)0xfdb2, (q15_t)0xa, (q15_t)0xfdbe, (q15_t)0xa, (q15_t)0xfdcb, + (q15_t)0x9, (q15_t)0xfdd7, (q15_t)0x9, (q15_t)0xfde4, (q15_t)0x9, (q15_t)0xfdf0, (q15_t)0x8, (q15_t)0xfdfd, + (q15_t)0x8, (q15_t)0xfe09, (q15_t)0x7, (q15_t)0xfe16, (q15_t)0x7, (q15_t)0xfe23, (q15_t)0x7, (q15_t)0xfe2f, + (q15_t)0x6, (q15_t)0xfe3c, (q15_t)0x6, (q15_t)0xfe48, (q15_t)0x6, (q15_t)0xfe55, (q15_t)0x5, (q15_t)0xfe61, + (q15_t)0x5, (q15_t)0xfe6e, (q15_t)0x5, (q15_t)0xfe7a, (q15_t)0x4, (q15_t)0xfe87, (q15_t)0x4, (q15_t)0xfe94, + (q15_t)0x4, (q15_t)0xfea0, (q15_t)0x4, (q15_t)0xfead, (q15_t)0x3, (q15_t)0xfeb9, (q15_t)0x3, (q15_t)0xfec6, + (q15_t)0x3, (q15_t)0xfed2, (q15_t)0x3, (q15_t)0xfedf, (q15_t)0x2, (q15_t)0xfeec, (q15_t)0x2, (q15_t)0xfef8, + (q15_t)0x2, (q15_t)0xff05, (q15_t)0x2, (q15_t)0xff11, (q15_t)0x2, (q15_t)0xff1e, (q15_t)0x1, (q15_t)0xff2a, + (q15_t)0x1, (q15_t)0xff37, (q15_t)0x1, (q15_t)0xff44, (q15_t)0x1, (q15_t)0xff50, (q15_t)0x1, (q15_t)0xff5d, + (q15_t)0x1, (q15_t)0xff69, (q15_t)0x1, (q15_t)0xff76, (q15_t)0x0, (q15_t)0xff82, (q15_t)0x0, (q15_t)0xff8f, + (q15_t)0x0, (q15_t)0xff9b, (q15_t)0x0, (q15_t)0xffa8, (q15_t)0x0, (q15_t)0xffb5, (q15_t)0x0, (q15_t)0xffc1, + (q15_t)0x0, (q15_t)0xffce, (q15_t)0x0, (q15_t)0xffda, (q15_t)0x0, (q15_t)0xffe7, (q15_t)0x0, (q15_t)0xfff3, + (q15_t)0x0, (q15_t)0x0, (q15_t)0x0, (q15_t)0xd, (q15_t)0x0, (q15_t)0x19, (q15_t)0x0, (q15_t)0x26, + (q15_t)0x0, (q15_t)0x32, (q15_t)0x0, (q15_t)0x3f, (q15_t)0x0, (q15_t)0x4b, (q15_t)0x0, (q15_t)0x58, + (q15_t)0x0, (q15_t)0x65, (q15_t)0x0, (q15_t)0x71, (q15_t)0x0, (q15_t)0x7e, (q15_t)0x1, (q15_t)0x8a, + (q15_t)0x1, (q15_t)0x97, (q15_t)0x1, (q15_t)0xa3, (q15_t)0x1, (q15_t)0xb0, (q15_t)0x1, (q15_t)0xbc, + (q15_t)0x1, (q15_t)0xc9, (q15_t)0x1, (q15_t)0xd6, (q15_t)0x2, (q15_t)0xe2, (q15_t)0x2, (q15_t)0xef, + (q15_t)0x2, (q15_t)0xfb, (q15_t)0x2, (q15_t)0x108, (q15_t)0x2, (q15_t)0x114, (q15_t)0x3, (q15_t)0x121, + (q15_t)0x3, (q15_t)0x12e, (q15_t)0x3, (q15_t)0x13a, (q15_t)0x3, (q15_t)0x147, (q15_t)0x4, (q15_t)0x153, + (q15_t)0x4, (q15_t)0x160, (q15_t)0x4, (q15_t)0x16c, (q15_t)0x4, (q15_t)0x179, (q15_t)0x5, (q15_t)0x186, + (q15_t)0x5, (q15_t)0x192, (q15_t)0x5, (q15_t)0x19f, (q15_t)0x6, (q15_t)0x1ab, (q15_t)0x6, (q15_t)0x1b8, + (q15_t)0x6, (q15_t)0x1c4, (q15_t)0x7, (q15_t)0x1d1, (q15_t)0x7, (q15_t)0x1dd, (q15_t)0x7, (q15_t)0x1ea, + (q15_t)0x8, (q15_t)0x1f7, (q15_t)0x8, (q15_t)0x203, (q15_t)0x9, (q15_t)0x210, (q15_t)0x9, (q15_t)0x21c, + (q15_t)0x9, (q15_t)0x229, (q15_t)0xa, (q15_t)0x235, (q15_t)0xa, (q15_t)0x242, (q15_t)0xb, (q15_t)0x24e, + (q15_t)0xb, (q15_t)0x25b, (q15_t)0xc, (q15_t)0x268, (q15_t)0xc, (q15_t)0x274, (q15_t)0xd, (q15_t)0x281, + (q15_t)0xd, (q15_t)0x28d, (q15_t)0xe, (q15_t)0x29a, (q15_t)0xe, (q15_t)0x2a6, (q15_t)0xf, (q15_t)0x2b3, + (q15_t)0xf, (q15_t)0x2c0, (q15_t)0x10, (q15_t)0x2cc, (q15_t)0x10, (q15_t)0x2d9, (q15_t)0x11, (q15_t)0x2e5, + (q15_t)0x11, (q15_t)0x2f2, (q15_t)0x12, (q15_t)0x2fe, (q15_t)0x13, (q15_t)0x30b, (q15_t)0x13, (q15_t)0x317, + (q15_t)0x14, (q15_t)0x324, (q15_t)0x14, (q15_t)0x330, (q15_t)0x15, (q15_t)0x33d, (q15_t)0x16, (q15_t)0x34a, + (q15_t)0x16, (q15_t)0x356, (q15_t)0x17, (q15_t)0x363, (q15_t)0x18, (q15_t)0x36f, (q15_t)0x18, (q15_t)0x37c, + (q15_t)0x19, (q15_t)0x388, (q15_t)0x1a, (q15_t)0x395, (q15_t)0x1a, (q15_t)0x3a1, (q15_t)0x1b, (q15_t)0x3ae, + (q15_t)0x1c, (q15_t)0x3bb, (q15_t)0x1d, (q15_t)0x3c7, (q15_t)0x1d, (q15_t)0x3d4, (q15_t)0x1e, (q15_t)0x3e0, + (q15_t)0x1f, (q15_t)0x3ed, (q15_t)0x20, (q15_t)0x3f9, (q15_t)0x20, (q15_t)0x406, (q15_t)0x21, (q15_t)0x412, + (q15_t)0x22, (q15_t)0x41f, (q15_t)0x23, (q15_t)0x42b, (q15_t)0x24, (q15_t)0x438, (q15_t)0x24, (q15_t)0x444, + (q15_t)0x25, (q15_t)0x451, (q15_t)0x26, (q15_t)0x45e, (q15_t)0x27, (q15_t)0x46a, (q15_t)0x28, (q15_t)0x477, + (q15_t)0x29, (q15_t)0x483, (q15_t)0x2a, (q15_t)0x490, (q15_t)0x2b, (q15_t)0x49c, (q15_t)0x2b, (q15_t)0x4a9, + (q15_t)0x2c, (q15_t)0x4b5, (q15_t)0x2d, (q15_t)0x4c2, (q15_t)0x2e, (q15_t)0x4ce, (q15_t)0x2f, (q15_t)0x4db, + (q15_t)0x30, (q15_t)0x4e7, (q15_t)0x31, (q15_t)0x4f4, (q15_t)0x32, (q15_t)0x500, (q15_t)0x33, (q15_t)0x50d, + (q15_t)0x34, (q15_t)0x51a, (q15_t)0x35, (q15_t)0x526, (q15_t)0x36, (q15_t)0x533, (q15_t)0x37, (q15_t)0x53f, + (q15_t)0x38, (q15_t)0x54c, (q15_t)0x39, (q15_t)0x558, (q15_t)0x3a, (q15_t)0x565, (q15_t)0x3b, (q15_t)0x571, + (q15_t)0x3c, (q15_t)0x57e, (q15_t)0x3d, (q15_t)0x58a, (q15_t)0x3f, (q15_t)0x597, (q15_t)0x40, (q15_t)0x5a3, + (q15_t)0x41, (q15_t)0x5b0, (q15_t)0x42, (q15_t)0x5bc, (q15_t)0x43, (q15_t)0x5c9, (q15_t)0x44, (q15_t)0x5d5, + (q15_t)0x45, (q15_t)0x5e2, (q15_t)0x47, (q15_t)0x5ee, (q15_t)0x48, (q15_t)0x5fb, (q15_t)0x49, (q15_t)0x607, + (q15_t)0x4a, (q15_t)0x614, (q15_t)0x4b, (q15_t)0x620, (q15_t)0x4c, (q15_t)0x62d, (q15_t)0x4e, (q15_t)0x639, + (q15_t)0x4f, (q15_t)0x646, (q15_t)0x50, (q15_t)0x652, (q15_t)0x51, (q15_t)0x65f, (q15_t)0x53, (q15_t)0x66b, + (q15_t)0x54, (q15_t)0x678, (q15_t)0x55, (q15_t)0x684, (q15_t)0x56, (q15_t)0x691, (q15_t)0x58, (q15_t)0x69d, + (q15_t)0x59, (q15_t)0x6aa, (q15_t)0x5a, (q15_t)0x6b6, (q15_t)0x5c, (q15_t)0x6c3, (q15_t)0x5d, (q15_t)0x6cf, + (q15_t)0x5e, (q15_t)0x6dc, (q15_t)0x60, (q15_t)0x6e8, (q15_t)0x61, (q15_t)0x6f5, (q15_t)0x62, (q15_t)0x701, + (q15_t)0x64, (q15_t)0x70e, (q15_t)0x65, (q15_t)0x71a, (q15_t)0x67, (q15_t)0x727, (q15_t)0x68, (q15_t)0x733, + (q15_t)0x69, (q15_t)0x740, (q15_t)0x6b, (q15_t)0x74c, (q15_t)0x6c, (q15_t)0x759, (q15_t)0x6e, (q15_t)0x765, + (q15_t)0x6f, (q15_t)0x772, (q15_t)0x71, (q15_t)0x77e, (q15_t)0x72, (q15_t)0x78b, (q15_t)0x74, (q15_t)0x797, + (q15_t)0x75, (q15_t)0x7a4, (q15_t)0x77, (q15_t)0x7b0, (q15_t)0x78, (q15_t)0x7bd, (q15_t)0x7a, (q15_t)0x7c9, + (q15_t)0x7b, (q15_t)0x7d6, (q15_t)0x7d, (q15_t)0x7e2, (q15_t)0x7e, (q15_t)0x7ef, (q15_t)0x80, (q15_t)0x7fb, + (q15_t)0x81, (q15_t)0x807, (q15_t)0x83, (q15_t)0x814, (q15_t)0x85, (q15_t)0x820, (q15_t)0x86, (q15_t)0x82d, + (q15_t)0x88, (q15_t)0x839, (q15_t)0x89, (q15_t)0x846, (q15_t)0x8b, (q15_t)0x852, (q15_t)0x8d, (q15_t)0x85f, + (q15_t)0x8e, (q15_t)0x86b, (q15_t)0x90, (q15_t)0x878, (q15_t)0x92, (q15_t)0x884, (q15_t)0x93, (q15_t)0x891, + (q15_t)0x95, (q15_t)0x89d, (q15_t)0x97, (q15_t)0x8a9, (q15_t)0x98, (q15_t)0x8b6, (q15_t)0x9a, (q15_t)0x8c2, + (q15_t)0x9c, (q15_t)0x8cf, (q15_t)0x9e, (q15_t)0x8db, (q15_t)0x9f, (q15_t)0x8e8, (q15_t)0xa1, (q15_t)0x8f4, + (q15_t)0xa3, (q15_t)0x901, (q15_t)0xa5, (q15_t)0x90d, (q15_t)0xa6, (q15_t)0x919, (q15_t)0xa8, (q15_t)0x926, + (q15_t)0xaa, (q15_t)0x932, (q15_t)0xac, (q15_t)0x93f, (q15_t)0xae, (q15_t)0x94b, (q15_t)0xaf, (q15_t)0x958, + (q15_t)0xb1, (q15_t)0x964, (q15_t)0xb3, (q15_t)0x970, (q15_t)0xb5, (q15_t)0x97d, (q15_t)0xb7, (q15_t)0x989, + (q15_t)0xb9, (q15_t)0x996, (q15_t)0xbb, (q15_t)0x9a2, (q15_t)0xbd, (q15_t)0x9af, (q15_t)0xbe, (q15_t)0x9bb, + (q15_t)0xc0, (q15_t)0x9c7, (q15_t)0xc2, (q15_t)0x9d4, (q15_t)0xc4, (q15_t)0x9e0, (q15_t)0xc6, (q15_t)0x9ed, + (q15_t)0xc8, (q15_t)0x9f9, (q15_t)0xca, (q15_t)0xa06, (q15_t)0xcc, (q15_t)0xa12, (q15_t)0xce, (q15_t)0xa1e, + (q15_t)0xd0, (q15_t)0xa2b, (q15_t)0xd2, (q15_t)0xa37, (q15_t)0xd4, (q15_t)0xa44, (q15_t)0xd6, (q15_t)0xa50, + (q15_t)0xd8, (q15_t)0xa5c, (q15_t)0xda, (q15_t)0xa69, (q15_t)0xdc, (q15_t)0xa75, (q15_t)0xde, (q15_t)0xa82, + (q15_t)0xe0, (q15_t)0xa8e, (q15_t)0xe2, (q15_t)0xa9a, (q15_t)0xe4, (q15_t)0xaa7, (q15_t)0xe7, (q15_t)0xab3, + (q15_t)0xe9, (q15_t)0xac0, (q15_t)0xeb, (q15_t)0xacc, (q15_t)0xed, (q15_t)0xad8, (q15_t)0xef, (q15_t)0xae5, + (q15_t)0xf1, (q15_t)0xaf1, (q15_t)0xf3, (q15_t)0xafd, (q15_t)0xf6, (q15_t)0xb0a, (q15_t)0xf8, (q15_t)0xb16, + (q15_t)0xfa, (q15_t)0xb23, (q15_t)0xfc, (q15_t)0xb2f, (q15_t)0xfe, (q15_t)0xb3b, (q15_t)0x100, (q15_t)0xb48, + (q15_t)0x103, (q15_t)0xb54, (q15_t)0x105, (q15_t)0xb60, (q15_t)0x107, (q15_t)0xb6d, (q15_t)0x109, (q15_t)0xb79, + (q15_t)0x10c, (q15_t)0xb85, (q15_t)0x10e, (q15_t)0xb92, (q15_t)0x110, (q15_t)0xb9e, (q15_t)0x113, (q15_t)0xbab, + (q15_t)0x115, (q15_t)0xbb7, (q15_t)0x117, (q15_t)0xbc3, (q15_t)0x119, (q15_t)0xbd0, (q15_t)0x11c, (q15_t)0xbdc, + (q15_t)0x11e, (q15_t)0xbe8, (q15_t)0x120, (q15_t)0xbf5, (q15_t)0x123, (q15_t)0xc01, (q15_t)0x125, (q15_t)0xc0d, + (q15_t)0x128, (q15_t)0xc1a, (q15_t)0x12a, (q15_t)0xc26, (q15_t)0x12c, (q15_t)0xc32, (q15_t)0x12f, (q15_t)0xc3f, + (q15_t)0x131, (q15_t)0xc4b, (q15_t)0x134, (q15_t)0xc57, (q15_t)0x136, (q15_t)0xc64, (q15_t)0x138, (q15_t)0xc70, + (q15_t)0x13b, (q15_t)0xc7c, (q15_t)0x13d, (q15_t)0xc89, (q15_t)0x140, (q15_t)0xc95, (q15_t)0x142, (q15_t)0xca1, + (q15_t)0x145, (q15_t)0xcae, (q15_t)0x147, (q15_t)0xcba, (q15_t)0x14a, (q15_t)0xcc6, (q15_t)0x14c, (q15_t)0xcd3, + (q15_t)0x14f, (q15_t)0xcdf, (q15_t)0x151, (q15_t)0xceb, (q15_t)0x154, (q15_t)0xcf8, (q15_t)0x156, (q15_t)0xd04, + (q15_t)0x159, (q15_t)0xd10, (q15_t)0x15b, (q15_t)0xd1c, (q15_t)0x15e, (q15_t)0xd29, (q15_t)0x161, (q15_t)0xd35, + (q15_t)0x163, (q15_t)0xd41, (q15_t)0x166, (q15_t)0xd4e, (q15_t)0x168, (q15_t)0xd5a, (q15_t)0x16b, (q15_t)0xd66, + (q15_t)0x16e, (q15_t)0xd72, (q15_t)0x170, (q15_t)0xd7f, (q15_t)0x173, (q15_t)0xd8b, (q15_t)0x176, (q15_t)0xd97, + (q15_t)0x178, (q15_t)0xda4, (q15_t)0x17b, (q15_t)0xdb0, (q15_t)0x17e, (q15_t)0xdbc, (q15_t)0x180, (q15_t)0xdc8, + (q15_t)0x183, (q15_t)0xdd5, (q15_t)0x186, (q15_t)0xde1, (q15_t)0x189, (q15_t)0xded, (q15_t)0x18b, (q15_t)0xdf9, + (q15_t)0x18e, (q15_t)0xe06, (q15_t)0x191, (q15_t)0xe12, (q15_t)0x194, (q15_t)0xe1e, (q15_t)0x196, (q15_t)0xe2b, + (q15_t)0x199, (q15_t)0xe37, (q15_t)0x19c, (q15_t)0xe43, (q15_t)0x19f, (q15_t)0xe4f, (q15_t)0x1a2, (q15_t)0xe5c, + (q15_t)0x1a4, (q15_t)0xe68, (q15_t)0x1a7, (q15_t)0xe74, (q15_t)0x1aa, (q15_t)0xe80, (q15_t)0x1ad, (q15_t)0xe8c, + (q15_t)0x1b0, (q15_t)0xe99, (q15_t)0x1b3, (q15_t)0xea5, (q15_t)0x1b6, (q15_t)0xeb1, (q15_t)0x1b8, (q15_t)0xebd, + (q15_t)0x1bb, (q15_t)0xeca, (q15_t)0x1be, (q15_t)0xed6, (q15_t)0x1c1, (q15_t)0xee2, (q15_t)0x1c4, (q15_t)0xeee, + (q15_t)0x1c7, (q15_t)0xefb, (q15_t)0x1ca, (q15_t)0xf07, (q15_t)0x1cd, (q15_t)0xf13, (q15_t)0x1d0, (q15_t)0xf1f, + (q15_t)0x1d3, (q15_t)0xf2b, (q15_t)0x1d6, (q15_t)0xf38, (q15_t)0x1d9, (q15_t)0xf44, (q15_t)0x1dc, (q15_t)0xf50, + (q15_t)0x1df, (q15_t)0xf5c, (q15_t)0x1e2, (q15_t)0xf68, (q15_t)0x1e5, (q15_t)0xf75, (q15_t)0x1e8, (q15_t)0xf81, + (q15_t)0x1eb, (q15_t)0xf8d, (q15_t)0x1ee, (q15_t)0xf99, (q15_t)0x1f1, (q15_t)0xfa5, (q15_t)0x1f4, (q15_t)0xfb2, + (q15_t)0x1f7, (q15_t)0xfbe, (q15_t)0x1fa, (q15_t)0xfca, (q15_t)0x1fd, (q15_t)0xfd6, (q15_t)0x201, (q15_t)0xfe2, + (q15_t)0x204, (q15_t)0xfee, (q15_t)0x207, (q15_t)0xffb, (q15_t)0x20a, (q15_t)0x1007, (q15_t)0x20d, (q15_t)0x1013, + (q15_t)0x210, (q15_t)0x101f, (q15_t)0x213, (q15_t)0x102b, (q15_t)0x217, (q15_t)0x1037, (q15_t)0x21a, (q15_t)0x1044, + (q15_t)0x21d, (q15_t)0x1050, (q15_t)0x220, (q15_t)0x105c, (q15_t)0x223, (q15_t)0x1068, (q15_t)0x227, (q15_t)0x1074, + (q15_t)0x22a, (q15_t)0x1080, (q15_t)0x22d, (q15_t)0x108c, (q15_t)0x230, (q15_t)0x1099, (q15_t)0x234, (q15_t)0x10a5, + (q15_t)0x237, (q15_t)0x10b1, (q15_t)0x23a, (q15_t)0x10bd, (q15_t)0x23e, (q15_t)0x10c9, (q15_t)0x241, (q15_t)0x10d5, + (q15_t)0x244, (q15_t)0x10e1, (q15_t)0x247, (q15_t)0x10ed, (q15_t)0x24b, (q15_t)0x10fa, (q15_t)0x24e, (q15_t)0x1106, + (q15_t)0x251, (q15_t)0x1112, (q15_t)0x255, (q15_t)0x111e, (q15_t)0x258, (q15_t)0x112a, (q15_t)0x25c, (q15_t)0x1136, + (q15_t)0x25f, (q15_t)0x1142, (q15_t)0x262, (q15_t)0x114e, (q15_t)0x266, (q15_t)0x115a, (q15_t)0x269, (q15_t)0x1167, + (q15_t)0x26d, (q15_t)0x1173, (q15_t)0x270, (q15_t)0x117f, (q15_t)0x273, (q15_t)0x118b, (q15_t)0x277, (q15_t)0x1197, + (q15_t)0x27a, (q15_t)0x11a3, (q15_t)0x27e, (q15_t)0x11af, (q15_t)0x281, (q15_t)0x11bb, (q15_t)0x285, (q15_t)0x11c7, + (q15_t)0x288, (q15_t)0x11d3, (q15_t)0x28c, (q15_t)0x11df, (q15_t)0x28f, (q15_t)0x11eb, (q15_t)0x293, (q15_t)0x11f7, + (q15_t)0x296, (q15_t)0x1204, (q15_t)0x29a, (q15_t)0x1210, (q15_t)0x29d, (q15_t)0x121c, (q15_t)0x2a1, (q15_t)0x1228, + (q15_t)0x2a5, (q15_t)0x1234, (q15_t)0x2a8, (q15_t)0x1240, (q15_t)0x2ac, (q15_t)0x124c, (q15_t)0x2af, (q15_t)0x1258, + (q15_t)0x2b3, (q15_t)0x1264, (q15_t)0x2b7, (q15_t)0x1270, (q15_t)0x2ba, (q15_t)0x127c, (q15_t)0x2be, (q15_t)0x1288, + (q15_t)0x2c1, (q15_t)0x1294, (q15_t)0x2c5, (q15_t)0x12a0, (q15_t)0x2c9, (q15_t)0x12ac, (q15_t)0x2cc, (q15_t)0x12b8, + (q15_t)0x2d0, (q15_t)0x12c4, (q15_t)0x2d4, (q15_t)0x12d0, (q15_t)0x2d8, (q15_t)0x12dc, (q15_t)0x2db, (q15_t)0x12e8, + (q15_t)0x2df, (q15_t)0x12f4, (q15_t)0x2e3, (q15_t)0x1300, (q15_t)0x2e6, (q15_t)0x130c, (q15_t)0x2ea, (q15_t)0x1318, + (q15_t)0x2ee, (q15_t)0x1324, (q15_t)0x2f2, (q15_t)0x1330, (q15_t)0x2f5, (q15_t)0x133c, (q15_t)0x2f9, (q15_t)0x1348, + (q15_t)0x2fd, (q15_t)0x1354, (q15_t)0x301, (q15_t)0x1360, (q15_t)0x305, (q15_t)0x136c, (q15_t)0x308, (q15_t)0x1378, + (q15_t)0x30c, (q15_t)0x1384, (q15_t)0x310, (q15_t)0x1390, (q15_t)0x314, (q15_t)0x139c, (q15_t)0x318, (q15_t)0x13a8, + (q15_t)0x31c, (q15_t)0x13b4, (q15_t)0x320, (q15_t)0x13c0, (q15_t)0x323, (q15_t)0x13cc, (q15_t)0x327, (q15_t)0x13d8, + (q15_t)0x32b, (q15_t)0x13e4, (q15_t)0x32f, (q15_t)0x13f0, (q15_t)0x333, (q15_t)0x13fb, (q15_t)0x337, (q15_t)0x1407, + (q15_t)0x33b, (q15_t)0x1413, (q15_t)0x33f, (q15_t)0x141f, (q15_t)0x343, (q15_t)0x142b, (q15_t)0x347, (q15_t)0x1437, + (q15_t)0x34b, (q15_t)0x1443, (q15_t)0x34f, (q15_t)0x144f, (q15_t)0x353, (q15_t)0x145b, (q15_t)0x357, (q15_t)0x1467, + (q15_t)0x35b, (q15_t)0x1473, (q15_t)0x35f, (q15_t)0x147f, (q15_t)0x363, (q15_t)0x148b, (q15_t)0x367, (q15_t)0x1496, + (q15_t)0x36b, (q15_t)0x14a2, (q15_t)0x36f, (q15_t)0x14ae, (q15_t)0x373, (q15_t)0x14ba, (q15_t)0x377, (q15_t)0x14c6, + (q15_t)0x37b, (q15_t)0x14d2, (q15_t)0x37f, (q15_t)0x14de, (q15_t)0x383, (q15_t)0x14ea, (q15_t)0x387, (q15_t)0x14f6, + (q15_t)0x38c, (q15_t)0x1501, (q15_t)0x390, (q15_t)0x150d, (q15_t)0x394, (q15_t)0x1519, (q15_t)0x398, (q15_t)0x1525, + (q15_t)0x39c, (q15_t)0x1531, (q15_t)0x3a0, (q15_t)0x153d, (q15_t)0x3a5, (q15_t)0x1549, (q15_t)0x3a9, (q15_t)0x1554, + (q15_t)0x3ad, (q15_t)0x1560, (q15_t)0x3b1, (q15_t)0x156c, (q15_t)0x3b5, (q15_t)0x1578, (q15_t)0x3ba, (q15_t)0x1584, + (q15_t)0x3be, (q15_t)0x1590, (q15_t)0x3c2, (q15_t)0x159b, (q15_t)0x3c6, (q15_t)0x15a7, (q15_t)0x3ca, (q15_t)0x15b3, + (q15_t)0x3cf, (q15_t)0x15bf, (q15_t)0x3d3, (q15_t)0x15cb, (q15_t)0x3d7, (q15_t)0x15d7, (q15_t)0x3dc, (q15_t)0x15e2, + (q15_t)0x3e0, (q15_t)0x15ee, (q15_t)0x3e4, (q15_t)0x15fa, (q15_t)0x3e9, (q15_t)0x1606, (q15_t)0x3ed, (q15_t)0x1612, + (q15_t)0x3f1, (q15_t)0x161d, (q15_t)0x3f6, (q15_t)0x1629, (q15_t)0x3fa, (q15_t)0x1635, (q15_t)0x3fe, (q15_t)0x1641, + (q15_t)0x403, (q15_t)0x164c, (q15_t)0x407, (q15_t)0x1658, (q15_t)0x40b, (q15_t)0x1664, (q15_t)0x410, (q15_t)0x1670, + (q15_t)0x414, (q15_t)0x167c, (q15_t)0x419, (q15_t)0x1687, (q15_t)0x41d, (q15_t)0x1693, (q15_t)0x422, (q15_t)0x169f, + (q15_t)0x426, (q15_t)0x16ab, (q15_t)0x42a, (q15_t)0x16b6, (q15_t)0x42f, (q15_t)0x16c2, (q15_t)0x433, (q15_t)0x16ce, + (q15_t)0x438, (q15_t)0x16da, (q15_t)0x43c, (q15_t)0x16e5, (q15_t)0x441, (q15_t)0x16f1, (q15_t)0x445, (q15_t)0x16fd, + (q15_t)0x44a, (q15_t)0x1709, (q15_t)0x44e, (q15_t)0x1714, (q15_t)0x453, (q15_t)0x1720, (q15_t)0x457, (q15_t)0x172c, + (q15_t)0x45c, (q15_t)0x1737, (q15_t)0x461, (q15_t)0x1743, (q15_t)0x465, (q15_t)0x174f, (q15_t)0x46a, (q15_t)0x175b, + (q15_t)0x46e, (q15_t)0x1766, (q15_t)0x473, (q15_t)0x1772, (q15_t)0x478, (q15_t)0x177e, (q15_t)0x47c, (q15_t)0x1789, + (q15_t)0x481, (q15_t)0x1795, (q15_t)0x485, (q15_t)0x17a1, (q15_t)0x48a, (q15_t)0x17ac, (q15_t)0x48f, (q15_t)0x17b8, + (q15_t)0x493, (q15_t)0x17c4, (q15_t)0x498, (q15_t)0x17cf, (q15_t)0x49d, (q15_t)0x17db, (q15_t)0x4a1, (q15_t)0x17e7, + (q15_t)0x4a6, (q15_t)0x17f2, (q15_t)0x4ab, (q15_t)0x17fe, (q15_t)0x4b0, (q15_t)0x180a, (q15_t)0x4b4, (q15_t)0x1815, + (q15_t)0x4b9, (q15_t)0x1821, (q15_t)0x4be, (q15_t)0x182d, (q15_t)0x4c2, (q15_t)0x1838, (q15_t)0x4c7, (q15_t)0x1844, + (q15_t)0x4cc, (q15_t)0x184f, (q15_t)0x4d1, (q15_t)0x185b, (q15_t)0x4d6, (q15_t)0x1867, (q15_t)0x4da, (q15_t)0x1872, + (q15_t)0x4df, (q15_t)0x187e, (q15_t)0x4e4, (q15_t)0x1889, (q15_t)0x4e9, (q15_t)0x1895, (q15_t)0x4ee, (q15_t)0x18a1, + (q15_t)0x4f2, (q15_t)0x18ac, (q15_t)0x4f7, (q15_t)0x18b8, (q15_t)0x4fc, (q15_t)0x18c3, (q15_t)0x501, (q15_t)0x18cf, + (q15_t)0x506, (q15_t)0x18db, (q15_t)0x50b, (q15_t)0x18e6, (q15_t)0x510, (q15_t)0x18f2, (q15_t)0x515, (q15_t)0x18fd, + (q15_t)0x51a, (q15_t)0x1909, (q15_t)0x51e, (q15_t)0x1914, (q15_t)0x523, (q15_t)0x1920, (q15_t)0x528, (q15_t)0x192c, + (q15_t)0x52d, (q15_t)0x1937, (q15_t)0x532, (q15_t)0x1943, (q15_t)0x537, (q15_t)0x194e, (q15_t)0x53c, (q15_t)0x195a, + (q15_t)0x541, (q15_t)0x1965, (q15_t)0x546, (q15_t)0x1971, (q15_t)0x54b, (q15_t)0x197c, (q15_t)0x550, (q15_t)0x1988, + (q15_t)0x555, (q15_t)0x1993, (q15_t)0x55a, (q15_t)0x199f, (q15_t)0x55f, (q15_t)0x19aa, (q15_t)0x564, (q15_t)0x19b6, + (q15_t)0x569, (q15_t)0x19c1, (q15_t)0x56e, (q15_t)0x19cd, (q15_t)0x573, (q15_t)0x19d8, (q15_t)0x578, (q15_t)0x19e4, + (q15_t)0x57e, (q15_t)0x19ef, (q15_t)0x583, (q15_t)0x19fb, (q15_t)0x588, (q15_t)0x1a06, (q15_t)0x58d, (q15_t)0x1a12, + (q15_t)0x592, (q15_t)0x1a1d, (q15_t)0x597, (q15_t)0x1a29, (q15_t)0x59c, (q15_t)0x1a34, (q15_t)0x5a1, (q15_t)0x1a40, + (q15_t)0x5a7, (q15_t)0x1a4b, (q15_t)0x5ac, (q15_t)0x1a57, (q15_t)0x5b1, (q15_t)0x1a62, (q15_t)0x5b6, (q15_t)0x1a6e, + (q15_t)0x5bb, (q15_t)0x1a79, (q15_t)0x5c1, (q15_t)0x1a84, (q15_t)0x5c6, (q15_t)0x1a90, (q15_t)0x5cb, (q15_t)0x1a9b, + (q15_t)0x5d0, (q15_t)0x1aa7, (q15_t)0x5d5, (q15_t)0x1ab2, (q15_t)0x5db, (q15_t)0x1abe, (q15_t)0x5e0, (q15_t)0x1ac9, + (q15_t)0x5e5, (q15_t)0x1ad4, (q15_t)0x5ea, (q15_t)0x1ae0, (q15_t)0x5f0, (q15_t)0x1aeb, (q15_t)0x5f5, (q15_t)0x1af7, + (q15_t)0x5fa, (q15_t)0x1b02, (q15_t)0x600, (q15_t)0x1b0d, (q15_t)0x605, (q15_t)0x1b19, (q15_t)0x60a, (q15_t)0x1b24, + (q15_t)0x610, (q15_t)0x1b30, (q15_t)0x615, (q15_t)0x1b3b, (q15_t)0x61a, (q15_t)0x1b46, (q15_t)0x620, (q15_t)0x1b52, + (q15_t)0x625, (q15_t)0x1b5d, (q15_t)0x62a, (q15_t)0x1b68, (q15_t)0x630, (q15_t)0x1b74, (q15_t)0x635, (q15_t)0x1b7f, + (q15_t)0x63b, (q15_t)0x1b8a, (q15_t)0x640, (q15_t)0x1b96, (q15_t)0x645, (q15_t)0x1ba1, (q15_t)0x64b, (q15_t)0x1bac, + (q15_t)0x650, (q15_t)0x1bb8, (q15_t)0x656, (q15_t)0x1bc3, (q15_t)0x65b, (q15_t)0x1bce, (q15_t)0x661, (q15_t)0x1bda, + (q15_t)0x666, (q15_t)0x1be5, (q15_t)0x66c, (q15_t)0x1bf0, (q15_t)0x671, (q15_t)0x1bfc, (q15_t)0x677, (q15_t)0x1c07, + (q15_t)0x67c, (q15_t)0x1c12, (q15_t)0x682, (q15_t)0x1c1e, (q15_t)0x687, (q15_t)0x1c29, (q15_t)0x68d, (q15_t)0x1c34, + (q15_t)0x692, (q15_t)0x1c3f, (q15_t)0x698, (q15_t)0x1c4b, (q15_t)0x69d, (q15_t)0x1c56, (q15_t)0x6a3, (q15_t)0x1c61, + (q15_t)0x6a8, (q15_t)0x1c6c, (q15_t)0x6ae, (q15_t)0x1c78, (q15_t)0x6b4, (q15_t)0x1c83, (q15_t)0x6b9, (q15_t)0x1c8e, + (q15_t)0x6bf, (q15_t)0x1c99, (q15_t)0x6c5, (q15_t)0x1ca5, (q15_t)0x6ca, (q15_t)0x1cb0, (q15_t)0x6d0, (q15_t)0x1cbb, + (q15_t)0x6d5, (q15_t)0x1cc6, (q15_t)0x6db, (q15_t)0x1cd2, (q15_t)0x6e1, (q15_t)0x1cdd, (q15_t)0x6e6, (q15_t)0x1ce8, + (q15_t)0x6ec, (q15_t)0x1cf3, (q15_t)0x6f2, (q15_t)0x1cff, (q15_t)0x6f7, (q15_t)0x1d0a, (q15_t)0x6fd, (q15_t)0x1d15, + (q15_t)0x703, (q15_t)0x1d20, (q15_t)0x709, (q15_t)0x1d2b, (q15_t)0x70e, (q15_t)0x1d36, (q15_t)0x714, (q15_t)0x1d42, + (q15_t)0x71a, (q15_t)0x1d4d, (q15_t)0x720, (q15_t)0x1d58, (q15_t)0x725, (q15_t)0x1d63, (q15_t)0x72b, (q15_t)0x1d6e, + (q15_t)0x731, (q15_t)0x1d79, (q15_t)0x737, (q15_t)0x1d85, (q15_t)0x73d, (q15_t)0x1d90, (q15_t)0x742, (q15_t)0x1d9b, + (q15_t)0x748, (q15_t)0x1da6, (q15_t)0x74e, (q15_t)0x1db1, (q15_t)0x754, (q15_t)0x1dbc, (q15_t)0x75a, (q15_t)0x1dc7, + (q15_t)0x75f, (q15_t)0x1dd3, (q15_t)0x765, (q15_t)0x1dde, (q15_t)0x76b, (q15_t)0x1de9, (q15_t)0x771, (q15_t)0x1df4, + (q15_t)0x777, (q15_t)0x1dff, (q15_t)0x77d, (q15_t)0x1e0a, (q15_t)0x783, (q15_t)0x1e15, (q15_t)0x789, (q15_t)0x1e20, + (q15_t)0x78f, (q15_t)0x1e2b, (q15_t)0x795, (q15_t)0x1e36, (q15_t)0x79a, (q15_t)0x1e42, (q15_t)0x7a0, (q15_t)0x1e4d, + (q15_t)0x7a6, (q15_t)0x1e58, (q15_t)0x7ac, (q15_t)0x1e63, (q15_t)0x7b2, (q15_t)0x1e6e, (q15_t)0x7b8, (q15_t)0x1e79, + (q15_t)0x7be, (q15_t)0x1e84, (q15_t)0x7c4, (q15_t)0x1e8f, (q15_t)0x7ca, (q15_t)0x1e9a, (q15_t)0x7d0, (q15_t)0x1ea5, + (q15_t)0x7d6, (q15_t)0x1eb0, (q15_t)0x7dc, (q15_t)0x1ebb, (q15_t)0x7e2, (q15_t)0x1ec6, (q15_t)0x7e8, (q15_t)0x1ed1, + (q15_t)0x7ee, (q15_t)0x1edc, (q15_t)0x7f5, (q15_t)0x1ee7, (q15_t)0x7fb, (q15_t)0x1ef2, (q15_t)0x801, (q15_t)0x1efd, + (q15_t)0x807, (q15_t)0x1f08, (q15_t)0x80d, (q15_t)0x1f13, (q15_t)0x813, (q15_t)0x1f1e, (q15_t)0x819, (q15_t)0x1f29, + (q15_t)0x81f, (q15_t)0x1f34, (q15_t)0x825, (q15_t)0x1f3f, (q15_t)0x82b, (q15_t)0x1f4a, (q15_t)0x832, (q15_t)0x1f55, + (q15_t)0x838, (q15_t)0x1f60, (q15_t)0x83e, (q15_t)0x1f6b, (q15_t)0x844, (q15_t)0x1f76, (q15_t)0x84a, (q15_t)0x1f81, + (q15_t)0x850, (q15_t)0x1f8c, (q15_t)0x857, (q15_t)0x1f97, (q15_t)0x85d, (q15_t)0x1fa2, (q15_t)0x863, (q15_t)0x1fac, + (q15_t)0x869, (q15_t)0x1fb7, (q15_t)0x870, (q15_t)0x1fc2, (q15_t)0x876, (q15_t)0x1fcd, (q15_t)0x87c, (q15_t)0x1fd8, + (q15_t)0x882, (q15_t)0x1fe3, (q15_t)0x889, (q15_t)0x1fee, (q15_t)0x88f, (q15_t)0x1ff9, (q15_t)0x895, (q15_t)0x2004, + (q15_t)0x89b, (q15_t)0x200f, (q15_t)0x8a2, (q15_t)0x2019, (q15_t)0x8a8, (q15_t)0x2024, (q15_t)0x8ae, (q15_t)0x202f, + (q15_t)0x8b5, (q15_t)0x203a, (q15_t)0x8bb, (q15_t)0x2045, (q15_t)0x8c1, (q15_t)0x2050, (q15_t)0x8c8, (q15_t)0x205b, + (q15_t)0x8ce, (q15_t)0x2065, (q15_t)0x8d4, (q15_t)0x2070, (q15_t)0x8db, (q15_t)0x207b, (q15_t)0x8e1, (q15_t)0x2086, + (q15_t)0x8e8, (q15_t)0x2091, (q15_t)0x8ee, (q15_t)0x209b, (q15_t)0x8f4, (q15_t)0x20a6, (q15_t)0x8fb, (q15_t)0x20b1, + (q15_t)0x901, (q15_t)0x20bc, (q15_t)0x908, (q15_t)0x20c7, (q15_t)0x90e, (q15_t)0x20d1, (q15_t)0x915, (q15_t)0x20dc, + (q15_t)0x91b, (q15_t)0x20e7, (q15_t)0x921, (q15_t)0x20f2, (q15_t)0x928, (q15_t)0x20fd, (q15_t)0x92e, (q15_t)0x2107, + (q15_t)0x935, (q15_t)0x2112, (q15_t)0x93b, (q15_t)0x211d, (q15_t)0x942, (q15_t)0x2128, (q15_t)0x948, (q15_t)0x2132, + (q15_t)0x94f, (q15_t)0x213d, (q15_t)0x955, (q15_t)0x2148, (q15_t)0x95c, (q15_t)0x2153, (q15_t)0x963, (q15_t)0x215d, + (q15_t)0x969, (q15_t)0x2168, (q15_t)0x970, (q15_t)0x2173, (q15_t)0x976, (q15_t)0x217d, (q15_t)0x97d, (q15_t)0x2188, + (q15_t)0x983, (q15_t)0x2193, (q15_t)0x98a, (q15_t)0x219e, (q15_t)0x991, (q15_t)0x21a8, (q15_t)0x997, (q15_t)0x21b3, + (q15_t)0x99e, (q15_t)0x21be, (q15_t)0x9a4, (q15_t)0x21c8, (q15_t)0x9ab, (q15_t)0x21d3, (q15_t)0x9b2, (q15_t)0x21de, + (q15_t)0x9b8, (q15_t)0x21e8, (q15_t)0x9bf, (q15_t)0x21f3, (q15_t)0x9c6, (q15_t)0x21fe, (q15_t)0x9cc, (q15_t)0x2208, + (q15_t)0x9d3, (q15_t)0x2213, (q15_t)0x9da, (q15_t)0x221e, (q15_t)0x9e0, (q15_t)0x2228, (q15_t)0x9e7, (q15_t)0x2233, + (q15_t)0x9ee, (q15_t)0x223d, (q15_t)0x9f5, (q15_t)0x2248, (q15_t)0x9fb, (q15_t)0x2253, (q15_t)0xa02, (q15_t)0x225d, + (q15_t)0xa09, (q15_t)0x2268, (q15_t)0xa10, (q15_t)0x2272, (q15_t)0xa16, (q15_t)0x227d, (q15_t)0xa1d, (q15_t)0x2288, + (q15_t)0xa24, (q15_t)0x2292, (q15_t)0xa2b, (q15_t)0x229d, (q15_t)0xa32, (q15_t)0x22a7, (q15_t)0xa38, (q15_t)0x22b2, + (q15_t)0xa3f, (q15_t)0x22bc, (q15_t)0xa46, (q15_t)0x22c7, (q15_t)0xa4d, (q15_t)0x22d2, (q15_t)0xa54, (q15_t)0x22dc, + (q15_t)0xa5b, (q15_t)0x22e7, (q15_t)0xa61, (q15_t)0x22f1, (q15_t)0xa68, (q15_t)0x22fc, (q15_t)0xa6f, (q15_t)0x2306, + (q15_t)0xa76, (q15_t)0x2311, (q15_t)0xa7d, (q15_t)0x231b, (q15_t)0xa84, (q15_t)0x2326, (q15_t)0xa8b, (q15_t)0x2330, + (q15_t)0xa92, (q15_t)0x233b, (q15_t)0xa99, (q15_t)0x2345, (q15_t)0xa9f, (q15_t)0x2350, (q15_t)0xaa6, (q15_t)0x235a, + (q15_t)0xaad, (q15_t)0x2365, (q15_t)0xab4, (q15_t)0x236f, (q15_t)0xabb, (q15_t)0x237a, (q15_t)0xac2, (q15_t)0x2384, + (q15_t)0xac9, (q15_t)0x238e, (q15_t)0xad0, (q15_t)0x2399, (q15_t)0xad7, (q15_t)0x23a3, (q15_t)0xade, (q15_t)0x23ae, + (q15_t)0xae5, (q15_t)0x23b8, (q15_t)0xaec, (q15_t)0x23c3, (q15_t)0xaf3, (q15_t)0x23cd, (q15_t)0xafa, (q15_t)0x23d7, + (q15_t)0xb01, (q15_t)0x23e2, (q15_t)0xb08, (q15_t)0x23ec, (q15_t)0xb0f, (q15_t)0x23f7, (q15_t)0xb16, (q15_t)0x2401, + (q15_t)0xb1e, (q15_t)0x240b, (q15_t)0xb25, (q15_t)0x2416, (q15_t)0xb2c, (q15_t)0x2420, (q15_t)0xb33, (q15_t)0x242b, + (q15_t)0xb3a, (q15_t)0x2435, (q15_t)0xb41, (q15_t)0x243f, (q15_t)0xb48, (q15_t)0x244a, (q15_t)0xb4f, (q15_t)0x2454, + (q15_t)0xb56, (q15_t)0x245e, (q15_t)0xb5e, (q15_t)0x2469, (q15_t)0xb65, (q15_t)0x2473, (q15_t)0xb6c, (q15_t)0x247d, + (q15_t)0xb73, (q15_t)0x2488, (q15_t)0xb7a, (q15_t)0x2492, (q15_t)0xb81, (q15_t)0x249c, (q15_t)0xb89, (q15_t)0x24a7, + (q15_t)0xb90, (q15_t)0x24b1, (q15_t)0xb97, (q15_t)0x24bb, (q15_t)0xb9e, (q15_t)0x24c5, (q15_t)0xba5, (q15_t)0x24d0, + (q15_t)0xbad, (q15_t)0x24da, (q15_t)0xbb4, (q15_t)0x24e4, (q15_t)0xbbb, (q15_t)0x24ef, (q15_t)0xbc2, (q15_t)0x24f9, + (q15_t)0xbca, (q15_t)0x2503, (q15_t)0xbd1, (q15_t)0x250d, (q15_t)0xbd8, (q15_t)0x2518, (q15_t)0xbe0, (q15_t)0x2522, + (q15_t)0xbe7, (q15_t)0x252c, (q15_t)0xbee, (q15_t)0x2536, (q15_t)0xbf5, (q15_t)0x2541, (q15_t)0xbfd, (q15_t)0x254b, + (q15_t)0xc04, (q15_t)0x2555, (q15_t)0xc0b, (q15_t)0x255f, (q15_t)0xc13, (q15_t)0x2569, (q15_t)0xc1a, (q15_t)0x2574, + (q15_t)0xc21, (q15_t)0x257e, (q15_t)0xc29, (q15_t)0x2588, (q15_t)0xc30, (q15_t)0x2592, (q15_t)0xc38, (q15_t)0x259c, + (q15_t)0xc3f, (q15_t)0x25a6, (q15_t)0xc46, (q15_t)0x25b1, (q15_t)0xc4e, (q15_t)0x25bb, (q15_t)0xc55, (q15_t)0x25c5, + (q15_t)0xc5d, (q15_t)0x25cf, (q15_t)0xc64, (q15_t)0x25d9, (q15_t)0xc6b, (q15_t)0x25e3, (q15_t)0xc73, (q15_t)0x25ed, + (q15_t)0xc7a, (q15_t)0x25f8, (q15_t)0xc82, (q15_t)0x2602, (q15_t)0xc89, (q15_t)0x260c, (q15_t)0xc91, (q15_t)0x2616, + (q15_t)0xc98, (q15_t)0x2620, (q15_t)0xca0, (q15_t)0x262a, (q15_t)0xca7, (q15_t)0x2634, (q15_t)0xcaf, (q15_t)0x263e, + (q15_t)0xcb6, (q15_t)0x2648, (q15_t)0xcbe, (q15_t)0x2652, (q15_t)0xcc5, (q15_t)0x265c, (q15_t)0xccd, (q15_t)0x2666, + (q15_t)0xcd4, (q15_t)0x2671, (q15_t)0xcdc, (q15_t)0x267b, (q15_t)0xce3, (q15_t)0x2685, (q15_t)0xceb, (q15_t)0x268f, + (q15_t)0xcf3, (q15_t)0x2699, (q15_t)0xcfa, (q15_t)0x26a3, (q15_t)0xd02, (q15_t)0x26ad, (q15_t)0xd09, (q15_t)0x26b7, + (q15_t)0xd11, (q15_t)0x26c1, (q15_t)0xd19, (q15_t)0x26cb, (q15_t)0xd20, (q15_t)0x26d5, (q15_t)0xd28, (q15_t)0x26df, + (q15_t)0xd30, (q15_t)0x26e9, (q15_t)0xd37, (q15_t)0x26f3, (q15_t)0xd3f, (q15_t)0x26fd, (q15_t)0xd46, (q15_t)0x2707, + (q15_t)0xd4e, (q15_t)0x2711, (q15_t)0xd56, (q15_t)0x271a, (q15_t)0xd5d, (q15_t)0x2724, (q15_t)0xd65, (q15_t)0x272e, + (q15_t)0xd6d, (q15_t)0x2738, (q15_t)0xd75, (q15_t)0x2742, (q15_t)0xd7c, (q15_t)0x274c, (q15_t)0xd84, (q15_t)0x2756, + (q15_t)0xd8c, (q15_t)0x2760, (q15_t)0xd93, (q15_t)0x276a, (q15_t)0xd9b, (q15_t)0x2774, (q15_t)0xda3, (q15_t)0x277e, + (q15_t)0xdab, (q15_t)0x2788, (q15_t)0xdb2, (q15_t)0x2791, (q15_t)0xdba, (q15_t)0x279b, (q15_t)0xdc2, (q15_t)0x27a5, + (q15_t)0xdca, (q15_t)0x27af, (q15_t)0xdd2, (q15_t)0x27b9, (q15_t)0xdd9, (q15_t)0x27c3, (q15_t)0xde1, (q15_t)0x27cd, + (q15_t)0xde9, (q15_t)0x27d6, (q15_t)0xdf1, (q15_t)0x27e0, (q15_t)0xdf9, (q15_t)0x27ea, (q15_t)0xe01, (q15_t)0x27f4, + (q15_t)0xe08, (q15_t)0x27fe, (q15_t)0xe10, (q15_t)0x2808, (q15_t)0xe18, (q15_t)0x2811, (q15_t)0xe20, (q15_t)0x281b, + (q15_t)0xe28, (q15_t)0x2825, (q15_t)0xe30, (q15_t)0x282f, (q15_t)0xe38, (q15_t)0x2838, (q15_t)0xe40, (q15_t)0x2842, + (q15_t)0xe47, (q15_t)0x284c, (q15_t)0xe4f, (q15_t)0x2856, (q15_t)0xe57, (q15_t)0x2860, (q15_t)0xe5f, (q15_t)0x2869, + (q15_t)0xe67, (q15_t)0x2873, (q15_t)0xe6f, (q15_t)0x287d, (q15_t)0xe77, (q15_t)0x2886, (q15_t)0xe7f, (q15_t)0x2890, + (q15_t)0xe87, (q15_t)0x289a, (q15_t)0xe8f, (q15_t)0x28a4, (q15_t)0xe97, (q15_t)0x28ad, (q15_t)0xe9f, (q15_t)0x28b7, + (q15_t)0xea7, (q15_t)0x28c1, (q15_t)0xeaf, (q15_t)0x28ca, (q15_t)0xeb7, (q15_t)0x28d4, (q15_t)0xebf, (q15_t)0x28de, + (q15_t)0xec7, (q15_t)0x28e7, (q15_t)0xecf, (q15_t)0x28f1, (q15_t)0xed7, (q15_t)0x28fb, (q15_t)0xedf, (q15_t)0x2904, + (q15_t)0xee7, (q15_t)0x290e, (q15_t)0xeef, (q15_t)0x2918, (q15_t)0xef7, (q15_t)0x2921, (q15_t)0xeff, (q15_t)0x292b, + (q15_t)0xf07, (q15_t)0x2935, (q15_t)0xf10, (q15_t)0x293e, (q15_t)0xf18, (q15_t)0x2948, (q15_t)0xf20, (q15_t)0x2951, + (q15_t)0xf28, (q15_t)0x295b, (q15_t)0xf30, (q15_t)0x2965, (q15_t)0xf38, (q15_t)0x296e, (q15_t)0xf40, (q15_t)0x2978, + (q15_t)0xf48, (q15_t)0x2981, (q15_t)0xf51, (q15_t)0x298b, (q15_t)0xf59, (q15_t)0x2994, (q15_t)0xf61, (q15_t)0x299e, + (q15_t)0xf69, (q15_t)0x29a7, (q15_t)0xf71, (q15_t)0x29b1, (q15_t)0xf79, (q15_t)0x29bb, (q15_t)0xf82, (q15_t)0x29c4, + (q15_t)0xf8a, (q15_t)0x29ce, (q15_t)0xf92, (q15_t)0x29d7, (q15_t)0xf9a, (q15_t)0x29e1, (q15_t)0xfa3, (q15_t)0x29ea, + (q15_t)0xfab, (q15_t)0x29f4, (q15_t)0xfb3, (q15_t)0x29fd, (q15_t)0xfbb, (q15_t)0x2a07, (q15_t)0xfc4, (q15_t)0x2a10, + (q15_t)0xfcc, (q15_t)0x2a1a, (q15_t)0xfd4, (q15_t)0x2a23, (q15_t)0xfdc, (q15_t)0x2a2c, (q15_t)0xfe5, (q15_t)0x2a36, + (q15_t)0xfed, (q15_t)0x2a3f, (q15_t)0xff5, (q15_t)0x2a49, (q15_t)0xffe, (q15_t)0x2a52, (q15_t)0x1006, (q15_t)0x2a5c, + (q15_t)0x100e, (q15_t)0x2a65, (q15_t)0x1016, (q15_t)0x2a6e, (q15_t)0x101f, (q15_t)0x2a78, (q15_t)0x1027, (q15_t)0x2a81, + (q15_t)0x1030, (q15_t)0x2a8b, (q15_t)0x1038, (q15_t)0x2a94, (q15_t)0x1040, (q15_t)0x2a9d, (q15_t)0x1049, (q15_t)0x2aa7, + (q15_t)0x1051, (q15_t)0x2ab0, (q15_t)0x1059, (q15_t)0x2ab9, (q15_t)0x1062, (q15_t)0x2ac3, (q15_t)0x106a, (q15_t)0x2acc, + (q15_t)0x1073, (q15_t)0x2ad6, (q15_t)0x107b, (q15_t)0x2adf, (q15_t)0x1083, (q15_t)0x2ae8, (q15_t)0x108c, (q15_t)0x2af2, + (q15_t)0x1094, (q15_t)0x2afb, (q15_t)0x109d, (q15_t)0x2b04, (q15_t)0x10a5, (q15_t)0x2b0d, (q15_t)0x10ae, (q15_t)0x2b17, + (q15_t)0x10b6, (q15_t)0x2b20, (q15_t)0x10bf, (q15_t)0x2b29, (q15_t)0x10c7, (q15_t)0x2b33, (q15_t)0x10d0, (q15_t)0x2b3c, + (q15_t)0x10d8, (q15_t)0x2b45, (q15_t)0x10e0, (q15_t)0x2b4e, (q15_t)0x10e9, (q15_t)0x2b58, (q15_t)0x10f2, (q15_t)0x2b61, + (q15_t)0x10fa, (q15_t)0x2b6a, (q15_t)0x1103, (q15_t)0x2b73, (q15_t)0x110b, (q15_t)0x2b7d, (q15_t)0x1114, (q15_t)0x2b86, + (q15_t)0x111c, (q15_t)0x2b8f, (q15_t)0x1125, (q15_t)0x2b98, (q15_t)0x112d, (q15_t)0x2ba1, (q15_t)0x1136, (q15_t)0x2bab, + (q15_t)0x113e, (q15_t)0x2bb4, (q15_t)0x1147, (q15_t)0x2bbd, (q15_t)0x1150, (q15_t)0x2bc6, (q15_t)0x1158, (q15_t)0x2bcf, + (q15_t)0x1161, (q15_t)0x2bd8, (q15_t)0x1169, (q15_t)0x2be2, (q15_t)0x1172, (q15_t)0x2beb, (q15_t)0x117b, (q15_t)0x2bf4, + (q15_t)0x1183, (q15_t)0x2bfd, (q15_t)0x118c, (q15_t)0x2c06, (q15_t)0x1195, (q15_t)0x2c0f, (q15_t)0x119d, (q15_t)0x2c18, + (q15_t)0x11a6, (q15_t)0x2c21, (q15_t)0x11af, (q15_t)0x2c2b, (q15_t)0x11b7, (q15_t)0x2c34, (q15_t)0x11c0, (q15_t)0x2c3d, + (q15_t)0x11c9, (q15_t)0x2c46, (q15_t)0x11d1, (q15_t)0x2c4f, (q15_t)0x11da, (q15_t)0x2c58, (q15_t)0x11e3, (q15_t)0x2c61, + (q15_t)0x11eb, (q15_t)0x2c6a, (q15_t)0x11f4, (q15_t)0x2c73, (q15_t)0x11fd, (q15_t)0x2c7c, (q15_t)0x1206, (q15_t)0x2c85, + (q15_t)0x120e, (q15_t)0x2c8e, (q15_t)0x1217, (q15_t)0x2c97, (q15_t)0x1220, (q15_t)0x2ca0, (q15_t)0x1229, (q15_t)0x2ca9, + (q15_t)0x1231, (q15_t)0x2cb2, (q15_t)0x123a, (q15_t)0x2cbb, (q15_t)0x1243, (q15_t)0x2cc4, (q15_t)0x124c, (q15_t)0x2ccd, + (q15_t)0x1255, (q15_t)0x2cd6, (q15_t)0x125d, (q15_t)0x2cdf, (q15_t)0x1266, (q15_t)0x2ce8, (q15_t)0x126f, (q15_t)0x2cf1, + (q15_t)0x1278, (q15_t)0x2cfa, (q15_t)0x1281, (q15_t)0x2d03, (q15_t)0x128a, (q15_t)0x2d0c, (q15_t)0x1292, (q15_t)0x2d15, + (q15_t)0x129b, (q15_t)0x2d1e, (q15_t)0x12a4, (q15_t)0x2d27, (q15_t)0x12ad, (q15_t)0x2d2f, (q15_t)0x12b6, (q15_t)0x2d38, + (q15_t)0x12bf, (q15_t)0x2d41, (q15_t)0x12c8, (q15_t)0x2d4a, (q15_t)0x12d1, (q15_t)0x2d53, (q15_t)0x12d9, (q15_t)0x2d5c, + (q15_t)0x12e2, (q15_t)0x2d65, (q15_t)0x12eb, (q15_t)0x2d6e, (q15_t)0x12f4, (q15_t)0x2d76, (q15_t)0x12fd, (q15_t)0x2d7f, + (q15_t)0x1306, (q15_t)0x2d88, (q15_t)0x130f, (q15_t)0x2d91, (q15_t)0x1318, (q15_t)0x2d9a, (q15_t)0x1321, (q15_t)0x2da3, + (q15_t)0x132a, (q15_t)0x2dab, (q15_t)0x1333, (q15_t)0x2db4, (q15_t)0x133c, (q15_t)0x2dbd, (q15_t)0x1345, (q15_t)0x2dc6, + (q15_t)0x134e, (q15_t)0x2dcf, (q15_t)0x1357, (q15_t)0x2dd7, (q15_t)0x1360, (q15_t)0x2de0, (q15_t)0x1369, (q15_t)0x2de9, + (q15_t)0x1372, (q15_t)0x2df2, (q15_t)0x137b, (q15_t)0x2dfa, (q15_t)0x1384, (q15_t)0x2e03, (q15_t)0x138d, (q15_t)0x2e0c, + (q15_t)0x1396, (q15_t)0x2e15, (q15_t)0x139f, (q15_t)0x2e1d, (q15_t)0x13a8, (q15_t)0x2e26, (q15_t)0x13b1, (q15_t)0x2e2f, + (q15_t)0x13ba, (q15_t)0x2e37, (q15_t)0x13c3, (q15_t)0x2e40, (q15_t)0x13cc, (q15_t)0x2e49, (q15_t)0x13d5, (q15_t)0x2e51, + (q15_t)0x13df, (q15_t)0x2e5a, (q15_t)0x13e8, (q15_t)0x2e63, (q15_t)0x13f1, (q15_t)0x2e6b, (q15_t)0x13fa, (q15_t)0x2e74, + (q15_t)0x1403, (q15_t)0x2e7d, (q15_t)0x140c, (q15_t)0x2e85, (q15_t)0x1415, (q15_t)0x2e8e, (q15_t)0x141e, (q15_t)0x2e97, + (q15_t)0x1428, (q15_t)0x2e9f, (q15_t)0x1431, (q15_t)0x2ea8, (q15_t)0x143a, (q15_t)0x2eb0, (q15_t)0x1443, (q15_t)0x2eb9, + (q15_t)0x144c, (q15_t)0x2ec2, (q15_t)0x1455, (q15_t)0x2eca, (q15_t)0x145f, (q15_t)0x2ed3, (q15_t)0x1468, (q15_t)0x2edb, + (q15_t)0x1471, (q15_t)0x2ee4, (q15_t)0x147a, (q15_t)0x2eec, (q15_t)0x1483, (q15_t)0x2ef5, (q15_t)0x148d, (q15_t)0x2efd, + (q15_t)0x1496, (q15_t)0x2f06, (q15_t)0x149f, (q15_t)0x2f0e, (q15_t)0x14a8, (q15_t)0x2f17, (q15_t)0x14b2, (q15_t)0x2f20, + (q15_t)0x14bb, (q15_t)0x2f28, (q15_t)0x14c4, (q15_t)0x2f30, (q15_t)0x14cd, (q15_t)0x2f39, (q15_t)0x14d7, (q15_t)0x2f41, + (q15_t)0x14e0, (q15_t)0x2f4a, (q15_t)0x14e9, (q15_t)0x2f52, (q15_t)0x14f3, (q15_t)0x2f5b, (q15_t)0x14fc, (q15_t)0x2f63, + (q15_t)0x1505, (q15_t)0x2f6c, (q15_t)0x150e, (q15_t)0x2f74, (q15_t)0x1518, (q15_t)0x2f7d, (q15_t)0x1521, (q15_t)0x2f85, + (q15_t)0x152a, (q15_t)0x2f8d, (q15_t)0x1534, (q15_t)0x2f96, (q15_t)0x153d, (q15_t)0x2f9e, (q15_t)0x1547, (q15_t)0x2fa7, + (q15_t)0x1550, (q15_t)0x2faf, (q15_t)0x1559, (q15_t)0x2fb7, (q15_t)0x1563, (q15_t)0x2fc0, (q15_t)0x156c, (q15_t)0x2fc8, + (q15_t)0x1575, (q15_t)0x2fd0, (q15_t)0x157f, (q15_t)0x2fd9, (q15_t)0x1588, (q15_t)0x2fe1, (q15_t)0x1592, (q15_t)0x2fea, + (q15_t)0x159b, (q15_t)0x2ff2, (q15_t)0x15a4, (q15_t)0x2ffa, (q15_t)0x15ae, (q15_t)0x3002, (q15_t)0x15b7, (q15_t)0x300b, + (q15_t)0x15c1, (q15_t)0x3013, (q15_t)0x15ca, (q15_t)0x301b, (q15_t)0x15d4, (q15_t)0x3024, (q15_t)0x15dd, (q15_t)0x302c, + (q15_t)0x15e6, (q15_t)0x3034, (q15_t)0x15f0, (q15_t)0x303c, (q15_t)0x15f9, (q15_t)0x3045, (q15_t)0x1603, (q15_t)0x304d, + (q15_t)0x160c, (q15_t)0x3055, (q15_t)0x1616, (q15_t)0x305d, (q15_t)0x161f, (q15_t)0x3066, (q15_t)0x1629, (q15_t)0x306e, + (q15_t)0x1632, (q15_t)0x3076, (q15_t)0x163c, (q15_t)0x307e, (q15_t)0x1645, (q15_t)0x3087, (q15_t)0x164f, (q15_t)0x308f, + (q15_t)0x1659, (q15_t)0x3097, (q15_t)0x1662, (q15_t)0x309f, (q15_t)0x166c, (q15_t)0x30a7, (q15_t)0x1675, (q15_t)0x30af, + (q15_t)0x167f, (q15_t)0x30b8, (q15_t)0x1688, (q15_t)0x30c0, (q15_t)0x1692, (q15_t)0x30c8, (q15_t)0x169b, (q15_t)0x30d0, + (q15_t)0x16a5, (q15_t)0x30d8, (q15_t)0x16af, (q15_t)0x30e0, (q15_t)0x16b8, (q15_t)0x30e8, (q15_t)0x16c2, (q15_t)0x30f0, + (q15_t)0x16cb, (q15_t)0x30f9, (q15_t)0x16d5, (q15_t)0x3101, (q15_t)0x16df, (q15_t)0x3109, (q15_t)0x16e8, (q15_t)0x3111, + (q15_t)0x16f2, (q15_t)0x3119, (q15_t)0x16fc, (q15_t)0x3121, (q15_t)0x1705, (q15_t)0x3129, (q15_t)0x170f, (q15_t)0x3131, + (q15_t)0x1719, (q15_t)0x3139, (q15_t)0x1722, (q15_t)0x3141, (q15_t)0x172c, (q15_t)0x3149, (q15_t)0x1736, (q15_t)0x3151, + (q15_t)0x173f, (q15_t)0x3159, (q15_t)0x1749, (q15_t)0x3161, (q15_t)0x1753, (q15_t)0x3169, (q15_t)0x175c, (q15_t)0x3171, + (q15_t)0x1766, (q15_t)0x3179, (q15_t)0x1770, (q15_t)0x3181, (q15_t)0x177a, (q15_t)0x3189, (q15_t)0x1783, (q15_t)0x3191, + (q15_t)0x178d, (q15_t)0x3199, (q15_t)0x1797, (q15_t)0x31a1, (q15_t)0x17a0, (q15_t)0x31a9, (q15_t)0x17aa, (q15_t)0x31b1, + (q15_t)0x17b4, (q15_t)0x31b9, (q15_t)0x17be, (q15_t)0x31c0, (q15_t)0x17c8, (q15_t)0x31c8, (q15_t)0x17d1, (q15_t)0x31d0, + (q15_t)0x17db, (q15_t)0x31d8, (q15_t)0x17e5, (q15_t)0x31e0, (q15_t)0x17ef, (q15_t)0x31e8, (q15_t)0x17f8, (q15_t)0x31f0, + (q15_t)0x1802, (q15_t)0x31f8, (q15_t)0x180c, (q15_t)0x31ff, (q15_t)0x1816, (q15_t)0x3207, (q15_t)0x1820, (q15_t)0x320f, + (q15_t)0x182a, (q15_t)0x3217, (q15_t)0x1833, (q15_t)0x321f, (q15_t)0x183d, (q15_t)0x3227, (q15_t)0x1847, (q15_t)0x322e, + (q15_t)0x1851, (q15_t)0x3236, (q15_t)0x185b, (q15_t)0x323e, (q15_t)0x1865, (q15_t)0x3246, (q15_t)0x186f, (q15_t)0x324e, + (q15_t)0x1878, (q15_t)0x3255, (q15_t)0x1882, (q15_t)0x325d, (q15_t)0x188c, (q15_t)0x3265, (q15_t)0x1896, (q15_t)0x326d, + (q15_t)0x18a0, (q15_t)0x3274, (q15_t)0x18aa, (q15_t)0x327c, (q15_t)0x18b4, (q15_t)0x3284, (q15_t)0x18be, (q15_t)0x328b, + (q15_t)0x18c8, (q15_t)0x3293, (q15_t)0x18d2, (q15_t)0x329b, (q15_t)0x18dc, (q15_t)0x32a3, (q15_t)0x18e6, (q15_t)0x32aa, + (q15_t)0x18ef, (q15_t)0x32b2, (q15_t)0x18f9, (q15_t)0x32ba, (q15_t)0x1903, (q15_t)0x32c1, (q15_t)0x190d, (q15_t)0x32c9, + (q15_t)0x1917, (q15_t)0x32d0, (q15_t)0x1921, (q15_t)0x32d8, (q15_t)0x192b, (q15_t)0x32e0, (q15_t)0x1935, (q15_t)0x32e7, + (q15_t)0x193f, (q15_t)0x32ef, (q15_t)0x1949, (q15_t)0x32f7, (q15_t)0x1953, (q15_t)0x32fe, (q15_t)0x195d, (q15_t)0x3306, + (q15_t)0x1967, (q15_t)0x330d, (q15_t)0x1971, (q15_t)0x3315, (q15_t)0x197b, (q15_t)0x331d, (q15_t)0x1985, (q15_t)0x3324, + (q15_t)0x198f, (q15_t)0x332c, (q15_t)0x199a, (q15_t)0x3333, (q15_t)0x19a4, (q15_t)0x333b, (q15_t)0x19ae, (q15_t)0x3342, + (q15_t)0x19b8, (q15_t)0x334a, (q15_t)0x19c2, (q15_t)0x3351, (q15_t)0x19cc, (q15_t)0x3359, (q15_t)0x19d6, (q15_t)0x3360, + (q15_t)0x19e0, (q15_t)0x3368, (q15_t)0x19ea, (q15_t)0x336f, (q15_t)0x19f4, (q15_t)0x3377, (q15_t)0x19fe, (q15_t)0x337e, + (q15_t)0x1a08, (q15_t)0x3386, (q15_t)0x1a13, (q15_t)0x338d, (q15_t)0x1a1d, (q15_t)0x3395, (q15_t)0x1a27, (q15_t)0x339c, + (q15_t)0x1a31, (q15_t)0x33a3, (q15_t)0x1a3b, (q15_t)0x33ab, (q15_t)0x1a45, (q15_t)0x33b2, (q15_t)0x1a4f, (q15_t)0x33ba, + (q15_t)0x1a5a, (q15_t)0x33c1, (q15_t)0x1a64, (q15_t)0x33c8, (q15_t)0x1a6e, (q15_t)0x33d0, (q15_t)0x1a78, (q15_t)0x33d7, + (q15_t)0x1a82, (q15_t)0x33df, (q15_t)0x1a8c, (q15_t)0x33e6, (q15_t)0x1a97, (q15_t)0x33ed, (q15_t)0x1aa1, (q15_t)0x33f5, + (q15_t)0x1aab, (q15_t)0x33fc, (q15_t)0x1ab5, (q15_t)0x3403, (q15_t)0x1abf, (q15_t)0x340b, (q15_t)0x1aca, (q15_t)0x3412, + (q15_t)0x1ad4, (q15_t)0x3419, (q15_t)0x1ade, (q15_t)0x3420, (q15_t)0x1ae8, (q15_t)0x3428, (q15_t)0x1af3, (q15_t)0x342f, + (q15_t)0x1afd, (q15_t)0x3436, (q15_t)0x1b07, (q15_t)0x343e, (q15_t)0x1b11, (q15_t)0x3445, (q15_t)0x1b1c, (q15_t)0x344c, + (q15_t)0x1b26, (q15_t)0x3453, (q15_t)0x1b30, (q15_t)0x345b, (q15_t)0x1b3b, (q15_t)0x3462, (q15_t)0x1b45, (q15_t)0x3469, + (q15_t)0x1b4f, (q15_t)0x3470, (q15_t)0x1b59, (q15_t)0x3477, (q15_t)0x1b64, (q15_t)0x347f, (q15_t)0x1b6e, (q15_t)0x3486, + (q15_t)0x1b78, (q15_t)0x348d, (q15_t)0x1b83, (q15_t)0x3494, (q15_t)0x1b8d, (q15_t)0x349b, (q15_t)0x1b97, (q15_t)0x34a2, + (q15_t)0x1ba2, (q15_t)0x34aa, (q15_t)0x1bac, (q15_t)0x34b1, (q15_t)0x1bb6, (q15_t)0x34b8, (q15_t)0x1bc1, (q15_t)0x34bf, + (q15_t)0x1bcb, (q15_t)0x34c6, (q15_t)0x1bd5, (q15_t)0x34cd, (q15_t)0x1be0, (q15_t)0x34d4, (q15_t)0x1bea, (q15_t)0x34db, + (q15_t)0x1bf5, (q15_t)0x34e2, (q15_t)0x1bff, (q15_t)0x34ea, (q15_t)0x1c09, (q15_t)0x34f1, (q15_t)0x1c14, (q15_t)0x34f8, + (q15_t)0x1c1e, (q15_t)0x34ff, (q15_t)0x1c29, (q15_t)0x3506, (q15_t)0x1c33, (q15_t)0x350d, (q15_t)0x1c3d, (q15_t)0x3514, + (q15_t)0x1c48, (q15_t)0x351b, (q15_t)0x1c52, (q15_t)0x3522, (q15_t)0x1c5d, (q15_t)0x3529, (q15_t)0x1c67, (q15_t)0x3530, + (q15_t)0x1c72, (q15_t)0x3537, (q15_t)0x1c7c, (q15_t)0x353e, (q15_t)0x1c86, (q15_t)0x3545, (q15_t)0x1c91, (q15_t)0x354c, + (q15_t)0x1c9b, (q15_t)0x3553, (q15_t)0x1ca6, (q15_t)0x355a, (q15_t)0x1cb0, (q15_t)0x3561, (q15_t)0x1cbb, (q15_t)0x3567, + (q15_t)0x1cc5, (q15_t)0x356e, (q15_t)0x1cd0, (q15_t)0x3575, (q15_t)0x1cda, (q15_t)0x357c, (q15_t)0x1ce5, (q15_t)0x3583, + (q15_t)0x1cef, (q15_t)0x358a, (q15_t)0x1cfa, (q15_t)0x3591, (q15_t)0x1d04, (q15_t)0x3598, (q15_t)0x1d0f, (q15_t)0x359f, + (q15_t)0x1d19, (q15_t)0x35a5, (q15_t)0x1d24, (q15_t)0x35ac, (q15_t)0x1d2e, (q15_t)0x35b3, (q15_t)0x1d39, (q15_t)0x35ba, + (q15_t)0x1d44, (q15_t)0x35c1, (q15_t)0x1d4e, (q15_t)0x35c8, (q15_t)0x1d59, (q15_t)0x35ce, (q15_t)0x1d63, (q15_t)0x35d5, + (q15_t)0x1d6e, (q15_t)0x35dc, (q15_t)0x1d78, (q15_t)0x35e3, (q15_t)0x1d83, (q15_t)0x35ea, (q15_t)0x1d8e, (q15_t)0x35f0, + (q15_t)0x1d98, (q15_t)0x35f7, (q15_t)0x1da3, (q15_t)0x35fe, (q15_t)0x1dad, (q15_t)0x3605, (q15_t)0x1db8, (q15_t)0x360b, + (q15_t)0x1dc3, (q15_t)0x3612, (q15_t)0x1dcd, (q15_t)0x3619, (q15_t)0x1dd8, (q15_t)0x3620, (q15_t)0x1de2, (q15_t)0x3626, + (q15_t)0x1ded, (q15_t)0x362d, (q15_t)0x1df8, (q15_t)0x3634, (q15_t)0x1e02, (q15_t)0x363a, (q15_t)0x1e0d, (q15_t)0x3641, + (q15_t)0x1e18, (q15_t)0x3648, (q15_t)0x1e22, (q15_t)0x364e, (q15_t)0x1e2d, (q15_t)0x3655, (q15_t)0x1e38, (q15_t)0x365c, + (q15_t)0x1e42, (q15_t)0x3662, (q15_t)0x1e4d, (q15_t)0x3669, (q15_t)0x1e58, (q15_t)0x366f, (q15_t)0x1e62, (q15_t)0x3676, + (q15_t)0x1e6d, (q15_t)0x367d, (q15_t)0x1e78, (q15_t)0x3683, (q15_t)0x1e83, (q15_t)0x368a, (q15_t)0x1e8d, (q15_t)0x3690, + (q15_t)0x1e98, (q15_t)0x3697, (q15_t)0x1ea3, (q15_t)0x369d, (q15_t)0x1ead, (q15_t)0x36a4, (q15_t)0x1eb8, (q15_t)0x36ab, + (q15_t)0x1ec3, (q15_t)0x36b1, (q15_t)0x1ece, (q15_t)0x36b8, (q15_t)0x1ed8, (q15_t)0x36be, (q15_t)0x1ee3, (q15_t)0x36c5, + (q15_t)0x1eee, (q15_t)0x36cb, (q15_t)0x1ef9, (q15_t)0x36d2, (q15_t)0x1f03, (q15_t)0x36d8, (q15_t)0x1f0e, (q15_t)0x36df, + (q15_t)0x1f19, (q15_t)0x36e5, (q15_t)0x1f24, (q15_t)0x36eb, (q15_t)0x1f2f, (q15_t)0x36f2, (q15_t)0x1f39, (q15_t)0x36f8, + (q15_t)0x1f44, (q15_t)0x36ff, (q15_t)0x1f4f, (q15_t)0x3705, (q15_t)0x1f5a, (q15_t)0x370c, (q15_t)0x1f65, (q15_t)0x3712, + (q15_t)0x1f6f, (q15_t)0x3718, (q15_t)0x1f7a, (q15_t)0x371f, (q15_t)0x1f85, (q15_t)0x3725, (q15_t)0x1f90, (q15_t)0x372c, + (q15_t)0x1f9b, (q15_t)0x3732, (q15_t)0x1fa5, (q15_t)0x3738, (q15_t)0x1fb0, (q15_t)0x373f, (q15_t)0x1fbb, (q15_t)0x3745, + (q15_t)0x1fc6, (q15_t)0x374b, (q15_t)0x1fd1, (q15_t)0x3752, (q15_t)0x1fdc, (q15_t)0x3758, (q15_t)0x1fe7, (q15_t)0x375e, + (q15_t)0x1ff1, (q15_t)0x3765, (q15_t)0x1ffc, (q15_t)0x376b, (q15_t)0x2007, (q15_t)0x3771, (q15_t)0x2012, (q15_t)0x3777, + (q15_t)0x201d, (q15_t)0x377e, (q15_t)0x2028, (q15_t)0x3784, (q15_t)0x2033, (q15_t)0x378a, (q15_t)0x203e, (q15_t)0x3790, + (q15_t)0x2049, (q15_t)0x3797, (q15_t)0x2054, (q15_t)0x379d, (q15_t)0x205e, (q15_t)0x37a3, (q15_t)0x2069, (q15_t)0x37a9, + (q15_t)0x2074, (q15_t)0x37b0, (q15_t)0x207f, (q15_t)0x37b6, (q15_t)0x208a, (q15_t)0x37bc, (q15_t)0x2095, (q15_t)0x37c2, + (q15_t)0x20a0, (q15_t)0x37c8, (q15_t)0x20ab, (q15_t)0x37ce, (q15_t)0x20b6, (q15_t)0x37d5, (q15_t)0x20c1, (q15_t)0x37db, + (q15_t)0x20cc, (q15_t)0x37e1, (q15_t)0x20d7, (q15_t)0x37e7, (q15_t)0x20e2, (q15_t)0x37ed, (q15_t)0x20ed, (q15_t)0x37f3, + (q15_t)0x20f8, (q15_t)0x37f9, (q15_t)0x2103, (q15_t)0x37ff, (q15_t)0x210e, (q15_t)0x3805, (q15_t)0x2119, (q15_t)0x380b, + (q15_t)0x2124, (q15_t)0x3812, (q15_t)0x212f, (q15_t)0x3818, (q15_t)0x213a, (q15_t)0x381e, (q15_t)0x2145, (q15_t)0x3824, + (q15_t)0x2150, (q15_t)0x382a, (q15_t)0x215b, (q15_t)0x3830, (q15_t)0x2166, (q15_t)0x3836, (q15_t)0x2171, (q15_t)0x383c, + (q15_t)0x217c, (q15_t)0x3842, (q15_t)0x2187, (q15_t)0x3848, (q15_t)0x2192, (q15_t)0x384e, (q15_t)0x219d, (q15_t)0x3854, + (q15_t)0x21a8, (q15_t)0x385a, (q15_t)0x21b3, (q15_t)0x3860, (q15_t)0x21be, (q15_t)0x3866, (q15_t)0x21ca, (q15_t)0x386b, + (q15_t)0x21d5, (q15_t)0x3871, (q15_t)0x21e0, (q15_t)0x3877, (q15_t)0x21eb, (q15_t)0x387d, (q15_t)0x21f6, (q15_t)0x3883, + (q15_t)0x2201, (q15_t)0x3889, (q15_t)0x220c, (q15_t)0x388f, (q15_t)0x2217, (q15_t)0x3895, (q15_t)0x2222, (q15_t)0x389b, + (q15_t)0x222d, (q15_t)0x38a1, (q15_t)0x2239, (q15_t)0x38a6, (q15_t)0x2244, (q15_t)0x38ac, (q15_t)0x224f, (q15_t)0x38b2, + (q15_t)0x225a, (q15_t)0x38b8, (q15_t)0x2265, (q15_t)0x38be, (q15_t)0x2270, (q15_t)0x38c3, (q15_t)0x227b, (q15_t)0x38c9, + (q15_t)0x2287, (q15_t)0x38cf, (q15_t)0x2292, (q15_t)0x38d5, (q15_t)0x229d, (q15_t)0x38db, (q15_t)0x22a8, (q15_t)0x38e0, + (q15_t)0x22b3, (q15_t)0x38e6, (q15_t)0x22be, (q15_t)0x38ec, (q15_t)0x22ca, (q15_t)0x38f2, (q15_t)0x22d5, (q15_t)0x38f7, + (q15_t)0x22e0, (q15_t)0x38fd, (q15_t)0x22eb, (q15_t)0x3903, (q15_t)0x22f6, (q15_t)0x3909, (q15_t)0x2301, (q15_t)0x390e, + (q15_t)0x230d, (q15_t)0x3914, (q15_t)0x2318, (q15_t)0x391a, (q15_t)0x2323, (q15_t)0x391f, (q15_t)0x232e, (q15_t)0x3925, + (q15_t)0x233a, (q15_t)0x392b, (q15_t)0x2345, (q15_t)0x3930, (q15_t)0x2350, (q15_t)0x3936, (q15_t)0x235b, (q15_t)0x393b, + (q15_t)0x2367, (q15_t)0x3941, (q15_t)0x2372, (q15_t)0x3947, (q15_t)0x237d, (q15_t)0x394c, (q15_t)0x2388, (q15_t)0x3952, + (q15_t)0x2394, (q15_t)0x3958, (q15_t)0x239f, (q15_t)0x395d, (q15_t)0x23aa, (q15_t)0x3963, (q15_t)0x23b5, (q15_t)0x3968, + (q15_t)0x23c1, (q15_t)0x396e, (q15_t)0x23cc, (q15_t)0x3973, (q15_t)0x23d7, (q15_t)0x3979, (q15_t)0x23e2, (q15_t)0x397e, + (q15_t)0x23ee, (q15_t)0x3984, (q15_t)0x23f9, (q15_t)0x3989, (q15_t)0x2404, (q15_t)0x398f, (q15_t)0x2410, (q15_t)0x3994, + (q15_t)0x241b, (q15_t)0x399a, (q15_t)0x2426, (q15_t)0x399f, (q15_t)0x2432, (q15_t)0x39a5, (q15_t)0x243d, (q15_t)0x39aa, + (q15_t)0x2448, (q15_t)0x39b0, (q15_t)0x2454, (q15_t)0x39b5, (q15_t)0x245f, (q15_t)0x39bb, (q15_t)0x246a, (q15_t)0x39c0, + (q15_t)0x2476, (q15_t)0x39c5, (q15_t)0x2481, (q15_t)0x39cb, (q15_t)0x248c, (q15_t)0x39d0, (q15_t)0x2498, (q15_t)0x39d6, + (q15_t)0x24a3, (q15_t)0x39db, (q15_t)0x24ae, (q15_t)0x39e0, (q15_t)0x24ba, (q15_t)0x39e6, (q15_t)0x24c5, (q15_t)0x39eb, + (q15_t)0x24d0, (q15_t)0x39f0, (q15_t)0x24dc, (q15_t)0x39f6, (q15_t)0x24e7, (q15_t)0x39fb, (q15_t)0x24f3, (q15_t)0x3a00, + (q15_t)0x24fe, (q15_t)0x3a06, (q15_t)0x2509, (q15_t)0x3a0b, (q15_t)0x2515, (q15_t)0x3a10, (q15_t)0x2520, (q15_t)0x3a16, + (q15_t)0x252c, (q15_t)0x3a1b, (q15_t)0x2537, (q15_t)0x3a20, (q15_t)0x2542, (q15_t)0x3a25, (q15_t)0x254e, (q15_t)0x3a2b, + (q15_t)0x2559, (q15_t)0x3a30, (q15_t)0x2565, (q15_t)0x3a35, (q15_t)0x2570, (q15_t)0x3a3a, (q15_t)0x257c, (q15_t)0x3a3f, + (q15_t)0x2587, (q15_t)0x3a45, (q15_t)0x2592, (q15_t)0x3a4a, (q15_t)0x259e, (q15_t)0x3a4f, (q15_t)0x25a9, (q15_t)0x3a54, + (q15_t)0x25b5, (q15_t)0x3a59, (q15_t)0x25c0, (q15_t)0x3a5f, (q15_t)0x25cc, (q15_t)0x3a64, (q15_t)0x25d7, (q15_t)0x3a69, + (q15_t)0x25e3, (q15_t)0x3a6e, (q15_t)0x25ee, (q15_t)0x3a73, (q15_t)0x25fa, (q15_t)0x3a78, (q15_t)0x2605, (q15_t)0x3a7d, + (q15_t)0x2611, (q15_t)0x3a82, (q15_t)0x261c, (q15_t)0x3a88, (q15_t)0x2628, (q15_t)0x3a8d, (q15_t)0x2633, (q15_t)0x3a92, + (q15_t)0x263f, (q15_t)0x3a97, (q15_t)0x264a, (q15_t)0x3a9c, (q15_t)0x2656, (q15_t)0x3aa1, (q15_t)0x2661, (q15_t)0x3aa6, + (q15_t)0x266d, (q15_t)0x3aab, (q15_t)0x2678, (q15_t)0x3ab0, (q15_t)0x2684, (q15_t)0x3ab5, (q15_t)0x268f, (q15_t)0x3aba, + (q15_t)0x269b, (q15_t)0x3abf, (q15_t)0x26a6, (q15_t)0x3ac4, (q15_t)0x26b2, (q15_t)0x3ac9, (q15_t)0x26bd, (q15_t)0x3ace, + (q15_t)0x26c9, (q15_t)0x3ad3, (q15_t)0x26d4, (q15_t)0x3ad8, (q15_t)0x26e0, (q15_t)0x3add, (q15_t)0x26ec, (q15_t)0x3ae2, + (q15_t)0x26f7, (q15_t)0x3ae6, (q15_t)0x2703, (q15_t)0x3aeb, (q15_t)0x270e, (q15_t)0x3af0, (q15_t)0x271a, (q15_t)0x3af5, + (q15_t)0x2725, (q15_t)0x3afa, (q15_t)0x2731, (q15_t)0x3aff, (q15_t)0x273d, (q15_t)0x3b04, (q15_t)0x2748, (q15_t)0x3b09, + (q15_t)0x2754, (q15_t)0x3b0e, (q15_t)0x275f, (q15_t)0x3b12, (q15_t)0x276b, (q15_t)0x3b17, (q15_t)0x2777, (q15_t)0x3b1c, + (q15_t)0x2782, (q15_t)0x3b21, (q15_t)0x278e, (q15_t)0x3b26, (q15_t)0x2799, (q15_t)0x3b2a, (q15_t)0x27a5, (q15_t)0x3b2f, + (q15_t)0x27b1, (q15_t)0x3b34, (q15_t)0x27bc, (q15_t)0x3b39, (q15_t)0x27c8, (q15_t)0x3b3e, (q15_t)0x27d3, (q15_t)0x3b42, + (q15_t)0x27df, (q15_t)0x3b47, (q15_t)0x27eb, (q15_t)0x3b4c, (q15_t)0x27f6, (q15_t)0x3b50, (q15_t)0x2802, (q15_t)0x3b55, + (q15_t)0x280e, (q15_t)0x3b5a, (q15_t)0x2819, (q15_t)0x3b5f, (q15_t)0x2825, (q15_t)0x3b63, (q15_t)0x2831, (q15_t)0x3b68, + (q15_t)0x283c, (q15_t)0x3b6d, (q15_t)0x2848, (q15_t)0x3b71, (q15_t)0x2854, (q15_t)0x3b76, (q15_t)0x285f, (q15_t)0x3b7b, + (q15_t)0x286b, (q15_t)0x3b7f, (q15_t)0x2877, (q15_t)0x3b84, (q15_t)0x2882, (q15_t)0x3b88, (q15_t)0x288e, (q15_t)0x3b8d, + (q15_t)0x289a, (q15_t)0x3b92, (q15_t)0x28a5, (q15_t)0x3b96, (q15_t)0x28b1, (q15_t)0x3b9b, (q15_t)0x28bd, (q15_t)0x3b9f, + (q15_t)0x28c9, (q15_t)0x3ba4, (q15_t)0x28d4, (q15_t)0x3ba9, (q15_t)0x28e0, (q15_t)0x3bad, (q15_t)0x28ec, (q15_t)0x3bb2, + (q15_t)0x28f7, (q15_t)0x3bb6, (q15_t)0x2903, (q15_t)0x3bbb, (q15_t)0x290f, (q15_t)0x3bbf, (q15_t)0x291b, (q15_t)0x3bc4, + (q15_t)0x2926, (q15_t)0x3bc8, (q15_t)0x2932, (q15_t)0x3bcd, (q15_t)0x293e, (q15_t)0x3bd1, (q15_t)0x294a, (q15_t)0x3bd6, + (q15_t)0x2955, (q15_t)0x3bda, (q15_t)0x2961, (q15_t)0x3bde, (q15_t)0x296d, (q15_t)0x3be3, (q15_t)0x2979, (q15_t)0x3be7, + (q15_t)0x2984, (q15_t)0x3bec, (q15_t)0x2990, (q15_t)0x3bf0, (q15_t)0x299c, (q15_t)0x3bf5, (q15_t)0x29a8, (q15_t)0x3bf9, + (q15_t)0x29b4, (q15_t)0x3bfd, (q15_t)0x29bf, (q15_t)0x3c02, (q15_t)0x29cb, (q15_t)0x3c06, (q15_t)0x29d7, (q15_t)0x3c0a, + (q15_t)0x29e3, (q15_t)0x3c0f, (q15_t)0x29ee, (q15_t)0x3c13, (q15_t)0x29fa, (q15_t)0x3c17, (q15_t)0x2a06, (q15_t)0x3c1c, + (q15_t)0x2a12, (q15_t)0x3c20, (q15_t)0x2a1e, (q15_t)0x3c24, (q15_t)0x2a29, (q15_t)0x3c29, (q15_t)0x2a35, (q15_t)0x3c2d, + (q15_t)0x2a41, (q15_t)0x3c31, (q15_t)0x2a4d, (q15_t)0x3c36, (q15_t)0x2a59, (q15_t)0x3c3a, (q15_t)0x2a65, (q15_t)0x3c3e, + (q15_t)0x2a70, (q15_t)0x3c42, (q15_t)0x2a7c, (q15_t)0x3c46, (q15_t)0x2a88, (q15_t)0x3c4b, (q15_t)0x2a94, (q15_t)0x3c4f, + (q15_t)0x2aa0, (q15_t)0x3c53, (q15_t)0x2aac, (q15_t)0x3c57, (q15_t)0x2ab7, (q15_t)0x3c5b, (q15_t)0x2ac3, (q15_t)0x3c60, + (q15_t)0x2acf, (q15_t)0x3c64, (q15_t)0x2adb, (q15_t)0x3c68, (q15_t)0x2ae7, (q15_t)0x3c6c, (q15_t)0x2af3, (q15_t)0x3c70, + (q15_t)0x2aff, (q15_t)0x3c74, (q15_t)0x2b0a, (q15_t)0x3c79, (q15_t)0x2b16, (q15_t)0x3c7d, (q15_t)0x2b22, (q15_t)0x3c81, + (q15_t)0x2b2e, (q15_t)0x3c85, (q15_t)0x2b3a, (q15_t)0x3c89, (q15_t)0x2b46, (q15_t)0x3c8d, (q15_t)0x2b52, (q15_t)0x3c91, + (q15_t)0x2b5e, (q15_t)0x3c95, (q15_t)0x2b6a, (q15_t)0x3c99, (q15_t)0x2b75, (q15_t)0x3c9d, (q15_t)0x2b81, (q15_t)0x3ca1, + (q15_t)0x2b8d, (q15_t)0x3ca5, (q15_t)0x2b99, (q15_t)0x3ca9, (q15_t)0x2ba5, (q15_t)0x3cad, (q15_t)0x2bb1, (q15_t)0x3cb1, + (q15_t)0x2bbd, (q15_t)0x3cb5, (q15_t)0x2bc9, (q15_t)0x3cb9, (q15_t)0x2bd5, (q15_t)0x3cbd, (q15_t)0x2be1, (q15_t)0x3cc1, + (q15_t)0x2bed, (q15_t)0x3cc5, (q15_t)0x2bf9, (q15_t)0x3cc9, (q15_t)0x2c05, (q15_t)0x3ccd, (q15_t)0x2c10, (q15_t)0x3cd1, + (q15_t)0x2c1c, (q15_t)0x3cd5, (q15_t)0x2c28, (q15_t)0x3cd9, (q15_t)0x2c34, (q15_t)0x3cdd, (q15_t)0x2c40, (q15_t)0x3ce0, + (q15_t)0x2c4c, (q15_t)0x3ce4, (q15_t)0x2c58, (q15_t)0x3ce8, (q15_t)0x2c64, (q15_t)0x3cec, (q15_t)0x2c70, (q15_t)0x3cf0, + (q15_t)0x2c7c, (q15_t)0x3cf4, (q15_t)0x2c88, (q15_t)0x3cf8, (q15_t)0x2c94, (q15_t)0x3cfb, (q15_t)0x2ca0, (q15_t)0x3cff, + (q15_t)0x2cac, (q15_t)0x3d03, (q15_t)0x2cb8, (q15_t)0x3d07, (q15_t)0x2cc4, (q15_t)0x3d0b, (q15_t)0x2cd0, (q15_t)0x3d0e, + (q15_t)0x2cdc, (q15_t)0x3d12, (q15_t)0x2ce8, (q15_t)0x3d16, (q15_t)0x2cf4, (q15_t)0x3d1a, (q15_t)0x2d00, (q15_t)0x3d1d, + (q15_t)0x2d0c, (q15_t)0x3d21, (q15_t)0x2d18, (q15_t)0x3d25, (q15_t)0x2d24, (q15_t)0x3d28, (q15_t)0x2d30, (q15_t)0x3d2c, + (q15_t)0x2d3c, (q15_t)0x3d30, (q15_t)0x2d48, (q15_t)0x3d34, (q15_t)0x2d54, (q15_t)0x3d37, (q15_t)0x2d60, (q15_t)0x3d3b, + (q15_t)0x2d6c, (q15_t)0x3d3f, (q15_t)0x2d78, (q15_t)0x3d42, (q15_t)0x2d84, (q15_t)0x3d46, (q15_t)0x2d90, (q15_t)0x3d49, + (q15_t)0x2d9c, (q15_t)0x3d4d, (q15_t)0x2da8, (q15_t)0x3d51, (q15_t)0x2db4, (q15_t)0x3d54, (q15_t)0x2dc0, (q15_t)0x3d58, + (q15_t)0x2dcc, (q15_t)0x3d5b, (q15_t)0x2dd8, (q15_t)0x3d5f, (q15_t)0x2de4, (q15_t)0x3d63, (q15_t)0x2df0, (q15_t)0x3d66, + (q15_t)0x2dfc, (q15_t)0x3d6a, (q15_t)0x2e09, (q15_t)0x3d6d, (q15_t)0x2e15, (q15_t)0x3d71, (q15_t)0x2e21, (q15_t)0x3d74, + (q15_t)0x2e2d, (q15_t)0x3d78, (q15_t)0x2e39, (q15_t)0x3d7b, (q15_t)0x2e45, (q15_t)0x3d7f, (q15_t)0x2e51, (q15_t)0x3d82, + (q15_t)0x2e5d, (q15_t)0x3d86, (q15_t)0x2e69, (q15_t)0x3d89, (q15_t)0x2e75, (q15_t)0x3d8d, (q15_t)0x2e81, (q15_t)0x3d90, + (q15_t)0x2e8d, (q15_t)0x3d93, (q15_t)0x2e99, (q15_t)0x3d97, (q15_t)0x2ea6, (q15_t)0x3d9a, (q15_t)0x2eb2, (q15_t)0x3d9e, + (q15_t)0x2ebe, (q15_t)0x3da1, (q15_t)0x2eca, (q15_t)0x3da4, (q15_t)0x2ed6, (q15_t)0x3da8, (q15_t)0x2ee2, (q15_t)0x3dab, + (q15_t)0x2eee, (q15_t)0x3daf, (q15_t)0x2efa, (q15_t)0x3db2, (q15_t)0x2f06, (q15_t)0x3db5, (q15_t)0x2f13, (q15_t)0x3db9, + (q15_t)0x2f1f, (q15_t)0x3dbc, (q15_t)0x2f2b, (q15_t)0x3dbf, (q15_t)0x2f37, (q15_t)0x3dc2, (q15_t)0x2f43, (q15_t)0x3dc6, + (q15_t)0x2f4f, (q15_t)0x3dc9, (q15_t)0x2f5b, (q15_t)0x3dcc, (q15_t)0x2f67, (q15_t)0x3dd0, (q15_t)0x2f74, (q15_t)0x3dd3, + (q15_t)0x2f80, (q15_t)0x3dd6, (q15_t)0x2f8c, (q15_t)0x3dd9, (q15_t)0x2f98, (q15_t)0x3ddd, (q15_t)0x2fa4, (q15_t)0x3de0, + (q15_t)0x2fb0, (q15_t)0x3de3, (q15_t)0x2fbc, (q15_t)0x3de6, (q15_t)0x2fc9, (q15_t)0x3de9, (q15_t)0x2fd5, (q15_t)0x3ded, + (q15_t)0x2fe1, (q15_t)0x3df0, (q15_t)0x2fed, (q15_t)0x3df3, (q15_t)0x2ff9, (q15_t)0x3df6, (q15_t)0x3005, (q15_t)0x3df9, + (q15_t)0x3012, (q15_t)0x3dfc, (q15_t)0x301e, (q15_t)0x3dff, (q15_t)0x302a, (q15_t)0x3e03, (q15_t)0x3036, (q15_t)0x3e06, + (q15_t)0x3042, (q15_t)0x3e09, (q15_t)0x304e, (q15_t)0x3e0c, (q15_t)0x305b, (q15_t)0x3e0f, (q15_t)0x3067, (q15_t)0x3e12, + (q15_t)0x3073, (q15_t)0x3e15, (q15_t)0x307f, (q15_t)0x3e18, (q15_t)0x308b, (q15_t)0x3e1b, (q15_t)0x3098, (q15_t)0x3e1e, + (q15_t)0x30a4, (q15_t)0x3e21, (q15_t)0x30b0, (q15_t)0x3e24, (q15_t)0x30bc, (q15_t)0x3e27, (q15_t)0x30c8, (q15_t)0x3e2a, + (q15_t)0x30d5, (q15_t)0x3e2d, (q15_t)0x30e1, (q15_t)0x3e30, (q15_t)0x30ed, (q15_t)0x3e33, (q15_t)0x30f9, (q15_t)0x3e36, + (q15_t)0x3105, (q15_t)0x3e39, (q15_t)0x3112, (q15_t)0x3e3c, (q15_t)0x311e, (q15_t)0x3e3f, (q15_t)0x312a, (q15_t)0x3e42, + (q15_t)0x3136, (q15_t)0x3e45, (q15_t)0x3143, (q15_t)0x3e48, (q15_t)0x314f, (q15_t)0x3e4a, (q15_t)0x315b, (q15_t)0x3e4d, + (q15_t)0x3167, (q15_t)0x3e50, (q15_t)0x3174, (q15_t)0x3e53, (q15_t)0x3180, (q15_t)0x3e56, (q15_t)0x318c, (q15_t)0x3e59, + (q15_t)0x3198, (q15_t)0x3e5c, (q15_t)0x31a4, (q15_t)0x3e5e, (q15_t)0x31b1, (q15_t)0x3e61, (q15_t)0x31bd, (q15_t)0x3e64, + (q15_t)0x31c9, (q15_t)0x3e67, (q15_t)0x31d5, (q15_t)0x3e6a, (q15_t)0x31e2, (q15_t)0x3e6c, (q15_t)0x31ee, (q15_t)0x3e6f, + (q15_t)0x31fa, (q15_t)0x3e72, (q15_t)0x3207, (q15_t)0x3e75, (q15_t)0x3213, (q15_t)0x3e77, (q15_t)0x321f, (q15_t)0x3e7a, + (q15_t)0x322b, (q15_t)0x3e7d, (q15_t)0x3238, (q15_t)0x3e80, (q15_t)0x3244, (q15_t)0x3e82, (q15_t)0x3250, (q15_t)0x3e85, + (q15_t)0x325c, (q15_t)0x3e88, (q15_t)0x3269, (q15_t)0x3e8a, (q15_t)0x3275, (q15_t)0x3e8d, (q15_t)0x3281, (q15_t)0x3e90, + (q15_t)0x328e, (q15_t)0x3e92, (q15_t)0x329a, (q15_t)0x3e95, (q15_t)0x32a6, (q15_t)0x3e98, (q15_t)0x32b2, (q15_t)0x3e9a, + (q15_t)0x32bf, (q15_t)0x3e9d, (q15_t)0x32cb, (q15_t)0x3e9f, (q15_t)0x32d7, (q15_t)0x3ea2, (q15_t)0x32e4, (q15_t)0x3ea5, + (q15_t)0x32f0, (q15_t)0x3ea7, (q15_t)0x32fc, (q15_t)0x3eaa, (q15_t)0x3308, (q15_t)0x3eac, (q15_t)0x3315, (q15_t)0x3eaf, + (q15_t)0x3321, (q15_t)0x3eb1, (q15_t)0x332d, (q15_t)0x3eb4, (q15_t)0x333a, (q15_t)0x3eb6, (q15_t)0x3346, (q15_t)0x3eb9, + (q15_t)0x3352, (q15_t)0x3ebb, (q15_t)0x335f, (q15_t)0x3ebe, (q15_t)0x336b, (q15_t)0x3ec0, (q15_t)0x3377, (q15_t)0x3ec3, + (q15_t)0x3384, (q15_t)0x3ec5, (q15_t)0x3390, (q15_t)0x3ec8, (q15_t)0x339c, (q15_t)0x3eca, (q15_t)0x33a9, (q15_t)0x3ecc, + (q15_t)0x33b5, (q15_t)0x3ecf, (q15_t)0x33c1, (q15_t)0x3ed1, (q15_t)0x33ce, (q15_t)0x3ed4, (q15_t)0x33da, (q15_t)0x3ed6, + (q15_t)0x33e6, (q15_t)0x3ed8, (q15_t)0x33f3, (q15_t)0x3edb, (q15_t)0x33ff, (q15_t)0x3edd, (q15_t)0x340b, (q15_t)0x3ee0, + (q15_t)0x3418, (q15_t)0x3ee2, (q15_t)0x3424, (q15_t)0x3ee4, (q15_t)0x3430, (q15_t)0x3ee7, (q15_t)0x343d, (q15_t)0x3ee9, + (q15_t)0x3449, (q15_t)0x3eeb, (q15_t)0x3455, (q15_t)0x3eed, (q15_t)0x3462, (q15_t)0x3ef0, (q15_t)0x346e, (q15_t)0x3ef2, + (q15_t)0x347b, (q15_t)0x3ef4, (q15_t)0x3487, (q15_t)0x3ef7, (q15_t)0x3493, (q15_t)0x3ef9, (q15_t)0x34a0, (q15_t)0x3efb, + (q15_t)0x34ac, (q15_t)0x3efd, (q15_t)0x34b8, (q15_t)0x3f00, (q15_t)0x34c5, (q15_t)0x3f02, (q15_t)0x34d1, (q15_t)0x3f04, + (q15_t)0x34dd, (q15_t)0x3f06, (q15_t)0x34ea, (q15_t)0x3f08, (q15_t)0x34f6, (q15_t)0x3f0a, (q15_t)0x3503, (q15_t)0x3f0d, + (q15_t)0x350f, (q15_t)0x3f0f, (q15_t)0x351b, (q15_t)0x3f11, (q15_t)0x3528, (q15_t)0x3f13, (q15_t)0x3534, (q15_t)0x3f15, + (q15_t)0x3540, (q15_t)0x3f17, (q15_t)0x354d, (q15_t)0x3f19, (q15_t)0x3559, (q15_t)0x3f1c, (q15_t)0x3566, (q15_t)0x3f1e, + (q15_t)0x3572, (q15_t)0x3f20, (q15_t)0x357e, (q15_t)0x3f22, (q15_t)0x358b, (q15_t)0x3f24, (q15_t)0x3597, (q15_t)0x3f26, + (q15_t)0x35a4, (q15_t)0x3f28, (q15_t)0x35b0, (q15_t)0x3f2a, (q15_t)0x35bc, (q15_t)0x3f2c, (q15_t)0x35c9, (q15_t)0x3f2e, + (q15_t)0x35d5, (q15_t)0x3f30, (q15_t)0x35e2, (q15_t)0x3f32, (q15_t)0x35ee, (q15_t)0x3f34, (q15_t)0x35fa, (q15_t)0x3f36, + (q15_t)0x3607, (q15_t)0x3f38, (q15_t)0x3613, (q15_t)0x3f3a, (q15_t)0x3620, (q15_t)0x3f3c, (q15_t)0x362c, (q15_t)0x3f3e, + (q15_t)0x3639, (q15_t)0x3f40, (q15_t)0x3645, (q15_t)0x3f42, (q15_t)0x3651, (q15_t)0x3f43, (q15_t)0x365e, (q15_t)0x3f45, + (q15_t)0x366a, (q15_t)0x3f47, (q15_t)0x3677, (q15_t)0x3f49, (q15_t)0x3683, (q15_t)0x3f4b, (q15_t)0x3690, (q15_t)0x3f4d, + (q15_t)0x369c, (q15_t)0x3f4f, (q15_t)0x36a8, (q15_t)0x3f51, (q15_t)0x36b5, (q15_t)0x3f52, (q15_t)0x36c1, (q15_t)0x3f54, + (q15_t)0x36ce, (q15_t)0x3f56, (q15_t)0x36da, (q15_t)0x3f58, (q15_t)0x36e7, (q15_t)0x3f5a, (q15_t)0x36f3, (q15_t)0x3f5b, + (q15_t)0x36ff, (q15_t)0x3f5d, (q15_t)0x370c, (q15_t)0x3f5f, (q15_t)0x3718, (q15_t)0x3f61, (q15_t)0x3725, (q15_t)0x3f62, + (q15_t)0x3731, (q15_t)0x3f64, (q15_t)0x373e, (q15_t)0x3f66, (q15_t)0x374a, (q15_t)0x3f68, (q15_t)0x3757, (q15_t)0x3f69, + (q15_t)0x3763, (q15_t)0x3f6b, (q15_t)0x376f, (q15_t)0x3f6d, (q15_t)0x377c, (q15_t)0x3f6e, (q15_t)0x3788, (q15_t)0x3f70, + (q15_t)0x3795, (q15_t)0x3f72, (q15_t)0x37a1, (q15_t)0x3f73, (q15_t)0x37ae, (q15_t)0x3f75, (q15_t)0x37ba, (q15_t)0x3f77, + (q15_t)0x37c7, (q15_t)0x3f78, (q15_t)0x37d3, (q15_t)0x3f7a, (q15_t)0x37e0, (q15_t)0x3f7b, (q15_t)0x37ec, (q15_t)0x3f7d, + (q15_t)0x37f9, (q15_t)0x3f7f, (q15_t)0x3805, (q15_t)0x3f80, (q15_t)0x3811, (q15_t)0x3f82, (q15_t)0x381e, (q15_t)0x3f83, + (q15_t)0x382a, (q15_t)0x3f85, (q15_t)0x3837, (q15_t)0x3f86, (q15_t)0x3843, (q15_t)0x3f88, (q15_t)0x3850, (q15_t)0x3f89, + (q15_t)0x385c, (q15_t)0x3f8b, (q15_t)0x3869, (q15_t)0x3f8c, (q15_t)0x3875, (q15_t)0x3f8e, (q15_t)0x3882, (q15_t)0x3f8f, + (q15_t)0x388e, (q15_t)0x3f91, (q15_t)0x389b, (q15_t)0x3f92, (q15_t)0x38a7, (q15_t)0x3f94, (q15_t)0x38b4, (q15_t)0x3f95, + (q15_t)0x38c0, (q15_t)0x3f97, (q15_t)0x38cd, (q15_t)0x3f98, (q15_t)0x38d9, (q15_t)0x3f99, (q15_t)0x38e6, (q15_t)0x3f9b, + (q15_t)0x38f2, (q15_t)0x3f9c, (q15_t)0x38ff, (q15_t)0x3f9e, (q15_t)0x390b, (q15_t)0x3f9f, (q15_t)0x3918, (q15_t)0x3fa0, + (q15_t)0x3924, (q15_t)0x3fa2, (q15_t)0x3931, (q15_t)0x3fa3, (q15_t)0x393d, (q15_t)0x3fa4, (q15_t)0x394a, (q15_t)0x3fa6, + (q15_t)0x3956, (q15_t)0x3fa7, (q15_t)0x3963, (q15_t)0x3fa8, (q15_t)0x396f, (q15_t)0x3faa, (q15_t)0x397c, (q15_t)0x3fab, + (q15_t)0x3988, (q15_t)0x3fac, (q15_t)0x3995, (q15_t)0x3fad, (q15_t)0x39a1, (q15_t)0x3faf, (q15_t)0x39ae, (q15_t)0x3fb0, + (q15_t)0x39ba, (q15_t)0x3fb1, (q15_t)0x39c7, (q15_t)0x3fb2, (q15_t)0x39d3, (q15_t)0x3fb4, (q15_t)0x39e0, (q15_t)0x3fb5, + (q15_t)0x39ec, (q15_t)0x3fb6, (q15_t)0x39f9, (q15_t)0x3fb7, (q15_t)0x3a05, (q15_t)0x3fb8, (q15_t)0x3a12, (q15_t)0x3fb9, + (q15_t)0x3a1e, (q15_t)0x3fbb, (q15_t)0x3a2b, (q15_t)0x3fbc, (q15_t)0x3a37, (q15_t)0x3fbd, (q15_t)0x3a44, (q15_t)0x3fbe, + (q15_t)0x3a50, (q15_t)0x3fbf, (q15_t)0x3a5d, (q15_t)0x3fc0, (q15_t)0x3a69, (q15_t)0x3fc1, (q15_t)0x3a76, (q15_t)0x3fc3, + (q15_t)0x3a82, (q15_t)0x3fc4, (q15_t)0x3a8f, (q15_t)0x3fc5, (q15_t)0x3a9b, (q15_t)0x3fc6, (q15_t)0x3aa8, (q15_t)0x3fc7, + (q15_t)0x3ab4, (q15_t)0x3fc8, (q15_t)0x3ac1, (q15_t)0x3fc9, (q15_t)0x3acd, (q15_t)0x3fca, (q15_t)0x3ada, (q15_t)0x3fcb, + (q15_t)0x3ae6, (q15_t)0x3fcc, (q15_t)0x3af3, (q15_t)0x3fcd, (q15_t)0x3b00, (q15_t)0x3fce, (q15_t)0x3b0c, (q15_t)0x3fcf, + (q15_t)0x3b19, (q15_t)0x3fd0, (q15_t)0x3b25, (q15_t)0x3fd1, (q15_t)0x3b32, (q15_t)0x3fd2, (q15_t)0x3b3e, (q15_t)0x3fd3, + (q15_t)0x3b4b, (q15_t)0x3fd4, (q15_t)0x3b57, (q15_t)0x3fd5, (q15_t)0x3b64, (q15_t)0x3fd5, (q15_t)0x3b70, (q15_t)0x3fd6, + (q15_t)0x3b7d, (q15_t)0x3fd7, (q15_t)0x3b89, (q15_t)0x3fd8, (q15_t)0x3b96, (q15_t)0x3fd9, (q15_t)0x3ba2, (q15_t)0x3fda, + (q15_t)0x3baf, (q15_t)0x3fdb, (q15_t)0x3bbc, (q15_t)0x3fdc, (q15_t)0x3bc8, (q15_t)0x3fdc, (q15_t)0x3bd5, (q15_t)0x3fdd, + (q15_t)0x3be1, (q15_t)0x3fde, (q15_t)0x3bee, (q15_t)0x3fdf, (q15_t)0x3bfa, (q15_t)0x3fe0, (q15_t)0x3c07, (q15_t)0x3fe0, + (q15_t)0x3c13, (q15_t)0x3fe1, (q15_t)0x3c20, (q15_t)0x3fe2, (q15_t)0x3c2c, (q15_t)0x3fe3, (q15_t)0x3c39, (q15_t)0x3fe3, + (q15_t)0x3c45, (q15_t)0x3fe4, (q15_t)0x3c52, (q15_t)0x3fe5, (q15_t)0x3c5f, (q15_t)0x3fe6, (q15_t)0x3c6b, (q15_t)0x3fe6, + (q15_t)0x3c78, (q15_t)0x3fe7, (q15_t)0x3c84, (q15_t)0x3fe8, (q15_t)0x3c91, (q15_t)0x3fe8, (q15_t)0x3c9d, (q15_t)0x3fe9, + (q15_t)0x3caa, (q15_t)0x3fea, (q15_t)0x3cb6, (q15_t)0x3fea, (q15_t)0x3cc3, (q15_t)0x3feb, (q15_t)0x3cd0, (q15_t)0x3fec, + (q15_t)0x3cdc, (q15_t)0x3fec, (q15_t)0x3ce9, (q15_t)0x3fed, (q15_t)0x3cf5, (q15_t)0x3fed, (q15_t)0x3d02, (q15_t)0x3fee, + (q15_t)0x3d0e, (q15_t)0x3fef, (q15_t)0x3d1b, (q15_t)0x3fef, (q15_t)0x3d27, (q15_t)0x3ff0, (q15_t)0x3d34, (q15_t)0x3ff0, + (q15_t)0x3d40, (q15_t)0x3ff1, (q15_t)0x3d4d, (q15_t)0x3ff1, (q15_t)0x3d5a, (q15_t)0x3ff2, (q15_t)0x3d66, (q15_t)0x3ff2, + (q15_t)0x3d73, (q15_t)0x3ff3, (q15_t)0x3d7f, (q15_t)0x3ff3, (q15_t)0x3d8c, (q15_t)0x3ff4, (q15_t)0x3d98, (q15_t)0x3ff4, + (q15_t)0x3da5, (q15_t)0x3ff5, (q15_t)0x3db2, (q15_t)0x3ff5, (q15_t)0x3dbe, (q15_t)0x3ff6, (q15_t)0x3dcb, (q15_t)0x3ff6, + (q15_t)0x3dd7, (q15_t)0x3ff7, (q15_t)0x3de4, (q15_t)0x3ff7, (q15_t)0x3df0, (q15_t)0x3ff7, (q15_t)0x3dfd, (q15_t)0x3ff8, + (q15_t)0x3e09, (q15_t)0x3ff8, (q15_t)0x3e16, (q15_t)0x3ff9, (q15_t)0x3e23, (q15_t)0x3ff9, (q15_t)0x3e2f, (q15_t)0x3ff9, + (q15_t)0x3e3c, (q15_t)0x3ffa, (q15_t)0x3e48, (q15_t)0x3ffa, (q15_t)0x3e55, (q15_t)0x3ffa, (q15_t)0x3e61, (q15_t)0x3ffb, + (q15_t)0x3e6e, (q15_t)0x3ffb, (q15_t)0x3e7a, (q15_t)0x3ffb, (q15_t)0x3e87, (q15_t)0x3ffc, (q15_t)0x3e94, (q15_t)0x3ffc, + (q15_t)0x3ea0, (q15_t)0x3ffc, (q15_t)0x3ead, (q15_t)0x3ffc, (q15_t)0x3eb9, (q15_t)0x3ffd, (q15_t)0x3ec6, (q15_t)0x3ffd, + (q15_t)0x3ed2, (q15_t)0x3ffd, (q15_t)0x3edf, (q15_t)0x3ffd, (q15_t)0x3eec, (q15_t)0x3ffe, (q15_t)0x3ef8, (q15_t)0x3ffe, + (q15_t)0x3f05, (q15_t)0x3ffe, (q15_t)0x3f11, (q15_t)0x3ffe, (q15_t)0x3f1e, (q15_t)0x3ffe, (q15_t)0x3f2a, (q15_t)0x3fff, + (q15_t)0x3f37, (q15_t)0x3fff, (q15_t)0x3f44, (q15_t)0x3fff, (q15_t)0x3f50, (q15_t)0x3fff, (q15_t)0x3f5d, (q15_t)0x3fff, + (q15_t)0x3f69, (q15_t)0x3fff, (q15_t)0x3f76, (q15_t)0x3fff, (q15_t)0x3f82, (q15_t)0x4000, (q15_t)0x3f8f, (q15_t)0x4000, + (q15_t)0x3f9b, (q15_t)0x4000, (q15_t)0x3fa8, (q15_t)0x4000, (q15_t)0x3fb5, (q15_t)0x4000, (q15_t)0x3fc1, (q15_t)0x4000, + (q15_t)0x3fce, (q15_t)0x4000, (q15_t)0x3fda, (q15_t)0x4000, (q15_t)0x3fe7, (q15_t)0x4000, (q15_t)0x3ff3, (q15_t)0x4000, +}; + +/** + @par + Generation of real_CoefB array: + @par + n = 4096 + 
for (i = 0; i < n; i++)
+  {
+     pBTable[2 * i]     = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+     pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+  }
+ @par + Convert to fixed point Q15 format + round(pBTable[i] * pow(2, 15)) +*/ +const q15_t __ALIGNED(4) realCoefBQ15[8192] = { + (q15_t)0x4000, (q15_t)0x4000, (q15_t)0x400d, (q15_t)0x4000, (q15_t)0x4019, (q15_t)0x4000, (q15_t)0x4026, (q15_t)0x4000, + (q15_t)0x4032, (q15_t)0x4000, (q15_t)0x403f, (q15_t)0x4000, (q15_t)0x404b, (q15_t)0x4000, (q15_t)0x4058, (q15_t)0x4000, + (q15_t)0x4065, (q15_t)0x4000, (q15_t)0x4071, (q15_t)0x4000, (q15_t)0x407e, (q15_t)0x4000, (q15_t)0x408a, (q15_t)0x3fff, + (q15_t)0x4097, (q15_t)0x3fff, (q15_t)0x40a3, (q15_t)0x3fff, (q15_t)0x40b0, (q15_t)0x3fff, (q15_t)0x40bc, (q15_t)0x3fff, + (q15_t)0x40c9, (q15_t)0x3fff, (q15_t)0x40d6, (q15_t)0x3fff, (q15_t)0x40e2, (q15_t)0x3ffe, (q15_t)0x40ef, (q15_t)0x3ffe, + (q15_t)0x40fb, (q15_t)0x3ffe, (q15_t)0x4108, (q15_t)0x3ffe, (q15_t)0x4114, (q15_t)0x3ffe, (q15_t)0x4121, (q15_t)0x3ffd, + (q15_t)0x412e, (q15_t)0x3ffd, (q15_t)0x413a, (q15_t)0x3ffd, (q15_t)0x4147, (q15_t)0x3ffd, (q15_t)0x4153, (q15_t)0x3ffc, + (q15_t)0x4160, (q15_t)0x3ffc, (q15_t)0x416c, (q15_t)0x3ffc, (q15_t)0x4179, (q15_t)0x3ffc, (q15_t)0x4186, (q15_t)0x3ffb, + (q15_t)0x4192, (q15_t)0x3ffb, (q15_t)0x419f, (q15_t)0x3ffb, (q15_t)0x41ab, (q15_t)0x3ffa, (q15_t)0x41b8, (q15_t)0x3ffa, + (q15_t)0x41c4, (q15_t)0x3ffa, (q15_t)0x41d1, (q15_t)0x3ff9, (q15_t)0x41dd, (q15_t)0x3ff9, (q15_t)0x41ea, (q15_t)0x3ff9, + (q15_t)0x41f7, (q15_t)0x3ff8, (q15_t)0x4203, (q15_t)0x3ff8, (q15_t)0x4210, (q15_t)0x3ff7, (q15_t)0x421c, (q15_t)0x3ff7, + (q15_t)0x4229, (q15_t)0x3ff7, (q15_t)0x4235, (q15_t)0x3ff6, (q15_t)0x4242, (q15_t)0x3ff6, (q15_t)0x424e, (q15_t)0x3ff5, + (q15_t)0x425b, (q15_t)0x3ff5, (q15_t)0x4268, (q15_t)0x3ff4, (q15_t)0x4274, (q15_t)0x3ff4, (q15_t)0x4281, (q15_t)0x3ff3, + (q15_t)0x428d, (q15_t)0x3ff3, (q15_t)0x429a, (q15_t)0x3ff2, (q15_t)0x42a6, (q15_t)0x3ff2, (q15_t)0x42b3, (q15_t)0x3ff1, + (q15_t)0x42c0, (q15_t)0x3ff1, (q15_t)0x42cc, (q15_t)0x3ff0, (q15_t)0x42d9, (q15_t)0x3ff0, (q15_t)0x42e5, (q15_t)0x3fef, + (q15_t)0x42f2, (q15_t)0x3fef, (q15_t)0x42fe, (q15_t)0x3fee, (q15_t)0x430b, (q15_t)0x3fed, (q15_t)0x4317, (q15_t)0x3fed, + (q15_t)0x4324, (q15_t)0x3fec, (q15_t)0x4330, (q15_t)0x3fec, (q15_t)0x433d, (q15_t)0x3feb, (q15_t)0x434a, (q15_t)0x3fea, + (q15_t)0x4356, (q15_t)0x3fea, (q15_t)0x4363, (q15_t)0x3fe9, (q15_t)0x436f, (q15_t)0x3fe8, (q15_t)0x437c, (q15_t)0x3fe8, + (q15_t)0x4388, (q15_t)0x3fe7, (q15_t)0x4395, (q15_t)0x3fe6, (q15_t)0x43a1, (q15_t)0x3fe6, (q15_t)0x43ae, (q15_t)0x3fe5, + (q15_t)0x43bb, (q15_t)0x3fe4, (q15_t)0x43c7, (q15_t)0x3fe3, (q15_t)0x43d4, (q15_t)0x3fe3, (q15_t)0x43e0, (q15_t)0x3fe2, + (q15_t)0x43ed, (q15_t)0x3fe1, (q15_t)0x43f9, (q15_t)0x3fe0, (q15_t)0x4406, (q15_t)0x3fe0, (q15_t)0x4412, (q15_t)0x3fdf, + (q15_t)0x441f, (q15_t)0x3fde, (q15_t)0x442b, (q15_t)0x3fdd, (q15_t)0x4438, (q15_t)0x3fdc, (q15_t)0x4444, (q15_t)0x3fdc, + (q15_t)0x4451, (q15_t)0x3fdb, (q15_t)0x445e, (q15_t)0x3fda, (q15_t)0x446a, (q15_t)0x3fd9, (q15_t)0x4477, (q15_t)0x3fd8, + (q15_t)0x4483, (q15_t)0x3fd7, (q15_t)0x4490, (q15_t)0x3fd6, (q15_t)0x449c, (q15_t)0x3fd5, (q15_t)0x44a9, (q15_t)0x3fd5, + (q15_t)0x44b5, (q15_t)0x3fd4, (q15_t)0x44c2, (q15_t)0x3fd3, (q15_t)0x44ce, (q15_t)0x3fd2, (q15_t)0x44db, (q15_t)0x3fd1, + (q15_t)0x44e7, (q15_t)0x3fd0, (q15_t)0x44f4, (q15_t)0x3fcf, (q15_t)0x4500, (q15_t)0x3fce, (q15_t)0x450d, (q15_t)0x3fcd, + (q15_t)0x451a, (q15_t)0x3fcc, (q15_t)0x4526, (q15_t)0x3fcb, (q15_t)0x4533, (q15_t)0x3fca, (q15_t)0x453f, (q15_t)0x3fc9, + (q15_t)0x454c, (q15_t)0x3fc8, (q15_t)0x4558, (q15_t)0x3fc7, (q15_t)0x4565, (q15_t)0x3fc6, (q15_t)0x4571, (q15_t)0x3fc5, + (q15_t)0x457e, (q15_t)0x3fc4, (q15_t)0x458a, (q15_t)0x3fc3, (q15_t)0x4597, (q15_t)0x3fc1, (q15_t)0x45a3, (q15_t)0x3fc0, + (q15_t)0x45b0, (q15_t)0x3fbf, (q15_t)0x45bc, (q15_t)0x3fbe, (q15_t)0x45c9, (q15_t)0x3fbd, (q15_t)0x45d5, (q15_t)0x3fbc, + (q15_t)0x45e2, (q15_t)0x3fbb, (q15_t)0x45ee, (q15_t)0x3fb9, (q15_t)0x45fb, (q15_t)0x3fb8, (q15_t)0x4607, (q15_t)0x3fb7, + (q15_t)0x4614, (q15_t)0x3fb6, (q15_t)0x4620, (q15_t)0x3fb5, (q15_t)0x462d, (q15_t)0x3fb4, (q15_t)0x4639, (q15_t)0x3fb2, + (q15_t)0x4646, (q15_t)0x3fb1, (q15_t)0x4652, (q15_t)0x3fb0, (q15_t)0x465f, (q15_t)0x3faf, (q15_t)0x466b, (q15_t)0x3fad, + (q15_t)0x4678, (q15_t)0x3fac, (q15_t)0x4684, (q15_t)0x3fab, (q15_t)0x4691, (q15_t)0x3faa, (q15_t)0x469d, (q15_t)0x3fa8, + (q15_t)0x46aa, (q15_t)0x3fa7, (q15_t)0x46b6, (q15_t)0x3fa6, (q15_t)0x46c3, (q15_t)0x3fa4, (q15_t)0x46cf, (q15_t)0x3fa3, + (q15_t)0x46dc, (q15_t)0x3fa2, (q15_t)0x46e8, (q15_t)0x3fa0, (q15_t)0x46f5, (q15_t)0x3f9f, (q15_t)0x4701, (q15_t)0x3f9e, + (q15_t)0x470e, (q15_t)0x3f9c, (q15_t)0x471a, (q15_t)0x3f9b, (q15_t)0x4727, (q15_t)0x3f99, (q15_t)0x4733, (q15_t)0x3f98, + (q15_t)0x4740, (q15_t)0x3f97, (q15_t)0x474c, (q15_t)0x3f95, (q15_t)0x4759, (q15_t)0x3f94, (q15_t)0x4765, (q15_t)0x3f92, + (q15_t)0x4772, (q15_t)0x3f91, (q15_t)0x477e, (q15_t)0x3f8f, (q15_t)0x478b, (q15_t)0x3f8e, (q15_t)0x4797, (q15_t)0x3f8c, + (q15_t)0x47a4, (q15_t)0x3f8b, (q15_t)0x47b0, (q15_t)0x3f89, (q15_t)0x47bd, (q15_t)0x3f88, (q15_t)0x47c9, (q15_t)0x3f86, + (q15_t)0x47d6, (q15_t)0x3f85, (q15_t)0x47e2, (q15_t)0x3f83, (q15_t)0x47ef, (q15_t)0x3f82, (q15_t)0x47fb, (q15_t)0x3f80, + (q15_t)0x4807, (q15_t)0x3f7f, (q15_t)0x4814, (q15_t)0x3f7d, (q15_t)0x4820, (q15_t)0x3f7b, (q15_t)0x482d, (q15_t)0x3f7a, + (q15_t)0x4839, (q15_t)0x3f78, (q15_t)0x4846, (q15_t)0x3f77, (q15_t)0x4852, (q15_t)0x3f75, (q15_t)0x485f, (q15_t)0x3f73, + (q15_t)0x486b, (q15_t)0x3f72, (q15_t)0x4878, (q15_t)0x3f70, (q15_t)0x4884, (q15_t)0x3f6e, (q15_t)0x4891, (q15_t)0x3f6d, + (q15_t)0x489d, (q15_t)0x3f6b, (q15_t)0x48a9, (q15_t)0x3f69, (q15_t)0x48b6, (q15_t)0x3f68, (q15_t)0x48c2, (q15_t)0x3f66, + (q15_t)0x48cf, (q15_t)0x3f64, (q15_t)0x48db, (q15_t)0x3f62, (q15_t)0x48e8, (q15_t)0x3f61, (q15_t)0x48f4, (q15_t)0x3f5f, + (q15_t)0x4901, (q15_t)0x3f5d, (q15_t)0x490d, (q15_t)0x3f5b, (q15_t)0x4919, (q15_t)0x3f5a, (q15_t)0x4926, (q15_t)0x3f58, + (q15_t)0x4932, (q15_t)0x3f56, (q15_t)0x493f, (q15_t)0x3f54, (q15_t)0x494b, (q15_t)0x3f52, (q15_t)0x4958, (q15_t)0x3f51, + (q15_t)0x4964, (q15_t)0x3f4f, (q15_t)0x4970, (q15_t)0x3f4d, (q15_t)0x497d, (q15_t)0x3f4b, (q15_t)0x4989, (q15_t)0x3f49, + (q15_t)0x4996, (q15_t)0x3f47, (q15_t)0x49a2, (q15_t)0x3f45, (q15_t)0x49af, (q15_t)0x3f43, (q15_t)0x49bb, (q15_t)0x3f42, + (q15_t)0x49c7, (q15_t)0x3f40, (q15_t)0x49d4, (q15_t)0x3f3e, (q15_t)0x49e0, (q15_t)0x3f3c, (q15_t)0x49ed, (q15_t)0x3f3a, + (q15_t)0x49f9, (q15_t)0x3f38, (q15_t)0x4a06, (q15_t)0x3f36, (q15_t)0x4a12, (q15_t)0x3f34, (q15_t)0x4a1e, (q15_t)0x3f32, + (q15_t)0x4a2b, (q15_t)0x3f30, (q15_t)0x4a37, (q15_t)0x3f2e, (q15_t)0x4a44, (q15_t)0x3f2c, (q15_t)0x4a50, (q15_t)0x3f2a, + (q15_t)0x4a5c, (q15_t)0x3f28, (q15_t)0x4a69, (q15_t)0x3f26, (q15_t)0x4a75, (q15_t)0x3f24, (q15_t)0x4a82, (q15_t)0x3f22, + (q15_t)0x4a8e, (q15_t)0x3f20, (q15_t)0x4a9a, (q15_t)0x3f1e, (q15_t)0x4aa7, (q15_t)0x3f1c, (q15_t)0x4ab3, (q15_t)0x3f19, + (q15_t)0x4ac0, (q15_t)0x3f17, (q15_t)0x4acc, (q15_t)0x3f15, (q15_t)0x4ad8, (q15_t)0x3f13, (q15_t)0x4ae5, (q15_t)0x3f11, + (q15_t)0x4af1, (q15_t)0x3f0f, (q15_t)0x4afd, (q15_t)0x3f0d, (q15_t)0x4b0a, (q15_t)0x3f0a, (q15_t)0x4b16, (q15_t)0x3f08, + (q15_t)0x4b23, (q15_t)0x3f06, (q15_t)0x4b2f, (q15_t)0x3f04, (q15_t)0x4b3b, (q15_t)0x3f02, (q15_t)0x4b48, (q15_t)0x3f00, + (q15_t)0x4b54, (q15_t)0x3efd, (q15_t)0x4b60, (q15_t)0x3efb, (q15_t)0x4b6d, (q15_t)0x3ef9, (q15_t)0x4b79, (q15_t)0x3ef7, + (q15_t)0x4b85, (q15_t)0x3ef4, (q15_t)0x4b92, (q15_t)0x3ef2, (q15_t)0x4b9e, (q15_t)0x3ef0, (q15_t)0x4bab, (q15_t)0x3eed, + (q15_t)0x4bb7, (q15_t)0x3eeb, (q15_t)0x4bc3, (q15_t)0x3ee9, (q15_t)0x4bd0, (q15_t)0x3ee7, (q15_t)0x4bdc, (q15_t)0x3ee4, + (q15_t)0x4be8, (q15_t)0x3ee2, (q15_t)0x4bf5, (q15_t)0x3ee0, (q15_t)0x4c01, (q15_t)0x3edd, (q15_t)0x4c0d, (q15_t)0x3edb, + (q15_t)0x4c1a, (q15_t)0x3ed8, (q15_t)0x4c26, (q15_t)0x3ed6, (q15_t)0x4c32, (q15_t)0x3ed4, (q15_t)0x4c3f, (q15_t)0x3ed1, + (q15_t)0x4c4b, (q15_t)0x3ecf, (q15_t)0x4c57, (q15_t)0x3ecc, (q15_t)0x4c64, (q15_t)0x3eca, (q15_t)0x4c70, (q15_t)0x3ec8, + (q15_t)0x4c7c, (q15_t)0x3ec5, (q15_t)0x4c89, (q15_t)0x3ec3, (q15_t)0x4c95, (q15_t)0x3ec0, (q15_t)0x4ca1, (q15_t)0x3ebe, + (q15_t)0x4cae, (q15_t)0x3ebb, (q15_t)0x4cba, (q15_t)0x3eb9, (q15_t)0x4cc6, (q15_t)0x3eb6, (q15_t)0x4cd3, (q15_t)0x3eb4, + (q15_t)0x4cdf, (q15_t)0x3eb1, (q15_t)0x4ceb, (q15_t)0x3eaf, (q15_t)0x4cf8, (q15_t)0x3eac, (q15_t)0x4d04, (q15_t)0x3eaa, + (q15_t)0x4d10, (q15_t)0x3ea7, (q15_t)0x4d1c, (q15_t)0x3ea5, (q15_t)0x4d29, (q15_t)0x3ea2, (q15_t)0x4d35, (q15_t)0x3e9f, + (q15_t)0x4d41, (q15_t)0x3e9d, (q15_t)0x4d4e, (q15_t)0x3e9a, (q15_t)0x4d5a, (q15_t)0x3e98, (q15_t)0x4d66, (q15_t)0x3e95, + (q15_t)0x4d72, (q15_t)0x3e92, (q15_t)0x4d7f, (q15_t)0x3e90, (q15_t)0x4d8b, (q15_t)0x3e8d, (q15_t)0x4d97, (q15_t)0x3e8a, + (q15_t)0x4da4, (q15_t)0x3e88, (q15_t)0x4db0, (q15_t)0x3e85, (q15_t)0x4dbc, (q15_t)0x3e82, (q15_t)0x4dc8, (q15_t)0x3e80, + (q15_t)0x4dd5, (q15_t)0x3e7d, (q15_t)0x4de1, (q15_t)0x3e7a, (q15_t)0x4ded, (q15_t)0x3e77, (q15_t)0x4df9, (q15_t)0x3e75, + (q15_t)0x4e06, (q15_t)0x3e72, (q15_t)0x4e12, (q15_t)0x3e6f, (q15_t)0x4e1e, (q15_t)0x3e6c, (q15_t)0x4e2b, (q15_t)0x3e6a, + (q15_t)0x4e37, (q15_t)0x3e67, (q15_t)0x4e43, (q15_t)0x3e64, (q15_t)0x4e4f, (q15_t)0x3e61, (q15_t)0x4e5c, (q15_t)0x3e5e, + (q15_t)0x4e68, (q15_t)0x3e5c, (q15_t)0x4e74, (q15_t)0x3e59, (q15_t)0x4e80, (q15_t)0x3e56, (q15_t)0x4e8c, (q15_t)0x3e53, + (q15_t)0x4e99, (q15_t)0x3e50, (q15_t)0x4ea5, (q15_t)0x3e4d, (q15_t)0x4eb1, (q15_t)0x3e4a, (q15_t)0x4ebd, (q15_t)0x3e48, + (q15_t)0x4eca, (q15_t)0x3e45, (q15_t)0x4ed6, (q15_t)0x3e42, (q15_t)0x4ee2, (q15_t)0x3e3f, (q15_t)0x4eee, (q15_t)0x3e3c, + (q15_t)0x4efb, (q15_t)0x3e39, (q15_t)0x4f07, (q15_t)0x3e36, (q15_t)0x4f13, (q15_t)0x3e33, (q15_t)0x4f1f, (q15_t)0x3e30, + (q15_t)0x4f2b, (q15_t)0x3e2d, (q15_t)0x4f38, (q15_t)0x3e2a, (q15_t)0x4f44, (q15_t)0x3e27, (q15_t)0x4f50, (q15_t)0x3e24, + (q15_t)0x4f5c, (q15_t)0x3e21, (q15_t)0x4f68, (q15_t)0x3e1e, (q15_t)0x4f75, (q15_t)0x3e1b, (q15_t)0x4f81, (q15_t)0x3e18, + (q15_t)0x4f8d, (q15_t)0x3e15, (q15_t)0x4f99, (q15_t)0x3e12, (q15_t)0x4fa5, (q15_t)0x3e0f, (q15_t)0x4fb2, (q15_t)0x3e0c, + (q15_t)0x4fbe, (q15_t)0x3e09, (q15_t)0x4fca, (q15_t)0x3e06, (q15_t)0x4fd6, (q15_t)0x3e03, (q15_t)0x4fe2, (q15_t)0x3dff, + (q15_t)0x4fee, (q15_t)0x3dfc, (q15_t)0x4ffb, (q15_t)0x3df9, (q15_t)0x5007, (q15_t)0x3df6, (q15_t)0x5013, (q15_t)0x3df3, + (q15_t)0x501f, (q15_t)0x3df0, (q15_t)0x502b, (q15_t)0x3ded, (q15_t)0x5037, (q15_t)0x3de9, (q15_t)0x5044, (q15_t)0x3de6, + (q15_t)0x5050, (q15_t)0x3de3, (q15_t)0x505c, (q15_t)0x3de0, (q15_t)0x5068, (q15_t)0x3ddd, (q15_t)0x5074, (q15_t)0x3dd9, + (q15_t)0x5080, (q15_t)0x3dd6, (q15_t)0x508c, (q15_t)0x3dd3, (q15_t)0x5099, (q15_t)0x3dd0, (q15_t)0x50a5, (q15_t)0x3dcc, + (q15_t)0x50b1, (q15_t)0x3dc9, (q15_t)0x50bd, (q15_t)0x3dc6, (q15_t)0x50c9, (q15_t)0x3dc2, (q15_t)0x50d5, (q15_t)0x3dbf, + (q15_t)0x50e1, (q15_t)0x3dbc, (q15_t)0x50ed, (q15_t)0x3db9, (q15_t)0x50fa, (q15_t)0x3db5, (q15_t)0x5106, (q15_t)0x3db2, + (q15_t)0x5112, (q15_t)0x3daf, (q15_t)0x511e, (q15_t)0x3dab, (q15_t)0x512a, (q15_t)0x3da8, (q15_t)0x5136, (q15_t)0x3da4, + (q15_t)0x5142, (q15_t)0x3da1, (q15_t)0x514e, (q15_t)0x3d9e, (q15_t)0x515a, (q15_t)0x3d9a, (q15_t)0x5167, (q15_t)0x3d97, + (q15_t)0x5173, (q15_t)0x3d93, (q15_t)0x517f, (q15_t)0x3d90, (q15_t)0x518b, (q15_t)0x3d8d, (q15_t)0x5197, (q15_t)0x3d89, + (q15_t)0x51a3, (q15_t)0x3d86, (q15_t)0x51af, (q15_t)0x3d82, (q15_t)0x51bb, (q15_t)0x3d7f, (q15_t)0x51c7, (q15_t)0x3d7b, + (q15_t)0x51d3, (q15_t)0x3d78, (q15_t)0x51df, (q15_t)0x3d74, (q15_t)0x51eb, (q15_t)0x3d71, (q15_t)0x51f7, (q15_t)0x3d6d, + (q15_t)0x5204, (q15_t)0x3d6a, (q15_t)0x5210, (q15_t)0x3d66, (q15_t)0x521c, (q15_t)0x3d63, (q15_t)0x5228, (q15_t)0x3d5f, + (q15_t)0x5234, (q15_t)0x3d5b, (q15_t)0x5240, (q15_t)0x3d58, (q15_t)0x524c, (q15_t)0x3d54, (q15_t)0x5258, (q15_t)0x3d51, + (q15_t)0x5264, (q15_t)0x3d4d, (q15_t)0x5270, (q15_t)0x3d49, (q15_t)0x527c, (q15_t)0x3d46, (q15_t)0x5288, (q15_t)0x3d42, + (q15_t)0x5294, (q15_t)0x3d3f, (q15_t)0x52a0, (q15_t)0x3d3b, (q15_t)0x52ac, (q15_t)0x3d37, (q15_t)0x52b8, (q15_t)0x3d34, + (q15_t)0x52c4, (q15_t)0x3d30, (q15_t)0x52d0, (q15_t)0x3d2c, (q15_t)0x52dc, (q15_t)0x3d28, (q15_t)0x52e8, (q15_t)0x3d25, + (q15_t)0x52f4, (q15_t)0x3d21, (q15_t)0x5300, (q15_t)0x3d1d, (q15_t)0x530c, (q15_t)0x3d1a, (q15_t)0x5318, (q15_t)0x3d16, + (q15_t)0x5324, (q15_t)0x3d12, (q15_t)0x5330, (q15_t)0x3d0e, (q15_t)0x533c, (q15_t)0x3d0b, (q15_t)0x5348, (q15_t)0x3d07, + (q15_t)0x5354, (q15_t)0x3d03, (q15_t)0x5360, (q15_t)0x3cff, (q15_t)0x536c, (q15_t)0x3cfb, (q15_t)0x5378, (q15_t)0x3cf8, + (q15_t)0x5384, (q15_t)0x3cf4, (q15_t)0x5390, (q15_t)0x3cf0, (q15_t)0x539c, (q15_t)0x3cec, (q15_t)0x53a8, (q15_t)0x3ce8, + (q15_t)0x53b4, (q15_t)0x3ce4, (q15_t)0x53c0, (q15_t)0x3ce0, (q15_t)0x53cc, (q15_t)0x3cdd, (q15_t)0x53d8, (q15_t)0x3cd9, + (q15_t)0x53e4, (q15_t)0x3cd5, (q15_t)0x53f0, (q15_t)0x3cd1, (q15_t)0x53fb, (q15_t)0x3ccd, (q15_t)0x5407, (q15_t)0x3cc9, + (q15_t)0x5413, (q15_t)0x3cc5, (q15_t)0x541f, (q15_t)0x3cc1, (q15_t)0x542b, (q15_t)0x3cbd, (q15_t)0x5437, (q15_t)0x3cb9, + (q15_t)0x5443, (q15_t)0x3cb5, (q15_t)0x544f, (q15_t)0x3cb1, (q15_t)0x545b, (q15_t)0x3cad, (q15_t)0x5467, (q15_t)0x3ca9, + (q15_t)0x5473, (q15_t)0x3ca5, (q15_t)0x547f, (q15_t)0x3ca1, (q15_t)0x548b, (q15_t)0x3c9d, (q15_t)0x5496, (q15_t)0x3c99, + (q15_t)0x54a2, (q15_t)0x3c95, (q15_t)0x54ae, (q15_t)0x3c91, (q15_t)0x54ba, (q15_t)0x3c8d, (q15_t)0x54c6, (q15_t)0x3c89, + (q15_t)0x54d2, (q15_t)0x3c85, (q15_t)0x54de, (q15_t)0x3c81, (q15_t)0x54ea, (q15_t)0x3c7d, (q15_t)0x54f6, (q15_t)0x3c79, + (q15_t)0x5501, (q15_t)0x3c74, (q15_t)0x550d, (q15_t)0x3c70, (q15_t)0x5519, (q15_t)0x3c6c, (q15_t)0x5525, (q15_t)0x3c68, + (q15_t)0x5531, (q15_t)0x3c64, (q15_t)0x553d, (q15_t)0x3c60, (q15_t)0x5549, (q15_t)0x3c5b, (q15_t)0x5554, (q15_t)0x3c57, + (q15_t)0x5560, (q15_t)0x3c53, (q15_t)0x556c, (q15_t)0x3c4f, (q15_t)0x5578, (q15_t)0x3c4b, (q15_t)0x5584, (q15_t)0x3c46, + (q15_t)0x5590, (q15_t)0x3c42, (q15_t)0x559b, (q15_t)0x3c3e, (q15_t)0x55a7, (q15_t)0x3c3a, (q15_t)0x55b3, (q15_t)0x3c36, + (q15_t)0x55bf, (q15_t)0x3c31, (q15_t)0x55cb, (q15_t)0x3c2d, (q15_t)0x55d7, (q15_t)0x3c29, (q15_t)0x55e2, (q15_t)0x3c24, + (q15_t)0x55ee, (q15_t)0x3c20, (q15_t)0x55fa, (q15_t)0x3c1c, (q15_t)0x5606, (q15_t)0x3c17, (q15_t)0x5612, (q15_t)0x3c13, + (q15_t)0x561d, (q15_t)0x3c0f, (q15_t)0x5629, (q15_t)0x3c0a, (q15_t)0x5635, (q15_t)0x3c06, (q15_t)0x5641, (q15_t)0x3c02, + (q15_t)0x564c, (q15_t)0x3bfd, (q15_t)0x5658, (q15_t)0x3bf9, (q15_t)0x5664, (q15_t)0x3bf5, (q15_t)0x5670, (q15_t)0x3bf0, + (q15_t)0x567c, (q15_t)0x3bec, (q15_t)0x5687, (q15_t)0x3be7, (q15_t)0x5693, (q15_t)0x3be3, (q15_t)0x569f, (q15_t)0x3bde, + (q15_t)0x56ab, (q15_t)0x3bda, (q15_t)0x56b6, (q15_t)0x3bd6, (q15_t)0x56c2, (q15_t)0x3bd1, (q15_t)0x56ce, (q15_t)0x3bcd, + (q15_t)0x56da, (q15_t)0x3bc8, (q15_t)0x56e5, (q15_t)0x3bc4, (q15_t)0x56f1, (q15_t)0x3bbf, (q15_t)0x56fd, (q15_t)0x3bbb, + (q15_t)0x5709, (q15_t)0x3bb6, (q15_t)0x5714, (q15_t)0x3bb2, (q15_t)0x5720, (q15_t)0x3bad, (q15_t)0x572c, (q15_t)0x3ba9, + (q15_t)0x5737, (q15_t)0x3ba4, (q15_t)0x5743, (q15_t)0x3b9f, (q15_t)0x574f, (q15_t)0x3b9b, (q15_t)0x575b, (q15_t)0x3b96, + (q15_t)0x5766, (q15_t)0x3b92, (q15_t)0x5772, (q15_t)0x3b8d, (q15_t)0x577e, (q15_t)0x3b88, (q15_t)0x5789, (q15_t)0x3b84, + (q15_t)0x5795, (q15_t)0x3b7f, (q15_t)0x57a1, (q15_t)0x3b7b, (q15_t)0x57ac, (q15_t)0x3b76, (q15_t)0x57b8, (q15_t)0x3b71, + (q15_t)0x57c4, (q15_t)0x3b6d, (q15_t)0x57cf, (q15_t)0x3b68, (q15_t)0x57db, (q15_t)0x3b63, (q15_t)0x57e7, (q15_t)0x3b5f, + (q15_t)0x57f2, (q15_t)0x3b5a, (q15_t)0x57fe, (q15_t)0x3b55, (q15_t)0x580a, (q15_t)0x3b50, (q15_t)0x5815, (q15_t)0x3b4c, + (q15_t)0x5821, (q15_t)0x3b47, (q15_t)0x582d, (q15_t)0x3b42, (q15_t)0x5838, (q15_t)0x3b3e, (q15_t)0x5844, (q15_t)0x3b39, + (q15_t)0x584f, (q15_t)0x3b34, (q15_t)0x585b, (q15_t)0x3b2f, (q15_t)0x5867, (q15_t)0x3b2a, (q15_t)0x5872, (q15_t)0x3b26, + (q15_t)0x587e, (q15_t)0x3b21, (q15_t)0x5889, (q15_t)0x3b1c, (q15_t)0x5895, (q15_t)0x3b17, (q15_t)0x58a1, (q15_t)0x3b12, + (q15_t)0x58ac, (q15_t)0x3b0e, (q15_t)0x58b8, (q15_t)0x3b09, (q15_t)0x58c3, (q15_t)0x3b04, (q15_t)0x58cf, (q15_t)0x3aff, + (q15_t)0x58db, (q15_t)0x3afa, (q15_t)0x58e6, (q15_t)0x3af5, (q15_t)0x58f2, (q15_t)0x3af0, (q15_t)0x58fd, (q15_t)0x3aeb, + (q15_t)0x5909, (q15_t)0x3ae6, (q15_t)0x5914, (q15_t)0x3ae2, (q15_t)0x5920, (q15_t)0x3add, (q15_t)0x592c, (q15_t)0x3ad8, + (q15_t)0x5937, (q15_t)0x3ad3, (q15_t)0x5943, (q15_t)0x3ace, (q15_t)0x594e, (q15_t)0x3ac9, (q15_t)0x595a, (q15_t)0x3ac4, + (q15_t)0x5965, (q15_t)0x3abf, (q15_t)0x5971, (q15_t)0x3aba, (q15_t)0x597c, (q15_t)0x3ab5, (q15_t)0x5988, (q15_t)0x3ab0, + (q15_t)0x5993, (q15_t)0x3aab, (q15_t)0x599f, (q15_t)0x3aa6, (q15_t)0x59aa, (q15_t)0x3aa1, (q15_t)0x59b6, (q15_t)0x3a9c, + (q15_t)0x59c1, (q15_t)0x3a97, (q15_t)0x59cd, (q15_t)0x3a92, (q15_t)0x59d8, (q15_t)0x3a8d, (q15_t)0x59e4, (q15_t)0x3a88, + (q15_t)0x59ef, (q15_t)0x3a82, (q15_t)0x59fb, (q15_t)0x3a7d, (q15_t)0x5a06, (q15_t)0x3a78, (q15_t)0x5a12, (q15_t)0x3a73, + (q15_t)0x5a1d, (q15_t)0x3a6e, (q15_t)0x5a29, (q15_t)0x3a69, (q15_t)0x5a34, (q15_t)0x3a64, (q15_t)0x5a40, (q15_t)0x3a5f, + (q15_t)0x5a4b, (q15_t)0x3a59, (q15_t)0x5a57, (q15_t)0x3a54, (q15_t)0x5a62, (q15_t)0x3a4f, (q15_t)0x5a6e, (q15_t)0x3a4a, + (q15_t)0x5a79, (q15_t)0x3a45, (q15_t)0x5a84, (q15_t)0x3a3f, (q15_t)0x5a90, (q15_t)0x3a3a, (q15_t)0x5a9b, (q15_t)0x3a35, + (q15_t)0x5aa7, (q15_t)0x3a30, (q15_t)0x5ab2, (q15_t)0x3a2b, (q15_t)0x5abe, (q15_t)0x3a25, (q15_t)0x5ac9, (q15_t)0x3a20, + (q15_t)0x5ad4, (q15_t)0x3a1b, (q15_t)0x5ae0, (q15_t)0x3a16, (q15_t)0x5aeb, (q15_t)0x3a10, (q15_t)0x5af7, (q15_t)0x3a0b, + (q15_t)0x5b02, (q15_t)0x3a06, (q15_t)0x5b0d, (q15_t)0x3a00, (q15_t)0x5b19, (q15_t)0x39fb, (q15_t)0x5b24, (q15_t)0x39f6, + (q15_t)0x5b30, (q15_t)0x39f0, (q15_t)0x5b3b, (q15_t)0x39eb, (q15_t)0x5b46, (q15_t)0x39e6, (q15_t)0x5b52, (q15_t)0x39e0, + (q15_t)0x5b5d, (q15_t)0x39db, (q15_t)0x5b68, (q15_t)0x39d6, (q15_t)0x5b74, (q15_t)0x39d0, (q15_t)0x5b7f, (q15_t)0x39cb, + (q15_t)0x5b8a, (q15_t)0x39c5, (q15_t)0x5b96, (q15_t)0x39c0, (q15_t)0x5ba1, (q15_t)0x39bb, (q15_t)0x5bac, (q15_t)0x39b5, + (q15_t)0x5bb8, (q15_t)0x39b0, (q15_t)0x5bc3, (q15_t)0x39aa, (q15_t)0x5bce, (q15_t)0x39a5, (q15_t)0x5bda, (q15_t)0x399f, + (q15_t)0x5be5, (q15_t)0x399a, (q15_t)0x5bf0, (q15_t)0x3994, (q15_t)0x5bfc, (q15_t)0x398f, (q15_t)0x5c07, (q15_t)0x3989, + (q15_t)0x5c12, (q15_t)0x3984, (q15_t)0x5c1e, (q15_t)0x397e, (q15_t)0x5c29, (q15_t)0x3979, (q15_t)0x5c34, (q15_t)0x3973, + (q15_t)0x5c3f, (q15_t)0x396e, (q15_t)0x5c4b, (q15_t)0x3968, (q15_t)0x5c56, (q15_t)0x3963, (q15_t)0x5c61, (q15_t)0x395d, + (q15_t)0x5c6c, (q15_t)0x3958, (q15_t)0x5c78, (q15_t)0x3952, (q15_t)0x5c83, (q15_t)0x394c, (q15_t)0x5c8e, (q15_t)0x3947, + (q15_t)0x5c99, (q15_t)0x3941, (q15_t)0x5ca5, (q15_t)0x393b, (q15_t)0x5cb0, (q15_t)0x3936, (q15_t)0x5cbb, (q15_t)0x3930, + (q15_t)0x5cc6, (q15_t)0x392b, (q15_t)0x5cd2, (q15_t)0x3925, (q15_t)0x5cdd, (q15_t)0x391f, (q15_t)0x5ce8, (q15_t)0x391a, + (q15_t)0x5cf3, (q15_t)0x3914, (q15_t)0x5cff, (q15_t)0x390e, (q15_t)0x5d0a, (q15_t)0x3909, (q15_t)0x5d15, (q15_t)0x3903, + (q15_t)0x5d20, (q15_t)0x38fd, (q15_t)0x5d2b, (q15_t)0x38f7, (q15_t)0x5d36, (q15_t)0x38f2, (q15_t)0x5d42, (q15_t)0x38ec, + (q15_t)0x5d4d, (q15_t)0x38e6, (q15_t)0x5d58, (q15_t)0x38e0, (q15_t)0x5d63, (q15_t)0x38db, (q15_t)0x5d6e, (q15_t)0x38d5, + (q15_t)0x5d79, (q15_t)0x38cf, (q15_t)0x5d85, (q15_t)0x38c9, (q15_t)0x5d90, (q15_t)0x38c3, (q15_t)0x5d9b, (q15_t)0x38be, + (q15_t)0x5da6, (q15_t)0x38b8, (q15_t)0x5db1, (q15_t)0x38b2, (q15_t)0x5dbc, (q15_t)0x38ac, (q15_t)0x5dc7, (q15_t)0x38a6, + (q15_t)0x5dd3, (q15_t)0x38a1, (q15_t)0x5dde, (q15_t)0x389b, (q15_t)0x5de9, (q15_t)0x3895, (q15_t)0x5df4, (q15_t)0x388f, + (q15_t)0x5dff, (q15_t)0x3889, (q15_t)0x5e0a, (q15_t)0x3883, (q15_t)0x5e15, (q15_t)0x387d, (q15_t)0x5e20, (q15_t)0x3877, + (q15_t)0x5e2b, (q15_t)0x3871, (q15_t)0x5e36, (q15_t)0x386b, (q15_t)0x5e42, (q15_t)0x3866, (q15_t)0x5e4d, (q15_t)0x3860, + (q15_t)0x5e58, (q15_t)0x385a, (q15_t)0x5e63, (q15_t)0x3854, (q15_t)0x5e6e, (q15_t)0x384e, (q15_t)0x5e79, (q15_t)0x3848, + (q15_t)0x5e84, (q15_t)0x3842, (q15_t)0x5e8f, (q15_t)0x383c, (q15_t)0x5e9a, (q15_t)0x3836, (q15_t)0x5ea5, (q15_t)0x3830, + (q15_t)0x5eb0, (q15_t)0x382a, (q15_t)0x5ebb, (q15_t)0x3824, (q15_t)0x5ec6, (q15_t)0x381e, (q15_t)0x5ed1, (q15_t)0x3818, + (q15_t)0x5edc, (q15_t)0x3812, (q15_t)0x5ee7, (q15_t)0x380b, (q15_t)0x5ef2, (q15_t)0x3805, (q15_t)0x5efd, (q15_t)0x37ff, + (q15_t)0x5f08, (q15_t)0x37f9, (q15_t)0x5f13, (q15_t)0x37f3, (q15_t)0x5f1e, (q15_t)0x37ed, (q15_t)0x5f29, (q15_t)0x37e7, + (q15_t)0x5f34, (q15_t)0x37e1, (q15_t)0x5f3f, (q15_t)0x37db, (q15_t)0x5f4a, (q15_t)0x37d5, (q15_t)0x5f55, (q15_t)0x37ce, + (q15_t)0x5f60, (q15_t)0x37c8, (q15_t)0x5f6b, (q15_t)0x37c2, (q15_t)0x5f76, (q15_t)0x37bc, (q15_t)0x5f81, (q15_t)0x37b6, + (q15_t)0x5f8c, (q15_t)0x37b0, (q15_t)0x5f97, (q15_t)0x37a9, (q15_t)0x5fa2, (q15_t)0x37a3, (q15_t)0x5fac, (q15_t)0x379d, + (q15_t)0x5fb7, (q15_t)0x3797, (q15_t)0x5fc2, (q15_t)0x3790, (q15_t)0x5fcd, (q15_t)0x378a, (q15_t)0x5fd8, (q15_t)0x3784, + (q15_t)0x5fe3, (q15_t)0x377e, (q15_t)0x5fee, (q15_t)0x3777, (q15_t)0x5ff9, (q15_t)0x3771, (q15_t)0x6004, (q15_t)0x376b, + (q15_t)0x600f, (q15_t)0x3765, (q15_t)0x6019, (q15_t)0x375e, (q15_t)0x6024, (q15_t)0x3758, (q15_t)0x602f, (q15_t)0x3752, + (q15_t)0x603a, (q15_t)0x374b, (q15_t)0x6045, (q15_t)0x3745, (q15_t)0x6050, (q15_t)0x373f, (q15_t)0x605b, (q15_t)0x3738, + (q15_t)0x6065, (q15_t)0x3732, (q15_t)0x6070, (q15_t)0x372c, (q15_t)0x607b, (q15_t)0x3725, (q15_t)0x6086, (q15_t)0x371f, + (q15_t)0x6091, (q15_t)0x3718, (q15_t)0x609b, (q15_t)0x3712, (q15_t)0x60a6, (q15_t)0x370c, (q15_t)0x60b1, (q15_t)0x3705, + (q15_t)0x60bc, (q15_t)0x36ff, (q15_t)0x60c7, (q15_t)0x36f8, (q15_t)0x60d1, (q15_t)0x36f2, (q15_t)0x60dc, (q15_t)0x36eb, + (q15_t)0x60e7, (q15_t)0x36e5, (q15_t)0x60f2, (q15_t)0x36df, (q15_t)0x60fd, (q15_t)0x36d8, (q15_t)0x6107, (q15_t)0x36d2, + (q15_t)0x6112, (q15_t)0x36cb, (q15_t)0x611d, (q15_t)0x36c5, (q15_t)0x6128, (q15_t)0x36be, (q15_t)0x6132, (q15_t)0x36b8, + (q15_t)0x613d, (q15_t)0x36b1, (q15_t)0x6148, (q15_t)0x36ab, (q15_t)0x6153, (q15_t)0x36a4, (q15_t)0x615d, (q15_t)0x369d, + (q15_t)0x6168, (q15_t)0x3697, (q15_t)0x6173, (q15_t)0x3690, (q15_t)0x617d, (q15_t)0x368a, (q15_t)0x6188, (q15_t)0x3683, + (q15_t)0x6193, (q15_t)0x367d, (q15_t)0x619e, (q15_t)0x3676, (q15_t)0x61a8, (q15_t)0x366f, (q15_t)0x61b3, (q15_t)0x3669, + (q15_t)0x61be, (q15_t)0x3662, (q15_t)0x61c8, (q15_t)0x365c, (q15_t)0x61d3, (q15_t)0x3655, (q15_t)0x61de, (q15_t)0x364e, + (q15_t)0x61e8, (q15_t)0x3648, (q15_t)0x61f3, (q15_t)0x3641, (q15_t)0x61fe, (q15_t)0x363a, (q15_t)0x6208, (q15_t)0x3634, + (q15_t)0x6213, (q15_t)0x362d, (q15_t)0x621e, (q15_t)0x3626, (q15_t)0x6228, (q15_t)0x3620, (q15_t)0x6233, (q15_t)0x3619, + (q15_t)0x623d, (q15_t)0x3612, (q15_t)0x6248, (q15_t)0x360b, (q15_t)0x6253, (q15_t)0x3605, (q15_t)0x625d, (q15_t)0x35fe, + (q15_t)0x6268, (q15_t)0x35f7, (q15_t)0x6272, (q15_t)0x35f0, (q15_t)0x627d, (q15_t)0x35ea, (q15_t)0x6288, (q15_t)0x35e3, + (q15_t)0x6292, (q15_t)0x35dc, (q15_t)0x629d, (q15_t)0x35d5, (q15_t)0x62a7, (q15_t)0x35ce, (q15_t)0x62b2, (q15_t)0x35c8, + (q15_t)0x62bc, (q15_t)0x35c1, (q15_t)0x62c7, (q15_t)0x35ba, (q15_t)0x62d2, (q15_t)0x35b3, (q15_t)0x62dc, (q15_t)0x35ac, + (q15_t)0x62e7, (q15_t)0x35a5, (q15_t)0x62f1, (q15_t)0x359f, (q15_t)0x62fc, (q15_t)0x3598, (q15_t)0x6306, (q15_t)0x3591, + (q15_t)0x6311, (q15_t)0x358a, (q15_t)0x631b, (q15_t)0x3583, (q15_t)0x6326, (q15_t)0x357c, (q15_t)0x6330, (q15_t)0x3575, + (q15_t)0x633b, (q15_t)0x356e, (q15_t)0x6345, (q15_t)0x3567, (q15_t)0x6350, (q15_t)0x3561, (q15_t)0x635a, (q15_t)0x355a, + (q15_t)0x6365, (q15_t)0x3553, (q15_t)0x636f, (q15_t)0x354c, (q15_t)0x637a, (q15_t)0x3545, (q15_t)0x6384, (q15_t)0x353e, + (q15_t)0x638e, (q15_t)0x3537, (q15_t)0x6399, (q15_t)0x3530, (q15_t)0x63a3, (q15_t)0x3529, (q15_t)0x63ae, (q15_t)0x3522, + (q15_t)0x63b8, (q15_t)0x351b, (q15_t)0x63c3, (q15_t)0x3514, (q15_t)0x63cd, (q15_t)0x350d, (q15_t)0x63d7, (q15_t)0x3506, + (q15_t)0x63e2, (q15_t)0x34ff, (q15_t)0x63ec, (q15_t)0x34f8, (q15_t)0x63f7, (q15_t)0x34f1, (q15_t)0x6401, (q15_t)0x34ea, + (q15_t)0x640b, (q15_t)0x34e2, (q15_t)0x6416, (q15_t)0x34db, (q15_t)0x6420, (q15_t)0x34d4, (q15_t)0x642b, (q15_t)0x34cd, + (q15_t)0x6435, (q15_t)0x34c6, (q15_t)0x643f, (q15_t)0x34bf, (q15_t)0x644a, (q15_t)0x34b8, (q15_t)0x6454, (q15_t)0x34b1, + (q15_t)0x645e, (q15_t)0x34aa, (q15_t)0x6469, (q15_t)0x34a2, (q15_t)0x6473, (q15_t)0x349b, (q15_t)0x647d, (q15_t)0x3494, + (q15_t)0x6488, (q15_t)0x348d, (q15_t)0x6492, (q15_t)0x3486, (q15_t)0x649c, (q15_t)0x347f, (q15_t)0x64a7, (q15_t)0x3477, + (q15_t)0x64b1, (q15_t)0x3470, (q15_t)0x64bb, (q15_t)0x3469, (q15_t)0x64c5, (q15_t)0x3462, (q15_t)0x64d0, (q15_t)0x345b, + (q15_t)0x64da, (q15_t)0x3453, (q15_t)0x64e4, (q15_t)0x344c, (q15_t)0x64ef, (q15_t)0x3445, (q15_t)0x64f9, (q15_t)0x343e, + (q15_t)0x6503, (q15_t)0x3436, (q15_t)0x650d, (q15_t)0x342f, (q15_t)0x6518, (q15_t)0x3428, (q15_t)0x6522, (q15_t)0x3420, + (q15_t)0x652c, (q15_t)0x3419, (q15_t)0x6536, (q15_t)0x3412, (q15_t)0x6541, (q15_t)0x340b, (q15_t)0x654b, (q15_t)0x3403, + (q15_t)0x6555, (q15_t)0x33fc, (q15_t)0x655f, (q15_t)0x33f5, (q15_t)0x6569, (q15_t)0x33ed, (q15_t)0x6574, (q15_t)0x33e6, + (q15_t)0x657e, (q15_t)0x33df, (q15_t)0x6588, (q15_t)0x33d7, (q15_t)0x6592, (q15_t)0x33d0, (q15_t)0x659c, (q15_t)0x33c8, + (q15_t)0x65a6, (q15_t)0x33c1, (q15_t)0x65b1, (q15_t)0x33ba, (q15_t)0x65bb, (q15_t)0x33b2, (q15_t)0x65c5, (q15_t)0x33ab, + (q15_t)0x65cf, (q15_t)0x33a3, (q15_t)0x65d9, (q15_t)0x339c, (q15_t)0x65e3, (q15_t)0x3395, (q15_t)0x65ed, (q15_t)0x338d, + (q15_t)0x65f8, (q15_t)0x3386, (q15_t)0x6602, (q15_t)0x337e, (q15_t)0x660c, (q15_t)0x3377, (q15_t)0x6616, (q15_t)0x336f, + (q15_t)0x6620, (q15_t)0x3368, (q15_t)0x662a, (q15_t)0x3360, (q15_t)0x6634, (q15_t)0x3359, (q15_t)0x663e, (q15_t)0x3351, + (q15_t)0x6648, (q15_t)0x334a, (q15_t)0x6652, (q15_t)0x3342, (q15_t)0x665c, (q15_t)0x333b, (q15_t)0x6666, (q15_t)0x3333, + (q15_t)0x6671, (q15_t)0x332c, (q15_t)0x667b, (q15_t)0x3324, (q15_t)0x6685, (q15_t)0x331d, (q15_t)0x668f, (q15_t)0x3315, + (q15_t)0x6699, (q15_t)0x330d, (q15_t)0x66a3, (q15_t)0x3306, (q15_t)0x66ad, (q15_t)0x32fe, (q15_t)0x66b7, (q15_t)0x32f7, + (q15_t)0x66c1, (q15_t)0x32ef, (q15_t)0x66cb, (q15_t)0x32e7, (q15_t)0x66d5, (q15_t)0x32e0, (q15_t)0x66df, (q15_t)0x32d8, + (q15_t)0x66e9, (q15_t)0x32d0, (q15_t)0x66f3, (q15_t)0x32c9, (q15_t)0x66fd, (q15_t)0x32c1, (q15_t)0x6707, (q15_t)0x32ba, + (q15_t)0x6711, (q15_t)0x32b2, (q15_t)0x671a, (q15_t)0x32aa, (q15_t)0x6724, (q15_t)0x32a3, (q15_t)0x672e, (q15_t)0x329b, + (q15_t)0x6738, (q15_t)0x3293, (q15_t)0x6742, (q15_t)0x328b, (q15_t)0x674c, (q15_t)0x3284, (q15_t)0x6756, (q15_t)0x327c, + (q15_t)0x6760, (q15_t)0x3274, (q15_t)0x676a, (q15_t)0x326d, (q15_t)0x6774, (q15_t)0x3265, (q15_t)0x677e, (q15_t)0x325d, + (q15_t)0x6788, (q15_t)0x3255, (q15_t)0x6791, (q15_t)0x324e, (q15_t)0x679b, (q15_t)0x3246, (q15_t)0x67a5, (q15_t)0x323e, + (q15_t)0x67af, (q15_t)0x3236, (q15_t)0x67b9, (q15_t)0x322e, (q15_t)0x67c3, (q15_t)0x3227, (q15_t)0x67cd, (q15_t)0x321f, + (q15_t)0x67d6, (q15_t)0x3217, (q15_t)0x67e0, (q15_t)0x320f, (q15_t)0x67ea, (q15_t)0x3207, (q15_t)0x67f4, (q15_t)0x31ff, + (q15_t)0x67fe, (q15_t)0x31f8, (q15_t)0x6808, (q15_t)0x31f0, (q15_t)0x6811, (q15_t)0x31e8, (q15_t)0x681b, (q15_t)0x31e0, + (q15_t)0x6825, (q15_t)0x31d8, (q15_t)0x682f, (q15_t)0x31d0, (q15_t)0x6838, (q15_t)0x31c8, (q15_t)0x6842, (q15_t)0x31c0, + (q15_t)0x684c, (q15_t)0x31b9, (q15_t)0x6856, (q15_t)0x31b1, (q15_t)0x6860, (q15_t)0x31a9, (q15_t)0x6869, (q15_t)0x31a1, + (q15_t)0x6873, (q15_t)0x3199, (q15_t)0x687d, (q15_t)0x3191, (q15_t)0x6886, (q15_t)0x3189, (q15_t)0x6890, (q15_t)0x3181, + (q15_t)0x689a, (q15_t)0x3179, (q15_t)0x68a4, (q15_t)0x3171, (q15_t)0x68ad, (q15_t)0x3169, (q15_t)0x68b7, (q15_t)0x3161, + (q15_t)0x68c1, (q15_t)0x3159, (q15_t)0x68ca, (q15_t)0x3151, (q15_t)0x68d4, (q15_t)0x3149, (q15_t)0x68de, (q15_t)0x3141, + (q15_t)0x68e7, (q15_t)0x3139, (q15_t)0x68f1, (q15_t)0x3131, (q15_t)0x68fb, (q15_t)0x3129, (q15_t)0x6904, (q15_t)0x3121, + (q15_t)0x690e, (q15_t)0x3119, (q15_t)0x6918, (q15_t)0x3111, (q15_t)0x6921, (q15_t)0x3109, (q15_t)0x692b, (q15_t)0x3101, + (q15_t)0x6935, (q15_t)0x30f9, (q15_t)0x693e, (q15_t)0x30f0, (q15_t)0x6948, (q15_t)0x30e8, (q15_t)0x6951, (q15_t)0x30e0, + (q15_t)0x695b, (q15_t)0x30d8, (q15_t)0x6965, (q15_t)0x30d0, (q15_t)0x696e, (q15_t)0x30c8, (q15_t)0x6978, (q15_t)0x30c0, + (q15_t)0x6981, (q15_t)0x30b8, (q15_t)0x698b, (q15_t)0x30af, (q15_t)0x6994, (q15_t)0x30a7, (q15_t)0x699e, (q15_t)0x309f, + (q15_t)0x69a7, (q15_t)0x3097, (q15_t)0x69b1, (q15_t)0x308f, (q15_t)0x69bb, (q15_t)0x3087, (q15_t)0x69c4, (q15_t)0x307e, + (q15_t)0x69ce, (q15_t)0x3076, (q15_t)0x69d7, (q15_t)0x306e, (q15_t)0x69e1, (q15_t)0x3066, (q15_t)0x69ea, (q15_t)0x305d, + (q15_t)0x69f4, (q15_t)0x3055, (q15_t)0x69fd, (q15_t)0x304d, (q15_t)0x6a07, (q15_t)0x3045, (q15_t)0x6a10, (q15_t)0x303c, + (q15_t)0x6a1a, (q15_t)0x3034, (q15_t)0x6a23, (q15_t)0x302c, (q15_t)0x6a2c, (q15_t)0x3024, (q15_t)0x6a36, (q15_t)0x301b, + (q15_t)0x6a3f, (q15_t)0x3013, (q15_t)0x6a49, (q15_t)0x300b, (q15_t)0x6a52, (q15_t)0x3002, (q15_t)0x6a5c, (q15_t)0x2ffa, + (q15_t)0x6a65, (q15_t)0x2ff2, (q15_t)0x6a6e, (q15_t)0x2fea, (q15_t)0x6a78, (q15_t)0x2fe1, (q15_t)0x6a81, (q15_t)0x2fd9, + (q15_t)0x6a8b, (q15_t)0x2fd0, (q15_t)0x6a94, (q15_t)0x2fc8, (q15_t)0x6a9d, (q15_t)0x2fc0, (q15_t)0x6aa7, (q15_t)0x2fb7, + (q15_t)0x6ab0, (q15_t)0x2faf, (q15_t)0x6ab9, (q15_t)0x2fa7, (q15_t)0x6ac3, (q15_t)0x2f9e, (q15_t)0x6acc, (q15_t)0x2f96, + (q15_t)0x6ad6, (q15_t)0x2f8d, (q15_t)0x6adf, (q15_t)0x2f85, (q15_t)0x6ae8, (q15_t)0x2f7d, (q15_t)0x6af2, (q15_t)0x2f74, + (q15_t)0x6afb, (q15_t)0x2f6c, (q15_t)0x6b04, (q15_t)0x2f63, (q15_t)0x6b0d, (q15_t)0x2f5b, (q15_t)0x6b17, (q15_t)0x2f52, + (q15_t)0x6b20, (q15_t)0x2f4a, (q15_t)0x6b29, (q15_t)0x2f41, (q15_t)0x6b33, (q15_t)0x2f39, (q15_t)0x6b3c, (q15_t)0x2f30, + (q15_t)0x6b45, (q15_t)0x2f28, (q15_t)0x6b4e, (q15_t)0x2f20, (q15_t)0x6b58, (q15_t)0x2f17, (q15_t)0x6b61, (q15_t)0x2f0e, + (q15_t)0x6b6a, (q15_t)0x2f06, (q15_t)0x6b73, (q15_t)0x2efd, (q15_t)0x6b7d, (q15_t)0x2ef5, (q15_t)0x6b86, (q15_t)0x2eec, + (q15_t)0x6b8f, (q15_t)0x2ee4, (q15_t)0x6b98, (q15_t)0x2edb, (q15_t)0x6ba1, (q15_t)0x2ed3, (q15_t)0x6bab, (q15_t)0x2eca, + (q15_t)0x6bb4, (q15_t)0x2ec2, (q15_t)0x6bbd, (q15_t)0x2eb9, (q15_t)0x6bc6, (q15_t)0x2eb0, (q15_t)0x6bcf, (q15_t)0x2ea8, + (q15_t)0x6bd8, (q15_t)0x2e9f, (q15_t)0x6be2, (q15_t)0x2e97, (q15_t)0x6beb, (q15_t)0x2e8e, (q15_t)0x6bf4, (q15_t)0x2e85, + (q15_t)0x6bfd, (q15_t)0x2e7d, (q15_t)0x6c06, (q15_t)0x2e74, (q15_t)0x6c0f, (q15_t)0x2e6b, (q15_t)0x6c18, (q15_t)0x2e63, + (q15_t)0x6c21, (q15_t)0x2e5a, (q15_t)0x6c2b, (q15_t)0x2e51, (q15_t)0x6c34, (q15_t)0x2e49, (q15_t)0x6c3d, (q15_t)0x2e40, + (q15_t)0x6c46, (q15_t)0x2e37, (q15_t)0x6c4f, (q15_t)0x2e2f, (q15_t)0x6c58, (q15_t)0x2e26, (q15_t)0x6c61, (q15_t)0x2e1d, + (q15_t)0x6c6a, (q15_t)0x2e15, (q15_t)0x6c73, (q15_t)0x2e0c, (q15_t)0x6c7c, (q15_t)0x2e03, (q15_t)0x6c85, (q15_t)0x2dfa, + (q15_t)0x6c8e, (q15_t)0x2df2, (q15_t)0x6c97, (q15_t)0x2de9, (q15_t)0x6ca0, (q15_t)0x2de0, (q15_t)0x6ca9, (q15_t)0x2dd7, + (q15_t)0x6cb2, (q15_t)0x2dcf, (q15_t)0x6cbb, (q15_t)0x2dc6, (q15_t)0x6cc4, (q15_t)0x2dbd, (q15_t)0x6ccd, (q15_t)0x2db4, + (q15_t)0x6cd6, (q15_t)0x2dab, (q15_t)0x6cdf, (q15_t)0x2da3, (q15_t)0x6ce8, (q15_t)0x2d9a, (q15_t)0x6cf1, (q15_t)0x2d91, + (q15_t)0x6cfa, (q15_t)0x2d88, (q15_t)0x6d03, (q15_t)0x2d7f, (q15_t)0x6d0c, (q15_t)0x2d76, (q15_t)0x6d15, (q15_t)0x2d6e, + (q15_t)0x6d1e, (q15_t)0x2d65, (q15_t)0x6d27, (q15_t)0x2d5c, (q15_t)0x6d2f, (q15_t)0x2d53, (q15_t)0x6d38, (q15_t)0x2d4a, + (q15_t)0x6d41, (q15_t)0x2d41, (q15_t)0x6d4a, (q15_t)0x2d38, (q15_t)0x6d53, (q15_t)0x2d2f, (q15_t)0x6d5c, (q15_t)0x2d27, + (q15_t)0x6d65, (q15_t)0x2d1e, (q15_t)0x6d6e, (q15_t)0x2d15, (q15_t)0x6d76, (q15_t)0x2d0c, (q15_t)0x6d7f, (q15_t)0x2d03, + (q15_t)0x6d88, (q15_t)0x2cfa, (q15_t)0x6d91, (q15_t)0x2cf1, (q15_t)0x6d9a, (q15_t)0x2ce8, (q15_t)0x6da3, (q15_t)0x2cdf, + (q15_t)0x6dab, (q15_t)0x2cd6, (q15_t)0x6db4, (q15_t)0x2ccd, (q15_t)0x6dbd, (q15_t)0x2cc4, (q15_t)0x6dc6, (q15_t)0x2cbb, + (q15_t)0x6dcf, (q15_t)0x2cb2, (q15_t)0x6dd7, (q15_t)0x2ca9, (q15_t)0x6de0, (q15_t)0x2ca0, (q15_t)0x6de9, (q15_t)0x2c97, + (q15_t)0x6df2, (q15_t)0x2c8e, (q15_t)0x6dfa, (q15_t)0x2c85, (q15_t)0x6e03, (q15_t)0x2c7c, (q15_t)0x6e0c, (q15_t)0x2c73, + (q15_t)0x6e15, (q15_t)0x2c6a, (q15_t)0x6e1d, (q15_t)0x2c61, (q15_t)0x6e26, (q15_t)0x2c58, (q15_t)0x6e2f, (q15_t)0x2c4f, + (q15_t)0x6e37, (q15_t)0x2c46, (q15_t)0x6e40, (q15_t)0x2c3d, (q15_t)0x6e49, (q15_t)0x2c34, (q15_t)0x6e51, (q15_t)0x2c2b, + (q15_t)0x6e5a, (q15_t)0x2c21, (q15_t)0x6e63, (q15_t)0x2c18, (q15_t)0x6e6b, (q15_t)0x2c0f, (q15_t)0x6e74, (q15_t)0x2c06, + (q15_t)0x6e7d, (q15_t)0x2bfd, (q15_t)0x6e85, (q15_t)0x2bf4, (q15_t)0x6e8e, (q15_t)0x2beb, (q15_t)0x6e97, (q15_t)0x2be2, + (q15_t)0x6e9f, (q15_t)0x2bd8, (q15_t)0x6ea8, (q15_t)0x2bcf, (q15_t)0x6eb0, (q15_t)0x2bc6, (q15_t)0x6eb9, (q15_t)0x2bbd, + (q15_t)0x6ec2, (q15_t)0x2bb4, (q15_t)0x6eca, (q15_t)0x2bab, (q15_t)0x6ed3, (q15_t)0x2ba1, (q15_t)0x6edb, (q15_t)0x2b98, + (q15_t)0x6ee4, (q15_t)0x2b8f, (q15_t)0x6eec, (q15_t)0x2b86, (q15_t)0x6ef5, (q15_t)0x2b7d, (q15_t)0x6efd, (q15_t)0x2b73, + (q15_t)0x6f06, (q15_t)0x2b6a, (q15_t)0x6f0e, (q15_t)0x2b61, (q15_t)0x6f17, (q15_t)0x2b58, (q15_t)0x6f20, (q15_t)0x2b4e, + (q15_t)0x6f28, (q15_t)0x2b45, (q15_t)0x6f30, (q15_t)0x2b3c, (q15_t)0x6f39, (q15_t)0x2b33, (q15_t)0x6f41, (q15_t)0x2b29, + (q15_t)0x6f4a, (q15_t)0x2b20, (q15_t)0x6f52, (q15_t)0x2b17, (q15_t)0x6f5b, (q15_t)0x2b0d, (q15_t)0x6f63, (q15_t)0x2b04, + (q15_t)0x6f6c, (q15_t)0x2afb, (q15_t)0x6f74, (q15_t)0x2af2, (q15_t)0x6f7d, (q15_t)0x2ae8, (q15_t)0x6f85, (q15_t)0x2adf, + (q15_t)0x6f8d, (q15_t)0x2ad6, (q15_t)0x6f96, (q15_t)0x2acc, (q15_t)0x6f9e, (q15_t)0x2ac3, (q15_t)0x6fa7, (q15_t)0x2ab9, + (q15_t)0x6faf, (q15_t)0x2ab0, (q15_t)0x6fb7, (q15_t)0x2aa7, (q15_t)0x6fc0, (q15_t)0x2a9d, (q15_t)0x6fc8, (q15_t)0x2a94, + (q15_t)0x6fd0, (q15_t)0x2a8b, (q15_t)0x6fd9, (q15_t)0x2a81, (q15_t)0x6fe1, (q15_t)0x2a78, (q15_t)0x6fea, (q15_t)0x2a6e, + (q15_t)0x6ff2, (q15_t)0x2a65, (q15_t)0x6ffa, (q15_t)0x2a5c, (q15_t)0x7002, (q15_t)0x2a52, (q15_t)0x700b, (q15_t)0x2a49, + (q15_t)0x7013, (q15_t)0x2a3f, (q15_t)0x701b, (q15_t)0x2a36, (q15_t)0x7024, (q15_t)0x2a2c, (q15_t)0x702c, (q15_t)0x2a23, + (q15_t)0x7034, (q15_t)0x2a1a, (q15_t)0x703c, (q15_t)0x2a10, (q15_t)0x7045, (q15_t)0x2a07, (q15_t)0x704d, (q15_t)0x29fd, + (q15_t)0x7055, (q15_t)0x29f4, (q15_t)0x705d, (q15_t)0x29ea, (q15_t)0x7066, (q15_t)0x29e1, (q15_t)0x706e, (q15_t)0x29d7, + (q15_t)0x7076, (q15_t)0x29ce, (q15_t)0x707e, (q15_t)0x29c4, (q15_t)0x7087, (q15_t)0x29bb, (q15_t)0x708f, (q15_t)0x29b1, + (q15_t)0x7097, (q15_t)0x29a7, (q15_t)0x709f, (q15_t)0x299e, (q15_t)0x70a7, (q15_t)0x2994, (q15_t)0x70af, (q15_t)0x298b, + (q15_t)0x70b8, (q15_t)0x2981, (q15_t)0x70c0, (q15_t)0x2978, (q15_t)0x70c8, (q15_t)0x296e, (q15_t)0x70d0, (q15_t)0x2965, + (q15_t)0x70d8, (q15_t)0x295b, (q15_t)0x70e0, (q15_t)0x2951, (q15_t)0x70e8, (q15_t)0x2948, (q15_t)0x70f0, (q15_t)0x293e, + (q15_t)0x70f9, (q15_t)0x2935, (q15_t)0x7101, (q15_t)0x292b, (q15_t)0x7109, (q15_t)0x2921, (q15_t)0x7111, (q15_t)0x2918, + (q15_t)0x7119, (q15_t)0x290e, (q15_t)0x7121, (q15_t)0x2904, (q15_t)0x7129, (q15_t)0x28fb, (q15_t)0x7131, (q15_t)0x28f1, + (q15_t)0x7139, (q15_t)0x28e7, (q15_t)0x7141, (q15_t)0x28de, (q15_t)0x7149, (q15_t)0x28d4, (q15_t)0x7151, (q15_t)0x28ca, + (q15_t)0x7159, (q15_t)0x28c1, (q15_t)0x7161, (q15_t)0x28b7, (q15_t)0x7169, (q15_t)0x28ad, (q15_t)0x7171, (q15_t)0x28a4, + (q15_t)0x7179, (q15_t)0x289a, (q15_t)0x7181, (q15_t)0x2890, (q15_t)0x7189, (q15_t)0x2886, (q15_t)0x7191, (q15_t)0x287d, + (q15_t)0x7199, (q15_t)0x2873, (q15_t)0x71a1, (q15_t)0x2869, (q15_t)0x71a9, (q15_t)0x2860, (q15_t)0x71b1, (q15_t)0x2856, + (q15_t)0x71b9, (q15_t)0x284c, (q15_t)0x71c0, (q15_t)0x2842, (q15_t)0x71c8, (q15_t)0x2838, (q15_t)0x71d0, (q15_t)0x282f, + (q15_t)0x71d8, (q15_t)0x2825, (q15_t)0x71e0, (q15_t)0x281b, (q15_t)0x71e8, (q15_t)0x2811, (q15_t)0x71f0, (q15_t)0x2808, + (q15_t)0x71f8, (q15_t)0x27fe, (q15_t)0x71ff, (q15_t)0x27f4, (q15_t)0x7207, (q15_t)0x27ea, (q15_t)0x720f, (q15_t)0x27e0, + (q15_t)0x7217, (q15_t)0x27d6, (q15_t)0x721f, (q15_t)0x27cd, (q15_t)0x7227, (q15_t)0x27c3, (q15_t)0x722e, (q15_t)0x27b9, + (q15_t)0x7236, (q15_t)0x27af, (q15_t)0x723e, (q15_t)0x27a5, (q15_t)0x7246, (q15_t)0x279b, (q15_t)0x724e, (q15_t)0x2791, + (q15_t)0x7255, (q15_t)0x2788, (q15_t)0x725d, (q15_t)0x277e, (q15_t)0x7265, (q15_t)0x2774, (q15_t)0x726d, (q15_t)0x276a, + (q15_t)0x7274, (q15_t)0x2760, (q15_t)0x727c, (q15_t)0x2756, (q15_t)0x7284, (q15_t)0x274c, (q15_t)0x728b, (q15_t)0x2742, + (q15_t)0x7293, (q15_t)0x2738, (q15_t)0x729b, (q15_t)0x272e, (q15_t)0x72a3, (q15_t)0x2724, (q15_t)0x72aa, (q15_t)0x271a, + (q15_t)0x72b2, (q15_t)0x2711, (q15_t)0x72ba, (q15_t)0x2707, (q15_t)0x72c1, (q15_t)0x26fd, (q15_t)0x72c9, (q15_t)0x26f3, + (q15_t)0x72d0, (q15_t)0x26e9, (q15_t)0x72d8, (q15_t)0x26df, (q15_t)0x72e0, (q15_t)0x26d5, (q15_t)0x72e7, (q15_t)0x26cb, + (q15_t)0x72ef, (q15_t)0x26c1, (q15_t)0x72f7, (q15_t)0x26b7, (q15_t)0x72fe, (q15_t)0x26ad, (q15_t)0x7306, (q15_t)0x26a3, + (q15_t)0x730d, (q15_t)0x2699, (q15_t)0x7315, (q15_t)0x268f, (q15_t)0x731d, (q15_t)0x2685, (q15_t)0x7324, (q15_t)0x267b, + (q15_t)0x732c, (q15_t)0x2671, (q15_t)0x7333, (q15_t)0x2666, (q15_t)0x733b, (q15_t)0x265c, (q15_t)0x7342, (q15_t)0x2652, + (q15_t)0x734a, (q15_t)0x2648, (q15_t)0x7351, (q15_t)0x263e, (q15_t)0x7359, (q15_t)0x2634, (q15_t)0x7360, (q15_t)0x262a, + (q15_t)0x7368, (q15_t)0x2620, (q15_t)0x736f, (q15_t)0x2616, (q15_t)0x7377, (q15_t)0x260c, (q15_t)0x737e, (q15_t)0x2602, + (q15_t)0x7386, (q15_t)0x25f8, (q15_t)0x738d, (q15_t)0x25ed, (q15_t)0x7395, (q15_t)0x25e3, (q15_t)0x739c, (q15_t)0x25d9, + (q15_t)0x73a3, (q15_t)0x25cf, (q15_t)0x73ab, (q15_t)0x25c5, (q15_t)0x73b2, (q15_t)0x25bb, (q15_t)0x73ba, (q15_t)0x25b1, + (q15_t)0x73c1, (q15_t)0x25a6, (q15_t)0x73c8, (q15_t)0x259c, (q15_t)0x73d0, (q15_t)0x2592, (q15_t)0x73d7, (q15_t)0x2588, + (q15_t)0x73df, (q15_t)0x257e, (q15_t)0x73e6, (q15_t)0x2574, (q15_t)0x73ed, (q15_t)0x2569, (q15_t)0x73f5, (q15_t)0x255f, + (q15_t)0x73fc, (q15_t)0x2555, (q15_t)0x7403, (q15_t)0x254b, (q15_t)0x740b, (q15_t)0x2541, (q15_t)0x7412, (q15_t)0x2536, + (q15_t)0x7419, (q15_t)0x252c, (q15_t)0x7420, (q15_t)0x2522, (q15_t)0x7428, (q15_t)0x2518, (q15_t)0x742f, (q15_t)0x250d, + (q15_t)0x7436, (q15_t)0x2503, (q15_t)0x743e, (q15_t)0x24f9, (q15_t)0x7445, (q15_t)0x24ef, (q15_t)0x744c, (q15_t)0x24e4, + (q15_t)0x7453, (q15_t)0x24da, (q15_t)0x745b, (q15_t)0x24d0, (q15_t)0x7462, (q15_t)0x24c5, (q15_t)0x7469, (q15_t)0x24bb, + (q15_t)0x7470, (q15_t)0x24b1, (q15_t)0x7477, (q15_t)0x24a7, (q15_t)0x747f, (q15_t)0x249c, (q15_t)0x7486, (q15_t)0x2492, + (q15_t)0x748d, (q15_t)0x2488, (q15_t)0x7494, (q15_t)0x247d, (q15_t)0x749b, (q15_t)0x2473, (q15_t)0x74a2, (q15_t)0x2469, + (q15_t)0x74aa, (q15_t)0x245e, (q15_t)0x74b1, (q15_t)0x2454, (q15_t)0x74b8, (q15_t)0x244a, (q15_t)0x74bf, (q15_t)0x243f, + (q15_t)0x74c6, (q15_t)0x2435, (q15_t)0x74cd, (q15_t)0x242b, (q15_t)0x74d4, (q15_t)0x2420, (q15_t)0x74db, (q15_t)0x2416, + (q15_t)0x74e2, (q15_t)0x240b, (q15_t)0x74ea, (q15_t)0x2401, (q15_t)0x74f1, (q15_t)0x23f7, (q15_t)0x74f8, (q15_t)0x23ec, + (q15_t)0x74ff, (q15_t)0x23e2, (q15_t)0x7506, (q15_t)0x23d7, (q15_t)0x750d, (q15_t)0x23cd, (q15_t)0x7514, (q15_t)0x23c3, + (q15_t)0x751b, (q15_t)0x23b8, (q15_t)0x7522, (q15_t)0x23ae, (q15_t)0x7529, (q15_t)0x23a3, (q15_t)0x7530, (q15_t)0x2399, + (q15_t)0x7537, (q15_t)0x238e, (q15_t)0x753e, (q15_t)0x2384, (q15_t)0x7545, (q15_t)0x237a, (q15_t)0x754c, (q15_t)0x236f, + (q15_t)0x7553, (q15_t)0x2365, (q15_t)0x755a, (q15_t)0x235a, (q15_t)0x7561, (q15_t)0x2350, (q15_t)0x7567, (q15_t)0x2345, + (q15_t)0x756e, (q15_t)0x233b, (q15_t)0x7575, (q15_t)0x2330, (q15_t)0x757c, (q15_t)0x2326, (q15_t)0x7583, (q15_t)0x231b, + (q15_t)0x758a, (q15_t)0x2311, (q15_t)0x7591, (q15_t)0x2306, (q15_t)0x7598, (q15_t)0x22fc, (q15_t)0x759f, (q15_t)0x22f1, + (q15_t)0x75a5, (q15_t)0x22e7, (q15_t)0x75ac, (q15_t)0x22dc, (q15_t)0x75b3, (q15_t)0x22d2, (q15_t)0x75ba, (q15_t)0x22c7, + (q15_t)0x75c1, (q15_t)0x22bc, (q15_t)0x75c8, (q15_t)0x22b2, (q15_t)0x75ce, (q15_t)0x22a7, (q15_t)0x75d5, (q15_t)0x229d, + (q15_t)0x75dc, (q15_t)0x2292, (q15_t)0x75e3, (q15_t)0x2288, (q15_t)0x75ea, (q15_t)0x227d, (q15_t)0x75f0, (q15_t)0x2272, + (q15_t)0x75f7, (q15_t)0x2268, (q15_t)0x75fe, (q15_t)0x225d, (q15_t)0x7605, (q15_t)0x2253, (q15_t)0x760b, (q15_t)0x2248, + (q15_t)0x7612, (q15_t)0x223d, (q15_t)0x7619, (q15_t)0x2233, (q15_t)0x7620, (q15_t)0x2228, (q15_t)0x7626, (q15_t)0x221e, + (q15_t)0x762d, (q15_t)0x2213, (q15_t)0x7634, (q15_t)0x2208, (q15_t)0x763a, (q15_t)0x21fe, (q15_t)0x7641, (q15_t)0x21f3, + (q15_t)0x7648, (q15_t)0x21e8, (q15_t)0x764e, (q15_t)0x21de, (q15_t)0x7655, (q15_t)0x21d3, (q15_t)0x765c, (q15_t)0x21c8, + (q15_t)0x7662, (q15_t)0x21be, (q15_t)0x7669, (q15_t)0x21b3, (q15_t)0x766f, (q15_t)0x21a8, (q15_t)0x7676, (q15_t)0x219e, + (q15_t)0x767d, (q15_t)0x2193, (q15_t)0x7683, (q15_t)0x2188, (q15_t)0x768a, (q15_t)0x217d, (q15_t)0x7690, (q15_t)0x2173, + (q15_t)0x7697, (q15_t)0x2168, (q15_t)0x769d, (q15_t)0x215d, (q15_t)0x76a4, (q15_t)0x2153, (q15_t)0x76ab, (q15_t)0x2148, + (q15_t)0x76b1, (q15_t)0x213d, (q15_t)0x76b8, (q15_t)0x2132, (q15_t)0x76be, (q15_t)0x2128, (q15_t)0x76c5, (q15_t)0x211d, + (q15_t)0x76cb, (q15_t)0x2112, (q15_t)0x76d2, (q15_t)0x2107, (q15_t)0x76d8, (q15_t)0x20fd, (q15_t)0x76df, (q15_t)0x20f2, + (q15_t)0x76e5, (q15_t)0x20e7, (q15_t)0x76eb, (q15_t)0x20dc, (q15_t)0x76f2, (q15_t)0x20d1, (q15_t)0x76f8, (q15_t)0x20c7, + (q15_t)0x76ff, (q15_t)0x20bc, (q15_t)0x7705, (q15_t)0x20b1, (q15_t)0x770c, (q15_t)0x20a6, (q15_t)0x7712, (q15_t)0x209b, + (q15_t)0x7718, (q15_t)0x2091, (q15_t)0x771f, (q15_t)0x2086, (q15_t)0x7725, (q15_t)0x207b, (q15_t)0x772c, (q15_t)0x2070, + (q15_t)0x7732, (q15_t)0x2065, (q15_t)0x7738, (q15_t)0x205b, (q15_t)0x773f, (q15_t)0x2050, (q15_t)0x7745, (q15_t)0x2045, + (q15_t)0x774b, (q15_t)0x203a, (q15_t)0x7752, (q15_t)0x202f, (q15_t)0x7758, (q15_t)0x2024, (q15_t)0x775e, (q15_t)0x2019, + (q15_t)0x7765, (q15_t)0x200f, (q15_t)0x776b, (q15_t)0x2004, (q15_t)0x7771, (q15_t)0x1ff9, (q15_t)0x7777, (q15_t)0x1fee, + (q15_t)0x777e, (q15_t)0x1fe3, (q15_t)0x7784, (q15_t)0x1fd8, (q15_t)0x778a, (q15_t)0x1fcd, (q15_t)0x7790, (q15_t)0x1fc2, + (q15_t)0x7797, (q15_t)0x1fb7, (q15_t)0x779d, (q15_t)0x1fac, (q15_t)0x77a3, (q15_t)0x1fa2, (q15_t)0x77a9, (q15_t)0x1f97, + (q15_t)0x77b0, (q15_t)0x1f8c, (q15_t)0x77b6, (q15_t)0x1f81, (q15_t)0x77bc, (q15_t)0x1f76, (q15_t)0x77c2, (q15_t)0x1f6b, + (q15_t)0x77c8, (q15_t)0x1f60, (q15_t)0x77ce, (q15_t)0x1f55, (q15_t)0x77d5, (q15_t)0x1f4a, (q15_t)0x77db, (q15_t)0x1f3f, + (q15_t)0x77e1, (q15_t)0x1f34, (q15_t)0x77e7, (q15_t)0x1f29, (q15_t)0x77ed, (q15_t)0x1f1e, (q15_t)0x77f3, (q15_t)0x1f13, + (q15_t)0x77f9, (q15_t)0x1f08, (q15_t)0x77ff, (q15_t)0x1efd, (q15_t)0x7805, (q15_t)0x1ef2, (q15_t)0x780b, (q15_t)0x1ee7, + (q15_t)0x7812, (q15_t)0x1edc, (q15_t)0x7818, (q15_t)0x1ed1, (q15_t)0x781e, (q15_t)0x1ec6, (q15_t)0x7824, (q15_t)0x1ebb, + (q15_t)0x782a, (q15_t)0x1eb0, (q15_t)0x7830, (q15_t)0x1ea5, (q15_t)0x7836, (q15_t)0x1e9a, (q15_t)0x783c, (q15_t)0x1e8f, + (q15_t)0x7842, (q15_t)0x1e84, (q15_t)0x7848, (q15_t)0x1e79, (q15_t)0x784e, (q15_t)0x1e6e, (q15_t)0x7854, (q15_t)0x1e63, + (q15_t)0x785a, (q15_t)0x1e58, (q15_t)0x7860, (q15_t)0x1e4d, (q15_t)0x7866, (q15_t)0x1e42, (q15_t)0x786b, (q15_t)0x1e36, + (q15_t)0x7871, (q15_t)0x1e2b, (q15_t)0x7877, (q15_t)0x1e20, (q15_t)0x787d, (q15_t)0x1e15, (q15_t)0x7883, (q15_t)0x1e0a, + (q15_t)0x7889, (q15_t)0x1dff, (q15_t)0x788f, (q15_t)0x1df4, (q15_t)0x7895, (q15_t)0x1de9, (q15_t)0x789b, (q15_t)0x1dde, + (q15_t)0x78a1, (q15_t)0x1dd3, (q15_t)0x78a6, (q15_t)0x1dc7, (q15_t)0x78ac, (q15_t)0x1dbc, (q15_t)0x78b2, (q15_t)0x1db1, + (q15_t)0x78b8, (q15_t)0x1da6, (q15_t)0x78be, (q15_t)0x1d9b, (q15_t)0x78c3, (q15_t)0x1d90, (q15_t)0x78c9, (q15_t)0x1d85, + (q15_t)0x78cf, (q15_t)0x1d79, (q15_t)0x78d5, (q15_t)0x1d6e, (q15_t)0x78db, (q15_t)0x1d63, (q15_t)0x78e0, (q15_t)0x1d58, + (q15_t)0x78e6, (q15_t)0x1d4d, (q15_t)0x78ec, (q15_t)0x1d42, (q15_t)0x78f2, (q15_t)0x1d36, (q15_t)0x78f7, (q15_t)0x1d2b, + (q15_t)0x78fd, (q15_t)0x1d20, (q15_t)0x7903, (q15_t)0x1d15, (q15_t)0x7909, (q15_t)0x1d0a, (q15_t)0x790e, (q15_t)0x1cff, + (q15_t)0x7914, (q15_t)0x1cf3, (q15_t)0x791a, (q15_t)0x1ce8, (q15_t)0x791f, (q15_t)0x1cdd, (q15_t)0x7925, (q15_t)0x1cd2, + (q15_t)0x792b, (q15_t)0x1cc6, (q15_t)0x7930, (q15_t)0x1cbb, (q15_t)0x7936, (q15_t)0x1cb0, (q15_t)0x793b, (q15_t)0x1ca5, + (q15_t)0x7941, (q15_t)0x1c99, (q15_t)0x7947, (q15_t)0x1c8e, (q15_t)0x794c, (q15_t)0x1c83, (q15_t)0x7952, (q15_t)0x1c78, + (q15_t)0x7958, (q15_t)0x1c6c, (q15_t)0x795d, (q15_t)0x1c61, (q15_t)0x7963, (q15_t)0x1c56, (q15_t)0x7968, (q15_t)0x1c4b, + (q15_t)0x796e, (q15_t)0x1c3f, (q15_t)0x7973, (q15_t)0x1c34, (q15_t)0x7979, (q15_t)0x1c29, (q15_t)0x797e, (q15_t)0x1c1e, + (q15_t)0x7984, (q15_t)0x1c12, (q15_t)0x7989, (q15_t)0x1c07, (q15_t)0x798f, (q15_t)0x1bfc, (q15_t)0x7994, (q15_t)0x1bf0, + (q15_t)0x799a, (q15_t)0x1be5, (q15_t)0x799f, (q15_t)0x1bda, (q15_t)0x79a5, (q15_t)0x1bce, (q15_t)0x79aa, (q15_t)0x1bc3, + (q15_t)0x79b0, (q15_t)0x1bb8, (q15_t)0x79b5, (q15_t)0x1bac, (q15_t)0x79bb, (q15_t)0x1ba1, (q15_t)0x79c0, (q15_t)0x1b96, + (q15_t)0x79c5, (q15_t)0x1b8a, (q15_t)0x79cb, (q15_t)0x1b7f, (q15_t)0x79d0, (q15_t)0x1b74, (q15_t)0x79d6, (q15_t)0x1b68, + (q15_t)0x79db, (q15_t)0x1b5d, (q15_t)0x79e0, (q15_t)0x1b52, (q15_t)0x79e6, (q15_t)0x1b46, (q15_t)0x79eb, (q15_t)0x1b3b, + (q15_t)0x79f0, (q15_t)0x1b30, (q15_t)0x79f6, (q15_t)0x1b24, (q15_t)0x79fb, (q15_t)0x1b19, (q15_t)0x7a00, (q15_t)0x1b0d, + (q15_t)0x7a06, (q15_t)0x1b02, (q15_t)0x7a0b, (q15_t)0x1af7, (q15_t)0x7a10, (q15_t)0x1aeb, (q15_t)0x7a16, (q15_t)0x1ae0, + (q15_t)0x7a1b, (q15_t)0x1ad4, (q15_t)0x7a20, (q15_t)0x1ac9, (q15_t)0x7a25, (q15_t)0x1abe, (q15_t)0x7a2b, (q15_t)0x1ab2, + (q15_t)0x7a30, (q15_t)0x1aa7, (q15_t)0x7a35, (q15_t)0x1a9b, (q15_t)0x7a3a, (q15_t)0x1a90, (q15_t)0x7a3f, (q15_t)0x1a84, + (q15_t)0x7a45, (q15_t)0x1a79, (q15_t)0x7a4a, (q15_t)0x1a6e, (q15_t)0x7a4f, (q15_t)0x1a62, (q15_t)0x7a54, (q15_t)0x1a57, + (q15_t)0x7a59, (q15_t)0x1a4b, (q15_t)0x7a5f, (q15_t)0x1a40, (q15_t)0x7a64, (q15_t)0x1a34, (q15_t)0x7a69, (q15_t)0x1a29, + (q15_t)0x7a6e, (q15_t)0x1a1d, (q15_t)0x7a73, (q15_t)0x1a12, (q15_t)0x7a78, (q15_t)0x1a06, (q15_t)0x7a7d, (q15_t)0x19fb, + (q15_t)0x7a82, (q15_t)0x19ef, (q15_t)0x7a88, (q15_t)0x19e4, (q15_t)0x7a8d, (q15_t)0x19d8, (q15_t)0x7a92, (q15_t)0x19cd, + (q15_t)0x7a97, (q15_t)0x19c1, (q15_t)0x7a9c, (q15_t)0x19b6, (q15_t)0x7aa1, (q15_t)0x19aa, (q15_t)0x7aa6, (q15_t)0x199f, + (q15_t)0x7aab, (q15_t)0x1993, (q15_t)0x7ab0, (q15_t)0x1988, (q15_t)0x7ab5, (q15_t)0x197c, (q15_t)0x7aba, (q15_t)0x1971, + (q15_t)0x7abf, (q15_t)0x1965, (q15_t)0x7ac4, (q15_t)0x195a, (q15_t)0x7ac9, (q15_t)0x194e, (q15_t)0x7ace, (q15_t)0x1943, + (q15_t)0x7ad3, (q15_t)0x1937, (q15_t)0x7ad8, (q15_t)0x192c, (q15_t)0x7add, (q15_t)0x1920, (q15_t)0x7ae2, (q15_t)0x1914, + (q15_t)0x7ae6, (q15_t)0x1909, (q15_t)0x7aeb, (q15_t)0x18fd, (q15_t)0x7af0, (q15_t)0x18f2, (q15_t)0x7af5, (q15_t)0x18e6, + (q15_t)0x7afa, (q15_t)0x18db, (q15_t)0x7aff, (q15_t)0x18cf, (q15_t)0x7b04, (q15_t)0x18c3, (q15_t)0x7b09, (q15_t)0x18b8, + (q15_t)0x7b0e, (q15_t)0x18ac, (q15_t)0x7b12, (q15_t)0x18a1, (q15_t)0x7b17, (q15_t)0x1895, (q15_t)0x7b1c, (q15_t)0x1889, + (q15_t)0x7b21, (q15_t)0x187e, (q15_t)0x7b26, (q15_t)0x1872, (q15_t)0x7b2a, (q15_t)0x1867, (q15_t)0x7b2f, (q15_t)0x185b, + (q15_t)0x7b34, (q15_t)0x184f, (q15_t)0x7b39, (q15_t)0x1844, (q15_t)0x7b3e, (q15_t)0x1838, (q15_t)0x7b42, (q15_t)0x182d, + (q15_t)0x7b47, (q15_t)0x1821, (q15_t)0x7b4c, (q15_t)0x1815, (q15_t)0x7b50, (q15_t)0x180a, (q15_t)0x7b55, (q15_t)0x17fe, + (q15_t)0x7b5a, (q15_t)0x17f2, (q15_t)0x7b5f, (q15_t)0x17e7, (q15_t)0x7b63, (q15_t)0x17db, (q15_t)0x7b68, (q15_t)0x17cf, + (q15_t)0x7b6d, (q15_t)0x17c4, (q15_t)0x7b71, (q15_t)0x17b8, (q15_t)0x7b76, (q15_t)0x17ac, (q15_t)0x7b7b, (q15_t)0x17a1, + (q15_t)0x7b7f, (q15_t)0x1795, (q15_t)0x7b84, (q15_t)0x1789, (q15_t)0x7b88, (q15_t)0x177e, (q15_t)0x7b8d, (q15_t)0x1772, + (q15_t)0x7b92, (q15_t)0x1766, (q15_t)0x7b96, (q15_t)0x175b, (q15_t)0x7b9b, (q15_t)0x174f, (q15_t)0x7b9f, (q15_t)0x1743, + (q15_t)0x7ba4, (q15_t)0x1737, (q15_t)0x7ba9, (q15_t)0x172c, (q15_t)0x7bad, (q15_t)0x1720, (q15_t)0x7bb2, (q15_t)0x1714, + (q15_t)0x7bb6, (q15_t)0x1709, (q15_t)0x7bbb, (q15_t)0x16fd, (q15_t)0x7bbf, (q15_t)0x16f1, (q15_t)0x7bc4, (q15_t)0x16e5, + (q15_t)0x7bc8, (q15_t)0x16da, (q15_t)0x7bcd, (q15_t)0x16ce, (q15_t)0x7bd1, (q15_t)0x16c2, (q15_t)0x7bd6, (q15_t)0x16b6, + (q15_t)0x7bda, (q15_t)0x16ab, (q15_t)0x7bde, (q15_t)0x169f, (q15_t)0x7be3, (q15_t)0x1693, (q15_t)0x7be7, (q15_t)0x1687, + (q15_t)0x7bec, (q15_t)0x167c, (q15_t)0x7bf0, (q15_t)0x1670, (q15_t)0x7bf5, (q15_t)0x1664, (q15_t)0x7bf9, (q15_t)0x1658, + (q15_t)0x7bfd, (q15_t)0x164c, (q15_t)0x7c02, (q15_t)0x1641, (q15_t)0x7c06, (q15_t)0x1635, (q15_t)0x7c0a, (q15_t)0x1629, + (q15_t)0x7c0f, (q15_t)0x161d, (q15_t)0x7c13, (q15_t)0x1612, (q15_t)0x7c17, (q15_t)0x1606, (q15_t)0x7c1c, (q15_t)0x15fa, + (q15_t)0x7c20, (q15_t)0x15ee, (q15_t)0x7c24, (q15_t)0x15e2, (q15_t)0x7c29, (q15_t)0x15d7, (q15_t)0x7c2d, (q15_t)0x15cb, + (q15_t)0x7c31, (q15_t)0x15bf, (q15_t)0x7c36, (q15_t)0x15b3, (q15_t)0x7c3a, (q15_t)0x15a7, (q15_t)0x7c3e, (q15_t)0x159b, + (q15_t)0x7c42, (q15_t)0x1590, (q15_t)0x7c46, (q15_t)0x1584, (q15_t)0x7c4b, (q15_t)0x1578, (q15_t)0x7c4f, (q15_t)0x156c, + (q15_t)0x7c53, (q15_t)0x1560, (q15_t)0x7c57, (q15_t)0x1554, (q15_t)0x7c5b, (q15_t)0x1549, (q15_t)0x7c60, (q15_t)0x153d, + (q15_t)0x7c64, (q15_t)0x1531, (q15_t)0x7c68, (q15_t)0x1525, (q15_t)0x7c6c, (q15_t)0x1519, (q15_t)0x7c70, (q15_t)0x150d, + (q15_t)0x7c74, (q15_t)0x1501, (q15_t)0x7c79, (q15_t)0x14f6, (q15_t)0x7c7d, (q15_t)0x14ea, (q15_t)0x7c81, (q15_t)0x14de, + (q15_t)0x7c85, (q15_t)0x14d2, (q15_t)0x7c89, (q15_t)0x14c6, (q15_t)0x7c8d, (q15_t)0x14ba, (q15_t)0x7c91, (q15_t)0x14ae, + (q15_t)0x7c95, (q15_t)0x14a2, (q15_t)0x7c99, (q15_t)0x1496, (q15_t)0x7c9d, (q15_t)0x148b, (q15_t)0x7ca1, (q15_t)0x147f, + (q15_t)0x7ca5, (q15_t)0x1473, (q15_t)0x7ca9, (q15_t)0x1467, (q15_t)0x7cad, (q15_t)0x145b, (q15_t)0x7cb1, (q15_t)0x144f, + (q15_t)0x7cb5, (q15_t)0x1443, (q15_t)0x7cb9, (q15_t)0x1437, (q15_t)0x7cbd, (q15_t)0x142b, (q15_t)0x7cc1, (q15_t)0x141f, + (q15_t)0x7cc5, (q15_t)0x1413, (q15_t)0x7cc9, (q15_t)0x1407, (q15_t)0x7ccd, (q15_t)0x13fb, (q15_t)0x7cd1, (q15_t)0x13f0, + (q15_t)0x7cd5, (q15_t)0x13e4, (q15_t)0x7cd9, (q15_t)0x13d8, (q15_t)0x7cdd, (q15_t)0x13cc, (q15_t)0x7ce0, (q15_t)0x13c0, + (q15_t)0x7ce4, (q15_t)0x13b4, (q15_t)0x7ce8, (q15_t)0x13a8, (q15_t)0x7cec, (q15_t)0x139c, (q15_t)0x7cf0, (q15_t)0x1390, + (q15_t)0x7cf4, (q15_t)0x1384, (q15_t)0x7cf8, (q15_t)0x1378, (q15_t)0x7cfb, (q15_t)0x136c, (q15_t)0x7cff, (q15_t)0x1360, + (q15_t)0x7d03, (q15_t)0x1354, (q15_t)0x7d07, (q15_t)0x1348, (q15_t)0x7d0b, (q15_t)0x133c, (q15_t)0x7d0e, (q15_t)0x1330, + (q15_t)0x7d12, (q15_t)0x1324, (q15_t)0x7d16, (q15_t)0x1318, (q15_t)0x7d1a, (q15_t)0x130c, (q15_t)0x7d1d, (q15_t)0x1300, + (q15_t)0x7d21, (q15_t)0x12f4, (q15_t)0x7d25, (q15_t)0x12e8, (q15_t)0x7d28, (q15_t)0x12dc, (q15_t)0x7d2c, (q15_t)0x12d0, + (q15_t)0x7d30, (q15_t)0x12c4, (q15_t)0x7d34, (q15_t)0x12b8, (q15_t)0x7d37, (q15_t)0x12ac, (q15_t)0x7d3b, (q15_t)0x12a0, + (q15_t)0x7d3f, (q15_t)0x1294, (q15_t)0x7d42, (q15_t)0x1288, (q15_t)0x7d46, (q15_t)0x127c, (q15_t)0x7d49, (q15_t)0x1270, + (q15_t)0x7d4d, (q15_t)0x1264, (q15_t)0x7d51, (q15_t)0x1258, (q15_t)0x7d54, (q15_t)0x124c, (q15_t)0x7d58, (q15_t)0x1240, + (q15_t)0x7d5b, (q15_t)0x1234, (q15_t)0x7d5f, (q15_t)0x1228, (q15_t)0x7d63, (q15_t)0x121c, (q15_t)0x7d66, (q15_t)0x1210, + (q15_t)0x7d6a, (q15_t)0x1204, (q15_t)0x7d6d, (q15_t)0x11f7, (q15_t)0x7d71, (q15_t)0x11eb, (q15_t)0x7d74, (q15_t)0x11df, + (q15_t)0x7d78, (q15_t)0x11d3, (q15_t)0x7d7b, (q15_t)0x11c7, (q15_t)0x7d7f, (q15_t)0x11bb, (q15_t)0x7d82, (q15_t)0x11af, + (q15_t)0x7d86, (q15_t)0x11a3, (q15_t)0x7d89, (q15_t)0x1197, (q15_t)0x7d8d, (q15_t)0x118b, (q15_t)0x7d90, (q15_t)0x117f, + (q15_t)0x7d93, (q15_t)0x1173, (q15_t)0x7d97, (q15_t)0x1167, (q15_t)0x7d9a, (q15_t)0x115a, (q15_t)0x7d9e, (q15_t)0x114e, + (q15_t)0x7da1, (q15_t)0x1142, (q15_t)0x7da4, (q15_t)0x1136, (q15_t)0x7da8, (q15_t)0x112a, (q15_t)0x7dab, (q15_t)0x111e, + (q15_t)0x7daf, (q15_t)0x1112, (q15_t)0x7db2, (q15_t)0x1106, (q15_t)0x7db5, (q15_t)0x10fa, (q15_t)0x7db9, (q15_t)0x10ed, + (q15_t)0x7dbc, (q15_t)0x10e1, (q15_t)0x7dbf, (q15_t)0x10d5, (q15_t)0x7dc2, (q15_t)0x10c9, (q15_t)0x7dc6, (q15_t)0x10bd, + (q15_t)0x7dc9, (q15_t)0x10b1, (q15_t)0x7dcc, (q15_t)0x10a5, (q15_t)0x7dd0, (q15_t)0x1099, (q15_t)0x7dd3, (q15_t)0x108c, + (q15_t)0x7dd6, (q15_t)0x1080, (q15_t)0x7dd9, (q15_t)0x1074, (q15_t)0x7ddd, (q15_t)0x1068, (q15_t)0x7de0, (q15_t)0x105c, + (q15_t)0x7de3, (q15_t)0x1050, (q15_t)0x7de6, (q15_t)0x1044, (q15_t)0x7de9, (q15_t)0x1037, (q15_t)0x7ded, (q15_t)0x102b, + (q15_t)0x7df0, (q15_t)0x101f, (q15_t)0x7df3, (q15_t)0x1013, (q15_t)0x7df6, (q15_t)0x1007, (q15_t)0x7df9, (q15_t)0xffb, + (q15_t)0x7dfc, (q15_t)0xfee, (q15_t)0x7dff, (q15_t)0xfe2, (q15_t)0x7e03, (q15_t)0xfd6, (q15_t)0x7e06, (q15_t)0xfca, + (q15_t)0x7e09, (q15_t)0xfbe, (q15_t)0x7e0c, (q15_t)0xfb2, (q15_t)0x7e0f, (q15_t)0xfa5, (q15_t)0x7e12, (q15_t)0xf99, + (q15_t)0x7e15, (q15_t)0xf8d, (q15_t)0x7e18, (q15_t)0xf81, (q15_t)0x7e1b, (q15_t)0xf75, (q15_t)0x7e1e, (q15_t)0xf68, + (q15_t)0x7e21, (q15_t)0xf5c, (q15_t)0x7e24, (q15_t)0xf50, (q15_t)0x7e27, (q15_t)0xf44, (q15_t)0x7e2a, (q15_t)0xf38, + (q15_t)0x7e2d, (q15_t)0xf2b, (q15_t)0x7e30, (q15_t)0xf1f, (q15_t)0x7e33, (q15_t)0xf13, (q15_t)0x7e36, (q15_t)0xf07, + (q15_t)0x7e39, (q15_t)0xefb, (q15_t)0x7e3c, (q15_t)0xeee, (q15_t)0x7e3f, (q15_t)0xee2, (q15_t)0x7e42, (q15_t)0xed6, + (q15_t)0x7e45, (q15_t)0xeca, (q15_t)0x7e48, (q15_t)0xebd, (q15_t)0x7e4a, (q15_t)0xeb1, (q15_t)0x7e4d, (q15_t)0xea5, + (q15_t)0x7e50, (q15_t)0xe99, (q15_t)0x7e53, (q15_t)0xe8c, (q15_t)0x7e56, (q15_t)0xe80, (q15_t)0x7e59, (q15_t)0xe74, + (q15_t)0x7e5c, (q15_t)0xe68, (q15_t)0x7e5e, (q15_t)0xe5c, (q15_t)0x7e61, (q15_t)0xe4f, (q15_t)0x7e64, (q15_t)0xe43, + (q15_t)0x7e67, (q15_t)0xe37, (q15_t)0x7e6a, (q15_t)0xe2b, (q15_t)0x7e6c, (q15_t)0xe1e, (q15_t)0x7e6f, (q15_t)0xe12, + (q15_t)0x7e72, (q15_t)0xe06, (q15_t)0x7e75, (q15_t)0xdf9, (q15_t)0x7e77, (q15_t)0xded, (q15_t)0x7e7a, (q15_t)0xde1, + (q15_t)0x7e7d, (q15_t)0xdd5, (q15_t)0x7e80, (q15_t)0xdc8, (q15_t)0x7e82, (q15_t)0xdbc, (q15_t)0x7e85, (q15_t)0xdb0, + (q15_t)0x7e88, (q15_t)0xda4, (q15_t)0x7e8a, (q15_t)0xd97, (q15_t)0x7e8d, (q15_t)0xd8b, (q15_t)0x7e90, (q15_t)0xd7f, + (q15_t)0x7e92, (q15_t)0xd72, (q15_t)0x7e95, (q15_t)0xd66, (q15_t)0x7e98, (q15_t)0xd5a, (q15_t)0x7e9a, (q15_t)0xd4e, + (q15_t)0x7e9d, (q15_t)0xd41, (q15_t)0x7e9f, (q15_t)0xd35, (q15_t)0x7ea2, (q15_t)0xd29, (q15_t)0x7ea5, (q15_t)0xd1c, + (q15_t)0x7ea7, (q15_t)0xd10, (q15_t)0x7eaa, (q15_t)0xd04, (q15_t)0x7eac, (q15_t)0xcf8, (q15_t)0x7eaf, (q15_t)0xceb, + (q15_t)0x7eb1, (q15_t)0xcdf, (q15_t)0x7eb4, (q15_t)0xcd3, (q15_t)0x7eb6, (q15_t)0xcc6, (q15_t)0x7eb9, (q15_t)0xcba, + (q15_t)0x7ebb, (q15_t)0xcae, (q15_t)0x7ebe, (q15_t)0xca1, (q15_t)0x7ec0, (q15_t)0xc95, (q15_t)0x7ec3, (q15_t)0xc89, + (q15_t)0x7ec5, (q15_t)0xc7c, (q15_t)0x7ec8, (q15_t)0xc70, (q15_t)0x7eca, (q15_t)0xc64, (q15_t)0x7ecc, (q15_t)0xc57, + (q15_t)0x7ecf, (q15_t)0xc4b, (q15_t)0x7ed1, (q15_t)0xc3f, (q15_t)0x7ed4, (q15_t)0xc32, (q15_t)0x7ed6, (q15_t)0xc26, + (q15_t)0x7ed8, (q15_t)0xc1a, (q15_t)0x7edb, (q15_t)0xc0d, (q15_t)0x7edd, (q15_t)0xc01, (q15_t)0x7ee0, (q15_t)0xbf5, + (q15_t)0x7ee2, (q15_t)0xbe8, (q15_t)0x7ee4, (q15_t)0xbdc, (q15_t)0x7ee7, (q15_t)0xbd0, (q15_t)0x7ee9, (q15_t)0xbc3, + (q15_t)0x7eeb, (q15_t)0xbb7, (q15_t)0x7eed, (q15_t)0xbab, (q15_t)0x7ef0, (q15_t)0xb9e, (q15_t)0x7ef2, (q15_t)0xb92, + (q15_t)0x7ef4, (q15_t)0xb85, (q15_t)0x7ef7, (q15_t)0xb79, (q15_t)0x7ef9, (q15_t)0xb6d, (q15_t)0x7efb, (q15_t)0xb60, + (q15_t)0x7efd, (q15_t)0xb54, (q15_t)0x7f00, (q15_t)0xb48, (q15_t)0x7f02, (q15_t)0xb3b, (q15_t)0x7f04, (q15_t)0xb2f, + (q15_t)0x7f06, (q15_t)0xb23, (q15_t)0x7f08, (q15_t)0xb16, (q15_t)0x7f0a, (q15_t)0xb0a, (q15_t)0x7f0d, (q15_t)0xafd, + (q15_t)0x7f0f, (q15_t)0xaf1, (q15_t)0x7f11, (q15_t)0xae5, (q15_t)0x7f13, (q15_t)0xad8, (q15_t)0x7f15, (q15_t)0xacc, + (q15_t)0x7f17, (q15_t)0xac0, (q15_t)0x7f19, (q15_t)0xab3, (q15_t)0x7f1c, (q15_t)0xaa7, (q15_t)0x7f1e, (q15_t)0xa9a, + (q15_t)0x7f20, (q15_t)0xa8e, (q15_t)0x7f22, (q15_t)0xa82, (q15_t)0x7f24, (q15_t)0xa75, (q15_t)0x7f26, (q15_t)0xa69, + (q15_t)0x7f28, (q15_t)0xa5c, (q15_t)0x7f2a, (q15_t)0xa50, (q15_t)0x7f2c, (q15_t)0xa44, (q15_t)0x7f2e, (q15_t)0xa37, + (q15_t)0x7f30, (q15_t)0xa2b, (q15_t)0x7f32, (q15_t)0xa1e, (q15_t)0x7f34, (q15_t)0xa12, (q15_t)0x7f36, (q15_t)0xa06, + (q15_t)0x7f38, (q15_t)0x9f9, (q15_t)0x7f3a, (q15_t)0x9ed, (q15_t)0x7f3c, (q15_t)0x9e0, (q15_t)0x7f3e, (q15_t)0x9d4, + (q15_t)0x7f40, (q15_t)0x9c7, (q15_t)0x7f42, (q15_t)0x9bb, (q15_t)0x7f43, (q15_t)0x9af, (q15_t)0x7f45, (q15_t)0x9a2, + (q15_t)0x7f47, (q15_t)0x996, (q15_t)0x7f49, (q15_t)0x989, (q15_t)0x7f4b, (q15_t)0x97d, (q15_t)0x7f4d, (q15_t)0x970, + (q15_t)0x7f4f, (q15_t)0x964, (q15_t)0x7f51, (q15_t)0x958, (q15_t)0x7f52, (q15_t)0x94b, (q15_t)0x7f54, (q15_t)0x93f, + (q15_t)0x7f56, (q15_t)0x932, (q15_t)0x7f58, (q15_t)0x926, (q15_t)0x7f5a, (q15_t)0x919, (q15_t)0x7f5b, (q15_t)0x90d, + (q15_t)0x7f5d, (q15_t)0x901, (q15_t)0x7f5f, (q15_t)0x8f4, (q15_t)0x7f61, (q15_t)0x8e8, (q15_t)0x7f62, (q15_t)0x8db, + (q15_t)0x7f64, (q15_t)0x8cf, (q15_t)0x7f66, (q15_t)0x8c2, (q15_t)0x7f68, (q15_t)0x8b6, (q15_t)0x7f69, (q15_t)0x8a9, + (q15_t)0x7f6b, (q15_t)0x89d, (q15_t)0x7f6d, (q15_t)0x891, (q15_t)0x7f6e, (q15_t)0x884, (q15_t)0x7f70, (q15_t)0x878, + (q15_t)0x7f72, (q15_t)0x86b, (q15_t)0x7f73, (q15_t)0x85f, (q15_t)0x7f75, (q15_t)0x852, (q15_t)0x7f77, (q15_t)0x846, + (q15_t)0x7f78, (q15_t)0x839, (q15_t)0x7f7a, (q15_t)0x82d, (q15_t)0x7f7b, (q15_t)0x820, (q15_t)0x7f7d, (q15_t)0x814, + (q15_t)0x7f7f, (q15_t)0x807, (q15_t)0x7f80, (q15_t)0x7fb, (q15_t)0x7f82, (q15_t)0x7ef, (q15_t)0x7f83, (q15_t)0x7e2, + (q15_t)0x7f85, (q15_t)0x7d6, (q15_t)0x7f86, (q15_t)0x7c9, (q15_t)0x7f88, (q15_t)0x7bd, (q15_t)0x7f89, (q15_t)0x7b0, + (q15_t)0x7f8b, (q15_t)0x7a4, (q15_t)0x7f8c, (q15_t)0x797, (q15_t)0x7f8e, (q15_t)0x78b, (q15_t)0x7f8f, (q15_t)0x77e, + (q15_t)0x7f91, (q15_t)0x772, (q15_t)0x7f92, (q15_t)0x765, (q15_t)0x7f94, (q15_t)0x759, (q15_t)0x7f95, (q15_t)0x74c, + (q15_t)0x7f97, (q15_t)0x740, (q15_t)0x7f98, (q15_t)0x733, (q15_t)0x7f99, (q15_t)0x727, (q15_t)0x7f9b, (q15_t)0x71a, + (q15_t)0x7f9c, (q15_t)0x70e, (q15_t)0x7f9e, (q15_t)0x701, (q15_t)0x7f9f, (q15_t)0x6f5, (q15_t)0x7fa0, (q15_t)0x6e8, + (q15_t)0x7fa2, (q15_t)0x6dc, (q15_t)0x7fa3, (q15_t)0x6cf, (q15_t)0x7fa4, (q15_t)0x6c3, (q15_t)0x7fa6, (q15_t)0x6b6, + (q15_t)0x7fa7, (q15_t)0x6aa, (q15_t)0x7fa8, (q15_t)0x69d, (q15_t)0x7faa, (q15_t)0x691, (q15_t)0x7fab, (q15_t)0x684, + (q15_t)0x7fac, (q15_t)0x678, (q15_t)0x7fad, (q15_t)0x66b, (q15_t)0x7faf, (q15_t)0x65f, (q15_t)0x7fb0, (q15_t)0x652, + (q15_t)0x7fb1, (q15_t)0x646, (q15_t)0x7fb2, (q15_t)0x639, (q15_t)0x7fb4, (q15_t)0x62d, (q15_t)0x7fb5, (q15_t)0x620, + (q15_t)0x7fb6, (q15_t)0x614, (q15_t)0x7fb7, (q15_t)0x607, (q15_t)0x7fb8, (q15_t)0x5fb, (q15_t)0x7fb9, (q15_t)0x5ee, + (q15_t)0x7fbb, (q15_t)0x5e2, (q15_t)0x7fbc, (q15_t)0x5d5, (q15_t)0x7fbd, (q15_t)0x5c9, (q15_t)0x7fbe, (q15_t)0x5bc, + (q15_t)0x7fbf, (q15_t)0x5b0, (q15_t)0x7fc0, (q15_t)0x5a3, (q15_t)0x7fc1, (q15_t)0x597, (q15_t)0x7fc3, (q15_t)0x58a, + (q15_t)0x7fc4, (q15_t)0x57e, (q15_t)0x7fc5, (q15_t)0x571, (q15_t)0x7fc6, (q15_t)0x565, (q15_t)0x7fc7, (q15_t)0x558, + (q15_t)0x7fc8, (q15_t)0x54c, (q15_t)0x7fc9, (q15_t)0x53f, (q15_t)0x7fca, (q15_t)0x533, (q15_t)0x7fcb, (q15_t)0x526, + (q15_t)0x7fcc, (q15_t)0x51a, (q15_t)0x7fcd, (q15_t)0x50d, (q15_t)0x7fce, (q15_t)0x500, (q15_t)0x7fcf, (q15_t)0x4f4, + (q15_t)0x7fd0, (q15_t)0x4e7, (q15_t)0x7fd1, (q15_t)0x4db, (q15_t)0x7fd2, (q15_t)0x4ce, (q15_t)0x7fd3, (q15_t)0x4c2, + (q15_t)0x7fd4, (q15_t)0x4b5, (q15_t)0x7fd5, (q15_t)0x4a9, (q15_t)0x7fd5, (q15_t)0x49c, (q15_t)0x7fd6, (q15_t)0x490, + (q15_t)0x7fd7, (q15_t)0x483, (q15_t)0x7fd8, (q15_t)0x477, (q15_t)0x7fd9, (q15_t)0x46a, (q15_t)0x7fda, (q15_t)0x45e, + (q15_t)0x7fdb, (q15_t)0x451, (q15_t)0x7fdc, (q15_t)0x444, (q15_t)0x7fdc, (q15_t)0x438, (q15_t)0x7fdd, (q15_t)0x42b, + (q15_t)0x7fde, (q15_t)0x41f, (q15_t)0x7fdf, (q15_t)0x412, (q15_t)0x7fe0, (q15_t)0x406, (q15_t)0x7fe0, (q15_t)0x3f9, + (q15_t)0x7fe1, (q15_t)0x3ed, (q15_t)0x7fe2, (q15_t)0x3e0, (q15_t)0x7fe3, (q15_t)0x3d4, (q15_t)0x7fe3, (q15_t)0x3c7, + (q15_t)0x7fe4, (q15_t)0x3bb, (q15_t)0x7fe5, (q15_t)0x3ae, (q15_t)0x7fe6, (q15_t)0x3a1, (q15_t)0x7fe6, (q15_t)0x395, + (q15_t)0x7fe7, (q15_t)0x388, (q15_t)0x7fe8, (q15_t)0x37c, (q15_t)0x7fe8, (q15_t)0x36f, (q15_t)0x7fe9, (q15_t)0x363, + (q15_t)0x7fea, (q15_t)0x356, (q15_t)0x7fea, (q15_t)0x34a, (q15_t)0x7feb, (q15_t)0x33d, (q15_t)0x7fec, (q15_t)0x330, + (q15_t)0x7fec, (q15_t)0x324, (q15_t)0x7fed, (q15_t)0x317, (q15_t)0x7fed, (q15_t)0x30b, (q15_t)0x7fee, (q15_t)0x2fe, + (q15_t)0x7fef, (q15_t)0x2f2, (q15_t)0x7fef, (q15_t)0x2e5, (q15_t)0x7ff0, (q15_t)0x2d9, (q15_t)0x7ff0, (q15_t)0x2cc, + (q15_t)0x7ff1, (q15_t)0x2c0, (q15_t)0x7ff1, (q15_t)0x2b3, (q15_t)0x7ff2, (q15_t)0x2a6, (q15_t)0x7ff2, (q15_t)0x29a, + (q15_t)0x7ff3, (q15_t)0x28d, (q15_t)0x7ff3, (q15_t)0x281, (q15_t)0x7ff4, (q15_t)0x274, (q15_t)0x7ff4, (q15_t)0x268, + (q15_t)0x7ff5, (q15_t)0x25b, (q15_t)0x7ff5, (q15_t)0x24e, (q15_t)0x7ff6, (q15_t)0x242, (q15_t)0x7ff6, (q15_t)0x235, + (q15_t)0x7ff7, (q15_t)0x229, (q15_t)0x7ff7, (q15_t)0x21c, (q15_t)0x7ff7, (q15_t)0x210, (q15_t)0x7ff8, (q15_t)0x203, + (q15_t)0x7ff8, (q15_t)0x1f7, (q15_t)0x7ff9, (q15_t)0x1ea, (q15_t)0x7ff9, (q15_t)0x1dd, (q15_t)0x7ff9, (q15_t)0x1d1, + (q15_t)0x7ffa, (q15_t)0x1c4, (q15_t)0x7ffa, (q15_t)0x1b8, (q15_t)0x7ffa, (q15_t)0x1ab, (q15_t)0x7ffb, (q15_t)0x19f, + (q15_t)0x7ffb, (q15_t)0x192, (q15_t)0x7ffb, (q15_t)0x186, (q15_t)0x7ffc, (q15_t)0x179, (q15_t)0x7ffc, (q15_t)0x16c, + (q15_t)0x7ffc, (q15_t)0x160, (q15_t)0x7ffc, (q15_t)0x153, (q15_t)0x7ffd, (q15_t)0x147, (q15_t)0x7ffd, (q15_t)0x13a, + (q15_t)0x7ffd, (q15_t)0x12e, (q15_t)0x7ffd, (q15_t)0x121, (q15_t)0x7ffe, (q15_t)0x114, (q15_t)0x7ffe, (q15_t)0x108, + (q15_t)0x7ffe, (q15_t)0xfb, (q15_t)0x7ffe, (q15_t)0xef, (q15_t)0x7ffe, (q15_t)0xe2, (q15_t)0x7fff, (q15_t)0xd6, + (q15_t)0x7fff, (q15_t)0xc9, (q15_t)0x7fff, (q15_t)0xbc, (q15_t)0x7fff, (q15_t)0xb0, (q15_t)0x7fff, (q15_t)0xa3, + (q15_t)0x7fff, (q15_t)0x97, (q15_t)0x7fff, (q15_t)0x8a, (q15_t)0x7fff, (q15_t)0x7e, (q15_t)0x7fff, (q15_t)0x71, + (q15_t)0x7fff, (q15_t)0x65, (q15_t)0x7fff, (q15_t)0x58, (q15_t)0x7fff, (q15_t)0x4b, (q15_t)0x7fff, (q15_t)0x3f, + (q15_t)0x7fff, (q15_t)0x32, (q15_t)0x7fff, (q15_t)0x26, (q15_t)0x7fff, (q15_t)0x19, (q15_t)0x7fff, (q15_t)0xd, + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfff3, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffda, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc1, (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffa8, + (q15_t)0x7fff, (q15_t)0xff9b, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff82, (q15_t)0x7fff, (q15_t)0xff76, + (q15_t)0x7fff, (q15_t)0xff69, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff50, (q15_t)0x7fff, (q15_t)0xff44, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff2a, (q15_t)0x7ffe, (q15_t)0xff1e, (q15_t)0x7ffe, (q15_t)0xff11, + (q15_t)0x7ffe, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfef8, (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffd, (q15_t)0xfedf, + (q15_t)0x7ffd, (q15_t)0xfed2, (q15_t)0x7ffd, (q15_t)0xfec6, (q15_t)0x7ffd, (q15_t)0xfeb9, (q15_t)0x7ffc, (q15_t)0xfead, + (q15_t)0x7ffc, (q15_t)0xfea0, (q15_t)0x7ffc, (q15_t)0xfe94, (q15_t)0x7ffc, (q15_t)0xfe87, (q15_t)0x7ffb, (q15_t)0xfe7a, + (q15_t)0x7ffb, (q15_t)0xfe6e, (q15_t)0x7ffb, (q15_t)0xfe61, (q15_t)0x7ffa, (q15_t)0xfe55, (q15_t)0x7ffa, (q15_t)0xfe48, + (q15_t)0x7ffa, (q15_t)0xfe3c, (q15_t)0x7ff9, (q15_t)0xfe2f, (q15_t)0x7ff9, (q15_t)0xfe23, (q15_t)0x7ff9, (q15_t)0xfe16, + (q15_t)0x7ff8, (q15_t)0xfe09, (q15_t)0x7ff8, (q15_t)0xfdfd, (q15_t)0x7ff7, (q15_t)0xfdf0, (q15_t)0x7ff7, (q15_t)0xfde4, + (q15_t)0x7ff7, (q15_t)0xfdd7, (q15_t)0x7ff6, (q15_t)0xfdcb, (q15_t)0x7ff6, (q15_t)0xfdbe, (q15_t)0x7ff5, (q15_t)0xfdb2, + (q15_t)0x7ff5, (q15_t)0xfda5, (q15_t)0x7ff4, (q15_t)0xfd98, (q15_t)0x7ff4, (q15_t)0xfd8c, (q15_t)0x7ff3, (q15_t)0xfd7f, + (q15_t)0x7ff3, (q15_t)0xfd73, (q15_t)0x7ff2, (q15_t)0xfd66, (q15_t)0x7ff2, (q15_t)0xfd5a, (q15_t)0x7ff1, (q15_t)0xfd4d, + (q15_t)0x7ff1, (q15_t)0xfd40, (q15_t)0x7ff0, (q15_t)0xfd34, (q15_t)0x7ff0, (q15_t)0xfd27, (q15_t)0x7fef, (q15_t)0xfd1b, + (q15_t)0x7fef, (q15_t)0xfd0e, (q15_t)0x7fee, (q15_t)0xfd02, (q15_t)0x7fed, (q15_t)0xfcf5, (q15_t)0x7fed, (q15_t)0xfce9, + (q15_t)0x7fec, (q15_t)0xfcdc, (q15_t)0x7fec, (q15_t)0xfcd0, (q15_t)0x7feb, (q15_t)0xfcc3, (q15_t)0x7fea, (q15_t)0xfcb6, + (q15_t)0x7fea, (q15_t)0xfcaa, (q15_t)0x7fe9, (q15_t)0xfc9d, (q15_t)0x7fe8, (q15_t)0xfc91, (q15_t)0x7fe8, (q15_t)0xfc84, + (q15_t)0x7fe7, (q15_t)0xfc78, (q15_t)0x7fe6, (q15_t)0xfc6b, (q15_t)0x7fe6, (q15_t)0xfc5f, (q15_t)0x7fe5, (q15_t)0xfc52, + (q15_t)0x7fe4, (q15_t)0xfc45, (q15_t)0x7fe3, (q15_t)0xfc39, (q15_t)0x7fe3, (q15_t)0xfc2c, (q15_t)0x7fe2, (q15_t)0xfc20, + (q15_t)0x7fe1, (q15_t)0xfc13, (q15_t)0x7fe0, (q15_t)0xfc07, (q15_t)0x7fe0, (q15_t)0xfbfa, (q15_t)0x7fdf, (q15_t)0xfbee, + (q15_t)0x7fde, (q15_t)0xfbe1, (q15_t)0x7fdd, (q15_t)0xfbd5, (q15_t)0x7fdc, (q15_t)0xfbc8, (q15_t)0x7fdc, (q15_t)0xfbbc, + (q15_t)0x7fdb, (q15_t)0xfbaf, (q15_t)0x7fda, (q15_t)0xfba2, (q15_t)0x7fd9, (q15_t)0xfb96, (q15_t)0x7fd8, (q15_t)0xfb89, + (q15_t)0x7fd7, (q15_t)0xfb7d, (q15_t)0x7fd6, (q15_t)0xfb70, (q15_t)0x7fd5, (q15_t)0xfb64, (q15_t)0x7fd5, (q15_t)0xfb57, + (q15_t)0x7fd4, (q15_t)0xfb4b, (q15_t)0x7fd3, (q15_t)0xfb3e, (q15_t)0x7fd2, (q15_t)0xfb32, (q15_t)0x7fd1, (q15_t)0xfb25, + (q15_t)0x7fd0, (q15_t)0xfb19, (q15_t)0x7fcf, (q15_t)0xfb0c, (q15_t)0x7fce, (q15_t)0xfb00, (q15_t)0x7fcd, (q15_t)0xfaf3, + (q15_t)0x7fcc, (q15_t)0xfae6, (q15_t)0x7fcb, (q15_t)0xfada, (q15_t)0x7fca, (q15_t)0xfacd, (q15_t)0x7fc9, (q15_t)0xfac1, + (q15_t)0x7fc8, (q15_t)0xfab4, (q15_t)0x7fc7, (q15_t)0xfaa8, (q15_t)0x7fc6, (q15_t)0xfa9b, (q15_t)0x7fc5, (q15_t)0xfa8f, + (q15_t)0x7fc4, (q15_t)0xfa82, (q15_t)0x7fc3, (q15_t)0xfa76, (q15_t)0x7fc1, (q15_t)0xfa69, (q15_t)0x7fc0, (q15_t)0xfa5d, + (q15_t)0x7fbf, (q15_t)0xfa50, (q15_t)0x7fbe, (q15_t)0xfa44, (q15_t)0x7fbd, (q15_t)0xfa37, (q15_t)0x7fbc, (q15_t)0xfa2b, + (q15_t)0x7fbb, (q15_t)0xfa1e, (q15_t)0x7fb9, (q15_t)0xfa12, (q15_t)0x7fb8, (q15_t)0xfa05, (q15_t)0x7fb7, (q15_t)0xf9f9, + (q15_t)0x7fb6, (q15_t)0xf9ec, (q15_t)0x7fb5, (q15_t)0xf9e0, (q15_t)0x7fb4, (q15_t)0xf9d3, (q15_t)0x7fb2, (q15_t)0xf9c7, + (q15_t)0x7fb1, (q15_t)0xf9ba, (q15_t)0x7fb0, (q15_t)0xf9ae, (q15_t)0x7faf, (q15_t)0xf9a1, (q15_t)0x7fad, (q15_t)0xf995, + (q15_t)0x7fac, (q15_t)0xf988, (q15_t)0x7fab, (q15_t)0xf97c, (q15_t)0x7faa, (q15_t)0xf96f, (q15_t)0x7fa8, (q15_t)0xf963, + (q15_t)0x7fa7, (q15_t)0xf956, (q15_t)0x7fa6, (q15_t)0xf94a, (q15_t)0x7fa4, (q15_t)0xf93d, (q15_t)0x7fa3, (q15_t)0xf931, + (q15_t)0x7fa2, (q15_t)0xf924, (q15_t)0x7fa0, (q15_t)0xf918, (q15_t)0x7f9f, (q15_t)0xf90b, (q15_t)0x7f9e, (q15_t)0xf8ff, + (q15_t)0x7f9c, (q15_t)0xf8f2, (q15_t)0x7f9b, (q15_t)0xf8e6, (q15_t)0x7f99, (q15_t)0xf8d9, (q15_t)0x7f98, (q15_t)0xf8cd, + (q15_t)0x7f97, (q15_t)0xf8c0, (q15_t)0x7f95, (q15_t)0xf8b4, (q15_t)0x7f94, (q15_t)0xf8a7, (q15_t)0x7f92, (q15_t)0xf89b, + (q15_t)0x7f91, (q15_t)0xf88e, (q15_t)0x7f8f, (q15_t)0xf882, (q15_t)0x7f8e, (q15_t)0xf875, (q15_t)0x7f8c, (q15_t)0xf869, + (q15_t)0x7f8b, (q15_t)0xf85c, (q15_t)0x7f89, (q15_t)0xf850, (q15_t)0x7f88, (q15_t)0xf843, (q15_t)0x7f86, (q15_t)0xf837, + (q15_t)0x7f85, (q15_t)0xf82a, (q15_t)0x7f83, (q15_t)0xf81e, (q15_t)0x7f82, (q15_t)0xf811, (q15_t)0x7f80, (q15_t)0xf805, + (q15_t)0x7f7f, (q15_t)0xf7f9, (q15_t)0x7f7d, (q15_t)0xf7ec, (q15_t)0x7f7b, (q15_t)0xf7e0, (q15_t)0x7f7a, (q15_t)0xf7d3, + (q15_t)0x7f78, (q15_t)0xf7c7, (q15_t)0x7f77, (q15_t)0xf7ba, (q15_t)0x7f75, (q15_t)0xf7ae, (q15_t)0x7f73, (q15_t)0xf7a1, + (q15_t)0x7f72, (q15_t)0xf795, (q15_t)0x7f70, (q15_t)0xf788, (q15_t)0x7f6e, (q15_t)0xf77c, (q15_t)0x7f6d, (q15_t)0xf76f, + (q15_t)0x7f6b, (q15_t)0xf763, (q15_t)0x7f69, (q15_t)0xf757, (q15_t)0x7f68, (q15_t)0xf74a, (q15_t)0x7f66, (q15_t)0xf73e, + (q15_t)0x7f64, (q15_t)0xf731, (q15_t)0x7f62, (q15_t)0xf725, (q15_t)0x7f61, (q15_t)0xf718, (q15_t)0x7f5f, (q15_t)0xf70c, + (q15_t)0x7f5d, (q15_t)0xf6ff, (q15_t)0x7f5b, (q15_t)0xf6f3, (q15_t)0x7f5a, (q15_t)0xf6e7, (q15_t)0x7f58, (q15_t)0xf6da, + (q15_t)0x7f56, (q15_t)0xf6ce, (q15_t)0x7f54, (q15_t)0xf6c1, (q15_t)0x7f52, (q15_t)0xf6b5, (q15_t)0x7f51, (q15_t)0xf6a8, + (q15_t)0x7f4f, (q15_t)0xf69c, (q15_t)0x7f4d, (q15_t)0xf690, (q15_t)0x7f4b, (q15_t)0xf683, (q15_t)0x7f49, (q15_t)0xf677, + (q15_t)0x7f47, (q15_t)0xf66a, (q15_t)0x7f45, (q15_t)0xf65e, (q15_t)0x7f43, (q15_t)0xf651, (q15_t)0x7f42, (q15_t)0xf645, + (q15_t)0x7f40, (q15_t)0xf639, (q15_t)0x7f3e, (q15_t)0xf62c, (q15_t)0x7f3c, (q15_t)0xf620, (q15_t)0x7f3a, (q15_t)0xf613, + (q15_t)0x7f38, (q15_t)0xf607, (q15_t)0x7f36, (q15_t)0xf5fa, (q15_t)0x7f34, (q15_t)0xf5ee, (q15_t)0x7f32, (q15_t)0xf5e2, + (q15_t)0x7f30, (q15_t)0xf5d5, (q15_t)0x7f2e, (q15_t)0xf5c9, (q15_t)0x7f2c, (q15_t)0xf5bc, (q15_t)0x7f2a, (q15_t)0xf5b0, + (q15_t)0x7f28, (q15_t)0xf5a4, (q15_t)0x7f26, (q15_t)0xf597, (q15_t)0x7f24, (q15_t)0xf58b, (q15_t)0x7f22, (q15_t)0xf57e, + (q15_t)0x7f20, (q15_t)0xf572, (q15_t)0x7f1e, (q15_t)0xf566, (q15_t)0x7f1c, (q15_t)0xf559, (q15_t)0x7f19, (q15_t)0xf54d, + (q15_t)0x7f17, (q15_t)0xf540, (q15_t)0x7f15, (q15_t)0xf534, (q15_t)0x7f13, (q15_t)0xf528, (q15_t)0x7f11, (q15_t)0xf51b, + (q15_t)0x7f0f, (q15_t)0xf50f, (q15_t)0x7f0d, (q15_t)0xf503, (q15_t)0x7f0a, (q15_t)0xf4f6, (q15_t)0x7f08, (q15_t)0xf4ea, + (q15_t)0x7f06, (q15_t)0xf4dd, (q15_t)0x7f04, (q15_t)0xf4d1, (q15_t)0x7f02, (q15_t)0xf4c5, (q15_t)0x7f00, (q15_t)0xf4b8, + (q15_t)0x7efd, (q15_t)0xf4ac, (q15_t)0x7efb, (q15_t)0xf4a0, (q15_t)0x7ef9, (q15_t)0xf493, (q15_t)0x7ef7, (q15_t)0xf487, + (q15_t)0x7ef4, (q15_t)0xf47b, (q15_t)0x7ef2, (q15_t)0xf46e, (q15_t)0x7ef0, (q15_t)0xf462, (q15_t)0x7eed, (q15_t)0xf455, + (q15_t)0x7eeb, (q15_t)0xf449, (q15_t)0x7ee9, (q15_t)0xf43d, (q15_t)0x7ee7, (q15_t)0xf430, (q15_t)0x7ee4, (q15_t)0xf424, + (q15_t)0x7ee2, (q15_t)0xf418, (q15_t)0x7ee0, (q15_t)0xf40b, (q15_t)0x7edd, (q15_t)0xf3ff, (q15_t)0x7edb, (q15_t)0xf3f3, + (q15_t)0x7ed8, (q15_t)0xf3e6, (q15_t)0x7ed6, (q15_t)0xf3da, (q15_t)0x7ed4, (q15_t)0xf3ce, (q15_t)0x7ed1, (q15_t)0xf3c1, + (q15_t)0x7ecf, (q15_t)0xf3b5, (q15_t)0x7ecc, (q15_t)0xf3a9, (q15_t)0x7eca, (q15_t)0xf39c, (q15_t)0x7ec8, (q15_t)0xf390, + (q15_t)0x7ec5, (q15_t)0xf384, (q15_t)0x7ec3, (q15_t)0xf377, (q15_t)0x7ec0, (q15_t)0xf36b, (q15_t)0x7ebe, (q15_t)0xf35f, + (q15_t)0x7ebb, (q15_t)0xf352, (q15_t)0x7eb9, (q15_t)0xf346, (q15_t)0x7eb6, (q15_t)0xf33a, (q15_t)0x7eb4, (q15_t)0xf32d, + (q15_t)0x7eb1, (q15_t)0xf321, (q15_t)0x7eaf, (q15_t)0xf315, (q15_t)0x7eac, (q15_t)0xf308, (q15_t)0x7eaa, (q15_t)0xf2fc, + (q15_t)0x7ea7, (q15_t)0xf2f0, (q15_t)0x7ea5, (q15_t)0xf2e4, (q15_t)0x7ea2, (q15_t)0xf2d7, (q15_t)0x7e9f, (q15_t)0xf2cb, + (q15_t)0x7e9d, (q15_t)0xf2bf, (q15_t)0x7e9a, (q15_t)0xf2b2, (q15_t)0x7e98, (q15_t)0xf2a6, (q15_t)0x7e95, (q15_t)0xf29a, + (q15_t)0x7e92, (q15_t)0xf28e, (q15_t)0x7e90, (q15_t)0xf281, (q15_t)0x7e8d, (q15_t)0xf275, (q15_t)0x7e8a, (q15_t)0xf269, + (q15_t)0x7e88, (q15_t)0xf25c, (q15_t)0x7e85, (q15_t)0xf250, (q15_t)0x7e82, (q15_t)0xf244, (q15_t)0x7e80, (q15_t)0xf238, + (q15_t)0x7e7d, (q15_t)0xf22b, (q15_t)0x7e7a, (q15_t)0xf21f, (q15_t)0x7e77, (q15_t)0xf213, (q15_t)0x7e75, (q15_t)0xf207, + (q15_t)0x7e72, (q15_t)0xf1fa, (q15_t)0x7e6f, (q15_t)0xf1ee, (q15_t)0x7e6c, (q15_t)0xf1e2, (q15_t)0x7e6a, (q15_t)0xf1d5, + (q15_t)0x7e67, (q15_t)0xf1c9, (q15_t)0x7e64, (q15_t)0xf1bd, (q15_t)0x7e61, (q15_t)0xf1b1, (q15_t)0x7e5e, (q15_t)0xf1a4, + (q15_t)0x7e5c, (q15_t)0xf198, (q15_t)0x7e59, (q15_t)0xf18c, (q15_t)0x7e56, (q15_t)0xf180, (q15_t)0x7e53, (q15_t)0xf174, + (q15_t)0x7e50, (q15_t)0xf167, (q15_t)0x7e4d, (q15_t)0xf15b, (q15_t)0x7e4a, (q15_t)0xf14f, (q15_t)0x7e48, (q15_t)0xf143, + (q15_t)0x7e45, (q15_t)0xf136, (q15_t)0x7e42, (q15_t)0xf12a, (q15_t)0x7e3f, (q15_t)0xf11e, (q15_t)0x7e3c, (q15_t)0xf112, + (q15_t)0x7e39, (q15_t)0xf105, (q15_t)0x7e36, (q15_t)0xf0f9, (q15_t)0x7e33, (q15_t)0xf0ed, (q15_t)0x7e30, (q15_t)0xf0e1, + (q15_t)0x7e2d, (q15_t)0xf0d5, (q15_t)0x7e2a, (q15_t)0xf0c8, (q15_t)0x7e27, (q15_t)0xf0bc, (q15_t)0x7e24, (q15_t)0xf0b0, + (q15_t)0x7e21, (q15_t)0xf0a4, (q15_t)0x7e1e, (q15_t)0xf098, (q15_t)0x7e1b, (q15_t)0xf08b, (q15_t)0x7e18, (q15_t)0xf07f, + (q15_t)0x7e15, (q15_t)0xf073, (q15_t)0x7e12, (q15_t)0xf067, (q15_t)0x7e0f, (q15_t)0xf05b, (q15_t)0x7e0c, (q15_t)0xf04e, + (q15_t)0x7e09, (q15_t)0xf042, (q15_t)0x7e06, (q15_t)0xf036, (q15_t)0x7e03, (q15_t)0xf02a, (q15_t)0x7dff, (q15_t)0xf01e, + (q15_t)0x7dfc, (q15_t)0xf012, (q15_t)0x7df9, (q15_t)0xf005, (q15_t)0x7df6, (q15_t)0xeff9, (q15_t)0x7df3, (q15_t)0xefed, + (q15_t)0x7df0, (q15_t)0xefe1, (q15_t)0x7ded, (q15_t)0xefd5, (q15_t)0x7de9, (q15_t)0xefc9, (q15_t)0x7de6, (q15_t)0xefbc, + (q15_t)0x7de3, (q15_t)0xefb0, (q15_t)0x7de0, (q15_t)0xefa4, (q15_t)0x7ddd, (q15_t)0xef98, (q15_t)0x7dd9, (q15_t)0xef8c, + (q15_t)0x7dd6, (q15_t)0xef80, (q15_t)0x7dd3, (q15_t)0xef74, (q15_t)0x7dd0, (q15_t)0xef67, (q15_t)0x7dcc, (q15_t)0xef5b, + (q15_t)0x7dc9, (q15_t)0xef4f, (q15_t)0x7dc6, (q15_t)0xef43, (q15_t)0x7dc2, (q15_t)0xef37, (q15_t)0x7dbf, (q15_t)0xef2b, + (q15_t)0x7dbc, (q15_t)0xef1f, (q15_t)0x7db9, (q15_t)0xef13, (q15_t)0x7db5, (q15_t)0xef06, (q15_t)0x7db2, (q15_t)0xeefa, + (q15_t)0x7daf, (q15_t)0xeeee, (q15_t)0x7dab, (q15_t)0xeee2, (q15_t)0x7da8, (q15_t)0xeed6, (q15_t)0x7da4, (q15_t)0xeeca, + (q15_t)0x7da1, (q15_t)0xeebe, (q15_t)0x7d9e, (q15_t)0xeeb2, (q15_t)0x7d9a, (q15_t)0xeea6, (q15_t)0x7d97, (q15_t)0xee99, + (q15_t)0x7d93, (q15_t)0xee8d, (q15_t)0x7d90, (q15_t)0xee81, (q15_t)0x7d8d, (q15_t)0xee75, (q15_t)0x7d89, (q15_t)0xee69, + (q15_t)0x7d86, (q15_t)0xee5d, (q15_t)0x7d82, (q15_t)0xee51, (q15_t)0x7d7f, (q15_t)0xee45, (q15_t)0x7d7b, (q15_t)0xee39, + (q15_t)0x7d78, (q15_t)0xee2d, (q15_t)0x7d74, (q15_t)0xee21, (q15_t)0x7d71, (q15_t)0xee15, (q15_t)0x7d6d, (q15_t)0xee09, + (q15_t)0x7d6a, (q15_t)0xedfc, (q15_t)0x7d66, (q15_t)0xedf0, (q15_t)0x7d63, (q15_t)0xede4, (q15_t)0x7d5f, (q15_t)0xedd8, + (q15_t)0x7d5b, (q15_t)0xedcc, (q15_t)0x7d58, (q15_t)0xedc0, (q15_t)0x7d54, (q15_t)0xedb4, (q15_t)0x7d51, (q15_t)0xeda8, + (q15_t)0x7d4d, (q15_t)0xed9c, (q15_t)0x7d49, (q15_t)0xed90, (q15_t)0x7d46, (q15_t)0xed84, (q15_t)0x7d42, (q15_t)0xed78, + (q15_t)0x7d3f, (q15_t)0xed6c, (q15_t)0x7d3b, (q15_t)0xed60, (q15_t)0x7d37, (q15_t)0xed54, (q15_t)0x7d34, (q15_t)0xed48, + (q15_t)0x7d30, (q15_t)0xed3c, (q15_t)0x7d2c, (q15_t)0xed30, (q15_t)0x7d28, (q15_t)0xed24, (q15_t)0x7d25, (q15_t)0xed18, + (q15_t)0x7d21, (q15_t)0xed0c, (q15_t)0x7d1d, (q15_t)0xed00, (q15_t)0x7d1a, (q15_t)0xecf4, (q15_t)0x7d16, (q15_t)0xece8, + (q15_t)0x7d12, (q15_t)0xecdc, (q15_t)0x7d0e, (q15_t)0xecd0, (q15_t)0x7d0b, (q15_t)0xecc4, (q15_t)0x7d07, (q15_t)0xecb8, + (q15_t)0x7d03, (q15_t)0xecac, (q15_t)0x7cff, (q15_t)0xeca0, (q15_t)0x7cfb, (q15_t)0xec94, (q15_t)0x7cf8, (q15_t)0xec88, + (q15_t)0x7cf4, (q15_t)0xec7c, (q15_t)0x7cf0, (q15_t)0xec70, (q15_t)0x7cec, (q15_t)0xec64, (q15_t)0x7ce8, (q15_t)0xec58, + (q15_t)0x7ce4, (q15_t)0xec4c, (q15_t)0x7ce0, (q15_t)0xec40, (q15_t)0x7cdd, (q15_t)0xec34, (q15_t)0x7cd9, (q15_t)0xec28, + (q15_t)0x7cd5, (q15_t)0xec1c, (q15_t)0x7cd1, (q15_t)0xec10, (q15_t)0x7ccd, (q15_t)0xec05, (q15_t)0x7cc9, (q15_t)0xebf9, + (q15_t)0x7cc5, (q15_t)0xebed, (q15_t)0x7cc1, (q15_t)0xebe1, (q15_t)0x7cbd, (q15_t)0xebd5, (q15_t)0x7cb9, (q15_t)0xebc9, + (q15_t)0x7cb5, (q15_t)0xebbd, (q15_t)0x7cb1, (q15_t)0xebb1, (q15_t)0x7cad, (q15_t)0xeba5, (q15_t)0x7ca9, (q15_t)0xeb99, + (q15_t)0x7ca5, (q15_t)0xeb8d, (q15_t)0x7ca1, (q15_t)0xeb81, (q15_t)0x7c9d, (q15_t)0xeb75, (q15_t)0x7c99, (q15_t)0xeb6a, + (q15_t)0x7c95, (q15_t)0xeb5e, (q15_t)0x7c91, (q15_t)0xeb52, (q15_t)0x7c8d, (q15_t)0xeb46, (q15_t)0x7c89, (q15_t)0xeb3a, + (q15_t)0x7c85, (q15_t)0xeb2e, (q15_t)0x7c81, (q15_t)0xeb22, (q15_t)0x7c7d, (q15_t)0xeb16, (q15_t)0x7c79, (q15_t)0xeb0a, + (q15_t)0x7c74, (q15_t)0xeaff, (q15_t)0x7c70, (q15_t)0xeaf3, (q15_t)0x7c6c, (q15_t)0xeae7, (q15_t)0x7c68, (q15_t)0xeadb, + (q15_t)0x7c64, (q15_t)0xeacf, (q15_t)0x7c60, (q15_t)0xeac3, (q15_t)0x7c5b, (q15_t)0xeab7, (q15_t)0x7c57, (q15_t)0xeaac, + (q15_t)0x7c53, (q15_t)0xeaa0, (q15_t)0x7c4f, (q15_t)0xea94, (q15_t)0x7c4b, (q15_t)0xea88, (q15_t)0x7c46, (q15_t)0xea7c, + (q15_t)0x7c42, (q15_t)0xea70, (q15_t)0x7c3e, (q15_t)0xea65, (q15_t)0x7c3a, (q15_t)0xea59, (q15_t)0x7c36, (q15_t)0xea4d, + (q15_t)0x7c31, (q15_t)0xea41, (q15_t)0x7c2d, (q15_t)0xea35, (q15_t)0x7c29, (q15_t)0xea29, (q15_t)0x7c24, (q15_t)0xea1e, + (q15_t)0x7c20, (q15_t)0xea12, (q15_t)0x7c1c, (q15_t)0xea06, (q15_t)0x7c17, (q15_t)0xe9fa, (q15_t)0x7c13, (q15_t)0xe9ee, + (q15_t)0x7c0f, (q15_t)0xe9e3, (q15_t)0x7c0a, (q15_t)0xe9d7, (q15_t)0x7c06, (q15_t)0xe9cb, (q15_t)0x7c02, (q15_t)0xe9bf, + (q15_t)0x7bfd, (q15_t)0xe9b4, (q15_t)0x7bf9, (q15_t)0xe9a8, (q15_t)0x7bf5, (q15_t)0xe99c, (q15_t)0x7bf0, (q15_t)0xe990, + (q15_t)0x7bec, (q15_t)0xe984, (q15_t)0x7be7, (q15_t)0xe979, (q15_t)0x7be3, (q15_t)0xe96d, (q15_t)0x7bde, (q15_t)0xe961, + (q15_t)0x7bda, (q15_t)0xe955, (q15_t)0x7bd6, (q15_t)0xe94a, (q15_t)0x7bd1, (q15_t)0xe93e, (q15_t)0x7bcd, (q15_t)0xe932, + (q15_t)0x7bc8, (q15_t)0xe926, (q15_t)0x7bc4, (q15_t)0xe91b, (q15_t)0x7bbf, (q15_t)0xe90f, (q15_t)0x7bbb, (q15_t)0xe903, + (q15_t)0x7bb6, (q15_t)0xe8f7, (q15_t)0x7bb2, (q15_t)0xe8ec, (q15_t)0x7bad, (q15_t)0xe8e0, (q15_t)0x7ba9, (q15_t)0xe8d4, + (q15_t)0x7ba4, (q15_t)0xe8c9, (q15_t)0x7b9f, (q15_t)0xe8bd, (q15_t)0x7b9b, (q15_t)0xe8b1, (q15_t)0x7b96, (q15_t)0xe8a5, + (q15_t)0x7b92, (q15_t)0xe89a, (q15_t)0x7b8d, (q15_t)0xe88e, (q15_t)0x7b88, (q15_t)0xe882, (q15_t)0x7b84, (q15_t)0xe877, + (q15_t)0x7b7f, (q15_t)0xe86b, (q15_t)0x7b7b, (q15_t)0xe85f, (q15_t)0x7b76, (q15_t)0xe854, (q15_t)0x7b71, (q15_t)0xe848, + (q15_t)0x7b6d, (q15_t)0xe83c, (q15_t)0x7b68, (q15_t)0xe831, (q15_t)0x7b63, (q15_t)0xe825, (q15_t)0x7b5f, (q15_t)0xe819, + (q15_t)0x7b5a, (q15_t)0xe80e, (q15_t)0x7b55, (q15_t)0xe802, (q15_t)0x7b50, (q15_t)0xe7f6, (q15_t)0x7b4c, (q15_t)0xe7eb, + (q15_t)0x7b47, (q15_t)0xe7df, (q15_t)0x7b42, (q15_t)0xe7d3, (q15_t)0x7b3e, (q15_t)0xe7c8, (q15_t)0x7b39, (q15_t)0xe7bc, + (q15_t)0x7b34, (q15_t)0xe7b1, (q15_t)0x7b2f, (q15_t)0xe7a5, (q15_t)0x7b2a, (q15_t)0xe799, (q15_t)0x7b26, (q15_t)0xe78e, + (q15_t)0x7b21, (q15_t)0xe782, (q15_t)0x7b1c, (q15_t)0xe777, (q15_t)0x7b17, (q15_t)0xe76b, (q15_t)0x7b12, (q15_t)0xe75f, + (q15_t)0x7b0e, (q15_t)0xe754, (q15_t)0x7b09, (q15_t)0xe748, (q15_t)0x7b04, (q15_t)0xe73d, (q15_t)0x7aff, (q15_t)0xe731, + (q15_t)0x7afa, (q15_t)0xe725, (q15_t)0x7af5, (q15_t)0xe71a, (q15_t)0x7af0, (q15_t)0xe70e, (q15_t)0x7aeb, (q15_t)0xe703, + (q15_t)0x7ae6, (q15_t)0xe6f7, (q15_t)0x7ae2, (q15_t)0xe6ec, (q15_t)0x7add, (q15_t)0xe6e0, (q15_t)0x7ad8, (q15_t)0xe6d4, + (q15_t)0x7ad3, (q15_t)0xe6c9, (q15_t)0x7ace, (q15_t)0xe6bd, (q15_t)0x7ac9, (q15_t)0xe6b2, (q15_t)0x7ac4, (q15_t)0xe6a6, + (q15_t)0x7abf, (q15_t)0xe69b, (q15_t)0x7aba, (q15_t)0xe68f, (q15_t)0x7ab5, (q15_t)0xe684, (q15_t)0x7ab0, (q15_t)0xe678, + (q15_t)0x7aab, (q15_t)0xe66d, (q15_t)0x7aa6, (q15_t)0xe661, (q15_t)0x7aa1, (q15_t)0xe656, (q15_t)0x7a9c, (q15_t)0xe64a, + (q15_t)0x7a97, (q15_t)0xe63f, (q15_t)0x7a92, (q15_t)0xe633, (q15_t)0x7a8d, (q15_t)0xe628, (q15_t)0x7a88, (q15_t)0xe61c, + (q15_t)0x7a82, (q15_t)0xe611, (q15_t)0x7a7d, (q15_t)0xe605, (q15_t)0x7a78, (q15_t)0xe5fa, (q15_t)0x7a73, (q15_t)0xe5ee, + (q15_t)0x7a6e, (q15_t)0xe5e3, (q15_t)0x7a69, (q15_t)0xe5d7, (q15_t)0x7a64, (q15_t)0xe5cc, (q15_t)0x7a5f, (q15_t)0xe5c0, + (q15_t)0x7a59, (q15_t)0xe5b5, (q15_t)0x7a54, (q15_t)0xe5a9, (q15_t)0x7a4f, (q15_t)0xe59e, (q15_t)0x7a4a, (q15_t)0xe592, + (q15_t)0x7a45, (q15_t)0xe587, (q15_t)0x7a3f, (q15_t)0xe57c, (q15_t)0x7a3a, (q15_t)0xe570, (q15_t)0x7a35, (q15_t)0xe565, + (q15_t)0x7a30, (q15_t)0xe559, (q15_t)0x7a2b, (q15_t)0xe54e, (q15_t)0x7a25, (q15_t)0xe542, (q15_t)0x7a20, (q15_t)0xe537, + (q15_t)0x7a1b, (q15_t)0xe52c, (q15_t)0x7a16, (q15_t)0xe520, (q15_t)0x7a10, (q15_t)0xe515, (q15_t)0x7a0b, (q15_t)0xe509, + (q15_t)0x7a06, (q15_t)0xe4fe, (q15_t)0x7a00, (q15_t)0xe4f3, (q15_t)0x79fb, (q15_t)0xe4e7, (q15_t)0x79f6, (q15_t)0xe4dc, + (q15_t)0x79f0, (q15_t)0xe4d0, (q15_t)0x79eb, (q15_t)0xe4c5, (q15_t)0x79e6, (q15_t)0xe4ba, (q15_t)0x79e0, (q15_t)0xe4ae, + (q15_t)0x79db, (q15_t)0xe4a3, (q15_t)0x79d6, (q15_t)0xe498, (q15_t)0x79d0, (q15_t)0xe48c, (q15_t)0x79cb, (q15_t)0xe481, + (q15_t)0x79c5, (q15_t)0xe476, (q15_t)0x79c0, (q15_t)0xe46a, (q15_t)0x79bb, (q15_t)0xe45f, (q15_t)0x79b5, (q15_t)0xe454, + (q15_t)0x79b0, (q15_t)0xe448, (q15_t)0x79aa, (q15_t)0xe43d, (q15_t)0x79a5, (q15_t)0xe432, (q15_t)0x799f, (q15_t)0xe426, + (q15_t)0x799a, (q15_t)0xe41b, (q15_t)0x7994, (q15_t)0xe410, (q15_t)0x798f, (q15_t)0xe404, (q15_t)0x7989, (q15_t)0xe3f9, + (q15_t)0x7984, (q15_t)0xe3ee, (q15_t)0x797e, (q15_t)0xe3e2, (q15_t)0x7979, (q15_t)0xe3d7, (q15_t)0x7973, (q15_t)0xe3cc, + (q15_t)0x796e, (q15_t)0xe3c1, (q15_t)0x7968, (q15_t)0xe3b5, (q15_t)0x7963, (q15_t)0xe3aa, (q15_t)0x795d, (q15_t)0xe39f, + (q15_t)0x7958, (q15_t)0xe394, (q15_t)0x7952, (q15_t)0xe388, (q15_t)0x794c, (q15_t)0xe37d, (q15_t)0x7947, (q15_t)0xe372, + (q15_t)0x7941, (q15_t)0xe367, (q15_t)0x793b, (q15_t)0xe35b, (q15_t)0x7936, (q15_t)0xe350, (q15_t)0x7930, (q15_t)0xe345, + (q15_t)0x792b, (q15_t)0xe33a, (q15_t)0x7925, (q15_t)0xe32e, (q15_t)0x791f, (q15_t)0xe323, (q15_t)0x791a, (q15_t)0xe318, + (q15_t)0x7914, (q15_t)0xe30d, (q15_t)0x790e, (q15_t)0xe301, (q15_t)0x7909, (q15_t)0xe2f6, (q15_t)0x7903, (q15_t)0xe2eb, + (q15_t)0x78fd, (q15_t)0xe2e0, (q15_t)0x78f7, (q15_t)0xe2d5, (q15_t)0x78f2, (q15_t)0xe2ca, (q15_t)0x78ec, (q15_t)0xe2be, + (q15_t)0x78e6, (q15_t)0xe2b3, (q15_t)0x78e0, (q15_t)0xe2a8, (q15_t)0x78db, (q15_t)0xe29d, (q15_t)0x78d5, (q15_t)0xe292, + (q15_t)0x78cf, (q15_t)0xe287, (q15_t)0x78c9, (q15_t)0xe27b, (q15_t)0x78c3, (q15_t)0xe270, (q15_t)0x78be, (q15_t)0xe265, + (q15_t)0x78b8, (q15_t)0xe25a, (q15_t)0x78b2, (q15_t)0xe24f, (q15_t)0x78ac, (q15_t)0xe244, (q15_t)0x78a6, (q15_t)0xe239, + (q15_t)0x78a1, (q15_t)0xe22d, (q15_t)0x789b, (q15_t)0xe222, (q15_t)0x7895, (q15_t)0xe217, (q15_t)0x788f, (q15_t)0xe20c, + (q15_t)0x7889, (q15_t)0xe201, (q15_t)0x7883, (q15_t)0xe1f6, (q15_t)0x787d, (q15_t)0xe1eb, (q15_t)0x7877, (q15_t)0xe1e0, + (q15_t)0x7871, (q15_t)0xe1d5, (q15_t)0x786b, (q15_t)0xe1ca, (q15_t)0x7866, (q15_t)0xe1be, (q15_t)0x7860, (q15_t)0xe1b3, + (q15_t)0x785a, (q15_t)0xe1a8, (q15_t)0x7854, (q15_t)0xe19d, (q15_t)0x784e, (q15_t)0xe192, (q15_t)0x7848, (q15_t)0xe187, + (q15_t)0x7842, (q15_t)0xe17c, (q15_t)0x783c, (q15_t)0xe171, (q15_t)0x7836, (q15_t)0xe166, (q15_t)0x7830, (q15_t)0xe15b, + (q15_t)0x782a, (q15_t)0xe150, (q15_t)0x7824, (q15_t)0xe145, (q15_t)0x781e, (q15_t)0xe13a, (q15_t)0x7818, (q15_t)0xe12f, + (q15_t)0x7812, (q15_t)0xe124, (q15_t)0x780b, (q15_t)0xe119, (q15_t)0x7805, (q15_t)0xe10e, (q15_t)0x77ff, (q15_t)0xe103, + (q15_t)0x77f9, (q15_t)0xe0f8, (q15_t)0x77f3, (q15_t)0xe0ed, (q15_t)0x77ed, (q15_t)0xe0e2, (q15_t)0x77e7, (q15_t)0xe0d7, + (q15_t)0x77e1, (q15_t)0xe0cc, (q15_t)0x77db, (q15_t)0xe0c1, (q15_t)0x77d5, (q15_t)0xe0b6, (q15_t)0x77ce, (q15_t)0xe0ab, + (q15_t)0x77c8, (q15_t)0xe0a0, (q15_t)0x77c2, (q15_t)0xe095, (q15_t)0x77bc, (q15_t)0xe08a, (q15_t)0x77b6, (q15_t)0xe07f, + (q15_t)0x77b0, (q15_t)0xe074, (q15_t)0x77a9, (q15_t)0xe069, (q15_t)0x77a3, (q15_t)0xe05e, (q15_t)0x779d, (q15_t)0xe054, + (q15_t)0x7797, (q15_t)0xe049, (q15_t)0x7790, (q15_t)0xe03e, (q15_t)0x778a, (q15_t)0xe033, (q15_t)0x7784, (q15_t)0xe028, + (q15_t)0x777e, (q15_t)0xe01d, (q15_t)0x7777, (q15_t)0xe012, (q15_t)0x7771, (q15_t)0xe007, (q15_t)0x776b, (q15_t)0xdffc, + (q15_t)0x7765, (q15_t)0xdff1, (q15_t)0x775e, (q15_t)0xdfe7, (q15_t)0x7758, (q15_t)0xdfdc, (q15_t)0x7752, (q15_t)0xdfd1, + (q15_t)0x774b, (q15_t)0xdfc6, (q15_t)0x7745, (q15_t)0xdfbb, (q15_t)0x773f, (q15_t)0xdfb0, (q15_t)0x7738, (q15_t)0xdfa5, + (q15_t)0x7732, (q15_t)0xdf9b, (q15_t)0x772c, (q15_t)0xdf90, (q15_t)0x7725, (q15_t)0xdf85, (q15_t)0x771f, (q15_t)0xdf7a, + (q15_t)0x7718, (q15_t)0xdf6f, (q15_t)0x7712, (q15_t)0xdf65, (q15_t)0x770c, (q15_t)0xdf5a, (q15_t)0x7705, (q15_t)0xdf4f, + (q15_t)0x76ff, (q15_t)0xdf44, (q15_t)0x76f8, (q15_t)0xdf39, (q15_t)0x76f2, (q15_t)0xdf2f, (q15_t)0x76eb, (q15_t)0xdf24, + (q15_t)0x76e5, (q15_t)0xdf19, (q15_t)0x76df, (q15_t)0xdf0e, (q15_t)0x76d8, (q15_t)0xdf03, (q15_t)0x76d2, (q15_t)0xdef9, + (q15_t)0x76cb, (q15_t)0xdeee, (q15_t)0x76c5, (q15_t)0xdee3, (q15_t)0x76be, (q15_t)0xded8, (q15_t)0x76b8, (q15_t)0xdece, + (q15_t)0x76b1, (q15_t)0xdec3, (q15_t)0x76ab, (q15_t)0xdeb8, (q15_t)0x76a4, (q15_t)0xdead, (q15_t)0x769d, (q15_t)0xdea3, + (q15_t)0x7697, (q15_t)0xde98, (q15_t)0x7690, (q15_t)0xde8d, (q15_t)0x768a, (q15_t)0xde83, (q15_t)0x7683, (q15_t)0xde78, + (q15_t)0x767d, (q15_t)0xde6d, (q15_t)0x7676, (q15_t)0xde62, (q15_t)0x766f, (q15_t)0xde58, (q15_t)0x7669, (q15_t)0xde4d, + (q15_t)0x7662, (q15_t)0xde42, (q15_t)0x765c, (q15_t)0xde38, (q15_t)0x7655, (q15_t)0xde2d, (q15_t)0x764e, (q15_t)0xde22, + (q15_t)0x7648, (q15_t)0xde18, (q15_t)0x7641, (q15_t)0xde0d, (q15_t)0x763a, (q15_t)0xde02, (q15_t)0x7634, (q15_t)0xddf8, + (q15_t)0x762d, (q15_t)0xdded, (q15_t)0x7626, (q15_t)0xdde2, (q15_t)0x7620, (q15_t)0xddd8, (q15_t)0x7619, (q15_t)0xddcd, + (q15_t)0x7612, (q15_t)0xddc3, (q15_t)0x760b, (q15_t)0xddb8, (q15_t)0x7605, (q15_t)0xddad, (q15_t)0x75fe, (q15_t)0xdda3, + (q15_t)0x75f7, (q15_t)0xdd98, (q15_t)0x75f0, (q15_t)0xdd8e, (q15_t)0x75ea, (q15_t)0xdd83, (q15_t)0x75e3, (q15_t)0xdd78, + (q15_t)0x75dc, (q15_t)0xdd6e, (q15_t)0x75d5, (q15_t)0xdd63, (q15_t)0x75ce, (q15_t)0xdd59, (q15_t)0x75c8, (q15_t)0xdd4e, + (q15_t)0x75c1, (q15_t)0xdd44, (q15_t)0x75ba, (q15_t)0xdd39, (q15_t)0x75b3, (q15_t)0xdd2e, (q15_t)0x75ac, (q15_t)0xdd24, + (q15_t)0x75a5, (q15_t)0xdd19, (q15_t)0x759f, (q15_t)0xdd0f, (q15_t)0x7598, (q15_t)0xdd04, (q15_t)0x7591, (q15_t)0xdcfa, + (q15_t)0x758a, (q15_t)0xdcef, (q15_t)0x7583, (q15_t)0xdce5, (q15_t)0x757c, (q15_t)0xdcda, (q15_t)0x7575, (q15_t)0xdcd0, + (q15_t)0x756e, (q15_t)0xdcc5, (q15_t)0x7567, (q15_t)0xdcbb, (q15_t)0x7561, (q15_t)0xdcb0, (q15_t)0x755a, (q15_t)0xdca6, + (q15_t)0x7553, (q15_t)0xdc9b, (q15_t)0x754c, (q15_t)0xdc91, (q15_t)0x7545, (q15_t)0xdc86, (q15_t)0x753e, (q15_t)0xdc7c, + (q15_t)0x7537, (q15_t)0xdc72, (q15_t)0x7530, (q15_t)0xdc67, (q15_t)0x7529, (q15_t)0xdc5d, (q15_t)0x7522, (q15_t)0xdc52, + (q15_t)0x751b, (q15_t)0xdc48, (q15_t)0x7514, (q15_t)0xdc3d, (q15_t)0x750d, (q15_t)0xdc33, (q15_t)0x7506, (q15_t)0xdc29, + (q15_t)0x74ff, (q15_t)0xdc1e, (q15_t)0x74f8, (q15_t)0xdc14, (q15_t)0x74f1, (q15_t)0xdc09, (q15_t)0x74ea, (q15_t)0xdbff, + (q15_t)0x74e2, (q15_t)0xdbf5, (q15_t)0x74db, (q15_t)0xdbea, (q15_t)0x74d4, (q15_t)0xdbe0, (q15_t)0x74cd, (q15_t)0xdbd5, + (q15_t)0x74c6, (q15_t)0xdbcb, (q15_t)0x74bf, (q15_t)0xdbc1, (q15_t)0x74b8, (q15_t)0xdbb6, (q15_t)0x74b1, (q15_t)0xdbac, + (q15_t)0x74aa, (q15_t)0xdba2, (q15_t)0x74a2, (q15_t)0xdb97, (q15_t)0x749b, (q15_t)0xdb8d, (q15_t)0x7494, (q15_t)0xdb83, + (q15_t)0x748d, (q15_t)0xdb78, (q15_t)0x7486, (q15_t)0xdb6e, (q15_t)0x747f, (q15_t)0xdb64, (q15_t)0x7477, (q15_t)0xdb59, + (q15_t)0x7470, (q15_t)0xdb4f, (q15_t)0x7469, (q15_t)0xdb45, (q15_t)0x7462, (q15_t)0xdb3b, (q15_t)0x745b, (q15_t)0xdb30, + (q15_t)0x7453, (q15_t)0xdb26, (q15_t)0x744c, (q15_t)0xdb1c, (q15_t)0x7445, (q15_t)0xdb11, (q15_t)0x743e, (q15_t)0xdb07, + (q15_t)0x7436, (q15_t)0xdafd, (q15_t)0x742f, (q15_t)0xdaf3, (q15_t)0x7428, (q15_t)0xdae8, (q15_t)0x7420, (q15_t)0xdade, + (q15_t)0x7419, (q15_t)0xdad4, (q15_t)0x7412, (q15_t)0xdaca, (q15_t)0x740b, (q15_t)0xdabf, (q15_t)0x7403, (q15_t)0xdab5, + (q15_t)0x73fc, (q15_t)0xdaab, (q15_t)0x73f5, (q15_t)0xdaa1, (q15_t)0x73ed, (q15_t)0xda97, (q15_t)0x73e6, (q15_t)0xda8c, + (q15_t)0x73df, (q15_t)0xda82, (q15_t)0x73d7, (q15_t)0xda78, (q15_t)0x73d0, (q15_t)0xda6e, (q15_t)0x73c8, (q15_t)0xda64, + (q15_t)0x73c1, (q15_t)0xda5a, (q15_t)0x73ba, (q15_t)0xda4f, (q15_t)0x73b2, (q15_t)0xda45, (q15_t)0x73ab, (q15_t)0xda3b, + (q15_t)0x73a3, (q15_t)0xda31, (q15_t)0x739c, (q15_t)0xda27, (q15_t)0x7395, (q15_t)0xda1d, (q15_t)0x738d, (q15_t)0xda13, + (q15_t)0x7386, (q15_t)0xda08, (q15_t)0x737e, (q15_t)0xd9fe, (q15_t)0x7377, (q15_t)0xd9f4, (q15_t)0x736f, (q15_t)0xd9ea, + (q15_t)0x7368, (q15_t)0xd9e0, (q15_t)0x7360, (q15_t)0xd9d6, (q15_t)0x7359, (q15_t)0xd9cc, (q15_t)0x7351, (q15_t)0xd9c2, + (q15_t)0x734a, (q15_t)0xd9b8, (q15_t)0x7342, (q15_t)0xd9ae, (q15_t)0x733b, (q15_t)0xd9a4, (q15_t)0x7333, (q15_t)0xd99a, + (q15_t)0x732c, (q15_t)0xd98f, (q15_t)0x7324, (q15_t)0xd985, (q15_t)0x731d, (q15_t)0xd97b, (q15_t)0x7315, (q15_t)0xd971, + (q15_t)0x730d, (q15_t)0xd967, (q15_t)0x7306, (q15_t)0xd95d, (q15_t)0x72fe, (q15_t)0xd953, (q15_t)0x72f7, (q15_t)0xd949, + (q15_t)0x72ef, (q15_t)0xd93f, (q15_t)0x72e7, (q15_t)0xd935, (q15_t)0x72e0, (q15_t)0xd92b, (q15_t)0x72d8, (q15_t)0xd921, + (q15_t)0x72d0, (q15_t)0xd917, (q15_t)0x72c9, (q15_t)0xd90d, (q15_t)0x72c1, (q15_t)0xd903, (q15_t)0x72ba, (q15_t)0xd8f9, + (q15_t)0x72b2, (q15_t)0xd8ef, (q15_t)0x72aa, (q15_t)0xd8e6, (q15_t)0x72a3, (q15_t)0xd8dc, (q15_t)0x729b, (q15_t)0xd8d2, + (q15_t)0x7293, (q15_t)0xd8c8, (q15_t)0x728b, (q15_t)0xd8be, (q15_t)0x7284, (q15_t)0xd8b4, (q15_t)0x727c, (q15_t)0xd8aa, + (q15_t)0x7274, (q15_t)0xd8a0, (q15_t)0x726d, (q15_t)0xd896, (q15_t)0x7265, (q15_t)0xd88c, (q15_t)0x725d, (q15_t)0xd882, + (q15_t)0x7255, (q15_t)0xd878, (q15_t)0x724e, (q15_t)0xd86f, (q15_t)0x7246, (q15_t)0xd865, (q15_t)0x723e, (q15_t)0xd85b, + (q15_t)0x7236, (q15_t)0xd851, (q15_t)0x722e, (q15_t)0xd847, (q15_t)0x7227, (q15_t)0xd83d, (q15_t)0x721f, (q15_t)0xd833, + (q15_t)0x7217, (q15_t)0xd82a, (q15_t)0x720f, (q15_t)0xd820, (q15_t)0x7207, (q15_t)0xd816, (q15_t)0x71ff, (q15_t)0xd80c, + (q15_t)0x71f8, (q15_t)0xd802, (q15_t)0x71f0, (q15_t)0xd7f8, (q15_t)0x71e8, (q15_t)0xd7ef, (q15_t)0x71e0, (q15_t)0xd7e5, + (q15_t)0x71d8, (q15_t)0xd7db, (q15_t)0x71d0, (q15_t)0xd7d1, (q15_t)0x71c8, (q15_t)0xd7c8, (q15_t)0x71c0, (q15_t)0xd7be, + (q15_t)0x71b9, (q15_t)0xd7b4, (q15_t)0x71b1, (q15_t)0xd7aa, (q15_t)0x71a9, (q15_t)0xd7a0, (q15_t)0x71a1, (q15_t)0xd797, + (q15_t)0x7199, (q15_t)0xd78d, (q15_t)0x7191, (q15_t)0xd783, (q15_t)0x7189, (q15_t)0xd77a, (q15_t)0x7181, (q15_t)0xd770, + (q15_t)0x7179, (q15_t)0xd766, (q15_t)0x7171, (q15_t)0xd75c, (q15_t)0x7169, (q15_t)0xd753, (q15_t)0x7161, (q15_t)0xd749, + (q15_t)0x7159, (q15_t)0xd73f, (q15_t)0x7151, (q15_t)0xd736, (q15_t)0x7149, (q15_t)0xd72c, (q15_t)0x7141, (q15_t)0xd722, + (q15_t)0x7139, (q15_t)0xd719, (q15_t)0x7131, (q15_t)0xd70f, (q15_t)0x7129, (q15_t)0xd705, (q15_t)0x7121, (q15_t)0xd6fc, + (q15_t)0x7119, (q15_t)0xd6f2, (q15_t)0x7111, (q15_t)0xd6e8, (q15_t)0x7109, (q15_t)0xd6df, (q15_t)0x7101, (q15_t)0xd6d5, + (q15_t)0x70f9, (q15_t)0xd6cb, (q15_t)0x70f0, (q15_t)0xd6c2, (q15_t)0x70e8, (q15_t)0xd6b8, (q15_t)0x70e0, (q15_t)0xd6af, + (q15_t)0x70d8, (q15_t)0xd6a5, (q15_t)0x70d0, (q15_t)0xd69b, (q15_t)0x70c8, (q15_t)0xd692, (q15_t)0x70c0, (q15_t)0xd688, + (q15_t)0x70b8, (q15_t)0xd67f, (q15_t)0x70af, (q15_t)0xd675, (q15_t)0x70a7, (q15_t)0xd66c, (q15_t)0x709f, (q15_t)0xd662, + (q15_t)0x7097, (q15_t)0xd659, (q15_t)0x708f, (q15_t)0xd64f, (q15_t)0x7087, (q15_t)0xd645, (q15_t)0x707e, (q15_t)0xd63c, + (q15_t)0x7076, (q15_t)0xd632, (q15_t)0x706e, (q15_t)0xd629, (q15_t)0x7066, (q15_t)0xd61f, (q15_t)0x705d, (q15_t)0xd616, + (q15_t)0x7055, (q15_t)0xd60c, (q15_t)0x704d, (q15_t)0xd603, (q15_t)0x7045, (q15_t)0xd5f9, (q15_t)0x703c, (q15_t)0xd5f0, + (q15_t)0x7034, (q15_t)0xd5e6, (q15_t)0x702c, (q15_t)0xd5dd, (q15_t)0x7024, (q15_t)0xd5d4, (q15_t)0x701b, (q15_t)0xd5ca, + (q15_t)0x7013, (q15_t)0xd5c1, (q15_t)0x700b, (q15_t)0xd5b7, (q15_t)0x7002, (q15_t)0xd5ae, (q15_t)0x6ffa, (q15_t)0xd5a4, + (q15_t)0x6ff2, (q15_t)0xd59b, (q15_t)0x6fea, (q15_t)0xd592, (q15_t)0x6fe1, (q15_t)0xd588, (q15_t)0x6fd9, (q15_t)0xd57f, + (q15_t)0x6fd0, (q15_t)0xd575, (q15_t)0x6fc8, (q15_t)0xd56c, (q15_t)0x6fc0, (q15_t)0xd563, (q15_t)0x6fb7, (q15_t)0xd559, + (q15_t)0x6faf, (q15_t)0xd550, (q15_t)0x6fa7, (q15_t)0xd547, (q15_t)0x6f9e, (q15_t)0xd53d, (q15_t)0x6f96, (q15_t)0xd534, + (q15_t)0x6f8d, (q15_t)0xd52a, (q15_t)0x6f85, (q15_t)0xd521, (q15_t)0x6f7d, (q15_t)0xd518, (q15_t)0x6f74, (q15_t)0xd50e, + (q15_t)0x6f6c, (q15_t)0xd505, (q15_t)0x6f63, (q15_t)0xd4fc, (q15_t)0x6f5b, (q15_t)0xd4f3, (q15_t)0x6f52, (q15_t)0xd4e9, + (q15_t)0x6f4a, (q15_t)0xd4e0, (q15_t)0x6f41, (q15_t)0xd4d7, (q15_t)0x6f39, (q15_t)0xd4cd, (q15_t)0x6f30, (q15_t)0xd4c4, + (q15_t)0x6f28, (q15_t)0xd4bb, (q15_t)0x6f20, (q15_t)0xd4b2, (q15_t)0x6f17, (q15_t)0xd4a8, (q15_t)0x6f0e, (q15_t)0xd49f, + (q15_t)0x6f06, (q15_t)0xd496, (q15_t)0x6efd, (q15_t)0xd48d, (q15_t)0x6ef5, (q15_t)0xd483, (q15_t)0x6eec, (q15_t)0xd47a, + (q15_t)0x6ee4, (q15_t)0xd471, (q15_t)0x6edb, (q15_t)0xd468, (q15_t)0x6ed3, (q15_t)0xd45f, (q15_t)0x6eca, (q15_t)0xd455, + (q15_t)0x6ec2, (q15_t)0xd44c, (q15_t)0x6eb9, (q15_t)0xd443, (q15_t)0x6eb0, (q15_t)0xd43a, (q15_t)0x6ea8, (q15_t)0xd431, + (q15_t)0x6e9f, (q15_t)0xd428, (q15_t)0x6e97, (q15_t)0xd41e, (q15_t)0x6e8e, (q15_t)0xd415, (q15_t)0x6e85, (q15_t)0xd40c, + (q15_t)0x6e7d, (q15_t)0xd403, (q15_t)0x6e74, (q15_t)0xd3fa, (q15_t)0x6e6b, (q15_t)0xd3f1, (q15_t)0x6e63, (q15_t)0xd3e8, + (q15_t)0x6e5a, (q15_t)0xd3df, (q15_t)0x6e51, (q15_t)0xd3d5, (q15_t)0x6e49, (q15_t)0xd3cc, (q15_t)0x6e40, (q15_t)0xd3c3, + (q15_t)0x6e37, (q15_t)0xd3ba, (q15_t)0x6e2f, (q15_t)0xd3b1, (q15_t)0x6e26, (q15_t)0xd3a8, (q15_t)0x6e1d, (q15_t)0xd39f, + (q15_t)0x6e15, (q15_t)0xd396, (q15_t)0x6e0c, (q15_t)0xd38d, (q15_t)0x6e03, (q15_t)0xd384, (q15_t)0x6dfa, (q15_t)0xd37b, + (q15_t)0x6df2, (q15_t)0xd372, (q15_t)0x6de9, (q15_t)0xd369, (q15_t)0x6de0, (q15_t)0xd360, (q15_t)0x6dd7, (q15_t)0xd357, + (q15_t)0x6dcf, (q15_t)0xd34e, (q15_t)0x6dc6, (q15_t)0xd345, (q15_t)0x6dbd, (q15_t)0xd33c, (q15_t)0x6db4, (q15_t)0xd333, + (q15_t)0x6dab, (q15_t)0xd32a, (q15_t)0x6da3, (q15_t)0xd321, (q15_t)0x6d9a, (q15_t)0xd318, (q15_t)0x6d91, (q15_t)0xd30f, + (q15_t)0x6d88, (q15_t)0xd306, (q15_t)0x6d7f, (q15_t)0xd2fd, (q15_t)0x6d76, (q15_t)0xd2f4, (q15_t)0x6d6e, (q15_t)0xd2eb, + (q15_t)0x6d65, (q15_t)0xd2e2, (q15_t)0x6d5c, (q15_t)0xd2d9, (q15_t)0x6d53, (q15_t)0xd2d1, (q15_t)0x6d4a, (q15_t)0xd2c8, + (q15_t)0x6d41, (q15_t)0xd2bf, (q15_t)0x6d38, (q15_t)0xd2b6, (q15_t)0x6d2f, (q15_t)0xd2ad, (q15_t)0x6d27, (q15_t)0xd2a4, + (q15_t)0x6d1e, (q15_t)0xd29b, (q15_t)0x6d15, (q15_t)0xd292, (q15_t)0x6d0c, (q15_t)0xd28a, (q15_t)0x6d03, (q15_t)0xd281, + (q15_t)0x6cfa, (q15_t)0xd278, (q15_t)0x6cf1, (q15_t)0xd26f, (q15_t)0x6ce8, (q15_t)0xd266, (q15_t)0x6cdf, (q15_t)0xd25d, + (q15_t)0x6cd6, (q15_t)0xd255, (q15_t)0x6ccd, (q15_t)0xd24c, (q15_t)0x6cc4, (q15_t)0xd243, (q15_t)0x6cbb, (q15_t)0xd23a, + (q15_t)0x6cb2, (q15_t)0xd231, (q15_t)0x6ca9, (q15_t)0xd229, (q15_t)0x6ca0, (q15_t)0xd220, (q15_t)0x6c97, (q15_t)0xd217, + (q15_t)0x6c8e, (q15_t)0xd20e, (q15_t)0x6c85, (q15_t)0xd206, (q15_t)0x6c7c, (q15_t)0xd1fd, (q15_t)0x6c73, (q15_t)0xd1f4, + (q15_t)0x6c6a, (q15_t)0xd1eb, (q15_t)0x6c61, (q15_t)0xd1e3, (q15_t)0x6c58, (q15_t)0xd1da, (q15_t)0x6c4f, (q15_t)0xd1d1, + (q15_t)0x6c46, (q15_t)0xd1c9, (q15_t)0x6c3d, (q15_t)0xd1c0, (q15_t)0x6c34, (q15_t)0xd1b7, (q15_t)0x6c2b, (q15_t)0xd1af, + (q15_t)0x6c21, (q15_t)0xd1a6, (q15_t)0x6c18, (q15_t)0xd19d, (q15_t)0x6c0f, (q15_t)0xd195, (q15_t)0x6c06, (q15_t)0xd18c, + (q15_t)0x6bfd, (q15_t)0xd183, (q15_t)0x6bf4, (q15_t)0xd17b, (q15_t)0x6beb, (q15_t)0xd172, (q15_t)0x6be2, (q15_t)0xd169, + (q15_t)0x6bd8, (q15_t)0xd161, (q15_t)0x6bcf, (q15_t)0xd158, (q15_t)0x6bc6, (q15_t)0xd150, (q15_t)0x6bbd, (q15_t)0xd147, + (q15_t)0x6bb4, (q15_t)0xd13e, (q15_t)0x6bab, (q15_t)0xd136, (q15_t)0x6ba1, (q15_t)0xd12d, (q15_t)0x6b98, (q15_t)0xd125, + (q15_t)0x6b8f, (q15_t)0xd11c, (q15_t)0x6b86, (q15_t)0xd114, (q15_t)0x6b7d, (q15_t)0xd10b, (q15_t)0x6b73, (q15_t)0xd103, + (q15_t)0x6b6a, (q15_t)0xd0fa, (q15_t)0x6b61, (q15_t)0xd0f2, (q15_t)0x6b58, (q15_t)0xd0e9, (q15_t)0x6b4e, (q15_t)0xd0e0, + (q15_t)0x6b45, (q15_t)0xd0d8, (q15_t)0x6b3c, (q15_t)0xd0d0, (q15_t)0x6b33, (q15_t)0xd0c7, (q15_t)0x6b29, (q15_t)0xd0bf, + (q15_t)0x6b20, (q15_t)0xd0b6, (q15_t)0x6b17, (q15_t)0xd0ae, (q15_t)0x6b0d, (q15_t)0xd0a5, (q15_t)0x6b04, (q15_t)0xd09d, + (q15_t)0x6afb, (q15_t)0xd094, (q15_t)0x6af2, (q15_t)0xd08c, (q15_t)0x6ae8, (q15_t)0xd083, (q15_t)0x6adf, (q15_t)0xd07b, + (q15_t)0x6ad6, (q15_t)0xd073, (q15_t)0x6acc, (q15_t)0xd06a, (q15_t)0x6ac3, (q15_t)0xd062, (q15_t)0x6ab9, (q15_t)0xd059, + (q15_t)0x6ab0, (q15_t)0xd051, (q15_t)0x6aa7, (q15_t)0xd049, (q15_t)0x6a9d, (q15_t)0xd040, (q15_t)0x6a94, (q15_t)0xd038, + (q15_t)0x6a8b, (q15_t)0xd030, (q15_t)0x6a81, (q15_t)0xd027, (q15_t)0x6a78, (q15_t)0xd01f, (q15_t)0x6a6e, (q15_t)0xd016, + (q15_t)0x6a65, (q15_t)0xd00e, (q15_t)0x6a5c, (q15_t)0xd006, (q15_t)0x6a52, (q15_t)0xcffe, (q15_t)0x6a49, (q15_t)0xcff5, + (q15_t)0x6a3f, (q15_t)0xcfed, (q15_t)0x6a36, (q15_t)0xcfe5, (q15_t)0x6a2c, (q15_t)0xcfdc, (q15_t)0x6a23, (q15_t)0xcfd4, + (q15_t)0x6a1a, (q15_t)0xcfcc, (q15_t)0x6a10, (q15_t)0xcfc4, (q15_t)0x6a07, (q15_t)0xcfbb, (q15_t)0x69fd, (q15_t)0xcfb3, + (q15_t)0x69f4, (q15_t)0xcfab, (q15_t)0x69ea, (q15_t)0xcfa3, (q15_t)0x69e1, (q15_t)0xcf9a, (q15_t)0x69d7, (q15_t)0xcf92, + (q15_t)0x69ce, (q15_t)0xcf8a, (q15_t)0x69c4, (q15_t)0xcf82, (q15_t)0x69bb, (q15_t)0xcf79, (q15_t)0x69b1, (q15_t)0xcf71, + (q15_t)0x69a7, (q15_t)0xcf69, (q15_t)0x699e, (q15_t)0xcf61, (q15_t)0x6994, (q15_t)0xcf59, (q15_t)0x698b, (q15_t)0xcf51, + (q15_t)0x6981, (q15_t)0xcf48, (q15_t)0x6978, (q15_t)0xcf40, (q15_t)0x696e, (q15_t)0xcf38, (q15_t)0x6965, (q15_t)0xcf30, + (q15_t)0x695b, (q15_t)0xcf28, (q15_t)0x6951, (q15_t)0xcf20, (q15_t)0x6948, (q15_t)0xcf18, (q15_t)0x693e, (q15_t)0xcf10, + (q15_t)0x6935, (q15_t)0xcf07, (q15_t)0x692b, (q15_t)0xceff, (q15_t)0x6921, (q15_t)0xcef7, (q15_t)0x6918, (q15_t)0xceef, + (q15_t)0x690e, (q15_t)0xcee7, (q15_t)0x6904, (q15_t)0xcedf, (q15_t)0x68fb, (q15_t)0xced7, (q15_t)0x68f1, (q15_t)0xcecf, + (q15_t)0x68e7, (q15_t)0xcec7, (q15_t)0x68de, (q15_t)0xcebf, (q15_t)0x68d4, (q15_t)0xceb7, (q15_t)0x68ca, (q15_t)0xceaf, + (q15_t)0x68c1, (q15_t)0xcea7, (q15_t)0x68b7, (q15_t)0xce9f, (q15_t)0x68ad, (q15_t)0xce97, (q15_t)0x68a4, (q15_t)0xce8f, + (q15_t)0x689a, (q15_t)0xce87, (q15_t)0x6890, (q15_t)0xce7f, (q15_t)0x6886, (q15_t)0xce77, (q15_t)0x687d, (q15_t)0xce6f, + (q15_t)0x6873, (q15_t)0xce67, (q15_t)0x6869, (q15_t)0xce5f, (q15_t)0x6860, (q15_t)0xce57, (q15_t)0x6856, (q15_t)0xce4f, + (q15_t)0x684c, (q15_t)0xce47, (q15_t)0x6842, (q15_t)0xce40, (q15_t)0x6838, (q15_t)0xce38, (q15_t)0x682f, (q15_t)0xce30, + (q15_t)0x6825, (q15_t)0xce28, (q15_t)0x681b, (q15_t)0xce20, (q15_t)0x6811, (q15_t)0xce18, (q15_t)0x6808, (q15_t)0xce10, + (q15_t)0x67fe, (q15_t)0xce08, (q15_t)0x67f4, (q15_t)0xce01, (q15_t)0x67ea, (q15_t)0xcdf9, (q15_t)0x67e0, (q15_t)0xcdf1, + (q15_t)0x67d6, (q15_t)0xcde9, (q15_t)0x67cd, (q15_t)0xcde1, (q15_t)0x67c3, (q15_t)0xcdd9, (q15_t)0x67b9, (q15_t)0xcdd2, + (q15_t)0x67af, (q15_t)0xcdca, (q15_t)0x67a5, (q15_t)0xcdc2, (q15_t)0x679b, (q15_t)0xcdba, (q15_t)0x6791, (q15_t)0xcdb2, + (q15_t)0x6788, (q15_t)0xcdab, (q15_t)0x677e, (q15_t)0xcda3, (q15_t)0x6774, (q15_t)0xcd9b, (q15_t)0x676a, (q15_t)0xcd93, + (q15_t)0x6760, (q15_t)0xcd8c, (q15_t)0x6756, (q15_t)0xcd84, (q15_t)0x674c, (q15_t)0xcd7c, (q15_t)0x6742, (q15_t)0xcd75, + (q15_t)0x6738, (q15_t)0xcd6d, (q15_t)0x672e, (q15_t)0xcd65, (q15_t)0x6724, (q15_t)0xcd5d, (q15_t)0x671a, (q15_t)0xcd56, + (q15_t)0x6711, (q15_t)0xcd4e, (q15_t)0x6707, (q15_t)0xcd46, (q15_t)0x66fd, (q15_t)0xcd3f, (q15_t)0x66f3, (q15_t)0xcd37, + (q15_t)0x66e9, (q15_t)0xcd30, (q15_t)0x66df, (q15_t)0xcd28, (q15_t)0x66d5, (q15_t)0xcd20, (q15_t)0x66cb, (q15_t)0xcd19, + (q15_t)0x66c1, (q15_t)0xcd11, (q15_t)0x66b7, (q15_t)0xcd09, (q15_t)0x66ad, (q15_t)0xcd02, (q15_t)0x66a3, (q15_t)0xccfa, + (q15_t)0x6699, (q15_t)0xccf3, (q15_t)0x668f, (q15_t)0xcceb, (q15_t)0x6685, (q15_t)0xcce3, (q15_t)0x667b, (q15_t)0xccdc, + (q15_t)0x6671, (q15_t)0xccd4, (q15_t)0x6666, (q15_t)0xcccd, (q15_t)0x665c, (q15_t)0xccc5, (q15_t)0x6652, (q15_t)0xccbe, + (q15_t)0x6648, (q15_t)0xccb6, (q15_t)0x663e, (q15_t)0xccaf, (q15_t)0x6634, (q15_t)0xcca7, (q15_t)0x662a, (q15_t)0xcca0, + (q15_t)0x6620, (q15_t)0xcc98, (q15_t)0x6616, (q15_t)0xcc91, (q15_t)0x660c, (q15_t)0xcc89, (q15_t)0x6602, (q15_t)0xcc82, + (q15_t)0x65f8, (q15_t)0xcc7a, (q15_t)0x65ed, (q15_t)0xcc73, (q15_t)0x65e3, (q15_t)0xcc6b, (q15_t)0x65d9, (q15_t)0xcc64, + (q15_t)0x65cf, (q15_t)0xcc5d, (q15_t)0x65c5, (q15_t)0xcc55, (q15_t)0x65bb, (q15_t)0xcc4e, (q15_t)0x65b1, (q15_t)0xcc46, + (q15_t)0x65a6, (q15_t)0xcc3f, (q15_t)0x659c, (q15_t)0xcc38, (q15_t)0x6592, (q15_t)0xcc30, (q15_t)0x6588, (q15_t)0xcc29, + (q15_t)0x657e, (q15_t)0xcc21, (q15_t)0x6574, (q15_t)0xcc1a, (q15_t)0x6569, (q15_t)0xcc13, (q15_t)0x655f, (q15_t)0xcc0b, + (q15_t)0x6555, (q15_t)0xcc04, (q15_t)0x654b, (q15_t)0xcbfd, (q15_t)0x6541, (q15_t)0xcbf5, (q15_t)0x6536, (q15_t)0xcbee, + (q15_t)0x652c, (q15_t)0xcbe7, (q15_t)0x6522, (q15_t)0xcbe0, (q15_t)0x6518, (q15_t)0xcbd8, (q15_t)0x650d, (q15_t)0xcbd1, + (q15_t)0x6503, (q15_t)0xcbca, (q15_t)0x64f9, (q15_t)0xcbc2, (q15_t)0x64ef, (q15_t)0xcbbb, (q15_t)0x64e4, (q15_t)0xcbb4, + (q15_t)0x64da, (q15_t)0xcbad, (q15_t)0x64d0, (q15_t)0xcba5, (q15_t)0x64c5, (q15_t)0xcb9e, (q15_t)0x64bb, (q15_t)0xcb97, + (q15_t)0x64b1, (q15_t)0xcb90, (q15_t)0x64a7, (q15_t)0xcb89, (q15_t)0x649c, (q15_t)0xcb81, (q15_t)0x6492, (q15_t)0xcb7a, + (q15_t)0x6488, (q15_t)0xcb73, (q15_t)0x647d, (q15_t)0xcb6c, (q15_t)0x6473, (q15_t)0xcb65, (q15_t)0x6469, (q15_t)0xcb5e, + (q15_t)0x645e, (q15_t)0xcb56, (q15_t)0x6454, (q15_t)0xcb4f, (q15_t)0x644a, (q15_t)0xcb48, (q15_t)0x643f, (q15_t)0xcb41, + (q15_t)0x6435, (q15_t)0xcb3a, (q15_t)0x642b, (q15_t)0xcb33, (q15_t)0x6420, (q15_t)0xcb2c, (q15_t)0x6416, (q15_t)0xcb25, + (q15_t)0x640b, (q15_t)0xcb1e, (q15_t)0x6401, (q15_t)0xcb16, (q15_t)0x63f7, (q15_t)0xcb0f, (q15_t)0x63ec, (q15_t)0xcb08, + (q15_t)0x63e2, (q15_t)0xcb01, (q15_t)0x63d7, (q15_t)0xcafa, (q15_t)0x63cd, (q15_t)0xcaf3, (q15_t)0x63c3, (q15_t)0xcaec, + (q15_t)0x63b8, (q15_t)0xcae5, (q15_t)0x63ae, (q15_t)0xcade, (q15_t)0x63a3, (q15_t)0xcad7, (q15_t)0x6399, (q15_t)0xcad0, + (q15_t)0x638e, (q15_t)0xcac9, (q15_t)0x6384, (q15_t)0xcac2, (q15_t)0x637a, (q15_t)0xcabb, (q15_t)0x636f, (q15_t)0xcab4, + (q15_t)0x6365, (q15_t)0xcaad, (q15_t)0x635a, (q15_t)0xcaa6, (q15_t)0x6350, (q15_t)0xca9f, (q15_t)0x6345, (q15_t)0xca99, + (q15_t)0x633b, (q15_t)0xca92, (q15_t)0x6330, (q15_t)0xca8b, (q15_t)0x6326, (q15_t)0xca84, (q15_t)0x631b, (q15_t)0xca7d, + (q15_t)0x6311, (q15_t)0xca76, (q15_t)0x6306, (q15_t)0xca6f, (q15_t)0x62fc, (q15_t)0xca68, (q15_t)0x62f1, (q15_t)0xca61, + (q15_t)0x62e7, (q15_t)0xca5b, (q15_t)0x62dc, (q15_t)0xca54, (q15_t)0x62d2, (q15_t)0xca4d, (q15_t)0x62c7, (q15_t)0xca46, + (q15_t)0x62bc, (q15_t)0xca3f, (q15_t)0x62b2, (q15_t)0xca38, (q15_t)0x62a7, (q15_t)0xca32, (q15_t)0x629d, (q15_t)0xca2b, + (q15_t)0x6292, (q15_t)0xca24, (q15_t)0x6288, (q15_t)0xca1d, (q15_t)0x627d, (q15_t)0xca16, (q15_t)0x6272, (q15_t)0xca10, + (q15_t)0x6268, (q15_t)0xca09, (q15_t)0x625d, (q15_t)0xca02, (q15_t)0x6253, (q15_t)0xc9fb, (q15_t)0x6248, (q15_t)0xc9f5, + (q15_t)0x623d, (q15_t)0xc9ee, (q15_t)0x6233, (q15_t)0xc9e7, (q15_t)0x6228, (q15_t)0xc9e0, (q15_t)0x621e, (q15_t)0xc9da, + (q15_t)0x6213, (q15_t)0xc9d3, (q15_t)0x6208, (q15_t)0xc9cc, (q15_t)0x61fe, (q15_t)0xc9c6, (q15_t)0x61f3, (q15_t)0xc9bf, + (q15_t)0x61e8, (q15_t)0xc9b8, (q15_t)0x61de, (q15_t)0xc9b2, (q15_t)0x61d3, (q15_t)0xc9ab, (q15_t)0x61c8, (q15_t)0xc9a4, + (q15_t)0x61be, (q15_t)0xc99e, (q15_t)0x61b3, (q15_t)0xc997, (q15_t)0x61a8, (q15_t)0xc991, (q15_t)0x619e, (q15_t)0xc98a, + (q15_t)0x6193, (q15_t)0xc983, (q15_t)0x6188, (q15_t)0xc97d, (q15_t)0x617d, (q15_t)0xc976, (q15_t)0x6173, (q15_t)0xc970, + (q15_t)0x6168, (q15_t)0xc969, (q15_t)0x615d, (q15_t)0xc963, (q15_t)0x6153, (q15_t)0xc95c, (q15_t)0x6148, (q15_t)0xc955, + (q15_t)0x613d, (q15_t)0xc94f, (q15_t)0x6132, (q15_t)0xc948, (q15_t)0x6128, (q15_t)0xc942, (q15_t)0x611d, (q15_t)0xc93b, + (q15_t)0x6112, (q15_t)0xc935, (q15_t)0x6107, (q15_t)0xc92e, (q15_t)0x60fd, (q15_t)0xc928, (q15_t)0x60f2, (q15_t)0xc921, + (q15_t)0x60e7, (q15_t)0xc91b, (q15_t)0x60dc, (q15_t)0xc915, (q15_t)0x60d1, (q15_t)0xc90e, (q15_t)0x60c7, (q15_t)0xc908, + (q15_t)0x60bc, (q15_t)0xc901, (q15_t)0x60b1, (q15_t)0xc8fb, (q15_t)0x60a6, (q15_t)0xc8f4, (q15_t)0x609b, (q15_t)0xc8ee, + (q15_t)0x6091, (q15_t)0xc8e8, (q15_t)0x6086, (q15_t)0xc8e1, (q15_t)0x607b, (q15_t)0xc8db, (q15_t)0x6070, (q15_t)0xc8d4, + (q15_t)0x6065, (q15_t)0xc8ce, (q15_t)0x605b, (q15_t)0xc8c8, (q15_t)0x6050, (q15_t)0xc8c1, (q15_t)0x6045, (q15_t)0xc8bb, + (q15_t)0x603a, (q15_t)0xc8b5, (q15_t)0x602f, (q15_t)0xc8ae, (q15_t)0x6024, (q15_t)0xc8a8, (q15_t)0x6019, (q15_t)0xc8a2, + (q15_t)0x600f, (q15_t)0xc89b, (q15_t)0x6004, (q15_t)0xc895, (q15_t)0x5ff9, (q15_t)0xc88f, (q15_t)0x5fee, (q15_t)0xc889, + (q15_t)0x5fe3, (q15_t)0xc882, (q15_t)0x5fd8, (q15_t)0xc87c, (q15_t)0x5fcd, (q15_t)0xc876, (q15_t)0x5fc2, (q15_t)0xc870, + (q15_t)0x5fb7, (q15_t)0xc869, (q15_t)0x5fac, (q15_t)0xc863, (q15_t)0x5fa2, (q15_t)0xc85d, (q15_t)0x5f97, (q15_t)0xc857, + (q15_t)0x5f8c, (q15_t)0xc850, (q15_t)0x5f81, (q15_t)0xc84a, (q15_t)0x5f76, (q15_t)0xc844, (q15_t)0x5f6b, (q15_t)0xc83e, + (q15_t)0x5f60, (q15_t)0xc838, (q15_t)0x5f55, (q15_t)0xc832, (q15_t)0x5f4a, (q15_t)0xc82b, (q15_t)0x5f3f, (q15_t)0xc825, + (q15_t)0x5f34, (q15_t)0xc81f, (q15_t)0x5f29, (q15_t)0xc819, (q15_t)0x5f1e, (q15_t)0xc813, (q15_t)0x5f13, (q15_t)0xc80d, + (q15_t)0x5f08, (q15_t)0xc807, (q15_t)0x5efd, (q15_t)0xc801, (q15_t)0x5ef2, (q15_t)0xc7fb, (q15_t)0x5ee7, (q15_t)0xc7f5, + (q15_t)0x5edc, (q15_t)0xc7ee, (q15_t)0x5ed1, (q15_t)0xc7e8, (q15_t)0x5ec6, (q15_t)0xc7e2, (q15_t)0x5ebb, (q15_t)0xc7dc, + (q15_t)0x5eb0, (q15_t)0xc7d6, (q15_t)0x5ea5, (q15_t)0xc7d0, (q15_t)0x5e9a, (q15_t)0xc7ca, (q15_t)0x5e8f, (q15_t)0xc7c4, + (q15_t)0x5e84, (q15_t)0xc7be, (q15_t)0x5e79, (q15_t)0xc7b8, (q15_t)0x5e6e, (q15_t)0xc7b2, (q15_t)0x5e63, (q15_t)0xc7ac, + (q15_t)0x5e58, (q15_t)0xc7a6, (q15_t)0x5e4d, (q15_t)0xc7a0, (q15_t)0x5e42, (q15_t)0xc79a, (q15_t)0x5e36, (q15_t)0xc795, + (q15_t)0x5e2b, (q15_t)0xc78f, (q15_t)0x5e20, (q15_t)0xc789, (q15_t)0x5e15, (q15_t)0xc783, (q15_t)0x5e0a, (q15_t)0xc77d, + (q15_t)0x5dff, (q15_t)0xc777, (q15_t)0x5df4, (q15_t)0xc771, (q15_t)0x5de9, (q15_t)0xc76b, (q15_t)0x5dde, (q15_t)0xc765, + (q15_t)0x5dd3, (q15_t)0xc75f, (q15_t)0x5dc7, (q15_t)0xc75a, (q15_t)0x5dbc, (q15_t)0xc754, (q15_t)0x5db1, (q15_t)0xc74e, + (q15_t)0x5da6, (q15_t)0xc748, (q15_t)0x5d9b, (q15_t)0xc742, (q15_t)0x5d90, (q15_t)0xc73d, (q15_t)0x5d85, (q15_t)0xc737, + (q15_t)0x5d79, (q15_t)0xc731, (q15_t)0x5d6e, (q15_t)0xc72b, (q15_t)0x5d63, (q15_t)0xc725, (q15_t)0x5d58, (q15_t)0xc720, + (q15_t)0x5d4d, (q15_t)0xc71a, (q15_t)0x5d42, (q15_t)0xc714, (q15_t)0x5d36, (q15_t)0xc70e, (q15_t)0x5d2b, (q15_t)0xc709, + (q15_t)0x5d20, (q15_t)0xc703, (q15_t)0x5d15, (q15_t)0xc6fd, (q15_t)0x5d0a, (q15_t)0xc6f7, (q15_t)0x5cff, (q15_t)0xc6f2, + (q15_t)0x5cf3, (q15_t)0xc6ec, (q15_t)0x5ce8, (q15_t)0xc6e6, (q15_t)0x5cdd, (q15_t)0xc6e1, (q15_t)0x5cd2, (q15_t)0xc6db, + (q15_t)0x5cc6, (q15_t)0xc6d5, (q15_t)0x5cbb, (q15_t)0xc6d0, (q15_t)0x5cb0, (q15_t)0xc6ca, (q15_t)0x5ca5, (q15_t)0xc6c5, + (q15_t)0x5c99, (q15_t)0xc6bf, (q15_t)0x5c8e, (q15_t)0xc6b9, (q15_t)0x5c83, (q15_t)0xc6b4, (q15_t)0x5c78, (q15_t)0xc6ae, + (q15_t)0x5c6c, (q15_t)0xc6a8, (q15_t)0x5c61, (q15_t)0xc6a3, (q15_t)0x5c56, (q15_t)0xc69d, (q15_t)0x5c4b, (q15_t)0xc698, + (q15_t)0x5c3f, (q15_t)0xc692, (q15_t)0x5c34, (q15_t)0xc68d, (q15_t)0x5c29, (q15_t)0xc687, (q15_t)0x5c1e, (q15_t)0xc682, + (q15_t)0x5c12, (q15_t)0xc67c, (q15_t)0x5c07, (q15_t)0xc677, (q15_t)0x5bfc, (q15_t)0xc671, (q15_t)0x5bf0, (q15_t)0xc66c, + (q15_t)0x5be5, (q15_t)0xc666, (q15_t)0x5bda, (q15_t)0xc661, (q15_t)0x5bce, (q15_t)0xc65b, (q15_t)0x5bc3, (q15_t)0xc656, + (q15_t)0x5bb8, (q15_t)0xc650, (q15_t)0x5bac, (q15_t)0xc64b, (q15_t)0x5ba1, (q15_t)0xc645, (q15_t)0x5b96, (q15_t)0xc640, + (q15_t)0x5b8a, (q15_t)0xc63b, (q15_t)0x5b7f, (q15_t)0xc635, (q15_t)0x5b74, (q15_t)0xc630, (q15_t)0x5b68, (q15_t)0xc62a, + (q15_t)0x5b5d, (q15_t)0xc625, (q15_t)0x5b52, (q15_t)0xc620, (q15_t)0x5b46, (q15_t)0xc61a, (q15_t)0x5b3b, (q15_t)0xc615, + (q15_t)0x5b30, (q15_t)0xc610, (q15_t)0x5b24, (q15_t)0xc60a, (q15_t)0x5b19, (q15_t)0xc605, (q15_t)0x5b0d, (q15_t)0xc600, + (q15_t)0x5b02, (q15_t)0xc5fa, (q15_t)0x5af7, (q15_t)0xc5f5, (q15_t)0x5aeb, (q15_t)0xc5f0, (q15_t)0x5ae0, (q15_t)0xc5ea, + (q15_t)0x5ad4, (q15_t)0xc5e5, (q15_t)0x5ac9, (q15_t)0xc5e0, (q15_t)0x5abe, (q15_t)0xc5db, (q15_t)0x5ab2, (q15_t)0xc5d5, + (q15_t)0x5aa7, (q15_t)0xc5d0, (q15_t)0x5a9b, (q15_t)0xc5cb, (q15_t)0x5a90, (q15_t)0xc5c6, (q15_t)0x5a84, (q15_t)0xc5c1, + (q15_t)0x5a79, (q15_t)0xc5bb, (q15_t)0x5a6e, (q15_t)0xc5b6, (q15_t)0x5a62, (q15_t)0xc5b1, (q15_t)0x5a57, (q15_t)0xc5ac, + (q15_t)0x5a4b, (q15_t)0xc5a7, (q15_t)0x5a40, (q15_t)0xc5a1, (q15_t)0x5a34, (q15_t)0xc59c, (q15_t)0x5a29, (q15_t)0xc597, + (q15_t)0x5a1d, (q15_t)0xc592, (q15_t)0x5a12, (q15_t)0xc58d, (q15_t)0x5a06, (q15_t)0xc588, (q15_t)0x59fb, (q15_t)0xc583, + (q15_t)0x59ef, (q15_t)0xc57e, (q15_t)0x59e4, (q15_t)0xc578, (q15_t)0x59d8, (q15_t)0xc573, (q15_t)0x59cd, (q15_t)0xc56e, + (q15_t)0x59c1, (q15_t)0xc569, (q15_t)0x59b6, (q15_t)0xc564, (q15_t)0x59aa, (q15_t)0xc55f, (q15_t)0x599f, (q15_t)0xc55a, + (q15_t)0x5993, (q15_t)0xc555, (q15_t)0x5988, (q15_t)0xc550, (q15_t)0x597c, (q15_t)0xc54b, (q15_t)0x5971, (q15_t)0xc546, + (q15_t)0x5965, (q15_t)0xc541, (q15_t)0x595a, (q15_t)0xc53c, (q15_t)0x594e, (q15_t)0xc537, (q15_t)0x5943, (q15_t)0xc532, + (q15_t)0x5937, (q15_t)0xc52d, (q15_t)0x592c, (q15_t)0xc528, (q15_t)0x5920, (q15_t)0xc523, (q15_t)0x5914, (q15_t)0xc51e, + (q15_t)0x5909, (q15_t)0xc51a, (q15_t)0x58fd, (q15_t)0xc515, (q15_t)0x58f2, (q15_t)0xc510, (q15_t)0x58e6, (q15_t)0xc50b, + (q15_t)0x58db, (q15_t)0xc506, (q15_t)0x58cf, (q15_t)0xc501, (q15_t)0x58c3, (q15_t)0xc4fc, (q15_t)0x58b8, (q15_t)0xc4f7, + (q15_t)0x58ac, (q15_t)0xc4f2, (q15_t)0x58a1, (q15_t)0xc4ee, (q15_t)0x5895, (q15_t)0xc4e9, (q15_t)0x5889, (q15_t)0xc4e4, + (q15_t)0x587e, (q15_t)0xc4df, (q15_t)0x5872, (q15_t)0xc4da, (q15_t)0x5867, (q15_t)0xc4d6, (q15_t)0x585b, (q15_t)0xc4d1, + (q15_t)0x584f, (q15_t)0xc4cc, (q15_t)0x5844, (q15_t)0xc4c7, (q15_t)0x5838, (q15_t)0xc4c2, (q15_t)0x582d, (q15_t)0xc4be, + (q15_t)0x5821, (q15_t)0xc4b9, (q15_t)0x5815, (q15_t)0xc4b4, (q15_t)0x580a, (q15_t)0xc4b0, (q15_t)0x57fe, (q15_t)0xc4ab, + (q15_t)0x57f2, (q15_t)0xc4a6, (q15_t)0x57e7, (q15_t)0xc4a1, (q15_t)0x57db, (q15_t)0xc49d, (q15_t)0x57cf, (q15_t)0xc498, + (q15_t)0x57c4, (q15_t)0xc493, (q15_t)0x57b8, (q15_t)0xc48f, (q15_t)0x57ac, (q15_t)0xc48a, (q15_t)0x57a1, (q15_t)0xc485, + (q15_t)0x5795, (q15_t)0xc481, (q15_t)0x5789, (q15_t)0xc47c, (q15_t)0x577e, (q15_t)0xc478, (q15_t)0x5772, (q15_t)0xc473, + (q15_t)0x5766, (q15_t)0xc46e, (q15_t)0x575b, (q15_t)0xc46a, (q15_t)0x574f, (q15_t)0xc465, (q15_t)0x5743, (q15_t)0xc461, + (q15_t)0x5737, (q15_t)0xc45c, (q15_t)0x572c, (q15_t)0xc457, (q15_t)0x5720, (q15_t)0xc453, (q15_t)0x5714, (q15_t)0xc44e, + (q15_t)0x5709, (q15_t)0xc44a, (q15_t)0x56fd, (q15_t)0xc445, (q15_t)0x56f1, (q15_t)0xc441, (q15_t)0x56e5, (q15_t)0xc43c, + (q15_t)0x56da, (q15_t)0xc438, (q15_t)0x56ce, (q15_t)0xc433, (q15_t)0x56c2, (q15_t)0xc42f, (q15_t)0x56b6, (q15_t)0xc42a, + (q15_t)0x56ab, (q15_t)0xc426, (q15_t)0x569f, (q15_t)0xc422, (q15_t)0x5693, (q15_t)0xc41d, (q15_t)0x5687, (q15_t)0xc419, + (q15_t)0x567c, (q15_t)0xc414, (q15_t)0x5670, (q15_t)0xc410, (q15_t)0x5664, (q15_t)0xc40b, (q15_t)0x5658, (q15_t)0xc407, + (q15_t)0x564c, (q15_t)0xc403, (q15_t)0x5641, (q15_t)0xc3fe, (q15_t)0x5635, (q15_t)0xc3fa, (q15_t)0x5629, (q15_t)0xc3f6, + (q15_t)0x561d, (q15_t)0xc3f1, (q15_t)0x5612, (q15_t)0xc3ed, (q15_t)0x5606, (q15_t)0xc3e9, (q15_t)0x55fa, (q15_t)0xc3e4, + (q15_t)0x55ee, (q15_t)0xc3e0, (q15_t)0x55e2, (q15_t)0xc3dc, (q15_t)0x55d7, (q15_t)0xc3d7, (q15_t)0x55cb, (q15_t)0xc3d3, + (q15_t)0x55bf, (q15_t)0xc3cf, (q15_t)0x55b3, (q15_t)0xc3ca, (q15_t)0x55a7, (q15_t)0xc3c6, (q15_t)0x559b, (q15_t)0xc3c2, + (q15_t)0x5590, (q15_t)0xc3be, (q15_t)0x5584, (q15_t)0xc3ba, (q15_t)0x5578, (q15_t)0xc3b5, (q15_t)0x556c, (q15_t)0xc3b1, + (q15_t)0x5560, (q15_t)0xc3ad, (q15_t)0x5554, (q15_t)0xc3a9, (q15_t)0x5549, (q15_t)0xc3a5, (q15_t)0x553d, (q15_t)0xc3a0, + (q15_t)0x5531, (q15_t)0xc39c, (q15_t)0x5525, (q15_t)0xc398, (q15_t)0x5519, (q15_t)0xc394, (q15_t)0x550d, (q15_t)0xc390, + (q15_t)0x5501, (q15_t)0xc38c, (q15_t)0x54f6, (q15_t)0xc387, (q15_t)0x54ea, (q15_t)0xc383, (q15_t)0x54de, (q15_t)0xc37f, + (q15_t)0x54d2, (q15_t)0xc37b, (q15_t)0x54c6, (q15_t)0xc377, (q15_t)0x54ba, (q15_t)0xc373, (q15_t)0x54ae, (q15_t)0xc36f, + (q15_t)0x54a2, (q15_t)0xc36b, (q15_t)0x5496, (q15_t)0xc367, (q15_t)0x548b, (q15_t)0xc363, (q15_t)0x547f, (q15_t)0xc35f, + (q15_t)0x5473, (q15_t)0xc35b, (q15_t)0x5467, (q15_t)0xc357, (q15_t)0x545b, (q15_t)0xc353, (q15_t)0x544f, (q15_t)0xc34f, + (q15_t)0x5443, (q15_t)0xc34b, (q15_t)0x5437, (q15_t)0xc347, (q15_t)0x542b, (q15_t)0xc343, (q15_t)0x541f, (q15_t)0xc33f, + (q15_t)0x5413, (q15_t)0xc33b, (q15_t)0x5407, (q15_t)0xc337, (q15_t)0x53fb, (q15_t)0xc333, (q15_t)0x53f0, (q15_t)0xc32f, + (q15_t)0x53e4, (q15_t)0xc32b, (q15_t)0x53d8, (q15_t)0xc327, (q15_t)0x53cc, (q15_t)0xc323, (q15_t)0x53c0, (q15_t)0xc320, + (q15_t)0x53b4, (q15_t)0xc31c, (q15_t)0x53a8, (q15_t)0xc318, (q15_t)0x539c, (q15_t)0xc314, (q15_t)0x5390, (q15_t)0xc310, + (q15_t)0x5384, (q15_t)0xc30c, (q15_t)0x5378, (q15_t)0xc308, (q15_t)0x536c, (q15_t)0xc305, (q15_t)0x5360, (q15_t)0xc301, + (q15_t)0x5354, (q15_t)0xc2fd, (q15_t)0x5348, (q15_t)0xc2f9, (q15_t)0x533c, (q15_t)0xc2f5, (q15_t)0x5330, (q15_t)0xc2f2, + (q15_t)0x5324, (q15_t)0xc2ee, (q15_t)0x5318, (q15_t)0xc2ea, (q15_t)0x530c, (q15_t)0xc2e6, (q15_t)0x5300, (q15_t)0xc2e3, + (q15_t)0x52f4, (q15_t)0xc2df, (q15_t)0x52e8, (q15_t)0xc2db, (q15_t)0x52dc, (q15_t)0xc2d8, (q15_t)0x52d0, (q15_t)0xc2d4, + (q15_t)0x52c4, (q15_t)0xc2d0, (q15_t)0x52b8, (q15_t)0xc2cc, (q15_t)0x52ac, (q15_t)0xc2c9, (q15_t)0x52a0, (q15_t)0xc2c5, + (q15_t)0x5294, (q15_t)0xc2c1, (q15_t)0x5288, (q15_t)0xc2be, (q15_t)0x527c, (q15_t)0xc2ba, (q15_t)0x5270, (q15_t)0xc2b7, + (q15_t)0x5264, (q15_t)0xc2b3, (q15_t)0x5258, (q15_t)0xc2af, (q15_t)0x524c, (q15_t)0xc2ac, (q15_t)0x5240, (q15_t)0xc2a8, + (q15_t)0x5234, (q15_t)0xc2a5, (q15_t)0x5228, (q15_t)0xc2a1, (q15_t)0x521c, (q15_t)0xc29d, (q15_t)0x5210, (q15_t)0xc29a, + (q15_t)0x5204, (q15_t)0xc296, (q15_t)0x51f7, (q15_t)0xc293, (q15_t)0x51eb, (q15_t)0xc28f, (q15_t)0x51df, (q15_t)0xc28c, + (q15_t)0x51d3, (q15_t)0xc288, (q15_t)0x51c7, (q15_t)0xc285, (q15_t)0x51bb, (q15_t)0xc281, (q15_t)0x51af, (q15_t)0xc27e, + (q15_t)0x51a3, (q15_t)0xc27a, (q15_t)0x5197, (q15_t)0xc277, (q15_t)0x518b, (q15_t)0xc273, (q15_t)0x517f, (q15_t)0xc270, + (q15_t)0x5173, (q15_t)0xc26d, (q15_t)0x5167, (q15_t)0xc269, (q15_t)0x515a, (q15_t)0xc266, (q15_t)0x514e, (q15_t)0xc262, + (q15_t)0x5142, (q15_t)0xc25f, (q15_t)0x5136, (q15_t)0xc25c, (q15_t)0x512a, (q15_t)0xc258, (q15_t)0x511e, (q15_t)0xc255, + (q15_t)0x5112, (q15_t)0xc251, (q15_t)0x5106, (q15_t)0xc24e, (q15_t)0x50fa, (q15_t)0xc24b, (q15_t)0x50ed, (q15_t)0xc247, + (q15_t)0x50e1, (q15_t)0xc244, (q15_t)0x50d5, (q15_t)0xc241, (q15_t)0x50c9, (q15_t)0xc23e, (q15_t)0x50bd, (q15_t)0xc23a, + (q15_t)0x50b1, (q15_t)0xc237, (q15_t)0x50a5, (q15_t)0xc234, (q15_t)0x5099, (q15_t)0xc230, (q15_t)0x508c, (q15_t)0xc22d, + (q15_t)0x5080, (q15_t)0xc22a, (q15_t)0x5074, (q15_t)0xc227, (q15_t)0x5068, (q15_t)0xc223, (q15_t)0x505c, (q15_t)0xc220, + (q15_t)0x5050, (q15_t)0xc21d, (q15_t)0x5044, (q15_t)0xc21a, (q15_t)0x5037, (q15_t)0xc217, (q15_t)0x502b, (q15_t)0xc213, + (q15_t)0x501f, (q15_t)0xc210, (q15_t)0x5013, (q15_t)0xc20d, (q15_t)0x5007, (q15_t)0xc20a, (q15_t)0x4ffb, (q15_t)0xc207, + (q15_t)0x4fee, (q15_t)0xc204, (q15_t)0x4fe2, (q15_t)0xc201, (q15_t)0x4fd6, (q15_t)0xc1fd, (q15_t)0x4fca, (q15_t)0xc1fa, + (q15_t)0x4fbe, (q15_t)0xc1f7, (q15_t)0x4fb2, (q15_t)0xc1f4, (q15_t)0x4fa5, (q15_t)0xc1f1, (q15_t)0x4f99, (q15_t)0xc1ee, + (q15_t)0x4f8d, (q15_t)0xc1eb, (q15_t)0x4f81, (q15_t)0xc1e8, (q15_t)0x4f75, (q15_t)0xc1e5, (q15_t)0x4f68, (q15_t)0xc1e2, + (q15_t)0x4f5c, (q15_t)0xc1df, (q15_t)0x4f50, (q15_t)0xc1dc, (q15_t)0x4f44, (q15_t)0xc1d9, (q15_t)0x4f38, (q15_t)0xc1d6, + (q15_t)0x4f2b, (q15_t)0xc1d3, (q15_t)0x4f1f, (q15_t)0xc1d0, (q15_t)0x4f13, (q15_t)0xc1cd, (q15_t)0x4f07, (q15_t)0xc1ca, + (q15_t)0x4efb, (q15_t)0xc1c7, (q15_t)0x4eee, (q15_t)0xc1c4, (q15_t)0x4ee2, (q15_t)0xc1c1, (q15_t)0x4ed6, (q15_t)0xc1be, + (q15_t)0x4eca, (q15_t)0xc1bb, (q15_t)0x4ebd, (q15_t)0xc1b8, (q15_t)0x4eb1, (q15_t)0xc1b6, (q15_t)0x4ea5, (q15_t)0xc1b3, + (q15_t)0x4e99, (q15_t)0xc1b0, (q15_t)0x4e8c, (q15_t)0xc1ad, (q15_t)0x4e80, (q15_t)0xc1aa, (q15_t)0x4e74, (q15_t)0xc1a7, + (q15_t)0x4e68, (q15_t)0xc1a4, (q15_t)0x4e5c, (q15_t)0xc1a2, (q15_t)0x4e4f, (q15_t)0xc19f, (q15_t)0x4e43, (q15_t)0xc19c, + (q15_t)0x4e37, (q15_t)0xc199, (q15_t)0x4e2b, (q15_t)0xc196, (q15_t)0x4e1e, (q15_t)0xc194, (q15_t)0x4e12, (q15_t)0xc191, + (q15_t)0x4e06, (q15_t)0xc18e, (q15_t)0x4df9, (q15_t)0xc18b, (q15_t)0x4ded, (q15_t)0xc189, (q15_t)0x4de1, (q15_t)0xc186, + (q15_t)0x4dd5, (q15_t)0xc183, (q15_t)0x4dc8, (q15_t)0xc180, (q15_t)0x4dbc, (q15_t)0xc17e, (q15_t)0x4db0, (q15_t)0xc17b, + (q15_t)0x4da4, (q15_t)0xc178, (q15_t)0x4d97, (q15_t)0xc176, (q15_t)0x4d8b, (q15_t)0xc173, (q15_t)0x4d7f, (q15_t)0xc170, + (q15_t)0x4d72, (q15_t)0xc16e, (q15_t)0x4d66, (q15_t)0xc16b, (q15_t)0x4d5a, (q15_t)0xc168, (q15_t)0x4d4e, (q15_t)0xc166, + (q15_t)0x4d41, (q15_t)0xc163, (q15_t)0x4d35, (q15_t)0xc161, (q15_t)0x4d29, (q15_t)0xc15e, (q15_t)0x4d1c, (q15_t)0xc15b, + (q15_t)0x4d10, (q15_t)0xc159, (q15_t)0x4d04, (q15_t)0xc156, (q15_t)0x4cf8, (q15_t)0xc154, (q15_t)0x4ceb, (q15_t)0xc151, + (q15_t)0x4cdf, (q15_t)0xc14f, (q15_t)0x4cd3, (q15_t)0xc14c, (q15_t)0x4cc6, (q15_t)0xc14a, (q15_t)0x4cba, (q15_t)0xc147, + (q15_t)0x4cae, (q15_t)0xc145, (q15_t)0x4ca1, (q15_t)0xc142, (q15_t)0x4c95, (q15_t)0xc140, (q15_t)0x4c89, (q15_t)0xc13d, + (q15_t)0x4c7c, (q15_t)0xc13b, (q15_t)0x4c70, (q15_t)0xc138, (q15_t)0x4c64, (q15_t)0xc136, (q15_t)0x4c57, (q15_t)0xc134, + (q15_t)0x4c4b, (q15_t)0xc131, (q15_t)0x4c3f, (q15_t)0xc12f, (q15_t)0x4c32, (q15_t)0xc12c, (q15_t)0x4c26, (q15_t)0xc12a, + (q15_t)0x4c1a, (q15_t)0xc128, (q15_t)0x4c0d, (q15_t)0xc125, (q15_t)0x4c01, (q15_t)0xc123, (q15_t)0x4bf5, (q15_t)0xc120, + (q15_t)0x4be8, (q15_t)0xc11e, (q15_t)0x4bdc, (q15_t)0xc11c, (q15_t)0x4bd0, (q15_t)0xc119, (q15_t)0x4bc3, (q15_t)0xc117, + (q15_t)0x4bb7, (q15_t)0xc115, (q15_t)0x4bab, (q15_t)0xc113, (q15_t)0x4b9e, (q15_t)0xc110, (q15_t)0x4b92, (q15_t)0xc10e, + (q15_t)0x4b85, (q15_t)0xc10c, (q15_t)0x4b79, (q15_t)0xc109, (q15_t)0x4b6d, (q15_t)0xc107, (q15_t)0x4b60, (q15_t)0xc105, + (q15_t)0x4b54, (q15_t)0xc103, (q15_t)0x4b48, (q15_t)0xc100, (q15_t)0x4b3b, (q15_t)0xc0fe, (q15_t)0x4b2f, (q15_t)0xc0fc, + (q15_t)0x4b23, (q15_t)0xc0fa, (q15_t)0x4b16, (q15_t)0xc0f8, (q15_t)0x4b0a, (q15_t)0xc0f6, (q15_t)0x4afd, (q15_t)0xc0f3, + (q15_t)0x4af1, (q15_t)0xc0f1, (q15_t)0x4ae5, (q15_t)0xc0ef, (q15_t)0x4ad8, (q15_t)0xc0ed, (q15_t)0x4acc, (q15_t)0xc0eb, + (q15_t)0x4ac0, (q15_t)0xc0e9, (q15_t)0x4ab3, (q15_t)0xc0e7, (q15_t)0x4aa7, (q15_t)0xc0e4, (q15_t)0x4a9a, (q15_t)0xc0e2, + (q15_t)0x4a8e, (q15_t)0xc0e0, (q15_t)0x4a82, (q15_t)0xc0de, (q15_t)0x4a75, (q15_t)0xc0dc, (q15_t)0x4a69, (q15_t)0xc0da, + (q15_t)0x4a5c, (q15_t)0xc0d8, (q15_t)0x4a50, (q15_t)0xc0d6, (q15_t)0x4a44, (q15_t)0xc0d4, (q15_t)0x4a37, (q15_t)0xc0d2, + (q15_t)0x4a2b, (q15_t)0xc0d0, (q15_t)0x4a1e, (q15_t)0xc0ce, (q15_t)0x4a12, (q15_t)0xc0cc, (q15_t)0x4a06, (q15_t)0xc0ca, + (q15_t)0x49f9, (q15_t)0xc0c8, (q15_t)0x49ed, (q15_t)0xc0c6, (q15_t)0x49e0, (q15_t)0xc0c4, (q15_t)0x49d4, (q15_t)0xc0c2, + (q15_t)0x49c7, (q15_t)0xc0c0, (q15_t)0x49bb, (q15_t)0xc0be, (q15_t)0x49af, (q15_t)0xc0bd, (q15_t)0x49a2, (q15_t)0xc0bb, + (q15_t)0x4996, (q15_t)0xc0b9, (q15_t)0x4989, (q15_t)0xc0b7, (q15_t)0x497d, (q15_t)0xc0b5, (q15_t)0x4970, (q15_t)0xc0b3, + (q15_t)0x4964, (q15_t)0xc0b1, (q15_t)0x4958, (q15_t)0xc0af, (q15_t)0x494b, (q15_t)0xc0ae, (q15_t)0x493f, (q15_t)0xc0ac, + (q15_t)0x4932, (q15_t)0xc0aa, (q15_t)0x4926, (q15_t)0xc0a8, (q15_t)0x4919, (q15_t)0xc0a6, (q15_t)0x490d, (q15_t)0xc0a5, + (q15_t)0x4901, (q15_t)0xc0a3, (q15_t)0x48f4, (q15_t)0xc0a1, (q15_t)0x48e8, (q15_t)0xc09f, (q15_t)0x48db, (q15_t)0xc09e, + (q15_t)0x48cf, (q15_t)0xc09c, (q15_t)0x48c2, (q15_t)0xc09a, (q15_t)0x48b6, (q15_t)0xc098, (q15_t)0x48a9, (q15_t)0xc097, + (q15_t)0x489d, (q15_t)0xc095, (q15_t)0x4891, (q15_t)0xc093, (q15_t)0x4884, (q15_t)0xc092, (q15_t)0x4878, (q15_t)0xc090, + (q15_t)0x486b, (q15_t)0xc08e, (q15_t)0x485f, (q15_t)0xc08d, (q15_t)0x4852, (q15_t)0xc08b, (q15_t)0x4846, (q15_t)0xc089, + (q15_t)0x4839, (q15_t)0xc088, (q15_t)0x482d, (q15_t)0xc086, (q15_t)0x4820, (q15_t)0xc085, (q15_t)0x4814, (q15_t)0xc083, + (q15_t)0x4807, (q15_t)0xc081, (q15_t)0x47fb, (q15_t)0xc080, (q15_t)0x47ef, (q15_t)0xc07e, (q15_t)0x47e2, (q15_t)0xc07d, + (q15_t)0x47d6, (q15_t)0xc07b, (q15_t)0x47c9, (q15_t)0xc07a, (q15_t)0x47bd, (q15_t)0xc078, (q15_t)0x47b0, (q15_t)0xc077, + (q15_t)0x47a4, (q15_t)0xc075, (q15_t)0x4797, (q15_t)0xc074, (q15_t)0x478b, (q15_t)0xc072, (q15_t)0x477e, (q15_t)0xc071, + (q15_t)0x4772, (q15_t)0xc06f, (q15_t)0x4765, (q15_t)0xc06e, (q15_t)0x4759, (q15_t)0xc06c, (q15_t)0x474c, (q15_t)0xc06b, + (q15_t)0x4740, (q15_t)0xc069, (q15_t)0x4733, (q15_t)0xc068, (q15_t)0x4727, (q15_t)0xc067, (q15_t)0x471a, (q15_t)0xc065, + (q15_t)0x470e, (q15_t)0xc064, (q15_t)0x4701, (q15_t)0xc062, (q15_t)0x46f5, (q15_t)0xc061, (q15_t)0x46e8, (q15_t)0xc060, + (q15_t)0x46dc, (q15_t)0xc05e, (q15_t)0x46cf, (q15_t)0xc05d, (q15_t)0x46c3, (q15_t)0xc05c, (q15_t)0x46b6, (q15_t)0xc05a, + (q15_t)0x46aa, (q15_t)0xc059, (q15_t)0x469d, (q15_t)0xc058, (q15_t)0x4691, (q15_t)0xc056, (q15_t)0x4684, (q15_t)0xc055, + (q15_t)0x4678, (q15_t)0xc054, (q15_t)0x466b, (q15_t)0xc053, (q15_t)0x465f, (q15_t)0xc051, (q15_t)0x4652, (q15_t)0xc050, + (q15_t)0x4646, (q15_t)0xc04f, (q15_t)0x4639, (q15_t)0xc04e, (q15_t)0x462d, (q15_t)0xc04c, (q15_t)0x4620, (q15_t)0xc04b, + (q15_t)0x4614, (q15_t)0xc04a, (q15_t)0x4607, (q15_t)0xc049, (q15_t)0x45fb, (q15_t)0xc048, (q15_t)0x45ee, (q15_t)0xc047, + (q15_t)0x45e2, (q15_t)0xc045, (q15_t)0x45d5, (q15_t)0xc044, (q15_t)0x45c9, (q15_t)0xc043, (q15_t)0x45bc, (q15_t)0xc042, + (q15_t)0x45b0, (q15_t)0xc041, (q15_t)0x45a3, (q15_t)0xc040, (q15_t)0x4597, (q15_t)0xc03f, (q15_t)0x458a, (q15_t)0xc03d, + (q15_t)0x457e, (q15_t)0xc03c, (q15_t)0x4571, (q15_t)0xc03b, (q15_t)0x4565, (q15_t)0xc03a, (q15_t)0x4558, (q15_t)0xc039, + (q15_t)0x454c, (q15_t)0xc038, (q15_t)0x453f, (q15_t)0xc037, (q15_t)0x4533, (q15_t)0xc036, (q15_t)0x4526, (q15_t)0xc035, + (q15_t)0x451a, (q15_t)0xc034, (q15_t)0x450d, (q15_t)0xc033, (q15_t)0x4500, (q15_t)0xc032, (q15_t)0x44f4, (q15_t)0xc031, + (q15_t)0x44e7, (q15_t)0xc030, (q15_t)0x44db, (q15_t)0xc02f, (q15_t)0x44ce, (q15_t)0xc02e, (q15_t)0x44c2, (q15_t)0xc02d, + (q15_t)0x44b5, (q15_t)0xc02c, (q15_t)0x44a9, (q15_t)0xc02b, (q15_t)0x449c, (q15_t)0xc02b, (q15_t)0x4490, (q15_t)0xc02a, + (q15_t)0x4483, (q15_t)0xc029, (q15_t)0x4477, (q15_t)0xc028, (q15_t)0x446a, (q15_t)0xc027, (q15_t)0x445e, (q15_t)0xc026, + (q15_t)0x4451, (q15_t)0xc025, (q15_t)0x4444, (q15_t)0xc024, (q15_t)0x4438, (q15_t)0xc024, (q15_t)0x442b, (q15_t)0xc023, + (q15_t)0x441f, (q15_t)0xc022, (q15_t)0x4412, (q15_t)0xc021, (q15_t)0x4406, (q15_t)0xc020, (q15_t)0x43f9, (q15_t)0xc020, + (q15_t)0x43ed, (q15_t)0xc01f, (q15_t)0x43e0, (q15_t)0xc01e, (q15_t)0x43d4, (q15_t)0xc01d, (q15_t)0x43c7, (q15_t)0xc01d, + (q15_t)0x43bb, (q15_t)0xc01c, (q15_t)0x43ae, (q15_t)0xc01b, (q15_t)0x43a1, (q15_t)0xc01a, (q15_t)0x4395, (q15_t)0xc01a, + (q15_t)0x4388, (q15_t)0xc019, (q15_t)0x437c, (q15_t)0xc018, (q15_t)0x436f, (q15_t)0xc018, (q15_t)0x4363, (q15_t)0xc017, + (q15_t)0x4356, (q15_t)0xc016, (q15_t)0x434a, (q15_t)0xc016, (q15_t)0x433d, (q15_t)0xc015, (q15_t)0x4330, (q15_t)0xc014, + (q15_t)0x4324, (q15_t)0xc014, (q15_t)0x4317, (q15_t)0xc013, (q15_t)0x430b, (q15_t)0xc013, (q15_t)0x42fe, (q15_t)0xc012, + (q15_t)0x42f2, (q15_t)0xc011, (q15_t)0x42e5, (q15_t)0xc011, (q15_t)0x42d9, (q15_t)0xc010, (q15_t)0x42cc, (q15_t)0xc010, + (q15_t)0x42c0, (q15_t)0xc00f, (q15_t)0x42b3, (q15_t)0xc00f, (q15_t)0x42a6, (q15_t)0xc00e, (q15_t)0x429a, (q15_t)0xc00e, + (q15_t)0x428d, (q15_t)0xc00d, (q15_t)0x4281, (q15_t)0xc00d, (q15_t)0x4274, (q15_t)0xc00c, (q15_t)0x4268, (q15_t)0xc00c, + (q15_t)0x425b, (q15_t)0xc00b, (q15_t)0x424e, (q15_t)0xc00b, (q15_t)0x4242, (q15_t)0xc00a, (q15_t)0x4235, (q15_t)0xc00a, + (q15_t)0x4229, (q15_t)0xc009, (q15_t)0x421c, (q15_t)0xc009, (q15_t)0x4210, (q15_t)0xc009, (q15_t)0x4203, (q15_t)0xc008, + (q15_t)0x41f7, (q15_t)0xc008, (q15_t)0x41ea, (q15_t)0xc007, (q15_t)0x41dd, (q15_t)0xc007, (q15_t)0x41d1, (q15_t)0xc007, + (q15_t)0x41c4, (q15_t)0xc006, (q15_t)0x41b8, (q15_t)0xc006, (q15_t)0x41ab, (q15_t)0xc006, (q15_t)0x419f, (q15_t)0xc005, + (q15_t)0x4192, (q15_t)0xc005, (q15_t)0x4186, (q15_t)0xc005, (q15_t)0x4179, (q15_t)0xc004, (q15_t)0x416c, (q15_t)0xc004, + (q15_t)0x4160, (q15_t)0xc004, (q15_t)0x4153, (q15_t)0xc004, (q15_t)0x4147, (q15_t)0xc003, (q15_t)0x413a, (q15_t)0xc003, + (q15_t)0x412e, (q15_t)0xc003, (q15_t)0x4121, (q15_t)0xc003, (q15_t)0x4114, (q15_t)0xc002, (q15_t)0x4108, (q15_t)0xc002, + (q15_t)0x40fb, (q15_t)0xc002, (q15_t)0x40ef, (q15_t)0xc002, (q15_t)0x40e2, (q15_t)0xc002, (q15_t)0x40d6, (q15_t)0xc001, + (q15_t)0x40c9, (q15_t)0xc001, (q15_t)0x40bc, (q15_t)0xc001, (q15_t)0x40b0, (q15_t)0xc001, (q15_t)0x40a3, (q15_t)0xc001, + (q15_t)0x4097, (q15_t)0xc001, (q15_t)0x408a, (q15_t)0xc001, (q15_t)0x407e, (q15_t)0xc000, (q15_t)0x4071, (q15_t)0xc000, + (q15_t)0x4065, (q15_t)0xc000, (q15_t)0x4058, (q15_t)0xc000, (q15_t)0x404b, (q15_t)0xc000, (q15_t)0x403f, (q15_t)0xc000, + (q15_t)0x4032, (q15_t)0xc000, (q15_t)0x4026, (q15_t)0xc000, (q15_t)0x4019, (q15_t)0xc000, (q15_t)0x400d, (q15_t)0xc000, +}; + +#endif +/** + @} end of RealFFT_Table group + */ + +/** + @ingroup DCT4_IDCT4 + */ + +/** + @addtogroup DCT4_IDCT4_Table DCT Type IV Tables + @{ + */ + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos (i*c);
+    weights[(2*i)+1] = -sin (i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + @par + 
 for(i = 0; i< N; i++)
+  {
+     cos_factors[i]= 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) +*/ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + const float32_t Weights_128[256] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f, -0.012271538285719925f, + 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f, -0.036807222941358832f, + 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f, -0.061320736302208578f, + 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f, -0.085797312344439894f, + 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f, -0.110222207293883060f, + 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f, -0.134580708507126170f, + 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f, -0.158858143333861450f, + 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f, -0.183039887955140950f, + 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f, -0.207111376192218560f, + 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f, -0.231058108280671110f, + 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f, -0.254865659604514570f, + 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f, -0.278519689385053060f, + 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f, -0.302005949319228080f, + 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f, -0.325310292162262930f, + 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f, -0.348418680249434560f, + 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f, -0.371317193951837540f, + 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f, -0.393992040061048100f, + 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f, -0.416429560097637150f, + 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f, -0.438616238538527660f, + 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f, -0.460538710958240010f, + 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f, -0.482183772079122720f, + 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f, -0.503538383725717580f, + 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f, -0.524589682678468950f, + 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f, -0.545324988422046460f, + 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f, -0.565731810783613120f, + 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f, -0.585797857456438860f, + 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f, -0.605511041404325550f, + 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f, -0.624859488142386340f, + 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f, -0.643831542889791390f, + 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f, -0.662415777590171780f, + 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f, -0.680600997795453020f, + 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f, -0.698376249408972920f, + 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f, -0.715730825283818590f, + 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f, -0.732654271672412820f, + 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f, -0.749136394523459260f, + 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f, -0.765167265622458960f, + 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f, -0.780737228572094380f, + 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f, -0.795836904608883460f, + 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f, -0.810457198252594770f, + 0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f, -0.824589302785025290f, + 0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f, -0.838224705554837970f, + 0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f, -0.851355193105265200f, + 0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f, -0.863972856121586700f, + 0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f, -0.876070094195406600f, + 0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f, -0.887639620402853930f, + 0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f, -0.898674465693953820f, + 0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f, -0.909167983090522270f, + 0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f, -0.919113851690057770f, + 0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f, -0.928506080473215480f, + 0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f, -0.937339011912574960f, + 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f, -0.945607325380521280f, + 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f, -0.953306040354193750f, + 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f, -0.960430519415565790f, + 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f, -0.966976471044852070f, + 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f, -0.972939952205560070f, + 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f, -0.978317370719627650f, + 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f, -0.983105487431216290f, + 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f, -0.987301418157858430f, + 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f, -0.990902635427780010f, + 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f, -0.993906970002356060f, + 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f, -0.996312612182778000f, + 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f, -0.998118112900149180f, + 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f, -0.999322384588349540f, + 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f, -0.999924701839144500f +}; + + const float32_t cos_factors_128[128] = { + 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f, + 0.999077727752645360f, + 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f, + 0.995767414467659820f, + 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f, + 0.990058210262297120f, + 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f, + 0.981963869109555240f, + 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f, + 0.971503890986251780f, + 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f, + 0.958703474895871600f, + 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f, + 0.943593458161960390f, + 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f, + 0.926210242138311380f, + 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f, + 0.906595704514915330f, + 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f, + 0.884797098430937790f, + 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f, + 0.860866938637767310f, + 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f, + 0.834862874986380010f, + 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f, + 0.806847553543799330f, + 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f, + 0.776888465673232440f, + 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f, + 0.745057785441466060f, + 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f, + 0.711432195745216430f, + 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f, + 0.676092703575316030f, + 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f, + 0.639124444863775730f, + 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f, + 0.600616479383868970f, + 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f, + 0.560661576197336030f, + 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f, + 0.519355990165589530f, + 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f, + 0.476799230063322250f, + 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f, + 0.433093818853152010f, + 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f, + 0.388345046698826300f, + 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f, + 0.342660717311994380f, + 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f, + 0.296150888243623960f, + 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f, + 0.248927605745720260f, + 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f, + 0.201104634842091960f, + 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f, + 0.152797185258443410f, + 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f, + 0.104121633872054730f, + 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f, + 0.055195244349690031f, + 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f, + 0.006135884649154515f +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + const float32_t Weights_512[1024] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f, -0.003067956762965976f, + 0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f, -0.009203754782059819f, + 0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f, -0.015339206284988100f, + 0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f, -0.021474080275469508f, + 0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f, -0.027608145778965740f, + 0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f, -0.033741171851377580f, + 0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f, -0.039872927587739811f, + 0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f, -0.046003182130914623f, + 0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f, -0.052131704680283324f, + 0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f, -0.058258264500435752f, + 0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f, -0.064382630929857465f, + 0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f, -0.070504573389613856f, + 0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f, -0.076623861392031492f, + 0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f, -0.082740264549375692f, + 0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f, -0.088853552582524600f, + 0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f, -0.094963495329638992f, + 0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f, -0.101069862754827820f, + 0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f, -0.107172424956808840f, + 0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f, -0.113270952177564350f, + 0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f, -0.119365214810991350f, + 0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f, -0.125454983411546230f, + 0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f, -0.131540028702883120f, + 0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f, -0.137620121586486040f, + 0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f, -0.143695033150294470f, + 0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f, -0.149764534677321510f, + 0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f, -0.155828397654265230f, + 0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f, -0.161886393780111830f, + 0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f, -0.167938294974731170f, + 0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f, -0.173983873387463820f, + 0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f, -0.180022901405699510f, + 0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f, -0.186055151663446630f, + 0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f, -0.192080397049892440f, + 0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f, -0.198098410717953560f, + 0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f, -0.204108966092816870f, + 0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f, -0.210111836880469610f, + 0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f, -0.216106797076219520f, + 0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f, -0.222093620973203510f, + 0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f, -0.228072083170885730f, + 0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f, -0.234041958583543430f, + 0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f, -0.240003022448741500f, + 0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f, -0.245955050335794590f, + 0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f, -0.251897818154216970f, + 0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f, -0.257831102162158990f, + 0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f, -0.263754678974831350f, + 0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f, -0.269668325572915090f, + 0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f, -0.275571819310958140f, + 0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f, -0.281464937925757940f, + 0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f, -0.287347459544729510f, + 0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f, -0.293219162694258630f, + 0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f, -0.299079826308040480f, + 0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f, -0.304929229735402370f, + 0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f, -0.310767152749611470f, + 0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f, -0.316593375556165850f, + 0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f, -0.322407678801069850f, + 0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f, -0.328209843579092500f, + 0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f, -0.333999651442009380f, + 0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f, -0.339776884406826850f, + 0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f, -0.345541324963989090f, + 0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f, -0.351292756085567090f, + 0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f, -0.357030961233429980f, + 0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f, -0.362755724367397230f, + 0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f, -0.368466829953372320f, + 0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f, -0.374164062971457930f, + 0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f, -0.379847208924051160f, + 0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f, -0.385516053843918850f, + 0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f, -0.391170384302253870f, + 0.919113851690057770f, -0.393992040061048100f, 0.917900775621390500f, -0.396809987416710310f, + 0.916679059921042700f, -0.399624199845646790f, 0.915448716088267830f, -0.402434650859418430f, + 0.914209755703530690f, -0.405241314004989860f, 0.912962190428398210f, -0.408044162864978690f, + 0.911706032005429880f, -0.410843171057903910f, 0.910441292258067250f, -0.413638312238434500f, + 0.909167983090522380f, -0.416429560097637150f, 0.907886116487666260f, -0.419216888363223910f, + 0.906595704514915330f, -0.422000270799799680f, 0.905296759318118820f, -0.424779681209108810f, + 0.903989293123443340f, -0.427555093430282080f, 0.902673318237258830f, -0.430326481340082610f, + 0.901348847046022030f, -0.433093818853151960f, 0.900015892016160280f, -0.435857079922255470f, + 0.898674465693953820f, -0.438616238538527660f, 0.897324580705418320f, -0.441371268731716670f, + 0.895966249756185220f, -0.444122144570429200f, 0.894599485631382700f, -0.446868840162374160f, + 0.893224301195515320f, -0.449611329654606540f, 0.891840709392342720f, -0.452349587233770890f, + 0.890448723244757880f, -0.455083587126343840f, 0.889048355854664570f, -0.457813303598877170f, + 0.887639620402853930f, -0.460538710958240010f, 0.886222530148880640f, -0.463259783551860150f, + 0.884797098430937790f, -0.465976495767966180f, 0.883363338665731580f, -0.468688822035827900f, + 0.881921264348355050f, -0.471396736825997640f, 0.880470889052160750f, -0.474100214650549970f, + 0.879012226428633530f, -0.476799230063322090f, 0.877545290207261350f, -0.479493757660153010f, + 0.876070094195406600f, -0.482183772079122720f, 0.874586652278176110f, -0.484869248000791060f, + 0.873094978418290090f, -0.487550160148436000f, 0.871595086655950980f, -0.490226483288291160f, + 0.870086991108711460f, -0.492898192229784040f, 0.868570705971340900f, -0.495565261825772540f, + 0.867046245515692650f, -0.498227666972781870f, 0.865513624090569090f, -0.500885382611240710f, + 0.863972856121586810f, -0.503538383725717580f, 0.862423956111040610f, -0.506186645345155230f, + 0.860866938637767310f, -0.508830142543106990f, 0.859301818357008470f, -0.511468850437970300f, + 0.857728610000272120f, -0.514102744193221660f, 0.856147328375194470f, -0.516731799017649870f, + 0.854557988365400530f, -0.519355990165589640f, 0.852960604930363630f, -0.521975292937154390f, + 0.851355193105265200f, -0.524589682678468950f, 0.849741768000852550f, -0.527199134781901280f, + 0.848120344803297230f, -0.529803624686294610f, 0.846490938774052130f, -0.532403127877197900f, + 0.844853565249707120f, -0.534997619887097150f, 0.843208239641845440f, -0.537587076295645390f, + 0.841554977436898440f, -0.540171472729892850f, 0.839893794195999520f, -0.542750784864515890f, + 0.838224705554838080f, -0.545324988422046460f, 0.836547727223512010f, -0.547894059173100190f, + 0.834862874986380010f, -0.550457972936604810f, 0.833170164701913190f, -0.553016705580027470f, + 0.831469612302545240f, -0.555570233019602180f, 0.829761233794523050f, -0.558118531220556100f, + 0.828045045257755800f, -0.560661576197336030f, 0.826321062845663530f, -0.563199344013834090f, + 0.824589302785025290f, -0.565731810783613120f, 0.822849781375826430f, -0.568258952670131490f, + 0.821102514991104650f, -0.570780745886967260f, 0.819347520076796900f, -0.573297166698042200f, + 0.817584813151583710f, -0.575808191417845340f, 0.815814410806733780f, -0.578313796411655590f, + 0.814036329705948410f, -0.580813958095764530f, 0.812250586585203880f, -0.583308652937698290f, + 0.810457198252594770f, -0.585797857456438860f, 0.808656181588174980f, -0.588281548222645220f, + 0.806847553543799330f, -0.590759701858874160f, 0.805031331142963660f, -0.593232295039799800f, + 0.803207531480644940f, -0.595699304492433360f, 0.801376171723140240f, -0.598160706996342270f, + 0.799537269107905010f, -0.600616479383868970f, 0.797690840943391160f, -0.603066598540348160f, + 0.795836904608883570f, -0.605511041404325550f, 0.793975477554337170f, -0.607949784967773630f, + 0.792106577300212390f, -0.610382806276309480f, 0.790230221437310030f, -0.612810082429409710f, + 0.788346427626606340f, -0.615231590580626820f, 0.786455213599085770f, -0.617647307937803870f, + 0.784556597155575240f, -0.620057211763289100f, 0.782650596166575730f, -0.622461279374149970f, + 0.780737228572094490f, -0.624859488142386340f, 0.778816512381475980f, -0.627251815495144080f, + 0.776888465673232440f, -0.629638238914926980f, 0.774953106594873930f, -0.632018735939809060f, + 0.773010453362736990f, -0.634393284163645490f, 0.771060524261813820f, -0.636761861236284200f, + 0.769103337645579700f, -0.639124444863775730f, 0.767138911935820400f, -0.641481012808583160f, + 0.765167265622458960f, -0.643831542889791390f, 0.763188417263381270f, -0.646176012983316280f, + 0.761202385484261780f, -0.648514401022112440f, 0.759209188978388070f, -0.650846684996380880f, + 0.757208846506484570f, -0.653172842953776760f, 0.755201376896536550f, -0.655492852999615350f, + 0.753186799043612520f, -0.657806693297078640f, 0.751165131909686480f, -0.660114342067420480f, + 0.749136394523459370f, -0.662415777590171780f, 0.747100605980180130f, -0.664710978203344790f, + 0.745057785441466060f, -0.666999922303637470f, 0.743007952135121720f, -0.669282588346636010f, + 0.740951125354959110f, -0.671558954847018330f, 0.738887324460615110f, -0.673829000378756040f, + 0.736816568877369900f, -0.676092703575315920f, 0.734738878095963500f, -0.678350043129861470f, + 0.732654271672412820f, -0.680600997795453020f, 0.730562769227827590f, -0.682845546385248080f, + 0.728464390448225200f, -0.685083667772700360f, 0.726359155084346010f, -0.687315340891759050f, + 0.724247082951467000f, -0.689540544737066830f, 0.722128193929215350f, -0.691759258364157750f, + 0.720002507961381650f, -0.693971460889654000f, 0.717870045055731710f, -0.696177131491462990f, + 0.715730825283818590f, -0.698376249408972920f, 0.713584868780793640f, -0.700568793943248340f, + 0.711432195745216430f, -0.702754744457225300f, 0.709272826438865690f, -0.704934080375904880f, + 0.707106781186547570f, -0.707106781186547460f, 0.704934080375904990f, -0.709272826438865580f, + 0.702754744457225300f, -0.711432195745216430f, 0.700568793943248450f, -0.713584868780793520f, + 0.698376249408972920f, -0.715730825283818590f, 0.696177131491462990f, -0.717870045055731710f, + 0.693971460889654000f, -0.720002507961381650f, 0.691759258364157750f, -0.722128193929215350f, + 0.689540544737066940f, -0.724247082951466890f, 0.687315340891759160f, -0.726359155084346010f, + 0.685083667772700360f, -0.728464390448225200f, 0.682845546385248080f, -0.730562769227827590f, + 0.680600997795453130f, -0.732654271672412820f, 0.678350043129861580f, -0.734738878095963390f, + 0.676092703575316030f, -0.736816568877369790f, 0.673829000378756150f, -0.738887324460615110f, + 0.671558954847018330f, -0.740951125354959110f, 0.669282588346636010f, -0.743007952135121720f, + 0.666999922303637470f, -0.745057785441465950f, 0.664710978203344900f, -0.747100605980180130f, + 0.662415777590171780f, -0.749136394523459260f, 0.660114342067420480f, -0.751165131909686370f, + 0.657806693297078640f, -0.753186799043612410f, 0.655492852999615460f, -0.755201376896536550f, + 0.653172842953776760f, -0.757208846506484460f, 0.650846684996380990f, -0.759209188978387960f, + 0.648514401022112550f, -0.761202385484261780f, 0.646176012983316390f, -0.763188417263381270f, + 0.643831542889791500f, -0.765167265622458960f, 0.641481012808583160f, -0.767138911935820400f, + 0.639124444863775730f, -0.769103337645579590f, 0.636761861236284200f, -0.771060524261813710f, + 0.634393284163645490f, -0.773010453362736990f, 0.632018735939809060f, -0.774953106594873820f, + 0.629638238914927100f, -0.776888465673232440f, 0.627251815495144190f, -0.778816512381475870f, + 0.624859488142386450f, -0.780737228572094380f, 0.622461279374150080f, -0.782650596166575730f, + 0.620057211763289210f, -0.784556597155575240f, 0.617647307937803980f, -0.786455213599085770f, + 0.615231590580626820f, -0.788346427626606230f, 0.612810082429409710f, -0.790230221437310030f, + 0.610382806276309480f, -0.792106577300212390f, 0.607949784967773740f, -0.793975477554337170f, + 0.605511041404325550f, -0.795836904608883460f, 0.603066598540348280f, -0.797690840943391040f, + 0.600616479383868970f, -0.799537269107905010f, 0.598160706996342380f, -0.801376171723140130f, + 0.595699304492433470f, -0.803207531480644830f, 0.593232295039799800f, -0.805031331142963660f, + 0.590759701858874280f, -0.806847553543799220f, 0.588281548222645330f, -0.808656181588174980f, + 0.585797857456438860f, -0.810457198252594770f, 0.583308652937698290f, -0.812250586585203880f, + 0.580813958095764530f, -0.814036329705948300f, 0.578313796411655590f, -0.815814410806733780f, + 0.575808191417845340f, -0.817584813151583710f, 0.573297166698042320f, -0.819347520076796900f, + 0.570780745886967370f, -0.821102514991104650f, 0.568258952670131490f, -0.822849781375826320f, + 0.565731810783613230f, -0.824589302785025290f, 0.563199344013834090f, -0.826321062845663420f, + 0.560661576197336030f, -0.828045045257755800f, 0.558118531220556100f, -0.829761233794523050f, + 0.555570233019602290f, -0.831469612302545240f, 0.553016705580027580f, -0.833170164701913190f, + 0.550457972936604810f, -0.834862874986380010f, 0.547894059173100190f, -0.836547727223511890f, + 0.545324988422046460f, -0.838224705554837970f, 0.542750784864516000f, -0.839893794195999410f, + 0.540171472729892970f, -0.841554977436898330f, 0.537587076295645510f, -0.843208239641845440f, + 0.534997619887097260f, -0.844853565249707010f, 0.532403127877198010f, -0.846490938774052020f, + 0.529803624686294830f, -0.848120344803297120f, 0.527199134781901390f, -0.849741768000852440f, + 0.524589682678468840f, -0.851355193105265200f, 0.521975292937154390f, -0.852960604930363630f, + 0.519355990165589530f, -0.854557988365400530f, 0.516731799017649980f, -0.856147328375194470f, + 0.514102744193221660f, -0.857728610000272120f, 0.511468850437970520f, -0.859301818357008360f, + 0.508830142543106990f, -0.860866938637767310f, 0.506186645345155450f, -0.862423956111040500f, + 0.503538383725717580f, -0.863972856121586700f, 0.500885382611240940f, -0.865513624090568980f, + 0.498227666972781870f, -0.867046245515692650f, 0.495565261825772490f, -0.868570705971340900f, + 0.492898192229784090f, -0.870086991108711350f, 0.490226483288291100f, -0.871595086655951090f, + 0.487550160148436050f, -0.873094978418290090f, 0.484869248000791120f, -0.874586652278176110f, + 0.482183772079122830f, -0.876070094195406600f, 0.479493757660153010f, -0.877545290207261240f, + 0.476799230063322250f, -0.879012226428633410f, 0.474100214650550020f, -0.880470889052160750f, + 0.471396736825997810f, -0.881921264348354940f, 0.468688822035827960f, -0.883363338665731580f, + 0.465976495767966130f, -0.884797098430937790f, 0.463259783551860260f, -0.886222530148880640f, + 0.460538710958240010f, -0.887639620402853930f, 0.457813303598877290f, -0.889048355854664570f, + 0.455083587126343840f, -0.890448723244757880f, 0.452349587233771000f, -0.891840709392342720f, + 0.449611329654606600f, -0.893224301195515320f, 0.446868840162374330f, -0.894599485631382580f, + 0.444122144570429260f, -0.895966249756185110f, 0.441371268731716620f, -0.897324580705418320f, + 0.438616238538527710f, -0.898674465693953820f, 0.435857079922255470f, -0.900015892016160280f, + 0.433093818853152010f, -0.901348847046022030f, 0.430326481340082610f, -0.902673318237258830f, + 0.427555093430282200f, -0.903989293123443340f, 0.424779681209108810f, -0.905296759318118820f, + 0.422000270799799790f, -0.906595704514915330f, 0.419216888363223960f, -0.907886116487666150f, + 0.416429560097637320f, -0.909167983090522270f, 0.413638312238434560f, -0.910441292258067140f, + 0.410843171057903910f, -0.911706032005429880f, 0.408044162864978740f, -0.912962190428398100f, + 0.405241314004989860f, -0.914209755703530690f, 0.402434650859418540f, -0.915448716088267830f, + 0.399624199845646790f, -0.916679059921042700f, 0.396809987416710420f, -0.917900775621390390f, + 0.393992040061048100f, -0.919113851690057770f, 0.391170384302253980f, -0.920318276709110480f, + 0.388345046698826300f, -0.921514039342041900f, 0.385516053843919020f, -0.922701128333878520f, + 0.382683432365089840f, -0.923879532511286740f, 0.379847208924051110f, -0.925049240782677580f, + 0.377007410216418310f, -0.926210242138311270f, 0.374164062971457990f, -0.927362525650401110f, + 0.371317193951837600f, -0.928506080473215480f, 0.368466829953372320f, -0.929640895843181330f, + 0.365612997804773960f, -0.930766961078983710f, 0.362755724367397230f, -0.931884265581668150f, + 0.359895036534988280f, -0.932992798834738850f, 0.357030961233430030f, -0.934092550404258870f, + 0.354163525420490510f, -0.935183509938947500f, 0.351292756085567150f, -0.936265667170278260f, + 0.348418680249434510f, -0.937339011912574960f, 0.345541324963989150f, -0.938403534063108060f, + 0.342660717311994380f, -0.939459223602189920f, 0.339776884406826960f, -0.940506070593268300f, + 0.336889853392220050f, -0.941544065183020810f, 0.333999651442009490f, -0.942573197601446870f, + 0.331106305759876430f, -0.943593458161960390f, 0.328209843579092660f, -0.944604837261480260f, + 0.325310292162262980f, -0.945607325380521280f, 0.322407678801070020f, -0.946600913083283530f, + 0.319502030816015750f, -0.947585591017741090f, 0.316593375556165850f, -0.948561349915730270f, + 0.313681740398891570f, -0.949528180593036670f, 0.310767152749611470f, -0.950486073949481700f, + 0.307849640041534980f, -0.951435020969008340f, 0.304929229735402430f, -0.952375012719765880f, + 0.302005949319228200f, -0.953306040354193750f, 0.299079826308040480f, -0.954228095109105670f, + 0.296150888243623960f, -0.955141168305770670f, 0.293219162694258680f, -0.956045251349996410f, + 0.290284677254462330f, -0.956940335732208940f, 0.287347459544729570f, -0.957826413027532910f, + 0.284407537211271820f, -0.958703474895871600f, 0.281464937925758050f, -0.959571513081984520f, + 0.278519689385053060f, -0.960430519415565790f, 0.275571819310958250f, -0.961280485811320640f, + 0.272621355449948980f, -0.962121404269041580f, 0.269668325572915200f, -0.962953266873683880f, + 0.266712757474898420f, -0.963776065795439840f, 0.263754678974831510f, -0.964589793289812650f, + 0.260794117915275570f, -0.965394441697689400f, 0.257831102162158930f, -0.966190003445412620f, + 0.254865659604514630f, -0.966976471044852070f, 0.251897818154216910f, -0.967753837093475510f, + 0.248927605745720260f, -0.968522094274417270f, 0.245955050335794590f, -0.969281235356548530f, + 0.242980179903263980f, -0.970031253194543970f, 0.240003022448741500f, -0.970772140728950350f, + 0.237023605994367340f, -0.971503890986251780f, 0.234041958583543460f, -0.972226497078936270f, + 0.231058108280671280f, -0.972939952205560070f, 0.228072083170885790f, -0.973644249650811870f, + 0.225083911359792780f, -0.974339382785575860f, 0.222093620973203590f, -0.975025345066994120f, + 0.219101240156869770f, -0.975702130038528570f, 0.216106797076219600f, -0.976369731330021140f, + 0.213110319916091360f, -0.977028142657754390f, 0.210111836880469720f, -0.977677357824509930f, + 0.207111376192218560f, -0.978317370719627650f, 0.204108966092817010f, -0.978948175319062200f, + 0.201104634842091960f, -0.979569765685440520f, 0.198098410717953730f, -0.980182135968117320f, + 0.195090322016128330f, -0.980785280403230430f, 0.192080397049892380f, -0.981379193313754560f, + 0.189068664149806280f, -0.981963869109555240f, 0.186055151663446630f, -0.982539302287441240f, + 0.183039887955141060f, -0.983105487431216290f, 0.180022901405699510f, -0.983662419211730250f, + 0.177004220412148860f, -0.984210092386929030f, 0.173983873387463850f, -0.984748501801904210f, + 0.170961888760301360f, -0.985277642388941220f, 0.167938294974731230f, -0.985797509167567370f, + 0.164913120489970090f, -0.986308097244598670f, 0.161886393780111910f, -0.986809401814185420f, + 0.158858143333861390f, -0.987301418157858430f, 0.155828397654265320f, -0.987784141644572180f, + 0.152797185258443410f, -0.988257567730749460f, 0.149764534677321620f, -0.988721691960323780f, + 0.146730474455361750f, -0.989176509964781010f, 0.143695033150294580f, -0.989622017463200780f, + 0.140658239332849240f, -0.990058210262297120f, 0.137620121586486180f, -0.990485084256456980f, + 0.134580708507126220f, -0.990902635427780010f, 0.131540028702883280f, -0.991310859846115440f, + 0.128498110793793220f, -0.991709753669099530f, 0.125454983411546210f, -0.992099313142191800f, + 0.122410675199216280f, -0.992479534598709970f, 0.119365214810991350f, -0.992850414459865100f, + 0.116318630911904880f, -0.993211949234794500f, 0.113270952177564360f, -0.993564135520595300f, + 0.110222207293883180f, -0.993906970002356060f, 0.107172424956808870f, -0.994240449453187900f, + 0.104121633872054730f, -0.994564570734255420f, 0.101069862754827880f, -0.994879330794805620f, + 0.098017140329560770f, -0.995184726672196820f, 0.094963495329639061f, -0.995480755491926940f, + 0.091908956497132696f, -0.995767414467659820f, 0.088853552582524684f, -0.996044700901251970f, + 0.085797312344439880f, -0.996312612182778000f, 0.082740264549375803f, -0.996571145790554840f, + 0.079682437971430126f, -0.996820299291165670f, 0.076623861392031617f, -0.997060070339482960f, + 0.073564563599667454f, -0.997290456678690210f, 0.070504573389614009f, -0.997511456140303450f, + 0.067443919563664106f, -0.997723066644191640f, 0.064382630929857410f, -0.997925286198596000f, + 0.061320736302208648f, -0.998118112900149180f, 0.058258264500435732f, -0.998301544933892890f, + 0.055195244349690031f, -0.998475580573294770f, 0.052131704680283317f, -0.998640218180265270f, + 0.049067674327418126f, -0.998795456205172410f, 0.046003182130914644f, -0.998941293186856870f, + 0.042938256934940959f, -0.999077727752645360f, 0.039872927587739845f, -0.999204758618363890f, + 0.036807222941358991f, -0.999322384588349540f, 0.033741171851377642f, -0.999430604555461730f, + 0.030674803176636581f, -0.999529417501093140f, 0.027608145778965820f, -0.999618822495178640f, + 0.024541228522912264f, -0.999698818696204250f, 0.021474080275469605f, -0.999769405351215280f, + 0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f, -0.999882347454212560f, + 0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f, -0.999957644551963900f, + 0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f, -0.999995293809576190f +}; + + const float32_t cos_factors_512[512] = { + 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f, + 0.999942349676023910f, + 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f, + 0.999735288260561680f, + 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f, + 0.999377670388002850f, + 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f, + 0.998869549914283560f, + 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f, + 0.998211003360478190f, + 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f, + 0.997402129901275300f, + 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f, + 0.996443051350042630f, + 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f, + 0.995333912140482280f, + 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f, + 0.994074879304879370f, + 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f, + 0.992666142448948020f, + 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f, + 0.991107913723276890f, + 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f, + 0.989400427791380380f, + 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f, + 0.987543941794359230f, + 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f, + 0.985538735312176060f, + 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f, + 0.983385110321551180f, + 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f, + 0.981083391150486710f, + 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f, + 0.978633924429423210f, + 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f, + 0.976037079039039020f, + 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f, + 0.973293246054698250f, + 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f, + 0.970402838687555500f, + 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f, + 0.967366292222328510f, + 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f, + 0.964184063951745830f, + 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f, + 0.960856633107679660f, + 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f, + 0.957384500788975860f, + 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f, + 0.953768189885990330f, + 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f, + 0.950008245001843000f, + 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f, + 0.946105232370403450f, + 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f, + 0.942059739771017310f, + 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f, + 0.937872376439989890f, + 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f, + 0.933543772978836170f, + 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f, + 0.929074581259315860f, + 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f, + 0.924465474325262600f, + 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f, + 0.919717146291227360f, + 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f, + 0.914830312237946200f, + 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f, + 0.909805708104652220f, + 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f, + 0.904644090578246240f, + 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f, + 0.899346236979341570f, + 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f, + 0.893912945145203250f, + 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f, + 0.888345033309596350f, + 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f, + 0.882643339979562790f, + 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f, + 0.876808723809145650f, + 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f, + 0.870842063470078980f, + 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f, + 0.864744257519462380f, + 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f, + 0.858516224264442740f, + 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f, + 0.852158901623919830f, + 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f, + 0.845673246987299070f, + 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f, + 0.839060237070312740f, + 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f, + 0.832320867767929680f, + 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f, + 0.825456154004377550f, + 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f, + 0.818467129580298660f, + 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f, + 0.811354847017063730f, + 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f, + 0.804120377398265810f, + 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f, + 0.796764810208418830f, + 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f, + 0.789289253168885650f, + 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f, + 0.781694832071059390f, + 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f, + 0.773982690606822900f, + 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f, + 0.766153990196312920f, + 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f, + 0.758209909813015280f, + 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f, + 0.750151645806215070f, + 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f, + 0.741980411720831070f, + 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f, + 0.733697438114660370f, + 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f, + 0.725303972373060770f, + 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f, + 0.716801278521099540f, + 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f, + 0.708190637033195400f, + 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f, + 0.699473344640283770f, + 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f, + 0.690650714134534720f, + 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f, + 0.681724074171649820f, + 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f, + 0.672694769070772970f, + 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f, + 0.663564158612039880f, + 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f, + 0.654333617831800550f, + 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f, + 0.645004536815544040f, + 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f, + 0.635578320488556230f, + 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f, + 0.626056388404343520f, + 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f, + 0.616440174530853650f, + 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f, + 0.606731127034524480f, + 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f, + 0.596930708062196500f, + 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f, + 0.587040393520918080f, + 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f, + 0.577061672855679550f, + 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f, + 0.566996048825108680f, + 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f, + 0.556845037275160100f, + 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f, + 0.546610166910834860f, + 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f, + 0.536292979065963180f, + 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f, + 0.525895027471084740f, + 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f, + 0.515417878019463150f, + 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f, + 0.504863108531267480f, + 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f, + 0.494232308515959730f, + 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f, + 0.483527078932918740f, + 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f, + 0.472749031950342900f, + 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f, + 0.461899790702462840f, + 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f, + 0.450980989045103810f, + 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f, + 0.439994271309633260f, + 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f, + 0.428941292055329550f, + 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f, + 0.417823715820212380f, + 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f, + 0.406643216870369140f, + 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f, + 0.395401478947816300f, + 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f, + 0.384100195016935040f, + 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f, + 0.372741067009515810f, + 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f, + 0.361325805568454340f, + 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f, + 0.349856129790135030f, + 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f, + 0.338333766965541290f, + 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f, + 0.326760452320131790f, + 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f, + 0.315137928752522440f, + 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f, + 0.303467946572011370f, + 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f, + 0.291752263234989370f, + 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f, + 0.279992643080273380f, + 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f, + 0.268190857063403180f, + 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f, + 0.256348682489942910f, + 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f, + 0.244467902747824210f, + 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f, + 0.232550307038775330f, + 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f, + 0.220597690108873650f, + 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f, + 0.208611851978263460f, + 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f, + 0.196594597670080220f, + 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f, + 0.184547736938619640f, + 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f, + 0.172473083996796030f, + 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f, + 0.160372457242928400f, + 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f, + 0.148247678986896200f, + 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f, + 0.136100575175706200f, + 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f, + 0.123932975118512200f, + 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f, + 0.111746711211126660f, + 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f, + 0.099543618660069444f, + 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f, + 0.087325535206192226f, + 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f, + 0.075094300847921291f, + 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f, + 0.062851757564161420f, + 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f, + 0.050599749036899337f, + 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f, + 0.038340120373552791f, + 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f, + 0.026074717829104040f, + 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f, + 0.013805388528060349f, + 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f, + 0.001533980186284766f +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + const float32_t Weights_2048[4096] = { + 1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f, -0.000766990318742704f, + 0.999998823451701880f, -0.001533980186284766f, 0.999997352766978210f, -0.002300969151425805f, + 0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f, -0.003834942569706228f, + 0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f, -0.005368906963996343f, + 0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f, -0.006902858724729756f, + 0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f, -0.008436794242369799f, + 0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f, -0.009970709907418031f, + 0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f, -0.011504602110422714f, + 0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f, -0.013038467241987334f, + 0.999904701082852900f, -0.013805388528060391f, 0.999893818374418490f, -0.014572301692779064f, + 0.999882347454212560f, -0.015339206284988100f, 0.999870288328982950f, -0.016106101853537287f, + 0.999857641005823860f, -0.016872987947281710f, 0.999844405492175240f, -0.017639864115082053f, + 0.999830581795823400f, -0.018406729905804820f, 0.999816169924900410f, -0.019173584868322623f, + 0.999801169887884260f, -0.019940428551514441f, 0.999785581693599210f, -0.020707260504265895f, + 0.999769405351215280f, -0.021474080275469508f, 0.999752640870248840f, -0.022240887414024961f, + 0.999735288260561680f, -0.023007681468839369f, 0.999717347532362190f, -0.023774461988827555f, + 0.999698818696204250f, -0.024541228522912288f, 0.999679701762987930f, -0.025307980620024571f, + 0.999659996743959220f, -0.026074717829103901f, 0.999639703650710200f, -0.026841439699098531f, + 0.999618822495178640f, -0.027608145778965740f, 0.999597353289648380f, -0.028374835617672099f, + 0.999575296046749220f, -0.029141508764193722f, 0.999552650779456990f, -0.029908164767516555f, + 0.999529417501093140f, -0.030674803176636626f, 0.999505596225325310f, -0.031441423540560301f, + 0.999481186966166950f, -0.032208025408304586f, 0.999456189737977340f, -0.032974608328897335f, + 0.999430604555461730f, -0.033741171851377580f, 0.999404431433671300f, -0.034507715524795750f, + 0.999377670388002850f, -0.035274238898213947f, 0.999350321434199440f, -0.036040741520706229f, + 0.999322384588349540f, -0.036807222941358832f, 0.999293859866887790f, -0.037573682709270494f, + 0.999264747286594420f, -0.038340120373552694f, 0.999235046864595850f, -0.039106535483329888f, + 0.999204758618363890f, -0.039872927587739811f, 0.999173882565716380f, -0.040639296235933736f, + 0.999142418724816910f, -0.041405640977076739f, 0.999110367114174890f, -0.042171961360347947f, + 0.999077727752645360f, -0.042938256934940820f, 0.999044500659429290f, -0.043704527250063421f, + 0.999010685854073380f, -0.044470771854938668f, 0.998976283356469820f, -0.045236990298804590f, + 0.998941293186856870f, -0.046003182130914623f, 0.998905715365818290f, -0.046769346900537863f, + 0.998869549914283560f, -0.047535484156959303f, 0.998832796853527990f, -0.048301593449480144f, + 0.998795456205172410f, -0.049067674327418015f, 0.998757527991183340f, -0.049833726340107277f, + 0.998719012233872940f, -0.050599749036899282f, 0.998679908955899090f, -0.051365741967162593f, + 0.998640218180265270f, -0.052131704680283324f, 0.998599939930320370f, -0.052897636725665324f, + 0.998559074229759310f, -0.053663537652730520f, 0.998517621102622210f, -0.054429407010919133f, + 0.998475580573294770f, -0.055195244349689934f, 0.998432952666508440f, -0.055961049218520569f, + 0.998389737407340160f, -0.056726821166907748f, 0.998345934821212370f, -0.057492559744367566f, + 0.998301544933892890f, -0.058258264500435752f, 0.998256567771495180f, -0.059023934984667931f, + 0.998211003360478190f, -0.059789570746639868f, 0.998164851727646240f, -0.060555171335947788f, + 0.998118112900149180f, -0.061320736302208578f, 0.998070786905482340f, -0.062086265195060088f, + 0.998022873771486240f, -0.062851757564161406f, 0.997974373526346990f, -0.063617212959193106f, + 0.997925286198596000f, -0.064382630929857465f, 0.997875611817110150f, -0.065148011025878833f, + 0.997825350411111640f, -0.065913352797003805f, 0.997774502010167820f, -0.066678655793001557f, + 0.997723066644191640f, -0.067443919563664051f, 0.997671044343441000f, -0.068209143658806329f, + 0.997618435138519550f, -0.068974327628266746f, 0.997565239060375750f, -0.069739471021907307f, + 0.997511456140303450f, -0.070504573389613856f, 0.997457086409941910f, -0.071269634281296401f, + 0.997402129901275300f, -0.072034653246889332f, 0.997346586646633230f, -0.072799629836351673f, + 0.997290456678690210f, -0.073564563599667426f, 0.997233740030466280f, -0.074329454086845756f, + 0.997176436735326190f, -0.075094300847921305f, 0.997118546826979980f, -0.075859103432954447f, + 0.997060070339482960f, -0.076623861392031492f, 0.997001007307235290f, -0.077388574275265049f, + 0.996941357764982160f, -0.078153241632794232f, 0.996881121747813850f, -0.078917863014784942f, + 0.996820299291165670f, -0.079682437971430126f, 0.996758890430818000f, -0.080446966052950014f, + 0.996696895202896060f, -0.081211446809592441f, 0.996634313643869900f, -0.081975879791633066f, + 0.996571145790554840f, -0.082740264549375692f, 0.996507391680110820f, -0.083504600633152432f, + 0.996443051350042630f, -0.084268887593324071f, 0.996378124838200210f, -0.085033124980280275f, + 0.996312612182778000f, -0.085797312344439894f, 0.996246513422315520f, -0.086561449236251170f, + 0.996179828595696980f, -0.087325535206192059f, 0.996112557742151130f, -0.088089569804770507f, + 0.996044700901251970f, -0.088853552582524600f, 0.995976258112917790f, -0.089617483090022959f, + 0.995907229417411720f, -0.090381360877864983f, 0.995837614855341610f, -0.091145185496681005f, + 0.995767414467659820f, -0.091908956497132724f, 0.995696628295663520f, -0.092672673429913310f, + 0.995625256380994310f, -0.093436335845747787f, 0.995553298765638470f, -0.094199943295393204f, + 0.995480755491926940f, -0.094963495329638992f, 0.995407626602534900f, -0.095726991499307162f, + 0.995333912140482280f, -0.096490431355252593f, 0.995259612149133390f, -0.097253814448363271f, + 0.995184726672196930f, -0.098017140329560604f, 0.995109255753726110f, -0.098780408549799623f, + 0.995033199438118630f, -0.099543618660069319f, 0.994956557770116380f, -0.100306770211392860f, + 0.994879330794805620f, -0.101069862754827820f, 0.994801518557617110f, -0.101832895841466530f, + 0.994723121104325700f, -0.102595869022436280f, 0.994644138481050710f, -0.103358781848899610f, + 0.994564570734255420f, -0.104121633872054590f, 0.994484417910747600f, -0.104884424643134970f, + 0.994403680057679100f, -0.105647153713410620f, 0.994322357222545810f, -0.106409820634187680f, + 0.994240449453187900f, -0.107172424956808840f, 0.994157956797789730f, -0.107934966232653650f, + 0.994074879304879370f, -0.108697444013138720f, 0.993991217023329380f, -0.109459857849717980f, + 0.993906970002356060f, -0.110222207293883060f, 0.993822138291519660f, -0.110984491897163390f, + 0.993736721940724600f, -0.111746711211126590f, 0.993650721000219120f, -0.112508864787378690f, + 0.993564135520595300f, -0.113270952177564350f, 0.993476965552789190f, -0.114032972933367200f, + 0.993389211148080650f, -0.114794926606510080f, 0.993300872358093280f, -0.115556812748755260f, + 0.993211949234794500f, -0.116318630911904750f, 0.993122441830495580f, -0.117080380647800590f, + 0.993032350197851410f, -0.117842061508324980f, 0.992941674389860470f, -0.118603673045400720f, + 0.992850414459865100f, -0.119365214810991350f, 0.992758570461551140f, -0.120126686357101500f, + 0.992666142448948020f, -0.120888087235777080f, 0.992573130476428810f, -0.121649416999105530f, + 0.992479534598709970f, -0.122410675199216200f, 0.992385354870851670f, -0.123171861388280480f, + 0.992290591348257370f, -0.123932975118512160f, 0.992195244086673920f, -0.124694015942167640f, + 0.992099313142191800f, -0.125454983411546230f, 0.992002798571244520f, -0.126215877078990350f, + 0.991905700430609330f, -0.126976696496885870f, 0.991808018777406430f, -0.127737441217662310f, + 0.991709753669099530f, -0.128498110793793170f, 0.991610905163495370f, -0.129258704777796140f, + 0.991511473318743900f, -0.130019222722233350f, 0.991411458193338540f, -0.130779664179711710f, + 0.991310859846115440f, -0.131540028702883120f, 0.991209678336254060f, -0.132300315844444650f, + 0.991107913723276890f, -0.133060525157139060f, 0.991005566067049370f, -0.133820656193754720f, + 0.990902635427780010f, -0.134580708507126170f, 0.990799121866020370f, -0.135340681650134210f, + 0.990695025442664630f, -0.136100575175706200f, 0.990590346218950150f, -0.136860388636816380f, + 0.990485084256457090f, -0.137620121586486040f, 0.990379239617108160f, -0.138379773577783890f, + 0.990272812363169110f, -0.139139344163826200f, 0.990165802557248400f, -0.139898832897777210f, + 0.990058210262297120f, -0.140658239332849210f, 0.989950035541608990f, -0.141417563022303020f, + 0.989841278458820530f, -0.142176803519448030f, 0.989731939077910570f, -0.142935960377642670f, + 0.989622017463200890f, -0.143695033150294470f, 0.989511513679355190f, -0.144454021390860470f, + 0.989400427791380380f, -0.145212924652847460f, 0.989288759864625170f, -0.145971742489812210f, + 0.989176509964781010f, -0.146730474455361750f, 0.989063678157881540f, -0.147489120103153570f, + 0.988950264510302990f, -0.148247678986896030f, 0.988836269088763540f, -0.149006150660348450f, + 0.988721691960323780f, -0.149764534677321510f, 0.988606533192386450f, -0.150522830591677400f, + 0.988490792852696590f, -0.151281037957330220f, 0.988374471009341280f, -0.152039156328246050f, + 0.988257567730749460f, -0.152797185258443440f, 0.988140083085692570f, -0.153555124301993450f, + 0.988022017143283530f, -0.154312973013020100f, 0.987903369972977790f, -0.155070730945700510f, + 0.987784141644572180f, -0.155828397654265230f, 0.987664332228205710f, -0.156585972692998430f, + 0.987543941794359230f, -0.157343455616238250f, 0.987422970413855410f, -0.158100845978376980f, + 0.987301418157858430f, -0.158858143333861450f, 0.987179285097874340f, -0.159615347237193060f, + 0.987056571305750970f, -0.160372457242928280f, 0.986933276853677710f, -0.161129472905678810f, + 0.986809401814185530f, -0.161886393780111830f, 0.986684946260146690f, -0.162643219420950310f, + 0.986559910264775410f, -0.163399949382973230f, 0.986434293901627180f, -0.164156583221015810f, + 0.986308097244598670f, -0.164913120489969890f, 0.986181320367928270f, -0.165669560744784120f, + 0.986053963346195440f, -0.166425903540464100f, 0.985926026254321130f, -0.167182148432072940f, + 0.985797509167567480f, -0.167938294974731170f, 0.985668412161537550f, -0.168694342723617330f, + 0.985538735312176060f, -0.169450291233967960f, 0.985408478695768420f, -0.170206140061078070f, + 0.985277642388941220f, -0.170961888760301220f, 0.985146226468662230f, -0.171717536887049970f, + 0.985014231012239840f, -0.172473083996795950f, 0.984881656097323700f, -0.173228529645070320f, + 0.984748501801904210f, -0.173983873387463820f, 0.984614768204312600f, -0.174739114779627200f, + 0.984480455383220930f, -0.175494253377271430f, 0.984345563417641900f, -0.176249288736167880f, + 0.984210092386929030f, -0.177004220412148750f, 0.984074042370776450f, -0.177759047961107170f, + 0.983937413449218920f, -0.178513770938997510f, 0.983800205702631600f, -0.179268388901835750f, + 0.983662419211730250f, -0.180022901405699510f, 0.983524054057571260f, -0.180777308006728590f, + 0.983385110321551180f, -0.181531608261124970f, 0.983245588085407070f, -0.182285801725153300f, + 0.983105487431216290f, -0.183039887955140950f, 0.982964808441396440f, -0.183793866507478450f, + 0.982823551198705240f, -0.184547736938619620f, 0.982681715786240860f, -0.185301498805081900f, + 0.982539302287441240f, -0.186055151663446630f, 0.982396310786084690f, -0.186808695070359270f, + 0.982252741366289370f, -0.187562128582529600f, 0.982108594112513610f, -0.188315451756732120f, + 0.981963869109555240f, -0.189068664149806190f, 0.981818566442552500f, -0.189821765318656410f, + 0.981672686196983110f, -0.190574754820252740f, 0.981526228458664770f, -0.191327632211630900f, + 0.981379193313754560f, -0.192080397049892440f, 0.981231580848749730f, -0.192833048892205230f, + 0.981083391150486710f, -0.193585587295803610f, 0.980934624306141640f, -0.194338011817988600f, + 0.980785280403230430f, -0.195090322016128250f, 0.980635359529608120f, -0.195842517447657850f, + 0.980484861773469380f, -0.196594597670080220f, 0.980333787223347960f, -0.197346562240965920f, + 0.980182135968117430f, -0.198098410717953560f, 0.980029908096990090f, -0.198850142658750090f, + 0.979877103699517640f, -0.199601757621130970f, 0.979723722865591170f, -0.200353255162940450f, + 0.979569765685440520f, -0.201104634842091900f, 0.979415232249634780f, -0.201855896216568050f, + 0.979260122649082020f, -0.202607038844421130f, 0.979104436975029250f, -0.203358062283773320f, + 0.978948175319062200f, -0.204108966092816870f, 0.978791337773105670f, -0.204859749829814420f, + 0.978633924429423210f, -0.205610413053099240f, 0.978475935380616830f, -0.206360955321075510f, + 0.978317370719627650f, -0.207111376192218560f, 0.978158230539735050f, -0.207861675225075070f, + 0.977998514934557140f, -0.208611851978263490f, 0.977838223998050430f, -0.209361906010474160f, + 0.977677357824509930f, -0.210111836880469610f, 0.977515916508569280f, -0.210861644147084860f, + 0.977353900145199960f, -0.211611327369227550f, 0.977191308829712280f, -0.212360886105878420f, + 0.977028142657754390f, -0.213110319916091360f, 0.976864401725312640f, -0.213859628358993750f, + 0.976700086128711840f, -0.214608810993786760f, 0.976535195964614470f, -0.215357867379745550f, + 0.976369731330021140f, -0.216106797076219520f, 0.976203692322270560f, -0.216855599642632620f, + 0.976037079039039020f, -0.217604274638483640f, 0.975869891578341030f, -0.218352821623346320f, + 0.975702130038528570f, -0.219101240156869800f, 0.975533794518291360f, -0.219849529798778700f, + 0.975364885116656980f, -0.220597690108873510f, 0.975195401932990370f, -0.221345720647030810f, + 0.975025345066994120f, -0.222093620973203510f, 0.974854714618708430f, -0.222841390647421120f, + 0.974683510688510670f, -0.223589029229789990f, 0.974511733377115720f, -0.224336536280493600f, + 0.974339382785575860f, -0.225083911359792830f, 0.974166459015280320f, -0.225831154028026170f, + 0.973992962167955830f, -0.226578263845610000f, 0.973818892345666100f, -0.227325240373038860f, + 0.973644249650811980f, -0.228072083170885730f, 0.973469034186131070f, -0.228818791799802220f, + 0.973293246054698250f, -0.229565365820518870f, 0.973116885359925130f, -0.230311804793845440f, + 0.972939952205560180f, -0.231058108280671110f, 0.972762446695688570f, -0.231804275841964780f, + 0.972584368934732210f, -0.232550307038775240f, 0.972405719027449770f, -0.233296201432231590f, + 0.972226497078936270f, -0.234041958583543430f, 0.972046703194623500f, -0.234787578054000970f, + 0.971866337480279400f, -0.235533059404975490f, 0.971685400042008540f, -0.236278402197919570f, + 0.971503890986251780f, -0.237023605994367200f, 0.971321810419786160f, -0.237768670355934190f, + 0.971139158449725090f, -0.238513594844318420f, 0.970955935183517970f, -0.239258379021299980f, + 0.970772140728950350f, -0.240003022448741500f, 0.970587775194143630f, -0.240747524688588430f, + 0.970402838687555500f, -0.241491885302869330f, 0.970217331317979160f, -0.242236103853696010f, + 0.970031253194543970f, -0.242980179903263870f, 0.969844604426714830f, -0.243724113013852160f, + 0.969657385124292450f, -0.244467902747824150f, 0.969469595397413060f, -0.245211548667627540f, + 0.969281235356548530f, -0.245955050335794590f, 0.969092305112506210f, -0.246698407314942410f, + 0.968902804776428870f, -0.247441619167773270f, 0.968712734459794780f, -0.248184685457074780f, + 0.968522094274417380f, -0.248927605745720150f, 0.968330884332445190f, -0.249670379596668570f, + 0.968139104746362440f, -0.250413006572965220f, 0.967946755628987800f, -0.251155486237741920f, + 0.967753837093475510f, -0.251897818154216970f, 0.967560349253314360f, -0.252640001885695520f, + 0.967366292222328510f, -0.253382036995570160f, 0.967171666114676640f, -0.254123923047320620f, + 0.966976471044852070f, -0.254865659604514570f, 0.966780707127683270f, -0.255607246230807380f, + 0.966584374478333120f, -0.256348682489942910f, 0.966387473212298900f, -0.257089967945753120f, + 0.966190003445412500f, -0.257831102162158990f, 0.965991965293840570f, + -0.258572084703170340f, + 0.965793358874083680f, -0.259312915132886230f, 0.965594184302976830f, + -0.260053593015495190f, + 0.965394441697689400f, -0.260794117915275510f, 0.965194131175724720f, + -0.261534489396595520f, + 0.964993252854920320f, -0.262274707023913590f, 0.964791806853447900f, + -0.263014770361779000f, + 0.964589793289812760f, -0.263754678974831350f, 0.964387212282854290f, + -0.264494432427801630f, + 0.964184063951745830f, -0.265234030285511790f, 0.963980348415994110f, + -0.265973472112875590f, + 0.963776065795439840f, -0.266712757474898370f, 0.963571216210257320f, + -0.267451885936677620f, + 0.963365799780954050f, -0.268190857063403180f, 0.963159816628371360f, + -0.268929670420357260f, + 0.962953266873683880f, -0.269668325572915090f, 0.962746150638399410f, + -0.270406822086544820f, + 0.962538468044359160f, -0.271145159526808010f, 0.962330219213737400f, + -0.271883337459359720f, + 0.962121404269041580f, -0.272621355449948980f, 0.961912023333112210f, + -0.273359213064418680f, + 0.961702076529122540f, -0.274096909868706380f, 0.961491563980579000f, + -0.274834445428843940f, + 0.961280485811320640f, -0.275571819310958140f, 0.961068842145519350f, + -0.276309031081271080f, + 0.960856633107679660f, -0.277046080306099900f, 0.960643858822638590f, + -0.277782966551857690f, + 0.960430519415565790f, -0.278519689385053060f, 0.960216615011963430f, + -0.279256248372291180f, + 0.960002145737665960f, -0.279992643080273220f, 0.959787111718839900f, + -0.280728873075797190f, + 0.959571513081984520f, -0.281464937925757940f, 0.959355349953930790f, + -0.282200837197147560f, + 0.959138622461841890f, -0.282936570457055390f, 0.958921330733213170f, + -0.283672137272668430f, + 0.958703474895871600f, -0.284407537211271880f, 0.958485055077976100f, + -0.285142769840248670f, + 0.958266071408017670f, -0.285877834727080620f, 0.958046524014818600f, + -0.286612731439347790f, + 0.957826413027532910f, -0.287347459544729510f, 0.957605738575646350f, + -0.288082018611004130f, + 0.957384500788975860f, -0.288816408206049480f, 0.957162699797670210f, + -0.289550627897843030f, + 0.956940335732208820f, -0.290284677254462330f, 0.956717408723403050f, + -0.291018555844085090f, + 0.956493918902395100f, -0.291752263234989260f, 0.956269866400658030f, + -0.292485798995553880f, + 0.956045251349996410f, -0.293219162694258630f, 0.955820073882545420f, + -0.293952353899684660f, + 0.955594334130771110f, -0.294685372180514330f, 0.955368032227470350f, + -0.295418217105532010f, + 0.955141168305770780f, -0.296150888243623790f, 0.954913742499130520f, + -0.296883385163778270f, + 0.954685754941338340f, -0.297615707435086200f, 0.954457205766513490f, + -0.298347854626741400f, + 0.954228095109105670f, -0.299079826308040480f, 0.953998423103894490f, + -0.299811622048383350f, + 0.953768189885990330f, -0.300543241417273450f, 0.953537395590833280f, + -0.301274683984317950f, + 0.953306040354193860f, -0.302005949319228080f, 0.953074124312172200f, + -0.302737036991819140f, + 0.952841647601198720f, -0.303467946572011320f, 0.952608610358033350f, + -0.304198677629829110f, + 0.952375012719765880f, -0.304929229735402370f, 0.952140854823815830f, + -0.305659602458966120f, + 0.951906136807932350f, -0.306389795370860920f, 0.951670858810193860f, + -0.307119808041533100f, + 0.951435020969008340f, -0.307849640041534870f, 0.951198623423113230f, + -0.308579290941525090f, + 0.950961666311575080f, -0.309308760312268730f, 0.950724149773789610f, + -0.310038047724637890f, + 0.950486073949481700f, -0.310767152749611470f, 0.950247438978705230f, + -0.311496074958275910f, + 0.950008245001843000f, -0.312224813921824880f, 0.949768492159606680f, + -0.312953369211560200f, + 0.949528180593036670f, -0.313681740398891520f, 0.949287310443502120f, + -0.314409927055336660f, + 0.949045881852700560f, -0.315137928752522440f, 0.948803894962658490f, + -0.315865745062183960f, + 0.948561349915730270f, -0.316593375556165850f, 0.948318246854599090f, + -0.317320819806421740f, + 0.948074585922276230f, -0.318048077385014950f, 0.947830367262101010f, + -0.318775147864118480f, + 0.947585591017741090f, -0.319502030816015690f, 0.947340257333192050f, + -0.320228725813099860f, + 0.947094366352777220f, -0.320955232427875210f, 0.946847918221148000f, + -0.321681550232956580f, + 0.946600913083283530f, -0.322407678801069850f, 0.946353351084490590f, + -0.323133617705052330f, + 0.946105232370403450f, -0.323859366517852850f, 0.945856557086983910f, + -0.324584924812532150f, + 0.945607325380521280f, -0.325310292162262930f, 0.945357537397632290f, + -0.326035468140330240f, + 0.945107193285260610f, -0.326760452320131730f, 0.944856293190677210f, + -0.327485244275178000f, + 0.944604837261480260f, -0.328209843579092500f, 0.944352825645594750f, + -0.328934249805612200f, + 0.944100258491272660f, -0.329658462528587490f, 0.943847135947092690f, + -0.330382481321982780f, + 0.943593458161960390f, -0.331106305759876430f, 0.943339225285107720f, + -0.331829935416461110f, + 0.943084437466093490f, -0.332553369866044220f, 0.942829094854802710f, + -0.333276608683047930f, + 0.942573197601446870f, -0.333999651442009380f, 0.942316745856563780f, + -0.334722497717581220f, + 0.942059739771017310f, -0.335445147084531600f, 0.941802179495997650f, + -0.336167599117744520f, + 0.941544065183020810f, -0.336889853392220050f, 0.941285396983928660f, + -0.337611909483074620f, + 0.941026175050889260f, -0.338333766965541130f, 0.940766399536396070f, + -0.339055425414969640f, + 0.940506070593268300f, -0.339776884406826850f, 0.940245188374650880f, + -0.340498143516697160f, + 0.939983753034014050f, -0.341219202320282360f, 0.939721764725153340f, + -0.341940060393402190f, + 0.939459223602189920f, -0.342660717311994380f, 0.939196129819569900f, + -0.343381172652115040f, + 0.938932483532064600f, -0.344101425989938810f, 0.938668284894770170f, + -0.344821476901759290f, + 0.938403534063108060f, -0.345541324963989090f, 0.938138231192824360f, + -0.346260969753160010f, + 0.937872376439989890f, -0.346980410845923680f, 0.937605969960999990f, + -0.347699647819051380f, + 0.937339011912574960f, -0.348418680249434560f, 0.937071502451759190f, + -0.349137507714084970f, + 0.936803441735921560f, -0.349856129790134920f, 0.936534829922755500f, + -0.350574546054837510f, + 0.936265667170278260f, -0.351292756085567090f, 0.935995953636831410f, + -0.352010759459819080f, + 0.935725689481080370f, -0.352728555755210730f, 0.935454874862014620f, + -0.353446144549480810f, + 0.935183509938947610f, -0.354163525420490340f, 0.934911594871516090f, + -0.354880697946222790f, + 0.934639129819680780f, -0.355597661704783850f, 0.934366114943725790f, + -0.356314416274402410f, + 0.934092550404258980f, -0.357030961233429980f, 0.933818436362210960f, + -0.357747296160341900f, + 0.933543772978836170f, -0.358463420633736540f, 0.933268560415712050f, + -0.359179334232336500f, + 0.932992798834738960f, -0.359895036534988110f, 0.932716488398140250f, + -0.360610527120662270f, + 0.932439629268462360f, -0.361325805568454280f, 0.932162221608574430f, + -0.362040871457584180f, + 0.931884265581668150f, -0.362755724367397230f, 0.931605761351257830f, + -0.363470363877363760f, + 0.931326709081180430f, -0.364184789567079890f, 0.931047108935595280f, + -0.364899001016267320f, + 0.930766961078983710f, -0.365612997804773850f, 0.930486265676149780f, + -0.366326779512573590f, + 0.930205022892219070f, -0.367040345719767180f, 0.929923232892639670f, + -0.367753696006581980f, + 0.929640895843181330f, -0.368466829953372320f, 0.929358011909935500f, + -0.369179747140620020f, + 0.929074581259315860f, -0.369892447148934100f, 0.928790604058057020f, + -0.370604929559051670f, + 0.928506080473215590f, -0.371317193951837540f, 0.928221010672169440f, + -0.372029239908285010f, + 0.927935394822617890f, -0.372741067009515760f, 0.927649233092581180f, + -0.373452674836780300f, + 0.927362525650401110f, -0.374164062971457930f, 0.927075272664740100f, + -0.374875230995057540f, + 0.926787474304581750f, -0.375586178489217220f, 0.926499130739230510f, + -0.376296905035704790f, + 0.926210242138311380f, -0.377007410216418260f, 0.925920808671770070f, + -0.377717693613385640f, + 0.925630830509872720f, -0.378427754808765560f, 0.925340307823206310f, + -0.379137593384847320f, + 0.925049240782677580f, -0.379847208924051160f, 0.924757629559513910f, + -0.380556601008928520f, + 0.924465474325262600f, -0.381265769222162380f, 0.924172775251791200f, + -0.381974713146567220f, + 0.923879532511286740f, -0.382683432365089780f, 0.923585746276256670f, + -0.383391926460808660f, + 0.923291416719527640f, -0.384100195016935040f, 0.922996544014246250f, + -0.384808237616812880f, + 0.922701128333878630f, -0.385516053843918850f, 0.922405169852209880f, + -0.386223643281862980f, + 0.922108668743345180f, -0.386931005514388580f, 0.921811625181708120f, + -0.387638140125372730f, + 0.921514039342042010f, -0.388345046698826250f, 0.921215911399408730f, + -0.389051724818894380f, + 0.920917241529189520f, -0.389758174069856410f, 0.920618029907083970f, + -0.390464394036126590f, + 0.920318276709110590f, -0.391170384302253870f, 0.920017982111606570f, + -0.391876144452922350f, + 0.919717146291227360f, -0.392581674072951470f, 0.919415769424947070f, + -0.393286972747296400f, + 0.919113851690057770f, -0.393992040061048100f, 0.918811393264170050f, + -0.394696875599433560f, + 0.918508394325212250f, -0.395401478947816350f, 0.918204855051430900f, + -0.396105849691696270f, + 0.917900775621390500f, -0.396809987416710310f, 0.917596156213972950f, + -0.397513891708632330f, + 0.917290997008377910f, -0.398217562153373560f, 0.916985298184123000f, + -0.398920998336982910f, + 0.916679059921042700f, -0.399624199845646790f, 0.916372282399289140f, + -0.400327166265690090f, + 0.916064965799331720f, -0.401029897183575620f, 0.915757110301956720f, + -0.401732392185905010f, + 0.915448716088267830f, -0.402434650859418430f, 0.915139783339685260f, + -0.403136672790995300f, + 0.914830312237946200f, -0.403838457567654070f, 0.914520302965104450f, + -0.404540004776553000f, + 0.914209755703530690f, -0.405241314004989860f, 0.913898670635911680f, + -0.405942384840402510f, + 0.913587047945250810f, -0.406643216870369030f, 0.913274887814867760f, + -0.407343809682607970f, + 0.912962190428398210f, -0.408044162864978690f, 0.912648955969793900f, + -0.408744276005481360f, + 0.912335184623322750f, -0.409444148692257590f, 0.912020876573568340f, + -0.410143780513590240f, + 0.911706032005429880f, -0.410843171057903910f, 0.911390651104122430f, + -0.411542319913765220f, + 0.911074734055176360f, -0.412241226669882890f, 0.910758281044437570f, + -0.412939890915108080f, + 0.910441292258067250f, -0.413638312238434500f, 0.910123767882541680f, + -0.414336490228999100f, + 0.909805708104652220f, -0.415034424476081630f, 0.909487113111505430f, + -0.415732114569105360f, + 0.909167983090522380f, -0.416429560097637150f, 0.908848318229439120f, + -0.417126760651387870f, + 0.908528118716306120f, -0.417823715820212270f, 0.908207384739488700f, + -0.418520425194109700f, + 0.907886116487666260f, -0.419216888363223910f, 0.907564314149832630f, + -0.419913104917843620f, + 0.907241977915295820f, -0.420609074448402510f, 0.906919107973678140f, + -0.421304796545479640f, + 0.906595704514915330f, -0.422000270799799680f, 0.906271767729257660f, + -0.422695496802232950f, + 0.905947297807268460f, -0.423390474143796050f, 0.905622294939825270f, + -0.424085202415651560f, + 0.905296759318118820f, -0.424779681209108810f, 0.904970691133653250f, + -0.425473910115623800f, + 0.904644090578246240f, -0.426167888726799620f, 0.904316957844028320f, + -0.426861616634386430f, + 0.903989293123443340f, -0.427555093430282080f, 0.903661096609247980f, + -0.428248318706531960f, + 0.903332368494511820f, -0.428941292055329490f, 0.903003108972617150f, + -0.429634013069016380f, + 0.902673318237258830f, -0.430326481340082610f, 0.902342996482444200f, + -0.431018696461167030f, + 0.902012143902493180f, -0.431710658025057260f, 0.901680760692037730f, + -0.432402365624690140f, + 0.901348847046022030f, -0.433093818853151960f, 0.901016403159702330f, + -0.433785017303678520f, + 0.900683429228646970f, -0.434475960569655650f, 0.900349925448735600f, + -0.435166648244619260f, + 0.900015892016160280f, -0.435857079922255470f, 0.899681329127423930f, + -0.436547255196401200f, + 0.899346236979341570f, -0.437237173661044090f, 0.899010615769039070f, + -0.437926834910322860f, + 0.898674465693953820f, -0.438616238538527660f, 0.898337786951834310f, + -0.439305384140099950f, + 0.898000579740739880f, -0.439994271309633260f, 0.897662844259040860f, + -0.440682899641872900f, + 0.897324580705418320f, -0.441371268731716670f, 0.896985789278863970f, + -0.442059378174214700f, + 0.896646470178680150f, -0.442747227564570020f, 0.896306623604479550f, + -0.443434816498138480f, + 0.895966249756185220f, -0.444122144570429200f, 0.895625348834030110f, + -0.444809211377104880f, + 0.895283921038557580f, -0.445496016513981740f, 0.894941966570620750f, + -0.446182559577030070f, + 0.894599485631382700f, -0.446868840162374160f, 0.894256478422316040f, + -0.447554857866293010f, + 0.893912945145203250f, -0.448240612285219890f, 0.893568886002135910f, + -0.448926103015743260f, + 0.893224301195515320f, -0.449611329654606540f, 0.892879190928051680f, + -0.450296291798708610f, + 0.892533555402764580f, -0.450980989045103860f, 0.892187394822982480f, + -0.451665420991002490f, + 0.891840709392342720f, -0.452349587233770890f, 0.891493499314791380f, + -0.453033487370931580f, + 0.891145764794583180f, -0.453717121000163870f, 0.890797506036281490f, + -0.454400487719303580f, + 0.890448723244757880f, -0.455083587126343840f, 0.890099416625192320f, + -0.455766418819434640f, + 0.889749586383072780f, -0.456448982396883920f, 0.889399232724195520f, + -0.457131277457156980f, + 0.889048355854664570f, -0.457813303598877170f, 0.888696955980891600f, + -0.458495060420826270f, + 0.888345033309596350f, -0.459176547521944090f, 0.887992588047805560f, + -0.459857764501329540f, + 0.887639620402853930f, -0.460538710958240010f, 0.887286130582383150f, + -0.461219386492092380f, + 0.886932118794342190f, -0.461899790702462730f, 0.886577585246987040f, + -0.462579923189086810f, + 0.886222530148880640f, -0.463259783551860150f, 0.885866953708892790f, + -0.463939371390838520f, + 0.885510856136199950f, -0.464618686306237820f, 0.885154237640285110f, + -0.465297727898434600f, + 0.884797098430937790f, -0.465976495767966180f, 0.884439438718253810f, + -0.466654989515530920f, + 0.884081258712634990f, -0.467333208741988420f, 0.883722558624789660f, + -0.468011153048359830f, + 0.883363338665731580f, -0.468688822035827900f, 0.883003599046780830f, + -0.469366215305737520f, + 0.882643339979562790f, -0.470043332459595620f, 0.882282561676008710f, + -0.470720173099071600f, + 0.881921264348355050f, -0.471396736825997640f, 0.881559448209143780f, + -0.472073023242368660f, + 0.881197113471222090f, -0.472749031950342790f, 0.880834260347742040f, + -0.473424762552241530f, + 0.880470889052160750f, -0.474100214650549970f, 0.880106999798240360f, + -0.474775387847917120f, + 0.879742592800047410f, -0.475450281747155870f, 0.879377668271953290f, + -0.476124895951243580f, + 0.879012226428633530f, -0.476799230063322090f, 0.878646267485068130f, + -0.477473283686698060f, + 0.878279791656541580f, -0.478147056424843010f, 0.877912799158641840f, + -0.478820547881393890f, + 0.877545290207261350f, -0.479493757660153010f, 0.877177265018595940f, + -0.480166685365088390f, + 0.876808723809145650f, -0.480839330600333960f, 0.876439666795713610f, + -0.481511692970189860f, + 0.876070094195406600f, -0.482183772079122720f, 0.875700006225634600f, + -0.482855567531765670f, + 0.875329403104110890f, -0.483527078932918740f, 0.874958285048851650f, + -0.484198305887549030f, + 0.874586652278176110f, -0.484869248000791060f, 0.874214505010706300f, + -0.485539904877946960f, + 0.873841843465366860f, -0.486210276124486420f, 0.873468667861384880f, + -0.486880361346047340f, + 0.873094978418290090f, -0.487550160148436000f, 0.872720775355914300f, + -0.488219672137626790f, + 0.872346058894391540f, -0.488888896919763170f, 0.871970829254157810f, + -0.489557834101157440f, + 0.871595086655950980f, -0.490226483288291160f, 0.871218831320811020f, + -0.490894844087815090f, + 0.870842063470078980f, -0.491562916106549900f, 0.870464783325397670f, + -0.492230698951486020f, + 0.870086991108711460f, -0.492898192229784040f, 0.869708687042265670f, + -0.493565395548774770f, + 0.869329871348606840f, -0.494232308515959670f, 0.868950544250582380f, + -0.494898930739011260f, + 0.868570705971340900f, -0.495565261825772540f, 0.868190356734331310f, + -0.496231301384258250f, + 0.867809496763303320f, -0.496897049022654470f, 0.867428126282306920f, + -0.497562504349319150f, + 0.867046245515692650f, -0.498227666972781870f, 0.866663854688111130f, + -0.498892536501744590f, + 0.866280954024512990f, -0.499557112545081840f, 0.865897543750148820f, + -0.500221394711840680f, + 0.865513624090569090f, -0.500885382611240710f, 0.865129195271623800f, + -0.501549075852675390f, + 0.864744257519462380f, -0.502212474045710790f, 0.864358811060534030f, + -0.502875576800086990f, + 0.863972856121586810f, -0.503538383725717580f, 0.863586392929668100f, + -0.504200894432690340f, + 0.863199421712124160f, -0.504863108531267590f, 0.862811942696600330f, + -0.505525025631885390f, + 0.862423956111040610f, -0.506186645345155230f, 0.862035462183687210f, + -0.506847967281863210f, + 0.861646461143081300f, -0.507508991052970870f, 0.861256953218062170f, + -0.508169716269614600f, + 0.860866938637767310f, -0.508830142543106990f, 0.860476417631632070f, + -0.509490269484936360f, + 0.860085390429390140f, -0.510150096706766810f, 0.859693857261072610f, + -0.510809623820439040f, + 0.859301818357008470f, -0.511468850437970300f, 0.858909273947823900f, + -0.512127776171554690f, + 0.858516224264442740f, -0.512786400633562960f, 0.858122669538086140f, + -0.513444723436543460f, + 0.857728610000272120f, -0.514102744193221660f, 0.857334045882815590f, + -0.514760462516501200f, + 0.856938977417828760f, -0.515417878019462930f, 0.856543404837719960f, + -0.516074990315366630f, + 0.856147328375194470f, -0.516731799017649870f, 0.855750748263253920f, + -0.517388303739929060f, + 0.855353664735196030f, -0.518044504095999340f, 0.854956078024614930f, + -0.518700399699834950f, + 0.854557988365400530f, -0.519355990165589640f, 0.854159395991738850f, + -0.520011275107596040f, + 0.853760301138111410f, -0.520666254140367160f, 0.853360704039295430f, + -0.521320926878595660f, + 0.852960604930363630f, -0.521975292937154390f, 0.852560004046684080f, + -0.522629351931096610f, + 0.852158901623919830f, -0.523283103475656430f, 0.851757297898029120f, + -0.523936547186248600f, + 0.851355193105265200f, -0.524589682678468950f, 0.850952587482175730f, + -0.525242509568094710f, + 0.850549481265603480f, -0.525895027471084630f, 0.850145874692685210f, + -0.526547236003579440f, + 0.849741768000852550f, -0.527199134781901280f, 0.849337161427830780f, + -0.527850723422555230f, + 0.848932055211639610f, -0.528502001542228480f, 0.848526449590592650f, + -0.529152968757790610f, + 0.848120344803297230f, -0.529803624686294610f, 0.847713741088654380f, + -0.530453968944976320f, + 0.847306638685858320f, -0.531104001151255000f, 0.846899037834397240f, + -0.531753720922733320f, + 0.846490938774052130f, -0.532403127877197900f, 0.846082341744897050f, + -0.533052221632619450f, + 0.845673246987299070f, -0.533701001807152960f, 0.845263654741918220f, + -0.534349468019137520f, + 0.844853565249707120f, -0.534997619887097150f, 0.844442978751910660f, + -0.535645457029741090f, + 0.844031895490066410f, -0.536292979065963180f, 0.843620315706004150f, + -0.536940185614842910f, + 0.843208239641845440f, -0.537587076295645390f, 0.842795667540004120f, + -0.538233650727821700f, + 0.842382599643185850f, -0.538879908531008420f, 0.841969036194387680f, + -0.539525849325028890f, + 0.841554977436898440f, -0.540171472729892850f, 0.841140423614298080f, + -0.540816778365796670f, + 0.840725374970458070f, -0.541461765853123440f, 0.840309831749540770f, + -0.542106434812443920f, + 0.839893794195999520f, -0.542750784864515890f, 0.839477262554578550f, + -0.543394815630284800f, + 0.839060237070312740f, -0.544038526730883820f, 0.838642717988527300f, + -0.544681917787634530f, + 0.838224705554838080f, -0.545324988422046460f, 0.837806200015150940f, + -0.545967738255817570f, + 0.837387201615661940f, -0.546610166910834860f, 0.836967710602857020f, + -0.547252274009174090f, + 0.836547727223512010f, -0.547894059173100190f, 0.836127251724692270f, + -0.548535522025067390f, + 0.835706284353752600f, -0.549176662187719660f, 0.835284825358337370f, + -0.549817479283890910f, + 0.834862874986380010f, -0.550457972936604810f, 0.834440433486103190f, + -0.551098142769075430f, + 0.834017501106018130f, -0.551737988404707340f, 0.833594078094925140f, + -0.552377509467096070f, + 0.833170164701913190f, -0.553016705580027470f, 0.832745761176359460f, + -0.553655576367479310f, + 0.832320867767929680f, -0.554294121453620000f, 0.831895484726577590f, + -0.554932340462810370f, + 0.831469612302545240f, -0.555570233019602180f, 0.831043250746362320f, + -0.556207798748739930f, + 0.830616400308846310f, -0.556845037275160100f, 0.830189061241102370f, + -0.557481948223991550f, + 0.829761233794523050f, -0.558118531220556100f, 0.829332918220788250f, + -0.558754785890368310f, + 0.828904114771864870f, -0.559390711859136140f, 0.828474823700007130f, + -0.560026308752760380f, + 0.828045045257755800f, -0.560661576197336030f, 0.827614779697938400f, + -0.561296513819151470f, + 0.827184027273669130f, -0.561931121244689470f, 0.826752788238348520f, + -0.562565398100626560f, + 0.826321062845663530f, -0.563199344013834090f, 0.825888851349586780f, + -0.563832958611378170f, + 0.825456154004377550f, -0.564466241520519500f, 0.825022971064580220f, + -0.565099192368713980f, + 0.824589302785025290f, -0.565731810783613120f, 0.824155149420828570f, + -0.566364096393063840f, + 0.823720511227391430f, -0.566996048825108680f, 0.823285388460400110f, + -0.567627667707986230f, + 0.822849781375826430f, -0.568258952670131490f, 0.822413690229926390f, + -0.568889903340175860f, + 0.821977115279241550f, -0.569520519346947140f, 0.821540056780597610f, + -0.570150800319470300f, + 0.821102514991104650f, -0.570780745886967260f, 0.820664490168157460f, + -0.571410355678857230f, + 0.820225982569434690f, -0.572039629324757050f, 0.819786992452898990f, + -0.572668566454481160f, + 0.819347520076796900f, -0.573297166698042200f, 0.818907565699658950f, + -0.573925429685650750f, + 0.818467129580298660f, -0.574553355047715760f, 0.818026211977813440f, + -0.575180942414845080f, + 0.817584813151583710f, -0.575808191417845340f, 0.817142933361272970f, + -0.576435101687721830f, + 0.816700572866827850f, -0.577061672855679440f, 0.816257731928477390f, + -0.577687904553122800f, + 0.815814410806733780f, -0.578313796411655590f, 0.815370609762391290f, + -0.578939348063081780f, + 0.814926329056526620f, -0.579564559139405630f, 0.814481568950498610f, + -0.580189429272831680f, + 0.814036329705948410f, -0.580813958095764530f, 0.813590611584798510f, + -0.581438145240810170f, + 0.813144414849253590f, -0.582061990340775440f, 0.812697739761799490f, + -0.582685493028668460f, + 0.812250586585203880f, -0.583308652937698290f, 0.811802955582515470f, + -0.583931469701276180f, + 0.811354847017063730f, -0.584553942953015330f, 0.810906261152459670f, + -0.585176072326730410f, + 0.810457198252594770f, -0.585797857456438860f, 0.810007658581641140f, + -0.586419297976360500f, + 0.809557642404051260f, -0.587040393520917970f, 0.809107149984558240f, + -0.587661143724736660f, + 0.808656181588174980f, -0.588281548222645220f, 0.808204737480194720f, + -0.588901606649675720f, + 0.807752817926190360f, -0.589521318641063940f, 0.807300423192014450f, + -0.590140683832248820f, + 0.806847553543799330f, -0.590759701858874160f, 0.806394209247956240f, + -0.591378372356787580f, + 0.805940390571176280f, -0.591996694962040990f, 0.805486097780429230f, + -0.592614669310891130f, + 0.805031331142963660f, -0.593232295039799800f, 0.804576090926307110f, + -0.593849571785433630f, + 0.804120377398265810f, -0.594466499184664430f, 0.803664190826924090f, + -0.595083076874569960f, + 0.803207531480644940f, -0.595699304492433360f, 0.802750399628069160f, + -0.596315181675743710f, + 0.802292795538115720f, -0.596930708062196500f, 0.801834719479981310f, + -0.597545883289693160f, + 0.801376171723140240f, -0.598160706996342270f, 0.800917152537344300f, + -0.598775178820458720f, + 0.800457662192622820f, -0.599389298400564540f, 0.799997700959281910f, + -0.600003065375388940f, + 0.799537269107905010f, -0.600616479383868970f, 0.799076366909352350f, + -0.601229540065148500f, + 0.798614994634760820f, -0.601842247058580030f, 0.798153152555543750f, + -0.602454600003723750f, + 0.797690840943391160f, -0.603066598540348160f, 0.797228060070268810f, + -0.603678242308430370f, + 0.796764810208418830f, -0.604289530948155960f, 0.796301091630359110f, + -0.604900464099919820f, + 0.795836904608883570f, -0.605511041404325550f, 0.795372249417061310f, + -0.606121262502186120f, + 0.794907126328237010f, -0.606731127034524480f, 0.794441535616030590f, + -0.607340634642572930f, + 0.793975477554337170f, -0.607949784967773630f, 0.793508952417326660f, + -0.608558577651779450f, + 0.793041960479443640f, -0.609167012336453210f, 0.792574502015407690f, + -0.609775088663868430f, + 0.792106577300212390f, -0.610382806276309480f, 0.791638186609125880f, + -0.610990164816271660f, + 0.791169330217690200f, -0.611597163926461910f, 0.790700008401721610f, + -0.612203803249797950f, + 0.790230221437310030f, -0.612810082429409710f, 0.789759969600819070f, + -0.613416001108638590f, + 0.789289253168885650f, -0.614021558931038380f, 0.788818072418420280f, + -0.614626755540375050f, + 0.788346427626606340f, -0.615231590580626820f, 0.787874319070900220f, + -0.615836063695985090f, + 0.787401747029031430f, -0.616440174530853650f, 0.786928711779001810f, + -0.617043922729849760f, + 0.786455213599085770f, -0.617647307937803870f, 0.785981252767830150f, + -0.618250329799760250f, + 0.785506829564053930f, -0.618852987960976320f, 0.785031944266848080f, + -0.619455282066924020f, + 0.784556597155575240f, -0.620057211763289100f, 0.784080788509869950f, + -0.620658776695972140f, + 0.783604518609638200f, -0.621259976511087550f, 0.783127787735057310f, + -0.621860810854965360f, + 0.782650596166575730f, -0.622461279374149970f, 0.782172944184913010f, + -0.623061381715401260f, + 0.781694832071059390f, -0.623661117525694530f, 0.781216260106276090f, + -0.624260486452220650f, + 0.780737228572094490f, -0.624859488142386340f, 0.780257737750316590f, + -0.625458122243814360f, + 0.779777787923014550f, -0.626056388404343520f, 0.779297379372530300f, + -0.626654286272029350f, + 0.778816512381475980f, -0.627251815495144080f, 0.778335187232733210f, + -0.627848975722176460f, + 0.777853404209453150f, -0.628445766601832710f, 0.777371163595056310f, + -0.629042187783036000f, + 0.776888465673232440f, -0.629638238914926980f, 0.776405310727940390f, + -0.630233919646864370f, + 0.775921699043407690f, -0.630829229628424470f, 0.775437630904130540f, + -0.631424168509401860f, + 0.774953106594873930f, -0.632018735939809060f, 0.774468126400670860f, + -0.632612931569877410f, + 0.773982690606822900f, -0.633206755050057190f, 0.773496799498899050f, + -0.633800206031017280f, + 0.773010453362736990f, -0.634393284163645490f, 0.772523652484441330f, + -0.634985989099049460f, + 0.772036397150384520f, -0.635578320488556110f, 0.771548687647206300f, + -0.636170277983712170f, + 0.771060524261813820f, -0.636761861236284200f, 0.770571907281380810f, + -0.637353069898259130f, + 0.770082836993347900f, -0.637943903621844060f, 0.769593313685422940f, + -0.638534362059466790f, + 0.769103337645579700f, -0.639124444863775730f, 0.768612909162058380f, + -0.639714151687640450f, + 0.768122028523365420f, -0.640303482184151670f, 0.767630696018273380f, + -0.640892436006621380f, + 0.767138911935820400f, -0.641481012808583160f, 0.766646676565310380f, + -0.642069212243792540f, + 0.766153990196312920f, -0.642657033966226860f, 0.765660853118662500f, + -0.643244477630085850f, + 0.765167265622458960f, -0.643831542889791390f, 0.764673227998067140f, + -0.644418229399988380f, + 0.764178740536116670f, -0.645004536815543930f, 0.763683803527501870f, + -0.645590464791548690f, + 0.763188417263381270f, -0.646176012983316280f, 0.762692582035177980f, + -0.646761181046383920f, + 0.762196298134578900f, -0.647345968636512060f, 0.761699565853535380f, + -0.647930375409685340f, + 0.761202385484261780f, -0.648514401022112440f, 0.760704757319236920f, + -0.649098045130225950f, + 0.760206681651202420f, -0.649681307390683190f, 0.759708158773163440f, + -0.650264187460365850f, + 0.759209188978388070f, -0.650846684996380880f, 0.758709772560407390f, + -0.651428799656059820f, + 0.758209909813015280f, -0.652010531096959500f, 0.757709601030268080f, + -0.652591878976862440f, + 0.757208846506484570f, -0.653172842953776760f, 0.756707646536245670f, + -0.653753422685936060f, + 0.756206001414394540f, -0.654333617831800440f, 0.755703911436035880f, + -0.654913428050056030f, + 0.755201376896536550f, -0.655492852999615350f, 0.754698398091524500f, + -0.656071892339617600f, + 0.754194975316889170f, -0.656650545729428940f, 0.753691108868781210f, + -0.657228812828642540f, + 0.753186799043612520f, -0.657806693297078640f, 0.752682046138055340f, + -0.658384186794785050f, + 0.752176850449042810f, -0.658961292982037320f, 0.751671212273768430f, + -0.659538011519338660f, + 0.751165131909686480f, -0.660114342067420480f, 0.750658609654510700f, + -0.660690284287242300f, + 0.750151645806215070f, -0.661265837839992270f, 0.749644240663033480f, + -0.661841002387086870f, + 0.749136394523459370f, -0.662415777590171780f, 0.748628107686245440f, + -0.662990163111121470f, + 0.748119380450403600f, -0.663564158612039770f, 0.747610213115205150f, + -0.664137763755260010f, + 0.747100605980180130f, -0.664710978203344790f, 0.746590559345117310f, + -0.665283801619087180f, + 0.746080073510063780f, -0.665856233665509720f, 0.745569148775325430f, + -0.666428274005865240f, + 0.745057785441466060f, -0.666999922303637470f, 0.744545983809307370f, + -0.667571178222540310f, + 0.744033744179929290f, -0.668142041426518450f, 0.743521066854669120f, + -0.668712511579747980f, + 0.743007952135121720f, -0.669282588346636010f, 0.742494400323139180f, + -0.669852271391821020f, + 0.741980411720831070f, -0.670421560380173090f, 0.741465986630563290f, + -0.670990454976794220f, + 0.740951125354959110f, -0.671558954847018330f, 0.740435828196898020f, + -0.672127059656411730f, + 0.739920095459516200f, -0.672694769070772860f, 0.739403927446205760f, + -0.673262082756132970f, + 0.738887324460615110f, -0.673829000378756040f, 0.738370286806648620f, + -0.674395521605139050f, + 0.737852814788465980f, -0.674961646102011930f, 0.737334908710482910f, + -0.675527373536338520f, + 0.736816568877369900f, -0.676092703575315920f, 0.736297795594053170f, + -0.676657635886374950f, + 0.735778589165713590f, -0.677222170137180330f, 0.735258949897786840f, + -0.677786305995631500f, + 0.734738878095963500f, -0.678350043129861470f, 0.734218374066188280f, + -0.678913381208238410f, + 0.733697438114660370f, -0.679476319899364970f, 0.733176070547832740f, + -0.680038858872078930f, + 0.732654271672412820f, -0.680600997795453020f, 0.732132041795361290f, + -0.681162736338795430f, + 0.731609381223892630f, -0.681724074171649710f, 0.731086290265474340f, + -0.682285010963795570f, + 0.730562769227827590f, -0.682845546385248080f, 0.730038818418926260f, + -0.683405680106258680f, + 0.729514438146997010f, -0.683965411797315400f, 0.728989628720519420f, + -0.684524741129142300f, + 0.728464390448225200f, -0.685083667772700360f, 0.727938723639098620f, + -0.685642191399187470f, + 0.727412628602375770f, -0.686200311680038590f, 0.726886105647544970f, + -0.686758028286925890f, + 0.726359155084346010f, -0.687315340891759050f, 0.725831777222770370f, + -0.687872249166685550f, + 0.725303972373060770f, -0.688428752784090440f, 0.724775740845711280f, + -0.688984851416597040f, + 0.724247082951467000f, -0.689540544737066830f, 0.723717999001323500f, + -0.690095832418599950f, + 0.723188489306527460f, -0.690650714134534600f, 0.722658554178575610f, + -0.691205189558448450f, + 0.722128193929215350f, -0.691759258364157750f, 0.721597408870443770f, + -0.692312920225718220f, + 0.721066199314508110f, -0.692866174817424630f, 0.720534565573905270f, + -0.693419021813811760f, + 0.720002507961381650f, -0.693971460889654000f, 0.719470026789932990f, + -0.694523491719965520f, + 0.718937122372804490f, -0.695075113980000880f, 0.718403795023489830f, + -0.695626327345254870f, + 0.717870045055731710f, -0.696177131491462990f, 0.717335872783521730f, + -0.696727526094601200f, + 0.716801278521099540f, -0.697277510830886520f, 0.716266262582953120f, + -0.697827085376777290f, + 0.715730825283818590f, -0.698376249408972920f, 0.715194966938680120f, + -0.698925002604414150f, + 0.714658687862769090f, -0.699473344640283770f, 0.714121988371564820f, + -0.700021275194006250f, + 0.713584868780793640f, -0.700568793943248340f, 0.713047329406429340f, + -0.701115900565918660f, + 0.712509370564692320f, -0.701662594740168450f, 0.711970992572050100f, + -0.702208876144391870f, + 0.711432195745216430f, -0.702754744457225300f, 0.710892980401151680f, + -0.703300199357548730f, + 0.710353346857062420f, -0.703845240524484940f, 0.709813295430400840f, + -0.704389867637400410f, + 0.709272826438865690f, -0.704934080375904880f, 0.708731940200400650f, + -0.705477878419852100f, + 0.708190637033195400f, -0.706021261449339740f, 0.707648917255684350f, + -0.706564229144709510f, + 0.707106781186547570f, -0.707106781186547460f, 0.706564229144709620f, + -0.707648917255684350f, + 0.706021261449339740f, -0.708190637033195290f, 0.705477878419852210f, + -0.708731940200400650f, + 0.704934080375904990f, -0.709272826438865580f, 0.704389867637400410f, + -0.709813295430400840f, + 0.703845240524484940f, -0.710353346857062310f, 0.703300199357548730f, + -0.710892980401151680f, + 0.702754744457225300f, -0.711432195745216430f, 0.702208876144391870f, + -0.711970992572049990f, + 0.701662594740168570f, -0.712509370564692320f, 0.701115900565918660f, + -0.713047329406429230f, + 0.700568793943248450f, -0.713584868780793520f, 0.700021275194006360f, + -0.714121988371564710f, + 0.699473344640283770f, -0.714658687862768980f, 0.698925002604414150f, + -0.715194966938680010f, + 0.698376249408972920f, -0.715730825283818590f, 0.697827085376777290f, + -0.716266262582953120f, + 0.697277510830886630f, -0.716801278521099540f, 0.696727526094601200f, + -0.717335872783521730f, + 0.696177131491462990f, -0.717870045055731710f, 0.695626327345254870f, + -0.718403795023489720f, + 0.695075113980000880f, -0.718937122372804380f, 0.694523491719965520f, + -0.719470026789932990f, + 0.693971460889654000f, -0.720002507961381650f, 0.693419021813811880f, + -0.720534565573905270f, + 0.692866174817424740f, -0.721066199314508110f, 0.692312920225718220f, + -0.721597408870443660f, + 0.691759258364157750f, -0.722128193929215350f, 0.691205189558448450f, + -0.722658554178575610f, + 0.690650714134534720f, -0.723188489306527350f, 0.690095832418599950f, + -0.723717999001323390f, + 0.689540544737066940f, -0.724247082951466890f, 0.688984851416597150f, + -0.724775740845711280f, + 0.688428752784090550f, -0.725303972373060660f, 0.687872249166685550f, + -0.725831777222770370f, + 0.687315340891759160f, -0.726359155084346010f, 0.686758028286925890f, + -0.726886105647544970f, + 0.686200311680038700f, -0.727412628602375770f, 0.685642191399187470f, + -0.727938723639098620f, + 0.685083667772700360f, -0.728464390448225200f, 0.684524741129142300f, + -0.728989628720519310f, + 0.683965411797315510f, -0.729514438146996900f, 0.683405680106258790f, + -0.730038818418926150f, + 0.682845546385248080f, -0.730562769227827590f, 0.682285010963795570f, + -0.731086290265474230f, + 0.681724074171649820f, -0.731609381223892520f, 0.681162736338795430f, + -0.732132041795361290f, + 0.680600997795453130f, -0.732654271672412820f, 0.680038858872079040f, + -0.733176070547832740f, + 0.679476319899365080f, -0.733697438114660260f, 0.678913381208238410f, + -0.734218374066188170f, + 0.678350043129861580f, -0.734738878095963390f, 0.677786305995631500f, + -0.735258949897786730f, + 0.677222170137180450f, -0.735778589165713480f, 0.676657635886374950f, + -0.736297795594053060f, + 0.676092703575316030f, -0.736816568877369790f, 0.675527373536338630f, + -0.737334908710482790f, + 0.674961646102012040f, -0.737852814788465980f, 0.674395521605139050f, + -0.738370286806648510f, + 0.673829000378756150f, -0.738887324460615110f, 0.673262082756132970f, + -0.739403927446205760f, + 0.672694769070772970f, -0.739920095459516090f, 0.672127059656411840f, + -0.740435828196898020f, + 0.671558954847018330f, -0.740951125354959110f, 0.670990454976794220f, + -0.741465986630563290f, + 0.670421560380173090f, -0.741980411720830960f, 0.669852271391821130f, + -0.742494400323139180f, + 0.669282588346636010f, -0.743007952135121720f, 0.668712511579748090f, + -0.743521066854669120f, + 0.668142041426518560f, -0.744033744179929180f, 0.667571178222540310f, + -0.744545983809307250f, + 0.666999922303637470f, -0.745057785441465950f, 0.666428274005865350f, + -0.745569148775325430f, + 0.665856233665509720f, -0.746080073510063780f, 0.665283801619087180f, + -0.746590559345117310f, + 0.664710978203344900f, -0.747100605980180130f, 0.664137763755260010f, + -0.747610213115205150f, + 0.663564158612039880f, -0.748119380450403490f, 0.662990163111121470f, + -0.748628107686245330f, + 0.662415777590171780f, -0.749136394523459260f, 0.661841002387086870f, + -0.749644240663033480f, + 0.661265837839992270f, -0.750151645806214960f, 0.660690284287242300f, + -0.750658609654510590f, + 0.660114342067420480f, -0.751165131909686370f, 0.659538011519338770f, + -0.751671212273768430f, + 0.658961292982037320f, -0.752176850449042700f, 0.658384186794785050f, + -0.752682046138055230f, + 0.657806693297078640f, -0.753186799043612410f, 0.657228812828642650f, + -0.753691108868781210f, + 0.656650545729429050f, -0.754194975316889170f, 0.656071892339617710f, + -0.754698398091524390f, + 0.655492852999615460f, -0.755201376896536550f, 0.654913428050056150f, + -0.755703911436035880f, + 0.654333617831800550f, -0.756206001414394540f, 0.653753422685936170f, + -0.756707646536245670f, + 0.653172842953776760f, -0.757208846506484460f, 0.652591878976862550f, + -0.757709601030268080f, + 0.652010531096959500f, -0.758209909813015280f, 0.651428799656059820f, + -0.758709772560407390f, + 0.650846684996380990f, -0.759209188978387960f, 0.650264187460365960f, + -0.759708158773163440f, + 0.649681307390683190f, -0.760206681651202420f, 0.649098045130226060f, + -0.760704757319236920f, + 0.648514401022112550f, -0.761202385484261780f, 0.647930375409685460f, + -0.761699565853535270f, + 0.647345968636512060f, -0.762196298134578900f, 0.646761181046383920f, + -0.762692582035177870f, + 0.646176012983316390f, -0.763188417263381270f, 0.645590464791548800f, + -0.763683803527501870f, + 0.645004536815544040f, -0.764178740536116670f, 0.644418229399988380f, + -0.764673227998067140f, + 0.643831542889791500f, -0.765167265622458960f, 0.643244477630085850f, + -0.765660853118662390f, + 0.642657033966226860f, -0.766153990196312810f, 0.642069212243792540f, + -0.766646676565310380f, + 0.641481012808583160f, -0.767138911935820400f, 0.640892436006621380f, + -0.767630696018273270f, + 0.640303482184151670f, -0.768122028523365310f, 0.639714151687640450f, + -0.768612909162058270f, + 0.639124444863775730f, -0.769103337645579590f, 0.638534362059466790f, + -0.769593313685422940f, + 0.637943903621844170f, -0.770082836993347900f, 0.637353069898259130f, + -0.770571907281380700f, + 0.636761861236284200f, -0.771060524261813710f, 0.636170277983712170f, + -0.771548687647206300f, + 0.635578320488556230f, -0.772036397150384410f, 0.634985989099049460f, + -0.772523652484441330f, + 0.634393284163645490f, -0.773010453362736990f, 0.633800206031017280f, + -0.773496799498899050f, + 0.633206755050057190f, -0.773982690606822790f, 0.632612931569877520f, + -0.774468126400670860f, + 0.632018735939809060f, -0.774953106594873820f, 0.631424168509401860f, + -0.775437630904130430f, + 0.630829229628424470f, -0.775921699043407580f, 0.630233919646864480f, + -0.776405310727940390f, + 0.629638238914927100f, -0.776888465673232440f, 0.629042187783036000f, + -0.777371163595056200f, + 0.628445766601832710f, -0.777853404209453040f, 0.627848975722176570f, + -0.778335187232733090f, + 0.627251815495144190f, -0.778816512381475870f, 0.626654286272029460f, + -0.779297379372530300f, + 0.626056388404343520f, -0.779777787923014440f, 0.625458122243814360f, + -0.780257737750316590f, + 0.624859488142386450f, -0.780737228572094380f, 0.624260486452220650f, + -0.781216260106276090f, + 0.623661117525694640f, -0.781694832071059390f, 0.623061381715401370f, + -0.782172944184912900f, + 0.622461279374150080f, -0.782650596166575730f, 0.621860810854965360f, + -0.783127787735057310f, + 0.621259976511087660f, -0.783604518609638200f, 0.620658776695972140f, + -0.784080788509869950f, + 0.620057211763289210f, -0.784556597155575240f, 0.619455282066924020f, + -0.785031944266848080f, + 0.618852987960976320f, -0.785506829564053930f, 0.618250329799760250f, + -0.785981252767830150f, + 0.617647307937803980f, -0.786455213599085770f, 0.617043922729849760f, + -0.786928711779001700f, + 0.616440174530853650f, -0.787401747029031320f, 0.615836063695985090f, + -0.787874319070900110f, + 0.615231590580626820f, -0.788346427626606230f, 0.614626755540375050f, + -0.788818072418420170f, + 0.614021558931038490f, -0.789289253168885650f, 0.613416001108638590f, + -0.789759969600819070f, + 0.612810082429409710f, -0.790230221437310030f, 0.612203803249798060f, + -0.790700008401721610f, + 0.611597163926462020f, -0.791169330217690090f, 0.610990164816271770f, + -0.791638186609125770f, + 0.610382806276309480f, -0.792106577300212390f, 0.609775088663868430f, + -0.792574502015407580f, + 0.609167012336453210f, -0.793041960479443640f, 0.608558577651779450f, + -0.793508952417326660f, + 0.607949784967773740f, -0.793975477554337170f, 0.607340634642572930f, + -0.794441535616030590f, + 0.606731127034524480f, -0.794907126328237010f, 0.606121262502186230f, + -0.795372249417061190f, + 0.605511041404325550f, -0.795836904608883460f, 0.604900464099919930f, + -0.796301091630359110f, + 0.604289530948156070f, -0.796764810208418720f, 0.603678242308430370f, + -0.797228060070268700f, + 0.603066598540348280f, -0.797690840943391040f, 0.602454600003723860f, + -0.798153152555543750f, + 0.601842247058580030f, -0.798614994634760820f, 0.601229540065148620f, + -0.799076366909352350f, + 0.600616479383868970f, -0.799537269107905010f, 0.600003065375389060f, + -0.799997700959281910f, + 0.599389298400564540f, -0.800457662192622710f, 0.598775178820458720f, + -0.800917152537344300f, + 0.598160706996342380f, -0.801376171723140130f, 0.597545883289693270f, + -0.801834719479981310f, + 0.596930708062196500f, -0.802292795538115720f, 0.596315181675743820f, + -0.802750399628069160f, + 0.595699304492433470f, -0.803207531480644830f, 0.595083076874569960f, + -0.803664190826924090f, + 0.594466499184664540f, -0.804120377398265700f, 0.593849571785433630f, + -0.804576090926307000f, + 0.593232295039799800f, -0.805031331142963660f, 0.592614669310891130f, + -0.805486097780429120f, + 0.591996694962040990f, -0.805940390571176280f, 0.591378372356787580f, + -0.806394209247956240f, + 0.590759701858874280f, -0.806847553543799220f, 0.590140683832248940f, + -0.807300423192014450f, + 0.589521318641063940f, -0.807752817926190360f, 0.588901606649675840f, + -0.808204737480194720f, + 0.588281548222645330f, -0.808656181588174980f, 0.587661143724736770f, + -0.809107149984558130f, + 0.587040393520918080f, -0.809557642404051260f, 0.586419297976360500f, + -0.810007658581641140f, + 0.585797857456438860f, -0.810457198252594770f, 0.585176072326730410f, + -0.810906261152459670f, + 0.584553942953015330f, -0.811354847017063730f, 0.583931469701276300f, + -0.811802955582515360f, + 0.583308652937698290f, -0.812250586585203880f, 0.582685493028668460f, + -0.812697739761799490f, + 0.582061990340775550f, -0.813144414849253590f, 0.581438145240810280f, + -0.813590611584798510f, + 0.580813958095764530f, -0.814036329705948300f, 0.580189429272831680f, + -0.814481568950498610f, + 0.579564559139405740f, -0.814926329056526620f, 0.578939348063081890f, + -0.815370609762391290f, + 0.578313796411655590f, -0.815814410806733780f, 0.577687904553122800f, + -0.816257731928477390f, + 0.577061672855679550f, -0.816700572866827850f, 0.576435101687721830f, + -0.817142933361272970f, + 0.575808191417845340f, -0.817584813151583710f, 0.575180942414845190f, + -0.818026211977813440f, + 0.574553355047715760f, -0.818467129580298660f, 0.573925429685650750f, + -0.818907565699658950f, + 0.573297166698042320f, -0.819347520076796900f, 0.572668566454481160f, + -0.819786992452898990f, + 0.572039629324757050f, -0.820225982569434690f, 0.571410355678857340f, + -0.820664490168157460f, + 0.570780745886967370f, -0.821102514991104650f, 0.570150800319470300f, + -0.821540056780597610f, + 0.569520519346947250f, -0.821977115279241550f, 0.568889903340175970f, + -0.822413690229926390f, + 0.568258952670131490f, -0.822849781375826320f, 0.567627667707986230f, + -0.823285388460400110f, + 0.566996048825108680f, -0.823720511227391320f, 0.566364096393063950f, + -0.824155149420828570f, + 0.565731810783613230f, -0.824589302785025290f, 0.565099192368714090f, + -0.825022971064580220f, + 0.564466241520519500f, -0.825456154004377440f, 0.563832958611378170f, + -0.825888851349586780f, + 0.563199344013834090f, -0.826321062845663420f, 0.562565398100626560f, + -0.826752788238348520f, + 0.561931121244689470f, -0.827184027273669020f, 0.561296513819151470f, + -0.827614779697938400f, + 0.560661576197336030f, -0.828045045257755800f, 0.560026308752760380f, + -0.828474823700007130f, + 0.559390711859136140f, -0.828904114771864870f, 0.558754785890368310f, + -0.829332918220788250f, + 0.558118531220556100f, -0.829761233794523050f, 0.557481948223991660f, + -0.830189061241102370f, + 0.556845037275160100f, -0.830616400308846200f, 0.556207798748739930f, + -0.831043250746362320f, + 0.555570233019602290f, -0.831469612302545240f, 0.554932340462810370f, + -0.831895484726577590f, + 0.554294121453620110f, -0.832320867767929680f, 0.553655576367479310f, + -0.832745761176359460f, + 0.553016705580027580f, -0.833170164701913190f, 0.552377509467096070f, + -0.833594078094925140f, + 0.551737988404707450f, -0.834017501106018130f, 0.551098142769075430f, + -0.834440433486103190f, + 0.550457972936604810f, -0.834862874986380010f, 0.549817479283891020f, + -0.835284825358337370f, + 0.549176662187719770f, -0.835706284353752600f, 0.548535522025067390f, + -0.836127251724692160f, + 0.547894059173100190f, -0.836547727223511890f, 0.547252274009174090f, + -0.836967710602857020f, + 0.546610166910834860f, -0.837387201615661940f, 0.545967738255817680f, + -0.837806200015150940f, + 0.545324988422046460f, -0.838224705554837970f, 0.544681917787634530f, + -0.838642717988527300f, + 0.544038526730883930f, -0.839060237070312630f, 0.543394815630284800f, + -0.839477262554578550f, + 0.542750784864516000f, -0.839893794195999410f, 0.542106434812444030f, + -0.840309831749540770f, + 0.541461765853123560f, -0.840725374970458070f, 0.540816778365796670f, + -0.841140423614298080f, + 0.540171472729892970f, -0.841554977436898330f, 0.539525849325029010f, + -0.841969036194387680f, + 0.538879908531008420f, -0.842382599643185960f, 0.538233650727821700f, + -0.842795667540004120f, + 0.537587076295645510f, -0.843208239641845440f, 0.536940185614843020f, + -0.843620315706004040f, + 0.536292979065963180f, -0.844031895490066410f, 0.535645457029741090f, + -0.844442978751910660f, + 0.534997619887097260f, -0.844853565249707010f, 0.534349468019137520f, + -0.845263654741918220f, + 0.533701001807152960f, -0.845673246987299070f, 0.533052221632619670f, + -0.846082341744896940f, + 0.532403127877198010f, -0.846490938774052020f, 0.531753720922733320f, + -0.846899037834397350f, + 0.531104001151255000f, -0.847306638685858320f, 0.530453968944976320f, + -0.847713741088654270f, + 0.529803624686294830f, -0.848120344803297120f, 0.529152968757790720f, + -0.848526449590592650f, + 0.528502001542228480f, -0.848932055211639610f, 0.527850723422555460f, + -0.849337161427830670f, + 0.527199134781901390f, -0.849741768000852440f, 0.526547236003579330f, + -0.850145874692685210f, + 0.525895027471084740f, -0.850549481265603370f, 0.525242509568094710f, + -0.850952587482175730f, + 0.524589682678468840f, -0.851355193105265200f, 0.523936547186248600f, + -0.851757297898029120f, + 0.523283103475656430f, -0.852158901623919830f, 0.522629351931096720f, + -0.852560004046683970f, + 0.521975292937154390f, -0.852960604930363630f, 0.521320926878595550f, + -0.853360704039295430f, + 0.520666254140367270f, -0.853760301138111300f, 0.520011275107596040f, + -0.854159395991738730f, + 0.519355990165589530f, -0.854557988365400530f, 0.518700399699835170f, + -0.854956078024614820f, + 0.518044504095999340f, -0.855353664735196030f, 0.517388303739929060f, + -0.855750748263253920f, + 0.516731799017649980f, -0.856147328375194470f, 0.516074990315366630f, + -0.856543404837719960f, + 0.515417878019463150f, -0.856938977417828650f, 0.514760462516501200f, + -0.857334045882815590f, + 0.514102744193221660f, -0.857728610000272120f, 0.513444723436543570f, + -0.858122669538086020f, + 0.512786400633563070f, -0.858516224264442740f, 0.512127776171554690f, + -0.858909273947823900f, + 0.511468850437970520f, -0.859301818357008360f, 0.510809623820439040f, + -0.859693857261072610f, + 0.510150096706766700f, -0.860085390429390140f, 0.509490269484936360f, + -0.860476417631632070f, + 0.508830142543106990f, -0.860866938637767310f, 0.508169716269614710f, + -0.861256953218062060f, + 0.507508991052970870f, -0.861646461143081300f, 0.506847967281863320f, + -0.862035462183687210f, + 0.506186645345155450f, -0.862423956111040500f, 0.505525025631885510f, + -0.862811942696600330f, + 0.504863108531267480f, -0.863199421712124160f, 0.504200894432690560f, + -0.863586392929667990f, + 0.503538383725717580f, -0.863972856121586700f, 0.502875576800086880f, + -0.864358811060534030f, + 0.502212474045710900f, -0.864744257519462380f, 0.501549075852675390f, + -0.865129195271623690f, + 0.500885382611240940f, -0.865513624090568980f, 0.500221394711840680f, + -0.865897543750148820f, + 0.499557112545081890f, -0.866280954024512990f, 0.498892536501744750f, + -0.866663854688111020f, + 0.498227666972781870f, -0.867046245515692650f, 0.497562504349319090f, + -0.867428126282306920f, + 0.496897049022654640f, -0.867809496763303210f, 0.496231301384258310f, + -0.868190356734331310f, + 0.495565261825772490f, -0.868570705971340900f, 0.494898930739011310f, + -0.868950544250582380f, + 0.494232308515959730f, -0.869329871348606730f, 0.493565395548774880f, + -0.869708687042265560f, + 0.492898192229784090f, -0.870086991108711350f, 0.492230698951486080f, + -0.870464783325397670f, + 0.491562916106550060f, -0.870842063470078860f, 0.490894844087815140f, + -0.871218831320810900f, + 0.490226483288291100f, -0.871595086655951090f, 0.489557834101157550f, + -0.871970829254157700f, + 0.488888896919763230f, -0.872346058894391540f, 0.488219672137626740f, + -0.872720775355914300f, + 0.487550160148436050f, -0.873094978418290090f, 0.486880361346047400f, + -0.873468667861384880f, + 0.486210276124486530f, -0.873841843465366750f, 0.485539904877947020f, + -0.874214505010706300f, + 0.484869248000791120f, -0.874586652278176110f, 0.484198305887549140f, + -0.874958285048851540f, + 0.483527078932918740f, -0.875329403104110780f, 0.482855567531765670f, + -0.875700006225634600f, + 0.482183772079122830f, -0.876070094195406600f, 0.481511692970189920f, + -0.876439666795713610f, + 0.480839330600333900f, -0.876808723809145760f, 0.480166685365088440f, + -0.877177265018595940f, + 0.479493757660153010f, -0.877545290207261240f, 0.478820547881394050f, + -0.877912799158641730f, + 0.478147056424843120f, -0.878279791656541460f, 0.477473283686698060f, + -0.878646267485068130f, + 0.476799230063322250f, -0.879012226428633410f, 0.476124895951243630f, + -0.879377668271953180f, + 0.475450281747155870f, -0.879742592800047410f, 0.474775387847917230f, + -0.880106999798240360f, + 0.474100214650550020f, -0.880470889052160750f, 0.473424762552241530f, + -0.880834260347742040f, + 0.472749031950342900f, -0.881197113471221980f, 0.472073023242368660f, + -0.881559448209143780f, + 0.471396736825997810f, -0.881921264348354940f, 0.470720173099071710f, + -0.882282561676008600f, + 0.470043332459595620f, -0.882643339979562790f, 0.469366215305737630f, + -0.883003599046780720f, + 0.468688822035827960f, -0.883363338665731580f, 0.468011153048359830f, + -0.883722558624789660f, + 0.467333208741988530f, -0.884081258712634990f, 0.466654989515530970f, + -0.884439438718253700f, + 0.465976495767966130f, -0.884797098430937790f, 0.465297727898434650f, + -0.885154237640285110f, + 0.464618686306237820f, -0.885510856136199950f, 0.463939371390838460f, + -0.885866953708892790f, + 0.463259783551860260f, -0.886222530148880640f, 0.462579923189086810f, + -0.886577585246987040f, + 0.461899790702462840f, -0.886932118794342080f, 0.461219386492092430f, + -0.887286130582383150f, + 0.460538710958240010f, -0.887639620402853930f, 0.459857764501329650f, + -0.887992588047805560f, + 0.459176547521944150f, -0.888345033309596240f, 0.458495060420826220f, + -0.888696955980891710f, + 0.457813303598877290f, -0.889048355854664570f, 0.457131277457156980f, + -0.889399232724195520f, + 0.456448982396883860f, -0.889749586383072890f, 0.455766418819434750f, + -0.890099416625192210f, + 0.455083587126343840f, -0.890448723244757880f, 0.454400487719303750f, + -0.890797506036281490f, + 0.453717121000163930f, -0.891145764794583180f, 0.453033487370931580f, + -0.891493499314791380f, + 0.452349587233771000f, -0.891840709392342720f, 0.451665420991002540f, + -0.892187394822982480f, + 0.450980989045103810f, -0.892533555402764690f, 0.450296291798708730f, + -0.892879190928051680f, + 0.449611329654606600f, -0.893224301195515320f, 0.448926103015743260f, + -0.893568886002136020f, + 0.448240612285220000f, -0.893912945145203250f, 0.447554857866293010f, + -0.894256478422316040f, + 0.446868840162374330f, -0.894599485631382580f, 0.446182559577030120f, + -0.894941966570620750f, + 0.445496016513981740f, -0.895283921038557580f, 0.444809211377105000f, + -0.895625348834030000f, + 0.444122144570429260f, -0.895966249756185110f, 0.443434816498138430f, + -0.896306623604479660f, + 0.442747227564570130f, -0.896646470178680150f, 0.442059378174214760f, + -0.896985789278863970f, + 0.441371268731716620f, -0.897324580705418320f, 0.440682899641873020f, + -0.897662844259040750f, + 0.439994271309633260f, -0.898000579740739880f, 0.439305384140100060f, + -0.898337786951834190f, + 0.438616238538527710f, -0.898674465693953820f, 0.437926834910322860f, + -0.899010615769039070f, + 0.437237173661044200f, -0.899346236979341460f, 0.436547255196401250f, + -0.899681329127423930f, + 0.435857079922255470f, -0.900015892016160280f, 0.435166648244619370f, + -0.900349925448735600f, + 0.434475960569655710f, -0.900683429228646860f, 0.433785017303678520f, + -0.901016403159702330f, + 0.433093818853152010f, -0.901348847046022030f, 0.432402365624690140f, + -0.901680760692037730f, + 0.431710658025057370f, -0.902012143902493070f, 0.431018696461167080f, + -0.902342996482444200f, + 0.430326481340082610f, -0.902673318237258830f, 0.429634013069016500f, + -0.903003108972617040f, + 0.428941292055329550f, -0.903332368494511820f, 0.428248318706531910f, + -0.903661096609247980f, + 0.427555093430282200f, -0.903989293123443340f, 0.426861616634386490f, + -0.904316957844028320f, + 0.426167888726799620f, -0.904644090578246240f, 0.425473910115623910f, + -0.904970691133653250f, + 0.424779681209108810f, -0.905296759318118820f, 0.424085202415651670f, + -0.905622294939825160f, + 0.423390474143796100f, -0.905947297807268460f, 0.422695496802232950f, + -0.906271767729257660f, + 0.422000270799799790f, -0.906595704514915330f, 0.421304796545479700f, + -0.906919107973678030f, + 0.420609074448402510f, -0.907241977915295930f, 0.419913104917843730f, + -0.907564314149832520f, + 0.419216888363223960f, -0.907886116487666150f, 0.418520425194109700f, + -0.908207384739488700f, + 0.417823715820212380f, -0.908528118716306120f, 0.417126760651387870f, + -0.908848318229439120f, + 0.416429560097637320f, -0.909167983090522270f, 0.415732114569105420f, + -0.909487113111505430f, + 0.415034424476081630f, -0.909805708104652220f, 0.414336490228999210f, + -0.910123767882541570f, + 0.413638312238434560f, -0.910441292258067140f, 0.412939890915108020f, + -0.910758281044437570f, + 0.412241226669883000f, -0.911074734055176250f, 0.411542319913765280f, + -0.911390651104122320f, + 0.410843171057903910f, -0.911706032005429880f, 0.410143780513590350f, + -0.912020876573568230f, + 0.409444148692257590f, -0.912335184623322750f, 0.408744276005481520f, + -0.912648955969793900f, + 0.408044162864978740f, -0.912962190428398100f, 0.407343809682607970f, + -0.913274887814867760f, + 0.406643216870369140f, -0.913587047945250810f, 0.405942384840402570f, + -0.913898670635911680f, + 0.405241314004989860f, -0.914209755703530690f, 0.404540004776553110f, + -0.914520302965104450f, + 0.403838457567654130f, -0.914830312237946090f, 0.403136672790995240f, + -0.915139783339685260f, + 0.402434650859418540f, -0.915448716088267830f, 0.401732392185905010f, + -0.915757110301956720f, + 0.401029897183575790f, -0.916064965799331610f, 0.400327166265690150f, + -0.916372282399289140f, + 0.399624199845646790f, -0.916679059921042700f, 0.398920998336983020f, + -0.916985298184122890f, + 0.398217562153373620f, -0.917290997008377910f, 0.397513891708632330f, + -0.917596156213972950f, + 0.396809987416710420f, -0.917900775621390390f, 0.396105849691696320f, + -0.918204855051430900f, + 0.395401478947816300f, -0.918508394325212250f, 0.394696875599433670f, + -0.918811393264169940f, + 0.393992040061048100f, -0.919113851690057770f, 0.393286972747296570f, + -0.919415769424946960f, + 0.392581674072951530f, -0.919717146291227360f, 0.391876144452922350f, + -0.920017982111606570f, + 0.391170384302253980f, -0.920318276709110480f, 0.390464394036126650f, + -0.920618029907083860f, + 0.389758174069856410f, -0.920917241529189520f, 0.389051724818894500f, + -0.921215911399408730f, + 0.388345046698826300f, -0.921514039342041900f, 0.387638140125372680f, + -0.921811625181708120f, + 0.386931005514388690f, -0.922108668743345070f, 0.386223643281862980f, + -0.922405169852209880f, + 0.385516053843919020f, -0.922701128333878520f, 0.384808237616812930f, + -0.922996544014246250f, + 0.384100195016935040f, -0.923291416719527640f, 0.383391926460808770f, + -0.923585746276256560f, + 0.382683432365089840f, -0.923879532511286740f, 0.381974713146567220f, + -0.924172775251791200f, + 0.381265769222162490f, -0.924465474325262600f, 0.380556601008928570f, + -0.924757629559513910f, + 0.379847208924051110f, -0.925049240782677580f, 0.379137593384847430f, + -0.925340307823206200f, + 0.378427754808765620f, -0.925630830509872720f, 0.377717693613385810f, + -0.925920808671769960f, + 0.377007410216418310f, -0.926210242138311270f, 0.376296905035704790f, + -0.926499130739230510f, + 0.375586178489217330f, -0.926787474304581750f, 0.374875230995057600f, + -0.927075272664740100f, + 0.374164062971457990f, -0.927362525650401110f, 0.373452674836780410f, + -0.927649233092581180f, + 0.372741067009515810f, -0.927935394822617890f, 0.372029239908284960f, + -0.928221010672169440f, + 0.371317193951837600f, -0.928506080473215480f, 0.370604929559051670f, + -0.928790604058057020f, + 0.369892447148934270f, -0.929074581259315750f, 0.369179747140620070f, + -0.929358011909935500f, + 0.368466829953372320f, -0.929640895843181330f, 0.367753696006582090f, + -0.929923232892639560f, + 0.367040345719767240f, -0.930205022892219070f, 0.366326779512573590f, + -0.930486265676149780f, + 0.365612997804773960f, -0.930766961078983710f, 0.364899001016267380f, + -0.931047108935595170f, + 0.364184789567079840f, -0.931326709081180430f, 0.363470363877363870f, + -0.931605761351257830f, + 0.362755724367397230f, -0.931884265581668150f, 0.362040871457584350f, + -0.932162221608574320f, + 0.361325805568454340f, -0.932439629268462360f, 0.360610527120662270f, + -0.932716488398140250f, + 0.359895036534988280f, -0.932992798834738850f, 0.359179334232336560f, + -0.933268560415712050f, + 0.358463420633736540f, -0.933543772978836170f, 0.357747296160342010f, + -0.933818436362210960f, + 0.357030961233430030f, -0.934092550404258870f, 0.356314416274402360f, + -0.934366114943725900f, + 0.355597661704783960f, -0.934639129819680780f, 0.354880697946222790f, + -0.934911594871516090f, + 0.354163525420490510f, -0.935183509938947500f, 0.353446144549480870f, + -0.935454874862014620f, + 0.352728555755210730f, -0.935725689481080370f, 0.352010759459819240f, + -0.935995953636831300f, + 0.351292756085567150f, -0.936265667170278260f, 0.350574546054837570f, + -0.936534829922755500f, + 0.349856129790135030f, -0.936803441735921560f, 0.349137507714085030f, + -0.937071502451759190f, + 0.348418680249434510f, -0.937339011912574960f, 0.347699647819051490f, + -0.937605969960999990f, + 0.346980410845923680f, -0.937872376439989890f, 0.346260969753160170f, + -0.938138231192824360f, + 0.345541324963989150f, -0.938403534063108060f, 0.344821476901759290f, + -0.938668284894770170f, + 0.344101425989938980f, -0.938932483532064490f, 0.343381172652115100f, + -0.939196129819569900f, + 0.342660717311994380f, -0.939459223602189920f, 0.341940060393402300f, + -0.939721764725153340f, + 0.341219202320282410f, -0.939983753034013940f, 0.340498143516697100f, + -0.940245188374650880f, + 0.339776884406826960f, -0.940506070593268300f, 0.339055425414969640f, + -0.940766399536396070f, + 0.338333766965541290f, -0.941026175050889260f, 0.337611909483074680f, + -0.941285396983928660f, + 0.336889853392220050f, -0.941544065183020810f, 0.336167599117744690f, + -0.941802179495997650f, + 0.335445147084531660f, -0.942059739771017310f, 0.334722497717581220f, + -0.942316745856563780f, + 0.333999651442009490f, -0.942573197601446870f, 0.333276608683047980f, + -0.942829094854802710f, + 0.332553369866044220f, -0.943084437466093490f, 0.331829935416461220f, + -0.943339225285107720f, + 0.331106305759876430f, -0.943593458161960390f, 0.330382481321982950f, + -0.943847135947092690f, + 0.329658462528587550f, -0.944100258491272660f, 0.328934249805612200f, + -0.944352825645594750f, + 0.328209843579092660f, -0.944604837261480260f, 0.327485244275178060f, + -0.944856293190677210f, + 0.326760452320131790f, -0.945107193285260610f, 0.326035468140330350f, + -0.945357537397632290f, + 0.325310292162262980f, -0.945607325380521280f, 0.324584924812532150f, + -0.945856557086983910f, + 0.323859366517852960f, -0.946105232370403340f, 0.323133617705052330f, + -0.946353351084490590f, + 0.322407678801070020f, -0.946600913083283530f, 0.321681550232956640f, + -0.946847918221148000f, + 0.320955232427875210f, -0.947094366352777220f, 0.320228725813100020f, + -0.947340257333191940f, + 0.319502030816015750f, -0.947585591017741090f, 0.318775147864118480f, + -0.947830367262101010f, + 0.318048077385015060f, -0.948074585922276230f, 0.317320819806421790f, + -0.948318246854599090f, + 0.316593375556165850f, -0.948561349915730270f, 0.315865745062184070f, + -0.948803894962658380f, + 0.315137928752522440f, -0.949045881852700560f, 0.314409927055336820f, + -0.949287310443502010f, + 0.313681740398891570f, -0.949528180593036670f, 0.312953369211560200f, + -0.949768492159606680f, + 0.312224813921825050f, -0.950008245001843000f, 0.311496074958275970f, + -0.950247438978705230f, + 0.310767152749611470f, -0.950486073949481700f, 0.310038047724638000f, + -0.950724149773789610f, + 0.309308760312268780f, -0.950961666311575080f, 0.308579290941525030f, + -0.951198623423113230f, + 0.307849640041534980f, -0.951435020969008340f, 0.307119808041533100f, + -0.951670858810193860f, + 0.306389795370861080f, -0.951906136807932230f, 0.305659602458966230f, + -0.952140854823815830f, + 0.304929229735402430f, -0.952375012719765880f, 0.304198677629829270f, + -0.952608610358033240f, + 0.303467946572011370f, -0.952841647601198720f, 0.302737036991819140f, + -0.953074124312172200f, + 0.302005949319228200f, -0.953306040354193750f, 0.301274683984318000f, + -0.953537395590833280f, + 0.300543241417273400f, -0.953768189885990330f, 0.299811622048383460f, + -0.953998423103894490f, + 0.299079826308040480f, -0.954228095109105670f, 0.298347854626741570f, + -0.954457205766513490f, + 0.297615707435086310f, -0.954685754941338340f, 0.296883385163778270f, + -0.954913742499130520f, + 0.296150888243623960f, -0.955141168305770670f, 0.295418217105532070f, + -0.955368032227470240f, + 0.294685372180514330f, -0.955594334130771110f, 0.293952353899684770f, + -0.955820073882545420f, + 0.293219162694258680f, -0.956045251349996410f, 0.292485798995553830f, + -0.956269866400658140f, + 0.291752263234989370f, -0.956493918902394990f, 0.291018555844085090f, + -0.956717408723403050f, + 0.290284677254462330f, -0.956940335732208940f, 0.289550627897843140f, + -0.957162699797670100f, + 0.288816408206049480f, -0.957384500788975860f, 0.288082018611004300f, + -0.957605738575646240f, + 0.287347459544729570f, -0.957826413027532910f, 0.286612731439347790f, + -0.958046524014818600f, + 0.285877834727080730f, -0.958266071408017670f, 0.285142769840248720f, + -0.958485055077976100f, + 0.284407537211271820f, -0.958703474895871600f, 0.283672137272668550f, + -0.958921330733213060f, + 0.282936570457055390f, -0.959138622461841890f, 0.282200837197147500f, + -0.959355349953930790f, + 0.281464937925758050f, -0.959571513081984520f, 0.280728873075797190f, + -0.959787111718839900f, + 0.279992643080273380f, -0.960002145737665850f, 0.279256248372291240f, + -0.960216615011963430f, + 0.278519689385053060f, -0.960430519415565790f, 0.277782966551857800f, + -0.960643858822638470f, + 0.277046080306099950f, -0.960856633107679660f, 0.276309031081271030f, + -0.961068842145519350f, + 0.275571819310958250f, -0.961280485811320640f, 0.274834445428843940f, + -0.961491563980579000f, + 0.274096909868706330f, -0.961702076529122540f, 0.273359213064418790f, + -0.961912023333112100f, + 0.272621355449948980f, -0.962121404269041580f, 0.271883337459359890f, + -0.962330219213737400f, + 0.271145159526808070f, -0.962538468044359160f, 0.270406822086544820f, + -0.962746150638399410f, + 0.269668325572915200f, -0.962953266873683880f, 0.268929670420357310f, + -0.963159816628371360f, + 0.268190857063403180f, -0.963365799780954050f, 0.267451885936677740f, + -0.963571216210257210f, + 0.266712757474898420f, -0.963776065795439840f, 0.265973472112875530f, + -0.963980348415994110f, + 0.265234030285511900f, -0.964184063951745720f, 0.264494432427801630f, + -0.964387212282854290f, + 0.263754678974831510f, -0.964589793289812650f, 0.263014770361779060f, + -0.964791806853447900f, + 0.262274707023913590f, -0.964993252854920320f, 0.261534489396595630f, + -0.965194131175724720f, + 0.260794117915275570f, -0.965394441697689400f, 0.260053593015495130f, + -0.965594184302976830f, + 0.259312915132886350f, -0.965793358874083570f, 0.258572084703170390f, + -0.965991965293840570f, + 0.257831102162158930f, -0.966190003445412620f, 0.257089967945753230f, + -0.966387473212298790f, + 0.256348682489942910f, -0.966584374478333120f, 0.255607246230807550f, + -0.966780707127683270f, + 0.254865659604514630f, -0.966976471044852070f, 0.254123923047320620f, + -0.967171666114676640f, + 0.253382036995570270f, -0.967366292222328510f, 0.252640001885695580f, + -0.967560349253314360f, + 0.251897818154216910f, -0.967753837093475510f, 0.251155486237742030f, + -0.967946755628987800f, + 0.250413006572965280f, -0.968139104746362330f, 0.249670379596668520f, + -0.968330884332445300f, + 0.248927605745720260f, -0.968522094274417270f, 0.248184685457074780f, + -0.968712734459794780f, + 0.247441619167773440f, -0.968902804776428870f, 0.246698407314942500f, + -0.969092305112506100f, + 0.245955050335794590f, -0.969281235356548530f, 0.245211548667627680f, + -0.969469595397412950f, + 0.244467902747824210f, -0.969657385124292450f, 0.243724113013852130f, + -0.969844604426714830f, + 0.242980179903263980f, -0.970031253194543970f, 0.242236103853696070f, + -0.970217331317979160f, + 0.241491885302869300f, -0.970402838687555500f, 0.240747524688588540f, + -0.970587775194143630f, + 0.240003022448741500f, -0.970772140728950350f, 0.239258379021300120f, + -0.970955935183517970f, + 0.238513594844318500f, -0.971139158449725090f, 0.237768670355934210f, + -0.971321810419786160f, + 0.237023605994367340f, -0.971503890986251780f, 0.236278402197919620f, + -0.971685400042008540f, + 0.235533059404975460f, -0.971866337480279400f, 0.234787578054001080f, + -0.972046703194623500f, + 0.234041958583543460f, -0.972226497078936270f, 0.233296201432231560f, + -0.972405719027449770f, + 0.232550307038775330f, -0.972584368934732210f, 0.231804275841964780f, + -0.972762446695688570f, + 0.231058108280671280f, -0.972939952205560070f, 0.230311804793845530f, + -0.973116885359925130f, + 0.229565365820518870f, -0.973293246054698250f, 0.228818791799802360f, + -0.973469034186130950f, + 0.228072083170885790f, -0.973644249650811870f, 0.227325240373038830f, + -0.973818892345666100f, + 0.226578263845610110f, -0.973992962167955830f, 0.225831154028026200f, + -0.974166459015280320f, + 0.225083911359792780f, -0.974339382785575860f, 0.224336536280493690f, + -0.974511733377115720f, + 0.223589029229790020f, -0.974683510688510670f, 0.222841390647421280f, + -0.974854714618708430f, + 0.222093620973203590f, -0.975025345066994120f, 0.221345720647030810f, + -0.975195401932990370f, + 0.220597690108873650f, -0.975364885116656870f, 0.219849529798778750f, + -0.975533794518291360f, + 0.219101240156869770f, -0.975702130038528570f, 0.218352821623346430f, + -0.975869891578341030f, + 0.217604274638483670f, -0.976037079039039020f, 0.216855599642632570f, + -0.976203692322270560f, + 0.216106797076219600f, -0.976369731330021140f, 0.215357867379745550f, + -0.976535195964614470f, + 0.214608810993786920f, -0.976700086128711840f, 0.213859628358993830f, + -0.976864401725312640f, + 0.213110319916091360f, -0.977028142657754390f, 0.212360886105878580f, + -0.977191308829712280f, + 0.211611327369227610f, -0.977353900145199960f, 0.210861644147084830f, + -0.977515916508569280f, + 0.210111836880469720f, -0.977677357824509930f, 0.209361906010474190f, + -0.977838223998050430f, + 0.208611851978263460f, -0.977998514934557140f, 0.207861675225075150f, + -0.978158230539735050f, + 0.207111376192218560f, -0.978317370719627650f, 0.206360955321075680f, + -0.978475935380616830f, + 0.205610413053099320f, -0.978633924429423100f, 0.204859749829814420f, + -0.978791337773105670f, + 0.204108966092817010f, -0.978948175319062200f, 0.203358062283773370f, + -0.979104436975029250f, + 0.202607038844421110f, -0.979260122649082020f, 0.201855896216568160f, + -0.979415232249634780f, + 0.201104634842091960f, -0.979569765685440520f, 0.200353255162940420f, + -0.979723722865591170f, + 0.199601757621131050f, -0.979877103699517640f, 0.198850142658750120f, + -0.980029908096989980f, + 0.198098410717953730f, -0.980182135968117320f, 0.197346562240966000f, + -0.980333787223347960f, + 0.196594597670080220f, -0.980484861773469380f, 0.195842517447657990f, + -0.980635359529608120f, + 0.195090322016128330f, -0.980785280403230430f, 0.194338011817988600f, + -0.980934624306141640f, + 0.193585587295803750f, -0.981083391150486590f, 0.192833048892205290f, + -0.981231580848749730f, + 0.192080397049892380f, -0.981379193313754560f, 0.191327632211630990f, + -0.981526228458664660f, + 0.190574754820252800f, -0.981672686196983110f, 0.189821765318656580f, + -0.981818566442552500f, + 0.189068664149806280f, -0.981963869109555240f, 0.188315451756732120f, + -0.982108594112513610f, + 0.187562128582529740f, -0.982252741366289370f, 0.186808695070359330f, + -0.982396310786084690f, + 0.186055151663446630f, -0.982539302287441240f, 0.185301498805082040f, + -0.982681715786240860f, + 0.184547736938619640f, -0.982823551198705240f, 0.183793866507478390f, + -0.982964808441396440f, + 0.183039887955141060f, -0.983105487431216290f, 0.182285801725153320f, + -0.983245588085407070f, + 0.181531608261125130f, -0.983385110321551180f, 0.180777308006728670f, + -0.983524054057571260f, + 0.180022901405699510f, -0.983662419211730250f, 0.179268388901835880f, + -0.983800205702631490f, + 0.178513770938997590f, -0.983937413449218920f, 0.177759047961107140f, + -0.984074042370776450f, + 0.177004220412148860f, -0.984210092386929030f, 0.176249288736167940f, + -0.984345563417641900f, + 0.175494253377271400f, -0.984480455383220930f, 0.174739114779627310f, + -0.984614768204312600f, + 0.173983873387463850f, -0.984748501801904210f, 0.173228529645070490f, + -0.984881656097323700f, + 0.172473083996796030f, -0.985014231012239840f, 0.171717536887049970f, + -0.985146226468662230f, + 0.170961888760301360f, -0.985277642388941220f, 0.170206140061078120f, + -0.985408478695768420f, + 0.169450291233967930f, -0.985538735312176060f, 0.168694342723617440f, + -0.985668412161537550f, + 0.167938294974731230f, -0.985797509167567370f, 0.167182148432072880f, + -0.985926026254321130f, + 0.166425903540464220f, -0.986053963346195440f, 0.165669560744784140f, + -0.986181320367928270f, + 0.164913120489970090f, -0.986308097244598670f, 0.164156583221015890f, + -0.986434293901627070f, + 0.163399949382973230f, -0.986559910264775410f, 0.162643219420950450f, + -0.986684946260146690f, + 0.161886393780111910f, -0.986809401814185420f, 0.161129472905678780f, + -0.986933276853677710f, + 0.160372457242928400f, -0.987056571305750970f, 0.159615347237193090f, + -0.987179285097874340f, + 0.158858143333861390f, -0.987301418157858430f, 0.158100845978377090f, + -0.987422970413855410f, + 0.157343455616238280f, -0.987543941794359230f, 0.156585972692998590f, + -0.987664332228205710f, + 0.155828397654265320f, -0.987784141644572180f, 0.155070730945700510f, + -0.987903369972977790f, + 0.154312973013020240f, -0.988022017143283530f, 0.153555124301993500f, + -0.988140083085692570f, + 0.152797185258443410f, -0.988257567730749460f, 0.152039156328246160f, + -0.988374471009341280f, + 0.151281037957330250f, -0.988490792852696590f, 0.150522830591677370f, + -0.988606533192386450f, + 0.149764534677321620f, -0.988721691960323780f, 0.149006150660348470f, + -0.988836269088763540f, + 0.148247678986896200f, -0.988950264510302990f, 0.147489120103153680f, + -0.989063678157881540f, + 0.146730474455361750f, -0.989176509964781010f, 0.145971742489812370f, + -0.989288759864625170f, + 0.145212924652847520f, -0.989400427791380380f, 0.144454021390860440f, + -0.989511513679355190f, + 0.143695033150294580f, -0.989622017463200780f, 0.142935960377642700f, + -0.989731939077910570f, + 0.142176803519448000f, -0.989841278458820530f, 0.141417563022303130f, + -0.989950035541608990f, + 0.140658239332849240f, -0.990058210262297120f, 0.139898832897777380f, + -0.990165802557248400f, + 0.139139344163826280f, -0.990272812363169110f, 0.138379773577783890f, + -0.990379239617108160f, + 0.137620121586486180f, -0.990485084256456980f, 0.136860388636816430f, + -0.990590346218950150f, + 0.136100575175706200f, -0.990695025442664630f, 0.135340681650134330f, + -0.990799121866020370f, + 0.134580708507126220f, -0.990902635427780010f, 0.133820656193754690f, + -0.991005566067049370f, + 0.133060525157139180f, -0.991107913723276780f, 0.132300315844444680f, + -0.991209678336254060f, + 0.131540028702883280f, -0.991310859846115440f, 0.130779664179711790f, + -0.991411458193338540f, + 0.130019222722233350f, -0.991511473318743900f, 0.129258704777796270f, + -0.991610905163495370f, + 0.128498110793793220f, -0.991709753669099530f, 0.127737441217662280f, + -0.991808018777406430f, + 0.126976696496885980f, -0.991905700430609330f, 0.126215877078990400f, + -0.992002798571244520f, + 0.125454983411546210f, -0.992099313142191800f, 0.124694015942167770f, + -0.992195244086673920f, + 0.123932975118512200f, -0.992290591348257370f, 0.123171861388280650f, + -0.992385354870851670f, + 0.122410675199216280f, -0.992479534598709970f, 0.121649416999105540f, + -0.992573130476428810f, + 0.120888087235777220f, -0.992666142448948020f, 0.120126686357101580f, + -0.992758570461551140f, + 0.119365214810991350f, -0.992850414459865100f, 0.118603673045400840f, + -0.992941674389860470f, + 0.117842061508325020f, -0.993032350197851410f, 0.117080380647800550f, + -0.993122441830495580f, + 0.116318630911904880f, -0.993211949234794500f, 0.115556812748755290f, + -0.993300872358093280f, + 0.114794926606510250f, -0.993389211148080650f, 0.114032972933367300f, + -0.993476965552789190f, + 0.113270952177564360f, -0.993564135520595300f, 0.112508864787378830f, + -0.993650721000219120f, + 0.111746711211126660f, -0.993736721940724600f, 0.110984491897163380f, + -0.993822138291519660f, + 0.110222207293883180f, -0.993906970002356060f, 0.109459857849718030f, + -0.993991217023329380f, + 0.108697444013138670f, -0.994074879304879370f, 0.107934966232653760f, + -0.994157956797789730f, + 0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f, + -0.994322357222545810f, + 0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f, + -0.994484417910747600f, + 0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f, + -0.994644138481050710f, + 0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f, + -0.994801518557617110f, + 0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f, + -0.994956557770116380f, + 0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f, + -0.995109255753726110f, + 0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f, + -0.995259612149133390f, + 0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f, + -0.995407626602534900f, + 0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f, + -0.995553298765638470f, + 0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f, + -0.995696628295663520f, + 0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f, + -0.995837614855341610f, + 0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f, + -0.995976258112917790f, + 0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f, + -0.996112557742151130f, + 0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f, + -0.996246513422315520f, + 0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f, + -0.996378124838200210f, + 0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f, + -0.996507391680110820f, + 0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f, + -0.996634313643869900f, + 0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f, + -0.996758890430818000f, + 0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f, + -0.996881121747813850f, + 0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f, + -0.997001007307235290f, + 0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f, + -0.997118546826979980f, + 0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f, + -0.997233740030466160f, + 0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f, + -0.997346586646633230f, + 0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f, + -0.997457086409941910f, + 0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f, + -0.997565239060375750f, + 0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f, + -0.997671044343441000f, + 0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f, + -0.997774502010167820f, + 0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f, + -0.997875611817110150f, + 0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f, + -0.997974373526346990f, + 0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f, + -0.998070786905482340f, + 0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f, + -0.998164851727646240f, + 0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f, + -0.998256567771495180f, + 0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f, + -0.998345934821212370f, + 0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f, + -0.998432952666508440f, + 0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f, + -0.998517621102622210f, + 0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f, + -0.998599939930320370f, + 0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f, + -0.998679908955899090f, + 0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f, + -0.998757527991183340f, + 0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f, + -0.998832796853527990f, + 0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f, + -0.998905715365818290f, + 0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f, + -0.998976283356469820f, + 0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f, + -0.999044500659429290f, + 0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f, + -0.999110367114174890f, + 0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f, + -0.999173882565716380f, + 0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f, + -0.999235046864595850f, + 0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f, + -0.999293859866887790f, + 0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f, + -0.999350321434199440f, + 0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f, + -0.999404431433671300f, + 0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f, + -0.999456189737977340f, + 0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f, + -0.999505596225325310f, + 0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f, + -0.999552650779456990f, + 0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f, + -0.999597353289648380f, + 0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f, + -0.999639703650710200f, + 0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f, + -0.999679701762987930f, + 0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f, + -0.999717347532362190f, + 0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f, + -0.999752640870248840f, + 0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f, + -0.999785581693599210f, + 0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f, + -0.999816169924900410f, + 0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f, + -0.999844405492175240f, + 0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f, + -0.999870288328982950f, + 0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f, + -0.999893818374418490f, + 0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f, + -0.999914995573113470f, + 0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f, + -0.999933819875236000f, + 0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f, + -0.999950291236490480f, + 0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f, + -0.999964409618118280f, + 0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f, + -0.999976174986897610f, + 0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f, + -0.999985587315143200f, + 0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f, + -0.999992646580707190f, + 0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f, + -0.999997352766978210f, + 0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f, + -0.999999705862882230f +}; + const float32_t cos_factors_2048[2048] = { + 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f, + 0.999996396822294350f, + 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f, + 0.999983454831937730f, + 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f, + 0.999961100616462820f, + 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f, + 0.999929334386276070f, + 0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f, + 0.999888156440373320f, + 0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f, + 0.999837567166337090f, + 0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f, + 0.999777567040332940f, + 0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f, + 0.999708156627104880f, + 0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f, + 0.999629336579970110f, + 0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f, + 0.999541107640812940f, + 0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f, + 0.999443470640077770f, + 0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f, + 0.999336426496761240f, + 0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f, + 0.999219976218403530f, + 0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f, + 0.999094120901079070f, + 0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f, + 0.998958861729386080f, + 0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f, + 0.998814199976435390f, + 0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f, + 0.998660137003838490f, + 0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f, + 0.998496674261694640f, + 0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f, + 0.998323813288577560f, + 0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f, + 0.998141555711520520f, + 0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f, + 0.997949903246001190f, + 0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f, + 0.997748857695925690f, + 0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f, + 0.997538420953611340f, + 0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f, + 0.997318594999768600f, + 0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f, + 0.997089381903483400f, + 0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f, + 0.996850783822196610f, + 0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f, + 0.996602803001684130f, + 0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f, + 0.996345441776035900f, + 0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f, + 0.996078702567633980f, + 0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f, + 0.995802587887129160f, + 0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f, + 0.995517100333418110f, + 0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f, + 0.995222242593618360f, + 0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f, + 0.994918017443043200f, + 0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f, + 0.994604427745175660f, + 0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f, + 0.994281476451641550f, + 0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f, + 0.993949166602181130f, + 0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f, + 0.993607501324621610f, + 0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f, + 0.993256483834846440f, + 0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f, + 0.992896117436765980f, + 0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f, + 0.992526405522286100f, + 0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f, + 0.992147351571276090f, + 0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f, + 0.991758959151536110f, + 0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f, + 0.991361231918763460f, + 0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f, + 0.990954173616518500f, + 0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f, + 0.990537788076188750f, + 0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f, + 0.990112079216953770f, + 0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f, + 0.989677051045747210f, + 0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f, + 0.989232707657220050f, + 0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f, + 0.988779053233701520f, + 0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f, + 0.988316092045159690f, + 0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f, + 0.987843828449161740f, + 0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f, + 0.987362266890832400f, + 0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f, + 0.986871411902812470f, + 0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f, + 0.986371268105216030f, + 0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f, + 0.985861840205586980f, + 0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f, + 0.985343132998854790f, + 0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f, + 0.984815151367289140f, + 0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f, + 0.984277900280454370f, + 0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f, + 0.983731384795162090f, + 0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f, + 0.983175610055424420f, + 0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f, + 0.982610581292404750f, + 0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f, + 0.982036303824369020f, + 0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f, + 0.981452783056635520f, + 0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f, + 0.980860024481523870f, + 0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f, + 0.980258033678303550f, + 0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f, + 0.979646816313141210f, + 0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f, + 0.979026378139047580f, + 0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f, + 0.978396724995823090f, + 0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f, + 0.977757862810002760f, + 0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f, + 0.977109797594800880f, + 0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f, + 0.976452535450054060f, + 0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f, + 0.975786082562163930f, + 0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f, + 0.975110445204038890f, + 0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f, + 0.974425629735034990f, + 0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f, + 0.973731642600896400f, + 0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f, + 0.973028490333694210f, + 0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f, + 0.972316179551765300f, + 0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f, + 0.971594716959650160f, + 0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f, + 0.970864109348029470f, + 0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f, + 0.970124363593660280f, + 0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f, + 0.969375486659311280f, + 0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f, + 0.968617485593697540f, + 0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f, + 0.967850367531413620f, + 0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f, + 0.967074139692867040f, + 0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f, + 0.966288809384209690f, + 0.966091055410438830f, 0.965892733110190860f, 0.965693842600133690f, + 0.965494383997269500f, + 0.965294357418934660f, 0.965093762982799590f, 0.964892600806868890f, + 0.964690871009481030f, + 0.964488573709308410f, 0.964285709025357480f, 0.964082277076968140f, + 0.963878277983814200f, + 0.963673711865903230f, 0.963468578843575950f, 0.963262879037507070f, + 0.963056612568704340f, + 0.962849779558509030f, 0.962642380128595710f, 0.962434414400972100f, + 0.962225882497979020f, + 0.962016784542290560f, 0.961807120656913540f, 0.961596890965187860f, + 0.961386095590786250f, + 0.961174734657714080f, 0.960962808290309780f, 0.960750316613243950f, + 0.960537259751520050f, + 0.960323637830473920f, 0.960109450975773940f, 0.959894699313420530f, + 0.959679382969746750f, + 0.959463502071417510f, 0.959247056745430090f, 0.959030047119113660f, + 0.958812473320129310f, + 0.958594335476470220f, 0.958375633716461170f, 0.958156368168758820f, + 0.957936538962351420f, + 0.957716146226558870f, 0.957495190091032570f, 0.957273670685755200f, + 0.957051588141040970f, + 0.956828942587535370f, 0.956605734156215080f, 0.956381962978387730f, + 0.956157629185692140f, + 0.955932732910098280f, 0.955707274283906560f, 0.955481253439748770f, + 0.955254670510586990f, + 0.955027525629714160f, 0.954799818930753720f, 0.954571550547659630f, + 0.954342720614716480f, + 0.954113329266538800f, 0.953883376638071770f, 0.953652862864590500f, + 0.953421788081700310f, + 0.953190152425336670f, 0.952957956031764700f, 0.952725199037579570f, + 0.952491881579706320f, + 0.952258003795399600f, 0.952023565822243570f, 0.951788567798152130f, + 0.951553009861368590f, + 0.951316892150465550f, 0.951080214804345010f, 0.950842977962238160f, + 0.950605181763705340f, + 0.950366826348635780f, 0.950127911857248100f, 0.949888438430089300f, + 0.949648406208035480f, + 0.949407815332291570f, 0.949166665944390700f, 0.948924958186195160f, + 0.948682692199895090f, + 0.948439868128009620f, 0.948196486113385580f, 0.947952546299198670f, + 0.947708048828952100f, + 0.947462993846477700f, 0.947217381495934820f, 0.946971211921810880f, + 0.946724485268921170f, + 0.946477201682408680f, 0.946229361307743820f, 0.945980964290724760f, + 0.945732010777477150f, + 0.945482500914453740f, 0.945232434848435000f, 0.944981812726528150f, + 0.944730634696167800f, + 0.944478900905115550f, 0.944226611501459810f, 0.943973766633615980f, + 0.943720366450326200f, + 0.943466411100659320f, 0.943211900734010620f, 0.942956835500102120f, + 0.942701215548981900f, + 0.942445041031024890f, 0.942188312096931770f, 0.941931028897729620f, + 0.941673191584771360f, + 0.941414800309736340f, 0.941155855224629190f, 0.940896356481780830f, + 0.940636304233847590f, + 0.940375698633811540f, 0.940114539834980280f, 0.939852827990986680f, + 0.939590563255789270f, + 0.939327745783671400f, 0.939064375729241950f, 0.938800453247434770f, + 0.938535978493508560f, + 0.938270951623047190f, 0.938005372791958840f, 0.937739242156476970f, + 0.937472559873159250f, + 0.937205326098887960f, 0.936937540990869900f, 0.936669204706636170f, + 0.936400317404042060f, + 0.936130879241267030f, 0.935860890376814640f, 0.935590350969512370f, + 0.935319261178511610f, + 0.935047621163287430f, 0.934775431083638700f, 0.934502691099687870f, + 0.934229401371880820f, + 0.933955562060986730f, 0.933681173328098410f, 0.933406235334631520f, + 0.933130748242325230f, + 0.932854712213241120f, 0.932578127409764420f, 0.932300993994602760f, + 0.932023312130786490f, + 0.931745081981668720f, 0.931466303710925090f, 0.931186977482553750f, + 0.930907103460875130f, + 0.930626681810531760f, 0.930345712696488470f, 0.930064196284032360f, + 0.929782132738772190f, + 0.929499522226638560f, 0.929216364913884040f, 0.928932660967082820f, + 0.928648410553130520f, + 0.928363613839244370f, 0.928078270992963140f, 0.927792382182146320f, + 0.927505947574975180f, + 0.927218967339951790f, 0.926931441645899130f, 0.926643370661961230f, + 0.926354754557602860f, + 0.926065593502609310f, 0.925775887667086740f, 0.925485637221461490f, + 0.925194842336480530f, + 0.924903503183210910f, 0.924611619933039970f, 0.924319192757675160f, + 0.924026221829143850f, + 0.923732707319793290f, 0.923438649402290370f, 0.923144048249621930f, + 0.922848904035094120f, + 0.922553216932332830f, 0.922256987115283030f, 0.921960214758209220f, + 0.921662900035694730f, + 0.921365043122642340f, 0.921066644194273640f, 0.920767703426128790f, + 0.920468220994067110f, + 0.920168197074266340f, 0.919867631843222950f, 0.919566525477751530f, + 0.919264878154985370f, + 0.918962690052375630f, 0.918659961347691900f, 0.918356692219021720f, + 0.918052882844770380f, + 0.917748533403661250f, 0.917443644074735220f, 0.917138215037350710f, + 0.916832246471183890f, + 0.916525738556228210f, 0.916218691472794220f, 0.915911105401509880f, + 0.915602980523320230f, + 0.915294317019487050f, 0.914985115071589310f, 0.914675374861522390f, + 0.914365096571498560f, + 0.914054280384046570f, 0.913742926482011390f, 0.913431035048554720f, + 0.913118606267154240f, + 0.912805640321603500f, 0.912492137396012650f, 0.912178097674807180f, + 0.911863521342728520f, + 0.911548408584833990f, 0.911232759586496190f, 0.910916574533403360f, + 0.910599853611558930f, + 0.910282597007281760f, 0.909964804907205660f, 0.909646477498279540f, + 0.909327614967767260f, + 0.909008217503247450f, 0.908688285292613360f, 0.908367818524072890f, + 0.908046817386148340f, + 0.907725282067676440f, 0.907403212757808110f, 0.907080609646008450f, + 0.906757472922056550f, + 0.906433802776045460f, 0.906109599398381980f, 0.905784862979786550f, + 0.905459593711293250f, + 0.905133791784249690f, 0.904807457390316540f, 0.904480590721468250f, + 0.904153191969991780f, + 0.903825261328487510f, 0.903496798989868450f, 0.903167805147360720f, + 0.902838279994502830f, + 0.902508223725145940f, 0.902177636533453620f, 0.901846518613901750f, + 0.901514870161278740f, + 0.901182691370684520f, 0.900849982437531450f, 0.900516743557543520f, + 0.900182974926756810f, + 0.899848676741518580f, 0.899513849198487980f, 0.899178492494635330f, + 0.898842606827242370f, + 0.898506192393901950f, 0.898169249392518080f, 0.897831778021305650f, + 0.897493778478790310f, + 0.897155250963808550f, 0.896816195675507300f, 0.896476612813344120f, + 0.896136502577086770f, + 0.895795865166813530f, 0.895454700782912450f, 0.895113009626081760f, + 0.894770791897329550f, + 0.894428047797973800f, 0.894084777529641990f, 0.893740981294271040f, + 0.893396659294107720f, + 0.893051811731707450f, 0.892706438809935390f, 0.892360540731965360f, + 0.892014117701280470f, + 0.891667169921672280f, 0.891319697597241390f, 0.890971700932396860f, + 0.890623180131855930f, + 0.890274135400644600f, 0.889924566944096720f, 0.889574474967854580f, + 0.889223859677868210f, + 0.888872721280395630f, 0.888521059982002260f, 0.888168875989561730f, + 0.887816169510254440f, + 0.887462940751568840f, 0.887109189921300170f, 0.886754917227550840f, + 0.886400122878730600f, + 0.886044807083555600f, 0.885688970051048960f, 0.885332611990540590f, + 0.884975733111666660f, + 0.884618333624369920f, 0.884260413738899190f, 0.883901973665809470f, + 0.883543013615961880f, + 0.883183533800523390f, 0.882823534430966620f, 0.882463015719070150f, + 0.882101977876917580f, + 0.881740421116898320f, 0.881378345651706920f, 0.881015751694342870f, + 0.880652639458111010f, + 0.880289009156621010f, 0.879924861003786860f, 0.879560195213827890f, + 0.879195012001267480f, + 0.878829311580933360f, 0.878463094167957870f, 0.878096359977777130f, + 0.877729109226131570f, + 0.877361342129065140f, 0.876993058902925890f, 0.876624259764365310f, + 0.876254944930338510f, + 0.875885114618103810f, 0.875514769045222850f, 0.875143908429560360f, + 0.874772532989284150f, + 0.874400642942864790f, 0.874028238509075740f, 0.873655319906992630f, + 0.873281887355994210f, + 0.872907941075761080f, 0.872533481286276170f, 0.872158508207824480f, + 0.871783022060993120f, + 0.871407023066670950f, 0.871030511446048260f, 0.870653487420617430f, + 0.870275951212171940f, + 0.869897903042806340f, 0.869519343134916860f, 0.869140271711200560f, + 0.868760688994655310f, + 0.868380595208579800f, 0.867999990576573510f, 0.867618875322536230f, + 0.867237249670668400f, + 0.866855113845470430f, 0.866472468071743050f, 0.866089312574586770f, + 0.865705647579402380f, + 0.865321473311889800f, 0.864936789998049020f, 0.864551597864179340f, + 0.864165897136879300f, + 0.863779688043046720f, 0.863392970809878420f, 0.863005745664870320f, + 0.862618012835816740f, + 0.862229772550811240f, 0.861841025038245330f, 0.861451770526809320f, + 0.861062009245491480f, + 0.860671741423578380f, 0.860280967290654510f, 0.859889687076602290f, + 0.859497901011601730f, + 0.859105609326130450f, 0.858712812250963520f, 0.858319510017173440f, + 0.857925702856129790f, + 0.857531390999499150f, 0.857136574679244980f, 0.856741254127627470f, + 0.856345429577203610f, + 0.855949101260826910f, 0.855552269411646860f, 0.855154934263109620f, + 0.854757096048957220f, + 0.854358755003227440f, 0.853959911360254180f, 0.853560565354666840f, + 0.853160717221390420f, + 0.852760367195645300f, 0.852359515512947090f, 0.851958162409106380f, + 0.851556308120228980f, + 0.851153952882715340f, 0.850751096933260790f, 0.850347740508854980f, + 0.849943883846782210f, + 0.849539527184620890f, 0.849134670760243630f, 0.848729314811817130f, + 0.848323459577801640f, + 0.847917105296951410f, 0.847510252208314330f, 0.847102900551231500f, + 0.846695050565337450f, + 0.846286702490559710f, 0.845877856567119000f, 0.845468513035528830f, + 0.845058672136595470f, + 0.844648334111417820f, 0.844237499201387020f, 0.843826167648186740f, + 0.843414339693792760f, + 0.843002015580472940f, 0.842589195550786710f, 0.842175879847585570f, + 0.841762068714012490f, + 0.841347762393501950f, 0.840932961129779780f, 0.840517665166862550f, + 0.840101874749058400f, + 0.839685590120966110f, 0.839268811527475230f, 0.838851539213765760f, + 0.838433773425308340f, + 0.838015514407863820f, 0.837596762407483040f, 0.837177517670507300f, + 0.836757780443567190f, + 0.836337550973583530f, 0.835916829507766360f, 0.835495616293615350f, + 0.835073911578919410f, + 0.834651715611756440f, 0.834229028640493420f, 0.833805850913786340f, + 0.833382182680579730f, + 0.832958024190106670f, 0.832533375691888680f, 0.832108237435735590f, + 0.831682609671745120f, + 0.831256492650303210f, 0.830829886622083570f, 0.830402791838047550f, + 0.829975208549443950f, + 0.829547137007808910f, 0.829118577464965980f, 0.828689530173025820f, + 0.828259995384385660f, + 0.827829973351729920f, 0.827399464328029470f, 0.826968468566541600f, + 0.826536986320809960f, + 0.826105017844664610f, 0.825672563392221390f, 0.825239623217882250f, + 0.824806197576334330f, + 0.824372286722551250f, 0.823937890911791370f, 0.823503010399598500f, + 0.823067645441801670f, + 0.822631796294514990f, 0.822195463214137170f, 0.821758646457351750f, + 0.821321346281126740f, + 0.820883562942714580f, 0.820445296699652050f, 0.820006547809759680f, + 0.819567316531142230f, + 0.819127603122188240f, 0.818687407841569680f, 0.818246730948242070f, + 0.817805572701444270f, + 0.817363933360698460f, 0.816921813185809480f, 0.816479212436865390f, + 0.816036131374236810f, + 0.815592570258576790f, 0.815148529350820830f, 0.814704008912187080f, + 0.814259009204175270f, + 0.813813530488567190f, 0.813367573027426570f, 0.812921137083098770f, + 0.812474222918210480f, + 0.812026830795669730f, 0.811578960978665890f, 0.811130613730669190f, + 0.810681789315430780f, + 0.810232487996982330f, 0.809782710039636530f, 0.809332455707985950f, + 0.808881725266903610f, + 0.808430518981542720f, 0.807978837117336310f, 0.807526679939997160f, + 0.807074047715517610f, + 0.806620940710169650f, 0.806167359190504420f, 0.805713303423352230f, + 0.805258773675822210f, + 0.804803770215302920f, 0.804348293309460780f, 0.803892343226241260f, + 0.803435920233868120f, + 0.802979024600843250f, 0.802521656595946430f, 0.802063816488235440f, + 0.801605504547046150f, + 0.801146721041991360f, 0.800687466242961610f, 0.800227740420124790f, + 0.799767543843925680f, + 0.799306876785086160f, 0.798845739514604580f, 0.798384132303756380f, + 0.797922055424093000f, + 0.797459509147442460f, 0.796996493745908750f, 0.796533009491872000f, + 0.796069056657987990f, + 0.795604635517188070f, 0.795139746342679590f, 0.794674389407944550f, + 0.794208564986740640f, + 0.793742273353100210f, 0.793275514781330630f, 0.792808289546014120f, + 0.792340597922007170f, + 0.791872440184440470f, 0.791403816608719500f, 0.790934727470523290f, + 0.790465173045804880f, + 0.789995153610791090f, 0.789524669441982190f, 0.789053720816151880f, + 0.788582308010347120f, + 0.788110431301888070f, 0.787638090968367450f, 0.787165287287651010f, + 0.786692020537876790f, + 0.786218290997455660f, 0.785744098945070360f, 0.785269444659675850f, + 0.784794328420499230f, + 0.784318750507038920f, 0.783842711199065230f, 0.783366210776619720f, + 0.782889249520015480f, + 0.782411827709836530f, 0.781933945626937630f, 0.781455603552444590f, + 0.780976801767753750f, + 0.780497540554531910f, 0.780017820194715990f, 0.779537640970513260f, + 0.779057003164400630f, + 0.778575907059125050f, 0.778094352937702790f, 0.777612341083420030f, + 0.777129871779831620f, + 0.776646945310762060f, 0.776163561960304340f, 0.775679722012820650f, + 0.775195425752941420f, + 0.774710673465565550f, 0.774225465435860680f, 0.773739801949261840f, + 0.773253683291472590f, + 0.772767109748463850f, 0.772280081606474320f, 0.771792599152010150f, + 0.771304662671844830f, + 0.770816272453018540f, 0.770327428782838890f, 0.769838131948879840f, + 0.769348382238982280f, + 0.768858179941253270f, 0.768367525344066270f, 0.767876418736060610f, + 0.767384860406141730f, + 0.766892850643480670f, 0.766400389737514230f, 0.765907477977944340f, + 0.765414115654738270f, + 0.764920303058128410f, 0.764426040478612070f, 0.763931328206951090f, + 0.763436166534172010f, + 0.762940555751565720f, 0.762444496150687210f, 0.761947988023355390f, + 0.761451031661653620f, + 0.760953627357928150f, 0.760455775404789260f, 0.759957476095110330f, + 0.759458729722028210f, + 0.758959536578942440f, 0.758459896959515430f, 0.757959811157672300f, + 0.757459279467600720f, + 0.756958302183750490f, 0.756456879600833740f, 0.755955012013824420f, + 0.755452699717958250f, + 0.754949943008732640f, 0.754446742181906440f, 0.753943097533499640f, + 0.753439009359793580f, + 0.752934477957330150f, 0.752429503622912390f, 0.751924086653603550f, + 0.751418227346727470f, + 0.750911925999867890f, 0.750405182910869330f, 0.749897998377835330f, + 0.749390372699129560f, + 0.748882306173375150f, 0.748373799099454560f, 0.747864851776509410f, + 0.747355464503940190f, + 0.746845637581406540f, 0.746335371308826320f, 0.745824665986376090f, + 0.745313521914490520f, + 0.744801939393862630f, 0.744289918725443260f, 0.743777460210440890f, + 0.743264564150321600f, + 0.742751230846809050f, 0.742237460601884000f, 0.741723253717784140f, + 0.741208610497004260f, + 0.740693531242295760f, 0.740178016256666240f, 0.739662065843380010f, + 0.739145680305957510f, + 0.738628859948174840f, 0.738111605074064260f, 0.737593915987913570f, + 0.737075792994265730f, + 0.736557236397919150f, 0.736038246503927350f, 0.735518823617598900f, + 0.734998968044496710f, + 0.734478680090438370f, 0.733957960061495940f, 0.733436808263995710f, + 0.732915225004517780f, + 0.732393210589896040f, 0.731870765327218290f, 0.731347889523825570f, + 0.730824583487312160f, + 0.730300847525525490f, 0.729776681946566090f, 0.729252087058786970f, + 0.728727063170793830f, + 0.728201610591444610f, 0.727675729629849610f, 0.727149420595371020f, + 0.726622683797622850f, + 0.726095519546471000f, 0.725567928152032300f, 0.725039909924675370f, + 0.724511465175019630f, + 0.723982594213935520f, 0.723453297352544380f, 0.722923574902217700f, + 0.722393427174577550f, + 0.721862854481496340f, 0.721331857135096290f, 0.720800435447749190f, + 0.720268589732077190f, + 0.719736320300951030f, 0.719203627467491220f, 0.718670511545067230f, + 0.718136972847297490f, + 0.717603011688049080f, 0.717068628381437480f, 0.716533823241826680f, + 0.715998596583828690f, + 0.715462948722303760f, 0.714926879972359490f, 0.714390390649351390f, + 0.713853481068882470f, + 0.713316151546802610f, 0.712778402399208980f, 0.712240233942445510f, + 0.711701646493102970f, + 0.711162640368018350f, 0.710623215884275020f, 0.710083373359202800f, + 0.709543113110376770f, + 0.709002435455618250f, 0.708461340712994160f, 0.707919829200816310f, + 0.707377901237642100f, + 0.706835557142273860f, 0.706292797233758480f, 0.705749621831387790f, + 0.705206031254697830f, + 0.704662025823468930f, 0.704117605857725430f, 0.703572771677735580f, + 0.703027523604011220f, + 0.702481861957308000f, 0.701935787058624360f, 0.701389299229202230f, + 0.700842398790526230f, + 0.700295086064323780f, 0.699747361372564990f, 0.699199225037462120f, + 0.698650677381469580f, + 0.698101718727283880f, 0.697552349397843270f, 0.697002569716327460f, + 0.696452380006157830f, + 0.695901780590996830f, 0.695350771794747800f, 0.694799353941554900f, + 0.694247527355803310f, + 0.693695292362118350f, 0.693142649285365510f, 0.692589598450650380f, + 0.692036140183318830f, + 0.691482274808955850f, 0.690928002653386280f, 0.690373324042674040f, + 0.689818239303122470f, + 0.689262748761273470f, 0.688706852743907750f, 0.688150551578044830f, + 0.687593845590942170f, + 0.687036735110095660f, 0.686479220463238950f, 0.685921301978343670f, + 0.685362979983618730f, + 0.684804254807510620f, 0.684245126778703080f, 0.683685596226116690f, + 0.683125663478908800f, + 0.682565328866473250f, 0.682004592718440830f, 0.681443455364677990f, + 0.680881917135287340f, + 0.680319978360607200f, 0.679757639371212030f, 0.679194900497911200f, + 0.678631762071749470f, + 0.678068224424006600f, 0.677504287886197430f, 0.676939952790071240f, + 0.676375219467611700f, + 0.675810088251037060f, 0.675244559472799270f, 0.674678633465584540f, + 0.674112310562312360f, + 0.673545591096136100f, 0.672978475400442090f, 0.672410963808849900f, + 0.671843056655211930f, + 0.671274754273613490f, 0.670706056998372160f, 0.670136965164037760f, + 0.669567479105392490f, + 0.668997599157450270f, 0.668427325655456820f, 0.667856658934889440f, + 0.667285599331456480f, + 0.666714147181097670f, 0.666142302819983540f, 0.665570066584515560f, + 0.664997438811325340f, + 0.664424419837275180f, 0.663851009999457340f, 0.663277209635194100f, + 0.662703019082037440f, + 0.662128438677768720f, 0.661553468760399000f, 0.660978109668168060f, + 0.660402361739545030f, + 0.659826225313227430f, 0.659249700728141490f, 0.658672788323441890f, + 0.658095488438511290f, + 0.657517801412960120f, 0.656939727586627110f, 0.656361267299578000f, + 0.655782420892106030f, + 0.655203188704731930f, 0.654623571078202680f, 0.654043568353492640f, + 0.653463180871802330f, + 0.652882408974558960f, 0.652301253003415460f, 0.651719713300251020f, + 0.651137790207170330f, + 0.650555484066503990f, 0.649972795220807530f, 0.649389724012861770f, + 0.648806270785672550f, + 0.648222435882470420f, 0.647638219646710420f, 0.647053622422071650f, + 0.646468644552457890f, + 0.645883286381996440f, 0.645297548255038380f, 0.644711430516158420f, + 0.644124933510154540f, + 0.643538057582047850f, 0.642950803077082080f, 0.642363170340724320f, + 0.641775159718663500f, + 0.641186771556811250f, 0.640598006201301030f, 0.640008863998488440f, + 0.639419345294950700f, + 0.638829450437486400f, 0.638239179773115390f, 0.637648533649078810f, + 0.637057512412838590f, + 0.636466116412077180f, 0.635874345994697720f, 0.635282201508823530f, + 0.634689683302797850f, + 0.634096791725183740f, 0.633503527124764320f, 0.632909889850541860f, + 0.632315880251737680f, + 0.631721498677792370f, 0.631126745478365340f, 0.630531621003334600f, + 0.629936125602796550f, + 0.629340259627065750f, 0.628744023426674790f, 0.628147417352374120f, + 0.627550441755131530f, + 0.626953096986132770f, 0.626355383396779990f, 0.625757301338692900f, + 0.625158851163707730f, + 0.624560033223877320f, 0.623960847871470770f, 0.623361295458973340f, + 0.622761376339086460f, + 0.622161090864726930f, 0.621560439389027270f, 0.620959422265335180f, + 0.620358039847213830f, + 0.619756292488440660f, 0.619154180543008410f, 0.618551704365123860f, + 0.617948864309208260f, + 0.617345660729896940f, 0.616742093982038830f, 0.616138164420696910f, + 0.615533872401147430f, + 0.614929218278879590f, 0.614324202409595950f, 0.613718825149211830f, + 0.613113086853854910f, + 0.612506987879865570f, 0.611900528583796070f, 0.611293709322411010f, + 0.610686530452686280f, + 0.610078992331809620f, 0.609471095317180240f, 0.608862839766408200f, + 0.608254226037314490f, + 0.607645254487930830f, 0.607035925476499760f, 0.606426239361473550f, + 0.605816196501515080f, + 0.605205797255496500f, 0.604595041982500360f, 0.603983931041818020f, + 0.603372464792950370f, + 0.602760643595607220f, 0.602148467809707320f, 0.601535937795377730f, + 0.600923053912954090f, + 0.600309816522980430f, 0.599696225986208310f, 0.599082282663597310f, + 0.598467986916314310f, + 0.597853339105733910f, 0.597238339593437530f, 0.596622988741213330f, + 0.596007286911056530f, + 0.595391234465168730f, 0.594774831765957580f, 0.594158079176036800f, + 0.593540977058226390f, + 0.592923525775551410f, 0.592305725691242400f, 0.591687577168735550f, + 0.591069080571671510f, + 0.590450236263895920f, 0.589831044609458900f, 0.589211505972615070f, + 0.588591620717822890f, + 0.587971389209745120f, 0.587350811813247660f, 0.586729888893400500f, + 0.586108620815476430f, + 0.585487007944951450f, 0.584865050647504490f, 0.584242749289016980f, + 0.583620104235572760f, + 0.582997115853457700f, 0.582373784509160220f, 0.581750110569369760f, + 0.581126094400977620f, + 0.580501736371076600f, 0.579877036846960350f, 0.579251996196123550f, + 0.578626614786261430f, + 0.578000892985269910f, 0.577374831161244880f, 0.576748429682482520f, + 0.576121688917478390f, + 0.575494609234928230f, 0.574867191003726740f, 0.574239434592967890f, + 0.573611340371944610f, + 0.572982908710148680f, 0.572354139977270030f, 0.571725034543197120f, + 0.571095592778016690f, + 0.570465815052012990f, 0.569835701735668110f, 0.569205253199661200f, + 0.568574469814869250f, + 0.567943351952365670f, 0.567311899983420800f, 0.566680114279501710f, + 0.566047995212271560f, + 0.565415543153589770f, 0.564782758475511400f, 0.564149641550287680f, + 0.563516192750364910f, + 0.562882412448384550f, 0.562248301017183150f, 0.561613858829792420f, + 0.560979086259438260f, + 0.560343983679540860f, 0.559708551463714790f, 0.559072789985768480f, + 0.558436699619704100f, + 0.557800280739717100f, 0.557163533720196340f, 0.556526458935723720f, + 0.555889056761073920f, + 0.555251327571214090f, 0.554613271741304040f, 0.553974889646695610f, + 0.553336181662932410f, + 0.552697148165749770f, 0.552057789531074980f, 0.551418106135026060f, + 0.550778098353912230f, + 0.550137766564233630f, 0.549497111142680960f, 0.548856132466135290f, + 0.548214830911667780f, + 0.547573206856539870f, 0.546931260678202190f, 0.546288992754295210f, + 0.545646403462648590f, + 0.545003493181281160f, 0.544360262288400400f, 0.543716711162402390f, + 0.543072840181871850f, + 0.542428649725581360f, 0.541784140172491660f, 0.541139311901750910f, + 0.540494165292695230f, + 0.539848700724847700f, 0.539202918577918240f, 0.538556819231804210f, + 0.537910403066588990f, + 0.537263670462542530f, 0.536616621800121150f, 0.535969257459966710f, + 0.535321577822907010f, + 0.534673583269955510f, 0.534025274182310380f, 0.533376650941355560f, + 0.532727713928658810f, + 0.532078463525973540f, 0.531428900115236910f, 0.530779024078570250f, + 0.530128835798278850f, + 0.529478335656852090f, 0.528827524036961980f, 0.528176401321464370f, + 0.527524967893398200f, + 0.526873224135984700f, 0.526221170432628170f, 0.525568807166914680f, + 0.524916134722612890f, + 0.524263153483673470f, 0.523609863834228030f, 0.522956266158590140f, + 0.522302360841254700f, + 0.521648148266897090f, 0.520993628820373810f, 0.520338802886721960f, + 0.519683670851158520f, + 0.519028233099080970f, 0.518372490016066220f, 0.517716441987871150f, + 0.517060089400432130f, + 0.516403432639863990f, 0.515746472092461380f, 0.515089208144697270f, + 0.514431641183222930f, + 0.513773771594868030f, 0.513115599766640560f, 0.512457126085725800f, + 0.511798350939487000f, + 0.511139274715464390f, 0.510479897801375700f, 0.509820220585115560f, + 0.509160243454754750f, + 0.508499966798540810f, 0.507839391004897940f, 0.507178516462425290f, + 0.506517343559898530f, + 0.505855872686268860f, 0.505194104230662240f, 0.504532038582380380f, + 0.503869676130898950f, + 0.503207017265869030f, 0.502544062377115800f, 0.501880811854638400f, + 0.501217266088609950f, + 0.500553425469377640f, 0.499889290387461380f, 0.499224861233555030f, + 0.498560138398525200f, + 0.497895122273410930f, 0.497229813249424340f, 0.496564211717949340f, + 0.495898318070542240f, + 0.495232132698931350f, 0.494565655995016010f, 0.493898888350867430f, + 0.493231830158728070f, + 0.492564481811010650f, 0.491896843700299240f, 0.491228916219348330f, + 0.490560699761082080f, + 0.489892194718595300f, 0.489223401485152030f, 0.488554320454186230f, + 0.487884952019301210f, + 0.487215296574268820f, 0.486545354513030270f, 0.485875126229695420f, + 0.485204612118541880f, + 0.484533812574016120f, 0.483862727990732320f, 0.483191358763471910f, + 0.482519705287184520f, + 0.481847767956986080f, 0.481175547168160360f, 0.480503043316157670f, + 0.479830256796594250f, + 0.479157188005253310f, 0.478483837338084080f, 0.477810205191201040f, + 0.477136291960884750f, + 0.476462098043581310f, 0.475787623835901120f, 0.475112869734620470f, + 0.474437836136679340f, + 0.473762523439182850f, 0.473086932039400220f, 0.472411062334764100f, + 0.471734914722871430f, + 0.471058489601482610f, 0.470381787368520710f, 0.469704808422072460f, + 0.469027553160387240f, + 0.468350021981876530f, 0.467672215285114710f, 0.466994133468838110f, + 0.466315776931944480f, + 0.465637146073493770f, 0.464958241292706740f, 0.464279062988965760f, + 0.463599611561814120f, + 0.462919887410955130f, 0.462239890936253280f, 0.461559622537733190f, + 0.460879082615578690f, + 0.460198271570134270f, 0.459517189801903590f, 0.458835837711549120f, + 0.458154215699893230f, + 0.457472324167916110f, 0.456790163516757220f, 0.456107734147714220f, + 0.455425036462242420f, + 0.454742070861955450f, 0.454058837748624540f, 0.453375337524177750f, + 0.452691570590700860f, + 0.452007537350436530f, 0.451323238205783520f, 0.450638673559297760f, + 0.449953843813690580f, + 0.449268749371829920f, 0.448583390636739300f, 0.447897768011597360f, + 0.447211881899738260f, + 0.446525732704651400f, 0.445839320829980350f, 0.445152646679523590f, + 0.444465710657234110f, + 0.443778513167218280f, 0.443091054613736990f, 0.442403335401204130f, + 0.441715355934187310f, + 0.441027116617407340f, 0.440338617855737300f, 0.439649860054203420f, + 0.438960843617984430f, + 0.438271568952410480f, 0.437582036462964340f, 0.436892246555280470f, + 0.436202199635143950f, + 0.435511896108492170f, 0.434821336381412350f, 0.434130520860143310f, + 0.433439449951074200f, + 0.432748124060743760f, 0.432056543595841450f, 0.431364708963206440f, + 0.430672620569826860f, + 0.429980278822840570f, 0.429287684129534720f, 0.428594836897344400f, + 0.427901737533854240f, + 0.427208386446796370f, 0.426514784044051520f, 0.425820930733648350f, + 0.425126826923762410f, + 0.424432473022717420f, 0.423737869438983950f, 0.423043016581179100f, + 0.422347914858067000f, + 0.421652564678558380f, 0.420956966451709440f, 0.420261120586723050f, + 0.419565027492946940f, + 0.418868687579875110f, 0.418172101257146430f, 0.417475268934544340f, + 0.416778191021997590f, + 0.416080867929579320f, 0.415383300067506290f, 0.414685487846140010f, + 0.413987431675985510f, + 0.413289131967690960f, 0.412590589132048380f, 0.411891803579992220f, + 0.411192775722600160f, + 0.410493505971092520f, 0.409793994736831200f, 0.409094242431320920f, + 0.408394249466208110f, + 0.407694016253280170f, 0.406993543204466460f, 0.406292830731837470f, + 0.405591879247603870f, + 0.404890689164117750f, 0.404189260893870750f, 0.403487594849495310f, + 0.402785691443763640f, + 0.402083551089587040f, 0.401381174200016790f, 0.400678561188243350f, + 0.399975712467595390f, + 0.399272628451540930f, 0.398569309553686360f, 0.397865756187775750f, + 0.397161968767691720f, + 0.396457947707453960f, 0.395753693421220080f, 0.395049206323284880f, + 0.394344486828079650f, + 0.393639535350172880f, 0.392934352304269600f, 0.392228938105210370f, + 0.391523293167972350f, + 0.390817417907668610f, 0.390111312739546910f, 0.389404978078991100f, + 0.388698414341519250f, + 0.387991621942784910f, 0.387284601298575890f, 0.386577352824813980f, + 0.385869876937555310f, + 0.385162174052989970f, 0.384454244587440870f, 0.383746088957365010f, + 0.383037707579352130f, + 0.382329100870124510f, 0.381620269246537520f, 0.380911213125578130f, + 0.380201932924366050f, + 0.379492429060152740f, 0.378782701950320600f, 0.378072752012383990f, + 0.377362579663988450f, + 0.376652185322909620f, 0.375941569407054420f, 0.375230732334460030f, + 0.374519674523293210f, + 0.373808396391851370f, 0.373096898358560690f, 0.372385180841977360f, + 0.371673244260786630f, + 0.370961089033802040f, 0.370248715579966360f, 0.369536124318350760f, + 0.368823315668153960f, + 0.368110290048703050f, 0.367397047879452820f, 0.366683589579984930f, + 0.365969915570008910f, + 0.365256026269360380f, 0.364541922098002180f, 0.363827603476023610f, + 0.363113070823639530f, + 0.362398324561191310f, 0.361683365109145950f, 0.360968192888095290f, + 0.360252808318756830f, + 0.359537211821973180f, 0.358821403818710860f, 0.358105384730061760f, + 0.357389154977241000f, + 0.356672714981588260f, 0.355956065164567010f, 0.355239205947763370f, + 0.354522137752887430f, + 0.353804861001772160f, 0.353087376116372530f, 0.352369683518766630f, + 0.351651783631154680f, + 0.350933676875858360f, 0.350215363675321740f, 0.349496844452109600f, + 0.348778119628908420f, + 0.348059189628525780f, 0.347340054873889190f, 0.346620715788047320f, + 0.345901172794169100f, + 0.345181426315542610f, 0.344461476775576480f, 0.343741324597798600f, + 0.343020970205855540f, + 0.342300414023513690f, 0.341579656474657210f, 0.340858697983289440f, + 0.340137538973531880f, + 0.339416179869623410f, 0.338694621095921190f, 0.337972863076899830f, + 0.337250906237150650f, + 0.336528751001382350f, 0.335806397794420560f, 0.335083847041206580f, + 0.334361099166798900f, + 0.333638154596370920f, 0.332915013755212650f, 0.332191677068729320f, + 0.331468144962440920f, + 0.330744417861982890f, 0.330020496193105530f, 0.329296380381672800f, + 0.328572070853663690f, + 0.327847568035170960f, 0.327122872352400510f, 0.326397984231672660f, + 0.325672904099419900f, + 0.324947632382188430f, 0.324222169506637130f, 0.323496515899536760f, + 0.322770671987770710f, + 0.322044638198334620f, 0.321318414958334910f, 0.320592002694990330f, + 0.319865401835630610f, + 0.319138612807695900f, 0.318411636038737960f, 0.317684471956418020f, + 0.316957120988508150f, + 0.316229583562890490f, 0.315501860107556040f, 0.314773951050606070f, + 0.314045856820250820f, + 0.313317577844809070f, 0.312589114552708660f, 0.311860467372486130f, + 0.311131636732785270f, + 0.310402623062358880f, 0.309673426790066490f, 0.308944048344875710f, + 0.308214488155861220f, + 0.307484746652204160f, 0.306754824263192780f, 0.306024721418221900f, + 0.305294438546791720f, + 0.304563976078509050f, 0.303833334443086470f, 0.303102514070341060f, + 0.302371515390196130f, + 0.301640338832678880f, 0.300908984827921890f, 0.300177453806162120f, + 0.299445746197739950f, + 0.298713862433100390f, 0.297981802942791920f, 0.297249568157465890f, + 0.296517158507877410f, + 0.295784574424884370f, 0.295051816339446720f, 0.294318884682627570f, + 0.293585779885591310f, + 0.292852502379604810f, 0.292119052596036540f, 0.291385430966355720f, + 0.290651637922133220f, + 0.289917673895040860f, 0.289183539316850310f, 0.288449234619434170f, + 0.287714760234765280f, + 0.286980116594915570f, 0.286245304132057120f, 0.285510323278461380f, + 0.284775174466498300f, + 0.284039858128637360f, 0.283304374697445790f, 0.282568724605589740f, + 0.281832908285833460f, + 0.281096926171038320f, 0.280360778694163810f, 0.279624466288266700f, + 0.278887989386500280f, + 0.278151348422115090f, 0.277414543828458200f, 0.276677576038972420f, + 0.275940445487197320f, + 0.275203152606767370f, 0.274465697831413220f, 0.273728081594960650f, + 0.272990304331329980f, + 0.272252366474536660f, 0.271514268458690810f, 0.270776010717996010f, + 0.270037593686750510f, + 0.269299017799346230f, 0.268560283490267890f, 0.267821391194094320f, + 0.267082341345496350f, + 0.266343134379238180f, 0.265603770730176440f, 0.264864250833259320f, + 0.264124575123527490f, + 0.263384744036113390f, 0.262644758006240100f, 0.261904617469222560f, + 0.261164322860466590f, + 0.260423874615468010f, 0.259683273169813930f, 0.258942518959180580f, + 0.258201612419334870f, + 0.257460553986133210f, 0.256719344095520720f, 0.255977983183532380f, + 0.255236471686291820f, + 0.254494810040010790f, 0.253752998680989940f, 0.253011038045617980f, + 0.252268928570370810f, + 0.251526670691812780f, 0.250784264846594550f, 0.250041711471454650f, + 0.249299011003218300f, + 0.248556163878796620f, 0.247813170535187620f, 0.247070031409475370f, + 0.246326746938829060f, + 0.245583317560504000f, 0.244839743711840750f, 0.244096025830264210f, + 0.243352164353284880f, + 0.242608159718496890f, 0.241864012363579210f, 0.241119722726294730f, + 0.240375291244489500f, + 0.239630718356093560f, 0.238886004499120170f, 0.238141150111664870f, + 0.237396155631906550f, + 0.236651021498106460f, 0.235905748148607370f, 0.235160336021834860f, + 0.234414785556295250f, + 0.233669097190576820f, 0.232923271363349120f, 0.232177308513361770f, + 0.231431209079445730f, + 0.230684973500512310f, 0.229938602215552260f, 0.229192095663636740f, + 0.228445454283916550f, + 0.227698678515621170f, 0.226951768798059980f, 0.226204725570620270f, + 0.225457549272768540f, + 0.224710240344049570f, 0.223962799224085520f, 0.223215226352576960f, + 0.222467522169301990f, + 0.221719687114115240f, 0.220971721626949060f, 0.220223626147812460f, + 0.219475401116790340f, + 0.218727046974044600f, 0.217978564159812290f, 0.217229953114406790f, + 0.216481214278216900f, + 0.215732348091705940f, 0.214983354995412820f, 0.214234235429951100f, + 0.213484989836008080f, + 0.212735618654345870f, 0.211986122325800410f, 0.211236501291280710f, + 0.210486755991769890f, + 0.209736886868323370f, 0.208986894362070070f, 0.208236778914211470f, + 0.207486540966020700f, + 0.206736180958843660f, 0.205985699334098050f, 0.205235096533272380f, + 0.204484372997927180f, + 0.203733529169694010f, 0.202982565490274460f, 0.202231482401441620f, + 0.201480280345037820f, + 0.200728959762976140f, 0.199977521097239290f, 0.199225964789878890f, + 0.198474291283016360f, + 0.197722501018842030f, 0.196970594439614370f, 0.196218571987660850f, + 0.195466434105377090f, + 0.194714181235225990f, 0.193961813819739010f, 0.193209332301514080f, + 0.192456737123216840f, + 0.191704028727579940f, 0.190951207557401860f, 0.190198274055548120f, + 0.189445228664950340f, + 0.188692071828605260f, 0.187938803989575850f, 0.187185425590990440f, + 0.186431937076041640f, + 0.185678338887987790f, 0.184924631470150870f, 0.184170815265917720f, + 0.183416890718739230f, + 0.182662858272129360f, 0.181908718369666160f, 0.181154471454990920f, + 0.180400117971807270f, + 0.179645658363882100f, 0.178891093075044830f, 0.178136422549186320f, + 0.177381647230260200f, + 0.176626767562280960f, 0.175871783989325040f, 0.175116696955530060f, + 0.174361506905093830f, + 0.173606214282275410f, 0.172850819531394200f, 0.172095323096829040f, + 0.171339725423019260f, + 0.170584026954463700f, 0.169828228135719880f, 0.169072329411405180f, + 0.168316331226194910f, + 0.167560234024823590f, 0.166804038252083870f, 0.166047744352825850f, + 0.165291352771957970f, + 0.164534863954446110f, 0.163778278345312690f, 0.163021596389637810f, + 0.162264818532558110f, + 0.161507945219266150f, 0.160750976895011390f, 0.159993914005098350f, + 0.159236756994887850f, + 0.158479506309796100f, 0.157722162395293690f, 0.156964725696906750f, + 0.156207196660216040f, + 0.155449575730855880f, 0.154691863354515400f, 0.153934059976937460f, + 0.153176166043917870f, + 0.152418182001306500f, 0.151660108295005400f, 0.150901945370970040f, + 0.150143693675208330f, + 0.149385353653779810f, 0.148626925752796540f, 0.147868410418422360f, + 0.147109808096871850f, + 0.146351119234411440f, 0.145592344277358450f, 0.144833483672080240f, + 0.144074537864995330f, + 0.143315507302571590f, 0.142556392431327340f, 0.141797193697830530f, + 0.141037911548697770f, + 0.140278546430595420f, 0.139519098790238600f, 0.138759569074390380f, + 0.137999957729862760f, + 0.137240265203515700f, 0.136480491942256310f, 0.135720638393040080f, + 0.134960705002868830f, + 0.134200692218792020f, 0.133440600487905820f, 0.132680430257352130f, + 0.131920181974319760f, + 0.131159856086043410f, 0.130399453039802740f, 0.129638973282923540f, + 0.128878417262776660f, + 0.128117785426777150f, 0.127357078222385570f, 0.126596296097105960f, + 0.125835439498487020f, + 0.125074508874121300f, 0.124313504671644300f, 0.123552427338735370f, + 0.122791277323116900f, + 0.122030055072553410f, 0.121268761034852550f, 0.120507395657864240f, + 0.119745959389479630f, + 0.118984452677632520f, 0.118222875970297250f, 0.117461229715489990f, + 0.116699514361267840f, + 0.115937730355727850f, 0.115175878147008180f, 0.114413958183287050f, + 0.113651970912781920f, + 0.112889916783750470f, 0.112127796244489750f, 0.111365609743335190f, + 0.110603357728661910f, + 0.109841040648882680f, 0.109078658952449240f, 0.108316213087851300f, + 0.107553703503615710f, + 0.106791130648307380f, 0.106028494970528530f, 0.105265796918917650f, + 0.104503036942150550f, + 0.103740215488939480f, 0.102977333008032250f, 0.102214389948213370f, + 0.101451386758302160f, + 0.100688323887153970f, 0.099925201783659226f, 0.099162020896742573f, + 0.098398781675363881f, + 0.097635484568517339f, 0.096872130025230527f, 0.096108718494565468f, + 0.095345250425617742f, + 0.094581726267515473f, 0.093818146469420494f, 0.093054511480527333f, + 0.092290821750062355f, + 0.091527077727284981f, 0.090763279861485704f, 0.089999428601987341f, + 0.089235524398144139f, + 0.088471567699340822f, 0.087707558954993645f, 0.086943498614549489f, + 0.086179387127484922f, + 0.085415224943307277f, 0.084651012511553700f, 0.083886750281790226f, + 0.083122438703613077f, + 0.082358078226646619f, 0.081593669300544638f, 0.080829212374989468f, + 0.080064707899690932f, + 0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f, + 0.077006223496245585f, + 0.076241488018856149f, 0.075476707690563416f, 0.074711882961268378f, + 0.073947014280897269f, + 0.073182102099402888f, 0.072417146866763538f, 0.071652149032982254f, + 0.070887109048087787f, + 0.070122027362133646f, 0.069356904425197236f, 0.068591740687380900f, + 0.067826536598810966f, + 0.067061292609636836f, 0.066296009170032283f, 0.065530686730193397f, + 0.064765325740339871f, + 0.063999926650714078f, 0.063234489911580136f, 0.062469015973224969f, + 0.061703505285957416f, + 0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f, + 0.058641104054683348f, + 0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f, + 0.055578150871004817f, + 0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f, + 0.052514674564603257f, + 0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f, + 0.049450703970084824f, + 0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f, + 0.046386267926707213f, + 0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f, + 0.043321395278109784f, + 0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f, + 0.040256114872041358f, + 0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f, + 0.037190455560088091f, + 0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f, + 0.034124446197403423f, + 0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f, + 0.031058115642434700f, + 0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f, + 0.027991492756653365f, + 0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f, + 0.024924606404281485f, + 0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f, + 0.021857485452021874f, + 0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f, + 0.018790158768784596f, + 0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f, + 0.015722655225417017f, + 0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f, + 0.012655003694430301f, + 0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f, + 0.009587233049729183f, + 0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f, + 0.006519372166339549f, + 0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f, + 0.003451449920135975f, + 0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f, + 0.000383495187571497f +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + const float32_t Weights_8192[16384] = { + 1.000000000000000000f, -0.000000000000000000f, 0.999999981616429330f, + -0.000191747597310703f, + 0.999999926465717890f, -0.000383495187571396f, 0.999999834547867670f, + -0.000575242763732066f, + 0.999999705862882230f, -0.000766990318742704f, 0.999999540410766110f, + -0.000958737845553301f, + 0.999999338191525530f, -0.001150485337113849f, 0.999999099205167830f, + -0.001342232786374338f, + 0.999998823451701880f, -0.001533980186284766f, 0.999998510931137790f, + -0.001725727529795126f, + 0.999998161643486980f, -0.001917474809855419f, 0.999997775588762350f, + -0.002109222019415644f, + 0.999997352766978210f, -0.002300969151425805f, 0.999996893178149880f, + -0.002492716198835908f, + 0.999996396822294350f, -0.002684463154595962f, 0.999995863699429940f, + -0.002876210011655979f, + 0.999995293809576190f, -0.003067956762965976f, 0.999994687152754080f, + -0.003259703401475973f, + 0.999994043728985820f, -0.003451449920135994f, 0.999993363538295150f, + -0.003643196311896068f, + 0.999992646580707190f, -0.003834942569706228f, 0.999991892856248010f, + -0.004026688686516512f, + 0.999991102364945590f, -0.004218434655276963f, 0.999990275106828920f, + -0.004410180468937631f, + 0.999989411081928400f, -0.004601926120448571f, 0.999988510290275690f, + -0.004793671602759841f, + 0.999987572731904080f, -0.004985416908821511f, 0.999986598406848000f, + -0.005177162031583651f, + 0.999985587315143200f, -0.005368906963996343f, 0.999984539456826970f, + -0.005560651699009674f, + 0.999983454831937730f, -0.005752396229573736f, 0.999982333440515350f, + -0.005944140548638633f, + 0.999981175282601110f, -0.006135884649154475f, 0.999979980358237650f, + -0.006327628524071378f, + 0.999978748667468830f, -0.006519372166339468f, 0.999977480210339940f, + -0.006711115568908879f, + 0.999976174986897610f, -0.006902858724729756f, 0.999974832997189810f, + -0.007094601626752250f, + 0.999973454241265940f, -0.007286344267926521f, 0.999972038719176730f, + -0.007478086641202744f, + 0.999970586430974140f, -0.007669828739531097f, 0.999969097376711580f, + -0.007861570555861772f, + 0.999967571556443780f, -0.008053312083144972f, 0.999966008970226920f, + -0.008245053314330906f, + 0.999964409618118280f, -0.008436794242369799f, 0.999962773500176930f, + -0.008628534860211886f, + 0.999961100616462820f, -0.008820275160807412f, 0.999959390967037450f, + -0.009012015137106633f, + 0.999957644551963900f, -0.009203754782059819f, 0.999955861371306100f, + -0.009395494088617252f, + 0.999954041425129780f, -0.009587233049729225f, 0.999952184713501780f, + -0.009778971658346044f, + 0.999950291236490480f, -0.009970709907418031f, 0.999948360994165400f, + -0.010162447789895513f, + 0.999946393986597460f, -0.010354185298728842f, 0.999944390213859060f, + -0.010545922426868378f, + 0.999942349676023910f, -0.010737659167264491f, 0.999940272373166960f, + -0.010929395512867571f, + 0.999938158305364590f, -0.011121131456628021f, 0.999936007472694620f, + -0.011312866991496258f, + 0.999933819875236000f, -0.011504602110422714f, 0.999931595513069200f, + -0.011696336806357838f, + 0.999929334386276070f, -0.011888071072252092f, 0.999927036494939640f, + -0.012079804901055957f, + 0.999924701839144500f, -0.012271538285719925f, 0.999922330418976490f, + -0.012463271219194511f, + 0.999919922234522750f, -0.012655003694430242f, 0.999917477285871770f, + -0.012846735704377662f, + 0.999914995573113470f, -0.013038467241987334f, 0.999912477096339240f, + -0.013230198300209835f, + 0.999909921855641540f, -0.013421928871995765f, 0.999907329851114300f, + -0.013613658950295740f, + 0.999904701082852900f, -0.013805388528060391f, 0.999902035550953920f, + -0.013997117598240367f, + 0.999899333255515390f, -0.014188846153786345f, 0.999896594196636680f, + -0.014380574187649006f, + 0.999893818374418490f, -0.014572301692779064f, 0.999891005788962950f, + -0.014764028662127246f, + 0.999888156440373320f, -0.014955755088644296f, 0.999885270328754520f, + -0.015147480965280987f, + 0.999882347454212560f, -0.015339206284988100f, 0.999879387816854930f, + -0.015530931040716447f, + 0.999876391416790410f, -0.015722655225416857f, 0.999873358254129260f, + -0.015914378832040183f, + 0.999870288328982950f, -0.016106101853537287f, 0.999867181641464380f, + -0.016297824282859065f, + 0.999864038191687680f, -0.016489546112956437f, 0.999860857979768540f, + -0.016681267336780332f, + 0.999857641005823860f, -0.016872987947281710f, 0.999854387269971890f, + -0.017064707937411563f, + 0.999851096772332190f, -0.017256427300120877f, 0.999847769513025900f, + -0.017448146028360693f, + 0.999844405492175240f, -0.017639864115082053f, 0.999841004709904000f, + -0.017831581553236039f, + 0.999837567166337090f, -0.018023298335773746f, 0.999834092861600960f, + -0.018215014455646290f, + 0.999830581795823400f, -0.018406729905804820f, 0.999827033969133420f, + -0.018598444679200511f, + 0.999823449381661570f, -0.018790158768784555f, 0.999819828033539420f, + -0.018981872167508178f, + 0.999816169924900410f, -0.019173584868322623f, 0.999812475055878780f, + -0.019365296864179156f, + 0.999808743426610520f, -0.019557008148029083f, 0.999804975037232870f, + -0.019748718712823729f, + 0.999801169887884260f, -0.019940428551514441f, 0.999797327978704690f, + -0.020132137657052594f, + 0.999793449309835270f, -0.020323846022389593f, 0.999789533881418780f, + -0.020515553640476875f, + 0.999785581693599210f, -0.020707260504265895f, 0.999781592746521670f, + -0.020898966606708137f, + 0.999777567040332940f, -0.021090671940755121f, 0.999773504575180990f, + -0.021282376499358387f, + 0.999769405351215280f, -0.021474080275469508f, 0.999765269368586450f, + -0.021665783262040078f, + 0.999761096627446610f, -0.021857485452021735f, 0.999756887127949080f, + -0.022049186838366135f, + 0.999752640870248840f, -0.022240887414024961f, 0.999748357854501780f, + -0.022432587171949934f, + 0.999744038080865430f, -0.022624286105092803f, 0.999739681549498660f, + -0.022815984206405345f, + 0.999735288260561680f, -0.023007681468839369f, 0.999730858214216030f, + -0.023199377885346720f, + 0.999726391410624470f, -0.023391073448879258f, 0.999721887849951310f, + -0.023582768152388894f, + 0.999717347532362190f, -0.023774461988827555f, 0.999712770458023870f, + -0.023966154951147210f, + 0.999708156627104880f, -0.024157847032299864f, 0.999703506039774650f, + -0.024349538225237534f, + 0.999698818696204250f, -0.024541228522912288f, 0.999694094596566000f, + -0.024732917918276223f, + 0.999689333741033640f, -0.024924606404281468f, 0.999684536129782140f, + -0.025116293973880186f, + 0.999679701762987930f, -0.025307980620024571f, 0.999674830640828740f, + -0.025499666335666853f, + 0.999669922763483760f, -0.025691351113759295f, 0.999664978131133310f, + -0.025883034947254198f, + 0.999659996743959220f, -0.026074717829103901f, 0.999654978602144690f, + -0.026266399752260760f, + 0.999649923705874240f, -0.026458080709677187f, 0.999644832055333610f, + -0.026649760694305618f, + 0.999639703650710200f, -0.026841439699098531f, 0.999634538492192300f, + -0.027033117717008431f, + 0.999629336579970110f, -0.027224794740987875f, 0.999624097914234570f, + -0.027416470763989436f, + 0.999618822495178640f, -0.027608145778965740f, 0.999613510322995950f, + -0.027799819778869445f, + 0.999608161397882110f, -0.027991492756653243f, 0.999602775720033530f, + -0.028183164705269874f, + 0.999597353289648380f, -0.028374835617672099f, 0.999591894106925950f, + -0.028566505486812728f, + 0.999586398172067070f, -0.028758174305644615f, 0.999580865485273700f, + -0.028949842067120635f, + 0.999575296046749220f, -0.029141508764193722f, 0.999569689856698580f, + -0.029333174389816835f, + 0.999564046915327740f, -0.029524838936942976f, 0.999558367222844300f, + -0.029716502398525191f, + 0.999552650779456990f, -0.029908164767516555f, 0.999546897585375960f, + -0.030099826036870198f, + 0.999541107640812940f, -0.030291486199539284f, 0.999535280945980540f, + -0.030483145248477009f, + 0.999529417501093140f, -0.030674803176636626f, 0.999523517306366350f, + -0.030866459976971412f, + 0.999517580362016990f, -0.031058115642434700f, 0.999511606668263440f, + -0.031249770165979861f, + 0.999505596225325310f, -0.031441423540560301f, 0.999499549033423640f, + -0.031633075759129478f, + 0.999493465092780590f, -0.031824726814640887f, 0.999487344403620080f, + -0.032016376700048060f, + 0.999481186966166950f, -0.032208025408304586f, 0.999474992780647780f, + -0.032399672932364086f, + 0.999468761847290050f, -0.032591319265180226f, 0.999462494166323160f, + -0.032782964399706724f, + 0.999456189737977340f, -0.032974608328897335f, 0.999449848562484530f, + -0.033166251045705857f, + 0.999443470640077770f, -0.033357892543086139f, 0.999437055970991530f, + -0.033549532813992068f, + 0.999430604555461730f, -0.033741171851377580f, 0.999424116393725640f, + -0.033932809648196664f, + 0.999417591486021720f, -0.034124446197403326f, 0.999411029832589780f, + -0.034316081491951651f, + 0.999404431433671300f, -0.034507715524795750f, 0.999397796289508640f, + -0.034699348288889799f, + 0.999391124400346050f, -0.034890979777188004f, 0.999384415766428560f, + -0.035082609982644619f, + 0.999377670388002850f, -0.035274238898213947f, 0.999370888265317170f, + -0.035465866516850353f, + 0.999364069398620550f, -0.035657492831508222f, 0.999357213788164000f, + -0.035849117835142018f, + 0.999350321434199440f, -0.036040741520706229f, 0.999343392336980220f, + -0.036232363881155395f, + 0.999336426496761240f, -0.036423984909444110f, 0.999329423913798420f, + -0.036615604598527030f, + 0.999322384588349540f, -0.036807222941358832f, 0.999315308520673070f, + -0.036998839930894263f, + 0.999308195711029470f, -0.037190455560088119f, 0.999301046159680070f, + -0.037382069821895229f, + 0.999293859866887790f, -0.037573682709270494f, 0.999286636832916740f, + -0.037765294215168860f, + 0.999279377058032710f, -0.037956904332545310f, 0.999272080542502610f, + -0.038148513054354891f, + 0.999264747286594420f, -0.038340120373552694f, 0.999257377290578060f, + -0.038531726283093870f, + 0.999249970554724420f, -0.038723330775933623f, 0.999242527079305830f, + -0.038914933845027193f, + 0.999235046864595850f, -0.039106535483329888f, 0.999227529910869610f, + -0.039298135683797059f, + 0.999219976218403530f, -0.039489734439384118f, 0.999212385787475290f, + -0.039681331743046527f, + 0.999204758618363890f, -0.039872927587739811f, 0.999197094711349880f, + -0.040064521966419520f, + 0.999189394066714920f, -0.040256114872041282f, 0.999181656684742350f, + -0.040447706297560782f, + 0.999173882565716380f, -0.040639296235933736f, 0.999166071709923000f, + -0.040830884680115948f, + 0.999158224117649430f, -0.041022471623063238f, 0.999150339789184110f, + -0.041214057057731519f, + 0.999142418724816910f, -0.041405640977076739f, 0.999134460924839150f, + -0.041597223374054894f, + 0.999126466389543390f, -0.041788804241622061f, 0.999118435119223490f, + -0.041980383572734356f, + 0.999110367114174890f, -0.042171961360347947f, 0.999102262374694130f, + -0.042363537597419072f, + 0.999094120901079070f, -0.042555112276904020f, 0.999085942693629270f, + -0.042746685391759132f, + 0.999077727752645360f, -0.042938256934940820f, 0.999069476078429330f, + -0.043129826899405546f, + 0.999061187671284600f, -0.043321395278109825f, 0.999052862531515930f, + -0.043512962064010237f, + 0.999044500659429290f, -0.043704527250063421f, 0.999036102055332330f, + -0.043896090829226068f, + 0.999027666719533690f, -0.044087652794454944f, 0.999019194652343460f, + -0.044279213138706849f, + 0.999010685854073380f, -0.044470771854938668f, 0.999002140325035980f, + -0.044662328936107325f, + 0.998993558065545680f, -0.044853884375169815f, 0.998984939075918010f, + -0.045045438165083197f, + 0.998976283356469820f, -0.045236990298804590f, 0.998967590907519300f, + -0.045428540769291155f, + 0.998958861729386080f, -0.045620089569500144f, 0.998950095822391250f, + -0.045811636692388844f, + 0.998941293186856870f, -0.046003182130914623f, 0.998932453823106690f, + -0.046194725878034908f, + 0.998923577731465780f, -0.046386267926707157f, 0.998914664912260440f, + -0.046577808269888943f, + 0.998905715365818290f, -0.046769346900537863f, 0.998896729092468410f, + -0.046960883811611592f, + 0.998887706092541290f, -0.047152418996067869f, 0.998878646366368690f, + -0.047343952446864478f, + 0.998869549914283560f, -0.047535484156959303f, 0.998860416736620520f, + -0.047727014119310254f, + 0.998851246833715180f, -0.047918542326875327f, 0.998842040205904840f, + -0.048110068772612591f, + 0.998832796853527990f, -0.048301593449480144f, 0.998823516776924490f, + -0.048493116350436176f, + 0.998814199976435390f, -0.048684637468438943f, 0.998804846452403420f, + -0.048876156796446760f, + 0.998795456205172410f, -0.049067674327418015f, 0.998786029235087640f, + -0.049259190054311140f, + 0.998776565542495610f, -0.049450703970084664f, 0.998767065127744380f, + -0.049642216067697156f, + 0.998757527991183340f, -0.049833726340107277f, 0.998747954133162860f, + -0.050025234780273729f, + 0.998738343554035230f, -0.050216741381155311f, 0.998728696254153720f, + -0.050408246135710856f, + 0.998719012233872940f, -0.050599749036899282f, 0.998709291493549030f, + -0.050791250077679581f, + 0.998699534033539280f, -0.050982749251010803f, 0.998689739854202620f, + -0.051174246549852080f, + 0.998679908955899090f, -0.051365741967162593f, 0.998670041338990070f, + -0.051557235495901611f, + 0.998660137003838490f, -0.051748727129028456f, 0.998650195950808280f, + -0.051940216859502536f, + 0.998640218180265270f, -0.052131704680283324f, 0.998630203692576050f, + -0.052323190584330347f, + 0.998620152488108870f, -0.052514674564603223f, 0.998610064567233340f, + -0.052706156614061632f, + 0.998599939930320370f, -0.052897636725665324f, 0.998589778577742230f, + -0.053089114892374133f, + 0.998579580509872500f, -0.053280591107147945f, 0.998569345727086110f, + -0.053472065362946727f, + 0.998559074229759310f, -0.053663537652730520f, 0.998548766018269920f, + -0.053855007969459440f, + 0.998538421092996730f, -0.054046476306093660f, 0.998528039454320230f, + -0.054237942655593452f, + 0.998517621102622210f, -0.054429407010919133f, 0.998507166038285490f, + -0.054620869365031105f, + 0.998496674261694640f, -0.054812329710889854f, 0.998486145773235360f, + -0.055003788041455920f, + 0.998475580573294770f, -0.055195244349689934f, 0.998464978662261250f, + -0.055386698628552597f, + 0.998454340040524800f, -0.055578150871004678f, 0.998443664708476340f, + -0.055769601070007030f, + 0.998432952666508440f, -0.055961049218520569f, 0.998422203915015020f, + -0.056152495309506292f, + 0.998411418454391300f, -0.056343939335925290f, 0.998400596285033640f, + -0.056535381290738700f, + 0.998389737407340160f, -0.056726821166907748f, 0.998378841821709990f, + -0.056918258957393740f, + 0.998367909528543820f, -0.057109694655158062f, 0.998356940528243420f, + -0.057301128253162158f, + 0.998345934821212370f, -0.057492559744367566f, 0.998334892407855000f, + -0.057683989121735904f, + 0.998323813288577560f, -0.057875416378228857f, 0.998312697463787260f, + -0.058066841506808194f, + 0.998301544933892890f, -0.058258264500435752f, 0.998290355699304350f, + -0.058449685352073476f, + 0.998279129760433200f, -0.058641104054683341f, 0.998267867117692110f, + -0.058832520601227435f, + 0.998256567771495180f, -0.059023934984667931f, 0.998245231722257880f, + -0.059215347197967061f, + 0.998233858970396850f, -0.059406757234087150f, 0.998222449516330550f, + -0.059598165085990591f, + 0.998211003360478190f, -0.059789570746639868f, 0.998199520503260660f, + -0.059980974208997548f, + 0.998188000945100300f, -0.060172375466026259f, 0.998176444686420530f, + -0.060363774510688743f, + 0.998164851727646240f, -0.060555171335947788f, 0.998153222069203760f, + -0.060746565934766288f, + 0.998141555711520520f, -0.060937958300107203f, 0.998129852655025630f, + -0.061129348424933588f, + 0.998118112900149180f, -0.061320736302208578f, 0.998106336447323050f, + -0.061512121924895378f, + 0.998094523296980010f, -0.061703505285957298f, 0.998082673449554590f, + -0.061894886378357716f, + 0.998070786905482340f, -0.062086265195060088f, 0.998058863665200250f, + -0.062277641729027972f, + 0.998046903729146840f, -0.062469015973224996f, 0.998034907097761770f, + -0.062660387920614874f, + 0.998022873771486240f, -0.062851757564161406f, 0.998010803750762450f, + -0.063043124896828492f, + 0.997998697036034390f, -0.063234489911580066f, 0.997986553627747020f, + -0.063425852601380228f, + 0.997974373526346990f, -0.063617212959193106f, 0.997962156732281950f, + -0.063808570977982898f, + 0.997949903246001190f, -0.063999926650713940f, 0.997937613067955250f, + -0.064191279970350637f, + 0.997925286198596000f, -0.064382630929857465f, 0.997912922638376610f, + -0.064573979522198982f, + 0.997900522387751620f, -0.064765325740339885f, 0.997888085447177110f, + -0.064956669577244872f, + 0.997875611817110150f, -0.065148011025878833f, 0.997863101498009500f, + -0.065339350079206632f, + 0.997850554490335110f, -0.065530686730193327f, 0.997837970794548280f, + -0.065722020971803990f, + 0.997825350411111640f, -0.065913352797003805f, 0.997812693340489280f, + -0.066104682198758077f, + 0.997799999583146470f, -0.066296009170032130f, 0.997787269139549960f, + -0.066487333703791451f, + 0.997774502010167820f, -0.066678655793001557f, 0.997761698195469560f, + -0.066869975430628115f, + 0.997748857695925690f, -0.067061292609636822f, 0.997735980512008620f, + -0.067252607322993499f, + 0.997723066644191640f, -0.067443919563664051f, 0.997710116092949570f, + -0.067635229324614479f, + 0.997697128858758500f, -0.067826536598810869f, 0.997684104942096030f, + -0.068017841379219388f, + 0.997671044343441000f, -0.068209143658806329f, 0.997657947063273710f, + -0.068400443430538013f, + 0.997644813102075420f, -0.068591740687380942f, 0.997631642460329320f, + -0.068783035422301630f, + 0.997618435138519550f, -0.068974327628266746f, 0.997605191137131640f, + -0.069165617298242985f, + 0.997591910456652630f, -0.069356904425197208f, 0.997578593097570800f, + -0.069548189002096306f, + 0.997565239060375750f, -0.069739471021907307f, 0.997551848345558430f, + -0.069930750477597309f, + 0.997538420953611340f, -0.070122027362133521f, 0.997524956885027960f, + -0.070313301668483250f, + 0.997511456140303450f, -0.070504573389613856f, 0.997497918719934210f, + -0.070695842518492855f, + 0.997484344624417930f, -0.070887109048087801f, 0.997470733854253670f, + -0.071078372971366405f, + 0.997457086409941910f, -0.071269634281296401f, 0.997443402291984360f, + -0.071460892970845680f, + 0.997429681500884180f, -0.071652149032982212f, 0.997415924037145960f, + -0.071843402460674027f, + 0.997402129901275300f, -0.072034653246889332f, 0.997388299093779460f, + -0.072225901384596322f, + 0.997374431615167150f, -0.072417146866763413f, 0.997360527465947940f, + -0.072608389686358993f, + 0.997346586646633230f, -0.072799629836351673f, 0.997332609157735470f, + -0.072990867309710036f, + 0.997318594999768600f, -0.073182102099402888f, 0.997304544173247990f, + -0.073373334198399032f, + 0.997290456678690210f, -0.073564563599667426f, 0.997276332516613180f, + -0.073755790296177098f, + 0.997262171687536170f, -0.073947014280897200f, 0.997247974191979860f, + -0.074138235546796979f, + 0.997233740030466280f, -0.074329454086845756f, 0.997219469203518670f, + -0.074520669894013000f, + 0.997205161711661850f, -0.074711882961268211f, 0.997190817555421940f, + -0.074903093281581082f, + 0.997176436735326190f, -0.075094300847921305f, 0.997162019251903290f, + -0.075285505653258769f, + 0.997147565105683480f, -0.075476707690563388f, 0.997133074297198110f, + -0.075667906952805231f, + 0.997118546826979980f, -0.075859103432954447f, 0.997103982695563330f, + -0.076050297123981259f, + 0.997089381903483400f, -0.076241488018856066f, 0.997074744451277310f, + -0.076432676110549283f, + 0.997060070339482960f, -0.076623861392031492f, 0.997045359568640040f, + -0.076815043856273343f, + 0.997030612139289450f, -0.077006223496245640f, 0.997015828051973310f, + -0.077197400304919200f, + 0.997001007307235290f, -0.077388574275265049f, 0.996986149905620180f, + -0.077579745400254224f, + 0.996971255847674320f, -0.077770913672857947f, 0.996956325133945280f, + -0.077962079086047492f, + 0.996941357764982160f, -0.078153241632794232f, 0.996926353741335090f, + -0.078344401306069705f, + 0.996911313063555740f, -0.078535558098845479f, 0.996896235732197210f, + -0.078726712004093299f, + 0.996881121747813850f, -0.078917863014784942f, 0.996865971110961310f, + -0.079109011123892375f, + 0.996850783822196610f, -0.079300156324387597f, 0.996835559882078170f, + -0.079491298609242769f, + 0.996820299291165670f, -0.079682437971430126f, 0.996805002050020430f, + -0.079873574403921996f, + 0.996789668159204560f, -0.080064707899690890f, 0.996774297619282050f, + -0.080255838451709319f, + 0.996758890430818000f, -0.080446966052950014f, 0.996743446594378860f, + -0.080638090696385709f, + 0.996727966110532490f, -0.080829212374989329f, 0.996712448979848010f, + -0.081020331081733857f, + 0.996696895202896060f, -0.081211446809592441f, 0.996681304780248300f, + -0.081402559551538245f, + 0.996665677712478160f, -0.081593669300544652f, 0.996650014000160070f, + -0.081784776049585076f, + 0.996634313643869900f, -0.081975879791633066f, 0.996618576644185070f, + -0.082166980519662314f, + 0.996602803001684130f, -0.082358078226646536f, 0.996586992716946950f, + -0.082549172905559673f, + 0.996571145790554840f, -0.082740264549375692f, 0.996555262223090540f, + -0.082931353151068699f, + 0.996539342015137940f, -0.083122438703612911f, 0.996523385167282450f, + -0.083313521199982685f, + 0.996507391680110820f, -0.083504600633152432f, 0.996491361554210920f, + -0.083695676996096716f, + 0.996475294790172160f, -0.083886750281790226f, 0.996459191388585410f, + -0.084077820483207694f, + 0.996443051350042630f, -0.084268887593324071f, 0.996426874675137240f, + -0.084459951605114325f, + 0.996410661364464100f, -0.084651012511553617f, 0.996394411418619290f, + -0.084842070305617134f, + 0.996378124838200210f, -0.085033124980280275f, 0.996361801623805720f, + -0.085224176528518478f, + 0.996345441776035900f, -0.085415224943307333f, 0.996329045295492380f, + -0.085606270217622529f, + 0.996312612182778000f, -0.085797312344439894f, 0.996296142438496850f, + -0.085988351316735337f, + 0.996279636063254650f, -0.086179387127484894f, 0.996263093057658140f, + -0.086370419769664752f, + 0.996246513422315520f, -0.086561449236251170f, 0.996229897157836500f, + -0.086752475520220543f, + 0.996213244264832040f, -0.086943498614549378f, 0.996196554743914220f, + -0.087134518512214307f, + 0.996179828595696980f, -0.087325535206192059f, 0.996163065820794950f, + -0.087516548689459531f, + 0.996146266419824620f, -0.087707558954993659f, 0.996129430393403740f, + -0.087898565995771588f, + 0.996112557742151130f, -0.088089569804770507f, 0.996095648466687300f, + -0.088280570374967740f, + 0.996078702567633980f, -0.088471567699340767f, 0.996061720045614000f, + -0.088662561770867149f, + 0.996044700901251970f, -0.088853552582524600f, 0.996027645135173610f, + -0.089044540127290892f, + 0.996010552748005870f, -0.089235524398144014f, 0.995993423740377360f, + -0.089426505388061961f, + 0.995976258112917790f, -0.089617483090022959f, 0.995959055866258320f, + -0.089808457497005278f, + 0.995941817001031350f, -0.089999428601987341f, 0.995924541517870800f, + -0.090190396397947695f, + 0.995907229417411720f, -0.090381360877864983f, 0.995889880700290720f, + -0.090572322034717989f, + 0.995872495367145730f, -0.090763279861485621f, 0.995855073418615790f, + -0.090954234351146926f, + 0.995837614855341610f, -0.091145185496681005f, 0.995820119677964910f, + -0.091336133291067184f, + 0.995802587887129160f, -0.091527077727284828f, 0.995785019483478750f, + -0.091718018798313455f, + 0.995767414467659820f, -0.091908956497132724f, 0.995749772840319510f, + -0.092099890816722388f, + 0.995732094602106430f, -0.092290821750062355f, 0.995714379753670610f, + -0.092481749290132600f, + 0.995696628295663520f, -0.092672673429913310f, 0.995678840228737540f, + -0.092863594162384724f, + 0.995661015553546910f, -0.093054511480527249f, 0.995643154270746900f, + -0.093245425377321375f, + 0.995625256380994310f, -0.093436335845747787f, 0.995607321884947050f, + -0.093627242878787195f, + 0.995589350783264600f, -0.093818146469420549f, 0.995571343076607770f, + -0.094009046610628838f, + 0.995553298765638470f, -0.094199943295393204f, 0.995535217851020390f, + -0.094390836516694943f, + 0.995517100333418110f, -0.094581726267515445f, 0.995498946213497770f, + -0.094772612540836243f, + 0.995480755491926940f, -0.094963495329638992f, 0.995462528169374420f, + -0.095154374626905486f, + 0.995444264246510340f, -0.095345250425617617f, 0.995425963724006160f, + -0.095536122718757471f, + 0.995407626602534900f, -0.095726991499307162f, 0.995389252882770690f, + -0.095917856760249040f, + 0.995370842565388990f, -0.096108718494565509f, 0.995352395651066810f, + -0.096299576695239128f, + 0.995333912140482280f, -0.096490431355252593f, 0.995315392034315070f, + -0.096681282467588725f, + 0.995296835333246090f, -0.096872130025230471f, 0.995278242037957670f, + -0.097062974021160917f, + 0.995259612149133390f, -0.097253814448363271f, 0.995240945667458130f, + -0.097444651299820870f, + 0.995222242593618360f, -0.097635484568517200f, 0.995203502928301510f, + -0.097826314247435861f, + 0.995184726672196930f, -0.098017140329560604f, 0.995165913825994620f, + -0.098207962807875276f, + 0.995147064390386470f, -0.098398781675363881f, 0.995128178366065490f, + -0.098589596925010584f, + 0.995109255753726110f, -0.098780408549799623f, 0.995090296554064000f, + -0.098971216542715429f, + 0.995071300767776170f, -0.099162020896742503f, 0.995052268395561050f, + -0.099352821604865540f, + 0.995033199438118630f, -0.099543618660069319f, 0.995014093896149700f, + -0.099734412055338825f, + 0.994994951770357020f, -0.099925201783659073f, 0.994975773061444140f, + -0.100115987838015310f, + 0.994956557770116380f, -0.100306770211392860f, 0.994937305897080070f, + -0.100497548896777200f, + 0.994918017443043200f, -0.100688323887153960f, 0.994898692408714870f, + -0.100879095175508860f, + 0.994879330794805620f, -0.101069862754827820f, 0.994859932602027320f, + -0.101260626618096830f, + 0.994840497831093180f, -0.101451386758302080f, 0.994821026482717860f, + -0.101642143168429830f, + 0.994801518557617110f, -0.101832895841466530f, 0.994781974056508260f, + -0.102023644770398740f, + 0.994762392980109930f, -0.102214389948213210f, 0.994742775329142010f, + -0.102405131367896720f, + 0.994723121104325700f, -0.102595869022436280f, 0.994703430306383860f, + -0.102786602904819040f, + 0.994683702936040250f, -0.102977333008032220f, 0.994663938994020390f, + -0.103168059325063230f, + 0.994644138481050710f, -0.103358781848899610f, 0.994624301397859400f, + -0.103549500572529070f, + 0.994604427745175660f, -0.103740215488939370f, 0.994584517523730340f, + -0.103930926591118510f, + 0.994564570734255420f, -0.104121633872054590f, 0.994544587377484300f, + -0.104312337324735800f, + 0.994524567454151740f, -0.104503036942150570f, 0.994504510964993700f, + -0.104693732717287390f, + 0.994484417910747600f, -0.104884424643134970f, 0.994464288292152390f, + -0.105075112712682040f, + 0.994444122109948040f, -0.105265796918917600f, 0.994423919364875950f, + -0.105456477254830710f, + 0.994403680057679100f, -0.105647153713410620f, 0.994383404189101430f, + -0.105837826287646670f, + 0.994363091759888570f, -0.106028494970528410f, 0.994342742770787270f, + -0.106219159755045480f, + 0.994322357222545810f, -0.106409820634187680f, 0.994301935115913580f, + -0.106600477600944960f, + 0.994281476451641550f, -0.106791130648307390f, 0.994260981230481790f, + -0.106981779769265230f, + 0.994240449453187900f, -0.107172424956808840f, 0.994219881120514960f, + -0.107363066203928760f, + 0.994199276233218910f, -0.107553703503615620f, 0.994178634792057590f, + -0.107744336848860280f, + 0.994157956797789730f, -0.107934966232653650f, 0.994137242251175720f, + -0.108125591647986870f, + 0.994116491152977070f, -0.108316213087851170f, 0.994095703503956930f, + -0.108506830545237920f, + 0.994074879304879370f, -0.108697444013138720f, 0.994054018556510210f, + -0.108888053484545190f, + 0.994033121259616400f, -0.109078658952449240f, 0.994012187414966220f, + -0.109269260409842780f, + 0.993991217023329380f, -0.109459857849717980f, 0.993970210085476920f, + -0.109650451265067100f, + 0.993949166602181130f, -0.109841040648882600f, 0.993928086574215830f, + -0.110031625994157000f, + 0.993906970002356060f, -0.110222207293883060f, 0.993885816887378090f, + -0.110412784541053630f, + 0.993864627230059750f, -0.110603357728661730f, 0.993843401031180180f, + -0.110793926849700560f, + 0.993822138291519660f, -0.110984491897163390f, 0.993800839011860120f, + -0.111175052864043720f, + 0.993779503192984580f, -0.111365609743335160f, 0.993758130835677430f, + -0.111556162528031480f, + 0.993736721940724600f, -0.111746711211126590f, 0.993715276508913230f, + -0.111937255785614570f, + 0.993693794541031790f, -0.112127796244489640f, 0.993672276037870010f, + -0.112318332580746170f, + 0.993650721000219120f, -0.112508864787378690f, 0.993629129428871720f, + -0.112699392857381860f, + 0.993607501324621610f, -0.112889916783750520f, 0.993585836688263950f, + -0.113080436559479620f, + 0.993564135520595300f, -0.113270952177564350f, 0.993542397822413600f, + -0.113461463630999950f, + 0.993520623594518090f, -0.113651970912781870f, 0.993498812837709360f, + -0.113842474015905710f, + 0.993476965552789190f, -0.114032972933367200f, 0.993455081740560960f, + -0.114223467658162260f, + 0.993433161401829360f, -0.114413958183286920f, 0.993411204537400060f, + -0.114604444501737420f, + 0.993389211148080650f, -0.114794926606510080f, 0.993367181234679600f, + -0.114985404490601460f, + 0.993345114798006910f, -0.115175878147008190f, 0.993323011838873950f, + -0.115366347568727140f, + 0.993300872358093280f, -0.115556812748755260f, 0.993278696356479030f, + -0.115747273680089720f, + 0.993256483834846440f, -0.115937730355727780f, 0.993234234794012290f, + -0.116128182768666930f, + 0.993211949234794500f, -0.116318630911904750f, 0.993189627158012620f, + -0.116509074778439040f, + 0.993167268564487230f, -0.116699514361267690f, 0.993144873455040430f, + -0.116889949653388780f, + 0.993122441830495580f, -0.117080380647800590f, 0.993099973691677570f, + -0.117270807337501460f, + 0.993077469039412300f, -0.117461229715489990f, 0.993054927874527320f, + -0.117651647774764860f, + 0.993032350197851410f, -0.117842061508324980f, 0.993009736010214580f, + -0.118032470909169340f, + 0.992987085312448390f, -0.118222875970297170f, 0.992964398105385610f, + -0.118413276684707790f, + 0.992941674389860470f, -0.118603673045400720f, 0.992918914166708300f, + -0.118794065045375640f, + 0.992896117436765980f, -0.118984452677632340f, 0.992873284200871730f, + -0.119174835935170880f, + 0.992850414459865100f, -0.119365214810991350f, 0.992827508214586760f, + -0.119555589298094110f, + 0.992804565465879140f, -0.119745959389479600f, 0.992781586214585570f, + -0.119936325078148470f, + 0.992758570461551140f, -0.120126686357101500f, 0.992735518207621850f, + -0.120317043219339680f, + 0.992712429453645460f, -0.120507395657864130f, 0.992689304200470750f, + -0.120697743665676110f, + 0.992666142448948020f, -0.120888087235777080f, 0.992642944199928820f, + -0.121078426361168640f, + 0.992619709454266140f, -0.121268761034852600f, 0.992596438212814290f, + -0.121459091249830840f, + 0.992573130476428810f, -0.121649416999105530f, 0.992549786245966680f, + -0.121839738275678890f, + 0.992526405522286100f, -0.122030055072553360f, 0.992502988306246950f, + -0.122220367382731540f, + 0.992479534598709970f, -0.122410675199216200f, 0.992456044400537700f, + -0.122600978515010240f, + 0.992432517712593660f, -0.122791277323116770f, 0.992408954535742850f, + -0.122981571616539050f, + 0.992385354870851670f, -0.123171861388280480f, 0.992361718718787870f, + -0.123362146631344680f, + 0.992338046080420420f, -0.123552427338735370f, 0.992314336956619640f, + -0.123742703503456510f, + 0.992290591348257370f, -0.123932975118512160f, 0.992266809256206580f, + -0.124123242176906600f, + 0.992242990681341700f, -0.124313504671644230f, 0.992219135624538450f, + -0.124503762595729660f, + 0.992195244086673920f, -0.124694015942167640f, 0.992171316068626520f, + -0.124884264703963130f, + 0.992147351571276090f, -0.125074508874121170f, 0.992123350595503720f, + -0.125264748445647060f, + 0.992099313142191800f, -0.125454983411546230f, 0.992075239212224070f, + -0.125645213764824290f, + 0.992051128806485720f, -0.125835439498487000f, 0.992026981925863360f, + -0.126025660605540320f, + 0.992002798571244520f, -0.126215877078990350f, 0.991978578743518580f, + -0.126406088911843380f, + 0.991954322443575950f, -0.126596296097105850f, 0.991930029672308480f, + -0.126786498627784410f, + 0.991905700430609330f, -0.126976696496885870f, 0.991881334719373010f, + -0.127166889697417160f, + 0.991856932539495470f, -0.127357078222385400f, 0.991832493891873780f, + -0.127547262064797970f, + 0.991808018777406430f, -0.127737441217662310f, 0.991783507196993490f, + -0.127927615673986080f, + 0.991758959151536110f, -0.128117785426777130f, 0.991734374641936810f, + -0.128307950469043420f, + 0.991709753669099530f, -0.128498110793793170f, 0.991685096233929420f, + -0.128688266394034690f, + 0.991660402337333210f, -0.128878417262776550f, 0.991635671980218740f, + -0.129068563393027410f, + 0.991610905163495370f, -0.129258704777796140f, 0.991586101888073500f, + -0.129448841410091780f, + 0.991561262154865290f, -0.129638973282923560f, 0.991536385964783880f, + -0.129829100389300930f, + 0.991511473318743900f, -0.130019222722233350f, 0.991486524217661480f, + -0.130209340274730630f, + 0.991461538662453790f, -0.130399453039802690f, 0.991436516654039420f, + -0.130589561010459650f, + 0.991411458193338540f, -0.130779664179711710f, 0.991386363281272280f, + -0.130969762540569380f, + 0.991361231918763460f, -0.131159856086043270f, 0.991336064106736140f, + -0.131349944809144190f, + 0.991310859846115440f, -0.131540028702883120f, 0.991285619137828200f, + -0.131730107760271160f, + 0.991260341982802440f, -0.131920181974319790f, 0.991235028381967420f, + -0.132110251338040360f, + 0.991209678336254060f, -0.132300315844444650f, 0.991184291846594180f, + -0.132490375486544550f, + 0.991158868913921350f, -0.132680430257352070f, 0.991133409539170170f, + -0.132870480149879430f, + 0.991107913723276890f, -0.133060525157139060f, 0.991082381467178640f, + -0.133250565272143570f, + 0.991056812771814340f, -0.133440600487905680f, 0.991031207638124130f, + -0.133630630797438340f, + 0.991005566067049370f, -0.133820656193754720f, 0.990979888059532740f, + -0.134010676669868130f, + 0.990954173616518500f, -0.134200692218792020f, 0.990928422738951990f, + -0.134390702833540070f, + 0.990902635427780010f, -0.134580708507126170f, 0.990876811683950700f, + -0.134770709232564350f, + 0.990850951508413620f, -0.134960705002868750f, 0.990825054902119470f, + -0.135150695811053850f, + 0.990799121866020370f, -0.135340681650134210f, 0.990773152401069780f, + -0.135530662513124590f, + 0.990747146508222710f, -0.135720638393039910f, 0.990721104188435180f, + -0.135910609282895330f, + 0.990695025442664630f, -0.136100575175706200f, 0.990668910271870100f, + -0.136290536064487960f, + 0.990642758677011570f, -0.136480491942256280f, 0.990616570659050620f, + -0.136670442802027090f, + 0.990590346218950150f, -0.136860388636816380f, 0.990564085357674370f, + -0.137050329439640410f, + 0.990537788076188750f, -0.137240265203515590f, 0.990511454375460290f, + -0.137430195921458550f, + 0.990485084256457090f, -0.137620121586486040f, 0.990458677720148620f, + -0.137810042191615080f, + 0.990432234767505970f, -0.137999957729862790f, 0.990405755399501260f, + -0.138189868194246560f, + 0.990379239617108160f, -0.138379773577783890f, 0.990352687421301450f, + -0.138569673873492500f, + 0.990326098813057330f, -0.138759569074390350f, 0.990299473793353590f, + -0.138949459173495490f, + 0.990272812363169110f, -0.139139344163826200f, 0.990246114523483990f, + -0.139329224038400980f, + 0.990219380275280000f, -0.139519098790238490f, 0.990192609619540030f, + -0.139708968412357550f, + 0.990165802557248400f, -0.139898832897777210f, 0.990138959089390650f, + -0.140088692239516670f, + 0.990112079216953770f, -0.140278546430595420f, 0.990085162940925970f, + -0.140468395464033000f, + 0.990058210262297120f, -0.140658239332849210f, 0.990031221182058000f, + -0.140848078030064080f, + 0.990004195701200910f, -0.141037911548697710f, 0.989977133820719610f, + -0.141227739881770510f, + 0.989950035541608990f, -0.141417563022303020f, 0.989922900864865450f, + -0.141607380963316020f, + 0.989895729791486660f, -0.141797193697830390f, 0.989868522322471580f, + -0.141987001218867290f, + 0.989841278458820530f, -0.142176803519448030f, 0.989813998201535260f, + -0.142366600592594180f, + 0.989786681551618640f, -0.142556392431327340f, 0.989759328510075200f, + -0.142746179028669460f, + 0.989731939077910570f, -0.142935960377642670f, 0.989704513256131850f, + -0.143125736471269190f, + 0.989677051045747210f, -0.143315507302571500f, 0.989649552447766530f, + -0.143505272864572290f, + 0.989622017463200890f, -0.143695033150294470f, 0.989594446093062460f, + -0.143884788152760980f, + 0.989566838338365120f, -0.144074537864995160f, 0.989539194200123930f, + -0.144264282280020440f, + 0.989511513679355190f, -0.144454021390860470f, 0.989483796777076760f, + -0.144643755190539040f, + 0.989456043494307710f, -0.144833483672080210f, 0.989428253832068230f, + -0.145023206828508220f, + 0.989400427791380380f, -0.145212924652847460f, 0.989372565373267010f, + -0.145402637138122570f, + 0.989344666578752640f, -0.145592344277358340f, 0.989316731408863000f, + -0.145782046063579860f, + 0.989288759864625170f, -0.145971742489812210f, 0.989260751947067640f, + -0.146161433549080900f, + 0.989232707657220050f, -0.146351119234411460f, 0.989204626996113780f, + -0.146540799538829760f, + 0.989176509964781010f, -0.146730474455361750f, 0.989148356564255590f, + -0.146920143977033620f, + 0.989120166795572690f, -0.147109808096871820f, 0.989091940659768800f, + -0.147299466807902850f, + 0.989063678157881540f, -0.147489120103153570f, 0.989035379290950310f, + -0.147678767975650970f, + 0.989007044060015270f, -0.147868410418422220f, 0.988978672466118480f, + -0.148058047424494720f, + 0.988950264510302990f, -0.148247678986896030f, 0.988921820193613190f, + -0.148437305098653970f, + 0.988893339517095130f, -0.148626925752796540f, 0.988864822481795640f, + -0.148816540942351920f, + 0.988836269088763540f, -0.149006150660348450f, 0.988807679339048450f, + -0.149195754899814820f, + 0.988779053233701520f, -0.149385353653779720f, 0.988750390773775360f, + -0.149574946915272230f, + 0.988721691960323780f, -0.149764534677321510f, 0.988692956794401940f, + -0.149954116932956960f, + 0.988664185277066230f, -0.150143693675208190f, 0.988635377409374790f, + -0.150333264897105000f, + 0.988606533192386450f, -0.150522830591677400f, 0.988577652627162020f, + -0.150712390751955610f, + 0.988548735714763200f, -0.150901945370970040f, 0.988519782456253270f, + -0.151091494441751300f, + 0.988490792852696590f, -0.151281037957330220f, 0.988461766905159300f, + -0.151470575910737810f, + 0.988432704614708340f, -0.151660108295005310f, 0.988403605982412390f, + -0.151849635103164180f, + 0.988374471009341280f, -0.152039156328246050f, 0.988345299696566150f, + -0.152228671963282740f, + 0.988316092045159690f, -0.152418182001306330f, 0.988286848056195820f, + -0.152607686435349050f, + 0.988257567730749460f, -0.152797185258443440f, 0.988228251069897420f, + -0.152986678463622040f, + 0.988198898074717610f, -0.153176166043917840f, 0.988169508746289060f, + -0.153365647992363880f, + 0.988140083085692570f, -0.153555124301993450f, 0.988110621094009820f, + -0.153744594965840030f, + 0.988081122772324070f, -0.153934059976937350f, 0.988051588121720110f, + -0.154123519328319360f, + 0.988022017143283530f, -0.154312973013020100f, 0.987992409838101880f, + -0.154502421024073940f, + 0.987962766207263420f, -0.154691863354515430f, 0.987933086251858380f, + -0.154881299997379320f, + 0.987903369972977790f, -0.155070730945700510f, 0.987873617371714200f, + -0.155260156192514240f, + 0.987843828449161740f, -0.155449575730855850f, 0.987814003206415550f, + -0.155638989553760900f, + 0.987784141644572180f, -0.155828397654265230f, 0.987754243764729530f, + -0.156017800025404800f, + 0.987724309567986960f, -0.156207196660215900f, 0.987694339055445130f, + -0.156396587551734880f, + 0.987664332228205710f, -0.156585972692998430f, 0.987634289087372160f, + -0.156775352077043350f, + 0.987604209634049160f, -0.156964725696906780f, 0.987574093869342360f, + -0.157154093545625900f, + 0.987543941794359230f, -0.157343455616238250f, 0.987513753410208420f, + -0.157532811901781530f, + 0.987483528717999710f, -0.157722162395293630f, 0.987453267718844560f, + -0.157911507089812660f, + 0.987422970413855410f, -0.158100845978376980f, 0.987392636804146240f, + -0.158290179054025180f, + 0.987362266890832400f, -0.158479506309795960f, 0.987331860675030430f, + -0.158668827738728310f, + 0.987301418157858430f, -0.158858143333861450f, 0.987270939340435420f, + -0.159047453088234760f, + 0.987240424223882250f, -0.159236756994887850f, 0.987209872809320820f, + -0.159426055046860580f, + 0.987179285097874340f, -0.159615347237193060f, 0.987148661090667570f, + -0.159804633558925440f, + 0.987118000788826280f, -0.159993914005098270f, 0.987087304193477900f, + -0.160183188568752220f, + 0.987056571305750970f, -0.160372457242928280f, 0.987025802126775600f, + -0.160561720020667490f, + 0.986994996657682980f, -0.160750976895011220f, 0.986964154899605650f, + -0.160940227859001080f, + 0.986933276853677710f, -0.161129472905678810f, 0.986902362521034470f, + -0.161318712028086400f, + 0.986871411902812470f, -0.161507945219266120f, 0.986840425000149680f, + -0.161697172472260400f, + 0.986809401814185530f, -0.161886393780111830f, 0.986778342346060430f, + -0.162075609135863330f, + 0.986747246596916590f, -0.162264818532558000f, 0.986716114567897100f, + -0.162454021963239190f, + 0.986684946260146690f, -0.162643219420950310f, 0.986653741674811350f, + -0.162832410898735210f, + 0.986622500813038480f, -0.163021596389637840f, 0.986591223675976400f, + -0.163210775886702380f, + 0.986559910264775410f, -0.163399949382973230f, 0.986528560580586690f, + -0.163589116871495020f, + 0.986497174624562880f, -0.163778278345312670f, 0.986465752397857940f, + -0.163967433797471170f, + 0.986434293901627180f, -0.164156583221015810f, 0.986402799137027220f, + -0.164345726608992190f, + 0.986371268105216030f, -0.164534863954446000f, 0.986339700807353000f, + -0.164723995250423170f, + 0.986308097244598670f, -0.164913120489969890f, 0.986276457418115090f, + -0.165102239666132660f, + 0.986244781329065460f, -0.165291352771958000f, 0.986213068978614490f, + -0.165480459800492780f, + 0.986181320367928270f, -0.165669560744784120f, 0.986149535498173860f, + -0.165858655597879300f, + 0.986117714370520090f, -0.166047744352825790f, 0.986085856986136820f, + -0.166236827002671420f, + 0.986053963346195440f, -0.166425903540464100f, 0.986022033451868560f, + -0.166614973959252090f, + 0.985990067304330140f, -0.166804038252083730f, 0.985958064904755460f, + -0.166993096412007710f, + 0.985926026254321130f, -0.167182148432072940f, 0.985893951354205210f, + -0.167371194305328430f, + 0.985861840205586980f, -0.167560234024823560f, 0.985829692809647050f, + -0.167749267583607890f, + 0.985797509167567480f, -0.167938294974731170f, 0.985765289280531310f, + -0.168127316191243410f, + 0.985733033149723490f, -0.168316331226194830f, 0.985700740776329850f, + -0.168505340072635900f, + 0.985668412161537550f, -0.168694342723617330f, 0.985636047306535420f, + -0.168883339172189980f, + 0.985603646212513400f, -0.169072329411405010f, 0.985571208880662740f, + -0.169261313434313830f, + 0.985538735312176060f, -0.169450291233967960f, 0.985506225508247290f, + -0.169639262803419290f, + 0.985473679470071810f, -0.169828228135719850f, 0.985441097198846210f, + -0.170017187223921950f, + 0.985408478695768420f, -0.170206140061078070f, 0.985375823962037710f, + -0.170395086640240940f, + 0.985343132998854790f, -0.170584026954463590f, 0.985310405807421570f, + -0.170772960996799230f, + 0.985277642388941220f, -0.170961888760301220f, 0.985244842744618540f, + -0.171150810238023280f, + 0.985212006875659350f, -0.171339725423019310f, 0.985179134783271130f, + -0.171528634308343420f, + 0.985146226468662230f, -0.171717536887049970f, 0.985113281933042710f, + -0.171906433152193530f, + 0.985080301177623800f, -0.172095323096829010f, 0.985047284203618200f, + -0.172284206714011370f, + 0.985014231012239840f, -0.172473083996795950f, 0.984981141604703960f, + -0.172661954938238270f, + 0.984948015982227030f, -0.172850819531394080f, 0.984914854146027200f, + -0.173039677769319360f, + 0.984881656097323700f, -0.173228529645070320f, 0.984848421837337010f, + -0.173417375151703470f, + 0.984815151367289140f, -0.173606214282275410f, 0.984781844688403350f, + -0.173795047029843160f, + 0.984748501801904210f, -0.173983873387463820f, 0.984715122709017620f, + -0.174172693348194820f, + 0.984681707410970940f, -0.174361506905093750f, 0.984648255908992630f, + -0.174550314051218510f, + 0.984614768204312600f, -0.174739114779627200f, 0.984581244298162180f, + -0.174927909083378160f, + 0.984547684191773960f, -0.175116696955529920f, 0.984514087886381840f, + -0.175305478389141320f, + 0.984480455383220930f, -0.175494253377271430f, 0.984446786683527920f, + -0.175683021912979490f, + 0.984413081788540700f, -0.175871783989325040f, 0.984379340699498510f, + -0.176060539599367820f, + 0.984345563417641900f, -0.176249288736167880f, 0.984311749944212780f, + -0.176438031392785410f, + 0.984277900280454370f, -0.176626767562280880f, 0.984244014427611110f, + -0.176815497237715000f, + 0.984210092386929030f, -0.177004220412148750f, 0.984176134159655320f, + -0.177192937078643280f, + 0.984142139747038570f, -0.177381647230260040f, 0.984108109150328540f, + -0.177570350860060710f, + 0.984074042370776450f, -0.177759047961107170f, 0.984039939409634970f, + -0.177947738526461560f, + 0.984005800268157870f, -0.178136422549186300f, 0.983971624947600270f, + -0.178325100022344000f, + 0.983937413449218920f, -0.178513770938997510f, 0.983903165774271500f, + -0.178702435292209970f, + 0.983868881924017220f, -0.178891093075044720f, 0.983834561899716630f, + -0.179079744280565390f, + 0.983800205702631600f, -0.179268388901835750f, 0.983765813334025240f, + -0.179457026931919890f, + 0.983731384795162090f, -0.179645658363882160f, 0.983696920087308140f, + -0.179834283190787090f, + 0.983662419211730250f, -0.180022901405699510f, 0.983627882169697210f, + -0.180211513001684450f, + 0.983593308962478650f, -0.180400117971807240f, 0.983558699591345900f, + -0.180588716309133340f, + 0.983524054057571260f, -0.180777308006728590f, 0.983489372362428730f, + -0.180965893057658980f, + 0.983454654507193270f, -0.181154471454990810f, 0.983419900493141540f, + -0.181343043191790540f, + 0.983385110321551180f, -0.181531608261124970f, 0.983350283993701500f, + -0.181720166656061110f, + 0.983315421510872810f, -0.181908718369666160f, 0.983280522874346970f, + -0.182097263395007650f, + 0.983245588085407070f, -0.182285801725153300f, 0.983210617145337640f, + -0.182474333353171120f, + 0.983175610055424420f, -0.182662858272129270f, 0.983140566816954500f, + -0.182851376475096330f, + 0.983105487431216290f, -0.183039887955140950f, 0.983070371899499640f, + -0.183228392705332140f, + 0.983035220223095640f, -0.183416890718739100f, 0.983000032403296590f, + -0.183605381988431270f, + 0.982964808441396440f, -0.183793866507478450f, 0.982929548338690170f, + -0.183982344268950520f, + 0.982894252096474070f, -0.184170815265917720f, 0.982858919716046110f, + -0.184359279491450510f, + 0.982823551198705240f, -0.184547736938619620f, 0.982788146545751970f, + -0.184736187600495950f, + 0.982752705758487830f, -0.184924631470150790f, 0.982717228838215990f, + -0.185113068540655540f, + 0.982681715786240860f, -0.185301498805081900f, 0.982646166603868050f, + -0.185489922256501880f, + 0.982610581292404750f, -0.185678338887987630f, 0.982574959853159240f, + -0.185866748692611660f, + 0.982539302287441240f, -0.186055151663446630f, 0.982503608596561830f, + -0.186243547793565560f, + 0.982467878781833170f, -0.186431937076041610f, 0.982432112844569110f, + -0.186620319503948280f, + 0.982396310786084690f, -0.186808695070359270f, 0.982360472607696210f, + -0.186997063768348540f, + 0.982324598310721280f, -0.187185425590990330f, 0.982288687896478830f, + -0.187373780531359110f, + 0.982252741366289370f, -0.187562128582529600f, 0.982216758721474510f, + -0.187750469737576780f, + 0.982180739963357090f, -0.187938803989575910f, 0.982144685093261580f, + -0.188127131331602420f, + 0.982108594112513610f, -0.188315451756732120f, 0.982072467022440000f, + -0.188503765258040940f, + 0.982036303824369020f, -0.188692071828605230f, 0.982000104519630490f, + -0.188880371461501380f, + 0.981963869109555240f, -0.189068664149806190f, 0.981927597595475540f, + -0.189256949886596750f, + 0.981891289978725100f, -0.189445228664950230f, 0.981854946260638630f, + -0.189633500477944190f, + 0.981818566442552500f, -0.189821765318656410f, 0.981782150525804310f, + -0.190010023180164990f, + 0.981745698511732990f, -0.190198274055548150f, 0.981709210401678800f, + -0.190386517937884470f, + 0.981672686196983110f, -0.190574754820252740f, 0.981636125898989080f, + -0.190762984695732110f, + 0.981599529509040720f, -0.190951207557401800f, 0.981562897028483650f, + -0.191139423398341450f, + 0.981526228458664770f, -0.191327632211630900f, 0.981489523800932130f, + -0.191515833990350210f, + 0.981452783056635520f, -0.191704028727579800f, 0.981416006227125550f, + -0.191892216416400220f, + 0.981379193313754560f, -0.192080397049892440f, 0.981342344317876040f, + -0.192268570621137500f, + 0.981305459240844670f, -0.192456737123216840f, 0.981268538084016710f, + -0.192644896549212100f, + 0.981231580848749730f, -0.192833048892205230f, 0.981194587536402320f, + -0.193021194145278380f, + 0.981157558148334830f, -0.193209332301513960f, 0.981120492685908730f, + -0.193397463353994740f, + 0.981083391150486710f, -0.193585587295803610f, 0.981046253543432780f, + -0.193773704120023820f, + 0.981009079866112630f, -0.193961813819738840f, 0.980971870119892840f, + -0.194149916388032450f, + 0.980934624306141640f, -0.194338011817988600f, 0.980897342426228390f, + -0.194526100102691610f, + 0.980860024481523870f, -0.194714181235225960f, 0.980822670473400100f, + -0.194902255208676520f, + 0.980785280403230430f, -0.195090322016128250f, 0.980747854272389750f, + -0.195278381650666550f, + 0.980710392082253970f, -0.195466434105376980f, 0.980672893834200530f, + -0.195654479373345370f, + 0.980635359529608120f, -0.195842517447657850f, 0.980597789169856850f, + -0.196030548321400790f, + 0.980560182756327840f, -0.196218571987660880f, 0.980522540290404090f, + -0.196406588439524970f, + 0.980484861773469380f, -0.196594597670080220f, 0.980447147206909060f, + -0.196782599672414100f, + 0.980409396592109910f, -0.196970594439614340f, 0.980371609930459800f, + -0.197158581964768880f, + 0.980333787223347960f, -0.197346562240965920f, 0.980295928472165290f, + -0.197534535261294030f, + 0.980258033678303550f, -0.197722501018841920f, 0.980220102843156080f, + -0.197910459506698670f, + 0.980182135968117430f, -0.198098410717953560f, 0.980144133054583590f, + -0.198286354645696220f, + 0.980106094103951770f, -0.198474291283016390f, 0.980068019117620650f, + -0.198662220623004200f, + 0.980029908096990090f, -0.198850142658750090f, 0.979991761043461200f, + -0.199038057383344680f, + 0.979953577958436740f, -0.199225964789878830f, 0.979915358843320480f, + -0.199413864871443770f, + 0.979877103699517640f, -0.199601757621130970f, 0.979838812528434740f, + -0.199789643032032090f, + 0.979800485331479790f, -0.199977521097239150f, 0.979762122110061750f, + -0.200165391809844440f, + 0.979723722865591170f, -0.200353255162940450f, 0.979685287599479930f, + -0.200541111149619980f, + 0.979646816313141210f, -0.200728959762976140f, 0.979608309007989450f, + -0.200916800996102230f, + 0.979569765685440520f, -0.201104634842091900f, 0.979531186346911500f, + -0.201292461294039020f, + 0.979492570993820810f, -0.201480280345037730f, 0.979453919627588210f, + -0.201668091988182530f, + 0.979415232249634780f, -0.201855896216568050f, 0.979376508861383170f, + -0.202043693023289260f, + 0.979337749464256780f, -0.202231482401441450f, 0.979298954059681040f, + -0.202419264344120160f, + 0.979260122649082020f, -0.202607038844421130f, 0.979221255233887700f, + -0.202794805895440440f, + 0.979182351815526930f, -0.202982565490274440f, 0.979143412395430230f, + -0.203170317622019790f, + 0.979104436975029250f, -0.203358062283773320f, 0.979065425555756930f, + -0.203545799468632190f, + 0.979026378139047580f, -0.203733529169693920f, 0.978987294726337050f, + -0.203921251380056120f, + 0.978948175319062200f, -0.204108966092816870f, 0.978909019918661310f, + -0.204296673301074370f, + 0.978869828526574120f, -0.204484372997927240f, 0.978830601144241470f, + -0.204672065176474210f, + 0.978791337773105670f, -0.204859749829814420f, 0.978752038414610340f, + -0.205047426951047250f, + 0.978712703070200420f, -0.205235096533272350f, 0.978673331741322210f, + -0.205422758569589610f, + 0.978633924429423210f, -0.205610413053099240f, 0.978594481135952270f, + -0.205798059976901790f, + 0.978555001862359550f, -0.205985699334097910f, 0.978515486610096910f, + -0.206173331117788710f, + 0.978475935380616830f, -0.206360955321075510f, 0.978436348175373730f, + -0.206548571937059890f, + 0.978396724995823090f, -0.206736180958843690f, 0.978357065843421640f, + -0.206923782379529100f, + 0.978317370719627650f, -0.207111376192218560f, 0.978277639625900530f, + -0.207298962390014750f, + 0.978237872563701090f, -0.207486540966020650f, 0.978198069534491400f, + -0.207674111913339570f, + 0.978158230539735050f, -0.207861675225075070f, 0.978118355580896660f, + -0.208049230894330940f, + 0.978078444659442380f, -0.208236778914211330f, 0.978038497776839600f, + -0.208424319277820600f, + 0.977998514934557140f, -0.208611851978263490f, 0.977958496134064830f, + -0.208799377008644900f, + 0.977918441376834370f, -0.208986894362070070f, 0.977878350664338150f, + -0.209174404031644580f, + 0.977838223998050430f, -0.209361906010474160f, 0.977798061379446360f, + -0.209549400291664940f, + 0.977757862810002760f, -0.209736886868323290f, 0.977717628291197460f, + -0.209924365733555880f, + 0.977677357824509930f, -0.210111836880469610f, 0.977637051411420770f, + -0.210299300302171730f, + 0.977596709053411890f, -0.210486755991769720f, 0.977556330751966460f, + -0.210674203942371440f, + 0.977515916508569280f, -0.210861644147084860f, 0.977475466324706170f, + -0.211049076599018390f, + 0.977434980201864260f, -0.211236501291280710f, 0.977394458141532250f, + -0.211423918216980670f, + 0.977353900145199960f, -0.211611327369227550f, 0.977313306214358750f, + -0.211798728741130840f, + 0.977272676350500860f, -0.211986122325800330f, 0.977232010555120320f, + -0.212173508116346080f, + 0.977191308829712280f, -0.212360886105878420f, 0.977150571175773200f, + -0.212548256287508060f, + 0.977109797594800880f, -0.212735618654345930f, 0.977068988088294450f, + -0.212922973199503180f, + 0.977028142657754390f, -0.213110319916091360f, 0.976987261304682390f, + -0.213297658797222320f, + 0.976946344030581670f, -0.213484989836008050f, 0.976905390836956490f, + -0.213672313025560970f, + 0.976864401725312640f, -0.213859628358993750f, 0.976823376697157240f, + -0.214046935829419360f, + 0.976782315753998650f, -0.214234235429950990f, 0.976741218897346550f, + -0.214421527153702160f, + 0.976700086128711840f, -0.214608810993786760f, 0.976658917449606980f, + -0.214796086943318860f, + 0.976617712861545640f, -0.214983354995412820f, 0.976576472366042610f, + -0.215170615143183390f, + 0.976535195964614470f, -0.215357867379745550f, 0.976493883658778650f, + -0.215545111698214500f, + 0.976452535450054060f, -0.215732348091705880f, 0.976411151339961040f, + -0.215919576553335490f, + 0.976369731330021140f, -0.216106797076219520f, 0.976328275421757260f, + -0.216294009653474340f, + 0.976286783616693630f, -0.216481214278216730f, 0.976245255916355800f, + -0.216668410943563730f, + 0.976203692322270560f, -0.216855599642632620f, 0.976162092835966110f, + -0.217042780368540990f, + 0.976120457458971910f, -0.217229953114406790f, 0.976078786192818850f, + -0.217417117873348190f, + 0.976037079039039020f, -0.217604274638483640f, 0.975995335999165990f, + -0.217791423402931950f, + 0.975953557074734300f, -0.217978564159812200f, 0.975911742267280170f, + -0.218165696902243800f, + 0.975869891578341030f, -0.218352821623346320f, 0.975828005009455660f, + -0.218539938316239770f, + 0.975786082562163930f, -0.218727046974044440f, 0.975744124238007270f, + -0.218914147589880840f, + 0.975702130038528570f, -0.219101240156869800f, 0.975660099965271590f, + -0.219288324668132470f, + 0.975618034019781750f, -0.219475401116790310f, 0.975575932203605720f, + -0.219662469495965050f, + 0.975533794518291360f, -0.219849529798778700f, 0.975491620965388110f, + -0.220036582018353580f, + 0.975449411546446380f, -0.220223626147812380f, 0.975407166263018270f, + -0.220410662180277940f, + 0.975364885116656980f, -0.220597690108873510f, 0.975322568108916930f, + -0.220784709926722610f, + 0.975280215241354220f, -0.220971721626949110f, 0.975237826515525820f, + -0.221158725202677010f, + 0.975195401932990370f, -0.221345720647030810f, 0.975152941495307620f, + -0.221532707953135230f, + 0.975110445204038890f, -0.221719687114115220f, 0.975067913060746470f, + -0.221906658123096100f, + 0.975025345066994120f, -0.222093620973203510f, 0.974982741224347140f, + -0.222280575657563370f, + 0.974940101534371830f, -0.222467522169301880f, 0.974897425998635820f, + -0.222654460501545500f, + 0.974854714618708430f, -0.222841390647421120f, 0.974811967396159830f, + -0.223028312600055820f, + 0.974769184332561770f, -0.223215226352576980f, 0.974726365429487320f, + -0.223402131898112370f, + 0.974683510688510670f, -0.223589029229789990f, 0.974640620111207560f, + -0.223775918340738150f, + 0.974597693699155050f, -0.223962799224085460f, 0.974554731453931230f, + -0.224149671872960870f, + 0.974511733377115720f, -0.224336536280493600f, 0.974468699470289580f, + -0.224523392439813170f, + 0.974425629735034990f, -0.224710240344049430f, 0.974382524172935470f, + -0.224897079986332490f, + 0.974339382785575860f, -0.225083911359792830f, 0.974296205574542440f, + -0.225270734457561160f, + 0.974252992541422500f, -0.225457549272768540f, 0.974209743687805220f, + -0.225644355798546330f, + 0.974166459015280320f, -0.225831154028026170f, 0.974123138525439640f, + -0.226017943954340020f, + 0.974079782219875680f, -0.226204725570620190f, 0.974036390100182610f, + -0.226391498869999240f, + 0.973992962167955830f, -0.226578263845610000f, 0.973949498424792170f, + -0.226765020490585690f, + 0.973905998872289570f, -0.226951768798059810f, 0.973862463512047300f, + -0.227138508761166170f, + 0.973818892345666100f, -0.227325240373038860f, 0.973775285374748110f, + -0.227511963626812280f, + 0.973731642600896400f, -0.227698678515621170f, 0.973687964025715670f, + -0.227885385032600530f, + 0.973644249650811980f, -0.228072083170885730f, 0.973600499477792370f, + -0.228258772923612380f, + 0.973556713508265560f, -0.228445454283916470f, 0.973512891743841370f, + -0.228632127244934230f, + 0.973469034186131070f, -0.228818791799802220f, 0.973425140836747030f, + -0.229005447941657340f, + 0.973381211697303290f, -0.229192095663636770f, 0.973337246769414910f, + -0.229378734958878010f, + 0.973293246054698250f, -0.229565365820518870f, 0.973249209554771230f, + -0.229751988241697490f, + 0.973205137271252800f, -0.229938602215552210f, 0.973161029205763530f, + -0.230125207735221850f, + 0.973116885359925130f, -0.230311804793845440f, 0.973072705735360530f, + -0.230498393384562350f, + 0.973028490333694210f, -0.230684973500512200f, 0.972984239156551740f, + -0.230871545134835020f, + 0.972939952205560180f, -0.231058108280671110f, 0.972895629482347760f, + -0.231244662931161050f, + 0.972851270988544180f, -0.231431209079445750f, 0.972806876725780370f, + -0.231617746718666470f, + 0.972762446695688570f, -0.231804275841964780f, 0.972717980899902250f, + -0.231990796442482440f, + 0.972673479340056430f, -0.232177308513361710f, 0.972628942017787270f, + -0.232363812047745030f, + 0.972584368934732210f, -0.232550307038775240f, 0.972539760092530180f, + -0.232736793479595390f, + 0.972495115492821190f, -0.232923271363348980f, 0.972450435137246830f, + -0.233109740683179690f, + 0.972405719027449770f, -0.233296201432231590f, 0.972360967165074140f, + -0.233482653603649090f, + 0.972316179551765300f, -0.233669097190576820f, 0.972271356189170040f, + -0.233855532186159840f, + 0.972226497078936270f, -0.234041958583543430f, 0.972181602222713440f, + -0.234228376375873210f, + 0.972136671622152230f, -0.234414785556295160f, 0.972091705278904430f, + -0.234601186117955550f, + 0.972046703194623500f, -0.234787578054000970f, 0.972001665370963890f, + -0.234973961357578250f, + 0.971956591809581720f, -0.235160336021834730f, 0.971911482512134000f, + -0.235346702039917840f, + 0.971866337480279400f, -0.235533059404975490f, 0.971821156715677700f, + -0.235719408110155820f, + 0.971775940219990140f, -0.235905748148607370f, 0.971730687994879160f, + -0.236092079513478910f, + 0.971685400042008540f, -0.236278402197919570f, 0.971640076363043390f, + -0.236464716195078780f, + 0.971594716959650160f, -0.236651021498106380f, 0.971549321833496630f, + -0.236837318100152380f, + 0.971503890986251780f, -0.237023605994367200f, 0.971458424419585960f, + -0.237209885173901600f, + 0.971412922135170940f, -0.237396155631906610f, 0.971367384134679490f, + -0.237582417361533570f, + 0.971321810419786160f, -0.237768670355934190f, 0.971276200992166490f, + -0.237954914608260540f, + 0.971230555853497380f, -0.238141150111664840f, 0.971184875005457030f, + -0.238327376859299810f, + 0.971139158449725090f, -0.238513594844318420f, 0.971093406187982460f, + -0.238699804059873980f, + 0.971047618221911100f, -0.238886004499120040f, 0.971001794553194690f, + -0.239072196155210610f, + 0.970955935183517970f, -0.239258379021299980f, 0.970910040114567050f, + -0.239444553090542630f, + 0.970864109348029470f, -0.239630718356093560f, 0.970818142885593870f, + -0.239816874811108000f, + 0.970772140728950350f, -0.240003022448741500f, 0.970726102879790110f, + -0.240189161262149900f, + 0.970680029339806130f, -0.240375291244489450f, 0.970633920110692160f, + -0.240561412388916650f, + 0.970587775194143630f, -0.240747524688588430f, 0.970541594591857070f, + -0.240933628136661910f, + 0.970495378305530560f, -0.241119722726294590f, 0.970449126336863090f, + -0.241305808450644370f, + 0.970402838687555500f, -0.241491885302869330f, 0.970356515359309450f, + -0.241677953276128010f, + 0.970310156353828110f, -0.241864012363579180f, 0.970263761672816140f, + -0.242050062558382070f, + 0.970217331317979160f, -0.242236103853696010f, 0.970170865291024480f, + -0.242422136242680890f, + 0.970124363593660280f, -0.242608159718496810f, 0.970077826227596420f, + -0.242794174274304220f, + 0.970031253194543970f, -0.242980179903263870f, 0.969984644496215240f, + -0.243166176598536900f, + 0.969938000134323960f, -0.243352164353284740f, 0.969891320110585100f, + -0.243538143160669130f, + 0.969844604426714830f, -0.243724113013852160f, 0.969797853084430890f, + -0.243910073905996260f, + 0.969751066085452140f, -0.244096025830264210f, 0.969704243431498860f, + -0.244281968779819030f, + 0.969657385124292450f, -0.244467902747824150f, 0.969610491165555870f, + -0.244653827727443320f, + 0.969563561557013180f, -0.244839743711840670f, 0.969516596300390000f, + -0.245025650694180470f, + 0.969469595397413060f, -0.245211548667627540f, 0.969422558849810320f, + -0.245397437625346960f, + 0.969375486659311280f, -0.245583317560504060f, 0.969328378827646660f, + -0.245769188466264580f, + 0.969281235356548530f, -0.245955050335794590f, 0.969234056247750050f, + -0.246140903162260530f, + 0.969186841502985950f, -0.246326746938829030f, 0.969139591123992280f, + -0.246512581658667210f, + 0.969092305112506210f, -0.246698407314942410f, 0.969044983470266240f, + -0.246884223900822430f, + 0.968997626199012420f, -0.247070031409475250f, 0.968950233300485800f, + -0.247255829834069300f, + 0.968902804776428870f, -0.247441619167773270f, 0.968855340628585580f, + -0.247627399403756280f, + 0.968807840858700970f, -0.247813170535187670f, 0.968760305468521430f, + -0.247998932555237110f, + 0.968712734459794780f, -0.248184685457074780f, 0.968665127834270060f, + -0.248370429233870980f, + 0.968617485593697540f, -0.248556163878796560f, 0.968569807739828930f, + -0.248741889385022480f, + 0.968522094274417380f, -0.248927605745720150f, 0.968474345199216820f, + -0.249113312954061360f, + 0.968426560515983190f, -0.249299011003218190f, 0.968378740226473300f, + -0.249484699886362960f, + 0.968330884332445190f, -0.249670379596668550f, 0.968282992835658660f, + -0.249856050127307990f, + 0.968235065737874320f, -0.250041711471454650f, 0.968187103040854420f, + -0.250227363622282370f, + 0.968139104746362440f, -0.250413006572965220f, 0.968091070856162970f, + -0.250598640316677670f, + 0.968043001372022260f, -0.250784264846594500f, 0.967994896295707670f, + -0.250969880155890720f, + 0.967946755628987800f, -0.251155486237741920f, 0.967898579373632660f, + -0.251341083085323880f, + 0.967850367531413620f, -0.251526670691812610f, 0.967802120104103270f, + -0.251712249050384700f, + 0.967753837093475510f, -0.251897818154216970f, 0.967705518501305480f, + -0.252083377996486450f, + 0.967657164329369880f, -0.252268928570370810f, 0.967608774579446500f, + -0.252454469869047740f, + 0.967560349253314360f, -0.252640001885695520f, 0.967511888352754150f, + -0.252825524613492610f, + 0.967463391879547550f, -0.253011038045617860f, 0.967414859835477480f, + -0.253196542175250560f, + 0.967366292222328510f, -0.253382036995570160f, 0.967317689041886310f, + -0.253567522499756560f, + 0.967269050295937790f, -0.253752998680989990f, 0.967220375986271420f, + -0.253938465532451090f, + 0.967171666114676640f, -0.254123923047320620f, 0.967122920682944360f, + -0.254309371218780000f, + 0.967074139692867040f, -0.254494810040010730f, 0.967025323146238010f, + -0.254680239504194830f, + 0.966976471044852070f, -0.254865659604514570f, 0.966927583390505660f, + -0.255051070334152470f, + 0.966878660184995910f, -0.255236471686291710f, 0.966829701430121810f, + -0.255421863654115460f, + 0.966780707127683270f, -0.255607246230807380f, 0.966731677279481840f, + -0.255792619409551610f, + 0.966682611887320080f, -0.255977983183532430f, 0.966633510953002100f, + -0.256163337545934460f, + 0.966584374478333120f, -0.256348682489942910f, 0.966535202465119700f, + -0.256534018008743040f, + 0.966485994915169840f, -0.256719344095520660f, 0.966436751830292650f, + -0.256904660743461910f, + 0.966387473212298900f, -0.257089967945753120f, 0.966338159063000130f, + -0.257275265695581120f, + 0.966288809384209690f, -0.257460553986133100f, 0.966239424177741890f, + -0.257645832810596390f, + 0.966190003445412500f, -0.257831102162158990f, 0.966140547189038750f, + -0.258016362034009020f, + 0.966091055410438830f, -0.258201612419334870f, 0.966041528111432400f, + -0.258386853311325600f, + 0.965991965293840570f, -0.258572084703170340f, 0.965942366959485540f, + -0.258757306588058680f, + 0.965892733110190860f, -0.258942518959180520f, 0.965843063747781510f, + -0.259127721809726150f, + 0.965793358874083680f, -0.259312915132886230f, 0.965743618490924830f, + -0.259498098921851660f, + 0.965693842600133690f, -0.259683273169813770f, 0.965644031203540590f, + -0.259868437869964270f, + 0.965594184302976830f, -0.260053593015495190f, 0.965544301900275180f, + -0.260238738599598840f, + 0.965494383997269500f, -0.260423874615468010f, 0.965444430595795430f, + -0.260609001056295750f, + 0.965394441697689400f, -0.260794117915275510f, 0.965344417304789370f, + -0.260979225185601070f, + 0.965294357418934660f, -0.261164322860466480f, 0.965244262041965780f, + -0.261349410933066350f, + 0.965194131175724720f, -0.261534489396595520f, 0.965143964822054450f, + -0.261719558244249030f, + 0.965093762982799590f, -0.261904617469222610f, 0.965043525659805890f, + -0.262089667064712040f, + 0.964993252854920320f, -0.262274707023913590f, 0.964942944569991410f, + -0.262459737340023980f, + 0.964892600806868890f, -0.262644758006240040f, 0.964842221567403620f, + -0.262829769015759160f, + 0.964791806853447900f, -0.263014770361779000f, 0.964741356666855340f, + -0.263199762037497560f, + 0.964690871009481030f, -0.263384744036113280f, 0.964640349883180930f, + -0.263569716350824880f, + 0.964589793289812760f, -0.263754678974831350f, 0.964539201231235150f, + -0.263939631901332350f, + 0.964488573709308410f, -0.264124575123527550f, 0.964437910725893910f, + -0.264309508634617110f, + 0.964387212282854290f, -0.264494432427801630f, 0.964336478382053720f, + -0.264679346496281890f, + 0.964285709025357480f, -0.264864250833259260f, 0.964234904214632200f, + -0.265049145431935250f, + 0.964184063951745830f, -0.265234030285511790f, 0.964133188238567640f, + -0.265418905387191260f, + 0.964082277076968140f, -0.265603770730176330f, 0.964031330468819280f, + -0.265788626307669920f, + 0.963980348415994110f, -0.265973472112875590f, 0.963929330920367140f, + -0.266158308138996990f, + 0.963878277983814200f, -0.266343134379238180f, 0.963827189608212340f, + -0.266527950826803690f, + 0.963776065795439840f, -0.266712757474898370f, 0.963724906547376530f, + -0.266897554316727350f, + 0.963673711865903230f, -0.267082341345496300f, 0.963622481752902220f, + -0.267267118554410930f, + 0.963571216210257320f, -0.267451885936677620f, 0.963519915239853140f, + -0.267636643485503090f, + 0.963468578843575950f, -0.267821391194094150f, 0.963417207023313350f, + -0.268006129055658290f, + 0.963365799780954050f, -0.268190857063403180f, 0.963314357118388200f, + -0.268375575210536900f, + 0.963262879037507070f, -0.268560283490267890f, 0.963211365540203480f, + -0.268744981895804980f, + 0.963159816628371360f, -0.268929670420357260f, 0.963108232303906190f, + -0.269114349057134380f, + 0.963056612568704340f, -0.269299017799346120f, 0.963004957424663850f, + -0.269483676640202840f, + 0.962953266873683880f, -0.269668325572915090f, 0.962901540917665000f, + -0.269852964590693860f, + 0.962849779558509030f, -0.270037593686750570f, 0.962797982798119010f, + -0.270222212854296870f, + 0.962746150638399410f, -0.270406822086544820f, 0.962694283081255930f, + -0.270591421376706940f, + 0.962642380128595710f, -0.270776010717996010f, 0.962590441782326890f, + -0.270960590103625170f, + 0.962538468044359160f, -0.271145159526808010f, 0.962486458916603450f, + -0.271329718980758420f, + 0.962434414400972100f, -0.271514268458690700f, 0.962382334499378380f, + -0.271698807953819510f, + 0.962330219213737400f, -0.271883337459359720f, 0.962278068545965090f, + -0.272067856968526920f, + 0.962225882497979020f, -0.272252366474536710f, 0.962173661071697880f, + -0.272436865970605240f, + 0.962121404269041580f, -0.272621355449948980f, 0.962069112091931580f, + -0.272805834905784810f, + 0.962016784542290560f, -0.272990304331329920f, 0.961964421622042320f, + -0.273174763719801930f, + 0.961912023333112210f, -0.273359213064418680f, 0.961859589677426570f, + -0.273543652358398730f, + 0.961807120656913540f, -0.273728081594960540f, 0.961754616273502010f, + -0.273912500767323260f, + 0.961702076529122540f, -0.274096909868706380f, 0.961649501425706820f, + -0.274281308892329660f, + 0.961596890965187860f, -0.274465697831413220f, 0.961544245149499990f, + -0.274650076679177680f, + 0.961491563980579000f, -0.274834445428843940f, 0.961438847460361680f, + -0.275018804073633220f, + 0.961386095590786250f, -0.275203152606767310f, 0.961333308373792270f, + -0.275387491021468140f, + 0.961280485811320640f, -0.275571819310958140f, 0.961227627905313460f, + -0.275756137468460120f, + 0.961174734657714080f, -0.275940445487197150f, 0.961121806070467380f, + -0.276124743360392830f, + 0.961068842145519350f, -0.276309031081271080f, 0.961015842884817230f, + -0.276493308643055990f, + 0.960962808290309780f, -0.276677576038972420f, 0.960909738363946770f, + -0.276861833262245280f, + 0.960856633107679660f, -0.277046080306099900f, 0.960803492523460760f, + -0.277230317163762170f, + 0.960750316613243950f, -0.277414543828458090f, 0.960697105378984450f, + -0.277598760293414290f, + 0.960643858822638590f, -0.277782966551857690f, 0.960590576946164120f, + -0.277967162597015370f, + 0.960537259751520050f, -0.278151348422115090f, 0.960483907240666790f, + -0.278335524020384920f, + 0.960430519415565790f, -0.278519689385053060f, 0.960377096278180130f, + -0.278703844509348490f, + 0.960323637830473920f, -0.278887989386500280f, 0.960270144074412800f, + -0.279072124009737800f, + 0.960216615011963430f, -0.279256248372291180f, 0.960163050645094000f, + -0.279440362467390510f, + 0.960109450975773940f, -0.279624466288266590f, 0.960055816005973890f, + -0.279808559828150390f, + 0.960002145737665960f, -0.279992643080273220f, 0.959948440172823210f, + -0.280176716037866980f, + 0.959894699313420530f, -0.280360778694163810f, 0.959840923161433770f, + -0.280544831042396250f, + 0.959787111718839900f, -0.280728873075797190f, 0.959733264987617680f, + -0.280912904787600000f, + 0.959679382969746750f, -0.281096926171038260f, 0.959625465667208190f, + -0.281280937219346110f, + 0.959571513081984520f, -0.281464937925757940f, 0.959517525216059260f, + -0.281648928283508630f, + 0.959463502071417510f, -0.281832908285833350f, 0.959409443650045550f, + -0.282016877925967640f, + 0.959355349953930790f, -0.282200837197147560f, 0.959301220985062210f, + -0.282384786092609360f, + 0.959247056745430090f, -0.282568724605589740f, 0.959192857237025740f, + -0.282752652729325930f, + 0.959138622461841890f, -0.282936570457055390f, 0.959084352421872730f, + -0.283120477782015820f, + 0.959030047119113660f, -0.283304374697445740f, 0.958975706555561080f, + -0.283488261196583550f, + 0.958921330733213170f, -0.283672137272668430f, 0.958866919654069010f, + -0.283856002918939750f, + 0.958812473320129310f, -0.284039858128637190f, 0.958757991733395710f, + -0.284223702895001040f, + 0.958703474895871600f, -0.284407537211271880f, 0.958648922809561150f, + -0.284591361070690440f, + 0.958594335476470220f, -0.284775174466498300f, 0.958539712898605730f, + -0.284958977391937040f, + 0.958485055077976100f, -0.285142769840248670f, 0.958430362016590930f, + -0.285326551804675870f, + 0.958375633716461170f, -0.285510323278461260f, 0.958320870179598880f, + -0.285694084254848320f, + 0.958266071408017670f, -0.285877834727080620f, 0.958211237403732260f, + -0.286061574688402040f, + 0.958156368168758820f, -0.286245304132057120f, 0.958101463705114730f, + -0.286429023051290700f, + 0.958046524014818600f, -0.286612731439347790f, 0.957991549099890370f, + -0.286796429289474080f, + 0.957936538962351420f, -0.286980116594915570f, 0.957881493604224370f, + -0.287163793348918390f, + 0.957826413027532910f, -0.287347459544729510f, 0.957771297234302320f, + -0.287531115175595930f, + 0.957716146226558870f, -0.287714760234765170f, 0.957660960006330610f, + -0.287898394715485170f, + 0.957605738575646350f, -0.288082018611004130f, 0.957550481936536470f, + -0.288265631914570770f, + 0.957495190091032570f, -0.288449234619434220f, 0.957439863041167680f, + -0.288632826718843830f, + 0.957384500788975860f, -0.288816408206049480f, 0.957329103336492790f, + -0.288999979074301420f, + 0.957273670685755200f, -0.289183539316850200f, 0.957218202838801210f, + -0.289367088926947010f, + 0.957162699797670210f, -0.289550627897843030f, 0.957107161564402790f, + -0.289734156222790250f, + 0.957051588141040970f, -0.289917673895040750f, 0.956995979529628230f, + -0.290101180907847090f, + 0.956940335732208820f, -0.290284677254462330f, 0.956884656750828900f, + -0.290468162928139820f, + 0.956828942587535370f, -0.290651637922133220f, 0.956773193244376930f, + -0.290835102229696830f, + 0.956717408723403050f, -0.291018555844085090f, 0.956661589026665090f, + -0.291201998758552900f, + 0.956605734156215080f, -0.291385430966355660f, 0.956549844114106820f, + -0.291568852460749040f, + 0.956493918902395100f, -0.291752263234989260f, 0.956437958523136180f, + -0.291935663282332780f, + 0.956381962978387730f, -0.292119052596036380f, 0.956325932270208230f, + -0.292302431169357560f, + 0.956269866400658030f, -0.292485798995553880f, 0.956213765371798470f, + -0.292669156067883460f, + 0.956157629185692140f, -0.292852502379604810f, 0.956101457844403040f, + -0.293035837923976810f, + 0.956045251349996410f, -0.293219162694258630f, 0.955989009704538930f, + -0.293402476683710110f, + 0.955932732910098280f, -0.293585779885591200f, 0.955876420968743590f, + -0.293769072293162400f, + 0.955820073882545420f, -0.293952353899684660f, 0.955763691653575440f, + -0.294135624698419030f, + 0.955707274283906560f, -0.294318884682627400f, 0.955650821775613330f, + -0.294502133845571670f, + 0.955594334130771110f, -0.294685372180514330f, 0.955537811351456880f, + -0.294868599680718270f, + 0.955481253439748770f, -0.295051816339446720f, 0.955424660397726330f, + -0.295235022149963220f, + 0.955368032227470350f, -0.295418217105532010f, 0.955311368931062720f, + -0.295601401199417360f, + 0.955254670510586990f, -0.295784574424884260f, 0.955197936968127710f, + -0.295967736775197890f, + 0.955141168305770780f, -0.296150888243623790f, 0.955084364525603410f, + -0.296334028823428190f, + 0.955027525629714160f, -0.296517158507877470f, 0.954970651620192790f, + -0.296700277290238350f, + 0.954913742499130520f, -0.296883385163778270f, 0.954856798268619580f, + -0.297066482121764730f, + 0.954799818930753720f, -0.297249568157465840f, 0.954742804487627940f, + -0.297432643264150030f, + 0.954685754941338340f, -0.297615707435086200f, 0.954628670293982680f, + -0.297798760663543550f, + 0.954571550547659630f, -0.297981802942791810f, 0.954514395704469500f, + -0.298164834266100850f, + 0.954457205766513490f, -0.298347854626741400f, 0.954399980735894490f, + -0.298530864017984120f, + 0.954342720614716480f, -0.298713862433100330f, 0.954285425405084650f, + -0.298896849865361800f, + 0.954228095109105670f, -0.299079826308040480f, 0.954170729728887280f, + -0.299262791754408840f, + 0.954113329266538800f, -0.299445746197739890f, 0.954055893724170660f, + -0.299628689631306790f, + 0.953998423103894490f, -0.299811622048383350f, 0.953940917407823500f, + -0.299994543442243580f, + 0.953883376638071770f, -0.300177453806161950f, 0.953825800796755050f, + -0.300360353133413530f, + 0.953768189885990330f, -0.300543241417273450f, 0.953710543907895670f, + -0.300726118651017500f, + 0.953652862864590500f, -0.300908984827921890f, 0.953595146758195680f, + -0.301091839941263100f, + 0.953537395590833280f, -0.301274683984317950f, 0.953479609364626610f, + -0.301457516950363940f, + 0.953421788081700310f, -0.301640338832678770f, 0.953363931744180330f, + -0.301823149624540650f, + 0.953306040354193860f, -0.302005949319228080f, 0.953248113913869320f, + -0.302188737910019990f, + 0.953190152425336670f, -0.302371515390195970f, 0.953132155890726750f, + -0.302554281753035610f, + 0.953074124312172200f, -0.302737036991819140f, 0.953016057691806530f, + -0.302919781099827310f, + 0.952957956031764700f, -0.303102514070341060f, 0.952899819334182880f, + -0.303285235896641750f, + 0.952841647601198720f, -0.303467946572011320f, 0.952783440834950920f, + -0.303650646089731910f, + 0.952725199037579570f, -0.303833334443086360f, 0.952666922211226170f, + -0.304016011625357570f, + 0.952608610358033350f, -0.304198677629829110f, 0.952550263480144930f, + -0.304381332449784880f, + 0.952491881579706320f, -0.304563976078509100f, 0.952433464658864030f, + -0.304746608509286530f, + 0.952375012719765880f, -0.304929229735402370f, 0.952316525764560940f, + -0.305111839750142110f, + 0.952258003795399600f, -0.305294438546791670f, 0.952199446814433580f, + -0.305477026118637420f, + 0.952140854823815830f, -0.305659602458966120f, 0.952082227825700620f, + -0.305842167561065080f, + 0.952023565822243570f, -0.306024721418221790f, 0.951964868815601380f, + -0.306207264023724220f, + 0.951906136807932350f, -0.306389795370860920f, 0.951847369801395620f, + -0.306572315452920740f, + 0.951788567798152130f, -0.306754824263192780f, 0.951729730800363830f, + -0.306937321794966910f, + 0.951670858810193860f, -0.307119808041533100f, 0.951611951829806850f, + -0.307302282996181790f, + 0.951553009861368590f, -0.307484746652204100f, 0.951494032907046370f, + -0.307667199002891190f, + 0.951435020969008340f, -0.307849640041534870f, 0.951375974049424420f, + -0.308032069761427330f, + 0.951316892150465550f, -0.308214488155861050f, 0.951257775274304000f, + -0.308396895218129190f, + 0.951198623423113230f, -0.308579290941525090f, 0.951139436599068190f, + -0.308761675319342450f, + 0.951080214804345010f, -0.308944048344875710f, 0.951020958041121080f, + -0.309126410011419440f, + 0.950961666311575080f, -0.309308760312268730f, 0.950902339617887060f, + -0.309491099240719100f, + 0.950842977962238160f, -0.309673426790066380f, 0.950783581346811070f, + -0.309855742953607070f, + 0.950724149773789610f, -0.310038047724637890f, 0.950664683245358910f, + -0.310220341096455850f, + 0.950605181763705340f, -0.310402623062358720f, 0.950545645331016600f, + -0.310584893615644450f, + 0.950486073949481700f, -0.310767152749611470f, 0.950426467621290900f, + -0.310949400457558640f, + 0.950366826348635780f, -0.311131636732785270f, 0.950307150133709260f, + -0.311313861568590920f, + 0.950247438978705230f, -0.311496074958275910f, 0.950187692885819280f, + -0.311678276895140550f, + 0.950127911857248100f, -0.311860467372486020f, 0.950068095895189590f, + -0.312042646383613510f, + 0.950008245001843000f, -0.312224813921824880f, 0.949948359179409010f, + -0.312406969980422440f, + 0.949888438430089300f, -0.312589114552708710f, 0.949828482756087110f, + -0.312771247631986770f, + 0.949768492159606680f, -0.312953369211560200f, 0.949708466642853800f, + -0.313135479284732840f, + 0.949648406208035480f, -0.313317577844809010f, 0.949588310857359950f, + -0.313499664885093510f, + 0.949528180593036670f, -0.313681740398891520f, 0.949468015417276550f, + -0.313863804379508500f, + 0.949407815332291570f, -0.314045856820250710f, 0.949347580340295210f, + -0.314227897714424440f, + 0.949287310443502120f, -0.314409927055336660f, 0.949227005644128210f, + -0.314591944836294660f, + 0.949166665944390700f, -0.314773951050606070f, 0.949106291346508260f, + -0.314955945691579140f, + 0.949045881852700560f, -0.315137928752522440f, 0.948985437465188710f, + -0.315319900226744890f, + 0.948924958186195160f, -0.315501860107555990f, 0.948864444017943340f, + -0.315683808388265650f, + 0.948803894962658490f, -0.315865745062183960f, 0.948743311022566480f, + -0.316047670122621860f, + 0.948682692199895090f, -0.316229583562890330f, 0.948622038496872990f, + -0.316411485376300980f, + 0.948561349915730270f, -0.316593375556165850f, 0.948500626458698260f, + -0.316775254095797270f, + 0.948439868128009620f, -0.316957120988508150f, 0.948379074925898120f, + -0.317138976227611780f, + 0.948318246854599090f, -0.317320819806421740f, 0.948257383916349060f, + -0.317502651718252260f, + 0.948196486113385580f, -0.317684471956417970f, 0.948135553447947980f, + -0.317866280514233660f, + 0.948074585922276230f, -0.318048077385014950f, 0.948013583538612200f, + -0.318229862562077530f, + 0.947952546299198670f, -0.318411636038737790f, 0.947891474206279840f, + -0.318593397808312420f, + 0.947830367262101010f, -0.318775147864118480f, 0.947769225468909180f, + -0.318956886199473650f, + 0.947708048828952100f, -0.319138612807695900f, 0.947646837344479300f, + -0.319320327682103610f, + 0.947585591017741090f, -0.319502030816015690f, 0.947524309850989570f, + -0.319683722202751430f, + 0.947462993846477700f, -0.319865401835630500f, 0.947401643006459900f, + -0.320047069707973140f, + 0.947340257333192050f, -0.320228725813099860f, 0.947278836828930880f, + -0.320410370144331820f, + 0.947217381495934820f, -0.320592002694990330f, 0.947155891336463270f, + -0.320773623458397330f, + 0.947094366352777220f, -0.320955232427875210f, 0.947032806547138620f, + -0.321136829596746660f, + 0.946971211921810880f, -0.321318414958334850f, 0.946909582479058760f, + -0.321499988505963510f, + 0.946847918221148000f, -0.321681550232956580f, 0.946786219150346000f, + -0.321863100132638580f, + 0.946724485268921170f, -0.322044638198334510f, 0.946662716579143360f, + -0.322226164423369600f, + 0.946600913083283530f, -0.322407678801069850f, 0.946539074783614100f, + -0.322589181324761330f, + 0.946477201682408680f, -0.322770671987770710f, 0.946415293781942110f, + -0.322952150783425260f, + 0.946353351084490590f, -0.323133617705052330f, 0.946291373592331620f, + -0.323315072745979980f, + 0.946229361307743820f, -0.323496515899536710f, 0.946167314233007370f, + -0.323677947159051240f, + 0.946105232370403450f, -0.323859366517852850f, 0.946043115722214560f, + -0.324040773969271450f, + 0.945980964290724760f, -0.324222169506636960f, 0.945918778078219110f, + -0.324403553123280230f, + 0.945856557086983910f, -0.324584924812532150f, 0.945794301319306970f, + -0.324766284567724220f, + 0.945732010777477150f, -0.324947632382188430f, 0.945669685463784710f, + -0.325128968249257080f, + 0.945607325380521280f, -0.325310292162262930f, 0.945544930529979680f, + -0.325491604114539310f, + 0.945482500914453740f, -0.325672904099419850f, 0.945420036536239070f, + -0.325854192110238580f, + 0.945357537397632290f, -0.326035468140330240f, 0.945295003500931210f, + -0.326216732183029710f, + 0.945232434848435000f, -0.326397984231672490f, 0.945169831442444150f, + -0.326579224279594400f, + 0.945107193285260610f, -0.326760452320131730f, 0.945044520379187070f, + -0.326941668346621420f, + 0.944981812726528150f, -0.327122872352400510f, 0.944919070329589220f, + -0.327304064330806670f, + 0.944856293190677210f, -0.327485244275178000f, 0.944793481312100280f, + -0.327666412178853120f, + 0.944730634696167800f, -0.327847568035170840f, 0.944667753345190490f, + -0.328028711837470680f, + 0.944604837261480260f, -0.328209843579092500f, 0.944541886447350490f, + -0.328390963253376580f, + 0.944478900905115550f, -0.328572070853663740f, 0.944415880637091250f, + -0.328753166373294990f, + 0.944352825645594750f, -0.328934249805612200f, 0.944289735932944410f, + -0.329115321143957250f, + 0.944226611501459810f, -0.329296380381672750f, 0.944163452353461770f, + -0.329477427512101740f, + 0.944100258491272660f, -0.329658462528587490f, 0.944037029917215830f, + -0.329839485424473940f, + 0.943973766633615980f, -0.330020496193105420f, 0.943910468642799150f, + -0.330201494827826570f, + 0.943847135947092690f, -0.330382481321982780f, 0.943783768548825060f, + -0.330563455668919540f, + 0.943720366450326200f, -0.330744417861982890f, 0.943656929653927220f, + -0.330925367894519540f, + 0.943593458161960390f, -0.331106305759876430f, 0.943529951976759480f, + -0.331287231451400820f, + 0.943466411100659320f, -0.331468144962440870f, 0.943402835535996240f, + -0.331649046286344670f, + 0.943339225285107720f, -0.331829935416461110f, 0.943275580350332540f, + -0.332010812346139380f, + 0.943211900734010620f, -0.332191677068729150f, 0.943148186438483420f, + -0.332372529577580620f, + 0.943084437466093490f, -0.332553369866044220f, 0.943020653819184650f, + -0.332734197927471050f, + 0.942956835500102120f, -0.332915013755212650f, 0.942892982511192250f, + -0.333095817342620780f, + 0.942829094854802710f, -0.333276608683047930f, 0.942765172533282510f, + -0.333457387769846850f, + 0.942701215548981900f, -0.333638154596370860f, 0.942637223904252530f, + -0.333818909155973620f, + 0.942573197601446870f, -0.333999651442009380f, 0.942509136642919240f, + -0.334180381447832690f, + 0.942445041031024890f, -0.334361099166798740f, 0.942380910768120470f, + -0.334541804592262900f, + 0.942316745856563780f, -0.334722497717581220f, 0.942252546298714020f, + -0.334903178536110180f, + 0.942188312096931770f, -0.335083847041206580f, 0.942124043253578570f, + -0.335264503226227810f, + 0.942059739771017310f, -0.335445147084531600f, 0.941995401651612550f, + -0.335625778609476290f, + 0.941931028897729620f, -0.335806397794420450f, 0.941866621511735280f, + -0.335987004632723350f, + 0.941802179495997650f, -0.336167599117744520f, 0.941737702852886160f, + -0.336348181242844050f, + 0.941673191584771360f, -0.336528751001382410f, 0.941608645694025250f, + -0.336709308386720580f, + 0.941544065183020810f, -0.336889853392220050f, 0.941479450054132580f, + -0.337070386011242620f, + 0.941414800309736340f, -0.337250906237150590f, 0.941350115952208970f, + -0.337431414063306840f, + 0.941285396983928660f, -0.337611909483074620f, 0.941220643407275180f, + -0.337792392489817460f, + 0.941155855224629190f, -0.337972863076899720f, 0.941091032438372780f, + -0.338153321237685930f, + 0.941026175050889260f, -0.338333766965541130f, 0.940961283064563280f, + -0.338514200253830940f, + 0.940896356481780830f, -0.338694621095921190f, 0.940831395304928870f, + -0.338875029485178450f, + 0.940766399536396070f, -0.339055425414969640f, 0.940701369178571940f, + -0.339235808878661950f, + 0.940636304233847590f, -0.339416179869623360f, 0.940571204704615190f, + -0.339596538381222110f, + 0.940506070593268300f, -0.339776884406826850f, 0.940440901902201750f, + -0.339957217939806880f, + 0.940375698633811540f, -0.340137538973531720f, 0.940310460790495070f, + -0.340317847501371670f, + 0.940245188374650880f, -0.340498143516697160f, 0.940179881388678920f, + -0.340678427012879200f, + 0.940114539834980280f, -0.340858697983289440f, 0.940049163715957370f, + -0.341038956421299720f, + 0.939983753034014050f, -0.341219202320282360f, 0.939918307791555050f, + -0.341399435673610420f, + 0.939852827990986680f, -0.341579656474657160f, 0.939787313634716570f, + -0.341759864716796310f, + 0.939721764725153340f, -0.341940060393402190f, 0.939656181264707180f, + -0.342120243497849530f, + 0.939590563255789270f, -0.342300414023513520f, 0.939524910700812230f, + -0.342480571963769800f, + 0.939459223602189920f, -0.342660717311994380f, 0.939393501962337510f, + -0.342840850061563950f, + 0.939327745783671400f, -0.343020970205855540f, 0.939261955068609210f, + -0.343201077738246540f, + 0.939196129819569900f, -0.343381172652115040f, 0.939130270038973650f, + -0.343561254940839390f, + 0.939064375729241950f, -0.343741324597798490f, 0.938998446892797540f, + -0.343921381616371700f, + 0.938932483532064600f, -0.344101425989938810f, 0.938866485649468060f, + -0.344281457711880180f, + 0.938800453247434770f, -0.344461476775576540f, 0.938734386328392460f, + -0.344641483174408960f, + 0.938668284894770170f, -0.344821476901759290f, 0.938602148948998400f, + -0.345001457951009670f, + 0.938535978493508560f, -0.345181426315542550f, 0.938469773530733800f, + -0.345361381988741220f, + 0.938403534063108060f, -0.345541324963989090f, 0.938337260093066950f, + -0.345721255234670120f, + 0.938270951623047190f, -0.345901172794168990f, 0.938204608655486490f, + -0.346081077635870430f, + 0.938138231192824360f, -0.346260969753160010f, 0.938071819237501270f, + -0.346440849139423520f, + 0.938005372791958840f, -0.346620715788047320f, 0.937938891858640320f, + -0.346800569692418290f, + 0.937872376439989890f, -0.346980410845923680f, 0.937805826538453120f, + -0.347160239241951160f, + 0.937739242156476970f, -0.347340054873889140f, 0.937672623296509470f, + -0.347519857735126110f, + 0.937605969960999990f, -0.347699647819051380f, 0.937539282152399230f, + -0.347879425119054510f, + 0.937472559873159250f, -0.348059189628525610f, 0.937405803125732960f, + -0.348238941340855260f, + 0.937339011912574960f, -0.348418680249434560f, 0.937272186236140950f, + -0.348598406347654930f, + 0.937205326098887960f, -0.348778119628908420f, 0.937138431503274140f, + -0.348957820086587490f, + 0.937071502451759190f, -0.349137507714084970f, 0.937004538946803690f, + -0.349317182504794380f, + 0.936937540990869900f, -0.349496844452109550f, 0.936870508586420960f, + -0.349676493549424760f, + 0.936803441735921560f, -0.349856129790134920f, 0.936736340441837620f, + -0.350035753167635240f, + 0.936669204706636170f, -0.350215363675321580f, 0.936602034532785570f, + -0.350394961306590150f, + 0.936534829922755500f, -0.350574546054837510f, 0.936467590879016990f, + -0.350754117913461060f, + 0.936400317404042060f, -0.350933676875858360f, 0.936333009500304180f, + -0.351113222935427460f, + 0.936265667170278260f, -0.351292756085567090f, 0.936198290416440090f, + -0.351472276319676310f, + 0.936130879241267030f, -0.351651783631154570f, 0.936063433647237540f, + -0.351831278013402030f, + 0.935995953636831410f, -0.352010759459819080f, 0.935928439212529660f, + -0.352190227963806830f, + 0.935860890376814640f, -0.352369683518766630f, 0.935793307132169900f, + -0.352549126118100460f, + 0.935725689481080370f, -0.352728555755210730f, 0.935658037426032040f, + -0.352907972423500250f, + 0.935590350969512370f, -0.353087376116372480f, 0.935522630114009930f, + -0.353266766827231240f, + 0.935454874862014620f, -0.353446144549480810f, 0.935387085216017770f, + -0.353625509276525970f, + 0.935319261178511610f, -0.353804861001772050f, 0.935251402751989920f, + -0.353984199718624770f, + 0.935183509938947610f, -0.354163525420490340f, 0.935115582741880890f, + -0.354342838100775550f, + 0.935047621163287430f, -0.354522137752887430f, 0.934979625205665800f, + -0.354701424370233830f, + 0.934911594871516090f, -0.354880697946222790f, 0.934843530163339540f, + -0.355059958474262860f, + 0.934775431083638700f, -0.355239205947763310f, 0.934707297634917440f, + -0.355418440360133650f, + 0.934639129819680780f, -0.355597661704783850f, 0.934570927640435030f, + -0.355776869975124640f, + 0.934502691099687870f, -0.355956065164566850f, 0.934434420199948050f, + -0.356135247266522130f, + 0.934366114943725790f, -0.356314416274402410f, 0.934297775333532530f, + -0.356493572181620090f, + 0.934229401371880820f, -0.356672714981588260f, 0.934160993061284530f, + -0.356851844667720300f, + 0.934092550404258980f, -0.357030961233429980f, 0.934024073403320390f, + -0.357210064672131960f, + 0.933955562060986730f, -0.357389154977240940f, 0.933887016379776890f, + -0.357568232142172260f, + 0.933818436362210960f, -0.357747296160341900f, 0.933749822010810580f, + -0.357926347025166010f, + 0.933681173328098410f, -0.358105384730061590f, 0.933612490316598540f, + -0.358284409268445850f, + 0.933543772978836170f, -0.358463420633736540f, 0.933475021317337950f, + -0.358642418819351990f, + 0.933406235334631520f, -0.358821403818710860f, 0.933337415033246190f, + -0.359000375625232460f, + 0.933268560415712050f, -0.359179334232336500f, 0.933199671484560730f, + -0.359358279633443130f, + 0.933130748242325230f, -0.359537211821973070f, 0.933061790691539380f, + -0.359716130791347570f, + 0.932992798834738960f, -0.359895036534988110f, 0.932923772674460140f, + -0.360073929046317020f, + 0.932854712213241120f, -0.360252808318756890f, 0.932785617453621100f, + -0.360431674345730700f, + 0.932716488398140250f, -0.360610527120662270f, 0.932647325049340450f, + -0.360789366636975580f, + 0.932578127409764420f, -0.360968192888095230f, 0.932508895481956590f, + -0.361147005867446250f, + 0.932439629268462360f, -0.361325805568454280f, 0.932370328771828460f, + -0.361504591984545260f, + 0.932300993994602760f, -0.361683365109145840f, 0.932231624939334540f, + -0.361862124935682980f, + 0.932162221608574430f, -0.362040871457584180f, 0.932092784004874050f, + -0.362219604668277460f, + 0.932023312130786490f, -0.362398324561191310f, 0.931953805988866010f, + -0.362577031129754760f, + 0.931884265581668150f, -0.362755724367397230f, 0.931814690911749730f, + -0.362934404267548640f, + 0.931745081981668720f, -0.363113070823639470f, 0.931675438793984620f, + -0.363291724029100760f, + 0.931605761351257830f, -0.363470363877363760f, 0.931536049656050300f, + -0.363648990361860550f, + 0.931466303710925090f, -0.363827603476023500f, 0.931396523518446600f, + -0.364006203213285470f, + 0.931326709081180430f, -0.364184789567079890f, 0.931256860401693420f, + -0.364363362530840620f, + 0.931186977482553750f, -0.364541922098002120f, 0.931117060326330790f, + -0.364720468261999280f, + 0.931047108935595280f, -0.364899001016267320f, 0.930977123312918930f, + -0.365077520354242180f, + 0.930907103460875130f, -0.365256026269360320f, 0.930837049382038150f, + -0.365434518755058390f, + 0.930766961078983710f, -0.365612997804773850f, 0.930696838554288860f, + -0.365791463411944570f, + 0.930626681810531760f, -0.365969915570008740f, 0.930556490850291800f, + -0.366148354272405330f, + 0.930486265676149780f, -0.366326779512573590f, 0.930416006290687550f, + -0.366505191283953370f, + 0.930345712696488470f, -0.366683589579984930f, 0.930275384896137150f, + -0.366861974394109060f, + 0.930205022892219070f, -0.367040345719767180f, 0.930134626687321390f, + -0.367218703550400980f, + 0.930064196284032360f, -0.367397047879452710f, 0.929993731684941480f, + -0.367575378700365330f, + 0.929923232892639670f, -0.367753696006581980f, 0.929852699909718750f, + -0.367931999791546450f, + 0.929782132738772190f, -0.368110290048703050f, 0.929711531382394370f, + -0.368288566771496570f, + 0.929640895843181330f, -0.368466829953372320f, 0.929570226123729860f, + -0.368645079587776040f, + 0.929499522226638560f, -0.368823315668153910f, 0.929428784154506800f, + -0.369001538187952780f, + 0.929358011909935500f, -0.369179747140620020f, 0.929287205495526790f, + -0.369357942519603130f, + 0.929216364913884040f, -0.369536124318350650f, 0.929145490167611720f, + -0.369714292530311240f, + 0.929074581259315860f, -0.369892447148934100f, 0.929003638191603360f, + -0.370070588167669080f, + 0.928932660967082820f, -0.370248715579966360f, 0.928861649588363700f, + -0.370426829379276790f, + 0.928790604058057020f, -0.370604929559051670f, 0.928719524378774810f, + -0.370783016112742560f, + 0.928648410553130520f, -0.370961089033801980f, 0.928577262583738850f, + -0.371139148315682570f, + 0.928506080473215590f, -0.371317193951837540f, 0.928434864224177980f, + -0.371495225935720760f, + 0.928363613839244370f, -0.371673244260786520f, 0.928292329321034670f, + -0.371851248920489490f, + 0.928221010672169440f, -0.372029239908285010f, 0.928149657895271150f, + -0.372207217217628840f, + 0.928078270992963140f, -0.372385180841977360f, 0.928006849967869970f, + -0.372563130774787250f, + 0.927935394822617890f, -0.372741067009515760f, 0.927863905559833780f, + -0.372918989539620830f, + 0.927792382182146320f, -0.373096898358560640f, 0.927720824692185200f, + -0.373274793459793970f, + 0.927649233092581180f, -0.373452674836780300f, 0.927577607385966730f, + -0.373630542482979280f, + 0.927505947574975180f, -0.373808396391851210f, 0.927434253662241300f, + -0.373986236556857030f, + 0.927362525650401110f, -0.374164062971457930f, 0.927290763542091720f, + -0.374341875629115920f, + 0.927218967339951790f, -0.374519674523293210f, 0.927147137046620880f, + -0.374697459647452600f, + 0.927075272664740100f, -0.374875230995057540f, 0.927003374196951670f, + -0.375052988559571920f, + 0.926931441645899130f, -0.375230732334459920f, 0.926859475014227160f, + -0.375408462313186590f, + 0.926787474304581750f, -0.375586178489217220f, 0.926715439519610330f, + -0.375763880856017700f, + 0.926643370661961230f, -0.375941569407054420f, 0.926571267734284330f, + -0.376119244135794340f, + 0.926499130739230510f, -0.376296905035704790f, 0.926426959679452210f, + -0.376474552100253770f, + 0.926354754557602860f, -0.376652185322909560f, 0.926282515376337210f, + -0.376829804697141280f, + 0.926210242138311380f, -0.377007410216418260f, 0.926137934846182560f, + -0.377185001874210450f, + 0.926065593502609310f, -0.377362579663988340f, 0.925993218110251480f, + -0.377540143579222940f, + 0.925920808671770070f, -0.377717693613385640f, 0.925848365189827270f, + -0.377895229759948490f, + 0.925775887667086740f, -0.378072752012383990f, 0.925703376106213230f, + -0.378250260364165200f, + 0.925630830509872720f, -0.378427754808765560f, 0.925558250880732740f, + -0.378605235339659120f, + 0.925485637221461490f, -0.378782701950320540f, 0.925412989534729060f, + -0.378960154634224720f, + 0.925340307823206310f, -0.379137593384847320f, 0.925267592089565660f, + -0.379315018195664430f, + 0.925194842336480530f, -0.379492429060152630f, 0.925122058566625880f, + -0.379669825971788940f, + 0.925049240782677580f, -0.379847208924051160f, 0.924976388987313160f, + -0.380024577910417270f, + 0.924903503183210910f, -0.380201932924366050f, 0.924830583373050800f, + -0.380379273959376600f, + 0.924757629559513910f, -0.380556601008928520f, 0.924684641745282420f, + -0.380733914066502140f, + 0.924611619933039970f, -0.380911213125578070f, 0.924538564125471420f, + -0.381088498179637520f, + 0.924465474325262600f, -0.381265769222162380f, 0.924392350535101050f, + -0.381443026246634730f, + 0.924319192757675160f, -0.381620269246537360f, 0.924246000995674890f, + -0.381797498215353640f, + 0.924172775251791200f, -0.381974713146567220f, 0.924099515528716280f, + -0.382151914033662610f, + 0.924026221829143850f, -0.382329100870124510f, 0.923952894155768640f, + -0.382506273649438230f, + 0.923879532511286740f, -0.382683432365089780f, 0.923806136898395410f, + -0.382860577010565420f, + 0.923732707319793290f, -0.383037707579352020f, 0.923659243778179980f, + -0.383214824064937180f, + 0.923585746276256670f, -0.383391926460808660f, 0.923512214816725630f, + -0.383569014760454910f, + 0.923438649402290370f, -0.383746088957365010f, 0.923365050035655720f, + -0.383923149045028390f, + 0.923291416719527640f, -0.384100195016935040f, 0.923217749456613500f, + -0.384277226866575510f, + 0.923144048249621930f, -0.384454244587440820f, 0.923070313101262420f, + -0.384631248173022580f, + 0.922996544014246250f, -0.384808237616812880f, 0.922922740991285680f, + -0.384985212912304200f, + 0.922848904035094120f, -0.385162174052989860f, 0.922775033148386380f, + -0.385339121032363340f, + 0.922701128333878630f, -0.385516053843918850f, 0.922627189594287910f, + -0.385692972481151140f, + 0.922553216932332830f, -0.385869876937555310f, 0.922479210350733210f, + -0.386046767206627170f, + 0.922405169852209880f, -0.386223643281862980f, 0.922331095439485440f, + -0.386400505156759440f, + 0.922256987115283030f, -0.386577352824813920f, 0.922182844882327600f, + -0.386754186279524180f, + 0.922108668743345180f, -0.386931005514388580f, 0.922034458701062820f, + -0.387107810522905990f, + 0.921960214758209220f, -0.387284601298575840f, 0.921885936917513970f, + -0.387461377834897870f, + 0.921811625181708120f, -0.387638140125372730f, 0.921737279553523910f, + -0.387814888163501180f, + 0.921662900035694730f, -0.387991621942784860f, 0.921588486630955490f, + -0.388168341456725740f, + 0.921514039342042010f, -0.388345046698826250f, 0.921439558171691430f, + -0.388521737662589570f, + 0.921365043122642340f, -0.388698414341519190f, 0.921290494197634540f, + -0.388875076729119250f, + 0.921215911399408730f, -0.389051724818894380f, 0.921141294730707270f, + -0.389228358604349730f, + 0.921066644194273640f, -0.389404978078990940f, 0.920991959792852310f, + -0.389581583236324300f, + 0.920917241529189520f, -0.389758174069856410f, 0.920842489406032190f, + -0.389934750573094730f, + 0.920767703426128790f, -0.390111312739546910f, 0.920692883592229120f, + -0.390287860562721190f, + 0.920618029907083970f, -0.390464394036126590f, 0.920543142373445480f, + -0.390640913153272430f, + 0.920468220994067110f, -0.390817417907668500f, 0.920393265771703550f, + -0.390993908292825380f, + 0.920318276709110590f, -0.391170384302253870f, 0.920243253809045370f, + -0.391346845929465560f, + 0.920168197074266340f, -0.391523293167972410f, 0.920093106507533180f, + -0.391699726011286940f, + 0.920017982111606570f, -0.391876144452922350f, 0.919942823889248640f, + -0.392052548486392090f, + 0.919867631843222950f, -0.392228938105210310f, 0.919792405976293860f, + -0.392405313302891690f, + 0.919717146291227360f, -0.392581674072951470f, 0.919641852790790470f, + -0.392758020408905280f, + 0.919566525477751530f, -0.392934352304269490f, 0.919491164354880100f, + -0.393110669752560760f, + 0.919415769424947070f, -0.393286972747296400f, 0.919340340690724340f, + -0.393463261281994330f, + 0.919264878154985370f, -0.393639535350172880f, 0.919189381820504470f, + -0.393815794945351020f, + 0.919113851690057770f, -0.393992040061048100f, 0.919038287766422050f, + -0.394168270690784080f, + 0.918962690052375630f, -0.394344486828079600f, 0.918887058550697970f, + -0.394520688466455600f, + 0.918811393264170050f, -0.394696875599433560f, 0.918735694195573550f, + -0.394873048220535760f, + 0.918659961347691900f, -0.395049206323284770f, 0.918584194723309540f, + -0.395225349901203670f, + 0.918508394325212250f, -0.395401478947816350f, 0.918432560156186910f, + -0.395577593456646840f, + 0.918356692219021720f, -0.395753693421220080f, 0.918280790516506130f, + -0.395929778835061250f, + 0.918204855051430900f, -0.396105849691696270f, 0.918128885826588030f, + -0.396281905984651520f, + 0.918052882844770380f, -0.396457947707453910f, 0.917976846108772730f, + -0.396633974853630830f, + 0.917900775621390500f, -0.396809987416710310f, 0.917824671385420570f, + -0.396985985390220900f, + 0.917748533403661250f, -0.397161968767691610f, 0.917672361678911860f, + -0.397337937542652060f, + 0.917596156213972950f, -0.397513891708632330f, 0.917519917011646260f, + -0.397689831259163180f, + 0.917443644074735220f, -0.397865756187775750f, 0.917367337406043930f, + -0.398041666488001770f, + 0.917290997008377910f, -0.398217562153373560f, 0.917214622884544250f, + -0.398393443177423980f, + 0.917138215037350710f, -0.398569309553686300f, 0.917061773469606820f, + -0.398745161275694430f, + 0.916985298184123000f, -0.398920998336982910f, 0.916908789183710990f, + -0.399096820731086540f, + 0.916832246471183890f, -0.399272628451540990f, 0.916755670049355990f, + -0.399448421491882140f, + 0.916679059921042700f, -0.399624199845646790f, 0.916602416089060790f, + -0.399799963506371980f, + 0.916525738556228210f, -0.399975712467595330f, 0.916449027325364150f, + -0.400151446722855130f, + 0.916372282399289140f, -0.400327166265690090f, 0.916295503780824800f, + -0.400502871089639500f, + 0.916218691472794220f, -0.400678561188243240f, 0.916141845478021350f, + -0.400854236555041650f, + 0.916064965799331720f, -0.401029897183575620f, 0.915988052439551950f, + -0.401205543067386710f, + 0.915911105401509880f, -0.401381174200016790f, 0.915834124688034710f, + -0.401556790575008540f, + 0.915757110301956720f, -0.401732392185905010f, 0.915680062246107650f, + -0.401907979026249700f, + 0.915602980523320230f, -0.402083551089586990f, 0.915525865136428530f, + -0.402259108369461490f, + 0.915448716088267830f, -0.402434650859418430f, 0.915371533381674760f, + -0.402610178553003680f, + 0.915294317019487050f, -0.402785691443763530f, 0.915217067004543860f, + -0.402961189525244900f, + 0.915139783339685260f, -0.403136672790995300f, 0.915062466027752760f, + -0.403312141234562550f, + 0.914985115071589310f, -0.403487594849495310f, 0.914907730474038730f, + -0.403663033629342640f, + 0.914830312237946200f, -0.403838457567654070f, 0.914752860366158220f, + -0.404013866657979890f, + 0.914675374861522390f, -0.404189260893870690f, 0.914597855726887790f, + -0.404364640268877810f, + 0.914520302965104450f, -0.404540004776553000f, 0.914442716579023870f, + -0.404715354410448650f, + 0.914365096571498560f, -0.404890689164117580f, 0.914287442945382440f, + -0.405066009031113340f, + 0.914209755703530690f, -0.405241314004989860f, 0.914132034848799460f, + -0.405416604079301630f, + 0.914054280384046570f, -0.405591879247603870f, 0.913976492312130630f, + -0.405767139503452060f, + 0.913898670635911680f, -0.405942384840402510f, 0.913820815358251100f, + -0.406117615252011840f, + 0.913742926482011390f, -0.406292830731837360f, 0.913665004010056350f, + -0.406468031273437000f, + 0.913587047945250810f, -0.406643216870369030f, 0.913509058290461140f, + -0.406818387516192310f, + 0.913431035048554720f, -0.406993543204466510f, 0.913352978222400250f, + -0.407168683928751550f, + 0.913274887814867760f, -0.407343809682607970f, 0.913196763828828200f, + -0.407518920459596920f, + 0.913118606267154240f, -0.407694016253280110f, 0.913040415132719160f, + -0.407869097057219800f, + 0.912962190428398210f, -0.408044162864978690f, 0.912883932157067200f, + -0.408219213670120100f, + 0.912805640321603500f, -0.408394249466208000f, 0.912727314924885900f, + -0.408569270246806780f, + 0.912648955969793900f, -0.408744276005481360f, 0.912570563459208730f, + -0.408919266735797430f, + 0.912492137396012650f, -0.409094242431320980f, 0.912413677783089020f, + -0.409269203085618590f, + 0.912335184623322750f, -0.409444148692257590f, 0.912256657919599760f, + -0.409619079244805670f, + 0.912178097674807180f, -0.409793994736831150f, 0.912099503891833470f, + -0.409968895161902880f, + 0.912020876573568340f, -0.410143780513590240f, 0.911942215722902570f, + -0.410318650785463260f, + 0.911863521342728520f, -0.410493505971092410f, 0.911784793435939430f, + -0.410668346064048730f, + 0.911706032005429880f, -0.410843171057903910f, 0.911627237054095650f, + -0.411017980946230210f, + 0.911548408584833990f, -0.411192775722600160f, 0.911469546600543020f, + -0.411367555380587220f, + 0.911390651104122430f, -0.411542319913765220f, 0.911311722098472780f, + -0.411717069315708560f, + 0.911232759586496190f, -0.411891803579992170f, 0.911153763571095900f, + -0.412066522700191560f, + 0.911074734055176360f, -0.412241226669882890f, 0.910995671041643140f, + -0.412415915482642730f, + 0.910916574533403360f, -0.412590589132048210f, 0.910837444533365010f, + -0.412765247611677270f, + 0.910758281044437570f, -0.412939890915108080f, 0.910679084069531570f, + -0.413114519035919450f, + 0.910599853611558930f, -0.413289131967690960f, 0.910520589673432750f, + -0.413463729704002410f, + 0.910441292258067250f, -0.413638312238434500f, 0.910361961368377990f, + -0.413812879564568300f, + 0.910282597007281760f, -0.413987431675985400f, 0.910203199177696540f, + -0.414161968566268080f, + 0.910123767882541680f, -0.414336490228999100f, 0.910044303124737500f, + -0.414510996657761750f, + 0.909964804907205660f, -0.414685487846140010f, 0.909885273232869160f, + -0.414859963787718330f, + 0.909805708104652220f, -0.415034424476081630f, 0.909726109525480160f, + -0.415208869904815590f, + 0.909646477498279540f, -0.415383300067506230f, 0.909566812025978330f, + -0.415557714957740410f, + 0.909487113111505430f, -0.415732114569105360f, 0.909407380757791260f, + -0.415906498895188770f, + 0.909327614967767260f, -0.416080867929579210f, 0.909247815744366310f, + -0.416255221665865480f, + 0.909167983090522380f, -0.416429560097637150f, 0.909088117009170580f, + -0.416603883218484350f, + 0.909008217503247450f, -0.416778191021997650f, 0.908928284575690640f, + -0.416952483501768170f, + 0.908848318229439120f, -0.417126760651387870f, 0.908768318467432890f, + -0.417301022464448890f, + 0.908688285292613360f, -0.417475268934544290f, 0.908608218707923190f, + -0.417649500055267410f, + 0.908528118716306120f, -0.417823715820212270f, 0.908447985320707250f, + -0.417997916222973550f, + 0.908367818524072890f, -0.418172101257146320f, 0.908287618329350450f, + -0.418346270916326260f, + 0.908207384739488700f, -0.418520425194109700f, 0.908127117757437600f, + -0.418694564084093560f, + 0.908046817386148340f, -0.418868687579875050f, 0.907966483628573350f, + -0.419042795675052370f, + 0.907886116487666260f, -0.419216888363223910f, 0.907805715966381930f, + -0.419390965637988890f, + 0.907725282067676440f, -0.419565027492946880f, 0.907644814794507200f, + -0.419739073921698180f, + 0.907564314149832630f, -0.419913104917843620f, 0.907483780136612570f, + -0.420087120474984530f, + 0.907403212757808110f, -0.420261120586722880f, 0.907322612016381420f, + -0.420435105246661170f, + 0.907241977915295820f, -0.420609074448402510f, 0.907161310457516250f, + -0.420783028185550520f, + 0.907080609646008450f, -0.420956966451709440f, 0.906999875483739610f, + -0.421130889240483970f, + 0.906919107973678140f, -0.421304796545479640f, 0.906838307118793430f, + -0.421478688360302280f, + 0.906757472922056550f, -0.421652564678558330f, 0.906676605386439460f, + -0.421826425493854910f, + 0.906595704514915330f, -0.422000270799799680f, 0.906514770310458800f, + -0.422174100590000770f, + 0.906433802776045460f, -0.422347914858067050f, 0.906352801914652400f, + -0.422521713597607820f, + 0.906271767729257660f, -0.422695496802232950f, 0.906190700222840650f, + -0.422869264465553060f, + 0.906109599398381980f, -0.423043016581179040f, 0.906028465258863600f, + -0.423216753142722610f, + 0.905947297807268460f, -0.423390474143796050f, 0.905866097046580940f, + -0.423564179578011960f, + 0.905784862979786550f, -0.423737869438983840f, 0.905703595609872010f, + -0.423911543720325580f, + 0.905622294939825270f, -0.424085202415651560f, 0.905540960972635590f, + -0.424258845518576950f, + 0.905459593711293250f, -0.424432473022717420f, 0.905378193158790090f, + -0.424606084921689110f, + 0.905296759318118820f, -0.424779681209108810f, 0.905215292192273590f, + -0.424953261878593890f, + 0.905133791784249690f, -0.425126826923762360f, 0.905052258097043590f, + -0.425300376338232640f, + 0.904970691133653250f, -0.425473910115623800f, 0.904889090897077470f, + -0.425647428249555590f, + 0.904807457390316540f, -0.425820930733648240f, 0.904725790616371930f, + -0.425994417561522400f, + 0.904644090578246240f, -0.426167888726799620f, 0.904562357278943300f, + -0.426341344223101830f, + 0.904480590721468250f, -0.426514784044051520f, 0.904398790908827350f, + -0.426688208183271860f, + 0.904316957844028320f, -0.426861616634386430f, 0.904235091530079750f, + -0.427035009391019680f, + 0.904153191969991780f, -0.427208386446796320f, 0.904071259166775440f, + -0.427381747795341770f, + 0.903989293123443340f, -0.427555093430282080f, 0.903907293843009050f, + -0.427728423345243800f, + 0.903825261328487510f, -0.427901737533854080f, 0.903743195582894620f, + -0.428075035989740730f, + 0.903661096609247980f, -0.428248318706531960f, 0.903578964410566070f, + -0.428421585677856650f, + 0.903496798989868450f, -0.428594836897344400f, 0.903414600350176290f, + -0.428768072358625070f, + 0.903332368494511820f, -0.428941292055329490f, 0.903250103425898400f, + -0.429114495981088750f, + 0.903167805147360720f, -0.429287684129534610f, 0.903085473661924600f, + -0.429460856494299490f, + 0.903003108972617150f, -0.429634013069016380f, 0.902920711082466740f, + -0.429807153847318710f, + 0.902838279994502830f, -0.429980278822840620f, 0.902755815711756120f, + -0.430153387989216870f, + 0.902673318237258830f, -0.430326481340082610f, 0.902590787574043870f, + -0.430499558869073820f, + 0.902508223725145940f, -0.430672620569826800f, 0.902425626693600380f, + -0.430845666435978660f, + 0.902342996482444200f, -0.431018696461167030f, 0.902260333094715540f, + -0.431191710639029950f, + 0.902177636533453620f, -0.431364708963206330f, 0.902094906801698900f, + -0.431537691427335500f, + 0.902012143902493180f, -0.431710658025057260f, 0.901929347838879460f, + -0.431883608750012250f, + 0.901846518613901750f, -0.432056543595841500f, 0.901763656230605730f, + -0.432229462556186720f, + 0.901680760692037730f, -0.432402365624690140f, 0.901597832001245660f, + -0.432575252794994650f, + 0.901514870161278740f, -0.432748124060743700f, 0.901431875175186970f, + -0.432920979415581280f, + 0.901348847046022030f, -0.433093818853151960f, 0.901265785776836580f, + -0.433266642367100940f, + 0.901182691370684520f, -0.433439449951074090f, 0.901099563830620950f, + -0.433612241598717580f, + 0.901016403159702330f, -0.433785017303678520f, 0.900933209360986200f, + -0.433957777059604420f, + 0.900849982437531450f, -0.434130520860143310f, 0.900766722392397860f, + -0.434303248698943990f, + 0.900683429228646970f, -0.434475960569655650f, 0.900600102949340900f, + -0.434648656465928320f, + 0.900516743557543520f, -0.434821336381412290f, 0.900433351056319830f, + -0.434994000309758710f, + 0.900349925448735600f, -0.435166648244619260f, 0.900266466737858480f, + -0.435339280179646070f, + 0.900182974926756810f, -0.435511896108492000f, 0.900099450018500450f, + -0.435684496024810460f, + 0.900015892016160280f, -0.435857079922255470f, 0.899932300922808510f, + -0.436029647794481560f, + 0.899848676741518580f, -0.436202199635143950f, 0.899765019475365140f, + -0.436374735437898340f, + 0.899681329127423930f, -0.436547255196401200f, 0.899597605700772180f, + -0.436719758904309360f, + 0.899513849198487980f, -0.436892246555280360f, 0.899430059623650860f, + -0.437064718142972370f, + 0.899346236979341570f, -0.437237173661044090f, 0.899262381268642000f, + -0.437409613103154790f, + 0.899178492494635330f, -0.437582036462964400f, 0.899094570660405770f, + -0.437754443734133410f, + 0.899010615769039070f, -0.437926834910322860f, 0.898926627823621870f, + -0.438099209985194470f, + 0.898842606827242370f, -0.438271568952410430f, 0.898758552782989440f, + -0.438443911805633690f, + 0.898674465693953820f, -0.438616238538527660f, 0.898590345563227030f, + -0.438788549144756290f, + 0.898506192393901950f, -0.438960843617984320f, 0.898422006189072530f, + -0.439133121951876930f, + 0.898337786951834310f, -0.439305384140099950f, 0.898253534685283570f, + -0.439477630176319800f, + 0.898169249392518080f, -0.439649860054203480f, 0.898084931076636780f, + -0.439822073767418500f, + 0.898000579740739880f, -0.439994271309633260f, 0.897916195387928660f, + -0.440166452674516320f, + 0.897831778021305650f, -0.440338617855737250f, 0.897747327643974690f, + -0.440510766846965940f, + 0.897662844259040860f, -0.440682899641872900f, 0.897578327869610230f, + -0.440855016234129430f, + 0.897493778478790310f, -0.441027116617407230f, 0.897409196089689720f, + -0.441199200785378660f, + 0.897324580705418320f, -0.441371268731716670f, 0.897239932329087160f, + -0.441543320450094870f, + 0.897155250963808550f, -0.441715355934187310f, 0.897070536612695870f, + -0.441887375177668850f, + 0.896985789278863970f, -0.442059378174214700f, 0.896901008965428790f, + -0.442231364917500980f, + 0.896816195675507300f, -0.442403335401204080f, 0.896731349412217880f, + -0.442575289619001170f, + 0.896646470178680150f, -0.442747227564570020f, 0.896561557978014960f, + -0.442919149231588980f, + 0.896476612813344120f, -0.443091054613736880f, 0.896391634687790820f, + -0.443262943704693320f, + 0.896306623604479550f, -0.443434816498138480f, 0.896221579566536030f, + -0.443606672987752970f, + 0.896136502577086770f, -0.443778513167218220f, 0.896051392639260150f, + -0.443950337030216140f, + 0.895966249756185220f, -0.444122144570429200f, 0.895881073930992370f, + -0.444293935781540580f, + 0.895795865166813530f, -0.444465710657234000f, 0.895710623466781320f, + -0.444637469191193790f, + 0.895625348834030110f, -0.444809211377104880f, 0.895540041271694950f, + -0.444980937208652730f, + 0.895454700782912450f, -0.445152646679523640f, 0.895369327370820310f, + -0.445324339783404190f, + 0.895283921038557580f, -0.445496016513981740f, 0.895198481789264200f, + -0.445667676864944300f, + 0.895113009626081760f, -0.445839320829980290f, 0.895027504552152630f, + -0.446010948402778940f, + 0.894941966570620750f, -0.446182559577030070f, 0.894856395684631050f, + -0.446354154346423840f, + 0.894770791897329550f, -0.446525732704651350f, 0.894685155211863980f, + -0.446697294645404090f, + 0.894599485631382700f, -0.446868840162374160f, 0.894513783159035620f, + -0.447040369249254440f, + 0.894428047797973800f, -0.447211881899738320f, 0.894342279551349480f, + -0.447383378107519600f, + 0.894256478422316040f, -0.447554857866293010f, 0.894170644414028270f, + -0.447726321169753580f, + 0.894084777529641990f, -0.447897768011597310f, 0.893998877772314240f, + -0.448069198385520400f, + 0.893912945145203250f, -0.448240612285219890f, 0.893826979651468620f, + -0.448412009704393430f, + 0.893740981294271040f, -0.448583390636739240f, 0.893654950076772540f, + -0.448754755075955970f, + 0.893568886002135910f, -0.448926103015743260f, 0.893482789073525850f, + -0.449097434449801050f, + 0.893396659294107720f, -0.449268749371829920f, 0.893310496667048200f, + -0.449440047775531150f, + 0.893224301195515320f, -0.449611329654606540f, 0.893138072882678320f, + -0.449782595002758690f, + 0.893051811731707450f, -0.449953843813690520f, 0.892965517745774370f, + -0.450125076081105690f, + 0.892879190928051680f, -0.450296291798708610f, 0.892792831281713610f, + -0.450467490960204110f, + 0.892706438809935390f, -0.450638673559297600f, 0.892620013515893150f, + -0.450809839589695280f, + 0.892533555402764580f, -0.450980989045103860f, 0.892447064473728680f, + -0.451152121919230600f, + 0.892360540731965360f, -0.451323238205783520f, 0.892273984180655840f, + -0.451494337898471100f, + 0.892187394822982480f, -0.451665420991002490f, 0.892100772662129060f, + -0.451836487477087490f, + 0.892014117701280470f, -0.452007537350436420f, 0.891927429943622510f, + -0.452178570604760350f, + 0.891840709392342720f, -0.452349587233770890f, 0.891753956050629460f, + -0.452520587231180050f, + 0.891667169921672280f, -0.452691570590700920f, 0.891580351008662290f, + -0.452862537306046750f, + 0.891493499314791380f, -0.453033487370931580f, 0.891406614843252900f, + -0.453204420779070190f, + 0.891319697597241390f, -0.453375337524177750f, 0.891232747579952520f, + -0.453546237599970090f, + 0.891145764794583180f, -0.453717121000163870f, 0.891058749244331590f, + -0.453887987718476050f, + 0.890971700932396860f, -0.454058837748624430f, 0.890884619861979530f, + -0.454229671084327320f, + 0.890797506036281490f, -0.454400487719303580f, 0.890710359458505630f, + -0.454571287647272950f, + 0.890623180131855930f, -0.454742070861955450f, 0.890535968059537830f, + -0.454912837357071940f, + 0.890448723244757880f, -0.455083587126343840f, 0.890361445690723840f, + -0.455254320163493100f, + 0.890274135400644600f, -0.455425036462242360f, 0.890186792377730240f, + -0.455595736016314980f, + 0.890099416625192320f, -0.455766418819434640f, 0.890012008146243260f, + -0.455937084865326030f, + 0.889924566944096720f, -0.456107734147714110f, 0.889837093021967900f, + -0.456278366660324620f, + 0.889749586383072780f, -0.456448982396883920f, 0.889662047030628900f, + -0.456619581351118910f, + 0.889574474967854580f, -0.456790163516757160f, 0.889486870197969900f, + -0.456960728887526980f, + 0.889399232724195520f, -0.457131277457156980f, 0.889311562549753850f, + -0.457301809219376630f, + 0.889223859677868210f, -0.457472324167916060f, 0.889136124111763240f, + -0.457642822296505770f, + 0.889048355854664570f, -0.457813303598877170f, 0.888960554909799310f, + -0.457983768068762120f, + 0.888872721280395630f, -0.458154215699893060f, 0.888784854969682850f, + -0.458324646486003240f, + 0.888696955980891600f, -0.458495060420826270f, 0.888609024317253860f, + -0.458665457498096560f, + 0.888521059982002260f, -0.458835837711549120f, 0.888433062978371320f, + -0.459006201054919630f, + 0.888345033309596350f, -0.459176547521944090f, 0.888256970978913870f, + -0.459346877106359630f, + 0.888168875989561730f, -0.459517189801903480f, 0.888080748344778900f, + -0.459687485602313870f, + 0.887992588047805560f, -0.459857764501329540f, 0.887904395101883240f, + -0.460028026492689650f, + 0.887816169510254440f, -0.460198271570134320f, 0.887727911276163020f, + -0.460368499727404010f, + 0.887639620402853930f, -0.460538710958240010f, 0.887551296893573370f, + -0.460708905256384080f, + 0.887462940751568840f, -0.460879082615578690f, 0.887374551980088850f, + -0.461049243029566900f, + 0.887286130582383150f, -0.461219386492092380f, 0.887197676561702900f, + -0.461389512996899450f, + 0.887109189921300170f, -0.461559622537733080f, 0.887020670664428360f, + -0.461729715108338770f, + 0.886932118794342190f, -0.461899790702462730f, 0.886843534314297410f, + -0.462069849313851750f, + 0.886754917227550840f, -0.462239890936253340f, 0.886666267537361000f, + -0.462409915563415430f, + 0.886577585246987040f, -0.462579923189086810f, 0.886488870359689600f, + -0.462749913807016740f, + 0.886400122878730600f, -0.462919887410955080f, 0.886311342807372780f, + -0.463089843994652530f, + 0.886222530148880640f, -0.463259783551860150f, 0.886133684906519340f, + -0.463429706076329830f, + 0.886044807083555600f, -0.463599611561814010f, 0.885955896683257030f, + -0.463769500002065630f, + 0.885866953708892790f, -0.463939371390838520f, 0.885777978163732940f, + -0.464109225721886950f, + 0.885688970051048960f, -0.464279062988965760f, 0.885599929374113360f, + -0.464448883185830660f, + 0.885510856136199950f, -0.464618686306237820f, 0.885421750340583680f, + -0.464788472343943990f, + 0.885332611990540590f, -0.464958241292706690f, 0.885243441089348270f, + -0.465127993146283950f, + 0.885154237640285110f, -0.465297727898434600f, 0.885065001646630930f, + -0.465467445542917800f, + 0.884975733111666660f, -0.465637146073493660f, 0.884886432038674560f, + -0.465806829483922710f, + 0.884797098430937790f, -0.465976495767966180f, 0.884707732291741040f, + -0.466146144919385890f, + 0.884618333624369920f, -0.466315776931944430f, 0.884528902432111460f, + -0.466485391799404900f, + 0.884439438718253810f, -0.466654989515530920f, 0.884349942486086120f, + -0.466824570074086950f, + 0.884260413738899190f, -0.466994133468838000f, 0.884170852479984500f, + -0.467163679693549770f, + 0.884081258712634990f, -0.467333208741988420f, 0.883991632440144890f, + -0.467502720607920920f, + 0.883901973665809470f, -0.467672215285114770f, 0.883812282392925090f, + -0.467841692767338170f, + 0.883722558624789660f, -0.468011153048359830f, 0.883632802364701870f, + -0.468180596121949290f, + 0.883543013615961880f, -0.468350021981876530f, 0.883453192381870920f, + -0.468519430621912310f, + 0.883363338665731580f, -0.468688822035827900f, 0.883273452470847430f, + -0.468858196217395330f, + 0.883183533800523390f, -0.469027553160387130f, 0.883093582658065370f, + -0.469196892858576580f, + 0.883003599046780830f, -0.469366215305737520f, 0.882913582969978020f, + -0.469535520495644450f, + 0.882823534430966620f, -0.469704808422072460f, 0.882733453433057650f, + -0.469874079078797360f, + 0.882643339979562790f, -0.470043332459595620f, 0.882553194073795510f, + -0.470212568558244170f, + 0.882463015719070150f, -0.470381787368520650f, 0.882372804918702290f, + -0.470550988884203550f, + 0.882282561676008710f, -0.470720173099071600f, 0.882192285994307430f, + -0.470889340006904520f, + 0.882101977876917580f, -0.471058489601482500f, 0.882011637327159590f, + -0.471227621876586340f, + 0.881921264348355050f, -0.471396736825997640f, 0.881830858943826620f, + -0.471565834443498420f, + 0.881740421116898320f, -0.471734914722871430f, 0.881649950870895260f, + -0.471903977657900210f, + 0.881559448209143780f, -0.472073023242368660f, 0.881468913134971440f, + -0.472242051470061490f, + 0.881378345651706920f, -0.472411062334764040f, 0.881287745762680100f, + -0.472580055830262250f, + 0.881197113471222090f, -0.472749031950342790f, 0.881106448780665130f, + -0.472917990688792760f, + 0.881015751694342870f, -0.473086932039400050f, 0.880925022215589880f, + -0.473255855995953320f, + 0.880834260347742040f, -0.473424762552241530f, 0.880743466094136340f, + -0.473593651702054530f, + 0.880652639458111010f, -0.473762523439182850f, 0.880561780443005700f, + -0.473931377757417450f, + 0.880470889052160750f, -0.474100214650549970f, 0.880379965288918150f, + -0.474269034112372980f, + 0.880289009156621010f, -0.474437836136679230f, 0.880198020658613190f, + -0.474606620717262560f, + 0.880106999798240360f, -0.474775387847917120f, 0.880015946578849070f, + -0.474944137522437800f, + 0.879924861003786860f, -0.475112869734620300f, 0.879833743076402940f, + -0.475281584478260740f, + 0.879742592800047410f, -0.475450281747155870f, 0.879651410178071580f, + -0.475618961535103300f, + 0.879560195213827890f, -0.475787623835901120f, 0.879468947910670210f, + -0.475956268643348060f, + 0.879377668271953290f, -0.476124895951243580f, 0.879286356301033250f, + -0.476293505753387690f, + 0.879195012001267480f, -0.476462098043581190f, 0.879103635376014330f, + -0.476630672815625320f, + 0.879012226428633530f, -0.476799230063322090f, 0.878920785162485840f, + -0.476967769780474170f, + 0.878829311580933360f, -0.477136291960884810f, 0.878737805687339390f, + -0.477304796598357890f, + 0.878646267485068130f, -0.477473283686698060f, 0.878554696977485450f, + -0.477641753219710470f, + 0.878463094167957870f, -0.477810205191200990f, 0.878371459059853480f, + -0.477978639594976160f, + 0.878279791656541580f, -0.478147056424843010f, 0.878188091961392250f, + -0.478315455674609480f, + 0.878096359977777130f, -0.478483837338083970f, 0.878004595709069080f, + -0.478652201409075500f, + 0.877912799158641840f, -0.478820547881393890f, 0.877820970329870500f, + -0.478988876748849490f, + 0.877729109226131570f, -0.479157188005253310f, 0.877637215850802230f, + -0.479325481644417070f, + 0.877545290207261350f, -0.479493757660153010f, 0.877453332298888560f, + -0.479662016046274180f, + 0.877361342129065140f, -0.479830256796594190f, 0.877269319701173170f, + -0.479998479904927280f, + 0.877177265018595940f, -0.480166685365088390f, 0.877085178084718420f, + -0.480334873170893020f, + 0.876993058902925890f, -0.480503043316157510f, 0.876900907476605650f, + -0.480671195794698640f, + 0.876808723809145650f, -0.480839330600333960f, 0.876716507903935400f, + -0.481007447726881590f, + 0.876624259764365310f, -0.481175547168160300f, 0.876531979393827100f, + -0.481343628917989710f, + 0.876439666795713610f, -0.481511692970189860f, 0.876347321973419020f, + -0.481679739318581490f, + 0.876254944930338510f, -0.481847767956986030f, 0.876162535669868460f, + -0.482015778879225590f, + 0.876070094195406600f, -0.482183772079122720f, 0.875977620510351770f, + -0.482351747550500980f, + 0.875885114618103810f, -0.482519705287184350f, 0.875792576522063880f, + -0.482687645282997460f, + 0.875700006225634600f, -0.482855567531765670f, 0.875607403732219350f, + -0.483023472027314880f, + 0.875514769045222850f, -0.483191358763471860f, 0.875422102168050940f, + -0.483359227734063810f, + 0.875329403104110890f, -0.483527078932918740f, 0.875236671856810870f, + -0.483694912353865140f, + 0.875143908429560360f, -0.483862727990732270f, 0.875051112825769970f, + -0.484030525837350010f, + 0.874958285048851650f, -0.484198305887549030f, 0.874865425102218320f, + -0.484366068135160420f, + 0.874772532989284150f, -0.484533812574016180f, 0.874679608713464510f, + -0.484701539197948670f, + 0.874586652278176110f, -0.484869248000791060f, 0.874493663686836560f, + -0.485036938976377290f, + 0.874400642942864790f, -0.485204612118541820f, 0.874307590049680950f, + -0.485372267421119770f, + 0.874214505010706300f, -0.485539904877946960f, 0.874121387829363330f, + -0.485707524482859750f, + 0.874028238509075740f, -0.485875126229695250f, 0.873935057053268240f, + -0.486042710112291330f, + 0.873841843465366860f, -0.486210276124486420f, 0.873748597748798870f, + -0.486377824260119440f, + 0.873655319906992630f, -0.486545354513030270f, 0.873562009943377850f, + -0.486712866877059170f, + 0.873468667861384880f, -0.486880361346047340f, 0.873375293664446000f, + -0.487047837913836380f, + 0.873281887355994210f, -0.487215296574268760f, 0.873188448939463790f, + -0.487382737321187360f, + 0.873094978418290090f, -0.487550160148436000f, 0.873001475795909920f, + -0.487717565049858800f, + 0.872907941075761080f, -0.487884952019301040f, 0.872814374261282390f, + -0.488052321050608250f, + 0.872720775355914300f, -0.488219672137626790f, 0.872627144363097960f, + -0.488387005274203530f, + 0.872533481286276170f, -0.488554320454186180f, 0.872439786128892280f, + -0.488721617671423080f, + 0.872346058894391540f, -0.488888896919763170f, 0.872252299586219860f, + -0.489056158193056030f, + 0.872158508207824480f, -0.489223401485151980f, 0.872064684762653860f, + -0.489390626789901920f, + 0.871970829254157810f, -0.489557834101157440f, 0.871876941685786890f, + -0.489725023412770910f, + 0.871783022060993120f, -0.489892194718595190f, 0.871689070383229740f, + -0.490059348012483850f, + 0.871595086655950980f, -0.490226483288291160f, 0.871501070882612530f, + -0.490393600539871970f, + 0.871407023066670950f, -0.490560699761082020f, 0.871312943211584030f, + -0.490727780945777400f, + 0.871218831320811020f, -0.490894844087815090f, 0.871124687397811900f, + -0.491061889181052650f, + 0.871030511446048260f, -0.491228916219348280f, 0.870936303468982760f, + -0.491395925196560780f, + 0.870842063470078980f, -0.491562916106549900f, 0.870747791452801790f, + -0.491729888943175760f, + 0.870653487420617430f, -0.491896843700299290f, 0.870559151376993250f, + -0.492063780371782000f, + 0.870464783325397670f, -0.492230698951486020f, 0.870370383269300270f, + -0.492397599433274380f, + 0.870275951212171940f, -0.492564481811010590f, 0.870181487157484560f, + -0.492731346078558840f, + 0.870086991108711460f, -0.492898192229784040f, 0.869992463069326870f, + -0.493065020258551700f, + 0.869897903042806340f, -0.493231830158727900f, 0.869803311032626650f, + -0.493398621924179770f, + 0.869708687042265670f, -0.493565395548774770f, 0.869614031075202300f, + -0.493732151026381020f, + 0.869519343134916860f, -0.493898888350867480f, 0.869424623224890890f, + -0.494065607516103570f, + 0.869329871348606840f, -0.494232308515959670f, 0.869235087509548370f, + -0.494398991344306650f, + 0.869140271711200560f, -0.494565655995015950f, 0.869045423957049530f, + -0.494732302461959870f, + 0.868950544250582380f, -0.494898930739011260f, 0.868855632595287860f, + -0.495065540820043560f, + 0.868760688994655310f, -0.495232132698931180f, 0.868665713452175690f, + -0.495398706369549020f, + 0.868570705971340900f, -0.495565261825772540f, 0.868475666555644120f, + -0.495731799061477960f, + 0.868380595208579800f, -0.495898318070542190f, 0.868285491933643350f, + -0.496064818846842890f, + 0.868190356734331310f, -0.496231301384258250f, 0.868095189614141670f, + -0.496397765676667160f, + 0.867999990576573510f, -0.496564211717949290f, 0.867904759625126920f, + -0.496730639501984760f, + 0.867809496763303320f, -0.496897049022654470f, 0.867714201994605140f, + -0.497063440273840250f, + 0.867618875322536230f, -0.497229813249424220f, 0.867523516750601460f, + -0.497396167943289280f, + 0.867428126282306920f, -0.497562504349319150f, 0.867332703921159800f, + -0.497728822461397940f, + 0.867237249670668400f, -0.497895122273410870f, 0.867141763534342470f, + -0.498061403779243410f, + 0.867046245515692650f, -0.498227666972781870f, 0.866950695618230900f, + -0.498393911847913210f, + 0.866855113845470430f, -0.498560138398525140f, 0.866759500200925400f, + -0.498726346618505900f, + 0.866663854688111130f, -0.498892536501744590f, 0.866568177310544470f, + -0.499058708042130870f, + 0.866472468071743050f, -0.499224861233555080f, 0.866376726975225830f, + -0.499390996069908170f, + 0.866280954024512990f, -0.499557112545081840f, 0.866185149223125840f, + -0.499723210652968540f, + 0.866089312574586770f, -0.499889290387461330f, 0.865993444082419520f, + -0.500055351742453860f, + 0.865897543750148820f, -0.500221394711840680f, 0.865801611581300760f, + -0.500387419289516580f, + 0.865705647579402380f, -0.500553425469377420f, 0.865609651747981990f, + -0.500719413245319880f, + 0.865513624090569090f, -0.500885382611240710f, 0.865417564610694410f, + -0.501051333561038040f, + 0.865321473311889800f, -0.501217266088609950f, 0.865225350197688200f, + -0.501383180187855770f, + 0.865129195271623800f, -0.501549075852675390f, 0.865033008537231860f, + -0.501714953076969120f, + 0.864936789998049020f, -0.501880811854638290f, 0.864840539657612870f, + -0.502046652179584660f, + 0.864744257519462380f, -0.502212474045710790f, 0.864647943587137480f, + -0.502378277446919760f, + 0.864551597864179340f, -0.502544062377115690f, 0.864455220354130360f, + -0.502709828830202990f, + 0.864358811060534030f, -0.502875576800086990f, 0.864262369986934950f, + -0.503041306280673450f, + 0.864165897136879300f, -0.503207017265868920f, 0.864069392513913790f, + -0.503372709749581040f, + 0.863972856121586810f, -0.503538383725717580f, 0.863876287963447510f, + -0.503704039188187070f, + 0.863779688043046720f, -0.503869676130898950f, 0.863683056363935830f, + -0.504035294547763190f, + 0.863586392929668100f, -0.504200894432690340f, 0.863489697743797140f, + -0.504366475779592040f, + 0.863392970809878420f, -0.504532038582380270f, 0.863296212131468230f, + -0.504697582834967570f, + 0.863199421712124160f, -0.504863108531267590f, 0.863102599555404910f, + -0.505028615665194080f, + 0.863005745664870320f, -0.505194104230662240f, 0.862908860044081400f, + -0.505359574221587280f, + 0.862811942696600330f, -0.505525025631885390f, 0.862714993625990690f, + -0.505690458455473450f, + 0.862618012835816740f, -0.505855872686268860f, 0.862521000329644520f, + -0.506021268318189720f, + 0.862423956111040610f, -0.506186645345155230f, 0.862326880183573060f, + -0.506352003761084800f, + 0.862229772550811240f, -0.506517343559898530f, 0.862132633216325380f, + -0.506682664735517600f, + 0.862035462183687210f, -0.506847967281863210f, 0.861938259456469290f, + -0.507013251192858230f, + 0.861841025038245330f, -0.507178516462425180f, 0.861743758932590700f, + -0.507343763084487920f, + 0.861646461143081300f, -0.507508991052970870f, 0.861549131673294720f, + -0.507674200361798890f, + 0.861451770526809320f, -0.507839391004897720f, 0.861354377707204910f, + -0.508004562976194010f, + 0.861256953218062170f, -0.508169716269614600f, 0.861159497062963350f, + -0.508334850879087360f, + 0.861062009245491480f, -0.508499966798540930f, 0.860964489769231010f, + -0.508665064021904030f, + 0.860866938637767310f, -0.508830142543106990f, 0.860769355854687170f, + -0.508995202356080090f, + 0.860671741423578380f, -0.509160243454754640f, 0.860574095348029980f, + -0.509325265833062480f, + 0.860476417631632070f, -0.509490269484936360f, 0.860378708277976130f, + -0.509655254404309250f, + 0.860280967290654510f, -0.509820220585115450f, 0.860183194673260990f, + -0.509985168021289460f, + 0.860085390429390140f, -0.510150096706766810f, 0.859987554562638200f, + -0.510315006635483240f, + 0.859889687076602290f, -0.510479897801375700f, 0.859791787974880650f, + -0.510644770198381610f, + 0.859693857261072610f, -0.510809623820439040f, 0.859595894938779080f, + -0.510974458661486830f, + 0.859497901011601730f, -0.511139274715464390f, 0.859399875483143450f, + -0.511304071976312000f, + 0.859301818357008470f, -0.511468850437970300f, 0.859203729636801920f, + -0.511633610094381240f, + 0.859105609326130450f, -0.511798350939486890f, 0.859007457428601520f, + -0.511963072967230200f, + 0.858909273947823900f, -0.512127776171554690f, 0.858811058887407610f, + -0.512292460546404870f, + 0.858712812250963520f, -0.512457126085725690f, 0.858614534042104190f, + -0.512621772783462990f, + 0.858516224264442740f, -0.512786400633562960f, 0.858417882921593930f, + -0.512951009629972980f, + 0.858319510017173440f, -0.513115599766640560f, 0.858221105554798250f, + -0.513280171037514220f, + 0.858122669538086140f, -0.513444723436543460f, 0.858024201970656540f, + -0.513609256957677780f, + 0.857925702856129790f, -0.513773771594868030f, 0.857827172198127430f, + -0.513938267342065380f, + 0.857728610000272120f, -0.514102744193221660f, 0.857630016266187620f, + -0.514267202142289710f, + 0.857531390999499150f, -0.514431641183222820f, 0.857432734203832700f, + -0.514596061309975040f, + 0.857334045882815590f, -0.514760462516501200f, 0.857235326040076460f, + -0.514924844796756490f, + 0.857136574679244980f, -0.515089208144697160f, 0.857037791803951680f, + -0.515253552554280180f, + 0.856938977417828760f, -0.515417878019462930f, 0.856840131524509220f, + -0.515582184534203790f, + 0.856741254127627470f, -0.515746472092461380f, 0.856642345230818840f, + -0.515910740688195650f, + 0.856543404837719960f, -0.516074990315366630f, 0.856444432951968590f, + -0.516239220967935510f, + 0.856345429577203610f, -0.516403432639863990f, 0.856246394717065210f, + -0.516567625325114350f, + 0.856147328375194470f, -0.516731799017649870f, 0.856048230555233940f, + -0.516895953711434150f, + 0.855949101260826910f, -0.517060089400431910f, 0.855849940495618240f, + -0.517224206078608310f, + 0.855750748263253920f, -0.517388303739929060f, 0.855651524567380690f, + -0.517552382378360880f, + 0.855552269411646860f, -0.517716441987871150f, 0.855452982799701830f, + -0.517880482562427690f, + 0.855353664735196030f, -0.518044504095999340f, 0.855254315221780970f, + -0.518208506582555460f, + 0.855154934263109620f, -0.518372490016066110f, 0.855055521862835950f, + -0.518536454390502220f, + 0.854956078024614930f, -0.518700399699834950f, 0.854856602752102850f, + -0.518864325938036890f, + 0.854757096048957220f, -0.519028233099080860f, 0.854657557918836460f, + -0.519192121176940250f, + 0.854557988365400530f, -0.519355990165589640f, 0.854458387392310170f, + -0.519519840059003760f, + 0.854358755003227440f, -0.519683670851158410f, 0.854259091201815530f, + -0.519847482536030190f, + 0.854159395991738850f, -0.520011275107596040f, 0.854059669376662780f, + -0.520175048559833760f, + 0.853959911360254180f, -0.520338802886721960f, 0.853860121946180770f, + -0.520502538082239670f, + 0.853760301138111410f, -0.520666254140367160f, 0.853660448939716380f, + -0.520829951055084670f, + 0.853560565354666840f, -0.520993628820373920f, 0.853460650386635320f, + -0.521157287430216610f, + 0.853360704039295430f, -0.521320926878595660f, 0.853260726316321880f, + -0.521484547159494330f, + 0.853160717221390420f, -0.521648148266897090f, 0.853060676758178320f, + -0.521811730194788550f, + 0.852960604930363630f, -0.521975292937154390f, 0.852860501741625750f, + -0.522138836487980760f, + 0.852760367195645300f, -0.522302360841254590f, 0.852660201296103760f, + -0.522465865990963780f, + 0.852560004046684080f, -0.522629351931096610f, 0.852459775451070100f, + -0.522792818655642090f, + 0.852359515512947090f, -0.522956266158590140f, 0.852259224236001090f, + -0.523119694433931250f, + 0.852158901623919830f, -0.523283103475656430f, 0.852058547680391690f, + -0.523446493277757830f, + 0.851958162409106380f, -0.523609863834227920f, 0.851857745813754840f, + -0.523773215139060170f, + 0.851757297898029120f, -0.523936547186248600f, 0.851656818665622370f, + -0.524099859969787700f, + 0.851556308120228980f, -0.524263153483673360f, 0.851455766265544310f, + -0.524426427721901400f, + 0.851355193105265200f, -0.524589682678468950f, 0.851254588643089120f, + -0.524752918347373360f, + 0.851153952882715340f, -0.524916134722613000f, 0.851053285827843790f, + -0.525079331798186780f, + 0.850952587482175730f, -0.525242509568094710f, 0.850851857849413530f, + -0.525405668026336930f, + 0.850751096933260790f, -0.525568807166914680f, 0.850650304737422090f, + -0.525731926983829760f, + 0.850549481265603480f, -0.525895027471084630f, 0.850448626521511760f, + -0.526058108622682760f, + 0.850347740508854980f, -0.526221170432628060f, 0.850246823231342710f, + -0.526384212894925100f, + 0.850145874692685210f, -0.526547236003579440f, 0.850044894896594180f, + -0.526710239752597010f, + 0.849943883846782210f, -0.526873224135984590f, 0.849842841546963320f, + -0.527036189147750080f, + 0.849741768000852550f, -0.527199134781901280f, 0.849640663212165910f, + -0.527362061032447540f, + 0.849539527184620890f, -0.527524967893398200f, 0.849438359921936060f, + -0.527687855358763720f, + 0.849337161427830780f, -0.527850723422555230f, 0.849235931706025960f, + -0.528013572078784630f, + 0.849134670760243630f, -0.528176401321464370f, 0.849033378594206800f, + -0.528339211144607690f, + 0.848932055211639610f, -0.528502001542228480f, 0.848830700616267530f, + -0.528664772508341320f, + 0.848729314811817130f, -0.528827524036961870f, 0.848627897802015860f, + -0.528990256122106040f, + 0.848526449590592650f, -0.529152968757790610f, 0.848424970181277600f, + -0.529315661938033260f, + 0.848323459577801640f, -0.529478335656851980f, 0.848221917783896990f, + -0.529640989908265910f, + 0.848120344803297230f, -0.529803624686294610f, 0.848018740639736810f, + -0.529966239984958620f, + 0.847917105296951410f, -0.530128835798278960f, 0.847815438778677930f, + -0.530291412120277310f, + 0.847713741088654380f, -0.530453968944976320f, 0.847612012230619660f, + -0.530616506266399330f, + 0.847510252208314330f, -0.530779024078570140f, 0.847408461025479730f, + -0.530941522375513620f, + 0.847306638685858320f, -0.531104001151255000f, 0.847204785193194090f, + -0.531266460399820390f, + 0.847102900551231500f, -0.531428900115236800f, 0.847000984763716880f, + -0.531591320291531670f, + 0.846899037834397240f, -0.531753720922733320f, 0.846797059767020910f, + -0.531916102002870650f, + 0.846695050565337450f, -0.532078463525973540f, 0.846593010233097190f, + -0.532240805486072220f, + 0.846490938774052130f, -0.532403127877197900f, 0.846388836191954930f, + -0.532565430693382580f, + 0.846286702490559710f, -0.532727713928658810f, 0.846184537673621560f, + -0.532889977577059800f, + 0.846082341744897050f, -0.533052221632619450f, 0.845980114708143270f, + -0.533214446089372960f, + 0.845877856567119000f, -0.533376650941355330f, 0.845775567325584010f, + -0.533538836182603120f, + 0.845673246987299070f, -0.533701001807152960f, 0.845570895556026270f, + -0.533863147809042650f, + 0.845468513035528830f, -0.534025274182310380f, 0.845366099429570970f, + -0.534187380920995380f, + 0.845263654741918220f, -0.534349468019137520f, 0.845161178976337140f, + -0.534511535470777120f, + 0.845058672136595470f, -0.534673583269955510f, 0.844956134226462210f, + -0.534835611410714560f, + 0.844853565249707120f, -0.534997619887097150f, 0.844750965210101510f, + -0.535159608693146600f, + 0.844648334111417820f, -0.535321577822907120f, 0.844545671957429240f, + -0.535483527270423370f, + 0.844442978751910660f, -0.535645457029741090f, 0.844340254498637590f, + -0.535807367094906390f, + 0.844237499201387020f, -0.535969257459966710f, 0.844134712863936930f, + -0.536131128118969460f, + 0.844031895490066410f, -0.536292979065963180f, 0.843929047083555870f, + -0.536454810294997090f, + 0.843826167648186740f, -0.536616621800121040f, 0.843723257187741660f, + -0.536778413575385920f, + 0.843620315706004150f, -0.536940185614842910f, 0.843517343206759200f, + -0.537101937912544130f, + 0.843414339693792760f, -0.537263670462542530f, 0.843311305170892140f, + -0.537425383258891550f, + 0.843208239641845440f, -0.537587076295645390f, 0.843105143110442160f, + -0.537748749566859360f, + 0.843002015580472940f, -0.537910403066588880f, 0.842898857055729310f, + -0.538072036788890600f, + 0.842795667540004120f, -0.538233650727821700f, 0.842692447037091670f, + -0.538395244877439950f, + 0.842589195550786710f, -0.538556819231804100f, 0.842485913084885630f, + -0.538718373784973560f, + 0.842382599643185850f, -0.538879908531008420f, 0.842279255229485990f, + -0.539041423463969440f, + 0.842175879847585570f, -0.539202918577918240f, 0.842072473501285560f, + -0.539364393866917040f, + 0.841969036194387680f, -0.539525849325028890f, 0.841865567930695340f, + -0.539687284946317570f, + 0.841762068714012490f, -0.539848700724847590f, 0.841658538548144760f, + -0.540010096654684020f, + 0.841554977436898440f, -0.540171472729892850f, 0.841451385384081260f, + -0.540332828944540710f, + 0.841347762393501950f, -0.540494165292695230f, 0.841244108468970580f, + -0.540655481768424150f, + 0.841140423614298080f, -0.540816778365796670f, 0.841036707833296650f, + -0.540978055078882080f, + 0.840932961129779780f, -0.541139311901750800f, 0.840829183507561640f, + -0.541300548828474120f, + 0.840725374970458070f, -0.541461765853123440f, 0.840621535522285690f, + -0.541622962969771530f, + 0.840517665166862550f, -0.541784140172491550f, 0.840413763908007480f, + -0.541945297455357360f, + 0.840309831749540770f, -0.542106434812443920f, 0.840205868695283580f, + -0.542267552237826520f, + 0.840101874749058400f, -0.542428649725581250f, 0.839997849914688840f, + -0.542589727269785270f, + 0.839893794195999520f, -0.542750784864515890f, 0.839789707596816370f, + -0.542911822503851730f, + 0.839685590120966110f, -0.543072840181871740f, 0.839581441772277120f, + -0.543233837892655890f, + 0.839477262554578550f, -0.543394815630284800f, 0.839373052471700690f, + -0.543555773388839540f, + 0.839268811527475230f, -0.543716711162402280f, 0.839164539725734680f, + -0.543877628945055980f, + 0.839060237070312740f, -0.544038526730883820f, 0.838955903565044460f, + -0.544199404513970310f, + 0.838851539213765760f, -0.544360262288400400f, 0.838747144020313920f, + -0.544521100048259600f, + 0.838642717988527300f, -0.544681917787634530f, 0.838538261122245280f, + -0.544842715500612360f, + 0.838433773425308340f, -0.545003493181281160f, 0.838329254901558300f, + -0.545164250823729320f, + 0.838224705554838080f, -0.545324988422046460f, 0.838120125388991500f, + -0.545485705970322530f, + 0.838015514407863820f, -0.545646403462648590f, 0.837910872615301170f, + -0.545807080893116140f, + 0.837806200015150940f, -0.545967738255817570f, 0.837701496611261700f, + -0.546128375544845950f, + 0.837596762407483040f, -0.546288992754295210f, 0.837491997407665890f, + -0.546449589878259650f, + 0.837387201615661940f, -0.546610166910834860f, 0.837282375035324320f, + -0.546770723846116800f, + 0.837177517670507300f, -0.546931260678202190f, 0.837072629525066000f, + -0.547091777401188530f, + 0.836967710602857020f, -0.547252274009174090f, 0.836862760907737920f, + -0.547412750496257930f, + 0.836757780443567190f, -0.547573206856539760f, 0.836652769214204950f, + -0.547733643084120090f, + 0.836547727223512010f, -0.547894059173100190f, 0.836442654475350380f, + -0.548054455117581880f, + 0.836337550973583530f, -0.548214830911667780f, 0.836232416722075600f, + -0.548375186549461600f, + 0.836127251724692270f, -0.548535522025067390f, 0.836022055985299880f, + -0.548695837332590090f, + 0.835916829507766360f, -0.548856132466135290f, 0.835811572295960700f, + -0.549016407419809390f, + 0.835706284353752600f, -0.549176662187719660f, 0.835600965685013410f, + -0.549336896763974010f, + 0.835495616293615350f, -0.549497111142680960f, 0.835390236183431890f, + -0.549657305317949870f, + 0.835284825358337370f, -0.549817479283890910f, 0.835179383822207690f, + -0.549977633034614890f, + 0.835073911578919410f, -0.550137766564233630f, 0.834968408632350450f, + -0.550297879866859190f, + 0.834862874986380010f, -0.550457972936604810f, 0.834757310644888230f, + -0.550618045767584330f, + 0.834651715611756440f, -0.550778098353912120f, 0.834546089890866870f, + -0.550938130689703880f, + 0.834440433486103190f, -0.551098142769075430f, 0.834334746401350080f, + -0.551258134586143590f, + 0.834229028640493420f, -0.551418106135026060f, 0.834123280207420100f, + -0.551578057409841000f, + 0.834017501106018130f, -0.551737988404707340f, 0.833911691340176840f, + -0.551897899113745210f, + 0.833805850913786340f, -0.552057789531074980f, 0.833699979830738290f, + -0.552217659650817930f, + 0.833594078094925140f, -0.552377509467096070f, 0.833488145710240770f, + -0.552537338974032120f, + 0.833382182680579730f, -0.552697148165749770f, 0.833276189009838240f, + -0.552856937036373290f, + 0.833170164701913190f, -0.553016705580027470f, 0.833064109760702890f, + -0.553176453790838350f, + 0.832958024190106670f, -0.553336181662932300f, 0.832851907994025090f, + -0.553495889190436570f, + 0.832745761176359460f, -0.553655576367479310f, 0.832639583741012770f, + -0.553815243188189090f, + 0.832533375691888680f, -0.553974889646695500f, 0.832427137032892280f, + -0.554134515737128910f, + 0.832320867767929680f, -0.554294121453620000f, 0.832214567900907980f, + -0.554453706790300930f, + 0.832108237435735590f, -0.554613271741304040f, 0.832001876376321950f, + -0.554772816300762470f, + 0.831895484726577590f, -0.554932340462810370f, 0.831789062490414400f, + -0.555091844221582420f, + 0.831682609671745120f, -0.555251327571213980f, 0.831576126274483740f, + -0.555410790505841630f, + 0.831469612302545240f, -0.555570233019602180f, 0.831363067759845920f, + -0.555729655106633410f, + 0.831256492650303210f, -0.555889056761073810f, 0.831149886977835540f, + -0.556048437977062600f, + 0.831043250746362320f, -0.556207798748739930f, 0.830936583959804410f, + -0.556367139070246370f, + 0.830829886622083570f, -0.556526458935723610f, 0.830723158737122880f, + -0.556685758339313890f, + 0.830616400308846310f, -0.556845037275160100f, 0.830509611341179070f, + -0.557004295737405950f, + 0.830402791838047550f, -0.557163533720196220f, 0.830295941803379070f, + -0.557322751217676160f, + 0.830189061241102370f, -0.557481948223991550f, 0.830082150155146970f, + -0.557641124733289420f, + 0.829975208549443950f, -0.557800280739716990f, 0.829868236427924840f, + -0.557959416237422960f, + 0.829761233794523050f, -0.558118531220556100f, 0.829654200653172640f, + -0.558277625683266330f, + 0.829547137007808910f, -0.558436699619704100f, 0.829440042862368170f, + -0.558595753024020760f, + 0.829332918220788250f, -0.558754785890368310f, 0.829225763087007570f, + -0.558913798212899770f, + 0.829118577464965980f, -0.559072789985768480f, 0.829011361358604430f, + -0.559231761203128900f, + 0.828904114771864870f, -0.559390711859136140f, 0.828796837708690610f, + -0.559549641947945760f, + 0.828689530173025820f, -0.559708551463714680f, 0.828582192168815790f, + -0.559867440400600210f, + 0.828474823700007130f, -0.560026308752760380f, 0.828367424770547480f, + -0.560185156514354080f, + 0.828259995384385660f, -0.560343983679540860f, 0.828152535545471410f, + -0.560502790242481060f, + 0.828045045257755800f, -0.560661576197336030f, 0.827937524525190870f, + -0.560820341538267430f, + 0.827829973351729920f, -0.560979086259438150f, 0.827722391741327220f, + -0.561137810355011420f, + 0.827614779697938400f, -0.561296513819151470f, 0.827507137225519830f, + -0.561455196646023280f, + 0.827399464328029470f, -0.561613858829792420f, 0.827291761009425810f, + -0.561772500364625340f, + 0.827184027273669130f, -0.561931121244689470f, 0.827076263124720270f, + -0.562089721464152480f, + 0.826968468566541600f, -0.562248301017183150f, 0.826860643603096190f, + -0.562406859897951140f, + 0.826752788238348520f, -0.562565398100626560f, 0.826644902476264320f, + -0.562723915619380400f, + 0.826536986320809960f, -0.562882412448384440f, 0.826429039775953500f, + -0.563040888581811230f, + 0.826321062845663530f, -0.563199344013834090f, 0.826213055533910220f, + -0.563357778738627020f, + 0.826105017844664610f, -0.563516192750364800f, 0.825996949781899080f, + -0.563674586043223070f, + 0.825888851349586780f, -0.563832958611378170f, 0.825780722551702430f, + -0.563991310449006970f, + 0.825672563392221390f, -0.564149641550287680f, 0.825564373875120490f, + -0.564307951909398640f, + 0.825456154004377550f, -0.564466241520519500f, 0.825347903783971380f, + -0.564624510377830120f, + 0.825239623217882250f, -0.564782758475511400f, 0.825131312310091070f, + -0.564940985807745210f, + 0.825022971064580220f, -0.565099192368713980f, 0.824914599485333190f, + -0.565257378152600800f, + 0.824806197576334330f, -0.565415543153589660f, 0.824697765341569470f, + -0.565573687365865330f, + 0.824589302785025290f, -0.565731810783613120f, 0.824480809910689500f, + -0.565889913401019570f, + 0.824372286722551250f, -0.566047995212271450f, 0.824263733224600560f, + -0.566206056211556730f, + 0.824155149420828570f, -0.566364096393063840f, 0.824046535315227760f, + -0.566522115750982100f, + 0.823937890911791370f, -0.566680114279501600f, 0.823829216214513990f, + -0.566838091972813320f, + 0.823720511227391430f, -0.566996048825108680f, 0.823611775954420260f, + -0.567153984830580100f, + 0.823503010399598500f, -0.567311899983420800f, 0.823394214566925080f, + -0.567469794277824510f, + 0.823285388460400110f, -0.567627667707986230f, 0.823176532084024860f, + -0.567785520268101140f, + 0.823067645441801670f, -0.567943351952365560f, 0.822958728537734000f, + -0.568101162754976460f, + 0.822849781375826430f, -0.568258952670131490f, 0.822740803960084420f, + -0.568416721692029280f, + 0.822631796294514990f, -0.568574469814869140f, 0.822522758383125940f, + -0.568732197032851050f, + 0.822413690229926390f, -0.568889903340175860f, 0.822304591838926350f, + -0.569047588731045110f, + 0.822195463214137170f, -0.569205253199661200f, 0.822086304359571090f, + -0.569362896740227220f, + 0.821977115279241550f, -0.569520519346947140f, 0.821867895977163250f, + -0.569678121014025600f, + 0.821758646457351750f, -0.569835701735668000f, 0.821649366723823940f, + -0.569993261506080540f, + 0.821540056780597610f, -0.570150800319470300f, 0.821430716631691870f, + -0.570308318170044900f, + 0.821321346281126740f, -0.570465815052012990f, 0.821211945732923550f, + -0.570623290959583750f, + 0.821102514991104650f, -0.570780745886967260f, 0.820993054059693580f, + -0.570938179828374360f, + 0.820883562942714580f, -0.571095592778016690f, 0.820774041644193650f, + -0.571252984730106660f, + 0.820664490168157460f, -0.571410355678857230f, 0.820554908518633890f, + -0.571567705618482580f, + 0.820445296699652050f, -0.571725034543197120f, 0.820335654715241840f, + -0.571882342447216590f, + 0.820225982569434690f, -0.572039629324757050f, 0.820116280266262820f, + -0.572196895170035580f, + 0.820006547809759680f, -0.572354139977269920f, 0.819896785203959810f, + -0.572511363740678790f, + 0.819786992452898990f, -0.572668566454481160f, 0.819677169560613870f, + -0.572825748112897550f, + 0.819567316531142230f, -0.572982908710148560f, 0.819457433368523280f, + -0.573140048240455950f, + 0.819347520076796900f, -0.573297166698042200f, 0.819237576660004520f, + -0.573454264077130400f, + 0.819127603122188240f, -0.573611340371944610f, 0.819017599467391500f, + -0.573768395576709560f, + 0.818907565699658950f, -0.573925429685650750f, 0.818797501823036010f, + -0.574082442692994470f, + 0.818687407841569680f, -0.574239434592967890f, 0.818577283759307610f, + -0.574396405379798750f, + 0.818467129580298660f, -0.574553355047715760f, 0.818356945308593150f, + -0.574710283590948330f, + 0.818246730948242070f, -0.574867191003726740f, 0.818136486503297730f, + -0.575024077280281710f, + 0.818026211977813440f, -0.575180942414845080f, 0.817915907375843850f, + -0.575337786401649450f, + 0.817805572701444270f, -0.575494609234928120f, 0.817695207958671680f, + -0.575651410908915140f, + 0.817584813151583710f, -0.575808191417845340f, 0.817474388284239240f, + -0.575964950755954220f, + 0.817363933360698460f, -0.576121688917478280f, 0.817253448385022340f, + -0.576278405896654910f, + 0.817142933361272970f, -0.576435101687721830f, 0.817032388293513880f, + -0.576591776284917760f, + 0.816921813185809480f, -0.576748429682482410f, 0.816811208042225290f, + -0.576905061874655960f, + 0.816700572866827850f, -0.577061672855679440f, 0.816589907663684890f, + -0.577218262619794920f, + 0.816479212436865390f, -0.577374831161244880f, 0.816368487190439200f, + -0.577531378474272720f, + 0.816257731928477390f, -0.577687904553122800f, 0.816146946655052270f, + -0.577844409392039850f, + 0.816036131374236810f, -0.578000892985269910f, 0.815925286090105510f, + -0.578157355327059360f, + 0.815814410806733780f, -0.578313796411655590f, 0.815703505528198260f, + -0.578470216233306630f, + 0.815592570258576790f, -0.578626614786261430f, 0.815481605001947770f, + -0.578782992064769690f, + 0.815370609762391290f, -0.578939348063081780f, 0.815259584543988280f, + -0.579095682775449090f, + 0.815148529350820830f, -0.579251996196123550f, 0.815037444186972220f, + -0.579408288319357870f, + 0.814926329056526620f, -0.579564559139405630f, 0.814815183963569440f, + -0.579720808650521450f, + 0.814704008912187080f, -0.579877036846960350f, 0.814592803906467270f, + -0.580033243722978150f, + 0.814481568950498610f, -0.580189429272831680f, 0.814370304048371070f, + -0.580345593490778300f, + 0.814259009204175270f, -0.580501736371076490f, 0.814147684422003360f, + -0.580657857907985300f, + 0.814036329705948410f, -0.580813958095764530f, 0.813924945060104600f, + -0.580970036928674770f, + 0.813813530488567190f, -0.581126094400977620f, 0.813702085995432700f, + -0.581282130506935000f, + 0.813590611584798510f, -0.581438145240810170f, 0.813479107260763220f, + -0.581594138596866930f, + 0.813367573027426570f, -0.581750110569369650f, 0.813256008888889380f, + -0.581906061152583810f, + 0.813144414849253590f, -0.582061990340775440f, 0.813032790912622040f, + -0.582217898128211670f, + 0.812921137083098770f, -0.582373784509160110f, 0.812809453364789270f, + -0.582529649477889320f, + 0.812697739761799490f, -0.582685493028668460f, 0.812585996278237130f, + -0.582841315155767650f, + 0.812474222918210480f, -0.582997115853457700f, 0.812362419685829230f, + -0.583152895116010430f, + 0.812250586585203880f, -0.583308652937698290f, 0.812138723620446480f, + -0.583464389312794320f, + 0.812026830795669730f, -0.583620104235572760f, 0.811914908114987790f, + -0.583775797700308070f, + 0.811802955582515470f, -0.583931469701276180f, 0.811690973202369050f, + -0.584087120232753440f, + 0.811578960978665890f, -0.584242749289016980f, 0.811466918915524250f, + -0.584398356864344600f, + 0.811354847017063730f, -0.584553942953015330f, 0.811242745287404810f, + -0.584709507549308390f, + 0.811130613730669190f, -0.584865050647504490f, 0.811018452350979470f, + -0.585020572241884530f, + 0.810906261152459670f, -0.585176072326730410f, 0.810794040139234730f, + -0.585331550896324940f, + 0.810681789315430780f, -0.585487007944951340f, 0.810569508685174630f, + -0.585642443466894420f, + 0.810457198252594770f, -0.585797857456438860f, 0.810344858021820550f, + -0.585953249907870570f, + 0.810232487996982330f, -0.586108620815476430f, 0.810120088182211600f, + -0.586263970173543590f, + 0.810007658581641140f, -0.586419297976360500f, 0.809895199199404450f, + -0.586574604218216170f, + 0.809782710039636530f, -0.586729888893400390f, 0.809670191106473090f, + -0.586885151996203950f, + 0.809557642404051260f, -0.587040393520917970f, 0.809445063936509170f, + -0.587195613461834800f, + 0.809332455707985950f, -0.587350811813247660f, 0.809219817722621750f, + -0.587505988569450020f, + 0.809107149984558240f, -0.587661143724736660f, 0.808994452497937670f, + -0.587816277273402910f, + 0.808881725266903610f, -0.587971389209745010f, 0.808768968295600850f, + -0.588126479528059850f, + 0.808656181588174980f, -0.588281548222645220f, 0.808543365148773010f, + -0.588436595287799790f, + 0.808430518981542720f, -0.588591620717822890f, 0.808317643090633250f, + -0.588746624507014540f, + 0.808204737480194720f, -0.588901606649675720f, 0.808091802154378370f, + -0.589056567140108460f, + 0.807978837117336310f, -0.589211505972614960f, 0.807865842373222120f, + -0.589366423141498790f, + 0.807752817926190360f, -0.589521318641063940f, 0.807639763780396480f, + -0.589676192465615420f, + 0.807526679939997160f, -0.589831044609458790f, 0.807413566409150190f, + -0.589985875066900920f, + 0.807300423192014450f, -0.590140683832248820f, 0.807187250292749960f, + -0.590295470899810830f, + 0.807074047715517610f, -0.590450236263895810f, 0.806960815464479730f, + -0.590604979918813330f, + 0.806847553543799330f, -0.590759701858874160f, 0.806734261957640860f, + -0.590914402078389520f, + 0.806620940710169650f, -0.591069080571671400f, 0.806507589805552260f, + -0.591223737333032910f, + 0.806394209247956240f, -0.591378372356787580f, 0.806280799041550480f, + -0.591532985637249990f, + 0.806167359190504420f, -0.591687577168735430f, 0.806053889698989060f, + -0.591842146945560140f, + 0.805940390571176280f, -0.591996694962040990f, 0.805826861811239300f, + -0.592151221212495530f, + 0.805713303423352230f, -0.592305725691242290f, 0.805599715411690060f, + -0.592460208392600830f, + 0.805486097780429230f, -0.592614669310891130f, 0.805372450533747060f, + -0.592769108440434070f, + 0.805258773675822210f, -0.592923525775551300f, 0.805145067210834230f, + -0.593077921310565470f, + 0.805031331142963660f, -0.593232295039799800f, 0.804917565476392260f, + -0.593386646957578480f, + 0.804803770215302920f, -0.593540977058226390f, 0.804689945363879500f, + -0.593695285336069190f, + 0.804576090926307110f, -0.593849571785433630f, 0.804462206906771840f, + -0.594003836400646690f, + 0.804348293309460780f, -0.594158079176036800f, 0.804234350138562260f, + -0.594312300105932830f, + 0.804120377398265810f, -0.594466499184664430f, 0.804006375092761520f, + -0.594620676406562240f, + 0.803892343226241260f, -0.594774831765957580f, 0.803778281802897570f, + -0.594928965257182420f, + 0.803664190826924090f, -0.595083076874569960f, 0.803550070302515680f, + -0.595237166612453850f, + 0.803435920233868120f, -0.595391234465168730f, 0.803321740625178580f, + -0.595545280427049790f, + 0.803207531480644940f, -0.595699304492433360f, 0.803093292804466400f, + -0.595853306655656280f, + 0.802979024600843250f, -0.596007286911056530f, 0.802864726873976700f, + -0.596161245252972540f, + 0.802750399628069160f, -0.596315181675743710f, 0.802636042867324150f, + -0.596469096173710360f, + 0.802521656595946430f, -0.596622988741213220f, 0.802407240818141300f, + -0.596776859372594390f, + 0.802292795538115720f, -0.596930708062196500f, 0.802178320760077450f, + -0.597084534804362740f, + 0.802063816488235440f, -0.597238339593437420f, 0.801949282726799770f, + -0.597392122423765710f, + 0.801834719479981310f, -0.597545883289693160f, 0.801720126751992330f, + -0.597699622185566830f, + 0.801605504547046150f, -0.597853339105733910f, 0.801490852869356950f, + -0.598007034044542700f, + 0.801376171723140240f, -0.598160706996342270f, 0.801261461112612540f, + -0.598314357955482600f, + 0.801146721041991360f, -0.598467986916314310f, 0.801031951515495330f, + -0.598621593873188920f, + 0.800917152537344300f, -0.598775178820458720f, 0.800802324111759110f, + -0.598928741752476900f, + 0.800687466242961610f, -0.599082282663597310f, 0.800572578935174860f, + -0.599235801548174570f, + 0.800457662192622820f, -0.599389298400564540f, 0.800342716019530660f, + -0.599542773215123390f, + 0.800227740420124790f, -0.599696225986208310f, 0.800112735398632370f, + -0.599849656708177250f, + 0.799997700959281910f, -0.600003065375388940f, 0.799882637106302810f, + -0.600156451982203240f, + 0.799767543843925680f, -0.600309816522980430f, 0.799652421176382240f, + -0.600463158992081580f, + 0.799537269107905010f, -0.600616479383868970f, 0.799422087642728040f, + -0.600769777692705230f, + 0.799306876785086160f, -0.600923053912954090f, 0.799191636539215210f, + -0.601076308038980160f, + 0.799076366909352350f, -0.601229540065148500f, 0.798961067899735760f, + -0.601382749985825420f, + 0.798845739514604580f, -0.601535937795377730f, 0.798730381758199210f, + -0.601689103488172950f, + 0.798614994634760820f, -0.601842247058580030f, 0.798499578148532120f, + -0.601995368500968020f, + 0.798384132303756380f, -0.602148467809707210f, 0.798268657104678430f, + -0.602301544979168550f, + 0.798153152555543750f, -0.602454600003723750f, 0.798037618660599410f, + -0.602607632877745440f, + 0.797922055424093000f, -0.602760643595607220f, 0.797806462850273570f, + -0.602913632151683030f, + 0.797690840943391160f, -0.603066598540348160f, 0.797575189707696700f, + -0.603219542755978440f, + 0.797459509147442460f, -0.603372464792950260f, 0.797343799266881700f, + -0.603525364645641550f, + 0.797228060070268700f, -0.603678242308430370f, 0.797112291561858920f, + -0.603831097775695880f, + 0.796996493745908750f, -0.603983931041818020f, 0.796880666626675780f, + -0.604136742101177520f, + 0.796764810208418830f, -0.604289530948155960f, 0.796648924495397260f, + -0.604442297577135860f, + 0.796533009491872000f, -0.604595041982500360f, 0.796417065202104980f, + -0.604747764158633410f, + 0.796301091630359110f, -0.604900464099919820f, 0.796185088780898440f, + -0.605053141800745320f, + 0.796069056657987990f, -0.605205797255496500f, 0.795952995265893910f, + -0.605358430458560530f, + 0.795836904608883570f, -0.605511041404325550f, 0.795720784691225090f, + -0.605663630087180380f, + 0.795604635517188070f, -0.605816196501514970f, 0.795488457091042990f, + -0.605968740641719680f, + 0.795372249417061310f, -0.606121262502186120f, 0.795256012499515610f, + -0.606273762077306430f, + 0.795139746342679590f, -0.606426239361473550f, 0.795023450950828050f, + -0.606578694349081290f, + 0.794907126328237010f, -0.606731127034524480f, 0.794790772479183170f, + -0.606883537412198470f, + 0.794674389407944550f, -0.607035925476499650f, 0.794557977118800380f, + -0.607188291221825160f, + 0.794441535616030590f, -0.607340634642572930f, 0.794325064903916520f, + -0.607492955733141550f, + 0.794208564986740640f, -0.607645254487930830f, 0.794092035868785960f, + -0.607797530901341140f, + 0.793975477554337170f, -0.607949784967773630f, 0.793858890047679730f, + -0.608102016681630440f, + 0.793742273353100210f, -0.608254226037314490f, 0.793625627474886300f, + -0.608406413029229150f, + 0.793508952417326660f, -0.608558577651779450f, 0.793392248184711100f, + -0.608710719899370310f, + 0.793275514781330630f, -0.608862839766408200f, 0.793158752211477140f, + -0.609014937247299830f, + 0.793041960479443640f, -0.609167012336453210f, 0.792925139589524260f, + -0.609319065028276820f, + 0.792808289546014120f, -0.609471095317180240f, 0.792691410353209450f, + -0.609623103197573730f, + 0.792574502015407690f, -0.609775088663868430f, 0.792457564536907080f, + -0.609927051710476120f, + 0.792340597922007170f, -0.610078992331809620f, 0.792223602175008310f, + -0.610230910522282620f, + 0.792106577300212390f, -0.610382806276309480f, 0.791989523301921850f, + -0.610534679588305320f, + 0.791872440184440470f, -0.610686530452686280f, 0.791755327952073150f, + -0.610838358863869170f, + 0.791638186609125880f, -0.610990164816271660f, 0.791521016159905220f, + -0.611141948304312570f, + 0.791403816608719500f, -0.611293709322410890f, 0.791286587959877830f, + -0.611445447864987000f, + 0.791169330217690200f, -0.611597163926461910f, 0.791052043386467950f, + -0.611748857501257290f, + 0.790934727470523290f, -0.611900528583796070f, 0.790817382474169770f, + -0.612052177168501470f, + 0.790700008401721610f, -0.612203803249797950f, 0.790582605257494460f, + -0.612355406822110650f, + 0.790465173045804880f, -0.612506987879865570f, 0.790347711770970520f, + -0.612658546417489290f, + 0.790230221437310030f, -0.612810082429409710f, 0.790112702049143300f, + -0.612961595910055170f, + 0.789995153610791090f, -0.613113086853854910f, 0.789877576126575280f, + -0.613264555255239040f, + 0.789759969600819070f, -0.613416001108638590f, 0.789642334037846340f, + -0.613567424408485330f, + 0.789524669441982190f, -0.613718825149211720f, 0.789406975817552930f, + -0.613870203325251330f, + 0.789289253168885650f, -0.614021558931038380f, 0.789171501500308900f, + -0.614172891961007990f, + 0.789053720816151880f, -0.614324202409595950f, 0.788935911120745240f, + -0.614475490271239040f, + 0.788818072418420280f, -0.614626755540375050f, 0.788700204713509660f, + -0.614777998211442080f, + 0.788582308010347120f, -0.614929218278879590f, 0.788464382313267540f, + -0.615080415737127460f, + 0.788346427626606340f, -0.615231590580626820f, 0.788228443954700490f, + -0.615382742803819220f, + 0.788110431301888070f, -0.615533872401147320f, 0.787992389672507950f, + -0.615684979367054570f, + 0.787874319070900220f, -0.615836063695985090f, 0.787756219501406060f, + -0.615987125382383760f, + 0.787638090968367450f, -0.616138164420696910f, 0.787519933476127810f, + -0.616289180805370980f, + 0.787401747029031430f, -0.616440174530853650f, 0.787283531631423620f, + -0.616591145591593110f, + 0.787165287287651010f, -0.616742093982038720f, 0.787047014002060790f, + -0.616893019696640680f, + 0.786928711779001810f, -0.617043922729849760f, 0.786810380622823490f, + -0.617194803076117630f, + 0.786692020537876790f, -0.617345660729896830f, 0.786573631528513230f, + -0.617496495685640910f, + 0.786455213599085770f, -0.617647307937803870f, 0.786336766753948260f, + -0.617798097480841020f, + 0.786218290997455660f, -0.617948864309208150f, 0.786099786333963930f, + -0.618099608417362000f, + 0.785981252767830150f, -0.618250329799760250f, 0.785862690303412600f, + -0.618401028450860980f, + 0.785744098945070360f, -0.618551704365123740f, 0.785625478697163700f, + -0.618702357537008530f, + 0.785506829564053930f, -0.618852987960976320f, 0.785388151550103550f, + -0.619003595631488660f, + 0.785269444659675850f, -0.619154180543008410f, 0.785150708897135560f, + -0.619304742689998690f, + 0.785031944266848080f, -0.619455282066924020f, 0.784913150773180020f, + -0.619605798668249270f, + 0.784794328420499230f, -0.619756292488440660f, 0.784675477213174320f, + -0.619906763521964720f, + 0.784556597155575240f, -0.620057211763289100f, 0.784437688252072830f, + -0.620207637206882430f, + 0.784318750507038920f, -0.620358039847213720f, 0.784199783924846570f, + -0.620508419678753360f, + 0.784080788509869950f, -0.620658776695972140f, 0.783961764266484120f, + -0.620809110893341900f, + 0.783842711199065230f, -0.620959422265335180f, 0.783723629311990470f, + -0.621109710806425630f, + 0.783604518609638200f, -0.621259976511087550f, 0.783485379096387820f, + -0.621410219373796150f, + 0.783366210776619720f, -0.621560439389027160f, 0.783247013654715380f, + -0.621710636551257690f, + 0.783127787735057310f, -0.621860810854965360f, 0.783008533022029110f, + -0.622010962294628600f, + 0.782889249520015480f, -0.622161090864726820f, 0.782769937233402050f, + -0.622311196559740320f, + 0.782650596166575730f, -0.622461279374149970f, 0.782531226323924240f, + -0.622611339302437730f, + 0.782411827709836530f, -0.622761376339086350f, 0.782292400328702400f, + -0.622911390478579460f, + 0.782172944184913010f, -0.623061381715401260f, 0.782053459282860300f, + -0.623211350044037270f, + 0.781933945626937630f, -0.623361295458973230f, 0.781814403221538830f, + -0.623511217954696440f, + 0.781694832071059390f, -0.623661117525694530f, 0.781575232179895550f, + -0.623810994166456130f, + 0.781455603552444590f, -0.623960847871470660f, 0.781335946193104870f, + -0.624110678635228510f, + 0.781216260106276090f, -0.624260486452220650f, 0.781096545296358520f, + -0.624410271316939270f, + 0.780976801767753750f, -0.624560033223877210f, 0.780857029524864580f, + -0.624709772167528100f, + 0.780737228572094490f, -0.624859488142386340f, 0.780617398913848400f, + -0.625009181142947460f, + 0.780497540554531910f, -0.625158851163707620f, 0.780377653498552040f, + -0.625308498199164010f, + 0.780257737750316590f, -0.625458122243814360f, 0.780137793314234610f, + -0.625607723292157410f, + 0.780017820194715990f, -0.625757301338692900f, 0.779897818396172000f, + -0.625906856377921090f, + 0.779777787923014550f, -0.626056388404343520f, 0.779657728779656890f, + -0.626205897412462130f, + 0.779537640970513260f, -0.626355383396779990f, 0.779417524499998900f, + -0.626504846351800810f, + 0.779297379372530300f, -0.626654286272029350f, 0.779177205592524680f, + -0.626803703151971200f, + 0.779057003164400630f, -0.626953096986132660f, 0.778936772092577500f, + -0.627102467769020900f, + 0.778816512381475980f, -0.627251815495144080f, 0.778696224035517530f, + -0.627401140159011050f, + 0.778575907059125050f, -0.627550441755131530f, 0.778455561456721900f, + -0.627699720278016240f, + 0.778335187232733210f, -0.627848975722176460f, 0.778214784391584540f, + -0.627998208082124700f, + 0.778094352937702790f, -0.628147417352374000f, 0.777973892875516100f, + -0.628296603527438320f, + 0.777853404209453150f, -0.628445766601832710f, 0.777732886943944050f, + -0.628594906570072550f, + 0.777612341083420030f, -0.628744023426674680f, 0.777491766632313010f, + -0.628893117166156480f, + 0.777371163595056310f, -0.629042187783036000f, 0.777250531976084070f, + -0.629191235271832290f, + 0.777129871779831620f, -0.629340259627065630f, 0.777009183010735290f, + -0.629489260843256630f, + 0.776888465673232440f, -0.629638238914926980f, 0.776767719771761510f, + -0.629787193836599200f, + 0.776646945310762060f, -0.629936125602796440f, 0.776526142294674430f, + -0.630085034208043180f, + 0.776405310727940390f, -0.630233919646864370f, 0.776284450615002510f, + -0.630382781913785940f, + 0.776163561960304340f, -0.630531621003334600f, 0.776042644768290770f, + -0.630680436910037940f, + 0.775921699043407690f, -0.630829229628424470f, 0.775800724790101650f, + -0.630977999153023550f, + 0.775679722012820650f, -0.631126745478365340f, 0.775558690716013580f, + -0.631275468598980760f, + 0.775437630904130540f, -0.631424168509401860f, 0.775316542581622530f, + -0.631572845204161020f, + 0.775195425752941420f, -0.631721498677792260f, 0.775074280422540450f, + -0.631870128924829850f, + 0.774953106594873930f, -0.632018735939809060f, 0.774831904274396850f, + -0.632167319717265920f, + 0.774710673465565550f, -0.632315880251737570f, 0.774589414172837550f, + -0.632464417537761840f, + 0.774468126400670860f, -0.632612931569877410f, 0.774346810153525130f, + -0.632761422342624000f, + 0.774225465435860680f, -0.632909889850541750f, 0.774104092252139050f, + -0.633058334088172140f, + 0.773982690606822900f, -0.633206755050057190f, 0.773861260504375540f, + -0.633355152730739950f, + 0.773739801949261840f, -0.633503527124764320f, 0.773618314945947460f, + -0.633651878226674900f, + 0.773496799498899050f, -0.633800206031017280f, 0.773375255612584470f, + -0.633948510532337810f, + 0.773253683291472590f, -0.634096791725183740f, 0.773132082540033070f, + -0.634245049604103330f, + 0.773010453362736990f, -0.634393284163645490f, 0.772888795764056220f, + -0.634541495398360020f, + 0.772767109748463850f, -0.634689683302797740f, 0.772645395320433860f, + -0.634837847871509990f, + 0.772523652484441330f, -0.634985989099049460f, 0.772401881244962450f, + -0.635134106979969190f, + 0.772280081606474320f, -0.635282201508823420f, 0.772158253573455240f, + -0.635430272680167160f, + 0.772036397150384520f, -0.635578320488556110f, 0.771914512341742350f, + -0.635726344928547070f, + 0.771792599152010150f, -0.635874345994697720f, 0.771670657585670330f, + -0.636022323681566300f, + 0.771548687647206300f, -0.636170277983712170f, 0.771426689341102590f, + -0.636318208895695460f, + 0.771304662671844830f, -0.636466116412077180f, 0.771182607643919330f, + -0.636614000527419120f, + 0.771060524261813820f, -0.636761861236284200f, 0.770938412530016940f, + -0.636909698533235870f, + 0.770816272453018540f, -0.637057512412838590f, 0.770694104035309140f, + -0.637205302869657600f, + 0.770571907281380810f, -0.637353069898259130f, 0.770449682195725960f, + -0.637500813493210190f, + 0.770327428782838890f, -0.637648533649078810f, 0.770205147047214210f, + -0.637796230360433540f, + 0.770082836993347900f, -0.637943903621844060f, 0.769960498625737230f, + -0.638091553427880820f, + 0.769838131948879840f, -0.638239179773115280f, 0.769715736967275130f, + -0.638386782652119570f, + 0.769593313685422940f, -0.638534362059466790f, 0.769470862107824670f, + -0.638681917989730730f, + 0.769348382238982280f, -0.638829450437486290f, 0.769225874083399260f, + -0.638976959397309140f, + 0.769103337645579700f, -0.639124444863775730f, 0.768980772930028870f, + -0.639271906831463510f, + 0.768858179941253270f, -0.639419345294950700f, 0.768735558683760310f, + -0.639566760248816310f, + 0.768612909162058380f, -0.639714151687640450f, 0.768490231380656860f, + -0.639861519606003900f, + 0.768367525344066270f, -0.640008863998488440f, 0.768244791056798330f, + -0.640156184859676510f, + 0.768122028523365420f, -0.640303482184151670f, 0.767999237748281270f, + -0.640450755966498140f, + 0.767876418736060610f, -0.640598006201301030f, 0.767753571491219030f, + -0.640745232883146440f, + 0.767630696018273380f, -0.640892436006621380f, 0.767507792321741270f, + -0.641039615566313390f, + 0.767384860406141730f, -0.641186771556811250f, 0.767261900275994500f, + -0.641333903972704290f, + 0.767138911935820400f, -0.641481012808583160f, 0.767015895390141480f, + -0.641628098059038750f, + 0.766892850643480670f, -0.641775159718663500f, 0.766769777700361920f, + -0.641922197782050170f, + 0.766646676565310380f, -0.642069212243792540f, 0.766523547242852210f, + -0.642216203098485370f, + 0.766400389737514230f, -0.642363170340724320f, 0.766277204053824710f, + -0.642510113965105710f, + 0.766153990196312920f, -0.642657033966226860f, 0.766030748169509000f, + -0.642803930338685990f, + 0.765907477977944340f, -0.642950803077082080f, 0.765784179626150970f, + -0.643097652176015110f, + 0.765660853118662500f, -0.643244477630085850f, 0.765537498460013070f, + -0.643391279433895850f, + 0.765414115654738270f, -0.643538057582047740f, 0.765290704707374370f, + -0.643684812069144850f, + 0.765167265622458960f, -0.643831542889791390f, 0.765043798404530520f, + -0.643978250038592660f, + 0.764920303058128410f, -0.644124933510154540f, 0.764796779587793460f, + -0.644271593299083790f, + 0.764673227998067140f, -0.644418229399988380f, 0.764549648293492150f, + -0.644564841807476640f, + 0.764426040478612070f, -0.644711430516158310f, 0.764302404557971720f, + -0.644857995520643710f, + 0.764178740536116670f, -0.645004536815543930f, 0.764055048417593970f, + -0.645151054395471160f, + 0.763931328206951090f, -0.645297548255038380f, 0.763807579908737160f, + -0.645444018388859230f, + 0.763683803527501870f, -0.645590464791548690f, 0.763559999067796150f, + -0.645736887457722290f, + 0.763436166534172010f, -0.645883286381996320f, 0.763312305931182380f, + -0.646029661558988330f, + 0.763188417263381270f, -0.646176012983316280f, 0.763064500535323710f, + -0.646322340649599480f, + 0.762940555751565720f, -0.646468644552457780f, 0.762816582916664430f, + -0.646614924686512050f, + 0.762692582035177980f, -0.646761181046383920f, 0.762568553111665380f, + -0.646907413626696020f, + 0.762444496150687210f, -0.647053622422071540f, 0.762320411156804270f, + -0.647199807427135230f, + 0.762196298134578900f, -0.647345968636512060f, 0.762072157088574560f, + -0.647492106044828100f, + 0.761947988023355390f, -0.647638219646710310f, 0.761823790943486960f, + -0.647784309436786440f, + 0.761699565853535380f, -0.647930375409685340f, 0.761575312758068000f, + -0.648076417560036530f, + 0.761451031661653620f, -0.648222435882470420f, 0.761326722568861360f, + -0.648368430371618290f, + 0.761202385484261780f, -0.648514401022112440f, 0.761078020412426560f, + -0.648660347828585840f, + 0.760953627357928150f, -0.648806270785672550f, 0.760829206325340010f, + -0.648952169888007300f, + 0.760704757319236920f, -0.649098045130225950f, 0.760580280344194450f, + -0.649243896506964900f, + 0.760455775404789260f, -0.649389724012861660f, 0.760331242505599030f, + -0.649535527642554730f, + 0.760206681651202420f, -0.649681307390683190f, 0.760082092846179340f, + -0.649827063251887100f, + 0.759957476095110330f, -0.649972795220807530f, 0.759832831402577400f, + -0.650118503292086200f, + 0.759708158773163440f, -0.650264187460365850f, 0.759583458211452010f, + -0.650409847720290310f, + 0.759458729722028210f, -0.650555484066503880f, 0.759333973309477940f, + -0.650701096493652040f, + 0.759209188978388070f, -0.650846684996380880f, 0.759084376733346610f, + -0.650992249569337660f, + 0.758959536578942440f, -0.651137790207170330f, 0.758834668519765660f, + -0.651283306904527740f, + 0.758709772560407390f, -0.651428799656059820f, 0.758584848705459610f, + -0.651574268456416970f, + 0.758459896959515430f, -0.651719713300250910f, 0.758334917327168960f, + -0.651865134182213920f, + 0.758209909813015280f, -0.652010531096959500f, 0.758084874421650730f, + -0.652155904039141590f, + 0.757959811157672300f, -0.652301253003415460f, 0.757834720025678310f, + -0.652446577984436730f, + 0.757709601030268080f, -0.652591878976862440f, 0.757584454176041810f, + -0.652737155975350310f, + 0.757459279467600720f, -0.652882408974558850f, 0.757334076909547130f, + -0.653027637969147530f, + 0.757208846506484570f, -0.653172842953776760f, 0.757083588263017140f, + -0.653318023923107670f, + 0.756958302183750490f, -0.653463180871802330f, 0.756832988273290820f, + -0.653608313794523890f, + 0.756707646536245670f, -0.653753422685936060f, 0.756582276977223470f, + -0.653898507540703780f, + 0.756456879600833740f, -0.654043568353492640f, 0.756331454411686920f, + -0.654188605118969040f, + 0.756206001414394540f, -0.654333617831800440f, 0.756080520613569120f, + -0.654478606486655350f, + 0.755955012013824420f, -0.654623571078202680f, 0.755829475619774760f, + -0.654768511601112600f, + 0.755703911436035880f, -0.654913428050056030f, 0.755578319467224540f, + -0.655058320419704910f, + 0.755452699717958250f, -0.655203188704731820f, 0.755327052192855670f, + -0.655348032899810470f, + 0.755201376896536550f, -0.655492852999615350f, 0.755075673833621620f, + -0.655637648998821820f, + 0.754949943008732640f, -0.655782420892106030f, 0.754824184426492350f, + -0.655927168674145360f, + 0.754698398091524500f, -0.656071892339617600f, 0.754572584008453840f, + -0.656216591883201920f, + 0.754446742181906440f, -0.656361267299578000f, 0.754320872616508820f, + -0.656505918583426550f, + 0.754194975316889170f, -0.656650545729428940f, 0.754069050287676120f, + -0.656795148732268070f, + 0.753943097533499640f, -0.656939727586627110f, 0.753817117058990790f, + -0.657084282287190180f, + 0.753691108868781210f, -0.657228812828642540f, 0.753565072967504300f, + -0.657373319205670210f, + 0.753439009359793580f, -0.657517801412960120f, 0.753312918050284330f, + -0.657662259445200070f, + 0.753186799043612520f, -0.657806693297078640f, 0.753060652344415100f, + -0.657951102963285520f, + 0.752934477957330150f, -0.658095488438511180f, 0.752808275886996950f, + -0.658239849717446870f, + 0.752682046138055340f, -0.658384186794785050f, 0.752555788715146390f, + -0.658528499665218650f, + 0.752429503622912390f, -0.658672788323441890f, 0.752303190865996400f, + -0.658817052764149480f, + 0.752176850449042810f, -0.658961292982037320f, 0.752050482376696360f, + -0.659105508971802090f, + 0.751924086653603550f, -0.659249700728141490f, 0.751797663284411550f, + -0.659393868245753860f, + 0.751671212273768430f, -0.659538011519338660f, 0.751544733626323680f, + -0.659682130543596150f, + 0.751418227346727470f, -0.659826225313227320f, 0.751291693439630870f, + -0.659970295822934540f, + 0.751165131909686480f, -0.660114342067420480f, 0.751038542761547360f, + -0.660258364041389050f, + 0.750911925999867890f, -0.660402361739545030f, 0.750785281629303690f, + -0.660546335156593890f, + 0.750658609654510700f, -0.660690284287242300f, 0.750531910080146410f, + -0.660834209126197610f, + 0.750405182910869330f, -0.660978109668168060f, 0.750278428151338720f, + -0.661121985907862860f, + 0.750151645806215070f, -0.661265837839992270f, 0.750024835880159780f, + -0.661409665459266940f, + 0.749897998377835330f, -0.661553468760398890f, 0.749771133303905100f, + -0.661697247738101010f, + 0.749644240663033480f, -0.661841002387086870f, 0.749517320459886170f, + -0.661984732702070920f, + 0.749390372699129560f, -0.662128438677768720f, 0.749263397385431130f, + -0.662272120308896590f, + 0.749136394523459370f, -0.662415777590171780f, 0.749009364117883880f, + -0.662559410516312290f, + 0.748882306173375150f, -0.662703019082037440f, 0.748755220694604760f, + -0.662846603282066900f, + 0.748628107686245440f, -0.662990163111121470f, 0.748500967152970430f, + -0.663133698563923010f, + 0.748373799099454560f, -0.663277209635194100f, 0.748246603530373420f, + -0.663420696319658280f, + 0.748119380450403600f, -0.663564158612039770f, 0.747992129864222700f, + -0.663707596507064010f, + 0.747864851776509410f, -0.663851009999457340f, 0.747737546191943330f, + -0.663994399083946640f, + 0.747610213115205150f, -0.664137763755260010f, 0.747482852550976570f, + -0.664281104008126230f, + 0.747355464503940190f, -0.664424419837275180f, 0.747228048978779920f, + -0.664567711237437520f, + 0.747100605980180130f, -0.664710978203344790f, 0.746973135512826850f, + -0.664854220729729660f, + 0.746845637581406540f, -0.664997438811325340f, 0.746718112190607130f, + -0.665140632442866140f, + 0.746590559345117310f, -0.665283801619087180f, 0.746462979049626770f, + -0.665426946334724660f, + 0.746335371308826320f, -0.665570066584515450f, 0.746207736127407760f, + -0.665713162363197550f, + 0.746080073510063780f, -0.665856233665509720f, 0.745952383461488290f, + -0.665999280486191500f, + 0.745824665986376090f, -0.666142302819983540f, 0.745696921089422760f, + -0.666285300661627280f, + 0.745569148775325430f, -0.666428274005865240f, 0.745441349048781680f, + -0.666571222847440640f, + 0.745313521914490520f, -0.666714147181097670f, 0.745185667377151640f, + -0.666857047001581220f, + 0.745057785441466060f, -0.666999922303637470f, 0.744929876112135350f, + -0.667142773082013310f, + 0.744801939393862630f, -0.667285599331456370f, 0.744673975291351710f, + -0.667428401046715520f, + 0.744545983809307370f, -0.667571178222540310f, 0.744417964952435620f, + -0.667713930853681030f, + 0.744289918725443260f, -0.667856658934889320f, 0.744161845133038180f, + -0.667999362460917400f, + 0.744033744179929290f, -0.668142041426518450f, 0.743905615870826490f, + -0.668284695826446670f, + 0.743777460210440890f, -0.668427325655456820f, 0.743649277203484060f, + -0.668569930908304970f, + 0.743521066854669120f, -0.668712511579747980f, 0.743392829168709970f, + -0.668855067664543610f, + 0.743264564150321600f, -0.668997599157450270f, 0.743136271804219820f, + -0.669140106053227600f, + 0.743007952135121720f, -0.669282588346636010f, 0.742879605147745200f, + -0.669425046032436910f, + 0.742751230846809050f, -0.669567479105392490f, 0.742622829237033490f, + -0.669709887560265840f, + 0.742494400323139180f, -0.669852271391821020f, 0.742365944109848460f, + -0.669994630594823000f, + 0.742237460601884000f, -0.670136965164037650f, 0.742108949803969910f, + -0.670279275094231800f, + 0.741980411720831070f, -0.670421560380173090f, 0.741851846357193480f, + -0.670563821016630040f, + 0.741723253717784140f, -0.670706056998372160f, 0.741594633807331150f, + -0.670848268320169640f, + 0.741465986630563290f, -0.670990454976794220f, 0.741337312192210660f, + -0.671132616963017740f, + 0.741208610497004260f, -0.671274754273613490f, 0.741079881549676080f, + -0.671416866903355450f, + 0.740951125354959110f, -0.671558954847018330f, 0.740822341917587330f, + -0.671701018099378320f, + 0.740693531242295760f, -0.671843056655211930f, 0.740564693333820250f, + -0.671985070509296900f, + 0.740435828196898020f, -0.672127059656411730f, 0.740306935836266940f, + -0.672269024091335930f, + 0.740178016256666240f, -0.672410963808849790f, 0.740049069462835550f, + -0.672552878803734710f, + 0.739920095459516200f, -0.672694769070772860f, 0.739791094251449950f, + -0.672836634604747300f, + 0.739662065843380010f, -0.672978475400442090f, 0.739533010240050250f, + -0.673120291452642070f, + 0.739403927446205760f, -0.673262082756132970f, 0.739274817466592520f, + -0.673403849305701740f, + 0.739145680305957510f, -0.673545591096136100f, 0.739016515969048720f, + -0.673687308122224330f, + 0.738887324460615110f, -0.673829000378756040f, 0.738758105785406900f, + -0.673970667860521620f, + 0.738628859948174840f, -0.674112310562312360f, 0.738499586953671130f, + -0.674253928478920410f, + 0.738370286806648620f, -0.674395521605139050f, 0.738240959511861310f, + -0.674537089935762000f, + 0.738111605074064260f, -0.674678633465584540f, 0.737982223498013570f, + -0.674820152189402170f, + 0.737852814788465980f, -0.674961646102011930f, 0.737723378950179700f, + -0.675103115198211420f, + 0.737593915987913570f, -0.675244559472799270f, 0.737464425906427580f, + -0.675385978920574840f, + 0.737334908710482910f, -0.675527373536338520f, 0.737205364404841190f, + -0.675668743314891910f, + 0.737075792994265730f, -0.675810088251036940f, 0.736946194483520280f, + -0.675951408339577010f, + 0.736816568877369900f, -0.676092703575315920f, 0.736686916180580460f, + -0.676233973953058950f, + 0.736557236397919150f, -0.676375219467611590f, 0.736427529534153690f, + -0.676516440113781090f, + 0.736297795594053170f, -0.676657635886374950f, 0.736168034582387330f, + -0.676798806780201770f, + 0.736038246503927350f, -0.676939952790071130f, 0.735908431363445190f, + -0.677081073910793530f, + 0.735778589165713590f, -0.677222170137180330f, 0.735648719915506510f, + -0.677363241464043920f, + 0.735518823617598900f, -0.677504287886197430f, 0.735388900276766730f, + -0.677645309398454910f, + 0.735258949897786840f, -0.677786305995631500f, 0.735128972485437180f, + -0.677927277672543020f, + 0.734998968044496710f, -0.678068224424006600f, 0.734868936579745170f, + -0.678209146244839860f, + 0.734738878095963500f, -0.678350043129861470f, 0.734608792597933550f, + -0.678490915073891140f, + 0.734478680090438370f, -0.678631762071749360f, 0.734348540578261600f, + -0.678772584118257690f, + 0.734218374066188280f, -0.678913381208238410f, 0.734088180559004040f, + -0.679054153336514870f, + 0.733957960061495940f, -0.679194900497911200f, 0.733827712578451700f, + -0.679335622687252560f, + 0.733697438114660370f, -0.679476319899364970f, 0.733567136674911360f, + -0.679616992129075560f, + 0.733436808263995710f, -0.679757639371212030f, 0.733306452886705260f, + -0.679898261620603290f, + 0.733176070547832740f, -0.680038858872078930f, 0.733045661252172080f, + -0.680179431120469750f, + 0.732915225004517780f, -0.680319978360607200f, 0.732784761809665790f, + -0.680460500587323880f, + 0.732654271672412820f, -0.680600997795453020f, 0.732523754597556700f, + -0.680741469979829090f, + 0.732393210589896040f, -0.680881917135287230f, 0.732262639654230770f, + -0.681022339256663670f, + 0.732132041795361290f, -0.681162736338795430f, 0.732001417018089630f, + -0.681303108376520530f, + 0.731870765327218290f, -0.681443455364677870f, 0.731740086727550980f, + -0.681583777298107480f, + 0.731609381223892630f, -0.681724074171649710f, 0.731478648821048520f, + -0.681864345980146670f, + 0.731347889523825570f, -0.682004592718440830f, 0.731217103337031270f, + -0.682144814381375640f, + 0.731086290265474340f, -0.682285010963795570f, 0.730955450313964360f, + -0.682425182460546060f, + 0.730824583487312160f, -0.682565328866473250f, 0.730693689790329000f, + -0.682705450176424590f, + 0.730562769227827590f, -0.682845546385248080f, 0.730431821804621520f, + -0.682985617487792740f, + 0.730300847525525490f, -0.683125663478908680f, 0.730169846395354870f, + -0.683265684353446700f, + 0.730038818418926260f, -0.683405680106258680f, 0.729907763601057140f, + -0.683545650732197530f, + 0.729776681946566090f, -0.683685596226116580f, 0.729645573460272480f, + -0.683825516582870720f, + 0.729514438146997010f, -0.683965411797315400f, 0.729383276011561050f, + -0.684105281864307080f, + 0.729252087058786970f, -0.684245126778703080f, 0.729120871293498230f, + -0.684384946535361750f, + 0.728989628720519420f, -0.684524741129142300f, 0.728858359344675800f, + -0.684664510554904960f, + 0.728727063170793830f, -0.684804254807510620f, 0.728595740203700770f, + -0.684943973881821490f, + 0.728464390448225200f, -0.685083667772700360f, 0.728333013909196360f, + -0.685223336475011210f, + 0.728201610591444610f, -0.685362979983618730f, 0.728070180499801210f, + -0.685502598293388550f, + 0.727938723639098620f, -0.685642191399187470f, 0.727807240014169960f, + -0.685781759295883030f, + 0.727675729629849610f, -0.685921301978343560f, 0.727544192490972800f, + -0.686060819441438710f, + 0.727412628602375770f, -0.686200311680038590f, 0.727281037968895870f, + -0.686339778689014520f, + 0.727149420595371020f, -0.686479220463238950f, 0.727017776486640680f, + -0.686618636997584630f, + 0.726886105647544970f, -0.686758028286925890f, 0.726754408082925020f, + -0.686897394326137610f, + 0.726622683797622850f, -0.687036735110095660f, 0.726490932796481910f, + -0.687176050633676820f, + 0.726359155084346010f, -0.687315340891759050f, 0.726227350666060370f, + -0.687454605879221030f, + 0.726095519546471000f, -0.687593845590942170f, 0.725963661730424930f, + -0.687733060021803230f, + 0.725831777222770370f, -0.687872249166685550f, 0.725699866028356120f, + -0.688011413020471640f, + 0.725567928152032300f, -0.688150551578044830f, 0.725435963598649810f, + -0.688289664834289330f, + 0.725303972373060770f, -0.688428752784090440f, 0.725171954480117950f, + -0.688567815422334250f, + 0.725039909924675370f, -0.688706852743907750f, 0.724907838711587820f, + -0.688845864743699020f, + 0.724775740845711280f, -0.688984851416597040f, 0.724643616331902550f, + -0.689123812757491570f, + 0.724511465175019630f, -0.689262748761273470f, 0.724379287379921190f, + -0.689401659422834270f, + 0.724247082951467000f, -0.689540544737066830f, 0.724114851894517850f, + -0.689679404698864800f, + 0.723982594213935520f, -0.689818239303122470f, 0.723850309914582880f, + -0.689957048544735390f, + 0.723717999001323500f, -0.690095832418599950f, 0.723585661479022150f, + -0.690234590919613370f, + 0.723453297352544380f, -0.690373324042674040f, 0.723320906626756970f, + -0.690512031782681060f, + 0.723188489306527460f, -0.690650714134534600f, 0.723056045396724410f, + -0.690789371093135650f, + 0.722923574902217700f, -0.690928002653386160f, 0.722791077827877550f, + -0.691066608810189220f, + 0.722658554178575610f, -0.691205189558448450f, 0.722526003959184540f, + -0.691343744893068710f, + 0.722393427174577550f, -0.691482274808955850f, 0.722260823829629310f, + -0.691620779301016290f, + 0.722128193929215350f, -0.691759258364157750f, 0.721995537478211880f, + -0.691897711993288760f, + 0.721862854481496340f, -0.692036140183318720f, 0.721730144943947160f, + -0.692174542929158140f, + 0.721597408870443770f, -0.692312920225718220f, 0.721464646265866370f, + -0.692451272067911130f, + 0.721331857135096290f, -0.692589598450650380f, 0.721199041483015720f, + -0.692727899368849820f, + 0.721066199314508110f, -0.692866174817424630f, 0.720933330634457530f, + -0.693004424791290870f, + 0.720800435447749190f, -0.693142649285365400f, 0.720667513759269520f, + -0.693280848294566040f, + 0.720534565573905270f, -0.693419021813811760f, 0.720401590896544760f, + -0.693557169838022290f, + 0.720268589732077190f, -0.693695292362118240f, 0.720135562085392420f, + -0.693833389381021350f, + 0.720002507961381650f, -0.693971460889654000f, 0.719869427364936860f, + -0.694109506882939820f, + 0.719736320300951030f, -0.694247527355803310f, 0.719603186774318120f, + -0.694385522303169740f, + 0.719470026789932990f, -0.694523491719965520f, 0.719336840352691740f, + -0.694661435601117820f, + 0.719203627467491220f, -0.694799353941554900f, 0.719070388139229190f, + -0.694937246736205830f, + 0.718937122372804490f, -0.695075113980000880f, 0.718803830173116890f, + -0.695212955667870780f, + 0.718670511545067230f, -0.695350771794747690f, 0.718537166493557370f, + -0.695488562355564440f, + 0.718403795023489830f, -0.695626327345254870f, 0.718270397139768260f, + -0.695764066758753690f, + 0.718136972847297490f, -0.695901780590996830f, 0.718003522150983180f, + -0.696039468836920690f, + 0.717870045055731710f, -0.696177131491462990f, 0.717736541566450950f, + -0.696314768549562090f, + 0.717603011688049080f, -0.696452380006157830f, 0.717469455425435830f, + -0.696589965856190370f, + 0.717335872783521730f, -0.696727526094601200f, 0.717202263767218070f, + -0.696865060716332470f, + 0.717068628381437480f, -0.697002569716327460f, 0.716934966631093130f, + -0.697140053089530420f, + 0.716801278521099540f, -0.697277510830886520f, 0.716667564056371890f, + -0.697414942935341790f, + 0.716533823241826680f, -0.697552349397843160f, 0.716400056082381000f, + -0.697689730213338800f, + 0.716266262582953120f, -0.697827085376777290f, 0.716132442748462330f, + -0.697964414883108670f, + 0.715998596583828690f, -0.698101718727283770f, 0.715864724093973500f, + -0.698238996904254280f, + 0.715730825283818590f, -0.698376249408972920f, 0.715596900158287470f, + -0.698513476236393040f, + 0.715462948722303760f, -0.698650677381469460f, 0.715328970980792620f, + -0.698787852839157670f, + 0.715194966938680120f, -0.698925002604414150f, 0.715060936600893090f, + -0.699062126672196140f, + 0.714926879972359490f, -0.699199225037462120f, 0.714792797058008240f, + -0.699336297695171140f, + 0.714658687862769090f, -0.699473344640283770f, 0.714524552391572860f, + -0.699610365867761040f, + 0.714390390649351390f, -0.699747361372564990f, 0.714256202641037510f, + -0.699884331149658760f, + 0.714121988371564820f, -0.700021275194006250f, 0.713987747845867830f, + -0.700158193500572730f, + 0.713853481068882470f, -0.700295086064323780f, 0.713719188045545240f, + -0.700431952880226420f, + 0.713584868780793640f, -0.700568793943248340f, 0.713450523279566260f, + -0.700705609248358450f, + 0.713316151546802610f, -0.700842398790526120f, 0.713181753587443180f, + -0.700979162564722370f, + 0.713047329406429340f, -0.701115900565918660f, 0.712912879008703480f, + -0.701252612789087460f, + 0.712778402399208980f, -0.701389299229202230f, 0.712643899582890210f, + -0.701525959881237340f, + 0.712509370564692320f, -0.701662594740168450f, 0.712374815349561710f, + -0.701799203800971720f, + 0.712240233942445510f, -0.701935787058624360f, 0.712105626348291890f, + -0.702072344508104630f, + 0.711970992572050100f, -0.702208876144391870f, 0.711836332618670080f, + -0.702345381962465880f, + 0.711701646493102970f, -0.702481861957308000f, 0.711566934200300700f, + -0.702618316123900130f, + 0.711432195745216430f, -0.702754744457225300f, 0.711297431132803970f, + -0.702891146952267400f, + 0.711162640368018350f, -0.703027523604011220f, 0.711027823455815280f, + -0.703163874407442770f, + 0.710892980401151680f, -0.703300199357548730f, 0.710758111208985350f, + -0.703436498449316660f, + 0.710623215884275020f, -0.703572771677735580f, 0.710488294431980470f, + -0.703709019037794810f, + 0.710353346857062420f, -0.703845240524484940f, 0.710218373164482220f, + -0.703981436132797620f, + 0.710083373359202800f, -0.704117605857725310f, 0.709948347446187400f, + -0.704253749694261470f, + 0.709813295430400840f, -0.704389867637400410f, 0.709678217316808580f, + -0.704525959682137380f, + 0.709543113110376770f, -0.704662025823468820f, 0.709407982816072980f, + -0.704798066056391950f, + 0.709272826438865690f, -0.704934080375904880f, 0.709137643983724030f, + -0.705070068777006840f, + 0.709002435455618250f, -0.705206031254697830f, 0.708867200859519820f, + -0.705341967803978840f, + 0.708731940200400650f, -0.705477878419852100f, 0.708596653483234080f, + -0.705613763097320490f, + 0.708461340712994160f, -0.705749621831387790f, 0.708326001894655890f, + -0.705885454617058980f, + 0.708190637033195400f, -0.706021261449339740f, 0.708055246133589500f, + -0.706157042323237060f, + 0.707919829200816310f, -0.706292797233758480f, 0.707784386239854620f, + -0.706428526175912790f, + 0.707648917255684350f, -0.706564229144709510f, 0.707513422253286280f, + -0.706699906135159430f, + 0.707377901237642100f, -0.706835557142273750f, 0.707242354213734710f, + -0.706971182161065360f, + 0.707106781186547570f, -0.707106781186547460f, 0.706971182161065360f, + -0.707242354213734600f, + 0.706835557142273860f, -0.707377901237642100f, 0.706699906135159430f, + -0.707513422253286170f, + 0.706564229144709620f, -0.707648917255684350f, 0.706428526175912790f, + -0.707784386239854620f, + 0.706292797233758480f, -0.707919829200816310f, 0.706157042323237060f, + -0.708055246133589500f, + 0.706021261449339740f, -0.708190637033195290f, 0.705885454617058980f, + -0.708326001894655780f, + 0.705749621831387790f, -0.708461340712994050f, 0.705613763097320490f, + -0.708596653483234080f, + 0.705477878419852210f, -0.708731940200400650f, 0.705341967803978950f, + -0.708867200859519820f, + 0.705206031254697830f, -0.709002435455618250f, 0.705070068777006840f, + -0.709137643983723920f, + 0.704934080375904990f, -0.709272826438865580f, 0.704798066056391950f, + -0.709407982816072980f, + 0.704662025823468930f, -0.709543113110376770f, 0.704525959682137380f, + -0.709678217316808470f, + 0.704389867637400410f, -0.709813295430400840f, 0.704253749694261580f, + -0.709948347446187400f, + 0.704117605857725430f, -0.710083373359202690f, 0.703981436132797730f, + -0.710218373164482220f, + 0.703845240524484940f, -0.710353346857062310f, 0.703709019037794810f, + -0.710488294431980470f, + 0.703572771677735580f, -0.710623215884275020f, 0.703436498449316770f, + -0.710758111208985350f, + 0.703300199357548730f, -0.710892980401151680f, 0.703163874407442770f, + -0.711027823455815280f, + 0.703027523604011220f, -0.711162640368018350f, 0.702891146952267400f, + -0.711297431132803970f, + 0.702754744457225300f, -0.711432195745216430f, 0.702618316123900130f, + -0.711566934200300700f, + 0.702481861957308000f, -0.711701646493102970f, 0.702345381962465880f, + -0.711836332618670080f, + 0.702208876144391870f, -0.711970992572049990f, 0.702072344508104740f, + -0.712105626348291890f, + 0.701935787058624360f, -0.712240233942445510f, 0.701799203800971720f, + -0.712374815349561710f, + 0.701662594740168570f, -0.712509370564692320f, 0.701525959881237450f, + -0.712643899582890210f, + 0.701389299229202230f, -0.712778402399208870f, 0.701252612789087460f, + -0.712912879008703370f, + 0.701115900565918660f, -0.713047329406429230f, 0.700979162564722480f, + -0.713181753587443070f, + 0.700842398790526230f, -0.713316151546802610f, 0.700705609248358450f, + -0.713450523279566150f, + 0.700568793943248450f, -0.713584868780793520f, 0.700431952880226420f, + -0.713719188045545130f, + 0.700295086064323780f, -0.713853481068882470f, 0.700158193500572730f, + -0.713987747845867830f, + 0.700021275194006360f, -0.714121988371564710f, 0.699884331149658760f, + -0.714256202641037400f, + 0.699747361372564990f, -0.714390390649351390f, 0.699610365867761040f, + -0.714524552391572860f, + 0.699473344640283770f, -0.714658687862768980f, 0.699336297695171250f, + -0.714792797058008130f, + 0.699199225037462120f, -0.714926879972359370f, 0.699062126672196140f, + -0.715060936600892980f, + 0.698925002604414150f, -0.715194966938680010f, 0.698787852839157790f, + -0.715328970980792620f, + 0.698650677381469580f, -0.715462948722303650f, 0.698513476236393040f, + -0.715596900158287360f, + 0.698376249408972920f, -0.715730825283818590f, 0.698238996904254390f, + -0.715864724093973390f, + 0.698101718727283880f, -0.715998596583828690f, 0.697964414883108790f, + -0.716132442748462330f, + 0.697827085376777290f, -0.716266262582953120f, 0.697689730213338800f, + -0.716400056082380890f, + 0.697552349397843270f, -0.716533823241826570f, 0.697414942935341790f, + -0.716667564056371890f, + 0.697277510830886630f, -0.716801278521099540f, 0.697140053089530530f, + -0.716934966631093130f, + 0.697002569716327460f, -0.717068628381437480f, 0.696865060716332470f, + -0.717202263767218070f, + 0.696727526094601200f, -0.717335872783521730f, 0.696589965856190370f, + -0.717469455425435830f, + 0.696452380006157830f, -0.717603011688049080f, 0.696314768549562200f, + -0.717736541566450840f, + 0.696177131491462990f, -0.717870045055731710f, 0.696039468836920690f, + -0.718003522150983060f, + 0.695901780590996830f, -0.718136972847297490f, 0.695764066758753800f, + -0.718270397139768260f, + 0.695626327345254870f, -0.718403795023489720f, 0.695488562355564440f, + -0.718537166493557370f, + 0.695350771794747800f, -0.718670511545067230f, 0.695212955667870890f, + -0.718803830173116890f, + 0.695075113980000880f, -0.718937122372804380f, 0.694937246736205940f, + -0.719070388139229190f, + 0.694799353941554900f, -0.719203627467491220f, 0.694661435601117930f, + -0.719336840352691740f, + 0.694523491719965520f, -0.719470026789932990f, 0.694385522303169860f, + -0.719603186774318000f, + 0.694247527355803310f, -0.719736320300951030f, 0.694109506882939820f, + -0.719869427364936860f, + 0.693971460889654000f, -0.720002507961381650f, 0.693833389381021350f, + -0.720135562085392310f, + 0.693695292362118350f, -0.720268589732077080f, 0.693557169838022400f, + -0.720401590896544760f, + 0.693419021813811880f, -0.720534565573905270f, 0.693280848294566150f, + -0.720667513759269410f, + 0.693142649285365510f, -0.720800435447749190f, 0.693004424791290870f, + -0.720933330634457530f, + 0.692866174817424740f, -0.721066199314508110f, 0.692727899368849820f, + -0.721199041483015720f, + 0.692589598450650380f, -0.721331857135096180f, 0.692451272067911240f, + -0.721464646265866370f, + 0.692312920225718220f, -0.721597408870443660f, 0.692174542929158140f, + -0.721730144943947160f, + 0.692036140183318830f, -0.721862854481496340f, 0.691897711993288760f, + -0.721995537478211880f, + 0.691759258364157750f, -0.722128193929215350f, 0.691620779301016400f, + -0.722260823829629310f, + 0.691482274808955850f, -0.722393427174577550f, 0.691343744893068820f, + -0.722526003959184430f, + 0.691205189558448450f, -0.722658554178575610f, 0.691066608810189220f, + -0.722791077827877550f, + 0.690928002653386280f, -0.722923574902217700f, 0.690789371093135760f, + -0.723056045396724410f, + 0.690650714134534720f, -0.723188489306527350f, 0.690512031782681170f, + -0.723320906626756850f, + 0.690373324042674040f, -0.723453297352544380f, 0.690234590919613370f, + -0.723585661479022040f, + 0.690095832418599950f, -0.723717999001323390f, 0.689957048544735390f, + -0.723850309914582880f, + 0.689818239303122470f, -0.723982594213935520f, 0.689679404698864800f, + -0.724114851894517850f, + 0.689540544737066940f, -0.724247082951466890f, 0.689401659422834380f, + -0.724379287379921080f, + 0.689262748761273470f, -0.724511465175019520f, 0.689123812757491680f, + -0.724643616331902550f, + 0.688984851416597150f, -0.724775740845711280f, 0.688845864743699130f, + -0.724907838711587820f, + 0.688706852743907750f, -0.725039909924675370f, 0.688567815422334360f, + -0.725171954480117840f, + 0.688428752784090550f, -0.725303972373060660f, 0.688289664834289440f, + -0.725435963598649810f, + 0.688150551578044830f, -0.725567928152032300f, 0.688011413020471640f, + -0.725699866028356120f, + 0.687872249166685550f, -0.725831777222770370f, 0.687733060021803230f, + -0.725963661730424930f, + 0.687593845590942170f, -0.726095519546470890f, 0.687454605879221030f, + -0.726227350666060260f, + 0.687315340891759160f, -0.726359155084346010f, 0.687176050633676930f, + -0.726490932796481910f, + 0.687036735110095660f, -0.726622683797622850f, 0.686897394326137610f, + -0.726754408082924910f, + 0.686758028286925890f, -0.726886105647544970f, 0.686618636997584740f, + -0.727017776486640680f, + 0.686479220463238950f, -0.727149420595371020f, 0.686339778689014630f, + -0.727281037968895760f, + 0.686200311680038700f, -0.727412628602375770f, 0.686060819441438710f, + -0.727544192490972800f, + 0.685921301978343670f, -0.727675729629849610f, 0.685781759295883030f, + -0.727807240014169960f, + 0.685642191399187470f, -0.727938723639098620f, 0.685502598293388670f, + -0.728070180499801210f, + 0.685362979983618730f, -0.728201610591444500f, 0.685223336475011210f, + -0.728333013909196360f, + 0.685083667772700360f, -0.728464390448225200f, 0.684943973881821490f, + -0.728595740203700770f, + 0.684804254807510620f, -0.728727063170793720f, 0.684664510554904960f, + -0.728858359344675690f, + 0.684524741129142300f, -0.728989628720519310f, 0.684384946535361750f, + -0.729120871293498230f, + 0.684245126778703080f, -0.729252087058786970f, 0.684105281864307080f, + -0.729383276011561050f, + 0.683965411797315510f, -0.729514438146996900f, 0.683825516582870830f, + -0.729645573460272480f, + 0.683685596226116690f, -0.729776681946565970f, 0.683545650732197530f, + -0.729907763601057140f, + 0.683405680106258790f, -0.730038818418926150f, 0.683265684353446700f, + -0.730169846395354870f, + 0.683125663478908800f, -0.730300847525525380f, 0.682985617487792850f, + -0.730431821804621520f, + 0.682845546385248080f, -0.730562769227827590f, 0.682705450176424590f, + -0.730693689790328890f, + 0.682565328866473250f, -0.730824583487312050f, 0.682425182460546060f, + -0.730955450313964360f, + 0.682285010963795570f, -0.731086290265474230f, 0.682144814381375640f, + -0.731217103337031160f, + 0.682004592718440830f, -0.731347889523825460f, 0.681864345980146780f, + -0.731478648821048520f, + 0.681724074171649820f, -0.731609381223892520f, 0.681583777298107480f, + -0.731740086727550980f, + 0.681443455364677990f, -0.731870765327218290f, 0.681303108376520530f, + -0.732001417018089520f, + 0.681162736338795430f, -0.732132041795361290f, 0.681022339256663670f, + -0.732262639654230660f, + 0.680881917135287340f, -0.732393210589896040f, 0.680741469979829090f, + -0.732523754597556590f, + 0.680600997795453130f, -0.732654271672412820f, 0.680460500587323880f, + -0.732784761809665790f, + 0.680319978360607200f, -0.732915225004517780f, 0.680179431120469750f, + -0.733045661252171970f, + 0.680038858872079040f, -0.733176070547832740f, 0.679898261620603290f, + -0.733306452886705260f, + 0.679757639371212030f, -0.733436808263995710f, 0.679616992129075560f, + -0.733567136674911360f, + 0.679476319899365080f, -0.733697438114660260f, 0.679335622687252670f, + -0.733827712578451700f, + 0.679194900497911200f, -0.733957960061495940f, 0.679054153336514870f, + -0.734088180559004040f, + 0.678913381208238410f, -0.734218374066188170f, 0.678772584118257690f, + -0.734348540578261600f, + 0.678631762071749470f, -0.734478680090438370f, 0.678490915073891250f, + -0.734608792597933550f, + 0.678350043129861580f, -0.734738878095963390f, 0.678209146244839860f, + -0.734868936579745060f, + 0.678068224424006600f, -0.734998968044496600f, 0.677927277672543130f, + -0.735128972485437180f, + 0.677786305995631500f, -0.735258949897786730f, 0.677645309398454910f, + -0.735388900276766620f, + 0.677504287886197430f, -0.735518823617598900f, 0.677363241464044030f, + -0.735648719915506400f, + 0.677222170137180450f, -0.735778589165713480f, 0.677081073910793530f, + -0.735908431363445190f, + 0.676939952790071240f, -0.736038246503927350f, 0.676798806780201770f, + -0.736168034582387330f, + 0.676657635886374950f, -0.736297795594053060f, 0.676516440113781090f, + -0.736427529534153690f, + 0.676375219467611700f, -0.736557236397919150f, 0.676233973953058950f, + -0.736686916180580460f, + 0.676092703575316030f, -0.736816568877369790f, 0.675951408339577010f, + -0.736946194483520170f, + 0.675810088251037060f, -0.737075792994265620f, 0.675668743314891910f, + -0.737205364404841190f, + 0.675527373536338630f, -0.737334908710482790f, 0.675385978920574950f, + -0.737464425906427580f, + 0.675244559472799270f, -0.737593915987913460f, 0.675103115198211530f, + -0.737723378950179590f, + 0.674961646102012040f, -0.737852814788465980f, 0.674820152189402280f, + -0.737982223498013570f, + 0.674678633465584540f, -0.738111605074064260f, 0.674537089935762110f, + -0.738240959511861310f, + 0.674395521605139050f, -0.738370286806648510f, 0.674253928478920520f, + -0.738499586953671130f, + 0.674112310562312360f, -0.738628859948174840f, 0.673970667860521620f, + -0.738758105785406900f, + 0.673829000378756150f, -0.738887324460615110f, 0.673687308122224330f, + -0.739016515969048600f, + 0.673545591096136100f, -0.739145680305957400f, 0.673403849305701850f, + -0.739274817466592520f, + 0.673262082756132970f, -0.739403927446205760f, 0.673120291452642070f, + -0.739533010240050250f, + 0.672978475400442090f, -0.739662065843379900f, 0.672836634604747410f, + -0.739791094251449950f, + 0.672694769070772970f, -0.739920095459516090f, 0.672552878803734820f, + -0.740049069462835550f, + 0.672410963808849900f, -0.740178016256666240f, 0.672269024091336040f, + -0.740306935836266940f, + 0.672127059656411840f, -0.740435828196898020f, 0.671985070509296900f, + -0.740564693333820250f, + 0.671843056655211930f, -0.740693531242295640f, 0.671701018099378320f, + -0.740822341917587330f, + 0.671558954847018330f, -0.740951125354959110f, 0.671416866903355450f, + -0.741079881549676080f, + 0.671274754273613490f, -0.741208610497004260f, 0.671132616963017850f, + -0.741337312192210660f, + 0.670990454976794220f, -0.741465986630563290f, 0.670848268320169750f, + -0.741594633807331150f, + 0.670706056998372160f, -0.741723253717784140f, 0.670563821016630040f, + -0.741851846357193480f, + 0.670421560380173090f, -0.741980411720830960f, 0.670279275094231910f, + -0.742108949803969800f, + 0.670136965164037760f, -0.742237460601884000f, 0.669994630594823000f, + -0.742365944109848460f, + 0.669852271391821130f, -0.742494400323139180f, 0.669709887560265840f, + -0.742622829237033380f, + 0.669567479105392490f, -0.742751230846809050f, 0.669425046032436910f, + -0.742879605147745090f, + 0.669282588346636010f, -0.743007952135121720f, 0.669140106053227710f, + -0.743136271804219820f, + 0.668997599157450270f, -0.743264564150321490f, 0.668855067664543610f, + -0.743392829168709970f, + 0.668712511579748090f, -0.743521066854669120f, 0.668569930908305080f, + -0.743649277203484060f, + 0.668427325655456820f, -0.743777460210440780f, 0.668284695826446670f, + -0.743905615870826490f, + 0.668142041426518560f, -0.744033744179929180f, 0.667999362460917510f, + -0.744161845133038070f, + 0.667856658934889440f, -0.744289918725443140f, 0.667713930853681140f, + -0.744417964952435620f, + 0.667571178222540310f, -0.744545983809307250f, 0.667428401046715640f, + -0.744673975291351600f, + 0.667285599331456480f, -0.744801939393862630f, 0.667142773082013310f, + -0.744929876112135350f, + 0.666999922303637470f, -0.745057785441465950f, 0.666857047001581220f, + -0.745185667377151640f, + 0.666714147181097670f, -0.745313521914490410f, 0.666571222847440750f, + -0.745441349048781680f, + 0.666428274005865350f, -0.745569148775325430f, 0.666285300661627390f, + -0.745696921089422760f, + 0.666142302819983540f, -0.745824665986375980f, 0.665999280486191500f, + -0.745952383461488180f, + 0.665856233665509720f, -0.746080073510063780f, 0.665713162363197660f, + -0.746207736127407650f, + 0.665570066584515560f, -0.746335371308826320f, 0.665426946334724660f, + -0.746462979049626770f, + 0.665283801619087180f, -0.746590559345117310f, 0.665140632442866140f, + -0.746718112190607020f, + 0.664997438811325340f, -0.746845637581406540f, 0.664854220729729660f, + -0.746973135512826740f, + 0.664710978203344900f, -0.747100605980180130f, 0.664567711237437520f, + -0.747228048978779920f, + 0.664424419837275180f, -0.747355464503940190f, 0.664281104008126230f, + -0.747482852550976570f, + 0.664137763755260010f, -0.747610213115205150f, 0.663994399083946640f, + -0.747737546191943330f, + 0.663851009999457340f, -0.747864851776509410f, 0.663707596507064120f, + -0.747992129864222700f, + 0.663564158612039880f, -0.748119380450403490f, 0.663420696319658280f, + -0.748246603530373420f, + 0.663277209635194100f, -0.748373799099454560f, 0.663133698563923010f, + -0.748500967152970430f, + 0.662990163111121470f, -0.748628107686245330f, 0.662846603282066900f, + -0.748755220694604760f, + 0.662703019082037440f, -0.748882306173375030f, 0.662559410516312400f, + -0.749009364117883770f, + 0.662415777590171780f, -0.749136394523459260f, 0.662272120308896590f, + -0.749263397385431020f, + 0.662128438677768720f, -0.749390372699129560f, 0.661984732702071030f, + -0.749517320459886170f, + 0.661841002387086870f, -0.749644240663033480f, 0.661697247738101120f, + -0.749771133303904990f, + 0.661553468760399000f, -0.749897998377835220f, 0.661409665459266940f, + -0.750024835880159780f, + 0.661265837839992270f, -0.750151645806214960f, 0.661121985907862970f, + -0.750278428151338610f, + 0.660978109668168060f, -0.750405182910869220f, 0.660834209126197610f, + -0.750531910080146410f, + 0.660690284287242300f, -0.750658609654510590f, 0.660546335156593890f, + -0.750785281629303580f, + 0.660402361739545030f, -0.750911925999867890f, 0.660258364041389050f, + -0.751038542761547250f, + 0.660114342067420480f, -0.751165131909686370f, 0.659970295822934540f, + -0.751291693439630870f, + 0.659826225313227430f, -0.751418227346727360f, 0.659682130543596150f, + -0.751544733626323570f, + 0.659538011519338770f, -0.751671212273768430f, 0.659393868245753970f, + -0.751797663284411440f, + 0.659249700728141490f, -0.751924086653603550f, 0.659105508971802200f, + -0.752050482376696360f, + 0.658961292982037320f, -0.752176850449042700f, 0.658817052764149480f, + -0.752303190865996400f, + 0.658672788323441890f, -0.752429503622912390f, 0.658528499665218760f, + -0.752555788715146390f, + 0.658384186794785050f, -0.752682046138055230f, 0.658239849717446980f, + -0.752808275886996950f, + 0.658095488438511290f, -0.752934477957330150f, 0.657951102963285630f, + -0.753060652344415100f, + 0.657806693297078640f, -0.753186799043612410f, 0.657662259445200070f, + -0.753312918050284330f, + 0.657517801412960120f, -0.753439009359793580f, 0.657373319205670210f, + -0.753565072967504190f, + 0.657228812828642650f, -0.753691108868781210f, 0.657084282287190180f, + -0.753817117058990680f, + 0.656939727586627110f, -0.753943097533499640f, 0.656795148732268070f, + -0.754069050287676120f, + 0.656650545729429050f, -0.754194975316889170f, 0.656505918583426550f, + -0.754320872616508820f, + 0.656361267299578000f, -0.754446742181906330f, 0.656216591883202030f, + -0.754572584008453840f, + 0.656071892339617710f, -0.754698398091524390f, 0.655927168674145360f, + -0.754824184426492240f, + 0.655782420892106030f, -0.754949943008732640f, 0.655637648998821820f, + -0.755075673833621510f, + 0.655492852999615460f, -0.755201376896536550f, 0.655348032899810580f, + -0.755327052192855560f, + 0.655203188704731930f, -0.755452699717958140f, 0.655058320419704910f, + -0.755578319467224540f, + 0.654913428050056150f, -0.755703911436035880f, 0.654768511601112600f, + -0.755829475619774760f, + 0.654623571078202680f, -0.755955012013824310f, 0.654478606486655350f, + -0.756080520613569120f, + 0.654333617831800550f, -0.756206001414394540f, 0.654188605118969040f, + -0.756331454411686920f, + 0.654043568353492640f, -0.756456879600833630f, 0.653898507540703890f, + -0.756582276977223470f, + 0.653753422685936170f, -0.756707646536245670f, 0.653608313794523890f, + -0.756832988273290820f, + 0.653463180871802330f, -0.756958302183750490f, 0.653318023923107670f, + -0.757083588263017140f, + 0.653172842953776760f, -0.757208846506484460f, 0.653027637969147650f, + -0.757334076909547130f, + 0.652882408974558960f, -0.757459279467600720f, 0.652737155975350420f, + -0.757584454176041810f, + 0.652591878976862550f, -0.757709601030268080f, 0.652446577984436840f, + -0.757834720025678310f, + 0.652301253003415460f, -0.757959811157672300f, 0.652155904039141700f, + -0.758084874421650620f, + 0.652010531096959500f, -0.758209909813015280f, 0.651865134182214030f, + -0.758334917327168960f, + 0.651719713300251020f, -0.758459896959515320f, 0.651574268456417080f, + -0.758584848705459500f, + 0.651428799656059820f, -0.758709772560407390f, 0.651283306904527850f, + -0.758834668519765660f, + 0.651137790207170330f, -0.758959536578942440f, 0.650992249569337660f, + -0.759084376733346500f, + 0.650846684996380990f, -0.759209188978387960f, 0.650701096493652040f, + -0.759333973309477940f, + 0.650555484066503990f, -0.759458729722028210f, 0.650409847720290420f, + -0.759583458211452010f, + 0.650264187460365960f, -0.759708158773163440f, 0.650118503292086200f, + -0.759832831402577400f, + 0.649972795220807530f, -0.759957476095110330f, 0.649827063251887100f, + -0.760082092846179220f, + 0.649681307390683190f, -0.760206681651202420f, 0.649535527642554730f, + -0.760331242505599030f, + 0.649389724012861770f, -0.760455775404789260f, 0.649243896506965010f, + -0.760580280344194340f, + 0.649098045130226060f, -0.760704757319236920f, 0.648952169888007410f, + -0.760829206325340010f, + 0.648806270785672550f, -0.760953627357928040f, 0.648660347828585840f, + -0.761078020412426560f, + 0.648514401022112550f, -0.761202385484261780f, 0.648368430371618400f, + -0.761326722568861250f, + 0.648222435882470420f, -0.761451031661653510f, 0.648076417560036530f, + -0.761575312758068000f, + 0.647930375409685460f, -0.761699565853535270f, 0.647784309436786550f, + -0.761823790943486840f, + 0.647638219646710420f, -0.761947988023355390f, 0.647492106044828100f, + -0.762072157088574560f, + 0.647345968636512060f, -0.762196298134578900f, 0.647199807427135230f, + -0.762320411156804160f, + 0.647053622422071650f, -0.762444496150687100f, 0.646907413626696020f, + -0.762568553111665380f, + 0.646761181046383920f, -0.762692582035177870f, 0.646614924686512050f, + -0.762816582916664320f, + 0.646468644552457890f, -0.762940555751565720f, 0.646322340649599590f, + -0.763064500535323710f, + 0.646176012983316390f, -0.763188417263381270f, 0.646029661558988330f, + -0.763312305931182380f, + 0.645883286381996440f, -0.763436166534172010f, 0.645736887457722290f, + -0.763559999067796150f, + 0.645590464791548800f, -0.763683803527501870f, 0.645444018388859230f, + -0.763807579908737160f, + 0.645297548255038380f, -0.763931328206951090f, 0.645151054395471270f, + -0.764055048417593860f, + 0.645004536815544040f, -0.764178740536116670f, 0.644857995520643710f, + -0.764302404557971720f, + 0.644711430516158420f, -0.764426040478612070f, 0.644564841807476750f, + -0.764549648293492150f, + 0.644418229399988380f, -0.764673227998067140f, 0.644271593299083900f, + -0.764796779587793460f, + 0.644124933510154540f, -0.764920303058128410f, 0.643978250038592660f, + -0.765043798404530410f, + 0.643831542889791500f, -0.765167265622458960f, 0.643684812069144960f, + -0.765290704707374260f, + 0.643538057582047850f, -0.765414115654738160f, 0.643391279433895960f, + -0.765537498460013070f, + 0.643244477630085850f, -0.765660853118662390f, 0.643097652176015110f, + -0.765784179626150970f, + 0.642950803077082080f, -0.765907477977944230f, 0.642803930338686100f, + -0.766030748169509000f, + 0.642657033966226860f, -0.766153990196312810f, 0.642510113965105710f, + -0.766277204053824710f, + 0.642363170340724320f, -0.766400389737514120f, 0.642216203098485370f, + -0.766523547242852100f, + 0.642069212243792540f, -0.766646676565310380f, 0.641922197782050170f, + -0.766769777700361920f, + 0.641775159718663500f, -0.766892850643480670f, 0.641628098059038860f, + -0.767015895390141480f, + 0.641481012808583160f, -0.767138911935820400f, 0.641333903972704290f, + -0.767261900275994390f, + 0.641186771556811250f, -0.767384860406141620f, 0.641039615566313390f, + -0.767507792321741270f, + 0.640892436006621380f, -0.767630696018273270f, 0.640745232883146440f, + -0.767753571491219030f, + 0.640598006201301030f, -0.767876418736060610f, 0.640450755966498140f, + -0.767999237748281270f, + 0.640303482184151670f, -0.768122028523365310f, 0.640156184859676620f, + -0.768244791056798220f, + 0.640008863998488440f, -0.768367525344066270f, 0.639861519606004010f, + -0.768490231380656750f, + 0.639714151687640450f, -0.768612909162058270f, 0.639566760248816420f, + -0.768735558683760310f, + 0.639419345294950700f, -0.768858179941253270f, 0.639271906831463510f, + -0.768980772930028870f, + 0.639124444863775730f, -0.769103337645579590f, 0.638976959397309140f, + -0.769225874083399260f, + 0.638829450437486400f, -0.769348382238982280f, 0.638681917989730840f, + -0.769470862107824560f, + 0.638534362059466790f, -0.769593313685422940f, 0.638386782652119680f, + -0.769715736967275020f, + 0.638239179773115390f, -0.769838131948879840f, 0.638091553427880930f, + -0.769960498625737230f, + 0.637943903621844170f, -0.770082836993347900f, 0.637796230360433540f, + -0.770205147047214100f, + 0.637648533649078810f, -0.770327428782838770f, 0.637500813493210310f, + -0.770449682195725960f, + 0.637353069898259130f, -0.770571907281380700f, 0.637205302869657600f, + -0.770694104035309140f, + 0.637057512412838590f, -0.770816272453018430f, 0.636909698533235870f, + -0.770938412530016940f, + 0.636761861236284200f, -0.771060524261813710f, 0.636614000527419230f, + -0.771182607643919220f, + 0.636466116412077180f, -0.771304662671844720f, 0.636318208895695570f, + -0.771426689341102590f, + 0.636170277983712170f, -0.771548687647206300f, 0.636022323681566300f, + -0.771670657585670330f, + 0.635874345994697720f, -0.771792599152010150f, 0.635726344928547180f, + -0.771914512341742350f, + 0.635578320488556230f, -0.772036397150384410f, 0.635430272680167160f, + -0.772158253573455240f, + 0.635282201508823530f, -0.772280081606474320f, 0.635134106979969300f, + -0.772401881244962340f, + 0.634985989099049460f, -0.772523652484441330f, 0.634837847871510100f, + -0.772645395320433860f, + 0.634689683302797850f, -0.772767109748463740f, 0.634541495398360130f, + -0.772888795764056220f, + 0.634393284163645490f, -0.773010453362736990f, 0.634245049604103330f, + -0.773132082540033070f, + 0.634096791725183740f, -0.773253683291472590f, 0.633948510532337810f, + -0.773375255612584470f, + 0.633800206031017280f, -0.773496799498899050f, 0.633651878226674900f, + -0.773618314945947460f, + 0.633503527124764320f, -0.773739801949261840f, 0.633355152730740060f, + -0.773861260504375540f, + 0.633206755050057190f, -0.773982690606822790f, 0.633058334088172250f, + -0.774104092252138940f, + 0.632909889850541860f, -0.774225465435860570f, 0.632761422342624000f, + -0.774346810153525020f, + 0.632612931569877520f, -0.774468126400670860f, 0.632464417537761840f, + -0.774589414172837550f, + 0.632315880251737680f, -0.774710673465565550f, 0.632167319717266030f, + -0.774831904274396850f, + 0.632018735939809060f, -0.774953106594873820f, 0.631870128924829850f, + -0.775074280422540450f, + 0.631721498677792370f, -0.775195425752941310f, 0.631572845204161130f, + -0.775316542581622410f, + 0.631424168509401860f, -0.775437630904130430f, 0.631275468598980870f, + -0.775558690716013580f, + 0.631126745478365340f, -0.775679722012820540f, 0.630977999153023660f, + -0.775800724790101540f, + 0.630829229628424470f, -0.775921699043407580f, 0.630680436910038060f, + -0.776042644768290770f, + 0.630531621003334600f, -0.776163561960304340f, 0.630382781913785940f, + -0.776284450615002400f, + 0.630233919646864480f, -0.776405310727940390f, 0.630085034208043290f, + -0.776526142294674430f, + 0.629936125602796550f, -0.776646945310762060f, 0.629787193836599200f, + -0.776767719771761510f, + 0.629638238914927100f, -0.776888465673232440f, 0.629489260843256740f, + -0.777009183010735290f, + 0.629340259627065750f, -0.777129871779831620f, 0.629191235271832410f, + -0.777250531976084070f, + 0.629042187783036000f, -0.777371163595056200f, 0.628893117166156480f, + -0.777491766632312900f, + 0.628744023426674790f, -0.777612341083419920f, 0.628594906570072660f, + -0.777732886943944050f, + 0.628445766601832710f, -0.777853404209453040f, 0.628296603527438440f, + -0.777973892875515990f, + 0.628147417352374120f, -0.778094352937702790f, 0.627998208082124810f, + -0.778214784391584420f, + 0.627848975722176570f, -0.778335187232733090f, 0.627699720278016240f, + -0.778455561456721900f, + 0.627550441755131530f, -0.778575907059124940f, 0.627401140159011160f, + -0.778696224035517530f, + 0.627251815495144190f, -0.778816512381475870f, 0.627102467769021010f, + -0.778936772092577500f, + 0.626953096986132770f, -0.779057003164400630f, 0.626803703151971310f, + -0.779177205592524680f, + 0.626654286272029460f, -0.779297379372530300f, 0.626504846351800930f, + -0.779417524499998900f, + 0.626355383396779990f, -0.779537640970513150f, 0.626205897412462130f, + -0.779657728779656780f, + 0.626056388404343520f, -0.779777787923014440f, 0.625906856377921210f, + -0.779897818396171890f, + 0.625757301338692900f, -0.780017820194715990f, 0.625607723292157410f, + -0.780137793314234500f, + 0.625458122243814360f, -0.780257737750316590f, 0.625308498199164010f, + -0.780377653498552040f, + 0.625158851163707730f, -0.780497540554531910f, 0.625009181142947460f, + -0.780617398913848290f, + 0.624859488142386450f, -0.780737228572094380f, 0.624709772167528100f, + -0.780857029524864470f, + 0.624560033223877320f, -0.780976801767753750f, 0.624410271316939380f, + -0.781096545296358410f, + 0.624260486452220650f, -0.781216260106276090f, 0.624110678635228510f, + -0.781335946193104870f, + 0.623960847871470770f, -0.781455603552444480f, 0.623810994166456130f, + -0.781575232179895550f, + 0.623661117525694640f, -0.781694832071059390f, 0.623511217954696550f, + -0.781814403221538830f, + 0.623361295458973340f, -0.781933945626937630f, 0.623211350044037270f, + -0.782053459282860300f, + 0.623061381715401370f, -0.782172944184912900f, 0.622911390478579460f, + -0.782292400328702400f, + 0.622761376339086460f, -0.782411827709836420f, 0.622611339302437730f, + -0.782531226323924240f, + 0.622461279374150080f, -0.782650596166575730f, 0.622311196559740320f, + -0.782769937233402050f, + 0.622161090864726930f, -0.782889249520015480f, 0.622010962294628600f, + -0.783008533022029110f, + 0.621860810854965360f, -0.783127787735057310f, 0.621710636551257690f, + -0.783247013654715380f, + 0.621560439389027270f, -0.783366210776619720f, 0.621410219373796150f, + -0.783485379096387820f, + 0.621259976511087660f, -0.783604518609638200f, 0.621109710806425740f, + -0.783723629311990470f, + 0.620959422265335180f, -0.783842711199065230f, 0.620809110893341900f, + -0.783961764266484010f, + 0.620658776695972140f, -0.784080788509869950f, 0.620508419678753360f, + -0.784199783924846570f, + 0.620358039847213830f, -0.784318750507038920f, 0.620207637206882430f, + -0.784437688252072720f, + 0.620057211763289210f, -0.784556597155575240f, 0.619906763521964830f, + -0.784675477213174320f, + 0.619756292488440660f, -0.784794328420499230f, 0.619605798668249390f, + -0.784913150773180020f, + 0.619455282066924020f, -0.785031944266848080f, 0.619304742689998690f, + -0.785150708897135560f, + 0.619154180543008410f, -0.785269444659675850f, 0.619003595631488770f, + -0.785388151550103550f, + 0.618852987960976320f, -0.785506829564053930f, 0.618702357537008640f, + -0.785625478697163700f, + 0.618551704365123860f, -0.785744098945070360f, 0.618401028450860980f, + -0.785862690303412600f, + 0.618250329799760250f, -0.785981252767830150f, 0.618099608417362110f, + -0.786099786333963820f, + 0.617948864309208260f, -0.786218290997455550f, 0.617798097480841140f, + -0.786336766753948260f, + 0.617647307937803980f, -0.786455213599085770f, 0.617496495685640910f, + -0.786573631528513230f, + 0.617345660729896940f, -0.786692020537876680f, 0.617194803076117630f, + -0.786810380622823490f, + 0.617043922729849760f, -0.786928711779001700f, 0.616893019696640790f, + -0.787047014002060790f, + 0.616742093982038830f, -0.787165287287650890f, 0.616591145591593230f, + -0.787283531631423620f, + 0.616440174530853650f, -0.787401747029031320f, 0.616289180805370980f, + -0.787519933476127810f, + 0.616138164420696910f, -0.787638090968367450f, 0.615987125382383870f, + -0.787756219501405950f, + 0.615836063695985090f, -0.787874319070900110f, 0.615684979367054570f, + -0.787992389672507950f, + 0.615533872401147430f, -0.788110431301888070f, 0.615382742803819330f, + -0.788228443954700490f, + 0.615231590580626820f, -0.788346427626606230f, 0.615080415737127460f, + -0.788464382313267430f, + 0.614929218278879590f, -0.788582308010347120f, 0.614777998211442190f, + -0.788700204713509660f, + 0.614626755540375050f, -0.788818072418420170f, 0.614475490271239160f, + -0.788935911120745130f, + 0.614324202409595950f, -0.789053720816151880f, 0.614172891961007990f, + -0.789171501500308790f, + 0.614021558931038490f, -0.789289253168885650f, 0.613870203325251440f, + -0.789406975817552810f, + 0.613718825149211830f, -0.789524669441982190f, 0.613567424408485330f, + -0.789642334037846340f, + 0.613416001108638590f, -0.789759969600819070f, 0.613264555255239150f, + -0.789877576126575280f, + 0.613113086853854910f, -0.789995153610791090f, 0.612961595910055170f, + -0.790112702049143300f, + 0.612810082429409710f, -0.790230221437310030f, 0.612658546417489290f, + -0.790347711770970520f, + 0.612506987879865570f, -0.790465173045804880f, 0.612355406822110760f, + -0.790582605257494460f, + 0.612203803249798060f, -0.790700008401721610f, 0.612052177168501580f, + -0.790817382474169660f, + 0.611900528583796070f, -0.790934727470523290f, 0.611748857501257400f, + -0.791052043386467950f, + 0.611597163926462020f, -0.791169330217690090f, 0.611445447864987110f, + -0.791286587959877720f, + 0.611293709322411010f, -0.791403816608719500f, 0.611141948304312570f, + -0.791521016159905220f, + 0.610990164816271770f, -0.791638186609125770f, 0.610838358863869280f, + -0.791755327952073150f, + 0.610686530452686280f, -0.791872440184440470f, 0.610534679588305320f, + -0.791989523301921850f, + 0.610382806276309480f, -0.792106577300212390f, 0.610230910522282620f, + -0.792223602175008310f, + 0.610078992331809620f, -0.792340597922007060f, 0.609927051710476230f, + -0.792457564536906970f, + 0.609775088663868430f, -0.792574502015407580f, 0.609623103197573730f, + -0.792691410353209450f, + 0.609471095317180240f, -0.792808289546014120f, 0.609319065028276820f, + -0.792925139589524260f, + 0.609167012336453210f, -0.793041960479443640f, 0.609014937247299940f, + -0.793158752211477140f, + 0.608862839766408200f, -0.793275514781330630f, 0.608710719899370420f, + -0.793392248184711100f, + 0.608558577651779450f, -0.793508952417326660f, 0.608406413029229260f, + -0.793625627474886190f, + 0.608254226037314490f, -0.793742273353100100f, 0.608102016681630550f, + -0.793858890047679620f, + 0.607949784967773740f, -0.793975477554337170f, 0.607797530901341140f, + -0.794092035868785960f, + 0.607645254487930830f, -0.794208564986740640f, 0.607492955733141660f, + -0.794325064903916520f, + 0.607340634642572930f, -0.794441535616030590f, 0.607188291221825160f, + -0.794557977118800270f, + 0.607035925476499760f, -0.794674389407944550f, 0.606883537412198580f, + -0.794790772479183170f, + 0.606731127034524480f, -0.794907126328237010f, 0.606578694349081400f, + -0.795023450950828050f, + 0.606426239361473550f, -0.795139746342679590f, 0.606273762077306430f, + -0.795256012499515500f, + 0.606121262502186230f, -0.795372249417061190f, 0.605968740641719790f, + -0.795488457091042990f, + 0.605816196501515080f, -0.795604635517188070f, 0.605663630087180490f, + -0.795720784691225090f, + 0.605511041404325550f, -0.795836904608883460f, 0.605358430458560530f, + -0.795952995265893910f, + 0.605205797255496500f, -0.796069056657987990f, 0.605053141800745430f, + -0.796185088780898440f, + 0.604900464099919930f, -0.796301091630359110f, 0.604747764158633410f, + -0.796417065202104980f, + 0.604595041982500360f, -0.796533009491872000f, 0.604442297577135970f, + -0.796648924495397150f, + 0.604289530948156070f, -0.796764810208418720f, 0.604136742101177630f, + -0.796880666626675780f, + 0.603983931041818020f, -0.796996493745908750f, 0.603831097775695880f, + -0.797112291561858920f, + 0.603678242308430370f, -0.797228060070268700f, 0.603525364645641550f, + -0.797343799266881700f, + 0.603372464792950370f, -0.797459509147442460f, 0.603219542755978440f, + -0.797575189707696590f, + 0.603066598540348280f, -0.797690840943391040f, 0.602913632151683140f, + -0.797806462850273570f, + 0.602760643595607220f, -0.797922055424093000f, 0.602607632877745550f, + -0.798037618660599410f, + 0.602454600003723860f, -0.798153152555543750f, 0.602301544979168550f, + -0.798268657104678310f, + 0.602148467809707320f, -0.798384132303756380f, 0.601995368500968130f, + -0.798499578148532010f, + 0.601842247058580030f, -0.798614994634760820f, 0.601689103488173060f, + -0.798730381758199210f, + 0.601535937795377730f, -0.798845739514604580f, 0.601382749985825420f, + -0.798961067899735760f, + 0.601229540065148620f, -0.799076366909352350f, 0.601076308038980160f, + -0.799191636539215210f, + 0.600923053912954090f, -0.799306876785086160f, 0.600769777692705230f, + -0.799422087642728040f, + 0.600616479383868970f, -0.799537269107905010f, 0.600463158992081690f, + -0.799652421176382130f, + 0.600309816522980430f, -0.799767543843925680f, 0.600156451982203350f, + -0.799882637106302810f, + 0.600003065375389060f, -0.799997700959281910f, 0.599849656708177360f, + -0.800112735398632370f, + 0.599696225986208310f, -0.800227740420124790f, 0.599542773215123390f, + -0.800342716019530660f, + 0.599389298400564540f, -0.800457662192622710f, 0.599235801548174570f, + -0.800572578935174750f, + 0.599082282663597310f, -0.800687466242961500f, 0.598928741752476900f, + -0.800802324111759110f, + 0.598775178820458720f, -0.800917152537344300f, 0.598621593873188920f, + -0.801031951515495330f, + 0.598467986916314310f, -0.801146721041991250f, 0.598314357955482600f, + -0.801261461112612540f, + 0.598160706996342380f, -0.801376171723140130f, 0.598007034044542700f, + -0.801490852869356840f, + 0.597853339105733910f, -0.801605504547046040f, 0.597699622185566830f, + -0.801720126751992330f, + 0.597545883289693270f, -0.801834719479981310f, 0.597392122423765710f, + -0.801949282726799660f, + 0.597238339593437530f, -0.802063816488235440f, 0.597084534804362740f, + -0.802178320760077450f, + 0.596930708062196500f, -0.802292795538115720f, 0.596776859372594500f, + -0.802407240818141300f, + 0.596622988741213330f, -0.802521656595946320f, 0.596469096173710360f, + -0.802636042867324150f, + 0.596315181675743820f, -0.802750399628069160f, 0.596161245252972540f, + -0.802864726873976590f, + 0.596007286911056530f, -0.802979024600843140f, 0.595853306655656390f, + -0.803093292804466400f, + 0.595699304492433470f, -0.803207531480644830f, 0.595545280427049790f, + -0.803321740625178470f, + 0.595391234465168730f, -0.803435920233868120f, 0.595237166612453850f, + -0.803550070302515570f, + 0.595083076874569960f, -0.803664190826924090f, 0.594928965257182420f, + -0.803778281802897570f, + 0.594774831765957580f, -0.803892343226241260f, 0.594620676406562240f, + -0.804006375092761520f, + 0.594466499184664540f, -0.804120377398265700f, 0.594312300105932830f, + -0.804234350138562260f, + 0.594158079176036800f, -0.804348293309460780f, 0.594003836400646690f, + -0.804462206906771840f, + 0.593849571785433630f, -0.804576090926307000f, 0.593695285336069300f, + -0.804689945363879500f, + 0.593540977058226390f, -0.804803770215302810f, 0.593386646957578480f, + -0.804917565476392150f, + 0.593232295039799800f, -0.805031331142963660f, 0.593077921310565580f, + -0.805145067210834120f, + 0.592923525775551410f, -0.805258773675822210f, 0.592769108440434070f, + -0.805372450533747060f, + 0.592614669310891130f, -0.805486097780429120f, 0.592460208392600940f, + -0.805599715411689950f, + 0.592305725691242400f, -0.805713303423352120f, 0.592151221212495640f, + -0.805826861811239300f, + 0.591996694962040990f, -0.805940390571176280f, 0.591842146945560250f, + -0.806053889698988950f, + 0.591687577168735550f, -0.806167359190504310f, 0.591532985637249990f, + -0.806280799041550370f, + 0.591378372356787580f, -0.806394209247956240f, 0.591223737333032910f, + -0.806507589805552260f, + 0.591069080571671510f, -0.806620940710169650f, 0.590914402078389520f, + -0.806734261957640750f, + 0.590759701858874280f, -0.806847553543799220f, 0.590604979918813440f, + -0.806960815464479620f, + 0.590450236263895920f, -0.807074047715517610f, 0.590295470899810940f, + -0.807187250292749850f, + 0.590140683832248940f, -0.807300423192014450f, 0.589985875066900920f, + -0.807413566409150190f, + 0.589831044609458900f, -0.807526679939997160f, 0.589676192465615420f, + -0.807639763780396370f, + 0.589521318641063940f, -0.807752817926190360f, 0.589366423141498790f, + -0.807865842373222120f, + 0.589211505972615070f, -0.807978837117336310f, 0.589056567140108460f, + -0.808091802154378260f, + 0.588901606649675840f, -0.808204737480194720f, 0.588746624507014650f, + -0.808317643090633250f, + 0.588591620717822890f, -0.808430518981542720f, 0.588436595287799900f, + -0.808543365148773010f, + 0.588281548222645330f, -0.808656181588174980f, 0.588126479528059850f, + -0.808768968295600850f, + 0.587971389209745120f, -0.808881725266903610f, 0.587816277273403020f, + -0.808994452497937560f, + 0.587661143724736770f, -0.809107149984558130f, 0.587505988569450020f, + -0.809219817722621750f, + 0.587350811813247660f, -0.809332455707985840f, 0.587195613461834910f, + -0.809445063936509170f, + 0.587040393520918080f, -0.809557642404051260f, 0.586885151996203950f, + -0.809670191106473090f, + 0.586729888893400500f, -0.809782710039636420f, 0.586574604218216280f, + -0.809895199199404450f, + 0.586419297976360500f, -0.810007658581641140f, 0.586263970173543700f, + -0.810120088182211600f, + 0.586108620815476430f, -0.810232487996982330f, 0.585953249907870680f, + -0.810344858021820550f, + 0.585797857456438860f, -0.810457198252594770f, 0.585642443466894420f, + -0.810569508685174630f, + 0.585487007944951450f, -0.810681789315430670f, 0.585331550896324940f, + -0.810794040139234730f, + 0.585176072326730410f, -0.810906261152459670f, 0.585020572241884530f, + -0.811018452350979470f, + 0.584865050647504490f, -0.811130613730669190f, 0.584709507549308500f, + -0.811242745287404810f, + 0.584553942953015330f, -0.811354847017063730f, 0.584398356864344710f, + -0.811466918915524250f, + 0.584242749289016980f, -0.811578960978665890f, 0.584087120232753550f, + -0.811690973202369050f, + 0.583931469701276300f, -0.811802955582515360f, 0.583775797700308070f, + -0.811914908114987680f, + 0.583620104235572760f, -0.812026830795669730f, 0.583464389312794430f, + -0.812138723620446480f, + 0.583308652937698290f, -0.812250586585203880f, 0.583152895116010540f, + -0.812362419685829120f, + 0.582997115853457700f, -0.812474222918210480f, 0.582841315155767650f, + -0.812585996278237020f, + 0.582685493028668460f, -0.812697739761799490f, 0.582529649477889320f, + -0.812809453364789160f, + 0.582373784509160220f, -0.812921137083098770f, 0.582217898128211790f, + -0.813032790912621930f, + 0.582061990340775550f, -0.813144414849253590f, 0.581906061152583920f, + -0.813256008888889380f, + 0.581750110569369760f, -0.813367573027426570f, 0.581594138596866930f, + -0.813479107260763220f, + 0.581438145240810280f, -0.813590611584798510f, 0.581282130506935110f, + -0.813702085995432700f, + 0.581126094400977620f, -0.813813530488567190f, 0.580970036928674880f, + -0.813924945060104490f, + 0.580813958095764530f, -0.814036329705948300f, 0.580657857907985410f, + -0.814147684422003360f, + 0.580501736371076600f, -0.814259009204175270f, 0.580345593490778300f, + -0.814370304048371070f, + 0.580189429272831680f, -0.814481568950498610f, 0.580033243722978150f, + -0.814592803906467270f, + 0.579877036846960350f, -0.814704008912187080f, 0.579720808650521560f, + -0.814815183963569330f, + 0.579564559139405740f, -0.814926329056526620f, 0.579408288319357980f, + -0.815037444186972220f, + 0.579251996196123550f, -0.815148529350820830f, 0.579095682775449210f, + -0.815259584543988280f, + 0.578939348063081890f, -0.815370609762391290f, 0.578782992064769690f, + -0.815481605001947770f, + 0.578626614786261430f, -0.815592570258576680f, 0.578470216233306740f, + -0.815703505528198260f, + 0.578313796411655590f, -0.815814410806733780f, 0.578157355327059360f, + -0.815925286090105390f, + 0.578000892985269910f, -0.816036131374236700f, 0.577844409392039850f, + -0.816146946655052160f, + 0.577687904553122800f, -0.816257731928477390f, 0.577531378474272830f, + -0.816368487190439200f, + 0.577374831161244880f, -0.816479212436865390f, 0.577218262619794920f, + -0.816589907663684890f, + 0.577061672855679550f, -0.816700572866827850f, 0.576905061874655960f, + -0.816811208042225290f, + 0.576748429682482520f, -0.816921813185809480f, 0.576591776284917870f, + -0.817032388293513880f, + 0.576435101687721830f, -0.817142933361272970f, 0.576278405896654910f, + -0.817253448385022230f, + 0.576121688917478390f, -0.817363933360698460f, 0.575964950755954330f, + -0.817474388284239240f, + 0.575808191417845340f, -0.817584813151583710f, 0.575651410908915250f, + -0.817695207958671680f, + 0.575494609234928230f, -0.817805572701444270f, 0.575337786401649560f, + -0.817915907375843740f, + 0.575180942414845190f, -0.818026211977813440f, 0.575024077280281820f, + -0.818136486503297620f, + 0.574867191003726740f, -0.818246730948241960f, 0.574710283590948450f, + -0.818356945308593150f, + 0.574553355047715760f, -0.818467129580298660f, 0.574396405379798750f, + -0.818577283759307490f, + 0.574239434592967890f, -0.818687407841569570f, 0.574082442692994470f, + -0.818797501823036010f, + 0.573925429685650750f, -0.818907565699658950f, 0.573768395576709560f, + -0.819017599467391500f, + 0.573611340371944610f, -0.819127603122188240f, 0.573454264077130400f, + -0.819237576660004520f, + 0.573297166698042320f, -0.819347520076796900f, 0.573140048240456060f, + -0.819457433368523280f, + 0.572982908710148680f, -0.819567316531142230f, 0.572825748112897550f, + -0.819677169560613760f, + 0.572668566454481160f, -0.819786992452898990f, 0.572511363740678790f, + -0.819896785203959810f, + 0.572354139977270030f, -0.820006547809759680f, 0.572196895170035580f, + -0.820116280266262710f, + 0.572039629324757050f, -0.820225982569434690f, 0.571882342447216590f, + -0.820335654715241840f, + 0.571725034543197120f, -0.820445296699652050f, 0.571567705618482580f, + -0.820554908518633890f, + 0.571410355678857340f, -0.820664490168157460f, 0.571252984730106660f, + -0.820774041644193650f, + 0.571095592778016690f, -0.820883562942714580f, 0.570938179828374360f, + -0.820993054059693470f, + 0.570780745886967370f, -0.821102514991104650f, 0.570623290959583860f, + -0.821211945732923550f, + 0.570465815052012990f, -0.821321346281126740f, 0.570308318170045010f, + -0.821430716631691760f, + 0.570150800319470300f, -0.821540056780597610f, 0.569993261506080650f, + -0.821649366723823830f, + 0.569835701735668110f, -0.821758646457351640f, 0.569678121014025710f, + -0.821867895977163140f, + 0.569520519346947250f, -0.821977115279241550f, 0.569362896740227330f, + -0.822086304359571090f, + 0.569205253199661200f, -0.822195463214137170f, 0.569047588731045220f, + -0.822304591838926350f, + 0.568889903340175970f, -0.822413690229926390f, 0.568732197032851160f, + -0.822522758383125940f, + 0.568574469814869250f, -0.822631796294514990f, 0.568416721692029390f, + -0.822740803960084420f, + 0.568258952670131490f, -0.822849781375826320f, 0.568101162754976570f, + -0.822958728537734000f, + 0.567943351952365670f, -0.823067645441801670f, 0.567785520268101250f, + -0.823176532084024860f, + 0.567627667707986230f, -0.823285388460400110f, 0.567469794277824620f, + -0.823394214566925080f, + 0.567311899983420800f, -0.823503010399598390f, 0.567153984830580100f, + -0.823611775954420260f, + 0.566996048825108680f, -0.823720511227391320f, 0.566838091972813320f, + -0.823829216214513990f, + 0.566680114279501710f, -0.823937890911791370f, 0.566522115750982100f, + -0.824046535315227760f, + 0.566364096393063950f, -0.824155149420828570f, 0.566206056211556840f, + -0.824263733224600450f, + 0.566047995212271560f, -0.824372286722551250f, 0.565889913401019570f, + -0.824480809910689500f, + 0.565731810783613230f, -0.824589302785025290f, 0.565573687365865440f, + -0.824697765341569470f, + 0.565415543153589770f, -0.824806197576334330f, 0.565257378152600910f, + -0.824914599485333080f, + 0.565099192368714090f, -0.825022971064580220f, 0.564940985807745320f, + -0.825131312310090960f, + 0.564782758475511400f, -0.825239623217882130f, 0.564624510377830120f, + -0.825347903783971380f, + 0.564466241520519500f, -0.825456154004377440f, 0.564307951909398750f, + -0.825564373875120490f, + 0.564149641550287680f, -0.825672563392221390f, 0.563991310449007080f, + -0.825780722551702430f, + 0.563832958611378170f, -0.825888851349586780f, 0.563674586043223180f, + -0.825996949781898970f, + 0.563516192750364910f, -0.826105017844664610f, 0.563357778738627020f, + -0.826213055533910110f, + 0.563199344013834090f, -0.826321062845663420f, 0.563040888581811230f, + -0.826429039775953390f, + 0.562882412448384550f, -0.826536986320809960f, 0.562723915619380400f, + -0.826644902476264210f, + 0.562565398100626560f, -0.826752788238348520f, 0.562406859897951140f, + -0.826860643603096080f, + 0.562248301017183150f, -0.826968468566541490f, 0.562089721464152480f, + -0.827076263124720270f, + 0.561931121244689470f, -0.827184027273669020f, 0.561772500364625450f, + -0.827291761009425810f, + 0.561613858829792420f, -0.827399464328029350f, 0.561455196646023280f, + -0.827507137225519830f, + 0.561296513819151470f, -0.827614779697938400f, 0.561137810355011530f, + -0.827722391741327220f, + 0.560979086259438260f, -0.827829973351729810f, 0.560820341538267540f, + -0.827937524525190870f, + 0.560661576197336030f, -0.828045045257755800f, 0.560502790242481060f, + -0.828152535545471410f, + 0.560343983679540860f, -0.828259995384385550f, 0.560185156514354080f, + -0.828367424770547480f, + 0.560026308752760380f, -0.828474823700007130f, 0.559867440400600320f, + -0.828582192168815790f, + 0.559708551463714790f, -0.828689530173025710f, 0.559549641947945870f, + -0.828796837708690610f, + 0.559390711859136140f, -0.828904114771864870f, 0.559231761203129010f, + -0.829011361358604430f, + 0.559072789985768480f, -0.829118577464965980f, 0.558913798212899770f, + -0.829225763087007570f, + 0.558754785890368310f, -0.829332918220788250f, 0.558595753024020760f, + -0.829440042862368170f, + 0.558436699619704100f, -0.829547137007808800f, 0.558277625683266330f, + -0.829654200653172640f, + 0.558118531220556100f, -0.829761233794523050f, 0.557959416237422960f, + -0.829868236427924840f, + 0.557800280739717100f, -0.829975208549443840f, 0.557641124733289420f, + -0.830082150155146970f, + 0.557481948223991660f, -0.830189061241102370f, 0.557322751217676160f, + -0.830295941803379070f, + 0.557163533720196340f, -0.830402791838047550f, 0.557004295737406060f, + -0.830509611341179070f, + 0.556845037275160100f, -0.830616400308846200f, 0.556685758339313890f, + -0.830723158737122880f, + 0.556526458935723720f, -0.830829886622083570f, 0.556367139070246490f, + -0.830936583959804410f, + 0.556207798748739930f, -0.831043250746362320f, 0.556048437977062720f, + -0.831149886977835430f, + 0.555889056761073920f, -0.831256492650303210f, 0.555729655106633520f, + -0.831363067759845920f, + 0.555570233019602290f, -0.831469612302545240f, 0.555410790505841740f, + -0.831576126274483630f, + 0.555251327571214090f, -0.831682609671745120f, 0.555091844221582420f, + -0.831789062490414400f, + 0.554932340462810370f, -0.831895484726577590f, 0.554772816300762580f, + -0.832001876376321840f, + 0.554613271741304040f, -0.832108237435735480f, 0.554453706790301040f, + -0.832214567900907980f, + 0.554294121453620110f, -0.832320867767929680f, 0.554134515737128910f, + -0.832427137032892280f, + 0.553974889646695610f, -0.832533375691888680f, 0.553815243188189090f, + -0.832639583741012770f, + 0.553655576367479310f, -0.832745761176359460f, 0.553495889190436570f, + -0.832851907994024980f, + 0.553336181662932410f, -0.832958024190106670f, 0.553176453790838460f, + -0.833064109760702890f, + 0.553016705580027580f, -0.833170164701913190f, 0.552856937036373290f, + -0.833276189009838240f, + 0.552697148165749770f, -0.833382182680579730f, 0.552537338974032120f, + -0.833488145710240770f, + 0.552377509467096070f, -0.833594078094925140f, 0.552217659650817930f, + -0.833699979830738290f, + 0.552057789531074980f, -0.833805850913786340f, 0.551897899113745320f, + -0.833911691340176730f, + 0.551737988404707450f, -0.834017501106018130f, 0.551578057409841000f, + -0.834123280207419990f, + 0.551418106135026060f, -0.834229028640493420f, 0.551258134586143700f, + -0.834334746401350080f, + 0.551098142769075430f, -0.834440433486103190f, 0.550938130689703880f, + -0.834546089890866760f, + 0.550778098353912230f, -0.834651715611756330f, 0.550618045767584330f, + -0.834757310644888230f, + 0.550457972936604810f, -0.834862874986380010f, 0.550297879866859190f, + -0.834968408632350450f, + 0.550137766564233630f, -0.835073911578919300f, 0.549977633034615000f, + -0.835179383822207580f, + 0.549817479283891020f, -0.835284825358337370f, 0.549657305317949980f, + -0.835390236183431780f, + 0.549497111142680960f, -0.835495616293615350f, 0.549336896763974010f, + -0.835600965685013410f, + 0.549176662187719770f, -0.835706284353752600f, 0.549016407419809390f, + -0.835811572295960590f, + 0.548856132466135290f, -0.835916829507766360f, 0.548695837332590090f, + -0.836022055985299880f, + 0.548535522025067390f, -0.836127251724692160f, 0.548375186549461600f, + -0.836232416722075600f, + 0.548214830911667780f, -0.836337550973583530f, 0.548054455117581880f, + -0.836442654475350380f, + 0.547894059173100190f, -0.836547727223511890f, 0.547733643084120200f, + -0.836652769214204950f, + 0.547573206856539870f, -0.836757780443567190f, 0.547412750496257930f, + -0.836862760907737810f, + 0.547252274009174090f, -0.836967710602857020f, 0.547091777401188530f, + -0.837072629525066000f, + 0.546931260678202190f, -0.837177517670507190f, 0.546770723846116800f, + -0.837282375035324320f, + 0.546610166910834860f, -0.837387201615661940f, 0.546449589878259760f, + -0.837491997407665890f, + 0.546288992754295210f, -0.837596762407483040f, 0.546128375544846060f, + -0.837701496611261700f, + 0.545967738255817680f, -0.837806200015150940f, 0.545807080893116140f, + -0.837910872615301060f, + 0.545646403462648590f, -0.838015514407863700f, 0.545485705970322530f, + -0.838120125388991500f, + 0.545324988422046460f, -0.838224705554837970f, 0.545164250823729320f, + -0.838329254901558300f, + 0.545003493181281160f, -0.838433773425308340f, 0.544842715500612470f, + -0.838538261122245170f, + 0.544681917787634530f, -0.838642717988527300f, 0.544521100048259710f, + -0.838747144020313920f, + 0.544360262288400400f, -0.838851539213765760f, 0.544199404513970420f, + -0.838955903565044350f, + 0.544038526730883930f, -0.839060237070312630f, 0.543877628945055980f, + -0.839164539725734570f, + 0.543716711162402390f, -0.839268811527475230f, 0.543555773388839650f, + -0.839373052471700690f, + 0.543394815630284800f, -0.839477262554578550f, 0.543233837892656000f, + -0.839581441772277120f, + 0.543072840181871850f, -0.839685590120966110f, 0.542911822503851730f, + -0.839789707596816260f, + 0.542750784864516000f, -0.839893794195999410f, 0.542589727269785270f, + -0.839997849914688730f, + 0.542428649725581360f, -0.840101874749058400f, 0.542267552237826520f, + -0.840205868695283580f, + 0.542106434812444030f, -0.840309831749540770f, 0.541945297455357470f, + -0.840413763908007480f, + 0.541784140172491660f, -0.840517665166862440f, 0.541622962969771640f, + -0.840621535522285690f, + 0.541461765853123560f, -0.840725374970458070f, 0.541300548828474120f, + -0.840829183507561640f, + 0.541139311901750910f, -0.840932961129779670f, 0.540978055078882190f, + -0.841036707833296650f, + 0.540816778365796670f, -0.841140423614298080f, 0.540655481768424260f, + -0.841244108468970580f, + 0.540494165292695230f, -0.841347762393501950f, 0.540332828944540820f, + -0.841451385384081260f, + 0.540171472729892970f, -0.841554977436898330f, 0.540010096654684020f, + -0.841658538548144760f, + 0.539848700724847700f, -0.841762068714012490f, 0.539687284946317570f, + -0.841865567930695340f, + 0.539525849325029010f, -0.841969036194387680f, 0.539364393866917150f, + -0.842072473501285450f, + 0.539202918577918240f, -0.842175879847585570f, 0.539041423463969550f, + -0.842279255229485880f, + 0.538879908531008420f, -0.842382599643185960f, 0.538718373784973670f, + -0.842485913084885630f, + 0.538556819231804210f, -0.842589195550786600f, 0.538395244877439950f, + -0.842692447037091560f, + 0.538233650727821700f, -0.842795667540004120f, 0.538072036788890600f, + -0.842898857055729310f, + 0.537910403066588990f, -0.843002015580472830f, 0.537748749566859470f, + -0.843105143110442050f, + 0.537587076295645510f, -0.843208239641845440f, 0.537425383258891660f, + -0.843311305170892030f, + 0.537263670462542530f, -0.843414339693792760f, 0.537101937912544240f, + -0.843517343206759080f, + 0.536940185614843020f, -0.843620315706004040f, 0.536778413575385920f, + -0.843723257187741550f, + 0.536616621800121150f, -0.843826167648186740f, 0.536454810294997090f, + -0.843929047083555870f, + 0.536292979065963180f, -0.844031895490066410f, 0.536131128118969350f, + -0.844134712863936930f, + 0.535969257459966710f, -0.844237499201387020f, 0.535807367094906620f, + -0.844340254498637590f, + 0.535645457029741090f, -0.844442978751910660f, 0.535483527270423370f, + -0.844545671957429240f, + 0.535321577822907010f, -0.844648334111417820f, 0.535159608693146720f, + -0.844750965210101510f, + 0.534997619887097260f, -0.844853565249707010f, 0.534835611410714670f, + -0.844956134226462100f, + 0.534673583269955510f, -0.845058672136595470f, 0.534511535470777010f, + -0.845161178976337140f, + 0.534349468019137520f, -0.845263654741918220f, 0.534187380920995600f, + -0.845366099429570970f, + 0.534025274182310380f, -0.845468513035528830f, 0.533863147809042650f, + -0.845570895556026270f, + 0.533701001807152960f, -0.845673246987299070f, 0.533538836182603120f, + -0.845775567325583900f, + 0.533376650941355560f, -0.845877856567118890f, 0.533214446089372960f, + -0.845980114708143270f, + 0.533052221632619670f, -0.846082341744896940f, 0.532889977577059690f, + -0.846184537673621670f, + 0.532727713928658810f, -0.846286702490559710f, 0.532565430693382580f, + -0.846388836191954930f, + 0.532403127877198010f, -0.846490938774052020f, 0.532240805486072330f, + -0.846593010233097190f, + 0.532078463525973540f, -0.846695050565337450f, 0.531916102002870760f, + -0.846797059767020910f, + 0.531753720922733320f, -0.846899037834397350f, 0.531591320291531780f, + -0.847000984763716880f, + 0.531428900115236910f, -0.847102900551231500f, 0.531266460399820390f, + -0.847204785193193980f, + 0.531104001151255000f, -0.847306638685858320f, 0.530941522375513510f, + -0.847408461025479730f, + 0.530779024078570250f, -0.847510252208314330f, 0.530616506266399450f, + -0.847612012230619660f, + 0.530453968944976320f, -0.847713741088654270f, 0.530291412120277420f, + -0.847815438778677930f, + 0.530128835798278850f, -0.847917105296951410f, 0.529966239984958620f, + -0.848018740639736810f, + 0.529803624686294830f, -0.848120344803297120f, 0.529640989908265910f, + -0.848221917783896990f, + 0.529478335656852090f, -0.848323459577801530f, 0.529315661938033140f, + -0.848424970181277600f, + 0.529152968757790720f, -0.848526449590592650f, 0.528990256122106040f, + -0.848627897802015860f, + 0.528827524036961980f, -0.848729314811817010f, 0.528664772508341540f, + -0.848830700616267530f, + 0.528502001542228480f, -0.848932055211639610f, 0.528339211144607690f, + -0.849033378594206690f, + 0.528176401321464370f, -0.849134670760243630f, 0.528013572078784740f, + -0.849235931706025960f, + 0.527850723422555460f, -0.849337161427830670f, 0.527687855358763720f, + -0.849438359921935950f, + 0.527524967893398200f, -0.849539527184620890f, 0.527362061032447430f, + -0.849640663212165910f, + 0.527199134781901390f, -0.849741768000852440f, 0.527036189147750190f, + -0.849842841546963210f, + 0.526873224135984700f, -0.849943883846782210f, 0.526710239752597010f, + -0.850044894896594070f, + 0.526547236003579330f, -0.850145874692685210f, 0.526384212894925210f, + -0.850246823231342710f, + 0.526221170432628170f, -0.850347740508854980f, 0.526058108622682760f, + -0.850448626521511650f, + 0.525895027471084740f, -0.850549481265603370f, 0.525731926983829640f, + -0.850650304737422200f, + 0.525568807166914680f, -0.850751096933260790f, 0.525405668026336810f, + -0.850851857849413640f, + 0.525242509568094710f, -0.850952587482175730f, 0.525079331798186890f, + -0.851053285827843790f, + 0.524916134722612890f, -0.851153952882715340f, 0.524752918347373360f, + -0.851254588643089120f, + 0.524589682678468840f, -0.851355193105265200f, 0.524426427721901510f, + -0.851455766265544310f, + 0.524263153483673470f, -0.851556308120228870f, 0.524099859969787810f, + -0.851656818665622370f, + 0.523936547186248600f, -0.851757297898029120f, 0.523773215139060170f, + -0.851857745813754840f, + 0.523609863834228030f, -0.851958162409106380f, 0.523446493277757940f, + -0.852058547680391580f, + 0.523283103475656430f, -0.852158901623919830f, 0.523119694433931250f, + -0.852259224236001090f, + 0.522956266158590140f, -0.852359515512947090f, 0.522792818655642200f, + -0.852459775451070100f, + 0.522629351931096720f, -0.852560004046683970f, 0.522465865990963900f, + -0.852660201296103760f, + 0.522302360841254700f, -0.852760367195645300f, 0.522138836487980650f, + -0.852860501741625860f, + 0.521975292937154390f, -0.852960604930363630f, 0.521811730194788550f, + -0.853060676758178320f, + 0.521648148266897090f, -0.853160717221390420f, 0.521484547159494550f, + -0.853260726316321770f, + 0.521320926878595550f, -0.853360704039295430f, 0.521157287430216610f, + -0.853460650386635320f, + 0.520993628820373810f, -0.853560565354666840f, 0.520829951055084780f, + -0.853660448939716270f, + 0.520666254140367270f, -0.853760301138111300f, 0.520502538082239790f, + -0.853860121946180660f, + 0.520338802886721960f, -0.853959911360254060f, 0.520175048559833760f, + -0.854059669376662780f, + 0.520011275107596040f, -0.854159395991738730f, 0.519847482536030300f, + -0.854259091201815420f, + 0.519683670851158520f, -0.854358755003227440f, 0.519519840059003870f, + -0.854458387392310060f, + 0.519355990165589530f, -0.854557988365400530f, 0.519192121176940360f, + -0.854657557918836460f, + 0.519028233099080970f, -0.854757096048957110f, 0.518864325938037000f, + -0.854856602752102850f, + 0.518700399699835170f, -0.854956078024614820f, 0.518536454390502110f, + -0.855055521862835950f, + 0.518372490016066220f, -0.855154934263109620f, 0.518208506582555460f, + -0.855254315221781080f, + 0.518044504095999340f, -0.855353664735196030f, 0.517880482562427800f, + -0.855452982799701830f, + 0.517716441987871150f, -0.855552269411646970f, 0.517552382378360990f, + -0.855651524567380690f, + 0.517388303739929060f, -0.855750748263253920f, 0.517224206078608310f, + -0.855849940495618240f, + 0.517060089400432130f, -0.855949101260826790f, 0.516895953711434260f, + -0.856048230555233820f, + 0.516731799017649980f, -0.856147328375194470f, 0.516567625325114350f, + -0.856246394717065210f, + 0.516403432639863990f, -0.856345429577203610f, 0.516239220967935620f, + -0.856444432951968480f, + 0.516074990315366630f, -0.856543404837719960f, 0.515910740688195650f, + -0.856642345230818720f, + 0.515746472092461380f, -0.856741254127627470f, 0.515582184534203790f, + -0.856840131524509220f, + 0.515417878019463150f, -0.856938977417828650f, 0.515253552554280290f, + -0.857037791803951680f, + 0.515089208144697270f, -0.857136574679244870f, 0.514924844796756490f, + -0.857235326040076460f, + 0.514760462516501200f, -0.857334045882815590f, 0.514596061309975040f, + -0.857432734203832700f, + 0.514431641183222930f, -0.857531390999499040f, 0.514267202142289830f, + -0.857630016266187620f, + 0.514102744193221660f, -0.857728610000272120f, 0.513938267342065490f, + -0.857827172198127320f, + 0.513773771594868030f, -0.857925702856129790f, 0.513609256957677900f, + -0.858024201970656540f, + 0.513444723436543570f, -0.858122669538086020f, 0.513280171037514330f, + -0.858221105554798250f, + 0.513115599766640560f, -0.858319510017173440f, 0.512951009629972860f, + -0.858417882921594040f, + 0.512786400633563070f, -0.858516224264442740f, 0.512621772783463100f, + -0.858614534042104080f, + 0.512457126085725800f, -0.858712812250963520f, 0.512292460546404980f, + -0.858811058887407500f, + 0.512127776171554690f, -0.858909273947823900f, 0.511963072967230200f, + -0.859007457428601410f, + 0.511798350939487000f, -0.859105609326130340f, 0.511633610094381350f, + -0.859203729636801920f, + 0.511468850437970520f, -0.859301818357008360f, 0.511304071976311890f, + -0.859399875483143450f, + 0.511139274715464390f, -0.859497901011601620f, 0.510974458661486720f, + -0.859595894938779080f, + 0.510809623820439040f, -0.859693857261072610f, 0.510644770198381730f, + -0.859791787974880540f, + 0.510479897801375700f, -0.859889687076602290f, 0.510315006635483350f, + -0.859987554562638200f, + 0.510150096706766700f, -0.860085390429390140f, 0.509985168021289570f, + -0.860183194673260880f, + 0.509820220585115560f, -0.860280967290654510f, 0.509655254404309250f, + -0.860378708277976130f, + 0.509490269484936360f, -0.860476417631632070f, 0.509325265833062480f, + -0.860574095348029980f, + 0.509160243454754750f, -0.860671741423578380f, 0.508995202356080310f, + -0.860769355854687060f, + 0.508830142543106990f, -0.860866938637767310f, 0.508665064021904260f, + -0.860964489769230900f, + 0.508499966798540810f, -0.861062009245491480f, 0.508334850879087470f, + -0.861159497062963350f, + 0.508169716269614710f, -0.861256953218062060f, 0.508004562976194010f, + -0.861354377707204800f, + 0.507839391004897940f, -0.861451770526809210f, 0.507674200361798890f, + -0.861549131673294720f, + 0.507508991052970870f, -0.861646461143081300f, 0.507343763084487920f, + -0.861743758932590700f, + 0.507178516462425290f, -0.861841025038245330f, 0.507013251192858340f, + -0.861938259456469180f, + 0.506847967281863320f, -0.862035462183687210f, 0.506682664735517600f, + -0.862132633216325380f, + 0.506517343559898530f, -0.862229772550811240f, 0.506352003761084800f, + -0.862326880183573060f, + 0.506186645345155450f, -0.862423956111040500f, 0.506021268318189830f, + -0.862521000329644520f, + 0.505855872686268860f, -0.862618012835816740f, 0.505690458455473340f, + -0.862714993625990690f, + 0.505525025631885510f, -0.862811942696600330f, 0.505359574221587390f, + -0.862908860044081290f, + 0.505194104230662240f, -0.863005745664870210f, 0.505028615665194300f, + -0.863102599555404800f, + 0.504863108531267480f, -0.863199421712124160f, 0.504697582834967680f, + -0.863296212131468230f, + 0.504532038582380380f, -0.863392970809878310f, 0.504366475779592150f, + -0.863489697743797140f, + 0.504200894432690560f, -0.863586392929667990f, 0.504035294547763080f, + -0.863683056363935940f, + 0.503869676130898950f, -0.863779688043046610f, 0.503704039188186960f, + -0.863876287963447510f, + 0.503538383725717580f, -0.863972856121586700f, 0.503372709749581150f, + -0.864069392513913680f, + 0.503207017265869030f, -0.864165897136879300f, 0.503041306280673450f, + -0.864262369986934950f, + 0.502875576800086880f, -0.864358811060534030f, 0.502709828830203100f, + -0.864455220354130250f, + 0.502544062377115800f, -0.864551597864179230f, 0.502378277446919870f, + -0.864647943587137480f, + 0.502212474045710900f, -0.864744257519462380f, 0.502046652179584660f, + -0.864840539657612980f, + 0.501880811854638400f, -0.864936789998049020f, 0.501714953076969230f, + -0.865033008537231750f, + 0.501549075852675390f, -0.865129195271623690f, 0.501383180187855880f, + -0.865225350197688090f, + 0.501217266088609950f, -0.865321473311889800f, 0.501051333561038040f, + -0.865417564610694410f, + 0.500885382611240940f, -0.865513624090568980f, 0.500719413245319880f, + -0.865609651747981880f, + 0.500553425469377640f, -0.865705647579402270f, 0.500387419289516580f, + -0.865801611581300760f, + 0.500221394711840680f, -0.865897543750148820f, 0.500055351742453860f, + -0.865993444082419520f, + 0.499889290387461380f, -0.866089312574586770f, 0.499723210652968710f, + -0.866185149223125730f, + 0.499557112545081890f, -0.866280954024512990f, 0.499390996069908220f, + -0.866376726975225830f, + 0.499224861233555030f, -0.866472468071743050f, 0.499058708042130930f, + -0.866568177310544360f, + 0.498892536501744750f, -0.866663854688111020f, 0.498726346618505960f, + -0.866759500200925290f, + 0.498560138398525200f, -0.866855113845470320f, 0.498393911847913150f, + -0.866950695618231020f, + 0.498227666972781870f, -0.867046245515692650f, 0.498061403779243520f, + -0.867141763534342360f, + 0.497895122273410930f, -0.867237249670668400f, 0.497728822461398100f, + -0.867332703921159690f, + 0.497562504349319090f, -0.867428126282306920f, 0.497396167943289340f, + -0.867523516750601460f, + 0.497229813249424340f, -0.867618875322536230f, 0.497063440273840310f, + -0.867714201994605140f, + 0.496897049022654640f, -0.867809496763303210f, 0.496730639501984710f, + -0.867904759625126920f, + 0.496564211717949340f, -0.867999990576573400f, 0.496397765676667160f, + -0.868095189614141670f, + 0.496231301384258310f, -0.868190356734331310f, 0.496064818846843060f, + -0.868285491933643240f, + 0.495898318070542240f, -0.868380595208579800f, 0.495731799061478020f, + -0.868475666555644120f, + 0.495565261825772490f, -0.868570705971340900f, 0.495398706369549080f, + -0.868665713452175580f, + 0.495232132698931350f, -0.868760688994655190f, 0.495065540820043610f, + -0.868855632595287750f, + 0.494898930739011310f, -0.868950544250582380f, 0.494732302461959820f, + -0.869045423957049530f, + 0.494565655995016010f, -0.869140271711200560f, 0.494398991344306760f, + -0.869235087509548250f, + 0.494232308515959730f, -0.869329871348606730f, 0.494065607516103730f, + -0.869424623224890780f, + 0.493898888350867430f, -0.869519343134916970f, 0.493732151026381070f, + -0.869614031075202300f, + 0.493565395548774880f, -0.869708687042265560f, 0.493398621924179830f, + -0.869803311032626650f, + 0.493231830158728070f, -0.869897903042806340f, 0.493065020258551650f, + -0.869992463069326870f, + 0.492898192229784090f, -0.870086991108711350f, 0.492731346078558840f, + -0.870181487157484560f, + 0.492564481811010650f, -0.870275951212171830f, 0.492397599433274550f, + -0.870370383269300160f, + 0.492230698951486080f, -0.870464783325397670f, 0.492063780371782060f, + -0.870559151376993250f, + 0.491896843700299240f, -0.870653487420617540f, 0.491729888943175820f, + -0.870747791452801790f, + 0.491562916106550060f, -0.870842063470078860f, 0.491395925196560830f, + -0.870936303468982760f, + 0.491228916219348330f, -0.871030511446048260f, 0.491061889181052590f, + -0.871124687397811900f, + 0.490894844087815140f, -0.871218831320810900f, 0.490727780945777570f, + -0.871312943211583920f, + 0.490560699761082080f, -0.871407023066670950f, 0.490393600539872130f, + -0.871501070882612530f, + 0.490226483288291100f, -0.871595086655951090f, 0.490059348012483910f, + -0.871689070383229740f, + 0.489892194718595300f, -0.871783022060993010f, 0.489725023412770970f, + -0.871876941685786890f, + 0.489557834101157550f, -0.871970829254157700f, 0.489390626789901920f, + -0.872064684762653970f, + 0.489223401485152030f, -0.872158508207824480f, 0.489056158193055980f, + -0.872252299586219860f, + 0.488888896919763230f, -0.872346058894391540f, 0.488721617671423250f, + -0.872439786128892280f, + 0.488554320454186230f, -0.872533481286276060f, 0.488387005274203590f, + -0.872627144363097960f, + 0.488219672137626740f, -0.872720775355914300f, 0.488052321050608310f, + -0.872814374261282390f, + 0.487884952019301210f, -0.872907941075760970f, 0.487717565049858860f, + -0.873001475795909920f, + 0.487550160148436050f, -0.873094978418290090f, 0.487382737321187310f, + -0.873188448939463790f, + 0.487215296574268820f, -0.873281887355994210f, 0.487047837913836550f, + -0.873375293664446000f, + 0.486880361346047400f, -0.873468667861384880f, 0.486712866877059340f, + -0.873562009943377740f, + 0.486545354513030270f, -0.873655319906992630f, 0.486377824260119500f, + -0.873748597748798870f, + 0.486210276124486530f, -0.873841843465366750f, 0.486042710112291390f, + -0.873935057053268130f, + 0.485875126229695420f, -0.874028238509075630f, 0.485707524482859750f, + -0.874121387829363330f, + 0.485539904877947020f, -0.874214505010706300f, 0.485372267421119770f, + -0.874307590049680950f, + 0.485204612118541880f, -0.874400642942864790f, 0.485036938976377450f, + -0.874493663686836450f, + 0.484869248000791120f, -0.874586652278176110f, 0.484701539197948730f, + -0.874679608713464510f, + 0.484533812574016120f, -0.874772532989284150f, 0.484366068135160480f, + -0.874865425102218210f, + 0.484198305887549140f, -0.874958285048851540f, 0.484030525837350010f, + -0.875051112825769970f, + 0.483862727990732320f, -0.875143908429560250f, 0.483694912353865080f, + -0.875236671856810870f, + 0.483527078932918740f, -0.875329403104110780f, 0.483359227734063980f, + -0.875422102168050830f, + 0.483191358763471910f, -0.875514769045222740f, 0.483023472027315050f, + -0.875607403732219240f, + 0.482855567531765670f, -0.875700006225634600f, 0.482687645282997510f, + -0.875792576522063880f, + 0.482519705287184520f, -0.875885114618103700f, 0.482351747550501030f, + -0.875977620510351660f, + 0.482183772079122830f, -0.876070094195406600f, 0.482015778879225530f, + -0.876162535669868460f, + 0.481847767956986080f, -0.876254944930338400f, 0.481679739318581490f, + -0.876347321973419020f, + 0.481511692970189920f, -0.876439666795713610f, 0.481343628917989870f, + -0.876531979393827100f, + 0.481175547168160360f, -0.876624259764365310f, 0.481007447726881640f, + -0.876716507903935400f, + 0.480839330600333900f, -0.876808723809145760f, 0.480671195794698690f, + -0.876900907476605650f, + 0.480503043316157670f, -0.876993058902925780f, 0.480334873170893070f, + -0.877085178084718310f, + 0.480166685365088440f, -0.877177265018595940f, 0.479998479904927220f, + -0.877269319701173170f, + 0.479830256796594250f, -0.877361342129065140f, 0.479662016046274340f, + -0.877453332298888560f, + 0.479493757660153060f, -0.877545290207261240f, 0.479325481644417130f, + -0.877637215850802120f, + 0.479157188005253310f, -0.877729109226131570f, 0.478988876748849550f, + -0.877820970329870500f, + 0.478820547881394050f, -0.877912799158641730f, 0.478652201409075550f, + -0.878004595709069080f, + 0.478483837338084080f, -0.878096359977777130f, 0.478315455674609480f, + -0.878188091961392250f, + 0.478147056424843120f, -0.878279791656541460f, 0.477978639594976110f, + -0.878371459059853590f, + 0.477810205191201040f, -0.878463094167957870f, 0.477641753219710590f, + -0.878554696977485340f, + 0.477473283686698060f, -0.878646267485068130f, 0.477304796598358010f, + -0.878737805687339280f, + 0.477136291960884750f, -0.878829311580933360f, 0.476967769780474230f, + -0.878920785162485840f, + 0.476799230063322250f, -0.879012226428633410f, 0.476630672815625380f, + -0.879103635376014330f, + 0.476462098043581310f, -0.879195012001267370f, 0.476293505753387750f, + -0.879286356301033250f, + 0.476124895951243630f, -0.879377668271953180f, 0.475956268643348220f, + -0.879468947910670100f, + 0.475787623835901120f, -0.879560195213827890f, 0.475618961535103410f, + -0.879651410178071470f, + 0.475450281747155870f, -0.879742592800047410f, 0.475281584478260800f, + -0.879833743076402940f, + 0.475112869734620470f, -0.879924861003786860f, 0.474944137522437860f, + -0.880015946578848960f, + 0.474775387847917230f, -0.880106999798240360f, 0.474606620717262560f, + -0.880198020658613190f, + 0.474437836136679340f, -0.880289009156620890f, 0.474269034112372920f, + -0.880379965288918260f, + 0.474100214650550020f, -0.880470889052160750f, 0.473931377757417560f, + -0.880561780443005590f, + 0.473762523439182850f, -0.880652639458111010f, 0.473593651702054640f, + -0.880743466094136230f, + 0.473424762552241530f, -0.880834260347742040f, 0.473255855995953380f, + -0.880925022215589880f, + 0.473086932039400220f, -0.881015751694342760f, 0.472917990688792760f, + -0.881106448780665130f, + 0.472749031950342900f, -0.881197113471221980f, 0.472580055830262250f, + -0.881287745762680100f, + 0.472411062334764100f, -0.881378345651706810f, 0.472242051470061650f, + -0.881468913134971330f, + 0.472073023242368660f, -0.881559448209143780f, 0.471903977657900320f, + -0.881649950870895260f, + 0.471734914722871430f, -0.881740421116898320f, 0.471565834443498480f, + -0.881830858943826620f, + 0.471396736825997810f, -0.881921264348354940f, 0.471227621876586400f, + -0.882011637327159590f, + 0.471058489601482610f, -0.882101977876917580f, 0.470889340006904520f, + -0.882192285994307430f, + 0.470720173099071710f, -0.882282561676008600f, 0.470550988884203490f, + -0.882372804918702290f, + 0.470381787368520710f, -0.882463015719070040f, 0.470212568558244280f, + -0.882553194073795400f, + 0.470043332459595620f, -0.882643339979562790f, 0.469874079078797470f, + -0.882733453433057540f, + 0.469704808422072460f, -0.882823534430966730f, 0.469535520495644510f, + -0.882913582969978020f, + 0.469366215305737630f, -0.883003599046780720f, 0.469196892858576630f, + -0.883093582658065370f, + 0.469027553160387240f, -0.883183533800523280f, 0.468858196217395330f, + -0.883273452470847430f, + 0.468688822035827960f, -0.883363338665731580f, 0.468519430621912420f, + -0.883453192381870920f, + 0.468350021981876530f, -0.883543013615961880f, 0.468180596121949400f, + -0.883632802364701760f, + 0.468011153048359830f, -0.883722558624789660f, 0.467841692767338220f, + -0.883812282392925090f, + 0.467672215285114710f, -0.883901973665809470f, 0.467502720607920920f, + -0.883991632440144890f, + 0.467333208741988530f, -0.884081258712634990f, 0.467163679693549770f, + -0.884170852479984500f, + 0.466994133468838110f, -0.884260413738899080f, 0.466824570074086950f, + -0.884349942486086120f, + 0.466654989515530970f, -0.884439438718253700f, 0.466485391799405010f, + -0.884528902432111350f, + 0.466315776931944480f, -0.884618333624369920f, 0.466146144919386000f, + -0.884707732291740930f, + 0.465976495767966130f, -0.884797098430937790f, 0.465806829483922770f, + -0.884886432038674560f, + 0.465637146073493770f, -0.884975733111666660f, 0.465467445542917800f, + -0.885065001646630930f, + 0.465297727898434650f, -0.885154237640285110f, 0.465127993146283950f, + -0.885243441089348270f, + 0.464958241292706740f, -0.885332611990540590f, 0.464788472343944160f, + -0.885421750340583570f, + 0.464618686306237820f, -0.885510856136199950f, 0.464448883185830770f, + -0.885599929374113360f, + 0.464279062988965760f, -0.885688970051048960f, 0.464109225721887010f, + -0.885777978163732940f, + 0.463939371390838460f, -0.885866953708892790f, 0.463769500002065680f, + -0.885955896683257030f, + 0.463599611561814120f, -0.886044807083555490f, 0.463429706076329880f, + -0.886133684906519340f, + 0.463259783551860260f, -0.886222530148880640f, 0.463089843994652470f, + -0.886311342807372890f, + 0.462919887410955130f, -0.886400122878730490f, 0.462749913807016850f, + -0.886488870359689600f, + 0.462579923189086810f, -0.886577585246987040f, 0.462409915563415540f, + -0.886666267537360890f, + 0.462239890936253280f, -0.886754917227550950f, 0.462069849313851810f, + -0.886843534314297300f, + 0.461899790702462840f, -0.886932118794342080f, 0.461729715108338770f, + -0.887020670664428360f, + 0.461559622537733190f, -0.887109189921300060f, 0.461389512996899450f, + -0.887197676561702900f, + 0.461219386492092430f, -0.887286130582383150f, 0.461049243029567010f, + -0.887374551980088740f, + 0.460879082615578690f, -0.887462940751568840f, 0.460708905256384190f, + -0.887551296893573370f, + 0.460538710958240010f, -0.887639620402853930f, 0.460368499727404070f, + -0.887727911276163020f, + 0.460198271570134270f, -0.887816169510254550f, 0.460028026492689700f, + -0.887904395101883240f, + 0.459857764501329650f, -0.887992588047805560f, 0.459687485602313870f, + -0.888080748344778900f, + 0.459517189801903590f, -0.888168875989561620f, 0.459346877106359570f, + -0.888256970978913870f, + 0.459176547521944150f, -0.888345033309596240f, 0.459006201054919680f, + -0.888433062978371320f, + 0.458835837711549120f, -0.888521059982002260f, 0.458665457498096670f, + -0.888609024317253750f, + 0.458495060420826220f, -0.888696955980891710f, 0.458324646486003300f, + -0.888784854969682850f, + 0.458154215699893230f, -0.888872721280395520f, 0.457983768068762180f, + -0.888960554909799310f, + 0.457813303598877290f, -0.889048355854664570f, 0.457642822296505770f, + -0.889136124111763240f, + 0.457472324167916110f, -0.889223859677868210f, 0.457301809219376800f, + -0.889311562549753850f, + 0.457131277457156980f, -0.889399232724195520f, 0.456960728887527030f, + -0.889486870197969790f, + 0.456790163516757220f, -0.889574474967854580f, 0.456619581351118960f, + -0.889662047030628790f, + 0.456448982396883860f, -0.889749586383072890f, 0.456278366660324670f, + -0.889837093021967900f, + 0.456107734147714220f, -0.889924566944096720f, 0.455937084865326030f, + -0.890012008146243260f, + 0.455766418819434750f, -0.890099416625192210f, 0.455595736016314920f, + -0.890186792377730240f, + 0.455425036462242420f, -0.890274135400644480f, 0.455254320163493210f, + -0.890361445690723730f, + 0.455083587126343840f, -0.890448723244757880f, 0.454912837357072050f, + -0.890535968059537830f, + 0.454742070861955450f, -0.890623180131855930f, 0.454571287647273000f, + -0.890710359458505520f, + 0.454400487719303750f, -0.890797506036281490f, 0.454229671084327320f, + -0.890884619861979530f, + 0.454058837748624540f, -0.890971700932396750f, 0.453887987718476050f, + -0.891058749244331590f, + 0.453717121000163930f, -0.891145764794583180f, 0.453546237599970260f, + -0.891232747579952520f, + 0.453375337524177750f, -0.891319697597241390f, 0.453204420779070300f, + -0.891406614843252900f, + 0.453033487370931580f, -0.891493499314791380f, 0.452862537306046810f, + -0.891580351008662290f, + 0.452691570590700860f, -0.891667169921672390f, 0.452520587231180100f, + -0.891753956050629460f, + 0.452349587233771000f, -0.891840709392342720f, 0.452178570604760410f, + -0.891927429943622510f, + 0.452007537350436530f, -0.892014117701280360f, 0.451836487477087430f, + -0.892100772662129170f, + 0.451665420991002540f, -0.892187394822982480f, 0.451494337898471210f, + -0.892273984180655730f, + 0.451323238205783520f, -0.892360540731965360f, 0.451152121919230710f, + -0.892447064473728680f, + 0.450980989045103810f, -0.892533555402764690f, 0.450809839589695340f, + -0.892620013515893040f, + 0.450638673559297760f, -0.892706438809935280f, 0.450467490960204110f, + -0.892792831281713610f, + 0.450296291798708730f, -0.892879190928051680f, 0.450125076081105750f, + -0.892965517745774260f, + 0.449953843813690580f, -0.893051811731707450f, 0.449782595002758860f, + -0.893138072882678210f, + 0.449611329654606600f, -0.893224301195515320f, 0.449440047775531260f, + -0.893310496667048090f, + 0.449268749371829920f, -0.893396659294107610f, 0.449097434449801100f, + -0.893482789073525850f, + 0.448926103015743260f, -0.893568886002136020f, 0.448754755075956020f, + -0.893654950076772430f, + 0.448583390636739300f, -0.893740981294271040f, 0.448412009704393430f, + -0.893826979651468620f, + 0.448240612285220000f, -0.893912945145203250f, 0.448069198385520340f, + -0.893998877772314240f, + 0.447897768011597310f, -0.894084777529641990f, 0.447726321169753750f, + -0.894170644414028270f, + 0.447554857866293010f, -0.894256478422316040f, 0.447383378107519710f, + -0.894342279551349480f, + 0.447211881899738260f, -0.894428047797973800f, 0.447040369249254500f, + -0.894513783159035620f, + 0.446868840162374330f, -0.894599485631382580f, 0.446697294645404090f, + -0.894685155211863980f, + 0.446525732704651400f, -0.894770791897329550f, 0.446354154346423840f, + -0.894856395684630930f, + 0.446182559577030120f, -0.894941966570620750f, 0.446010948402779110f, + -0.895027504552152630f, + 0.445839320829980350f, -0.895113009626081760f, 0.445667676864944350f, + -0.895198481789264200f, + 0.445496016513981740f, -0.895283921038557580f, 0.445324339783404240f, + -0.895369327370820310f, + 0.445152646679523590f, -0.895454700782912450f, 0.444980937208652780f, + -0.895540041271694840f, + 0.444809211377105000f, -0.895625348834030000f, 0.444637469191193790f, + -0.895710623466781320f, + 0.444465710657234110f, -0.895795865166813420f, 0.444293935781540580f, + -0.895881073930992370f, + 0.444122144570429260f, -0.895966249756185110f, 0.443950337030216250f, + -0.896051392639260040f, + 0.443778513167218220f, -0.896136502577086770f, 0.443606672987753080f, + -0.896221579566535920f, + 0.443434816498138430f, -0.896306623604479660f, 0.443262943704693380f, + -0.896391634687790820f, + 0.443091054613736990f, -0.896476612813344010f, 0.442919149231588980f, + -0.896561557978014960f, + 0.442747227564570130f, -0.896646470178680150f, 0.442575289619001170f, + -0.896731349412217880f, + 0.442403335401204130f, -0.896816195675507190f, 0.442231364917501090f, + -0.896901008965428680f, + 0.442059378174214760f, -0.896985789278863970f, 0.441887375177668960f, + -0.897070536612695870f, + 0.441715355934187310f, -0.897155250963808550f, 0.441543320450094920f, + -0.897239932329087050f, + 0.441371268731716620f, -0.897324580705418320f, 0.441199200785378660f, + -0.897409196089689720f, + 0.441027116617407340f, -0.897493778478790190f, 0.440855016234129430f, + -0.897578327869610230f, + 0.440682899641873020f, -0.897662844259040750f, 0.440510766846965880f, + -0.897747327643974690f, + 0.440338617855737300f, -0.897831778021305650f, 0.440166452674516480f, + -0.897916195387928550f, + 0.439994271309633260f, -0.898000579740739880f, 0.439822073767418610f, + -0.898084931076636780f, + 0.439649860054203420f, -0.898169249392518080f, 0.439477630176319860f, + -0.898253534685283570f, + 0.439305384140100060f, -0.898337786951834190f, 0.439133121951876930f, + -0.898422006189072530f, + 0.438960843617984430f, -0.898506192393901840f, 0.438788549144756290f, + -0.898590345563227030f, + 0.438616238538527710f, -0.898674465693953820f, 0.438443911805633860f, + -0.898758552782989440f, + 0.438271568952410480f, -0.898842606827242260f, 0.438099209985194580f, + -0.898926627823621870f, + 0.437926834910322860f, -0.899010615769039070f, 0.437754443734133470f, + -0.899094570660405770f, + 0.437582036462964340f, -0.899178492494635330f, 0.437409613103154850f, + -0.899262381268642000f, + 0.437237173661044200f, -0.899346236979341460f, 0.437064718142972370f, + -0.899430059623650860f, + 0.436892246555280470f, -0.899513849198487870f, 0.436719758904309310f, + -0.899597605700772180f, + 0.436547255196401250f, -0.899681329127423930f, 0.436374735437898510f, + -0.899765019475365020f, + 0.436202199635143950f, -0.899848676741518580f, 0.436029647794481670f, + -0.899932300922808400f, + 0.435857079922255470f, -0.900015892016160280f, 0.435684496024810520f, + -0.900099450018500340f, + 0.435511896108492170f, -0.900182974926756700f, 0.435339280179646070f, + -0.900266466737858480f, + 0.435166648244619370f, -0.900349925448735600f, 0.434994000309758710f, + -0.900433351056319830f, + 0.434821336381412350f, -0.900516743557543520f, 0.434648656465928430f, + -0.900600102949340790f, + 0.434475960569655710f, -0.900683429228646860f, 0.434303248698944100f, + -0.900766722392397860f, + 0.434130520860143310f, -0.900849982437531450f, 0.433957777059604480f, + -0.900933209360986200f, + 0.433785017303678520f, -0.901016403159702330f, 0.433612241598717640f, + -0.901099563830620950f, + 0.433439449951074200f, -0.901182691370684410f, 0.433266642367100940f, + -0.901265785776836580f, + 0.433093818853152010f, -0.901348847046022030f, 0.432920979415581220f, + -0.901431875175186970f, + 0.432748124060743760f, -0.901514870161278630f, 0.432575252794994810f, + -0.901597832001245660f, + 0.432402365624690140f, -0.901680760692037730f, 0.432229462556186770f, + -0.901763656230605610f, + 0.432056543595841450f, -0.901846518613901860f, 0.431883608750012300f, + -0.901929347838879350f, + 0.431710658025057370f, -0.902012143902493070f, 0.431537691427335500f, + -0.902094906801698900f, + 0.431364708963206440f, -0.902177636533453510f, 0.431191710639030000f, + -0.902260333094715540f, + 0.431018696461167080f, -0.902342996482444200f, 0.430845666435978820f, + -0.902425626693600270f, + 0.430672620569826860f, -0.902508223725145830f, 0.430499558869073930f, + -0.902590787574043870f, + 0.430326481340082610f, -0.902673318237258830f, 0.430153387989216930f, + -0.902755815711756120f, + 0.429980278822840570f, -0.902838279994502830f, 0.429807153847318770f, + -0.902920711082466630f, + 0.429634013069016500f, -0.903003108972617040f, 0.429460856494299490f, + -0.903085473661924600f, + 0.429287684129534720f, -0.903167805147360610f, 0.429114495981088690f, + -0.903250103425898400f, + 0.428941292055329550f, -0.903332368494511820f, 0.428768072358625240f, + -0.903414600350176290f, + 0.428594836897344400f, -0.903496798989868450f, 0.428421585677856760f, + -0.903578964410565950f, + 0.428248318706531910f, -0.903661096609247980f, 0.428075035989740780f, + -0.903743195582894620f, + 0.427901737533854240f, -0.903825261328487390f, 0.427728423345243860f, + -0.903907293843009050f, + 0.427555093430282200f, -0.903989293123443340f, 0.427381747795341770f, + -0.904071259166775440f, + 0.427208386446796370f, -0.904153191969991670f, 0.427035009391019790f, + -0.904235091530079750f, + 0.426861616634386490f, -0.904316957844028320f, 0.426688208183271970f, + -0.904398790908827350f, + 0.426514784044051520f, -0.904480590721468250f, 0.426341344223101880f, + -0.904562357278943190f, + 0.426167888726799620f, -0.904644090578246240f, 0.425994417561522450f, + -0.904725790616371930f, + 0.425820930733648300f, -0.904807457390316540f, 0.425647428249555590f, + -0.904889090897077470f, + 0.425473910115623910f, -0.904970691133653250f, 0.425300376338232590f, + -0.905052258097043590f, + 0.425126826923762410f, -0.905133791784249580f, 0.424953261878594060f, + -0.905215292192273480f, + 0.424779681209108810f, -0.905296759318118820f, 0.424606084921689220f, + -0.905378193158789980f, + 0.424432473022717420f, -0.905459593711293250f, 0.424258845518577010f, + -0.905540960972635480f, + 0.424085202415651670f, -0.905622294939825160f, 0.423911543720325580f, + -0.905703595609872010f, + 0.423737869438983950f, -0.905784862979786440f, 0.423564179578011960f, + -0.905866097046580940f, + 0.423390474143796100f, -0.905947297807268460f, 0.423216753142722780f, + -0.906028465258863490f, + 0.423043016581179100f, -0.906109599398381980f, 0.422869264465553170f, + -0.906190700222840540f, + 0.422695496802232950f, -0.906271767729257660f, 0.422521713597607870f, + -0.906352801914652280f, + 0.422347914858067000f, -0.906433802776045460f, 0.422174100590000820f, + -0.906514770310458800f, + 0.422000270799799790f, -0.906595704514915330f, 0.421826425493854910f, + -0.906676605386439460f, + 0.421652564678558380f, -0.906757472922056550f, 0.421478688360302220f, + -0.906838307118793540f, + 0.421304796545479700f, -0.906919107973678030f, 0.421130889240484140f, + -0.906999875483739610f, + 0.420956966451709440f, -0.907080609646008450f, 0.420783028185550630f, + -0.907161310457516250f, + 0.420609074448402510f, -0.907241977915295930f, 0.420435105246661220f, + -0.907322612016381310f, + 0.420261120586723050f, -0.907403212757808000f, 0.420087120474984590f, + -0.907483780136612570f, + 0.419913104917843730f, -0.907564314149832520f, 0.419739073921698180f, + -0.907644814794507090f, + 0.419565027492946940f, -0.907725282067676330f, 0.419390965637989050f, + -0.907805715966381820f, + 0.419216888363223960f, -0.907886116487666150f, 0.419042795675052480f, + -0.907966483628573240f, + 0.418868687579875110f, -0.908046817386148340f, 0.418694564084093610f, + -0.908127117757437600f, + 0.418520425194109700f, -0.908207384739488700f, 0.418346270916326310f, + -0.908287618329350450f, + 0.418172101257146430f, -0.908367818524072780f, 0.417997916222973550f, + -0.908447985320707250f, + 0.417823715820212380f, -0.908528118716306120f, 0.417649500055267410f, + -0.908608218707923190f, + 0.417475268934544340f, -0.908688285292613360f, 0.417301022464449060f, + -0.908768318467432780f, + 0.417126760651387870f, -0.908848318229439120f, 0.416952483501768280f, + -0.908928284575690640f, + 0.416778191021997590f, -0.909008217503247450f, 0.416603883218484410f, + -0.909088117009170580f, + 0.416429560097637320f, -0.909167983090522270f, 0.416255221665865480f, + -0.909247815744366310f, + 0.416080867929579320f, -0.909327614967767260f, 0.415906498895188770f, + -0.909407380757791260f, + 0.415732114569105420f, -0.909487113111505430f, 0.415557714957740580f, + -0.909566812025978220f, + 0.415383300067506290f, -0.909646477498279540f, 0.415208869904815650f, + -0.909726109525480160f, + 0.415034424476081630f, -0.909805708104652220f, 0.414859963787718390f, + -0.909885273232869160f, + 0.414685487846140010f, -0.909964804907205660f, 0.414510996657761810f, + -0.910044303124737390f, + 0.414336490228999210f, -0.910123767882541570f, 0.414161968566268080f, + -0.910203199177696540f, + 0.413987431675985510f, -0.910282597007281760f, 0.413812879564568300f, + -0.910361961368377990f, + 0.413638312238434560f, -0.910441292258067140f, 0.413463729704002580f, + -0.910520589673432630f, + 0.413289131967690960f, -0.910599853611558930f, 0.413114519035919560f, + -0.910679084069531570f, + 0.412939890915108020f, -0.910758281044437570f, 0.412765247611677320f, + -0.910837444533365010f, + 0.412590589132048380f, -0.910916574533403240f, 0.412415915482642730f, + -0.910995671041643140f, + 0.412241226669883000f, -0.911074734055176250f, 0.412066522700191560f, + -0.911153763571095900f, + 0.411891803579992220f, -0.911232759586496190f, 0.411717069315708670f, + -0.911311722098472670f, + 0.411542319913765280f, -0.911390651104122320f, 0.411367555380587340f, + -0.911469546600543020f, + 0.411192775722600160f, -0.911548408584833990f, 0.411017980946230270f, + -0.911627237054095650f, + 0.410843171057903910f, -0.911706032005429880f, 0.410668346064048780f, + -0.911784793435939430f, + 0.410493505971092520f, -0.911863521342728520f, 0.410318650785463260f, + -0.911942215722902570f, + 0.410143780513590350f, -0.912020876573568230f, 0.409968895161902820f, + -0.912099503891833470f, + 0.409793994736831200f, -0.912178097674807060f, 0.409619079244805840f, + -0.912256657919599650f, + 0.409444148692257590f, -0.912335184623322750f, 0.409269203085618700f, + -0.912413677783089020f, + 0.409094242431320920f, -0.912492137396012650f, 0.408919266735797480f, + -0.912570563459208730f, + 0.408744276005481520f, -0.912648955969793900f, 0.408569270246806780f, + -0.912727314924885900f, + 0.408394249466208110f, -0.912805640321603500f, 0.408219213670120100f, + -0.912883932157067200f, + 0.408044162864978740f, -0.912962190428398100f, 0.407869097057219960f, + -0.913040415132719160f, + 0.407694016253280170f, -0.913118606267154130f, 0.407518920459597030f, + -0.913196763828828200f, + 0.407343809682607970f, -0.913274887814867760f, 0.407168683928751610f, + -0.913352978222400250f, + 0.406993543204466460f, -0.913431035048554720f, 0.406818387516192370f, + -0.913509058290461140f, + 0.406643216870369140f, -0.913587047945250810f, 0.406468031273437000f, + -0.913665004010056350f, + 0.406292830731837470f, -0.913742926482011390f, 0.406117615252011790f, + -0.913820815358251100f, + 0.405942384840402570f, -0.913898670635911680f, 0.405767139503452220f, + -0.913976492312130520f, + 0.405591879247603870f, -0.914054280384046460f, 0.405416604079301750f, + -0.914132034848799460f, + 0.405241314004989860f, -0.914209755703530690f, 0.405066009031113390f, + -0.914287442945382440f, + 0.404890689164117750f, -0.914365096571498450f, 0.404715354410448650f, + -0.914442716579023870f, + 0.404540004776553110f, -0.914520302965104450f, 0.404364640268877810f, + -0.914597855726887790f, + 0.404189260893870750f, -0.914675374861522390f, 0.404013866657980060f, + -0.914752860366158100f, + 0.403838457567654130f, -0.914830312237946090f, 0.403663033629342750f, + -0.914907730474038620f, + 0.403487594849495310f, -0.914985115071589310f, 0.403312141234562660f, + -0.915062466027752760f, + 0.403136672790995240f, -0.915139783339685260f, 0.402961189525244960f, + -0.915217067004543750f, + 0.402785691443763640f, -0.915294317019487050f, 0.402610178553003680f, + -0.915371533381674760f, + 0.402434650859418540f, -0.915448716088267830f, 0.402259108369461440f, + -0.915525865136428530f, + 0.402083551089587040f, -0.915602980523320230f, 0.401907979026249860f, + -0.915680062246107650f, + 0.401732392185905010f, -0.915757110301956720f, 0.401556790575008650f, + -0.915834124688034710f, + 0.401381174200016790f, -0.915911105401509880f, 0.401205543067386760f, + -0.915988052439551840f, + 0.401029897183575790f, -0.916064965799331610f, 0.400854236555041650f, + -0.916141845478021350f, + 0.400678561188243350f, -0.916218691472794110f, 0.400502871089639500f, + -0.916295503780824800f, + 0.400327166265690150f, -0.916372282399289140f, 0.400151446722855300f, + -0.916449027325364040f, + 0.399975712467595390f, -0.916525738556228100f, 0.399799963506372090f, + -0.916602416089060680f, + 0.399624199845646790f, -0.916679059921042700f, 0.399448421491882260f, + -0.916755670049355990f, + 0.399272628451540930f, -0.916832246471183890f, 0.399096820731086600f, + -0.916908789183710990f, + 0.398920998336983020f, -0.916985298184122890f, 0.398745161275694480f, + -0.917061773469606820f, + 0.398569309553686360f, -0.917138215037350710f, 0.398393443177423920f, + -0.917214622884544250f, + 0.398217562153373620f, -0.917290997008377910f, 0.398041666488001930f, + -0.917367337406043810f, + 0.397865756187775750f, -0.917443644074735220f, 0.397689831259163240f, + -0.917519917011646260f, + 0.397513891708632330f, -0.917596156213972950f, 0.397337937542652120f, + -0.917672361678911750f, + 0.397161968767691720f, -0.917748533403661250f, 0.396985985390220900f, + -0.917824671385420570f, + 0.396809987416710420f, -0.917900775621390390f, 0.396633974853630830f, + -0.917976846108772730f, + 0.396457947707453960f, -0.918052882844770380f, 0.396281905984651680f, + -0.918128885826587910f, + 0.396105849691696320f, -0.918204855051430900f, 0.395929778835061360f, + -0.918280790516506130f, + 0.395753693421220080f, -0.918356692219021720f, 0.395577593456646950f, + -0.918432560156186790f, + 0.395401478947816300f, -0.918508394325212250f, 0.395225349901203730f, + -0.918584194723309540f, + 0.395049206323284880f, -0.918659961347691900f, 0.394873048220535760f, + -0.918735694195573550f, + 0.394696875599433670f, -0.918811393264169940f, 0.394520688466455550f, + -0.918887058550697970f, + 0.394344486828079650f, -0.918962690052375630f, 0.394168270690784250f, + -0.919038287766421940f, + 0.393992040061048100f, -0.919113851690057770f, 0.393815794945351130f, + -0.919189381820504470f, + 0.393639535350172880f, -0.919264878154985250f, 0.393463261281994380f, + -0.919340340690724230f, + 0.393286972747296570f, -0.919415769424946960f, 0.393110669752560760f, + -0.919491164354880100f, + 0.392934352304269600f, -0.919566525477751530f, 0.392758020408905280f, + -0.919641852790790470f, + 0.392581674072951530f, -0.919717146291227360f, 0.392405313302891860f, + -0.919792405976293750f, + 0.392228938105210370f, -0.919867631843222950f, 0.392052548486392200f, + -0.919942823889248640f, + 0.391876144452922350f, -0.920017982111606570f, 0.391699726011287050f, + -0.920093106507533070f, + 0.391523293167972350f, -0.920168197074266450f, 0.391346845929465610f, + -0.920243253809045370f, + 0.391170384302253980f, -0.920318276709110480f, 0.390993908292825380f, + -0.920393265771703550f, + 0.390817417907668610f, -0.920468220994067110f, 0.390640913153272370f, + -0.920543142373445480f, + 0.390464394036126650f, -0.920618029907083860f, 0.390287860562721360f, + -0.920692883592229010f, + 0.390111312739546910f, -0.920767703426128790f, 0.389934750573094790f, + -0.920842489406032080f, + 0.389758174069856410f, -0.920917241529189520f, 0.389581583236324360f, + -0.920991959792852310f, + 0.389404978078991100f, -0.921066644194273530f, 0.389228358604349730f, + -0.921141294730707270f, + 0.389051724818894500f, -0.921215911399408730f, 0.388875076729119250f, + -0.921290494197634540f, + 0.388698414341519250f, -0.921365043122642340f, 0.388521737662589740f, + -0.921439558171691320f, + 0.388345046698826300f, -0.921514039342041900f, 0.388168341456725850f, + -0.921588486630955380f, + 0.387991621942784910f, -0.921662900035694730f, 0.387814888163501290f, + -0.921737279553523800f, + 0.387638140125372680f, -0.921811625181708120f, 0.387461377834897920f, + -0.921885936917513970f, + 0.387284601298575890f, -0.921960214758209110f, 0.387107810522905990f, + -0.922034458701062820f, + 0.386931005514388690f, -0.922108668743345070f, 0.386754186279524130f, + -0.922182844882327600f, + 0.386577352824813980f, -0.922256987115283030f, 0.386400505156759610f, + -0.922331095439485330f, + 0.386223643281862980f, -0.922405169852209880f, 0.386046767206627280f, + -0.922479210350733100f, + 0.385869876937555310f, -0.922553216932332830f, 0.385692972481151200f, + -0.922627189594287800f, + 0.385516053843919020f, -0.922701128333878520f, 0.385339121032363340f, + -0.922775033148386380f, + 0.385162174052989970f, -0.922848904035094120f, 0.384985212912304200f, + -0.922922740991285680f, + 0.384808237616812930f, -0.922996544014246250f, 0.384631248173022740f, + -0.923070313101262420f, + 0.384454244587440870f, -0.923144048249621820f, 0.384277226866575620f, + -0.923217749456613500f, + 0.384100195016935040f, -0.923291416719527640f, 0.383923149045028500f, + -0.923365050035655610f, + 0.383746088957365010f, -0.923438649402290370f, 0.383569014760454960f, + -0.923512214816725520f, + 0.383391926460808770f, -0.923585746276256560f, 0.383214824064937180f, + -0.923659243778179980f, + 0.383037707579352130f, -0.923732707319793180f, 0.382860577010565360f, + -0.923806136898395410f, + 0.382683432365089840f, -0.923879532511286740f, 0.382506273649438400f, + -0.923952894155768640f, + 0.382329100870124510f, -0.924026221829143850f, 0.382151914033662720f, + -0.924099515528716280f, + 0.381974713146567220f, -0.924172775251791200f, 0.381797498215353690f, + -0.924246000995674890f, + 0.381620269246537520f, -0.924319192757675160f, 0.381443026246634730f, + -0.924392350535101050f, + 0.381265769222162490f, -0.924465474325262600f, 0.381088498179637520f, + -0.924538564125471420f, + 0.380911213125578130f, -0.924611619933039970f, 0.380733914066502090f, + -0.924684641745282530f, + 0.380556601008928570f, -0.924757629559513910f, 0.380379273959376710f, + -0.924830583373050800f, + 0.380201932924366050f, -0.924903503183210910f, 0.380024577910417380f, + -0.924976388987313050f, + 0.379847208924051110f, -0.925049240782677580f, 0.379669825971789000f, + -0.925122058566625770f, + 0.379492429060152740f, -0.925194842336480420f, 0.379315018195664430f, + -0.925267592089565550f, + 0.379137593384847430f, -0.925340307823206200f, 0.378960154634224720f, + -0.925412989534729060f, + 0.378782701950320600f, -0.925485637221461490f, 0.378605235339659290f, + -0.925558250880732620f, + 0.378427754808765620f, -0.925630830509872720f, 0.378250260364165310f, + -0.925703376106213120f, + 0.378072752012383990f, -0.925775887667086740f, 0.377895229759948550f, + -0.925848365189827270f, + 0.377717693613385810f, -0.925920808671769960f, 0.377540143579222940f, + -0.925993218110251480f, + 0.377362579663988450f, -0.926065593502609310f, 0.377185001874210450f, + -0.926137934846182560f, + 0.377007410216418310f, -0.926210242138311270f, 0.376829804697141220f, + -0.926282515376337210f, + 0.376652185322909620f, -0.926354754557602860f, 0.376474552100253880f, + -0.926426959679452100f, + 0.376296905035704790f, -0.926499130739230510f, 0.376119244135794390f, + -0.926571267734284220f, + 0.375941569407054420f, -0.926643370661961230f, 0.375763880856017750f, + -0.926715439519610330f, + 0.375586178489217330f, -0.926787474304581750f, 0.375408462313186590f, + -0.926859475014227160f, + 0.375230732334460030f, -0.926931441645899130f, 0.375052988559571860f, + -0.927003374196951670f, + 0.374875230995057600f, -0.927075272664740100f, 0.374697459647452770f, + -0.927147137046620880f, + 0.374519674523293210f, -0.927218967339951790f, 0.374341875629116030f, + -0.927290763542091720f, + 0.374164062971457990f, -0.927362525650401110f, 0.373986236556857090f, + -0.927434253662241300f, + 0.373808396391851370f, -0.927505947574975180f, 0.373630542482979280f, + -0.927577607385966730f, + 0.373452674836780410f, -0.927649233092581180f, 0.373274793459794030f, + -0.927720824692185200f, + 0.373096898358560690f, -0.927792382182146320f, 0.372918989539620770f, + -0.927863905559833780f, + 0.372741067009515810f, -0.927935394822617890f, 0.372563130774787370f, + -0.928006849967869970f, + 0.372385180841977360f, -0.928078270992963140f, 0.372207217217628950f, + -0.928149657895271150f, + 0.372029239908284960f, -0.928221010672169440f, 0.371851248920489540f, + -0.928292329321034560f, + 0.371673244260786630f, -0.928363613839244370f, 0.371495225935720760f, + -0.928434864224177980f, + 0.371317193951837600f, -0.928506080473215480f, 0.371139148315682510f, + -0.928577262583738850f, + 0.370961089033802040f, -0.928648410553130520f, 0.370783016112742720f, + -0.928719524378774700f, + 0.370604929559051670f, -0.928790604058057020f, 0.370426829379276900f, + -0.928861649588363700f, + 0.370248715579966360f, -0.928932660967082820f, 0.370070588167669130f, + -0.929003638191603360f, + 0.369892447148934270f, -0.929074581259315750f, 0.369714292530311240f, + -0.929145490167611720f, + 0.369536124318350760f, -0.929216364913883930f, 0.369357942519603190f, + -0.929287205495526790f, + 0.369179747140620070f, -0.929358011909935500f, 0.369001538187952780f, + -0.929428784154506800f, + 0.368823315668153960f, -0.929499522226638560f, 0.368645079587776150f, + -0.929570226123729860f, + 0.368466829953372320f, -0.929640895843181330f, 0.368288566771496680f, + -0.929711531382394370f, + 0.368110290048703050f, -0.929782132738772190f, 0.367931999791546500f, + -0.929852699909718750f, + 0.367753696006582090f, -0.929923232892639560f, 0.367575378700365330f, + -0.929993731684941480f, + 0.367397047879452820f, -0.930064196284032360f, 0.367218703550400930f, + -0.930134626687321390f, + 0.367040345719767240f, -0.930205022892219070f, 0.366861974394109220f, + -0.930275384896137040f, + 0.366683589579984930f, -0.930345712696488470f, 0.366505191283953480f, + -0.930416006290687550f, + 0.366326779512573590f, -0.930486265676149780f, 0.366148354272405390f, + -0.930556490850291800f, + 0.365969915570008910f, -0.930626681810531650f, 0.365791463411944570f, + -0.930696838554288860f, + 0.365612997804773960f, -0.930766961078983710f, 0.365434518755058390f, + -0.930837049382038150f, + 0.365256026269360380f, -0.930907103460875020f, 0.365077520354242180f, + -0.930977123312918930f, + 0.364899001016267380f, -0.931047108935595170f, 0.364720468261999390f, + -0.931117060326330790f, + 0.364541922098002180f, -0.931186977482553750f, 0.364363362530840730f, + -0.931256860401693420f, + 0.364184789567079840f, -0.931326709081180430f, 0.364006203213285530f, + -0.931396523518446600f, + 0.363827603476023610f, -0.931466303710925090f, 0.363648990361860550f, + -0.931536049656050300f, + 0.363470363877363870f, -0.931605761351257830f, 0.363291724029100700f, + -0.931675438793984620f, + 0.363113070823639530f, -0.931745081981668720f, 0.362934404267548750f, + -0.931814690911749620f, + 0.362755724367397230f, -0.931884265581668150f, 0.362577031129754870f, + -0.931953805988865900f, + 0.362398324561191310f, -0.932023312130786490f, 0.362219604668277570f, + -0.932092784004874050f, + 0.362040871457584350f, -0.932162221608574320f, 0.361862124935682980f, + -0.932231624939334540f, + 0.361683365109145950f, -0.932300993994602640f, 0.361504591984545260f, + -0.932370328771828460f, + 0.361325805568454340f, -0.932439629268462360f, 0.361147005867446190f, + -0.932508895481956700f, + 0.360968192888095290f, -0.932578127409764420f, 0.360789366636975690f, + -0.932647325049340340f, + 0.360610527120662270f, -0.932716488398140250f, 0.360431674345730810f, + -0.932785617453620990f, + 0.360252808318756830f, -0.932854712213241230f, 0.360073929046317080f, + -0.932923772674460140f, + 0.359895036534988280f, -0.932992798834738850f, 0.359716130791347570f, + -0.933061790691539380f, + 0.359537211821973180f, -0.933130748242325110f, 0.359358279633443080f, + -0.933199671484560730f, + 0.359179334232336560f, -0.933268560415712050f, 0.359000375625232630f, + -0.933337415033246080f, + 0.358821403818710920f, -0.933406235334631520f, 0.358642418819352100f, + -0.933475021317337950f, + 0.358463420633736540f, -0.933543772978836170f, 0.358284409268445900f, + -0.933612490316598540f, + 0.358105384730061760f, -0.933681173328098300f, 0.357926347025166070f, + -0.933749822010810580f, + 0.357747296160342010f, -0.933818436362210960f, 0.357568232142172260f, + -0.933887016379776890f, + 0.357389154977241000f, -0.933955562060986730f, 0.357210064672131900f, + -0.934024073403320500f, + 0.357030961233430030f, -0.934092550404258870f, 0.356851844667720410f, + -0.934160993061284420f, + 0.356672714981588260f, -0.934229401371880820f, 0.356493572181620200f, + -0.934297775333532530f, + 0.356314416274402360f, -0.934366114943725900f, 0.356135247266522180f, + -0.934434420199948050f, + 0.355956065164567010f, -0.934502691099687870f, 0.355776869975124640f, + -0.934570927640435030f, + 0.355597661704783960f, -0.934639129819680780f, 0.355418440360133590f, + -0.934707297634917440f, + 0.355239205947763370f, -0.934775431083638700f, 0.355059958474263030f, + -0.934843530163339430f, + 0.354880697946222790f, -0.934911594871516090f, 0.354701424370233940f, + -0.934979625205665800f, + 0.354522137752887430f, -0.935047621163287430f, 0.354342838100775600f, + -0.935115582741880890f, + 0.354163525420490510f, -0.935183509938947500f, 0.353984199718624830f, + -0.935251402751989810f, + 0.353804861001772160f, -0.935319261178511500f, 0.353625509276525970f, + -0.935387085216017770f, + 0.353446144549480870f, -0.935454874862014620f, 0.353266766827231180f, + -0.935522630114009930f, + 0.353087376116372530f, -0.935590350969512370f, 0.352907972423500360f, + -0.935658037426032040f, + 0.352728555755210730f, -0.935725689481080370f, 0.352549126118100580f, + -0.935793307132169900f, + 0.352369683518766630f, -0.935860890376814640f, 0.352190227963806890f, + -0.935928439212529660f, + 0.352010759459819240f, -0.935995953636831300f, 0.351831278013402030f, + -0.936063433647237540f, + 0.351651783631154680f, -0.936130879241266920f, 0.351472276319676260f, + -0.936198290416440090f, + 0.351292756085567150f, -0.936265667170278260f, 0.351113222935427630f, + -0.936333009500304180f, + 0.350933676875858360f, -0.936400317404042060f, 0.350754117913461170f, + -0.936467590879016880f, + 0.350574546054837570f, -0.936534829922755500f, 0.350394961306590200f, + -0.936602034532785570f, + 0.350215363675321740f, -0.936669204706636060f, 0.350035753167635300f, + -0.936736340441837620f, + 0.349856129790135030f, -0.936803441735921560f, 0.349676493549424760f, + -0.936870508586420960f, + 0.349496844452109600f, -0.936937540990869900f, 0.349317182504794320f, + -0.937004538946803690f, + 0.349137507714085030f, -0.937071502451759190f, 0.348957820086587600f, + -0.937138431503274140f, + 0.348778119628908420f, -0.937205326098887960f, 0.348598406347655040f, + -0.937272186236140950f, + 0.348418680249434510f, -0.937339011912574960f, 0.348238941340855310f, + -0.937405803125732850f, + 0.348059189628525780f, -0.937472559873159140f, 0.347879425119054510f, + -0.937539282152399230f, + 0.347699647819051490f, -0.937605969960999990f, 0.347519857735126110f, + -0.937672623296509470f, + 0.347340054873889190f, -0.937739242156476970f, 0.347160239241951330f, + -0.937805826538453010f, + 0.346980410845923680f, -0.937872376439989890f, 0.346800569692418400f, + -0.937938891858640210f, + 0.346620715788047320f, -0.938005372791958840f, 0.346440849139423580f, + -0.938071819237501160f, + 0.346260969753160170f, -0.938138231192824360f, 0.346081077635870480f, + -0.938204608655486490f, + 0.345901172794169100f, -0.938270951623047080f, 0.345721255234670120f, + -0.938337260093066950f, + 0.345541324963989150f, -0.938403534063108060f, 0.345361381988741170f, + -0.938469773530733800f, + 0.345181426315542610f, -0.938535978493508560f, 0.345001457951009780f, + -0.938602148948998290f, + 0.344821476901759290f, -0.938668284894770170f, 0.344641483174409070f, + -0.938734386328392460f, + 0.344461476775576480f, -0.938800453247434770f, 0.344281457711880230f, + -0.938866485649468060f, + 0.344101425989938980f, -0.938932483532064490f, 0.343921381616371700f, + -0.938998446892797540f, + 0.343741324597798600f, -0.939064375729241950f, 0.343561254940839330f, + -0.939130270038973650f, + 0.343381172652115100f, -0.939196129819569900f, 0.343201077738246710f, + -0.939261955068609100f, + 0.343020970205855540f, -0.939327745783671400f, 0.342840850061564060f, + -0.939393501962337510f, + 0.342660717311994380f, -0.939459223602189920f, 0.342480571963769850f, + -0.939524910700812120f, + 0.342300414023513690f, -0.939590563255789160f, 0.342120243497849590f, + -0.939656181264707070f, + 0.341940060393402300f, -0.939721764725153340f, 0.341759864716796310f, + -0.939787313634716570f, + 0.341579656474657210f, -0.939852827990986680f, 0.341399435673610360f, + -0.939918307791555050f, + 0.341219202320282410f, -0.939983753034013940f, 0.341038956421299830f, + -0.940049163715957370f, + 0.340858697983289440f, -0.940114539834980280f, 0.340678427012879310f, + -0.940179881388678810f, + 0.340498143516697100f, -0.940245188374650880f, 0.340317847501371730f, + -0.940310460790495070f, + 0.340137538973531880f, -0.940375698633811540f, 0.339957217939806880f, + -0.940440901902201750f, + 0.339776884406826960f, -0.940506070593268300f, 0.339596538381222060f, + -0.940571204704615190f, + 0.339416179869623410f, -0.940636304233847590f, 0.339235808878662120f, + -0.940701369178571940f, + 0.339055425414969640f, -0.940766399536396070f, 0.338875029485178560f, + -0.940831395304928870f, + 0.338694621095921190f, -0.940896356481780830f, 0.338514200253831000f, + -0.940961283064563280f, + 0.338333766965541290f, -0.941026175050889260f, 0.338153321237685990f, + -0.941091032438372780f, + 0.337972863076899830f, -0.941155855224629190f, 0.337792392489817460f, + -0.941220643407275180f, + 0.337611909483074680f, -0.941285396983928660f, 0.337431414063306790f, + -0.941350115952208970f, + 0.337250906237150650f, -0.941414800309736230f, 0.337070386011242730f, + -0.941479450054132580f, + 0.336889853392220050f, -0.941544065183020810f, 0.336709308386720700f, + -0.941608645694025140f, + 0.336528751001382350f, -0.941673191584771360f, 0.336348181242844100f, + -0.941737702852886160f, + 0.336167599117744690f, -0.941802179495997650f, 0.335987004632723350f, + -0.941866621511735280f, + 0.335806397794420560f, -0.941931028897729510f, 0.335625778609476230f, + -0.941995401651612550f, + 0.335445147084531660f, -0.942059739771017310f, 0.335264503226227970f, + -0.942124043253578460f, + 0.335083847041206580f, -0.942188312096931770f, 0.334903178536110290f, + -0.942252546298714020f, + 0.334722497717581220f, -0.942316745856563780f, 0.334541804592262960f, + -0.942380910768120470f, + 0.334361099166798900f, -0.942445041031024890f, 0.334180381447832740f, + -0.942509136642919240f, + 0.333999651442009490f, -0.942573197601446870f, 0.333818909155973620f, + -0.942637223904252530f, + 0.333638154596370920f, -0.942701215548981900f, 0.333457387769846790f, + -0.942765172533282510f, + 0.333276608683047980f, -0.942829094854802710f, 0.333095817342620890f, + -0.942892982511192130f, + 0.332915013755212650f, -0.942956835500102120f, 0.332734197927471160f, + -0.943020653819184650f, + 0.332553369866044220f, -0.943084437466093490f, 0.332372529577580680f, + -0.943148186438483420f, + 0.332191677068729320f, -0.943211900734010620f, 0.332010812346139380f, + -0.943275580350332540f, + 0.331829935416461220f, -0.943339225285107720f, 0.331649046286344620f, + -0.943402835535996240f, + 0.331468144962440920f, -0.943466411100659320f, 0.331287231451400990f, + -0.943529951976759370f, + 0.331106305759876430f, -0.943593458161960390f, 0.330925367894519650f, + -0.943656929653927110f, + 0.330744417861982890f, -0.943720366450326200f, 0.330563455668919590f, + -0.943783768548825060f, + 0.330382481321982950f, -0.943847135947092690f, 0.330201494827826620f, + -0.943910468642799150f, + 0.330020496193105530f, -0.943973766633615980f, 0.329839485424473940f, + -0.944037029917215830f, + 0.329658462528587550f, -0.944100258491272660f, 0.329477427512101680f, + -0.944163452353461770f, + 0.329296380381672800f, -0.944226611501459810f, 0.329115321143957360f, + -0.944289735932944410f, + 0.328934249805612200f, -0.944352825645594750f, 0.328753166373295100f, + -0.944415880637091250f, + 0.328572070853663690f, -0.944478900905115550f, 0.328390963253376630f, + -0.944541886447350380f, + 0.328209843579092660f, -0.944604837261480260f, 0.328028711837470730f, + -0.944667753345190490f, + 0.327847568035170960f, -0.944730634696167800f, 0.327666412178853060f, + -0.944793481312100280f, + 0.327485244275178060f, -0.944856293190677210f, 0.327304064330806830f, + -0.944919070329589220f, + 0.327122872352400510f, -0.944981812726528150f, 0.326941668346621530f, + -0.945044520379187070f, + 0.326760452320131790f, -0.945107193285260610f, 0.326579224279594460f, + -0.945169831442444150f, + 0.326397984231672660f, -0.945232434848434890f, 0.326216732183029770f, + -0.945295003500931100f, + 0.326035468140330350f, -0.945357537397632290f, 0.325854192110238580f, + -0.945420036536239070f, + 0.325672904099419900f, -0.945482500914453740f, 0.325491604114539260f, + -0.945544930529979680f, + 0.325310292162262980f, -0.945607325380521280f, 0.325128968249257190f, + -0.945669685463784710f, + 0.324947632382188430f, -0.945732010777477150f, 0.324766284567724330f, + -0.945794301319306860f, + 0.324584924812532150f, -0.945856557086983910f, 0.324403553123280290f, + -0.945918778078219110f, + 0.324222169506637130f, -0.945980964290724760f, 0.324040773969271450f, + -0.946043115722214560f, + 0.323859366517852960f, -0.946105232370403340f, 0.323677947159051180f, + -0.946167314233007370f, + 0.323496515899536760f, -0.946229361307743820f, 0.323315072745980150f, + -0.946291373592331510f, + 0.323133617705052330f, -0.946353351084490590f, 0.322952150783425370f, + -0.946415293781942110f, + 0.322770671987770710f, -0.946477201682408680f, 0.322589181324761390f, + -0.946539074783614100f, + 0.322407678801070020f, -0.946600913083283530f, 0.322226164423369650f, + -0.946662716579143360f, + 0.322044638198334620f, -0.946724485268921170f, 0.321863100132638580f, + -0.946786219150346000f, + 0.321681550232956640f, -0.946847918221148000f, 0.321499988505963450f, + -0.946909582479058760f, + 0.321318414958334910f, -0.946971211921810880f, 0.321136829596746780f, + -0.947032806547138620f, + 0.320955232427875210f, -0.947094366352777220f, 0.320773623458397440f, + -0.947155891336463270f, + 0.320592002694990330f, -0.947217381495934820f, 0.320410370144331880f, + -0.947278836828930880f, + 0.320228725813100020f, -0.947340257333191940f, 0.320047069707973140f, + -0.947401643006459900f, + 0.319865401835630610f, -0.947462993846477700f, 0.319683722202751370f, + -0.947524309850989570f, + 0.319502030816015750f, -0.947585591017741090f, 0.319320327682103720f, + -0.947646837344479190f, + 0.319138612807695900f, -0.947708048828952100f, 0.318956886199473770f, + -0.947769225468909180f, + 0.318775147864118480f, -0.947830367262101010f, 0.318593397808312470f, + -0.947891474206279730f, + 0.318411636038737960f, -0.947952546299198560f, 0.318229862562077580f, + -0.948013583538612200f, + 0.318048077385015060f, -0.948074585922276230f, 0.317866280514233660f, + -0.948135553447947980f, + 0.317684471956418020f, -0.948196486113385580f, 0.317502651718252260f, + -0.948257383916349060f, + 0.317320819806421790f, -0.948318246854599090f, 0.317138976227611890f, + -0.948379074925898120f, + 0.316957120988508150f, -0.948439868128009620f, 0.316775254095797380f, + -0.948500626458698260f, + 0.316593375556165850f, -0.948561349915730270f, 0.316411485376301090f, + -0.948622038496872990f, + 0.316229583562890490f, -0.948682692199895090f, 0.316047670122621860f, + -0.948743311022566480f, + 0.315865745062184070f, -0.948803894962658380f, 0.315683808388265600f, + -0.948864444017943340f, + 0.315501860107556040f, -0.948924958186195160f, 0.315319900226745050f, + -0.948985437465188710f, + 0.315137928752522440f, -0.949045881852700560f, 0.314955945691579250f, + -0.949106291346508260f, + 0.314773951050606070f, -0.949166665944390700f, 0.314591944836294710f, + -0.949227005644128210f, + 0.314409927055336820f, -0.949287310443502010f, 0.314227897714424500f, + -0.949347580340295210f, + 0.314045856820250820f, -0.949407815332291460f, 0.313863804379508500f, + -0.949468015417276550f, + 0.313681740398891570f, -0.949528180593036670f, 0.313499664885093450f, + -0.949588310857359950f, + 0.313317577844809070f, -0.949648406208035480f, 0.313135479284732950f, + -0.949708466642853800f, + 0.312953369211560200f, -0.949768492159606680f, 0.312771247631986880f, + -0.949828482756087000f, + 0.312589114552708660f, -0.949888438430089300f, 0.312406969980422500f, + -0.949948359179409010f, + 0.312224813921825050f, -0.950008245001843000f, 0.312042646383613510f, + -0.950068095895189590f, + 0.311860467372486130f, -0.950127911857248100f, 0.311678276895140550f, + -0.950187692885819280f, + 0.311496074958275970f, -0.950247438978705230f, 0.311313861568591090f, + -0.950307150133709140f, + 0.311131636732785270f, -0.950366826348635780f, 0.310949400457558760f, + -0.950426467621290900f, + 0.310767152749611470f, -0.950486073949481700f, 0.310584893615644560f, + -0.950545645331016600f, + 0.310402623062358880f, -0.950605181763705230f, 0.310220341096455910f, + -0.950664683245358910f, + 0.310038047724638000f, -0.950724149773789610f, 0.309855742953607130f, + -0.950783581346811070f, + 0.309673426790066490f, -0.950842977962238160f, 0.309491099240719050f, + -0.950902339617887060f, + 0.309308760312268780f, -0.950961666311575080f, 0.309126410011419550f, + -0.951020958041121080f, + 0.308944048344875710f, -0.951080214804345010f, 0.308761675319342570f, + -0.951139436599068190f, + 0.308579290941525030f, -0.951198623423113230f, 0.308396895218129240f, + -0.951257775274304000f, + 0.308214488155861220f, -0.951316892150465550f, 0.308032069761427330f, + -0.951375974049424420f, + 0.307849640041534980f, -0.951435020969008340f, 0.307667199002891190f, + -0.951494032907046370f, + 0.307484746652204160f, -0.951553009861368590f, 0.307302282996181950f, + -0.951611951829806730f, + 0.307119808041533100f, -0.951670858810193860f, 0.306937321794967020f, + -0.951729730800363720f, + 0.306754824263192780f, -0.951788567798152130f, 0.306572315452920800f, + -0.951847369801395620f, + 0.306389795370861080f, -0.951906136807932230f, 0.306207264023724280f, + -0.951964868815601380f, + 0.306024721418221900f, -0.952023565822243570f, 0.305842167561065080f, + -0.952082227825700620f, + 0.305659602458966230f, -0.952140854823815830f, 0.305477026118637360f, + -0.952199446814433580f, + 0.305294438546791720f, -0.952258003795399600f, 0.305111839750142220f, + -0.952316525764560830f, + 0.304929229735402430f, -0.952375012719765880f, 0.304746608509286640f, + -0.952433464658864030f, + 0.304563976078509050f, -0.952491881579706320f, 0.304381332449784940f, + -0.952550263480144930f, + 0.304198677629829270f, -0.952608610358033240f, 0.304016011625357570f, + -0.952666922211226170f, + 0.303833334443086470f, -0.952725199037579570f, 0.303650646089731910f, + -0.952783440834950920f, + 0.303467946572011370f, -0.952841647601198720f, 0.303285235896641910f, + -0.952899819334182880f, + 0.303102514070341060f, -0.952957956031764700f, 0.302919781099827420f, + -0.953016057691806530f, + 0.302737036991819140f, -0.953074124312172200f, 0.302554281753035670f, + -0.953132155890726750f, + 0.302371515390196130f, -0.953190152425336560f, 0.302188737910020040f, + -0.953248113913869320f, + 0.302005949319228200f, -0.953306040354193750f, 0.301823149624540650f, + -0.953363931744180330f, + 0.301640338832678880f, -0.953421788081700310f, 0.301457516950363940f, + -0.953479609364626610f, + 0.301274683984318000f, -0.953537395590833280f, 0.301091839941263210f, + -0.953595146758195680f, + 0.300908984827921890f, -0.953652862864590500f, 0.300726118651017620f, + -0.953710543907895560f, + 0.300543241417273400f, -0.953768189885990330f, 0.300360353133413580f, + -0.953825800796755050f, + 0.300177453806162120f, -0.953883376638071770f, 0.299994543442243580f, + -0.953940917407823500f, + 0.299811622048383460f, -0.953998423103894490f, 0.299628689631306790f, + -0.954055893724170660f, + 0.299445746197739950f, -0.954113329266538800f, 0.299262791754409010f, + -0.954170729728887280f, + 0.299079826308040480f, -0.954228095109105670f, 0.298896849865361910f, + -0.954285425405084650f, + 0.298713862433100390f, -0.954342720614716480f, 0.298530864017984230f, + -0.954399980735894490f, + 0.298347854626741570f, -0.954457205766513490f, 0.298164834266100910f, + -0.954514395704469500f, + 0.297981802942791920f, -0.954571550547659630f, 0.297798760663543550f, + -0.954628670293982680f, + 0.297615707435086310f, -0.954685754941338340f, 0.297432643264150030f, + -0.954742804487627940f, + 0.297249568157465890f, -0.954799818930753720f, 0.297066482121764840f, + -0.954856798268619580f, + 0.296883385163778270f, -0.954913742499130520f, 0.296700277290238460f, + -0.954970651620192790f, + 0.296517158507877410f, -0.955027525629714160f, 0.296334028823428240f, + -0.955084364525603410f, + 0.296150888243623960f, -0.955141168305770670f, 0.295967736775197890f, + -0.955197936968127710f, + 0.295784574424884370f, -0.955254670510586990f, 0.295601401199417360f, + -0.955311368931062720f, + 0.295418217105532070f, -0.955368032227470240f, 0.295235022149963390f, + -0.955424660397726330f, + 0.295051816339446720f, -0.955481253439748770f, 0.294868599680718380f, + -0.955537811351456770f, + 0.294685372180514330f, -0.955594334130771110f, 0.294502133845571720f, + -0.955650821775613220f, + 0.294318884682627570f, -0.955707274283906560f, 0.294135624698419080f, + -0.955763691653575440f, + 0.293952353899684770f, -0.955820073882545420f, 0.293769072293162400f, + -0.955876420968743590f, + 0.293585779885591310f, -0.955932732910098170f, 0.293402476683710060f, + -0.955989009704538930f, + 0.293219162694258680f, -0.956045251349996410f, 0.293035837923976920f, + -0.956101457844403040f, + 0.292852502379604810f, -0.956157629185692140f, 0.292669156067883570f, + -0.956213765371798470f, + 0.292485798995553830f, -0.956269866400658140f, 0.292302431169357610f, + -0.956325932270208230f, + 0.292119052596036540f, -0.956381962978387620f, 0.291935663282332780f, + -0.956437958523136180f, + 0.291752263234989370f, -0.956493918902394990f, 0.291568852460749040f, + -0.956549844114106820f, + 0.291385430966355720f, -0.956605734156215080f, 0.291201998758553020f, + -0.956661589026664980f, + 0.291018555844085090f, -0.956717408723403050f, 0.290835102229696940f, + -0.956773193244376930f, + 0.290651637922133220f, -0.956828942587535370f, 0.290468162928139870f, + -0.956884656750828900f, + 0.290284677254462330f, -0.956940335732208940f, 0.290101180907847140f, + -0.956995979529628230f, + 0.289917673895040860f, -0.957051588141040970f, 0.289734156222790250f, + -0.957107161564402790f, + 0.289550627897843140f, -0.957162699797670100f, 0.289367088926946960f, + -0.957218202838801210f, + 0.289183539316850310f, -0.957273670685755200f, 0.288999979074301530f, + -0.957329103336492790f, + 0.288816408206049480f, -0.957384500788975860f, 0.288632826718843940f, + -0.957439863041167570f, + 0.288449234619434170f, -0.957495190091032570f, 0.288265631914570830f, + -0.957550481936536470f, + 0.288082018611004300f, -0.957605738575646240f, 0.287898394715485170f, + -0.957660960006330610f, + 0.287714760234765280f, -0.957716146226558870f, 0.287531115175595930f, + -0.957771297234302320f, + 0.287347459544729570f, -0.957826413027532910f, 0.287163793348918560f, + -0.957881493604224250f, + 0.286980116594915570f, -0.957936538962351420f, 0.286796429289474190f, + -0.957991549099890370f, + 0.286612731439347790f, -0.958046524014818600f, 0.286429023051290750f, + -0.958101463705114620f, + 0.286245304132057120f, -0.958156368168758820f, 0.286061574688402100f, + -0.958211237403732260f, + 0.285877834727080730f, -0.958266071408017670f, 0.285694084254848320f, + -0.958320870179598880f, + 0.285510323278461380f, -0.958375633716461170f, 0.285326551804675810f, + -0.958430362016591040f, + 0.285142769840248720f, -0.958485055077976100f, 0.284958977391937150f, + -0.958539712898605730f, + 0.284775174466498300f, -0.958594335476470220f, 0.284591361070690550f, + -0.958648922809561040f, + 0.284407537211271820f, -0.958703474895871600f, 0.284223702895001100f, + -0.958757991733395710f, + 0.284039858128637360f, -0.958812473320129200f, 0.283856002918939750f, + -0.958866919654069010f, + 0.283672137272668550f, -0.958921330733213060f, 0.283488261196583550f, + -0.958975706555561080f, + 0.283304374697445790f, -0.959030047119113550f, 0.283120477782015990f, + -0.959084352421872730f, + 0.282936570457055390f, -0.959138622461841890f, 0.282752652729326040f, + -0.959192857237025740f, + 0.282568724605589740f, -0.959247056745430090f, 0.282384786092609420f, + -0.959301220985062210f, + 0.282200837197147500f, -0.959355349953930790f, 0.282016877925967690f, + -0.959409443650045550f, + 0.281832908285833460f, -0.959463502071417510f, 0.281648928283508680f, + -0.959517525216059260f, + 0.281464937925758050f, -0.959571513081984520f, 0.281280937219346110f, + -0.959625465667208300f, + 0.281096926171038320f, -0.959679382969746750f, 0.280912904787600120f, + -0.959733264987617680f, + 0.280728873075797190f, -0.959787111718839900f, 0.280544831042396360f, + -0.959840923161433660f, + 0.280360778694163810f, -0.959894699313420530f, 0.280176716037867040f, + -0.959948440172823210f, + 0.279992643080273380f, -0.960002145737665850f, 0.279808559828150390f, + -0.960055816005973890f, + 0.279624466288266700f, -0.960109450975773940f, 0.279440362467390510f, + -0.960163050645094000f, + 0.279256248372291240f, -0.960216615011963430f, 0.279072124009737970f, + -0.960270144074412800f, + 0.278887989386500280f, -0.960323637830473920f, 0.278703844509348600f, + -0.960377096278180130f, + 0.278519689385053060f, -0.960430519415565790f, 0.278335524020384970f, + -0.960483907240666790f, + 0.278151348422115090f, -0.960537259751520050f, 0.277967162597015430f, + -0.960590576946164120f, + 0.277782966551857800f, -0.960643858822638470f, 0.277598760293414290f, + -0.960697105378984450f, + 0.277414543828458200f, -0.960750316613243950f, 0.277230317163762120f, + -0.960803492523460760f, + 0.277046080306099950f, -0.960856633107679660f, 0.276861833262245390f, + -0.960909738363946770f, + 0.276677576038972420f, -0.960962808290309780f, 0.276493308643056100f, + -0.961015842884817230f, + 0.276309031081271030f, -0.961068842145519350f, 0.276124743360392890f, + -0.961121806070467380f, + 0.275940445487197320f, -0.961174734657714080f, 0.275756137468460120f, + -0.961227627905313460f, + 0.275571819310958250f, -0.961280485811320640f, 0.275387491021468140f, + -0.961333308373792270f, + 0.275203152606767370f, -0.961386095590786250f, 0.275018804073633380f, + -0.961438847460361570f, + 0.274834445428843940f, -0.961491563980579000f, 0.274650076679177790f, + -0.961544245149499990f, + 0.274465697831413220f, -0.961596890965187860f, 0.274281308892329710f, + -0.961649501425706820f, + 0.274096909868706330f, -0.961702076529122540f, 0.273912500767323320f, + -0.961754616273502010f, + 0.273728081594960650f, -0.961807120656913540f, 0.273543652358398730f, + -0.961859589677426570f, + 0.273359213064418790f, -0.961912023333112100f, 0.273174763719801870f, + -0.961964421622042320f, + 0.272990304331329980f, -0.962016784542290560f, 0.272805834905784920f, + -0.962069112091931580f, + 0.272621355449948980f, -0.962121404269041580f, 0.272436865970605350f, + -0.962173661071697770f, + 0.272252366474536660f, -0.962225882497979020f, 0.272067856968526980f, + -0.962278068545965090f, + 0.271883337459359890f, -0.962330219213737400f, 0.271698807953819510f, + -0.962382334499378380f, + 0.271514268458690810f, -0.962434414400971990f, 0.271329718980758420f, + -0.962486458916603450f, + 0.271145159526808070f, -0.962538468044359160f, 0.270960590103625330f, + -0.962590441782326780f, + 0.270776010717996010f, -0.962642380128595710f, 0.270591421376707050f, + -0.962694283081255930f, + 0.270406822086544820f, -0.962746150638399410f, 0.270222212854296930f, + -0.962797982798119010f, + 0.270037593686750510f, -0.962849779558509030f, 0.269852964590693910f, + -0.962901540917665000f, + 0.269668325572915200f, -0.962953266873683880f, 0.269483676640202840f, + -0.963004957424663850f, + 0.269299017799346230f, -0.963056612568704340f, 0.269114349057134330f, + -0.963108232303906190f, + 0.268929670420357310f, -0.963159816628371360f, 0.268744981895805090f, + -0.963211365540203480f, + 0.268560283490267890f, -0.963262879037507070f, 0.268375575210537010f, + -0.963314357118388090f, + 0.268190857063403180f, -0.963365799780954050f, 0.268006129055658350f, + -0.963417207023313350f, + 0.267821391194094320f, -0.963468578843575950f, 0.267636643485503090f, + -0.963519915239853140f, + 0.267451885936677740f, -0.963571216210257210f, 0.267267118554410930f, + -0.963622481752902220f, + 0.267082341345496350f, -0.963673711865903230f, 0.266897554316727510f, + -0.963724906547376410f, + 0.266712757474898420f, -0.963776065795439840f, 0.266527950826803810f, + -0.963827189608212340f, + 0.266343134379238180f, -0.963878277983814200f, 0.266158308138997050f, + -0.963929330920367140f, + 0.265973472112875530f, -0.963980348415994110f, 0.265788626307669970f, + -0.964031330468819280f, + 0.265603770730176440f, -0.964082277076968140f, 0.265418905387191260f, + -0.964133188238567640f, + 0.265234030285511900f, -0.964184063951745720f, 0.265049145431935200f, + -0.964234904214632200f, + 0.264864250833259320f, -0.964285709025357370f, 0.264679346496282050f, + -0.964336478382053720f, + 0.264494432427801630f, -0.964387212282854290f, 0.264309508634617220f, + -0.964437910725893910f, + 0.264124575123527490f, -0.964488573709308410f, 0.263939631901332410f, + -0.964539201231235150f, + 0.263754678974831510f, -0.964589793289812650f, 0.263569716350824880f, + -0.964640349883180930f, + 0.263384744036113390f, -0.964690871009480920f, 0.263199762037497560f, + -0.964741356666855340f, + 0.263014770361779060f, -0.964791806853447900f, 0.262829769015759330f, + -0.964842221567403510f, + 0.262644758006240100f, -0.964892600806868890f, 0.262459737340024090f, + -0.964942944569991410f, + 0.262274707023913590f, -0.964993252854920320f, 0.262089667064712100f, + -0.965043525659805890f, + 0.261904617469222560f, -0.965093762982799590f, 0.261719558244249080f, + -0.965143964822054450f, + 0.261534489396595630f, -0.965194131175724720f, 0.261349410933066350f, + -0.965244262041965780f, + 0.261164322860466590f, -0.965294357418934660f, 0.260979225185601020f, + -0.965344417304789370f, + 0.260794117915275570f, -0.965394441697689400f, 0.260609001056295920f, + -0.965444430595795430f, + 0.260423874615468010f, -0.965494383997269500f, 0.260238738599598950f, + -0.965544301900275070f, + 0.260053593015495130f, -0.965594184302976830f, 0.259868437869964330f, + -0.965644031203540590f, + 0.259683273169813930f, -0.965693842600133690f, 0.259498098921851660f, + -0.965743618490924830f, + 0.259312915132886350f, -0.965793358874083570f, 0.259127721809726150f, + -0.965843063747781510f, + 0.258942518959180580f, -0.965892733110190860f, 0.258757306588058840f, + -0.965942366959485540f, + 0.258572084703170390f, -0.965991965293840570f, 0.258386853311325710f, + -0.966041528111432400f, + 0.258201612419334870f, -0.966091055410438830f, 0.258016362034009070f, + -0.966140547189038750f, + 0.257831102162158930f, -0.966190003445412620f, 0.257645832810596440f, + -0.966239424177741890f, + 0.257460553986133210f, -0.966288809384209580f, 0.257275265695581120f, + -0.966338159063000130f, + 0.257089967945753230f, -0.966387473212298790f, 0.256904660743461850f, + -0.966436751830292650f, + 0.256719344095520720f, -0.966485994915169840f, 0.256534018008743200f, + -0.966535202465119700f, + 0.256348682489942910f, -0.966584374478333120f, 0.256163337545934570f, + -0.966633510953002100f, + 0.255977983183532380f, -0.966682611887320190f, 0.255792619409551670f, + -0.966731677279481840f, + 0.255607246230807550f, -0.966780707127683270f, 0.255421863654115460f, + -0.966829701430121810f, + 0.255236471686291820f, -0.966878660184995910f, 0.255051070334152530f, + -0.966927583390505660f, + 0.254865659604514630f, -0.966976471044852070f, 0.254680239504194990f, + -0.967025323146237900f, + 0.254494810040010790f, -0.967074139692867040f, 0.254309371218780110f, + -0.967122920682944360f, + 0.254123923047320620f, -0.967171666114676640f, 0.253938465532451140f, + -0.967220375986271310f, + 0.253752998680989940f, -0.967269050295937790f, 0.253567522499756610f, + -0.967317689041886310f, + 0.253382036995570270f, -0.967366292222328510f, 0.253196542175250560f, + -0.967414859835477480f, + 0.253011038045617980f, -0.967463391879547440f, 0.252825524613492610f, + -0.967511888352754150f, + 0.252640001885695580f, -0.967560349253314360f, 0.252454469869047900f, + -0.967608774579446380f, + 0.252268928570370810f, -0.967657164329369880f, 0.252083377996486560f, + -0.967705518501305480f, + 0.251897818154216910f, -0.967753837093475510f, 0.251712249050384750f, + -0.967802120104103270f, + 0.251526670691812780f, -0.967850367531413620f, 0.251341083085323880f, + -0.967898579373632660f, + 0.251155486237742030f, -0.967946755628987800f, 0.250969880155890720f, + -0.967994896295707670f, + 0.250784264846594550f, -0.968043001372022260f, 0.250598640316677830f, + -0.968091070856162970f, + 0.250413006572965280f, -0.968139104746362330f, 0.250227363622282540f, + -0.968187103040854420f, + 0.250041711471454650f, -0.968235065737874320f, 0.249856050127308050f, + -0.968282992835658660f, + 0.249670379596668520f, -0.968330884332445300f, 0.249484699886363010f, + -0.968378740226473300f, + 0.249299011003218300f, -0.968426560515983190f, 0.249113312954061360f, + -0.968474345199216820f, + 0.248927605745720260f, -0.968522094274417270f, 0.248741889385022420f, + -0.968569807739828930f, + 0.248556163878796620f, -0.968617485593697540f, 0.248370429233871150f, + -0.968665127834269950f, + 0.248184685457074780f, -0.968712734459794780f, 0.247998932555237220f, + -0.968760305468521430f, + 0.247813170535187620f, -0.968807840858700970f, 0.247627399403756330f, + -0.968855340628585580f, + 0.247441619167773440f, -0.968902804776428870f, 0.247255829834069320f, + -0.968950233300485800f, + 0.247070031409475370f, -0.968997626199012310f, 0.246884223900822430f, + -0.969044983470266240f, + 0.246698407314942500f, -0.969092305112506100f, 0.246512581658667380f, + -0.969139591123992280f, + 0.246326746938829060f, -0.969186841502985950f, 0.246140903162260640f, + -0.969234056247750050f, + 0.245955050335794590f, -0.969281235356548530f, 0.245769188466264670f, + -0.969328378827646660f, + 0.245583317560504000f, -0.969375486659311280f, 0.245397437625346990f, + -0.969422558849810320f, + 0.245211548667627680f, -0.969469595397412950f, 0.245025650694180470f, + -0.969516596300390000f, + 0.244839743711840750f, -0.969563561557013180f, 0.244653827727443320f, + -0.969610491165555870f, + 0.244467902747824210f, -0.969657385124292450f, 0.244281968779819170f, + -0.969704243431498750f, + 0.244096025830264210f, -0.969751066085452140f, 0.243910073905996370f, + -0.969797853084430890f, + 0.243724113013852130f, -0.969844604426714830f, 0.243538143160669180f, + -0.969891320110585100f, + 0.243352164353284880f, -0.969938000134323960f, 0.243166176598536930f, + -0.969984644496215240f, + 0.242980179903263980f, -0.970031253194543970f, 0.242794174274304190f, + -0.970077826227596420f, + 0.242608159718496890f, -0.970124363593660280f, 0.242422136242681050f, + -0.970170865291024360f, + 0.242236103853696040f, -0.970217331317979160f, 0.242050062558382180f, + -0.970263761672816140f, + 0.241864012363579210f, -0.970310156353828110f, 0.241677953276128090f, + -0.970356515359309450f, + 0.241491885302869300f, -0.970402838687555500f, 0.241305808450644390f, + -0.970449126336863090f, + 0.241119722726294730f, -0.970495378305530450f, 0.240933628136661910f, + -0.970541594591857070f, + 0.240747524688588540f, -0.970587775194143630f, 0.240561412388916620f, + -0.970633920110692160f, + 0.240375291244489500f, -0.970680029339806130f, 0.240189161262150040f, + -0.970726102879790110f, + 0.240003022448741500f, -0.970772140728950350f, 0.239816874811108110f, + -0.970818142885593870f, + 0.239630718356093560f, -0.970864109348029470f, 0.239444553090542720f, + -0.970910040114567050f, + 0.239258379021300120f, -0.970955935183517970f, 0.239072196155210660f, + -0.971001794553194690f, + 0.238886004499120170f, -0.971047618221911100f, 0.238699804059873950f, + -0.971093406187982460f, + 0.238513594844318500f, -0.971139158449725090f, 0.238327376859299970f, + -0.971184875005457030f, + 0.238141150111664870f, -0.971230555853497380f, 0.237954914608260650f, + -0.971276200992166490f, + 0.237768670355934210f, -0.971321810419786160f, 0.237582417361533650f, + -0.971367384134679490f, + 0.237396155631906550f, -0.971412922135170940f, 0.237209885173901620f, + -0.971458424419585960f, + 0.237023605994367340f, -0.971503890986251780f, 0.236837318100152380f, + -0.971549321833496630f, + 0.236651021498106460f, -0.971594716959650160f, 0.236464716195078750f, + -0.971640076363043390f, + 0.236278402197919620f, -0.971685400042008540f, 0.236092079513479050f, + -0.971730687994879160f, + 0.235905748148607370f, -0.971775940219990140f, 0.235719408110155930f, + -0.971821156715677700f, + 0.235533059404975460f, -0.971866337480279400f, 0.235346702039917920f, + -0.971911482512134000f, + 0.235160336021834860f, -0.971956591809581600f, 0.234973961357578310f, + -0.972001665370963890f, + 0.234787578054001080f, -0.972046703194623380f, 0.234601186117955550f, + -0.972091705278904430f, + 0.234414785556295250f, -0.972136671622152120f, 0.234228376375873380f, + -0.972181602222713440f, + 0.234041958583543460f, -0.972226497078936270f, 0.233855532186159950f, + -0.972271356189170040f, + 0.233669097190576820f, -0.972316179551765300f, 0.233482653603649170f, + -0.972360967165074140f, + 0.233296201432231560f, -0.972405719027449770f, 0.233109740683179740f, + -0.972450435137246830f, + 0.232923271363349120f, -0.972495115492821190f, 0.232736793479595420f, + -0.972539760092530180f, + 0.232550307038775330f, -0.972584368934732210f, 0.232363812047745010f, + -0.972628942017787270f, + 0.232177308513361770f, -0.972673479340056430f, 0.231990796442482580f, + -0.972717980899902250f, + 0.231804275841964780f, -0.972762446695688570f, 0.231617746718666580f, + -0.972806876725780370f, + 0.231431209079445730f, -0.972851270988544180f, 0.231244662931161110f, + -0.972895629482347760f, + 0.231058108280671280f, -0.972939952205560070f, 0.230871545134835070f, + -0.972984239156551740f, + 0.230684973500512310f, -0.973028490333694100f, 0.230498393384562320f, + -0.973072705735360530f, + 0.230311804793845530f, -0.973116885359925130f, 0.230125207735222020f, + -0.973161029205763530f, + 0.229938602215552260f, -0.973205137271252800f, 0.229751988241697600f, + -0.973249209554771120f, + 0.229565365820518870f, -0.973293246054698250f, 0.229378734958878120f, + -0.973337246769414800f, + 0.229192095663636740f, -0.973381211697303290f, 0.229005447941657390f, + -0.973425140836747030f, + 0.228818791799802360f, -0.973469034186130950f, 0.228632127244934230f, + -0.973512891743841370f, + 0.228445454283916550f, -0.973556713508265560f, 0.228258772923612350f, + -0.973600499477792370f, + 0.228072083170885790f, -0.973644249650811870f, 0.227885385032600700f, + -0.973687964025715670f, + 0.227698678515621170f, -0.973731642600896400f, 0.227511963626812390f, + -0.973775285374748000f, + 0.227325240373038830f, -0.973818892345666100f, 0.227138508761166260f, + -0.973862463512047300f, + 0.226951768798059980f, -0.973905998872289460f, 0.226765020490585720f, + -0.973949498424792170f, + 0.226578263845610110f, -0.973992962167955830f, 0.226391498869999210f, + -0.974036390100182610f, + 0.226204725570620270f, -0.974079782219875680f, 0.226017943954340190f, + -0.974123138525439520f, + 0.225831154028026200f, -0.974166459015280320f, 0.225644355798546440f, + -0.974209743687805110f, + 0.225457549272768540f, -0.974252992541422500f, 0.225270734457561240f, + -0.974296205574542330f, + 0.225083911359792780f, -0.974339382785575860f, 0.224897079986332540f, + -0.974382524172935470f, + 0.224710240344049570f, -0.974425629735034990f, 0.224523392439813170f, + -0.974468699470289580f, + 0.224336536280493690f, -0.974511733377115720f, 0.224149671872960840f, + -0.974554731453931230f, + 0.223962799224085520f, -0.974597693699155050f, 0.223775918340738290f, + -0.974640620111207560f, + 0.223589029229790020f, -0.974683510688510670f, 0.223402131898112480f, + -0.974726365429487320f, + 0.223215226352576960f, -0.974769184332561770f, 0.223028312600055870f, + -0.974811967396159830f, + 0.222841390647421280f, -0.974854714618708430f, 0.222654460501545550f, + -0.974897425998635820f, + 0.222467522169301990f, -0.974940101534371720f, 0.222280575657563370f, + -0.974982741224347140f, + 0.222093620973203590f, -0.975025345066994120f, 0.221906658123096260f, + -0.975067913060746360f, + 0.221719687114115240f, -0.975110445204038890f, 0.221532707953135340f, + -0.975152941495307620f, + 0.221345720647030810f, -0.975195401932990370f, 0.221158725202677100f, + -0.975237826515525820f, + 0.220971721626949060f, -0.975280215241354220f, 0.220784709926722670f, + -0.975322568108916930f, + 0.220597690108873650f, -0.975364885116656870f, 0.220410662180277940f, + -0.975407166263018270f, + 0.220223626147812460f, -0.975449411546446380f, 0.220036582018353550f, + -0.975491620965388110f, + 0.219849529798778750f, -0.975533794518291360f, 0.219662469495965180f, + -0.975575932203605610f, + 0.219475401116790340f, -0.975618034019781750f, 0.219288324668132580f, + -0.975660099965271590f, + 0.219101240156869770f, -0.975702130038528570f, 0.218914147589880900f, + -0.975744124238007270f, + 0.218727046974044600f, -0.975786082562163930f, 0.218539938316239830f, + -0.975828005009455550f, + 0.218352821623346430f, -0.975869891578341030f, 0.218165696902243770f, + -0.975911742267280170f, + 0.217978564159812290f, -0.975953557074734300f, 0.217791423402932120f, + -0.975995335999165880f, + 0.217604274638483670f, -0.976037079039039020f, 0.217417117873348300f, + -0.976078786192818850f, + 0.217229953114406790f, -0.976120457458971910f, 0.217042780368541080f, + -0.976162092835966110f, + 0.216855599642632570f, -0.976203692322270560f, 0.216668410943563790f, + -0.976245255916355800f, + 0.216481214278216900f, -0.976286783616693630f, 0.216294009653474370f, + -0.976328275421757260f, + 0.216106797076219600f, -0.976369731330021140f, 0.215919576553335460f, + -0.976411151339961040f, + 0.215732348091705940f, -0.976452535450054060f, 0.215545111698214660f, + -0.976493883658778540f, + 0.215357867379745550f, -0.976535195964614470f, 0.215170615143183500f, + -0.976576472366042610f, + 0.214983354995412820f, -0.976617712861545640f, 0.214796086943318920f, + -0.976658917449606980f, + 0.214608810993786920f, -0.976700086128711840f, 0.214421527153702190f, + -0.976741218897346550f, + 0.214234235429951100f, -0.976782315753998650f, 0.214046935829419330f, + -0.976823376697157240f, + 0.213859628358993830f, -0.976864401725312640f, 0.213672313025561140f, + -0.976905390836956490f, + 0.213484989836008080f, -0.976946344030581560f, 0.213297658797222430f, + -0.976987261304682390f, + 0.213110319916091360f, -0.977028142657754390f, 0.212922973199503260f, + -0.977068988088294450f, + 0.212735618654345870f, -0.977109797594800880f, 0.212548256287508120f, + -0.977150571175773200f, + 0.212360886105878580f, -0.977191308829712280f, 0.212173508116346080f, + -0.977232010555120320f, + 0.211986122325800410f, -0.977272676350500860f, 0.211798728741130820f, + -0.977313306214358750f, + 0.211611327369227610f, -0.977353900145199960f, 0.211423918216980810f, + -0.977394458141532250f, + 0.211236501291280710f, -0.977434980201864260f, 0.211049076599018500f, + -0.977475466324706050f, + 0.210861644147084830f, -0.977515916508569280f, 0.210674203942371490f, + -0.977556330751966460f, + 0.210486755991769890f, -0.977596709053411780f, 0.210299300302171750f, + -0.977637051411420770f, + 0.210111836880469720f, -0.977677357824509930f, 0.209924365733555860f, + -0.977717628291197570f, + 0.209736886868323370f, -0.977757862810002760f, 0.209549400291665110f, + -0.977798061379446360f, + 0.209361906010474190f, -0.977838223998050430f, 0.209174404031644700f, + -0.977878350664338150f, + 0.208986894362070070f, -0.977918441376834370f, 0.208799377008644980f, + -0.977958496134064830f, + 0.208611851978263460f, -0.977998514934557140f, 0.208424319277820650f, + -0.978038497776839600f, + 0.208236778914211470f, -0.978078444659442380f, 0.208049230894330940f, + -0.978118355580896660f, + 0.207861675225075150f, -0.978158230539735050f, 0.207674111913339540f, + -0.978198069534491400f, + 0.207486540966020700f, -0.978237872563701090f, 0.207298962390014880f, + -0.978277639625900420f, + 0.207111376192218560f, -0.978317370719627650f, 0.206923782379529210f, + -0.978357065843421640f, + 0.206736180958843660f, -0.978396724995823090f, 0.206548571937059940f, + -0.978436348175373730f, + 0.206360955321075680f, -0.978475935380616830f, 0.206173331117788770f, + -0.978515486610096910f, + 0.205985699334098050f, -0.978555001862359550f, 0.205798059976901760f, + -0.978594481135952270f, + 0.205610413053099320f, -0.978633924429423100f, 0.205422758569589780f, + -0.978673331741322210f, + 0.205235096533272380f, -0.978712703070200420f, 0.205047426951047380f, + -0.978752038414610340f, + 0.204859749829814420f, -0.978791337773105670f, 0.204672065176474290f, + -0.978830601144241470f, + 0.204484372997927180f, -0.978869828526574120f, 0.204296673301074430f, + -0.978909019918661310f, + 0.204108966092817010f, -0.978948175319062200f, 0.203921251380056150f, + -0.978987294726337050f, + 0.203733529169694010f, -0.979026378139047580f, 0.203545799468632190f, + -0.979065425555756930f, + 0.203358062283773370f, -0.979104436975029250f, 0.203170317622019920f, + -0.979143412395430230f, + 0.202982565490274460f, -0.979182351815526930f, 0.202794805895440550f, + -0.979221255233887700f, + 0.202607038844421110f, -0.979260122649082020f, 0.202419264344120220f, + -0.979298954059681040f, + 0.202231482401441620f, -0.979337749464256780f, 0.202043693023289280f, + -0.979376508861383170f, + 0.201855896216568160f, -0.979415232249634780f, 0.201668091988182500f, + -0.979453919627588210f, + 0.201480280345037820f, -0.979492570993820700f, 0.201292461294039190f, + -0.979531186346911390f, + 0.201104634842091960f, -0.979569765685440520f, 0.200916800996102370f, + -0.979608309007989450f, + 0.200728959762976140f, -0.979646816313141210f, 0.200541111149620090f, + -0.979685287599479930f, + 0.200353255162940420f, -0.979723722865591170f, 0.200165391809844500f, + -0.979762122110061640f, + 0.199977521097239290f, -0.979800485331479680f, 0.199789643032032120f, + -0.979838812528434740f, + 0.199601757621131050f, -0.979877103699517640f, 0.199413864871443750f, + -0.979915358843320480f, + 0.199225964789878890f, -0.979953577958436740f, 0.199038057383344820f, + -0.979991761043461200f, + 0.198850142658750120f, -0.980029908096989980f, 0.198662220623004320f, + -0.980068019117620650f, + 0.198474291283016360f, -0.980106094103951770f, 0.198286354645696270f, + -0.980144133054583590f, + 0.198098410717953730f, -0.980182135968117320f, 0.197910459506698720f, + -0.980220102843155970f, + 0.197722501018842030f, -0.980258033678303550f, 0.197534535261294000f, + -0.980295928472165290f, + 0.197346562240966000f, -0.980333787223347960f, 0.197158581964769040f, + -0.980371609930459690f, + 0.196970594439614370f, -0.980409396592109910f, 0.196782599672414240f, + -0.980447147206909060f, + 0.196594597670080220f, -0.980484861773469380f, 0.196406588439525050f, + -0.980522540290404090f, + 0.196218571987660850f, -0.980560182756327950f, 0.196030548321400880f, + -0.980597789169856850f, + 0.195842517447657990f, -0.980635359529608120f, 0.195654479373345370f, + -0.980672893834200530f, + 0.195466434105377090f, -0.980710392082253970f, 0.195278381650666520f, + -0.980747854272389750f, + 0.195090322016128330f, -0.980785280403230430f, 0.194902255208676660f, + -0.980822670473399990f, + 0.194714181235225990f, -0.980860024481523870f, 0.194526100102691720f, + -0.980897342426228390f, + 0.194338011817988600f, -0.980934624306141640f, 0.194149916388032530f, + -0.980971870119892840f, + 0.193961813819739010f, -0.981009079866112630f, 0.193773704120023840f, + -0.981046253543432780f, + 0.193585587295803750f, -0.981083391150486590f, 0.193397463353994740f, + -0.981120492685908730f, + 0.193209332301514080f, -0.981157558148334830f, 0.193021194145278320f, + -0.981194587536402320f, + 0.192833048892205290f, -0.981231580848749730f, 0.192644896549212240f, + -0.981268538084016710f, + 0.192456737123216840f, -0.981305459240844670f, 0.192268570621137590f, + -0.981342344317875930f, + 0.192080397049892380f, -0.981379193313754560f, 0.191892216416400310f, + -0.981416006227125550f, + 0.191704028727579940f, -0.981452783056635520f, 0.191515833990350240f, + -0.981489523800932130f, + 0.191327632211630990f, -0.981526228458664660f, 0.191139423398341420f, + -0.981562897028483650f, + 0.190951207557401860f, -0.981599529509040720f, 0.190762984695732250f, + -0.981636125898989080f, + 0.190574754820252800f, -0.981672686196983110f, 0.190386517937884580f, + -0.981709210401678800f, + 0.190198274055548120f, -0.981745698511732990f, 0.190010023180165050f, + -0.981782150525804310f, + 0.189821765318656580f, -0.981818566442552500f, 0.189633500477944220f, + -0.981854946260638630f, + 0.189445228664950340f, -0.981891289978724990f, 0.189256949886596720f, + -0.981927597595475540f, + 0.189068664149806280f, -0.981963869109555240f, 0.188880371461501330f, + -0.982000104519630490f, + 0.188692071828605260f, -0.982036303824369020f, 0.188503765258041080f, + -0.982072467022439890f, + 0.188315451756732120f, -0.982108594112513610f, 0.188127131331602530f, + -0.982144685093261580f, + 0.187938803989575850f, -0.982180739963357200f, 0.187750469737576840f, + -0.982216758721474510f, + 0.187562128582529740f, -0.982252741366289370f, 0.187373780531359110f, + -0.982288687896478830f, + 0.187185425590990440f, -0.982324598310721160f, 0.186997063768348510f, + -0.982360472607696210f, + 0.186808695070359330f, -0.982396310786084690f, 0.186620319503948420f, + -0.982432112844569110f, + 0.186431937076041640f, -0.982467878781833170f, 0.186243547793565670f, + -0.982503608596561720f, + 0.186055151663446630f, -0.982539302287441240f, 0.185866748692611720f, + -0.982574959853159240f, + 0.185678338887987790f, -0.982610581292404750f, 0.185489922256501900f, + -0.982646166603868050f, + 0.185301498805082040f, -0.982681715786240860f, 0.185113068540655510f, + -0.982717228838215990f, + 0.184924631470150870f, -0.982752705758487830f, 0.184736187600495930f, + -0.982788146545751970f, + 0.184547736938619640f, -0.982823551198705240f, 0.184359279491450640f, + -0.982858919716046110f, + 0.184170815265917720f, -0.982894252096474070f, 0.183982344268950600f, + -0.982929548338690060f, + 0.183793866507478390f, -0.982964808441396440f, 0.183605381988431350f, + -0.983000032403296590f, + 0.183416890718739230f, -0.983035220223095640f, 0.183228392705332140f, + -0.983070371899499640f, + 0.183039887955141060f, -0.983105487431216290f, 0.182851376475096310f, + -0.983140566816954500f, + 0.182662858272129360f, -0.983175610055424420f, 0.182474333353171260f, + -0.983210617145337640f, + 0.182285801725153320f, -0.983245588085407070f, 0.182097263395007760f, + -0.983280522874346970f, + 0.181908718369666160f, -0.983315421510872810f, 0.181720166656061170f, + -0.983350283993701500f, + 0.181531608261125130f, -0.983385110321551180f, 0.181343043191790590f, + -0.983419900493141540f, + 0.181154471454990920f, -0.983454654507193270f, 0.180965893057658980f, + -0.983489372362428730f, + 0.180777308006728670f, -0.983524054057571260f, 0.180588716309133280f, + -0.983558699591345900f, + 0.180400117971807270f, -0.983593308962478650f, 0.180211513001684590f, + -0.983627882169697210f, + 0.180022901405699510f, -0.983662419211730250f, 0.179834283190787180f, + -0.983696920087308020f, + 0.179645658363882100f, -0.983731384795162090f, 0.179457026931919950f, + -0.983765813334025240f, + 0.179268388901835880f, -0.983800205702631490f, 0.179079744280565390f, + -0.983834561899716630f, + 0.178891093075044830f, -0.983868881924017220f, 0.178702435292209940f, + -0.983903165774271500f, + 0.178513770938997590f, -0.983937413449218920f, 0.178325100022344140f, + -0.983971624947600270f, + 0.178136422549186320f, -0.984005800268157870f, 0.177947738526461670f, + -0.984039939409634970f, + 0.177759047961107140f, -0.984074042370776450f, 0.177570350860060790f, + -0.984108109150328540f, + 0.177381647230260200f, -0.984142139747038570f, 0.177192937078643310f, + -0.984176134159655320f, + 0.177004220412148860f, -0.984210092386929030f, 0.176815497237715000f, + -0.984244014427611110f, + 0.176626767562280960f, -0.984277900280454370f, 0.176438031392785350f, + -0.984311749944212780f, + 0.176249288736167940f, -0.984345563417641900f, 0.176060539599367960f, + -0.984379340699498510f, + 0.175871783989325040f, -0.984413081788540700f, 0.175683021912979580f, + -0.984446786683527920f, + 0.175494253377271400f, -0.984480455383220930f, 0.175305478389141370f, + -0.984514087886381840f, + 0.175116696955530060f, -0.984547684191773960f, 0.174927909083378160f, + -0.984581244298162180f, + 0.174739114779627310f, -0.984614768204312600f, 0.174550314051218490f, + -0.984648255908992630f, + 0.174361506905093830f, -0.984681707410970940f, 0.174172693348194960f, + -0.984715122709017620f, + 0.173983873387463850f, -0.984748501801904210f, 0.173795047029843270f, + -0.984781844688403350f, + 0.173606214282275410f, -0.984815151367289140f, 0.173417375151703520f, + -0.984848421837337010f, + 0.173228529645070490f, -0.984881656097323700f, 0.173039677769319390f, + -0.984914854146027200f, + 0.172850819531394200f, -0.984948015982227030f, 0.172661954938238270f, + -0.984981141604703960f, + 0.172473083996796030f, -0.985014231012239840f, 0.172284206714011350f, + -0.985047284203618200f, + 0.172095323096829040f, -0.985080301177623800f, 0.171906433152193700f, + -0.985113281933042590f, + 0.171717536887049970f, -0.985146226468662230f, 0.171528634308343500f, + -0.985179134783271020f, + 0.171339725423019260f, -0.985212006875659460f, 0.171150810238023340f, + -0.985244842744618540f, + 0.170961888760301360f, -0.985277642388941220f, 0.170772960996799230f, + -0.985310405807421570f, + 0.170584026954463700f, -0.985343132998854790f, 0.170395086640240920f, + -0.985375823962037710f, + 0.170206140061078120f, -0.985408478695768420f, 0.170017187223922090f, + -0.985441097198846210f, + 0.169828228135719880f, -0.985473679470071810f, 0.169639262803419400f, + -0.985506225508247290f, + 0.169450291233967930f, -0.985538735312176060f, 0.169261313434313890f, + -0.985571208880662740f, + 0.169072329411405180f, -0.985603646212513400f, 0.168883339172190010f, + -0.985636047306535420f, + 0.168694342723617440f, -0.985668412161537550f, 0.168505340072635900f, + -0.985700740776329850f, + 0.168316331226194910f, -0.985733033149723490f, 0.168127316191243350f, + -0.985765289280531310f, + 0.167938294974731230f, -0.985797509167567370f, 0.167749267583608030f, + -0.985829692809647050f, + 0.167560234024823590f, -0.985861840205586980f, 0.167371194305328540f, + -0.985893951354205210f, + 0.167182148432072880f, -0.985926026254321130f, 0.166993096412007770f, + -0.985958064904755460f, + 0.166804038252083870f, -0.985990067304330030f, 0.166614973959252090f, + -0.986022033451868560f, + 0.166425903540464220f, -0.986053963346195440f, 0.166236827002671390f, + -0.986085856986136820f, + 0.166047744352825850f, -0.986117714370520090f, 0.165858655597879430f, + -0.986149535498173860f, + 0.165669560744784140f, -0.986181320367928270f, 0.165480459800492890f, + -0.986213068978614490f, + 0.165291352771957970f, -0.986244781329065460f, 0.165102239666132720f, + -0.986276457418114980f, + 0.164913120489970090f, -0.986308097244598670f, 0.164723995250423190f, + -0.986339700807353000f, + 0.164534863954446110f, -0.986371268105216030f, 0.164345726608992190f, + -0.986402799137027220f, + 0.164156583221015890f, -0.986434293901627070f, 0.163967433797471110f, + -0.986465752397857940f, + 0.163778278345312690f, -0.986497174624562880f, 0.163589116871495160f, + -0.986528560580586690f, + 0.163399949382973230f, -0.986559910264775410f, 0.163210775886702460f, + -0.986591223675976400f, + 0.163021596389637810f, -0.986622500813038480f, 0.162832410898735260f, + -0.986653741674811350f, + 0.162643219420950450f, -0.986684946260146690f, 0.162454021963239190f, + -0.986716114567897100f, + 0.162264818532558110f, -0.986747246596916480f, 0.162075609135863330f, + -0.986778342346060430f, + 0.161886393780111910f, -0.986809401814185420f, 0.161697172472260540f, + -0.986840425000149680f, + 0.161507945219266150f, -0.986871411902812470f, 0.161318712028086540f, + -0.986902362521034470f, + 0.161129472905678780f, -0.986933276853677710f, 0.160940227859001140f, + -0.986964154899605650f, + 0.160750976895011390f, -0.986994996657682870f, 0.160561720020667510f, + -0.987025802126775600f, + 0.160372457242928400f, -0.987056571305750970f, 0.160183188568752240f, + -0.987087304193477900f, + 0.159993914005098350f, -0.987118000788826280f, 0.159804633558925380f, + -0.987148661090667570f, + 0.159615347237193090f, -0.987179285097874340f, 0.159426055046860750f, + -0.987209872809320820f, + 0.159236756994887850f, -0.987240424223882250f, 0.159047453088234840f, + -0.987270939340435420f, + 0.158858143333861390f, -0.987301418157858430f, 0.158668827738728370f, + -0.987331860675030430f, + 0.158479506309796100f, -0.987362266890832400f, 0.158290179054025180f, + -0.987392636804146240f, + 0.158100845978377090f, -0.987422970413855410f, 0.157911507089812640f, + -0.987453267718844560f, + 0.157722162395293690f, -0.987483528717999710f, 0.157532811901781670f, + -0.987513753410208420f, + 0.157343455616238280f, -0.987543941794359230f, 0.157154093545626010f, + -0.987574093869342360f, + 0.156964725696906750f, -0.987604209634049160f, 0.156775352077043430f, + -0.987634289087372160f, + 0.156585972692998590f, -0.987664332228205710f, 0.156396587551734940f, + -0.987694339055445130f, + 0.156207196660216040f, -0.987724309567986960f, 0.156017800025404830f, + -0.987754243764729530f, + 0.155828397654265320f, -0.987784141644572180f, 0.155638989553760850f, + -0.987814003206415550f, + 0.155449575730855880f, -0.987843828449161740f, 0.155260156192514380f, + -0.987873617371714200f, + 0.155070730945700510f, -0.987903369972977790f, 0.154881299997379400f, + -0.987933086251858380f, + 0.154691863354515400f, -0.987962766207263420f, 0.154502421024073990f, + -0.987992409838101880f, + 0.154312973013020240f, -0.988022017143283530f, 0.154123519328319360f, + -0.988051588121720110f, + 0.153934059976937460f, -0.988081122772324070f, 0.153744594965840000f, + -0.988110621094009820f, + 0.153555124301993500f, -0.988140083085692570f, 0.153365647992364020f, + -0.988169508746289060f, + 0.153176166043917870f, -0.988198898074717610f, 0.152986678463622160f, + -0.988228251069897420f, + 0.152797185258443410f, -0.988257567730749460f, 0.152607686435349140f, + -0.988286848056195710f, + 0.152418182001306500f, -0.988316092045159690f, 0.152228671963282770f, + -0.988345299696566150f, + 0.152039156328246160f, -0.988374471009341280f, 0.151849635103164180f, + -0.988403605982412390f, + 0.151660108295005400f, -0.988432704614708340f, 0.151470575910737760f, + -0.988461766905159300f, + 0.151281037957330250f, -0.988490792852696590f, 0.151091494441751430f, + -0.988519782456253270f, + 0.150901945370970040f, -0.988548735714763200f, 0.150712390751955720f, + -0.988577652627162020f, + 0.150522830591677370f, -0.988606533192386450f, 0.150333264897105050f, + -0.988635377409374790f, + 0.150143693675208330f, -0.988664185277066230f, 0.149954116932956990f, + -0.988692956794401940f, + 0.149764534677321620f, -0.988721691960323780f, 0.149574946915272210f, + -0.988750390773775360f, + 0.149385353653779810f, -0.988779053233701520f, 0.149195754899814960f, + -0.988807679339048340f, + 0.149006150660348470f, -0.988836269088763540f, 0.148816540942352030f, + -0.988864822481795640f, + 0.148626925752796540f, -0.988893339517095130f, 0.148437305098654050f, + -0.988921820193613190f, + 0.148247678986896200f, -0.988950264510302990f, 0.148058047424494740f, + -0.988978672466118480f, + 0.147868410418422360f, -0.989007044060015270f, 0.147678767975650970f, + -0.989035379290950310f, + 0.147489120103153680f, -0.989063678157881540f, 0.147299466807902820f, + -0.989091940659768800f, + 0.147109808096871850f, -0.989120166795572690f, 0.146920143977033760f, + -0.989148356564255590f, + 0.146730474455361750f, -0.989176509964781010f, 0.146540799538829870f, + -0.989204626996113780f, + 0.146351119234411440f, -0.989232707657220050f, 0.146161433549080950f, + -0.989260751947067640f, + 0.145971742489812370f, -0.989288759864625170f, 0.145782046063579860f, + -0.989316731408863000f, + 0.145592344277358450f, -0.989344666578752640f, 0.145402637138122540f, + -0.989372565373267010f, + 0.145212924652847520f, -0.989400427791380380f, 0.145023206828508360f, + -0.989428253832068230f, + 0.144833483672080240f, -0.989456043494307710f, 0.144643755190539150f, + -0.989483796777076760f, + 0.144454021390860440f, -0.989511513679355190f, 0.144264282280020530f, + -0.989539194200123930f, + 0.144074537864995330f, -0.989566838338365120f, 0.143884788152761010f, + -0.989594446093062460f, + 0.143695033150294580f, -0.989622017463200780f, 0.143505272864572290f, + -0.989649552447766530f, + 0.143315507302571590f, -0.989677051045747210f, 0.143125736471269140f, + -0.989704513256131850f, + 0.142935960377642700f, -0.989731939077910570f, 0.142746179028669620f, + -0.989759328510075200f, + 0.142556392431327340f, -0.989786681551618640f, 0.142366600592594260f, + -0.989813998201535260f, + 0.142176803519448000f, -0.989841278458820530f, 0.141987001218867340f, + -0.989868522322471580f, + 0.141797193697830530f, -0.989895729791486660f, 0.141607380963316020f, + -0.989922900864865450f, + 0.141417563022303130f, -0.989950035541608990f, 0.141227739881770480f, + -0.989977133820719610f, + 0.141037911548697770f, -0.990004195701200910f, 0.140848078030064220f, + -0.990031221182058000f, + 0.140658239332849240f, -0.990058210262297120f, 0.140468395464033110f, + -0.990085162940925970f, + 0.140278546430595420f, -0.990112079216953770f, 0.140088692239516780f, + -0.990138959089390650f, + 0.139898832897777380f, -0.990165802557248400f, 0.139708968412357580f, + -0.990192609619540030f, + 0.139519098790238600f, -0.990219380275280000f, 0.139329224038400980f, + -0.990246114523483990f, + 0.139139344163826280f, -0.990272812363169110f, 0.138949459173495440f, + -0.990299473793353590f, + 0.138759569074390380f, -0.990326098813057330f, 0.138569673873492640f, + -0.990352687421301340f, + 0.138379773577783890f, -0.990379239617108160f, 0.138189868194246640f, + -0.990405755399501260f, + 0.137999957729862760f, -0.990432234767505970f, 0.137810042191615130f, + -0.990458677720148620f, + 0.137620121586486180f, -0.990485084256456980f, 0.137430195921458550f, + -0.990511454375460290f, + 0.137240265203515700f, -0.990537788076188750f, 0.137050329439640380f, + -0.990564085357674370f, + 0.136860388636816430f, -0.990590346218950150f, 0.136670442802027230f, + -0.990616570659050620f, + 0.136480491942256310f, -0.990642758677011570f, 0.136290536064488070f, + -0.990668910271869980f, + 0.136100575175706200f, -0.990695025442664630f, 0.135910609282895440f, + -0.990721104188435180f, + 0.135720638393040080f, -0.990747146508222710f, 0.135530662513124620f, + -0.990773152401069780f, + 0.135340681650134330f, -0.990799121866020370f, 0.135150695811053850f, + -0.990825054902119470f, + 0.134960705002868830f, -0.990850951508413620f, 0.134770709232564290f, + -0.990876811683950810f, + 0.134580708507126220f, -0.990902635427780010f, 0.134390702833540240f, + -0.990928422738951990f, + 0.134200692218792020f, -0.990954173616518500f, 0.134010676669868210f, + -0.990979888059532740f, + 0.133820656193754690f, -0.991005566067049370f, 0.133630630797438390f, + -0.991031207638124130f, + 0.133440600487905820f, -0.991056812771814340f, 0.133250565272143570f, + -0.991082381467178640f, + 0.133060525157139180f, -0.991107913723276780f, 0.132870480149879400f, + -0.991133409539170170f, + 0.132680430257352130f, -0.991158868913921350f, 0.132490375486544710f, + -0.991184291846594180f, + 0.132300315844444680f, -0.991209678336254060f, 0.132110251338040470f, + -0.991235028381967420f, + 0.131920181974319760f, -0.991260341982802440f, 0.131730107760271280f, + -0.991285619137828200f, + 0.131540028702883280f, -0.991310859846115440f, 0.131349944809144220f, + -0.991336064106736140f, + 0.131159856086043410f, -0.991361231918763460f, 0.130969762540569380f, + -0.991386363281272280f, + 0.130779664179711790f, -0.991411458193338540f, 0.130589561010459600f, + -0.991436516654039420f, + 0.130399453039802740f, -0.991461538662453790f, 0.130209340274730770f, + -0.991486524217661480f, + 0.130019222722233350f, -0.991511473318743900f, 0.129829100389301010f, + -0.991536385964783880f, + 0.129638973282923540f, -0.991561262154865290f, 0.129448841410091830f, + -0.991586101888073500f, + 0.129258704777796270f, -0.991610905163495370f, 0.129068563393027410f, + -0.991635671980218740f, + 0.128878417262776660f, -0.991660402337333210f, 0.128688266394034690f, + -0.991685096233929530f, + 0.128498110793793220f, -0.991709753669099530f, 0.128307950469043590f, + -0.991734374641936810f, + 0.128117785426777150f, -0.991758959151536110f, 0.127927615673986190f, + -0.991783507196993490f, + 0.127737441217662280f, -0.991808018777406430f, 0.127547262064798050f, + -0.991832493891873780f, + 0.127357078222385570f, -0.991856932539495360f, 0.127166889697417180f, + -0.991881334719373010f, + 0.126976696496885980f, -0.991905700430609330f, 0.126786498627784430f, + -0.991930029672308480f, + 0.126596296097105960f, -0.991954322443575950f, 0.126406088911843320f, + -0.991978578743518580f, + 0.126215877078990400f, -0.992002798571244520f, 0.126025660605540460f, + -0.992026981925863360f, + 0.125835439498487020f, -0.992051128806485720f, 0.125645213764824380f, + -0.992075239212224070f, + 0.125454983411546210f, -0.992099313142191800f, 0.125264748445647110f, + -0.992123350595503720f, + 0.125074508874121300f, -0.992147351571276090f, 0.124884264703963150f, + -0.992171316068626520f, + 0.124694015942167770f, -0.992195244086673920f, 0.124503762595729650f, + -0.992219135624538450f, + 0.124313504671644300f, -0.992242990681341700f, 0.124123242176906760f, + -0.992266809256206580f, + 0.123932975118512200f, -0.992290591348257370f, 0.123742703503456630f, + -0.992314336956619640f, + 0.123552427338735370f, -0.992338046080420420f, 0.123362146631344750f, + -0.992361718718787870f, + 0.123171861388280650f, -0.992385354870851670f, 0.122981571616539080f, + -0.992408954535742850f, + 0.122791277323116900f, -0.992432517712593550f, 0.122600978515010240f, + -0.992456044400537700f, + 0.122410675199216280f, -0.992479534598709970f, 0.122220367382731500f, + -0.992502988306246950f, + 0.122030055072553410f, -0.992526405522286100f, 0.121839738275679020f, + -0.992549786245966570f, + 0.121649416999105540f, -0.992573130476428810f, 0.121459091249830950f, + -0.992596438212814290f, + 0.121268761034852550f, -0.992619709454266140f, 0.121078426361168710f, + -0.992642944199928820f, + 0.120888087235777220f, -0.992666142448948020f, 0.120697743665676120f, + -0.992689304200470750f, + 0.120507395657864240f, -0.992712429453645460f, 0.120317043219339670f, + -0.992735518207621850f, + 0.120126686357101580f, -0.992758570461551140f, 0.119936325078148620f, + -0.992781586214585570f, + 0.119745959389479630f, -0.992804565465879140f, 0.119555589298094230f, + -0.992827508214586760f, + 0.119365214810991350f, -0.992850414459865100f, 0.119174835935170960f, + -0.992873284200871730f, + 0.118984452677632520f, -0.992896117436765980f, 0.118794065045375670f, + -0.992918914166708300f, + 0.118603673045400840f, -0.992941674389860470f, 0.118413276684707770f, + -0.992964398105385610f, + 0.118222875970297250f, -0.992987085312448390f, 0.118032470909169300f, + -0.993009736010214580f, + 0.117842061508325020f, -0.993032350197851410f, 0.117651647774765000f, + -0.993054927874527320f, + 0.117461229715489990f, -0.993077469039412300f, 0.117270807337501560f, + -0.993099973691677570f, + 0.117080380647800550f, -0.993122441830495580f, 0.116889949653388850f, + -0.993144873455040430f, + 0.116699514361267840f, -0.993167268564487230f, 0.116509074778439050f, + -0.993189627158012620f, + 0.116318630911904880f, -0.993211949234794500f, 0.116128182768666920f, + -0.993234234794012290f, + 0.115937730355727850f, -0.993256483834846440f, 0.115747273680089870f, + -0.993278696356479030f, + 0.115556812748755290f, -0.993300872358093280f, 0.115366347568727250f, + -0.993323011838873950f, + 0.115175878147008180f, -0.993345114798006910f, 0.114985404490601530f, + -0.993367181234679600f, + 0.114794926606510250f, -0.993389211148080650f, 0.114604444501737460f, + -0.993411204537400060f, + 0.114413958183287050f, -0.993433161401829360f, 0.114223467658162260f, + -0.993455081740560960f, + 0.114032972933367300f, -0.993476965552789190f, 0.113842474015905660f, + -0.993498812837709360f, + 0.113651970912781920f, -0.993520623594518090f, 0.113461463631000080f, + -0.993542397822413600f, + 0.113270952177564360f, -0.993564135520595300f, 0.113080436559479720f, + -0.993585836688263950f, + 0.112889916783750470f, -0.993607501324621610f, 0.112699392857381910f, + -0.993629129428871720f, + 0.112508864787378830f, -0.993650721000219120f, 0.112318332580746190f, + -0.993672276037870010f, + 0.112127796244489750f, -0.993693794541031680f, 0.111937255785614560f, + -0.993715276508913230f, + 0.111746711211126660f, -0.993736721940724600f, 0.111556162528031630f, + -0.993758130835677430f, + 0.111365609743335190f, -0.993779503192984580f, 0.111175052864043830f, + -0.993800839011860120f, + 0.110984491897163380f, -0.993822138291519660f, 0.110793926849700630f, + -0.993843401031180180f, + 0.110603357728661910f, -0.993864627230059750f, 0.110412784541053660f, + -0.993885816887378090f, + 0.110222207293883180f, -0.993906970002356060f, 0.110031625994157000f, + -0.993928086574215830f, + 0.109841040648882680f, -0.993949166602181130f, 0.109650451265067080f, + -0.993970210085476920f, + 0.109459857849718030f, -0.993991217023329380f, 0.109269260409842920f, + -0.994012187414966220f, + 0.109078658952449240f, -0.994033121259616400f, 0.108888053484545310f, + -0.994054018556510210f, + 0.108697444013138670f, -0.994074879304879370f, 0.108506830545237980f, + -0.994095703503956930f, + 0.108316213087851300f, -0.994116491152977070f, 0.108125591647986880f, + -0.994137242251175720f, + 0.107934966232653760f, -0.994157956797789730f, 0.107744336848860260f, + -0.994178634792057590f, + 0.107553703503615710f, -0.994199276233218910f, 0.107363066203928920f, + -0.994219881120514850f, + 0.107172424956808870f, -0.994240449453187900f, 0.106981779769265340f, + -0.994260981230481790f, + 0.106791130648307380f, -0.994281476451641550f, 0.106600477600945030f, + -0.994301935115913580f, + 0.106409820634187840f, -0.994322357222545810f, 0.106219159755045520f, + -0.994342742770787270f, + 0.106028494970528530f, -0.994363091759888570f, 0.105837826287646670f, + -0.994383404189101430f, + 0.105647153713410700f, -0.994403680057679100f, 0.105456477254830660f, + -0.994423919364875950f, + 0.105265796918917650f, -0.994444122109948040f, 0.105075112712682180f, + -0.994464288292152390f, + 0.104884424643134970f, -0.994484417910747600f, 0.104693732717287500f, + -0.994504510964993590f, + 0.104503036942150550f, -0.994524567454151740f, 0.104312337324735870f, + -0.994544587377484300f, + 0.104121633872054730f, -0.994564570734255420f, 0.103930926591118540f, + -0.994584517523730340f, + 0.103740215488939480f, -0.994604427745175660f, 0.103549500572529040f, + -0.994624301397859400f, + 0.103358781848899700f, -0.994644138481050710f, 0.103168059325063390f, + -0.994663938994020280f, + 0.102977333008032250f, -0.994683702936040250f, 0.102786602904819150f, + -0.994703430306383860f, + 0.102595869022436280f, -0.994723121104325700f, 0.102405131367896790f, + -0.994742775329142010f, + 0.102214389948213370f, -0.994762392980109930f, 0.102023644770398800f, + -0.994781974056508260f, + 0.101832895841466670f, -0.994801518557617110f, 0.101642143168429830f, + -0.994821026482717860f, + 0.101451386758302160f, -0.994840497831093180f, 0.101260626618096800f, + -0.994859932602027320f, + 0.101069862754827880f, -0.994879330794805620f, 0.100879095175509010f, + -0.994898692408714870f, + 0.100688323887153970f, -0.994918017443043200f, 0.100497548896777310f, + -0.994937305897080070f, + 0.100306770211392820f, -0.994956557770116380f, 0.100115987838015370f, + -0.994975773061444140f, + 0.099925201783659226f, -0.994994951770357020f, 0.099734412055338839f, + -0.995014093896149700f, + 0.099543618660069444f, -0.995033199438118630f, 0.099352821604865513f, + -0.995052268395561160f, + 0.099162020896742573f, -0.995071300767776170f, 0.098971216542715582f, + -0.995090296554063890f, + 0.098780408549799664f, -0.995109255753726110f, 0.098589596925010708f, + -0.995128178366065490f, + 0.098398781675363881f, -0.995147064390386470f, 0.098207962807875346f, + -0.995165913825994620f, + 0.098017140329560770f, -0.995184726672196820f, 0.097826314247435903f, + -0.995203502928301510f, + 0.097635484568517339f, -0.995222242593618240f, 0.097444651299820870f, + -0.995240945667458130f, + 0.097253814448363354f, -0.995259612149133390f, 0.097062974021160875f, + -0.995278242037957670f, + 0.096872130025230527f, -0.995296835333246090f, 0.096681282467588864f, + -0.995315392034315070f, + 0.096490431355252607f, -0.995333912140482280f, 0.096299576695239225f, + -0.995352395651066810f, + 0.096108718494565468f, -0.995370842565388990f, 0.095917856760249096f, + -0.995389252882770690f, + 0.095726991499307315f, -0.995407626602534900f, 0.095536122718757485f, + -0.995425963724006160f, + 0.095345250425617742f, -0.995444264246510340f, 0.095154374626905472f, + -0.995462528169374420f, + 0.094963495329639061f, -0.995480755491926940f, 0.094772612540836410f, + -0.995498946213497770f, + 0.094581726267515473f, -0.995517100333418110f, 0.094390836516695067f, + -0.995535217851020390f, + 0.094199943295393190f, -0.995553298765638470f, 0.094009046610628907f, + -0.995571343076607770f, + 0.093818146469420494f, -0.995589350783264600f, 0.093627242878787237f, + -0.995607321884947050f, + 0.093436335845747912f, -0.995625256380994310f, 0.093245425377321389f, + -0.995643154270746900f, + 0.093054511480527333f, -0.995661015553546910f, 0.092863594162384697f, + -0.995678840228737540f, + 0.092672673429913366f, -0.995696628295663520f, 0.092481749290132753f, + -0.995714379753670610f, + 0.092290821750062355f, -0.995732094602106430f, 0.092099890816722485f, + -0.995749772840319400f, + 0.091908956497132696f, -0.995767414467659820f, 0.091718018798313525f, + -0.995785019483478750f, + 0.091527077727284981f, -0.995802587887129160f, 0.091336133291067212f, + -0.995820119677964910f, + 0.091145185496681130f, -0.995837614855341610f, 0.090954234351146898f, + -0.995855073418615790f, + 0.090763279861485704f, -0.995872495367145730f, 0.090572322034718156f, + -0.995889880700290720f, + 0.090381360877865011f, -0.995907229417411720f, 0.090190396397947820f, + -0.995924541517870690f, + 0.089999428601987341f, -0.995941817001031350f, 0.089808457497005362f, + -0.995959055866258320f, + 0.089617483090022917f, -0.995976258112917790f, 0.089426505388062016f, + -0.995993423740377360f, + 0.089235524398144139f, -0.996010552748005870f, 0.089044540127290905f, + -0.996027645135173610f, + 0.088853552582524684f, -0.996044700901251970f, 0.088662561770867121f, + -0.996061720045614000f, + 0.088471567699340822f, -0.996078702567633980f, 0.088280570374967879f, + -0.996095648466687300f, + 0.088089569804770507f, -0.996112557742151130f, 0.087898565995771685f, + -0.996129430393403740f, + 0.087707558954993645f, -0.996146266419824620f, 0.087516548689459586f, + -0.996163065820794950f, + 0.087325535206192226f, -0.996179828595696870f, 0.087134518512214321f, + -0.996196554743914220f, + 0.086943498614549489f, -0.996213244264832040f, 0.086752475520220515f, + -0.996229897157836500f, + 0.086561449236251239f, -0.996246513422315520f, 0.086370419769664919f, + -0.996263093057658030f, + 0.086179387127484922f, -0.996279636063254650f, 0.085988351316735448f, + -0.996296142438496850f, + 0.085797312344439880f, -0.996312612182778000f, 0.085606270217622613f, + -0.996329045295492380f, + 0.085415224943307277f, -0.996345441776035900f, 0.085224176528518519f, + -0.996361801623805720f, + 0.085033124980280414f, -0.996378124838200210f, 0.084842070305617148f, + -0.996394411418619290f, + 0.084651012511553700f, -0.996410661364464100f, 0.084459951605114297f, + -0.996426874675137240f, + 0.084268887593324127f, -0.996443051350042630f, 0.084077820483207846f, + -0.996459191388585410f, + 0.083886750281790226f, -0.996475294790172160f, 0.083695676996096827f, + -0.996491361554210920f, + 0.083504600633152404f, -0.996507391680110820f, 0.083313521199982740f, + -0.996523385167282450f, + 0.083122438703613077f, -0.996539342015137940f, 0.082931353151068726f, + -0.996555262223090540f, + 0.082740264549375803f, -0.996571145790554840f, 0.082549172905559659f, + -0.996586992716946950f, + 0.082358078226646619f, -0.996602803001684130f, 0.082166980519662466f, + -0.996618576644185070f, + 0.081975879791633108f, -0.996634313643869900f, 0.081784776049585201f, + -0.996650014000160070f, + 0.081593669300544638f, -0.996665677712478160f, 0.081402559551538328f, + -0.996681304780248300f, + 0.081211446809592386f, -0.996696895202896060f, 0.081020331081733912f, + -0.996712448979848010f, + 0.080829212374989468f, -0.996727966110532490f, 0.080638090696385709f, + -0.996743446594378860f, + 0.080446966052950097f, -0.996758890430818000f, 0.080255838451709291f, + -0.996774297619282050f, + 0.080064707899690932f, -0.996789668159204560f, 0.079873574403922148f, + -0.996805002050020320f, + 0.079682437971430126f, -0.996820299291165670f, 0.079491298609242866f, + -0.996835559882078170f, + 0.079300156324387569f, -0.996850783822196610f, 0.079109011123892431f, + -0.996865971110961310f, + 0.078917863014785095f, -0.996881121747813850f, 0.078726712004093313f, + -0.996896235732197210f, + 0.078535558098845590f, -0.996911313063555740f, 0.078344401306069678f, + -0.996926353741335090f, + 0.078153241632794315f, -0.996941357764982160f, 0.077962079086047645f, + -0.996956325133945280f, + 0.077770913672857989f, -0.996971255847674320f, 0.077579745400254363f, + -0.996986149905620180f, + 0.077388574275265049f, -0.997001007307235290f, 0.077197400304919297f, + -0.997015828051973310f, + 0.077006223496245585f, -0.997030612139289450f, 0.076815043856273399f, + -0.997045359568640040f, + 0.076623861392031617f, -0.997060070339482960f, 0.076432676110549283f, + -0.997074744451277310f, + 0.076241488018856149f, -0.997089381903483400f, 0.076050297123981231f, + -0.997103982695563330f, + 0.075859103432954503f, -0.997118546826979980f, 0.075667906952805383f, + -0.997133074297198110f, + 0.075476707690563416f, -0.997147565105683480f, 0.075285505653258880f, + -0.997162019251903290f, + 0.075094300847921291f, -0.997176436735326190f, 0.074903093281581137f, + -0.997190817555421940f, + 0.074711882961268378f, -0.997205161711661850f, 0.074520669894013014f, + -0.997219469203518670f, + 0.074329454086845867f, -0.997233740030466160f, 0.074138235546796952f, + -0.997247974191979860f, + 0.073947014280897269f, -0.997262171687536170f, 0.073755790296177265f, + -0.997276332516613180f, + 0.073564563599667454f, -0.997290456678690210f, 0.073373334198399157f, + -0.997304544173247990f, + 0.073182102099402888f, -0.997318594999768600f, 0.072990867309710133f, + -0.997332609157735470f, + 0.072799629836351618f, -0.997346586646633230f, 0.072608389686359048f, + -0.997360527465947940f, + 0.072417146866763538f, -0.997374431615167030f, 0.072225901384596336f, + -0.997388299093779460f, + 0.072034653246889416f, -0.997402129901275300f, 0.071843402460674000f, + -0.997415924037145960f, + 0.071652149032982254f, -0.997429681500884180f, 0.071460892970845832f, + -0.997443402291984360f, + 0.071269634281296415f, -0.997457086409941910f, 0.071078372971366502f, + -0.997470733854253670f, + 0.070887109048087787f, -0.997484344624417930f, 0.070695842518492924f, + -0.997497918719934210f, + 0.070504573389614009f, -0.997511456140303450f, 0.070313301668483263f, + -0.997524956885027960f, + 0.070122027362133646f, -0.997538420953611230f, 0.069930750477597295f, + -0.997551848345558430f, + 0.069739471021907376f, -0.997565239060375750f, 0.069548189002096472f, + -0.997578593097570800f, + 0.069356904425197236f, -0.997591910456652630f, 0.069165617298243109f, + -0.997605191137131640f, + 0.068974327628266732f, -0.997618435138519550f, 0.068783035422301728f, + -0.997631642460329320f, + 0.068591740687380900f, -0.997644813102075420f, 0.068400443430538069f, + -0.997657947063273710f, + 0.068209143658806454f, -0.997671044343441000f, 0.068017841379219388f, + -0.997684104942096030f, + 0.067826536598810966f, -0.997697128858758500f, 0.067635229324614451f, + -0.997710116092949570f, + 0.067443919563664106f, -0.997723066644191640f, 0.067252607322993652f, + -0.997735980512008620f, + 0.067061292609636836f, -0.997748857695925690f, 0.066869975430628226f, + -0.997761698195469560f, + 0.066678655793001543f, -0.997774502010167820f, 0.066487333703791507f, + -0.997787269139549960f, + 0.066296009170032283f, -0.997799999583146470f, 0.066104682198758091f, + -0.997812693340489280f, + 0.065913352797003930f, -0.997825350411111640f, 0.065722020971803977f, + -0.997837970794548280f, + 0.065530686730193397f, -0.997850554490335110f, 0.065339350079206798f, + -0.997863101498009500f, + 0.065148011025878860f, -0.997875611817110150f, 0.064956669577245010f, + -0.997888085447177110f, + 0.064765325740339871f, -0.997900522387751620f, 0.064573979522199065f, + -0.997912922638376610f, + 0.064382630929857410f, -0.997925286198596000f, 0.064191279970350679f, + -0.997937613067955250f, + 0.063999926650714078f, -0.997949903246001190f, 0.063808570977982898f, + -0.997962156732281950f, + 0.063617212959193190f, -0.997974373526346990f, 0.063425852601380200f, + -0.997986553627747020f, + 0.063234489911580136f, -0.997998697036034390f, 0.063043124896828631f, + -0.998010803750762450f, + 0.062851757564161420f, -0.998022873771486240f, 0.062660387920614985f, + -0.998034907097761770f, + 0.062469015973224969f, -0.998046903729146840f, 0.062277641729028041f, + -0.998058863665200250f, + 0.062086265195060247f, -0.998070786905482340f, 0.061894886378357744f, + -0.998082673449554590f, + 0.061703505285957416f, -0.998094523296980010f, 0.061512121924895365f, + -0.998106336447323050f, + 0.061320736302208648f, -0.998118112900149180f, 0.061129348424933755f, + -0.998129852655025520f, + 0.060937958300107238f, -0.998141555711520520f, 0.060746565934766412f, + -0.998153222069203650f, + 0.060555171335947781f, -0.998164851727646240f, 0.060363774510688827f, + -0.998176444686420530f, + 0.060172375466026218f, -0.998188000945100300f, 0.059980974208997596f, + -0.998199520503260660f, + 0.059789570746640007f, -0.998211003360478190f, 0.059598165085990598f, + -0.998222449516330550f, + 0.059406757234087247f, -0.998233858970396850f, 0.059215347197967026f, + -0.998245231722257880f, + 0.059023934984667986f, -0.998256567771495180f, 0.058832520601227581f, + -0.998267867117692110f, + 0.058641104054683348f, -0.998279129760433200f, 0.058449685352073573f, + -0.998290355699304350f, + 0.058258264500435732f, -0.998301544933892890f, 0.058066841506808263f, + -0.998312697463787260f, + 0.057875416378229017f, -0.998323813288577560f, 0.057683989121735932f, + -0.998334892407855000f, + 0.057492559744367684f, -0.998345934821212370f, 0.057301128253162144f, + -0.998356940528243420f, + 0.057109694655158132f, -0.998367909528543820f, 0.056918258957393907f, + -0.998378841821709990f, + 0.056726821166907783f, -0.998389737407340160f, 0.056535381290738825f, + -0.998400596285033640f, + 0.056343939335925283f, -0.998411418454391300f, 0.056152495309506383f, + -0.998422203915015020f, + 0.055961049218520520f, -0.998432952666508440f, 0.055769601070007072f, + -0.998443664708476340f, + 0.055578150871004817f, -0.998454340040524800f, 0.055386698628552604f, + -0.998464978662261250f, + 0.055195244349690031f, -0.998475580573294770f, 0.055003788041455885f, + -0.998486145773235360f, + 0.054812329710889909f, -0.998496674261694640f, 0.054620869365031251f, + -0.998507166038285490f, + 0.054429407010919147f, -0.998517621102622210f, 0.054237942655593556f, + -0.998528039454320230f, + 0.054046476306093640f, -0.998538421092996730f, 0.053855007969459509f, + -0.998548766018269920f, + 0.053663537652730679f, -0.998559074229759310f, 0.053472065362946755f, + -0.998569345727086110f, + 0.053280591107148056f, -0.998579580509872500f, 0.053089114892374119f, + -0.998589778577742230f, + 0.052897636725665401f, -0.998599939930320370f, 0.052706156614061798f, + -0.998610064567233340f, + 0.052514674564603257f, -0.998620152488108870f, 0.052323190584330471f, + -0.998630203692576050f, + 0.052131704680283317f, -0.998640218180265270f, 0.051940216859502626f, + -0.998650195950808280f, + 0.051748727129028414f, -0.998660137003838490f, 0.051557235495901653f, + -0.998670041338990070f, + 0.051365741967162731f, -0.998679908955899090f, 0.051174246549852087f, + -0.998689739854202620f, + 0.050982749251010900f, -0.998699534033539280f, 0.050791250077679546f, + -0.998709291493549030f, + 0.050599749036899337f, -0.998719012233872940f, 0.050408246135710995f, + -0.998728696254153720f, + 0.050216741381155325f, -0.998738343554035230f, 0.050025234780273840f, + -0.998747954133162860f, + 0.049833726340107257f, -0.998757527991183340f, 0.049642216067697226f, + -0.998767065127744380f, + 0.049450703970084824f, -0.998776565542495610f, 0.049259190054311168f, + -0.998786029235087640f, + 0.049067674327418126f, -0.998795456205172410f, 0.048876156796446746f, + -0.998804846452403420f, + 0.048684637468439020f, -0.998814199976435390f, 0.048493116350436342f, + -0.998823516776924380f, + 0.048301593449480172f, -0.998832796853527990f, 0.048110068772612716f, + -0.998842040205904840f, + 0.047918542326875327f, -0.998851246833715180f, 0.047727014119310344f, + -0.998860416736620520f, + 0.047535484156959261f, -0.998869549914283560f, 0.047343952446864526f, + -0.998878646366368690f, + 0.047152418996068000f, -0.998887706092541290f, 0.046960883811611599f, + -0.998896729092468410f, + 0.046769346900537960f, -0.998905715365818290f, 0.046577808269888908f, + -0.998914664912260440f, + 0.046386267926707213f, -0.998923577731465780f, 0.046194725878035046f, + -0.998932453823106690f, + 0.046003182130914644f, -0.998941293186856870f, 0.045811636692388955f, + -0.998950095822391250f, + 0.045620089569500123f, -0.998958861729386080f, 0.045428540769291224f, + -0.998967590907519300f, + 0.045236990298804750f, -0.998976283356469820f, 0.045045438165083225f, + -0.998984939075918010f, + 0.044853884375169933f, -0.998993558065545680f, 0.044662328936107311f, + -0.999002140325035980f, + 0.044470771854938744f, -0.999010685854073380f, 0.044279213138707016f, + -0.999019194652343460f, + 0.044087652794454979f, -0.999027666719533690f, 0.043896090829226200f, + -0.999036102055332330f, + 0.043704527250063421f, -0.999044500659429290f, 0.043512962064010327f, + -0.999052862531515930f, + 0.043321395278109784f, -0.999061187671284600f, 0.043129826899405595f, + -0.999069476078429330f, + 0.042938256934940959f, -0.999077727752645360f, 0.042746685391759139f, + -0.999085942693629270f, + 0.042555112276904117f, -0.999094120901079070f, 0.042363537597419038f, + -0.999102262374694130f, + 0.042171961360348002f, -0.999110367114174890f, 0.041980383572734502f, + -0.999118435119223490f, + 0.041788804241622082f, -0.999126466389543390f, 0.041597223374055005f, + -0.999134460924839150f, + 0.041405640977076712f, -0.999142418724816910f, 0.041214057057731589f, + -0.999150339789184110f, + 0.041022471623063397f, -0.999158224117649430f, 0.040830884680115968f, + -0.999166071709923000f, + 0.040639296235933854f, -0.999173882565716380f, 0.040447706297560768f, + -0.999181656684742350f, + 0.040256114872041358f, -0.999189394066714920f, 0.040064521966419686f, + -0.999197094711349880f, + 0.039872927587739845f, -0.999204758618363890f, 0.039681331743046659f, + -0.999212385787475290f, + 0.039489734439384118f, -0.999219976218403530f, 0.039298135683797149f, + -0.999227529910869610f, + 0.039106535483329839f, -0.999235046864595850f, 0.038914933845027241f, + -0.999242527079305830f, + 0.038723330775933762f, -0.999249970554724420f, 0.038531726283093877f, + -0.999257377290578060f, + 0.038340120373552791f, -0.999264747286594420f, 0.038148513054354856f, + -0.999272080542502610f, + 0.037956904332545366f, -0.999279377058032710f, 0.037765294215169005f, + -0.999286636832916740f, + 0.037573682709270514f, -0.999293859866887790f, 0.037382069821895340f, + -0.999301046159680070f, + 0.037190455560088091f, -0.999308195711029470f, 0.036998839930894332f, + -0.999315308520673070f, + 0.036807222941358991f, -0.999322384588349540f, 0.036615604598527057f, + -0.999329423913798420f, + 0.036423984909444228f, -0.999336426496761240f, 0.036232363881155374f, + -0.999343392336980220f, + 0.036040741520706299f, -0.999350321434199440f, 0.035849117835142184f, + -0.999357213788164000f, + 0.035657492831508264f, -0.999364069398620550f, 0.035465866516850478f, + -0.999370888265317060f, + 0.035274238898213947f, -0.999377670388002850f, 0.035082609982644702f, + -0.999384415766428560f, + 0.034890979777187955f, -0.999391124400346050f, 0.034699348288889847f, + -0.999397796289508640f, + 0.034507715524795889f, -0.999404431433671300f, 0.034316081491951658f, + -0.999411029832589780f, + 0.034124446197403423f, -0.999417591486021720f, 0.033932809648196623f, + -0.999424116393725640f, + 0.033741171851377642f, -0.999430604555461730f, 0.033549532813992221f, + -0.999437055970991530f, + 0.033357892543086159f, -0.999443470640077770f, 0.033166251045705968f, + -0.999449848562484530f, + 0.032974608328897315f, -0.999456189737977340f, 0.032782964399706793f, + -0.999462494166323160f, + 0.032591319265180385f, -0.999468761847290050f, 0.032399672932364114f, + -0.999474992780647780f, + 0.032208025408304704f, -0.999481186966166950f, 0.032016376700048046f, + -0.999487344403620080f, + 0.031824726814640963f, -0.999493465092780590f, 0.031633075759129645f, + -0.999499549033423640f, + 0.031441423540560343f, -0.999505596225325310f, 0.031249770165979990f, + -0.999511606668263440f, + 0.031058115642434700f, -0.999517580362016990f, 0.030866459976971503f, + -0.999523517306366350f, + 0.030674803176636581f, -0.999529417501093140f, 0.030483145248477058f, + -0.999535280945980540f, + 0.030291486199539423f, -0.999541107640812940f, 0.030099826036870208f, + -0.999546897585375960f, + 0.029908164767516655f, -0.999552650779456990f, 0.029716502398525156f, + -0.999558367222844300f, + 0.029524838936943035f, -0.999564046915327740f, 0.029333174389816984f, + -0.999569689856698580f, + 0.029141508764193740f, -0.999575296046749220f, 0.028949842067120746f, + -0.999580865485273700f, + 0.028758174305644590f, -0.999586398172067070f, 0.028566505486812797f, + -0.999591894106925950f, + 0.028374835617672258f, -0.999597353289648380f, 0.028183164705269902f, + -0.999602775720033530f, + 0.027991492756653365f, -0.999608161397882110f, 0.027799819778869434f, + -0.999613510322995950f, + 0.027608145778965820f, -0.999618822495178640f, 0.027416470763989606f, + -0.999624097914234570f, + 0.027224794740987910f, -0.999629336579970110f, 0.027033117717008563f, + -0.999634538492192300f, + 0.026841439699098527f, -0.999639703650710200f, 0.026649760694305708f, + -0.999644832055333610f, + 0.026458080709677145f, -0.999649923705874240f, 0.026266399752260809f, + -0.999654978602144690f, + 0.026074717829104040f, -0.999659996743959220f, 0.025883034947254208f, + -0.999664978131133310f, + 0.025691351113759395f, -0.999669922763483760f, 0.025499666335666818f, + -0.999674830640828740f, + 0.025307980620024630f, -0.999679701762987930f, 0.025116293973880335f, + -0.999684536129782140f, + 0.024924606404281485f, -0.999689333741033640f, 0.024732917918276334f, + -0.999694094596566000f, + 0.024541228522912264f, -0.999698818696204250f, 0.024349538225237600f, + -0.999703506039774650f, + 0.024157847032300020f, -0.999708156627104880f, 0.023966154951147241f, + -0.999712770458023870f, + 0.023774461988827676f, -0.999717347532362190f, 0.023582768152388880f, + -0.999721887849951310f, + 0.023391073448879338f, -0.999726391410624470f, 0.023199377885346890f, + -0.999730858214216030f, + 0.023007681468839410f, -0.999735288260561680f, 0.022815984206405477f, + -0.999739681549498660f, + 0.022624286105092803f, -0.999744038080865430f, 0.022432587171950024f, + -0.999748357854501780f, + 0.022240887414024919f, -0.999752640870248840f, 0.022049186838366180f, + -0.999756887127949080f, + 0.021857485452021874f, -0.999761096627446610f, 0.021665783262040089f, + -0.999765269368586450f, + 0.021474080275469605f, -0.999769405351215280f, 0.021282376499358355f, + -0.999773504575180990f, + 0.021090671940755180f, -0.999777567040332940f, 0.020898966606708289f, + -0.999781592746521670f, + 0.020707260504265912f, -0.999785581693599210f, 0.020515553640476986f, + -0.999789533881418780f, + 0.020323846022389572f, -0.999793449309835270f, 0.020132137657052664f, + -0.999797327978704690f, + 0.019940428551514598f, -0.999801169887884260f, 0.019748718712823757f, + -0.999804975037232870f, + 0.019557008148029204f, -0.999808743426610520f, 0.019365296864179146f, + -0.999812475055878780f, + 0.019173584868322699f, -0.999816169924900410f, 0.018981872167508348f, + -0.999819828033539420f, + 0.018790158768784596f, -0.999823449381661570f, 0.018598444679200642f, + -0.999827033969133420f, + 0.018406729905804820f, -0.999830581795823400f, 0.018215014455646376f, + -0.999834092861600960f, + 0.018023298335773701f, -0.999837567166337090f, 0.017831581553236088f, + -0.999841004709904000f, + 0.017639864115082195f, -0.999844405492175240f, 0.017448146028360704f, + -0.999847769513025900f, + 0.017256427300120978f, -0.999851096772332190f, 0.017064707937411529f, + -0.999854387269971890f, + 0.016872987947281773f, -0.999857641005823860f, 0.016681267336780482f, + -0.999860857979768540f, + 0.016489546112956454f, -0.999864038191687680f, 0.016297824282859176f, + -0.999867181641464380f, + 0.016106101853537263f, -0.999870288328982950f, 0.015914378832040249f, + -0.999873358254129260f, + 0.015722655225417017f, -0.999876391416790410f, 0.015530931040716478f, + -0.999879387816854930f, + 0.015339206284988220f, -0.999882347454212560f, 0.015147480965280975f, + -0.999885270328754520f, + 0.014955755088644378f, -0.999888156440373320f, 0.014764028662127416f, + -0.999891005788962950f, + 0.014572301692779104f, -0.999893818374418490f, 0.014380574187649138f, + -0.999896594196636680f, + 0.014188846153786343f, -0.999899333255515390f, 0.013997117598240459f, + -0.999902035550953920f, + 0.013805388528060349f, -0.999904701082852900f, 0.013613658950295789f, + -0.999907329851114300f, + 0.013421928871995907f, -0.999909921855641540f, 0.013230198300209845f, + -0.999912477096339240f, + 0.013038467241987433f, -0.999914995573113470f, 0.012846735704377631f, + -0.999917477285871770f, + 0.012655003694430301f, -0.999919922234522750f, 0.012463271219194662f, + -0.999922330418976490f, + 0.012271538285719944f, -0.999924701839144500f, 0.012079804901056066f, + -0.999927036494939640f, + 0.011888071072252072f, -0.999929334386276070f, 0.011696336806357907f, + -0.999931595513069200f, + 0.011504602110422875f, -0.999933819875236000f, 0.011312866991496287f, + -0.999936007472694620f, + 0.011121131456628141f, -0.999938158305364590f, 0.010929395512867561f, + -0.999940272373166960f, + 0.010737659167264572f, -0.999942349676023910f, 0.010545922426868548f, + -0.999944390213859060f, + 0.010354185298728884f, -0.999946393986597460f, 0.010162447789895645f, + -0.999948360994165400f, + 0.009970709907418029f, -0.999950291236490480f, 0.009778971658346134f, + -0.999952184713501780f, + 0.009587233049729183f, -0.999954041425129780f, 0.009395494088617302f, + -0.999955861371306100f, + 0.009203754782059960f, -0.999957644551963900f, 0.009012015137106642f, + -0.999959390967037450f, + 0.008820275160807512f, -0.999961100616462820f, 0.008628534860211857f, + -0.999962773500176930f, + 0.008436794242369860f, -0.999964409618118280f, 0.008245053314331058f, + -0.999966008970226920f, + 0.008053312083144991f, -0.999967571556443780f, 0.007861570555861883f, + -0.999969097376711580f, + 0.007669828739531077f, -0.999970586430974140f, 0.007478086641202815f, + -0.999972038719176730f, + 0.007286344267926684f, -0.999973454241265940f, 0.007094601626752279f, + -0.999974832997189810f, + 0.006902858724729877f, -0.999976174986897610f, 0.006711115568908869f, + -0.999977480210339940f, + 0.006519372166339549f, -0.999978748667468830f, 0.006327628524071549f, + -0.999979980358237650f, + 0.006135884649154515f, -0.999981175282601110f, 0.005944140548638765f, + -0.999982333440515350f, + 0.005752396229573737f, -0.999983454831937730f, 0.005560651699009764f, + -0.999984539456826970f, + 0.005368906963996303f, -0.999985587315143200f, 0.005177162031583702f, + -0.999986598406848000f, + 0.004985416908821652f, -0.999987572731904080f, 0.004793671602759852f, + -0.999988510290275690f, + 0.004601926120448672f, -0.999989411081928400f, 0.004410180468937601f, + -0.999990275106828920f, + 0.004218434655277024f, -0.999991102364945590f, 0.004026688686516664f, + -0.999991892856248010f, + 0.003834942569706248f, -0.999992646580707190f, 0.003643196311896179f, + -0.999993363538295150f, + 0.003451449920135975f, -0.999994043728985820f, 0.003259703401476044f, + -0.999994687152754080f, + 0.003067956762966138f, -0.999995293809576190f, 0.002876210011656010f, + -0.999995863699429940f, + 0.002684463154596083f, -0.999996396822294350f, 0.002492716198835898f, + -0.999996893178149880f, + 0.002300969151425887f, -0.999997352766978210f, 0.002109222019415816f, + -0.999997775588762350f, + 0.001917474809855460f, -0.999998161643486980f, 0.001725727529795258f, + -0.999998510931137790f, + 0.001533980186284766f, -0.999998823451701880f, 0.001342232786374430f, + -0.999999099205167830f, + 0.001150485337113809f, -0.999999338191525530f, 0.000958737845553352f, + -0.999999540410766110f, + 0.000766990318742846f, -0.999999705862882230f, 0.000575242763732077f, + -0.999999834547867670f, + 0.000383495187571497f, -0.999999926465717890f, 0.000191747597310674f, + -0.999999981616429330f +}; + + const float32_t cos_factors_8192[8192] = { + 1.999999990808214700f, 1.999999917273932200f, 1.999999770205369800f, + 1.999999549602533100f, + 1.999999255465430200f, 1.999998887794072000f, 1.999998446588471700f, + 1.999997931848645600f, + 1.999997343574612800f, 1.999996681766395000f, 1.999995946424016200f, + 1.999995137547503600f, + 1.999994255136887000f, 1.999993299192198700f, 1.999992269713474200f, + 1.999991166700750800f, + 1.999989990154069600f, 1.999988740073473500f, 1.999987416459008600f, + 1.999986019310723500f, + 1.999984548628669600f, 1.999983004412901000f, 1.999981386663474400f, + 1.999979695380449400f, + 1.999977930563888100f, 1.999976092213855400f, 1.999974180330418700f, + 1.999972194913648900f, + 1.999970135963618400f, 1.999968003480403000f, 1.999965797464081200f, + 1.999963517914734100f, + 1.999961164832445800f, 1.999958738217302300f, 1.999956238069392900f, + 1.999953664388809800f, + 1.999951017175647600f, 1.999948296430003500f, 1.999945502151977600f, + 1.999942634341672600f, + 1.999939692999193900f, 1.999936678124649700f, 1.999933589718150700f, + 1.999930427779810900f, + 1.999927192309745900f, 1.999923883308075200f, 1.999920500774920300f, + 1.999917044710405500f, + 1.999913515114657900f, 1.999909911987807200f, 1.999906235329986100f, + 1.999902485141329400f, + 1.999898661421975400f, 1.999894764172064600f, 1.999890793391740000f, + 1.999886749081147800f, + 1.999882631240436700f, 1.999878439869758200f, 1.999874174969266300f, + 1.999869836539117700f, + 1.999865424579472000f, 1.999860939090491600f, 1.999856380072341000f, + 1.999851747525188200f, + 1.999847041449203300f, 1.999842261844559700f, 1.999837408711432600f, + 1.999832482050000900f, + 1.999827481860445300f, 1.999822408142949900f, 1.999817260897701400f, + 1.999812040124888700f, + 1.999806745824704000f, 1.999801377997341800f, 1.999795936642999600f, + 1.999790421761877400f, + 1.999784833354177900f, 1.999779171420106700f, 1.999773435959872000f, + 1.999767626973684400f, + 1.999761744461757700f, 1.999755788424308200f, 1.999749758861554900f, + 1.999743655773719400f, + 1.999737479161026100f, 1.999731229023702200f, 1.999724905361977200f, + 1.999718508176084000f, + 1.999712037466257600f, 1.999705493232735800f, 1.999698875475759600f, + 1.999692184195571900f, + 1.999685419392419000f, 1.999678581066549400f, 1.999671669218214600f, + 1.999664683847668800f, + 1.999657624955168700f, 1.999650492540973900f, 1.999643286605346800f, + 1.999636007148552400f, + 1.999628654170857900f, 1.999621227672533800f, 1.999613727653853500f, + 1.999606154115092500f, + 1.999598507056529000f, 1.999590786478444600f, 1.999582992381123000f, + 1.999575124764850800f, + 1.999567183629917100f, 1.999559168976613900f, 1.999551080805236100f, + 1.999542919116081000f, + 1.999534683909448600f, 1.999526375185641800f, 1.999517992944965800f, + 1.999509537187729200f, + 1.999501007914242600f, 1.999492405124819700f, 1.999483728819776900f, + 1.999474978999432800f, + 1.999466155664109600f, 1.999457258814131500f, 1.999448288449825500f, + 1.999439244571521700f, + 1.999430127179552500f, 1.999420936274252800f, 1.999411671855960900f, + 1.999402333925017300f, + 1.999392922481765500f, 1.999383437526551300f, 1.999373879059723500f, + 1.999364247081633500f, + 1.999354541592635500f, 1.999344762593086500f, 1.999334910083345700f, + 1.999324984063775700f, + 1.999314984534741100f, 1.999304911496609700f, 1.999294764949752100f, + 1.999284544894541100f, + 1.999274251331352400f, 1.999263884260564600f, 1.999253443682558900f, + 1.999242929597719200f, + 1.999232342006432000f, 1.999221680909086400f, 1.999210946306074500f, + 1.999200138197791100f, + 1.999189256584633600f, 1.999178301467001900f, 1.999167272845298900f, + 1.999156170719930100f, + 1.999144995091303600f, 1.999133745959830600f, 1.999122423325924200f, + 1.999111027190001000f, + 1.999099557552479900f, 1.999088014413782800f, 1.999076397774334000f, + 1.999064707634560700f, + 1.999052943994892300f, 1.999041106855761900f, 1.999029196217604100f, + 1.999017212080857400f, + 1.999005154445962200f, 1.998993023313361700f, 1.998980818683502100f, + 1.998968540556831800f, + 1.998956188933802800f, 1.998943763814868800f, 1.998931265200486900f, + 1.998918693091116200f, + 1.998906047487219600f, 1.998893328389261400f, 1.998880535797709700f, + 1.998867669713034500f, + 1.998854730135709400f, 1.998841717066209400f, 1.998828630505013400f, + 1.998815470452602400f, + 1.998802236909460500f, 1.998788929876074100f, 1.998775549352932400f, + 1.998762095340527400f, + 1.998748567839354000f, 1.998734966849909000f, 1.998721292372693100f, + 1.998707544408208700f, + 1.998693722956961500f, 1.998679828019459300f, 1.998665859596213500f, + 1.998651817687737300f, + 1.998637702294547000f, 1.998623513417161700f, 1.998609251056103100f, + 1.998594915211895600f, + 1.998580505885066100f, 1.998566023076144600f, 1.998551466785663400f, + 1.998536837014157900f, + 1.998522133762165900f, 1.998507357030227900f, 1.998492506818887200f, + 1.998477583128690100f, + 1.998462585960185000f, 1.998447515313923400f, 1.998432371190459500f, + 1.998417153590349900f, + 1.998401862514154200f, 1.998386497962434800f, 1.998371059935756300f, + 1.998355548434686400f, + 1.998339963459795400f, 1.998324305011656600f, 1.998308573090845200f, + 1.998292767697940100f, + 1.998276888833522300f, 1.998260936498175400f, 1.998244910692486000f, + 1.998228811417043700f, + 1.998212638672439900f, 1.998196392459269400f, 1.998180072778129600f, + 1.998163679629620500f, + 1.998147213014344900f, 1.998130672932908000f, 1.998114059385918400f, + 1.998097372373986300f, + 1.998080611897725700f, 1.998063777957752600f, 1.998046870554686100f, + 1.998029889689147700f, + 1.998012835361761900f, 1.997995707573155600f, 1.997978506323958600f, + 1.997961231614803200f, + 1.997943883446324800f, 1.997926461819161000f, 1.997908966733952500f, + 1.997891398191342400f, + 1.997873756191977000f, 1.997856040736504500f, 1.997838251825576400f, + 1.997820389459846700f, + 1.997802453639972300f, 1.997784444366612600f, 1.997766361640429800f, + 1.997748205462088500f, + 1.997729975832256600f, 1.997711672751604200f, 1.997693296220804000f, + 1.997674846240532000f, + 1.997656322811466500f, 1.997637725934288300f, 1.997619055609681600f, + 1.997600311838332500f, + 1.997581494620930300f, 1.997562603958166600f, 1.997543639850736200f, + 1.997524602299336500f, + 1.997505491304667000f, 1.997486306867430900f, 1.997467048988333000f, + 1.997447717668082000f, + 1.997428312907388200f, 1.997408834706965000f, 1.997389283067528800f, + 1.997369657989798400f, + 1.997349959474495200f, 1.997330187522343700f, 1.997310342134070800f, + 1.997290423310406100f, + 1.997270431052081900f, 1.997250365359833200f, 1.997230226234397900f, + 1.997210013676516700f, + 1.997189727686932400f, 1.997169368266390900f, 1.997148935415640600f, + 1.997128429135433400f, + 1.997107849426522600f, 1.997087196289665000f, 1.997066469725620200f, + 1.997045669735150000f, + 1.997024796319019300f, 1.997003849477995600f, 1.996982829212848900f, + 1.996961735524351900f, + 1.996940568413280600f, 1.996919327880412900f, 1.996898013926530000f, + 1.996876626552415400f, + 1.996855165758855600f, 1.996833631546639300f, 1.996812023916558800f, + 1.996790342869408000f, + 1.996768588405984300f, 1.996746760527087700f, 1.996724859233520500f, + 1.996702884526087900f, + 1.996680836405598100f, 1.996658714872861800f, 1.996636519928692000f, + 1.996614251573904900f, + 1.996591909809319400f, 1.996569494635756600f, 1.996547006054041100f, + 1.996524444064999400f, + 1.996501808669461000f, 1.996479099868258400f, 1.996456317662226300f, + 1.996433462052202600f, + 1.996410533039027400f, 1.996387530623543900f, 1.996364454806597500f, + 1.996341305589037100f, + 1.996318082971713500f, 1.996294786955480800f, 1.996271417541195300f, + 1.996247974729716200f, + 1.996224458521905600f, 1.996200868918628100f, 1.996177205920750800f, + 1.996153469529144100f, + 1.996129659744680300f, 1.996105776568235100f, 1.996081820000686500f, + 1.996057790042915500f, + 1.996033686695805300f, 1.996009509960242400f, 1.995985259837115500f, + 1.995960936327316300f, + 1.995936539431739000f, 1.995912069151280800f, 1.995887525486841300f, + 1.995862908439323100f, + 1.995838218009630800f, 1.995813454198672700f, 1.995788617007359100f, + 1.995763706436603200f, + 1.995738722487320600f, 1.995713665160430600f, 1.995688534456853800f, + 1.995663330377514400f, + 1.995638052923339300f, 1.995612702095257400f, 1.995587277894201400f, + 1.995561780321105600f, + 1.995536209376907600f, 1.995510565062547800f, 1.995484847378968600f, + 1.995459056327116000f, + 1.995433191907938000f, 1.995407254122385700f, 1.995381242971412600f, + 1.995355158455975200f, + 1.995329000577032800f, 1.995302769335546500f, 1.995276464732481200f, + 1.995250086768804100f, + 1.995223635445484900f, 1.995197110763496000f, 1.995170512723813100f, + 1.995143841327413400f, + 1.995117096575278200f, 1.995090278468390600f, 1.995063387007736600f, + 1.995036422194304700f, + 1.995009384029086800f, 1.994982272513076600f, 1.994955087647271000f, + 1.994927829432669800f, + 1.994900497870274900f, 1.994873092961091200f, 1.994845614706126400f, + 1.994818063106391000f, + 1.994790438162897600f, 1.994762739876662100f, 1.994734968248702800f, + 1.994707123280041100f, + 1.994679204971700100f, 1.994651213324707000f, 1.994623148340090700f, + 1.994595010018883000f, + 1.994566798362118300f, 1.994538513370834200f, 1.994510155046070700f, + 1.994481723388870100f, + 1.994453218400277900f, 1.994424640081342100f, 1.994395988433113700f, + 1.994367263456646100f, + 1.994338465152995000f, 1.994309593523219600f, 1.994280648568381500f, + 1.994251630289544600f, + 1.994222538687776100f, 1.994193373764145500f, 1.994164135519725000f, + 1.994134823955589800f, + 1.994105439072817700f, 1.994075980872488800f, 1.994046449355686200f, + 1.994016844523496000f, + 1.993987166377006600f, 1.993957414917308700f, 1.993927590145496900f, + 1.993897692062667200f, + 1.993867720669919400f, 1.993837675968354700f, 1.993807557959078600f, + 1.993777366643197900f, + 1.993747102021822900f, 1.993716764096066200f, 1.993686352867043200f, + 1.993655868335872300f, + 1.993625310503674100f, 1.993594679371572200f, 1.993563974940692800f, + 1.993533197212164800f, + 1.993502346187119700f, 1.993471421866692200f, 1.993440424252018900f, + 1.993409353344239600f, + 1.993378209144496700f, 1.993346991653935300f, 1.993315700873703200f, + 1.993284336804950900f, + 1.993252899448831400f, 1.993221388806500900f, 1.993189804879117500f, + 1.993158147667842800f, + 1.993126417173840500f, 1.993094613398277400f, 1.993062736342323000f, + 1.993030786007148800f, + 1.992998762393930000f, 1.992966665503844000f, 1.992934495338070800f, + 1.992902251897793000f, + 1.992869935184196300f, 1.992837545198469000f, 1.992805081941801700f, + 1.992772545415388200f, + 1.992739935620424700f, 1.992707252558110200f, 1.992674496229646500f, + 1.992641666636237700f, + 1.992608763779091000f, 1.992575787659416100f, 1.992542738278425300f, + 1.992509615637334100f, + 1.992476419737359900f, 1.992443150579723500f, 1.992409808165648100f, + 1.992376392496359300f, + 1.992342903573086000f, 1.992309341397059600f, 1.992275705969513800f, + 1.992241997291685400f, + 1.992208215364813700f, 1.992174360190140900f, 1.992140431768911500f, + 1.992106430102373400f, + 1.992072355191776300f, 1.992038207038373300f, 1.992003985643419700f, + 1.991969691008174100f, + 1.991935323133897000f, 1.991900882021852200f, 1.991866367673306200f, + 1.991831780089527500f, + 1.991797119271788300f, 1.991762385221362600f, 1.991727577939527600f, + 1.991692697427563300f, + 1.991657743686751700f, 1.991622716718378400f, 1.991587616523731000f, + 1.991552443104099800f, + 1.991517196460778500f, 1.991481876595062800f, 1.991446483508251500f, + 1.991411017201645500f, + 1.991375477676549100f, 1.991339864934268800f, 1.991304178976114100f, + 1.991268419803397200f, + 1.991232587417432600f, 1.991196681819537900f, 1.991160703011033200f, + 1.991124650993241400f, + 1.991088525767488200f, 1.991052327335101300f, 1.991016055697411900f, + 1.990979710855753900f, + 1.990943292811463000f, 1.990906801565878600f, 1.990870237120342400f, + 1.990833599476198800f, + 1.990796888634794400f, 1.990760104597479400f, 1.990723247365606200f, + 1.990686316940529800f, + 1.990649313323608100f, 1.990612236516201300f, 1.990575086519673200f, + 1.990537863335389400f, + 1.990500566964718400f, 1.990463197409031700f, 1.990425754669703100f, + 1.990388238748109100f, + 1.990350649645629600f, 1.990312987363646000f, 1.990275251903543600f, + 1.990237443266709400f, + 1.990199561454533600f, 1.990161606468409300f, 1.990123578309731700f, + 1.990085476979899000f, + 1.990047302480312300f, 1.990009054812374800f, 1.989970733977493000f, + 1.989932339977075900f, + 1.989893872812535000f, 1.989855332485284800f, 1.989816718996742200f, + 1.989778032348326700f, + 1.989739272541461100f, 1.989700439577570400f, 1.989661533458082100f, + 1.989622554184426800f, + 1.989583501758037700f, 1.989544376180350600f, 1.989505177452804100f, + 1.989465905576839600f, + 1.989426560553900500f, 1.989387142385433900f, 1.989347651072888900f, + 1.989308086617717500f, + 1.989268449021374300f, 1.989228738285316900f, 1.989188954411005100f, + 1.989149097399901500f, + 1.989109167253472000f, 1.989069163973184300f, 1.989029087560509700f, + 1.988988938016921000f, + 1.988948715343894900f, 1.988908419542910100f, 1.988868050615448100f, + 1.988827608562993200f, + 1.988787093387032600f, 1.988746505089055600f, 1.988705843670554500f, + 1.988665109133024500f, + 1.988624301477963200f, 1.988583420706871100f, 1.988542466821251000f, + 1.988501439822608900f, + 1.988460339712453200f, 1.988419166492295000f, 1.988377920163648000f, + 1.988336600728029000f, + 1.988295208186956700f, 1.988253742541953800f, 1.988212203794544000f, + 1.988170591946255100f, + 1.988128906998616800f, 1.988087148953161700f, 1.988045317811425700f, + 1.988003413574946000f, + 1.987961436245263800f, 1.987919385823922400f, 1.987877262312467600f, + 1.987835065712448600f, + 1.987792796025416500f, 1.987750453252925500f, 1.987708037396532800f, + 1.987665548457797400f, + 1.987622986438281700f, 1.987580351339550700f, 1.987537643163171700f, + 1.987494861910715100f, + 1.987452007583754100f, 1.987409080183863800f, 1.987366079712622900f, + 1.987323006171612500f, + 1.987279859562415900f, 1.987236639886619700f, 1.987193347145813000f, + 1.987149981341587400f, + 1.987106542475537400f, 1.987063030549260300f, 1.987019445564355700f, + 1.986975787522426100f, + 1.986932056425076800f, 1.986888252273915500f, 1.986844375070552900f, + 1.986800424816602200f, + 1.986756401513679400f, 1.986712305163403000f, 1.986668135767394300f, + 1.986623893327277500f, + 1.986579577844678900f, 1.986535189321228000f, 1.986490727758556800f, + 1.986446193158300400f, + 1.986401585522095600f, 1.986356904851583000f, 1.986312151148405200f, + 1.986267324414207500f, + 1.986222424650638400f, 1.986177451859348200f, 1.986132406041990900f, + 1.986087287200222700f, + 1.986042095335702300f, 1.985996830450091200f, 1.985951492545054100f, + 1.985906081622257300f, + 1.985860597683371000f, 1.985815040730067200f, 1.985769410764020900f, + 1.985723707786909900f, + 1.985677931800414500f, 1.985632082806217900f, 1.985586160806005700f, + 1.985540165801466200f, + 1.985494097794290800f, 1.985447956786173100f, 1.985401742778809500f, + 1.985355455773899500f, + 1.985309095773144500f, 1.985262662778249300f, 1.985216156790921000f, + 1.985169577812869500f, + 1.985122925845807400f, 1.985076200891450000f, 1.985029402951515200f, + 1.984982532027723700f, + 1.984935588121798700f, 1.984888571235466200f, 1.984841481370454900f, + 1.984794318528496200f, + 1.984747082711324100f, 1.984699773920675300f, 1.984652392158289500f, + 1.984604937425908300f, + 1.984557409725276700f, 1.984509809058142300f, 1.984462135426255000f, + 1.984414388831367900f, + 1.984366569275236400f, 1.984318676759618400f, 1.984270711286275200f, + 1.984222672856969800f, + 1.984174561473469200f, 1.984126377137541700f, 1.984078119850959200f, + 1.984029789615495900f, + 1.983981386432928800f, 1.983932910305037400f, 1.983884361233604100f, + 1.983835739220414000f, + 1.983787044267254700f, 1.983738276375916800f, 1.983689435548192900f, + 1.983640521785879200f, + 1.983591535090773800f, 1.983542475464678000f, 1.983493342909395500f, + 1.983444137426732600f, + 1.983394859018498900f, 1.983345507686505900f, 1.983296083432567900f, + 1.983246586258502700f, + 1.983197016166129400f, 1.983147373157271300f, 1.983097657233753100f, + 1.983047868397403100f, + 1.982998006650051400f, 1.982948071993531700f, 1.982898064429679900f, + 1.982847983960334600f, + 1.982797830587336800f, 1.982747604312531200f, 1.982697305137763700f, + 1.982646933064884200f, + 1.982596488095744300f, 1.982545970232199000f, 1.982495379476105800f, + 1.982444715829324600f, + 1.982393979293718200f, 1.982343169871152000f, 1.982292287563494300f, + 1.982241332372615600f, + 1.982190304300389400f, 1.982139203348692200f, 1.982088029519402300f, + 1.982036782814401900f, + 1.981985463235574700f, 1.981934070784807400f, 1.981882605463990200f, + 1.981831067275015000f, + 1.981779456219776600f, 1.981727772300172500f, 1.981676015518103500f, + 1.981624185875472000f, + 1.981572283374183800f, 1.981520308016147200f, 1.981468259803273300f, + 1.981416138737475800f, + 1.981363944820670800f, 1.981311678054777500f, 1.981259338441717400f, + 1.981206925983415300f, + 1.981154440681797800f, 1.981101882538794900f, 1.981049251556338900f, + 1.980996547736364900f, + 1.980943771080810700f, 1.980890921591616600f, 1.980837999270726100f, + 1.980785004120084700f, + 1.980731936141640900f, 1.980678795337345900f, 1.980625581709153600f, + 1.980572295259020600f, + 1.980518935988905700f, 1.980465503900771000f, 1.980411998996581200f, + 1.980358421278303200f, + 1.980304770747907300f, 1.980251047407365600f, 1.980197251258653900f, + 1.980143382303749500f, + 1.980089440544633600f, 1.980035425983289300f, 1.979981338621702200f, + 1.979927178461861500f, + 1.979872945505758000f, 1.979818639755386100f, 1.979764261212742400f, + 1.979709809879825800f, + 1.979655285758638900f, 1.979600688851186100f, 1.979546019159474900f, + 1.979491276685515300f, + 1.979436461431320000f, 1.979381573398904400f, 1.979326612590286400f, + 1.979271579007487100f, + 1.979216472652529900f, 1.979161293527440500f, 1.979106041634248100f, + 1.979050716974983800f, + 1.978995319551682100f, 1.978939849366379700f, 1.978884306421115900f, + 1.978828690717932900f, + 1.978773002258875600f, 1.978717241045991700f, 1.978661407081331100f, + 1.978605500366946700f, + 1.978549520904894000f, 1.978493468697231300f, 1.978437343746019600f, + 1.978381146053322000f, + 1.978324875621205300f, 1.978268532451738200f, 1.978212116546992100f, + 1.978155627909041300f, + 1.978099066539962900f, 1.978042432441836400f, 1.977985725616743900f, + 1.977928946066770600f, + 1.977872093794004200f, 1.977815168800534500f, 1.977758171088455100f, + 1.977701100659861300f, + 1.977643957516851400f, 1.977586741661526500f, 1.977529453095990200f, + 1.977472091822348700f, + 1.977414657842711200f, 1.977357151159189400f, 1.977299571773897700f, + 1.977241919688953000f, + 1.977184194906475000f, 1.977126397428586000f, 1.977068527257411300f, + 1.977010584395078300f, + 1.976952568843717700f, 1.976894480605462500f, 1.976836319682448300f, + 1.976778086076813600f, + 1.976719779790699500f, 1.976661400826249500f, 1.976602949185610500f, + 1.976544424870931400f, + 1.976485827884363800f, 1.976427158228062100f, 1.976368415904183900f, + 1.976309600914888400f, + 1.976250713262338600f, 1.976191752948699200f, 1.976132719976138000f, + 1.976073614346825800f, + 1.976014436062935700f, 1.975955185126643300f, 1.975895861540127200f, + 1.975836465305568400f, + 1.975776996425151000f, 1.975717454901061400f, 1.975657840735488800f, + 1.975598153930624900f, + 1.975538394488664200f, 1.975478562411804100f, 1.975418657702244300f, + 1.975358680362187400f, + 1.975298630393838500f, 1.975238507799405500f, 1.975178312581099100f, + 1.975118044741132300f, + 1.975057704281721000f, 1.974997291205083700f, 1.974936805513442000f, + 1.974876247209019100f, + 1.974815616294042200f, 1.974754912770740200f, 1.974694136641345300f, + 1.974633287908091500f, + 1.974572366573216400f, 1.974511372638960000f, 1.974450306107564900f, + 1.974389166981275900f, + 1.974327955262341400f, 1.974266670953011400f, 1.974205314055540000f, + 1.974143884572182400f, + 1.974082382505197400f, 1.974020807856846400f, 1.973959160629393100f, + 1.973897440825104200f, + 1.973835648446248900f, 1.973773783495099500f, 1.973711845973930000f, + 1.973649835885018100f, + 1.973587753230643400f, 1.973525598013088800f, 1.973463370234639600f, + 1.973401069897583200f, + 1.973338697004211100f, 1.973276251556815600f, 1.973213733557693400f, + 1.973151143009142800f, + 1.973088479913465100f, 1.973025744272964200f, 1.972962936089946800f, + 1.972900055366722000f, + 1.972837102105601900f, 1.972774076308901200f, 1.972710977978936900f, + 1.972647807118029300f, + 1.972584563728500700f, 1.972521247812676600f, 1.972457859372884500f, + 1.972394398411455800f, + 1.972330864930723200f, 1.972267258933022600f, 1.972203580420693000f, + 1.972139829396075200f, + 1.972076005861513700f, 1.972012109819354600f, 1.971948141271947500f, + 1.971884100221644300f, + 1.971819986670799500f, 1.971755800621770400f, 1.971691542076916800f, + 1.971627211038601500f, + 1.971562807509189800f, 1.971498331491049700f, 1.971433782986551400f, + 1.971369161998068400f, + 1.971304468527976800f, 1.971239702578655000f, 1.971174864152484400f, + 1.971109953251848600f, + 1.971044969879134600f, 1.970979914036731500f, 1.970914785727030800f, + 1.970849584952427900f, + 1.970784311715319400f, 1.970718966018105500f, 1.970653547863188600f, + 1.970588057252973900f, + 1.970522494189869800f, 1.970456858676286300f, 1.970391150714636800f, + 1.970325370307337100f, + 1.970259517456806100f, 1.970193592165464700f, 1.970127594435737000f, + 1.970061524270049400f, + 1.969995381670831100f, 1.969929166640514100f, 1.969862879181532700f, + 1.969796519296324300f, + 1.969730086987328900f, 1.969663582256988600f, 1.969597005107748900f, + 1.969530355542057800f, + 1.969463633562365400f, 1.969396839171125200f, 1.969329972370792700f, + 1.969263033163826800f, + 1.969196021552688500f, 1.969128937539841500f, 1.969061781127752400f, + 1.968994552318890300f, + 1.968927251115727200f, 1.968859877520737300f, 1.968792431536398000f, + 1.968724913165188900f, + 1.968657322409592500f, 1.968589659272094000f, 1.968521923755181000f, + 1.968454115861344000f, + 1.968386235593076300f, 1.968318282952873600f, 1.968250257943234200f, + 1.968182160566659000f, + 1.968113990825652200f, 1.968045748722719900f, 1.967977434260371300f, + 1.967909047441118100f, + 1.967840588267474500f, 1.967772056741957900f, 1.967703452867087800f, + 1.967634776645386600f, + 1.967566028079379200f, 1.967497207171593500f, 1.967428313924559600f, + 1.967359348340810700f, + 1.967290310422882700f, 1.967221200173313400f, 1.967152017594644200f, + 1.967082762689418500f, + 1.967013435460182700f, 1.966944035909485600f, 1.966874564039879300f, + 1.966805019853917500f, + 1.966735403354157500f, 1.966665714543159000f, 1.966595953423483800f, + 1.966526119997697100f, + 1.966456214268366600f, 1.966386236238062200f, 1.966316185909357200f, + 1.966246063284826700f, + 1.966175868367049400f, 1.966105601158605600f, 1.966035261662079300f, + 1.965964849880056600f, + 1.965894365815126000f, 1.965823809469879400f, 1.965753180846910900f, + 1.965682479948817100f, + 1.965611706778197700f, 1.965540861337654600f, 1.965469943629792700f, + 1.965398953657219600f, + 1.965327891422544900f, 1.965256756928382100f, 1.965185550177345900f, + 1.965114271172054800f, + 1.965042919915129400f, 1.964971496409193100f, 1.964900000656872000f, + 1.964828432660794500f, + 1.964756792423592200f, 1.964685079947899200f, 1.964613295236352000f, + 1.964541438291590000f, + 1.964469509116255000f, 1.964397507712991800f, 1.964325434084447600f, + 1.964253288233272400f, + 1.964181070162119000f, 1.964108779873642100f, 1.964036417370500300f, + 1.963963982655353400f, + 1.963891475730865400f, 1.963818896599701400f, 1.963746245264530700f, + 1.963673521728023900f, + 1.963600725992855200f, 1.963527858061700600f, 1.963454917937239800f, + 1.963381905622154400f, + 1.963308821119128700f, 1.963235664430850200f, 1.963162435560008100f, + 1.963089134509295300f, + 1.963015761281406800f, 1.962942315879040000f, 1.962868798304895400f, + 1.962795208561676200f, + 1.962721546652088200f, 1.962647812578839400f, 1.962574006344640900f, + 1.962500127952206300f, + 1.962426177404252200f, 1.962352154703497200f, 1.962278059852663000f, + 1.962203892854473800f, + 1.962129653711656800f, 1.962055342426941400f, 1.961980959003059500f, + 1.961906503442746300f, + 1.961831975748739200f, 1.961757375923778700f, 1.961682703970607100f, + 1.961607959891970200f, + 1.961533143690616000f, 1.961458255369295400f, 1.961383294930761700f, + 1.961308262377770900f, + 1.961233157713082200f, 1.961157980939456400f, 1.961082732059657800f, + 1.961007411076453000f, + 1.960932017992611500f, 1.960856552810905200f, 1.960781015534108800f, + 1.960705406164999300f, + 1.960629724706357100f, 1.960553971160964500f, 1.960478145531606700f, + 1.960402247821071900f, + 1.960326278032150200f, 1.960250236167635100f, 1.960174122230322400f, + 1.960097936223010400f, + 1.960021678148500500f, 1.959945348009596500f, 1.959868945809104500f, + 1.959792471549834000f, + 1.959715925234596600f, 1.959639306866206600f, 1.959562616447480900f, + 1.959485853981239600f, + 1.959409019470304700f, 1.959332112917501400f, 1.959255134325657000f, + 1.959178083697602300f, + 1.959100961036169800f, 1.959023766344195200f, 1.958946499624516700f, + 1.958869160879975500f, + 1.958791750113414700f, 1.958714267327680500f, 1.958636712525621900f, + 1.958559085710090500f, + 1.958481386883940100f, 1.958403616050027600f, 1.958325773211212300f, + 1.958247858370356400f, + 1.958169871530324600f, 1.958091812693984400f, 1.958013681864205500f, + 1.957935479043860600f, + 1.957857204235825100f, 1.957778857442976900f, 1.957700438668196700f, + 1.957621947914367500f, + 1.957543385184375300f, 1.957464750481108700f, 1.957386043807458800f, + 1.957307265166319500f, + 1.957228414560587200f, 1.957149491993160900f, 1.957070497466942400f, + 1.956991430984836400f, + 1.956912292549749500f, 1.956833082164591600f, 1.956753799832275300f, + 1.956674445555715000f, + 1.956595019337829000f, 1.956515521181537000f, 1.956435951089762200f, + 1.956356309065430100f, + 1.956276595111468900f, 1.956196809230809500f, 1.956116951426385600f, + 1.956037021701132900f, + 1.955957020057990500f, 1.955876946499899700f, 1.955796801029804800f, + 1.955716583650652000f, + 1.955636294365391300f, 1.955555933176974300f, 1.955475500088355900f, + 1.955394995102493100f, + 1.955314418222346100f, 1.955233769450877200f, 1.955153048791052000f, + 1.955072256245838000f, + 1.954991391818206000f, 1.954910455511129000f, 1.954829447327582900f, + 1.954748367270545900f, + 1.954667215342999600f, 1.954585991547927100f, 1.954504695888315000f, + 1.954423328367152600f, + 1.954341888987431100f, 1.954260377752145000f, 1.954178794664291200f, + 1.954097139726869600f, + 1.954015412942881900f, 1.953933614315333200f, 1.953851743847231100f, + 1.953769801541585400f, + 1.953687787401409400f, 1.953605701429718100f, 1.953523543629529700f, + 1.953441314003864900f, + 1.953359012555747200f, 1.953276639288202400f, 1.953194194204259200f, + 1.953111677306948800f, + 1.953029088599305100f, 1.952946428084364900f, 1.952863695765167100f, + 1.952780891644753500f, + 1.952698015726169100f, 1.952615068012460300f, 1.952532048506677300f, + 1.952448957211872200f, + 1.952365794131100300f, 1.952282559267419100f, 1.952199252623889200f, + 1.952115874203572900f, + 1.952032424009536600f, 1.951948902044847900f, 1.951865308312577900f, + 1.951781642815800100f, + 1.951697905557590700f, 1.951614096541028500f, 1.951530215769194700f, + 1.951446263245173500f, + 1.951362238972051500f, 1.951278142952918200f, 1.951193975190865600f, + 1.951109735688987900f, + 1.951025424450382900f, 1.950941041478150100f, 1.950856586775392200f, + 1.950772060345214300f, + 1.950687462190724200f, 1.950602792315032200f, 1.950518050721251600f, + 1.950433237412498000f, + 1.950348352391889600f, 1.950263395662547700f, 1.950178367227595900f, + 1.950093267090159800f, + 1.950008095253369200f, 1.949922851720355100f, 1.949837536494251700f, + 1.949752149578196000f, + 1.949666690975327100f, 1.949581160688787400f, 1.949495558721721500f, + 1.949409885077276500f, + 1.949324139758602700f, 1.949238322768852800f, 1.949152434111181700f, + 1.949066473788747300f, + 1.948980441804710300f, 1.948894338162233900f, 1.948808162864483600f, + 1.948721915914628100f, + 1.948635597315838200f, 1.948549207071288000f, 1.948462745184153400f, + 1.948376211657613500f, + 1.948289606494849800f, 1.948202929699046800f, 1.948116181273391100f, + 1.948029361221072400f, + 1.947942469545282500f, 1.947855506249216700f, 1.947768471336071700f, + 1.947681364809048100f, + 1.947594186671348000f, 1.947506936926177300f, 1.947419615576743600f, + 1.947332222626257500f, + 1.947244758077932200f, 1.947157221934983500f, 1.947069614200629900f, + 1.946981934878092300f, + 1.946894183970594900f, 1.946806361481363500f, 1.946718467413627300f, + 1.946630501770618000f, + 1.946542464555569800f, 1.946454355771719300f, 1.946366175422306500f, + 1.946277923510573200f, + 1.946189600039764300f, 1.946101205013127000f, 1.946012738433911600f, + 1.945924200305370700f, + 1.945835590630759400f, 1.945746909413335900f, 1.945658156656360700f, + 1.945569332363096700f, + 1.945480436536810100f, 1.945391469180769200f, 1.945302430298244900f, + 1.945213319892511200f, + 1.945124137966844200f, 1.945034884524523100f, 1.944945559568829200f, + 1.944856163103046800f, + 1.944766695130463000f, 1.944677155654366900f, 1.944587544678050900f, + 1.944497862204809900f, + 1.944408108237940700f, 1.944318282780743900f, 1.944228385836521700f, + 1.944138417408579400f, + 1.944048377500225100f, 1.943958266114769200f, 1.943868083255524800f, + 1.943777828925807600f, + 1.943687503128936200f, 1.943597105868231500f, 1.943506637147017300f, + 1.943416096968619400f, + 1.943325485336367300f, 1.943234802253592400f, 1.943144047723628400f, + 1.943053221749812400f, + 1.942962324335484100f, 1.942871355483985200f, 1.942780315198660200f, + 1.942689203482856900f, + 1.942598020339924700f, 1.942506765773216500f, 1.942415439786087300f, + 1.942324042381895000f, + 1.942232573564000000f, 1.942141033335765400f, 1.942049421700556600f, + 1.941957738661741900f, + 1.941865984222692900f, 1.941774158386782200f, 1.941682261157386700f, + 1.941590292537884700f, + 1.941498252531658200f, 1.941406141142090600f, 1.941313958372568900f, + 1.941221704226482500f, + 1.941129378707223000f, 1.941036981818185400f, 1.940944513562766300f, + 1.940851973944365900f, + 1.940759362966386600f, 1.940666680632233200f, 1.940573926945313700f, + 1.940481101909038200f, + 1.940388205526819600f, 1.940295237802073500f, 1.940202198738217900f, + 1.940109088338673600f, + 1.940015906606864300f, 1.939922653546215500f, 1.939829329160156500f, + 1.939735933452118000f, + 1.939642466425534300f, 1.939548928083841800f, 1.939455318430479500f, + 1.939361637468889100f, + 1.939267885202515400f, 1.939174061634805000f, 1.939080166769207700f, + 1.938986200609175600f, + 1.938892163158163700f, 1.938798054419629500f, 1.938703874397032800f, + 1.938609623093837000f, + 1.938515300513506700f, 1.938420906659510600f, 1.938326441535318500f, + 1.938231905144404400f, + 1.938137297490243500f, 1.938042618576314400f, 1.937947868406098500f, + 1.937853046983079300f, + 1.937758154310742900f, 1.937663190392578500f, 1.937568155232077600f, + 1.937473048832734500f, + 1.937377871198045600f, 1.937282622331510500f, 1.937187302236631500f, + 1.937091910916912900f, + 1.936996448375861900f, 1.936900914616988900f, 1.936805309643805800f, + 1.936709633459828200f, + 1.936613886068573500f, 1.936518067473562300f, 1.936422177678317300f, + 1.936326216686364400f, + 1.936230184501231500f, 1.936134081126449800f, 1.936037906565552400f, + 1.935941660822075600f, + 1.935845343899558000f, 1.935748955801540800f, 1.935652496531568000f, + 1.935555966093186300f, + 1.935459364489944500f, 1.935362691725394500f, 1.935265947803090900f, + 1.935169132726590500f, + 1.935072246499453000f, 1.934975289125240500f, 1.934878260607517900f, + 1.934781160949852600f, + 1.934683990155814800f, 1.934586748228977100f, 1.934489435172914900f, + 1.934392050991206300f, + 1.934294595687431300f, 1.934197069265173500f, 1.934099471728018700f, + 1.934001803079554700f, + 1.933904063323373300f, 1.933806252463067500f, 1.933708370502233800f, + 1.933610417444471000f, + 1.933512393293380600f, 1.933414298052566600f, 1.933316131725635800f, + 1.933217894316197300f, + 1.933119585827862900f, 1.933021206264247600f, 1.932922755628968100f, + 1.932824233925644300f, + 1.932725641157898600f, 1.932626977329356100f, 1.932528242443643900f, + 1.932429436504392800f, + 1.932330559515235100f, 1.932231611479806800f, 1.932132592401745400f, + 1.932033502284691700f, + 1.931934341132289100f, 1.931835108948183300f, 1.931735805736022800f, + 1.931636431499459000f, + 1.931536986242145200f, 1.931437469967737900f, 1.931337882679895900f, + 1.931238224382281000f, + 1.931138495078557300f, 1.931038694772391200f, 1.930938823467452500f, + 1.930838881167413100f, + 1.930738867875947400f, 1.930638783596732700f, 1.930538628333448900f, + 1.930438402089778200f, + 1.930338104869405900f, 1.930237736676019500f, 1.930137297513309300f, + 1.930036787384968200f, + 1.929936206294691400f, 1.929835554246177400f, 1.929734831243126600f, + 1.929634037289242400f, + 1.929533172388230700f, 1.929432236543799900f, 1.929331229759661200f, + 1.929230152039528500f, + 1.929129003387117800f, 1.929027783806148300f, 1.928926493300341400f, + 1.928825131873421500f, + 1.928723699529115000f, 1.928622196271151800f, 1.928520622103263400f, + 1.928418977029184600f, + 1.928317261052652700f, 1.928215474177407100f, 1.928113616407190600f, + 1.928011687745748300f, + 1.927909688196827400f, 1.927807617764178300f, 1.927705476451554000f, + 1.927603264262709900f, + 1.927500981201404100f, 1.927398627271397000f, 1.927296202476451900f, + 1.927193706820335100f, + 1.927091140306814500f, 1.926988502939661400f, 1.926885794722649600f, + 1.926783015659555300f, + 1.926680165754157500f, 1.926577245010237400f, 1.926474253431579500f, + 1.926371191021970100f, + 1.926268057785198700f, 1.926164853725057300f, 1.926061578845340600f, + 1.925958233149845000f, + 1.925854816642371000f, 1.925751329326720600f, 1.925647771206698600f, + 1.925544142286112800f, + 1.925440442568773000f, 1.925336672058492300f, 1.925232830759086000f, + 1.925128918674371900f, + 1.925024935808170600f, 1.924920882164305300f, 1.924816757746601800f, + 1.924712562558888100f, + 1.924608296604995800f, 1.924503959888757900f, 1.924399552414010700f, + 1.924295074184593000f, + 1.924190525204346300f, 1.924085905477114400f, 1.923981215006744100f, + 1.923876453797084300f, + 1.923771621851986700f, 1.923666719175306100f, 1.923561745770898900f, + 1.923456701642625200f, + 1.923351586794346900f, 1.923246401229928600f, 1.923141144953238300f, + 1.923035817968145300f, + 1.922930420278522500f, 1.922824951888245000f, 1.922719412801190600f, + 1.922613803021239600f, + 1.922508122552275100f, 1.922402371398182600f, 1.922296549562850100f, + 1.922190657050168800f, + 1.922084693864031700f, 1.921978660008334600f, 1.921872555486976700f, + 1.921766380303858500f, + 1.921660134462884100f, 1.921553817967959900f, 1.921447430822994500f, + 1.921340973031900000f, + 1.921234444598590100f, 1.921127845526981600f, 1.921021175820994100f, + 1.920914435484549100f, + 1.920807624521571700f, 1.920700742935988600f, 1.920593790731729600f, + 1.920486767912727300f, + 1.920379674482916500f, 1.920272510446234400f, 1.920165275806621400f, + 1.920057970568020100f, + 1.919950594734376000f, 1.919843148309637000f, 1.919735631297753400f, + 1.919628043702678300f, + 1.919520385528367300f, 1.919412656778779000f, 1.919304857457874200f, + 1.919196987569616200f, + 1.919089047117971100f, 1.918981036106907700f, 1.918872954540397300f, + 1.918764802422413500f, + 1.918656579756932800f, 1.918548286547934400f, 1.918439922799399800f, + 1.918331488515313300f, + 1.918222983699661600f, 1.918114408356434300f, 1.918005762489623400f, + 1.917897046103223200f, + 1.917788259201231200f, 1.917679401787647100f, 1.917570473866473200f, + 1.917461475441714500f, + 1.917352406517378600f, 1.917243267097475700f, 1.917134057186018300f, + 1.917024776787022100f, + 1.916915425904504700f, 1.916806004542486800f, 1.916696512704991500f, + 1.916586950396044400f, + 1.916477317619674100f, 1.916367614379911100f, 1.916257840680788900f, + 1.916147996526343700f, + 1.916038081920614400f, 1.915928096867641800f, 1.915818041371470000f, + 1.915707915436145200f, + 1.915597719065716700f, 1.915487452264236000f, 1.915377115035757200f, + 1.915266707384337200f, + 1.915156229314035200f, 1.915045680828913400f, 1.914935061933036300f, + 1.914824372630470800f, + 1.914713612925287100f, 1.914602782821557000f, 1.914491882323355700f, + 1.914380911434760500f, + 1.914269870159851700f, 1.914158758502712000f, 1.914047576467426500f, + 1.913936324058083100f, + 1.913825001278772100f, 1.913713608133586600f, 1.913602144626622500f, + 1.913490610761977600f, + 1.913379006543752800f, 1.913267331976051400f, 1.913155587062979500f, + 1.913043771808645700f, + 1.912931886217160900f, 1.912819930292639000f, 1.912707904039196300f, + 1.912595807460951500f, + 1.912483640562026200f, 1.912371403346544400f, 1.912259095818632700f, + 1.912146717982420500f, + 1.912034269842039600f, 1.911921751401624200f, 1.911809162665311500f, + 1.911696503637241100f, + 1.911583774321554700f, 1.911470974722397500f, 1.911358104843916500f, + 1.911245164690262000f, + 1.911132154265586100f, 1.911019073574044200f, 1.910905922619793800f, + 1.910792701406995000f, + 1.910679409939810600f, 1.910566048222406300f, 1.910452616258949900f, + 1.910339114053611900f, + 1.910225541610565800f, 1.910111898933986900f, 1.909998186028053700f, + 1.909884402896947100f, + 1.909770549544850500f, 1.909656625975950200f, 1.909542632194434700f, + 1.909428568204495100f, + 1.909314434010325400f, 1.909200229616121700f, 1.909085955026083200f, + 1.908971610244411600f, + 1.908857195275310800f, 1.908742710122987700f, 1.908628154791651300f, + 1.908513529285513500f, + 1.908398833608789100f, 1.908284067765694900f, 1.908169231760450400f, + 1.908054325597278200f, + 1.907939349280402400f, 1.907824302814050900f, 1.907709186202453600f, + 1.907593999449842800f, + 1.907478742560453600f, 1.907363415538523700f, 1.907248018388293400f, + 1.907132551114005600f, + 1.907017013719905600f, 1.906901406210241200f, 1.906785728589263300f, + 1.906669980861224900f, + 1.906554163030381500f, 1.906438275100991600f, 1.906322317077316300f, + 1.906206288963618700f, + 1.906090190764164700f, 1.905974022483223300f, 1.905857784125065500f, + 1.905741475693964800f, + 1.905625097194197900f, 1.905508648630043700f, 1.905392130005783400f, + 1.905275541325701400f, + 1.905158882594083900f, 1.905042153815220700f, 1.904925354993402900f, + 1.904808486132925300f, + 1.904691547238084800f, 1.904574538313180700f, 1.904457459362515200f, + 1.904340310390393100f, + 1.904223091401121600f, 1.904105802399010300f, 1.903988443388371600f, + 1.903871014373520700f, + 1.903753515358774800f, 1.903635946348454500f, 1.903518307346881800f, + 1.903400598358382600f, + 1.903282819387284200f, 1.903164970437917400f, 1.903047051514615000f, + 1.902929062621712600f, + 1.902811003763547900f, 1.902692874944462300f, 1.902574676168798700f, + 1.902456407440902700f, + 1.902338068765123200f, 1.902219660145810800f, 1.902101181587319000f, + 1.901982633094004200f, + 1.901864014670225000f, 1.901745326320342500f, 1.901626568048721000f, + 1.901507739859726200f, + 1.901388841757727600f, 1.901269873747096600f, 1.901150835832207100f, + 1.901031728017436300f, + 1.900912550307162700f, 1.900793302705768900f, 1.900673985217638900f, + 1.900554597847159400f, + 1.900435140598720500f, 1.900315613476714100f, 1.900196016485534700f, + 1.900076349629579600f, + 1.899956612913248800f, 1.899836806340944300f, 1.899716929917071500f, + 1.899596983646037600f, + 1.899476967532252900f, 1.899356881580129800f, 1.899236725794083600f, + 1.899116500178532200f, + 1.898996204737895900f, 1.898875839476597700f, 1.898755404399062900f, + 1.898634899509719500f, + 1.898514324812998300f, 1.898393680313332600f, 1.898272966015157800f, + 1.898152181922912600f, + 1.898031328041037700f, 1.897910404373976500f, 1.897789410926175000f, + 1.897668347702081900f, + 1.897547214706148300f, 1.897426011942827900f, 1.897304739416577200f, + 1.897183397131854600f, + 1.897061985093121800f, 1.896940503304842800f, 1.896818951771484000f, + 1.896697330497514800f, + 1.896575639487406300f, 1.896453878745633100f, 1.896332048276672100f, + 1.896210148085002400f, + 1.896088178175106200f, 1.895966138551467700f, 1.895844029218574100f, + 1.895721850180915000f, + 1.895599601442982600f, 1.895477283009271400f, 1.895354894884279100f, + 1.895232437072505300f, + 1.895109909578452500f, 1.894987312406625700f, 1.894864645561532100f, + 1.894741909047682500f, + 1.894619102869589100f, 1.894496227031767100f, 1.894373281538734400f, + 1.894250266395011600f, + 1.894127181605121100f, 1.894004027173588700f, 1.893880803104942600f, + 1.893757509403713100f, + 1.893634146074433500f, 1.893510713121639300f, 1.893387210549869000f, + 1.893263638363663400f, + 1.893139996567565900f, 1.893016285166122500f, 1.892892504163881600f, + 1.892768653565394300f, + 1.892644733375214300f, 1.892520743597897700f, 1.892396684238003300f, + 1.892272555300092300f, + 1.892148356788728700f, 1.892024088708479200f, 1.891899751063912200f, + 1.891775343859599400f, + 1.891650867100115300f, 1.891526320790036100f, 1.891401704933941100f, + 1.891277019536412400f, + 1.891152264602033800f, 1.891027440135392600f, 1.890902546141078000f, + 1.890777582623682300f, + 1.890652549587799700f, 1.890527447038027300f, 1.890402274978965100f, + 1.890277033415215200f, + 1.890151722351382200f, 1.890026341792073500f, 1.889900891741899100f, + 1.889775372205471300f, + 1.889649783187405100f, 1.889524124692318200f, 1.889398396724830500f, + 1.889272599289564900f, + 1.889146732391146400f, 1.889020796034202700f, 1.888894790223364600f, + 1.888768714963264400f, + 1.888642570258537700f, 1.888516356113822700f, 1.888390072533759700f, + 1.888263719522991900f, + 1.888137297086165000f, 1.888010805227927000f, 1.887884243952928600f, + 1.887757613265823400f, + 1.887630913171267000f, 1.887504143673917700f, 1.887377304778437000f, + 1.887250396489487800f, + 1.887123418811736500f, 1.886996371749851700f, 1.886869255308504200f, + 1.886742069492368000f, + 1.886614814306119400f, 1.886487489754437300f, 1.886360095842002600f, + 1.886232632573499700f, + 1.886105099953614900f, 1.885977497987037000f, 1.885849826678457800f, + 1.885722086032571200f, + 1.885594276054074300f, 1.885466396747665700f, 1.885338448118047700f, + 1.885210430169924200f, + 1.885082342908002400f, 1.884954186336991400f, 1.884825960461603100f, + 1.884697665286552400f, + 1.884569300816556000f, 1.884440867056333700f, 1.884312364010607600f, + 1.884183791684102400f, + 1.884055150081545200f, 1.883926439207665800f, 1.883797659067196800f, + 1.883668809664872600f, + 1.883539891005431100f, 1.883410903093611900f, 1.883281845934157800f, + 1.883152719531813800f, + 1.883023523891327300f, 1.882894259017448900f, 1.882764924914930700f, + 1.882635521588528400f, + 1.882506049042999700f, 1.882376507283104900f, 1.882246896313606800f, + 1.882117216139270700f, + 1.881987466764865100f, 1.881857648195159900f, 1.881727760434928500f, + 1.881597803488946500f, + 1.881467777361992100f, 1.881337682058845700f, 1.881207517584290600f, + 1.881077283943112900f, + 1.880946981140100500f, 1.880816609180044700f, 1.880686168067738500f, + 1.880555657807977800f, + 1.880425078405561600f, 1.880294429865290600f, 1.880163712191968300f, + 1.880032925390400900f, + 1.879902069465397200f, 1.879771144421768200f, 1.879640150264327600f, + 1.879509086997891900f, + 1.879377954627279700f, 1.879246753157312700f, 1.879115482592814500f, + 1.878984142938611600f, + 1.878852734199532900f, 1.878721256380410100f, 1.878589709486077300f, + 1.878458093521370800f, + 1.878326408491130200f, 1.878194654400196600f, 1.878062831253414900f, + 1.877930939055631100f, + 1.877798977811695200f, 1.877666947526458700f, 1.877534848204775800f, + 1.877402679851504000f, + 1.877270442471502100f, 1.877138136069632400f, 1.877005760650759500f, + 1.876873316219750200f, + 1.876740802781474500f, 1.876608220340804100f, 1.876475568902614000f, + 1.876342848471781200f, + 1.876210059053185600f, 1.876077200651709500f, 1.875944273272237800f, + 1.875811276919657500f, + 1.875678211598858800f, 1.875545077314734000f, 1.875411874072178100f, + 1.875278601876088700f, + 1.875145260731365700f, 1.875011850642911600f, 1.874878371615631900f, + 1.874744823654434000f, + 1.874611206764227800f, 1.874477520949926500f, 1.874343766216444800f, + 1.874209942568701100f, + 1.874076050011615400f, 1.873942088550110400f, 1.873808058189111700f, + 1.873673958933546900f, + 1.873539790788347100f, 1.873405553758444600f, 1.873271247848775400f, + 1.873136873064277000f, + 1.873002429409890600f, 1.872867916890558900f, 1.872733335511227700f, + 1.872598685276845000f, + 1.872463966192361900f, 1.872329178262731200f, 1.872194321492908700f, + 1.872059395887852900f, + 1.871924401452524700f, 1.871789338191887100f, 1.871654206110906500f, + 1.871519005214550700f, + 1.871383735507791100f, 1.871248396995601300f, 1.871112989682956800f, + 1.870977513574836500f, + 1.870841968676221400f, 1.870706354992095000f, 1.870570672527443600f, + 1.870434921287255700f, + 1.870299101276522400f, 1.870163212500237900f, 1.870027254963397800f, + 1.869891228671001200f, + 1.869755133628049600f, 1.869618969839546500f, 1.869482737310498100f, + 1.869346436045913800f, + 1.869210066050804600f, 1.869073627330184700f, 1.868937119889070300f, + 1.868800543732480600f, + 1.868663898865437200f, 1.868527185292963700f, 1.868390403020087100f, + 1.868253552051836200f, + 1.868116632393243000f, 1.867979644049341200f, 1.867842587025167800f, + 1.867705461325761800f, + 1.867568266956164800f, 1.867431003921421500f, 1.867293672226578300f, + 1.867156271876684500f, + 1.867018802876792200f, 1.866881265231955500f, 1.866743658947231300f, + 1.866605984027679000f, + 1.866468240478360600f, 1.866330428304340300f, 1.866192547510685300f, + 1.866054598102465000f, + 1.865916580084751500f, 1.865778493462619100f, 1.865640338241145100f, + 1.865502114425408900f, + 1.865363822020492700f, 1.865225461031480900f, 1.865087031463460900f, + 1.864948533321522300f, + 1.864809966610757400f, 1.864671331336260600f, 1.864532627503129100f, + 1.864393855116463200f, + 1.864255014181364500f, 1.864116104702938000f, 1.863977126686291200f, + 1.863838080136534000f, + 1.863698965058778300f, 1.863559781458139300f, 1.863420529339734100f, + 1.863281208708683000f, + 1.863141819570107900f, 1.863002361929134500f, 1.862862835790889400f, + 1.862723241160503300f, + 1.862583578043108100f, 1.862443846443839300f, 1.862304046367834200f, + 1.862164177820232700f, + 1.862024240806177800f, 1.861884235330814300f, 1.861744161399289600f, + 1.861604019016754200f, + 1.861463808188360500f, 1.861323528919263800f, 1.861183181214621600f, + 1.861042765079594200f, + 1.860902280519344500f, 1.860761727539037300f, 1.860621106143840500f, + 1.860480416338924600f, + 1.860339658129461800f, 1.860198831520627900f, 1.860057936517600700f, + 1.859916973125560000f, + 1.859775941349689000f, 1.859634841195173100f, 1.859493672667199800f, + 1.859352435770959900f, + 1.859211130511645900f, 1.859069756894453400f, 1.858928314924580300f, + 1.858786804607227100f, + 1.858645225947596300f, 1.858503578950893900f, 1.858361863622327400f, + 1.858220079967107600f, + 1.858078227990447300f, 1.857936307697561900f, 1.857794319093669900f, + 1.857652262183991000f, + 1.857510136973749000f, 1.857367943468169100f, 1.857225681672479300f, + 1.857083351591910300f, + 1.856940953231694900f, 1.856798486597069000f, 1.856655951693270600f, + 1.856513348525540300f, + 1.856370677099121100f, 1.856227937419258700f, 1.856085129491201100f, + 1.855942253320199200f, + 1.855799308911506100f, 1.855656296270377300f, 1.855513215402071000f, + 1.855370066311848000f, + 1.855226849004971500f, 1.855083563486706900f, 1.854940209762322700f, + 1.854796787837089500f, + 1.854653297716280400f, 1.854509739405171300f, 1.854366112909040300f, + 1.854222418233168400f, + 1.854078655382838300f, 1.853934824363336200f, 1.853790925179950500f, + 1.853646957837971500f, + 1.853502922342692600f, 1.853358818699409900f, 1.853214646913421200f, + 1.853070406990027500f, + 1.852926098934532200f, 1.852781722752241000f, 1.852637278448462200f, + 1.852492766028506400f, + 1.852348185497687300f, 1.852203536861320600f, 1.852058820124724300f, + 1.851914035293219700f, + 1.851769182372129600f, 1.851624261366780400f, 1.851479272282500000f, + 1.851334215124619300f, + 1.851189089898471800f, 1.851043896609393400f, 1.850898635262721900f, + 1.850753305863798800f, + 1.850607908417967200f, 1.850462442930572900f, 1.850316909406964200f, + 1.850171307852492200f, + 1.850025638272510000f, 1.849879900672373600f, 1.849734095057441200f, + 1.849588221433073700f, + 1.849442279804634600f, 1.849296270177489800f, 1.849150192557007300f, + 1.849004046948558200f, + 1.848857833357515900f, 1.848711551789256300f, 1.848565202249157400f, + 1.848418784742600400f, + 1.848272299274968500f, 1.848125745851647800f, 1.847979124478026100f, + 1.847832435159495000f, + 1.847685677901447200f, 1.847538852709279100f, 1.847391959588388300f, + 1.847244998544176300f, + 1.847097969582046200f, 1.846950872707404000f, 1.846803707925657600f, + 1.846656475242218300f, + 1.846509174662499300f, 1.846361806191916000f, 1.846214369835887500f, + 1.846066865599834000f, + 1.845919293489179000f, 1.845771653509348200f, 1.845623945665770100f, + 1.845476169963875500f, + 1.845328326409097400f, 1.845180415006871800f, 1.845032435762637100f, + 1.844884388681833800f, + 1.844736273769905300f, 1.844588091032297400f, 1.844439840474458200f, + 1.844291522101838800f, + 1.844143135919891900f, 1.843994681934073600f, 1.843846160149842200f, + 1.843697570572658200f, + 1.843548913207985000f, 1.843400188061288000f, 1.843251395138035800f, + 1.843102534443698900f, + 1.842953605983750400f, 1.842804609763666100f, 1.842655545788924000f, + 1.842506414065004900f, + 1.842357214597392100f, 1.842207947391570900f, 1.842058612453029600f, + 1.841909209787258900f, + 1.841759739399751800f, 1.841610201296003800f, 1.841460595481513100f, + 1.841310921961780500f, + 1.841161180742308500f, 1.841011371828603200f, 1.840861495226172600f, + 1.840711550940526700f, + 1.840561538977179200f, 1.840411459341645400f, 1.840261312039443100f, + 1.840111097076092800f, + 1.839960814457117600f, 1.839810464188043100f, 1.839660046274397100f, + 1.839509560721709800f, + 1.839359007535514400f, 1.839208386721346500f, 1.839057698284743500f, + 1.838906942231246100f, + 1.838756118566397200f, 1.838605227295741800f, 1.838454268424828400f, + 1.838303241959206700f, + 1.838152147904429800f, 1.838000986266052900f, 1.837849757049633900f, + 1.837698460260732900f, + 1.837547095904912700f, 1.837395663987738700f, 1.837244164514778600f, + 1.837092597491602100f, + 1.836940962923782700f, 1.836789260816895000f, 1.836637491176516600f, + 1.836485654008228200f, + 1.836333749317611700f, 1.836181777110252900f, 1.836029737391738700f, + 1.835877630167659800f, + 1.835725455443608200f, 1.835573213225179400f, 1.835420903517970500f, + 1.835268526327581900f, + 1.835116081659615700f, 1.834963569519677100f, 1.834810989913373500f, + 1.834658342846314800f, + 1.834505628324113200f, 1.834352846352383700f, 1.834199996936744000f, + 1.834047080082813300f, + 1.833894095796214400f, 1.833741044082571900f, 1.833587924947513100f, + 1.833434738396668000f, + 1.833281484435668400f, 1.833128163070149300f, 1.832974774305747600f, + 1.832821318148103500f, + 1.832667794602858400f, 1.832514203675657600f, 1.832360545372147900f, + 1.832206819697979000f, + 1.832053026658802700f, 1.831899166260273700f, 1.831745238508049300f, + 1.831591243407788300f, + 1.831437180965153100f, 1.831283051185808300f, 1.831128854075420500f, + 1.830974589639659000f, + 1.830820257884196100f, 1.830665858814705600f, 1.830511392436864800f, + 1.830356858756352800f, + 1.830202257778851300f, 1.830047589510044500f, 1.829892853955619200f, + 1.829738051121264600f, + 1.829583181012672400f, 1.829428243635536500f, 1.829273238995553700f, + 1.829118167098423100f, + 1.828963027949846100f, 1.828807821555527000f, 1.828652547921171900f, + 1.828497207052490100f, + 1.828341798955192900f, 1.828186323634994200f, 1.828030781097610400f, + 1.827875171348760400f, + 1.827719494394165500f, 1.827563750239549400f, 1.827407938890638600f, + 1.827252060353161500f, + 1.827096114632849700f, 1.826940101735436500f, 1.826784021666658400f, + 1.826627874432253700f, + 1.826471660037963800f, 1.826315378489531800f, 1.826159029792704400f, + 1.826002613953229500f, + 1.825846130976858100f, 1.825689580869344100f, 1.825532963636443000f, + 1.825376279283913200f, + 1.825219527817515800f, 1.825062709243013800f, 1.824905823566173000f, + 1.824748870792761900f, + 1.824591850928550800f, 1.824434763979313300f, 1.824277609950824700f, + 1.824120388848863300f, + 1.823963100679209600f, 1.823805745447646600f, 1.823648323159960100f, + 1.823490833821937600f, + 1.823333277439369600f, 1.823175654018049300f, 1.823017963563772000f, + 1.822860206082335300f, + 1.822702381579539800f, 1.822544490061187800f, 1.822386531533084900f, + 1.822228506001038800f, + 1.822070413470859600f, 1.821912253948359700f, 1.821754027439354400f, + 1.821595733949661100f, + 1.821437373485099900f, 1.821278946051493100f, 1.821120451654665700f, + 1.820961890300445400f, + 1.820803261994661500f, 1.820644566743146800f, 1.820485804551735800f, + 1.820326975426265600f, + 1.820168079372576300f, 1.820009116396509800f, 1.819850086503910700f, + 1.819690989700625900f, + 1.819531825992505500f, 1.819372595385401000f, 1.819213297885166900f, + 1.819053933497660300f, + 1.818894502228740600f, 1.818735004084269600f, 1.818575439070111200f, + 1.818415807192132600f, + 1.818256108456203000f, 1.818096342868193800f, 1.817936510433979300f, + 1.817776611159436000f, + 1.817616645050443000f, 1.817456612112881900f, 1.817296512352636300f, + 1.817136345775592900f, + 1.816976112387640700f, 1.816815812194670700f, 1.816655445202576700f, + 1.816495011417255300f, + 1.816334510844604700f, 1.816173943490526400f, 1.816013309360923900f, + 1.815852608461703300f, + 1.815691840798773000f, 1.815531006378043900f, 1.815370105205429600f, + 1.815209137286846200f, + 1.815048102628211500f, 1.814887001235446600f, 1.814725833114474700f, + 1.814564598271221300f, + 1.814403296711615000f, 1.814241928441585800f, 1.814080493467067300f, + 1.813918991793994900f, + 1.813757423428306000f, 1.813595788375941700f, 1.813434086642844400f, + 1.813272318234959700f, + 1.813110483158235400f, 1.812948581418621500f, 1.812786613022070700f, + 1.812624577974538000f, + 1.812462476281981200f, 1.812300307950360300f, 1.812138072985637800f, + 1.811975771393778300f, + 1.811813403180749300f, 1.811650968352521000f, 1.811488466915065000f, + 1.811325898874356800f, + 1.811163264236372900f, 1.811000563007093100f, 1.810837795192499400f, + 1.810674960798576600f, + 1.810512059831311400f, 1.810349092296693400f, 1.810186058200714100f, + 1.810022957549368000f, + 1.809859790348652200f, 1.809696556604565300f, 1.809533256323109200f, + 1.809369889510288100f, + 1.809206456172108200f, 1.809042956314578900f, 1.808879389943711200f, + 1.808715757065519200f, + 1.808552057686019200f, 1.808388291811230000f, 1.808224459447172800f, + 1.808060560599871200f, + 1.807896595275351200f, 1.807732563479641300f, 1.807568465218772900f, + 1.807404300498778800f, + 1.807240069325695400f, 1.807075771705560800f, 1.806911407644415700f, + 1.806746977148303300f, + 1.806582480223269500f, 1.806417916875362000f, 1.806253287110631600f, + 1.806088590935131000f, + 1.805923828354915900f, 1.805758999376044100f, 1.805594104004575800f, + 1.805429142246573600f, + 1.805264114108102900f, 1.805099019595231200f, 1.804933858714028700f, + 1.804768631470567500f, + 1.804603337870923000f, 1.804437977921172300f, 1.804272551627395400f, + 1.804107058995674500f, + 1.803941500032094200f, 1.803775874742741500f, 1.803610183133706400f, + 1.803444425211080400f, + 1.803278600980958300f, 1.803112710449436900f, 1.802946753622615400f, + 1.802780730506595700f, + 1.802614641107481900f, 1.802448485431380900f, 1.802282263484401300f, + 1.802115975272655000f, + 1.801949620802255600f, 1.801783200079319900f, 1.801616713109966300f, + 1.801450159900316300f, + 1.801283540456493700f, 1.801116854784624400f, 1.800950102890836800f, + 1.800783284781262200f, + 1.800616400462033800f, 1.800449449939287800f, 1.800282433219162000f, + 1.800115350307797600f, + 1.799948201211337500f, 1.799780985935927300f, 1.799613704487715200f, + 1.799446356872851400f, + 1.799278943097489100f, 1.799111463167783400f, 1.798943917089892000f, + 1.798776304869975200f, + 1.798608626514195800f, 1.798440882028718500f, 1.798273071419711000f, + 1.798105194693343500f, + 1.797937251855787700f, 1.797769242913218800f, 1.797601167871813800f, + 1.797433026737752700f, + 1.797264819517217200f, 1.797096546216391900f, 1.796928206841463800f, + 1.796759801398622100f, + 1.796591329894058800f, 1.796422792333968000f, 1.796254188724546500f, + 1.796085519071992900f, + 1.795916783382509200f, 1.795747981662299200f, 1.795579113917569200f, + 1.795410180154527900f, + 1.795241180379386800f, 1.795072114598359200f, 1.794902982817661500f, + 1.794733785043511900f, + 1.794564521282131300f, 1.794395191539743400f, 1.794225795822573600f, + 1.794056334136850300f, + 1.793886806488804100f, 1.793717212884667900f, 1.793547553330677300f, + 1.793377827833070100f, + 1.793208036398086900f, 1.793038179031970000f, 1.792868255740965000f, + 1.792698266531319400f, + 1.792528211409282900f, 1.792358090381108300f, 1.792187903453050100f, + 1.792017650631366100f, + 1.791847331922315600f, 1.791676947332161000f, 1.791506496867166600f, + 1.791335980533599300f, + 1.791165398337728900f, 1.790994750285827000f, 1.790824036384167900f, + 1.790653256639028100f, + 1.790482411056686800f, 1.790311499643425500f, 1.790140522405528200f, + 1.789969479349281100f, + 1.789798370480973000f, 1.789627195806895200f, 1.789455955333341100f, + 1.789284649066606800f, + 1.789113277012990900f, 1.788941839178794100f, 1.788770335570319700f, + 1.788598766193873600f, + 1.788427131055763600f, 1.788255430162300400f, 1.788083663519796800f, + 1.787911831134568300f, + 1.787739933012932900f, 1.787567969161210300f, 1.787395939585723500f, + 1.787223844292797500f, + 1.787051683288759500f, 1.786879456579939700f, 1.786707164172670200f, + 1.786534806073285700f, + 1.786362382288123400f, 1.786189892823522700f, 1.786017337685825700f, + 1.785844716881376700f, + 1.785672030416522300f, 1.785499278297612000f, 1.785326460530997300f, + 1.785153577123032000f, + 1.784980628080072900f, 1.784807613408478300f, 1.784634533114609800f, + 1.784461387204831400f, + 1.784288175685508700f, 1.784114898563010200f, 1.783941555843707100f, + 1.783768147533972200f, + 1.783594673640181800f, 1.783421134168713800f, 1.783247529125948900f, + 1.783073858518269700f, + 1.782900122352062000f, 1.782726320633713200f, 1.782552453369613800f, + 1.782378520566156200f, + 1.782204522229735600f, 1.782030458366749200f, 1.781856328983596900f, + 1.781682134086680900f, + 1.781507873682406200f, 1.781333547777179200f, 1.781159156377410100f, + 1.780984699489510200f, + 1.780810177119894100f, 1.780635589274978600f, 1.780460935961182300f, + 1.780286217184927000f, + 1.780111432952636600f, 1.779936583270737400f, 1.779761668145658300f, + 1.779586687583830200f, + 1.779411641591686500f, 1.779236530175663600f, 1.779061353342199500f, + 1.778886111097735000f, + 1.778710803448713400f, 1.778535430401580100f, 1.778359991962783000f, + 1.778184488138772900f, + 1.778008918936002000f, 1.777833284360925900f, 1.777657584420002000f, + 1.777481819119690200f, + 1.777305988466453000f, 1.777130092466755200f, 1.776954131127064200f, + 1.776778104453849100f, + 1.776602012453582400f, 1.776425855132738100f, 1.776249632497793200f, + 1.776073344555227000f, + 1.775896991311520800f, 1.775720572773158900f, 1.775544088946627600f, + 1.775367539838415700f, + 1.775190925455014400f, 1.775014245802917200f, 1.774837500888620400f, + 1.774660690718622000f, + 1.774483815299423100f, 1.774306874637527000f, 1.774129868739439100f, + 1.773952797611667100f, + 1.773775661260722100f, 1.773598459693116500f, 1.773421192915365400f, + 1.773243860933986400f, + 1.773066463755499800f, 1.772889001386427800f, 1.772711473833295200f, + 1.772533881102629000f, + 1.772356223200959100f, 1.772178500134817100f, 1.772000711910737700f, + 1.771822858535257600f, + 1.771644940014915700f, 1.771466956356254000f, 1.771288907565816000f, + 1.771110793650148500f, + 1.770932614615799800f, 1.770754370469321400f, 1.770576061217266500f, + 1.770397686866191300f, + 1.770219247422653700f, 1.770040742893215000f, 1.769862173284438000f, + 1.769683538602888000f, + 1.769504838855133100f, 1.769326074047743700f, 1.769147244187292200f, + 1.768968349280353800f, + 1.768789389333506000f, 1.768610364353328600f, 1.768431274346403900f, + 1.768252119319316400f, + 1.768072899278653200f, 1.767893614231003800f, 1.767714264182959500f, + 1.767534849141115100f, + 1.767355369112067100f, 1.767175824102414000f, 1.766996214118757800f, + 1.766816539167701800f, + 1.766636799255852300f, 1.766456994389817600f, 1.766277124576209000f, + 1.766097189821639300f, + 1.765917190132724600f, 1.765737125516083000f, 1.765556995978334800f, + 1.765376801526102700f, + 1.765196542166012100f, 1.765016217904690900f, 1.764835828748768400f, + 1.764655374704877700f, + 1.764474855779653200f, 1.764294271979732100f, 1.764113623311754000f, + 1.763932909782361100f, + 1.763752131398197200f, 1.763571288165909400f, 1.763390380092146400f, + 1.763209407183560200f, + 1.763028369446804500f, 1.762847266888535100f, 1.762666099515411100f, + 1.762484867334093400f, + 1.762303570351245300f, 1.762122208573532600f, 1.761940782007623600f, + 1.761759290660188400f, + 1.761577734537900500f, 1.761396113647435000f, 1.761214427995469100f, + 1.761032677588683800f, + 1.760850862433760700f, 1.760668982537384900f, 1.760487037906243600f, + 1.760305028547026500f, + 1.760122954466425600f, 1.759940815671135100f, 1.759758612167851700f, + 1.759576343963274600f, + 1.759394011064105100f, 1.759211613477047200f, 1.759029151208807400f, + 1.758846624266093800f, + 1.758664032655617500f, 1.758481376384092500f, 1.758298655458233600f, + 1.758115869884759700f, + 1.757933019670390800f, 1.757750104821850000f, 1.757567125345862700f, + 1.757384081249156100f, + 1.757200972538460700f, 1.757017799220508500f, 1.756834561302034400f, + 1.756651258789775800f, + 1.756467891690471700f, 1.756284460010864200f, 1.756100963757697900f, + 1.755917402937718900f, + 1.755733777557676500f, 1.755550087624322000f, 1.755366333144409200f, + 1.755182514124693900f, + 1.754998630571935200f, 1.754814682492893600f, 1.754630669894332600f, + 1.754446592783017500f, + 1.754262451165716300f, 1.754078245049199600f, 1.753893974440240000f, + 1.753709639345612600f, + 1.753525239772095100f, 1.753340775726466700f, 1.753156247215510400f, + 1.752971654246010300f, + 1.752786996824753600f, 1.752602274958529500f, 1.752417488654129700f, + 1.752232637918348200f, + 1.752047722757981600f, 1.751862743179828600f, 1.751677699190690400f, + 1.751492590797370600f, + 1.751307418006674800f, 1.751122180825411800f, 1.750936879260391700f, + 1.750751513318427700f, + 1.750566083006335600f, 1.750380588330932500f, 1.750195029299038900f, + 1.750009405917477100f, + 1.749823718193071800f, 1.749637966132650900f, 1.749452149743043100f, + 1.749266269031080700f, + 1.749080324003598100f, 1.748894314667431800f, 1.748708241029421000f, + 1.748522103096407300f, + 1.748335900875233900f, 1.748149634372747200f, 1.747963303595795500f, + 1.747776908551230000f, + 1.747590449245904000f, 1.747403925686672500f, 1.747217337880393900f, + 1.747030685833928200f, + 1.746843969554138200f, 1.746657189047889200f, 1.746470344322048200f, + 1.746283435383485100f, + 1.746096462239072000f, 1.745909424895683200f, 1.745722323360195900f, + 1.745535157639489100f, + 1.745347927740444200f, 1.745160633669945200f, 1.744973275434878300f, + 1.744785853042132300f, + 1.744598366498598200f, 1.744410815811169300f, 1.744223200986741100f, + 1.744035522032211900f, + 1.743847778954482000f, 1.743659971760454200f, 1.743472100457033700f, + 1.743284165051127700f, + 1.743096165549646400f, 1.742908101959502100f, 1.742719974287608900f, + 1.742531782540884100f, + 1.742343526726246800f, 1.742155206850618800f, 1.741966822920923800f, + 1.741778374944088000f, + 1.741589862927040800f, 1.741401286876712800f, 1.741212646800037300f, + 1.741023942703950200f, + 1.740835174595389600f, 1.740646342481295900f, 1.740457446368612000f, + 1.740268486264283200f, + 1.740079462175256900f, 1.739890374108482600f, 1.739701222070913200f, + 1.739512006069502800f, + 1.739322726111208500f, 1.739133382202989500f, 1.738943974351807600f, + 1.738754502564626700f, + 1.738564966848413100f, 1.738375367210135400f, 1.738185703656765200f, + 1.737995976195275000f, + 1.737806184832640900f, 1.737616329575841300f, 1.737426410431856200f, + 1.737236427407668800f, + 1.737046380510263800f, 1.736856269746629000f, 1.736666095123754000f, + 1.736475856648631400f, + 1.736285554328254900f, 1.736095188169622500f, 1.735904758179732400f, + 1.735714264365586700f, + 1.735523706734189100f, 1.735333085292545900f, 1.735142400047666100f, + 1.734951651006560100f, + 1.734760838176241400f, 1.734569961563725600f, 1.734379021176030600f, + 1.734188017020177100f, + 1.733996949103187500f, 1.733805817432086900f, 1.733614622013902600f, + 1.733423362855664100f, + 1.733232039964403900f, 1.733040653347156300f, 1.732849203010957900f, + 1.732657688962847600f, + 1.732466111209867200f, 1.732274469759060200f, 1.732082764617472800f, + 1.731890995792153600f, + 1.731699163290153100f, 1.731507267118524500f, 1.731315307284323700f, + 1.731123283794607800f, + 1.730931196656437600f, 1.730739045876875200f, 1.730546831462985500f, + 1.730354553421835600f, + 1.730162211760495300f, 1.729969806486036500f, 1.729777337605533000f, + 1.729584805126061400f, + 1.729392209054700900f, 1.729199549398532400f, 1.729006826164639400f, + 1.728814039360108100f, + 1.728621188992026400f, 1.728428275067485100f, 1.728235297593577100f, + 1.728042256577397200f, + 1.727849152026043500f, 1.727655983946615700f, 1.727462752346216000f, + 1.727269457231948900f, + 1.727076098610921500f, 1.726882676490243000f, 1.726689190877025000f, + 1.726495641778381200f, + 1.726302029201427900f, 1.726108353153283900f, 1.725914613641069900f, + 1.725720810671909300f, + 1.725526944252927700f, 1.725333014391252900f, 1.725139021094015200f, + 1.724944964368347000f, + 1.724750844221383500f, 1.724556660660261800f, 1.724362413692121400f, + 1.724168103324104300f, + 1.723973729563354600f, 1.723779292417019200f, 1.723584791892246700f, + 1.723390227996188600f, + 1.723195600735998100f, 1.723000910118831300f, 1.722806156151846400f, + 1.722611338842204000f, + 1.722416458197066900f, 1.722221514223600100f, 1.722026506928971500f, + 1.721831436320350800f, + 1.721636302404910200f, 1.721441105189824000f, 1.721245844682269600f, + 1.721050520889425600f, + 1.720855133818473900f, 1.720659683476597900f, 1.720464169870984200f, + 1.720268593008821100f, + 1.720072952897299100f, 1.719877249543611900f, 1.719681482954954500f, + 1.719485653138524800f, + 1.719289760101522900f, 1.719093803851151400f, 1.718897784394614900f, + 1.718701701739120400f, + 1.718505555891877400f, 1.718309346860097600f, 1.718113074650995200f, + 1.717916739271786500f, + 1.717720340729689700f, 1.717523879031926500f, 1.717327354185719900f, + 1.717130766198295700f, + 1.716934115076881800f, 1.716737400828708400f, 1.716540623461008100f, + 1.716343782981016200f, + 1.716146879395969500f, 1.715949912713108100f, 1.715752882939673300f, + 1.715555790082909900f, + 1.715358634150064000f, 1.715161415148384500f, 1.714964133085122900f, + 1.714766787967532600f, + 1.714569379802868900f, 1.714371908598390800f, 1.714174374361358000f, + 1.713976777099033700f, + 1.713779116818682900f, 1.713581393527573000f, 1.713383607232973600f, + 1.713185757942156800f, + 1.712987845662396800f, 1.712789870400970700f, 1.712591832165157200f, + 1.712393730962237500f, + 1.712195566799495500f, 1.711997339684216700f, 1.711799049623689900f, + 1.711600696625205300f, + 1.711402280696055800f, 1.711203801843536700f, 1.711005260074945200f, + 1.710806655397581600f, + 1.710607987818747700f, 1.710409257345748100f, 1.710210463985889500f, + 1.710011607746480600f, + 1.709812688634833300f, 1.709613706658261100f, 1.709414661824080000f, + 1.709215554139608400f, + 1.709016383612166600f, 1.708817150249077900f, 1.708617854057667300f, + 1.708418495045262300f, + 1.708219073219193300f, 1.708019588586791700f, 1.707820041155392500f, + 1.707620430932332400f, + 1.707420757924950300f, 1.707221022140587900f, 1.707021223586588700f, + 1.706821362270298600f, + 1.706621438199066300f, 1.706421451380242000f, 1.706221401821179200f, + 1.706021289529232800f, + 1.705821114511760300f, 1.705620876776121600f, 1.705420576329679000f, + 1.705220213179796900f, + 1.705019787333842200f, 1.704819298799183700f, 1.704618747583193100f, + 1.704418133693243800f, + 1.704217457136711900f, 1.704016717920976000f, 1.703815916053416300f, + 1.703615051541415900f, + 1.703414124392360000f, 1.703213134613636100f, 1.703012082212634000f, + 1.702810967196746000f, + 1.702609789573366300f, 1.702408549349891500f, 1.702207246533721000f, + 1.702005881132255800f, + 1.701804453152900000f, 1.701602962603059100f, 1.701401409490141300f, + 1.701199793821557300f, + 1.700998115604720000f, 1.700796374847044300f, 1.700594571555948100f, + 1.700392705738850400f, + 1.700190777403173700f, 1.699988786556342300f, 1.699786733205783000f, + 1.699584617358924400f, + 1.699382439023197700f, 1.699180198206036600f, 1.698977894914877100f, + 1.698775529157156700f, + 1.698573100940316400f, 1.698370610271798800f, 1.698168057159048700f, + 1.697965441609513300f, + 1.697762763630642700f, 1.697560023229888200f, 1.697357220414704500f, + 1.697154355192547900f, + 1.696951427570877000f, 1.696748437557152900f, 1.696545385158839200f, + 1.696342270383401200f, + 1.696139093238307400f, 1.695935853731027600f, 1.695732551869034300f, + 1.695529187659802400f, + 1.695325761110809200f, 1.695122272229534000f, 1.694918721023458600f, + 1.694715107500066800f, + 1.694511431666845000f, 1.694307693531282000f, 1.694103893100868100f, + 1.693900030383096900f, + 1.693696105385463800f, 1.693492118115466500f, 1.693288068580604900f, + 1.693083956788381500f, + 1.692879782746300700f, 1.692675546461869900f, 1.692471247942597600f, + 1.692266887195995600f, + 1.692062464229577600f, 1.691857979050859900f, 1.691653431667360600f, + 1.691448822086600400f, + 1.691244150316102000f, 1.691039416363390800f, 1.690834620235994300f, + 1.690629761941442100f, + 1.690424841487266700f, 1.690219858881001800f, 1.690014814130184300f, + 1.689809707242353200f, + 1.689604538225049700f, 1.689399307085817300f, 1.689194013832201500f, + 1.688988658471750600f, + 1.688783241012014700f, 1.688577761460546800f, 1.688372219824901400f, + 1.688166616112636100f, + 1.687960950331309800f, 1.687755222488484600f, 1.687549432591724400f, + 1.687343580648595700f, + 1.687137666666667100f, 1.686931690653509000f, 1.686725652616694900f, + 1.686519552563800400f, + 1.686313390502403000f, 1.686107166440082600f, 1.685900880384421800f, + 1.685694532343004600f, + 1.685488122323418400f, 1.685281650333251900f, 1.685075116380096800f, + 1.684868520471546600f, + 1.684661862615197000f, 1.684455142818646700f, 1.684248361089495800f, + 1.684041517435347400f, + 1.683834611863806100f, 1.683627644382479800f, 1.683420614998977900f, + 1.683213523720911800f, + 1.683006370555896400f, 1.682799155511547600f, 1.682591878595484300f, + 1.682384539815327400f, + 1.682177139178700400f, 1.681969676693228600f, 1.681762152366539600f, + 1.681554566206263900f, + 1.681346918220033800f, 1.681139208415483700f, 1.680931436800250600f, + 1.680723603381973500f, + 1.680515708168294200f, 1.680307751166856300f, 1.680099732385305300f, + 1.679891651831290100f, + 1.679683509512460900f, 1.679475305436470600f, 1.679267039610974300f, + 1.679058712043629300f, + 1.678850322742095200f, 1.678641871714033900f, 1.678433358967109400f, + 1.678224784508988400f, + 1.678016148347339300f, 1.677807450489833300f, 1.677598690944143400f, + 1.677389869717945000f, + 1.677180986818916300f, 1.676972042254736900f, 1.676763036033089600f, + 1.676553968161658600f, + 1.676344838648130600f, 1.676135647500194700f, 1.675926394725542700f, + 1.675717080331867900f, + 1.675507704326866200f, 1.675298266718235900f, 1.675088767513677200f, + 1.674879206720892900f, + 1.674669584347587800f, 1.674459900401469700f, 1.674250154890247300f, + 1.674040347821632800f, + 1.673830479203340000f, 1.673620549043085500f, 1.673410557348587600f, + 1.673200504127567000f, + 1.672990389387746700f, 1.672780213136852300f, 1.672569975382611300f, + 1.672359676132753500f, + 1.672149315395010900f, 1.671938893177118000f, 1.671728409486811500f, + 1.671517864331830000f, + 1.671307257719914800f, 1.671096589658809500f, 1.670885860156259300f, + 1.670675069220012500f, + 1.670464216857819200f, 1.670253303077431800f, 1.670042327886605200f, + 1.669831291293095900f, + 1.669620193304663500f, 1.669409033929069500f, 1.669197813174077200f, + 1.668986531047453000f, + 1.668775187556965000f, 1.668563782710383600f, 1.668352316515481700f, + 1.668140788980034400f, + 1.667929200111818400f, 1.667717549918614100f, 1.667505838408202700f, + 1.667294065588368100f, + 1.667082231466896900f, 1.666870336051577800f, 1.666658379350201000f, + 1.666446361370560000f, + 1.666234282120450100f, 1.666022141607668600f, 1.665809939840015500f, + 1.665597676825292700f, + 1.665385352571304500f, 1.665172967085857700f, 1.664960520376761000f, + 1.664748012451825200f, + 1.664535443318863900f, 1.664322812985692600f, 1.664110121460129000f, + 1.663897368749993400f, + 1.663684554863107800f, 1.663471679807296800f, 1.663258743590387400f, + 1.663045746220208600f, + 1.662832687704591800f, 1.662619568051370500f, 1.662406387268380100f, + 1.662193145363459100f, + 1.661979842344447600f, 1.661766478219188300f, 1.661553052995526000f, + 1.661339566681307600f, + 1.661126019284382200f, 1.660912410812601900f, 1.660698741273819700f, + 1.660485010675892400f, + 1.660271219026677700f, 1.660057366334036300f, 1.659843452605831200f, + 1.659629477849926800f, + 1.659415442074190900f, 1.659201345286492900f, 1.658987187494704200f, + 1.658772968706699000f, + 1.658558688930353400f, 1.658344348173546300f, 1.658129946444157700f, + 1.657915483750071100f, + 1.657700960099171200f, 1.657486375499345900f, 1.657271729958484500f, + 1.657057023484479000f, + 1.656842256085223800f, 1.656627427768615000f, 1.656412538542551200f, + 1.656197588414933600f, + 1.655982577393664700f, 1.655767505486650500f, 1.655552372701798200f, + 1.655337179047017700f, + 1.655121924530220900f, 1.654906609159322500f, 1.654691232942238500f, + 1.654475795886888300f, + 1.654260298001192200f, 1.654044739293073900f, 1.653829119770458900f, + 1.653613439441274500f, + 1.653397698313451300f, 1.653181896394921000f, 1.652966033693617800f, + 1.652750110217479100f, + 1.652534125974443000f, 1.652318080972451400f, 1.652101975219447200f, + 1.651885808723375900f, + 1.651669581492185300f, 1.651453293533826000f, 1.651236944856249600f, + 1.651020535467411200f, + 1.650804065375267400f, 1.650587534587776700f, 1.650370943112901000f, + 1.650154290958603300f, + 1.649937578132849400f, 1.649720804643607400f, 1.649503970498847200f, + 1.649287075706541200f, + 1.649070120274664000f, 1.648853104211192700f, 1.648636027524106100f, + 1.648418890221385400f, + 1.648201692311014300f, 1.647984433800978600f, 1.647767114699266100f, + 1.647549735013867000f, + 1.647332294752774200f, 1.647114793923981600f, 1.646897232535486500f, + 1.646679610595287900f, + 1.646461928111387300f, 1.646244185091788400f, 1.646026381544496400f, + 1.645808517477519700f, + 1.645590592898868600f, 1.645372607816555400f, 1.645154562238594800f, + 1.644936456173004000f, + 1.644718289627801600f, 1.644500062611009300f, 1.644281775130650900f, + 1.644063427194751600f, + 1.643845018811340300f, 1.643626549988446200f, 1.643408020734102600f, + 1.643189431056343700f, + 1.642970780963206800f, 1.642752070462730800f, 1.642533299562957100f, + 1.642314468271929300f, + 1.642095576597693200f, 1.641876624548297000f, 1.641657612131790500f, + 1.641438539356226500f, + 1.641219406229659700f, 1.641000212760146800f, 1.640780958955747200f, + 1.640561644824521700f, + 1.640342270374534500f, 1.640122835613851100f, 1.639903340550539200f, + 1.639683785192669600f, + 1.639464169548314100f, 1.639244493625547900f, 1.639024757432447500f, + 1.638804960977092100f, + 1.638585104267562800f, 1.638365187311943400f, 1.638145210118319400f, + 1.637925172694778800f, + 1.637705075049411800f, 1.637484917190310800f, 1.637264699125570200f, + 1.637044420863286600f, + 1.636824082411559600f, 1.636603683778490100f, 1.636383224972181500f, + 1.636162706000739300f, + 1.635942126872271800f, 1.635721487594888400f, 1.635500788176702100f, + 1.635280028625826900f, + 1.635059208950379700f, 1.634838329158479200f, 1.634617389258246700f, + 1.634396389257805700f, + 1.634175329165281400f, 1.633954208988801700f, 1.633733028736496400f, + 1.633511788416498000f, + 1.633290488036940500f, 1.633069127605960800f, 1.632847707131697600f, + 1.632626226622291700f, + 1.632404686085886300f, 1.632183085530627200f, 1.631961424964661700f, + 1.631739704396139900f, + 1.631517923833213400f, 1.631296083284036900f, 1.631074182756766300f, + 1.630852222259560700f, + 1.630630201800580900f, 1.630408121387990000f, 1.630185981029953000f, + 1.629963780734637400f, + 1.629741520510213000f, 1.629519200364851800f, 1.629296820306727700f, + 1.629074380344017100f, + 1.628851880484898200f, 1.628629320737551700f, 1.628406701110161100f, + 1.628184021610910700f, + 1.627961282247988300f, 1.627738483029583100f, 1.627515623963887000f, + 1.627292705059093700f, + 1.627069726323399500f, 1.626846687765002700f, 1.626623589392103500f, + 1.626400431212904800f, + 1.626177213235611400f, 1.625953935468430500f, 1.625730597919571300f, + 1.625507200597245500f, + 1.625283743509666300f, 1.625060226665050000f, 1.624836650071614500f, + 1.624613013737580000f, + 1.624389317671169500f, 1.624165561880607000f, 1.623941746374119500f, + 1.623717871159936300f, + 1.623493936246288300f, 1.623269941641409400f, 1.623045887353534900f, + 1.622821773390902700f, + 1.622597599761753000f, 1.622373366474327800f, 1.622149073536871800f, + 1.621924720957631300f, + 1.621700308744855200f, 1.621475836906794500f, 1.621251305451702400f, + 1.621026714387834300f, + 1.620802063723447700f, 1.620577353466802700f, 1.620352583626160500f, + 1.620127754209786100f, + 1.619902865225945300f, 1.619677916682906700f, 1.619452908588941300f, + 1.619227840952321800f, + 1.619002713781323200f, 1.618777527084222800f, 1.618552280869300300f, + 1.618326975144837000f, + 1.618101609919117200f, 1.617876185200426600f, 1.617650700997053500f, + 1.617425157317288200f, + 1.617199554169423500f, 1.616973891561754200f, 1.616748169502577200f, + 1.616522388000191500f, + 1.616296547062898500f, 1.616070646699001800f, 1.615844686916807300f, + 1.615618667724622700f, + 1.615392589130757900f, 1.615166451143525300f, 1.614940253771239400f, + 1.614713997022216900f, + 1.614487680904776600f, 1.614261305427239200f, 1.614034870597928400f, + 1.613808376425168900f, + 1.613581822917288900f, 1.613355210082617800f, 1.613128537929487500f, + 1.612901806466232200f, + 1.612675015701188000f, 1.612448165642693400f, 1.612221256299089200f, + 1.611994287678718100f, + 1.611767259789925100f, 1.611540172641057200f, 1.611313026240463800f, + 1.611085820596496600f, + 1.610858555717509200f, 1.610631231611857800f, 1.610403848287899700f, + 1.610176405753995800f, + 1.609948904018508200f, 1.609721343089801600f, 1.609493722976242900f, + 1.609266043686200700f, + 1.609038305228046400f, 1.608810507610153100f, 1.608582650840896200f, + 1.608354734928653800f, + 1.608126759881805400f, 1.607898725708732900f, 1.607670632417820500f, + 1.607442480017454700f, + 1.607214268516024000f, 1.606985997921919000f, 1.606757668243532500f, + 1.606529279489259600f, + 1.606300831667497600f, 1.606072324786645500f, 1.605843758855105300f, + 1.605615133881280700f, + 1.605386449873577300f, 1.605157706840403300f, 1.604928904790168700f, + 1.604700043731286200f, + 1.604471123672170500f, 1.604242144621237800f, 1.604013106586907400f, + 1.603784009577600100f, + 1.603554853601739700f, 1.603325638667751000f, 1.603096364784061900f, + 1.602867031959102100f, + 1.602637640201303400f, 1.602408189519099800f, 1.602178679920927900f, + 1.601949111415226000f, + 1.601719484010434300f, 1.601489797714996000f, 1.601260052537355700f, + 1.601030248485960900f, + 1.600800385569260300f, 1.600570463795705700f, 1.600340483173750400f, + 1.600110443711850300f, + 1.599880345418463100f, 1.599650188302049100f, 1.599419972371070500f, + 1.599189697633991400f, + 1.598959364099278700f, 1.598728971775401000f, 1.598498520670828900f, + 1.598268010794035900f, + 1.598037442153496900f, 1.597806814757689200f, 1.597576128615092200f, + 1.597345383734188000f, + 1.597114580123460100f, 1.596883717791394800f, 1.596652796746479600f, + 1.596421816997205500f, + 1.596190778552064800f, 1.595959681419551800f, 1.595728525608163700f, + 1.595497311126399300f, + 1.595266037982759500f, 1.595034706185747500f, 1.594803315743869000f, + 1.594571866665631700f, + 1.594340358959544800f, 1.594108792634120600f, 1.593877167697873100f, + 1.593645484159318200f, + 1.593413742026974500f, 1.593181941309362400f, 1.592950082015004700f, + 1.592718164152426000f, + 1.592486187730153300f, 1.592254152756715600f, 1.592022059240644400f, + 1.591789907190473100f, + 1.591557696614737100f, 1.591325427521974100f, 1.591093099920724200f, + 1.590860713819529400f, + 1.590628269226933600f, 1.590395766151483400f, 1.590163204601727100f, + 1.589930584586215500f, + 1.589697906113501000f, 1.589465169192139100f, 1.589232373830686400f, + 1.588999520037702300f, + 1.588766607821748200f, 1.588533637191387400f, 1.588300608155185600f, + 1.588067520721711000f, + 1.587834374899533400f, 1.587601170697224600f, 1.587367908123358900f, + 1.587134587186513000f, + 1.586901207895265300f, 1.586667770258196600f, 1.586434274283889500f, + 1.586200719980929200f, + 1.585967107357902700f, 1.585733436423399000f, 1.585499707186010200f, + 1.585265919654329300f, + 1.585032073836952100f, 1.584798169742476400f, 1.584564207379502500f, + 1.584330186756632200f, + 1.584096107882470000f, 1.583861970765622100f, 1.583627775414697000f, + 1.583393521838305700f, + 1.583159210045060900f, 1.582924840043577400f, 1.582690411842472700f, + 1.582455925450365600f, + 1.582221380875877800f, 1.581986778127632700f, 1.581752117214255900f, + 1.581517398144375800f, + 1.581282620926621300f, 1.581047785569625400f, 1.580812892082021900f, + 1.580577940472447200f, + 1.580342930749539800f, 1.580107862921940700f, 1.579872736998292100f, + 1.579637552987239100f, + 1.579402310897428900f, 1.579167010737510600f, 1.578931652516135700f, + 1.578696236241957200f, + 1.578460761923630800f, 1.578225229569814700f, 1.577989639189168100f, + 1.577753990790353500f, + 1.577518284382034800f, 1.577282519972878200f, 1.577046697571552000f, + 1.576810817186727000f, + 1.576574878827075700f, 1.576338882501273000f, 1.576102828217995600f, + 1.575866715985922500f, + 1.575630545813735200f, 1.575394317710116600f, 1.575158031683752300f, + 1.574921687743330300f, + 1.574685285897539800f, 1.574448826155072400f, 1.574212308524622500f, + 1.573975733014886000f, + 1.573739099634561500f, 1.573502408392348600f, 1.573265659296950300f, + 1.573028852357070800f, + 1.572791987581417100f, 1.572555064978698100f, 1.572318084557624800f, + 1.572081046326909900f, + 1.571843950295269000f, 1.571606796471419100f, 1.571369584864080100f, + 1.571132315481973200f, + 1.570894988333822400f, 1.570657603428353300f, 1.570420160774294000f, + 1.570182660380374600f, + 1.569945102255327200f, 1.569707486407886600f, 1.569469812846788500f, + 1.569232081580771900f, + 1.568994292618577400f, 1.568756445968948000f, 1.568518541640628400f, + 1.568280579642366000f, + 1.568042559982909500f, 1.567804482671010500f, 1.567566347715422500f, + 1.567328155124900800f, + 1.567089904908203200f, 1.566851597074089500f, 1.566613231631321500f, + 1.566374808588663300f, + 1.566136327954881000f, 1.565897789738742900f, 1.565659193949019400f, + 1.565420540594482800f, + 1.565181829683907700f, 1.564943061226071100f, 1.564704235229751500f, + 1.564465351703730400f, + 1.564226410656790000f, 1.563987412097716200f, 1.563748356035296000f, + 1.563509242478319000f, + 1.563270071435576500f, 1.563030842915862100f, 1.562791556927971800f, + 1.562552213480703300f, + 1.562312812582856500f, 1.562073354243233700f, 1.561833838470639200f, + 1.561594265273878800f, + 1.561354634661761300f, 1.561114946643096900f, 1.560875201226698900f, + 1.560635398421381400f, + 1.560395538235961800f, 1.560155620679258400f, 1.559915645760092900f, + 1.559675613487288200f, + 1.559435523869669500f, 1.559195376916064700f, 1.558955172635302800f, + 1.558714911036215700f, + 1.558474592127637100f, 1.558234215918402600f, 1.557993782417350400f, + 1.557753291633320500f, + 1.557512743575155000f, 1.557272138251698300f, 1.557031475671796400f, + 1.556790755844298400f, + 1.556549978778054300f, 1.556309144481917300f, 1.556068252964741600f, + 1.555827304235384500f, + 1.555586298302704900f, 1.555345235175563900f, 1.555104114862824600f, + 1.554862937373352500f, + 1.554621702716015000f, 1.554380410899681300f, 1.554139061933223200f, + 1.553897655825514600f, + 1.553656192585431100f, 1.553414672221850700f, 1.553173094743653300f, + 1.552931460159721100f, + 1.552689768478938500f, 1.552448019710191300f, 1.552206213862368500f, + 1.551964350944360100f, + 1.551722430965059000f, 1.551480453933359800f, 1.551238419858159700f, + 1.550996328748356800f, + 1.550754180612852900f, 1.550511975460550500f, 1.550269713300355100f, + 1.550027394141174000f, + 1.549785017991916400f, 1.549542584861493900f, 1.549300094758820000f, + 1.549057547692810600f, + 1.548814943672383300f, 1.548572282706457900f, 1.548329564803956300f, + 1.548086789973802700f, + 1.547843958224923000f, 1.547601069566245900f, 1.547358124006701400f, + 1.547115121555221700f, + 1.546872062220741700f, 1.546628946012197800f, 1.546385772938528600f, + 1.546142543008675300f, + 1.545899256231580300f, 1.545655912616188800f, 1.545412512171447700f, + 1.545169054906306200f, + 1.544925540829715600f, 1.544681969950629300f, 1.544438342278002600f, + 1.544194657820792800f, + 1.543950916587959700f, 1.543707118588464800f, 1.543463263831272000f, + 1.543219352325347200f, + 1.542975384079658300f, 1.542731359103175300f, 1.542487277404870100f, + 1.542243138993717000f, + 1.541998943878692300f, 1.541754692068774600f, 1.541510383572944000f, + 1.541266018400183200f, + 1.541021596559476700f, 1.540777118059811100f, 1.540532582910175500f, + 1.540287991119560600f, + 1.540043342696959100f, 1.539798637651366400f, 1.539553875991779300f, + 1.539309057727197300f, + 1.539064182866621400f, 1.538819251419055100f, 1.538574263393503800f, + 1.538329218798974800f, + 1.538084117644477900f, 1.537838959939025200f, 1.537593745691629500f, + 1.537348474911307300f, + 1.537103147607076200f, 1.536857763787956400f, 1.536612323462969800f, + 1.536366826641140800f, + 1.536121273331495300f, 1.535875663543061700f, 1.535629997284870400f, + 1.535384274565953600f, + 1.535138495395346400f, 1.534892659782085100f, 1.534646767735208000f, + 1.534400819263756400f, + 1.534154814376772700f, 1.533908753083302200f, 1.533662635392391700f, + 1.533416461313090100f, + 1.533170230854448400f, 1.532923944025520200f, 1.532677600835360600f, + 1.532431201293027000f, + 1.532184745407578500f, 1.531938233188077100f, 1.531691664643585900f, + 1.531445039783170500f, + 1.531198358615898800f, 1.530951621150840700f, 1.530704827397067800f, + 1.530457977363654000f, + 1.530211071059675200f, 1.529964108494209700f, 1.529717089676337500f, + 1.529470014615140800f, + 1.529222883319703700f, 1.528975695799112500f, 1.528728452062455600f, + 1.528481152118823700f, + 1.528233795977309400f, 1.527986383647006500f, 1.527738915137012400f, + 1.527491390456425600f, + 1.527243809614346600f, 1.526996172619878900f, 1.526748479482126700f, + 1.526500730210197200f, + 1.526252924813199500f, 1.526005063300244900f, 1.525757145680446200f, + 1.525509171962918800f, + 1.525261142156779900f, 1.525013056271149000f, 1.524764914315147200f, + 1.524516716297898300f, + 1.524268462228527900f, 1.524020152116163200f, 1.523771785969934000f, + 1.523523363798972000f, + 1.523274885612411200f, 1.523026351419387100f, 1.522777761229038100f, + 1.522529115050503600f, + 1.522280412892925900f, 1.522031654765448900f, 1.521782840677218700f, + 1.521533970637383800f, + 1.521285044655094300f, 1.521036062739502300f, 1.520787024899762100f, + 1.520537931145030400f, + 1.520288781484465700f, 1.520039575927228500f, 1.519790314482481100f, + 1.519540997159388300f, + 1.519291623967116600f, 1.519042194914835200f, 1.518792710011714500f, + 1.518543169266927600f, + 1.518293572689648900f, 1.518043920289055900f, 1.517794212074327500f, + 1.517544448054644500f, + 1.517294628239190400f, 1.517044752637150000f, 1.516794821257710500f, + 1.516544834110061600f, + 1.516294791203394200f, 1.516044692546901800f, 1.515794538149779700f, + 1.515544328021225500f, + 1.515294062170438700f, 1.515043740606620800f, 1.514793363338975600f, + 1.514542930376708600f, + 1.514292441729027300f, 1.514041897405141700f, 1.513791297414263800f, + 1.513540641765606800f, + 1.513289930468387300f, 1.513039163531823000f, 1.512788340965133500f, + 1.512537462777541200f, + 1.512286528978270300f, 1.512035539576546600f, 1.511784494581598600f, + 1.511533394002656100f, + 1.511282237848951400f, 1.511031026129719100f, 1.510779758854195400f, + 1.510528436031618900f, + 1.510277057671229400f, 1.510025623782270000f, 1.509774134373984800f, + 1.509522589455620600f, + 1.509270989036425800f, 1.509019333125651200f, 1.508767621732549400f, + 1.508515854866375100f, + 1.508264032536385000f, 1.508012154751837700f, 1.507760221521994700f, + 1.507508232856118200f, + 1.507256188763473200f, 1.507004089253327000f, 1.506751934334948000f, + 1.506499724017607900f, + 1.506247458310579400f, 1.505995137223137500f, 1.505742760764559300f, + 1.505490328944124200f, + 1.505237841771113200f, 1.504985299254809800f, 1.504732701404498900f, + 1.504480048229468000f, + 1.504227339739006500f, 1.503974575942405700f, 1.503721756848958700f, + 1.503468882467961600f, + 1.503215952808711500f, 1.502962967880507600f, 1.502709927692651900f, + 1.502456832254447600f, + 1.502203681575200700f, 1.501950475664218600f, 1.501697214530810700f, + 1.501443898184289200f, + 1.501190526633967600f, 1.500937099889161600f, 1.500683617959188900f, + 1.500430080853369500f, + 1.500176488581024900f, 1.499922841151479600f, 1.499669138574058800f, + 1.499415380858090800f, + 1.499161568012905300f, 1.498907700047834600f, 1.498653776972212600f, + 1.498399798795375000f, + 1.498145765526660300f, 1.497891677175408500f, 1.497637533750961300f, + 1.497383335262663300f, + 1.497129081719860400f, 1.496874773131900800f, 1.496620409508134800f, + 1.496365990857914600f, + 1.496111517190594300f, 1.495856988515530400f, 1.495602404842080800f, + 1.495347766179606400f, + 1.495093072537469100f, 1.494838323925033400f, 1.494583520351665500f, + 1.494328661826734200f, + 1.494073748359609600f, 1.493818779959664300f, 1.493563756636272500f, + 1.493308678398810800f, + 1.493053545256657800f, 1.492798357219194100f, 1.492543114295801900f, + 1.492287816495866200f, + 1.492032463828773200f, 1.491777056303911700f, 1.491521593930672100f, + 1.491266076718446900f, + 1.491010504676631500f, 1.490754877814621800f, 1.490499196141816600f, + 1.490243459667616600f, + 1.489987668401424800f, 1.489731822352645500f, 1.489475921530685900f, + 1.489219965944954300f, + 1.488963955604861500f, 1.488707890519820600f, 1.488451770699245900f, + 1.488195596152554800f, + 1.487939366889165600f, 1.487683082918499300f, 1.487426744249978400f, + 1.487170350893028500f, + 1.486913902857075700f, 1.486657400151549600f, 1.486400842785880100f, + 1.486144230769501000f, + 1.485887564111846500f, 1.485630842822354100f, 1.485374066910462500f, + 1.485117236385612200f, + 1.484860351257246500f, 1.484603411534810300f, 1.484346417227750700f, + 1.484089368345516300f, + 1.483832264897558400f, 1.483575106893329600f, 1.483317894342285100f, + 1.483060627253882000f, + 1.482803305637578900f, 1.482545929502837100f, 1.482288498859119400f, + 1.482031013715890700f, + 1.481773474082618300f, 1.481515879968770900f, 1.481258231383819800f, + 1.481000528337237800f, + 1.480742770838499900f, 1.480484958897083200f, 1.480227092522466500f, + 1.479969171724131200f, + 1.479711196511560100f, 1.479453166894238100f, 1.479195082881652200f, + 1.478936944483291600f, + 1.478678751708647000f, 1.478420504567211900f, 1.478162203068481100f, + 1.477903847221951400f, + 1.477645437037121900f, 1.477386972523493800f, 1.477128453690569800f, + 1.476869880547855300f, + 1.476611253104856700f, 1.476352571371083700f, 1.476093835356046700f, + 1.475835045069259000f, + 1.475576200520235500f, 1.475317301718493300f, 1.475058348673551100f, + 1.474799341394929900f, + 1.474540279892153000f, 1.474281164174744900f, 1.474021994252233000f, + 1.473762770134145800f, + 1.473503491830014300f, 1.473244159349371700f, 1.472984772701752900f, + 1.472725331896694400f, + 1.472465836943735600f, 1.472206287852416900f, 1.471946684632281500f, + 1.471687027292874400f, + 1.471427315843742100f, 1.471167550294433700f, 1.470907730654499800f, + 1.470647856933493300f, + 1.470387929140969200f, 1.470127947286484100f, 1.469867911379596900f, + 1.469607821429868500f, + 1.469347677446861500f, 1.469087479440140300f, 1.468827227419272200f, + 1.468566921393825700f, + 1.468306561373371900f, 1.468046147367482600f, 1.467785679385733300f, + 1.467525157437700200f, + 1.467264581532962100f, 1.467003951681099800f, 1.466743267891695800f, + 1.466482530174334500f, + 1.466221738538602500f, 1.465960892994088800f, 1.465699993550383400f, + 1.465439040217079400f, + 1.465178033003770700f, 1.464916971920054100f, 1.464655856975527900f, + 1.464394688179792900f, + 1.464133465542451200f, 1.463872189073107500f, 1.463610858781367900f, + 1.463349474676840700f, + 1.463088036769136600f, 1.462826545067867700f, 1.462564999582648600f, + 1.462303400323095000f, + 1.462041747298825900f, 1.461780040519460800f, 1.461518279994622200f, + 1.461256465733934400f, + 1.460994597747023600f, 1.460732676043517800f, 1.460470700633046800f, + 1.460208671525243400f, + 1.459946588729741100f, 1.459684452256176300f, 1.459422262114186800f, + 1.459160018313412400f, + 1.458897720863495500f, 1.458635369774079500f, 1.458372965054810700f, + 1.458110506715337000f, + 1.457847994765308200f, 1.457585429214375700f, 1.457322810072193800f, + 1.457060137348418000f, + 1.456797411052706200f, 1.456534631194717800f, 1.456271797784114900f, + 1.456008910830560500f, + 1.455745970343720800f, 1.455482976333263100f, 1.455219928808857200f, + 1.454956827780174100f, + 1.454693673256887600f, 1.454430465248673300f, 1.454167203765208000f, + 1.453903888816171900f, + 1.453640520411245900f, 1.453377098560113100f, 1.453113623272459100f, + 1.452850094557971000f, + 1.452586512426338000f, 1.452322876887251400f, 1.452059187950404100f, + 1.451795445625491300f, + 1.451531649922210200f, 1.451267800850259500f, 1.451003898419340500f, + 1.450739942639155800f, + 1.450475933519410400f, 1.450211871069811300f, 1.449947755300067500f, + 1.449683586219889400f, + 1.449419363838989800f, 1.449155088167083600f, 1.448890759213887100f, + 1.448626376989119400f, + 1.448361941502500900f, 1.448097452763754000f, 1.447832910782603100f, + 1.447568315568775100f, + 1.447303667131997900f, 1.447038965482002200f, 1.446774210628520200f, + 1.446509402581286400f, + 1.446244541350036700f, 1.445979626944509300f, 1.445714659374444500f, + 1.445449638649584500f, + 1.445184564779673500f, 1.444919437774456700f, 1.444654257643682900f, + 1.444389024397101600f, + 1.444123738044464900f, 1.443858398595526400f, 1.443593006060042100f, + 1.443327560447769600f, + 1.443062061768468400f, 1.442796510031900500f, 1.442530905247829200f, + 1.442265247426020200f, + 1.441999536576240800f, 1.441733772708260600f, 1.441467955831850800f, + 1.441202085956784900f, + 1.440936163092837900f, 1.440670187249787600f, 1.440404158437412500f, + 1.440138076665494100f, + 1.439871941943815300f, 1.439605754282161400f, 1.439339513690319100f, + 1.439073220178077400f, + 1.438806873755226900f, 1.438540474431560600f, 1.438274022216873500f, + 1.438007517120961900f, + 1.437740959153624500f, 1.437474348324662100f, 1.437207684643876800f, + 1.436940968121073600f, + 1.436674198766058500f, 1.436407376588640000f, 1.436140501598628400f, + 1.435873573805835900f, + 1.435606593220076600f, 1.435339559851166500f, 1.435072473708924000f, + 1.434805334803169100f, + 1.434538143143723200f, 1.434270898740410700f, 1.434003601603057300f, + 1.433736251741490700f, + 1.433468849165540500f, 1.433201393885038500f, 1.432933885909818000f, + 1.432666325249714700f, + 1.432398711914566200f, 1.432131045914211600f, 1.431863327258492400f, + 1.431595555957251700f, + 1.431327732020334800f, 1.431059855457588600f, 1.430791926278862400f, + 1.430523944494007400f, + 1.430255910112876000f, 1.429987823145323100f, 1.429719683601205800f, + 1.429451491490382900f, + 1.429183246822714800f, 1.428914949608064200f, 1.428646599856295400f, + 1.428378197577275100f, + 1.428109742780871800f, 1.427841235476955400f, 1.427572675675398600f, + 1.427304063386075200f, + 1.427035398618861500f, 1.426766681383635500f, 1.426497911690277000f, + 1.426229089548668200f, + 1.425960214968693000f, 1.425691287960236600f, 1.425422308533187200f, + 1.425153276697434000f, + 1.424884192462868800f, 1.424615055839385300f, 1.424345866836878200f, + 1.424076625465245500f, + 1.423807331734385800f, 1.423537985654200800f, 1.423268587234593400f, + 1.422999136485468600f, + 1.422729633416733200f, 1.422460078038296300f, 1.422190470360068300f, + 1.421920810391962500f, + 1.421651098143893000f, 1.421381333625776600f, 1.421111516847531700f, + 1.420841647819078600f, + 1.420571726550339700f, 1.420301753051239400f, 1.420031727331703800f, + 1.419761649401660500f, + 1.419491519271040000f, 1.419221336949774100f, 1.418951102447796800f, + 1.418680815775043500f, + 1.418410476941452100f, 1.418140085956961900f, 1.417869642831514700f, + 1.417599147575054000f, + 1.417328600197524900f, 1.417058000708874700f, 1.416787349119052600f, + 1.416516645438009600f, + 1.416245889675698900f, 1.415975081842075300f, 1.415704221947095700f, + 1.415433310000718600f, + 1.415162346012905000f, 1.414891329993617200f, 1.414620261952819600f, + 1.414349141900479000f, + 1.414077969846563500f, 1.413806745801043500f, 1.413535469773890700f, + 1.413264141775079300f, + 1.412992761814585400f, 1.412721329902386900f, 1.412449846048463600f, + 1.412178310262796900f, + 1.411906722555370500f, 1.411635082936170100f, 1.411363391415182900f, + 1.411091648002398500f, + 1.410819852707807700f, 1.410548005541404100f, 1.410276106513182400f, + 1.410004155633139500f, + 1.409732152911274500f, 1.409460098357588200f, 1.409187991982083100f, + 1.408915833794763800f, + 1.408643623805636800f, 1.408371362024710500f, 1.408099048461995300f, + 1.407826683127503000f, + 1.407554266031248100f, 1.407281797183246500f, 1.407009276593515800f, + 1.406736704272076400f, + 1.406464080228949600f, 1.406191404474159000f, 1.405918677017730100f, + 1.405645897869690400f, + 1.405373067040069300f, 1.405100184538898000f, 1.404827250376209400f, + 1.404554264562038400f, + 1.404281227106422400f, 1.404008138019399800f, 1.403734997311011600f, + 1.403461804991300100f, + 1.403188561070310100f, 1.402915265558087700f, 1.402641918464681400f, + 1.402368519800141200f, + 1.402095069574519800f, 1.401821567797870300f, 1.401548014480249000f, + 1.401274409631713600f, + 1.401000753262323900f, 1.400727045382141400f, 1.400453286001229800f, + 1.400179475129653700f, + 1.399905612777481200f, 1.399631698954780800f, 1.399357733671623900f, + 1.399083716938083600f, + 1.398809648764234100f, 1.398535529160152400f, 1.398261358135917300f, + 1.397987135701609200f, + 1.397712861867310300f, 1.397438536643105000f, 1.397164160039079200f, + 1.396889732065321300f, + 1.396615252731921100f, 1.396340722048970300f, 1.396066140026562800f, + 1.395791506674794100f, + 1.395516822003761700f, 1.395242086023564800f, 1.394967298744304900f, + 1.394692460176085300f, + 1.394417570329010700f, 1.394142629213188000f, 1.393867636838725900f, + 1.393592593215735600f, + 1.393317498354329300f, 1.393042352264621600f, 1.392767154956728400f, + 1.392491906440768600f, + 1.392216606726861800f, 1.391941255825130100f, 1.391665853745697400f, + 1.391390400498689700f, + 1.391114896094234100f, 1.390839340542460600f, 1.390563733853500200f, + 1.390288076037486500f, + 1.390012367104554600f, 1.389736607064841100f, 1.389460795928485500f, + 1.389184933705628300f, + 1.388909020406412100f, 1.388633056040981600f, 1.388357040619483200f, + 1.388080974152065200f, + 1.387804856648877600f, 1.387528688120072600f, 1.387252468575804100f, + 1.386976198026228100f, + 1.386699876481501900f, 1.386423503951785200f, 1.386147080447239600f, + 1.385870605978028100f, + 1.385594080554316100f, 1.385317504186270900f, 1.385040876884061000f, + 1.384764198657857200f, + 1.384487469517832200f, 1.384210689474160600f, 1.383933858537019100f, + 1.383656976716585600f, + 1.383380044023040400f, 1.383103060466565300f, 1.382826026057344600f, + 1.382548940805563800f, + 1.382271804721410600f, 1.381994617815074400f, 1.381717380096746800f, + 1.381440091576620700f, + 1.381162752264891500f, 1.380885362171756300f, 1.380607921307413400f, + 1.380330429682064000f, + 1.380052887305910400f, 1.379775294189157000f, 1.379497650342010400f, + 1.379219955774678700f, + 1.378942210497371600f, 1.378664414520301500f, 1.378386567853681700f, + 1.378108670507728300f, + 1.377830722492658500f, 1.377552723818691500f, 1.377274674496048700f, + 1.376996574534953300f, + 1.376718423945630000f, 1.376440222738305700f, 1.376161970923209400f, + 1.375883668510570900f, + 1.375605315510623200f, 1.375326911933600200f, 1.375048457789738400f, + 1.374769953089275400f, + 1.374491397842451100f, 1.374212792059507100f, 1.373934135750687100f, + 1.373655428926236400f, + 1.373376671596402400f, 1.373097863771434200f, 1.372819005461582500f, + 1.372540096677100200f, + 1.372261137428242300f, 1.371982127725264800f, 1.371703067578426700f, + 1.371423956997988000f, + 1.371144795994210500f, 1.370865584577358300f, 1.370586322757697500f, + 1.370307010545495500f, + 1.370027647951022100f, 1.369748234984548000f, 1.369468771656347200f, + 1.369189257976694200f, + 1.368909693955866000f, 1.368630079604142000f, 1.368350414931802000f, + 1.368070699949128800f, + 1.367790934666406600f, 1.367511119093921800f, 1.367231253241962200f, + 1.366951337120818000f, + 1.366671370740780500f, 1.366391354112143500f, 1.366111287245202400f, + 1.365831170150254300f, + 1.365551002837598600f, 1.365270785317536100f, 1.364990517600369400f, + 1.364710199696403300f, + 1.364429831615944200f, 1.364149413369300600f, 1.363868944966782900f, + 1.363588426418702600f, + 1.363307857735373900f, 1.363027238927112300f, 1.362746570004235400f, + 1.362465850977062900f, + 1.362185081855915600f, 1.361904262651116900f, 1.361623393372991300f, + 1.361342474031866000f, + 1.361061504638069400f, 1.360780485201932300f, 1.360499415733786400f, + 1.360218296243966200f, + 1.359937126742807300f, 1.359655907240648000f, 1.359374637747827700f, + 1.359093318274687800f, + 1.358811948831571500f, 1.358530529428824400f, 1.358249060076792900f, + 1.357967540785826300f, + 1.357685971566275200f, 1.357404352428492000f, 1.357122683382830900f, + 1.356840964439648200f, + 1.356559195609301700f, 1.356277376902151900f, 1.355995508328559500f, + 1.355713589898888800f, + 1.355431621623504700f, 1.355149603512774400f, 1.354867535577067200f, + 1.354585417826753800f, + 1.354303250272206500f, 1.354021032923800300f, 1.353738765791911100f, + 1.353456448886917200f, + 1.353174082219199100f, 1.352891665799137900f, 1.352609199637117500f, + 1.352326683743523300f, + 1.352044118128742600f, 1.351761502803164900f, 1.351478837777180700f, + 1.351196123061183100f, + 1.350913358665566400f, 1.350630544600727200f, 1.350347680877063800f, + 1.350064767504976400f, + 1.349781804494866600f, 1.349498791857138400f, 1.349215729602197400f, + 1.348932617740450600f, + 1.348649456282307700f, 1.348366245238179500f, 1.348082984618478800f, + 1.347799674433620500f, + 1.347516314694020800f, 1.347232905410098200f, 1.346949446592273100f, + 1.346665938250967100f, + 1.346382380396604000f, 1.346098773039609700f, 1.345815116190411300f, + 1.345531409859438200f, + 1.345247654057121700f, 1.344963848793894200f, 1.344679994080190800f, + 1.344396089926448000f, + 1.344112136343103900f, 1.343828133340598800f, 1.343544080929374800f, + 1.343259979119875600f, + 1.342975827922546600f, 1.342691627347835500f, 1.342407377406191500f, + 1.342123078108065700f, + 1.341838729463910900f, 1.341554331484181600f, 1.341269884179334700f, + 1.340985387559828100f, + 1.340700841636122400f, 1.340416246418678800f, 1.340131601917961900f, + 1.339846908144436600f, + 1.339562165108570700f, 1.339277372820833400f, 1.338992531291695500f, + 1.338707640531629800f, + 1.338422700551110900f, 1.338137711360615200f, 1.337852672970621300f, + 1.337567585391608900f, + 1.337282448634059800f, 1.336997262708457900f, 1.336712027625288600f, + 1.336426743395039000f, + 1.336141410028198500f, 1.335856027535258000f, 1.335570595926709700f, + 1.335285115213048500f, + 1.334999585404770700f, 1.334714006512374400f, 1.334428378546359500f, + 1.334142701517227600f, + 1.333856975435482300f, 1.333571200311629100f, 1.333285376156174700f, + 1.332999502979628700f, + 1.332713580792501500f, 1.332427609605305400f, 1.332141589428554900f, + 1.331855520272766200f, + 1.331569402148457400f, 1.331283235066148100f, 1.330997019036359800f, + 1.330710754069615700f, + 1.330424440176441300f, 1.330138077367363200f, 1.329851665652910500f, + 1.329565205043613800f, + 1.329278695550004700f, 1.328992137182618100f, 1.328705529951989400f, + 1.328418873868656900f, + 1.328132168943159800f, 1.327845415186039000f, 1.327558612607838500f, + 1.327271761219102500f, + 1.326984861030378000f, 1.326697912052213500f, 1.326410914295159400f, + 1.326123867769767500f, + 1.325836772486591800f, 1.325549628456188100f, 1.325262435689113600f, + 1.324975194195928000f, + 1.324687903987191900f, 1.324400565073468300f, 1.324113177465321900f, + 1.323825741173318700f, + 1.323538256208027800f, 1.323250722580018500f, 1.322963140299862500f, + 1.322675509378133900f, + 1.322387829825407700f, 1.322100101652261100f, 1.321812324869273500f, + 1.321524499487024800f, + 1.321236625516098100f, 1.320948702967077400f, 1.320660731850549000f, + 1.320372712177100700f, + 1.320084643957322400f, 1.319796527201805300f, 1.319508361921142500f, + 1.319220148125929100f, + 1.318931885826762000f, 1.318643575034239800f, 1.318355215758962900f, + 1.318066808011533200f, + 1.317778351802554800f, 1.317489847142633300f, 1.317201294042376300f, + 1.316912692512393300f, + 1.316624042563294900f, 1.316335344205694200f, 1.316046597450205800f, + 1.315757802307445900f, + 1.315468958788033000f, 1.315180066902586800f, 1.314891126661728900f, + 1.314602138076083300f, + 1.314313101156274800f, 1.314024015912930600f, 1.313734882356679900f, + 1.313445700498152800f, + 1.313156470347981900f, 1.312867191916801100f, 1.312577865215246900f, + 1.312288490253956900f, + 1.311999067043570200f, 1.311709595594728000f, 1.311420075918073900f, + 1.311130508024252400f, + 1.310840891923910100f, 1.310551227627695400f, 1.310261515146258200f, + 1.309971754490250700f, + 1.309681945670326400f, 1.309392088697140900f, 1.309102183581351200f, + 1.308812230333616500f, + 1.308522228964597500f, 1.308232179484956500f, 1.307942081905358000f, + 1.307651936236467800f, + 1.307361742488954300f, 1.307071500673486800f, 1.306781210800736200f, + 1.306490872881376200f, + 1.306200486926081700f, 1.305910052945529200f, 1.305619570950396800f, + 1.305329040951365100f, + 1.305038462959116100f, 1.304747836984333300f, 1.304457163037702200f, + 1.304166441129910300f, + 1.303875671271646400f, 1.303584853473601200f, 1.303293987746467300f, + 1.303003074100939100f, + 1.302712112547712800f, 1.302421103097485900f, 1.302130045760958100f, + 1.301838940548830600f, + 1.301547787471806900f, 1.301256586540591600f, 1.300965337765891600f, + 1.300674041158414800f, + 1.300382696728871400f, 1.300091304487973800f, 1.299799864446435200f, + 1.299508376614971500f, + 1.299216841004299200f, 1.298925257625137800f, 1.298633626488207500f, + 1.298341947604231300f, + 1.298050220983932900f, 1.297758446638038700f, 1.297466624577275900f, + 1.297174754812374400f, + 1.296882837354065100f, 1.296590872213081200f, 1.296298859400157700f, + 1.296006798926030200f, + 1.295714690801437600f, 1.295422535037119800f, 1.295130331643818500f, + 1.294838080632277000f, + 1.294545782013240900f, 1.294253435797456900f, 1.293961041995673700f, + 1.293668600618642000f, + 1.293376111677113900f, 1.293083575181843500f, 1.292790991143586200f, + 1.292498359573099700f, + 1.292205680481143500f, 1.291912953878477900f, 1.291620179775866400f, + 1.291327358184073200f, + 1.291034489113864100f, 1.290741572576007400f, 1.290448608581273000f, + 1.290155597140431700f, + 1.289862538264257700f, 1.289569431963524900f, 1.289276278249010600f, + 1.288983077131493000f, + 1.288689828621752300f, 1.288396532730570400f, 1.288103189468731400f, + 1.287809798847019800f, + 1.287516360876223500f, 1.287222875567130900f, 1.286929342930532800f, + 1.286635762977221800f, + 1.286342135717991600f, 1.286048461163638000f, 1.285754739324958900f, + 1.285460970212753500f, + 1.285167153837822900f, 1.284873290210969900f, 1.284579379342998700f, + 1.284285421244715900f, + 1.283991415926929400f, 1.283697363400448900f, 1.283403263676086100f, + 1.283109116764654000f, + 1.282814922676967400f, 1.282520681423843000f, 1.282226393016099500f, + 1.281932057464557000f, + 1.281637674780037100f, 1.281343244973363700f, 1.281048768055361900f, + 1.280754244036858900f, + 1.280459672928683500f, 1.280165054741666300f, 1.279870389486639400f, + 1.279575677174437100f, + 1.279280917815894600f, 1.278986111421849900f, 1.278691258003142000f, + 1.278396357570611900f, + 1.278101410135101800f, 1.277806415707456700f, 1.277511374298522200f, + 1.277216285919146500f, + 1.276921150580179200f, 1.276625968292471000f, 1.276330739066875400f, + 1.276035462914247000f, + 1.275740139845442400f, 1.275444769871319600f, 1.275149353002738700f, + 1.274853889250561200f, + 1.274558378625650200f, 1.274262821138871300f, 1.273967216801090900f, + 1.273671565623178100f, + 1.273375867616002300f, 1.273080122790436000f, 1.272784331157352800f, + 1.272488492727628100f, + 1.272192607512139300f, 1.271896675521764900f, 1.271600696767385400f, + 1.271304671259883200f, + 1.271008599010142500f, 1.270712480029048800f, 1.270416314327489800f, + 1.270120101916354600f, + 1.269823842806533800f, 1.269527537008920300f, 1.269231184534408200f, + 1.268934785393893700f, + 1.268638339598274500f, 1.268341847158450200f, 1.268045308085321800f, + 1.267748722389792100f, + 1.267452090082765900f, 1.267155411175149500f, 1.266858685677851000f, + 1.266561913601780100f, + 1.266265094957848000f, 1.265968229756968100f, 1.265671318010055400f, + 1.265374359728026500f, + 1.265077354921799300f, 1.264780303602294200f, 1.264483205780432700f, + 1.264186061467138500f, + 1.263888870673336400f, 1.263591633409954000f, 1.263294349687918800f, + 1.262997019518161700f, + 1.262699642911614600f, 1.262402219879211300f, 1.262104750431887000f, + 1.261807234580578900f, + 1.261509672336225600f, 1.261212063709767900f, 1.260914408712147800f, + 1.260616707354309500f, + 1.260318959647198400f, 1.260021165601761900f, 1.259723325228949000f, + 1.259425438539710300f, + 1.259127505544998600f, 1.258829526255768000f, 1.258531500682973800f, + 1.258233428837574300f, + 1.257935310730528000f, 1.257637146372796400f, 1.257338935775342200f, + 1.257040678949129500f, + 1.256742375905124400f, 1.256444026654294400f, 1.256145631207609400f, + 1.255847189576040100f, + 1.255548701770560000f, 1.255250167802143000f, 1.254951587681765600f, + 1.254652961420405600f, + 1.254354289029042900f, 1.254055570518658500f, 1.253756805900235700f, + 1.253457995184759300f, + 1.253159138383215200f, 1.252860235506592100f, 1.252561286565879300f, + 1.252262291572068900f, + 1.251963250536153500f, 1.251664163469128300f, 1.251365030381989700f, + 1.251065851285736200f, + 1.250766626191367500f, 1.250467355109885500f, 1.250168038052293500f, + 1.249868675029596200f, + 1.249569266052800800f, 1.249269811132915200f, 1.248970310280950200f, + 1.248670763507917100f, + 1.248371170824829300f, 1.248071532242702100f, 1.247771847772552300f, + 1.247472117425398700f, + 1.247172341212261500f, 1.246872519144162300f, 1.246572651232124700f, + 1.246272737487174300f, + 1.245972777920338000f, 1.245672772542644400f, 1.245372721365123600f, + 1.245072624398807900f, + 1.244772481654731000f, 1.244472293143928300f, 1.244172058877436800f, + 1.243871778866295400f, + 1.243571453121544000f, 1.243271081654225400f, 1.242970664475383100f, + 1.242670201596062700f, + 1.242369693027311200f, 1.242069138780177400f, 1.241768538865712000f, + 1.241467893294967200f, + 1.241167202078996800f, 1.240866465228856100f, 1.240565682755603100f, + 1.240264854670295900f, + 1.239963980983995300f, 1.239663061707763700f, 1.239362096852665300f, + 1.239061086429765300f, + 1.238760030450130900f, 1.238458928924831600f, 1.238157781864937400f, + 1.237856589281521000f, + 1.237555351185656500f, 1.237254067588419400f, 1.236952738500886900f, + 1.236651363934138300f, + 1.236349943899254000f, 1.236048478407316500f, 1.235746967469409900f, + 1.235445411096619500f, + 1.235143809300033300f, 1.234842162090739700f, 1.234540469479829900f, + 1.234238731478396000f, + 1.233936948097532400f, 1.233635119348334400f, 1.233333245241899200f, + 1.233031325789326400f, + 1.232729361001716500f, 1.232427350890172000f, 1.232125295465796600f, + 1.231823194739696300f, + 1.231521048722978200f, 1.231218857426751700f, 1.230916620862127400f, + 1.230614339040217800f, + 1.230312011972136500f, 1.230009639668999500f, 1.229707222141924100f, + 1.229404759402029400f, + 1.229102251460436400f, 1.228799698328266700f, 1.228497100016644900f, + 1.228194456536696500f, + 1.227891767899548700f, 1.227589034116330700f, 1.227286255198173100f, + 1.226983431156208200f, + 1.226680562001569900f, 1.226377647745394000f, 1.226074688398817600f, + 1.225771683972980200f, + 1.225468634479021500f, 1.225165539928084300f, 1.224862400331312400f, + 1.224559215699851500f, + 1.224255986044848500f, 1.223952711377453100f, 1.223649391708814700f, + 1.223346027050086400f, + 1.223042617412421600f, 1.222739162806975900f, 1.222435663244906700f, + 1.222132118737372400f, + 1.221828529295533800f, 1.221524894930552800f, 1.221221215653593100f, + 1.220917491475820500f, + 1.220613722408401900f, 1.220309908462505800f, 1.220006049649302800f, + 1.219702145979964600f, + 1.219398197465665400f, 1.219094204117580300f, 1.218790165946886100f, + 1.218486082964761500f, + 1.218181955182386500f, 1.217877782610943700f, 1.217573565261616000f, + 1.217269303145589000f, + 1.216964996274049400f, 1.216660644658185600f, 1.216356248309187600f, + 1.216051807238247800f, + 1.215747321456559300f, 1.215442790975316700f, 1.215138215805717300f, + 1.214833595958959300f, + 1.214528931446242600f, 1.214224222278769100f, 1.213919468467741900f, + 1.213614670024366000f, + 1.213309826959847700f, 1.213004939285395400f, 1.212700007012219100f, + 1.212395030151530300f, + 1.212090008714541600f, 1.211784942712468300f, 1.211479832156526800f, + 1.211174677057934800f, + 1.210869477427912300f, 1.210564233277680500f, 1.210258944618462200f, + 1.209953611461482200f, + 1.209648233817966600f, 1.209342811699143600f, 1.209037345116242400f, + 1.208731834080493800f, + 1.208426278603131200f, 1.208120678695388600f, 1.207815034368502100f, + 1.207509345633709600f, + 1.207203612502250300f, 1.206897834985365000f, 1.206592013094296200f, + 1.206286146840288300f, + 1.205980236234587100f, 1.205674281288440000f, 1.205368282013096200f, + 1.205062238419806200f, + 1.204756150519822300f, 1.204450018324398900f, 1.204143841844791200f, + 1.203837621092256800f, + 1.203531356078054100f, 1.203225046813444000f, 1.202918693309688300f, + 1.202612295578050900f, + 1.202305853629797500f, 1.201999367476194400f, 1.201692837128510700f, + 1.201386262598016500f, + 1.201079643895983700f, 1.200772981033685800f, 1.200466274022397900f, + 1.200159522873396800f, + 1.199852727597960700f, 1.199545888207369700f, 1.199239004712905300f, + 1.198932077125851100f, + 1.198625105457491700f, 1.198318089719113200f, 1.198011029922004400f, + 1.197703926077454200f, + 1.197396778196754700f, 1.197089586291198500f, 1.196782350372080300f, + 1.196475070450696100f, + 1.196167746538343600f, 1.195860378646322700f, 1.195552966785933900f, + 1.195245510968480300f, + 1.194938011205265900f, 1.194630467507596500f, 1.194322879886780000f, + 1.194015248354125100f, + 1.193707572920943000f, 1.193399853598545500f, 1.193092090398246900f, + 1.192784283331362700f, + 1.192476432409210100f, 1.192168537643107900f, 1.191860599044376500f, + 1.191552616624337800f, + 1.191244590394315400f, 1.190936520365635000f, 1.190628406549622900f, + 1.190320248957608100f, + 1.190012047600920200f, 1.189703802490891000f, 1.189395513638853900f, + 1.189087181056143900f, + 1.188778804754097300f, 1.188470384744052100f, 1.188161921037348400f, + 1.187853413645327100f, + 1.187544862579331500f, 1.187236267850706000f, 1.186927629470796900f, + 1.186618947450951600f, + 1.186310221802519900f, 1.186001452536852300f, 1.185692639665301600f, + 1.185383783199222000f, + 1.185074883149969100f, 1.184765939528900500f, 1.184456952347374900f, + 1.184147921616753200f, + 1.183838847348397400f, 1.183529729553671500f, 1.183220568243940300f, + 1.182911363430571200f, + 1.182602115124932900f, 1.182292823338395100f, 1.181983488082330300f, + 1.181674109368111300f, + 1.181364687207113100f, 1.181055221610712400f, 1.180745712590287400f, + 1.180436160157217800f, + 1.180126564322885100f, 1.179816925098671900f, 1.179507242495962900f, + 1.179197516526144600f, + 1.178887747200604300f, 1.178577934530731700f, 1.178268078527917200f, + 1.177958179203553800f, + 1.177648236569035300f, 1.177338250635757700f, 1.177028221415118200f, + 1.176718148918515700f, + 1.176408033157350300f, 1.176097874143024600f, 1.175787671886942000f, + 1.175477426400507700f, + 1.175167137695128900f, 1.174856805782213500f, 1.174546430673171900f, + 1.174236012379415600f, + 1.173925550912357800f, 1.173615046283413200f, 1.173304498503998400f, + 1.172993907585530900f, + 1.172683273539430800f, 1.172372596377118800f, 1.172061876110017700f, + 1.171751112749551900f, + 1.171440306307147200f, 1.171129456794231200f, 1.170818564222232800f, + 1.170507628602582800f, + 1.170196649946713100f, 1.169885628266057900f, 1.169574563572052300f, + 1.169263455876133200f, + 1.168952305189739200f, 1.168641111524310700f, 1.168329874891289400f, + 1.168018595302118000f, + 1.167707272768241800f, 1.167395907301107100f, 1.167084498912162300f, + 1.166773047612856400f, + 1.166461553414641000f, 1.166150016328968600f, 1.165838436367293800f, + 1.165526813541072100f, + 1.165215147861761400f, 1.164903439340820900f, 1.164591687989710500f, + 1.164279893819892800f, + 1.163968056842831700f, 1.163656177069992500f, 1.163344254512841800f, + 1.163032289182848800f, + 1.162720281091483000f, 1.162408230250216100f, 1.162096136670521600f, + 1.161784000363874000f, + 1.161471821341749900f, 1.161159599615627000f, 1.160847335196984800f, + 1.160535028097304600f, + 1.160222678328068700f, 1.159910285900761700f, 1.159597850826869200f, + 1.159285373117878500f, + 1.158972852785278500f, 1.158660289840559800f, 1.158347684295214300f, + 1.158035036160735900f, + 1.157722345448619400f, 1.157409612170361600f, 1.157096836337461000f, + 1.156784017961417500f, + 1.156471157053732300f, 1.156158253625908700f, 1.155845307689450800f, + 1.155532319255865300f, + 1.155219288336659400f, 1.154906214943342700f, 1.154593099087426000f, + 1.154279940780421400f, + 1.153966740033842900f, 1.153653496859206000f, 1.153340211268028000f, + 1.153026883271827300f, + 1.152713512882124400f, 1.152400100110440700f, 1.152086644968299400f, + 1.151773147467225300f, + 1.151459607618745300f, 1.151146025434387000f, 1.150832400925680100f, + 1.150518734104155400f, + 1.150205024981345800f, 1.149891273568785400f, 1.149577479878009800f, + 1.149263643920556800f, + 1.148949765707964600f, 1.148635845251773800f, 1.148321882563526400f, + 1.148007877654766200f, + 1.147693830537038100f, 1.147379741221888500f, 1.147065609720865600f, + 1.146751436045519300f, + 1.146437220207400700f, 1.146122962218062600f, 1.145808662089060000f, + 1.145494319831947800f, + 1.145179935458284100f, 1.144865508979627800f, 1.144551040407539400f, + 1.144236529753581000f, + 1.143921977029316500f, 1.143607382246310600f, 1.143292745416130600f, + 1.142978066550344400f, + 1.142663345660522000f, 1.142348582758234900f, 1.142033777855056000f, + 1.141718930962559500f, + 1.141404042092321500f, 1.141089111255919800f, 1.140774138464933700f, + 1.140459123730943200f, + 1.140144067065530700f, 1.139828968480280300f, 1.139513827986776900f, + 1.139198645596607400f, + 1.138883421321360600f, 1.138568155172625700f, 1.138252847161994400f, + 1.137937497301059600f, + 1.137622105601416000f, 1.137306672074659900f, 1.136991196732388200f, + 1.136675679586200500f, + 1.136360120647697200f, 1.136044519928480800f, 1.135728877440154800f, + 1.135413193194324800f, + 1.135097467202597100f, 1.134781699476580300f, 1.134465890027884300f, + 1.134150038868120500f, + 1.133834146008902100f, 1.133518211461843200f, 1.133202235238559800f, + 1.132886217350669500f, + 1.132570157809791500f, 1.132254056627546300f, 1.131937913815556300f, + 1.131621729385444900f, + 1.131305503348837300f, 1.130989235717360100f, 1.130672926502642100f, + 1.130356575716312500f, + 1.130040183370002900f, 1.129723749475346000f, 1.129407274043976200f, + 1.129090757087529500f, + 1.128774198617643200f, 1.128457598645956600f, 1.128140957184109700f, + 1.127824274243744500f, + 1.127507549836505000f, 1.127190783974035800f, 1.126873976667983800f, + 1.126557127929996800f, + 1.126240237771724700f, 1.125923306204818400f, 1.125606333240930700f, + 1.125289318891715900f, + 1.124972263168829500f, 1.124655166083928800f, 1.124338027648672500f, + 1.124020847874721100f, + 1.123703626773736100f, 1.123386364357381200f, 1.123069060637320600f, + 1.122751715625221400f, + 1.122434329332750800f, 1.122116901771578400f, 1.121799432953375600f, + 1.121481922889814300f, + 1.121164371592568300f, 1.120846779073313400f, 1.120529145343726500f, + 1.120211470415486200f, + 1.119893754300272300f, 1.119575997009766300f, 1.119258198555651300f, + 1.118940358949611900f, + 1.118622478203333800f, 1.118304556328505200f, 1.117986593336814700f, + 1.117668589239953200f, + 1.117350544049612300f, 1.117032457777486200f, 1.116714330435269600f, + 1.116396162034659600f, + 1.116077952587353600f, 1.115759702105052000f, 1.115441410599455500f, + 1.115123078082267000f, + 1.114804704565190500f, 1.114486290059931900f, 1.114167834578198200f, + 1.113849338131698300f, + 1.113530800732142100f, 1.113212222391241500f, 1.112893603120710000f, + 1.112574942932261600f, + 1.112256241837613000f, 1.111937499848481900f, 1.111618716976587700f, + 1.111299893233650600f, + 1.110981028631393700f, 1.110662123181539900f, 1.110343176895814500f, + 1.110024189785944900f, + 1.109705161863658600f, 1.109386093140686000f, 1.109066983628758100f, + 1.108747833339607200f, + 1.108428642284968100f, 1.108109410476576300f, 1.107790137926169200f, + 1.107470824645485600f, + 1.107151470646265300f, 1.106832075940250600f, 1.106512640539184100f, + 1.106193164454811100f, + 1.105873647698877300f, 1.105554090283131100f, 1.105234492219321100f, + 1.104914853519198400f, + 1.104595174194514800f, 1.104275454257024300f, 1.103955693718482200f, + 1.103635892590644900f, + 1.103316050885270600f, 1.102996168614119000f, 1.102676245788951400f, + 1.102356282421530300f, + 1.102036278523620000f, 1.101716234106985700f, 1.101396149183395000f, + 1.101076023764616400f, + 1.100755857862419700f, 1.100435651488577100f, 1.100115404654861100f, + 1.099795117373046200f, + 1.099474789654909100f, 1.099154421512226600f, 1.098834012956778200f, + 1.098513564000344300f, + 1.098193074654706800f, 1.097872544931649100f, 1.097551974842956500f, + 1.097231364400415000f, + 1.096910713615813200f, 1.096590022500939700f, 1.096269291067585700f, + 1.095948519327543800f, + 1.095627707292607700f, 1.095306854974572800f, 1.094985962385235800f, + 1.094665029536395100f, + 1.094344056439850600f, 1.094023043107403200f, 1.093701989550856000f, + 1.093380895782013000f, + 1.093059761812680100f, 1.092738587654664300f, 1.092417373319774200f, + 1.092096118819820200f, + 1.091774824166613600f, 1.091453489371968100f, 1.091132114447697300f, + 1.090810699405617900f, + 1.090489244257547300f, 1.090167749015304300f, 1.089846213690709900f, + 1.089524638295585400f, + 1.089203022841754400f, 1.088881367341041800f, 1.088559671805274100f, + 1.088237936246279100f, + 1.087916160675885800f, 1.087594345105925300f, 1.087272489548229700f, + 1.086950594014632700f, + 1.086628658516969500f, 1.086306683067076900f, 1.085984667676792600f, + 1.085662612357956500f, + 1.085340517122409800f, 1.085018381981994500f, 1.084696206948555300f, + 1.084373992033937000f, + 1.084051737249986900f, 1.083729442608553300f, 1.083407108121486000f, + 1.083084733800636200f, + 1.082762319657857100f, 1.082439865705002500f, 1.082117371953928300f, + 1.081794838416491700f, + 1.081472265104551200f, 1.081149652029967000f, 1.080826999204601100f, + 1.080504306640315500f, + 1.080181574348975500f, 1.079858802342446900f, 1.079535990632596800f, + 1.079213139231294500f, + 1.078890248150409700f, 1.078567317401815100f, 1.078244346997383300f, + 1.077921336948988600f, + 1.077598287268508400f, 1.077275197967819000f, 1.076952069058800400f, + 1.076628900553332700f, + 1.076305692463297900f, 1.075982444800579700f, 1.075659157577062200f, + 1.075335830804633000f, + 1.075012464495178800f, 1.074689058660589700f, 1.074365613312755900f, + 1.074042128463569500f, + 1.073718604124924500f, 1.073395040308715400f, 1.073071437026839500f, + 1.072747794291194300f, + 1.072424112113678600f, 1.072100390506194500f, 1.071776629480643500f, + 1.071452829048929800f, + 1.071128989222958500f, 1.070805110014635900f, 1.070481191435870500f, + 1.070157233498571600f, + 1.069833236214650800f, 1.069509199596019800f, 1.069185123654592600f, + 1.068861008402285200f, + 1.068536853851013600f, 1.068212660012696700f, 1.067888426899253500f, + 1.067564154522606000f, + 1.067239842894676100f, 1.066915492027387600f, 1.066591101932666800f, + 1.066266672622439700f, + 1.065942204108635300f, 1.065617696403183400f, 1.065293149518014500f, + 1.064968563465062100f, + 1.064643938256259400f, 1.064319273903543000f, 1.063994570418849400f, + 1.063669827814116300f, + 1.063345046101285000f, 1.063020225292295300f, 1.062695365399091200f, + 1.062370466433616400f, + 1.062045528407815900f, 1.061720551333637600f, 1.061395535223029500f, + 1.061070480087941800f, + 1.060745385940325500f, 1.060420252792134000f, 1.060095080655320900f, + 1.059769869541841800f, + 1.059444619463654400f, 1.059119330432716700f, 1.058794002460989000f, + 1.058468635560432500f, + 1.058143229743009600f, 1.057817785020685100f, 1.057492301405424500f, + 1.057166778909195000f, + 1.056841217543965200f, 1.056515617321704500f, 1.056189978254385100f, + 1.055864300353978900f, + 1.055538583632461100f, 1.055212828101807200f, 1.054887033773993300f, + 1.054561200660999200f, + 1.054235328774803900f, 1.053909418127389400f, 1.053583468730738200f, + 1.053257480596834700f, + 1.052931453737664600f, 1.052605388165214700f, 1.052279283891473600f, + 1.051953140928431100f, + 1.051626959288079100f, 1.051300738982409800f, 1.050974480023417500f, + 1.050648182423098000f, + 1.050321846193448000f, 1.049995471346466300f, 1.049669057894152800f, + 1.049342605848508200f, + 1.049016115221536000f, 1.048689586025239700f, 1.048363018271625300f, + 1.048036411972699500f, + 1.047709767140470500f, 1.047383083786948700f, 1.047056361924144400f, + 1.046729601564071200f, + 1.046402802718742400f, 1.046075965400174300f, 1.045749089620383200f, + 1.045422175391386800f, + 1.045095222725206200f, 1.044768231633861100f, 1.044441202129375200f, + 1.044114134223771900f, + 1.043787027929076000f, 1.043459883257315400f, 1.043132700220517300f, + 1.042805478830712200f, + 1.042478219099930400f, 1.042150921040204200f, 1.041823584663568200f, + 1.041496209982056600f, + 1.041168797007707000f, 1.040841345752557200f, 1.040513856228645800f, + 1.040186328448014800f, + 1.039858762422705600f, 1.039531158164762400f, 1.039203515686230000f, + 1.038875834999155100f, + 1.038548116115585800f, 1.038220359047570500f, 1.037892563807160800f, + 1.037564730406408200f, + 1.037236858857366600f, 1.036908949172090900f, 1.036581001362636600f, + 1.036253015441062700f, + 1.035924991419427100f, 1.035596929309791300f, 1.035268829124216700f, + 1.034940690874766300f, + 1.034612514573505700f, 1.034284300232500000f, 1.033956047863817500f, + 1.033627757479526700f, + 1.033299429091697700f, 1.032971062712402700f, 1.032642658353714300f, + 1.032314216027707700f, + 1.031985735746457900f, 1.031657217522042900f, 1.031328661366541300f, + 1.031000067292032300f, + 1.030671435310598600f, 1.030342765434322200f, 1.030014057675287900f, + 1.029685312045581100f, + 1.029356528557288300f, 1.029027707222499100f, 1.028698848053302100f, + 1.028369951061789600f, + 1.028041016260053500f, 1.027712043660187600f, 1.027383033274288400f, + 1.027053985114451100f, + 1.026724899192775300f, 1.026395775521359500f, 1.026066614112305600f, + 1.025737414977715200f, + 1.025408178129692000f, 1.025078903580341600f, 1.024749591341769700f, + 1.024420241426085200f, + 1.024090853845396800f, 1.023761428611814600f, 1.023431965737451800f, + 1.023102465234420700f, + 1.022772927114837100f, 1.022443351390816400f, 1.022113738074476300f, + 1.021784087177936000f, + 1.021454398713315600f, 1.021124672692737000f, 1.020794909128323000f, + 1.020465108032198300f, + 1.020135269416488700f, 1.019805393293321100f, 1.019475479674824900f, + 1.019145528573129000f, + 1.018815540000365800f, 1.018485513968667500f, 1.018155450490168000f, + 1.017825349577003300f, + 1.017495211241309800f, 1.017165035495226400f, 1.016834822350892300f, + 1.016504571820448000f, + 1.016174283916036800f, 1.015843958649801600f, 1.015513596033888400f, + 1.015183196080442900f, + 1.014852758801613200f, 1.014522284209548900f, 1.014191772316400000f, + 1.013861223134318900f, + 1.013530636675459100f, 1.013200012951974700f, 1.012869351976022300f, + 1.012538653759758900f, + 1.012207918315344300f, 1.011877145654937400f, 1.011546335790700600f, + 1.011215488734796800f, + 1.010884604499389800f, 1.010553683096645900f, 1.010222724538731600f, + 1.009891728837815700f, + 1.009560696006067900f, 1.009229626055658800f, 1.008898518998761800f, + 1.008567374847549900f, + 1.008236193614199000f, 1.007904975310885300f, 1.007573719949786700f, + 1.007242427543082900f, + 1.006911098102953900f, 1.006579731641582500f, 1.006248328171152100f, + 1.005916887703846500f, + 1.005585410251852700f, 1.005253895827357800f, 1.004922344442551000f, + 1.004590756109621900f, + 1.004259130840762700f, 1.003927468648166100f, 1.003595769544025900f, + 1.003264033540538500f, + 1.002932260649900000f, 1.002600450884309800f, 1.002268604255967200f, + 1.001936720777072400f, + 1.001604800459829000f, 1.001272843316440000f, 1.000940849359111000f, + 1.000608818600048100f, + 1.000276751051459200f, 0.999944646725553720f, 0.999612505634541740f, + 0.999280327790635690f, + 0.998948113206048590f, 0.998615861892994560f, 0.998283573863690270f, + 0.997951249130352380f, + 0.997618887705200020f, 0.997286489600452630f, 0.996954054828332210f, + 0.996621583401061110f, + 0.996289075330862860f, 0.995956530629963810f, 0.995623949310589620f, + 0.995291331384969390f, + 0.994958676865332010f, 0.994625985763907820f, 0.994293258092929790f, + 0.993960493864630480f, + 0.993627693091245660f, 0.993294855785010760f, 0.992961981958163210f, + 0.992629071622942340f, + 0.992296124791587690f, 0.991963141476341460f, 0.991630121689446090f, + 0.991297065443145440f, + 0.990963972749685840f, 0.990630843621313260f, 0.990297678070276800f, + 0.989964476108825210f, + 0.989631237749210020f, 0.989297963003683330f, 0.988964651884498000f, + 0.988631304403909890f, + 0.988297920574174430f, 0.987964500407549910f, 0.987631043916294970f, + 0.987297551112669370f, + 0.986964022008935520f, 0.986630456617355380f, 0.986296854950194260f, + 0.985963217019717120f, + 0.985629542838190490f, 0.985295832417883540f, 0.984962085771065030f, + 0.984628302910006580f, + 0.984294483846980150f, 0.983960628594258810f, 0.983626737164118190f, + 0.983292809568833910f, + 0.982958845820684270f, 0.982624845931947320f, 0.982290809914904140f, + 0.981956737781835790f, + 0.981622629545024770f, 0.981288485216756160f, 0.980954304809314670f, + 0.980620088334987930f, + 0.980285835806063770f, 0.979951547234831130f, 0.979617222633581860f, + 0.979282862014607240f, + 0.978948465390201530f, 0.978614032772659240f, 0.978279564174275860f, + 0.977945059607349900f, + 0.977610519084179290f, 0.977275942617064740f, 0.976941330218307540f, + 0.976606681900209830f, + 0.976271997675076550f, 0.975937277555212310f, 0.975602521552924600f, + 0.975267729680520560f, + 0.974932901950310350f, 0.974598038374604350f, 0.974263138965714040f, + 0.973928203735953460f, + 0.973593232697636530f, 0.973258225863079970f, 0.972923183244600480f, + 0.972588104854516410f, + 0.972252990705148370f, 0.971917840808816710f, 0.971582655177844700f, + 0.971247433824555920f, + 0.970912176761274950f, 0.970576884000329040f, 0.970241555554045230f, + 0.969906191434753320f, + 0.969570791654783330f, 0.969235356226466500f, 0.968899885162136650f, + 0.968564378474127350f, + 0.968228836174775060f, 0.967893258276415700f, 0.967557644791388500f, + 0.967221995732032490f, + 0.966886311110688230f, 0.966550590939698640f, 0.966214835231406500f, + 0.965879043998157160f, + 0.965543217252296420f, 0.965207355006171270f, 0.964871457272131190f, + 0.964535524062525410f, + 0.964199555389706030f, 0.963863551266025300f, 0.963527511703836660f, + 0.963191436715496120f, + 0.962855326313359350f, 0.962519180509785130f, 0.962182999317132030f, + 0.961846782747760140f, + 0.961510530814032040f, 0.961174243528309820f, 0.960837920902958720f, + 0.960501562950343390f, + 0.960165169682831830f, 0.959828741112791590f, 0.959492277252591900f, + 0.959155778114604400f, + 0.958819243711200310f, 0.958482674054753960f, 0.958146069157639560f, + 0.957809429032232760f, + 0.957472753690911670f, 0.957136043146054050f, 0.956799297410040440f, + 0.956462516495251940f, + 0.956125700414070300f, 0.955788849178880300f, 0.955451962802066120f, + 0.955115041296014880f, + 0.954778084673113870f, 0.954441092945751630f, 0.954104066126319150f, + 0.953767004227207060f, + 0.953429907260809120f, 0.953092775239518630f, 0.952755608175731570f, + 0.952418406081844360f, + 0.952081168970254520f, 0.951743896853362140f, 0.951406589743566950f, + 0.951069247653271500f, + 0.950731870594878510f, 0.950394458580791970f, 0.950057011623418380f, + 0.949719529735163940f, + 0.949382012928437600f, 0.949044461215648560f, 0.948706874609207220f, + 0.948369253121526420f, + 0.948031596765018910f, 0.947693905552099870f, 0.947356179495185020f, + 0.947018418606691230f, + 0.946680622899037650f, 0.946342792384643360f, 0.946004927075930090f, + 0.945667026985319680f, + 0.945329092125236190f, 0.944991122508104350f, 0.944653118146349890f, + 0.944315079052401090f, + 0.943977005238685770f, 0.943638896717634900f, 0.943300753501679190f, + 0.942962575603250920f, + 0.942624363034784580f, 0.942286115808714690f, 0.941947833937478270f, + 0.941609517433512730f, + 0.941271166309256450f, 0.940932780577150460f, 0.940594360249635500f, + 0.940255905339155150f, + 0.939917415858152920f, 0.939578891819073720f, 0.939240333234364950f, + 0.938901740116473540f, + 0.938563112477849630f, 0.938224450330942590f, 0.937885753688204820f, + 0.937547022562088990f, + 0.937208256965048840f, 0.936869456909540490f, 0.936530622408019990f, + 0.936191753472946030f, + 0.935852850116777430f, 0.935513912351974450f, 0.935174940190999560f, + 0.934835933646314900f, + 0.934496892730385720f, 0.934157817455677160f, 0.933818707834655590f, + 0.933479563879790030f, + 0.933140385603548840f, 0.932801173018403480f, 0.932461926136825660f, + 0.932122644971287830f, + 0.931783329534265240f, 0.931443979838232900f, 0.931104595895668410f, + 0.930765177719049210f, + 0.930425725320855430f, 0.930086238713567440f, 0.929746717909666790f, + 0.929407162921637610f, + 0.929067573761963250f, 0.928727950443130500f, 0.928388292977625930f, + 0.928048601377937210f, + 0.927708875656554800f, 0.927369115825968480f, 0.927029321898671270f, + 0.926689493887155820f, + 0.926349631803916270f, 0.926009735661449170f, 0.925669805472250860f, + 0.925329841248820340f, + 0.924989843003656610f, 0.924649810749260110f, 0.924309744498133750f, + 0.923969644262779830f, + 0.923629510055703820f, 0.923289341889410480f, 0.922949139776407800f, + 0.922608903729203570f, + 0.922268633760306990f, 0.921928329882229390f, 0.921587992107482210f, + 0.921247620448579440f, + 0.920907214918035070f, 0.920566775528364410f, 0.920226302292085460f, + 0.919885795221715540f, + 0.919545254329774850f, 0.919204679628783720f, 0.918864071131263780f, + 0.918523428849739030f, + 0.918182752796733110f, 0.917842042984772340f, 0.917501299426383480f, + 0.917160522134094160f, + 0.916819711120434700f, 0.916478866397934850f, 0.916137987979127270f, + 0.915797075876544350f, + 0.915456130102721200f, 0.915115150670193110f, 0.914774137591496510f, + 0.914433090879170130f, + 0.914092010545752620f, 0.913750896603785280f, 0.913409749065809520f, + 0.913068567944367970f, + 0.912727353252005710f, 0.912386105001267270f, 0.912044823204700370f, + 0.911703507874852440f, + 0.911362159024272310f, 0.911020776665511290f, 0.910679360811120000f, + 0.910337911473652390f, + 0.909996428665661990f, 0.909654912399703860f, 0.909313362688335290f, + 0.908971779544113350f, + 0.908630162979597760f, 0.908288513007348140f, 0.907946829639926790f, + 0.907605112889895870f, + 0.907263362769819000f, 0.906921579292262250f, 0.906579762469791110f, + 0.906237912314974080f, + 0.905896028840379560f, 0.905554112058577170f, 0.905212161982139160f, + 0.904870178623637170f, + 0.904528161995645670f, 0.904186112110739510f, 0.903844028981494190f, + 0.903501912620488070f, + 0.903159763040298880f, 0.902817580253507450f, 0.902475364272694370f, + 0.902133115110441470f, + 0.901790832779333250f, 0.901448517291953520f, 0.901106168660889110f, + 0.900763786898726380f, + 0.900421372018054500f, 0.900078924031462610f, 0.899736442951541320f, + 0.899393928790883420f, + 0.899051381562081310f, 0.898708801277730340f, 0.898366187950425780f, + 0.898023541592764210f, + 0.897680862217344440f, 0.897338149836764960f, 0.896995404463627350f, + 0.896652626110532870f, + 0.896309814790084090f, 0.895966970514885940f, 0.895624093297543110f, + 0.895281183150662960f, + 0.894938240086852970f, 0.894595264118721810f, 0.894252255258880410f, + 0.893909213519939460f, + 0.893566138914512420f, 0.893223031455212530f, 0.892879891154655380f, + 0.892536718025457090f, + 0.892193512080234670f, 0.891850273331607600f, 0.891507001792195000f, + 0.891163697474618880f, + 0.890820360391500920f, 0.890476990555464480f, 0.890133587979135000f, + 0.889790152675137610f, + 0.889446684656100330f, 0.889103183934650930f, 0.888759650523418650f, + 0.888416084435035060f, + 0.888072485682131150f, 0.887728854277341050f, 0.887385190233298650f, + 0.887041493562639060f, + 0.886697764277999840f, 0.886354002392018110f, 0.886010207917333760f, + 0.885666380866586560f, + 0.885322521252418610f, 0.884978629087472270f, 0.884634704384391180f, + 0.884290747155821230f, + 0.883946757414407980f, 0.883602735172799640f, 0.883258680443644530f, + 0.882914593239592320f, + 0.882570473573294660f, 0.882226321457403320f, 0.881882136904572400f, + 0.881537919927456340f, + 0.881193670538710450f, 0.880849388750992610f, 0.880505074576960370f, + 0.880160728029273920f, + 0.879816349120593590f, 0.879471937863580690f, 0.879127494270899090f, + 0.878783018355212220f, + 0.878438510129186170f, 0.878093969605486800f, 0.877749396796782770f, + 0.877404791715742370f, + 0.877060154375035710f, 0.876715484787334630f, 0.876370782965310900f, + 0.876026048921639160f, + 0.875681282668993700f, 0.875336484220050390f, 0.874991653587487090f, + 0.874646790783981660f, + 0.874301895822214290f, 0.873956968714865500f, 0.873612009474616810f, + 0.873267018114152300f, + 0.872921994646155390f, 0.872576939083312460f, 0.872231851438309840f, + 0.871886731723835020f, + 0.871541579952577750f, 0.871196396137227660f, 0.870851180290476810f, + 0.870505932425017060f, + 0.870160652553543020f, 0.869815340688749220f, 0.869469996843331370f, + 0.869124621029987670f, + 0.868779213261415610f, 0.868433773550315810f, 0.868088301909388680f, + 0.867742798351335720f, + 0.867397262888861100f, 0.867051695534668210f, 0.866706096301463340f, + 0.866360465201952980f, + 0.866014802248844420f, 0.865669107454847490f, 0.865323380832671800f, + 0.864977622395029290f, + 0.864631832154632240f, 0.864286010124194040f, 0.863940156316430170f, + 0.863594270744056040f, + 0.863248353419789670f, 0.862902404356348570f, 0.862556423566453230f, + 0.862210411062823810f, + 0.861864366858181910f, 0.861518290965251340f, 0.861172183396755500f, + 0.860826044165420630f, + 0.860479873283972910f, 0.860133670765139580f, 0.859787436621650360f, + 0.859441170866234390f, + 0.859094873511623840f, 0.858748544570550610f, 0.858402184055747750f, + 0.858055791979950740f, + 0.857709368355894840f, 0.857362913196317630f, 0.857016426513956930f, + 0.856669908321551650f, + 0.856323358631843170f, 0.855976777457572280f, 0.855630164811482460f, + 0.855283520706317080f, + 0.854936845154821930f, 0.854590138169742830f, 0.854243399763827020f, + 0.853896629949823630f, + 0.853549828740481690f, 0.853202996148552880f, 0.852856132186788910f, + 0.852509236867942440f, + 0.852162310204768740f, 0.851815352210022470f, 0.851468362896461110f, + 0.851121342276842110f, + 0.850774290363923820f, 0.850427207170467380f, 0.850080092709233130f, + 0.849732946992984290f, + 0.849385770034483680f, 0.849038561846496730f, 0.848691322441788910f, + 0.848344051833126780f, + 0.847996750033279350f, 0.847649417055015060f, 0.847302052911105160f, + 0.846954657614320980f, + 0.846607231177434640f, 0.846259773613221020f, 0.845912284934454140f, + 0.845564765153910990f, + 0.845217214284368690f, 0.844869632338605130f, 0.844522019329400630f, + 0.844174375269535320f, + 0.843826700171791620f, 0.843478994048952440f, 0.843131256913801420f, + 0.842783488779124570f, + 0.842435689657707650f, 0.842087859562339000f, 0.841739998505806610f, + 0.841392106500900900f, + 0.841044183560412770f, 0.840696229697133760f, 0.840348244923857960f, + 0.840000229253379030f, + 0.839652182698493290f, 0.839304105271996950f, 0.838955996986687550f, + 0.838607857855364740f, + 0.838259687890827830f, 0.837911487105878820f, 0.837563255513319780f, + 0.837214993125953600f, + 0.836866699956585690f, 0.836518376018021260f, 0.836170021323067610f, + 0.835821635884532730f, + 0.835473219715225040f, 0.835124772827955830f, 0.834776295235535540f, + 0.834427786950777460f, + 0.834079247986494690f, 0.833730678355502630f, 0.833382078070616820f, + 0.833033447144653880f, + 0.832684785590432690f, 0.832336093420771970f, 0.831987370648492710f, + 0.831638617286416190f, + 0.831289833347364620f, 0.830941018844162600f, 0.830592173789634240f, + 0.830243298196606360f, + 0.829894392077905720f, 0.829545455446360270f, 0.829196488314800080f, + 0.828847490696055010f, + 0.828498462602957340f, 0.828149404048339590f, 0.827800315045035150f, + 0.827451195605879990f, + 0.827102045743709160f, 0.826752865471360950f, 0.826403654801672770f, + 0.826054413747485010f, + 0.825705142321637720f, 0.825355840536972420f, 0.825006508406332490f, + 0.824657145942561230f, + 0.824307753158504460f, 0.823958330067008030f, 0.823608876680918760f, + 0.823259393013085820f, + 0.822909879076357930f, 0.822560334883586490f, 0.822210760447622980f, + 0.821861155781319800f, + 0.821511520897531660f, 0.821161855809112830f, 0.820812160528920360f, + 0.820462435069811090f, + 0.820112679444643060f, 0.819762893666276530f, 0.819413077747571440f, + 0.819063231701390170f, + 0.818713355540594880f, 0.818363449278050270f, 0.818013512926620940f, + 0.817663546499172720f, + 0.817313550008573640f, 0.816963523467691410f, 0.816613466889396070f, + 0.816263380286557980f, + 0.815913263672048310f, 0.815563117058740630f, 0.815212940459508210f, + 0.814862733887226740f, + 0.814512497354771830f, 0.814162230875020380f, 0.813811934460851430f, + 0.813461608125143560f, + 0.813111251880778150f, 0.812760865740636440f, 0.812410449717600570f, + 0.812060003824555230f, + 0.811709528074384460f, 0.811359022479975040f, 0.811008487054213360f, + 0.810657921809988410f, + 0.810307326760189020f, 0.809956701917705080f, 0.809606047295428950f, + 0.809255362906252440f, + 0.808904648763069890f, 0.808553904878775760f, 0.808203131266265420f, + 0.807852327938436750f, + 0.807501494908186900f, 0.807150632188415760f, 0.806799739792023240f, + 0.806448817731910130f, + 0.806097866020979660f, 0.805746884672134620f, 0.805395873698280360f, + 0.805044833112322000f, + 0.804693762927166100f, 0.804342663155721230f, 0.803991533810895500f, + 0.803640374905599810f, + 0.803289186452744390f, 0.802937968465242240f, 0.802586720956006250f, + 0.802235443937950320f, + 0.801884137423990890f, 0.801532801427043530f, 0.801181435960026780f, + 0.800830041035858750f, + 0.800478616667459010f, 0.800127162867749210f, 0.799775679649650460f, + 0.799424167026086540f, + 0.799072625009981330f, 0.798721053614259490f, 0.798369452851848020f, + 0.798017822735673680f, + 0.797666163278665570f, 0.797314474493752810f, 0.796962756393865600f, + 0.796611008991936490f, + 0.796259232300897350f, 0.795907426333682830f, 0.795555591103226930f, + 0.795203726622466520f, + 0.794851832904338360f, 0.794499909961779990f, 0.794147957807731400f, + 0.793795976455132220f, + 0.793443965916924570f, 0.793091926206050400f, 0.792739857335452710f, + 0.792387759318077150f, + 0.792035632166868230f, 0.791683475894773720f, 0.791331290514740830f, + 0.790979076039718180f, + 0.790626832482656310f, 0.790274559856505520f, 0.789922258174218570f, + 0.789569927448748320f, + 0.789217567693048520f, 0.788865178920075130f, 0.788512761142783790f, + 0.788160314374132590f, + 0.787807838627079260f, 0.787455333914584220f, 0.787102800249607550f, + 0.786750237645110430f, + 0.786397646114056490f, 0.786045025669408700f, 0.785692376324132690f, + 0.785339698091194080f, + 0.784986990983559170f, 0.784634255014197040f, 0.784281490196075850f, + 0.783928696542166680f, + 0.783575874065440270f, 0.783223022778868350f, 0.782870142695425320f, + 0.782517233828084580f, + 0.782164296189822530f, 0.781811329793615120f, 0.781458334652439630f, + 0.781105310779275470f, + 0.780752258187101480f, 0.780399176888899150f, 0.780046066897649550f, + 0.779692928226336290f, + 0.779339760887942880f, 0.778986564895453810f, 0.778633340261856040f, + 0.778280087000135730f, + 0.777926805123281830f, 0.777573494644283050f, 0.777220155576129220f, + 0.776866787931812410f, + 0.776513391724324210f, 0.776159966966658680f, 0.775806513671809860f, + 0.775453031852772920f, + 0.775099521522545020f, 0.774745982694123090f, 0.774392415380506400f, + 0.774038819594694230f, + 0.773685195349686940f, 0.773331542658487140f, 0.772977861534096640f, + 0.772624151989520280f, + 0.772270414037761980f, 0.771916647691828660f, 0.771562852964726710f, + 0.771209029869463940f, + 0.770855178419050050f, 0.770501298626494410f, 0.770147390504808960f, + 0.769793454067005500f, + 0.769439489326096850f, 0.769085496295098040f, 0.768731474987023660f, + 0.768377425414890850f, + 0.768023347591716640f, 0.767669241530518850f, 0.767315107244318060f, + 0.766960944746133740f, + 0.766606754048988260f, 0.766252535165903970f, 0.765898288109903900f, + 0.765544012894013530f, + 0.765189709531257760f, 0.764835378034664170f, 0.764481018417259680f, + 0.764126630692073870f, + 0.763772214872136200f, 0.763417770970477140f, 0.763063299000129260f, + 0.762708798974124800f, + 0.762354270905498450f, 0.761999714807284790f, 0.761645130692519490f, + 0.761290518574240350f, + 0.760935878465484720f, 0.760581210379292380f, 0.760226514328703140f, + 0.759871790326757670f, + 0.759517038386499090f, 0.759162258520969860f, 0.758807450743214760f, + 0.758452615066278920f, + 0.758097751503208020f, 0.757742860067050380f, 0.757387940770853360f, + 0.757032993627667290f, + 0.756678018650541630f, 0.756323015852528700f, 0.755967985246680520f, + 0.755612926846050080f, + 0.755257840663692730f, 0.754902726712663120f, 0.754547585006018600f, + 0.754192415556816380f, + 0.753837218378114460f, 0.753481993482973400f, 0.753126740884452970f, + 0.752771460595615500f, + 0.752416152629523330f, 0.752060816999239660f, 0.751705453717829930f, + 0.751350062798359140f, + 0.750994644253894730f, 0.750639198097504010f, 0.750283724342255320f, + 0.749928223001219310f, + 0.749572694087465850f, 0.749217137614067500f, 0.748861553594096340f, + 0.748505942040627040f, + 0.748150302966733790f, 0.747794636385492150f, 0.747438942309979870f, + 0.747083220753273820f, + 0.746727471728453770f, 0.746371695248599140f, 0.746015891326790470f, + 0.745660059976110400f, + 0.745304201209641030f, 0.744948315040467210f, 0.744592401481673270f, + 0.744236460546344850f, + 0.743880492247569580f, 0.743524496598434670f, 0.743168473612029980f, + 0.742812423301444810f, + 0.742456345679769810f, 0.742100240760097840f, 0.741744108555520860f, + 0.741387949079133860f, + 0.741031762344030790f, 0.740675548363308620f, 0.740319307150063780f, + 0.739963038717393880f, + 0.739606743078398690f, 0.739250420246177380f, 0.738894070233831800f, + 0.738537693054463370f, + 0.738181288721174830f, 0.737824857247070810f, 0.737468398645255490f, + 0.737111912928835710f, + 0.736755400110918000f, 0.736398860204609870f, 0.736042293223021060f, + 0.735685699179260850f, + 0.735329078086440880f, 0.734972429957672760f, 0.734615754806068890f, + 0.734259052644744230f, + 0.733902323486812610f, 0.733545567345390890f, 0.733188784233595240f, + 0.732831974164544150f, + 0.732475137151356370f, 0.732118273207151170f, 0.731761382345050280f, + 0.731404464578174760f, + 0.731047519919648340f, 0.730690548382594280f, 0.730333549980137110f, + 0.729976524725403530f, + 0.729619472631519270f, 0.729262393711613280f, 0.728905287978813600f, + 0.728548155446249730f, + 0.728190996127053180f, 0.727833810034354990f, 0.727476597181288540f, + 0.727119357580987220f, + 0.726762091246585200f, 0.726404798191218950f, 0.726047478428024420f, + 0.725690131970139980f, + 0.725332758830703360f, 0.724975359022855150f, 0.724617932559735390f, + 0.724260479454485130f, + 0.723902999720247850f, 0.723545493370166160f, 0.723187960417385530f, + 0.722830400875050790f, + 0.722472814756308090f, 0.722115202074305680f, 0.721757562842191060f, + 0.721399897073114470f, + 0.721042204780225960f, 0.720684485976676230f, 0.720326740675618530f, + 0.719968968890205230f, + 0.719611170633591480f, 0.719253345918932090f, 0.718895494759382860f, + 0.718537617168101610f, + 0.718179713158245800f, 0.717821782742975370f, 0.717463825935449550f, + 0.717105842748830160f, + 0.716747833196278770f, 0.716389797290958090f, 0.716031735046032900f, + 0.715673646474667140f, + 0.715315531590027700f, 0.714957390405280950f, 0.714599222933594240f, + 0.714241029188137260f, + 0.713882809182079030f, 0.713524562928591010f, 0.713166290440844450f, + 0.712807991732011590f, + 0.712449666815266890f, 0.712091315703784260f, 0.711732938410739810f, + 0.711374534949309800f, + 0.711016105332671340f, 0.710657649574003460f, 0.710299167686484930f, + 0.709940659683296890f, + 0.709582125577619790f, 0.709223565382636760f, 0.708864979111530680f, + 0.708506366777485130f, + 0.708147728393686340f, 0.707789063973319310f, 0.707430373529572170f, + 0.707071657075632460f, + 0.706712914624688770f, 0.706354146189931750f, 0.705995351784551530f, + 0.705636531421740880f, + 0.705277685114692020f, 0.704918812876598410f, 0.704559914720655490f, + 0.704200990660058150f, + 0.703842040708003820f, 0.703483064877689630f, 0.703124063182313690f, + 0.702765035635076310f, + 0.702405982249177160f, 0.702046903037818250f, 0.701687798014201110f, + 0.701328667191529980f, + 0.700969510583008600f, 0.700610328201841660f, 0.700251120061236020f, + 0.699891886174398130f, + 0.699532626554536630f, 0.699173341214860190f, 0.698814030168578240f, + 0.698454693428902320f, + 0.698095331009043640f, 0.697735942922215520f, 0.697376529181631400f, + 0.697017089800505250f, + 0.696657624792053730f, 0.696298134169492380f, 0.695938617946039510f, + 0.695579076134912990f, + 0.695219508749331800f, 0.694859915802517050f, 0.694500297307689140f, + 0.694140653278070950f, + 0.693780983726884790f, 0.693421288667355530f, 0.693061568112707690f, + 0.692701822076166820f, + 0.692342050570960430f, 0.691982253610315510f, 0.691622431207461700f, + 0.691262583375628180f, + 0.690902710128045050f, 0.690542811477944610f, 0.690182887438558710f, + 0.689822938023121220f, + 0.689462963244866330f, 0.689102963117028790f, 0.688742937652845550f, + 0.688382886865552930f, + 0.688022810768389670f, 0.687662709374594510f, 0.687302582697406850f, + 0.686942430750068330f, + 0.686582253545819920f, 0.686222051097905130f, 0.685861823419566700f, + 0.685501570524050140f, + 0.685141292424600310f, 0.684780989134463280f, 0.684420660666887120f, + 0.684060307035119440f, + 0.683699928252410110f, 0.683339524332008840f, 0.682979095287166160f, + 0.682618641131135020f, + 0.682258161877167370f, 0.681897657538517720f, 0.681537128128440470f, + 0.681176573660190910f, + 0.680815994147026320f, 0.680455389602203310f, 0.680094760038981280f, + 0.679734105470619080f, + 0.679373425910376310f, 0.679012721371515250f, 0.678651991867297080f, + 0.678291237410985510f, + 0.677930458015843620f, 0.677569653695137220f, 0.677208824462131490f, + 0.676847970330092700f, + 0.676487091312289350f, 0.676126187421989040f, 0.675765258672461950f, + 0.675404305076978020f, + 0.675043326648808170f, 0.674682323401225250f, 0.674321295347501510f, + 0.673960242500911690f, + 0.673599164874730370f, 0.673238062482232950f, 0.672876935336696900f, + 0.672515783451398950f, + 0.672154606839618470f, 0.671793405514634180f, 0.671432179489727110f, + 0.671070928778178090f, + 0.670709653393269050f, 0.670348353348283690f, 0.669987028656505170f, + 0.669625679331219300f, + 0.669264305385711360f, 0.668902906833267590f, 0.668541483687176590f, + 0.668180035960725840f, + 0.667818563667205600f, 0.667457066819905800f, 0.667095545432117240f, + 0.666733999517132860f, + 0.666372429088244790f, 0.666010834158747840f, 0.665649214741936390f, + 0.665287570851105680f, + 0.664925902499553190f, 0.664564209700575500f, 0.664202492467472090f, + 0.663840750813541210f, + 0.663478984752084110f, 0.663117194296401260f, 0.662755379459794350f, + 0.662393540255567070f, + 0.662031676697022450f, 0.661669788797465960f, 0.661307876570202740f, + 0.660945940028538900f, + 0.660583979185782600f, 0.660221994055241400f, 0.659859984650225110f, + 0.659497950984043510f, + 0.659135893070007080f, 0.658773810921428500f, 0.658411704551619570f, + 0.658049573973894850f, + 0.657687419201568260f, 0.657325240247955020f, 0.656963037126372160f, + 0.656600809850135910f, + 0.656238558432565400f, 0.655876282886978410f, 0.655513983226695960f, + 0.655151659465038060f, + 0.654789311615326050f, 0.654426939690883280f, 0.654064543705032310f, + 0.653702123671098150f, + 0.653339679602405470f, 0.652977211512280050f, 0.652614719414049580f, + 0.652252203321041060f, + 0.651889663246583930f, 0.651527099204007310f, 0.651164511206641320f, + 0.650801899267818060f, + 0.650439263400868990f, 0.650076603619127890f, 0.649713919935928420f, + 0.649351212364604910f, + 0.648988480918494040f, 0.648625725610931460f, 0.648262946455255510f, + 0.647900143464803730f, + 0.647537316652916140f, 0.647174466032932490f, 0.646811591618193350f, + 0.646448693422041360f, + 0.646085771457818310f, 0.645722825738868860f, 0.645359856278536980f, + 0.644996863090167570f, + 0.644633846187107620f, 0.644270805582703550f, 0.643907741290304040f, + 0.643544653323257610f, + 0.643181541694913480f, 0.642818406418622980f, 0.642455247507736860f, + 0.642092064975608220f, + 0.641728858835589830f, 0.641365629101035340f, 0.641002375785300500f, + 0.640639098901740200f, + 0.640275798463712080f, 0.639912474484572560f, 0.639549126977681070f, + 0.639185755956396480f, + 0.638822361434078330f, 0.638458943424088490f, 0.638095501939787920f, + 0.637732036994540290f, + 0.637368548601708660f, 0.637005036774657030f, 0.636641501526751590f, + 0.636277942871357530f, + 0.635914360821842830f, 0.635550755391574910f, 0.635187126593922070f, + 0.634823474442254840f, + 0.634459798949942640f, 0.634096100130357660f, 0.633732377996871770f, + 0.633368632562857470f, + 0.633004863841689520f, 0.632641071846741790f, 0.632277256591390780f, + 0.631913418089012020f, + 0.631549556352983710f, 0.631185671396683470f, 0.630821763233490040f, + 0.630457831876783950f, + 0.630093877339945260f, 0.629729899636356280f, 0.629365898779399080f, + 0.629001874782456500f, + 0.628637827658913300f, 0.628273757422153860f, 0.627909664085564810f, + 0.627545547662532230f, + 0.627181408166443410f, 0.626817245610687520f, 0.626453060008652860f, + 0.626088851373730380f, + 0.625724619719310480f, 0.625360365058784670f, 0.624996087405546350f, + 0.624631786772988030f, + 0.624267463174504880f, 0.623903116623491180f, 0.623538747133343780f, + 0.623174354717459190f, + 0.622809939389234460f, 0.622445501162069090f, 0.622081040049361490f, + 0.621716556064512820f, + 0.621352049220923570f, 0.620987519531995270f, 0.620622967011131400f, + 0.620258391671734690f, + 0.619893793527210410f, 0.619529172590963410f, 0.619164528876399280f, + 0.618799862396925750f, + 0.618435173165949760f, 0.618070461196880800f, 0.617705726503127720f, + 0.617340969098100430f, + 0.616976188995210780f, 0.616611386207870040f, 0.616246560749491690f, + 0.615881712633488340f, + 0.615516841873275490f, 0.615151948482267840f, 0.614787032473881110f, + 0.614422093861533010f, + 0.614057132658640590f, 0.613692148878623000f, 0.613327142534899510f, + 0.612962113640889710f, + 0.612597062210015750f, 0.612231988255698470f, 0.611866891791361560f, + 0.611501772830428060f, + 0.611136631386322020f, 0.610771467472469460f, 0.610406281102295440f, + 0.610041072289227990f, + 0.609675841046694030f, 0.609310587388121830f, 0.608945311326941520f, + 0.608580012876582370f, + 0.608214692050476290f, 0.607849348862054220f, 0.607483983324749510f, + 0.607118595451995420f, + 0.606753185257225550f, 0.606387752753876020f, 0.606022297955381760f, + 0.605656820875180360f, + 0.605291321526709060f, 0.604925799923405670f, 0.604560256078710220f, + 0.604194690006061960f, + 0.603829101718902580f, 0.603463491230673220f, 0.603097858554815790f, + 0.602732203704774650f, + 0.602366526693992930f, 0.602000827535916330f, 0.601635106243990190f, + 0.601269362831660550f, + 0.600903597312375640f, 0.600537809699582810f, 0.600172000006731770f, + 0.599806168247271620f, + 0.599440314434653620f, 0.599074438582328780f, 0.598708540703749010f, + 0.598342620812368000f, + 0.597976678921638860f, 0.597610715045016950f, 0.597244729195957500f, + 0.596878721387916090f, + 0.596512691634350830f, 0.596146639948718640f, 0.595780566344478960f, + 0.595414470835091030f, + 0.595048353434014630f, 0.594682214154711790f, 0.594316053010643270f, + 0.593949870015273000f, + 0.593583665182063740f, 0.593217438524479500f, 0.592851190055986300f, + 0.592484919790049140f, + 0.592118627740135460f, 0.591752313919712170f, 0.591385978342248260f, + 0.591019621021212420f, + 0.590653241970074180f, 0.590286841202305120f, 0.589920418731375800f, + 0.589553974570759530f, + 0.589187508733928890f, 0.588821021234357310f, 0.588454512085520460f, + 0.588087981300892900f, + 0.587721428893951850f, 0.587354854878173850f, 0.586988259267036350f, + 0.586621642074019120f, + 0.586255003312600500f, 0.585888342996261690f, 0.585521661138483250f, + 0.585154957752746730f, + 0.584788232852535560f, 0.584421486451332410f, 0.584054718562622140f, + 0.583687929199888990f, + 0.583321118376619710f, 0.582954286106300290f, 0.582587432402417840f, + 0.582220557278461340f, + 0.581853660747918780f, 0.581486742824280810f, 0.581119803521037650f, + 0.580752842851679940f, + 0.580385860829700780f, 0.580018857468592270f, 0.579651832781848730f, + 0.579284786782964360f, + 0.578917719485433800f, 0.578550630902754050f, 0.578183521048421080f, + 0.577816389935933090f, + 0.577449237578788300f, 0.577082063990485340f, 0.576714869184524860f, + 0.576347653174406840f, + 0.575980415973633590f, 0.575613157595706530f, 0.575245878054129520f, + 0.574878577362406000f, + 0.574511255534040030f, 0.574143912582537940f, 0.573776548521405030f, + 0.573409163364148930f, + 0.573041757124277180f, 0.572674329815297640f, 0.572306881450720390f, + 0.571939412044054740f, + 0.571571921608812320f, 0.571204410158504090f, 0.570836877706642270f, + 0.570469324266740570f, + 0.570101749852312100f, 0.569734154476872480f, 0.569366538153936560f, + 0.568998900897020210f, + 0.568631242719641270f, 0.568263563635316600f, 0.567895863657565500f, + 0.567528142799906490f, + 0.567160401075860410f, 0.566792638498947680f, 0.566424855082689470f, + 0.566057050840608870f, + 0.565689225786228160f, 0.565321379933072190f, 0.564953513294665140f, + 0.564585625884531870f, + 0.564217717716199550f, 0.563849788803194140f, 0.563481839159044150f, + 0.563113868797277870f, + 0.562745877731423820f, 0.562377865975012940f, 0.562009833541575080f, + 0.561641780444642640f, + 0.561273706697747450f, 0.560905612314422150f, 0.560537497308201240f, + 0.560169361692618440f, + 0.559801205481210040f, 0.559433028687510990f, 0.559064831325059240f, + 0.558696613407391630f, + 0.558328374948046320f, 0.557960115960563050f, 0.557591836458480870f, + 0.557223536455341280f, + 0.556855215964685120f, 0.556486875000054000f, 0.556118513574991650f, + 0.555750131703040880f, + 0.555381729397746880f, 0.555013306672654360f, 0.554644863541308600f, + 0.554276400017257090f, + 0.553907916114046440f, 0.553539411845225590f, 0.553170887224342820f, + 0.552802342264947400f, + 0.552433776980590490f, 0.552065191384822350f, 0.551696585491195710f, + 0.551327959313262280f, + 0.550959312864576220f, 0.550590646158691240f, 0.550221959209161620f, + 0.549853252029543830f, + 0.549484524633393480f, 0.549115777034268170f, 0.548747009245725500f, + 0.548378221281323520f, + 0.548009413154622370f, 0.547640584879181100f, 0.547271736468561530f, + 0.546902867936324590f, + 0.546533979296032200f, 0.546165070561248080f, 0.545796141745535150f, + 0.545427192862458780f, + 0.545058223925583670f, 0.544689234948475210f, 0.544320225944701200f, + 0.543951196927828010f, + 0.543582147911424560f, 0.543213078909059120f, 0.542843989934301940f, + 0.542474881000723050f, + 0.542105752121893050f, 0.541736603311384620f, 0.541367434582769480f, + 0.540998245949621760f, + 0.540629037425515050f, 0.540259809024023600f, 0.539890560758723770f, + 0.539521292643190930f, + 0.539152004691002770f, 0.538782696915736770f, 0.538413369330970610f, + 0.538044021950284450f, + 0.537674654787257180f, 0.537305267855470390f, 0.536935861168504670f, + 0.536566434739941920f, + 0.536196988583365510f, 0.535827522712358230f, 0.535458037140505110f, + 0.535088531881390050f, + 0.534719006948599860f, 0.534349462355720230f, 0.533979898116337950f, + 0.533610314244041710f, + 0.533240710752419080f, 0.532871087655060300f, 0.532501444965554960f, + 0.532131782697493170f, + 0.531762100864467290f, 0.531392399480068670f, 0.531022678557890980f, + 0.530652938111527360f, + 0.530283178154571710f, 0.529913398700619820f, 0.529543599763266700f, + 0.529173781356109600f, + 0.528803943492745180f, 0.528434086186771010f, 0.528064209451786560f, + 0.527694313301390160f, + 0.527324397749182720f, 0.526954462808764120f, 0.526584508493736840f, + 0.526214534817702310f, + 0.525844541794263210f, 0.525474529437023890f, 0.525104497759587900f, + 0.524734446775560910f, + 0.524364376498548390f, 0.523994286942156220f, 0.523624178119992400f, + 0.523254050045663940f, + 0.522883902732780290f, 0.522513736194950230f, 0.522143550445783310f, + 0.521773345498891090f, + 0.521403121367884030f, 0.521032878066375100f, 0.520662615607976660f, + 0.520292334006301820f, + 0.519922033274965560f, 0.519551713427582000f, 0.519181374477767470f, + 0.518811016439137520f, + 0.518440639325310040f, 0.518070243149902240f, 0.517699827926532130f, + 0.517329393668819580f, + 0.516958940390383700f, 0.516588468104845820f, 0.516217976825826600f, + 0.515847466566947580f, + 0.515476937341832310f, 0.515106389164103120f, 0.514735822047384990f, + 0.514365236005302040f, + 0.513994631051479240f, 0.513624007199543600f, 0.513253364463121090f, + 0.512882702855839920f, + 0.512512022391327980f, 0.512141323083213470f, 0.511770604945127050f, + 0.511399867990697920f, + 0.511029112233557960f, 0.510658337687338040f, 0.510287544365671140f, + 0.509916732282189920f, + 0.509545901450527690f, 0.509175051884319660f, 0.508804183597200140f, + 0.508433296602805670f, + 0.508062390914772230f, 0.507691466546736580f, 0.507320523512337470f, + 0.506949561825212450f, + 0.506578581499001590f, 0.506207582547344550f, 0.505836564983881190f, + 0.505465528822253710f, + 0.505094474076103310f, 0.504723400759073290f, 0.504352308884806750f, + 0.503981198466947000f, + 0.503610069519139780f, 0.503238922055029400f, 0.502867756088262840f, + 0.502496571632486070f, + 0.502125368701347050f, 0.501754147308493770f, 0.501382907467574190f, + 0.501011649192238950f, + 0.500640372496137020f, 0.500269077392920150f, 0.499897763896239410f, + 0.499526432019746450f, + 0.499155081777094940f, 0.498783713181937540f, 0.498412326247929250f, + 0.498040920988724490f, + 0.497669497417978280f, 0.497298055549347750f, 0.496926595396488870f, + 0.496555116973059980f, + 0.496183620292718900f, 0.495812105369124070f, 0.495440572215935850f, + 0.495069020846813650f, + 0.494697451275419140f, 0.494325863515413130f, 0.493954257580458580f, + 0.493582633484217940f, + 0.493210991240354450f, 0.492839330862533120f, 0.492467652364417970f, + 0.492095955759675460f, + 0.491724241061971320f, 0.491352508284972070f, 0.490980757442346090f, + 0.490608988547760690f, + 0.490237201614885710f, 0.489865396657390210f, 0.489493573688943970f, + 0.489121732723218740f, + 0.488749873773885120f, 0.488377996854616250f, 0.488006101979084450f, + 0.487634189160962910f, + 0.487262258413926560f, 0.486890309751649490f, 0.486518343187807900f, + 0.486146358736077200f, + 0.485774356410135000f, 0.485402336223658360f, 0.485030298190324950f, + 0.484658242323814380f, + 0.484286168637805270f, 0.483914077145978560f, 0.483541967862014480f, + 0.483169840799594130f, + 0.482797695972400300f, 0.482425533394114920f, 0.482053353078422120f, + 0.481681155039005550f, + 0.481308939289549380f, 0.480936705843739820f, 0.480564454715261990f, + 0.480192185917803270f, + 0.479819899465050160f, 0.479447595370691370f, 0.479075273648415010f, + 0.478702934311909910f, + 0.478330577374866780f, 0.477958202850975230f, 0.477585810753927250f, + 0.477213401097414220f, + 0.476840973895128200f, 0.476468529160763100f, 0.476096066908011760f, + 0.475723587150569390f, + 0.475351089902130650f, 0.474978575176390750f, 0.474606042987046840f, + 0.474233493347795020f, + 0.473860926272333670f, 0.473488341774360670f, 0.473115739867574380f, + 0.472743120565675250f, + 0.472370483882362520f, 0.471997829831337810f, 0.471625158426301700f, + 0.471252469680957190f, + 0.470879763609006460f, 0.470507040224152460f, 0.470134299540099940f, + 0.469761541570552780f, + 0.469388766329217000f, 0.469015973829798090f, 0.468643164086002100f, + 0.468270337111537040f, + 0.467897492920109850f, 0.467524631525429830f, 0.467151752941205530f, + 0.466778857181146260f, + 0.466405944258963200f, 0.466033014188366350f, 0.465660066983068220f, + 0.465287102656780530f, + 0.464914121223215740f, 0.464541122696088100f, 0.464168107089110940f, + 0.463795074415999760f, + 0.463422024690469060f, 0.463048957926235630f, 0.462675874137015720f, + 0.462302773336526080f, + 0.461929655538485470f, 0.461556520756611410f, 0.461183369004623920f, + 0.460810200296242310f, + 0.460437014645186440f, 0.460063812065178160f, 0.459690592569938270f, + 0.459317356173189750f, + 0.458944102888655060f, 0.458570832730057170f, 0.458197545711121090f, + 0.457824241845570630f, + 0.457450921147131930f, 0.457077583629530550f, 0.456704229306492570f, + 0.456330858191746010f, + 0.455957470299017840f, 0.455584065642037350f, 0.455210644234532610f, + 0.454837206090234200f, + 0.454463751222871910f, 0.454090279646176210f, 0.453716791373879380f, + 0.453343286419712720f, + 0.452969764797409750f, 0.452596226520703360f, 0.452222671603327130f, + 0.451849100059016350f, + 0.451475511901505420f, 0.451101907144530910f, 0.450728285801828830f, + 0.450354647887135640f, + 0.449980993414189900f, 0.449607322396728900f, 0.449233634848492320f, + 0.448859930783219170f, + 0.448486210214649020f, 0.448112473156523420f, 0.447738719622582710f, + 0.447364949626569590f, + 0.446991163182225700f, 0.446617360303294910f, 0.446243541003520480f, + 0.445869705296646270f, + 0.445495853196417930f, 0.445121984716580210f, 0.444748099870879880f, + 0.444374198673063330f, + 0.444000281136877280f, 0.443626347276070590f, 0.443252397104390790f, + 0.442878430635587910f, + 0.442504447883411090f, 0.442130448861610240f, 0.441756433583937120f, + 0.441382402064142250f, + 0.441008354315978680f, 0.440634290353198510f, 0.440260210189554690f, + 0.439886113838801880f, + 0.439512001314693700f, 0.439137872630986080f, 0.438763727801433690f, + 0.438389566839793740f, + 0.438015389759822630f, 0.437641196575277220f, 0.437266987299916590f, + 0.436892761947498260f, + 0.436518520531782470f, 0.436144263066528480f, 0.435769989565496290f, + 0.435395700042447710f, + 0.435021394511143410f, 0.434647072985346380f, 0.434272735478819010f, + 0.433898382005324050f, + 0.433524012578626440f, 0.433149627212489670f, 0.432775225920679740f, + 0.432400808716961900f, + 0.432026375615101930f, 0.431651926628867530f, 0.431277461772025310f, + 0.430902981058344070f, + 0.430528484501591540f, 0.430153972115537800f, 0.429779443913952170f, + 0.429404899910604490f, + 0.429030340119266550f, 0.428655764553708960f, 0.428281173227704760f, + 0.427906566155026040f, + 0.427531943349445720f, 0.427157304824738350f, 0.426782650594677570f, + 0.426407980673039090f, + 0.426033295073598160f, 0.425658593810130330f, 0.425283876896413280f, + 0.424909144346223290f, + 0.424534396173339160f, 0.424159632391538870f, 0.423784853014600950f, + 0.423410058056305830f, + 0.423035247530432810f, 0.422660421450763490f, 0.422285579831078230f, + 0.421910722685159720f, + 0.421535850026790060f, 0.421160961869751720f, 0.420786058227829220f, + 0.420411139114805770f, + 0.420036204544466940f, 0.419661254530597550f, 0.419286289086983070f, + 0.418911308227410740f, + 0.418536311965666650f, 0.418161300315539220f, 0.417786273290816130f, + 0.417411230905285650f, + 0.417036173172737830f, 0.416661100106961610f, 0.416286011721748230f, + 0.415910908030888200f, + 0.415535789048172620f, 0.415160654787394280f, 0.414785505262345030f, + 0.414410340486818910f, + 0.414035160474608700f, 0.413659965239509710f, 0.413284754795316230f, + 0.412909529155823300f, + 0.412534288334827750f, 0.412159032346125280f, 0.411783761203513790f, + 0.411408474920790520f, + 0.411033173511753220f, 0.410657856990201580f, 0.410282525369933980f, + 0.409907178664751180f, + 0.409531816888453190f, 0.409156440054840590f, 0.408781048177715660f, + 0.408405641270879690f, + 0.408030219348136270f, 0.407654782423288010f, 0.407279330510138260f, + 0.406903863622492260f, + 0.406528381774153900f, 0.406152884978929480f, 0.405777373250624070f, + 0.405401846603045010f, + 0.405026305049998980f, 0.404650748605293040f, 0.404275177282736260f, + 0.403899591096136380f, + 0.403523990059303620f, 0.403148374186047210f, 0.402772743490177110f, + 0.402397097985504990f, + 0.402021437685841480f, 0.401645762604999350f, 0.401270072756790610f, + 0.400894368155027990f, + 0.400518648813525830f, 0.400142914746097480f, 0.399767165966558420f, + 0.399391402488723400f, + 0.399015624326407800f, 0.398639831493428740f, 0.398264024003602220f, + 0.397888201870746420f, + 0.397512365108678430f, 0.397136513731217500f, 0.396760647752182230f, + 0.396384767185391620f, + 0.396008872044666730f, 0.395632962343827170f, 0.395257038096694990f, + 0.394881099317091370f, + 0.394505146018838130f, 0.394129178215758820f, 0.393753195921675850f, + 0.393377199150413860f, + 0.393001187915796750f, 0.392625162231649010f, 0.392249122111796800f, + 0.391873067570065240f, + 0.391496998620281590f, 0.391120915276272410f, 0.390744817551864850f, + 0.390368705460887750f, + 0.389992579017168830f, 0.389616438234538010f, 0.389240283126824070f, + 0.388864113707858060f, + 0.388487929991470140f, 0.388111731991491180f, 0.387735519721753690f, + 0.387359293196089140f, + 0.386983052428331030f, 0.386606797432312350f, 0.386230528221866430f, + 0.385854244810828530f, + 0.385477947213032580f, 0.385101635442314900f, 0.384725309512510880f, + 0.384348969437456610f, + 0.383972615230989860f, 0.383596246906947210f, 0.383219864479167560f, + 0.382843467961488940f, + 0.382467057367749940f, 0.382090632711791060f, 0.381714194007451380f, + 0.381337741268572390f, + 0.380961274508994250f, 0.380584793742559550f, 0.380208298983109930f, + 0.379831790244487540f, + 0.379455267540536490f, 0.379078730885099520f, 0.378702180292021630f, + 0.378325615775147170f, + 0.377949037348320800f, 0.377572445025389230f, 0.377195838820197690f, + 0.376819218746593910f, + 0.376442584818424570f, 0.376065937049537060f, 0.375689275453780500f, + 0.375312600045002780f, + 0.374935910837054080f, 0.374559207843783660f, 0.374182491079041500f, + 0.373805760556679190f, + 0.373429016290547200f, 0.373052258294498230f, 0.372675486582383640f, + 0.372298701168057190f, + 0.371921902065371730f, 0.371545089288180640f, 0.371168262850339210f, + 0.370791422765701320f, + 0.370414569048123140f, 0.370037701711460170f, 0.369660820769568240f, + 0.369283926236305070f, + 0.368907018125527120f, 0.368530096451093140f, 0.368153161226860980f, + 0.367776212466689010f, + 0.367399250184437480f, 0.367022274393965340f, 0.366645285109133750f, + 0.366268282343803150f, + 0.365891266111834370f, 0.365514236427090080f, 0.365137193303431750f, + 0.364760136754723020f, + 0.364383066794826350f, 0.364005983437606320f, 0.363628886696926890f, + 0.363251776586652310f, + 0.362874653120648700f, 0.362497516312780990f, 0.362120366176916230f, + 0.361743202726920790f, + 0.361366025976661450f, 0.360988835940006750f, 0.360611632630824020f, + 0.360234416062982840f, + 0.359857186250351960f, 0.359479943206800550f, 0.359102686946199680f, + 0.358725417482419150f, + 0.358348134829330870f, 0.357970839000806010f, 0.357593530010716310f, + 0.357216207872935120f, + 0.356838872601334680f, 0.356461524209789380f, 0.356084162712172360f, + 0.355706788122359060f, + 0.355329400454223950f, 0.354951999721642100f, 0.354574585938490280f, + 0.354197159118644080f, + 0.353819719275981330f, 0.353442266424378930f, 0.353064800577714280f, + 0.352687321749866610f, + 0.352309829954713830f, 0.351932325206136210f, 0.351554807518012990f, + 0.351177276904224070f, + 0.350799733378650890f, 0.350422176955173910f, 0.350044607647675640f, + 0.349667025470037810f, + 0.349289430436142520f, 0.348911822559873850f, 0.348534201855114360f, + 0.348156568335749040f, + 0.347778922015661520f, 0.347401262908737570f, 0.347023591028862320f, + 0.346645906389921150f, + 0.346268209005801410f, 0.345890498890388980f, 0.345512776057572080f, + 0.345135040521238170f, + 0.344757292295274910f, 0.344379531393571970f, 0.344001757830017680f, + 0.343623971618502560f, + 0.343246172772916250f, 0.342868361307148980f, 0.342490537235092600f, + 0.342112700570637750f, + 0.341734851327677280f, 0.341356989520103240f, 0.340979115161808070f, + 0.340601228266685980f, + 0.340223328848629880f, 0.339845416921535030f, 0.339467492499295200f, + 0.339089555595806560f, + 0.338711606224964210f, 0.338333644400663940f, 0.337955670136803170f, + 0.337577683447278010f, + 0.337199684345986910f, 0.336821672846827290f, 0.336443648963697160f, + 0.336065612710496290f, + 0.335687564101123050f, 0.335309503149478110f, 0.334931429869461230f, + 0.334553344274972690f, + 0.334175246379914470f, 0.333797136198187240f, 0.333419013743693980f, + 0.333040879030336690f, + 0.332662732072017800f, 0.332284572882641680f, 0.331906401476111280f, + 0.331528217866331690f, + 0.331150022067206780f, 0.330771814092642610f, 0.330393593956544440f, + 0.330015361672817750f, + 0.329637117255370090f, 0.329258860718107450f, 0.328880592074938190f, + 0.328502311339769700f, + 0.328124018526509800f, 0.327745713649068180f, 0.327367396721353070f, + 0.326989067757275040f, + 0.326610726770743760f, 0.326232373775669270f, 0.325854008785963320f, + 0.325475631815536570f, + 0.325097242878301660f, 0.324718841988170470f, 0.324340429159055250f, + 0.323962004404870050f, + 0.323583567739527570f, 0.323205119176942720f, 0.322826658731029110f, + 0.322448186415702550f, + 0.322069702244877910f, 0.321691206232470550f, 0.321312698392397570f, + 0.320934178738574720f, + 0.320555647284919980f, 0.320177104045350440f, 0.319798549033783570f, + 0.319419982264138650f, + 0.319041403750333630f, 0.318662813506288670f, 0.318284211545923010f, + 0.317905597883156250f, + 0.317526972531909870f, 0.317148335506103940f, 0.316769686819660780f, + 0.316391026486501690f, + 0.316012354520548600f, 0.315633670935725030f, 0.315254975745953180f, + 0.314876268965157470f, + 0.314497550607261090f, 0.314118820686189180f, 0.313740079215866160f, + 0.313361326210216840f, + 0.312982561683167790f, 0.312603785648644220f, 0.312224998120573420f, + 0.311846199112882030f, + 0.311467388639496860f, 0.311088566714346650f, 0.310709733351358600f, + 0.310330888564462340f, + 0.309952032367586390f, 0.309573164774659850f, 0.309194285799613390f, + 0.308815395456376430f, + 0.308436493758880660f, 0.308057580721056660f, 0.307678656356835560f, + 0.307299720680150270f, + 0.306920773704932260f, 0.306541815445115160f, 0.306162845914631390f, + 0.305783865127415400f, + 0.305404873097400780f, 0.305025869838521590f, 0.304646855364713530f, + 0.304267829689911010f, + 0.303888792828050650f, 0.303509744793068030f, 0.303130685598899270f, + 0.302751615259482190f, + 0.302372533788753170f, 0.301993441200650910f, 0.301614337509113100f, + 0.301235222728077840f, + 0.300856096871485010f, 0.300476959953273060f, 0.300097811987382670f, + 0.299718652987753580f, + 0.299339482968325970f, 0.298960301943041680f, 0.298581109925841300f, + 0.298201906930667390f, + 0.297822692971461410f, 0.297443468062166820f, 0.297064232216726120f, + 0.296684985449082390f, + 0.296305727773180260f, 0.295926459202963120f, 0.295547179752376430f, + 0.295167889435364820f, + 0.294788588265873170f, 0.294409276257848300f, 0.294029953425235520f, + 0.293650619781982260f, + 0.293271275342035120f, 0.292891920119341120f, 0.292512554127848930f, + 0.292133177381505850f, + 0.291753789894261320f, 0.291374391680063520f, 0.290994982752862730f, + 0.290615563126608250f, + 0.290236132815249790f, 0.289856691832738880f, 0.289477240193025510f, + 0.289097777910061970f, + 0.288718304997799550f, 0.288338821470189910f, 0.287959327341186510f, + 0.287579822624741350f, + 0.287200307334808670f, 0.286820781485341620f, 0.286441245090293950f, + 0.286061698163620930f, + 0.285682140719276560f, 0.285302572771216960f, 0.284922994333397350f, + 0.284543405419773240f, + 0.284163806044301910f, 0.283784196220939370f, 0.283404575963643550f, + 0.283024945286371230f, + 0.282645304203081090f, 0.282265652727731130f, 0.281885990874279570f, + 0.281506318656686290f, + 0.281126636088910030f, 0.280746943184911340f, 0.280367239958650150f, + 0.279987526424086530f, + 0.279607802595182420f, 0.279228068485898210f, 0.278848324110196550f, + 0.278468569482039130f, + 0.278088804615388040f, 0.277709029524206950f, 0.277329244222458250f, + 0.276949448724106480f, + 0.276569643043115150f, 0.276189827193448200f, 0.275810001189071290f, + 0.275430165043948570f, + 0.275050318772046500f, 0.274670462387330010f, 0.274290595903766200f, + 0.273910719335321300f, + 0.273530832695961790f, 0.273150935999655950f, 0.272771029260370560f, + 0.272391112492074590f, + 0.272011185708736060f, 0.271631248924323390f, 0.271251302152806570f, + 0.270871345408154380f, + 0.270491378704337540f, 0.270111402055325910f, 0.269731415475089780f, + 0.269351418977600950f, + 0.268971412576829990f, 0.268591396286749500f, 0.268211370121331170f, + 0.267831334094547010f, + 0.267451288220370730f, 0.267071232512774700f, 0.266691166985733360f, + 0.266311091653219700f, + 0.265931006529208920f, 0.265550911627675250f, 0.265170806962593210f, + 0.264790692547939020f, + 0.264410568397687560f, 0.264030434525815760f, 0.263650290946299660f, + 0.263270137673115630f, + 0.262889974720241610f, 0.262509802101654310f, 0.262129619831332370f, + 0.261749427923253670f, + 0.261369226391396310f, 0.260989015249740050f, 0.260608794512263380f, + 0.260228564192946710f, + 0.259848324305769600f, 0.259468074864711960f, 0.259087815883755400f, + 0.258707547376880010f, + 0.258327269358068100f, 0.257946981841300490f, 0.257566684840560170f, + 0.257186378369829110f, + 0.256806062443089680f, 0.256425737074325920f, 0.256045402277520320f, + 0.255665058066657680f, + 0.255284704455721660f, 0.254904341458696390f, 0.254523969089567590f, + 0.254143587362319620f, + 0.253763196290938850f, 0.253382795889410710f, 0.253002386171721110f, + 0.252621967151857420f, + 0.252241538843805680f, 0.251861101261554090f, 0.251480654419089730f, + 0.251100198330400150f, + 0.250719733009474530f, 0.250339258470300590f, 0.249958774726868170f, + 0.249578281793165680f, + 0.249197779683183660f, 0.248817268410911650f, 0.248436747990339490f, + 0.248056218435458720f, + 0.247675679760259450f, 0.247295131978733870f, 0.246914575104873220f, + 0.246534009152669040f, + 0.246153434136114490f, 0.245772850069201410f, 0.245392256965923620f, + 0.245011654840274010f, + 0.244631043706245800f, 0.244250423577833860f, 0.243869794469031620f, + 0.243489156393834590f, + 0.243108509366237320f, 0.242727853400234670f, 0.242347188509823150f, + 0.241966514708997830f, + 0.241585832011755900f, 0.241205140432093070f, 0.240824439984007180f, + 0.240443730681495050f, + 0.240063012538553830f, 0.239682285569182310f, 0.239301549787377890f, + 0.238920805207139960f, + 0.238540051842467020f, 0.238159289707357810f, 0.237778518815812740f, + 0.237397739181830820f, + 0.237016950819413100f, 0.236636153742559610f, 0.236255347965270780f, + 0.235874533501548580f, + 0.235493710365393630f, 0.235112878570808560f, 0.234732038131795020f, + 0.234351189062355030f, + 0.233970331376492150f, 0.233589465088208580f, 0.233208590211508550f, + 0.232827706760394850f, + 0.232446814748872410f, 0.232065914190945020f, 0.231685005100616930f, + 0.231304087491893930f, + 0.230923161378780380f, 0.230542226775282770f, 0.230161283695406500f, + 0.229780332153157300f, + 0.229399372162542610f, 0.229018403737568290f, 0.228637426892242400f, + 0.228256441640571880f, + 0.227875447996564060f, 0.227494445974227850f, 0.227113435587570770f, + 0.226732416850602300f, + 0.226351389777330990f, 0.225970354381765690f, 0.225589310677916880f, + 0.225208258679793520f, + 0.224827198401406690f, 0.224446129856766040f, 0.224065053059883250f, + 0.223683968024768950f, + 0.223302874765434120f, 0.222921773295891380f, 0.222540663630151820f, + 0.222159545782228660f, + 0.221778419766134050f, 0.221397285595880480f, 0.221016143285482050f, + 0.220634992848951380f, + 0.220253834300303180f, 0.219872667653551100f, 0.219491492922709110f, + 0.219110310121792800f, + 0.218729119264816280f, 0.218347920365795780f, 0.217966713438746380f, + 0.217585498497683580f, + 0.217204275556624420f, 0.216823044629584520f, 0.216441805730581500f, + 0.216060558873631570f, + 0.215679304072752960f, 0.215298041341962870f, 0.214916770695278810f, + 0.214535492146719880f, + 0.214154205710303750f, 0.213772911400050090f, 0.213391609229977570f, + 0.213010299214105140f, + 0.212628981366453330f, 0.212247655701041290f, 0.211866322231890090f, + 0.211484980973019880f, + 0.211103631938451000f, 0.210722275142205480f, 0.210340910598303870f, + 0.209959538320768660f, + 0.209578158323621420f, 0.209196770620883960f, 0.208815375226579670f, + 0.208433972154730530f, + 0.208052561419360520f, 0.207671143034492080f, 0.207289717014149830f, + 0.206908283372357230f, + 0.206526842123138070f, 0.206145393280517730f, 0.205763936858520150f, + 0.205382472871171230f, + 0.205001001332495910f, 0.204619522256519300f, 0.204238035657268250f, + 0.203856541548768030f, + 0.203475039945045950f, 0.203093530860128300f, 0.202712014308041620f, + 0.202330490302814110f, + 0.201948958858472420f, 0.201567419989045200f, 0.201185873708560170f, + 0.200804320031045230f, + 0.200422758970529910f, 0.200041190541042220f, 0.199659614756612230f, + 0.199278031631268500f, + 0.198896441179041650f, 0.198514843413961220f, 0.198133238350057030f, + 0.197751626001360480f, + 0.197370006381901520f, 0.196988379505712050f, 0.196606745386822960f, + 0.196225104039265410f, + 0.195843455477072190f, 0.195461799714274460f, 0.195080136764905570f, + 0.194698466642997730f, + 0.194316789362583340f, 0.193935104937696560f, 0.193553413382369890f, + 0.193171714710637930f, + 0.192790008936534220f, 0.192408296074092570f, 0.192026576137348330f, + 0.191644849140335360f, + 0.191263115097089540f, 0.190881374021645320f, 0.190499625928039040f, + 0.190117870830306100f, + 0.189736108742482030f, 0.189354339678604100f, 0.188972563652707950f, + 0.188590780678831250f, + 0.188208990771010640f, 0.187827193943283040f, 0.187445390209686870f, + 0.187063579584259070f, + 0.186681762081038650f, 0.186299937714063470f, 0.185918106497371700f, + 0.185536268445003070f, + 0.185154423570995760f, 0.184772571889390000f, 0.184390713414225000f, + 0.184008848159540110f, + 0.183626976139376310f, 0.183245097367773090f, 0.182863211858771880f, + 0.182481319626412670f, + 0.182099420684737420f, 0.181717515047787020f, 0.181335602729602590f, + 0.180953683744226880f, + 0.180571758105701030f, 0.180189825828068250f, 0.179807886925370670f, + 0.179425941411650660f, + 0.179043989300952110f, 0.178662030607317450f, 0.178280065344791100f, + 0.177898093527416370f, + 0.177516115169236820f, 0.177134130284297610f, 0.176752138886642350f, + 0.176370140990316640f, + 0.175988136609365020f, 0.175606125757832240f, 0.175224108449764660f, + 0.174842084699207030f, + 0.174460054520206240f, 0.174078017926807490f, 0.173695974933058080f, + 0.173313925553004180f, + 0.172931869800692250f, 0.172549807690170230f, 0.172167739235484620f, + 0.171785664450683800f, + 0.171403583349815180f, 0.171021495946926340f, 0.170639402256066410f, + 0.170257302291283000f, + 0.169875196066625710f, 0.169493083596143100f, 0.169110964893883830f, + 0.168728839973898290f, + 0.168346708850235140f, 0.167964571536945220f, 0.167582428048078130f, + 0.167200278397683750f, + 0.166818122599813570f, 0.166435960668517400f, 0.166053792617847200f, + 0.165671618461853270f, + 0.165289438214587970f, 0.164907251890102520f, 0.164525059502448390f, + 0.164142861065678550f, + 0.163760656593844480f, 0.163378446100999640f, 0.162996229601196390f, + 0.162614007108487250f, + 0.162231778636926370f, 0.161849544200566300f, 0.161467303813461580f, + 0.161085057489665670f, + 0.160702805243232240f, 0.160320547088216470f, 0.159938283038672050f, + 0.159556013108654580f, + 0.159173737312218650f, 0.158791455663418930f, 0.158409168176311760f, + 0.158026874864951870f, + 0.157644575743395960f, 0.157262270825699210f, 0.156879960125918730f, + 0.156497643658110590f, + 0.156115321436331000f, 0.155732993474637760f, 0.155350659787087090f, + 0.154968320387737170f, + 0.154585975290645110f, 0.154203624509868190f, 0.153821268059465250f, + 0.153438905953493550f, + 0.153056538206012340f, 0.152674164831079730f, 0.152291785842754070f, + 0.151909401255095250f, + 0.151527011082161540f, 0.151144615338013210f, 0.150762214036709470f, + 0.150379807192309620f, + 0.149997394818874590f, 0.149614976930463660f, 0.149232553541138180f, + 0.148850124664957870f, + 0.148467690315984390f, 0.148085250508278370f, 0.147702805255900570f, + 0.147320354572913260f, + 0.146937898473377210f, 0.146555436971355090f, 0.146172970080908520f, + 0.145790497816099230f, + 0.145408020190990560f, 0.145025537219644170f, 0.144643048916123810f, + 0.144260555294492000f, + 0.143878056368811510f, 0.143495552153146630f, 0.143113042661560050f, + 0.142730527908116440f, + 0.142348007906879320f, 0.141965482671912420f, 0.141582952217280980f, + 0.141200416557048680f, + 0.140817875705281120f, 0.140435329676042390f, 0.140052778483398480f, + 0.139670222141414250f, + 0.139287660664154770f, 0.138905094065686600f, 0.138522522360074780f, + 0.138139945561386200f, + 0.137757363683686740f, 0.137374776741042340f, 0.136992184747520560f, + 0.136609587717187310f, + 0.136226985664110460f, 0.135844378602356760f, 0.135461766545993150f, + 0.135079149509088060f, + 0.134696527505708320f, 0.134313900549922760f, 0.133931268655799020f, + 0.133548631837404950f, + 0.133165990108809860f, 0.132783343484081580f, 0.132400691977289760f, + 0.132018035602502530f, + 0.131635374373789940f, 0.131252708305220960f, 0.130870037410864640f, + 0.130487361704791580f, + 0.130104681201070800f, 0.129721995913773260f, 0.129339305856968730f, + 0.128956611044727220f, + 0.128573911491120210f, 0.128191207210217570f, 0.127808498216091110f, + 0.127425784522811530f, + 0.127043066144449680f, 0.126660343095077900f, 0.126277615388766920f, + 0.125894883039589430f, + 0.125512146061616980f, 0.125129404468921260f, 0.124746658275575490f, + 0.124363907495651240f, + 0.123981152143222060f, 0.123598392232359880f, 0.123215627777138580f, + 0.122832858791630880f, + 0.122450085289909640f, 0.122067307286049230f, 0.121684524794122440f, + 0.121301737828203960f, + 0.120918946402367330f, 0.120536150530686250f, 0.120153350227235940f, + 0.119770545506089950f, + 0.119387736381323830f, 0.119004922867011920f, 0.118622104977228730f, + 0.118239282726050290f, + 0.117856456127550970f, 0.117473625195807100f, 0.117090789944893860f, + 0.116707950388886520f, + 0.116325106541861910f, 0.115942258417895240f, 0.115559406031063570f, + 0.115176549395442460f, + 0.114793688525109290f, 0.114410823434140360f, 0.114027954136612060f, + 0.113645080646602280f, + 0.113262202978187320f, 0.112879321145445350f, 0.112496435162453430f, + 0.112113545043288730f, + 0.111730650802029900f, 0.111347752452754000f, 0.110964850009539970f, + 0.110581943486465610f, + 0.110199032897608850f, 0.109816118257049110f, 0.109433199578864170f, + 0.109050276877133770f, + 0.108667350165936400f, 0.108284419459350770f, 0.107901484771457020f, + 0.107518546116333660f, + 0.107135603508061170f, 0.106752656960718350f, 0.106369706488385940f, + 0.105986752105143480f, + 0.105603793825070680f, 0.105220831662248700f, 0.104837865630757090f, + 0.104454895744677270f, + 0.104071922018089540f, 0.103688944465074300f, 0.103305963099713400f, + 0.102922977936087120f, + 0.102539988988277600f, 0.102156996270365800f, 0.101773999796432830f, + 0.101390999580561250f, + 0.101007995636832020f, 0.100624987979327970f, 0.100241976622130760f, + 0.099858961579322170f, + 0.099475942864985456f, 0.099092920493202258f, 0.098709894478056073f, + 0.098326864833628791f, + 0.097943831574004214f, 0.097560794713264939f, 0.097177754265493674f, + 0.096794710244774623f, + 0.096411662665190329f, 0.096028611540825232f, 0.095645556885762609f, + 0.095262498714085819f, + 0.094879437039879722f, 0.094496371877227495f, 0.094113303240214247f, + 0.093730231142923864f, + 0.093347155599440373f, 0.092964076623849271f, 0.092580994230234359f, + 0.092197908432681386f, + 0.091814819245274432f, 0.091431726682099479f, 0.091048630757241303f, + 0.090665531484784803f, + 0.090282428878816323f, 0.089899322953420582f, 0.089516213722684160f, + 0.089133101200692441f, + 0.088749985401530951f, 0.088366866339286629f, 0.087983744028044805f, + 0.087600618481892656f, + 0.087217489714916191f, 0.086834357741201490f, 0.086451222574836131f, + 0.086068084229906014f, + 0.085684942720498897f, 0.085301798060701386f, 0.084918650264600160f, + 0.084535499346283349f, + 0.084152345319837438f, 0.083769188199350780f, 0.083386027998910095f, + 0.083002864732603973f, + 0.082619698414519799f, 0.082236529058745025f, 0.081853356679368619f, + 0.081470181290477811f, + 0.081087002906161790f, 0.080703821540508452f, 0.080320637207605849f, + 0.079937449921543474f, + 0.079554259696409127f, 0.079171066546292510f, 0.078787870485282088f, + 0.078404671527466441f, + 0.078021469686935602f, 0.077638264977777913f, 0.077255057414083589f, + 0.076871847009941652f, + 0.076488633779441206f, 0.076105417736672773f, 0.075722198895725248f, + 0.075338977270689375f, + 0.074955752875654230f, 0.074572525724710764f, 0.074189295831948693f, + 0.073806063211457842f, + 0.073422827877329483f, 0.073039589843653177f, 0.072656349124520389f, + 0.072273105734021334f, + 0.071889859686246352f, 0.071506610995287156f, 0.071123359675233852f, + 0.070740105740178361f, + 0.070356849204211397f, 0.069973590081423773f, 0.069590328385907715f, + 0.069207064131753759f, + 0.068823797333054326f, 0.068440528003900616f, 0.068057256158383886f, + 0.067673981810596848f, + 0.067290704974630494f, 0.066907425664577733f, 0.066524143894529736f, + 0.066140859678579578f, + 0.065757573030819083f, 0.065374283965340146f, 0.064990992496236119f, + 0.064607698637598646f, + 0.064224402403521202f, 0.063841103808096086f, 0.063457802865415636f, + 0.063074499589573618f, + 0.062691193994662109f, 0.062307886094775049f, 0.061924575904005130f, + 0.061541263436445129f, + 0.061157948706189229f, 0.060774631727329942f, 0.060391312513961619f, + 0.060007991080177375f, + 0.059624667440070382f, 0.059241341607735261f, 0.058858013597264912f, + 0.058474683422754095f, + 0.058091351098295878f, 0.057708016637985186f, 0.057324680055915692f, + 0.056941341366181127f, + 0.056558000582876661f, 0.056174657720095743f, 0.055791312791933681f, + 0.055407965812484541f, + 0.055024616795842439f, 0.054641265756102911f, 0.054257912707359794f, + 0.053874557663708772f, + 0.053491200639244271f, 0.053107841648060788f, 0.052724480704254229f, + 0.052341117821918783f, + 0.051957753015150501f, 0.051574386298044173f, 0.051191017684694640f, + 0.050807647189198162f, + 0.050424274825649297f, 0.050040900608144430f, 0.049657524550778251f, + 0.049274146667647289f, + 0.048890766972846805f, 0.048507385480472134f, 0.048124002204620014f, + 0.047740617159385448f, + 0.047357230358865306f, 0.046973841817155179f, 0.046590451548350717f, + 0.046207059566548990f, + 0.045823665885845313f, 0.045440270520336883f, 0.045056873484119603f, + 0.044673474791289434f, + 0.044290074455943754f, 0.043906672492178188f, 0.043523268914090238f, + 0.043139863735776100f, + 0.042756456971332048f, 0.042373048634855741f, 0.041989638740443119f, + 0.041606227302191955f, + 0.041222814334198304f, 0.040839399850560058f, 0.040455983865373815f, + 0.040072566392736257f, + 0.039689147446745419f, 0.039305727041497644f, 0.038922305191091085f, + 0.038538881909622631f, + 0.038155457211189216f, 0.037772031109889144f, 0.037388603619819022f, + 0.037005174755077273f, + 0.036621744529761024f, 0.036238312957967478f, 0.035854880053795196f, + 0.035471445831341021f, + 0.035088010304703626f, 0.034704573487980395f, 0.034321135395268765f, + 0.033937696040667535f, + 0.033554255438273790f, 0.033170813602186440f, 0.032787370546502645f, + 0.032403926285321405f, + 0.032020480832740429f, 0.031637034202857461f, 0.031253586409771626f, + 0.030870137467580314f, + 0.030486687390382738f, 0.030103236192276818f, 0.029719783887360508f, + 0.029336330489733147f, + 0.028952876013492331f, 0.028569420472737472f, 0.028185963881566689f, + 0.027802506254078142f, + 0.027419047604371360f, 0.027035587946544135f, 0.026652127294696067f, + 0.026268665662925468f, + 0.025885203065330677f, 0.025501739516011413f, 0.025118275029065638f, + 0.024734809618593138f, + 0.024351343298691951f, 0.023967876083461924f, 0.023584407987001611f, + 0.023200939023409587f, + 0.022817469206785804f, 0.022433998551228459f, 0.022050527070837558f, + 0.021667054779711814f, + 0.021283581691949955f, 0.020900107821652084f, 0.020516633182916549f, + 0.020133157789843505f, + 0.019749681656531803f, 0.019366204797080316f, 0.018982727225589285f, + 0.018599248956157190f, + 0.018215770002884327f, 0.017832290379869671f, 0.017448810101212228f, + 0.017065329181012358f, + 0.016681847633368677f, 0.016298365472381587f, 0.015914882712149747f, + 0.015531399366773606f, + 0.015147915450352307f, 0.014764430976985016f, 0.014380945960772247f, + 0.013997460415812761f, + 0.013613974356207112f, 0.013230487796054543f, 0.012847000749454314f, + 0.012463513230507034f, + 0.012080025253311559f, 0.011696536831968529f, 0.011313047980577277f, + 0.010929558713237145f, + 0.010546069044048827f, 0.010162578987111254f, 0.009779088556525145f, + 0.009395597766389905f, + 0.009012106630804949f, 0.008628615163871038f, 0.008245123379687167f, + 0.007861631292354124f, + 0.007478138915970929f, 0.007094646264638386f, 0.006711153352455981f, + 0.006327660193523208f, + 0.005944166801940901f, 0.005560673191808128f, 0.005177179377225743f, + 0.004793685372293270f, + 0.004410191191110246f, 0.004026696847777542f, 0.003643202356394263f, + 0.003259707731061291f, + 0.002876212985878184f, 0.002492718134944503f, 0.002109223192361147f, + 0.001725728172227238f, + 0.001342233088643682f, 0.000958737955710053f, 0.000575242787525925f, + 0.000191747598192208f +}; + #endif + +/** + @brief Weights Table + */ + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for(i = 0; i< N; i++)
+  { 
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Converted the output to q15 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q15 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + + const q15_t __ALIGNED(4) WeightsQ15_128[256] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7fe9, (q15_t)0xfb4a, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f87, (q15_t)0xf505, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7ed5, (q15_t)0xeec7, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7dd6, (q15_t)0xe893, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7c89, (q15_t)0xe26d, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7aef, (q15_t)0xdc5a, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7909, (q15_t)0xd65d, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x76d9, (q15_t)0xd079, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x745f, (q15_t)0xcab3, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x719e, (q15_t)0xc50e, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6e96, (q15_t)0xbf8d, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6b4a, (q15_t)0xba33, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x67bd, (q15_t)0xb505, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x63ef, (q15_t)0xb005, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x5fe3, (q15_t)0xab36, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5b9d, (q15_t)0xa69c, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x571d, (q15_t)0xa239, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5269, (q15_t)0x9e0f, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4d81, (q15_t)0x9a23, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4869, (q15_t)0x9674, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4325, (q15_t)0x9307, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3db8, (q15_t)0x8fdd, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3824, (q15_t)0x8cf9, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x326e, (q15_t)0x8a5b, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2c98, (q15_t)0x8806, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x26a8, (q15_t)0x85fb, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x209f, (q15_t)0x843b, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1a82, (q15_t)0x82c7, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x1455, (q15_t)0x81a1, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1139, (q15_t)0x812b, (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xe1b, (q15_t)0x80c8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xafb, (q15_t)0x8079, (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x7d9, (q15_t)0x803e, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x324, (q15_t)0x800a, (q15_t)0x192, (q15_t)0x8003 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_128[128] = { + (q15_t)0x7fff, (q15_t)0x7ffa, (q15_t)0x7ff0, (q15_t)0x7fe1, (q15_t)0x7fce, (q15_t)0x7fb5, (q15_t)0x7f97, (q15_t)0x7f75, + (q15_t)0x7f4d, (q15_t)0x7f21, (q15_t)0x7ef0, (q15_t)0x7eba, (q15_t)0x7e7f, (q15_t)0x7e3f, (q15_t)0x7dfa, (q15_t)0x7db0, + (q15_t)0x7d62, (q15_t)0x7d0f, (q15_t)0x7cb7, (q15_t)0x7c5a, (q15_t)0x7bf8, (q15_t)0x7b92, (q15_t)0x7b26, (q15_t)0x7ab6, + (q15_t)0x7a42, (q15_t)0x79c8, (q15_t)0x794a, (q15_t)0x78c7, (q15_t)0x7840, (q15_t)0x77b4, (q15_t)0x7723, (q15_t)0x768e, + (q15_t)0x75f4, (q15_t)0x7555, (q15_t)0x74b2, (q15_t)0x740b, (q15_t)0x735f, (q15_t)0x72af, (q15_t)0x71fa, (q15_t)0x7141, + (q15_t)0x7083, (q15_t)0x6fc1, (q15_t)0x6efb, (q15_t)0x6e30, (q15_t)0x6d62, (q15_t)0x6c8f, (q15_t)0x6bb8, (q15_t)0x6adc, + (q15_t)0x69fd, (q15_t)0x6919, (q15_t)0x6832, (q15_t)0x6746, (q15_t)0x6657, (q15_t)0x6563, (q15_t)0x646c, (q15_t)0x6371, + (q15_t)0x6271, (q15_t)0x616f, (q15_t)0x6068, (q15_t)0x5f5e, (q15_t)0x5e50, (q15_t)0x5d3e, (q15_t)0x5c29, (q15_t)0x5b10, + (q15_t)0x59f3, (q15_t)0x58d4, (q15_t)0x57b0, (q15_t)0x568a, (q15_t)0x5560, (q15_t)0x5433, (q15_t)0x5302, (q15_t)0x51ce, + (q15_t)0x5097, (q15_t)0x4f5e, (q15_t)0x4e21, (q15_t)0x4ce1, (q15_t)0x4b9e, (q15_t)0x4a58, (q15_t)0x490f, (q15_t)0x47c3, + (q15_t)0x4675, (q15_t)0x4524, (q15_t)0x43d0, (q15_t)0x427a, (q15_t)0x4121, (q15_t)0x3fc5, (q15_t)0x3e68, (q15_t)0x3d07, + (q15_t)0x3ba5, (q15_t)0x3a40, (q15_t)0x38d8, (q15_t)0x376f, (q15_t)0x3604, (q15_t)0x3496, (q15_t)0x3326, (q15_t)0x31b5, + (q15_t)0x3041, (q15_t)0x2ecc, (q15_t)0x2d55, (q15_t)0x2bdc, (q15_t)0x2a61, (q15_t)0x28e5, (q15_t)0x2767, (q15_t)0x25e8, + (q15_t)0x2467, (q15_t)0x22e5, (q15_t)0x2161, (q15_t)0x1fdc, (q15_t)0x1e56, (q15_t)0x1ccf, (q15_t)0x1b47, (q15_t)0x19bd, + (q15_t)0x1833, (q15_t)0x16a8, (q15_t)0x151b, (q15_t)0x138e, (q15_t)0x1201, (q15_t)0x1072, (q15_t)0xee3, (q15_t)0xd53, + (q15_t)0xbc3, (q15_t)0xa33, (q15_t)0x8a2, (q15_t)0x710, (q15_t)0x57f, (q15_t)0x3ed, (q15_t)0x25b, (q15_t)0xc9 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + const q15_t __ALIGNED(4) WeightsQ15_512[1024] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7ffe, (q15_t)0xfed3, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff8, (q15_t)0xfd41, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fed, (q15_t)0xfbaf, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fdd, (q15_t)0xfa1d, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fc8, (q15_t)0xf88b, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fae, (q15_t)0xf6fa, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f8f, (q15_t)0xf569, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f6b, (q15_t)0xf3d9, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f43, (q15_t)0xf249, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f15, (q15_t)0xf0b9, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7ee3, (q15_t)0xef2a, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eab, (q15_t)0xed9c, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e6f, (q15_t)0xec0e, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e2e, (q15_t)0xea81, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7de8, (q15_t)0xe8f6, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7d9d, (q15_t)0xe76a, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d4e, (q15_t)0xe5e0, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7cf9, (q15_t)0xe457, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7ca0, (q15_t)0xe2cf, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c42, (q15_t)0xe148, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bdf, (q15_t)0xdfc2, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b77, (q15_t)0xde3e, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b0b, (q15_t)0xdcbb, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7a9a, (q15_t)0xdb39, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a24, (q15_t)0xd9b8, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79a9, (q15_t)0xd839, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x792a, (q15_t)0xd6bc, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78a6, (q15_t)0xd540, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x781d, (q15_t)0xd3c6, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x7790, (q15_t)0xd24d, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x76fe, (q15_t)0xd0d7, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7668, (q15_t)0xcf62, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75cc, (q15_t)0xcdef, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x752d, (q15_t)0xcc7e, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x7489, (q15_t)0xcb0e, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x73e0, (q15_t)0xc9a1, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7333, (q15_t)0xc836, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x7282, (q15_t)0xc6ce, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71cc, (q15_t)0xc567, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7112, (q15_t)0xc403, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7053, (q15_t)0xc2a0, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6f90, (q15_t)0xc141, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ec9, (q15_t)0xbfe3, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6dfd, (q15_t)0xbe89, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d2d, (q15_t)0xbd30, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c59, (q15_t)0xbbdb, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6b81, (q15_t)0xba88, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6aa5, (q15_t)0xb937, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69c4, (q15_t)0xb7ea, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x68e0, (q15_t)0xb69f, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x67f7, (q15_t)0xb557, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x670b, (q15_t)0xb411, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x661a, (q15_t)0xb2cf, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6526, (q15_t)0xb190, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x642d, (q15_t)0xb054, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6331, (q15_t)0xaf1b, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6231, (q15_t)0xade4, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x612d, (q15_t)0xacb2, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6026, (q15_t)0xab82, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f1a, (q15_t)0xaa55, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e0b, (q15_t)0xa92c, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5cf9, (q15_t)0xa807, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5be3, (q15_t)0xa6e4, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5ac9, (q15_t)0xa5c5, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ac, (q15_t)0xa4aa, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x588b, (q15_t)0xa392, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x5767, (q15_t)0xa27d, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5640, (q15_t)0xa16d, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x5515, (q15_t)0xa060, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x53e7, (q15_t)0x9f56, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52b5, (q15_t)0x9e50, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x5181, (q15_t)0x9d4e, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5049, (q15_t)0x9c50, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f0f, (q15_t)0x9b56, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4dd1, (q15_t)0x9a60, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4c90, (q15_t)0x996d, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b4c, (q15_t)0x987e, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a06, (q15_t)0x9794, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48bc, (q15_t)0x96ad, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x4770, (q15_t)0x95cb, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4621, (q15_t)0x94ed, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x44cf, (q15_t)0x9412, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x437b, (q15_t)0x933c, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4224, (q15_t)0x926a, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x40ca, (q15_t)0x919d, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3f6e, (q15_t)0x90d3, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e10, (q15_t)0x900e, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3caf, (q15_t)0x8f4d, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b4c, (q15_t)0x8e91, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x39e6, (q15_t)0x8dd9, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x387e, (q15_t)0x8d25, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3714, (q15_t)0x8c76, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35a8, (q15_t)0x8bcb, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x343a, (q15_t)0x8b25, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x32ca, (q15_t)0x8a83, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x3158, (q15_t)0x89e5, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x2fe4, (q15_t)0x894d, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2e6e, (q15_t)0x88b9, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2cf7, (q15_t)0x8829, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2b7d, (q15_t)0x879e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a02, (q15_t)0x8718, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x2886, (q15_t)0x8696, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2707, (q15_t)0x8619, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x2588, (q15_t)0x85a1, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2407, (q15_t)0x852d, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x2284, (q15_t)0x84be, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2100, (q15_t)0x8454, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1f7b, (q15_t)0x83ef, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1df5, (q15_t)0x838f, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1c6d, (q15_t)0x8333, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1ae4, (q15_t)0x82dc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x195b, (q15_t)0x828a, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x17d0, (q15_t)0x823d, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x1645, (q15_t)0x81f4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x14b8, (q15_t)0x81b1, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x132b, (q15_t)0x8172, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x119d, (q15_t)0x8138, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x100e, (q15_t)0x8103, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xe7f, (q15_t)0x80d3, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xcef, (q15_t)0x80a8, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xb5f, (q15_t)0x8082, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa33, (q15_t)0x8069, (q15_t)0x9ce, (q15_t)0x8061, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x83d, (q15_t)0x8044, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x775, (q15_t)0x8038, (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6ac, (q15_t)0x802d, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x51a, (q15_t)0x801b, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x451, (q15_t)0x8013, (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x388, (q15_t)0x800d, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x1f6, (q15_t)0x8004, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x12d, (q15_t)0x8002, (q15_t)0xc9, (q15_t)0x8001, (q15_t)0x64, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_512[512] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ff9, (q15_t)0x7ff7, + (q15_t)0x7ff4, (q15_t)0x7ff2, (q15_t)0x7fee, (q15_t)0x7feb, (q15_t)0x7fe7, (q15_t)0x7fe3, (q15_t)0x7fdf, (q15_t)0x7fda, + (q15_t)0x7fd6, (q15_t)0x7fd0, (q15_t)0x7fcb, (q15_t)0x7fc5, (q15_t)0x7fbf, (q15_t)0x7fb8, (q15_t)0x7fb1, (q15_t)0x7faa, + (q15_t)0x7fa3, (q15_t)0x7f9b, (q15_t)0x7f93, (q15_t)0x7f8b, (q15_t)0x7f82, (q15_t)0x7f79, (q15_t)0x7f70, (q15_t)0x7f67, + (q15_t)0x7f5d, (q15_t)0x7f53, (q15_t)0x7f48, (q15_t)0x7f3d, (q15_t)0x7f32, (q15_t)0x7f27, (q15_t)0x7f1b, (q15_t)0x7f0f, + (q15_t)0x7f03, (q15_t)0x7ef6, (q15_t)0x7ee9, (q15_t)0x7edc, (q15_t)0x7ecf, (q15_t)0x7ec1, (q15_t)0x7eb3, (q15_t)0x7ea4, + (q15_t)0x7e95, (q15_t)0x7e86, (q15_t)0x7e77, (q15_t)0x7e67, (q15_t)0x7e57, (q15_t)0x7e47, (q15_t)0x7e37, (q15_t)0x7e26, + (q15_t)0x7e14, (q15_t)0x7e03, (q15_t)0x7df1, (q15_t)0x7ddf, (q15_t)0x7dcd, (q15_t)0x7dba, (q15_t)0x7da7, (q15_t)0x7d94, + (q15_t)0x7d80, (q15_t)0x7d6c, (q15_t)0x7d58, (q15_t)0x7d43, (q15_t)0x7d2f, (q15_t)0x7d19, (q15_t)0x7d04, (q15_t)0x7cee, + (q15_t)0x7cd8, (q15_t)0x7cc2, (q15_t)0x7cab, (q15_t)0x7c94, (q15_t)0x7c7d, (q15_t)0x7c66, (q15_t)0x7c4e, (q15_t)0x7c36, + (q15_t)0x7c1d, (q15_t)0x7c05, (q15_t)0x7beb, (q15_t)0x7bd2, (q15_t)0x7bb9, (q15_t)0x7b9f, (q15_t)0x7b84, (q15_t)0x7b6a, + (q15_t)0x7b4f, (q15_t)0x7b34, (q15_t)0x7b19, (q15_t)0x7afd, (q15_t)0x7ae1, (q15_t)0x7ac5, (q15_t)0x7aa8, (q15_t)0x7a8b, + (q15_t)0x7a6e, (q15_t)0x7a50, (q15_t)0x7a33, (q15_t)0x7a15, (q15_t)0x79f6, (q15_t)0x79d8, (q15_t)0x79b9, (q15_t)0x7999, + (q15_t)0x797a, (q15_t)0x795a, (q15_t)0x793a, (q15_t)0x7919, (q15_t)0x78f9, (q15_t)0x78d8, (q15_t)0x78b6, (q15_t)0x7895, + (q15_t)0x7873, (q15_t)0x7851, (q15_t)0x782e, (q15_t)0x780c, (q15_t)0x77e9, (q15_t)0x77c5, (q15_t)0x77a2, (q15_t)0x777e, + (q15_t)0x775a, (q15_t)0x7735, (q15_t)0x7710, (q15_t)0x76eb, (q15_t)0x76c6, (q15_t)0x76a0, (q15_t)0x767b, (q15_t)0x7654, + (q15_t)0x762e, (q15_t)0x7607, (q15_t)0x75e0, (q15_t)0x75b9, (q15_t)0x7591, (q15_t)0x7569, (q15_t)0x7541, (q15_t)0x7519, + (q15_t)0x74f0, (q15_t)0x74c7, (q15_t)0x749e, (q15_t)0x7474, (q15_t)0x744a, (q15_t)0x7420, (q15_t)0x73f6, (q15_t)0x73cb, + (q15_t)0x73a0, (q15_t)0x7375, (q15_t)0x7349, (q15_t)0x731d, (q15_t)0x72f1, (q15_t)0x72c5, (q15_t)0x7298, (q15_t)0x726b, + (q15_t)0x723e, (q15_t)0x7211, (q15_t)0x71e3, (q15_t)0x71b5, (q15_t)0x7186, (q15_t)0x7158, (q15_t)0x7129, (q15_t)0x70fa, + (q15_t)0x70cb, (q15_t)0x709b, (q15_t)0x706b, (q15_t)0x703b, (q15_t)0x700a, (q15_t)0x6fda, (q15_t)0x6fa9, (q15_t)0x6f77, + (q15_t)0x6f46, (q15_t)0x6f14, (q15_t)0x6ee2, (q15_t)0x6eaf, (q15_t)0x6e7d, (q15_t)0x6e4a, (q15_t)0x6e17, (q15_t)0x6de3, + (q15_t)0x6db0, (q15_t)0x6d7c, (q15_t)0x6d48, (q15_t)0x6d13, (q15_t)0x6cde, (q15_t)0x6ca9, (q15_t)0x6c74, (q15_t)0x6c3f, + (q15_t)0x6c09, (q15_t)0x6bd3, (q15_t)0x6b9c, (q15_t)0x6b66, (q15_t)0x6b2f, (q15_t)0x6af8, (q15_t)0x6ac1, (q15_t)0x6a89, + (q15_t)0x6a51, (q15_t)0x6a19, (q15_t)0x69e1, (q15_t)0x69a8, (q15_t)0x696f, (q15_t)0x6936, (q15_t)0x68fd, (q15_t)0x68c3, + (q15_t)0x6889, (q15_t)0x684f, (q15_t)0x6815, (q15_t)0x67da, (q15_t)0x679f, (q15_t)0x6764, (q15_t)0x6729, (q15_t)0x66ed, + (q15_t)0x66b1, (q15_t)0x6675, (q15_t)0x6639, (q15_t)0x65fc, (q15_t)0x65bf, (q15_t)0x6582, (q15_t)0x6545, (q15_t)0x6507, + (q15_t)0x64c9, (q15_t)0x648b, (q15_t)0x644d, (q15_t)0x640e, (q15_t)0x63cf, (q15_t)0x6390, (q15_t)0x6351, (q15_t)0x6311, + (q15_t)0x62d2, (q15_t)0x6292, (q15_t)0x6251, (q15_t)0x6211, (q15_t)0x61d0, (q15_t)0x618f, (q15_t)0x614e, (q15_t)0x610d, + (q15_t)0x60cb, (q15_t)0x6089, (q15_t)0x6047, (q15_t)0x6004, (q15_t)0x5fc2, (q15_t)0x5f7f, (q15_t)0x5f3c, (q15_t)0x5ef9, + (q15_t)0x5eb5, (q15_t)0x5e71, (q15_t)0x5e2d, (q15_t)0x5de9, (q15_t)0x5da5, (q15_t)0x5d60, (q15_t)0x5d1b, (q15_t)0x5cd6, + (q15_t)0x5c91, (q15_t)0x5c4b, (q15_t)0x5c06, (q15_t)0x5bc0, (q15_t)0x5b79, (q15_t)0x5b33, (q15_t)0x5aec, (q15_t)0x5aa5, + (q15_t)0x5a5e, (q15_t)0x5a17, (q15_t)0x59d0, (q15_t)0x5988, (q15_t)0x5940, (q15_t)0x58f8, (q15_t)0x58af, (q15_t)0x5867, + (q15_t)0x581e, (q15_t)0x57d5, (q15_t)0x578c, (q15_t)0x5742, (q15_t)0x56f9, (q15_t)0x56af, (q15_t)0x5665, (q15_t)0x561a, + (q15_t)0x55d0, (q15_t)0x5585, (q15_t)0x553a, (q15_t)0x54ef, (q15_t)0x54a4, (q15_t)0x5458, (q15_t)0x540d, (q15_t)0x53c1, + (q15_t)0x5375, (q15_t)0x5328, (q15_t)0x52dc, (q15_t)0x528f, (q15_t)0x5242, (q15_t)0x51f5, (q15_t)0x51a8, (q15_t)0x515a, + (q15_t)0x510c, (q15_t)0x50bf, (q15_t)0x5070, (q15_t)0x5022, (q15_t)0x4fd4, (q15_t)0x4f85, (q15_t)0x4f36, (q15_t)0x4ee7, + (q15_t)0x4e98, (q15_t)0x4e48, (q15_t)0x4df9, (q15_t)0x4da9, (q15_t)0x4d59, (q15_t)0x4d09, (q15_t)0x4cb8, (q15_t)0x4c68, + (q15_t)0x4c17, (q15_t)0x4bc6, (q15_t)0x4b75, (q15_t)0x4b24, (q15_t)0x4ad2, (q15_t)0x4a81, (q15_t)0x4a2f, (q15_t)0x49dd, + (q15_t)0x498a, (q15_t)0x4938, (q15_t)0x48e6, (q15_t)0x4893, (q15_t)0x4840, (q15_t)0x47ed, (q15_t)0x479a, (q15_t)0x4746, + (q15_t)0x46f3, (q15_t)0x469f, (q15_t)0x464b, (q15_t)0x45f7, (q15_t)0x45a3, (q15_t)0x454e, (q15_t)0x44fa, (q15_t)0x44a5, + (q15_t)0x4450, (q15_t)0x43fb, (q15_t)0x43a5, (q15_t)0x4350, (q15_t)0x42fa, (q15_t)0x42a5, (q15_t)0x424f, (q15_t)0x41f9, + (q15_t)0x41a2, (q15_t)0x414c, (q15_t)0x40f6, (q15_t)0x409f, (q15_t)0x4048, (q15_t)0x3ff1, (q15_t)0x3f9a, (q15_t)0x3f43, + (q15_t)0x3eeb, (q15_t)0x3e93, (q15_t)0x3e3c, (q15_t)0x3de4, (q15_t)0x3d8c, (q15_t)0x3d33, (q15_t)0x3cdb, (q15_t)0x3c83, + (q15_t)0x3c2a, (q15_t)0x3bd1, (q15_t)0x3b78, (q15_t)0x3b1f, (q15_t)0x3ac6, (q15_t)0x3a6c, (q15_t)0x3a13, (q15_t)0x39b9, + (q15_t)0x395f, (q15_t)0x3906, (q15_t)0x38ab, (q15_t)0x3851, (q15_t)0x37f7, (q15_t)0x379c, (q15_t)0x3742, (q15_t)0x36e7, + (q15_t)0x368c, (q15_t)0x3631, (q15_t)0x35d6, (q15_t)0x357b, (q15_t)0x351f, (q15_t)0x34c4, (q15_t)0x3468, (q15_t)0x340c, + (q15_t)0x33b0, (q15_t)0x3354, (q15_t)0x32f8, (q15_t)0x329c, (q15_t)0x3240, (q15_t)0x31e3, (q15_t)0x3186, (q15_t)0x312a, + (q15_t)0x30cd, (q15_t)0x3070, (q15_t)0x3013, (q15_t)0x2fb5, (q15_t)0x2f58, (q15_t)0x2efb, (q15_t)0x2e9d, (q15_t)0x2e3f, + (q15_t)0x2de2, (q15_t)0x2d84, (q15_t)0x2d26, (q15_t)0x2cc8, (q15_t)0x2c69, (q15_t)0x2c0b, (q15_t)0x2bad, (q15_t)0x2b4e, + (q15_t)0x2aef, (q15_t)0x2a91, (q15_t)0x2a32, (q15_t)0x29d3, (q15_t)0x2974, (q15_t)0x2915, (q15_t)0x28b5, (q15_t)0x2856, + (q15_t)0x27f6, (q15_t)0x2797, (q15_t)0x2737, (q15_t)0x26d8, (q15_t)0x2678, (q15_t)0x2618, (q15_t)0x25b8, (q15_t)0x2558, + (q15_t)0x24f7, (q15_t)0x2497, (q15_t)0x2437, (q15_t)0x23d6, (q15_t)0x2376, (q15_t)0x2315, (q15_t)0x22b4, (q15_t)0x2254, + (q15_t)0x21f3, (q15_t)0x2192, (q15_t)0x2131, (q15_t)0x20d0, (q15_t)0x206e, (q15_t)0x200d, (q15_t)0x1fac, (q15_t)0x1f4a, + (q15_t)0x1ee9, (q15_t)0x1e87, (q15_t)0x1e25, (q15_t)0x1dc4, (q15_t)0x1d62, (q15_t)0x1d00, (q15_t)0x1c9e, (q15_t)0x1c3c, + (q15_t)0x1bda, (q15_t)0x1b78, (q15_t)0x1b16, (q15_t)0x1ab3, (q15_t)0x1a51, (q15_t)0x19ef, (q15_t)0x198c, (q15_t)0x192a, + (q15_t)0x18c7, (q15_t)0x1864, (q15_t)0x1802, (q15_t)0x179f, (q15_t)0x173c, (q15_t)0x16d9, (q15_t)0x1676, (q15_t)0x1613, + (q15_t)0x15b0, (q15_t)0x154d, (q15_t)0x14ea, (q15_t)0x1487, (q15_t)0x1423, (q15_t)0x13c0, (q15_t)0x135d, (q15_t)0x12f9, + (q15_t)0x1296, (q15_t)0x1232, (q15_t)0x11cf, (q15_t)0x116b, (q15_t)0x1108, (q15_t)0x10a4, (q15_t)0x1040, (q15_t)0xfdd, + (q15_t)0xf79, (q15_t)0xf15, (q15_t)0xeb1, (q15_t)0xe4d, (q15_t)0xde9, (q15_t)0xd85, (q15_t)0xd21, (q15_t)0xcbd, + (q15_t)0xc59, (q15_t)0xbf5, (q15_t)0xb91, (q15_t)0xb2d, (q15_t)0xac9, (q15_t)0xa65, (q15_t)0xa00, (q15_t)0x99c, + (q15_t)0x938, (q15_t)0x8d4, (q15_t)0x86f, (q15_t)0x80b, (q15_t)0x7a7, (q15_t)0x742, (q15_t)0x6de, (q15_t)0x67a, + (q15_t)0x615, (q15_t)0x5b1, (q15_t)0x54c, (q15_t)0x4e8, (q15_t)0x483, (q15_t)0x41f, (q15_t)0x3ba, (q15_t)0x356, + (q15_t)0x2f1, (q15_t)0x28d, (q15_t)0x228, (q15_t)0x1c4, (q15_t)0x15f, (q15_t)0xfb, (q15_t)0x96, (q15_t)0x32 +}; + + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + const q15_t __ALIGNED(4) WeightsQ15_2048[4096] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffb5, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff51, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeec, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffd, (q15_t)0xfe88, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe23, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffa, (q15_t)0xfdbe, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff8, (q15_t)0xfd5a, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff6, (q15_t)0xfcf5, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfc91, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc2c, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbc8, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7fea, (q15_t)0xfb64, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe6, (q15_t)0xfaff, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe2, (q15_t)0xfa9b, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fde, (q15_t)0xfa36, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fd9, (q15_t)0xf9d2, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd4, (q15_t)0xf96d, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fcf, (q15_t)0xf909, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fc9, (q15_t)0xf8a5, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc3, (q15_t)0xf840, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbd, (q15_t)0xf7dc, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb7, (q15_t)0xf778, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb0, (q15_t)0xf713, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7fa9, (q15_t)0xf6af, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa1, (q15_t)0xf64b, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f99, (q15_t)0xf5e7, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f91, (q15_t)0xf582, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f89, (q15_t)0xf51e, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f80, (q15_t)0xf4ba, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f77, (q15_t)0xf456, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f6e, (q15_t)0xf3f2, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f64, (q15_t)0xf38e, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5a, (q15_t)0xf32a, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f50, (q15_t)0xf2c6, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f45, (q15_t)0xf262, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3b, (q15_t)0xf1fe, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f2f, (q15_t)0xf19a, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f24, (q15_t)0xf136, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f18, (q15_t)0xf0d2, + (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0c, (q15_t)0xf06e, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f00, (q15_t)0xf00b, + (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef3, (q15_t)0xefa7, + (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee6, (q15_t)0xef43, + (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7ed9, (q15_t)0xeedf, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ecb, (q15_t)0xee7c, + (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ebd, (q15_t)0xee18, + (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eaf, (q15_t)0xedb5, + (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea1, (q15_t)0xed51, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e92, (q15_t)0xecee, + (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e83, (q15_t)0xec8a, + (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e73, (q15_t)0xec27, + (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e63, (q15_t)0xebc4, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e53, (q15_t)0xeb61, + (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e43, (q15_t)0xeafd, + (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e32, (q15_t)0xea9a, + (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e21, (q15_t)0xea37, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e10, (q15_t)0xe9d4, + (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7dff, (q15_t)0xe971, + (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7ded, (q15_t)0xe90e, + (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dda, (q15_t)0xe8ab, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dc8, (q15_t)0xe849, + (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db5, (q15_t)0xe7e6, + (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da2, (q15_t)0xe783, + (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d8f, (q15_t)0xe720, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7b, (q15_t)0xe6be, + (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d67, (q15_t)0xe65b, + (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d53, (q15_t)0xe5f9, + (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d3e, (q15_t)0xe596, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d29, (q15_t)0xe534, + (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d14, (q15_t)0xe4d2, + (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7cff, (q15_t)0xe470, + (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ce9, (q15_t)0xe40e, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd3, (q15_t)0xe3ab, + (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cbc, (q15_t)0xe349, + (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7ca6, (q15_t)0xe2e8, + (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c8f, (q15_t)0xe286, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c77, (q15_t)0xe224, + (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c60, (q15_t)0xe1c2, + (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c48, (q15_t)0xe160, + (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c30, (q15_t)0xe0ff, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c17, (q15_t)0xe09d, + (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7bfe, (q15_t)0xe03c, + (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7be5, (q15_t)0xdfdb, + (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bcc, (q15_t)0xdf79, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb2, (q15_t)0xdf18, + (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b98, (q15_t)0xdeb7, + (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b7e, (q15_t)0xde56, + (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b63, (q15_t)0xddf5, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b48, (q15_t)0xdd94, + (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b2d, (q15_t)0xdd33, + (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b12, (q15_t)0xdcd3, + (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7af6, (q15_t)0xdc72, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7ada, (q15_t)0xdc12, + (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7abd, (q15_t)0xdbb1, + (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa1, (q15_t)0xdb51, + (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a84, (q15_t)0xdaf1, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a67, (q15_t)0xda90, + (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a49, (q15_t)0xda30, + (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a2b, (q15_t)0xd9d0, + (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a0d, (q15_t)0xd970, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79ef, (q15_t)0xd911, + (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d0, (q15_t)0xd8b1, + (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b1, (q15_t)0xd851, + (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7992, (q15_t)0xd7f2, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7972, (q15_t)0xd792, + (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7952, (q15_t)0xd733, + (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7932, (q15_t)0xd6d4, + (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7911, (q15_t)0xd675, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f1, (q15_t)0xd615, + (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78cf, (q15_t)0xd5b7, + (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78ae, (q15_t)0xd558, + (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x788c, (q15_t)0xd4f9, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x786b, (q15_t)0xd49a, + (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x7848, (q15_t)0xd43c, + (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x7826, (q15_t)0xd3dd, + (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x7803, (q15_t)0xd37f, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e0, (q15_t)0xd321, + (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77bc, (q15_t)0xd2c3, + (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x7799, (q15_t)0xd265, + (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x7775, (q15_t)0xd207, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7751, (q15_t)0xd1a9, + (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x772c, (q15_t)0xd14b, + (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x7707, (q15_t)0xd0ee, + (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e2, (q15_t)0xd091, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76bd, (q15_t)0xd033, + (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x7697, (q15_t)0xcfd6, + (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7671, (q15_t)0xcf79, + (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x764b, (q15_t)0xcf1c, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x7624, (q15_t)0xcebf, + (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x75fd, (q15_t)0xce62, + (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75d6, (q15_t)0xce06, + (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75af, (q15_t)0xcda9, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x7587, (q15_t)0xcd4d, + (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x755f, (q15_t)0xccf1, + (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x7537, (q15_t)0xcc95, + (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x750f, (q15_t)0xcc39, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74e6, (q15_t)0xcbdd, + (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74bd, (q15_t)0xcb81, + (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x7493, (q15_t)0xcb25, + (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x746a, (q15_t)0xcaca, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7440, (q15_t)0xca6e, + (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x7415, (q15_t)0xca13, + (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73eb, (q15_t)0xc9b8, + (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c0, (q15_t)0xc95d, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x7395, (q15_t)0xc902, + (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x736a, (q15_t)0xc8a8, + (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x733e, (q15_t)0xc84d, + (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x7312, (q15_t)0xc7f3, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72e6, (q15_t)0xc798, + (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72ba, (q15_t)0xc73e, + (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x728d, (q15_t)0xc6e4, + (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7260, (q15_t)0xc68a, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x7233, (q15_t)0xc630, + (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x7205, (q15_t)0xc5d7, + (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71d7, (q15_t)0xc57d, + (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71a9, (q15_t)0xc524, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x717b, (q15_t)0xc4cb, + (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x714c, (q15_t)0xc472, + (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x711d, (q15_t)0xc419, + (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70ee, (q15_t)0xc3c0, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70bf, (q15_t)0xc367, + (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x708f, (q15_t)0xc30f, + (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x705f, (q15_t)0xc2b7, + (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x702f, (q15_t)0xc25e, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x6ffe, (q15_t)0xc206, + (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fcd, (q15_t)0xc1ae, + (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6f9c, (q15_t)0xc157, + (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f6b, (q15_t)0xc0ff, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f39, (q15_t)0xc0a8, + (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f07, (q15_t)0xc050, + (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6ed5, (q15_t)0xbff9, + (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6ea3, (q15_t)0xbfa2, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e70, (q15_t)0xbf4b, + (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e3d, (q15_t)0xbef5, + (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e0a, (q15_t)0xbe9e, + (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6dd6, (q15_t)0xbe48, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6da3, (q15_t)0xbdf2, + (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d6f, (q15_t)0xbd9c, + (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d3a, (q15_t)0xbd46, + (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d06, (q15_t)0xbcf0, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cd1, (q15_t)0xbc9b, + (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6c9c, (q15_t)0xbc45, + (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c67, (q15_t)0xbbf0, + (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c31, (q15_t)0xbb9b, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6bfb, (q15_t)0xbb46, + (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bc5, (q15_t)0xbaf1, + (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b8f, (q15_t)0xba9d, + (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b58, (q15_t)0xba48, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b21, (q15_t)0xb9f4, + (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6aea, (q15_t)0xb9a0, + (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6ab3, (q15_t)0xb94c, + (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a7b, (q15_t)0xb8f8, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a43, (q15_t)0xb8a5, + (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a0b, (q15_t)0xb852, + (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69d3, (q15_t)0xb7fe, + (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x699a, (q15_t)0xb7ab, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x6961, (q15_t)0xb758, + (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6928, (q15_t)0xb706, + (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68ee, (q15_t)0xb6b3, + (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68b5, (q15_t)0xb661, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x687b, (q15_t)0xb60f, + (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x6840, (q15_t)0xb5bd, + (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6806, (q15_t)0xb56b, + (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67cb, (q15_t)0xb519, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x6790, (q15_t)0xb4c8, + (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6755, (q15_t)0xb477, + (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x671a, (q15_t)0xb426, + (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66de, (q15_t)0xb3d5, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66a2, (q15_t)0xb384, + (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6666, (q15_t)0xb334, + (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6629, (q15_t)0xb2e3, + (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65ed, (q15_t)0xb293, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65b0, (q15_t)0xb243, + (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x6573, (q15_t)0xb1f3, + (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6535, (q15_t)0xb1a4, + (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x64f7, (q15_t)0xb154, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64ba, (q15_t)0xb105, + (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x647b, (q15_t)0xb0b6, + (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x643d, (q15_t)0xb067, + (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x63fe, (q15_t)0xb019, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63c0, (q15_t)0xafca, + (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x6380, (q15_t)0xaf7c, + (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x6341, (q15_t)0xaf2e, + (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x6301, (q15_t)0xaee0, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62c2, (q15_t)0xae92, + (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x6282, (q15_t)0xae45, + (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x6241, (q15_t)0xadf8, + (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x6201, (q15_t)0xadab, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61c0, (q15_t)0xad5e, + (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x617f, (q15_t)0xad11, + (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x613e, (q15_t)0xacc5, + (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x60fc, (q15_t)0xac78, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60ba, (q15_t)0xac2c, + (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6078, (q15_t)0xabe0, + (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6036, (q15_t)0xab95, + (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x5ff4, (q15_t)0xab49, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fb1, (q15_t)0xaafe, + (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f6e, (q15_t)0xaab3, + (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f2b, (q15_t)0xaa68, + (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ee8, (q15_t)0xaa1d, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5ea4, (q15_t)0xa9d3, + (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e60, (q15_t)0xa989, + (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e1c, (q15_t)0xa93f, + (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5dd8, (q15_t)0xa8f5, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5d94, (q15_t)0xa8ab, + (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d4f, (q15_t)0xa862, + (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d0a, (q15_t)0xa819, + (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cc5, (q15_t)0xa7d0, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c80, (q15_t)0xa787, + (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c3a, (q15_t)0xa73f, + (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5bf4, (q15_t)0xa6f6, + (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bae, (q15_t)0xa6ae, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b68, (q15_t)0xa666, + (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b21, (q15_t)0xa61f, + (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5adb, (q15_t)0xa5d7, + (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5a94, (q15_t)0xa590, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a4d, (q15_t)0xa549, + (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a05, (q15_t)0xa502, + (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59be, (q15_t)0xa4bb, + (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5976, (q15_t)0xa475, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x592e, (q15_t)0xa42f, + (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58e6, (q15_t)0xa3e9, + (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x589d, (q15_t)0xa3a3, + (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5855, (q15_t)0xa35e, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x580c, (q15_t)0xa318, + (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57c3, (q15_t)0xa2d3, + (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5779, (q15_t)0xa28f, + (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x5730, (q15_t)0xa24a, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56e6, (q15_t)0xa206, + (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x569c, (q15_t)0xa1c1, + (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5652, (q15_t)0xa17e, + (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5608, (q15_t)0xa13a, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55bd, (q15_t)0xa0f6, + (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5572, (q15_t)0xa0b3, + (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5528, (q15_t)0xa070, + (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54dc, (q15_t)0xa02d, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x5491, (q15_t)0x9feb, + (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5445, (q15_t)0x9fa9, + (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x53fa, (q15_t)0x9f67, + (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53ae, (q15_t)0x9f25, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5362, (q15_t)0x9ee3, + (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5315, (q15_t)0x9ea2, + (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52c9, (q15_t)0x9e61, + (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x527c, (q15_t)0x9e20, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x522f, (q15_t)0x9ddf, + (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51e2, (q15_t)0x9d9f, + (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x5194, (q15_t)0x9d5e, + (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5147, (q15_t)0x9d1e, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x50f9, (q15_t)0x9cdf, + (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ab, (q15_t)0x9c9f, + (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x505d, (q15_t)0x9c60, + (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x500f, (q15_t)0x9c21, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fc0, (q15_t)0x9be2, + (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f71, (q15_t)0x9ba4, + (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f22, (q15_t)0x9b65, + (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ed3, (q15_t)0x9b27, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e84, (q15_t)0x9aea, + (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e34, (q15_t)0x9aac, + (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4de5, (q15_t)0x9a6f, + (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4d95, (q15_t)0x9a32, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d45, (q15_t)0x99f5, + (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4cf5, (q15_t)0x99b8, + (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4ca4, (q15_t)0x997c, + (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c54, (q15_t)0x9940, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c03, (q15_t)0x9904, + (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bb2, (q15_t)0x98c9, + (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b61, (q15_t)0x988d, + (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b0f, (q15_t)0x9852, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4abe, (q15_t)0x9817, + (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a6c, (q15_t)0x97dd, + (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a1a, (q15_t)0x97a2, + (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49c8, (q15_t)0x9768, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4976, (q15_t)0x972f, + (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4923, (q15_t)0x96f5, + (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48d1, (q15_t)0x96bc, + (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x487e, (q15_t)0x9683, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x482b, (q15_t)0x964a, + (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47d8, (q15_t)0x9611, + (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4785, (q15_t)0x95d9, + (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4731, (q15_t)0x95a1, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46de, (q15_t)0x9569, + (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x468a, (q15_t)0x9532, + (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4636, (q15_t)0x94fa, + (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45e2, (q15_t)0x94c3, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x458d, (q15_t)0x948d, + (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4539, (q15_t)0x9456, + (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44e4, (q15_t)0x9420, + (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x4490, (q15_t)0x93ea, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x443b, (q15_t)0x93b4, + (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43e5, (q15_t)0x937f, + (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x4390, (q15_t)0x9349, + (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x433b, (q15_t)0x9314, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42e5, (q15_t)0x92e0, + (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x428f, (q15_t)0x92ab, + (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4239, (q15_t)0x9277, + (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41e3, (q15_t)0x9243, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x418d, (q15_t)0x9210, + (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4136, (q15_t)0x91dc, + (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40e0, (q15_t)0x91a9, + (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4089, (q15_t)0x9177, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4032, (q15_t)0x9144, + (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fdb, (q15_t)0x9112, + (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f84, (q15_t)0x90e0, + (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f2d, (q15_t)0x90ae, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ed5, (q15_t)0x907c, + (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e7d, (q15_t)0x904b, + (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e26, (q15_t)0x901a, + (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dce, (q15_t)0x8fea, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d76, (q15_t)0x8fb9, + (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d1d, (q15_t)0x8f89, + (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cc5, (q15_t)0x8f59, + (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c6c, (q15_t)0x8f2a, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c14, (q15_t)0x8efa, + (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bbb, (q15_t)0x8ecb, + (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b62, (q15_t)0x8e9c, + (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b09, (q15_t)0x8e6e, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3aaf, (q15_t)0x8e40, + (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a56, (q15_t)0x8e12, + (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x39fd, (q15_t)0x8de4, + (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39a3, (q15_t)0x8db7, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x3949, (q15_t)0x8d8a, + (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x38ef, (q15_t)0x8d5d, + (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x3895, (q15_t)0x8d30, + (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x383b, (q15_t)0x8d04, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37e0, (q15_t)0x8cd8, + (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3786, (q15_t)0x8cac, + (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x372b, (q15_t)0x8c81, + (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36d0, (q15_t)0x8c55, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3675, (q15_t)0x8c2a, + (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x361a, (q15_t)0x8c00, + (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35bf, (q15_t)0x8bd5, + (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3564, (q15_t)0x8bab, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x3508, (q15_t)0x8b82, + (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34ad, (q15_t)0x8b58, + (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3451, (q15_t)0x8b2f, + (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x33f5, (q15_t)0x8b06, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x3399, (q15_t)0x8add, + (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x333d, (q15_t)0x8ab5, + (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32e1, (q15_t)0x8a8d, + (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3285, (q15_t)0x8a65, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x3228, (q15_t)0x8a3d, + (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31cc, (q15_t)0x8a16, + (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x316f, (q15_t)0x89ef, + (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3112, (q15_t)0x89c8, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30b6, (q15_t)0x89a2, + (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x3059, (q15_t)0x897c, + (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x2ffb, (q15_t)0x8956, + (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2f9e, (q15_t)0x8931, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f41, (q15_t)0x890b, + (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ee3, (q15_t)0x88e6, + (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e86, (q15_t)0x88c2, + (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e28, (q15_t)0x889d, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2dca, (q15_t)0x8879, + (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d6c, (q15_t)0x8855, + (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d0e, (q15_t)0x8832, + (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cb0, (q15_t)0x880f, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c52, (q15_t)0x87ec, + (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2bf3, (q15_t)0x87c9, + (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2b95, (q15_t)0x87a7, + (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b36, (q15_t)0x8784, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ad8, (q15_t)0x8763, + (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a79, (q15_t)0x8741, + (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a1a, (q15_t)0x8720, + (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29bb, (q15_t)0x86ff, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x295c, (q15_t)0x86de, + (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x28fd, (q15_t)0x86be, + (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x289d, (q15_t)0x869e, + (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x283e, (q15_t)0x867e, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27df, (q15_t)0x865f, + (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x277f, (q15_t)0x8640, + (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x271f, (q15_t)0x8621, + (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26c0, (q15_t)0x8602, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2660, (q15_t)0x85e4, + (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2600, (q15_t)0x85c6, + (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25a0, (q15_t)0x85a8, + (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2540, (q15_t)0x858b, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24df, (q15_t)0x856e, + (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x247f, (q15_t)0x8551, + (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x241f, (q15_t)0x8534, + (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23be, (q15_t)0x8518, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x235e, (q15_t)0x84fc, + (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x22fd, (q15_t)0x84e1, + (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x229c, (q15_t)0x84c5, + (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x223b, (q15_t)0x84aa, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21da, (q15_t)0x848f, + (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x2179, (q15_t)0x8475, + (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x2118, (q15_t)0x845b, + (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20b7, (q15_t)0x8441, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2056, (q15_t)0x8427, + (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x1ff5, (q15_t)0x840e, + (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1f93, (q15_t)0x83f5, + (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f32, (q15_t)0x83dd, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ed0, (q15_t)0x83c4, + (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e6f, (q15_t)0x83ac, + (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e0d, (q15_t)0x8394, + (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dab, (q15_t)0x837d, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d49, (q15_t)0x8366, + (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1ce8, (q15_t)0x834f, + (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c86, (q15_t)0x8338, + (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c24, (q15_t)0x8322, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bc1, (q15_t)0x830c, + (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b5f, (q15_t)0x82f7, + (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1afd, (q15_t)0x82e1, + (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1a9b, (q15_t)0x82cc, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a38, (q15_t)0x82b7, + (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19d6, (q15_t)0x82a3, + (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1973, (q15_t)0x828f, + (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1911, (q15_t)0x827b, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18ae, (q15_t)0x8268, + (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x184c, (q15_t)0x8254, + (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17e9, (q15_t)0x8241, + (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1786, (q15_t)0x822f, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1723, (q15_t)0x821c, + (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16c0, (q15_t)0x820a, + (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x165d, (q15_t)0x81f9, + (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x15fa, (q15_t)0x81e7, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x1597, (q15_t)0x81d6, + (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1534, (q15_t)0x81c5, + (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14d1, (q15_t)0x81b5, + (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x146e, (q15_t)0x81a5, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x140b, (q15_t)0x8195, + (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13a7, (q15_t)0x8185, + (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1344, (q15_t)0x8176, + (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12e0, (q15_t)0x8167, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x127d, (q15_t)0x8158, + (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x1219, (q15_t)0x814a, + (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11b6, (q15_t)0x813c, + (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1152, (q15_t)0x812e, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x10ef, (q15_t)0x8121, + (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x108b, (q15_t)0x8113, + (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x1027, (q15_t)0x8107, + (q15_t)0x100e, (q15_t)0x8103, (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfc4, (q15_t)0x80fa, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf60, (q15_t)0x80ee, + (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xefc, (q15_t)0x80e2, + (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xe98, (q15_t)0x80d6, + (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe34, (q15_t)0x80cb, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xdd0, (q15_t)0x80c0, + (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd6c, (q15_t)0x80b5, + (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd08, (q15_t)0x80ab, + (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xca4, (q15_t)0x80a1, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc40, (q15_t)0x8097, + (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbdc, (q15_t)0x808e, + (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb78, (q15_t)0x8084, + (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb14, (q15_t)0x807b, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xab0, (q15_t)0x8073, + (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa4c, (q15_t)0x806b, + (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9e7, (q15_t)0x8063, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x983, (q15_t)0x805b, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x951, (q15_t)0x8057, (q15_t)0x938, (q15_t)0x8056, (q15_t)0x91f, (q15_t)0x8054, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8bb, (q15_t)0x804d, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x888, (q15_t)0x8049, (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x856, (q15_t)0x8046, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x824, (q15_t)0x8043, (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x7f2, (q15_t)0x8040, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x78e, (q15_t)0x803a, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x742, (q15_t)0x8035, (q15_t)0x729, (q15_t)0x8034, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6c5, (q15_t)0x802e, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x693, (q15_t)0x802c, (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x660, (q15_t)0x8029, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x615, (q15_t)0x8026, (q15_t)0x5fc, (q15_t)0x8024, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x598, (q15_t)0x8020, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x565, (q15_t)0x801e, (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x533, (q15_t)0x801c, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4cf, (q15_t)0x8018, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x483, (q15_t)0x8015, (q15_t)0x46a, (q15_t)0x8014, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x438, (q15_t)0x8012, (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x406, (q15_t)0x8011, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3a1, (q15_t)0x800e, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x356, (q15_t)0x800c, (q15_t)0x33d, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2d8, (q15_t)0x8009, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x274, (q15_t)0x8007, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x242, (q15_t)0x8006, (q15_t)0x228, (q15_t)0x8005, (q15_t)0x20f, (q15_t)0x8005, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1ab, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x178, (q15_t)0x8003, (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x146, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x114, (q15_t)0x8002, (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xe2, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xaf, (q15_t)0x8001, (q15_t)0x96, (q15_t)0x8001, (q15_t)0x7d, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x32, (q15_t)0x8001, (q15_t)0x19, (q15_t)0x8001 +}; + const q15_t __ALIGNED(4) cos_factorsQ15_2048[2048] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, + (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff1, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7fea, + (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe3, (q15_t)0x7fe2, + (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fda, (q15_t)0x7fd9, + (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd0, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc4, (q15_t)0x7fc3, + (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fbe, (q15_t)0x7fbc, (q15_t)0x7fbb, (q15_t)0x7fb9, (q15_t)0x7fb7, (q15_t)0x7fb6, + (q15_t)0x7fb4, (q15_t)0x7fb2, (q15_t)0x7fb1, (q15_t)0x7faf, (q15_t)0x7fad, (q15_t)0x7fab, (q15_t)0x7fa9, (q15_t)0x7fa8, + (q15_t)0x7fa6, (q15_t)0x7fa4, (q15_t)0x7fa2, (q15_t)0x7fa0, (q15_t)0x7f9e, (q15_t)0x7f9c, (q15_t)0x7f9a, (q15_t)0x7f98, + (q15_t)0x7f96, (q15_t)0x7f94, (q15_t)0x7f92, (q15_t)0x7f90, (q15_t)0x7f8e, (q15_t)0x7f8c, (q15_t)0x7f8a, (q15_t)0x7f88, + (q15_t)0x7f86, (q15_t)0x7f83, (q15_t)0x7f81, (q15_t)0x7f7f, (q15_t)0x7f7d, (q15_t)0x7f7b, (q15_t)0x7f78, (q15_t)0x7f76, + (q15_t)0x7f74, (q15_t)0x7f71, (q15_t)0x7f6f, (q15_t)0x7f6d, (q15_t)0x7f6a, (q15_t)0x7f68, (q15_t)0x7f65, (q15_t)0x7f63, + (q15_t)0x7f60, (q15_t)0x7f5e, (q15_t)0x7f5b, (q15_t)0x7f59, (q15_t)0x7f56, (q15_t)0x7f54, (q15_t)0x7f51, (q15_t)0x7f4f, + (q15_t)0x7f4c, (q15_t)0x7f49, (q15_t)0x7f47, (q15_t)0x7f44, (q15_t)0x7f41, (q15_t)0x7f3f, (q15_t)0x7f3c, (q15_t)0x7f39, + (q15_t)0x7f36, (q15_t)0x7f34, (q15_t)0x7f31, (q15_t)0x7f2e, (q15_t)0x7f2b, (q15_t)0x7f28, (q15_t)0x7f25, (q15_t)0x7f23, + (q15_t)0x7f20, (q15_t)0x7f1d, (q15_t)0x7f1a, (q15_t)0x7f17, (q15_t)0x7f14, (q15_t)0x7f11, (q15_t)0x7f0e, (q15_t)0x7f0b, + (q15_t)0x7f08, (q15_t)0x7f04, (q15_t)0x7f01, (q15_t)0x7efe, (q15_t)0x7efb, (q15_t)0x7ef8, (q15_t)0x7ef5, (q15_t)0x7ef1, + (q15_t)0x7eee, (q15_t)0x7eeb, (q15_t)0x7ee8, (q15_t)0x7ee4, (q15_t)0x7ee1, (q15_t)0x7ede, (q15_t)0x7eda, (q15_t)0x7ed7, + (q15_t)0x7ed4, (q15_t)0x7ed0, (q15_t)0x7ecd, (q15_t)0x7ec9, (q15_t)0x7ec6, (q15_t)0x7ec3, (q15_t)0x7ebf, (q15_t)0x7ebb, + (q15_t)0x7eb8, (q15_t)0x7eb4, (q15_t)0x7eb1, (q15_t)0x7ead, (q15_t)0x7eaa, (q15_t)0x7ea6, (q15_t)0x7ea2, (q15_t)0x7e9f, + (q15_t)0x7e9b, (q15_t)0x7e97, (q15_t)0x7e94, (q15_t)0x7e90, (q15_t)0x7e8c, (q15_t)0x7e88, (q15_t)0x7e84, (q15_t)0x7e81, + (q15_t)0x7e7d, (q15_t)0x7e79, (q15_t)0x7e75, (q15_t)0x7e71, (q15_t)0x7e6d, (q15_t)0x7e69, (q15_t)0x7e65, (q15_t)0x7e61, + (q15_t)0x7e5d, (q15_t)0x7e59, (q15_t)0x7e55, (q15_t)0x7e51, (q15_t)0x7e4d, (q15_t)0x7e49, (q15_t)0x7e45, (q15_t)0x7e41, + (q15_t)0x7e3d, (q15_t)0x7e39, (q15_t)0x7e34, (q15_t)0x7e30, (q15_t)0x7e2c, (q15_t)0x7e28, (q15_t)0x7e24, (q15_t)0x7e1f, + (q15_t)0x7e1b, (q15_t)0x7e17, (q15_t)0x7e12, (q15_t)0x7e0e, (q15_t)0x7e0a, (q15_t)0x7e05, (q15_t)0x7e01, (q15_t)0x7dfc, + (q15_t)0x7df8, (q15_t)0x7df3, (q15_t)0x7def, (q15_t)0x7dea, (q15_t)0x7de6, (q15_t)0x7de1, (q15_t)0x7ddd, (q15_t)0x7dd8, + (q15_t)0x7dd4, (q15_t)0x7dcf, (q15_t)0x7dca, (q15_t)0x7dc6, (q15_t)0x7dc1, (q15_t)0x7dbc, (q15_t)0x7db8, (q15_t)0x7db3, + (q15_t)0x7dae, (q15_t)0x7da9, (q15_t)0x7da5, (q15_t)0x7da0, (q15_t)0x7d9b, (q15_t)0x7d96, (q15_t)0x7d91, (q15_t)0x7d8c, + (q15_t)0x7d87, (q15_t)0x7d82, (q15_t)0x7d7e, (q15_t)0x7d79, (q15_t)0x7d74, (q15_t)0x7d6f, (q15_t)0x7d6a, (q15_t)0x7d65, + (q15_t)0x7d60, (q15_t)0x7d5a, (q15_t)0x7d55, (q15_t)0x7d50, (q15_t)0x7d4b, (q15_t)0x7d46, (q15_t)0x7d41, (q15_t)0x7d3c, + (q15_t)0x7d36, (q15_t)0x7d31, (q15_t)0x7d2c, (q15_t)0x7d27, (q15_t)0x7d21, (q15_t)0x7d1c, (q15_t)0x7d17, (q15_t)0x7d11, + (q15_t)0x7d0c, (q15_t)0x7d07, (q15_t)0x7d01, (q15_t)0x7cfc, (q15_t)0x7cf6, (q15_t)0x7cf1, (q15_t)0x7cec, (q15_t)0x7ce6, + (q15_t)0x7ce1, (q15_t)0x7cdb, (q15_t)0x7cd5, (q15_t)0x7cd0, (q15_t)0x7cca, (q15_t)0x7cc5, (q15_t)0x7cbf, (q15_t)0x7cb9, + (q15_t)0x7cb4, (q15_t)0x7cae, (q15_t)0x7ca8, (q15_t)0x7ca3, (q15_t)0x7c9d, (q15_t)0x7c97, (q15_t)0x7c91, (q15_t)0x7c8c, + (q15_t)0x7c86, (q15_t)0x7c80, (q15_t)0x7c7a, (q15_t)0x7c74, (q15_t)0x7c6e, (q15_t)0x7c69, (q15_t)0x7c63, (q15_t)0x7c5d, + (q15_t)0x7c57, (q15_t)0x7c51, (q15_t)0x7c4b, (q15_t)0x7c45, (q15_t)0x7c3f, (q15_t)0x7c39, (q15_t)0x7c33, (q15_t)0x7c2d, + (q15_t)0x7c26, (q15_t)0x7c20, (q15_t)0x7c1a, (q15_t)0x7c14, (q15_t)0x7c0e, (q15_t)0x7c08, (q15_t)0x7c01, (q15_t)0x7bfb, + (q15_t)0x7bf5, (q15_t)0x7bef, (q15_t)0x7be8, (q15_t)0x7be2, (q15_t)0x7bdc, (q15_t)0x7bd5, (q15_t)0x7bcf, (q15_t)0x7bc9, + (q15_t)0x7bc2, (q15_t)0x7bbc, (q15_t)0x7bb5, (q15_t)0x7baf, (q15_t)0x7ba8, (q15_t)0x7ba2, (q15_t)0x7b9b, (q15_t)0x7b95, + (q15_t)0x7b8e, (q15_t)0x7b88, (q15_t)0x7b81, (q15_t)0x7b7a, (q15_t)0x7b74, (q15_t)0x7b6d, (q15_t)0x7b67, (q15_t)0x7b60, + (q15_t)0x7b59, (q15_t)0x7b52, (q15_t)0x7b4c, (q15_t)0x7b45, (q15_t)0x7b3e, (q15_t)0x7b37, (q15_t)0x7b31, (q15_t)0x7b2a, + (q15_t)0x7b23, (q15_t)0x7b1c, (q15_t)0x7b15, (q15_t)0x7b0e, (q15_t)0x7b07, (q15_t)0x7b00, (q15_t)0x7af9, (q15_t)0x7af2, + (q15_t)0x7aeb, (q15_t)0x7ae4, (q15_t)0x7add, (q15_t)0x7ad6, (q15_t)0x7acf, (q15_t)0x7ac8, (q15_t)0x7ac1, (q15_t)0x7aba, + (q15_t)0x7ab3, (q15_t)0x7aac, (q15_t)0x7aa4, (q15_t)0x7a9d, (q15_t)0x7a96, (q15_t)0x7a8f, (q15_t)0x7a87, (q15_t)0x7a80, + (q15_t)0x7a79, (q15_t)0x7a72, (q15_t)0x7a6a, (q15_t)0x7a63, (q15_t)0x7a5c, (q15_t)0x7a54, (q15_t)0x7a4d, (q15_t)0x7a45, + (q15_t)0x7a3e, (q15_t)0x7a36, (q15_t)0x7a2f, (q15_t)0x7a27, (q15_t)0x7a20, (q15_t)0x7a18, (q15_t)0x7a11, (q15_t)0x7a09, + (q15_t)0x7a02, (q15_t)0x79fa, (q15_t)0x79f2, (q15_t)0x79eb, (q15_t)0x79e3, (q15_t)0x79db, (q15_t)0x79d4, (q15_t)0x79cc, + (q15_t)0x79c4, (q15_t)0x79bc, (q15_t)0x79b5, (q15_t)0x79ad, (q15_t)0x79a5, (q15_t)0x799d, (q15_t)0x7995, (q15_t)0x798e, + (q15_t)0x7986, (q15_t)0x797e, (q15_t)0x7976, (q15_t)0x796e, (q15_t)0x7966, (q15_t)0x795e, (q15_t)0x7956, (q15_t)0x794e, + (q15_t)0x7946, (q15_t)0x793e, (q15_t)0x7936, (q15_t)0x792e, (q15_t)0x7926, (q15_t)0x791e, (q15_t)0x7915, (q15_t)0x790d, + (q15_t)0x7905, (q15_t)0x78fd, (q15_t)0x78f5, (q15_t)0x78ec, (q15_t)0x78e4, (q15_t)0x78dc, (q15_t)0x78d4, (q15_t)0x78cb, + (q15_t)0x78c3, (q15_t)0x78bb, (q15_t)0x78b2, (q15_t)0x78aa, (q15_t)0x78a2, (q15_t)0x7899, (q15_t)0x7891, (q15_t)0x7888, + (q15_t)0x7880, (q15_t)0x7877, (q15_t)0x786f, (q15_t)0x7866, (q15_t)0x785e, (q15_t)0x7855, (q15_t)0x784d, (q15_t)0x7844, + (q15_t)0x783b, (q15_t)0x7833, (q15_t)0x782a, (q15_t)0x7821, (q15_t)0x7819, (q15_t)0x7810, (q15_t)0x7807, (q15_t)0x77ff, + (q15_t)0x77f6, (q15_t)0x77ed, (q15_t)0x77e4, (q15_t)0x77db, (q15_t)0x77d3, (q15_t)0x77ca, (q15_t)0x77c1, (q15_t)0x77b8, + (q15_t)0x77af, (q15_t)0x77a6, (q15_t)0x779d, (q15_t)0x7794, (q15_t)0x778b, (q15_t)0x7782, (q15_t)0x7779, (q15_t)0x7770, + (q15_t)0x7767, (q15_t)0x775e, (q15_t)0x7755, (q15_t)0x774c, (q15_t)0x7743, (q15_t)0x773a, (q15_t)0x7731, (q15_t)0x7727, + (q15_t)0x771e, (q15_t)0x7715, (q15_t)0x770c, (q15_t)0x7703, (q15_t)0x76f9, (q15_t)0x76f0, (q15_t)0x76e7, (q15_t)0x76dd, + (q15_t)0x76d4, (q15_t)0x76cb, (q15_t)0x76c1, (q15_t)0x76b8, (q15_t)0x76af, (q15_t)0x76a5, (q15_t)0x769c, (q15_t)0x7692, + (q15_t)0x7689, (q15_t)0x767f, (q15_t)0x7676, (q15_t)0x766c, (q15_t)0x7663, (q15_t)0x7659, (q15_t)0x7650, (q15_t)0x7646, + (q15_t)0x763c, (q15_t)0x7633, (q15_t)0x7629, (q15_t)0x761f, (q15_t)0x7616, (q15_t)0x760c, (q15_t)0x7602, (q15_t)0x75f9, + (q15_t)0x75ef, (q15_t)0x75e5, (q15_t)0x75db, (q15_t)0x75d1, (q15_t)0x75c8, (q15_t)0x75be, (q15_t)0x75b4, (q15_t)0x75aa, + (q15_t)0x75a0, (q15_t)0x7596, (q15_t)0x758c, (q15_t)0x7582, (q15_t)0x7578, (q15_t)0x756e, (q15_t)0x7564, (q15_t)0x755a, + (q15_t)0x7550, (q15_t)0x7546, (q15_t)0x753c, (q15_t)0x7532, (q15_t)0x7528, (q15_t)0x751e, (q15_t)0x7514, (q15_t)0x7509, + (q15_t)0x74ff, (q15_t)0x74f5, (q15_t)0x74eb, (q15_t)0x74e1, (q15_t)0x74d6, (q15_t)0x74cc, (q15_t)0x74c2, (q15_t)0x74b7, + (q15_t)0x74ad, (q15_t)0x74a3, (q15_t)0x7498, (q15_t)0x748e, (q15_t)0x7484, (q15_t)0x7479, (q15_t)0x746f, (q15_t)0x7464, + (q15_t)0x745a, (q15_t)0x744f, (q15_t)0x7445, (q15_t)0x743a, (q15_t)0x7430, (q15_t)0x7425, (q15_t)0x741b, (q15_t)0x7410, + (q15_t)0x7406, (q15_t)0x73fb, (q15_t)0x73f0, (q15_t)0x73e6, (q15_t)0x73db, (q15_t)0x73d0, (q15_t)0x73c6, (q15_t)0x73bb, + (q15_t)0x73b0, (q15_t)0x73a5, (q15_t)0x739b, (q15_t)0x7390, (q15_t)0x7385, (q15_t)0x737a, (q15_t)0x736f, (q15_t)0x7364, + (q15_t)0x7359, (q15_t)0x734f, (q15_t)0x7344, (q15_t)0x7339, (q15_t)0x732e, (q15_t)0x7323, (q15_t)0x7318, (q15_t)0x730d, + (q15_t)0x7302, (q15_t)0x72f7, (q15_t)0x72ec, (q15_t)0x72e1, (q15_t)0x72d5, (q15_t)0x72ca, (q15_t)0x72bf, (q15_t)0x72b4, + (q15_t)0x72a9, (q15_t)0x729e, (q15_t)0x7293, (q15_t)0x7287, (q15_t)0x727c, (q15_t)0x7271, (q15_t)0x7266, (q15_t)0x725a, + (q15_t)0x724f, (q15_t)0x7244, (q15_t)0x7238, (q15_t)0x722d, (q15_t)0x7222, (q15_t)0x7216, (q15_t)0x720b, (q15_t)0x71ff, + (q15_t)0x71f4, (q15_t)0x71e9, (q15_t)0x71dd, (q15_t)0x71d2, (q15_t)0x71c6, (q15_t)0x71bb, (q15_t)0x71af, (q15_t)0x71a3, + (q15_t)0x7198, (q15_t)0x718c, (q15_t)0x7181, (q15_t)0x7175, (q15_t)0x7169, (q15_t)0x715e, (q15_t)0x7152, (q15_t)0x7146, + (q15_t)0x713b, (q15_t)0x712f, (q15_t)0x7123, (q15_t)0x7117, (q15_t)0x710c, (q15_t)0x7100, (q15_t)0x70f4, (q15_t)0x70e8, + (q15_t)0x70dc, (q15_t)0x70d1, (q15_t)0x70c5, (q15_t)0x70b9, (q15_t)0x70ad, (q15_t)0x70a1, (q15_t)0x7095, (q15_t)0x7089, + (q15_t)0x707d, (q15_t)0x7071, (q15_t)0x7065, (q15_t)0x7059, (q15_t)0x704d, (q15_t)0x7041, (q15_t)0x7035, (q15_t)0x7029, + (q15_t)0x701d, (q15_t)0x7010, (q15_t)0x7004, (q15_t)0x6ff8, (q15_t)0x6fec, (q15_t)0x6fe0, (q15_t)0x6fd3, (q15_t)0x6fc7, + (q15_t)0x6fbb, (q15_t)0x6faf, (q15_t)0x6fa2, (q15_t)0x6f96, (q15_t)0x6f8a, (q15_t)0x6f7d, (q15_t)0x6f71, (q15_t)0x6f65, + (q15_t)0x6f58, (q15_t)0x6f4c, (q15_t)0x6f3f, (q15_t)0x6f33, (q15_t)0x6f27, (q15_t)0x6f1a, (q15_t)0x6f0e, (q15_t)0x6f01, + (q15_t)0x6ef5, (q15_t)0x6ee8, (q15_t)0x6edc, (q15_t)0x6ecf, (q15_t)0x6ec2, (q15_t)0x6eb6, (q15_t)0x6ea9, (q15_t)0x6e9c, + (q15_t)0x6e90, (q15_t)0x6e83, (q15_t)0x6e76, (q15_t)0x6e6a, (q15_t)0x6e5d, (q15_t)0x6e50, (q15_t)0x6e44, (q15_t)0x6e37, + (q15_t)0x6e2a, (q15_t)0x6e1d, (q15_t)0x6e10, (q15_t)0x6e04, (q15_t)0x6df7, (q15_t)0x6dea, (q15_t)0x6ddd, (q15_t)0x6dd0, + (q15_t)0x6dc3, (q15_t)0x6db6, (q15_t)0x6da9, (q15_t)0x6d9c, (q15_t)0x6d8f, (q15_t)0x6d82, (q15_t)0x6d75, (q15_t)0x6d68, + (q15_t)0x6d5b, (q15_t)0x6d4e, (q15_t)0x6d41, (q15_t)0x6d34, (q15_t)0x6d27, (q15_t)0x6d1a, (q15_t)0x6d0c, (q15_t)0x6cff, + (q15_t)0x6cf2, (q15_t)0x6ce5, (q15_t)0x6cd8, (q15_t)0x6cca, (q15_t)0x6cbd, (q15_t)0x6cb0, (q15_t)0x6ca3, (q15_t)0x6c95, + (q15_t)0x6c88, (q15_t)0x6c7b, (q15_t)0x6c6d, (q15_t)0x6c60, (q15_t)0x6c53, (q15_t)0x6c45, (q15_t)0x6c38, (q15_t)0x6c2a, + (q15_t)0x6c1d, (q15_t)0x6c0f, (q15_t)0x6c02, (q15_t)0x6bf5, (q15_t)0x6be7, (q15_t)0x6bd9, (q15_t)0x6bcc, (q15_t)0x6bbe, + (q15_t)0x6bb1, (q15_t)0x6ba3, (q15_t)0x6b96, (q15_t)0x6b88, (q15_t)0x6b7a, (q15_t)0x6b6d, (q15_t)0x6b5f, (q15_t)0x6b51, + (q15_t)0x6b44, (q15_t)0x6b36, (q15_t)0x6b28, (q15_t)0x6b1a, (q15_t)0x6b0d, (q15_t)0x6aff, (q15_t)0x6af1, (q15_t)0x6ae3, + (q15_t)0x6ad5, (q15_t)0x6ac8, (q15_t)0x6aba, (q15_t)0x6aac, (q15_t)0x6a9e, (q15_t)0x6a90, (q15_t)0x6a82, (q15_t)0x6a74, + (q15_t)0x6a66, (q15_t)0x6a58, (q15_t)0x6a4a, (q15_t)0x6a3c, (q15_t)0x6a2e, (q15_t)0x6a20, (q15_t)0x6a12, (q15_t)0x6a04, + (q15_t)0x69f6, (q15_t)0x69e8, (q15_t)0x69da, (q15_t)0x69cb, (q15_t)0x69bd, (q15_t)0x69af, (q15_t)0x69a1, (q15_t)0x6993, + (q15_t)0x6985, (q15_t)0x6976, (q15_t)0x6968, (q15_t)0x695a, (q15_t)0x694b, (q15_t)0x693d, (q15_t)0x692f, (q15_t)0x6921, + (q15_t)0x6912, (q15_t)0x6904, (q15_t)0x68f5, (q15_t)0x68e7, (q15_t)0x68d9, (q15_t)0x68ca, (q15_t)0x68bc, (q15_t)0x68ad, + (q15_t)0x689f, (q15_t)0x6890, (q15_t)0x6882, (q15_t)0x6873, (q15_t)0x6865, (q15_t)0x6856, (q15_t)0x6848, (q15_t)0x6839, + (q15_t)0x682b, (q15_t)0x681c, (q15_t)0x680d, (q15_t)0x67ff, (q15_t)0x67f0, (q15_t)0x67e1, (q15_t)0x67d3, (q15_t)0x67c4, + (q15_t)0x67b5, (q15_t)0x67a6, (q15_t)0x6798, (q15_t)0x6789, (q15_t)0x677a, (q15_t)0x676b, (q15_t)0x675d, (q15_t)0x674e, + (q15_t)0x673f, (q15_t)0x6730, (q15_t)0x6721, (q15_t)0x6712, (q15_t)0x6703, (q15_t)0x66f4, (q15_t)0x66e5, (q15_t)0x66d6, + (q15_t)0x66c8, (q15_t)0x66b9, (q15_t)0x66aa, (q15_t)0x669b, (q15_t)0x668b, (q15_t)0x667c, (q15_t)0x666d, (q15_t)0x665e, + (q15_t)0x664f, (q15_t)0x6640, (q15_t)0x6631, (q15_t)0x6622, (q15_t)0x6613, (q15_t)0x6603, (q15_t)0x65f4, (q15_t)0x65e5, + (q15_t)0x65d6, (q15_t)0x65c7, (q15_t)0x65b7, (q15_t)0x65a8, (q15_t)0x6599, (q15_t)0x658a, (q15_t)0x657a, (q15_t)0x656b, + (q15_t)0x655c, (q15_t)0x654c, (q15_t)0x653d, (q15_t)0x652d, (q15_t)0x651e, (q15_t)0x650f, (q15_t)0x64ff, (q15_t)0x64f0, + (q15_t)0x64e0, (q15_t)0x64d1, (q15_t)0x64c1, (q15_t)0x64b2, (q15_t)0x64a2, (q15_t)0x6493, (q15_t)0x6483, (q15_t)0x6474, + (q15_t)0x6464, (q15_t)0x6454, (q15_t)0x6445, (q15_t)0x6435, (q15_t)0x6426, (q15_t)0x6416, (q15_t)0x6406, (q15_t)0x63f7, + (q15_t)0x63e7, (q15_t)0x63d7, (q15_t)0x63c7, (q15_t)0x63b8, (q15_t)0x63a8, (q15_t)0x6398, (q15_t)0x6388, (q15_t)0x6378, + (q15_t)0x6369, (q15_t)0x6359, (q15_t)0x6349, (q15_t)0x6339, (q15_t)0x6329, (q15_t)0x6319, (q15_t)0x6309, (q15_t)0x62f9, + (q15_t)0x62ea, (q15_t)0x62da, (q15_t)0x62ca, (q15_t)0x62ba, (q15_t)0x62aa, (q15_t)0x629a, (q15_t)0x628a, (q15_t)0x627a, + (q15_t)0x6269, (q15_t)0x6259, (q15_t)0x6249, (q15_t)0x6239, (q15_t)0x6229, (q15_t)0x6219, (q15_t)0x6209, (q15_t)0x61f9, + (q15_t)0x61e8, (q15_t)0x61d8, (q15_t)0x61c8, (q15_t)0x61b8, (q15_t)0x61a8, (q15_t)0x6197, (q15_t)0x6187, (q15_t)0x6177, + (q15_t)0x6166, (q15_t)0x6156, (q15_t)0x6146, (q15_t)0x6135, (q15_t)0x6125, (q15_t)0x6115, (q15_t)0x6104, (q15_t)0x60f4, + (q15_t)0x60e4, (q15_t)0x60d3, (q15_t)0x60c3, (q15_t)0x60b2, (q15_t)0x60a2, (q15_t)0x6091, (q15_t)0x6081, (q15_t)0x6070, + (q15_t)0x6060, (q15_t)0x604f, (q15_t)0x603f, (q15_t)0x602e, (q15_t)0x601d, (q15_t)0x600d, (q15_t)0x5ffc, (q15_t)0x5fec, + (q15_t)0x5fdb, (q15_t)0x5fca, (q15_t)0x5fba, (q15_t)0x5fa9, (q15_t)0x5f98, (q15_t)0x5f87, (q15_t)0x5f77, (q15_t)0x5f66, + (q15_t)0x5f55, (q15_t)0x5f44, (q15_t)0x5f34, (q15_t)0x5f23, (q15_t)0x5f12, (q15_t)0x5f01, (q15_t)0x5ef0, (q15_t)0x5edf, + (q15_t)0x5ecf, (q15_t)0x5ebe, (q15_t)0x5ead, (q15_t)0x5e9c, (q15_t)0x5e8b, (q15_t)0x5e7a, (q15_t)0x5e69, (q15_t)0x5e58, + (q15_t)0x5e47, (q15_t)0x5e36, (q15_t)0x5e25, (q15_t)0x5e14, (q15_t)0x5e03, (q15_t)0x5df2, (q15_t)0x5de1, (q15_t)0x5dd0, + (q15_t)0x5dbf, (q15_t)0x5dad, (q15_t)0x5d9c, (q15_t)0x5d8b, (q15_t)0x5d7a, (q15_t)0x5d69, (q15_t)0x5d58, (q15_t)0x5d46, + (q15_t)0x5d35, (q15_t)0x5d24, (q15_t)0x5d13, (q15_t)0x5d01, (q15_t)0x5cf0, (q15_t)0x5cdf, (q15_t)0x5cce, (q15_t)0x5cbc, + (q15_t)0x5cab, (q15_t)0x5c9a, (q15_t)0x5c88, (q15_t)0x5c77, (q15_t)0x5c66, (q15_t)0x5c54, (q15_t)0x5c43, (q15_t)0x5c31, + (q15_t)0x5c20, (q15_t)0x5c0e, (q15_t)0x5bfd, (q15_t)0x5beb, (q15_t)0x5bda, (q15_t)0x5bc8, (q15_t)0x5bb7, (q15_t)0x5ba5, + (q15_t)0x5b94, (q15_t)0x5b82, (q15_t)0x5b71, (q15_t)0x5b5f, (q15_t)0x5b4d, (q15_t)0x5b3c, (q15_t)0x5b2a, (q15_t)0x5b19, + (q15_t)0x5b07, (q15_t)0x5af5, (q15_t)0x5ae4, (q15_t)0x5ad2, (q15_t)0x5ac0, (q15_t)0x5aae, (q15_t)0x5a9d, (q15_t)0x5a8b, + (q15_t)0x5a79, (q15_t)0x5a67, (q15_t)0x5a56, (q15_t)0x5a44, (q15_t)0x5a32, (q15_t)0x5a20, (q15_t)0x5a0e, (q15_t)0x59fc, + (q15_t)0x59ea, (q15_t)0x59d9, (q15_t)0x59c7, (q15_t)0x59b5, (q15_t)0x59a3, (q15_t)0x5991, (q15_t)0x597f, (q15_t)0x596d, + (q15_t)0x595b, (q15_t)0x5949, (q15_t)0x5937, (q15_t)0x5925, (q15_t)0x5913, (q15_t)0x5901, (q15_t)0x58ef, (q15_t)0x58dd, + (q15_t)0x58cb, (q15_t)0x58b8, (q15_t)0x58a6, (q15_t)0x5894, (q15_t)0x5882, (q15_t)0x5870, (q15_t)0x585e, (q15_t)0x584b, + (q15_t)0x5839, (q15_t)0x5827, (q15_t)0x5815, (q15_t)0x5803, (q15_t)0x57f0, (q15_t)0x57de, (q15_t)0x57cc, (q15_t)0x57b9, + (q15_t)0x57a7, (q15_t)0x5795, (q15_t)0x5783, (q15_t)0x5770, (q15_t)0x575e, (q15_t)0x574b, (q15_t)0x5739, (q15_t)0x5727, + (q15_t)0x5714, (q15_t)0x5702, (q15_t)0x56ef, (q15_t)0x56dd, (q15_t)0x56ca, (q15_t)0x56b8, (q15_t)0x56a5, (q15_t)0x5693, + (q15_t)0x5680, (q15_t)0x566e, (q15_t)0x565b, (q15_t)0x5649, (q15_t)0x5636, (q15_t)0x5624, (q15_t)0x5611, (q15_t)0x55fe, + (q15_t)0x55ec, (q15_t)0x55d9, (q15_t)0x55c7, (q15_t)0x55b4, (q15_t)0x55a1, (q15_t)0x558f, (q15_t)0x557c, (q15_t)0x5569, + (q15_t)0x5556, (q15_t)0x5544, (q15_t)0x5531, (q15_t)0x551e, (q15_t)0x550b, (q15_t)0x54f9, (q15_t)0x54e6, (q15_t)0x54d3, + (q15_t)0x54c0, (q15_t)0x54ad, (q15_t)0x549a, (q15_t)0x5488, (q15_t)0x5475, (q15_t)0x5462, (q15_t)0x544f, (q15_t)0x543c, + (q15_t)0x5429, (q15_t)0x5416, (q15_t)0x5403, (q15_t)0x53f0, (q15_t)0x53dd, (q15_t)0x53ca, (q15_t)0x53b7, (q15_t)0x53a4, + (q15_t)0x5391, (q15_t)0x537e, (q15_t)0x536b, (q15_t)0x5358, (q15_t)0x5345, (q15_t)0x5332, (q15_t)0x531f, (q15_t)0x530c, + (q15_t)0x52f8, (q15_t)0x52e5, (q15_t)0x52d2, (q15_t)0x52bf, (q15_t)0x52ac, (q15_t)0x5299, (q15_t)0x5285, (q15_t)0x5272, + (q15_t)0x525f, (q15_t)0x524c, (q15_t)0x5238, (q15_t)0x5225, (q15_t)0x5212, (q15_t)0x51ff, (q15_t)0x51eb, (q15_t)0x51d8, + (q15_t)0x51c5, (q15_t)0x51b1, (q15_t)0x519e, (q15_t)0x518b, (q15_t)0x5177, (q15_t)0x5164, (q15_t)0x5150, (q15_t)0x513d, + (q15_t)0x512a, (q15_t)0x5116, (q15_t)0x5103, (q15_t)0x50ef, (q15_t)0x50dc, (q15_t)0x50c8, (q15_t)0x50b5, (q15_t)0x50a1, + (q15_t)0x508e, (q15_t)0x507a, (q15_t)0x5067, (q15_t)0x5053, (q15_t)0x503f, (q15_t)0x502c, (q15_t)0x5018, (q15_t)0x5005, + (q15_t)0x4ff1, (q15_t)0x4fdd, (q15_t)0x4fca, (q15_t)0x4fb6, (q15_t)0x4fa2, (q15_t)0x4f8f, (q15_t)0x4f7b, (q15_t)0x4f67, + (q15_t)0x4f54, (q15_t)0x4f40, (q15_t)0x4f2c, (q15_t)0x4f18, (q15_t)0x4f05, (q15_t)0x4ef1, (q15_t)0x4edd, (q15_t)0x4ec9, + (q15_t)0x4eb6, (q15_t)0x4ea2, (q15_t)0x4e8e, (q15_t)0x4e7a, (q15_t)0x4e66, (q15_t)0x4e52, (q15_t)0x4e3e, (q15_t)0x4e2a, + (q15_t)0x4e17, (q15_t)0x4e03, (q15_t)0x4def, (q15_t)0x4ddb, (q15_t)0x4dc7, (q15_t)0x4db3, (q15_t)0x4d9f, (q15_t)0x4d8b, + (q15_t)0x4d77, (q15_t)0x4d63, (q15_t)0x4d4f, (q15_t)0x4d3b, (q15_t)0x4d27, (q15_t)0x4d13, (q15_t)0x4cff, (q15_t)0x4ceb, + (q15_t)0x4cd6, (q15_t)0x4cc2, (q15_t)0x4cae, (q15_t)0x4c9a, (q15_t)0x4c86, (q15_t)0x4c72, (q15_t)0x4c5e, (q15_t)0x4c49, + (q15_t)0x4c35, (q15_t)0x4c21, (q15_t)0x4c0d, (q15_t)0x4bf9, (q15_t)0x4be4, (q15_t)0x4bd0, (q15_t)0x4bbc, (q15_t)0x4ba8, + (q15_t)0x4b93, (q15_t)0x4b7f, (q15_t)0x4b6b, (q15_t)0x4b56, (q15_t)0x4b42, (q15_t)0x4b2e, (q15_t)0x4b19, (q15_t)0x4b05, + (q15_t)0x4af1, (q15_t)0x4adc, (q15_t)0x4ac8, (q15_t)0x4ab4, (q15_t)0x4a9f, (q15_t)0x4a8b, (q15_t)0x4a76, (q15_t)0x4a62, + (q15_t)0x4a4d, (q15_t)0x4a39, (q15_t)0x4a24, (q15_t)0x4a10, (q15_t)0x49fb, (q15_t)0x49e7, (q15_t)0x49d2, (q15_t)0x49be, + (q15_t)0x49a9, (q15_t)0x4995, (q15_t)0x4980, (q15_t)0x496c, (q15_t)0x4957, (q15_t)0x4942, (q15_t)0x492e, (q15_t)0x4919, + (q15_t)0x4905, (q15_t)0x48f0, (q15_t)0x48db, (q15_t)0x48c7, (q15_t)0x48b2, (q15_t)0x489d, (q15_t)0x4888, (q15_t)0x4874, + (q15_t)0x485f, (q15_t)0x484a, (q15_t)0x4836, (q15_t)0x4821, (q15_t)0x480c, (q15_t)0x47f7, (q15_t)0x47e2, (q15_t)0x47ce, + (q15_t)0x47b9, (q15_t)0x47a4, (q15_t)0x478f, (q15_t)0x477a, (q15_t)0x4765, (q15_t)0x4751, (q15_t)0x473c, (q15_t)0x4727, + (q15_t)0x4712, (q15_t)0x46fd, (q15_t)0x46e8, (q15_t)0x46d3, (q15_t)0x46be, (q15_t)0x46a9, (q15_t)0x4694, (q15_t)0x467f, + (q15_t)0x466a, (q15_t)0x4655, (q15_t)0x4640, (q15_t)0x462b, (q15_t)0x4616, (q15_t)0x4601, (q15_t)0x45ec, (q15_t)0x45d7, + (q15_t)0x45c2, (q15_t)0x45ad, (q15_t)0x4598, (q15_t)0x4583, (q15_t)0x456e, (q15_t)0x4559, (q15_t)0x4544, (q15_t)0x452e, + (q15_t)0x4519, (q15_t)0x4504, (q15_t)0x44ef, (q15_t)0x44da, (q15_t)0x44c5, (q15_t)0x44af, (q15_t)0x449a, (q15_t)0x4485, + (q15_t)0x4470, (q15_t)0x445a, (q15_t)0x4445, (q15_t)0x4430, (q15_t)0x441b, (q15_t)0x4405, (q15_t)0x43f0, (q15_t)0x43db, + (q15_t)0x43c5, (q15_t)0x43b0, (q15_t)0x439b, (q15_t)0x4385, (q15_t)0x4370, (q15_t)0x435b, (q15_t)0x4345, (q15_t)0x4330, + (q15_t)0x431b, (q15_t)0x4305, (q15_t)0x42f0, (q15_t)0x42da, (q15_t)0x42c5, (q15_t)0x42af, (q15_t)0x429a, (q15_t)0x4284, + (q15_t)0x426f, (q15_t)0x425a, (q15_t)0x4244, (q15_t)0x422f, (q15_t)0x4219, (q15_t)0x4203, (q15_t)0x41ee, (q15_t)0x41d8, + (q15_t)0x41c3, (q15_t)0x41ad, (q15_t)0x4198, (q15_t)0x4182, (q15_t)0x416d, (q15_t)0x4157, (q15_t)0x4141, (q15_t)0x412c, + (q15_t)0x4116, (q15_t)0x4100, (q15_t)0x40eb, (q15_t)0x40d5, (q15_t)0x40bf, (q15_t)0x40aa, (q15_t)0x4094, (q15_t)0x407e, + (q15_t)0x4069, (q15_t)0x4053, (q15_t)0x403d, (q15_t)0x4027, (q15_t)0x4012, (q15_t)0x3ffc, (q15_t)0x3fe6, (q15_t)0x3fd0, + (q15_t)0x3fbb, (q15_t)0x3fa5, (q15_t)0x3f8f, (q15_t)0x3f79, (q15_t)0x3f63, (q15_t)0x3f4d, (q15_t)0x3f38, (q15_t)0x3f22, + (q15_t)0x3f0c, (q15_t)0x3ef6, (q15_t)0x3ee0, (q15_t)0x3eca, (q15_t)0x3eb4, (q15_t)0x3e9e, (q15_t)0x3e88, (q15_t)0x3e73, + (q15_t)0x3e5d, (q15_t)0x3e47, (q15_t)0x3e31, (q15_t)0x3e1b, (q15_t)0x3e05, (q15_t)0x3def, (q15_t)0x3dd9, (q15_t)0x3dc3, + (q15_t)0x3dad, (q15_t)0x3d97, (q15_t)0x3d81, (q15_t)0x3d6b, (q15_t)0x3d55, (q15_t)0x3d3e, (q15_t)0x3d28, (q15_t)0x3d12, + (q15_t)0x3cfc, (q15_t)0x3ce6, (q15_t)0x3cd0, (q15_t)0x3cba, (q15_t)0x3ca4, (q15_t)0x3c8e, (q15_t)0x3c77, (q15_t)0x3c61, + (q15_t)0x3c4b, (q15_t)0x3c35, (q15_t)0x3c1f, (q15_t)0x3c09, (q15_t)0x3bf2, (q15_t)0x3bdc, (q15_t)0x3bc6, (q15_t)0x3bb0, + (q15_t)0x3b99, (q15_t)0x3b83, (q15_t)0x3b6d, (q15_t)0x3b57, (q15_t)0x3b40, (q15_t)0x3b2a, (q15_t)0x3b14, (q15_t)0x3afe, + (q15_t)0x3ae7, (q15_t)0x3ad1, (q15_t)0x3abb, (q15_t)0x3aa4, (q15_t)0x3a8e, (q15_t)0x3a78, (q15_t)0x3a61, (q15_t)0x3a4b, + (q15_t)0x3a34, (q15_t)0x3a1e, (q15_t)0x3a08, (q15_t)0x39f1, (q15_t)0x39db, (q15_t)0x39c4, (q15_t)0x39ae, (q15_t)0x3998, + (q15_t)0x3981, (q15_t)0x396b, (q15_t)0x3954, (q15_t)0x393e, (q15_t)0x3927, (q15_t)0x3911, (q15_t)0x38fa, (q15_t)0x38e4, + (q15_t)0x38cd, (q15_t)0x38b7, (q15_t)0x38a0, (q15_t)0x388a, (q15_t)0x3873, (q15_t)0x385d, (q15_t)0x3846, (q15_t)0x382f, + (q15_t)0x3819, (q15_t)0x3802, (q15_t)0x37ec, (q15_t)0x37d5, (q15_t)0x37be, (q15_t)0x37a8, (q15_t)0x3791, (q15_t)0x377a, + (q15_t)0x3764, (q15_t)0x374d, (q15_t)0x3736, (q15_t)0x3720, (q15_t)0x3709, (q15_t)0x36f2, (q15_t)0x36dc, (q15_t)0x36c5, + (q15_t)0x36ae, (q15_t)0x3698, (q15_t)0x3681, (q15_t)0x366a, (q15_t)0x3653, (q15_t)0x363d, (q15_t)0x3626, (q15_t)0x360f, + (q15_t)0x35f8, (q15_t)0x35e1, (q15_t)0x35cb, (q15_t)0x35b4, (q15_t)0x359d, (q15_t)0x3586, (q15_t)0x356f, (q15_t)0x3558, + (q15_t)0x3542, (q15_t)0x352b, (q15_t)0x3514, (q15_t)0x34fd, (q15_t)0x34e6, (q15_t)0x34cf, (q15_t)0x34b8, (q15_t)0x34a1, + (q15_t)0x348b, (q15_t)0x3474, (q15_t)0x345d, (q15_t)0x3446, (q15_t)0x342f, (q15_t)0x3418, (q15_t)0x3401, (q15_t)0x33ea, + (q15_t)0x33d3, (q15_t)0x33bc, (q15_t)0x33a5, (q15_t)0x338e, (q15_t)0x3377, (q15_t)0x3360, (q15_t)0x3349, (q15_t)0x3332, + (q15_t)0x331b, (q15_t)0x3304, (q15_t)0x32ed, (q15_t)0x32d6, (q15_t)0x32bf, (q15_t)0x32a8, (q15_t)0x3290, (q15_t)0x3279, + (q15_t)0x3262, (q15_t)0x324b, (q15_t)0x3234, (q15_t)0x321d, (q15_t)0x3206, (q15_t)0x31ef, (q15_t)0x31d8, (q15_t)0x31c0, + (q15_t)0x31a9, (q15_t)0x3192, (q15_t)0x317b, (q15_t)0x3164, (q15_t)0x314c, (q15_t)0x3135, (q15_t)0x311e, (q15_t)0x3107, + (q15_t)0x30f0, (q15_t)0x30d8, (q15_t)0x30c1, (q15_t)0x30aa, (q15_t)0x3093, (q15_t)0x307b, (q15_t)0x3064, (q15_t)0x304d, + (q15_t)0x3036, (q15_t)0x301e, (q15_t)0x3007, (q15_t)0x2ff0, (q15_t)0x2fd8, (q15_t)0x2fc1, (q15_t)0x2faa, (q15_t)0x2f92, + (q15_t)0x2f7b, (q15_t)0x2f64, (q15_t)0x2f4c, (q15_t)0x2f35, (q15_t)0x2f1e, (q15_t)0x2f06, (q15_t)0x2eef, (q15_t)0x2ed8, + (q15_t)0x2ec0, (q15_t)0x2ea9, (q15_t)0x2e91, (q15_t)0x2e7a, (q15_t)0x2e63, (q15_t)0x2e4b, (q15_t)0x2e34, (q15_t)0x2e1c, + (q15_t)0x2e05, (q15_t)0x2ded, (q15_t)0x2dd6, (q15_t)0x2dbe, (q15_t)0x2da7, (q15_t)0x2d8f, (q15_t)0x2d78, (q15_t)0x2d60, + (q15_t)0x2d49, (q15_t)0x2d31, (q15_t)0x2d1a, (q15_t)0x2d02, (q15_t)0x2ceb, (q15_t)0x2cd3, (q15_t)0x2cbc, (q15_t)0x2ca4, + (q15_t)0x2c8d, (q15_t)0x2c75, (q15_t)0x2c5e, (q15_t)0x2c46, (q15_t)0x2c2e, (q15_t)0x2c17, (q15_t)0x2bff, (q15_t)0x2be8, + (q15_t)0x2bd0, (q15_t)0x2bb8, (q15_t)0x2ba1, (q15_t)0x2b89, (q15_t)0x2b71, (q15_t)0x2b5a, (q15_t)0x2b42, (q15_t)0x2b2b, + (q15_t)0x2b13, (q15_t)0x2afb, (q15_t)0x2ae4, (q15_t)0x2acc, (q15_t)0x2ab4, (q15_t)0x2a9c, (q15_t)0x2a85, (q15_t)0x2a6d, + (q15_t)0x2a55, (q15_t)0x2a3e, (q15_t)0x2a26, (q15_t)0x2a0e, (q15_t)0x29f6, (q15_t)0x29df, (q15_t)0x29c7, (q15_t)0x29af, + (q15_t)0x2997, (q15_t)0x2980, (q15_t)0x2968, (q15_t)0x2950, (q15_t)0x2938, (q15_t)0x2920, (q15_t)0x2909, (q15_t)0x28f1, + (q15_t)0x28d9, (q15_t)0x28c1, (q15_t)0x28a9, (q15_t)0x2892, (q15_t)0x287a, (q15_t)0x2862, (q15_t)0x284a, (q15_t)0x2832, + (q15_t)0x281a, (q15_t)0x2802, (q15_t)0x27eb, (q15_t)0x27d3, (q15_t)0x27bb, (q15_t)0x27a3, (q15_t)0x278b, (q15_t)0x2773, + (q15_t)0x275b, (q15_t)0x2743, (q15_t)0x272b, (q15_t)0x2713, (q15_t)0x26fb, (q15_t)0x26e4, (q15_t)0x26cc, (q15_t)0x26b4, + (q15_t)0x269c, (q15_t)0x2684, (q15_t)0x266c, (q15_t)0x2654, (q15_t)0x263c, (q15_t)0x2624, (q15_t)0x260c, (q15_t)0x25f4, + (q15_t)0x25dc, (q15_t)0x25c4, (q15_t)0x25ac, (q15_t)0x2594, (q15_t)0x257c, (q15_t)0x2564, (q15_t)0x254c, (q15_t)0x2534, + (q15_t)0x251c, (q15_t)0x2503, (q15_t)0x24eb, (q15_t)0x24d3, (q15_t)0x24bb, (q15_t)0x24a3, (q15_t)0x248b, (q15_t)0x2473, + (q15_t)0x245b, (q15_t)0x2443, (q15_t)0x242b, (q15_t)0x2413, (q15_t)0x23fa, (q15_t)0x23e2, (q15_t)0x23ca, (q15_t)0x23b2, + (q15_t)0x239a, (q15_t)0x2382, (q15_t)0x236a, (q15_t)0x2352, (q15_t)0x2339, (q15_t)0x2321, (q15_t)0x2309, (q15_t)0x22f1, + (q15_t)0x22d9, (q15_t)0x22c0, (q15_t)0x22a8, (q15_t)0x2290, (q15_t)0x2278, (q15_t)0x2260, (q15_t)0x2247, (q15_t)0x222f, + (q15_t)0x2217, (q15_t)0x21ff, (q15_t)0x21e7, (q15_t)0x21ce, (q15_t)0x21b6, (q15_t)0x219e, (q15_t)0x2186, (q15_t)0x216d, + (q15_t)0x2155, (q15_t)0x213d, (q15_t)0x2125, (q15_t)0x210c, (q15_t)0x20f4, (q15_t)0x20dc, (q15_t)0x20c3, (q15_t)0x20ab, + (q15_t)0x2093, (q15_t)0x207a, (q15_t)0x2062, (q15_t)0x204a, (q15_t)0x2032, (q15_t)0x2019, (q15_t)0x2001, (q15_t)0x1fe9, + (q15_t)0x1fd0, (q15_t)0x1fb8, (q15_t)0x1f9f, (q15_t)0x1f87, (q15_t)0x1f6f, (q15_t)0x1f56, (q15_t)0x1f3e, (q15_t)0x1f26, + (q15_t)0x1f0d, (q15_t)0x1ef5, (q15_t)0x1edd, (q15_t)0x1ec4, (q15_t)0x1eac, (q15_t)0x1e93, (q15_t)0x1e7b, (q15_t)0x1e62, + (q15_t)0x1e4a, (q15_t)0x1e32, (q15_t)0x1e19, (q15_t)0x1e01, (q15_t)0x1de8, (q15_t)0x1dd0, (q15_t)0x1db7, (q15_t)0x1d9f, + (q15_t)0x1d87, (q15_t)0x1d6e, (q15_t)0x1d56, (q15_t)0x1d3d, (q15_t)0x1d25, (q15_t)0x1d0c, (q15_t)0x1cf4, (q15_t)0x1cdb, + (q15_t)0x1cc3, (q15_t)0x1caa, (q15_t)0x1c92, (q15_t)0x1c79, (q15_t)0x1c61, (q15_t)0x1c48, (q15_t)0x1c30, (q15_t)0x1c17, + (q15_t)0x1bff, (q15_t)0x1be6, (q15_t)0x1bce, (q15_t)0x1bb5, (q15_t)0x1b9d, (q15_t)0x1b84, (q15_t)0x1b6c, (q15_t)0x1b53, + (q15_t)0x1b3a, (q15_t)0x1b22, (q15_t)0x1b09, (q15_t)0x1af1, (q15_t)0x1ad8, (q15_t)0x1ac0, (q15_t)0x1aa7, (q15_t)0x1a8e, + (q15_t)0x1a76, (q15_t)0x1a5d, (q15_t)0x1a45, (q15_t)0x1a2c, (q15_t)0x1a13, (q15_t)0x19fb, (q15_t)0x19e2, (q15_t)0x19ca, + (q15_t)0x19b1, (q15_t)0x1998, (q15_t)0x1980, (q15_t)0x1967, (q15_t)0x194e, (q15_t)0x1936, (q15_t)0x191d, (q15_t)0x1905, + (q15_t)0x18ec, (q15_t)0x18d3, (q15_t)0x18bb, (q15_t)0x18a2, (q15_t)0x1889, (q15_t)0x1871, (q15_t)0x1858, (q15_t)0x183f, + (q15_t)0x1827, (q15_t)0x180e, (q15_t)0x17f5, (q15_t)0x17dd, (q15_t)0x17c4, (q15_t)0x17ab, (q15_t)0x1792, (q15_t)0x177a, + (q15_t)0x1761, (q15_t)0x1748, (q15_t)0x1730, (q15_t)0x1717, (q15_t)0x16fe, (q15_t)0x16e5, (q15_t)0x16cd, (q15_t)0x16b4, + (q15_t)0x169b, (q15_t)0x1682, (q15_t)0x166a, (q15_t)0x1651, (q15_t)0x1638, (q15_t)0x161f, (q15_t)0x1607, (q15_t)0x15ee, + (q15_t)0x15d5, (q15_t)0x15bc, (q15_t)0x15a4, (q15_t)0x158b, (q15_t)0x1572, (q15_t)0x1559, (q15_t)0x1541, (q15_t)0x1528, + (q15_t)0x150f, (q15_t)0x14f6, (q15_t)0x14dd, (q15_t)0x14c5, (q15_t)0x14ac, (q15_t)0x1493, (q15_t)0x147a, (q15_t)0x1461, + (q15_t)0x1449, (q15_t)0x1430, (q15_t)0x1417, (q15_t)0x13fe, (q15_t)0x13e5, (q15_t)0x13cc, (q15_t)0x13b4, (q15_t)0x139b, + (q15_t)0x1382, (q15_t)0x1369, (q15_t)0x1350, (q15_t)0x1337, (q15_t)0x131f, (q15_t)0x1306, (q15_t)0x12ed, (q15_t)0x12d4, + (q15_t)0x12bb, (q15_t)0x12a2, (q15_t)0x1289, (q15_t)0x1271, (q15_t)0x1258, (q15_t)0x123f, (q15_t)0x1226, (q15_t)0x120d, + (q15_t)0x11f4, (q15_t)0x11db, (q15_t)0x11c2, (q15_t)0x11a9, (q15_t)0x1191, (q15_t)0x1178, (q15_t)0x115f, (q15_t)0x1146, + (q15_t)0x112d, (q15_t)0x1114, (q15_t)0x10fb, (q15_t)0x10e2, (q15_t)0x10c9, (q15_t)0x10b0, (q15_t)0x1098, (q15_t)0x107f, + (q15_t)0x1066, (q15_t)0x104d, (q15_t)0x1034, (q15_t)0x101b, (q15_t)0x1002, (q15_t)0xfe9, (q15_t)0xfd0, (q15_t)0xfb7, + (q15_t)0xf9e, (q15_t)0xf85, (q15_t)0xf6c, (q15_t)0xf53, (q15_t)0xf3a, (q15_t)0xf21, (q15_t)0xf08, (q15_t)0xef0, + (q15_t)0xed7, (q15_t)0xebe, (q15_t)0xea5, (q15_t)0xe8c, (q15_t)0xe73, (q15_t)0xe5a, (q15_t)0xe41, (q15_t)0xe28, + (q15_t)0xe0f, (q15_t)0xdf6, (q15_t)0xddd, (q15_t)0xdc4, (q15_t)0xdab, (q15_t)0xd92, (q15_t)0xd79, (q15_t)0xd60, + (q15_t)0xd47, (q15_t)0xd2e, (q15_t)0xd15, (q15_t)0xcfc, (q15_t)0xce3, (q15_t)0xcca, (q15_t)0xcb1, (q15_t)0xc98, + (q15_t)0xc7f, (q15_t)0xc66, (q15_t)0xc4d, (q15_t)0xc34, (q15_t)0xc1b, (q15_t)0xc02, (q15_t)0xbe9, (q15_t)0xbd0, + (q15_t)0xbb7, (q15_t)0xb9e, (q15_t)0xb85, (q15_t)0xb6c, (q15_t)0xb53, (q15_t)0xb3a, (q15_t)0xb20, (q15_t)0xb07, + (q15_t)0xaee, (q15_t)0xad5, (q15_t)0xabc, (q15_t)0xaa3, (q15_t)0xa8a, (q15_t)0xa71, (q15_t)0xa58, (q15_t)0xa3f, + (q15_t)0xa26, (q15_t)0xa0d, (q15_t)0x9f4, (q15_t)0x9db, (q15_t)0x9c2, (q15_t)0x9a9, (q15_t)0x990, (q15_t)0x977, + (q15_t)0x95e, (q15_t)0x944, (q15_t)0x92b, (q15_t)0x912, (q15_t)0x8f9, (q15_t)0x8e0, (q15_t)0x8c7, (q15_t)0x8ae, + (q15_t)0x895, (q15_t)0x87c, (q15_t)0x863, (q15_t)0x84a, (q15_t)0x831, (q15_t)0x818, (q15_t)0x7fe, (q15_t)0x7e5, + (q15_t)0x7cc, (q15_t)0x7b3, (q15_t)0x79a, (q15_t)0x781, (q15_t)0x768, (q15_t)0x74f, (q15_t)0x736, (q15_t)0x71d, + (q15_t)0x704, (q15_t)0x6ea, (q15_t)0x6d1, (q15_t)0x6b8, (q15_t)0x69f, (q15_t)0x686, (q15_t)0x66d, (q15_t)0x654, + (q15_t)0x63b, (q15_t)0x622, (q15_t)0x609, (q15_t)0x5ef, (q15_t)0x5d6, (q15_t)0x5bd, (q15_t)0x5a4, (q15_t)0x58b, + (q15_t)0x572, (q15_t)0x559, (q15_t)0x540, (q15_t)0x527, (q15_t)0x50d, (q15_t)0x4f4, (q15_t)0x4db, (q15_t)0x4c2, + (q15_t)0x4a9, (q15_t)0x490, (q15_t)0x477, (q15_t)0x45e, (q15_t)0x445, (q15_t)0x42b, (q15_t)0x412, (q15_t)0x3f9, + (q15_t)0x3e0, (q15_t)0x3c7, (q15_t)0x3ae, (q15_t)0x395, (q15_t)0x37c, (q15_t)0x362, (q15_t)0x349, (q15_t)0x330, + (q15_t)0x317, (q15_t)0x2fe, (q15_t)0x2e5, (q15_t)0x2cc, (q15_t)0x2b3, (q15_t)0x299, (q15_t)0x280, (q15_t)0x267, + (q15_t)0x24e, (q15_t)0x235, (q15_t)0x21c, (q15_t)0x203, (q15_t)0x1ea, (q15_t)0x1d0, (q15_t)0x1b7, (q15_t)0x19e, + (q15_t)0x185, (q15_t)0x16c, (q15_t)0x153, (q15_t)0x13a, (q15_t)0x121, (q15_t)0x107, (q15_t)0xee, (q15_t)0xd5, + (q15_t)0xbc, (q15_t)0xa3, (q15_t)0x8a, (q15_t)0x71, (q15_t)0x57, (q15_t)0x3e, (q15_t)0x25, (q15_t)0xc + +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + const q15_t __ALIGNED(4) WeightsQ15_8192[16384] = { + (q15_t)0x7fff, (q15_t)0x0, (q15_t)0x7fff, (q15_t)0xfffa, (q15_t)0x7fff, (q15_t)0xfff4, (q15_t)0x7fff, (q15_t)0xffee, + (q15_t)0x7fff, (q15_t)0xffe7, (q15_t)0x7fff, (q15_t)0xffe1, (q15_t)0x7fff, (q15_t)0xffdb, (q15_t)0x7fff, (q15_t)0xffd5, + (q15_t)0x7fff, (q15_t)0xffce, (q15_t)0x7fff, (q15_t)0xffc8, (q15_t)0x7fff, (q15_t)0xffc2, (q15_t)0x7fff, (q15_t)0xffbb, + (q15_t)0x7fff, (q15_t)0xffb5, (q15_t)0x7fff, (q15_t)0xffaf, (q15_t)0x7fff, (q15_t)0xffa9, (q15_t)0x7fff, (q15_t)0xffa2, + (q15_t)0x7fff, (q15_t)0xff9c, (q15_t)0x7fff, (q15_t)0xff96, (q15_t)0x7fff, (q15_t)0xff8f, (q15_t)0x7fff, (q15_t)0xff89, + (q15_t)0x7fff, (q15_t)0xff83, (q15_t)0x7fff, (q15_t)0xff7d, (q15_t)0x7fff, (q15_t)0xff76, (q15_t)0x7fff, (q15_t)0xff70, + (q15_t)0x7fff, (q15_t)0xff6a, (q15_t)0x7fff, (q15_t)0xff63, (q15_t)0x7fff, (q15_t)0xff5d, (q15_t)0x7fff, (q15_t)0xff57, + (q15_t)0x7fff, (q15_t)0xff51, (q15_t)0x7fff, (q15_t)0xff4a, (q15_t)0x7fff, (q15_t)0xff44, (q15_t)0x7fff, (q15_t)0xff3e, + (q15_t)0x7fff, (q15_t)0xff37, (q15_t)0x7fff, (q15_t)0xff31, (q15_t)0x7fff, (q15_t)0xff2b, (q15_t)0x7fff, (q15_t)0xff25, + (q15_t)0x7fff, (q15_t)0xff1e, (q15_t)0x7fff, (q15_t)0xff18, (q15_t)0x7fff, (q15_t)0xff12, (q15_t)0x7fff, (q15_t)0xff0b, + (q15_t)0x7fff, (q15_t)0xff05, (q15_t)0x7ffe, (q15_t)0xfeff, (q15_t)0x7ffe, (q15_t)0xfef9, (q15_t)0x7ffe, (q15_t)0xfef2, + (q15_t)0x7ffe, (q15_t)0xfeec, (q15_t)0x7ffe, (q15_t)0xfee6, (q15_t)0x7ffe, (q15_t)0xfedf, (q15_t)0x7ffe, (q15_t)0xfed9, + (q15_t)0x7ffe, (q15_t)0xfed3, (q15_t)0x7ffe, (q15_t)0xfecd, (q15_t)0x7ffe, (q15_t)0xfec6, (q15_t)0x7ffe, (q15_t)0xfec0, + (q15_t)0x7ffe, (q15_t)0xfeba, (q15_t)0x7ffe, (q15_t)0xfeb3, (q15_t)0x7ffe, (q15_t)0xfead, (q15_t)0x7ffe, (q15_t)0xfea7, + (q15_t)0x7ffe, (q15_t)0xfea1, (q15_t)0x7ffe, (q15_t)0xfe9a, (q15_t)0x7ffd, (q15_t)0xfe94, (q15_t)0x7ffd, (q15_t)0xfe8e, + (q15_t)0x7ffd, (q15_t)0xfe88, (q15_t)0x7ffd, (q15_t)0xfe81, (q15_t)0x7ffd, (q15_t)0xfe7b, (q15_t)0x7ffd, (q15_t)0xfe75, + (q15_t)0x7ffd, (q15_t)0xfe6e, (q15_t)0x7ffd, (q15_t)0xfe68, (q15_t)0x7ffd, (q15_t)0xfe62, (q15_t)0x7ffd, (q15_t)0xfe5c, + (q15_t)0x7ffd, (q15_t)0xfe55, (q15_t)0x7ffd, (q15_t)0xfe4f, (q15_t)0x7ffd, (q15_t)0xfe49, (q15_t)0x7ffc, (q15_t)0xfe42, + (q15_t)0x7ffc, (q15_t)0xfe3c, (q15_t)0x7ffc, (q15_t)0xfe36, (q15_t)0x7ffc, (q15_t)0xfe30, (q15_t)0x7ffc, (q15_t)0xfe29, + (q15_t)0x7ffc, (q15_t)0xfe23, (q15_t)0x7ffc, (q15_t)0xfe1d, (q15_t)0x7ffc, (q15_t)0xfe16, (q15_t)0x7ffc, (q15_t)0xfe10, + (q15_t)0x7ffc, (q15_t)0xfe0a, (q15_t)0x7ffc, (q15_t)0xfe04, (q15_t)0x7ffb, (q15_t)0xfdfd, (q15_t)0x7ffb, (q15_t)0xfdf7, + (q15_t)0x7ffb, (q15_t)0xfdf1, (q15_t)0x7ffb, (q15_t)0xfdea, (q15_t)0x7ffb, (q15_t)0xfde4, (q15_t)0x7ffb, (q15_t)0xfdde, + (q15_t)0x7ffb, (q15_t)0xfdd8, (q15_t)0x7ffb, (q15_t)0xfdd1, (q15_t)0x7ffb, (q15_t)0xfdcb, (q15_t)0x7ffb, (q15_t)0xfdc5, + (q15_t)0x7ffa, (q15_t)0xfdbe, (q15_t)0x7ffa, (q15_t)0xfdb8, (q15_t)0x7ffa, (q15_t)0xfdb2, (q15_t)0x7ffa, (q15_t)0xfdac, + (q15_t)0x7ffa, (q15_t)0xfda5, (q15_t)0x7ffa, (q15_t)0xfd9f, (q15_t)0x7ffa, (q15_t)0xfd99, (q15_t)0x7ffa, (q15_t)0xfd93, + (q15_t)0x7ff9, (q15_t)0xfd8c, (q15_t)0x7ff9, (q15_t)0xfd86, (q15_t)0x7ff9, (q15_t)0xfd80, (q15_t)0x7ff9, (q15_t)0xfd79, + (q15_t)0x7ff9, (q15_t)0xfd73, (q15_t)0x7ff9, (q15_t)0xfd6d, (q15_t)0x7ff9, (q15_t)0xfd67, (q15_t)0x7ff9, (q15_t)0xfd60, + (q15_t)0x7ff8, (q15_t)0xfd5a, (q15_t)0x7ff8, (q15_t)0xfd54, (q15_t)0x7ff8, (q15_t)0xfd4d, (q15_t)0x7ff8, (q15_t)0xfd47, + (q15_t)0x7ff8, (q15_t)0xfd41, (q15_t)0x7ff8, (q15_t)0xfd3b, (q15_t)0x7ff8, (q15_t)0xfd34, (q15_t)0x7ff8, (q15_t)0xfd2e, + (q15_t)0x7ff7, (q15_t)0xfd28, (q15_t)0x7ff7, (q15_t)0xfd21, (q15_t)0x7ff7, (q15_t)0xfd1b, (q15_t)0x7ff7, (q15_t)0xfd15, + (q15_t)0x7ff7, (q15_t)0xfd0f, (q15_t)0x7ff7, (q15_t)0xfd08, (q15_t)0x7ff7, (q15_t)0xfd02, (q15_t)0x7ff6, (q15_t)0xfcfc, + (q15_t)0x7ff6, (q15_t)0xfcf5, (q15_t)0x7ff6, (q15_t)0xfcef, (q15_t)0x7ff6, (q15_t)0xfce9, (q15_t)0x7ff6, (q15_t)0xfce3, + (q15_t)0x7ff6, (q15_t)0xfcdc, (q15_t)0x7ff5, (q15_t)0xfcd6, (q15_t)0x7ff5, (q15_t)0xfcd0, (q15_t)0x7ff5, (q15_t)0xfcc9, + (q15_t)0x7ff5, (q15_t)0xfcc3, (q15_t)0x7ff5, (q15_t)0xfcbd, (q15_t)0x7ff5, (q15_t)0xfcb7, (q15_t)0x7ff5, (q15_t)0xfcb0, + (q15_t)0x7ff4, (q15_t)0xfcaa, (q15_t)0x7ff4, (q15_t)0xfca4, (q15_t)0x7ff4, (q15_t)0xfc9e, (q15_t)0x7ff4, (q15_t)0xfc97, + (q15_t)0x7ff4, (q15_t)0xfc91, (q15_t)0x7ff4, (q15_t)0xfc8b, (q15_t)0x7ff3, (q15_t)0xfc84, (q15_t)0x7ff3, (q15_t)0xfc7e, + (q15_t)0x7ff3, (q15_t)0xfc78, (q15_t)0x7ff3, (q15_t)0xfc72, (q15_t)0x7ff3, (q15_t)0xfc6b, (q15_t)0x7ff2, (q15_t)0xfc65, + (q15_t)0x7ff2, (q15_t)0xfc5f, (q15_t)0x7ff2, (q15_t)0xfc58, (q15_t)0x7ff2, (q15_t)0xfc52, (q15_t)0x7ff2, (q15_t)0xfc4c, + (q15_t)0x7ff2, (q15_t)0xfc46, (q15_t)0x7ff1, (q15_t)0xfc3f, (q15_t)0x7ff1, (q15_t)0xfc39, (q15_t)0x7ff1, (q15_t)0xfc33, + (q15_t)0x7ff1, (q15_t)0xfc2c, (q15_t)0x7ff1, (q15_t)0xfc26, (q15_t)0x7ff0, (q15_t)0xfc20, (q15_t)0x7ff0, (q15_t)0xfc1a, + (q15_t)0x7ff0, (q15_t)0xfc13, (q15_t)0x7ff0, (q15_t)0xfc0d, (q15_t)0x7ff0, (q15_t)0xfc07, (q15_t)0x7fef, (q15_t)0xfc01, + (q15_t)0x7fef, (q15_t)0xfbfa, (q15_t)0x7fef, (q15_t)0xfbf4, (q15_t)0x7fef, (q15_t)0xfbee, (q15_t)0x7fef, (q15_t)0xfbe7, + (q15_t)0x7fee, (q15_t)0xfbe1, (q15_t)0x7fee, (q15_t)0xfbdb, (q15_t)0x7fee, (q15_t)0xfbd5, (q15_t)0x7fee, (q15_t)0xfbce, + (q15_t)0x7fee, (q15_t)0xfbc8, (q15_t)0x7fed, (q15_t)0xfbc2, (q15_t)0x7fed, (q15_t)0xfbbb, (q15_t)0x7fed, (q15_t)0xfbb5, + (q15_t)0x7fed, (q15_t)0xfbaf, (q15_t)0x7fed, (q15_t)0xfba9, (q15_t)0x7fec, (q15_t)0xfba2, (q15_t)0x7fec, (q15_t)0xfb9c, + (q15_t)0x7fec, (q15_t)0xfb96, (q15_t)0x7fec, (q15_t)0xfb8f, (q15_t)0x7fec, (q15_t)0xfb89, (q15_t)0x7feb, (q15_t)0xfb83, + (q15_t)0x7feb, (q15_t)0xfb7d, (q15_t)0x7feb, (q15_t)0xfb76, (q15_t)0x7feb, (q15_t)0xfb70, (q15_t)0x7fea, (q15_t)0xfb6a, + (q15_t)0x7fea, (q15_t)0xfb64, (q15_t)0x7fea, (q15_t)0xfb5d, (q15_t)0x7fea, (q15_t)0xfb57, (q15_t)0x7fea, (q15_t)0xfb51, + (q15_t)0x7fe9, (q15_t)0xfb4a, (q15_t)0x7fe9, (q15_t)0xfb44, (q15_t)0x7fe9, (q15_t)0xfb3e, (q15_t)0x7fe9, (q15_t)0xfb38, + (q15_t)0x7fe8, (q15_t)0xfb31, (q15_t)0x7fe8, (q15_t)0xfb2b, (q15_t)0x7fe8, (q15_t)0xfb25, (q15_t)0x7fe8, (q15_t)0xfb1e, + (q15_t)0x7fe7, (q15_t)0xfb18, (q15_t)0x7fe7, (q15_t)0xfb12, (q15_t)0x7fe7, (q15_t)0xfb0c, (q15_t)0x7fe7, (q15_t)0xfb05, + (q15_t)0x7fe6, (q15_t)0xfaff, (q15_t)0x7fe6, (q15_t)0xfaf9, (q15_t)0x7fe6, (q15_t)0xfaf3, (q15_t)0x7fe6, (q15_t)0xfaec, + (q15_t)0x7fe5, (q15_t)0xfae6, (q15_t)0x7fe5, (q15_t)0xfae0, (q15_t)0x7fe5, (q15_t)0xfad9, (q15_t)0x7fe5, (q15_t)0xfad3, + (q15_t)0x7fe4, (q15_t)0xfacd, (q15_t)0x7fe4, (q15_t)0xfac7, (q15_t)0x7fe4, (q15_t)0xfac0, (q15_t)0x7fe4, (q15_t)0xfaba, + (q15_t)0x7fe3, (q15_t)0xfab4, (q15_t)0x7fe3, (q15_t)0xfaad, (q15_t)0x7fe3, (q15_t)0xfaa7, (q15_t)0x7fe3, (q15_t)0xfaa1, + (q15_t)0x7fe2, (q15_t)0xfa9b, (q15_t)0x7fe2, (q15_t)0xfa94, (q15_t)0x7fe2, (q15_t)0xfa8e, (q15_t)0x7fe2, (q15_t)0xfa88, + (q15_t)0x7fe1, (q15_t)0xfa81, (q15_t)0x7fe1, (q15_t)0xfa7b, (q15_t)0x7fe1, (q15_t)0xfa75, (q15_t)0x7fe0, (q15_t)0xfa6f, + (q15_t)0x7fe0, (q15_t)0xfa68, (q15_t)0x7fe0, (q15_t)0xfa62, (q15_t)0x7fe0, (q15_t)0xfa5c, (q15_t)0x7fdf, (q15_t)0xfa56, + (q15_t)0x7fdf, (q15_t)0xfa4f, (q15_t)0x7fdf, (q15_t)0xfa49, (q15_t)0x7fdf, (q15_t)0xfa43, (q15_t)0x7fde, (q15_t)0xfa3c, + (q15_t)0x7fde, (q15_t)0xfa36, (q15_t)0x7fde, (q15_t)0xfa30, (q15_t)0x7fdd, (q15_t)0xfa2a, (q15_t)0x7fdd, (q15_t)0xfa23, + (q15_t)0x7fdd, (q15_t)0xfa1d, (q15_t)0x7fdd, (q15_t)0xfa17, (q15_t)0x7fdc, (q15_t)0xfa11, (q15_t)0x7fdc, (q15_t)0xfa0a, + (q15_t)0x7fdc, (q15_t)0xfa04, (q15_t)0x7fdb, (q15_t)0xf9fe, (q15_t)0x7fdb, (q15_t)0xf9f7, (q15_t)0x7fdb, (q15_t)0xf9f1, + (q15_t)0x7fda, (q15_t)0xf9eb, (q15_t)0x7fda, (q15_t)0xf9e5, (q15_t)0x7fda, (q15_t)0xf9de, (q15_t)0x7fda, (q15_t)0xf9d8, + (q15_t)0x7fd9, (q15_t)0xf9d2, (q15_t)0x7fd9, (q15_t)0xf9cb, (q15_t)0x7fd9, (q15_t)0xf9c5, (q15_t)0x7fd8, (q15_t)0xf9bf, + (q15_t)0x7fd8, (q15_t)0xf9b9, (q15_t)0x7fd8, (q15_t)0xf9b2, (q15_t)0x7fd7, (q15_t)0xf9ac, (q15_t)0x7fd7, (q15_t)0xf9a6, + (q15_t)0x7fd7, (q15_t)0xf9a0, (q15_t)0x7fd6, (q15_t)0xf999, (q15_t)0x7fd6, (q15_t)0xf993, (q15_t)0x7fd6, (q15_t)0xf98d, + (q15_t)0x7fd6, (q15_t)0xf986, (q15_t)0x7fd5, (q15_t)0xf980, (q15_t)0x7fd5, (q15_t)0xf97a, (q15_t)0x7fd5, (q15_t)0xf974, + (q15_t)0x7fd4, (q15_t)0xf96d, (q15_t)0x7fd4, (q15_t)0xf967, (q15_t)0x7fd4, (q15_t)0xf961, (q15_t)0x7fd3, (q15_t)0xf95b, + (q15_t)0x7fd3, (q15_t)0xf954, (q15_t)0x7fd3, (q15_t)0xf94e, (q15_t)0x7fd2, (q15_t)0xf948, (q15_t)0x7fd2, (q15_t)0xf941, + (q15_t)0x7fd2, (q15_t)0xf93b, (q15_t)0x7fd1, (q15_t)0xf935, (q15_t)0x7fd1, (q15_t)0xf92f, (q15_t)0x7fd1, (q15_t)0xf928, + (q15_t)0x7fd0, (q15_t)0xf922, (q15_t)0x7fd0, (q15_t)0xf91c, (q15_t)0x7fd0, (q15_t)0xf916, (q15_t)0x7fcf, (q15_t)0xf90f, + (q15_t)0x7fcf, (q15_t)0xf909, (q15_t)0x7fcf, (q15_t)0xf903, (q15_t)0x7fce, (q15_t)0xf8fc, (q15_t)0x7fce, (q15_t)0xf8f6, + (q15_t)0x7fce, (q15_t)0xf8f0, (q15_t)0x7fcd, (q15_t)0xf8ea, (q15_t)0x7fcd, (q15_t)0xf8e3, (q15_t)0x7fcd, (q15_t)0xf8dd, + (q15_t)0x7fcc, (q15_t)0xf8d7, (q15_t)0x7fcc, (q15_t)0xf8d0, (q15_t)0x7fcb, (q15_t)0xf8ca, (q15_t)0x7fcb, (q15_t)0xf8c4, + (q15_t)0x7fcb, (q15_t)0xf8be, (q15_t)0x7fca, (q15_t)0xf8b7, (q15_t)0x7fca, (q15_t)0xf8b1, (q15_t)0x7fca, (q15_t)0xf8ab, + (q15_t)0x7fc9, (q15_t)0xf8a5, (q15_t)0x7fc9, (q15_t)0xf89e, (q15_t)0x7fc9, (q15_t)0xf898, (q15_t)0x7fc8, (q15_t)0xf892, + (q15_t)0x7fc8, (q15_t)0xf88b, (q15_t)0x7fc7, (q15_t)0xf885, (q15_t)0x7fc7, (q15_t)0xf87f, (q15_t)0x7fc7, (q15_t)0xf879, + (q15_t)0x7fc6, (q15_t)0xf872, (q15_t)0x7fc6, (q15_t)0xf86c, (q15_t)0x7fc6, (q15_t)0xf866, (q15_t)0x7fc5, (q15_t)0xf860, + (q15_t)0x7fc5, (q15_t)0xf859, (q15_t)0x7fc5, (q15_t)0xf853, (q15_t)0x7fc4, (q15_t)0xf84d, (q15_t)0x7fc4, (q15_t)0xf846, + (q15_t)0x7fc3, (q15_t)0xf840, (q15_t)0x7fc3, (q15_t)0xf83a, (q15_t)0x7fc3, (q15_t)0xf834, (q15_t)0x7fc2, (q15_t)0xf82d, + (q15_t)0x7fc2, (q15_t)0xf827, (q15_t)0x7fc1, (q15_t)0xf821, (q15_t)0x7fc1, (q15_t)0xf81b, (q15_t)0x7fc1, (q15_t)0xf814, + (q15_t)0x7fc0, (q15_t)0xf80e, (q15_t)0x7fc0, (q15_t)0xf808, (q15_t)0x7fc0, (q15_t)0xf802, (q15_t)0x7fbf, (q15_t)0xf7fb, + (q15_t)0x7fbf, (q15_t)0xf7f5, (q15_t)0x7fbe, (q15_t)0xf7ef, (q15_t)0x7fbe, (q15_t)0xf7e8, (q15_t)0x7fbe, (q15_t)0xf7e2, + (q15_t)0x7fbd, (q15_t)0xf7dc, (q15_t)0x7fbd, (q15_t)0xf7d6, (q15_t)0x7fbc, (q15_t)0xf7cf, (q15_t)0x7fbc, (q15_t)0xf7c9, + (q15_t)0x7fbc, (q15_t)0xf7c3, (q15_t)0x7fbb, (q15_t)0xf7bd, (q15_t)0x7fbb, (q15_t)0xf7b6, (q15_t)0x7fba, (q15_t)0xf7b0, + (q15_t)0x7fba, (q15_t)0xf7aa, (q15_t)0x7fb9, (q15_t)0xf7a3, (q15_t)0x7fb9, (q15_t)0xf79d, (q15_t)0x7fb9, (q15_t)0xf797, + (q15_t)0x7fb8, (q15_t)0xf791, (q15_t)0x7fb8, (q15_t)0xf78a, (q15_t)0x7fb7, (q15_t)0xf784, (q15_t)0x7fb7, (q15_t)0xf77e, + (q15_t)0x7fb7, (q15_t)0xf778, (q15_t)0x7fb6, (q15_t)0xf771, (q15_t)0x7fb6, (q15_t)0xf76b, (q15_t)0x7fb5, (q15_t)0xf765, + (q15_t)0x7fb5, (q15_t)0xf75e, (q15_t)0x7fb4, (q15_t)0xf758, (q15_t)0x7fb4, (q15_t)0xf752, (q15_t)0x7fb4, (q15_t)0xf74c, + (q15_t)0x7fb3, (q15_t)0xf745, (q15_t)0x7fb3, (q15_t)0xf73f, (q15_t)0x7fb2, (q15_t)0xf739, (q15_t)0x7fb2, (q15_t)0xf733, + (q15_t)0x7fb1, (q15_t)0xf72c, (q15_t)0x7fb1, (q15_t)0xf726, (q15_t)0x7fb1, (q15_t)0xf720, (q15_t)0x7fb0, (q15_t)0xf71a, + (q15_t)0x7fb0, (q15_t)0xf713, (q15_t)0x7faf, (q15_t)0xf70d, (q15_t)0x7faf, (q15_t)0xf707, (q15_t)0x7fae, (q15_t)0xf700, + (q15_t)0x7fae, (q15_t)0xf6fa, (q15_t)0x7fae, (q15_t)0xf6f4, (q15_t)0x7fad, (q15_t)0xf6ee, (q15_t)0x7fad, (q15_t)0xf6e7, + (q15_t)0x7fac, (q15_t)0xf6e1, (q15_t)0x7fac, (q15_t)0xf6db, (q15_t)0x7fab, (q15_t)0xf6d5, (q15_t)0x7fab, (q15_t)0xf6ce, + (q15_t)0x7faa, (q15_t)0xf6c8, (q15_t)0x7faa, (q15_t)0xf6c2, (q15_t)0x7fa9, (q15_t)0xf6bc, (q15_t)0x7fa9, (q15_t)0xf6b5, + (q15_t)0x7fa9, (q15_t)0xf6af, (q15_t)0x7fa8, (q15_t)0xf6a9, (q15_t)0x7fa8, (q15_t)0xf6a2, (q15_t)0x7fa7, (q15_t)0xf69c, + (q15_t)0x7fa7, (q15_t)0xf696, (q15_t)0x7fa6, (q15_t)0xf690, (q15_t)0x7fa6, (q15_t)0xf689, (q15_t)0x7fa5, (q15_t)0xf683, + (q15_t)0x7fa5, (q15_t)0xf67d, (q15_t)0x7fa4, (q15_t)0xf677, (q15_t)0x7fa4, (q15_t)0xf670, (q15_t)0x7fa3, (q15_t)0xf66a, + (q15_t)0x7fa3, (q15_t)0xf664, (q15_t)0x7fa3, (q15_t)0xf65e, (q15_t)0x7fa2, (q15_t)0xf657, (q15_t)0x7fa2, (q15_t)0xf651, + (q15_t)0x7fa1, (q15_t)0xf64b, (q15_t)0x7fa1, (q15_t)0xf644, (q15_t)0x7fa0, (q15_t)0xf63e, (q15_t)0x7fa0, (q15_t)0xf638, + (q15_t)0x7f9f, (q15_t)0xf632, (q15_t)0x7f9f, (q15_t)0xf62b, (q15_t)0x7f9e, (q15_t)0xf625, (q15_t)0x7f9e, (q15_t)0xf61f, + (q15_t)0x7f9d, (q15_t)0xf619, (q15_t)0x7f9d, (q15_t)0xf612, (q15_t)0x7f9c, (q15_t)0xf60c, (q15_t)0x7f9c, (q15_t)0xf606, + (q15_t)0x7f9b, (q15_t)0xf600, (q15_t)0x7f9b, (q15_t)0xf5f9, (q15_t)0x7f9a, (q15_t)0xf5f3, (q15_t)0x7f9a, (q15_t)0xf5ed, + (q15_t)0x7f99, (q15_t)0xf5e7, (q15_t)0x7f99, (q15_t)0xf5e0, (q15_t)0x7f98, (q15_t)0xf5da, (q15_t)0x7f98, (q15_t)0xf5d4, + (q15_t)0x7f97, (q15_t)0xf5cd, (q15_t)0x7f97, (q15_t)0xf5c7, (q15_t)0x7f96, (q15_t)0xf5c1, (q15_t)0x7f96, (q15_t)0xf5bb, + (q15_t)0x7f95, (q15_t)0xf5b4, (q15_t)0x7f95, (q15_t)0xf5ae, (q15_t)0x7f94, (q15_t)0xf5a8, (q15_t)0x7f94, (q15_t)0xf5a2, + (q15_t)0x7f93, (q15_t)0xf59b, (q15_t)0x7f93, (q15_t)0xf595, (q15_t)0x7f92, (q15_t)0xf58f, (q15_t)0x7f92, (q15_t)0xf589, + (q15_t)0x7f91, (q15_t)0xf582, (q15_t)0x7f91, (q15_t)0xf57c, (q15_t)0x7f90, (q15_t)0xf576, (q15_t)0x7f90, (q15_t)0xf570, + (q15_t)0x7f8f, (q15_t)0xf569, (q15_t)0x7f8f, (q15_t)0xf563, (q15_t)0x7f8e, (q15_t)0xf55d, (q15_t)0x7f8e, (q15_t)0xf556, + (q15_t)0x7f8d, (q15_t)0xf550, (q15_t)0x7f8d, (q15_t)0xf54a, (q15_t)0x7f8c, (q15_t)0xf544, (q15_t)0x7f8b, (q15_t)0xf53d, + (q15_t)0x7f8b, (q15_t)0xf537, (q15_t)0x7f8a, (q15_t)0xf531, (q15_t)0x7f8a, (q15_t)0xf52b, (q15_t)0x7f89, (q15_t)0xf524, + (q15_t)0x7f89, (q15_t)0xf51e, (q15_t)0x7f88, (q15_t)0xf518, (q15_t)0x7f88, (q15_t)0xf512, (q15_t)0x7f87, (q15_t)0xf50b, + (q15_t)0x7f87, (q15_t)0xf505, (q15_t)0x7f86, (q15_t)0xf4ff, (q15_t)0x7f86, (q15_t)0xf4f9, (q15_t)0x7f85, (q15_t)0xf4f2, + (q15_t)0x7f85, (q15_t)0xf4ec, (q15_t)0x7f84, (q15_t)0xf4e6, (q15_t)0x7f83, (q15_t)0xf4e0, (q15_t)0x7f83, (q15_t)0xf4d9, + (q15_t)0x7f82, (q15_t)0xf4d3, (q15_t)0x7f82, (q15_t)0xf4cd, (q15_t)0x7f81, (q15_t)0xf4c6, (q15_t)0x7f81, (q15_t)0xf4c0, + (q15_t)0x7f80, (q15_t)0xf4ba, (q15_t)0x7f80, (q15_t)0xf4b4, (q15_t)0x7f7f, (q15_t)0xf4ad, (q15_t)0x7f7e, (q15_t)0xf4a7, + (q15_t)0x7f7e, (q15_t)0xf4a1, (q15_t)0x7f7d, (q15_t)0xf49b, (q15_t)0x7f7d, (q15_t)0xf494, (q15_t)0x7f7c, (q15_t)0xf48e, + (q15_t)0x7f7c, (q15_t)0xf488, (q15_t)0x7f7b, (q15_t)0xf482, (q15_t)0x7f7b, (q15_t)0xf47b, (q15_t)0x7f7a, (q15_t)0xf475, + (q15_t)0x7f79, (q15_t)0xf46f, (q15_t)0x7f79, (q15_t)0xf469, (q15_t)0x7f78, (q15_t)0xf462, (q15_t)0x7f78, (q15_t)0xf45c, + (q15_t)0x7f77, (q15_t)0xf456, (q15_t)0x7f77, (q15_t)0xf450, (q15_t)0x7f76, (q15_t)0xf449, (q15_t)0x7f75, (q15_t)0xf443, + (q15_t)0x7f75, (q15_t)0xf43d, (q15_t)0x7f74, (q15_t)0xf437, (q15_t)0x7f74, (q15_t)0xf430, (q15_t)0x7f73, (q15_t)0xf42a, + (q15_t)0x7f72, (q15_t)0xf424, (q15_t)0x7f72, (q15_t)0xf41e, (q15_t)0x7f71, (q15_t)0xf417, (q15_t)0x7f71, (q15_t)0xf411, + (q15_t)0x7f70, (q15_t)0xf40b, (q15_t)0x7f70, (q15_t)0xf405, (q15_t)0x7f6f, (q15_t)0xf3fe, (q15_t)0x7f6e, (q15_t)0xf3f8, + (q15_t)0x7f6e, (q15_t)0xf3f2, (q15_t)0x7f6d, (q15_t)0xf3ec, (q15_t)0x7f6d, (q15_t)0xf3e5, (q15_t)0x7f6c, (q15_t)0xf3df, + (q15_t)0x7f6b, (q15_t)0xf3d9, (q15_t)0x7f6b, (q15_t)0xf3d2, (q15_t)0x7f6a, (q15_t)0xf3cc, (q15_t)0x7f6a, (q15_t)0xf3c6, + (q15_t)0x7f69, (q15_t)0xf3c0, (q15_t)0x7f68, (q15_t)0xf3b9, (q15_t)0x7f68, (q15_t)0xf3b3, (q15_t)0x7f67, (q15_t)0xf3ad, + (q15_t)0x7f67, (q15_t)0xf3a7, (q15_t)0x7f66, (q15_t)0xf3a0, (q15_t)0x7f65, (q15_t)0xf39a, (q15_t)0x7f65, (q15_t)0xf394, + (q15_t)0x7f64, (q15_t)0xf38e, (q15_t)0x7f64, (q15_t)0xf387, (q15_t)0x7f63, (q15_t)0xf381, (q15_t)0x7f62, (q15_t)0xf37b, + (q15_t)0x7f62, (q15_t)0xf375, (q15_t)0x7f61, (q15_t)0xf36e, (q15_t)0x7f60, (q15_t)0xf368, (q15_t)0x7f60, (q15_t)0xf362, + (q15_t)0x7f5f, (q15_t)0xf35c, (q15_t)0x7f5f, (q15_t)0xf355, (q15_t)0x7f5e, (q15_t)0xf34f, (q15_t)0x7f5d, (q15_t)0xf349, + (q15_t)0x7f5d, (q15_t)0xf343, (q15_t)0x7f5c, (q15_t)0xf33c, (q15_t)0x7f5b, (q15_t)0xf336, (q15_t)0x7f5b, (q15_t)0xf330, + (q15_t)0x7f5a, (q15_t)0xf32a, (q15_t)0x7f5a, (q15_t)0xf323, (q15_t)0x7f59, (q15_t)0xf31d, (q15_t)0x7f58, (q15_t)0xf317, + (q15_t)0x7f58, (q15_t)0xf311, (q15_t)0x7f57, (q15_t)0xf30a, (q15_t)0x7f56, (q15_t)0xf304, (q15_t)0x7f56, (q15_t)0xf2fe, + (q15_t)0x7f55, (q15_t)0xf2f8, (q15_t)0x7f55, (q15_t)0xf2f1, (q15_t)0x7f54, (q15_t)0xf2eb, (q15_t)0x7f53, (q15_t)0xf2e5, + (q15_t)0x7f53, (q15_t)0xf2df, (q15_t)0x7f52, (q15_t)0xf2d8, (q15_t)0x7f51, (q15_t)0xf2d2, (q15_t)0x7f51, (q15_t)0xf2cc, + (q15_t)0x7f50, (q15_t)0xf2c6, (q15_t)0x7f4f, (q15_t)0xf2bf, (q15_t)0x7f4f, (q15_t)0xf2b9, (q15_t)0x7f4e, (q15_t)0xf2b3, + (q15_t)0x7f4d, (q15_t)0xf2ad, (q15_t)0x7f4d, (q15_t)0xf2a6, (q15_t)0x7f4c, (q15_t)0xf2a0, (q15_t)0x7f4b, (q15_t)0xf29a, + (q15_t)0x7f4b, (q15_t)0xf294, (q15_t)0x7f4a, (q15_t)0xf28d, (q15_t)0x7f49, (q15_t)0xf287, (q15_t)0x7f49, (q15_t)0xf281, + (q15_t)0x7f48, (q15_t)0xf27b, (q15_t)0x7f47, (q15_t)0xf274, (q15_t)0x7f47, (q15_t)0xf26e, (q15_t)0x7f46, (q15_t)0xf268, + (q15_t)0x7f45, (q15_t)0xf262, (q15_t)0x7f45, (q15_t)0xf25b, (q15_t)0x7f44, (q15_t)0xf255, (q15_t)0x7f43, (q15_t)0xf24f, + (q15_t)0x7f43, (q15_t)0xf249, (q15_t)0x7f42, (q15_t)0xf242, (q15_t)0x7f41, (q15_t)0xf23c, (q15_t)0x7f41, (q15_t)0xf236, + (q15_t)0x7f40, (q15_t)0xf230, (q15_t)0x7f3f, (q15_t)0xf229, (q15_t)0x7f3f, (q15_t)0xf223, (q15_t)0x7f3e, (q15_t)0xf21d, + (q15_t)0x7f3d, (q15_t)0xf217, (q15_t)0x7f3d, (q15_t)0xf210, (q15_t)0x7f3c, (q15_t)0xf20a, (q15_t)0x7f3b, (q15_t)0xf204, + (q15_t)0x7f3b, (q15_t)0xf1fe, (q15_t)0x7f3a, (q15_t)0xf1f7, (q15_t)0x7f39, (q15_t)0xf1f1, (q15_t)0x7f39, (q15_t)0xf1eb, + (q15_t)0x7f38, (q15_t)0xf1e5, (q15_t)0x7f37, (q15_t)0xf1de, (q15_t)0x7f36, (q15_t)0xf1d8, (q15_t)0x7f36, (q15_t)0xf1d2, + (q15_t)0x7f35, (q15_t)0xf1cc, (q15_t)0x7f34, (q15_t)0xf1c6, (q15_t)0x7f34, (q15_t)0xf1bf, (q15_t)0x7f33, (q15_t)0xf1b9, + (q15_t)0x7f32, (q15_t)0xf1b3, (q15_t)0x7f32, (q15_t)0xf1ad, (q15_t)0x7f31, (q15_t)0xf1a6, (q15_t)0x7f30, (q15_t)0xf1a0, + (q15_t)0x7f2f, (q15_t)0xf19a, (q15_t)0x7f2f, (q15_t)0xf194, (q15_t)0x7f2e, (q15_t)0xf18d, (q15_t)0x7f2d, (q15_t)0xf187, + (q15_t)0x7f2d, (q15_t)0xf181, (q15_t)0x7f2c, (q15_t)0xf17b, (q15_t)0x7f2b, (q15_t)0xf174, (q15_t)0x7f2a, (q15_t)0xf16e, + (q15_t)0x7f2a, (q15_t)0xf168, (q15_t)0x7f29, (q15_t)0xf162, (q15_t)0x7f28, (q15_t)0xf15b, (q15_t)0x7f28, (q15_t)0xf155, + (q15_t)0x7f27, (q15_t)0xf14f, (q15_t)0x7f26, (q15_t)0xf149, (q15_t)0x7f25, (q15_t)0xf142, (q15_t)0x7f25, (q15_t)0xf13c, + (q15_t)0x7f24, (q15_t)0xf136, (q15_t)0x7f23, (q15_t)0xf130, (q15_t)0x7f23, (q15_t)0xf129, (q15_t)0x7f22, (q15_t)0xf123, + (q15_t)0x7f21, (q15_t)0xf11d, (q15_t)0x7f20, (q15_t)0xf117, (q15_t)0x7f20, (q15_t)0xf110, (q15_t)0x7f1f, (q15_t)0xf10a, + (q15_t)0x7f1e, (q15_t)0xf104, (q15_t)0x7f1d, (q15_t)0xf0fe, (q15_t)0x7f1d, (q15_t)0xf0f8, (q15_t)0x7f1c, (q15_t)0xf0f1, + (q15_t)0x7f1b, (q15_t)0xf0eb, (q15_t)0x7f1a, (q15_t)0xf0e5, (q15_t)0x7f1a, (q15_t)0xf0df, (q15_t)0x7f19, (q15_t)0xf0d8, + (q15_t)0x7f18, (q15_t)0xf0d2, (q15_t)0x7f17, (q15_t)0xf0cc, (q15_t)0x7f17, (q15_t)0xf0c6, (q15_t)0x7f16, (q15_t)0xf0bf, + (q15_t)0x7f15, (q15_t)0xf0b9, (q15_t)0x7f14, (q15_t)0xf0b3, (q15_t)0x7f14, (q15_t)0xf0ad, (q15_t)0x7f13, (q15_t)0xf0a6, + (q15_t)0x7f12, (q15_t)0xf0a0, (q15_t)0x7f11, (q15_t)0xf09a, (q15_t)0x7f11, (q15_t)0xf094, (q15_t)0x7f10, (q15_t)0xf08d, + (q15_t)0x7f0f, (q15_t)0xf087, (q15_t)0x7f0e, (q15_t)0xf081, (q15_t)0x7f0e, (q15_t)0xf07b, (q15_t)0x7f0d, (q15_t)0xf075, + (q15_t)0x7f0c, (q15_t)0xf06e, (q15_t)0x7f0b, (q15_t)0xf068, (q15_t)0x7f0b, (q15_t)0xf062, (q15_t)0x7f0a, (q15_t)0xf05c, + (q15_t)0x7f09, (q15_t)0xf055, (q15_t)0x7f08, (q15_t)0xf04f, (q15_t)0x7f08, (q15_t)0xf049, (q15_t)0x7f07, (q15_t)0xf043, + (q15_t)0x7f06, (q15_t)0xf03c, (q15_t)0x7f05, (q15_t)0xf036, (q15_t)0x7f04, (q15_t)0xf030, (q15_t)0x7f04, (q15_t)0xf02a, + (q15_t)0x7f03, (q15_t)0xf023, (q15_t)0x7f02, (q15_t)0xf01d, (q15_t)0x7f01, (q15_t)0xf017, (q15_t)0x7f01, (q15_t)0xf011, + (q15_t)0x7f00, (q15_t)0xf00b, (q15_t)0x7eff, (q15_t)0xf004, (q15_t)0x7efe, (q15_t)0xeffe, (q15_t)0x7efd, (q15_t)0xeff8, + (q15_t)0x7efd, (q15_t)0xeff2, (q15_t)0x7efc, (q15_t)0xefeb, (q15_t)0x7efb, (q15_t)0xefe5, (q15_t)0x7efa, (q15_t)0xefdf, + (q15_t)0x7ef9, (q15_t)0xefd9, (q15_t)0x7ef9, (q15_t)0xefd2, (q15_t)0x7ef8, (q15_t)0xefcc, (q15_t)0x7ef7, (q15_t)0xefc6, + (q15_t)0x7ef6, (q15_t)0xefc0, (q15_t)0x7ef5, (q15_t)0xefb9, (q15_t)0x7ef5, (q15_t)0xefb3, (q15_t)0x7ef4, (q15_t)0xefad, + (q15_t)0x7ef3, (q15_t)0xefa7, (q15_t)0x7ef2, (q15_t)0xefa1, (q15_t)0x7ef1, (q15_t)0xef9a, (q15_t)0x7ef1, (q15_t)0xef94, + (q15_t)0x7ef0, (q15_t)0xef8e, (q15_t)0x7eef, (q15_t)0xef88, (q15_t)0x7eee, (q15_t)0xef81, (q15_t)0x7eed, (q15_t)0xef7b, + (q15_t)0x7eed, (q15_t)0xef75, (q15_t)0x7eec, (q15_t)0xef6f, (q15_t)0x7eeb, (q15_t)0xef68, (q15_t)0x7eea, (q15_t)0xef62, + (q15_t)0x7ee9, (q15_t)0xef5c, (q15_t)0x7ee9, (q15_t)0xef56, (q15_t)0x7ee8, (q15_t)0xef50, (q15_t)0x7ee7, (q15_t)0xef49, + (q15_t)0x7ee6, (q15_t)0xef43, (q15_t)0x7ee5, (q15_t)0xef3d, (q15_t)0x7ee4, (q15_t)0xef37, (q15_t)0x7ee4, (q15_t)0xef30, + (q15_t)0x7ee3, (q15_t)0xef2a, (q15_t)0x7ee2, (q15_t)0xef24, (q15_t)0x7ee1, (q15_t)0xef1e, (q15_t)0x7ee0, (q15_t)0xef18, + (q15_t)0x7edf, (q15_t)0xef11, (q15_t)0x7edf, (q15_t)0xef0b, (q15_t)0x7ede, (q15_t)0xef05, (q15_t)0x7edd, (q15_t)0xeeff, + (q15_t)0x7edc, (q15_t)0xeef8, (q15_t)0x7edb, (q15_t)0xeef2, (q15_t)0x7eda, (q15_t)0xeeec, (q15_t)0x7eda, (q15_t)0xeee6, + (q15_t)0x7ed9, (q15_t)0xeedf, (q15_t)0x7ed8, (q15_t)0xeed9, (q15_t)0x7ed7, (q15_t)0xeed3, (q15_t)0x7ed6, (q15_t)0xeecd, + (q15_t)0x7ed5, (q15_t)0xeec7, (q15_t)0x7ed5, (q15_t)0xeec0, (q15_t)0x7ed4, (q15_t)0xeeba, (q15_t)0x7ed3, (q15_t)0xeeb4, + (q15_t)0x7ed2, (q15_t)0xeeae, (q15_t)0x7ed1, (q15_t)0xeea7, (q15_t)0x7ed0, (q15_t)0xeea1, (q15_t)0x7ecf, (q15_t)0xee9b, + (q15_t)0x7ecf, (q15_t)0xee95, (q15_t)0x7ece, (q15_t)0xee8f, (q15_t)0x7ecd, (q15_t)0xee88, (q15_t)0x7ecc, (q15_t)0xee82, + (q15_t)0x7ecb, (q15_t)0xee7c, (q15_t)0x7eca, (q15_t)0xee76, (q15_t)0x7ec9, (q15_t)0xee6f, (q15_t)0x7ec9, (q15_t)0xee69, + (q15_t)0x7ec8, (q15_t)0xee63, (q15_t)0x7ec7, (q15_t)0xee5d, (q15_t)0x7ec6, (q15_t)0xee57, (q15_t)0x7ec5, (q15_t)0xee50, + (q15_t)0x7ec4, (q15_t)0xee4a, (q15_t)0x7ec3, (q15_t)0xee44, (q15_t)0x7ec3, (q15_t)0xee3e, (q15_t)0x7ec2, (q15_t)0xee37, + (q15_t)0x7ec1, (q15_t)0xee31, (q15_t)0x7ec0, (q15_t)0xee2b, (q15_t)0x7ebf, (q15_t)0xee25, (q15_t)0x7ebe, (q15_t)0xee1f, + (q15_t)0x7ebd, (q15_t)0xee18, (q15_t)0x7ebc, (q15_t)0xee12, (q15_t)0x7ebb, (q15_t)0xee0c, (q15_t)0x7ebb, (q15_t)0xee06, + (q15_t)0x7eba, (q15_t)0xedff, (q15_t)0x7eb9, (q15_t)0xedf9, (q15_t)0x7eb8, (q15_t)0xedf3, (q15_t)0x7eb7, (q15_t)0xeded, + (q15_t)0x7eb6, (q15_t)0xede7, (q15_t)0x7eb5, (q15_t)0xede0, (q15_t)0x7eb4, (q15_t)0xedda, (q15_t)0x7eb4, (q15_t)0xedd4, + (q15_t)0x7eb3, (q15_t)0xedce, (q15_t)0x7eb2, (q15_t)0xedc7, (q15_t)0x7eb1, (q15_t)0xedc1, (q15_t)0x7eb0, (q15_t)0xedbb, + (q15_t)0x7eaf, (q15_t)0xedb5, (q15_t)0x7eae, (q15_t)0xedaf, (q15_t)0x7ead, (q15_t)0xeda8, (q15_t)0x7eac, (q15_t)0xeda2, + (q15_t)0x7eab, (q15_t)0xed9c, (q15_t)0x7eab, (q15_t)0xed96, (q15_t)0x7eaa, (q15_t)0xed8f, (q15_t)0x7ea9, (q15_t)0xed89, + (q15_t)0x7ea8, (q15_t)0xed83, (q15_t)0x7ea7, (q15_t)0xed7d, (q15_t)0x7ea6, (q15_t)0xed77, (q15_t)0x7ea5, (q15_t)0xed70, + (q15_t)0x7ea4, (q15_t)0xed6a, (q15_t)0x7ea3, (q15_t)0xed64, (q15_t)0x7ea2, (q15_t)0xed5e, (q15_t)0x7ea1, (q15_t)0xed58, + (q15_t)0x7ea1, (q15_t)0xed51, (q15_t)0x7ea0, (q15_t)0xed4b, (q15_t)0x7e9f, (q15_t)0xed45, (q15_t)0x7e9e, (q15_t)0xed3f, + (q15_t)0x7e9d, (q15_t)0xed38, (q15_t)0x7e9c, (q15_t)0xed32, (q15_t)0x7e9b, (q15_t)0xed2c, (q15_t)0x7e9a, (q15_t)0xed26, + (q15_t)0x7e99, (q15_t)0xed20, (q15_t)0x7e98, (q15_t)0xed19, (q15_t)0x7e97, (q15_t)0xed13, (q15_t)0x7e96, (q15_t)0xed0d, + (q15_t)0x7e95, (q15_t)0xed07, (q15_t)0x7e94, (q15_t)0xed01, (q15_t)0x7e94, (q15_t)0xecfa, (q15_t)0x7e93, (q15_t)0xecf4, + (q15_t)0x7e92, (q15_t)0xecee, (q15_t)0x7e91, (q15_t)0xece8, (q15_t)0x7e90, (q15_t)0xece1, (q15_t)0x7e8f, (q15_t)0xecdb, + (q15_t)0x7e8e, (q15_t)0xecd5, (q15_t)0x7e8d, (q15_t)0xeccf, (q15_t)0x7e8c, (q15_t)0xecc9, (q15_t)0x7e8b, (q15_t)0xecc2, + (q15_t)0x7e8a, (q15_t)0xecbc, (q15_t)0x7e89, (q15_t)0xecb6, (q15_t)0x7e88, (q15_t)0xecb0, (q15_t)0x7e87, (q15_t)0xecaa, + (q15_t)0x7e86, (q15_t)0xeca3, (q15_t)0x7e85, (q15_t)0xec9d, (q15_t)0x7e84, (q15_t)0xec97, (q15_t)0x7e84, (q15_t)0xec91, + (q15_t)0x7e83, (q15_t)0xec8a, (q15_t)0x7e82, (q15_t)0xec84, (q15_t)0x7e81, (q15_t)0xec7e, (q15_t)0x7e80, (q15_t)0xec78, + (q15_t)0x7e7f, (q15_t)0xec72, (q15_t)0x7e7e, (q15_t)0xec6b, (q15_t)0x7e7d, (q15_t)0xec65, (q15_t)0x7e7c, (q15_t)0xec5f, + (q15_t)0x7e7b, (q15_t)0xec59, (q15_t)0x7e7a, (q15_t)0xec53, (q15_t)0x7e79, (q15_t)0xec4c, (q15_t)0x7e78, (q15_t)0xec46, + (q15_t)0x7e77, (q15_t)0xec40, (q15_t)0x7e76, (q15_t)0xec3a, (q15_t)0x7e75, (q15_t)0xec34, (q15_t)0x7e74, (q15_t)0xec2d, + (q15_t)0x7e73, (q15_t)0xec27, (q15_t)0x7e72, (q15_t)0xec21, (q15_t)0x7e71, (q15_t)0xec1b, (q15_t)0x7e70, (q15_t)0xec15, + (q15_t)0x7e6f, (q15_t)0xec0e, (q15_t)0x7e6e, (q15_t)0xec08, (q15_t)0x7e6d, (q15_t)0xec02, (q15_t)0x7e6c, (q15_t)0xebfc, + (q15_t)0x7e6b, (q15_t)0xebf5, (q15_t)0x7e6a, (q15_t)0xebef, (q15_t)0x7e69, (q15_t)0xebe9, (q15_t)0x7e68, (q15_t)0xebe3, + (q15_t)0x7e67, (q15_t)0xebdd, (q15_t)0x7e66, (q15_t)0xebd6, (q15_t)0x7e65, (q15_t)0xebd0, (q15_t)0x7e64, (q15_t)0xebca, + (q15_t)0x7e63, (q15_t)0xebc4, (q15_t)0x7e62, (q15_t)0xebbe, (q15_t)0x7e61, (q15_t)0xebb7, (q15_t)0x7e60, (q15_t)0xebb1, + (q15_t)0x7e5f, (q15_t)0xebab, (q15_t)0x7e5e, (q15_t)0xeba5, (q15_t)0x7e5d, (q15_t)0xeb9f, (q15_t)0x7e5c, (q15_t)0xeb98, + (q15_t)0x7e5b, (q15_t)0xeb92, (q15_t)0x7e5a, (q15_t)0xeb8c, (q15_t)0x7e59, (q15_t)0xeb86, (q15_t)0x7e58, (q15_t)0xeb80, + (q15_t)0x7e57, (q15_t)0xeb79, (q15_t)0x7e56, (q15_t)0xeb73, (q15_t)0x7e55, (q15_t)0xeb6d, (q15_t)0x7e54, (q15_t)0xeb67, + (q15_t)0x7e53, (q15_t)0xeb61, (q15_t)0x7e52, (q15_t)0xeb5a, (q15_t)0x7e51, (q15_t)0xeb54, (q15_t)0x7e50, (q15_t)0xeb4e, + (q15_t)0x7e4f, (q15_t)0xeb48, (q15_t)0x7e4e, (q15_t)0xeb42, (q15_t)0x7e4d, (q15_t)0xeb3b, (q15_t)0x7e4c, (q15_t)0xeb35, + (q15_t)0x7e4b, (q15_t)0xeb2f, (q15_t)0x7e4a, (q15_t)0xeb29, (q15_t)0x7e49, (q15_t)0xeb23, (q15_t)0x7e48, (q15_t)0xeb1c, + (q15_t)0x7e47, (q15_t)0xeb16, (q15_t)0x7e46, (q15_t)0xeb10, (q15_t)0x7e45, (q15_t)0xeb0a, (q15_t)0x7e44, (q15_t)0xeb04, + (q15_t)0x7e43, (q15_t)0xeafd, (q15_t)0x7e42, (q15_t)0xeaf7, (q15_t)0x7e41, (q15_t)0xeaf1, (q15_t)0x7e40, (q15_t)0xeaeb, + (q15_t)0x7e3f, (q15_t)0xeae5, (q15_t)0x7e3e, (q15_t)0xeade, (q15_t)0x7e3d, (q15_t)0xead8, (q15_t)0x7e3c, (q15_t)0xead2, + (q15_t)0x7e3b, (q15_t)0xeacc, (q15_t)0x7e3a, (q15_t)0xeac6, (q15_t)0x7e39, (q15_t)0xeabf, (q15_t)0x7e38, (q15_t)0xeab9, + (q15_t)0x7e37, (q15_t)0xeab3, (q15_t)0x7e35, (q15_t)0xeaad, (q15_t)0x7e34, (q15_t)0xeaa7, (q15_t)0x7e33, (q15_t)0xeaa0, + (q15_t)0x7e32, (q15_t)0xea9a, (q15_t)0x7e31, (q15_t)0xea94, (q15_t)0x7e30, (q15_t)0xea8e, (q15_t)0x7e2f, (q15_t)0xea88, + (q15_t)0x7e2e, (q15_t)0xea81, (q15_t)0x7e2d, (q15_t)0xea7b, (q15_t)0x7e2c, (q15_t)0xea75, (q15_t)0x7e2b, (q15_t)0xea6f, + (q15_t)0x7e2a, (q15_t)0xea69, (q15_t)0x7e29, (q15_t)0xea63, (q15_t)0x7e28, (q15_t)0xea5c, (q15_t)0x7e27, (q15_t)0xea56, + (q15_t)0x7e26, (q15_t)0xea50, (q15_t)0x7e25, (q15_t)0xea4a, (q15_t)0x7e24, (q15_t)0xea44, (q15_t)0x7e22, (q15_t)0xea3d, + (q15_t)0x7e21, (q15_t)0xea37, (q15_t)0x7e20, (q15_t)0xea31, (q15_t)0x7e1f, (q15_t)0xea2b, (q15_t)0x7e1e, (q15_t)0xea25, + (q15_t)0x7e1d, (q15_t)0xea1e, (q15_t)0x7e1c, (q15_t)0xea18, (q15_t)0x7e1b, (q15_t)0xea12, (q15_t)0x7e1a, (q15_t)0xea0c, + (q15_t)0x7e19, (q15_t)0xea06, (q15_t)0x7e18, (q15_t)0xe9ff, (q15_t)0x7e17, (q15_t)0xe9f9, (q15_t)0x7e16, (q15_t)0xe9f3, + (q15_t)0x7e14, (q15_t)0xe9ed, (q15_t)0x7e13, (q15_t)0xe9e7, (q15_t)0x7e12, (q15_t)0xe9e1, (q15_t)0x7e11, (q15_t)0xe9da, + (q15_t)0x7e10, (q15_t)0xe9d4, (q15_t)0x7e0f, (q15_t)0xe9ce, (q15_t)0x7e0e, (q15_t)0xe9c8, (q15_t)0x7e0d, (q15_t)0xe9c2, + (q15_t)0x7e0c, (q15_t)0xe9bb, (q15_t)0x7e0b, (q15_t)0xe9b5, (q15_t)0x7e0a, (q15_t)0xe9af, (q15_t)0x7e08, (q15_t)0xe9a9, + (q15_t)0x7e07, (q15_t)0xe9a3, (q15_t)0x7e06, (q15_t)0xe99c, (q15_t)0x7e05, (q15_t)0xe996, (q15_t)0x7e04, (q15_t)0xe990, + (q15_t)0x7e03, (q15_t)0xe98a, (q15_t)0x7e02, (q15_t)0xe984, (q15_t)0x7e01, (q15_t)0xe97e, (q15_t)0x7e00, (q15_t)0xe977, + (q15_t)0x7dff, (q15_t)0xe971, (q15_t)0x7dfd, (q15_t)0xe96b, (q15_t)0x7dfc, (q15_t)0xe965, (q15_t)0x7dfb, (q15_t)0xe95f, + (q15_t)0x7dfa, (q15_t)0xe958, (q15_t)0x7df9, (q15_t)0xe952, (q15_t)0x7df8, (q15_t)0xe94c, (q15_t)0x7df7, (q15_t)0xe946, + (q15_t)0x7df6, (q15_t)0xe940, (q15_t)0x7df5, (q15_t)0xe93a, (q15_t)0x7df3, (q15_t)0xe933, (q15_t)0x7df2, (q15_t)0xe92d, + (q15_t)0x7df1, (q15_t)0xe927, (q15_t)0x7df0, (q15_t)0xe921, (q15_t)0x7def, (q15_t)0xe91b, (q15_t)0x7dee, (q15_t)0xe914, + (q15_t)0x7ded, (q15_t)0xe90e, (q15_t)0x7dec, (q15_t)0xe908, (q15_t)0x7dea, (q15_t)0xe902, (q15_t)0x7de9, (q15_t)0xe8fc, + (q15_t)0x7de8, (q15_t)0xe8f6, (q15_t)0x7de7, (q15_t)0xe8ef, (q15_t)0x7de6, (q15_t)0xe8e9, (q15_t)0x7de5, (q15_t)0xe8e3, + (q15_t)0x7de4, (q15_t)0xe8dd, (q15_t)0x7de2, (q15_t)0xe8d7, (q15_t)0x7de1, (q15_t)0xe8d0, (q15_t)0x7de0, (q15_t)0xe8ca, + (q15_t)0x7ddf, (q15_t)0xe8c4, (q15_t)0x7dde, (q15_t)0xe8be, (q15_t)0x7ddd, (q15_t)0xe8b8, (q15_t)0x7ddc, (q15_t)0xe8b2, + (q15_t)0x7dda, (q15_t)0xe8ab, (q15_t)0x7dd9, (q15_t)0xe8a5, (q15_t)0x7dd8, (q15_t)0xe89f, (q15_t)0x7dd7, (q15_t)0xe899, + (q15_t)0x7dd6, (q15_t)0xe893, (q15_t)0x7dd5, (q15_t)0xe88c, (q15_t)0x7dd4, (q15_t)0xe886, (q15_t)0x7dd2, (q15_t)0xe880, + (q15_t)0x7dd1, (q15_t)0xe87a, (q15_t)0x7dd0, (q15_t)0xe874, (q15_t)0x7dcf, (q15_t)0xe86e, (q15_t)0x7dce, (q15_t)0xe867, + (q15_t)0x7dcd, (q15_t)0xe861, (q15_t)0x7dcc, (q15_t)0xe85b, (q15_t)0x7dca, (q15_t)0xe855, (q15_t)0x7dc9, (q15_t)0xe84f, + (q15_t)0x7dc8, (q15_t)0xe849, (q15_t)0x7dc7, (q15_t)0xe842, (q15_t)0x7dc6, (q15_t)0xe83c, (q15_t)0x7dc5, (q15_t)0xe836, + (q15_t)0x7dc3, (q15_t)0xe830, (q15_t)0x7dc2, (q15_t)0xe82a, (q15_t)0x7dc1, (q15_t)0xe823, (q15_t)0x7dc0, (q15_t)0xe81d, + (q15_t)0x7dbf, (q15_t)0xe817, (q15_t)0x7dbd, (q15_t)0xe811, (q15_t)0x7dbc, (q15_t)0xe80b, (q15_t)0x7dbb, (q15_t)0xe805, + (q15_t)0x7dba, (q15_t)0xe7fe, (q15_t)0x7db9, (q15_t)0xe7f8, (q15_t)0x7db8, (q15_t)0xe7f2, (q15_t)0x7db6, (q15_t)0xe7ec, + (q15_t)0x7db5, (q15_t)0xe7e6, (q15_t)0x7db4, (q15_t)0xe7e0, (q15_t)0x7db3, (q15_t)0xe7d9, (q15_t)0x7db2, (q15_t)0xe7d3, + (q15_t)0x7db0, (q15_t)0xe7cd, (q15_t)0x7daf, (q15_t)0xe7c7, (q15_t)0x7dae, (q15_t)0xe7c1, (q15_t)0x7dad, (q15_t)0xe7bb, + (q15_t)0x7dac, (q15_t)0xe7b4, (q15_t)0x7dab, (q15_t)0xe7ae, (q15_t)0x7da9, (q15_t)0xe7a8, (q15_t)0x7da8, (q15_t)0xe7a2, + (q15_t)0x7da7, (q15_t)0xe79c, (q15_t)0x7da6, (q15_t)0xe796, (q15_t)0x7da5, (q15_t)0xe78f, (q15_t)0x7da3, (q15_t)0xe789, + (q15_t)0x7da2, (q15_t)0xe783, (q15_t)0x7da1, (q15_t)0xe77d, (q15_t)0x7da0, (q15_t)0xe777, (q15_t)0x7d9f, (q15_t)0xe771, + (q15_t)0x7d9d, (q15_t)0xe76a, (q15_t)0x7d9c, (q15_t)0xe764, (q15_t)0x7d9b, (q15_t)0xe75e, (q15_t)0x7d9a, (q15_t)0xe758, + (q15_t)0x7d98, (q15_t)0xe752, (q15_t)0x7d97, (q15_t)0xe74c, (q15_t)0x7d96, (q15_t)0xe745, (q15_t)0x7d95, (q15_t)0xe73f, + (q15_t)0x7d94, (q15_t)0xe739, (q15_t)0x7d92, (q15_t)0xe733, (q15_t)0x7d91, (q15_t)0xe72d, (q15_t)0x7d90, (q15_t)0xe727, + (q15_t)0x7d8f, (q15_t)0xe720, (q15_t)0x7d8e, (q15_t)0xe71a, (q15_t)0x7d8c, (q15_t)0xe714, (q15_t)0x7d8b, (q15_t)0xe70e, + (q15_t)0x7d8a, (q15_t)0xe708, (q15_t)0x7d89, (q15_t)0xe702, (q15_t)0x7d87, (q15_t)0xe6fb, (q15_t)0x7d86, (q15_t)0xe6f5, + (q15_t)0x7d85, (q15_t)0xe6ef, (q15_t)0x7d84, (q15_t)0xe6e9, (q15_t)0x7d82, (q15_t)0xe6e3, (q15_t)0x7d81, (q15_t)0xe6dd, + (q15_t)0x7d80, (q15_t)0xe6d6, (q15_t)0x7d7f, (q15_t)0xe6d0, (q15_t)0x7d7e, (q15_t)0xe6ca, (q15_t)0x7d7c, (q15_t)0xe6c4, + (q15_t)0x7d7b, (q15_t)0xe6be, (q15_t)0x7d7a, (q15_t)0xe6b8, (q15_t)0x7d79, (q15_t)0xe6b2, (q15_t)0x7d77, (q15_t)0xe6ab, + (q15_t)0x7d76, (q15_t)0xe6a5, (q15_t)0x7d75, (q15_t)0xe69f, (q15_t)0x7d74, (q15_t)0xe699, (q15_t)0x7d72, (q15_t)0xe693, + (q15_t)0x7d71, (q15_t)0xe68d, (q15_t)0x7d70, (q15_t)0xe686, (q15_t)0x7d6f, (q15_t)0xe680, (q15_t)0x7d6d, (q15_t)0xe67a, + (q15_t)0x7d6c, (q15_t)0xe674, (q15_t)0x7d6b, (q15_t)0xe66e, (q15_t)0x7d6a, (q15_t)0xe668, (q15_t)0x7d68, (q15_t)0xe661, + (q15_t)0x7d67, (q15_t)0xe65b, (q15_t)0x7d66, (q15_t)0xe655, (q15_t)0x7d65, (q15_t)0xe64f, (q15_t)0x7d63, (q15_t)0xe649, + (q15_t)0x7d62, (q15_t)0xe643, (q15_t)0x7d61, (q15_t)0xe63d, (q15_t)0x7d60, (q15_t)0xe636, (q15_t)0x7d5e, (q15_t)0xe630, + (q15_t)0x7d5d, (q15_t)0xe62a, (q15_t)0x7d5c, (q15_t)0xe624, (q15_t)0x7d5a, (q15_t)0xe61e, (q15_t)0x7d59, (q15_t)0xe618, + (q15_t)0x7d58, (q15_t)0xe611, (q15_t)0x7d57, (q15_t)0xe60b, (q15_t)0x7d55, (q15_t)0xe605, (q15_t)0x7d54, (q15_t)0xe5ff, + (q15_t)0x7d53, (q15_t)0xe5f9, (q15_t)0x7d52, (q15_t)0xe5f3, (q15_t)0x7d50, (q15_t)0xe5ed, (q15_t)0x7d4f, (q15_t)0xe5e6, + (q15_t)0x7d4e, (q15_t)0xe5e0, (q15_t)0x7d4c, (q15_t)0xe5da, (q15_t)0x7d4b, (q15_t)0xe5d4, (q15_t)0x7d4a, (q15_t)0xe5ce, + (q15_t)0x7d49, (q15_t)0xe5c8, (q15_t)0x7d47, (q15_t)0xe5c2, (q15_t)0x7d46, (q15_t)0xe5bb, (q15_t)0x7d45, (q15_t)0xe5b5, + (q15_t)0x7d43, (q15_t)0xe5af, (q15_t)0x7d42, (q15_t)0xe5a9, (q15_t)0x7d41, (q15_t)0xe5a3, (q15_t)0x7d3f, (q15_t)0xe59d, + (q15_t)0x7d3e, (q15_t)0xe596, (q15_t)0x7d3d, (q15_t)0xe590, (q15_t)0x7d3c, (q15_t)0xe58a, (q15_t)0x7d3a, (q15_t)0xe584, + (q15_t)0x7d39, (q15_t)0xe57e, (q15_t)0x7d38, (q15_t)0xe578, (q15_t)0x7d36, (q15_t)0xe572, (q15_t)0x7d35, (q15_t)0xe56b, + (q15_t)0x7d34, (q15_t)0xe565, (q15_t)0x7d32, (q15_t)0xe55f, (q15_t)0x7d31, (q15_t)0xe559, (q15_t)0x7d30, (q15_t)0xe553, + (q15_t)0x7d2f, (q15_t)0xe54d, (q15_t)0x7d2d, (q15_t)0xe547, (q15_t)0x7d2c, (q15_t)0xe540, (q15_t)0x7d2b, (q15_t)0xe53a, + (q15_t)0x7d29, (q15_t)0xe534, (q15_t)0x7d28, (q15_t)0xe52e, (q15_t)0x7d27, (q15_t)0xe528, (q15_t)0x7d25, (q15_t)0xe522, + (q15_t)0x7d24, (q15_t)0xe51c, (q15_t)0x7d23, (q15_t)0xe515, (q15_t)0x7d21, (q15_t)0xe50f, (q15_t)0x7d20, (q15_t)0xe509, + (q15_t)0x7d1f, (q15_t)0xe503, (q15_t)0x7d1d, (q15_t)0xe4fd, (q15_t)0x7d1c, (q15_t)0xe4f7, (q15_t)0x7d1b, (q15_t)0xe4f1, + (q15_t)0x7d19, (q15_t)0xe4ea, (q15_t)0x7d18, (q15_t)0xe4e4, (q15_t)0x7d17, (q15_t)0xe4de, (q15_t)0x7d15, (q15_t)0xe4d8, + (q15_t)0x7d14, (q15_t)0xe4d2, (q15_t)0x7d13, (q15_t)0xe4cc, (q15_t)0x7d11, (q15_t)0xe4c6, (q15_t)0x7d10, (q15_t)0xe4bf, + (q15_t)0x7d0f, (q15_t)0xe4b9, (q15_t)0x7d0d, (q15_t)0xe4b3, (q15_t)0x7d0c, (q15_t)0xe4ad, (q15_t)0x7d0b, (q15_t)0xe4a7, + (q15_t)0x7d09, (q15_t)0xe4a1, (q15_t)0x7d08, (q15_t)0xe49b, (q15_t)0x7d07, (q15_t)0xe494, (q15_t)0x7d05, (q15_t)0xe48e, + (q15_t)0x7d04, (q15_t)0xe488, (q15_t)0x7d03, (q15_t)0xe482, (q15_t)0x7d01, (q15_t)0xe47c, (q15_t)0x7d00, (q15_t)0xe476, + (q15_t)0x7cff, (q15_t)0xe470, (q15_t)0x7cfd, (q15_t)0xe46a, (q15_t)0x7cfc, (q15_t)0xe463, (q15_t)0x7cfb, (q15_t)0xe45d, + (q15_t)0x7cf9, (q15_t)0xe457, (q15_t)0x7cf8, (q15_t)0xe451, (q15_t)0x7cf6, (q15_t)0xe44b, (q15_t)0x7cf5, (q15_t)0xe445, + (q15_t)0x7cf4, (q15_t)0xe43f, (q15_t)0x7cf2, (q15_t)0xe438, (q15_t)0x7cf1, (q15_t)0xe432, (q15_t)0x7cf0, (q15_t)0xe42c, + (q15_t)0x7cee, (q15_t)0xe426, (q15_t)0x7ced, (q15_t)0xe420, (q15_t)0x7cec, (q15_t)0xe41a, (q15_t)0x7cea, (q15_t)0xe414, + (q15_t)0x7ce9, (q15_t)0xe40e, (q15_t)0x7ce7, (q15_t)0xe407, (q15_t)0x7ce6, (q15_t)0xe401, (q15_t)0x7ce5, (q15_t)0xe3fb, + (q15_t)0x7ce3, (q15_t)0xe3f5, (q15_t)0x7ce2, (q15_t)0xe3ef, (q15_t)0x7ce1, (q15_t)0xe3e9, (q15_t)0x7cdf, (q15_t)0xe3e3, + (q15_t)0x7cde, (q15_t)0xe3dc, (q15_t)0x7cdc, (q15_t)0xe3d6, (q15_t)0x7cdb, (q15_t)0xe3d0, (q15_t)0x7cda, (q15_t)0xe3ca, + (q15_t)0x7cd8, (q15_t)0xe3c4, (q15_t)0x7cd7, (q15_t)0xe3be, (q15_t)0x7cd5, (q15_t)0xe3b8, (q15_t)0x7cd4, (q15_t)0xe3b2, + (q15_t)0x7cd3, (q15_t)0xe3ab, (q15_t)0x7cd1, (q15_t)0xe3a5, (q15_t)0x7cd0, (q15_t)0xe39f, (q15_t)0x7ccf, (q15_t)0xe399, + (q15_t)0x7ccd, (q15_t)0xe393, (q15_t)0x7ccc, (q15_t)0xe38d, (q15_t)0x7cca, (q15_t)0xe387, (q15_t)0x7cc9, (q15_t)0xe381, + (q15_t)0x7cc8, (q15_t)0xe37a, (q15_t)0x7cc6, (q15_t)0xe374, (q15_t)0x7cc5, (q15_t)0xe36e, (q15_t)0x7cc3, (q15_t)0xe368, + (q15_t)0x7cc2, (q15_t)0xe362, (q15_t)0x7cc1, (q15_t)0xe35c, (q15_t)0x7cbf, (q15_t)0xe356, (q15_t)0x7cbe, (q15_t)0xe350, + (q15_t)0x7cbc, (q15_t)0xe349, (q15_t)0x7cbb, (q15_t)0xe343, (q15_t)0x7cb9, (q15_t)0xe33d, (q15_t)0x7cb8, (q15_t)0xe337, + (q15_t)0x7cb7, (q15_t)0xe331, (q15_t)0x7cb5, (q15_t)0xe32b, (q15_t)0x7cb4, (q15_t)0xe325, (q15_t)0x7cb2, (q15_t)0xe31f, + (q15_t)0x7cb1, (q15_t)0xe318, (q15_t)0x7cb0, (q15_t)0xe312, (q15_t)0x7cae, (q15_t)0xe30c, (q15_t)0x7cad, (q15_t)0xe306, + (q15_t)0x7cab, (q15_t)0xe300, (q15_t)0x7caa, (q15_t)0xe2fa, (q15_t)0x7ca8, (q15_t)0xe2f4, (q15_t)0x7ca7, (q15_t)0xe2ee, + (q15_t)0x7ca6, (q15_t)0xe2e8, (q15_t)0x7ca4, (q15_t)0xe2e1, (q15_t)0x7ca3, (q15_t)0xe2db, (q15_t)0x7ca1, (q15_t)0xe2d5, + (q15_t)0x7ca0, (q15_t)0xe2cf, (q15_t)0x7c9e, (q15_t)0xe2c9, (q15_t)0x7c9d, (q15_t)0xe2c3, (q15_t)0x7c9c, (q15_t)0xe2bd, + (q15_t)0x7c9a, (q15_t)0xe2b7, (q15_t)0x7c99, (q15_t)0xe2b0, (q15_t)0x7c97, (q15_t)0xe2aa, (q15_t)0x7c96, (q15_t)0xe2a4, + (q15_t)0x7c94, (q15_t)0xe29e, (q15_t)0x7c93, (q15_t)0xe298, (q15_t)0x7c91, (q15_t)0xe292, (q15_t)0x7c90, (q15_t)0xe28c, + (q15_t)0x7c8f, (q15_t)0xe286, (q15_t)0x7c8d, (q15_t)0xe280, (q15_t)0x7c8c, (q15_t)0xe279, (q15_t)0x7c8a, (q15_t)0xe273, + (q15_t)0x7c89, (q15_t)0xe26d, (q15_t)0x7c87, (q15_t)0xe267, (q15_t)0x7c86, (q15_t)0xe261, (q15_t)0x7c84, (q15_t)0xe25b, + (q15_t)0x7c83, (q15_t)0xe255, (q15_t)0x7c82, (q15_t)0xe24f, (q15_t)0x7c80, (q15_t)0xe249, (q15_t)0x7c7f, (q15_t)0xe242, + (q15_t)0x7c7d, (q15_t)0xe23c, (q15_t)0x7c7c, (q15_t)0xe236, (q15_t)0x7c7a, (q15_t)0xe230, (q15_t)0x7c79, (q15_t)0xe22a, + (q15_t)0x7c77, (q15_t)0xe224, (q15_t)0x7c76, (q15_t)0xe21e, (q15_t)0x7c74, (q15_t)0xe218, (q15_t)0x7c73, (q15_t)0xe212, + (q15_t)0x7c71, (q15_t)0xe20b, (q15_t)0x7c70, (q15_t)0xe205, (q15_t)0x7c6e, (q15_t)0xe1ff, (q15_t)0x7c6d, (q15_t)0xe1f9, + (q15_t)0x7c6c, (q15_t)0xe1f3, (q15_t)0x7c6a, (q15_t)0xe1ed, (q15_t)0x7c69, (q15_t)0xe1e7, (q15_t)0x7c67, (q15_t)0xe1e1, + (q15_t)0x7c66, (q15_t)0xe1db, (q15_t)0x7c64, (q15_t)0xe1d4, (q15_t)0x7c63, (q15_t)0xe1ce, (q15_t)0x7c61, (q15_t)0xe1c8, + (q15_t)0x7c60, (q15_t)0xe1c2, (q15_t)0x7c5e, (q15_t)0xe1bc, (q15_t)0x7c5d, (q15_t)0xe1b6, (q15_t)0x7c5b, (q15_t)0xe1b0, + (q15_t)0x7c5a, (q15_t)0xe1aa, (q15_t)0x7c58, (q15_t)0xe1a4, (q15_t)0x7c57, (q15_t)0xe19e, (q15_t)0x7c55, (q15_t)0xe197, + (q15_t)0x7c54, (q15_t)0xe191, (q15_t)0x7c52, (q15_t)0xe18b, (q15_t)0x7c51, (q15_t)0xe185, (q15_t)0x7c4f, (q15_t)0xe17f, + (q15_t)0x7c4e, (q15_t)0xe179, (q15_t)0x7c4c, (q15_t)0xe173, (q15_t)0x7c4b, (q15_t)0xe16d, (q15_t)0x7c49, (q15_t)0xe167, + (q15_t)0x7c48, (q15_t)0xe160, (q15_t)0x7c46, (q15_t)0xe15a, (q15_t)0x7c45, (q15_t)0xe154, (q15_t)0x7c43, (q15_t)0xe14e, + (q15_t)0x7c42, (q15_t)0xe148, (q15_t)0x7c40, (q15_t)0xe142, (q15_t)0x7c3f, (q15_t)0xe13c, (q15_t)0x7c3d, (q15_t)0xe136, + (q15_t)0x7c3c, (q15_t)0xe130, (q15_t)0x7c3a, (q15_t)0xe12a, (q15_t)0x7c39, (q15_t)0xe123, (q15_t)0x7c37, (q15_t)0xe11d, + (q15_t)0x7c36, (q15_t)0xe117, (q15_t)0x7c34, (q15_t)0xe111, (q15_t)0x7c33, (q15_t)0xe10b, (q15_t)0x7c31, (q15_t)0xe105, + (q15_t)0x7c30, (q15_t)0xe0ff, (q15_t)0x7c2e, (q15_t)0xe0f9, (q15_t)0x7c2d, (q15_t)0xe0f3, (q15_t)0x7c2b, (q15_t)0xe0ed, + (q15_t)0x7c29, (q15_t)0xe0e7, (q15_t)0x7c28, (q15_t)0xe0e0, (q15_t)0x7c26, (q15_t)0xe0da, (q15_t)0x7c25, (q15_t)0xe0d4, + (q15_t)0x7c23, (q15_t)0xe0ce, (q15_t)0x7c22, (q15_t)0xe0c8, (q15_t)0x7c20, (q15_t)0xe0c2, (q15_t)0x7c1f, (q15_t)0xe0bc, + (q15_t)0x7c1d, (q15_t)0xe0b6, (q15_t)0x7c1c, (q15_t)0xe0b0, (q15_t)0x7c1a, (q15_t)0xe0aa, (q15_t)0x7c19, (q15_t)0xe0a3, + (q15_t)0x7c17, (q15_t)0xe09d, (q15_t)0x7c16, (q15_t)0xe097, (q15_t)0x7c14, (q15_t)0xe091, (q15_t)0x7c12, (q15_t)0xe08b, + (q15_t)0x7c11, (q15_t)0xe085, (q15_t)0x7c0f, (q15_t)0xe07f, (q15_t)0x7c0e, (q15_t)0xe079, (q15_t)0x7c0c, (q15_t)0xe073, + (q15_t)0x7c0b, (q15_t)0xe06d, (q15_t)0x7c09, (q15_t)0xe067, (q15_t)0x7c08, (q15_t)0xe061, (q15_t)0x7c06, (q15_t)0xe05a, + (q15_t)0x7c05, (q15_t)0xe054, (q15_t)0x7c03, (q15_t)0xe04e, (q15_t)0x7c01, (q15_t)0xe048, (q15_t)0x7c00, (q15_t)0xe042, + (q15_t)0x7bfe, (q15_t)0xe03c, (q15_t)0x7bfd, (q15_t)0xe036, (q15_t)0x7bfb, (q15_t)0xe030, (q15_t)0x7bfa, (q15_t)0xe02a, + (q15_t)0x7bf8, (q15_t)0xe024, (q15_t)0x7bf6, (q15_t)0xe01e, (q15_t)0x7bf5, (q15_t)0xe017, (q15_t)0x7bf3, (q15_t)0xe011, + (q15_t)0x7bf2, (q15_t)0xe00b, (q15_t)0x7bf0, (q15_t)0xe005, (q15_t)0x7bef, (q15_t)0xdfff, (q15_t)0x7bed, (q15_t)0xdff9, + (q15_t)0x7beb, (q15_t)0xdff3, (q15_t)0x7bea, (q15_t)0xdfed, (q15_t)0x7be8, (q15_t)0xdfe7, (q15_t)0x7be7, (q15_t)0xdfe1, + (q15_t)0x7be5, (q15_t)0xdfdb, (q15_t)0x7be4, (q15_t)0xdfd5, (q15_t)0x7be2, (q15_t)0xdfce, (q15_t)0x7be0, (q15_t)0xdfc8, + (q15_t)0x7bdf, (q15_t)0xdfc2, (q15_t)0x7bdd, (q15_t)0xdfbc, (q15_t)0x7bdc, (q15_t)0xdfb6, (q15_t)0x7bda, (q15_t)0xdfb0, + (q15_t)0x7bd9, (q15_t)0xdfaa, (q15_t)0x7bd7, (q15_t)0xdfa4, (q15_t)0x7bd5, (q15_t)0xdf9e, (q15_t)0x7bd4, (q15_t)0xdf98, + (q15_t)0x7bd2, (q15_t)0xdf92, (q15_t)0x7bd1, (q15_t)0xdf8c, (q15_t)0x7bcf, (q15_t)0xdf86, (q15_t)0x7bcd, (q15_t)0xdf7f, + (q15_t)0x7bcc, (q15_t)0xdf79, (q15_t)0x7bca, (q15_t)0xdf73, (q15_t)0x7bc9, (q15_t)0xdf6d, (q15_t)0x7bc7, (q15_t)0xdf67, + (q15_t)0x7bc5, (q15_t)0xdf61, (q15_t)0x7bc4, (q15_t)0xdf5b, (q15_t)0x7bc2, (q15_t)0xdf55, (q15_t)0x7bc1, (q15_t)0xdf4f, + (q15_t)0x7bbf, (q15_t)0xdf49, (q15_t)0x7bbd, (q15_t)0xdf43, (q15_t)0x7bbc, (q15_t)0xdf3d, (q15_t)0x7bba, (q15_t)0xdf37, + (q15_t)0x7bb9, (q15_t)0xdf30, (q15_t)0x7bb7, (q15_t)0xdf2a, (q15_t)0x7bb5, (q15_t)0xdf24, (q15_t)0x7bb4, (q15_t)0xdf1e, + (q15_t)0x7bb2, (q15_t)0xdf18, (q15_t)0x7bb0, (q15_t)0xdf12, (q15_t)0x7baf, (q15_t)0xdf0c, (q15_t)0x7bad, (q15_t)0xdf06, + (q15_t)0x7bac, (q15_t)0xdf00, (q15_t)0x7baa, (q15_t)0xdefa, (q15_t)0x7ba8, (q15_t)0xdef4, (q15_t)0x7ba7, (q15_t)0xdeee, + (q15_t)0x7ba5, (q15_t)0xdee8, (q15_t)0x7ba3, (q15_t)0xdee2, (q15_t)0x7ba2, (q15_t)0xdedb, (q15_t)0x7ba0, (q15_t)0xded5, + (q15_t)0x7b9f, (q15_t)0xdecf, (q15_t)0x7b9d, (q15_t)0xdec9, (q15_t)0x7b9b, (q15_t)0xdec3, (q15_t)0x7b9a, (q15_t)0xdebd, + (q15_t)0x7b98, (q15_t)0xdeb7, (q15_t)0x7b96, (q15_t)0xdeb1, (q15_t)0x7b95, (q15_t)0xdeab, (q15_t)0x7b93, (q15_t)0xdea5, + (q15_t)0x7b92, (q15_t)0xde9f, (q15_t)0x7b90, (q15_t)0xde99, (q15_t)0x7b8e, (q15_t)0xde93, (q15_t)0x7b8d, (q15_t)0xde8d, + (q15_t)0x7b8b, (q15_t)0xde87, (q15_t)0x7b89, (q15_t)0xde80, (q15_t)0x7b88, (q15_t)0xde7a, (q15_t)0x7b86, (q15_t)0xde74, + (q15_t)0x7b84, (q15_t)0xde6e, (q15_t)0x7b83, (q15_t)0xde68, (q15_t)0x7b81, (q15_t)0xde62, (q15_t)0x7b7f, (q15_t)0xde5c, + (q15_t)0x7b7e, (q15_t)0xde56, (q15_t)0x7b7c, (q15_t)0xde50, (q15_t)0x7b7a, (q15_t)0xde4a, (q15_t)0x7b79, (q15_t)0xde44, + (q15_t)0x7b77, (q15_t)0xde3e, (q15_t)0x7b76, (q15_t)0xde38, (q15_t)0x7b74, (q15_t)0xde32, (q15_t)0x7b72, (q15_t)0xde2c, + (q15_t)0x7b71, (q15_t)0xde26, (q15_t)0x7b6f, (q15_t)0xde1f, (q15_t)0x7b6d, (q15_t)0xde19, (q15_t)0x7b6c, (q15_t)0xde13, + (q15_t)0x7b6a, (q15_t)0xde0d, (q15_t)0x7b68, (q15_t)0xde07, (q15_t)0x7b67, (q15_t)0xde01, (q15_t)0x7b65, (q15_t)0xddfb, + (q15_t)0x7b63, (q15_t)0xddf5, (q15_t)0x7b62, (q15_t)0xddef, (q15_t)0x7b60, (q15_t)0xdde9, (q15_t)0x7b5e, (q15_t)0xdde3, + (q15_t)0x7b5d, (q15_t)0xdddd, (q15_t)0x7b5b, (q15_t)0xddd7, (q15_t)0x7b59, (q15_t)0xddd1, (q15_t)0x7b57, (q15_t)0xddcb, + (q15_t)0x7b56, (q15_t)0xddc5, (q15_t)0x7b54, (q15_t)0xddbf, (q15_t)0x7b52, (q15_t)0xddb9, (q15_t)0x7b51, (q15_t)0xddb2, + (q15_t)0x7b4f, (q15_t)0xddac, (q15_t)0x7b4d, (q15_t)0xdda6, (q15_t)0x7b4c, (q15_t)0xdda0, (q15_t)0x7b4a, (q15_t)0xdd9a, + (q15_t)0x7b48, (q15_t)0xdd94, (q15_t)0x7b47, (q15_t)0xdd8e, (q15_t)0x7b45, (q15_t)0xdd88, (q15_t)0x7b43, (q15_t)0xdd82, + (q15_t)0x7b42, (q15_t)0xdd7c, (q15_t)0x7b40, (q15_t)0xdd76, (q15_t)0x7b3e, (q15_t)0xdd70, (q15_t)0x7b3c, (q15_t)0xdd6a, + (q15_t)0x7b3b, (q15_t)0xdd64, (q15_t)0x7b39, (q15_t)0xdd5e, (q15_t)0x7b37, (q15_t)0xdd58, (q15_t)0x7b36, (q15_t)0xdd52, + (q15_t)0x7b34, (q15_t)0xdd4c, (q15_t)0x7b32, (q15_t)0xdd46, (q15_t)0x7b31, (q15_t)0xdd40, (q15_t)0x7b2f, (q15_t)0xdd39, + (q15_t)0x7b2d, (q15_t)0xdd33, (q15_t)0x7b2b, (q15_t)0xdd2d, (q15_t)0x7b2a, (q15_t)0xdd27, (q15_t)0x7b28, (q15_t)0xdd21, + (q15_t)0x7b26, (q15_t)0xdd1b, (q15_t)0x7b25, (q15_t)0xdd15, (q15_t)0x7b23, (q15_t)0xdd0f, (q15_t)0x7b21, (q15_t)0xdd09, + (q15_t)0x7b1f, (q15_t)0xdd03, (q15_t)0x7b1e, (q15_t)0xdcfd, (q15_t)0x7b1c, (q15_t)0xdcf7, (q15_t)0x7b1a, (q15_t)0xdcf1, + (q15_t)0x7b19, (q15_t)0xdceb, (q15_t)0x7b17, (q15_t)0xdce5, (q15_t)0x7b15, (q15_t)0xdcdf, (q15_t)0x7b13, (q15_t)0xdcd9, + (q15_t)0x7b12, (q15_t)0xdcd3, (q15_t)0x7b10, (q15_t)0xdccd, (q15_t)0x7b0e, (q15_t)0xdcc7, (q15_t)0x7b0c, (q15_t)0xdcc1, + (q15_t)0x7b0b, (q15_t)0xdcbb, (q15_t)0x7b09, (q15_t)0xdcb5, (q15_t)0x7b07, (q15_t)0xdcae, (q15_t)0x7b06, (q15_t)0xdca8, + (q15_t)0x7b04, (q15_t)0xdca2, (q15_t)0x7b02, (q15_t)0xdc9c, (q15_t)0x7b00, (q15_t)0xdc96, (q15_t)0x7aff, (q15_t)0xdc90, + (q15_t)0x7afd, (q15_t)0xdc8a, (q15_t)0x7afb, (q15_t)0xdc84, (q15_t)0x7af9, (q15_t)0xdc7e, (q15_t)0x7af8, (q15_t)0xdc78, + (q15_t)0x7af6, (q15_t)0xdc72, (q15_t)0x7af4, (q15_t)0xdc6c, (q15_t)0x7af2, (q15_t)0xdc66, (q15_t)0x7af1, (q15_t)0xdc60, + (q15_t)0x7aef, (q15_t)0xdc5a, (q15_t)0x7aed, (q15_t)0xdc54, (q15_t)0x7aeb, (q15_t)0xdc4e, (q15_t)0x7aea, (q15_t)0xdc48, + (q15_t)0x7ae8, (q15_t)0xdc42, (q15_t)0x7ae6, (q15_t)0xdc3c, (q15_t)0x7ae4, (q15_t)0xdc36, (q15_t)0x7ae3, (q15_t)0xdc30, + (q15_t)0x7ae1, (q15_t)0xdc2a, (q15_t)0x7adf, (q15_t)0xdc24, (q15_t)0x7add, (q15_t)0xdc1e, (q15_t)0x7adc, (q15_t)0xdc18, + (q15_t)0x7ada, (q15_t)0xdc12, (q15_t)0x7ad8, (q15_t)0xdc0c, (q15_t)0x7ad6, (q15_t)0xdc06, (q15_t)0x7ad5, (q15_t)0xdbff, + (q15_t)0x7ad3, (q15_t)0xdbf9, (q15_t)0x7ad1, (q15_t)0xdbf3, (q15_t)0x7acf, (q15_t)0xdbed, (q15_t)0x7acd, (q15_t)0xdbe7, + (q15_t)0x7acc, (q15_t)0xdbe1, (q15_t)0x7aca, (q15_t)0xdbdb, (q15_t)0x7ac8, (q15_t)0xdbd5, (q15_t)0x7ac6, (q15_t)0xdbcf, + (q15_t)0x7ac5, (q15_t)0xdbc9, (q15_t)0x7ac3, (q15_t)0xdbc3, (q15_t)0x7ac1, (q15_t)0xdbbd, (q15_t)0x7abf, (q15_t)0xdbb7, + (q15_t)0x7abd, (q15_t)0xdbb1, (q15_t)0x7abc, (q15_t)0xdbab, (q15_t)0x7aba, (q15_t)0xdba5, (q15_t)0x7ab8, (q15_t)0xdb9f, + (q15_t)0x7ab6, (q15_t)0xdb99, (q15_t)0x7ab5, (q15_t)0xdb93, (q15_t)0x7ab3, (q15_t)0xdb8d, (q15_t)0x7ab1, (q15_t)0xdb87, + (q15_t)0x7aaf, (q15_t)0xdb81, (q15_t)0x7aad, (q15_t)0xdb7b, (q15_t)0x7aac, (q15_t)0xdb75, (q15_t)0x7aaa, (q15_t)0xdb6f, + (q15_t)0x7aa8, (q15_t)0xdb69, (q15_t)0x7aa6, (q15_t)0xdb63, (q15_t)0x7aa4, (q15_t)0xdb5d, (q15_t)0x7aa3, (q15_t)0xdb57, + (q15_t)0x7aa1, (q15_t)0xdb51, (q15_t)0x7a9f, (q15_t)0xdb4b, (q15_t)0x7a9d, (q15_t)0xdb45, (q15_t)0x7a9b, (q15_t)0xdb3f, + (q15_t)0x7a9a, (q15_t)0xdb39, (q15_t)0x7a98, (q15_t)0xdb33, (q15_t)0x7a96, (q15_t)0xdb2d, (q15_t)0x7a94, (q15_t)0xdb27, + (q15_t)0x7a92, (q15_t)0xdb21, (q15_t)0x7a91, (q15_t)0xdb1b, (q15_t)0x7a8f, (q15_t)0xdb15, (q15_t)0x7a8d, (q15_t)0xdb0f, + (q15_t)0x7a8b, (q15_t)0xdb09, (q15_t)0x7a89, (q15_t)0xdb03, (q15_t)0x7a87, (q15_t)0xdafd, (q15_t)0x7a86, (q15_t)0xdaf7, + (q15_t)0x7a84, (q15_t)0xdaf1, (q15_t)0x7a82, (q15_t)0xdaea, (q15_t)0x7a80, (q15_t)0xdae4, (q15_t)0x7a7e, (q15_t)0xdade, + (q15_t)0x7a7d, (q15_t)0xdad8, (q15_t)0x7a7b, (q15_t)0xdad2, (q15_t)0x7a79, (q15_t)0xdacc, (q15_t)0x7a77, (q15_t)0xdac6, + (q15_t)0x7a75, (q15_t)0xdac0, (q15_t)0x7a73, (q15_t)0xdaba, (q15_t)0x7a72, (q15_t)0xdab4, (q15_t)0x7a70, (q15_t)0xdaae, + (q15_t)0x7a6e, (q15_t)0xdaa8, (q15_t)0x7a6c, (q15_t)0xdaa2, (q15_t)0x7a6a, (q15_t)0xda9c, (q15_t)0x7a68, (q15_t)0xda96, + (q15_t)0x7a67, (q15_t)0xda90, (q15_t)0x7a65, (q15_t)0xda8a, (q15_t)0x7a63, (q15_t)0xda84, (q15_t)0x7a61, (q15_t)0xda7e, + (q15_t)0x7a5f, (q15_t)0xda78, (q15_t)0x7a5d, (q15_t)0xda72, (q15_t)0x7a5c, (q15_t)0xda6c, (q15_t)0x7a5a, (q15_t)0xda66, + (q15_t)0x7a58, (q15_t)0xda60, (q15_t)0x7a56, (q15_t)0xda5a, (q15_t)0x7a54, (q15_t)0xda54, (q15_t)0x7a52, (q15_t)0xda4e, + (q15_t)0x7a50, (q15_t)0xda48, (q15_t)0x7a4f, (q15_t)0xda42, (q15_t)0x7a4d, (q15_t)0xda3c, (q15_t)0x7a4b, (q15_t)0xda36, + (q15_t)0x7a49, (q15_t)0xda30, (q15_t)0x7a47, (q15_t)0xda2a, (q15_t)0x7a45, (q15_t)0xda24, (q15_t)0x7a43, (q15_t)0xda1e, + (q15_t)0x7a42, (q15_t)0xda18, (q15_t)0x7a40, (q15_t)0xda12, (q15_t)0x7a3e, (q15_t)0xda0c, (q15_t)0x7a3c, (q15_t)0xda06, + (q15_t)0x7a3a, (q15_t)0xda00, (q15_t)0x7a38, (q15_t)0xd9fa, (q15_t)0x7a36, (q15_t)0xd9f4, (q15_t)0x7a35, (q15_t)0xd9ee, + (q15_t)0x7a33, (q15_t)0xd9e8, (q15_t)0x7a31, (q15_t)0xd9e2, (q15_t)0x7a2f, (q15_t)0xd9dc, (q15_t)0x7a2d, (q15_t)0xd9d6, + (q15_t)0x7a2b, (q15_t)0xd9d0, (q15_t)0x7a29, (q15_t)0xd9ca, (q15_t)0x7a27, (q15_t)0xd9c4, (q15_t)0x7a26, (q15_t)0xd9be, + (q15_t)0x7a24, (q15_t)0xd9b8, (q15_t)0x7a22, (q15_t)0xd9b2, (q15_t)0x7a20, (q15_t)0xd9ac, (q15_t)0x7a1e, (q15_t)0xd9a6, + (q15_t)0x7a1c, (q15_t)0xd9a0, (q15_t)0x7a1a, (q15_t)0xd99a, (q15_t)0x7a18, (q15_t)0xd994, (q15_t)0x7a16, (q15_t)0xd98e, + (q15_t)0x7a15, (q15_t)0xd988, (q15_t)0x7a13, (q15_t)0xd982, (q15_t)0x7a11, (q15_t)0xd97c, (q15_t)0x7a0f, (q15_t)0xd976, + (q15_t)0x7a0d, (q15_t)0xd970, (q15_t)0x7a0b, (q15_t)0xd96a, (q15_t)0x7a09, (q15_t)0xd964, (q15_t)0x7a07, (q15_t)0xd95e, + (q15_t)0x7a05, (q15_t)0xd958, (q15_t)0x7a04, (q15_t)0xd952, (q15_t)0x7a02, (q15_t)0xd94c, (q15_t)0x7a00, (q15_t)0xd946, + (q15_t)0x79fe, (q15_t)0xd940, (q15_t)0x79fc, (q15_t)0xd93a, (q15_t)0x79fa, (q15_t)0xd934, (q15_t)0x79f8, (q15_t)0xd92e, + (q15_t)0x79f6, (q15_t)0xd928, (q15_t)0x79f4, (q15_t)0xd922, (q15_t)0x79f2, (q15_t)0xd91c, (q15_t)0x79f0, (q15_t)0xd917, + (q15_t)0x79ef, (q15_t)0xd911, (q15_t)0x79ed, (q15_t)0xd90b, (q15_t)0x79eb, (q15_t)0xd905, (q15_t)0x79e9, (q15_t)0xd8ff, + (q15_t)0x79e7, (q15_t)0xd8f9, (q15_t)0x79e5, (q15_t)0xd8f3, (q15_t)0x79e3, (q15_t)0xd8ed, (q15_t)0x79e1, (q15_t)0xd8e7, + (q15_t)0x79df, (q15_t)0xd8e1, (q15_t)0x79dd, (q15_t)0xd8db, (q15_t)0x79db, (q15_t)0xd8d5, (q15_t)0x79d9, (q15_t)0xd8cf, + (q15_t)0x79d8, (q15_t)0xd8c9, (q15_t)0x79d6, (q15_t)0xd8c3, (q15_t)0x79d4, (q15_t)0xd8bd, (q15_t)0x79d2, (q15_t)0xd8b7, + (q15_t)0x79d0, (q15_t)0xd8b1, (q15_t)0x79ce, (q15_t)0xd8ab, (q15_t)0x79cc, (q15_t)0xd8a5, (q15_t)0x79ca, (q15_t)0xd89f, + (q15_t)0x79c8, (q15_t)0xd899, (q15_t)0x79c6, (q15_t)0xd893, (q15_t)0x79c4, (q15_t)0xd88d, (q15_t)0x79c2, (q15_t)0xd887, + (q15_t)0x79c0, (q15_t)0xd881, (q15_t)0x79be, (q15_t)0xd87b, (q15_t)0x79bc, (q15_t)0xd875, (q15_t)0x79bb, (q15_t)0xd86f, + (q15_t)0x79b9, (q15_t)0xd869, (q15_t)0x79b7, (q15_t)0xd863, (q15_t)0x79b5, (q15_t)0xd85d, (q15_t)0x79b3, (q15_t)0xd857, + (q15_t)0x79b1, (q15_t)0xd851, (q15_t)0x79af, (q15_t)0xd84b, (q15_t)0x79ad, (q15_t)0xd845, (q15_t)0x79ab, (q15_t)0xd83f, + (q15_t)0x79a9, (q15_t)0xd839, (q15_t)0x79a7, (q15_t)0xd833, (q15_t)0x79a5, (q15_t)0xd82d, (q15_t)0x79a3, (q15_t)0xd827, + (q15_t)0x79a1, (q15_t)0xd821, (q15_t)0x799f, (q15_t)0xd81b, (q15_t)0x799d, (q15_t)0xd815, (q15_t)0x799b, (q15_t)0xd80f, + (q15_t)0x7999, (q15_t)0xd80a, (q15_t)0x7997, (q15_t)0xd804, (q15_t)0x7995, (q15_t)0xd7fe, (q15_t)0x7993, (q15_t)0xd7f8, + (q15_t)0x7992, (q15_t)0xd7f2, (q15_t)0x7990, (q15_t)0xd7ec, (q15_t)0x798e, (q15_t)0xd7e6, (q15_t)0x798c, (q15_t)0xd7e0, + (q15_t)0x798a, (q15_t)0xd7da, (q15_t)0x7988, (q15_t)0xd7d4, (q15_t)0x7986, (q15_t)0xd7ce, (q15_t)0x7984, (q15_t)0xd7c8, + (q15_t)0x7982, (q15_t)0xd7c2, (q15_t)0x7980, (q15_t)0xd7bc, (q15_t)0x797e, (q15_t)0xd7b6, (q15_t)0x797c, (q15_t)0xd7b0, + (q15_t)0x797a, (q15_t)0xd7aa, (q15_t)0x7978, (q15_t)0xd7a4, (q15_t)0x7976, (q15_t)0xd79e, (q15_t)0x7974, (q15_t)0xd798, + (q15_t)0x7972, (q15_t)0xd792, (q15_t)0x7970, (q15_t)0xd78c, (q15_t)0x796e, (q15_t)0xd786, (q15_t)0x796c, (q15_t)0xd780, + (q15_t)0x796a, (q15_t)0xd77a, (q15_t)0x7968, (q15_t)0xd774, (q15_t)0x7966, (q15_t)0xd76e, (q15_t)0x7964, (q15_t)0xd768, + (q15_t)0x7962, (q15_t)0xd763, (q15_t)0x7960, (q15_t)0xd75d, (q15_t)0x795e, (q15_t)0xd757, (q15_t)0x795c, (q15_t)0xd751, + (q15_t)0x795a, (q15_t)0xd74b, (q15_t)0x7958, (q15_t)0xd745, (q15_t)0x7956, (q15_t)0xd73f, (q15_t)0x7954, (q15_t)0xd739, + (q15_t)0x7952, (q15_t)0xd733, (q15_t)0x7950, (q15_t)0xd72d, (q15_t)0x794e, (q15_t)0xd727, (q15_t)0x794c, (q15_t)0xd721, + (q15_t)0x794a, (q15_t)0xd71b, (q15_t)0x7948, (q15_t)0xd715, (q15_t)0x7946, (q15_t)0xd70f, (q15_t)0x7944, (q15_t)0xd709, + (q15_t)0x7942, (q15_t)0xd703, (q15_t)0x7940, (q15_t)0xd6fd, (q15_t)0x793e, (q15_t)0xd6f7, (q15_t)0x793c, (q15_t)0xd6f1, + (q15_t)0x793a, (q15_t)0xd6eb, (q15_t)0x7938, (q15_t)0xd6e5, (q15_t)0x7936, (q15_t)0xd6e0, (q15_t)0x7934, (q15_t)0xd6da, + (q15_t)0x7932, (q15_t)0xd6d4, (q15_t)0x7930, (q15_t)0xd6ce, (q15_t)0x792e, (q15_t)0xd6c8, (q15_t)0x792c, (q15_t)0xd6c2, + (q15_t)0x792a, (q15_t)0xd6bc, (q15_t)0x7928, (q15_t)0xd6b6, (q15_t)0x7926, (q15_t)0xd6b0, (q15_t)0x7924, (q15_t)0xd6aa, + (q15_t)0x7922, (q15_t)0xd6a4, (q15_t)0x7920, (q15_t)0xd69e, (q15_t)0x791e, (q15_t)0xd698, (q15_t)0x791c, (q15_t)0xd692, + (q15_t)0x7919, (q15_t)0xd68c, (q15_t)0x7917, (q15_t)0xd686, (q15_t)0x7915, (q15_t)0xd680, (q15_t)0x7913, (q15_t)0xd67a, + (q15_t)0x7911, (q15_t)0xd675, (q15_t)0x790f, (q15_t)0xd66f, (q15_t)0x790d, (q15_t)0xd669, (q15_t)0x790b, (q15_t)0xd663, + (q15_t)0x7909, (q15_t)0xd65d, (q15_t)0x7907, (q15_t)0xd657, (q15_t)0x7905, (q15_t)0xd651, (q15_t)0x7903, (q15_t)0xd64b, + (q15_t)0x7901, (q15_t)0xd645, (q15_t)0x78ff, (q15_t)0xd63f, (q15_t)0x78fd, (q15_t)0xd639, (q15_t)0x78fb, (q15_t)0xd633, + (q15_t)0x78f9, (q15_t)0xd62d, (q15_t)0x78f7, (q15_t)0xd627, (q15_t)0x78f5, (q15_t)0xd621, (q15_t)0x78f3, (q15_t)0xd61b, + (q15_t)0x78f1, (q15_t)0xd615, (q15_t)0x78ee, (q15_t)0xd610, (q15_t)0x78ec, (q15_t)0xd60a, (q15_t)0x78ea, (q15_t)0xd604, + (q15_t)0x78e8, (q15_t)0xd5fe, (q15_t)0x78e6, (q15_t)0xd5f8, (q15_t)0x78e4, (q15_t)0xd5f2, (q15_t)0x78e2, (q15_t)0xd5ec, + (q15_t)0x78e0, (q15_t)0xd5e6, (q15_t)0x78de, (q15_t)0xd5e0, (q15_t)0x78dc, (q15_t)0xd5da, (q15_t)0x78da, (q15_t)0xd5d4, + (q15_t)0x78d8, (q15_t)0xd5ce, (q15_t)0x78d6, (q15_t)0xd5c8, (q15_t)0x78d4, (q15_t)0xd5c2, (q15_t)0x78d2, (q15_t)0xd5bc, + (q15_t)0x78cf, (q15_t)0xd5b7, (q15_t)0x78cd, (q15_t)0xd5b1, (q15_t)0x78cb, (q15_t)0xd5ab, (q15_t)0x78c9, (q15_t)0xd5a5, + (q15_t)0x78c7, (q15_t)0xd59f, (q15_t)0x78c5, (q15_t)0xd599, (q15_t)0x78c3, (q15_t)0xd593, (q15_t)0x78c1, (q15_t)0xd58d, + (q15_t)0x78bf, (q15_t)0xd587, (q15_t)0x78bd, (q15_t)0xd581, (q15_t)0x78bb, (q15_t)0xd57b, (q15_t)0x78b9, (q15_t)0xd575, + (q15_t)0x78b6, (q15_t)0xd56f, (q15_t)0x78b4, (q15_t)0xd569, (q15_t)0x78b2, (q15_t)0xd564, (q15_t)0x78b0, (q15_t)0xd55e, + (q15_t)0x78ae, (q15_t)0xd558, (q15_t)0x78ac, (q15_t)0xd552, (q15_t)0x78aa, (q15_t)0xd54c, (q15_t)0x78a8, (q15_t)0xd546, + (q15_t)0x78a6, (q15_t)0xd540, (q15_t)0x78a4, (q15_t)0xd53a, (q15_t)0x78a2, (q15_t)0xd534, (q15_t)0x789f, (q15_t)0xd52e, + (q15_t)0x789d, (q15_t)0xd528, (q15_t)0x789b, (q15_t)0xd522, (q15_t)0x7899, (q15_t)0xd51c, (q15_t)0x7897, (q15_t)0xd517, + (q15_t)0x7895, (q15_t)0xd511, (q15_t)0x7893, (q15_t)0xd50b, (q15_t)0x7891, (q15_t)0xd505, (q15_t)0x788f, (q15_t)0xd4ff, + (q15_t)0x788c, (q15_t)0xd4f9, (q15_t)0x788a, (q15_t)0xd4f3, (q15_t)0x7888, (q15_t)0xd4ed, (q15_t)0x7886, (q15_t)0xd4e7, + (q15_t)0x7884, (q15_t)0xd4e1, (q15_t)0x7882, (q15_t)0xd4db, (q15_t)0x7880, (q15_t)0xd4d5, (q15_t)0x787e, (q15_t)0xd4d0, + (q15_t)0x787c, (q15_t)0xd4ca, (q15_t)0x7879, (q15_t)0xd4c4, (q15_t)0x7877, (q15_t)0xd4be, (q15_t)0x7875, (q15_t)0xd4b8, + (q15_t)0x7873, (q15_t)0xd4b2, (q15_t)0x7871, (q15_t)0xd4ac, (q15_t)0x786f, (q15_t)0xd4a6, (q15_t)0x786d, (q15_t)0xd4a0, + (q15_t)0x786b, (q15_t)0xd49a, (q15_t)0x7868, (q15_t)0xd494, (q15_t)0x7866, (q15_t)0xd48f, (q15_t)0x7864, (q15_t)0xd489, + (q15_t)0x7862, (q15_t)0xd483, (q15_t)0x7860, (q15_t)0xd47d, (q15_t)0x785e, (q15_t)0xd477, (q15_t)0x785c, (q15_t)0xd471, + (q15_t)0x7859, (q15_t)0xd46b, (q15_t)0x7857, (q15_t)0xd465, (q15_t)0x7855, (q15_t)0xd45f, (q15_t)0x7853, (q15_t)0xd459, + (q15_t)0x7851, (q15_t)0xd453, (q15_t)0x784f, (q15_t)0xd44e, (q15_t)0x784d, (q15_t)0xd448, (q15_t)0x784a, (q15_t)0xd442, + (q15_t)0x7848, (q15_t)0xd43c, (q15_t)0x7846, (q15_t)0xd436, (q15_t)0x7844, (q15_t)0xd430, (q15_t)0x7842, (q15_t)0xd42a, + (q15_t)0x7840, (q15_t)0xd424, (q15_t)0x783e, (q15_t)0xd41e, (q15_t)0x783b, (q15_t)0xd418, (q15_t)0x7839, (q15_t)0xd412, + (q15_t)0x7837, (q15_t)0xd40d, (q15_t)0x7835, (q15_t)0xd407, (q15_t)0x7833, (q15_t)0xd401, (q15_t)0x7831, (q15_t)0xd3fb, + (q15_t)0x782e, (q15_t)0xd3f5, (q15_t)0x782c, (q15_t)0xd3ef, (q15_t)0x782a, (q15_t)0xd3e9, (q15_t)0x7828, (q15_t)0xd3e3, + (q15_t)0x7826, (q15_t)0xd3dd, (q15_t)0x7824, (q15_t)0xd3d7, (q15_t)0x7821, (q15_t)0xd3d2, (q15_t)0x781f, (q15_t)0xd3cc, + (q15_t)0x781d, (q15_t)0xd3c6, (q15_t)0x781b, (q15_t)0xd3c0, (q15_t)0x7819, (q15_t)0xd3ba, (q15_t)0x7817, (q15_t)0xd3b4, + (q15_t)0x7814, (q15_t)0xd3ae, (q15_t)0x7812, (q15_t)0xd3a8, (q15_t)0x7810, (q15_t)0xd3a2, (q15_t)0x780e, (q15_t)0xd39d, + (q15_t)0x780c, (q15_t)0xd397, (q15_t)0x780a, (q15_t)0xd391, (q15_t)0x7807, (q15_t)0xd38b, (q15_t)0x7805, (q15_t)0xd385, + (q15_t)0x7803, (q15_t)0xd37f, (q15_t)0x7801, (q15_t)0xd379, (q15_t)0x77ff, (q15_t)0xd373, (q15_t)0x77fc, (q15_t)0xd36d, + (q15_t)0x77fa, (q15_t)0xd368, (q15_t)0x77f8, (q15_t)0xd362, (q15_t)0x77f6, (q15_t)0xd35c, (q15_t)0x77f4, (q15_t)0xd356, + (q15_t)0x77f1, (q15_t)0xd350, (q15_t)0x77ef, (q15_t)0xd34a, (q15_t)0x77ed, (q15_t)0xd344, (q15_t)0x77eb, (q15_t)0xd33e, + (q15_t)0x77e9, (q15_t)0xd338, (q15_t)0x77e6, (q15_t)0xd333, (q15_t)0x77e4, (q15_t)0xd32d, (q15_t)0x77e2, (q15_t)0xd327, + (q15_t)0x77e0, (q15_t)0xd321, (q15_t)0x77de, (q15_t)0xd31b, (q15_t)0x77db, (q15_t)0xd315, (q15_t)0x77d9, (q15_t)0xd30f, + (q15_t)0x77d7, (q15_t)0xd309, (q15_t)0x77d5, (q15_t)0xd303, (q15_t)0x77d3, (q15_t)0xd2fe, (q15_t)0x77d0, (q15_t)0xd2f8, + (q15_t)0x77ce, (q15_t)0xd2f2, (q15_t)0x77cc, (q15_t)0xd2ec, (q15_t)0x77ca, (q15_t)0xd2e6, (q15_t)0x77c8, (q15_t)0xd2e0, + (q15_t)0x77c5, (q15_t)0xd2da, (q15_t)0x77c3, (q15_t)0xd2d4, (q15_t)0x77c1, (q15_t)0xd2cf, (q15_t)0x77bf, (q15_t)0xd2c9, + (q15_t)0x77bc, (q15_t)0xd2c3, (q15_t)0x77ba, (q15_t)0xd2bd, (q15_t)0x77b8, (q15_t)0xd2b7, (q15_t)0x77b6, (q15_t)0xd2b1, + (q15_t)0x77b4, (q15_t)0xd2ab, (q15_t)0x77b1, (q15_t)0xd2a5, (q15_t)0x77af, (q15_t)0xd2a0, (q15_t)0x77ad, (q15_t)0xd29a, + (q15_t)0x77ab, (q15_t)0xd294, (q15_t)0x77a8, (q15_t)0xd28e, (q15_t)0x77a6, (q15_t)0xd288, (q15_t)0x77a4, (q15_t)0xd282, + (q15_t)0x77a2, (q15_t)0xd27c, (q15_t)0x77a0, (q15_t)0xd276, (q15_t)0x779d, (q15_t)0xd271, (q15_t)0x779b, (q15_t)0xd26b, + (q15_t)0x7799, (q15_t)0xd265, (q15_t)0x7797, (q15_t)0xd25f, (q15_t)0x7794, (q15_t)0xd259, (q15_t)0x7792, (q15_t)0xd253, + (q15_t)0x7790, (q15_t)0xd24d, (q15_t)0x778e, (q15_t)0xd247, (q15_t)0x778b, (q15_t)0xd242, (q15_t)0x7789, (q15_t)0xd23c, + (q15_t)0x7787, (q15_t)0xd236, (q15_t)0x7785, (q15_t)0xd230, (q15_t)0x7782, (q15_t)0xd22a, (q15_t)0x7780, (q15_t)0xd224, + (q15_t)0x777e, (q15_t)0xd21e, (q15_t)0x777c, (q15_t)0xd219, (q15_t)0x7779, (q15_t)0xd213, (q15_t)0x7777, (q15_t)0xd20d, + (q15_t)0x7775, (q15_t)0xd207, (q15_t)0x7773, (q15_t)0xd201, (q15_t)0x7770, (q15_t)0xd1fb, (q15_t)0x776e, (q15_t)0xd1f5, + (q15_t)0x776c, (q15_t)0xd1ef, (q15_t)0x776a, (q15_t)0xd1ea, (q15_t)0x7767, (q15_t)0xd1e4, (q15_t)0x7765, (q15_t)0xd1de, + (q15_t)0x7763, (q15_t)0xd1d8, (q15_t)0x7760, (q15_t)0xd1d2, (q15_t)0x775e, (q15_t)0xd1cc, (q15_t)0x775c, (q15_t)0xd1c6, + (q15_t)0x775a, (q15_t)0xd1c1, (q15_t)0x7757, (q15_t)0xd1bb, (q15_t)0x7755, (q15_t)0xd1b5, (q15_t)0x7753, (q15_t)0xd1af, + (q15_t)0x7751, (q15_t)0xd1a9, (q15_t)0x774e, (q15_t)0xd1a3, (q15_t)0x774c, (q15_t)0xd19d, (q15_t)0x774a, (q15_t)0xd198, + (q15_t)0x7747, (q15_t)0xd192, (q15_t)0x7745, (q15_t)0xd18c, (q15_t)0x7743, (q15_t)0xd186, (q15_t)0x7741, (q15_t)0xd180, + (q15_t)0x773e, (q15_t)0xd17a, (q15_t)0x773c, (q15_t)0xd174, (q15_t)0x773a, (q15_t)0xd16f, (q15_t)0x7738, (q15_t)0xd169, + (q15_t)0x7735, (q15_t)0xd163, (q15_t)0x7733, (q15_t)0xd15d, (q15_t)0x7731, (q15_t)0xd157, (q15_t)0x772e, (q15_t)0xd151, + (q15_t)0x772c, (q15_t)0xd14b, (q15_t)0x772a, (q15_t)0xd146, (q15_t)0x7727, (q15_t)0xd140, (q15_t)0x7725, (q15_t)0xd13a, + (q15_t)0x7723, (q15_t)0xd134, (q15_t)0x7721, (q15_t)0xd12e, (q15_t)0x771e, (q15_t)0xd128, (q15_t)0x771c, (q15_t)0xd123, + (q15_t)0x771a, (q15_t)0xd11d, (q15_t)0x7717, (q15_t)0xd117, (q15_t)0x7715, (q15_t)0xd111, (q15_t)0x7713, (q15_t)0xd10b, + (q15_t)0x7710, (q15_t)0xd105, (q15_t)0x770e, (q15_t)0xd0ff, (q15_t)0x770c, (q15_t)0xd0fa, (q15_t)0x770a, (q15_t)0xd0f4, + (q15_t)0x7707, (q15_t)0xd0ee, (q15_t)0x7705, (q15_t)0xd0e8, (q15_t)0x7703, (q15_t)0xd0e2, (q15_t)0x7700, (q15_t)0xd0dc, + (q15_t)0x76fe, (q15_t)0xd0d7, (q15_t)0x76fc, (q15_t)0xd0d1, (q15_t)0x76f9, (q15_t)0xd0cb, (q15_t)0x76f7, (q15_t)0xd0c5, + (q15_t)0x76f5, (q15_t)0xd0bf, (q15_t)0x76f2, (q15_t)0xd0b9, (q15_t)0x76f0, (q15_t)0xd0b4, (q15_t)0x76ee, (q15_t)0xd0ae, + (q15_t)0x76eb, (q15_t)0xd0a8, (q15_t)0x76e9, (q15_t)0xd0a2, (q15_t)0x76e7, (q15_t)0xd09c, (q15_t)0x76e4, (q15_t)0xd096, + (q15_t)0x76e2, (q15_t)0xd091, (q15_t)0x76e0, (q15_t)0xd08b, (q15_t)0x76dd, (q15_t)0xd085, (q15_t)0x76db, (q15_t)0xd07f, + (q15_t)0x76d9, (q15_t)0xd079, (q15_t)0x76d6, (q15_t)0xd073, (q15_t)0x76d4, (q15_t)0xd06e, (q15_t)0x76d2, (q15_t)0xd068, + (q15_t)0x76cf, (q15_t)0xd062, (q15_t)0x76cd, (q15_t)0xd05c, (q15_t)0x76cb, (q15_t)0xd056, (q15_t)0x76c8, (q15_t)0xd050, + (q15_t)0x76c6, (q15_t)0xd04b, (q15_t)0x76c4, (q15_t)0xd045, (q15_t)0x76c1, (q15_t)0xd03f, (q15_t)0x76bf, (q15_t)0xd039, + (q15_t)0x76bd, (q15_t)0xd033, (q15_t)0x76ba, (q15_t)0xd02d, (q15_t)0x76b8, (q15_t)0xd028, (q15_t)0x76b6, (q15_t)0xd022, + (q15_t)0x76b3, (q15_t)0xd01c, (q15_t)0x76b1, (q15_t)0xd016, (q15_t)0x76af, (q15_t)0xd010, (q15_t)0x76ac, (q15_t)0xd00a, + (q15_t)0x76aa, (q15_t)0xd005, (q15_t)0x76a8, (q15_t)0xcfff, (q15_t)0x76a5, (q15_t)0xcff9, (q15_t)0x76a3, (q15_t)0xcff3, + (q15_t)0x76a0, (q15_t)0xcfed, (q15_t)0x769e, (q15_t)0xcfe7, (q15_t)0x769c, (q15_t)0xcfe2, (q15_t)0x7699, (q15_t)0xcfdc, + (q15_t)0x7697, (q15_t)0xcfd6, (q15_t)0x7695, (q15_t)0xcfd0, (q15_t)0x7692, (q15_t)0xcfca, (q15_t)0x7690, (q15_t)0xcfc5, + (q15_t)0x768e, (q15_t)0xcfbf, (q15_t)0x768b, (q15_t)0xcfb9, (q15_t)0x7689, (q15_t)0xcfb3, (q15_t)0x7686, (q15_t)0xcfad, + (q15_t)0x7684, (q15_t)0xcfa7, (q15_t)0x7682, (q15_t)0xcfa2, (q15_t)0x767f, (q15_t)0xcf9c, (q15_t)0x767d, (q15_t)0xcf96, + (q15_t)0x767b, (q15_t)0xcf90, (q15_t)0x7678, (q15_t)0xcf8a, (q15_t)0x7676, (q15_t)0xcf85, (q15_t)0x7673, (q15_t)0xcf7f, + (q15_t)0x7671, (q15_t)0xcf79, (q15_t)0x766f, (q15_t)0xcf73, (q15_t)0x766c, (q15_t)0xcf6d, (q15_t)0x766a, (q15_t)0xcf67, + (q15_t)0x7668, (q15_t)0xcf62, (q15_t)0x7665, (q15_t)0xcf5c, (q15_t)0x7663, (q15_t)0xcf56, (q15_t)0x7660, (q15_t)0xcf50, + (q15_t)0x765e, (q15_t)0xcf4a, (q15_t)0x765c, (q15_t)0xcf45, (q15_t)0x7659, (q15_t)0xcf3f, (q15_t)0x7657, (q15_t)0xcf39, + (q15_t)0x7654, (q15_t)0xcf33, (q15_t)0x7652, (q15_t)0xcf2d, (q15_t)0x7650, (q15_t)0xcf28, (q15_t)0x764d, (q15_t)0xcf22, + (q15_t)0x764b, (q15_t)0xcf1c, (q15_t)0x7648, (q15_t)0xcf16, (q15_t)0x7646, (q15_t)0xcf10, (q15_t)0x7644, (q15_t)0xcf0b, + (q15_t)0x7641, (q15_t)0xcf05, (q15_t)0x763f, (q15_t)0xceff, (q15_t)0x763c, (q15_t)0xcef9, (q15_t)0x763a, (q15_t)0xcef3, + (q15_t)0x7638, (q15_t)0xceee, (q15_t)0x7635, (q15_t)0xcee8, (q15_t)0x7633, (q15_t)0xcee2, (q15_t)0x7630, (q15_t)0xcedc, + (q15_t)0x762e, (q15_t)0xced6, (q15_t)0x762b, (q15_t)0xced1, (q15_t)0x7629, (q15_t)0xcecb, (q15_t)0x7627, (q15_t)0xcec5, + (q15_t)0x7624, (q15_t)0xcebf, (q15_t)0x7622, (q15_t)0xceb9, (q15_t)0x761f, (q15_t)0xceb4, (q15_t)0x761d, (q15_t)0xceae, + (q15_t)0x761b, (q15_t)0xcea8, (q15_t)0x7618, (q15_t)0xcea2, (q15_t)0x7616, (q15_t)0xce9c, (q15_t)0x7613, (q15_t)0xce97, + (q15_t)0x7611, (q15_t)0xce91, (q15_t)0x760e, (q15_t)0xce8b, (q15_t)0x760c, (q15_t)0xce85, (q15_t)0x760a, (q15_t)0xce7f, + (q15_t)0x7607, (q15_t)0xce7a, (q15_t)0x7605, (q15_t)0xce74, (q15_t)0x7602, (q15_t)0xce6e, (q15_t)0x7600, (q15_t)0xce68, + (q15_t)0x75fd, (q15_t)0xce62, (q15_t)0x75fb, (q15_t)0xce5d, (q15_t)0x75f9, (q15_t)0xce57, (q15_t)0x75f6, (q15_t)0xce51, + (q15_t)0x75f4, (q15_t)0xce4b, (q15_t)0x75f1, (q15_t)0xce45, (q15_t)0x75ef, (q15_t)0xce40, (q15_t)0x75ec, (q15_t)0xce3a, + (q15_t)0x75ea, (q15_t)0xce34, (q15_t)0x75e7, (q15_t)0xce2e, (q15_t)0x75e5, (q15_t)0xce28, (q15_t)0x75e3, (q15_t)0xce23, + (q15_t)0x75e0, (q15_t)0xce1d, (q15_t)0x75de, (q15_t)0xce17, (q15_t)0x75db, (q15_t)0xce11, (q15_t)0x75d9, (q15_t)0xce0c, + (q15_t)0x75d6, (q15_t)0xce06, (q15_t)0x75d4, (q15_t)0xce00, (q15_t)0x75d1, (q15_t)0xcdfa, (q15_t)0x75cf, (q15_t)0xcdf4, + (q15_t)0x75cc, (q15_t)0xcdef, (q15_t)0x75ca, (q15_t)0xcde9, (q15_t)0x75c8, (q15_t)0xcde3, (q15_t)0x75c5, (q15_t)0xcddd, + (q15_t)0x75c3, (q15_t)0xcdd8, (q15_t)0x75c0, (q15_t)0xcdd2, (q15_t)0x75be, (q15_t)0xcdcc, (q15_t)0x75bb, (q15_t)0xcdc6, + (q15_t)0x75b9, (q15_t)0xcdc0, (q15_t)0x75b6, (q15_t)0xcdbb, (q15_t)0x75b4, (q15_t)0xcdb5, (q15_t)0x75b1, (q15_t)0xcdaf, + (q15_t)0x75af, (q15_t)0xcda9, (q15_t)0x75ac, (q15_t)0xcda3, (q15_t)0x75aa, (q15_t)0xcd9e, (q15_t)0x75a7, (q15_t)0xcd98, + (q15_t)0x75a5, (q15_t)0xcd92, (q15_t)0x75a3, (q15_t)0xcd8c, (q15_t)0x75a0, (q15_t)0xcd87, (q15_t)0x759e, (q15_t)0xcd81, + (q15_t)0x759b, (q15_t)0xcd7b, (q15_t)0x7599, (q15_t)0xcd75, (q15_t)0x7596, (q15_t)0xcd70, (q15_t)0x7594, (q15_t)0xcd6a, + (q15_t)0x7591, (q15_t)0xcd64, (q15_t)0x758f, (q15_t)0xcd5e, (q15_t)0x758c, (q15_t)0xcd58, (q15_t)0x758a, (q15_t)0xcd53, + (q15_t)0x7587, (q15_t)0xcd4d, (q15_t)0x7585, (q15_t)0xcd47, (q15_t)0x7582, (q15_t)0xcd41, (q15_t)0x7580, (q15_t)0xcd3c, + (q15_t)0x757d, (q15_t)0xcd36, (q15_t)0x757b, (q15_t)0xcd30, (q15_t)0x7578, (q15_t)0xcd2a, (q15_t)0x7576, (q15_t)0xcd25, + (q15_t)0x7573, (q15_t)0xcd1f, (q15_t)0x7571, (q15_t)0xcd19, (q15_t)0x756e, (q15_t)0xcd13, (q15_t)0x756c, (q15_t)0xcd0d, + (q15_t)0x7569, (q15_t)0xcd08, (q15_t)0x7567, (q15_t)0xcd02, (q15_t)0x7564, (q15_t)0xccfc, (q15_t)0x7562, (q15_t)0xccf6, + (q15_t)0x755f, (q15_t)0xccf1, (q15_t)0x755d, (q15_t)0xcceb, (q15_t)0x755a, (q15_t)0xcce5, (q15_t)0x7558, (q15_t)0xccdf, + (q15_t)0x7555, (q15_t)0xccda, (q15_t)0x7553, (q15_t)0xccd4, (q15_t)0x7550, (q15_t)0xccce, (q15_t)0x754e, (q15_t)0xccc8, + (q15_t)0x754b, (q15_t)0xccc3, (q15_t)0x7549, (q15_t)0xccbd, (q15_t)0x7546, (q15_t)0xccb7, (q15_t)0x7544, (q15_t)0xccb1, + (q15_t)0x7541, (q15_t)0xccac, (q15_t)0x753f, (q15_t)0xcca6, (q15_t)0x753c, (q15_t)0xcca0, (q15_t)0x753a, (q15_t)0xcc9a, + (q15_t)0x7537, (q15_t)0xcc95, (q15_t)0x7535, (q15_t)0xcc8f, (q15_t)0x7532, (q15_t)0xcc89, (q15_t)0x752f, (q15_t)0xcc83, + (q15_t)0x752d, (q15_t)0xcc7e, (q15_t)0x752a, (q15_t)0xcc78, (q15_t)0x7528, (q15_t)0xcc72, (q15_t)0x7525, (q15_t)0xcc6c, + (q15_t)0x7523, (q15_t)0xcc67, (q15_t)0x7520, (q15_t)0xcc61, (q15_t)0x751e, (q15_t)0xcc5b, (q15_t)0x751b, (q15_t)0xcc55, + (q15_t)0x7519, (q15_t)0xcc50, (q15_t)0x7516, (q15_t)0xcc4a, (q15_t)0x7514, (q15_t)0xcc44, (q15_t)0x7511, (q15_t)0xcc3e, + (q15_t)0x750f, (q15_t)0xcc39, (q15_t)0x750c, (q15_t)0xcc33, (q15_t)0x7509, (q15_t)0xcc2d, (q15_t)0x7507, (q15_t)0xcc27, + (q15_t)0x7504, (q15_t)0xcc22, (q15_t)0x7502, (q15_t)0xcc1c, (q15_t)0x74ff, (q15_t)0xcc16, (q15_t)0x74fd, (q15_t)0xcc10, + (q15_t)0x74fa, (q15_t)0xcc0b, (q15_t)0x74f8, (q15_t)0xcc05, (q15_t)0x74f5, (q15_t)0xcbff, (q15_t)0x74f2, (q15_t)0xcbf9, + (q15_t)0x74f0, (q15_t)0xcbf4, (q15_t)0x74ed, (q15_t)0xcbee, (q15_t)0x74eb, (q15_t)0xcbe8, (q15_t)0x74e8, (q15_t)0xcbe2, + (q15_t)0x74e6, (q15_t)0xcbdd, (q15_t)0x74e3, (q15_t)0xcbd7, (q15_t)0x74e1, (q15_t)0xcbd1, (q15_t)0x74de, (q15_t)0xcbcb, + (q15_t)0x74db, (q15_t)0xcbc6, (q15_t)0x74d9, (q15_t)0xcbc0, (q15_t)0x74d6, (q15_t)0xcbba, (q15_t)0x74d4, (q15_t)0xcbb5, + (q15_t)0x74d1, (q15_t)0xcbaf, (q15_t)0x74cf, (q15_t)0xcba9, (q15_t)0x74cc, (q15_t)0xcba3, (q15_t)0x74c9, (q15_t)0xcb9e, + (q15_t)0x74c7, (q15_t)0xcb98, (q15_t)0x74c4, (q15_t)0xcb92, (q15_t)0x74c2, (q15_t)0xcb8c, (q15_t)0x74bf, (q15_t)0xcb87, + (q15_t)0x74bd, (q15_t)0xcb81, (q15_t)0x74ba, (q15_t)0xcb7b, (q15_t)0x74b7, (q15_t)0xcb75, (q15_t)0x74b5, (q15_t)0xcb70, + (q15_t)0x74b2, (q15_t)0xcb6a, (q15_t)0x74b0, (q15_t)0xcb64, (q15_t)0x74ad, (q15_t)0xcb5f, (q15_t)0x74ab, (q15_t)0xcb59, + (q15_t)0x74a8, (q15_t)0xcb53, (q15_t)0x74a5, (q15_t)0xcb4d, (q15_t)0x74a3, (q15_t)0xcb48, (q15_t)0x74a0, (q15_t)0xcb42, + (q15_t)0x749e, (q15_t)0xcb3c, (q15_t)0x749b, (q15_t)0xcb36, (q15_t)0x7498, (q15_t)0xcb31, (q15_t)0x7496, (q15_t)0xcb2b, + (q15_t)0x7493, (q15_t)0xcb25, (q15_t)0x7491, (q15_t)0xcb20, (q15_t)0x748e, (q15_t)0xcb1a, (q15_t)0x748b, (q15_t)0xcb14, + (q15_t)0x7489, (q15_t)0xcb0e, (q15_t)0x7486, (q15_t)0xcb09, (q15_t)0x7484, (q15_t)0xcb03, (q15_t)0x7481, (q15_t)0xcafd, + (q15_t)0x747e, (q15_t)0xcaf8, (q15_t)0x747c, (q15_t)0xcaf2, (q15_t)0x7479, (q15_t)0xcaec, (q15_t)0x7477, (q15_t)0xcae6, + (q15_t)0x7474, (q15_t)0xcae1, (q15_t)0x7471, (q15_t)0xcadb, (q15_t)0x746f, (q15_t)0xcad5, (q15_t)0x746c, (q15_t)0xcad0, + (q15_t)0x746a, (q15_t)0xcaca, (q15_t)0x7467, (q15_t)0xcac4, (q15_t)0x7464, (q15_t)0xcabe, (q15_t)0x7462, (q15_t)0xcab9, + (q15_t)0x745f, (q15_t)0xcab3, (q15_t)0x745c, (q15_t)0xcaad, (q15_t)0x745a, (q15_t)0xcaa8, (q15_t)0x7457, (q15_t)0xcaa2, + (q15_t)0x7455, (q15_t)0xca9c, (q15_t)0x7452, (q15_t)0xca96, (q15_t)0x744f, (q15_t)0xca91, (q15_t)0x744d, (q15_t)0xca8b, + (q15_t)0x744a, (q15_t)0xca85, (q15_t)0x7448, (q15_t)0xca80, (q15_t)0x7445, (q15_t)0xca7a, (q15_t)0x7442, (q15_t)0xca74, + (q15_t)0x7440, (q15_t)0xca6e, (q15_t)0x743d, (q15_t)0xca69, (q15_t)0x743a, (q15_t)0xca63, (q15_t)0x7438, (q15_t)0xca5d, + (q15_t)0x7435, (q15_t)0xca58, (q15_t)0x7432, (q15_t)0xca52, (q15_t)0x7430, (q15_t)0xca4c, (q15_t)0x742d, (q15_t)0xca46, + (q15_t)0x742b, (q15_t)0xca41, (q15_t)0x7428, (q15_t)0xca3b, (q15_t)0x7425, (q15_t)0xca35, (q15_t)0x7423, (q15_t)0xca30, + (q15_t)0x7420, (q15_t)0xca2a, (q15_t)0x741d, (q15_t)0xca24, (q15_t)0x741b, (q15_t)0xca1f, (q15_t)0x7418, (q15_t)0xca19, + (q15_t)0x7415, (q15_t)0xca13, (q15_t)0x7413, (q15_t)0xca0d, (q15_t)0x7410, (q15_t)0xca08, (q15_t)0x740d, (q15_t)0xca02, + (q15_t)0x740b, (q15_t)0xc9fc, (q15_t)0x7408, (q15_t)0xc9f7, (q15_t)0x7406, (q15_t)0xc9f1, (q15_t)0x7403, (q15_t)0xc9eb, + (q15_t)0x7400, (q15_t)0xc9e6, (q15_t)0x73fe, (q15_t)0xc9e0, (q15_t)0x73fb, (q15_t)0xc9da, (q15_t)0x73f8, (q15_t)0xc9d5, + (q15_t)0x73f6, (q15_t)0xc9cf, (q15_t)0x73f3, (q15_t)0xc9c9, (q15_t)0x73f0, (q15_t)0xc9c3, (q15_t)0x73ee, (q15_t)0xc9be, + (q15_t)0x73eb, (q15_t)0xc9b8, (q15_t)0x73e8, (q15_t)0xc9b2, (q15_t)0x73e6, (q15_t)0xc9ad, (q15_t)0x73e3, (q15_t)0xc9a7, + (q15_t)0x73e0, (q15_t)0xc9a1, (q15_t)0x73de, (q15_t)0xc99c, (q15_t)0x73db, (q15_t)0xc996, (q15_t)0x73d8, (q15_t)0xc990, + (q15_t)0x73d6, (q15_t)0xc98b, (q15_t)0x73d3, (q15_t)0xc985, (q15_t)0x73d0, (q15_t)0xc97f, (q15_t)0x73ce, (q15_t)0xc97a, + (q15_t)0x73cb, (q15_t)0xc974, (q15_t)0x73c8, (q15_t)0xc96e, (q15_t)0x73c6, (q15_t)0xc968, (q15_t)0x73c3, (q15_t)0xc963, + (q15_t)0x73c0, (q15_t)0xc95d, (q15_t)0x73bd, (q15_t)0xc957, (q15_t)0x73bb, (q15_t)0xc952, (q15_t)0x73b8, (q15_t)0xc94c, + (q15_t)0x73b5, (q15_t)0xc946, (q15_t)0x73b3, (q15_t)0xc941, (q15_t)0x73b0, (q15_t)0xc93b, (q15_t)0x73ad, (q15_t)0xc935, + (q15_t)0x73ab, (q15_t)0xc930, (q15_t)0x73a8, (q15_t)0xc92a, (q15_t)0x73a5, (q15_t)0xc924, (q15_t)0x73a3, (q15_t)0xc91f, + (q15_t)0x73a0, (q15_t)0xc919, (q15_t)0x739d, (q15_t)0xc913, (q15_t)0x739b, (q15_t)0xc90e, (q15_t)0x7398, (q15_t)0xc908, + (q15_t)0x7395, (q15_t)0xc902, (q15_t)0x7392, (q15_t)0xc8fd, (q15_t)0x7390, (q15_t)0xc8f7, (q15_t)0x738d, (q15_t)0xc8f1, + (q15_t)0x738a, (q15_t)0xc8ec, (q15_t)0x7388, (q15_t)0xc8e6, (q15_t)0x7385, (q15_t)0xc8e0, (q15_t)0x7382, (q15_t)0xc8db, + (q15_t)0x737f, (q15_t)0xc8d5, (q15_t)0x737d, (q15_t)0xc8cf, (q15_t)0x737a, (q15_t)0xc8ca, (q15_t)0x7377, (q15_t)0xc8c4, + (q15_t)0x7375, (q15_t)0xc8be, (q15_t)0x7372, (q15_t)0xc8b9, (q15_t)0x736f, (q15_t)0xc8b3, (q15_t)0x736c, (q15_t)0xc8ad, + (q15_t)0x736a, (q15_t)0xc8a8, (q15_t)0x7367, (q15_t)0xc8a2, (q15_t)0x7364, (q15_t)0xc89c, (q15_t)0x7362, (q15_t)0xc897, + (q15_t)0x735f, (q15_t)0xc891, (q15_t)0x735c, (q15_t)0xc88b, (q15_t)0x7359, (q15_t)0xc886, (q15_t)0x7357, (q15_t)0xc880, + (q15_t)0x7354, (q15_t)0xc87a, (q15_t)0x7351, (q15_t)0xc875, (q15_t)0x734f, (q15_t)0xc86f, (q15_t)0x734c, (q15_t)0xc869, + (q15_t)0x7349, (q15_t)0xc864, (q15_t)0x7346, (q15_t)0xc85e, (q15_t)0x7344, (q15_t)0xc858, (q15_t)0x7341, (q15_t)0xc853, + (q15_t)0x733e, (q15_t)0xc84d, (q15_t)0x733b, (q15_t)0xc847, (q15_t)0x7339, (q15_t)0xc842, (q15_t)0x7336, (q15_t)0xc83c, + (q15_t)0x7333, (q15_t)0xc836, (q15_t)0x7330, (q15_t)0xc831, (q15_t)0x732e, (q15_t)0xc82b, (q15_t)0x732b, (q15_t)0xc825, + (q15_t)0x7328, (q15_t)0xc820, (q15_t)0x7326, (q15_t)0xc81a, (q15_t)0x7323, (q15_t)0xc814, (q15_t)0x7320, (q15_t)0xc80f, + (q15_t)0x731d, (q15_t)0xc809, (q15_t)0x731b, (q15_t)0xc803, (q15_t)0x7318, (q15_t)0xc7fe, (q15_t)0x7315, (q15_t)0xc7f8, + (q15_t)0x7312, (q15_t)0xc7f3, (q15_t)0x7310, (q15_t)0xc7ed, (q15_t)0x730d, (q15_t)0xc7e7, (q15_t)0x730a, (q15_t)0xc7e2, + (q15_t)0x7307, (q15_t)0xc7dc, (q15_t)0x7305, (q15_t)0xc7d6, (q15_t)0x7302, (q15_t)0xc7d1, (q15_t)0x72ff, (q15_t)0xc7cb, + (q15_t)0x72fc, (q15_t)0xc7c5, (q15_t)0x72f9, (q15_t)0xc7c0, (q15_t)0x72f7, (q15_t)0xc7ba, (q15_t)0x72f4, (q15_t)0xc7b4, + (q15_t)0x72f1, (q15_t)0xc7af, (q15_t)0x72ee, (q15_t)0xc7a9, (q15_t)0x72ec, (q15_t)0xc7a3, (q15_t)0x72e9, (q15_t)0xc79e, + (q15_t)0x72e6, (q15_t)0xc798, (q15_t)0x72e3, (q15_t)0xc793, (q15_t)0x72e1, (q15_t)0xc78d, (q15_t)0x72de, (q15_t)0xc787, + (q15_t)0x72db, (q15_t)0xc782, (q15_t)0x72d8, (q15_t)0xc77c, (q15_t)0x72d5, (q15_t)0xc776, (q15_t)0x72d3, (q15_t)0xc771, + (q15_t)0x72d0, (q15_t)0xc76b, (q15_t)0x72cd, (q15_t)0xc765, (q15_t)0x72ca, (q15_t)0xc760, (q15_t)0x72c8, (q15_t)0xc75a, + (q15_t)0x72c5, (q15_t)0xc755, (q15_t)0x72c2, (q15_t)0xc74f, (q15_t)0x72bf, (q15_t)0xc749, (q15_t)0x72bc, (q15_t)0xc744, + (q15_t)0x72ba, (q15_t)0xc73e, (q15_t)0x72b7, (q15_t)0xc738, (q15_t)0x72b4, (q15_t)0xc733, (q15_t)0x72b1, (q15_t)0xc72d, + (q15_t)0x72af, (q15_t)0xc728, (q15_t)0x72ac, (q15_t)0xc722, (q15_t)0x72a9, (q15_t)0xc71c, (q15_t)0x72a6, (q15_t)0xc717, + (q15_t)0x72a3, (q15_t)0xc711, (q15_t)0x72a1, (q15_t)0xc70b, (q15_t)0x729e, (q15_t)0xc706, (q15_t)0x729b, (q15_t)0xc700, + (q15_t)0x7298, (q15_t)0xc6fa, (q15_t)0x7295, (q15_t)0xc6f5, (q15_t)0x7293, (q15_t)0xc6ef, (q15_t)0x7290, (q15_t)0xc6ea, + (q15_t)0x728d, (q15_t)0xc6e4, (q15_t)0x728a, (q15_t)0xc6de, (q15_t)0x7287, (q15_t)0xc6d9, (q15_t)0x7285, (q15_t)0xc6d3, + (q15_t)0x7282, (q15_t)0xc6ce, (q15_t)0x727f, (q15_t)0xc6c8, (q15_t)0x727c, (q15_t)0xc6c2, (q15_t)0x7279, (q15_t)0xc6bd, + (q15_t)0x7276, (q15_t)0xc6b7, (q15_t)0x7274, (q15_t)0xc6b1, (q15_t)0x7271, (q15_t)0xc6ac, (q15_t)0x726e, (q15_t)0xc6a6, + (q15_t)0x726b, (q15_t)0xc6a1, (q15_t)0x7268, (q15_t)0xc69b, (q15_t)0x7266, (q15_t)0xc695, (q15_t)0x7263, (q15_t)0xc690, + (q15_t)0x7260, (q15_t)0xc68a, (q15_t)0x725d, (q15_t)0xc684, (q15_t)0x725a, (q15_t)0xc67f, (q15_t)0x7257, (q15_t)0xc679, + (q15_t)0x7255, (q15_t)0xc674, (q15_t)0x7252, (q15_t)0xc66e, (q15_t)0x724f, (q15_t)0xc668, (q15_t)0x724c, (q15_t)0xc663, + (q15_t)0x7249, (q15_t)0xc65d, (q15_t)0x7247, (q15_t)0xc658, (q15_t)0x7244, (q15_t)0xc652, (q15_t)0x7241, (q15_t)0xc64c, + (q15_t)0x723e, (q15_t)0xc647, (q15_t)0x723b, (q15_t)0xc641, (q15_t)0x7238, (q15_t)0xc63c, (q15_t)0x7236, (q15_t)0xc636, + (q15_t)0x7233, (q15_t)0xc630, (q15_t)0x7230, (q15_t)0xc62b, (q15_t)0x722d, (q15_t)0xc625, (q15_t)0x722a, (q15_t)0xc620, + (q15_t)0x7227, (q15_t)0xc61a, (q15_t)0x7224, (q15_t)0xc614, (q15_t)0x7222, (q15_t)0xc60f, (q15_t)0x721f, (q15_t)0xc609, + (q15_t)0x721c, (q15_t)0xc603, (q15_t)0x7219, (q15_t)0xc5fe, (q15_t)0x7216, (q15_t)0xc5f8, (q15_t)0x7213, (q15_t)0xc5f3, + (q15_t)0x7211, (q15_t)0xc5ed, (q15_t)0x720e, (q15_t)0xc5e7, (q15_t)0x720b, (q15_t)0xc5e2, (q15_t)0x7208, (q15_t)0xc5dc, + (q15_t)0x7205, (q15_t)0xc5d7, (q15_t)0x7202, (q15_t)0xc5d1, (q15_t)0x71ff, (q15_t)0xc5cc, (q15_t)0x71fd, (q15_t)0xc5c6, + (q15_t)0x71fa, (q15_t)0xc5c0, (q15_t)0x71f7, (q15_t)0xc5bb, (q15_t)0x71f4, (q15_t)0xc5b5, (q15_t)0x71f1, (q15_t)0xc5b0, + (q15_t)0x71ee, (q15_t)0xc5aa, (q15_t)0x71eb, (q15_t)0xc5a4, (q15_t)0x71e9, (q15_t)0xc59f, (q15_t)0x71e6, (q15_t)0xc599, + (q15_t)0x71e3, (q15_t)0xc594, (q15_t)0x71e0, (q15_t)0xc58e, (q15_t)0x71dd, (q15_t)0xc588, (q15_t)0x71da, (q15_t)0xc583, + (q15_t)0x71d7, (q15_t)0xc57d, (q15_t)0x71d4, (q15_t)0xc578, (q15_t)0x71d2, (q15_t)0xc572, (q15_t)0x71cf, (q15_t)0xc56c, + (q15_t)0x71cc, (q15_t)0xc567, (q15_t)0x71c9, (q15_t)0xc561, (q15_t)0x71c6, (q15_t)0xc55c, (q15_t)0x71c3, (q15_t)0xc556, + (q15_t)0x71c0, (q15_t)0xc551, (q15_t)0x71bd, (q15_t)0xc54b, (q15_t)0x71bb, (q15_t)0xc545, (q15_t)0x71b8, (q15_t)0xc540, + (q15_t)0x71b5, (q15_t)0xc53a, (q15_t)0x71b2, (q15_t)0xc535, (q15_t)0x71af, (q15_t)0xc52f, (q15_t)0x71ac, (q15_t)0xc529, + (q15_t)0x71a9, (q15_t)0xc524, (q15_t)0x71a6, (q15_t)0xc51e, (q15_t)0x71a3, (q15_t)0xc519, (q15_t)0x71a1, (q15_t)0xc513, + (q15_t)0x719e, (q15_t)0xc50e, (q15_t)0x719b, (q15_t)0xc508, (q15_t)0x7198, (q15_t)0xc502, (q15_t)0x7195, (q15_t)0xc4fd, + (q15_t)0x7192, (q15_t)0xc4f7, (q15_t)0x718f, (q15_t)0xc4f2, (q15_t)0x718c, (q15_t)0xc4ec, (q15_t)0x7189, (q15_t)0xc4e7, + (q15_t)0x7186, (q15_t)0xc4e1, (q15_t)0x7184, (q15_t)0xc4db, (q15_t)0x7181, (q15_t)0xc4d6, (q15_t)0x717e, (q15_t)0xc4d0, + (q15_t)0x717b, (q15_t)0xc4cb, (q15_t)0x7178, (q15_t)0xc4c5, (q15_t)0x7175, (q15_t)0xc4c0, (q15_t)0x7172, (q15_t)0xc4ba, + (q15_t)0x716f, (q15_t)0xc4b4, (q15_t)0x716c, (q15_t)0xc4af, (q15_t)0x7169, (q15_t)0xc4a9, (q15_t)0x7167, (q15_t)0xc4a4, + (q15_t)0x7164, (q15_t)0xc49e, (q15_t)0x7161, (q15_t)0xc499, (q15_t)0x715e, (q15_t)0xc493, (q15_t)0x715b, (q15_t)0xc48d, + (q15_t)0x7158, (q15_t)0xc488, (q15_t)0x7155, (q15_t)0xc482, (q15_t)0x7152, (q15_t)0xc47d, (q15_t)0x714f, (q15_t)0xc477, + (q15_t)0x714c, (q15_t)0xc472, (q15_t)0x7149, (q15_t)0xc46c, (q15_t)0x7146, (q15_t)0xc467, (q15_t)0x7143, (q15_t)0xc461, + (q15_t)0x7141, (q15_t)0xc45b, (q15_t)0x713e, (q15_t)0xc456, (q15_t)0x713b, (q15_t)0xc450, (q15_t)0x7138, (q15_t)0xc44b, + (q15_t)0x7135, (q15_t)0xc445, (q15_t)0x7132, (q15_t)0xc440, (q15_t)0x712f, (q15_t)0xc43a, (q15_t)0x712c, (q15_t)0xc434, + (q15_t)0x7129, (q15_t)0xc42f, (q15_t)0x7126, (q15_t)0xc429, (q15_t)0x7123, (q15_t)0xc424, (q15_t)0x7120, (q15_t)0xc41e, + (q15_t)0x711d, (q15_t)0xc419, (q15_t)0x711a, (q15_t)0xc413, (q15_t)0x7117, (q15_t)0xc40e, (q15_t)0x7114, (q15_t)0xc408, + (q15_t)0x7112, (q15_t)0xc403, (q15_t)0x710f, (q15_t)0xc3fd, (q15_t)0x710c, (q15_t)0xc3f7, (q15_t)0x7109, (q15_t)0xc3f2, + (q15_t)0x7106, (q15_t)0xc3ec, (q15_t)0x7103, (q15_t)0xc3e7, (q15_t)0x7100, (q15_t)0xc3e1, (q15_t)0x70fd, (q15_t)0xc3dc, + (q15_t)0x70fa, (q15_t)0xc3d6, (q15_t)0x70f7, (q15_t)0xc3d1, (q15_t)0x70f4, (q15_t)0xc3cb, (q15_t)0x70f1, (q15_t)0xc3c5, + (q15_t)0x70ee, (q15_t)0xc3c0, (q15_t)0x70eb, (q15_t)0xc3ba, (q15_t)0x70e8, (q15_t)0xc3b5, (q15_t)0x70e5, (q15_t)0xc3af, + (q15_t)0x70e2, (q15_t)0xc3aa, (q15_t)0x70df, (q15_t)0xc3a4, (q15_t)0x70dc, (q15_t)0xc39f, (q15_t)0x70d9, (q15_t)0xc399, + (q15_t)0x70d6, (q15_t)0xc394, (q15_t)0x70d3, (q15_t)0xc38e, (q15_t)0x70d1, (q15_t)0xc389, (q15_t)0x70ce, (q15_t)0xc383, + (q15_t)0x70cb, (q15_t)0xc37d, (q15_t)0x70c8, (q15_t)0xc378, (q15_t)0x70c5, (q15_t)0xc372, (q15_t)0x70c2, (q15_t)0xc36d, + (q15_t)0x70bf, (q15_t)0xc367, (q15_t)0x70bc, (q15_t)0xc362, (q15_t)0x70b9, (q15_t)0xc35c, (q15_t)0x70b6, (q15_t)0xc357, + (q15_t)0x70b3, (q15_t)0xc351, (q15_t)0x70b0, (q15_t)0xc34c, (q15_t)0x70ad, (q15_t)0xc346, (q15_t)0x70aa, (q15_t)0xc341, + (q15_t)0x70a7, (q15_t)0xc33b, (q15_t)0x70a4, (q15_t)0xc336, (q15_t)0x70a1, (q15_t)0xc330, (q15_t)0x709e, (q15_t)0xc32a, + (q15_t)0x709b, (q15_t)0xc325, (q15_t)0x7098, (q15_t)0xc31f, (q15_t)0x7095, (q15_t)0xc31a, (q15_t)0x7092, (q15_t)0xc314, + (q15_t)0x708f, (q15_t)0xc30f, (q15_t)0x708c, (q15_t)0xc309, (q15_t)0x7089, (q15_t)0xc304, (q15_t)0x7086, (q15_t)0xc2fe, + (q15_t)0x7083, (q15_t)0xc2f9, (q15_t)0x7080, (q15_t)0xc2f3, (q15_t)0x707d, (q15_t)0xc2ee, (q15_t)0x707a, (q15_t)0xc2e8, + (q15_t)0x7077, (q15_t)0xc2e3, (q15_t)0x7074, (q15_t)0xc2dd, (q15_t)0x7071, (q15_t)0xc2d8, (q15_t)0x706e, (q15_t)0xc2d2, + (q15_t)0x706b, (q15_t)0xc2cd, (q15_t)0x7068, (q15_t)0xc2c7, (q15_t)0x7065, (q15_t)0xc2c2, (q15_t)0x7062, (q15_t)0xc2bc, + (q15_t)0x705f, (q15_t)0xc2b7, (q15_t)0x705c, (q15_t)0xc2b1, (q15_t)0x7059, (q15_t)0xc2ab, (q15_t)0x7056, (q15_t)0xc2a6, + (q15_t)0x7053, (q15_t)0xc2a0, (q15_t)0x7050, (q15_t)0xc29b, (q15_t)0x704d, (q15_t)0xc295, (q15_t)0x704a, (q15_t)0xc290, + (q15_t)0x7047, (q15_t)0xc28a, (q15_t)0x7044, (q15_t)0xc285, (q15_t)0x7041, (q15_t)0xc27f, (q15_t)0x703e, (q15_t)0xc27a, + (q15_t)0x703b, (q15_t)0xc274, (q15_t)0x7038, (q15_t)0xc26f, (q15_t)0x7035, (q15_t)0xc269, (q15_t)0x7032, (q15_t)0xc264, + (q15_t)0x702f, (q15_t)0xc25e, (q15_t)0x702c, (q15_t)0xc259, (q15_t)0x7029, (q15_t)0xc253, (q15_t)0x7026, (q15_t)0xc24e, + (q15_t)0x7023, (q15_t)0xc248, (q15_t)0x7020, (q15_t)0xc243, (q15_t)0x701d, (q15_t)0xc23d, (q15_t)0x7019, (q15_t)0xc238, + (q15_t)0x7016, (q15_t)0xc232, (q15_t)0x7013, (q15_t)0xc22d, (q15_t)0x7010, (q15_t)0xc227, (q15_t)0x700d, (q15_t)0xc222, + (q15_t)0x700a, (q15_t)0xc21c, (q15_t)0x7007, (q15_t)0xc217, (q15_t)0x7004, (q15_t)0xc211, (q15_t)0x7001, (q15_t)0xc20c, + (q15_t)0x6ffe, (q15_t)0xc206, (q15_t)0x6ffb, (q15_t)0xc201, (q15_t)0x6ff8, (q15_t)0xc1fb, (q15_t)0x6ff5, (q15_t)0xc1f6, + (q15_t)0x6ff2, (q15_t)0xc1f0, (q15_t)0x6fef, (q15_t)0xc1eb, (q15_t)0x6fec, (q15_t)0xc1e5, (q15_t)0x6fe9, (q15_t)0xc1e0, + (q15_t)0x6fe6, (q15_t)0xc1da, (q15_t)0x6fe3, (q15_t)0xc1d5, (q15_t)0x6fe0, (q15_t)0xc1cf, (q15_t)0x6fdd, (q15_t)0xc1ca, + (q15_t)0x6fda, (q15_t)0xc1c4, (q15_t)0x6fd6, (q15_t)0xc1bf, (q15_t)0x6fd3, (q15_t)0xc1b9, (q15_t)0x6fd0, (q15_t)0xc1b4, + (q15_t)0x6fcd, (q15_t)0xc1ae, (q15_t)0x6fca, (q15_t)0xc1a9, (q15_t)0x6fc7, (q15_t)0xc1a3, (q15_t)0x6fc4, (q15_t)0xc19e, + (q15_t)0x6fc1, (q15_t)0xc198, (q15_t)0x6fbe, (q15_t)0xc193, (q15_t)0x6fbb, (q15_t)0xc18d, (q15_t)0x6fb8, (q15_t)0xc188, + (q15_t)0x6fb5, (q15_t)0xc183, (q15_t)0x6fb2, (q15_t)0xc17d, (q15_t)0x6faf, (q15_t)0xc178, (q15_t)0x6fac, (q15_t)0xc172, + (q15_t)0x6fa9, (q15_t)0xc16d, (q15_t)0x6fa5, (q15_t)0xc167, (q15_t)0x6fa2, (q15_t)0xc162, (q15_t)0x6f9f, (q15_t)0xc15c, + (q15_t)0x6f9c, (q15_t)0xc157, (q15_t)0x6f99, (q15_t)0xc151, (q15_t)0x6f96, (q15_t)0xc14c, (q15_t)0x6f93, (q15_t)0xc146, + (q15_t)0x6f90, (q15_t)0xc141, (q15_t)0x6f8d, (q15_t)0xc13b, (q15_t)0x6f8a, (q15_t)0xc136, (q15_t)0x6f87, (q15_t)0xc130, + (q15_t)0x6f84, (q15_t)0xc12b, (q15_t)0x6f81, (q15_t)0xc125, (q15_t)0x6f7d, (q15_t)0xc120, (q15_t)0x6f7a, (q15_t)0xc11a, + (q15_t)0x6f77, (q15_t)0xc115, (q15_t)0x6f74, (q15_t)0xc10f, (q15_t)0x6f71, (q15_t)0xc10a, (q15_t)0x6f6e, (q15_t)0xc105, + (q15_t)0x6f6b, (q15_t)0xc0ff, (q15_t)0x6f68, (q15_t)0xc0fa, (q15_t)0x6f65, (q15_t)0xc0f4, (q15_t)0x6f62, (q15_t)0xc0ef, + (q15_t)0x6f5f, (q15_t)0xc0e9, (q15_t)0x6f5b, (q15_t)0xc0e4, (q15_t)0x6f58, (q15_t)0xc0de, (q15_t)0x6f55, (q15_t)0xc0d9, + (q15_t)0x6f52, (q15_t)0xc0d3, (q15_t)0x6f4f, (q15_t)0xc0ce, (q15_t)0x6f4c, (q15_t)0xc0c8, (q15_t)0x6f49, (q15_t)0xc0c3, + (q15_t)0x6f46, (q15_t)0xc0bd, (q15_t)0x6f43, (q15_t)0xc0b8, (q15_t)0x6f3f, (q15_t)0xc0b3, (q15_t)0x6f3c, (q15_t)0xc0ad, + (q15_t)0x6f39, (q15_t)0xc0a8, (q15_t)0x6f36, (q15_t)0xc0a2, (q15_t)0x6f33, (q15_t)0xc09d, (q15_t)0x6f30, (q15_t)0xc097, + (q15_t)0x6f2d, (q15_t)0xc092, (q15_t)0x6f2a, (q15_t)0xc08c, (q15_t)0x6f27, (q15_t)0xc087, (q15_t)0x6f23, (q15_t)0xc081, + (q15_t)0x6f20, (q15_t)0xc07c, (q15_t)0x6f1d, (q15_t)0xc077, (q15_t)0x6f1a, (q15_t)0xc071, (q15_t)0x6f17, (q15_t)0xc06c, + (q15_t)0x6f14, (q15_t)0xc066, (q15_t)0x6f11, (q15_t)0xc061, (q15_t)0x6f0e, (q15_t)0xc05b, (q15_t)0x6f0b, (q15_t)0xc056, + (q15_t)0x6f07, (q15_t)0xc050, (q15_t)0x6f04, (q15_t)0xc04b, (q15_t)0x6f01, (q15_t)0xc045, (q15_t)0x6efe, (q15_t)0xc040, + (q15_t)0x6efb, (q15_t)0xc03b, (q15_t)0x6ef8, (q15_t)0xc035, (q15_t)0x6ef5, (q15_t)0xc030, (q15_t)0x6ef1, (q15_t)0xc02a, + (q15_t)0x6eee, (q15_t)0xc025, (q15_t)0x6eeb, (q15_t)0xc01f, (q15_t)0x6ee8, (q15_t)0xc01a, (q15_t)0x6ee5, (q15_t)0xc014, + (q15_t)0x6ee2, (q15_t)0xc00f, (q15_t)0x6edf, (q15_t)0xc00a, (q15_t)0x6edc, (q15_t)0xc004, (q15_t)0x6ed8, (q15_t)0xbfff, + (q15_t)0x6ed5, (q15_t)0xbff9, (q15_t)0x6ed2, (q15_t)0xbff4, (q15_t)0x6ecf, (q15_t)0xbfee, (q15_t)0x6ecc, (q15_t)0xbfe9, + (q15_t)0x6ec9, (q15_t)0xbfe3, (q15_t)0x6ec6, (q15_t)0xbfde, (q15_t)0x6ec2, (q15_t)0xbfd9, (q15_t)0x6ebf, (q15_t)0xbfd3, + (q15_t)0x6ebc, (q15_t)0xbfce, (q15_t)0x6eb9, (q15_t)0xbfc8, (q15_t)0x6eb6, (q15_t)0xbfc3, (q15_t)0x6eb3, (q15_t)0xbfbd, + (q15_t)0x6eaf, (q15_t)0xbfb8, (q15_t)0x6eac, (q15_t)0xbfb3, (q15_t)0x6ea9, (q15_t)0xbfad, (q15_t)0x6ea6, (q15_t)0xbfa8, + (q15_t)0x6ea3, (q15_t)0xbfa2, (q15_t)0x6ea0, (q15_t)0xbf9d, (q15_t)0x6e9c, (q15_t)0xbf97, (q15_t)0x6e99, (q15_t)0xbf92, + (q15_t)0x6e96, (q15_t)0xbf8d, (q15_t)0x6e93, (q15_t)0xbf87, (q15_t)0x6e90, (q15_t)0xbf82, (q15_t)0x6e8d, (q15_t)0xbf7c, + (q15_t)0x6e89, (q15_t)0xbf77, (q15_t)0x6e86, (q15_t)0xbf71, (q15_t)0x6e83, (q15_t)0xbf6c, (q15_t)0x6e80, (q15_t)0xbf67, + (q15_t)0x6e7d, (q15_t)0xbf61, (q15_t)0x6e7a, (q15_t)0xbf5c, (q15_t)0x6e76, (q15_t)0xbf56, (q15_t)0x6e73, (q15_t)0xbf51, + (q15_t)0x6e70, (q15_t)0xbf4b, (q15_t)0x6e6d, (q15_t)0xbf46, (q15_t)0x6e6a, (q15_t)0xbf41, (q15_t)0x6e67, (q15_t)0xbf3b, + (q15_t)0x6e63, (q15_t)0xbf36, (q15_t)0x6e60, (q15_t)0xbf30, (q15_t)0x6e5d, (q15_t)0xbf2b, (q15_t)0x6e5a, (q15_t)0xbf26, + (q15_t)0x6e57, (q15_t)0xbf20, (q15_t)0x6e53, (q15_t)0xbf1b, (q15_t)0x6e50, (q15_t)0xbf15, (q15_t)0x6e4d, (q15_t)0xbf10, + (q15_t)0x6e4a, (q15_t)0xbf0a, (q15_t)0x6e47, (q15_t)0xbf05, (q15_t)0x6e44, (q15_t)0xbf00, (q15_t)0x6e40, (q15_t)0xbefa, + (q15_t)0x6e3d, (q15_t)0xbef5, (q15_t)0x6e3a, (q15_t)0xbeef, (q15_t)0x6e37, (q15_t)0xbeea, (q15_t)0x6e34, (q15_t)0xbee5, + (q15_t)0x6e30, (q15_t)0xbedf, (q15_t)0x6e2d, (q15_t)0xbeda, (q15_t)0x6e2a, (q15_t)0xbed4, (q15_t)0x6e27, (q15_t)0xbecf, + (q15_t)0x6e24, (q15_t)0xbeca, (q15_t)0x6e20, (q15_t)0xbec4, (q15_t)0x6e1d, (q15_t)0xbebf, (q15_t)0x6e1a, (q15_t)0xbeb9, + (q15_t)0x6e17, (q15_t)0xbeb4, (q15_t)0x6e14, (q15_t)0xbeae, (q15_t)0x6e10, (q15_t)0xbea9, (q15_t)0x6e0d, (q15_t)0xbea4, + (q15_t)0x6e0a, (q15_t)0xbe9e, (q15_t)0x6e07, (q15_t)0xbe99, (q15_t)0x6e04, (q15_t)0xbe93, (q15_t)0x6e00, (q15_t)0xbe8e, + (q15_t)0x6dfd, (q15_t)0xbe89, (q15_t)0x6dfa, (q15_t)0xbe83, (q15_t)0x6df7, (q15_t)0xbe7e, (q15_t)0x6df3, (q15_t)0xbe78, + (q15_t)0x6df0, (q15_t)0xbe73, (q15_t)0x6ded, (q15_t)0xbe6e, (q15_t)0x6dea, (q15_t)0xbe68, (q15_t)0x6de7, (q15_t)0xbe63, + (q15_t)0x6de3, (q15_t)0xbe5e, (q15_t)0x6de0, (q15_t)0xbe58, (q15_t)0x6ddd, (q15_t)0xbe53, (q15_t)0x6dda, (q15_t)0xbe4d, + (q15_t)0x6dd6, (q15_t)0xbe48, (q15_t)0x6dd3, (q15_t)0xbe43, (q15_t)0x6dd0, (q15_t)0xbe3d, (q15_t)0x6dcd, (q15_t)0xbe38, + (q15_t)0x6dca, (q15_t)0xbe32, (q15_t)0x6dc6, (q15_t)0xbe2d, (q15_t)0x6dc3, (q15_t)0xbe28, (q15_t)0x6dc0, (q15_t)0xbe22, + (q15_t)0x6dbd, (q15_t)0xbe1d, (q15_t)0x6db9, (q15_t)0xbe17, (q15_t)0x6db6, (q15_t)0xbe12, (q15_t)0x6db3, (q15_t)0xbe0d, + (q15_t)0x6db0, (q15_t)0xbe07, (q15_t)0x6dac, (q15_t)0xbe02, (q15_t)0x6da9, (q15_t)0xbdfd, (q15_t)0x6da6, (q15_t)0xbdf7, + (q15_t)0x6da3, (q15_t)0xbdf2, (q15_t)0x6d9f, (q15_t)0xbdec, (q15_t)0x6d9c, (q15_t)0xbde7, (q15_t)0x6d99, (q15_t)0xbde2, + (q15_t)0x6d96, (q15_t)0xbddc, (q15_t)0x6d92, (q15_t)0xbdd7, (q15_t)0x6d8f, (q15_t)0xbdd1, (q15_t)0x6d8c, (q15_t)0xbdcc, + (q15_t)0x6d89, (q15_t)0xbdc7, (q15_t)0x6d85, (q15_t)0xbdc1, (q15_t)0x6d82, (q15_t)0xbdbc, (q15_t)0x6d7f, (q15_t)0xbdb7, + (q15_t)0x6d7c, (q15_t)0xbdb1, (q15_t)0x6d78, (q15_t)0xbdac, (q15_t)0x6d75, (q15_t)0xbda6, (q15_t)0x6d72, (q15_t)0xbda1, + (q15_t)0x6d6f, (q15_t)0xbd9c, (q15_t)0x6d6b, (q15_t)0xbd96, (q15_t)0x6d68, (q15_t)0xbd91, (q15_t)0x6d65, (q15_t)0xbd8c, + (q15_t)0x6d62, (q15_t)0xbd86, (q15_t)0x6d5e, (q15_t)0xbd81, (q15_t)0x6d5b, (q15_t)0xbd7c, (q15_t)0x6d58, (q15_t)0xbd76, + (q15_t)0x6d55, (q15_t)0xbd71, (q15_t)0x6d51, (q15_t)0xbd6b, (q15_t)0x6d4e, (q15_t)0xbd66, (q15_t)0x6d4b, (q15_t)0xbd61, + (q15_t)0x6d48, (q15_t)0xbd5b, (q15_t)0x6d44, (q15_t)0xbd56, (q15_t)0x6d41, (q15_t)0xbd51, (q15_t)0x6d3e, (q15_t)0xbd4b, + (q15_t)0x6d3a, (q15_t)0xbd46, (q15_t)0x6d37, (q15_t)0xbd40, (q15_t)0x6d34, (q15_t)0xbd3b, (q15_t)0x6d31, (q15_t)0xbd36, + (q15_t)0x6d2d, (q15_t)0xbd30, (q15_t)0x6d2a, (q15_t)0xbd2b, (q15_t)0x6d27, (q15_t)0xbd26, (q15_t)0x6d23, (q15_t)0xbd20, + (q15_t)0x6d20, (q15_t)0xbd1b, (q15_t)0x6d1d, (q15_t)0xbd16, (q15_t)0x6d1a, (q15_t)0xbd10, (q15_t)0x6d16, (q15_t)0xbd0b, + (q15_t)0x6d13, (q15_t)0xbd06, (q15_t)0x6d10, (q15_t)0xbd00, (q15_t)0x6d0c, (q15_t)0xbcfb, (q15_t)0x6d09, (q15_t)0xbcf5, + (q15_t)0x6d06, (q15_t)0xbcf0, (q15_t)0x6d03, (q15_t)0xbceb, (q15_t)0x6cff, (q15_t)0xbce5, (q15_t)0x6cfc, (q15_t)0xbce0, + (q15_t)0x6cf9, (q15_t)0xbcdb, (q15_t)0x6cf5, (q15_t)0xbcd5, (q15_t)0x6cf2, (q15_t)0xbcd0, (q15_t)0x6cef, (q15_t)0xbccb, + (q15_t)0x6cec, (q15_t)0xbcc5, (q15_t)0x6ce8, (q15_t)0xbcc0, (q15_t)0x6ce5, (q15_t)0xbcbb, (q15_t)0x6ce2, (q15_t)0xbcb5, + (q15_t)0x6cde, (q15_t)0xbcb0, (q15_t)0x6cdb, (q15_t)0xbcab, (q15_t)0x6cd8, (q15_t)0xbca5, (q15_t)0x6cd4, (q15_t)0xbca0, + (q15_t)0x6cd1, (q15_t)0xbc9b, (q15_t)0x6cce, (q15_t)0xbc95, (q15_t)0x6cca, (q15_t)0xbc90, (q15_t)0x6cc7, (q15_t)0xbc8b, + (q15_t)0x6cc4, (q15_t)0xbc85, (q15_t)0x6cc1, (q15_t)0xbc80, (q15_t)0x6cbd, (q15_t)0xbc7b, (q15_t)0x6cba, (q15_t)0xbc75, + (q15_t)0x6cb7, (q15_t)0xbc70, (q15_t)0x6cb3, (q15_t)0xbc6b, (q15_t)0x6cb0, (q15_t)0xbc65, (q15_t)0x6cad, (q15_t)0xbc60, + (q15_t)0x6ca9, (q15_t)0xbc5b, (q15_t)0x6ca6, (q15_t)0xbc55, (q15_t)0x6ca3, (q15_t)0xbc50, (q15_t)0x6c9f, (q15_t)0xbc4b, + (q15_t)0x6c9c, (q15_t)0xbc45, (q15_t)0x6c99, (q15_t)0xbc40, (q15_t)0x6c95, (q15_t)0xbc3b, (q15_t)0x6c92, (q15_t)0xbc35, + (q15_t)0x6c8f, (q15_t)0xbc30, (q15_t)0x6c8b, (q15_t)0xbc2b, (q15_t)0x6c88, (q15_t)0xbc25, (q15_t)0x6c85, (q15_t)0xbc20, + (q15_t)0x6c81, (q15_t)0xbc1b, (q15_t)0x6c7e, (q15_t)0xbc15, (q15_t)0x6c7b, (q15_t)0xbc10, (q15_t)0x6c77, (q15_t)0xbc0b, + (q15_t)0x6c74, (q15_t)0xbc05, (q15_t)0x6c71, (q15_t)0xbc00, (q15_t)0x6c6d, (q15_t)0xbbfb, (q15_t)0x6c6a, (q15_t)0xbbf5, + (q15_t)0x6c67, (q15_t)0xbbf0, (q15_t)0x6c63, (q15_t)0xbbeb, (q15_t)0x6c60, (q15_t)0xbbe5, (q15_t)0x6c5d, (q15_t)0xbbe0, + (q15_t)0x6c59, (q15_t)0xbbdb, (q15_t)0x6c56, (q15_t)0xbbd5, (q15_t)0x6c53, (q15_t)0xbbd0, (q15_t)0x6c4f, (q15_t)0xbbcb, + (q15_t)0x6c4c, (q15_t)0xbbc5, (q15_t)0x6c49, (q15_t)0xbbc0, (q15_t)0x6c45, (q15_t)0xbbbb, (q15_t)0x6c42, (q15_t)0xbbb5, + (q15_t)0x6c3f, (q15_t)0xbbb0, (q15_t)0x6c3b, (q15_t)0xbbab, (q15_t)0x6c38, (q15_t)0xbba6, (q15_t)0x6c34, (q15_t)0xbba0, + (q15_t)0x6c31, (q15_t)0xbb9b, (q15_t)0x6c2e, (q15_t)0xbb96, (q15_t)0x6c2a, (q15_t)0xbb90, (q15_t)0x6c27, (q15_t)0xbb8b, + (q15_t)0x6c24, (q15_t)0xbb86, (q15_t)0x6c20, (q15_t)0xbb80, (q15_t)0x6c1d, (q15_t)0xbb7b, (q15_t)0x6c1a, (q15_t)0xbb76, + (q15_t)0x6c16, (q15_t)0xbb70, (q15_t)0x6c13, (q15_t)0xbb6b, (q15_t)0x6c0f, (q15_t)0xbb66, (q15_t)0x6c0c, (q15_t)0xbb61, + (q15_t)0x6c09, (q15_t)0xbb5b, (q15_t)0x6c05, (q15_t)0xbb56, (q15_t)0x6c02, (q15_t)0xbb51, (q15_t)0x6bff, (q15_t)0xbb4b, + (q15_t)0x6bfb, (q15_t)0xbb46, (q15_t)0x6bf8, (q15_t)0xbb41, (q15_t)0x6bf5, (q15_t)0xbb3b, (q15_t)0x6bf1, (q15_t)0xbb36, + (q15_t)0x6bee, (q15_t)0xbb31, (q15_t)0x6bea, (q15_t)0xbb2c, (q15_t)0x6be7, (q15_t)0xbb26, (q15_t)0x6be4, (q15_t)0xbb21, + (q15_t)0x6be0, (q15_t)0xbb1c, (q15_t)0x6bdd, (q15_t)0xbb16, (q15_t)0x6bd9, (q15_t)0xbb11, (q15_t)0x6bd6, (q15_t)0xbb0c, + (q15_t)0x6bd3, (q15_t)0xbb06, (q15_t)0x6bcf, (q15_t)0xbb01, (q15_t)0x6bcc, (q15_t)0xbafc, (q15_t)0x6bc9, (q15_t)0xbaf7, + (q15_t)0x6bc5, (q15_t)0xbaf1, (q15_t)0x6bc2, (q15_t)0xbaec, (q15_t)0x6bbe, (q15_t)0xbae7, (q15_t)0x6bbb, (q15_t)0xbae1, + (q15_t)0x6bb8, (q15_t)0xbadc, (q15_t)0x6bb4, (q15_t)0xbad7, (q15_t)0x6bb1, (q15_t)0xbad2, (q15_t)0x6bad, (q15_t)0xbacc, + (q15_t)0x6baa, (q15_t)0xbac7, (q15_t)0x6ba7, (q15_t)0xbac2, (q15_t)0x6ba3, (q15_t)0xbabc, (q15_t)0x6ba0, (q15_t)0xbab7, + (q15_t)0x6b9c, (q15_t)0xbab2, (q15_t)0x6b99, (q15_t)0xbaad, (q15_t)0x6b96, (q15_t)0xbaa7, (q15_t)0x6b92, (q15_t)0xbaa2, + (q15_t)0x6b8f, (q15_t)0xba9d, (q15_t)0x6b8b, (q15_t)0xba97, (q15_t)0x6b88, (q15_t)0xba92, (q15_t)0x6b85, (q15_t)0xba8d, + (q15_t)0x6b81, (q15_t)0xba88, (q15_t)0x6b7e, (q15_t)0xba82, (q15_t)0x6b7a, (q15_t)0xba7d, (q15_t)0x6b77, (q15_t)0xba78, + (q15_t)0x6b73, (q15_t)0xba73, (q15_t)0x6b70, (q15_t)0xba6d, (q15_t)0x6b6d, (q15_t)0xba68, (q15_t)0x6b69, (q15_t)0xba63, + (q15_t)0x6b66, (q15_t)0xba5d, (q15_t)0x6b62, (q15_t)0xba58, (q15_t)0x6b5f, (q15_t)0xba53, (q15_t)0x6b5c, (q15_t)0xba4e, + (q15_t)0x6b58, (q15_t)0xba48, (q15_t)0x6b55, (q15_t)0xba43, (q15_t)0x6b51, (q15_t)0xba3e, (q15_t)0x6b4e, (q15_t)0xba39, + (q15_t)0x6b4a, (q15_t)0xba33, (q15_t)0x6b47, (q15_t)0xba2e, (q15_t)0x6b44, (q15_t)0xba29, (q15_t)0x6b40, (q15_t)0xba23, + (q15_t)0x6b3d, (q15_t)0xba1e, (q15_t)0x6b39, (q15_t)0xba19, (q15_t)0x6b36, (q15_t)0xba14, (q15_t)0x6b32, (q15_t)0xba0e, + (q15_t)0x6b2f, (q15_t)0xba09, (q15_t)0x6b2c, (q15_t)0xba04, (q15_t)0x6b28, (q15_t)0xb9ff, (q15_t)0x6b25, (q15_t)0xb9f9, + (q15_t)0x6b21, (q15_t)0xb9f4, (q15_t)0x6b1e, (q15_t)0xb9ef, (q15_t)0x6b1a, (q15_t)0xb9ea, (q15_t)0x6b17, (q15_t)0xb9e4, + (q15_t)0x6b13, (q15_t)0xb9df, (q15_t)0x6b10, (q15_t)0xb9da, (q15_t)0x6b0d, (q15_t)0xb9d5, (q15_t)0x6b09, (q15_t)0xb9cf, + (q15_t)0x6b06, (q15_t)0xb9ca, (q15_t)0x6b02, (q15_t)0xb9c5, (q15_t)0x6aff, (q15_t)0xb9c0, (q15_t)0x6afb, (q15_t)0xb9ba, + (q15_t)0x6af8, (q15_t)0xb9b5, (q15_t)0x6af4, (q15_t)0xb9b0, (q15_t)0x6af1, (q15_t)0xb9ab, (q15_t)0x6aee, (q15_t)0xb9a5, + (q15_t)0x6aea, (q15_t)0xb9a0, (q15_t)0x6ae7, (q15_t)0xb99b, (q15_t)0x6ae3, (q15_t)0xb996, (q15_t)0x6ae0, (q15_t)0xb990, + (q15_t)0x6adc, (q15_t)0xb98b, (q15_t)0x6ad9, (q15_t)0xb986, (q15_t)0x6ad5, (q15_t)0xb981, (q15_t)0x6ad2, (q15_t)0xb97b, + (q15_t)0x6ace, (q15_t)0xb976, (q15_t)0x6acb, (q15_t)0xb971, (q15_t)0x6ac8, (q15_t)0xb96c, (q15_t)0x6ac4, (q15_t)0xb966, + (q15_t)0x6ac1, (q15_t)0xb961, (q15_t)0x6abd, (q15_t)0xb95c, (q15_t)0x6aba, (q15_t)0xb957, (q15_t)0x6ab6, (q15_t)0xb951, + (q15_t)0x6ab3, (q15_t)0xb94c, (q15_t)0x6aaf, (q15_t)0xb947, (q15_t)0x6aac, (q15_t)0xb942, (q15_t)0x6aa8, (q15_t)0xb93c, + (q15_t)0x6aa5, (q15_t)0xb937, (q15_t)0x6aa1, (q15_t)0xb932, (q15_t)0x6a9e, (q15_t)0xb92d, (q15_t)0x6a9a, (q15_t)0xb928, + (q15_t)0x6a97, (q15_t)0xb922, (q15_t)0x6a93, (q15_t)0xb91d, (q15_t)0x6a90, (q15_t)0xb918, (q15_t)0x6a8c, (q15_t)0xb913, + (q15_t)0x6a89, (q15_t)0xb90d, (q15_t)0x6a86, (q15_t)0xb908, (q15_t)0x6a82, (q15_t)0xb903, (q15_t)0x6a7f, (q15_t)0xb8fe, + (q15_t)0x6a7b, (q15_t)0xb8f8, (q15_t)0x6a78, (q15_t)0xb8f3, (q15_t)0x6a74, (q15_t)0xb8ee, (q15_t)0x6a71, (q15_t)0xb8e9, + (q15_t)0x6a6d, (q15_t)0xb8e4, (q15_t)0x6a6a, (q15_t)0xb8de, (q15_t)0x6a66, (q15_t)0xb8d9, (q15_t)0x6a63, (q15_t)0xb8d4, + (q15_t)0x6a5f, (q15_t)0xb8cf, (q15_t)0x6a5c, (q15_t)0xb8c9, (q15_t)0x6a58, (q15_t)0xb8c4, (q15_t)0x6a55, (q15_t)0xb8bf, + (q15_t)0x6a51, (q15_t)0xb8ba, (q15_t)0x6a4e, (q15_t)0xb8b5, (q15_t)0x6a4a, (q15_t)0xb8af, (q15_t)0x6a47, (q15_t)0xb8aa, + (q15_t)0x6a43, (q15_t)0xb8a5, (q15_t)0x6a40, (q15_t)0xb8a0, (q15_t)0x6a3c, (q15_t)0xb89b, (q15_t)0x6a39, (q15_t)0xb895, + (q15_t)0x6a35, (q15_t)0xb890, (q15_t)0x6a32, (q15_t)0xb88b, (q15_t)0x6a2e, (q15_t)0xb886, (q15_t)0x6a2b, (q15_t)0xb880, + (q15_t)0x6a27, (q15_t)0xb87b, (q15_t)0x6a24, (q15_t)0xb876, (q15_t)0x6a20, (q15_t)0xb871, (q15_t)0x6a1d, (q15_t)0xb86c, + (q15_t)0x6a19, (q15_t)0xb866, (q15_t)0x6a16, (q15_t)0xb861, (q15_t)0x6a12, (q15_t)0xb85c, (q15_t)0x6a0e, (q15_t)0xb857, + (q15_t)0x6a0b, (q15_t)0xb852, (q15_t)0x6a07, (q15_t)0xb84c, (q15_t)0x6a04, (q15_t)0xb847, (q15_t)0x6a00, (q15_t)0xb842, + (q15_t)0x69fd, (q15_t)0xb83d, (q15_t)0x69f9, (q15_t)0xb838, (q15_t)0x69f6, (q15_t)0xb832, (q15_t)0x69f2, (q15_t)0xb82d, + (q15_t)0x69ef, (q15_t)0xb828, (q15_t)0x69eb, (q15_t)0xb823, (q15_t)0x69e8, (q15_t)0xb81e, (q15_t)0x69e4, (q15_t)0xb818, + (q15_t)0x69e1, (q15_t)0xb813, (q15_t)0x69dd, (q15_t)0xb80e, (q15_t)0x69da, (q15_t)0xb809, (q15_t)0x69d6, (q15_t)0xb804, + (q15_t)0x69d3, (q15_t)0xb7fe, (q15_t)0x69cf, (q15_t)0xb7f9, (q15_t)0x69cb, (q15_t)0xb7f4, (q15_t)0x69c8, (q15_t)0xb7ef, + (q15_t)0x69c4, (q15_t)0xb7ea, (q15_t)0x69c1, (q15_t)0xb7e4, (q15_t)0x69bd, (q15_t)0xb7df, (q15_t)0x69ba, (q15_t)0xb7da, + (q15_t)0x69b6, (q15_t)0xb7d5, (q15_t)0x69b3, (q15_t)0xb7d0, (q15_t)0x69af, (q15_t)0xb7ca, (q15_t)0x69ac, (q15_t)0xb7c5, + (q15_t)0x69a8, (q15_t)0xb7c0, (q15_t)0x69a5, (q15_t)0xb7bb, (q15_t)0x69a1, (q15_t)0xb7b6, (q15_t)0x699d, (q15_t)0xb7b1, + (q15_t)0x699a, (q15_t)0xb7ab, (q15_t)0x6996, (q15_t)0xb7a6, (q15_t)0x6993, (q15_t)0xb7a1, (q15_t)0x698f, (q15_t)0xb79c, + (q15_t)0x698c, (q15_t)0xb797, (q15_t)0x6988, (q15_t)0xb791, (q15_t)0x6985, (q15_t)0xb78c, (q15_t)0x6981, (q15_t)0xb787, + (q15_t)0x697d, (q15_t)0xb782, (q15_t)0x697a, (q15_t)0xb77d, (q15_t)0x6976, (q15_t)0xb778, (q15_t)0x6973, (q15_t)0xb772, + (q15_t)0x696f, (q15_t)0xb76d, (q15_t)0x696c, (q15_t)0xb768, (q15_t)0x6968, (q15_t)0xb763, (q15_t)0x6964, (q15_t)0xb75e, + (q15_t)0x6961, (q15_t)0xb758, (q15_t)0x695d, (q15_t)0xb753, (q15_t)0x695a, (q15_t)0xb74e, (q15_t)0x6956, (q15_t)0xb749, + (q15_t)0x6953, (q15_t)0xb744, (q15_t)0x694f, (q15_t)0xb73f, (q15_t)0x694b, (q15_t)0xb739, (q15_t)0x6948, (q15_t)0xb734, + (q15_t)0x6944, (q15_t)0xb72f, (q15_t)0x6941, (q15_t)0xb72a, (q15_t)0x693d, (q15_t)0xb725, (q15_t)0x693a, (q15_t)0xb720, + (q15_t)0x6936, (q15_t)0xb71a, (q15_t)0x6932, (q15_t)0xb715, (q15_t)0x692f, (q15_t)0xb710, (q15_t)0x692b, (q15_t)0xb70b, + (q15_t)0x6928, (q15_t)0xb706, (q15_t)0x6924, (q15_t)0xb701, (q15_t)0x6921, (q15_t)0xb6fb, (q15_t)0x691d, (q15_t)0xb6f6, + (q15_t)0x6919, (q15_t)0xb6f1, (q15_t)0x6916, (q15_t)0xb6ec, (q15_t)0x6912, (q15_t)0xb6e7, (q15_t)0x690f, (q15_t)0xb6e2, + (q15_t)0x690b, (q15_t)0xb6dd, (q15_t)0x6907, (q15_t)0xb6d7, (q15_t)0x6904, (q15_t)0xb6d2, (q15_t)0x6900, (q15_t)0xb6cd, + (q15_t)0x68fd, (q15_t)0xb6c8, (q15_t)0x68f9, (q15_t)0xb6c3, (q15_t)0x68f5, (q15_t)0xb6be, (q15_t)0x68f2, (q15_t)0xb6b8, + (q15_t)0x68ee, (q15_t)0xb6b3, (q15_t)0x68eb, (q15_t)0xb6ae, (q15_t)0x68e7, (q15_t)0xb6a9, (q15_t)0x68e3, (q15_t)0xb6a4, + (q15_t)0x68e0, (q15_t)0xb69f, (q15_t)0x68dc, (q15_t)0xb69a, (q15_t)0x68d9, (q15_t)0xb694, (q15_t)0x68d5, (q15_t)0xb68f, + (q15_t)0x68d1, (q15_t)0xb68a, (q15_t)0x68ce, (q15_t)0xb685, (q15_t)0x68ca, (q15_t)0xb680, (q15_t)0x68c7, (q15_t)0xb67b, + (q15_t)0x68c3, (q15_t)0xb676, (q15_t)0x68bf, (q15_t)0xb670, (q15_t)0x68bc, (q15_t)0xb66b, (q15_t)0x68b8, (q15_t)0xb666, + (q15_t)0x68b5, (q15_t)0xb661, (q15_t)0x68b1, (q15_t)0xb65c, (q15_t)0x68ad, (q15_t)0xb657, (q15_t)0x68aa, (q15_t)0xb652, + (q15_t)0x68a6, (q15_t)0xb64c, (q15_t)0x68a3, (q15_t)0xb647, (q15_t)0x689f, (q15_t)0xb642, (q15_t)0x689b, (q15_t)0xb63d, + (q15_t)0x6898, (q15_t)0xb638, (q15_t)0x6894, (q15_t)0xb633, (q15_t)0x6890, (q15_t)0xb62e, (q15_t)0x688d, (q15_t)0xb628, + (q15_t)0x6889, (q15_t)0xb623, (q15_t)0x6886, (q15_t)0xb61e, (q15_t)0x6882, (q15_t)0xb619, (q15_t)0x687e, (q15_t)0xb614, + (q15_t)0x687b, (q15_t)0xb60f, (q15_t)0x6877, (q15_t)0xb60a, (q15_t)0x6873, (q15_t)0xb605, (q15_t)0x6870, (q15_t)0xb5ff, + (q15_t)0x686c, (q15_t)0xb5fa, (q15_t)0x6868, (q15_t)0xb5f5, (q15_t)0x6865, (q15_t)0xb5f0, (q15_t)0x6861, (q15_t)0xb5eb, + (q15_t)0x685e, (q15_t)0xb5e6, (q15_t)0x685a, (q15_t)0xb5e1, (q15_t)0x6856, (q15_t)0xb5dc, (q15_t)0x6853, (q15_t)0xb5d6, + (q15_t)0x684f, (q15_t)0xb5d1, (q15_t)0x684b, (q15_t)0xb5cc, (q15_t)0x6848, (q15_t)0xb5c7, (q15_t)0x6844, (q15_t)0xb5c2, + (q15_t)0x6840, (q15_t)0xb5bd, (q15_t)0x683d, (q15_t)0xb5b8, (q15_t)0x6839, (q15_t)0xb5b3, (q15_t)0x6835, (q15_t)0xb5ae, + (q15_t)0x6832, (q15_t)0xb5a8, (q15_t)0x682e, (q15_t)0xb5a3, (q15_t)0x682b, (q15_t)0xb59e, (q15_t)0x6827, (q15_t)0xb599, + (q15_t)0x6823, (q15_t)0xb594, (q15_t)0x6820, (q15_t)0xb58f, (q15_t)0x681c, (q15_t)0xb58a, (q15_t)0x6818, (q15_t)0xb585, + (q15_t)0x6815, (q15_t)0xb57f, (q15_t)0x6811, (q15_t)0xb57a, (q15_t)0x680d, (q15_t)0xb575, (q15_t)0x680a, (q15_t)0xb570, + (q15_t)0x6806, (q15_t)0xb56b, (q15_t)0x6802, (q15_t)0xb566, (q15_t)0x67ff, (q15_t)0xb561, (q15_t)0x67fb, (q15_t)0xb55c, + (q15_t)0x67f7, (q15_t)0xb557, (q15_t)0x67f4, (q15_t)0xb552, (q15_t)0x67f0, (q15_t)0xb54c, (q15_t)0x67ec, (q15_t)0xb547, + (q15_t)0x67e9, (q15_t)0xb542, (q15_t)0x67e5, (q15_t)0xb53d, (q15_t)0x67e1, (q15_t)0xb538, (q15_t)0x67de, (q15_t)0xb533, + (q15_t)0x67da, (q15_t)0xb52e, (q15_t)0x67d6, (q15_t)0xb529, (q15_t)0x67d3, (q15_t)0xb524, (q15_t)0x67cf, (q15_t)0xb51f, + (q15_t)0x67cb, (q15_t)0xb519, (q15_t)0x67c8, (q15_t)0xb514, (q15_t)0x67c4, (q15_t)0xb50f, (q15_t)0x67c0, (q15_t)0xb50a, + (q15_t)0x67bd, (q15_t)0xb505, (q15_t)0x67b9, (q15_t)0xb500, (q15_t)0x67b5, (q15_t)0xb4fb, (q15_t)0x67b2, (q15_t)0xb4f6, + (q15_t)0x67ae, (q15_t)0xb4f1, (q15_t)0x67aa, (q15_t)0xb4ec, (q15_t)0x67a6, (q15_t)0xb4e7, (q15_t)0x67a3, (q15_t)0xb4e1, + (q15_t)0x679f, (q15_t)0xb4dc, (q15_t)0x679b, (q15_t)0xb4d7, (q15_t)0x6798, (q15_t)0xb4d2, (q15_t)0x6794, (q15_t)0xb4cd, + (q15_t)0x6790, (q15_t)0xb4c8, (q15_t)0x678d, (q15_t)0xb4c3, (q15_t)0x6789, (q15_t)0xb4be, (q15_t)0x6785, (q15_t)0xb4b9, + (q15_t)0x6782, (q15_t)0xb4b4, (q15_t)0x677e, (q15_t)0xb4af, (q15_t)0x677a, (q15_t)0xb4aa, (q15_t)0x6776, (q15_t)0xb4a4, + (q15_t)0x6773, (q15_t)0xb49f, (q15_t)0x676f, (q15_t)0xb49a, (q15_t)0x676b, (q15_t)0xb495, (q15_t)0x6768, (q15_t)0xb490, + (q15_t)0x6764, (q15_t)0xb48b, (q15_t)0x6760, (q15_t)0xb486, (q15_t)0x675d, (q15_t)0xb481, (q15_t)0x6759, (q15_t)0xb47c, + (q15_t)0x6755, (q15_t)0xb477, (q15_t)0x6751, (q15_t)0xb472, (q15_t)0x674e, (q15_t)0xb46d, (q15_t)0x674a, (q15_t)0xb468, + (q15_t)0x6746, (q15_t)0xb462, (q15_t)0x6743, (q15_t)0xb45d, (q15_t)0x673f, (q15_t)0xb458, (q15_t)0x673b, (q15_t)0xb453, + (q15_t)0x6737, (q15_t)0xb44e, (q15_t)0x6734, (q15_t)0xb449, (q15_t)0x6730, (q15_t)0xb444, (q15_t)0x672c, (q15_t)0xb43f, + (q15_t)0x6729, (q15_t)0xb43a, (q15_t)0x6725, (q15_t)0xb435, (q15_t)0x6721, (q15_t)0xb430, (q15_t)0x671d, (q15_t)0xb42b, + (q15_t)0x671a, (q15_t)0xb426, (q15_t)0x6716, (q15_t)0xb421, (q15_t)0x6712, (q15_t)0xb41c, (q15_t)0x670e, (q15_t)0xb417, + (q15_t)0x670b, (q15_t)0xb411, (q15_t)0x6707, (q15_t)0xb40c, (q15_t)0x6703, (q15_t)0xb407, (q15_t)0x6700, (q15_t)0xb402, + (q15_t)0x66fc, (q15_t)0xb3fd, (q15_t)0x66f8, (q15_t)0xb3f8, (q15_t)0x66f4, (q15_t)0xb3f3, (q15_t)0x66f1, (q15_t)0xb3ee, + (q15_t)0x66ed, (q15_t)0xb3e9, (q15_t)0x66e9, (q15_t)0xb3e4, (q15_t)0x66e5, (q15_t)0xb3df, (q15_t)0x66e2, (q15_t)0xb3da, + (q15_t)0x66de, (q15_t)0xb3d5, (q15_t)0x66da, (q15_t)0xb3d0, (q15_t)0x66d6, (q15_t)0xb3cb, (q15_t)0x66d3, (q15_t)0xb3c6, + (q15_t)0x66cf, (q15_t)0xb3c1, (q15_t)0x66cb, (q15_t)0xb3bc, (q15_t)0x66c8, (q15_t)0xb3b7, (q15_t)0x66c4, (q15_t)0xb3b1, + (q15_t)0x66c0, (q15_t)0xb3ac, (q15_t)0x66bc, (q15_t)0xb3a7, (q15_t)0x66b9, (q15_t)0xb3a2, (q15_t)0x66b5, (q15_t)0xb39d, + (q15_t)0x66b1, (q15_t)0xb398, (q15_t)0x66ad, (q15_t)0xb393, (q15_t)0x66aa, (q15_t)0xb38e, (q15_t)0x66a6, (q15_t)0xb389, + (q15_t)0x66a2, (q15_t)0xb384, (q15_t)0x669e, (q15_t)0xb37f, (q15_t)0x669b, (q15_t)0xb37a, (q15_t)0x6697, (q15_t)0xb375, + (q15_t)0x6693, (q15_t)0xb370, (q15_t)0x668f, (q15_t)0xb36b, (q15_t)0x668b, (q15_t)0xb366, (q15_t)0x6688, (q15_t)0xb361, + (q15_t)0x6684, (q15_t)0xb35c, (q15_t)0x6680, (q15_t)0xb357, (q15_t)0x667c, (q15_t)0xb352, (q15_t)0x6679, (q15_t)0xb34d, + (q15_t)0x6675, (q15_t)0xb348, (q15_t)0x6671, (q15_t)0xb343, (q15_t)0x666d, (q15_t)0xb33e, (q15_t)0x666a, (q15_t)0xb339, + (q15_t)0x6666, (q15_t)0xb334, (q15_t)0x6662, (q15_t)0xb32f, (q15_t)0x665e, (q15_t)0xb32a, (q15_t)0x665b, (q15_t)0xb325, + (q15_t)0x6657, (q15_t)0xb31f, (q15_t)0x6653, (q15_t)0xb31a, (q15_t)0x664f, (q15_t)0xb315, (q15_t)0x664b, (q15_t)0xb310, + (q15_t)0x6648, (q15_t)0xb30b, (q15_t)0x6644, (q15_t)0xb306, (q15_t)0x6640, (q15_t)0xb301, (q15_t)0x663c, (q15_t)0xb2fc, + (q15_t)0x6639, (q15_t)0xb2f7, (q15_t)0x6635, (q15_t)0xb2f2, (q15_t)0x6631, (q15_t)0xb2ed, (q15_t)0x662d, (q15_t)0xb2e8, + (q15_t)0x6629, (q15_t)0xb2e3, (q15_t)0x6626, (q15_t)0xb2de, (q15_t)0x6622, (q15_t)0xb2d9, (q15_t)0x661e, (q15_t)0xb2d4, + (q15_t)0x661a, (q15_t)0xb2cf, (q15_t)0x6616, (q15_t)0xb2ca, (q15_t)0x6613, (q15_t)0xb2c5, (q15_t)0x660f, (q15_t)0xb2c0, + (q15_t)0x660b, (q15_t)0xb2bb, (q15_t)0x6607, (q15_t)0xb2b6, (q15_t)0x6603, (q15_t)0xb2b1, (q15_t)0x6600, (q15_t)0xb2ac, + (q15_t)0x65fc, (q15_t)0xb2a7, (q15_t)0x65f8, (q15_t)0xb2a2, (q15_t)0x65f4, (q15_t)0xb29d, (q15_t)0x65f0, (q15_t)0xb298, + (q15_t)0x65ed, (q15_t)0xb293, (q15_t)0x65e9, (q15_t)0xb28e, (q15_t)0x65e5, (q15_t)0xb289, (q15_t)0x65e1, (q15_t)0xb284, + (q15_t)0x65dd, (q15_t)0xb27f, (q15_t)0x65da, (q15_t)0xb27a, (q15_t)0x65d6, (q15_t)0xb275, (q15_t)0x65d2, (q15_t)0xb270, + (q15_t)0x65ce, (q15_t)0xb26b, (q15_t)0x65ca, (q15_t)0xb266, (q15_t)0x65c7, (q15_t)0xb261, (q15_t)0x65c3, (q15_t)0xb25c, + (q15_t)0x65bf, (q15_t)0xb257, (q15_t)0x65bb, (q15_t)0xb252, (q15_t)0x65b7, (q15_t)0xb24d, (q15_t)0x65b4, (q15_t)0xb248, + (q15_t)0x65b0, (q15_t)0xb243, (q15_t)0x65ac, (q15_t)0xb23e, (q15_t)0x65a8, (q15_t)0xb239, (q15_t)0x65a4, (q15_t)0xb234, + (q15_t)0x65a0, (q15_t)0xb22f, (q15_t)0x659d, (q15_t)0xb22a, (q15_t)0x6599, (q15_t)0xb225, (q15_t)0x6595, (q15_t)0xb220, + (q15_t)0x6591, (q15_t)0xb21b, (q15_t)0x658d, (q15_t)0xb216, (q15_t)0x658a, (q15_t)0xb211, (q15_t)0x6586, (q15_t)0xb20c, + (q15_t)0x6582, (q15_t)0xb207, (q15_t)0x657e, (q15_t)0xb202, (q15_t)0x657a, (q15_t)0xb1fd, (q15_t)0x6576, (q15_t)0xb1f8, + (q15_t)0x6573, (q15_t)0xb1f3, (q15_t)0x656f, (q15_t)0xb1ee, (q15_t)0x656b, (q15_t)0xb1e9, (q15_t)0x6567, (q15_t)0xb1e4, + (q15_t)0x6563, (q15_t)0xb1df, (q15_t)0x655f, (q15_t)0xb1da, (q15_t)0x655c, (q15_t)0xb1d6, (q15_t)0x6558, (q15_t)0xb1d1, + (q15_t)0x6554, (q15_t)0xb1cc, (q15_t)0x6550, (q15_t)0xb1c7, (q15_t)0x654c, (q15_t)0xb1c2, (q15_t)0x6548, (q15_t)0xb1bd, + (q15_t)0x6545, (q15_t)0xb1b8, (q15_t)0x6541, (q15_t)0xb1b3, (q15_t)0x653d, (q15_t)0xb1ae, (q15_t)0x6539, (q15_t)0xb1a9, + (q15_t)0x6535, (q15_t)0xb1a4, (q15_t)0x6531, (q15_t)0xb19f, (q15_t)0x652d, (q15_t)0xb19a, (q15_t)0x652a, (q15_t)0xb195, + (q15_t)0x6526, (q15_t)0xb190, (q15_t)0x6522, (q15_t)0xb18b, (q15_t)0x651e, (q15_t)0xb186, (q15_t)0x651a, (q15_t)0xb181, + (q15_t)0x6516, (q15_t)0xb17c, (q15_t)0x6513, (q15_t)0xb177, (q15_t)0x650f, (q15_t)0xb172, (q15_t)0x650b, (q15_t)0xb16d, + (q15_t)0x6507, (q15_t)0xb168, (q15_t)0x6503, (q15_t)0xb163, (q15_t)0x64ff, (q15_t)0xb15e, (q15_t)0x64fb, (q15_t)0xb159, + (q15_t)0x64f7, (q15_t)0xb154, (q15_t)0x64f4, (q15_t)0xb14f, (q15_t)0x64f0, (q15_t)0xb14a, (q15_t)0x64ec, (q15_t)0xb146, + (q15_t)0x64e8, (q15_t)0xb141, (q15_t)0x64e4, (q15_t)0xb13c, (q15_t)0x64e0, (q15_t)0xb137, (q15_t)0x64dc, (q15_t)0xb132, + (q15_t)0x64d9, (q15_t)0xb12d, (q15_t)0x64d5, (q15_t)0xb128, (q15_t)0x64d1, (q15_t)0xb123, (q15_t)0x64cd, (q15_t)0xb11e, + (q15_t)0x64c9, (q15_t)0xb119, (q15_t)0x64c5, (q15_t)0xb114, (q15_t)0x64c1, (q15_t)0xb10f, (q15_t)0x64bd, (q15_t)0xb10a, + (q15_t)0x64ba, (q15_t)0xb105, (q15_t)0x64b6, (q15_t)0xb100, (q15_t)0x64b2, (q15_t)0xb0fb, (q15_t)0x64ae, (q15_t)0xb0f6, + (q15_t)0x64aa, (q15_t)0xb0f1, (q15_t)0x64a6, (q15_t)0xb0ec, (q15_t)0x64a2, (q15_t)0xb0e8, (q15_t)0x649e, (q15_t)0xb0e3, + (q15_t)0x649b, (q15_t)0xb0de, (q15_t)0x6497, (q15_t)0xb0d9, (q15_t)0x6493, (q15_t)0xb0d4, (q15_t)0x648f, (q15_t)0xb0cf, + (q15_t)0x648b, (q15_t)0xb0ca, (q15_t)0x6487, (q15_t)0xb0c5, (q15_t)0x6483, (q15_t)0xb0c0, (q15_t)0x647f, (q15_t)0xb0bb, + (q15_t)0x647b, (q15_t)0xb0b6, (q15_t)0x6478, (q15_t)0xb0b1, (q15_t)0x6474, (q15_t)0xb0ac, (q15_t)0x6470, (q15_t)0xb0a7, + (q15_t)0x646c, (q15_t)0xb0a2, (q15_t)0x6468, (q15_t)0xb09e, (q15_t)0x6464, (q15_t)0xb099, (q15_t)0x6460, (q15_t)0xb094, + (q15_t)0x645c, (q15_t)0xb08f, (q15_t)0x6458, (q15_t)0xb08a, (q15_t)0x6454, (q15_t)0xb085, (q15_t)0x6451, (q15_t)0xb080, + (q15_t)0x644d, (q15_t)0xb07b, (q15_t)0x6449, (q15_t)0xb076, (q15_t)0x6445, (q15_t)0xb071, (q15_t)0x6441, (q15_t)0xb06c, + (q15_t)0x643d, (q15_t)0xb067, (q15_t)0x6439, (q15_t)0xb062, (q15_t)0x6435, (q15_t)0xb05e, (q15_t)0x6431, (q15_t)0xb059, + (q15_t)0x642d, (q15_t)0xb054, (q15_t)0x6429, (q15_t)0xb04f, (q15_t)0x6426, (q15_t)0xb04a, (q15_t)0x6422, (q15_t)0xb045, + (q15_t)0x641e, (q15_t)0xb040, (q15_t)0x641a, (q15_t)0xb03b, (q15_t)0x6416, (q15_t)0xb036, (q15_t)0x6412, (q15_t)0xb031, + (q15_t)0x640e, (q15_t)0xb02c, (q15_t)0x640a, (q15_t)0xb027, (q15_t)0x6406, (q15_t)0xb023, (q15_t)0x6402, (q15_t)0xb01e, + (q15_t)0x63fe, (q15_t)0xb019, (q15_t)0x63fa, (q15_t)0xb014, (q15_t)0x63f7, (q15_t)0xb00f, (q15_t)0x63f3, (q15_t)0xb00a, + (q15_t)0x63ef, (q15_t)0xb005, (q15_t)0x63eb, (q15_t)0xb000, (q15_t)0x63e7, (q15_t)0xaffb, (q15_t)0x63e3, (q15_t)0xaff6, + (q15_t)0x63df, (q15_t)0xaff1, (q15_t)0x63db, (q15_t)0xafed, (q15_t)0x63d7, (q15_t)0xafe8, (q15_t)0x63d3, (q15_t)0xafe3, + (q15_t)0x63cf, (q15_t)0xafde, (q15_t)0x63cb, (q15_t)0xafd9, (q15_t)0x63c7, (q15_t)0xafd4, (q15_t)0x63c3, (q15_t)0xafcf, + (q15_t)0x63c0, (q15_t)0xafca, (q15_t)0x63bc, (q15_t)0xafc5, (q15_t)0x63b8, (q15_t)0xafc1, (q15_t)0x63b4, (q15_t)0xafbc, + (q15_t)0x63b0, (q15_t)0xafb7, (q15_t)0x63ac, (q15_t)0xafb2, (q15_t)0x63a8, (q15_t)0xafad, (q15_t)0x63a4, (q15_t)0xafa8, + (q15_t)0x63a0, (q15_t)0xafa3, (q15_t)0x639c, (q15_t)0xaf9e, (q15_t)0x6398, (q15_t)0xaf99, (q15_t)0x6394, (q15_t)0xaf94, + (q15_t)0x6390, (q15_t)0xaf90, (q15_t)0x638c, (q15_t)0xaf8b, (q15_t)0x6388, (q15_t)0xaf86, (q15_t)0x6384, (q15_t)0xaf81, + (q15_t)0x6380, (q15_t)0xaf7c, (q15_t)0x637c, (q15_t)0xaf77, (q15_t)0x6378, (q15_t)0xaf72, (q15_t)0x6375, (q15_t)0xaf6d, + (q15_t)0x6371, (q15_t)0xaf69, (q15_t)0x636d, (q15_t)0xaf64, (q15_t)0x6369, (q15_t)0xaf5f, (q15_t)0x6365, (q15_t)0xaf5a, + (q15_t)0x6361, (q15_t)0xaf55, (q15_t)0x635d, (q15_t)0xaf50, (q15_t)0x6359, (q15_t)0xaf4b, (q15_t)0x6355, (q15_t)0xaf46, + (q15_t)0x6351, (q15_t)0xaf41, (q15_t)0x634d, (q15_t)0xaf3d, (q15_t)0x6349, (q15_t)0xaf38, (q15_t)0x6345, (q15_t)0xaf33, + (q15_t)0x6341, (q15_t)0xaf2e, (q15_t)0x633d, (q15_t)0xaf29, (q15_t)0x6339, (q15_t)0xaf24, (q15_t)0x6335, (q15_t)0xaf1f, + (q15_t)0x6331, (q15_t)0xaf1b, (q15_t)0x632d, (q15_t)0xaf16, (q15_t)0x6329, (q15_t)0xaf11, (q15_t)0x6325, (q15_t)0xaf0c, + (q15_t)0x6321, (q15_t)0xaf07, (q15_t)0x631d, (q15_t)0xaf02, (q15_t)0x6319, (q15_t)0xaefd, (q15_t)0x6315, (q15_t)0xaef8, + (q15_t)0x6311, (q15_t)0xaef4, (q15_t)0x630d, (q15_t)0xaeef, (q15_t)0x6309, (q15_t)0xaeea, (q15_t)0x6305, (q15_t)0xaee5, + (q15_t)0x6301, (q15_t)0xaee0, (q15_t)0x62fd, (q15_t)0xaedb, (q15_t)0x62f9, (q15_t)0xaed6, (q15_t)0x62f5, (q15_t)0xaed2, + (q15_t)0x62f2, (q15_t)0xaecd, (q15_t)0x62ee, (q15_t)0xaec8, (q15_t)0x62ea, (q15_t)0xaec3, (q15_t)0x62e6, (q15_t)0xaebe, + (q15_t)0x62e2, (q15_t)0xaeb9, (q15_t)0x62de, (q15_t)0xaeb4, (q15_t)0x62da, (q15_t)0xaeb0, (q15_t)0x62d6, (q15_t)0xaeab, + (q15_t)0x62d2, (q15_t)0xaea6, (q15_t)0x62ce, (q15_t)0xaea1, (q15_t)0x62ca, (q15_t)0xae9c, (q15_t)0x62c6, (q15_t)0xae97, + (q15_t)0x62c2, (q15_t)0xae92, (q15_t)0x62be, (q15_t)0xae8e, (q15_t)0x62ba, (q15_t)0xae89, (q15_t)0x62b6, (q15_t)0xae84, + (q15_t)0x62b2, (q15_t)0xae7f, (q15_t)0x62ae, (q15_t)0xae7a, (q15_t)0x62aa, (q15_t)0xae75, (q15_t)0x62a6, (q15_t)0xae71, + (q15_t)0x62a2, (q15_t)0xae6c, (q15_t)0x629e, (q15_t)0xae67, (q15_t)0x629a, (q15_t)0xae62, (q15_t)0x6296, (q15_t)0xae5d, + (q15_t)0x6292, (q15_t)0xae58, (q15_t)0x628e, (q15_t)0xae54, (q15_t)0x628a, (q15_t)0xae4f, (q15_t)0x6286, (q15_t)0xae4a, + (q15_t)0x6282, (q15_t)0xae45, (q15_t)0x627e, (q15_t)0xae40, (q15_t)0x627a, (q15_t)0xae3b, (q15_t)0x6275, (q15_t)0xae37, + (q15_t)0x6271, (q15_t)0xae32, (q15_t)0x626d, (q15_t)0xae2d, (q15_t)0x6269, (q15_t)0xae28, (q15_t)0x6265, (q15_t)0xae23, + (q15_t)0x6261, (q15_t)0xae1e, (q15_t)0x625d, (q15_t)0xae1a, (q15_t)0x6259, (q15_t)0xae15, (q15_t)0x6255, (q15_t)0xae10, + (q15_t)0x6251, (q15_t)0xae0b, (q15_t)0x624d, (q15_t)0xae06, (q15_t)0x6249, (q15_t)0xae01, (q15_t)0x6245, (q15_t)0xadfd, + (q15_t)0x6241, (q15_t)0xadf8, (q15_t)0x623d, (q15_t)0xadf3, (q15_t)0x6239, (q15_t)0xadee, (q15_t)0x6235, (q15_t)0xade9, + (q15_t)0x6231, (q15_t)0xade4, (q15_t)0x622d, (q15_t)0xade0, (q15_t)0x6229, (q15_t)0xaddb, (q15_t)0x6225, (q15_t)0xadd6, + (q15_t)0x6221, (q15_t)0xadd1, (q15_t)0x621d, (q15_t)0xadcc, (q15_t)0x6219, (q15_t)0xadc8, (q15_t)0x6215, (q15_t)0xadc3, + (q15_t)0x6211, (q15_t)0xadbe, (q15_t)0x620d, (q15_t)0xadb9, (q15_t)0x6209, (q15_t)0xadb4, (q15_t)0x6205, (q15_t)0xadaf, + (q15_t)0x6201, (q15_t)0xadab, (q15_t)0x61fd, (q15_t)0xada6, (q15_t)0x61f9, (q15_t)0xada1, (q15_t)0x61f5, (q15_t)0xad9c, + (q15_t)0x61f1, (q15_t)0xad97, (q15_t)0x61ec, (q15_t)0xad93, (q15_t)0x61e8, (q15_t)0xad8e, (q15_t)0x61e4, (q15_t)0xad89, + (q15_t)0x61e0, (q15_t)0xad84, (q15_t)0x61dc, (q15_t)0xad7f, (q15_t)0x61d8, (q15_t)0xad7b, (q15_t)0x61d4, (q15_t)0xad76, + (q15_t)0x61d0, (q15_t)0xad71, (q15_t)0x61cc, (q15_t)0xad6c, (q15_t)0x61c8, (q15_t)0xad67, (q15_t)0x61c4, (q15_t)0xad63, + (q15_t)0x61c0, (q15_t)0xad5e, (q15_t)0x61bc, (q15_t)0xad59, (q15_t)0x61b8, (q15_t)0xad54, (q15_t)0x61b4, (q15_t)0xad4f, + (q15_t)0x61b0, (q15_t)0xad4b, (q15_t)0x61ac, (q15_t)0xad46, (q15_t)0x61a8, (q15_t)0xad41, (q15_t)0x61a3, (q15_t)0xad3c, + (q15_t)0x619f, (q15_t)0xad37, (q15_t)0x619b, (q15_t)0xad33, (q15_t)0x6197, (q15_t)0xad2e, (q15_t)0x6193, (q15_t)0xad29, + (q15_t)0x618f, (q15_t)0xad24, (q15_t)0x618b, (q15_t)0xad1f, (q15_t)0x6187, (q15_t)0xad1b, (q15_t)0x6183, (q15_t)0xad16, + (q15_t)0x617f, (q15_t)0xad11, (q15_t)0x617b, (q15_t)0xad0c, (q15_t)0x6177, (q15_t)0xad08, (q15_t)0x6173, (q15_t)0xad03, + (q15_t)0x616f, (q15_t)0xacfe, (q15_t)0x616b, (q15_t)0xacf9, (q15_t)0x6166, (q15_t)0xacf4, (q15_t)0x6162, (q15_t)0xacf0, + (q15_t)0x615e, (q15_t)0xaceb, (q15_t)0x615a, (q15_t)0xace6, (q15_t)0x6156, (q15_t)0xace1, (q15_t)0x6152, (q15_t)0xacdd, + (q15_t)0x614e, (q15_t)0xacd8, (q15_t)0x614a, (q15_t)0xacd3, (q15_t)0x6146, (q15_t)0xacce, (q15_t)0x6142, (q15_t)0xacc9, + (q15_t)0x613e, (q15_t)0xacc5, (q15_t)0x613a, (q15_t)0xacc0, (q15_t)0x6135, (q15_t)0xacbb, (q15_t)0x6131, (q15_t)0xacb6, + (q15_t)0x612d, (q15_t)0xacb2, (q15_t)0x6129, (q15_t)0xacad, (q15_t)0x6125, (q15_t)0xaca8, (q15_t)0x6121, (q15_t)0xaca3, + (q15_t)0x611d, (q15_t)0xac9e, (q15_t)0x6119, (q15_t)0xac9a, (q15_t)0x6115, (q15_t)0xac95, (q15_t)0x6111, (q15_t)0xac90, + (q15_t)0x610d, (q15_t)0xac8b, (q15_t)0x6108, (q15_t)0xac87, (q15_t)0x6104, (q15_t)0xac82, (q15_t)0x6100, (q15_t)0xac7d, + (q15_t)0x60fc, (q15_t)0xac78, (q15_t)0x60f8, (q15_t)0xac74, (q15_t)0x60f4, (q15_t)0xac6f, (q15_t)0x60f0, (q15_t)0xac6a, + (q15_t)0x60ec, (q15_t)0xac65, (q15_t)0x60e8, (q15_t)0xac61, (q15_t)0x60e4, (q15_t)0xac5c, (q15_t)0x60df, (q15_t)0xac57, + (q15_t)0x60db, (q15_t)0xac52, (q15_t)0x60d7, (q15_t)0xac4e, (q15_t)0x60d3, (q15_t)0xac49, (q15_t)0x60cf, (q15_t)0xac44, + (q15_t)0x60cb, (q15_t)0xac3f, (q15_t)0x60c7, (q15_t)0xac3b, (q15_t)0x60c3, (q15_t)0xac36, (q15_t)0x60bf, (q15_t)0xac31, + (q15_t)0x60ba, (q15_t)0xac2c, (q15_t)0x60b6, (q15_t)0xac28, (q15_t)0x60b2, (q15_t)0xac23, (q15_t)0x60ae, (q15_t)0xac1e, + (q15_t)0x60aa, (q15_t)0xac19, (q15_t)0x60a6, (q15_t)0xac15, (q15_t)0x60a2, (q15_t)0xac10, (q15_t)0x609e, (q15_t)0xac0b, + (q15_t)0x6099, (q15_t)0xac06, (q15_t)0x6095, (q15_t)0xac02, (q15_t)0x6091, (q15_t)0xabfd, (q15_t)0x608d, (q15_t)0xabf8, + (q15_t)0x6089, (q15_t)0xabf3, (q15_t)0x6085, (q15_t)0xabef, (q15_t)0x6081, (q15_t)0xabea, (q15_t)0x607d, (q15_t)0xabe5, + (q15_t)0x6078, (q15_t)0xabe0, (q15_t)0x6074, (q15_t)0xabdc, (q15_t)0x6070, (q15_t)0xabd7, (q15_t)0x606c, (q15_t)0xabd2, + (q15_t)0x6068, (q15_t)0xabcd, (q15_t)0x6064, (q15_t)0xabc9, (q15_t)0x6060, (q15_t)0xabc4, (q15_t)0x605c, (q15_t)0xabbf, + (q15_t)0x6057, (q15_t)0xabbb, (q15_t)0x6053, (q15_t)0xabb6, (q15_t)0x604f, (q15_t)0xabb1, (q15_t)0x604b, (q15_t)0xabac, + (q15_t)0x6047, (q15_t)0xaba8, (q15_t)0x6043, (q15_t)0xaba3, (q15_t)0x603f, (q15_t)0xab9e, (q15_t)0x603a, (q15_t)0xab99, + (q15_t)0x6036, (q15_t)0xab95, (q15_t)0x6032, (q15_t)0xab90, (q15_t)0x602e, (q15_t)0xab8b, (q15_t)0x602a, (q15_t)0xab87, + (q15_t)0x6026, (q15_t)0xab82, (q15_t)0x6022, (q15_t)0xab7d, (q15_t)0x601d, (q15_t)0xab78, (q15_t)0x6019, (q15_t)0xab74, + (q15_t)0x6015, (q15_t)0xab6f, (q15_t)0x6011, (q15_t)0xab6a, (q15_t)0x600d, (q15_t)0xab66, (q15_t)0x6009, (q15_t)0xab61, + (q15_t)0x6004, (q15_t)0xab5c, (q15_t)0x6000, (q15_t)0xab57, (q15_t)0x5ffc, (q15_t)0xab53, (q15_t)0x5ff8, (q15_t)0xab4e, + (q15_t)0x5ff4, (q15_t)0xab49, (q15_t)0x5ff0, (q15_t)0xab45, (q15_t)0x5fec, (q15_t)0xab40, (q15_t)0x5fe7, (q15_t)0xab3b, + (q15_t)0x5fe3, (q15_t)0xab36, (q15_t)0x5fdf, (q15_t)0xab32, (q15_t)0x5fdb, (q15_t)0xab2d, (q15_t)0x5fd7, (q15_t)0xab28, + (q15_t)0x5fd3, (q15_t)0xab24, (q15_t)0x5fce, (q15_t)0xab1f, (q15_t)0x5fca, (q15_t)0xab1a, (q15_t)0x5fc6, (q15_t)0xab16, + (q15_t)0x5fc2, (q15_t)0xab11, (q15_t)0x5fbe, (q15_t)0xab0c, (q15_t)0x5fba, (q15_t)0xab07, (q15_t)0x5fb5, (q15_t)0xab03, + (q15_t)0x5fb1, (q15_t)0xaafe, (q15_t)0x5fad, (q15_t)0xaaf9, (q15_t)0x5fa9, (q15_t)0xaaf5, (q15_t)0x5fa5, (q15_t)0xaaf0, + (q15_t)0x5fa0, (q15_t)0xaaeb, (q15_t)0x5f9c, (q15_t)0xaae7, (q15_t)0x5f98, (q15_t)0xaae2, (q15_t)0x5f94, (q15_t)0xaadd, + (q15_t)0x5f90, (q15_t)0xaad8, (q15_t)0x5f8c, (q15_t)0xaad4, (q15_t)0x5f87, (q15_t)0xaacf, (q15_t)0x5f83, (q15_t)0xaaca, + (q15_t)0x5f7f, (q15_t)0xaac6, (q15_t)0x5f7b, (q15_t)0xaac1, (q15_t)0x5f77, (q15_t)0xaabc, (q15_t)0x5f72, (q15_t)0xaab8, + (q15_t)0x5f6e, (q15_t)0xaab3, (q15_t)0x5f6a, (q15_t)0xaaae, (q15_t)0x5f66, (q15_t)0xaaaa, (q15_t)0x5f62, (q15_t)0xaaa5, + (q15_t)0x5f5e, (q15_t)0xaaa0, (q15_t)0x5f59, (q15_t)0xaa9c, (q15_t)0x5f55, (q15_t)0xaa97, (q15_t)0x5f51, (q15_t)0xaa92, + (q15_t)0x5f4d, (q15_t)0xaa8e, (q15_t)0x5f49, (q15_t)0xaa89, (q15_t)0x5f44, (q15_t)0xaa84, (q15_t)0x5f40, (q15_t)0xaa7f, + (q15_t)0x5f3c, (q15_t)0xaa7b, (q15_t)0x5f38, (q15_t)0xaa76, (q15_t)0x5f34, (q15_t)0xaa71, (q15_t)0x5f2f, (q15_t)0xaa6d, + (q15_t)0x5f2b, (q15_t)0xaa68, (q15_t)0x5f27, (q15_t)0xaa63, (q15_t)0x5f23, (q15_t)0xaa5f, (q15_t)0x5f1f, (q15_t)0xaa5a, + (q15_t)0x5f1a, (q15_t)0xaa55, (q15_t)0x5f16, (q15_t)0xaa51, (q15_t)0x5f12, (q15_t)0xaa4c, (q15_t)0x5f0e, (q15_t)0xaa47, + (q15_t)0x5f0a, (q15_t)0xaa43, (q15_t)0x5f05, (q15_t)0xaa3e, (q15_t)0x5f01, (q15_t)0xaa39, (q15_t)0x5efd, (q15_t)0xaa35, + (q15_t)0x5ef9, (q15_t)0xaa30, (q15_t)0x5ef5, (q15_t)0xaa2b, (q15_t)0x5ef0, (q15_t)0xaa27, (q15_t)0x5eec, (q15_t)0xaa22, + (q15_t)0x5ee8, (q15_t)0xaa1d, (q15_t)0x5ee4, (q15_t)0xaa19, (q15_t)0x5edf, (q15_t)0xaa14, (q15_t)0x5edb, (q15_t)0xaa10, + (q15_t)0x5ed7, (q15_t)0xaa0b, (q15_t)0x5ed3, (q15_t)0xaa06, (q15_t)0x5ecf, (q15_t)0xaa02, (q15_t)0x5eca, (q15_t)0xa9fd, + (q15_t)0x5ec6, (q15_t)0xa9f8, (q15_t)0x5ec2, (q15_t)0xa9f4, (q15_t)0x5ebe, (q15_t)0xa9ef, (q15_t)0x5eb9, (q15_t)0xa9ea, + (q15_t)0x5eb5, (q15_t)0xa9e6, (q15_t)0x5eb1, (q15_t)0xa9e1, (q15_t)0x5ead, (q15_t)0xa9dc, (q15_t)0x5ea9, (q15_t)0xa9d8, + (q15_t)0x5ea4, (q15_t)0xa9d3, (q15_t)0x5ea0, (q15_t)0xa9ce, (q15_t)0x5e9c, (q15_t)0xa9ca, (q15_t)0x5e98, (q15_t)0xa9c5, + (q15_t)0x5e93, (q15_t)0xa9c0, (q15_t)0x5e8f, (q15_t)0xa9bc, (q15_t)0x5e8b, (q15_t)0xa9b7, (q15_t)0x5e87, (q15_t)0xa9b3, + (q15_t)0x5e82, (q15_t)0xa9ae, (q15_t)0x5e7e, (q15_t)0xa9a9, (q15_t)0x5e7a, (q15_t)0xa9a5, (q15_t)0x5e76, (q15_t)0xa9a0, + (q15_t)0x5e71, (q15_t)0xa99b, (q15_t)0x5e6d, (q15_t)0xa997, (q15_t)0x5e69, (q15_t)0xa992, (q15_t)0x5e65, (q15_t)0xa98d, + (q15_t)0x5e60, (q15_t)0xa989, (q15_t)0x5e5c, (q15_t)0xa984, (q15_t)0x5e58, (q15_t)0xa980, (q15_t)0x5e54, (q15_t)0xa97b, + (q15_t)0x5e50, (q15_t)0xa976, (q15_t)0x5e4b, (q15_t)0xa972, (q15_t)0x5e47, (q15_t)0xa96d, (q15_t)0x5e43, (q15_t)0xa968, + (q15_t)0x5e3f, (q15_t)0xa964, (q15_t)0x5e3a, (q15_t)0xa95f, (q15_t)0x5e36, (q15_t)0xa95b, (q15_t)0x5e32, (q15_t)0xa956, + (q15_t)0x5e2d, (q15_t)0xa951, (q15_t)0x5e29, (q15_t)0xa94d, (q15_t)0x5e25, (q15_t)0xa948, (q15_t)0x5e21, (q15_t)0xa943, + (q15_t)0x5e1c, (q15_t)0xa93f, (q15_t)0x5e18, (q15_t)0xa93a, (q15_t)0x5e14, (q15_t)0xa936, (q15_t)0x5e10, (q15_t)0xa931, + (q15_t)0x5e0b, (q15_t)0xa92c, (q15_t)0x5e07, (q15_t)0xa928, (q15_t)0x5e03, (q15_t)0xa923, (q15_t)0x5dff, (q15_t)0xa91e, + (q15_t)0x5dfa, (q15_t)0xa91a, (q15_t)0x5df6, (q15_t)0xa915, (q15_t)0x5df2, (q15_t)0xa911, (q15_t)0x5dee, (q15_t)0xa90c, + (q15_t)0x5de9, (q15_t)0xa907, (q15_t)0x5de5, (q15_t)0xa903, (q15_t)0x5de1, (q15_t)0xa8fe, (q15_t)0x5ddc, (q15_t)0xa8fa, + (q15_t)0x5dd8, (q15_t)0xa8f5, (q15_t)0x5dd4, (q15_t)0xa8f0, (q15_t)0x5dd0, (q15_t)0xa8ec, (q15_t)0x5dcb, (q15_t)0xa8e7, + (q15_t)0x5dc7, (q15_t)0xa8e3, (q15_t)0x5dc3, (q15_t)0xa8de, (q15_t)0x5dbf, (q15_t)0xa8d9, (q15_t)0x5dba, (q15_t)0xa8d5, + (q15_t)0x5db6, (q15_t)0xa8d0, (q15_t)0x5db2, (q15_t)0xa8cc, (q15_t)0x5dad, (q15_t)0xa8c7, (q15_t)0x5da9, (q15_t)0xa8c2, + (q15_t)0x5da5, (q15_t)0xa8be, (q15_t)0x5da1, (q15_t)0xa8b9, (q15_t)0x5d9c, (q15_t)0xa8b5, (q15_t)0x5d98, (q15_t)0xa8b0, + (q15_t)0x5d94, (q15_t)0xa8ab, (q15_t)0x5d8f, (q15_t)0xa8a7, (q15_t)0x5d8b, (q15_t)0xa8a2, (q15_t)0x5d87, (q15_t)0xa89e, + (q15_t)0x5d83, (q15_t)0xa899, (q15_t)0x5d7e, (q15_t)0xa894, (q15_t)0x5d7a, (q15_t)0xa890, (q15_t)0x5d76, (q15_t)0xa88b, + (q15_t)0x5d71, (q15_t)0xa887, (q15_t)0x5d6d, (q15_t)0xa882, (q15_t)0x5d69, (q15_t)0xa87d, (q15_t)0x5d65, (q15_t)0xa879, + (q15_t)0x5d60, (q15_t)0xa874, (q15_t)0x5d5c, (q15_t)0xa870, (q15_t)0x5d58, (q15_t)0xa86b, (q15_t)0x5d53, (q15_t)0xa867, + (q15_t)0x5d4f, (q15_t)0xa862, (q15_t)0x5d4b, (q15_t)0xa85d, (q15_t)0x5d46, (q15_t)0xa859, (q15_t)0x5d42, (q15_t)0xa854, + (q15_t)0x5d3e, (q15_t)0xa850, (q15_t)0x5d3a, (q15_t)0xa84b, (q15_t)0x5d35, (q15_t)0xa847, (q15_t)0x5d31, (q15_t)0xa842, + (q15_t)0x5d2d, (q15_t)0xa83d, (q15_t)0x5d28, (q15_t)0xa839, (q15_t)0x5d24, (q15_t)0xa834, (q15_t)0x5d20, (q15_t)0xa830, + (q15_t)0x5d1b, (q15_t)0xa82b, (q15_t)0x5d17, (q15_t)0xa827, (q15_t)0x5d13, (q15_t)0xa822, (q15_t)0x5d0e, (q15_t)0xa81d, + (q15_t)0x5d0a, (q15_t)0xa819, (q15_t)0x5d06, (q15_t)0xa814, (q15_t)0x5d01, (q15_t)0xa810, (q15_t)0x5cfd, (q15_t)0xa80b, + (q15_t)0x5cf9, (q15_t)0xa807, (q15_t)0x5cf5, (q15_t)0xa802, (q15_t)0x5cf0, (q15_t)0xa7fd, (q15_t)0x5cec, (q15_t)0xa7f9, + (q15_t)0x5ce8, (q15_t)0xa7f4, (q15_t)0x5ce3, (q15_t)0xa7f0, (q15_t)0x5cdf, (q15_t)0xa7eb, (q15_t)0x5cdb, (q15_t)0xa7e7, + (q15_t)0x5cd6, (q15_t)0xa7e2, (q15_t)0x5cd2, (q15_t)0xa7de, (q15_t)0x5cce, (q15_t)0xa7d9, (q15_t)0x5cc9, (q15_t)0xa7d4, + (q15_t)0x5cc5, (q15_t)0xa7d0, (q15_t)0x5cc1, (q15_t)0xa7cb, (q15_t)0x5cbc, (q15_t)0xa7c7, (q15_t)0x5cb8, (q15_t)0xa7c2, + (q15_t)0x5cb4, (q15_t)0xa7be, (q15_t)0x5caf, (q15_t)0xa7b9, (q15_t)0x5cab, (q15_t)0xa7b5, (q15_t)0x5ca7, (q15_t)0xa7b0, + (q15_t)0x5ca2, (q15_t)0xa7ab, (q15_t)0x5c9e, (q15_t)0xa7a7, (q15_t)0x5c9a, (q15_t)0xa7a2, (q15_t)0x5c95, (q15_t)0xa79e, + (q15_t)0x5c91, (q15_t)0xa799, (q15_t)0x5c8d, (q15_t)0xa795, (q15_t)0x5c88, (q15_t)0xa790, (q15_t)0x5c84, (q15_t)0xa78c, + (q15_t)0x5c80, (q15_t)0xa787, (q15_t)0x5c7b, (q15_t)0xa783, (q15_t)0x5c77, (q15_t)0xa77e, (q15_t)0x5c73, (q15_t)0xa779, + (q15_t)0x5c6e, (q15_t)0xa775, (q15_t)0x5c6a, (q15_t)0xa770, (q15_t)0x5c66, (q15_t)0xa76c, (q15_t)0x5c61, (q15_t)0xa767, + (q15_t)0x5c5d, (q15_t)0xa763, (q15_t)0x5c58, (q15_t)0xa75e, (q15_t)0x5c54, (q15_t)0xa75a, (q15_t)0x5c50, (q15_t)0xa755, + (q15_t)0x5c4b, (q15_t)0xa751, (q15_t)0x5c47, (q15_t)0xa74c, (q15_t)0x5c43, (q15_t)0xa748, (q15_t)0x5c3e, (q15_t)0xa743, + (q15_t)0x5c3a, (q15_t)0xa73f, (q15_t)0x5c36, (q15_t)0xa73a, (q15_t)0x5c31, (q15_t)0xa735, (q15_t)0x5c2d, (q15_t)0xa731, + (q15_t)0x5c29, (q15_t)0xa72c, (q15_t)0x5c24, (q15_t)0xa728, (q15_t)0x5c20, (q15_t)0xa723, (q15_t)0x5c1b, (q15_t)0xa71f, + (q15_t)0x5c17, (q15_t)0xa71a, (q15_t)0x5c13, (q15_t)0xa716, (q15_t)0x5c0e, (q15_t)0xa711, (q15_t)0x5c0a, (q15_t)0xa70d, + (q15_t)0x5c06, (q15_t)0xa708, (q15_t)0x5c01, (q15_t)0xa704, (q15_t)0x5bfd, (q15_t)0xa6ff, (q15_t)0x5bf9, (q15_t)0xa6fb, + (q15_t)0x5bf4, (q15_t)0xa6f6, (q15_t)0x5bf0, (q15_t)0xa6f2, (q15_t)0x5beb, (q15_t)0xa6ed, (q15_t)0x5be7, (q15_t)0xa6e9, + (q15_t)0x5be3, (q15_t)0xa6e4, (q15_t)0x5bde, (q15_t)0xa6e0, (q15_t)0x5bda, (q15_t)0xa6db, (q15_t)0x5bd6, (q15_t)0xa6d7, + (q15_t)0x5bd1, (q15_t)0xa6d2, (q15_t)0x5bcd, (q15_t)0xa6ce, (q15_t)0x5bc8, (q15_t)0xa6c9, (q15_t)0x5bc4, (q15_t)0xa6c5, + (q15_t)0x5bc0, (q15_t)0xa6c0, (q15_t)0x5bbb, (q15_t)0xa6bc, (q15_t)0x5bb7, (q15_t)0xa6b7, (q15_t)0x5bb2, (q15_t)0xa6b3, + (q15_t)0x5bae, (q15_t)0xa6ae, (q15_t)0x5baa, (q15_t)0xa6aa, (q15_t)0x5ba5, (q15_t)0xa6a5, (q15_t)0x5ba1, (q15_t)0xa6a1, + (q15_t)0x5b9d, (q15_t)0xa69c, (q15_t)0x5b98, (q15_t)0xa698, (q15_t)0x5b94, (q15_t)0xa693, (q15_t)0x5b8f, (q15_t)0xa68f, + (q15_t)0x5b8b, (q15_t)0xa68a, (q15_t)0x5b87, (q15_t)0xa686, (q15_t)0x5b82, (q15_t)0xa681, (q15_t)0x5b7e, (q15_t)0xa67d, + (q15_t)0x5b79, (q15_t)0xa678, (q15_t)0x5b75, (q15_t)0xa674, (q15_t)0x5b71, (q15_t)0xa66f, (q15_t)0x5b6c, (q15_t)0xa66b, + (q15_t)0x5b68, (q15_t)0xa666, (q15_t)0x5b63, (q15_t)0xa662, (q15_t)0x5b5f, (q15_t)0xa65d, (q15_t)0x5b5b, (q15_t)0xa659, + (q15_t)0x5b56, (q15_t)0xa654, (q15_t)0x5b52, (q15_t)0xa650, (q15_t)0x5b4d, (q15_t)0xa64b, (q15_t)0x5b49, (q15_t)0xa647, + (q15_t)0x5b45, (q15_t)0xa642, (q15_t)0x5b40, (q15_t)0xa63e, (q15_t)0x5b3c, (q15_t)0xa639, (q15_t)0x5b37, (q15_t)0xa635, + (q15_t)0x5b33, (q15_t)0xa630, (q15_t)0x5b2f, (q15_t)0xa62c, (q15_t)0x5b2a, (q15_t)0xa627, (q15_t)0x5b26, (q15_t)0xa623, + (q15_t)0x5b21, (q15_t)0xa61f, (q15_t)0x5b1d, (q15_t)0xa61a, (q15_t)0x5b19, (q15_t)0xa616, (q15_t)0x5b14, (q15_t)0xa611, + (q15_t)0x5b10, (q15_t)0xa60d, (q15_t)0x5b0b, (q15_t)0xa608, (q15_t)0x5b07, (q15_t)0xa604, (q15_t)0x5b02, (q15_t)0xa5ff, + (q15_t)0x5afe, (q15_t)0xa5fb, (q15_t)0x5afa, (q15_t)0xa5f6, (q15_t)0x5af5, (q15_t)0xa5f2, (q15_t)0x5af1, (q15_t)0xa5ed, + (q15_t)0x5aec, (q15_t)0xa5e9, (q15_t)0x5ae8, (q15_t)0xa5e4, (q15_t)0x5ae4, (q15_t)0xa5e0, (q15_t)0x5adf, (q15_t)0xa5dc, + (q15_t)0x5adb, (q15_t)0xa5d7, (q15_t)0x5ad6, (q15_t)0xa5d3, (q15_t)0x5ad2, (q15_t)0xa5ce, (q15_t)0x5acd, (q15_t)0xa5ca, + (q15_t)0x5ac9, (q15_t)0xa5c5, (q15_t)0x5ac5, (q15_t)0xa5c1, (q15_t)0x5ac0, (q15_t)0xa5bc, (q15_t)0x5abc, (q15_t)0xa5b8, + (q15_t)0x5ab7, (q15_t)0xa5b3, (q15_t)0x5ab3, (q15_t)0xa5af, (q15_t)0x5aae, (q15_t)0xa5aa, (q15_t)0x5aaa, (q15_t)0xa5a6, + (q15_t)0x5aa5, (q15_t)0xa5a2, (q15_t)0x5aa1, (q15_t)0xa59d, (q15_t)0x5a9d, (q15_t)0xa599, (q15_t)0x5a98, (q15_t)0xa594, + (q15_t)0x5a94, (q15_t)0xa590, (q15_t)0x5a8f, (q15_t)0xa58b, (q15_t)0x5a8b, (q15_t)0xa587, (q15_t)0x5a86, (q15_t)0xa582, + (q15_t)0x5a82, (q15_t)0xa57e, (q15_t)0x5a7e, (q15_t)0xa57a, (q15_t)0x5a79, (q15_t)0xa575, (q15_t)0x5a75, (q15_t)0xa571, + (q15_t)0x5a70, (q15_t)0xa56c, (q15_t)0x5a6c, (q15_t)0xa568, (q15_t)0x5a67, (q15_t)0xa563, (q15_t)0x5a63, (q15_t)0xa55f, + (q15_t)0x5a5e, (q15_t)0xa55b, (q15_t)0x5a5a, (q15_t)0xa556, (q15_t)0x5a56, (q15_t)0xa552, (q15_t)0x5a51, (q15_t)0xa54d, + (q15_t)0x5a4d, (q15_t)0xa549, (q15_t)0x5a48, (q15_t)0xa544, (q15_t)0x5a44, (q15_t)0xa540, (q15_t)0x5a3f, (q15_t)0xa53b, + (q15_t)0x5a3b, (q15_t)0xa537, (q15_t)0x5a36, (q15_t)0xa533, (q15_t)0x5a32, (q15_t)0xa52e, (q15_t)0x5a2d, (q15_t)0xa52a, + (q15_t)0x5a29, (q15_t)0xa525, (q15_t)0x5a24, (q15_t)0xa521, (q15_t)0x5a20, (q15_t)0xa51c, (q15_t)0x5a1c, (q15_t)0xa518, + (q15_t)0x5a17, (q15_t)0xa514, (q15_t)0x5a13, (q15_t)0xa50f, (q15_t)0x5a0e, (q15_t)0xa50b, (q15_t)0x5a0a, (q15_t)0xa506, + (q15_t)0x5a05, (q15_t)0xa502, (q15_t)0x5a01, (q15_t)0xa4fe, (q15_t)0x59fc, (q15_t)0xa4f9, (q15_t)0x59f8, (q15_t)0xa4f5, + (q15_t)0x59f3, (q15_t)0xa4f0, (q15_t)0x59ef, (q15_t)0xa4ec, (q15_t)0x59ea, (q15_t)0xa4e7, (q15_t)0x59e6, (q15_t)0xa4e3, + (q15_t)0x59e1, (q15_t)0xa4df, (q15_t)0x59dd, (q15_t)0xa4da, (q15_t)0x59d9, (q15_t)0xa4d6, (q15_t)0x59d4, (q15_t)0xa4d1, + (q15_t)0x59d0, (q15_t)0xa4cd, (q15_t)0x59cb, (q15_t)0xa4c9, (q15_t)0x59c7, (q15_t)0xa4c4, (q15_t)0x59c2, (q15_t)0xa4c0, + (q15_t)0x59be, (q15_t)0xa4bb, (q15_t)0x59b9, (q15_t)0xa4b7, (q15_t)0x59b5, (q15_t)0xa4b3, (q15_t)0x59b0, (q15_t)0xa4ae, + (q15_t)0x59ac, (q15_t)0xa4aa, (q15_t)0x59a7, (q15_t)0xa4a5, (q15_t)0x59a3, (q15_t)0xa4a1, (q15_t)0x599e, (q15_t)0xa49d, + (q15_t)0x599a, (q15_t)0xa498, (q15_t)0x5995, (q15_t)0xa494, (q15_t)0x5991, (q15_t)0xa48f, (q15_t)0x598c, (q15_t)0xa48b, + (q15_t)0x5988, (q15_t)0xa487, (q15_t)0x5983, (q15_t)0xa482, (q15_t)0x597f, (q15_t)0xa47e, (q15_t)0x597a, (q15_t)0xa479, + (q15_t)0x5976, (q15_t)0xa475, (q15_t)0x5971, (q15_t)0xa471, (q15_t)0x596d, (q15_t)0xa46c, (q15_t)0x5968, (q15_t)0xa468, + (q15_t)0x5964, (q15_t)0xa463, (q15_t)0x595f, (q15_t)0xa45f, (q15_t)0x595b, (q15_t)0xa45b, (q15_t)0x5956, (q15_t)0xa456, + (q15_t)0x5952, (q15_t)0xa452, (q15_t)0x594d, (q15_t)0xa44e, (q15_t)0x5949, (q15_t)0xa449, (q15_t)0x5944, (q15_t)0xa445, + (q15_t)0x5940, (q15_t)0xa440, (q15_t)0x593b, (q15_t)0xa43c, (q15_t)0x5937, (q15_t)0xa438, (q15_t)0x5932, (q15_t)0xa433, + (q15_t)0x592e, (q15_t)0xa42f, (q15_t)0x5929, (q15_t)0xa42a, (q15_t)0x5925, (q15_t)0xa426, (q15_t)0x5920, (q15_t)0xa422, + (q15_t)0x591c, (q15_t)0xa41d, (q15_t)0x5917, (q15_t)0xa419, (q15_t)0x5913, (q15_t)0xa415, (q15_t)0x590e, (q15_t)0xa410, + (q15_t)0x590a, (q15_t)0xa40c, (q15_t)0x5905, (q15_t)0xa407, (q15_t)0x5901, (q15_t)0xa403, (q15_t)0x58fc, (q15_t)0xa3ff, + (q15_t)0x58f8, (q15_t)0xa3fa, (q15_t)0x58f3, (q15_t)0xa3f6, (q15_t)0x58ef, (q15_t)0xa3f2, (q15_t)0x58ea, (q15_t)0xa3ed, + (q15_t)0x58e6, (q15_t)0xa3e9, (q15_t)0x58e1, (q15_t)0xa3e5, (q15_t)0x58dd, (q15_t)0xa3e0, (q15_t)0x58d8, (q15_t)0xa3dc, + (q15_t)0x58d4, (q15_t)0xa3d7, (q15_t)0x58cf, (q15_t)0xa3d3, (q15_t)0x58cb, (q15_t)0xa3cf, (q15_t)0x58c6, (q15_t)0xa3ca, + (q15_t)0x58c1, (q15_t)0xa3c6, (q15_t)0x58bd, (q15_t)0xa3c2, (q15_t)0x58b8, (q15_t)0xa3bd, (q15_t)0x58b4, (q15_t)0xa3b9, + (q15_t)0x58af, (q15_t)0xa3b5, (q15_t)0x58ab, (q15_t)0xa3b0, (q15_t)0x58a6, (q15_t)0xa3ac, (q15_t)0x58a2, (q15_t)0xa3a8, + (q15_t)0x589d, (q15_t)0xa3a3, (q15_t)0x5899, (q15_t)0xa39f, (q15_t)0x5894, (q15_t)0xa39a, (q15_t)0x5890, (q15_t)0xa396, + (q15_t)0x588b, (q15_t)0xa392, (q15_t)0x5887, (q15_t)0xa38d, (q15_t)0x5882, (q15_t)0xa389, (q15_t)0x587d, (q15_t)0xa385, + (q15_t)0x5879, (q15_t)0xa380, (q15_t)0x5874, (q15_t)0xa37c, (q15_t)0x5870, (q15_t)0xa378, (q15_t)0x586b, (q15_t)0xa373, + (q15_t)0x5867, (q15_t)0xa36f, (q15_t)0x5862, (q15_t)0xa36b, (q15_t)0x585e, (q15_t)0xa366, (q15_t)0x5859, (q15_t)0xa362, + (q15_t)0x5855, (q15_t)0xa35e, (q15_t)0x5850, (q15_t)0xa359, (q15_t)0x584b, (q15_t)0xa355, (q15_t)0x5847, (q15_t)0xa351, + (q15_t)0x5842, (q15_t)0xa34c, (q15_t)0x583e, (q15_t)0xa348, (q15_t)0x5839, (q15_t)0xa344, (q15_t)0x5835, (q15_t)0xa33f, + (q15_t)0x5830, (q15_t)0xa33b, (q15_t)0x582c, (q15_t)0xa337, (q15_t)0x5827, (q15_t)0xa332, (q15_t)0x5822, (q15_t)0xa32e, + (q15_t)0x581e, (q15_t)0xa32a, (q15_t)0x5819, (q15_t)0xa325, (q15_t)0x5815, (q15_t)0xa321, (q15_t)0x5810, (q15_t)0xa31d, + (q15_t)0x580c, (q15_t)0xa318, (q15_t)0x5807, (q15_t)0xa314, (q15_t)0x5803, (q15_t)0xa310, (q15_t)0x57fe, (q15_t)0xa30b, + (q15_t)0x57f9, (q15_t)0xa307, (q15_t)0x57f5, (q15_t)0xa303, (q15_t)0x57f0, (q15_t)0xa2ff, (q15_t)0x57ec, (q15_t)0xa2fa, + (q15_t)0x57e7, (q15_t)0xa2f6, (q15_t)0x57e3, (q15_t)0xa2f2, (q15_t)0x57de, (q15_t)0xa2ed, (q15_t)0x57d9, (q15_t)0xa2e9, + (q15_t)0x57d5, (q15_t)0xa2e5, (q15_t)0x57d0, (q15_t)0xa2e0, (q15_t)0x57cc, (q15_t)0xa2dc, (q15_t)0x57c7, (q15_t)0xa2d8, + (q15_t)0x57c3, (q15_t)0xa2d3, (q15_t)0x57be, (q15_t)0xa2cf, (q15_t)0x57b9, (q15_t)0xa2cb, (q15_t)0x57b5, (q15_t)0xa2c6, + (q15_t)0x57b0, (q15_t)0xa2c2, (q15_t)0x57ac, (q15_t)0xa2be, (q15_t)0x57a7, (q15_t)0xa2ba, (q15_t)0x57a3, (q15_t)0xa2b5, + (q15_t)0x579e, (q15_t)0xa2b1, (q15_t)0x5799, (q15_t)0xa2ad, (q15_t)0x5795, (q15_t)0xa2a8, (q15_t)0x5790, (q15_t)0xa2a4, + (q15_t)0x578c, (q15_t)0xa2a0, (q15_t)0x5787, (q15_t)0xa29b, (q15_t)0x5783, (q15_t)0xa297, (q15_t)0x577e, (q15_t)0xa293, + (q15_t)0x5779, (q15_t)0xa28f, (q15_t)0x5775, (q15_t)0xa28a, (q15_t)0x5770, (q15_t)0xa286, (q15_t)0x576c, (q15_t)0xa282, + (q15_t)0x5767, (q15_t)0xa27d, (q15_t)0x5762, (q15_t)0xa279, (q15_t)0x575e, (q15_t)0xa275, (q15_t)0x5759, (q15_t)0xa271, + (q15_t)0x5755, (q15_t)0xa26c, (q15_t)0x5750, (q15_t)0xa268, (q15_t)0x574b, (q15_t)0xa264, (q15_t)0x5747, (q15_t)0xa25f, + (q15_t)0x5742, (q15_t)0xa25b, (q15_t)0x573e, (q15_t)0xa257, (q15_t)0x5739, (q15_t)0xa253, (q15_t)0x5734, (q15_t)0xa24e, + (q15_t)0x5730, (q15_t)0xa24a, (q15_t)0x572b, (q15_t)0xa246, (q15_t)0x5727, (q15_t)0xa241, (q15_t)0x5722, (q15_t)0xa23d, + (q15_t)0x571d, (q15_t)0xa239, (q15_t)0x5719, (q15_t)0xa235, (q15_t)0x5714, (q15_t)0xa230, (q15_t)0x5710, (q15_t)0xa22c, + (q15_t)0x570b, (q15_t)0xa228, (q15_t)0x5706, (q15_t)0xa224, (q15_t)0x5702, (q15_t)0xa21f, (q15_t)0x56fd, (q15_t)0xa21b, + (q15_t)0x56f9, (q15_t)0xa217, (q15_t)0x56f4, (q15_t)0xa212, (q15_t)0x56ef, (q15_t)0xa20e, (q15_t)0x56eb, (q15_t)0xa20a, + (q15_t)0x56e6, (q15_t)0xa206, (q15_t)0x56e2, (q15_t)0xa201, (q15_t)0x56dd, (q15_t)0xa1fd, (q15_t)0x56d8, (q15_t)0xa1f9, + (q15_t)0x56d4, (q15_t)0xa1f5, (q15_t)0x56cf, (q15_t)0xa1f0, (q15_t)0x56ca, (q15_t)0xa1ec, (q15_t)0x56c6, (q15_t)0xa1e8, + (q15_t)0x56c1, (q15_t)0xa1e4, (q15_t)0x56bd, (q15_t)0xa1df, (q15_t)0x56b8, (q15_t)0xa1db, (q15_t)0x56b3, (q15_t)0xa1d7, + (q15_t)0x56af, (q15_t)0xa1d3, (q15_t)0x56aa, (q15_t)0xa1ce, (q15_t)0x56a5, (q15_t)0xa1ca, (q15_t)0x56a1, (q15_t)0xa1c6, + (q15_t)0x569c, (q15_t)0xa1c1, (q15_t)0x5698, (q15_t)0xa1bd, (q15_t)0x5693, (q15_t)0xa1b9, (q15_t)0x568e, (q15_t)0xa1b5, + (q15_t)0x568a, (q15_t)0xa1b0, (q15_t)0x5685, (q15_t)0xa1ac, (q15_t)0x5680, (q15_t)0xa1a8, (q15_t)0x567c, (q15_t)0xa1a4, + (q15_t)0x5677, (q15_t)0xa1a0, (q15_t)0x5673, (q15_t)0xa19b, (q15_t)0x566e, (q15_t)0xa197, (q15_t)0x5669, (q15_t)0xa193, + (q15_t)0x5665, (q15_t)0xa18f, (q15_t)0x5660, (q15_t)0xa18a, (q15_t)0x565b, (q15_t)0xa186, (q15_t)0x5657, (q15_t)0xa182, + (q15_t)0x5652, (q15_t)0xa17e, (q15_t)0x564d, (q15_t)0xa179, (q15_t)0x5649, (q15_t)0xa175, (q15_t)0x5644, (q15_t)0xa171, + (q15_t)0x5640, (q15_t)0xa16d, (q15_t)0x563b, (q15_t)0xa168, (q15_t)0x5636, (q15_t)0xa164, (q15_t)0x5632, (q15_t)0xa160, + (q15_t)0x562d, (q15_t)0xa15c, (q15_t)0x5628, (q15_t)0xa157, (q15_t)0x5624, (q15_t)0xa153, (q15_t)0x561f, (q15_t)0xa14f, + (q15_t)0x561a, (q15_t)0xa14b, (q15_t)0x5616, (q15_t)0xa147, (q15_t)0x5611, (q15_t)0xa142, (q15_t)0x560c, (q15_t)0xa13e, + (q15_t)0x5608, (q15_t)0xa13a, (q15_t)0x5603, (q15_t)0xa136, (q15_t)0x55fe, (q15_t)0xa131, (q15_t)0x55fa, (q15_t)0xa12d, + (q15_t)0x55f5, (q15_t)0xa129, (q15_t)0x55f0, (q15_t)0xa125, (q15_t)0x55ec, (q15_t)0xa121, (q15_t)0x55e7, (q15_t)0xa11c, + (q15_t)0x55e3, (q15_t)0xa118, (q15_t)0x55de, (q15_t)0xa114, (q15_t)0x55d9, (q15_t)0xa110, (q15_t)0x55d5, (q15_t)0xa10b, + (q15_t)0x55d0, (q15_t)0xa107, (q15_t)0x55cb, (q15_t)0xa103, (q15_t)0x55c7, (q15_t)0xa0ff, (q15_t)0x55c2, (q15_t)0xa0fb, + (q15_t)0x55bd, (q15_t)0xa0f6, (q15_t)0x55b9, (q15_t)0xa0f2, (q15_t)0x55b4, (q15_t)0xa0ee, (q15_t)0x55af, (q15_t)0xa0ea, + (q15_t)0x55ab, (q15_t)0xa0e6, (q15_t)0x55a6, (q15_t)0xa0e1, (q15_t)0x55a1, (q15_t)0xa0dd, (q15_t)0x559d, (q15_t)0xa0d9, + (q15_t)0x5598, (q15_t)0xa0d5, (q15_t)0x5593, (q15_t)0xa0d1, (q15_t)0x558f, (q15_t)0xa0cc, (q15_t)0x558a, (q15_t)0xa0c8, + (q15_t)0x5585, (q15_t)0xa0c4, (q15_t)0x5581, (q15_t)0xa0c0, (q15_t)0x557c, (q15_t)0xa0bc, (q15_t)0x5577, (q15_t)0xa0b7, + (q15_t)0x5572, (q15_t)0xa0b3, (q15_t)0x556e, (q15_t)0xa0af, (q15_t)0x5569, (q15_t)0xa0ab, (q15_t)0x5564, (q15_t)0xa0a7, + (q15_t)0x5560, (q15_t)0xa0a2, (q15_t)0x555b, (q15_t)0xa09e, (q15_t)0x5556, (q15_t)0xa09a, (q15_t)0x5552, (q15_t)0xa096, + (q15_t)0x554d, (q15_t)0xa092, (q15_t)0x5548, (q15_t)0xa08e, (q15_t)0x5544, (q15_t)0xa089, (q15_t)0x553f, (q15_t)0xa085, + (q15_t)0x553a, (q15_t)0xa081, (q15_t)0x5536, (q15_t)0xa07d, (q15_t)0x5531, (q15_t)0xa079, (q15_t)0x552c, (q15_t)0xa074, + (q15_t)0x5528, (q15_t)0xa070, (q15_t)0x5523, (q15_t)0xa06c, (q15_t)0x551e, (q15_t)0xa068, (q15_t)0x5519, (q15_t)0xa064, + (q15_t)0x5515, (q15_t)0xa060, (q15_t)0x5510, (q15_t)0xa05b, (q15_t)0x550b, (q15_t)0xa057, (q15_t)0x5507, (q15_t)0xa053, + (q15_t)0x5502, (q15_t)0xa04f, (q15_t)0x54fd, (q15_t)0xa04b, (q15_t)0x54f9, (q15_t)0xa046, (q15_t)0x54f4, (q15_t)0xa042, + (q15_t)0x54ef, (q15_t)0xa03e, (q15_t)0x54ea, (q15_t)0xa03a, (q15_t)0x54e6, (q15_t)0xa036, (q15_t)0x54e1, (q15_t)0xa032, + (q15_t)0x54dc, (q15_t)0xa02d, (q15_t)0x54d8, (q15_t)0xa029, (q15_t)0x54d3, (q15_t)0xa025, (q15_t)0x54ce, (q15_t)0xa021, + (q15_t)0x54ca, (q15_t)0xa01d, (q15_t)0x54c5, (q15_t)0xa019, (q15_t)0x54c0, (q15_t)0xa014, (q15_t)0x54bb, (q15_t)0xa010, + (q15_t)0x54b7, (q15_t)0xa00c, (q15_t)0x54b2, (q15_t)0xa008, (q15_t)0x54ad, (q15_t)0xa004, (q15_t)0x54a9, (q15_t)0xa000, + (q15_t)0x54a4, (q15_t)0x9ffc, (q15_t)0x549f, (q15_t)0x9ff7, (q15_t)0x549a, (q15_t)0x9ff3, (q15_t)0x5496, (q15_t)0x9fef, + (q15_t)0x5491, (q15_t)0x9feb, (q15_t)0x548c, (q15_t)0x9fe7, (q15_t)0x5488, (q15_t)0x9fe3, (q15_t)0x5483, (q15_t)0x9fde, + (q15_t)0x547e, (q15_t)0x9fda, (q15_t)0x5479, (q15_t)0x9fd6, (q15_t)0x5475, (q15_t)0x9fd2, (q15_t)0x5470, (q15_t)0x9fce, + (q15_t)0x546b, (q15_t)0x9fca, (q15_t)0x5467, (q15_t)0x9fc6, (q15_t)0x5462, (q15_t)0x9fc1, (q15_t)0x545d, (q15_t)0x9fbd, + (q15_t)0x5458, (q15_t)0x9fb9, (q15_t)0x5454, (q15_t)0x9fb5, (q15_t)0x544f, (q15_t)0x9fb1, (q15_t)0x544a, (q15_t)0x9fad, + (q15_t)0x5445, (q15_t)0x9fa9, (q15_t)0x5441, (q15_t)0x9fa4, (q15_t)0x543c, (q15_t)0x9fa0, (q15_t)0x5437, (q15_t)0x9f9c, + (q15_t)0x5433, (q15_t)0x9f98, (q15_t)0x542e, (q15_t)0x9f94, (q15_t)0x5429, (q15_t)0x9f90, (q15_t)0x5424, (q15_t)0x9f8c, + (q15_t)0x5420, (q15_t)0x9f88, (q15_t)0x541b, (q15_t)0x9f83, (q15_t)0x5416, (q15_t)0x9f7f, (q15_t)0x5411, (q15_t)0x9f7b, + (q15_t)0x540d, (q15_t)0x9f77, (q15_t)0x5408, (q15_t)0x9f73, (q15_t)0x5403, (q15_t)0x9f6f, (q15_t)0x53fe, (q15_t)0x9f6b, + (q15_t)0x53fa, (q15_t)0x9f67, (q15_t)0x53f5, (q15_t)0x9f62, (q15_t)0x53f0, (q15_t)0x9f5e, (q15_t)0x53eb, (q15_t)0x9f5a, + (q15_t)0x53e7, (q15_t)0x9f56, (q15_t)0x53e2, (q15_t)0x9f52, (q15_t)0x53dd, (q15_t)0x9f4e, (q15_t)0x53d8, (q15_t)0x9f4a, + (q15_t)0x53d4, (q15_t)0x9f46, (q15_t)0x53cf, (q15_t)0x9f41, (q15_t)0x53ca, (q15_t)0x9f3d, (q15_t)0x53c5, (q15_t)0x9f39, + (q15_t)0x53c1, (q15_t)0x9f35, (q15_t)0x53bc, (q15_t)0x9f31, (q15_t)0x53b7, (q15_t)0x9f2d, (q15_t)0x53b2, (q15_t)0x9f29, + (q15_t)0x53ae, (q15_t)0x9f25, (q15_t)0x53a9, (q15_t)0x9f21, (q15_t)0x53a4, (q15_t)0x9f1c, (q15_t)0x539f, (q15_t)0x9f18, + (q15_t)0x539b, (q15_t)0x9f14, (q15_t)0x5396, (q15_t)0x9f10, (q15_t)0x5391, (q15_t)0x9f0c, (q15_t)0x538c, (q15_t)0x9f08, + (q15_t)0x5388, (q15_t)0x9f04, (q15_t)0x5383, (q15_t)0x9f00, (q15_t)0x537e, (q15_t)0x9efc, (q15_t)0x5379, (q15_t)0x9ef8, + (q15_t)0x5375, (q15_t)0x9ef3, (q15_t)0x5370, (q15_t)0x9eef, (q15_t)0x536b, (q15_t)0x9eeb, (q15_t)0x5366, (q15_t)0x9ee7, + (q15_t)0x5362, (q15_t)0x9ee3, (q15_t)0x535d, (q15_t)0x9edf, (q15_t)0x5358, (q15_t)0x9edb, (q15_t)0x5353, (q15_t)0x9ed7, + (q15_t)0x534e, (q15_t)0x9ed3, (q15_t)0x534a, (q15_t)0x9ecf, (q15_t)0x5345, (q15_t)0x9ecb, (q15_t)0x5340, (q15_t)0x9ec6, + (q15_t)0x533b, (q15_t)0x9ec2, (q15_t)0x5337, (q15_t)0x9ebe, (q15_t)0x5332, (q15_t)0x9eba, (q15_t)0x532d, (q15_t)0x9eb6, + (q15_t)0x5328, (q15_t)0x9eb2, (q15_t)0x5323, (q15_t)0x9eae, (q15_t)0x531f, (q15_t)0x9eaa, (q15_t)0x531a, (q15_t)0x9ea6, + (q15_t)0x5315, (q15_t)0x9ea2, (q15_t)0x5310, (q15_t)0x9e9e, (q15_t)0x530c, (q15_t)0x9e9a, (q15_t)0x5307, (q15_t)0x9e95, + (q15_t)0x5302, (q15_t)0x9e91, (q15_t)0x52fd, (q15_t)0x9e8d, (q15_t)0x52f8, (q15_t)0x9e89, (q15_t)0x52f4, (q15_t)0x9e85, + (q15_t)0x52ef, (q15_t)0x9e81, (q15_t)0x52ea, (q15_t)0x9e7d, (q15_t)0x52e5, (q15_t)0x9e79, (q15_t)0x52e1, (q15_t)0x9e75, + (q15_t)0x52dc, (q15_t)0x9e71, (q15_t)0x52d7, (q15_t)0x9e6d, (q15_t)0x52d2, (q15_t)0x9e69, (q15_t)0x52cd, (q15_t)0x9e65, + (q15_t)0x52c9, (q15_t)0x9e61, (q15_t)0x52c4, (q15_t)0x9e5d, (q15_t)0x52bf, (q15_t)0x9e58, (q15_t)0x52ba, (q15_t)0x9e54, + (q15_t)0x52b5, (q15_t)0x9e50, (q15_t)0x52b1, (q15_t)0x9e4c, (q15_t)0x52ac, (q15_t)0x9e48, (q15_t)0x52a7, (q15_t)0x9e44, + (q15_t)0x52a2, (q15_t)0x9e40, (q15_t)0x529d, (q15_t)0x9e3c, (q15_t)0x5299, (q15_t)0x9e38, (q15_t)0x5294, (q15_t)0x9e34, + (q15_t)0x528f, (q15_t)0x9e30, (q15_t)0x528a, (q15_t)0x9e2c, (q15_t)0x5285, (q15_t)0x9e28, (q15_t)0x5281, (q15_t)0x9e24, + (q15_t)0x527c, (q15_t)0x9e20, (q15_t)0x5277, (q15_t)0x9e1c, (q15_t)0x5272, (q15_t)0x9e18, (q15_t)0x526d, (q15_t)0x9e14, + (q15_t)0x5269, (q15_t)0x9e0f, (q15_t)0x5264, (q15_t)0x9e0b, (q15_t)0x525f, (q15_t)0x9e07, (q15_t)0x525a, (q15_t)0x9e03, + (q15_t)0x5255, (q15_t)0x9dff, (q15_t)0x5251, (q15_t)0x9dfb, (q15_t)0x524c, (q15_t)0x9df7, (q15_t)0x5247, (q15_t)0x9df3, + (q15_t)0x5242, (q15_t)0x9def, (q15_t)0x523d, (q15_t)0x9deb, (q15_t)0x5238, (q15_t)0x9de7, (q15_t)0x5234, (q15_t)0x9de3, + (q15_t)0x522f, (q15_t)0x9ddf, (q15_t)0x522a, (q15_t)0x9ddb, (q15_t)0x5225, (q15_t)0x9dd7, (q15_t)0x5220, (q15_t)0x9dd3, + (q15_t)0x521c, (q15_t)0x9dcf, (q15_t)0x5217, (q15_t)0x9dcb, (q15_t)0x5212, (q15_t)0x9dc7, (q15_t)0x520d, (q15_t)0x9dc3, + (q15_t)0x5208, (q15_t)0x9dbf, (q15_t)0x5203, (q15_t)0x9dbb, (q15_t)0x51ff, (q15_t)0x9db7, (q15_t)0x51fa, (q15_t)0x9db3, + (q15_t)0x51f5, (q15_t)0x9daf, (q15_t)0x51f0, (q15_t)0x9dab, (q15_t)0x51eb, (q15_t)0x9da7, (q15_t)0x51e6, (q15_t)0x9da3, + (q15_t)0x51e2, (q15_t)0x9d9f, (q15_t)0x51dd, (q15_t)0x9d9b, (q15_t)0x51d8, (q15_t)0x9d97, (q15_t)0x51d3, (q15_t)0x9d93, + (q15_t)0x51ce, (q15_t)0x9d8f, (q15_t)0x51c9, (q15_t)0x9d8b, (q15_t)0x51c5, (q15_t)0x9d86, (q15_t)0x51c0, (q15_t)0x9d82, + (q15_t)0x51bb, (q15_t)0x9d7e, (q15_t)0x51b6, (q15_t)0x9d7a, (q15_t)0x51b1, (q15_t)0x9d76, (q15_t)0x51ac, (q15_t)0x9d72, + (q15_t)0x51a8, (q15_t)0x9d6e, (q15_t)0x51a3, (q15_t)0x9d6a, (q15_t)0x519e, (q15_t)0x9d66, (q15_t)0x5199, (q15_t)0x9d62, + (q15_t)0x5194, (q15_t)0x9d5e, (q15_t)0x518f, (q15_t)0x9d5a, (q15_t)0x518b, (q15_t)0x9d56, (q15_t)0x5186, (q15_t)0x9d52, + (q15_t)0x5181, (q15_t)0x9d4e, (q15_t)0x517c, (q15_t)0x9d4a, (q15_t)0x5177, (q15_t)0x9d46, (q15_t)0x5172, (q15_t)0x9d42, + (q15_t)0x516e, (q15_t)0x9d3e, (q15_t)0x5169, (q15_t)0x9d3a, (q15_t)0x5164, (q15_t)0x9d36, (q15_t)0x515f, (q15_t)0x9d32, + (q15_t)0x515a, (q15_t)0x9d2e, (q15_t)0x5155, (q15_t)0x9d2a, (q15_t)0x5150, (q15_t)0x9d26, (q15_t)0x514c, (q15_t)0x9d22, + (q15_t)0x5147, (q15_t)0x9d1e, (q15_t)0x5142, (q15_t)0x9d1a, (q15_t)0x513d, (q15_t)0x9d16, (q15_t)0x5138, (q15_t)0x9d12, + (q15_t)0x5133, (q15_t)0x9d0e, (q15_t)0x512e, (q15_t)0x9d0b, (q15_t)0x512a, (q15_t)0x9d07, (q15_t)0x5125, (q15_t)0x9d03, + (q15_t)0x5120, (q15_t)0x9cff, (q15_t)0x511b, (q15_t)0x9cfb, (q15_t)0x5116, (q15_t)0x9cf7, (q15_t)0x5111, (q15_t)0x9cf3, + (q15_t)0x510c, (q15_t)0x9cef, (q15_t)0x5108, (q15_t)0x9ceb, (q15_t)0x5103, (q15_t)0x9ce7, (q15_t)0x50fe, (q15_t)0x9ce3, + (q15_t)0x50f9, (q15_t)0x9cdf, (q15_t)0x50f4, (q15_t)0x9cdb, (q15_t)0x50ef, (q15_t)0x9cd7, (q15_t)0x50ea, (q15_t)0x9cd3, + (q15_t)0x50e5, (q15_t)0x9ccf, (q15_t)0x50e1, (q15_t)0x9ccb, (q15_t)0x50dc, (q15_t)0x9cc7, (q15_t)0x50d7, (q15_t)0x9cc3, + (q15_t)0x50d2, (q15_t)0x9cbf, (q15_t)0x50cd, (q15_t)0x9cbb, (q15_t)0x50c8, (q15_t)0x9cb7, (q15_t)0x50c3, (q15_t)0x9cb3, + (q15_t)0x50bf, (q15_t)0x9caf, (q15_t)0x50ba, (q15_t)0x9cab, (q15_t)0x50b5, (q15_t)0x9ca7, (q15_t)0x50b0, (q15_t)0x9ca3, + (q15_t)0x50ab, (q15_t)0x9c9f, (q15_t)0x50a6, (q15_t)0x9c9b, (q15_t)0x50a1, (q15_t)0x9c97, (q15_t)0x509c, (q15_t)0x9c93, + (q15_t)0x5097, (q15_t)0x9c8f, (q15_t)0x5093, (q15_t)0x9c8b, (q15_t)0x508e, (q15_t)0x9c88, (q15_t)0x5089, (q15_t)0x9c84, + (q15_t)0x5084, (q15_t)0x9c80, (q15_t)0x507f, (q15_t)0x9c7c, (q15_t)0x507a, (q15_t)0x9c78, (q15_t)0x5075, (q15_t)0x9c74, + (q15_t)0x5070, (q15_t)0x9c70, (q15_t)0x506c, (q15_t)0x9c6c, (q15_t)0x5067, (q15_t)0x9c68, (q15_t)0x5062, (q15_t)0x9c64, + (q15_t)0x505d, (q15_t)0x9c60, (q15_t)0x5058, (q15_t)0x9c5c, (q15_t)0x5053, (q15_t)0x9c58, (q15_t)0x504e, (q15_t)0x9c54, + (q15_t)0x5049, (q15_t)0x9c50, (q15_t)0x5044, (q15_t)0x9c4c, (q15_t)0x503f, (q15_t)0x9c48, (q15_t)0x503b, (q15_t)0x9c44, + (q15_t)0x5036, (q15_t)0x9c40, (q15_t)0x5031, (q15_t)0x9c3d, (q15_t)0x502c, (q15_t)0x9c39, (q15_t)0x5027, (q15_t)0x9c35, + (q15_t)0x5022, (q15_t)0x9c31, (q15_t)0x501d, (q15_t)0x9c2d, (q15_t)0x5018, (q15_t)0x9c29, (q15_t)0x5013, (q15_t)0x9c25, + (q15_t)0x500f, (q15_t)0x9c21, (q15_t)0x500a, (q15_t)0x9c1d, (q15_t)0x5005, (q15_t)0x9c19, (q15_t)0x5000, (q15_t)0x9c15, + (q15_t)0x4ffb, (q15_t)0x9c11, (q15_t)0x4ff6, (q15_t)0x9c0d, (q15_t)0x4ff1, (q15_t)0x9c09, (q15_t)0x4fec, (q15_t)0x9c06, + (q15_t)0x4fe7, (q15_t)0x9c02, (q15_t)0x4fe2, (q15_t)0x9bfe, (q15_t)0x4fdd, (q15_t)0x9bfa, (q15_t)0x4fd9, (q15_t)0x9bf6, + (q15_t)0x4fd4, (q15_t)0x9bf2, (q15_t)0x4fcf, (q15_t)0x9bee, (q15_t)0x4fca, (q15_t)0x9bea, (q15_t)0x4fc5, (q15_t)0x9be6, + (q15_t)0x4fc0, (q15_t)0x9be2, (q15_t)0x4fbb, (q15_t)0x9bde, (q15_t)0x4fb6, (q15_t)0x9bda, (q15_t)0x4fb1, (q15_t)0x9bd7, + (q15_t)0x4fac, (q15_t)0x9bd3, (q15_t)0x4fa7, (q15_t)0x9bcf, (q15_t)0x4fa2, (q15_t)0x9bcb, (q15_t)0x4f9e, (q15_t)0x9bc7, + (q15_t)0x4f99, (q15_t)0x9bc3, (q15_t)0x4f94, (q15_t)0x9bbf, (q15_t)0x4f8f, (q15_t)0x9bbb, (q15_t)0x4f8a, (q15_t)0x9bb7, + (q15_t)0x4f85, (q15_t)0x9bb3, (q15_t)0x4f80, (q15_t)0x9baf, (q15_t)0x4f7b, (q15_t)0x9bac, (q15_t)0x4f76, (q15_t)0x9ba8, + (q15_t)0x4f71, (q15_t)0x9ba4, (q15_t)0x4f6c, (q15_t)0x9ba0, (q15_t)0x4f67, (q15_t)0x9b9c, (q15_t)0x4f62, (q15_t)0x9b98, + (q15_t)0x4f5e, (q15_t)0x9b94, (q15_t)0x4f59, (q15_t)0x9b90, (q15_t)0x4f54, (q15_t)0x9b8c, (q15_t)0x4f4f, (q15_t)0x9b88, + (q15_t)0x4f4a, (q15_t)0x9b85, (q15_t)0x4f45, (q15_t)0x9b81, (q15_t)0x4f40, (q15_t)0x9b7d, (q15_t)0x4f3b, (q15_t)0x9b79, + (q15_t)0x4f36, (q15_t)0x9b75, (q15_t)0x4f31, (q15_t)0x9b71, (q15_t)0x4f2c, (q15_t)0x9b6d, (q15_t)0x4f27, (q15_t)0x9b69, + (q15_t)0x4f22, (q15_t)0x9b65, (q15_t)0x4f1d, (q15_t)0x9b62, (q15_t)0x4f18, (q15_t)0x9b5e, (q15_t)0x4f14, (q15_t)0x9b5a, + (q15_t)0x4f0f, (q15_t)0x9b56, (q15_t)0x4f0a, (q15_t)0x9b52, (q15_t)0x4f05, (q15_t)0x9b4e, (q15_t)0x4f00, (q15_t)0x9b4a, + (q15_t)0x4efb, (q15_t)0x9b46, (q15_t)0x4ef6, (q15_t)0x9b43, (q15_t)0x4ef1, (q15_t)0x9b3f, (q15_t)0x4eec, (q15_t)0x9b3b, + (q15_t)0x4ee7, (q15_t)0x9b37, (q15_t)0x4ee2, (q15_t)0x9b33, (q15_t)0x4edd, (q15_t)0x9b2f, (q15_t)0x4ed8, (q15_t)0x9b2b, + (q15_t)0x4ed3, (q15_t)0x9b27, (q15_t)0x4ece, (q15_t)0x9b24, (q15_t)0x4ec9, (q15_t)0x9b20, (q15_t)0x4ec4, (q15_t)0x9b1c, + (q15_t)0x4ebf, (q15_t)0x9b18, (q15_t)0x4eba, (q15_t)0x9b14, (q15_t)0x4eb6, (q15_t)0x9b10, (q15_t)0x4eb1, (q15_t)0x9b0c, + (q15_t)0x4eac, (q15_t)0x9b09, (q15_t)0x4ea7, (q15_t)0x9b05, (q15_t)0x4ea2, (q15_t)0x9b01, (q15_t)0x4e9d, (q15_t)0x9afd, + (q15_t)0x4e98, (q15_t)0x9af9, (q15_t)0x4e93, (q15_t)0x9af5, (q15_t)0x4e8e, (q15_t)0x9af1, (q15_t)0x4e89, (q15_t)0x9aed, + (q15_t)0x4e84, (q15_t)0x9aea, (q15_t)0x4e7f, (q15_t)0x9ae6, (q15_t)0x4e7a, (q15_t)0x9ae2, (q15_t)0x4e75, (q15_t)0x9ade, + (q15_t)0x4e70, (q15_t)0x9ada, (q15_t)0x4e6b, (q15_t)0x9ad6, (q15_t)0x4e66, (q15_t)0x9ad3, (q15_t)0x4e61, (q15_t)0x9acf, + (q15_t)0x4e5c, (q15_t)0x9acb, (q15_t)0x4e57, (q15_t)0x9ac7, (q15_t)0x4e52, (q15_t)0x9ac3, (q15_t)0x4e4d, (q15_t)0x9abf, + (q15_t)0x4e48, (q15_t)0x9abb, (q15_t)0x4e43, (q15_t)0x9ab8, (q15_t)0x4e3e, (q15_t)0x9ab4, (q15_t)0x4e39, (q15_t)0x9ab0, + (q15_t)0x4e34, (q15_t)0x9aac, (q15_t)0x4e2f, (q15_t)0x9aa8, (q15_t)0x4e2a, (q15_t)0x9aa4, (q15_t)0x4e26, (q15_t)0x9aa1, + (q15_t)0x4e21, (q15_t)0x9a9d, (q15_t)0x4e1c, (q15_t)0x9a99, (q15_t)0x4e17, (q15_t)0x9a95, (q15_t)0x4e12, (q15_t)0x9a91, + (q15_t)0x4e0d, (q15_t)0x9a8d, (q15_t)0x4e08, (q15_t)0x9a8a, (q15_t)0x4e03, (q15_t)0x9a86, (q15_t)0x4dfe, (q15_t)0x9a82, + (q15_t)0x4df9, (q15_t)0x9a7e, (q15_t)0x4df4, (q15_t)0x9a7a, (q15_t)0x4def, (q15_t)0x9a76, (q15_t)0x4dea, (q15_t)0x9a73, + (q15_t)0x4de5, (q15_t)0x9a6f, (q15_t)0x4de0, (q15_t)0x9a6b, (q15_t)0x4ddb, (q15_t)0x9a67, (q15_t)0x4dd6, (q15_t)0x9a63, + (q15_t)0x4dd1, (q15_t)0x9a60, (q15_t)0x4dcc, (q15_t)0x9a5c, (q15_t)0x4dc7, (q15_t)0x9a58, (q15_t)0x4dc2, (q15_t)0x9a54, + (q15_t)0x4dbd, (q15_t)0x9a50, (q15_t)0x4db8, (q15_t)0x9a4c, (q15_t)0x4db3, (q15_t)0x9a49, (q15_t)0x4dae, (q15_t)0x9a45, + (q15_t)0x4da9, (q15_t)0x9a41, (q15_t)0x4da4, (q15_t)0x9a3d, (q15_t)0x4d9f, (q15_t)0x9a39, (q15_t)0x4d9a, (q15_t)0x9a36, + (q15_t)0x4d95, (q15_t)0x9a32, (q15_t)0x4d90, (q15_t)0x9a2e, (q15_t)0x4d8b, (q15_t)0x9a2a, (q15_t)0x4d86, (q15_t)0x9a26, + (q15_t)0x4d81, (q15_t)0x9a23, (q15_t)0x4d7c, (q15_t)0x9a1f, (q15_t)0x4d77, (q15_t)0x9a1b, (q15_t)0x4d72, (q15_t)0x9a17, + (q15_t)0x4d6d, (q15_t)0x9a13, (q15_t)0x4d68, (q15_t)0x9a10, (q15_t)0x4d63, (q15_t)0x9a0c, (q15_t)0x4d5e, (q15_t)0x9a08, + (q15_t)0x4d59, (q15_t)0x9a04, (q15_t)0x4d54, (q15_t)0x9a00, (q15_t)0x4d4f, (q15_t)0x99fd, (q15_t)0x4d4a, (q15_t)0x99f9, + (q15_t)0x4d45, (q15_t)0x99f5, (q15_t)0x4d40, (q15_t)0x99f1, (q15_t)0x4d3b, (q15_t)0x99ed, (q15_t)0x4d36, (q15_t)0x99ea, + (q15_t)0x4d31, (q15_t)0x99e6, (q15_t)0x4d2c, (q15_t)0x99e2, (q15_t)0x4d27, (q15_t)0x99de, (q15_t)0x4d22, (q15_t)0x99da, + (q15_t)0x4d1d, (q15_t)0x99d7, (q15_t)0x4d18, (q15_t)0x99d3, (q15_t)0x4d13, (q15_t)0x99cf, (q15_t)0x4d0e, (q15_t)0x99cb, + (q15_t)0x4d09, (q15_t)0x99c7, (q15_t)0x4d04, (q15_t)0x99c4, (q15_t)0x4cff, (q15_t)0x99c0, (q15_t)0x4cfa, (q15_t)0x99bc, + (q15_t)0x4cf5, (q15_t)0x99b8, (q15_t)0x4cf0, (q15_t)0x99b5, (q15_t)0x4ceb, (q15_t)0x99b1, (q15_t)0x4ce6, (q15_t)0x99ad, + (q15_t)0x4ce1, (q15_t)0x99a9, (q15_t)0x4cdb, (q15_t)0x99a5, (q15_t)0x4cd6, (q15_t)0x99a2, (q15_t)0x4cd1, (q15_t)0x999e, + (q15_t)0x4ccc, (q15_t)0x999a, (q15_t)0x4cc7, (q15_t)0x9996, (q15_t)0x4cc2, (q15_t)0x9993, (q15_t)0x4cbd, (q15_t)0x998f, + (q15_t)0x4cb8, (q15_t)0x998b, (q15_t)0x4cb3, (q15_t)0x9987, (q15_t)0x4cae, (q15_t)0x9984, (q15_t)0x4ca9, (q15_t)0x9980, + (q15_t)0x4ca4, (q15_t)0x997c, (q15_t)0x4c9f, (q15_t)0x9978, (q15_t)0x4c9a, (q15_t)0x9975, (q15_t)0x4c95, (q15_t)0x9971, + (q15_t)0x4c90, (q15_t)0x996d, (q15_t)0x4c8b, (q15_t)0x9969, (q15_t)0x4c86, (q15_t)0x9965, (q15_t)0x4c81, (q15_t)0x9962, + (q15_t)0x4c7c, (q15_t)0x995e, (q15_t)0x4c77, (q15_t)0x995a, (q15_t)0x4c72, (q15_t)0x9956, (q15_t)0x4c6d, (q15_t)0x9953, + (q15_t)0x4c68, (q15_t)0x994f, (q15_t)0x4c63, (q15_t)0x994b, (q15_t)0x4c5e, (q15_t)0x9947, (q15_t)0x4c59, (q15_t)0x9944, + (q15_t)0x4c54, (q15_t)0x9940, (q15_t)0x4c4f, (q15_t)0x993c, (q15_t)0x4c49, (q15_t)0x9938, (q15_t)0x4c44, (q15_t)0x9935, + (q15_t)0x4c3f, (q15_t)0x9931, (q15_t)0x4c3a, (q15_t)0x992d, (q15_t)0x4c35, (q15_t)0x992a, (q15_t)0x4c30, (q15_t)0x9926, + (q15_t)0x4c2b, (q15_t)0x9922, (q15_t)0x4c26, (q15_t)0x991e, (q15_t)0x4c21, (q15_t)0x991b, (q15_t)0x4c1c, (q15_t)0x9917, + (q15_t)0x4c17, (q15_t)0x9913, (q15_t)0x4c12, (q15_t)0x990f, (q15_t)0x4c0d, (q15_t)0x990c, (q15_t)0x4c08, (q15_t)0x9908, + (q15_t)0x4c03, (q15_t)0x9904, (q15_t)0x4bfe, (q15_t)0x9900, (q15_t)0x4bf9, (q15_t)0x98fd, (q15_t)0x4bf4, (q15_t)0x98f9, + (q15_t)0x4bef, (q15_t)0x98f5, (q15_t)0x4be9, (q15_t)0x98f2, (q15_t)0x4be4, (q15_t)0x98ee, (q15_t)0x4bdf, (q15_t)0x98ea, + (q15_t)0x4bda, (q15_t)0x98e6, (q15_t)0x4bd5, (q15_t)0x98e3, (q15_t)0x4bd0, (q15_t)0x98df, (q15_t)0x4bcb, (q15_t)0x98db, + (q15_t)0x4bc6, (q15_t)0x98d7, (q15_t)0x4bc1, (q15_t)0x98d4, (q15_t)0x4bbc, (q15_t)0x98d0, (q15_t)0x4bb7, (q15_t)0x98cc, + (q15_t)0x4bb2, (q15_t)0x98c9, (q15_t)0x4bad, (q15_t)0x98c5, (q15_t)0x4ba8, (q15_t)0x98c1, (q15_t)0x4ba3, (q15_t)0x98bd, + (q15_t)0x4b9e, (q15_t)0x98ba, (q15_t)0x4b98, (q15_t)0x98b6, (q15_t)0x4b93, (q15_t)0x98b2, (q15_t)0x4b8e, (q15_t)0x98af, + (q15_t)0x4b89, (q15_t)0x98ab, (q15_t)0x4b84, (q15_t)0x98a7, (q15_t)0x4b7f, (q15_t)0x98a3, (q15_t)0x4b7a, (q15_t)0x98a0, + (q15_t)0x4b75, (q15_t)0x989c, (q15_t)0x4b70, (q15_t)0x9898, (q15_t)0x4b6b, (q15_t)0x9895, (q15_t)0x4b66, (q15_t)0x9891, + (q15_t)0x4b61, (q15_t)0x988d, (q15_t)0x4b5c, (q15_t)0x988a, (q15_t)0x4b56, (q15_t)0x9886, (q15_t)0x4b51, (q15_t)0x9882, + (q15_t)0x4b4c, (q15_t)0x987e, (q15_t)0x4b47, (q15_t)0x987b, (q15_t)0x4b42, (q15_t)0x9877, (q15_t)0x4b3d, (q15_t)0x9873, + (q15_t)0x4b38, (q15_t)0x9870, (q15_t)0x4b33, (q15_t)0x986c, (q15_t)0x4b2e, (q15_t)0x9868, (q15_t)0x4b29, (q15_t)0x9865, + (q15_t)0x4b24, (q15_t)0x9861, (q15_t)0x4b1f, (q15_t)0x985d, (q15_t)0x4b19, (q15_t)0x985a, (q15_t)0x4b14, (q15_t)0x9856, + (q15_t)0x4b0f, (q15_t)0x9852, (q15_t)0x4b0a, (q15_t)0x984e, (q15_t)0x4b05, (q15_t)0x984b, (q15_t)0x4b00, (q15_t)0x9847, + (q15_t)0x4afb, (q15_t)0x9843, (q15_t)0x4af6, (q15_t)0x9840, (q15_t)0x4af1, (q15_t)0x983c, (q15_t)0x4aec, (q15_t)0x9838, + (q15_t)0x4ae7, (q15_t)0x9835, (q15_t)0x4ae1, (q15_t)0x9831, (q15_t)0x4adc, (q15_t)0x982d, (q15_t)0x4ad7, (q15_t)0x982a, + (q15_t)0x4ad2, (q15_t)0x9826, (q15_t)0x4acd, (q15_t)0x9822, (q15_t)0x4ac8, (q15_t)0x981f, (q15_t)0x4ac3, (q15_t)0x981b, + (q15_t)0x4abe, (q15_t)0x9817, (q15_t)0x4ab9, (q15_t)0x9814, (q15_t)0x4ab4, (q15_t)0x9810, (q15_t)0x4aae, (q15_t)0x980c, + (q15_t)0x4aa9, (q15_t)0x9809, (q15_t)0x4aa4, (q15_t)0x9805, (q15_t)0x4a9f, (q15_t)0x9801, (q15_t)0x4a9a, (q15_t)0x97fe, + (q15_t)0x4a95, (q15_t)0x97fa, (q15_t)0x4a90, (q15_t)0x97f6, (q15_t)0x4a8b, (q15_t)0x97f3, (q15_t)0x4a86, (q15_t)0x97ef, + (q15_t)0x4a81, (q15_t)0x97eb, (q15_t)0x4a7b, (q15_t)0x97e8, (q15_t)0x4a76, (q15_t)0x97e4, (q15_t)0x4a71, (q15_t)0x97e0, + (q15_t)0x4a6c, (q15_t)0x97dd, (q15_t)0x4a67, (q15_t)0x97d9, (q15_t)0x4a62, (q15_t)0x97d5, (q15_t)0x4a5d, (q15_t)0x97d2, + (q15_t)0x4a58, (q15_t)0x97ce, (q15_t)0x4a52, (q15_t)0x97cb, (q15_t)0x4a4d, (q15_t)0x97c7, (q15_t)0x4a48, (q15_t)0x97c3, + (q15_t)0x4a43, (q15_t)0x97c0, (q15_t)0x4a3e, (q15_t)0x97bc, (q15_t)0x4a39, (q15_t)0x97b8, (q15_t)0x4a34, (q15_t)0x97b5, + (q15_t)0x4a2f, (q15_t)0x97b1, (q15_t)0x4a2a, (q15_t)0x97ad, (q15_t)0x4a24, (q15_t)0x97aa, (q15_t)0x4a1f, (q15_t)0x97a6, + (q15_t)0x4a1a, (q15_t)0x97a2, (q15_t)0x4a15, (q15_t)0x979f, (q15_t)0x4a10, (q15_t)0x979b, (q15_t)0x4a0b, (q15_t)0x9798, + (q15_t)0x4a06, (q15_t)0x9794, (q15_t)0x4a01, (q15_t)0x9790, (q15_t)0x49fb, (q15_t)0x978d, (q15_t)0x49f6, (q15_t)0x9789, + (q15_t)0x49f1, (q15_t)0x9785, (q15_t)0x49ec, (q15_t)0x9782, (q15_t)0x49e7, (q15_t)0x977e, (q15_t)0x49e2, (q15_t)0x977a, + (q15_t)0x49dd, (q15_t)0x9777, (q15_t)0x49d8, (q15_t)0x9773, (q15_t)0x49d2, (q15_t)0x9770, (q15_t)0x49cd, (q15_t)0x976c, + (q15_t)0x49c8, (q15_t)0x9768, (q15_t)0x49c3, (q15_t)0x9765, (q15_t)0x49be, (q15_t)0x9761, (q15_t)0x49b9, (q15_t)0x975d, + (q15_t)0x49b4, (q15_t)0x975a, (q15_t)0x49ae, (q15_t)0x9756, (q15_t)0x49a9, (q15_t)0x9753, (q15_t)0x49a4, (q15_t)0x974f, + (q15_t)0x499f, (q15_t)0x974b, (q15_t)0x499a, (q15_t)0x9748, (q15_t)0x4995, (q15_t)0x9744, (q15_t)0x4990, (q15_t)0x9741, + (q15_t)0x498a, (q15_t)0x973d, (q15_t)0x4985, (q15_t)0x9739, (q15_t)0x4980, (q15_t)0x9736, (q15_t)0x497b, (q15_t)0x9732, + (q15_t)0x4976, (q15_t)0x972f, (q15_t)0x4971, (q15_t)0x972b, (q15_t)0x496c, (q15_t)0x9727, (q15_t)0x4966, (q15_t)0x9724, + (q15_t)0x4961, (q15_t)0x9720, (q15_t)0x495c, (q15_t)0x971d, (q15_t)0x4957, (q15_t)0x9719, (q15_t)0x4952, (q15_t)0x9715, + (q15_t)0x494d, (q15_t)0x9712, (q15_t)0x4948, (q15_t)0x970e, (q15_t)0x4942, (q15_t)0x970b, (q15_t)0x493d, (q15_t)0x9707, + (q15_t)0x4938, (q15_t)0x9703, (q15_t)0x4933, (q15_t)0x9700, (q15_t)0x492e, (q15_t)0x96fc, (q15_t)0x4929, (q15_t)0x96f9, + (q15_t)0x4923, (q15_t)0x96f5, (q15_t)0x491e, (q15_t)0x96f1, (q15_t)0x4919, (q15_t)0x96ee, (q15_t)0x4914, (q15_t)0x96ea, + (q15_t)0x490f, (q15_t)0x96e7, (q15_t)0x490a, (q15_t)0x96e3, (q15_t)0x4905, (q15_t)0x96df, (q15_t)0x48ff, (q15_t)0x96dc, + (q15_t)0x48fa, (q15_t)0x96d8, (q15_t)0x48f5, (q15_t)0x96d5, (q15_t)0x48f0, (q15_t)0x96d1, (q15_t)0x48eb, (q15_t)0x96ce, + (q15_t)0x48e6, (q15_t)0x96ca, (q15_t)0x48e0, (q15_t)0x96c6, (q15_t)0x48db, (q15_t)0x96c3, (q15_t)0x48d6, (q15_t)0x96bf, + (q15_t)0x48d1, (q15_t)0x96bc, (q15_t)0x48cc, (q15_t)0x96b8, (q15_t)0x48c7, (q15_t)0x96b5, (q15_t)0x48c1, (q15_t)0x96b1, + (q15_t)0x48bc, (q15_t)0x96ad, (q15_t)0x48b7, (q15_t)0x96aa, (q15_t)0x48b2, (q15_t)0x96a6, (q15_t)0x48ad, (q15_t)0x96a3, + (q15_t)0x48a8, (q15_t)0x969f, (q15_t)0x48a2, (q15_t)0x969c, (q15_t)0x489d, (q15_t)0x9698, (q15_t)0x4898, (q15_t)0x9694, + (q15_t)0x4893, (q15_t)0x9691, (q15_t)0x488e, (q15_t)0x968d, (q15_t)0x4888, (q15_t)0x968a, (q15_t)0x4883, (q15_t)0x9686, + (q15_t)0x487e, (q15_t)0x9683, (q15_t)0x4879, (q15_t)0x967f, (q15_t)0x4874, (q15_t)0x967b, (q15_t)0x486f, (q15_t)0x9678, + (q15_t)0x4869, (q15_t)0x9674, (q15_t)0x4864, (q15_t)0x9671, (q15_t)0x485f, (q15_t)0x966d, (q15_t)0x485a, (q15_t)0x966a, + (q15_t)0x4855, (q15_t)0x9666, (q15_t)0x484f, (q15_t)0x9663, (q15_t)0x484a, (q15_t)0x965f, (q15_t)0x4845, (q15_t)0x965b, + (q15_t)0x4840, (q15_t)0x9658, (q15_t)0x483b, (q15_t)0x9654, (q15_t)0x4836, (q15_t)0x9651, (q15_t)0x4830, (q15_t)0x964d, + (q15_t)0x482b, (q15_t)0x964a, (q15_t)0x4826, (q15_t)0x9646, (q15_t)0x4821, (q15_t)0x9643, (q15_t)0x481c, (q15_t)0x963f, + (q15_t)0x4816, (q15_t)0x963c, (q15_t)0x4811, (q15_t)0x9638, (q15_t)0x480c, (q15_t)0x9635, (q15_t)0x4807, (q15_t)0x9631, + (q15_t)0x4802, (q15_t)0x962d, (q15_t)0x47fc, (q15_t)0x962a, (q15_t)0x47f7, (q15_t)0x9626, (q15_t)0x47f2, (q15_t)0x9623, + (q15_t)0x47ed, (q15_t)0x961f, (q15_t)0x47e8, (q15_t)0x961c, (q15_t)0x47e2, (q15_t)0x9618, (q15_t)0x47dd, (q15_t)0x9615, + (q15_t)0x47d8, (q15_t)0x9611, (q15_t)0x47d3, (q15_t)0x960e, (q15_t)0x47ce, (q15_t)0x960a, (q15_t)0x47c8, (q15_t)0x9607, + (q15_t)0x47c3, (q15_t)0x9603, (q15_t)0x47be, (q15_t)0x9600, (q15_t)0x47b9, (q15_t)0x95fc, (q15_t)0x47b4, (q15_t)0x95f9, + (q15_t)0x47ae, (q15_t)0x95f5, (q15_t)0x47a9, (q15_t)0x95f2, (q15_t)0x47a4, (q15_t)0x95ee, (q15_t)0x479f, (q15_t)0x95ea, + (q15_t)0x479a, (q15_t)0x95e7, (q15_t)0x4794, (q15_t)0x95e3, (q15_t)0x478f, (q15_t)0x95e0, (q15_t)0x478a, (q15_t)0x95dc, + (q15_t)0x4785, (q15_t)0x95d9, (q15_t)0x4780, (q15_t)0x95d5, (q15_t)0x477a, (q15_t)0x95d2, (q15_t)0x4775, (q15_t)0x95ce, + (q15_t)0x4770, (q15_t)0x95cb, (q15_t)0x476b, (q15_t)0x95c7, (q15_t)0x4765, (q15_t)0x95c4, (q15_t)0x4760, (q15_t)0x95c0, + (q15_t)0x475b, (q15_t)0x95bd, (q15_t)0x4756, (q15_t)0x95b9, (q15_t)0x4751, (q15_t)0x95b6, (q15_t)0x474b, (q15_t)0x95b2, + (q15_t)0x4746, (q15_t)0x95af, (q15_t)0x4741, (q15_t)0x95ab, (q15_t)0x473c, (q15_t)0x95a8, (q15_t)0x4737, (q15_t)0x95a4, + (q15_t)0x4731, (q15_t)0x95a1, (q15_t)0x472c, (q15_t)0x959d, (q15_t)0x4727, (q15_t)0x959a, (q15_t)0x4722, (q15_t)0x9596, + (q15_t)0x471c, (q15_t)0x9593, (q15_t)0x4717, (q15_t)0x958f, (q15_t)0x4712, (q15_t)0x958c, (q15_t)0x470d, (q15_t)0x9588, + (q15_t)0x4708, (q15_t)0x9585, (q15_t)0x4702, (q15_t)0x9581, (q15_t)0x46fd, (q15_t)0x957e, (q15_t)0x46f8, (q15_t)0x957a, + (q15_t)0x46f3, (q15_t)0x9577, (q15_t)0x46ed, (q15_t)0x9574, (q15_t)0x46e8, (q15_t)0x9570, (q15_t)0x46e3, (q15_t)0x956d, + (q15_t)0x46de, (q15_t)0x9569, (q15_t)0x46d8, (q15_t)0x9566, (q15_t)0x46d3, (q15_t)0x9562, (q15_t)0x46ce, (q15_t)0x955f, + (q15_t)0x46c9, (q15_t)0x955b, (q15_t)0x46c4, (q15_t)0x9558, (q15_t)0x46be, (q15_t)0x9554, (q15_t)0x46b9, (q15_t)0x9551, + (q15_t)0x46b4, (q15_t)0x954d, (q15_t)0x46af, (q15_t)0x954a, (q15_t)0x46a9, (q15_t)0x9546, (q15_t)0x46a4, (q15_t)0x9543, + (q15_t)0x469f, (q15_t)0x953f, (q15_t)0x469a, (q15_t)0x953c, (q15_t)0x4694, (q15_t)0x9538, (q15_t)0x468f, (q15_t)0x9535, + (q15_t)0x468a, (q15_t)0x9532, (q15_t)0x4685, (q15_t)0x952e, (q15_t)0x467f, (q15_t)0x952b, (q15_t)0x467a, (q15_t)0x9527, + (q15_t)0x4675, (q15_t)0x9524, (q15_t)0x4670, (q15_t)0x9520, (q15_t)0x466a, (q15_t)0x951d, (q15_t)0x4665, (q15_t)0x9519, + (q15_t)0x4660, (q15_t)0x9516, (q15_t)0x465b, (q15_t)0x9512, (q15_t)0x4655, (q15_t)0x950f, (q15_t)0x4650, (q15_t)0x950c, + (q15_t)0x464b, (q15_t)0x9508, (q15_t)0x4646, (q15_t)0x9505, (q15_t)0x4640, (q15_t)0x9501, (q15_t)0x463b, (q15_t)0x94fe, + (q15_t)0x4636, (q15_t)0x94fa, (q15_t)0x4631, (q15_t)0x94f7, (q15_t)0x462b, (q15_t)0x94f3, (q15_t)0x4626, (q15_t)0x94f0, + (q15_t)0x4621, (q15_t)0x94ed, (q15_t)0x461c, (q15_t)0x94e9, (q15_t)0x4616, (q15_t)0x94e6, (q15_t)0x4611, (q15_t)0x94e2, + (q15_t)0x460c, (q15_t)0x94df, (q15_t)0x4607, (q15_t)0x94db, (q15_t)0x4601, (q15_t)0x94d8, (q15_t)0x45fc, (q15_t)0x94d4, + (q15_t)0x45f7, (q15_t)0x94d1, (q15_t)0x45f2, (q15_t)0x94ce, (q15_t)0x45ec, (q15_t)0x94ca, (q15_t)0x45e7, (q15_t)0x94c7, + (q15_t)0x45e2, (q15_t)0x94c3, (q15_t)0x45dd, (q15_t)0x94c0, (q15_t)0x45d7, (q15_t)0x94bc, (q15_t)0x45d2, (q15_t)0x94b9, + (q15_t)0x45cd, (q15_t)0x94b6, (q15_t)0x45c7, (q15_t)0x94b2, (q15_t)0x45c2, (q15_t)0x94af, (q15_t)0x45bd, (q15_t)0x94ab, + (q15_t)0x45b8, (q15_t)0x94a8, (q15_t)0x45b2, (q15_t)0x94a4, (q15_t)0x45ad, (q15_t)0x94a1, (q15_t)0x45a8, (q15_t)0x949e, + (q15_t)0x45a3, (q15_t)0x949a, (q15_t)0x459d, (q15_t)0x9497, (q15_t)0x4598, (q15_t)0x9493, (q15_t)0x4593, (q15_t)0x9490, + (q15_t)0x458d, (q15_t)0x948d, (q15_t)0x4588, (q15_t)0x9489, (q15_t)0x4583, (q15_t)0x9486, (q15_t)0x457e, (q15_t)0x9482, + (q15_t)0x4578, (q15_t)0x947f, (q15_t)0x4573, (q15_t)0x947b, (q15_t)0x456e, (q15_t)0x9478, (q15_t)0x4569, (q15_t)0x9475, + (q15_t)0x4563, (q15_t)0x9471, (q15_t)0x455e, (q15_t)0x946e, (q15_t)0x4559, (q15_t)0x946a, (q15_t)0x4553, (q15_t)0x9467, + (q15_t)0x454e, (q15_t)0x9464, (q15_t)0x4549, (q15_t)0x9460, (q15_t)0x4544, (q15_t)0x945d, (q15_t)0x453e, (q15_t)0x9459, + (q15_t)0x4539, (q15_t)0x9456, (q15_t)0x4534, (q15_t)0x9453, (q15_t)0x452e, (q15_t)0x944f, (q15_t)0x4529, (q15_t)0x944c, + (q15_t)0x4524, (q15_t)0x9448, (q15_t)0x451f, (q15_t)0x9445, (q15_t)0x4519, (q15_t)0x9442, (q15_t)0x4514, (q15_t)0x943e, + (q15_t)0x450f, (q15_t)0x943b, (q15_t)0x4509, (q15_t)0x9437, (q15_t)0x4504, (q15_t)0x9434, (q15_t)0x44ff, (q15_t)0x9431, + (q15_t)0x44fa, (q15_t)0x942d, (q15_t)0x44f4, (q15_t)0x942a, (q15_t)0x44ef, (q15_t)0x9427, (q15_t)0x44ea, (q15_t)0x9423, + (q15_t)0x44e4, (q15_t)0x9420, (q15_t)0x44df, (q15_t)0x941c, (q15_t)0x44da, (q15_t)0x9419, (q15_t)0x44d4, (q15_t)0x9416, + (q15_t)0x44cf, (q15_t)0x9412, (q15_t)0x44ca, (q15_t)0x940f, (q15_t)0x44c5, (q15_t)0x940b, (q15_t)0x44bf, (q15_t)0x9408, + (q15_t)0x44ba, (q15_t)0x9405, (q15_t)0x44b5, (q15_t)0x9401, (q15_t)0x44af, (q15_t)0x93fe, (q15_t)0x44aa, (q15_t)0x93fb, + (q15_t)0x44a5, (q15_t)0x93f7, (q15_t)0x449f, (q15_t)0x93f4, (q15_t)0x449a, (q15_t)0x93f1, (q15_t)0x4495, (q15_t)0x93ed, + (q15_t)0x4490, (q15_t)0x93ea, (q15_t)0x448a, (q15_t)0x93e6, (q15_t)0x4485, (q15_t)0x93e3, (q15_t)0x4480, (q15_t)0x93e0, + (q15_t)0x447a, (q15_t)0x93dc, (q15_t)0x4475, (q15_t)0x93d9, (q15_t)0x4470, (q15_t)0x93d6, (q15_t)0x446a, (q15_t)0x93d2, + (q15_t)0x4465, (q15_t)0x93cf, (q15_t)0x4460, (q15_t)0x93cc, (q15_t)0x445a, (q15_t)0x93c8, (q15_t)0x4455, (q15_t)0x93c5, + (q15_t)0x4450, (q15_t)0x93c1, (q15_t)0x444b, (q15_t)0x93be, (q15_t)0x4445, (q15_t)0x93bb, (q15_t)0x4440, (q15_t)0x93b7, + (q15_t)0x443b, (q15_t)0x93b4, (q15_t)0x4435, (q15_t)0x93b1, (q15_t)0x4430, (q15_t)0x93ad, (q15_t)0x442b, (q15_t)0x93aa, + (q15_t)0x4425, (q15_t)0x93a7, (q15_t)0x4420, (q15_t)0x93a3, (q15_t)0x441b, (q15_t)0x93a0, (q15_t)0x4415, (q15_t)0x939d, + (q15_t)0x4410, (q15_t)0x9399, (q15_t)0x440b, (q15_t)0x9396, (q15_t)0x4405, (q15_t)0x9393, (q15_t)0x4400, (q15_t)0x938f, + (q15_t)0x43fb, (q15_t)0x938c, (q15_t)0x43f5, (q15_t)0x9389, (q15_t)0x43f0, (q15_t)0x9385, (q15_t)0x43eb, (q15_t)0x9382, + (q15_t)0x43e5, (q15_t)0x937f, (q15_t)0x43e0, (q15_t)0x937b, (q15_t)0x43db, (q15_t)0x9378, (q15_t)0x43d5, (q15_t)0x9375, + (q15_t)0x43d0, (q15_t)0x9371, (q15_t)0x43cb, (q15_t)0x936e, (q15_t)0x43c5, (q15_t)0x936b, (q15_t)0x43c0, (q15_t)0x9367, + (q15_t)0x43bb, (q15_t)0x9364, (q15_t)0x43b5, (q15_t)0x9361, (q15_t)0x43b0, (q15_t)0x935d, (q15_t)0x43ab, (q15_t)0x935a, + (q15_t)0x43a5, (q15_t)0x9357, (q15_t)0x43a0, (q15_t)0x9353, (q15_t)0x439b, (q15_t)0x9350, (q15_t)0x4395, (q15_t)0x934d, + (q15_t)0x4390, (q15_t)0x9349, (q15_t)0x438b, (q15_t)0x9346, (q15_t)0x4385, (q15_t)0x9343, (q15_t)0x4380, (q15_t)0x933f, + (q15_t)0x437b, (q15_t)0x933c, (q15_t)0x4375, (q15_t)0x9339, (q15_t)0x4370, (q15_t)0x9336, (q15_t)0x436b, (q15_t)0x9332, + (q15_t)0x4365, (q15_t)0x932f, (q15_t)0x4360, (q15_t)0x932c, (q15_t)0x435b, (q15_t)0x9328, (q15_t)0x4355, (q15_t)0x9325, + (q15_t)0x4350, (q15_t)0x9322, (q15_t)0x434b, (q15_t)0x931e, (q15_t)0x4345, (q15_t)0x931b, (q15_t)0x4340, (q15_t)0x9318, + (q15_t)0x433b, (q15_t)0x9314, (q15_t)0x4335, (q15_t)0x9311, (q15_t)0x4330, (q15_t)0x930e, (q15_t)0x432b, (q15_t)0x930b, + (q15_t)0x4325, (q15_t)0x9307, (q15_t)0x4320, (q15_t)0x9304, (q15_t)0x431b, (q15_t)0x9301, (q15_t)0x4315, (q15_t)0x92fd, + (q15_t)0x4310, (q15_t)0x92fa, (q15_t)0x430b, (q15_t)0x92f7, (q15_t)0x4305, (q15_t)0x92f4, (q15_t)0x4300, (q15_t)0x92f0, + (q15_t)0x42fa, (q15_t)0x92ed, (q15_t)0x42f5, (q15_t)0x92ea, (q15_t)0x42f0, (q15_t)0x92e6, (q15_t)0x42ea, (q15_t)0x92e3, + (q15_t)0x42e5, (q15_t)0x92e0, (q15_t)0x42e0, (q15_t)0x92dd, (q15_t)0x42da, (q15_t)0x92d9, (q15_t)0x42d5, (q15_t)0x92d6, + (q15_t)0x42d0, (q15_t)0x92d3, (q15_t)0x42ca, (q15_t)0x92cf, (q15_t)0x42c5, (q15_t)0x92cc, (q15_t)0x42c0, (q15_t)0x92c9, + (q15_t)0x42ba, (q15_t)0x92c6, (q15_t)0x42b5, (q15_t)0x92c2, (q15_t)0x42af, (q15_t)0x92bf, (q15_t)0x42aa, (q15_t)0x92bc, + (q15_t)0x42a5, (q15_t)0x92b8, (q15_t)0x429f, (q15_t)0x92b5, (q15_t)0x429a, (q15_t)0x92b2, (q15_t)0x4295, (q15_t)0x92af, + (q15_t)0x428f, (q15_t)0x92ab, (q15_t)0x428a, (q15_t)0x92a8, (q15_t)0x4284, (q15_t)0x92a5, (q15_t)0x427f, (q15_t)0x92a2, + (q15_t)0x427a, (q15_t)0x929e, (q15_t)0x4274, (q15_t)0x929b, (q15_t)0x426f, (q15_t)0x9298, (q15_t)0x426a, (q15_t)0x9295, + (q15_t)0x4264, (q15_t)0x9291, (q15_t)0x425f, (q15_t)0x928e, (q15_t)0x425a, (q15_t)0x928b, (q15_t)0x4254, (q15_t)0x9288, + (q15_t)0x424f, (q15_t)0x9284, (q15_t)0x4249, (q15_t)0x9281, (q15_t)0x4244, (q15_t)0x927e, (q15_t)0x423f, (q15_t)0x927b, + (q15_t)0x4239, (q15_t)0x9277, (q15_t)0x4234, (q15_t)0x9274, (q15_t)0x422f, (q15_t)0x9271, (q15_t)0x4229, (q15_t)0x926e, + (q15_t)0x4224, (q15_t)0x926a, (q15_t)0x421e, (q15_t)0x9267, (q15_t)0x4219, (q15_t)0x9264, (q15_t)0x4214, (q15_t)0x9261, + (q15_t)0x420e, (q15_t)0x925d, (q15_t)0x4209, (q15_t)0x925a, (q15_t)0x4203, (q15_t)0x9257, (q15_t)0x41fe, (q15_t)0x9254, + (q15_t)0x41f9, (q15_t)0x9250, (q15_t)0x41f3, (q15_t)0x924d, (q15_t)0x41ee, (q15_t)0x924a, (q15_t)0x41e9, (q15_t)0x9247, + (q15_t)0x41e3, (q15_t)0x9243, (q15_t)0x41de, (q15_t)0x9240, (q15_t)0x41d8, (q15_t)0x923d, (q15_t)0x41d3, (q15_t)0x923a, + (q15_t)0x41ce, (q15_t)0x9236, (q15_t)0x41c8, (q15_t)0x9233, (q15_t)0x41c3, (q15_t)0x9230, (q15_t)0x41bd, (q15_t)0x922d, + (q15_t)0x41b8, (q15_t)0x922a, (q15_t)0x41b3, (q15_t)0x9226, (q15_t)0x41ad, (q15_t)0x9223, (q15_t)0x41a8, (q15_t)0x9220, + (q15_t)0x41a2, (q15_t)0x921d, (q15_t)0x419d, (q15_t)0x9219, (q15_t)0x4198, (q15_t)0x9216, (q15_t)0x4192, (q15_t)0x9213, + (q15_t)0x418d, (q15_t)0x9210, (q15_t)0x4188, (q15_t)0x920d, (q15_t)0x4182, (q15_t)0x9209, (q15_t)0x417d, (q15_t)0x9206, + (q15_t)0x4177, (q15_t)0x9203, (q15_t)0x4172, (q15_t)0x9200, (q15_t)0x416d, (q15_t)0x91fc, (q15_t)0x4167, (q15_t)0x91f9, + (q15_t)0x4162, (q15_t)0x91f6, (q15_t)0x415c, (q15_t)0x91f3, (q15_t)0x4157, (q15_t)0x91f0, (q15_t)0x4152, (q15_t)0x91ec, + (q15_t)0x414c, (q15_t)0x91e9, (q15_t)0x4147, (q15_t)0x91e6, (q15_t)0x4141, (q15_t)0x91e3, (q15_t)0x413c, (q15_t)0x91e0, + (q15_t)0x4136, (q15_t)0x91dc, (q15_t)0x4131, (q15_t)0x91d9, (q15_t)0x412c, (q15_t)0x91d6, (q15_t)0x4126, (q15_t)0x91d3, + (q15_t)0x4121, (q15_t)0x91d0, (q15_t)0x411b, (q15_t)0x91cc, (q15_t)0x4116, (q15_t)0x91c9, (q15_t)0x4111, (q15_t)0x91c6, + (q15_t)0x410b, (q15_t)0x91c3, (q15_t)0x4106, (q15_t)0x91c0, (q15_t)0x4100, (q15_t)0x91bc, (q15_t)0x40fb, (q15_t)0x91b9, + (q15_t)0x40f6, (q15_t)0x91b6, (q15_t)0x40f0, (q15_t)0x91b3, (q15_t)0x40eb, (q15_t)0x91b0, (q15_t)0x40e5, (q15_t)0x91ad, + (q15_t)0x40e0, (q15_t)0x91a9, (q15_t)0x40da, (q15_t)0x91a6, (q15_t)0x40d5, (q15_t)0x91a3, (q15_t)0x40d0, (q15_t)0x91a0, + (q15_t)0x40ca, (q15_t)0x919d, (q15_t)0x40c5, (q15_t)0x9199, (q15_t)0x40bf, (q15_t)0x9196, (q15_t)0x40ba, (q15_t)0x9193, + (q15_t)0x40b5, (q15_t)0x9190, (q15_t)0x40af, (q15_t)0x918d, (q15_t)0x40aa, (q15_t)0x918a, (q15_t)0x40a4, (q15_t)0x9186, + (q15_t)0x409f, (q15_t)0x9183, (q15_t)0x4099, (q15_t)0x9180, (q15_t)0x4094, (q15_t)0x917d, (q15_t)0x408f, (q15_t)0x917a, + (q15_t)0x4089, (q15_t)0x9177, (q15_t)0x4084, (q15_t)0x9173, (q15_t)0x407e, (q15_t)0x9170, (q15_t)0x4079, (q15_t)0x916d, + (q15_t)0x4073, (q15_t)0x916a, (q15_t)0x406e, (q15_t)0x9167, (q15_t)0x4069, (q15_t)0x9164, (q15_t)0x4063, (q15_t)0x9160, + (q15_t)0x405e, (q15_t)0x915d, (q15_t)0x4058, (q15_t)0x915a, (q15_t)0x4053, (q15_t)0x9157, (q15_t)0x404d, (q15_t)0x9154, + (q15_t)0x4048, (q15_t)0x9151, (q15_t)0x4043, (q15_t)0x914d, (q15_t)0x403d, (q15_t)0x914a, (q15_t)0x4038, (q15_t)0x9147, + (q15_t)0x4032, (q15_t)0x9144, (q15_t)0x402d, (q15_t)0x9141, (q15_t)0x4027, (q15_t)0x913e, (q15_t)0x4022, (q15_t)0x913a, + (q15_t)0x401d, (q15_t)0x9137, (q15_t)0x4017, (q15_t)0x9134, (q15_t)0x4012, (q15_t)0x9131, (q15_t)0x400c, (q15_t)0x912e, + (q15_t)0x4007, (q15_t)0x912b, (q15_t)0x4001, (q15_t)0x9128, (q15_t)0x3ffc, (q15_t)0x9124, (q15_t)0x3ff6, (q15_t)0x9121, + (q15_t)0x3ff1, (q15_t)0x911e, (q15_t)0x3fec, (q15_t)0x911b, (q15_t)0x3fe6, (q15_t)0x9118, (q15_t)0x3fe1, (q15_t)0x9115, + (q15_t)0x3fdb, (q15_t)0x9112, (q15_t)0x3fd6, (q15_t)0x910f, (q15_t)0x3fd0, (q15_t)0x910b, (q15_t)0x3fcb, (q15_t)0x9108, + (q15_t)0x3fc5, (q15_t)0x9105, (q15_t)0x3fc0, (q15_t)0x9102, (q15_t)0x3fbb, (q15_t)0x90ff, (q15_t)0x3fb5, (q15_t)0x90fc, + (q15_t)0x3fb0, (q15_t)0x90f9, (q15_t)0x3faa, (q15_t)0x90f5, (q15_t)0x3fa5, (q15_t)0x90f2, (q15_t)0x3f9f, (q15_t)0x90ef, + (q15_t)0x3f9a, (q15_t)0x90ec, (q15_t)0x3f94, (q15_t)0x90e9, (q15_t)0x3f8f, (q15_t)0x90e6, (q15_t)0x3f89, (q15_t)0x90e3, + (q15_t)0x3f84, (q15_t)0x90e0, (q15_t)0x3f7f, (q15_t)0x90dd, (q15_t)0x3f79, (q15_t)0x90d9, (q15_t)0x3f74, (q15_t)0x90d6, + (q15_t)0x3f6e, (q15_t)0x90d3, (q15_t)0x3f69, (q15_t)0x90d0, (q15_t)0x3f63, (q15_t)0x90cd, (q15_t)0x3f5e, (q15_t)0x90ca, + (q15_t)0x3f58, (q15_t)0x90c7, (q15_t)0x3f53, (q15_t)0x90c4, (q15_t)0x3f4d, (q15_t)0x90c1, (q15_t)0x3f48, (q15_t)0x90bd, + (q15_t)0x3f43, (q15_t)0x90ba, (q15_t)0x3f3d, (q15_t)0x90b7, (q15_t)0x3f38, (q15_t)0x90b4, (q15_t)0x3f32, (q15_t)0x90b1, + (q15_t)0x3f2d, (q15_t)0x90ae, (q15_t)0x3f27, (q15_t)0x90ab, (q15_t)0x3f22, (q15_t)0x90a8, (q15_t)0x3f1c, (q15_t)0x90a5, + (q15_t)0x3f17, (q15_t)0x90a1, (q15_t)0x3f11, (q15_t)0x909e, (q15_t)0x3f0c, (q15_t)0x909b, (q15_t)0x3f06, (q15_t)0x9098, + (q15_t)0x3f01, (q15_t)0x9095, (q15_t)0x3efb, (q15_t)0x9092, (q15_t)0x3ef6, (q15_t)0x908f, (q15_t)0x3ef1, (q15_t)0x908c, + (q15_t)0x3eeb, (q15_t)0x9089, (q15_t)0x3ee6, (q15_t)0x9086, (q15_t)0x3ee0, (q15_t)0x9083, (q15_t)0x3edb, (q15_t)0x907f, + (q15_t)0x3ed5, (q15_t)0x907c, (q15_t)0x3ed0, (q15_t)0x9079, (q15_t)0x3eca, (q15_t)0x9076, (q15_t)0x3ec5, (q15_t)0x9073, + (q15_t)0x3ebf, (q15_t)0x9070, (q15_t)0x3eba, (q15_t)0x906d, (q15_t)0x3eb4, (q15_t)0x906a, (q15_t)0x3eaf, (q15_t)0x9067, + (q15_t)0x3ea9, (q15_t)0x9064, (q15_t)0x3ea4, (q15_t)0x9061, (q15_t)0x3e9e, (q15_t)0x905e, (q15_t)0x3e99, (q15_t)0x905b, + (q15_t)0x3e93, (q15_t)0x9057, (q15_t)0x3e8e, (q15_t)0x9054, (q15_t)0x3e88, (q15_t)0x9051, (q15_t)0x3e83, (q15_t)0x904e, + (q15_t)0x3e7d, (q15_t)0x904b, (q15_t)0x3e78, (q15_t)0x9048, (q15_t)0x3e73, (q15_t)0x9045, (q15_t)0x3e6d, (q15_t)0x9042, + (q15_t)0x3e68, (q15_t)0x903f, (q15_t)0x3e62, (q15_t)0x903c, (q15_t)0x3e5d, (q15_t)0x9039, (q15_t)0x3e57, (q15_t)0x9036, + (q15_t)0x3e52, (q15_t)0x9033, (q15_t)0x3e4c, (q15_t)0x9030, (q15_t)0x3e47, (q15_t)0x902d, (q15_t)0x3e41, (q15_t)0x902a, + (q15_t)0x3e3c, (q15_t)0x9026, (q15_t)0x3e36, (q15_t)0x9023, (q15_t)0x3e31, (q15_t)0x9020, (q15_t)0x3e2b, (q15_t)0x901d, + (q15_t)0x3e26, (q15_t)0x901a, (q15_t)0x3e20, (q15_t)0x9017, (q15_t)0x3e1b, (q15_t)0x9014, (q15_t)0x3e15, (q15_t)0x9011, + (q15_t)0x3e10, (q15_t)0x900e, (q15_t)0x3e0a, (q15_t)0x900b, (q15_t)0x3e05, (q15_t)0x9008, (q15_t)0x3dff, (q15_t)0x9005, + (q15_t)0x3dfa, (q15_t)0x9002, (q15_t)0x3df4, (q15_t)0x8fff, (q15_t)0x3def, (q15_t)0x8ffc, (q15_t)0x3de9, (q15_t)0x8ff9, + (q15_t)0x3de4, (q15_t)0x8ff6, (q15_t)0x3dde, (q15_t)0x8ff3, (q15_t)0x3dd9, (q15_t)0x8ff0, (q15_t)0x3dd3, (q15_t)0x8fed, + (q15_t)0x3dce, (q15_t)0x8fea, (q15_t)0x3dc8, (q15_t)0x8fe7, (q15_t)0x3dc3, (q15_t)0x8fe3, (q15_t)0x3dbd, (q15_t)0x8fe0, + (q15_t)0x3db8, (q15_t)0x8fdd, (q15_t)0x3db2, (q15_t)0x8fda, (q15_t)0x3dad, (q15_t)0x8fd7, (q15_t)0x3da7, (q15_t)0x8fd4, + (q15_t)0x3da2, (q15_t)0x8fd1, (q15_t)0x3d9c, (q15_t)0x8fce, (q15_t)0x3d97, (q15_t)0x8fcb, (q15_t)0x3d91, (q15_t)0x8fc8, + (q15_t)0x3d8c, (q15_t)0x8fc5, (q15_t)0x3d86, (q15_t)0x8fc2, (q15_t)0x3d81, (q15_t)0x8fbf, (q15_t)0x3d7b, (q15_t)0x8fbc, + (q15_t)0x3d76, (q15_t)0x8fb9, (q15_t)0x3d70, (q15_t)0x8fb6, (q15_t)0x3d6b, (q15_t)0x8fb3, (q15_t)0x3d65, (q15_t)0x8fb0, + (q15_t)0x3d60, (q15_t)0x8fad, (q15_t)0x3d5a, (q15_t)0x8faa, (q15_t)0x3d55, (q15_t)0x8fa7, (q15_t)0x3d4f, (q15_t)0x8fa4, + (q15_t)0x3d49, (q15_t)0x8fa1, (q15_t)0x3d44, (q15_t)0x8f9e, (q15_t)0x3d3e, (q15_t)0x8f9b, (q15_t)0x3d39, (q15_t)0x8f98, + (q15_t)0x3d33, (q15_t)0x8f95, (q15_t)0x3d2e, (q15_t)0x8f92, (q15_t)0x3d28, (q15_t)0x8f8f, (q15_t)0x3d23, (q15_t)0x8f8c, + (q15_t)0x3d1d, (q15_t)0x8f89, (q15_t)0x3d18, (q15_t)0x8f86, (q15_t)0x3d12, (q15_t)0x8f83, (q15_t)0x3d0d, (q15_t)0x8f80, + (q15_t)0x3d07, (q15_t)0x8f7d, (q15_t)0x3d02, (q15_t)0x8f7a, (q15_t)0x3cfc, (q15_t)0x8f77, (q15_t)0x3cf7, (q15_t)0x8f74, + (q15_t)0x3cf1, (q15_t)0x8f71, (q15_t)0x3cec, (q15_t)0x8f6e, (q15_t)0x3ce6, (q15_t)0x8f6b, (q15_t)0x3ce1, (q15_t)0x8f68, + (q15_t)0x3cdb, (q15_t)0x8f65, (q15_t)0x3cd6, (q15_t)0x8f62, (q15_t)0x3cd0, (q15_t)0x8f5f, (q15_t)0x3cca, (q15_t)0x8f5c, + (q15_t)0x3cc5, (q15_t)0x8f59, (q15_t)0x3cbf, (q15_t)0x8f56, (q15_t)0x3cba, (q15_t)0x8f53, (q15_t)0x3cb4, (q15_t)0x8f50, + (q15_t)0x3caf, (q15_t)0x8f4d, (q15_t)0x3ca9, (q15_t)0x8f4a, (q15_t)0x3ca4, (q15_t)0x8f47, (q15_t)0x3c9e, (q15_t)0x8f44, + (q15_t)0x3c99, (q15_t)0x8f41, (q15_t)0x3c93, (q15_t)0x8f3e, (q15_t)0x3c8e, (q15_t)0x8f3b, (q15_t)0x3c88, (q15_t)0x8f38, + (q15_t)0x3c83, (q15_t)0x8f35, (q15_t)0x3c7d, (q15_t)0x8f32, (q15_t)0x3c77, (q15_t)0x8f2f, (q15_t)0x3c72, (q15_t)0x8f2d, + (q15_t)0x3c6c, (q15_t)0x8f2a, (q15_t)0x3c67, (q15_t)0x8f27, (q15_t)0x3c61, (q15_t)0x8f24, (q15_t)0x3c5c, (q15_t)0x8f21, + (q15_t)0x3c56, (q15_t)0x8f1e, (q15_t)0x3c51, (q15_t)0x8f1b, (q15_t)0x3c4b, (q15_t)0x8f18, (q15_t)0x3c46, (q15_t)0x8f15, + (q15_t)0x3c40, (q15_t)0x8f12, (q15_t)0x3c3b, (q15_t)0x8f0f, (q15_t)0x3c35, (q15_t)0x8f0c, (q15_t)0x3c2f, (q15_t)0x8f09, + (q15_t)0x3c2a, (q15_t)0x8f06, (q15_t)0x3c24, (q15_t)0x8f03, (q15_t)0x3c1f, (q15_t)0x8f00, (q15_t)0x3c19, (q15_t)0x8efd, + (q15_t)0x3c14, (q15_t)0x8efa, (q15_t)0x3c0e, (q15_t)0x8ef7, (q15_t)0x3c09, (q15_t)0x8ef4, (q15_t)0x3c03, (q15_t)0x8ef1, + (q15_t)0x3bfd, (q15_t)0x8eee, (q15_t)0x3bf8, (q15_t)0x8eec, (q15_t)0x3bf2, (q15_t)0x8ee9, (q15_t)0x3bed, (q15_t)0x8ee6, + (q15_t)0x3be7, (q15_t)0x8ee3, (q15_t)0x3be2, (q15_t)0x8ee0, (q15_t)0x3bdc, (q15_t)0x8edd, (q15_t)0x3bd7, (q15_t)0x8eda, + (q15_t)0x3bd1, (q15_t)0x8ed7, (q15_t)0x3bcc, (q15_t)0x8ed4, (q15_t)0x3bc6, (q15_t)0x8ed1, (q15_t)0x3bc0, (q15_t)0x8ece, + (q15_t)0x3bbb, (q15_t)0x8ecb, (q15_t)0x3bb5, (q15_t)0x8ec8, (q15_t)0x3bb0, (q15_t)0x8ec5, (q15_t)0x3baa, (q15_t)0x8ec2, + (q15_t)0x3ba5, (q15_t)0x8ebf, (q15_t)0x3b9f, (q15_t)0x8ebd, (q15_t)0x3b99, (q15_t)0x8eba, (q15_t)0x3b94, (q15_t)0x8eb7, + (q15_t)0x3b8e, (q15_t)0x8eb4, (q15_t)0x3b89, (q15_t)0x8eb1, (q15_t)0x3b83, (q15_t)0x8eae, (q15_t)0x3b7e, (q15_t)0x8eab, + (q15_t)0x3b78, (q15_t)0x8ea8, (q15_t)0x3b73, (q15_t)0x8ea5, (q15_t)0x3b6d, (q15_t)0x8ea2, (q15_t)0x3b67, (q15_t)0x8e9f, + (q15_t)0x3b62, (q15_t)0x8e9c, (q15_t)0x3b5c, (q15_t)0x8e99, (q15_t)0x3b57, (q15_t)0x8e97, (q15_t)0x3b51, (q15_t)0x8e94, + (q15_t)0x3b4c, (q15_t)0x8e91, (q15_t)0x3b46, (q15_t)0x8e8e, (q15_t)0x3b40, (q15_t)0x8e8b, (q15_t)0x3b3b, (q15_t)0x8e88, + (q15_t)0x3b35, (q15_t)0x8e85, (q15_t)0x3b30, (q15_t)0x8e82, (q15_t)0x3b2a, (q15_t)0x8e7f, (q15_t)0x3b25, (q15_t)0x8e7c, + (q15_t)0x3b1f, (q15_t)0x8e7a, (q15_t)0x3b19, (q15_t)0x8e77, (q15_t)0x3b14, (q15_t)0x8e74, (q15_t)0x3b0e, (q15_t)0x8e71, + (q15_t)0x3b09, (q15_t)0x8e6e, (q15_t)0x3b03, (q15_t)0x8e6b, (q15_t)0x3afe, (q15_t)0x8e68, (q15_t)0x3af8, (q15_t)0x8e65, + (q15_t)0x3af2, (q15_t)0x8e62, (q15_t)0x3aed, (q15_t)0x8e5f, (q15_t)0x3ae7, (q15_t)0x8e5d, (q15_t)0x3ae2, (q15_t)0x8e5a, + (q15_t)0x3adc, (q15_t)0x8e57, (q15_t)0x3ad7, (q15_t)0x8e54, (q15_t)0x3ad1, (q15_t)0x8e51, (q15_t)0x3acb, (q15_t)0x8e4e, + (q15_t)0x3ac6, (q15_t)0x8e4b, (q15_t)0x3ac0, (q15_t)0x8e48, (q15_t)0x3abb, (q15_t)0x8e45, (q15_t)0x3ab5, (q15_t)0x8e43, + (q15_t)0x3aaf, (q15_t)0x8e40, (q15_t)0x3aaa, (q15_t)0x8e3d, (q15_t)0x3aa4, (q15_t)0x8e3a, (q15_t)0x3a9f, (q15_t)0x8e37, + (q15_t)0x3a99, (q15_t)0x8e34, (q15_t)0x3a94, (q15_t)0x8e31, (q15_t)0x3a8e, (q15_t)0x8e2e, (q15_t)0x3a88, (q15_t)0x8e2c, + (q15_t)0x3a83, (q15_t)0x8e29, (q15_t)0x3a7d, (q15_t)0x8e26, (q15_t)0x3a78, (q15_t)0x8e23, (q15_t)0x3a72, (q15_t)0x8e20, + (q15_t)0x3a6c, (q15_t)0x8e1d, (q15_t)0x3a67, (q15_t)0x8e1a, (q15_t)0x3a61, (q15_t)0x8e17, (q15_t)0x3a5c, (q15_t)0x8e15, + (q15_t)0x3a56, (q15_t)0x8e12, (q15_t)0x3a50, (q15_t)0x8e0f, (q15_t)0x3a4b, (q15_t)0x8e0c, (q15_t)0x3a45, (q15_t)0x8e09, + (q15_t)0x3a40, (q15_t)0x8e06, (q15_t)0x3a3a, (q15_t)0x8e03, (q15_t)0x3a34, (q15_t)0x8e01, (q15_t)0x3a2f, (q15_t)0x8dfe, + (q15_t)0x3a29, (q15_t)0x8dfb, (q15_t)0x3a24, (q15_t)0x8df8, (q15_t)0x3a1e, (q15_t)0x8df5, (q15_t)0x3a19, (q15_t)0x8df2, + (q15_t)0x3a13, (q15_t)0x8def, (q15_t)0x3a0d, (q15_t)0x8ded, (q15_t)0x3a08, (q15_t)0x8dea, (q15_t)0x3a02, (q15_t)0x8de7, + (q15_t)0x39fd, (q15_t)0x8de4, (q15_t)0x39f7, (q15_t)0x8de1, (q15_t)0x39f1, (q15_t)0x8dde, (q15_t)0x39ec, (q15_t)0x8ddc, + (q15_t)0x39e6, (q15_t)0x8dd9, (q15_t)0x39e0, (q15_t)0x8dd6, (q15_t)0x39db, (q15_t)0x8dd3, (q15_t)0x39d5, (q15_t)0x8dd0, + (q15_t)0x39d0, (q15_t)0x8dcd, (q15_t)0x39ca, (q15_t)0x8dca, (q15_t)0x39c4, (q15_t)0x8dc8, (q15_t)0x39bf, (q15_t)0x8dc5, + (q15_t)0x39b9, (q15_t)0x8dc2, (q15_t)0x39b4, (q15_t)0x8dbf, (q15_t)0x39ae, (q15_t)0x8dbc, (q15_t)0x39a8, (q15_t)0x8db9, + (q15_t)0x39a3, (q15_t)0x8db7, (q15_t)0x399d, (q15_t)0x8db4, (q15_t)0x3998, (q15_t)0x8db1, (q15_t)0x3992, (q15_t)0x8dae, + (q15_t)0x398c, (q15_t)0x8dab, (q15_t)0x3987, (q15_t)0x8da9, (q15_t)0x3981, (q15_t)0x8da6, (q15_t)0x397c, (q15_t)0x8da3, + (q15_t)0x3976, (q15_t)0x8da0, (q15_t)0x3970, (q15_t)0x8d9d, (q15_t)0x396b, (q15_t)0x8d9a, (q15_t)0x3965, (q15_t)0x8d98, + (q15_t)0x395f, (q15_t)0x8d95, (q15_t)0x395a, (q15_t)0x8d92, (q15_t)0x3954, (q15_t)0x8d8f, (q15_t)0x394f, (q15_t)0x8d8c, + (q15_t)0x3949, (q15_t)0x8d8a, (q15_t)0x3943, (q15_t)0x8d87, (q15_t)0x393e, (q15_t)0x8d84, (q15_t)0x3938, (q15_t)0x8d81, + (q15_t)0x3932, (q15_t)0x8d7e, (q15_t)0x392d, (q15_t)0x8d7b, (q15_t)0x3927, (q15_t)0x8d79, (q15_t)0x3922, (q15_t)0x8d76, + (q15_t)0x391c, (q15_t)0x8d73, (q15_t)0x3916, (q15_t)0x8d70, (q15_t)0x3911, (q15_t)0x8d6d, (q15_t)0x390b, (q15_t)0x8d6b, + (q15_t)0x3906, (q15_t)0x8d68, (q15_t)0x3900, (q15_t)0x8d65, (q15_t)0x38fa, (q15_t)0x8d62, (q15_t)0x38f5, (q15_t)0x8d5f, + (q15_t)0x38ef, (q15_t)0x8d5d, (q15_t)0x38e9, (q15_t)0x8d5a, (q15_t)0x38e4, (q15_t)0x8d57, (q15_t)0x38de, (q15_t)0x8d54, + (q15_t)0x38d8, (q15_t)0x8d51, (q15_t)0x38d3, (q15_t)0x8d4f, (q15_t)0x38cd, (q15_t)0x8d4c, (q15_t)0x38c8, (q15_t)0x8d49, + (q15_t)0x38c2, (q15_t)0x8d46, (q15_t)0x38bc, (q15_t)0x8d44, (q15_t)0x38b7, (q15_t)0x8d41, (q15_t)0x38b1, (q15_t)0x8d3e, + (q15_t)0x38ab, (q15_t)0x8d3b, (q15_t)0x38a6, (q15_t)0x8d38, (q15_t)0x38a0, (q15_t)0x8d36, (q15_t)0x389b, (q15_t)0x8d33, + (q15_t)0x3895, (q15_t)0x8d30, (q15_t)0x388f, (q15_t)0x8d2d, (q15_t)0x388a, (q15_t)0x8d2b, (q15_t)0x3884, (q15_t)0x8d28, + (q15_t)0x387e, (q15_t)0x8d25, (q15_t)0x3879, (q15_t)0x8d22, (q15_t)0x3873, (q15_t)0x8d1f, (q15_t)0x386d, (q15_t)0x8d1d, + (q15_t)0x3868, (q15_t)0x8d1a, (q15_t)0x3862, (q15_t)0x8d17, (q15_t)0x385d, (q15_t)0x8d14, (q15_t)0x3857, (q15_t)0x8d12, + (q15_t)0x3851, (q15_t)0x8d0f, (q15_t)0x384c, (q15_t)0x8d0c, (q15_t)0x3846, (q15_t)0x8d09, (q15_t)0x3840, (q15_t)0x8d07, + (q15_t)0x383b, (q15_t)0x8d04, (q15_t)0x3835, (q15_t)0x8d01, (q15_t)0x382f, (q15_t)0x8cfe, (q15_t)0x382a, (q15_t)0x8cfb, + (q15_t)0x3824, (q15_t)0x8cf9, (q15_t)0x381e, (q15_t)0x8cf6, (q15_t)0x3819, (q15_t)0x8cf3, (q15_t)0x3813, (q15_t)0x8cf0, + (q15_t)0x380d, (q15_t)0x8cee, (q15_t)0x3808, (q15_t)0x8ceb, (q15_t)0x3802, (q15_t)0x8ce8, (q15_t)0x37fd, (q15_t)0x8ce5, + (q15_t)0x37f7, (q15_t)0x8ce3, (q15_t)0x37f1, (q15_t)0x8ce0, (q15_t)0x37ec, (q15_t)0x8cdd, (q15_t)0x37e6, (q15_t)0x8cda, + (q15_t)0x37e0, (q15_t)0x8cd8, (q15_t)0x37db, (q15_t)0x8cd5, (q15_t)0x37d5, (q15_t)0x8cd2, (q15_t)0x37cf, (q15_t)0x8cd0, + (q15_t)0x37ca, (q15_t)0x8ccd, (q15_t)0x37c4, (q15_t)0x8cca, (q15_t)0x37be, (q15_t)0x8cc7, (q15_t)0x37b9, (q15_t)0x8cc5, + (q15_t)0x37b3, (q15_t)0x8cc2, (q15_t)0x37ad, (q15_t)0x8cbf, (q15_t)0x37a8, (q15_t)0x8cbc, (q15_t)0x37a2, (q15_t)0x8cba, + (q15_t)0x379c, (q15_t)0x8cb7, (q15_t)0x3797, (q15_t)0x8cb4, (q15_t)0x3791, (q15_t)0x8cb1, (q15_t)0x378b, (q15_t)0x8caf, + (q15_t)0x3786, (q15_t)0x8cac, (q15_t)0x3780, (q15_t)0x8ca9, (q15_t)0x377a, (q15_t)0x8ca7, (q15_t)0x3775, (q15_t)0x8ca4, + (q15_t)0x376f, (q15_t)0x8ca1, (q15_t)0x3769, (q15_t)0x8c9e, (q15_t)0x3764, (q15_t)0x8c9c, (q15_t)0x375e, (q15_t)0x8c99, + (q15_t)0x3758, (q15_t)0x8c96, (q15_t)0x3753, (q15_t)0x8c94, (q15_t)0x374d, (q15_t)0x8c91, (q15_t)0x3747, (q15_t)0x8c8e, + (q15_t)0x3742, (q15_t)0x8c8b, (q15_t)0x373c, (q15_t)0x8c89, (q15_t)0x3736, (q15_t)0x8c86, (q15_t)0x3731, (q15_t)0x8c83, + (q15_t)0x372b, (q15_t)0x8c81, (q15_t)0x3725, (q15_t)0x8c7e, (q15_t)0x3720, (q15_t)0x8c7b, (q15_t)0x371a, (q15_t)0x8c78, + (q15_t)0x3714, (q15_t)0x8c76, (q15_t)0x370f, (q15_t)0x8c73, (q15_t)0x3709, (q15_t)0x8c70, (q15_t)0x3703, (q15_t)0x8c6e, + (q15_t)0x36fe, (q15_t)0x8c6b, (q15_t)0x36f8, (q15_t)0x8c68, (q15_t)0x36f2, (q15_t)0x8c65, (q15_t)0x36ed, (q15_t)0x8c63, + (q15_t)0x36e7, (q15_t)0x8c60, (q15_t)0x36e1, (q15_t)0x8c5d, (q15_t)0x36dc, (q15_t)0x8c5b, (q15_t)0x36d6, (q15_t)0x8c58, + (q15_t)0x36d0, (q15_t)0x8c55, (q15_t)0x36cb, (q15_t)0x8c53, (q15_t)0x36c5, (q15_t)0x8c50, (q15_t)0x36bf, (q15_t)0x8c4d, + (q15_t)0x36ba, (q15_t)0x8c4b, (q15_t)0x36b4, (q15_t)0x8c48, (q15_t)0x36ae, (q15_t)0x8c45, (q15_t)0x36a9, (q15_t)0x8c43, + (q15_t)0x36a3, (q15_t)0x8c40, (q15_t)0x369d, (q15_t)0x8c3d, (q15_t)0x3698, (q15_t)0x8c3a, (q15_t)0x3692, (q15_t)0x8c38, + (q15_t)0x368c, (q15_t)0x8c35, (q15_t)0x3686, (q15_t)0x8c32, (q15_t)0x3681, (q15_t)0x8c30, (q15_t)0x367b, (q15_t)0x8c2d, + (q15_t)0x3675, (q15_t)0x8c2a, (q15_t)0x3670, (q15_t)0x8c28, (q15_t)0x366a, (q15_t)0x8c25, (q15_t)0x3664, (q15_t)0x8c22, + (q15_t)0x365f, (q15_t)0x8c20, (q15_t)0x3659, (q15_t)0x8c1d, (q15_t)0x3653, (q15_t)0x8c1a, (q15_t)0x364e, (q15_t)0x8c18, + (q15_t)0x3648, (q15_t)0x8c15, (q15_t)0x3642, (q15_t)0x8c12, (q15_t)0x363d, (q15_t)0x8c10, (q15_t)0x3637, (q15_t)0x8c0d, + (q15_t)0x3631, (q15_t)0x8c0a, (q15_t)0x362b, (q15_t)0x8c08, (q15_t)0x3626, (q15_t)0x8c05, (q15_t)0x3620, (q15_t)0x8c02, + (q15_t)0x361a, (q15_t)0x8c00, (q15_t)0x3615, (q15_t)0x8bfd, (q15_t)0x360f, (q15_t)0x8bfa, (q15_t)0x3609, (q15_t)0x8bf8, + (q15_t)0x3604, (q15_t)0x8bf5, (q15_t)0x35fe, (q15_t)0x8bf3, (q15_t)0x35f8, (q15_t)0x8bf0, (q15_t)0x35f3, (q15_t)0x8bed, + (q15_t)0x35ed, (q15_t)0x8beb, (q15_t)0x35e7, (q15_t)0x8be8, (q15_t)0x35e1, (q15_t)0x8be5, (q15_t)0x35dc, (q15_t)0x8be3, + (q15_t)0x35d6, (q15_t)0x8be0, (q15_t)0x35d0, (q15_t)0x8bdd, (q15_t)0x35cb, (q15_t)0x8bdb, (q15_t)0x35c5, (q15_t)0x8bd8, + (q15_t)0x35bf, (q15_t)0x8bd5, (q15_t)0x35ba, (q15_t)0x8bd3, (q15_t)0x35b4, (q15_t)0x8bd0, (q15_t)0x35ae, (q15_t)0x8bce, + (q15_t)0x35a8, (q15_t)0x8bcb, (q15_t)0x35a3, (q15_t)0x8bc8, (q15_t)0x359d, (q15_t)0x8bc6, (q15_t)0x3597, (q15_t)0x8bc3, + (q15_t)0x3592, (q15_t)0x8bc0, (q15_t)0x358c, (q15_t)0x8bbe, (q15_t)0x3586, (q15_t)0x8bbb, (q15_t)0x3580, (q15_t)0x8bb8, + (q15_t)0x357b, (q15_t)0x8bb6, (q15_t)0x3575, (q15_t)0x8bb3, (q15_t)0x356f, (q15_t)0x8bb1, (q15_t)0x356a, (q15_t)0x8bae, + (q15_t)0x3564, (q15_t)0x8bab, (q15_t)0x355e, (q15_t)0x8ba9, (q15_t)0x3558, (q15_t)0x8ba6, (q15_t)0x3553, (q15_t)0x8ba4, + (q15_t)0x354d, (q15_t)0x8ba1, (q15_t)0x3547, (q15_t)0x8b9e, (q15_t)0x3542, (q15_t)0x8b9c, (q15_t)0x353c, (q15_t)0x8b99, + (q15_t)0x3536, (q15_t)0x8b96, (q15_t)0x3530, (q15_t)0x8b94, (q15_t)0x352b, (q15_t)0x8b91, (q15_t)0x3525, (q15_t)0x8b8f, + (q15_t)0x351f, (q15_t)0x8b8c, (q15_t)0x351a, (q15_t)0x8b89, (q15_t)0x3514, (q15_t)0x8b87, (q15_t)0x350e, (q15_t)0x8b84, + (q15_t)0x3508, (q15_t)0x8b82, (q15_t)0x3503, (q15_t)0x8b7f, (q15_t)0x34fd, (q15_t)0x8b7c, (q15_t)0x34f7, (q15_t)0x8b7a, + (q15_t)0x34f2, (q15_t)0x8b77, (q15_t)0x34ec, (q15_t)0x8b75, (q15_t)0x34e6, (q15_t)0x8b72, (q15_t)0x34e0, (q15_t)0x8b6f, + (q15_t)0x34db, (q15_t)0x8b6d, (q15_t)0x34d5, (q15_t)0x8b6a, (q15_t)0x34cf, (q15_t)0x8b68, (q15_t)0x34ca, (q15_t)0x8b65, + (q15_t)0x34c4, (q15_t)0x8b62, (q15_t)0x34be, (q15_t)0x8b60, (q15_t)0x34b8, (q15_t)0x8b5d, (q15_t)0x34b3, (q15_t)0x8b5b, + (q15_t)0x34ad, (q15_t)0x8b58, (q15_t)0x34a7, (q15_t)0x8b55, (q15_t)0x34a1, (q15_t)0x8b53, (q15_t)0x349c, (q15_t)0x8b50, + (q15_t)0x3496, (q15_t)0x8b4e, (q15_t)0x3490, (q15_t)0x8b4b, (q15_t)0x348b, (q15_t)0x8b49, (q15_t)0x3485, (q15_t)0x8b46, + (q15_t)0x347f, (q15_t)0x8b43, (q15_t)0x3479, (q15_t)0x8b41, (q15_t)0x3474, (q15_t)0x8b3e, (q15_t)0x346e, (q15_t)0x8b3c, + (q15_t)0x3468, (q15_t)0x8b39, (q15_t)0x3462, (q15_t)0x8b37, (q15_t)0x345d, (q15_t)0x8b34, (q15_t)0x3457, (q15_t)0x8b31, + (q15_t)0x3451, (q15_t)0x8b2f, (q15_t)0x344b, (q15_t)0x8b2c, (q15_t)0x3446, (q15_t)0x8b2a, (q15_t)0x3440, (q15_t)0x8b27, + (q15_t)0x343a, (q15_t)0x8b25, (q15_t)0x3435, (q15_t)0x8b22, (q15_t)0x342f, (q15_t)0x8b1f, (q15_t)0x3429, (q15_t)0x8b1d, + (q15_t)0x3423, (q15_t)0x8b1a, (q15_t)0x341e, (q15_t)0x8b18, (q15_t)0x3418, (q15_t)0x8b15, (q15_t)0x3412, (q15_t)0x8b13, + (q15_t)0x340c, (q15_t)0x8b10, (q15_t)0x3407, (q15_t)0x8b0e, (q15_t)0x3401, (q15_t)0x8b0b, (q15_t)0x33fb, (q15_t)0x8b08, + (q15_t)0x33f5, (q15_t)0x8b06, (q15_t)0x33f0, (q15_t)0x8b03, (q15_t)0x33ea, (q15_t)0x8b01, (q15_t)0x33e4, (q15_t)0x8afe, + (q15_t)0x33de, (q15_t)0x8afc, (q15_t)0x33d9, (q15_t)0x8af9, (q15_t)0x33d3, (q15_t)0x8af7, (q15_t)0x33cd, (q15_t)0x8af4, + (q15_t)0x33c7, (q15_t)0x8af1, (q15_t)0x33c2, (q15_t)0x8aef, (q15_t)0x33bc, (q15_t)0x8aec, (q15_t)0x33b6, (q15_t)0x8aea, + (q15_t)0x33b0, (q15_t)0x8ae7, (q15_t)0x33ab, (q15_t)0x8ae5, (q15_t)0x33a5, (q15_t)0x8ae2, (q15_t)0x339f, (q15_t)0x8ae0, + (q15_t)0x3399, (q15_t)0x8add, (q15_t)0x3394, (q15_t)0x8adb, (q15_t)0x338e, (q15_t)0x8ad8, (q15_t)0x3388, (q15_t)0x8ad6, + (q15_t)0x3382, (q15_t)0x8ad3, (q15_t)0x337d, (q15_t)0x8ad1, (q15_t)0x3377, (q15_t)0x8ace, (q15_t)0x3371, (q15_t)0x8acb, + (q15_t)0x336b, (q15_t)0x8ac9, (q15_t)0x3366, (q15_t)0x8ac6, (q15_t)0x3360, (q15_t)0x8ac4, (q15_t)0x335a, (q15_t)0x8ac1, + (q15_t)0x3354, (q15_t)0x8abf, (q15_t)0x334f, (q15_t)0x8abc, (q15_t)0x3349, (q15_t)0x8aba, (q15_t)0x3343, (q15_t)0x8ab7, + (q15_t)0x333d, (q15_t)0x8ab5, (q15_t)0x3338, (q15_t)0x8ab2, (q15_t)0x3332, (q15_t)0x8ab0, (q15_t)0x332c, (q15_t)0x8aad, + (q15_t)0x3326, (q15_t)0x8aab, (q15_t)0x3321, (q15_t)0x8aa8, (q15_t)0x331b, (q15_t)0x8aa6, (q15_t)0x3315, (q15_t)0x8aa3, + (q15_t)0x330f, (q15_t)0x8aa1, (q15_t)0x330a, (q15_t)0x8a9e, (q15_t)0x3304, (q15_t)0x8a9c, (q15_t)0x32fe, (q15_t)0x8a99, + (q15_t)0x32f8, (q15_t)0x8a97, (q15_t)0x32f3, (q15_t)0x8a94, (q15_t)0x32ed, (q15_t)0x8a92, (q15_t)0x32e7, (q15_t)0x8a8f, + (q15_t)0x32e1, (q15_t)0x8a8d, (q15_t)0x32db, (q15_t)0x8a8a, (q15_t)0x32d6, (q15_t)0x8a88, (q15_t)0x32d0, (q15_t)0x8a85, + (q15_t)0x32ca, (q15_t)0x8a83, (q15_t)0x32c4, (q15_t)0x8a80, (q15_t)0x32bf, (q15_t)0x8a7e, (q15_t)0x32b9, (q15_t)0x8a7b, + (q15_t)0x32b3, (q15_t)0x8a79, (q15_t)0x32ad, (q15_t)0x8a76, (q15_t)0x32a8, (q15_t)0x8a74, (q15_t)0x32a2, (q15_t)0x8a71, + (q15_t)0x329c, (q15_t)0x8a6f, (q15_t)0x3296, (q15_t)0x8a6c, (q15_t)0x3290, (q15_t)0x8a6a, (q15_t)0x328b, (q15_t)0x8a67, + (q15_t)0x3285, (q15_t)0x8a65, (q15_t)0x327f, (q15_t)0x8a62, (q15_t)0x3279, (q15_t)0x8a60, (q15_t)0x3274, (q15_t)0x8a5d, + (q15_t)0x326e, (q15_t)0x8a5b, (q15_t)0x3268, (q15_t)0x8a59, (q15_t)0x3262, (q15_t)0x8a56, (q15_t)0x325d, (q15_t)0x8a54, + (q15_t)0x3257, (q15_t)0x8a51, (q15_t)0x3251, (q15_t)0x8a4f, (q15_t)0x324b, (q15_t)0x8a4c, (q15_t)0x3245, (q15_t)0x8a4a, + (q15_t)0x3240, (q15_t)0x8a47, (q15_t)0x323a, (q15_t)0x8a45, (q15_t)0x3234, (q15_t)0x8a42, (q15_t)0x322e, (q15_t)0x8a40, + (q15_t)0x3228, (q15_t)0x8a3d, (q15_t)0x3223, (q15_t)0x8a3b, (q15_t)0x321d, (q15_t)0x8a38, (q15_t)0x3217, (q15_t)0x8a36, + (q15_t)0x3211, (q15_t)0x8a34, (q15_t)0x320c, (q15_t)0x8a31, (q15_t)0x3206, (q15_t)0x8a2f, (q15_t)0x3200, (q15_t)0x8a2c, + (q15_t)0x31fa, (q15_t)0x8a2a, (q15_t)0x31f4, (q15_t)0x8a27, (q15_t)0x31ef, (q15_t)0x8a25, (q15_t)0x31e9, (q15_t)0x8a22, + (q15_t)0x31e3, (q15_t)0x8a20, (q15_t)0x31dd, (q15_t)0x8a1d, (q15_t)0x31d8, (q15_t)0x8a1b, (q15_t)0x31d2, (q15_t)0x8a19, + (q15_t)0x31cc, (q15_t)0x8a16, (q15_t)0x31c6, (q15_t)0x8a14, (q15_t)0x31c0, (q15_t)0x8a11, (q15_t)0x31bb, (q15_t)0x8a0f, + (q15_t)0x31b5, (q15_t)0x8a0c, (q15_t)0x31af, (q15_t)0x8a0a, (q15_t)0x31a9, (q15_t)0x8a07, (q15_t)0x31a3, (q15_t)0x8a05, + (q15_t)0x319e, (q15_t)0x8a03, (q15_t)0x3198, (q15_t)0x8a00, (q15_t)0x3192, (q15_t)0x89fe, (q15_t)0x318c, (q15_t)0x89fb, + (q15_t)0x3186, (q15_t)0x89f9, (q15_t)0x3181, (q15_t)0x89f6, (q15_t)0x317b, (q15_t)0x89f4, (q15_t)0x3175, (q15_t)0x89f2, + (q15_t)0x316f, (q15_t)0x89ef, (q15_t)0x3169, (q15_t)0x89ed, (q15_t)0x3164, (q15_t)0x89ea, (q15_t)0x315e, (q15_t)0x89e8, + (q15_t)0x3158, (q15_t)0x89e5, (q15_t)0x3152, (q15_t)0x89e3, (q15_t)0x314c, (q15_t)0x89e1, (q15_t)0x3147, (q15_t)0x89de, + (q15_t)0x3141, (q15_t)0x89dc, (q15_t)0x313b, (q15_t)0x89d9, (q15_t)0x3135, (q15_t)0x89d7, (q15_t)0x312f, (q15_t)0x89d5, + (q15_t)0x312a, (q15_t)0x89d2, (q15_t)0x3124, (q15_t)0x89d0, (q15_t)0x311e, (q15_t)0x89cd, (q15_t)0x3118, (q15_t)0x89cb, + (q15_t)0x3112, (q15_t)0x89c8, (q15_t)0x310d, (q15_t)0x89c6, (q15_t)0x3107, (q15_t)0x89c4, (q15_t)0x3101, (q15_t)0x89c1, + (q15_t)0x30fb, (q15_t)0x89bf, (q15_t)0x30f5, (q15_t)0x89bc, (q15_t)0x30f0, (q15_t)0x89ba, (q15_t)0x30ea, (q15_t)0x89b8, + (q15_t)0x30e4, (q15_t)0x89b5, (q15_t)0x30de, (q15_t)0x89b3, (q15_t)0x30d8, (q15_t)0x89b0, (q15_t)0x30d3, (q15_t)0x89ae, + (q15_t)0x30cd, (q15_t)0x89ac, (q15_t)0x30c7, (q15_t)0x89a9, (q15_t)0x30c1, (q15_t)0x89a7, (q15_t)0x30bb, (q15_t)0x89a4, + (q15_t)0x30b6, (q15_t)0x89a2, (q15_t)0x30b0, (q15_t)0x89a0, (q15_t)0x30aa, (q15_t)0x899d, (q15_t)0x30a4, (q15_t)0x899b, + (q15_t)0x309e, (q15_t)0x8998, (q15_t)0x3099, (q15_t)0x8996, (q15_t)0x3093, (q15_t)0x8994, (q15_t)0x308d, (q15_t)0x8991, + (q15_t)0x3087, (q15_t)0x898f, (q15_t)0x3081, (q15_t)0x898d, (q15_t)0x307b, (q15_t)0x898a, (q15_t)0x3076, (q15_t)0x8988, + (q15_t)0x3070, (q15_t)0x8985, (q15_t)0x306a, (q15_t)0x8983, (q15_t)0x3064, (q15_t)0x8981, (q15_t)0x305e, (q15_t)0x897e, + (q15_t)0x3059, (q15_t)0x897c, (q15_t)0x3053, (q15_t)0x897a, (q15_t)0x304d, (q15_t)0x8977, (q15_t)0x3047, (q15_t)0x8975, + (q15_t)0x3041, (q15_t)0x8972, (q15_t)0x303b, (q15_t)0x8970, (q15_t)0x3036, (q15_t)0x896e, (q15_t)0x3030, (q15_t)0x896b, + (q15_t)0x302a, (q15_t)0x8969, (q15_t)0x3024, (q15_t)0x8967, (q15_t)0x301e, (q15_t)0x8964, (q15_t)0x3019, (q15_t)0x8962, + (q15_t)0x3013, (q15_t)0x8960, (q15_t)0x300d, (q15_t)0x895d, (q15_t)0x3007, (q15_t)0x895b, (q15_t)0x3001, (q15_t)0x8958, + (q15_t)0x2ffb, (q15_t)0x8956, (q15_t)0x2ff6, (q15_t)0x8954, (q15_t)0x2ff0, (q15_t)0x8951, (q15_t)0x2fea, (q15_t)0x894f, + (q15_t)0x2fe4, (q15_t)0x894d, (q15_t)0x2fde, (q15_t)0x894a, (q15_t)0x2fd8, (q15_t)0x8948, (q15_t)0x2fd3, (q15_t)0x8946, + (q15_t)0x2fcd, (q15_t)0x8943, (q15_t)0x2fc7, (q15_t)0x8941, (q15_t)0x2fc1, (q15_t)0x893f, (q15_t)0x2fbb, (q15_t)0x893c, + (q15_t)0x2fb5, (q15_t)0x893a, (q15_t)0x2fb0, (q15_t)0x8938, (q15_t)0x2faa, (q15_t)0x8935, (q15_t)0x2fa4, (q15_t)0x8933, + (q15_t)0x2f9e, (q15_t)0x8931, (q15_t)0x2f98, (q15_t)0x892e, (q15_t)0x2f92, (q15_t)0x892c, (q15_t)0x2f8d, (q15_t)0x892a, + (q15_t)0x2f87, (q15_t)0x8927, (q15_t)0x2f81, (q15_t)0x8925, (q15_t)0x2f7b, (q15_t)0x8923, (q15_t)0x2f75, (q15_t)0x8920, + (q15_t)0x2f6f, (q15_t)0x891e, (q15_t)0x2f6a, (q15_t)0x891c, (q15_t)0x2f64, (q15_t)0x8919, (q15_t)0x2f5e, (q15_t)0x8917, + (q15_t)0x2f58, (q15_t)0x8915, (q15_t)0x2f52, (q15_t)0x8912, (q15_t)0x2f4c, (q15_t)0x8910, (q15_t)0x2f47, (q15_t)0x890e, + (q15_t)0x2f41, (q15_t)0x890b, (q15_t)0x2f3b, (q15_t)0x8909, (q15_t)0x2f35, (q15_t)0x8907, (q15_t)0x2f2f, (q15_t)0x8904, + (q15_t)0x2f29, (q15_t)0x8902, (q15_t)0x2f24, (q15_t)0x8900, (q15_t)0x2f1e, (q15_t)0x88fd, (q15_t)0x2f18, (q15_t)0x88fb, + (q15_t)0x2f12, (q15_t)0x88f9, (q15_t)0x2f0c, (q15_t)0x88f6, (q15_t)0x2f06, (q15_t)0x88f4, (q15_t)0x2f01, (q15_t)0x88f2, + (q15_t)0x2efb, (q15_t)0x88f0, (q15_t)0x2ef5, (q15_t)0x88ed, (q15_t)0x2eef, (q15_t)0x88eb, (q15_t)0x2ee9, (q15_t)0x88e9, + (q15_t)0x2ee3, (q15_t)0x88e6, (q15_t)0x2edd, (q15_t)0x88e4, (q15_t)0x2ed8, (q15_t)0x88e2, (q15_t)0x2ed2, (q15_t)0x88df, + (q15_t)0x2ecc, (q15_t)0x88dd, (q15_t)0x2ec6, (q15_t)0x88db, (q15_t)0x2ec0, (q15_t)0x88d9, (q15_t)0x2eba, (q15_t)0x88d6, + (q15_t)0x2eb5, (q15_t)0x88d4, (q15_t)0x2eaf, (q15_t)0x88d2, (q15_t)0x2ea9, (q15_t)0x88cf, (q15_t)0x2ea3, (q15_t)0x88cd, + (q15_t)0x2e9d, (q15_t)0x88cb, (q15_t)0x2e97, (q15_t)0x88c8, (q15_t)0x2e91, (q15_t)0x88c6, (q15_t)0x2e8c, (q15_t)0x88c4, + (q15_t)0x2e86, (q15_t)0x88c2, (q15_t)0x2e80, (q15_t)0x88bf, (q15_t)0x2e7a, (q15_t)0x88bd, (q15_t)0x2e74, (q15_t)0x88bb, + (q15_t)0x2e6e, (q15_t)0x88b9, (q15_t)0x2e68, (q15_t)0x88b6, (q15_t)0x2e63, (q15_t)0x88b4, (q15_t)0x2e5d, (q15_t)0x88b2, + (q15_t)0x2e57, (q15_t)0x88af, (q15_t)0x2e51, (q15_t)0x88ad, (q15_t)0x2e4b, (q15_t)0x88ab, (q15_t)0x2e45, (q15_t)0x88a9, + (q15_t)0x2e3f, (q15_t)0x88a6, (q15_t)0x2e3a, (q15_t)0x88a4, (q15_t)0x2e34, (q15_t)0x88a2, (q15_t)0x2e2e, (q15_t)0x88a0, + (q15_t)0x2e28, (q15_t)0x889d, (q15_t)0x2e22, (q15_t)0x889b, (q15_t)0x2e1c, (q15_t)0x8899, (q15_t)0x2e16, (q15_t)0x8896, + (q15_t)0x2e11, (q15_t)0x8894, (q15_t)0x2e0b, (q15_t)0x8892, (q15_t)0x2e05, (q15_t)0x8890, (q15_t)0x2dff, (q15_t)0x888d, + (q15_t)0x2df9, (q15_t)0x888b, (q15_t)0x2df3, (q15_t)0x8889, (q15_t)0x2ded, (q15_t)0x8887, (q15_t)0x2de7, (q15_t)0x8884, + (q15_t)0x2de2, (q15_t)0x8882, (q15_t)0x2ddc, (q15_t)0x8880, (q15_t)0x2dd6, (q15_t)0x887e, (q15_t)0x2dd0, (q15_t)0x887b, + (q15_t)0x2dca, (q15_t)0x8879, (q15_t)0x2dc4, (q15_t)0x8877, (q15_t)0x2dbe, (q15_t)0x8875, (q15_t)0x2db9, (q15_t)0x8872, + (q15_t)0x2db3, (q15_t)0x8870, (q15_t)0x2dad, (q15_t)0x886e, (q15_t)0x2da7, (q15_t)0x886c, (q15_t)0x2da1, (q15_t)0x8869, + (q15_t)0x2d9b, (q15_t)0x8867, (q15_t)0x2d95, (q15_t)0x8865, (q15_t)0x2d8f, (q15_t)0x8863, (q15_t)0x2d8a, (q15_t)0x8860, + (q15_t)0x2d84, (q15_t)0x885e, (q15_t)0x2d7e, (q15_t)0x885c, (q15_t)0x2d78, (q15_t)0x885a, (q15_t)0x2d72, (q15_t)0x8858, + (q15_t)0x2d6c, (q15_t)0x8855, (q15_t)0x2d66, (q15_t)0x8853, (q15_t)0x2d60, (q15_t)0x8851, (q15_t)0x2d5b, (q15_t)0x884f, + (q15_t)0x2d55, (q15_t)0x884c, (q15_t)0x2d4f, (q15_t)0x884a, (q15_t)0x2d49, (q15_t)0x8848, (q15_t)0x2d43, (q15_t)0x8846, + (q15_t)0x2d3d, (q15_t)0x8844, (q15_t)0x2d37, (q15_t)0x8841, (q15_t)0x2d31, (q15_t)0x883f, (q15_t)0x2d2c, (q15_t)0x883d, + (q15_t)0x2d26, (q15_t)0x883b, (q15_t)0x2d20, (q15_t)0x8838, (q15_t)0x2d1a, (q15_t)0x8836, (q15_t)0x2d14, (q15_t)0x8834, + (q15_t)0x2d0e, (q15_t)0x8832, (q15_t)0x2d08, (q15_t)0x8830, (q15_t)0x2d02, (q15_t)0x882d, (q15_t)0x2cfd, (q15_t)0x882b, + (q15_t)0x2cf7, (q15_t)0x8829, (q15_t)0x2cf1, (q15_t)0x8827, (q15_t)0x2ceb, (q15_t)0x8825, (q15_t)0x2ce5, (q15_t)0x8822, + (q15_t)0x2cdf, (q15_t)0x8820, (q15_t)0x2cd9, (q15_t)0x881e, (q15_t)0x2cd3, (q15_t)0x881c, (q15_t)0x2ccd, (q15_t)0x881a, + (q15_t)0x2cc8, (q15_t)0x8817, (q15_t)0x2cc2, (q15_t)0x8815, (q15_t)0x2cbc, (q15_t)0x8813, (q15_t)0x2cb6, (q15_t)0x8811, + (q15_t)0x2cb0, (q15_t)0x880f, (q15_t)0x2caa, (q15_t)0x880c, (q15_t)0x2ca4, (q15_t)0x880a, (q15_t)0x2c9e, (q15_t)0x8808, + (q15_t)0x2c98, (q15_t)0x8806, (q15_t)0x2c93, (q15_t)0x8804, (q15_t)0x2c8d, (q15_t)0x8801, (q15_t)0x2c87, (q15_t)0x87ff, + (q15_t)0x2c81, (q15_t)0x87fd, (q15_t)0x2c7b, (q15_t)0x87fb, (q15_t)0x2c75, (q15_t)0x87f9, (q15_t)0x2c6f, (q15_t)0x87f6, + (q15_t)0x2c69, (q15_t)0x87f4, (q15_t)0x2c63, (q15_t)0x87f2, (q15_t)0x2c5e, (q15_t)0x87f0, (q15_t)0x2c58, (q15_t)0x87ee, + (q15_t)0x2c52, (q15_t)0x87ec, (q15_t)0x2c4c, (q15_t)0x87e9, (q15_t)0x2c46, (q15_t)0x87e7, (q15_t)0x2c40, (q15_t)0x87e5, + (q15_t)0x2c3a, (q15_t)0x87e3, (q15_t)0x2c34, (q15_t)0x87e1, (q15_t)0x2c2e, (q15_t)0x87df, (q15_t)0x2c29, (q15_t)0x87dc, + (q15_t)0x2c23, (q15_t)0x87da, (q15_t)0x2c1d, (q15_t)0x87d8, (q15_t)0x2c17, (q15_t)0x87d6, (q15_t)0x2c11, (q15_t)0x87d4, + (q15_t)0x2c0b, (q15_t)0x87d2, (q15_t)0x2c05, (q15_t)0x87cf, (q15_t)0x2bff, (q15_t)0x87cd, (q15_t)0x2bf9, (q15_t)0x87cb, + (q15_t)0x2bf3, (q15_t)0x87c9, (q15_t)0x2bee, (q15_t)0x87c7, (q15_t)0x2be8, (q15_t)0x87c5, (q15_t)0x2be2, (q15_t)0x87c2, + (q15_t)0x2bdc, (q15_t)0x87c0, (q15_t)0x2bd6, (q15_t)0x87be, (q15_t)0x2bd0, (q15_t)0x87bc, (q15_t)0x2bca, (q15_t)0x87ba, + (q15_t)0x2bc4, (q15_t)0x87b8, (q15_t)0x2bbe, (q15_t)0x87b6, (q15_t)0x2bb8, (q15_t)0x87b3, (q15_t)0x2bb2, (q15_t)0x87b1, + (q15_t)0x2bad, (q15_t)0x87af, (q15_t)0x2ba7, (q15_t)0x87ad, (q15_t)0x2ba1, (q15_t)0x87ab, (q15_t)0x2b9b, (q15_t)0x87a9, + (q15_t)0x2b95, (q15_t)0x87a7, (q15_t)0x2b8f, (q15_t)0x87a4, (q15_t)0x2b89, (q15_t)0x87a2, (q15_t)0x2b83, (q15_t)0x87a0, + (q15_t)0x2b7d, (q15_t)0x879e, (q15_t)0x2b77, (q15_t)0x879c, (q15_t)0x2b71, (q15_t)0x879a, (q15_t)0x2b6c, (q15_t)0x8798, + (q15_t)0x2b66, (q15_t)0x8795, (q15_t)0x2b60, (q15_t)0x8793, (q15_t)0x2b5a, (q15_t)0x8791, (q15_t)0x2b54, (q15_t)0x878f, + (q15_t)0x2b4e, (q15_t)0x878d, (q15_t)0x2b48, (q15_t)0x878b, (q15_t)0x2b42, (q15_t)0x8789, (q15_t)0x2b3c, (q15_t)0x8787, + (q15_t)0x2b36, (q15_t)0x8784, (q15_t)0x2b30, (q15_t)0x8782, (q15_t)0x2b2b, (q15_t)0x8780, (q15_t)0x2b25, (q15_t)0x877e, + (q15_t)0x2b1f, (q15_t)0x877c, (q15_t)0x2b19, (q15_t)0x877a, (q15_t)0x2b13, (q15_t)0x8778, (q15_t)0x2b0d, (q15_t)0x8776, + (q15_t)0x2b07, (q15_t)0x8774, (q15_t)0x2b01, (q15_t)0x8771, (q15_t)0x2afb, (q15_t)0x876f, (q15_t)0x2af5, (q15_t)0x876d, + (q15_t)0x2aef, (q15_t)0x876b, (q15_t)0x2ae9, (q15_t)0x8769, (q15_t)0x2ae4, (q15_t)0x8767, (q15_t)0x2ade, (q15_t)0x8765, + (q15_t)0x2ad8, (q15_t)0x8763, (q15_t)0x2ad2, (q15_t)0x8761, (q15_t)0x2acc, (q15_t)0x875e, (q15_t)0x2ac6, (q15_t)0x875c, + (q15_t)0x2ac0, (q15_t)0x875a, (q15_t)0x2aba, (q15_t)0x8758, (q15_t)0x2ab4, (q15_t)0x8756, (q15_t)0x2aae, (q15_t)0x8754, + (q15_t)0x2aa8, (q15_t)0x8752, (q15_t)0x2aa2, (q15_t)0x8750, (q15_t)0x2a9c, (q15_t)0x874e, (q15_t)0x2a97, (q15_t)0x874c, + (q15_t)0x2a91, (q15_t)0x874a, (q15_t)0x2a8b, (q15_t)0x8747, (q15_t)0x2a85, (q15_t)0x8745, (q15_t)0x2a7f, (q15_t)0x8743, + (q15_t)0x2a79, (q15_t)0x8741, (q15_t)0x2a73, (q15_t)0x873f, (q15_t)0x2a6d, (q15_t)0x873d, (q15_t)0x2a67, (q15_t)0x873b, + (q15_t)0x2a61, (q15_t)0x8739, (q15_t)0x2a5b, (q15_t)0x8737, (q15_t)0x2a55, (q15_t)0x8735, (q15_t)0x2a4f, (q15_t)0x8733, + (q15_t)0x2a49, (q15_t)0x8731, (q15_t)0x2a44, (q15_t)0x872e, (q15_t)0x2a3e, (q15_t)0x872c, (q15_t)0x2a38, (q15_t)0x872a, + (q15_t)0x2a32, (q15_t)0x8728, (q15_t)0x2a2c, (q15_t)0x8726, (q15_t)0x2a26, (q15_t)0x8724, (q15_t)0x2a20, (q15_t)0x8722, + (q15_t)0x2a1a, (q15_t)0x8720, (q15_t)0x2a14, (q15_t)0x871e, (q15_t)0x2a0e, (q15_t)0x871c, (q15_t)0x2a08, (q15_t)0x871a, + (q15_t)0x2a02, (q15_t)0x8718, (q15_t)0x29fc, (q15_t)0x8716, (q15_t)0x29f6, (q15_t)0x8714, (q15_t)0x29f0, (q15_t)0x8712, + (q15_t)0x29eb, (q15_t)0x870f, (q15_t)0x29e5, (q15_t)0x870d, (q15_t)0x29df, (q15_t)0x870b, (q15_t)0x29d9, (q15_t)0x8709, + (q15_t)0x29d3, (q15_t)0x8707, (q15_t)0x29cd, (q15_t)0x8705, (q15_t)0x29c7, (q15_t)0x8703, (q15_t)0x29c1, (q15_t)0x8701, + (q15_t)0x29bb, (q15_t)0x86ff, (q15_t)0x29b5, (q15_t)0x86fd, (q15_t)0x29af, (q15_t)0x86fb, (q15_t)0x29a9, (q15_t)0x86f9, + (q15_t)0x29a3, (q15_t)0x86f7, (q15_t)0x299d, (q15_t)0x86f5, (q15_t)0x2997, (q15_t)0x86f3, (q15_t)0x2991, (q15_t)0x86f1, + (q15_t)0x298b, (q15_t)0x86ef, (q15_t)0x2986, (q15_t)0x86ed, (q15_t)0x2980, (q15_t)0x86eb, (q15_t)0x297a, (q15_t)0x86e9, + (q15_t)0x2974, (q15_t)0x86e7, (q15_t)0x296e, (q15_t)0x86e4, (q15_t)0x2968, (q15_t)0x86e2, (q15_t)0x2962, (q15_t)0x86e0, + (q15_t)0x295c, (q15_t)0x86de, (q15_t)0x2956, (q15_t)0x86dc, (q15_t)0x2950, (q15_t)0x86da, (q15_t)0x294a, (q15_t)0x86d8, + (q15_t)0x2944, (q15_t)0x86d6, (q15_t)0x293e, (q15_t)0x86d4, (q15_t)0x2938, (q15_t)0x86d2, (q15_t)0x2932, (q15_t)0x86d0, + (q15_t)0x292c, (q15_t)0x86ce, (q15_t)0x2926, (q15_t)0x86cc, (q15_t)0x2920, (q15_t)0x86ca, (q15_t)0x291b, (q15_t)0x86c8, + (q15_t)0x2915, (q15_t)0x86c6, (q15_t)0x290f, (q15_t)0x86c4, (q15_t)0x2909, (q15_t)0x86c2, (q15_t)0x2903, (q15_t)0x86c0, + (q15_t)0x28fd, (q15_t)0x86be, (q15_t)0x28f7, (q15_t)0x86bc, (q15_t)0x28f1, (q15_t)0x86ba, (q15_t)0x28eb, (q15_t)0x86b8, + (q15_t)0x28e5, (q15_t)0x86b6, (q15_t)0x28df, (q15_t)0x86b4, (q15_t)0x28d9, (q15_t)0x86b2, (q15_t)0x28d3, (q15_t)0x86b0, + (q15_t)0x28cd, (q15_t)0x86ae, (q15_t)0x28c7, (q15_t)0x86ac, (q15_t)0x28c1, (q15_t)0x86aa, (q15_t)0x28bb, (q15_t)0x86a8, + (q15_t)0x28b5, (q15_t)0x86a6, (q15_t)0x28af, (q15_t)0x86a4, (q15_t)0x28a9, (q15_t)0x86a2, (q15_t)0x28a3, (q15_t)0x86a0, + (q15_t)0x289d, (q15_t)0x869e, (q15_t)0x2898, (q15_t)0x869c, (q15_t)0x2892, (q15_t)0x869a, (q15_t)0x288c, (q15_t)0x8698, + (q15_t)0x2886, (q15_t)0x8696, (q15_t)0x2880, (q15_t)0x8694, (q15_t)0x287a, (q15_t)0x8692, (q15_t)0x2874, (q15_t)0x8690, + (q15_t)0x286e, (q15_t)0x868e, (q15_t)0x2868, (q15_t)0x868c, (q15_t)0x2862, (q15_t)0x868a, (q15_t)0x285c, (q15_t)0x8688, + (q15_t)0x2856, (q15_t)0x8686, (q15_t)0x2850, (q15_t)0x8684, (q15_t)0x284a, (q15_t)0x8682, (q15_t)0x2844, (q15_t)0x8680, + (q15_t)0x283e, (q15_t)0x867e, (q15_t)0x2838, (q15_t)0x867c, (q15_t)0x2832, (q15_t)0x867a, (q15_t)0x282c, (q15_t)0x8678, + (q15_t)0x2826, (q15_t)0x8676, (q15_t)0x2820, (q15_t)0x8674, (q15_t)0x281a, (q15_t)0x8672, (q15_t)0x2814, (q15_t)0x8670, + (q15_t)0x280e, (q15_t)0x866e, (q15_t)0x2808, (q15_t)0x866d, (q15_t)0x2802, (q15_t)0x866b, (q15_t)0x27fc, (q15_t)0x8669, + (q15_t)0x27f6, (q15_t)0x8667, (q15_t)0x27f1, (q15_t)0x8665, (q15_t)0x27eb, (q15_t)0x8663, (q15_t)0x27e5, (q15_t)0x8661, + (q15_t)0x27df, (q15_t)0x865f, (q15_t)0x27d9, (q15_t)0x865d, (q15_t)0x27d3, (q15_t)0x865b, (q15_t)0x27cd, (q15_t)0x8659, + (q15_t)0x27c7, (q15_t)0x8657, (q15_t)0x27c1, (q15_t)0x8655, (q15_t)0x27bb, (q15_t)0x8653, (q15_t)0x27b5, (q15_t)0x8651, + (q15_t)0x27af, (q15_t)0x864f, (q15_t)0x27a9, (q15_t)0x864d, (q15_t)0x27a3, (q15_t)0x864b, (q15_t)0x279d, (q15_t)0x8649, + (q15_t)0x2797, (q15_t)0x8647, (q15_t)0x2791, (q15_t)0x8645, (q15_t)0x278b, (q15_t)0x8644, (q15_t)0x2785, (q15_t)0x8642, + (q15_t)0x277f, (q15_t)0x8640, (q15_t)0x2779, (q15_t)0x863e, (q15_t)0x2773, (q15_t)0x863c, (q15_t)0x276d, (q15_t)0x863a, + (q15_t)0x2767, (q15_t)0x8638, (q15_t)0x2761, (q15_t)0x8636, (q15_t)0x275b, (q15_t)0x8634, (q15_t)0x2755, (q15_t)0x8632, + (q15_t)0x274f, (q15_t)0x8630, (q15_t)0x2749, (q15_t)0x862e, (q15_t)0x2743, (q15_t)0x862c, (q15_t)0x273d, (q15_t)0x862a, + (q15_t)0x2737, (q15_t)0x8628, (q15_t)0x2731, (q15_t)0x8627, (q15_t)0x272b, (q15_t)0x8625, (q15_t)0x2725, (q15_t)0x8623, + (q15_t)0x271f, (q15_t)0x8621, (q15_t)0x2719, (q15_t)0x861f, (q15_t)0x2713, (q15_t)0x861d, (q15_t)0x270d, (q15_t)0x861b, + (q15_t)0x2707, (q15_t)0x8619, (q15_t)0x2701, (q15_t)0x8617, (q15_t)0x26fb, (q15_t)0x8615, (q15_t)0x26f5, (q15_t)0x8613, + (q15_t)0x26ef, (q15_t)0x8611, (q15_t)0x26e9, (q15_t)0x8610, (q15_t)0x26e4, (q15_t)0x860e, (q15_t)0x26de, (q15_t)0x860c, + (q15_t)0x26d8, (q15_t)0x860a, (q15_t)0x26d2, (q15_t)0x8608, (q15_t)0x26cc, (q15_t)0x8606, (q15_t)0x26c6, (q15_t)0x8604, + (q15_t)0x26c0, (q15_t)0x8602, (q15_t)0x26ba, (q15_t)0x8600, (q15_t)0x26b4, (q15_t)0x85fe, (q15_t)0x26ae, (q15_t)0x85fc, + (q15_t)0x26a8, (q15_t)0x85fb, (q15_t)0x26a2, (q15_t)0x85f9, (q15_t)0x269c, (q15_t)0x85f7, (q15_t)0x2696, (q15_t)0x85f5, + (q15_t)0x2690, (q15_t)0x85f3, (q15_t)0x268a, (q15_t)0x85f1, (q15_t)0x2684, (q15_t)0x85ef, (q15_t)0x267e, (q15_t)0x85ed, + (q15_t)0x2678, (q15_t)0x85eb, (q15_t)0x2672, (q15_t)0x85ea, (q15_t)0x266c, (q15_t)0x85e8, (q15_t)0x2666, (q15_t)0x85e6, + (q15_t)0x2660, (q15_t)0x85e4, (q15_t)0x265a, (q15_t)0x85e2, (q15_t)0x2654, (q15_t)0x85e0, (q15_t)0x264e, (q15_t)0x85de, + (q15_t)0x2648, (q15_t)0x85dc, (q15_t)0x2642, (q15_t)0x85da, (q15_t)0x263c, (q15_t)0x85d9, (q15_t)0x2636, (q15_t)0x85d7, + (q15_t)0x2630, (q15_t)0x85d5, (q15_t)0x262a, (q15_t)0x85d3, (q15_t)0x2624, (q15_t)0x85d1, (q15_t)0x261e, (q15_t)0x85cf, + (q15_t)0x2618, (q15_t)0x85cd, (q15_t)0x2612, (q15_t)0x85cb, (q15_t)0x260c, (q15_t)0x85ca, (q15_t)0x2606, (q15_t)0x85c8, + (q15_t)0x2600, (q15_t)0x85c6, (q15_t)0x25fa, (q15_t)0x85c4, (q15_t)0x25f4, (q15_t)0x85c2, (q15_t)0x25ee, (q15_t)0x85c0, + (q15_t)0x25e8, (q15_t)0x85be, (q15_t)0x25e2, (q15_t)0x85bd, (q15_t)0x25dc, (q15_t)0x85bb, (q15_t)0x25d6, (q15_t)0x85b9, + (q15_t)0x25d0, (q15_t)0x85b7, (q15_t)0x25ca, (q15_t)0x85b5, (q15_t)0x25c4, (q15_t)0x85b3, (q15_t)0x25be, (q15_t)0x85b1, + (q15_t)0x25b8, (q15_t)0x85b0, (q15_t)0x25b2, (q15_t)0x85ae, (q15_t)0x25ac, (q15_t)0x85ac, (q15_t)0x25a6, (q15_t)0x85aa, + (q15_t)0x25a0, (q15_t)0x85a8, (q15_t)0x259a, (q15_t)0x85a6, (q15_t)0x2594, (q15_t)0x85a4, (q15_t)0x258e, (q15_t)0x85a3, + (q15_t)0x2588, (q15_t)0x85a1, (q15_t)0x2582, (q15_t)0x859f, (q15_t)0x257c, (q15_t)0x859d, (q15_t)0x2576, (q15_t)0x859b, + (q15_t)0x2570, (q15_t)0x8599, (q15_t)0x256a, (q15_t)0x8598, (q15_t)0x2564, (q15_t)0x8596, (q15_t)0x255e, (q15_t)0x8594, + (q15_t)0x2558, (q15_t)0x8592, (q15_t)0x2552, (q15_t)0x8590, (q15_t)0x254c, (q15_t)0x858e, (q15_t)0x2546, (q15_t)0x858d, + (q15_t)0x2540, (q15_t)0x858b, (q15_t)0x253a, (q15_t)0x8589, (q15_t)0x2534, (q15_t)0x8587, (q15_t)0x252e, (q15_t)0x8585, + (q15_t)0x2528, (q15_t)0x8583, (q15_t)0x2522, (q15_t)0x8582, (q15_t)0x251c, (q15_t)0x8580, (q15_t)0x2516, (q15_t)0x857e, + (q15_t)0x250f, (q15_t)0x857c, (q15_t)0x2509, (q15_t)0x857a, (q15_t)0x2503, (q15_t)0x8579, (q15_t)0x24fd, (q15_t)0x8577, + (q15_t)0x24f7, (q15_t)0x8575, (q15_t)0x24f1, (q15_t)0x8573, (q15_t)0x24eb, (q15_t)0x8571, (q15_t)0x24e5, (q15_t)0x856f, + (q15_t)0x24df, (q15_t)0x856e, (q15_t)0x24d9, (q15_t)0x856c, (q15_t)0x24d3, (q15_t)0x856a, (q15_t)0x24cd, (q15_t)0x8568, + (q15_t)0x24c7, (q15_t)0x8566, (q15_t)0x24c1, (q15_t)0x8565, (q15_t)0x24bb, (q15_t)0x8563, (q15_t)0x24b5, (q15_t)0x8561, + (q15_t)0x24af, (q15_t)0x855f, (q15_t)0x24a9, (q15_t)0x855d, (q15_t)0x24a3, (q15_t)0x855c, (q15_t)0x249d, (q15_t)0x855a, + (q15_t)0x2497, (q15_t)0x8558, (q15_t)0x2491, (q15_t)0x8556, (q15_t)0x248b, (q15_t)0x8554, (q15_t)0x2485, (q15_t)0x8553, + (q15_t)0x247f, (q15_t)0x8551, (q15_t)0x2479, (q15_t)0x854f, (q15_t)0x2473, (q15_t)0x854d, (q15_t)0x246d, (q15_t)0x854b, + (q15_t)0x2467, (q15_t)0x854a, (q15_t)0x2461, (q15_t)0x8548, (q15_t)0x245b, (q15_t)0x8546, (q15_t)0x2455, (q15_t)0x8544, + (q15_t)0x244f, (q15_t)0x8543, (q15_t)0x2449, (q15_t)0x8541, (q15_t)0x2443, (q15_t)0x853f, (q15_t)0x243d, (q15_t)0x853d, + (q15_t)0x2437, (q15_t)0x853b, (q15_t)0x2431, (q15_t)0x853a, (q15_t)0x242b, (q15_t)0x8538, (q15_t)0x2425, (q15_t)0x8536, + (q15_t)0x241f, (q15_t)0x8534, (q15_t)0x2419, (q15_t)0x8533, (q15_t)0x2413, (q15_t)0x8531, (q15_t)0x240d, (q15_t)0x852f, + (q15_t)0x2407, (q15_t)0x852d, (q15_t)0x2401, (q15_t)0x852b, (q15_t)0x23fa, (q15_t)0x852a, (q15_t)0x23f4, (q15_t)0x8528, + (q15_t)0x23ee, (q15_t)0x8526, (q15_t)0x23e8, (q15_t)0x8524, (q15_t)0x23e2, (q15_t)0x8523, (q15_t)0x23dc, (q15_t)0x8521, + (q15_t)0x23d6, (q15_t)0x851f, (q15_t)0x23d0, (q15_t)0x851d, (q15_t)0x23ca, (q15_t)0x851c, (q15_t)0x23c4, (q15_t)0x851a, + (q15_t)0x23be, (q15_t)0x8518, (q15_t)0x23b8, (q15_t)0x8516, (q15_t)0x23b2, (q15_t)0x8515, (q15_t)0x23ac, (q15_t)0x8513, + (q15_t)0x23a6, (q15_t)0x8511, (q15_t)0x23a0, (q15_t)0x850f, (q15_t)0x239a, (q15_t)0x850e, (q15_t)0x2394, (q15_t)0x850c, + (q15_t)0x238e, (q15_t)0x850a, (q15_t)0x2388, (q15_t)0x8508, (q15_t)0x2382, (q15_t)0x8507, (q15_t)0x237c, (q15_t)0x8505, + (q15_t)0x2376, (q15_t)0x8503, (q15_t)0x2370, (q15_t)0x8501, (q15_t)0x236a, (q15_t)0x8500, (q15_t)0x2364, (q15_t)0x84fe, + (q15_t)0x235e, (q15_t)0x84fc, (q15_t)0x2358, (q15_t)0x84fa, (q15_t)0x2352, (q15_t)0x84f9, (q15_t)0x234b, (q15_t)0x84f7, + (q15_t)0x2345, (q15_t)0x84f5, (q15_t)0x233f, (q15_t)0x84f4, (q15_t)0x2339, (q15_t)0x84f2, (q15_t)0x2333, (q15_t)0x84f0, + (q15_t)0x232d, (q15_t)0x84ee, (q15_t)0x2327, (q15_t)0x84ed, (q15_t)0x2321, (q15_t)0x84eb, (q15_t)0x231b, (q15_t)0x84e9, + (q15_t)0x2315, (q15_t)0x84e7, (q15_t)0x230f, (q15_t)0x84e6, (q15_t)0x2309, (q15_t)0x84e4, (q15_t)0x2303, (q15_t)0x84e2, + (q15_t)0x22fd, (q15_t)0x84e1, (q15_t)0x22f7, (q15_t)0x84df, (q15_t)0x22f1, (q15_t)0x84dd, (q15_t)0x22eb, (q15_t)0x84db, + (q15_t)0x22e5, (q15_t)0x84da, (q15_t)0x22df, (q15_t)0x84d8, (q15_t)0x22d9, (q15_t)0x84d6, (q15_t)0x22d3, (q15_t)0x84d5, + (q15_t)0x22cd, (q15_t)0x84d3, (q15_t)0x22c7, (q15_t)0x84d1, (q15_t)0x22c0, (q15_t)0x84cf, (q15_t)0x22ba, (q15_t)0x84ce, + (q15_t)0x22b4, (q15_t)0x84cc, (q15_t)0x22ae, (q15_t)0x84ca, (q15_t)0x22a8, (q15_t)0x84c9, (q15_t)0x22a2, (q15_t)0x84c7, + (q15_t)0x229c, (q15_t)0x84c5, (q15_t)0x2296, (q15_t)0x84c4, (q15_t)0x2290, (q15_t)0x84c2, (q15_t)0x228a, (q15_t)0x84c0, + (q15_t)0x2284, (q15_t)0x84be, (q15_t)0x227e, (q15_t)0x84bd, (q15_t)0x2278, (q15_t)0x84bb, (q15_t)0x2272, (q15_t)0x84b9, + (q15_t)0x226c, (q15_t)0x84b8, (q15_t)0x2266, (q15_t)0x84b6, (q15_t)0x2260, (q15_t)0x84b4, (q15_t)0x225a, (q15_t)0x84b3, + (q15_t)0x2254, (q15_t)0x84b1, (q15_t)0x224e, (q15_t)0x84af, (q15_t)0x2247, (q15_t)0x84ae, (q15_t)0x2241, (q15_t)0x84ac, + (q15_t)0x223b, (q15_t)0x84aa, (q15_t)0x2235, (q15_t)0x84a9, (q15_t)0x222f, (q15_t)0x84a7, (q15_t)0x2229, (q15_t)0x84a5, + (q15_t)0x2223, (q15_t)0x84a3, (q15_t)0x221d, (q15_t)0x84a2, (q15_t)0x2217, (q15_t)0x84a0, (q15_t)0x2211, (q15_t)0x849e, + (q15_t)0x220b, (q15_t)0x849d, (q15_t)0x2205, (q15_t)0x849b, (q15_t)0x21ff, (q15_t)0x8499, (q15_t)0x21f9, (q15_t)0x8498, + (q15_t)0x21f3, (q15_t)0x8496, (q15_t)0x21ed, (q15_t)0x8494, (q15_t)0x21e7, (q15_t)0x8493, (q15_t)0x21e1, (q15_t)0x8491, + (q15_t)0x21da, (q15_t)0x848f, (q15_t)0x21d4, (q15_t)0x848e, (q15_t)0x21ce, (q15_t)0x848c, (q15_t)0x21c8, (q15_t)0x848a, + (q15_t)0x21c2, (q15_t)0x8489, (q15_t)0x21bc, (q15_t)0x8487, (q15_t)0x21b6, (q15_t)0x8486, (q15_t)0x21b0, (q15_t)0x8484, + (q15_t)0x21aa, (q15_t)0x8482, (q15_t)0x21a4, (q15_t)0x8481, (q15_t)0x219e, (q15_t)0x847f, (q15_t)0x2198, (q15_t)0x847d, + (q15_t)0x2192, (q15_t)0x847c, (q15_t)0x218c, (q15_t)0x847a, (q15_t)0x2186, (q15_t)0x8478, (q15_t)0x2180, (q15_t)0x8477, + (q15_t)0x2179, (q15_t)0x8475, (q15_t)0x2173, (q15_t)0x8473, (q15_t)0x216d, (q15_t)0x8472, (q15_t)0x2167, (q15_t)0x8470, + (q15_t)0x2161, (q15_t)0x846e, (q15_t)0x215b, (q15_t)0x846d, (q15_t)0x2155, (q15_t)0x846b, (q15_t)0x214f, (q15_t)0x846a, + (q15_t)0x2149, (q15_t)0x8468, (q15_t)0x2143, (q15_t)0x8466, (q15_t)0x213d, (q15_t)0x8465, (q15_t)0x2137, (q15_t)0x8463, + (q15_t)0x2131, (q15_t)0x8461, (q15_t)0x212b, (q15_t)0x8460, (q15_t)0x2125, (q15_t)0x845e, (q15_t)0x211e, (q15_t)0x845d, + (q15_t)0x2118, (q15_t)0x845b, (q15_t)0x2112, (q15_t)0x8459, (q15_t)0x210c, (q15_t)0x8458, (q15_t)0x2106, (q15_t)0x8456, + (q15_t)0x2100, (q15_t)0x8454, (q15_t)0x20fa, (q15_t)0x8453, (q15_t)0x20f4, (q15_t)0x8451, (q15_t)0x20ee, (q15_t)0x8450, + (q15_t)0x20e8, (q15_t)0x844e, (q15_t)0x20e2, (q15_t)0x844c, (q15_t)0x20dc, (q15_t)0x844b, (q15_t)0x20d6, (q15_t)0x8449, + (q15_t)0x20d0, (q15_t)0x8447, (q15_t)0x20c9, (q15_t)0x8446, (q15_t)0x20c3, (q15_t)0x8444, (q15_t)0x20bd, (q15_t)0x8443, + (q15_t)0x20b7, (q15_t)0x8441, (q15_t)0x20b1, (q15_t)0x843f, (q15_t)0x20ab, (q15_t)0x843e, (q15_t)0x20a5, (q15_t)0x843c, + (q15_t)0x209f, (q15_t)0x843b, (q15_t)0x2099, (q15_t)0x8439, (q15_t)0x2093, (q15_t)0x8437, (q15_t)0x208d, (q15_t)0x8436, + (q15_t)0x2087, (q15_t)0x8434, (q15_t)0x2081, (q15_t)0x8433, (q15_t)0x207a, (q15_t)0x8431, (q15_t)0x2074, (q15_t)0x842f, + (q15_t)0x206e, (q15_t)0x842e, (q15_t)0x2068, (q15_t)0x842c, (q15_t)0x2062, (q15_t)0x842b, (q15_t)0x205c, (q15_t)0x8429, + (q15_t)0x2056, (q15_t)0x8427, (q15_t)0x2050, (q15_t)0x8426, (q15_t)0x204a, (q15_t)0x8424, (q15_t)0x2044, (q15_t)0x8423, + (q15_t)0x203e, (q15_t)0x8421, (q15_t)0x2038, (q15_t)0x8420, (q15_t)0x2032, (q15_t)0x841e, (q15_t)0x202b, (q15_t)0x841c, + (q15_t)0x2025, (q15_t)0x841b, (q15_t)0x201f, (q15_t)0x8419, (q15_t)0x2019, (q15_t)0x8418, (q15_t)0x2013, (q15_t)0x8416, + (q15_t)0x200d, (q15_t)0x8415, (q15_t)0x2007, (q15_t)0x8413, (q15_t)0x2001, (q15_t)0x8411, (q15_t)0x1ffb, (q15_t)0x8410, + (q15_t)0x1ff5, (q15_t)0x840e, (q15_t)0x1fef, (q15_t)0x840d, (q15_t)0x1fe9, (q15_t)0x840b, (q15_t)0x1fe2, (q15_t)0x840a, + (q15_t)0x1fdc, (q15_t)0x8408, (q15_t)0x1fd6, (q15_t)0x8406, (q15_t)0x1fd0, (q15_t)0x8405, (q15_t)0x1fca, (q15_t)0x8403, + (q15_t)0x1fc4, (q15_t)0x8402, (q15_t)0x1fbe, (q15_t)0x8400, (q15_t)0x1fb8, (q15_t)0x83ff, (q15_t)0x1fb2, (q15_t)0x83fd, + (q15_t)0x1fac, (q15_t)0x83fb, (q15_t)0x1fa6, (q15_t)0x83fa, (q15_t)0x1f9f, (q15_t)0x83f8, (q15_t)0x1f99, (q15_t)0x83f7, + (q15_t)0x1f93, (q15_t)0x83f5, (q15_t)0x1f8d, (q15_t)0x83f4, (q15_t)0x1f87, (q15_t)0x83f2, (q15_t)0x1f81, (q15_t)0x83f1, + (q15_t)0x1f7b, (q15_t)0x83ef, (q15_t)0x1f75, (q15_t)0x83ee, (q15_t)0x1f6f, (q15_t)0x83ec, (q15_t)0x1f69, (q15_t)0x83ea, + (q15_t)0x1f63, (q15_t)0x83e9, (q15_t)0x1f5d, (q15_t)0x83e7, (q15_t)0x1f56, (q15_t)0x83e6, (q15_t)0x1f50, (q15_t)0x83e4, + (q15_t)0x1f4a, (q15_t)0x83e3, (q15_t)0x1f44, (q15_t)0x83e1, (q15_t)0x1f3e, (q15_t)0x83e0, (q15_t)0x1f38, (q15_t)0x83de, + (q15_t)0x1f32, (q15_t)0x83dd, (q15_t)0x1f2c, (q15_t)0x83db, (q15_t)0x1f26, (q15_t)0x83da, (q15_t)0x1f20, (q15_t)0x83d8, + (q15_t)0x1f19, (q15_t)0x83d7, (q15_t)0x1f13, (q15_t)0x83d5, (q15_t)0x1f0d, (q15_t)0x83d3, (q15_t)0x1f07, (q15_t)0x83d2, + (q15_t)0x1f01, (q15_t)0x83d0, (q15_t)0x1efb, (q15_t)0x83cf, (q15_t)0x1ef5, (q15_t)0x83cd, (q15_t)0x1eef, (q15_t)0x83cc, + (q15_t)0x1ee9, (q15_t)0x83ca, (q15_t)0x1ee3, (q15_t)0x83c9, (q15_t)0x1edd, (q15_t)0x83c7, (q15_t)0x1ed6, (q15_t)0x83c6, + (q15_t)0x1ed0, (q15_t)0x83c4, (q15_t)0x1eca, (q15_t)0x83c3, (q15_t)0x1ec4, (q15_t)0x83c1, (q15_t)0x1ebe, (q15_t)0x83c0, + (q15_t)0x1eb8, (q15_t)0x83be, (q15_t)0x1eb2, (q15_t)0x83bd, (q15_t)0x1eac, (q15_t)0x83bb, (q15_t)0x1ea6, (q15_t)0x83ba, + (q15_t)0x1ea0, (q15_t)0x83b8, (q15_t)0x1e99, (q15_t)0x83b7, (q15_t)0x1e93, (q15_t)0x83b5, (q15_t)0x1e8d, (q15_t)0x83b4, + (q15_t)0x1e87, (q15_t)0x83b2, (q15_t)0x1e81, (q15_t)0x83b1, (q15_t)0x1e7b, (q15_t)0x83af, (q15_t)0x1e75, (q15_t)0x83ae, + (q15_t)0x1e6f, (q15_t)0x83ac, (q15_t)0x1e69, (q15_t)0x83ab, (q15_t)0x1e62, (q15_t)0x83a9, (q15_t)0x1e5c, (q15_t)0x83a8, + (q15_t)0x1e56, (q15_t)0x83a6, (q15_t)0x1e50, (q15_t)0x83a5, (q15_t)0x1e4a, (q15_t)0x83a3, (q15_t)0x1e44, (q15_t)0x83a2, + (q15_t)0x1e3e, (q15_t)0x83a0, (q15_t)0x1e38, (q15_t)0x839f, (q15_t)0x1e32, (q15_t)0x839d, (q15_t)0x1e2c, (q15_t)0x839c, + (q15_t)0x1e25, (q15_t)0x839a, (q15_t)0x1e1f, (q15_t)0x8399, (q15_t)0x1e19, (q15_t)0x8397, (q15_t)0x1e13, (q15_t)0x8396, + (q15_t)0x1e0d, (q15_t)0x8394, (q15_t)0x1e07, (q15_t)0x8393, (q15_t)0x1e01, (q15_t)0x8392, (q15_t)0x1dfb, (q15_t)0x8390, + (q15_t)0x1df5, (q15_t)0x838f, (q15_t)0x1dee, (q15_t)0x838d, (q15_t)0x1de8, (q15_t)0x838c, (q15_t)0x1de2, (q15_t)0x838a, + (q15_t)0x1ddc, (q15_t)0x8389, (q15_t)0x1dd6, (q15_t)0x8387, (q15_t)0x1dd0, (q15_t)0x8386, (q15_t)0x1dca, (q15_t)0x8384, + (q15_t)0x1dc4, (q15_t)0x8383, (q15_t)0x1dbe, (q15_t)0x8381, (q15_t)0x1db7, (q15_t)0x8380, (q15_t)0x1db1, (q15_t)0x837e, + (q15_t)0x1dab, (q15_t)0x837d, (q15_t)0x1da5, (q15_t)0x837c, (q15_t)0x1d9f, (q15_t)0x837a, (q15_t)0x1d99, (q15_t)0x8379, + (q15_t)0x1d93, (q15_t)0x8377, (q15_t)0x1d8d, (q15_t)0x8376, (q15_t)0x1d87, (q15_t)0x8374, (q15_t)0x1d80, (q15_t)0x8373, + (q15_t)0x1d7a, (q15_t)0x8371, (q15_t)0x1d74, (q15_t)0x8370, (q15_t)0x1d6e, (q15_t)0x836f, (q15_t)0x1d68, (q15_t)0x836d, + (q15_t)0x1d62, (q15_t)0x836c, (q15_t)0x1d5c, (q15_t)0x836a, (q15_t)0x1d56, (q15_t)0x8369, (q15_t)0x1d50, (q15_t)0x8367, + (q15_t)0x1d49, (q15_t)0x8366, (q15_t)0x1d43, (q15_t)0x8364, (q15_t)0x1d3d, (q15_t)0x8363, (q15_t)0x1d37, (q15_t)0x8362, + (q15_t)0x1d31, (q15_t)0x8360, (q15_t)0x1d2b, (q15_t)0x835f, (q15_t)0x1d25, (q15_t)0x835d, (q15_t)0x1d1f, (q15_t)0x835c, + (q15_t)0x1d18, (q15_t)0x835a, (q15_t)0x1d12, (q15_t)0x8359, (q15_t)0x1d0c, (q15_t)0x8358, (q15_t)0x1d06, (q15_t)0x8356, + (q15_t)0x1d00, (q15_t)0x8355, (q15_t)0x1cfa, (q15_t)0x8353, (q15_t)0x1cf4, (q15_t)0x8352, (q15_t)0x1cee, (q15_t)0x8350, + (q15_t)0x1ce8, (q15_t)0x834f, (q15_t)0x1ce1, (q15_t)0x834e, (q15_t)0x1cdb, (q15_t)0x834c, (q15_t)0x1cd5, (q15_t)0x834b, + (q15_t)0x1ccf, (q15_t)0x8349, (q15_t)0x1cc9, (q15_t)0x8348, (q15_t)0x1cc3, (q15_t)0x8347, (q15_t)0x1cbd, (q15_t)0x8345, + (q15_t)0x1cb7, (q15_t)0x8344, (q15_t)0x1cb0, (q15_t)0x8342, (q15_t)0x1caa, (q15_t)0x8341, (q15_t)0x1ca4, (q15_t)0x833f, + (q15_t)0x1c9e, (q15_t)0x833e, (q15_t)0x1c98, (q15_t)0x833d, (q15_t)0x1c92, (q15_t)0x833b, (q15_t)0x1c8c, (q15_t)0x833a, + (q15_t)0x1c86, (q15_t)0x8338, (q15_t)0x1c7f, (q15_t)0x8337, (q15_t)0x1c79, (q15_t)0x8336, (q15_t)0x1c73, (q15_t)0x8334, + (q15_t)0x1c6d, (q15_t)0x8333, (q15_t)0x1c67, (q15_t)0x8331, (q15_t)0x1c61, (q15_t)0x8330, (q15_t)0x1c5b, (q15_t)0x832f, + (q15_t)0x1c55, (q15_t)0x832d, (q15_t)0x1c4e, (q15_t)0x832c, (q15_t)0x1c48, (q15_t)0x832b, (q15_t)0x1c42, (q15_t)0x8329, + (q15_t)0x1c3c, (q15_t)0x8328, (q15_t)0x1c36, (q15_t)0x8326, (q15_t)0x1c30, (q15_t)0x8325, (q15_t)0x1c2a, (q15_t)0x8324, + (q15_t)0x1c24, (q15_t)0x8322, (q15_t)0x1c1d, (q15_t)0x8321, (q15_t)0x1c17, (q15_t)0x831f, (q15_t)0x1c11, (q15_t)0x831e, + (q15_t)0x1c0b, (q15_t)0x831d, (q15_t)0x1c05, (q15_t)0x831b, (q15_t)0x1bff, (q15_t)0x831a, (q15_t)0x1bf9, (q15_t)0x8319, + (q15_t)0x1bf2, (q15_t)0x8317, (q15_t)0x1bec, (q15_t)0x8316, (q15_t)0x1be6, (q15_t)0x8314, (q15_t)0x1be0, (q15_t)0x8313, + (q15_t)0x1bda, (q15_t)0x8312, (q15_t)0x1bd4, (q15_t)0x8310, (q15_t)0x1bce, (q15_t)0x830f, (q15_t)0x1bc8, (q15_t)0x830e, + (q15_t)0x1bc1, (q15_t)0x830c, (q15_t)0x1bbb, (q15_t)0x830b, (q15_t)0x1bb5, (q15_t)0x830a, (q15_t)0x1baf, (q15_t)0x8308, + (q15_t)0x1ba9, (q15_t)0x8307, (q15_t)0x1ba3, (q15_t)0x8305, (q15_t)0x1b9d, (q15_t)0x8304, (q15_t)0x1b96, (q15_t)0x8303, + (q15_t)0x1b90, (q15_t)0x8301, (q15_t)0x1b8a, (q15_t)0x8300, (q15_t)0x1b84, (q15_t)0x82ff, (q15_t)0x1b7e, (q15_t)0x82fd, + (q15_t)0x1b78, (q15_t)0x82fc, (q15_t)0x1b72, (q15_t)0x82fb, (q15_t)0x1b6c, (q15_t)0x82f9, (q15_t)0x1b65, (q15_t)0x82f8, + (q15_t)0x1b5f, (q15_t)0x82f7, (q15_t)0x1b59, (q15_t)0x82f5, (q15_t)0x1b53, (q15_t)0x82f4, (q15_t)0x1b4d, (q15_t)0x82f3, + (q15_t)0x1b47, (q15_t)0x82f1, (q15_t)0x1b41, (q15_t)0x82f0, (q15_t)0x1b3a, (q15_t)0x82ef, (q15_t)0x1b34, (q15_t)0x82ed, + (q15_t)0x1b2e, (q15_t)0x82ec, (q15_t)0x1b28, (q15_t)0x82eb, (q15_t)0x1b22, (q15_t)0x82e9, (q15_t)0x1b1c, (q15_t)0x82e8, + (q15_t)0x1b16, (q15_t)0x82e7, (q15_t)0x1b0f, (q15_t)0x82e5, (q15_t)0x1b09, (q15_t)0x82e4, (q15_t)0x1b03, (q15_t)0x82e3, + (q15_t)0x1afd, (q15_t)0x82e1, (q15_t)0x1af7, (q15_t)0x82e0, (q15_t)0x1af1, (q15_t)0x82df, (q15_t)0x1aeb, (q15_t)0x82dd, + (q15_t)0x1ae4, (q15_t)0x82dc, (q15_t)0x1ade, (q15_t)0x82db, (q15_t)0x1ad8, (q15_t)0x82d9, (q15_t)0x1ad2, (q15_t)0x82d8, + (q15_t)0x1acc, (q15_t)0x82d7, (q15_t)0x1ac6, (q15_t)0x82d5, (q15_t)0x1ac0, (q15_t)0x82d4, (q15_t)0x1ab9, (q15_t)0x82d3, + (q15_t)0x1ab3, (q15_t)0x82d1, (q15_t)0x1aad, (q15_t)0x82d0, (q15_t)0x1aa7, (q15_t)0x82cf, (q15_t)0x1aa1, (q15_t)0x82ce, + (q15_t)0x1a9b, (q15_t)0x82cc, (q15_t)0x1a95, (q15_t)0x82cb, (q15_t)0x1a8e, (q15_t)0x82ca, (q15_t)0x1a88, (q15_t)0x82c8, + (q15_t)0x1a82, (q15_t)0x82c7, (q15_t)0x1a7c, (q15_t)0x82c6, (q15_t)0x1a76, (q15_t)0x82c4, (q15_t)0x1a70, (q15_t)0x82c3, + (q15_t)0x1a6a, (q15_t)0x82c2, (q15_t)0x1a63, (q15_t)0x82c1, (q15_t)0x1a5d, (q15_t)0x82bf, (q15_t)0x1a57, (q15_t)0x82be, + (q15_t)0x1a51, (q15_t)0x82bd, (q15_t)0x1a4b, (q15_t)0x82bb, (q15_t)0x1a45, (q15_t)0x82ba, (q15_t)0x1a3e, (q15_t)0x82b9, + (q15_t)0x1a38, (q15_t)0x82b7, (q15_t)0x1a32, (q15_t)0x82b6, (q15_t)0x1a2c, (q15_t)0x82b5, (q15_t)0x1a26, (q15_t)0x82b4, + (q15_t)0x1a20, (q15_t)0x82b2, (q15_t)0x1a1a, (q15_t)0x82b1, (q15_t)0x1a13, (q15_t)0x82b0, (q15_t)0x1a0d, (q15_t)0x82ae, + (q15_t)0x1a07, (q15_t)0x82ad, (q15_t)0x1a01, (q15_t)0x82ac, (q15_t)0x19fb, (q15_t)0x82ab, (q15_t)0x19f5, (q15_t)0x82a9, + (q15_t)0x19ef, (q15_t)0x82a8, (q15_t)0x19e8, (q15_t)0x82a7, (q15_t)0x19e2, (q15_t)0x82a6, (q15_t)0x19dc, (q15_t)0x82a4, + (q15_t)0x19d6, (q15_t)0x82a3, (q15_t)0x19d0, (q15_t)0x82a2, (q15_t)0x19ca, (q15_t)0x82a0, (q15_t)0x19c3, (q15_t)0x829f, + (q15_t)0x19bd, (q15_t)0x829e, (q15_t)0x19b7, (q15_t)0x829d, (q15_t)0x19b1, (q15_t)0x829b, (q15_t)0x19ab, (q15_t)0x829a, + (q15_t)0x19a5, (q15_t)0x8299, (q15_t)0x199f, (q15_t)0x8298, (q15_t)0x1998, (q15_t)0x8296, (q15_t)0x1992, (q15_t)0x8295, + (q15_t)0x198c, (q15_t)0x8294, (q15_t)0x1986, (q15_t)0x8293, (q15_t)0x1980, (q15_t)0x8291, (q15_t)0x197a, (q15_t)0x8290, + (q15_t)0x1973, (q15_t)0x828f, (q15_t)0x196d, (q15_t)0x828e, (q15_t)0x1967, (q15_t)0x828c, (q15_t)0x1961, (q15_t)0x828b, + (q15_t)0x195b, (q15_t)0x828a, (q15_t)0x1955, (q15_t)0x8289, (q15_t)0x194e, (q15_t)0x8287, (q15_t)0x1948, (q15_t)0x8286, + (q15_t)0x1942, (q15_t)0x8285, (q15_t)0x193c, (q15_t)0x8284, (q15_t)0x1936, (q15_t)0x8282, (q15_t)0x1930, (q15_t)0x8281, + (q15_t)0x192a, (q15_t)0x8280, (q15_t)0x1923, (q15_t)0x827f, (q15_t)0x191d, (q15_t)0x827e, (q15_t)0x1917, (q15_t)0x827c, + (q15_t)0x1911, (q15_t)0x827b, (q15_t)0x190b, (q15_t)0x827a, (q15_t)0x1905, (q15_t)0x8279, (q15_t)0x18fe, (q15_t)0x8277, + (q15_t)0x18f8, (q15_t)0x8276, (q15_t)0x18f2, (q15_t)0x8275, (q15_t)0x18ec, (q15_t)0x8274, (q15_t)0x18e6, (q15_t)0x8272, + (q15_t)0x18e0, (q15_t)0x8271, (q15_t)0x18d9, (q15_t)0x8270, (q15_t)0x18d3, (q15_t)0x826f, (q15_t)0x18cd, (q15_t)0x826e, + (q15_t)0x18c7, (q15_t)0x826c, (q15_t)0x18c1, (q15_t)0x826b, (q15_t)0x18bb, (q15_t)0x826a, (q15_t)0x18b4, (q15_t)0x8269, + (q15_t)0x18ae, (q15_t)0x8268, (q15_t)0x18a8, (q15_t)0x8266, (q15_t)0x18a2, (q15_t)0x8265, (q15_t)0x189c, (q15_t)0x8264, + (q15_t)0x1896, (q15_t)0x8263, (q15_t)0x188f, (q15_t)0x8261, (q15_t)0x1889, (q15_t)0x8260, (q15_t)0x1883, (q15_t)0x825f, + (q15_t)0x187d, (q15_t)0x825e, (q15_t)0x1877, (q15_t)0x825d, (q15_t)0x1871, (q15_t)0x825b, (q15_t)0x186a, (q15_t)0x825a, + (q15_t)0x1864, (q15_t)0x8259, (q15_t)0x185e, (q15_t)0x8258, (q15_t)0x1858, (q15_t)0x8257, (q15_t)0x1852, (q15_t)0x8255, + (q15_t)0x184c, (q15_t)0x8254, (q15_t)0x1845, (q15_t)0x8253, (q15_t)0x183f, (q15_t)0x8252, (q15_t)0x1839, (q15_t)0x8251, + (q15_t)0x1833, (q15_t)0x8250, (q15_t)0x182d, (q15_t)0x824e, (q15_t)0x1827, (q15_t)0x824d, (q15_t)0x1820, (q15_t)0x824c, + (q15_t)0x181a, (q15_t)0x824b, (q15_t)0x1814, (q15_t)0x824a, (q15_t)0x180e, (q15_t)0x8248, (q15_t)0x1808, (q15_t)0x8247, + (q15_t)0x1802, (q15_t)0x8246, (q15_t)0x17fb, (q15_t)0x8245, (q15_t)0x17f5, (q15_t)0x8244, (q15_t)0x17ef, (q15_t)0x8243, + (q15_t)0x17e9, (q15_t)0x8241, (q15_t)0x17e3, (q15_t)0x8240, (q15_t)0x17dd, (q15_t)0x823f, (q15_t)0x17d6, (q15_t)0x823e, + (q15_t)0x17d0, (q15_t)0x823d, (q15_t)0x17ca, (q15_t)0x823b, (q15_t)0x17c4, (q15_t)0x823a, (q15_t)0x17be, (q15_t)0x8239, + (q15_t)0x17b7, (q15_t)0x8238, (q15_t)0x17b1, (q15_t)0x8237, (q15_t)0x17ab, (q15_t)0x8236, (q15_t)0x17a5, (q15_t)0x8234, + (q15_t)0x179f, (q15_t)0x8233, (q15_t)0x1799, (q15_t)0x8232, (q15_t)0x1792, (q15_t)0x8231, (q15_t)0x178c, (q15_t)0x8230, + (q15_t)0x1786, (q15_t)0x822f, (q15_t)0x1780, (q15_t)0x822e, (q15_t)0x177a, (q15_t)0x822c, (q15_t)0x1774, (q15_t)0x822b, + (q15_t)0x176d, (q15_t)0x822a, (q15_t)0x1767, (q15_t)0x8229, (q15_t)0x1761, (q15_t)0x8228, (q15_t)0x175b, (q15_t)0x8227, + (q15_t)0x1755, (q15_t)0x8226, (q15_t)0x174e, (q15_t)0x8224, (q15_t)0x1748, (q15_t)0x8223, (q15_t)0x1742, (q15_t)0x8222, + (q15_t)0x173c, (q15_t)0x8221, (q15_t)0x1736, (q15_t)0x8220, (q15_t)0x1730, (q15_t)0x821f, (q15_t)0x1729, (q15_t)0x821e, + (q15_t)0x1723, (q15_t)0x821c, (q15_t)0x171d, (q15_t)0x821b, (q15_t)0x1717, (q15_t)0x821a, (q15_t)0x1711, (q15_t)0x8219, + (q15_t)0x170a, (q15_t)0x8218, (q15_t)0x1704, (q15_t)0x8217, (q15_t)0x16fe, (q15_t)0x8216, (q15_t)0x16f8, (q15_t)0x8214, + (q15_t)0x16f2, (q15_t)0x8213, (q15_t)0x16ec, (q15_t)0x8212, (q15_t)0x16e5, (q15_t)0x8211, (q15_t)0x16df, (q15_t)0x8210, + (q15_t)0x16d9, (q15_t)0x820f, (q15_t)0x16d3, (q15_t)0x820e, (q15_t)0x16cd, (q15_t)0x820d, (q15_t)0x16c6, (q15_t)0x820b, + (q15_t)0x16c0, (q15_t)0x820a, (q15_t)0x16ba, (q15_t)0x8209, (q15_t)0x16b4, (q15_t)0x8208, (q15_t)0x16ae, (q15_t)0x8207, + (q15_t)0x16a8, (q15_t)0x8206, (q15_t)0x16a1, (q15_t)0x8205, (q15_t)0x169b, (q15_t)0x8204, (q15_t)0x1695, (q15_t)0x8203, + (q15_t)0x168f, (q15_t)0x8201, (q15_t)0x1689, (q15_t)0x8200, (q15_t)0x1682, (q15_t)0x81ff, (q15_t)0x167c, (q15_t)0x81fe, + (q15_t)0x1676, (q15_t)0x81fd, (q15_t)0x1670, (q15_t)0x81fc, (q15_t)0x166a, (q15_t)0x81fb, (q15_t)0x1664, (q15_t)0x81fa, + (q15_t)0x165d, (q15_t)0x81f9, (q15_t)0x1657, (q15_t)0x81f8, (q15_t)0x1651, (q15_t)0x81f6, (q15_t)0x164b, (q15_t)0x81f5, + (q15_t)0x1645, (q15_t)0x81f4, (q15_t)0x163e, (q15_t)0x81f3, (q15_t)0x1638, (q15_t)0x81f2, (q15_t)0x1632, (q15_t)0x81f1, + (q15_t)0x162c, (q15_t)0x81f0, (q15_t)0x1626, (q15_t)0x81ef, (q15_t)0x161f, (q15_t)0x81ee, (q15_t)0x1619, (q15_t)0x81ed, + (q15_t)0x1613, (q15_t)0x81ec, (q15_t)0x160d, (q15_t)0x81ea, (q15_t)0x1607, (q15_t)0x81e9, (q15_t)0x1601, (q15_t)0x81e8, + (q15_t)0x15fa, (q15_t)0x81e7, (q15_t)0x15f4, (q15_t)0x81e6, (q15_t)0x15ee, (q15_t)0x81e5, (q15_t)0x15e8, (q15_t)0x81e4, + (q15_t)0x15e2, (q15_t)0x81e3, (q15_t)0x15db, (q15_t)0x81e2, (q15_t)0x15d5, (q15_t)0x81e1, (q15_t)0x15cf, (q15_t)0x81e0, + (q15_t)0x15c9, (q15_t)0x81df, (q15_t)0x15c3, (q15_t)0x81de, (q15_t)0x15bc, (q15_t)0x81dc, (q15_t)0x15b6, (q15_t)0x81db, + (q15_t)0x15b0, (q15_t)0x81da, (q15_t)0x15aa, (q15_t)0x81d9, (q15_t)0x15a4, (q15_t)0x81d8, (q15_t)0x159d, (q15_t)0x81d7, + (q15_t)0x1597, (q15_t)0x81d6, (q15_t)0x1591, (q15_t)0x81d5, (q15_t)0x158b, (q15_t)0x81d4, (q15_t)0x1585, (q15_t)0x81d3, + (q15_t)0x157f, (q15_t)0x81d2, (q15_t)0x1578, (q15_t)0x81d1, (q15_t)0x1572, (q15_t)0x81d0, (q15_t)0x156c, (q15_t)0x81cf, + (q15_t)0x1566, (q15_t)0x81ce, (q15_t)0x1560, (q15_t)0x81cd, (q15_t)0x1559, (q15_t)0x81cc, (q15_t)0x1553, (q15_t)0x81cb, + (q15_t)0x154d, (q15_t)0x81c9, (q15_t)0x1547, (q15_t)0x81c8, (q15_t)0x1541, (q15_t)0x81c7, (q15_t)0x153a, (q15_t)0x81c6, + (q15_t)0x1534, (q15_t)0x81c5, (q15_t)0x152e, (q15_t)0x81c4, (q15_t)0x1528, (q15_t)0x81c3, (q15_t)0x1522, (q15_t)0x81c2, + (q15_t)0x151b, (q15_t)0x81c1, (q15_t)0x1515, (q15_t)0x81c0, (q15_t)0x150f, (q15_t)0x81bf, (q15_t)0x1509, (q15_t)0x81be, + (q15_t)0x1503, (q15_t)0x81bd, (q15_t)0x14fc, (q15_t)0x81bc, (q15_t)0x14f6, (q15_t)0x81bb, (q15_t)0x14f0, (q15_t)0x81ba, + (q15_t)0x14ea, (q15_t)0x81b9, (q15_t)0x14e4, (q15_t)0x81b8, (q15_t)0x14dd, (q15_t)0x81b7, (q15_t)0x14d7, (q15_t)0x81b6, + (q15_t)0x14d1, (q15_t)0x81b5, (q15_t)0x14cb, (q15_t)0x81b4, (q15_t)0x14c5, (q15_t)0x81b3, (q15_t)0x14be, (q15_t)0x81b2, + (q15_t)0x14b8, (q15_t)0x81b1, (q15_t)0x14b2, (q15_t)0x81b0, (q15_t)0x14ac, (q15_t)0x81af, (q15_t)0x14a6, (q15_t)0x81ae, + (q15_t)0x149f, (q15_t)0x81ad, (q15_t)0x1499, (q15_t)0x81ac, (q15_t)0x1493, (q15_t)0x81ab, (q15_t)0x148d, (q15_t)0x81aa, + (q15_t)0x1487, (q15_t)0x81a9, (q15_t)0x1480, (q15_t)0x81a8, (q15_t)0x147a, (q15_t)0x81a7, (q15_t)0x1474, (q15_t)0x81a6, + (q15_t)0x146e, (q15_t)0x81a5, (q15_t)0x1468, (q15_t)0x81a4, (q15_t)0x1461, (q15_t)0x81a3, (q15_t)0x145b, (q15_t)0x81a2, + (q15_t)0x1455, (q15_t)0x81a1, (q15_t)0x144f, (q15_t)0x81a0, (q15_t)0x1449, (q15_t)0x819f, (q15_t)0x1442, (q15_t)0x819e, + (q15_t)0x143c, (q15_t)0x819d, (q15_t)0x1436, (q15_t)0x819c, (q15_t)0x1430, (q15_t)0x819b, (q15_t)0x142a, (q15_t)0x819a, + (q15_t)0x1423, (q15_t)0x8199, (q15_t)0x141d, (q15_t)0x8198, (q15_t)0x1417, (q15_t)0x8197, (q15_t)0x1411, (q15_t)0x8196, + (q15_t)0x140b, (q15_t)0x8195, (q15_t)0x1404, (q15_t)0x8194, (q15_t)0x13fe, (q15_t)0x8193, (q15_t)0x13f8, (q15_t)0x8192, + (q15_t)0x13f2, (q15_t)0x8191, (q15_t)0x13eb, (q15_t)0x8190, (q15_t)0x13e5, (q15_t)0x818f, (q15_t)0x13df, (q15_t)0x818e, + (q15_t)0x13d9, (q15_t)0x818d, (q15_t)0x13d3, (q15_t)0x818c, (q15_t)0x13cc, (q15_t)0x818b, (q15_t)0x13c6, (q15_t)0x818a, + (q15_t)0x13c0, (q15_t)0x8189, (q15_t)0x13ba, (q15_t)0x8188, (q15_t)0x13b4, (q15_t)0x8187, (q15_t)0x13ad, (q15_t)0x8186, + (q15_t)0x13a7, (q15_t)0x8185, (q15_t)0x13a1, (q15_t)0x8184, (q15_t)0x139b, (q15_t)0x8183, (q15_t)0x1395, (q15_t)0x8182, + (q15_t)0x138e, (q15_t)0x8181, (q15_t)0x1388, (q15_t)0x8180, (q15_t)0x1382, (q15_t)0x817f, (q15_t)0x137c, (q15_t)0x817e, + (q15_t)0x1376, (q15_t)0x817d, (q15_t)0x136f, (q15_t)0x817c, (q15_t)0x1369, (q15_t)0x817c, (q15_t)0x1363, (q15_t)0x817b, + (q15_t)0x135d, (q15_t)0x817a, (q15_t)0x1356, (q15_t)0x8179, (q15_t)0x1350, (q15_t)0x8178, (q15_t)0x134a, (q15_t)0x8177, + (q15_t)0x1344, (q15_t)0x8176, (q15_t)0x133e, (q15_t)0x8175, (q15_t)0x1337, (q15_t)0x8174, (q15_t)0x1331, (q15_t)0x8173, + (q15_t)0x132b, (q15_t)0x8172, (q15_t)0x1325, (q15_t)0x8171, (q15_t)0x131f, (q15_t)0x8170, (q15_t)0x1318, (q15_t)0x816f, + (q15_t)0x1312, (q15_t)0x816e, (q15_t)0x130c, (q15_t)0x816d, (q15_t)0x1306, (q15_t)0x816c, (q15_t)0x12ff, (q15_t)0x816c, + (q15_t)0x12f9, (q15_t)0x816b, (q15_t)0x12f3, (q15_t)0x816a, (q15_t)0x12ed, (q15_t)0x8169, (q15_t)0x12e7, (q15_t)0x8168, + (q15_t)0x12e0, (q15_t)0x8167, (q15_t)0x12da, (q15_t)0x8166, (q15_t)0x12d4, (q15_t)0x8165, (q15_t)0x12ce, (q15_t)0x8164, + (q15_t)0x12c8, (q15_t)0x8163, (q15_t)0x12c1, (q15_t)0x8162, (q15_t)0x12bb, (q15_t)0x8161, (q15_t)0x12b5, (q15_t)0x8160, + (q15_t)0x12af, (q15_t)0x815f, (q15_t)0x12a8, (q15_t)0x815f, (q15_t)0x12a2, (q15_t)0x815e, (q15_t)0x129c, (q15_t)0x815d, + (q15_t)0x1296, (q15_t)0x815c, (q15_t)0x1290, (q15_t)0x815b, (q15_t)0x1289, (q15_t)0x815a, (q15_t)0x1283, (q15_t)0x8159, + (q15_t)0x127d, (q15_t)0x8158, (q15_t)0x1277, (q15_t)0x8157, (q15_t)0x1271, (q15_t)0x8156, (q15_t)0x126a, (q15_t)0x8155, + (q15_t)0x1264, (q15_t)0x8155, (q15_t)0x125e, (q15_t)0x8154, (q15_t)0x1258, (q15_t)0x8153, (q15_t)0x1251, (q15_t)0x8152, + (q15_t)0x124b, (q15_t)0x8151, (q15_t)0x1245, (q15_t)0x8150, (q15_t)0x123f, (q15_t)0x814f, (q15_t)0x1239, (q15_t)0x814e, + (q15_t)0x1232, (q15_t)0x814d, (q15_t)0x122c, (q15_t)0x814c, (q15_t)0x1226, (q15_t)0x814c, (q15_t)0x1220, (q15_t)0x814b, + (q15_t)0x1219, (q15_t)0x814a, (q15_t)0x1213, (q15_t)0x8149, (q15_t)0x120d, (q15_t)0x8148, (q15_t)0x1207, (q15_t)0x8147, + (q15_t)0x1201, (q15_t)0x8146, (q15_t)0x11fa, (q15_t)0x8145, (q15_t)0x11f4, (q15_t)0x8145, (q15_t)0x11ee, (q15_t)0x8144, + (q15_t)0x11e8, (q15_t)0x8143, (q15_t)0x11e1, (q15_t)0x8142, (q15_t)0x11db, (q15_t)0x8141, (q15_t)0x11d5, (q15_t)0x8140, + (q15_t)0x11cf, (q15_t)0x813f, (q15_t)0x11c9, (q15_t)0x813e, (q15_t)0x11c2, (q15_t)0x813d, (q15_t)0x11bc, (q15_t)0x813d, + (q15_t)0x11b6, (q15_t)0x813c, (q15_t)0x11b0, (q15_t)0x813b, (q15_t)0x11a9, (q15_t)0x813a, (q15_t)0x11a3, (q15_t)0x8139, + (q15_t)0x119d, (q15_t)0x8138, (q15_t)0x1197, (q15_t)0x8137, (q15_t)0x1191, (q15_t)0x8137, (q15_t)0x118a, (q15_t)0x8136, + (q15_t)0x1184, (q15_t)0x8135, (q15_t)0x117e, (q15_t)0x8134, (q15_t)0x1178, (q15_t)0x8133, (q15_t)0x1171, (q15_t)0x8132, + (q15_t)0x116b, (q15_t)0x8131, (q15_t)0x1165, (q15_t)0x8131, (q15_t)0x115f, (q15_t)0x8130, (q15_t)0x1159, (q15_t)0x812f, + (q15_t)0x1152, (q15_t)0x812e, (q15_t)0x114c, (q15_t)0x812d, (q15_t)0x1146, (q15_t)0x812c, (q15_t)0x1140, (q15_t)0x812b, + (q15_t)0x1139, (q15_t)0x812b, (q15_t)0x1133, (q15_t)0x812a, (q15_t)0x112d, (q15_t)0x8129, (q15_t)0x1127, (q15_t)0x8128, + (q15_t)0x1121, (q15_t)0x8127, (q15_t)0x111a, (q15_t)0x8126, (q15_t)0x1114, (q15_t)0x8126, (q15_t)0x110e, (q15_t)0x8125, + (q15_t)0x1108, (q15_t)0x8124, (q15_t)0x1101, (q15_t)0x8123, (q15_t)0x10fb, (q15_t)0x8122, (q15_t)0x10f5, (q15_t)0x8121, + (q15_t)0x10ef, (q15_t)0x8121, (q15_t)0x10e8, (q15_t)0x8120, (q15_t)0x10e2, (q15_t)0x811f, (q15_t)0x10dc, (q15_t)0x811e, + (q15_t)0x10d6, (q15_t)0x811d, (q15_t)0x10d0, (q15_t)0x811c, (q15_t)0x10c9, (q15_t)0x811c, (q15_t)0x10c3, (q15_t)0x811b, + (q15_t)0x10bd, (q15_t)0x811a, (q15_t)0x10b7, (q15_t)0x8119, (q15_t)0x10b0, (q15_t)0x8118, (q15_t)0x10aa, (q15_t)0x8117, + (q15_t)0x10a4, (q15_t)0x8117, (q15_t)0x109e, (q15_t)0x8116, (q15_t)0x1098, (q15_t)0x8115, (q15_t)0x1091, (q15_t)0x8114, + (q15_t)0x108b, (q15_t)0x8113, (q15_t)0x1085, (q15_t)0x8113, (q15_t)0x107f, (q15_t)0x8112, (q15_t)0x1078, (q15_t)0x8111, + (q15_t)0x1072, (q15_t)0x8110, (q15_t)0x106c, (q15_t)0x810f, (q15_t)0x1066, (q15_t)0x810f, (q15_t)0x105f, (q15_t)0x810e, + (q15_t)0x1059, (q15_t)0x810d, (q15_t)0x1053, (q15_t)0x810c, (q15_t)0x104d, (q15_t)0x810b, (q15_t)0x1047, (q15_t)0x810b, + (q15_t)0x1040, (q15_t)0x810a, (q15_t)0x103a, (q15_t)0x8109, (q15_t)0x1034, (q15_t)0x8108, (q15_t)0x102e, (q15_t)0x8107, + (q15_t)0x1027, (q15_t)0x8107, (q15_t)0x1021, (q15_t)0x8106, (q15_t)0x101b, (q15_t)0x8105, (q15_t)0x1015, (q15_t)0x8104, + (q15_t)0x100e, (q15_t)0x8103, (q15_t)0x1008, (q15_t)0x8103, (q15_t)0x1002, (q15_t)0x8102, (q15_t)0xffc, (q15_t)0x8101, + (q15_t)0xff5, (q15_t)0x8100, (q15_t)0xfef, (q15_t)0x80ff, (q15_t)0xfe9, (q15_t)0x80ff, (q15_t)0xfe3, (q15_t)0x80fe, + (q15_t)0xfdd, (q15_t)0x80fd, (q15_t)0xfd6, (q15_t)0x80fc, (q15_t)0xfd0, (q15_t)0x80fc, (q15_t)0xfca, (q15_t)0x80fb, + (q15_t)0xfc4, (q15_t)0x80fa, (q15_t)0xfbd, (q15_t)0x80f9, (q15_t)0xfb7, (q15_t)0x80f8, (q15_t)0xfb1, (q15_t)0x80f8, + (q15_t)0xfab, (q15_t)0x80f7, (q15_t)0xfa4, (q15_t)0x80f6, (q15_t)0xf9e, (q15_t)0x80f5, (q15_t)0xf98, (q15_t)0x80f5, + (q15_t)0xf92, (q15_t)0x80f4, (q15_t)0xf8b, (q15_t)0x80f3, (q15_t)0xf85, (q15_t)0x80f2, (q15_t)0xf7f, (q15_t)0x80f2, + (q15_t)0xf79, (q15_t)0x80f1, (q15_t)0xf73, (q15_t)0x80f0, (q15_t)0xf6c, (q15_t)0x80ef, (q15_t)0xf66, (q15_t)0x80ef, + (q15_t)0xf60, (q15_t)0x80ee, (q15_t)0xf5a, (q15_t)0x80ed, (q15_t)0xf53, (q15_t)0x80ec, (q15_t)0xf4d, (q15_t)0x80ec, + (q15_t)0xf47, (q15_t)0x80eb, (q15_t)0xf41, (q15_t)0x80ea, (q15_t)0xf3a, (q15_t)0x80e9, (q15_t)0xf34, (q15_t)0x80e9, + (q15_t)0xf2e, (q15_t)0x80e8, (q15_t)0xf28, (q15_t)0x80e7, (q15_t)0xf21, (q15_t)0x80e6, (q15_t)0xf1b, (q15_t)0x80e6, + (q15_t)0xf15, (q15_t)0x80e5, (q15_t)0xf0f, (q15_t)0x80e4, (q15_t)0xf08, (q15_t)0x80e3, (q15_t)0xf02, (q15_t)0x80e3, + (q15_t)0xefc, (q15_t)0x80e2, (q15_t)0xef6, (q15_t)0x80e1, (q15_t)0xef0, (q15_t)0x80e0, (q15_t)0xee9, (q15_t)0x80e0, + (q15_t)0xee3, (q15_t)0x80df, (q15_t)0xedd, (q15_t)0x80de, (q15_t)0xed7, (q15_t)0x80dd, (q15_t)0xed0, (q15_t)0x80dd, + (q15_t)0xeca, (q15_t)0x80dc, (q15_t)0xec4, (q15_t)0x80db, (q15_t)0xebe, (q15_t)0x80db, (q15_t)0xeb7, (q15_t)0x80da, + (q15_t)0xeb1, (q15_t)0x80d9, (q15_t)0xeab, (q15_t)0x80d8, (q15_t)0xea5, (q15_t)0x80d8, (q15_t)0xe9e, (q15_t)0x80d7, + (q15_t)0xe98, (q15_t)0x80d6, (q15_t)0xe92, (q15_t)0x80d6, (q15_t)0xe8c, (q15_t)0x80d5, (q15_t)0xe85, (q15_t)0x80d4, + (q15_t)0xe7f, (q15_t)0x80d3, (q15_t)0xe79, (q15_t)0x80d3, (q15_t)0xe73, (q15_t)0x80d2, (q15_t)0xe6c, (q15_t)0x80d1, + (q15_t)0xe66, (q15_t)0x80d1, (q15_t)0xe60, (q15_t)0x80d0, (q15_t)0xe5a, (q15_t)0x80cf, (q15_t)0xe53, (q15_t)0x80ce, + (q15_t)0xe4d, (q15_t)0x80ce, (q15_t)0xe47, (q15_t)0x80cd, (q15_t)0xe41, (q15_t)0x80cc, (q15_t)0xe3a, (q15_t)0x80cc, + (q15_t)0xe34, (q15_t)0x80cb, (q15_t)0xe2e, (q15_t)0x80ca, (q15_t)0xe28, (q15_t)0x80ca, (q15_t)0xe22, (q15_t)0x80c9, + (q15_t)0xe1b, (q15_t)0x80c8, (q15_t)0xe15, (q15_t)0x80c7, (q15_t)0xe0f, (q15_t)0x80c7, (q15_t)0xe09, (q15_t)0x80c6, + (q15_t)0xe02, (q15_t)0x80c5, (q15_t)0xdfc, (q15_t)0x80c5, (q15_t)0xdf6, (q15_t)0x80c4, (q15_t)0xdf0, (q15_t)0x80c3, + (q15_t)0xde9, (q15_t)0x80c3, (q15_t)0xde3, (q15_t)0x80c2, (q15_t)0xddd, (q15_t)0x80c1, (q15_t)0xdd7, (q15_t)0x80c1, + (q15_t)0xdd0, (q15_t)0x80c0, (q15_t)0xdca, (q15_t)0x80bf, (q15_t)0xdc4, (q15_t)0x80bf, (q15_t)0xdbe, (q15_t)0x80be, + (q15_t)0xdb7, (q15_t)0x80bd, (q15_t)0xdb1, (q15_t)0x80bd, (q15_t)0xdab, (q15_t)0x80bc, (q15_t)0xda5, (q15_t)0x80bb, + (q15_t)0xd9e, (q15_t)0x80bb, (q15_t)0xd98, (q15_t)0x80ba, (q15_t)0xd92, (q15_t)0x80b9, (q15_t)0xd8c, (q15_t)0x80b9, + (q15_t)0xd85, (q15_t)0x80b8, (q15_t)0xd7f, (q15_t)0x80b7, (q15_t)0xd79, (q15_t)0x80b7, (q15_t)0xd73, (q15_t)0x80b6, + (q15_t)0xd6c, (q15_t)0x80b5, (q15_t)0xd66, (q15_t)0x80b5, (q15_t)0xd60, (q15_t)0x80b4, (q15_t)0xd5a, (q15_t)0x80b3, + (q15_t)0xd53, (q15_t)0x80b3, (q15_t)0xd4d, (q15_t)0x80b2, (q15_t)0xd47, (q15_t)0x80b1, (q15_t)0xd41, (q15_t)0x80b1, + (q15_t)0xd3a, (q15_t)0x80b0, (q15_t)0xd34, (q15_t)0x80af, (q15_t)0xd2e, (q15_t)0x80af, (q15_t)0xd28, (q15_t)0x80ae, + (q15_t)0xd21, (q15_t)0x80ad, (q15_t)0xd1b, (q15_t)0x80ad, (q15_t)0xd15, (q15_t)0x80ac, (q15_t)0xd0f, (q15_t)0x80ab, + (q15_t)0xd08, (q15_t)0x80ab, (q15_t)0xd02, (q15_t)0x80aa, (q15_t)0xcfc, (q15_t)0x80aa, (q15_t)0xcf6, (q15_t)0x80a9, + (q15_t)0xcef, (q15_t)0x80a8, (q15_t)0xce9, (q15_t)0x80a8, (q15_t)0xce3, (q15_t)0x80a7, (q15_t)0xcdd, (q15_t)0x80a6, + (q15_t)0xcd6, (q15_t)0x80a6, (q15_t)0xcd0, (q15_t)0x80a5, (q15_t)0xcca, (q15_t)0x80a5, (q15_t)0xcc4, (q15_t)0x80a4, + (q15_t)0xcbd, (q15_t)0x80a3, (q15_t)0xcb7, (q15_t)0x80a3, (q15_t)0xcb1, (q15_t)0x80a2, (q15_t)0xcab, (q15_t)0x80a1, + (q15_t)0xca4, (q15_t)0x80a1, (q15_t)0xc9e, (q15_t)0x80a0, (q15_t)0xc98, (q15_t)0x80a0, (q15_t)0xc92, (q15_t)0x809f, + (q15_t)0xc8b, (q15_t)0x809e, (q15_t)0xc85, (q15_t)0x809e, (q15_t)0xc7f, (q15_t)0x809d, (q15_t)0xc79, (q15_t)0x809c, + (q15_t)0xc72, (q15_t)0x809c, (q15_t)0xc6c, (q15_t)0x809b, (q15_t)0xc66, (q15_t)0x809b, (q15_t)0xc60, (q15_t)0x809a, + (q15_t)0xc59, (q15_t)0x8099, (q15_t)0xc53, (q15_t)0x8099, (q15_t)0xc4d, (q15_t)0x8098, (q15_t)0xc47, (q15_t)0x8098, + (q15_t)0xc40, (q15_t)0x8097, (q15_t)0xc3a, (q15_t)0x8096, (q15_t)0xc34, (q15_t)0x8096, (q15_t)0xc2e, (q15_t)0x8095, + (q15_t)0xc27, (q15_t)0x8095, (q15_t)0xc21, (q15_t)0x8094, (q15_t)0xc1b, (q15_t)0x8093, (q15_t)0xc14, (q15_t)0x8093, + (q15_t)0xc0e, (q15_t)0x8092, (q15_t)0xc08, (q15_t)0x8092, (q15_t)0xc02, (q15_t)0x8091, (q15_t)0xbfb, (q15_t)0x8090, + (q15_t)0xbf5, (q15_t)0x8090, (q15_t)0xbef, (q15_t)0x808f, (q15_t)0xbe9, (q15_t)0x808f, (q15_t)0xbe2, (q15_t)0x808e, + (q15_t)0xbdc, (q15_t)0x808e, (q15_t)0xbd6, (q15_t)0x808d, (q15_t)0xbd0, (q15_t)0x808c, (q15_t)0xbc9, (q15_t)0x808c, + (q15_t)0xbc3, (q15_t)0x808b, (q15_t)0xbbd, (q15_t)0x808b, (q15_t)0xbb7, (q15_t)0x808a, (q15_t)0xbb0, (q15_t)0x8089, + (q15_t)0xbaa, (q15_t)0x8089, (q15_t)0xba4, (q15_t)0x8088, (q15_t)0xb9e, (q15_t)0x8088, (q15_t)0xb97, (q15_t)0x8087, + (q15_t)0xb91, (q15_t)0x8087, (q15_t)0xb8b, (q15_t)0x8086, (q15_t)0xb85, (q15_t)0x8085, (q15_t)0xb7e, (q15_t)0x8085, + (q15_t)0xb78, (q15_t)0x8084, (q15_t)0xb72, (q15_t)0x8084, (q15_t)0xb6c, (q15_t)0x8083, (q15_t)0xb65, (q15_t)0x8083, + (q15_t)0xb5f, (q15_t)0x8082, (q15_t)0xb59, (q15_t)0x8082, (q15_t)0xb53, (q15_t)0x8081, (q15_t)0xb4c, (q15_t)0x8080, + (q15_t)0xb46, (q15_t)0x8080, (q15_t)0xb40, (q15_t)0x807f, (q15_t)0xb3a, (q15_t)0x807f, (q15_t)0xb33, (q15_t)0x807e, + (q15_t)0xb2d, (q15_t)0x807e, (q15_t)0xb27, (q15_t)0x807d, (q15_t)0xb20, (q15_t)0x807d, (q15_t)0xb1a, (q15_t)0x807c, + (q15_t)0xb14, (q15_t)0x807b, (q15_t)0xb0e, (q15_t)0x807b, (q15_t)0xb07, (q15_t)0x807a, (q15_t)0xb01, (q15_t)0x807a, + (q15_t)0xafb, (q15_t)0x8079, (q15_t)0xaf5, (q15_t)0x8079, (q15_t)0xaee, (q15_t)0x8078, (q15_t)0xae8, (q15_t)0x8078, + (q15_t)0xae2, (q15_t)0x8077, (q15_t)0xadc, (q15_t)0x8077, (q15_t)0xad5, (q15_t)0x8076, (q15_t)0xacf, (q15_t)0x8076, + (q15_t)0xac9, (q15_t)0x8075, (q15_t)0xac3, (q15_t)0x8075, (q15_t)0xabc, (q15_t)0x8074, (q15_t)0xab6, (q15_t)0x8073, + (q15_t)0xab0, (q15_t)0x8073, (q15_t)0xaaa, (q15_t)0x8072, (q15_t)0xaa3, (q15_t)0x8072, (q15_t)0xa9d, (q15_t)0x8071, + (q15_t)0xa97, (q15_t)0x8071, (q15_t)0xa90, (q15_t)0x8070, (q15_t)0xa8a, (q15_t)0x8070, (q15_t)0xa84, (q15_t)0x806f, + (q15_t)0xa7e, (q15_t)0x806f, (q15_t)0xa77, (q15_t)0x806e, (q15_t)0xa71, (q15_t)0x806e, (q15_t)0xa6b, (q15_t)0x806d, + (q15_t)0xa65, (q15_t)0x806d, (q15_t)0xa5e, (q15_t)0x806c, (q15_t)0xa58, (q15_t)0x806c, (q15_t)0xa52, (q15_t)0x806b, + (q15_t)0xa4c, (q15_t)0x806b, (q15_t)0xa45, (q15_t)0x806a, (q15_t)0xa3f, (q15_t)0x806a, (q15_t)0xa39, (q15_t)0x8069, + (q15_t)0xa33, (q15_t)0x8069, (q15_t)0xa2c, (q15_t)0x8068, (q15_t)0xa26, (q15_t)0x8068, (q15_t)0xa20, (q15_t)0x8067, + (q15_t)0xa19, (q15_t)0x8067, (q15_t)0xa13, (q15_t)0x8066, (q15_t)0xa0d, (q15_t)0x8066, (q15_t)0xa07, (q15_t)0x8065, + (q15_t)0xa00, (q15_t)0x8065, (q15_t)0x9fa, (q15_t)0x8064, (q15_t)0x9f4, (q15_t)0x8064, (q15_t)0x9ee, (q15_t)0x8063, + (q15_t)0x9e7, (q15_t)0x8063, (q15_t)0x9e1, (q15_t)0x8062, (q15_t)0x9db, (q15_t)0x8062, (q15_t)0x9d5, (q15_t)0x8061, + (q15_t)0x9ce, (q15_t)0x8061, (q15_t)0x9c8, (q15_t)0x8060, (q15_t)0x9c2, (q15_t)0x8060, (q15_t)0x9bc, (q15_t)0x805f, + (q15_t)0x9b5, (q15_t)0x805f, (q15_t)0x9af, (q15_t)0x805e, (q15_t)0x9a9, (q15_t)0x805e, (q15_t)0x9a2, (q15_t)0x805d, + (q15_t)0x99c, (q15_t)0x805d, (q15_t)0x996, (q15_t)0x805d, (q15_t)0x990, (q15_t)0x805c, (q15_t)0x989, (q15_t)0x805c, + (q15_t)0x983, (q15_t)0x805b, (q15_t)0x97d, (q15_t)0x805b, (q15_t)0x977, (q15_t)0x805a, (q15_t)0x970, (q15_t)0x805a, + (q15_t)0x96a, (q15_t)0x8059, (q15_t)0x964, (q15_t)0x8059, (q15_t)0x95e, (q15_t)0x8058, (q15_t)0x957, (q15_t)0x8058, + (q15_t)0x951, (q15_t)0x8057, (q15_t)0x94b, (q15_t)0x8057, (q15_t)0x944, (q15_t)0x8057, (q15_t)0x93e, (q15_t)0x8056, + (q15_t)0x938, (q15_t)0x8056, (q15_t)0x932, (q15_t)0x8055, (q15_t)0x92b, (q15_t)0x8055, (q15_t)0x925, (q15_t)0x8054, + (q15_t)0x91f, (q15_t)0x8054, (q15_t)0x919, (q15_t)0x8053, (q15_t)0x912, (q15_t)0x8053, (q15_t)0x90c, (q15_t)0x8052, + (q15_t)0x906, (q15_t)0x8052, (q15_t)0x900, (q15_t)0x8052, (q15_t)0x8f9, (q15_t)0x8051, (q15_t)0x8f3, (q15_t)0x8051, + (q15_t)0x8ed, (q15_t)0x8050, (q15_t)0x8e6, (q15_t)0x8050, (q15_t)0x8e0, (q15_t)0x804f, (q15_t)0x8da, (q15_t)0x804f, + (q15_t)0x8d4, (q15_t)0x804f, (q15_t)0x8cd, (q15_t)0x804e, (q15_t)0x8c7, (q15_t)0x804e, (q15_t)0x8c1, (q15_t)0x804d, + (q15_t)0x8bb, (q15_t)0x804d, (q15_t)0x8b4, (q15_t)0x804c, (q15_t)0x8ae, (q15_t)0x804c, (q15_t)0x8a8, (q15_t)0x804c, + (q15_t)0x8a2, (q15_t)0x804b, (q15_t)0x89b, (q15_t)0x804b, (q15_t)0x895, (q15_t)0x804a, (q15_t)0x88f, (q15_t)0x804a, + (q15_t)0x888, (q15_t)0x8049, (q15_t)0x882, (q15_t)0x8049, (q15_t)0x87c, (q15_t)0x8049, (q15_t)0x876, (q15_t)0x8048, + (q15_t)0x86f, (q15_t)0x8048, (q15_t)0x869, (q15_t)0x8047, (q15_t)0x863, (q15_t)0x8047, (q15_t)0x85d, (q15_t)0x8047, + (q15_t)0x856, (q15_t)0x8046, (q15_t)0x850, (q15_t)0x8046, (q15_t)0x84a, (q15_t)0x8045, (q15_t)0x843, (q15_t)0x8045, + (q15_t)0x83d, (q15_t)0x8044, (q15_t)0x837, (q15_t)0x8044, (q15_t)0x831, (q15_t)0x8044, (q15_t)0x82a, (q15_t)0x8043, + (q15_t)0x824, (q15_t)0x8043, (q15_t)0x81e, (q15_t)0x8042, (q15_t)0x818, (q15_t)0x8042, (q15_t)0x811, (q15_t)0x8042, + (q15_t)0x80b, (q15_t)0x8041, (q15_t)0x805, (q15_t)0x8041, (q15_t)0x7fe, (q15_t)0x8040, (q15_t)0x7f8, (q15_t)0x8040, + (q15_t)0x7f2, (q15_t)0x8040, (q15_t)0x7ec, (q15_t)0x803f, (q15_t)0x7e5, (q15_t)0x803f, (q15_t)0x7df, (q15_t)0x803f, + (q15_t)0x7d9, (q15_t)0x803e, (q15_t)0x7d3, (q15_t)0x803e, (q15_t)0x7cc, (q15_t)0x803d, (q15_t)0x7c6, (q15_t)0x803d, + (q15_t)0x7c0, (q15_t)0x803d, (q15_t)0x7ba, (q15_t)0x803c, (q15_t)0x7b3, (q15_t)0x803c, (q15_t)0x7ad, (q15_t)0x803b, + (q15_t)0x7a7, (q15_t)0x803b, (q15_t)0x7a0, (q15_t)0x803b, (q15_t)0x79a, (q15_t)0x803a, (q15_t)0x794, (q15_t)0x803a, + (q15_t)0x78e, (q15_t)0x803a, (q15_t)0x787, (q15_t)0x8039, (q15_t)0x781, (q15_t)0x8039, (q15_t)0x77b, (q15_t)0x8039, + (q15_t)0x775, (q15_t)0x8038, (q15_t)0x76e, (q15_t)0x8038, (q15_t)0x768, (q15_t)0x8037, (q15_t)0x762, (q15_t)0x8037, + (q15_t)0x75b, (q15_t)0x8037, (q15_t)0x755, (q15_t)0x8036, (q15_t)0x74f, (q15_t)0x8036, (q15_t)0x749, (q15_t)0x8036, + (q15_t)0x742, (q15_t)0x8035, (q15_t)0x73c, (q15_t)0x8035, (q15_t)0x736, (q15_t)0x8035, (q15_t)0x730, (q15_t)0x8034, + (q15_t)0x729, (q15_t)0x8034, (q15_t)0x723, (q15_t)0x8033, (q15_t)0x71d, (q15_t)0x8033, (q15_t)0x716, (q15_t)0x8033, + (q15_t)0x710, (q15_t)0x8032, (q15_t)0x70a, (q15_t)0x8032, (q15_t)0x704, (q15_t)0x8032, (q15_t)0x6fd, (q15_t)0x8031, + (q15_t)0x6f7, (q15_t)0x8031, (q15_t)0x6f1, (q15_t)0x8031, (q15_t)0x6ea, (q15_t)0x8030, (q15_t)0x6e4, (q15_t)0x8030, + (q15_t)0x6de, (q15_t)0x8030, (q15_t)0x6d8, (q15_t)0x802f, (q15_t)0x6d1, (q15_t)0x802f, (q15_t)0x6cb, (q15_t)0x802f, + (q15_t)0x6c5, (q15_t)0x802e, (q15_t)0x6bf, (q15_t)0x802e, (q15_t)0x6b8, (q15_t)0x802e, (q15_t)0x6b2, (q15_t)0x802d, + (q15_t)0x6ac, (q15_t)0x802d, (q15_t)0x6a5, (q15_t)0x802d, (q15_t)0x69f, (q15_t)0x802c, (q15_t)0x699, (q15_t)0x802c, + (q15_t)0x693, (q15_t)0x802c, (q15_t)0x68c, (q15_t)0x802b, (q15_t)0x686, (q15_t)0x802b, (q15_t)0x680, (q15_t)0x802b, + (q15_t)0x67a, (q15_t)0x802a, (q15_t)0x673, (q15_t)0x802a, (q15_t)0x66d, (q15_t)0x802a, (q15_t)0x667, (q15_t)0x802a, + (q15_t)0x660, (q15_t)0x8029, (q15_t)0x65a, (q15_t)0x8029, (q15_t)0x654, (q15_t)0x8029, (q15_t)0x64e, (q15_t)0x8028, + (q15_t)0x647, (q15_t)0x8028, (q15_t)0x641, (q15_t)0x8028, (q15_t)0x63b, (q15_t)0x8027, (q15_t)0x635, (q15_t)0x8027, + (q15_t)0x62e, (q15_t)0x8027, (q15_t)0x628, (q15_t)0x8026, (q15_t)0x622, (q15_t)0x8026, (q15_t)0x61b, (q15_t)0x8026, + (q15_t)0x615, (q15_t)0x8026, (q15_t)0x60f, (q15_t)0x8025, (q15_t)0x609, (q15_t)0x8025, (q15_t)0x602, (q15_t)0x8025, + (q15_t)0x5fc, (q15_t)0x8024, (q15_t)0x5f6, (q15_t)0x8024, (q15_t)0x5ef, (q15_t)0x8024, (q15_t)0x5e9, (q15_t)0x8023, + (q15_t)0x5e3, (q15_t)0x8023, (q15_t)0x5dd, (q15_t)0x8023, (q15_t)0x5d6, (q15_t)0x8023, (q15_t)0x5d0, (q15_t)0x8022, + (q15_t)0x5ca, (q15_t)0x8022, (q15_t)0x5c4, (q15_t)0x8022, (q15_t)0x5bd, (q15_t)0x8021, (q15_t)0x5b7, (q15_t)0x8021, + (q15_t)0x5b1, (q15_t)0x8021, (q15_t)0x5aa, (q15_t)0x8021, (q15_t)0x5a4, (q15_t)0x8020, (q15_t)0x59e, (q15_t)0x8020, + (q15_t)0x598, (q15_t)0x8020, (q15_t)0x591, (q15_t)0x8020, (q15_t)0x58b, (q15_t)0x801f, (q15_t)0x585, (q15_t)0x801f, + (q15_t)0x57f, (q15_t)0x801f, (q15_t)0x578, (q15_t)0x801e, (q15_t)0x572, (q15_t)0x801e, (q15_t)0x56c, (q15_t)0x801e, + (q15_t)0x565, (q15_t)0x801e, (q15_t)0x55f, (q15_t)0x801d, (q15_t)0x559, (q15_t)0x801d, (q15_t)0x553, (q15_t)0x801d, + (q15_t)0x54c, (q15_t)0x801d, (q15_t)0x546, (q15_t)0x801c, (q15_t)0x540, (q15_t)0x801c, (q15_t)0x539, (q15_t)0x801c, + (q15_t)0x533, (q15_t)0x801c, (q15_t)0x52d, (q15_t)0x801b, (q15_t)0x527, (q15_t)0x801b, (q15_t)0x520, (q15_t)0x801b, + (q15_t)0x51a, (q15_t)0x801b, (q15_t)0x514, (q15_t)0x801a, (q15_t)0x50d, (q15_t)0x801a, (q15_t)0x507, (q15_t)0x801a, + (q15_t)0x501, (q15_t)0x801a, (q15_t)0x4fb, (q15_t)0x8019, (q15_t)0x4f4, (q15_t)0x8019, (q15_t)0x4ee, (q15_t)0x8019, + (q15_t)0x4e8, (q15_t)0x8019, (q15_t)0x4e2, (q15_t)0x8018, (q15_t)0x4db, (q15_t)0x8018, (q15_t)0x4d5, (q15_t)0x8018, + (q15_t)0x4cf, (q15_t)0x8018, (q15_t)0x4c8, (q15_t)0x8017, (q15_t)0x4c2, (q15_t)0x8017, (q15_t)0x4bc, (q15_t)0x8017, + (q15_t)0x4b6, (q15_t)0x8017, (q15_t)0x4af, (q15_t)0x8016, (q15_t)0x4a9, (q15_t)0x8016, (q15_t)0x4a3, (q15_t)0x8016, + (q15_t)0x49c, (q15_t)0x8016, (q15_t)0x496, (q15_t)0x8016, (q15_t)0x490, (q15_t)0x8015, (q15_t)0x48a, (q15_t)0x8015, + (q15_t)0x483, (q15_t)0x8015, (q15_t)0x47d, (q15_t)0x8015, (q15_t)0x477, (q15_t)0x8014, (q15_t)0x471, (q15_t)0x8014, + (q15_t)0x46a, (q15_t)0x8014, (q15_t)0x464, (q15_t)0x8014, (q15_t)0x45e, (q15_t)0x8014, (q15_t)0x457, (q15_t)0x8013, + (q15_t)0x451, (q15_t)0x8013, (q15_t)0x44b, (q15_t)0x8013, (q15_t)0x445, (q15_t)0x8013, (q15_t)0x43e, (q15_t)0x8013, + (q15_t)0x438, (q15_t)0x8012, (q15_t)0x432, (q15_t)0x8012, (q15_t)0x42b, (q15_t)0x8012, (q15_t)0x425, (q15_t)0x8012, + (q15_t)0x41f, (q15_t)0x8012, (q15_t)0x419, (q15_t)0x8011, (q15_t)0x412, (q15_t)0x8011, (q15_t)0x40c, (q15_t)0x8011, + (q15_t)0x406, (q15_t)0x8011, (q15_t)0x3ff, (q15_t)0x8011, (q15_t)0x3f9, (q15_t)0x8010, (q15_t)0x3f3, (q15_t)0x8010, + (q15_t)0x3ed, (q15_t)0x8010, (q15_t)0x3e6, (q15_t)0x8010, (q15_t)0x3e0, (q15_t)0x8010, (q15_t)0x3da, (q15_t)0x800f, + (q15_t)0x3d4, (q15_t)0x800f, (q15_t)0x3cd, (q15_t)0x800f, (q15_t)0x3c7, (q15_t)0x800f, (q15_t)0x3c1, (q15_t)0x800f, + (q15_t)0x3ba, (q15_t)0x800e, (q15_t)0x3b4, (q15_t)0x800e, (q15_t)0x3ae, (q15_t)0x800e, (q15_t)0x3a8, (q15_t)0x800e, + (q15_t)0x3a1, (q15_t)0x800e, (q15_t)0x39b, (q15_t)0x800e, (q15_t)0x395, (q15_t)0x800d, (q15_t)0x38e, (q15_t)0x800d, + (q15_t)0x388, (q15_t)0x800d, (q15_t)0x382, (q15_t)0x800d, (q15_t)0x37c, (q15_t)0x800d, (q15_t)0x375, (q15_t)0x800c, + (q15_t)0x36f, (q15_t)0x800c, (q15_t)0x369, (q15_t)0x800c, (q15_t)0x362, (q15_t)0x800c, (q15_t)0x35c, (q15_t)0x800c, + (q15_t)0x356, (q15_t)0x800c, (q15_t)0x350, (q15_t)0x800b, (q15_t)0x349, (q15_t)0x800b, (q15_t)0x343, (q15_t)0x800b, + (q15_t)0x33d, (q15_t)0x800b, (q15_t)0x337, (q15_t)0x800b, (q15_t)0x330, (q15_t)0x800b, (q15_t)0x32a, (q15_t)0x800b, + (q15_t)0x324, (q15_t)0x800a, (q15_t)0x31d, (q15_t)0x800a, (q15_t)0x317, (q15_t)0x800a, (q15_t)0x311, (q15_t)0x800a, + (q15_t)0x30b, (q15_t)0x800a, (q15_t)0x304, (q15_t)0x800a, (q15_t)0x2fe, (q15_t)0x8009, (q15_t)0x2f8, (q15_t)0x8009, + (q15_t)0x2f1, (q15_t)0x8009, (q15_t)0x2eb, (q15_t)0x8009, (q15_t)0x2e5, (q15_t)0x8009, (q15_t)0x2df, (q15_t)0x8009, + (q15_t)0x2d8, (q15_t)0x8009, (q15_t)0x2d2, (q15_t)0x8008, (q15_t)0x2cc, (q15_t)0x8008, (q15_t)0x2c5, (q15_t)0x8008, + (q15_t)0x2bf, (q15_t)0x8008, (q15_t)0x2b9, (q15_t)0x8008, (q15_t)0x2b3, (q15_t)0x8008, (q15_t)0x2ac, (q15_t)0x8008, + (q15_t)0x2a6, (q15_t)0x8008, (q15_t)0x2a0, (q15_t)0x8007, (q15_t)0x299, (q15_t)0x8007, (q15_t)0x293, (q15_t)0x8007, + (q15_t)0x28d, (q15_t)0x8007, (q15_t)0x287, (q15_t)0x8007, (q15_t)0x280, (q15_t)0x8007, (q15_t)0x27a, (q15_t)0x8007, + (q15_t)0x274, (q15_t)0x8007, (q15_t)0x26d, (q15_t)0x8006, (q15_t)0x267, (q15_t)0x8006, (q15_t)0x261, (q15_t)0x8006, + (q15_t)0x25b, (q15_t)0x8006, (q15_t)0x254, (q15_t)0x8006, (q15_t)0x24e, (q15_t)0x8006, (q15_t)0x248, (q15_t)0x8006, + (q15_t)0x242, (q15_t)0x8006, (q15_t)0x23b, (q15_t)0x8005, (q15_t)0x235, (q15_t)0x8005, (q15_t)0x22f, (q15_t)0x8005, + (q15_t)0x228, (q15_t)0x8005, (q15_t)0x222, (q15_t)0x8005, (q15_t)0x21c, (q15_t)0x8005, (q15_t)0x216, (q15_t)0x8005, + (q15_t)0x20f, (q15_t)0x8005, (q15_t)0x209, (q15_t)0x8005, (q15_t)0x203, (q15_t)0x8005, (q15_t)0x1fc, (q15_t)0x8004, + (q15_t)0x1f6, (q15_t)0x8004, (q15_t)0x1f0, (q15_t)0x8004, (q15_t)0x1ea, (q15_t)0x8004, (q15_t)0x1e3, (q15_t)0x8004, + (q15_t)0x1dd, (q15_t)0x8004, (q15_t)0x1d7, (q15_t)0x8004, (q15_t)0x1d0, (q15_t)0x8004, (q15_t)0x1ca, (q15_t)0x8004, + (q15_t)0x1c4, (q15_t)0x8004, (q15_t)0x1be, (q15_t)0x8004, (q15_t)0x1b7, (q15_t)0x8003, (q15_t)0x1b1, (q15_t)0x8003, + (q15_t)0x1ab, (q15_t)0x8003, (q15_t)0x1a4, (q15_t)0x8003, (q15_t)0x19e, (q15_t)0x8003, (q15_t)0x198, (q15_t)0x8003, + (q15_t)0x192, (q15_t)0x8003, (q15_t)0x18b, (q15_t)0x8003, (q15_t)0x185, (q15_t)0x8003, (q15_t)0x17f, (q15_t)0x8003, + (q15_t)0x178, (q15_t)0x8003, (q15_t)0x172, (q15_t)0x8003, (q15_t)0x16c, (q15_t)0x8003, (q15_t)0x166, (q15_t)0x8002, + (q15_t)0x15f, (q15_t)0x8002, (q15_t)0x159, (q15_t)0x8002, (q15_t)0x153, (q15_t)0x8002, (q15_t)0x14d, (q15_t)0x8002, + (q15_t)0x146, (q15_t)0x8002, (q15_t)0x140, (q15_t)0x8002, (q15_t)0x13a, (q15_t)0x8002, (q15_t)0x133, (q15_t)0x8002, + (q15_t)0x12d, (q15_t)0x8002, (q15_t)0x127, (q15_t)0x8002, (q15_t)0x121, (q15_t)0x8002, (q15_t)0x11a, (q15_t)0x8002, + (q15_t)0x114, (q15_t)0x8002, (q15_t)0x10e, (q15_t)0x8002, (q15_t)0x107, (q15_t)0x8002, (q15_t)0x101, (q15_t)0x8002, + (q15_t)0xfb, (q15_t)0x8001, (q15_t)0xf5, (q15_t)0x8001, (q15_t)0xee, (q15_t)0x8001, (q15_t)0xe8, (q15_t)0x8001, + (q15_t)0xe2, (q15_t)0x8001, (q15_t)0xdb, (q15_t)0x8001, (q15_t)0xd5, (q15_t)0x8001, (q15_t)0xcf, (q15_t)0x8001, + (q15_t)0xc9, (q15_t)0x8001, (q15_t)0xc2, (q15_t)0x8001, (q15_t)0xbc, (q15_t)0x8001, (q15_t)0xb6, (q15_t)0x8001, + (q15_t)0xaf, (q15_t)0x8001, (q15_t)0xa9, (q15_t)0x8001, (q15_t)0xa3, (q15_t)0x8001, (q15_t)0x9d, (q15_t)0x8001, + (q15_t)0x96, (q15_t)0x8001, (q15_t)0x90, (q15_t)0x8001, (q15_t)0x8a, (q15_t)0x8001, (q15_t)0x83, (q15_t)0x8001, + (q15_t)0x7d, (q15_t)0x8001, (q15_t)0x77, (q15_t)0x8001, (q15_t)0x71, (q15_t)0x8001, (q15_t)0x6a, (q15_t)0x8001, + (q15_t)0x64, (q15_t)0x8001, (q15_t)0x5e, (q15_t)0x8001, (q15_t)0x57, (q15_t)0x8001, (q15_t)0x51, (q15_t)0x8001, + (q15_t)0x4b, (q15_t)0x8001, (q15_t)0x45, (q15_t)0x8001, (q15_t)0x3e, (q15_t)0x8001, (q15_t)0x38, (q15_t)0x8001, + (q15_t)0x32, (q15_t)0x8001, (q15_t)0x2b, (q15_t)0x8001, (q15_t)0x25, (q15_t)0x8001, (q15_t)0x1f, (q15_t)0x8001, + (q15_t)0x19, (q15_t)0x8001, (q15_t)0x12, (q15_t)0x8001, (q15_t)0xc, (q15_t)0x8001, (q15_t)0x6, (q15_t)0x8001 +}; + + const q15_t __ALIGNED(4) cos_factorsQ15_8192[8192] = { + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, (q15_t)0x7fff, + (q15_t)0x7fff, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffe, + (q15_t)0x7ffe, (q15_t)0x7ffe, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, + (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffd, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, (q15_t)0x7ffc, + (q15_t)0x7ffc, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, + (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffb, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, + (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ffa, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, + (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff9, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, + (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff8, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff7, + (q15_t)0x7ff7, (q15_t)0x7ff7, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, (q15_t)0x7ff6, + (q15_t)0x7ff6, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff5, (q15_t)0x7ff4, + (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff4, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, + (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff3, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, (q15_t)0x7ff2, + (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff1, (q15_t)0x7ff0, (q15_t)0x7ff0, + (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7ff0, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, (q15_t)0x7fef, + (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fee, (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fed, + (q15_t)0x7fed, (q15_t)0x7fed, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7fec, (q15_t)0x7feb, (q15_t)0x7feb, + (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7feb, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fea, (q15_t)0x7fe9, + (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe9, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, (q15_t)0x7fe8, + (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe7, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, (q15_t)0x7fe6, + (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe5, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, (q15_t)0x7fe4, + (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe3, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe2, (q15_t)0x7fe1, + (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe1, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fe0, (q15_t)0x7fdf, (q15_t)0x7fdf, + (q15_t)0x7fdf, (q15_t)0x7fdf, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fde, (q15_t)0x7fdd, (q15_t)0x7fdd, + (q15_t)0x7fdd, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdc, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, (q15_t)0x7fdb, + (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fda, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd9, (q15_t)0x7fd8, (q15_t)0x7fd8, + (q15_t)0x7fd8, (q15_t)0x7fd8, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd7, (q15_t)0x7fd6, (q15_t)0x7fd6, (q15_t)0x7fd6, + (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd5, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd4, (q15_t)0x7fd3, (q15_t)0x7fd3, + (q15_t)0x7fd3, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd2, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd1, (q15_t)0x7fd0, + (q15_t)0x7fd0, (q15_t)0x7fd0, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fcf, (q15_t)0x7fce, (q15_t)0x7fce, (q15_t)0x7fce, + (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcd, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcc, (q15_t)0x7fcb, (q15_t)0x7fcb, + (q15_t)0x7fcb, (q15_t)0x7fca, (q15_t)0x7fca, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc9, (q15_t)0x7fc8, (q15_t)0x7fc8, + (q15_t)0x7fc8, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc7, (q15_t)0x7fc6, (q15_t)0x7fc6, (q15_t)0x7fc5, (q15_t)0x7fc5, + (q15_t)0x7fc5, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc4, (q15_t)0x7fc3, (q15_t)0x7fc3, (q15_t)0x7fc2, (q15_t)0x7fc2, + (q15_t)0x7fc2, (q15_t)0x7fc1, (q15_t)0x7fc1, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fc0, (q15_t)0x7fbf, (q15_t)0x7fbf, + (q15_t)0x7fbf, (q15_t)0x7fbe, (q15_t)0x7fbe, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbd, (q15_t)0x7fbc, (q15_t)0x7fbc, + (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fbb, (q15_t)0x7fba, (q15_t)0x7fba, (q15_t)0x7fb9, (q15_t)0x7fb9, (q15_t)0x7fb8, + (q15_t)0x7fb8, (q15_t)0x7fb8, (q15_t)0x7fb7, (q15_t)0x7fb7, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb6, (q15_t)0x7fb5, + (q15_t)0x7fb5, (q15_t)0x7fb4, (q15_t)0x7fb4, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb3, (q15_t)0x7fb2, (q15_t)0x7fb2, + (q15_t)0x7fb1, (q15_t)0x7fb1, (q15_t)0x7fb0, (q15_t)0x7fb0, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7faf, (q15_t)0x7fae, + (q15_t)0x7fae, (q15_t)0x7fad, (q15_t)0x7fad, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fac, (q15_t)0x7fab, (q15_t)0x7fab, + (q15_t)0x7faa, (q15_t)0x7faa, (q15_t)0x7fa9, (q15_t)0x7fa9, (q15_t)0x7fa8, (q15_t)0x7fa8, (q15_t)0x7fa7, (q15_t)0x7fa7, + (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa6, (q15_t)0x7fa5, (q15_t)0x7fa5, (q15_t)0x7fa4, (q15_t)0x7fa4, (q15_t)0x7fa3, + (q15_t)0x7fa3, (q15_t)0x7fa2, (q15_t)0x7fa2, (q15_t)0x7fa1, (q15_t)0x7fa1, (q15_t)0x7fa0, (q15_t)0x7fa0, (q15_t)0x7f9f, + (q15_t)0x7f9f, (q15_t)0x7f9e, (q15_t)0x7f9e, (q15_t)0x7f9d, (q15_t)0x7f9d, (q15_t)0x7f9c, (q15_t)0x7f9c, (q15_t)0x7f9c, + (q15_t)0x7f9b, (q15_t)0x7f9b, (q15_t)0x7f9a, (q15_t)0x7f9a, (q15_t)0x7f99, (q15_t)0x7f99, (q15_t)0x7f98, (q15_t)0x7f98, + (q15_t)0x7f97, (q15_t)0x7f97, (q15_t)0x7f96, (q15_t)0x7f96, (q15_t)0x7f95, (q15_t)0x7f95, (q15_t)0x7f94, (q15_t)0x7f94, + (q15_t)0x7f93, (q15_t)0x7f92, (q15_t)0x7f92, (q15_t)0x7f91, (q15_t)0x7f91, (q15_t)0x7f90, (q15_t)0x7f90, (q15_t)0x7f8f, + (q15_t)0x7f8f, (q15_t)0x7f8e, (q15_t)0x7f8e, (q15_t)0x7f8d, (q15_t)0x7f8d, (q15_t)0x7f8c, (q15_t)0x7f8c, (q15_t)0x7f8b, + (q15_t)0x7f8b, (q15_t)0x7f8a, (q15_t)0x7f8a, (q15_t)0x7f89, (q15_t)0x7f89, (q15_t)0x7f88, (q15_t)0x7f87, (q15_t)0x7f87, + (q15_t)0x7f86, (q15_t)0x7f86, (q15_t)0x7f85, (q15_t)0x7f85, (q15_t)0x7f84, (q15_t)0x7f84, (q15_t)0x7f83, (q15_t)0x7f83, + (q15_t)0x7f82, (q15_t)0x7f81, (q15_t)0x7f81, (q15_t)0x7f80, (q15_t)0x7f80, (q15_t)0x7f7f, (q15_t)0x7f7f, (q15_t)0x7f7e, + (q15_t)0x7f7e, (q15_t)0x7f7d, (q15_t)0x7f7c, (q15_t)0x7f7c, (q15_t)0x7f7b, (q15_t)0x7f7b, (q15_t)0x7f7a, (q15_t)0x7f7a, + (q15_t)0x7f79, (q15_t)0x7f79, (q15_t)0x7f78, (q15_t)0x7f77, (q15_t)0x7f77, (q15_t)0x7f76, (q15_t)0x7f76, (q15_t)0x7f75, + (q15_t)0x7f75, (q15_t)0x7f74, (q15_t)0x7f73, (q15_t)0x7f73, (q15_t)0x7f72, (q15_t)0x7f72, (q15_t)0x7f71, (q15_t)0x7f70, + (q15_t)0x7f70, (q15_t)0x7f6f, (q15_t)0x7f6f, (q15_t)0x7f6e, (q15_t)0x7f6d, (q15_t)0x7f6d, (q15_t)0x7f6c, (q15_t)0x7f6c, + (q15_t)0x7f6b, (q15_t)0x7f6b, (q15_t)0x7f6a, (q15_t)0x7f69, (q15_t)0x7f69, (q15_t)0x7f68, (q15_t)0x7f68, (q15_t)0x7f67, + (q15_t)0x7f66, (q15_t)0x7f66, (q15_t)0x7f65, (q15_t)0x7f64, (q15_t)0x7f64, (q15_t)0x7f63, (q15_t)0x7f63, (q15_t)0x7f62, + (q15_t)0x7f61, (q15_t)0x7f61, (q15_t)0x7f60, (q15_t)0x7f60, (q15_t)0x7f5f, (q15_t)0x7f5e, (q15_t)0x7f5e, (q15_t)0x7f5d, + (q15_t)0x7f5c, (q15_t)0x7f5c, (q15_t)0x7f5b, (q15_t)0x7f5b, (q15_t)0x7f5a, (q15_t)0x7f59, (q15_t)0x7f59, (q15_t)0x7f58, + (q15_t)0x7f57, (q15_t)0x7f57, (q15_t)0x7f56, (q15_t)0x7f55, (q15_t)0x7f55, (q15_t)0x7f54, (q15_t)0x7f54, (q15_t)0x7f53, + (q15_t)0x7f52, (q15_t)0x7f52, (q15_t)0x7f51, (q15_t)0x7f50, (q15_t)0x7f50, (q15_t)0x7f4f, (q15_t)0x7f4e, (q15_t)0x7f4e, + (q15_t)0x7f4d, (q15_t)0x7f4c, (q15_t)0x7f4c, (q15_t)0x7f4b, (q15_t)0x7f4a, (q15_t)0x7f4a, (q15_t)0x7f49, (q15_t)0x7f48, + (q15_t)0x7f48, (q15_t)0x7f47, (q15_t)0x7f46, (q15_t)0x7f46, (q15_t)0x7f45, (q15_t)0x7f44, (q15_t)0x7f44, (q15_t)0x7f43, + (q15_t)0x7f42, (q15_t)0x7f42, (q15_t)0x7f41, (q15_t)0x7f40, (q15_t)0x7f40, (q15_t)0x7f3f, (q15_t)0x7f3e, (q15_t)0x7f3e, + (q15_t)0x7f3d, (q15_t)0x7f3c, (q15_t)0x7f3c, (q15_t)0x7f3b, (q15_t)0x7f3a, (q15_t)0x7f3a, (q15_t)0x7f39, (q15_t)0x7f38, + (q15_t)0x7f37, (q15_t)0x7f37, (q15_t)0x7f36, (q15_t)0x7f35, (q15_t)0x7f35, (q15_t)0x7f34, (q15_t)0x7f33, (q15_t)0x7f33, + (q15_t)0x7f32, (q15_t)0x7f31, (q15_t)0x7f31, (q15_t)0x7f30, (q15_t)0x7f2f, (q15_t)0x7f2e, (q15_t)0x7f2e, (q15_t)0x7f2d, + (q15_t)0x7f2c, (q15_t)0x7f2c, (q15_t)0x7f2b, (q15_t)0x7f2a, (q15_t)0x7f29, (q15_t)0x7f29, (q15_t)0x7f28, (q15_t)0x7f27, + (q15_t)0x7f27, (q15_t)0x7f26, (q15_t)0x7f25, (q15_t)0x7f24, (q15_t)0x7f24, (q15_t)0x7f23, (q15_t)0x7f22, (q15_t)0x7f21, + (q15_t)0x7f21, (q15_t)0x7f20, (q15_t)0x7f1f, (q15_t)0x7f1f, (q15_t)0x7f1e, (q15_t)0x7f1d, (q15_t)0x7f1c, (q15_t)0x7f1c, + (q15_t)0x7f1b, (q15_t)0x7f1a, (q15_t)0x7f19, (q15_t)0x7f19, (q15_t)0x7f18, (q15_t)0x7f17, (q15_t)0x7f16, (q15_t)0x7f16, + (q15_t)0x7f15, (q15_t)0x7f14, (q15_t)0x7f13, (q15_t)0x7f13, (q15_t)0x7f12, (q15_t)0x7f11, (q15_t)0x7f10, (q15_t)0x7f10, + (q15_t)0x7f0f, (q15_t)0x7f0e, (q15_t)0x7f0d, (q15_t)0x7f0d, (q15_t)0x7f0c, (q15_t)0x7f0b, (q15_t)0x7f0a, (q15_t)0x7f09, + (q15_t)0x7f09, (q15_t)0x7f08, (q15_t)0x7f07, (q15_t)0x7f06, (q15_t)0x7f06, (q15_t)0x7f05, (q15_t)0x7f04, (q15_t)0x7f03, + (q15_t)0x7f02, (q15_t)0x7f02, (q15_t)0x7f01, (q15_t)0x7f00, (q15_t)0x7eff, (q15_t)0x7eff, (q15_t)0x7efe, (q15_t)0x7efd, + (q15_t)0x7efc, (q15_t)0x7efb, (q15_t)0x7efb, (q15_t)0x7efa, (q15_t)0x7ef9, (q15_t)0x7ef8, (q15_t)0x7ef7, (q15_t)0x7ef7, + (q15_t)0x7ef6, (q15_t)0x7ef5, (q15_t)0x7ef4, (q15_t)0x7ef3, (q15_t)0x7ef3, (q15_t)0x7ef2, (q15_t)0x7ef1, (q15_t)0x7ef0, + (q15_t)0x7eef, (q15_t)0x7eef, (q15_t)0x7eee, (q15_t)0x7eed, (q15_t)0x7eec, (q15_t)0x7eeb, (q15_t)0x7eeb, (q15_t)0x7eea, + (q15_t)0x7ee9, (q15_t)0x7ee8, (q15_t)0x7ee7, (q15_t)0x7ee6, (q15_t)0x7ee6, (q15_t)0x7ee5, (q15_t)0x7ee4, (q15_t)0x7ee3, + (q15_t)0x7ee2, (q15_t)0x7ee2, (q15_t)0x7ee1, (q15_t)0x7ee0, (q15_t)0x7edf, (q15_t)0x7ede, (q15_t)0x7edd, (q15_t)0x7edd, + (q15_t)0x7edc, (q15_t)0x7edb, (q15_t)0x7eda, (q15_t)0x7ed9, (q15_t)0x7ed8, (q15_t)0x7ed8, (q15_t)0x7ed7, (q15_t)0x7ed6, + (q15_t)0x7ed5, (q15_t)0x7ed4, (q15_t)0x7ed3, (q15_t)0x7ed2, (q15_t)0x7ed2, (q15_t)0x7ed1, (q15_t)0x7ed0, (q15_t)0x7ecf, + (q15_t)0x7ece, (q15_t)0x7ecd, (q15_t)0x7ecc, (q15_t)0x7ecc, (q15_t)0x7ecb, (q15_t)0x7eca, (q15_t)0x7ec9, (q15_t)0x7ec8, + (q15_t)0x7ec7, (q15_t)0x7ec6, (q15_t)0x7ec6, (q15_t)0x7ec5, (q15_t)0x7ec4, (q15_t)0x7ec3, (q15_t)0x7ec2, (q15_t)0x7ec1, + (q15_t)0x7ec0, (q15_t)0x7ebf, (q15_t)0x7ebf, (q15_t)0x7ebe, (q15_t)0x7ebd, (q15_t)0x7ebc, (q15_t)0x7ebb, (q15_t)0x7eba, + (q15_t)0x7eb9, (q15_t)0x7eb8, (q15_t)0x7eb8, (q15_t)0x7eb7, (q15_t)0x7eb6, (q15_t)0x7eb5, (q15_t)0x7eb4, (q15_t)0x7eb3, + (q15_t)0x7eb2, (q15_t)0x7eb1, (q15_t)0x7eb0, (q15_t)0x7eaf, (q15_t)0x7eaf, (q15_t)0x7eae, (q15_t)0x7ead, (q15_t)0x7eac, + (q15_t)0x7eab, (q15_t)0x7eaa, (q15_t)0x7ea9, (q15_t)0x7ea8, (q15_t)0x7ea7, (q15_t)0x7ea6, (q15_t)0x7ea6, (q15_t)0x7ea5, + (q15_t)0x7ea4, (q15_t)0x7ea3, (q15_t)0x7ea2, (q15_t)0x7ea1, (q15_t)0x7ea0, (q15_t)0x7e9f, (q15_t)0x7e9e, (q15_t)0x7e9d, + (q15_t)0x7e9c, (q15_t)0x7e9b, (q15_t)0x7e9b, (q15_t)0x7e9a, (q15_t)0x7e99, (q15_t)0x7e98, (q15_t)0x7e97, (q15_t)0x7e96, + (q15_t)0x7e95, (q15_t)0x7e94, (q15_t)0x7e93, (q15_t)0x7e92, (q15_t)0x7e91, (q15_t)0x7e90, (q15_t)0x7e8f, (q15_t)0x7e8e, + (q15_t)0x7e8d, (q15_t)0x7e8d, (q15_t)0x7e8c, (q15_t)0x7e8b, (q15_t)0x7e8a, (q15_t)0x7e89, (q15_t)0x7e88, (q15_t)0x7e87, + (q15_t)0x7e86, (q15_t)0x7e85, (q15_t)0x7e84, (q15_t)0x7e83, (q15_t)0x7e82, (q15_t)0x7e81, (q15_t)0x7e80, (q15_t)0x7e7f, + (q15_t)0x7e7e, (q15_t)0x7e7d, (q15_t)0x7e7c, (q15_t)0x7e7b, (q15_t)0x7e7a, (q15_t)0x7e79, (q15_t)0x7e78, (q15_t)0x7e77, + (q15_t)0x7e77, (q15_t)0x7e76, (q15_t)0x7e75, (q15_t)0x7e74, (q15_t)0x7e73, (q15_t)0x7e72, (q15_t)0x7e71, (q15_t)0x7e70, + (q15_t)0x7e6f, (q15_t)0x7e6e, (q15_t)0x7e6d, (q15_t)0x7e6c, (q15_t)0x7e6b, (q15_t)0x7e6a, (q15_t)0x7e69, (q15_t)0x7e68, + (q15_t)0x7e67, (q15_t)0x7e66, (q15_t)0x7e65, (q15_t)0x7e64, (q15_t)0x7e63, (q15_t)0x7e62, (q15_t)0x7e61, (q15_t)0x7e60, + (q15_t)0x7e5f, (q15_t)0x7e5e, (q15_t)0x7e5d, (q15_t)0x7e5c, (q15_t)0x7e5b, (q15_t)0x7e5a, (q15_t)0x7e59, (q15_t)0x7e58, + (q15_t)0x7e57, (q15_t)0x7e56, (q15_t)0x7e55, (q15_t)0x7e54, (q15_t)0x7e53, (q15_t)0x7e52, (q15_t)0x7e51, (q15_t)0x7e50, + (q15_t)0x7e4f, (q15_t)0x7e4e, (q15_t)0x7e4d, (q15_t)0x7e4c, (q15_t)0x7e4b, (q15_t)0x7e4a, (q15_t)0x7e49, (q15_t)0x7e48, + (q15_t)0x7e47, (q15_t)0x7e46, (q15_t)0x7e45, (q15_t)0x7e43, (q15_t)0x7e42, (q15_t)0x7e41, (q15_t)0x7e40, (q15_t)0x7e3f, + (q15_t)0x7e3e, (q15_t)0x7e3d, (q15_t)0x7e3c, (q15_t)0x7e3b, (q15_t)0x7e3a, (q15_t)0x7e39, (q15_t)0x7e38, (q15_t)0x7e37, + (q15_t)0x7e36, (q15_t)0x7e35, (q15_t)0x7e34, (q15_t)0x7e33, (q15_t)0x7e32, (q15_t)0x7e31, (q15_t)0x7e30, (q15_t)0x7e2f, + (q15_t)0x7e2e, (q15_t)0x7e2d, (q15_t)0x7e2b, (q15_t)0x7e2a, (q15_t)0x7e29, (q15_t)0x7e28, (q15_t)0x7e27, (q15_t)0x7e26, + (q15_t)0x7e25, (q15_t)0x7e24, (q15_t)0x7e23, (q15_t)0x7e22, (q15_t)0x7e21, (q15_t)0x7e20, (q15_t)0x7e1f, (q15_t)0x7e1e, + (q15_t)0x7e1d, (q15_t)0x7e1b, (q15_t)0x7e1a, (q15_t)0x7e19, (q15_t)0x7e18, (q15_t)0x7e17, (q15_t)0x7e16, (q15_t)0x7e15, + (q15_t)0x7e14, (q15_t)0x7e13, (q15_t)0x7e12, (q15_t)0x7e11, (q15_t)0x7e10, (q15_t)0x7e0e, (q15_t)0x7e0d, (q15_t)0x7e0c, + (q15_t)0x7e0b, (q15_t)0x7e0a, (q15_t)0x7e09, (q15_t)0x7e08, (q15_t)0x7e07, (q15_t)0x7e06, (q15_t)0x7e05, (q15_t)0x7e04, + (q15_t)0x7e02, (q15_t)0x7e01, (q15_t)0x7e00, (q15_t)0x7dff, (q15_t)0x7dfe, (q15_t)0x7dfd, (q15_t)0x7dfc, (q15_t)0x7dfb, + (q15_t)0x7dfa, (q15_t)0x7df8, (q15_t)0x7df7, (q15_t)0x7df6, (q15_t)0x7df5, (q15_t)0x7df4, (q15_t)0x7df3, (q15_t)0x7df2, + (q15_t)0x7df1, (q15_t)0x7def, (q15_t)0x7dee, (q15_t)0x7ded, (q15_t)0x7dec, (q15_t)0x7deb, (q15_t)0x7dea, (q15_t)0x7de9, + (q15_t)0x7de8, (q15_t)0x7de6, (q15_t)0x7de5, (q15_t)0x7de4, (q15_t)0x7de3, (q15_t)0x7de2, (q15_t)0x7de1, (q15_t)0x7de0, + (q15_t)0x7dde, (q15_t)0x7ddd, (q15_t)0x7ddc, (q15_t)0x7ddb, (q15_t)0x7dda, (q15_t)0x7dd9, (q15_t)0x7dd8, (q15_t)0x7dd6, + (q15_t)0x7dd5, (q15_t)0x7dd4, (q15_t)0x7dd3, (q15_t)0x7dd2, (q15_t)0x7dd1, (q15_t)0x7dd0, (q15_t)0x7dce, (q15_t)0x7dcd, + (q15_t)0x7dcc, (q15_t)0x7dcb, (q15_t)0x7dca, (q15_t)0x7dc9, (q15_t)0x7dc7, (q15_t)0x7dc6, (q15_t)0x7dc5, (q15_t)0x7dc4, + (q15_t)0x7dc3, (q15_t)0x7dc2, (q15_t)0x7dc0, (q15_t)0x7dbf, (q15_t)0x7dbe, (q15_t)0x7dbd, (q15_t)0x7dbc, (q15_t)0x7dbb, + (q15_t)0x7db9, (q15_t)0x7db8, (q15_t)0x7db7, (q15_t)0x7db6, (q15_t)0x7db5, (q15_t)0x7db3, (q15_t)0x7db2, (q15_t)0x7db1, + (q15_t)0x7db0, (q15_t)0x7daf, (q15_t)0x7dae, (q15_t)0x7dac, (q15_t)0x7dab, (q15_t)0x7daa, (q15_t)0x7da9, (q15_t)0x7da8, + (q15_t)0x7da6, (q15_t)0x7da5, (q15_t)0x7da4, (q15_t)0x7da3, (q15_t)0x7da2, (q15_t)0x7da0, (q15_t)0x7d9f, (q15_t)0x7d9e, + (q15_t)0x7d9d, (q15_t)0x7d9c, (q15_t)0x7d9a, (q15_t)0x7d99, (q15_t)0x7d98, (q15_t)0x7d97, (q15_t)0x7d95, (q15_t)0x7d94, + (q15_t)0x7d93, (q15_t)0x7d92, (q15_t)0x7d91, (q15_t)0x7d8f, (q15_t)0x7d8e, (q15_t)0x7d8d, (q15_t)0x7d8c, (q15_t)0x7d8a, + (q15_t)0x7d89, (q15_t)0x7d88, (q15_t)0x7d87, (q15_t)0x7d86, (q15_t)0x7d84, (q15_t)0x7d83, (q15_t)0x7d82, (q15_t)0x7d81, + (q15_t)0x7d7f, (q15_t)0x7d7e, (q15_t)0x7d7d, (q15_t)0x7d7c, (q15_t)0x7d7a, (q15_t)0x7d79, (q15_t)0x7d78, (q15_t)0x7d77, + (q15_t)0x7d75, (q15_t)0x7d74, (q15_t)0x7d73, (q15_t)0x7d72, (q15_t)0x7d70, (q15_t)0x7d6f, (q15_t)0x7d6e, (q15_t)0x7d6d, + (q15_t)0x7d6b, (q15_t)0x7d6a, (q15_t)0x7d69, (q15_t)0x7d68, (q15_t)0x7d66, (q15_t)0x7d65, (q15_t)0x7d64, (q15_t)0x7d63, + (q15_t)0x7d61, (q15_t)0x7d60, (q15_t)0x7d5f, (q15_t)0x7d5e, (q15_t)0x7d5c, (q15_t)0x7d5b, (q15_t)0x7d5a, (q15_t)0x7d59, + (q15_t)0x7d57, (q15_t)0x7d56, (q15_t)0x7d55, (q15_t)0x7d53, (q15_t)0x7d52, (q15_t)0x7d51, (q15_t)0x7d50, (q15_t)0x7d4e, + (q15_t)0x7d4d, (q15_t)0x7d4c, (q15_t)0x7d4a, (q15_t)0x7d49, (q15_t)0x7d48, (q15_t)0x7d47, (q15_t)0x7d45, (q15_t)0x7d44, + (q15_t)0x7d43, (q15_t)0x7d41, (q15_t)0x7d40, (q15_t)0x7d3f, (q15_t)0x7d3e, (q15_t)0x7d3c, (q15_t)0x7d3b, (q15_t)0x7d3a, + (q15_t)0x7d38, (q15_t)0x7d37, (q15_t)0x7d36, (q15_t)0x7d34, (q15_t)0x7d33, (q15_t)0x7d32, (q15_t)0x7d31, (q15_t)0x7d2f, + (q15_t)0x7d2e, (q15_t)0x7d2d, (q15_t)0x7d2b, (q15_t)0x7d2a, (q15_t)0x7d29, (q15_t)0x7d27, (q15_t)0x7d26, (q15_t)0x7d25, + (q15_t)0x7d23, (q15_t)0x7d22, (q15_t)0x7d21, (q15_t)0x7d1f, (q15_t)0x7d1e, (q15_t)0x7d1d, (q15_t)0x7d1b, (q15_t)0x7d1a, + (q15_t)0x7d19, (q15_t)0x7d17, (q15_t)0x7d16, (q15_t)0x7d15, (q15_t)0x7d13, (q15_t)0x7d12, (q15_t)0x7d11, (q15_t)0x7d0f, + (q15_t)0x7d0e, (q15_t)0x7d0d, (q15_t)0x7d0b, (q15_t)0x7d0a, (q15_t)0x7d09, (q15_t)0x7d07, (q15_t)0x7d06, (q15_t)0x7d05, + (q15_t)0x7d03, (q15_t)0x7d02, (q15_t)0x7d01, (q15_t)0x7cff, (q15_t)0x7cfe, (q15_t)0x7cfd, (q15_t)0x7cfb, (q15_t)0x7cfa, + (q15_t)0x7cf9, (q15_t)0x7cf7, (q15_t)0x7cf6, (q15_t)0x7cf4, (q15_t)0x7cf3, (q15_t)0x7cf2, (q15_t)0x7cf0, (q15_t)0x7cef, + (q15_t)0x7cee, (q15_t)0x7cec, (q15_t)0x7ceb, (q15_t)0x7ce9, (q15_t)0x7ce8, (q15_t)0x7ce7, (q15_t)0x7ce5, (q15_t)0x7ce4, + (q15_t)0x7ce3, (q15_t)0x7ce1, (q15_t)0x7ce0, (q15_t)0x7cde, (q15_t)0x7cdd, (q15_t)0x7cdc, (q15_t)0x7cda, (q15_t)0x7cd9, + (q15_t)0x7cd8, (q15_t)0x7cd6, (q15_t)0x7cd5, (q15_t)0x7cd3, (q15_t)0x7cd2, (q15_t)0x7cd1, (q15_t)0x7ccf, (q15_t)0x7cce, + (q15_t)0x7ccc, (q15_t)0x7ccb, (q15_t)0x7cca, (q15_t)0x7cc8, (q15_t)0x7cc7, (q15_t)0x7cc5, (q15_t)0x7cc4, (q15_t)0x7cc3, + (q15_t)0x7cc1, (q15_t)0x7cc0, (q15_t)0x7cbe, (q15_t)0x7cbd, (q15_t)0x7cbc, (q15_t)0x7cba, (q15_t)0x7cb9, (q15_t)0x7cb7, + (q15_t)0x7cb6, (q15_t)0x7cb5, (q15_t)0x7cb3, (q15_t)0x7cb2, (q15_t)0x7cb0, (q15_t)0x7caf, (q15_t)0x7cad, (q15_t)0x7cac, + (q15_t)0x7cab, (q15_t)0x7ca9, (q15_t)0x7ca8, (q15_t)0x7ca6, (q15_t)0x7ca5, (q15_t)0x7ca3, (q15_t)0x7ca2, (q15_t)0x7ca1, + (q15_t)0x7c9f, (q15_t)0x7c9e, (q15_t)0x7c9c, (q15_t)0x7c9b, (q15_t)0x7c99, (q15_t)0x7c98, (q15_t)0x7c97, (q15_t)0x7c95, + (q15_t)0x7c94, (q15_t)0x7c92, (q15_t)0x7c91, (q15_t)0x7c8f, (q15_t)0x7c8e, (q15_t)0x7c8c, (q15_t)0x7c8b, (q15_t)0x7c8a, + (q15_t)0x7c88, (q15_t)0x7c87, (q15_t)0x7c85, (q15_t)0x7c84, (q15_t)0x7c82, (q15_t)0x7c81, (q15_t)0x7c7f, (q15_t)0x7c7e, + (q15_t)0x7c7c, (q15_t)0x7c7b, (q15_t)0x7c79, (q15_t)0x7c78, (q15_t)0x7c77, (q15_t)0x7c75, (q15_t)0x7c74, (q15_t)0x7c72, + (q15_t)0x7c71, (q15_t)0x7c6f, (q15_t)0x7c6e, (q15_t)0x7c6c, (q15_t)0x7c6b, (q15_t)0x7c69, (q15_t)0x7c68, (q15_t)0x7c66, + (q15_t)0x7c65, (q15_t)0x7c63, (q15_t)0x7c62, (q15_t)0x7c60, (q15_t)0x7c5f, (q15_t)0x7c5d, (q15_t)0x7c5c, (q15_t)0x7c5a, + (q15_t)0x7c59, (q15_t)0x7c58, (q15_t)0x7c56, (q15_t)0x7c55, (q15_t)0x7c53, (q15_t)0x7c52, (q15_t)0x7c50, (q15_t)0x7c4f, + (q15_t)0x7c4d, (q15_t)0x7c4c, (q15_t)0x7c4a, (q15_t)0x7c49, (q15_t)0x7c47, (q15_t)0x7c46, (q15_t)0x7c44, (q15_t)0x7c43, + (q15_t)0x7c41, (q15_t)0x7c3f, (q15_t)0x7c3e, (q15_t)0x7c3c, (q15_t)0x7c3b, (q15_t)0x7c39, (q15_t)0x7c38, (q15_t)0x7c36, + (q15_t)0x7c35, (q15_t)0x7c33, (q15_t)0x7c32, (q15_t)0x7c30, (q15_t)0x7c2f, (q15_t)0x7c2d, (q15_t)0x7c2c, (q15_t)0x7c2a, + (q15_t)0x7c29, (q15_t)0x7c27, (q15_t)0x7c26, (q15_t)0x7c24, (q15_t)0x7c23, (q15_t)0x7c21, (q15_t)0x7c20, (q15_t)0x7c1e, + (q15_t)0x7c1c, (q15_t)0x7c1b, (q15_t)0x7c19, (q15_t)0x7c18, (q15_t)0x7c16, (q15_t)0x7c15, (q15_t)0x7c13, (q15_t)0x7c12, + (q15_t)0x7c10, (q15_t)0x7c0f, (q15_t)0x7c0d, (q15_t)0x7c0b, (q15_t)0x7c0a, (q15_t)0x7c08, (q15_t)0x7c07, (q15_t)0x7c05, + (q15_t)0x7c04, (q15_t)0x7c02, (q15_t)0x7c01, (q15_t)0x7bff, (q15_t)0x7bfd, (q15_t)0x7bfc, (q15_t)0x7bfa, (q15_t)0x7bf9, + (q15_t)0x7bf7, (q15_t)0x7bf6, (q15_t)0x7bf4, (q15_t)0x7bf3, (q15_t)0x7bf1, (q15_t)0x7bef, (q15_t)0x7bee, (q15_t)0x7bec, + (q15_t)0x7beb, (q15_t)0x7be9, (q15_t)0x7be8, (q15_t)0x7be6, (q15_t)0x7be4, (q15_t)0x7be3, (q15_t)0x7be1, (q15_t)0x7be0, + (q15_t)0x7bde, (q15_t)0x7bdc, (q15_t)0x7bdb, (q15_t)0x7bd9, (q15_t)0x7bd8, (q15_t)0x7bd6, (q15_t)0x7bd5, (q15_t)0x7bd3, + (q15_t)0x7bd1, (q15_t)0x7bd0, (q15_t)0x7bce, (q15_t)0x7bcd, (q15_t)0x7bcb, (q15_t)0x7bc9, (q15_t)0x7bc8, (q15_t)0x7bc6, + (q15_t)0x7bc5, (q15_t)0x7bc3, (q15_t)0x7bc1, (q15_t)0x7bc0, (q15_t)0x7bbe, (q15_t)0x7bbd, (q15_t)0x7bbb, (q15_t)0x7bb9, + (q15_t)0x7bb8, (q15_t)0x7bb6, (q15_t)0x7bb5, (q15_t)0x7bb3, (q15_t)0x7bb1, (q15_t)0x7bb0, (q15_t)0x7bae, (q15_t)0x7bac, + (q15_t)0x7bab, (q15_t)0x7ba9, (q15_t)0x7ba8, (q15_t)0x7ba6, (q15_t)0x7ba4, (q15_t)0x7ba3, (q15_t)0x7ba1, (q15_t)0x7b9f, + (q15_t)0x7b9e, (q15_t)0x7b9c, (q15_t)0x7b9b, (q15_t)0x7b99, (q15_t)0x7b97, (q15_t)0x7b96, (q15_t)0x7b94, (q15_t)0x7b92, + (q15_t)0x7b91, (q15_t)0x7b8f, (q15_t)0x7b8d, (q15_t)0x7b8c, (q15_t)0x7b8a, (q15_t)0x7b89, (q15_t)0x7b87, (q15_t)0x7b85, + (q15_t)0x7b84, (q15_t)0x7b82, (q15_t)0x7b80, (q15_t)0x7b7f, (q15_t)0x7b7d, (q15_t)0x7b7b, (q15_t)0x7b7a, (q15_t)0x7b78, + (q15_t)0x7b76, (q15_t)0x7b75, (q15_t)0x7b73, (q15_t)0x7b71, (q15_t)0x7b70, (q15_t)0x7b6e, (q15_t)0x7b6c, (q15_t)0x7b6b, + (q15_t)0x7b69, (q15_t)0x7b67, (q15_t)0x7b66, (q15_t)0x7b64, (q15_t)0x7b62, (q15_t)0x7b61, (q15_t)0x7b5f, (q15_t)0x7b5d, + (q15_t)0x7b5c, (q15_t)0x7b5a, (q15_t)0x7b58, (q15_t)0x7b57, (q15_t)0x7b55, (q15_t)0x7b53, (q15_t)0x7b52, (q15_t)0x7b50, + (q15_t)0x7b4e, (q15_t)0x7b4d, (q15_t)0x7b4b, (q15_t)0x7b49, (q15_t)0x7b47, (q15_t)0x7b46, (q15_t)0x7b44, (q15_t)0x7b42, + (q15_t)0x7b41, (q15_t)0x7b3f, (q15_t)0x7b3d, (q15_t)0x7b3c, (q15_t)0x7b3a, (q15_t)0x7b38, (q15_t)0x7b37, (q15_t)0x7b35, + (q15_t)0x7b33, (q15_t)0x7b31, (q15_t)0x7b30, (q15_t)0x7b2e, (q15_t)0x7b2c, (q15_t)0x7b2b, (q15_t)0x7b29, (q15_t)0x7b27, + (q15_t)0x7b25, (q15_t)0x7b24, (q15_t)0x7b22, (q15_t)0x7b20, (q15_t)0x7b1f, (q15_t)0x7b1d, (q15_t)0x7b1b, (q15_t)0x7b19, + (q15_t)0x7b18, (q15_t)0x7b16, (q15_t)0x7b14, (q15_t)0x7b13, (q15_t)0x7b11, (q15_t)0x7b0f, (q15_t)0x7b0d, (q15_t)0x7b0c, + (q15_t)0x7b0a, (q15_t)0x7b08, (q15_t)0x7b06, (q15_t)0x7b05, (q15_t)0x7b03, (q15_t)0x7b01, (q15_t)0x7aff, (q15_t)0x7afe, + (q15_t)0x7afc, (q15_t)0x7afa, (q15_t)0x7af8, (q15_t)0x7af7, (q15_t)0x7af5, (q15_t)0x7af3, (q15_t)0x7af2, (q15_t)0x7af0, + (q15_t)0x7aee, (q15_t)0x7aec, (q15_t)0x7aeb, (q15_t)0x7ae9, (q15_t)0x7ae7, (q15_t)0x7ae5, (q15_t)0x7ae3, (q15_t)0x7ae2, + (q15_t)0x7ae0, (q15_t)0x7ade, (q15_t)0x7adc, (q15_t)0x7adb, (q15_t)0x7ad9, (q15_t)0x7ad7, (q15_t)0x7ad5, (q15_t)0x7ad4, + (q15_t)0x7ad2, (q15_t)0x7ad0, (q15_t)0x7ace, (q15_t)0x7acd, (q15_t)0x7acb, (q15_t)0x7ac9, (q15_t)0x7ac7, (q15_t)0x7ac5, + (q15_t)0x7ac4, (q15_t)0x7ac2, (q15_t)0x7ac0, (q15_t)0x7abe, (q15_t)0x7abd, (q15_t)0x7abb, (q15_t)0x7ab9, (q15_t)0x7ab7, + (q15_t)0x7ab5, (q15_t)0x7ab4, (q15_t)0x7ab2, (q15_t)0x7ab0, (q15_t)0x7aae, (q15_t)0x7aac, (q15_t)0x7aab, (q15_t)0x7aa9, + (q15_t)0x7aa7, (q15_t)0x7aa5, (q15_t)0x7aa3, (q15_t)0x7aa2, (q15_t)0x7aa0, (q15_t)0x7a9e, (q15_t)0x7a9c, (q15_t)0x7a9a, + (q15_t)0x7a99, (q15_t)0x7a97, (q15_t)0x7a95, (q15_t)0x7a93, (q15_t)0x7a91, (q15_t)0x7a90, (q15_t)0x7a8e, (q15_t)0x7a8c, + (q15_t)0x7a8a, (q15_t)0x7a88, (q15_t)0x7a87, (q15_t)0x7a85, (q15_t)0x7a83, (q15_t)0x7a81, (q15_t)0x7a7f, (q15_t)0x7a7d, + (q15_t)0x7a7c, (q15_t)0x7a7a, (q15_t)0x7a78, (q15_t)0x7a76, (q15_t)0x7a74, (q15_t)0x7a72, (q15_t)0x7a71, (q15_t)0x7a6f, + (q15_t)0x7a6d, (q15_t)0x7a6b, (q15_t)0x7a69, (q15_t)0x7a67, (q15_t)0x7a66, (q15_t)0x7a64, (q15_t)0x7a62, (q15_t)0x7a60, + (q15_t)0x7a5e, (q15_t)0x7a5c, (q15_t)0x7a5b, (q15_t)0x7a59, (q15_t)0x7a57, (q15_t)0x7a55, (q15_t)0x7a53, (q15_t)0x7a51, + (q15_t)0x7a4f, (q15_t)0x7a4e, (q15_t)0x7a4c, (q15_t)0x7a4a, (q15_t)0x7a48, (q15_t)0x7a46, (q15_t)0x7a44, (q15_t)0x7a42, + (q15_t)0x7a41, (q15_t)0x7a3f, (q15_t)0x7a3d, (q15_t)0x7a3b, (q15_t)0x7a39, (q15_t)0x7a37, (q15_t)0x7a35, (q15_t)0x7a34, + (q15_t)0x7a32, (q15_t)0x7a30, (q15_t)0x7a2e, (q15_t)0x7a2c, (q15_t)0x7a2a, (q15_t)0x7a28, (q15_t)0x7a26, (q15_t)0x7a25, + (q15_t)0x7a23, (q15_t)0x7a21, (q15_t)0x7a1f, (q15_t)0x7a1d, (q15_t)0x7a1b, (q15_t)0x7a19, (q15_t)0x7a17, (q15_t)0x7a16, + (q15_t)0x7a14, (q15_t)0x7a12, (q15_t)0x7a10, (q15_t)0x7a0e, (q15_t)0x7a0c, (q15_t)0x7a0a, (q15_t)0x7a08, (q15_t)0x7a06, + (q15_t)0x7a04, (q15_t)0x7a03, (q15_t)0x7a01, (q15_t)0x79ff, (q15_t)0x79fd, (q15_t)0x79fb, (q15_t)0x79f9, (q15_t)0x79f7, + (q15_t)0x79f5, (q15_t)0x79f3, (q15_t)0x79f1, (q15_t)0x79f0, (q15_t)0x79ee, (q15_t)0x79ec, (q15_t)0x79ea, (q15_t)0x79e8, + (q15_t)0x79e6, (q15_t)0x79e4, (q15_t)0x79e2, (q15_t)0x79e0, (q15_t)0x79de, (q15_t)0x79dc, (q15_t)0x79da, (q15_t)0x79d9, + (q15_t)0x79d7, (q15_t)0x79d5, (q15_t)0x79d3, (q15_t)0x79d1, (q15_t)0x79cf, (q15_t)0x79cd, (q15_t)0x79cb, (q15_t)0x79c9, + (q15_t)0x79c7, (q15_t)0x79c5, (q15_t)0x79c3, (q15_t)0x79c1, (q15_t)0x79bf, (q15_t)0x79bd, (q15_t)0x79bc, (q15_t)0x79ba, + (q15_t)0x79b8, (q15_t)0x79b6, (q15_t)0x79b4, (q15_t)0x79b2, (q15_t)0x79b0, (q15_t)0x79ae, (q15_t)0x79ac, (q15_t)0x79aa, + (q15_t)0x79a8, (q15_t)0x79a6, (q15_t)0x79a4, (q15_t)0x79a2, (q15_t)0x79a0, (q15_t)0x799e, (q15_t)0x799c, (q15_t)0x799a, + (q15_t)0x7998, (q15_t)0x7996, (q15_t)0x7994, (q15_t)0x7992, (q15_t)0x7991, (q15_t)0x798f, (q15_t)0x798d, (q15_t)0x798b, + (q15_t)0x7989, (q15_t)0x7987, (q15_t)0x7985, (q15_t)0x7983, (q15_t)0x7981, (q15_t)0x797f, (q15_t)0x797d, (q15_t)0x797b, + (q15_t)0x7979, (q15_t)0x7977, (q15_t)0x7975, (q15_t)0x7973, (q15_t)0x7971, (q15_t)0x796f, (q15_t)0x796d, (q15_t)0x796b, + (q15_t)0x7969, (q15_t)0x7967, (q15_t)0x7965, (q15_t)0x7963, (q15_t)0x7961, (q15_t)0x795f, (q15_t)0x795d, (q15_t)0x795b, + (q15_t)0x7959, (q15_t)0x7957, (q15_t)0x7955, (q15_t)0x7953, (q15_t)0x7951, (q15_t)0x794f, (q15_t)0x794d, (q15_t)0x794b, + (q15_t)0x7949, (q15_t)0x7947, (q15_t)0x7945, (q15_t)0x7943, (q15_t)0x7941, (q15_t)0x793f, (q15_t)0x793d, (q15_t)0x793b, + (q15_t)0x7939, (q15_t)0x7937, (q15_t)0x7935, (q15_t)0x7933, (q15_t)0x7931, (q15_t)0x792f, (q15_t)0x792d, (q15_t)0x792b, + (q15_t)0x7929, (q15_t)0x7927, (q15_t)0x7925, (q15_t)0x7923, (q15_t)0x7921, (q15_t)0x791f, (q15_t)0x791d, (q15_t)0x791a, + (q15_t)0x7918, (q15_t)0x7916, (q15_t)0x7914, (q15_t)0x7912, (q15_t)0x7910, (q15_t)0x790e, (q15_t)0x790c, (q15_t)0x790a, + (q15_t)0x7908, (q15_t)0x7906, (q15_t)0x7904, (q15_t)0x7902, (q15_t)0x7900, (q15_t)0x78fe, (q15_t)0x78fc, (q15_t)0x78fa, + (q15_t)0x78f8, (q15_t)0x78f6, (q15_t)0x78f4, (q15_t)0x78f2, (q15_t)0x78f0, (q15_t)0x78ed, (q15_t)0x78eb, (q15_t)0x78e9, + (q15_t)0x78e7, (q15_t)0x78e5, (q15_t)0x78e3, (q15_t)0x78e1, (q15_t)0x78df, (q15_t)0x78dd, (q15_t)0x78db, (q15_t)0x78d9, + (q15_t)0x78d7, (q15_t)0x78d5, (q15_t)0x78d3, (q15_t)0x78d1, (q15_t)0x78ce, (q15_t)0x78cc, (q15_t)0x78ca, (q15_t)0x78c8, + (q15_t)0x78c6, (q15_t)0x78c4, (q15_t)0x78c2, (q15_t)0x78c0, (q15_t)0x78be, (q15_t)0x78bc, (q15_t)0x78ba, (q15_t)0x78b8, + (q15_t)0x78b5, (q15_t)0x78b3, (q15_t)0x78b1, (q15_t)0x78af, (q15_t)0x78ad, (q15_t)0x78ab, (q15_t)0x78a9, (q15_t)0x78a7, + (q15_t)0x78a5, (q15_t)0x78a3, (q15_t)0x78a0, (q15_t)0x789e, (q15_t)0x789c, (q15_t)0x789a, (q15_t)0x7898, (q15_t)0x7896, + (q15_t)0x7894, (q15_t)0x7892, (q15_t)0x7890, (q15_t)0x788e, (q15_t)0x788b, (q15_t)0x7889, (q15_t)0x7887, (q15_t)0x7885, + (q15_t)0x7883, (q15_t)0x7881, (q15_t)0x787f, (q15_t)0x787d, (q15_t)0x787a, (q15_t)0x7878, (q15_t)0x7876, (q15_t)0x7874, + (q15_t)0x7872, (q15_t)0x7870, (q15_t)0x786e, (q15_t)0x786c, (q15_t)0x7869, (q15_t)0x7867, (q15_t)0x7865, (q15_t)0x7863, + (q15_t)0x7861, (q15_t)0x785f, (q15_t)0x785d, (q15_t)0x785b, (q15_t)0x7858, (q15_t)0x7856, (q15_t)0x7854, (q15_t)0x7852, + (q15_t)0x7850, (q15_t)0x784e, (q15_t)0x784c, (q15_t)0x7849, (q15_t)0x7847, (q15_t)0x7845, (q15_t)0x7843, (q15_t)0x7841, + (q15_t)0x783f, (q15_t)0x783c, (q15_t)0x783a, (q15_t)0x7838, (q15_t)0x7836, (q15_t)0x7834, (q15_t)0x7832, (q15_t)0x7830, + (q15_t)0x782d, (q15_t)0x782b, (q15_t)0x7829, (q15_t)0x7827, (q15_t)0x7825, (q15_t)0x7823, (q15_t)0x7820, (q15_t)0x781e, + (q15_t)0x781c, (q15_t)0x781a, (q15_t)0x7818, (q15_t)0x7816, (q15_t)0x7813, (q15_t)0x7811, (q15_t)0x780f, (q15_t)0x780d, + (q15_t)0x780b, (q15_t)0x7808, (q15_t)0x7806, (q15_t)0x7804, (q15_t)0x7802, (q15_t)0x7800, (q15_t)0x77fe, (q15_t)0x77fb, + (q15_t)0x77f9, (q15_t)0x77f7, (q15_t)0x77f5, (q15_t)0x77f3, (q15_t)0x77f0, (q15_t)0x77ee, (q15_t)0x77ec, (q15_t)0x77ea, + (q15_t)0x77e8, (q15_t)0x77e5, (q15_t)0x77e3, (q15_t)0x77e1, (q15_t)0x77df, (q15_t)0x77dd, (q15_t)0x77da, (q15_t)0x77d8, + (q15_t)0x77d6, (q15_t)0x77d4, (q15_t)0x77d2, (q15_t)0x77cf, (q15_t)0x77cd, (q15_t)0x77cb, (q15_t)0x77c9, (q15_t)0x77c6, + (q15_t)0x77c4, (q15_t)0x77c2, (q15_t)0x77c0, (q15_t)0x77be, (q15_t)0x77bb, (q15_t)0x77b9, (q15_t)0x77b7, (q15_t)0x77b5, + (q15_t)0x77b2, (q15_t)0x77b0, (q15_t)0x77ae, (q15_t)0x77ac, (q15_t)0x77aa, (q15_t)0x77a7, (q15_t)0x77a5, (q15_t)0x77a3, + (q15_t)0x77a1, (q15_t)0x779e, (q15_t)0x779c, (q15_t)0x779a, (q15_t)0x7798, (q15_t)0x7795, (q15_t)0x7793, (q15_t)0x7791, + (q15_t)0x778f, (q15_t)0x778c, (q15_t)0x778a, (q15_t)0x7788, (q15_t)0x7786, (q15_t)0x7783, (q15_t)0x7781, (q15_t)0x777f, + (q15_t)0x777d, (q15_t)0x777a, (q15_t)0x7778, (q15_t)0x7776, (q15_t)0x7774, (q15_t)0x7771, (q15_t)0x776f, (q15_t)0x776d, + (q15_t)0x776b, (q15_t)0x7768, (q15_t)0x7766, (q15_t)0x7764, (q15_t)0x7762, (q15_t)0x775f, (q15_t)0x775d, (q15_t)0x775b, + (q15_t)0x7759, (q15_t)0x7756, (q15_t)0x7754, (q15_t)0x7752, (q15_t)0x774f, (q15_t)0x774d, (q15_t)0x774b, (q15_t)0x7749, + (q15_t)0x7746, (q15_t)0x7744, (q15_t)0x7742, (q15_t)0x773f, (q15_t)0x773d, (q15_t)0x773b, (q15_t)0x7739, (q15_t)0x7736, + (q15_t)0x7734, (q15_t)0x7732, (q15_t)0x772f, (q15_t)0x772d, (q15_t)0x772b, (q15_t)0x7729, (q15_t)0x7726, (q15_t)0x7724, + (q15_t)0x7722, (q15_t)0x771f, (q15_t)0x771d, (q15_t)0x771b, (q15_t)0x7719, (q15_t)0x7716, (q15_t)0x7714, (q15_t)0x7712, + (q15_t)0x770f, (q15_t)0x770d, (q15_t)0x770b, (q15_t)0x7708, (q15_t)0x7706, (q15_t)0x7704, (q15_t)0x7701, (q15_t)0x76ff, + (q15_t)0x76fd, (q15_t)0x76fa, (q15_t)0x76f8, (q15_t)0x76f6, (q15_t)0x76f4, (q15_t)0x76f1, (q15_t)0x76ef, (q15_t)0x76ed, + (q15_t)0x76ea, (q15_t)0x76e8, (q15_t)0x76e6, (q15_t)0x76e3, (q15_t)0x76e1, (q15_t)0x76df, (q15_t)0x76dc, (q15_t)0x76da, + (q15_t)0x76d8, (q15_t)0x76d5, (q15_t)0x76d3, (q15_t)0x76d1, (q15_t)0x76ce, (q15_t)0x76cc, (q15_t)0x76ca, (q15_t)0x76c7, + (q15_t)0x76c5, (q15_t)0x76c3, (q15_t)0x76c0, (q15_t)0x76be, (q15_t)0x76bc, (q15_t)0x76b9, (q15_t)0x76b7, (q15_t)0x76b4, + (q15_t)0x76b2, (q15_t)0x76b0, (q15_t)0x76ad, (q15_t)0x76ab, (q15_t)0x76a9, (q15_t)0x76a6, (q15_t)0x76a4, (q15_t)0x76a2, + (q15_t)0x769f, (q15_t)0x769d, (q15_t)0x769b, (q15_t)0x7698, (q15_t)0x7696, (q15_t)0x7693, (q15_t)0x7691, (q15_t)0x768f, + (q15_t)0x768c, (q15_t)0x768a, (q15_t)0x7688, (q15_t)0x7685, (q15_t)0x7683, (q15_t)0x7681, (q15_t)0x767e, (q15_t)0x767c, + (q15_t)0x7679, (q15_t)0x7677, (q15_t)0x7675, (q15_t)0x7672, (q15_t)0x7670, (q15_t)0x766d, (q15_t)0x766b, (q15_t)0x7669, + (q15_t)0x7666, (q15_t)0x7664, (q15_t)0x7662, (q15_t)0x765f, (q15_t)0x765d, (q15_t)0x765a, (q15_t)0x7658, (q15_t)0x7656, + (q15_t)0x7653, (q15_t)0x7651, (q15_t)0x764e, (q15_t)0x764c, (q15_t)0x764a, (q15_t)0x7647, (q15_t)0x7645, (q15_t)0x7642, + (q15_t)0x7640, (q15_t)0x763e, (q15_t)0x763b, (q15_t)0x7639, (q15_t)0x7636, (q15_t)0x7634, (q15_t)0x7632, (q15_t)0x762f, + (q15_t)0x762d, (q15_t)0x762a, (q15_t)0x7628, (q15_t)0x7625, (q15_t)0x7623, (q15_t)0x7621, (q15_t)0x761e, (q15_t)0x761c, + (q15_t)0x7619, (q15_t)0x7617, (q15_t)0x7615, (q15_t)0x7612, (q15_t)0x7610, (q15_t)0x760d, (q15_t)0x760b, (q15_t)0x7608, + (q15_t)0x7606, (q15_t)0x7604, (q15_t)0x7601, (q15_t)0x75ff, (q15_t)0x75fc, (q15_t)0x75fa, (q15_t)0x75f7, (q15_t)0x75f5, + (q15_t)0x75f2, (q15_t)0x75f0, (q15_t)0x75ee, (q15_t)0x75eb, (q15_t)0x75e9, (q15_t)0x75e6, (q15_t)0x75e4, (q15_t)0x75e1, + (q15_t)0x75df, (q15_t)0x75dc, (q15_t)0x75da, (q15_t)0x75d8, (q15_t)0x75d5, (q15_t)0x75d3, (q15_t)0x75d0, (q15_t)0x75ce, + (q15_t)0x75cb, (q15_t)0x75c9, (q15_t)0x75c6, (q15_t)0x75c4, (q15_t)0x75c1, (q15_t)0x75bf, (q15_t)0x75bc, (q15_t)0x75ba, + (q15_t)0x75b8, (q15_t)0x75b5, (q15_t)0x75b3, (q15_t)0x75b0, (q15_t)0x75ae, (q15_t)0x75ab, (q15_t)0x75a9, (q15_t)0x75a6, + (q15_t)0x75a4, (q15_t)0x75a1, (q15_t)0x759f, (q15_t)0x759c, (q15_t)0x759a, (q15_t)0x7597, (q15_t)0x7595, (q15_t)0x7592, + (q15_t)0x7590, (q15_t)0x758d, (q15_t)0x758b, (q15_t)0x7588, (q15_t)0x7586, (q15_t)0x7584, (q15_t)0x7581, (q15_t)0x757f, + (q15_t)0x757c, (q15_t)0x757a, (q15_t)0x7577, (q15_t)0x7575, (q15_t)0x7572, (q15_t)0x7570, (q15_t)0x756d, (q15_t)0x756b, + (q15_t)0x7568, (q15_t)0x7566, (q15_t)0x7563, (q15_t)0x7561, (q15_t)0x755e, (q15_t)0x755c, (q15_t)0x7559, (q15_t)0x7556, + (q15_t)0x7554, (q15_t)0x7551, (q15_t)0x754f, (q15_t)0x754c, (q15_t)0x754a, (q15_t)0x7547, (q15_t)0x7545, (q15_t)0x7542, + (q15_t)0x7540, (q15_t)0x753d, (q15_t)0x753b, (q15_t)0x7538, (q15_t)0x7536, (q15_t)0x7533, (q15_t)0x7531, (q15_t)0x752e, + (q15_t)0x752c, (q15_t)0x7529, (q15_t)0x7527, (q15_t)0x7524, (q15_t)0x7522, (q15_t)0x751f, (q15_t)0x751c, (q15_t)0x751a, + (q15_t)0x7517, (q15_t)0x7515, (q15_t)0x7512, (q15_t)0x7510, (q15_t)0x750d, (q15_t)0x750b, (q15_t)0x7508, (q15_t)0x7506, + (q15_t)0x7503, (q15_t)0x7501, (q15_t)0x74fe, (q15_t)0x74fb, (q15_t)0x74f9, (q15_t)0x74f6, (q15_t)0x74f4, (q15_t)0x74f1, + (q15_t)0x74ef, (q15_t)0x74ec, (q15_t)0x74ea, (q15_t)0x74e7, (q15_t)0x74e4, (q15_t)0x74e2, (q15_t)0x74df, (q15_t)0x74dd, + (q15_t)0x74da, (q15_t)0x74d8, (q15_t)0x74d5, (q15_t)0x74d2, (q15_t)0x74d0, (q15_t)0x74cd, (q15_t)0x74cb, (q15_t)0x74c8, + (q15_t)0x74c6, (q15_t)0x74c3, (q15_t)0x74c0, (q15_t)0x74be, (q15_t)0x74bb, (q15_t)0x74b9, (q15_t)0x74b6, (q15_t)0x74b4, + (q15_t)0x74b1, (q15_t)0x74ae, (q15_t)0x74ac, (q15_t)0x74a9, (q15_t)0x74a7, (q15_t)0x74a4, (q15_t)0x74a1, (q15_t)0x749f, + (q15_t)0x749c, (q15_t)0x749a, (q15_t)0x7497, (q15_t)0x7495, (q15_t)0x7492, (q15_t)0x748f, (q15_t)0x748d, (q15_t)0x748a, + (q15_t)0x7488, (q15_t)0x7485, (q15_t)0x7482, (q15_t)0x7480, (q15_t)0x747d, (q15_t)0x747b, (q15_t)0x7478, (q15_t)0x7475, + (q15_t)0x7473, (q15_t)0x7470, (q15_t)0x746d, (q15_t)0x746b, (q15_t)0x7468, (q15_t)0x7466, (q15_t)0x7463, (q15_t)0x7460, + (q15_t)0x745e, (q15_t)0x745b, (q15_t)0x7459, (q15_t)0x7456, (q15_t)0x7453, (q15_t)0x7451, (q15_t)0x744e, (q15_t)0x744b, + (q15_t)0x7449, (q15_t)0x7446, (q15_t)0x7444, (q15_t)0x7441, (q15_t)0x743e, (q15_t)0x743c, (q15_t)0x7439, (q15_t)0x7436, + (q15_t)0x7434, (q15_t)0x7431, (q15_t)0x742f, (q15_t)0x742c, (q15_t)0x7429, (q15_t)0x7427, (q15_t)0x7424, (q15_t)0x7421, + (q15_t)0x741f, (q15_t)0x741c, (q15_t)0x7419, (q15_t)0x7417, (q15_t)0x7414, (q15_t)0x7411, (q15_t)0x740f, (q15_t)0x740c, + (q15_t)0x740a, (q15_t)0x7407, (q15_t)0x7404, (q15_t)0x7402, (q15_t)0x73ff, (q15_t)0x73fc, (q15_t)0x73fa, (q15_t)0x73f7, + (q15_t)0x73f4, (q15_t)0x73f2, (q15_t)0x73ef, (q15_t)0x73ec, (q15_t)0x73ea, (q15_t)0x73e7, (q15_t)0x73e4, (q15_t)0x73e2, + (q15_t)0x73df, (q15_t)0x73dc, (q15_t)0x73da, (q15_t)0x73d7, (q15_t)0x73d4, (q15_t)0x73d2, (q15_t)0x73cf, (q15_t)0x73cc, + (q15_t)0x73ca, (q15_t)0x73c7, (q15_t)0x73c4, (q15_t)0x73c1, (q15_t)0x73bf, (q15_t)0x73bc, (q15_t)0x73b9, (q15_t)0x73b7, + (q15_t)0x73b4, (q15_t)0x73b1, (q15_t)0x73af, (q15_t)0x73ac, (q15_t)0x73a9, (q15_t)0x73a7, (q15_t)0x73a4, (q15_t)0x73a1, + (q15_t)0x739f, (q15_t)0x739c, (q15_t)0x7399, (q15_t)0x7396, (q15_t)0x7394, (q15_t)0x7391, (q15_t)0x738e, (q15_t)0x738c, + (q15_t)0x7389, (q15_t)0x7386, (q15_t)0x7384, (q15_t)0x7381, (q15_t)0x737e, (q15_t)0x737b, (q15_t)0x7379, (q15_t)0x7376, + (q15_t)0x7373, (q15_t)0x7371, (q15_t)0x736e, (q15_t)0x736b, (q15_t)0x7368, (q15_t)0x7366, (q15_t)0x7363, (q15_t)0x7360, + (q15_t)0x735e, (q15_t)0x735b, (q15_t)0x7358, (q15_t)0x7355, (q15_t)0x7353, (q15_t)0x7350, (q15_t)0x734d, (q15_t)0x734a, + (q15_t)0x7348, (q15_t)0x7345, (q15_t)0x7342, (q15_t)0x7340, (q15_t)0x733d, (q15_t)0x733a, (q15_t)0x7337, (q15_t)0x7335, + (q15_t)0x7332, (q15_t)0x732f, (q15_t)0x732c, (q15_t)0x732a, (q15_t)0x7327, (q15_t)0x7324, (q15_t)0x7321, (q15_t)0x731f, + (q15_t)0x731c, (q15_t)0x7319, (q15_t)0x7316, (q15_t)0x7314, (q15_t)0x7311, (q15_t)0x730e, (q15_t)0x730b, (q15_t)0x7309, + (q15_t)0x7306, (q15_t)0x7303, (q15_t)0x7300, (q15_t)0x72fe, (q15_t)0x72fb, (q15_t)0x72f8, (q15_t)0x72f5, (q15_t)0x72f3, + (q15_t)0x72f0, (q15_t)0x72ed, (q15_t)0x72ea, (q15_t)0x72e8, (q15_t)0x72e5, (q15_t)0x72e2, (q15_t)0x72df, (q15_t)0x72dc, + (q15_t)0x72da, (q15_t)0x72d7, (q15_t)0x72d4, (q15_t)0x72d1, (q15_t)0x72cf, (q15_t)0x72cc, (q15_t)0x72c9, (q15_t)0x72c6, + (q15_t)0x72c3, (q15_t)0x72c1, (q15_t)0x72be, (q15_t)0x72bb, (q15_t)0x72b8, (q15_t)0x72b5, (q15_t)0x72b3, (q15_t)0x72b0, + (q15_t)0x72ad, (q15_t)0x72aa, (q15_t)0x72a8, (q15_t)0x72a5, (q15_t)0x72a2, (q15_t)0x729f, (q15_t)0x729c, (q15_t)0x729a, + (q15_t)0x7297, (q15_t)0x7294, (q15_t)0x7291, (q15_t)0x728e, (q15_t)0x728c, (q15_t)0x7289, (q15_t)0x7286, (q15_t)0x7283, + (q15_t)0x7280, (q15_t)0x727e, (q15_t)0x727b, (q15_t)0x7278, (q15_t)0x7275, (q15_t)0x7272, (q15_t)0x726f, (q15_t)0x726d, + (q15_t)0x726a, (q15_t)0x7267, (q15_t)0x7264, (q15_t)0x7261, (q15_t)0x725f, (q15_t)0x725c, (q15_t)0x7259, (q15_t)0x7256, + (q15_t)0x7253, (q15_t)0x7250, (q15_t)0x724e, (q15_t)0x724b, (q15_t)0x7248, (q15_t)0x7245, (q15_t)0x7242, (q15_t)0x723f, + (q15_t)0x723d, (q15_t)0x723a, (q15_t)0x7237, (q15_t)0x7234, (q15_t)0x7231, (q15_t)0x722e, (q15_t)0x722c, (q15_t)0x7229, + (q15_t)0x7226, (q15_t)0x7223, (q15_t)0x7220, (q15_t)0x721d, (q15_t)0x721b, (q15_t)0x7218, (q15_t)0x7215, (q15_t)0x7212, + (q15_t)0x720f, (q15_t)0x720c, (q15_t)0x7209, (q15_t)0x7207, (q15_t)0x7204, (q15_t)0x7201, (q15_t)0x71fe, (q15_t)0x71fb, + (q15_t)0x71f8, (q15_t)0x71f5, (q15_t)0x71f3, (q15_t)0x71f0, (q15_t)0x71ed, (q15_t)0x71ea, (q15_t)0x71e7, (q15_t)0x71e4, + (q15_t)0x71e1, (q15_t)0x71df, (q15_t)0x71dc, (q15_t)0x71d9, (q15_t)0x71d6, (q15_t)0x71d3, (q15_t)0x71d0, (q15_t)0x71cd, + (q15_t)0x71ca, (q15_t)0x71c8, (q15_t)0x71c5, (q15_t)0x71c2, (q15_t)0x71bf, (q15_t)0x71bc, (q15_t)0x71b9, (q15_t)0x71b6, + (q15_t)0x71b3, (q15_t)0x71b0, (q15_t)0x71ae, (q15_t)0x71ab, (q15_t)0x71a8, (q15_t)0x71a5, (q15_t)0x71a2, (q15_t)0x719f, + (q15_t)0x719c, (q15_t)0x7199, (q15_t)0x7196, (q15_t)0x7194, (q15_t)0x7191, (q15_t)0x718e, (q15_t)0x718b, (q15_t)0x7188, + (q15_t)0x7185, (q15_t)0x7182, (q15_t)0x717f, (q15_t)0x717c, (q15_t)0x7179, (q15_t)0x7177, (q15_t)0x7174, (q15_t)0x7171, + (q15_t)0x716e, (q15_t)0x716b, (q15_t)0x7168, (q15_t)0x7165, (q15_t)0x7162, (q15_t)0x715f, (q15_t)0x715c, (q15_t)0x7159, + (q15_t)0x7156, (q15_t)0x7154, (q15_t)0x7151, (q15_t)0x714e, (q15_t)0x714b, (q15_t)0x7148, (q15_t)0x7145, (q15_t)0x7142, + (q15_t)0x713f, (q15_t)0x713c, (q15_t)0x7139, (q15_t)0x7136, (q15_t)0x7133, (q15_t)0x7130, (q15_t)0x712d, (q15_t)0x712b, + (q15_t)0x7128, (q15_t)0x7125, (q15_t)0x7122, (q15_t)0x711f, (q15_t)0x711c, (q15_t)0x7119, (q15_t)0x7116, (q15_t)0x7113, + (q15_t)0x7110, (q15_t)0x710d, (q15_t)0x710a, (q15_t)0x7107, (q15_t)0x7104, (q15_t)0x7101, (q15_t)0x70fe, (q15_t)0x70fb, + (q15_t)0x70f8, (q15_t)0x70f6, (q15_t)0x70f3, (q15_t)0x70f0, (q15_t)0x70ed, (q15_t)0x70ea, (q15_t)0x70e7, (q15_t)0x70e4, + (q15_t)0x70e1, (q15_t)0x70de, (q15_t)0x70db, (q15_t)0x70d8, (q15_t)0x70d5, (q15_t)0x70d2, (q15_t)0x70cf, (q15_t)0x70cc, + (q15_t)0x70c9, (q15_t)0x70c6, (q15_t)0x70c3, (q15_t)0x70c0, (q15_t)0x70bd, (q15_t)0x70ba, (q15_t)0x70b7, (q15_t)0x70b4, + (q15_t)0x70b1, (q15_t)0x70ae, (q15_t)0x70ab, (q15_t)0x70a8, (q15_t)0x70a5, (q15_t)0x70a2, (q15_t)0x709f, (q15_t)0x709c, + (q15_t)0x7099, (q15_t)0x7096, (q15_t)0x7093, (q15_t)0x7090, (q15_t)0x708d, (q15_t)0x708a, (q15_t)0x7087, (q15_t)0x7084, + (q15_t)0x7081, (q15_t)0x707e, (q15_t)0x707b, (q15_t)0x7078, (q15_t)0x7075, (q15_t)0x7072, (q15_t)0x706f, (q15_t)0x706c, + (q15_t)0x7069, (q15_t)0x7066, (q15_t)0x7063, (q15_t)0x7060, (q15_t)0x705d, (q15_t)0x705a, (q15_t)0x7057, (q15_t)0x7054, + (q15_t)0x7051, (q15_t)0x704e, (q15_t)0x704b, (q15_t)0x7048, (q15_t)0x7045, (q15_t)0x7042, (q15_t)0x703f, (q15_t)0x703c, + (q15_t)0x7039, (q15_t)0x7036, (q15_t)0x7033, (q15_t)0x7030, (q15_t)0x702d, (q15_t)0x702a, (q15_t)0x7027, (q15_t)0x7024, + (q15_t)0x7021, (q15_t)0x701e, (q15_t)0x701b, (q15_t)0x7018, (q15_t)0x7015, (q15_t)0x7012, (q15_t)0x700f, (q15_t)0x700c, + (q15_t)0x7009, (q15_t)0x7006, (q15_t)0x7003, (q15_t)0x7000, (q15_t)0x6ffd, (q15_t)0x6ffa, (q15_t)0x6ff7, (q15_t)0x6ff3, + (q15_t)0x6ff0, (q15_t)0x6fed, (q15_t)0x6fea, (q15_t)0x6fe7, (q15_t)0x6fe4, (q15_t)0x6fe1, (q15_t)0x6fde, (q15_t)0x6fdb, + (q15_t)0x6fd8, (q15_t)0x6fd5, (q15_t)0x6fd2, (q15_t)0x6fcf, (q15_t)0x6fcc, (q15_t)0x6fc9, (q15_t)0x6fc6, (q15_t)0x6fc3, + (q15_t)0x6fc0, (q15_t)0x6fbc, (q15_t)0x6fb9, (q15_t)0x6fb6, (q15_t)0x6fb3, (q15_t)0x6fb0, (q15_t)0x6fad, (q15_t)0x6faa, + (q15_t)0x6fa7, (q15_t)0x6fa4, (q15_t)0x6fa1, (q15_t)0x6f9e, (q15_t)0x6f9b, (q15_t)0x6f98, (q15_t)0x6f95, (q15_t)0x6f91, + (q15_t)0x6f8e, (q15_t)0x6f8b, (q15_t)0x6f88, (q15_t)0x6f85, (q15_t)0x6f82, (q15_t)0x6f7f, (q15_t)0x6f7c, (q15_t)0x6f79, + (q15_t)0x6f76, (q15_t)0x6f73, (q15_t)0x6f70, (q15_t)0x6f6c, (q15_t)0x6f69, (q15_t)0x6f66, (q15_t)0x6f63, (q15_t)0x6f60, + (q15_t)0x6f5d, (q15_t)0x6f5a, (q15_t)0x6f57, (q15_t)0x6f54, (q15_t)0x6f51, (q15_t)0x6f4d, (q15_t)0x6f4a, (q15_t)0x6f47, + (q15_t)0x6f44, (q15_t)0x6f41, (q15_t)0x6f3e, (q15_t)0x6f3b, (q15_t)0x6f38, (q15_t)0x6f35, (q15_t)0x6f31, (q15_t)0x6f2e, + (q15_t)0x6f2b, (q15_t)0x6f28, (q15_t)0x6f25, (q15_t)0x6f22, (q15_t)0x6f1f, (q15_t)0x6f1c, (q15_t)0x6f19, (q15_t)0x6f15, + (q15_t)0x6f12, (q15_t)0x6f0f, (q15_t)0x6f0c, (q15_t)0x6f09, (q15_t)0x6f06, (q15_t)0x6f03, (q15_t)0x6f00, (q15_t)0x6efc, + (q15_t)0x6ef9, (q15_t)0x6ef6, (q15_t)0x6ef3, (q15_t)0x6ef0, (q15_t)0x6eed, (q15_t)0x6eea, (q15_t)0x6ee7, (q15_t)0x6ee3, + (q15_t)0x6ee0, (q15_t)0x6edd, (q15_t)0x6eda, (q15_t)0x6ed7, (q15_t)0x6ed4, (q15_t)0x6ed1, (q15_t)0x6ecd, (q15_t)0x6eca, + (q15_t)0x6ec7, (q15_t)0x6ec4, (q15_t)0x6ec1, (q15_t)0x6ebe, (q15_t)0x6eba, (q15_t)0x6eb7, (q15_t)0x6eb4, (q15_t)0x6eb1, + (q15_t)0x6eae, (q15_t)0x6eab, (q15_t)0x6ea8, (q15_t)0x6ea4, (q15_t)0x6ea1, (q15_t)0x6e9e, (q15_t)0x6e9b, (q15_t)0x6e98, + (q15_t)0x6e95, (q15_t)0x6e91, (q15_t)0x6e8e, (q15_t)0x6e8b, (q15_t)0x6e88, (q15_t)0x6e85, (q15_t)0x6e82, (q15_t)0x6e7e, + (q15_t)0x6e7b, (q15_t)0x6e78, (q15_t)0x6e75, (q15_t)0x6e72, (q15_t)0x6e6f, (q15_t)0x6e6b, (q15_t)0x6e68, (q15_t)0x6e65, + (q15_t)0x6e62, (q15_t)0x6e5f, (q15_t)0x6e5b, (q15_t)0x6e58, (q15_t)0x6e55, (q15_t)0x6e52, (q15_t)0x6e4f, (q15_t)0x6e4c, + (q15_t)0x6e48, (q15_t)0x6e45, (q15_t)0x6e42, (q15_t)0x6e3f, (q15_t)0x6e3c, (q15_t)0x6e38, (q15_t)0x6e35, (q15_t)0x6e32, + (q15_t)0x6e2f, (q15_t)0x6e2c, (q15_t)0x6e28, (q15_t)0x6e25, (q15_t)0x6e22, (q15_t)0x6e1f, (q15_t)0x6e1c, (q15_t)0x6e18, + (q15_t)0x6e15, (q15_t)0x6e12, (q15_t)0x6e0f, (q15_t)0x6e0c, (q15_t)0x6e08, (q15_t)0x6e05, (q15_t)0x6e02, (q15_t)0x6dff, + (q15_t)0x6dfb, (q15_t)0x6df8, (q15_t)0x6df5, (q15_t)0x6df2, (q15_t)0x6def, (q15_t)0x6deb, (q15_t)0x6de8, (q15_t)0x6de5, + (q15_t)0x6de2, (q15_t)0x6ddf, (q15_t)0x6ddb, (q15_t)0x6dd8, (q15_t)0x6dd5, (q15_t)0x6dd2, (q15_t)0x6dce, (q15_t)0x6dcb, + (q15_t)0x6dc8, (q15_t)0x6dc5, (q15_t)0x6dc1, (q15_t)0x6dbe, (q15_t)0x6dbb, (q15_t)0x6db8, (q15_t)0x6db5, (q15_t)0x6db1, + (q15_t)0x6dae, (q15_t)0x6dab, (q15_t)0x6da8, (q15_t)0x6da4, (q15_t)0x6da1, (q15_t)0x6d9e, (q15_t)0x6d9b, (q15_t)0x6d97, + (q15_t)0x6d94, (q15_t)0x6d91, (q15_t)0x6d8e, (q15_t)0x6d8a, (q15_t)0x6d87, (q15_t)0x6d84, (q15_t)0x6d81, (q15_t)0x6d7d, + (q15_t)0x6d7a, (q15_t)0x6d77, (q15_t)0x6d74, (q15_t)0x6d70, (q15_t)0x6d6d, (q15_t)0x6d6a, (q15_t)0x6d67, (q15_t)0x6d63, + (q15_t)0x6d60, (q15_t)0x6d5d, (q15_t)0x6d59, (q15_t)0x6d56, (q15_t)0x6d53, (q15_t)0x6d50, (q15_t)0x6d4c, (q15_t)0x6d49, + (q15_t)0x6d46, (q15_t)0x6d43, (q15_t)0x6d3f, (q15_t)0x6d3c, (q15_t)0x6d39, (q15_t)0x6d36, (q15_t)0x6d32, (q15_t)0x6d2f, + (q15_t)0x6d2c, (q15_t)0x6d28, (q15_t)0x6d25, (q15_t)0x6d22, (q15_t)0x6d1f, (q15_t)0x6d1b, (q15_t)0x6d18, (q15_t)0x6d15, + (q15_t)0x6d11, (q15_t)0x6d0e, (q15_t)0x6d0b, (q15_t)0x6d08, (q15_t)0x6d04, (q15_t)0x6d01, (q15_t)0x6cfe, (q15_t)0x6cfa, + (q15_t)0x6cf7, (q15_t)0x6cf4, (q15_t)0x6cf0, (q15_t)0x6ced, (q15_t)0x6cea, (q15_t)0x6ce7, (q15_t)0x6ce3, (q15_t)0x6ce0, + (q15_t)0x6cdd, (q15_t)0x6cd9, (q15_t)0x6cd6, (q15_t)0x6cd3, (q15_t)0x6ccf, (q15_t)0x6ccc, (q15_t)0x6cc9, (q15_t)0x6cc5, + (q15_t)0x6cc2, (q15_t)0x6cbf, (q15_t)0x6cbc, (q15_t)0x6cb8, (q15_t)0x6cb5, (q15_t)0x6cb2, (q15_t)0x6cae, (q15_t)0x6cab, + (q15_t)0x6ca8, (q15_t)0x6ca4, (q15_t)0x6ca1, (q15_t)0x6c9e, (q15_t)0x6c9a, (q15_t)0x6c97, (q15_t)0x6c94, (q15_t)0x6c90, + (q15_t)0x6c8d, (q15_t)0x6c8a, (q15_t)0x6c86, (q15_t)0x6c83, (q15_t)0x6c80, (q15_t)0x6c7c, (q15_t)0x6c79, (q15_t)0x6c76, + (q15_t)0x6c72, (q15_t)0x6c6f, (q15_t)0x6c6c, (q15_t)0x6c68, (q15_t)0x6c65, (q15_t)0x6c62, (q15_t)0x6c5e, (q15_t)0x6c5b, + (q15_t)0x6c58, (q15_t)0x6c54, (q15_t)0x6c51, (q15_t)0x6c4e, (q15_t)0x6c4a, (q15_t)0x6c47, (q15_t)0x6c44, (q15_t)0x6c40, + (q15_t)0x6c3d, (q15_t)0x6c39, (q15_t)0x6c36, (q15_t)0x6c33, (q15_t)0x6c2f, (q15_t)0x6c2c, (q15_t)0x6c29, (q15_t)0x6c25, + (q15_t)0x6c22, (q15_t)0x6c1f, (q15_t)0x6c1b, (q15_t)0x6c18, (q15_t)0x6c15, (q15_t)0x6c11, (q15_t)0x6c0e, (q15_t)0x6c0a, + (q15_t)0x6c07, (q15_t)0x6c04, (q15_t)0x6c00, (q15_t)0x6bfd, (q15_t)0x6bfa, (q15_t)0x6bf6, (q15_t)0x6bf3, (q15_t)0x6bef, + (q15_t)0x6bec, (q15_t)0x6be9, (q15_t)0x6be5, (q15_t)0x6be2, (q15_t)0x6bdf, (q15_t)0x6bdb, (q15_t)0x6bd8, (q15_t)0x6bd4, + (q15_t)0x6bd1, (q15_t)0x6bce, (q15_t)0x6bca, (q15_t)0x6bc7, (q15_t)0x6bc3, (q15_t)0x6bc0, (q15_t)0x6bbd, (q15_t)0x6bb9, + (q15_t)0x6bb6, (q15_t)0x6bb2, (q15_t)0x6baf, (q15_t)0x6bac, (q15_t)0x6ba8, (q15_t)0x6ba5, (q15_t)0x6ba1, (q15_t)0x6b9e, + (q15_t)0x6b9b, (q15_t)0x6b97, (q15_t)0x6b94, (q15_t)0x6b90, (q15_t)0x6b8d, (q15_t)0x6b8a, (q15_t)0x6b86, (q15_t)0x6b83, + (q15_t)0x6b7f, (q15_t)0x6b7c, (q15_t)0x6b79, (q15_t)0x6b75, (q15_t)0x6b72, (q15_t)0x6b6e, (q15_t)0x6b6b, (q15_t)0x6b68, + (q15_t)0x6b64, (q15_t)0x6b61, (q15_t)0x6b5d, (q15_t)0x6b5a, (q15_t)0x6b56, (q15_t)0x6b53, (q15_t)0x6b50, (q15_t)0x6b4c, + (q15_t)0x6b49, (q15_t)0x6b45, (q15_t)0x6b42, (q15_t)0x6b3e, (q15_t)0x6b3b, (q15_t)0x6b38, (q15_t)0x6b34, (q15_t)0x6b31, + (q15_t)0x6b2d, (q15_t)0x6b2a, (q15_t)0x6b26, (q15_t)0x6b23, (q15_t)0x6b20, (q15_t)0x6b1c, (q15_t)0x6b19, (q15_t)0x6b15, + (q15_t)0x6b12, (q15_t)0x6b0e, (q15_t)0x6b0b, (q15_t)0x6b07, (q15_t)0x6b04, (q15_t)0x6b01, (q15_t)0x6afd, (q15_t)0x6afa, + (q15_t)0x6af6, (q15_t)0x6af3, (q15_t)0x6aef, (q15_t)0x6aec, (q15_t)0x6ae8, (q15_t)0x6ae5, (q15_t)0x6ae1, (q15_t)0x6ade, + (q15_t)0x6adb, (q15_t)0x6ad7, (q15_t)0x6ad4, (q15_t)0x6ad0, (q15_t)0x6acd, (q15_t)0x6ac9, (q15_t)0x6ac6, (q15_t)0x6ac2, + (q15_t)0x6abf, (q15_t)0x6abb, (q15_t)0x6ab8, (q15_t)0x6ab4, (q15_t)0x6ab1, (q15_t)0x6aae, (q15_t)0x6aaa, (q15_t)0x6aa7, + (q15_t)0x6aa3, (q15_t)0x6aa0, (q15_t)0x6a9c, (q15_t)0x6a99, (q15_t)0x6a95, (q15_t)0x6a92, (q15_t)0x6a8e, (q15_t)0x6a8b, + (q15_t)0x6a87, (q15_t)0x6a84, (q15_t)0x6a80, (q15_t)0x6a7d, (q15_t)0x6a79, (q15_t)0x6a76, (q15_t)0x6a72, (q15_t)0x6a6f, + (q15_t)0x6a6b, (q15_t)0x6a68, (q15_t)0x6a64, (q15_t)0x6a61, (q15_t)0x6a5d, (q15_t)0x6a5a, (q15_t)0x6a56, (q15_t)0x6a53, + (q15_t)0x6a4f, (q15_t)0x6a4c, (q15_t)0x6a48, (q15_t)0x6a45, (q15_t)0x6a41, (q15_t)0x6a3e, (q15_t)0x6a3a, (q15_t)0x6a37, + (q15_t)0x6a33, (q15_t)0x6a30, (q15_t)0x6a2c, (q15_t)0x6a29, (q15_t)0x6a25, (q15_t)0x6a22, (q15_t)0x6a1e, (q15_t)0x6a1b, + (q15_t)0x6a17, (q15_t)0x6a14, (q15_t)0x6a10, (q15_t)0x6a0d, (q15_t)0x6a09, (q15_t)0x6a06, (q15_t)0x6a02, (q15_t)0x69ff, + (q15_t)0x69fb, (q15_t)0x69f8, (q15_t)0x69f4, (q15_t)0x69f1, (q15_t)0x69ed, (q15_t)0x69e9, (q15_t)0x69e6, (q15_t)0x69e2, + (q15_t)0x69df, (q15_t)0x69db, (q15_t)0x69d8, (q15_t)0x69d4, (q15_t)0x69d1, (q15_t)0x69cd, (q15_t)0x69ca, (q15_t)0x69c6, + (q15_t)0x69c3, (q15_t)0x69bf, (q15_t)0x69bc, (q15_t)0x69b8, (q15_t)0x69b4, (q15_t)0x69b1, (q15_t)0x69ad, (q15_t)0x69aa, + (q15_t)0x69a6, (q15_t)0x69a3, (q15_t)0x699f, (q15_t)0x699c, (q15_t)0x6998, (q15_t)0x6995, (q15_t)0x6991, (q15_t)0x698d, + (q15_t)0x698a, (q15_t)0x6986, (q15_t)0x6983, (q15_t)0x697f, (q15_t)0x697c, (q15_t)0x6978, (q15_t)0x6975, (q15_t)0x6971, + (q15_t)0x696d, (q15_t)0x696a, (q15_t)0x6966, (q15_t)0x6963, (q15_t)0x695f, (q15_t)0x695c, (q15_t)0x6958, (q15_t)0x6954, + (q15_t)0x6951, (q15_t)0x694d, (q15_t)0x694a, (q15_t)0x6946, (q15_t)0x6943, (q15_t)0x693f, (q15_t)0x693b, (q15_t)0x6938, + (q15_t)0x6934, (q15_t)0x6931, (q15_t)0x692d, (q15_t)0x692a, (q15_t)0x6926, (q15_t)0x6922, (q15_t)0x691f, (q15_t)0x691b, + (q15_t)0x6918, (q15_t)0x6914, (q15_t)0x6910, (q15_t)0x690d, (q15_t)0x6909, (q15_t)0x6906, (q15_t)0x6902, (q15_t)0x68fe, + (q15_t)0x68fb, (q15_t)0x68f7, (q15_t)0x68f4, (q15_t)0x68f0, (q15_t)0x68ec, (q15_t)0x68e9, (q15_t)0x68e5, (q15_t)0x68e2, + (q15_t)0x68de, (q15_t)0x68da, (q15_t)0x68d7, (q15_t)0x68d3, (q15_t)0x68d0, (q15_t)0x68cc, (q15_t)0x68c8, (q15_t)0x68c5, + (q15_t)0x68c1, (q15_t)0x68be, (q15_t)0x68ba, (q15_t)0x68b6, (q15_t)0x68b3, (q15_t)0x68af, (q15_t)0x68ac, (q15_t)0x68a8, + (q15_t)0x68a4, (q15_t)0x68a1, (q15_t)0x689d, (q15_t)0x6899, (q15_t)0x6896, (q15_t)0x6892, (q15_t)0x688f, (q15_t)0x688b, + (q15_t)0x6887, (q15_t)0x6884, (q15_t)0x6880, (q15_t)0x687c, (q15_t)0x6879, (q15_t)0x6875, (q15_t)0x6872, (q15_t)0x686e, + (q15_t)0x686a, (q15_t)0x6867, (q15_t)0x6863, (q15_t)0x685f, (q15_t)0x685c, (q15_t)0x6858, (q15_t)0x6854, (q15_t)0x6851, + (q15_t)0x684d, (q15_t)0x684a, (q15_t)0x6846, (q15_t)0x6842, (q15_t)0x683f, (q15_t)0x683b, (q15_t)0x6837, (q15_t)0x6834, + (q15_t)0x6830, (q15_t)0x682c, (q15_t)0x6829, (q15_t)0x6825, (q15_t)0x6821, (q15_t)0x681e, (q15_t)0x681a, (q15_t)0x6816, + (q15_t)0x6813, (q15_t)0x680f, (q15_t)0x680b, (q15_t)0x6808, (q15_t)0x6804, (q15_t)0x6800, (q15_t)0x67fd, (q15_t)0x67f9, + (q15_t)0x67f5, (q15_t)0x67f2, (q15_t)0x67ee, (q15_t)0x67ea, (q15_t)0x67e7, (q15_t)0x67e3, (q15_t)0x67df, (q15_t)0x67dc, + (q15_t)0x67d8, (q15_t)0x67d4, (q15_t)0x67d1, (q15_t)0x67cd, (q15_t)0x67c9, (q15_t)0x67c6, (q15_t)0x67c2, (q15_t)0x67be, + (q15_t)0x67bb, (q15_t)0x67b7, (q15_t)0x67b3, (q15_t)0x67b0, (q15_t)0x67ac, (q15_t)0x67a8, (q15_t)0x67a5, (q15_t)0x67a1, + (q15_t)0x679d, (q15_t)0x679a, (q15_t)0x6796, (q15_t)0x6792, (q15_t)0x678e, (q15_t)0x678b, (q15_t)0x6787, (q15_t)0x6783, + (q15_t)0x6780, (q15_t)0x677c, (q15_t)0x6778, (q15_t)0x6775, (q15_t)0x6771, (q15_t)0x676d, (q15_t)0x6769, (q15_t)0x6766, + (q15_t)0x6762, (q15_t)0x675e, (q15_t)0x675b, (q15_t)0x6757, (q15_t)0x6753, (q15_t)0x6750, (q15_t)0x674c, (q15_t)0x6748, + (q15_t)0x6744, (q15_t)0x6741, (q15_t)0x673d, (q15_t)0x6739, (q15_t)0x6736, (q15_t)0x6732, (q15_t)0x672e, (q15_t)0x672a, + (q15_t)0x6727, (q15_t)0x6723, (q15_t)0x671f, (q15_t)0x671c, (q15_t)0x6718, (q15_t)0x6714, (q15_t)0x6710, (q15_t)0x670d, + (q15_t)0x6709, (q15_t)0x6705, (q15_t)0x6701, (q15_t)0x66fe, (q15_t)0x66fa, (q15_t)0x66f6, (q15_t)0x66f3, (q15_t)0x66ef, + (q15_t)0x66eb, (q15_t)0x66e7, (q15_t)0x66e4, (q15_t)0x66e0, (q15_t)0x66dc, (q15_t)0x66d8, (q15_t)0x66d5, (q15_t)0x66d1, + (q15_t)0x66cd, (q15_t)0x66c9, (q15_t)0x66c6, (q15_t)0x66c2, (q15_t)0x66be, (q15_t)0x66ba, (q15_t)0x66b7, (q15_t)0x66b3, + (q15_t)0x66af, (q15_t)0x66ab, (q15_t)0x66a8, (q15_t)0x66a4, (q15_t)0x66a0, (q15_t)0x669c, (q15_t)0x6699, (q15_t)0x6695, + (q15_t)0x6691, (q15_t)0x668d, (q15_t)0x668a, (q15_t)0x6686, (q15_t)0x6682, (q15_t)0x667e, (q15_t)0x667b, (q15_t)0x6677, + (q15_t)0x6673, (q15_t)0x666f, (q15_t)0x666b, (q15_t)0x6668, (q15_t)0x6664, (q15_t)0x6660, (q15_t)0x665c, (q15_t)0x6659, + (q15_t)0x6655, (q15_t)0x6651, (q15_t)0x664d, (q15_t)0x664a, (q15_t)0x6646, (q15_t)0x6642, (q15_t)0x663e, (q15_t)0x663a, + (q15_t)0x6637, (q15_t)0x6633, (q15_t)0x662f, (q15_t)0x662b, (q15_t)0x6627, (q15_t)0x6624, (q15_t)0x6620, (q15_t)0x661c, + (q15_t)0x6618, (q15_t)0x6615, (q15_t)0x6611, (q15_t)0x660d, (q15_t)0x6609, (q15_t)0x6605, (q15_t)0x6602, (q15_t)0x65fe, + (q15_t)0x65fa, (q15_t)0x65f6, (q15_t)0x65f2, (q15_t)0x65ef, (q15_t)0x65eb, (q15_t)0x65e7, (q15_t)0x65e3, (q15_t)0x65df, + (q15_t)0x65dc, (q15_t)0x65d8, (q15_t)0x65d4, (q15_t)0x65d0, (q15_t)0x65cc, (q15_t)0x65c9, (q15_t)0x65c5, (q15_t)0x65c1, + (q15_t)0x65bd, (q15_t)0x65b9, (q15_t)0x65b5, (q15_t)0x65b2, (q15_t)0x65ae, (q15_t)0x65aa, (q15_t)0x65a6, (q15_t)0x65a2, + (q15_t)0x659f, (q15_t)0x659b, (q15_t)0x6597, (q15_t)0x6593, (q15_t)0x658f, (q15_t)0x658b, (q15_t)0x6588, (q15_t)0x6584, + (q15_t)0x6580, (q15_t)0x657c, (q15_t)0x6578, (q15_t)0x6574, (q15_t)0x6571, (q15_t)0x656d, (q15_t)0x6569, (q15_t)0x6565, + (q15_t)0x6561, (q15_t)0x655d, (q15_t)0x655a, (q15_t)0x6556, (q15_t)0x6552, (q15_t)0x654e, (q15_t)0x654a, (q15_t)0x6546, + (q15_t)0x6543, (q15_t)0x653f, (q15_t)0x653b, (q15_t)0x6537, (q15_t)0x6533, (q15_t)0x652f, (q15_t)0x652c, (q15_t)0x6528, + (q15_t)0x6524, (q15_t)0x6520, (q15_t)0x651c, (q15_t)0x6518, (q15_t)0x6514, (q15_t)0x6511, (q15_t)0x650d, (q15_t)0x6509, + (q15_t)0x6505, (q15_t)0x6501, (q15_t)0x64fd, (q15_t)0x64f9, (q15_t)0x64f6, (q15_t)0x64f2, (q15_t)0x64ee, (q15_t)0x64ea, + (q15_t)0x64e6, (q15_t)0x64e2, (q15_t)0x64de, (q15_t)0x64db, (q15_t)0x64d7, (q15_t)0x64d3, (q15_t)0x64cf, (q15_t)0x64cb, + (q15_t)0x64c7, (q15_t)0x64c3, (q15_t)0x64bf, (q15_t)0x64bc, (q15_t)0x64b8, (q15_t)0x64b4, (q15_t)0x64b0, (q15_t)0x64ac, + (q15_t)0x64a8, (q15_t)0x64a4, (q15_t)0x64a0, (q15_t)0x649c, (q15_t)0x6499, (q15_t)0x6495, (q15_t)0x6491, (q15_t)0x648d, + (q15_t)0x6489, (q15_t)0x6485, (q15_t)0x6481, (q15_t)0x647d, (q15_t)0x6479, (q15_t)0x6476, (q15_t)0x6472, (q15_t)0x646e, + (q15_t)0x646a, (q15_t)0x6466, (q15_t)0x6462, (q15_t)0x645e, (q15_t)0x645a, (q15_t)0x6456, (q15_t)0x6453, (q15_t)0x644f, + (q15_t)0x644b, (q15_t)0x6447, (q15_t)0x6443, (q15_t)0x643f, (q15_t)0x643b, (q15_t)0x6437, (q15_t)0x6433, (q15_t)0x642f, + (q15_t)0x642b, (q15_t)0x6428, (q15_t)0x6424, (q15_t)0x6420, (q15_t)0x641c, (q15_t)0x6418, (q15_t)0x6414, (q15_t)0x6410, + (q15_t)0x640c, (q15_t)0x6408, (q15_t)0x6404, (q15_t)0x6400, (q15_t)0x63fc, (q15_t)0x63f9, (q15_t)0x63f5, (q15_t)0x63f1, + (q15_t)0x63ed, (q15_t)0x63e9, (q15_t)0x63e5, (q15_t)0x63e1, (q15_t)0x63dd, (q15_t)0x63d9, (q15_t)0x63d5, (q15_t)0x63d1, + (q15_t)0x63cd, (q15_t)0x63c9, (q15_t)0x63c5, (q15_t)0x63c1, (q15_t)0x63be, (q15_t)0x63ba, (q15_t)0x63b6, (q15_t)0x63b2, + (q15_t)0x63ae, (q15_t)0x63aa, (q15_t)0x63a6, (q15_t)0x63a2, (q15_t)0x639e, (q15_t)0x639a, (q15_t)0x6396, (q15_t)0x6392, + (q15_t)0x638e, (q15_t)0x638a, (q15_t)0x6386, (q15_t)0x6382, (q15_t)0x637e, (q15_t)0x637a, (q15_t)0x6377, (q15_t)0x6373, + (q15_t)0x636f, (q15_t)0x636b, (q15_t)0x6367, (q15_t)0x6363, (q15_t)0x635f, (q15_t)0x635b, (q15_t)0x6357, (q15_t)0x6353, + (q15_t)0x634f, (q15_t)0x634b, (q15_t)0x6347, (q15_t)0x6343, (q15_t)0x633f, (q15_t)0x633b, (q15_t)0x6337, (q15_t)0x6333, + (q15_t)0x632f, (q15_t)0x632b, (q15_t)0x6327, (q15_t)0x6323, (q15_t)0x631f, (q15_t)0x631b, (q15_t)0x6317, (q15_t)0x6313, + (q15_t)0x630f, (q15_t)0x630b, (q15_t)0x6307, (q15_t)0x6303, (q15_t)0x62ff, (q15_t)0x62fb, (q15_t)0x62f7, (q15_t)0x62f3, + (q15_t)0x62f0, (q15_t)0x62ec, (q15_t)0x62e8, (q15_t)0x62e4, (q15_t)0x62e0, (q15_t)0x62dc, (q15_t)0x62d8, (q15_t)0x62d4, + (q15_t)0x62d0, (q15_t)0x62cc, (q15_t)0x62c8, (q15_t)0x62c4, (q15_t)0x62c0, (q15_t)0x62bc, (q15_t)0x62b8, (q15_t)0x62b4, + (q15_t)0x62b0, (q15_t)0x62ac, (q15_t)0x62a8, (q15_t)0x62a4, (q15_t)0x62a0, (q15_t)0x629c, (q15_t)0x6298, (q15_t)0x6294, + (q15_t)0x6290, (q15_t)0x628c, (q15_t)0x6288, (q15_t)0x6284, (q15_t)0x6280, (q15_t)0x627c, (q15_t)0x6278, (q15_t)0x6273, + (q15_t)0x626f, (q15_t)0x626b, (q15_t)0x6267, (q15_t)0x6263, (q15_t)0x625f, (q15_t)0x625b, (q15_t)0x6257, (q15_t)0x6253, + (q15_t)0x624f, (q15_t)0x624b, (q15_t)0x6247, (q15_t)0x6243, (q15_t)0x623f, (q15_t)0x623b, (q15_t)0x6237, (q15_t)0x6233, + (q15_t)0x622f, (q15_t)0x622b, (q15_t)0x6227, (q15_t)0x6223, (q15_t)0x621f, (q15_t)0x621b, (q15_t)0x6217, (q15_t)0x6213, + (q15_t)0x620f, (q15_t)0x620b, (q15_t)0x6207, (q15_t)0x6203, (q15_t)0x61ff, (q15_t)0x61fb, (q15_t)0x61f7, (q15_t)0x61f3, + (q15_t)0x61ee, (q15_t)0x61ea, (q15_t)0x61e6, (q15_t)0x61e2, (q15_t)0x61de, (q15_t)0x61da, (q15_t)0x61d6, (q15_t)0x61d2, + (q15_t)0x61ce, (q15_t)0x61ca, (q15_t)0x61c6, (q15_t)0x61c2, (q15_t)0x61be, (q15_t)0x61ba, (q15_t)0x61b6, (q15_t)0x61b2, + (q15_t)0x61ae, (q15_t)0x61aa, (q15_t)0x61a6, (q15_t)0x61a1, (q15_t)0x619d, (q15_t)0x6199, (q15_t)0x6195, (q15_t)0x6191, + (q15_t)0x618d, (q15_t)0x6189, (q15_t)0x6185, (q15_t)0x6181, (q15_t)0x617d, (q15_t)0x6179, (q15_t)0x6175, (q15_t)0x6171, + (q15_t)0x616d, (q15_t)0x6168, (q15_t)0x6164, (q15_t)0x6160, (q15_t)0x615c, (q15_t)0x6158, (q15_t)0x6154, (q15_t)0x6150, + (q15_t)0x614c, (q15_t)0x6148, (q15_t)0x6144, (q15_t)0x6140, (q15_t)0x613c, (q15_t)0x6137, (q15_t)0x6133, (q15_t)0x612f, + (q15_t)0x612b, (q15_t)0x6127, (q15_t)0x6123, (q15_t)0x611f, (q15_t)0x611b, (q15_t)0x6117, (q15_t)0x6113, (q15_t)0x610f, + (q15_t)0x610a, (q15_t)0x6106, (q15_t)0x6102, (q15_t)0x60fe, (q15_t)0x60fa, (q15_t)0x60f6, (q15_t)0x60f2, (q15_t)0x60ee, + (q15_t)0x60ea, (q15_t)0x60e6, (q15_t)0x60e1, (q15_t)0x60dd, (q15_t)0x60d9, (q15_t)0x60d5, (q15_t)0x60d1, (q15_t)0x60cd, + (q15_t)0x60c9, (q15_t)0x60c5, (q15_t)0x60c1, (q15_t)0x60bc, (q15_t)0x60b8, (q15_t)0x60b4, (q15_t)0x60b0, (q15_t)0x60ac, + (q15_t)0x60a8, (q15_t)0x60a4, (q15_t)0x60a0, (q15_t)0x609c, (q15_t)0x6097, (q15_t)0x6093, (q15_t)0x608f, (q15_t)0x608b, + (q15_t)0x6087, (q15_t)0x6083, (q15_t)0x607f, (q15_t)0x607b, (q15_t)0x6076, (q15_t)0x6072, (q15_t)0x606e, (q15_t)0x606a, + (q15_t)0x6066, (q15_t)0x6062, (q15_t)0x605e, (q15_t)0x6059, (q15_t)0x6055, (q15_t)0x6051, (q15_t)0x604d, (q15_t)0x6049, + (q15_t)0x6045, (q15_t)0x6041, (q15_t)0x603c, (q15_t)0x6038, (q15_t)0x6034, (q15_t)0x6030, (q15_t)0x602c, (q15_t)0x6028, + (q15_t)0x6024, (q15_t)0x601f, (q15_t)0x601b, (q15_t)0x6017, (q15_t)0x6013, (q15_t)0x600f, (q15_t)0x600b, (q15_t)0x6007, + (q15_t)0x6002, (q15_t)0x5ffe, (q15_t)0x5ffa, (q15_t)0x5ff6, (q15_t)0x5ff2, (q15_t)0x5fee, (q15_t)0x5fe9, (q15_t)0x5fe5, + (q15_t)0x5fe1, (q15_t)0x5fdd, (q15_t)0x5fd9, (q15_t)0x5fd5, (q15_t)0x5fd0, (q15_t)0x5fcc, (q15_t)0x5fc8, (q15_t)0x5fc4, + (q15_t)0x5fc0, (q15_t)0x5fbc, (q15_t)0x5fb7, (q15_t)0x5fb3, (q15_t)0x5faf, (q15_t)0x5fab, (q15_t)0x5fa7, (q15_t)0x5fa3, + (q15_t)0x5f9e, (q15_t)0x5f9a, (q15_t)0x5f96, (q15_t)0x5f92, (q15_t)0x5f8e, (q15_t)0x5f8a, (q15_t)0x5f85, (q15_t)0x5f81, + (q15_t)0x5f7d, (q15_t)0x5f79, (q15_t)0x5f75, (q15_t)0x5f70, (q15_t)0x5f6c, (q15_t)0x5f68, (q15_t)0x5f64, (q15_t)0x5f60, + (q15_t)0x5f5b, (q15_t)0x5f57, (q15_t)0x5f53, (q15_t)0x5f4f, (q15_t)0x5f4b, (q15_t)0x5f46, (q15_t)0x5f42, (q15_t)0x5f3e, + (q15_t)0x5f3a, (q15_t)0x5f36, (q15_t)0x5f31, (q15_t)0x5f2d, (q15_t)0x5f29, (q15_t)0x5f25, (q15_t)0x5f21, (q15_t)0x5f1c, + (q15_t)0x5f18, (q15_t)0x5f14, (q15_t)0x5f10, (q15_t)0x5f0c, (q15_t)0x5f07, (q15_t)0x5f03, (q15_t)0x5eff, (q15_t)0x5efb, + (q15_t)0x5ef7, (q15_t)0x5ef2, (q15_t)0x5eee, (q15_t)0x5eea, (q15_t)0x5ee6, (q15_t)0x5ee2, (q15_t)0x5edd, (q15_t)0x5ed9, + (q15_t)0x5ed5, (q15_t)0x5ed1, (q15_t)0x5ecc, (q15_t)0x5ec8, (q15_t)0x5ec4, (q15_t)0x5ec0, (q15_t)0x5ebc, (q15_t)0x5eb7, + (q15_t)0x5eb3, (q15_t)0x5eaf, (q15_t)0x5eab, (q15_t)0x5ea6, (q15_t)0x5ea2, (q15_t)0x5e9e, (q15_t)0x5e9a, (q15_t)0x5e95, + (q15_t)0x5e91, (q15_t)0x5e8d, (q15_t)0x5e89, (q15_t)0x5e85, (q15_t)0x5e80, (q15_t)0x5e7c, (q15_t)0x5e78, (q15_t)0x5e74, + (q15_t)0x5e6f, (q15_t)0x5e6b, (q15_t)0x5e67, (q15_t)0x5e63, (q15_t)0x5e5e, (q15_t)0x5e5a, (q15_t)0x5e56, (q15_t)0x5e52, + (q15_t)0x5e4d, (q15_t)0x5e49, (q15_t)0x5e45, (q15_t)0x5e41, (q15_t)0x5e3c, (q15_t)0x5e38, (q15_t)0x5e34, (q15_t)0x5e30, + (q15_t)0x5e2b, (q15_t)0x5e27, (q15_t)0x5e23, (q15_t)0x5e1f, (q15_t)0x5e1a, (q15_t)0x5e16, (q15_t)0x5e12, (q15_t)0x5e0e, + (q15_t)0x5e09, (q15_t)0x5e05, (q15_t)0x5e01, (q15_t)0x5dfd, (q15_t)0x5df8, (q15_t)0x5df4, (q15_t)0x5df0, (q15_t)0x5deb, + (q15_t)0x5de7, (q15_t)0x5de3, (q15_t)0x5ddf, (q15_t)0x5dda, (q15_t)0x5dd6, (q15_t)0x5dd2, (q15_t)0x5dce, (q15_t)0x5dc9, + (q15_t)0x5dc5, (q15_t)0x5dc1, (q15_t)0x5dbc, (q15_t)0x5db8, (q15_t)0x5db4, (q15_t)0x5db0, (q15_t)0x5dab, (q15_t)0x5da7, + (q15_t)0x5da3, (q15_t)0x5d9e, (q15_t)0x5d9a, (q15_t)0x5d96, (q15_t)0x5d92, (q15_t)0x5d8d, (q15_t)0x5d89, (q15_t)0x5d85, + (q15_t)0x5d80, (q15_t)0x5d7c, (q15_t)0x5d78, (q15_t)0x5d74, (q15_t)0x5d6f, (q15_t)0x5d6b, (q15_t)0x5d67, (q15_t)0x5d62, + (q15_t)0x5d5e, (q15_t)0x5d5a, (q15_t)0x5d55, (q15_t)0x5d51, (q15_t)0x5d4d, (q15_t)0x5d49, (q15_t)0x5d44, (q15_t)0x5d40, + (q15_t)0x5d3c, (q15_t)0x5d37, (q15_t)0x5d33, (q15_t)0x5d2f, (q15_t)0x5d2a, (q15_t)0x5d26, (q15_t)0x5d22, (q15_t)0x5d1e, + (q15_t)0x5d19, (q15_t)0x5d15, (q15_t)0x5d11, (q15_t)0x5d0c, (q15_t)0x5d08, (q15_t)0x5d04, (q15_t)0x5cff, (q15_t)0x5cfb, + (q15_t)0x5cf7, (q15_t)0x5cf2, (q15_t)0x5cee, (q15_t)0x5cea, (q15_t)0x5ce5, (q15_t)0x5ce1, (q15_t)0x5cdd, (q15_t)0x5cd8, + (q15_t)0x5cd4, (q15_t)0x5cd0, (q15_t)0x5ccb, (q15_t)0x5cc7, (q15_t)0x5cc3, (q15_t)0x5cbe, (q15_t)0x5cba, (q15_t)0x5cb6, + (q15_t)0x5cb1, (q15_t)0x5cad, (q15_t)0x5ca9, (q15_t)0x5ca4, (q15_t)0x5ca0, (q15_t)0x5c9c, (q15_t)0x5c97, (q15_t)0x5c93, + (q15_t)0x5c8f, (q15_t)0x5c8a, (q15_t)0x5c86, (q15_t)0x5c82, (q15_t)0x5c7d, (q15_t)0x5c79, (q15_t)0x5c75, (q15_t)0x5c70, + (q15_t)0x5c6c, (q15_t)0x5c68, (q15_t)0x5c63, (q15_t)0x5c5f, (q15_t)0x5c5b, (q15_t)0x5c56, (q15_t)0x5c52, (q15_t)0x5c4e, + (q15_t)0x5c49, (q15_t)0x5c45, (q15_t)0x5c41, (q15_t)0x5c3c, (q15_t)0x5c38, (q15_t)0x5c33, (q15_t)0x5c2f, (q15_t)0x5c2b, + (q15_t)0x5c26, (q15_t)0x5c22, (q15_t)0x5c1e, (q15_t)0x5c19, (q15_t)0x5c15, (q15_t)0x5c11, (q15_t)0x5c0c, (q15_t)0x5c08, + (q15_t)0x5c03, (q15_t)0x5bff, (q15_t)0x5bfb, (q15_t)0x5bf6, (q15_t)0x5bf2, (q15_t)0x5bee, (q15_t)0x5be9, (q15_t)0x5be5, + (q15_t)0x5be0, (q15_t)0x5bdc, (q15_t)0x5bd8, (q15_t)0x5bd3, (q15_t)0x5bcf, (q15_t)0x5bcb, (q15_t)0x5bc6, (q15_t)0x5bc2, + (q15_t)0x5bbd, (q15_t)0x5bb9, (q15_t)0x5bb5, (q15_t)0x5bb0, (q15_t)0x5bac, (q15_t)0x5ba8, (q15_t)0x5ba3, (q15_t)0x5b9f, + (q15_t)0x5b9a, (q15_t)0x5b96, (q15_t)0x5b92, (q15_t)0x5b8d, (q15_t)0x5b89, (q15_t)0x5b84, (q15_t)0x5b80, (q15_t)0x5b7c, + (q15_t)0x5b77, (q15_t)0x5b73, (q15_t)0x5b6e, (q15_t)0x5b6a, (q15_t)0x5b66, (q15_t)0x5b61, (q15_t)0x5b5d, (q15_t)0x5b58, + (q15_t)0x5b54, (q15_t)0x5b50, (q15_t)0x5b4b, (q15_t)0x5b47, (q15_t)0x5b42, (q15_t)0x5b3e, (q15_t)0x5b3a, (q15_t)0x5b35, + (q15_t)0x5b31, (q15_t)0x5b2c, (q15_t)0x5b28, (q15_t)0x5b24, (q15_t)0x5b1f, (q15_t)0x5b1b, (q15_t)0x5b16, (q15_t)0x5b12, + (q15_t)0x5b0e, (q15_t)0x5b09, (q15_t)0x5b05, (q15_t)0x5b00, (q15_t)0x5afc, (q15_t)0x5af7, (q15_t)0x5af3, (q15_t)0x5aef, + (q15_t)0x5aea, (q15_t)0x5ae6, (q15_t)0x5ae1, (q15_t)0x5add, (q15_t)0x5ad8, (q15_t)0x5ad4, (q15_t)0x5ad0, (q15_t)0x5acb, + (q15_t)0x5ac7, (q15_t)0x5ac2, (q15_t)0x5abe, (q15_t)0x5ab9, (q15_t)0x5ab5, (q15_t)0x5ab1, (q15_t)0x5aac, (q15_t)0x5aa8, + (q15_t)0x5aa3, (q15_t)0x5a9f, (q15_t)0x5a9a, (q15_t)0x5a96, (q15_t)0x5a92, (q15_t)0x5a8d, (q15_t)0x5a89, (q15_t)0x5a84, + (q15_t)0x5a80, (q15_t)0x5a7b, (q15_t)0x5a77, (q15_t)0x5a72, (q15_t)0x5a6e, (q15_t)0x5a6a, (q15_t)0x5a65, (q15_t)0x5a61, + (q15_t)0x5a5c, (q15_t)0x5a58, (q15_t)0x5a53, (q15_t)0x5a4f, (q15_t)0x5a4a, (q15_t)0x5a46, (q15_t)0x5a41, (q15_t)0x5a3d, + (q15_t)0x5a39, (q15_t)0x5a34, (q15_t)0x5a30, (q15_t)0x5a2b, (q15_t)0x5a27, (q15_t)0x5a22, (q15_t)0x5a1e, (q15_t)0x5a19, + (q15_t)0x5a15, (q15_t)0x5a10, (q15_t)0x5a0c, (q15_t)0x5a07, (q15_t)0x5a03, (q15_t)0x59ff, (q15_t)0x59fa, (q15_t)0x59f6, + (q15_t)0x59f1, (q15_t)0x59ed, (q15_t)0x59e8, (q15_t)0x59e4, (q15_t)0x59df, (q15_t)0x59db, (q15_t)0x59d6, (q15_t)0x59d2, + (q15_t)0x59cd, (q15_t)0x59c9, (q15_t)0x59c4, (q15_t)0x59c0, (q15_t)0x59bb, (q15_t)0x59b7, (q15_t)0x59b2, (q15_t)0x59ae, + (q15_t)0x59a9, (q15_t)0x59a5, (q15_t)0x59a1, (q15_t)0x599c, (q15_t)0x5998, (q15_t)0x5993, (q15_t)0x598f, (q15_t)0x598a, + (q15_t)0x5986, (q15_t)0x5981, (q15_t)0x597d, (q15_t)0x5978, (q15_t)0x5974, (q15_t)0x596f, (q15_t)0x596b, (q15_t)0x5966, + (q15_t)0x5962, (q15_t)0x595d, (q15_t)0x5959, (q15_t)0x5954, (q15_t)0x5950, (q15_t)0x594b, (q15_t)0x5947, (q15_t)0x5942, + (q15_t)0x593e, (q15_t)0x5939, (q15_t)0x5935, (q15_t)0x5930, (q15_t)0x592c, (q15_t)0x5927, (q15_t)0x5923, (q15_t)0x591e, + (q15_t)0x591a, (q15_t)0x5915, (q15_t)0x5911, (q15_t)0x590c, (q15_t)0x5908, (q15_t)0x5903, (q15_t)0x58fe, (q15_t)0x58fa, + (q15_t)0x58f5, (q15_t)0x58f1, (q15_t)0x58ec, (q15_t)0x58e8, (q15_t)0x58e3, (q15_t)0x58df, (q15_t)0x58da, (q15_t)0x58d6, + (q15_t)0x58d1, (q15_t)0x58cd, (q15_t)0x58c8, (q15_t)0x58c4, (q15_t)0x58bf, (q15_t)0x58bb, (q15_t)0x58b6, (q15_t)0x58b2, + (q15_t)0x58ad, (q15_t)0x58a9, (q15_t)0x58a4, (q15_t)0x589f, (q15_t)0x589b, (q15_t)0x5896, (q15_t)0x5892, (q15_t)0x588d, + (q15_t)0x5889, (q15_t)0x5884, (q15_t)0x5880, (q15_t)0x587b, (q15_t)0x5877, (q15_t)0x5872, (q15_t)0x586e, (q15_t)0x5869, + (q15_t)0x5864, (q15_t)0x5860, (q15_t)0x585b, (q15_t)0x5857, (q15_t)0x5852, (q15_t)0x584e, (q15_t)0x5849, (q15_t)0x5845, + (q15_t)0x5840, (q15_t)0x583c, (q15_t)0x5837, (q15_t)0x5832, (q15_t)0x582e, (q15_t)0x5829, (q15_t)0x5825, (q15_t)0x5820, + (q15_t)0x581c, (q15_t)0x5817, (q15_t)0x5813, (q15_t)0x580e, (q15_t)0x5809, (q15_t)0x5805, (q15_t)0x5800, (q15_t)0x57fc, + (q15_t)0x57f7, (q15_t)0x57f3, (q15_t)0x57ee, (q15_t)0x57e9, (q15_t)0x57e5, (q15_t)0x57e0, (q15_t)0x57dc, (q15_t)0x57d7, + (q15_t)0x57d3, (q15_t)0x57ce, (q15_t)0x57c9, (q15_t)0x57c5, (q15_t)0x57c0, (q15_t)0x57bc, (q15_t)0x57b7, (q15_t)0x57b3, + (q15_t)0x57ae, (q15_t)0x57a9, (q15_t)0x57a5, (q15_t)0x57a0, (q15_t)0x579c, (q15_t)0x5797, (q15_t)0x5793, (q15_t)0x578e, + (q15_t)0x5789, (q15_t)0x5785, (q15_t)0x5780, (q15_t)0x577c, (q15_t)0x5777, (q15_t)0x5772, (q15_t)0x576e, (q15_t)0x5769, + (q15_t)0x5765, (q15_t)0x5760, (q15_t)0x575c, (q15_t)0x5757, (q15_t)0x5752, (q15_t)0x574e, (q15_t)0x5749, (q15_t)0x5745, + (q15_t)0x5740, (q15_t)0x573b, (q15_t)0x5737, (q15_t)0x5732, (q15_t)0x572e, (q15_t)0x5729, (q15_t)0x5724, (q15_t)0x5720, + (q15_t)0x571b, (q15_t)0x5717, (q15_t)0x5712, (q15_t)0x570d, (q15_t)0x5709, (q15_t)0x5704, (q15_t)0x56ff, (q15_t)0x56fb, + (q15_t)0x56f6, (q15_t)0x56f2, (q15_t)0x56ed, (q15_t)0x56e8, (q15_t)0x56e4, (q15_t)0x56df, (q15_t)0x56db, (q15_t)0x56d6, + (q15_t)0x56d1, (q15_t)0x56cd, (q15_t)0x56c8, (q15_t)0x56c4, (q15_t)0x56bf, (q15_t)0x56ba, (q15_t)0x56b6, (q15_t)0x56b1, + (q15_t)0x56ac, (q15_t)0x56a8, (q15_t)0x56a3, (q15_t)0x569f, (q15_t)0x569a, (q15_t)0x5695, (q15_t)0x5691, (q15_t)0x568c, + (q15_t)0x5687, (q15_t)0x5683, (q15_t)0x567e, (q15_t)0x5679, (q15_t)0x5675, (q15_t)0x5670, (q15_t)0x566c, (q15_t)0x5667, + (q15_t)0x5662, (q15_t)0x565e, (q15_t)0x5659, (q15_t)0x5654, (q15_t)0x5650, (q15_t)0x564b, (q15_t)0x5646, (q15_t)0x5642, + (q15_t)0x563d, (q15_t)0x5639, (q15_t)0x5634, (q15_t)0x562f, (q15_t)0x562b, (q15_t)0x5626, (q15_t)0x5621, (q15_t)0x561d, + (q15_t)0x5618, (q15_t)0x5613, (q15_t)0x560f, (q15_t)0x560a, (q15_t)0x5605, (q15_t)0x5601, (q15_t)0x55fc, (q15_t)0x55f7, + (q15_t)0x55f3, (q15_t)0x55ee, (q15_t)0x55ea, (q15_t)0x55e5, (q15_t)0x55e0, (q15_t)0x55dc, (q15_t)0x55d7, (q15_t)0x55d2, + (q15_t)0x55ce, (q15_t)0x55c9, (q15_t)0x55c4, (q15_t)0x55c0, (q15_t)0x55bb, (q15_t)0x55b6, (q15_t)0x55b2, (q15_t)0x55ad, + (q15_t)0x55a8, (q15_t)0x55a4, (q15_t)0x559f, (q15_t)0x559a, (q15_t)0x5596, (q15_t)0x5591, (q15_t)0x558c, (q15_t)0x5588, + (q15_t)0x5583, (q15_t)0x557e, (q15_t)0x5579, (q15_t)0x5575, (q15_t)0x5570, (q15_t)0x556b, (q15_t)0x5567, (q15_t)0x5562, + (q15_t)0x555d, (q15_t)0x5559, (q15_t)0x5554, (q15_t)0x554f, (q15_t)0x554b, (q15_t)0x5546, (q15_t)0x5541, (q15_t)0x553d, + (q15_t)0x5538, (q15_t)0x5533, (q15_t)0x552f, (q15_t)0x552a, (q15_t)0x5525, (q15_t)0x5520, (q15_t)0x551c, (q15_t)0x5517, + (q15_t)0x5512, (q15_t)0x550e, (q15_t)0x5509, (q15_t)0x5504, (q15_t)0x5500, (q15_t)0x54fb, (q15_t)0x54f6, (q15_t)0x54f2, + (q15_t)0x54ed, (q15_t)0x54e8, (q15_t)0x54e3, (q15_t)0x54df, (q15_t)0x54da, (q15_t)0x54d5, (q15_t)0x54d1, (q15_t)0x54cc, + (q15_t)0x54c7, (q15_t)0x54c2, (q15_t)0x54be, (q15_t)0x54b9, (q15_t)0x54b4, (q15_t)0x54b0, (q15_t)0x54ab, (q15_t)0x54a6, + (q15_t)0x54a2, (q15_t)0x549d, (q15_t)0x5498, (q15_t)0x5493, (q15_t)0x548f, (q15_t)0x548a, (q15_t)0x5485, (q15_t)0x5480, + (q15_t)0x547c, (q15_t)0x5477, (q15_t)0x5472, (q15_t)0x546e, (q15_t)0x5469, (q15_t)0x5464, (q15_t)0x545f, (q15_t)0x545b, + (q15_t)0x5456, (q15_t)0x5451, (q15_t)0x544d, (q15_t)0x5448, (q15_t)0x5443, (q15_t)0x543e, (q15_t)0x543a, (q15_t)0x5435, + (q15_t)0x5430, (q15_t)0x542b, (q15_t)0x5427, (q15_t)0x5422, (q15_t)0x541d, (q15_t)0x5418, (q15_t)0x5414, (q15_t)0x540f, + (q15_t)0x540a, (q15_t)0x5406, (q15_t)0x5401, (q15_t)0x53fc, (q15_t)0x53f7, (q15_t)0x53f3, (q15_t)0x53ee, (q15_t)0x53e9, + (q15_t)0x53e4, (q15_t)0x53e0, (q15_t)0x53db, (q15_t)0x53d6, (q15_t)0x53d1, (q15_t)0x53cd, (q15_t)0x53c8, (q15_t)0x53c3, + (q15_t)0x53be, (q15_t)0x53ba, (q15_t)0x53b5, (q15_t)0x53b0, (q15_t)0x53ab, (q15_t)0x53a7, (q15_t)0x53a2, (q15_t)0x539d, + (q15_t)0x5398, (q15_t)0x5394, (q15_t)0x538f, (q15_t)0x538a, (q15_t)0x5385, (q15_t)0x5380, (q15_t)0x537c, (q15_t)0x5377, + (q15_t)0x5372, (q15_t)0x536d, (q15_t)0x5369, (q15_t)0x5364, (q15_t)0x535f, (q15_t)0x535a, (q15_t)0x5356, (q15_t)0x5351, + (q15_t)0x534c, (q15_t)0x5347, (q15_t)0x5343, (q15_t)0x533e, (q15_t)0x5339, (q15_t)0x5334, (q15_t)0x532f, (q15_t)0x532b, + (q15_t)0x5326, (q15_t)0x5321, (q15_t)0x531c, (q15_t)0x5318, (q15_t)0x5313, (q15_t)0x530e, (q15_t)0x5309, (q15_t)0x5304, + (q15_t)0x5300, (q15_t)0x52fb, (q15_t)0x52f6, (q15_t)0x52f1, (q15_t)0x52ec, (q15_t)0x52e8, (q15_t)0x52e3, (q15_t)0x52de, + (q15_t)0x52d9, (q15_t)0x52d5, (q15_t)0x52d0, (q15_t)0x52cb, (q15_t)0x52c6, (q15_t)0x52c1, (q15_t)0x52bd, (q15_t)0x52b8, + (q15_t)0x52b3, (q15_t)0x52ae, (q15_t)0x52a9, (q15_t)0x52a5, (q15_t)0x52a0, (q15_t)0x529b, (q15_t)0x5296, (q15_t)0x5291, + (q15_t)0x528d, (q15_t)0x5288, (q15_t)0x5283, (q15_t)0x527e, (q15_t)0x5279, (q15_t)0x5275, (q15_t)0x5270, (q15_t)0x526b, + (q15_t)0x5266, (q15_t)0x5261, (q15_t)0x525d, (q15_t)0x5258, (q15_t)0x5253, (q15_t)0x524e, (q15_t)0x5249, (q15_t)0x5244, + (q15_t)0x5240, (q15_t)0x523b, (q15_t)0x5236, (q15_t)0x5231, (q15_t)0x522c, (q15_t)0x5228, (q15_t)0x5223, (q15_t)0x521e, + (q15_t)0x5219, (q15_t)0x5214, (q15_t)0x520f, (q15_t)0x520b, (q15_t)0x5206, (q15_t)0x5201, (q15_t)0x51fc, (q15_t)0x51f7, + (q15_t)0x51f3, (q15_t)0x51ee, (q15_t)0x51e9, (q15_t)0x51e4, (q15_t)0x51df, (q15_t)0x51da, (q15_t)0x51d6, (q15_t)0x51d1, + (q15_t)0x51cc, (q15_t)0x51c7, (q15_t)0x51c2, (q15_t)0x51bd, (q15_t)0x51b9, (q15_t)0x51b4, (q15_t)0x51af, (q15_t)0x51aa, + (q15_t)0x51a5, (q15_t)0x51a0, (q15_t)0x519c, (q15_t)0x5197, (q15_t)0x5192, (q15_t)0x518d, (q15_t)0x5188, (q15_t)0x5183, + (q15_t)0x517e, (q15_t)0x517a, (q15_t)0x5175, (q15_t)0x5170, (q15_t)0x516b, (q15_t)0x5166, (q15_t)0x5161, (q15_t)0x515d, + (q15_t)0x5158, (q15_t)0x5153, (q15_t)0x514e, (q15_t)0x5149, (q15_t)0x5144, (q15_t)0x513f, (q15_t)0x513b, (q15_t)0x5136, + (q15_t)0x5131, (q15_t)0x512c, (q15_t)0x5127, (q15_t)0x5122, (q15_t)0x511d, (q15_t)0x5119, (q15_t)0x5114, (q15_t)0x510f, + (q15_t)0x510a, (q15_t)0x5105, (q15_t)0x5100, (q15_t)0x50fb, (q15_t)0x50f7, (q15_t)0x50f2, (q15_t)0x50ed, (q15_t)0x50e8, + (q15_t)0x50e3, (q15_t)0x50de, (q15_t)0x50d9, (q15_t)0x50d4, (q15_t)0x50d0, (q15_t)0x50cb, (q15_t)0x50c6, (q15_t)0x50c1, + (q15_t)0x50bc, (q15_t)0x50b7, (q15_t)0x50b2, (q15_t)0x50ad, (q15_t)0x50a9, (q15_t)0x50a4, (q15_t)0x509f, (q15_t)0x509a, + (q15_t)0x5095, (q15_t)0x5090, (q15_t)0x508b, (q15_t)0x5086, (q15_t)0x5082, (q15_t)0x507d, (q15_t)0x5078, (q15_t)0x5073, + (q15_t)0x506e, (q15_t)0x5069, (q15_t)0x5064, (q15_t)0x505f, (q15_t)0x505a, (q15_t)0x5056, (q15_t)0x5051, (q15_t)0x504c, + (q15_t)0x5047, (q15_t)0x5042, (q15_t)0x503d, (q15_t)0x5038, (q15_t)0x5033, (q15_t)0x502e, (q15_t)0x5029, (q15_t)0x5025, + (q15_t)0x5020, (q15_t)0x501b, (q15_t)0x5016, (q15_t)0x5011, (q15_t)0x500c, (q15_t)0x5007, (q15_t)0x5002, (q15_t)0x4ffd, + (q15_t)0x4ff8, (q15_t)0x4ff4, (q15_t)0x4fef, (q15_t)0x4fea, (q15_t)0x4fe5, (q15_t)0x4fe0, (q15_t)0x4fdb, (q15_t)0x4fd6, + (q15_t)0x4fd1, (q15_t)0x4fcc, (q15_t)0x4fc7, (q15_t)0x4fc2, (q15_t)0x4fbe, (q15_t)0x4fb9, (q15_t)0x4fb4, (q15_t)0x4faf, + (q15_t)0x4faa, (q15_t)0x4fa5, (q15_t)0x4fa0, (q15_t)0x4f9b, (q15_t)0x4f96, (q15_t)0x4f91, (q15_t)0x4f8c, (q15_t)0x4f87, + (q15_t)0x4f82, (q15_t)0x4f7e, (q15_t)0x4f79, (q15_t)0x4f74, (q15_t)0x4f6f, (q15_t)0x4f6a, (q15_t)0x4f65, (q15_t)0x4f60, + (q15_t)0x4f5b, (q15_t)0x4f56, (q15_t)0x4f51, (q15_t)0x4f4c, (q15_t)0x4f47, (q15_t)0x4f42, (q15_t)0x4f3d, (q15_t)0x4f39, + (q15_t)0x4f34, (q15_t)0x4f2f, (q15_t)0x4f2a, (q15_t)0x4f25, (q15_t)0x4f20, (q15_t)0x4f1b, (q15_t)0x4f16, (q15_t)0x4f11, + (q15_t)0x4f0c, (q15_t)0x4f07, (q15_t)0x4f02, (q15_t)0x4efd, (q15_t)0x4ef8, (q15_t)0x4ef3, (q15_t)0x4eee, (q15_t)0x4ee9, + (q15_t)0x4ee5, (q15_t)0x4ee0, (q15_t)0x4edb, (q15_t)0x4ed6, (q15_t)0x4ed1, (q15_t)0x4ecc, (q15_t)0x4ec7, (q15_t)0x4ec2, + (q15_t)0x4ebd, (q15_t)0x4eb8, (q15_t)0x4eb3, (q15_t)0x4eae, (q15_t)0x4ea9, (q15_t)0x4ea4, (q15_t)0x4e9f, (q15_t)0x4e9a, + (q15_t)0x4e95, (q15_t)0x4e90, (q15_t)0x4e8b, (q15_t)0x4e86, (q15_t)0x4e81, (q15_t)0x4e7c, (q15_t)0x4e78, (q15_t)0x4e73, + (q15_t)0x4e6e, (q15_t)0x4e69, (q15_t)0x4e64, (q15_t)0x4e5f, (q15_t)0x4e5a, (q15_t)0x4e55, (q15_t)0x4e50, (q15_t)0x4e4b, + (q15_t)0x4e46, (q15_t)0x4e41, (q15_t)0x4e3c, (q15_t)0x4e37, (q15_t)0x4e32, (q15_t)0x4e2d, (q15_t)0x4e28, (q15_t)0x4e23, + (q15_t)0x4e1e, (q15_t)0x4e19, (q15_t)0x4e14, (q15_t)0x4e0f, (q15_t)0x4e0a, (q15_t)0x4e05, (q15_t)0x4e00, (q15_t)0x4dfb, + (q15_t)0x4df6, (q15_t)0x4df1, (q15_t)0x4dec, (q15_t)0x4de7, (q15_t)0x4de2, (q15_t)0x4ddd, (q15_t)0x4dd8, (q15_t)0x4dd3, + (q15_t)0x4dce, (q15_t)0x4dc9, (q15_t)0x4dc4, (q15_t)0x4dbf, (q15_t)0x4dba, (q15_t)0x4db5, (q15_t)0x4db0, (q15_t)0x4dab, + (q15_t)0x4da6, (q15_t)0x4da1, (q15_t)0x4d9c, (q15_t)0x4d97, (q15_t)0x4d92, (q15_t)0x4d8d, (q15_t)0x4d88, (q15_t)0x4d83, + (q15_t)0x4d7e, (q15_t)0x4d79, (q15_t)0x4d74, (q15_t)0x4d6f, (q15_t)0x4d6a, (q15_t)0x4d65, (q15_t)0x4d60, (q15_t)0x4d5b, + (q15_t)0x4d56, (q15_t)0x4d51, (q15_t)0x4d4c, (q15_t)0x4d47, (q15_t)0x4d42, (q15_t)0x4d3d, (q15_t)0x4d38, (q15_t)0x4d33, + (q15_t)0x4d2e, (q15_t)0x4d29, (q15_t)0x4d24, (q15_t)0x4d1f, (q15_t)0x4d1a, (q15_t)0x4d15, (q15_t)0x4d10, (q15_t)0x4d0b, + (q15_t)0x4d06, (q15_t)0x4d01, (q15_t)0x4cfc, (q15_t)0x4cf7, (q15_t)0x4cf2, (q15_t)0x4ced, (q15_t)0x4ce8, (q15_t)0x4ce3, + (q15_t)0x4cde, (q15_t)0x4cd9, (q15_t)0x4cd4, (q15_t)0x4ccf, (q15_t)0x4cca, (q15_t)0x4cc5, (q15_t)0x4cc0, (q15_t)0x4cbb, + (q15_t)0x4cb6, (q15_t)0x4cb1, (q15_t)0x4cac, (q15_t)0x4ca7, (q15_t)0x4ca2, (q15_t)0x4c9d, (q15_t)0x4c98, (q15_t)0x4c93, + (q15_t)0x4c8e, (q15_t)0x4c88, (q15_t)0x4c83, (q15_t)0x4c7e, (q15_t)0x4c79, (q15_t)0x4c74, (q15_t)0x4c6f, (q15_t)0x4c6a, + (q15_t)0x4c65, (q15_t)0x4c60, (q15_t)0x4c5b, (q15_t)0x4c56, (q15_t)0x4c51, (q15_t)0x4c4c, (q15_t)0x4c47, (q15_t)0x4c42, + (q15_t)0x4c3d, (q15_t)0x4c38, (q15_t)0x4c33, (q15_t)0x4c2e, (q15_t)0x4c29, (q15_t)0x4c24, (q15_t)0x4c1f, (q15_t)0x4c1a, + (q15_t)0x4c14, (q15_t)0x4c0f, (q15_t)0x4c0a, (q15_t)0x4c05, (q15_t)0x4c00, (q15_t)0x4bfb, (q15_t)0x4bf6, (q15_t)0x4bf1, + (q15_t)0x4bec, (q15_t)0x4be7, (q15_t)0x4be2, (q15_t)0x4bdd, (q15_t)0x4bd8, (q15_t)0x4bd3, (q15_t)0x4bce, (q15_t)0x4bc9, + (q15_t)0x4bc4, (q15_t)0x4bbe, (q15_t)0x4bb9, (q15_t)0x4bb4, (q15_t)0x4baf, (q15_t)0x4baa, (q15_t)0x4ba5, (q15_t)0x4ba0, + (q15_t)0x4b9b, (q15_t)0x4b96, (q15_t)0x4b91, (q15_t)0x4b8c, (q15_t)0x4b87, (q15_t)0x4b82, (q15_t)0x4b7d, (q15_t)0x4b77, + (q15_t)0x4b72, (q15_t)0x4b6d, (q15_t)0x4b68, (q15_t)0x4b63, (q15_t)0x4b5e, (q15_t)0x4b59, (q15_t)0x4b54, (q15_t)0x4b4f, + (q15_t)0x4b4a, (q15_t)0x4b45, (q15_t)0x4b40, (q15_t)0x4b3b, (q15_t)0x4b35, (q15_t)0x4b30, (q15_t)0x4b2b, (q15_t)0x4b26, + (q15_t)0x4b21, (q15_t)0x4b1c, (q15_t)0x4b17, (q15_t)0x4b12, (q15_t)0x4b0d, (q15_t)0x4b08, (q15_t)0x4b03, (q15_t)0x4afd, + (q15_t)0x4af8, (q15_t)0x4af3, (q15_t)0x4aee, (q15_t)0x4ae9, (q15_t)0x4ae4, (q15_t)0x4adf, (q15_t)0x4ada, (q15_t)0x4ad5, + (q15_t)0x4ad0, (q15_t)0x4acb, (q15_t)0x4ac5, (q15_t)0x4ac0, (q15_t)0x4abb, (q15_t)0x4ab6, (q15_t)0x4ab1, (q15_t)0x4aac, + (q15_t)0x4aa7, (q15_t)0x4aa2, (q15_t)0x4a9d, (q15_t)0x4a97, (q15_t)0x4a92, (q15_t)0x4a8d, (q15_t)0x4a88, (q15_t)0x4a83, + (q15_t)0x4a7e, (q15_t)0x4a79, (q15_t)0x4a74, (q15_t)0x4a6f, (q15_t)0x4a6a, (q15_t)0x4a64, (q15_t)0x4a5f, (q15_t)0x4a5a, + (q15_t)0x4a55, (q15_t)0x4a50, (q15_t)0x4a4b, (q15_t)0x4a46, (q15_t)0x4a41, (q15_t)0x4a3b, (q15_t)0x4a36, (q15_t)0x4a31, + (q15_t)0x4a2c, (q15_t)0x4a27, (q15_t)0x4a22, (q15_t)0x4a1d, (q15_t)0x4a18, (q15_t)0x4a12, (q15_t)0x4a0d, (q15_t)0x4a08, + (q15_t)0x4a03, (q15_t)0x49fe, (q15_t)0x49f9, (q15_t)0x49f4, (q15_t)0x49ef, (q15_t)0x49e9, (q15_t)0x49e4, (q15_t)0x49df, + (q15_t)0x49da, (q15_t)0x49d5, (q15_t)0x49d0, (q15_t)0x49cb, (q15_t)0x49c6, (q15_t)0x49c0, (q15_t)0x49bb, (q15_t)0x49b6, + (q15_t)0x49b1, (q15_t)0x49ac, (q15_t)0x49a7, (q15_t)0x49a2, (q15_t)0x499c, (q15_t)0x4997, (q15_t)0x4992, (q15_t)0x498d, + (q15_t)0x4988, (q15_t)0x4983, (q15_t)0x497e, (q15_t)0x4978, (q15_t)0x4973, (q15_t)0x496e, (q15_t)0x4969, (q15_t)0x4964, + (q15_t)0x495f, (q15_t)0x495a, (q15_t)0x4954, (q15_t)0x494f, (q15_t)0x494a, (q15_t)0x4945, (q15_t)0x4940, (q15_t)0x493b, + (q15_t)0x4936, (q15_t)0x4930, (q15_t)0x492b, (q15_t)0x4926, (q15_t)0x4921, (q15_t)0x491c, (q15_t)0x4917, (q15_t)0x4911, + (q15_t)0x490c, (q15_t)0x4907, (q15_t)0x4902, (q15_t)0x48fd, (q15_t)0x48f8, (q15_t)0x48f2, (q15_t)0x48ed, (q15_t)0x48e8, + (q15_t)0x48e3, (q15_t)0x48de, (q15_t)0x48d9, (q15_t)0x48d3, (q15_t)0x48ce, (q15_t)0x48c9, (q15_t)0x48c4, (q15_t)0x48bf, + (q15_t)0x48ba, (q15_t)0x48b4, (q15_t)0x48af, (q15_t)0x48aa, (q15_t)0x48a5, (q15_t)0x48a0, (q15_t)0x489b, (q15_t)0x4895, + (q15_t)0x4890, (q15_t)0x488b, (q15_t)0x4886, (q15_t)0x4881, (q15_t)0x487c, (q15_t)0x4876, (q15_t)0x4871, (q15_t)0x486c, + (q15_t)0x4867, (q15_t)0x4862, (q15_t)0x485c, (q15_t)0x4857, (q15_t)0x4852, (q15_t)0x484d, (q15_t)0x4848, (q15_t)0x4843, + (q15_t)0x483d, (q15_t)0x4838, (q15_t)0x4833, (q15_t)0x482e, (q15_t)0x4829, (q15_t)0x4823, (q15_t)0x481e, (q15_t)0x4819, + (q15_t)0x4814, (q15_t)0x480f, (q15_t)0x4809, (q15_t)0x4804, (q15_t)0x47ff, (q15_t)0x47fa, (q15_t)0x47f5, (q15_t)0x47ef, + (q15_t)0x47ea, (q15_t)0x47e5, (q15_t)0x47e0, (q15_t)0x47db, (q15_t)0x47d5, (q15_t)0x47d0, (q15_t)0x47cb, (q15_t)0x47c6, + (q15_t)0x47c1, (q15_t)0x47bb, (q15_t)0x47b6, (q15_t)0x47b1, (q15_t)0x47ac, (q15_t)0x47a7, (q15_t)0x47a1, (q15_t)0x479c, + (q15_t)0x4797, (q15_t)0x4792, (q15_t)0x478d, (q15_t)0x4787, (q15_t)0x4782, (q15_t)0x477d, (q15_t)0x4778, (q15_t)0x4773, + (q15_t)0x476d, (q15_t)0x4768, (q15_t)0x4763, (q15_t)0x475e, (q15_t)0x4758, (q15_t)0x4753, (q15_t)0x474e, (q15_t)0x4749, + (q15_t)0x4744, (q15_t)0x473e, (q15_t)0x4739, (q15_t)0x4734, (q15_t)0x472f, (q15_t)0x4729, (q15_t)0x4724, (q15_t)0x471f, + (q15_t)0x471a, (q15_t)0x4715, (q15_t)0x470f, (q15_t)0x470a, (q15_t)0x4705, (q15_t)0x4700, (q15_t)0x46fa, (q15_t)0x46f5, + (q15_t)0x46f0, (q15_t)0x46eb, (q15_t)0x46e6, (q15_t)0x46e0, (q15_t)0x46db, (q15_t)0x46d6, (q15_t)0x46d1, (q15_t)0x46cb, + (q15_t)0x46c6, (q15_t)0x46c1, (q15_t)0x46bc, (q15_t)0x46b6, (q15_t)0x46b1, (q15_t)0x46ac, (q15_t)0x46a7, (q15_t)0x46a1, + (q15_t)0x469c, (q15_t)0x4697, (q15_t)0x4692, (q15_t)0x468d, (q15_t)0x4687, (q15_t)0x4682, (q15_t)0x467d, (q15_t)0x4678, + (q15_t)0x4672, (q15_t)0x466d, (q15_t)0x4668, (q15_t)0x4663, (q15_t)0x465d, (q15_t)0x4658, (q15_t)0x4653, (q15_t)0x464e, + (q15_t)0x4648, (q15_t)0x4643, (q15_t)0x463e, (q15_t)0x4639, (q15_t)0x4633, (q15_t)0x462e, (q15_t)0x4629, (q15_t)0x4624, + (q15_t)0x461e, (q15_t)0x4619, (q15_t)0x4614, (q15_t)0x460e, (q15_t)0x4609, (q15_t)0x4604, (q15_t)0x45ff, (q15_t)0x45f9, + (q15_t)0x45f4, (q15_t)0x45ef, (q15_t)0x45ea, (q15_t)0x45e4, (q15_t)0x45df, (q15_t)0x45da, (q15_t)0x45d5, (q15_t)0x45cf, + (q15_t)0x45ca, (q15_t)0x45c5, (q15_t)0x45c0, (q15_t)0x45ba, (q15_t)0x45b5, (q15_t)0x45b0, (q15_t)0x45aa, (q15_t)0x45a5, + (q15_t)0x45a0, (q15_t)0x459b, (q15_t)0x4595, (q15_t)0x4590, (q15_t)0x458b, (q15_t)0x4586, (q15_t)0x4580, (q15_t)0x457b, + (q15_t)0x4576, (q15_t)0x4570, (q15_t)0x456b, (q15_t)0x4566, (q15_t)0x4561, (q15_t)0x455b, (q15_t)0x4556, (q15_t)0x4551, + (q15_t)0x454b, (q15_t)0x4546, (q15_t)0x4541, (q15_t)0x453c, (q15_t)0x4536, (q15_t)0x4531, (q15_t)0x452c, (q15_t)0x4526, + (q15_t)0x4521, (q15_t)0x451c, (q15_t)0x4517, (q15_t)0x4511, (q15_t)0x450c, (q15_t)0x4507, (q15_t)0x4501, (q15_t)0x44fc, + (q15_t)0x44f7, (q15_t)0x44f2, (q15_t)0x44ec, (q15_t)0x44e7, (q15_t)0x44e2, (q15_t)0x44dc, (q15_t)0x44d7, (q15_t)0x44d2, + (q15_t)0x44cd, (q15_t)0x44c7, (q15_t)0x44c2, (q15_t)0x44bd, (q15_t)0x44b7, (q15_t)0x44b2, (q15_t)0x44ad, (q15_t)0x44a7, + (q15_t)0x44a2, (q15_t)0x449d, (q15_t)0x4497, (q15_t)0x4492, (q15_t)0x448d, (q15_t)0x4488, (q15_t)0x4482, (q15_t)0x447d, + (q15_t)0x4478, (q15_t)0x4472, (q15_t)0x446d, (q15_t)0x4468, (q15_t)0x4462, (q15_t)0x445d, (q15_t)0x4458, (q15_t)0x4452, + (q15_t)0x444d, (q15_t)0x4448, (q15_t)0x4443, (q15_t)0x443d, (q15_t)0x4438, (q15_t)0x4433, (q15_t)0x442d, (q15_t)0x4428, + (q15_t)0x4423, (q15_t)0x441d, (q15_t)0x4418, (q15_t)0x4413, (q15_t)0x440d, (q15_t)0x4408, (q15_t)0x4403, (q15_t)0x43fd, + (q15_t)0x43f8, (q15_t)0x43f3, (q15_t)0x43ed, (q15_t)0x43e8, (q15_t)0x43e3, (q15_t)0x43dd, (q15_t)0x43d8, (q15_t)0x43d3, + (q15_t)0x43cd, (q15_t)0x43c8, (q15_t)0x43c3, (q15_t)0x43bd, (q15_t)0x43b8, (q15_t)0x43b3, (q15_t)0x43ad, (q15_t)0x43a8, + (q15_t)0x43a3, (q15_t)0x439d, (q15_t)0x4398, (q15_t)0x4393, (q15_t)0x438d, (q15_t)0x4388, (q15_t)0x4383, (q15_t)0x437d, + (q15_t)0x4378, (q15_t)0x4373, (q15_t)0x436d, (q15_t)0x4368, (q15_t)0x4363, (q15_t)0x435d, (q15_t)0x4358, (q15_t)0x4353, + (q15_t)0x434d, (q15_t)0x4348, (q15_t)0x4343, (q15_t)0x433d, (q15_t)0x4338, (q15_t)0x4333, (q15_t)0x432d, (q15_t)0x4328, + (q15_t)0x4323, (q15_t)0x431d, (q15_t)0x4318, (q15_t)0x4313, (q15_t)0x430d, (q15_t)0x4308, (q15_t)0x4302, (q15_t)0x42fd, + (q15_t)0x42f8, (q15_t)0x42f2, (q15_t)0x42ed, (q15_t)0x42e8, (q15_t)0x42e2, (q15_t)0x42dd, (q15_t)0x42d8, (q15_t)0x42d2, + (q15_t)0x42cd, (q15_t)0x42c8, (q15_t)0x42c2, (q15_t)0x42bd, (q15_t)0x42b7, (q15_t)0x42b2, (q15_t)0x42ad, (q15_t)0x42a7, + (q15_t)0x42a2, (q15_t)0x429d, (q15_t)0x4297, (q15_t)0x4292, (q15_t)0x428d, (q15_t)0x4287, (q15_t)0x4282, (q15_t)0x427c, + (q15_t)0x4277, (q15_t)0x4272, (q15_t)0x426c, (q15_t)0x4267, (q15_t)0x4262, (q15_t)0x425c, (q15_t)0x4257, (q15_t)0x4251, + (q15_t)0x424c, (q15_t)0x4247, (q15_t)0x4241, (q15_t)0x423c, (q15_t)0x4237, (q15_t)0x4231, (q15_t)0x422c, (q15_t)0x4226, + (q15_t)0x4221, (q15_t)0x421c, (q15_t)0x4216, (q15_t)0x4211, (q15_t)0x420c, (q15_t)0x4206, (q15_t)0x4201, (q15_t)0x41fb, + (q15_t)0x41f6, (q15_t)0x41f1, (q15_t)0x41eb, (q15_t)0x41e6, (q15_t)0x41e0, (q15_t)0x41db, (q15_t)0x41d6, (q15_t)0x41d0, + (q15_t)0x41cb, (q15_t)0x41c6, (q15_t)0x41c0, (q15_t)0x41bb, (q15_t)0x41b5, (q15_t)0x41b0, (q15_t)0x41ab, (q15_t)0x41a5, + (q15_t)0x41a0, (q15_t)0x419a, (q15_t)0x4195, (q15_t)0x4190, (q15_t)0x418a, (q15_t)0x4185, (q15_t)0x417f, (q15_t)0x417a, + (q15_t)0x4175, (q15_t)0x416f, (q15_t)0x416a, (q15_t)0x4164, (q15_t)0x415f, (q15_t)0x415a, (q15_t)0x4154, (q15_t)0x414f, + (q15_t)0x4149, (q15_t)0x4144, (q15_t)0x413f, (q15_t)0x4139, (q15_t)0x4134, (q15_t)0x412e, (q15_t)0x4129, (q15_t)0x4124, + (q15_t)0x411e, (q15_t)0x4119, (q15_t)0x4113, (q15_t)0x410e, (q15_t)0x4108, (q15_t)0x4103, (q15_t)0x40fe, (q15_t)0x40f8, + (q15_t)0x40f3, (q15_t)0x40ed, (q15_t)0x40e8, (q15_t)0x40e3, (q15_t)0x40dd, (q15_t)0x40d8, (q15_t)0x40d2, (q15_t)0x40cd, + (q15_t)0x40c8, (q15_t)0x40c2, (q15_t)0x40bd, (q15_t)0x40b7, (q15_t)0x40b2, (q15_t)0x40ac, (q15_t)0x40a7, (q15_t)0x40a2, + (q15_t)0x409c, (q15_t)0x4097, (q15_t)0x4091, (q15_t)0x408c, (q15_t)0x4086, (q15_t)0x4081, (q15_t)0x407c, (q15_t)0x4076, + (q15_t)0x4071, (q15_t)0x406b, (q15_t)0x4066, (q15_t)0x4060, (q15_t)0x405b, (q15_t)0x4056, (q15_t)0x4050, (q15_t)0x404b, + (q15_t)0x4045, (q15_t)0x4040, (q15_t)0x403a, (q15_t)0x4035, (q15_t)0x4030, (q15_t)0x402a, (q15_t)0x4025, (q15_t)0x401f, + (q15_t)0x401a, (q15_t)0x4014, (q15_t)0x400f, (q15_t)0x4009, (q15_t)0x4004, (q15_t)0x3fff, (q15_t)0x3ff9, (q15_t)0x3ff4, + (q15_t)0x3fee, (q15_t)0x3fe9, (q15_t)0x3fe3, (q15_t)0x3fde, (q15_t)0x3fd8, (q15_t)0x3fd3, (q15_t)0x3fce, (q15_t)0x3fc8, + (q15_t)0x3fc3, (q15_t)0x3fbd, (q15_t)0x3fb8, (q15_t)0x3fb2, (q15_t)0x3fad, (q15_t)0x3fa7, (q15_t)0x3fa2, (q15_t)0x3f9d, + (q15_t)0x3f97, (q15_t)0x3f92, (q15_t)0x3f8c, (q15_t)0x3f87, (q15_t)0x3f81, (q15_t)0x3f7c, (q15_t)0x3f76, (q15_t)0x3f71, + (q15_t)0x3f6b, (q15_t)0x3f66, (q15_t)0x3f61, (q15_t)0x3f5b, (q15_t)0x3f56, (q15_t)0x3f50, (q15_t)0x3f4b, (q15_t)0x3f45, + (q15_t)0x3f40, (q15_t)0x3f3a, (q15_t)0x3f35, (q15_t)0x3f2f, (q15_t)0x3f2a, (q15_t)0x3f24, (q15_t)0x3f1f, (q15_t)0x3f1a, + (q15_t)0x3f14, (q15_t)0x3f0f, (q15_t)0x3f09, (q15_t)0x3f04, (q15_t)0x3efe, (q15_t)0x3ef9, (q15_t)0x3ef3, (q15_t)0x3eee, + (q15_t)0x3ee8, (q15_t)0x3ee3, (q15_t)0x3edd, (q15_t)0x3ed8, (q15_t)0x3ed2, (q15_t)0x3ecd, (q15_t)0x3ec7, (q15_t)0x3ec2, + (q15_t)0x3ebd, (q15_t)0x3eb7, (q15_t)0x3eb2, (q15_t)0x3eac, (q15_t)0x3ea7, (q15_t)0x3ea1, (q15_t)0x3e9c, (q15_t)0x3e96, + (q15_t)0x3e91, (q15_t)0x3e8b, (q15_t)0x3e86, (q15_t)0x3e80, (q15_t)0x3e7b, (q15_t)0x3e75, (q15_t)0x3e70, (q15_t)0x3e6a, + (q15_t)0x3e65, (q15_t)0x3e5f, (q15_t)0x3e5a, (q15_t)0x3e54, (q15_t)0x3e4f, (q15_t)0x3e49, (q15_t)0x3e44, (q15_t)0x3e3e, + (q15_t)0x3e39, (q15_t)0x3e33, (q15_t)0x3e2e, (q15_t)0x3e28, (q15_t)0x3e23, (q15_t)0x3e1d, (q15_t)0x3e18, (q15_t)0x3e12, + (q15_t)0x3e0d, (q15_t)0x3e07, (q15_t)0x3e02, (q15_t)0x3dfc, (q15_t)0x3df7, (q15_t)0x3df1, (q15_t)0x3dec, (q15_t)0x3de6, + (q15_t)0x3de1, (q15_t)0x3ddb, (q15_t)0x3dd6, (q15_t)0x3dd0, (q15_t)0x3dcb, (q15_t)0x3dc5, (q15_t)0x3dc0, (q15_t)0x3dba, + (q15_t)0x3db5, (q15_t)0x3daf, (q15_t)0x3daa, (q15_t)0x3da4, (q15_t)0x3d9f, (q15_t)0x3d99, (q15_t)0x3d94, (q15_t)0x3d8e, + (q15_t)0x3d89, (q15_t)0x3d83, (q15_t)0x3d7e, (q15_t)0x3d78, (q15_t)0x3d73, (q15_t)0x3d6d, (q15_t)0x3d68, (q15_t)0x3d62, + (q15_t)0x3d5d, (q15_t)0x3d57, (q15_t)0x3d52, (q15_t)0x3d4c, (q15_t)0x3d47, (q15_t)0x3d41, (q15_t)0x3d3c, (q15_t)0x3d36, + (q15_t)0x3d31, (q15_t)0x3d2b, (q15_t)0x3d26, (q15_t)0x3d20, (q15_t)0x3d1b, (q15_t)0x3d15, (q15_t)0x3d10, (q15_t)0x3d0a, + (q15_t)0x3d04, (q15_t)0x3cff, (q15_t)0x3cf9, (q15_t)0x3cf4, (q15_t)0x3cee, (q15_t)0x3ce9, (q15_t)0x3ce3, (q15_t)0x3cde, + (q15_t)0x3cd8, (q15_t)0x3cd3, (q15_t)0x3ccd, (q15_t)0x3cc8, (q15_t)0x3cc2, (q15_t)0x3cbd, (q15_t)0x3cb7, (q15_t)0x3cb2, + (q15_t)0x3cac, (q15_t)0x3ca7, (q15_t)0x3ca1, (q15_t)0x3c9b, (q15_t)0x3c96, (q15_t)0x3c90, (q15_t)0x3c8b, (q15_t)0x3c85, + (q15_t)0x3c80, (q15_t)0x3c7a, (q15_t)0x3c75, (q15_t)0x3c6f, (q15_t)0x3c6a, (q15_t)0x3c64, (q15_t)0x3c5f, (q15_t)0x3c59, + (q15_t)0x3c53, (q15_t)0x3c4e, (q15_t)0x3c48, (q15_t)0x3c43, (q15_t)0x3c3d, (q15_t)0x3c38, (q15_t)0x3c32, (q15_t)0x3c2d, + (q15_t)0x3c27, (q15_t)0x3c22, (q15_t)0x3c1c, (q15_t)0x3c16, (q15_t)0x3c11, (q15_t)0x3c0b, (q15_t)0x3c06, (q15_t)0x3c00, + (q15_t)0x3bfb, (q15_t)0x3bf5, (q15_t)0x3bf0, (q15_t)0x3bea, (q15_t)0x3be5, (q15_t)0x3bdf, (q15_t)0x3bd9, (q15_t)0x3bd4, + (q15_t)0x3bce, (q15_t)0x3bc9, (q15_t)0x3bc3, (q15_t)0x3bbe, (q15_t)0x3bb8, (q15_t)0x3bb3, (q15_t)0x3bad, (q15_t)0x3ba7, + (q15_t)0x3ba2, (q15_t)0x3b9c, (q15_t)0x3b97, (q15_t)0x3b91, (q15_t)0x3b8c, (q15_t)0x3b86, (q15_t)0x3b80, (q15_t)0x3b7b, + (q15_t)0x3b75, (q15_t)0x3b70, (q15_t)0x3b6a, (q15_t)0x3b65, (q15_t)0x3b5f, (q15_t)0x3b5a, (q15_t)0x3b54, (q15_t)0x3b4e, + (q15_t)0x3b49, (q15_t)0x3b43, (q15_t)0x3b3e, (q15_t)0x3b38, (q15_t)0x3b33, (q15_t)0x3b2d, (q15_t)0x3b27, (q15_t)0x3b22, + (q15_t)0x3b1c, (q15_t)0x3b17, (q15_t)0x3b11, (q15_t)0x3b0c, (q15_t)0x3b06, (q15_t)0x3b00, (q15_t)0x3afb, (q15_t)0x3af5, + (q15_t)0x3af0, (q15_t)0x3aea, (q15_t)0x3ae4, (q15_t)0x3adf, (q15_t)0x3ad9, (q15_t)0x3ad4, (q15_t)0x3ace, (q15_t)0x3ac9, + (q15_t)0x3ac3, (q15_t)0x3abd, (q15_t)0x3ab8, (q15_t)0x3ab2, (q15_t)0x3aad, (q15_t)0x3aa7, (q15_t)0x3aa2, (q15_t)0x3a9c, + (q15_t)0x3a96, (q15_t)0x3a91, (q15_t)0x3a8b, (q15_t)0x3a86, (q15_t)0x3a80, (q15_t)0x3a7a, (q15_t)0x3a75, (q15_t)0x3a6f, + (q15_t)0x3a6a, (q15_t)0x3a64, (q15_t)0x3a5e, (q15_t)0x3a59, (q15_t)0x3a53, (q15_t)0x3a4e, (q15_t)0x3a48, (q15_t)0x3a42, + (q15_t)0x3a3d, (q15_t)0x3a37, (q15_t)0x3a32, (q15_t)0x3a2c, (q15_t)0x3a26, (q15_t)0x3a21, (q15_t)0x3a1b, (q15_t)0x3a16, + (q15_t)0x3a10, (q15_t)0x3a0b, (q15_t)0x3a05, (q15_t)0x39ff, (q15_t)0x39fa, (q15_t)0x39f4, (q15_t)0x39ee, (q15_t)0x39e9, + (q15_t)0x39e3, (q15_t)0x39de, (q15_t)0x39d8, (q15_t)0x39d2, (q15_t)0x39cd, (q15_t)0x39c7, (q15_t)0x39c2, (q15_t)0x39bc, + (q15_t)0x39b6, (q15_t)0x39b1, (q15_t)0x39ab, (q15_t)0x39a6, (q15_t)0x39a0, (q15_t)0x399a, (q15_t)0x3995, (q15_t)0x398f, + (q15_t)0x398a, (q15_t)0x3984, (q15_t)0x397e, (q15_t)0x3979, (q15_t)0x3973, (q15_t)0x396d, (q15_t)0x3968, (q15_t)0x3962, + (q15_t)0x395d, (q15_t)0x3957, (q15_t)0x3951, (q15_t)0x394c, (q15_t)0x3946, (q15_t)0x3941, (q15_t)0x393b, (q15_t)0x3935, + (q15_t)0x3930, (q15_t)0x392a, (q15_t)0x3924, (q15_t)0x391f, (q15_t)0x3919, (q15_t)0x3914, (q15_t)0x390e, (q15_t)0x3908, + (q15_t)0x3903, (q15_t)0x38fd, (q15_t)0x38f7, (q15_t)0x38f2, (q15_t)0x38ec, (q15_t)0x38e7, (q15_t)0x38e1, (q15_t)0x38db, + (q15_t)0x38d6, (q15_t)0x38d0, (q15_t)0x38ca, (q15_t)0x38c5, (q15_t)0x38bf, (q15_t)0x38ba, (q15_t)0x38b4, (q15_t)0x38ae, + (q15_t)0x38a9, (q15_t)0x38a3, (q15_t)0x389d, (q15_t)0x3898, (q15_t)0x3892, (q15_t)0x388c, (q15_t)0x3887, (q15_t)0x3881, + (q15_t)0x387c, (q15_t)0x3876, (q15_t)0x3870, (q15_t)0x386b, (q15_t)0x3865, (q15_t)0x385f, (q15_t)0x385a, (q15_t)0x3854, + (q15_t)0x384e, (q15_t)0x3849, (q15_t)0x3843, (q15_t)0x383d, (q15_t)0x3838, (q15_t)0x3832, (q15_t)0x382d, (q15_t)0x3827, + (q15_t)0x3821, (q15_t)0x381c, (q15_t)0x3816, (q15_t)0x3810, (q15_t)0x380b, (q15_t)0x3805, (q15_t)0x37ff, (q15_t)0x37fa, + (q15_t)0x37f4, (q15_t)0x37ee, (q15_t)0x37e9, (q15_t)0x37e3, (q15_t)0x37dd, (q15_t)0x37d8, (q15_t)0x37d2, (q15_t)0x37cc, + (q15_t)0x37c7, (q15_t)0x37c1, (q15_t)0x37bc, (q15_t)0x37b6, (q15_t)0x37b0, (q15_t)0x37ab, (q15_t)0x37a5, (q15_t)0x379f, + (q15_t)0x379a, (q15_t)0x3794, (q15_t)0x378e, (q15_t)0x3789, (q15_t)0x3783, (q15_t)0x377d, (q15_t)0x3778, (q15_t)0x3772, + (q15_t)0x376c, (q15_t)0x3767, (q15_t)0x3761, (q15_t)0x375b, (q15_t)0x3756, (q15_t)0x3750, (q15_t)0x374a, (q15_t)0x3745, + (q15_t)0x373f, (q15_t)0x3739, (q15_t)0x3734, (q15_t)0x372e, (q15_t)0x3728, (q15_t)0x3723, (q15_t)0x371d, (q15_t)0x3717, + (q15_t)0x3712, (q15_t)0x370c, (q15_t)0x3706, (q15_t)0x3701, (q15_t)0x36fb, (q15_t)0x36f5, (q15_t)0x36f0, (q15_t)0x36ea, + (q15_t)0x36e4, (q15_t)0x36df, (q15_t)0x36d9, (q15_t)0x36d3, (q15_t)0x36ce, (q15_t)0x36c8, (q15_t)0x36c2, (q15_t)0x36bc, + (q15_t)0x36b7, (q15_t)0x36b1, (q15_t)0x36ab, (q15_t)0x36a6, (q15_t)0x36a0, (q15_t)0x369a, (q15_t)0x3695, (q15_t)0x368f, + (q15_t)0x3689, (q15_t)0x3684, (q15_t)0x367e, (q15_t)0x3678, (q15_t)0x3673, (q15_t)0x366d, (q15_t)0x3667, (q15_t)0x3662, + (q15_t)0x365c, (q15_t)0x3656, (q15_t)0x3650, (q15_t)0x364b, (q15_t)0x3645, (q15_t)0x363f, (q15_t)0x363a, (q15_t)0x3634, + (q15_t)0x362e, (q15_t)0x3629, (q15_t)0x3623, (q15_t)0x361d, (q15_t)0x3618, (q15_t)0x3612, (q15_t)0x360c, (q15_t)0x3606, + (q15_t)0x3601, (q15_t)0x35fb, (q15_t)0x35f5, (q15_t)0x35f0, (q15_t)0x35ea, (q15_t)0x35e4, (q15_t)0x35df, (q15_t)0x35d9, + (q15_t)0x35d3, (q15_t)0x35cd, (q15_t)0x35c8, (q15_t)0x35c2, (q15_t)0x35bc, (q15_t)0x35b7, (q15_t)0x35b1, (q15_t)0x35ab, + (q15_t)0x35a6, (q15_t)0x35a0, (q15_t)0x359a, (q15_t)0x3594, (q15_t)0x358f, (q15_t)0x3589, (q15_t)0x3583, (q15_t)0x357e, + (q15_t)0x3578, (q15_t)0x3572, (q15_t)0x356c, (q15_t)0x3567, (q15_t)0x3561, (q15_t)0x355b, (q15_t)0x3556, (q15_t)0x3550, + (q15_t)0x354a, (q15_t)0x3544, (q15_t)0x353f, (q15_t)0x3539, (q15_t)0x3533, (q15_t)0x352e, (q15_t)0x3528, (q15_t)0x3522, + (q15_t)0x351c, (q15_t)0x3517, (q15_t)0x3511, (q15_t)0x350b, (q15_t)0x3506, (q15_t)0x3500, (q15_t)0x34fa, (q15_t)0x34f4, + (q15_t)0x34ef, (q15_t)0x34e9, (q15_t)0x34e3, (q15_t)0x34de, (q15_t)0x34d8, (q15_t)0x34d2, (q15_t)0x34cc, (q15_t)0x34c7, + (q15_t)0x34c1, (q15_t)0x34bb, (q15_t)0x34b6, (q15_t)0x34b0, (q15_t)0x34aa, (q15_t)0x34a4, (q15_t)0x349f, (q15_t)0x3499, + (q15_t)0x3493, (q15_t)0x348d, (q15_t)0x3488, (q15_t)0x3482, (q15_t)0x347c, (q15_t)0x3476, (q15_t)0x3471, (q15_t)0x346b, + (q15_t)0x3465, (q15_t)0x3460, (q15_t)0x345a, (q15_t)0x3454, (q15_t)0x344e, (q15_t)0x3449, (q15_t)0x3443, (q15_t)0x343d, + (q15_t)0x3437, (q15_t)0x3432, (q15_t)0x342c, (q15_t)0x3426, (q15_t)0x3420, (q15_t)0x341b, (q15_t)0x3415, (q15_t)0x340f, + (q15_t)0x340a, (q15_t)0x3404, (q15_t)0x33fe, (q15_t)0x33f8, (q15_t)0x33f3, (q15_t)0x33ed, (q15_t)0x33e7, (q15_t)0x33e1, + (q15_t)0x33dc, (q15_t)0x33d6, (q15_t)0x33d0, (q15_t)0x33ca, (q15_t)0x33c5, (q15_t)0x33bf, (q15_t)0x33b9, (q15_t)0x33b3, + (q15_t)0x33ae, (q15_t)0x33a8, (q15_t)0x33a2, (q15_t)0x339c, (q15_t)0x3397, (q15_t)0x3391, (q15_t)0x338b, (q15_t)0x3385, + (q15_t)0x3380, (q15_t)0x337a, (q15_t)0x3374, (q15_t)0x336e, (q15_t)0x3369, (q15_t)0x3363, (q15_t)0x335d, (q15_t)0x3357, + (q15_t)0x3352, (q15_t)0x334c, (q15_t)0x3346, (q15_t)0x3340, (q15_t)0x333b, (q15_t)0x3335, (q15_t)0x332f, (q15_t)0x3329, + (q15_t)0x3324, (q15_t)0x331e, (q15_t)0x3318, (q15_t)0x3312, (q15_t)0x330c, (q15_t)0x3307, (q15_t)0x3301, (q15_t)0x32fb, + (q15_t)0x32f5, (q15_t)0x32f0, (q15_t)0x32ea, (q15_t)0x32e4, (q15_t)0x32de, (q15_t)0x32d9, (q15_t)0x32d3, (q15_t)0x32cd, + (q15_t)0x32c7, (q15_t)0x32c2, (q15_t)0x32bc, (q15_t)0x32b6, (q15_t)0x32b0, (q15_t)0x32aa, (q15_t)0x32a5, (q15_t)0x329f, + (q15_t)0x3299, (q15_t)0x3293, (q15_t)0x328e, (q15_t)0x3288, (q15_t)0x3282, (q15_t)0x327c, (q15_t)0x3276, (q15_t)0x3271, + (q15_t)0x326b, (q15_t)0x3265, (q15_t)0x325f, (q15_t)0x325a, (q15_t)0x3254, (q15_t)0x324e, (q15_t)0x3248, (q15_t)0x3243, + (q15_t)0x323d, (q15_t)0x3237, (q15_t)0x3231, (q15_t)0x322b, (q15_t)0x3226, (q15_t)0x3220, (q15_t)0x321a, (q15_t)0x3214, + (q15_t)0x320e, (q15_t)0x3209, (q15_t)0x3203, (q15_t)0x31fd, (q15_t)0x31f7, (q15_t)0x31f2, (q15_t)0x31ec, (q15_t)0x31e6, + (q15_t)0x31e0, (q15_t)0x31da, (q15_t)0x31d5, (q15_t)0x31cf, (q15_t)0x31c9, (q15_t)0x31c3, (q15_t)0x31bd, (q15_t)0x31b8, + (q15_t)0x31b2, (q15_t)0x31ac, (q15_t)0x31a6, (q15_t)0x31a1, (q15_t)0x319b, (q15_t)0x3195, (q15_t)0x318f, (q15_t)0x3189, + (q15_t)0x3184, (q15_t)0x317e, (q15_t)0x3178, (q15_t)0x3172, (q15_t)0x316c, (q15_t)0x3167, (q15_t)0x3161, (q15_t)0x315b, + (q15_t)0x3155, (q15_t)0x314f, (q15_t)0x314a, (q15_t)0x3144, (q15_t)0x313e, (q15_t)0x3138, (q15_t)0x3132, (q15_t)0x312d, + (q15_t)0x3127, (q15_t)0x3121, (q15_t)0x311b, (q15_t)0x3115, (q15_t)0x3110, (q15_t)0x310a, (q15_t)0x3104, (q15_t)0x30fe, + (q15_t)0x30f8, (q15_t)0x30f3, (q15_t)0x30ed, (q15_t)0x30e7, (q15_t)0x30e1, (q15_t)0x30db, (q15_t)0x30d6, (q15_t)0x30d0, + (q15_t)0x30ca, (q15_t)0x30c4, (q15_t)0x30be, (q15_t)0x30b8, (q15_t)0x30b3, (q15_t)0x30ad, (q15_t)0x30a7, (q15_t)0x30a1, + (q15_t)0x309b, (q15_t)0x3096, (q15_t)0x3090, (q15_t)0x308a, (q15_t)0x3084, (q15_t)0x307e, (q15_t)0x3079, (q15_t)0x3073, + (q15_t)0x306d, (q15_t)0x3067, (q15_t)0x3061, (q15_t)0x305b, (q15_t)0x3056, (q15_t)0x3050, (q15_t)0x304a, (q15_t)0x3044, + (q15_t)0x303e, (q15_t)0x3039, (q15_t)0x3033, (q15_t)0x302d, (q15_t)0x3027, (q15_t)0x3021, (q15_t)0x301b, (q15_t)0x3016, + (q15_t)0x3010, (q15_t)0x300a, (q15_t)0x3004, (q15_t)0x2ffe, (q15_t)0x2ff8, (q15_t)0x2ff3, (q15_t)0x2fed, (q15_t)0x2fe7, + (q15_t)0x2fe1, (q15_t)0x2fdb, (q15_t)0x2fd6, (q15_t)0x2fd0, (q15_t)0x2fca, (q15_t)0x2fc4, (q15_t)0x2fbe, (q15_t)0x2fb8, + (q15_t)0x2fb3, (q15_t)0x2fad, (q15_t)0x2fa7, (q15_t)0x2fa1, (q15_t)0x2f9b, (q15_t)0x2f95, (q15_t)0x2f90, (q15_t)0x2f8a, + (q15_t)0x2f84, (q15_t)0x2f7e, (q15_t)0x2f78, (q15_t)0x2f72, (q15_t)0x2f6d, (q15_t)0x2f67, (q15_t)0x2f61, (q15_t)0x2f5b, + (q15_t)0x2f55, (q15_t)0x2f4f, (q15_t)0x2f4a, (q15_t)0x2f44, (q15_t)0x2f3e, (q15_t)0x2f38, (q15_t)0x2f32, (q15_t)0x2f2c, + (q15_t)0x2f27, (q15_t)0x2f21, (q15_t)0x2f1b, (q15_t)0x2f15, (q15_t)0x2f0f, (q15_t)0x2f09, (q15_t)0x2f03, (q15_t)0x2efe, + (q15_t)0x2ef8, (q15_t)0x2ef2, (q15_t)0x2eec, (q15_t)0x2ee6, (q15_t)0x2ee0, (q15_t)0x2edb, (q15_t)0x2ed5, (q15_t)0x2ecf, + (q15_t)0x2ec9, (q15_t)0x2ec3, (q15_t)0x2ebd, (q15_t)0x2eb7, (q15_t)0x2eb2, (q15_t)0x2eac, (q15_t)0x2ea6, (q15_t)0x2ea0, + (q15_t)0x2e9a, (q15_t)0x2e94, (q15_t)0x2e8e, (q15_t)0x2e89, (q15_t)0x2e83, (q15_t)0x2e7d, (q15_t)0x2e77, (q15_t)0x2e71, + (q15_t)0x2e6b, (q15_t)0x2e65, (q15_t)0x2e60, (q15_t)0x2e5a, (q15_t)0x2e54, (q15_t)0x2e4e, (q15_t)0x2e48, (q15_t)0x2e42, + (q15_t)0x2e3c, (q15_t)0x2e37, (q15_t)0x2e31, (q15_t)0x2e2b, (q15_t)0x2e25, (q15_t)0x2e1f, (q15_t)0x2e19, (q15_t)0x2e13, + (q15_t)0x2e0e, (q15_t)0x2e08, (q15_t)0x2e02, (q15_t)0x2dfc, (q15_t)0x2df6, (q15_t)0x2df0, (q15_t)0x2dea, (q15_t)0x2de5, + (q15_t)0x2ddf, (q15_t)0x2dd9, (q15_t)0x2dd3, (q15_t)0x2dcd, (q15_t)0x2dc7, (q15_t)0x2dc1, (q15_t)0x2dbb, (q15_t)0x2db6, + (q15_t)0x2db0, (q15_t)0x2daa, (q15_t)0x2da4, (q15_t)0x2d9e, (q15_t)0x2d98, (q15_t)0x2d92, (q15_t)0x2d8d, (q15_t)0x2d87, + (q15_t)0x2d81, (q15_t)0x2d7b, (q15_t)0x2d75, (q15_t)0x2d6f, (q15_t)0x2d69, (q15_t)0x2d63, (q15_t)0x2d5e, (q15_t)0x2d58, + (q15_t)0x2d52, (q15_t)0x2d4c, (q15_t)0x2d46, (q15_t)0x2d40, (q15_t)0x2d3a, (q15_t)0x2d34, (q15_t)0x2d2f, (q15_t)0x2d29, + (q15_t)0x2d23, (q15_t)0x2d1d, (q15_t)0x2d17, (q15_t)0x2d11, (q15_t)0x2d0b, (q15_t)0x2d05, (q15_t)0x2cff, (q15_t)0x2cfa, + (q15_t)0x2cf4, (q15_t)0x2cee, (q15_t)0x2ce8, (q15_t)0x2ce2, (q15_t)0x2cdc, (q15_t)0x2cd6, (q15_t)0x2cd0, (q15_t)0x2ccb, + (q15_t)0x2cc5, (q15_t)0x2cbf, (q15_t)0x2cb9, (q15_t)0x2cb3, (q15_t)0x2cad, (q15_t)0x2ca7, (q15_t)0x2ca1, (q15_t)0x2c9b, + (q15_t)0x2c96, (q15_t)0x2c90, (q15_t)0x2c8a, (q15_t)0x2c84, (q15_t)0x2c7e, (q15_t)0x2c78, (q15_t)0x2c72, (q15_t)0x2c6c, + (q15_t)0x2c66, (q15_t)0x2c61, (q15_t)0x2c5b, (q15_t)0x2c55, (q15_t)0x2c4f, (q15_t)0x2c49, (q15_t)0x2c43, (q15_t)0x2c3d, + (q15_t)0x2c37, (q15_t)0x2c31, (q15_t)0x2c2b, (q15_t)0x2c26, (q15_t)0x2c20, (q15_t)0x2c1a, (q15_t)0x2c14, (q15_t)0x2c0e, + (q15_t)0x2c08, (q15_t)0x2c02, (q15_t)0x2bfc, (q15_t)0x2bf6, (q15_t)0x2bf0, (q15_t)0x2beb, (q15_t)0x2be5, (q15_t)0x2bdf, + (q15_t)0x2bd9, (q15_t)0x2bd3, (q15_t)0x2bcd, (q15_t)0x2bc7, (q15_t)0x2bc1, (q15_t)0x2bbb, (q15_t)0x2bb5, (q15_t)0x2bb0, + (q15_t)0x2baa, (q15_t)0x2ba4, (q15_t)0x2b9e, (q15_t)0x2b98, (q15_t)0x2b92, (q15_t)0x2b8c, (q15_t)0x2b86, (q15_t)0x2b80, + (q15_t)0x2b7a, (q15_t)0x2b74, (q15_t)0x2b6f, (q15_t)0x2b69, (q15_t)0x2b63, (q15_t)0x2b5d, (q15_t)0x2b57, (q15_t)0x2b51, + (q15_t)0x2b4b, (q15_t)0x2b45, (q15_t)0x2b3f, (q15_t)0x2b39, (q15_t)0x2b33, (q15_t)0x2b2d, (q15_t)0x2b28, (q15_t)0x2b22, + (q15_t)0x2b1c, (q15_t)0x2b16, (q15_t)0x2b10, (q15_t)0x2b0a, (q15_t)0x2b04, (q15_t)0x2afe, (q15_t)0x2af8, (q15_t)0x2af2, + (q15_t)0x2aec, (q15_t)0x2ae6, (q15_t)0x2ae1, (q15_t)0x2adb, (q15_t)0x2ad5, (q15_t)0x2acf, (q15_t)0x2ac9, (q15_t)0x2ac3, + (q15_t)0x2abd, (q15_t)0x2ab7, (q15_t)0x2ab1, (q15_t)0x2aab, (q15_t)0x2aa5, (q15_t)0x2a9f, (q15_t)0x2a99, (q15_t)0x2a94, + (q15_t)0x2a8e, (q15_t)0x2a88, (q15_t)0x2a82, (q15_t)0x2a7c, (q15_t)0x2a76, (q15_t)0x2a70, (q15_t)0x2a6a, (q15_t)0x2a64, + (q15_t)0x2a5e, (q15_t)0x2a58, (q15_t)0x2a52, (q15_t)0x2a4c, (q15_t)0x2a47, (q15_t)0x2a41, (q15_t)0x2a3b, (q15_t)0x2a35, + (q15_t)0x2a2f, (q15_t)0x2a29, (q15_t)0x2a23, (q15_t)0x2a1d, (q15_t)0x2a17, (q15_t)0x2a11, (q15_t)0x2a0b, (q15_t)0x2a05, + (q15_t)0x29ff, (q15_t)0x29f9, (q15_t)0x29f3, (q15_t)0x29ee, (q15_t)0x29e8, (q15_t)0x29e2, (q15_t)0x29dc, (q15_t)0x29d6, + (q15_t)0x29d0, (q15_t)0x29ca, (q15_t)0x29c4, (q15_t)0x29be, (q15_t)0x29b8, (q15_t)0x29b2, (q15_t)0x29ac, (q15_t)0x29a6, + (q15_t)0x29a0, (q15_t)0x299a, (q15_t)0x2994, (q15_t)0x298e, (q15_t)0x2989, (q15_t)0x2983, (q15_t)0x297d, (q15_t)0x2977, + (q15_t)0x2971, (q15_t)0x296b, (q15_t)0x2965, (q15_t)0x295f, (q15_t)0x2959, (q15_t)0x2953, (q15_t)0x294d, (q15_t)0x2947, + (q15_t)0x2941, (q15_t)0x293b, (q15_t)0x2935, (q15_t)0x292f, (q15_t)0x2929, (q15_t)0x2923, (q15_t)0x291d, (q15_t)0x2918, + (q15_t)0x2912, (q15_t)0x290c, (q15_t)0x2906, (q15_t)0x2900, (q15_t)0x28fa, (q15_t)0x28f4, (q15_t)0x28ee, (q15_t)0x28e8, + (q15_t)0x28e2, (q15_t)0x28dc, (q15_t)0x28d6, (q15_t)0x28d0, (q15_t)0x28ca, (q15_t)0x28c4, (q15_t)0x28be, (q15_t)0x28b8, + (q15_t)0x28b2, (q15_t)0x28ac, (q15_t)0x28a6, (q15_t)0x28a0, (q15_t)0x289a, (q15_t)0x2895, (q15_t)0x288f, (q15_t)0x2889, + (q15_t)0x2883, (q15_t)0x287d, (q15_t)0x2877, (q15_t)0x2871, (q15_t)0x286b, (q15_t)0x2865, (q15_t)0x285f, (q15_t)0x2859, + (q15_t)0x2853, (q15_t)0x284d, (q15_t)0x2847, (q15_t)0x2841, (q15_t)0x283b, (q15_t)0x2835, (q15_t)0x282f, (q15_t)0x2829, + (q15_t)0x2823, (q15_t)0x281d, (q15_t)0x2817, (q15_t)0x2811, (q15_t)0x280b, (q15_t)0x2805, (q15_t)0x27ff, (q15_t)0x27f9, + (q15_t)0x27f3, (q15_t)0x27ee, (q15_t)0x27e8, (q15_t)0x27e2, (q15_t)0x27dc, (q15_t)0x27d6, (q15_t)0x27d0, (q15_t)0x27ca, + (q15_t)0x27c4, (q15_t)0x27be, (q15_t)0x27b8, (q15_t)0x27b2, (q15_t)0x27ac, (q15_t)0x27a6, (q15_t)0x27a0, (q15_t)0x279a, + (q15_t)0x2794, (q15_t)0x278e, (q15_t)0x2788, (q15_t)0x2782, (q15_t)0x277c, (q15_t)0x2776, (q15_t)0x2770, (q15_t)0x276a, + (q15_t)0x2764, (q15_t)0x275e, (q15_t)0x2758, (q15_t)0x2752, (q15_t)0x274c, (q15_t)0x2746, (q15_t)0x2740, (q15_t)0x273a, + (q15_t)0x2734, (q15_t)0x272e, (q15_t)0x2728, (q15_t)0x2722, (q15_t)0x271c, (q15_t)0x2716, (q15_t)0x2710, (q15_t)0x270a, + (q15_t)0x2704, (q15_t)0x26fe, (q15_t)0x26f8, (q15_t)0x26f2, (q15_t)0x26ec, (q15_t)0x26e7, (q15_t)0x26e1, (q15_t)0x26db, + (q15_t)0x26d5, (q15_t)0x26cf, (q15_t)0x26c9, (q15_t)0x26c3, (q15_t)0x26bd, (q15_t)0x26b7, (q15_t)0x26b1, (q15_t)0x26ab, + (q15_t)0x26a5, (q15_t)0x269f, (q15_t)0x2699, (q15_t)0x2693, (q15_t)0x268d, (q15_t)0x2687, (q15_t)0x2681, (q15_t)0x267b, + (q15_t)0x2675, (q15_t)0x266f, (q15_t)0x2669, (q15_t)0x2663, (q15_t)0x265d, (q15_t)0x2657, (q15_t)0x2651, (q15_t)0x264b, + (q15_t)0x2645, (q15_t)0x263f, (q15_t)0x2639, (q15_t)0x2633, (q15_t)0x262d, (q15_t)0x2627, (q15_t)0x2621, (q15_t)0x261b, + (q15_t)0x2615, (q15_t)0x260f, (q15_t)0x2609, (q15_t)0x2603, (q15_t)0x25fd, (q15_t)0x25f7, (q15_t)0x25f1, (q15_t)0x25eb, + (q15_t)0x25e5, (q15_t)0x25df, (q15_t)0x25d9, (q15_t)0x25d3, (q15_t)0x25cd, (q15_t)0x25c7, (q15_t)0x25c1, (q15_t)0x25bb, + (q15_t)0x25b5, (q15_t)0x25af, (q15_t)0x25a9, (q15_t)0x25a3, (q15_t)0x259d, (q15_t)0x2597, (q15_t)0x2591, (q15_t)0x258b, + (q15_t)0x2585, (q15_t)0x257f, (q15_t)0x2579, (q15_t)0x2573, (q15_t)0x256d, (q15_t)0x2567, (q15_t)0x2561, (q15_t)0x255b, + (q15_t)0x2555, (q15_t)0x254f, (q15_t)0x2549, (q15_t)0x2543, (q15_t)0x253d, (q15_t)0x2537, (q15_t)0x2531, (q15_t)0x252b, + (q15_t)0x2525, (q15_t)0x251f, (q15_t)0x2519, (q15_t)0x2513, (q15_t)0x250c, (q15_t)0x2506, (q15_t)0x2500, (q15_t)0x24fa, + (q15_t)0x24f4, (q15_t)0x24ee, (q15_t)0x24e8, (q15_t)0x24e2, (q15_t)0x24dc, (q15_t)0x24d6, (q15_t)0x24d0, (q15_t)0x24ca, + (q15_t)0x24c4, (q15_t)0x24be, (q15_t)0x24b8, (q15_t)0x24b2, (q15_t)0x24ac, (q15_t)0x24a6, (q15_t)0x24a0, (q15_t)0x249a, + (q15_t)0x2494, (q15_t)0x248e, (q15_t)0x2488, (q15_t)0x2482, (q15_t)0x247c, (q15_t)0x2476, (q15_t)0x2470, (q15_t)0x246a, + (q15_t)0x2464, (q15_t)0x245e, (q15_t)0x2458, (q15_t)0x2452, (q15_t)0x244c, (q15_t)0x2446, (q15_t)0x2440, (q15_t)0x243a, + (q15_t)0x2434, (q15_t)0x242e, (q15_t)0x2428, (q15_t)0x2422, (q15_t)0x241c, (q15_t)0x2416, (q15_t)0x2410, (q15_t)0x240a, + (q15_t)0x2404, (q15_t)0x23fd, (q15_t)0x23f7, (q15_t)0x23f1, (q15_t)0x23eb, (q15_t)0x23e5, (q15_t)0x23df, (q15_t)0x23d9, + (q15_t)0x23d3, (q15_t)0x23cd, (q15_t)0x23c7, (q15_t)0x23c1, (q15_t)0x23bb, (q15_t)0x23b5, (q15_t)0x23af, (q15_t)0x23a9, + (q15_t)0x23a3, (q15_t)0x239d, (q15_t)0x2397, (q15_t)0x2391, (q15_t)0x238b, (q15_t)0x2385, (q15_t)0x237f, (q15_t)0x2379, + (q15_t)0x2373, (q15_t)0x236d, (q15_t)0x2367, (q15_t)0x2361, (q15_t)0x235b, (q15_t)0x2355, (q15_t)0x234e, (q15_t)0x2348, + (q15_t)0x2342, (q15_t)0x233c, (q15_t)0x2336, (q15_t)0x2330, (q15_t)0x232a, (q15_t)0x2324, (q15_t)0x231e, (q15_t)0x2318, + (q15_t)0x2312, (q15_t)0x230c, (q15_t)0x2306, (q15_t)0x2300, (q15_t)0x22fa, (q15_t)0x22f4, (q15_t)0x22ee, (q15_t)0x22e8, + (q15_t)0x22e2, (q15_t)0x22dc, (q15_t)0x22d6, (q15_t)0x22d0, (q15_t)0x22ca, (q15_t)0x22c4, (q15_t)0x22bd, (q15_t)0x22b7, + (q15_t)0x22b1, (q15_t)0x22ab, (q15_t)0x22a5, (q15_t)0x229f, (q15_t)0x2299, (q15_t)0x2293, (q15_t)0x228d, (q15_t)0x2287, + (q15_t)0x2281, (q15_t)0x227b, (q15_t)0x2275, (q15_t)0x226f, (q15_t)0x2269, (q15_t)0x2263, (q15_t)0x225d, (q15_t)0x2257, + (q15_t)0x2251, (q15_t)0x224a, (q15_t)0x2244, (q15_t)0x223e, (q15_t)0x2238, (q15_t)0x2232, (q15_t)0x222c, (q15_t)0x2226, + (q15_t)0x2220, (q15_t)0x221a, (q15_t)0x2214, (q15_t)0x220e, (q15_t)0x2208, (q15_t)0x2202, (q15_t)0x21fc, (q15_t)0x21f6, + (q15_t)0x21f0, (q15_t)0x21ea, (q15_t)0x21e4, (q15_t)0x21dd, (q15_t)0x21d7, (q15_t)0x21d1, (q15_t)0x21cb, (q15_t)0x21c5, + (q15_t)0x21bf, (q15_t)0x21b9, (q15_t)0x21b3, (q15_t)0x21ad, (q15_t)0x21a7, (q15_t)0x21a1, (q15_t)0x219b, (q15_t)0x2195, + (q15_t)0x218f, (q15_t)0x2189, (q15_t)0x2183, (q15_t)0x217c, (q15_t)0x2176, (q15_t)0x2170, (q15_t)0x216a, (q15_t)0x2164, + (q15_t)0x215e, (q15_t)0x2158, (q15_t)0x2152, (q15_t)0x214c, (q15_t)0x2146, (q15_t)0x2140, (q15_t)0x213a, (q15_t)0x2134, + (q15_t)0x212e, (q15_t)0x2128, (q15_t)0x2121, (q15_t)0x211b, (q15_t)0x2115, (q15_t)0x210f, (q15_t)0x2109, (q15_t)0x2103, + (q15_t)0x20fd, (q15_t)0x20f7, (q15_t)0x20f1, (q15_t)0x20eb, (q15_t)0x20e5, (q15_t)0x20df, (q15_t)0x20d9, (q15_t)0x20d3, + (q15_t)0x20cc, (q15_t)0x20c6, (q15_t)0x20c0, (q15_t)0x20ba, (q15_t)0x20b4, (q15_t)0x20ae, (q15_t)0x20a8, (q15_t)0x20a2, + (q15_t)0x209c, (q15_t)0x2096, (q15_t)0x2090, (q15_t)0x208a, (q15_t)0x2084, (q15_t)0x207e, (q15_t)0x2077, (q15_t)0x2071, + (q15_t)0x206b, (q15_t)0x2065, (q15_t)0x205f, (q15_t)0x2059, (q15_t)0x2053, (q15_t)0x204d, (q15_t)0x2047, (q15_t)0x2041, + (q15_t)0x203b, (q15_t)0x2035, (q15_t)0x202e, (q15_t)0x2028, (q15_t)0x2022, (q15_t)0x201c, (q15_t)0x2016, (q15_t)0x2010, + (q15_t)0x200a, (q15_t)0x2004, (q15_t)0x1ffe, (q15_t)0x1ff8, (q15_t)0x1ff2, (q15_t)0x1fec, (q15_t)0x1fe5, (q15_t)0x1fdf, + (q15_t)0x1fd9, (q15_t)0x1fd3, (q15_t)0x1fcd, (q15_t)0x1fc7, (q15_t)0x1fc1, (q15_t)0x1fbb, (q15_t)0x1fb5, (q15_t)0x1faf, + (q15_t)0x1fa9, (q15_t)0x1fa3, (q15_t)0x1f9c, (q15_t)0x1f96, (q15_t)0x1f90, (q15_t)0x1f8a, (q15_t)0x1f84, (q15_t)0x1f7e, + (q15_t)0x1f78, (q15_t)0x1f72, (q15_t)0x1f6c, (q15_t)0x1f66, (q15_t)0x1f60, (q15_t)0x1f59, (q15_t)0x1f53, (q15_t)0x1f4d, + (q15_t)0x1f47, (q15_t)0x1f41, (q15_t)0x1f3b, (q15_t)0x1f35, (q15_t)0x1f2f, (q15_t)0x1f29, (q15_t)0x1f23, (q15_t)0x1f1d, + (q15_t)0x1f16, (q15_t)0x1f10, (q15_t)0x1f0a, (q15_t)0x1f04, (q15_t)0x1efe, (q15_t)0x1ef8, (q15_t)0x1ef2, (q15_t)0x1eec, + (q15_t)0x1ee6, (q15_t)0x1ee0, (q15_t)0x1ed9, (q15_t)0x1ed3, (q15_t)0x1ecd, (q15_t)0x1ec7, (q15_t)0x1ec1, (q15_t)0x1ebb, + (q15_t)0x1eb5, (q15_t)0x1eaf, (q15_t)0x1ea9, (q15_t)0x1ea3, (q15_t)0x1e9c, (q15_t)0x1e96, (q15_t)0x1e90, (q15_t)0x1e8a, + (q15_t)0x1e84, (q15_t)0x1e7e, (q15_t)0x1e78, (q15_t)0x1e72, (q15_t)0x1e6c, (q15_t)0x1e66, (q15_t)0x1e5f, (q15_t)0x1e59, + (q15_t)0x1e53, (q15_t)0x1e4d, (q15_t)0x1e47, (q15_t)0x1e41, (q15_t)0x1e3b, (q15_t)0x1e35, (q15_t)0x1e2f, (q15_t)0x1e29, + (q15_t)0x1e22, (q15_t)0x1e1c, (q15_t)0x1e16, (q15_t)0x1e10, (q15_t)0x1e0a, (q15_t)0x1e04, (q15_t)0x1dfe, (q15_t)0x1df8, + (q15_t)0x1df2, (q15_t)0x1deb, (q15_t)0x1de5, (q15_t)0x1ddf, (q15_t)0x1dd9, (q15_t)0x1dd3, (q15_t)0x1dcd, (q15_t)0x1dc7, + (q15_t)0x1dc1, (q15_t)0x1dbb, (q15_t)0x1db4, (q15_t)0x1dae, (q15_t)0x1da8, (q15_t)0x1da2, (q15_t)0x1d9c, (q15_t)0x1d96, + (q15_t)0x1d90, (q15_t)0x1d8a, (q15_t)0x1d84, (q15_t)0x1d7d, (q15_t)0x1d77, (q15_t)0x1d71, (q15_t)0x1d6b, (q15_t)0x1d65, + (q15_t)0x1d5f, (q15_t)0x1d59, (q15_t)0x1d53, (q15_t)0x1d4c, (q15_t)0x1d46, (q15_t)0x1d40, (q15_t)0x1d3a, (q15_t)0x1d34, + (q15_t)0x1d2e, (q15_t)0x1d28, (q15_t)0x1d22, (q15_t)0x1d1c, (q15_t)0x1d15, (q15_t)0x1d0f, (q15_t)0x1d09, (q15_t)0x1d03, + (q15_t)0x1cfd, (q15_t)0x1cf7, (q15_t)0x1cf1, (q15_t)0x1ceb, (q15_t)0x1ce4, (q15_t)0x1cde, (q15_t)0x1cd8, (q15_t)0x1cd2, + (q15_t)0x1ccc, (q15_t)0x1cc6, (q15_t)0x1cc0, (q15_t)0x1cba, (q15_t)0x1cb3, (q15_t)0x1cad, (q15_t)0x1ca7, (q15_t)0x1ca1, + (q15_t)0x1c9b, (q15_t)0x1c95, (q15_t)0x1c8f, (q15_t)0x1c89, (q15_t)0x1c83, (q15_t)0x1c7c, (q15_t)0x1c76, (q15_t)0x1c70, + (q15_t)0x1c6a, (q15_t)0x1c64, (q15_t)0x1c5e, (q15_t)0x1c58, (q15_t)0x1c51, (q15_t)0x1c4b, (q15_t)0x1c45, (q15_t)0x1c3f, + (q15_t)0x1c39, (q15_t)0x1c33, (q15_t)0x1c2d, (q15_t)0x1c27, (q15_t)0x1c20, (q15_t)0x1c1a, (q15_t)0x1c14, (q15_t)0x1c0e, + (q15_t)0x1c08, (q15_t)0x1c02, (q15_t)0x1bfc, (q15_t)0x1bf6, (q15_t)0x1bef, (q15_t)0x1be9, (q15_t)0x1be3, (q15_t)0x1bdd, + (q15_t)0x1bd7, (q15_t)0x1bd1, (q15_t)0x1bcb, (q15_t)0x1bc4, (q15_t)0x1bbe, (q15_t)0x1bb8, (q15_t)0x1bb2, (q15_t)0x1bac, + (q15_t)0x1ba6, (q15_t)0x1ba0, (q15_t)0x1b9a, (q15_t)0x1b93, (q15_t)0x1b8d, (q15_t)0x1b87, (q15_t)0x1b81, (q15_t)0x1b7b, + (q15_t)0x1b75, (q15_t)0x1b6f, (q15_t)0x1b68, (q15_t)0x1b62, (q15_t)0x1b5c, (q15_t)0x1b56, (q15_t)0x1b50, (q15_t)0x1b4a, + (q15_t)0x1b44, (q15_t)0x1b3d, (q15_t)0x1b37, (q15_t)0x1b31, (q15_t)0x1b2b, (q15_t)0x1b25, (q15_t)0x1b1f, (q15_t)0x1b19, + (q15_t)0x1b13, (q15_t)0x1b0c, (q15_t)0x1b06, (q15_t)0x1b00, (q15_t)0x1afa, (q15_t)0x1af4, (q15_t)0x1aee, (q15_t)0x1ae8, + (q15_t)0x1ae1, (q15_t)0x1adb, (q15_t)0x1ad5, (q15_t)0x1acf, (q15_t)0x1ac9, (q15_t)0x1ac3, (q15_t)0x1abd, (q15_t)0x1ab6, + (q15_t)0x1ab0, (q15_t)0x1aaa, (q15_t)0x1aa4, (q15_t)0x1a9e, (q15_t)0x1a98, (q15_t)0x1a91, (q15_t)0x1a8b, (q15_t)0x1a85, + (q15_t)0x1a7f, (q15_t)0x1a79, (q15_t)0x1a73, (q15_t)0x1a6d, (q15_t)0x1a66, (q15_t)0x1a60, (q15_t)0x1a5a, (q15_t)0x1a54, + (q15_t)0x1a4e, (q15_t)0x1a48, (q15_t)0x1a42, (q15_t)0x1a3b, (q15_t)0x1a35, (q15_t)0x1a2f, (q15_t)0x1a29, (q15_t)0x1a23, + (q15_t)0x1a1d, (q15_t)0x1a17, (q15_t)0x1a10, (q15_t)0x1a0a, (q15_t)0x1a04, (q15_t)0x19fe, (q15_t)0x19f8, (q15_t)0x19f2, + (q15_t)0x19eb, (q15_t)0x19e5, (q15_t)0x19df, (q15_t)0x19d9, (q15_t)0x19d3, (q15_t)0x19cd, (q15_t)0x19c7, (q15_t)0x19c0, + (q15_t)0x19ba, (q15_t)0x19b4, (q15_t)0x19ae, (q15_t)0x19a8, (q15_t)0x19a2, (q15_t)0x199b, (q15_t)0x1995, (q15_t)0x198f, + (q15_t)0x1989, (q15_t)0x1983, (q15_t)0x197d, (q15_t)0x1977, (q15_t)0x1970, (q15_t)0x196a, (q15_t)0x1964, (q15_t)0x195e, + (q15_t)0x1958, (q15_t)0x1952, (q15_t)0x194b, (q15_t)0x1945, (q15_t)0x193f, (q15_t)0x1939, (q15_t)0x1933, (q15_t)0x192d, + (q15_t)0x1926, (q15_t)0x1920, (q15_t)0x191a, (q15_t)0x1914, (q15_t)0x190e, (q15_t)0x1908, (q15_t)0x1901, (q15_t)0x18fb, + (q15_t)0x18f5, (q15_t)0x18ef, (q15_t)0x18e9, (q15_t)0x18e3, (q15_t)0x18dc, (q15_t)0x18d6, (q15_t)0x18d0, (q15_t)0x18ca, + (q15_t)0x18c4, (q15_t)0x18be, (q15_t)0x18b8, (q15_t)0x18b1, (q15_t)0x18ab, (q15_t)0x18a5, (q15_t)0x189f, (q15_t)0x1899, + (q15_t)0x1893, (q15_t)0x188c, (q15_t)0x1886, (q15_t)0x1880, (q15_t)0x187a, (q15_t)0x1874, (q15_t)0x186e, (q15_t)0x1867, + (q15_t)0x1861, (q15_t)0x185b, (q15_t)0x1855, (q15_t)0x184f, (q15_t)0x1848, (q15_t)0x1842, (q15_t)0x183c, (q15_t)0x1836, + (q15_t)0x1830, (q15_t)0x182a, (q15_t)0x1823, (q15_t)0x181d, (q15_t)0x1817, (q15_t)0x1811, (q15_t)0x180b, (q15_t)0x1805, + (q15_t)0x17fe, (q15_t)0x17f8, (q15_t)0x17f2, (q15_t)0x17ec, (q15_t)0x17e6, (q15_t)0x17e0, (q15_t)0x17d9, (q15_t)0x17d3, + (q15_t)0x17cd, (q15_t)0x17c7, (q15_t)0x17c1, (q15_t)0x17bb, (q15_t)0x17b4, (q15_t)0x17ae, (q15_t)0x17a8, (q15_t)0x17a2, + (q15_t)0x179c, (q15_t)0x1795, (q15_t)0x178f, (q15_t)0x1789, (q15_t)0x1783, (q15_t)0x177d, (q15_t)0x1777, (q15_t)0x1770, + (q15_t)0x176a, (q15_t)0x1764, (q15_t)0x175e, (q15_t)0x1758, (q15_t)0x1752, (q15_t)0x174b, (q15_t)0x1745, (q15_t)0x173f, + (q15_t)0x1739, (q15_t)0x1733, (q15_t)0x172c, (q15_t)0x1726, (q15_t)0x1720, (q15_t)0x171a, (q15_t)0x1714, (q15_t)0x170e, + (q15_t)0x1707, (q15_t)0x1701, (q15_t)0x16fb, (q15_t)0x16f5, (q15_t)0x16ef, (q15_t)0x16e8, (q15_t)0x16e2, (q15_t)0x16dc, + (q15_t)0x16d6, (q15_t)0x16d0, (q15_t)0x16ca, (q15_t)0x16c3, (q15_t)0x16bd, (q15_t)0x16b7, (q15_t)0x16b1, (q15_t)0x16ab, + (q15_t)0x16a4, (q15_t)0x169e, (q15_t)0x1698, (q15_t)0x1692, (q15_t)0x168c, (q15_t)0x1686, (q15_t)0x167f, (q15_t)0x1679, + (q15_t)0x1673, (q15_t)0x166d, (q15_t)0x1667, (q15_t)0x1660, (q15_t)0x165a, (q15_t)0x1654, (q15_t)0x164e, (q15_t)0x1648, + (q15_t)0x1642, (q15_t)0x163b, (q15_t)0x1635, (q15_t)0x162f, (q15_t)0x1629, (q15_t)0x1623, (q15_t)0x161c, (q15_t)0x1616, + (q15_t)0x1610, (q15_t)0x160a, (q15_t)0x1604, (q15_t)0x15fd, (q15_t)0x15f7, (q15_t)0x15f1, (q15_t)0x15eb, (q15_t)0x15e5, + (q15_t)0x15de, (q15_t)0x15d8, (q15_t)0x15d2, (q15_t)0x15cc, (q15_t)0x15c6, (q15_t)0x15c0, (q15_t)0x15b9, (q15_t)0x15b3, + (q15_t)0x15ad, (q15_t)0x15a7, (q15_t)0x15a1, (q15_t)0x159a, (q15_t)0x1594, (q15_t)0x158e, (q15_t)0x1588, (q15_t)0x1582, + (q15_t)0x157b, (q15_t)0x1575, (q15_t)0x156f, (q15_t)0x1569, (q15_t)0x1563, (q15_t)0x155c, (q15_t)0x1556, (q15_t)0x1550, + (q15_t)0x154a, (q15_t)0x1544, (q15_t)0x153d, (q15_t)0x1537, (q15_t)0x1531, (q15_t)0x152b, (q15_t)0x1525, (q15_t)0x151e, + (q15_t)0x1518, (q15_t)0x1512, (q15_t)0x150c, (q15_t)0x1506, (q15_t)0x14ff, (q15_t)0x14f9, (q15_t)0x14f3, (q15_t)0x14ed, + (q15_t)0x14e7, (q15_t)0x14e0, (q15_t)0x14da, (q15_t)0x14d4, (q15_t)0x14ce, (q15_t)0x14c8, (q15_t)0x14c1, (q15_t)0x14bb, + (q15_t)0x14b5, (q15_t)0x14af, (q15_t)0x14a9, (q15_t)0x14a2, (q15_t)0x149c, (q15_t)0x1496, (q15_t)0x1490, (q15_t)0x148a, + (q15_t)0x1483, (q15_t)0x147d, (q15_t)0x1477, (q15_t)0x1471, (q15_t)0x146b, (q15_t)0x1464, (q15_t)0x145e, (q15_t)0x1458, + (q15_t)0x1452, (q15_t)0x144c, (q15_t)0x1445, (q15_t)0x143f, (q15_t)0x1439, (q15_t)0x1433, (q15_t)0x142d, (q15_t)0x1426, + (q15_t)0x1420, (q15_t)0x141a, (q15_t)0x1414, (q15_t)0x140e, (q15_t)0x1407, (q15_t)0x1401, (q15_t)0x13fb, (q15_t)0x13f5, + (q15_t)0x13ef, (q15_t)0x13e8, (q15_t)0x13e2, (q15_t)0x13dc, (q15_t)0x13d6, (q15_t)0x13d0, (q15_t)0x13c9, (q15_t)0x13c3, + (q15_t)0x13bd, (q15_t)0x13b7, (q15_t)0x13b1, (q15_t)0x13aa, (q15_t)0x13a4, (q15_t)0x139e, (q15_t)0x1398, (q15_t)0x1391, + (q15_t)0x138b, (q15_t)0x1385, (q15_t)0x137f, (q15_t)0x1379, (q15_t)0x1372, (q15_t)0x136c, (q15_t)0x1366, (q15_t)0x1360, + (q15_t)0x135a, (q15_t)0x1353, (q15_t)0x134d, (q15_t)0x1347, (q15_t)0x1341, (q15_t)0x133b, (q15_t)0x1334, (q15_t)0x132e, + (q15_t)0x1328, (q15_t)0x1322, (q15_t)0x131b, (q15_t)0x1315, (q15_t)0x130f, (q15_t)0x1309, (q15_t)0x1303, (q15_t)0x12fc, + (q15_t)0x12f6, (q15_t)0x12f0, (q15_t)0x12ea, (q15_t)0x12e4, (q15_t)0x12dd, (q15_t)0x12d7, (q15_t)0x12d1, (q15_t)0x12cb, + (q15_t)0x12c4, (q15_t)0x12be, (q15_t)0x12b8, (q15_t)0x12b2, (q15_t)0x12ac, (q15_t)0x12a5, (q15_t)0x129f, (q15_t)0x1299, + (q15_t)0x1293, (q15_t)0x128d, (q15_t)0x1286, (q15_t)0x1280, (q15_t)0x127a, (q15_t)0x1274, (q15_t)0x126d, (q15_t)0x1267, + (q15_t)0x1261, (q15_t)0x125b, (q15_t)0x1255, (q15_t)0x124e, (q15_t)0x1248, (q15_t)0x1242, (q15_t)0x123c, (q15_t)0x1235, + (q15_t)0x122f, (q15_t)0x1229, (q15_t)0x1223, (q15_t)0x121d, (q15_t)0x1216, (q15_t)0x1210, (q15_t)0x120a, (q15_t)0x1204, + (q15_t)0x11fd, (q15_t)0x11f7, (q15_t)0x11f1, (q15_t)0x11eb, (q15_t)0x11e5, (q15_t)0x11de, (q15_t)0x11d8, (q15_t)0x11d2, + (q15_t)0x11cc, (q15_t)0x11c5, (q15_t)0x11bf, (q15_t)0x11b9, (q15_t)0x11b3, (q15_t)0x11ad, (q15_t)0x11a6, (q15_t)0x11a0, + (q15_t)0x119a, (q15_t)0x1194, (q15_t)0x118d, (q15_t)0x1187, (q15_t)0x1181, (q15_t)0x117b, (q15_t)0x1175, (q15_t)0x116e, + (q15_t)0x1168, (q15_t)0x1162, (q15_t)0x115c, (q15_t)0x1155, (q15_t)0x114f, (q15_t)0x1149, (q15_t)0x1143, (q15_t)0x113d, + (q15_t)0x1136, (q15_t)0x1130, (q15_t)0x112a, (q15_t)0x1124, (q15_t)0x111d, (q15_t)0x1117, (q15_t)0x1111, (q15_t)0x110b, + (q15_t)0x1105, (q15_t)0x10fe, (q15_t)0x10f8, (q15_t)0x10f2, (q15_t)0x10ec, (q15_t)0x10e5, (q15_t)0x10df, (q15_t)0x10d9, + (q15_t)0x10d3, (q15_t)0x10cc, (q15_t)0x10c6, (q15_t)0x10c0, (q15_t)0x10ba, (q15_t)0x10b4, (q15_t)0x10ad, (q15_t)0x10a7, + (q15_t)0x10a1, (q15_t)0x109b, (q15_t)0x1094, (q15_t)0x108e, (q15_t)0x1088, (q15_t)0x1082, (q15_t)0x107b, (q15_t)0x1075, + (q15_t)0x106f, (q15_t)0x1069, (q15_t)0x1063, (q15_t)0x105c, (q15_t)0x1056, (q15_t)0x1050, (q15_t)0x104a, (q15_t)0x1043, + (q15_t)0x103d, (q15_t)0x1037, (q15_t)0x1031, (q15_t)0x102a, (q15_t)0x1024, (q15_t)0x101e, (q15_t)0x1018, (q15_t)0x1012, + (q15_t)0x100b, (q15_t)0x1005, (q15_t)0xfff, (q15_t)0xff9, (q15_t)0xff2, (q15_t)0xfec, (q15_t)0xfe6, (q15_t)0xfe0, + (q15_t)0xfd9, (q15_t)0xfd3, (q15_t)0xfcd, (q15_t)0xfc7, (q15_t)0xfc0, (q15_t)0xfba, (q15_t)0xfb4, (q15_t)0xfae, + (q15_t)0xfa8, (q15_t)0xfa1, (q15_t)0xf9b, (q15_t)0xf95, (q15_t)0xf8f, (q15_t)0xf88, (q15_t)0xf82, (q15_t)0xf7c, + (q15_t)0xf76, (q15_t)0xf6f, (q15_t)0xf69, (q15_t)0xf63, (q15_t)0xf5d, (q15_t)0xf56, (q15_t)0xf50, (q15_t)0xf4a, + (q15_t)0xf44, (q15_t)0xf3e, (q15_t)0xf37, (q15_t)0xf31, (q15_t)0xf2b, (q15_t)0xf25, (q15_t)0xf1e, (q15_t)0xf18, + (q15_t)0xf12, (q15_t)0xf0c, (q15_t)0xf05, (q15_t)0xeff, (q15_t)0xef9, (q15_t)0xef3, (q15_t)0xeec, (q15_t)0xee6, + (q15_t)0xee0, (q15_t)0xeda, (q15_t)0xed3, (q15_t)0xecd, (q15_t)0xec7, (q15_t)0xec1, (q15_t)0xeba, (q15_t)0xeb4, + (q15_t)0xeae, (q15_t)0xea8, (q15_t)0xea1, (q15_t)0xe9b, (q15_t)0xe95, (q15_t)0xe8f, (q15_t)0xe89, (q15_t)0xe82, + (q15_t)0xe7c, (q15_t)0xe76, (q15_t)0xe70, (q15_t)0xe69, (q15_t)0xe63, (q15_t)0xe5d, (q15_t)0xe57, (q15_t)0xe50, + (q15_t)0xe4a, (q15_t)0xe44, (q15_t)0xe3e, (q15_t)0xe37, (q15_t)0xe31, (q15_t)0xe2b, (q15_t)0xe25, (q15_t)0xe1e, + (q15_t)0xe18, (q15_t)0xe12, (q15_t)0xe0c, (q15_t)0xe05, (q15_t)0xdff, (q15_t)0xdf9, (q15_t)0xdf3, (q15_t)0xdec, + (q15_t)0xde6, (q15_t)0xde0, (q15_t)0xdda, (q15_t)0xdd3, (q15_t)0xdcd, (q15_t)0xdc7, (q15_t)0xdc1, (q15_t)0xdba, + (q15_t)0xdb4, (q15_t)0xdae, (q15_t)0xda8, (q15_t)0xda1, (q15_t)0xd9b, (q15_t)0xd95, (q15_t)0xd8f, (q15_t)0xd88, + (q15_t)0xd82, (q15_t)0xd7c, (q15_t)0xd76, (q15_t)0xd6f, (q15_t)0xd69, (q15_t)0xd63, (q15_t)0xd5d, (q15_t)0xd56, + (q15_t)0xd50, (q15_t)0xd4a, (q15_t)0xd44, (q15_t)0xd3d, (q15_t)0xd37, (q15_t)0xd31, (q15_t)0xd2b, (q15_t)0xd24, + (q15_t)0xd1e, (q15_t)0xd18, (q15_t)0xd12, (q15_t)0xd0b, (q15_t)0xd05, (q15_t)0xcff, (q15_t)0xcf9, (q15_t)0xcf2, + (q15_t)0xcec, (q15_t)0xce6, (q15_t)0xce0, (q15_t)0xcd9, (q15_t)0xcd3, (q15_t)0xccd, (q15_t)0xcc7, (q15_t)0xcc0, + (q15_t)0xcba, (q15_t)0xcb4, (q15_t)0xcae, (q15_t)0xca7, (q15_t)0xca1, (q15_t)0xc9b, (q15_t)0xc95, (q15_t)0xc8e, + (q15_t)0xc88, (q15_t)0xc82, (q15_t)0xc7c, (q15_t)0xc75, (q15_t)0xc6f, (q15_t)0xc69, (q15_t)0xc63, (q15_t)0xc5c, + (q15_t)0xc56, (q15_t)0xc50, (q15_t)0xc4a, (q15_t)0xc43, (q15_t)0xc3d, (q15_t)0xc37, (q15_t)0xc31, (q15_t)0xc2a, + (q15_t)0xc24, (q15_t)0xc1e, (q15_t)0xc18, (q15_t)0xc11, (q15_t)0xc0b, (q15_t)0xc05, (q15_t)0xbff, (q15_t)0xbf8, + (q15_t)0xbf2, (q15_t)0xbec, (q15_t)0xbe6, (q15_t)0xbdf, (q15_t)0xbd9, (q15_t)0xbd3, (q15_t)0xbcd, (q15_t)0xbc6, + (q15_t)0xbc0, (q15_t)0xbba, (q15_t)0xbb4, (q15_t)0xbad, (q15_t)0xba7, (q15_t)0xba1, (q15_t)0xb9b, (q15_t)0xb94, + (q15_t)0xb8e, (q15_t)0xb88, (q15_t)0xb81, (q15_t)0xb7b, (q15_t)0xb75, (q15_t)0xb6f, (q15_t)0xb68, (q15_t)0xb62, + (q15_t)0xb5c, (q15_t)0xb56, (q15_t)0xb4f, (q15_t)0xb49, (q15_t)0xb43, (q15_t)0xb3d, (q15_t)0xb36, (q15_t)0xb30, + (q15_t)0xb2a, (q15_t)0xb24, (q15_t)0xb1d, (q15_t)0xb17, (q15_t)0xb11, (q15_t)0xb0b, (q15_t)0xb04, (q15_t)0xafe, + (q15_t)0xaf8, (q15_t)0xaf2, (q15_t)0xaeb, (q15_t)0xae5, (q15_t)0xadf, (q15_t)0xad8, (q15_t)0xad2, (q15_t)0xacc, + (q15_t)0xac6, (q15_t)0xabf, (q15_t)0xab9, (q15_t)0xab3, (q15_t)0xaad, (q15_t)0xaa6, (q15_t)0xaa0, (q15_t)0xa9a, + (q15_t)0xa94, (q15_t)0xa8d, (q15_t)0xa87, (q15_t)0xa81, (q15_t)0xa7b, (q15_t)0xa74, (q15_t)0xa6e, (q15_t)0xa68, + (q15_t)0xa62, (q15_t)0xa5b, (q15_t)0xa55, (q15_t)0xa4f, (q15_t)0xa48, (q15_t)0xa42, (q15_t)0xa3c, (q15_t)0xa36, + (q15_t)0xa2f, (q15_t)0xa29, (q15_t)0xa23, (q15_t)0xa1d, (q15_t)0xa16, (q15_t)0xa10, (q15_t)0xa0a, (q15_t)0xa04, + (q15_t)0x9fd, (q15_t)0x9f7, (q15_t)0x9f1, (q15_t)0x9eb, (q15_t)0x9e4, (q15_t)0x9de, (q15_t)0x9d8, (q15_t)0x9d1, + (q15_t)0x9cb, (q15_t)0x9c5, (q15_t)0x9bf, (q15_t)0x9b8, (q15_t)0x9b2, (q15_t)0x9ac, (q15_t)0x9a6, (q15_t)0x99f, + (q15_t)0x999, (q15_t)0x993, (q15_t)0x98d, (q15_t)0x986, (q15_t)0x980, (q15_t)0x97a, (q15_t)0x973, (q15_t)0x96d, + (q15_t)0x967, (q15_t)0x961, (q15_t)0x95a, (q15_t)0x954, (q15_t)0x94e, (q15_t)0x948, (q15_t)0x941, (q15_t)0x93b, + (q15_t)0x935, (q15_t)0x92f, (q15_t)0x928, (q15_t)0x922, (q15_t)0x91c, (q15_t)0x915, (q15_t)0x90f, (q15_t)0x909, + (q15_t)0x903, (q15_t)0x8fc, (q15_t)0x8f6, (q15_t)0x8f0, (q15_t)0x8ea, (q15_t)0x8e3, (q15_t)0x8dd, (q15_t)0x8d7, + (q15_t)0x8d1, (q15_t)0x8ca, (q15_t)0x8c4, (q15_t)0x8be, (q15_t)0x8b7, (q15_t)0x8b1, (q15_t)0x8ab, (q15_t)0x8a5, + (q15_t)0x89e, (q15_t)0x898, (q15_t)0x892, (q15_t)0x88c, (q15_t)0x885, (q15_t)0x87f, (q15_t)0x879, (q15_t)0x872, + (q15_t)0x86c, (q15_t)0x866, (q15_t)0x860, (q15_t)0x859, (q15_t)0x853, (q15_t)0x84d, (q15_t)0x847, (q15_t)0x840, + (q15_t)0x83a, (q15_t)0x834, (q15_t)0x82e, (q15_t)0x827, (q15_t)0x821, (q15_t)0x81b, (q15_t)0x814, (q15_t)0x80e, + (q15_t)0x808, (q15_t)0x802, (q15_t)0x7fb, (q15_t)0x7f5, (q15_t)0x7ef, (q15_t)0x7e9, (q15_t)0x7e2, (q15_t)0x7dc, + (q15_t)0x7d6, (q15_t)0x7cf, (q15_t)0x7c9, (q15_t)0x7c3, (q15_t)0x7bd, (q15_t)0x7b6, (q15_t)0x7b0, (q15_t)0x7aa, + (q15_t)0x7a4, (q15_t)0x79d, (q15_t)0x797, (q15_t)0x791, (q15_t)0x78a, (q15_t)0x784, (q15_t)0x77e, (q15_t)0x778, + (q15_t)0x771, (q15_t)0x76b, (q15_t)0x765, (q15_t)0x75f, (q15_t)0x758, (q15_t)0x752, (q15_t)0x74c, (q15_t)0x745, + (q15_t)0x73f, (q15_t)0x739, (q15_t)0x733, (q15_t)0x72c, (q15_t)0x726, (q15_t)0x720, (q15_t)0x71a, (q15_t)0x713, + (q15_t)0x70d, (q15_t)0x707, (q15_t)0x700, (q15_t)0x6fa, (q15_t)0x6f4, (q15_t)0x6ee, (q15_t)0x6e7, (q15_t)0x6e1, + (q15_t)0x6db, (q15_t)0x6d5, (q15_t)0x6ce, (q15_t)0x6c8, (q15_t)0x6c2, (q15_t)0x6bb, (q15_t)0x6b5, (q15_t)0x6af, + (q15_t)0x6a9, (q15_t)0x6a2, (q15_t)0x69c, (q15_t)0x696, (q15_t)0x690, (q15_t)0x689, (q15_t)0x683, (q15_t)0x67d, + (q15_t)0x676, (q15_t)0x670, (q15_t)0x66a, (q15_t)0x664, (q15_t)0x65d, (q15_t)0x657, (q15_t)0x651, (q15_t)0x64a, + (q15_t)0x644, (q15_t)0x63e, (q15_t)0x638, (q15_t)0x631, (q15_t)0x62b, (q15_t)0x625, (q15_t)0x61f, (q15_t)0x618, + (q15_t)0x612, (q15_t)0x60c, (q15_t)0x605, (q15_t)0x5ff, (q15_t)0x5f9, (q15_t)0x5f3, (q15_t)0x5ec, (q15_t)0x5e6, + (q15_t)0x5e0, (q15_t)0x5da, (q15_t)0x5d3, (q15_t)0x5cd, (q15_t)0x5c7, (q15_t)0x5c0, (q15_t)0x5ba, (q15_t)0x5b4, + (q15_t)0x5ae, (q15_t)0x5a7, (q15_t)0x5a1, (q15_t)0x59b, (q15_t)0x594, (q15_t)0x58e, (q15_t)0x588, (q15_t)0x582, + (q15_t)0x57b, (q15_t)0x575, (q15_t)0x56f, (q15_t)0x569, (q15_t)0x562, (q15_t)0x55c, (q15_t)0x556, (q15_t)0x54f, + (q15_t)0x549, (q15_t)0x543, (q15_t)0x53d, (q15_t)0x536, (q15_t)0x530, (q15_t)0x52a, (q15_t)0x523, (q15_t)0x51d, + (q15_t)0x517, (q15_t)0x511, (q15_t)0x50a, (q15_t)0x504, (q15_t)0x4fe, (q15_t)0x4f8, (q15_t)0x4f1, (q15_t)0x4eb, + (q15_t)0x4e5, (q15_t)0x4de, (q15_t)0x4d8, (q15_t)0x4d2, (q15_t)0x4cc, (q15_t)0x4c5, (q15_t)0x4bf, (q15_t)0x4b9, + (q15_t)0x4b2, (q15_t)0x4ac, (q15_t)0x4a6, (q15_t)0x4a0, (q15_t)0x499, (q15_t)0x493, (q15_t)0x48d, (q15_t)0x487, + (q15_t)0x480, (q15_t)0x47a, (q15_t)0x474, (q15_t)0x46d, (q15_t)0x467, (q15_t)0x461, (q15_t)0x45b, (q15_t)0x454, + (q15_t)0x44e, (q15_t)0x448, (q15_t)0x441, (q15_t)0x43b, (q15_t)0x435, (q15_t)0x42f, (q15_t)0x428, (q15_t)0x422, + (q15_t)0x41c, (q15_t)0x415, (q15_t)0x40f, (q15_t)0x409, (q15_t)0x403, (q15_t)0x3fc, (q15_t)0x3f6, (q15_t)0x3f0, + (q15_t)0x3ea, (q15_t)0x3e3, (q15_t)0x3dd, (q15_t)0x3d7, (q15_t)0x3d0, (q15_t)0x3ca, (q15_t)0x3c4, (q15_t)0x3be, + (q15_t)0x3b7, (q15_t)0x3b1, (q15_t)0x3ab, (q15_t)0x3a4, (q15_t)0x39e, (q15_t)0x398, (q15_t)0x392, (q15_t)0x38b, + (q15_t)0x385, (q15_t)0x37f, (q15_t)0x378, (q15_t)0x372, (q15_t)0x36c, (q15_t)0x366, (q15_t)0x35f, (q15_t)0x359, + (q15_t)0x353, (q15_t)0x34c, (q15_t)0x346, (q15_t)0x340, (q15_t)0x33a, (q15_t)0x333, (q15_t)0x32d, (q15_t)0x327, + (q15_t)0x321, (q15_t)0x31a, (q15_t)0x314, (q15_t)0x30e, (q15_t)0x307, (q15_t)0x301, (q15_t)0x2fb, (q15_t)0x2f5, + (q15_t)0x2ee, (q15_t)0x2e8, (q15_t)0x2e2, (q15_t)0x2db, (q15_t)0x2d5, (q15_t)0x2cf, (q15_t)0x2c9, (q15_t)0x2c2, + (q15_t)0x2bc, (q15_t)0x2b6, (q15_t)0x2af, (q15_t)0x2a9, (q15_t)0x2a3, (q15_t)0x29d, (q15_t)0x296, (q15_t)0x290, + (q15_t)0x28a, (q15_t)0x283, (q15_t)0x27d, (q15_t)0x277, (q15_t)0x271, (q15_t)0x26a, (q15_t)0x264, (q15_t)0x25e, + (q15_t)0x258, (q15_t)0x251, (q15_t)0x24b, (q15_t)0x245, (q15_t)0x23e, (q15_t)0x238, (q15_t)0x232, (q15_t)0x22c, + (q15_t)0x225, (q15_t)0x21f, (q15_t)0x219, (q15_t)0x212, (q15_t)0x20c, (q15_t)0x206, (q15_t)0x200, (q15_t)0x1f9, + (q15_t)0x1f3, (q15_t)0x1ed, (q15_t)0x1e6, (q15_t)0x1e0, (q15_t)0x1da, (q15_t)0x1d4, (q15_t)0x1cd, (q15_t)0x1c7, + (q15_t)0x1c1, (q15_t)0x1ba, (q15_t)0x1b4, (q15_t)0x1ae, (q15_t)0x1a8, (q15_t)0x1a1, (q15_t)0x19b, (q15_t)0x195, + (q15_t)0x18e, (q15_t)0x188, (q15_t)0x182, (q15_t)0x17c, (q15_t)0x175, (q15_t)0x16f, (q15_t)0x169, (q15_t)0x162, + (q15_t)0x15c, (q15_t)0x156, (q15_t)0x150, (q15_t)0x149, (q15_t)0x143, (q15_t)0x13d, (q15_t)0x137, (q15_t)0x130, + (q15_t)0x12a, (q15_t)0x124, (q15_t)0x11d, (q15_t)0x117, (q15_t)0x111, (q15_t)0x10b, (q15_t)0x104, (q15_t)0xfe, + (q15_t)0xf8, (q15_t)0xf1, (q15_t)0xeb, (q15_t)0xe5, (q15_t)0xdf, (q15_t)0xd8, (q15_t)0xd2, (q15_t)0xcc, + (q15_t)0xc5, (q15_t)0xbf, (q15_t)0xb9, (q15_t)0xb3, (q15_t)0xac, (q15_t)0xa6, (q15_t)0xa0, (q15_t)0x99, + (q15_t)0x93, (q15_t)0x8d, (q15_t)0x87, (q15_t)0x80, (q15_t)0x7a, (q15_t)0x74, (q15_t)0x6d, (q15_t)0x67, + (q15_t)0x61, (q15_t)0x5b, (q15_t)0x54, (q15_t)0x4e, (q15_t)0x48, (q15_t)0x41, (q15_t)0x3b, (q15_t)0x35, + (q15_t)0x2f, (q15_t)0x28, (q15_t)0x22, (q15_t)0x1c, (q15_t)0x15, (q15_t)0xf, (q15_t)0x9, (q15_t)0x3 +}; + #endif + +/** + @par + Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    weights[(2*i)]   =  cos(i*c);
+    weights[(2*i)+1] = -sin(i*c);
+  }
+ @par + where N is the Number of weights to be calculated and c is pi/(2*N) + @par + Convert the output to q31 format by multiplying with 2^31 and saturated if required. + @par + In the tables below the real and imaginary values are placed alternatively, hence the + array length is 2*N. + */ + +/** + @par + cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
+ @par + C command to generate the table + 
+  for (i = 0; i< N; i++)
+  {
+    cos_factors[i] = 2 * cos((2*i+1)*c/2);
+  }
+ @par + where N is the number of factors to generate and c is pi/(2*N) + @par + Then converted to q31 format by multiplying with 2^31 and saturated if required. +*/ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + const q31_t WeightsQ31_128[256] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f872bf3, (q31_t)0xf50497fb, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7dd6668f, (q31_t)0xe8922622, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7c894bde, (q31_t)0xe26cb01b, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7aef6323, (q31_t)0xdc597781, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x76d94989, (q31_t)0xd078ad9e, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x719e2cd2, (q31_t)0xc50d1149, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6b4af279, (q31_t)0xba32ca71, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x67bd0fbd, (q31_t)0xb5049368, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x63ef3290, (q31_t)0xb0049ab3, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x571deefa, (q31_t)0xa2386284, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x5269126e, (q31_t)0x9e0effc1, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4d8162c4, (q31_t)0x9a22042d, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4869e665, (q31_t)0x9673db94, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4325c135, (q31_t)0x9306cb04, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3db832a6, (q31_t)0x8fdcef66, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x382493b0, (q31_t)0x8cf83c30, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2c98fbba, (q31_t)0x88054677, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x26a82186, (q31_t)0x85fa1153, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x209f701c, (q31_t)0x843a1d70, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1a82a026, (q31_t)0x82c67f14, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x145576b1, (q31_t)0x81a01b6d, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x07d95b9e, (q31_t)0x803daa6a, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x01921d20, (q31_t)0x800277a6 +}; + const q31_t cos_factorsQ31_128[128] = { + (q31_t)0x7fff6216, (q31_t)0x7ffa72d1, (q31_t)0x7ff09478, (q31_t)0x7fe1c76b, (q31_t)0x7fce0c3e, (q31_t)0x7fb563b3, + (q31_t)0x7f97cebd, (q31_t)0x7f754e80, + (q31_t)0x7f4de451, (q31_t)0x7f2191b4, (q31_t)0x7ef05860, (q31_t)0x7eba3a39, (q31_t)0x7e7f3957, (q31_t)0x7e3f57ff, + (q31_t)0x7dfa98a8, (q31_t)0x7db0fdf8, + (q31_t)0x7d628ac6, (q31_t)0x7d0f4218, (q31_t)0x7cb72724, (q31_t)0x7c5a3d50, (q31_t)0x7bf88830, (q31_t)0x7b920b89, + (q31_t)0x7b26cb4f, (q31_t)0x7ab6cba4, + (q31_t)0x7a4210d8, (q31_t)0x79c89f6e, (q31_t)0x794a7c12, (q31_t)0x78c7aba2, (q31_t)0x78403329, (q31_t)0x77b417df, + (q31_t)0x77235f2d, (q31_t)0x768e0ea6, + (q31_t)0x75f42c0b, (q31_t)0x7555bd4c, (q31_t)0x74b2c884, (q31_t)0x740b53fb, (q31_t)0x735f6626, (q31_t)0x72af05a7, + (q31_t)0x71fa3949, (q31_t)0x71410805, + (q31_t)0x708378ff, (q31_t)0x6fc19385, (q31_t)0x6efb5f12, (q31_t)0x6e30e34a, (q31_t)0x6d6227fa, (q31_t)0x6c8f351c, + (q31_t)0x6bb812d1, (q31_t)0x6adcc964, + (q31_t)0x69fd614a, (q31_t)0x6919e320, (q31_t)0x683257ab, (q31_t)0x6746c7d8, (q31_t)0x66573cbb, (q31_t)0x6563bf92, + (q31_t)0x646c59bf, (q31_t)0x637114cc, + (q31_t)0x6271fa69, (q31_t)0x616f146c, (q31_t)0x60686ccf, (q31_t)0x5f5e0db3, (q31_t)0x5e50015d, (q31_t)0x5d3e5237, + (q31_t)0x5c290acc, (q31_t)0x5b1035cf, + (q31_t)0x59f3de12, (q31_t)0x58d40e8c, (q31_t)0x57b0d256, (q31_t)0x568a34a9, (q31_t)0x556040e2, (q31_t)0x5433027d, + (q31_t)0x53028518, (q31_t)0x51ced46e, + (q31_t)0x5097fc5e, (q31_t)0x4f5e08e3, (q31_t)0x4e210617, (q31_t)0x4ce10034, (q31_t)0x4b9e0390, (q31_t)0x4a581c9e, + (q31_t)0x490f57ee, (q31_t)0x47c3c22f, + (q31_t)0x46756828, (q31_t)0x452456bd, (q31_t)0x43d09aed, (q31_t)0x427a41d0, (q31_t)0x4121589b, (q31_t)0x3fc5ec98, + (q31_t)0x3e680b2c, (q31_t)0x3d07c1d6, + (q31_t)0x3ba51e29, (q31_t)0x3a402dd2, (q31_t)0x38d8fe93, (q31_t)0x376f9e46, (q31_t)0x36041ad9, (q31_t)0x34968250, + (q31_t)0x3326e2c3, (q31_t)0x31b54a5e, + (q31_t)0x3041c761, (q31_t)0x2ecc681e, (q31_t)0x2d553afc, (q31_t)0x2bdc4e6f, (q31_t)0x2a61b101, (q31_t)0x28e5714b, + (q31_t)0x27679df4, (q31_t)0x25e845b6, + (q31_t)0x24677758, (q31_t)0x22e541af, (q31_t)0x2161b3a0, (q31_t)0x1fdcdc1b, (q31_t)0x1e56ca1e, (q31_t)0x1ccf8cb3, + (q31_t)0x1b4732ef, (q31_t)0x19bdcbf3, + (q31_t)0x183366e9, (q31_t)0x16a81305, (q31_t)0x151bdf86, (q31_t)0x138edbb1, (q31_t)0x120116d5, (q31_t)0x1072a048, + (q31_t)0xee38766, (q31_t)0xd53db92, + (q31_t)0xbc3ac35, (q31_t)0xa3308bd, (q31_t)0x8a2009a, (q31_t)0x710a345, (q31_t)0x57f0035, (q31_t)0x3ed26e6, (q31_t)0x25b26d7, + (q31_t)0xc90f88 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + const q31_t WeightsQ31_512[1024] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff871a2, (q31_t)0xfd40565c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fed5791, (q31_t)0xfbae5e89, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fc85854, (q31_t)0xf88afe42, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f434563, (q31_t)0xf2482c8a, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7ee34636, (q31_t)0xef29b243, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7de8a670, (q31_t)0xe8f50273, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c4242f2, (q31_t)0xe14794ba, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b77ada8, (q31_t)0xde3d4964, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a24256f, (q31_t)0xd9b7c094, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79a98715, (q31_t)0xd838c82d, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x792a37fe, (q31_t)0xd6bb585e, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78a63d11, (q31_t)0xd53f7fda, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x781d9b65, (q31_t)0xd3c54d47, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x7790583e, (q31_t)0xd24ccf39, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x76fe790e, (q31_t)0xd0d61434, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x76680376, (q31_t)0xcf612aaa, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x7489571c, (q31_t)0xcb0de658, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x7333b883, (q31_t)0xc835d5d0, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72823c67, (q31_t)0xc6cd0079, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71cc5626, (q31_t)0xc5665fa9, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71120cc5, (q31_t)0xc4020133, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70536771, (q31_t)0xc29ff2d4, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6f906d84, (q31_t)0xc1404233, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6b81a3cd, (q31_t)0xba87246d, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x68e06129, (q31_t)0xb69e32cd, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x67f7d3c5, (q31_t)0xb556245e, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x670b4444, (q31_t)0xb410f6d3, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6526438f, (q31_t)0xb18f7071, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x642de50d, (q31_t)0xb0533055, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x62319b9d, (q31_t)0xade3f33e, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x612dc447, (q31_t)0xacb10e4b, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60262dd6, (q31_t)0xab815f8d, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5cf95638, (q31_t)0xa8060d08, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x588b9140, (q31_t)0xa3914da8, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56400758, (q31_t)0xa16c23e1, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x55153fd4, (q31_t)0xa05f01e1, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x53e73097, (q31_t)0x9f558fb0, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x518169a5, (q31_t)0x9d4de385, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x5049c999, (q31_t)0x9c4fbd93, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f0f1126, (q31_t)0x9b556f81, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4c9087b1, (q31_t)0x996c816f, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b4ccf4d, (q31_t)0x987df449, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a062fbd, (q31_t)0x979364b5, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48bcb599, (q31_t)0x96acdbbe, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47706d93, (q31_t)0x95ca6247, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x4621647d, (q31_t)0x94ec010b, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x44cfa740, (q31_t)0x9411c09e, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x437b42e1, (q31_t)0x933ba968, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x42244481, (q31_t)0x9269c3ac, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x40cab958, (q31_t)0x919c1781, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e10320d, (q31_t)0x900d8b69, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b4c18ba, (q31_t)0x8e904298, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x39e6975e, (q31_t)0x8dd829e4, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x387eda8e, (q31_t)0x8d2477d8, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3714f02a, (q31_t)0x8c753362, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35a8e625, (q31_t)0x8bca6343, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x343aca87, (q31_t)0x8b240e11, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x32caab6f, (q31_t)0x8a823a36, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x3158970e, (q31_t)0x89e4edef, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2e6ec792, (q31_t)0x88b80432, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2cf72939, (q31_t)0x88287256, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a02c7b8, (q31_t)0x8717304e, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x288621b9, (q31_t)0x86958aac, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2707ebc7, (q31_t)0x86189359, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x2588349d, (q31_t)0x85a04f28, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x24070b08, (q31_t)0x852cc2bb, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22847de0, (q31_t)0x84bdf286, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21009c0c, (q31_t)0x8453e2cf, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1df5163f, (q31_t)0x838e1507, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1c6d9053, (q31_t)0x83325e97, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x195b49ea, (q31_t)0x8289644b, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16451a83, (q31_t)0x81f3c2d7, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x132b7bf9, (q31_t)0x8171914e, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x119d8941, (q31_t)0x8137c8e6, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, + (q31_t)0x0fab272b, (q31_t)0x80f66e3c, (q31_t)0x0f475bff, (q31_t)0x80ea4712, (q31_t)0x0ee38766, (q31_t)0x80de6e4c, (q31_t)0x0e7fa99e, (q31_t)0x80d2e3f2, + (q31_t)0x0e1bc2e4, (q31_t)0x80c7a80a, (q31_t)0x0db7d376, (q31_t)0x80bcba9d, (q31_t)0x0d53db92, (q31_t)0x80b21baf, (q31_t)0x0cefdb76, (q31_t)0x80a7cb49, + (q31_t)0x0c8bd35e, (q31_t)0x809dc971, (q31_t)0x0c27c389, (q31_t)0x8094162c, (q31_t)0x0bc3ac35, (q31_t)0x808ab180, (q31_t)0x0b5f8d9f, (q31_t)0x80819b74, + (q31_t)0x0afb6805, (q31_t)0x8078d40d, (q31_t)0x0a973ba5, (q31_t)0x80705b50, (q31_t)0x0a3308bd, (q31_t)0x80683143, (q31_t)0x09cecf89, (q31_t)0x806055eb, + (q31_t)0x096a9049, (q31_t)0x8058c94c, (q31_t)0x09064b3a, (q31_t)0x80518b6b, (q31_t)0x08a2009a, (q31_t)0x804a9c4d, (q31_t)0x083db0a7, (q31_t)0x8043fbf6, + (q31_t)0x07d95b9e, (q31_t)0x803daa6a, (q31_t)0x077501be, (q31_t)0x8037a7ac, (q31_t)0x0710a345, (q31_t)0x8031f3c2, (q31_t)0x06ac406f, (q31_t)0x802c8ead, + (q31_t)0x0647d97c, (q31_t)0x80277872, (q31_t)0x05e36ea9, (q31_t)0x8022b114, (q31_t)0x057f0035, (q31_t)0x801e3895, (q31_t)0x051a8e5c, (q31_t)0x801a0ef8, + (q31_t)0x04b6195d, (q31_t)0x80163440, (q31_t)0x0451a177, (q31_t)0x8012a86f, (q31_t)0x03ed26e6, (q31_t)0x800f6b88, (q31_t)0x0388a9ea, (q31_t)0x800c7d8c, + (q31_t)0x03242abf, (q31_t)0x8009de7e, (q31_t)0x02bfa9a4, (q31_t)0x80078e5e, (q31_t)0x025b26d7, (q31_t)0x80058d2f, (q31_t)0x01f6a297, (q31_t)0x8003daf1, + (q31_t)0x01921d20, (q31_t)0x800277a6, (q31_t)0x012d96b1, (q31_t)0x8001634e, (q31_t)0x00c90f88, (q31_t)0x80009dea, (q31_t)0x006487e3, (q31_t)0x8000277a +}; + const q31_t cos_factorsQ31_512[512] = { + (q31_t)0x7ffff621, (q31_t)0x7fffa72c, (q31_t)0x7fff0943, (q31_t)0x7ffe1c65, (q31_t)0x7ffce093, (q31_t)0x7ffb55ce, + (q31_t)0x7ff97c18, (q31_t)0x7ff75370, + (q31_t)0x7ff4dbd9, (q31_t)0x7ff21553, (q31_t)0x7feeffe1, (q31_t)0x7feb9b85, (q31_t)0x7fe7e841, (q31_t)0x7fe3e616, + (q31_t)0x7fdf9508, (q31_t)0x7fdaf519, + (q31_t)0x7fd6064c, (q31_t)0x7fd0c8a3, (q31_t)0x7fcb3c23, (q31_t)0x7fc560cf, (q31_t)0x7fbf36aa, (q31_t)0x7fb8bdb8, + (q31_t)0x7fb1f5fc, (q31_t)0x7faadf7c, + (q31_t)0x7fa37a3c, (q31_t)0x7f9bc640, (q31_t)0x7f93c38c, (q31_t)0x7f8b7227, (q31_t)0x7f82d214, (q31_t)0x7f79e35a, + (q31_t)0x7f70a5fe, (q31_t)0x7f671a05, + (q31_t)0x7f5d3f75, (q31_t)0x7f531655, (q31_t)0x7f489eaa, (q31_t)0x7f3dd87c, (q31_t)0x7f32c3d1, (q31_t)0x7f2760af, + (q31_t)0x7f1baf1e, (q31_t)0x7f0faf25, + (q31_t)0x7f0360cb, (q31_t)0x7ef6c418, (q31_t)0x7ee9d914, (q31_t)0x7edc9fc6, (q31_t)0x7ecf1837, (q31_t)0x7ec14270, + (q31_t)0x7eb31e78, (q31_t)0x7ea4ac58, + (q31_t)0x7e95ec1a, (q31_t)0x7e86ddc6, (q31_t)0x7e778166, (q31_t)0x7e67d703, (q31_t)0x7e57dea7, (q31_t)0x7e47985b, + (q31_t)0x7e37042a, (q31_t)0x7e26221f, + (q31_t)0x7e14f242, (q31_t)0x7e0374a0, (q31_t)0x7df1a942, (q31_t)0x7ddf9034, (q31_t)0x7dcd2981, (q31_t)0x7dba7534, + (q31_t)0x7da77359, (q31_t)0x7d9423fc, + (q31_t)0x7d808728, (q31_t)0x7d6c9ce9, (q31_t)0x7d58654d, (q31_t)0x7d43e05e, (q31_t)0x7d2f0e2b, (q31_t)0x7d19eebf, + (q31_t)0x7d048228, (q31_t)0x7ceec873, + (q31_t)0x7cd8c1ae, (q31_t)0x7cc26de5, (q31_t)0x7cabcd28, (q31_t)0x7c94df83, (q31_t)0x7c7da505, (q31_t)0x7c661dbc, + (q31_t)0x7c4e49b7, (q31_t)0x7c362904, + (q31_t)0x7c1dbbb3, (q31_t)0x7c0501d2, (q31_t)0x7bebfb70, (q31_t)0x7bd2a89e, (q31_t)0x7bb9096b, (q31_t)0x7b9f1de6, + (q31_t)0x7b84e61f, (q31_t)0x7b6a6227, + (q31_t)0x7b4f920e, (q31_t)0x7b3475e5, (q31_t)0x7b190dbc, (q31_t)0x7afd59a4, (q31_t)0x7ae159ae, (q31_t)0x7ac50dec, + (q31_t)0x7aa8766f, (q31_t)0x7a8b9348, + (q31_t)0x7a6e648a, (q31_t)0x7a50ea47, (q31_t)0x7a332490, (q31_t)0x7a151378, (q31_t)0x79f6b711, (q31_t)0x79d80f6f, + (q31_t)0x79b91ca4, (q31_t)0x7999dec4, + (q31_t)0x797a55e0, (q31_t)0x795a820e, (q31_t)0x793a6361, (q31_t)0x7919f9ec, (q31_t)0x78f945c3, (q31_t)0x78d846fb, + (q31_t)0x78b6fda8, (q31_t)0x789569df, + (q31_t)0x78738bb3, (q31_t)0x7851633b, (q31_t)0x782ef08b, (q31_t)0x780c33b8, (q31_t)0x77e92cd9, (q31_t)0x77c5dc01, + (q31_t)0x77a24148, (q31_t)0x777e5cc3, + (q31_t)0x775a2e89, (q31_t)0x7735b6af, (q31_t)0x7710f54c, (q31_t)0x76ebea77, (q31_t)0x76c69647, (q31_t)0x76a0f8d2, + (q31_t)0x767b1231, (q31_t)0x7654e279, + (q31_t)0x762e69c4, (q31_t)0x7607a828, (q31_t)0x75e09dbd, (q31_t)0x75b94a9c, (q31_t)0x7591aedd, (q31_t)0x7569ca99, + (q31_t)0x75419de7, (q31_t)0x751928e0, + (q31_t)0x74f06b9e, (q31_t)0x74c7663a, (q31_t)0x749e18cd, (q31_t)0x74748371, (q31_t)0x744aa63f, (q31_t)0x74208150, + (q31_t)0x73f614c0, (q31_t)0x73cb60a8, + (q31_t)0x73a06522, (q31_t)0x73752249, (q31_t)0x73499838, (q31_t)0x731dc70a, (q31_t)0x72f1aed9, (q31_t)0x72c54fc1, + (q31_t)0x7298a9dd, (q31_t)0x726bbd48, + (q31_t)0x723e8a20, (q31_t)0x7211107e, (q31_t)0x71e35080, (q31_t)0x71b54a41, (q31_t)0x7186fdde, (q31_t)0x71586b74, + (q31_t)0x7129931f, (q31_t)0x70fa74fc, + (q31_t)0x70cb1128, (q31_t)0x709b67c0, (q31_t)0x706b78e3, (q31_t)0x703b44ad, (q31_t)0x700acb3c, (q31_t)0x6fda0cae, + (q31_t)0x6fa90921, (q31_t)0x6f77c0b3, + (q31_t)0x6f463383, (q31_t)0x6f1461b0, (q31_t)0x6ee24b57, (q31_t)0x6eaff099, (q31_t)0x6e7d5193, (q31_t)0x6e4a6e66, + (q31_t)0x6e174730, (q31_t)0x6de3dc11, + (q31_t)0x6db02d29, (q31_t)0x6d7c3a98, (q31_t)0x6d48047e, (q31_t)0x6d138afb, (q31_t)0x6cdece2f, (q31_t)0x6ca9ce3b, + (q31_t)0x6c748b3f, (q31_t)0x6c3f055d, + (q31_t)0x6c093cb6, (q31_t)0x6bd3316a, (q31_t)0x6b9ce39b, (q31_t)0x6b66536b, (q31_t)0x6b2f80fb, (q31_t)0x6af86c6c, + (q31_t)0x6ac115e2, (q31_t)0x6a897d7d, + (q31_t)0x6a51a361, (q31_t)0x6a1987b0, (q31_t)0x69e12a8c, (q31_t)0x69a88c19, (q31_t)0x696fac78, (q31_t)0x69368bce, + (q31_t)0x68fd2a3d, (q31_t)0x68c387e9, + (q31_t)0x6889a4f6, (q31_t)0x684f8186, (q31_t)0x68151dbe, (q31_t)0x67da79c3, (q31_t)0x679f95b7, (q31_t)0x676471c0, + (q31_t)0x67290e02, (q31_t)0x66ed6aa1, + (q31_t)0x66b187c3, (q31_t)0x6675658c, (q31_t)0x66390422, (q31_t)0x65fc63a9, (q31_t)0x65bf8447, (q31_t)0x65826622, + (q31_t)0x6545095f, (q31_t)0x65076e25, + (q31_t)0x64c99498, (q31_t)0x648b7ce0, (q31_t)0x644d2722, (q31_t)0x640e9386, (q31_t)0x63cfc231, (q31_t)0x6390b34a, + (q31_t)0x635166f9, (q31_t)0x6311dd64, + (q31_t)0x62d216b3, (q31_t)0x6292130c, (q31_t)0x6251d298, (q31_t)0x6211557e, (q31_t)0x61d09be5, (q31_t)0x618fa5f7, + (q31_t)0x614e73da, (q31_t)0x610d05b7, + (q31_t)0x60cb5bb7, (q31_t)0x60897601, (q31_t)0x604754bf, (q31_t)0x6004f819, (q31_t)0x5fc26038, (q31_t)0x5f7f8d46, + (q31_t)0x5f3c7f6b, (q31_t)0x5ef936d1, + (q31_t)0x5eb5b3a2, (q31_t)0x5e71f606, (q31_t)0x5e2dfe29, (q31_t)0x5de9cc33, (q31_t)0x5da5604f, (q31_t)0x5d60baa7, + (q31_t)0x5d1bdb65, (q31_t)0x5cd6c2b5, + (q31_t)0x5c9170bf, (q31_t)0x5c4be5b0, (q31_t)0x5c0621b2, (q31_t)0x5bc024f0, (q31_t)0x5b79ef96, (q31_t)0x5b3381ce, + (q31_t)0x5aecdbc5, (q31_t)0x5aa5fda5, + (q31_t)0x5a5ee79a, (q31_t)0x5a1799d1, (q31_t)0x59d01475, (q31_t)0x598857b2, (q31_t)0x594063b5, (q31_t)0x58f838a9, + (q31_t)0x58afd6bd, (q31_t)0x58673e1b, + (q31_t)0x581e6ef1, (q31_t)0x57d5696d, (q31_t)0x578c2dba, (q31_t)0x5742bc06, (q31_t)0x56f9147e, (q31_t)0x56af3750, + (q31_t)0x566524aa, (q31_t)0x561adcb9, + (q31_t)0x55d05faa, (q31_t)0x5585adad, (q31_t)0x553ac6ee, (q31_t)0x54efab9c, (q31_t)0x54a45be6, (q31_t)0x5458d7f9, + (q31_t)0x540d2005, (q31_t)0x53c13439, + (q31_t)0x537514c2, (q31_t)0x5328c1d0, (q31_t)0x52dc3b92, (q31_t)0x528f8238, (q31_t)0x524295f0, (q31_t)0x51f576ea, + (q31_t)0x51a82555, (q31_t)0x515aa162, + (q31_t)0x510ceb40, (q31_t)0x50bf031f, (q31_t)0x5070e92f, (q31_t)0x50229da1, (q31_t)0x4fd420a4, (q31_t)0x4f857269, + (q31_t)0x4f369320, (q31_t)0x4ee782fb, + (q31_t)0x4e984229, (q31_t)0x4e48d0dd, (q31_t)0x4df92f46, (q31_t)0x4da95d96, (q31_t)0x4d595bfe, (q31_t)0x4d092ab0, + (q31_t)0x4cb8c9dd, (q31_t)0x4c6839b7, + (q31_t)0x4c177a6e, (q31_t)0x4bc68c36, (q31_t)0x4b756f40, (q31_t)0x4b2423be, (q31_t)0x4ad2a9e2, (q31_t)0x4a8101de, + (q31_t)0x4a2f2be6, (q31_t)0x49dd282a, + (q31_t)0x498af6df, (q31_t)0x49389836, (q31_t)0x48e60c62, (q31_t)0x48935397, (q31_t)0x48406e08, (q31_t)0x47ed5be6, + (q31_t)0x479a1d67, (q31_t)0x4746b2bc, + (q31_t)0x46f31c1a, (q31_t)0x469f59b4, (q31_t)0x464b6bbe, (q31_t)0x45f7526b, (q31_t)0x45a30df0, (q31_t)0x454e9e80, + (q31_t)0x44fa0450, (q31_t)0x44a53f93, + (q31_t)0x4450507e, (q31_t)0x43fb3746, (q31_t)0x43a5f41e, (q31_t)0x4350873c, (q31_t)0x42faf0d4, (q31_t)0x42a5311b, + (q31_t)0x424f4845, (q31_t)0x41f93689, + (q31_t)0x41a2fc1a, (q31_t)0x414c992f, (q31_t)0x40f60dfb, (q31_t)0x409f5ab6, (q31_t)0x40487f94, (q31_t)0x3ff17cca, + (q31_t)0x3f9a5290, (q31_t)0x3f430119, + (q31_t)0x3eeb889c, (q31_t)0x3e93e950, (q31_t)0x3e3c2369, (q31_t)0x3de4371f, (q31_t)0x3d8c24a8, (q31_t)0x3d33ec39, + (q31_t)0x3cdb8e09, (q31_t)0x3c830a50, + (q31_t)0x3c2a6142, (q31_t)0x3bd19318, (q31_t)0x3b78a007, (q31_t)0x3b1f8848, (q31_t)0x3ac64c0f, (q31_t)0x3a6ceb96, + (q31_t)0x3a136712, (q31_t)0x39b9bebc, + (q31_t)0x395ff2c9, (q31_t)0x39060373, (q31_t)0x38abf0ef, (q31_t)0x3851bb77, (q31_t)0x37f76341, (q31_t)0x379ce885, + (q31_t)0x37424b7b, (q31_t)0x36e78c5b, + (q31_t)0x368cab5c, (q31_t)0x3631a8b8, (q31_t)0x35d684a6, (q31_t)0x357b3f5d, (q31_t)0x351fd918, (q31_t)0x34c4520d, + (q31_t)0x3468aa76, (q31_t)0x340ce28b, + (q31_t)0x33b0fa84, (q31_t)0x3354f29b, (q31_t)0x32f8cb07, (q31_t)0x329c8402, (q31_t)0x32401dc6, (q31_t)0x31e39889, + (q31_t)0x3186f487, (q31_t)0x312a31f8, + (q31_t)0x30cd5115, (q31_t)0x30705217, (q31_t)0x30133539, (q31_t)0x2fb5fab2, (q31_t)0x2f58a2be, (q31_t)0x2efb2d95, + (q31_t)0x2e9d9b70, (q31_t)0x2e3fec8b, + (q31_t)0x2de2211e, (q31_t)0x2d843964, (q31_t)0x2d263596, (q31_t)0x2cc815ee, (q31_t)0x2c69daa6, (q31_t)0x2c0b83fa, + (q31_t)0x2bad1221, (q31_t)0x2b4e8558, + (q31_t)0x2aefddd8, (q31_t)0x2a911bdc, (q31_t)0x2a323f9e, (q31_t)0x29d34958, (q31_t)0x29743946, (q31_t)0x29150fa1, + (q31_t)0x28b5cca5, (q31_t)0x2856708d, + (q31_t)0x27f6fb92, (q31_t)0x27976df1, (q31_t)0x2737c7e3, (q31_t)0x26d809a5, (q31_t)0x26783370, (q31_t)0x26184581, + (q31_t)0x25b84012, (q31_t)0x2558235f, + (q31_t)0x24f7efa2, (q31_t)0x2497a517, (q31_t)0x243743fa, (q31_t)0x23d6cc87, (q31_t)0x23763ef7, (q31_t)0x23159b88, + (q31_t)0x22b4e274, (q31_t)0x225413f8, + (q31_t)0x21f3304f, (q31_t)0x219237b5, (q31_t)0x21312a65, (q31_t)0x20d0089c, (q31_t)0x206ed295, (q31_t)0x200d888d, + (q31_t)0x1fac2abf, (q31_t)0x1f4ab968, + (q31_t)0x1ee934c3, (q31_t)0x1e879d0d, (q31_t)0x1e25f282, (q31_t)0x1dc4355e, (q31_t)0x1d6265dd, (q31_t)0x1d00843d, + (q31_t)0x1c9e90b8, (q31_t)0x1c3c8b8c, + (q31_t)0x1bda74f6, (q31_t)0x1b784d30, (q31_t)0x1b161479, (q31_t)0x1ab3cb0d, (q31_t)0x1a517128, (q31_t)0x19ef0707, + (q31_t)0x198c8ce7, (q31_t)0x192a0304, + (q31_t)0x18c7699b, (q31_t)0x1864c0ea, (q31_t)0x1802092c, (q31_t)0x179f429f, (q31_t)0x173c6d80, (q31_t)0x16d98a0c, + (q31_t)0x1676987f, (q31_t)0x16139918, + (q31_t)0x15b08c12, (q31_t)0x154d71aa, (q31_t)0x14ea4a1f, (q31_t)0x148715ae, (q31_t)0x1423d492, (q31_t)0x13c0870a, + (q31_t)0x135d2d53, (q31_t)0x12f9c7aa, + (q31_t)0x1296564d, (q31_t)0x1232d979, (q31_t)0x11cf516a, (q31_t)0x116bbe60, (q31_t)0x11082096, (q31_t)0x10a4784b, + (q31_t)0x1040c5bb, (q31_t)0xfdd0926, + (q31_t)0xf7942c7, (q31_t)0xf1572dc, (q31_t)0xeb199a4, (q31_t)0xe4db75b, (q31_t)0xde9cc40, (q31_t)0xd85d88f, (q31_t)0xd21dc87, + (q31_t)0xcbdd865, + (q31_t)0xc59cc68, (q31_t)0xbf5b8cb, (q31_t)0xb919dcf, (q31_t)0xb2d7baf, (q31_t)0xac952aa, (q31_t)0xa6522fe, (q31_t)0xa00ece8, + (q31_t)0x99cb0a7, + (q31_t)0x9386e78, (q31_t)0x8d42699, (q31_t)0x86fd947, (q31_t)0x80b86c2, (q31_t)0x7a72f45, (q31_t)0x742d311, (q31_t)0x6de7262, + (q31_t)0x67a0d76, + (q31_t)0x615a48b, (q31_t)0x5b137df, (q31_t)0x54cc7b1, (q31_t)0x4e8543e, (q31_t)0x483ddc3, (q31_t)0x41f6480, (q31_t)0x3bae8b2, + (q31_t)0x3566a96, + (q31_t)0x2f1ea6c, (q31_t)0x28d6870, (q31_t)0x228e4e2, (q31_t)0x1c45ffe, (q31_t)0x15fda03, (q31_t)0xfb5330, (q31_t)0x96cbc1, + (q31_t)0x3243f5 +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + const q31_t WeightsQ31_2048[4096] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff8719, (q31_t)0xff501258, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffc8549, (q31_t)0xfe227eac, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4319d, (q31_t)0xfc9075af, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feab61a, (q31_t)0xfb630459, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb7132b, (q31_t)0xf77712e5, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f91b694, (q31_t)0xf581d07b, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f895182, (q31_t)0xf51da273, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f779b62, (q31_t)0xf4555ac5, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f45f47b, (q31_t)0xf26129ba, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f247ba5, (q31_t)0xf1356f32, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f18b679, (q31_t)0xf0d19848, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef390ae, (q31_t)0xefa64cae, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee69217, (q31_t)0xef429caa, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7ed94538, (q31_t)0xeedef6f9, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eaf8943, (q31_t)0xedb44642, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea1039b, (q31_t)0xed50cc46, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e830dff, (q31_t)0xec89fb1e, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e739e1d, (q31_t)0xec26a46d, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e63e03b, (q31_t)0xebc359fb, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e53d462, (q31_t)0xeb601c04, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e437a9c, (q31_t)0xeafceac6, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e21dd73, (q31_t)0xea36af69, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e0374a0, (q31_t)0xe9896781, (q31_t)0x7dff0911, (q31_t)0xe970a9ce, + (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7df62362, (q31_t)0xe93f3107, (q31_t)0x7df1a942, (q31_t)0xe92675f4, (q31_t)0x7ded2a47, (q31_t)0xe90dbbc2, + (q31_t)0x7de8a670, (q31_t)0xe8f50273, (q31_t)0x7de41dc0, (q31_t)0xe8dc4a07, (q31_t)0x7ddf9034, (q31_t)0xe8c39280, (q31_t)0x7ddafdce, (q31_t)0xe8aadbde, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dd1ca75, (q31_t)0xe879714d, (q31_t)0x7dcd2981, (q31_t)0xe860bd61, (q31_t)0x7dc883b4, (q31_t)0xe8480a5d, + (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7dbf298d, (q31_t)0xe816a716, (q31_t)0x7dba7534, (q31_t)0xe7fdf6d4, (q31_t)0x7db5bc02, (q31_t)0xe7e5477f, + (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da2a6c6, (q31_t)0xe782937e, + (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, (q31_t)0x7d98ff17, (q31_t)0xe7513f25, (q31_t)0x7d9423fc, (q31_t)0xe7389665, (q31_t)0x7d8f4409, (q31_t)0xe71fee99, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d85759f, (q31_t)0xe6eea1e4, (q31_t)0x7d808728, (q31_t)0xe6d5fcfc, (q31_t)0x7d7b93da, (q31_t)0xe6bd590d, + (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d719eba, (q31_t)0xe68c141a, (q31_t)0x7d6c9ce9, (q31_t)0xe6737319, (q31_t)0x7d679642, (q31_t)0xe65ad315, + (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d5d7a74, (q31_t)0xe6299604, (q31_t)0x7d58654d, (q31_t)0xe610f8f9, (q31_t)0x7d534b50, (q31_t)0xe5f85cef, + (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, (q31_t)0x7d4908d9, (q31_t)0xe5c727dd, (q31_t)0x7d43e05e, (q31_t)0xe5ae8ed8, (q31_t)0x7d3eb30f, (q31_t)0xe595f6d7, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d3449f5, (q31_t)0xe564c9e3, (q31_t)0x7d2f0e2b, (q31_t)0xe54c34f3, (q31_t)0x7d29cd8c, (q31_t)0xe533a10a, + (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d1f3dd6, (q31_t)0xe5027c53, (q31_t)0x7d19eebf, (q31_t)0xe4e9eb87, (q31_t)0x7d149ad5, (q31_t)0xe4d15bc6, + (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7d09e489, (q31_t)0xe4a03f69, (q31_t)0x7d048228, (q31_t)0xe487b2d0, (q31_t)0x7cff1af5, (q31_t)0xe46f2745, + (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, (q31_t)0x7cf43e1a, (q31_t)0xe43e1362, (q31_t)0x7ceec873, (q31_t)0xe4258b0a, (q31_t)0x7ce94dfb, (q31_t)0xe40d03c6, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7cde4a98, (q31_t)0xe3dbf87a, (q31_t)0x7cd8c1ae, (q31_t)0xe3c37474, (q31_t)0x7cd333f3, (q31_t)0xe3aaf184, + (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7cc80a0f, (q31_t)0xe379eeed, (q31_t)0x7cc26de5, (q31_t)0xe3616f48, (q31_t)0x7cbcccec, (q31_t)0xe348f0bd, + (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7cb17c8d, (q31_t)0xe317f6fa, (q31_t)0x7cabcd28, (q31_t)0xe2ff7bc3, (q31_t)0x7ca618f3, (q31_t)0xe2e701ac, + (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, (q31_t)0x7c9aa221, (q31_t)0xe2b610da, (q31_t)0x7c94df83, (q31_t)0xe29d9a23, (q31_t)0x7c8f1817, (q31_t)0xe285248d, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c837ad8, (q31_t)0xe2543ccc, (q31_t)0x7c7da505, (q31_t)0xe23bcaa2, (q31_t)0x7c77ca65, (q31_t)0xe223599e, + (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c6c06c0, (q31_t)0xe1f27b0b, (q31_t)0x7c661dbc, (q31_t)0xe1da0d7e, (q31_t)0x7c602fec, (q31_t)0xe1c1a11b, + (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c5445e9, (q31_t)0xe190cbd4, (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f, + (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c3c3860, (q31_t)0xe12f2f63, (q31_t)0x7c362904, (q31_t)0xe116cb3d, (q31_t)0x7c3014de, (q31_t)0xe0fe6848, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c179467, (q31_t)0xe09ce871, + (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7bfec765, (q31_t)0xe03b7bf6, + (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7be5ade6, (q31_t)0xdfda2314, + (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bcc47fa, (q31_t)0xdf78de07, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a, + (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b989719, (q31_t)0xdeb69059, + (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b7e4c45, (q31_t)0xde558831, + (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b63b543, (q31_t)0xddf494ce, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b48d225, (q31_t)0xdd93b66a, + (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43, + (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1227d3, (q31_t)0xdcd23993, + (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7af660c2, (q31_t)0xdc719b96, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7ada4dd8, (q31_t)0xdc111388, + (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4, + (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa144bc, (q31_t)0xdb504626, + (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a844eae, (q31_t)0xdaf00149, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a670d0d, (q31_t)0xda8fd349, + (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a497feb, (q31_t)0xda2fbc61, + (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd, + (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79ef1436, (q31_t)0xd910048a, + (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d059c8, (q31_t)0xd8b04c52, + (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b15435, (q31_t)0xd850ac5a, + (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x79920392, (q31_t)0xd7f124dd, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x797267f2, (q31_t)0xd791b616, + (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79528167, (q31_t)0xd732603f, + (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79325006, (q31_t)0xd6d32393, + (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7911d3e2, (q31_t)0xd674004e, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f10d0f, (q31_t)0xd614f6a9, + (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78cffba3, (q31_t)0xd5b606e0, + (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78ae9fb0, (q31_t)0xd557312d, + (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x788cf94c, (q31_t)0xd4f875ca, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x786b088c, (q31_t)0xd499d4f2, + (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x7848cd83, (q31_t)0xd43b4ee0, + (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x78264849, (q31_t)0xd3dce3cd, + (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780378f1, (q31_t)0xd37e93f4, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e05f91, (q31_t)0xd3205f8f, + (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8, + (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77994f11, (q31_t)0xd2644a0a, + (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x7775581d, (q31_t)0xd206695d, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x77511778, (q31_t)0xd1a8a50d, + (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x772c8d3a, (q31_t)0xd14afd52, + (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x7707b979, (q31_t)0xd0ed7267, + (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e29c4b, (q31_t)0xd0900486, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76bd35c7, (q31_t)0xd032b3e7, + (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x76978605, (q31_t)0xcfd580c6, + (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x76718d1c, (q31_t)0xcf786b5a, + (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x764b4b23, (q31_t)0xcf1b73de, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x7624c031, (q31_t)0xcebe9a8a, + (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x75fdec60, (q31_t)0xce61df99, + (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75d6cfc5, (q31_t)0xce054343, + (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x7587bc98, (q31_t)0xcd4c674d, + (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x755fc635, (q31_t)0xccf0281f, + (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x7537876c, (q31_t)0xcc940871, + (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x750f0054, (q31_t)0xcc38087b, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74e63108, (q31_t)0xcbdc2876, + (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74bd199f, (q31_t)0xcb80689a, + (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x7493ba34, (q31_t)0xcb24c921, + (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x746a12df, (q31_t)0xcac94a42, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x744023bc, (q31_t)0xca6dec37, + (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x7415ece2, (q31_t)0xca12af37, + (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a, + (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c0a878, (q31_t)0xc95c993a, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x73959b1b, (q31_t)0xc901c0ae, + (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x736a4671, (q31_t)0xc8a70a0e, + (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x733eaa96, (q31_t)0xc84c7593, + (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x7312c7a5, (q31_t)0xc7f20373, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72e69db7, (q31_t)0xc797b3e7, + (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72ba2cea, (q31_t)0xc73d8727, + (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x728d7557, (q31_t)0xc6e37d69, + (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7260771b, (q31_t)0xc68996e7, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x72333251, (q31_t)0xc62fd3d6, + (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x7205a716, (q31_t)0xc5d6346f, + (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71d7d585, (q31_t)0xc57cb8e9, + (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71a9bdba, (q31_t)0xc523617a, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b, + (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x714cbbeb, (q31_t)0xc4711fc2, + (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x711dd220, (q31_t)0xc41835e6, + (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70eea28e, (q31_t)0xc3bf70fd, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70bf2d53, (q31_t)0xc366d140, + (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x708f728b, (q31_t)0xc30e56e4, + (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x705f7255, (q31_t)0xc2b6021f, + (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x702f2ccd, (q31_t)0xc25dd329, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x6ffea212, (q31_t)0xc205ca38, + (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fcdd241, (q31_t)0xc1ade781, + (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d, + (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f39c57d, (q31_t)0xc0a726df, + (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f07e285, (q31_t)0xc04fdf32, + (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6ed5bb10, (q31_t)0xbff8bece, + (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba, + (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e3daaf8, (q31_t)0xbef44b74, + (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e, + (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6da336dc, (q31_t)0xbdf14135, + (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad, + (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a, + (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d066215, (q31_t)0xbcefa5b0, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5, + (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c, + (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c67300b, (q31_t)0xbbef7e7c, + (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c319975, (q31_t)0xbb9a6fc7, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6bfbc021, (q31_t)0xbb458b43, + (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bc5a431, (q31_t)0xbaf0d125, + (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0, + (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b58a503, (q31_t)0xba47dce8, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b21c208, (q31_t)0xb9f3a332, + (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6aea9cf8, (q31_t)0xb99f94b2, + (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6acef1b2, (q31_t)0xb9759db6, (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6ab335f4, (q31_t)0xb94bb19b, + (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, (q31_t)0x6a9769c1, (q31_t)0xb921d067, (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a7b8d1e, (q31_t)0xb8f7fa21, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a5fa010, (q31_t)0xb8ce2ecf, (q31_t)0x6a51a361, (q31_t)0xb8b94d44, (q31_t)0x6a43a29a, (q31_t)0xb8a46e78, + (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a0b7689, (q31_t)0xb8510ed4, + (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69ef47f6, (q31_t)0xb8276f93, (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69d3090e, (q31_t)0xb7fddb67, + (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69b6b9d3, (q31_t)0xb7d45255, (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x699a5a4c, (q31_t)0xb7aad465, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x69616a65, (q31_t)0xb757fa01, + (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6928397e, (q31_t)0xb7054c6f, + (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2, + (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68b5153a, (q31_t)0xb660788c, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x687b2224, (q31_t)0xb60e529f, + (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50, + (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68067ac3, (q31_t)0xb56a8fd0, + (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67cbc6c0, (q31_t)0xb518f351, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x6790d2b6, (q31_t)0xb4c78507, + (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x67559eca, (q31_t)0xb4764523, + (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x671a2b20, (q31_t)0xb42533d8, + (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66de77dc, (q31_t)0xb3d45157, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66a28524, (q31_t)0xb3839dd3, + (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6666531d, (q31_t)0xb333197c, + (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x6629e1ec, (q31_t)0xb2e2c486, + (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65ed31b5, (q31_t)0xb2929f21, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65b0429f, (q31_t)0xb242a97e, + (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657314cf, (q31_t)0xb1f2e3d0, + (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x6535a86b, (q31_t)0xb1a34e47, + (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x64f7fd98, (q31_t)0xb153e915, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64ba147d, (q31_t)0xb104b46a, + (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x647bed3f, (q31_t)0xb0b5b077, + (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x643d8806, (q31_t)0xb066dd6d, + (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x63fee4f8, (q31_t)0xb0183b7d, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63c0043b, (q31_t)0xafc9cad7, + (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x63a07cc7, (q31_t)0xafa2a50f, (q31_t)0x6390b34a, (q31_t)0xaf8f16d1, (q31_t)0x6380e5f6, (q31_t)0xaf7b8bac, + (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x63418a50, (q31_t)0xaf2d7e2b, + (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, (q31_t)0x6321c585, (q31_t)0xaf068a1a, (q31_t)0x6311dd64, (q31_t)0xaef314c0, (q31_t)0x6301f171, (q31_t)0xaedfa285, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62e20e17, (q31_t)0xaeb8c774, (q31_t)0x62d216b3, (q31_t)0xaea55e9e, (q31_t)0x62c21b7e, (q31_t)0xae91f8eb, + (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x62a219aa, (q31_t)0xae6b36f0, (q31_t)0x6292130c, (q31_t)0xae57daab, (q31_t)0x628208a1, (q31_t)0xae44818b, + (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x6261e866, (q31_t)0xae1dd8c0, (q31_t)0x6251d298, (q31_t)0xae0a8916, (q31_t)0x6241b8ff, (q31_t)0xadf73c96, + (q31_t)0x62319b9d, (q31_t)0xade3f33e, (q31_t)0x62217a72, (q31_t)0xadd0ad12, (q31_t)0x6211557e, (q31_t)0xadbd6a10, (q31_t)0x62012cc2, (q31_t)0xadaa2a3b, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61e0cff5, (q31_t)0xad83b416, (q31_t)0x61d09be5, (q31_t)0xad707dc8, (q31_t)0x61c06410, (q31_t)0xad5d4aaa, + (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x619fe918, (q31_t)0xad36edfc, (q31_t)0x618fa5f7, (q31_t)0xad23c46e, (q31_t)0x617f5f12, (q31_t)0xad109e12, + (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x615ec603, (q31_t)0xacea5af2, (q31_t)0x614e73da, (q31_t)0xacd73e30, (q31_t)0x613e1df0, (q31_t)0xacc424a3, + (q31_t)0x612dc447, (q31_t)0xacb10e4b, (q31_t)0x611d66de, (q31_t)0xac9dfb29, (q31_t)0x610d05b7, (q31_t)0xac8aeb3e, (q31_t)0x60fca0d2, (q31_t)0xac77de8b, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60dbcbd1, (q31_t)0xac51cecf, (q31_t)0x60cb5bb7, (q31_t)0xac3ecbc7, (q31_t)0x60bae7e1, (q31_t)0xac2bcbfa, + (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x6099f505, (q31_t)0xac05d613, (q31_t)0x60897601, (q31_t)0xabf2dffb, (q31_t)0x6078f344, (q31_t)0xabdfed1f, + (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x6057e2a2, (q31_t)0xabba1125, (q31_t)0x604754bf, (q31_t)0xaba72807, (q31_t)0x6036c325, (q31_t)0xab944229, + (q31_t)0x60262dd6, (q31_t)0xab815f8d, (q31_t)0x601594d1, (q31_t)0xab6e8032, (q31_t)0x6004f819, (q31_t)0xab5ba41a, (q31_t)0x5ff457ad, (q31_t)0xab48cb46, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fd30bbc, (q31_t)0xab23236a, (q31_t)0x5fc26038, (q31_t)0xab105464, (q31_t)0x5fb1b104, (q31_t)0xaafd88a4, + (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f90478a, (q31_t)0xaad7fafb, (q31_t)0x5f7f8d46, (q31_t)0xaac53912, (q31_t)0x5f6ecf53, (q31_t)0xaab27a73, + (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0, + (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e, + (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e60fd84, (q31_t)0xa98851ac, + (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e3f0194, (q31_t)0xa9634858, (q31_t)0x5e2dfe29, (q31_t)0xa950c8b0, (q31_t)0x5e1cf71c, (q31_t)0xa93e4c5f, + (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5db680b4, (q31_t)0xa8cfa8d2, (q31_t)0x5da5604f, (q31_t)0xa8bd43fa, (q31_t)0x5d943c4e, (q31_t)0xa8aae280, + (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d71e979, (q31_t)0xa88629a5, (q31_t)0x5d60baa7, (q31_t)0xa873d246, (q31_t)0x5d4f883b, (q31_t)0xa8617e48, + (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5d2d189a, (q31_t)0xa83ce06e, (q31_t)0x5d1bdb65, (q31_t)0xa82a9693, (q31_t)0x5d0a9a9a, (q31_t)0xa818501c, + (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cc57394, (q31_t)0xa7cf582a, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5ca2ca99, (q31_t)0xa7aaf094, (q31_t)0x5c9170bf, (q31_t)0xa798c1e5, (q31_t)0x5c801354, (q31_t)0xa786969e, + (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c5d4dcc, (q31_t)0xa7624a4d, (q31_t)0x5c4be5b0, (q31_t)0xa7502943, (q31_t)0x5c3a7a05, (q31_t)0xa73e0ba5, + (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5c179806, (q31_t)0xa719daae, (q31_t)0x5c0621b2, (q31_t)0xa707c757, (q31_t)0x5bf4a7d2, (q31_t)0xa6f5b76d, + (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, (q31_t)0x5bd1a971, (q31_t)0xa6d1a1e7, (q31_t)0x5bc024f0, (q31_t)0xa6bf9c4b, (q31_t)0x5bae9ce7, (q31_t)0xa6ad9a21, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b8b8239, (q31_t)0xa689a022, (q31_t)0x5b79ef96, (q31_t)0xa677a84e, (q31_t)0x5b68596d, (q31_t)0xa665b3ee, + (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b452288, (q31_t)0xa641d58c, (q31_t)0x5b3381ce, (q31_t)0xa62feb8b, (q31_t)0x5b21dd90, (q31_t)0xa61e0501, + (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5afe8a8b, (q31_t)0xa5fa4252, (q31_t)0x5aecdbc5, (q31_t)0xa5e8662f, (q31_t)0x5adb297d, (q31_t)0xa5d68d85, + (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, (q31_t)0x5ab7ba6c, (q31_t)0xa5b2e6a0, (q31_t)0x5aa5fda5, (q31_t)0xa5a11866, (q31_t)0x5a943d5e, (q31_t)0xa58f4da8, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a70b258, (q31_t)0xa56bc2a2, (q31_t)0x5a5ee79a, (q31_t)0xa55a025b, (q31_t)0x5a4d1960, (q31_t)0xa5484594, + (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x5a29727b, (q31_t)0xa524d683, (q31_t)0x5a1799d1, (q31_t)0xa513243b, (q31_t)0x5a05bdae, (q31_t)0xa5017575, + (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59e1faff, (q31_t)0xa4de2270, (q31_t)0x59d01475, (q31_t)0xa4cc7e32, (q31_t)0x59be2a74, (q31_t)0xa4badd78, + (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, (q31_t)0x599a4c12, (q31_t)0xa497a693, (q31_t)0x598857b2, (q31_t)0xa486106a, (q31_t)0x59765fde, (q31_t)0xa4747dc7, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x595265df, (q31_t)0xa4516319, (q31_t)0x594063b5, (q31_t)0xa43fdb10, (q31_t)0x592e5e19, (q31_t)0xa42e568f, + (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x590a4893, (q31_t)0xa40b582e, (q31_t)0x58f838a9, (q31_t)0xa3f9de4e, (q31_t)0x58e62552, (q31_t)0xa3e867fa, + (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x58c1f45b, (q31_t)0xa3c585fb, (q31_t)0x58afd6bd, (q31_t)0xa3b41a50, (q31_t)0x589db5b3, (q31_t)0xa3a2b234, + (q31_t)0x588b9140, (q31_t)0xa3914da8, (q31_t)0x58796962, (q31_t)0xa37fecac, (q31_t)0x58673e1b, (q31_t)0xa36e8f41, (q31_t)0x58550f6c, (q31_t)0xa35d3567, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x5830a7d6, (q31_t)0xa33a8c6c, (q31_t)0x581e6ef1, (q31_t)0xa3293d4b, (q31_t)0x580c32a7, (q31_t)0xa317f1bf, + (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57e7afe4, (q31_t)0xa2f56566, (q31_t)0x57d5696d, (q31_t)0xa2e4249b, (q31_t)0x57c31f92, (q31_t)0xa2d2e766, + (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x579e81b8, (q31_t)0xa2b077c5, (q31_t)0x578c2dba, (q31_t)0xa29f4559, (q31_t)0x5779d65b, (q31_t)0xa28e1687, + (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, (q31_t)0x57551d80, (q31_t)0xa26bc3b2, (q31_t)0x5742bc06, (q31_t)0xa25a9fb1, (q31_t)0x5730572e, (q31_t)0xa2497f4c, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x570b8369, (q31_t)0xa2274959, (q31_t)0x56f9147e, (q31_t)0xa21633cd, (q31_t)0x56e6a239, (q31_t)0xa20521e0, + (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x56c1b3a1, (q31_t)0xa1e308e4, (q31_t)0x56af3750, (q31_t)0xa1d201d7, (q31_t)0x569cb7a8, (q31_t)0xa1c0fe6c, + (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x5677ae54, (q31_t)0xa19f027c, (q31_t)0x566524aa, (q31_t)0xa18e09fa, (q31_t)0x565297ab, (q31_t)0xa17d151b, + (q31_t)0x56400758, (q31_t)0xa16c23e1, (q31_t)0x562d73b2, (q31_t)0xa15b364d, (q31_t)0x561adcb9, (q31_t)0xa14a4c5e, (q31_t)0x5608426e, (q31_t)0xa1396617, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55e303e6, (q31_t)0xa117a47e, (q31_t)0x55d05faa, (q31_t)0xa106c92f, (q31_t)0x55bdb81f, (q31_t)0xa0f5f189, + (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x55985f20, (q31_t)0xa0d44d3b, (q31_t)0x5585adad, (q31_t)0xa0c38095, (q31_t)0x5572f8ed, (q31_t)0xa0b2b79b, + (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x554d858d, (q31_t)0xa09130ad, (q31_t)0x553ac6ee, (q31_t)0xa08072ba, (q31_t)0x55280505, (q31_t)0xa06fb876, + (q31_t)0x55153fd4, (q31_t)0xa05f01e1, (q31_t)0x5502775c, (q31_t)0xa04e4efc, (q31_t)0x54efab9c, (q31_t)0xa03d9fc8, (q31_t)0x54dcdc96, (q31_t)0xa02cf444, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x54b734ba, (q31_t)0xa00ba853, (q31_t)0x54a45be6, (q31_t)0x9ffb07e7, (q31_t)0x54917fce, (q31_t)0x9fea6b2f, + (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x546bbdd7, (q31_t)0x9fc93cdb, (q31_t)0x5458d7f9, (q31_t)0x9fb8ab41, (q31_t)0x5445eedb, (q31_t)0x9fa81d5e, + (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x542012e1, (q31_t)0x9f870cbc, (q31_t)0x540d2005, (q31_t)0x9f7689ff, (q31_t)0x53fa29ed, (q31_t)0x9f660afb, + (q31_t)0x53e73097, (q31_t)0x9f558fb0, (q31_t)0x53d43406, (q31_t)0x9f45181f, (q31_t)0x53c13439, (q31_t)0x9f34a449, (q31_t)0x53ae3131, (q31_t)0x9f24342f, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x53882175, (q31_t)0x9f035f2e, (q31_t)0x537514c2, (q31_t)0x9ef2fa49, (q31_t)0x536204d7, (q31_t)0x9ee29922, + (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x533bdb5d, (q31_t)0x9ec1e210, (q31_t)0x5328c1d0, (q31_t)0x9eb18c26, (q31_t)0x5315a50e, (q31_t)0x9ea139fd, + (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52ef61ee, (q31_t)0x9e80a0ee, (q31_t)0x52dc3b92, (q31_t)0x9e705a09, (q31_t)0x52c91204, (q31_t)0x9e6016e8, + (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, (q31_t)0x52a2b556, (q31_t)0x9e3f9bf0, (q31_t)0x528f8238, (q31_t)0x9e2f641b, (q31_t)0x527c4bea, (q31_t)0x9e1f300b, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x5255d5c5, (q31_t)0x9dfed33e, (q31_t)0x524295f0, (q31_t)0x9deeaa82, (q31_t)0x522f52ee, (q31_t)0x9dde858e, + (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51e22740, (q31_t)0x9d9e179a, + (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x51bb7e75, (q31_t)0x9d7df75f, (q31_t)0x51a82555, (q31_t)0x9d6decf4, (q31_t)0x5194c910, (q31_t)0x9d5de656, + (q31_t)0x518169a5, (q31_t)0x9d4de385, (q31_t)0x516e0715, (q31_t)0x9d3de482, (q31_t)0x515aa162, (q31_t)0x9d2de94d, (q31_t)0x5147388c, (q31_t)0x9d1df1e9, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x51205d7b, (q31_t)0x9cfe0e8f, (q31_t)0x510ceb40, (q31_t)0x9cee229c, (q31_t)0x50f975e6, (q31_t)0x9cde3a7b, + (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ab814d, (q31_t)0x9c9ec033, + (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x505d5af1, (q31_t)0x9c5f8339, + (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x500f0302, (q31_t)0x9c2083b3, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8, + (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0, + (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f22d3aa, (q31_t)0x9b64f760, + (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e846a60, (q31_t)0x9ae92533, + (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e34ecfc, (q31_t)0x9aab9993, + (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74, + (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4d9561ac, (q31_t)0x9a313dfc, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d455422, (q31_t)0x99f46e51, + (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4cf516ee, (q31_t)0x99b7dd99, + (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8, + (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c540e4e, (q31_t)0x993f7993, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c034345, (q31_t)0x9903a691, + (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bb24958, (q31_t)0x98c81316, + (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b6120bb, (q31_t)0x988cbf46, + (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b0fc99d, (q31_t)0x9851ab46, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4abe4433, (q31_t)0x9816d73b, + (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a6c90ad, (q31_t)0x97dc4349, + (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94, + (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49c8a01b, (q31_t)0x9767dc41, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x49766373, (q31_t)0x972e0971, + (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x4923f97b, (q31_t)0x96f4774b, + (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48d16265, (q31_t)0x96bb25f0, + (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x487e9e64, (q31_t)0x96821585, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x482badab, (q31_t)0x9649462d, + (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47d8906d, (q31_t)0x9610b80a, + (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x478546de, (q31_t)0x95d86b3f, + (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x4731d131, (q31_t)0x95a05ff0, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46de2f99, (q31_t)0x9568963f, + (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x468a624a, (q31_t)0x95310e4e, + (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46366978, (q31_t)0x94f9c83f, + (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45e24556, (q31_t)0x94c2c435, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x458df619, (q31_t)0x948c0252, + (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x45397bf4, (q31_t)0x945582b7, + (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44e4d71c, (q31_t)0x941f4585, + (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449007c4, (q31_t)0x93e94adf, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x443b0e21, (q31_t)0x93b392e6, + (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43e5ea68, (q31_t)0x937e1dbb, + (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43bb48d4, (q31_t)0x93637c3d, (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43909ccd, (q31_t)0x9348eb7e, + (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x433b2585, (q31_t)0x9313fc51, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42e584c3, (q31_t)0x92df5054, + (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x428fbabe, (q31_t)0x92aae7a8, + (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4239c7aa, (q31_t)0x9276c26d, + (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41e3abbc, (q31_t)0x9242e0c4, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x418d6729, (q31_t)0x920f42cb, + (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x4136fa27, (q31_t)0x91dbe8a4, + (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40e064ea, (q31_t)0x91a8d26d, + (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4089a7a8, (q31_t)0x91760047, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x4032c297, (q31_t)0x91437250, + (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fdbb5ec, (q31_t)0x911128a8, + (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f8481dd, (q31_t)0x90df236e, + (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ed5a46b, (q31_t)0x907be6be, + (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e7dfb73, (q31_t)0x904aaf86, + (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e262bee, (q31_t)0x9019bd36, + (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3dce3614, (q31_t)0x8fe90fec, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7, + (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d1dd835, (q31_t)0x8f8884e4, + (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cc5709e, (q31_t)0x8f58a761, + (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c143130, (q31_t)0x8ef9bcf2, + (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bbb59c7, (q31_t)0x8ecab040, + (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b625d86, (q31_t)0x8e9be963, + (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b093ca3, (q31_t)0x8e6d6877, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3adc9e86, (q31_t)0x8e564246, (q31_t)0x3ac64c0f, (q31_t)0x8e4ab5bf, (q31_t)0x3aaff755, (q31_t)0x8e3f2d9b, + (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a834717, (q31_t)0x8e282a7b, (q31_t)0x3a6ceb96, (q31_t)0x8e1caf80, (q31_t)0x3a568dd4, (q31_t)0x8e1138ea, + (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x3a29cb91, (q31_t)0x8dfa58ea, (q31_t)0x3a136712, (q31_t)0x8deeef82, (q31_t)0x39fd0056, (q31_t)0x8de38a80, + (q31_t)0x39e6975e, (q31_t)0x8dd829e4, (q31_t)0x39d02c2a, (q31_t)0x8dcccdaf, (q31_t)0x39b9bebc, (q31_t)0x8dc175e0, (q31_t)0x39a34f13, (q31_t)0x8db6227a, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x39766919, (q31_t)0x8d9f88e5, (q31_t)0x395ff2c9, (q31_t)0x8d9442b8, (q31_t)0x39497a43, (q31_t)0x8d8900f3, + (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x391c8297, (q31_t)0x8d728aa9, (q31_t)0x39060373, (q31_t)0x8d675623, (q31_t)0x38ef821c, (q31_t)0x8d5c2609, + (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x38c278d9, (q31_t)0x8d45d316, (q31_t)0x38abf0ef, (q31_t)0x8d3ab03f, (q31_t)0x389566d6, (q31_t)0x8d2f91d5, + (q31_t)0x387eda8e, (q31_t)0x8d2477d8, (q31_t)0x38684c19, (q31_t)0x8d196249, (q31_t)0x3851bb77, (q31_t)0x8d0e5127, (q31_t)0x383b28a9, (q31_t)0x8d034474, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x380dfc8d, (q31_t)0x8ced385b, (q31_t)0x37f76341, (q31_t)0x8ce238f6, (q31_t)0x37e0c7cc, (q31_t)0x8cd73e01, + (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x37b38a6d, (q31_t)0x8cc1556a, (q31_t)0x379ce885, (q31_t)0x8cb667c8, (q31_t)0x37864477, (q31_t)0x8cab7e98, + (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3758f5f2, (q31_t)0x8c95b98f, (q31_t)0x37424b7b, (q31_t)0x8c8addb7, (q31_t)0x372b9ee3, (q31_t)0x8c800652, + (q31_t)0x3714f02a, (q31_t)0x8c753362, (q31_t)0x36fe3f52, (q31_t)0x8c6a64e5, (q31_t)0x36e78c5b, (q31_t)0x8c5f9ade, (q31_t)0x36d0d746, (q31_t)0x8c54d54c, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x36a366c6, (q31_t)0x8c3f5788, (q31_t)0x368cab5c, (q31_t)0x8c349f58, (q31_t)0x3675edd9, (q31_t)0x8c29eb9f, + (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36486c86, (q31_t)0x8c149192, (q31_t)0x3631a8b8, (q31_t)0x8c09eb40, (q31_t)0x361ae2d3, (q31_t)0x8bff4966, + (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35ed50c9, (q31_t)0x8bea131e, (q31_t)0x35d684a6, (q31_t)0x8bdf7eb0, (q31_t)0x35bfb66e, (q31_t)0x8bd4eebc, + (q31_t)0x35a8e625, (q31_t)0x8bca6343, (q31_t)0x359213c9, (q31_t)0x8bbfdc44, (q31_t)0x357b3f5d, (q31_t)0x8bb559c1, (q31_t)0x356468e2, (q31_t)0x8baadbba, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x3536b5be, (q31_t)0x8b95ed21, (q31_t)0x351fd918, (q31_t)0x8b8b7c8f, (q31_t)0x3508fa66, (q31_t)0x8b81107b, + (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34db36df, (q31_t)0x8b6c45cc, (q31_t)0x34c4520d, (q31_t)0x8b61e733, (q31_t)0x34ad6b32, (q31_t)0x8b578d18, + (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x347f9766, (q31_t)0x8b42e661, (q31_t)0x3468aa76, (q31_t)0x8b3899c6, (q31_t)0x3451bb81, (q31_t)0x8b2e51ab, + (q31_t)0x343aca87, (q31_t)0x8b240e11, (q31_t)0x3423d78a, (q31_t)0x8b19cef8, (q31_t)0x340ce28b, (q31_t)0x8b0f9462, (q31_t)0x33f5eb89, (q31_t)0x8b055e4d, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x33c7f785, (q31_t)0x8af0ffac, (q31_t)0x33b0fa84, (q31_t)0x8ae6d720, (q31_t)0x3399fb85, (q31_t)0x8adcb318, + (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x336bf78f, (q31_t)0x8ac87894, (q31_t)0x3354f29b, (q31_t)0x8abe6219, (q31_t)0x333debab, (q31_t)0x8ab45024, + (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x330fd7e1, (q31_t)0x8aa039cb, (q31_t)0x32f8cb07, (q31_t)0x8a963567, (q31_t)0x32e1bc36, (q31_t)0x8a8c358b, + (q31_t)0x32caab6f, (q31_t)0x8a823a36, (q31_t)0x32b398b3, (q31_t)0x8a784368, (q31_t)0x329c8402, (q31_t)0x8a6e5123, (q31_t)0x32856d5e, (q31_t)0x8a646365, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x32573a3f, (q31_t)0x8a509585, (q31_t)0x32401dc6, (q31_t)0x8a46b564, (q31_t)0x3228ff5c, (q31_t)0x8a3cd9cc, + (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x31fabcbd, (q31_t)0x8a29303b, (q31_t)0x31e39889, (q31_t)0x8a1f6243, (q31_t)0x31cc7269, (q31_t)0x8a1598d6, + (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x319e2067, (q31_t)0x8a0213a0, (q31_t)0x3186f487, (q31_t)0x89f857d8, (q31_t)0x316fc6be, (q31_t)0x89eea09d, + (q31_t)0x3158970e, (q31_t)0x89e4edef, (q31_t)0x31416576, (q31_t)0x89db3fcf, (q31_t)0x312a31f8, (q31_t)0x89d1963c, (q31_t)0x3112fc95, (q31_t)0x89c7f138, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x30e48c22, (q31_t)0x89b4b4dd, (q31_t)0x30cd5115, (q31_t)0x89ab1d87, (q31_t)0x30b61426, (q31_t)0x89a18ac0, + (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x308794a6, (q31_t)0x898e72e4, (q31_t)0x30705217, (q31_t)0x8984edcf, (q31_t)0x30590dab, (q31_t)0x897b6d4c, + (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x302a7f3a, (q31_t)0x896879fb, (q31_t)0x30133539, (q31_t)0x895f072e, (q31_t)0x2ffbe95d, (q31_t)0x895598f3, + (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, (q31_t)0x2fcd4c19, (q31_t)0x8942ca39, (q31_t)0x2fb5fab2, (q31_t)0x893969b9, (q31_t)0x2f9ea775, (q31_t)0x89300dce, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f6ffb7a, (q31_t)0x891d63b5, (q31_t)0x2f58a2be, (q31_t)0x89141589, (q31_t)0x2f41482e, (q31_t)0x890acbf2, + (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2f128d99, (q31_t)0x88f84687, (q31_t)0x2efb2d95, (q31_t)0x88ef0ab4, (q31_t)0x2ee3cbc1, (q31_t)0x88e5d378, + (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2eb502ae, (q31_t)0x88d372c6, (q31_t)0x2e9d9b70, (q31_t)0x88ca4951, (q31_t)0x2e863267, (q31_t)0x88c12475, + (q31_t)0x2e6ec792, (q31_t)0x88b80432, (q31_t)0x2e575af3, (q31_t)0x88aee888, (q31_t)0x2e3fec8b, (q31_t)0x88a5d177, (q31_t)0x2e287c5a, (q31_t)0x889cbf01, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2df996a3, (q31_t)0x888aa7e3, (q31_t)0x2de2211e, (q31_t)0x8881a33d, (q31_t)0x2dcaa9d5, (q31_t)0x8878a332, + (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2d9bb5f6, (q31_t)0x8866b0ef, (q31_t)0x2d843964, (q31_t)0x885dbeb8, (q31_t)0x2d6cbb10, (q31_t)0x8854d11e, + (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2d3db928, (q31_t)0x884303c1, (q31_t)0x2d263596, (q31_t)0x883a23ff, (q31_t)0x2d0eb046, (q31_t)0x883148db, + (q31_t)0x2cf72939, (q31_t)0x88287256, (q31_t)0x2cdfa071, (q31_t)0x881fa06f, (q31_t)0x2cc815ee, (q31_t)0x8816d327, (q31_t)0x2cb089b1, (q31_t)0x880e0a7f, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c816c0c, (q31_t)0x87fc870f, (q31_t)0x2c69daa6, (q31_t)0x87f3cc48, (q31_t)0x2c52478a, (q31_t)0x87eb1621, + (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2c231c33, (q31_t)0x87d9b7b7, (q31_t)0x2c0b83fa, (q31_t)0x87d10f75, (q31_t)0x2bf3ea0d, (q31_t)0x87c86bd5, + (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2bc4b120, (q31_t)0x87b7327d, (q31_t)0x2bad1221, (q31_t)0x87ae9cc5, (q31_t)0x2b957173, (q31_t)0x87a60bb1, + (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, (q31_t)0x2b662b0e, (q31_t)0x8794f774, (q31_t)0x2b4e8558, (q31_t)0x878c744d, (q31_t)0x2b36ddf7, (q31_t)0x8783f5ca, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2b078a36, (q31_t)0x877306b4, (q31_t)0x2aefddd8, (q31_t)0x876a9621, (q31_t)0x2ad82fd2, (q31_t)0x87622a35, + (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2aa8ced3, (q31_t)0x87516050, (q31_t)0x2a911bdc, (q31_t)0x87490258, (q31_t)0x2a796740, (q31_t)0x8740a907, + (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a49f920, (q31_t)0x8730045d, (q31_t)0x2a323f9e, (q31_t)0x8727b905, (q31_t)0x2a1a847b, (q31_t)0x871f7255, + (q31_t)0x2a02c7b8, (q31_t)0x8717304e, (q31_t)0x29eb0957, (q31_t)0x870ef2f1, (q31_t)0x29d34958, (q31_t)0x8706ba3d, (q31_t)0x29bb87bc, (q31_t)0x86fe8633, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x298bffb2, (q31_t)0x86ee2c1e, (q31_t)0x29743946, (q31_t)0x86e60614, (q31_t)0x295c7140, (q31_t)0x86dde4b5, + (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x292cdc6d, (q31_t)0x86cdaffa, (q31_t)0x29150fa1, (q31_t)0x86c59c9f, (q31_t)0x28fd4140, (q31_t)0x86bd8df0, + (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x28cd9fc1, (q31_t)0x86ad7e99, (q31_t)0x28b5cca5, (q31_t)0x86a57df2, (q31_t)0x289df7f8, (q31_t)0x869d81f8, + (q31_t)0x288621b9, (q31_t)0x86958aac, (q31_t)0x286e49ea, (q31_t)0x868d980e, (q31_t)0x2856708d, (q31_t)0x8685aa20, (q31_t)0x283e95a1, (q31_t)0x867dc0e0, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x280edb23, (q31_t)0x866dfc6e, (q31_t)0x27f6fb92, (q31_t)0x8666213c, (q31_t)0x27df1a77, (q31_t)0x865e4abb, + (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27af53a6, (q31_t)0x864eabcb, (q31_t)0x27976df1, (q31_t)0x8646e35c, (q31_t)0x277f86b5, (q31_t)0x863f1f9e, + (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x274fb3ae, (q31_t)0x862fa638, (q31_t)0x2737c7e3, (q31_t)0x8627f091, (q31_t)0x271fda96, (q31_t)0x86203f9c, + (q31_t)0x2707ebc7, (q31_t)0x86189359, (q31_t)0x26effb76, (q31_t)0x8610ebca, (q31_t)0x26d809a5, (q31_t)0x860948ef, (q31_t)0x26c01655, (q31_t)0x8601aac7, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26902b39, (q31_t)0x85f27c93, (q31_t)0x26783370, (q31_t)0x85eaec88, (q31_t)0x26603a2c, (q31_t)0x85e36132, + (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x26304333, (q31_t)0x85d458a6, (q31_t)0x26184581, (q31_t)0x85ccdb70, (q31_t)0x26004657, (q31_t)0x85c562f1, + (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25a03b11, (q31_t)0x85a7b015, + (q31_t)0x2588349d, (q31_t)0x85a04f28, (q31_t)0x25702cb7, (q31_t)0x8598f2f3, (q31_t)0x2558235f, (q31_t)0x85919b76, (q31_t)0x25401896, (q31_t)0x858a48b1, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24dfdf20, (q31_t)0x856d2cd7, + (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24afb9da, (q31_t)0x855ebb44, (q31_t)0x2497a517, (q31_t)0x85578991, (q31_t)0x247f8eec, (q31_t)0x85505c99, + (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x241f2833, (q31_t)0x8533d809, + (q31_t)0x24070b08, (q31_t)0x852cc2bb, (q31_t)0x23eeec78, (q31_t)0x8525b228, (q31_t)0x23d6cc87, (q31_t)0x851ea652, (q31_t)0x23beab33, (q31_t)0x85179f39, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x238e646a, (q31_t)0x85099f3e, (q31_t)0x23763ef7, (q31_t)0x8502a65c, (q31_t)0x235e1826, (q31_t)0x84fbb239, + (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x232dc66d, (q31_t)0x84edd82d, (q31_t)0x23159b88, (q31_t)0x84e6f244, (q31_t)0x22fd6f48, (q31_t)0x84e0111b, + (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0, + (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x223bdd08, (q31_t)0x84a9b2ca, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21daf41d, (q31_t)0x848ef5b7, + (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x21aa77cf, (q31_t)0x8481b3bb, (q31_t)0x219237b5, (q31_t)0x847b19e1, (q31_t)0x2179f64f, (q31_t)0x847484ca, + (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x2118e3dc, (q31_t)0x845a6012, + (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20b7bcfe, (q31_t)0x844087a0, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x205681f1, (q31_t)0x8426fb84, + (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x2025dcec, (q31_t)0x841a521a, (q31_t)0x200d888d, (q31_t)0x84140490, (q31_t)0x1ff532f2, (q31_t)0x840dbbcc, + (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1f93d03c, (q31_t)0x83f4c889, + (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f325a0b, (q31_t)0x83dc21cb, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0, + (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e6f342c, (q31_t)0x83abba17, + (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e0d84f5, (q31_t)0x8393f940, + (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dabc334, (q31_t)0x837c8528, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d49ef26, (q31_t)0x83655ddf, + (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1ce80906, (q31_t)0x834e8373, + (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c861113, (q31_t)0x8337f5f1, + (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c240786, (q31_t)0x8321b568, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6, + (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b5fc097, (q31_t)0x82f61b77, + (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1afd83ad, (q31_t)0x82e0c22a, + (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1a9b361d, (q31_t)0x82cbb60b, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a38d823, (q31_t)0x82b6f727, + (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19d669fc, (q31_t)0x82a2858c, + (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x1973ebe6, (q31_t)0x828e6146, + (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x19115e1c, (q31_t)0x827a8a61, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18aec0db, (q31_t)0x826700e9, + (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x184c1461, (q31_t)0x8253c4eb, + (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17e958ea, (q31_t)0x8240d673, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x17868eb3, (q31_t)0x822e358b, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x1723b5f9, (q31_t)0x821be240, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x165dd9f0, (q31_t)0x81f824ae, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x1597c6b7, (q31_t)0x81d59e13, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x1534a901, (q31_t)0x81c4cf7d, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14d17e36, (q31_t)0x81b44ec4, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x146e4694, (q31_t)0x81a41bf4, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x140b0258, (q31_t)0x81943715, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13a7b1bf, (q31_t)0x8184a032, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x13445505, (q31_t)0x81755754, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12e0ec6a, (q31_t)0x81665c84, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x127d7829, (q31_t)0x8157afcd, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x1219f880, (q31_t)0x81495136, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11b66dad, (q31_t)0x813b40ca, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x10ef377d, (q31_t)0x81200a90, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x1027d784, (q31_t)0x81060d63, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfc41876, (q31_t)0x80f98446, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf604faf, (q31_t)0x80ed4984, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xefc7d6b, (q31_t)0x80e15d24, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd08dc3f, (q31_t)0x80aa5806, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xca4d620, (q31_t)0x80a04289, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc40c835, (q31_t)0x80967b9f, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbdcb2bb, (q31_t)0x808d034c, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb7895f0, (q31_t)0x8083d998, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb147211, (q31_t)0x807afe87, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xab0475c, (q31_t)0x8072721f, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa4c1610, (q31_t)0x806a3466, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9e7de6a, (q31_t)0x80624560, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x983a0a7, (q31_t)0x805aa512, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x91f5d06, (q31_t)0x80535381, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8bb13c5, (q31_t)0x804c50b2, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x856c520, (q31_t)0x80459ca9, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x7f27157, (q31_t)0x803f376a, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x78e18a7, (q31_t)0x803920f8, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x729bb4e, (q31_t)0x80335959, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6c5598a, (q31_t)0x802de08e, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x660f398, (q31_t)0x8028b69c, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x5fc89b8, (q31_t)0x8023db86, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5981c26, (q31_t)0x801f4f4f, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x533ab20, (q31_t)0x801b11fa, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4cf36e5, (q31_t)0x80172388, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x46abfb3, (q31_t)0x801383fe, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x40645c7, (q31_t)0x8010335c, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3a1c960, (q31_t)0x800d31a5, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x33d4abb, (q31_t)0x800a7edb, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2d8ca16, (q31_t)0x80081b00, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x27447b0, (q31_t)0x80060614, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x20fc3c6, (q31_t)0x8004401a, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1ab3e97, (q31_t)0x8002c912, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x146b860, (q31_t)0x8001a0fd, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0xe23160, (q31_t)0x8000c7dc, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x7da9d4, (q31_t)0x80003daf, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x1921fb, (q31_t)0x80000278 +}; + const q31_t cos_factorsQ31_2048[2048] = { + (q31_t)0x7fffff62, (q31_t)0x7ffffa73, (q31_t)0x7ffff094, (q31_t)0x7fffe1c6, (q31_t)0x7fffce09, (q31_t)0x7fffb55c, + (q31_t)0x7fff97c1, (q31_t)0x7fff7536, + (q31_t)0x7fff4dbb, (q31_t)0x7fff2151, (q31_t)0x7ffeeff8, (q31_t)0x7ffeb9b0, (q31_t)0x7ffe7e79, (q31_t)0x7ffe3e52, + (q31_t)0x7ffdf93c, (q31_t)0x7ffdaf37, + (q31_t)0x7ffd6042, (q31_t)0x7ffd0c5f, (q31_t)0x7ffcb38c, (q31_t)0x7ffc55ca, (q31_t)0x7ffbf319, (q31_t)0x7ffb8b78, + (q31_t)0x7ffb1ee9, (q31_t)0x7ffaad6a, + (q31_t)0x7ffa36fc, (q31_t)0x7ff9bba0, (q31_t)0x7ff93b54, (q31_t)0x7ff8b619, (q31_t)0x7ff82bef, (q31_t)0x7ff79cd6, + (q31_t)0x7ff708ce, (q31_t)0x7ff66fd7, + (q31_t)0x7ff5d1f1, (q31_t)0x7ff52f1d, (q31_t)0x7ff48759, (q31_t)0x7ff3daa6, (q31_t)0x7ff32905, (q31_t)0x7ff27275, + (q31_t)0x7ff1b6f6, (q31_t)0x7ff0f688, + (q31_t)0x7ff0312c, (q31_t)0x7fef66e1, (q31_t)0x7fee97a7, (q31_t)0x7fedc37e, (q31_t)0x7fecea67, (q31_t)0x7fec0c62, + (q31_t)0x7feb296d, (q31_t)0x7fea418b, + (q31_t)0x7fe954ba, (q31_t)0x7fe862fa, (q31_t)0x7fe76c4c, (q31_t)0x7fe670b0, (q31_t)0x7fe57025, (q31_t)0x7fe46aac, + (q31_t)0x7fe36045, (q31_t)0x7fe250ef, + (q31_t)0x7fe13cac, (q31_t)0x7fe0237a, (q31_t)0x7fdf055a, (q31_t)0x7fdde24d, (q31_t)0x7fdcba51, (q31_t)0x7fdb8d67, + (q31_t)0x7fda5b8f, (q31_t)0x7fd924ca, + (q31_t)0x7fd7e917, (q31_t)0x7fd6a875, (q31_t)0x7fd562e7, (q31_t)0x7fd4186a, (q31_t)0x7fd2c900, (q31_t)0x7fd174a8, + (q31_t)0x7fd01b63, (q31_t)0x7fcebd31, + (q31_t)0x7fcd5a11, (q31_t)0x7fcbf203, (q31_t)0x7fca8508, (q31_t)0x7fc91320, (q31_t)0x7fc79c4b, (q31_t)0x7fc62089, + (q31_t)0x7fc49fda, (q31_t)0x7fc31a3d, + (q31_t)0x7fc18fb4, (q31_t)0x7fc0003e, (q31_t)0x7fbe6bdb, (q31_t)0x7fbcd28b, (q31_t)0x7fbb344e, (q31_t)0x7fb99125, + (q31_t)0x7fb7e90f, (q31_t)0x7fb63c0d, + (q31_t)0x7fb48a1e, (q31_t)0x7fb2d343, (q31_t)0x7fb1177b, (q31_t)0x7faf56c7, (q31_t)0x7fad9127, (q31_t)0x7fabc69b, + (q31_t)0x7fa9f723, (q31_t)0x7fa822bf, + (q31_t)0x7fa6496e, (q31_t)0x7fa46b32, (q31_t)0x7fa2880b, (q31_t)0x7fa09ff7, (q31_t)0x7f9eb2f8, (q31_t)0x7f9cc10d, + (q31_t)0x7f9aca37, (q31_t)0x7f98ce76, + (q31_t)0x7f96cdc9, (q31_t)0x7f94c831, (q31_t)0x7f92bdad, (q31_t)0x7f90ae3f, (q31_t)0x7f8e99e6, (q31_t)0x7f8c80a1, + (q31_t)0x7f8a6272, (q31_t)0x7f883f58, + (q31_t)0x7f861753, (q31_t)0x7f83ea64, (q31_t)0x7f81b88a, (q31_t)0x7f7f81c6, (q31_t)0x7f7d4617, (q31_t)0x7f7b057e, + (q31_t)0x7f78bffb, (q31_t)0x7f76758e, + (q31_t)0x7f742637, (q31_t)0x7f71d1f6, (q31_t)0x7f6f78cb, (q31_t)0x7f6d1ab6, (q31_t)0x7f6ab7b8, (q31_t)0x7f684fd0, + (q31_t)0x7f65e2ff, (q31_t)0x7f637144, + (q31_t)0x7f60faa0, (q31_t)0x7f5e7f13, (q31_t)0x7f5bfe9d, (q31_t)0x7f59793e, (q31_t)0x7f56eef5, (q31_t)0x7f545fc5, + (q31_t)0x7f51cbab, (q31_t)0x7f4f32a9, + (q31_t)0x7f4c94be, (q31_t)0x7f49f1eb, (q31_t)0x7f474a30, (q31_t)0x7f449d8c, (q31_t)0x7f41ec01, (q31_t)0x7f3f358d, + (q31_t)0x7f3c7a31, (q31_t)0x7f39b9ee, + (q31_t)0x7f36f4c3, (q31_t)0x7f342ab1, (q31_t)0x7f315bb7, (q31_t)0x7f2e87d6, (q31_t)0x7f2baf0d, (q31_t)0x7f28d15d, + (q31_t)0x7f25eec7, (q31_t)0x7f230749, + (q31_t)0x7f201ae5, (q31_t)0x7f1d299a, (q31_t)0x7f1a3368, (q31_t)0x7f173850, (q31_t)0x7f143852, (q31_t)0x7f11336d, + (q31_t)0x7f0e29a3, (q31_t)0x7f0b1af2, + (q31_t)0x7f08075c, (q31_t)0x7f04eedf, (q31_t)0x7f01d17d, (q31_t)0x7efeaf36, (q31_t)0x7efb8809, (q31_t)0x7ef85bf7, + (q31_t)0x7ef52b00, (q31_t)0x7ef1f524, + (q31_t)0x7eeeba62, (q31_t)0x7eeb7abc, (q31_t)0x7ee83632, (q31_t)0x7ee4ecc3, (q31_t)0x7ee19e6f, (q31_t)0x7ede4b38, + (q31_t)0x7edaf31c, (q31_t)0x7ed7961c, + (q31_t)0x7ed43438, (q31_t)0x7ed0cd70, (q31_t)0x7ecd61c5, (q31_t)0x7ec9f137, (q31_t)0x7ec67bc5, (q31_t)0x7ec3016f, + (q31_t)0x7ebf8237, (q31_t)0x7ebbfe1c, + (q31_t)0x7eb8751e, (q31_t)0x7eb4e73d, (q31_t)0x7eb1547a, (q31_t)0x7eadbcd4, (q31_t)0x7eaa204c, (q31_t)0x7ea67ee2, + (q31_t)0x7ea2d896, (q31_t)0x7e9f2d68, + (q31_t)0x7e9b7d58, (q31_t)0x7e97c867, (q31_t)0x7e940e94, (q31_t)0x7e904fe0, (q31_t)0x7e8c8c4b, (q31_t)0x7e88c3d5, + (q31_t)0x7e84f67e, (q31_t)0x7e812447, + (q31_t)0x7e7d4d2f, (q31_t)0x7e797136, (q31_t)0x7e75905d, (q31_t)0x7e71aaa4, (q31_t)0x7e6dc00c, (q31_t)0x7e69d093, + (q31_t)0x7e65dc3b, (q31_t)0x7e61e303, + (q31_t)0x7e5de4ec, (q31_t)0x7e59e1f5, (q31_t)0x7e55da20, (q31_t)0x7e51cd6c, (q31_t)0x7e4dbbd9, (q31_t)0x7e49a567, + (q31_t)0x7e458a17, (q31_t)0x7e4169e9, + (q31_t)0x7e3d44dd, (q31_t)0x7e391af3, (q31_t)0x7e34ec2b, (q31_t)0x7e30b885, (q31_t)0x7e2c8002, (q31_t)0x7e2842a2, + (q31_t)0x7e240064, (q31_t)0x7e1fb94a, + (q31_t)0x7e1b6d53, (q31_t)0x7e171c7f, (q31_t)0x7e12c6ce, (q31_t)0x7e0e6c42, (q31_t)0x7e0a0cd9, (q31_t)0x7e05a894, + (q31_t)0x7e013f74, (q31_t)0x7dfcd178, + (q31_t)0x7df85ea0, (q31_t)0x7df3e6ee, (q31_t)0x7def6a60, (q31_t)0x7deae8f7, (q31_t)0x7de662b3, (q31_t)0x7de1d795, + (q31_t)0x7ddd479d, (q31_t)0x7dd8b2ca, + (q31_t)0x7dd4191d, (q31_t)0x7dcf7a96, (q31_t)0x7dcad736, (q31_t)0x7dc62efc, (q31_t)0x7dc181e8, (q31_t)0x7dbccffc, + (q31_t)0x7db81936, (q31_t)0x7db35d98, + (q31_t)0x7dae9d21, (q31_t)0x7da9d7d2, (q31_t)0x7da50dab, (q31_t)0x7da03eab, (q31_t)0x7d9b6ad3, (q31_t)0x7d969224, + (q31_t)0x7d91b49e, (q31_t)0x7d8cd240, + (q31_t)0x7d87eb0a, (q31_t)0x7d82fefe, (q31_t)0x7d7e0e1c, (q31_t)0x7d791862, (q31_t)0x7d741dd2, (q31_t)0x7d6f1e6c, + (q31_t)0x7d6a1a31, (q31_t)0x7d65111f, + (q31_t)0x7d600338, (q31_t)0x7d5af07b, (q31_t)0x7d55d8e9, (q31_t)0x7d50bc82, (q31_t)0x7d4b9b46, (q31_t)0x7d467536, + (q31_t)0x7d414a51, (q31_t)0x7d3c1a98, + (q31_t)0x7d36e60b, (q31_t)0x7d31acaa, (q31_t)0x7d2c6e76, (q31_t)0x7d272b6e, (q31_t)0x7d21e393, (q31_t)0x7d1c96e5, + (q31_t)0x7d174564, (q31_t)0x7d11ef11, + (q31_t)0x7d0c93eb, (q31_t)0x7d0733f3, (q31_t)0x7d01cf29, (q31_t)0x7cfc658d, (q31_t)0x7cf6f720, (q31_t)0x7cf183e1, + (q31_t)0x7cec0bd1, (q31_t)0x7ce68ef0, + (q31_t)0x7ce10d3f, (q31_t)0x7cdb86bd, (q31_t)0x7cd5fb6a, (q31_t)0x7cd06b48, (q31_t)0x7ccad656, (q31_t)0x7cc53c94, + (q31_t)0x7cbf9e03, (q31_t)0x7cb9faa2, + (q31_t)0x7cb45272, (q31_t)0x7caea574, (q31_t)0x7ca8f3a7, (q31_t)0x7ca33d0c, (q31_t)0x7c9d81a3, (q31_t)0x7c97c16b, + (q31_t)0x7c91fc66, (q31_t)0x7c8c3294, + (q31_t)0x7c8663f4, (q31_t)0x7c809088, (q31_t)0x7c7ab84e, (q31_t)0x7c74db48, (q31_t)0x7c6ef976, (q31_t)0x7c6912d7, + (q31_t)0x7c63276d, (q31_t)0x7c5d3737, + (q31_t)0x7c574236, (q31_t)0x7c514869, (q31_t)0x7c4b49d2, (q31_t)0x7c45466f, (q31_t)0x7c3f3e42, (q31_t)0x7c39314b, + (q31_t)0x7c331f8a, (q31_t)0x7c2d08ff, + (q31_t)0x7c26edab, (q31_t)0x7c20cd8d, (q31_t)0x7c1aa8a6, (q31_t)0x7c147ef6, (q31_t)0x7c0e507e, (q31_t)0x7c081d3d, + (q31_t)0x7c01e534, (q31_t)0x7bfba863, + (q31_t)0x7bf566cb, (q31_t)0x7bef206b, (q31_t)0x7be8d544, (q31_t)0x7be28556, (q31_t)0x7bdc30a1, (q31_t)0x7bd5d726, + (q31_t)0x7bcf78e5, (q31_t)0x7bc915dd, + (q31_t)0x7bc2ae10, (q31_t)0x7bbc417e, (q31_t)0x7bb5d026, (q31_t)0x7baf5a09, (q31_t)0x7ba8df28, (q31_t)0x7ba25f82, + (q31_t)0x7b9bdb18, (q31_t)0x7b9551ea, + (q31_t)0x7b8ec3f8, (q31_t)0x7b883143, (q31_t)0x7b8199ca, (q31_t)0x7b7afd8f, (q31_t)0x7b745c91, (q31_t)0x7b6db6d0, + (q31_t)0x7b670c4d, (q31_t)0x7b605d09, + (q31_t)0x7b59a902, (q31_t)0x7b52f03a, (q31_t)0x7b4c32b1, (q31_t)0x7b457068, (q31_t)0x7b3ea95d, (q31_t)0x7b37dd92, + (q31_t)0x7b310d07, (q31_t)0x7b2a37bc, + (q31_t)0x7b235db2, (q31_t)0x7b1c7ee8, (q31_t)0x7b159b5f, (q31_t)0x7b0eb318, (q31_t)0x7b07c612, (q31_t)0x7b00d44d, + (q31_t)0x7af9ddcb, (q31_t)0x7af2e28b, + (q31_t)0x7aebe28d, (q31_t)0x7ae4ddd2, (q31_t)0x7addd45b, (q31_t)0x7ad6c626, (q31_t)0x7acfb336, (q31_t)0x7ac89b89, + (q31_t)0x7ac17f20, (q31_t)0x7aba5dfc, + (q31_t)0x7ab3381d, (q31_t)0x7aac0d82, (q31_t)0x7aa4de2d, (q31_t)0x7a9daa1d, (q31_t)0x7a967153, (q31_t)0x7a8f33d0, + (q31_t)0x7a87f192, (q31_t)0x7a80aa9c, + (q31_t)0x7a795eec, (q31_t)0x7a720e84, (q31_t)0x7a6ab963, (q31_t)0x7a635f8a, (q31_t)0x7a5c00f9, (q31_t)0x7a549db0, + (q31_t)0x7a4d35b0, (q31_t)0x7a45c8f9, + (q31_t)0x7a3e578b, (q31_t)0x7a36e166, (q31_t)0x7a2f668c, (q31_t)0x7a27e6fb, (q31_t)0x7a2062b5, (q31_t)0x7a18d9b9, + (q31_t)0x7a114c09, (q31_t)0x7a09b9a4, + (q31_t)0x7a02228a, (q31_t)0x79fa86bc, (q31_t)0x79f2e63a, (q31_t)0x79eb4105, (q31_t)0x79e3971c, (q31_t)0x79dbe880, + (q31_t)0x79d43532, (q31_t)0x79cc7d31, + (q31_t)0x79c4c07e, (q31_t)0x79bcff19, (q31_t)0x79b53903, (q31_t)0x79ad6e3c, (q31_t)0x79a59ec3, (q31_t)0x799dca9a, + (q31_t)0x7995f1c1, (q31_t)0x798e1438, + (q31_t)0x798631ff, (q31_t)0x797e4b16, (q31_t)0x79765f7f, (q31_t)0x796e6f39, (q31_t)0x79667a44, (q31_t)0x795e80a1, + (q31_t)0x79568250, (q31_t)0x794e7f52, + (q31_t)0x794677a6, (q31_t)0x793e6b4e, (q31_t)0x79365a49, (q31_t)0x792e4497, (q31_t)0x79262a3a, (q31_t)0x791e0b31, + (q31_t)0x7915e77c, (q31_t)0x790dbf1d, + (q31_t)0x79059212, (q31_t)0x78fd605d, (q31_t)0x78f529fe, (q31_t)0x78eceef6, (q31_t)0x78e4af44, (q31_t)0x78dc6ae8, + (q31_t)0x78d421e4, (q31_t)0x78cbd437, + (q31_t)0x78c381e2, (q31_t)0x78bb2ae5, (q31_t)0x78b2cf41, (q31_t)0x78aa6ef5, (q31_t)0x78a20a03, (q31_t)0x7899a06a, + (q31_t)0x7891322a, (q31_t)0x7888bf45, + (q31_t)0x788047ba, (q31_t)0x7877cb89, (q31_t)0x786f4ab4, (q31_t)0x7866c53a, (q31_t)0x785e3b1c, (q31_t)0x7855ac5a, + (q31_t)0x784d18f4, (q31_t)0x784480ea, + (q31_t)0x783be43e, (q31_t)0x783342ef, (q31_t)0x782a9cfe, (q31_t)0x7821f26b, (q31_t)0x78194336, (q31_t)0x78108f60, + (q31_t)0x7807d6e9, (q31_t)0x77ff19d1, + (q31_t)0x77f65819, (q31_t)0x77ed91c0, (q31_t)0x77e4c6c9, (q31_t)0x77dbf732, (q31_t)0x77d322fc, (q31_t)0x77ca4a27, + (q31_t)0x77c16cb4, (q31_t)0x77b88aa3, + (q31_t)0x77afa3f5, (q31_t)0x77a6b8a9, (q31_t)0x779dc8c0, (q31_t)0x7794d43b, (q31_t)0x778bdb19, (q31_t)0x7782dd5c, + (q31_t)0x7779db03, (q31_t)0x7770d40f, + (q31_t)0x7767c880, (q31_t)0x775eb857, (q31_t)0x7755a394, (q31_t)0x774c8a36, (q31_t)0x77436c40, (q31_t)0x773a49b0, + (q31_t)0x77312287, (q31_t)0x7727f6c6, + (q31_t)0x771ec66e, (q31_t)0x7715917d, (q31_t)0x770c57f5, (q31_t)0x770319d6, (q31_t)0x76f9d721, (q31_t)0x76f08fd5, + (q31_t)0x76e743f4, (q31_t)0x76ddf37c, + (q31_t)0x76d49e70, (q31_t)0x76cb44cf, (q31_t)0x76c1e699, (q31_t)0x76b883d0, (q31_t)0x76af1c72, (q31_t)0x76a5b082, + (q31_t)0x769c3ffe, (q31_t)0x7692cae8, + (q31_t)0x7689513f, (q31_t)0x767fd304, (q31_t)0x76765038, (q31_t)0x766cc8db, (q31_t)0x76633ced, (q31_t)0x7659ac6f, + (q31_t)0x76501760, (q31_t)0x76467dc2, + (q31_t)0x763cdf94, (q31_t)0x76333cd8, (q31_t)0x7629958c, (q31_t)0x761fe9b3, (q31_t)0x7616394c, (q31_t)0x760c8457, + (q31_t)0x7602cad5, (q31_t)0x75f90cc7, + (q31_t)0x75ef4a2c, (q31_t)0x75e58305, (q31_t)0x75dbb753, (q31_t)0x75d1e715, (q31_t)0x75c8124d, (q31_t)0x75be38fa, + (q31_t)0x75b45b1d, (q31_t)0x75aa78b6, + (q31_t)0x75a091c6, (q31_t)0x7596a64d, (q31_t)0x758cb64c, (q31_t)0x7582c1c2, (q31_t)0x7578c8b0, (q31_t)0x756ecb18, + (q31_t)0x7564c8f8, (q31_t)0x755ac251, + (q31_t)0x7550b725, (q31_t)0x7546a772, (q31_t)0x753c933a, (q31_t)0x75327a7d, (q31_t)0x75285d3b, (q31_t)0x751e3b75, + (q31_t)0x7514152b, (q31_t)0x7509ea5d, + (q31_t)0x74ffbb0d, (q31_t)0x74f58739, (q31_t)0x74eb4ee3, (q31_t)0x74e1120c, (q31_t)0x74d6d0b2, (q31_t)0x74cc8ad8, + (q31_t)0x74c2407d, (q31_t)0x74b7f1a1, + (q31_t)0x74ad9e46, (q31_t)0x74a3466b, (q31_t)0x7498ea11, (q31_t)0x748e8938, (q31_t)0x748423e0, (q31_t)0x7479ba0b, + (q31_t)0x746f4bb8, (q31_t)0x7464d8e8, + (q31_t)0x745a619b, (q31_t)0x744fe5d2, (q31_t)0x7445658d, (q31_t)0x743ae0cc, (q31_t)0x74305790, (q31_t)0x7425c9da, + (q31_t)0x741b37a9, (q31_t)0x7410a0fe, + (q31_t)0x740605d9, (q31_t)0x73fb663c, (q31_t)0x73f0c226, (q31_t)0x73e61997, (q31_t)0x73db6c91, (q31_t)0x73d0bb13, + (q31_t)0x73c6051f, (q31_t)0x73bb4ab3, + (q31_t)0x73b08bd1, (q31_t)0x73a5c87a, (q31_t)0x739b00ad, (q31_t)0x7390346b, (q31_t)0x738563b5, (q31_t)0x737a8e8a, + (q31_t)0x736fb4ec, (q31_t)0x7364d6da, + (q31_t)0x7359f456, (q31_t)0x734f0d5f, (q31_t)0x734421f6, (q31_t)0x7339321b, (q31_t)0x732e3dcf, (q31_t)0x73234512, + (q31_t)0x731847e5, (q31_t)0x730d4648, + (q31_t)0x7302403c, (q31_t)0x72f735c0, (q31_t)0x72ec26d6, (q31_t)0x72e1137d, (q31_t)0x72d5fbb7, (q31_t)0x72cadf83, + (q31_t)0x72bfbee3, (q31_t)0x72b499d6, + (q31_t)0x72a9705c, (q31_t)0x729e4277, (q31_t)0x72931027, (q31_t)0x7287d96c, (q31_t)0x727c9e47, (q31_t)0x72715eb8, + (q31_t)0x72661abf, (q31_t)0x725ad25d, + (q31_t)0x724f8593, (q31_t)0x72443460, (q31_t)0x7238dec5, (q31_t)0x722d84c4, (q31_t)0x7222265b, (q31_t)0x7216c38c, + (q31_t)0x720b5c57, (q31_t)0x71fff0bc, + (q31_t)0x71f480bc, (q31_t)0x71e90c57, (q31_t)0x71dd938f, (q31_t)0x71d21662, (q31_t)0x71c694d2, (q31_t)0x71bb0edf, + (q31_t)0x71af848a, (q31_t)0x71a3f5d2, + (q31_t)0x719862b9, (q31_t)0x718ccb3f, (q31_t)0x71812f65, (q31_t)0x71758f29, (q31_t)0x7169ea8f, (q31_t)0x715e4194, + (q31_t)0x7152943b, (q31_t)0x7146e284, + (q31_t)0x713b2c6e, (q31_t)0x712f71fb, (q31_t)0x7123b32b, (q31_t)0x7117effe, (q31_t)0x710c2875, (q31_t)0x71005c90, + (q31_t)0x70f48c50, (q31_t)0x70e8b7b5, + (q31_t)0x70dcdec0, (q31_t)0x70d10171, (q31_t)0x70c51fc8, (q31_t)0x70b939c7, (q31_t)0x70ad4f6d, (q31_t)0x70a160ba, + (q31_t)0x70956db1, (q31_t)0x70897650, + (q31_t)0x707d7a98, (q31_t)0x70717a8a, (q31_t)0x70657626, (q31_t)0x70596d6d, (q31_t)0x704d6060, (q31_t)0x70414efd, + (q31_t)0x70353947, (q31_t)0x70291f3e, + (q31_t)0x701d00e1, (q31_t)0x7010de32, (q31_t)0x7004b731, (q31_t)0x6ff88bde, (q31_t)0x6fec5c3b, (q31_t)0x6fe02846, + (q31_t)0x6fd3f001, (q31_t)0x6fc7b36d, + (q31_t)0x6fbb728a, (q31_t)0x6faf2d57, (q31_t)0x6fa2e3d7, (q31_t)0x6f969608, (q31_t)0x6f8a43ed, (q31_t)0x6f7ded84, + (q31_t)0x6f7192cf, (q31_t)0x6f6533ce, + (q31_t)0x6f58d082, (q31_t)0x6f4c68eb, (q31_t)0x6f3ffd09, (q31_t)0x6f338cde, (q31_t)0x6f271868, (q31_t)0x6f1a9faa, + (q31_t)0x6f0e22a3, (q31_t)0x6f01a155, + (q31_t)0x6ef51bbe, (q31_t)0x6ee891e1, (q31_t)0x6edc03bc, (q31_t)0x6ecf7152, (q31_t)0x6ec2daa2, (q31_t)0x6eb63fad, + (q31_t)0x6ea9a073, (q31_t)0x6e9cfcf5, + (q31_t)0x6e905534, (q31_t)0x6e83a92f, (q31_t)0x6e76f8e7, (q31_t)0x6e6a445d, (q31_t)0x6e5d8b91, (q31_t)0x6e50ce84, + (q31_t)0x6e440d37, (q31_t)0x6e3747a9, + (q31_t)0x6e2a7ddb, (q31_t)0x6e1dafce, (q31_t)0x6e10dd82, (q31_t)0x6e0406f8, (q31_t)0x6df72c30, (q31_t)0x6dea4d2b, + (q31_t)0x6ddd69e9, (q31_t)0x6dd0826a, + (q31_t)0x6dc396b0, (q31_t)0x6db6a6ba, (q31_t)0x6da9b28a, (q31_t)0x6d9cba1f, (q31_t)0x6d8fbd7a, (q31_t)0x6d82bc9d, + (q31_t)0x6d75b786, (q31_t)0x6d68ae37, + (q31_t)0x6d5ba0b0, (q31_t)0x6d4e8ef2, (q31_t)0x6d4178fd, (q31_t)0x6d345ed1, (q31_t)0x6d274070, (q31_t)0x6d1a1dda, + (q31_t)0x6d0cf70f, (q31_t)0x6cffcc0f, + (q31_t)0x6cf29cdc, (q31_t)0x6ce56975, (q31_t)0x6cd831dc, (q31_t)0x6ccaf610, (q31_t)0x6cbdb613, (q31_t)0x6cb071e4, + (q31_t)0x6ca32985, (q31_t)0x6c95dcf6, + (q31_t)0x6c888c36, (q31_t)0x6c7b3748, (q31_t)0x6c6dde2b, (q31_t)0x6c6080e0, (q31_t)0x6c531f67, (q31_t)0x6c45b9c1, + (q31_t)0x6c384fef, (q31_t)0x6c2ae1f0, + (q31_t)0x6c1d6fc6, (q31_t)0x6c0ff971, (q31_t)0x6c027ef1, (q31_t)0x6bf50047, (q31_t)0x6be77d74, (q31_t)0x6bd9f677, + (q31_t)0x6bcc6b53, (q31_t)0x6bbedc06, + (q31_t)0x6bb14892, (q31_t)0x6ba3b0f7, (q31_t)0x6b961536, (q31_t)0x6b88754f, (q31_t)0x6b7ad142, (q31_t)0x6b6d2911, + (q31_t)0x6b5f7cbc, (q31_t)0x6b51cc42, + (q31_t)0x6b4417a6, (q31_t)0x6b365ee7, (q31_t)0x6b28a206, (q31_t)0x6b1ae103, (q31_t)0x6b0d1bdf, (q31_t)0x6aff529a, + (q31_t)0x6af18536, (q31_t)0x6ae3b3b2, + (q31_t)0x6ad5de0f, (q31_t)0x6ac8044e, (q31_t)0x6aba266e, (q31_t)0x6aac4472, (q31_t)0x6a9e5e58, (q31_t)0x6a907423, + (q31_t)0x6a8285d1, (q31_t)0x6a749365, + (q31_t)0x6a669cdd, (q31_t)0x6a58a23c, (q31_t)0x6a4aa381, (q31_t)0x6a3ca0ad, (q31_t)0x6a2e99c0, (q31_t)0x6a208ebb, + (q31_t)0x6a127f9f, (q31_t)0x6a046c6c, + (q31_t)0x69f65523, (q31_t)0x69e839c4, (q31_t)0x69da1a50, (q31_t)0x69cbf6c7, (q31_t)0x69bdcf29, (q31_t)0x69afa378, + (q31_t)0x69a173b5, (q31_t)0x69933fde, + (q31_t)0x698507f6, (q31_t)0x6976cbfc, (q31_t)0x69688bf1, (q31_t)0x695a47d6, (q31_t)0x694bffab, (q31_t)0x693db371, + (q31_t)0x692f6328, (q31_t)0x69210ed1, + (q31_t)0x6912b66c, (q31_t)0x690459fb, (q31_t)0x68f5f97d, (q31_t)0x68e794f3, (q31_t)0x68d92c5d, (q31_t)0x68cabfbd, + (q31_t)0x68bc4f13, (q31_t)0x68adda5f, + (q31_t)0x689f61a1, (q31_t)0x6890e4dc, (q31_t)0x6882640e, (q31_t)0x6873df38, (q31_t)0x6865565c, (q31_t)0x6856c979, + (q31_t)0x68483891, (q31_t)0x6839a3a4, + (q31_t)0x682b0ab1, (q31_t)0x681c6dbb, (q31_t)0x680dccc1, (q31_t)0x67ff27c4, (q31_t)0x67f07ec5, (q31_t)0x67e1d1c4, + (q31_t)0x67d320c1, (q31_t)0x67c46bbe, + (q31_t)0x67b5b2bb, (q31_t)0x67a6f5b8, (q31_t)0x679834b6, (q31_t)0x67896fb6, (q31_t)0x677aa6b8, (q31_t)0x676bd9bd, + (q31_t)0x675d08c4, (q31_t)0x674e33d0, + (q31_t)0x673f5ae0, (q31_t)0x67307df5, (q31_t)0x67219d10, (q31_t)0x6712b831, (q31_t)0x6703cf58, (q31_t)0x66f4e287, + (q31_t)0x66e5f1be, (q31_t)0x66d6fcfd, + (q31_t)0x66c80445, (q31_t)0x66b90797, (q31_t)0x66aa06f3, (q31_t)0x669b0259, (q31_t)0x668bf9cb, (q31_t)0x667ced49, + (q31_t)0x666ddcd3, (q31_t)0x665ec86b, + (q31_t)0x664fb010, (q31_t)0x664093c3, (q31_t)0x66317385, (q31_t)0x66224f56, (q31_t)0x66132738, (q31_t)0x6603fb2a, + (q31_t)0x65f4cb2d, (q31_t)0x65e59742, + (q31_t)0x65d65f69, (q31_t)0x65c723a3, (q31_t)0x65b7e3f1, (q31_t)0x65a8a052, (q31_t)0x659958c9, (q31_t)0x658a0d54, + (q31_t)0x657abdf6, (q31_t)0x656b6aae, + (q31_t)0x655c137d, (q31_t)0x654cb863, (q31_t)0x653d5962, (q31_t)0x652df679, (q31_t)0x651e8faa, (q31_t)0x650f24f5, + (q31_t)0x64ffb65b, (q31_t)0x64f043dc, + (q31_t)0x64e0cd78, (q31_t)0x64d15331, (q31_t)0x64c1d507, (q31_t)0x64b252fa, (q31_t)0x64a2cd0c, (q31_t)0x6493433c, + (q31_t)0x6483b58c, (q31_t)0x647423fb, + (q31_t)0x64648e8c, (q31_t)0x6454f53d, (q31_t)0x64455810, (q31_t)0x6435b706, (q31_t)0x6426121e, (q31_t)0x6416695a, + (q31_t)0x6406bcba, (q31_t)0x63f70c3f, + (q31_t)0x63e757ea, (q31_t)0x63d79fba, (q31_t)0x63c7e3b1, (q31_t)0x63b823cf, (q31_t)0x63a86015, (q31_t)0x63989884, + (q31_t)0x6388cd1b, (q31_t)0x6378fddc, + (q31_t)0x63692ac7, (q31_t)0x635953dd, (q31_t)0x6349791f, (q31_t)0x63399a8d, (q31_t)0x6329b827, (q31_t)0x6319d1ef, + (q31_t)0x6309e7e4, (q31_t)0x62f9fa09, + (q31_t)0x62ea085c, (q31_t)0x62da12df, (q31_t)0x62ca1992, (q31_t)0x62ba1c77, (q31_t)0x62aa1b8d, (q31_t)0x629a16d5, + (q31_t)0x628a0e50, (q31_t)0x627a01fe, + (q31_t)0x6269f1e1, (q31_t)0x6259ddf8, (q31_t)0x6249c645, (q31_t)0x6239aac7, (q31_t)0x62298b81, (q31_t)0x62196871, + (q31_t)0x62094199, (q31_t)0x61f916f9, + (q31_t)0x61e8e893, (q31_t)0x61d8b666, (q31_t)0x61c88074, (q31_t)0x61b846bc, (q31_t)0x61a80940, (q31_t)0x6197c800, + (q31_t)0x618782fd, (q31_t)0x61773a37, + (q31_t)0x6166edb0, (q31_t)0x61569d67, (q31_t)0x6146495d, (q31_t)0x6135f193, (q31_t)0x6125960a, (q31_t)0x611536c2, + (q31_t)0x6104d3bc, (q31_t)0x60f46cf9, + (q31_t)0x60e40278, (q31_t)0x60d3943b, (q31_t)0x60c32243, (q31_t)0x60b2ac8f, (q31_t)0x60a23322, (q31_t)0x6091b5fa, + (q31_t)0x60813519, (q31_t)0x6070b080, + (q31_t)0x6060282f, (q31_t)0x604f9c27, (q31_t)0x603f0c69, (q31_t)0x602e78f4, (q31_t)0x601de1ca, (q31_t)0x600d46ec, + (q31_t)0x5ffca859, (q31_t)0x5fec0613, + (q31_t)0x5fdb601b, (q31_t)0x5fcab670, (q31_t)0x5fba0914, (q31_t)0x5fa95807, (q31_t)0x5f98a34a, (q31_t)0x5f87eade, + (q31_t)0x5f772ec2, (q31_t)0x5f666ef9, + (q31_t)0x5f55ab82, (q31_t)0x5f44e45e, (q31_t)0x5f34198e, (q31_t)0x5f234b12, (q31_t)0x5f1278eb, (q31_t)0x5f01a31a, + (q31_t)0x5ef0c99f, (q31_t)0x5edfec7b, + (q31_t)0x5ecf0baf, (q31_t)0x5ebe273b, (q31_t)0x5ead3f1f, (q31_t)0x5e9c535e, (q31_t)0x5e8b63f7, (q31_t)0x5e7a70ea, + (q31_t)0x5e697a39, (q31_t)0x5e587fe5, + (q31_t)0x5e4781ed, (q31_t)0x5e368053, (q31_t)0x5e257b17, (q31_t)0x5e147239, (q31_t)0x5e0365bb, (q31_t)0x5df2559e, + (q31_t)0x5de141e1, (q31_t)0x5dd02a85, + (q31_t)0x5dbf0f8c, (q31_t)0x5dadf0f5, (q31_t)0x5d9ccec2, (q31_t)0x5d8ba8f3, (q31_t)0x5d7a7f88, (q31_t)0x5d695283, + (q31_t)0x5d5821e4, (q31_t)0x5d46edac, + (q31_t)0x5d35b5db, (q31_t)0x5d247a72, (q31_t)0x5d133b72, (q31_t)0x5d01f8dc, (q31_t)0x5cf0b2af, (q31_t)0x5cdf68ed, + (q31_t)0x5cce1b97, (q31_t)0x5cbccaac, + (q31_t)0x5cab762f, (q31_t)0x5c9a1e1e, (q31_t)0x5c88c27c, (q31_t)0x5c776348, (q31_t)0x5c660084, (q31_t)0x5c549a30, + (q31_t)0x5c43304d, (q31_t)0x5c31c2db, + (q31_t)0x5c2051db, (q31_t)0x5c0edd4e, (q31_t)0x5bfd6534, (q31_t)0x5bebe98e, (q31_t)0x5bda6a5d, (q31_t)0x5bc8e7a2, + (q31_t)0x5bb7615d, (q31_t)0x5ba5d78e, + (q31_t)0x5b944a37, (q31_t)0x5b82b958, (q31_t)0x5b7124f2, (q31_t)0x5b5f8d06, (q31_t)0x5b4df193, (q31_t)0x5b3c529c, + (q31_t)0x5b2ab020, (q31_t)0x5b190a20, + (q31_t)0x5b07609d, (q31_t)0x5af5b398, (q31_t)0x5ae40311, (q31_t)0x5ad24f09, (q31_t)0x5ac09781, (q31_t)0x5aaedc78, + (q31_t)0x5a9d1df1, (q31_t)0x5a8b5bec, + (q31_t)0x5a799669, (q31_t)0x5a67cd69, (q31_t)0x5a5600ec, (q31_t)0x5a4430f5, (q31_t)0x5a325d82, (q31_t)0x5a208695, + (q31_t)0x5a0eac2e, (q31_t)0x59fcce4f, + (q31_t)0x59eaecf8, (q31_t)0x59d90829, (q31_t)0x59c71fe3, (q31_t)0x59b53427, (q31_t)0x59a344f6, (q31_t)0x59915250, + (q31_t)0x597f5c36, (q31_t)0x596d62a9, + (q31_t)0x595b65aa, (q31_t)0x59496538, (q31_t)0x59376155, (q31_t)0x59255a02, (q31_t)0x59134f3e, (q31_t)0x5901410c, + (q31_t)0x58ef2f6b, (q31_t)0x58dd1a5d, + (q31_t)0x58cb01e1, (q31_t)0x58b8e5f9, (q31_t)0x58a6c6a5, (q31_t)0x5894a3e7, (q31_t)0x58827dbe, (q31_t)0x5870542c, + (q31_t)0x585e2730, (q31_t)0x584bf6cd, + (q31_t)0x5839c302, (q31_t)0x58278bd1, (q31_t)0x58155139, (q31_t)0x5803133c, (q31_t)0x57f0d1da, (q31_t)0x57de8d15, + (q31_t)0x57cc44ec, (q31_t)0x57b9f960, + (q31_t)0x57a7aa73, (q31_t)0x57955825, (q31_t)0x57830276, (q31_t)0x5770a968, (q31_t)0x575e4cfa, (q31_t)0x574bed2f, + (q31_t)0x57398a05, (q31_t)0x5727237f, + (q31_t)0x5714b99d, (q31_t)0x57024c5f, (q31_t)0x56efdbc7, (q31_t)0x56dd67d4, (q31_t)0x56caf088, (q31_t)0x56b875e4, + (q31_t)0x56a5f7e7, (q31_t)0x56937694, + (q31_t)0x5680f1ea, (q31_t)0x566e69ea, (q31_t)0x565bde95, (q31_t)0x56494fec, (q31_t)0x5636bdef, (q31_t)0x5624289f, + (q31_t)0x56118ffe, (q31_t)0x55fef40a, + (q31_t)0x55ec54c6, (q31_t)0x55d9b232, (q31_t)0x55c70c4f, (q31_t)0x55b4631d, (q31_t)0x55a1b69d, (q31_t)0x558f06d0, + (q31_t)0x557c53b6, (q31_t)0x55699d51, + (q31_t)0x5556e3a1, (q31_t)0x554426a7, (q31_t)0x55316663, (q31_t)0x551ea2d6, (q31_t)0x550bdc01, (q31_t)0x54f911e5, + (q31_t)0x54e64482, (q31_t)0x54d373d9, + (q31_t)0x54c09feb, (q31_t)0x54adc8b8, (q31_t)0x549aee42, (q31_t)0x54881089, (q31_t)0x54752f8d, (q31_t)0x54624b50, + (q31_t)0x544f63d2, (q31_t)0x543c7914, + (q31_t)0x54298b17, (q31_t)0x541699db, (q31_t)0x5403a561, (q31_t)0x53f0adaa, (q31_t)0x53ddb2b6, (q31_t)0x53cab486, + (q31_t)0x53b7b31c, (q31_t)0x53a4ae77, + (q31_t)0x5391a699, (q31_t)0x537e9b82, (q31_t)0x536b8d33, (q31_t)0x53587bad, (q31_t)0x534566f0, (q31_t)0x53324efd, + (q31_t)0x531f33d5, (q31_t)0x530c1579, + (q31_t)0x52f8f3e9, (q31_t)0x52e5cf27, (q31_t)0x52d2a732, (q31_t)0x52bf7c0b, (q31_t)0x52ac4db4, (q31_t)0x52991c2d, + (q31_t)0x5285e777, (q31_t)0x5272af92, + (q31_t)0x525f7480, (q31_t)0x524c3640, (q31_t)0x5238f4d4, (q31_t)0x5225b03d, (q31_t)0x5212687b, (q31_t)0x51ff1d8f, + (q31_t)0x51ebcf7a, (q31_t)0x51d87e3c, + (q31_t)0x51c529d7, (q31_t)0x51b1d24a, (q31_t)0x519e7797, (q31_t)0x518b19bf, (q31_t)0x5177b8c2, (q31_t)0x516454a0, + (q31_t)0x5150ed5c, (q31_t)0x513d82f4, + (q31_t)0x512a156b, (q31_t)0x5116a4c1, (q31_t)0x510330f7, (q31_t)0x50efba0d, (q31_t)0x50dc4005, (q31_t)0x50c8c2de, + (q31_t)0x50b5429a, (q31_t)0x50a1bf39, + (q31_t)0x508e38bd, (q31_t)0x507aaf25, (q31_t)0x50672273, (q31_t)0x505392a8, (q31_t)0x503fffc4, (q31_t)0x502c69c8, + (q31_t)0x5018d0b4, (q31_t)0x5005348a, + (q31_t)0x4ff1954b, (q31_t)0x4fddf2f6, (q31_t)0x4fca4d8d, (q31_t)0x4fb6a510, (q31_t)0x4fa2f981, (q31_t)0x4f8f4ae0, + (q31_t)0x4f7b992d, (q31_t)0x4f67e46a, + (q31_t)0x4f542c98, (q31_t)0x4f4071b6, (q31_t)0x4f2cb3c7, (q31_t)0x4f18f2c9, (q31_t)0x4f052ec0, (q31_t)0x4ef167aa, + (q31_t)0x4edd9d89, (q31_t)0x4ec9d05e, + (q31_t)0x4eb60029, (q31_t)0x4ea22ceb, (q31_t)0x4e8e56a5, (q31_t)0x4e7a7d58, (q31_t)0x4e66a105, (q31_t)0x4e52c1ab, + (q31_t)0x4e3edf4d, (q31_t)0x4e2af9ea, + (q31_t)0x4e171184, (q31_t)0x4e03261b, (q31_t)0x4def37b0, (q31_t)0x4ddb4644, (q31_t)0x4dc751d8, (q31_t)0x4db35a6c, + (q31_t)0x4d9f6001, (q31_t)0x4d8b6298, + (q31_t)0x4d776231, (q31_t)0x4d635ece, (q31_t)0x4d4f5870, (q31_t)0x4d3b4f16, (q31_t)0x4d2742c2, (q31_t)0x4d133374, + (q31_t)0x4cff212e, (q31_t)0x4ceb0bf0, + (q31_t)0x4cd6f3bb, (q31_t)0x4cc2d88f, (q31_t)0x4caeba6e, (q31_t)0x4c9a9958, (q31_t)0x4c86754e, (q31_t)0x4c724e50, + (q31_t)0x4c5e2460, (q31_t)0x4c49f77f, + (q31_t)0x4c35c7ac, (q31_t)0x4c2194e9, (q31_t)0x4c0d5f37, (q31_t)0x4bf92697, (q31_t)0x4be4eb08, (q31_t)0x4bd0ac8d, + (q31_t)0x4bbc6b25, (q31_t)0x4ba826d1, + (q31_t)0x4b93df93, (q31_t)0x4b7f956b, (q31_t)0x4b6b485a, (q31_t)0x4b56f861, (q31_t)0x4b42a580, (q31_t)0x4b2e4fb8, + (q31_t)0x4b19f70a, (q31_t)0x4b059b77, + (q31_t)0x4af13d00, (q31_t)0x4adcdba5, (q31_t)0x4ac87767, (q31_t)0x4ab41046, (q31_t)0x4a9fa645, (q31_t)0x4a8b3963, + (q31_t)0x4a76c9a2, (q31_t)0x4a625701, + (q31_t)0x4a4de182, (q31_t)0x4a396926, (q31_t)0x4a24edee, (q31_t)0x4a106fda, (q31_t)0x49fbeeea, (q31_t)0x49e76b21, + (q31_t)0x49d2e47e, (q31_t)0x49be5b02, + (q31_t)0x49a9ceaf, (q31_t)0x49953f84, (q31_t)0x4980ad84, (q31_t)0x496c18ae, (q31_t)0x49578103, (q31_t)0x4942e684, + (q31_t)0x492e4933, (q31_t)0x4919a90f, + (q31_t)0x4905061a, (q31_t)0x48f06054, (q31_t)0x48dbb7be, (q31_t)0x48c70c59, (q31_t)0x48b25e25, (q31_t)0x489dad25, + (q31_t)0x4888f957, (q31_t)0x487442be, + (q31_t)0x485f8959, (q31_t)0x484acd2a, (q31_t)0x48360e32, (q31_t)0x48214c71, (q31_t)0x480c87e8, (q31_t)0x47f7c099, + (q31_t)0x47e2f682, (q31_t)0x47ce29a7, + (q31_t)0x47b95a06, (q31_t)0x47a487a2, (q31_t)0x478fb27b, (q31_t)0x477ada91, (q31_t)0x4765ffe6, (q31_t)0x4751227a, + (q31_t)0x473c424e, (q31_t)0x47275f63, + (q31_t)0x471279ba, (q31_t)0x46fd9154, (q31_t)0x46e8a631, (q31_t)0x46d3b852, (q31_t)0x46bec7b8, (q31_t)0x46a9d464, + (q31_t)0x4694de56, (q31_t)0x467fe590, + (q31_t)0x466aea12, (q31_t)0x4655ebdd, (q31_t)0x4640eaf2, (q31_t)0x462be751, (q31_t)0x4616e0fc, (q31_t)0x4601d7f3, + (q31_t)0x45eccc37, (q31_t)0x45d7bdc9, + (q31_t)0x45c2acaa, (q31_t)0x45ad98da, (q31_t)0x4598825a, (q31_t)0x4583692c, (q31_t)0x456e4d4f, (q31_t)0x45592ec6, + (q31_t)0x45440d90, (q31_t)0x452ee9ae, + (q31_t)0x4519c321, (q31_t)0x450499eb, (q31_t)0x44ef6e0b, (q31_t)0x44da3f83, (q31_t)0x44c50e53, (q31_t)0x44afda7d, + (q31_t)0x449aa400, (q31_t)0x44856adf, + (q31_t)0x44702f19, (q31_t)0x445af0b0, (q31_t)0x4445afa4, (q31_t)0x44306bf6, (q31_t)0x441b25a8, (q31_t)0x4405dcb9, + (q31_t)0x43f0912b, (q31_t)0x43db42fe, + (q31_t)0x43c5f234, (q31_t)0x43b09ecc, (q31_t)0x439b48c9, (q31_t)0x4385f02a, (q31_t)0x437094f1, (q31_t)0x435b371f, + (q31_t)0x4345d6b3, (q31_t)0x433073b0, + (q31_t)0x431b0e15, (q31_t)0x4305a5e5, (q31_t)0x42f03b1e, (q31_t)0x42dacdc3, (q31_t)0x42c55dd4, (q31_t)0x42afeb53, + (q31_t)0x429a763f, (q31_t)0x4284fe99, + (q31_t)0x426f8463, (q31_t)0x425a079e, (q31_t)0x42448849, (q31_t)0x422f0667, (q31_t)0x421981f7, (q31_t)0x4203fafb, + (q31_t)0x41ee7174, (q31_t)0x41d8e561, + (q31_t)0x41c356c5, (q31_t)0x41adc5a0, (q31_t)0x419831f3, (q31_t)0x41829bbe, (q31_t)0x416d0302, (q31_t)0x415767c1, + (q31_t)0x4141c9fb, (q31_t)0x412c29b1, + (q31_t)0x411686e4, (q31_t)0x4100e194, (q31_t)0x40eb39c3, (q31_t)0x40d58f71, (q31_t)0x40bfe29f, (q31_t)0x40aa334e, + (q31_t)0x4094817f, (q31_t)0x407ecd32, + (q31_t)0x40691669, (q31_t)0x40535d24, (q31_t)0x403da165, (q31_t)0x4027e32b, (q31_t)0x40122278, (q31_t)0x3ffc5f4d, + (q31_t)0x3fe699aa, (q31_t)0x3fd0d191, + (q31_t)0x3fbb0702, (q31_t)0x3fa539fd, (q31_t)0x3f8f6a85, (q31_t)0x3f799899, (q31_t)0x3f63c43b, (q31_t)0x3f4ded6b, + (q31_t)0x3f38142a, (q31_t)0x3f22387a, + (q31_t)0x3f0c5a5a, (q31_t)0x3ef679cc, (q31_t)0x3ee096d1, (q31_t)0x3ecab169, (q31_t)0x3eb4c995, (q31_t)0x3e9edf57, + (q31_t)0x3e88f2ae, (q31_t)0x3e73039d, + (q31_t)0x3e5d1222, (q31_t)0x3e471e41, (q31_t)0x3e3127f9, (q31_t)0x3e1b2f4a, (q31_t)0x3e053437, (q31_t)0x3def36c0, + (q31_t)0x3dd936e6, (q31_t)0x3dc334a9, + (q31_t)0x3dad300b, (q31_t)0x3d97290b, (q31_t)0x3d811fac, (q31_t)0x3d6b13ee, (q31_t)0x3d5505d2, (q31_t)0x3d3ef559, + (q31_t)0x3d28e282, (q31_t)0x3d12cd51, + (q31_t)0x3cfcb5c4, (q31_t)0x3ce69bde, (q31_t)0x3cd07f9f, (q31_t)0x3cba6107, (q31_t)0x3ca44018, (q31_t)0x3c8e1cd3, + (q31_t)0x3c77f737, (q31_t)0x3c61cf48, + (q31_t)0x3c4ba504, (q31_t)0x3c35786d, (q31_t)0x3c1f4983, (q31_t)0x3c091849, (q31_t)0x3bf2e4be, (q31_t)0x3bdcaee3, + (q31_t)0x3bc676b9, (q31_t)0x3bb03c42, + (q31_t)0x3b99ff7d, (q31_t)0x3b83c06c, (q31_t)0x3b6d7f10, (q31_t)0x3b573b69, (q31_t)0x3b40f579, (q31_t)0x3b2aad3f, + (q31_t)0x3b1462be, (q31_t)0x3afe15f6, + (q31_t)0x3ae7c6e7, (q31_t)0x3ad17593, (q31_t)0x3abb21fb, (q31_t)0x3aa4cc1e, (q31_t)0x3a8e7400, (q31_t)0x3a78199f, + (q31_t)0x3a61bcfd, (q31_t)0x3a4b5e1b, + (q31_t)0x3a34fcf9, (q31_t)0x3a1e9999, (q31_t)0x3a0833fc, (q31_t)0x39f1cc21, (q31_t)0x39db620b, (q31_t)0x39c4f5ba, + (q31_t)0x39ae872f, (q31_t)0x3998166a, + (q31_t)0x3981a36d, (q31_t)0x396b2e38, (q31_t)0x3954b6cd, (q31_t)0x393e3d2c, (q31_t)0x3927c155, (q31_t)0x3911434b, + (q31_t)0x38fac30e, (q31_t)0x38e4409e, + (q31_t)0x38cdbbfc, (q31_t)0x38b7352a, (q31_t)0x38a0ac29, (q31_t)0x388a20f8, (q31_t)0x38739399, (q31_t)0x385d040d, + (q31_t)0x38467255, (q31_t)0x382fde72, + (q31_t)0x38194864, (q31_t)0x3802b02c, (q31_t)0x37ec15cb, (q31_t)0x37d57943, (q31_t)0x37beda93, (q31_t)0x37a839be, + (q31_t)0x379196c3, (q31_t)0x377af1a3, + (q31_t)0x37644a60, (q31_t)0x374da0fa, (q31_t)0x3736f573, (q31_t)0x372047ca, (q31_t)0x37099802, (q31_t)0x36f2e61a, + (q31_t)0x36dc3214, (q31_t)0x36c57bf0, + (q31_t)0x36aec3b0, (q31_t)0x36980954, (q31_t)0x36814cde, (q31_t)0x366a8e4d, (q31_t)0x3653cda3, (q31_t)0x363d0ae2, + (q31_t)0x36264609, (q31_t)0x360f7f19, + (q31_t)0x35f8b614, (q31_t)0x35e1eafa, (q31_t)0x35cb1dcc, (q31_t)0x35b44e8c, (q31_t)0x359d7d39, (q31_t)0x3586a9d5, + (q31_t)0x356fd461, (q31_t)0x3558fcde, + (q31_t)0x3542234c, (q31_t)0x352b47ad, (q31_t)0x35146a00, (q31_t)0x34fd8a48, (q31_t)0x34e6a885, (q31_t)0x34cfc4b7, + (q31_t)0x34b8dee1, (q31_t)0x34a1f702, + (q31_t)0x348b0d1c, (q31_t)0x3474212f, (q31_t)0x345d333c, (q31_t)0x34464345, (q31_t)0x342f5149, (q31_t)0x34185d4b, + (q31_t)0x3401674a, (q31_t)0x33ea6f48, + (q31_t)0x33d37546, (q31_t)0x33bc7944, (q31_t)0x33a57b44, (q31_t)0x338e7b46, (q31_t)0x3377794b, (q31_t)0x33607554, + (q31_t)0x33496f62, (q31_t)0x33326776, + (q31_t)0x331b5d91, (q31_t)0x330451b3, (q31_t)0x32ed43de, (q31_t)0x32d63412, (q31_t)0x32bf2250, (q31_t)0x32a80e99, + (q31_t)0x3290f8ef, (q31_t)0x3279e151, + (q31_t)0x3262c7c1, (q31_t)0x324bac40, (q31_t)0x32348ecf, (q31_t)0x321d6f6e, (q31_t)0x32064e1e, (q31_t)0x31ef2ae1, + (q31_t)0x31d805b7, (q31_t)0x31c0dea1, + (q31_t)0x31a9b5a0, (q31_t)0x31928ab4, (q31_t)0x317b5de0, (q31_t)0x31642f23, (q31_t)0x314cfe7f, (q31_t)0x3135cbf4, + (q31_t)0x311e9783, (q31_t)0x3107612e, + (q31_t)0x30f028f4, (q31_t)0x30d8eed8, (q31_t)0x30c1b2da, (q31_t)0x30aa74fa, (q31_t)0x3093353a, (q31_t)0x307bf39b, + (q31_t)0x3064b01d, (q31_t)0x304d6ac1, + (q31_t)0x30362389, (q31_t)0x301eda75, (q31_t)0x30078f86, (q31_t)0x2ff042bd, (q31_t)0x2fd8f41b, (q31_t)0x2fc1a3a0, + (q31_t)0x2faa514f, (q31_t)0x2f92fd26, + (q31_t)0x2f7ba729, (q31_t)0x2f644f56, (q31_t)0x2f4cf5b0, (q31_t)0x2f359a37, (q31_t)0x2f1e3ced, (q31_t)0x2f06ddd1, + (q31_t)0x2eef7ce5, (q31_t)0x2ed81a29, + (q31_t)0x2ec0b5a0, (q31_t)0x2ea94f49, (q31_t)0x2e91e725, (q31_t)0x2e7a7d36, (q31_t)0x2e63117c, (q31_t)0x2e4ba3f8, + (q31_t)0x2e3434ac, (q31_t)0x2e1cc397, + (q31_t)0x2e0550bb, (q31_t)0x2deddc19, (q31_t)0x2dd665b2, (q31_t)0x2dbeed86, (q31_t)0x2da77397, (q31_t)0x2d8ff7e5, + (q31_t)0x2d787a72, (q31_t)0x2d60fb3e, + (q31_t)0x2d497a4a, (q31_t)0x2d31f797, (q31_t)0x2d1a7325, (q31_t)0x2d02ecf7, (q31_t)0x2ceb650d, (q31_t)0x2cd3db67, + (q31_t)0x2cbc5006, (q31_t)0x2ca4c2ed, + (q31_t)0x2c8d341a, (q31_t)0x2c75a390, (q31_t)0x2c5e114f, (q31_t)0x2c467d58, (q31_t)0x2c2ee7ad, (q31_t)0x2c17504d, + (q31_t)0x2bffb73a, (q31_t)0x2be81c74, + (q31_t)0x2bd07ffe, (q31_t)0x2bb8e1d7, (q31_t)0x2ba14200, (q31_t)0x2b89a07b, (q31_t)0x2b71fd48, (q31_t)0x2b5a5868, + (q31_t)0x2b42b1dd, (q31_t)0x2b2b09a6, + (q31_t)0x2b135fc6, (q31_t)0x2afbb43c, (q31_t)0x2ae4070a, (q31_t)0x2acc5831, (q31_t)0x2ab4a7b1, (q31_t)0x2a9cf58c, + (q31_t)0x2a8541c3, (q31_t)0x2a6d8c55, + (q31_t)0x2a55d545, (q31_t)0x2a3e1c93, (q31_t)0x2a266240, (q31_t)0x2a0ea64d, (q31_t)0x29f6e8bb, (q31_t)0x29df298b, + (q31_t)0x29c768be, (q31_t)0x29afa654, + (q31_t)0x2997e24f, (q31_t)0x29801caf, (q31_t)0x29685576, (q31_t)0x29508ca4, (q31_t)0x2938c23a, (q31_t)0x2920f63a, + (q31_t)0x290928a3, (q31_t)0x28f15978, + (q31_t)0x28d988b8, (q31_t)0x28c1b666, (q31_t)0x28a9e281, (q31_t)0x28920d0a, (q31_t)0x287a3604, (q31_t)0x28625d6d, + (q31_t)0x284a8349, (q31_t)0x2832a796, + (q31_t)0x281aca57, (q31_t)0x2802eb8c, (q31_t)0x27eb0b36, (q31_t)0x27d32956, (q31_t)0x27bb45ed, (q31_t)0x27a360fc, + (q31_t)0x278b7a84, (q31_t)0x27739285, + (q31_t)0x275ba901, (q31_t)0x2743bdf9, (q31_t)0x272bd16d, (q31_t)0x2713e35f, (q31_t)0x26fbf3ce, (q31_t)0x26e402bd, + (q31_t)0x26cc102d, (q31_t)0x26b41c1d, + (q31_t)0x269c268f, (q31_t)0x26842f84, (q31_t)0x266c36fe, (q31_t)0x26543cfb, (q31_t)0x263c417f, (q31_t)0x26244489, + (q31_t)0x260c461b, (q31_t)0x25f44635, + (q31_t)0x25dc44d9, (q31_t)0x25c44207, (q31_t)0x25ac3dc0, (q31_t)0x25943806, (q31_t)0x257c30d8, (q31_t)0x25642839, + (q31_t)0x254c1e28, (q31_t)0x253412a8, + (q31_t)0x251c05b8, (q31_t)0x2503f75a, (q31_t)0x24ebe78f, (q31_t)0x24d3d657, (q31_t)0x24bbc3b4, (q31_t)0x24a3afa6, + (q31_t)0x248b9a2f, (q31_t)0x2473834f, + (q31_t)0x245b6b07, (q31_t)0x24435158, (q31_t)0x242b3644, (q31_t)0x241319ca, (q31_t)0x23fafbec, (q31_t)0x23e2dcac, + (q31_t)0x23cabc09, (q31_t)0x23b29a05, + (q31_t)0x239a76a0, (q31_t)0x238251dd, (q31_t)0x236a2bba, (q31_t)0x2352043b, (q31_t)0x2339db5e, (q31_t)0x2321b126, + (q31_t)0x23098593, (q31_t)0x22f158a7, + (q31_t)0x22d92a61, (q31_t)0x22c0fac4, (q31_t)0x22a8c9cf, (q31_t)0x22909785, (q31_t)0x227863e5, (q31_t)0x22602ef1, + (q31_t)0x2247f8aa, (q31_t)0x222fc111, + (q31_t)0x22178826, (q31_t)0x21ff4dea, (q31_t)0x21e71260, (q31_t)0x21ced586, (q31_t)0x21b6975f, (q31_t)0x219e57eb, + (q31_t)0x2186172b, (q31_t)0x216dd521, + (q31_t)0x215591cc, (q31_t)0x213d4d2f, (q31_t)0x21250749, (q31_t)0x210cc01d, (q31_t)0x20f477aa, (q31_t)0x20dc2df2, + (q31_t)0x20c3e2f5, (q31_t)0x20ab96b5, + (q31_t)0x20934933, (q31_t)0x207afa6f, (q31_t)0x2062aa6b, (q31_t)0x204a5927, (q31_t)0x203206a4, (q31_t)0x2019b2e4, + (q31_t)0x20015de7, (q31_t)0x1fe907ae, + (q31_t)0x1fd0b03a, (q31_t)0x1fb8578b, (q31_t)0x1f9ffda4, (q31_t)0x1f87a285, (q31_t)0x1f6f462f, (q31_t)0x1f56e8a2, + (q31_t)0x1f3e89e0, (q31_t)0x1f2629ea, + (q31_t)0x1f0dc8c0, (q31_t)0x1ef56664, (q31_t)0x1edd02d6, (q31_t)0x1ec49e17, (q31_t)0x1eac3829, (q31_t)0x1e93d10c, + (q31_t)0x1e7b68c2, (q31_t)0x1e62ff4a, + (q31_t)0x1e4a94a7, (q31_t)0x1e3228d9, (q31_t)0x1e19bbe0, (q31_t)0x1e014dbf, (q31_t)0x1de8de75, (q31_t)0x1dd06e04, + (q31_t)0x1db7fc6d, (q31_t)0x1d9f89b1, + (q31_t)0x1d8715d0, (q31_t)0x1d6ea0cc, (q31_t)0x1d562aa6, (q31_t)0x1d3db35e, (q31_t)0x1d253af5, (q31_t)0x1d0cc16c, + (q31_t)0x1cf446c5, (q31_t)0x1cdbcb00, + (q31_t)0x1cc34e1f, (q31_t)0x1caad021, (q31_t)0x1c925109, (q31_t)0x1c79d0d6, (q31_t)0x1c614f8b, (q31_t)0x1c48cd27, + (q31_t)0x1c3049ac, (q31_t)0x1c17c51b, + (q31_t)0x1bff3f75, (q31_t)0x1be6b8ba, (q31_t)0x1bce30ec, (q31_t)0x1bb5a80c, (q31_t)0x1b9d1e1a, (q31_t)0x1b849317, + (q31_t)0x1b6c0705, (q31_t)0x1b5379e5, + (q31_t)0x1b3aebb6, (q31_t)0x1b225c7b, (q31_t)0x1b09cc34, (q31_t)0x1af13ae3, (q31_t)0x1ad8a887, (q31_t)0x1ac01522, + (q31_t)0x1aa780b6, (q31_t)0x1a8eeb42, + (q31_t)0x1a7654c8, (q31_t)0x1a5dbd49, (q31_t)0x1a4524c6, (q31_t)0x1a2c8b3f, (q31_t)0x1a13f0b6, (q31_t)0x19fb552c, + (q31_t)0x19e2b8a2, (q31_t)0x19ca1b17, + (q31_t)0x19b17c8f, (q31_t)0x1998dd09, (q31_t)0x19803c86, (q31_t)0x19679b07, (q31_t)0x194ef88e, (q31_t)0x1936551b, + (q31_t)0x191db0af, (q31_t)0x19050b4b, + (q31_t)0x18ec64f0, (q31_t)0x18d3bda0, (q31_t)0x18bb155a, (q31_t)0x18a26c20, (q31_t)0x1889c1f3, (q31_t)0x187116d4, + (q31_t)0x18586ac3, (q31_t)0x183fbdc3, + (q31_t)0x18270fd3, (q31_t)0x180e60f4, (q31_t)0x17f5b129, (q31_t)0x17dd0070, (q31_t)0x17c44ecd, (q31_t)0x17ab9c3e, + (q31_t)0x1792e8c6, (q31_t)0x177a3466, + (q31_t)0x17617f1d, (q31_t)0x1748c8ee, (q31_t)0x173011d9, (q31_t)0x171759df, (q31_t)0x16fea102, (q31_t)0x16e5e741, + (q31_t)0x16cd2c9f, (q31_t)0x16b4711b, + (q31_t)0x169bb4b7, (q31_t)0x1682f774, (q31_t)0x166a3953, (q31_t)0x16517a55, (q31_t)0x1638ba7a, (q31_t)0x161ff9c4, + (q31_t)0x16073834, (q31_t)0x15ee75cb, + (q31_t)0x15d5b288, (q31_t)0x15bcee6f, (q31_t)0x15a4297f, (q31_t)0x158b63b9, (q31_t)0x15729d1f, (q31_t)0x1559d5b1, + (q31_t)0x15410d70, (q31_t)0x1528445d, + (q31_t)0x150f7a7a, (q31_t)0x14f6afc7, (q31_t)0x14dde445, (q31_t)0x14c517f4, (q31_t)0x14ac4ad7, (q31_t)0x14937cee, + (q31_t)0x147aae3a, (q31_t)0x1461debc, + (q31_t)0x14490e74, (q31_t)0x14303d65, (q31_t)0x14176b8e, (q31_t)0x13fe98f1, (q31_t)0x13e5c58e, (q31_t)0x13ccf167, + (q31_t)0x13b41c7d, (q31_t)0x139b46d0, + (q31_t)0x13827062, (q31_t)0x13699933, (q31_t)0x1350c144, (q31_t)0x1337e897, (q31_t)0x131f0f2c, (q31_t)0x13063505, + (q31_t)0x12ed5a21, (q31_t)0x12d47e83, + (q31_t)0x12bba22b, (q31_t)0x12a2c51b, (q31_t)0x1289e752, (q31_t)0x127108d2, (q31_t)0x1258299c, (q31_t)0x123f49b2, + (q31_t)0x12266913, (q31_t)0x120d87c1, + (q31_t)0x11f4a5bd, (q31_t)0x11dbc307, (q31_t)0x11c2dfa2, (q31_t)0x11a9fb8d, (q31_t)0x119116c9, (q31_t)0x11783159, + (q31_t)0x115f4b3c, (q31_t)0x11466473, + (q31_t)0x112d7d00, (q31_t)0x111494e4, (q31_t)0x10fbac1e, (q31_t)0x10e2c2b2, (q31_t)0x10c9d89e, (q31_t)0x10b0ede5, + (q31_t)0x10980287, (q31_t)0x107f1686, + (q31_t)0x106629e1, (q31_t)0x104d3c9b, (q31_t)0x10344eb4, (q31_t)0x101b602d, (q31_t)0x10027107, (q31_t)0xfe98143, + (q31_t)0xfd090e1, (q31_t)0xfb79fe4, + (q31_t)0xf9eae4c, (q31_t)0xf85bc19, (q31_t)0xf6cc94e, (q31_t)0xf53d5ea, (q31_t)0xf3ae1ee, (q31_t)0xf21ed5d, (q31_t)0xf08f836, + (q31_t)0xef0027b, + (q31_t)0xed70c2c, (q31_t)0xebe154b, (q31_t)0xea51dd8, (q31_t)0xe8c25d5, (q31_t)0xe732d42, (q31_t)0xe5a3421, (q31_t)0xe413a72, + (q31_t)0xe284036, + (q31_t)0xe0f456f, (q31_t)0xdf64a1c, (q31_t)0xddd4e40, (q31_t)0xdc451dc, (q31_t)0xdab54ef, (q31_t)0xd92577b, (q31_t)0xd795982, + (q31_t)0xd605b03, + (q31_t)0xd475c00, (q31_t)0xd2e5c7b, (q31_t)0xd155c73, (q31_t)0xcfc5bea, (q31_t)0xce35ae1, (q31_t)0xcca5959, (q31_t)0xcb15752, + (q31_t)0xc9854cf, + (q31_t)0xc7f51cf, (q31_t)0xc664e53, (q31_t)0xc4d4a5d, (q31_t)0xc3445ee, (q31_t)0xc1b4107, (q31_t)0xc023ba7, (q31_t)0xbe935d2, + (q31_t)0xbd02f87, + (q31_t)0xbb728c7, (q31_t)0xb9e2193, (q31_t)0xb8519ed, (q31_t)0xb6c11d5, (q31_t)0xb53094d, (q31_t)0xb3a0055, (q31_t)0xb20f6ee, + (q31_t)0xb07ed19, + (q31_t)0xaeee2d7, (q31_t)0xad5d829, (q31_t)0xabccd11, (q31_t)0xaa3c18e, (q31_t)0xa8ab5a2, (q31_t)0xa71a94f, (q31_t)0xa589c94, + (q31_t)0xa3f8f73, + (q31_t)0xa2681ed, (q31_t)0xa0d7403, (q31_t)0x9f465b5, (q31_t)0x9db5706, (q31_t)0x9c247f5, (q31_t)0x9a93884, (q31_t)0x99028b3, + (q31_t)0x9771884, + (q31_t)0x95e07f8, (q31_t)0x944f70f, (q31_t)0x92be5ca, (q31_t)0x912d42c, (q31_t)0x8f9c233, (q31_t)0x8e0afe2, (q31_t)0x8c79d3a, + (q31_t)0x8ae8a3a, + (q31_t)0x89576e5, (q31_t)0x87c633c, (q31_t)0x8634f3e, (q31_t)0x84a3aee, (q31_t)0x831264c, (q31_t)0x8181159, (q31_t)0x7fefc16, + (q31_t)0x7e5e685, + (q31_t)0x7ccd0a5, (q31_t)0x7b3ba78, (q31_t)0x79aa400, (q31_t)0x7818d3c, (q31_t)0x768762e, (q31_t)0x74f5ed7, (q31_t)0x7364738, + (q31_t)0x71d2f52, + (q31_t)0x7041726, (q31_t)0x6eafeb4, (q31_t)0x6d1e5fe, (q31_t)0x6b8cd05, (q31_t)0x69fb3c9, (q31_t)0x6869a4c, (q31_t)0x66d808f, + (q31_t)0x6546692, + (q31_t)0x63b4c57, (q31_t)0x62231de, (q31_t)0x6091729, (q31_t)0x5effc38, (q31_t)0x5d6e10c, (q31_t)0x5bdc5a7, (q31_t)0x5a4aa09, + (q31_t)0x58b8e34, + (q31_t)0x5727228, (q31_t)0x55955e6, (q31_t)0x540396f, (q31_t)0x5271cc4, (q31_t)0x50dffe7, (q31_t)0x4f4e2d8, (q31_t)0x4dbc597, + (q31_t)0x4c2a827, + (q31_t)0x4a98a88, (q31_t)0x4906cbb, (q31_t)0x4774ec1, (q31_t)0x45e309a, (q31_t)0x4451249, (q31_t)0x42bf3cd, (q31_t)0x412d528, + (q31_t)0x3f9b65b, + (q31_t)0x3e09767, (q31_t)0x3c7784d, (q31_t)0x3ae590d, (q31_t)0x39539a9, (q31_t)0x37c1a22, (q31_t)0x362fa78, (q31_t)0x349daac, + (q31_t)0x330bac1, + (q31_t)0x3179ab5, (q31_t)0x2fe7a8c, (q31_t)0x2e55a44, (q31_t)0x2cc39e1, (q31_t)0x2b31961, (q31_t)0x299f8c7, (q31_t)0x280d813, + (q31_t)0x267b747, + (q31_t)0x24e9662, (q31_t)0x2357567, (q31_t)0x21c5457, (q31_t)0x2033331, (q31_t)0x1ea11f7, (q31_t)0x1d0f0ab, (q31_t)0x1b7cf4d, + (q31_t)0x19eaddd, + (q31_t)0x1858c5e, (q31_t)0x16c6ad0, (q31_t)0x1534934, (q31_t)0x13a278a, (q31_t)0x12105d5, (q31_t)0x107e414, (q31_t)0xeec249, + (q31_t)0xd5a075, + (q31_t)0xbc7e99, (q31_t)0xa35cb5, (q31_t)0x8a3acb, (q31_t)0x7118dc, (q31_t)0x57f6e9, (q31_t)0x3ed4f2, (q31_t)0x25b2f8, + (q31_t)0xc90fe +}; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + const q31_t WeightsQ31_8192[16384] = { + (q31_t)0x7fffffff, (q31_t)0x00000000, (q31_t)0x7fffffd9, (q31_t)0xfff9b781, (q31_t)0x7fffff62, (q31_t)0xfff36f02, (q31_t)0x7ffffe9d, (q31_t)0xffed2684, + (q31_t)0x7ffffd88, (q31_t)0xffe6de05, (q31_t)0x7ffffc25, (q31_t)0xffe09586, (q31_t)0x7ffffa73, (q31_t)0xffda4d08, (q31_t)0x7ffff872, (q31_t)0xffd40489, + (q31_t)0x7ffff621, (q31_t)0xffcdbc0b, (q31_t)0x7ffff382, (q31_t)0xffc7738c, (q31_t)0x7ffff094, (q31_t)0xffc12b0e, (q31_t)0x7fffed57, (q31_t)0xffbae290, + (q31_t)0x7fffe9cb, (q31_t)0xffb49a12, (q31_t)0x7fffe5f0, (q31_t)0xffae5195, (q31_t)0x7fffe1c6, (q31_t)0xffa80917, (q31_t)0x7fffdd4d, (q31_t)0xffa1c09a, + (q31_t)0x7fffd886, (q31_t)0xff9b781d, (q31_t)0x7fffd36f, (q31_t)0xff952fa0, (q31_t)0x7fffce09, (q31_t)0xff8ee724, (q31_t)0x7fffc854, (q31_t)0xff889ea7, + (q31_t)0x7fffc251, (q31_t)0xff82562c, (q31_t)0x7fffbbfe, (q31_t)0xff7c0db0, (q31_t)0x7fffb55c, (q31_t)0xff75c535, (q31_t)0x7fffae6c, (q31_t)0xff6f7cba, + (q31_t)0x7fffa72c, (q31_t)0xff69343f, (q31_t)0x7fff9f9e, (q31_t)0xff62ebc5, (q31_t)0x7fff97c1, (q31_t)0xff5ca34b, (q31_t)0x7fff8f94, (q31_t)0xff565ad1, + (q31_t)0x7fff8719, (q31_t)0xff501258, (q31_t)0x7fff7e4f, (q31_t)0xff49c9df, (q31_t)0x7fff7536, (q31_t)0xff438167, (q31_t)0x7fff6bcd, (q31_t)0xff3d38ef, + (q31_t)0x7fff6216, (q31_t)0xff36f078, (q31_t)0x7fff5810, (q31_t)0xff30a801, (q31_t)0x7fff4dbb, (q31_t)0xff2a5f8b, (q31_t)0x7fff4317, (q31_t)0xff241715, + (q31_t)0x7fff3824, (q31_t)0xff1dcea0, (q31_t)0x7fff2ce2, (q31_t)0xff17862b, (q31_t)0x7fff2151, (q31_t)0xff113db7, (q31_t)0x7fff1572, (q31_t)0xff0af543, + (q31_t)0x7fff0943, (q31_t)0xff04acd0, (q31_t)0x7ffefcc5, (q31_t)0xfefe645e, (q31_t)0x7ffeeff8, (q31_t)0xfef81bec, (q31_t)0x7ffee2dd, (q31_t)0xfef1d37b, + (q31_t)0x7ffed572, (q31_t)0xfeeb8b0a, (q31_t)0x7ffec7b9, (q31_t)0xfee5429a, (q31_t)0x7ffeb9b0, (q31_t)0xfedefa2b, (q31_t)0x7ffeab59, (q31_t)0xfed8b1bd, + (q31_t)0x7ffe9cb2, (q31_t)0xfed2694f, (q31_t)0x7ffe8dbd, (q31_t)0xfecc20e2, (q31_t)0x7ffe7e79, (q31_t)0xfec5d876, (q31_t)0x7ffe6ee5, (q31_t)0xfebf900a, + (q31_t)0x7ffe5f03, (q31_t)0xfeb947a0, (q31_t)0x7ffe4ed2, (q31_t)0xfeb2ff36, (q31_t)0x7ffe3e52, (q31_t)0xfeacb6cc, (q31_t)0x7ffe2d83, (q31_t)0xfea66e64, + (q31_t)0x7ffe1c65, (q31_t)0xfea025fd, (q31_t)0x7ffe0af8, (q31_t)0xfe99dd96, (q31_t)0x7ffdf93c, (q31_t)0xfe939530, (q31_t)0x7ffde731, (q31_t)0xfe8d4ccb, + (q31_t)0x7ffdd4d7, (q31_t)0xfe870467, (q31_t)0x7ffdc22e, (q31_t)0xfe80bc04, (q31_t)0x7ffdaf37, (q31_t)0xfe7a73a2, (q31_t)0x7ffd9bf0, (q31_t)0xfe742b41, + (q31_t)0x7ffd885a, (q31_t)0xfe6de2e0, (q31_t)0x7ffd7476, (q31_t)0xfe679a81, (q31_t)0x7ffd6042, (q31_t)0xfe615223, (q31_t)0x7ffd4bc0, (q31_t)0xfe5b09c5, + (q31_t)0x7ffd36ee, (q31_t)0xfe54c169, (q31_t)0x7ffd21ce, (q31_t)0xfe4e790d, (q31_t)0x7ffd0c5f, (q31_t)0xfe4830b3, (q31_t)0x7ffcf6a0, (q31_t)0xfe41e85a, + (q31_t)0x7ffce093, (q31_t)0xfe3ba002, (q31_t)0x7ffcca37, (q31_t)0xfe3557ab, (q31_t)0x7ffcb38c, (q31_t)0xfe2f0f55, (q31_t)0x7ffc9c92, (q31_t)0xfe28c700, + (q31_t)0x7ffc8549, (q31_t)0xfe227eac, (q31_t)0x7ffc6db1, (q31_t)0xfe1c365a, (q31_t)0x7ffc55ca, (q31_t)0xfe15ee09, (q31_t)0x7ffc3d94, (q31_t)0xfe0fa5b8, + (q31_t)0x7ffc250f, (q31_t)0xfe095d69, (q31_t)0x7ffc0c3b, (q31_t)0xfe03151c, (q31_t)0x7ffbf319, (q31_t)0xfdfccccf, (q31_t)0x7ffbd9a7, (q31_t)0xfdf68484, + (q31_t)0x7ffbbfe6, (q31_t)0xfdf03c3a, (q31_t)0x7ffba5d7, (q31_t)0xfde9f3f1, (q31_t)0x7ffb8b78, (q31_t)0xfde3aba9, (q31_t)0x7ffb70cb, (q31_t)0xfddd6363, + (q31_t)0x7ffb55ce, (q31_t)0xfdd71b1e, (q31_t)0x7ffb3a83, (q31_t)0xfdd0d2db, (q31_t)0x7ffb1ee9, (q31_t)0xfdca8a99, (q31_t)0x7ffb0300, (q31_t)0xfdc44258, + (q31_t)0x7ffae6c7, (q31_t)0xfdbdfa18, (q31_t)0x7ffaca40, (q31_t)0xfdb7b1da, (q31_t)0x7ffaad6a, (q31_t)0xfdb1699e, (q31_t)0x7ffa9045, (q31_t)0xfdab2162, + (q31_t)0x7ffa72d1, (q31_t)0xfda4d929, (q31_t)0x7ffa550e, (q31_t)0xfd9e90f0, (q31_t)0x7ffa36fc, (q31_t)0xfd9848b9, (q31_t)0x7ffa189c, (q31_t)0xfd920084, + (q31_t)0x7ff9f9ec, (q31_t)0xfd8bb850, (q31_t)0x7ff9daed, (q31_t)0xfd85701e, (q31_t)0x7ff9bba0, (q31_t)0xfd7f27ed, (q31_t)0x7ff99c03, (q31_t)0xfd78dfbd, + (q31_t)0x7ff97c18, (q31_t)0xfd729790, (q31_t)0x7ff95bdd, (q31_t)0xfd6c4f64, (q31_t)0x7ff93b54, (q31_t)0xfd660739, (q31_t)0x7ff91a7b, (q31_t)0xfd5fbf10, + (q31_t)0x7ff8f954, (q31_t)0xfd5976e9, (q31_t)0x7ff8d7de, (q31_t)0xfd532ec3, (q31_t)0x7ff8b619, (q31_t)0xfd4ce69f, (q31_t)0x7ff89405, (q31_t)0xfd469e7c, + (q31_t)0x7ff871a2, (q31_t)0xfd40565c, (q31_t)0x7ff84ef0, (q31_t)0xfd3a0e3d, (q31_t)0x7ff82bef, (q31_t)0xfd33c61f, (q31_t)0x7ff8089f, (q31_t)0xfd2d7e04, + (q31_t)0x7ff7e500, (q31_t)0xfd2735ea, (q31_t)0x7ff7c113, (q31_t)0xfd20edd2, (q31_t)0x7ff79cd6, (q31_t)0xfd1aa5bc, (q31_t)0x7ff7784a, (q31_t)0xfd145da7, + (q31_t)0x7ff75370, (q31_t)0xfd0e1594, (q31_t)0x7ff72e46, (q31_t)0xfd07cd83, (q31_t)0x7ff708ce, (q31_t)0xfd018574, (q31_t)0x7ff6e307, (q31_t)0xfcfb3d67, + (q31_t)0x7ff6bcf0, (q31_t)0xfcf4f55c, (q31_t)0x7ff6968b, (q31_t)0xfceead52, (q31_t)0x7ff66fd7, (q31_t)0xfce8654b, (q31_t)0x7ff648d4, (q31_t)0xfce21d45, + (q31_t)0x7ff62182, (q31_t)0xfcdbd541, (q31_t)0x7ff5f9e1, (q31_t)0xfcd58d3f, (q31_t)0x7ff5d1f1, (q31_t)0xfccf453f, (q31_t)0x7ff5a9b2, (q31_t)0xfcc8fd41, + (q31_t)0x7ff58125, (q31_t)0xfcc2b545, (q31_t)0x7ff55848, (q31_t)0xfcbc6d4c, (q31_t)0x7ff52f1d, (q31_t)0xfcb62554, (q31_t)0x7ff505a2, (q31_t)0xfcafdd5e, + (q31_t)0x7ff4dbd9, (q31_t)0xfca9956a, (q31_t)0x7ff4b1c0, (q31_t)0xfca34d78, (q31_t)0x7ff48759, (q31_t)0xfc9d0588, (q31_t)0x7ff45ca3, (q31_t)0xfc96bd9b, + (q31_t)0x7ff4319d, (q31_t)0xfc9075af, (q31_t)0x7ff40649, (q31_t)0xfc8a2dc6, (q31_t)0x7ff3daa6, (q31_t)0xfc83e5de, (q31_t)0x7ff3aeb4, (q31_t)0xfc7d9df9, + (q31_t)0x7ff38274, (q31_t)0xfc775616, (q31_t)0x7ff355e4, (q31_t)0xfc710e36, (q31_t)0x7ff32905, (q31_t)0xfc6ac657, (q31_t)0x7ff2fbd7, (q31_t)0xfc647e7b, + (q31_t)0x7ff2ce5b, (q31_t)0xfc5e36a0, (q31_t)0x7ff2a08f, (q31_t)0xfc57eec9, (q31_t)0x7ff27275, (q31_t)0xfc51a6f3, (q31_t)0x7ff2440b, (q31_t)0xfc4b5f20, + (q31_t)0x7ff21553, (q31_t)0xfc45174e, (q31_t)0x7ff1e64c, (q31_t)0xfc3ecf80, (q31_t)0x7ff1b6f6, (q31_t)0xfc3887b3, (q31_t)0x7ff18751, (q31_t)0xfc323fe9, + (q31_t)0x7ff1575d, (q31_t)0xfc2bf821, (q31_t)0x7ff1271a, (q31_t)0xfc25b05c, (q31_t)0x7ff0f688, (q31_t)0xfc1f6899, (q31_t)0x7ff0c5a7, (q31_t)0xfc1920d8, + (q31_t)0x7ff09478, (q31_t)0xfc12d91a, (q31_t)0x7ff062f9, (q31_t)0xfc0c915e, (q31_t)0x7ff0312c, (q31_t)0xfc0649a5, (q31_t)0x7fefff0f, (q31_t)0xfc0001ee, + (q31_t)0x7fefcca4, (q31_t)0xfbf9ba39, (q31_t)0x7fef99ea, (q31_t)0xfbf37287, (q31_t)0x7fef66e1, (q31_t)0xfbed2ad8, (q31_t)0x7fef3388, (q31_t)0xfbe6e32b, + (q31_t)0x7feeffe1, (q31_t)0xfbe09b80, (q31_t)0x7feecbec, (q31_t)0xfbda53d8, (q31_t)0x7fee97a7, (q31_t)0xfbd40c33, (q31_t)0x7fee6313, (q31_t)0xfbcdc490, + (q31_t)0x7fee2e30, (q31_t)0xfbc77cf0, (q31_t)0x7fedf8ff, (q31_t)0xfbc13552, (q31_t)0x7fedc37e, (q31_t)0xfbbaedb7, (q31_t)0x7fed8daf, (q31_t)0xfbb4a61f, + (q31_t)0x7fed5791, (q31_t)0xfbae5e89, (q31_t)0x7fed2123, (q31_t)0xfba816f6, (q31_t)0x7fecea67, (q31_t)0xfba1cf66, (q31_t)0x7fecb35c, (q31_t)0xfb9b87d8, + (q31_t)0x7fec7c02, (q31_t)0xfb95404d, (q31_t)0x7fec4459, (q31_t)0xfb8ef8c5, (q31_t)0x7fec0c62, (q31_t)0xfb88b13f, (q31_t)0x7febd41b, (q31_t)0xfb8269bd, + (q31_t)0x7feb9b85, (q31_t)0xfb7c223d, (q31_t)0x7feb62a1, (q31_t)0xfb75dac0, (q31_t)0x7feb296d, (q31_t)0xfb6f9345, (q31_t)0x7feaefeb, (q31_t)0xfb694bce, + (q31_t)0x7feab61a, (q31_t)0xfb630459, (q31_t)0x7fea7bfa, (q31_t)0xfb5cbce7, (q31_t)0x7fea418b, (q31_t)0xfb567578, (q31_t)0x7fea06cd, (q31_t)0xfb502e0c, + (q31_t)0x7fe9cbc0, (q31_t)0xfb49e6a3, (q31_t)0x7fe99064, (q31_t)0xfb439f3c, (q31_t)0x7fe954ba, (q31_t)0xfb3d57d9, (q31_t)0x7fe918c0, (q31_t)0xfb371078, + (q31_t)0x7fe8dc78, (q31_t)0xfb30c91b, (q31_t)0x7fe89fe0, (q31_t)0xfb2a81c0, (q31_t)0x7fe862fa, (q31_t)0xfb243a69, (q31_t)0x7fe825c5, (q31_t)0xfb1df314, + (q31_t)0x7fe7e841, (q31_t)0xfb17abc2, (q31_t)0x7fe7aa6e, (q31_t)0xfb116474, (q31_t)0x7fe76c4c, (q31_t)0xfb0b1d28, (q31_t)0x7fe72ddb, (q31_t)0xfb04d5e0, + (q31_t)0x7fe6ef1c, (q31_t)0xfafe8e9b, (q31_t)0x7fe6b00d, (q31_t)0xfaf84758, (q31_t)0x7fe670b0, (q31_t)0xfaf20019, (q31_t)0x7fe63103, (q31_t)0xfaebb8dd, + (q31_t)0x7fe5f108, (q31_t)0xfae571a4, (q31_t)0x7fe5b0be, (q31_t)0xfadf2a6e, (q31_t)0x7fe57025, (q31_t)0xfad8e33c, (q31_t)0x7fe52f3d, (q31_t)0xfad29c0c, + (q31_t)0x7fe4ee06, (q31_t)0xfacc54e0, (q31_t)0x7fe4ac81, (q31_t)0xfac60db7, (q31_t)0x7fe46aac, (q31_t)0xfabfc691, (q31_t)0x7fe42889, (q31_t)0xfab97f6e, + (q31_t)0x7fe3e616, (q31_t)0xfab3384f, (q31_t)0x7fe3a355, (q31_t)0xfaacf133, (q31_t)0x7fe36045, (q31_t)0xfaa6aa1a, (q31_t)0x7fe31ce6, (q31_t)0xfaa06305, + (q31_t)0x7fe2d938, (q31_t)0xfa9a1bf3, (q31_t)0x7fe2953b, (q31_t)0xfa93d4e4, (q31_t)0x7fe250ef, (q31_t)0xfa8d8dd8, (q31_t)0x7fe20c55, (q31_t)0xfa8746d0, + (q31_t)0x7fe1c76b, (q31_t)0xfa80ffcb, (q31_t)0x7fe18233, (q31_t)0xfa7ab8ca, (q31_t)0x7fe13cac, (q31_t)0xfa7471cc, (q31_t)0x7fe0f6d6, (q31_t)0xfa6e2ad1, + (q31_t)0x7fe0b0b1, (q31_t)0xfa67e3da, (q31_t)0x7fe06a3d, (q31_t)0xfa619ce7, (q31_t)0x7fe0237a, (q31_t)0xfa5b55f7, (q31_t)0x7fdfdc69, (q31_t)0xfa550f0a, + (q31_t)0x7fdf9508, (q31_t)0xfa4ec821, (q31_t)0x7fdf4d59, (q31_t)0xfa48813b, (q31_t)0x7fdf055a, (q31_t)0xfa423a59, (q31_t)0x7fdebd0d, (q31_t)0xfa3bf37a, + (q31_t)0x7fde7471, (q31_t)0xfa35ac9f, (q31_t)0x7fde2b86, (q31_t)0xfa2f65c8, (q31_t)0x7fdde24d, (q31_t)0xfa291ef4, (q31_t)0x7fdd98c4, (q31_t)0xfa22d823, + (q31_t)0x7fdd4eec, (q31_t)0xfa1c9157, (q31_t)0x7fdd04c6, (q31_t)0xfa164a8e, (q31_t)0x7fdcba51, (q31_t)0xfa1003c8, (q31_t)0x7fdc6f8d, (q31_t)0xfa09bd06, + (q31_t)0x7fdc247a, (q31_t)0xfa037648, (q31_t)0x7fdbd918, (q31_t)0xf9fd2f8e, (q31_t)0x7fdb8d67, (q31_t)0xf9f6e8d7, (q31_t)0x7fdb4167, (q31_t)0xf9f0a224, + (q31_t)0x7fdaf519, (q31_t)0xf9ea5b75, (q31_t)0x7fdaa87c, (q31_t)0xf9e414ca, (q31_t)0x7fda5b8f, (q31_t)0xf9ddce22, (q31_t)0x7fda0e54, (q31_t)0xf9d7877e, + (q31_t)0x7fd9c0ca, (q31_t)0xf9d140de, (q31_t)0x7fd972f2, (q31_t)0xf9cafa42, (q31_t)0x7fd924ca, (q31_t)0xf9c4b3a9, (q31_t)0x7fd8d653, (q31_t)0xf9be6d15, + (q31_t)0x7fd8878e, (q31_t)0xf9b82684, (q31_t)0x7fd8387a, (q31_t)0xf9b1dff7, (q31_t)0x7fd7e917, (q31_t)0xf9ab996e, (q31_t)0x7fd79965, (q31_t)0xf9a552e9, + (q31_t)0x7fd74964, (q31_t)0xf99f0c68, (q31_t)0x7fd6f914, (q31_t)0xf998c5ea, (q31_t)0x7fd6a875, (q31_t)0xf9927f71, (q31_t)0x7fd65788, (q31_t)0xf98c38fc, + (q31_t)0x7fd6064c, (q31_t)0xf985f28a, (q31_t)0x7fd5b4c1, (q31_t)0xf97fac1d, (q31_t)0x7fd562e7, (q31_t)0xf97965b4, (q31_t)0x7fd510be, (q31_t)0xf9731f4e, + (q31_t)0x7fd4be46, (q31_t)0xf96cd8ed, (q31_t)0x7fd46b80, (q31_t)0xf9669290, (q31_t)0x7fd4186a, (q31_t)0xf9604c37, (q31_t)0x7fd3c506, (q31_t)0xf95a05e2, + (q31_t)0x7fd37153, (q31_t)0xf953bf91, (q31_t)0x7fd31d51, (q31_t)0xf94d7944, (q31_t)0x7fd2c900, (q31_t)0xf94732fb, (q31_t)0x7fd27460, (q31_t)0xf940ecb7, + (q31_t)0x7fd21f72, (q31_t)0xf93aa676, (q31_t)0x7fd1ca35, (q31_t)0xf934603a, (q31_t)0x7fd174a8, (q31_t)0xf92e1a02, (q31_t)0x7fd11ecd, (q31_t)0xf927d3ce, + (q31_t)0x7fd0c8a3, (q31_t)0xf9218d9e, (q31_t)0x7fd0722b, (q31_t)0xf91b4773, (q31_t)0x7fd01b63, (q31_t)0xf915014c, (q31_t)0x7fcfc44d, (q31_t)0xf90ebb29, + (q31_t)0x7fcf6ce8, (q31_t)0xf908750a, (q31_t)0x7fcf1533, (q31_t)0xf9022ef0, (q31_t)0x7fcebd31, (q31_t)0xf8fbe8da, (q31_t)0x7fce64df, (q31_t)0xf8f5a2c9, + (q31_t)0x7fce0c3e, (q31_t)0xf8ef5cbb, (q31_t)0x7fcdb34f, (q31_t)0xf8e916b2, (q31_t)0x7fcd5a11, (q31_t)0xf8e2d0ae, (q31_t)0x7fcd0083, (q31_t)0xf8dc8aae, + (q31_t)0x7fcca6a7, (q31_t)0xf8d644b2, (q31_t)0x7fcc4c7d, (q31_t)0xf8cffebb, (q31_t)0x7fcbf203, (q31_t)0xf8c9b8c8, (q31_t)0x7fcb973b, (q31_t)0xf8c372d9, + (q31_t)0x7fcb3c23, (q31_t)0xf8bd2cef, (q31_t)0x7fcae0bd, (q31_t)0xf8b6e70a, (q31_t)0x7fca8508, (q31_t)0xf8b0a129, (q31_t)0x7fca2905, (q31_t)0xf8aa5b4c, + (q31_t)0x7fc9ccb2, (q31_t)0xf8a41574, (q31_t)0x7fc97011, (q31_t)0xf89dcfa1, (q31_t)0x7fc91320, (q31_t)0xf89789d2, (q31_t)0x7fc8b5e1, (q31_t)0xf8914407, + (q31_t)0x7fc85854, (q31_t)0xf88afe42, (q31_t)0x7fc7fa77, (q31_t)0xf884b880, (q31_t)0x7fc79c4b, (q31_t)0xf87e72c4, (q31_t)0x7fc73dd1, (q31_t)0xf8782d0c, + (q31_t)0x7fc6df08, (q31_t)0xf871e759, (q31_t)0x7fc67ff0, (q31_t)0xf86ba1aa, (q31_t)0x7fc62089, (q31_t)0xf8655c00, (q31_t)0x7fc5c0d3, (q31_t)0xf85f165b, + (q31_t)0x7fc560cf, (q31_t)0xf858d0bb, (q31_t)0x7fc5007c, (q31_t)0xf8528b1f, (q31_t)0x7fc49fda, (q31_t)0xf84c4588, (q31_t)0x7fc43ee9, (q31_t)0xf845fff5, + (q31_t)0x7fc3dda9, (q31_t)0xf83fba68, (q31_t)0x7fc37c1b, (q31_t)0xf83974df, (q31_t)0x7fc31a3d, (q31_t)0xf8332f5b, (q31_t)0x7fc2b811, (q31_t)0xf82ce9dc, + (q31_t)0x7fc25596, (q31_t)0xf826a462, (q31_t)0x7fc1f2cc, (q31_t)0xf8205eec, (q31_t)0x7fc18fb4, (q31_t)0xf81a197b, (q31_t)0x7fc12c4d, (q31_t)0xf813d410, + (q31_t)0x7fc0c896, (q31_t)0xf80d8ea9, (q31_t)0x7fc06491, (q31_t)0xf8074947, (q31_t)0x7fc0003e, (q31_t)0xf80103ea, (q31_t)0x7fbf9b9b, (q31_t)0xf7fabe92, + (q31_t)0x7fbf36aa, (q31_t)0xf7f4793e, (q31_t)0x7fbed16a, (q31_t)0xf7ee33f0, (q31_t)0x7fbe6bdb, (q31_t)0xf7e7eea7, (q31_t)0x7fbe05fd, (q31_t)0xf7e1a963, + (q31_t)0x7fbd9fd0, (q31_t)0xf7db6423, (q31_t)0x7fbd3955, (q31_t)0xf7d51ee9, (q31_t)0x7fbcd28b, (q31_t)0xf7ced9b4, (q31_t)0x7fbc6b72, (q31_t)0xf7c89484, + (q31_t)0x7fbc040a, (q31_t)0xf7c24f59, (q31_t)0x7fbb9c53, (q31_t)0xf7bc0a33, (q31_t)0x7fbb344e, (q31_t)0xf7b5c512, (q31_t)0x7fbacbfa, (q31_t)0xf7af7ff6, + (q31_t)0x7fba6357, (q31_t)0xf7a93ae0, (q31_t)0x7fb9fa65, (q31_t)0xf7a2f5ce, (q31_t)0x7fb99125, (q31_t)0xf79cb0c2, (q31_t)0x7fb92796, (q31_t)0xf7966bbb, + (q31_t)0x7fb8bdb8, (q31_t)0xf79026b9, (q31_t)0x7fb8538b, (q31_t)0xf789e1bc, (q31_t)0x7fb7e90f, (q31_t)0xf7839cc4, (q31_t)0x7fb77e45, (q31_t)0xf77d57d2, + (q31_t)0x7fb7132b, (q31_t)0xf77712e5, (q31_t)0x7fb6a7c3, (q31_t)0xf770cdfd, (q31_t)0x7fb63c0d, (q31_t)0xf76a891b, (q31_t)0x7fb5d007, (q31_t)0xf764443d, + (q31_t)0x7fb563b3, (q31_t)0xf75dff66, (q31_t)0x7fb4f710, (q31_t)0xf757ba93, (q31_t)0x7fb48a1e, (q31_t)0xf75175c6, (q31_t)0x7fb41cdd, (q31_t)0xf74b30fe, + (q31_t)0x7fb3af4e, (q31_t)0xf744ec3b, (q31_t)0x7fb34170, (q31_t)0xf73ea77e, (q31_t)0x7fb2d343, (q31_t)0xf73862c6, (q31_t)0x7fb264c7, (q31_t)0xf7321e14, + (q31_t)0x7fb1f5fc, (q31_t)0xf72bd967, (q31_t)0x7fb186e3, (q31_t)0xf72594c0, (q31_t)0x7fb1177b, (q31_t)0xf71f501e, (q31_t)0x7fb0a7c4, (q31_t)0xf7190b81, + (q31_t)0x7fb037bf, (q31_t)0xf712c6ea, (q31_t)0x7fafc76a, (q31_t)0xf70c8259, (q31_t)0x7faf56c7, (q31_t)0xf7063dcd, (q31_t)0x7faee5d5, (q31_t)0xf6fff946, + (q31_t)0x7fae7495, (q31_t)0xf6f9b4c6, (q31_t)0x7fae0305, (q31_t)0xf6f3704a, (q31_t)0x7fad9127, (q31_t)0xf6ed2bd4, (q31_t)0x7fad1efa, (q31_t)0xf6e6e764, + (q31_t)0x7facac7f, (q31_t)0xf6e0a2fa, (q31_t)0x7fac39b4, (q31_t)0xf6da5e95, (q31_t)0x7fabc69b, (q31_t)0xf6d41a36, (q31_t)0x7fab5333, (q31_t)0xf6cdd5dc, + (q31_t)0x7faadf7c, (q31_t)0xf6c79188, (q31_t)0x7faa6b77, (q31_t)0xf6c14d3a, (q31_t)0x7fa9f723, (q31_t)0xf6bb08f1, (q31_t)0x7fa98280, (q31_t)0xf6b4c4ae, + (q31_t)0x7fa90d8e, (q31_t)0xf6ae8071, (q31_t)0x7fa8984e, (q31_t)0xf6a83c3a, (q31_t)0x7fa822bf, (q31_t)0xf6a1f808, (q31_t)0x7fa7ace1, (q31_t)0xf69bb3dd, + (q31_t)0x7fa736b4, (q31_t)0xf6956fb7, (q31_t)0x7fa6c039, (q31_t)0xf68f2b96, (q31_t)0x7fa6496e, (q31_t)0xf688e77c, (q31_t)0x7fa5d256, (q31_t)0xf682a367, + (q31_t)0x7fa55aee, (q31_t)0xf67c5f59, (q31_t)0x7fa4e338, (q31_t)0xf6761b50, (q31_t)0x7fa46b32, (q31_t)0xf66fd74d, (q31_t)0x7fa3f2df, (q31_t)0xf6699350, + (q31_t)0x7fa37a3c, (q31_t)0xf6634f59, (q31_t)0x7fa3014b, (q31_t)0xf65d0b68, (q31_t)0x7fa2880b, (q31_t)0xf656c77c, (q31_t)0x7fa20e7c, (q31_t)0xf6508397, + (q31_t)0x7fa1949e, (q31_t)0xf64a3fb8, (q31_t)0x7fa11a72, (q31_t)0xf643fbdf, (q31_t)0x7fa09ff7, (q31_t)0xf63db80b, (q31_t)0x7fa0252e, (q31_t)0xf637743e, + (q31_t)0x7f9faa15, (q31_t)0xf6313077, (q31_t)0x7f9f2eae, (q31_t)0xf62aecb5, (q31_t)0x7f9eb2f8, (q31_t)0xf624a8fa, (q31_t)0x7f9e36f4, (q31_t)0xf61e6545, + (q31_t)0x7f9dbaa0, (q31_t)0xf6182196, (q31_t)0x7f9d3dfe, (q31_t)0xf611dded, (q31_t)0x7f9cc10d, (q31_t)0xf60b9a4b, (q31_t)0x7f9c43ce, (q31_t)0xf60556ae, + (q31_t)0x7f9bc640, (q31_t)0xf5ff1318, (q31_t)0x7f9b4863, (q31_t)0xf5f8cf87, (q31_t)0x7f9aca37, (q31_t)0xf5f28bfd, (q31_t)0x7f9a4bbd, (q31_t)0xf5ec4879, + (q31_t)0x7f99ccf4, (q31_t)0xf5e604fc, (q31_t)0x7f994ddc, (q31_t)0xf5dfc184, (q31_t)0x7f98ce76, (q31_t)0xf5d97e13, (q31_t)0x7f984ec1, (q31_t)0xf5d33aa8, + (q31_t)0x7f97cebd, (q31_t)0xf5ccf743, (q31_t)0x7f974e6a, (q31_t)0xf5c6b3e5, (q31_t)0x7f96cdc9, (q31_t)0xf5c0708d, (q31_t)0x7f964cd9, (q31_t)0xf5ba2d3b, + (q31_t)0x7f95cb9a, (q31_t)0xf5b3e9f0, (q31_t)0x7f954a0d, (q31_t)0xf5ada6ab, (q31_t)0x7f94c831, (q31_t)0xf5a7636c, (q31_t)0x7f944606, (q31_t)0xf5a12034, + (q31_t)0x7f93c38c, (q31_t)0xf59add02, (q31_t)0x7f9340c4, (q31_t)0xf59499d6, (q31_t)0x7f92bdad, (q31_t)0xf58e56b1, (q31_t)0x7f923a48, (q31_t)0xf5881393, + (q31_t)0x7f91b694, (q31_t)0xf581d07b, (q31_t)0x7f913291, (q31_t)0xf57b8d69, (q31_t)0x7f90ae3f, (q31_t)0xf5754a5e, (q31_t)0x7f90299f, (q31_t)0xf56f0759, + (q31_t)0x7f8fa4b0, (q31_t)0xf568c45b, (q31_t)0x7f8f1f72, (q31_t)0xf5628163, (q31_t)0x7f8e99e6, (q31_t)0xf55c3e72, (q31_t)0x7f8e140a, (q31_t)0xf555fb88, + (q31_t)0x7f8d8de1, (q31_t)0xf54fb8a4, (q31_t)0x7f8d0768, (q31_t)0xf54975c6, (q31_t)0x7f8c80a1, (q31_t)0xf54332ef, (q31_t)0x7f8bf98b, (q31_t)0xf53cf01f, + (q31_t)0x7f8b7227, (q31_t)0xf536ad56, (q31_t)0x7f8aea74, (q31_t)0xf5306a93, (q31_t)0x7f8a6272, (q31_t)0xf52a27d7, (q31_t)0x7f89da21, (q31_t)0xf523e521, + (q31_t)0x7f895182, (q31_t)0xf51da273, (q31_t)0x7f88c894, (q31_t)0xf5175fca, (q31_t)0x7f883f58, (q31_t)0xf5111d29, (q31_t)0x7f87b5cd, (q31_t)0xf50ada8f, + (q31_t)0x7f872bf3, (q31_t)0xf50497fb, (q31_t)0x7f86a1ca, (q31_t)0xf4fe556e, (q31_t)0x7f861753, (q31_t)0xf4f812e7, (q31_t)0x7f858c8d, (q31_t)0xf4f1d068, + (q31_t)0x7f850179, (q31_t)0xf4eb8def, (q31_t)0x7f847616, (q31_t)0xf4e54b7d, (q31_t)0x7f83ea64, (q31_t)0xf4df0912, (q31_t)0x7f835e64, (q31_t)0xf4d8c6ae, + (q31_t)0x7f82d214, (q31_t)0xf4d28451, (q31_t)0x7f824577, (q31_t)0xf4cc41fb, (q31_t)0x7f81b88a, (q31_t)0xf4c5ffab, (q31_t)0x7f812b4f, (q31_t)0xf4bfbd63, + (q31_t)0x7f809dc5, (q31_t)0xf4b97b21, (q31_t)0x7f800fed, (q31_t)0xf4b338e7, (q31_t)0x7f7f81c6, (q31_t)0xf4acf6b3, (q31_t)0x7f7ef350, (q31_t)0xf4a6b486, + (q31_t)0x7f7e648c, (q31_t)0xf4a07261, (q31_t)0x7f7dd579, (q31_t)0xf49a3042, (q31_t)0x7f7d4617, (q31_t)0xf493ee2b, (q31_t)0x7f7cb667, (q31_t)0xf48dac1a, + (q31_t)0x7f7c2668, (q31_t)0xf4876a10, (q31_t)0x7f7b961b, (q31_t)0xf481280e, (q31_t)0x7f7b057e, (q31_t)0xf47ae613, (q31_t)0x7f7a7494, (q31_t)0xf474a41f, + (q31_t)0x7f79e35a, (q31_t)0xf46e6231, (q31_t)0x7f7951d2, (q31_t)0xf468204b, (q31_t)0x7f78bffb, (q31_t)0xf461de6d, (q31_t)0x7f782dd6, (q31_t)0xf45b9c95, + (q31_t)0x7f779b62, (q31_t)0xf4555ac5, (q31_t)0x7f77089f, (q31_t)0xf44f18fb, (q31_t)0x7f76758e, (q31_t)0xf448d739, (q31_t)0x7f75e22e, (q31_t)0xf442957e, + (q31_t)0x7f754e80, (q31_t)0xf43c53cb, (q31_t)0x7f74ba83, (q31_t)0xf436121e, (q31_t)0x7f742637, (q31_t)0xf42fd079, (q31_t)0x7f73919d, (q31_t)0xf4298edc, + (q31_t)0x7f72fcb4, (q31_t)0xf4234d45, (q31_t)0x7f72677c, (q31_t)0xf41d0bb6, (q31_t)0x7f71d1f6, (q31_t)0xf416ca2e, (q31_t)0x7f713c21, (q31_t)0xf41088ae, + (q31_t)0x7f70a5fe, (q31_t)0xf40a4735, (q31_t)0x7f700f8c, (q31_t)0xf40405c3, (q31_t)0x7f6f78cb, (q31_t)0xf3fdc459, (q31_t)0x7f6ee1bc, (q31_t)0xf3f782f6, + (q31_t)0x7f6e4a5e, (q31_t)0xf3f1419a, (q31_t)0x7f6db2b1, (q31_t)0xf3eb0046, (q31_t)0x7f6d1ab6, (q31_t)0xf3e4bef9, (q31_t)0x7f6c826d, (q31_t)0xf3de7db4, + (q31_t)0x7f6be9d4, (q31_t)0xf3d83c77, (q31_t)0x7f6b50ed, (q31_t)0xf3d1fb40, (q31_t)0x7f6ab7b8, (q31_t)0xf3cbba12, (q31_t)0x7f6a1e34, (q31_t)0xf3c578eb, + (q31_t)0x7f698461, (q31_t)0xf3bf37cb, (q31_t)0x7f68ea40, (q31_t)0xf3b8f6b3, (q31_t)0x7f684fd0, (q31_t)0xf3b2b5a3, (q31_t)0x7f67b512, (q31_t)0xf3ac749a, + (q31_t)0x7f671a05, (q31_t)0xf3a63398, (q31_t)0x7f667ea9, (q31_t)0xf39ff29f, (q31_t)0x7f65e2ff, (q31_t)0xf399b1ad, (q31_t)0x7f654706, (q31_t)0xf39370c2, + (q31_t)0x7f64aabf, (q31_t)0xf38d2fe0, (q31_t)0x7f640e29, (q31_t)0xf386ef05, (q31_t)0x7f637144, (q31_t)0xf380ae31, (q31_t)0x7f62d411, (q31_t)0xf37a6d66, + (q31_t)0x7f62368f, (q31_t)0xf3742ca2, (q31_t)0x7f6198bf, (q31_t)0xf36debe6, (q31_t)0x7f60faa0, (q31_t)0xf367ab31, (q31_t)0x7f605c33, (q31_t)0xf3616a85, + (q31_t)0x7f5fbd77, (q31_t)0xf35b29e0, (q31_t)0x7f5f1e6c, (q31_t)0xf354e943, (q31_t)0x7f5e7f13, (q31_t)0xf34ea8ae, (q31_t)0x7f5ddf6b, (q31_t)0xf3486820, + (q31_t)0x7f5d3f75, (q31_t)0xf342279b, (q31_t)0x7f5c9f30, (q31_t)0xf33be71d, (q31_t)0x7f5bfe9d, (q31_t)0xf335a6a7, (q31_t)0x7f5b5dbb, (q31_t)0xf32f6639, + (q31_t)0x7f5abc8a, (q31_t)0xf32925d3, (q31_t)0x7f5a1b0b, (q31_t)0xf322e575, (q31_t)0x7f59793e, (q31_t)0xf31ca51f, (q31_t)0x7f58d721, (q31_t)0xf31664d1, + (q31_t)0x7f5834b7, (q31_t)0xf310248a, (q31_t)0x7f5791fd, (q31_t)0xf309e44c, (q31_t)0x7f56eef5, (q31_t)0xf303a416, (q31_t)0x7f564b9f, (q31_t)0xf2fd63e8, + (q31_t)0x7f55a7fa, (q31_t)0xf2f723c1, (q31_t)0x7f550407, (q31_t)0xf2f0e3a3, (q31_t)0x7f545fc5, (q31_t)0xf2eaa38d, (q31_t)0x7f53bb34, (q31_t)0xf2e4637f, + (q31_t)0x7f531655, (q31_t)0xf2de2379, (q31_t)0x7f527127, (q31_t)0xf2d7e37b, (q31_t)0x7f51cbab, (q31_t)0xf2d1a385, (q31_t)0x7f5125e0, (q31_t)0xf2cb6398, + (q31_t)0x7f507fc7, (q31_t)0xf2c523b2, (q31_t)0x7f4fd95f, (q31_t)0xf2bee3d5, (q31_t)0x7f4f32a9, (q31_t)0xf2b8a400, (q31_t)0x7f4e8ba4, (q31_t)0xf2b26433, + (q31_t)0x7f4de451, (q31_t)0xf2ac246e, (q31_t)0x7f4d3caf, (q31_t)0xf2a5e4b1, (q31_t)0x7f4c94be, (q31_t)0xf29fa4fd, (q31_t)0x7f4bec7f, (q31_t)0xf2996551, + (q31_t)0x7f4b43f2, (q31_t)0xf29325ad, (q31_t)0x7f4a9b16, (q31_t)0xf28ce612, (q31_t)0x7f49f1eb, (q31_t)0xf286a67e, (q31_t)0x7f494872, (q31_t)0xf28066f4, + (q31_t)0x7f489eaa, (q31_t)0xf27a2771, (q31_t)0x7f47f494, (q31_t)0xf273e7f7, (q31_t)0x7f474a30, (q31_t)0xf26da885, (q31_t)0x7f469f7d, (q31_t)0xf267691b, + (q31_t)0x7f45f47b, (q31_t)0xf26129ba, (q31_t)0x7f45492b, (q31_t)0xf25aea61, (q31_t)0x7f449d8c, (q31_t)0xf254ab11, (q31_t)0x7f43f19f, (q31_t)0xf24e6bc9, + (q31_t)0x7f434563, (q31_t)0xf2482c8a, (q31_t)0x7f4298d9, (q31_t)0xf241ed53, (q31_t)0x7f41ec01, (q31_t)0xf23bae24, (q31_t)0x7f413ed9, (q31_t)0xf2356efe, + (q31_t)0x7f409164, (q31_t)0xf22f2fe1, (q31_t)0x7f3fe3a0, (q31_t)0xf228f0cc, (q31_t)0x7f3f358d, (q31_t)0xf222b1c0, (q31_t)0x7f3e872c, (q31_t)0xf21c72bc, + (q31_t)0x7f3dd87c, (q31_t)0xf21633c0, (q31_t)0x7f3d297e, (q31_t)0xf20ff4ce, (q31_t)0x7f3c7a31, (q31_t)0xf209b5e4, (q31_t)0x7f3bca96, (q31_t)0xf2037702, + (q31_t)0x7f3b1aad, (q31_t)0xf1fd3829, (q31_t)0x7f3a6a75, (q31_t)0xf1f6f959, (q31_t)0x7f39b9ee, (q31_t)0xf1f0ba91, (q31_t)0x7f390919, (q31_t)0xf1ea7bd2, + (q31_t)0x7f3857f6, (q31_t)0xf1e43d1c, (q31_t)0x7f37a684, (q31_t)0xf1ddfe6f, (q31_t)0x7f36f4c3, (q31_t)0xf1d7bfca, (q31_t)0x7f3642b4, (q31_t)0xf1d1812e, + (q31_t)0x7f359057, (q31_t)0xf1cb429a, (q31_t)0x7f34ddab, (q31_t)0xf1c50410, (q31_t)0x7f342ab1, (q31_t)0xf1bec58e, (q31_t)0x7f337768, (q31_t)0xf1b88715, + (q31_t)0x7f32c3d1, (q31_t)0xf1b248a5, (q31_t)0x7f320feb, (q31_t)0xf1ac0a3e, (q31_t)0x7f315bb7, (q31_t)0xf1a5cbdf, (q31_t)0x7f30a734, (q31_t)0xf19f8d89, + (q31_t)0x7f2ff263, (q31_t)0xf1994f3d, (q31_t)0x7f2f3d44, (q31_t)0xf19310f9, (q31_t)0x7f2e87d6, (q31_t)0xf18cd2be, (q31_t)0x7f2dd219, (q31_t)0xf186948c, + (q31_t)0x7f2d1c0e, (q31_t)0xf1805662, (q31_t)0x7f2c65b5, (q31_t)0xf17a1842, (q31_t)0x7f2baf0d, (q31_t)0xf173da2b, (q31_t)0x7f2af817, (q31_t)0xf16d9c1d, + (q31_t)0x7f2a40d2, (q31_t)0xf1675e17, (q31_t)0x7f29893f, (q31_t)0xf161201b, (q31_t)0x7f28d15d, (q31_t)0xf15ae228, (q31_t)0x7f28192d, (q31_t)0xf154a43d, + (q31_t)0x7f2760af, (q31_t)0xf14e665c, (q31_t)0x7f26a7e2, (q31_t)0xf1482884, (q31_t)0x7f25eec7, (q31_t)0xf141eab5, (q31_t)0x7f25355d, (q31_t)0xf13bacef, + (q31_t)0x7f247ba5, (q31_t)0xf1356f32, (q31_t)0x7f23c19e, (q31_t)0xf12f317e, (q31_t)0x7f230749, (q31_t)0xf128f3d4, (q31_t)0x7f224ca6, (q31_t)0xf122b632, + (q31_t)0x7f2191b4, (q31_t)0xf11c789a, (q31_t)0x7f20d674, (q31_t)0xf1163b0b, (q31_t)0x7f201ae5, (q31_t)0xf10ffd85, (q31_t)0x7f1f5f08, (q31_t)0xf109c009, + (q31_t)0x7f1ea2dc, (q31_t)0xf1038295, (q31_t)0x7f1de662, (q31_t)0xf0fd452b, (q31_t)0x7f1d299a, (q31_t)0xf0f707ca, (q31_t)0x7f1c6c83, (q31_t)0xf0f0ca72, + (q31_t)0x7f1baf1e, (q31_t)0xf0ea8d24, (q31_t)0x7f1af16a, (q31_t)0xf0e44fdf, (q31_t)0x7f1a3368, (q31_t)0xf0de12a3, (q31_t)0x7f197518, (q31_t)0xf0d7d571, + (q31_t)0x7f18b679, (q31_t)0xf0d19848, (q31_t)0x7f17f78c, (q31_t)0xf0cb5b28, (q31_t)0x7f173850, (q31_t)0xf0c51e12, (q31_t)0x7f1678c6, (q31_t)0xf0bee105, + (q31_t)0x7f15b8ee, (q31_t)0xf0b8a401, (q31_t)0x7f14f8c7, (q31_t)0xf0b26707, (q31_t)0x7f143852, (q31_t)0xf0ac2a16, (q31_t)0x7f13778e, (q31_t)0xf0a5ed2f, + (q31_t)0x7f12b67c, (q31_t)0xf09fb051, (q31_t)0x7f11f51c, (q31_t)0xf099737d, (q31_t)0x7f11336d, (q31_t)0xf09336b2, (q31_t)0x7f107170, (q31_t)0xf08cf9f1, + (q31_t)0x7f0faf25, (q31_t)0xf086bd39, (q31_t)0x7f0eec8b, (q31_t)0xf080808b, (q31_t)0x7f0e29a3, (q31_t)0xf07a43e7, (q31_t)0x7f0d666c, (q31_t)0xf074074c, + (q31_t)0x7f0ca2e7, (q31_t)0xf06dcaba, (q31_t)0x7f0bdf14, (q31_t)0xf0678e32, (q31_t)0x7f0b1af2, (q31_t)0xf06151b4, (q31_t)0x7f0a5682, (q31_t)0xf05b1540, + (q31_t)0x7f0991c4, (q31_t)0xf054d8d5, (q31_t)0x7f08ccb7, (q31_t)0xf04e9c73, (q31_t)0x7f08075c, (q31_t)0xf048601c, (q31_t)0x7f0741b2, (q31_t)0xf04223ce, + (q31_t)0x7f067bba, (q31_t)0xf03be78a, (q31_t)0x7f05b574, (q31_t)0xf035ab4f, (q31_t)0x7f04eedf, (q31_t)0xf02f6f1f, (q31_t)0x7f0427fc, (q31_t)0xf02932f8, + (q31_t)0x7f0360cb, (q31_t)0xf022f6da, (q31_t)0x7f02994b, (q31_t)0xf01cbac7, (q31_t)0x7f01d17d, (q31_t)0xf0167ebd, (q31_t)0x7f010961, (q31_t)0xf01042be, + (q31_t)0x7f0040f6, (q31_t)0xf00a06c8, (q31_t)0x7eff783d, (q31_t)0xf003cadc, (q31_t)0x7efeaf36, (q31_t)0xeffd8ef9, (q31_t)0x7efde5e0, (q31_t)0xeff75321, + (q31_t)0x7efd1c3c, (q31_t)0xeff11753, (q31_t)0x7efc524a, (q31_t)0xefeadb8e, (q31_t)0x7efb8809, (q31_t)0xefe49fd3, (q31_t)0x7efabd7a, (q31_t)0xefde6423, + (q31_t)0x7ef9f29d, (q31_t)0xefd8287c, (q31_t)0x7ef92771, (q31_t)0xefd1ecdf, (q31_t)0x7ef85bf7, (q31_t)0xefcbb14c, (q31_t)0x7ef7902f, (q31_t)0xefc575c3, + (q31_t)0x7ef6c418, (q31_t)0xefbf3a45, (q31_t)0x7ef5f7b3, (q31_t)0xefb8fed0, (q31_t)0x7ef52b00, (q31_t)0xefb2c365, (q31_t)0x7ef45dfe, (q31_t)0xefac8804, + (q31_t)0x7ef390ae, (q31_t)0xefa64cae, (q31_t)0x7ef2c310, (q31_t)0xefa01161, (q31_t)0x7ef1f524, (q31_t)0xef99d61f, (q31_t)0x7ef126e9, (q31_t)0xef939ae6, + (q31_t)0x7ef05860, (q31_t)0xef8d5fb8, (q31_t)0x7eef8988, (q31_t)0xef872494, (q31_t)0x7eeeba62, (q31_t)0xef80e97a, (q31_t)0x7eedeaee, (q31_t)0xef7aae6b, + (q31_t)0x7eed1b2c, (q31_t)0xef747365, (q31_t)0x7eec4b1b, (q31_t)0xef6e386a, (q31_t)0x7eeb7abc, (q31_t)0xef67fd79, (q31_t)0x7eeaaa0f, (q31_t)0xef61c292, + (q31_t)0x7ee9d914, (q31_t)0xef5b87b5, (q31_t)0x7ee907ca, (q31_t)0xef554ce3, (q31_t)0x7ee83632, (q31_t)0xef4f121b, (q31_t)0x7ee7644c, (q31_t)0xef48d75d, + (q31_t)0x7ee69217, (q31_t)0xef429caa, (q31_t)0x7ee5bf94, (q31_t)0xef3c6201, (q31_t)0x7ee4ecc3, (q31_t)0xef362762, (q31_t)0x7ee419a3, (q31_t)0xef2feccd, + (q31_t)0x7ee34636, (q31_t)0xef29b243, (q31_t)0x7ee2727a, (q31_t)0xef2377c4, (q31_t)0x7ee19e6f, (q31_t)0xef1d3d4e, (q31_t)0x7ee0ca17, (q31_t)0xef1702e4, + (q31_t)0x7edff570, (q31_t)0xef10c883, (q31_t)0x7edf207b, (q31_t)0xef0a8e2d, (q31_t)0x7ede4b38, (q31_t)0xef0453e2, (q31_t)0x7edd75a6, (q31_t)0xeefe19a1, + (q31_t)0x7edc9fc6, (q31_t)0xeef7df6a, (q31_t)0x7edbc998, (q31_t)0xeef1a53e, (q31_t)0x7edaf31c, (q31_t)0xeeeb6b1c, (q31_t)0x7eda1c51, (q31_t)0xeee53105, + (q31_t)0x7ed94538, (q31_t)0xeedef6f9, (q31_t)0x7ed86dd1, (q31_t)0xeed8bcf7, (q31_t)0x7ed7961c, (q31_t)0xeed28300, (q31_t)0x7ed6be18, (q31_t)0xeecc4913, + (q31_t)0x7ed5e5c6, (q31_t)0xeec60f31, (q31_t)0x7ed50d26, (q31_t)0xeebfd55a, (q31_t)0x7ed43438, (q31_t)0xeeb99b8d, (q31_t)0x7ed35afb, (q31_t)0xeeb361cb, + (q31_t)0x7ed28171, (q31_t)0xeead2813, (q31_t)0x7ed1a798, (q31_t)0xeea6ee66, (q31_t)0x7ed0cd70, (q31_t)0xeea0b4c4, (q31_t)0x7ecff2fb, (q31_t)0xee9a7b2d, + (q31_t)0x7ecf1837, (q31_t)0xee9441a0, (q31_t)0x7ece3d25, (q31_t)0xee8e081e, (q31_t)0x7ecd61c5, (q31_t)0xee87cea7, (q31_t)0x7ecc8617, (q31_t)0xee81953b, + (q31_t)0x7ecbaa1a, (q31_t)0xee7b5bd9, (q31_t)0x7ecacdd0, (q31_t)0xee752283, (q31_t)0x7ec9f137, (q31_t)0xee6ee937, (q31_t)0x7ec9144f, (q31_t)0xee68aff6, + (q31_t)0x7ec8371a, (q31_t)0xee6276bf, (q31_t)0x7ec75996, (q31_t)0xee5c3d94, (q31_t)0x7ec67bc5, (q31_t)0xee560473, (q31_t)0x7ec59da5, (q31_t)0xee4fcb5e, + (q31_t)0x7ec4bf36, (q31_t)0xee499253, (q31_t)0x7ec3e07a, (q31_t)0xee435953, (q31_t)0x7ec3016f, (q31_t)0xee3d205e, (q31_t)0x7ec22217, (q31_t)0xee36e775, + (q31_t)0x7ec14270, (q31_t)0xee30ae96, (q31_t)0x7ec0627a, (q31_t)0xee2a75c2, (q31_t)0x7ebf8237, (q31_t)0xee243cf9, (q31_t)0x7ebea1a6, (q31_t)0xee1e043b, + (q31_t)0x7ebdc0c6, (q31_t)0xee17cb88, (q31_t)0x7ebcdf98, (q31_t)0xee1192e0, (q31_t)0x7ebbfe1c, (q31_t)0xee0b5a43, (q31_t)0x7ebb1c52, (q31_t)0xee0521b2, + (q31_t)0x7eba3a39, (q31_t)0xedfee92b, (q31_t)0x7eb957d2, (q31_t)0xedf8b0b0, (q31_t)0x7eb8751e, (q31_t)0xedf2783f, (q31_t)0x7eb7921b, (q31_t)0xedec3fda, + (q31_t)0x7eb6aeca, (q31_t)0xede60780, (q31_t)0x7eb5cb2a, (q31_t)0xeddfcf31, (q31_t)0x7eb4e73d, (q31_t)0xedd996ed, (q31_t)0x7eb40301, (q31_t)0xedd35eb5, + (q31_t)0x7eb31e78, (q31_t)0xedcd2687, (q31_t)0x7eb239a0, (q31_t)0xedc6ee65, (q31_t)0x7eb1547a, (q31_t)0xedc0b64e, (q31_t)0x7eb06f05, (q31_t)0xedba7e43, + (q31_t)0x7eaf8943, (q31_t)0xedb44642, (q31_t)0x7eaea333, (q31_t)0xedae0e4d, (q31_t)0x7eadbcd4, (q31_t)0xeda7d664, (q31_t)0x7eacd627, (q31_t)0xeda19e85, + (q31_t)0x7eabef2c, (q31_t)0xed9b66b2, (q31_t)0x7eab07e3, (q31_t)0xed952eea, (q31_t)0x7eaa204c, (q31_t)0xed8ef72e, (q31_t)0x7ea93867, (q31_t)0xed88bf7d, + (q31_t)0x7ea85033, (q31_t)0xed8287d7, (q31_t)0x7ea767b2, (q31_t)0xed7c503d, (q31_t)0x7ea67ee2, (q31_t)0xed7618ae, (q31_t)0x7ea595c4, (q31_t)0xed6fe12b, + (q31_t)0x7ea4ac58, (q31_t)0xed69a9b3, (q31_t)0x7ea3c29e, (q31_t)0xed637246, (q31_t)0x7ea2d896, (q31_t)0xed5d3ae5, (q31_t)0x7ea1ee3f, (q31_t)0xed570390, + (q31_t)0x7ea1039b, (q31_t)0xed50cc46, (q31_t)0x7ea018a8, (q31_t)0xed4a9507, (q31_t)0x7e9f2d68, (q31_t)0xed445dd5, (q31_t)0x7e9e41d9, (q31_t)0xed3e26ad, + (q31_t)0x7e9d55fc, (q31_t)0xed37ef91, (q31_t)0x7e9c69d1, (q31_t)0xed31b881, (q31_t)0x7e9b7d58, (q31_t)0xed2b817d, (q31_t)0x7e9a9091, (q31_t)0xed254a84, + (q31_t)0x7e99a37c, (q31_t)0xed1f1396, (q31_t)0x7e98b618, (q31_t)0xed18dcb5, (q31_t)0x7e97c867, (q31_t)0xed12a5df, (q31_t)0x7e96da67, (q31_t)0xed0c6f14, + (q31_t)0x7e95ec1a, (q31_t)0xed063856, (q31_t)0x7e94fd7e, (q31_t)0xed0001a3, (q31_t)0x7e940e94, (q31_t)0xecf9cafb, (q31_t)0x7e931f5c, (q31_t)0xecf39460, + (q31_t)0x7e922fd6, (q31_t)0xeced5dd0, (q31_t)0x7e914002, (q31_t)0xece7274c, (q31_t)0x7e904fe0, (q31_t)0xece0f0d4, (q31_t)0x7e8f5f70, (q31_t)0xecdaba67, + (q31_t)0x7e8e6eb2, (q31_t)0xecd48407, (q31_t)0x7e8d7da6, (q31_t)0xecce4db2, (q31_t)0x7e8c8c4b, (q31_t)0xecc81769, (q31_t)0x7e8b9aa3, (q31_t)0xecc1e12c, + (q31_t)0x7e8aa8ac, (q31_t)0xecbbaafb, (q31_t)0x7e89b668, (q31_t)0xecb574d5, (q31_t)0x7e88c3d5, (q31_t)0xecaf3ebc, (q31_t)0x7e87d0f5, (q31_t)0xeca908ae, + (q31_t)0x7e86ddc6, (q31_t)0xeca2d2ad, (q31_t)0x7e85ea49, (q31_t)0xec9c9cb7, (q31_t)0x7e84f67e, (q31_t)0xec9666cd, (q31_t)0x7e840265, (q31_t)0xec9030f0, + (q31_t)0x7e830dff, (q31_t)0xec89fb1e, (q31_t)0x7e82194a, (q31_t)0xec83c558, (q31_t)0x7e812447, (q31_t)0xec7d8f9e, (q31_t)0x7e802ef6, (q31_t)0xec7759f1, + (q31_t)0x7e7f3957, (q31_t)0xec71244f, (q31_t)0x7e7e436a, (q31_t)0xec6aeeba, (q31_t)0x7e7d4d2f, (q31_t)0xec64b930, (q31_t)0x7e7c56a5, (q31_t)0xec5e83b3, + (q31_t)0x7e7b5fce, (q31_t)0xec584e41, (q31_t)0x7e7a68a9, (q31_t)0xec5218dc, (q31_t)0x7e797136, (q31_t)0xec4be383, (q31_t)0x7e787975, (q31_t)0xec45ae36, + (q31_t)0x7e778166, (q31_t)0xec3f78f6, (q31_t)0x7e768908, (q31_t)0xec3943c1, (q31_t)0x7e75905d, (q31_t)0xec330e99, (q31_t)0x7e749764, (q31_t)0xec2cd97d, + (q31_t)0x7e739e1d, (q31_t)0xec26a46d, (q31_t)0x7e72a488, (q31_t)0xec206f69, (q31_t)0x7e71aaa4, (q31_t)0xec1a3a72, (q31_t)0x7e70b073, (q31_t)0xec140587, + (q31_t)0x7e6fb5f4, (q31_t)0xec0dd0a8, (q31_t)0x7e6ebb27, (q31_t)0xec079bd6, (q31_t)0x7e6dc00c, (q31_t)0xec01670f, (q31_t)0x7e6cc4a2, (q31_t)0xebfb3256, + (q31_t)0x7e6bc8eb, (q31_t)0xebf4fda8, (q31_t)0x7e6acce6, (q31_t)0xebeec907, (q31_t)0x7e69d093, (q31_t)0xebe89472, (q31_t)0x7e68d3f2, (q31_t)0xebe25fea, + (q31_t)0x7e67d703, (q31_t)0xebdc2b6e, (q31_t)0x7e66d9c6, (q31_t)0xebd5f6fe, (q31_t)0x7e65dc3b, (q31_t)0xebcfc29b, (q31_t)0x7e64de62, (q31_t)0xebc98e45, + (q31_t)0x7e63e03b, (q31_t)0xebc359fb, (q31_t)0x7e62e1c6, (q31_t)0xebbd25bd, (q31_t)0x7e61e303, (q31_t)0xebb6f18c, (q31_t)0x7e60e3f2, (q31_t)0xebb0bd67, + (q31_t)0x7e5fe493, (q31_t)0xebaa894f, (q31_t)0x7e5ee4e6, (q31_t)0xeba45543, (q31_t)0x7e5de4ec, (q31_t)0xeb9e2144, (q31_t)0x7e5ce4a3, (q31_t)0xeb97ed52, + (q31_t)0x7e5be40c, (q31_t)0xeb91b96c, (q31_t)0x7e5ae328, (q31_t)0xeb8b8593, (q31_t)0x7e59e1f5, (q31_t)0xeb8551c6, (q31_t)0x7e58e075, (q31_t)0xeb7f1e06, + (q31_t)0x7e57dea7, (q31_t)0xeb78ea52, (q31_t)0x7e56dc8a, (q31_t)0xeb72b6ac, (q31_t)0x7e55da20, (q31_t)0xeb6c8312, (q31_t)0x7e54d768, (q31_t)0xeb664f84, + (q31_t)0x7e53d462, (q31_t)0xeb601c04, (q31_t)0x7e52d10e, (q31_t)0xeb59e890, (q31_t)0x7e51cd6c, (q31_t)0xeb53b529, (q31_t)0x7e50c97c, (q31_t)0xeb4d81ce, + (q31_t)0x7e4fc53e, (q31_t)0xeb474e81, (q31_t)0x7e4ec0b2, (q31_t)0xeb411b40, (q31_t)0x7e4dbbd9, (q31_t)0xeb3ae80c, (q31_t)0x7e4cb6b1, (q31_t)0xeb34b4e4, + (q31_t)0x7e4bb13c, (q31_t)0xeb2e81ca, (q31_t)0x7e4aab78, (q31_t)0xeb284ebc, (q31_t)0x7e49a567, (q31_t)0xeb221bbb, (q31_t)0x7e489f08, (q31_t)0xeb1be8c8, + (q31_t)0x7e47985b, (q31_t)0xeb15b5e1, (q31_t)0x7e469160, (q31_t)0xeb0f8307, (q31_t)0x7e458a17, (q31_t)0xeb095039, (q31_t)0x7e448281, (q31_t)0xeb031d79, + (q31_t)0x7e437a9c, (q31_t)0xeafceac6, (q31_t)0x7e427269, (q31_t)0xeaf6b81f, (q31_t)0x7e4169e9, (q31_t)0xeaf08586, (q31_t)0x7e40611b, (q31_t)0xeaea52fa, + (q31_t)0x7e3f57ff, (q31_t)0xeae4207a, (q31_t)0x7e3e4e95, (q31_t)0xeaddee08, (q31_t)0x7e3d44dd, (q31_t)0xead7bba3, (q31_t)0x7e3c3ad7, (q31_t)0xead1894b, + (q31_t)0x7e3b3083, (q31_t)0xeacb56ff, (q31_t)0x7e3a25e2, (q31_t)0xeac524c1, (q31_t)0x7e391af3, (q31_t)0xeabef290, (q31_t)0x7e380fb5, (q31_t)0xeab8c06c, + (q31_t)0x7e37042a, (q31_t)0xeab28e56, (q31_t)0x7e35f851, (q31_t)0xeaac5c4c, (q31_t)0x7e34ec2b, (q31_t)0xeaa62a4f, (q31_t)0x7e33dfb6, (q31_t)0xea9ff860, + (q31_t)0x7e32d2f4, (q31_t)0xea99c67e, (q31_t)0x7e31c5e3, (q31_t)0xea9394a9, (q31_t)0x7e30b885, (q31_t)0xea8d62e1, (q31_t)0x7e2faad9, (q31_t)0xea873127, + (q31_t)0x7e2e9cdf, (q31_t)0xea80ff7a, (q31_t)0x7e2d8e97, (q31_t)0xea7acdda, (q31_t)0x7e2c8002, (q31_t)0xea749c47, (q31_t)0x7e2b711f, (q31_t)0xea6e6ac2, + (q31_t)0x7e2a61ed, (q31_t)0xea683949, (q31_t)0x7e29526e, (q31_t)0xea6207df, (q31_t)0x7e2842a2, (q31_t)0xea5bd681, (q31_t)0x7e273287, (q31_t)0xea55a531, + (q31_t)0x7e26221f, (q31_t)0xea4f73ee, (q31_t)0x7e251168, (q31_t)0xea4942b9, (q31_t)0x7e240064, (q31_t)0xea431191, (q31_t)0x7e22ef12, (q31_t)0xea3ce077, + (q31_t)0x7e21dd73, (q31_t)0xea36af69, (q31_t)0x7e20cb85, (q31_t)0xea307e6a, (q31_t)0x7e1fb94a, (q31_t)0xea2a4d78, (q31_t)0x7e1ea6c1, (q31_t)0xea241c93, + (q31_t)0x7e1d93ea, (q31_t)0xea1debbb, (q31_t)0x7e1c80c5, (q31_t)0xea17baf2, (q31_t)0x7e1b6d53, (q31_t)0xea118a35, (q31_t)0x7e1a5992, (q31_t)0xea0b5987, + (q31_t)0x7e194584, (q31_t)0xea0528e5, (q31_t)0x7e183128, (q31_t)0xe9fef852, (q31_t)0x7e171c7f, (q31_t)0xe9f8c7cc, (q31_t)0x7e160787, (q31_t)0xe9f29753, + (q31_t)0x7e14f242, (q31_t)0xe9ec66e8, (q31_t)0x7e13dcaf, (q31_t)0xe9e6368b, (q31_t)0x7e12c6ce, (q31_t)0xe9e0063c, (q31_t)0x7e11b0a0, (q31_t)0xe9d9d5fa, + (q31_t)0x7e109a24, (q31_t)0xe9d3a5c5, (q31_t)0x7e0f835a, (q31_t)0xe9cd759f, (q31_t)0x7e0e6c42, (q31_t)0xe9c74586, (q31_t)0x7e0d54dc, (q31_t)0xe9c1157a, + (q31_t)0x7e0c3d29, (q31_t)0xe9bae57d, (q31_t)0x7e0b2528, (q31_t)0xe9b4b58d, (q31_t)0x7e0a0cd9, (q31_t)0xe9ae85ab, (q31_t)0x7e08f43d, (q31_t)0xe9a855d7, + (q31_t)0x7e07db52, (q31_t)0xe9a22610, (q31_t)0x7e06c21a, (q31_t)0xe99bf658, (q31_t)0x7e05a894, (q31_t)0xe995c6ad, (q31_t)0x7e048ec1, (q31_t)0xe98f9710, + (q31_t)0x7e0374a0, (q31_t)0xe9896781, (q31_t)0x7e025a31, (q31_t)0xe98337ff, (q31_t)0x7e013f74, (q31_t)0xe97d088c, (q31_t)0x7e00246a, (q31_t)0xe976d926, + (q31_t)0x7dff0911, (q31_t)0xe970a9ce, (q31_t)0x7dfded6c, (q31_t)0xe96a7a85, (q31_t)0x7dfcd178, (q31_t)0xe9644b49, (q31_t)0x7dfbb537, (q31_t)0xe95e1c1b, + (q31_t)0x7dfa98a8, (q31_t)0xe957ecfb, (q31_t)0x7df97bcb, (q31_t)0xe951bde9, (q31_t)0x7df85ea0, (q31_t)0xe94b8ee5, (q31_t)0x7df74128, (q31_t)0xe9455fef, + (q31_t)0x7df62362, (q31_t)0xe93f3107, (q31_t)0x7df5054f, (q31_t)0xe939022d, (q31_t)0x7df3e6ee, (q31_t)0xe932d361, (q31_t)0x7df2c83f, (q31_t)0xe92ca4a4, + (q31_t)0x7df1a942, (q31_t)0xe92675f4, (q31_t)0x7df089f8, (q31_t)0xe9204752, (q31_t)0x7def6a60, (q31_t)0xe91a18bf, (q31_t)0x7dee4a7a, (q31_t)0xe913ea39, + (q31_t)0x7ded2a47, (q31_t)0xe90dbbc2, (q31_t)0x7dec09c6, (q31_t)0xe9078d59, (q31_t)0x7deae8f7, (q31_t)0xe9015efe, (q31_t)0x7de9c7da, (q31_t)0xe8fb30b1, + (q31_t)0x7de8a670, (q31_t)0xe8f50273, (q31_t)0x7de784b9, (q31_t)0xe8eed443, (q31_t)0x7de662b3, (q31_t)0xe8e8a621, (q31_t)0x7de54060, (q31_t)0xe8e2780d, + (q31_t)0x7de41dc0, (q31_t)0xe8dc4a07, (q31_t)0x7de2fad1, (q31_t)0xe8d61c10, (q31_t)0x7de1d795, (q31_t)0xe8cfee27, (q31_t)0x7de0b40b, (q31_t)0xe8c9c04c, + (q31_t)0x7ddf9034, (q31_t)0xe8c39280, (q31_t)0x7dde6c0f, (q31_t)0xe8bd64c2, (q31_t)0x7ddd479d, (q31_t)0xe8b73712, (q31_t)0x7ddc22dc, (q31_t)0xe8b10971, + (q31_t)0x7ddafdce, (q31_t)0xe8aadbde, (q31_t)0x7dd9d873, (q31_t)0xe8a4ae59, (q31_t)0x7dd8b2ca, (q31_t)0xe89e80e3, (q31_t)0x7dd78cd3, (q31_t)0xe898537b, + (q31_t)0x7dd6668f, (q31_t)0xe8922622, (q31_t)0x7dd53ffc, (q31_t)0xe88bf8d7, (q31_t)0x7dd4191d, (q31_t)0xe885cb9a, (q31_t)0x7dd2f1f0, (q31_t)0xe87f9e6c, + (q31_t)0x7dd1ca75, (q31_t)0xe879714d, (q31_t)0x7dd0a2ac, (q31_t)0xe873443c, (q31_t)0x7dcf7a96, (q31_t)0xe86d173a, (q31_t)0x7dce5232, (q31_t)0xe866ea46, + (q31_t)0x7dcd2981, (q31_t)0xe860bd61, (q31_t)0x7dcc0082, (q31_t)0xe85a908a, (q31_t)0x7dcad736, (q31_t)0xe85463c2, (q31_t)0x7dc9ad9c, (q31_t)0xe84e3708, + (q31_t)0x7dc883b4, (q31_t)0xe8480a5d, (q31_t)0x7dc7597f, (q31_t)0xe841ddc1, (q31_t)0x7dc62efc, (q31_t)0xe83bb133, (q31_t)0x7dc5042b, (q31_t)0xe83584b4, + (q31_t)0x7dc3d90d, (q31_t)0xe82f5844, (q31_t)0x7dc2ada2, (q31_t)0xe8292be3, (q31_t)0x7dc181e8, (q31_t)0xe822ff90, (q31_t)0x7dc055e2, (q31_t)0xe81cd34b, + (q31_t)0x7dbf298d, (q31_t)0xe816a716, (q31_t)0x7dbdfceb, (q31_t)0xe8107aef, (q31_t)0x7dbccffc, (q31_t)0xe80a4ed7, (q31_t)0x7dbba2bf, (q31_t)0xe80422ce, + (q31_t)0x7dba7534, (q31_t)0xe7fdf6d4, (q31_t)0x7db9475c, (q31_t)0xe7f7cae8, (q31_t)0x7db81936, (q31_t)0xe7f19f0c, (q31_t)0x7db6eac3, (q31_t)0xe7eb733e, + (q31_t)0x7db5bc02, (q31_t)0xe7e5477f, (q31_t)0x7db48cf4, (q31_t)0xe7df1bcf, (q31_t)0x7db35d98, (q31_t)0xe7d8f02d, (q31_t)0x7db22def, (q31_t)0xe7d2c49b, + (q31_t)0x7db0fdf8, (q31_t)0xe7cc9917, (q31_t)0x7dafcdb3, (q31_t)0xe7c66da3, (q31_t)0x7dae9d21, (q31_t)0xe7c0423d, (q31_t)0x7dad6c42, (q31_t)0xe7ba16e7, + (q31_t)0x7dac3b15, (q31_t)0xe7b3eb9f, (q31_t)0x7dab099a, (q31_t)0xe7adc066, (q31_t)0x7da9d7d2, (q31_t)0xe7a7953d, (q31_t)0x7da8a5bc, (q31_t)0xe7a16a22, + (q31_t)0x7da77359, (q31_t)0xe79b3f16, (q31_t)0x7da640a9, (q31_t)0xe795141a, (q31_t)0x7da50dab, (q31_t)0xe78ee92c, (q31_t)0x7da3da5f, (q31_t)0xe788be4e, + (q31_t)0x7da2a6c6, (q31_t)0xe782937e, (q31_t)0x7da172df, (q31_t)0xe77c68be, (q31_t)0x7da03eab, (q31_t)0xe7763e0d, (q31_t)0x7d9f0a29, (q31_t)0xe770136b, + (q31_t)0x7d9dd55a, (q31_t)0xe769e8d8, (q31_t)0x7d9ca03e, (q31_t)0xe763be55, (q31_t)0x7d9b6ad3, (q31_t)0xe75d93e0, (q31_t)0x7d9a351c, (q31_t)0xe757697b, + (q31_t)0x7d98ff17, (q31_t)0xe7513f25, (q31_t)0x7d97c8c4, (q31_t)0xe74b14de, (q31_t)0x7d969224, (q31_t)0xe744eaa6, (q31_t)0x7d955b37, (q31_t)0xe73ec07e, + (q31_t)0x7d9423fc, (q31_t)0xe7389665, (q31_t)0x7d92ec73, (q31_t)0xe7326c5b, (q31_t)0x7d91b49e, (q31_t)0xe72c4260, (q31_t)0x7d907c7a, (q31_t)0xe7261875, + (q31_t)0x7d8f4409, (q31_t)0xe71fee99, (q31_t)0x7d8e0b4b, (q31_t)0xe719c4cd, (q31_t)0x7d8cd240, (q31_t)0xe7139b10, (q31_t)0x7d8b98e6, (q31_t)0xe70d7162, + (q31_t)0x7d8a5f40, (q31_t)0xe70747c4, (q31_t)0x7d89254c, (q31_t)0xe7011e35, (q31_t)0x7d87eb0a, (q31_t)0xe6faf4b5, (q31_t)0x7d86b07c, (q31_t)0xe6f4cb45, + (q31_t)0x7d85759f, (q31_t)0xe6eea1e4, (q31_t)0x7d843a76, (q31_t)0xe6e87893, (q31_t)0x7d82fefe, (q31_t)0xe6e24f51, (q31_t)0x7d81c33a, (q31_t)0xe6dc261f, + (q31_t)0x7d808728, (q31_t)0xe6d5fcfc, (q31_t)0x7d7f4ac8, (q31_t)0xe6cfd3e9, (q31_t)0x7d7e0e1c, (q31_t)0xe6c9aae5, (q31_t)0x7d7cd121, (q31_t)0xe6c381f1, + (q31_t)0x7d7b93da, (q31_t)0xe6bd590d, (q31_t)0x7d7a5645, (q31_t)0xe6b73038, (q31_t)0x7d791862, (q31_t)0xe6b10772, (q31_t)0x7d77da32, (q31_t)0xe6aadebc, + (q31_t)0x7d769bb5, (q31_t)0xe6a4b616, (q31_t)0x7d755cea, (q31_t)0xe69e8d80, (q31_t)0x7d741dd2, (q31_t)0xe69864f9, (q31_t)0x7d72de6d, (q31_t)0xe6923c82, + (q31_t)0x7d719eba, (q31_t)0xe68c141a, (q31_t)0x7d705eba, (q31_t)0xe685ebc2, (q31_t)0x7d6f1e6c, (q31_t)0xe67fc37a, (q31_t)0x7d6dddd2, (q31_t)0xe6799b42, + (q31_t)0x7d6c9ce9, (q31_t)0xe6737319, (q31_t)0x7d6b5bb4, (q31_t)0xe66d4b01, (q31_t)0x7d6a1a31, (q31_t)0xe66722f7, (q31_t)0x7d68d860, (q31_t)0xe660fafe, + (q31_t)0x7d679642, (q31_t)0xe65ad315, (q31_t)0x7d6653d7, (q31_t)0xe654ab3b, (q31_t)0x7d65111f, (q31_t)0xe64e8371, (q31_t)0x7d63ce19, (q31_t)0xe6485bb7, + (q31_t)0x7d628ac6, (q31_t)0xe642340d, (q31_t)0x7d614725, (q31_t)0xe63c0c73, (q31_t)0x7d600338, (q31_t)0xe635e4e9, (q31_t)0x7d5ebefc, (q31_t)0xe62fbd6e, + (q31_t)0x7d5d7a74, (q31_t)0xe6299604, (q31_t)0x7d5c359e, (q31_t)0xe6236ea9, (q31_t)0x7d5af07b, (q31_t)0xe61d475e, (q31_t)0x7d59ab0a, (q31_t)0xe6172024, + (q31_t)0x7d58654d, (q31_t)0xe610f8f9, (q31_t)0x7d571f41, (q31_t)0xe60ad1de, (q31_t)0x7d55d8e9, (q31_t)0xe604aad4, (q31_t)0x7d549243, (q31_t)0xe5fe83d9, + (q31_t)0x7d534b50, (q31_t)0xe5f85cef, (q31_t)0x7d520410, (q31_t)0xe5f23614, (q31_t)0x7d50bc82, (q31_t)0xe5ec0f4a, (q31_t)0x7d4f74a7, (q31_t)0xe5e5e88f, + (q31_t)0x7d4e2c7f, (q31_t)0xe5dfc1e5, (q31_t)0x7d4ce409, (q31_t)0xe5d99b4b, (q31_t)0x7d4b9b46, (q31_t)0xe5d374c1, (q31_t)0x7d4a5236, (q31_t)0xe5cd4e47, + (q31_t)0x7d4908d9, (q31_t)0xe5c727dd, (q31_t)0x7d47bf2e, (q31_t)0xe5c10184, (q31_t)0x7d467536, (q31_t)0xe5badb3a, (q31_t)0x7d452af1, (q31_t)0xe5b4b501, + (q31_t)0x7d43e05e, (q31_t)0xe5ae8ed8, (q31_t)0x7d42957e, (q31_t)0xe5a868bf, (q31_t)0x7d414a51, (q31_t)0xe5a242b7, (q31_t)0x7d3ffed7, (q31_t)0xe59c1cbf, + (q31_t)0x7d3eb30f, (q31_t)0xe595f6d7, (q31_t)0x7d3d66fa, (q31_t)0xe58fd0ff, (q31_t)0x7d3c1a98, (q31_t)0xe589ab38, (q31_t)0x7d3acde9, (q31_t)0xe5838581, + (q31_t)0x7d3980ec, (q31_t)0xe57d5fda, (q31_t)0x7d3833a2, (q31_t)0xe5773a44, (q31_t)0x7d36e60b, (q31_t)0xe57114be, (q31_t)0x7d359827, (q31_t)0xe56aef49, + (q31_t)0x7d3449f5, (q31_t)0xe564c9e3, (q31_t)0x7d32fb76, (q31_t)0xe55ea48f, (q31_t)0x7d31acaa, (q31_t)0xe5587f4a, (q31_t)0x7d305d91, (q31_t)0xe5525a17, + (q31_t)0x7d2f0e2b, (q31_t)0xe54c34f3, (q31_t)0x7d2dbe77, (q31_t)0xe5460fe0, (q31_t)0x7d2c6e76, (q31_t)0xe53feade, (q31_t)0x7d2b1e28, (q31_t)0xe539c5ec, + (q31_t)0x7d29cd8c, (q31_t)0xe533a10a, (q31_t)0x7d287ca4, (q31_t)0xe52d7c39, (q31_t)0x7d272b6e, (q31_t)0xe5275779, (q31_t)0x7d25d9eb, (q31_t)0xe52132c9, + (q31_t)0x7d24881b, (q31_t)0xe51b0e2a, (q31_t)0x7d2335fe, (q31_t)0xe514e99b, (q31_t)0x7d21e393, (q31_t)0xe50ec51d, (q31_t)0x7d2090db, (q31_t)0xe508a0b0, + (q31_t)0x7d1f3dd6, (q31_t)0xe5027c53, (q31_t)0x7d1dea84, (q31_t)0xe4fc5807, (q31_t)0x7d1c96e5, (q31_t)0xe4f633cc, (q31_t)0x7d1b42f9, (q31_t)0xe4f00fa1, + (q31_t)0x7d19eebf, (q31_t)0xe4e9eb87, (q31_t)0x7d189a38, (q31_t)0xe4e3c77d, (q31_t)0x7d174564, (q31_t)0xe4dda385, (q31_t)0x7d15f043, (q31_t)0xe4d77f9d, + (q31_t)0x7d149ad5, (q31_t)0xe4d15bc6, (q31_t)0x7d134519, (q31_t)0xe4cb37ff, (q31_t)0x7d11ef11, (q31_t)0xe4c5144a, (q31_t)0x7d1098bb, (q31_t)0xe4bef0a5, + (q31_t)0x7d0f4218, (q31_t)0xe4b8cd11, (q31_t)0x7d0deb28, (q31_t)0xe4b2a98e, (q31_t)0x7d0c93eb, (q31_t)0xe4ac861b, (q31_t)0x7d0b3c60, (q31_t)0xe4a662ba, + (q31_t)0x7d09e489, (q31_t)0xe4a03f69, (q31_t)0x7d088c64, (q31_t)0xe49a1c29, (q31_t)0x7d0733f3, (q31_t)0xe493f8fb, (q31_t)0x7d05db34, (q31_t)0xe48dd5dd, + (q31_t)0x7d048228, (q31_t)0xe487b2d0, (q31_t)0x7d0328cf, (q31_t)0xe4818fd4, (q31_t)0x7d01cf29, (q31_t)0xe47b6ce9, (q31_t)0x7d007535, (q31_t)0xe4754a0e, + (q31_t)0x7cff1af5, (q31_t)0xe46f2745, (q31_t)0x7cfdc068, (q31_t)0xe469048d, (q31_t)0x7cfc658d, (q31_t)0xe462e1e6, (q31_t)0x7cfb0a65, (q31_t)0xe45cbf50, + (q31_t)0x7cf9aef0, (q31_t)0xe4569ccb, (q31_t)0x7cf8532f, (q31_t)0xe4507a57, (q31_t)0x7cf6f720, (q31_t)0xe44a57f4, (q31_t)0x7cf59ac4, (q31_t)0xe44435a2, + (q31_t)0x7cf43e1a, (q31_t)0xe43e1362, (q31_t)0x7cf2e124, (q31_t)0xe437f132, (q31_t)0x7cf183e1, (q31_t)0xe431cf14, (q31_t)0x7cf02651, (q31_t)0xe42bad07, + (q31_t)0x7ceec873, (q31_t)0xe4258b0a, (q31_t)0x7ced6a49, (q31_t)0xe41f6920, (q31_t)0x7cec0bd1, (q31_t)0xe4194746, (q31_t)0x7ceaad0c, (q31_t)0xe413257d, + (q31_t)0x7ce94dfb, (q31_t)0xe40d03c6, (q31_t)0x7ce7ee9c, (q31_t)0xe406e220, (q31_t)0x7ce68ef0, (q31_t)0xe400c08b, (q31_t)0x7ce52ef7, (q31_t)0xe3fa9f08, + (q31_t)0x7ce3ceb2, (q31_t)0xe3f47d96, (q31_t)0x7ce26e1f, (q31_t)0xe3ee5c35, (q31_t)0x7ce10d3f, (q31_t)0xe3e83ae5, (q31_t)0x7cdfac12, (q31_t)0xe3e219a7, + (q31_t)0x7cde4a98, (q31_t)0xe3dbf87a, (q31_t)0x7cdce8d1, (q31_t)0xe3d5d75e, (q31_t)0x7cdb86bd, (q31_t)0xe3cfb654, (q31_t)0x7cda245c, (q31_t)0xe3c9955b, + (q31_t)0x7cd8c1ae, (q31_t)0xe3c37474, (q31_t)0x7cd75eb3, (q31_t)0xe3bd539e, (q31_t)0x7cd5fb6a, (q31_t)0xe3b732d9, (q31_t)0x7cd497d5, (q31_t)0xe3b11226, + (q31_t)0x7cd333f3, (q31_t)0xe3aaf184, (q31_t)0x7cd1cfc4, (q31_t)0xe3a4d0f4, (q31_t)0x7cd06b48, (q31_t)0xe39eb075, (q31_t)0x7ccf067f, (q31_t)0xe3989008, + (q31_t)0x7ccda169, (q31_t)0xe3926fad, (q31_t)0x7ccc3c06, (q31_t)0xe38c4f63, (q31_t)0x7ccad656, (q31_t)0xe3862f2a, (q31_t)0x7cc97059, (q31_t)0xe3800f03, + (q31_t)0x7cc80a0f, (q31_t)0xe379eeed, (q31_t)0x7cc6a378, (q31_t)0xe373ceea, (q31_t)0x7cc53c94, (q31_t)0xe36daef7, (q31_t)0x7cc3d563, (q31_t)0xe3678f17, + (q31_t)0x7cc26de5, (q31_t)0xe3616f48, (q31_t)0x7cc1061a, (q31_t)0xe35b4f8b, (q31_t)0x7cbf9e03, (q31_t)0xe3552fdf, (q31_t)0x7cbe359e, (q31_t)0xe34f1045, + (q31_t)0x7cbcccec, (q31_t)0xe348f0bd, (q31_t)0x7cbb63ee, (q31_t)0xe342d146, (q31_t)0x7cb9faa2, (q31_t)0xe33cb1e1, (q31_t)0x7cb8910a, (q31_t)0xe336928e, + (q31_t)0x7cb72724, (q31_t)0xe330734d, (q31_t)0x7cb5bcf2, (q31_t)0xe32a541d, (q31_t)0x7cb45272, (q31_t)0xe3243500, (q31_t)0x7cb2e7a6, (q31_t)0xe31e15f4, + (q31_t)0x7cb17c8d, (q31_t)0xe317f6fa, (q31_t)0x7cb01127, (q31_t)0xe311d811, (q31_t)0x7caea574, (q31_t)0xe30bb93b, (q31_t)0x7cad3974, (q31_t)0xe3059a76, + (q31_t)0x7cabcd28, (q31_t)0xe2ff7bc3, (q31_t)0x7caa608e, (q31_t)0xe2f95d23, (q31_t)0x7ca8f3a7, (q31_t)0xe2f33e94, (q31_t)0x7ca78674, (q31_t)0xe2ed2017, + (q31_t)0x7ca618f3, (q31_t)0xe2e701ac, (q31_t)0x7ca4ab26, (q31_t)0xe2e0e352, (q31_t)0x7ca33d0c, (q31_t)0xe2dac50b, (q31_t)0x7ca1cea5, (q31_t)0xe2d4a6d6, + (q31_t)0x7ca05ff1, (q31_t)0xe2ce88b3, (q31_t)0x7c9ef0f0, (q31_t)0xe2c86aa2, (q31_t)0x7c9d81a3, (q31_t)0xe2c24ca2, (q31_t)0x7c9c1208, (q31_t)0xe2bc2eb5, + (q31_t)0x7c9aa221, (q31_t)0xe2b610da, (q31_t)0x7c9931ec, (q31_t)0xe2aff311, (q31_t)0x7c97c16b, (q31_t)0xe2a9d55a, (q31_t)0x7c96509d, (q31_t)0xe2a3b7b5, + (q31_t)0x7c94df83, (q31_t)0xe29d9a23, (q31_t)0x7c936e1b, (q31_t)0xe2977ca2, (q31_t)0x7c91fc66, (q31_t)0xe2915f34, (q31_t)0x7c908a65, (q31_t)0xe28b41d7, + (q31_t)0x7c8f1817, (q31_t)0xe285248d, (q31_t)0x7c8da57c, (q31_t)0xe27f0755, (q31_t)0x7c8c3294, (q31_t)0xe278ea30, (q31_t)0x7c8abf5f, (q31_t)0xe272cd1c, + (q31_t)0x7c894bde, (q31_t)0xe26cb01b, (q31_t)0x7c87d810, (q31_t)0xe266932c, (q31_t)0x7c8663f4, (q31_t)0xe260764f, (q31_t)0x7c84ef8c, (q31_t)0xe25a5984, + (q31_t)0x7c837ad8, (q31_t)0xe2543ccc, (q31_t)0x7c8205d6, (q31_t)0xe24e2026, (q31_t)0x7c809088, (q31_t)0xe2480393, (q31_t)0x7c7f1aed, (q31_t)0xe241e711, + (q31_t)0x7c7da505, (q31_t)0xe23bcaa2, (q31_t)0x7c7c2ed0, (q31_t)0xe235ae46, (q31_t)0x7c7ab84e, (q31_t)0xe22f91fc, (q31_t)0x7c794180, (q31_t)0xe22975c4, + (q31_t)0x7c77ca65, (q31_t)0xe223599e, (q31_t)0x7c7652fd, (q31_t)0xe21d3d8b, (q31_t)0x7c74db48, (q31_t)0xe217218b, (q31_t)0x7c736347, (q31_t)0xe211059d, + (q31_t)0x7c71eaf9, (q31_t)0xe20ae9c1, (q31_t)0x7c70725e, (q31_t)0xe204cdf8, (q31_t)0x7c6ef976, (q31_t)0xe1feb241, (q31_t)0x7c6d8041, (q31_t)0xe1f8969d, + (q31_t)0x7c6c06c0, (q31_t)0xe1f27b0b, (q31_t)0x7c6a8cf2, (q31_t)0xe1ec5f8c, (q31_t)0x7c6912d7, (q31_t)0xe1e64420, (q31_t)0x7c679870, (q31_t)0xe1e028c6, + (q31_t)0x7c661dbc, (q31_t)0xe1da0d7e, (q31_t)0x7c64a2bb, (q31_t)0xe1d3f24a, (q31_t)0x7c63276d, (q31_t)0xe1cdd727, (q31_t)0x7c61abd3, (q31_t)0xe1c7bc18, + (q31_t)0x7c602fec, (q31_t)0xe1c1a11b, (q31_t)0x7c5eb3b8, (q31_t)0xe1bb8631, (q31_t)0x7c5d3737, (q31_t)0xe1b56b59, (q31_t)0x7c5bba6a, (q31_t)0xe1af5094, + (q31_t)0x7c5a3d50, (q31_t)0xe1a935e2, (q31_t)0x7c58bfe9, (q31_t)0xe1a31b42, (q31_t)0x7c574236, (q31_t)0xe19d00b6, (q31_t)0x7c55c436, (q31_t)0xe196e63c, + (q31_t)0x7c5445e9, (q31_t)0xe190cbd4, (q31_t)0x7c52c74f, (q31_t)0xe18ab180, (q31_t)0x7c514869, (q31_t)0xe184973e, (q31_t)0x7c4fc936, (q31_t)0xe17e7d0f, + (q31_t)0x7c4e49b7, (q31_t)0xe17862f3, (q31_t)0x7c4cc9ea, (q31_t)0xe17248ea, (q31_t)0x7c4b49d2, (q31_t)0xe16c2ef4, (q31_t)0x7c49c96c, (q31_t)0xe1661510, + (q31_t)0x7c4848ba, (q31_t)0xe15ffb3f, (q31_t)0x7c46c7bb, (q31_t)0xe159e182, (q31_t)0x7c45466f, (q31_t)0xe153c7d7, (q31_t)0x7c43c4d7, (q31_t)0xe14dae3f, + (q31_t)0x7c4242f2, (q31_t)0xe14794ba, (q31_t)0x7c40c0c1, (q31_t)0xe1417b48, (q31_t)0x7c3f3e42, (q31_t)0xe13b61e9, (q31_t)0x7c3dbb78, (q31_t)0xe135489d, + (q31_t)0x7c3c3860, (q31_t)0xe12f2f63, (q31_t)0x7c3ab4fc, (q31_t)0xe129163d, (q31_t)0x7c39314b, (q31_t)0xe122fd2a, (q31_t)0x7c37ad4e, (q31_t)0xe11ce42a, + (q31_t)0x7c362904, (q31_t)0xe116cb3d, (q31_t)0x7c34a46d, (q31_t)0xe110b263, (q31_t)0x7c331f8a, (q31_t)0xe10a999c, (q31_t)0x7c319a5a, (q31_t)0xe10480e9, + (q31_t)0x7c3014de, (q31_t)0xe0fe6848, (q31_t)0x7c2e8f15, (q31_t)0xe0f84fbb, (q31_t)0x7c2d08ff, (q31_t)0xe0f23740, (q31_t)0x7c2b829d, (q31_t)0xe0ec1ed9, + (q31_t)0x7c29fbee, (q31_t)0xe0e60685, (q31_t)0x7c2874f3, (q31_t)0xe0dfee44, (q31_t)0x7c26edab, (q31_t)0xe0d9d616, (q31_t)0x7c256616, (q31_t)0xe0d3bdfc, + (q31_t)0x7c23de35, (q31_t)0xe0cda5f5, (q31_t)0x7c225607, (q31_t)0xe0c78e01, (q31_t)0x7c20cd8d, (q31_t)0xe0c17620, (q31_t)0x7c1f44c6, (q31_t)0xe0bb5e53, + (q31_t)0x7c1dbbb3, (q31_t)0xe0b54698, (q31_t)0x7c1c3253, (q31_t)0xe0af2ef2, (q31_t)0x7c1aa8a6, (q31_t)0xe0a9175e, (q31_t)0x7c191ead, (q31_t)0xe0a2ffde, + (q31_t)0x7c179467, (q31_t)0xe09ce871, (q31_t)0x7c1609d5, (q31_t)0xe096d117, (q31_t)0x7c147ef6, (q31_t)0xe090b9d1, (q31_t)0x7c12f3cb, (q31_t)0xe08aa29f, + (q31_t)0x7c116853, (q31_t)0xe0848b7f, (q31_t)0x7c0fdc8f, (q31_t)0xe07e7473, (q31_t)0x7c0e507e, (q31_t)0xe0785d7b, (q31_t)0x7c0cc421, (q31_t)0xe0724696, + (q31_t)0x7c0b3777, (q31_t)0xe06c2fc4, (q31_t)0x7c09aa80, (q31_t)0xe0661906, (q31_t)0x7c081d3d, (q31_t)0xe060025c, (q31_t)0x7c068fae, (q31_t)0xe059ebc5, + (q31_t)0x7c0501d2, (q31_t)0xe053d541, (q31_t)0x7c0373a9, (q31_t)0xe04dbed1, (q31_t)0x7c01e534, (q31_t)0xe047a875, (q31_t)0x7c005673, (q31_t)0xe041922c, + (q31_t)0x7bfec765, (q31_t)0xe03b7bf6, (q31_t)0x7bfd380a, (q31_t)0xe03565d5, (q31_t)0x7bfba863, (q31_t)0xe02f4fc6, (q31_t)0x7bfa1870, (q31_t)0xe02939cc, + (q31_t)0x7bf88830, (q31_t)0xe02323e5, (q31_t)0x7bf6f7a4, (q31_t)0xe01d0e12, (q31_t)0x7bf566cb, (q31_t)0xe016f852, (q31_t)0x7bf3d5a6, (q31_t)0xe010e2a7, + (q31_t)0x7bf24434, (q31_t)0xe00acd0e, (q31_t)0x7bf0b276, (q31_t)0xe004b78a, (q31_t)0x7bef206b, (q31_t)0xdffea219, (q31_t)0x7bed8e14, (q31_t)0xdff88cbc, + (q31_t)0x7bebfb70, (q31_t)0xdff27773, (q31_t)0x7bea6880, (q31_t)0xdfec623e, (q31_t)0x7be8d544, (q31_t)0xdfe64d1c, (q31_t)0x7be741bb, (q31_t)0xdfe0380e, + (q31_t)0x7be5ade6, (q31_t)0xdfda2314, (q31_t)0x7be419c4, (q31_t)0xdfd40e2e, (q31_t)0x7be28556, (q31_t)0xdfcdf95c, (q31_t)0x7be0f09b, (q31_t)0xdfc7e49d, + (q31_t)0x7bdf5b94, (q31_t)0xdfc1cff3, (q31_t)0x7bddc641, (q31_t)0xdfbbbb5c, (q31_t)0x7bdc30a1, (q31_t)0xdfb5a6d9, (q31_t)0x7bda9ab5, (q31_t)0xdfaf926a, + (q31_t)0x7bd9047c, (q31_t)0xdfa97e0f, (q31_t)0x7bd76df7, (q31_t)0xdfa369c8, (q31_t)0x7bd5d726, (q31_t)0xdf9d5595, (q31_t)0x7bd44008, (q31_t)0xdf974176, + (q31_t)0x7bd2a89e, (q31_t)0xdf912d6b, (q31_t)0x7bd110e8, (q31_t)0xdf8b1974, (q31_t)0x7bcf78e5, (q31_t)0xdf850591, (q31_t)0x7bcde095, (q31_t)0xdf7ef1c2, + (q31_t)0x7bcc47fa, (q31_t)0xdf78de07, (q31_t)0x7bcaaf12, (q31_t)0xdf72ca60, (q31_t)0x7bc915dd, (q31_t)0xdf6cb6cd, (q31_t)0x7bc77c5d, (q31_t)0xdf66a34e, + (q31_t)0x7bc5e290, (q31_t)0xdf608fe4, (q31_t)0x7bc44876, (q31_t)0xdf5a7c8d, (q31_t)0x7bc2ae10, (q31_t)0xdf54694b, (q31_t)0x7bc1135e, (q31_t)0xdf4e561c, + (q31_t)0x7bbf7860, (q31_t)0xdf484302, (q31_t)0x7bbddd15, (q31_t)0xdf422ffd, (q31_t)0x7bbc417e, (q31_t)0xdf3c1d0b, (q31_t)0x7bbaa59a, (q31_t)0xdf360a2d, + (q31_t)0x7bb9096b, (q31_t)0xdf2ff764, (q31_t)0x7bb76cef, (q31_t)0xdf29e4af, (q31_t)0x7bb5d026, (q31_t)0xdf23d20e, (q31_t)0x7bb43311, (q31_t)0xdf1dbf82, + (q31_t)0x7bb295b0, (q31_t)0xdf17ad0a, (q31_t)0x7bb0f803, (q31_t)0xdf119aa6, (q31_t)0x7baf5a09, (q31_t)0xdf0b8856, (q31_t)0x7badbbc3, (q31_t)0xdf05761b, + (q31_t)0x7bac1d31, (q31_t)0xdeff63f4, (q31_t)0x7baa7e53, (q31_t)0xdef951e2, (q31_t)0x7ba8df28, (q31_t)0xdef33fe3, (q31_t)0x7ba73fb1, (q31_t)0xdeed2dfa, + (q31_t)0x7ba59fee, (q31_t)0xdee71c24, (q31_t)0x7ba3ffde, (q31_t)0xdee10a63, (q31_t)0x7ba25f82, (q31_t)0xdedaf8b7, (q31_t)0x7ba0beda, (q31_t)0xded4e71f, + (q31_t)0x7b9f1de6, (q31_t)0xdeced59b, (q31_t)0x7b9d7ca5, (q31_t)0xdec8c42c, (q31_t)0x7b9bdb18, (q31_t)0xdec2b2d1, (q31_t)0x7b9a393f, (q31_t)0xdebca18b, + (q31_t)0x7b989719, (q31_t)0xdeb69059, (q31_t)0x7b96f4a8, (q31_t)0xdeb07f3c, (q31_t)0x7b9551ea, (q31_t)0xdeaa6e34, (q31_t)0x7b93aee0, (q31_t)0xdea45d40, + (q31_t)0x7b920b89, (q31_t)0xde9e4c60, (q31_t)0x7b9067e7, (q31_t)0xde983b95, (q31_t)0x7b8ec3f8, (q31_t)0xde922adf, (q31_t)0x7b8d1fbd, (q31_t)0xde8c1a3e, + (q31_t)0x7b8b7b36, (q31_t)0xde8609b1, (q31_t)0x7b89d662, (q31_t)0xde7ff938, (q31_t)0x7b883143, (q31_t)0xde79e8d5, (q31_t)0x7b868bd7, (q31_t)0xde73d886, + (q31_t)0x7b84e61f, (q31_t)0xde6dc84b, (q31_t)0x7b83401b, (q31_t)0xde67b826, (q31_t)0x7b8199ca, (q31_t)0xde61a815, (q31_t)0x7b7ff32e, (q31_t)0xde5b9819, + (q31_t)0x7b7e4c45, (q31_t)0xde558831, (q31_t)0x7b7ca510, (q31_t)0xde4f785f, (q31_t)0x7b7afd8f, (q31_t)0xde4968a1, (q31_t)0x7b7955c2, (q31_t)0xde4358f8, + (q31_t)0x7b77ada8, (q31_t)0xde3d4964, (q31_t)0x7b760542, (q31_t)0xde3739e4, (q31_t)0x7b745c91, (q31_t)0xde312a7a, (q31_t)0x7b72b393, (q31_t)0xde2b1b24, + (q31_t)0x7b710a49, (q31_t)0xde250be3, (q31_t)0x7b6f60b2, (q31_t)0xde1efcb7, (q31_t)0x7b6db6d0, (q31_t)0xde18eda0, (q31_t)0x7b6c0ca2, (q31_t)0xde12de9e, + (q31_t)0x7b6a6227, (q31_t)0xde0ccfb1, (q31_t)0x7b68b760, (q31_t)0xde06c0d9, (q31_t)0x7b670c4d, (q31_t)0xde00b216, (q31_t)0x7b6560ee, (q31_t)0xddfaa367, + (q31_t)0x7b63b543, (q31_t)0xddf494ce, (q31_t)0x7b62094c, (q31_t)0xddee8649, (q31_t)0x7b605d09, (q31_t)0xdde877da, (q31_t)0x7b5eb079, (q31_t)0xdde26980, + (q31_t)0x7b5d039e, (q31_t)0xdddc5b3b, (q31_t)0x7b5b5676, (q31_t)0xddd64d0a, (q31_t)0x7b59a902, (q31_t)0xddd03eef, (q31_t)0x7b57fb42, (q31_t)0xddca30e9, + (q31_t)0x7b564d36, (q31_t)0xddc422f8, (q31_t)0x7b549ede, (q31_t)0xddbe151d, (q31_t)0x7b52f03a, (q31_t)0xddb80756, (q31_t)0x7b51414a, (q31_t)0xddb1f9a4, + (q31_t)0x7b4f920e, (q31_t)0xddabec08, (q31_t)0x7b4de286, (q31_t)0xdda5de81, (q31_t)0x7b4c32b1, (q31_t)0xdd9fd10f, (q31_t)0x7b4a8291, (q31_t)0xdd99c3b2, + (q31_t)0x7b48d225, (q31_t)0xdd93b66a, (q31_t)0x7b47216c, (q31_t)0xdd8da938, (q31_t)0x7b457068, (q31_t)0xdd879c1b, (q31_t)0x7b43bf17, (q31_t)0xdd818f13, + (q31_t)0x7b420d7a, (q31_t)0xdd7b8220, (q31_t)0x7b405b92, (q31_t)0xdd757543, (q31_t)0x7b3ea95d, (q31_t)0xdd6f687b, (q31_t)0x7b3cf6dc, (q31_t)0xdd695bc9, + (q31_t)0x7b3b4410, (q31_t)0xdd634f2b, (q31_t)0x7b3990f7, (q31_t)0xdd5d42a3, (q31_t)0x7b37dd92, (q31_t)0xdd573631, (q31_t)0x7b3629e1, (q31_t)0xdd5129d4, + (q31_t)0x7b3475e5, (q31_t)0xdd4b1d8c, (q31_t)0x7b32c19c, (q31_t)0xdd451159, (q31_t)0x7b310d07, (q31_t)0xdd3f053c, (q31_t)0x7b2f5826, (q31_t)0xdd38f935, + (q31_t)0x7b2da2fa, (q31_t)0xdd32ed43, (q31_t)0x7b2bed81, (q31_t)0xdd2ce166, (q31_t)0x7b2a37bc, (q31_t)0xdd26d59f, (q31_t)0x7b2881ac, (q31_t)0xdd20c9ed, + (q31_t)0x7b26cb4f, (q31_t)0xdd1abe51, (q31_t)0x7b2514a6, (q31_t)0xdd14b2ca, (q31_t)0x7b235db2, (q31_t)0xdd0ea759, (q31_t)0x7b21a671, (q31_t)0xdd089bfe, + (q31_t)0x7b1feee5, (q31_t)0xdd0290b8, (q31_t)0x7b1e370d, (q31_t)0xdcfc8588, (q31_t)0x7b1c7ee8, (q31_t)0xdcf67a6d, (q31_t)0x7b1ac678, (q31_t)0xdcf06f68, + (q31_t)0x7b190dbc, (q31_t)0xdcea6478, (q31_t)0x7b1754b3, (q31_t)0xdce4599e, (q31_t)0x7b159b5f, (q31_t)0xdcde4eda, (q31_t)0x7b13e1bf, (q31_t)0xdcd8442b, + (q31_t)0x7b1227d3, (q31_t)0xdcd23993, (q31_t)0x7b106d9b, (q31_t)0xdccc2f0f, (q31_t)0x7b0eb318, (q31_t)0xdcc624a2, (q31_t)0x7b0cf848, (q31_t)0xdcc01a4a, + (q31_t)0x7b0b3d2c, (q31_t)0xdcba1008, (q31_t)0x7b0981c5, (q31_t)0xdcb405dc, (q31_t)0x7b07c612, (q31_t)0xdcadfbc5, (q31_t)0x7b060a12, (q31_t)0xdca7f1c5, + (q31_t)0x7b044dc7, (q31_t)0xdca1e7da, (q31_t)0x7b029130, (q31_t)0xdc9bde05, (q31_t)0x7b00d44d, (q31_t)0xdc95d446, (q31_t)0x7aff171e, (q31_t)0xdc8fca9c, + (q31_t)0x7afd59a4, (q31_t)0xdc89c109, (q31_t)0x7afb9bdd, (q31_t)0xdc83b78b, (q31_t)0x7af9ddcb, (q31_t)0xdc7dae23, (q31_t)0x7af81f6c, (q31_t)0xdc77a4d2, + (q31_t)0x7af660c2, (q31_t)0xdc719b96, (q31_t)0x7af4a1cc, (q31_t)0xdc6b9270, (q31_t)0x7af2e28b, (q31_t)0xdc658960, (q31_t)0x7af122fd, (q31_t)0xdc5f8066, + (q31_t)0x7aef6323, (q31_t)0xdc597781, (q31_t)0x7aeda2fe, (q31_t)0xdc536eb3, (q31_t)0x7aebe28d, (q31_t)0xdc4d65fb, (q31_t)0x7aea21d0, (q31_t)0xdc475d59, + (q31_t)0x7ae860c7, (q31_t)0xdc4154cd, (q31_t)0x7ae69f73, (q31_t)0xdc3b4c57, (q31_t)0x7ae4ddd2, (q31_t)0xdc3543f7, (q31_t)0x7ae31be6, (q31_t)0xdc2f3bad, + (q31_t)0x7ae159ae, (q31_t)0xdc293379, (q31_t)0x7adf972a, (q31_t)0xdc232b5c, (q31_t)0x7addd45b, (q31_t)0xdc1d2354, (q31_t)0x7adc113f, (q31_t)0xdc171b63, + (q31_t)0x7ada4dd8, (q31_t)0xdc111388, (q31_t)0x7ad88a25, (q31_t)0xdc0b0bc2, (q31_t)0x7ad6c626, (q31_t)0xdc050414, (q31_t)0x7ad501dc, (q31_t)0xdbfefc7b, + (q31_t)0x7ad33d45, (q31_t)0xdbf8f4f8, (q31_t)0x7ad17863, (q31_t)0xdbf2ed8c, (q31_t)0x7acfb336, (q31_t)0xdbece636, (q31_t)0x7acdedbc, (q31_t)0xdbe6def6, + (q31_t)0x7acc27f7, (q31_t)0xdbe0d7cd, (q31_t)0x7aca61e6, (q31_t)0xdbdad0b9, (q31_t)0x7ac89b89, (q31_t)0xdbd4c9bc, (q31_t)0x7ac6d4e0, (q31_t)0xdbcec2d6, + (q31_t)0x7ac50dec, (q31_t)0xdbc8bc06, (q31_t)0x7ac346ac, (q31_t)0xdbc2b54c, (q31_t)0x7ac17f20, (q31_t)0xdbbcaea8, (q31_t)0x7abfb749, (q31_t)0xdbb6a81b, + (q31_t)0x7abdef25, (q31_t)0xdbb0a1a4, (q31_t)0x7abc26b7, (q31_t)0xdbaa9b43, (q31_t)0x7aba5dfc, (q31_t)0xdba494f9, (q31_t)0x7ab894f6, (q31_t)0xdb9e8ec6, + (q31_t)0x7ab6cba4, (q31_t)0xdb9888a8, (q31_t)0x7ab50206, (q31_t)0xdb9282a2, (q31_t)0x7ab3381d, (q31_t)0xdb8c7cb1, (q31_t)0x7ab16de7, (q31_t)0xdb8676d8, + (q31_t)0x7aafa367, (q31_t)0xdb807114, (q31_t)0x7aadd89a, (q31_t)0xdb7a6b68, (q31_t)0x7aac0d82, (q31_t)0xdb7465d1, (q31_t)0x7aaa421e, (q31_t)0xdb6e6052, + (q31_t)0x7aa8766f, (q31_t)0xdb685ae9, (q31_t)0x7aa6aa74, (q31_t)0xdb625596, (q31_t)0x7aa4de2d, (q31_t)0xdb5c505a, (q31_t)0x7aa3119a, (q31_t)0xdb564b35, + (q31_t)0x7aa144bc, (q31_t)0xdb504626, (q31_t)0x7a9f7793, (q31_t)0xdb4a412e, (q31_t)0x7a9daa1d, (q31_t)0xdb443c4c, (q31_t)0x7a9bdc5c, (q31_t)0xdb3e3781, + (q31_t)0x7a9a0e50, (q31_t)0xdb3832cd, (q31_t)0x7a983ff7, (q31_t)0xdb322e30, (q31_t)0x7a967153, (q31_t)0xdb2c29a9, (q31_t)0x7a94a264, (q31_t)0xdb262539, + (q31_t)0x7a92d329, (q31_t)0xdb2020e0, (q31_t)0x7a9103a2, (q31_t)0xdb1a1c9d, (q31_t)0x7a8f33d0, (q31_t)0xdb141871, (q31_t)0x7a8d63b2, (q31_t)0xdb0e145c, + (q31_t)0x7a8b9348, (q31_t)0xdb08105e, (q31_t)0x7a89c293, (q31_t)0xdb020c77, (q31_t)0x7a87f192, (q31_t)0xdafc08a6, (q31_t)0x7a862046, (q31_t)0xdaf604ec, + (q31_t)0x7a844eae, (q31_t)0xdaf00149, (q31_t)0x7a827ccb, (q31_t)0xdae9fdbd, (q31_t)0x7a80aa9c, (q31_t)0xdae3fa48, (q31_t)0x7a7ed821, (q31_t)0xdaddf6ea, + (q31_t)0x7a7d055b, (q31_t)0xdad7f3a2, (q31_t)0x7a7b3249, (q31_t)0xdad1f072, (q31_t)0x7a795eec, (q31_t)0xdacbed58, (q31_t)0x7a778b43, (q31_t)0xdac5ea56, + (q31_t)0x7a75b74f, (q31_t)0xdabfe76a, (q31_t)0x7a73e30f, (q31_t)0xdab9e495, (q31_t)0x7a720e84, (q31_t)0xdab3e1d8, (q31_t)0x7a7039ad, (q31_t)0xdaaddf31, + (q31_t)0x7a6e648a, (q31_t)0xdaa7dca1, (q31_t)0x7a6c8f1c, (q31_t)0xdaa1da29, (q31_t)0x7a6ab963, (q31_t)0xda9bd7c7, (q31_t)0x7a68e35e, (q31_t)0xda95d57d, + (q31_t)0x7a670d0d, (q31_t)0xda8fd349, (q31_t)0x7a653671, (q31_t)0xda89d12d, (q31_t)0x7a635f8a, (q31_t)0xda83cf28, (q31_t)0x7a618857, (q31_t)0xda7dcd3a, + (q31_t)0x7a5fb0d8, (q31_t)0xda77cb63, (q31_t)0x7a5dd90e, (q31_t)0xda71c9a3, (q31_t)0x7a5c00f9, (q31_t)0xda6bc7fa, (q31_t)0x7a5a2898, (q31_t)0xda65c669, + (q31_t)0x7a584feb, (q31_t)0xda5fc4ef, (q31_t)0x7a5676f3, (q31_t)0xda59c38c, (q31_t)0x7a549db0, (q31_t)0xda53c240, (q31_t)0x7a52c421, (q31_t)0xda4dc10b, + (q31_t)0x7a50ea47, (q31_t)0xda47bfee, (q31_t)0x7a4f1021, (q31_t)0xda41bee8, (q31_t)0x7a4d35b0, (q31_t)0xda3bbdf9, (q31_t)0x7a4b5af3, (q31_t)0xda35bd22, + (q31_t)0x7a497feb, (q31_t)0xda2fbc61, (q31_t)0x7a47a498, (q31_t)0xda29bbb9, (q31_t)0x7a45c8f9, (q31_t)0xda23bb27, (q31_t)0x7a43ed0e, (q31_t)0xda1dbaad, + (q31_t)0x7a4210d8, (q31_t)0xda17ba4a, (q31_t)0x7a403457, (q31_t)0xda11b9ff, (q31_t)0x7a3e578b, (q31_t)0xda0bb9cb, (q31_t)0x7a3c7a73, (q31_t)0xda05b9ae, + (q31_t)0x7a3a9d0f, (q31_t)0xd9ffb9a9, (q31_t)0x7a38bf60, (q31_t)0xd9f9b9bb, (q31_t)0x7a36e166, (q31_t)0xd9f3b9e5, (q31_t)0x7a350321, (q31_t)0xd9edba26, + (q31_t)0x7a332490, (q31_t)0xd9e7ba7f, (q31_t)0x7a3145b3, (q31_t)0xd9e1baef, (q31_t)0x7a2f668c, (q31_t)0xd9dbbb77, (q31_t)0x7a2d8719, (q31_t)0xd9d5bc16, + (q31_t)0x7a2ba75a, (q31_t)0xd9cfbccd, (q31_t)0x7a29c750, (q31_t)0xd9c9bd9b, (q31_t)0x7a27e6fb, (q31_t)0xd9c3be81, (q31_t)0x7a26065b, (q31_t)0xd9bdbf7e, + (q31_t)0x7a24256f, (q31_t)0xd9b7c094, (q31_t)0x7a224437, (q31_t)0xd9b1c1c0, (q31_t)0x7a2062b5, (q31_t)0xd9abc305, (q31_t)0x7a1e80e7, (q31_t)0xd9a5c461, + (q31_t)0x7a1c9ece, (q31_t)0xd99fc5d4, (q31_t)0x7a1abc69, (q31_t)0xd999c75f, (q31_t)0x7a18d9b9, (q31_t)0xd993c902, (q31_t)0x7a16f6be, (q31_t)0xd98dcabd, + (q31_t)0x7a151378, (q31_t)0xd987cc90, (q31_t)0x7a132fe6, (q31_t)0xd981ce7a, (q31_t)0x7a114c09, (q31_t)0xd97bd07c, (q31_t)0x7a0f67e0, (q31_t)0xd975d295, + (q31_t)0x7a0d836d, (q31_t)0xd96fd4c7, (q31_t)0x7a0b9eae, (q31_t)0xd969d710, (q31_t)0x7a09b9a4, (q31_t)0xd963d971, (q31_t)0x7a07d44e, (q31_t)0xd95ddbea, + (q31_t)0x7a05eead, (q31_t)0xd957de7a, (q31_t)0x7a0408c1, (q31_t)0xd951e123, (q31_t)0x7a02228a, (q31_t)0xd94be3e3, (q31_t)0x7a003c07, (q31_t)0xd945e6bb, + (q31_t)0x79fe5539, (q31_t)0xd93fe9ab, (q31_t)0x79fc6e20, (q31_t)0xd939ecb3, (q31_t)0x79fa86bc, (q31_t)0xd933efd3, (q31_t)0x79f89f0c, (q31_t)0xd92df30b, + (q31_t)0x79f6b711, (q31_t)0xd927f65b, (q31_t)0x79f4cecb, (q31_t)0xd921f9c3, (q31_t)0x79f2e63a, (q31_t)0xd91bfd43, (q31_t)0x79f0fd5d, (q31_t)0xd91600da, + (q31_t)0x79ef1436, (q31_t)0xd910048a, (q31_t)0x79ed2ac3, (q31_t)0xd90a0852, (q31_t)0x79eb4105, (q31_t)0xd9040c32, (q31_t)0x79e956fb, (q31_t)0xd8fe1029, + (q31_t)0x79e76ca7, (q31_t)0xd8f81439, (q31_t)0x79e58207, (q31_t)0xd8f21861, (q31_t)0x79e3971c, (q31_t)0xd8ec1ca1, (q31_t)0x79e1abe6, (q31_t)0xd8e620fa, + (q31_t)0x79dfc064, (q31_t)0xd8e0256a, (q31_t)0x79ddd498, (q31_t)0xd8da29f2, (q31_t)0x79dbe880, (q31_t)0xd8d42e93, (q31_t)0x79d9fc1d, (q31_t)0xd8ce334c, + (q31_t)0x79d80f6f, (q31_t)0xd8c8381d, (q31_t)0x79d62276, (q31_t)0xd8c23d06, (q31_t)0x79d43532, (q31_t)0xd8bc4207, (q31_t)0x79d247a2, (q31_t)0xd8b64720, + (q31_t)0x79d059c8, (q31_t)0xd8b04c52, (q31_t)0x79ce6ba2, (q31_t)0xd8aa519c, (q31_t)0x79cc7d31, (q31_t)0xd8a456ff, (q31_t)0x79ca8e75, (q31_t)0xd89e5c79, + (q31_t)0x79c89f6e, (q31_t)0xd898620c, (q31_t)0x79c6b01b, (q31_t)0xd89267b7, (q31_t)0x79c4c07e, (q31_t)0xd88c6d7b, (q31_t)0x79c2d095, (q31_t)0xd8867356, + (q31_t)0x79c0e062, (q31_t)0xd880794b, (q31_t)0x79beefe3, (q31_t)0xd87a7f57, (q31_t)0x79bcff19, (q31_t)0xd874857c, (q31_t)0x79bb0e04, (q31_t)0xd86e8bb9, + (q31_t)0x79b91ca4, (q31_t)0xd868920f, (q31_t)0x79b72af9, (q31_t)0xd862987d, (q31_t)0x79b53903, (q31_t)0xd85c9f04, (q31_t)0x79b346c2, (q31_t)0xd856a5a3, + (q31_t)0x79b15435, (q31_t)0xd850ac5a, (q31_t)0x79af615e, (q31_t)0xd84ab32a, (q31_t)0x79ad6e3c, (q31_t)0xd844ba13, (q31_t)0x79ab7ace, (q31_t)0xd83ec114, + (q31_t)0x79a98715, (q31_t)0xd838c82d, (q31_t)0x79a79312, (q31_t)0xd832cf5f, (q31_t)0x79a59ec3, (q31_t)0xd82cd6aa, (q31_t)0x79a3aa29, (q31_t)0xd826de0d, + (q31_t)0x79a1b545, (q31_t)0xd820e589, (q31_t)0x799fc015, (q31_t)0xd81aed1d, (q31_t)0x799dca9a, (q31_t)0xd814f4ca, (q31_t)0x799bd4d4, (q31_t)0xd80efc8f, + (q31_t)0x7999dec4, (q31_t)0xd809046e, (q31_t)0x7997e868, (q31_t)0xd8030c64, (q31_t)0x7995f1c1, (q31_t)0xd7fd1474, (q31_t)0x7993facf, (q31_t)0xd7f71c9c, + (q31_t)0x79920392, (q31_t)0xd7f124dd, (q31_t)0x79900c0a, (q31_t)0xd7eb2d37, (q31_t)0x798e1438, (q31_t)0xd7e535a9, (q31_t)0x798c1c1a, (q31_t)0xd7df3e34, + (q31_t)0x798a23b1, (q31_t)0xd7d946d8, (q31_t)0x79882afd, (q31_t)0xd7d34f94, (q31_t)0x798631ff, (q31_t)0xd7cd586a, (q31_t)0x798438b5, (q31_t)0xd7c76158, + (q31_t)0x79823f20, (q31_t)0xd7c16a5f, (q31_t)0x79804541, (q31_t)0xd7bb737f, (q31_t)0x797e4b16, (q31_t)0xd7b57cb7, (q31_t)0x797c50a1, (q31_t)0xd7af8609, + (q31_t)0x797a55e0, (q31_t)0xd7a98f73, (q31_t)0x79785ad5, (q31_t)0xd7a398f6, (q31_t)0x79765f7f, (q31_t)0xd79da293, (q31_t)0x797463de, (q31_t)0xd797ac48, + (q31_t)0x797267f2, (q31_t)0xd791b616, (q31_t)0x79706bbb, (q31_t)0xd78bbffc, (q31_t)0x796e6f39, (q31_t)0xd785c9fc, (q31_t)0x796c726c, (q31_t)0xd77fd415, + (q31_t)0x796a7554, (q31_t)0xd779de47, (q31_t)0x796877f1, (q31_t)0xd773e892, (q31_t)0x79667a44, (q31_t)0xd76df2f6, (q31_t)0x79647c4c, (q31_t)0xd767fd72, + (q31_t)0x79627e08, (q31_t)0xd7620808, (q31_t)0x79607f7a, (q31_t)0xd75c12b7, (q31_t)0x795e80a1, (q31_t)0xd7561d7f, (q31_t)0x795c817d, (q31_t)0xd7502860, + (q31_t)0x795a820e, (q31_t)0xd74a335b, (q31_t)0x79588255, (q31_t)0xd7443e6e, (q31_t)0x79568250, (q31_t)0xd73e499a, (q31_t)0x79548201, (q31_t)0xd73854e0, + (q31_t)0x79528167, (q31_t)0xd732603f, (q31_t)0x79508082, (q31_t)0xd72c6bb6, (q31_t)0x794e7f52, (q31_t)0xd7267748, (q31_t)0x794c7dd7, (q31_t)0xd72082f2, + (q31_t)0x794a7c12, (q31_t)0xd71a8eb5, (q31_t)0x79487a01, (q31_t)0xd7149a92, (q31_t)0x794677a6, (q31_t)0xd70ea688, (q31_t)0x79447500, (q31_t)0xd708b297, + (q31_t)0x79427210, (q31_t)0xd702bec0, (q31_t)0x79406ed4, (q31_t)0xd6fccb01, (q31_t)0x793e6b4e, (q31_t)0xd6f6d75d, (q31_t)0x793c677d, (q31_t)0xd6f0e3d1, + (q31_t)0x793a6361, (q31_t)0xd6eaf05f, (q31_t)0x79385efa, (q31_t)0xd6e4fd06, (q31_t)0x79365a49, (q31_t)0xd6df09c6, (q31_t)0x7934554d, (q31_t)0xd6d916a0, + (q31_t)0x79325006, (q31_t)0xd6d32393, (q31_t)0x79304a74, (q31_t)0xd6cd30a0, (q31_t)0x792e4497, (q31_t)0xd6c73dc6, (q31_t)0x792c3e70, (q31_t)0xd6c14b05, + (q31_t)0x792a37fe, (q31_t)0xd6bb585e, (q31_t)0x79283141, (q31_t)0xd6b565d0, (q31_t)0x79262a3a, (q31_t)0xd6af735c, (q31_t)0x792422e8, (q31_t)0xd6a98101, + (q31_t)0x79221b4b, (q31_t)0xd6a38ec0, (q31_t)0x79201363, (q31_t)0xd69d9c98, (q31_t)0x791e0b31, (q31_t)0xd697aa8a, (q31_t)0x791c02b4, (q31_t)0xd691b895, + (q31_t)0x7919f9ec, (q31_t)0xd68bc6ba, (q31_t)0x7917f0d9, (q31_t)0xd685d4f9, (q31_t)0x7915e77c, (q31_t)0xd67fe351, (q31_t)0x7913ddd4, (q31_t)0xd679f1c2, + (q31_t)0x7911d3e2, (q31_t)0xd674004e, (q31_t)0x790fc9a4, (q31_t)0xd66e0ef2, (q31_t)0x790dbf1d, (q31_t)0xd6681db1, (q31_t)0x790bb44a, (q31_t)0xd6622c89, + (q31_t)0x7909a92d, (q31_t)0xd65c3b7b, (q31_t)0x79079dc5, (q31_t)0xd6564a87, (q31_t)0x79059212, (q31_t)0xd65059ac, (q31_t)0x79038615, (q31_t)0xd64a68eb, + (q31_t)0x790179cd, (q31_t)0xd6447844, (q31_t)0x78ff6d3b, (q31_t)0xd63e87b6, (q31_t)0x78fd605d, (q31_t)0xd6389742, (q31_t)0x78fb5336, (q31_t)0xd632a6e8, + (q31_t)0x78f945c3, (q31_t)0xd62cb6a8, (q31_t)0x78f73806, (q31_t)0xd626c681, (q31_t)0x78f529fe, (q31_t)0xd620d675, (q31_t)0x78f31bac, (q31_t)0xd61ae682, + (q31_t)0x78f10d0f, (q31_t)0xd614f6a9, (q31_t)0x78eefe28, (q31_t)0xd60f06ea, (q31_t)0x78eceef6, (q31_t)0xd6091745, (q31_t)0x78eadf79, (q31_t)0xd60327b9, + (q31_t)0x78e8cfb2, (q31_t)0xd5fd3848, (q31_t)0x78e6bfa0, (q31_t)0xd5f748f0, (q31_t)0x78e4af44, (q31_t)0xd5f159b3, (q31_t)0x78e29e9d, (q31_t)0xd5eb6a8f, + (q31_t)0x78e08dab, (q31_t)0xd5e57b85, (q31_t)0x78de7c6f, (q31_t)0xd5df8c96, (q31_t)0x78dc6ae8, (q31_t)0xd5d99dc0, (q31_t)0x78da5917, (q31_t)0xd5d3af04, + (q31_t)0x78d846fb, (q31_t)0xd5cdc062, (q31_t)0x78d63495, (q31_t)0xd5c7d1db, (q31_t)0x78d421e4, (q31_t)0xd5c1e36d, (q31_t)0x78d20ee9, (q31_t)0xd5bbf519, + (q31_t)0x78cffba3, (q31_t)0xd5b606e0, (q31_t)0x78cde812, (q31_t)0xd5b018c0, (q31_t)0x78cbd437, (q31_t)0xd5aa2abb, (q31_t)0x78c9c012, (q31_t)0xd5a43cd0, + (q31_t)0x78c7aba2, (q31_t)0xd59e4eff, (q31_t)0x78c596e7, (q31_t)0xd5986148, (q31_t)0x78c381e2, (q31_t)0xd59273ab, (q31_t)0x78c16c93, (q31_t)0xd58c8628, + (q31_t)0x78bf56f9, (q31_t)0xd58698c0, (q31_t)0x78bd4114, (q31_t)0xd580ab72, (q31_t)0x78bb2ae5, (q31_t)0xd57abe3d, (q31_t)0x78b9146c, (q31_t)0xd574d124, + (q31_t)0x78b6fda8, (q31_t)0xd56ee424, (q31_t)0x78b4e69a, (q31_t)0xd568f73f, (q31_t)0x78b2cf41, (q31_t)0xd5630a74, (q31_t)0x78b0b79e, (q31_t)0xd55d1dc3, + (q31_t)0x78ae9fb0, (q31_t)0xd557312d, (q31_t)0x78ac8778, (q31_t)0xd55144b0, (q31_t)0x78aa6ef5, (q31_t)0xd54b584f, (q31_t)0x78a85628, (q31_t)0xd5456c07, + (q31_t)0x78a63d11, (q31_t)0xd53f7fda, (q31_t)0x78a423af, (q31_t)0xd53993c7, (q31_t)0x78a20a03, (q31_t)0xd533a7cf, (q31_t)0x789ff00c, (q31_t)0xd52dbbf1, + (q31_t)0x789dd5cb, (q31_t)0xd527d02e, (q31_t)0x789bbb3f, (q31_t)0xd521e484, (q31_t)0x7899a06a, (q31_t)0xd51bf8f6, (q31_t)0x78978549, (q31_t)0xd5160d82, + (q31_t)0x789569df, (q31_t)0xd5102228, (q31_t)0x78934e2a, (q31_t)0xd50a36e9, (q31_t)0x7891322a, (q31_t)0xd5044bc4, (q31_t)0x788f15e0, (q31_t)0xd4fe60ba, + (q31_t)0x788cf94c, (q31_t)0xd4f875ca, (q31_t)0x788adc6e, (q31_t)0xd4f28af5, (q31_t)0x7888bf45, (q31_t)0xd4eca03a, (q31_t)0x7886a1d1, (q31_t)0xd4e6b59a, + (q31_t)0x78848414, (q31_t)0xd4e0cb15, (q31_t)0x7882660c, (q31_t)0xd4dae0aa, (q31_t)0x788047ba, (q31_t)0xd4d4f65a, (q31_t)0x787e291d, (q31_t)0xd4cf0c24, + (q31_t)0x787c0a36, (q31_t)0xd4c92209, (q31_t)0x7879eb05, (q31_t)0xd4c33809, (q31_t)0x7877cb89, (q31_t)0xd4bd4e23, (q31_t)0x7875abc3, (q31_t)0xd4b76458, + (q31_t)0x78738bb3, (q31_t)0xd4b17aa8, (q31_t)0x78716b59, (q31_t)0xd4ab9112, (q31_t)0x786f4ab4, (q31_t)0xd4a5a798, (q31_t)0x786d29c5, (q31_t)0xd49fbe37, + (q31_t)0x786b088c, (q31_t)0xd499d4f2, (q31_t)0x7868e708, (q31_t)0xd493ebc8, (q31_t)0x7866c53a, (q31_t)0xd48e02b8, (q31_t)0x7864a322, (q31_t)0xd48819c3, + (q31_t)0x786280bf, (q31_t)0xd48230e9, (q31_t)0x78605e13, (q31_t)0xd47c4829, (q31_t)0x785e3b1c, (q31_t)0xd4765f85, (q31_t)0x785c17db, (q31_t)0xd47076fb, + (q31_t)0x7859f44f, (q31_t)0xd46a8e8d, (q31_t)0x7857d079, (q31_t)0xd464a639, (q31_t)0x7855ac5a, (q31_t)0xd45ebe00, (q31_t)0x785387ef, (q31_t)0xd458d5e2, + (q31_t)0x7851633b, (q31_t)0xd452eddf, (q31_t)0x784f3e3c, (q31_t)0xd44d05f6, (q31_t)0x784d18f4, (q31_t)0xd4471e29, (q31_t)0x784af361, (q31_t)0xd4413677, + (q31_t)0x7848cd83, (q31_t)0xd43b4ee0, (q31_t)0x7846a75c, (q31_t)0xd4356763, (q31_t)0x784480ea, (q31_t)0xd42f8002, (q31_t)0x78425a2f, (q31_t)0xd42998bc, + (q31_t)0x78403329, (q31_t)0xd423b191, (q31_t)0x783e0bd9, (q31_t)0xd41dca81, (q31_t)0x783be43e, (q31_t)0xd417e38c, (q31_t)0x7839bc5a, (q31_t)0xd411fcb2, + (q31_t)0x7837942b, (q31_t)0xd40c15f3, (q31_t)0x78356bb2, (q31_t)0xd4062f4f, (q31_t)0x783342ef, (q31_t)0xd40048c6, (q31_t)0x783119e2, (q31_t)0xd3fa6259, + (q31_t)0x782ef08b, (q31_t)0xd3f47c06, (q31_t)0x782cc6ea, (q31_t)0xd3ee95cf, (q31_t)0x782a9cfe, (q31_t)0xd3e8afb3, (q31_t)0x782872c8, (q31_t)0xd3e2c9b2, + (q31_t)0x78264849, (q31_t)0xd3dce3cd, (q31_t)0x78241d7f, (q31_t)0xd3d6fe03, (q31_t)0x7821f26b, (q31_t)0xd3d11853, (q31_t)0x781fc70d, (q31_t)0xd3cb32c0, + (q31_t)0x781d9b65, (q31_t)0xd3c54d47, (q31_t)0x781b6f72, (q31_t)0xd3bf67ea, (q31_t)0x78194336, (q31_t)0xd3b982a8, (q31_t)0x781716b0, (q31_t)0xd3b39d81, + (q31_t)0x7814e9df, (q31_t)0xd3adb876, (q31_t)0x7812bcc4, (q31_t)0xd3a7d385, (q31_t)0x78108f60, (q31_t)0xd3a1eeb1, (q31_t)0x780e61b1, (q31_t)0xd39c09f7, + (q31_t)0x780c33b8, (q31_t)0xd396255a, (q31_t)0x780a0575, (q31_t)0xd39040d7, (q31_t)0x7807d6e9, (q31_t)0xd38a5c70, (q31_t)0x7805a812, (q31_t)0xd3847824, + (q31_t)0x780378f1, (q31_t)0xd37e93f4, (q31_t)0x78014986, (q31_t)0xd378afdf, (q31_t)0x77ff19d1, (q31_t)0xd372cbe6, (q31_t)0x77fce9d2, (q31_t)0xd36ce808, + (q31_t)0x77fab989, (q31_t)0xd3670446, (q31_t)0x77f888f6, (q31_t)0xd361209f, (q31_t)0x77f65819, (q31_t)0xd35b3d13, (q31_t)0x77f426f2, (q31_t)0xd35559a4, + (q31_t)0x77f1f581, (q31_t)0xd34f764f, (q31_t)0x77efc3c5, (q31_t)0xd3499317, (q31_t)0x77ed91c0, (q31_t)0xd343affa, (q31_t)0x77eb5f71, (q31_t)0xd33dccf8, + (q31_t)0x77e92cd9, (q31_t)0xd337ea12, (q31_t)0x77e6f9f6, (q31_t)0xd3320748, (q31_t)0x77e4c6c9, (q31_t)0xd32c2499, (q31_t)0x77e29352, (q31_t)0xd3264206, + (q31_t)0x77e05f91, (q31_t)0xd3205f8f, (q31_t)0x77de2b86, (q31_t)0xd31a7d33, (q31_t)0x77dbf732, (q31_t)0xd3149af3, (q31_t)0x77d9c293, (q31_t)0xd30eb8cf, + (q31_t)0x77d78daa, (q31_t)0xd308d6c7, (q31_t)0x77d55878, (q31_t)0xd302f4da, (q31_t)0x77d322fc, (q31_t)0xd2fd1309, (q31_t)0x77d0ed35, (q31_t)0xd2f73154, + (q31_t)0x77ceb725, (q31_t)0xd2f14fba, (q31_t)0x77cc80cb, (q31_t)0xd2eb6e3c, (q31_t)0x77ca4a27, (q31_t)0xd2e58cdb, (q31_t)0x77c81339, (q31_t)0xd2dfab95, + (q31_t)0x77c5dc01, (q31_t)0xd2d9ca6a, (q31_t)0x77c3a47f, (q31_t)0xd2d3e95c, (q31_t)0x77c16cb4, (q31_t)0xd2ce0869, (q31_t)0x77bf349f, (q31_t)0xd2c82793, + (q31_t)0x77bcfc3f, (q31_t)0xd2c246d8, (q31_t)0x77bac396, (q31_t)0xd2bc6639, (q31_t)0x77b88aa3, (q31_t)0xd2b685b6, (q31_t)0x77b65166, (q31_t)0xd2b0a54f, + (q31_t)0x77b417df, (q31_t)0xd2aac504, (q31_t)0x77b1de0f, (q31_t)0xd2a4e4d5, (q31_t)0x77afa3f5, (q31_t)0xd29f04c2, (q31_t)0x77ad6990, (q31_t)0xd29924cb, + (q31_t)0x77ab2ee2, (q31_t)0xd29344f0, (q31_t)0x77a8f3ea, (q31_t)0xd28d6531, (q31_t)0x77a6b8a9, (q31_t)0xd287858e, (q31_t)0x77a47d1d, (q31_t)0xd281a607, + (q31_t)0x77a24148, (q31_t)0xd27bc69c, (q31_t)0x77a00529, (q31_t)0xd275e74d, (q31_t)0x779dc8c0, (q31_t)0xd270081b, (q31_t)0x779b8c0e, (q31_t)0xd26a2904, + (q31_t)0x77994f11, (q31_t)0xd2644a0a, (q31_t)0x779711cb, (q31_t)0xd25e6b2b, (q31_t)0x7794d43b, (q31_t)0xd2588c69, (q31_t)0x77929661, (q31_t)0xd252adc3, + (q31_t)0x7790583e, (q31_t)0xd24ccf39, (q31_t)0x778e19d0, (q31_t)0xd246f0cb, (q31_t)0x778bdb19, (q31_t)0xd241127a, (q31_t)0x77899c19, (q31_t)0xd23b3444, + (q31_t)0x77875cce, (q31_t)0xd235562b, (q31_t)0x77851d3a, (q31_t)0xd22f782f, (q31_t)0x7782dd5c, (q31_t)0xd2299a4e, (q31_t)0x77809d35, (q31_t)0xd223bc8a, + (q31_t)0x777e5cc3, (q31_t)0xd21ddee2, (q31_t)0x777c1c08, (q31_t)0xd2180156, (q31_t)0x7779db03, (q31_t)0xd21223e7, (q31_t)0x777799b5, (q31_t)0xd20c4694, + (q31_t)0x7775581d, (q31_t)0xd206695d, (q31_t)0x7773163b, (q31_t)0xd2008c43, (q31_t)0x7770d40f, (q31_t)0xd1faaf45, (q31_t)0x776e919a, (q31_t)0xd1f4d263, + (q31_t)0x776c4edb, (q31_t)0xd1eef59e, (q31_t)0x776a0bd3, (q31_t)0xd1e918f5, (q31_t)0x7767c880, (q31_t)0xd1e33c69, (q31_t)0x776584e5, (q31_t)0xd1dd5ff9, + (q31_t)0x776340ff, (q31_t)0xd1d783a6, (q31_t)0x7760fcd0, (q31_t)0xd1d1a76f, (q31_t)0x775eb857, (q31_t)0xd1cbcb54, (q31_t)0x775c7395, (q31_t)0xd1c5ef56, + (q31_t)0x775a2e89, (q31_t)0xd1c01375, (q31_t)0x7757e933, (q31_t)0xd1ba37b0, (q31_t)0x7755a394, (q31_t)0xd1b45c08, (q31_t)0x77535dab, (q31_t)0xd1ae807c, + (q31_t)0x77511778, (q31_t)0xd1a8a50d, (q31_t)0x774ed0fc, (q31_t)0xd1a2c9ba, (q31_t)0x774c8a36, (q31_t)0xd19cee84, (q31_t)0x774a4327, (q31_t)0xd197136b, + (q31_t)0x7747fbce, (q31_t)0xd191386e, (q31_t)0x7745b42c, (q31_t)0xd18b5d8e, (q31_t)0x77436c40, (q31_t)0xd18582ca, (q31_t)0x7741240a, (q31_t)0xd17fa823, + (q31_t)0x773edb8b, (q31_t)0xd179cd99, (q31_t)0x773c92c2, (q31_t)0xd173f32c, (q31_t)0x773a49b0, (q31_t)0xd16e18db, (q31_t)0x77380054, (q31_t)0xd1683ea7, + (q31_t)0x7735b6af, (q31_t)0xd1626490, (q31_t)0x77336cc0, (q31_t)0xd15c8a95, (q31_t)0x77312287, (q31_t)0xd156b0b7, (q31_t)0x772ed805, (q31_t)0xd150d6f6, + (q31_t)0x772c8d3a, (q31_t)0xd14afd52, (q31_t)0x772a4225, (q31_t)0xd14523cb, (q31_t)0x7727f6c6, (q31_t)0xd13f4a60, (q31_t)0x7725ab1f, (q31_t)0xd1397113, + (q31_t)0x77235f2d, (q31_t)0xd13397e2, (q31_t)0x772112f2, (q31_t)0xd12dbece, (q31_t)0x771ec66e, (q31_t)0xd127e5d7, (q31_t)0x771c79a0, (q31_t)0xd1220cfc, + (q31_t)0x771a2c88, (q31_t)0xd11c343f, (q31_t)0x7717df27, (q31_t)0xd1165b9f, (q31_t)0x7715917d, (q31_t)0xd110831b, (q31_t)0x77134389, (q31_t)0xd10aaab5, + (q31_t)0x7710f54c, (q31_t)0xd104d26b, (q31_t)0x770ea6c5, (q31_t)0xd0fefa3f, (q31_t)0x770c57f5, (q31_t)0xd0f9222f, (q31_t)0x770a08dc, (q31_t)0xd0f34a3d, + (q31_t)0x7707b979, (q31_t)0xd0ed7267, (q31_t)0x770569cc, (q31_t)0xd0e79aaf, (q31_t)0x770319d6, (q31_t)0xd0e1c313, (q31_t)0x7700c997, (q31_t)0xd0dbeb95, + (q31_t)0x76fe790e, (q31_t)0xd0d61434, (q31_t)0x76fc283c, (q31_t)0xd0d03cf0, (q31_t)0x76f9d721, (q31_t)0xd0ca65c9, (q31_t)0x76f785bc, (q31_t)0xd0c48ebf, + (q31_t)0x76f5340e, (q31_t)0xd0beb7d2, (q31_t)0x76f2e216, (q31_t)0xd0b8e102, (q31_t)0x76f08fd5, (q31_t)0xd0b30a50, (q31_t)0x76ee3d4b, (q31_t)0xd0ad33ba, + (q31_t)0x76ebea77, (q31_t)0xd0a75d42, (q31_t)0x76e9975a, (q31_t)0xd0a186e7, (q31_t)0x76e743f4, (q31_t)0xd09bb0aa, (q31_t)0x76e4f044, (q31_t)0xd095da89, + (q31_t)0x76e29c4b, (q31_t)0xd0900486, (q31_t)0x76e04808, (q31_t)0xd08a2ea0, (q31_t)0x76ddf37c, (q31_t)0xd08458d7, (q31_t)0x76db9ea7, (q31_t)0xd07e832c, + (q31_t)0x76d94989, (q31_t)0xd078ad9e, (q31_t)0x76d6f421, (q31_t)0xd072d82d, (q31_t)0x76d49e70, (q31_t)0xd06d02da, (q31_t)0x76d24876, (q31_t)0xd0672da3, + (q31_t)0x76cff232, (q31_t)0xd061588b, (q31_t)0x76cd9ba5, (q31_t)0xd05b838f, (q31_t)0x76cb44cf, (q31_t)0xd055aeb1, (q31_t)0x76c8edb0, (q31_t)0xd04fd9f1, + (q31_t)0x76c69647, (q31_t)0xd04a054e, (q31_t)0x76c43e95, (q31_t)0xd04430c8, (q31_t)0x76c1e699, (q31_t)0xd03e5c60, (q31_t)0x76bf8e55, (q31_t)0xd0388815, + (q31_t)0x76bd35c7, (q31_t)0xd032b3e7, (q31_t)0x76badcf0, (q31_t)0xd02cdfd8, (q31_t)0x76b883d0, (q31_t)0xd0270be5, (q31_t)0x76b62a66, (q31_t)0xd0213810, + (q31_t)0x76b3d0b4, (q31_t)0xd01b6459, (q31_t)0x76b176b8, (q31_t)0xd01590bf, (q31_t)0x76af1c72, (q31_t)0xd00fbd43, (q31_t)0x76acc1e4, (q31_t)0xd009e9e4, + (q31_t)0x76aa670d, (q31_t)0xd00416a3, (q31_t)0x76a80bec, (q31_t)0xcffe4380, (q31_t)0x76a5b082, (q31_t)0xcff8707a, (q31_t)0x76a354cf, (q31_t)0xcff29d92, + (q31_t)0x76a0f8d2, (q31_t)0xcfeccac7, (q31_t)0x769e9c8d, (q31_t)0xcfe6f81a, (q31_t)0x769c3ffe, (q31_t)0xcfe1258b, (q31_t)0x7699e326, (q31_t)0xcfdb531a, + (q31_t)0x76978605, (q31_t)0xcfd580c6, (q31_t)0x7695289b, (q31_t)0xcfcfae8f, (q31_t)0x7692cae8, (q31_t)0xcfc9dc77, (q31_t)0x76906ceb, (q31_t)0xcfc40a7c, + (q31_t)0x768e0ea6, (q31_t)0xcfbe389f, (q31_t)0x768bb017, (q31_t)0xcfb866e0, (q31_t)0x7689513f, (q31_t)0xcfb2953f, (q31_t)0x7686f21e, (q31_t)0xcfacc3bb, + (q31_t)0x768492b4, (q31_t)0xcfa6f255, (q31_t)0x76823301, (q31_t)0xcfa1210d, (q31_t)0x767fd304, (q31_t)0xcf9b4fe3, (q31_t)0x767d72bf, (q31_t)0xcf957ed7, + (q31_t)0x767b1231, (q31_t)0xcf8fade9, (q31_t)0x7678b159, (q31_t)0xcf89dd18, (q31_t)0x76765038, (q31_t)0xcf840c65, (q31_t)0x7673eecf, (q31_t)0xcf7e3bd1, + (q31_t)0x76718d1c, (q31_t)0xcf786b5a, (q31_t)0x766f2b20, (q31_t)0xcf729b01, (q31_t)0x766cc8db, (q31_t)0xcf6ccac6, (q31_t)0x766a664d, (q31_t)0xcf66faa9, + (q31_t)0x76680376, (q31_t)0xcf612aaa, (q31_t)0x7665a056, (q31_t)0xcf5b5ac9, (q31_t)0x76633ced, (q31_t)0xcf558b06, (q31_t)0x7660d93b, (q31_t)0xcf4fbb61, + (q31_t)0x765e7540, (q31_t)0xcf49ebda, (q31_t)0x765c10fc, (q31_t)0xcf441c71, (q31_t)0x7659ac6f, (q31_t)0xcf3e4d26, (q31_t)0x76574798, (q31_t)0xcf387dfa, + (q31_t)0x7654e279, (q31_t)0xcf32aeeb, (q31_t)0x76527d11, (q31_t)0xcf2cdffa, (q31_t)0x76501760, (q31_t)0xcf271128, (q31_t)0x764db166, (q31_t)0xcf214274, + (q31_t)0x764b4b23, (q31_t)0xcf1b73de, (q31_t)0x7648e497, (q31_t)0xcf15a566, (q31_t)0x76467dc2, (q31_t)0xcf0fd70c, (q31_t)0x764416a4, (q31_t)0xcf0a08d0, + (q31_t)0x7641af3d, (q31_t)0xcf043ab3, (q31_t)0x763f478d, (q31_t)0xcefe6cb3, (q31_t)0x763cdf94, (q31_t)0xcef89ed2, (q31_t)0x763a7752, (q31_t)0xcef2d110, + (q31_t)0x76380ec8, (q31_t)0xceed036b, (q31_t)0x7635a5f4, (q31_t)0xcee735e5, (q31_t)0x76333cd8, (q31_t)0xcee1687d, (q31_t)0x7630d372, (q31_t)0xcedb9b33, + (q31_t)0x762e69c4, (q31_t)0xced5ce08, (q31_t)0x762bffcd, (q31_t)0xced000fb, (q31_t)0x7629958c, (q31_t)0xceca340c, (q31_t)0x76272b03, (q31_t)0xcec4673c, + (q31_t)0x7624c031, (q31_t)0xcebe9a8a, (q31_t)0x76225517, (q31_t)0xceb8cdf7, (q31_t)0x761fe9b3, (q31_t)0xceb30181, (q31_t)0x761d7e06, (q31_t)0xcead352b, + (q31_t)0x761b1211, (q31_t)0xcea768f2, (q31_t)0x7618a5d3, (q31_t)0xcea19cd8, (q31_t)0x7616394c, (q31_t)0xce9bd0dd, (q31_t)0x7613cc7c, (q31_t)0xce960500, + (q31_t)0x76115f63, (q31_t)0xce903942, (q31_t)0x760ef201, (q31_t)0xce8a6da2, (q31_t)0x760c8457, (q31_t)0xce84a220, (q31_t)0x760a1664, (q31_t)0xce7ed6bd, + (q31_t)0x7607a828, (q31_t)0xce790b79, (q31_t)0x760539a3, (q31_t)0xce734053, (q31_t)0x7602cad5, (q31_t)0xce6d754c, (q31_t)0x76005bbf, (q31_t)0xce67aa63, + (q31_t)0x75fdec60, (q31_t)0xce61df99, (q31_t)0x75fb7cb8, (q31_t)0xce5c14ed, (q31_t)0x75f90cc7, (q31_t)0xce564a60, (q31_t)0x75f69c8d, (q31_t)0xce507ff2, + (q31_t)0x75f42c0b, (q31_t)0xce4ab5a2, (q31_t)0x75f1bb40, (q31_t)0xce44eb71, (q31_t)0x75ef4a2c, (q31_t)0xce3f215f, (q31_t)0x75ecd8cf, (q31_t)0xce39576c, + (q31_t)0x75ea672a, (q31_t)0xce338d97, (q31_t)0x75e7f53c, (q31_t)0xce2dc3e1, (q31_t)0x75e58305, (q31_t)0xce27fa49, (q31_t)0x75e31086, (q31_t)0xce2230d0, + (q31_t)0x75e09dbd, (q31_t)0xce1c6777, (q31_t)0x75de2aac, (q31_t)0xce169e3b, (q31_t)0x75dbb753, (q31_t)0xce10d51f, (q31_t)0x75d943b0, (q31_t)0xce0b0c21, + (q31_t)0x75d6cfc5, (q31_t)0xce054343, (q31_t)0x75d45b92, (q31_t)0xcdff7a83, (q31_t)0x75d1e715, (q31_t)0xcdf9b1e2, (q31_t)0x75cf7250, (q31_t)0xcdf3e95f, + (q31_t)0x75ccfd42, (q31_t)0xcdee20fc, (q31_t)0x75ca87ec, (q31_t)0xcde858b8, (q31_t)0x75c8124d, (q31_t)0xcde29092, (q31_t)0x75c59c65, (q31_t)0xcddcc88b, + (q31_t)0x75c32634, (q31_t)0xcdd700a4, (q31_t)0x75c0afbb, (q31_t)0xcdd138db, (q31_t)0x75be38fa, (q31_t)0xcdcb7131, (q31_t)0x75bbc1ef, (q31_t)0xcdc5a9a6, + (q31_t)0x75b94a9c, (q31_t)0xcdbfe23a, (q31_t)0x75b6d301, (q31_t)0xcdba1aee, (q31_t)0x75b45b1d, (q31_t)0xcdb453c0, (q31_t)0x75b1e2f0, (q31_t)0xcdae8cb1, + (q31_t)0x75af6a7b, (q31_t)0xcda8c5c1, (q31_t)0x75acf1bd, (q31_t)0xcda2fef0, (q31_t)0x75aa78b6, (q31_t)0xcd9d383f, (q31_t)0x75a7ff67, (q31_t)0xcd9771ac, + (q31_t)0x75a585cf, (q31_t)0xcd91ab39, (q31_t)0x75a30bef, (q31_t)0xcd8be4e4, (q31_t)0x75a091c6, (q31_t)0xcd861eaf, (q31_t)0x759e1755, (q31_t)0xcd805899, + (q31_t)0x759b9c9b, (q31_t)0xcd7a92a2, (q31_t)0x75992198, (q31_t)0xcd74ccca, (q31_t)0x7596a64d, (q31_t)0xcd6f0711, (q31_t)0x75942ab9, (q31_t)0xcd694178, + (q31_t)0x7591aedd, (q31_t)0xcd637bfe, (q31_t)0x758f32b9, (q31_t)0xcd5db6a3, (q31_t)0x758cb64c, (q31_t)0xcd57f167, (q31_t)0x758a3996, (q31_t)0xcd522c4a, + (q31_t)0x7587bc98, (q31_t)0xcd4c674d, (q31_t)0x75853f51, (q31_t)0xcd46a26f, (q31_t)0x7582c1c2, (q31_t)0xcd40ddb0, (q31_t)0x758043ea, (q31_t)0xcd3b1911, + (q31_t)0x757dc5ca, (q31_t)0xcd355491, (q31_t)0x757b4762, (q31_t)0xcd2f9030, (q31_t)0x7578c8b0, (q31_t)0xcd29cbee, (q31_t)0x757649b7, (q31_t)0xcd2407cc, + (q31_t)0x7573ca75, (q31_t)0xcd1e43ca, (q31_t)0x75714aea, (q31_t)0xcd187fe6, (q31_t)0x756ecb18, (q31_t)0xcd12bc22, (q31_t)0x756c4afc, (q31_t)0xcd0cf87e, + (q31_t)0x7569ca99, (q31_t)0xcd0734f9, (q31_t)0x756749ec, (q31_t)0xcd017193, (q31_t)0x7564c8f8, (q31_t)0xccfbae4d, (q31_t)0x756247bb, (q31_t)0xccf5eb26, + (q31_t)0x755fc635, (q31_t)0xccf0281f, (q31_t)0x755d4467, (q31_t)0xccea6538, (q31_t)0x755ac251, (q31_t)0xcce4a26f, (q31_t)0x75583ff3, (q31_t)0xccdedfc7, + (q31_t)0x7555bd4c, (q31_t)0xccd91d3d, (q31_t)0x75533a5c, (q31_t)0xccd35ad4, (q31_t)0x7550b725, (q31_t)0xcccd988a, (q31_t)0x754e33a4, (q31_t)0xccc7d65f, + (q31_t)0x754bafdc, (q31_t)0xccc21455, (q31_t)0x75492bcb, (q31_t)0xccbc5269, (q31_t)0x7546a772, (q31_t)0xccb6909e, (q31_t)0x754422d0, (q31_t)0xccb0cef2, + (q31_t)0x75419de7, (q31_t)0xccab0d65, (q31_t)0x753f18b4, (q31_t)0xcca54bf9, (q31_t)0x753c933a, (q31_t)0xcc9f8aac, (q31_t)0x753a0d77, (q31_t)0xcc99c97e, + (q31_t)0x7537876c, (q31_t)0xcc940871, (q31_t)0x75350118, (q31_t)0xcc8e4783, (q31_t)0x75327a7d, (q31_t)0xcc8886b5, (q31_t)0x752ff399, (q31_t)0xcc82c607, + (q31_t)0x752d6c6c, (q31_t)0xcc7d0578, (q31_t)0x752ae4f8, (q31_t)0xcc774509, (q31_t)0x75285d3b, (q31_t)0xcc7184ba, (q31_t)0x7525d536, (q31_t)0xcc6bc48b, + (q31_t)0x75234ce8, (q31_t)0xcc66047b, (q31_t)0x7520c453, (q31_t)0xcc60448c, (q31_t)0x751e3b75, (q31_t)0xcc5a84bc, (q31_t)0x751bb24f, (q31_t)0xcc54c50c, + (q31_t)0x751928e0, (q31_t)0xcc4f057c, (q31_t)0x75169f2a, (q31_t)0xcc49460c, (q31_t)0x7514152b, (q31_t)0xcc4386bc, (q31_t)0x75118ae4, (q31_t)0xcc3dc78b, + (q31_t)0x750f0054, (q31_t)0xcc38087b, (q31_t)0x750c757d, (q31_t)0xcc32498a, (q31_t)0x7509ea5d, (q31_t)0xcc2c8aba, (q31_t)0x75075ef5, (q31_t)0xcc26cc09, + (q31_t)0x7504d345, (q31_t)0xcc210d79, (q31_t)0x7502474d, (q31_t)0xcc1b4f08, (q31_t)0x74ffbb0d, (q31_t)0xcc1590b8, (q31_t)0x74fd2e84, (q31_t)0xcc0fd287, + (q31_t)0x74faa1b3, (q31_t)0xcc0a1477, (q31_t)0x74f8149a, (q31_t)0xcc045686, (q31_t)0x74f58739, (q31_t)0xcbfe98b6, (q31_t)0x74f2f990, (q31_t)0xcbf8db05, + (q31_t)0x74f06b9e, (q31_t)0xcbf31d75, (q31_t)0x74eddd65, (q31_t)0xcbed6005, (q31_t)0x74eb4ee3, (q31_t)0xcbe7a2b5, (q31_t)0x74e8c01a, (q31_t)0xcbe1e585, + (q31_t)0x74e63108, (q31_t)0xcbdc2876, (q31_t)0x74e3a1ae, (q31_t)0xcbd66b86, (q31_t)0x74e1120c, (q31_t)0xcbd0aeb7, (q31_t)0x74de8221, (q31_t)0xcbcaf208, + (q31_t)0x74dbf1ef, (q31_t)0xcbc53579, (q31_t)0x74d96175, (q31_t)0xcbbf790a, (q31_t)0x74d6d0b2, (q31_t)0xcbb9bcbb, (q31_t)0x74d43fa8, (q31_t)0xcbb4008d, + (q31_t)0x74d1ae55, (q31_t)0xcbae447f, (q31_t)0x74cf1cbb, (q31_t)0xcba88891, (q31_t)0x74cc8ad8, (q31_t)0xcba2ccc4, (q31_t)0x74c9f8ad, (q31_t)0xcb9d1117, + (q31_t)0x74c7663a, (q31_t)0xcb97558a, (q31_t)0x74c4d380, (q31_t)0xcb919a1d, (q31_t)0x74c2407d, (q31_t)0xcb8bded1, (q31_t)0x74bfad32, (q31_t)0xcb8623a5, + (q31_t)0x74bd199f, (q31_t)0xcb80689a, (q31_t)0x74ba85c4, (q31_t)0xcb7aadaf, (q31_t)0x74b7f1a1, (q31_t)0xcb74f2e4, (q31_t)0x74b55d36, (q31_t)0xcb6f383a, + (q31_t)0x74b2c884, (q31_t)0xcb697db0, (q31_t)0x74b03389, (q31_t)0xcb63c347, (q31_t)0x74ad9e46, (q31_t)0xcb5e08fe, (q31_t)0x74ab08bb, (q31_t)0xcb584ed6, + (q31_t)0x74a872e8, (q31_t)0xcb5294ce, (q31_t)0x74a5dccd, (q31_t)0xcb4cdae6, (q31_t)0x74a3466b, (q31_t)0xcb47211f, (q31_t)0x74a0afc0, (q31_t)0xcb416779, + (q31_t)0x749e18cd, (q31_t)0xcb3badf3, (q31_t)0x749b8193, (q31_t)0xcb35f48d, (q31_t)0x7498ea11, (q31_t)0xcb303b49, (q31_t)0x74965246, (q31_t)0xcb2a8224, + (q31_t)0x7493ba34, (q31_t)0xcb24c921, (q31_t)0x749121da, (q31_t)0xcb1f103e, (q31_t)0x748e8938, (q31_t)0xcb19577b, (q31_t)0x748bf04d, (q31_t)0xcb139ed9, + (q31_t)0x7489571c, (q31_t)0xcb0de658, (q31_t)0x7486bda2, (q31_t)0xcb082df8, (q31_t)0x748423e0, (q31_t)0xcb0275b8, (q31_t)0x748189d7, (q31_t)0xcafcbd99, + (q31_t)0x747eef85, (q31_t)0xcaf7059a, (q31_t)0x747c54ec, (q31_t)0xcaf14dbd, (q31_t)0x7479ba0b, (q31_t)0xcaeb9600, (q31_t)0x74771ee2, (q31_t)0xcae5de64, + (q31_t)0x74748371, (q31_t)0xcae026e8, (q31_t)0x7471e7b8, (q31_t)0xcada6f8d, (q31_t)0x746f4bb8, (q31_t)0xcad4b853, (q31_t)0x746caf70, (q31_t)0xcacf013a, + (q31_t)0x746a12df, (q31_t)0xcac94a42, (q31_t)0x74677608, (q31_t)0xcac3936b, (q31_t)0x7464d8e8, (q31_t)0xcabddcb4, (q31_t)0x74623b80, (q31_t)0xcab8261e, + (q31_t)0x745f9dd1, (q31_t)0xcab26fa9, (q31_t)0x745cffda, (q31_t)0xcaacb955, (q31_t)0x745a619b, (q31_t)0xcaa70322, (q31_t)0x7457c314, (q31_t)0xcaa14d10, + (q31_t)0x74552446, (q31_t)0xca9b971e, (q31_t)0x74528530, (q31_t)0xca95e14e, (q31_t)0x744fe5d2, (q31_t)0xca902b9f, (q31_t)0x744d462c, (q31_t)0xca8a7610, + (q31_t)0x744aa63f, (q31_t)0xca84c0a3, (q31_t)0x7448060a, (q31_t)0xca7f0b56, (q31_t)0x7445658d, (q31_t)0xca79562b, (q31_t)0x7442c4c8, (q31_t)0xca73a120, + (q31_t)0x744023bc, (q31_t)0xca6dec37, (q31_t)0x743d8268, (q31_t)0xca68376e, (q31_t)0x743ae0cc, (q31_t)0xca6282c7, (q31_t)0x74383ee9, (q31_t)0xca5cce40, + (q31_t)0x74359cbd, (q31_t)0xca5719db, (q31_t)0x7432fa4b, (q31_t)0xca516597, (q31_t)0x74305790, (q31_t)0xca4bb174, (q31_t)0x742db48e, (q31_t)0xca45fd72, + (q31_t)0x742b1144, (q31_t)0xca404992, (q31_t)0x74286db3, (q31_t)0xca3a95d2, (q31_t)0x7425c9da, (q31_t)0xca34e234, (q31_t)0x742325b9, (q31_t)0xca2f2eb6, + (q31_t)0x74208150, (q31_t)0xca297b5a, (q31_t)0x741ddca0, (q31_t)0xca23c820, (q31_t)0x741b37a9, (q31_t)0xca1e1506, (q31_t)0x74189269, (q31_t)0xca18620e, + (q31_t)0x7415ece2, (q31_t)0xca12af37, (q31_t)0x74134714, (q31_t)0xca0cfc81, (q31_t)0x7410a0fe, (q31_t)0xca0749ec, (q31_t)0x740dfaa0, (q31_t)0xca019779, + (q31_t)0x740b53fb, (q31_t)0xc9fbe527, (q31_t)0x7408ad0e, (q31_t)0xc9f632f6, (q31_t)0x740605d9, (q31_t)0xc9f080e7, (q31_t)0x74035e5d, (q31_t)0xc9eacef9, + (q31_t)0x7400b69a, (q31_t)0xc9e51d2d, (q31_t)0x73fe0e8f, (q31_t)0xc9df6b81, (q31_t)0x73fb663c, (q31_t)0xc9d9b9f7, (q31_t)0x73f8bda2, (q31_t)0xc9d4088f, + (q31_t)0x73f614c0, (q31_t)0xc9ce5748, (q31_t)0x73f36b97, (q31_t)0xc9c8a622, (q31_t)0x73f0c226, (q31_t)0xc9c2f51e, (q31_t)0x73ee186e, (q31_t)0xc9bd443c, + (q31_t)0x73eb6e6e, (q31_t)0xc9b7937a, (q31_t)0x73e8c426, (q31_t)0xc9b1e2db, (q31_t)0x73e61997, (q31_t)0xc9ac325d, (q31_t)0x73e36ec1, (q31_t)0xc9a68200, + (q31_t)0x73e0c3a3, (q31_t)0xc9a0d1c5, (q31_t)0x73de183e, (q31_t)0xc99b21ab, (q31_t)0x73db6c91, (q31_t)0xc99571b3, (q31_t)0x73d8c09d, (q31_t)0xc98fc1dc, + (q31_t)0x73d61461, (q31_t)0xc98a1227, (q31_t)0x73d367de, (q31_t)0xc9846294, (q31_t)0x73d0bb13, (q31_t)0xc97eb322, (q31_t)0x73ce0e01, (q31_t)0xc97903d2, + (q31_t)0x73cb60a8, (q31_t)0xc97354a4, (q31_t)0x73c8b307, (q31_t)0xc96da597, (q31_t)0x73c6051f, (q31_t)0xc967f6ac, (q31_t)0x73c356ef, (q31_t)0xc96247e2, + (q31_t)0x73c0a878, (q31_t)0xc95c993a, (q31_t)0x73bdf9b9, (q31_t)0xc956eab4, (q31_t)0x73bb4ab3, (q31_t)0xc9513c50, (q31_t)0x73b89b66, (q31_t)0xc94b8e0d, + (q31_t)0x73b5ebd1, (q31_t)0xc945dfec, (q31_t)0x73b33bf5, (q31_t)0xc94031ed, (q31_t)0x73b08bd1, (q31_t)0xc93a8410, (q31_t)0x73addb67, (q31_t)0xc934d654, + (q31_t)0x73ab2ab4, (q31_t)0xc92f28ba, (q31_t)0x73a879bb, (q31_t)0xc9297b42, (q31_t)0x73a5c87a, (q31_t)0xc923cdec, (q31_t)0x73a316f2, (q31_t)0xc91e20b8, + (q31_t)0x73a06522, (q31_t)0xc91873a5, (q31_t)0x739db30b, (q31_t)0xc912c6b5, (q31_t)0x739b00ad, (q31_t)0xc90d19e6, (q31_t)0x73984e07, (q31_t)0xc9076d39, + (q31_t)0x73959b1b, (q31_t)0xc901c0ae, (q31_t)0x7392e7e6, (q31_t)0xc8fc1445, (q31_t)0x7390346b, (q31_t)0xc8f667fe, (q31_t)0x738d80a8, (q31_t)0xc8f0bbd9, + (q31_t)0x738acc9e, (q31_t)0xc8eb0fd6, (q31_t)0x7388184d, (q31_t)0xc8e563f5, (q31_t)0x738563b5, (q31_t)0xc8dfb836, (q31_t)0x7382aed5, (q31_t)0xc8da0c99, + (q31_t)0x737ff9ae, (q31_t)0xc8d4611d, (q31_t)0x737d4440, (q31_t)0xc8ceb5c4, (q31_t)0x737a8e8a, (q31_t)0xc8c90a8d, (q31_t)0x7377d88d, (q31_t)0xc8c35f78, + (q31_t)0x73752249, (q31_t)0xc8bdb485, (q31_t)0x73726bbe, (q31_t)0xc8b809b4, (q31_t)0x736fb4ec, (q31_t)0xc8b25f06, (q31_t)0x736cfdd2, (q31_t)0xc8acb479, + (q31_t)0x736a4671, (q31_t)0xc8a70a0e, (q31_t)0x73678ec9, (q31_t)0xc8a15fc6, (q31_t)0x7364d6da, (q31_t)0xc89bb5a0, (q31_t)0x73621ea4, (q31_t)0xc8960b9c, + (q31_t)0x735f6626, (q31_t)0xc89061ba, (q31_t)0x735cad61, (q31_t)0xc88ab7fa, (q31_t)0x7359f456, (q31_t)0xc8850e5d, (q31_t)0x73573b03, (q31_t)0xc87f64e2, + (q31_t)0x73548168, (q31_t)0xc879bb89, (q31_t)0x7351c787, (q31_t)0xc8741252, (q31_t)0x734f0d5f, (q31_t)0xc86e693d, (q31_t)0x734c52ef, (q31_t)0xc868c04b, + (q31_t)0x73499838, (q31_t)0xc863177b, (q31_t)0x7346dd3a, (q31_t)0xc85d6ece, (q31_t)0x734421f6, (q31_t)0xc857c642, (q31_t)0x7341666a, (q31_t)0xc8521dd9, + (q31_t)0x733eaa96, (q31_t)0xc84c7593, (q31_t)0x733bee7c, (q31_t)0xc846cd6e, (q31_t)0x7339321b, (q31_t)0xc841256d, (q31_t)0x73367572, (q31_t)0xc83b7d8d, + (q31_t)0x7333b883, (q31_t)0xc835d5d0, (q31_t)0x7330fb4d, (q31_t)0xc8302e35, (q31_t)0x732e3dcf, (q31_t)0xc82a86bd, (q31_t)0x732b800a, (q31_t)0xc824df67, + (q31_t)0x7328c1ff, (q31_t)0xc81f3834, (q31_t)0x732603ac, (q31_t)0xc8199123, (q31_t)0x73234512, (q31_t)0xc813ea35, (q31_t)0x73208632, (q31_t)0xc80e4369, + (q31_t)0x731dc70a, (q31_t)0xc8089cbf, (q31_t)0x731b079b, (q31_t)0xc802f638, (q31_t)0x731847e5, (q31_t)0xc7fd4fd4, (q31_t)0x731587e8, (q31_t)0xc7f7a992, + (q31_t)0x7312c7a5, (q31_t)0xc7f20373, (q31_t)0x7310071a, (q31_t)0xc7ec5d76, (q31_t)0x730d4648, (q31_t)0xc7e6b79c, (q31_t)0x730a8530, (q31_t)0xc7e111e5, + (q31_t)0x7307c3d0, (q31_t)0xc7db6c50, (q31_t)0x73050229, (q31_t)0xc7d5c6de, (q31_t)0x7302403c, (q31_t)0xc7d0218e, (q31_t)0x72ff7e07, (q31_t)0xc7ca7c61, + (q31_t)0x72fcbb8c, (q31_t)0xc7c4d757, (q31_t)0x72f9f8c9, (q31_t)0xc7bf3270, (q31_t)0x72f735c0, (q31_t)0xc7b98dab, (q31_t)0x72f47270, (q31_t)0xc7b3e909, + (q31_t)0x72f1aed9, (q31_t)0xc7ae4489, (q31_t)0x72eeeafb, (q31_t)0xc7a8a02c, (q31_t)0x72ec26d6, (q31_t)0xc7a2fbf3, (q31_t)0x72e9626a, (q31_t)0xc79d57db, + (q31_t)0x72e69db7, (q31_t)0xc797b3e7, (q31_t)0x72e3d8be, (q31_t)0xc7921015, (q31_t)0x72e1137d, (q31_t)0xc78c6c67, (q31_t)0x72de4df6, (q31_t)0xc786c8db, + (q31_t)0x72db8828, (q31_t)0xc7812572, (q31_t)0x72d8c213, (q31_t)0xc77b822b, (q31_t)0x72d5fbb7, (q31_t)0xc775df08, (q31_t)0x72d33514, (q31_t)0xc7703c08, + (q31_t)0x72d06e2b, (q31_t)0xc76a992a, (q31_t)0x72cda6fb, (q31_t)0xc764f66f, (q31_t)0x72cadf83, (q31_t)0xc75f53d7, (q31_t)0x72c817c6, (q31_t)0xc759b163, + (q31_t)0x72c54fc1, (q31_t)0xc7540f11, (q31_t)0x72c28775, (q31_t)0xc74e6ce2, (q31_t)0x72bfbee3, (q31_t)0xc748cad6, (q31_t)0x72bcf60a, (q31_t)0xc74328ed, + (q31_t)0x72ba2cea, (q31_t)0xc73d8727, (q31_t)0x72b76383, (q31_t)0xc737e584, (q31_t)0x72b499d6, (q31_t)0xc7324404, (q31_t)0x72b1cfe1, (q31_t)0xc72ca2a7, + (q31_t)0x72af05a7, (q31_t)0xc727016d, (q31_t)0x72ac3b25, (q31_t)0xc7216056, (q31_t)0x72a9705c, (q31_t)0xc71bbf62, (q31_t)0x72a6a54d, (q31_t)0xc7161e92, + (q31_t)0x72a3d9f7, (q31_t)0xc7107de4, (q31_t)0x72a10e5b, (q31_t)0xc70add5a, (q31_t)0x729e4277, (q31_t)0xc7053cf2, (q31_t)0x729b764d, (q31_t)0xc6ff9cae, + (q31_t)0x7298a9dd, (q31_t)0xc6f9fc8d, (q31_t)0x7295dd25, (q31_t)0xc6f45c8f, (q31_t)0x72931027, (q31_t)0xc6eebcb5, (q31_t)0x729042e3, (q31_t)0xc6e91cfd, + (q31_t)0x728d7557, (q31_t)0xc6e37d69, (q31_t)0x728aa785, (q31_t)0xc6ddddf8, (q31_t)0x7287d96c, (q31_t)0xc6d83eab, (q31_t)0x72850b0d, (q31_t)0xc6d29f80, + (q31_t)0x72823c67, (q31_t)0xc6cd0079, (q31_t)0x727f6d7a, (q31_t)0xc6c76195, (q31_t)0x727c9e47, (q31_t)0xc6c1c2d4, (q31_t)0x7279cecd, (q31_t)0xc6bc2437, + (q31_t)0x7276ff0d, (q31_t)0xc6b685bd, (q31_t)0x72742f05, (q31_t)0xc6b0e767, (q31_t)0x72715eb8, (q31_t)0xc6ab4933, (q31_t)0x726e8e23, (q31_t)0xc6a5ab23, + (q31_t)0x726bbd48, (q31_t)0xc6a00d37, (q31_t)0x7268ec27, (q31_t)0xc69a6f6e, (q31_t)0x72661abf, (q31_t)0xc694d1c8, (q31_t)0x72634910, (q31_t)0xc68f3446, + (q31_t)0x7260771b, (q31_t)0xc68996e7, (q31_t)0x725da4df, (q31_t)0xc683f9ab, (q31_t)0x725ad25d, (q31_t)0xc67e5c93, (q31_t)0x7257ff94, (q31_t)0xc678bf9f, + (q31_t)0x72552c85, (q31_t)0xc67322ce, (q31_t)0x7252592f, (q31_t)0xc66d8620, (q31_t)0x724f8593, (q31_t)0xc667e996, (q31_t)0x724cb1b0, (q31_t)0xc6624d30, + (q31_t)0x7249dd86, (q31_t)0xc65cb0ed, (q31_t)0x72470916, (q31_t)0xc65714cd, (q31_t)0x72443460, (q31_t)0xc65178d1, (q31_t)0x72415f63, (q31_t)0xc64bdcf9, + (q31_t)0x723e8a20, (q31_t)0xc6464144, (q31_t)0x723bb496, (q31_t)0xc640a5b3, (q31_t)0x7238dec5, (q31_t)0xc63b0a46, (q31_t)0x723608af, (q31_t)0xc6356efc, + (q31_t)0x72333251, (q31_t)0xc62fd3d6, (q31_t)0x72305bae, (q31_t)0xc62a38d4, (q31_t)0x722d84c4, (q31_t)0xc6249df5, (q31_t)0x722aad93, (q31_t)0xc61f033a, + (q31_t)0x7227d61c, (q31_t)0xc61968a2, (q31_t)0x7224fe5f, (q31_t)0xc613ce2f, (q31_t)0x7222265b, (q31_t)0xc60e33df, (q31_t)0x721f4e11, (q31_t)0xc60899b2, + (q31_t)0x721c7580, (q31_t)0xc602ffaa, (q31_t)0x72199ca9, (q31_t)0xc5fd65c5, (q31_t)0x7216c38c, (q31_t)0xc5f7cc04, (q31_t)0x7213ea28, (q31_t)0xc5f23267, + (q31_t)0x7211107e, (q31_t)0xc5ec98ee, (q31_t)0x720e368d, (q31_t)0xc5e6ff98, (q31_t)0x720b5c57, (q31_t)0xc5e16667, (q31_t)0x720881d9, (q31_t)0xc5dbcd59, + (q31_t)0x7205a716, (q31_t)0xc5d6346f, (q31_t)0x7202cc0c, (q31_t)0xc5d09ba9, (q31_t)0x71fff0bc, (q31_t)0xc5cb0307, (q31_t)0x71fd1525, (q31_t)0xc5c56a89, + (q31_t)0x71fa3949, (q31_t)0xc5bfd22e, (q31_t)0x71f75d25, (q31_t)0xc5ba39f8, (q31_t)0x71f480bc, (q31_t)0xc5b4a1e5, (q31_t)0x71f1a40c, (q31_t)0xc5af09f7, + (q31_t)0x71eec716, (q31_t)0xc5a9722c, (q31_t)0x71ebe9da, (q31_t)0xc5a3da86, (q31_t)0x71e90c57, (q31_t)0xc59e4303, (q31_t)0x71e62e8f, (q31_t)0xc598aba5, + (q31_t)0x71e35080, (q31_t)0xc593146a, (q31_t)0x71e0722a, (q31_t)0xc58d7d54, (q31_t)0x71dd938f, (q31_t)0xc587e661, (q31_t)0x71dab4ad, (q31_t)0xc5824f93, + (q31_t)0x71d7d585, (q31_t)0xc57cb8e9, (q31_t)0x71d4f617, (q31_t)0xc5772263, (q31_t)0x71d21662, (q31_t)0xc5718c00, (q31_t)0x71cf3667, (q31_t)0xc56bf5c2, + (q31_t)0x71cc5626, (q31_t)0xc5665fa9, (q31_t)0x71c9759f, (q31_t)0xc560c9b3, (q31_t)0x71c694d2, (q31_t)0xc55b33e2, (q31_t)0x71c3b3bf, (q31_t)0xc5559e34, + (q31_t)0x71c0d265, (q31_t)0xc55008ab, (q31_t)0x71bdf0c5, (q31_t)0xc54a7346, (q31_t)0x71bb0edf, (q31_t)0xc544de05, (q31_t)0x71b82cb3, (q31_t)0xc53f48e9, + (q31_t)0x71b54a41, (q31_t)0xc539b3f1, (q31_t)0x71b26788, (q31_t)0xc5341f1d, (q31_t)0x71af848a, (q31_t)0xc52e8a6d, (q31_t)0x71aca145, (q31_t)0xc528f5e1, + (q31_t)0x71a9bdba, (q31_t)0xc523617a, (q31_t)0x71a6d9e9, (q31_t)0xc51dcd37, (q31_t)0x71a3f5d2, (q31_t)0xc5183919, (q31_t)0x71a11175, (q31_t)0xc512a51f, + (q31_t)0x719e2cd2, (q31_t)0xc50d1149, (q31_t)0x719b47e9, (q31_t)0xc5077d97, (q31_t)0x719862b9, (q31_t)0xc501ea0a, (q31_t)0x71957d44, (q31_t)0xc4fc56a2, + (q31_t)0x71929789, (q31_t)0xc4f6c35d, (q31_t)0x718fb187, (q31_t)0xc4f1303d, (q31_t)0x718ccb3f, (q31_t)0xc4eb9d42, (q31_t)0x7189e4b2, (q31_t)0xc4e60a6b, + (q31_t)0x7186fdde, (q31_t)0xc4e077b8, (q31_t)0x718416c4, (q31_t)0xc4dae52a, (q31_t)0x71812f65, (q31_t)0xc4d552c1, (q31_t)0x717e47bf, (q31_t)0xc4cfc07c, + (q31_t)0x717b5fd3, (q31_t)0xc4ca2e5b, (q31_t)0x717877a1, (q31_t)0xc4c49c5f, (q31_t)0x71758f29, (q31_t)0xc4bf0a87, (q31_t)0x7172a66c, (q31_t)0xc4b978d4, + (q31_t)0x716fbd68, (q31_t)0xc4b3e746, (q31_t)0x716cd41e, (q31_t)0xc4ae55dc, (q31_t)0x7169ea8f, (q31_t)0xc4a8c497, (q31_t)0x716700b9, (q31_t)0xc4a33376, + (q31_t)0x7164169d, (q31_t)0xc49da27a, (q31_t)0x71612c3c, (q31_t)0xc49811a3, (q31_t)0x715e4194, (q31_t)0xc49280f0, (q31_t)0x715b56a7, (q31_t)0xc48cf062, + (q31_t)0x71586b74, (q31_t)0xc4875ff9, (q31_t)0x71557ffa, (q31_t)0xc481cfb4, (q31_t)0x7152943b, (q31_t)0xc47c3f94, (q31_t)0x714fa836, (q31_t)0xc476af98, + (q31_t)0x714cbbeb, (q31_t)0xc4711fc2, (q31_t)0x7149cf5a, (q31_t)0xc46b9010, (q31_t)0x7146e284, (q31_t)0xc4660083, (q31_t)0x7143f567, (q31_t)0xc460711b, + (q31_t)0x71410805, (q31_t)0xc45ae1d7, (q31_t)0x713e1a5c, (q31_t)0xc45552b8, (q31_t)0x713b2c6e, (q31_t)0xc44fc3be, (q31_t)0x71383e3a, (q31_t)0xc44a34e9, + (q31_t)0x71354fc0, (q31_t)0xc444a639, (q31_t)0x71326101, (q31_t)0xc43f17ad, (q31_t)0x712f71fb, (q31_t)0xc4398947, (q31_t)0x712c82b0, (q31_t)0xc433fb05, + (q31_t)0x7129931f, (q31_t)0xc42e6ce8, (q31_t)0x7126a348, (q31_t)0xc428def0, (q31_t)0x7123b32b, (q31_t)0xc423511d, (q31_t)0x7120c2c8, (q31_t)0xc41dc36f, + (q31_t)0x711dd220, (q31_t)0xc41835e6, (q31_t)0x711ae132, (q31_t)0xc412a882, (q31_t)0x7117effe, (q31_t)0xc40d1b42, (q31_t)0x7114fe84, (q31_t)0xc4078e28, + (q31_t)0x71120cc5, (q31_t)0xc4020133, (q31_t)0x710f1ac0, (q31_t)0xc3fc7462, (q31_t)0x710c2875, (q31_t)0xc3f6e7b7, (q31_t)0x710935e4, (q31_t)0xc3f15b31, + (q31_t)0x7106430e, (q31_t)0xc3ebced0, (q31_t)0x71034ff2, (q31_t)0xc3e64294, (q31_t)0x71005c90, (q31_t)0xc3e0b67d, (q31_t)0x70fd68e9, (q31_t)0xc3db2a8b, + (q31_t)0x70fa74fc, (q31_t)0xc3d59ebe, (q31_t)0x70f780c9, (q31_t)0xc3d01316, (q31_t)0x70f48c50, (q31_t)0xc3ca8793, (q31_t)0x70f19792, (q31_t)0xc3c4fc36, + (q31_t)0x70eea28e, (q31_t)0xc3bf70fd, (q31_t)0x70ebad45, (q31_t)0xc3b9e5ea, (q31_t)0x70e8b7b5, (q31_t)0xc3b45afc, (q31_t)0x70e5c1e1, (q31_t)0xc3aed034, + (q31_t)0x70e2cbc6, (q31_t)0xc3a94590, (q31_t)0x70dfd566, (q31_t)0xc3a3bb12, (q31_t)0x70dcdec0, (q31_t)0xc39e30b8, (q31_t)0x70d9e7d5, (q31_t)0xc398a685, + (q31_t)0x70d6f0a4, (q31_t)0xc3931c76, (q31_t)0x70d3f92d, (q31_t)0xc38d928d, (q31_t)0x70d10171, (q31_t)0xc38808c9, (q31_t)0x70ce096f, (q31_t)0xc3827f2a, + (q31_t)0x70cb1128, (q31_t)0xc37cf5b0, (q31_t)0x70c8189b, (q31_t)0xc3776c5c, (q31_t)0x70c51fc8, (q31_t)0xc371e32d, (q31_t)0x70c226b0, (q31_t)0xc36c5a24, + (q31_t)0x70bf2d53, (q31_t)0xc366d140, (q31_t)0x70bc33b0, (q31_t)0xc3614881, (q31_t)0x70b939c7, (q31_t)0xc35bbfe8, (q31_t)0x70b63f99, (q31_t)0xc3563774, + (q31_t)0x70b34525, (q31_t)0xc350af26, (q31_t)0x70b04a6b, (q31_t)0xc34b26fc, (q31_t)0x70ad4f6d, (q31_t)0xc3459ef9, (q31_t)0x70aa5428, (q31_t)0xc340171b, + (q31_t)0x70a7589f, (q31_t)0xc33a8f62, (q31_t)0x70a45ccf, (q31_t)0xc33507cf, (q31_t)0x70a160ba, (q31_t)0xc32f8061, (q31_t)0x709e6460, (q31_t)0xc329f919, + (q31_t)0x709b67c0, (q31_t)0xc32471f7, (q31_t)0x70986adb, (q31_t)0xc31eeaf9, (q31_t)0x70956db1, (q31_t)0xc3196422, (q31_t)0x70927041, (q31_t)0xc313dd70, + (q31_t)0x708f728b, (q31_t)0xc30e56e4, (q31_t)0x708c7490, (q31_t)0xc308d07d, (q31_t)0x70897650, (q31_t)0xc3034a3c, (q31_t)0x708677ca, (q31_t)0xc2fdc420, + (q31_t)0x708378ff, (q31_t)0xc2f83e2a, (q31_t)0x708079ee, (q31_t)0xc2f2b85a, (q31_t)0x707d7a98, (q31_t)0xc2ed32af, (q31_t)0x707a7afd, (q31_t)0xc2e7ad2a, + (q31_t)0x70777b1c, (q31_t)0xc2e227cb, (q31_t)0x70747af6, (q31_t)0xc2dca291, (q31_t)0x70717a8a, (q31_t)0xc2d71d7e, (q31_t)0x706e79d9, (q31_t)0xc2d1988f, + (q31_t)0x706b78e3, (q31_t)0xc2cc13c7, (q31_t)0x706877a7, (q31_t)0xc2c68f24, (q31_t)0x70657626, (q31_t)0xc2c10aa7, (q31_t)0x70627460, (q31_t)0xc2bb8650, + (q31_t)0x705f7255, (q31_t)0xc2b6021f, (q31_t)0x705c7004, (q31_t)0xc2b07e14, (q31_t)0x70596d6d, (q31_t)0xc2aafa2e, (q31_t)0x70566a92, (q31_t)0xc2a5766e, + (q31_t)0x70536771, (q31_t)0xc29ff2d4, (q31_t)0x7050640b, (q31_t)0xc29a6f60, (q31_t)0x704d6060, (q31_t)0xc294ec12, (q31_t)0x704a5c6f, (q31_t)0xc28f68e9, + (q31_t)0x70475839, (q31_t)0xc289e5e7, (q31_t)0x704453be, (q31_t)0xc284630a, (q31_t)0x70414efd, (q31_t)0xc27ee054, (q31_t)0x703e49f8, (q31_t)0xc2795dc3, + (q31_t)0x703b44ad, (q31_t)0xc273db58, (q31_t)0x70383f1d, (q31_t)0xc26e5913, (q31_t)0x70353947, (q31_t)0xc268d6f5, (q31_t)0x7032332d, (q31_t)0xc26354fc, + (q31_t)0x702f2ccd, (q31_t)0xc25dd329, (q31_t)0x702c2628, (q31_t)0xc258517c, (q31_t)0x70291f3e, (q31_t)0xc252cff5, (q31_t)0x7026180e, (q31_t)0xc24d4e95, + (q31_t)0x7023109a, (q31_t)0xc247cd5a, (q31_t)0x702008e0, (q31_t)0xc2424c46, (q31_t)0x701d00e1, (q31_t)0xc23ccb57, (q31_t)0x7019f89d, (q31_t)0xc2374a8f, + (q31_t)0x7016f014, (q31_t)0xc231c9ec, (q31_t)0x7013e746, (q31_t)0xc22c4970, (q31_t)0x7010de32, (q31_t)0xc226c91a, (q31_t)0x700dd4da, (q31_t)0xc22148ea, + (q31_t)0x700acb3c, (q31_t)0xc21bc8e1, (q31_t)0x7007c159, (q31_t)0xc21648fd, (q31_t)0x7004b731, (q31_t)0xc210c940, (q31_t)0x7001acc4, (q31_t)0xc20b49a9, + (q31_t)0x6ffea212, (q31_t)0xc205ca38, (q31_t)0x6ffb971b, (q31_t)0xc2004aed, (q31_t)0x6ff88bde, (q31_t)0xc1facbc9, (q31_t)0x6ff5805d, (q31_t)0xc1f54cca, + (q31_t)0x6ff27497, (q31_t)0xc1efcdf3, (q31_t)0x6fef688b, (q31_t)0xc1ea4f41, (q31_t)0x6fec5c3b, (q31_t)0xc1e4d0b6, (q31_t)0x6fe94fa5, (q31_t)0xc1df5251, + (q31_t)0x6fe642ca, (q31_t)0xc1d9d412, (q31_t)0x6fe335ab, (q31_t)0xc1d455f9, (q31_t)0x6fe02846, (q31_t)0xc1ced807, (q31_t)0x6fdd1a9c, (q31_t)0xc1c95a3c, + (q31_t)0x6fda0cae, (q31_t)0xc1c3dc97, (q31_t)0x6fd6fe7a, (q31_t)0xc1be5f18, (q31_t)0x6fd3f001, (q31_t)0xc1b8e1bf, (q31_t)0x6fd0e144, (q31_t)0xc1b3648d, + (q31_t)0x6fcdd241, (q31_t)0xc1ade781, (q31_t)0x6fcac2fa, (q31_t)0xc1a86a9c, (q31_t)0x6fc7b36d, (q31_t)0xc1a2edde, (q31_t)0x6fc4a39c, (q31_t)0xc19d7145, + (q31_t)0x6fc19385, (q31_t)0xc197f4d4, (q31_t)0x6fbe832a, (q31_t)0xc1927888, (q31_t)0x6fbb728a, (q31_t)0xc18cfc63, (q31_t)0x6fb861a4, (q31_t)0xc1878065, + (q31_t)0x6fb5507a, (q31_t)0xc182048d, (q31_t)0x6fb23f0b, (q31_t)0xc17c88dc, (q31_t)0x6faf2d57, (q31_t)0xc1770d52, (q31_t)0x6fac1b5f, (q31_t)0xc17191ee, + (q31_t)0x6fa90921, (q31_t)0xc16c16b0, (q31_t)0x6fa5f69e, (q31_t)0xc1669b99, (q31_t)0x6fa2e3d7, (q31_t)0xc16120a9, (q31_t)0x6f9fd0cb, (q31_t)0xc15ba5df, + (q31_t)0x6f9cbd79, (q31_t)0xc1562b3d, (q31_t)0x6f99a9e3, (q31_t)0xc150b0c0, (q31_t)0x6f969608, (q31_t)0xc14b366b, (q31_t)0x6f9381e9, (q31_t)0xc145bc3c, + (q31_t)0x6f906d84, (q31_t)0xc1404233, (q31_t)0x6f8d58db, (q31_t)0xc13ac852, (q31_t)0x6f8a43ed, (q31_t)0xc1354e97, (q31_t)0x6f872eba, (q31_t)0xc12fd503, + (q31_t)0x6f841942, (q31_t)0xc12a5b95, (q31_t)0x6f810386, (q31_t)0xc124e24f, (q31_t)0x6f7ded84, (q31_t)0xc11f692f, (q31_t)0x6f7ad73e, (q31_t)0xc119f036, + (q31_t)0x6f77c0b3, (q31_t)0xc1147764, (q31_t)0x6f74a9e4, (q31_t)0xc10efeb8, (q31_t)0x6f7192cf, (q31_t)0xc1098634, (q31_t)0x6f6e7b76, (q31_t)0xc1040dd6, + (q31_t)0x6f6b63d8, (q31_t)0xc0fe959f, (q31_t)0x6f684bf6, (q31_t)0xc0f91d8f, (q31_t)0x6f6533ce, (q31_t)0xc0f3a5a6, (q31_t)0x6f621b62, (q31_t)0xc0ee2de3, + (q31_t)0x6f5f02b2, (q31_t)0xc0e8b648, (q31_t)0x6f5be9bc, (q31_t)0xc0e33ed4, (q31_t)0x6f58d082, (q31_t)0xc0ddc786, (q31_t)0x6f55b703, (q31_t)0xc0d8505f, + (q31_t)0x6f529d40, (q31_t)0xc0d2d960, (q31_t)0x6f4f8338, (q31_t)0xc0cd6287, (q31_t)0x6f4c68eb, (q31_t)0xc0c7ebd6, (q31_t)0x6f494e5a, (q31_t)0xc0c2754b, + (q31_t)0x6f463383, (q31_t)0xc0bcfee7, (q31_t)0x6f431869, (q31_t)0xc0b788ab, (q31_t)0x6f3ffd09, (q31_t)0xc0b21295, (q31_t)0x6f3ce165, (q31_t)0xc0ac9ca6, + (q31_t)0x6f39c57d, (q31_t)0xc0a726df, (q31_t)0x6f36a94f, (q31_t)0xc0a1b13e, (q31_t)0x6f338cde, (q31_t)0xc09c3bc5, (q31_t)0x6f307027, (q31_t)0xc096c673, + (q31_t)0x6f2d532c, (q31_t)0xc0915148, (q31_t)0x6f2a35ed, (q31_t)0xc08bdc44, (q31_t)0x6f271868, (q31_t)0xc0866767, (q31_t)0x6f23faa0, (q31_t)0xc080f2b1, + (q31_t)0x6f20dc92, (q31_t)0xc07b7e23, (q31_t)0x6f1dbe41, (q31_t)0xc07609bb, (q31_t)0x6f1a9faa, (q31_t)0xc070957b, (q31_t)0x6f1780cf, (q31_t)0xc06b2162, + (q31_t)0x6f1461b0, (q31_t)0xc065ad70, (q31_t)0x6f11424c, (q31_t)0xc06039a6, (q31_t)0x6f0e22a3, (q31_t)0xc05ac603, (q31_t)0x6f0b02b6, (q31_t)0xc0555287, + (q31_t)0x6f07e285, (q31_t)0xc04fdf32, (q31_t)0x6f04c20f, (q31_t)0xc04a6c05, (q31_t)0x6f01a155, (q31_t)0xc044f8fe, (q31_t)0x6efe8056, (q31_t)0xc03f8620, + (q31_t)0x6efb5f12, (q31_t)0xc03a1368, (q31_t)0x6ef83d8a, (q31_t)0xc034a0d8, (q31_t)0x6ef51bbe, (q31_t)0xc02f2e6f, (q31_t)0x6ef1f9ad, (q31_t)0xc029bc2e, + (q31_t)0x6eeed758, (q31_t)0xc0244a14, (q31_t)0x6eebb4bf, (q31_t)0xc01ed821, (q31_t)0x6ee891e1, (q31_t)0xc0196656, (q31_t)0x6ee56ebe, (q31_t)0xc013f4b2, + (q31_t)0x6ee24b57, (q31_t)0xc00e8336, (q31_t)0x6edf27ac, (q31_t)0xc00911e1, (q31_t)0x6edc03bc, (q31_t)0xc003a0b3, (q31_t)0x6ed8df88, (q31_t)0xbffe2fad, + (q31_t)0x6ed5bb10, (q31_t)0xbff8bece, (q31_t)0x6ed29653, (q31_t)0xbff34e17, (q31_t)0x6ecf7152, (q31_t)0xbfeddd88, (q31_t)0x6ecc4c0d, (q31_t)0xbfe86d20, + (q31_t)0x6ec92683, (q31_t)0xbfe2fcdf, (q31_t)0x6ec600b5, (q31_t)0xbfdd8cc6, (q31_t)0x6ec2daa2, (q31_t)0xbfd81cd5, (q31_t)0x6ebfb44b, (q31_t)0xbfd2ad0b, + (q31_t)0x6ebc8db0, (q31_t)0xbfcd3d69, (q31_t)0x6eb966d1, (q31_t)0xbfc7cdee, (q31_t)0x6eb63fad, (q31_t)0xbfc25e9b, (q31_t)0x6eb31845, (q31_t)0xbfbcef70, + (q31_t)0x6eaff099, (q31_t)0xbfb7806c, (q31_t)0x6eacc8a8, (q31_t)0xbfb21190, (q31_t)0x6ea9a073, (q31_t)0xbfaca2dc, (q31_t)0x6ea677fa, (q31_t)0xbfa7344f, + (q31_t)0x6ea34f3d, (q31_t)0xbfa1c5ea, (q31_t)0x6ea0263b, (q31_t)0xbf9c57ac, (q31_t)0x6e9cfcf5, (q31_t)0xbf96e997, (q31_t)0x6e99d36b, (q31_t)0xbf917ba9, + (q31_t)0x6e96a99d, (q31_t)0xbf8c0de3, (q31_t)0x6e937f8a, (q31_t)0xbf86a044, (q31_t)0x6e905534, (q31_t)0xbf8132ce, (q31_t)0x6e8d2a99, (q31_t)0xbf7bc57f, + (q31_t)0x6e89ffb9, (q31_t)0xbf765858, (q31_t)0x6e86d496, (q31_t)0xbf70eb59, (q31_t)0x6e83a92f, (q31_t)0xbf6b7e81, (q31_t)0x6e807d83, (q31_t)0xbf6611d2, + (q31_t)0x6e7d5193, (q31_t)0xbf60a54a, (q31_t)0x6e7a255f, (q31_t)0xbf5b38ea, (q31_t)0x6e76f8e7, (q31_t)0xbf55ccb2, (q31_t)0x6e73cc2b, (q31_t)0xbf5060a2, + (q31_t)0x6e709f2a, (q31_t)0xbf4af4ba, (q31_t)0x6e6d71e6, (q31_t)0xbf4588fa, (q31_t)0x6e6a445d, (q31_t)0xbf401d61, (q31_t)0x6e671690, (q31_t)0xbf3ab1f1, + (q31_t)0x6e63e87f, (q31_t)0xbf3546a8, (q31_t)0x6e60ba2a, (q31_t)0xbf2fdb88, (q31_t)0x6e5d8b91, (q31_t)0xbf2a708f, (q31_t)0x6e5a5cb4, (q31_t)0xbf2505bf, + (q31_t)0x6e572d93, (q31_t)0xbf1f9b16, (q31_t)0x6e53fe2e, (q31_t)0xbf1a3096, (q31_t)0x6e50ce84, (q31_t)0xbf14c63d, (q31_t)0x6e4d9e97, (q31_t)0xbf0f5c0d, + (q31_t)0x6e4a6e66, (q31_t)0xbf09f205, (q31_t)0x6e473df0, (q31_t)0xbf048824, (q31_t)0x6e440d37, (q31_t)0xbeff1e6c, (q31_t)0x6e40dc39, (q31_t)0xbef9b4dc, + (q31_t)0x6e3daaf8, (q31_t)0xbef44b74, (q31_t)0x6e3a7972, (q31_t)0xbeeee234, (q31_t)0x6e3747a9, (q31_t)0xbee9791c, (q31_t)0x6e34159b, (q31_t)0xbee4102d, + (q31_t)0x6e30e34a, (q31_t)0xbedea765, (q31_t)0x6e2db0b4, (q31_t)0xbed93ec6, (q31_t)0x6e2a7ddb, (q31_t)0xbed3d64f, (q31_t)0x6e274abe, (q31_t)0xbece6e00, + (q31_t)0x6e24175c, (q31_t)0xbec905d9, (q31_t)0x6e20e3b7, (q31_t)0xbec39ddb, (q31_t)0x6e1dafce, (q31_t)0xbebe3605, (q31_t)0x6e1a7ba1, (q31_t)0xbeb8ce57, + (q31_t)0x6e174730, (q31_t)0xbeb366d1, (q31_t)0x6e14127b, (q31_t)0xbeadff74, (q31_t)0x6e10dd82, (q31_t)0xbea8983f, (q31_t)0x6e0da845, (q31_t)0xbea33132, + (q31_t)0x6e0a72c5, (q31_t)0xbe9dca4e, (q31_t)0x6e073d00, (q31_t)0xbe986391, (q31_t)0x6e0406f8, (q31_t)0xbe92fcfe, (q31_t)0x6e00d0ac, (q31_t)0xbe8d9692, + (q31_t)0x6dfd9a1c, (q31_t)0xbe88304f, (q31_t)0x6dfa6348, (q31_t)0xbe82ca35, (q31_t)0x6df72c30, (q31_t)0xbe7d6442, (q31_t)0x6df3f4d4, (q31_t)0xbe77fe78, + (q31_t)0x6df0bd35, (q31_t)0xbe7298d7, (q31_t)0x6ded8552, (q31_t)0xbe6d335e, (q31_t)0x6dea4d2b, (q31_t)0xbe67ce0d, (q31_t)0x6de714c0, (q31_t)0xbe6268e5, + (q31_t)0x6de3dc11, (q31_t)0xbe5d03e6, (q31_t)0x6de0a31f, (q31_t)0xbe579f0f, (q31_t)0x6ddd69e9, (q31_t)0xbe523a60, (q31_t)0x6dda306f, (q31_t)0xbe4cd5da, + (q31_t)0x6dd6f6b1, (q31_t)0xbe47717c, (q31_t)0x6dd3bcaf, (q31_t)0xbe420d47, (q31_t)0x6dd0826a, (q31_t)0xbe3ca93b, (q31_t)0x6dcd47e1, (q31_t)0xbe374557, + (q31_t)0x6dca0d14, (q31_t)0xbe31e19b, (q31_t)0x6dc6d204, (q31_t)0xbe2c7e09, (q31_t)0x6dc396b0, (q31_t)0xbe271a9f, (q31_t)0x6dc05b18, (q31_t)0xbe21b75d, + (q31_t)0x6dbd1f3c, (q31_t)0xbe1c5444, (q31_t)0x6db9e31d, (q31_t)0xbe16f154, (q31_t)0x6db6a6ba, (q31_t)0xbe118e8c, (q31_t)0x6db36a14, (q31_t)0xbe0c2bed, + (q31_t)0x6db02d29, (q31_t)0xbe06c977, (q31_t)0x6daceffb, (q31_t)0xbe01672a, (q31_t)0x6da9b28a, (q31_t)0xbdfc0505, (q31_t)0x6da674d5, (q31_t)0xbdf6a309, + (q31_t)0x6da336dc, (q31_t)0xbdf14135, (q31_t)0x6d9ff89f, (q31_t)0xbdebdf8b, (q31_t)0x6d9cba1f, (q31_t)0xbde67e09, (q31_t)0x6d997b5b, (q31_t)0xbde11cb0, + (q31_t)0x6d963c54, (q31_t)0xbddbbb7f, (q31_t)0x6d92fd09, (q31_t)0xbdd65a78, (q31_t)0x6d8fbd7a, (q31_t)0xbdd0f999, (q31_t)0x6d8c7da8, (q31_t)0xbdcb98e3, + (q31_t)0x6d893d93, (q31_t)0xbdc63856, (q31_t)0x6d85fd39, (q31_t)0xbdc0d7f2, (q31_t)0x6d82bc9d, (q31_t)0xbdbb77b7, (q31_t)0x6d7f7bbc, (q31_t)0xbdb617a4, + (q31_t)0x6d7c3a98, (q31_t)0xbdb0b7bb, (q31_t)0x6d78f931, (q31_t)0xbdab57fa, (q31_t)0x6d75b786, (q31_t)0xbda5f862, (q31_t)0x6d727597, (q31_t)0xbda098f3, + (q31_t)0x6d6f3365, (q31_t)0xbd9b39ad, (q31_t)0x6d6bf0f0, (q31_t)0xbd95da91, (q31_t)0x6d68ae37, (q31_t)0xbd907b9d, (q31_t)0x6d656b3a, (q31_t)0xbd8b1cd2, + (q31_t)0x6d6227fa, (q31_t)0xbd85be30, (q31_t)0x6d5ee477, (q31_t)0xbd805fb7, (q31_t)0x6d5ba0b0, (q31_t)0xbd7b0167, (q31_t)0x6d585ca6, (q31_t)0xbd75a340, + (q31_t)0x6d551858, (q31_t)0xbd704542, (q31_t)0x6d51d3c6, (q31_t)0xbd6ae76d, (q31_t)0x6d4e8ef2, (q31_t)0xbd6589c1, (q31_t)0x6d4b49da, (q31_t)0xbd602c3f, + (q31_t)0x6d48047e, (q31_t)0xbd5acee5, (q31_t)0x6d44bedf, (q31_t)0xbd5571b5, (q31_t)0x6d4178fd, (q31_t)0xbd5014ad, (q31_t)0x6d3e32d7, (q31_t)0xbd4ab7cf, + (q31_t)0x6d3aec6e, (q31_t)0xbd455b1a, (q31_t)0x6d37a5c1, (q31_t)0xbd3ffe8e, (q31_t)0x6d345ed1, (q31_t)0xbd3aa22c, (q31_t)0x6d31179e, (q31_t)0xbd3545f2, + (q31_t)0x6d2dd027, (q31_t)0xbd2fe9e2, (q31_t)0x6d2a886e, (q31_t)0xbd2a8dfb, (q31_t)0x6d274070, (q31_t)0xbd25323d, (q31_t)0x6d23f830, (q31_t)0xbd1fd6a8, + (q31_t)0x6d20afac, (q31_t)0xbd1a7b3d, (q31_t)0x6d1d66e4, (q31_t)0xbd151ffb, (q31_t)0x6d1a1dda, (q31_t)0xbd0fc4e2, (q31_t)0x6d16d48c, (q31_t)0xbd0a69f2, + (q31_t)0x6d138afb, (q31_t)0xbd050f2c, (q31_t)0x6d104126, (q31_t)0xbcffb48f, (q31_t)0x6d0cf70f, (q31_t)0xbcfa5a1b, (q31_t)0x6d09acb4, (q31_t)0xbcf4ffd1, + (q31_t)0x6d066215, (q31_t)0xbcefa5b0, (q31_t)0x6d031734, (q31_t)0xbcea4bb9, (q31_t)0x6cffcc0f, (q31_t)0xbce4f1eb, (q31_t)0x6cfc80a7, (q31_t)0xbcdf9846, + (q31_t)0x6cf934fc, (q31_t)0xbcda3ecb, (q31_t)0x6cf5e90d, (q31_t)0xbcd4e579, (q31_t)0x6cf29cdc, (q31_t)0xbccf8c50, (q31_t)0x6cef5067, (q31_t)0xbcca3351, + (q31_t)0x6cec03af, (q31_t)0xbcc4da7b, (q31_t)0x6ce8b6b4, (q31_t)0xbcbf81cf, (q31_t)0x6ce56975, (q31_t)0xbcba294d, (q31_t)0x6ce21bf4, (q31_t)0xbcb4d0f4, + (q31_t)0x6cdece2f, (q31_t)0xbcaf78c4, (q31_t)0x6cdb8027, (q31_t)0xbcaa20be, (q31_t)0x6cd831dc, (q31_t)0xbca4c8e1, (q31_t)0x6cd4e34e, (q31_t)0xbc9f712e, + (q31_t)0x6cd1947c, (q31_t)0xbc9a19a5, (q31_t)0x6cce4568, (q31_t)0xbc94c245, (q31_t)0x6ccaf610, (q31_t)0xbc8f6b0f, (q31_t)0x6cc7a676, (q31_t)0xbc8a1402, + (q31_t)0x6cc45698, (q31_t)0xbc84bd1f, (q31_t)0x6cc10677, (q31_t)0xbc7f6665, (q31_t)0x6cbdb613, (q31_t)0xbc7a0fd6, (q31_t)0x6cba656c, (q31_t)0xbc74b96f, + (q31_t)0x6cb71482, (q31_t)0xbc6f6333, (q31_t)0x6cb3c355, (q31_t)0xbc6a0d20, (q31_t)0x6cb071e4, (q31_t)0xbc64b737, (q31_t)0x6cad2031, (q31_t)0xbc5f6177, + (q31_t)0x6ca9ce3b, (q31_t)0xbc5a0be2, (q31_t)0x6ca67c01, (q31_t)0xbc54b676, (q31_t)0x6ca32985, (q31_t)0xbc4f6134, (q31_t)0x6c9fd6c6, (q31_t)0xbc4a0c1b, + (q31_t)0x6c9c83c3, (q31_t)0xbc44b72c, (q31_t)0x6c99307e, (q31_t)0xbc3f6267, (q31_t)0x6c95dcf6, (q31_t)0xbc3a0dcc, (q31_t)0x6c92892a, (q31_t)0xbc34b95b, + (q31_t)0x6c8f351c, (q31_t)0xbc2f6513, (q31_t)0x6c8be0cb, (q31_t)0xbc2a10f6, (q31_t)0x6c888c36, (q31_t)0xbc24bd02, (q31_t)0x6c85375f, (q31_t)0xbc1f6938, + (q31_t)0x6c81e245, (q31_t)0xbc1a1598, (q31_t)0x6c7e8ce8, (q31_t)0xbc14c221, (q31_t)0x6c7b3748, (q31_t)0xbc0f6ed5, (q31_t)0x6c77e165, (q31_t)0xbc0a1bb3, + (q31_t)0x6c748b3f, (q31_t)0xbc04c8ba, (q31_t)0x6c7134d7, (q31_t)0xbbff75ec, (q31_t)0x6c6dde2b, (q31_t)0xbbfa2347, (q31_t)0x6c6a873d, (q31_t)0xbbf4d0cc, + (q31_t)0x6c67300b, (q31_t)0xbbef7e7c, (q31_t)0x6c63d897, (q31_t)0xbbea2c55, (q31_t)0x6c6080e0, (q31_t)0xbbe4da58, (q31_t)0x6c5d28e6, (q31_t)0xbbdf8885, + (q31_t)0x6c59d0a9, (q31_t)0xbbda36dd, (q31_t)0x6c56782a, (q31_t)0xbbd4e55e, (q31_t)0x6c531f67, (q31_t)0xbbcf940a, (q31_t)0x6c4fc662, (q31_t)0xbbca42df, + (q31_t)0x6c4c6d1a, (q31_t)0xbbc4f1df, (q31_t)0x6c49138f, (q31_t)0xbbbfa108, (q31_t)0x6c45b9c1, (q31_t)0xbbba505c, (q31_t)0x6c425fb1, (q31_t)0xbbb4ffda, + (q31_t)0x6c3f055d, (q31_t)0xbbafaf82, (q31_t)0x6c3baac7, (q31_t)0xbbaa5f54, (q31_t)0x6c384fef, (q31_t)0xbba50f50, (q31_t)0x6c34f4d3, (q31_t)0xbb9fbf77, + (q31_t)0x6c319975, (q31_t)0xbb9a6fc7, (q31_t)0x6c2e3dd4, (q31_t)0xbb952042, (q31_t)0x6c2ae1f0, (q31_t)0xbb8fd0e7, (q31_t)0x6c2785ca, (q31_t)0xbb8a81b6, + (q31_t)0x6c242960, (q31_t)0xbb8532b0, (q31_t)0x6c20ccb4, (q31_t)0xbb7fe3d3, (q31_t)0x6c1d6fc6, (q31_t)0xbb7a9521, (q31_t)0x6c1a1295, (q31_t)0xbb754699, + (q31_t)0x6c16b521, (q31_t)0xbb6ff83c, (q31_t)0x6c13576a, (q31_t)0xbb6aaa09, (q31_t)0x6c0ff971, (q31_t)0xbb655c00, (q31_t)0x6c0c9b35, (q31_t)0xbb600e21, + (q31_t)0x6c093cb6, (q31_t)0xbb5ac06d, (q31_t)0x6c05ddf5, (q31_t)0xbb5572e3, (q31_t)0x6c027ef1, (q31_t)0xbb502583, (q31_t)0x6bff1faa, (q31_t)0xbb4ad84e, + (q31_t)0x6bfbc021, (q31_t)0xbb458b43, (q31_t)0x6bf86055, (q31_t)0xbb403e63, (q31_t)0x6bf50047, (q31_t)0xbb3af1ad, (q31_t)0x6bf19ff6, (q31_t)0xbb35a521, + (q31_t)0x6bee3f62, (q31_t)0xbb3058c0, (q31_t)0x6beade8c, (q31_t)0xbb2b0c8a, (q31_t)0x6be77d74, (q31_t)0xbb25c07d, (q31_t)0x6be41c18, (q31_t)0xbb20749c, + (q31_t)0x6be0ba7b, (q31_t)0xbb1b28e4, (q31_t)0x6bdd589a, (q31_t)0xbb15dd57, (q31_t)0x6bd9f677, (q31_t)0xbb1091f5, (q31_t)0x6bd69412, (q31_t)0xbb0b46bd, + (q31_t)0x6bd3316a, (q31_t)0xbb05fbb0, (q31_t)0x6bcfce80, (q31_t)0xbb00b0ce, (q31_t)0x6bcc6b53, (q31_t)0xbafb6615, (q31_t)0x6bc907e3, (q31_t)0xbaf61b88, + (q31_t)0x6bc5a431, (q31_t)0xbaf0d125, (q31_t)0x6bc2403d, (q31_t)0xbaeb86ed, (q31_t)0x6bbedc06, (q31_t)0xbae63cdf, (q31_t)0x6bbb778d, (q31_t)0xbae0f2fc, + (q31_t)0x6bb812d1, (q31_t)0xbadba943, (q31_t)0x6bb4add3, (q31_t)0xbad65fb5, (q31_t)0x6bb14892, (q31_t)0xbad11652, (q31_t)0x6bade30f, (q31_t)0xbacbcd1a, + (q31_t)0x6baa7d49, (q31_t)0xbac6840c, (q31_t)0x6ba71741, (q31_t)0xbac13b29, (q31_t)0x6ba3b0f7, (q31_t)0xbabbf270, (q31_t)0x6ba04a6a, (q31_t)0xbab6a9e3, + (q31_t)0x6b9ce39b, (q31_t)0xbab16180, (q31_t)0x6b997c8a, (q31_t)0xbaac1948, (q31_t)0x6b961536, (q31_t)0xbaa6d13a, (q31_t)0x6b92ada0, (q31_t)0xbaa18958, + (q31_t)0x6b8f45c7, (q31_t)0xba9c41a0, (q31_t)0x6b8bddac, (q31_t)0xba96fa13, (q31_t)0x6b88754f, (q31_t)0xba91b2b1, (q31_t)0x6b850caf, (q31_t)0xba8c6b79, + (q31_t)0x6b81a3cd, (q31_t)0xba87246d, (q31_t)0x6b7e3aa9, (q31_t)0xba81dd8b, (q31_t)0x6b7ad142, (q31_t)0xba7c96d4, (q31_t)0x6b776799, (q31_t)0xba775048, + (q31_t)0x6b73fdae, (q31_t)0xba7209e7, (q31_t)0x6b709381, (q31_t)0xba6cc3b1, (q31_t)0x6b6d2911, (q31_t)0xba677da6, (q31_t)0x6b69be5f, (q31_t)0xba6237c5, + (q31_t)0x6b66536b, (q31_t)0xba5cf210, (q31_t)0x6b62e834, (q31_t)0xba57ac86, (q31_t)0x6b5f7cbc, (q31_t)0xba526726, (q31_t)0x6b5c1101, (q31_t)0xba4d21f2, + (q31_t)0x6b58a503, (q31_t)0xba47dce8, (q31_t)0x6b5538c4, (q31_t)0xba42980a, (q31_t)0x6b51cc42, (q31_t)0xba3d5356, (q31_t)0x6b4e5f7f, (q31_t)0xba380ece, + (q31_t)0x6b4af279, (q31_t)0xba32ca71, (q31_t)0x6b478530, (q31_t)0xba2d863e, (q31_t)0x6b4417a6, (q31_t)0xba284237, (q31_t)0x6b40a9d9, (q31_t)0xba22fe5b, + (q31_t)0x6b3d3bcb, (q31_t)0xba1dbaaa, (q31_t)0x6b39cd7a, (q31_t)0xba187724, (q31_t)0x6b365ee7, (q31_t)0xba1333c9, (q31_t)0x6b32f012, (q31_t)0xba0df099, + (q31_t)0x6b2f80fb, (q31_t)0xba08ad95, (q31_t)0x6b2c11a1, (q31_t)0xba036abb, (q31_t)0x6b28a206, (q31_t)0xb9fe280d, (q31_t)0x6b253228, (q31_t)0xb9f8e58a, + (q31_t)0x6b21c208, (q31_t)0xb9f3a332, (q31_t)0x6b1e51a7, (q31_t)0xb9ee6106, (q31_t)0x6b1ae103, (q31_t)0xb9e91f04, (q31_t)0x6b17701d, (q31_t)0xb9e3dd2e, + (q31_t)0x6b13fef5, (q31_t)0xb9de9b83, (q31_t)0x6b108d8b, (q31_t)0xb9d95a03, (q31_t)0x6b0d1bdf, (q31_t)0xb9d418af, (q31_t)0x6b09a9f1, (q31_t)0xb9ced786, + (q31_t)0x6b0637c1, (q31_t)0xb9c99688, (q31_t)0x6b02c54f, (q31_t)0xb9c455b6, (q31_t)0x6aff529a, (q31_t)0xb9bf150e, (q31_t)0x6afbdfa4, (q31_t)0xb9b9d493, + (q31_t)0x6af86c6c, (q31_t)0xb9b49442, (q31_t)0x6af4f8f2, (q31_t)0xb9af541d, (q31_t)0x6af18536, (q31_t)0xb9aa1423, (q31_t)0x6aee1138, (q31_t)0xb9a4d455, + (q31_t)0x6aea9cf8, (q31_t)0xb99f94b2, (q31_t)0x6ae72876, (q31_t)0xb99a553a, (q31_t)0x6ae3b3b2, (q31_t)0xb99515ee, (q31_t)0x6ae03eac, (q31_t)0xb98fd6cd, + (q31_t)0x6adcc964, (q31_t)0xb98a97d8, (q31_t)0x6ad953db, (q31_t)0xb985590e, (q31_t)0x6ad5de0f, (q31_t)0xb9801a70, (q31_t)0x6ad26802, (q31_t)0xb97adbfd, + (q31_t)0x6acef1b2, (q31_t)0xb9759db6, (q31_t)0x6acb7b21, (q31_t)0xb9705f9a, (q31_t)0x6ac8044e, (q31_t)0xb96b21aa, (q31_t)0x6ac48d39, (q31_t)0xb965e3e5, + (q31_t)0x6ac115e2, (q31_t)0xb960a64c, (q31_t)0x6abd9e49, (q31_t)0xb95b68de, (q31_t)0x6aba266e, (q31_t)0xb9562b9c, (q31_t)0x6ab6ae52, (q31_t)0xb950ee86, + (q31_t)0x6ab335f4, (q31_t)0xb94bb19b, (q31_t)0x6aafbd54, (q31_t)0xb94674dc, (q31_t)0x6aac4472, (q31_t)0xb9413848, (q31_t)0x6aa8cb4e, (q31_t)0xb93bfbe0, + (q31_t)0x6aa551e9, (q31_t)0xb936bfa4, (q31_t)0x6aa1d841, (q31_t)0xb9318393, (q31_t)0x6a9e5e58, (q31_t)0xb92c47ae, (q31_t)0x6a9ae42e, (q31_t)0xb9270bf5, + (q31_t)0x6a9769c1, (q31_t)0xb921d067, (q31_t)0x6a93ef13, (q31_t)0xb91c9505, (q31_t)0x6a907423, (q31_t)0xb91759cf, (q31_t)0x6a8cf8f1, (q31_t)0xb9121ec5, + (q31_t)0x6a897d7d, (q31_t)0xb90ce3e6, (q31_t)0x6a8601c8, (q31_t)0xb907a933, (q31_t)0x6a8285d1, (q31_t)0xb9026eac, (q31_t)0x6a7f0999, (q31_t)0xb8fd3451, + (q31_t)0x6a7b8d1e, (q31_t)0xb8f7fa21, (q31_t)0x6a781062, (q31_t)0xb8f2c01d, (q31_t)0x6a749365, (q31_t)0xb8ed8646, (q31_t)0x6a711625, (q31_t)0xb8e84c99, + (q31_t)0x6a6d98a4, (q31_t)0xb8e31319, (q31_t)0x6a6a1ae2, (q31_t)0xb8ddd9c5, (q31_t)0x6a669cdd, (q31_t)0xb8d8a09d, (q31_t)0x6a631e97, (q31_t)0xb8d367a0, + (q31_t)0x6a5fa010, (q31_t)0xb8ce2ecf, (q31_t)0x6a5c2147, (q31_t)0xb8c8f62b, (q31_t)0x6a58a23c, (q31_t)0xb8c3bdb2, (q31_t)0x6a5522ef, (q31_t)0xb8be8565, + (q31_t)0x6a51a361, (q31_t)0xb8b94d44, (q31_t)0x6a4e2392, (q31_t)0xb8b4154f, (q31_t)0x6a4aa381, (q31_t)0xb8aedd86, (q31_t)0x6a47232e, (q31_t)0xb8a9a5e9, + (q31_t)0x6a43a29a, (q31_t)0xb8a46e78, (q31_t)0x6a4021c4, (q31_t)0xb89f3733, (q31_t)0x6a3ca0ad, (q31_t)0xb89a001a, (q31_t)0x6a391f54, (q31_t)0xb894c92d, + (q31_t)0x6a359db9, (q31_t)0xb88f926d, (q31_t)0x6a321bdd, (q31_t)0xb88a5bd8, (q31_t)0x6a2e99c0, (q31_t)0xb885256f, (q31_t)0x6a2b1761, (q31_t)0xb87fef33, + (q31_t)0x6a2794c1, (q31_t)0xb87ab922, (q31_t)0x6a2411df, (q31_t)0xb875833e, (q31_t)0x6a208ebb, (q31_t)0xb8704d85, (q31_t)0x6a1d0b57, (q31_t)0xb86b17f9, + (q31_t)0x6a1987b0, (q31_t)0xb865e299, (q31_t)0x6a1603c8, (q31_t)0xb860ad66, (q31_t)0x6a127f9f, (q31_t)0xb85b785e, (q31_t)0x6a0efb35, (q31_t)0xb8564383, + (q31_t)0x6a0b7689, (q31_t)0xb8510ed4, (q31_t)0x6a07f19b, (q31_t)0xb84bda51, (q31_t)0x6a046c6c, (q31_t)0xb846a5fa, (q31_t)0x6a00e6fc, (q31_t)0xb84171cf, + (q31_t)0x69fd614a, (q31_t)0xb83c3dd1, (q31_t)0x69f9db57, (q31_t)0xb83709ff, (q31_t)0x69f65523, (q31_t)0xb831d659, (q31_t)0x69f2cead, (q31_t)0xb82ca2e0, + (q31_t)0x69ef47f6, (q31_t)0xb8276f93, (q31_t)0x69ebc0fe, (q31_t)0xb8223c72, (q31_t)0x69e839c4, (q31_t)0xb81d097e, (q31_t)0x69e4b249, (q31_t)0xb817d6b6, + (q31_t)0x69e12a8c, (q31_t)0xb812a41a, (q31_t)0x69dda28f, (q31_t)0xb80d71aa, (q31_t)0x69da1a50, (q31_t)0xb8083f67, (q31_t)0x69d691cf, (q31_t)0xb8030d51, + (q31_t)0x69d3090e, (q31_t)0xb7fddb67, (q31_t)0x69cf800b, (q31_t)0xb7f8a9a9, (q31_t)0x69cbf6c7, (q31_t)0xb7f37818, (q31_t)0x69c86d41, (q31_t)0xb7ee46b3, + (q31_t)0x69c4e37a, (q31_t)0xb7e9157a, (q31_t)0x69c15973, (q31_t)0xb7e3e46e, (q31_t)0x69bdcf29, (q31_t)0xb7deb38f, (q31_t)0x69ba449f, (q31_t)0xb7d982dc, + (q31_t)0x69b6b9d3, (q31_t)0xb7d45255, (q31_t)0x69b32ec7, (q31_t)0xb7cf21fb, (q31_t)0x69afa378, (q31_t)0xb7c9f1ce, (q31_t)0x69ac17e9, (q31_t)0xb7c4c1cd, + (q31_t)0x69a88c19, (q31_t)0xb7bf91f8, (q31_t)0x69a50007, (q31_t)0xb7ba6251, (q31_t)0x69a173b5, (q31_t)0xb7b532d6, (q31_t)0x699de721, (q31_t)0xb7b00387, + (q31_t)0x699a5a4c, (q31_t)0xb7aad465, (q31_t)0x6996cd35, (q31_t)0xb7a5a570, (q31_t)0x69933fde, (q31_t)0xb7a076a7, (q31_t)0x698fb246, (q31_t)0xb79b480b, + (q31_t)0x698c246c, (q31_t)0xb796199b, (q31_t)0x69889651, (q31_t)0xb790eb58, (q31_t)0x698507f6, (q31_t)0xb78bbd42, (q31_t)0x69817959, (q31_t)0xb7868f59, + (q31_t)0x697dea7b, (q31_t)0xb781619c, (q31_t)0x697a5b5c, (q31_t)0xb77c340c, (q31_t)0x6976cbfc, (q31_t)0xb77706a9, (q31_t)0x69733c5b, (q31_t)0xb771d972, + (q31_t)0x696fac78, (q31_t)0xb76cac69, (q31_t)0x696c1c55, (q31_t)0xb7677f8c, (q31_t)0x69688bf1, (q31_t)0xb76252db, (q31_t)0x6964fb4c, (q31_t)0xb75d2658, + (q31_t)0x69616a65, (q31_t)0xb757fa01, (q31_t)0x695dd93e, (q31_t)0xb752cdd8, (q31_t)0x695a47d6, (q31_t)0xb74da1db, (q31_t)0x6956b62d, (q31_t)0xb748760b, + (q31_t)0x69532442, (q31_t)0xb7434a67, (q31_t)0x694f9217, (q31_t)0xb73e1ef1, (q31_t)0x694bffab, (q31_t)0xb738f3a7, (q31_t)0x69486cfe, (q31_t)0xb733c88b, + (q31_t)0x6944da10, (q31_t)0xb72e9d9b, (q31_t)0x694146e1, (q31_t)0xb72972d8, (q31_t)0x693db371, (q31_t)0xb7244842, (q31_t)0x693a1fc0, (q31_t)0xb71f1dd9, + (q31_t)0x69368bce, (q31_t)0xb719f39e, (q31_t)0x6932f79b, (q31_t)0xb714c98e, (q31_t)0x692f6328, (q31_t)0xb70f9fac, (q31_t)0x692bce73, (q31_t)0xb70a75f7, + (q31_t)0x6928397e, (q31_t)0xb7054c6f, (q31_t)0x6924a448, (q31_t)0xb7002314, (q31_t)0x69210ed1, (q31_t)0xb6faf9e6, (q31_t)0x691d7919, (q31_t)0xb6f5d0e5, + (q31_t)0x6919e320, (q31_t)0xb6f0a812, (q31_t)0x69164ce7, (q31_t)0xb6eb7f6b, (q31_t)0x6912b66c, (q31_t)0xb6e656f1, (q31_t)0x690f1fb1, (q31_t)0xb6e12ea4, + (q31_t)0x690b88b5, (q31_t)0xb6dc0685, (q31_t)0x6907f178, (q31_t)0xb6d6de92, (q31_t)0x690459fb, (q31_t)0xb6d1b6cd, (q31_t)0x6900c23c, (q31_t)0xb6cc8f35, + (q31_t)0x68fd2a3d, (q31_t)0xb6c767ca, (q31_t)0x68f991fd, (q31_t)0xb6c2408c, (q31_t)0x68f5f97d, (q31_t)0xb6bd197c, (q31_t)0x68f260bb, (q31_t)0xb6b7f298, + (q31_t)0x68eec7b9, (q31_t)0xb6b2cbe2, (q31_t)0x68eb2e76, (q31_t)0xb6ada559, (q31_t)0x68e794f3, (q31_t)0xb6a87efd, (q31_t)0x68e3fb2e, (q31_t)0xb6a358ce, + (q31_t)0x68e06129, (q31_t)0xb69e32cd, (q31_t)0x68dcc6e4, (q31_t)0xb6990cf9, (q31_t)0x68d92c5d, (q31_t)0xb693e752, (q31_t)0x68d59196, (q31_t)0xb68ec1d9, + (q31_t)0x68d1f68f, (q31_t)0xb6899c8d, (q31_t)0x68ce5b46, (q31_t)0xb684776e, (q31_t)0x68cabfbd, (q31_t)0xb67f527c, (q31_t)0x68c723f3, (q31_t)0xb67a2db8, + (q31_t)0x68c387e9, (q31_t)0xb6750921, (q31_t)0x68bfeb9e, (q31_t)0xb66fe4b8, (q31_t)0x68bc4f13, (q31_t)0xb66ac07c, (q31_t)0x68b8b247, (q31_t)0xb6659c6d, + (q31_t)0x68b5153a, (q31_t)0xb660788c, (q31_t)0x68b177ed, (q31_t)0xb65b54d8, (q31_t)0x68adda5f, (q31_t)0xb6563151, (q31_t)0x68aa3c90, (q31_t)0xb6510df8, + (q31_t)0x68a69e81, (q31_t)0xb64beacd, (q31_t)0x68a30031, (q31_t)0xb646c7ce, (q31_t)0x689f61a1, (q31_t)0xb641a4fe, (q31_t)0x689bc2d1, (q31_t)0xb63c825b, + (q31_t)0x689823bf, (q31_t)0xb6375fe5, (q31_t)0x6894846e, (q31_t)0xb6323d9d, (q31_t)0x6890e4dc, (q31_t)0xb62d1b82, (q31_t)0x688d4509, (q31_t)0xb627f995, + (q31_t)0x6889a4f6, (q31_t)0xb622d7d6, (q31_t)0x688604a2, (q31_t)0xb61db644, (q31_t)0x6882640e, (q31_t)0xb61894df, (q31_t)0x687ec339, (q31_t)0xb61373a9, + (q31_t)0x687b2224, (q31_t)0xb60e529f, (q31_t)0x687780ce, (q31_t)0xb60931c4, (q31_t)0x6873df38, (q31_t)0xb6041116, (q31_t)0x68703d62, (q31_t)0xb5fef095, + (q31_t)0x686c9b4b, (q31_t)0xb5f9d043, (q31_t)0x6868f8f4, (q31_t)0xb5f4b01e, (q31_t)0x6865565c, (q31_t)0xb5ef9026, (q31_t)0x6861b384, (q31_t)0xb5ea705d, + (q31_t)0x685e106c, (q31_t)0xb5e550c1, (q31_t)0x685a6d13, (q31_t)0xb5e03153, (q31_t)0x6856c979, (q31_t)0xb5db1212, (q31_t)0x685325a0, (q31_t)0xb5d5f2ff, + (q31_t)0x684f8186, (q31_t)0xb5d0d41a, (q31_t)0x684bdd2c, (q31_t)0xb5cbb563, (q31_t)0x68483891, (q31_t)0xb5c696da, (q31_t)0x684493b6, (q31_t)0xb5c1787e, + (q31_t)0x6840ee9b, (q31_t)0xb5bc5a50, (q31_t)0x683d493f, (q31_t)0xb5b73c50, (q31_t)0x6839a3a4, (q31_t)0xb5b21e7e, (q31_t)0x6835fdc7, (q31_t)0xb5ad00d9, + (q31_t)0x683257ab, (q31_t)0xb5a7e362, (q31_t)0x682eb14e, (q31_t)0xb5a2c61a, (q31_t)0x682b0ab1, (q31_t)0xb59da8ff, (q31_t)0x682763d4, (q31_t)0xb5988c12, + (q31_t)0x6823bcb7, (q31_t)0xb5936f53, (q31_t)0x68201559, (q31_t)0xb58e52c2, (q31_t)0x681c6dbb, (q31_t)0xb589365e, (q31_t)0x6818c5dd, (q31_t)0xb5841a29, + (q31_t)0x68151dbe, (q31_t)0xb57efe22, (q31_t)0x68117560, (q31_t)0xb579e248, (q31_t)0x680dccc1, (q31_t)0xb574c69d, (q31_t)0x680a23e2, (q31_t)0xb56fab1f, + (q31_t)0x68067ac3, (q31_t)0xb56a8fd0, (q31_t)0x6802d164, (q31_t)0xb56574ae, (q31_t)0x67ff27c4, (q31_t)0xb56059bb, (q31_t)0x67fb7de5, (q31_t)0xb55b3ef5, + (q31_t)0x67f7d3c5, (q31_t)0xb556245e, (q31_t)0x67f42965, (q31_t)0xb55109f5, (q31_t)0x67f07ec5, (q31_t)0xb54befba, (q31_t)0x67ecd3e5, (q31_t)0xb546d5ac, + (q31_t)0x67e928c5, (q31_t)0xb541bbcd, (q31_t)0x67e57d64, (q31_t)0xb53ca21c, (q31_t)0x67e1d1c4, (q31_t)0xb5378899, (q31_t)0x67de25e3, (q31_t)0xb5326f45, + (q31_t)0x67da79c3, (q31_t)0xb52d561e, (q31_t)0x67d6cd62, (q31_t)0xb5283d26, (q31_t)0x67d320c1, (q31_t)0xb523245b, (q31_t)0x67cf73e1, (q31_t)0xb51e0bbf, + (q31_t)0x67cbc6c0, (q31_t)0xb518f351, (q31_t)0x67c8195f, (q31_t)0xb513db12, (q31_t)0x67c46bbe, (q31_t)0xb50ec300, (q31_t)0x67c0bddd, (q31_t)0xb509ab1d, + (q31_t)0x67bd0fbd, (q31_t)0xb5049368, (q31_t)0x67b9615c, (q31_t)0xb4ff7be1, (q31_t)0x67b5b2bb, (q31_t)0xb4fa6489, (q31_t)0x67b203da, (q31_t)0xb4f54d5f, + (q31_t)0x67ae54ba, (q31_t)0xb4f03663, (q31_t)0x67aaa559, (q31_t)0xb4eb1f95, (q31_t)0x67a6f5b8, (q31_t)0xb4e608f6, (q31_t)0x67a345d8, (q31_t)0xb4e0f285, + (q31_t)0x679f95b7, (q31_t)0xb4dbdc42, (q31_t)0x679be557, (q31_t)0xb4d6c62e, (q31_t)0x679834b6, (q31_t)0xb4d1b048, (q31_t)0x679483d6, (q31_t)0xb4cc9a90, + (q31_t)0x6790d2b6, (q31_t)0xb4c78507, (q31_t)0x678d2156, (q31_t)0xb4c26fad, (q31_t)0x67896fb6, (q31_t)0xb4bd5a80, (q31_t)0x6785bdd6, (q31_t)0xb4b84582, + (q31_t)0x67820bb7, (q31_t)0xb4b330b3, (q31_t)0x677e5957, (q31_t)0xb4ae1c12, (q31_t)0x677aa6b8, (q31_t)0xb4a9079f, (q31_t)0x6776f3d9, (q31_t)0xb4a3f35b, + (q31_t)0x677340ba, (q31_t)0xb49edf45, (q31_t)0x676f8d5b, (q31_t)0xb499cb5e, (q31_t)0x676bd9bd, (q31_t)0xb494b7a6, (q31_t)0x676825de, (q31_t)0xb48fa41c, + (q31_t)0x676471c0, (q31_t)0xb48a90c0, (q31_t)0x6760bd62, (q31_t)0xb4857d93, (q31_t)0x675d08c4, (q31_t)0xb4806a95, (q31_t)0x675953e7, (q31_t)0xb47b57c5, + (q31_t)0x67559eca, (q31_t)0xb4764523, (q31_t)0x6751e96d, (q31_t)0xb47132b1, (q31_t)0x674e33d0, (q31_t)0xb46c206d, (q31_t)0x674a7df4, (q31_t)0xb4670e57, + (q31_t)0x6746c7d8, (q31_t)0xb461fc70, (q31_t)0x6743117c, (q31_t)0xb45ceab8, (q31_t)0x673f5ae0, (q31_t)0xb457d92f, (q31_t)0x673ba405, (q31_t)0xb452c7d4, + (q31_t)0x6737ecea, (q31_t)0xb44db6a8, (q31_t)0x67343590, (q31_t)0xb448a5aa, (q31_t)0x67307df5, (q31_t)0xb44394db, (q31_t)0x672cc61c, (q31_t)0xb43e843b, + (q31_t)0x67290e02, (q31_t)0xb43973ca, (q31_t)0x672555a9, (q31_t)0xb4346387, (q31_t)0x67219d10, (q31_t)0xb42f5373, (q31_t)0x671de438, (q31_t)0xb42a438e, + (q31_t)0x671a2b20, (q31_t)0xb42533d8, (q31_t)0x671671c8, (q31_t)0xb4202451, (q31_t)0x6712b831, (q31_t)0xb41b14f8, (q31_t)0x670efe5a, (q31_t)0xb41605ce, + (q31_t)0x670b4444, (q31_t)0xb410f6d3, (q31_t)0x670789ee, (q31_t)0xb40be807, (q31_t)0x6703cf58, (q31_t)0xb406d969, (q31_t)0x67001483, (q31_t)0xb401cafb, + (q31_t)0x66fc596f, (q31_t)0xb3fcbcbb, (q31_t)0x66f89e1b, (q31_t)0xb3f7aeaa, (q31_t)0x66f4e287, (q31_t)0xb3f2a0c9, (q31_t)0x66f126b4, (q31_t)0xb3ed9316, + (q31_t)0x66ed6aa1, (q31_t)0xb3e88592, (q31_t)0x66e9ae4f, (q31_t)0xb3e3783d, (q31_t)0x66e5f1be, (q31_t)0xb3de6b17, (q31_t)0x66e234ed, (q31_t)0xb3d95e1f, + (q31_t)0x66de77dc, (q31_t)0xb3d45157, (q31_t)0x66daba8c, (q31_t)0xb3cf44be, (q31_t)0x66d6fcfd, (q31_t)0xb3ca3854, (q31_t)0x66d33f2e, (q31_t)0xb3c52c19, + (q31_t)0x66cf8120, (q31_t)0xb3c0200c, (q31_t)0x66cbc2d2, (q31_t)0xb3bb142f, (q31_t)0x66c80445, (q31_t)0xb3b60881, (q31_t)0x66c44579, (q31_t)0xb3b0fd02, + (q31_t)0x66c0866d, (q31_t)0xb3abf1b2, (q31_t)0x66bcc721, (q31_t)0xb3a6e691, (q31_t)0x66b90797, (q31_t)0xb3a1dba0, (q31_t)0x66b547cd, (q31_t)0xb39cd0dd, + (q31_t)0x66b187c3, (q31_t)0xb397c649, (q31_t)0x66adc77b, (q31_t)0xb392bbe5, (q31_t)0x66aa06f3, (q31_t)0xb38db1b0, (q31_t)0x66a6462b, (q31_t)0xb388a7aa, + (q31_t)0x66a28524, (q31_t)0xb3839dd3, (q31_t)0x669ec3de, (q31_t)0xb37e942b, (q31_t)0x669b0259, (q31_t)0xb3798ab2, (q31_t)0x66974095, (q31_t)0xb3748169, + (q31_t)0x66937e91, (q31_t)0xb36f784f, (q31_t)0x668fbc4e, (q31_t)0xb36a6f64, (q31_t)0x668bf9cb, (q31_t)0xb36566a8, (q31_t)0x66883709, (q31_t)0xb3605e1c, + (q31_t)0x66847408, (q31_t)0xb35b55bf, (q31_t)0x6680b0c8, (q31_t)0xb3564d91, (q31_t)0x667ced49, (q31_t)0xb3514592, (q31_t)0x6679298a, (q31_t)0xb34c3dc3, + (q31_t)0x6675658c, (q31_t)0xb3473623, (q31_t)0x6671a14f, (q31_t)0xb3422eb2, (q31_t)0x666ddcd3, (q31_t)0xb33d2771, (q31_t)0x666a1818, (q31_t)0xb338205f, + (q31_t)0x6666531d, (q31_t)0xb333197c, (q31_t)0x66628de4, (q31_t)0xb32e12c9, (q31_t)0x665ec86b, (q31_t)0xb3290c45, (q31_t)0x665b02b3, (q31_t)0xb32405f1, + (q31_t)0x66573cbb, (q31_t)0xb31effcc, (q31_t)0x66537685, (q31_t)0xb319f9d6, (q31_t)0x664fb010, (q31_t)0xb314f410, (q31_t)0x664be95b, (q31_t)0xb30fee79, + (q31_t)0x66482267, (q31_t)0xb30ae912, (q31_t)0x66445b35, (q31_t)0xb305e3da, (q31_t)0x664093c3, (q31_t)0xb300ded2, (q31_t)0x663ccc12, (q31_t)0xb2fbd9f9, + (q31_t)0x66390422, (q31_t)0xb2f6d550, (q31_t)0x66353bf3, (q31_t)0xb2f1d0d6, (q31_t)0x66317385, (q31_t)0xb2eccc8c, (q31_t)0x662daad8, (q31_t)0xb2e7c871, + (q31_t)0x6629e1ec, (q31_t)0xb2e2c486, (q31_t)0x662618c1, (q31_t)0xb2ddc0ca, (q31_t)0x66224f56, (q31_t)0xb2d8bd3e, (q31_t)0x661e85ad, (q31_t)0xb2d3b9e2, + (q31_t)0x661abbc5, (q31_t)0xb2ceb6b5, (q31_t)0x6616f19e, (q31_t)0xb2c9b3b8, (q31_t)0x66132738, (q31_t)0xb2c4b0ea, (q31_t)0x660f5c93, (q31_t)0xb2bfae4c, + (q31_t)0x660b91af, (q31_t)0xb2baabde, (q31_t)0x6607c68c, (q31_t)0xb2b5a99f, (q31_t)0x6603fb2a, (q31_t)0xb2b0a790, (q31_t)0x66002f89, (q31_t)0xb2aba5b1, + (q31_t)0x65fc63a9, (q31_t)0xb2a6a402, (q31_t)0x65f8978b, (q31_t)0xb2a1a282, (q31_t)0x65f4cb2d, (q31_t)0xb29ca132, (q31_t)0x65f0fe91, (q31_t)0xb297a011, + (q31_t)0x65ed31b5, (q31_t)0xb2929f21, (q31_t)0x65e9649b, (q31_t)0xb28d9e60, (q31_t)0x65e59742, (q31_t)0xb2889dcf, (q31_t)0x65e1c9aa, (q31_t)0xb2839d6d, + (q31_t)0x65ddfbd3, (q31_t)0xb27e9d3c, (q31_t)0x65da2dbd, (q31_t)0xb2799d3a, (q31_t)0x65d65f69, (q31_t)0xb2749d68, (q31_t)0x65d290d6, (q31_t)0xb26f9dc6, + (q31_t)0x65cec204, (q31_t)0xb26a9e54, (q31_t)0x65caf2f3, (q31_t)0xb2659f12, (q31_t)0x65c723a3, (q31_t)0xb2609fff, (q31_t)0x65c35415, (q31_t)0xb25ba11d, + (q31_t)0x65bf8447, (q31_t)0xb256a26a, (q31_t)0x65bbb43b, (q31_t)0xb251a3e7, (q31_t)0x65b7e3f1, (q31_t)0xb24ca594, (q31_t)0x65b41367, (q31_t)0xb247a771, + (q31_t)0x65b0429f, (q31_t)0xb242a97e, (q31_t)0x65ac7198, (q31_t)0xb23dabbb, (q31_t)0x65a8a052, (q31_t)0xb238ae28, (q31_t)0x65a4cece, (q31_t)0xb233b0c5, + (q31_t)0x65a0fd0b, (q31_t)0xb22eb392, (q31_t)0x659d2b09, (q31_t)0xb229b68f, (q31_t)0x659958c9, (q31_t)0xb224b9bc, (q31_t)0x6595864a, (q31_t)0xb21fbd19, + (q31_t)0x6591b38c, (q31_t)0xb21ac0a6, (q31_t)0x658de08f, (q31_t)0xb215c463, (q31_t)0x658a0d54, (q31_t)0xb210c850, (q31_t)0x658639db, (q31_t)0xb20bcc6d, + (q31_t)0x65826622, (q31_t)0xb206d0ba, (q31_t)0x657e922b, (q31_t)0xb201d537, (q31_t)0x657abdf6, (q31_t)0xb1fcd9e5, (q31_t)0x6576e982, (q31_t)0xb1f7dec2, + (q31_t)0x657314cf, (q31_t)0xb1f2e3d0, (q31_t)0x656f3fde, (q31_t)0xb1ede90e, (q31_t)0x656b6aae, (q31_t)0xb1e8ee7c, (q31_t)0x6567953f, (q31_t)0xb1e3f41a, + (q31_t)0x6563bf92, (q31_t)0xb1def9e9, (q31_t)0x655fe9a7, (q31_t)0xb1d9ffe7, (q31_t)0x655c137d, (q31_t)0xb1d50616, (q31_t)0x65583d14, (q31_t)0xb1d00c75, + (q31_t)0x6554666d, (q31_t)0xb1cb1304, (q31_t)0x65508f87, (q31_t)0xb1c619c3, (q31_t)0x654cb863, (q31_t)0xb1c120b3, (q31_t)0x6548e101, (q31_t)0xb1bc27d3, + (q31_t)0x6545095f, (q31_t)0xb1b72f23, (q31_t)0x65413180, (q31_t)0xb1b236a4, (q31_t)0x653d5962, (q31_t)0xb1ad3e55, (q31_t)0x65398105, (q31_t)0xb1a84636, + (q31_t)0x6535a86b, (q31_t)0xb1a34e47, (q31_t)0x6531cf91, (q31_t)0xb19e5689, (q31_t)0x652df679, (q31_t)0xb1995efb, (q31_t)0x652a1d23, (q31_t)0xb194679e, + (q31_t)0x6526438f, (q31_t)0xb18f7071, (q31_t)0x652269bc, (q31_t)0xb18a7974, (q31_t)0x651e8faa, (q31_t)0xb18582a8, (q31_t)0x651ab55b, (q31_t)0xb1808c0c, + (q31_t)0x6516dacd, (q31_t)0xb17b95a0, (q31_t)0x65130000, (q31_t)0xb1769f65, (q31_t)0x650f24f5, (q31_t)0xb171a95b, (q31_t)0x650b49ac, (q31_t)0xb16cb380, + (q31_t)0x65076e25, (q31_t)0xb167bdd7, (q31_t)0x6503925f, (q31_t)0xb162c85d, (q31_t)0x64ffb65b, (q31_t)0xb15dd315, (q31_t)0x64fbda18, (q31_t)0xb158ddfd, + (q31_t)0x64f7fd98, (q31_t)0xb153e915, (q31_t)0x64f420d9, (q31_t)0xb14ef45e, (q31_t)0x64f043dc, (q31_t)0xb149ffd7, (q31_t)0x64ec66a0, (q31_t)0xb1450b81, + (q31_t)0x64e88926, (q31_t)0xb140175b, (q31_t)0x64e4ab6e, (q31_t)0xb13b2367, (q31_t)0x64e0cd78, (q31_t)0xb1362fa2, (q31_t)0x64dcef44, (q31_t)0xb1313c0e, + (q31_t)0x64d910d1, (q31_t)0xb12c48ab, (q31_t)0x64d53220, (q31_t)0xb1275579, (q31_t)0x64d15331, (q31_t)0xb1226277, (q31_t)0x64cd7404, (q31_t)0xb11d6fa6, + (q31_t)0x64c99498, (q31_t)0xb1187d05, (q31_t)0x64c5b4ef, (q31_t)0xb1138a95, (q31_t)0x64c1d507, (q31_t)0xb10e9856, (q31_t)0x64bdf4e1, (q31_t)0xb109a648, + (q31_t)0x64ba147d, (q31_t)0xb104b46a, (q31_t)0x64b633da, (q31_t)0xb0ffc2bd, (q31_t)0x64b252fa, (q31_t)0xb0fad140, (q31_t)0x64ae71dc, (q31_t)0xb0f5dff5, + (q31_t)0x64aa907f, (q31_t)0xb0f0eeda, (q31_t)0x64a6aee4, (q31_t)0xb0ebfdf0, (q31_t)0x64a2cd0c, (q31_t)0xb0e70d37, (q31_t)0x649eeaf5, (q31_t)0xb0e21cae, + (q31_t)0x649b08a0, (q31_t)0xb0dd2c56, (q31_t)0x6497260d, (q31_t)0xb0d83c2f, (q31_t)0x6493433c, (q31_t)0xb0d34c39, (q31_t)0x648f602d, (q31_t)0xb0ce5c74, + (q31_t)0x648b7ce0, (q31_t)0xb0c96ce0, (q31_t)0x64879955, (q31_t)0xb0c47d7c, (q31_t)0x6483b58c, (q31_t)0xb0bf8e4a, (q31_t)0x647fd185, (q31_t)0xb0ba9f48, + (q31_t)0x647bed3f, (q31_t)0xb0b5b077, (q31_t)0x647808bc, (q31_t)0xb0b0c1d7, (q31_t)0x647423fb, (q31_t)0xb0abd368, (q31_t)0x64703efc, (q31_t)0xb0a6e52a, + (q31_t)0x646c59bf, (q31_t)0xb0a1f71d, (q31_t)0x64687444, (q31_t)0xb09d0941, (q31_t)0x64648e8c, (q31_t)0xb0981b96, (q31_t)0x6460a895, (q31_t)0xb0932e1b, + (q31_t)0x645cc260, (q31_t)0xb08e40d2, (q31_t)0x6458dbed, (q31_t)0xb08953ba, (q31_t)0x6454f53d, (q31_t)0xb08466d3, (q31_t)0x64510e4e, (q31_t)0xb07f7a1c, + (q31_t)0x644d2722, (q31_t)0xb07a8d97, (q31_t)0x64493fb8, (q31_t)0xb075a143, (q31_t)0x64455810, (q31_t)0xb070b520, (q31_t)0x6441702a, (q31_t)0xb06bc92e, + (q31_t)0x643d8806, (q31_t)0xb066dd6d, (q31_t)0x64399fa5, (q31_t)0xb061f1de, (q31_t)0x6435b706, (q31_t)0xb05d067f, (q31_t)0x6431ce28, (q31_t)0xb0581b51, + (q31_t)0x642de50d, (q31_t)0xb0533055, (q31_t)0x6429fbb5, (q31_t)0xb04e458a, (q31_t)0x6426121e, (q31_t)0xb0495af0, (q31_t)0x6422284a, (q31_t)0xb0447087, + (q31_t)0x641e3e38, (q31_t)0xb03f864f, (q31_t)0x641a53e8, (q31_t)0xb03a9c49, (q31_t)0x6416695a, (q31_t)0xb035b273, (q31_t)0x64127e8f, (q31_t)0xb030c8cf, + (q31_t)0x640e9386, (q31_t)0xb02bdf5c, (q31_t)0x640aa83f, (q31_t)0xb026f61b, (q31_t)0x6406bcba, (q31_t)0xb0220d0a, (q31_t)0x6402d0f8, (q31_t)0xb01d242b, + (q31_t)0x63fee4f8, (q31_t)0xb0183b7d, (q31_t)0x63faf8bb, (q31_t)0xb0135301, (q31_t)0x63f70c3f, (q31_t)0xb00e6ab5, (q31_t)0x63f31f86, (q31_t)0xb009829c, + (q31_t)0x63ef3290, (q31_t)0xb0049ab3, (q31_t)0x63eb455c, (q31_t)0xafffb2fc, (q31_t)0x63e757ea, (q31_t)0xaffacb76, (q31_t)0x63e36a3a, (q31_t)0xaff5e421, + (q31_t)0x63df7c4d, (q31_t)0xaff0fcfe, (q31_t)0x63db8e22, (q31_t)0xafec160c, (q31_t)0x63d79fba, (q31_t)0xafe72f4c, (q31_t)0x63d3b114, (q31_t)0xafe248bd, + (q31_t)0x63cfc231, (q31_t)0xafdd625f, (q31_t)0x63cbd310, (q31_t)0xafd87c33, (q31_t)0x63c7e3b1, (q31_t)0xafd39638, (q31_t)0x63c3f415, (q31_t)0xafceb06f, + (q31_t)0x63c0043b, (q31_t)0xafc9cad7, (q31_t)0x63bc1424, (q31_t)0xafc4e571, (q31_t)0x63b823cf, (q31_t)0xafc0003c, (q31_t)0x63b4333d, (q31_t)0xafbb1b39, + (q31_t)0x63b0426d, (q31_t)0xafb63667, (q31_t)0x63ac5160, (q31_t)0xafb151c7, (q31_t)0x63a86015, (q31_t)0xafac6d58, (q31_t)0x63a46e8d, (q31_t)0xafa7891b, + (q31_t)0x63a07cc7, (q31_t)0xafa2a50f, (q31_t)0x639c8ac4, (q31_t)0xaf9dc135, (q31_t)0x63989884, (q31_t)0xaf98dd8d, (q31_t)0x6394a606, (q31_t)0xaf93fa16, + (q31_t)0x6390b34a, (q31_t)0xaf8f16d1, (q31_t)0x638cc051, (q31_t)0xaf8a33bd, (q31_t)0x6388cd1b, (q31_t)0xaf8550db, (q31_t)0x6384d9a7, (q31_t)0xaf806e2b, + (q31_t)0x6380e5f6, (q31_t)0xaf7b8bac, (q31_t)0x637cf208, (q31_t)0xaf76a95f, (q31_t)0x6378fddc, (q31_t)0xaf71c743, (q31_t)0x63750973, (q31_t)0xaf6ce55a, + (q31_t)0x637114cc, (q31_t)0xaf6803a2, (q31_t)0x636d1fe9, (q31_t)0xaf63221c, (q31_t)0x63692ac7, (q31_t)0xaf5e40c7, (q31_t)0x63653569, (q31_t)0xaf595fa4, + (q31_t)0x63613fcd, (q31_t)0xaf547eb3, (q31_t)0x635d49f4, (q31_t)0xaf4f9df4, (q31_t)0x635953dd, (q31_t)0xaf4abd66, (q31_t)0x63555d8a, (q31_t)0xaf45dd0b, + (q31_t)0x635166f9, (q31_t)0xaf40fce1, (q31_t)0x634d702b, (q31_t)0xaf3c1ce9, (q31_t)0x6349791f, (q31_t)0xaf373d22, (q31_t)0x634581d6, (q31_t)0xaf325d8e, + (q31_t)0x63418a50, (q31_t)0xaf2d7e2b, (q31_t)0x633d928d, (q31_t)0xaf289efa, (q31_t)0x63399a8d, (q31_t)0xaf23bffb, (q31_t)0x6335a24f, (q31_t)0xaf1ee12e, + (q31_t)0x6331a9d4, (q31_t)0xaf1a0293, (q31_t)0x632db11c, (q31_t)0xaf15242a, (q31_t)0x6329b827, (q31_t)0xaf1045f3, (q31_t)0x6325bef5, (q31_t)0xaf0b67ed, + (q31_t)0x6321c585, (q31_t)0xaf068a1a, (q31_t)0x631dcbd9, (q31_t)0xaf01ac78, (q31_t)0x6319d1ef, (q31_t)0xaefccf09, (q31_t)0x6315d7c8, (q31_t)0xaef7f1cb, + (q31_t)0x6311dd64, (q31_t)0xaef314c0, (q31_t)0x630de2c3, (q31_t)0xaeee37e6, (q31_t)0x6309e7e4, (q31_t)0xaee95b3f, (q31_t)0x6305ecc9, (q31_t)0xaee47ec9, + (q31_t)0x6301f171, (q31_t)0xaedfa285, (q31_t)0x62fdf5db, (q31_t)0xaedac674, (q31_t)0x62f9fa09, (q31_t)0xaed5ea95, (q31_t)0x62f5fdf9, (q31_t)0xaed10ee7, + (q31_t)0x62f201ac, (q31_t)0xaecc336c, (q31_t)0x62ee0523, (q31_t)0xaec75823, (q31_t)0x62ea085c, (q31_t)0xaec27d0c, (q31_t)0x62e60b58, (q31_t)0xaebda227, + (q31_t)0x62e20e17, (q31_t)0xaeb8c774, (q31_t)0x62de109a, (q31_t)0xaeb3ecf3, (q31_t)0x62da12df, (q31_t)0xaeaf12a4, (q31_t)0x62d614e7, (q31_t)0xaeaa3888, + (q31_t)0x62d216b3, (q31_t)0xaea55e9e, (q31_t)0x62ce1841, (q31_t)0xaea084e6, (q31_t)0x62ca1992, (q31_t)0xae9bab60, (q31_t)0x62c61aa7, (q31_t)0xae96d20c, + (q31_t)0x62c21b7e, (q31_t)0xae91f8eb, (q31_t)0x62be1c19, (q31_t)0xae8d1ffb, (q31_t)0x62ba1c77, (q31_t)0xae88473e, (q31_t)0x62b61c98, (q31_t)0xae836eb4, + (q31_t)0x62b21c7b, (q31_t)0xae7e965b, (q31_t)0x62ae1c23, (q31_t)0xae79be35, (q31_t)0x62aa1b8d, (q31_t)0xae74e641, (q31_t)0x62a61aba, (q31_t)0xae700e80, + (q31_t)0x62a219aa, (q31_t)0xae6b36f0, (q31_t)0x629e185e, (q31_t)0xae665f93, (q31_t)0x629a16d5, (q31_t)0xae618869, (q31_t)0x6296150f, (q31_t)0xae5cb171, + (q31_t)0x6292130c, (q31_t)0xae57daab, (q31_t)0x628e10cc, (q31_t)0xae530417, (q31_t)0x628a0e50, (q31_t)0xae4e2db6, (q31_t)0x62860b97, (q31_t)0xae495787, + (q31_t)0x628208a1, (q31_t)0xae44818b, (q31_t)0x627e056e, (q31_t)0xae3fabc1, (q31_t)0x627a01fe, (q31_t)0xae3ad629, (q31_t)0x6275fe52, (q31_t)0xae3600c4, + (q31_t)0x6271fa69, (q31_t)0xae312b92, (q31_t)0x626df643, (q31_t)0xae2c5691, (q31_t)0x6269f1e1, (q31_t)0xae2781c4, (q31_t)0x6265ed42, (q31_t)0xae22ad29, + (q31_t)0x6261e866, (q31_t)0xae1dd8c0, (q31_t)0x625de34e, (q31_t)0xae19048a, (q31_t)0x6259ddf8, (q31_t)0xae143086, (q31_t)0x6255d866, (q31_t)0xae0f5cb5, + (q31_t)0x6251d298, (q31_t)0xae0a8916, (q31_t)0x624dcc8d, (q31_t)0xae05b5aa, (q31_t)0x6249c645, (q31_t)0xae00e271, (q31_t)0x6245bfc0, (q31_t)0xadfc0f6a, + (q31_t)0x6241b8ff, (q31_t)0xadf73c96, (q31_t)0x623db202, (q31_t)0xadf269f4, (q31_t)0x6239aac7, (q31_t)0xaded9785, (q31_t)0x6235a351, (q31_t)0xade8c548, + (q31_t)0x62319b9d, (q31_t)0xade3f33e, (q31_t)0x622d93ad, (q31_t)0xaddf2167, (q31_t)0x62298b81, (q31_t)0xadda4fc3, (q31_t)0x62258317, (q31_t)0xadd57e51, + (q31_t)0x62217a72, (q31_t)0xadd0ad12, (q31_t)0x621d7190, (q31_t)0xadcbdc05, (q31_t)0x62196871, (q31_t)0xadc70b2c, (q31_t)0x62155f16, (q31_t)0xadc23a85, + (q31_t)0x6211557e, (q31_t)0xadbd6a10, (q31_t)0x620d4baa, (q31_t)0xadb899cf, (q31_t)0x62094199, (q31_t)0xadb3c9c0, (q31_t)0x6205374c, (q31_t)0xadaef9e4, + (q31_t)0x62012cc2, (q31_t)0xadaa2a3b, (q31_t)0x61fd21fc, (q31_t)0xada55ac4, (q31_t)0x61f916f9, (q31_t)0xada08b80, (q31_t)0x61f50bba, (q31_t)0xad9bbc70, + (q31_t)0x61f1003f, (q31_t)0xad96ed92, (q31_t)0x61ecf487, (q31_t)0xad921ee6, (q31_t)0x61e8e893, (q31_t)0xad8d506e, (q31_t)0x61e4dc62, (q31_t)0xad888229, + (q31_t)0x61e0cff5, (q31_t)0xad83b416, (q31_t)0x61dcc34c, (q31_t)0xad7ee636, (q31_t)0x61d8b666, (q31_t)0xad7a1889, (q31_t)0x61d4a944, (q31_t)0xad754b0f, + (q31_t)0x61d09be5, (q31_t)0xad707dc8, (q31_t)0x61cc8e4b, (q31_t)0xad6bb0b4, (q31_t)0x61c88074, (q31_t)0xad66e3d3, (q31_t)0x61c47260, (q31_t)0xad621725, + (q31_t)0x61c06410, (q31_t)0xad5d4aaa, (q31_t)0x61bc5584, (q31_t)0xad587e61, (q31_t)0x61b846bc, (q31_t)0xad53b24c, (q31_t)0x61b437b7, (q31_t)0xad4ee66a, + (q31_t)0x61b02876, (q31_t)0xad4a1aba, (q31_t)0x61ac18f9, (q31_t)0xad454f3e, (q31_t)0x61a80940, (q31_t)0xad4083f5, (q31_t)0x61a3f94a, (q31_t)0xad3bb8df, + (q31_t)0x619fe918, (q31_t)0xad36edfc, (q31_t)0x619bd8aa, (q31_t)0xad32234b, (q31_t)0x6197c800, (q31_t)0xad2d58ce, (q31_t)0x6193b719, (q31_t)0xad288e85, + (q31_t)0x618fa5f7, (q31_t)0xad23c46e, (q31_t)0x618b9498, (q31_t)0xad1efa8a, (q31_t)0x618782fd, (q31_t)0xad1a30d9, (q31_t)0x61837126, (q31_t)0xad15675c, + (q31_t)0x617f5f12, (q31_t)0xad109e12, (q31_t)0x617b4cc3, (q31_t)0xad0bd4fb, (q31_t)0x61773a37, (q31_t)0xad070c17, (q31_t)0x61732770, (q31_t)0xad024366, + (q31_t)0x616f146c, (q31_t)0xacfd7ae8, (q31_t)0x616b012c, (q31_t)0xacf8b29e, (q31_t)0x6166edb0, (q31_t)0xacf3ea87, (q31_t)0x6162d9f8, (q31_t)0xacef22a3, + (q31_t)0x615ec603, (q31_t)0xacea5af2, (q31_t)0x615ab1d3, (q31_t)0xace59375, (q31_t)0x61569d67, (q31_t)0xace0cc2b, (q31_t)0x615288be, (q31_t)0xacdc0514, + (q31_t)0x614e73da, (q31_t)0xacd73e30, (q31_t)0x614a5eba, (q31_t)0xacd27780, (q31_t)0x6146495d, (q31_t)0xaccdb103, (q31_t)0x614233c5, (q31_t)0xacc8eab9, + (q31_t)0x613e1df0, (q31_t)0xacc424a3, (q31_t)0x613a07e0, (q31_t)0xacbf5ec0, (q31_t)0x6135f193, (q31_t)0xacba9910, (q31_t)0x6131db0b, (q31_t)0xacb5d394, + (q31_t)0x612dc447, (q31_t)0xacb10e4b, (q31_t)0x6129ad46, (q31_t)0xacac4935, (q31_t)0x6125960a, (q31_t)0xaca78453, (q31_t)0x61217e92, (q31_t)0xaca2bfa4, + (q31_t)0x611d66de, (q31_t)0xac9dfb29, (q31_t)0x61194eee, (q31_t)0xac9936e1, (q31_t)0x611536c2, (q31_t)0xac9472cd, (q31_t)0x61111e5b, (q31_t)0xac8faeec, + (q31_t)0x610d05b7, (q31_t)0xac8aeb3e, (q31_t)0x6108ecd8, (q31_t)0xac8627c4, (q31_t)0x6104d3bc, (q31_t)0xac81647e, (q31_t)0x6100ba65, (q31_t)0xac7ca16b, + (q31_t)0x60fca0d2, (q31_t)0xac77de8b, (q31_t)0x60f88703, (q31_t)0xac731bdf, (q31_t)0x60f46cf9, (q31_t)0xac6e5967, (q31_t)0x60f052b2, (q31_t)0xac699722, + (q31_t)0x60ec3830, (q31_t)0xac64d510, (q31_t)0x60e81d72, (q31_t)0xac601333, (q31_t)0x60e40278, (q31_t)0xac5b5189, (q31_t)0x60dfe743, (q31_t)0xac569012, + (q31_t)0x60dbcbd1, (q31_t)0xac51cecf, (q31_t)0x60d7b024, (q31_t)0xac4d0dc0, (q31_t)0x60d3943b, (q31_t)0xac484ce4, (q31_t)0x60cf7817, (q31_t)0xac438c3c, + (q31_t)0x60cb5bb7, (q31_t)0xac3ecbc7, (q31_t)0x60c73f1b, (q31_t)0xac3a0b87, (q31_t)0x60c32243, (q31_t)0xac354b7a, (q31_t)0x60bf0530, (q31_t)0xac308ba0, + (q31_t)0x60bae7e1, (q31_t)0xac2bcbfa, (q31_t)0x60b6ca56, (q31_t)0xac270c88, (q31_t)0x60b2ac8f, (q31_t)0xac224d4a, (q31_t)0x60ae8e8d, (q31_t)0xac1d8e40, + (q31_t)0x60aa7050, (q31_t)0xac18cf69, (q31_t)0x60a651d7, (q31_t)0xac1410c6, (q31_t)0x60a23322, (q31_t)0xac0f5256, (q31_t)0x609e1431, (q31_t)0xac0a941b, + (q31_t)0x6099f505, (q31_t)0xac05d613, (q31_t)0x6095d59d, (q31_t)0xac01183f, (q31_t)0x6091b5fa, (q31_t)0xabfc5a9f, (q31_t)0x608d961b, (q31_t)0xabf79d33, + (q31_t)0x60897601, (q31_t)0xabf2dffb, (q31_t)0x608555ab, (q31_t)0xabee22f6, (q31_t)0x60813519, (q31_t)0xabe96625, (q31_t)0x607d144c, (q31_t)0xabe4a988, + (q31_t)0x6078f344, (q31_t)0xabdfed1f, (q31_t)0x6074d200, (q31_t)0xabdb30ea, (q31_t)0x6070b080, (q31_t)0xabd674e9, (q31_t)0x606c8ec5, (q31_t)0xabd1b91c, + (q31_t)0x60686ccf, (q31_t)0xabccfd83, (q31_t)0x60644a9d, (q31_t)0xabc8421d, (q31_t)0x6060282f, (q31_t)0xabc386ec, (q31_t)0x605c0587, (q31_t)0xabbecbee, + (q31_t)0x6057e2a2, (q31_t)0xabba1125, (q31_t)0x6053bf82, (q31_t)0xabb5568f, (q31_t)0x604f9c27, (q31_t)0xabb09c2e, (q31_t)0x604b7891, (q31_t)0xababe200, + (q31_t)0x604754bf, (q31_t)0xaba72807, (q31_t)0x604330b1, (q31_t)0xaba26e41, (q31_t)0x603f0c69, (q31_t)0xab9db4b0, (q31_t)0x603ae7e5, (q31_t)0xab98fb52, + (q31_t)0x6036c325, (q31_t)0xab944229, (q31_t)0x60329e2a, (q31_t)0xab8f8934, (q31_t)0x602e78f4, (q31_t)0xab8ad073, (q31_t)0x602a5383, (q31_t)0xab8617e6, + (q31_t)0x60262dd6, (q31_t)0xab815f8d, (q31_t)0x602207ee, (q31_t)0xab7ca768, (q31_t)0x601de1ca, (q31_t)0xab77ef77, (q31_t)0x6019bb6b, (q31_t)0xab7337bb, + (q31_t)0x601594d1, (q31_t)0xab6e8032, (q31_t)0x60116dfc, (q31_t)0xab69c8de, (q31_t)0x600d46ec, (q31_t)0xab6511be, (q31_t)0x60091fa0, (q31_t)0xab605ad2, + (q31_t)0x6004f819, (q31_t)0xab5ba41a, (q31_t)0x6000d057, (q31_t)0xab56ed97, (q31_t)0x5ffca859, (q31_t)0xab523748, (q31_t)0x5ff88021, (q31_t)0xab4d812d, + (q31_t)0x5ff457ad, (q31_t)0xab48cb46, (q31_t)0x5ff02efe, (q31_t)0xab441593, (q31_t)0x5fec0613, (q31_t)0xab3f6015, (q31_t)0x5fe7dcee, (q31_t)0xab3aaacb, + (q31_t)0x5fe3b38d, (q31_t)0xab35f5b5, (q31_t)0x5fdf89f2, (q31_t)0xab3140d4, (q31_t)0x5fdb601b, (q31_t)0xab2c8c27, (q31_t)0x5fd73609, (q31_t)0xab27d7ae, + (q31_t)0x5fd30bbc, (q31_t)0xab23236a, (q31_t)0x5fcee133, (q31_t)0xab1e6f5a, (q31_t)0x5fcab670, (q31_t)0xab19bb7e, (q31_t)0x5fc68b72, (q31_t)0xab1507d7, + (q31_t)0x5fc26038, (q31_t)0xab105464, (q31_t)0x5fbe34c4, (q31_t)0xab0ba125, (q31_t)0x5fba0914, (q31_t)0xab06ee1b, (q31_t)0x5fb5dd29, (q31_t)0xab023b46, + (q31_t)0x5fb1b104, (q31_t)0xaafd88a4, (q31_t)0x5fad84a3, (q31_t)0xaaf8d637, (q31_t)0x5fa95807, (q31_t)0xaaf423ff, (q31_t)0x5fa52b31, (q31_t)0xaaef71fb, + (q31_t)0x5fa0fe1f, (q31_t)0xaaeac02c, (q31_t)0x5f9cd0d2, (q31_t)0xaae60e91, (q31_t)0x5f98a34a, (q31_t)0xaae15d2a, (q31_t)0x5f947588, (q31_t)0xaadcabf8, + (q31_t)0x5f90478a, (q31_t)0xaad7fafb, (q31_t)0x5f8c1951, (q31_t)0xaad34a32, (q31_t)0x5f87eade, (q31_t)0xaace999d, (q31_t)0x5f83bc2f, (q31_t)0xaac9e93e, + (q31_t)0x5f7f8d46, (q31_t)0xaac53912, (q31_t)0x5f7b5e22, (q31_t)0xaac0891c, (q31_t)0x5f772ec2, (q31_t)0xaabbd959, (q31_t)0x5f72ff28, (q31_t)0xaab729cc, + (q31_t)0x5f6ecf53, (q31_t)0xaab27a73, (q31_t)0x5f6a9f44, (q31_t)0xaaadcb4f, (q31_t)0x5f666ef9, (q31_t)0xaaa91c5f, (q31_t)0x5f623e73, (q31_t)0xaaa46da4, + (q31_t)0x5f5e0db3, (q31_t)0xaa9fbf1e, (q31_t)0x5f59dcb8, (q31_t)0xaa9b10cc, (q31_t)0x5f55ab82, (q31_t)0xaa9662af, (q31_t)0x5f517a11, (q31_t)0xaa91b4c7, + (q31_t)0x5f4d4865, (q31_t)0xaa8d0713, (q31_t)0x5f49167f, (q31_t)0xaa885994, (q31_t)0x5f44e45e, (q31_t)0xaa83ac4a, (q31_t)0x5f40b202, (q31_t)0xaa7eff34, + (q31_t)0x5f3c7f6b, (q31_t)0xaa7a5253, (q31_t)0x5f384c9a, (q31_t)0xaa75a5a8, (q31_t)0x5f34198e, (q31_t)0xaa70f930, (q31_t)0x5f2fe647, (q31_t)0xaa6c4cee, + (q31_t)0x5f2bb2c5, (q31_t)0xaa67a0e0, (q31_t)0x5f277f09, (q31_t)0xaa62f507, (q31_t)0x5f234b12, (q31_t)0xaa5e4963, (q31_t)0x5f1f16e0, (q31_t)0xaa599df4, + (q31_t)0x5f1ae274, (q31_t)0xaa54f2ba, (q31_t)0x5f16adcc, (q31_t)0xaa5047b4, (q31_t)0x5f1278eb, (q31_t)0xaa4b9ce3, (q31_t)0x5f0e43ce, (q31_t)0xaa46f248, + (q31_t)0x5f0a0e77, (q31_t)0xaa4247e1, (q31_t)0x5f05d8e6, (q31_t)0xaa3d9daf, (q31_t)0x5f01a31a, (q31_t)0xaa38f3b1, (q31_t)0x5efd6d13, (q31_t)0xaa3449e9, + (q31_t)0x5ef936d1, (q31_t)0xaa2fa056, (q31_t)0x5ef50055, (q31_t)0xaa2af6f7, (q31_t)0x5ef0c99f, (q31_t)0xaa264dce, (q31_t)0x5eec92ae, (q31_t)0xaa21a4d9, + (q31_t)0x5ee85b82, (q31_t)0xaa1cfc1a, (q31_t)0x5ee4241c, (q31_t)0xaa18538f, (q31_t)0x5edfec7b, (q31_t)0xaa13ab3a, (q31_t)0x5edbb49f, (q31_t)0xaa0f0319, + (q31_t)0x5ed77c8a, (q31_t)0xaa0a5b2e, (q31_t)0x5ed34439, (q31_t)0xaa05b377, (q31_t)0x5ecf0baf, (q31_t)0xaa010bf6, (q31_t)0x5ecad2e9, (q31_t)0xa9fc64a9, + (q31_t)0x5ec699e9, (q31_t)0xa9f7bd92, (q31_t)0x5ec260af, (q31_t)0xa9f316b0, (q31_t)0x5ebe273b, (q31_t)0xa9ee7002, (q31_t)0x5eb9ed8b, (q31_t)0xa9e9c98a, + (q31_t)0x5eb5b3a2, (q31_t)0xa9e52347, (q31_t)0x5eb1797e, (q31_t)0xa9e07d39, (q31_t)0x5ead3f1f, (q31_t)0xa9dbd761, (q31_t)0x5ea90487, (q31_t)0xa9d731bd, + (q31_t)0x5ea4c9b3, (q31_t)0xa9d28c4e, (q31_t)0x5ea08ea6, (q31_t)0xa9cde715, (q31_t)0x5e9c535e, (q31_t)0xa9c94211, (q31_t)0x5e9817dc, (q31_t)0xa9c49d42, + (q31_t)0x5e93dc1f, (q31_t)0xa9bff8a8, (q31_t)0x5e8fa028, (q31_t)0xa9bb5444, (q31_t)0x5e8b63f7, (q31_t)0xa9b6b014, (q31_t)0x5e87278b, (q31_t)0xa9b20c1a, + (q31_t)0x5e82eae5, (q31_t)0xa9ad6855, (q31_t)0x5e7eae05, (q31_t)0xa9a8c4c5, (q31_t)0x5e7a70ea, (q31_t)0xa9a4216b, (q31_t)0x5e763395, (q31_t)0xa99f7e46, + (q31_t)0x5e71f606, (q31_t)0xa99adb56, (q31_t)0x5e6db83d, (q31_t)0xa996389b, (q31_t)0x5e697a39, (q31_t)0xa9919616, (q31_t)0x5e653bfc, (q31_t)0xa98cf3c6, + (q31_t)0x5e60fd84, (q31_t)0xa98851ac, (q31_t)0x5e5cbed1, (q31_t)0xa983afc6, (q31_t)0x5e587fe5, (q31_t)0xa97f0e16, (q31_t)0x5e5440be, (q31_t)0xa97a6c9c, + (q31_t)0x5e50015d, (q31_t)0xa975cb57, (q31_t)0x5e4bc1c2, (q31_t)0xa9712a47, (q31_t)0x5e4781ed, (q31_t)0xa96c896c, (q31_t)0x5e4341de, (q31_t)0xa967e8c7, + (q31_t)0x5e3f0194, (q31_t)0xa9634858, (q31_t)0x5e3ac110, (q31_t)0xa95ea81d, (q31_t)0x5e368053, (q31_t)0xa95a0819, (q31_t)0x5e323f5b, (q31_t)0xa9556849, + (q31_t)0x5e2dfe29, (q31_t)0xa950c8b0, (q31_t)0x5e29bcbd, (q31_t)0xa94c294b, (q31_t)0x5e257b17, (q31_t)0xa9478a1c, (q31_t)0x5e213936, (q31_t)0xa942eb23, + (q31_t)0x5e1cf71c, (q31_t)0xa93e4c5f, (q31_t)0x5e18b4c8, (q31_t)0xa939add1, (q31_t)0x5e147239, (q31_t)0xa9350f78, (q31_t)0x5e102f71, (q31_t)0xa9307155, + (q31_t)0x5e0bec6e, (q31_t)0xa92bd367, (q31_t)0x5e07a932, (q31_t)0xa92735af, (q31_t)0x5e0365bb, (q31_t)0xa922982c, (q31_t)0x5dff220b, (q31_t)0xa91dfadf, + (q31_t)0x5dfade20, (q31_t)0xa9195dc7, (q31_t)0x5df699fc, (q31_t)0xa914c0e6, (q31_t)0x5df2559e, (q31_t)0xa9102439, (q31_t)0x5dee1105, (q31_t)0xa90b87c3, + (q31_t)0x5de9cc33, (q31_t)0xa906eb82, (q31_t)0x5de58727, (q31_t)0xa9024f76, (q31_t)0x5de141e1, (q31_t)0xa8fdb3a1, (q31_t)0x5ddcfc61, (q31_t)0xa8f91801, + (q31_t)0x5dd8b6a7, (q31_t)0xa8f47c97, (q31_t)0x5dd470b3, (q31_t)0xa8efe162, (q31_t)0x5dd02a85, (q31_t)0xa8eb4663, (q31_t)0x5dcbe41d, (q31_t)0xa8e6ab9a, + (q31_t)0x5dc79d7c, (q31_t)0xa8e21106, (q31_t)0x5dc356a1, (q31_t)0xa8dd76a9, (q31_t)0x5dbf0f8c, (q31_t)0xa8d8dc81, (q31_t)0x5dbac83d, (q31_t)0xa8d4428f, + (q31_t)0x5db680b4, (q31_t)0xa8cfa8d2, (q31_t)0x5db238f1, (q31_t)0xa8cb0f4b, (q31_t)0x5dadf0f5, (q31_t)0xa8c675fb, (q31_t)0x5da9a8bf, (q31_t)0xa8c1dce0, + (q31_t)0x5da5604f, (q31_t)0xa8bd43fa, (q31_t)0x5da117a5, (q31_t)0xa8b8ab4b, (q31_t)0x5d9ccec2, (q31_t)0xa8b412d1, (q31_t)0x5d9885a5, (q31_t)0xa8af7a8e, + (q31_t)0x5d943c4e, (q31_t)0xa8aae280, (q31_t)0x5d8ff2bd, (q31_t)0xa8a64aa8, (q31_t)0x5d8ba8f3, (q31_t)0xa8a1b306, (q31_t)0x5d875eef, (q31_t)0xa89d1b99, + (q31_t)0x5d8314b1, (q31_t)0xa8988463, (q31_t)0x5d7eca39, (q31_t)0xa893ed63, (q31_t)0x5d7a7f88, (q31_t)0xa88f5698, (q31_t)0x5d76349d, (q31_t)0xa88ac004, + (q31_t)0x5d71e979, (q31_t)0xa88629a5, (q31_t)0x5d6d9e1b, (q31_t)0xa881937c, (q31_t)0x5d695283, (q31_t)0xa87cfd8a, (q31_t)0x5d6506b2, (q31_t)0xa87867cd, + (q31_t)0x5d60baa7, (q31_t)0xa873d246, (q31_t)0x5d5c6e62, (q31_t)0xa86f3cf6, (q31_t)0x5d5821e4, (q31_t)0xa86aa7db, (q31_t)0x5d53d52d, (q31_t)0xa86612f6, + (q31_t)0x5d4f883b, (q31_t)0xa8617e48, (q31_t)0x5d4b3b10, (q31_t)0xa85ce9cf, (q31_t)0x5d46edac, (q31_t)0xa858558d, (q31_t)0x5d42a00e, (q31_t)0xa853c180, + (q31_t)0x5d3e5237, (q31_t)0xa84f2daa, (q31_t)0x5d3a0426, (q31_t)0xa84a9a0a, (q31_t)0x5d35b5db, (q31_t)0xa84606a0, (q31_t)0x5d316757, (q31_t)0xa841736c, + (q31_t)0x5d2d189a, (q31_t)0xa83ce06e, (q31_t)0x5d28c9a3, (q31_t)0xa8384da6, (q31_t)0x5d247a72, (q31_t)0xa833bb14, (q31_t)0x5d202b09, (q31_t)0xa82f28b9, + (q31_t)0x5d1bdb65, (q31_t)0xa82a9693, (q31_t)0x5d178b89, (q31_t)0xa82604a4, (q31_t)0x5d133b72, (q31_t)0xa82172eb, (q31_t)0x5d0eeb23, (q31_t)0xa81ce169, + (q31_t)0x5d0a9a9a, (q31_t)0xa818501c, (q31_t)0x5d0649d7, (q31_t)0xa813bf06, (q31_t)0x5d01f8dc, (q31_t)0xa80f2e26, (q31_t)0x5cfda7a7, (q31_t)0xa80a9d7c, + (q31_t)0x5cf95638, (q31_t)0xa8060d08, (q31_t)0x5cf50490, (q31_t)0xa8017ccb, (q31_t)0x5cf0b2af, (q31_t)0xa7fcecc4, (q31_t)0x5cec6095, (q31_t)0xa7f85cf3, + (q31_t)0x5ce80e41, (q31_t)0xa7f3cd59, (q31_t)0x5ce3bbb4, (q31_t)0xa7ef3df5, (q31_t)0x5cdf68ed, (q31_t)0xa7eaaec7, (q31_t)0x5cdb15ed, (q31_t)0xa7e61fd0, + (q31_t)0x5cd6c2b5, (q31_t)0xa7e1910f, (q31_t)0x5cd26f42, (q31_t)0xa7dd0284, (q31_t)0x5cce1b97, (q31_t)0xa7d8742f, (q31_t)0x5cc9c7b2, (q31_t)0xa7d3e611, + (q31_t)0x5cc57394, (q31_t)0xa7cf582a, (q31_t)0x5cc11f3d, (q31_t)0xa7caca79, (q31_t)0x5cbccaac, (q31_t)0xa7c63cfe, (q31_t)0x5cb875e3, (q31_t)0xa7c1afb9, + (q31_t)0x5cb420e0, (q31_t)0xa7bd22ac, (q31_t)0x5cafcba4, (q31_t)0xa7b895d4, (q31_t)0x5cab762f, (q31_t)0xa7b40933, (q31_t)0x5ca72080, (q31_t)0xa7af7cc8, + (q31_t)0x5ca2ca99, (q31_t)0xa7aaf094, (q31_t)0x5c9e7478, (q31_t)0xa7a66497, (q31_t)0x5c9a1e1e, (q31_t)0xa7a1d8d0, (q31_t)0x5c95c78b, (q31_t)0xa79d4d3f, + (q31_t)0x5c9170bf, (q31_t)0xa798c1e5, (q31_t)0x5c8d19ba, (q31_t)0xa79436c1, (q31_t)0x5c88c27c, (q31_t)0xa78fabd4, (q31_t)0x5c846b05, (q31_t)0xa78b211e, + (q31_t)0x5c801354, (q31_t)0xa786969e, (q31_t)0x5c7bbb6b, (q31_t)0xa7820c55, (q31_t)0x5c776348, (q31_t)0xa77d8242, (q31_t)0x5c730aed, (q31_t)0xa778f866, + (q31_t)0x5c6eb258, (q31_t)0xa7746ec0, (q31_t)0x5c6a598b, (q31_t)0xa76fe551, (q31_t)0x5c660084, (q31_t)0xa76b5c19, (q31_t)0x5c61a745, (q31_t)0xa766d317, + (q31_t)0x5c5d4dcc, (q31_t)0xa7624a4d, (q31_t)0x5c58f41a, (q31_t)0xa75dc1b8, (q31_t)0x5c549a30, (q31_t)0xa759395b, (q31_t)0x5c50400d, (q31_t)0xa754b134, + (q31_t)0x5c4be5b0, (q31_t)0xa7502943, (q31_t)0x5c478b1b, (q31_t)0xa74ba18a, (q31_t)0x5c43304d, (q31_t)0xa7471a07, (q31_t)0x5c3ed545, (q31_t)0xa74292bb, + (q31_t)0x5c3a7a05, (q31_t)0xa73e0ba5, (q31_t)0x5c361e8c, (q31_t)0xa73984c7, (q31_t)0x5c31c2db, (q31_t)0xa734fe1f, (q31_t)0x5c2d66f0, (q31_t)0xa73077ae, + (q31_t)0x5c290acc, (q31_t)0xa72bf174, (q31_t)0x5c24ae70, (q31_t)0xa7276b70, (q31_t)0x5c2051db, (q31_t)0xa722e5a3, (q31_t)0x5c1bf50d, (q31_t)0xa71e600d, + (q31_t)0x5c179806, (q31_t)0xa719daae, (q31_t)0x5c133ac6, (q31_t)0xa7155586, (q31_t)0x5c0edd4e, (q31_t)0xa710d095, (q31_t)0x5c0a7f9c, (q31_t)0xa70c4bda, + (q31_t)0x5c0621b2, (q31_t)0xa707c757, (q31_t)0x5c01c38f, (q31_t)0xa703430a, (q31_t)0x5bfd6534, (q31_t)0xa6febef4, (q31_t)0x5bf906a0, (q31_t)0xa6fa3b15, + (q31_t)0x5bf4a7d2, (q31_t)0xa6f5b76d, (q31_t)0x5bf048cd, (q31_t)0xa6f133fc, (q31_t)0x5bebe98e, (q31_t)0xa6ecb0c2, (q31_t)0x5be78a17, (q31_t)0xa6e82dbe, + (q31_t)0x5be32a67, (q31_t)0xa6e3aaf2, (q31_t)0x5bdeca7f, (q31_t)0xa6df285d, (q31_t)0x5bda6a5d, (q31_t)0xa6daa5fe, (q31_t)0x5bd60a03, (q31_t)0xa6d623d7, + (q31_t)0x5bd1a971, (q31_t)0xa6d1a1e7, (q31_t)0x5bcd48a6, (q31_t)0xa6cd202d, (q31_t)0x5bc8e7a2, (q31_t)0xa6c89eab, (q31_t)0x5bc48666, (q31_t)0xa6c41d60, + (q31_t)0x5bc024f0, (q31_t)0xa6bf9c4b, (q31_t)0x5bbbc343, (q31_t)0xa6bb1b6e, (q31_t)0x5bb7615d, (q31_t)0xa6b69ac8, (q31_t)0x5bb2ff3e, (q31_t)0xa6b21a59, + (q31_t)0x5bae9ce7, (q31_t)0xa6ad9a21, (q31_t)0x5baa3a57, (q31_t)0xa6a91a20, (q31_t)0x5ba5d78e, (q31_t)0xa6a49a56, (q31_t)0x5ba1748d, (q31_t)0xa6a01ac4, + (q31_t)0x5b9d1154, (q31_t)0xa69b9b68, (q31_t)0x5b98ade2, (q31_t)0xa6971c44, (q31_t)0x5b944a37, (q31_t)0xa6929d57, (q31_t)0x5b8fe654, (q31_t)0xa68e1ea1, + (q31_t)0x5b8b8239, (q31_t)0xa689a022, (q31_t)0x5b871de5, (q31_t)0xa68521da, (q31_t)0x5b82b958, (q31_t)0xa680a3ca, (q31_t)0x5b7e5493, (q31_t)0xa67c25f0, + (q31_t)0x5b79ef96, (q31_t)0xa677a84e, (q31_t)0x5b758a60, (q31_t)0xa6732ae3, (q31_t)0x5b7124f2, (q31_t)0xa66eadb0, (q31_t)0x5b6cbf4c, (q31_t)0xa66a30b3, + (q31_t)0x5b68596d, (q31_t)0xa665b3ee, (q31_t)0x5b63f355, (q31_t)0xa6613760, (q31_t)0x5b5f8d06, (q31_t)0xa65cbb0a, (q31_t)0x5b5b267e, (q31_t)0xa6583eeb, + (q31_t)0x5b56bfbd, (q31_t)0xa653c303, (q31_t)0x5b5258c4, (q31_t)0xa64f4752, (q31_t)0x5b4df193, (q31_t)0xa64acbd9, (q31_t)0x5b498a2a, (q31_t)0xa6465097, + (q31_t)0x5b452288, (q31_t)0xa641d58c, (q31_t)0x5b40baae, (q31_t)0xa63d5ab9, (q31_t)0x5b3c529c, (q31_t)0xa638e01d, (q31_t)0x5b37ea51, (q31_t)0xa63465b9, + (q31_t)0x5b3381ce, (q31_t)0xa62feb8b, (q31_t)0x5b2f1913, (q31_t)0xa62b7196, (q31_t)0x5b2ab020, (q31_t)0xa626f7d7, (q31_t)0x5b2646f4, (q31_t)0xa6227e50, + (q31_t)0x5b21dd90, (q31_t)0xa61e0501, (q31_t)0x5b1d73f4, (q31_t)0xa6198be9, (q31_t)0x5b190a20, (q31_t)0xa6151308, (q31_t)0x5b14a014, (q31_t)0xa6109a5f, + (q31_t)0x5b1035cf, (q31_t)0xa60c21ee, (q31_t)0x5b0bcb52, (q31_t)0xa607a9b4, (q31_t)0x5b07609d, (q31_t)0xa60331b1, (q31_t)0x5b02f5b0, (q31_t)0xa5feb9e6, + (q31_t)0x5afe8a8b, (q31_t)0xa5fa4252, (q31_t)0x5afa1f2e, (q31_t)0xa5f5caf6, (q31_t)0x5af5b398, (q31_t)0xa5f153d2, (q31_t)0x5af147ca, (q31_t)0xa5ecdce5, + (q31_t)0x5aecdbc5, (q31_t)0xa5e8662f, (q31_t)0x5ae86f87, (q31_t)0xa5e3efb1, (q31_t)0x5ae40311, (q31_t)0xa5df796b, (q31_t)0x5adf9663, (q31_t)0xa5db035c, + (q31_t)0x5adb297d, (q31_t)0xa5d68d85, (q31_t)0x5ad6bc5f, (q31_t)0xa5d217e6, (q31_t)0x5ad24f09, (q31_t)0xa5cda27e, (q31_t)0x5acde17b, (q31_t)0xa5c92d4e, + (q31_t)0x5ac973b5, (q31_t)0xa5c4b855, (q31_t)0x5ac505b7, (q31_t)0xa5c04395, (q31_t)0x5ac09781, (q31_t)0xa5bbcf0b, (q31_t)0x5abc2912, (q31_t)0xa5b75aba, + (q31_t)0x5ab7ba6c, (q31_t)0xa5b2e6a0, (q31_t)0x5ab34b8e, (q31_t)0xa5ae72be, (q31_t)0x5aaedc78, (q31_t)0xa5a9ff14, (q31_t)0x5aaa6d2b, (q31_t)0xa5a58ba1, + (q31_t)0x5aa5fda5, (q31_t)0xa5a11866, (q31_t)0x5aa18de7, (q31_t)0xa59ca563, (q31_t)0x5a9d1df1, (q31_t)0xa5983297, (q31_t)0x5a98adc4, (q31_t)0xa593c004, + (q31_t)0x5a943d5e, (q31_t)0xa58f4da8, (q31_t)0x5a8fccc1, (q31_t)0xa58adb84, (q31_t)0x5a8b5bec, (q31_t)0xa5866997, (q31_t)0x5a86eadf, (q31_t)0xa581f7e3, + (q31_t)0x5a82799a, (q31_t)0xa57d8666, (q31_t)0x5a7e081d, (q31_t)0xa5791521, (q31_t)0x5a799669, (q31_t)0xa574a414, (q31_t)0x5a75247c, (q31_t)0xa570333f, + (q31_t)0x5a70b258, (q31_t)0xa56bc2a2, (q31_t)0x5a6c3ffc, (q31_t)0xa567523c, (q31_t)0x5a67cd69, (q31_t)0xa562e20f, (q31_t)0x5a635a9d, (q31_t)0xa55e7219, + (q31_t)0x5a5ee79a, (q31_t)0xa55a025b, (q31_t)0x5a5a745f, (q31_t)0xa55592d5, (q31_t)0x5a5600ec, (q31_t)0xa5512388, (q31_t)0x5a518d42, (q31_t)0xa54cb472, + (q31_t)0x5a4d1960, (q31_t)0xa5484594, (q31_t)0x5a48a546, (q31_t)0xa543d6ee, (q31_t)0x5a4430f5, (q31_t)0xa53f687f, (q31_t)0x5a3fbc6b, (q31_t)0xa53afa49, + (q31_t)0x5a3b47ab, (q31_t)0xa5368c4b, (q31_t)0x5a36d2b2, (q31_t)0xa5321e85, (q31_t)0x5a325d82, (q31_t)0xa52db0f7, (q31_t)0x5a2de81a, (q31_t)0xa52943a1, + (q31_t)0x5a29727b, (q31_t)0xa524d683, (q31_t)0x5a24fca4, (q31_t)0xa520699d, (q31_t)0x5a208695, (q31_t)0xa51bfcef, (q31_t)0x5a1c104f, (q31_t)0xa5179079, + (q31_t)0x5a1799d1, (q31_t)0xa513243b, (q31_t)0x5a13231b, (q31_t)0xa50eb836, (q31_t)0x5a0eac2e, (q31_t)0xa50a4c68, (q31_t)0x5a0a350a, (q31_t)0xa505e0d2, + (q31_t)0x5a05bdae, (q31_t)0xa5017575, (q31_t)0x5a01461a, (q31_t)0xa4fd0a50, (q31_t)0x59fcce4f, (q31_t)0xa4f89f63, (q31_t)0x59f8564c, (q31_t)0xa4f434ae, + (q31_t)0x59f3de12, (q31_t)0xa4efca31, (q31_t)0x59ef65a1, (q31_t)0xa4eb5fec, (q31_t)0x59eaecf8, (q31_t)0xa4e6f5e0, (q31_t)0x59e67417, (q31_t)0xa4e28c0c, + (q31_t)0x59e1faff, (q31_t)0xa4de2270, (q31_t)0x59dd81b0, (q31_t)0xa4d9b90c, (q31_t)0x59d90829, (q31_t)0xa4d54fe0, (q31_t)0x59d48e6a, (q31_t)0xa4d0e6ed, + (q31_t)0x59d01475, (q31_t)0xa4cc7e32, (q31_t)0x59cb9a47, (q31_t)0xa4c815af, (q31_t)0x59c71fe3, (q31_t)0xa4c3ad64, (q31_t)0x59c2a547, (q31_t)0xa4bf4552, + (q31_t)0x59be2a74, (q31_t)0xa4badd78, (q31_t)0x59b9af69, (q31_t)0xa4b675d6, (q31_t)0x59b53427, (q31_t)0xa4b20e6d, (q31_t)0x59b0b8ae, (q31_t)0xa4ada73c, + (q31_t)0x59ac3cfd, (q31_t)0xa4a94043, (q31_t)0x59a7c115, (q31_t)0xa4a4d982, (q31_t)0x59a344f6, (q31_t)0xa4a072fa, (q31_t)0x599ec8a0, (q31_t)0xa49c0cab, + (q31_t)0x599a4c12, (q31_t)0xa497a693, (q31_t)0x5995cf4d, (q31_t)0xa49340b4, (q31_t)0x59915250, (q31_t)0xa48edb0e, (q31_t)0x598cd51d, (q31_t)0xa48a75a0, + (q31_t)0x598857b2, (q31_t)0xa486106a, (q31_t)0x5983da10, (q31_t)0xa481ab6d, (q31_t)0x597f5c36, (q31_t)0xa47d46a8, (q31_t)0x597ade26, (q31_t)0xa478e21b, + (q31_t)0x59765fde, (q31_t)0xa4747dc7, (q31_t)0x5971e15f, (q31_t)0xa47019ac, (q31_t)0x596d62a9, (q31_t)0xa46bb5c9, (q31_t)0x5968e3bc, (q31_t)0xa467521e, + (q31_t)0x59646498, (q31_t)0xa462eeac, (q31_t)0x595fe53c, (q31_t)0xa45e8b73, (q31_t)0x595b65aa, (q31_t)0xa45a2872, (q31_t)0x5956e5e0, (q31_t)0xa455c5a9, + (q31_t)0x595265df, (q31_t)0xa4516319, (q31_t)0x594de5a7, (q31_t)0xa44d00c2, (q31_t)0x59496538, (q31_t)0xa4489ea3, (q31_t)0x5944e492, (q31_t)0xa4443cbd, + (q31_t)0x594063b5, (q31_t)0xa43fdb10, (q31_t)0x593be2a0, (q31_t)0xa43b799a, (q31_t)0x59376155, (q31_t)0xa437185e, (q31_t)0x5932dfd3, (q31_t)0xa432b75a, + (q31_t)0x592e5e19, (q31_t)0xa42e568f, (q31_t)0x5929dc29, (q31_t)0xa429f5fd, (q31_t)0x59255a02, (q31_t)0xa42595a3, (q31_t)0x5920d7a3, (q31_t)0xa4213581, + (q31_t)0x591c550e, (q31_t)0xa41cd599, (q31_t)0x5917d242, (q31_t)0xa41875e9, (q31_t)0x59134f3e, (q31_t)0xa4141672, (q31_t)0x590ecc04, (q31_t)0xa40fb733, + (q31_t)0x590a4893, (q31_t)0xa40b582e, (q31_t)0x5905c4eb, (q31_t)0xa406f960, (q31_t)0x5901410c, (q31_t)0xa4029acc, (q31_t)0x58fcbcf6, (q31_t)0xa3fe3c71, + (q31_t)0x58f838a9, (q31_t)0xa3f9de4e, (q31_t)0x58f3b426, (q31_t)0xa3f58064, (q31_t)0x58ef2f6b, (q31_t)0xa3f122b2, (q31_t)0x58eaaa7a, (q31_t)0xa3ecc53a, + (q31_t)0x58e62552, (q31_t)0xa3e867fa, (q31_t)0x58e19ff3, (q31_t)0xa3e40af3, (q31_t)0x58dd1a5d, (q31_t)0xa3dfae25, (q31_t)0x58d89490, (q31_t)0xa3db5190, + (q31_t)0x58d40e8c, (q31_t)0xa3d6f534, (q31_t)0x58cf8852, (q31_t)0xa3d29910, (q31_t)0x58cb01e1, (q31_t)0xa3ce3d25, (q31_t)0x58c67b39, (q31_t)0xa3c9e174, + (q31_t)0x58c1f45b, (q31_t)0xa3c585fb, (q31_t)0x58bd6d45, (q31_t)0xa3c12abb, (q31_t)0x58b8e5f9, (q31_t)0xa3bccfb3, (q31_t)0x58b45e76, (q31_t)0xa3b874e5, + (q31_t)0x58afd6bd, (q31_t)0xa3b41a50, (q31_t)0x58ab4ecc, (q31_t)0xa3afbff3, (q31_t)0x58a6c6a5, (q31_t)0xa3ab65d0, (q31_t)0x58a23e48, (q31_t)0xa3a70be6, + (q31_t)0x589db5b3, (q31_t)0xa3a2b234, (q31_t)0x58992ce9, (q31_t)0xa39e58bb, (q31_t)0x5894a3e7, (q31_t)0xa399ff7c, (q31_t)0x58901aaf, (q31_t)0xa395a675, + (q31_t)0x588b9140, (q31_t)0xa3914da8, (q31_t)0x5887079a, (q31_t)0xa38cf513, (q31_t)0x58827dbe, (q31_t)0xa3889cb8, (q31_t)0x587df3ab, (q31_t)0xa3844495, + (q31_t)0x58796962, (q31_t)0xa37fecac, (q31_t)0x5874dee2, (q31_t)0xa37b94fb, (q31_t)0x5870542c, (q31_t)0xa3773d84, (q31_t)0x586bc93f, (q31_t)0xa372e646, + (q31_t)0x58673e1b, (q31_t)0xa36e8f41, (q31_t)0x5862b2c1, (q31_t)0xa36a3875, (q31_t)0x585e2730, (q31_t)0xa365e1e2, (q31_t)0x58599b69, (q31_t)0xa3618b88, + (q31_t)0x58550f6c, (q31_t)0xa35d3567, (q31_t)0x58508338, (q31_t)0xa358df80, (q31_t)0x584bf6cd, (q31_t)0xa35489d1, (q31_t)0x58476a2c, (q31_t)0xa350345c, + (q31_t)0x5842dd54, (q31_t)0xa34bdf20, (q31_t)0x583e5047, (q31_t)0xa3478a1d, (q31_t)0x5839c302, (q31_t)0xa3433554, (q31_t)0x58353587, (q31_t)0xa33ee0c3, + (q31_t)0x5830a7d6, (q31_t)0xa33a8c6c, (q31_t)0x582c19ef, (q31_t)0xa336384e, (q31_t)0x58278bd1, (q31_t)0xa331e469, (q31_t)0x5822fd7c, (q31_t)0xa32d90be, + (q31_t)0x581e6ef1, (q31_t)0xa3293d4b, (q31_t)0x5819e030, (q31_t)0xa324ea13, (q31_t)0x58155139, (q31_t)0xa3209713, (q31_t)0x5810c20b, (q31_t)0xa31c444c, + (q31_t)0x580c32a7, (q31_t)0xa317f1bf, (q31_t)0x5807a30d, (q31_t)0xa3139f6b, (q31_t)0x5803133c, (q31_t)0xa30f4d51, (q31_t)0x57fe8335, (q31_t)0xa30afb70, + (q31_t)0x57f9f2f8, (q31_t)0xa306a9c8, (q31_t)0x57f56284, (q31_t)0xa3025859, (q31_t)0x57f0d1da, (q31_t)0xa2fe0724, (q31_t)0x57ec40fa, (q31_t)0xa2f9b629, + (q31_t)0x57e7afe4, (q31_t)0xa2f56566, (q31_t)0x57e31e97, (q31_t)0xa2f114dd, (q31_t)0x57de8d15, (q31_t)0xa2ecc48e, (q31_t)0x57d9fb5c, (q31_t)0xa2e87477, + (q31_t)0x57d5696d, (q31_t)0xa2e4249b, (q31_t)0x57d0d747, (q31_t)0xa2dfd4f7, (q31_t)0x57cc44ec, (q31_t)0xa2db858e, (q31_t)0x57c7b25a, (q31_t)0xa2d7365d, + (q31_t)0x57c31f92, (q31_t)0xa2d2e766, (q31_t)0x57be8c94, (q31_t)0xa2ce98a9, (q31_t)0x57b9f960, (q31_t)0xa2ca4a25, (q31_t)0x57b565f6, (q31_t)0xa2c5fbda, + (q31_t)0x57b0d256, (q31_t)0xa2c1adc9, (q31_t)0x57ac3e80, (q31_t)0xa2bd5ff2, (q31_t)0x57a7aa73, (q31_t)0xa2b91254, (q31_t)0x57a31631, (q31_t)0xa2b4c4f0, + (q31_t)0x579e81b8, (q31_t)0xa2b077c5, (q31_t)0x5799ed0a, (q31_t)0xa2ac2ad3, (q31_t)0x57955825, (q31_t)0xa2a7de1c, (q31_t)0x5790c30a, (q31_t)0xa2a3919e, + (q31_t)0x578c2dba, (q31_t)0xa29f4559, (q31_t)0x57879833, (q31_t)0xa29af94e, (q31_t)0x57830276, (q31_t)0xa296ad7d, (q31_t)0x577e6c84, (q31_t)0xa29261e5, + (q31_t)0x5779d65b, (q31_t)0xa28e1687, (q31_t)0x57753ffc, (q31_t)0xa289cb63, (q31_t)0x5770a968, (q31_t)0xa2858078, (q31_t)0x576c129d, (q31_t)0xa28135c7, + (q31_t)0x57677b9d, (q31_t)0xa27ceb4f, (q31_t)0x5762e467, (q31_t)0xa278a111, (q31_t)0x575e4cfa, (q31_t)0xa274570d, (q31_t)0x5759b558, (q31_t)0xa2700d43, + (q31_t)0x57551d80, (q31_t)0xa26bc3b2, (q31_t)0x57508572, (q31_t)0xa2677a5b, (q31_t)0x574bed2f, (q31_t)0xa263313e, (q31_t)0x574754b5, (q31_t)0xa25ee85b, + (q31_t)0x5742bc06, (q31_t)0xa25a9fb1, (q31_t)0x573e2320, (q31_t)0xa2565741, (q31_t)0x57398a05, (q31_t)0xa2520f0b, (q31_t)0x5734f0b5, (q31_t)0xa24dc70f, + (q31_t)0x5730572e, (q31_t)0xa2497f4c, (q31_t)0x572bbd71, (q31_t)0xa24537c3, (q31_t)0x5727237f, (q31_t)0xa240f074, (q31_t)0x57228957, (q31_t)0xa23ca95f, + (q31_t)0x571deefa, (q31_t)0xa2386284, (q31_t)0x57195466, (q31_t)0xa2341be3, (q31_t)0x5714b99d, (q31_t)0xa22fd57b, (q31_t)0x57101e9e, (q31_t)0xa22b8f4d, + (q31_t)0x570b8369, (q31_t)0xa2274959, (q31_t)0x5706e7ff, (q31_t)0xa223039f, (q31_t)0x57024c5f, (q31_t)0xa21ebe1f, (q31_t)0x56fdb08a, (q31_t)0xa21a78d9, + (q31_t)0x56f9147e, (q31_t)0xa21633cd, (q31_t)0x56f4783d, (q31_t)0xa211eefb, (q31_t)0x56efdbc7, (q31_t)0xa20daa62, (q31_t)0x56eb3f1a, (q31_t)0xa2096604, + (q31_t)0x56e6a239, (q31_t)0xa20521e0, (q31_t)0x56e20521, (q31_t)0xa200ddf5, (q31_t)0x56dd67d4, (q31_t)0xa1fc9a45, (q31_t)0x56d8ca51, (q31_t)0xa1f856ce, + (q31_t)0x56d42c99, (q31_t)0xa1f41392, (q31_t)0x56cf8eab, (q31_t)0xa1efd08f, (q31_t)0x56caf088, (q31_t)0xa1eb8dc7, (q31_t)0x56c6522f, (q31_t)0xa1e74b38, + (q31_t)0x56c1b3a1, (q31_t)0xa1e308e4, (q31_t)0x56bd14dd, (q31_t)0xa1dec6ca, (q31_t)0x56b875e4, (q31_t)0xa1da84e9, (q31_t)0x56b3d6b5, (q31_t)0xa1d64343, + (q31_t)0x56af3750, (q31_t)0xa1d201d7, (q31_t)0x56aa97b7, (q31_t)0xa1cdc0a5, (q31_t)0x56a5f7e7, (q31_t)0xa1c97fad, (q31_t)0x56a157e3, (q31_t)0xa1c53ef0, + (q31_t)0x569cb7a8, (q31_t)0xa1c0fe6c, (q31_t)0x56981739, (q31_t)0xa1bcbe22, (q31_t)0x56937694, (q31_t)0xa1b87e13, (q31_t)0x568ed5b9, (q31_t)0xa1b43e3e, + (q31_t)0x568a34a9, (q31_t)0xa1affea3, (q31_t)0x56859364, (q31_t)0xa1abbf42, (q31_t)0x5680f1ea, (q31_t)0xa1a7801b, (q31_t)0x567c503a, (q31_t)0xa1a3412f, + (q31_t)0x5677ae54, (q31_t)0xa19f027c, (q31_t)0x56730c3a, (q31_t)0xa19ac404, (q31_t)0x566e69ea, (q31_t)0xa19685c7, (q31_t)0x5669c765, (q31_t)0xa19247c3, + (q31_t)0x566524aa, (q31_t)0xa18e09fa, (q31_t)0x566081ba, (q31_t)0xa189cc6b, (q31_t)0x565bde95, (q31_t)0xa1858f16, (q31_t)0x56573b3b, (q31_t)0xa18151fb, + (q31_t)0x565297ab, (q31_t)0xa17d151b, (q31_t)0x564df3e6, (q31_t)0xa178d875, (q31_t)0x56494fec, (q31_t)0xa1749c09, (q31_t)0x5644abbc, (q31_t)0xa1705fd8, + (q31_t)0x56400758, (q31_t)0xa16c23e1, (q31_t)0x563b62be, (q31_t)0xa167e824, (q31_t)0x5636bdef, (q31_t)0xa163aca2, (q31_t)0x563218eb, (q31_t)0xa15f715a, + (q31_t)0x562d73b2, (q31_t)0xa15b364d, (q31_t)0x5628ce43, (q31_t)0xa156fb79, (q31_t)0x5624289f, (q31_t)0xa152c0e1, (q31_t)0x561f82c7, (q31_t)0xa14e8682, + (q31_t)0x561adcb9, (q31_t)0xa14a4c5e, (q31_t)0x56163676, (q31_t)0xa1461275, (q31_t)0x56118ffe, (q31_t)0xa141d8c5, (q31_t)0x560ce950, (q31_t)0xa13d9f51, + (q31_t)0x5608426e, (q31_t)0xa1396617, (q31_t)0x56039b57, (q31_t)0xa1352d17, (q31_t)0x55fef40a, (q31_t)0xa130f451, (q31_t)0x55fa4c89, (q31_t)0xa12cbbc7, + (q31_t)0x55f5a4d2, (q31_t)0xa1288376, (q31_t)0x55f0fce7, (q31_t)0xa1244b61, (q31_t)0x55ec54c6, (q31_t)0xa1201385, (q31_t)0x55e7ac71, (q31_t)0xa11bdbe4, + (q31_t)0x55e303e6, (q31_t)0xa117a47e, (q31_t)0x55de5b27, (q31_t)0xa1136d52, (q31_t)0x55d9b232, (q31_t)0xa10f3661, (q31_t)0x55d50909, (q31_t)0xa10affab, + (q31_t)0x55d05faa, (q31_t)0xa106c92f, (q31_t)0x55cbb617, (q31_t)0xa10292ed, (q31_t)0x55c70c4f, (q31_t)0xa0fe5ce6, (q31_t)0x55c26251, (q31_t)0xa0fa271a, + (q31_t)0x55bdb81f, (q31_t)0xa0f5f189, (q31_t)0x55b90db8, (q31_t)0xa0f1bc32, (q31_t)0x55b4631d, (q31_t)0xa0ed8715, (q31_t)0x55afb84c, (q31_t)0xa0e95234, + (q31_t)0x55ab0d46, (q31_t)0xa0e51d8c, (q31_t)0x55a6620c, (q31_t)0xa0e0e920, (q31_t)0x55a1b69d, (q31_t)0xa0dcb4ee, (q31_t)0x559d0af9, (q31_t)0xa0d880f7, + (q31_t)0x55985f20, (q31_t)0xa0d44d3b, (q31_t)0x5593b312, (q31_t)0xa0d019b9, (q31_t)0x558f06d0, (q31_t)0xa0cbe672, (q31_t)0x558a5a58, (q31_t)0xa0c7b366, + (q31_t)0x5585adad, (q31_t)0xa0c38095, (q31_t)0x558100cc, (q31_t)0xa0bf4dfe, (q31_t)0x557c53b6, (q31_t)0xa0bb1ba2, (q31_t)0x5577a66c, (q31_t)0xa0b6e981, + (q31_t)0x5572f8ed, (q31_t)0xa0b2b79b, (q31_t)0x556e4b39, (q31_t)0xa0ae85ef, (q31_t)0x55699d51, (q31_t)0xa0aa547e, (q31_t)0x5564ef34, (q31_t)0xa0a62348, + (q31_t)0x556040e2, (q31_t)0xa0a1f24d, (q31_t)0x555b925c, (q31_t)0xa09dc18d, (q31_t)0x5556e3a1, (q31_t)0xa0999107, (q31_t)0x555234b1, (q31_t)0xa09560bc, + (q31_t)0x554d858d, (q31_t)0xa09130ad, (q31_t)0x5548d634, (q31_t)0xa08d00d8, (q31_t)0x554426a7, (q31_t)0xa088d13e, (q31_t)0x553f76e4, (q31_t)0xa084a1de, + (q31_t)0x553ac6ee, (q31_t)0xa08072ba, (q31_t)0x553616c2, (q31_t)0xa07c43d1, (q31_t)0x55316663, (q31_t)0xa0781522, (q31_t)0x552cb5ce, (q31_t)0xa073e6af, + (q31_t)0x55280505, (q31_t)0xa06fb876, (q31_t)0x55235408, (q31_t)0xa06b8a78, (q31_t)0x551ea2d6, (q31_t)0xa0675cb6, (q31_t)0x5519f16f, (q31_t)0xa0632f2e, + (q31_t)0x55153fd4, (q31_t)0xa05f01e1, (q31_t)0x55108e05, (q31_t)0xa05ad4cf, (q31_t)0x550bdc01, (q31_t)0xa056a7f9, (q31_t)0x550729c9, (q31_t)0xa0527b5d, + (q31_t)0x5502775c, (q31_t)0xa04e4efc, (q31_t)0x54fdc4ba, (q31_t)0xa04a22d7, (q31_t)0x54f911e5, (q31_t)0xa045f6ec, (q31_t)0x54f45edb, (q31_t)0xa041cb3c, + (q31_t)0x54efab9c, (q31_t)0xa03d9fc8, (q31_t)0x54eaf829, (q31_t)0xa039748e, (q31_t)0x54e64482, (q31_t)0xa0354990, (q31_t)0x54e190a6, (q31_t)0xa0311ecd, + (q31_t)0x54dcdc96, (q31_t)0xa02cf444, (q31_t)0x54d82852, (q31_t)0xa028c9f7, (q31_t)0x54d373d9, (q31_t)0xa0249fe5, (q31_t)0x54cebf2c, (q31_t)0xa020760e, + (q31_t)0x54ca0a4b, (q31_t)0xa01c4c73, (q31_t)0x54c55535, (q31_t)0xa0182312, (q31_t)0x54c09feb, (q31_t)0xa013f9ed, (q31_t)0x54bbea6d, (q31_t)0xa00fd102, + (q31_t)0x54b734ba, (q31_t)0xa00ba853, (q31_t)0x54b27ed3, (q31_t)0xa0077fdf, (q31_t)0x54adc8b8, (q31_t)0xa00357a7, (q31_t)0x54a91269, (q31_t)0x9fff2fa9, + (q31_t)0x54a45be6, (q31_t)0x9ffb07e7, (q31_t)0x549fa52e, (q31_t)0x9ff6e060, (q31_t)0x549aee42, (q31_t)0x9ff2b914, (q31_t)0x54963722, (q31_t)0x9fee9204, + (q31_t)0x54917fce, (q31_t)0x9fea6b2f, (q31_t)0x548cc845, (q31_t)0x9fe64495, (q31_t)0x54881089, (q31_t)0x9fe21e36, (q31_t)0x54835898, (q31_t)0x9fddf812, + (q31_t)0x547ea073, (q31_t)0x9fd9d22a, (q31_t)0x5479e81a, (q31_t)0x9fd5ac7d, (q31_t)0x54752f8d, (q31_t)0x9fd1870c, (q31_t)0x547076cc, (q31_t)0x9fcd61d6, + (q31_t)0x546bbdd7, (q31_t)0x9fc93cdb, (q31_t)0x546704ae, (q31_t)0x9fc5181b, (q31_t)0x54624b50, (q31_t)0x9fc0f397, (q31_t)0x545d91bf, (q31_t)0x9fbccf4f, + (q31_t)0x5458d7f9, (q31_t)0x9fb8ab41, (q31_t)0x54541e00, (q31_t)0x9fb4876f, (q31_t)0x544f63d2, (q31_t)0x9fb063d9, (q31_t)0x544aa971, (q31_t)0x9fac407e, + (q31_t)0x5445eedb, (q31_t)0x9fa81d5e, (q31_t)0x54413412, (q31_t)0x9fa3fa79, (q31_t)0x543c7914, (q31_t)0x9f9fd7d1, (q31_t)0x5437bde3, (q31_t)0x9f9bb563, + (q31_t)0x5433027d, (q31_t)0x9f979331, (q31_t)0x542e46e4, (q31_t)0x9f93713b, (q31_t)0x54298b17, (q31_t)0x9f8f4f80, (q31_t)0x5424cf16, (q31_t)0x9f8b2e00, + (q31_t)0x542012e1, (q31_t)0x9f870cbc, (q31_t)0x541b5678, (q31_t)0x9f82ebb4, (q31_t)0x541699db, (q31_t)0x9f7ecae7, (q31_t)0x5411dd0a, (q31_t)0x9f7aaa55, + (q31_t)0x540d2005, (q31_t)0x9f7689ff, (q31_t)0x540862cd, (q31_t)0x9f7269e5, (q31_t)0x5403a561, (q31_t)0x9f6e4a06, (q31_t)0x53fee7c1, (q31_t)0x9f6a2a63, + (q31_t)0x53fa29ed, (q31_t)0x9f660afb, (q31_t)0x53f56be5, (q31_t)0x9f61ebcf, (q31_t)0x53f0adaa, (q31_t)0x9f5dccde, (q31_t)0x53ebef3a, (q31_t)0x9f59ae29, + (q31_t)0x53e73097, (q31_t)0x9f558fb0, (q31_t)0x53e271c0, (q31_t)0x9f517173, (q31_t)0x53ddb2b6, (q31_t)0x9f4d5371, (q31_t)0x53d8f378, (q31_t)0x9f4935aa, + (q31_t)0x53d43406, (q31_t)0x9f45181f, (q31_t)0x53cf7460, (q31_t)0x9f40fad0, (q31_t)0x53cab486, (q31_t)0x9f3cddbd, (q31_t)0x53c5f479, (q31_t)0x9f38c0e5, + (q31_t)0x53c13439, (q31_t)0x9f34a449, (q31_t)0x53bc73c4, (q31_t)0x9f3087e9, (q31_t)0x53b7b31c, (q31_t)0x9f2c6bc5, (q31_t)0x53b2f240, (q31_t)0x9f284fdc, + (q31_t)0x53ae3131, (q31_t)0x9f24342f, (q31_t)0x53a96fee, (q31_t)0x9f2018bd, (q31_t)0x53a4ae77, (q31_t)0x9f1bfd88, (q31_t)0x539feccd, (q31_t)0x9f17e28e, + (q31_t)0x539b2af0, (q31_t)0x9f13c7d0, (q31_t)0x539668de, (q31_t)0x9f0fad4e, (q31_t)0x5391a699, (q31_t)0x9f0b9307, (q31_t)0x538ce421, (q31_t)0x9f0778fd, + (q31_t)0x53882175, (q31_t)0x9f035f2e, (q31_t)0x53835e95, (q31_t)0x9eff459b, (q31_t)0x537e9b82, (q31_t)0x9efb2c44, (q31_t)0x5379d83c, (q31_t)0x9ef71328, + (q31_t)0x537514c2, (q31_t)0x9ef2fa49, (q31_t)0x53705114, (q31_t)0x9eeee1a5, (q31_t)0x536b8d33, (q31_t)0x9eeac93e, (q31_t)0x5366c91f, (q31_t)0x9ee6b112, + (q31_t)0x536204d7, (q31_t)0x9ee29922, (q31_t)0x535d405c, (q31_t)0x9ede816e, (q31_t)0x53587bad, (q31_t)0x9eda69f6, (q31_t)0x5353b6cb, (q31_t)0x9ed652ba, + (q31_t)0x534ef1b5, (q31_t)0x9ed23bb9, (q31_t)0x534a2c6c, (q31_t)0x9ece24f5, (q31_t)0x534566f0, (q31_t)0x9eca0e6d, (q31_t)0x5340a140, (q31_t)0x9ec5f820, + (q31_t)0x533bdb5d, (q31_t)0x9ec1e210, (q31_t)0x53371547, (q31_t)0x9ebdcc3b, (q31_t)0x53324efd, (q31_t)0x9eb9b6a3, (q31_t)0x532d8880, (q31_t)0x9eb5a146, + (q31_t)0x5328c1d0, (q31_t)0x9eb18c26, (q31_t)0x5323faec, (q31_t)0x9ead7742, (q31_t)0x531f33d5, (q31_t)0x9ea96299, (q31_t)0x531a6c8b, (q31_t)0x9ea54e2d, + (q31_t)0x5315a50e, (q31_t)0x9ea139fd, (q31_t)0x5310dd5d, (q31_t)0x9e9d2608, (q31_t)0x530c1579, (q31_t)0x9e991250, (q31_t)0x53074d62, (q31_t)0x9e94fed4, + (q31_t)0x53028518, (q31_t)0x9e90eb94, (q31_t)0x52fdbc9a, (q31_t)0x9e8cd890, (q31_t)0x52f8f3e9, (q31_t)0x9e88c5c9, (q31_t)0x52f42b05, (q31_t)0x9e84b33d, + (q31_t)0x52ef61ee, (q31_t)0x9e80a0ee, (q31_t)0x52ea98a4, (q31_t)0x9e7c8eda, (q31_t)0x52e5cf27, (q31_t)0x9e787d03, (q31_t)0x52e10576, (q31_t)0x9e746b68, + (q31_t)0x52dc3b92, (q31_t)0x9e705a09, (q31_t)0x52d7717b, (q31_t)0x9e6c48e7, (q31_t)0x52d2a732, (q31_t)0x9e683800, (q31_t)0x52cddcb5, (q31_t)0x9e642756, + (q31_t)0x52c91204, (q31_t)0x9e6016e8, (q31_t)0x52c44721, (q31_t)0x9e5c06b6, (q31_t)0x52bf7c0b, (q31_t)0x9e57f6c0, (q31_t)0x52bab0c2, (q31_t)0x9e53e707, + (q31_t)0x52b5e546, (q31_t)0x9e4fd78a, (q31_t)0x52b11996, (q31_t)0x9e4bc849, (q31_t)0x52ac4db4, (q31_t)0x9e47b944, (q31_t)0x52a7819f, (q31_t)0x9e43aa7c, + (q31_t)0x52a2b556, (q31_t)0x9e3f9bf0, (q31_t)0x529de8db, (q31_t)0x9e3b8da0, (q31_t)0x52991c2d, (q31_t)0x9e377f8c, (q31_t)0x52944f4c, (q31_t)0x9e3371b5, + (q31_t)0x528f8238, (q31_t)0x9e2f641b, (q31_t)0x528ab4f1, (q31_t)0x9e2b56bc, (q31_t)0x5285e777, (q31_t)0x9e27499a, (q31_t)0x528119ca, (q31_t)0x9e233cb4, + (q31_t)0x527c4bea, (q31_t)0x9e1f300b, (q31_t)0x52777dd7, (q31_t)0x9e1b239e, (q31_t)0x5272af92, (q31_t)0x9e17176d, (q31_t)0x526de11a, (q31_t)0x9e130b79, + (q31_t)0x5269126e, (q31_t)0x9e0effc1, (q31_t)0x52644390, (q31_t)0x9e0af446, (q31_t)0x525f7480, (q31_t)0x9e06e907, (q31_t)0x525aa53c, (q31_t)0x9e02de04, + (q31_t)0x5255d5c5, (q31_t)0x9dfed33e, (q31_t)0x5251061c, (q31_t)0x9dfac8b4, (q31_t)0x524c3640, (q31_t)0x9df6be67, (q31_t)0x52476631, (q31_t)0x9df2b456, + (q31_t)0x524295f0, (q31_t)0x9deeaa82, (q31_t)0x523dc57b, (q31_t)0x9deaa0ea, (q31_t)0x5238f4d4, (q31_t)0x9de6978f, (q31_t)0x523423fb, (q31_t)0x9de28e70, + (q31_t)0x522f52ee, (q31_t)0x9dde858e, (q31_t)0x522a81af, (q31_t)0x9dda7ce9, (q31_t)0x5225b03d, (q31_t)0x9dd6747f, (q31_t)0x5220de99, (q31_t)0x9dd26c53, + (q31_t)0x521c0cc2, (q31_t)0x9dce6463, (q31_t)0x52173ab8, (q31_t)0x9dca5caf, (q31_t)0x5212687b, (q31_t)0x9dc65539, (q31_t)0x520d960c, (q31_t)0x9dc24dfe, + (q31_t)0x5208c36a, (q31_t)0x9dbe4701, (q31_t)0x5203f096, (q31_t)0x9dba4040, (q31_t)0x51ff1d8f, (q31_t)0x9db639bb, (q31_t)0x51fa4a56, (q31_t)0x9db23373, + (q31_t)0x51f576ea, (q31_t)0x9dae2d68, (q31_t)0x51f0a34b, (q31_t)0x9daa279a, (q31_t)0x51ebcf7a, (q31_t)0x9da62208, (q31_t)0x51e6fb76, (q31_t)0x9da21cb2, + (q31_t)0x51e22740, (q31_t)0x9d9e179a, (q31_t)0x51dd52d7, (q31_t)0x9d9a12be, (q31_t)0x51d87e3c, (q31_t)0x9d960e1f, (q31_t)0x51d3a96f, (q31_t)0x9d9209bd, + (q31_t)0x51ced46e, (q31_t)0x9d8e0597, (q31_t)0x51c9ff3c, (q31_t)0x9d8a01ae, (q31_t)0x51c529d7, (q31_t)0x9d85fe02, (q31_t)0x51c0543f, (q31_t)0x9d81fa92, + (q31_t)0x51bb7e75, (q31_t)0x9d7df75f, (q31_t)0x51b6a879, (q31_t)0x9d79f469, (q31_t)0x51b1d24a, (q31_t)0x9d75f1b0, (q31_t)0x51acfbe9, (q31_t)0x9d71ef34, + (q31_t)0x51a82555, (q31_t)0x9d6decf4, (q31_t)0x51a34e8f, (q31_t)0x9d69eaf1, (q31_t)0x519e7797, (q31_t)0x9d65e92b, (q31_t)0x5199a06d, (q31_t)0x9d61e7a2, + (q31_t)0x5194c910, (q31_t)0x9d5de656, (q31_t)0x518ff180, (q31_t)0x9d59e546, (q31_t)0x518b19bf, (q31_t)0x9d55e473, (q31_t)0x518641cb, (q31_t)0x9d51e3dd, + (q31_t)0x518169a5, (q31_t)0x9d4de385, (q31_t)0x517c914c, (q31_t)0x9d49e368, (q31_t)0x5177b8c2, (q31_t)0x9d45e389, (q31_t)0x5172e005, (q31_t)0x9d41e3e7, + (q31_t)0x516e0715, (q31_t)0x9d3de482, (q31_t)0x51692df4, (q31_t)0x9d39e559, (q31_t)0x516454a0, (q31_t)0x9d35e66e, (q31_t)0x515f7b1a, (q31_t)0x9d31e7bf, + (q31_t)0x515aa162, (q31_t)0x9d2de94d, (q31_t)0x5155c778, (q31_t)0x9d29eb19, (q31_t)0x5150ed5c, (q31_t)0x9d25ed21, (q31_t)0x514c130d, (q31_t)0x9d21ef66, + (q31_t)0x5147388c, (q31_t)0x9d1df1e9, (q31_t)0x51425dd9, (q31_t)0x9d19f4a8, (q31_t)0x513d82f4, (q31_t)0x9d15f7a4, (q31_t)0x5138a7dd, (q31_t)0x9d11fadd, + (q31_t)0x5133cc94, (q31_t)0x9d0dfe54, (q31_t)0x512ef119, (q31_t)0x9d0a0207, (q31_t)0x512a156b, (q31_t)0x9d0605f7, (q31_t)0x5125398c, (q31_t)0x9d020a25, + (q31_t)0x51205d7b, (q31_t)0x9cfe0e8f, (q31_t)0x511b8137, (q31_t)0x9cfa1337, (q31_t)0x5116a4c1, (q31_t)0x9cf6181c, (q31_t)0x5111c81a, (q31_t)0x9cf21d3d, + (q31_t)0x510ceb40, (q31_t)0x9cee229c, (q31_t)0x51080e35, (q31_t)0x9cea2838, (q31_t)0x510330f7, (q31_t)0x9ce62e11, (q31_t)0x50fe5388, (q31_t)0x9ce23427, + (q31_t)0x50f975e6, (q31_t)0x9cde3a7b, (q31_t)0x50f49813, (q31_t)0x9cda410b, (q31_t)0x50efba0d, (q31_t)0x9cd647d9, (q31_t)0x50eadbd6, (q31_t)0x9cd24ee4, + (q31_t)0x50e5fd6d, (q31_t)0x9cce562c, (q31_t)0x50e11ed2, (q31_t)0x9cca5db1, (q31_t)0x50dc4005, (q31_t)0x9cc66573, (q31_t)0x50d76106, (q31_t)0x9cc26d73, + (q31_t)0x50d281d5, (q31_t)0x9cbe75b0, (q31_t)0x50cda272, (q31_t)0x9cba7e2a, (q31_t)0x50c8c2de, (q31_t)0x9cb686e1, (q31_t)0x50c3e317, (q31_t)0x9cb28fd5, + (q31_t)0x50bf031f, (q31_t)0x9cae9907, (q31_t)0x50ba22f5, (q31_t)0x9caaa276, (q31_t)0x50b5429a, (q31_t)0x9ca6ac23, (q31_t)0x50b0620c, (q31_t)0x9ca2b60c, + (q31_t)0x50ab814d, (q31_t)0x9c9ec033, (q31_t)0x50a6a05c, (q31_t)0x9c9aca97, (q31_t)0x50a1bf39, (q31_t)0x9c96d539, (q31_t)0x509cdde4, (q31_t)0x9c92e017, + (q31_t)0x5097fc5e, (q31_t)0x9c8eeb34, (q31_t)0x50931aa6, (q31_t)0x9c8af68d, (q31_t)0x508e38bd, (q31_t)0x9c870224, (q31_t)0x508956a1, (q31_t)0x9c830df8, + (q31_t)0x50847454, (q31_t)0x9c7f1a0a, (q31_t)0x507f91d5, (q31_t)0x9c7b2659, (q31_t)0x507aaf25, (q31_t)0x9c7732e5, (q31_t)0x5075cc43, (q31_t)0x9c733faf, + (q31_t)0x5070e92f, (q31_t)0x9c6f4cb6, (q31_t)0x506c05ea, (q31_t)0x9c6b59fa, (q31_t)0x50672273, (q31_t)0x9c67677c, (q31_t)0x50623ecb, (q31_t)0x9c63753c, + (q31_t)0x505d5af1, (q31_t)0x9c5f8339, (q31_t)0x505876e5, (q31_t)0x9c5b9173, (q31_t)0x505392a8, (q31_t)0x9c579feb, (q31_t)0x504eae39, (q31_t)0x9c53aea0, + (q31_t)0x5049c999, (q31_t)0x9c4fbd93, (q31_t)0x5044e4c7, (q31_t)0x9c4bccc3, (q31_t)0x503fffc4, (q31_t)0x9c47dc31, (q31_t)0x503b1a8f, (q31_t)0x9c43ebdc, + (q31_t)0x50363529, (q31_t)0x9c3ffbc5, (q31_t)0x50314f91, (q31_t)0x9c3c0beb, (q31_t)0x502c69c8, (q31_t)0x9c381c4f, (q31_t)0x502783cd, (q31_t)0x9c342cf0, + (q31_t)0x50229da1, (q31_t)0x9c303dcf, (q31_t)0x501db743, (q31_t)0x9c2c4eec, (q31_t)0x5018d0b4, (q31_t)0x9c286046, (q31_t)0x5013e9f4, (q31_t)0x9c2471de, + (q31_t)0x500f0302, (q31_t)0x9c2083b3, (q31_t)0x500a1bdf, (q31_t)0x9c1c95c6, (q31_t)0x5005348a, (q31_t)0x9c18a816, (q31_t)0x50004d04, (q31_t)0x9c14baa4, + (q31_t)0x4ffb654d, (q31_t)0x9c10cd70, (q31_t)0x4ff67d64, (q31_t)0x9c0ce07a, (q31_t)0x4ff1954b, (q31_t)0x9c08f3c1, (q31_t)0x4fecacff, (q31_t)0x9c050745, + (q31_t)0x4fe7c483, (q31_t)0x9c011b08, (q31_t)0x4fe2dbd5, (q31_t)0x9bfd2f08, (q31_t)0x4fddf2f6, (q31_t)0x9bf94346, (q31_t)0x4fd909e5, (q31_t)0x9bf557c1, + (q31_t)0x4fd420a4, (q31_t)0x9bf16c7a, (q31_t)0x4fcf3731, (q31_t)0x9bed8171, (q31_t)0x4fca4d8d, (q31_t)0x9be996a6, (q31_t)0x4fc563b7, (q31_t)0x9be5ac18, + (q31_t)0x4fc079b1, (q31_t)0x9be1c1c8, (q31_t)0x4fbb8f79, (q31_t)0x9bddd7b6, (q31_t)0x4fb6a510, (q31_t)0x9bd9ede2, (q31_t)0x4fb1ba76, (q31_t)0x9bd6044b, + (q31_t)0x4faccfab, (q31_t)0x9bd21af3, (q31_t)0x4fa7e4af, (q31_t)0x9bce31d8, (q31_t)0x4fa2f981, (q31_t)0x9bca48fa, (q31_t)0x4f9e0e22, (q31_t)0x9bc6605b, + (q31_t)0x4f992293, (q31_t)0x9bc277fa, (q31_t)0x4f9436d2, (q31_t)0x9bbe8fd6, (q31_t)0x4f8f4ae0, (q31_t)0x9bbaa7f0, (q31_t)0x4f8a5ebd, (q31_t)0x9bb6c048, + (q31_t)0x4f857269, (q31_t)0x9bb2d8de, (q31_t)0x4f8085e4, (q31_t)0x9baef1b2, (q31_t)0x4f7b992d, (q31_t)0x9bab0ac3, (q31_t)0x4f76ac46, (q31_t)0x9ba72413, + (q31_t)0x4f71bf2e, (q31_t)0x9ba33da0, (q31_t)0x4f6cd1e5, (q31_t)0x9b9f576b, (q31_t)0x4f67e46a, (q31_t)0x9b9b7174, (q31_t)0x4f62f6bf, (q31_t)0x9b978bbc, + (q31_t)0x4f5e08e3, (q31_t)0x9b93a641, (q31_t)0x4f591ad6, (q31_t)0x9b8fc104, (q31_t)0x4f542c98, (q31_t)0x9b8bdc05, (q31_t)0x4f4f3e29, (q31_t)0x9b87f744, + (q31_t)0x4f4a4f89, (q31_t)0x9b8412c1, (q31_t)0x4f4560b8, (q31_t)0x9b802e7b, (q31_t)0x4f4071b6, (q31_t)0x9b7c4a74, (q31_t)0x4f3b8284, (q31_t)0x9b7866ab, + (q31_t)0x4f369320, (q31_t)0x9b748320, (q31_t)0x4f31a38c, (q31_t)0x9b709fd3, (q31_t)0x4f2cb3c7, (q31_t)0x9b6cbcc4, (q31_t)0x4f27c3d1, (q31_t)0x9b68d9f3, + (q31_t)0x4f22d3aa, (q31_t)0x9b64f760, (q31_t)0x4f1de352, (q31_t)0x9b61150b, (q31_t)0x4f18f2c9, (q31_t)0x9b5d32f4, (q31_t)0x4f140210, (q31_t)0x9b59511c, + (q31_t)0x4f0f1126, (q31_t)0x9b556f81, (q31_t)0x4f0a200b, (q31_t)0x9b518e24, (q31_t)0x4f052ec0, (q31_t)0x9b4dad06, (q31_t)0x4f003d43, (q31_t)0x9b49cc26, + (q31_t)0x4efb4b96, (q31_t)0x9b45eb83, (q31_t)0x4ef659b8, (q31_t)0x9b420b1f, (q31_t)0x4ef167aa, (q31_t)0x9b3e2af9, (q31_t)0x4eec756b, (q31_t)0x9b3a4b11, + (q31_t)0x4ee782fb, (q31_t)0x9b366b68, (q31_t)0x4ee2905a, (q31_t)0x9b328bfc, (q31_t)0x4edd9d89, (q31_t)0x9b2eaccf, (q31_t)0x4ed8aa87, (q31_t)0x9b2acde0, + (q31_t)0x4ed3b755, (q31_t)0x9b26ef2f, (q31_t)0x4ecec3f2, (q31_t)0x9b2310bc, (q31_t)0x4ec9d05e, (q31_t)0x9b1f3288, (q31_t)0x4ec4dc99, (q31_t)0x9b1b5492, + (q31_t)0x4ebfe8a5, (q31_t)0x9b1776da, (q31_t)0x4ebaf47f, (q31_t)0x9b139960, (q31_t)0x4eb60029, (q31_t)0x9b0fbc24, (q31_t)0x4eb10ba2, (q31_t)0x9b0bdf27, + (q31_t)0x4eac16eb, (q31_t)0x9b080268, (q31_t)0x4ea72203, (q31_t)0x9b0425e8, (q31_t)0x4ea22ceb, (q31_t)0x9b0049a5, (q31_t)0x4e9d37a3, (q31_t)0x9afc6da1, + (q31_t)0x4e984229, (q31_t)0x9af891db, (q31_t)0x4e934c80, (q31_t)0x9af4b654, (q31_t)0x4e8e56a5, (q31_t)0x9af0db0b, (q31_t)0x4e89609b, (q31_t)0x9aed0000, + (q31_t)0x4e846a60, (q31_t)0x9ae92533, (q31_t)0x4e7f73f4, (q31_t)0x9ae54aa5, (q31_t)0x4e7a7d58, (q31_t)0x9ae17056, (q31_t)0x4e75868c, (q31_t)0x9add9644, + (q31_t)0x4e708f8f, (q31_t)0x9ad9bc71, (q31_t)0x4e6b9862, (q31_t)0x9ad5e2dd, (q31_t)0x4e66a105, (q31_t)0x9ad20987, (q31_t)0x4e61a977, (q31_t)0x9ace306f, + (q31_t)0x4e5cb1b9, (q31_t)0x9aca5795, (q31_t)0x4e57b9ca, (q31_t)0x9ac67efb, (q31_t)0x4e52c1ab, (q31_t)0x9ac2a69e, (q31_t)0x4e4dc95c, (q31_t)0x9abece80, + (q31_t)0x4e48d0dd, (q31_t)0x9abaf6a1, (q31_t)0x4e43d82d, (q31_t)0x9ab71eff, (q31_t)0x4e3edf4d, (q31_t)0x9ab3479d, (q31_t)0x4e39e63d, (q31_t)0x9aaf7079, + (q31_t)0x4e34ecfc, (q31_t)0x9aab9993, (q31_t)0x4e2ff38b, (q31_t)0x9aa7c2ec, (q31_t)0x4e2af9ea, (q31_t)0x9aa3ec83, (q31_t)0x4e260019, (q31_t)0x9aa01659, + (q31_t)0x4e210617, (q31_t)0x9a9c406e, (q31_t)0x4e1c0be6, (q31_t)0x9a986ac1, (q31_t)0x4e171184, (q31_t)0x9a949552, (q31_t)0x4e1216f2, (q31_t)0x9a90c022, + (q31_t)0x4e0d1c30, (q31_t)0x9a8ceb31, (q31_t)0x4e08213e, (q31_t)0x9a89167e, (q31_t)0x4e03261b, (q31_t)0x9a85420a, (q31_t)0x4dfe2ac9, (q31_t)0x9a816dd5, + (q31_t)0x4df92f46, (q31_t)0x9a7d99de, (q31_t)0x4df43393, (q31_t)0x9a79c625, (q31_t)0x4def37b0, (q31_t)0x9a75f2ac, (q31_t)0x4dea3b9d, (q31_t)0x9a721f71, + (q31_t)0x4de53f5a, (q31_t)0x9a6e4c74, (q31_t)0x4de042e7, (q31_t)0x9a6a79b6, (q31_t)0x4ddb4644, (q31_t)0x9a66a737, (q31_t)0x4dd64971, (q31_t)0x9a62d4f7, + (q31_t)0x4dd14c6e, (q31_t)0x9a5f02f5, (q31_t)0x4dcc4f3b, (q31_t)0x9a5b3132, (q31_t)0x4dc751d8, (q31_t)0x9a575fae, (q31_t)0x4dc25445, (q31_t)0x9a538e68, + (q31_t)0x4dbd5682, (q31_t)0x9a4fbd61, (q31_t)0x4db8588f, (q31_t)0x9a4bec99, (q31_t)0x4db35a6c, (q31_t)0x9a481c0f, (q31_t)0x4dae5c19, (q31_t)0x9a444bc5, + (q31_t)0x4da95d96, (q31_t)0x9a407bb9, (q31_t)0x4da45ee3, (q31_t)0x9a3cabeb, (q31_t)0x4d9f6001, (q31_t)0x9a38dc5d, (q31_t)0x4d9a60ee, (q31_t)0x9a350d0d, + (q31_t)0x4d9561ac, (q31_t)0x9a313dfc, (q31_t)0x4d90623a, (q31_t)0x9a2d6f2a, (q31_t)0x4d8b6298, (q31_t)0x9a29a097, (q31_t)0x4d8662c6, (q31_t)0x9a25d243, + (q31_t)0x4d8162c4, (q31_t)0x9a22042d, (q31_t)0x4d7c6293, (q31_t)0x9a1e3656, (q31_t)0x4d776231, (q31_t)0x9a1a68be, (q31_t)0x4d7261a0, (q31_t)0x9a169b65, + (q31_t)0x4d6d60df, (q31_t)0x9a12ce4b, (q31_t)0x4d685fef, (q31_t)0x9a0f016f, (q31_t)0x4d635ece, (q31_t)0x9a0b34d3, (q31_t)0x4d5e5d7e, (q31_t)0x9a076875, + (q31_t)0x4d595bfe, (q31_t)0x9a039c57, (q31_t)0x4d545a4f, (q31_t)0x99ffd077, (q31_t)0x4d4f5870, (q31_t)0x99fc04d6, (q31_t)0x4d4a5661, (q31_t)0x99f83974, + (q31_t)0x4d455422, (q31_t)0x99f46e51, (q31_t)0x4d4051b4, (q31_t)0x99f0a36d, (q31_t)0x4d3b4f16, (q31_t)0x99ecd8c8, (q31_t)0x4d364c48, (q31_t)0x99e90e62, + (q31_t)0x4d31494b, (q31_t)0x99e5443b, (q31_t)0x4d2c461e, (q31_t)0x99e17a53, (q31_t)0x4d2742c2, (q31_t)0x99ddb0aa, (q31_t)0x4d223f36, (q31_t)0x99d9e73f, + (q31_t)0x4d1d3b7a, (q31_t)0x99d61e14, (q31_t)0x4d18378f, (q31_t)0x99d25528, (q31_t)0x4d133374, (q31_t)0x99ce8c7b, (q31_t)0x4d0e2f2a, (q31_t)0x99cac40d, + (q31_t)0x4d092ab0, (q31_t)0x99c6fbde, (q31_t)0x4d042607, (q31_t)0x99c333ee, (q31_t)0x4cff212e, (q31_t)0x99bf6c3d, (q31_t)0x4cfa1c26, (q31_t)0x99bba4cb, + (q31_t)0x4cf516ee, (q31_t)0x99b7dd99, (q31_t)0x4cf01187, (q31_t)0x99b416a5, (q31_t)0x4ceb0bf0, (q31_t)0x99b04ff0, (q31_t)0x4ce6062a, (q31_t)0x99ac897b, + (q31_t)0x4ce10034, (q31_t)0x99a8c345, (q31_t)0x4cdbfa0f, (q31_t)0x99a4fd4d, (q31_t)0x4cd6f3bb, (q31_t)0x99a13795, (q31_t)0x4cd1ed37, (q31_t)0x999d721c, + (q31_t)0x4ccce684, (q31_t)0x9999ace3, (q31_t)0x4cc7dfa1, (q31_t)0x9995e7e8, (q31_t)0x4cc2d88f, (q31_t)0x9992232d, (q31_t)0x4cbdd14e, (q31_t)0x998e5eb1, + (q31_t)0x4cb8c9dd, (q31_t)0x998a9a74, (q31_t)0x4cb3c23d, (q31_t)0x9986d676, (q31_t)0x4caeba6e, (q31_t)0x998312b7, (q31_t)0x4ca9b26f, (q31_t)0x997f4f38, + (q31_t)0x4ca4aa41, (q31_t)0x997b8bf8, (q31_t)0x4c9fa1e4, (q31_t)0x9977c8f7, (q31_t)0x4c9a9958, (q31_t)0x99740635, (q31_t)0x4c95909c, (q31_t)0x997043b2, + (q31_t)0x4c9087b1, (q31_t)0x996c816f, (q31_t)0x4c8b7e97, (q31_t)0x9968bf6b, (q31_t)0x4c86754e, (q31_t)0x9964fda7, (q31_t)0x4c816bd5, (q31_t)0x99613c22, + (q31_t)0x4c7c622d, (q31_t)0x995d7adc, (q31_t)0x4c775856, (q31_t)0x9959b9d5, (q31_t)0x4c724e50, (q31_t)0x9955f90d, (q31_t)0x4c6d441b, (q31_t)0x99523885, + (q31_t)0x4c6839b7, (q31_t)0x994e783d, (q31_t)0x4c632f23, (q31_t)0x994ab833, (q31_t)0x4c5e2460, (q31_t)0x9946f869, (q31_t)0x4c59196f, (q31_t)0x994338df, + (q31_t)0x4c540e4e, (q31_t)0x993f7993, (q31_t)0x4c4f02fe, (q31_t)0x993bba87, (q31_t)0x4c49f77f, (q31_t)0x9937fbbb, (q31_t)0x4c44ebd1, (q31_t)0x99343d2e, + (q31_t)0x4c3fdff4, (q31_t)0x99307ee0, (q31_t)0x4c3ad3e7, (q31_t)0x992cc0d2, (q31_t)0x4c35c7ac, (q31_t)0x99290303, (q31_t)0x4c30bb42, (q31_t)0x99254574, + (q31_t)0x4c2baea9, (q31_t)0x99218824, (q31_t)0x4c26a1e1, (q31_t)0x991dcb13, (q31_t)0x4c2194e9, (q31_t)0x991a0e42, (q31_t)0x4c1c87c3, (q31_t)0x991651b1, + (q31_t)0x4c177a6e, (q31_t)0x9912955f, (q31_t)0x4c126cea, (q31_t)0x990ed94c, (q31_t)0x4c0d5f37, (q31_t)0x990b1d79, (q31_t)0x4c085156, (q31_t)0x990761e5, + (q31_t)0x4c034345, (q31_t)0x9903a691, (q31_t)0x4bfe3505, (q31_t)0x98ffeb7d, (q31_t)0x4bf92697, (q31_t)0x98fc30a8, (q31_t)0x4bf417f9, (q31_t)0x98f87612, + (q31_t)0x4bef092d, (q31_t)0x98f4bbbc, (q31_t)0x4be9fa32, (q31_t)0x98f101a6, (q31_t)0x4be4eb08, (q31_t)0x98ed47cf, (q31_t)0x4bdfdbaf, (q31_t)0x98e98e38, + (q31_t)0x4bdacc28, (q31_t)0x98e5d4e0, (q31_t)0x4bd5bc72, (q31_t)0x98e21bc8, (q31_t)0x4bd0ac8d, (q31_t)0x98de62f0, (q31_t)0x4bcb9c79, (q31_t)0x98daaa57, + (q31_t)0x4bc68c36, (q31_t)0x98d6f1fe, (q31_t)0x4bc17bc5, (q31_t)0x98d339e4, (q31_t)0x4bbc6b25, (q31_t)0x98cf820b, (q31_t)0x4bb75a56, (q31_t)0x98cbca70, + (q31_t)0x4bb24958, (q31_t)0x98c81316, (q31_t)0x4bad382c, (q31_t)0x98c45bfb, (q31_t)0x4ba826d1, (q31_t)0x98c0a520, (q31_t)0x4ba31548, (q31_t)0x98bcee84, + (q31_t)0x4b9e0390, (q31_t)0x98b93828, (q31_t)0x4b98f1a9, (q31_t)0x98b5820c, (q31_t)0x4b93df93, (q31_t)0x98b1cc30, (q31_t)0x4b8ecd4f, (q31_t)0x98ae1693, + (q31_t)0x4b89badd, (q31_t)0x98aa6136, (q31_t)0x4b84a83b, (q31_t)0x98a6ac19, (q31_t)0x4b7f956b, (q31_t)0x98a2f73c, (q31_t)0x4b7a826d, (q31_t)0x989f429e, + (q31_t)0x4b756f40, (q31_t)0x989b8e40, (q31_t)0x4b705be4, (q31_t)0x9897da22, (q31_t)0x4b6b485a, (q31_t)0x98942643, (q31_t)0x4b6634a2, (q31_t)0x989072a5, + (q31_t)0x4b6120bb, (q31_t)0x988cbf46, (q31_t)0x4b5c0ca5, (q31_t)0x98890c27, (q31_t)0x4b56f861, (q31_t)0x98855948, (q31_t)0x4b51e3ee, (q31_t)0x9881a6a9, + (q31_t)0x4b4ccf4d, (q31_t)0x987df449, (q31_t)0x4b47ba7e, (q31_t)0x987a422a, (q31_t)0x4b42a580, (q31_t)0x9876904a, (q31_t)0x4b3d9053, (q31_t)0x9872deaa, + (q31_t)0x4b387af9, (q31_t)0x986f2d4a, (q31_t)0x4b336570, (q31_t)0x986b7c2a, (q31_t)0x4b2e4fb8, (q31_t)0x9867cb4a, (q31_t)0x4b2939d2, (q31_t)0x98641aa9, + (q31_t)0x4b2423be, (q31_t)0x98606a49, (q31_t)0x4b1f0d7b, (q31_t)0x985cba28, (q31_t)0x4b19f70a, (q31_t)0x98590a48, (q31_t)0x4b14e06b, (q31_t)0x98555aa7, + (q31_t)0x4b0fc99d, (q31_t)0x9851ab46, (q31_t)0x4b0ab2a1, (q31_t)0x984dfc26, (q31_t)0x4b059b77, (q31_t)0x984a4d45, (q31_t)0x4b00841f, (q31_t)0x98469ea4, + (q31_t)0x4afb6c98, (q31_t)0x9842f043, (q31_t)0x4af654e3, (q31_t)0x983f4223, (q31_t)0x4af13d00, (q31_t)0x983b9442, (q31_t)0x4aec24ee, (q31_t)0x9837e6a1, + (q31_t)0x4ae70caf, (q31_t)0x98343940, (q31_t)0x4ae1f441, (q31_t)0x98308c1f, (q31_t)0x4adcdba5, (q31_t)0x982cdf3f, (q31_t)0x4ad7c2da, (q31_t)0x9829329e, + (q31_t)0x4ad2a9e2, (q31_t)0x9825863d, (q31_t)0x4acd90bb, (q31_t)0x9821da1d, (q31_t)0x4ac87767, (q31_t)0x981e2e3c, (q31_t)0x4ac35de4, (q31_t)0x981a829c, + (q31_t)0x4abe4433, (q31_t)0x9816d73b, (q31_t)0x4ab92a54, (q31_t)0x98132c1b, (q31_t)0x4ab41046, (q31_t)0x980f813b, (q31_t)0x4aaef60b, (q31_t)0x980bd69b, + (q31_t)0x4aa9dba2, (q31_t)0x98082c3b, (q31_t)0x4aa4c10b, (q31_t)0x9804821b, (q31_t)0x4a9fa645, (q31_t)0x9800d83c, (q31_t)0x4a9a8b52, (q31_t)0x97fd2e9c, + (q31_t)0x4a957030, (q31_t)0x97f9853d, (q31_t)0x4a9054e1, (q31_t)0x97f5dc1e, (q31_t)0x4a8b3963, (q31_t)0x97f2333f, (q31_t)0x4a861db8, (q31_t)0x97ee8aa0, + (q31_t)0x4a8101de, (q31_t)0x97eae242, (q31_t)0x4a7be5d7, (q31_t)0x97e73a23, (q31_t)0x4a76c9a2, (q31_t)0x97e39245, (q31_t)0x4a71ad3e, (q31_t)0x97dfeaa7, + (q31_t)0x4a6c90ad, (q31_t)0x97dc4349, (q31_t)0x4a6773ee, (q31_t)0x97d89c2c, (q31_t)0x4a625701, (q31_t)0x97d4f54f, (q31_t)0x4a5d39e6, (q31_t)0x97d14eb2, + (q31_t)0x4a581c9e, (q31_t)0x97cda855, (q31_t)0x4a52ff27, (q31_t)0x97ca0239, (q31_t)0x4a4de182, (q31_t)0x97c65c5c, (q31_t)0x4a48c3b0, (q31_t)0x97c2b6c1, + (q31_t)0x4a43a5b0, (q31_t)0x97bf1165, (q31_t)0x4a3e8782, (q31_t)0x97bb6c4a, (q31_t)0x4a396926, (q31_t)0x97b7c76f, (q31_t)0x4a344a9d, (q31_t)0x97b422d4, + (q31_t)0x4a2f2be6, (q31_t)0x97b07e7a, (q31_t)0x4a2a0d01, (q31_t)0x97acda60, (q31_t)0x4a24edee, (q31_t)0x97a93687, (q31_t)0x4a1fcead, (q31_t)0x97a592ed, + (q31_t)0x4a1aaf3f, (q31_t)0x97a1ef94, (q31_t)0x4a158fa3, (q31_t)0x979e4c7c, (q31_t)0x4a106fda, (q31_t)0x979aa9a4, (q31_t)0x4a0b4fe2, (q31_t)0x9797070c, + (q31_t)0x4a062fbd, (q31_t)0x979364b5, (q31_t)0x4a010f6b, (q31_t)0x978fc29e, (q31_t)0x49fbeeea, (q31_t)0x978c20c8, (q31_t)0x49f6ce3c, (q31_t)0x97887f32, + (q31_t)0x49f1ad61, (q31_t)0x9784dddc, (q31_t)0x49ec8c57, (q31_t)0x97813cc7, (q31_t)0x49e76b21, (q31_t)0x977d9bf2, (q31_t)0x49e249bc, (q31_t)0x9779fb5e, + (q31_t)0x49dd282a, (q31_t)0x97765b0a, (q31_t)0x49d8066b, (q31_t)0x9772baf7, (q31_t)0x49d2e47e, (q31_t)0x976f1b24, (q31_t)0x49cdc263, (q31_t)0x976b7b92, + (q31_t)0x49c8a01b, (q31_t)0x9767dc41, (q31_t)0x49c37da5, (q31_t)0x97643d2f, (q31_t)0x49be5b02, (q31_t)0x97609e5f, (q31_t)0x49b93832, (q31_t)0x975cffcf, + (q31_t)0x49b41533, (q31_t)0x9759617f, (q31_t)0x49aef208, (q31_t)0x9755c370, (q31_t)0x49a9ceaf, (q31_t)0x975225a1, (q31_t)0x49a4ab28, (q31_t)0x974e8813, + (q31_t)0x499f8774, (q31_t)0x974aeac6, (q31_t)0x499a6393, (q31_t)0x97474db9, (q31_t)0x49953f84, (q31_t)0x9743b0ed, (q31_t)0x49901b48, (q31_t)0x97401462, + (q31_t)0x498af6df, (q31_t)0x973c7817, (q31_t)0x4985d248, (q31_t)0x9738dc0d, (q31_t)0x4980ad84, (q31_t)0x97354043, (q31_t)0x497b8892, (q31_t)0x9731a4ba, + (q31_t)0x49766373, (q31_t)0x972e0971, (q31_t)0x49713e27, (q31_t)0x972a6e6a, (q31_t)0x496c18ae, (q31_t)0x9726d3a3, (q31_t)0x4966f307, (q31_t)0x9723391c, + (q31_t)0x4961cd33, (q31_t)0x971f9ed7, (q31_t)0x495ca732, (q31_t)0x971c04d2, (q31_t)0x49578103, (q31_t)0x97186b0d, (q31_t)0x49525aa7, (q31_t)0x9714d18a, + (q31_t)0x494d341e, (q31_t)0x97113847, (q31_t)0x49480d68, (q31_t)0x970d9f45, (q31_t)0x4942e684, (q31_t)0x970a0683, (q31_t)0x493dbf74, (q31_t)0x97066e03, + (q31_t)0x49389836, (q31_t)0x9702d5c3, (q31_t)0x493370cb, (q31_t)0x96ff3dc4, (q31_t)0x492e4933, (q31_t)0x96fba605, (q31_t)0x4929216e, (q31_t)0x96f80e88, + (q31_t)0x4923f97b, (q31_t)0x96f4774b, (q31_t)0x491ed15c, (q31_t)0x96f0e04f, (q31_t)0x4919a90f, (q31_t)0x96ed4994, (q31_t)0x49148095, (q31_t)0x96e9b319, + (q31_t)0x490f57ee, (q31_t)0x96e61ce0, (q31_t)0x490a2f1b, (q31_t)0x96e286e7, (q31_t)0x4905061a, (q31_t)0x96def12f, (q31_t)0x48ffdcec, (q31_t)0x96db5bb8, + (q31_t)0x48fab391, (q31_t)0x96d7c682, (q31_t)0x48f58a09, (q31_t)0x96d4318d, (q31_t)0x48f06054, (q31_t)0x96d09cd8, (q31_t)0x48eb3672, (q31_t)0x96cd0865, + (q31_t)0x48e60c62, (q31_t)0x96c97432, (q31_t)0x48e0e227, (q31_t)0x96c5e040, (q31_t)0x48dbb7be, (q31_t)0x96c24c8f, (q31_t)0x48d68d28, (q31_t)0x96beb91f, + (q31_t)0x48d16265, (q31_t)0x96bb25f0, (q31_t)0x48cc3775, (q31_t)0x96b79302, (q31_t)0x48c70c59, (q31_t)0x96b40055, (q31_t)0x48c1e10f, (q31_t)0x96b06de9, + (q31_t)0x48bcb599, (q31_t)0x96acdbbe, (q31_t)0x48b789f5, (q31_t)0x96a949d3, (q31_t)0x48b25e25, (q31_t)0x96a5b82a, (q31_t)0x48ad3228, (q31_t)0x96a226c2, + (q31_t)0x48a805ff, (q31_t)0x969e959b, (q31_t)0x48a2d9a8, (q31_t)0x969b04b4, (q31_t)0x489dad25, (q31_t)0x9697740f, (q31_t)0x48988074, (q31_t)0x9693e3ab, + (q31_t)0x48935397, (q31_t)0x96905388, (q31_t)0x488e268e, (q31_t)0x968cc3a5, (q31_t)0x4888f957, (q31_t)0x96893404, (q31_t)0x4883cbf4, (q31_t)0x9685a4a4, + (q31_t)0x487e9e64, (q31_t)0x96821585, (q31_t)0x487970a7, (q31_t)0x967e86a7, (q31_t)0x487442be, (q31_t)0x967af80a, (q31_t)0x486f14a8, (q31_t)0x967769af, + (q31_t)0x4869e665, (q31_t)0x9673db94, (q31_t)0x4864b7f5, (q31_t)0x96704dba, (q31_t)0x485f8959, (q31_t)0x966cc022, (q31_t)0x485a5a90, (q31_t)0x966932cb, + (q31_t)0x48552b9b, (q31_t)0x9665a5b4, (q31_t)0x484ffc79, (q31_t)0x966218df, (q31_t)0x484acd2a, (q31_t)0x965e8c4b, (q31_t)0x48459daf, (q31_t)0x965afff9, + (q31_t)0x48406e08, (q31_t)0x965773e7, (q31_t)0x483b3e33, (q31_t)0x9653e817, (q31_t)0x48360e32, (q31_t)0x96505c88, (q31_t)0x4830de05, (q31_t)0x964cd139, + (q31_t)0x482badab, (q31_t)0x9649462d, (q31_t)0x48267d24, (q31_t)0x9645bb61, (q31_t)0x48214c71, (q31_t)0x964230d7, (q31_t)0x481c1b92, (q31_t)0x963ea68d, + (q31_t)0x4816ea86, (q31_t)0x963b1c86, (q31_t)0x4811b94d, (q31_t)0x963792bf, (q31_t)0x480c87e8, (q31_t)0x96340939, (q31_t)0x48075657, (q31_t)0x96307ff5, + (q31_t)0x48022499, (q31_t)0x962cf6f2, (q31_t)0x47fcf2af, (q31_t)0x96296e31, (q31_t)0x47f7c099, (q31_t)0x9625e5b0, (q31_t)0x47f28e56, (q31_t)0x96225d71, + (q31_t)0x47ed5be6, (q31_t)0x961ed574, (q31_t)0x47e8294a, (q31_t)0x961b4db7, (q31_t)0x47e2f682, (q31_t)0x9617c63c, (q31_t)0x47ddc38e, (q31_t)0x96143f02, + (q31_t)0x47d8906d, (q31_t)0x9610b80a, (q31_t)0x47d35d20, (q31_t)0x960d3153, (q31_t)0x47ce29a7, (q31_t)0x9609aadd, (q31_t)0x47c8f601, (q31_t)0x960624a9, + (q31_t)0x47c3c22f, (q31_t)0x96029eb6, (q31_t)0x47be8e31, (q31_t)0x95ff1904, (q31_t)0x47b95a06, (q31_t)0x95fb9394, (q31_t)0x47b425af, (q31_t)0x95f80e65, + (q31_t)0x47aef12c, (q31_t)0x95f48977, (q31_t)0x47a9bc7d, (q31_t)0x95f104cb, (q31_t)0x47a487a2, (q31_t)0x95ed8061, (q31_t)0x479f529a, (q31_t)0x95e9fc38, + (q31_t)0x479a1d67, (q31_t)0x95e67850, (q31_t)0x4794e807, (q31_t)0x95e2f4a9, (q31_t)0x478fb27b, (q31_t)0x95df7145, (q31_t)0x478a7cc2, (q31_t)0x95dbee21, + (q31_t)0x478546de, (q31_t)0x95d86b3f, (q31_t)0x478010cd, (q31_t)0x95d4e89f, (q31_t)0x477ada91, (q31_t)0x95d16640, (q31_t)0x4775a428, (q31_t)0x95cde423, + (q31_t)0x47706d93, (q31_t)0x95ca6247, (q31_t)0x476b36d3, (q31_t)0x95c6e0ac, (q31_t)0x4765ffe6, (q31_t)0x95c35f53, (q31_t)0x4760c8cd, (q31_t)0x95bfde3c, + (q31_t)0x475b9188, (q31_t)0x95bc5d66, (q31_t)0x47565a17, (q31_t)0x95b8dcd2, (q31_t)0x4751227a, (q31_t)0x95b55c7f, (q31_t)0x474beab1, (q31_t)0x95b1dc6e, + (q31_t)0x4746b2bc, (q31_t)0x95ae5c9f, (q31_t)0x47417a9b, (q31_t)0x95aadd11, (q31_t)0x473c424e, (q31_t)0x95a75dc4, (q31_t)0x473709d5, (q31_t)0x95a3deb9, + (q31_t)0x4731d131, (q31_t)0x95a05ff0, (q31_t)0x472c9860, (q31_t)0x959ce169, (q31_t)0x47275f63, (q31_t)0x95996323, (q31_t)0x4722263b, (q31_t)0x9595e51e, + (q31_t)0x471cece7, (q31_t)0x9592675c, (q31_t)0x4717b367, (q31_t)0x958ee9db, (q31_t)0x471279ba, (q31_t)0x958b6c9b, (q31_t)0x470d3fe3, (q31_t)0x9587ef9e, + (q31_t)0x470805df, (q31_t)0x958472e2, (q31_t)0x4702cbaf, (q31_t)0x9580f667, (q31_t)0x46fd9154, (q31_t)0x957d7a2f, (q31_t)0x46f856cd, (q31_t)0x9579fe38, + (q31_t)0x46f31c1a, (q31_t)0x95768283, (q31_t)0x46ede13b, (q31_t)0x9573070f, (q31_t)0x46e8a631, (q31_t)0x956f8bdd, (q31_t)0x46e36afb, (q31_t)0x956c10ed, + (q31_t)0x46de2f99, (q31_t)0x9568963f, (q31_t)0x46d8f40b, (q31_t)0x95651bd2, (q31_t)0x46d3b852, (q31_t)0x9561a1a8, (q31_t)0x46ce7c6d, (q31_t)0x955e27bf, + (q31_t)0x46c9405c, (q31_t)0x955aae17, (q31_t)0x46c40420, (q31_t)0x955734b2, (q31_t)0x46bec7b8, (q31_t)0x9553bb8e, (q31_t)0x46b98b24, (q31_t)0x955042ac, + (q31_t)0x46b44e65, (q31_t)0x954cca0c, (q31_t)0x46af117a, (q31_t)0x954951ae, (q31_t)0x46a9d464, (q31_t)0x9545d992, (q31_t)0x46a49722, (q31_t)0x954261b7, + (q31_t)0x469f59b4, (q31_t)0x953eea1e, (q31_t)0x469a1c1b, (q31_t)0x953b72c7, (q31_t)0x4694de56, (q31_t)0x9537fbb2, (q31_t)0x468fa066, (q31_t)0x953484df, + (q31_t)0x468a624a, (q31_t)0x95310e4e, (q31_t)0x46852403, (q31_t)0x952d97fe, (q31_t)0x467fe590, (q31_t)0x952a21f1, (q31_t)0x467aa6f2, (q31_t)0x9526ac25, + (q31_t)0x46756828, (q31_t)0x9523369c, (q31_t)0x46702933, (q31_t)0x951fc154, (q31_t)0x466aea12, (q31_t)0x951c4c4e, (q31_t)0x4665aac6, (q31_t)0x9518d78a, + (q31_t)0x46606b4e, (q31_t)0x95156308, (q31_t)0x465b2bab, (q31_t)0x9511eec8, (q31_t)0x4655ebdd, (q31_t)0x950e7aca, (q31_t)0x4650abe3, (q31_t)0x950b070e, + (q31_t)0x464b6bbe, (q31_t)0x95079394, (q31_t)0x46462b6d, (q31_t)0x9504205c, (q31_t)0x4640eaf2, (q31_t)0x9500ad66, (q31_t)0x463baa4a, (q31_t)0x94fd3ab1, + (q31_t)0x46366978, (q31_t)0x94f9c83f, (q31_t)0x4631287a, (q31_t)0x94f6560f, (q31_t)0x462be751, (q31_t)0x94f2e421, (q31_t)0x4626a5fd, (q31_t)0x94ef7275, + (q31_t)0x4621647d, (q31_t)0x94ec010b, (q31_t)0x461c22d2, (q31_t)0x94e88fe3, (q31_t)0x4616e0fc, (q31_t)0x94e51efd, (q31_t)0x46119efa, (q31_t)0x94e1ae59, + (q31_t)0x460c5cce, (q31_t)0x94de3df8, (q31_t)0x46071a76, (q31_t)0x94dacdd8, (q31_t)0x4601d7f3, (q31_t)0x94d75dfa, (q31_t)0x45fc9545, (q31_t)0x94d3ee5f, + (q31_t)0x45f7526b, (q31_t)0x94d07f05, (q31_t)0x45f20f67, (q31_t)0x94cd0fee, (q31_t)0x45eccc37, (q31_t)0x94c9a119, (q31_t)0x45e788dc, (q31_t)0x94c63286, + (q31_t)0x45e24556, (q31_t)0x94c2c435, (q31_t)0x45dd01a5, (q31_t)0x94bf5627, (q31_t)0x45d7bdc9, (q31_t)0x94bbe85a, (q31_t)0x45d279c2, (q31_t)0x94b87ad0, + (q31_t)0x45cd358f, (q31_t)0x94b50d87, (q31_t)0x45c7f132, (q31_t)0x94b1a081, (q31_t)0x45c2acaa, (q31_t)0x94ae33be, (q31_t)0x45bd67f6, (q31_t)0x94aac73c, + (q31_t)0x45b82318, (q31_t)0x94a75afd, (q31_t)0x45b2de0e, (q31_t)0x94a3eeff, (q31_t)0x45ad98da, (q31_t)0x94a08344, (q31_t)0x45a8537a, (q31_t)0x949d17cc, + (q31_t)0x45a30df0, (q31_t)0x9499ac95, (q31_t)0x459dc83b, (q31_t)0x949641a1, (q31_t)0x4598825a, (q31_t)0x9492d6ef, (q31_t)0x45933c4f, (q31_t)0x948f6c7f, + (q31_t)0x458df619, (q31_t)0x948c0252, (q31_t)0x4588afb8, (q31_t)0x94889867, (q31_t)0x4583692c, (q31_t)0x94852ebe, (q31_t)0x457e2275, (q31_t)0x9481c557, + (q31_t)0x4578db93, (q31_t)0x947e5c33, (q31_t)0x45739487, (q31_t)0x947af351, (q31_t)0x456e4d4f, (q31_t)0x94778ab1, (q31_t)0x456905ed, (q31_t)0x94742254, + (q31_t)0x4563be60, (q31_t)0x9470ba39, (q31_t)0x455e76a8, (q31_t)0x946d5260, (q31_t)0x45592ec6, (q31_t)0x9469eaca, (q31_t)0x4553e6b8, (q31_t)0x94668376, + (q31_t)0x454e9e80, (q31_t)0x94631c65, (q31_t)0x4549561d, (q31_t)0x945fb596, (q31_t)0x45440d90, (q31_t)0x945c4f09, (q31_t)0x453ec4d7, (q31_t)0x9458e8bf, + (q31_t)0x45397bf4, (q31_t)0x945582b7, (q31_t)0x453432e6, (q31_t)0x94521cf1, (q31_t)0x452ee9ae, (q31_t)0x944eb76e, (q31_t)0x4529a04b, (q31_t)0x944b522d, + (q31_t)0x452456bd, (q31_t)0x9447ed2f, (q31_t)0x451f0d04, (q31_t)0x94448873, (q31_t)0x4519c321, (q31_t)0x944123fa, (q31_t)0x45147913, (q31_t)0x943dbfc3, + (q31_t)0x450f2edb, (q31_t)0x943a5bcf, (q31_t)0x4509e478, (q31_t)0x9436f81d, (q31_t)0x450499eb, (q31_t)0x943394ad, (q31_t)0x44ff4f32, (q31_t)0x94303180, + (q31_t)0x44fa0450, (q31_t)0x942cce96, (q31_t)0x44f4b943, (q31_t)0x94296bee, (q31_t)0x44ef6e0b, (q31_t)0x94260989, (q31_t)0x44ea22a9, (q31_t)0x9422a766, + (q31_t)0x44e4d71c, (q31_t)0x941f4585, (q31_t)0x44df8b64, (q31_t)0x941be3e8, (q31_t)0x44da3f83, (q31_t)0x9418828c, (q31_t)0x44d4f376, (q31_t)0x94152174, + (q31_t)0x44cfa740, (q31_t)0x9411c09e, (q31_t)0x44ca5adf, (q31_t)0x940e600a, (q31_t)0x44c50e53, (q31_t)0x940affb9, (q31_t)0x44bfc19d, (q31_t)0x94079fab, + (q31_t)0x44ba74bd, (q31_t)0x94043fdf, (q31_t)0x44b527b2, (q31_t)0x9400e056, (q31_t)0x44afda7d, (q31_t)0x93fd810f, (q31_t)0x44aa8d1d, (q31_t)0x93fa220b, + (q31_t)0x44a53f93, (q31_t)0x93f6c34a, (q31_t)0x449ff1df, (q31_t)0x93f364cb, (q31_t)0x449aa400, (q31_t)0x93f0068f, (q31_t)0x449555f7, (q31_t)0x93eca896, + (q31_t)0x449007c4, (q31_t)0x93e94adf, (q31_t)0x448ab967, (q31_t)0x93e5ed6b, (q31_t)0x44856adf, (q31_t)0x93e2903a, (q31_t)0x44801c2d, (q31_t)0x93df334c, + (q31_t)0x447acd50, (q31_t)0x93dbd6a0, (q31_t)0x44757e4a, (q31_t)0x93d87a36, (q31_t)0x44702f19, (q31_t)0x93d51e10, (q31_t)0x446adfbe, (q31_t)0x93d1c22c, + (q31_t)0x44659039, (q31_t)0x93ce668b, (q31_t)0x44604089, (q31_t)0x93cb0b2d, (q31_t)0x445af0b0, (q31_t)0x93c7b011, (q31_t)0x4455a0ac, (q31_t)0x93c45539, + (q31_t)0x4450507e, (q31_t)0x93c0faa3, (q31_t)0x444b0026, (q31_t)0x93bda04f, (q31_t)0x4445afa4, (q31_t)0x93ba463f, (q31_t)0x44405ef8, (q31_t)0x93b6ec71, + (q31_t)0x443b0e21, (q31_t)0x93b392e6, (q31_t)0x4435bd21, (q31_t)0x93b0399e, (q31_t)0x44306bf6, (q31_t)0x93ace099, (q31_t)0x442b1aa2, (q31_t)0x93a987d6, + (q31_t)0x4425c923, (q31_t)0x93a62f57, (q31_t)0x4420777b, (q31_t)0x93a2d71a, (q31_t)0x441b25a8, (q31_t)0x939f7f20, (q31_t)0x4415d3ab, (q31_t)0x939c2769, + (q31_t)0x44108184, (q31_t)0x9398cff5, (q31_t)0x440b2f34, (q31_t)0x939578c3, (q31_t)0x4405dcb9, (q31_t)0x939221d5, (q31_t)0x44008a14, (q31_t)0x938ecb29, + (q31_t)0x43fb3746, (q31_t)0x938b74c1, (q31_t)0x43f5e44d, (q31_t)0x93881e9b, (q31_t)0x43f0912b, (q31_t)0x9384c8b8, (q31_t)0x43eb3ddf, (q31_t)0x93817318, + (q31_t)0x43e5ea68, (q31_t)0x937e1dbb, (q31_t)0x43e096c8, (q31_t)0x937ac8a1, (q31_t)0x43db42fe, (q31_t)0x937773ca, (q31_t)0x43d5ef0a, (q31_t)0x93741f35, + (q31_t)0x43d09aed, (q31_t)0x9370cae4, (q31_t)0x43cb46a5, (q31_t)0x936d76d6, (q31_t)0x43c5f234, (q31_t)0x936a230a, (q31_t)0x43c09d99, (q31_t)0x9366cf82, + (q31_t)0x43bb48d4, (q31_t)0x93637c3d, (q31_t)0x43b5f3e5, (q31_t)0x9360293a, (q31_t)0x43b09ecc, (q31_t)0x935cd67b, (q31_t)0x43ab498a, (q31_t)0x935983ff, + (q31_t)0x43a5f41e, (q31_t)0x935631c5, (q31_t)0x43a09e89, (q31_t)0x9352dfcf, (q31_t)0x439b48c9, (q31_t)0x934f8e1c, (q31_t)0x4395f2e0, (q31_t)0x934c3cab, + (q31_t)0x43909ccd, (q31_t)0x9348eb7e, (q31_t)0x438b4691, (q31_t)0x93459a94, (q31_t)0x4385f02a, (q31_t)0x934249ed, (q31_t)0x4380999b, (q31_t)0x933ef989, + (q31_t)0x437b42e1, (q31_t)0x933ba968, (q31_t)0x4375ebfe, (q31_t)0x9338598a, (q31_t)0x437094f1, (q31_t)0x933509f0, (q31_t)0x436b3dbb, (q31_t)0x9331ba98, + (q31_t)0x4365e65b, (q31_t)0x932e6b84, (q31_t)0x43608ed2, (q31_t)0x932b1cb2, (q31_t)0x435b371f, (q31_t)0x9327ce24, (q31_t)0x4355df42, (q31_t)0x93247fd9, + (q31_t)0x4350873c, (q31_t)0x932131d1, (q31_t)0x434b2f0c, (q31_t)0x931de40c, (q31_t)0x4345d6b3, (q31_t)0x931a968b, (q31_t)0x43407e31, (q31_t)0x9317494c, + (q31_t)0x433b2585, (q31_t)0x9313fc51, (q31_t)0x4335ccaf, (q31_t)0x9310af99, (q31_t)0x433073b0, (q31_t)0x930d6324, (q31_t)0x432b1a87, (q31_t)0x930a16f3, + (q31_t)0x4325c135, (q31_t)0x9306cb04, (q31_t)0x432067ba, (q31_t)0x93037f59, (q31_t)0x431b0e15, (q31_t)0x930033f1, (q31_t)0x4315b447, (q31_t)0x92fce8cc, + (q31_t)0x43105a50, (q31_t)0x92f99deb, (q31_t)0x430b002f, (q31_t)0x92f6534c, (q31_t)0x4305a5e5, (q31_t)0x92f308f1, (q31_t)0x43004b71, (q31_t)0x92efbeda, + (q31_t)0x42faf0d4, (q31_t)0x92ec7505, (q31_t)0x42f5960e, (q31_t)0x92e92b74, (q31_t)0x42f03b1e, (q31_t)0x92e5e226, (q31_t)0x42eae005, (q31_t)0x92e2991c, + (q31_t)0x42e584c3, (q31_t)0x92df5054, (q31_t)0x42e02958, (q31_t)0x92dc07d0, (q31_t)0x42dacdc3, (q31_t)0x92d8bf90, (q31_t)0x42d57205, (q31_t)0x92d57792, + (q31_t)0x42d0161e, (q31_t)0x92d22fd9, (q31_t)0x42caba0e, (q31_t)0x92cee862, (q31_t)0x42c55dd4, (q31_t)0x92cba12f, (q31_t)0x42c00172, (q31_t)0x92c85a3f, + (q31_t)0x42baa4e6, (q31_t)0x92c51392, (q31_t)0x42b54831, (q31_t)0x92c1cd29, (q31_t)0x42afeb53, (q31_t)0x92be8703, (q31_t)0x42aa8e4b, (q31_t)0x92bb4121, + (q31_t)0x42a5311b, (q31_t)0x92b7fb82, (q31_t)0x429fd3c1, (q31_t)0x92b4b626, (q31_t)0x429a763f, (q31_t)0x92b1710e, (q31_t)0x42951893, (q31_t)0x92ae2c3a, + (q31_t)0x428fbabe, (q31_t)0x92aae7a8, (q31_t)0x428a5cc0, (q31_t)0x92a7a35a, (q31_t)0x4284fe99, (q31_t)0x92a45f50, (q31_t)0x427fa049, (q31_t)0x92a11b89, + (q31_t)0x427a41d0, (q31_t)0x929dd806, (q31_t)0x4274e32e, (q31_t)0x929a94c6, (q31_t)0x426f8463, (q31_t)0x929751c9, (q31_t)0x426a256f, (q31_t)0x92940f10, + (q31_t)0x4264c653, (q31_t)0x9290cc9b, (q31_t)0x425f670d, (q31_t)0x928d8a69, (q31_t)0x425a079e, (q31_t)0x928a487a, (q31_t)0x4254a806, (q31_t)0x928706cf, + (q31_t)0x424f4845, (q31_t)0x9283c568, (q31_t)0x4249e85c, (q31_t)0x92808444, (q31_t)0x42448849, (q31_t)0x927d4363, (q31_t)0x423f280e, (q31_t)0x927a02c7, + (q31_t)0x4239c7aa, (q31_t)0x9276c26d, (q31_t)0x4234671d, (q31_t)0x92738258, (q31_t)0x422f0667, (q31_t)0x92704286, (q31_t)0x4229a588, (q31_t)0x926d02f7, + (q31_t)0x42244481, (q31_t)0x9269c3ac, (q31_t)0x421ee350, (q31_t)0x926684a5, (q31_t)0x421981f7, (q31_t)0x926345e1, (q31_t)0x42142075, (q31_t)0x92600761, + (q31_t)0x420ebecb, (q31_t)0x925cc924, (q31_t)0x42095cf7, (q31_t)0x92598b2b, (q31_t)0x4203fafb, (q31_t)0x92564d76, (q31_t)0x41fe98d6, (q31_t)0x92531005, + (q31_t)0x41f93689, (q31_t)0x924fd2d7, (q31_t)0x41f3d413, (q31_t)0x924c95ec, (q31_t)0x41ee7174, (q31_t)0x92495946, (q31_t)0x41e90eac, (q31_t)0x92461ce3, + (q31_t)0x41e3abbc, (q31_t)0x9242e0c4, (q31_t)0x41de48a3, (q31_t)0x923fa4e8, (q31_t)0x41d8e561, (q31_t)0x923c6950, (q31_t)0x41d381f7, (q31_t)0x92392dfc, + (q31_t)0x41ce1e65, (q31_t)0x9235f2ec, (q31_t)0x41c8baa9, (q31_t)0x9232b81f, (q31_t)0x41c356c5, (q31_t)0x922f7d96, (q31_t)0x41bdf2b9, (q31_t)0x922c4351, + (q31_t)0x41b88e84, (q31_t)0x9229094f, (q31_t)0x41b32a26, (q31_t)0x9225cf91, (q31_t)0x41adc5a0, (q31_t)0x92229617, (q31_t)0x41a860f1, (q31_t)0x921f5ce1, + (q31_t)0x41a2fc1a, (q31_t)0x921c23ef, (q31_t)0x419d971b, (q31_t)0x9218eb40, (q31_t)0x419831f3, (q31_t)0x9215b2d5, (q31_t)0x4192cca2, (q31_t)0x92127aae, + (q31_t)0x418d6729, (q31_t)0x920f42cb, (q31_t)0x41880188, (q31_t)0x920c0b2c, (q31_t)0x41829bbe, (q31_t)0x9208d3d0, (q31_t)0x417d35cb, (q31_t)0x92059cb8, + (q31_t)0x4177cfb1, (q31_t)0x920265e4, (q31_t)0x4172696e, (q31_t)0x91ff2f54, (q31_t)0x416d0302, (q31_t)0x91fbf908, (q31_t)0x41679c6f, (q31_t)0x91f8c300, + (q31_t)0x416235b2, (q31_t)0x91f58d3b, (q31_t)0x415ccece, (q31_t)0x91f257bb, (q31_t)0x415767c1, (q31_t)0x91ef227e, (q31_t)0x4152008c, (q31_t)0x91ebed85, + (q31_t)0x414c992f, (q31_t)0x91e8b8d0, (q31_t)0x414731a9, (q31_t)0x91e5845f, (q31_t)0x4141c9fb, (q31_t)0x91e25032, (q31_t)0x413c6225, (q31_t)0x91df1c49, + (q31_t)0x4136fa27, (q31_t)0x91dbe8a4, (q31_t)0x41319200, (q31_t)0x91d8b542, (q31_t)0x412c29b1, (q31_t)0x91d58225, (q31_t)0x4126c13a, (q31_t)0x91d24f4c, + (q31_t)0x4121589b, (q31_t)0x91cf1cb6, (q31_t)0x411befd3, (q31_t)0x91cbea65, (q31_t)0x411686e4, (q31_t)0x91c8b857, (q31_t)0x41111dcc, (q31_t)0x91c5868e, + (q31_t)0x410bb48c, (q31_t)0x91c25508, (q31_t)0x41064b24, (q31_t)0x91bf23c7, (q31_t)0x4100e194, (q31_t)0x91bbf2c9, (q31_t)0x40fb77dc, (q31_t)0x91b8c210, + (q31_t)0x40f60dfb, (q31_t)0x91b5919a, (q31_t)0x40f0a3f3, (q31_t)0x91b26169, (q31_t)0x40eb39c3, (q31_t)0x91af317c, (q31_t)0x40e5cf6a, (q31_t)0x91ac01d2, + (q31_t)0x40e064ea, (q31_t)0x91a8d26d, (q31_t)0x40dafa41, (q31_t)0x91a5a34c, (q31_t)0x40d58f71, (q31_t)0x91a2746f, (q31_t)0x40d02478, (q31_t)0x919f45d6, + (q31_t)0x40cab958, (q31_t)0x919c1781, (q31_t)0x40c54e0f, (q31_t)0x9198e970, (q31_t)0x40bfe29f, (q31_t)0x9195bba3, (q31_t)0x40ba7706, (q31_t)0x91928e1a, + (q31_t)0x40b50b46, (q31_t)0x918f60d6, (q31_t)0x40af9f5e, (q31_t)0x918c33d5, (q31_t)0x40aa334e, (q31_t)0x91890719, (q31_t)0x40a4c716, (q31_t)0x9185daa1, + (q31_t)0x409f5ab6, (q31_t)0x9182ae6d, (q31_t)0x4099ee2e, (q31_t)0x917f827d, (q31_t)0x4094817f, (q31_t)0x917c56d1, (q31_t)0x408f14a7, (q31_t)0x91792b6a, + (q31_t)0x4089a7a8, (q31_t)0x91760047, (q31_t)0x40843a81, (q31_t)0x9172d567, (q31_t)0x407ecd32, (q31_t)0x916faacc, (q31_t)0x40795fbc, (q31_t)0x916c8076, + (q31_t)0x4073f21d, (q31_t)0x91695663, (q31_t)0x406e8457, (q31_t)0x91662c95, (q31_t)0x40691669, (q31_t)0x9163030b, (q31_t)0x4063a854, (q31_t)0x915fd9c5, + (q31_t)0x405e3a16, (q31_t)0x915cb0c3, (q31_t)0x4058cbb1, (q31_t)0x91598806, (q31_t)0x40535d24, (q31_t)0x91565f8d, (q31_t)0x404dee70, (q31_t)0x91533758, + (q31_t)0x40487f94, (q31_t)0x91500f67, (q31_t)0x40431090, (q31_t)0x914ce7bb, (q31_t)0x403da165, (q31_t)0x9149c053, (q31_t)0x40383212, (q31_t)0x9146992f, + (q31_t)0x4032c297, (q31_t)0x91437250, (q31_t)0x402d52f5, (q31_t)0x91404bb5, (q31_t)0x4027e32b, (q31_t)0x913d255e, (q31_t)0x4022733a, (q31_t)0x9139ff4b, + (q31_t)0x401d0321, (q31_t)0x9136d97d, (q31_t)0x401792e0, (q31_t)0x9133b3f3, (q31_t)0x40122278, (q31_t)0x91308eae, (q31_t)0x400cb1e9, (q31_t)0x912d69ad, + (q31_t)0x40074132, (q31_t)0x912a44f0, (q31_t)0x4001d053, (q31_t)0x91272078, (q31_t)0x3ffc5f4d, (q31_t)0x9123fc44, (q31_t)0x3ff6ee1f, (q31_t)0x9120d854, + (q31_t)0x3ff17cca, (q31_t)0x911db4a9, (q31_t)0x3fec0b4e, (q31_t)0x911a9142, (q31_t)0x3fe699aa, (q31_t)0x91176e1f, (q31_t)0x3fe127df, (q31_t)0x91144b41, + (q31_t)0x3fdbb5ec, (q31_t)0x911128a8, (q31_t)0x3fd643d2, (q31_t)0x910e0653, (q31_t)0x3fd0d191, (q31_t)0x910ae442, (q31_t)0x3fcb5f28, (q31_t)0x9107c276, + (q31_t)0x3fc5ec98, (q31_t)0x9104a0ee, (q31_t)0x3fc079e0, (q31_t)0x91017faa, (q31_t)0x3fbb0702, (q31_t)0x90fe5eab, (q31_t)0x3fb593fb, (q31_t)0x90fb3df1, + (q31_t)0x3fb020ce, (q31_t)0x90f81d7b, (q31_t)0x3faaad79, (q31_t)0x90f4fd4a, (q31_t)0x3fa539fd, (q31_t)0x90f1dd5d, (q31_t)0x3f9fc65a, (q31_t)0x90eebdb4, + (q31_t)0x3f9a5290, (q31_t)0x90eb9e50, (q31_t)0x3f94de9e, (q31_t)0x90e87f31, (q31_t)0x3f8f6a85, (q31_t)0x90e56056, (q31_t)0x3f89f645, (q31_t)0x90e241bf, + (q31_t)0x3f8481dd, (q31_t)0x90df236e, (q31_t)0x3f7f0d4f, (q31_t)0x90dc0560, (q31_t)0x3f799899, (q31_t)0x90d8e798, (q31_t)0x3f7423bc, (q31_t)0x90d5ca13, + (q31_t)0x3f6eaeb8, (q31_t)0x90d2acd4, (q31_t)0x3f69398d, (q31_t)0x90cf8fd9, (q31_t)0x3f63c43b, (q31_t)0x90cc7322, (q31_t)0x3f5e4ec2, (q31_t)0x90c956b1, + (q31_t)0x3f58d921, (q31_t)0x90c63a83, (q31_t)0x3f53635a, (q31_t)0x90c31e9b, (q31_t)0x3f4ded6b, (q31_t)0x90c002f7, (q31_t)0x3f487755, (q31_t)0x90bce797, + (q31_t)0x3f430119, (q31_t)0x90b9cc7d, (q31_t)0x3f3d8ab5, (q31_t)0x90b6b1a6, (q31_t)0x3f38142a, (q31_t)0x90b39715, (q31_t)0x3f329d79, (q31_t)0x90b07cc8, + (q31_t)0x3f2d26a0, (q31_t)0x90ad62c0, (q31_t)0x3f27afa1, (q31_t)0x90aa48fd, (q31_t)0x3f22387a, (q31_t)0x90a72f7e, (q31_t)0x3f1cc12c, (q31_t)0x90a41644, + (q31_t)0x3f1749b8, (q31_t)0x90a0fd4e, (q31_t)0x3f11d21d, (q31_t)0x909de49e, (q31_t)0x3f0c5a5a, (q31_t)0x909acc32, (q31_t)0x3f06e271, (q31_t)0x9097b40a, + (q31_t)0x3f016a61, (q31_t)0x90949c28, (q31_t)0x3efbf22a, (q31_t)0x9091848a, (q31_t)0x3ef679cc, (q31_t)0x908e6d31, (q31_t)0x3ef10148, (q31_t)0x908b561c, + (q31_t)0x3eeb889c, (q31_t)0x90883f4d, (q31_t)0x3ee60fca, (q31_t)0x908528c2, (q31_t)0x3ee096d1, (q31_t)0x9082127c, (q31_t)0x3edb1db1, (q31_t)0x907efc7a, + (q31_t)0x3ed5a46b, (q31_t)0x907be6be, (q31_t)0x3ed02afd, (q31_t)0x9078d146, (q31_t)0x3ecab169, (q31_t)0x9075bc13, (q31_t)0x3ec537ae, (q31_t)0x9072a725, + (q31_t)0x3ebfbdcd, (q31_t)0x906f927c, (q31_t)0x3eba43c4, (q31_t)0x906c7e17, (q31_t)0x3eb4c995, (q31_t)0x906969f8, (q31_t)0x3eaf4f40, (q31_t)0x9066561d, + (q31_t)0x3ea9d4c3, (q31_t)0x90634287, (q31_t)0x3ea45a21, (q31_t)0x90602f35, (q31_t)0x3e9edf57, (q31_t)0x905d1c29, (q31_t)0x3e996467, (q31_t)0x905a0962, + (q31_t)0x3e93e950, (q31_t)0x9056f6df, (q31_t)0x3e8e6e12, (q31_t)0x9053e4a1, (q31_t)0x3e88f2ae, (q31_t)0x9050d2a9, (q31_t)0x3e837724, (q31_t)0x904dc0f5, + (q31_t)0x3e7dfb73, (q31_t)0x904aaf86, (q31_t)0x3e787f9b, (q31_t)0x90479e5c, (q31_t)0x3e73039d, (q31_t)0x90448d76, (q31_t)0x3e6d8778, (q31_t)0x90417cd6, + (q31_t)0x3e680b2c, (q31_t)0x903e6c7b, (q31_t)0x3e628ebb, (q31_t)0x903b5c64, (q31_t)0x3e5d1222, (q31_t)0x90384c93, (q31_t)0x3e579564, (q31_t)0x90353d06, + (q31_t)0x3e52187f, (q31_t)0x90322dbf, (q31_t)0x3e4c9b73, (q31_t)0x902f1ebc, (q31_t)0x3e471e41, (q31_t)0x902c0fff, (q31_t)0x3e41a0e8, (q31_t)0x90290186, + (q31_t)0x3e3c2369, (q31_t)0x9025f352, (q31_t)0x3e36a5c4, (q31_t)0x9022e564, (q31_t)0x3e3127f9, (q31_t)0x901fd7ba, (q31_t)0x3e2baa07, (q31_t)0x901cca55, + (q31_t)0x3e262bee, (q31_t)0x9019bd36, (q31_t)0x3e20adaf, (q31_t)0x9016b05b, (q31_t)0x3e1b2f4a, (q31_t)0x9013a3c5, (q31_t)0x3e15b0bf, (q31_t)0x90109775, + (q31_t)0x3e10320d, (q31_t)0x900d8b69, (q31_t)0x3e0ab336, (q31_t)0x900a7fa3, (q31_t)0x3e053437, (q31_t)0x90077422, (q31_t)0x3dffb513, (q31_t)0x900468e5, + (q31_t)0x3dfa35c8, (q31_t)0x90015dee, (q31_t)0x3df4b657, (q31_t)0x8ffe533c, (q31_t)0x3def36c0, (q31_t)0x8ffb48cf, (q31_t)0x3de9b703, (q31_t)0x8ff83ea7, + (q31_t)0x3de4371f, (q31_t)0x8ff534c4, (q31_t)0x3ddeb716, (q31_t)0x8ff22b26, (q31_t)0x3dd936e6, (q31_t)0x8fef21ce, (q31_t)0x3dd3b690, (q31_t)0x8fec18ba, + (q31_t)0x3dce3614, (q31_t)0x8fe90fec, (q31_t)0x3dc8b571, (q31_t)0x8fe60763, (q31_t)0x3dc334a9, (q31_t)0x8fe2ff1f, (q31_t)0x3dbdb3ba, (q31_t)0x8fdff720, + (q31_t)0x3db832a6, (q31_t)0x8fdcef66, (q31_t)0x3db2b16b, (q31_t)0x8fd9e7f2, (q31_t)0x3dad300b, (q31_t)0x8fd6e0c2, (q31_t)0x3da7ae84, (q31_t)0x8fd3d9d8, + (q31_t)0x3da22cd7, (q31_t)0x8fd0d333, (q31_t)0x3d9cab04, (q31_t)0x8fcdccd3, (q31_t)0x3d97290b, (q31_t)0x8fcac6b9, (q31_t)0x3d91a6ed, (q31_t)0x8fc7c0e3, + (q31_t)0x3d8c24a8, (q31_t)0x8fc4bb53, (q31_t)0x3d86a23d, (q31_t)0x8fc1b608, (q31_t)0x3d811fac, (q31_t)0x8fbeb103, (q31_t)0x3d7b9cf6, (q31_t)0x8fbbac42, + (q31_t)0x3d761a19, (q31_t)0x8fb8a7c7, (q31_t)0x3d709717, (q31_t)0x8fb5a391, (q31_t)0x3d6b13ee, (q31_t)0x8fb29fa0, (q31_t)0x3d6590a0, (q31_t)0x8faf9bf5, + (q31_t)0x3d600d2c, (q31_t)0x8fac988f, (q31_t)0x3d5a8992, (q31_t)0x8fa9956e, (q31_t)0x3d5505d2, (q31_t)0x8fa69293, (q31_t)0x3d4f81ec, (q31_t)0x8fa38ffc, + (q31_t)0x3d49fde1, (q31_t)0x8fa08dab, (q31_t)0x3d4479b0, (q31_t)0x8f9d8ba0, (q31_t)0x3d3ef559, (q31_t)0x8f9a89da, (q31_t)0x3d3970dc, (q31_t)0x8f978859, + (q31_t)0x3d33ec39, (q31_t)0x8f94871d, (q31_t)0x3d2e6771, (q31_t)0x8f918627, (q31_t)0x3d28e282, (q31_t)0x8f8e8576, (q31_t)0x3d235d6f, (q31_t)0x8f8b850a, + (q31_t)0x3d1dd835, (q31_t)0x8f8884e4, (q31_t)0x3d1852d6, (q31_t)0x8f858503, (q31_t)0x3d12cd51, (q31_t)0x8f828568, (q31_t)0x3d0d47a6, (q31_t)0x8f7f8612, + (q31_t)0x3d07c1d6, (q31_t)0x8f7c8701, (q31_t)0x3d023be0, (q31_t)0x8f798836, (q31_t)0x3cfcb5c4, (q31_t)0x8f7689b0, (q31_t)0x3cf72f83, (q31_t)0x8f738b70, + (q31_t)0x3cf1a91c, (q31_t)0x8f708d75, (q31_t)0x3cec2290, (q31_t)0x8f6d8fbf, (q31_t)0x3ce69bde, (q31_t)0x8f6a924f, (q31_t)0x3ce11507, (q31_t)0x8f679525, + (q31_t)0x3cdb8e09, (q31_t)0x8f649840, (q31_t)0x3cd606e7, (q31_t)0x8f619ba0, (q31_t)0x3cd07f9f, (q31_t)0x8f5e9f46, (q31_t)0x3ccaf831, (q31_t)0x8f5ba331, + (q31_t)0x3cc5709e, (q31_t)0x8f58a761, (q31_t)0x3cbfe8e5, (q31_t)0x8f55abd8, (q31_t)0x3cba6107, (q31_t)0x8f52b093, (q31_t)0x3cb4d904, (q31_t)0x8f4fb595, + (q31_t)0x3caf50da, (q31_t)0x8f4cbadb, (q31_t)0x3ca9c88c, (q31_t)0x8f49c067, (q31_t)0x3ca44018, (q31_t)0x8f46c639, (q31_t)0x3c9eb77f, (q31_t)0x8f43cc50, + (q31_t)0x3c992ec0, (q31_t)0x8f40d2ad, (q31_t)0x3c93a5dc, (q31_t)0x8f3dd950, (q31_t)0x3c8e1cd3, (q31_t)0x8f3ae038, (q31_t)0x3c8893a4, (q31_t)0x8f37e765, + (q31_t)0x3c830a50, (q31_t)0x8f34eed8, (q31_t)0x3c7d80d6, (q31_t)0x8f31f691, (q31_t)0x3c77f737, (q31_t)0x8f2efe8f, (q31_t)0x3c726d73, (q31_t)0x8f2c06d3, + (q31_t)0x3c6ce38a, (q31_t)0x8f290f5c, (q31_t)0x3c67597b, (q31_t)0x8f26182b, (q31_t)0x3c61cf48, (q31_t)0x8f232140, (q31_t)0x3c5c44ee, (q31_t)0x8f202a9a, + (q31_t)0x3c56ba70, (q31_t)0x8f1d343a, (q31_t)0x3c512fcc, (q31_t)0x8f1a3e1f, (q31_t)0x3c4ba504, (q31_t)0x8f17484b, (q31_t)0x3c461a16, (q31_t)0x8f1452bb, + (q31_t)0x3c408f03, (q31_t)0x8f115d72, (q31_t)0x3c3b03ca, (q31_t)0x8f0e686e, (q31_t)0x3c35786d, (q31_t)0x8f0b73b0, (q31_t)0x3c2fecea, (q31_t)0x8f087f37, + (q31_t)0x3c2a6142, (q31_t)0x8f058b04, (q31_t)0x3c24d575, (q31_t)0x8f029717, (q31_t)0x3c1f4983, (q31_t)0x8effa370, (q31_t)0x3c19bd6c, (q31_t)0x8efcb00e, + (q31_t)0x3c143130, (q31_t)0x8ef9bcf2, (q31_t)0x3c0ea4cf, (q31_t)0x8ef6ca1c, (q31_t)0x3c091849, (q31_t)0x8ef3d78b, (q31_t)0x3c038b9e, (q31_t)0x8ef0e540, + (q31_t)0x3bfdfecd, (q31_t)0x8eedf33b, (q31_t)0x3bf871d8, (q31_t)0x8eeb017c, (q31_t)0x3bf2e4be, (q31_t)0x8ee81002, (q31_t)0x3bed577e, (q31_t)0x8ee51ece, + (q31_t)0x3be7ca1a, (q31_t)0x8ee22de0, (q31_t)0x3be23c91, (q31_t)0x8edf3d38, (q31_t)0x3bdcaee3, (q31_t)0x8edc4cd5, (q31_t)0x3bd72110, (q31_t)0x8ed95cb8, + (q31_t)0x3bd19318, (q31_t)0x8ed66ce1, (q31_t)0x3bcc04fb, (q31_t)0x8ed37d50, (q31_t)0x3bc676b9, (q31_t)0x8ed08e05, (q31_t)0x3bc0e853, (q31_t)0x8ecd9eff, + (q31_t)0x3bbb59c7, (q31_t)0x8ecab040, (q31_t)0x3bb5cb17, (q31_t)0x8ec7c1c6, (q31_t)0x3bb03c42, (q31_t)0x8ec4d392, (q31_t)0x3baaad48, (q31_t)0x8ec1e5a4, + (q31_t)0x3ba51e29, (q31_t)0x8ebef7fb, (q31_t)0x3b9f8ee5, (q31_t)0x8ebc0a99, (q31_t)0x3b99ff7d, (q31_t)0x8eb91d7c, (q31_t)0x3b946ff0, (q31_t)0x8eb630a6, + (q31_t)0x3b8ee03e, (q31_t)0x8eb34415, (q31_t)0x3b895068, (q31_t)0x8eb057ca, (q31_t)0x3b83c06c, (q31_t)0x8ead6bc5, (q31_t)0x3b7e304c, (q31_t)0x8eaa8006, + (q31_t)0x3b78a007, (q31_t)0x8ea7948c, (q31_t)0x3b730f9e, (q31_t)0x8ea4a959, (q31_t)0x3b6d7f10, (q31_t)0x8ea1be6c, (q31_t)0x3b67ee5d, (q31_t)0x8e9ed3c4, + (q31_t)0x3b625d86, (q31_t)0x8e9be963, (q31_t)0x3b5ccc8a, (q31_t)0x8e98ff47, (q31_t)0x3b573b69, (q31_t)0x8e961571, (q31_t)0x3b51aa24, (q31_t)0x8e932be2, + (q31_t)0x3b4c18ba, (q31_t)0x8e904298, (q31_t)0x3b46872c, (q31_t)0x8e8d5994, (q31_t)0x3b40f579, (q31_t)0x8e8a70d7, (q31_t)0x3b3b63a1, (q31_t)0x8e87885f, + (q31_t)0x3b35d1a5, (q31_t)0x8e84a02d, (q31_t)0x3b303f84, (q31_t)0x8e81b841, (q31_t)0x3b2aad3f, (q31_t)0x8e7ed09b, (q31_t)0x3b251ad6, (q31_t)0x8e7be93c, + (q31_t)0x3b1f8848, (q31_t)0x8e790222, (q31_t)0x3b19f595, (q31_t)0x8e761b4e, (q31_t)0x3b1462be, (q31_t)0x8e7334c1, (q31_t)0x3b0ecfc3, (q31_t)0x8e704e79, + (q31_t)0x3b093ca3, (q31_t)0x8e6d6877, (q31_t)0x3b03a95e, (q31_t)0x8e6a82bc, (q31_t)0x3afe15f6, (q31_t)0x8e679d47, (q31_t)0x3af88269, (q31_t)0x8e64b817, + (q31_t)0x3af2eeb7, (q31_t)0x8e61d32e, (q31_t)0x3aed5ae1, (q31_t)0x8e5eee8b, (q31_t)0x3ae7c6e7, (q31_t)0x8e5c0a2e, (q31_t)0x3ae232c9, (q31_t)0x8e592617, + (q31_t)0x3adc9e86, (q31_t)0x8e564246, (q31_t)0x3ad70a1f, (q31_t)0x8e535ebb, (q31_t)0x3ad17593, (q31_t)0x8e507b76, (q31_t)0x3acbe0e3, (q31_t)0x8e4d9878, + (q31_t)0x3ac64c0f, (q31_t)0x8e4ab5bf, (q31_t)0x3ac0b717, (q31_t)0x8e47d34d, (q31_t)0x3abb21fb, (q31_t)0x8e44f121, (q31_t)0x3ab58cba, (q31_t)0x8e420f3b, + (q31_t)0x3aaff755, (q31_t)0x8e3f2d9b, (q31_t)0x3aaa61cc, (q31_t)0x8e3c4c41, (q31_t)0x3aa4cc1e, (q31_t)0x8e396b2e, (q31_t)0x3a9f364d, (q31_t)0x8e368a61, + (q31_t)0x3a99a057, (q31_t)0x8e33a9da, (q31_t)0x3a940a3e, (q31_t)0x8e30c999, (q31_t)0x3a8e7400, (q31_t)0x8e2de99e, (q31_t)0x3a88dd9d, (q31_t)0x8e2b09e9, + (q31_t)0x3a834717, (q31_t)0x8e282a7b, (q31_t)0x3a7db06d, (q31_t)0x8e254b53, (q31_t)0x3a78199f, (q31_t)0x8e226c71, (q31_t)0x3a7282ac, (q31_t)0x8e1f8dd6, + (q31_t)0x3a6ceb96, (q31_t)0x8e1caf80, (q31_t)0x3a67545b, (q31_t)0x8e19d171, (q31_t)0x3a61bcfd, (q31_t)0x8e16f3a9, (q31_t)0x3a5c257a, (q31_t)0x8e141626, + (q31_t)0x3a568dd4, (q31_t)0x8e1138ea, (q31_t)0x3a50f609, (q31_t)0x8e0e5bf4, (q31_t)0x3a4b5e1b, (q31_t)0x8e0b7f44, (q31_t)0x3a45c608, (q31_t)0x8e08a2db, + (q31_t)0x3a402dd2, (q31_t)0x8e05c6b7, (q31_t)0x3a3a9577, (q31_t)0x8e02eadb, (q31_t)0x3a34fcf9, (q31_t)0x8e000f44, (q31_t)0x3a2f6457, (q31_t)0x8dfd33f4, + (q31_t)0x3a29cb91, (q31_t)0x8dfa58ea, (q31_t)0x3a2432a7, (q31_t)0x8df77e27, (q31_t)0x3a1e9999, (q31_t)0x8df4a3a9, (q31_t)0x3a190068, (q31_t)0x8df1c973, + (q31_t)0x3a136712, (q31_t)0x8deeef82, (q31_t)0x3a0dcd99, (q31_t)0x8dec15d8, (q31_t)0x3a0833fc, (q31_t)0x8de93c74, (q31_t)0x3a029a3b, (q31_t)0x8de66357, + (q31_t)0x39fd0056, (q31_t)0x8de38a80, (q31_t)0x39f7664e, (q31_t)0x8de0b1ef, (q31_t)0x39f1cc21, (q31_t)0x8dddd9a5, (q31_t)0x39ec31d1, (q31_t)0x8ddb01a1, + (q31_t)0x39e6975e, (q31_t)0x8dd829e4, (q31_t)0x39e0fcc6, (q31_t)0x8dd5526d, (q31_t)0x39db620b, (q31_t)0x8dd27b3c, (q31_t)0x39d5c72c, (q31_t)0x8dcfa452, + (q31_t)0x39d02c2a, (q31_t)0x8dcccdaf, (q31_t)0x39ca9104, (q31_t)0x8dc9f751, (q31_t)0x39c4f5ba, (q31_t)0x8dc7213b, (q31_t)0x39bf5a4d, (q31_t)0x8dc44b6a, + (q31_t)0x39b9bebc, (q31_t)0x8dc175e0, (q31_t)0x39b42307, (q31_t)0x8dbea09d, (q31_t)0x39ae872f, (q31_t)0x8dbbcba0, (q31_t)0x39a8eb33, (q31_t)0x8db8f6ea, + (q31_t)0x39a34f13, (q31_t)0x8db6227a, (q31_t)0x399db2d0, (q31_t)0x8db34e50, (q31_t)0x3998166a, (q31_t)0x8db07a6d, (q31_t)0x399279e0, (q31_t)0x8dada6d1, + (q31_t)0x398cdd32, (q31_t)0x8daad37b, (q31_t)0x39874061, (q31_t)0x8da8006c, (q31_t)0x3981a36d, (q31_t)0x8da52da3, (q31_t)0x397c0655, (q31_t)0x8da25b21, + (q31_t)0x39766919, (q31_t)0x8d9f88e5, (q31_t)0x3970cbba, (q31_t)0x8d9cb6f0, (q31_t)0x396b2e38, (q31_t)0x8d99e541, (q31_t)0x39659092, (q31_t)0x8d9713d9, + (q31_t)0x395ff2c9, (q31_t)0x8d9442b8, (q31_t)0x395a54dd, (q31_t)0x8d9171dd, (q31_t)0x3954b6cd, (q31_t)0x8d8ea148, (q31_t)0x394f1899, (q31_t)0x8d8bd0fb, + (q31_t)0x39497a43, (q31_t)0x8d8900f3, (q31_t)0x3943dbc9, (q31_t)0x8d863133, (q31_t)0x393e3d2c, (q31_t)0x8d8361b9, (q31_t)0x39389e6b, (q31_t)0x8d809286, + (q31_t)0x3932ff87, (q31_t)0x8d7dc399, (q31_t)0x392d6080, (q31_t)0x8d7af4f3, (q31_t)0x3927c155, (q31_t)0x8d782694, (q31_t)0x39222208, (q31_t)0x8d75587b, + (q31_t)0x391c8297, (q31_t)0x8d728aa9, (q31_t)0x3916e303, (q31_t)0x8d6fbd1d, (q31_t)0x3911434b, (q31_t)0x8d6cefd9, (q31_t)0x390ba371, (q31_t)0x8d6a22db, + (q31_t)0x39060373, (q31_t)0x8d675623, (q31_t)0x39006352, (q31_t)0x8d6489b3, (q31_t)0x38fac30e, (q31_t)0x8d61bd89, (q31_t)0x38f522a6, (q31_t)0x8d5ef1a5, + (q31_t)0x38ef821c, (q31_t)0x8d5c2609, (q31_t)0x38e9e16e, (q31_t)0x8d595ab3, (q31_t)0x38e4409e, (q31_t)0x8d568fa4, (q31_t)0x38de9faa, (q31_t)0x8d53c4db, + (q31_t)0x38d8fe93, (q31_t)0x8d50fa59, (q31_t)0x38d35d59, (q31_t)0x8d4e301f, (q31_t)0x38cdbbfc, (q31_t)0x8d4b662a, (q31_t)0x38c81a7c, (q31_t)0x8d489c7d, + (q31_t)0x38c278d9, (q31_t)0x8d45d316, (q31_t)0x38bcd713, (q31_t)0x8d4309f6, (q31_t)0x38b7352a, (q31_t)0x8d40411d, (q31_t)0x38b1931e, (q31_t)0x8d3d788b, + (q31_t)0x38abf0ef, (q31_t)0x8d3ab03f, (q31_t)0x38a64e9d, (q31_t)0x8d37e83a, (q31_t)0x38a0ac29, (q31_t)0x8d35207d, (q31_t)0x389b0991, (q31_t)0x8d325905, + (q31_t)0x389566d6, (q31_t)0x8d2f91d5, (q31_t)0x388fc3f8, (q31_t)0x8d2ccaec, (q31_t)0x388a20f8, (q31_t)0x8d2a0449, (q31_t)0x38847dd5, (q31_t)0x8d273ded, + (q31_t)0x387eda8e, (q31_t)0x8d2477d8, (q31_t)0x38793725, (q31_t)0x8d21b20a, (q31_t)0x38739399, (q31_t)0x8d1eec83, (q31_t)0x386defeb, (q31_t)0x8d1c2742, + (q31_t)0x38684c19, (q31_t)0x8d196249, (q31_t)0x3862a825, (q31_t)0x8d169d96, (q31_t)0x385d040d, (q31_t)0x8d13d92a, (q31_t)0x38575fd4, (q31_t)0x8d111505, + (q31_t)0x3851bb77, (q31_t)0x8d0e5127, (q31_t)0x384c16f7, (q31_t)0x8d0b8d90, (q31_t)0x38467255, (q31_t)0x8d08ca40, (q31_t)0x3840cd90, (q31_t)0x8d060737, + (q31_t)0x383b28a9, (q31_t)0x8d034474, (q31_t)0x3835839f, (q31_t)0x8d0081f9, (q31_t)0x382fde72, (q31_t)0x8cfdbfc4, (q31_t)0x382a3922, (q31_t)0x8cfafdd7, + (q31_t)0x382493b0, (q31_t)0x8cf83c30, (q31_t)0x381eee1b, (q31_t)0x8cf57ad0, (q31_t)0x38194864, (q31_t)0x8cf2b9b8, (q31_t)0x3813a28a, (q31_t)0x8ceff8e6, + (q31_t)0x380dfc8d, (q31_t)0x8ced385b, (q31_t)0x3808566e, (q31_t)0x8cea7818, (q31_t)0x3802b02c, (q31_t)0x8ce7b81b, (q31_t)0x37fd09c8, (q31_t)0x8ce4f865, + (q31_t)0x37f76341, (q31_t)0x8ce238f6, (q31_t)0x37f1bc97, (q31_t)0x8cdf79ce, (q31_t)0x37ec15cb, (q31_t)0x8cdcbaee, (q31_t)0x37e66edd, (q31_t)0x8cd9fc54, + (q31_t)0x37e0c7cc, (q31_t)0x8cd73e01, (q31_t)0x37db2099, (q31_t)0x8cd47ff6, (q31_t)0x37d57943, (q31_t)0x8cd1c231, (q31_t)0x37cfd1cb, (q31_t)0x8ccf04b3, + (q31_t)0x37ca2a30, (q31_t)0x8ccc477d, (q31_t)0x37c48273, (q31_t)0x8cc98a8e, (q31_t)0x37beda93, (q31_t)0x8cc6cde5, (q31_t)0x37b93292, (q31_t)0x8cc41184, + (q31_t)0x37b38a6d, (q31_t)0x8cc1556a, (q31_t)0x37ade227, (q31_t)0x8cbe9996, (q31_t)0x37a839be, (q31_t)0x8cbbde0a, (q31_t)0x37a29132, (q31_t)0x8cb922c6, + (q31_t)0x379ce885, (q31_t)0x8cb667c8, (q31_t)0x37973fb5, (q31_t)0x8cb3ad11, (q31_t)0x379196c3, (q31_t)0x8cb0f2a1, (q31_t)0x378bedae, (q31_t)0x8cae3879, + (q31_t)0x37864477, (q31_t)0x8cab7e98, (q31_t)0x37809b1e, (q31_t)0x8ca8c4fd, (q31_t)0x377af1a3, (q31_t)0x8ca60baa, (q31_t)0x37754806, (q31_t)0x8ca3529f, + (q31_t)0x376f9e46, (q31_t)0x8ca099da, (q31_t)0x3769f464, (q31_t)0x8c9de15c, (q31_t)0x37644a60, (q31_t)0x8c9b2926, (q31_t)0x375ea03a, (q31_t)0x8c987137, + (q31_t)0x3758f5f2, (q31_t)0x8c95b98f, (q31_t)0x37534b87, (q31_t)0x8c93022e, (q31_t)0x374da0fa, (q31_t)0x8c904b14, (q31_t)0x3747f64c, (q31_t)0x8c8d9442, + (q31_t)0x37424b7b, (q31_t)0x8c8addb7, (q31_t)0x373ca088, (q31_t)0x8c882773, (q31_t)0x3736f573, (q31_t)0x8c857176, (q31_t)0x37314a3c, (q31_t)0x8c82bbc0, + (q31_t)0x372b9ee3, (q31_t)0x8c800652, (q31_t)0x3725f367, (q31_t)0x8c7d512b, (q31_t)0x372047ca, (q31_t)0x8c7a9c4b, (q31_t)0x371a9c0b, (q31_t)0x8c77e7b3, + (q31_t)0x3714f02a, (q31_t)0x8c753362, (q31_t)0x370f4427, (q31_t)0x8c727f58, (q31_t)0x37099802, (q31_t)0x8c6fcb95, (q31_t)0x3703ebbb, (q31_t)0x8c6d181a, + (q31_t)0x36fe3f52, (q31_t)0x8c6a64e5, (q31_t)0x36f892c7, (q31_t)0x8c67b1f9, (q31_t)0x36f2e61a, (q31_t)0x8c64ff53, (q31_t)0x36ed394b, (q31_t)0x8c624cf5, + (q31_t)0x36e78c5b, (q31_t)0x8c5f9ade, (q31_t)0x36e1df48, (q31_t)0x8c5ce90e, (q31_t)0x36dc3214, (q31_t)0x8c5a3786, (q31_t)0x36d684be, (q31_t)0x8c578645, + (q31_t)0x36d0d746, (q31_t)0x8c54d54c, (q31_t)0x36cb29ac, (q31_t)0x8c522499, (q31_t)0x36c57bf0, (q31_t)0x8c4f742f, (q31_t)0x36bfce13, (q31_t)0x8c4cc40b, + (q31_t)0x36ba2014, (q31_t)0x8c4a142f, (q31_t)0x36b471f3, (q31_t)0x8c47649a, (q31_t)0x36aec3b0, (q31_t)0x8c44b54d, (q31_t)0x36a9154c, (q31_t)0x8c420647, + (q31_t)0x36a366c6, (q31_t)0x8c3f5788, (q31_t)0x369db81e, (q31_t)0x8c3ca911, (q31_t)0x36980954, (q31_t)0x8c39fae1, (q31_t)0x36925a69, (q31_t)0x8c374cf9, + (q31_t)0x368cab5c, (q31_t)0x8c349f58, (q31_t)0x3686fc2e, (q31_t)0x8c31f1ff, (q31_t)0x36814cde, (q31_t)0x8c2f44ed, (q31_t)0x367b9d6c, (q31_t)0x8c2c9822, + (q31_t)0x3675edd9, (q31_t)0x8c29eb9f, (q31_t)0x36703e24, (q31_t)0x8c273f63, (q31_t)0x366a8e4d, (q31_t)0x8c24936f, (q31_t)0x3664de55, (q31_t)0x8c21e7c2, + (q31_t)0x365f2e3b, (q31_t)0x8c1f3c5d, (q31_t)0x36597e00, (q31_t)0x8c1c913f, (q31_t)0x3653cda3, (q31_t)0x8c19e669, (q31_t)0x364e1d25, (q31_t)0x8c173bda, + (q31_t)0x36486c86, (q31_t)0x8c149192, (q31_t)0x3642bbc4, (q31_t)0x8c11e792, (q31_t)0x363d0ae2, (q31_t)0x8c0f3dda, (q31_t)0x363759de, (q31_t)0x8c0c9469, + (q31_t)0x3631a8b8, (q31_t)0x8c09eb40, (q31_t)0x362bf771, (q31_t)0x8c07425e, (q31_t)0x36264609, (q31_t)0x8c0499c4, (q31_t)0x3620947f, (q31_t)0x8c01f171, + (q31_t)0x361ae2d3, (q31_t)0x8bff4966, (q31_t)0x36153107, (q31_t)0x8bfca1a3, (q31_t)0x360f7f19, (q31_t)0x8bf9fa27, (q31_t)0x3609cd0a, (q31_t)0x8bf752f2, + (q31_t)0x36041ad9, (q31_t)0x8bf4ac05, (q31_t)0x35fe6887, (q31_t)0x8bf20560, (q31_t)0x35f8b614, (q31_t)0x8bef5f02, (q31_t)0x35f3037f, (q31_t)0x8becb8ec, + (q31_t)0x35ed50c9, (q31_t)0x8bea131e, (q31_t)0x35e79df2, (q31_t)0x8be76d97, (q31_t)0x35e1eafa, (q31_t)0x8be4c857, (q31_t)0x35dc37e0, (q31_t)0x8be22360, + (q31_t)0x35d684a6, (q31_t)0x8bdf7eb0, (q31_t)0x35d0d14a, (q31_t)0x8bdcda47, (q31_t)0x35cb1dcc, (q31_t)0x8bda3626, (q31_t)0x35c56a2e, (q31_t)0x8bd7924d, + (q31_t)0x35bfb66e, (q31_t)0x8bd4eebc, (q31_t)0x35ba028e, (q31_t)0x8bd24b72, (q31_t)0x35b44e8c, (q31_t)0x8bcfa870, (q31_t)0x35ae9a69, (q31_t)0x8bcd05b5, + (q31_t)0x35a8e625, (q31_t)0x8bca6343, (q31_t)0x35a331c0, (q31_t)0x8bc7c117, (q31_t)0x359d7d39, (q31_t)0x8bc51f34, (q31_t)0x3597c892, (q31_t)0x8bc27d98, + (q31_t)0x359213c9, (q31_t)0x8bbfdc44, (q31_t)0x358c5ee0, (q31_t)0x8bbd3b38, (q31_t)0x3586a9d5, (q31_t)0x8bba9a73, (q31_t)0x3580f4aa, (q31_t)0x8bb7f9f6, + (q31_t)0x357b3f5d, (q31_t)0x8bb559c1, (q31_t)0x357589f0, (q31_t)0x8bb2b9d4, (q31_t)0x356fd461, (q31_t)0x8bb01a2e, (q31_t)0x356a1eb2, (q31_t)0x8bad7ad0, + (q31_t)0x356468e2, (q31_t)0x8baadbba, (q31_t)0x355eb2f0, (q31_t)0x8ba83cec, (q31_t)0x3558fcde, (q31_t)0x8ba59e65, (q31_t)0x355346ab, (q31_t)0x8ba30026, + (q31_t)0x354d9057, (q31_t)0x8ba0622f, (q31_t)0x3547d9e2, (q31_t)0x8b9dc480, (q31_t)0x3542234c, (q31_t)0x8b9b2718, (q31_t)0x353c6c95, (q31_t)0x8b9889f8, + (q31_t)0x3536b5be, (q31_t)0x8b95ed21, (q31_t)0x3530fec6, (q31_t)0x8b935090, (q31_t)0x352b47ad, (q31_t)0x8b90b448, (q31_t)0x35259073, (q31_t)0x8b8e1848, + (q31_t)0x351fd918, (q31_t)0x8b8b7c8f, (q31_t)0x351a219c, (q31_t)0x8b88e11e, (q31_t)0x35146a00, (q31_t)0x8b8645f5, (q31_t)0x350eb243, (q31_t)0x8b83ab14, + (q31_t)0x3508fa66, (q31_t)0x8b81107b, (q31_t)0x35034267, (q31_t)0x8b7e7629, (q31_t)0x34fd8a48, (q31_t)0x8b7bdc20, (q31_t)0x34f7d208, (q31_t)0x8b79425e, + (q31_t)0x34f219a8, (q31_t)0x8b76a8e4, (q31_t)0x34ec6127, (q31_t)0x8b740fb3, (q31_t)0x34e6a885, (q31_t)0x8b7176c8, (q31_t)0x34e0efc2, (q31_t)0x8b6ede26, + (q31_t)0x34db36df, (q31_t)0x8b6c45cc, (q31_t)0x34d57ddc, (q31_t)0x8b69adba, (q31_t)0x34cfc4b7, (q31_t)0x8b6715ef, (q31_t)0x34ca0b73, (q31_t)0x8b647e6d, + (q31_t)0x34c4520d, (q31_t)0x8b61e733, (q31_t)0x34be9887, (q31_t)0x8b5f5040, (q31_t)0x34b8dee1, (q31_t)0x8b5cb995, (q31_t)0x34b3251a, (q31_t)0x8b5a2333, + (q31_t)0x34ad6b32, (q31_t)0x8b578d18, (q31_t)0x34a7b12a, (q31_t)0x8b54f745, (q31_t)0x34a1f702, (q31_t)0x8b5261ba, (q31_t)0x349c3cb9, (q31_t)0x8b4fcc77, + (q31_t)0x34968250, (q31_t)0x8b4d377c, (q31_t)0x3490c7c6, (q31_t)0x8b4aa2ca, (q31_t)0x348b0d1c, (q31_t)0x8b480e5f, (q31_t)0x34855251, (q31_t)0x8b457a3c, + (q31_t)0x347f9766, (q31_t)0x8b42e661, (q31_t)0x3479dc5b, (q31_t)0x8b4052ce, (q31_t)0x3474212f, (q31_t)0x8b3dbf83, (q31_t)0x346e65e3, (q31_t)0x8b3b2c80, + (q31_t)0x3468aa76, (q31_t)0x8b3899c6, (q31_t)0x3462eee9, (q31_t)0x8b360753, (q31_t)0x345d333c, (q31_t)0x8b337528, (q31_t)0x3457776f, (q31_t)0x8b30e345, + (q31_t)0x3451bb81, (q31_t)0x8b2e51ab, (q31_t)0x344bff73, (q31_t)0x8b2bc058, (q31_t)0x34464345, (q31_t)0x8b292f4e, (q31_t)0x344086f6, (q31_t)0x8b269e8b, + (q31_t)0x343aca87, (q31_t)0x8b240e11, (q31_t)0x34350df8, (q31_t)0x8b217ddf, (q31_t)0x342f5149, (q31_t)0x8b1eedf4, (q31_t)0x3429947a, (q31_t)0x8b1c5e52, + (q31_t)0x3423d78a, (q31_t)0x8b19cef8, (q31_t)0x341e1a7b, (q31_t)0x8b173fe6, (q31_t)0x34185d4b, (q31_t)0x8b14b11d, (q31_t)0x34129ffb, (q31_t)0x8b12229b, + (q31_t)0x340ce28b, (q31_t)0x8b0f9462, (q31_t)0x340724fb, (q31_t)0x8b0d0670, (q31_t)0x3401674a, (q31_t)0x8b0a78c7, (q31_t)0x33fba97a, (q31_t)0x8b07eb66, + (q31_t)0x33f5eb89, (q31_t)0x8b055e4d, (q31_t)0x33f02d79, (q31_t)0x8b02d17c, (q31_t)0x33ea6f48, (q31_t)0x8b0044f3, (q31_t)0x33e4b0f8, (q31_t)0x8afdb8b3, + (q31_t)0x33def287, (q31_t)0x8afb2cbb, (q31_t)0x33d933f7, (q31_t)0x8af8a10b, (q31_t)0x33d37546, (q31_t)0x8af615a3, (q31_t)0x33cdb676, (q31_t)0x8af38a83, + (q31_t)0x33c7f785, (q31_t)0x8af0ffac, (q31_t)0x33c23875, (q31_t)0x8aee751c, (q31_t)0x33bc7944, (q31_t)0x8aebead5, (q31_t)0x33b6b9f4, (q31_t)0x8ae960d6, + (q31_t)0x33b0fa84, (q31_t)0x8ae6d720, (q31_t)0x33ab3af4, (q31_t)0x8ae44db1, (q31_t)0x33a57b44, (q31_t)0x8ae1c48b, (q31_t)0x339fbb74, (q31_t)0x8adf3bad, + (q31_t)0x3399fb85, (q31_t)0x8adcb318, (q31_t)0x33943b75, (q31_t)0x8ada2aca, (q31_t)0x338e7b46, (q31_t)0x8ad7a2c5, (q31_t)0x3388baf7, (q31_t)0x8ad51b08, + (q31_t)0x3382fa88, (q31_t)0x8ad29394, (q31_t)0x337d39f9, (q31_t)0x8ad00c67, (q31_t)0x3377794b, (q31_t)0x8acd8583, (q31_t)0x3371b87d, (q31_t)0x8acafee8, + (q31_t)0x336bf78f, (q31_t)0x8ac87894, (q31_t)0x33663682, (q31_t)0x8ac5f289, (q31_t)0x33607554, (q31_t)0x8ac36cc6, (q31_t)0x335ab407, (q31_t)0x8ac0e74c, + (q31_t)0x3354f29b, (q31_t)0x8abe6219, (q31_t)0x334f310e, (q31_t)0x8abbdd30, (q31_t)0x33496f62, (q31_t)0x8ab9588e, (q31_t)0x3343ad97, (q31_t)0x8ab6d435, + (q31_t)0x333debab, (q31_t)0x8ab45024, (q31_t)0x333829a1, (q31_t)0x8ab1cc5c, (q31_t)0x33326776, (q31_t)0x8aaf48db, (q31_t)0x332ca52c, (q31_t)0x8aacc5a4, + (q31_t)0x3326e2c3, (q31_t)0x8aaa42b4, (q31_t)0x33212039, (q31_t)0x8aa7c00d, (q31_t)0x331b5d91, (q31_t)0x8aa53daf, (q31_t)0x33159ac8, (q31_t)0x8aa2bb99, + (q31_t)0x330fd7e1, (q31_t)0x8aa039cb, (q31_t)0x330a14da, (q31_t)0x8a9db845, (q31_t)0x330451b3, (q31_t)0x8a9b3708, (q31_t)0x32fe8e6d, (q31_t)0x8a98b614, + (q31_t)0x32f8cb07, (q31_t)0x8a963567, (q31_t)0x32f30782, (q31_t)0x8a93b504, (q31_t)0x32ed43de, (q31_t)0x8a9134e8, (q31_t)0x32e7801a, (q31_t)0x8a8eb516, + (q31_t)0x32e1bc36, (q31_t)0x8a8c358b, (q31_t)0x32dbf834, (q31_t)0x8a89b649, (q31_t)0x32d63412, (q31_t)0x8a873750, (q31_t)0x32d06fd0, (q31_t)0x8a84b89e, + (q31_t)0x32caab6f, (q31_t)0x8a823a36, (q31_t)0x32c4e6ef, (q31_t)0x8a7fbc16, (q31_t)0x32bf2250, (q31_t)0x8a7d3e3e, (q31_t)0x32b95d91, (q31_t)0x8a7ac0af, + (q31_t)0x32b398b3, (q31_t)0x8a784368, (q31_t)0x32add3b6, (q31_t)0x8a75c66a, (q31_t)0x32a80e99, (q31_t)0x8a7349b4, (q31_t)0x32a2495d, (q31_t)0x8a70cd47, + (q31_t)0x329c8402, (q31_t)0x8a6e5123, (q31_t)0x3296be88, (q31_t)0x8a6bd547, (q31_t)0x3290f8ef, (q31_t)0x8a6959b3, (q31_t)0x328b3336, (q31_t)0x8a66de68, + (q31_t)0x32856d5e, (q31_t)0x8a646365, (q31_t)0x327fa767, (q31_t)0x8a61e8ab, (q31_t)0x3279e151, (q31_t)0x8a5f6e3a, (q31_t)0x32741b1c, (q31_t)0x8a5cf411, + (q31_t)0x326e54c7, (q31_t)0x8a5a7a31, (q31_t)0x32688e54, (q31_t)0x8a580099, (q31_t)0x3262c7c1, (q31_t)0x8a55874a, (q31_t)0x325d0110, (q31_t)0x8a530e43, + (q31_t)0x32573a3f, (q31_t)0x8a509585, (q31_t)0x3251734f, (q31_t)0x8a4e1d10, (q31_t)0x324bac40, (q31_t)0x8a4ba4e3, (q31_t)0x3245e512, (q31_t)0x8a492cff, + (q31_t)0x32401dc6, (q31_t)0x8a46b564, (q31_t)0x323a565a, (q31_t)0x8a443e11, (q31_t)0x32348ecf, (q31_t)0x8a41c706, (q31_t)0x322ec725, (q31_t)0x8a3f5045, + (q31_t)0x3228ff5c, (q31_t)0x8a3cd9cc, (q31_t)0x32233775, (q31_t)0x8a3a639b, (q31_t)0x321d6f6e, (q31_t)0x8a37edb3, (q31_t)0x3217a748, (q31_t)0x8a357814, + (q31_t)0x3211df04, (q31_t)0x8a3302be, (q31_t)0x320c16a1, (q31_t)0x8a308db0, (q31_t)0x32064e1e, (q31_t)0x8a2e18eb, (q31_t)0x3200857d, (q31_t)0x8a2ba46e, + (q31_t)0x31fabcbd, (q31_t)0x8a29303b, (q31_t)0x31f4f3df, (q31_t)0x8a26bc50, (q31_t)0x31ef2ae1, (q31_t)0x8a2448ad, (q31_t)0x31e961c5, (q31_t)0x8a21d554, + (q31_t)0x31e39889, (q31_t)0x8a1f6243, (q31_t)0x31ddcf30, (q31_t)0x8a1cef7a, (q31_t)0x31d805b7, (q31_t)0x8a1a7cfb, (q31_t)0x31d23c1f, (q31_t)0x8a180ac4, + (q31_t)0x31cc7269, (q31_t)0x8a1598d6, (q31_t)0x31c6a894, (q31_t)0x8a132731, (q31_t)0x31c0dea1, (q31_t)0x8a10b5d4, (q31_t)0x31bb148f, (q31_t)0x8a0e44c0, + (q31_t)0x31b54a5e, (q31_t)0x8a0bd3f5, (q31_t)0x31af800e, (q31_t)0x8a096373, (q31_t)0x31a9b5a0, (q31_t)0x8a06f339, (q31_t)0x31a3eb13, (q31_t)0x8a048348, + (q31_t)0x319e2067, (q31_t)0x8a0213a0, (q31_t)0x3198559d, (q31_t)0x89ffa441, (q31_t)0x31928ab4, (q31_t)0x89fd352b, (q31_t)0x318cbfad, (q31_t)0x89fac65d, + (q31_t)0x3186f487, (q31_t)0x89f857d8, (q31_t)0x31812943, (q31_t)0x89f5e99c, (q31_t)0x317b5de0, (q31_t)0x89f37ba9, (q31_t)0x3175925e, (q31_t)0x89f10dff, + (q31_t)0x316fc6be, (q31_t)0x89eea09d, (q31_t)0x3169fb00, (q31_t)0x89ec3384, (q31_t)0x31642f23, (q31_t)0x89e9c6b4, (q31_t)0x315e6328, (q31_t)0x89e75a2d, + (q31_t)0x3158970e, (q31_t)0x89e4edef, (q31_t)0x3152cad5, (q31_t)0x89e281fa, (q31_t)0x314cfe7f, (q31_t)0x89e0164d, (q31_t)0x31473209, (q31_t)0x89ddaae9, + (q31_t)0x31416576, (q31_t)0x89db3fcf, (q31_t)0x313b98c4, (q31_t)0x89d8d4fd, (q31_t)0x3135cbf4, (q31_t)0x89d66a74, (q31_t)0x312fff05, (q31_t)0x89d40033, + (q31_t)0x312a31f8, (q31_t)0x89d1963c, (q31_t)0x312464cd, (q31_t)0x89cf2c8e, (q31_t)0x311e9783, (q31_t)0x89ccc328, (q31_t)0x3118ca1b, (q31_t)0x89ca5a0c, + (q31_t)0x3112fc95, (q31_t)0x89c7f138, (q31_t)0x310d2ef0, (q31_t)0x89c588ae, (q31_t)0x3107612e, (q31_t)0x89c3206c, (q31_t)0x3101934d, (q31_t)0x89c0b873, + (q31_t)0x30fbc54d, (q31_t)0x89be50c3, (q31_t)0x30f5f730, (q31_t)0x89bbe95c, (q31_t)0x30f028f4, (q31_t)0x89b9823e, (q31_t)0x30ea5a9a, (q31_t)0x89b71b69, + (q31_t)0x30e48c22, (q31_t)0x89b4b4dd, (q31_t)0x30debd8c, (q31_t)0x89b24e9a, (q31_t)0x30d8eed8, (q31_t)0x89afe8a0, (q31_t)0x30d32006, (q31_t)0x89ad82ef, + (q31_t)0x30cd5115, (q31_t)0x89ab1d87, (q31_t)0x30c78206, (q31_t)0x89a8b868, (q31_t)0x30c1b2da, (q31_t)0x89a65391, (q31_t)0x30bbe38f, (q31_t)0x89a3ef04, + (q31_t)0x30b61426, (q31_t)0x89a18ac0, (q31_t)0x30b0449f, (q31_t)0x899f26c5, (q31_t)0x30aa74fa, (q31_t)0x899cc313, (q31_t)0x30a4a537, (q31_t)0x899a5faa, + (q31_t)0x309ed556, (q31_t)0x8997fc8a, (q31_t)0x30990557, (q31_t)0x899599b3, (q31_t)0x3093353a, (q31_t)0x89933725, (q31_t)0x308d64ff, (q31_t)0x8990d4e0, + (q31_t)0x308794a6, (q31_t)0x898e72e4, (q31_t)0x3081c42f, (q31_t)0x898c1131, (q31_t)0x307bf39b, (q31_t)0x8989afc8, (q31_t)0x307622e8, (q31_t)0x89874ea7, + (q31_t)0x30705217, (q31_t)0x8984edcf, (q31_t)0x306a8129, (q31_t)0x89828d41, (q31_t)0x3064b01d, (q31_t)0x89802cfc, (q31_t)0x305edef3, (q31_t)0x897dccff, + (q31_t)0x30590dab, (q31_t)0x897b6d4c, (q31_t)0x30533c45, (q31_t)0x89790de2, (q31_t)0x304d6ac1, (q31_t)0x8976aec1, (q31_t)0x30479920, (q31_t)0x89744fe9, + (q31_t)0x3041c761, (q31_t)0x8971f15a, (q31_t)0x303bf584, (q31_t)0x896f9315, (q31_t)0x30362389, (q31_t)0x896d3518, (q31_t)0x30305171, (q31_t)0x896ad765, + (q31_t)0x302a7f3a, (q31_t)0x896879fb, (q31_t)0x3024ace6, (q31_t)0x89661cda, (q31_t)0x301eda75, (q31_t)0x8963c002, (q31_t)0x301907e6, (q31_t)0x89616373, + (q31_t)0x30133539, (q31_t)0x895f072e, (q31_t)0x300d626e, (q31_t)0x895cab31, (q31_t)0x30078f86, (q31_t)0x895a4f7e, (q31_t)0x3001bc80, (q31_t)0x8957f414, + (q31_t)0x2ffbe95d, (q31_t)0x895598f3, (q31_t)0x2ff6161c, (q31_t)0x89533e1c, (q31_t)0x2ff042bd, (q31_t)0x8950e38e, (q31_t)0x2fea6f41, (q31_t)0x894e8948, + (q31_t)0x2fe49ba7, (q31_t)0x894c2f4c, (q31_t)0x2fdec7f0, (q31_t)0x8949d59a, (q31_t)0x2fd8f41b, (q31_t)0x89477c30, (q31_t)0x2fd32028, (q31_t)0x89452310, + (q31_t)0x2fcd4c19, (q31_t)0x8942ca39, (q31_t)0x2fc777eb, (q31_t)0x894071ab, (q31_t)0x2fc1a3a0, (q31_t)0x893e1967, (q31_t)0x2fbbcf38, (q31_t)0x893bc16b, + (q31_t)0x2fb5fab2, (q31_t)0x893969b9, (q31_t)0x2fb0260f, (q31_t)0x89371250, (q31_t)0x2faa514f, (q31_t)0x8934bb31, (q31_t)0x2fa47c71, (q31_t)0x8932645b, + (q31_t)0x2f9ea775, (q31_t)0x89300dce, (q31_t)0x2f98d25d, (q31_t)0x892db78a, (q31_t)0x2f92fd26, (q31_t)0x892b6190, (q31_t)0x2f8d27d3, (q31_t)0x89290bdf, + (q31_t)0x2f875262, (q31_t)0x8926b677, (q31_t)0x2f817cd4, (q31_t)0x89246159, (q31_t)0x2f7ba729, (q31_t)0x89220c84, (q31_t)0x2f75d160, (q31_t)0x891fb7f8, + (q31_t)0x2f6ffb7a, (q31_t)0x891d63b5, (q31_t)0x2f6a2577, (q31_t)0x891b0fbc, (q31_t)0x2f644f56, (q31_t)0x8918bc0c, (q31_t)0x2f5e7919, (q31_t)0x891668a6, + (q31_t)0x2f58a2be, (q31_t)0x89141589, (q31_t)0x2f52cc46, (q31_t)0x8911c2b5, (q31_t)0x2f4cf5b0, (q31_t)0x890f702b, (q31_t)0x2f471efe, (q31_t)0x890d1dea, + (q31_t)0x2f41482e, (q31_t)0x890acbf2, (q31_t)0x2f3b7141, (q31_t)0x89087a44, (q31_t)0x2f359a37, (q31_t)0x890628df, (q31_t)0x2f2fc310, (q31_t)0x8903d7c4, + (q31_t)0x2f29ebcc, (q31_t)0x890186f2, (q31_t)0x2f24146b, (q31_t)0x88ff3669, (q31_t)0x2f1e3ced, (q31_t)0x88fce62a, (q31_t)0x2f186551, (q31_t)0x88fa9634, + (q31_t)0x2f128d99, (q31_t)0x88f84687, (q31_t)0x2f0cb5c3, (q31_t)0x88f5f724, (q31_t)0x2f06ddd1, (q31_t)0x88f3a80b, (q31_t)0x2f0105c1, (q31_t)0x88f1593b, + (q31_t)0x2efb2d95, (q31_t)0x88ef0ab4, (q31_t)0x2ef5554b, (q31_t)0x88ecbc77, (q31_t)0x2eef7ce5, (q31_t)0x88ea6e83, (q31_t)0x2ee9a461, (q31_t)0x88e820d9, + (q31_t)0x2ee3cbc1, (q31_t)0x88e5d378, (q31_t)0x2eddf304, (q31_t)0x88e38660, (q31_t)0x2ed81a29, (q31_t)0x88e13992, (q31_t)0x2ed24132, (q31_t)0x88deed0e, + (q31_t)0x2ecc681e, (q31_t)0x88dca0d3, (q31_t)0x2ec68eed, (q31_t)0x88da54e1, (q31_t)0x2ec0b5a0, (q31_t)0x88d8093a, (q31_t)0x2ebadc35, (q31_t)0x88d5bddb, + (q31_t)0x2eb502ae, (q31_t)0x88d372c6, (q31_t)0x2eaf290a, (q31_t)0x88d127fb, (q31_t)0x2ea94f49, (q31_t)0x88cedd79, (q31_t)0x2ea3756b, (q31_t)0x88cc9340, + (q31_t)0x2e9d9b70, (q31_t)0x88ca4951, (q31_t)0x2e97c159, (q31_t)0x88c7ffac, (q31_t)0x2e91e725, (q31_t)0x88c5b650, (q31_t)0x2e8c0cd4, (q31_t)0x88c36d3e, + (q31_t)0x2e863267, (q31_t)0x88c12475, (q31_t)0x2e8057dd, (q31_t)0x88bedbf6, (q31_t)0x2e7a7d36, (q31_t)0x88bc93c0, (q31_t)0x2e74a272, (q31_t)0x88ba4bd4, + (q31_t)0x2e6ec792, (q31_t)0x88b80432, (q31_t)0x2e68ec95, (q31_t)0x88b5bcd9, (q31_t)0x2e63117c, (q31_t)0x88b375ca, (q31_t)0x2e5d3646, (q31_t)0x88b12f04, + (q31_t)0x2e575af3, (q31_t)0x88aee888, (q31_t)0x2e517f84, (q31_t)0x88aca255, (q31_t)0x2e4ba3f8, (q31_t)0x88aa5c6c, (q31_t)0x2e45c850, (q31_t)0x88a816cd, + (q31_t)0x2e3fec8b, (q31_t)0x88a5d177, (q31_t)0x2e3a10aa, (q31_t)0x88a38c6b, (q31_t)0x2e3434ac, (q31_t)0x88a147a9, (q31_t)0x2e2e5891, (q31_t)0x889f0330, + (q31_t)0x2e287c5a, (q31_t)0x889cbf01, (q31_t)0x2e22a007, (q31_t)0x889a7b1b, (q31_t)0x2e1cc397, (q31_t)0x88983780, (q31_t)0x2e16e70b, (q31_t)0x8895f42d, + (q31_t)0x2e110a62, (q31_t)0x8893b125, (q31_t)0x2e0b2d9d, (q31_t)0x88916e66, (q31_t)0x2e0550bb, (q31_t)0x888f2bf1, (q31_t)0x2dff73bd, (q31_t)0x888ce9c5, + (q31_t)0x2df996a3, (q31_t)0x888aa7e3, (q31_t)0x2df3b96c, (q31_t)0x8888664b, (q31_t)0x2deddc19, (q31_t)0x888624fd, (q31_t)0x2de7feaa, (q31_t)0x8883e3f8, + (q31_t)0x2de2211e, (q31_t)0x8881a33d, (q31_t)0x2ddc4376, (q31_t)0x887f62cb, (q31_t)0x2dd665b2, (q31_t)0x887d22a4, (q31_t)0x2dd087d1, (q31_t)0x887ae2c6, + (q31_t)0x2dcaa9d5, (q31_t)0x8878a332, (q31_t)0x2dc4cbbc, (q31_t)0x887663e7, (q31_t)0x2dbeed86, (q31_t)0x887424e7, (q31_t)0x2db90f35, (q31_t)0x8871e630, + (q31_t)0x2db330c7, (q31_t)0x886fa7c2, (q31_t)0x2dad523d, (q31_t)0x886d699f, (q31_t)0x2da77397, (q31_t)0x886b2bc5, (q31_t)0x2da194d5, (q31_t)0x8868ee35, + (q31_t)0x2d9bb5f6, (q31_t)0x8866b0ef, (q31_t)0x2d95d6fc, (q31_t)0x886473f2, (q31_t)0x2d8ff7e5, (q31_t)0x88623740, (q31_t)0x2d8a18b3, (q31_t)0x885ffad7, + (q31_t)0x2d843964, (q31_t)0x885dbeb8, (q31_t)0x2d7e59f9, (q31_t)0x885b82e3, (q31_t)0x2d787a72, (q31_t)0x88594757, (q31_t)0x2d729acf, (q31_t)0x88570c16, + (q31_t)0x2d6cbb10, (q31_t)0x8854d11e, (q31_t)0x2d66db35, (q31_t)0x88529670, (q31_t)0x2d60fb3e, (q31_t)0x88505c0b, (q31_t)0x2d5b1b2b, (q31_t)0x884e21f1, + (q31_t)0x2d553afc, (q31_t)0x884be821, (q31_t)0x2d4f5ab1, (q31_t)0x8849ae9a, (q31_t)0x2d497a4a, (q31_t)0x8847755d, (q31_t)0x2d4399c7, (q31_t)0x88453c6a, + (q31_t)0x2d3db928, (q31_t)0x884303c1, (q31_t)0x2d37d86d, (q31_t)0x8840cb61, (q31_t)0x2d31f797, (q31_t)0x883e934c, (q31_t)0x2d2c16a4, (q31_t)0x883c5b81, + (q31_t)0x2d263596, (q31_t)0x883a23ff, (q31_t)0x2d20546b, (q31_t)0x8837ecc7, (q31_t)0x2d1a7325, (q31_t)0x8835b5d9, (q31_t)0x2d1491c4, (q31_t)0x88337f35, + (q31_t)0x2d0eb046, (q31_t)0x883148db, (q31_t)0x2d08ceac, (q31_t)0x882f12cb, (q31_t)0x2d02ecf7, (q31_t)0x882cdd04, (q31_t)0x2cfd0b26, (q31_t)0x882aa788, + (q31_t)0x2cf72939, (q31_t)0x88287256, (q31_t)0x2cf14731, (q31_t)0x88263d6d, (q31_t)0x2ceb650d, (q31_t)0x882408ce, (q31_t)0x2ce582cd, (q31_t)0x8821d47a, + (q31_t)0x2cdfa071, (q31_t)0x881fa06f, (q31_t)0x2cd9bdfa, (q31_t)0x881d6cae, (q31_t)0x2cd3db67, (q31_t)0x881b3937, (q31_t)0x2ccdf8b8, (q31_t)0x8819060a, + (q31_t)0x2cc815ee, (q31_t)0x8816d327, (q31_t)0x2cc23308, (q31_t)0x8814a08f, (q31_t)0x2cbc5006, (q31_t)0x88126e40, (q31_t)0x2cb66ce9, (q31_t)0x88103c3b, + (q31_t)0x2cb089b1, (q31_t)0x880e0a7f, (q31_t)0x2caaa65c, (q31_t)0x880bd90e, (q31_t)0x2ca4c2ed, (q31_t)0x8809a7e7, (q31_t)0x2c9edf61, (q31_t)0x8807770a, + (q31_t)0x2c98fbba, (q31_t)0x88054677, (q31_t)0x2c9317f8, (q31_t)0x8803162e, (q31_t)0x2c8d341a, (q31_t)0x8800e62f, (q31_t)0x2c875021, (q31_t)0x87feb67a, + (q31_t)0x2c816c0c, (q31_t)0x87fc870f, (q31_t)0x2c7b87dc, (q31_t)0x87fa57ee, (q31_t)0x2c75a390, (q31_t)0x87f82917, (q31_t)0x2c6fbf29, (q31_t)0x87f5fa8b, + (q31_t)0x2c69daa6, (q31_t)0x87f3cc48, (q31_t)0x2c63f609, (q31_t)0x87f19e4f, (q31_t)0x2c5e114f, (q31_t)0x87ef70a0, (q31_t)0x2c582c7b, (q31_t)0x87ed433c, + (q31_t)0x2c52478a, (q31_t)0x87eb1621, (q31_t)0x2c4c627f, (q31_t)0x87e8e950, (q31_t)0x2c467d58, (q31_t)0x87e6bcca, (q31_t)0x2c409816, (q31_t)0x87e4908e, + (q31_t)0x2c3ab2b9, (q31_t)0x87e2649b, (q31_t)0x2c34cd40, (q31_t)0x87e038f3, (q31_t)0x2c2ee7ad, (q31_t)0x87de0d95, (q31_t)0x2c2901fd, (q31_t)0x87dbe281, + (q31_t)0x2c231c33, (q31_t)0x87d9b7b7, (q31_t)0x2c1d364e, (q31_t)0x87d78d38, (q31_t)0x2c17504d, (q31_t)0x87d56302, (q31_t)0x2c116a31, (q31_t)0x87d33916, + (q31_t)0x2c0b83fa, (q31_t)0x87d10f75, (q31_t)0x2c059da7, (q31_t)0x87cee61e, (q31_t)0x2bffb73a, (q31_t)0x87ccbd11, (q31_t)0x2bf9d0b1, (q31_t)0x87ca944e, + (q31_t)0x2bf3ea0d, (q31_t)0x87c86bd5, (q31_t)0x2bee034e, (q31_t)0x87c643a6, (q31_t)0x2be81c74, (q31_t)0x87c41bc2, (q31_t)0x2be2357f, (q31_t)0x87c1f427, + (q31_t)0x2bdc4e6f, (q31_t)0x87bfccd7, (q31_t)0x2bd66744, (q31_t)0x87bda5d1, (q31_t)0x2bd07ffe, (q31_t)0x87bb7f16, (q31_t)0x2bca989d, (q31_t)0x87b958a4, + (q31_t)0x2bc4b120, (q31_t)0x87b7327d, (q31_t)0x2bbec989, (q31_t)0x87b50c9f, (q31_t)0x2bb8e1d7, (q31_t)0x87b2e70c, (q31_t)0x2bb2fa0a, (q31_t)0x87b0c1c4, + (q31_t)0x2bad1221, (q31_t)0x87ae9cc5, (q31_t)0x2ba72a1e, (q31_t)0x87ac7811, (q31_t)0x2ba14200, (q31_t)0x87aa53a6, (q31_t)0x2b9b59c7, (q31_t)0x87a82f87, + (q31_t)0x2b957173, (q31_t)0x87a60bb1, (q31_t)0x2b8f8905, (q31_t)0x87a3e825, (q31_t)0x2b89a07b, (q31_t)0x87a1c4e4, (q31_t)0x2b83b7d7, (q31_t)0x879fa1ed, + (q31_t)0x2b7dcf17, (q31_t)0x879d7f41, (q31_t)0x2b77e63d, (q31_t)0x879b5cde, (q31_t)0x2b71fd48, (q31_t)0x87993ac6, (q31_t)0x2b6c1438, (q31_t)0x879718f8, + (q31_t)0x2b662b0e, (q31_t)0x8794f774, (q31_t)0x2b6041c9, (q31_t)0x8792d63b, (q31_t)0x2b5a5868, (q31_t)0x8790b54c, (q31_t)0x2b546eee, (q31_t)0x878e94a7, + (q31_t)0x2b4e8558, (q31_t)0x878c744d, (q31_t)0x2b489ba8, (q31_t)0x878a543d, (q31_t)0x2b42b1dd, (q31_t)0x87883477, (q31_t)0x2b3cc7f7, (q31_t)0x878614fb, + (q31_t)0x2b36ddf7, (q31_t)0x8783f5ca, (q31_t)0x2b30f3dc, (q31_t)0x8781d6e3, (q31_t)0x2b2b09a6, (q31_t)0x877fb846, (q31_t)0x2b251f56, (q31_t)0x877d99f4, + (q31_t)0x2b1f34eb, (q31_t)0x877b7bec, (q31_t)0x2b194a66, (q31_t)0x87795e2f, (q31_t)0x2b135fc6, (q31_t)0x877740bb, (q31_t)0x2b0d750b, (q31_t)0x87752392, + (q31_t)0x2b078a36, (q31_t)0x877306b4, (q31_t)0x2b019f46, (q31_t)0x8770ea20, (q31_t)0x2afbb43c, (q31_t)0x876ecdd6, (q31_t)0x2af5c917, (q31_t)0x876cb1d6, + (q31_t)0x2aefddd8, (q31_t)0x876a9621, (q31_t)0x2ae9f27e, (q31_t)0x87687ab7, (q31_t)0x2ae4070a, (q31_t)0x87665f96, (q31_t)0x2ade1b7c, (q31_t)0x876444c1, + (q31_t)0x2ad82fd2, (q31_t)0x87622a35, (q31_t)0x2ad2440f, (q31_t)0x87600ff4, (q31_t)0x2acc5831, (q31_t)0x875df5fd, (q31_t)0x2ac66c39, (q31_t)0x875bdc51, + (q31_t)0x2ac08026, (q31_t)0x8759c2ef, (q31_t)0x2aba93f9, (q31_t)0x8757a9d8, (q31_t)0x2ab4a7b1, (q31_t)0x8755910b, (q31_t)0x2aaebb50, (q31_t)0x87537888, + (q31_t)0x2aa8ced3, (q31_t)0x87516050, (q31_t)0x2aa2e23d, (q31_t)0x874f4862, (q31_t)0x2a9cf58c, (q31_t)0x874d30bf, (q31_t)0x2a9708c1, (q31_t)0x874b1966, + (q31_t)0x2a911bdc, (q31_t)0x87490258, (q31_t)0x2a8b2edc, (q31_t)0x8746eb94, (q31_t)0x2a8541c3, (q31_t)0x8744d51b, (q31_t)0x2a7f548e, (q31_t)0x8742beec, + (q31_t)0x2a796740, (q31_t)0x8740a907, (q31_t)0x2a7379d8, (q31_t)0x873e936d, (q31_t)0x2a6d8c55, (q31_t)0x873c7e1e, (q31_t)0x2a679eb8, (q31_t)0x873a6919, + (q31_t)0x2a61b101, (q31_t)0x8738545e, (q31_t)0x2a5bc330, (q31_t)0x87363fee, (q31_t)0x2a55d545, (q31_t)0x87342bc9, (q31_t)0x2a4fe740, (q31_t)0x873217ee, + (q31_t)0x2a49f920, (q31_t)0x8730045d, (q31_t)0x2a440ae7, (q31_t)0x872df117, (q31_t)0x2a3e1c93, (q31_t)0x872bde1c, (q31_t)0x2a382e25, (q31_t)0x8729cb6b, + (q31_t)0x2a323f9e, (q31_t)0x8727b905, (q31_t)0x2a2c50fc, (q31_t)0x8725a6e9, (q31_t)0x2a266240, (q31_t)0x87239518, (q31_t)0x2a20736a, (q31_t)0x87218391, + (q31_t)0x2a1a847b, (q31_t)0x871f7255, (q31_t)0x2a149571, (q31_t)0x871d6163, (q31_t)0x2a0ea64d, (q31_t)0x871b50bc, (q31_t)0x2a08b710, (q31_t)0x87194060, + (q31_t)0x2a02c7b8, (q31_t)0x8717304e, (q31_t)0x29fcd847, (q31_t)0x87152087, (q31_t)0x29f6e8bb, (q31_t)0x8713110a, (q31_t)0x29f0f916, (q31_t)0x871101d8, + (q31_t)0x29eb0957, (q31_t)0x870ef2f1, (q31_t)0x29e5197e, (q31_t)0x870ce454, (q31_t)0x29df298b, (q31_t)0x870ad602, (q31_t)0x29d9397f, (q31_t)0x8708c7fa, + (q31_t)0x29d34958, (q31_t)0x8706ba3d, (q31_t)0x29cd5918, (q31_t)0x8704acca, (q31_t)0x29c768be, (q31_t)0x87029fa3, (q31_t)0x29c1784a, (q31_t)0x870092c5, + (q31_t)0x29bb87bc, (q31_t)0x86fe8633, (q31_t)0x29b59715, (q31_t)0x86fc79eb, (q31_t)0x29afa654, (q31_t)0x86fa6dee, (q31_t)0x29a9b579, (q31_t)0x86f8623b, + (q31_t)0x29a3c485, (q31_t)0x86f656d3, (q31_t)0x299dd377, (q31_t)0x86f44bb6, (q31_t)0x2997e24f, (q31_t)0x86f240e3, (q31_t)0x2991f10e, (q31_t)0x86f0365c, + (q31_t)0x298bffb2, (q31_t)0x86ee2c1e, (q31_t)0x29860e3e, (q31_t)0x86ec222c, (q31_t)0x29801caf, (q31_t)0x86ea1884, (q31_t)0x297a2b07, (q31_t)0x86e80f27, + (q31_t)0x29743946, (q31_t)0x86e60614, (q31_t)0x296e476b, (q31_t)0x86e3fd4c, (q31_t)0x29685576, (q31_t)0x86e1f4cf, (q31_t)0x29626368, (q31_t)0x86dfec9d, + (q31_t)0x295c7140, (q31_t)0x86dde4b5, (q31_t)0x29567eff, (q31_t)0x86dbdd18, (q31_t)0x29508ca4, (q31_t)0x86d9d5c6, (q31_t)0x294a9a30, (q31_t)0x86d7cebf, + (q31_t)0x2944a7a2, (q31_t)0x86d5c802, (q31_t)0x293eb4fb, (q31_t)0x86d3c190, (q31_t)0x2938c23a, (q31_t)0x86d1bb69, (q31_t)0x2932cf60, (q31_t)0x86cfb58c, + (q31_t)0x292cdc6d, (q31_t)0x86cdaffa, (q31_t)0x2926e960, (q31_t)0x86cbaab3, (q31_t)0x2920f63a, (q31_t)0x86c9a5b7, (q31_t)0x291b02fa, (q31_t)0x86c7a106, + (q31_t)0x29150fa1, (q31_t)0x86c59c9f, (q31_t)0x290f1c2f, (q31_t)0x86c39883, (q31_t)0x290928a3, (q31_t)0x86c194b2, (q31_t)0x290334ff, (q31_t)0x86bf912c, + (q31_t)0x28fd4140, (q31_t)0x86bd8df0, (q31_t)0x28f74d69, (q31_t)0x86bb8b00, (q31_t)0x28f15978, (q31_t)0x86b9885a, (q31_t)0x28eb656e, (q31_t)0x86b785ff, + (q31_t)0x28e5714b, (q31_t)0x86b583ee, (q31_t)0x28df7d0e, (q31_t)0x86b38229, (q31_t)0x28d988b8, (q31_t)0x86b180ae, (q31_t)0x28d3944a, (q31_t)0x86af7f7e, + (q31_t)0x28cd9fc1, (q31_t)0x86ad7e99, (q31_t)0x28c7ab20, (q31_t)0x86ab7dff, (q31_t)0x28c1b666, (q31_t)0x86a97db0, (q31_t)0x28bbc192, (q31_t)0x86a77dab, + (q31_t)0x28b5cca5, (q31_t)0x86a57df2, (q31_t)0x28afd7a0, (q31_t)0x86a37e83, (q31_t)0x28a9e281, (q31_t)0x86a17f5f, (q31_t)0x28a3ed49, (q31_t)0x869f8086, + (q31_t)0x289df7f8, (q31_t)0x869d81f8, (q31_t)0x2898028e, (q31_t)0x869b83b4, (q31_t)0x28920d0a, (q31_t)0x869985bc, (q31_t)0x288c176e, (q31_t)0x8697880f, + (q31_t)0x288621b9, (q31_t)0x86958aac, (q31_t)0x28802beb, (q31_t)0x86938d94, (q31_t)0x287a3604, (q31_t)0x869190c7, (q31_t)0x28744004, (q31_t)0x868f9445, + (q31_t)0x286e49ea, (q31_t)0x868d980e, (q31_t)0x286853b8, (q31_t)0x868b9c22, (q31_t)0x28625d6d, (q31_t)0x8689a081, (q31_t)0x285c670a, (q31_t)0x8687a52b, + (q31_t)0x2856708d, (q31_t)0x8685aa20, (q31_t)0x285079f7, (q31_t)0x8683af5f, (q31_t)0x284a8349, (q31_t)0x8681b4ea, (q31_t)0x28448c81, (q31_t)0x867fbabf, + (q31_t)0x283e95a1, (q31_t)0x867dc0e0, (q31_t)0x28389ea8, (q31_t)0x867bc74b, (q31_t)0x2832a796, (q31_t)0x8679ce01, (q31_t)0x282cb06c, (q31_t)0x8677d503, + (q31_t)0x2826b928, (q31_t)0x8675dc4f, (q31_t)0x2820c1cc, (q31_t)0x8673e3e6, (q31_t)0x281aca57, (q31_t)0x8671ebc8, (q31_t)0x2814d2c9, (q31_t)0x866ff3f6, + (q31_t)0x280edb23, (q31_t)0x866dfc6e, (q31_t)0x2808e364, (q31_t)0x866c0531, (q31_t)0x2802eb8c, (q31_t)0x866a0e3f, (q31_t)0x27fcf39c, (q31_t)0x86681798, + (q31_t)0x27f6fb92, (q31_t)0x8666213c, (q31_t)0x27f10371, (q31_t)0x86642b2c, (q31_t)0x27eb0b36, (q31_t)0x86623566, (q31_t)0x27e512e3, (q31_t)0x86603feb, + (q31_t)0x27df1a77, (q31_t)0x865e4abb, (q31_t)0x27d921f3, (q31_t)0x865c55d7, (q31_t)0x27d32956, (q31_t)0x865a613d, (q31_t)0x27cd30a1, (q31_t)0x86586cee, + (q31_t)0x27c737d3, (q31_t)0x865678eb, (q31_t)0x27c13eec, (q31_t)0x86548532, (q31_t)0x27bb45ed, (q31_t)0x865291c4, (q31_t)0x27b54cd6, (q31_t)0x86509ea2, + (q31_t)0x27af53a6, (q31_t)0x864eabcb, (q31_t)0x27a95a5d, (q31_t)0x864cb93e, (q31_t)0x27a360fc, (q31_t)0x864ac6fd, (q31_t)0x279d6783, (q31_t)0x8648d507, + (q31_t)0x27976df1, (q31_t)0x8646e35c, (q31_t)0x27917447, (q31_t)0x8644f1fc, (q31_t)0x278b7a84, (q31_t)0x864300e7, (q31_t)0x278580a9, (q31_t)0x8641101d, + (q31_t)0x277f86b5, (q31_t)0x863f1f9e, (q31_t)0x27798caa, (q31_t)0x863d2f6b, (q31_t)0x27739285, (q31_t)0x863b3f82, (q31_t)0x276d9849, (q31_t)0x86394fe5, + (q31_t)0x27679df4, (q31_t)0x86376092, (q31_t)0x2761a387, (q31_t)0x8635718b, (q31_t)0x275ba901, (q31_t)0x863382cf, (q31_t)0x2755ae64, (q31_t)0x8631945e, + (q31_t)0x274fb3ae, (q31_t)0x862fa638, (q31_t)0x2749b8e0, (q31_t)0x862db85e, (q31_t)0x2743bdf9, (q31_t)0x862bcace, (q31_t)0x273dc2fa, (q31_t)0x8629dd8a, + (q31_t)0x2737c7e3, (q31_t)0x8627f091, (q31_t)0x2731ccb4, (q31_t)0x862603e3, (q31_t)0x272bd16d, (q31_t)0x86241780, (q31_t)0x2725d60e, (q31_t)0x86222b68, + (q31_t)0x271fda96, (q31_t)0x86203f9c, (q31_t)0x2719df06, (q31_t)0x861e541a, (q31_t)0x2713e35f, (q31_t)0x861c68e4, (q31_t)0x270de79f, (q31_t)0x861a7df9, + (q31_t)0x2707ebc7, (q31_t)0x86189359, (q31_t)0x2701efd7, (q31_t)0x8616a905, (q31_t)0x26fbf3ce, (q31_t)0x8614befb, (q31_t)0x26f5f7ae, (q31_t)0x8612d53d, + (q31_t)0x26effb76, (q31_t)0x8610ebca, (q31_t)0x26e9ff26, (q31_t)0x860f02a3, (q31_t)0x26e402bd, (q31_t)0x860d19c6, (q31_t)0x26de063d, (q31_t)0x860b3135, + (q31_t)0x26d809a5, (q31_t)0x860948ef, (q31_t)0x26d20cf5, (q31_t)0x860760f4, (q31_t)0x26cc102d, (q31_t)0x86057944, (q31_t)0x26c6134d, (q31_t)0x860391e0, + (q31_t)0x26c01655, (q31_t)0x8601aac7, (q31_t)0x26ba1945, (q31_t)0x85ffc3f9, (q31_t)0x26b41c1d, (q31_t)0x85fddd76, (q31_t)0x26ae1edd, (q31_t)0x85fbf73f, + (q31_t)0x26a82186, (q31_t)0x85fa1153, (q31_t)0x26a22416, (q31_t)0x85f82bb2, (q31_t)0x269c268f, (q31_t)0x85f6465c, (q31_t)0x269628f0, (q31_t)0x85f46152, + (q31_t)0x26902b39, (q31_t)0x85f27c93, (q31_t)0x268a2d6b, (q31_t)0x85f09820, (q31_t)0x26842f84, (q31_t)0x85eeb3f7, (q31_t)0x267e3186, (q31_t)0x85ecd01a, + (q31_t)0x26783370, (q31_t)0x85eaec88, (q31_t)0x26723543, (q31_t)0x85e90942, (q31_t)0x266c36fe, (q31_t)0x85e72647, (q31_t)0x266638a1, (q31_t)0x85e54397, + (q31_t)0x26603a2c, (q31_t)0x85e36132, (q31_t)0x265a3b9f, (q31_t)0x85e17f19, (q31_t)0x26543cfb, (q31_t)0x85df9d4b, (q31_t)0x264e3e40, (q31_t)0x85ddbbc9, + (q31_t)0x26483f6c, (q31_t)0x85dbda91, (q31_t)0x26424082, (q31_t)0x85d9f9a5, (q31_t)0x263c417f, (q31_t)0x85d81905, (q31_t)0x26364265, (q31_t)0x85d638b0, + (q31_t)0x26304333, (q31_t)0x85d458a6, (q31_t)0x262a43ea, (q31_t)0x85d278e7, (q31_t)0x26244489, (q31_t)0x85d09974, (q31_t)0x261e4511, (q31_t)0x85ceba4d, + (q31_t)0x26184581, (q31_t)0x85ccdb70, (q31_t)0x261245da, (q31_t)0x85cafcdf, (q31_t)0x260c461b, (q31_t)0x85c91e9a, (q31_t)0x26064645, (q31_t)0x85c740a0, + (q31_t)0x26004657, (q31_t)0x85c562f1, (q31_t)0x25fa4652, (q31_t)0x85c3858d, (q31_t)0x25f44635, (q31_t)0x85c1a875, (q31_t)0x25ee4601, (q31_t)0x85bfcba9, + (q31_t)0x25e845b6, (q31_t)0x85bdef28, (q31_t)0x25e24553, (q31_t)0x85bc12f2, (q31_t)0x25dc44d9, (q31_t)0x85ba3707, (q31_t)0x25d64447, (q31_t)0x85b85b68, + (q31_t)0x25d0439f, (q31_t)0x85b68015, (q31_t)0x25ca42de, (q31_t)0x85b4a50d, (q31_t)0x25c44207, (q31_t)0x85b2ca50, (q31_t)0x25be4118, (q31_t)0x85b0efdf, + (q31_t)0x25b84012, (q31_t)0x85af15b9, (q31_t)0x25b23ef5, (q31_t)0x85ad3bdf, (q31_t)0x25ac3dc0, (q31_t)0x85ab6250, (q31_t)0x25a63c74, (q31_t)0x85a9890d, + (q31_t)0x25a03b11, (q31_t)0x85a7b015, (q31_t)0x259a3997, (q31_t)0x85a5d768, (q31_t)0x25943806, (q31_t)0x85a3ff07, (q31_t)0x258e365d, (q31_t)0x85a226f2, + (q31_t)0x2588349d, (q31_t)0x85a04f28, (q31_t)0x258232c6, (q31_t)0x859e77a9, (q31_t)0x257c30d8, (q31_t)0x859ca076, (q31_t)0x25762ed3, (q31_t)0x859ac98f, + (q31_t)0x25702cb7, (q31_t)0x8598f2f3, (q31_t)0x256a2a83, (q31_t)0x85971ca2, (q31_t)0x25642839, (q31_t)0x8595469d, (q31_t)0x255e25d7, (q31_t)0x859370e4, + (q31_t)0x2558235f, (q31_t)0x85919b76, (q31_t)0x255220cf, (q31_t)0x858fc653, (q31_t)0x254c1e28, (q31_t)0x858df17c, (q31_t)0x25461b6b, (q31_t)0x858c1cf1, + (q31_t)0x25401896, (q31_t)0x858a48b1, (q31_t)0x253a15aa, (q31_t)0x858874bd, (q31_t)0x253412a8, (q31_t)0x8586a114, (q31_t)0x252e0f8e, (q31_t)0x8584cdb7, + (q31_t)0x25280c5e, (q31_t)0x8582faa5, (q31_t)0x25220916, (q31_t)0x858127df, (q31_t)0x251c05b8, (q31_t)0x857f5564, (q31_t)0x25160243, (q31_t)0x857d8335, + (q31_t)0x250ffeb7, (q31_t)0x857bb152, (q31_t)0x2509fb14, (q31_t)0x8579dfba, (q31_t)0x2503f75a, (q31_t)0x85780e6e, (q31_t)0x24fdf389, (q31_t)0x85763d6d, + (q31_t)0x24f7efa2, (q31_t)0x85746cb8, (q31_t)0x24f1eba4, (q31_t)0x85729c4e, (q31_t)0x24ebe78f, (q31_t)0x8570cc30, (q31_t)0x24e5e363, (q31_t)0x856efc5e, + (q31_t)0x24dfdf20, (q31_t)0x856d2cd7, (q31_t)0x24d9dac7, (q31_t)0x856b5d9c, (q31_t)0x24d3d657, (q31_t)0x85698ead, (q31_t)0x24cdd1d0, (q31_t)0x8567c009, + (q31_t)0x24c7cd33, (q31_t)0x8565f1b0, (q31_t)0x24c1c87f, (q31_t)0x856423a4, (q31_t)0x24bbc3b4, (q31_t)0x856255e3, (q31_t)0x24b5bed2, (q31_t)0x8560886d, + (q31_t)0x24afb9da, (q31_t)0x855ebb44, (q31_t)0x24a9b4cb, (q31_t)0x855cee66, (q31_t)0x24a3afa6, (q31_t)0x855b21d3, (q31_t)0x249daa6a, (q31_t)0x8559558c, + (q31_t)0x2497a517, (q31_t)0x85578991, (q31_t)0x24919fae, (q31_t)0x8555bde2, (q31_t)0x248b9a2f, (q31_t)0x8553f27e, (q31_t)0x24859498, (q31_t)0x85522766, + (q31_t)0x247f8eec, (q31_t)0x85505c99, (q31_t)0x24798928, (q31_t)0x854e9219, (q31_t)0x2473834f, (q31_t)0x854cc7e3, (q31_t)0x246d7d5e, (q31_t)0x854afdfa, + (q31_t)0x24677758, (q31_t)0x8549345c, (q31_t)0x2461713a, (q31_t)0x85476b0a, (q31_t)0x245b6b07, (q31_t)0x8545a204, (q31_t)0x245564bd, (q31_t)0x8543d949, + (q31_t)0x244f5e5c, (q31_t)0x854210db, (q31_t)0x244957e5, (q31_t)0x854048b7, (q31_t)0x24435158, (q31_t)0x853e80e0, (q31_t)0x243d4ab4, (q31_t)0x853cb954, + (q31_t)0x243743fa, (q31_t)0x853af214, (q31_t)0x24313d2a, (q31_t)0x85392b20, (q31_t)0x242b3644, (q31_t)0x85376477, (q31_t)0x24252f47, (q31_t)0x85359e1a, + (q31_t)0x241f2833, (q31_t)0x8533d809, (q31_t)0x2419210a, (q31_t)0x85321244, (q31_t)0x241319ca, (q31_t)0x85304cca, (q31_t)0x240d1274, (q31_t)0x852e879d, + (q31_t)0x24070b08, (q31_t)0x852cc2bb, (q31_t)0x24010385, (q31_t)0x852afe24, (q31_t)0x23fafbec, (q31_t)0x852939da, (q31_t)0x23f4f43e, (q31_t)0x852775db, + (q31_t)0x23eeec78, (q31_t)0x8525b228, (q31_t)0x23e8e49d, (q31_t)0x8523eec1, (q31_t)0x23e2dcac, (q31_t)0x85222ba5, (q31_t)0x23dcd4a4, (q31_t)0x852068d6, + (q31_t)0x23d6cc87, (q31_t)0x851ea652, (q31_t)0x23d0c453, (q31_t)0x851ce41a, (q31_t)0x23cabc09, (q31_t)0x851b222e, (q31_t)0x23c4b3a9, (q31_t)0x8519608d, + (q31_t)0x23beab33, (q31_t)0x85179f39, (q31_t)0x23b8a2a7, (q31_t)0x8515de30, (q31_t)0x23b29a05, (q31_t)0x85141d73, (q31_t)0x23ac914d, (q31_t)0x85125d02, + (q31_t)0x23a6887f, (q31_t)0x85109cdd, (q31_t)0x23a07f9a, (q31_t)0x850edd03, (q31_t)0x239a76a0, (q31_t)0x850d1d75, (q31_t)0x23946d90, (q31_t)0x850b5e34, + (q31_t)0x238e646a, (q31_t)0x85099f3e, (q31_t)0x23885b2e, (q31_t)0x8507e094, (q31_t)0x238251dd, (q31_t)0x85062235, (q31_t)0x237c4875, (q31_t)0x85046423, + (q31_t)0x23763ef7, (q31_t)0x8502a65c, (q31_t)0x23703564, (q31_t)0x8500e8e2, (q31_t)0x236a2bba, (q31_t)0x84ff2bb3, (q31_t)0x236421fb, (q31_t)0x84fd6ed0, + (q31_t)0x235e1826, (q31_t)0x84fbb239, (q31_t)0x23580e3b, (q31_t)0x84f9f5ee, (q31_t)0x2352043b, (q31_t)0x84f839ee, (q31_t)0x234bfa24, (q31_t)0x84f67e3b, + (q31_t)0x2345eff8, (q31_t)0x84f4c2d4, (q31_t)0x233fe5b6, (q31_t)0x84f307b8, (q31_t)0x2339db5e, (q31_t)0x84f14ce8, (q31_t)0x2333d0f1, (q31_t)0x84ef9265, + (q31_t)0x232dc66d, (q31_t)0x84edd82d, (q31_t)0x2327bbd5, (q31_t)0x84ec1e41, (q31_t)0x2321b126, (q31_t)0x84ea64a1, (q31_t)0x231ba662, (q31_t)0x84e8ab4d, + (q31_t)0x23159b88, (q31_t)0x84e6f244, (q31_t)0x230f9098, (q31_t)0x84e53988, (q31_t)0x23098593, (q31_t)0x84e38118, (q31_t)0x23037a78, (q31_t)0x84e1c8f3, + (q31_t)0x22fd6f48, (q31_t)0x84e0111b, (q31_t)0x22f76402, (q31_t)0x84de598f, (q31_t)0x22f158a7, (q31_t)0x84dca24e, (q31_t)0x22eb4d36, (q31_t)0x84daeb5a, + (q31_t)0x22e541af, (q31_t)0x84d934b1, (q31_t)0x22df3613, (q31_t)0x84d77e54, (q31_t)0x22d92a61, (q31_t)0x84d5c844, (q31_t)0x22d31e9a, (q31_t)0x84d4127f, + (q31_t)0x22cd12bd, (q31_t)0x84d25d06, (q31_t)0x22c706cb, (q31_t)0x84d0a7da, (q31_t)0x22c0fac4, (q31_t)0x84cef2f9, (q31_t)0x22baeea7, (q31_t)0x84cd3e64, + (q31_t)0x22b4e274, (q31_t)0x84cb8a1b, (q31_t)0x22aed62c, (q31_t)0x84c9d61f, (q31_t)0x22a8c9cf, (q31_t)0x84c8226e, (q31_t)0x22a2bd5d, (q31_t)0x84c66f09, + (q31_t)0x229cb0d5, (q31_t)0x84c4bbf0, (q31_t)0x2296a437, (q31_t)0x84c30924, (q31_t)0x22909785, (q31_t)0x84c156a3, (q31_t)0x228a8abd, (q31_t)0x84bfa46e, + (q31_t)0x22847de0, (q31_t)0x84bdf286, (q31_t)0x227e70ed, (q31_t)0x84bc40e9, (q31_t)0x227863e5, (q31_t)0x84ba8f98, (q31_t)0x227256c8, (q31_t)0x84b8de94, + (q31_t)0x226c4996, (q31_t)0x84b72ddb, (q31_t)0x22663c4e, (q31_t)0x84b57d6f, (q31_t)0x22602ef1, (q31_t)0x84b3cd4f, (q31_t)0x225a217f, (q31_t)0x84b21d7a, + (q31_t)0x225413f8, (q31_t)0x84b06df2, (q31_t)0x224e065c, (q31_t)0x84aebeb6, (q31_t)0x2247f8aa, (q31_t)0x84ad0fc6, (q31_t)0x2241eae3, (q31_t)0x84ab6122, + (q31_t)0x223bdd08, (q31_t)0x84a9b2ca, (q31_t)0x2235cf17, (q31_t)0x84a804be, (q31_t)0x222fc111, (q31_t)0x84a656fe, (q31_t)0x2229b2f6, (q31_t)0x84a4a98a, + (q31_t)0x2223a4c5, (q31_t)0x84a2fc62, (q31_t)0x221d9680, (q31_t)0x84a14f87, (q31_t)0x22178826, (q31_t)0x849fa2f7, (q31_t)0x221179b7, (q31_t)0x849df6b4, + (q31_t)0x220b6b32, (q31_t)0x849c4abd, (q31_t)0x22055c99, (q31_t)0x849a9f12, (q31_t)0x21ff4dea, (q31_t)0x8498f3b3, (q31_t)0x21f93f27, (q31_t)0x849748a0, + (q31_t)0x21f3304f, (q31_t)0x84959dd9, (q31_t)0x21ed2162, (q31_t)0x8493f35e, (q31_t)0x21e71260, (q31_t)0x84924930, (q31_t)0x21e10349, (q31_t)0x84909f4e, + (q31_t)0x21daf41d, (q31_t)0x848ef5b7, (q31_t)0x21d4e4dc, (q31_t)0x848d4c6d, (q31_t)0x21ced586, (q31_t)0x848ba36f, (q31_t)0x21c8c61c, (q31_t)0x8489fabe, + (q31_t)0x21c2b69c, (q31_t)0x84885258, (q31_t)0x21bca708, (q31_t)0x8486aa3e, (q31_t)0x21b6975f, (q31_t)0x84850271, (q31_t)0x21b087a1, (q31_t)0x84835af0, + (q31_t)0x21aa77cf, (q31_t)0x8481b3bb, (q31_t)0x21a467e7, (q31_t)0x84800cd2, (q31_t)0x219e57eb, (q31_t)0x847e6636, (q31_t)0x219847da, (q31_t)0x847cbfe5, + (q31_t)0x219237b5, (q31_t)0x847b19e1, (q31_t)0x218c277a, (q31_t)0x84797429, (q31_t)0x2186172b, (q31_t)0x8477cebd, (q31_t)0x218006c8, (q31_t)0x8476299e, + (q31_t)0x2179f64f, (q31_t)0x847484ca, (q31_t)0x2173e5c2, (q31_t)0x8472e043, (q31_t)0x216dd521, (q31_t)0x84713c08, (q31_t)0x2167c46b, (q31_t)0x846f9819, + (q31_t)0x2161b3a0, (q31_t)0x846df477, (q31_t)0x215ba2c0, (q31_t)0x846c5120, (q31_t)0x215591cc, (q31_t)0x846aae16, (q31_t)0x214f80c4, (q31_t)0x84690b58, + (q31_t)0x21496fa7, (q31_t)0x846768e7, (q31_t)0x21435e75, (q31_t)0x8465c6c1, (q31_t)0x213d4d2f, (q31_t)0x846424e8, (q31_t)0x21373bd4, (q31_t)0x8462835b, + (q31_t)0x21312a65, (q31_t)0x8460e21a, (q31_t)0x212b18e1, (q31_t)0x845f4126, (q31_t)0x21250749, (q31_t)0x845da07e, (q31_t)0x211ef59d, (q31_t)0x845c0022, + (q31_t)0x2118e3dc, (q31_t)0x845a6012, (q31_t)0x2112d206, (q31_t)0x8458c04f, (q31_t)0x210cc01d, (q31_t)0x845720d8, (q31_t)0x2106ae1e, (q31_t)0x845581ad, + (q31_t)0x21009c0c, (q31_t)0x8453e2cf, (q31_t)0x20fa89e5, (q31_t)0x8452443d, (q31_t)0x20f477aa, (q31_t)0x8450a5f7, (q31_t)0x20ee655a, (q31_t)0x844f07fd, + (q31_t)0x20e852f6, (q31_t)0x844d6a50, (q31_t)0x20e2407e, (q31_t)0x844bccef, (q31_t)0x20dc2df2, (q31_t)0x844a2fda, (q31_t)0x20d61b51, (q31_t)0x84489311, + (q31_t)0x20d0089c, (q31_t)0x8446f695, (q31_t)0x20c9f5d3, (q31_t)0x84455a66, (q31_t)0x20c3e2f5, (q31_t)0x8443be82, (q31_t)0x20bdd003, (q31_t)0x844222eb, + (q31_t)0x20b7bcfe, (q31_t)0x844087a0, (q31_t)0x20b1a9e4, (q31_t)0x843eeca2, (q31_t)0x20ab96b5, (q31_t)0x843d51f0, (q31_t)0x20a58373, (q31_t)0x843bb78a, + (q31_t)0x209f701c, (q31_t)0x843a1d70, (q31_t)0x20995cb2, (q31_t)0x843883a3, (q31_t)0x20934933, (q31_t)0x8436ea23, (q31_t)0x208d35a0, (q31_t)0x843550ee, + (q31_t)0x208721f9, (q31_t)0x8433b806, (q31_t)0x20810e3e, (q31_t)0x84321f6b, (q31_t)0x207afa6f, (q31_t)0x8430871b, (q31_t)0x2074e68c, (q31_t)0x842eef18, + (q31_t)0x206ed295, (q31_t)0x842d5762, (q31_t)0x2068be8a, (q31_t)0x842bbff8, (q31_t)0x2062aa6b, (q31_t)0x842a28da, (q31_t)0x205c9638, (q31_t)0x84289209, + (q31_t)0x205681f1, (q31_t)0x8426fb84, (q31_t)0x20506d96, (q31_t)0x8425654b, (q31_t)0x204a5927, (q31_t)0x8423cf5f, (q31_t)0x204444a4, (q31_t)0x842239bf, + (q31_t)0x203e300d, (q31_t)0x8420a46c, (q31_t)0x20381b63, (q31_t)0x841f0f65, (q31_t)0x203206a4, (q31_t)0x841d7aaa, (q31_t)0x202bf1d2, (q31_t)0x841be63c, + (q31_t)0x2025dcec, (q31_t)0x841a521a, (q31_t)0x201fc7f2, (q31_t)0x8418be45, (q31_t)0x2019b2e4, (q31_t)0x84172abc, (q31_t)0x20139dc2, (q31_t)0x84159780, + (q31_t)0x200d888d, (q31_t)0x84140490, (q31_t)0x20077344, (q31_t)0x841271ec, (q31_t)0x20015de7, (q31_t)0x8410df95, (q31_t)0x1ffb4876, (q31_t)0x840f4d8a, + (q31_t)0x1ff532f2, (q31_t)0x840dbbcc, (q31_t)0x1fef1d59, (q31_t)0x840c2a5a, (q31_t)0x1fe907ae, (q31_t)0x840a9935, (q31_t)0x1fe2f1ee, (q31_t)0x8409085c, + (q31_t)0x1fdcdc1b, (q31_t)0x840777d0, (q31_t)0x1fd6c634, (q31_t)0x8405e790, (q31_t)0x1fd0b03a, (q31_t)0x8404579d, (q31_t)0x1fca9a2b, (q31_t)0x8402c7f6, + (q31_t)0x1fc4840a, (q31_t)0x8401389b, (q31_t)0x1fbe6dd4, (q31_t)0x83ffa98d, (q31_t)0x1fb8578b, (q31_t)0x83fe1acc, (q31_t)0x1fb2412f, (q31_t)0x83fc8c57, + (q31_t)0x1fac2abf, (q31_t)0x83fafe2e, (q31_t)0x1fa6143b, (q31_t)0x83f97052, (q31_t)0x1f9ffda4, (q31_t)0x83f7e2c3, (q31_t)0x1f99e6fa, (q31_t)0x83f65580, + (q31_t)0x1f93d03c, (q31_t)0x83f4c889, (q31_t)0x1f8db96a, (q31_t)0x83f33bdf, (q31_t)0x1f87a285, (q31_t)0x83f1af82, (q31_t)0x1f818b8d, (q31_t)0x83f02371, + (q31_t)0x1f7b7481, (q31_t)0x83ee97ad, (q31_t)0x1f755d61, (q31_t)0x83ed0c35, (q31_t)0x1f6f462f, (q31_t)0x83eb810a, (q31_t)0x1f692ee9, (q31_t)0x83e9f62b, + (q31_t)0x1f63178f, (q31_t)0x83e86b99, (q31_t)0x1f5d0022, (q31_t)0x83e6e153, (q31_t)0x1f56e8a2, (q31_t)0x83e5575a, (q31_t)0x1f50d10e, (q31_t)0x83e3cdad, + (q31_t)0x1f4ab968, (q31_t)0x83e2444d, (q31_t)0x1f44a1ad, (q31_t)0x83e0bb3a, (q31_t)0x1f3e89e0, (q31_t)0x83df3273, (q31_t)0x1f3871ff, (q31_t)0x83dda9f9, + (q31_t)0x1f325a0b, (q31_t)0x83dc21cb, (q31_t)0x1f2c4204, (q31_t)0x83da99ea, (q31_t)0x1f2629ea, (q31_t)0x83d91255, (q31_t)0x1f2011bc, (q31_t)0x83d78b0d, + (q31_t)0x1f19f97b, (q31_t)0x83d60412, (q31_t)0x1f13e127, (q31_t)0x83d47d63, (q31_t)0x1f0dc8c0, (q31_t)0x83d2f701, (q31_t)0x1f07b045, (q31_t)0x83d170eb, + (q31_t)0x1f0197b8, (q31_t)0x83cfeb22, (q31_t)0x1efb7f17, (q31_t)0x83ce65a6, (q31_t)0x1ef56664, (q31_t)0x83cce076, (q31_t)0x1eef4d9d, (q31_t)0x83cb5b93, + (q31_t)0x1ee934c3, (q31_t)0x83c9d6fc, (q31_t)0x1ee31bd6, (q31_t)0x83c852b2, (q31_t)0x1edd02d6, (q31_t)0x83c6ceb5, (q31_t)0x1ed6e9c3, (q31_t)0x83c54b04, + (q31_t)0x1ed0d09d, (q31_t)0x83c3c7a0, (q31_t)0x1ecab763, (q31_t)0x83c24488, (q31_t)0x1ec49e17, (q31_t)0x83c0c1be, (q31_t)0x1ebe84b8, (q31_t)0x83bf3f3f, + (q31_t)0x1eb86b46, (q31_t)0x83bdbd0e, (q31_t)0x1eb251c1, (q31_t)0x83bc3b29, (q31_t)0x1eac3829, (q31_t)0x83bab991, (q31_t)0x1ea61e7e, (q31_t)0x83b93845, + (q31_t)0x1ea004c1, (q31_t)0x83b7b746, (q31_t)0x1e99eaf0, (q31_t)0x83b63694, (q31_t)0x1e93d10c, (q31_t)0x83b4b62e, (q31_t)0x1e8db716, (q31_t)0x83b33616, + (q31_t)0x1e879d0d, (q31_t)0x83b1b649, (q31_t)0x1e8182f1, (q31_t)0x83b036ca, (q31_t)0x1e7b68c2, (q31_t)0x83aeb797, (q31_t)0x1e754e80, (q31_t)0x83ad38b1, + (q31_t)0x1e6f342c, (q31_t)0x83abba17, (q31_t)0x1e6919c4, (q31_t)0x83aa3bca, (q31_t)0x1e62ff4a, (q31_t)0x83a8bdca, (q31_t)0x1e5ce4be, (q31_t)0x83a74017, + (q31_t)0x1e56ca1e, (q31_t)0x83a5c2b0, (q31_t)0x1e50af6c, (q31_t)0x83a44596, (q31_t)0x1e4a94a7, (q31_t)0x83a2c8c9, (q31_t)0x1e4479cf, (q31_t)0x83a14c48, + (q31_t)0x1e3e5ee5, (q31_t)0x839fd014, (q31_t)0x1e3843e8, (q31_t)0x839e542d, (q31_t)0x1e3228d9, (q31_t)0x839cd893, (q31_t)0x1e2c0db6, (q31_t)0x839b5d45, + (q31_t)0x1e25f282, (q31_t)0x8399e244, (q31_t)0x1e1fd73a, (q31_t)0x83986790, (q31_t)0x1e19bbe0, (q31_t)0x8396ed29, (q31_t)0x1e13a074, (q31_t)0x8395730e, + (q31_t)0x1e0d84f5, (q31_t)0x8393f940, (q31_t)0x1e076963, (q31_t)0x83927fbf, (q31_t)0x1e014dbf, (q31_t)0x8391068a, (q31_t)0x1dfb3208, (q31_t)0x838f8da2, + (q31_t)0x1df5163f, (q31_t)0x838e1507, (q31_t)0x1deefa63, (q31_t)0x838c9cb9, (q31_t)0x1de8de75, (q31_t)0x838b24b8, (q31_t)0x1de2c275, (q31_t)0x8389ad03, + (q31_t)0x1ddca662, (q31_t)0x8388359b, (q31_t)0x1dd68a3c, (q31_t)0x8386be80, (q31_t)0x1dd06e04, (q31_t)0x838547b2, (q31_t)0x1dca51ba, (q31_t)0x8383d130, + (q31_t)0x1dc4355e, (q31_t)0x83825afb, (q31_t)0x1dbe18ef, (q31_t)0x8380e513, (q31_t)0x1db7fc6d, (q31_t)0x837f6f78, (q31_t)0x1db1dfda, (q31_t)0x837dfa2a, + (q31_t)0x1dabc334, (q31_t)0x837c8528, (q31_t)0x1da5a67c, (q31_t)0x837b1074, (q31_t)0x1d9f89b1, (q31_t)0x83799c0c, (q31_t)0x1d996cd4, (q31_t)0x837827f0, + (q31_t)0x1d934fe5, (q31_t)0x8376b422, (q31_t)0x1d8d32e4, (q31_t)0x837540a1, (q31_t)0x1d8715d0, (q31_t)0x8373cd6c, (q31_t)0x1d80f8ab, (q31_t)0x83725a84, + (q31_t)0x1d7adb73, (q31_t)0x8370e7e9, (q31_t)0x1d74be29, (q31_t)0x836f759b, (q31_t)0x1d6ea0cc, (q31_t)0x836e039a, (q31_t)0x1d68835e, (q31_t)0x836c91e5, + (q31_t)0x1d6265dd, (q31_t)0x836b207d, (q31_t)0x1d5c484b, (q31_t)0x8369af63, (q31_t)0x1d562aa6, (q31_t)0x83683e95, (q31_t)0x1d500cef, (q31_t)0x8366ce14, + (q31_t)0x1d49ef26, (q31_t)0x83655ddf, (q31_t)0x1d43d14b, (q31_t)0x8363edf8, (q31_t)0x1d3db35e, (q31_t)0x83627e5d, (q31_t)0x1d37955e, (q31_t)0x83610f10, + (q31_t)0x1d31774d, (q31_t)0x835fa00f, (q31_t)0x1d2b592a, (q31_t)0x835e315b, (q31_t)0x1d253af5, (q31_t)0x835cc2f4, (q31_t)0x1d1f1cae, (q31_t)0x835b54da, + (q31_t)0x1d18fe54, (q31_t)0x8359e70d, (q31_t)0x1d12dfe9, (q31_t)0x8358798c, (q31_t)0x1d0cc16c, (q31_t)0x83570c59, (q31_t)0x1d06a2dd, (q31_t)0x83559f72, + (q31_t)0x1d00843d, (q31_t)0x835432d8, (q31_t)0x1cfa658a, (q31_t)0x8352c68c, (q31_t)0x1cf446c5, (q31_t)0x83515a8c, (q31_t)0x1cee27ef, (q31_t)0x834feed9, + (q31_t)0x1ce80906, (q31_t)0x834e8373, (q31_t)0x1ce1ea0c, (q31_t)0x834d185a, (q31_t)0x1cdbcb00, (q31_t)0x834bad8e, (q31_t)0x1cd5abe3, (q31_t)0x834a430e, + (q31_t)0x1ccf8cb3, (q31_t)0x8348d8dc, (q31_t)0x1cc96d72, (q31_t)0x83476ef6, (q31_t)0x1cc34e1f, (q31_t)0x8346055e, (q31_t)0x1cbd2eba, (q31_t)0x83449c12, + (q31_t)0x1cb70f43, (q31_t)0x83433314, (q31_t)0x1cb0efbb, (q31_t)0x8341ca62, (q31_t)0x1caad021, (q31_t)0x834061fd, (q31_t)0x1ca4b075, (q31_t)0x833ef9e6, + (q31_t)0x1c9e90b8, (q31_t)0x833d921b, (q31_t)0x1c9870e9, (q31_t)0x833c2a9d, (q31_t)0x1c925109, (q31_t)0x833ac36c, (q31_t)0x1c8c3116, (q31_t)0x83395c88, + (q31_t)0x1c861113, (q31_t)0x8337f5f1, (q31_t)0x1c7ff0fd, (q31_t)0x83368fa7, (q31_t)0x1c79d0d6, (q31_t)0x833529aa, (q31_t)0x1c73b09d, (q31_t)0x8333c3fa, + (q31_t)0x1c6d9053, (q31_t)0x83325e97, (q31_t)0x1c676ff8, (q31_t)0x8330f981, (q31_t)0x1c614f8b, (q31_t)0x832f94b8, (q31_t)0x1c5b2f0c, (q31_t)0x832e303c, + (q31_t)0x1c550e7c, (q31_t)0x832ccc0d, (q31_t)0x1c4eedda, (q31_t)0x832b682b, (q31_t)0x1c48cd27, (q31_t)0x832a0496, (q31_t)0x1c42ac62, (q31_t)0x8328a14d, + (q31_t)0x1c3c8b8c, (q31_t)0x83273e52, (q31_t)0x1c366aa5, (q31_t)0x8325dba4, (q31_t)0x1c3049ac, (q31_t)0x83247943, (q31_t)0x1c2a28a2, (q31_t)0x8323172f, + (q31_t)0x1c240786, (q31_t)0x8321b568, (q31_t)0x1c1de659, (q31_t)0x832053ee, (q31_t)0x1c17c51b, (q31_t)0x831ef2c1, (q31_t)0x1c11a3cb, (q31_t)0x831d91e1, + (q31_t)0x1c0b826a, (q31_t)0x831c314e, (q31_t)0x1c0560f8, (q31_t)0x831ad109, (q31_t)0x1bff3f75, (q31_t)0x83197110, (q31_t)0x1bf91de0, (q31_t)0x83181164, + (q31_t)0x1bf2fc3a, (q31_t)0x8316b205, (q31_t)0x1becda83, (q31_t)0x831552f4, (q31_t)0x1be6b8ba, (q31_t)0x8313f42f, (q31_t)0x1be096e0, (q31_t)0x831295b7, + (q31_t)0x1bda74f6, (q31_t)0x8311378d, (q31_t)0x1bd452f9, (q31_t)0x830fd9af, (q31_t)0x1bce30ec, (q31_t)0x830e7c1f, (q31_t)0x1bc80ece, (q31_t)0x830d1edc, + (q31_t)0x1bc1ec9e, (q31_t)0x830bc1e6, (q31_t)0x1bbbca5e, (q31_t)0x830a653c, (q31_t)0x1bb5a80c, (q31_t)0x830908e0, (q31_t)0x1baf85a9, (q31_t)0x8307acd1, + (q31_t)0x1ba96335, (q31_t)0x83065110, (q31_t)0x1ba340b0, (q31_t)0x8304f59b, (q31_t)0x1b9d1e1a, (q31_t)0x83039a73, (q31_t)0x1b96fb73, (q31_t)0x83023f98, + (q31_t)0x1b90d8bb, (q31_t)0x8300e50b, (q31_t)0x1b8ab5f2, (q31_t)0x82ff8acb, (q31_t)0x1b849317, (q31_t)0x82fe30d7, (q31_t)0x1b7e702c, (q31_t)0x82fcd731, + (q31_t)0x1b784d30, (q31_t)0x82fb7dd8, (q31_t)0x1b722a23, (q31_t)0x82fa24cc, (q31_t)0x1b6c0705, (q31_t)0x82f8cc0d, (q31_t)0x1b65e3d7, (q31_t)0x82f7739c, + (q31_t)0x1b5fc097, (q31_t)0x82f61b77, (q31_t)0x1b599d46, (q31_t)0x82f4c3a0, (q31_t)0x1b5379e5, (q31_t)0x82f36c15, (q31_t)0x1b4d5672, (q31_t)0x82f214d8, + (q31_t)0x1b4732ef, (q31_t)0x82f0bde8, (q31_t)0x1b410f5b, (q31_t)0x82ef6745, (q31_t)0x1b3aebb6, (q31_t)0x82ee10ef, (q31_t)0x1b34c801, (q31_t)0x82ecbae7, + (q31_t)0x1b2ea43a, (q31_t)0x82eb652b, (q31_t)0x1b288063, (q31_t)0x82ea0fbd, (q31_t)0x1b225c7b, (q31_t)0x82e8ba9c, (q31_t)0x1b1c3883, (q31_t)0x82e765c8, + (q31_t)0x1b161479, (q31_t)0x82e61141, (q31_t)0x1b0ff05f, (q31_t)0x82e4bd07, (q31_t)0x1b09cc34, (q31_t)0x82e3691b, (q31_t)0x1b03a7f9, (q31_t)0x82e2157c, + (q31_t)0x1afd83ad, (q31_t)0x82e0c22a, (q31_t)0x1af75f50, (q31_t)0x82df6f25, (q31_t)0x1af13ae3, (q31_t)0x82de1c6d, (q31_t)0x1aeb1665, (q31_t)0x82dcca02, + (q31_t)0x1ae4f1d6, (q31_t)0x82db77e5, (q31_t)0x1adecd37, (q31_t)0x82da2615, (q31_t)0x1ad8a887, (q31_t)0x82d8d492, (q31_t)0x1ad283c7, (q31_t)0x82d7835c, + (q31_t)0x1acc5ef6, (q31_t)0x82d63274, (q31_t)0x1ac63a14, (q31_t)0x82d4e1d8, (q31_t)0x1ac01522, (q31_t)0x82d3918a, (q31_t)0x1ab9f020, (q31_t)0x82d24189, + (q31_t)0x1ab3cb0d, (q31_t)0x82d0f1d5, (q31_t)0x1aada5e9, (q31_t)0x82cfa26f, (q31_t)0x1aa780b6, (q31_t)0x82ce5356, (q31_t)0x1aa15b71, (q31_t)0x82cd048a, + (q31_t)0x1a9b361d, (q31_t)0x82cbb60b, (q31_t)0x1a9510b7, (q31_t)0x82ca67d9, (q31_t)0x1a8eeb42, (q31_t)0x82c919f5, (q31_t)0x1a88c5bc, (q31_t)0x82c7cc5e, + (q31_t)0x1a82a026, (q31_t)0x82c67f14, (q31_t)0x1a7c7a7f, (q31_t)0x82c53217, (q31_t)0x1a7654c8, (q31_t)0x82c3e568, (q31_t)0x1a702f01, (q31_t)0x82c29906, + (q31_t)0x1a6a0929, (q31_t)0x82c14cf1, (q31_t)0x1a63e341, (q31_t)0x82c00129, (q31_t)0x1a5dbd49, (q31_t)0x82beb5af, (q31_t)0x1a579741, (q31_t)0x82bd6a82, + (q31_t)0x1a517128, (q31_t)0x82bc1fa2, (q31_t)0x1a4b4aff, (q31_t)0x82bad50f, (q31_t)0x1a4524c6, (q31_t)0x82b98aca, (q31_t)0x1a3efe7c, (q31_t)0x82b840d2, + (q31_t)0x1a38d823, (q31_t)0x82b6f727, (q31_t)0x1a32b1b9, (q31_t)0x82b5adca, (q31_t)0x1a2c8b3f, (q31_t)0x82b464ba, (q31_t)0x1a2664b5, (q31_t)0x82b31bf7, + (q31_t)0x1a203e1b, (q31_t)0x82b1d381, (q31_t)0x1a1a1771, (q31_t)0x82b08b59, (q31_t)0x1a13f0b6, (q31_t)0x82af437e, (q31_t)0x1a0dc9ec, (q31_t)0x82adfbf0, + (q31_t)0x1a07a311, (q31_t)0x82acb4b0, (q31_t)0x1a017c27, (q31_t)0x82ab6dbd, (q31_t)0x19fb552c, (q31_t)0x82aa2717, (q31_t)0x19f52e22, (q31_t)0x82a8e0bf, + (q31_t)0x19ef0707, (q31_t)0x82a79ab3, (q31_t)0x19e8dfdc, (q31_t)0x82a654f6, (q31_t)0x19e2b8a2, (q31_t)0x82a50f85, (q31_t)0x19dc9157, (q31_t)0x82a3ca62, + (q31_t)0x19d669fc, (q31_t)0x82a2858c, (q31_t)0x19d04292, (q31_t)0x82a14104, (q31_t)0x19ca1b17, (q31_t)0x829ffcc8, (q31_t)0x19c3f38d, (q31_t)0x829eb8db, + (q31_t)0x19bdcbf3, (q31_t)0x829d753a, (q31_t)0x19b7a449, (q31_t)0x829c31e7, (q31_t)0x19b17c8f, (q31_t)0x829aeee1, (q31_t)0x19ab54c5, (q31_t)0x8299ac29, + (q31_t)0x19a52ceb, (q31_t)0x829869be, (q31_t)0x199f0502, (q31_t)0x829727a0, (q31_t)0x1998dd09, (q31_t)0x8295e5cf, (q31_t)0x1992b4ff, (q31_t)0x8294a44c, + (q31_t)0x198c8ce7, (q31_t)0x82936317, (q31_t)0x198664be, (q31_t)0x8292222e, (q31_t)0x19803c86, (q31_t)0x8290e194, (q31_t)0x197a143e, (q31_t)0x828fa146, + (q31_t)0x1973ebe6, (q31_t)0x828e6146, (q31_t)0x196dc37e, (q31_t)0x828d2193, (q31_t)0x19679b07, (q31_t)0x828be22e, (q31_t)0x19617280, (q31_t)0x828aa316, + (q31_t)0x195b49ea, (q31_t)0x8289644b, (q31_t)0x19552144, (q31_t)0x828825ce, (q31_t)0x194ef88e, (q31_t)0x8286e79e, (q31_t)0x1948cfc8, (q31_t)0x8285a9bb, + (q31_t)0x1942a6f3, (q31_t)0x82846c26, (q31_t)0x193c7e0f, (q31_t)0x82832edf, (q31_t)0x1936551b, (q31_t)0x8281f1e4, (q31_t)0x19302c17, (q31_t)0x8280b538, + (q31_t)0x192a0304, (q31_t)0x827f78d8, (q31_t)0x1923d9e1, (q31_t)0x827e3cc6, (q31_t)0x191db0af, (q31_t)0x827d0102, (q31_t)0x1917876d, (q31_t)0x827bc58a, + (q31_t)0x19115e1c, (q31_t)0x827a8a61, (q31_t)0x190b34bb, (q31_t)0x82794f84, (q31_t)0x19050b4b, (q31_t)0x827814f6, (q31_t)0x18fee1cb, (q31_t)0x8276dab4, + (q31_t)0x18f8b83c, (q31_t)0x8275a0c0, (q31_t)0x18f28e9e, (q31_t)0x8274671a, (q31_t)0x18ec64f0, (q31_t)0x82732dc0, (q31_t)0x18e63b33, (q31_t)0x8271f4b5, + (q31_t)0x18e01167, (q31_t)0x8270bbf7, (q31_t)0x18d9e78b, (q31_t)0x826f8386, (q31_t)0x18d3bda0, (q31_t)0x826e4b62, (q31_t)0x18cd93a5, (q31_t)0x826d138d, + (q31_t)0x18c7699b, (q31_t)0x826bdc04, (q31_t)0x18c13f82, (q31_t)0x826aa4c9, (q31_t)0x18bb155a, (q31_t)0x82696ddc, (q31_t)0x18b4eb22, (q31_t)0x8268373c, + (q31_t)0x18aec0db, (q31_t)0x826700e9, (q31_t)0x18a89685, (q31_t)0x8265cae4, (q31_t)0x18a26c20, (q31_t)0x8264952d, (q31_t)0x189c41ab, (q31_t)0x82635fc2, + (q31_t)0x18961728, (q31_t)0x82622aa6, (q31_t)0x188fec95, (q31_t)0x8260f5d7, (q31_t)0x1889c1f3, (q31_t)0x825fc155, (q31_t)0x18839742, (q31_t)0x825e8d21, + (q31_t)0x187d6c82, (q31_t)0x825d593a, (q31_t)0x187741b2, (q31_t)0x825c25a1, (q31_t)0x187116d4, (q31_t)0x825af255, (q31_t)0x186aebe6, (q31_t)0x8259bf57, + (q31_t)0x1864c0ea, (q31_t)0x82588ca7, (q31_t)0x185e95de, (q31_t)0x82575a44, (q31_t)0x18586ac3, (q31_t)0x8256282e, (q31_t)0x18523f9a, (q31_t)0x8254f666, + (q31_t)0x184c1461, (q31_t)0x8253c4eb, (q31_t)0x1845e919, (q31_t)0x825293be, (q31_t)0x183fbdc3, (q31_t)0x825162df, (q31_t)0x1839925d, (q31_t)0x8250324d, + (q31_t)0x183366e9, (q31_t)0x824f0208, (q31_t)0x182d3b65, (q31_t)0x824dd211, (q31_t)0x18270fd3, (q31_t)0x824ca268, (q31_t)0x1820e431, (q31_t)0x824b730c, + (q31_t)0x181ab881, (q31_t)0x824a43fe, (q31_t)0x18148cc2, (q31_t)0x8249153d, (q31_t)0x180e60f4, (q31_t)0x8247e6ca, (q31_t)0x18083518, (q31_t)0x8246b8a4, + (q31_t)0x1802092c, (q31_t)0x82458acc, (q31_t)0x17fbdd32, (q31_t)0x82445d41, (q31_t)0x17f5b129, (q31_t)0x82433004, (q31_t)0x17ef8511, (q31_t)0x82420315, + (q31_t)0x17e958ea, (q31_t)0x8240d673, (q31_t)0x17e32cb5, (q31_t)0x823faa1e, (q31_t)0x17dd0070, (q31_t)0x823e7e18, (q31_t)0x17d6d41d, (q31_t)0x823d525e, + (q31_t)0x17d0a7bc, (q31_t)0x823c26f3, (q31_t)0x17ca7b4c, (q31_t)0x823afbd5, (q31_t)0x17c44ecd, (q31_t)0x8239d104, (q31_t)0x17be223f, (q31_t)0x8238a681, + (q31_t)0x17b7f5a3, (q31_t)0x82377c4c, (q31_t)0x17b1c8f8, (q31_t)0x82365264, (q31_t)0x17ab9c3e, (q31_t)0x823528ca, (q31_t)0x17a56f76, (q31_t)0x8233ff7e, + (q31_t)0x179f429f, (q31_t)0x8232d67f, (q31_t)0x179915ba, (q31_t)0x8231adce, (q31_t)0x1792e8c6, (q31_t)0x8230856a, (q31_t)0x178cbbc4, (q31_t)0x822f5d54, + (q31_t)0x17868eb3, (q31_t)0x822e358b, (q31_t)0x17806194, (q31_t)0x822d0e10, (q31_t)0x177a3466, (q31_t)0x822be6e3, (q31_t)0x17740729, (q31_t)0x822ac004, + (q31_t)0x176dd9de, (q31_t)0x82299971, (q31_t)0x1767ac85, (q31_t)0x8228732d, (q31_t)0x17617f1d, (q31_t)0x82274d36, (q31_t)0x175b51a7, (q31_t)0x8226278d, + (q31_t)0x17552422, (q31_t)0x82250232, (q31_t)0x174ef68f, (q31_t)0x8223dd24, (q31_t)0x1748c8ee, (q31_t)0x8222b863, (q31_t)0x17429b3e, (q31_t)0x822193f1, + (q31_t)0x173c6d80, (q31_t)0x82206fcc, (q31_t)0x17363fb4, (q31_t)0x821f4bf5, (q31_t)0x173011d9, (q31_t)0x821e286b, (q31_t)0x1729e3f0, (q31_t)0x821d052f, + (q31_t)0x1723b5f9, (q31_t)0x821be240, (q31_t)0x171d87f3, (q31_t)0x821abfa0, (q31_t)0x171759df, (q31_t)0x82199d4d, (q31_t)0x17112bbd, (q31_t)0x82187b47, + (q31_t)0x170afd8d, (q31_t)0x82175990, (q31_t)0x1704cf4f, (q31_t)0x82163826, (q31_t)0x16fea102, (q31_t)0x82151709, (q31_t)0x16f872a7, (q31_t)0x8213f63a, + (q31_t)0x16f2443e, (q31_t)0x8212d5b9, (q31_t)0x16ec15c7, (q31_t)0x8211b586, (q31_t)0x16e5e741, (q31_t)0x821095a0, (q31_t)0x16dfb8ae, (q31_t)0x820f7608, + (q31_t)0x16d98a0c, (q31_t)0x820e56be, (q31_t)0x16d35b5c, (q31_t)0x820d37c1, (q31_t)0x16cd2c9f, (q31_t)0x820c1912, (q31_t)0x16c6fdd3, (q31_t)0x820afab1, + (q31_t)0x16c0cef9, (q31_t)0x8209dc9e, (q31_t)0x16baa011, (q31_t)0x8208bed8, (q31_t)0x16b4711b, (q31_t)0x8207a160, (q31_t)0x16ae4217, (q31_t)0x82068435, + (q31_t)0x16a81305, (q31_t)0x82056758, (q31_t)0x16a1e3e5, (q31_t)0x82044ac9, (q31_t)0x169bb4b7, (q31_t)0x82032e88, (q31_t)0x1695857b, (q31_t)0x82021294, + (q31_t)0x168f5632, (q31_t)0x8200f6ef, (q31_t)0x168926da, (q31_t)0x81ffdb96, (q31_t)0x1682f774, (q31_t)0x81fec08c, (q31_t)0x167cc801, (q31_t)0x81fda5cf, + (q31_t)0x1676987f, (q31_t)0x81fc8b60, (q31_t)0x167068f0, (q31_t)0x81fb713f, (q31_t)0x166a3953, (q31_t)0x81fa576c, (q31_t)0x166409a8, (q31_t)0x81f93de6, + (q31_t)0x165dd9f0, (q31_t)0x81f824ae, (q31_t)0x1657aa29, (q31_t)0x81f70bc3, (q31_t)0x16517a55, (q31_t)0x81f5f327, (q31_t)0x164b4a73, (q31_t)0x81f4dad8, + (q31_t)0x16451a83, (q31_t)0x81f3c2d7, (q31_t)0x163eea86, (q31_t)0x81f2ab24, (q31_t)0x1638ba7a, (q31_t)0x81f193be, (q31_t)0x16328a61, (q31_t)0x81f07ca6, + (q31_t)0x162c5a3b, (q31_t)0x81ef65dc, (q31_t)0x16262a06, (q31_t)0x81ee4f60, (q31_t)0x161ff9c4, (q31_t)0x81ed3932, (q31_t)0x1619c975, (q31_t)0x81ec2351, + (q31_t)0x16139918, (q31_t)0x81eb0dbe, (q31_t)0x160d68ad, (q31_t)0x81e9f879, (q31_t)0x16073834, (q31_t)0x81e8e381, (q31_t)0x160107ae, (q31_t)0x81e7ced8, + (q31_t)0x15fad71b, (q31_t)0x81e6ba7c, (q31_t)0x15f4a679, (q31_t)0x81e5a66e, (q31_t)0x15ee75cb, (q31_t)0x81e492ad, (q31_t)0x15e8450e, (q31_t)0x81e37f3b, + (q31_t)0x15e21445, (q31_t)0x81e26c16, (q31_t)0x15dbe36d, (q31_t)0x81e1593f, (q31_t)0x15d5b288, (q31_t)0x81e046b6, (q31_t)0x15cf8196, (q31_t)0x81df347b, + (q31_t)0x15c95097, (q31_t)0x81de228d, (q31_t)0x15c31f89, (q31_t)0x81dd10ee, (q31_t)0x15bcee6f, (q31_t)0x81dbff9c, (q31_t)0x15b6bd47, (q31_t)0x81daee98, + (q31_t)0x15b08c12, (q31_t)0x81d9dde1, (q31_t)0x15aa5acf, (q31_t)0x81d8cd79, (q31_t)0x15a4297f, (q31_t)0x81d7bd5e, (q31_t)0x159df821, (q31_t)0x81d6ad92, + (q31_t)0x1597c6b7, (q31_t)0x81d59e13, (q31_t)0x1591953e, (q31_t)0x81d48ee1, (q31_t)0x158b63b9, (q31_t)0x81d37ffe, (q31_t)0x15853226, (q31_t)0x81d27169, + (q31_t)0x157f0086, (q31_t)0x81d16321, (q31_t)0x1578ced9, (q31_t)0x81d05527, (q31_t)0x15729d1f, (q31_t)0x81cf477b, (q31_t)0x156c6b57, (q31_t)0x81ce3a1d, + (q31_t)0x15663982, (q31_t)0x81cd2d0c, (q31_t)0x156007a0, (q31_t)0x81cc204a, (q31_t)0x1559d5b1, (q31_t)0x81cb13d5, (q31_t)0x1553a3b4, (q31_t)0x81ca07af, + (q31_t)0x154d71aa, (q31_t)0x81c8fbd6, (q31_t)0x15473f94, (q31_t)0x81c7f04b, (q31_t)0x15410d70, (q31_t)0x81c6e50d, (q31_t)0x153adb3f, (q31_t)0x81c5da1e, + (q31_t)0x1534a901, (q31_t)0x81c4cf7d, (q31_t)0x152e76b5, (q31_t)0x81c3c529, (q31_t)0x1528445d, (q31_t)0x81c2bb23, (q31_t)0x152211f8, (q31_t)0x81c1b16b, + (q31_t)0x151bdf86, (q31_t)0x81c0a801, (q31_t)0x1515ad06, (q31_t)0x81bf9ee5, (q31_t)0x150f7a7a, (q31_t)0x81be9617, (q31_t)0x150947e1, (q31_t)0x81bd8d97, + (q31_t)0x1503153a, (q31_t)0x81bc8564, (q31_t)0x14fce287, (q31_t)0x81bb7d7f, (q31_t)0x14f6afc7, (q31_t)0x81ba75e9, (q31_t)0x14f07cf9, (q31_t)0x81b96ea0, + (q31_t)0x14ea4a1f, (q31_t)0x81b867a5, (q31_t)0x14e41738, (q31_t)0x81b760f8, (q31_t)0x14dde445, (q31_t)0x81b65a99, (q31_t)0x14d7b144, (q31_t)0x81b55488, + (q31_t)0x14d17e36, (q31_t)0x81b44ec4, (q31_t)0x14cb4b1c, (q31_t)0x81b3494f, (q31_t)0x14c517f4, (q31_t)0x81b24427, (q31_t)0x14bee4c0, (q31_t)0x81b13f4e, + (q31_t)0x14b8b17f, (q31_t)0x81b03ac2, (q31_t)0x14b27e32, (q31_t)0x81af3684, (q31_t)0x14ac4ad7, (q31_t)0x81ae3294, (q31_t)0x14a61770, (q31_t)0x81ad2ef2, + (q31_t)0x149fe3fc, (q31_t)0x81ac2b9e, (q31_t)0x1499b07c, (q31_t)0x81ab2898, (q31_t)0x14937cee, (q31_t)0x81aa25e0, (q31_t)0x148d4954, (q31_t)0x81a92376, + (q31_t)0x148715ae, (q31_t)0x81a82159, (q31_t)0x1480e1fa, (q31_t)0x81a71f8b, (q31_t)0x147aae3a, (q31_t)0x81a61e0b, (q31_t)0x14747a6d, (q31_t)0x81a51cd8, + (q31_t)0x146e4694, (q31_t)0x81a41bf4, (q31_t)0x146812ae, (q31_t)0x81a31b5d, (q31_t)0x1461debc, (q31_t)0x81a21b14, (q31_t)0x145baabd, (q31_t)0x81a11b1a, + (q31_t)0x145576b1, (q31_t)0x81a01b6d, (q31_t)0x144f4299, (q31_t)0x819f1c0e, (q31_t)0x14490e74, (q31_t)0x819e1cfd, (q31_t)0x1442da43, (q31_t)0x819d1e3a, + (q31_t)0x143ca605, (q31_t)0x819c1fc5, (q31_t)0x143671bb, (q31_t)0x819b219e, (q31_t)0x14303d65, (q31_t)0x819a23c5, (q31_t)0x142a0902, (q31_t)0x8199263a, + (q31_t)0x1423d492, (q31_t)0x819828fd, (q31_t)0x141da016, (q31_t)0x81972c0e, (q31_t)0x14176b8e, (q31_t)0x81962f6d, (q31_t)0x141136f9, (q31_t)0x8195331a, + (q31_t)0x140b0258, (q31_t)0x81943715, (q31_t)0x1404cdaa, (q31_t)0x81933b5e, (q31_t)0x13fe98f1, (q31_t)0x81923ff4, (q31_t)0x13f8642a, (q31_t)0x819144d9, + (q31_t)0x13f22f58, (q31_t)0x81904a0c, (q31_t)0x13ebfa79, (q31_t)0x818f4f8d, (q31_t)0x13e5c58e, (q31_t)0x818e555c, (q31_t)0x13df9097, (q31_t)0x818d5b78, + (q31_t)0x13d95b93, (q31_t)0x818c61e3, (q31_t)0x13d32683, (q31_t)0x818b689c, (q31_t)0x13ccf167, (q31_t)0x818a6fa3, (q31_t)0x13c6bc3f, (q31_t)0x818976f8, + (q31_t)0x13c0870a, (q31_t)0x81887e9a, (q31_t)0x13ba51ca, (q31_t)0x8187868b, (q31_t)0x13b41c7d, (q31_t)0x81868eca, (q31_t)0x13ade724, (q31_t)0x81859757, + (q31_t)0x13a7b1bf, (q31_t)0x8184a032, (q31_t)0x13a17c4d, (q31_t)0x8183a95b, (q31_t)0x139b46d0, (q31_t)0x8182b2d1, (q31_t)0x13951146, (q31_t)0x8181bc96, + (q31_t)0x138edbb1, (q31_t)0x8180c6a9, (q31_t)0x1388a60f, (q31_t)0x817fd10a, (q31_t)0x13827062, (q31_t)0x817edbb9, (q31_t)0x137c3aa8, (q31_t)0x817de6b6, + (q31_t)0x137604e2, (q31_t)0x817cf201, (q31_t)0x136fcf10, (q31_t)0x817bfd9b, (q31_t)0x13699933, (q31_t)0x817b0982, (q31_t)0x13636349, (q31_t)0x817a15b7, + (q31_t)0x135d2d53, (q31_t)0x8179223a, (q31_t)0x1356f752, (q31_t)0x81782f0b, (q31_t)0x1350c144, (q31_t)0x81773c2b, (q31_t)0x134a8b2b, (q31_t)0x81764998, + (q31_t)0x13445505, (q31_t)0x81755754, (q31_t)0x133e1ed4, (q31_t)0x8174655d, (q31_t)0x1337e897, (q31_t)0x817373b5, (q31_t)0x1331b24e, (q31_t)0x8172825a, + (q31_t)0x132b7bf9, (q31_t)0x8171914e, (q31_t)0x13254599, (q31_t)0x8170a090, (q31_t)0x131f0f2c, (q31_t)0x816fb020, (q31_t)0x1318d8b4, (q31_t)0x816ebffe, + (q31_t)0x1312a230, (q31_t)0x816dd02a, (q31_t)0x130c6ba0, (q31_t)0x816ce0a4, (q31_t)0x13063505, (q31_t)0x816bf16c, (q31_t)0x12fffe5d, (q31_t)0x816b0282, + (q31_t)0x12f9c7aa, (q31_t)0x816a13e6, (q31_t)0x12f390ec, (q31_t)0x81692599, (q31_t)0x12ed5a21, (q31_t)0x81683799, (q31_t)0x12e7234b, (q31_t)0x816749e8, + (q31_t)0x12e0ec6a, (q31_t)0x81665c84, (q31_t)0x12dab57c, (q31_t)0x81656f6f, (q31_t)0x12d47e83, (q31_t)0x816482a8, (q31_t)0x12ce477f, (q31_t)0x8163962f, + (q31_t)0x12c8106f, (q31_t)0x8162aa04, (q31_t)0x12c1d953, (q31_t)0x8161be27, (q31_t)0x12bba22b, (q31_t)0x8160d298, (q31_t)0x12b56af9, (q31_t)0x815fe758, + (q31_t)0x12af33ba, (q31_t)0x815efc65, (q31_t)0x12a8fc70, (q31_t)0x815e11c1, (q31_t)0x12a2c51b, (q31_t)0x815d276a, (q31_t)0x129c8dba, (q31_t)0x815c3d62, + (q31_t)0x1296564d, (q31_t)0x815b53a8, (q31_t)0x12901ed5, (q31_t)0x815a6a3c, (q31_t)0x1289e752, (q31_t)0x8159811e, (q31_t)0x1283afc3, (q31_t)0x8158984e, + (q31_t)0x127d7829, (q31_t)0x8157afcd, (q31_t)0x12774083, (q31_t)0x8156c799, (q31_t)0x127108d2, (q31_t)0x8155dfb4, (q31_t)0x126ad116, (q31_t)0x8154f81d, + (q31_t)0x1264994e, (q31_t)0x815410d4, (q31_t)0x125e617b, (q31_t)0x815329d9, (q31_t)0x1258299c, (q31_t)0x8152432c, (q31_t)0x1251f1b3, (q31_t)0x81515ccd, + (q31_t)0x124bb9be, (q31_t)0x815076bd, (q31_t)0x124581bd, (q31_t)0x814f90fb, (q31_t)0x123f49b2, (q31_t)0x814eab86, (q31_t)0x1239119b, (q31_t)0x814dc660, + (q31_t)0x1232d979, (q31_t)0x814ce188, (q31_t)0x122ca14b, (q31_t)0x814bfcff, (q31_t)0x12266913, (q31_t)0x814b18c3, (q31_t)0x122030cf, (q31_t)0x814a34d6, + (q31_t)0x1219f880, (q31_t)0x81495136, (q31_t)0x1213c026, (q31_t)0x81486de5, (q31_t)0x120d87c1, (q31_t)0x81478ae2, (q31_t)0x12074f50, (q31_t)0x8146a82e, + (q31_t)0x120116d5, (q31_t)0x8145c5c7, (q31_t)0x11fade4e, (q31_t)0x8144e3ae, (q31_t)0x11f4a5bd, (q31_t)0x814401e4, (q31_t)0x11ee6d20, (q31_t)0x81432068, + (q31_t)0x11e83478, (q31_t)0x81423f3a, (q31_t)0x11e1fbc5, (q31_t)0x81415e5a, (q31_t)0x11dbc307, (q31_t)0x81407dc9, (q31_t)0x11d58a3e, (q31_t)0x813f9d86, + (q31_t)0x11cf516a, (q31_t)0x813ebd90, (q31_t)0x11c9188b, (q31_t)0x813ddde9, (q31_t)0x11c2dfa2, (q31_t)0x813cfe91, (q31_t)0x11bca6ad, (q31_t)0x813c1f86, + (q31_t)0x11b66dad, (q31_t)0x813b40ca, (q31_t)0x11b034a2, (q31_t)0x813a625b, (q31_t)0x11a9fb8d, (q31_t)0x8139843b, (q31_t)0x11a3c26c, (q31_t)0x8138a66a, + (q31_t)0x119d8941, (q31_t)0x8137c8e6, (q31_t)0x1197500a, (q31_t)0x8136ebb1, (q31_t)0x119116c9, (q31_t)0x81360ec9, (q31_t)0x118add7d, (q31_t)0x81353230, + (q31_t)0x1184a427, (q31_t)0x813455e6, (q31_t)0x117e6ac5, (q31_t)0x813379e9, (q31_t)0x11783159, (q31_t)0x81329e3b, (q31_t)0x1171f7e2, (q31_t)0x8131c2db, + (q31_t)0x116bbe60, (q31_t)0x8130e7c9, (q31_t)0x116584d3, (q31_t)0x81300d05, (q31_t)0x115f4b3c, (q31_t)0x812f3290, (q31_t)0x1159119a, (q31_t)0x812e5868, + (q31_t)0x1152d7ed, (q31_t)0x812d7e8f, (q31_t)0x114c9e35, (q31_t)0x812ca505, (q31_t)0x11466473, (q31_t)0x812bcbc8, (q31_t)0x11402aa6, (q31_t)0x812af2da, + (q31_t)0x1139f0cf, (q31_t)0x812a1a3a, (q31_t)0x1133b6ed, (q31_t)0x812941e8, (q31_t)0x112d7d00, (q31_t)0x812869e4, (q31_t)0x11274309, (q31_t)0x8127922f, + (q31_t)0x11210907, (q31_t)0x8126bac8, (q31_t)0x111acefb, (q31_t)0x8125e3af, (q31_t)0x111494e4, (q31_t)0x81250ce4, (q31_t)0x110e5ac2, (q31_t)0x81243668, + (q31_t)0x11082096, (q31_t)0x8123603a, (q31_t)0x1101e65f, (q31_t)0x81228a5a, (q31_t)0x10fbac1e, (q31_t)0x8121b4c8, (q31_t)0x10f571d3, (q31_t)0x8120df85, + (q31_t)0x10ef377d, (q31_t)0x81200a90, (q31_t)0x10e8fd1c, (q31_t)0x811f35e9, (q31_t)0x10e2c2b2, (q31_t)0x811e6191, (q31_t)0x10dc883c, (q31_t)0x811d8d86, + (q31_t)0x10d64dbd, (q31_t)0x811cb9ca, (q31_t)0x10d01333, (q31_t)0x811be65d, (q31_t)0x10c9d89e, (q31_t)0x811b133d, (q31_t)0x10c39dff, (q31_t)0x811a406c, + (q31_t)0x10bd6356, (q31_t)0x81196de9, (q31_t)0x10b728a3, (q31_t)0x81189bb4, (q31_t)0x10b0ede5, (q31_t)0x8117c9ce, (q31_t)0x10aab31d, (q31_t)0x8116f836, + (q31_t)0x10a4784b, (q31_t)0x811626ec, (q31_t)0x109e3d6e, (q31_t)0x811555f1, (q31_t)0x10980287, (q31_t)0x81148544, (q31_t)0x1091c796, (q31_t)0x8113b4e5, + (q31_t)0x108b8c9b, (q31_t)0x8112e4d4, (q31_t)0x10855195, (q31_t)0x81121512, (q31_t)0x107f1686, (q31_t)0x8111459e, (q31_t)0x1078db6c, (q31_t)0x81107678, + (q31_t)0x1072a048, (q31_t)0x810fa7a0, (q31_t)0x106c651a, (q31_t)0x810ed917, (q31_t)0x106629e1, (q31_t)0x810e0adc, (q31_t)0x105fee9f, (q31_t)0x810d3cf0, + (q31_t)0x1059b352, (q31_t)0x810c6f52, (q31_t)0x105377fc, (q31_t)0x810ba202, (q31_t)0x104d3c9b, (q31_t)0x810ad500, (q31_t)0x10470130, (q31_t)0x810a084d, + (q31_t)0x1040c5bb, (q31_t)0x81093be8, (q31_t)0x103a8a3d, (q31_t)0x81086fd1, (q31_t)0x10344eb4, (q31_t)0x8107a409, (q31_t)0x102e1321, (q31_t)0x8106d88f, + (q31_t)0x1027d784, (q31_t)0x81060d63, (q31_t)0x10219bdd, (q31_t)0x81054286, (q31_t)0x101b602d, (q31_t)0x810477f7, (q31_t)0x10152472, (q31_t)0x8103adb6, + (q31_t)0x100ee8ad, (q31_t)0x8102e3c4, (q31_t)0x1008acdf, (q31_t)0x81021a20, (q31_t)0x10027107, (q31_t)0x810150ca, (q31_t)0xffc3524, (q31_t)0x810087c3, + (q31_t)0xff5f938, (q31_t)0x80ffbf0a, (q31_t)0xfefbd42, (q31_t)0x80fef69f, (q31_t)0xfe98143, (q31_t)0x80fe2e83, (q31_t)0xfe34539, (q31_t)0x80fd66b5, + (q31_t)0xfdd0926, (q31_t)0x80fc9f35, (q31_t)0xfd6cd08, (q31_t)0x80fbd804, (q31_t)0xfd090e1, (q31_t)0x80fb1121, (q31_t)0xfca54b1, (q31_t)0x80fa4a8c, + (q31_t)0xfc41876, (q31_t)0x80f98446, (q31_t)0xfbddc32, (q31_t)0x80f8be4e, (q31_t)0xfb79fe4, (q31_t)0x80f7f8a4, (q31_t)0xfb1638d, (q31_t)0x80f73349, + (q31_t)0xfab272b, (q31_t)0x80f66e3c, (q31_t)0xfa4eac0, (q31_t)0x80f5a97e, (q31_t)0xf9eae4c, (q31_t)0x80f4e50e, (q31_t)0xf9871ce, (q31_t)0x80f420ec, + (q31_t)0xf923546, (q31_t)0x80f35d19, (q31_t)0xf8bf8b4, (q31_t)0x80f29994, (q31_t)0xf85bc19, (q31_t)0x80f1d65d, (q31_t)0xf7f7f75, (q31_t)0x80f11375, + (q31_t)0xf7942c7, (q31_t)0x80f050db, (q31_t)0xf73060f, (q31_t)0x80ef8e90, (q31_t)0xf6cc94e, (q31_t)0x80eecc93, (q31_t)0xf668c83, (q31_t)0x80ee0ae4, + (q31_t)0xf604faf, (q31_t)0x80ed4984, (q31_t)0xf5a12d1, (q31_t)0x80ec8872, (q31_t)0xf53d5ea, (q31_t)0x80ebc7ae, (q31_t)0xf4d98f9, (q31_t)0x80eb0739, + (q31_t)0xf475bff, (q31_t)0x80ea4712, (q31_t)0xf411efb, (q31_t)0x80e9873a, (q31_t)0xf3ae1ee, (q31_t)0x80e8c7b0, (q31_t)0xf34a4d8, (q31_t)0x80e80874, + (q31_t)0xf2e67b8, (q31_t)0x80e74987, (q31_t)0xf282a8f, (q31_t)0x80e68ae8, (q31_t)0xf21ed5d, (q31_t)0x80e5cc98, (q31_t)0xf1bb021, (q31_t)0x80e50e96, + (q31_t)0xf1572dc, (q31_t)0x80e450e2, (q31_t)0xf0f358e, (q31_t)0x80e3937d, (q31_t)0xf08f836, (q31_t)0x80e2d666, (q31_t)0xf02bad5, (q31_t)0x80e2199e, + (q31_t)0xefc7d6b, (q31_t)0x80e15d24, (q31_t)0xef63ff7, (q31_t)0x80e0a0f8, (q31_t)0xef0027b, (q31_t)0x80dfe51b, (q31_t)0xee9c4f5, (q31_t)0x80df298c, + (q31_t)0xee38766, (q31_t)0x80de6e4c, (q31_t)0xedd49ce, (q31_t)0x80ddb35a, (q31_t)0xed70c2c, (q31_t)0x80dcf8b7, (q31_t)0xed0ce82, (q31_t)0x80dc3e62, + (q31_t)0xeca90ce, (q31_t)0x80db845b, (q31_t)0xec45311, (q31_t)0x80dacaa3, (q31_t)0xebe154b, (q31_t)0x80da1139, (q31_t)0xeb7d77c, (q31_t)0x80d9581e, + (q31_t)0xeb199a4, (q31_t)0x80d89f51, (q31_t)0xeab5bc3, (q31_t)0x80d7e6d3, (q31_t)0xea51dd8, (q31_t)0x80d72ea3, (q31_t)0xe9edfe5, (q31_t)0x80d676c1, + (q31_t)0xe98a1e9, (q31_t)0x80d5bf2e, (q31_t)0xe9263e3, (q31_t)0x80d507e9, (q31_t)0xe8c25d5, (q31_t)0x80d450f3, (q31_t)0xe85e7be, (q31_t)0x80d39a4b, + (q31_t)0xe7fa99e, (q31_t)0x80d2e3f2, (q31_t)0xe796b74, (q31_t)0x80d22de7, (q31_t)0xe732d42, (q31_t)0x80d1782a, (q31_t)0xe6cef07, (q31_t)0x80d0c2bc, + (q31_t)0xe66b0c3, (q31_t)0x80d00d9d, (q31_t)0xe607277, (q31_t)0x80cf58cc, (q31_t)0xe5a3421, (q31_t)0x80cea449, (q31_t)0xe53f5c2, (q31_t)0x80cdf015, + (q31_t)0xe4db75b, (q31_t)0x80cd3c2f, (q31_t)0xe4778eb, (q31_t)0x80cc8898, (q31_t)0xe413a72, (q31_t)0x80cbd54f, (q31_t)0xe3afbf0, (q31_t)0x80cb2255, + (q31_t)0xe34bd66, (q31_t)0x80ca6fa9, (q31_t)0xe2e7ed2, (q31_t)0x80c9bd4c, (q31_t)0xe284036, (q31_t)0x80c90b3d, (q31_t)0xe220191, (q31_t)0x80c8597c, + (q31_t)0xe1bc2e4, (q31_t)0x80c7a80a, (q31_t)0xe15842e, (q31_t)0x80c6f6e7, (q31_t)0xe0f456f, (q31_t)0x80c64612, (q31_t)0xe0906a7, (q31_t)0x80c5958b, + (q31_t)0xe02c7d7, (q31_t)0x80c4e553, (q31_t)0xdfc88fe, (q31_t)0x80c4356a, (q31_t)0xdf64a1c, (q31_t)0x80c385cf, (q31_t)0xdf00b32, (q31_t)0x80c2d682, + (q31_t)0xde9cc40, (q31_t)0x80c22784, (q31_t)0xde38d44, (q31_t)0x80c178d4, (q31_t)0xddd4e40, (q31_t)0x80c0ca73, (q31_t)0xdd70f34, (q31_t)0x80c01c60, + (q31_t)0xdd0d01f, (q31_t)0x80bf6e9c, (q31_t)0xdca9102, (q31_t)0x80bec127, (q31_t)0xdc451dc, (q31_t)0x80be13ff, (q31_t)0xdbe12ad, (q31_t)0x80bd6727, + (q31_t)0xdb7d376, (q31_t)0x80bcba9d, (q31_t)0xdb19437, (q31_t)0x80bc0e61, (q31_t)0xdab54ef, (q31_t)0x80bb6274, (q31_t)0xda5159f, (q31_t)0x80bab6d5, + (q31_t)0xd9ed646, (q31_t)0x80ba0b85, (q31_t)0xd9896e5, (q31_t)0x80b96083, (q31_t)0xd92577b, (q31_t)0x80b8b5d0, (q31_t)0xd8c1809, (q31_t)0x80b80b6c, + (q31_t)0xd85d88f, (q31_t)0x80b76156, (q31_t)0xd7f990c, (q31_t)0x80b6b78e, (q31_t)0xd795982, (q31_t)0x80b60e15, (q31_t)0xd7319ee, (q31_t)0x80b564ea, + (q31_t)0xd6cda53, (q31_t)0x80b4bc0e, (q31_t)0xd669aaf, (q31_t)0x80b41381, (q31_t)0xd605b03, (q31_t)0x80b36b42, (q31_t)0xd5a1b4f, (q31_t)0x80b2c351, + (q31_t)0xd53db92, (q31_t)0x80b21baf, (q31_t)0xd4d9bcd, (q31_t)0x80b1745c, (q31_t)0xd475c00, (q31_t)0x80b0cd57, (q31_t)0xd411c2b, (q31_t)0x80b026a1, + (q31_t)0xd3adc4e, (q31_t)0x80af8039, (q31_t)0xd349c68, (q31_t)0x80aeda20, (q31_t)0xd2e5c7b, (q31_t)0x80ae3455, (q31_t)0xd281c85, (q31_t)0x80ad8ed9, + (q31_t)0xd21dc87, (q31_t)0x80ace9ab, (q31_t)0xd1b9c81, (q31_t)0x80ac44cc, (q31_t)0xd155c73, (q31_t)0x80aba03b, (q31_t)0xd0f1c5d, (q31_t)0x80aafbf9, + (q31_t)0xd08dc3f, (q31_t)0x80aa5806, (q31_t)0xd029c18, (q31_t)0x80a9b461, (q31_t)0xcfc5bea, (q31_t)0x80a9110b, (q31_t)0xcf61bb4, (q31_t)0x80a86e03, + (q31_t)0xcefdb76, (q31_t)0x80a7cb49, (q31_t)0xce99b2f, (q31_t)0x80a728df, (q31_t)0xce35ae1, (q31_t)0x80a686c2, (q31_t)0xcdd1a8b, (q31_t)0x80a5e4f5, + (q31_t)0xcd6da2d, (q31_t)0x80a54376, (q31_t)0xcd099c7, (q31_t)0x80a4a245, (q31_t)0xcca5959, (q31_t)0x80a40163, (q31_t)0xcc418e3, (q31_t)0x80a360d0, + (q31_t)0xcbdd865, (q31_t)0x80a2c08b, (q31_t)0xcb797e0, (q31_t)0x80a22095, (q31_t)0xcb15752, (q31_t)0x80a180ed, (q31_t)0xcab16bd, (q31_t)0x80a0e194, + (q31_t)0xca4d620, (q31_t)0x80a04289, (q31_t)0xc9e957b, (q31_t)0x809fa3cd, (q31_t)0xc9854cf, (q31_t)0x809f0560, (q31_t)0xc92141a, (q31_t)0x809e6741, + (q31_t)0xc8bd35e, (q31_t)0x809dc971, (q31_t)0xc85929a, (q31_t)0x809d2bef, (q31_t)0xc7f51cf, (q31_t)0x809c8ebc, (q31_t)0xc7910fb, (q31_t)0x809bf1d7, + (q31_t)0xc72d020, (q31_t)0x809b5541, (q31_t)0xc6c8f3e, (q31_t)0x809ab8fa, (q31_t)0xc664e53, (q31_t)0x809a1d01, (q31_t)0xc600d61, (q31_t)0x80998157, + (q31_t)0xc59cc68, (q31_t)0x8098e5fb, (q31_t)0xc538b66, (q31_t)0x80984aee, (q31_t)0xc4d4a5d, (q31_t)0x8097b030, (q31_t)0xc47094d, (q31_t)0x809715c0, + (q31_t)0xc40c835, (q31_t)0x80967b9f, (q31_t)0xc3a8715, (q31_t)0x8095e1cc, (q31_t)0xc3445ee, (q31_t)0x80954848, (q31_t)0xc2e04c0, (q31_t)0x8094af13, + (q31_t)0xc27c389, (q31_t)0x8094162c, (q31_t)0xc21824c, (q31_t)0x80937d93, (q31_t)0xc1b4107, (q31_t)0x8092e54a, (q31_t)0xc14ffba, (q31_t)0x80924d4f, + (q31_t)0xc0ebe66, (q31_t)0x8091b5a2, (q31_t)0xc087d0a, (q31_t)0x80911e44, (q31_t)0xc023ba7, (q31_t)0x80908735, (q31_t)0xbfbfa3d, (q31_t)0x808ff074, + (q31_t)0xbf5b8cb, (q31_t)0x808f5a02, (q31_t)0xbef7752, (q31_t)0x808ec3df, (q31_t)0xbe935d2, (q31_t)0x808e2e0a, (q31_t)0xbe2f44a, (q31_t)0x808d9884, + (q31_t)0xbdcb2bb, (q31_t)0x808d034c, (q31_t)0xbd67124, (q31_t)0x808c6e63, (q31_t)0xbd02f87, (q31_t)0x808bd9c9, (q31_t)0xbc9ede2, (q31_t)0x808b457d, + (q31_t)0xbc3ac35, (q31_t)0x808ab180, (q31_t)0xbbd6a82, (q31_t)0x808a1dd2, (q31_t)0xbb728c7, (q31_t)0x80898a72, (q31_t)0xbb0e705, (q31_t)0x8088f761, + (q31_t)0xbaaa53b, (q31_t)0x8088649e, (q31_t)0xba4636b, (q31_t)0x8087d22a, (q31_t)0xb9e2193, (q31_t)0x80874005, (q31_t)0xb97dfb5, (q31_t)0x8086ae2e, + (q31_t)0xb919dcf, (q31_t)0x80861ca6, (q31_t)0xb8b5be1, (q31_t)0x80858b6c, (q31_t)0xb8519ed, (q31_t)0x8084fa82, (q31_t)0xb7ed7f2, (q31_t)0x808469e5, + (q31_t)0xb7895f0, (q31_t)0x8083d998, (q31_t)0xb7253e6, (q31_t)0x80834999, (q31_t)0xb6c11d5, (q31_t)0x8082b9e9, (q31_t)0xb65cfbe, (q31_t)0x80822a87, + (q31_t)0xb5f8d9f, (q31_t)0x80819b74, (q31_t)0xb594b7a, (q31_t)0x80810cb0, (q31_t)0xb53094d, (q31_t)0x80807e3a, (q31_t)0xb4cc719, (q31_t)0x807ff013, + (q31_t)0xb4684df, (q31_t)0x807f623b, (q31_t)0xb40429d, (q31_t)0x807ed4b1, (q31_t)0xb3a0055, (q31_t)0x807e4776, (q31_t)0xb33be05, (q31_t)0x807dba89, + (q31_t)0xb2d7baf, (q31_t)0x807d2dec, (q31_t)0xb273952, (q31_t)0x807ca19c, (q31_t)0xb20f6ee, (q31_t)0x807c159c, (q31_t)0xb1ab483, (q31_t)0x807b89ea, + (q31_t)0xb147211, (q31_t)0x807afe87, (q31_t)0xb0e2f98, (q31_t)0x807a7373, (q31_t)0xb07ed19, (q31_t)0x8079e8ad, (q31_t)0xb01aa92, (q31_t)0x80795e36, + (q31_t)0xafb6805, (q31_t)0x8078d40d, (q31_t)0xaf52571, (q31_t)0x80784a33, (q31_t)0xaeee2d7, (q31_t)0x8077c0a8, (q31_t)0xae8a036, (q31_t)0x8077376c, + (q31_t)0xae25d8d, (q31_t)0x8076ae7e, (q31_t)0xadc1adf, (q31_t)0x807625df, (q31_t)0xad5d829, (q31_t)0x80759d8e, (q31_t)0xacf956d, (q31_t)0x8075158c, + (q31_t)0xac952aa, (q31_t)0x80748dd9, (q31_t)0xac30fe1, (q31_t)0x80740675, (q31_t)0xabccd11, (q31_t)0x80737f5f, (q31_t)0xab68a3a, (q31_t)0x8072f898, + (q31_t)0xab0475c, (q31_t)0x8072721f, (q31_t)0xaaa0478, (q31_t)0x8071ebf6, (q31_t)0xaa3c18e, (q31_t)0x8071661a, (q31_t)0xa9d7e9d, (q31_t)0x8070e08e, + (q31_t)0xa973ba5, (q31_t)0x80705b50, (q31_t)0xa90f8a7, (q31_t)0x806fd661, (q31_t)0xa8ab5a2, (q31_t)0x806f51c1, (q31_t)0xa847297, (q31_t)0x806ecd6f, + (q31_t)0xa7e2f85, (q31_t)0x806e496c, (q31_t)0xa77ec6d, (q31_t)0x806dc5b8, (q31_t)0xa71a94f, (q31_t)0x806d4253, (q31_t)0xa6b662a, (q31_t)0x806cbf3c, + (q31_t)0xa6522fe, (q31_t)0x806c3c74, (q31_t)0xa5edfcc, (q31_t)0x806bb9fa, (q31_t)0xa589c94, (q31_t)0x806b37cf, (q31_t)0xa525955, (q31_t)0x806ab5f3, + (q31_t)0xa4c1610, (q31_t)0x806a3466, (q31_t)0xa45d2c5, (q31_t)0x8069b327, (q31_t)0xa3f8f73, (q31_t)0x80693237, (q31_t)0xa394c1b, (q31_t)0x8068b196, + (q31_t)0xa3308bd, (q31_t)0x80683143, (q31_t)0xa2cc558, (q31_t)0x8067b13f, (q31_t)0xa2681ed, (q31_t)0x8067318a, (q31_t)0xa203e7c, (q31_t)0x8066b224, + (q31_t)0xa19fb04, (q31_t)0x8066330c, (q31_t)0xa13b787, (q31_t)0x8065b443, (q31_t)0xa0d7403, (q31_t)0x806535c9, (q31_t)0xa073079, (q31_t)0x8064b79d, + (q31_t)0xa00ece8, (q31_t)0x806439c0, (q31_t)0x9faa952, (q31_t)0x8063bc32, (q31_t)0x9f465b5, (q31_t)0x80633ef3, (q31_t)0x9ee2213, (q31_t)0x8062c202, + (q31_t)0x9e7de6a, (q31_t)0x80624560, (q31_t)0x9e19abb, (q31_t)0x8061c90c, (q31_t)0x9db5706, (q31_t)0x80614d08, (q31_t)0x9d5134b, (q31_t)0x8060d152, + (q31_t)0x9cecf89, (q31_t)0x806055eb, (q31_t)0x9c88bc2, (q31_t)0x805fdad2, (q31_t)0x9c247f5, (q31_t)0x805f6009, (q31_t)0x9bc0421, (q31_t)0x805ee58e, + (q31_t)0x9b5c048, (q31_t)0x805e6b62, (q31_t)0x9af7c69, (q31_t)0x805df184, (q31_t)0x9a93884, (q31_t)0x805d77f5, (q31_t)0x9a2f498, (q31_t)0x805cfeb5, + (q31_t)0x99cb0a7, (q31_t)0x805c85c4, (q31_t)0x9966cb0, (q31_t)0x805c0d21, (q31_t)0x99028b3, (q31_t)0x805b94ce, (q31_t)0x989e4b0, (q31_t)0x805b1cc8, + (q31_t)0x983a0a7, (q31_t)0x805aa512, (q31_t)0x97d5c99, (q31_t)0x805a2daa, (q31_t)0x9771884, (q31_t)0x8059b692, (q31_t)0x970d46a, (q31_t)0x80593fc7, + (q31_t)0x96a9049, (q31_t)0x8058c94c, (q31_t)0x9644c23, (q31_t)0x8058531f, (q31_t)0x95e07f8, (q31_t)0x8057dd41, (q31_t)0x957c3c6, (q31_t)0x805767b2, + (q31_t)0x9517f8f, (q31_t)0x8056f272, (q31_t)0x94b3b52, (q31_t)0x80567d80, (q31_t)0x944f70f, (q31_t)0x805608dd, (q31_t)0x93eb2c6, (q31_t)0x80559489, + (q31_t)0x9386e78, (q31_t)0x80552084, (q31_t)0x9322a24, (q31_t)0x8054accd, (q31_t)0x92be5ca, (q31_t)0x80543965, (q31_t)0x925a16b, (q31_t)0x8053c64c, + (q31_t)0x91f5d06, (q31_t)0x80535381, (q31_t)0x919189c, (q31_t)0x8052e106, (q31_t)0x912d42c, (q31_t)0x80526ed9, (q31_t)0x90c8fb6, (q31_t)0x8051fcfb, + (q31_t)0x9064b3a, (q31_t)0x80518b6b, (q31_t)0x90006ba, (q31_t)0x80511a2b, (q31_t)0x8f9c233, (q31_t)0x8050a939, (q31_t)0x8f37da7, (q31_t)0x80503896, + (q31_t)0x8ed3916, (q31_t)0x804fc841, (q31_t)0x8e6f47f, (q31_t)0x804f583c, (q31_t)0x8e0afe2, (q31_t)0x804ee885, (q31_t)0x8da6b40, (q31_t)0x804e791d, + (q31_t)0x8d42699, (q31_t)0x804e0a04, (q31_t)0x8cde1ec, (q31_t)0x804d9b39, (q31_t)0x8c79d3a, (q31_t)0x804d2cbd, (q31_t)0x8c15882, (q31_t)0x804cbe90, + (q31_t)0x8bb13c5, (q31_t)0x804c50b2, (q31_t)0x8b4cf02, (q31_t)0x804be323, (q31_t)0x8ae8a3a, (q31_t)0x804b75e2, (q31_t)0x8a8456d, (q31_t)0x804b08f0, + (q31_t)0x8a2009a, (q31_t)0x804a9c4d, (q31_t)0x89bbbc3, (q31_t)0x804a2ff9, (q31_t)0x89576e5, (q31_t)0x8049c3f3, (q31_t)0x88f3203, (q31_t)0x8049583d, + (q31_t)0x888ed1b, (q31_t)0x8048ecd5, (q31_t)0x882a82e, (q31_t)0x804881bb, (q31_t)0x87c633c, (q31_t)0x804816f1, (q31_t)0x8761e44, (q31_t)0x8047ac75, + (q31_t)0x86fd947, (q31_t)0x80474248, (q31_t)0x8699445, (q31_t)0x8046d86a, (q31_t)0x8634f3e, (q31_t)0x80466edb, (q31_t)0x85d0a32, (q31_t)0x8046059b, + (q31_t)0x856c520, (q31_t)0x80459ca9, (q31_t)0x850800a, (q31_t)0x80453406, (q31_t)0x84a3aee, (q31_t)0x8044cbb2, (q31_t)0x843f5cd, (q31_t)0x804463ad, + (q31_t)0x83db0a7, (q31_t)0x8043fbf6, (q31_t)0x8376b7c, (q31_t)0x8043948e, (q31_t)0x831264c, (q31_t)0x80432d75, (q31_t)0x82ae117, (q31_t)0x8042c6ab, + (q31_t)0x8249bdd, (q31_t)0x80426030, (q31_t)0x81e569d, (q31_t)0x8041fa03, (q31_t)0x8181159, (q31_t)0x80419425, (q31_t)0x811cc10, (q31_t)0x80412e96, + (q31_t)0x80b86c2, (q31_t)0x8040c956, (q31_t)0x805416e, (q31_t)0x80406465, (q31_t)0x7fefc16, (q31_t)0x803fffc2, (q31_t)0x7f8b6b9, (q31_t)0x803f9b6f, + (q31_t)0x7f27157, (q31_t)0x803f376a, (q31_t)0x7ec2bf0, (q31_t)0x803ed3b3, (q31_t)0x7e5e685, (q31_t)0x803e704c, (q31_t)0x7dfa114, (q31_t)0x803e0d34, + (q31_t)0x7d95b9e, (q31_t)0x803daa6a, (q31_t)0x7d31624, (q31_t)0x803d47ef, (q31_t)0x7ccd0a5, (q31_t)0x803ce5c3, (q31_t)0x7c68b21, (q31_t)0x803c83e5, + (q31_t)0x7c04598, (q31_t)0x803c2257, (q31_t)0x7ba000b, (q31_t)0x803bc117, (q31_t)0x7b3ba78, (q31_t)0x803b6026, (q31_t)0x7ad74e1, (q31_t)0x803aff84, + (q31_t)0x7a72f45, (q31_t)0x803a9f31, (q31_t)0x7a0e9a5, (q31_t)0x803a3f2d, (q31_t)0x79aa400, (q31_t)0x8039df77, (q31_t)0x7945e56, (q31_t)0x80398010, + (q31_t)0x78e18a7, (q31_t)0x803920f8, (q31_t)0x787d2f4, (q31_t)0x8038c22f, (q31_t)0x7818d3c, (q31_t)0x803863b5, (q31_t)0x77b4780, (q31_t)0x80380589, + (q31_t)0x77501be, (q31_t)0x8037a7ac, (q31_t)0x76ebbf9, (q31_t)0x80374a1f, (q31_t)0x768762e, (q31_t)0x8036ece0, (q31_t)0x762305f, (q31_t)0x80368fef, + (q31_t)0x75bea8c, (q31_t)0x8036334e, (q31_t)0x755a4b4, (q31_t)0x8035d6fb, (q31_t)0x74f5ed7, (q31_t)0x80357af8, (q31_t)0x74918f6, (q31_t)0x80351f43, + (q31_t)0x742d311, (q31_t)0x8034c3dd, (q31_t)0x73c8d27, (q31_t)0x803468c5, (q31_t)0x7364738, (q31_t)0x80340dfd, (q31_t)0x7300145, (q31_t)0x8033b383, + (q31_t)0x729bb4e, (q31_t)0x80335959, (q31_t)0x7237552, (q31_t)0x8032ff7d, (q31_t)0x71d2f52, (q31_t)0x8032a5ef, (q31_t)0x716e94e, (q31_t)0x80324cb1, + (q31_t)0x710a345, (q31_t)0x8031f3c2, (q31_t)0x70a5d37, (q31_t)0x80319b21, (q31_t)0x7041726, (q31_t)0x803142cf, (q31_t)0x6fdd110, (q31_t)0x8030eacd, + (q31_t)0x6f78af6, (q31_t)0x80309318, (q31_t)0x6f144d7, (q31_t)0x80303bb3, (q31_t)0x6eafeb4, (q31_t)0x802fe49d, (q31_t)0x6e4b88d, (q31_t)0x802f8dd5, + (q31_t)0x6de7262, (q31_t)0x802f375d, (q31_t)0x6d82c32, (q31_t)0x802ee133, (q31_t)0x6d1e5fe, (q31_t)0x802e8b58, (q31_t)0x6cb9fc6, (q31_t)0x802e35cb, + (q31_t)0x6c5598a, (q31_t)0x802de08e, (q31_t)0x6bf1349, (q31_t)0x802d8ba0, (q31_t)0x6b8cd05, (q31_t)0x802d3700, (q31_t)0x6b286bc, (q31_t)0x802ce2af, + (q31_t)0x6ac406f, (q31_t)0x802c8ead, (q31_t)0x6a5fa1e, (q31_t)0x802c3afa, (q31_t)0x69fb3c9, (q31_t)0x802be796, (q31_t)0x6996d70, (q31_t)0x802b9480, + (q31_t)0x6932713, (q31_t)0x802b41ba, (q31_t)0x68ce0b2, (q31_t)0x802aef42, (q31_t)0x6869a4c, (q31_t)0x802a9d19, (q31_t)0x68053e3, (q31_t)0x802a4b3f, + (q31_t)0x67a0d76, (q31_t)0x8029f9b4, (q31_t)0x673c704, (q31_t)0x8029a878, (q31_t)0x66d808f, (q31_t)0x8029578b, (q31_t)0x6673a16, (q31_t)0x802906ec, + (q31_t)0x660f398, (q31_t)0x8028b69c, (q31_t)0x65aad17, (q31_t)0x8028669b, (q31_t)0x6546692, (q31_t)0x802816e9, (q31_t)0x64e2009, (q31_t)0x8027c786, + (q31_t)0x647d97c, (q31_t)0x80277872, (q31_t)0x64192eb, (q31_t)0x802729ad, (q31_t)0x63b4c57, (q31_t)0x8026db36, (q31_t)0x63505be, (q31_t)0x80268d0e, + (q31_t)0x62ebf22, (q31_t)0x80263f36, (q31_t)0x6287882, (q31_t)0x8025f1ac, (q31_t)0x62231de, (q31_t)0x8025a471, (q31_t)0x61beb36, (q31_t)0x80255784, + (q31_t)0x615a48b, (q31_t)0x80250ae7, (q31_t)0x60f5ddc, (q31_t)0x8024be99, (q31_t)0x6091729, (q31_t)0x80247299, (q31_t)0x602d072, (q31_t)0x802426e8, + (q31_t)0x5fc89b8, (q31_t)0x8023db86, (q31_t)0x5f642fa, (q31_t)0x80239073, (q31_t)0x5effc38, (q31_t)0x802345af, (q31_t)0x5e9b572, (q31_t)0x8022fb3a, + (q31_t)0x5e36ea9, (q31_t)0x8022b114, (q31_t)0x5dd27dd, (q31_t)0x8022673c, (q31_t)0x5d6e10c, (q31_t)0x80221db3, (q31_t)0x5d09a38, (q31_t)0x8021d47a, + (q31_t)0x5ca5361, (q31_t)0x80218b8f, (q31_t)0x5c40c86, (q31_t)0x802142f3, (q31_t)0x5bdc5a7, (q31_t)0x8020faa6, (q31_t)0x5b77ec5, (q31_t)0x8020b2a7, + (q31_t)0x5b137df, (q31_t)0x80206af8, (q31_t)0x5aaf0f6, (q31_t)0x80202397, (q31_t)0x5a4aa09, (q31_t)0x801fdc86, (q31_t)0x59e6319, (q31_t)0x801f95c3, + (q31_t)0x5981c26, (q31_t)0x801f4f4f, (q31_t)0x591d52f, (q31_t)0x801f092a, (q31_t)0x58b8e34, (q31_t)0x801ec354, (q31_t)0x5854736, (q31_t)0x801e7dcd, + (q31_t)0x57f0035, (q31_t)0x801e3895, (q31_t)0x578b930, (q31_t)0x801df3ab, (q31_t)0x5727228, (q31_t)0x801daf11, (q31_t)0x56c2b1c, (q31_t)0x801d6ac5, + (q31_t)0x565e40d, (q31_t)0x801d26c8, (q31_t)0x55f9cfb, (q31_t)0x801ce31a, (q31_t)0x55955e6, (q31_t)0x801c9fbb, (q31_t)0x5530ecd, (q31_t)0x801c5cab, + (q31_t)0x54cc7b1, (q31_t)0x801c19ea, (q31_t)0x5468092, (q31_t)0x801bd777, (q31_t)0x540396f, (q31_t)0x801b9554, (q31_t)0x539f249, (q31_t)0x801b537f, + (q31_t)0x533ab20, (q31_t)0x801b11fa, (q31_t)0x52d63f4, (q31_t)0x801ad0c3, (q31_t)0x5271cc4, (q31_t)0x801a8fdb, (q31_t)0x520d592, (q31_t)0x801a4f42, + (q31_t)0x51a8e5c, (q31_t)0x801a0ef8, (q31_t)0x5144723, (q31_t)0x8019cefd, (q31_t)0x50dffe7, (q31_t)0x80198f50, (q31_t)0x507b8a8, (q31_t)0x80194ff3, + (q31_t)0x5017165, (q31_t)0x801910e4, (q31_t)0x4fb2a20, (q31_t)0x8018d225, (q31_t)0x4f4e2d8, (q31_t)0x801893b4, (q31_t)0x4ee9b8c, (q31_t)0x80185592, + (q31_t)0x4e8543e, (q31_t)0x801817bf, (q31_t)0x4e20cec, (q31_t)0x8017da3b, (q31_t)0x4dbc597, (q31_t)0x80179d06, (q31_t)0x4d57e40, (q31_t)0x80176020, + (q31_t)0x4cf36e5, (q31_t)0x80172388, (q31_t)0x4c8ef88, (q31_t)0x8016e740, (q31_t)0x4c2a827, (q31_t)0x8016ab46, (q31_t)0x4bc60c4, (q31_t)0x80166f9c, + (q31_t)0x4b6195d, (q31_t)0x80163440, (q31_t)0x4afd1f4, (q31_t)0x8015f933, (q31_t)0x4a98a88, (q31_t)0x8015be75, (q31_t)0x4a34319, (q31_t)0x80158406, + (q31_t)0x49cfba7, (q31_t)0x801549e6, (q31_t)0x496b432, (q31_t)0x80151015, (q31_t)0x4906cbb, (q31_t)0x8014d693, (q31_t)0x48a2540, (q31_t)0x80149d5f, + (q31_t)0x483ddc3, (q31_t)0x8014647b, (q31_t)0x47d9643, (q31_t)0x80142be5, (q31_t)0x4774ec1, (q31_t)0x8013f39e, (q31_t)0x471073b, (q31_t)0x8013bba7, + (q31_t)0x46abfb3, (q31_t)0x801383fe, (q31_t)0x4647828, (q31_t)0x80134ca4, (q31_t)0x45e309a, (q31_t)0x80131599, (q31_t)0x457e90a, (q31_t)0x8012dedd, + (q31_t)0x451a177, (q31_t)0x8012a86f, (q31_t)0x44b59e1, (q31_t)0x80127251, (q31_t)0x4451249, (q31_t)0x80123c82, (q31_t)0x43ecaae, (q31_t)0x80120701, + (q31_t)0x4388310, (q31_t)0x8011d1d0, (q31_t)0x4323b70, (q31_t)0x80119ced, (q31_t)0x42bf3cd, (q31_t)0x80116859, (q31_t)0x425ac28, (q31_t)0x80113414, + (q31_t)0x41f6480, (q31_t)0x8011001f, (q31_t)0x4191cd5, (q31_t)0x8010cc78, (q31_t)0x412d528, (q31_t)0x8010991f, (q31_t)0x40c8d79, (q31_t)0x80106616, + (q31_t)0x40645c7, (q31_t)0x8010335c, (q31_t)0x3fffe12, (q31_t)0x801000f1, (q31_t)0x3f9b65b, (q31_t)0x800fced4, (q31_t)0x3f36ea2, (q31_t)0x800f9d07, + (q31_t)0x3ed26e6, (q31_t)0x800f6b88, (q31_t)0x3e6df28, (q31_t)0x800f3a59, (q31_t)0x3e09767, (q31_t)0x800f0978, (q31_t)0x3da4fa4, (q31_t)0x800ed8e6, + (q31_t)0x3d407df, (q31_t)0x800ea8a3, (q31_t)0x3cdc017, (q31_t)0x800e78af, (q31_t)0x3c7784d, (q31_t)0x800e490a, (q31_t)0x3c13080, (q31_t)0x800e19b4, + (q31_t)0x3bae8b2, (q31_t)0x800deaad, (q31_t)0x3b4a0e0, (q31_t)0x800dbbf5, (q31_t)0x3ae590d, (q31_t)0x800d8d8b, (q31_t)0x3a81137, (q31_t)0x800d5f71, + (q31_t)0x3a1c960, (q31_t)0x800d31a5, (q31_t)0x39b8185, (q31_t)0x800d0429, (q31_t)0x39539a9, (q31_t)0x800cd6fb, (q31_t)0x38ef1ca, (q31_t)0x800caa1c, + (q31_t)0x388a9ea, (q31_t)0x800c7d8c, (q31_t)0x3826207, (q31_t)0x800c514c, (q31_t)0x37c1a22, (q31_t)0x800c255a, (q31_t)0x375d23a, (q31_t)0x800bf9b7, + (q31_t)0x36f8a51, (q31_t)0x800bce63, (q31_t)0x3694265, (q31_t)0x800ba35d, (q31_t)0x362fa78, (q31_t)0x800b78a7, (q31_t)0x35cb288, (q31_t)0x800b4e40, + (q31_t)0x3566a96, (q31_t)0x800b2427, (q31_t)0x35022a2, (q31_t)0x800afa5e, (q31_t)0x349daac, (q31_t)0x800ad0e3, (q31_t)0x34392b4, (q31_t)0x800aa7b8, + (q31_t)0x33d4abb, (q31_t)0x800a7edb, (q31_t)0x33702bf, (q31_t)0x800a564e, (q31_t)0x330bac1, (q31_t)0x800a2e0f, (q31_t)0x32a72c1, (q31_t)0x800a061f, + (q31_t)0x3242abf, (q31_t)0x8009de7e, (q31_t)0x31de2bb, (q31_t)0x8009b72c, (q31_t)0x3179ab5, (q31_t)0x80099029, (q31_t)0x31152ae, (q31_t)0x80096975, + (q31_t)0x30b0aa4, (q31_t)0x80094310, (q31_t)0x304c299, (q31_t)0x80091cf9, (q31_t)0x2fe7a8c, (q31_t)0x8008f732, (q31_t)0x2f8327d, (q31_t)0x8008d1ba, + (q31_t)0x2f1ea6c, (q31_t)0x8008ac90, (q31_t)0x2eba259, (q31_t)0x800887b6, (q31_t)0x2e55a44, (q31_t)0x8008632a, (q31_t)0x2df122e, (q31_t)0x80083eed, + (q31_t)0x2d8ca16, (q31_t)0x80081b00, (q31_t)0x2d281fc, (q31_t)0x8007f761, (q31_t)0x2cc39e1, (q31_t)0x8007d411, (q31_t)0x2c5f1c3, (q31_t)0x8007b110, + (q31_t)0x2bfa9a4, (q31_t)0x80078e5e, (q31_t)0x2b96184, (q31_t)0x80076bfb, (q31_t)0x2b31961, (q31_t)0x800749e7, (q31_t)0x2acd13d, (q31_t)0x80072822, + (q31_t)0x2a68917, (q31_t)0x800706ac, (q31_t)0x2a040f0, (q31_t)0x8006e585, (q31_t)0x299f8c7, (q31_t)0x8006c4ac, (q31_t)0x293b09c, (q31_t)0x8006a423, + (q31_t)0x28d6870, (q31_t)0x800683e8, (q31_t)0x2872043, (q31_t)0x800663fd, (q31_t)0x280d813, (q31_t)0x80064460, (q31_t)0x27a8fe2, (q31_t)0x80062513, + (q31_t)0x27447b0, (q31_t)0x80060614, (q31_t)0x26dff7c, (q31_t)0x8005e764, (q31_t)0x267b747, (q31_t)0x8005c904, (q31_t)0x2616f10, (q31_t)0x8005aaf2, + (q31_t)0x25b26d7, (q31_t)0x80058d2f, (q31_t)0x254de9e, (q31_t)0x80056fbb, (q31_t)0x24e9662, (q31_t)0x80055296, (q31_t)0x2484e26, (q31_t)0x800535c0, + (q31_t)0x24205e8, (q31_t)0x80051939, (q31_t)0x23bbda8, (q31_t)0x8004fd00, (q31_t)0x2357567, (q31_t)0x8004e117, (q31_t)0x22f2d25, (q31_t)0x8004c57d, + (q31_t)0x228e4e2, (q31_t)0x8004aa32, (q31_t)0x2229c9d, (q31_t)0x80048f35, (q31_t)0x21c5457, (q31_t)0x80047488, (q31_t)0x2160c0f, (q31_t)0x80045a29, + (q31_t)0x20fc3c6, (q31_t)0x8004401a, (q31_t)0x2097b7c, (q31_t)0x80042659, (q31_t)0x2033331, (q31_t)0x80040ce7, (q31_t)0x1fceae4, (q31_t)0x8003f3c5, + (q31_t)0x1f6a297, (q31_t)0x8003daf1, (q31_t)0x1f05a48, (q31_t)0x8003c26c, (q31_t)0x1ea11f7, (q31_t)0x8003aa36, (q31_t)0x1e3c9a6, (q31_t)0x8003924f, + (q31_t)0x1dd8154, (q31_t)0x80037ab7, (q31_t)0x1d73900, (q31_t)0x8003636e, (q31_t)0x1d0f0ab, (q31_t)0x80034c74, (q31_t)0x1caa855, (q31_t)0x800335c9, + (q31_t)0x1c45ffe, (q31_t)0x80031f6d, (q31_t)0x1be17a6, (q31_t)0x80030960, (q31_t)0x1b7cf4d, (q31_t)0x8002f3a1, (q31_t)0x1b186f3, (q31_t)0x8002de32, + (q31_t)0x1ab3e97, (q31_t)0x8002c912, (q31_t)0x1a4f63b, (q31_t)0x8002b440, (q31_t)0x19eaddd, (q31_t)0x80029fbe, (q31_t)0x198657f, (q31_t)0x80028b8a, + (q31_t)0x1921d20, (q31_t)0x800277a6, (q31_t)0x18bd4bf, (q31_t)0x80026410, (q31_t)0x1858c5e, (q31_t)0x800250c9, (q31_t)0x17f43fc, (q31_t)0x80023dd2, + (q31_t)0x178fb99, (q31_t)0x80022b29, (q31_t)0x172b335, (q31_t)0x800218cf, (q31_t)0x16c6ad0, (q31_t)0x800206c4, (q31_t)0x166226a, (q31_t)0x8001f508, + (q31_t)0x15fda03, (q31_t)0x8001e39b, (q31_t)0x159919c, (q31_t)0x8001d27d, (q31_t)0x1534934, (q31_t)0x8001c1ae, (q31_t)0x14d00ca, (q31_t)0x8001b12e, + (q31_t)0x146b860, (q31_t)0x8001a0fd, (q31_t)0x1406ff6, (q31_t)0x8001911b, (q31_t)0x13a278a, (q31_t)0x80018187, (q31_t)0x133df1e, (q31_t)0x80017243, + (q31_t)0x12d96b1, (q31_t)0x8001634e, (q31_t)0x1274e43, (q31_t)0x800154a7, (q31_t)0x12105d5, (q31_t)0x80014650, (q31_t)0x11abd66, (q31_t)0x80013847, + (q31_t)0x11474f6, (q31_t)0x80012a8e, (q31_t)0x10e2c85, (q31_t)0x80011d23, (q31_t)0x107e414, (q31_t)0x80011008, (q31_t)0x1019ba2, (q31_t)0x8001033b, + (q31_t)0x0fb5330, (q31_t)0x8000f6bd, (q31_t)0x0f50abd, (q31_t)0x8000ea8e, (q31_t)0x0eec249, (q31_t)0x8000deaf, (q31_t)0x0e879d5, (q31_t)0x8000d31e, + (q31_t)0x0e23160, (q31_t)0x8000c7dc, (q31_t)0x0dbe8eb, (q31_t)0x8000bce9, (q31_t)0x0d5a075, (q31_t)0x8000b245, (q31_t)0x0cf57ff, (q31_t)0x8000a7f0, + (q31_t)0x0c90f88, (q31_t)0x80009dea, (q31_t)0x0c2c711, (q31_t)0x80009433, (q31_t)0x0bc7e99, (q31_t)0x80008aca, (q31_t)0x0b63621, (q31_t)0x800081b1, + (q31_t)0x0afeda8, (q31_t)0x800078e7, (q31_t)0x0a9a52f, (q31_t)0x8000706c, (q31_t)0x0a35cb5, (q31_t)0x8000683f, (q31_t)0x09d143b, (q31_t)0x80006062, + (q31_t)0x096cbc1, (q31_t)0x800058d4, (q31_t)0x0908346, (q31_t)0x80005194, (q31_t)0x08a3acb, (q31_t)0x80004aa4, (q31_t)0x083f250, (q31_t)0x80004402, + (q31_t)0x07da9d4, (q31_t)0x80003daf, (q31_t)0x0776159, (q31_t)0x800037ac, (q31_t)0x07118dc, (q31_t)0x800031f7, (q31_t)0x06ad060, (q31_t)0x80002c91, + (q31_t)0x06487e3, (q31_t)0x8000277a, (q31_t)0x05e3f66, (q31_t)0x800022b3, (q31_t)0x057f6e9, (q31_t)0x80001e3a, (q31_t)0x051ae6b, (q31_t)0x80001a10, + (q31_t)0x04b65ee, (q31_t)0x80001635, (q31_t)0x0451d70, (q31_t)0x800012a9, (q31_t)0x03ed4f2, (q31_t)0x80000f6c, (q31_t)0x0388c74, (q31_t)0x80000c7e, + (q31_t)0x03243f5, (q31_t)0x800009df, (q31_t)0x02bfb77, (q31_t)0x8000078e, (q31_t)0x025b2f8, (q31_t)0x8000058d, (q31_t)0x01f6a7a, (q31_t)0x800003db, + (q31_t)0x01921fb, (q31_t)0x80000278, (q31_t)0x012d97c, (q31_t)0x80000163, (q31_t)0x00c90fe, (q31_t)0x8000009e, (q31_t)0x006487f, (q31_t)0x80000027 +}; + const q31_t cos_factorsQ31_8192[8192] = { + (q31_t)0x7ffffff6, (q31_t)0x7fffffa7, (q31_t)0x7fffff09, (q31_t)0x7ffffe1c, (q31_t)0x7ffffce1, (q31_t)0x7ffffb56, (q31_t)0x7ffff97c, (q31_t)0x7ffff753, + (q31_t)0x7ffff4dc, (q31_t)0x7ffff215, (q31_t)0x7fffef00, (q31_t)0x7fffeb9b, (q31_t)0x7fffe7e8, (q31_t)0x7fffe3e5, (q31_t)0x7fffdf94, (q31_t)0x7fffdaf3, + (q31_t)0x7fffd604, (q31_t)0x7fffd0c6, (q31_t)0x7fffcb39, (q31_t)0x7fffc55c, (q31_t)0x7fffbf31, (q31_t)0x7fffb8b7, (q31_t)0x7fffb1ee, (q31_t)0x7fffaad6, + (q31_t)0x7fffa36f, (q31_t)0x7fff9bb9, (q31_t)0x7fff93b4, (q31_t)0x7fff8b61, (q31_t)0x7fff82be, (q31_t)0x7fff79cc, (q31_t)0x7fff708b, (q31_t)0x7fff66fc, + (q31_t)0x7fff5d1d, (q31_t)0x7fff52ef, (q31_t)0x7fff4873, (q31_t)0x7fff3da8, (q31_t)0x7fff328d, (q31_t)0x7fff2724, (q31_t)0x7fff1b6b, (q31_t)0x7fff0f64, + (q31_t)0x7fff030e, (q31_t)0x7ffef669, (q31_t)0x7ffee975, (q31_t)0x7ffedc31, (q31_t)0x7ffece9f, (q31_t)0x7ffec0be, (q31_t)0x7ffeb28e, (q31_t)0x7ffea40f, + (q31_t)0x7ffe9542, (q31_t)0x7ffe8625, (q31_t)0x7ffe76b9, (q31_t)0x7ffe66fe, (q31_t)0x7ffe56f5, (q31_t)0x7ffe469c, (q31_t)0x7ffe35f4, (q31_t)0x7ffe24fe, + (q31_t)0x7ffe13b8, (q31_t)0x7ffe0224, (q31_t)0x7ffdf040, (q31_t)0x7ffdde0e, (q31_t)0x7ffdcb8d, (q31_t)0x7ffdb8bc, (q31_t)0x7ffda59d, (q31_t)0x7ffd922f, + (q31_t)0x7ffd7e72, (q31_t)0x7ffd6a66, (q31_t)0x7ffd560b, (q31_t)0x7ffd4161, (q31_t)0x7ffd2c68, (q31_t)0x7ffd1720, (q31_t)0x7ffd0189, (q31_t)0x7ffceba4, + (q31_t)0x7ffcd56f, (q31_t)0x7ffcbeeb, (q31_t)0x7ffca819, (q31_t)0x7ffc90f7, (q31_t)0x7ffc7987, (q31_t)0x7ffc61c7, (q31_t)0x7ffc49b9, (q31_t)0x7ffc315b, + (q31_t)0x7ffc18af, (q31_t)0x7ffbffb4, (q31_t)0x7ffbe66a, (q31_t)0x7ffbccd0, (q31_t)0x7ffbb2e8, (q31_t)0x7ffb98b1, (q31_t)0x7ffb7e2b, (q31_t)0x7ffb6356, + (q31_t)0x7ffb4833, (q31_t)0x7ffb2cc0, (q31_t)0x7ffb10fe, (q31_t)0x7ffaf4ed, (q31_t)0x7ffad88e, (q31_t)0x7ffabbdf, (q31_t)0x7ffa9ee2, (q31_t)0x7ffa8195, + (q31_t)0x7ffa63fa, (q31_t)0x7ffa460f, (q31_t)0x7ffa27d6, (q31_t)0x7ffa094e, (q31_t)0x7ff9ea76, (q31_t)0x7ff9cb50, (q31_t)0x7ff9abdb, (q31_t)0x7ff98c17, + (q31_t)0x7ff96c04, (q31_t)0x7ff94ba2, (q31_t)0x7ff92af1, (q31_t)0x7ff909f2, (q31_t)0x7ff8e8a3, (q31_t)0x7ff8c705, (q31_t)0x7ff8a519, (q31_t)0x7ff882dd, + (q31_t)0x7ff86053, (q31_t)0x7ff83d79, (q31_t)0x7ff81a51, (q31_t)0x7ff7f6da, (q31_t)0x7ff7d313, (q31_t)0x7ff7aefe, (q31_t)0x7ff78a9a, (q31_t)0x7ff765e7, + (q31_t)0x7ff740e5, (q31_t)0x7ff71b94, (q31_t)0x7ff6f5f4, (q31_t)0x7ff6d005, (q31_t)0x7ff6a9c8, (q31_t)0x7ff6833b, (q31_t)0x7ff65c5f, (q31_t)0x7ff63535, + (q31_t)0x7ff60dbb, (q31_t)0x7ff5e5f3, (q31_t)0x7ff5bddc, (q31_t)0x7ff59576, (q31_t)0x7ff56cc0, (q31_t)0x7ff543bc, (q31_t)0x7ff51a69, (q31_t)0x7ff4f0c7, + (q31_t)0x7ff4c6d6, (q31_t)0x7ff49c96, (q31_t)0x7ff47208, (q31_t)0x7ff4472a, (q31_t)0x7ff41bfd, (q31_t)0x7ff3f082, (q31_t)0x7ff3c4b7, (q31_t)0x7ff3989e, + (q31_t)0x7ff36c36, (q31_t)0x7ff33f7e, (q31_t)0x7ff31278, (q31_t)0x7ff2e523, (q31_t)0x7ff2b77f, (q31_t)0x7ff2898c, (q31_t)0x7ff25b4a, (q31_t)0x7ff22cb9, + (q31_t)0x7ff1fdd9, (q31_t)0x7ff1ceab, (q31_t)0x7ff19f2d, (q31_t)0x7ff16f61, (q31_t)0x7ff13f45, (q31_t)0x7ff10edb, (q31_t)0x7ff0de22, (q31_t)0x7ff0ad19, + (q31_t)0x7ff07bc2, (q31_t)0x7ff04a1c, (q31_t)0x7ff01827, (q31_t)0x7fefe5e4, (q31_t)0x7fefb351, (q31_t)0x7fef806f, (q31_t)0x7fef4d3e, (q31_t)0x7fef19bf, + (q31_t)0x7feee5f0, (q31_t)0x7feeb1d3, (q31_t)0x7fee7d67, (q31_t)0x7fee48ac, (q31_t)0x7fee13a1, (q31_t)0x7fedde48, (q31_t)0x7feda8a0, (q31_t)0x7fed72aa, + (q31_t)0x7fed3c64, (q31_t)0x7fed05cf, (q31_t)0x7fecceec, (q31_t)0x7fec97b9, (q31_t)0x7fec6038, (q31_t)0x7fec2867, (q31_t)0x7febf048, (q31_t)0x7febb7da, + (q31_t)0x7feb7f1d, (q31_t)0x7feb4611, (q31_t)0x7feb0cb6, (q31_t)0x7fead30c, (q31_t)0x7fea9914, (q31_t)0x7fea5ecc, (q31_t)0x7fea2436, (q31_t)0x7fe9e950, + (q31_t)0x7fe9ae1c, (q31_t)0x7fe97299, (q31_t)0x7fe936c7, (q31_t)0x7fe8faa6, (q31_t)0x7fe8be36, (q31_t)0x7fe88177, (q31_t)0x7fe84469, (q31_t)0x7fe8070d, + (q31_t)0x7fe7c961, (q31_t)0x7fe78b67, (q31_t)0x7fe74d1e, (q31_t)0x7fe70e85, (q31_t)0x7fe6cf9e, (q31_t)0x7fe69068, (q31_t)0x7fe650e3, (q31_t)0x7fe61110, + (q31_t)0x7fe5d0ed, (q31_t)0x7fe5907b, (q31_t)0x7fe54fbb, (q31_t)0x7fe50eac, (q31_t)0x7fe4cd4d, (q31_t)0x7fe48ba0, (q31_t)0x7fe449a4, (q31_t)0x7fe40759, + (q31_t)0x7fe3c4bf, (q31_t)0x7fe381d7, (q31_t)0x7fe33e9f, (q31_t)0x7fe2fb19, (q31_t)0x7fe2b743, (q31_t)0x7fe2731f, (q31_t)0x7fe22eac, (q31_t)0x7fe1e9ea, + (q31_t)0x7fe1a4d9, (q31_t)0x7fe15f79, (q31_t)0x7fe119cb, (q31_t)0x7fe0d3cd, (q31_t)0x7fe08d81, (q31_t)0x7fe046e5, (q31_t)0x7fdffffb, (q31_t)0x7fdfb8c2, + (q31_t)0x7fdf713a, (q31_t)0x7fdf2963, (q31_t)0x7fdee13e, (q31_t)0x7fde98c9, (q31_t)0x7fde5006, (q31_t)0x7fde06f3, (q31_t)0x7fddbd92, (q31_t)0x7fdd73e2, + (q31_t)0x7fdd29e3, (q31_t)0x7fdcdf95, (q31_t)0x7fdc94f9, (q31_t)0x7fdc4a0d, (q31_t)0x7fdbfed3, (q31_t)0x7fdbb349, (q31_t)0x7fdb6771, (q31_t)0x7fdb1b4a, + (q31_t)0x7fdaced4, (q31_t)0x7fda820f, (q31_t)0x7fda34fc, (q31_t)0x7fd9e799, (q31_t)0x7fd999e8, (q31_t)0x7fd94be8, (q31_t)0x7fd8fd98, (q31_t)0x7fd8aefa, + (q31_t)0x7fd8600e, (q31_t)0x7fd810d2, (q31_t)0x7fd7c147, (q31_t)0x7fd7716e, (q31_t)0x7fd72146, (q31_t)0x7fd6d0cf, (q31_t)0x7fd68009, (q31_t)0x7fd62ef4, + (q31_t)0x7fd5dd90, (q31_t)0x7fd58bdd, (q31_t)0x7fd539dc, (q31_t)0x7fd4e78c, (q31_t)0x7fd494ed, (q31_t)0x7fd441ff, (q31_t)0x7fd3eec2, (q31_t)0x7fd39b36, + (q31_t)0x7fd3475c, (q31_t)0x7fd2f332, (q31_t)0x7fd29eba, (q31_t)0x7fd249f3, (q31_t)0x7fd1f4dd, (q31_t)0x7fd19f78, (q31_t)0x7fd149c5, (q31_t)0x7fd0f3c2, + (q31_t)0x7fd09d71, (q31_t)0x7fd046d1, (q31_t)0x7fcfefe2, (q31_t)0x7fcf98a4, (q31_t)0x7fcf4117, (q31_t)0x7fcee93c, (q31_t)0x7fce9112, (q31_t)0x7fce3898, + (q31_t)0x7fcddfd0, (q31_t)0x7fcd86b9, (q31_t)0x7fcd2d54, (q31_t)0x7fccd39f, (q31_t)0x7fcc799c, (q31_t)0x7fcc1f4a, (q31_t)0x7fcbc4a9, (q31_t)0x7fcb69b9, + (q31_t)0x7fcb0e7a, (q31_t)0x7fcab2ed, (q31_t)0x7fca5710, (q31_t)0x7fc9fae5, (q31_t)0x7fc99e6b, (q31_t)0x7fc941a2, (q31_t)0x7fc8e48b, (q31_t)0x7fc88724, + (q31_t)0x7fc8296f, (q31_t)0x7fc7cb6b, (q31_t)0x7fc76d18, (q31_t)0x7fc70e76, (q31_t)0x7fc6af86, (q31_t)0x7fc65046, (q31_t)0x7fc5f0b8, (q31_t)0x7fc590db, + (q31_t)0x7fc530af, (q31_t)0x7fc4d035, (q31_t)0x7fc46f6b, (q31_t)0x7fc40e53, (q31_t)0x7fc3acec, (q31_t)0x7fc34b36, (q31_t)0x7fc2e931, (q31_t)0x7fc286de, + (q31_t)0x7fc2243b, (q31_t)0x7fc1c14a, (q31_t)0x7fc15e0a, (q31_t)0x7fc0fa7b, (q31_t)0x7fc0969e, (q31_t)0x7fc03271, (q31_t)0x7fbfcdf6, (q31_t)0x7fbf692c, + (q31_t)0x7fbf0414, (q31_t)0x7fbe9eac, (q31_t)0x7fbe38f6, (q31_t)0x7fbdd2f0, (q31_t)0x7fbd6c9c, (q31_t)0x7fbd05fa, (q31_t)0x7fbc9f08, (q31_t)0x7fbc37c8, + (q31_t)0x7fbbd039, (q31_t)0x7fbb685b, (q31_t)0x7fbb002e, (q31_t)0x7fba97b2, (q31_t)0x7fba2ee8, (q31_t)0x7fb9c5cf, (q31_t)0x7fb95c67, (q31_t)0x7fb8f2b0, + (q31_t)0x7fb888ab, (q31_t)0x7fb81e57, (q31_t)0x7fb7b3b4, (q31_t)0x7fb748c2, (q31_t)0x7fb6dd81, (q31_t)0x7fb671f2, (q31_t)0x7fb60614, (q31_t)0x7fb599e7, + (q31_t)0x7fb52d6b, (q31_t)0x7fb4c0a1, (q31_t)0x7fb45387, (q31_t)0x7fb3e61f, (q31_t)0x7fb37869, (q31_t)0x7fb30a63, (q31_t)0x7fb29c0f, (q31_t)0x7fb22d6c, + (q31_t)0x7fb1be7a, (q31_t)0x7fb14f39, (q31_t)0x7fb0dfaa, (q31_t)0x7fb06fcb, (q31_t)0x7fafff9e, (q31_t)0x7faf8f23, (q31_t)0x7faf1e58, (q31_t)0x7faead3f, + (q31_t)0x7fae3bd7, (q31_t)0x7fadca20, (q31_t)0x7fad581b, (q31_t)0x7face5c6, (q31_t)0x7fac7323, (q31_t)0x7fac0031, (q31_t)0x7fab8cf1, (q31_t)0x7fab1962, + (q31_t)0x7faaa584, (q31_t)0x7faa3157, (q31_t)0x7fa9bcdb, (q31_t)0x7fa94811, (q31_t)0x7fa8d2f8, (q31_t)0x7fa85d90, (q31_t)0x7fa7e7d9, (q31_t)0x7fa771d4, + (q31_t)0x7fa6fb80, (q31_t)0x7fa684dd, (q31_t)0x7fa60dec, (q31_t)0x7fa596ac, (q31_t)0x7fa51f1d, (q31_t)0x7fa4a73f, (q31_t)0x7fa42f12, (q31_t)0x7fa3b697, + (q31_t)0x7fa33dcd, (q31_t)0x7fa2c4b5, (q31_t)0x7fa24b4d, (q31_t)0x7fa1d197, (q31_t)0x7fa15792, (q31_t)0x7fa0dd3f, (q31_t)0x7fa0629c, (q31_t)0x7f9fe7ab, + (q31_t)0x7f9f6c6b, (q31_t)0x7f9ef0dd, (q31_t)0x7f9e7500, (q31_t)0x7f9df8d4, (q31_t)0x7f9d7c59, (q31_t)0x7f9cff90, (q31_t)0x7f9c8278, (q31_t)0x7f9c0511, + (q31_t)0x7f9b875b, (q31_t)0x7f9b0957, (q31_t)0x7f9a8b04, (q31_t)0x7f9a0c62, (q31_t)0x7f998d72, (q31_t)0x7f990e33, (q31_t)0x7f988ea5, (q31_t)0x7f980ec8, + (q31_t)0x7f978e9d, (q31_t)0x7f970e23, (q31_t)0x7f968d5b, (q31_t)0x7f960c43, (q31_t)0x7f958add, (q31_t)0x7f950929, (q31_t)0x7f948725, (q31_t)0x7f9404d3, + (q31_t)0x7f938232, (q31_t)0x7f92ff43, (q31_t)0x7f927c04, (q31_t)0x7f91f878, (q31_t)0x7f91749c, (q31_t)0x7f90f072, (q31_t)0x7f906bf9, (q31_t)0x7f8fe731, + (q31_t)0x7f8f621b, (q31_t)0x7f8edcb6, (q31_t)0x7f8e5702, (q31_t)0x7f8dd0ff, (q31_t)0x7f8d4aae, (q31_t)0x7f8cc40f, (q31_t)0x7f8c3d20, (q31_t)0x7f8bb5e3, + (q31_t)0x7f8b2e57, (q31_t)0x7f8aa67d, (q31_t)0x7f8a1e54, (q31_t)0x7f8995dc, (q31_t)0x7f890d15, (q31_t)0x7f888400, (q31_t)0x7f87fa9c, (q31_t)0x7f8770ea, + (q31_t)0x7f86e6e9, (q31_t)0x7f865c99, (q31_t)0x7f85d1fa, (q31_t)0x7f85470d, (q31_t)0x7f84bbd1, (q31_t)0x7f843047, (q31_t)0x7f83a46e, (q31_t)0x7f831846, + (q31_t)0x7f828bcf, (q31_t)0x7f81ff0a, (q31_t)0x7f8171f6, (q31_t)0x7f80e494, (q31_t)0x7f8056e3, (q31_t)0x7f7fc8e3, (q31_t)0x7f7f3a95, (q31_t)0x7f7eabf8, + (q31_t)0x7f7e1d0c, (q31_t)0x7f7d8dd2, (q31_t)0x7f7cfe49, (q31_t)0x7f7c6e71, (q31_t)0x7f7bde4b, (q31_t)0x7f7b4dd6, (q31_t)0x7f7abd13, (q31_t)0x7f7a2c01, + (q31_t)0x7f799aa0, (q31_t)0x7f7908f0, (q31_t)0x7f7876f2, (q31_t)0x7f77e4a6, (q31_t)0x7f77520a, (q31_t)0x7f76bf21, (q31_t)0x7f762be8, (q31_t)0x7f759861, + (q31_t)0x7f75048b, (q31_t)0x7f747067, (q31_t)0x7f73dbf4, (q31_t)0x7f734732, (q31_t)0x7f72b222, (q31_t)0x7f721cc3, (q31_t)0x7f718715, (q31_t)0x7f70f119, + (q31_t)0x7f705ace, (q31_t)0x7f6fc435, (q31_t)0x7f6f2d4d, (q31_t)0x7f6e9617, (q31_t)0x7f6dfe91, (q31_t)0x7f6d66be, (q31_t)0x7f6cce9b, (q31_t)0x7f6c362a, + (q31_t)0x7f6b9d6b, (q31_t)0x7f6b045d, (q31_t)0x7f6a6b00, (q31_t)0x7f69d154, (q31_t)0x7f69375a, (q31_t)0x7f689d12, (q31_t)0x7f68027b, (q31_t)0x7f676795, + (q31_t)0x7f66cc61, (q31_t)0x7f6630de, (q31_t)0x7f65950c, (q31_t)0x7f64f8ec, (q31_t)0x7f645c7d, (q31_t)0x7f63bfc0, (q31_t)0x7f6322b4, (q31_t)0x7f62855a, + (q31_t)0x7f61e7b1, (q31_t)0x7f6149b9, (q31_t)0x7f60ab73, (q31_t)0x7f600cdf, (q31_t)0x7f5f6dfb, (q31_t)0x7f5ecec9, (q31_t)0x7f5e2f49, (q31_t)0x7f5d8f7a, + (q31_t)0x7f5cef5c, (q31_t)0x7f5c4ef0, (q31_t)0x7f5bae36, (q31_t)0x7f5b0d2c, (q31_t)0x7f5a6bd5, (q31_t)0x7f59ca2e, (q31_t)0x7f592839, (q31_t)0x7f5885f6, + (q31_t)0x7f57e364, (q31_t)0x7f574083, (q31_t)0x7f569d54, (q31_t)0x7f55f9d6, (q31_t)0x7f55560a, (q31_t)0x7f54b1ef, (q31_t)0x7f540d86, (q31_t)0x7f5368ce, + (q31_t)0x7f52c3c8, (q31_t)0x7f521e73, (q31_t)0x7f5178cf, (q31_t)0x7f50d2dd, (q31_t)0x7f502c9d, (q31_t)0x7f4f860e, (q31_t)0x7f4edf30, (q31_t)0x7f4e3804, + (q31_t)0x7f4d9089, (q31_t)0x7f4ce8c0, (q31_t)0x7f4c40a8, (q31_t)0x7f4b9842, (q31_t)0x7f4aef8d, (q31_t)0x7f4a468a, (q31_t)0x7f499d38, (q31_t)0x7f48f398, + (q31_t)0x7f4849a9, (q31_t)0x7f479f6c, (q31_t)0x7f46f4e0, (q31_t)0x7f464a06, (q31_t)0x7f459edd, (q31_t)0x7f44f365, (q31_t)0x7f44479f, (q31_t)0x7f439b8b, + (q31_t)0x7f42ef28, (q31_t)0x7f424277, (q31_t)0x7f419577, (q31_t)0x7f40e828, (q31_t)0x7f403a8b, (q31_t)0x7f3f8ca0, (q31_t)0x7f3ede66, (q31_t)0x7f3e2fde, + (q31_t)0x7f3d8107, (q31_t)0x7f3cd1e2, (q31_t)0x7f3c226e, (q31_t)0x7f3b72ab, (q31_t)0x7f3ac29b, (q31_t)0x7f3a123b, (q31_t)0x7f39618e, (q31_t)0x7f38b091, + (q31_t)0x7f37ff47, (q31_t)0x7f374dad, (q31_t)0x7f369bc6, (q31_t)0x7f35e990, (q31_t)0x7f35370b, (q31_t)0x7f348438, (q31_t)0x7f33d116, (q31_t)0x7f331da6, + (q31_t)0x7f3269e8, (q31_t)0x7f31b5db, (q31_t)0x7f31017f, (q31_t)0x7f304cd6, (q31_t)0x7f2f97dd, (q31_t)0x7f2ee296, (q31_t)0x7f2e2d01, (q31_t)0x7f2d771e, + (q31_t)0x7f2cc0eb, (q31_t)0x7f2c0a6b, (q31_t)0x7f2b539c, (q31_t)0x7f2a9c7e, (q31_t)0x7f29e512, (q31_t)0x7f292d58, (q31_t)0x7f28754f, (q31_t)0x7f27bcf8, + (q31_t)0x7f270452, (q31_t)0x7f264b5e, (q31_t)0x7f25921c, (q31_t)0x7f24d88b, (q31_t)0x7f241eab, (q31_t)0x7f23647e, (q31_t)0x7f22aa01, (q31_t)0x7f21ef37, + (q31_t)0x7f21341e, (q31_t)0x7f2078b6, (q31_t)0x7f1fbd00, (q31_t)0x7f1f00fc, (q31_t)0x7f1e44a9, (q31_t)0x7f1d8808, (q31_t)0x7f1ccb18, (q31_t)0x7f1c0dda, + (q31_t)0x7f1b504e, (q31_t)0x7f1a9273, (q31_t)0x7f19d44a, (q31_t)0x7f1915d2, (q31_t)0x7f18570c, (q31_t)0x7f1797f8, (q31_t)0x7f16d895, (q31_t)0x7f1618e4, + (q31_t)0x7f1558e4, (q31_t)0x7f149896, (q31_t)0x7f13d7fa, (q31_t)0x7f13170f, (q31_t)0x7f1255d6, (q31_t)0x7f11944f, (q31_t)0x7f10d279, (q31_t)0x7f101054, + (q31_t)0x7f0f4de2, (q31_t)0x7f0e8b21, (q31_t)0x7f0dc811, (q31_t)0x7f0d04b3, (q31_t)0x7f0c4107, (q31_t)0x7f0b7d0d, (q31_t)0x7f0ab8c4, (q31_t)0x7f09f42d, + (q31_t)0x7f092f47, (q31_t)0x7f086a13, (q31_t)0x7f07a491, (q31_t)0x7f06dec0, (q31_t)0x7f0618a1, (q31_t)0x7f055233, (q31_t)0x7f048b78, (q31_t)0x7f03c46d, + (q31_t)0x7f02fd15, (q31_t)0x7f02356e, (q31_t)0x7f016d79, (q31_t)0x7f00a535, (q31_t)0x7effdca4, (q31_t)0x7eff13c3, (q31_t)0x7efe4a95, (q31_t)0x7efd8118, + (q31_t)0x7efcb74d, (q31_t)0x7efbed33, (q31_t)0x7efb22cb, (q31_t)0x7efa5815, (q31_t)0x7ef98d11, (q31_t)0x7ef8c1be, (q31_t)0x7ef7f61d, (q31_t)0x7ef72a2d, + (q31_t)0x7ef65def, (q31_t)0x7ef59163, (q31_t)0x7ef4c489, (q31_t)0x7ef3f760, (q31_t)0x7ef329e9, (q31_t)0x7ef25c24, (q31_t)0x7ef18e10, (q31_t)0x7ef0bfae, + (q31_t)0x7eeff0fe, (q31_t)0x7eef21ff, (q31_t)0x7eee52b2, (q31_t)0x7eed8317, (q31_t)0x7eecb32d, (q31_t)0x7eebe2f6, (q31_t)0x7eeb1270, (q31_t)0x7eea419b, + (q31_t)0x7ee97079, (q31_t)0x7ee89f08, (q31_t)0x7ee7cd49, (q31_t)0x7ee6fb3b, (q31_t)0x7ee628df, (q31_t)0x7ee55635, (q31_t)0x7ee4833d, (q31_t)0x7ee3aff6, + (q31_t)0x7ee2dc61, (q31_t)0x7ee2087e, (q31_t)0x7ee1344d, (q31_t)0x7ee05fcd, (q31_t)0x7edf8aff, (q31_t)0x7edeb5e3, (q31_t)0x7edde079, (q31_t)0x7edd0ac0, + (q31_t)0x7edc34b9, (q31_t)0x7edb5e64, (q31_t)0x7eda87c0, (q31_t)0x7ed9b0ce, (q31_t)0x7ed8d98e, (q31_t)0x7ed80200, (q31_t)0x7ed72a24, (q31_t)0x7ed651f9, + (q31_t)0x7ed57980, (q31_t)0x7ed4a0b9, (q31_t)0x7ed3c7a3, (q31_t)0x7ed2ee40, (q31_t)0x7ed2148e, (q31_t)0x7ed13a8e, (q31_t)0x7ed0603f, (q31_t)0x7ecf85a3, + (q31_t)0x7eceaab8, (q31_t)0x7ecdcf7f, (q31_t)0x7eccf3f8, (q31_t)0x7ecc1822, (q31_t)0x7ecb3bff, (q31_t)0x7eca5f8d, (q31_t)0x7ec982cd, (q31_t)0x7ec8a5bf, + (q31_t)0x7ec7c862, (q31_t)0x7ec6eab7, (q31_t)0x7ec60cbe, (q31_t)0x7ec52e77, (q31_t)0x7ec44fe2, (q31_t)0x7ec370fe, (q31_t)0x7ec291cd, (q31_t)0x7ec1b24d, + (q31_t)0x7ec0d27f, (q31_t)0x7ebff263, (q31_t)0x7ebf11f8, (q31_t)0x7ebe313f, (q31_t)0x7ebd5039, (q31_t)0x7ebc6ee4, (q31_t)0x7ebb8d40, (q31_t)0x7ebaab4f, + (q31_t)0x7eb9c910, (q31_t)0x7eb8e682, (q31_t)0x7eb803a6, (q31_t)0x7eb7207c, (q31_t)0x7eb63d04, (q31_t)0x7eb5593d, (q31_t)0x7eb47529, (q31_t)0x7eb390c6, + (q31_t)0x7eb2ac15, (q31_t)0x7eb1c716, (q31_t)0x7eb0e1c9, (q31_t)0x7eaffc2e, (q31_t)0x7eaf1645, (q31_t)0x7eae300d, (q31_t)0x7ead4987, (q31_t)0x7eac62b3, + (q31_t)0x7eab7b91, (q31_t)0x7eaa9421, (q31_t)0x7ea9ac63, (q31_t)0x7ea8c457, (q31_t)0x7ea7dbfc, (q31_t)0x7ea6f353, (q31_t)0x7ea60a5d, (q31_t)0x7ea52118, + (q31_t)0x7ea43785, (q31_t)0x7ea34da4, (q31_t)0x7ea26374, (q31_t)0x7ea178f7, (q31_t)0x7ea08e2b, (q31_t)0x7e9fa312, (q31_t)0x7e9eb7aa, (q31_t)0x7e9dcbf4, + (q31_t)0x7e9cdff0, (q31_t)0x7e9bf39e, (q31_t)0x7e9b06fe, (q31_t)0x7e9a1a10, (q31_t)0x7e992cd4, (q31_t)0x7e983f49, (q31_t)0x7e975171, (q31_t)0x7e96634a, + (q31_t)0x7e9574d6, (q31_t)0x7e948613, (q31_t)0x7e939702, (q31_t)0x7e92a7a3, (q31_t)0x7e91b7f6, (q31_t)0x7e90c7fb, (q31_t)0x7e8fd7b2, (q31_t)0x7e8ee71b, + (q31_t)0x7e8df636, (q31_t)0x7e8d0502, (q31_t)0x7e8c1381, (q31_t)0x7e8b21b1, (q31_t)0x7e8a2f94, (q31_t)0x7e893d28, (q31_t)0x7e884a6f, (q31_t)0x7e875767, + (q31_t)0x7e866411, (q31_t)0x7e85706d, (q31_t)0x7e847c7c, (q31_t)0x7e83883c, (q31_t)0x7e8293ae, (q31_t)0x7e819ed2, (q31_t)0x7e80a9a8, (q31_t)0x7e7fb430, + (q31_t)0x7e7ebe6a, (q31_t)0x7e7dc856, (q31_t)0x7e7cd1f4, (q31_t)0x7e7bdb44, (q31_t)0x7e7ae446, (q31_t)0x7e79ecf9, (q31_t)0x7e78f55f, (q31_t)0x7e77fd77, + (q31_t)0x7e770541, (q31_t)0x7e760cbd, (q31_t)0x7e7513ea, (q31_t)0x7e741aca, (q31_t)0x7e73215c, (q31_t)0x7e7227a0, (q31_t)0x7e712d96, (q31_t)0x7e70333d, + (q31_t)0x7e6f3897, (q31_t)0x7e6e3da3, (q31_t)0x7e6d4261, (q31_t)0x7e6c46d1, (q31_t)0x7e6b4af2, (q31_t)0x7e6a4ec6, (q31_t)0x7e69524c, (q31_t)0x7e685584, + (q31_t)0x7e67586e, (q31_t)0x7e665b0a, (q31_t)0x7e655d58, (q31_t)0x7e645f58, (q31_t)0x7e63610a, (q31_t)0x7e62626e, (q31_t)0x7e616384, (q31_t)0x7e60644c, + (q31_t)0x7e5f64c7, (q31_t)0x7e5e64f3, (q31_t)0x7e5d64d1, (q31_t)0x7e5c6461, (q31_t)0x7e5b63a4, (q31_t)0x7e5a6298, (q31_t)0x7e59613f, (q31_t)0x7e585f97, + (q31_t)0x7e575da2, (q31_t)0x7e565b5f, (q31_t)0x7e5558ce, (q31_t)0x7e5455ef, (q31_t)0x7e5352c1, (q31_t)0x7e524f46, (q31_t)0x7e514b7e, (q31_t)0x7e504767, + (q31_t)0x7e4f4302, (q31_t)0x7e4e3e4f, (q31_t)0x7e4d394f, (q31_t)0x7e4c3400, (q31_t)0x7e4b2e64, (q31_t)0x7e4a287a, (q31_t)0x7e492241, (q31_t)0x7e481bbb, + (q31_t)0x7e4714e7, (q31_t)0x7e460dc5, (q31_t)0x7e450656, (q31_t)0x7e43fe98, (q31_t)0x7e42f68c, (q31_t)0x7e41ee33, (q31_t)0x7e40e58c, (q31_t)0x7e3fdc97, + (q31_t)0x7e3ed353, (q31_t)0x7e3dc9c3, (q31_t)0x7e3cbfe4, (q31_t)0x7e3bb5b7, (q31_t)0x7e3aab3c, (q31_t)0x7e39a074, (q31_t)0x7e38955e, (q31_t)0x7e3789fa, + (q31_t)0x7e367e48, (q31_t)0x7e357248, (q31_t)0x7e3465fa, (q31_t)0x7e33595e, (q31_t)0x7e324c75, (q31_t)0x7e313f3e, (q31_t)0x7e3031b9, (q31_t)0x7e2f23e6, + (q31_t)0x7e2e15c5, (q31_t)0x7e2d0756, (q31_t)0x7e2bf89a, (q31_t)0x7e2ae990, (q31_t)0x7e29da38, (q31_t)0x7e28ca92, (q31_t)0x7e27ba9e, (q31_t)0x7e26aa5d, + (q31_t)0x7e2599cd, (q31_t)0x7e2488f0, (q31_t)0x7e2377c5, (q31_t)0x7e22664c, (q31_t)0x7e215486, (q31_t)0x7e204271, (q31_t)0x7e1f300f, (q31_t)0x7e1e1d5f, + (q31_t)0x7e1d0a61, (q31_t)0x7e1bf716, (q31_t)0x7e1ae37c, (q31_t)0x7e19cf95, (q31_t)0x7e18bb60, (q31_t)0x7e17a6dd, (q31_t)0x7e16920d, (q31_t)0x7e157cee, + (q31_t)0x7e146782, (q31_t)0x7e1351c9, (q31_t)0x7e123bc1, (q31_t)0x7e11256c, (q31_t)0x7e100ec8, (q31_t)0x7e0ef7d7, (q31_t)0x7e0de099, (q31_t)0x7e0cc90c, + (q31_t)0x7e0bb132, (q31_t)0x7e0a990a, (q31_t)0x7e098095, (q31_t)0x7e0867d1, (q31_t)0x7e074ec0, (q31_t)0x7e063561, (q31_t)0x7e051bb4, (q31_t)0x7e0401ba, + (q31_t)0x7e02e772, (q31_t)0x7e01ccdc, (q31_t)0x7e00b1f9, (q31_t)0x7dff96c7, (q31_t)0x7dfe7b48, (q31_t)0x7dfd5f7b, (q31_t)0x7dfc4361, (q31_t)0x7dfb26f9, + (q31_t)0x7dfa0a43, (q31_t)0x7df8ed3f, (q31_t)0x7df7cfee, (q31_t)0x7df6b24f, (q31_t)0x7df59462, (q31_t)0x7df47628, (q31_t)0x7df357a0, (q31_t)0x7df238ca, + (q31_t)0x7df119a7, (q31_t)0x7deffa35, (q31_t)0x7deeda77, (q31_t)0x7dedba6a, (q31_t)0x7dec9a10, (q31_t)0x7deb7968, (q31_t)0x7dea5872, (q31_t)0x7de9372f, + (q31_t)0x7de8159e, (q31_t)0x7de6f3c0, (q31_t)0x7de5d193, (q31_t)0x7de4af1a, (q31_t)0x7de38c52, (q31_t)0x7de2693d, (q31_t)0x7de145da, (q31_t)0x7de02229, + (q31_t)0x7ddefe2b, (q31_t)0x7dddd9e0, (q31_t)0x7ddcb546, (q31_t)0x7ddb905f, (q31_t)0x7dda6b2a, (q31_t)0x7dd945a8, (q31_t)0x7dd81fd8, (q31_t)0x7dd6f9ba, + (q31_t)0x7dd5d34f, (q31_t)0x7dd4ac96, (q31_t)0x7dd38590, (q31_t)0x7dd25e3c, (q31_t)0x7dd1369a, (q31_t)0x7dd00eab, (q31_t)0x7dcee66e, (q31_t)0x7dcdbde3, + (q31_t)0x7dcc950b, (q31_t)0x7dcb6be6, (q31_t)0x7dca4272, (q31_t)0x7dc918b1, (q31_t)0x7dc7eea3, (q31_t)0x7dc6c447, (q31_t)0x7dc5999d, (q31_t)0x7dc46ea6, + (q31_t)0x7dc34361, (q31_t)0x7dc217cf, (q31_t)0x7dc0ebef, (q31_t)0x7dbfbfc1, (q31_t)0x7dbe9346, (q31_t)0x7dbd667d, (q31_t)0x7dbc3967, (q31_t)0x7dbb0c03, + (q31_t)0x7db9de52, (q31_t)0x7db8b053, (q31_t)0x7db78207, (q31_t)0x7db6536d, (q31_t)0x7db52485, (q31_t)0x7db3f550, (q31_t)0x7db2c5cd, (q31_t)0x7db195fd, + (q31_t)0x7db065df, (q31_t)0x7daf3574, (q31_t)0x7dae04bb, (q31_t)0x7dacd3b5, (q31_t)0x7daba261, (q31_t)0x7daa70c0, (q31_t)0x7da93ed1, (q31_t)0x7da80c95, + (q31_t)0x7da6da0b, (q31_t)0x7da5a733, (q31_t)0x7da4740e, (q31_t)0x7da3409c, (q31_t)0x7da20cdc, (q31_t)0x7da0d8cf, (q31_t)0x7d9fa474, (q31_t)0x7d9e6fcb, + (q31_t)0x7d9d3ad6, (q31_t)0x7d9c0592, (q31_t)0x7d9ad001, (q31_t)0x7d999a23, (q31_t)0x7d9863f7, (q31_t)0x7d972d7e, (q31_t)0x7d95f6b7, (q31_t)0x7d94bfa3, + (q31_t)0x7d938841, (q31_t)0x7d925092, (q31_t)0x7d911896, (q31_t)0x7d8fe04c, (q31_t)0x7d8ea7b4, (q31_t)0x7d8d6ecf, (q31_t)0x7d8c359d, (q31_t)0x7d8afc1d, + (q31_t)0x7d89c250, (q31_t)0x7d888835, (q31_t)0x7d874dcd, (q31_t)0x7d861317, (q31_t)0x7d84d814, (q31_t)0x7d839cc4, (q31_t)0x7d826126, (q31_t)0x7d81253a, + (q31_t)0x7d7fe902, (q31_t)0x7d7eac7c, (q31_t)0x7d7d6fa8, (q31_t)0x7d7c3287, (q31_t)0x7d7af519, (q31_t)0x7d79b75d, (q31_t)0x7d787954, (q31_t)0x7d773afd, + (q31_t)0x7d75fc59, (q31_t)0x7d74bd68, (q31_t)0x7d737e29, (q31_t)0x7d723e9d, (q31_t)0x7d70fec4, (q31_t)0x7d6fbe9d, (q31_t)0x7d6e7e29, (q31_t)0x7d6d3d67, + (q31_t)0x7d6bfc58, (q31_t)0x7d6abafc, (q31_t)0x7d697952, (q31_t)0x7d68375b, (q31_t)0x7d66f517, (q31_t)0x7d65b285, (q31_t)0x7d646fa6, (q31_t)0x7d632c79, + (q31_t)0x7d61e8ff, (q31_t)0x7d60a538, (q31_t)0x7d5f6124, (q31_t)0x7d5e1cc2, (q31_t)0x7d5cd813, (q31_t)0x7d5b9316, (q31_t)0x7d5a4dcc, (q31_t)0x7d590835, + (q31_t)0x7d57c251, (q31_t)0x7d567c1f, (q31_t)0x7d5535a0, (q31_t)0x7d53eed3, (q31_t)0x7d52a7ba, (q31_t)0x7d516053, (q31_t)0x7d50189e, (q31_t)0x7d4ed09d, + (q31_t)0x7d4d884e, (q31_t)0x7d4c3fb1, (q31_t)0x7d4af6c8, (q31_t)0x7d49ad91, (q31_t)0x7d48640d, (q31_t)0x7d471a3c, (q31_t)0x7d45d01d, (q31_t)0x7d4485b1, + (q31_t)0x7d433af8, (q31_t)0x7d41eff1, (q31_t)0x7d40a49e, (q31_t)0x7d3f58fd, (q31_t)0x7d3e0d0e, (q31_t)0x7d3cc0d3, (q31_t)0x7d3b744a, (q31_t)0x7d3a2774, + (q31_t)0x7d38da51, (q31_t)0x7d378ce0, (q31_t)0x7d363f23, (q31_t)0x7d34f118, (q31_t)0x7d33a2bf, (q31_t)0x7d32541a, (q31_t)0x7d310527, (q31_t)0x7d2fb5e7, + (q31_t)0x7d2e665a, (q31_t)0x7d2d1680, (q31_t)0x7d2bc659, (q31_t)0x7d2a75e4, (q31_t)0x7d292522, (q31_t)0x7d27d413, (q31_t)0x7d2682b6, (q31_t)0x7d25310d, + (q31_t)0x7d23df16, (q31_t)0x7d228cd2, (q31_t)0x7d213a41, (q31_t)0x7d1fe762, (q31_t)0x7d1e9437, (q31_t)0x7d1d40be, (q31_t)0x7d1becf8, (q31_t)0x7d1a98e5, + (q31_t)0x7d194485, (q31_t)0x7d17efd8, (q31_t)0x7d169add, (q31_t)0x7d154595, (q31_t)0x7d13f001, (q31_t)0x7d129a1f, (q31_t)0x7d1143ef, (q31_t)0x7d0fed73, + (q31_t)0x7d0e96aa, (q31_t)0x7d0d3f93, (q31_t)0x7d0be82f, (q31_t)0x7d0a907e, (q31_t)0x7d093880, (q31_t)0x7d07e035, (q31_t)0x7d06879d, (q31_t)0x7d052eb8, + (q31_t)0x7d03d585, (q31_t)0x7d027c05, (q31_t)0x7d012239, (q31_t)0x7cffc81f, (q31_t)0x7cfe6db8, (q31_t)0x7cfd1304, (q31_t)0x7cfbb803, (q31_t)0x7cfa5cb4, + (q31_t)0x7cf90119, (q31_t)0x7cf7a531, (q31_t)0x7cf648fb, (q31_t)0x7cf4ec79, (q31_t)0x7cf38fa9, (q31_t)0x7cf2328c, (q31_t)0x7cf0d522, (q31_t)0x7cef776b, + (q31_t)0x7cee1967, (q31_t)0x7cecbb16, (q31_t)0x7ceb5c78, (q31_t)0x7ce9fd8d, (q31_t)0x7ce89e55, (q31_t)0x7ce73ed0, (q31_t)0x7ce5defd, (q31_t)0x7ce47ede, + (q31_t)0x7ce31e72, (q31_t)0x7ce1bdb8, (q31_t)0x7ce05cb2, (q31_t)0x7cdefb5e, (q31_t)0x7cdd99be, (q31_t)0x7cdc37d0, (q31_t)0x7cdad596, (q31_t)0x7cd9730e, + (q31_t)0x7cd8103a, (q31_t)0x7cd6ad18, (q31_t)0x7cd549aa, (q31_t)0x7cd3e5ee, (q31_t)0x7cd281e5, (q31_t)0x7cd11d90, (q31_t)0x7ccfb8ed, (q31_t)0x7cce53fe, + (q31_t)0x7ccceec1, (q31_t)0x7ccb8937, (q31_t)0x7cca2361, (q31_t)0x7cc8bd3d, (q31_t)0x7cc756cd, (q31_t)0x7cc5f010, (q31_t)0x7cc48905, (q31_t)0x7cc321ae, + (q31_t)0x7cc1ba09, (q31_t)0x7cc05218, (q31_t)0x7cbee9da, (q31_t)0x7cbd814f, (q31_t)0x7cbc1877, (q31_t)0x7cbaaf51, (q31_t)0x7cb945df, (q31_t)0x7cb7dc20, + (q31_t)0x7cb67215, (q31_t)0x7cb507bc, (q31_t)0x7cb39d16, (q31_t)0x7cb23223, (q31_t)0x7cb0c6e4, (q31_t)0x7caf5b57, (q31_t)0x7cadef7e, (q31_t)0x7cac8358, + (q31_t)0x7cab16e4, (q31_t)0x7ca9aa24, (q31_t)0x7ca83d17, (q31_t)0x7ca6cfbd, (q31_t)0x7ca56216, (q31_t)0x7ca3f423, (q31_t)0x7ca285e2, (q31_t)0x7ca11755, + (q31_t)0x7c9fa87a, (q31_t)0x7c9e3953, (q31_t)0x7c9cc9df, (q31_t)0x7c9b5a1e, (q31_t)0x7c99ea10, (q31_t)0x7c9879b6, (q31_t)0x7c97090e, (q31_t)0x7c95981a, + (q31_t)0x7c9426d8, (q31_t)0x7c92b54a, (q31_t)0x7c91436f, (q31_t)0x7c8fd148, (q31_t)0x7c8e5ed3, (q31_t)0x7c8cec12, (q31_t)0x7c8b7903, (q31_t)0x7c8a05a8, + (q31_t)0x7c889200, (q31_t)0x7c871e0c, (q31_t)0x7c85a9ca, (q31_t)0x7c84353c, (q31_t)0x7c82c060, (q31_t)0x7c814b39, (q31_t)0x7c7fd5c4, (q31_t)0x7c7e6002, + (q31_t)0x7c7ce9f4, (q31_t)0x7c7b7399, (q31_t)0x7c79fcf1, (q31_t)0x7c7885fc, (q31_t)0x7c770eba, (q31_t)0x7c75972c, (q31_t)0x7c741f51, (q31_t)0x7c72a729, + (q31_t)0x7c712eb5, (q31_t)0x7c6fb5f3, (q31_t)0x7c6e3ce5, (q31_t)0x7c6cc38a, (q31_t)0x7c6b49e3, (q31_t)0x7c69cfee, (q31_t)0x7c6855ad, (q31_t)0x7c66db1f, + (q31_t)0x7c656045, (q31_t)0x7c63e51e, (q31_t)0x7c6269aa, (q31_t)0x7c60ede9, (q31_t)0x7c5f71db, (q31_t)0x7c5df581, (q31_t)0x7c5c78da, (q31_t)0x7c5afbe6, + (q31_t)0x7c597ea6, (q31_t)0x7c580119, (q31_t)0x7c56833f, (q31_t)0x7c550519, (q31_t)0x7c5386a6, (q31_t)0x7c5207e6, (q31_t)0x7c5088d9, (q31_t)0x7c4f0980, + (q31_t)0x7c4d89da, (q31_t)0x7c4c09e8, (q31_t)0x7c4a89a8, (q31_t)0x7c49091c, (q31_t)0x7c478844, (q31_t)0x7c46071f, (q31_t)0x7c4485ad, (q31_t)0x7c4303ee, + (q31_t)0x7c4181e3, (q31_t)0x7c3fff8b, (q31_t)0x7c3e7ce7, (q31_t)0x7c3cf9f5, (q31_t)0x7c3b76b8, (q31_t)0x7c39f32d, (q31_t)0x7c386f56, (q31_t)0x7c36eb33, + (q31_t)0x7c3566c2, (q31_t)0x7c33e205, (q31_t)0x7c325cfc, (q31_t)0x7c30d7a6, (q31_t)0x7c2f5203, (q31_t)0x7c2dcc14, (q31_t)0x7c2c45d8, (q31_t)0x7c2abf4f, + (q31_t)0x7c29387a, (q31_t)0x7c27b158, (q31_t)0x7c2629ea, (q31_t)0x7c24a22f, (q31_t)0x7c231a28, (q31_t)0x7c2191d4, (q31_t)0x7c200933, (q31_t)0x7c1e8046, + (q31_t)0x7c1cf70c, (q31_t)0x7c1b6d86, (q31_t)0x7c19e3b3, (q31_t)0x7c185994, (q31_t)0x7c16cf28, (q31_t)0x7c15446f, (q31_t)0x7c13b96a, (q31_t)0x7c122e19, + (q31_t)0x7c10a27b, (q31_t)0x7c0f1690, (q31_t)0x7c0d8a59, (q31_t)0x7c0bfdd5, (q31_t)0x7c0a7105, (q31_t)0x7c08e3e8, (q31_t)0x7c07567f, (q31_t)0x7c05c8c9, + (q31_t)0x7c043ac7, (q31_t)0x7c02ac78, (q31_t)0x7c011ddd, (q31_t)0x7bff8ef5, (q31_t)0x7bfdffc1, (q31_t)0x7bfc7041, (q31_t)0x7bfae073, (q31_t)0x7bf9505a, + (q31_t)0x7bf7bff4, (q31_t)0x7bf62f41, (q31_t)0x7bf49e42, (q31_t)0x7bf30cf6, (q31_t)0x7bf17b5e, (q31_t)0x7befe97a, (q31_t)0x7bee5749, (q31_t)0x7becc4cc, + (q31_t)0x7beb3202, (q31_t)0x7be99eec, (q31_t)0x7be80b89, (q31_t)0x7be677da, (q31_t)0x7be4e3df, (q31_t)0x7be34f97, (q31_t)0x7be1bb02, (q31_t)0x7be02621, + (q31_t)0x7bde90f4, (q31_t)0x7bdcfb7b, (q31_t)0x7bdb65b5, (q31_t)0x7bd9cfa2, (q31_t)0x7bd83944, (q31_t)0x7bd6a298, (q31_t)0x7bd50ba1, (q31_t)0x7bd3745d, + (q31_t)0x7bd1dccc, (q31_t)0x7bd044f0, (q31_t)0x7bceacc7, (q31_t)0x7bcd1451, (q31_t)0x7bcb7b8f, (q31_t)0x7bc9e281, (q31_t)0x7bc84927, (q31_t)0x7bc6af80, + (q31_t)0x7bc5158c, (q31_t)0x7bc37b4d, (q31_t)0x7bc1e0c1, (q31_t)0x7bc045e9, (q31_t)0x7bbeaac4, (q31_t)0x7bbd0f53, (q31_t)0x7bbb7396, (q31_t)0x7bb9d78c, + (q31_t)0x7bb83b36, (q31_t)0x7bb69e94, (q31_t)0x7bb501a5, (q31_t)0x7bb3646a, (q31_t)0x7bb1c6e3, (q31_t)0x7bb02910, (q31_t)0x7bae8af0, (q31_t)0x7bacec84, + (q31_t)0x7bab4dcc, (q31_t)0x7ba9aec7, (q31_t)0x7ba80f76, (q31_t)0x7ba66fd9, (q31_t)0x7ba4cfef, (q31_t)0x7ba32fba, (q31_t)0x7ba18f38, (q31_t)0x7b9fee69, + (q31_t)0x7b9e4d4f, (q31_t)0x7b9cabe8, (q31_t)0x7b9b0a35, (q31_t)0x7b996836, (q31_t)0x7b97c5ea, (q31_t)0x7b962352, (q31_t)0x7b94806e, (q31_t)0x7b92dd3e, + (q31_t)0x7b9139c2, (q31_t)0x7b8f95f9, (q31_t)0x7b8df1e4, (q31_t)0x7b8c4d83, (q31_t)0x7b8aa8d6, (q31_t)0x7b8903dc, (q31_t)0x7b875e96, (q31_t)0x7b85b904, + (q31_t)0x7b841326, (q31_t)0x7b826cfc, (q31_t)0x7b80c686, (q31_t)0x7b7f1fc3, (q31_t)0x7b7d78b4, (q31_t)0x7b7bd159, (q31_t)0x7b7a29b2, (q31_t)0x7b7881be, + (q31_t)0x7b76d97f, (q31_t)0x7b7530f3, (q31_t)0x7b73881b, (q31_t)0x7b71def7, (q31_t)0x7b703587, (q31_t)0x7b6e8bcb, (q31_t)0x7b6ce1c2, (q31_t)0x7b6b376e, + (q31_t)0x7b698ccd, (q31_t)0x7b67e1e0, (q31_t)0x7b6636a7, (q31_t)0x7b648b22, (q31_t)0x7b62df51, (q31_t)0x7b613334, (q31_t)0x7b5f86ca, (q31_t)0x7b5dda15, + (q31_t)0x7b5c2d13, (q31_t)0x7b5a7fc6, (q31_t)0x7b58d22c, (q31_t)0x7b572446, (q31_t)0x7b557614, (q31_t)0x7b53c796, (q31_t)0x7b5218cc, (q31_t)0x7b5069b6, + (q31_t)0x7b4eba53, (q31_t)0x7b4d0aa5, (q31_t)0x7b4b5aab, (q31_t)0x7b49aa64, (q31_t)0x7b47f9d2, (q31_t)0x7b4648f3, (q31_t)0x7b4497c9, (q31_t)0x7b42e652, + (q31_t)0x7b413490, (q31_t)0x7b3f8281, (q31_t)0x7b3dd026, (q31_t)0x7b3c1d80, (q31_t)0x7b3a6a8d, (q31_t)0x7b38b74e, (q31_t)0x7b3703c3, (q31_t)0x7b354fed, + (q31_t)0x7b339bca, (q31_t)0x7b31e75b, (q31_t)0x7b3032a0, (q31_t)0x7b2e7d9a, (q31_t)0x7b2cc847, (q31_t)0x7b2b12a8, (q31_t)0x7b295cbe, (q31_t)0x7b27a687, + (q31_t)0x7b25f004, (q31_t)0x7b243936, (q31_t)0x7b22821b, (q31_t)0x7b20cab5, (q31_t)0x7b1f1302, (q31_t)0x7b1d5b04, (q31_t)0x7b1ba2b9, (q31_t)0x7b19ea23, + (q31_t)0x7b183141, (q31_t)0x7b167813, (q31_t)0x7b14be99, (q31_t)0x7b1304d3, (q31_t)0x7b114ac1, (q31_t)0x7b0f9063, (q31_t)0x7b0dd5b9, (q31_t)0x7b0c1ac4, + (q31_t)0x7b0a5f82, (q31_t)0x7b08a3f5, (q31_t)0x7b06e81b, (q31_t)0x7b052bf6, (q31_t)0x7b036f85, (q31_t)0x7b01b2c8, (q31_t)0x7afff5bf, (q31_t)0x7afe386a, + (q31_t)0x7afc7aca, (q31_t)0x7afabcdd, (q31_t)0x7af8fea5, (q31_t)0x7af74021, (q31_t)0x7af58151, (q31_t)0x7af3c235, (q31_t)0x7af202cd, (q31_t)0x7af0431a, + (q31_t)0x7aee831a, (q31_t)0x7aecc2cf, (q31_t)0x7aeb0238, (q31_t)0x7ae94155, (q31_t)0x7ae78026, (q31_t)0x7ae5beac, (q31_t)0x7ae3fce6, (q31_t)0x7ae23ad4, + (q31_t)0x7ae07876, (q31_t)0x7adeb5cc, (q31_t)0x7adcf2d6, (q31_t)0x7adb2f95, (q31_t)0x7ad96c08, (q31_t)0x7ad7a82f, (q31_t)0x7ad5e40a, (q31_t)0x7ad41f9a, + (q31_t)0x7ad25ade, (q31_t)0x7ad095d6, (q31_t)0x7aced082, (q31_t)0x7acd0ae3, (q31_t)0x7acb44f8, (q31_t)0x7ac97ec1, (q31_t)0x7ac7b83e, (q31_t)0x7ac5f170, + (q31_t)0x7ac42a55, (q31_t)0x7ac262ef, (q31_t)0x7ac09b3e, (q31_t)0x7abed341, (q31_t)0x7abd0af7, (q31_t)0x7abb4263, (q31_t)0x7ab97982, (q31_t)0x7ab7b056, + (q31_t)0x7ab5e6de, (q31_t)0x7ab41d1b, (q31_t)0x7ab2530b, (q31_t)0x7ab088b0, (q31_t)0x7aaebe0a, (q31_t)0x7aacf318, (q31_t)0x7aab27da, (q31_t)0x7aa95c50, + (q31_t)0x7aa7907b, (q31_t)0x7aa5c45a, (q31_t)0x7aa3f7ed, (q31_t)0x7aa22b35, (q31_t)0x7aa05e31, (q31_t)0x7a9e90e1, (q31_t)0x7a9cc346, (q31_t)0x7a9af55f, + (q31_t)0x7a99272d, (q31_t)0x7a9758af, (q31_t)0x7a9589e5, (q31_t)0x7a93bad0, (q31_t)0x7a91eb6f, (q31_t)0x7a901bc2, (q31_t)0x7a8e4bca, (q31_t)0x7a8c7b87, + (q31_t)0x7a8aaaf7, (q31_t)0x7a88da1c, (q31_t)0x7a8708f6, (q31_t)0x7a853784, (q31_t)0x7a8365c6, (q31_t)0x7a8193bd, (q31_t)0x7a7fc168, (q31_t)0x7a7deec8, + (q31_t)0x7a7c1bdc, (q31_t)0x7a7a48a4, (q31_t)0x7a787521, (q31_t)0x7a76a153, (q31_t)0x7a74cd38, (q31_t)0x7a72f8d3, (q31_t)0x7a712422, (q31_t)0x7a6f4f25, + (q31_t)0x7a6d79dd, (q31_t)0x7a6ba449, (q31_t)0x7a69ce6a, (q31_t)0x7a67f83f, (q31_t)0x7a6621c9, (q31_t)0x7a644b07, (q31_t)0x7a6273fa, (q31_t)0x7a609ca1, + (q31_t)0x7a5ec4fc, (q31_t)0x7a5ced0d, (q31_t)0x7a5b14d1, (q31_t)0x7a593c4b, (q31_t)0x7a576379, (q31_t)0x7a558a5b, (q31_t)0x7a53b0f2, (q31_t)0x7a51d73d, + (q31_t)0x7a4ffd3d, (q31_t)0x7a4e22f2, (q31_t)0x7a4c485b, (q31_t)0x7a4a6d78, (q31_t)0x7a48924b, (q31_t)0x7a46b6d1, (q31_t)0x7a44db0d, (q31_t)0x7a42fefd, + (q31_t)0x7a4122a1, (q31_t)0x7a3f45fa, (q31_t)0x7a3d6908, (q31_t)0x7a3b8bca, (q31_t)0x7a39ae41, (q31_t)0x7a37d06d, (q31_t)0x7a35f24d, (q31_t)0x7a3413e2, + (q31_t)0x7a32352b, (q31_t)0x7a305629, (q31_t)0x7a2e76dc, (q31_t)0x7a2c9743, (q31_t)0x7a2ab75f, (q31_t)0x7a28d72f, (q31_t)0x7a26f6b4, (q31_t)0x7a2515ee, + (q31_t)0x7a2334dd, (q31_t)0x7a215380, (q31_t)0x7a1f71d7, (q31_t)0x7a1d8fe4, (q31_t)0x7a1bada5, (q31_t)0x7a19cb1b, (q31_t)0x7a17e845, (q31_t)0x7a160524, + (q31_t)0x7a1421b8, (q31_t)0x7a123e01, (q31_t)0x7a1059fe, (q31_t)0x7a0e75b0, (q31_t)0x7a0c9117, (q31_t)0x7a0aac32, (q31_t)0x7a08c702, (q31_t)0x7a06e187, + (q31_t)0x7a04fbc1, (q31_t)0x7a0315af, (q31_t)0x7a012f52, (q31_t)0x79ff48aa, (q31_t)0x79fd61b6, (q31_t)0x79fb7a77, (q31_t)0x79f992ed, (q31_t)0x79f7ab18, + (q31_t)0x79f5c2f8, (q31_t)0x79f3da8c, (q31_t)0x79f1f1d5, (q31_t)0x79f008d3, (q31_t)0x79ee1f86, (q31_t)0x79ec35ed, (q31_t)0x79ea4c09, (q31_t)0x79e861da, + (q31_t)0x79e67760, (q31_t)0x79e48c9b, (q31_t)0x79e2a18a, (q31_t)0x79e0b62e, (q31_t)0x79deca87, (q31_t)0x79dcde95, (q31_t)0x79daf258, (q31_t)0x79d905d0, + (q31_t)0x79d718fc, (q31_t)0x79d52bdd, (q31_t)0x79d33e73, (q31_t)0x79d150be, (q31_t)0x79cf62be, (q31_t)0x79cd7473, (q31_t)0x79cb85dc, (q31_t)0x79c996fb, + (q31_t)0x79c7a7ce, (q31_t)0x79c5b856, (q31_t)0x79c3c893, (q31_t)0x79c1d885, (q31_t)0x79bfe82c, (q31_t)0x79bdf788, (q31_t)0x79bc0698, (q31_t)0x79ba155e, + (q31_t)0x79b823d8, (q31_t)0x79b63207, (q31_t)0x79b43fec, (q31_t)0x79b24d85, (q31_t)0x79b05ad3, (q31_t)0x79ae67d6, (q31_t)0x79ac748e, (q31_t)0x79aa80fb, + (q31_t)0x79a88d1d, (q31_t)0x79a698f4, (q31_t)0x79a4a480, (q31_t)0x79a2afc1, (q31_t)0x79a0bab6, (q31_t)0x799ec561, (q31_t)0x799ccfc1, (q31_t)0x799ad9d5, + (q31_t)0x7998e39f, (q31_t)0x7996ed1e, (q31_t)0x7994f651, (q31_t)0x7992ff3a, (q31_t)0x799107d8, (q31_t)0x798f102a, (q31_t)0x798d1832, (q31_t)0x798b1fef, + (q31_t)0x79892761, (q31_t)0x79872e87, (q31_t)0x79853563, (q31_t)0x79833bf4, (q31_t)0x7981423a, (q31_t)0x797f4835, (q31_t)0x797d4de5, (q31_t)0x797b534a, + (q31_t)0x79795864, (q31_t)0x79775d33, (q31_t)0x797561b8, (q31_t)0x797365f1, (q31_t)0x797169df, (q31_t)0x796f6d83, (q31_t)0x796d70dc, (q31_t)0x796b73e9, + (q31_t)0x796976ac, (q31_t)0x79677924, (q31_t)0x79657b51, (q31_t)0x79637d33, (q31_t)0x79617eca, (q31_t)0x795f8017, (q31_t)0x795d8118, (q31_t)0x795b81cf, + (q31_t)0x7959823b, (q31_t)0x7957825c, (q31_t)0x79558232, (q31_t)0x795381bd, (q31_t)0x795180fe, (q31_t)0x794f7ff3, (q31_t)0x794d7e9e, (q31_t)0x794b7cfe, + (q31_t)0x79497b13, (q31_t)0x794778dd, (q31_t)0x7945765d, (q31_t)0x79437391, (q31_t)0x7941707b, (q31_t)0x793f6d1a, (q31_t)0x793d696f, (q31_t)0x793b6578, + (q31_t)0x79396137, (q31_t)0x79375cab, (q31_t)0x793557d4, (q31_t)0x793352b2, (q31_t)0x79314d46, (q31_t)0x792f478f, (q31_t)0x792d418d, (q31_t)0x792b3b40, + (q31_t)0x792934a9, (q31_t)0x79272dc7, (q31_t)0x7925269a, (q31_t)0x79231f22, (q31_t)0x79211760, (q31_t)0x791f0f53, (q31_t)0x791d06fb, (q31_t)0x791afe59, + (q31_t)0x7918f56c, (q31_t)0x7916ec34, (q31_t)0x7914e2b2, (q31_t)0x7912d8e4, (q31_t)0x7910cecc, (q31_t)0x790ec46a, (q31_t)0x790cb9bd, (q31_t)0x790aaec5, + (q31_t)0x7908a382, (q31_t)0x790697f5, (q31_t)0x79048c1d, (q31_t)0x79027ffa, (q31_t)0x7900738d, (q31_t)0x78fe66d5, (q31_t)0x78fc59d3, (q31_t)0x78fa4c86, + (q31_t)0x78f83eee, (q31_t)0x78f6310c, (q31_t)0x78f422df, (q31_t)0x78f21467, (q31_t)0x78f005a5, (q31_t)0x78edf698, (q31_t)0x78ebe741, (q31_t)0x78e9d79f, + (q31_t)0x78e7c7b2, (q31_t)0x78e5b77b, (q31_t)0x78e3a6f9, (q31_t)0x78e1962d, (q31_t)0x78df8516, (q31_t)0x78dd73b5, (q31_t)0x78db6209, (q31_t)0x78d95012, + (q31_t)0x78d73dd1, (q31_t)0x78d52b46, (q31_t)0x78d31870, (q31_t)0x78d1054f, (q31_t)0x78cef1e4, (q31_t)0x78ccde2e, (q31_t)0x78caca2e, (q31_t)0x78c8b5e3, + (q31_t)0x78c6a14e, (q31_t)0x78c48c6e, (q31_t)0x78c27744, (q31_t)0x78c061cf, (q31_t)0x78be4c10, (q31_t)0x78bc3606, (q31_t)0x78ba1fb2, (q31_t)0x78b80913, + (q31_t)0x78b5f22a, (q31_t)0x78b3daf7, (q31_t)0x78b1c379, (q31_t)0x78afabb0, (q31_t)0x78ad939d, (q31_t)0x78ab7b40, (q31_t)0x78a96298, (q31_t)0x78a749a6, + (q31_t)0x78a53069, (q31_t)0x78a316e2, (q31_t)0x78a0fd11, (q31_t)0x789ee2f5, (q31_t)0x789cc88f, (q31_t)0x789aadde, (q31_t)0x789892e3, (q31_t)0x7896779d, + (q31_t)0x78945c0d, (q31_t)0x78924033, (q31_t)0x7890240e, (q31_t)0x788e07a0, (q31_t)0x788beae6, (q31_t)0x7889cde2, (q31_t)0x7887b094, (q31_t)0x788592fc, + (q31_t)0x78837519, (q31_t)0x788156ec, (q31_t)0x787f3875, (q31_t)0x787d19b3, (q31_t)0x787afaa7, (q31_t)0x7878db50, (q31_t)0x7876bbb0, (q31_t)0x78749bc5, + (q31_t)0x78727b8f, (q31_t)0x78705b10, (q31_t)0x786e3a46, (q31_t)0x786c1932, (q31_t)0x7869f7d3, (q31_t)0x7867d62a, (q31_t)0x7865b437, (q31_t)0x786391fa, + (q31_t)0x78616f72, (q31_t)0x785f4ca1, (q31_t)0x785d2984, (q31_t)0x785b061e, (q31_t)0x7858e26e, (q31_t)0x7856be73, (q31_t)0x78549a2e, (q31_t)0x7852759e, + (q31_t)0x785050c5, (q31_t)0x784e2ba1, (q31_t)0x784c0633, (q31_t)0x7849e07b, (q31_t)0x7847ba79, (q31_t)0x7845942c, (q31_t)0x78436d96, (q31_t)0x784146b5, + (q31_t)0x783f1f8a, (q31_t)0x783cf815, (q31_t)0x783ad055, (q31_t)0x7838a84c, (q31_t)0x78367ff8, (q31_t)0x7834575a, (q31_t)0x78322e72, (q31_t)0x78300540, + (q31_t)0x782ddbc4, (q31_t)0x782bb1fd, (q31_t)0x782987ed, (q31_t)0x78275d92, (q31_t)0x782532ed, (q31_t)0x782307fe, (q31_t)0x7820dcc5, (q31_t)0x781eb142, + (q31_t)0x781c8575, (q31_t)0x781a595d, (q31_t)0x78182cfc, (q31_t)0x78160051, (q31_t)0x7813d35b, (q31_t)0x7811a61b, (q31_t)0x780f7892, (q31_t)0x780d4abe, + (q31_t)0x780b1ca0, (q31_t)0x7808ee38, (q31_t)0x7806bf86, (q31_t)0x7804908a, (q31_t)0x78026145, (q31_t)0x780031b5, (q31_t)0x77fe01db, (q31_t)0x77fbd1b6, + (q31_t)0x77f9a148, (q31_t)0x77f77090, (q31_t)0x77f53f8e, (q31_t)0x77f30e42, (q31_t)0x77f0dcac, (q31_t)0x77eeaacc, (q31_t)0x77ec78a2, (q31_t)0x77ea462e, + (q31_t)0x77e81370, (q31_t)0x77e5e068, (q31_t)0x77e3ad17, (q31_t)0x77e1797b, (q31_t)0x77df4595, (q31_t)0x77dd1165, (q31_t)0x77dadcec, (q31_t)0x77d8a828, + (q31_t)0x77d6731a, (q31_t)0x77d43dc3, (q31_t)0x77d20822, (q31_t)0x77cfd236, (q31_t)0x77cd9c01, (q31_t)0x77cb6582, (q31_t)0x77c92eb9, (q31_t)0x77c6f7a6, + (q31_t)0x77c4c04a, (q31_t)0x77c288a3, (q31_t)0x77c050b2, (q31_t)0x77be1878, (q31_t)0x77bbdff4, (q31_t)0x77b9a726, (q31_t)0x77b76e0e, (q31_t)0x77b534ac, + (q31_t)0x77b2fb00, (q31_t)0x77b0c10b, (q31_t)0x77ae86cc, (q31_t)0x77ac4c43, (q31_t)0x77aa1170, (q31_t)0x77a7d653, (q31_t)0x77a59aec, (q31_t)0x77a35f3c, + (q31_t)0x77a12342, (q31_t)0x779ee6fe, (q31_t)0x779caa70, (q31_t)0x779a6d99, (q31_t)0x77983077, (q31_t)0x7795f30c, (q31_t)0x7793b557, (q31_t)0x77917759, + (q31_t)0x778f3910, (q31_t)0x778cfa7e, (q31_t)0x778abba2, (q31_t)0x77887c7d, (q31_t)0x77863d0d, (q31_t)0x7783fd54, (q31_t)0x7781bd52, (q31_t)0x777f7d05, + (q31_t)0x777d3c6f, (q31_t)0x777afb8f, (q31_t)0x7778ba65, (q31_t)0x777678f2, (q31_t)0x77743735, (q31_t)0x7771f52e, (q31_t)0x776fb2de, (q31_t)0x776d7044, + (q31_t)0x776b2d60, (q31_t)0x7768ea33, (q31_t)0x7766a6bc, (q31_t)0x776462fb, (q31_t)0x77621ef1, (q31_t)0x775fda9d, (q31_t)0x775d95ff, (q31_t)0x775b5118, + (q31_t)0x77590be7, (q31_t)0x7756c66c, (q31_t)0x775480a8, (q31_t)0x77523a9b, (q31_t)0x774ff443, (q31_t)0x774dada2, (q31_t)0x774b66b8, (q31_t)0x77491f84, + (q31_t)0x7746d806, (q31_t)0x7744903f, (q31_t)0x7742482e, (q31_t)0x773fffd4, (q31_t)0x773db730, (q31_t)0x773b6e42, (q31_t)0x7739250b, (q31_t)0x7736db8b, + (q31_t)0x773491c0, (q31_t)0x773247ad, (q31_t)0x772ffd50, (q31_t)0x772db2a9, (q31_t)0x772b67b9, (q31_t)0x77291c7f, (q31_t)0x7726d0fc, (q31_t)0x7724852f, + (q31_t)0x77223919, (q31_t)0x771fecb9, (q31_t)0x771da010, (q31_t)0x771b531d, (q31_t)0x771905e1, (q31_t)0x7716b85b, (q31_t)0x77146a8c, (q31_t)0x77121c74, + (q31_t)0x770fce12, (q31_t)0x770d7f66, (q31_t)0x770b3072, (q31_t)0x7708e133, (q31_t)0x770691ab, (q31_t)0x770441da, (q31_t)0x7701f1c0, (q31_t)0x76ffa15c, + (q31_t)0x76fd50ae, (q31_t)0x76faffb8, (q31_t)0x76f8ae78, (q31_t)0x76f65cee, (q31_t)0x76f40b1b, (q31_t)0x76f1b8ff, (q31_t)0x76ef6699, (q31_t)0x76ed13ea, + (q31_t)0x76eac0f2, (q31_t)0x76e86db0, (q31_t)0x76e61a25, (q31_t)0x76e3c650, (q31_t)0x76e17233, (q31_t)0x76df1dcb, (q31_t)0x76dcc91b, (q31_t)0x76da7421, + (q31_t)0x76d81ede, (q31_t)0x76d5c952, (q31_t)0x76d3737c, (q31_t)0x76d11d5d, (q31_t)0x76cec6f5, (q31_t)0x76cc7043, (q31_t)0x76ca1948, (q31_t)0x76c7c204, + (q31_t)0x76c56a77, (q31_t)0x76c312a0, (q31_t)0x76c0ba80, (q31_t)0x76be6217, (q31_t)0x76bc0965, (q31_t)0x76b9b069, (q31_t)0x76b75724, (q31_t)0x76b4fd96, + (q31_t)0x76b2a3bf, (q31_t)0x76b0499e, (q31_t)0x76adef34, (q31_t)0x76ab9481, (q31_t)0x76a93985, (q31_t)0x76a6de40, (q31_t)0x76a482b1, (q31_t)0x76a226da, + (q31_t)0x769fcab9, (q31_t)0x769d6e4f, (q31_t)0x769b119b, (q31_t)0x7698b49f, (q31_t)0x76965759, (q31_t)0x7693f9ca, (q31_t)0x76919bf3, (q31_t)0x768f3dd2, + (q31_t)0x768cdf67, (q31_t)0x768a80b4, (q31_t)0x768821b8, (q31_t)0x7685c272, (q31_t)0x768362e4, (q31_t)0x7681030c, (q31_t)0x767ea2eb, (q31_t)0x767c4281, + (q31_t)0x7679e1ce, (q31_t)0x767780d2, (q31_t)0x76751f8d, (q31_t)0x7672bdfe, (q31_t)0x76705c27, (q31_t)0x766dfa07, (q31_t)0x766b979d, (q31_t)0x766934eb, + (q31_t)0x7666d1ef, (q31_t)0x76646eab, (q31_t)0x76620b1d, (q31_t)0x765fa747, (q31_t)0x765d4327, (q31_t)0x765adebe, (q31_t)0x76587a0d, (q31_t)0x76561512, + (q31_t)0x7653afce, (q31_t)0x76514a42, (q31_t)0x764ee46c, (q31_t)0x764c7e4d, (q31_t)0x764a17e6, (q31_t)0x7647b135, (q31_t)0x76454a3c, (q31_t)0x7642e2f9, + (q31_t)0x76407b6e, (q31_t)0x763e139a, (q31_t)0x763bab7c, (q31_t)0x76394316, (q31_t)0x7636da67, (q31_t)0x7634716f, (q31_t)0x7632082e, (q31_t)0x762f9ea4, + (q31_t)0x762d34d1, (q31_t)0x762acab6, (q31_t)0x76286051, (q31_t)0x7625f5a3, (q31_t)0x76238aad, (q31_t)0x76211f6e, (q31_t)0x761eb3e6, (q31_t)0x761c4815, + (q31_t)0x7619dbfb, (q31_t)0x76176f98, (q31_t)0x761502ed, (q31_t)0x761295f9, (q31_t)0x761028bb, (q31_t)0x760dbb35, (q31_t)0x760b4d67, (q31_t)0x7608df4f, + (q31_t)0x760670ee, (q31_t)0x76040245, (q31_t)0x76019353, (q31_t)0x75ff2418, (q31_t)0x75fcb495, (q31_t)0x75fa44c8, (q31_t)0x75f7d4b3, (q31_t)0x75f56455, + (q31_t)0x75f2f3ae, (q31_t)0x75f082bf, (q31_t)0x75ee1187, (q31_t)0x75eba006, (q31_t)0x75e92e3c, (q31_t)0x75e6bc2a, (q31_t)0x75e449ce, (q31_t)0x75e1d72b, + (q31_t)0x75df643e, (q31_t)0x75dcf109, (q31_t)0x75da7d8b, (q31_t)0x75d809c4, (q31_t)0x75d595b4, (q31_t)0x75d3215c, (q31_t)0x75d0acbc, (q31_t)0x75ce37d2, + (q31_t)0x75cbc2a0, (q31_t)0x75c94d25, (q31_t)0x75c6d762, (q31_t)0x75c46156, (q31_t)0x75c1eb01, (q31_t)0x75bf7464, (q31_t)0x75bcfd7e, (q31_t)0x75ba864f, + (q31_t)0x75b80ed8, (q31_t)0x75b59718, (q31_t)0x75b31f0f, (q31_t)0x75b0a6be, (q31_t)0x75ae2e25, (q31_t)0x75abb542, (q31_t)0x75a93c18, (q31_t)0x75a6c2a4, + (q31_t)0x75a448e8, (q31_t)0x75a1cee4, (q31_t)0x759f5496, (q31_t)0x759cda01, (q31_t)0x759a5f22, (q31_t)0x7597e3fc, (q31_t)0x7595688c, (q31_t)0x7592ecd4, + (q31_t)0x759070d4, (q31_t)0x758df48b, (q31_t)0x758b77fa, (q31_t)0x7588fb20, (q31_t)0x75867dfd, (q31_t)0x75840093, (q31_t)0x758182df, (q31_t)0x757f04e3, + (q31_t)0x757c869f, (q31_t)0x757a0812, (q31_t)0x7577893d, (q31_t)0x75750a1f, (q31_t)0x75728ab9, (q31_t)0x75700b0a, (q31_t)0x756d8b13, (q31_t)0x756b0ad3, + (q31_t)0x75688a4b, (q31_t)0x7566097b, (q31_t)0x75638862, (q31_t)0x75610701, (q31_t)0x755e8557, (q31_t)0x755c0365, (q31_t)0x7559812b, (q31_t)0x7556fea8, + (q31_t)0x75547bdd, (q31_t)0x7551f8c9, (q31_t)0x754f756e, (q31_t)0x754cf1c9, (q31_t)0x754a6ddd, (q31_t)0x7547e9a8, (q31_t)0x7545652a, (q31_t)0x7542e065, + (q31_t)0x75405b57, (q31_t)0x753dd600, (q31_t)0x753b5061, (q31_t)0x7538ca7b, (q31_t)0x7536444b, (q31_t)0x7533bdd4, (q31_t)0x75313714, (q31_t)0x752eb00c, + (q31_t)0x752c28bb, (q31_t)0x7529a122, (q31_t)0x75271941, (q31_t)0x75249118, (q31_t)0x752208a7, (q31_t)0x751f7fed, (q31_t)0x751cf6eb, (q31_t)0x751a6da0, + (q31_t)0x7517e40e, (q31_t)0x75155a33, (q31_t)0x7512d010, (q31_t)0x751045a5, (q31_t)0x750dbaf2, (q31_t)0x750b2ff6, (q31_t)0x7508a4b2, (q31_t)0x75061926, + (q31_t)0x75038d52, (q31_t)0x75010136, (q31_t)0x74fe74d1, (q31_t)0x74fbe825, (q31_t)0x74f95b30, (q31_t)0x74f6cdf3, (q31_t)0x74f4406d, (q31_t)0x74f1b2a0, + (q31_t)0x74ef248b, (q31_t)0x74ec962d, (q31_t)0x74ea0787, (q31_t)0x74e7789a, (q31_t)0x74e4e964, (q31_t)0x74e259e6, (q31_t)0x74dfca20, (q31_t)0x74dd3a11, + (q31_t)0x74daa9bb, (q31_t)0x74d8191d, (q31_t)0x74d58836, (q31_t)0x74d2f708, (q31_t)0x74d06591, (q31_t)0x74cdd3d2, (q31_t)0x74cb41cc, (q31_t)0x74c8af7d, + (q31_t)0x74c61ce6, (q31_t)0x74c38a07, (q31_t)0x74c0f6e0, (q31_t)0x74be6372, (q31_t)0x74bbcfbb, (q31_t)0x74b93bbc, (q31_t)0x74b6a775, (q31_t)0x74b412e6, + (q31_t)0x74b17e0f, (q31_t)0x74aee8f0, (q31_t)0x74ac5389, (q31_t)0x74a9bddb, (q31_t)0x74a727e4, (q31_t)0x74a491a5, (q31_t)0x74a1fb1e, (q31_t)0x749f6450, + (q31_t)0x749ccd39, (q31_t)0x749a35db, (q31_t)0x74979e34, (q31_t)0x74950646, (q31_t)0x74926e10, (q31_t)0x748fd592, (q31_t)0x748d3ccb, (q31_t)0x748aa3be, + (q31_t)0x74880a68, (q31_t)0x748570ca, (q31_t)0x7482d6e4, (q31_t)0x74803cb7, (q31_t)0x747da242, (q31_t)0x747b0784, (q31_t)0x74786c7f, (q31_t)0x7475d132, + (q31_t)0x7473359e, (q31_t)0x747099c1, (q31_t)0x746dfd9d, (q31_t)0x746b6131, (q31_t)0x7468c47c, (q31_t)0x74662781, (q31_t)0x74638a3d, (q31_t)0x7460ecb2, + (q31_t)0x745e4ede, (q31_t)0x745bb0c3, (q31_t)0x74591261, (q31_t)0x745673b6, (q31_t)0x7453d4c4, (q31_t)0x7451358a, (q31_t)0x744e9608, (q31_t)0x744bf63e, + (q31_t)0x7449562d, (q31_t)0x7446b5d4, (q31_t)0x74441533, (q31_t)0x7441744b, (q31_t)0x743ed31b, (q31_t)0x743c31a3, (q31_t)0x74398fe3, (q31_t)0x7436eddc, + (q31_t)0x74344b8d, (q31_t)0x7431a8f6, (q31_t)0x742f0618, (q31_t)0x742c62f2, (q31_t)0x7429bf84, (q31_t)0x74271bcf, (q31_t)0x742477d2, (q31_t)0x7421d38e, + (q31_t)0x741f2f01, (q31_t)0x741c8a2d, (q31_t)0x7419e512, (q31_t)0x74173faf, (q31_t)0x74149a04, (q31_t)0x7411f412, (q31_t)0x740f4dd8, (q31_t)0x740ca756, + (q31_t)0x740a008d, (q31_t)0x7407597d, (q31_t)0x7404b224, (q31_t)0x74020a85, (q31_t)0x73ff629d, (q31_t)0x73fcba6e, (q31_t)0x73fa11f8, (q31_t)0x73f7693a, + (q31_t)0x73f4c034, (q31_t)0x73f216e7, (q31_t)0x73ef6d53, (q31_t)0x73ecc377, (q31_t)0x73ea1953, (q31_t)0x73e76ee8, (q31_t)0x73e4c435, (q31_t)0x73e2193b, + (q31_t)0x73df6df9, (q31_t)0x73dcc270, (q31_t)0x73da16a0, (q31_t)0x73d76a88, (q31_t)0x73d4be28, (q31_t)0x73d21182, (q31_t)0x73cf6493, (q31_t)0x73ccb75d, + (q31_t)0x73ca09e0, (q31_t)0x73c75c1c, (q31_t)0x73c4ae10, (q31_t)0x73c1ffbc, (q31_t)0x73bf5121, (q31_t)0x73bca23f, (q31_t)0x73b9f315, (q31_t)0x73b743a4, + (q31_t)0x73b493ec, (q31_t)0x73b1e3ec, (q31_t)0x73af33a5, (q31_t)0x73ac8316, (q31_t)0x73a9d240, (q31_t)0x73a72123, (q31_t)0x73a46fbf, (q31_t)0x73a1be13, + (q31_t)0x739f0c20, (q31_t)0x739c59e5, (q31_t)0x7399a763, (q31_t)0x7396f49a, (q31_t)0x73944189, (q31_t)0x73918e32, (q31_t)0x738eda93, (q31_t)0x738c26ac, + (q31_t)0x7389727f, (q31_t)0x7386be0a, (q31_t)0x7384094e, (q31_t)0x7381544a, (q31_t)0x737e9f00, (q31_t)0x737be96e, (q31_t)0x73793395, (q31_t)0x73767d74, + (q31_t)0x7373c70d, (q31_t)0x7371105e, (q31_t)0x736e5968, (q31_t)0x736ba22b, (q31_t)0x7368eaa6, (q31_t)0x736632db, (q31_t)0x73637ac8, (q31_t)0x7360c26e, + (q31_t)0x735e09cd, (q31_t)0x735b50e4, (q31_t)0x735897b5, (q31_t)0x7355de3e, (q31_t)0x73532481, (q31_t)0x73506a7c, (q31_t)0x734db030, (q31_t)0x734af59d, + (q31_t)0x73483ac2, (q31_t)0x73457fa1, (q31_t)0x7342c438, (q31_t)0x73400889, (q31_t)0x733d4c92, (q31_t)0x733a9054, (q31_t)0x7337d3d0, (q31_t)0x73351704, + (q31_t)0x733259f1, (q31_t)0x732f9c97, (q31_t)0x732cdef6, (q31_t)0x732a210d, (q31_t)0x732762de, (q31_t)0x7324a468, (q31_t)0x7321e5ab, (q31_t)0x731f26a7, + (q31_t)0x731c675b, (q31_t)0x7319a7c9, (q31_t)0x7316e7f0, (q31_t)0x731427cf, (q31_t)0x73116768, (q31_t)0x730ea6ba, (q31_t)0x730be5c5, (q31_t)0x73092489, + (q31_t)0x73066306, (q31_t)0x7303a13b, (q31_t)0x7300df2a, (q31_t)0x72fe1cd2, (q31_t)0x72fb5a34, (q31_t)0x72f8974e, (q31_t)0x72f5d421, (q31_t)0x72f310ad, + (q31_t)0x72f04cf3, (q31_t)0x72ed88f1, (q31_t)0x72eac4a9, (q31_t)0x72e8001a, (q31_t)0x72e53b44, (q31_t)0x72e27627, (q31_t)0x72dfb0c3, (q31_t)0x72dceb18, + (q31_t)0x72da2526, (q31_t)0x72d75eee, (q31_t)0x72d4986f, (q31_t)0x72d1d1a9, (q31_t)0x72cf0a9c, (q31_t)0x72cc4348, (q31_t)0x72c97bad, (q31_t)0x72c6b3cc, + (q31_t)0x72c3eba4, (q31_t)0x72c12335, (q31_t)0x72be5a7f, (q31_t)0x72bb9183, (q31_t)0x72b8c83f, (q31_t)0x72b5feb5, (q31_t)0x72b334e4, (q31_t)0x72b06acd, + (q31_t)0x72ada06f, (q31_t)0x72aad5c9, (q31_t)0x72a80ade, (q31_t)0x72a53fab, (q31_t)0x72a27432, (q31_t)0x729fa872, (q31_t)0x729cdc6b, (q31_t)0x729a101e, + (q31_t)0x7297438a, (q31_t)0x729476af, (q31_t)0x7291a98e, (q31_t)0x728edc26, (q31_t)0x728c0e77, (q31_t)0x72894082, (q31_t)0x72867245, (q31_t)0x7283a3c3, + (q31_t)0x7280d4f9, (q31_t)0x727e05e9, (q31_t)0x727b3693, (q31_t)0x727866f6, (q31_t)0x72759712, (q31_t)0x7272c6e7, (q31_t)0x726ff676, (q31_t)0x726d25bf, + (q31_t)0x726a54c1, (q31_t)0x7267837c, (q31_t)0x7264b1f0, (q31_t)0x7261e01e, (q31_t)0x725f0e06, (q31_t)0x725c3ba7, (q31_t)0x72596901, (q31_t)0x72569615, + (q31_t)0x7253c2e3, (q31_t)0x7250ef6a, (q31_t)0x724e1baa, (q31_t)0x724b47a4, (q31_t)0x72487357, (q31_t)0x72459ec4, (q31_t)0x7242c9ea, (q31_t)0x723ff4ca, + (q31_t)0x723d1f63, (q31_t)0x723a49b6, (q31_t)0x723773c3, (q31_t)0x72349d89, (q31_t)0x7231c708, (q31_t)0x722ef041, (q31_t)0x722c1934, (q31_t)0x722941e0, + (q31_t)0x72266a46, (q31_t)0x72239266, (q31_t)0x7220ba3f, (q31_t)0x721de1d1, (q31_t)0x721b091d, (q31_t)0x72183023, (q31_t)0x721556e3, (q31_t)0x72127d5c, + (q31_t)0x720fa38e, (q31_t)0x720cc97b, (q31_t)0x7209ef21, (q31_t)0x72071480, (q31_t)0x7204399a, (q31_t)0x72015e6d, (q31_t)0x71fe82f9, (q31_t)0x71fba740, + (q31_t)0x71f8cb40, (q31_t)0x71f5eefa, (q31_t)0x71f3126d, (q31_t)0x71f0359a, (q31_t)0x71ed5881, (q31_t)0x71ea7b22, (q31_t)0x71e79d7c, (q31_t)0x71e4bf90, + (q31_t)0x71e1e15e, (q31_t)0x71df02e5, (q31_t)0x71dc2427, (q31_t)0x71d94522, (q31_t)0x71d665d6, (q31_t)0x71d38645, (q31_t)0x71d0a66d, (q31_t)0x71cdc650, + (q31_t)0x71cae5ec, (q31_t)0x71c80542, (q31_t)0x71c52451, (q31_t)0x71c2431b, (q31_t)0x71bf619e, (q31_t)0x71bc7fdb, (q31_t)0x71b99dd2, (q31_t)0x71b6bb83, + (q31_t)0x71b3d8ed, (q31_t)0x71b0f612, (q31_t)0x71ae12f0, (q31_t)0x71ab2f89, (q31_t)0x71a84bdb, (q31_t)0x71a567e7, (q31_t)0x71a283ad, (q31_t)0x719f9f2c, + (q31_t)0x719cba66, (q31_t)0x7199d55a, (q31_t)0x7196f008, (q31_t)0x71940a6f, (q31_t)0x71912490, (q31_t)0x718e3e6c, (q31_t)0x718b5801, (q31_t)0x71887151, + (q31_t)0x71858a5a, (q31_t)0x7182a31d, (q31_t)0x717fbb9a, (q31_t)0x717cd3d2, (q31_t)0x7179ebc3, (q31_t)0x7177036e, (q31_t)0x71741ad3, (q31_t)0x717131f3, + (q31_t)0x716e48cc, (q31_t)0x716b5f5f, (q31_t)0x716875ad, (q31_t)0x71658bb4, (q31_t)0x7162a175, (q31_t)0x715fb6f1, (q31_t)0x715ccc26, (q31_t)0x7159e116, + (q31_t)0x7156f5c0, (q31_t)0x71540a24, (q31_t)0x71511e42, (q31_t)0x714e321a, (q31_t)0x714b45ac, (q31_t)0x714858f8, (q31_t)0x71456bfe, (q31_t)0x71427ebf, + (q31_t)0x713f9139, (q31_t)0x713ca36e, (q31_t)0x7139b55d, (q31_t)0x7136c706, (q31_t)0x7133d869, (q31_t)0x7130e987, (q31_t)0x712dfa5e, (q31_t)0x712b0af0, + (q31_t)0x71281b3c, (q31_t)0x71252b42, (q31_t)0x71223b02, (q31_t)0x711f4a7d, (q31_t)0x711c59b2, (q31_t)0x711968a1, (q31_t)0x7116774a, (q31_t)0x711385ad, + (q31_t)0x711093cb, (q31_t)0x710da1a3, (q31_t)0x710aaf35, (q31_t)0x7107bc82, (q31_t)0x7104c989, (q31_t)0x7101d64a, (q31_t)0x70fee2c5, (q31_t)0x70fbeefb, + (q31_t)0x70f8faeb, (q31_t)0x70f60695, (q31_t)0x70f311fa, (q31_t)0x70f01d19, (q31_t)0x70ed27f2, (q31_t)0x70ea3286, (q31_t)0x70e73cd4, (q31_t)0x70e446dc, + (q31_t)0x70e1509f, (q31_t)0x70de5a1c, (q31_t)0x70db6353, (q31_t)0x70d86c45, (q31_t)0x70d574f1, (q31_t)0x70d27d58, (q31_t)0x70cf8579, (q31_t)0x70cc8d54, + (q31_t)0x70c994ea, (q31_t)0x70c69c3a, (q31_t)0x70c3a345, (q31_t)0x70c0aa0a, (q31_t)0x70bdb08a, (q31_t)0x70bab6c4, (q31_t)0x70b7bcb8, (q31_t)0x70b4c267, + (q31_t)0x70b1c7d1, (q31_t)0x70aeccf5, (q31_t)0x70abd1d3, (q31_t)0x70a8d66c, (q31_t)0x70a5dac0, (q31_t)0x70a2dece, (q31_t)0x709fe296, (q31_t)0x709ce619, + (q31_t)0x7099e957, (q31_t)0x7096ec4f, (q31_t)0x7093ef01, (q31_t)0x7090f16e, (q31_t)0x708df396, (q31_t)0x708af579, (q31_t)0x7087f715, (q31_t)0x7084f86d, + (q31_t)0x7081f97f, (q31_t)0x707efa4c, (q31_t)0x707bfad3, (q31_t)0x7078fb15, (q31_t)0x7075fb11, (q31_t)0x7072fac9, (q31_t)0x706ffa3a, (q31_t)0x706cf967, + (q31_t)0x7069f84e, (q31_t)0x7066f6f0, (q31_t)0x7063f54c, (q31_t)0x7060f363, (q31_t)0x705df135, (q31_t)0x705aeec1, (q31_t)0x7057ec08, (q31_t)0x7054e90a, + (q31_t)0x7051e5c7, (q31_t)0x704ee23e, (q31_t)0x704bde70, (q31_t)0x7048da5d, (q31_t)0x7045d604, (q31_t)0x7042d166, (q31_t)0x703fcc83, (q31_t)0x703cc75b, + (q31_t)0x7039c1ed, (q31_t)0x7036bc3b, (q31_t)0x7033b643, (q31_t)0x7030b005, (q31_t)0x702da983, (q31_t)0x702aa2bb, (q31_t)0x70279baf, (q31_t)0x7024945d, + (q31_t)0x70218cc6, (q31_t)0x701e84e9, (q31_t)0x701b7cc8, (q31_t)0x70187461, (q31_t)0x70156bb5, (q31_t)0x701262c4, (q31_t)0x700f598e, (q31_t)0x700c5013, + (q31_t)0x70094653, (q31_t)0x70063c4e, (q31_t)0x70033203, (q31_t)0x70002774, (q31_t)0x6ffd1c9f, (q31_t)0x6ffa1185, (q31_t)0x6ff70626, (q31_t)0x6ff3fa82, + (q31_t)0x6ff0ee99, (q31_t)0x6fede26b, (q31_t)0x6fead5f8, (q31_t)0x6fe7c940, (q31_t)0x6fe4bc43, (q31_t)0x6fe1af01, (q31_t)0x6fdea17a, (q31_t)0x6fdb93ae, + (q31_t)0x6fd8859d, (q31_t)0x6fd57746, (q31_t)0x6fd268ab, (q31_t)0x6fcf59cb, (q31_t)0x6fcc4aa6, (q31_t)0x6fc93b3c, (q31_t)0x6fc62b8d, (q31_t)0x6fc31b99, + (q31_t)0x6fc00b60, (q31_t)0x6fbcfae2, (q31_t)0x6fb9ea20, (q31_t)0x6fb6d918, (q31_t)0x6fb3c7cb, (q31_t)0x6fb0b63a, (q31_t)0x6fada464, (q31_t)0x6faa9248, + (q31_t)0x6fa77fe8, (q31_t)0x6fa46d43, (q31_t)0x6fa15a59, (q31_t)0x6f9e472b, (q31_t)0x6f9b33b7, (q31_t)0x6f981fff, (q31_t)0x6f950c01, (q31_t)0x6f91f7bf, + (q31_t)0x6f8ee338, (q31_t)0x6f8bce6c, (q31_t)0x6f88b95c, (q31_t)0x6f85a407, (q31_t)0x6f828e6c, (q31_t)0x6f7f788d, (q31_t)0x6f7c626a, (q31_t)0x6f794c01, + (q31_t)0x6f763554, (q31_t)0x6f731e62, (q31_t)0x6f70072b, (q31_t)0x6f6cefb0, (q31_t)0x6f69d7f0, (q31_t)0x6f66bfeb, (q31_t)0x6f63a7a1, (q31_t)0x6f608f13, + (q31_t)0x6f5d7640, (q31_t)0x6f5a5d28, (q31_t)0x6f5743cb, (q31_t)0x6f542a2a, (q31_t)0x6f511044, (q31_t)0x6f4df61a, (q31_t)0x6f4adbab, (q31_t)0x6f47c0f7, + (q31_t)0x6f44a5ff, (q31_t)0x6f418ac2, (q31_t)0x6f3e6f40, (q31_t)0x6f3b537a, (q31_t)0x6f38376f, (q31_t)0x6f351b1f, (q31_t)0x6f31fe8b, (q31_t)0x6f2ee1b2, + (q31_t)0x6f2bc495, (q31_t)0x6f28a733, (q31_t)0x6f25898d, (q31_t)0x6f226ba2, (q31_t)0x6f1f4d72, (q31_t)0x6f1c2efe, (q31_t)0x6f191045, (q31_t)0x6f15f148, + (q31_t)0x6f12d206, (q31_t)0x6f0fb280, (q31_t)0x6f0c92b6, (q31_t)0x6f0972a6, (q31_t)0x6f065253, (q31_t)0x6f0331ba, (q31_t)0x6f0010de, (q31_t)0x6efcefbd, + (q31_t)0x6ef9ce57, (q31_t)0x6ef6acad, (q31_t)0x6ef38abe, (q31_t)0x6ef0688b, (q31_t)0x6eed4614, (q31_t)0x6eea2358, (q31_t)0x6ee70058, (q31_t)0x6ee3dd13, + (q31_t)0x6ee0b98a, (q31_t)0x6edd95bd, (q31_t)0x6eda71ab, (q31_t)0x6ed74d55, (q31_t)0x6ed428ba, (q31_t)0x6ed103db, (q31_t)0x6ecddeb8, (q31_t)0x6ecab950, + (q31_t)0x6ec793a4, (q31_t)0x6ec46db4, (q31_t)0x6ec1477f, (q31_t)0x6ebe2106, (q31_t)0x6ebafa49, (q31_t)0x6eb7d347, (q31_t)0x6eb4ac02, (q31_t)0x6eb18477, + (q31_t)0x6eae5ca9, (q31_t)0x6eab3496, (q31_t)0x6ea80c3f, (q31_t)0x6ea4e3a4, (q31_t)0x6ea1bac4, (q31_t)0x6e9e91a1, (q31_t)0x6e9b6839, (q31_t)0x6e983e8d, + (q31_t)0x6e95149c, (q31_t)0x6e91ea67, (q31_t)0x6e8ebfef, (q31_t)0x6e8b9532, (q31_t)0x6e886a30, (q31_t)0x6e853eeb, (q31_t)0x6e821361, (q31_t)0x6e7ee794, + (q31_t)0x6e7bbb82, (q31_t)0x6e788f2c, (q31_t)0x6e756291, (q31_t)0x6e7235b3, (q31_t)0x6e6f0890, (q31_t)0x6e6bdb2a, (q31_t)0x6e68ad7f, (q31_t)0x6e657f90, + (q31_t)0x6e62515d, (q31_t)0x6e5f22e6, (q31_t)0x6e5bf42b, (q31_t)0x6e58c52c, (q31_t)0x6e5595e9, (q31_t)0x6e526662, (q31_t)0x6e4f3696, (q31_t)0x6e4c0687, + (q31_t)0x6e48d633, (q31_t)0x6e45a59c, (q31_t)0x6e4274c1, (q31_t)0x6e3f43a1, (q31_t)0x6e3c123e, (q31_t)0x6e38e096, (q31_t)0x6e35aeab, (q31_t)0x6e327c7b, + (q31_t)0x6e2f4a08, (q31_t)0x6e2c1750, (q31_t)0x6e28e455, (q31_t)0x6e25b115, (q31_t)0x6e227d92, (q31_t)0x6e1f49cb, (q31_t)0x6e1c15c0, (q31_t)0x6e18e171, + (q31_t)0x6e15acde, (q31_t)0x6e127807, (q31_t)0x6e0f42ec, (q31_t)0x6e0c0d8e, (q31_t)0x6e08d7eb, (q31_t)0x6e05a205, (q31_t)0x6e026bda, (q31_t)0x6dff356c, + (q31_t)0x6dfbfeba, (q31_t)0x6df8c7c4, (q31_t)0x6df5908b, (q31_t)0x6df2590d, (q31_t)0x6def214c, (q31_t)0x6debe947, (q31_t)0x6de8b0fe, (q31_t)0x6de57871, + (q31_t)0x6de23fa0, (q31_t)0x6ddf068c, (q31_t)0x6ddbcd34, (q31_t)0x6dd89398, (q31_t)0x6dd559b9, (q31_t)0x6dd21f95, (q31_t)0x6dcee52e, (q31_t)0x6dcbaa83, + (q31_t)0x6dc86f95, (q31_t)0x6dc53462, (q31_t)0x6dc1f8ec, (q31_t)0x6dbebd33, (q31_t)0x6dbb8135, (q31_t)0x6db844f4, (q31_t)0x6db5086f, (q31_t)0x6db1cba7, + (q31_t)0x6dae8e9b, (q31_t)0x6dab514b, (q31_t)0x6da813b8, (q31_t)0x6da4d5e1, (q31_t)0x6da197c6, (q31_t)0x6d9e5968, (q31_t)0x6d9b1ac6, (q31_t)0x6d97dbe0, + (q31_t)0x6d949cb7, (q31_t)0x6d915d4a, (q31_t)0x6d8e1d9a, (q31_t)0x6d8adda6, (q31_t)0x6d879d6e, (q31_t)0x6d845cf3, (q31_t)0x6d811c35, (q31_t)0x6d7ddb33, + (q31_t)0x6d7a99ed, (q31_t)0x6d775864, (q31_t)0x6d741697, (q31_t)0x6d70d487, (q31_t)0x6d6d9233, (q31_t)0x6d6a4f9c, (q31_t)0x6d670cc1, (q31_t)0x6d63c9a3, + (q31_t)0x6d608641, (q31_t)0x6d5d429c, (q31_t)0x6d59feb3, (q31_t)0x6d56ba87, (q31_t)0x6d537617, (q31_t)0x6d503164, (q31_t)0x6d4cec6e, (q31_t)0x6d49a734, + (q31_t)0x6d4661b7, (q31_t)0x6d431bf6, (q31_t)0x6d3fd5f2, (q31_t)0x6d3c8fab, (q31_t)0x6d394920, (q31_t)0x6d360252, (q31_t)0x6d32bb40, (q31_t)0x6d2f73eb, + (q31_t)0x6d2c2c53, (q31_t)0x6d28e477, (q31_t)0x6d259c58, (q31_t)0x6d2253f6, (q31_t)0x6d1f0b50, (q31_t)0x6d1bc267, (q31_t)0x6d18793b, (q31_t)0x6d152fcc, + (q31_t)0x6d11e619, (q31_t)0x6d0e9c23, (q31_t)0x6d0b51e9, (q31_t)0x6d08076d, (q31_t)0x6d04bcad, (q31_t)0x6d0171aa, (q31_t)0x6cfe2663, (q31_t)0x6cfadada, + (q31_t)0x6cf78f0d, (q31_t)0x6cf442fd, (q31_t)0x6cf0f6aa, (q31_t)0x6cedaa13, (q31_t)0x6cea5d3a, (q31_t)0x6ce7101d, (q31_t)0x6ce3c2bd, (q31_t)0x6ce0751a, + (q31_t)0x6cdd2733, (q31_t)0x6cd9d90a, (q31_t)0x6cd68a9d, (q31_t)0x6cd33bed, (q31_t)0x6ccfecfa, (q31_t)0x6ccc9dc4, (q31_t)0x6cc94e4b, (q31_t)0x6cc5fe8f, + (q31_t)0x6cc2ae90, (q31_t)0x6cbf5e4d, (q31_t)0x6cbc0dc8, (q31_t)0x6cb8bcff, (q31_t)0x6cb56bf4, (q31_t)0x6cb21aa5, (q31_t)0x6caec913, (q31_t)0x6cab773e, + (q31_t)0x6ca82527, (q31_t)0x6ca4d2cc, (q31_t)0x6ca1802e, (q31_t)0x6c9e2d4d, (q31_t)0x6c9ada29, (q31_t)0x6c9786c2, (q31_t)0x6c943318, (q31_t)0x6c90df2c, + (q31_t)0x6c8d8afc, (q31_t)0x6c8a3689, (q31_t)0x6c86e1d3, (q31_t)0x6c838cdb, (q31_t)0x6c80379f, (q31_t)0x6c7ce220, (q31_t)0x6c798c5f, (q31_t)0x6c76365b, + (q31_t)0x6c72e013, (q31_t)0x6c6f8989, (q31_t)0x6c6c32bc, (q31_t)0x6c68dbac, (q31_t)0x6c658459, (q31_t)0x6c622cc4, (q31_t)0x6c5ed4eb, (q31_t)0x6c5b7cd0, + (q31_t)0x6c582472, (q31_t)0x6c54cbd1, (q31_t)0x6c5172ed, (q31_t)0x6c4e19c6, (q31_t)0x6c4ac05d, (q31_t)0x6c4766b0, (q31_t)0x6c440cc1, (q31_t)0x6c40b28f, + (q31_t)0x6c3d581b, (q31_t)0x6c39fd63, (q31_t)0x6c36a269, (q31_t)0x6c33472c, (q31_t)0x6c2febad, (q31_t)0x6c2c8fea, (q31_t)0x6c2933e5, (q31_t)0x6c25d79d, + (q31_t)0x6c227b13, (q31_t)0x6c1f1e45, (q31_t)0x6c1bc136, (q31_t)0x6c1863e3, (q31_t)0x6c15064e, (q31_t)0x6c11a876, (q31_t)0x6c0e4a5b, (q31_t)0x6c0aebfe, + (q31_t)0x6c078d5e, (q31_t)0x6c042e7b, (q31_t)0x6c00cf56, (q31_t)0x6bfd6fee, (q31_t)0x6bfa1044, (q31_t)0x6bf6b056, (q31_t)0x6bf35027, (q31_t)0x6befefb5, + (q31_t)0x6bec8f00, (q31_t)0x6be92e08, (q31_t)0x6be5ccce, (q31_t)0x6be26b52, (q31_t)0x6bdf0993, (q31_t)0x6bdba791, (q31_t)0x6bd8454d, (q31_t)0x6bd4e2c6, + (q31_t)0x6bd17ffd, (q31_t)0x6bce1cf1, (q31_t)0x6bcab9a3, (q31_t)0x6bc75613, (q31_t)0x6bc3f23f, (q31_t)0x6bc08e2a, (q31_t)0x6bbd29d2, (q31_t)0x6bb9c537, + (q31_t)0x6bb6605a, (q31_t)0x6bb2fb3b, (q31_t)0x6baf95d9, (q31_t)0x6bac3034, (q31_t)0x6ba8ca4e, (q31_t)0x6ba56425, (q31_t)0x6ba1fdb9, (q31_t)0x6b9e970b, + (q31_t)0x6b9b301b, (q31_t)0x6b97c8e8, (q31_t)0x6b946173, (q31_t)0x6b90f9bc, (q31_t)0x6b8d91c2, (q31_t)0x6b8a2986, (q31_t)0x6b86c107, (q31_t)0x6b835846, + (q31_t)0x6b7fef43, (q31_t)0x6b7c85fe, (q31_t)0x6b791c76, (q31_t)0x6b75b2ac, (q31_t)0x6b7248a0, (q31_t)0x6b6ede51, (q31_t)0x6b6b73c0, (q31_t)0x6b6808ed, + (q31_t)0x6b649dd8, (q31_t)0x6b613280, (q31_t)0x6b5dc6e6, (q31_t)0x6b5a5b0a, (q31_t)0x6b56eeec, (q31_t)0x6b53828b, (q31_t)0x6b5015e9, (q31_t)0x6b4ca904, + (q31_t)0x6b493bdd, (q31_t)0x6b45ce73, (q31_t)0x6b4260c8, (q31_t)0x6b3ef2da, (q31_t)0x6b3b84ab, (q31_t)0x6b381639, (q31_t)0x6b34a785, (q31_t)0x6b31388e, + (q31_t)0x6b2dc956, (q31_t)0x6b2a59dc, (q31_t)0x6b26ea1f, (q31_t)0x6b237a21, (q31_t)0x6b2009e0, (q31_t)0x6b1c995d, (q31_t)0x6b192898, (q31_t)0x6b15b791, + (q31_t)0x6b124648, (q31_t)0x6b0ed4bd, (q31_t)0x6b0b62f0, (q31_t)0x6b07f0e1, (q31_t)0x6b047e90, (q31_t)0x6b010bfd, (q31_t)0x6afd9928, (q31_t)0x6afa2610, + (q31_t)0x6af6b2b7, (q31_t)0x6af33f1c, (q31_t)0x6aefcb3f, (q31_t)0x6aec5720, (q31_t)0x6ae8e2bf, (q31_t)0x6ae56e1c, (q31_t)0x6ae1f937, (q31_t)0x6ade8410, + (q31_t)0x6adb0ea8, (q31_t)0x6ad798fd, (q31_t)0x6ad42311, (q31_t)0x6ad0ace2, (q31_t)0x6acd3672, (q31_t)0x6ac9bfc0, (q31_t)0x6ac648cb, (q31_t)0x6ac2d195, + (q31_t)0x6abf5a1e, (q31_t)0x6abbe264, (q31_t)0x6ab86a68, (q31_t)0x6ab4f22b, (q31_t)0x6ab179ac, (q31_t)0x6aae00eb, (q31_t)0x6aaa87e8, (q31_t)0x6aa70ea4, + (q31_t)0x6aa3951d, (q31_t)0x6aa01b55, (q31_t)0x6a9ca14b, (q31_t)0x6a992700, (q31_t)0x6a95ac72, (q31_t)0x6a9231a3, (q31_t)0x6a8eb692, (q31_t)0x6a8b3b3f, + (q31_t)0x6a87bfab, (q31_t)0x6a8443d5, (q31_t)0x6a80c7bd, (q31_t)0x6a7d4b64, (q31_t)0x6a79cec8, (q31_t)0x6a7651ec, (q31_t)0x6a72d4cd, (q31_t)0x6a6f576d, + (q31_t)0x6a6bd9cb, (q31_t)0x6a685be8, (q31_t)0x6a64ddc2, (q31_t)0x6a615f5c, (q31_t)0x6a5de0b3, (q31_t)0x6a5a61c9, (q31_t)0x6a56e29e, (q31_t)0x6a536331, + (q31_t)0x6a4fe382, (q31_t)0x6a4c6391, (q31_t)0x6a48e360, (q31_t)0x6a4562ec, (q31_t)0x6a41e237, (q31_t)0x6a3e6140, (q31_t)0x6a3ae008, (q31_t)0x6a375e8f, + (q31_t)0x6a33dcd4, (q31_t)0x6a305ad7, (q31_t)0x6a2cd899, (q31_t)0x6a295619, (q31_t)0x6a25d358, (q31_t)0x6a225055, (q31_t)0x6a1ecd11, (q31_t)0x6a1b498c, + (q31_t)0x6a17c5c5, (q31_t)0x6a1441bc, (q31_t)0x6a10bd72, (q31_t)0x6a0d38e7, (q31_t)0x6a09b41a, (q31_t)0x6a062f0c, (q31_t)0x6a02a9bc, (q31_t)0x69ff242b, + (q31_t)0x69fb9e59, (q31_t)0x69f81845, (q31_t)0x69f491f0, (q31_t)0x69f10b5a, (q31_t)0x69ed8482, (q31_t)0x69e9fd69, (q31_t)0x69e6760f, (q31_t)0x69e2ee73, + (q31_t)0x69df6696, (q31_t)0x69dbde77, (q31_t)0x69d85618, (q31_t)0x69d4cd77, (q31_t)0x69d14494, (q31_t)0x69cdbb71, (q31_t)0x69ca320c, (q31_t)0x69c6a866, + (q31_t)0x69c31e7f, (q31_t)0x69bf9456, (q31_t)0x69bc09ec, (q31_t)0x69b87f41, (q31_t)0x69b4f455, (q31_t)0x69b16928, (q31_t)0x69adddb9, (q31_t)0x69aa5209, + (q31_t)0x69a6c618, (q31_t)0x69a339e6, (q31_t)0x699fad73, (q31_t)0x699c20be, (q31_t)0x699893c9, (q31_t)0x69950692, (q31_t)0x6991791a, (q31_t)0x698deb61, + (q31_t)0x698a5d67, (q31_t)0x6986cf2c, (q31_t)0x698340af, (q31_t)0x697fb1f2, (q31_t)0x697c22f3, (q31_t)0x697893b4, (q31_t)0x69750433, (q31_t)0x69717472, + (q31_t)0x696de46f, (q31_t)0x696a542b, (q31_t)0x6966c3a6, (q31_t)0x696332e1, (q31_t)0x695fa1da, (q31_t)0x695c1092, (q31_t)0x69587f09, (q31_t)0x6954ed40, + (q31_t)0x69515b35, (q31_t)0x694dc8e9, (q31_t)0x694a365c, (q31_t)0x6946a38f, (q31_t)0x69431080, (q31_t)0x693f7d31, (q31_t)0x693be9a0, (q31_t)0x693855cf, + (q31_t)0x6934c1bd, (q31_t)0x69312d6a, (q31_t)0x692d98d6, (q31_t)0x692a0401, (q31_t)0x69266eeb, (q31_t)0x6922d995, (q31_t)0x691f43fd, (q31_t)0x691bae25, + (q31_t)0x6918180c, (q31_t)0x691481b2, (q31_t)0x6910eb17, (q31_t)0x690d543b, (q31_t)0x6909bd1f, (q31_t)0x690625c2, (q31_t)0x69028e24, (q31_t)0x68fef645, + (q31_t)0x68fb5e25, (q31_t)0x68f7c5c5, (q31_t)0x68f42d24, (q31_t)0x68f09442, (q31_t)0x68ecfb20, (q31_t)0x68e961bd, (q31_t)0x68e5c819, (q31_t)0x68e22e34, + (q31_t)0x68de940f, (q31_t)0x68daf9a9, (q31_t)0x68d75f02, (q31_t)0x68d3c41b, (q31_t)0x68d028f2, (q31_t)0x68cc8d8a, (q31_t)0x68c8f1e0, (q31_t)0x68c555f6, + (q31_t)0x68c1b9cc, (q31_t)0x68be1d61, (q31_t)0x68ba80b5, (q31_t)0x68b6e3c8, (q31_t)0x68b3469b, (q31_t)0x68afa92e, (q31_t)0x68ac0b7f, (q31_t)0x68a86d91, + (q31_t)0x68a4cf61, (q31_t)0x68a130f1, (q31_t)0x689d9241, (q31_t)0x6899f350, (q31_t)0x6896541f, (q31_t)0x6892b4ad, (q31_t)0x688f14fa, (q31_t)0x688b7507, + (q31_t)0x6887d4d4, (q31_t)0x68843460, (q31_t)0x688093ab, (q31_t)0x687cf2b6, (q31_t)0x68795181, (q31_t)0x6875b00b, (q31_t)0x68720e55, (q31_t)0x686e6c5e, + (q31_t)0x686aca27, (q31_t)0x686727b0, (q31_t)0x686384f8, (q31_t)0x685fe200, (q31_t)0x685c3ec7, (q31_t)0x68589b4e, (q31_t)0x6854f795, (q31_t)0x6851539b, + (q31_t)0x684daf61, (q31_t)0x684a0ae6, (q31_t)0x6846662c, (q31_t)0x6842c131, (q31_t)0x683f1bf5, (q31_t)0x683b7679, (q31_t)0x6837d0bd, (q31_t)0x68342ac1, + (q31_t)0x68308485, (q31_t)0x682cde08, (q31_t)0x6829374b, (q31_t)0x6825904d, (q31_t)0x6821e910, (q31_t)0x681e4192, (q31_t)0x681a99d4, (q31_t)0x6816f1d6, + (q31_t)0x68134997, (q31_t)0x680fa118, (q31_t)0x680bf85a, (q31_t)0x68084f5a, (q31_t)0x6804a61b, (q31_t)0x6800fc9c, (q31_t)0x67fd52dc, (q31_t)0x67f9a8dd, + (q31_t)0x67f5fe9d, (q31_t)0x67f2541d, (q31_t)0x67eea95d, (q31_t)0x67eafe5d, (q31_t)0x67e7531c, (q31_t)0x67e3a79c, (q31_t)0x67dffbdc, (q31_t)0x67dc4fdb, + (q31_t)0x67d8a39a, (q31_t)0x67d4f71a, (q31_t)0x67d14a59, (q31_t)0x67cd9d58, (q31_t)0x67c9f017, (q31_t)0x67c64297, (q31_t)0x67c294d6, (q31_t)0x67bee6d5, + (q31_t)0x67bb3894, (q31_t)0x67b78a13, (q31_t)0x67b3db53, (q31_t)0x67b02c52, (q31_t)0x67ac7d11, (q31_t)0x67a8cd91, (q31_t)0x67a51dd0, (q31_t)0x67a16dcf, + (q31_t)0x679dbd8f, (q31_t)0x679a0d0f, (q31_t)0x67965c4e, (q31_t)0x6792ab4e, (q31_t)0x678efa0e, (q31_t)0x678b488e, (q31_t)0x678796ce, (q31_t)0x6783e4cf, + (q31_t)0x6780328f, (q31_t)0x677c8010, (q31_t)0x6778cd50, (q31_t)0x67751a51, (q31_t)0x67716713, (q31_t)0x676db394, (q31_t)0x6769ffd5, (q31_t)0x67664bd7, + (q31_t)0x67629799, (q31_t)0x675ee31b, (q31_t)0x675b2e5e, (q31_t)0x67577960, (q31_t)0x6753c423, (q31_t)0x67500ea7, (q31_t)0x674c58ea, (q31_t)0x6748a2ee, + (q31_t)0x6744ecb2, (q31_t)0x67413636, (q31_t)0x673d7f7b, (q31_t)0x6739c880, (q31_t)0x67361145, (q31_t)0x673259ca, (q31_t)0x672ea210, (q31_t)0x672aea17, + (q31_t)0x672731dd, (q31_t)0x67237964, (q31_t)0x671fc0ac, (q31_t)0x671c07b4, (q31_t)0x67184e7c, (q31_t)0x67149504, (q31_t)0x6710db4d, (q31_t)0x670d2157, + (q31_t)0x67096721, (q31_t)0x6705acab, (q31_t)0x6701f1f6, (q31_t)0x66fe3701, (q31_t)0x66fa7bcd, (q31_t)0x66f6c059, (q31_t)0x66f304a6, (q31_t)0x66ef48b3, + (q31_t)0x66eb8c80, (q31_t)0x66e7d00f, (q31_t)0x66e4135d, (q31_t)0x66e0566c, (q31_t)0x66dc993c, (q31_t)0x66d8dbcd, (q31_t)0x66d51e1d, (q31_t)0x66d1602f, + (q31_t)0x66cda201, (q31_t)0x66c9e393, (q31_t)0x66c624e7, (q31_t)0x66c265fa, (q31_t)0x66bea6cf, (q31_t)0x66bae764, (q31_t)0x66b727ba, (q31_t)0x66b367d0, + (q31_t)0x66afa7a7, (q31_t)0x66abe73f, (q31_t)0x66a82697, (q31_t)0x66a465b0, (q31_t)0x66a0a489, (q31_t)0x669ce324, (q31_t)0x6699217f, (q31_t)0x66955f9b, + (q31_t)0x66919d77, (q31_t)0x668ddb14, (q31_t)0x668a1872, (q31_t)0x66865591, (q31_t)0x66829270, (q31_t)0x667ecf11, (q31_t)0x667b0b72, (q31_t)0x66774793, + (q31_t)0x66738376, (q31_t)0x666fbf19, (q31_t)0x666bfa7d, (q31_t)0x666835a2, (q31_t)0x66647088, (q31_t)0x6660ab2f, (q31_t)0x665ce596, (q31_t)0x66591fbf, + (q31_t)0x665559a8, (q31_t)0x66519352, (q31_t)0x664dccbd, (q31_t)0x664a05e9, (q31_t)0x66463ed6, (q31_t)0x66427784, (q31_t)0x663eaff2, (q31_t)0x663ae822, + (q31_t)0x66372012, (q31_t)0x663357c4, (q31_t)0x662f8f36, (q31_t)0x662bc66a, (q31_t)0x6627fd5e, (q31_t)0x66243413, (q31_t)0x66206a8a, (q31_t)0x661ca0c1, + (q31_t)0x6618d6b9, (q31_t)0x66150c73, (q31_t)0x661141ed, (q31_t)0x660d7729, (q31_t)0x6609ac25, (q31_t)0x6605e0e3, (q31_t)0x66021561, (q31_t)0x65fe49a1, + (q31_t)0x65fa7da2, (q31_t)0x65f6b164, (q31_t)0x65f2e4e7, (q31_t)0x65ef182b, (q31_t)0x65eb4b30, (q31_t)0x65e77df6, (q31_t)0x65e3b07e, (q31_t)0x65dfe2c6, + (q31_t)0x65dc14d0, (q31_t)0x65d8469b, (q31_t)0x65d47827, (q31_t)0x65d0a975, (q31_t)0x65ccda83, (q31_t)0x65c90b53, (q31_t)0x65c53be4, (q31_t)0x65c16c36, + (q31_t)0x65bd9c49, (q31_t)0x65b9cc1e, (q31_t)0x65b5fbb4, (q31_t)0x65b22b0b, (q31_t)0x65ae5a23, (q31_t)0x65aa88fd, (q31_t)0x65a6b798, (q31_t)0x65a2e5f4, + (q31_t)0x659f1412, (q31_t)0x659b41f1, (q31_t)0x65976f91, (q31_t)0x65939cf3, (q31_t)0x658fca15, (q31_t)0x658bf6fa, (q31_t)0x6588239f, (q31_t)0x65845006, + (q31_t)0x65807c2f, (q31_t)0x657ca818, (q31_t)0x6578d3c4, (q31_t)0x6574ff30, (q31_t)0x65712a5e, (q31_t)0x656d554d, (q31_t)0x65697ffe, (q31_t)0x6565aa71, + (q31_t)0x6561d4a4, (q31_t)0x655dfe99, (q31_t)0x655a2850, (q31_t)0x655651c8, (q31_t)0x65527b02, (q31_t)0x654ea3fd, (q31_t)0x654accba, (q31_t)0x6546f538, + (q31_t)0x65431d77, (q31_t)0x653f4579, (q31_t)0x653b6d3b, (q31_t)0x653794c0, (q31_t)0x6533bc06, (q31_t)0x652fe30d, (q31_t)0x652c09d6, (q31_t)0x65283061, + (q31_t)0x652456ad, (q31_t)0x65207cbb, (q31_t)0x651ca28a, (q31_t)0x6518c81b, (q31_t)0x6514ed6e, (q31_t)0x65111283, (q31_t)0x650d3759, (q31_t)0x65095bf0, + (q31_t)0x6505804a, (q31_t)0x6501a465, (q31_t)0x64fdc841, (q31_t)0x64f9ebe0, (q31_t)0x64f60f40, (q31_t)0x64f23262, (q31_t)0x64ee5546, (q31_t)0x64ea77eb, + (q31_t)0x64e69a52, (q31_t)0x64e2bc7b, (q31_t)0x64dede66, (q31_t)0x64db0012, (q31_t)0x64d72180, (q31_t)0x64d342b0, (q31_t)0x64cf63a2, (q31_t)0x64cb8456, + (q31_t)0x64c7a4cb, (q31_t)0x64c3c502, (q31_t)0x64bfe4fc, (q31_t)0x64bc04b6, (q31_t)0x64b82433, (q31_t)0x64b44372, (q31_t)0x64b06273, (q31_t)0x64ac8135, + (q31_t)0x64a89fba, (q31_t)0x64a4be00, (q31_t)0x64a0dc08, (q31_t)0x649cf9d2, (q31_t)0x6499175e, (q31_t)0x649534ac, (q31_t)0x649151bc, (q31_t)0x648d6e8e, + (q31_t)0x64898b22, (q31_t)0x6485a778, (q31_t)0x6481c390, (q31_t)0x647ddf6a, (q31_t)0x6479fb06, (q31_t)0x64761664, (q31_t)0x64723184, (q31_t)0x646e4c66, + (q31_t)0x646a670a, (q31_t)0x64668170, (q31_t)0x64629b98, (q31_t)0x645eb582, (q31_t)0x645acf2e, (q31_t)0x6456e89d, (q31_t)0x645301cd, (q31_t)0x644f1ac0, + (q31_t)0x644b3375, (q31_t)0x64474bec, (q31_t)0x64436425, (q31_t)0x643f7c20, (q31_t)0x643b93dd, (q31_t)0x6437ab5d, (q31_t)0x6433c29f, (q31_t)0x642fd9a3, + (q31_t)0x642bf069, (q31_t)0x642806f1, (q31_t)0x64241d3c, (q31_t)0x64203348, (q31_t)0x641c4917, (q31_t)0x64185ea9, (q31_t)0x641473fc, (q31_t)0x64108912, + (q31_t)0x640c9dea, (q31_t)0x6408b284, (q31_t)0x6404c6e1, (q31_t)0x6400db00, (q31_t)0x63fceee1, (q31_t)0x63f90285, (q31_t)0x63f515eb, (q31_t)0x63f12913, + (q31_t)0x63ed3bfd, (q31_t)0x63e94eaa, (q31_t)0x63e5611a, (q31_t)0x63e1734b, (q31_t)0x63dd853f, (q31_t)0x63d996f6, (q31_t)0x63d5a86f, (q31_t)0x63d1b9aa, + (q31_t)0x63cdcaa8, (q31_t)0x63c9db68, (q31_t)0x63c5ebeb, (q31_t)0x63c1fc30, (q31_t)0x63be0c37, (q31_t)0x63ba1c01, (q31_t)0x63b62b8e, (q31_t)0x63b23add, + (q31_t)0x63ae49ee, (q31_t)0x63aa58c2, (q31_t)0x63a66759, (q31_t)0x63a275b2, (q31_t)0x639e83cd, (q31_t)0x639a91ac, (q31_t)0x63969f4c, (q31_t)0x6392acaf, + (q31_t)0x638eb9d5, (q31_t)0x638ac6be, (q31_t)0x6386d369, (q31_t)0x6382dfd6, (q31_t)0x637eec07, (q31_t)0x637af7fa, (q31_t)0x637703af, (q31_t)0x63730f27, + (q31_t)0x636f1a62, (q31_t)0x636b2560, (q31_t)0x63673020, (q31_t)0x63633aa3, (q31_t)0x635f44e8, (q31_t)0x635b4ef0, (q31_t)0x635758bb, (q31_t)0x63536249, + (q31_t)0x634f6b99, (q31_t)0x634b74ad, (q31_t)0x63477d82, (q31_t)0x6343861b, (q31_t)0x633f8e76, (q31_t)0x633b9695, (q31_t)0x63379e76, (q31_t)0x6333a619, + (q31_t)0x632fad80, (q31_t)0x632bb4a9, (q31_t)0x6327bb96, (q31_t)0x6323c245, (q31_t)0x631fc8b7, (q31_t)0x631bceeb, (q31_t)0x6317d4e3, (q31_t)0x6313da9e, + (q31_t)0x630fe01b, (q31_t)0x630be55b, (q31_t)0x6307ea5e, (q31_t)0x6303ef25, (q31_t)0x62fff3ae, (q31_t)0x62fbf7fa, (q31_t)0x62f7fc08, (q31_t)0x62f3ffda, + (q31_t)0x62f0036f, (q31_t)0x62ec06c7, (q31_t)0x62e809e2, (q31_t)0x62e40cbf, (q31_t)0x62e00f60, (q31_t)0x62dc11c4, (q31_t)0x62d813eb, (q31_t)0x62d415d4, + (q31_t)0x62d01781, (q31_t)0x62cc18f1, (q31_t)0x62c81a24, (q31_t)0x62c41b1a, (q31_t)0x62c01bd3, (q31_t)0x62bc1c4f, (q31_t)0x62b81c8f, (q31_t)0x62b41c91, + (q31_t)0x62b01c57, (q31_t)0x62ac1bdf, (q31_t)0x62a81b2b, (q31_t)0x62a41a3a, (q31_t)0x62a0190c, (q31_t)0x629c17a1, (q31_t)0x629815fa, (q31_t)0x62941415, + (q31_t)0x629011f4, (q31_t)0x628c0f96, (q31_t)0x62880cfb, (q31_t)0x62840a23, (q31_t)0x6280070f, (q31_t)0x627c03be, (q31_t)0x62780030, (q31_t)0x6273fc65, + (q31_t)0x626ff85e, (q31_t)0x626bf41a, (q31_t)0x6267ef99, (q31_t)0x6263eadc, (q31_t)0x625fe5e1, (q31_t)0x625be0ab, (q31_t)0x6257db37, (q31_t)0x6253d587, + (q31_t)0x624fcf9a, (q31_t)0x624bc970, (q31_t)0x6247c30a, (q31_t)0x6243bc68, (q31_t)0x623fb588, (q31_t)0x623bae6c, (q31_t)0x6237a714, (q31_t)0x62339f7e, + (q31_t)0x622f97ad, (q31_t)0x622b8f9e, (q31_t)0x62278754, (q31_t)0x62237ecc, (q31_t)0x621f7608, (q31_t)0x621b6d08, (q31_t)0x621763cb, (q31_t)0x62135a51, + (q31_t)0x620f509b, (q31_t)0x620b46a9, (q31_t)0x62073c7a, (q31_t)0x6203320e, (q31_t)0x61ff2766, (q31_t)0x61fb1c82, (q31_t)0x61f71161, (q31_t)0x61f30604, + (q31_t)0x61eefa6b, (q31_t)0x61eaee95, (q31_t)0x61e6e282, (q31_t)0x61e2d633, (q31_t)0x61dec9a8, (q31_t)0x61dabce0, (q31_t)0x61d6afdd, (q31_t)0x61d2a29c, + (q31_t)0x61ce9520, (q31_t)0x61ca8767, (q31_t)0x61c67971, (q31_t)0x61c26b40, (q31_t)0x61be5cd2, (q31_t)0x61ba4e28, (q31_t)0x61b63f41, (q31_t)0x61b2301e, + (q31_t)0x61ae20bf, (q31_t)0x61aa1124, (q31_t)0x61a6014d, (q31_t)0x61a1f139, (q31_t)0x619de0e9, (q31_t)0x6199d05d, (q31_t)0x6195bf94, (q31_t)0x6191ae90, + (q31_t)0x618d9d4f, (q31_t)0x61898bd2, (q31_t)0x61857a19, (q31_t)0x61816824, (q31_t)0x617d55f2, (q31_t)0x61794385, (q31_t)0x617530db, (q31_t)0x61711df5, + (q31_t)0x616d0ad3, (q31_t)0x6168f775, (q31_t)0x6164e3db, (q31_t)0x6160d005, (q31_t)0x615cbbf3, (q31_t)0x6158a7a4, (q31_t)0x6154931a, (q31_t)0x61507e54, + (q31_t)0x614c6951, (q31_t)0x61485413, (q31_t)0x61443e98, (q31_t)0x614028e2, (q31_t)0x613c12f0, (q31_t)0x6137fcc1, (q31_t)0x6133e657, (q31_t)0x612fcfb0, + (q31_t)0x612bb8ce, (q31_t)0x6127a1b0, (q31_t)0x61238a56, (q31_t)0x611f72c0, (q31_t)0x611b5aee, (q31_t)0x611742e0, (q31_t)0x61132a96, (q31_t)0x610f1210, + (q31_t)0x610af94f, (q31_t)0x6106e051, (q31_t)0x6102c718, (q31_t)0x60feada3, (q31_t)0x60fa93f2, (q31_t)0x60f67a05, (q31_t)0x60f25fdd, (q31_t)0x60ee4579, + (q31_t)0x60ea2ad8, (q31_t)0x60e60ffd, (q31_t)0x60e1f4e5, (q31_t)0x60ddd991, (q31_t)0x60d9be02, (q31_t)0x60d5a237, (q31_t)0x60d18631, (q31_t)0x60cd69ee, + (q31_t)0x60c94d70, (q31_t)0x60c530b6, (q31_t)0x60c113c1, (q31_t)0x60bcf690, (q31_t)0x60b8d923, (q31_t)0x60b4bb7a, (q31_t)0x60b09d96, (q31_t)0x60ac7f76, + (q31_t)0x60a8611b, (q31_t)0x60a44284, (q31_t)0x60a023b1, (q31_t)0x609c04a3, (q31_t)0x6097e559, (q31_t)0x6093c5d3, (q31_t)0x608fa612, (q31_t)0x608b8616, + (q31_t)0x608765dd, (q31_t)0x6083456a, (q31_t)0x607f24ba, (q31_t)0x607b03d0, (q31_t)0x6076e2a9, (q31_t)0x6072c148, (q31_t)0x606e9faa, (q31_t)0x606a7dd2, + (q31_t)0x60665bbd, (q31_t)0x6062396e, (q31_t)0x605e16e2, (q31_t)0x6059f41c, (q31_t)0x6055d11a, (q31_t)0x6051addc, (q31_t)0x604d8a63, (q31_t)0x604966af, + (q31_t)0x604542bf, (q31_t)0x60411e94, (q31_t)0x603cfa2e, (q31_t)0x6038d58c, (q31_t)0x6034b0af, (q31_t)0x60308b97, (q31_t)0x602c6643, (q31_t)0x602840b4, + (q31_t)0x60241ae9, (q31_t)0x601ff4e3, (q31_t)0x601bcea2, (q31_t)0x6017a826, (q31_t)0x6013816e, (q31_t)0x600f5a7b, (q31_t)0x600b334d, (q31_t)0x60070be4, + (q31_t)0x6002e43f, (q31_t)0x5ffebc5f, (q31_t)0x5ffa9444, (q31_t)0x5ff66bee, (q31_t)0x5ff2435d, (q31_t)0x5fee1a90, (q31_t)0x5fe9f188, (q31_t)0x5fe5c845, + (q31_t)0x5fe19ec7, (q31_t)0x5fdd750e, (q31_t)0x5fd94b19, (q31_t)0x5fd520ea, (q31_t)0x5fd0f67f, (q31_t)0x5fcccbd9, (q31_t)0x5fc8a0f8, (q31_t)0x5fc475dc, + (q31_t)0x5fc04a85, (q31_t)0x5fbc1ef3, (q31_t)0x5fb7f326, (q31_t)0x5fb3c71e, (q31_t)0x5faf9adb, (q31_t)0x5fab6e5d, (q31_t)0x5fa741a3, (q31_t)0x5fa314af, + (q31_t)0x5f9ee780, (q31_t)0x5f9aba16, (q31_t)0x5f968c70, (q31_t)0x5f925e90, (q31_t)0x5f8e3075, (q31_t)0x5f8a021f, (q31_t)0x5f85d38e, (q31_t)0x5f81a4c2, + (q31_t)0x5f7d75bb, (q31_t)0x5f794679, (q31_t)0x5f7516fd, (q31_t)0x5f70e745, (q31_t)0x5f6cb753, (q31_t)0x5f688726, (q31_t)0x5f6456be, (q31_t)0x5f60261b, + (q31_t)0x5f5bf53d, (q31_t)0x5f57c424, (q31_t)0x5f5392d1, (q31_t)0x5f4f6143, (q31_t)0x5f4b2f7a, (q31_t)0x5f46fd76, (q31_t)0x5f42cb37, (q31_t)0x5f3e98be, + (q31_t)0x5f3a660a, (q31_t)0x5f36331b, (q31_t)0x5f31fff1, (q31_t)0x5f2dcc8d, (q31_t)0x5f2998ee, (q31_t)0x5f256515, (q31_t)0x5f213100, (q31_t)0x5f1cfcb1, + (q31_t)0x5f18c827, (q31_t)0x5f149363, (q31_t)0x5f105e64, (q31_t)0x5f0c292a, (q31_t)0x5f07f3b6, (q31_t)0x5f03be07, (q31_t)0x5eff881d, (q31_t)0x5efb51f9, + (q31_t)0x5ef71b9b, (q31_t)0x5ef2e501, (q31_t)0x5eeeae2d, (q31_t)0x5eea771f, (q31_t)0x5ee63fd6, (q31_t)0x5ee20853, (q31_t)0x5eddd094, (q31_t)0x5ed9989c, + (q31_t)0x5ed56069, (q31_t)0x5ed127fb, (q31_t)0x5eccef53, (q31_t)0x5ec8b671, (q31_t)0x5ec47d54, (q31_t)0x5ec043fc, (q31_t)0x5ebc0a6a, (q31_t)0x5eb7d09e, + (q31_t)0x5eb39697, (q31_t)0x5eaf5c56, (q31_t)0x5eab21da, (q31_t)0x5ea6e724, (q31_t)0x5ea2ac34, (q31_t)0x5e9e7109, (q31_t)0x5e9a35a4, (q31_t)0x5e95fa05, + (q31_t)0x5e91be2b, (q31_t)0x5e8d8217, (q31_t)0x5e8945c8, (q31_t)0x5e85093f, (q31_t)0x5e80cc7c, (q31_t)0x5e7c8f7f, (q31_t)0x5e785247, (q31_t)0x5e7414d5, + (q31_t)0x5e6fd729, (q31_t)0x5e6b9943, (q31_t)0x5e675b22, (q31_t)0x5e631cc7, (q31_t)0x5e5ede32, (q31_t)0x5e5a9f62, (q31_t)0x5e566059, (q31_t)0x5e522115, + (q31_t)0x5e4de197, (q31_t)0x5e49a1df, (q31_t)0x5e4561ed, (q31_t)0x5e4121c0, (q31_t)0x5e3ce15a, (q31_t)0x5e38a0b9, (q31_t)0x5e345fde, (q31_t)0x5e301ec9, + (q31_t)0x5e2bdd7a, (q31_t)0x5e279bf1, (q31_t)0x5e235a2e, (q31_t)0x5e1f1830, (q31_t)0x5e1ad5f9, (q31_t)0x5e169388, (q31_t)0x5e1250dc, (q31_t)0x5e0e0df7, + (q31_t)0x5e09cad7, (q31_t)0x5e05877e, (q31_t)0x5e0143ea, (q31_t)0x5dfd001d, (q31_t)0x5df8bc15, (q31_t)0x5df477d4, (q31_t)0x5df03359, (q31_t)0x5debeea3, + (q31_t)0x5de7a9b4, (q31_t)0x5de3648b, (q31_t)0x5ddf1f28, (q31_t)0x5ddad98b, (q31_t)0x5dd693b4, (q31_t)0x5dd24da3, (q31_t)0x5dce0759, (q31_t)0x5dc9c0d4, + (q31_t)0x5dc57a16, (q31_t)0x5dc1331d, (q31_t)0x5dbcebeb, (q31_t)0x5db8a480, (q31_t)0x5db45cda, (q31_t)0x5db014fa, (q31_t)0x5dabcce1, (q31_t)0x5da7848e, + (q31_t)0x5da33c01, (q31_t)0x5d9ef33b, (q31_t)0x5d9aaa3a, (q31_t)0x5d966100, (q31_t)0x5d92178d, (q31_t)0x5d8dcddf, (q31_t)0x5d8983f8, (q31_t)0x5d8539d7, + (q31_t)0x5d80ef7c, (q31_t)0x5d7ca4e8, (q31_t)0x5d785a1a, (q31_t)0x5d740f12, (q31_t)0x5d6fc3d1, (q31_t)0x5d6b7856, (q31_t)0x5d672ca2, (q31_t)0x5d62e0b4, + (q31_t)0x5d5e948c, (q31_t)0x5d5a482a, (q31_t)0x5d55fb90, (q31_t)0x5d51aebb, (q31_t)0x5d4d61ad, (q31_t)0x5d491465, (q31_t)0x5d44c6e4, (q31_t)0x5d40792a, + (q31_t)0x5d3c2b35, (q31_t)0x5d37dd08, (q31_t)0x5d338ea0, (q31_t)0x5d2f4000, (q31_t)0x5d2af125, (q31_t)0x5d26a212, (q31_t)0x5d2252c5, (q31_t)0x5d1e033e, + (q31_t)0x5d19b37e, (q31_t)0x5d156385, (q31_t)0x5d111352, (q31_t)0x5d0cc2e5, (q31_t)0x5d087240, (q31_t)0x5d042161, (q31_t)0x5cffd048, (q31_t)0x5cfb7ef7, + (q31_t)0x5cf72d6b, (q31_t)0x5cf2dba7, (q31_t)0x5cee89a9, (q31_t)0x5cea3772, (q31_t)0x5ce5e501, (q31_t)0x5ce19258, (q31_t)0x5cdd3f75, (q31_t)0x5cd8ec58, + (q31_t)0x5cd49903, (q31_t)0x5cd04574, (q31_t)0x5ccbf1ab, (q31_t)0x5cc79daa, (q31_t)0x5cc3496f, (q31_t)0x5cbef4fc, (q31_t)0x5cbaa04f, (q31_t)0x5cb64b68, + (q31_t)0x5cb1f649, (q31_t)0x5cada0f0, (q31_t)0x5ca94b5e, (q31_t)0x5ca4f594, (q31_t)0x5ca09f8f, (q31_t)0x5c9c4952, (q31_t)0x5c97f2dc, (q31_t)0x5c939c2c, + (q31_t)0x5c8f4544, (q31_t)0x5c8aee22, (q31_t)0x5c8696c7, (q31_t)0x5c823f34, (q31_t)0x5c7de767, (q31_t)0x5c798f61, (q31_t)0x5c753722, (q31_t)0x5c70deaa, + (q31_t)0x5c6c85f9, (q31_t)0x5c682d0f, (q31_t)0x5c63d3eb, (q31_t)0x5c5f7a8f, (q31_t)0x5c5b20fa, (q31_t)0x5c56c72c, (q31_t)0x5c526d25, (q31_t)0x5c4e12e5, + (q31_t)0x5c49b86d, (q31_t)0x5c455dbb, (q31_t)0x5c4102d0, (q31_t)0x5c3ca7ad, (q31_t)0x5c384c50, (q31_t)0x5c33f0bb, (q31_t)0x5c2f94ec, (q31_t)0x5c2b38e5, + (q31_t)0x5c26dca5, (q31_t)0x5c22802c, (q31_t)0x5c1e237b, (q31_t)0x5c19c690, (q31_t)0x5c15696d, (q31_t)0x5c110c11, (q31_t)0x5c0cae7c, (q31_t)0x5c0850ae, + (q31_t)0x5c03f2a8, (q31_t)0x5bff9469, (q31_t)0x5bfb35f1, (q31_t)0x5bf6d740, (q31_t)0x5bf27857, (q31_t)0x5bee1935, (q31_t)0x5be9b9da, (q31_t)0x5be55a46, + (q31_t)0x5be0fa7a, (q31_t)0x5bdc9a75, (q31_t)0x5bd83a37, (q31_t)0x5bd3d9c1, (q31_t)0x5bcf7912, (q31_t)0x5bcb182b, (q31_t)0x5bc6b70b, (q31_t)0x5bc255b2, + (q31_t)0x5bbdf421, (q31_t)0x5bb99257, (q31_t)0x5bb53054, (q31_t)0x5bb0ce19, (q31_t)0x5bac6ba6, (q31_t)0x5ba808f9, (q31_t)0x5ba3a615, (q31_t)0x5b9f42f7, + (q31_t)0x5b9adfa2, (q31_t)0x5b967c13, (q31_t)0x5b92184d, (q31_t)0x5b8db44d, (q31_t)0x5b895016, (q31_t)0x5b84eba6, (q31_t)0x5b8086fd, (q31_t)0x5b7c221c, + (q31_t)0x5b77bd02, (q31_t)0x5b7357b0, (q31_t)0x5b6ef226, (q31_t)0x5b6a8c63, (q31_t)0x5b662668, (q31_t)0x5b61c035, (q31_t)0x5b5d59c9, (q31_t)0x5b58f324, + (q31_t)0x5b548c48, (q31_t)0x5b502533, (q31_t)0x5b4bbde6, (q31_t)0x5b475660, (q31_t)0x5b42eea2, (q31_t)0x5b3e86ac, (q31_t)0x5b3a1e7e, (q31_t)0x5b35b617, + (q31_t)0x5b314d78, (q31_t)0x5b2ce4a1, (q31_t)0x5b287b91, (q31_t)0x5b241249, (q31_t)0x5b1fa8c9, (q31_t)0x5b1b3f11, (q31_t)0x5b16d521, (q31_t)0x5b126af8, + (q31_t)0x5b0e0098, (q31_t)0x5b0995ff, (q31_t)0x5b052b2e, (q31_t)0x5b00c025, (q31_t)0x5afc54e3, (q31_t)0x5af7e96a, (q31_t)0x5af37db8, (q31_t)0x5aef11cf, + (q31_t)0x5aeaa5ad, (q31_t)0x5ae63953, (q31_t)0x5ae1ccc1, (q31_t)0x5add5ff7, (q31_t)0x5ad8f2f5, (q31_t)0x5ad485bb, (q31_t)0x5ad01849, (q31_t)0x5acbaa9f, + (q31_t)0x5ac73cbd, (q31_t)0x5ac2cea3, (q31_t)0x5abe6050, (q31_t)0x5ab9f1c6, (q31_t)0x5ab58304, (q31_t)0x5ab1140a, (q31_t)0x5aaca4d8, (q31_t)0x5aa8356f, + (q31_t)0x5aa3c5cd, (q31_t)0x5a9f55f3, (q31_t)0x5a9ae5e2, (q31_t)0x5a967598, (q31_t)0x5a920517, (q31_t)0x5a8d945d, (q31_t)0x5a89236c, (q31_t)0x5a84b243, + (q31_t)0x5a8040e3, (q31_t)0x5a7bcf4a, (q31_t)0x5a775d7a, (q31_t)0x5a72eb71, (q31_t)0x5a6e7931, (q31_t)0x5a6a06ba, (q31_t)0x5a65940a, (q31_t)0x5a612123, + (q31_t)0x5a5cae04, (q31_t)0x5a583aad, (q31_t)0x5a53c71e, (q31_t)0x5a4f5358, (q31_t)0x5a4adf5a, (q31_t)0x5a466b24, (q31_t)0x5a41f6b7, (q31_t)0x5a3d8212, + (q31_t)0x5a390d35, (q31_t)0x5a349821, (q31_t)0x5a3022d5, (q31_t)0x5a2bad51, (q31_t)0x5a273796, (q31_t)0x5a22c1a3, (q31_t)0x5a1e4b79, (q31_t)0x5a19d517, + (q31_t)0x5a155e7d, (q31_t)0x5a10e7ac, (q31_t)0x5a0c70a3, (q31_t)0x5a07f963, (q31_t)0x5a0381eb, (q31_t)0x59ff0a3c, (q31_t)0x59fa9255, (q31_t)0x59f61a36, + (q31_t)0x59f1a1e0, (q31_t)0x59ed2953, (q31_t)0x59e8b08e, (q31_t)0x59e43792, (q31_t)0x59dfbe5e, (q31_t)0x59db44f3, (q31_t)0x59d6cb50, (q31_t)0x59d25176, + (q31_t)0x59cdd765, (q31_t)0x59c95d1c, (q31_t)0x59c4e29c, (q31_t)0x59c067e4, (q31_t)0x59bbecf5, (q31_t)0x59b771cf, (q31_t)0x59b2f671, (q31_t)0x59ae7add, + (q31_t)0x59a9ff10, (q31_t)0x59a5830d, (q31_t)0x59a106d2, (q31_t)0x599c8a60, (q31_t)0x59980db6, (q31_t)0x599390d5, (q31_t)0x598f13bd, (q31_t)0x598a966e, + (q31_t)0x598618e8, (q31_t)0x59819b2a, (q31_t)0x597d1d35, (q31_t)0x59789f09, (q31_t)0x597420a6, (q31_t)0x596fa20b, (q31_t)0x596b233a, (q31_t)0x5966a431, + (q31_t)0x596224f1, (q31_t)0x595da57a, (q31_t)0x595925cc, (q31_t)0x5954a5e6, (q31_t)0x595025ca, (q31_t)0x594ba576, (q31_t)0x594724ec, (q31_t)0x5942a42a, + (q31_t)0x593e2331, (q31_t)0x5939a202, (q31_t)0x5935209b, (q31_t)0x59309efd, (q31_t)0x592c1d28, (q31_t)0x59279b1c, (q31_t)0x592318d9, (q31_t)0x591e9660, + (q31_t)0x591a13af, (q31_t)0x591590c7, (q31_t)0x59110da8, (q31_t)0x590c8a53, (q31_t)0x590806c6, (q31_t)0x59038302, (q31_t)0x58feff08, (q31_t)0x58fa7ad7, + (q31_t)0x58f5f66e, (q31_t)0x58f171cf, (q31_t)0x58ececf9, (q31_t)0x58e867ed, (q31_t)0x58e3e2a9, (q31_t)0x58df5d2e, (q31_t)0x58dad77d, (q31_t)0x58d65195, + (q31_t)0x58d1cb76, (q31_t)0x58cd4520, (q31_t)0x58c8be94, (q31_t)0x58c437d1, (q31_t)0x58bfb0d7, (q31_t)0x58bb29a6, (q31_t)0x58b6a23e, (q31_t)0x58b21aa0, + (q31_t)0x58ad92cb, (q31_t)0x58a90ac0, (q31_t)0x58a4827d, (q31_t)0x589ffa04, (q31_t)0x589b7155, (q31_t)0x5896e86f, (q31_t)0x58925f52, (q31_t)0x588dd5fe, + (q31_t)0x58894c74, (q31_t)0x5884c2b3, (q31_t)0x588038bb, (q31_t)0x587bae8d, (q31_t)0x58772429, (q31_t)0x5872998e, (q31_t)0x586e0ebc, (q31_t)0x586983b4, + (q31_t)0x5864f875, (q31_t)0x58606d00, (q31_t)0x585be154, (q31_t)0x58575571, (q31_t)0x5852c958, (q31_t)0x584e3d09, (q31_t)0x5849b083, (q31_t)0x584523c7, + (q31_t)0x584096d4, (q31_t)0x583c09ab, (q31_t)0x58377c4c, (q31_t)0x5832eeb6, (q31_t)0x582e60e9, (q31_t)0x5829d2e6, (q31_t)0x582544ad, (q31_t)0x5820b63e, + (q31_t)0x581c2798, (q31_t)0x581798bb, (q31_t)0x581309a9, (q31_t)0x580e7a60, (q31_t)0x5809eae1, (q31_t)0x58055b2b, (q31_t)0x5800cb3f, (q31_t)0x57fc3b1d, + (q31_t)0x57f7aac5, (q31_t)0x57f31a36, (q31_t)0x57ee8971, (q31_t)0x57e9f876, (q31_t)0x57e56744, (q31_t)0x57e0d5dd, (q31_t)0x57dc443f, (q31_t)0x57d7b26b, + (q31_t)0x57d32061, (q31_t)0x57ce8e20, (q31_t)0x57c9fbaa, (q31_t)0x57c568fd, (q31_t)0x57c0d61a, (q31_t)0x57bc4301, (q31_t)0x57b7afb2, (q31_t)0x57b31c2d, + (q31_t)0x57ae8872, (q31_t)0x57a9f480, (q31_t)0x57a56059, (q31_t)0x57a0cbfb, (q31_t)0x579c3768, (q31_t)0x5797a29e, (q31_t)0x57930d9e, (q31_t)0x578e7869, + (q31_t)0x5789e2fd, (q31_t)0x57854d5b, (q31_t)0x5780b784, (q31_t)0x577c2176, (q31_t)0x57778b32, (q31_t)0x5772f4b9, (q31_t)0x576e5e09, (q31_t)0x5769c724, + (q31_t)0x57653009, (q31_t)0x576098b7, (q31_t)0x575c0130, (q31_t)0x57576973, (q31_t)0x5752d180, (q31_t)0x574e3957, (q31_t)0x5749a0f9, (q31_t)0x57450864, + (q31_t)0x57406f9a, (q31_t)0x573bd69a, (q31_t)0x57373d64, (q31_t)0x5732a3f8, (q31_t)0x572e0a56, (q31_t)0x5729707f, (q31_t)0x5724d672, (q31_t)0x57203c2f, + (q31_t)0x571ba1b7, (q31_t)0x57170708, (q31_t)0x57126c24, (q31_t)0x570dd10a, (q31_t)0x570935bb, (q31_t)0x57049a36, (q31_t)0x56fffe7b, (q31_t)0x56fb628b, + (q31_t)0x56f6c664, (q31_t)0x56f22a09, (q31_t)0x56ed8d77, (q31_t)0x56e8f0b0, (q31_t)0x56e453b4, (q31_t)0x56dfb681, (q31_t)0x56db1919, (q31_t)0x56d67b7c, + (q31_t)0x56d1dda9, (q31_t)0x56cd3fa1, (q31_t)0x56c8a162, (q31_t)0x56c402ef, (q31_t)0x56bf6446, (q31_t)0x56bac567, (q31_t)0x56b62653, (q31_t)0x56b18709, + (q31_t)0x56ace78a, (q31_t)0x56a847d6, (q31_t)0x56a3a7ec, (q31_t)0x569f07cc, (q31_t)0x569a6777, (q31_t)0x5695c6ed, (q31_t)0x5691262d, (q31_t)0x568c8538, + (q31_t)0x5687e40e, (q31_t)0x568342ae, (q31_t)0x567ea118, (q31_t)0x5679ff4e, (q31_t)0x56755d4e, (q31_t)0x5670bb19, (q31_t)0x566c18ae, (q31_t)0x5667760e, + (q31_t)0x5662d339, (q31_t)0x565e302e, (q31_t)0x56598cee, (q31_t)0x5654e979, (q31_t)0x565045cf, (q31_t)0x564ba1f0, (q31_t)0x5646fddb, (q31_t)0x56425991, + (q31_t)0x563db512, (q31_t)0x5639105d, (q31_t)0x56346b74, (q31_t)0x562fc655, (q31_t)0x562b2101, (q31_t)0x56267b78, (q31_t)0x5621d5ba, (q31_t)0x561d2fc6, + (q31_t)0x5618899e, (q31_t)0x5613e340, (q31_t)0x560f3cae, (q31_t)0x560a95e6, (q31_t)0x5605eee9, (q31_t)0x560147b7, (q31_t)0x55fca050, (q31_t)0x55f7f8b4, + (q31_t)0x55f350e3, (q31_t)0x55eea8dd, (q31_t)0x55ea00a2, (q31_t)0x55e55832, (q31_t)0x55e0af8d, (q31_t)0x55dc06b3, (q31_t)0x55d75da4, (q31_t)0x55d2b460, + (q31_t)0x55ce0ae7, (q31_t)0x55c96139, (q31_t)0x55c4b757, (q31_t)0x55c00d3f, (q31_t)0x55bb62f3, (q31_t)0x55b6b871, (q31_t)0x55b20dbb, (q31_t)0x55ad62d0, + (q31_t)0x55a8b7b0, (q31_t)0x55a40c5b, (q31_t)0x559f60d1, (q31_t)0x559ab513, (q31_t)0x55960920, (q31_t)0x55915cf8, (q31_t)0x558cb09b, (q31_t)0x55880409, + (q31_t)0x55835743, (q31_t)0x557eaa48, (q31_t)0x5579fd18, (q31_t)0x55754fb3, (q31_t)0x5570a21a, (q31_t)0x556bf44c, (q31_t)0x55674649, (q31_t)0x55629812, + (q31_t)0x555de9a6, (q31_t)0x55593b05, (q31_t)0x55548c30, (q31_t)0x554fdd26, (q31_t)0x554b2de7, (q31_t)0x55467e74, (q31_t)0x5541cecc, (q31_t)0x553d1ef0, + (q31_t)0x55386edf, (q31_t)0x5533be99, (q31_t)0x552f0e1f, (q31_t)0x552a5d70, (q31_t)0x5525ac8d, (q31_t)0x5520fb75, (q31_t)0x551c4a29, (q31_t)0x551798a8, + (q31_t)0x5512e6f3, (q31_t)0x550e3509, (q31_t)0x550982eb, (q31_t)0x5504d099, (q31_t)0x55001e12, (q31_t)0x54fb6b56, (q31_t)0x54f6b866, (q31_t)0x54f20542, + (q31_t)0x54ed51e9, (q31_t)0x54e89e5c, (q31_t)0x54e3ea9a, (q31_t)0x54df36a5, (q31_t)0x54da827a, (q31_t)0x54d5ce1c, (q31_t)0x54d11989, (q31_t)0x54cc64c2, + (q31_t)0x54c7afc6, (q31_t)0x54c2fa96, (q31_t)0x54be4532, (q31_t)0x54b98f9a, (q31_t)0x54b4d9cd, (q31_t)0x54b023cc, (q31_t)0x54ab6d97, (q31_t)0x54a6b72e, + (q31_t)0x54a20090, (q31_t)0x549d49bf, (q31_t)0x549892b9, (q31_t)0x5493db7f, (q31_t)0x548f2410, (q31_t)0x548a6c6e, (q31_t)0x5485b497, (q31_t)0x5480fc8c, + (q31_t)0x547c444d, (q31_t)0x54778bda, (q31_t)0x5472d333, (q31_t)0x546e1a58, (q31_t)0x54696149, (q31_t)0x5464a805, (q31_t)0x545fee8e, (q31_t)0x545b34e3, + (q31_t)0x54567b03, (q31_t)0x5451c0f0, (q31_t)0x544d06a8, (q31_t)0x54484c2d, (q31_t)0x5443917d, (q31_t)0x543ed699, (q31_t)0x543a1b82, (q31_t)0x54356037, + (q31_t)0x5430a4b7, (q31_t)0x542be904, (q31_t)0x54272d1d, (q31_t)0x54227102, (q31_t)0x541db4b3, (q31_t)0x5418f830, (q31_t)0x54143b79, (q31_t)0x540f7e8e, + (q31_t)0x540ac170, (q31_t)0x5406041d, (q31_t)0x54014697, (q31_t)0x53fc88dd, (q31_t)0x53f7caef, (q31_t)0x53f30cce, (q31_t)0x53ee4e78, (q31_t)0x53e98fef, + (q31_t)0x53e4d132, (q31_t)0x53e01242, (q31_t)0x53db531d, (q31_t)0x53d693c5, (q31_t)0x53d1d439, (q31_t)0x53cd147a, (q31_t)0x53c85486, (q31_t)0x53c3945f, + (q31_t)0x53bed405, (q31_t)0x53ba1377, (q31_t)0x53b552b5, (q31_t)0x53b091bf, (q31_t)0x53abd096, (q31_t)0x53a70f39, (q31_t)0x53a24da9, (q31_t)0x539d8be5, + (q31_t)0x5398c9ed, (q31_t)0x539407c2, (q31_t)0x538f4564, (q31_t)0x538a82d1, (q31_t)0x5385c00c, (q31_t)0x5380fd12, (q31_t)0x537c39e6, (q31_t)0x53777685, + (q31_t)0x5372b2f2, (q31_t)0x536def2a, (q31_t)0x53692b30, (q31_t)0x53646701, (q31_t)0x535fa2a0, (q31_t)0x535ade0b, (q31_t)0x53561942, (q31_t)0x53515447, + (q31_t)0x534c8f17, (q31_t)0x5347c9b5, (q31_t)0x5343041f, (q31_t)0x533e3e55, (q31_t)0x53397859, (q31_t)0x5334b229, (q31_t)0x532febc5, (q31_t)0x532b252f, + (q31_t)0x53265e65, (q31_t)0x53219767, (q31_t)0x531cd037, (q31_t)0x531808d3, (q31_t)0x5313413c, (q31_t)0x530e7972, (q31_t)0x5309b174, (q31_t)0x5304e943, + (q31_t)0x530020df, (q31_t)0x52fb5848, (q31_t)0x52f68f7e, (q31_t)0x52f1c680, (q31_t)0x52ecfd4f, (q31_t)0x52e833ec, (q31_t)0x52e36a55, (q31_t)0x52dea08a, + (q31_t)0x52d9d68d, (q31_t)0x52d50c5d, (q31_t)0x52d041f9, (q31_t)0x52cb7763, (q31_t)0x52c6ac99, (q31_t)0x52c1e19d, (q31_t)0x52bd166d, (q31_t)0x52b84b0a, + (q31_t)0x52b37f74, (q31_t)0x52aeb3ac, (q31_t)0x52a9e7b0, (q31_t)0x52a51b81, (q31_t)0x52a04f1f, (q31_t)0x529b828a, (q31_t)0x5296b5c3, (q31_t)0x5291e8c8, + (q31_t)0x528d1b9b, (q31_t)0x52884e3a, (q31_t)0x528380a7, (q31_t)0x527eb2e0, (q31_t)0x5279e4e7, (q31_t)0x527516bb, (q31_t)0x5270485c, (q31_t)0x526b79ca, + (q31_t)0x5266ab06, (q31_t)0x5261dc0e, (q31_t)0x525d0ce4, (q31_t)0x52583d87, (q31_t)0x52536df7, (q31_t)0x524e9e34, (q31_t)0x5249ce3f, (q31_t)0x5244fe17, + (q31_t)0x52402dbc, (q31_t)0x523b5d2e, (q31_t)0x52368c6e, (q31_t)0x5231bb7b, (q31_t)0x522cea55, (q31_t)0x522818fc, (q31_t)0x52234771, (q31_t)0x521e75b3, + (q31_t)0x5219a3c3, (q31_t)0x5214d1a0, (q31_t)0x520fff4a, (q31_t)0x520b2cc2, (q31_t)0x52065a07, (q31_t)0x52018719, (q31_t)0x51fcb3f9, (q31_t)0x51f7e0a6, + (q31_t)0x51f30d21, (q31_t)0x51ee3969, (q31_t)0x51e9657e, (q31_t)0x51e49162, (q31_t)0x51dfbd12, (q31_t)0x51dae890, (q31_t)0x51d613dc, (q31_t)0x51d13ef5, + (q31_t)0x51cc69db, (q31_t)0x51c79490, (q31_t)0x51c2bf11, (q31_t)0x51bde960, (q31_t)0x51b9137d, (q31_t)0x51b43d68, (q31_t)0x51af6720, (q31_t)0x51aa90a5, + (q31_t)0x51a5b9f9, (q31_t)0x51a0e31a, (q31_t)0x519c0c08, (q31_t)0x519734c4, (q31_t)0x51925d4e, (q31_t)0x518d85a6, (q31_t)0x5188adcb, (q31_t)0x5183d5be, + (q31_t)0x517efd7f, (q31_t)0x517a250d, (q31_t)0x51754c69, (q31_t)0x51707393, (q31_t)0x516b9a8b, (q31_t)0x5166c150, (q31_t)0x5161e7e4, (q31_t)0x515d0e45, + (q31_t)0x51583473, (q31_t)0x51535a70, (q31_t)0x514e803b, (q31_t)0x5149a5d3, (q31_t)0x5144cb39, (q31_t)0x513ff06d, (q31_t)0x513b156f, (q31_t)0x51363a3f, + (q31_t)0x51315edd, (q31_t)0x512c8348, (q31_t)0x5127a782, (q31_t)0x5122cb8a, (q31_t)0x511def5f, (q31_t)0x51191302, (q31_t)0x51143674, (q31_t)0x510f59b3, + (q31_t)0x510a7cc1, (q31_t)0x51059f9c, (q31_t)0x5100c246, (q31_t)0x50fbe4bd, (q31_t)0x50f70703, (q31_t)0x50f22916, (q31_t)0x50ed4af8, (q31_t)0x50e86ca8, + (q31_t)0x50e38e25, (q31_t)0x50deaf71, (q31_t)0x50d9d08b, (q31_t)0x50d4f173, (q31_t)0x50d0122a, (q31_t)0x50cb32ae, (q31_t)0x50c65301, (q31_t)0x50c17322, + (q31_t)0x50bc9311, (q31_t)0x50b7b2ce, (q31_t)0x50b2d259, (q31_t)0x50adf1b3, (q31_t)0x50a910db, (q31_t)0x50a42fd1, (q31_t)0x509f4e95, (q31_t)0x509a6d28, + (q31_t)0x50958b88, (q31_t)0x5090a9b8, (q31_t)0x508bc7b5, (q31_t)0x5086e581, (q31_t)0x5082031b, (q31_t)0x507d2083, (q31_t)0x50783dba, (q31_t)0x50735abf, + (q31_t)0x506e7793, (q31_t)0x50699435, (q31_t)0x5064b0a5, (q31_t)0x505fcce4, (q31_t)0x505ae8f1, (q31_t)0x505604cd, (q31_t)0x50512077, (q31_t)0x504c3bef, + (q31_t)0x50475736, (q31_t)0x5042724c, (q31_t)0x503d8d30, (q31_t)0x5038a7e2, (q31_t)0x5033c263, (q31_t)0x502edcb2, (q31_t)0x5029f6d1, (q31_t)0x502510bd, + (q31_t)0x50202a78, (q31_t)0x501b4402, (q31_t)0x50165d5a, (q31_t)0x50117681, (q31_t)0x500c8f77, (q31_t)0x5007a83b, (q31_t)0x5002c0cd, (q31_t)0x4ffdd92f, + (q31_t)0x4ff8f15f, (q31_t)0x4ff4095e, (q31_t)0x4fef212b, (q31_t)0x4fea38c7, (q31_t)0x4fe55032, (q31_t)0x4fe0676c, (q31_t)0x4fdb7e74, (q31_t)0x4fd6954b, + (q31_t)0x4fd1abf0, (q31_t)0x4fccc265, (q31_t)0x4fc7d8a8, (q31_t)0x4fc2eeba, (q31_t)0x4fbe049b, (q31_t)0x4fb91a4b, (q31_t)0x4fb42fc9, (q31_t)0x4faf4517, + (q31_t)0x4faa5a33, (q31_t)0x4fa56f1e, (q31_t)0x4fa083d8, (q31_t)0x4f9b9861, (q31_t)0x4f96acb8, (q31_t)0x4f91c0df, (q31_t)0x4f8cd4d4, (q31_t)0x4f87e899, + (q31_t)0x4f82fc2c, (q31_t)0x4f7e0f8f, (q31_t)0x4f7922c0, (q31_t)0x4f7435c0, (q31_t)0x4f6f488f, (q31_t)0x4f6a5b2e, (q31_t)0x4f656d9b, (q31_t)0x4f607fd7, + (q31_t)0x4f5b91e3, (q31_t)0x4f56a3bd, (q31_t)0x4f51b566, (q31_t)0x4f4cc6df, (q31_t)0x4f47d827, (q31_t)0x4f42e93d, (q31_t)0x4f3dfa23, (q31_t)0x4f390ad8, + (q31_t)0x4f341b5c, (q31_t)0x4f2f2baf, (q31_t)0x4f2a3bd2, (q31_t)0x4f254bc3, (q31_t)0x4f205b84, (q31_t)0x4f1b6b14, (q31_t)0x4f167a73, (q31_t)0x4f1189a1, + (q31_t)0x4f0c989f, (q31_t)0x4f07a76b, (q31_t)0x4f02b608, (q31_t)0x4efdc473, (q31_t)0x4ef8d2ad, (q31_t)0x4ef3e0b7, (q31_t)0x4eeeee90, (q31_t)0x4ee9fc39, + (q31_t)0x4ee509b1, (q31_t)0x4ee016f8, (q31_t)0x4edb240e, (q31_t)0x4ed630f4, (q31_t)0x4ed13da9, (q31_t)0x4ecc4a2e, (q31_t)0x4ec75682, (q31_t)0x4ec262a5, + (q31_t)0x4ebd6e98, (q31_t)0x4eb87a5a, (q31_t)0x4eb385ec, (q31_t)0x4eae914d, (q31_t)0x4ea99c7d, (q31_t)0x4ea4a77d, (q31_t)0x4e9fb24d, (q31_t)0x4e9abcec, + (q31_t)0x4e95c75b, (q31_t)0x4e90d199, (q31_t)0x4e8bdba6, (q31_t)0x4e86e583, (q31_t)0x4e81ef30, (q31_t)0x4e7cf8ac, (q31_t)0x4e7801f8, (q31_t)0x4e730b14, + (q31_t)0x4e6e13ff, (q31_t)0x4e691cba, (q31_t)0x4e642544, (q31_t)0x4e5f2d9e, (q31_t)0x4e5a35c7, (q31_t)0x4e553dc1, (q31_t)0x4e50458a, (q31_t)0x4e4b4d22, + (q31_t)0x4e46548b, (q31_t)0x4e415bc3, (q31_t)0x4e3c62cb, (q31_t)0x4e3769a2, (q31_t)0x4e32704a, (q31_t)0x4e2d76c1, (q31_t)0x4e287d08, (q31_t)0x4e23831e, + (q31_t)0x4e1e8905, (q31_t)0x4e198ebb, (q31_t)0x4e149441, (q31_t)0x4e0f9997, (q31_t)0x4e0a9ebd, (q31_t)0x4e05a3b2, (q31_t)0x4e00a878, (q31_t)0x4dfbad0d, + (q31_t)0x4df6b173, (q31_t)0x4df1b5a8, (q31_t)0x4decb9ad, (q31_t)0x4de7bd82, (q31_t)0x4de2c127, (q31_t)0x4dddc49c, (q31_t)0x4dd8c7e1, (q31_t)0x4dd3caf6, + (q31_t)0x4dcecdda, (q31_t)0x4dc9d08f, (q31_t)0x4dc4d314, (q31_t)0x4dbfd569, (q31_t)0x4dbad78e, (q31_t)0x4db5d983, (q31_t)0x4db0db48, (q31_t)0x4dabdcdd, + (q31_t)0x4da6de43, (q31_t)0x4da1df78, (q31_t)0x4d9ce07d, (q31_t)0x4d97e153, (q31_t)0x4d92e1f9, (q31_t)0x4d8de26f, (q31_t)0x4d88e2b5, (q31_t)0x4d83e2cb, + (q31_t)0x4d7ee2b1, (q31_t)0x4d79e268, (q31_t)0x4d74e1ef, (q31_t)0x4d6fe146, (q31_t)0x4d6ae06d, (q31_t)0x4d65df64, (q31_t)0x4d60de2c, (q31_t)0x4d5bdcc4, + (q31_t)0x4d56db2d, (q31_t)0x4d51d965, (q31_t)0x4d4cd76e, (q31_t)0x4d47d547, (q31_t)0x4d42d2f1, (q31_t)0x4d3dd06b, (q31_t)0x4d38cdb5, (q31_t)0x4d33cad0, + (q31_t)0x4d2ec7bb, (q31_t)0x4d29c476, (q31_t)0x4d24c102, (q31_t)0x4d1fbd5e, (q31_t)0x4d1ab98b, (q31_t)0x4d15b588, (q31_t)0x4d10b155, (q31_t)0x4d0bacf3, + (q31_t)0x4d06a862, (q31_t)0x4d01a3a0, (q31_t)0x4cfc9eb0, (q31_t)0x4cf79990, (q31_t)0x4cf29440, (q31_t)0x4ced8ec1, (q31_t)0x4ce88913, (q31_t)0x4ce38335, + (q31_t)0x4cde7d28, (q31_t)0x4cd976eb, (q31_t)0x4cd4707f, (q31_t)0x4ccf69e3, (q31_t)0x4cca6318, (q31_t)0x4cc55c1e, (q31_t)0x4cc054f4, (q31_t)0x4cbb4d9b, + (q31_t)0x4cb64613, (q31_t)0x4cb13e5b, (q31_t)0x4cac3674, (q31_t)0x4ca72e5e, (q31_t)0x4ca22619, (q31_t)0x4c9d1da4, (q31_t)0x4c981500, (q31_t)0x4c930c2d, + (q31_t)0x4c8e032a, (q31_t)0x4c88f9f8, (q31_t)0x4c83f097, (q31_t)0x4c7ee707, (q31_t)0x4c79dd48, (q31_t)0x4c74d359, (q31_t)0x4c6fc93b, (q31_t)0x4c6abeef, + (q31_t)0x4c65b473, (q31_t)0x4c60a9c8, (q31_t)0x4c5b9eed, (q31_t)0x4c5693e4, (q31_t)0x4c5188ac, (q31_t)0x4c4c7d44, (q31_t)0x4c4771ae, (q31_t)0x4c4265e8, + (q31_t)0x4c3d59f3, (q31_t)0x4c384dd0, (q31_t)0x4c33417d, (q31_t)0x4c2e34fb, (q31_t)0x4c29284b, (q31_t)0x4c241b6b, (q31_t)0x4c1f0e5c, (q31_t)0x4c1a011f, + (q31_t)0x4c14f3b2, (q31_t)0x4c0fe617, (q31_t)0x4c0ad84c, (q31_t)0x4c05ca53, (q31_t)0x4c00bc2b, (q31_t)0x4bfbadd4, (q31_t)0x4bf69f4e, (q31_t)0x4bf19099, + (q31_t)0x4bec81b5, (q31_t)0x4be772a3, (q31_t)0x4be26362, (q31_t)0x4bdd53f2, (q31_t)0x4bd84453, (q31_t)0x4bd33485, (q31_t)0x4bce2488, (q31_t)0x4bc9145d, + (q31_t)0x4bc40403, (q31_t)0x4bbef37b, (q31_t)0x4bb9e2c3, (q31_t)0x4bb4d1dd, (q31_t)0x4bafc0c8, (q31_t)0x4baaaf85, (q31_t)0x4ba59e12, (q31_t)0x4ba08c72, + (q31_t)0x4b9b7aa2, (q31_t)0x4b9668a4, (q31_t)0x4b915677, (q31_t)0x4b8c441c, (q31_t)0x4b873192, (q31_t)0x4b821ed9, (q31_t)0x4b7d0bf2, (q31_t)0x4b77f8dc, + (q31_t)0x4b72e598, (q31_t)0x4b6dd225, (q31_t)0x4b68be84, (q31_t)0x4b63aab4, (q31_t)0x4b5e96b6, (q31_t)0x4b598289, (q31_t)0x4b546e2d, (q31_t)0x4b4f59a4, + (q31_t)0x4b4a44eb, (q31_t)0x4b453005, (q31_t)0x4b401aef, (q31_t)0x4b3b05ac, (q31_t)0x4b35f03a, (q31_t)0x4b30da9a, (q31_t)0x4b2bc4cb, (q31_t)0x4b26aece, + (q31_t)0x4b2198a2, (q31_t)0x4b1c8248, (q31_t)0x4b176bc0, (q31_t)0x4b12550a, (q31_t)0x4b0d3e25, (q31_t)0x4b082712, (q31_t)0x4b030fd1, (q31_t)0x4afdf861, + (q31_t)0x4af8e0c3, (q31_t)0x4af3c8f7, (q31_t)0x4aeeb0fd, (q31_t)0x4ae998d4, (q31_t)0x4ae4807d, (q31_t)0x4adf67f8, (q31_t)0x4ada4f45, (q31_t)0x4ad53664, + (q31_t)0x4ad01d54, (q31_t)0x4acb0417, (q31_t)0x4ac5eaab, (q31_t)0x4ac0d111, (q31_t)0x4abbb749, (q31_t)0x4ab69d53, (q31_t)0x4ab1832f, (q31_t)0x4aac68dc, + (q31_t)0x4aa74e5c, (q31_t)0x4aa233ae, (q31_t)0x4a9d18d1, (q31_t)0x4a97fdc7, (q31_t)0x4a92e28e, (q31_t)0x4a8dc728, (q31_t)0x4a88ab93, (q31_t)0x4a838fd1, + (q31_t)0x4a7e73e0, (q31_t)0x4a7957c2, (q31_t)0x4a743b76, (q31_t)0x4a6f1efc, (q31_t)0x4a6a0253, (q31_t)0x4a64e57d, (q31_t)0x4a5fc879, (q31_t)0x4a5aab48, + (q31_t)0x4a558de8, (q31_t)0x4a50705a, (q31_t)0x4a4b529f, (q31_t)0x4a4634b6, (q31_t)0x4a41169f, (q31_t)0x4a3bf85a, (q31_t)0x4a36d9e7, (q31_t)0x4a31bb47, + (q31_t)0x4a2c9c79, (q31_t)0x4a277d7d, (q31_t)0x4a225e53, (q31_t)0x4a1d3efc, (q31_t)0x4a181f77, (q31_t)0x4a12ffc4, (q31_t)0x4a0ddfe4, (q31_t)0x4a08bfd5, + (q31_t)0x4a039f9a, (q31_t)0x49fe7f30, (q31_t)0x49f95e99, (q31_t)0x49f43dd4, (q31_t)0x49ef1ce2, (q31_t)0x49e9fbc2, (q31_t)0x49e4da74, (q31_t)0x49dfb8f9, + (q31_t)0x49da9750, (q31_t)0x49d5757a, (q31_t)0x49d05376, (q31_t)0x49cb3145, (q31_t)0x49c60ee6, (q31_t)0x49c0ec59, (q31_t)0x49bbc9a0, (q31_t)0x49b6a6b8, + (q31_t)0x49b183a3, (q31_t)0x49ac6061, (q31_t)0x49a73cf1, (q31_t)0x49a21954, (q31_t)0x499cf589, (q31_t)0x4997d191, (q31_t)0x4992ad6c, (q31_t)0x498d8919, + (q31_t)0x49886499, (q31_t)0x49833fec, (q31_t)0x497e1b11, (q31_t)0x4978f609, (q31_t)0x4973d0d3, (q31_t)0x496eab70, (q31_t)0x496985e0, (q31_t)0x49646023, + (q31_t)0x495f3a38, (q31_t)0x495a1420, (q31_t)0x4954eddb, (q31_t)0x494fc768, (q31_t)0x494aa0c9, (q31_t)0x494579fc, (q31_t)0x49405302, (q31_t)0x493b2bdb, + (q31_t)0x49360486, (q31_t)0x4930dd05, (q31_t)0x492bb556, (q31_t)0x49268d7a, (q31_t)0x49216571, (q31_t)0x491c3d3b, (q31_t)0x491714d8, (q31_t)0x4911ec47, + (q31_t)0x490cc38a, (q31_t)0x49079aa0, (q31_t)0x49027188, (q31_t)0x48fd4844, (q31_t)0x48f81ed2, (q31_t)0x48f2f534, (q31_t)0x48edcb68, (q31_t)0x48e8a170, + (q31_t)0x48e3774a, (q31_t)0x48de4cf8, (q31_t)0x48d92278, (q31_t)0x48d3f7cc, (q31_t)0x48ceccf3, (q31_t)0x48c9a1ed, (q31_t)0x48c476b9, (q31_t)0x48bf4b59, + (q31_t)0x48ba1fcd, (q31_t)0x48b4f413, (q31_t)0x48afc82c, (q31_t)0x48aa9c19, (q31_t)0x48a56fd9, (q31_t)0x48a0436c, (q31_t)0x489b16d2, (q31_t)0x4895ea0b, + (q31_t)0x4890bd18, (q31_t)0x488b8ff8, (q31_t)0x488662ab, (q31_t)0x48813531, (q31_t)0x487c078b, (q31_t)0x4876d9b8, (q31_t)0x4871abb8, (q31_t)0x486c7d8c, + (q31_t)0x48674f33, (q31_t)0x486220ad, (q31_t)0x485cf1fa, (q31_t)0x4857c31b, (q31_t)0x48529410, (q31_t)0x484d64d7, (q31_t)0x48483572, (q31_t)0x484305e1, + (q31_t)0x483dd623, (q31_t)0x4838a638, (q31_t)0x48337621, (q31_t)0x482e45dd, (q31_t)0x4829156d, (q31_t)0x4823e4d0, (q31_t)0x481eb407, (q31_t)0x48198311, + (q31_t)0x481451ef, (q31_t)0x480f20a0, (q31_t)0x4809ef25, (q31_t)0x4804bd7e, (q31_t)0x47ff8baa, (q31_t)0x47fa59a9, (q31_t)0x47f5277d, (q31_t)0x47eff523, + (q31_t)0x47eac29e, (q31_t)0x47e58fec, (q31_t)0x47e05d0e, (q31_t)0x47db2a03, (q31_t)0x47d5f6cc, (q31_t)0x47d0c369, (q31_t)0x47cb8fd9, (q31_t)0x47c65c1d, + (q31_t)0x47c12835, (q31_t)0x47bbf421, (q31_t)0x47b6bfe0, (q31_t)0x47b18b74, (q31_t)0x47ac56da, (q31_t)0x47a72215, (q31_t)0x47a1ed24, (q31_t)0x479cb806, + (q31_t)0x479782bc, (q31_t)0x47924d46, (q31_t)0x478d17a4, (q31_t)0x4787e1d6, (q31_t)0x4782abdb, (q31_t)0x477d75b5, (q31_t)0x47783f62, (q31_t)0x477308e3, + (q31_t)0x476dd239, (q31_t)0x47689b62, (q31_t)0x4763645f, (q31_t)0x475e2d30, (q31_t)0x4758f5d5, (q31_t)0x4753be4e, (q31_t)0x474e869b, (q31_t)0x47494ebc, + (q31_t)0x474416b1, (q31_t)0x473ede7a, (q31_t)0x4739a617, (q31_t)0x47346d89, (q31_t)0x472f34ce, (q31_t)0x4729fbe7, (q31_t)0x4724c2d5, (q31_t)0x471f8996, + (q31_t)0x471a502c, (q31_t)0x47151696, (q31_t)0x470fdcd4, (q31_t)0x470aa2e6, (q31_t)0x470568cd, (q31_t)0x47002e87, (q31_t)0x46faf416, (q31_t)0x46f5b979, + (q31_t)0x46f07eb0, (q31_t)0x46eb43bc, (q31_t)0x46e6089b, (q31_t)0x46e0cd4f, (q31_t)0x46db91d8, (q31_t)0x46d65634, (q31_t)0x46d11a65, (q31_t)0x46cbde6a, + (q31_t)0x46c6a244, (q31_t)0x46c165f1, (q31_t)0x46bc2974, (q31_t)0x46b6ecca, (q31_t)0x46b1aff5, (q31_t)0x46ac72f4, (q31_t)0x46a735c8, (q31_t)0x46a1f870, + (q31_t)0x469cbaed, (q31_t)0x46977d3e, (q31_t)0x46923f63, (q31_t)0x468d015d, (q31_t)0x4687c32c, (q31_t)0x468284cf, (q31_t)0x467d4646, (q31_t)0x46780792, + (q31_t)0x4672c8b3, (q31_t)0x466d89a8, (q31_t)0x46684a71, (q31_t)0x46630b0f, (q31_t)0x465dcb82, (q31_t)0x46588bc9, (q31_t)0x46534be5, (q31_t)0x464e0bd6, + (q31_t)0x4648cb9b, (q31_t)0x46438b35, (q31_t)0x463e4aa3, (q31_t)0x463909e7, (q31_t)0x4633c8fe, (q31_t)0x462e87eb, (q31_t)0x462946ac, (q31_t)0x46240542, + (q31_t)0x461ec3ad, (q31_t)0x461981ec, (q31_t)0x46144001, (q31_t)0x460efde9, (q31_t)0x4609bba7, (q31_t)0x4604793a, (q31_t)0x45ff36a1, (q31_t)0x45f9f3dd, + (q31_t)0x45f4b0ee, (q31_t)0x45ef6dd4, (q31_t)0x45ea2a8f, (q31_t)0x45e4e71f, (q31_t)0x45dfa383, (q31_t)0x45da5fbc, (q31_t)0x45d51bcb, (q31_t)0x45cfd7ae, + (q31_t)0x45ca9366, (q31_t)0x45c54ef3, (q31_t)0x45c00a55, (q31_t)0x45bac58c, (q31_t)0x45b58098, (q31_t)0x45b03b79, (q31_t)0x45aaf630, (q31_t)0x45a5b0bb, + (q31_t)0x45a06b1b, (q31_t)0x459b2550, (q31_t)0x4595df5a, (q31_t)0x45909939, (q31_t)0x458b52ee, (q31_t)0x45860c77, (q31_t)0x4580c5d6, (q31_t)0x457b7f0a, + (q31_t)0x45763813, (q31_t)0x4570f0f1, (q31_t)0x456ba9a4, (q31_t)0x4566622c, (q31_t)0x45611a8a, (q31_t)0x455bd2bc, (q31_t)0x45568ac4, (q31_t)0x455142a2, + (q31_t)0x454bfa54, (q31_t)0x4546b1dc, (q31_t)0x45416939, (q31_t)0x453c206b, (q31_t)0x4536d773, (q31_t)0x45318e4f, (q31_t)0x452c4502, (q31_t)0x4526fb89, + (q31_t)0x4521b1e6, (q31_t)0x451c6818, (q31_t)0x45171e20, (q31_t)0x4511d3fd, (q31_t)0x450c89af, (q31_t)0x45073f37, (q31_t)0x4501f494, (q31_t)0x44fca9c6, + (q31_t)0x44f75ecf, (q31_t)0x44f213ac, (q31_t)0x44ecc85f, (q31_t)0x44e77ce7, (q31_t)0x44e23145, (q31_t)0x44dce579, (q31_t)0x44d79982, (q31_t)0x44d24d60, + (q31_t)0x44cd0114, (q31_t)0x44c7b49e, (q31_t)0x44c267fd, (q31_t)0x44bd1b32, (q31_t)0x44b7ce3c, (q31_t)0x44b2811c, (q31_t)0x44ad33d2, (q31_t)0x44a7e65d, + (q31_t)0x44a298be, (q31_t)0x449d4af5, (q31_t)0x4497fd01, (q31_t)0x4492aee3, (q31_t)0x448d609b, (q31_t)0x44881228, (q31_t)0x4482c38b, (q31_t)0x447d74c4, + (q31_t)0x447825d2, (q31_t)0x4472d6b7, (q31_t)0x446d8771, (q31_t)0x44683801, (q31_t)0x4462e866, (q31_t)0x445d98a2, (q31_t)0x445848b3, (q31_t)0x4452f89b, + (q31_t)0x444da858, (q31_t)0x444857ea, (q31_t)0x44430753, (q31_t)0x443db692, (q31_t)0x443865a7, (q31_t)0x44331491, (q31_t)0x442dc351, (q31_t)0x442871e8, + (q31_t)0x44232054, (q31_t)0x441dce96, (q31_t)0x44187caf, (q31_t)0x44132a9d, (q31_t)0x440dd861, (q31_t)0x440885fc, (q31_t)0x4403336c, (q31_t)0x43fde0b2, + (q31_t)0x43f88dcf, (q31_t)0x43f33ac1, (q31_t)0x43ede78a, (q31_t)0x43e89429, (q31_t)0x43e3409d, (q31_t)0x43ddece8, (q31_t)0x43d8990a, (q31_t)0x43d34501, + (q31_t)0x43cdf0ce, (q31_t)0x43c89c72, (q31_t)0x43c347eb, (q31_t)0x43bdf33b, (q31_t)0x43b89e62, (q31_t)0x43b3495e, (q31_t)0x43adf431, (q31_t)0x43a89ed9, + (q31_t)0x43a34959, (q31_t)0x439df3ae, (q31_t)0x43989dda, (q31_t)0x439347dc, (q31_t)0x438df1b4, (q31_t)0x43889b63, (q31_t)0x438344e8, (q31_t)0x437dee43, + (q31_t)0x43789775, (q31_t)0x4373407d, (q31_t)0x436de95b, (q31_t)0x43689210, (q31_t)0x43633a9c, (q31_t)0x435de2fd, (q31_t)0x43588b36, (q31_t)0x43533344, + (q31_t)0x434ddb29, (q31_t)0x434882e5, (q31_t)0x43432a77, (q31_t)0x433dd1e0, (q31_t)0x4338791f, (q31_t)0x43332035, (q31_t)0x432dc721, (q31_t)0x43286de4, + (q31_t)0x4323147d, (q31_t)0x431dbaed, (q31_t)0x43186133, (q31_t)0x43130751, (q31_t)0x430dad44, (q31_t)0x4308530f, (q31_t)0x4302f8b0, (q31_t)0x42fd9e28, + (q31_t)0x42f84376, (q31_t)0x42f2e89b, (q31_t)0x42ed8d97, (q31_t)0x42e83269, (q31_t)0x42e2d713, (q31_t)0x42dd7b93, (q31_t)0x42d81fe9, (q31_t)0x42d2c417, + (q31_t)0x42cd681b, (q31_t)0x42c80bf6, (q31_t)0x42c2afa8, (q31_t)0x42bd5331, (q31_t)0x42b7f690, (q31_t)0x42b299c7, (q31_t)0x42ad3cd4, (q31_t)0x42a7dfb8, + (q31_t)0x42a28273, (q31_t)0x429d2505, (q31_t)0x4297c76e, (q31_t)0x429269ae, (q31_t)0x428d0bc4, (q31_t)0x4287adb2, (q31_t)0x42824f76, (q31_t)0x427cf112, + (q31_t)0x42779285, (q31_t)0x427233ce, (q31_t)0x426cd4ef, (q31_t)0x426775e6, (q31_t)0x426216b5, (q31_t)0x425cb75a, (q31_t)0x425757d7, (q31_t)0x4251f82b, + (q31_t)0x424c9856, (q31_t)0x42473858, (q31_t)0x4241d831, (q31_t)0x423c77e1, (q31_t)0x42371769, (q31_t)0x4231b6c7, (q31_t)0x422c55fd, (q31_t)0x4226f50a, + (q31_t)0x422193ee, (q31_t)0x421c32a9, (q31_t)0x4216d13c, (q31_t)0x42116fa5, (q31_t)0x420c0de6, (q31_t)0x4206abfe, (q31_t)0x420149ee, (q31_t)0x41fbe7b5, + (q31_t)0x41f68553, (q31_t)0x41f122c8, (q31_t)0x41ebc015, (q31_t)0x41e65d39, (q31_t)0x41e0fa35, (q31_t)0x41db9707, (q31_t)0x41d633b1, (q31_t)0x41d0d033, + (q31_t)0x41cb6c8c, (q31_t)0x41c608bc, (q31_t)0x41c0a4c4, (q31_t)0x41bb40a3, (q31_t)0x41b5dc5a, (q31_t)0x41b077e8, (q31_t)0x41ab134e, (q31_t)0x41a5ae8b, + (q31_t)0x41a049a0, (q31_t)0x419ae48c, (q31_t)0x41957f4f, (q31_t)0x419019eb, (q31_t)0x418ab45d, (q31_t)0x41854ea8, (q31_t)0x417fe8ca, (q31_t)0x417a82c3, + (q31_t)0x41751c94, (q31_t)0x416fb63d, (q31_t)0x416a4fbd, (q31_t)0x4164e916, (q31_t)0x415f8245, (q31_t)0x415a1b4d, (q31_t)0x4154b42c, (q31_t)0x414f4ce2, + (q31_t)0x4149e571, (q31_t)0x41447dd7, (q31_t)0x413f1615, (q31_t)0x4139ae2b, (q31_t)0x41344618, (q31_t)0x412edddd, (q31_t)0x4129757b, (q31_t)0x41240cef, + (q31_t)0x411ea43c, (q31_t)0x41193b61, (q31_t)0x4113d25d, (q31_t)0x410e6931, (q31_t)0x4108ffdd, (q31_t)0x41039661, (q31_t)0x40fe2cbd, (q31_t)0x40f8c2f1, + (q31_t)0x40f358fc, (q31_t)0x40edeee0, (q31_t)0x40e8849b, (q31_t)0x40e31a2f, (q31_t)0x40ddaf9b, (q31_t)0x40d844de, (q31_t)0x40d2d9f9, (q31_t)0x40cd6eed, + (q31_t)0x40c803b8, (q31_t)0x40c2985c, (q31_t)0x40bd2cd8, (q31_t)0x40b7c12b, (q31_t)0x40b25557, (q31_t)0x40ace95b, (q31_t)0x40a77d37, (q31_t)0x40a210eb, + (q31_t)0x409ca477, (q31_t)0x409737dc, (q31_t)0x4091cb18, (q31_t)0x408c5e2d, (q31_t)0x4086f11a, (q31_t)0x408183df, (q31_t)0x407c167c, (q31_t)0x4076a8f1, + (q31_t)0x40713b3f, (q31_t)0x406bcd65, (q31_t)0x40665f63, (q31_t)0x4060f13a, (q31_t)0x405b82e9, (q31_t)0x40561470, (q31_t)0x4050a5cf, (q31_t)0x404b3707, + (q31_t)0x4045c817, (q31_t)0x404058ff, (q31_t)0x403ae9c0, (q31_t)0x40357a59, (q31_t)0x40300acb, (q31_t)0x402a9b15, (q31_t)0x40252b37, (q31_t)0x401fbb32, + (q31_t)0x401a4b05, (q31_t)0x4014dab1, (q31_t)0x400f6a35, (q31_t)0x4009f992, (q31_t)0x400488c7, (q31_t)0x3fff17d5, (q31_t)0x3ff9a6bb, (q31_t)0x3ff4357a, + (q31_t)0x3feec411, (q31_t)0x3fe95281, (q31_t)0x3fe3e0c9, (q31_t)0x3fde6eeb, (q31_t)0x3fd8fce4, (q31_t)0x3fd38ab6, (q31_t)0x3fce1861, (q31_t)0x3fc8a5e5, + (q31_t)0x3fc33341, (q31_t)0x3fbdc076, (q31_t)0x3fb84d83, (q31_t)0x3fb2da6a, (q31_t)0x3fad6729, (q31_t)0x3fa7f3c0, (q31_t)0x3fa28031, (q31_t)0x3f9d0c7a, + (q31_t)0x3f97989c, (q31_t)0x3f922496, (q31_t)0x3f8cb06a, (q31_t)0x3f873c16, (q31_t)0x3f81c79b, (q31_t)0x3f7c52f9, (q31_t)0x3f76de30, (q31_t)0x3f71693f, + (q31_t)0x3f6bf428, (q31_t)0x3f667ee9, (q31_t)0x3f610983, (q31_t)0x3f5b93f6, (q31_t)0x3f561e42, (q31_t)0x3f50a867, (q31_t)0x3f4b3265, (q31_t)0x3f45bc3c, + (q31_t)0x3f4045ec, (q31_t)0x3f3acf75, (q31_t)0x3f3558d7, (q31_t)0x3f2fe211, (q31_t)0x3f2a6b25, (q31_t)0x3f24f412, (q31_t)0x3f1f7cd8, (q31_t)0x3f1a0577, + (q31_t)0x3f148def, (q31_t)0x3f0f1640, (q31_t)0x3f099e6b, (q31_t)0x3f04266e, (q31_t)0x3efeae4a, (q31_t)0x3ef93600, (q31_t)0x3ef3bd8f, (q31_t)0x3eee44f7, + (q31_t)0x3ee8cc38, (q31_t)0x3ee35352, (q31_t)0x3eddda46, (q31_t)0x3ed86113, (q31_t)0x3ed2e7b9, (q31_t)0x3ecd6e38, (q31_t)0x3ec7f491, (q31_t)0x3ec27ac2, + (q31_t)0x3ebd00cd, (q31_t)0x3eb786b2, (q31_t)0x3eb20c6f, (q31_t)0x3eac9206, (q31_t)0x3ea71777, (q31_t)0x3ea19cc1, (q31_t)0x3e9c21e4, (q31_t)0x3e96a6e0, + (q31_t)0x3e912bb6, (q31_t)0x3e8bb065, (q31_t)0x3e8634ee, (q31_t)0x3e80b950, (q31_t)0x3e7b3d8c, (q31_t)0x3e75c1a1, (q31_t)0x3e70458f, (q31_t)0x3e6ac957, + (q31_t)0x3e654cf8, (q31_t)0x3e5fd073, (q31_t)0x3e5a53c8, (q31_t)0x3e54d6f6, (q31_t)0x3e4f59fe, (q31_t)0x3e49dcdf, (q31_t)0x3e445f99, (q31_t)0x3e3ee22e, + (q31_t)0x3e39649c, (q31_t)0x3e33e6e3, (q31_t)0x3e2e6904, (q31_t)0x3e28eaff, (q31_t)0x3e236cd4, (q31_t)0x3e1dee82, (q31_t)0x3e18700a, (q31_t)0x3e12f16b, + (q31_t)0x3e0d72a6, (q31_t)0x3e07f3bb, (q31_t)0x3e0274aa, (q31_t)0x3dfcf572, (q31_t)0x3df77615, (q31_t)0x3df1f691, (q31_t)0x3dec76e6, (q31_t)0x3de6f716, + (q31_t)0x3de1771f, (q31_t)0x3ddbf703, (q31_t)0x3dd676c0, (q31_t)0x3dd0f656, (q31_t)0x3dcb75c7, (q31_t)0x3dc5f512, (q31_t)0x3dc07436, (q31_t)0x3dbaf335, + (q31_t)0x3db5720d, (q31_t)0x3daff0c0, (q31_t)0x3daa6f4c, (q31_t)0x3da4edb2, (q31_t)0x3d9f6bf2, (q31_t)0x3d99ea0d, (q31_t)0x3d946801, (q31_t)0x3d8ee5cf, + (q31_t)0x3d896377, (q31_t)0x3d83e0f9, (q31_t)0x3d7e5e56, (q31_t)0x3d78db8c, (q31_t)0x3d73589d, (q31_t)0x3d6dd587, (q31_t)0x3d68524c, (q31_t)0x3d62ceeb, + (q31_t)0x3d5d4b64, (q31_t)0x3d57c7b7, (q31_t)0x3d5243e4, (q31_t)0x3d4cbfeb, (q31_t)0x3d473bcd, (q31_t)0x3d41b789, (q31_t)0x3d3c331f, (q31_t)0x3d36ae8f, + (q31_t)0x3d3129da, (q31_t)0x3d2ba4fe, (q31_t)0x3d261ffd, (q31_t)0x3d209ad7, (q31_t)0x3d1b158a, (q31_t)0x3d159018, (q31_t)0x3d100a80, (q31_t)0x3d0a84c3, + (q31_t)0x3d04fee0, (q31_t)0x3cff78d7, (q31_t)0x3cf9f2a9, (q31_t)0x3cf46c55, (q31_t)0x3ceee5db, (q31_t)0x3ce95f3c, (q31_t)0x3ce3d877, (q31_t)0x3cde518d, + (q31_t)0x3cd8ca7d, (q31_t)0x3cd34347, (q31_t)0x3ccdbbed, (q31_t)0x3cc8346c, (q31_t)0x3cc2acc6, (q31_t)0x3cbd24fb, (q31_t)0x3cb79d0a, (q31_t)0x3cb214f4, + (q31_t)0x3cac8cb8, (q31_t)0x3ca70457, (q31_t)0x3ca17bd0, (q31_t)0x3c9bf324, (q31_t)0x3c966a53, (q31_t)0x3c90e15c, (q31_t)0x3c8b5840, (q31_t)0x3c85cefe, + (q31_t)0x3c804598, (q31_t)0x3c7abc0c, (q31_t)0x3c75325a, (q31_t)0x3c6fa883, (q31_t)0x3c6a1e87, (q31_t)0x3c649466, (q31_t)0x3c5f0a20, (q31_t)0x3c597fb4, + (q31_t)0x3c53f523, (q31_t)0x3c4e6a6d, (q31_t)0x3c48df91, (q31_t)0x3c435491, (q31_t)0x3c3dc96b, (q31_t)0x3c383e20, (q31_t)0x3c32b2b0, (q31_t)0x3c2d271b, + (q31_t)0x3c279b61, (q31_t)0x3c220f81, (q31_t)0x3c1c837d, (q31_t)0x3c16f753, (q31_t)0x3c116b04, (q31_t)0x3c0bde91, (q31_t)0x3c0651f8, (q31_t)0x3c00c53a, + (q31_t)0x3bfb3857, (q31_t)0x3bf5ab50, (q31_t)0x3bf01e23, (q31_t)0x3bea90d1, (q31_t)0x3be5035a, (q31_t)0x3bdf75bf, (q31_t)0x3bd9e7fe, (q31_t)0x3bd45a19, + (q31_t)0x3bcecc0e, (q31_t)0x3bc93ddf, (q31_t)0x3bc3af8b, (q31_t)0x3bbe2112, (q31_t)0x3bb89274, (q31_t)0x3bb303b1, (q31_t)0x3bad74c9, (q31_t)0x3ba7e5bd, + (q31_t)0x3ba2568c, (q31_t)0x3b9cc736, (q31_t)0x3b9737bb, (q31_t)0x3b91a81c, (q31_t)0x3b8c1857, (q31_t)0x3b86886e, (q31_t)0x3b80f861, (q31_t)0x3b7b682e, + (q31_t)0x3b75d7d7, (q31_t)0x3b70475c, (q31_t)0x3b6ab6bb, (q31_t)0x3b6525f6, (q31_t)0x3b5f950c, (q31_t)0x3b5a03fe, (q31_t)0x3b5472cb, (q31_t)0x3b4ee173, + (q31_t)0x3b494ff7, (q31_t)0x3b43be57, (q31_t)0x3b3e2c91, (q31_t)0x3b389aa8, (q31_t)0x3b330899, (q31_t)0x3b2d7666, (q31_t)0x3b27e40f, (q31_t)0x3b225193, + (q31_t)0x3b1cbef3, (q31_t)0x3b172c2e, (q31_t)0x3b119945, (q31_t)0x3b0c0637, (q31_t)0x3b067305, (q31_t)0x3b00dfaf, (q31_t)0x3afb4c34, (q31_t)0x3af5b894, + (q31_t)0x3af024d1, (q31_t)0x3aea90e9, (q31_t)0x3ae4fcdc, (q31_t)0x3adf68ac, (q31_t)0x3ad9d457, (q31_t)0x3ad43fdd, (q31_t)0x3aceab40, (q31_t)0x3ac9167e, + (q31_t)0x3ac38198, (q31_t)0x3abdec8d, (q31_t)0x3ab8575f, (q31_t)0x3ab2c20c, (q31_t)0x3aad2c95, (q31_t)0x3aa796fa, (q31_t)0x3aa2013a, (q31_t)0x3a9c6b57, + (q31_t)0x3a96d54f, (q31_t)0x3a913f23, (q31_t)0x3a8ba8d3, (q31_t)0x3a86125f, (q31_t)0x3a807bc7, (q31_t)0x3a7ae50a, (q31_t)0x3a754e2a, (q31_t)0x3a6fb726, + (q31_t)0x3a6a1ffd, (q31_t)0x3a6488b1, (q31_t)0x3a5ef140, (q31_t)0x3a5959ab, (q31_t)0x3a53c1f3, (q31_t)0x3a4e2a16, (q31_t)0x3a489216, (q31_t)0x3a42f9f2, + (q31_t)0x3a3d61a9, (q31_t)0x3a37c93d, (q31_t)0x3a3230ad, (q31_t)0x3a2c97f9, (q31_t)0x3a26ff21, (q31_t)0x3a216625, (q31_t)0x3a1bcd05, (q31_t)0x3a1633c1, + (q31_t)0x3a109a5a, (q31_t)0x3a0b00cf, (q31_t)0x3a056720, (q31_t)0x39ffcd4d, (q31_t)0x39fa3356, (q31_t)0x39f4993c, (q31_t)0x39eefefe, (q31_t)0x39e9649c, + (q31_t)0x39e3ca17, (q31_t)0x39de2f6d, (q31_t)0x39d894a0, (q31_t)0x39d2f9b0, (q31_t)0x39cd5e9b, (q31_t)0x39c7c363, (q31_t)0x39c22808, (q31_t)0x39bc8c89, + (q31_t)0x39b6f0e6, (q31_t)0x39b1551f, (q31_t)0x39abb935, (q31_t)0x39a61d28, (q31_t)0x39a080f6, (q31_t)0x399ae4a2, (q31_t)0x39954829, (q31_t)0x398fab8e, + (q31_t)0x398a0ece, (q31_t)0x398471ec, (q31_t)0x397ed4e5, (q31_t)0x397937bc, (q31_t)0x39739a6e, (q31_t)0x396dfcfe, (q31_t)0x39685f6a, (q31_t)0x3962c1b2, + (q31_t)0x395d23d7, (q31_t)0x395785d9, (q31_t)0x3951e7b8, (q31_t)0x394c4973, (q31_t)0x3946ab0a, (q31_t)0x39410c7f, (q31_t)0x393b6dd0, (q31_t)0x3935cefd, + (q31_t)0x39303008, (q31_t)0x392a90ef, (q31_t)0x3924f1b3, (q31_t)0x391f5254, (q31_t)0x3919b2d1, (q31_t)0x3914132b, (q31_t)0x390e7362, (q31_t)0x3908d376, + (q31_t)0x39033367, (q31_t)0x38fd9334, (q31_t)0x38f7f2de, (q31_t)0x38f25266, (q31_t)0x38ecb1ca, (q31_t)0x38e7110a, (q31_t)0x38e17028, (q31_t)0x38dbcf23, + (q31_t)0x38d62dfb, (q31_t)0x38d08caf, (q31_t)0x38caeb41, (q31_t)0x38c549af, (q31_t)0x38bfa7fb, (q31_t)0x38ba0623, (q31_t)0x38b46429, (q31_t)0x38aec20b, + (q31_t)0x38a91fcb, (q31_t)0x38a37d67, (q31_t)0x389ddae1, (q31_t)0x38983838, (q31_t)0x3892956c, (q31_t)0x388cf27d, (q31_t)0x38874f6b, (q31_t)0x3881ac36, + (q31_t)0x387c08de, (q31_t)0x38766564, (q31_t)0x3870c1c6, (q31_t)0x386b1e06, (q31_t)0x38657a23, (q31_t)0x385fd61d, (q31_t)0x385a31f5, (q31_t)0x38548daa, + (q31_t)0x384ee93b, (q31_t)0x384944ab, (q31_t)0x38439ff7, (q31_t)0x383dfb21, (q31_t)0x38385628, (q31_t)0x3832b10d, (q31_t)0x382d0bce, (q31_t)0x3827666d, + (q31_t)0x3821c0ea, (q31_t)0x381c1b44, (q31_t)0x3816757b, (q31_t)0x3810cf90, (q31_t)0x380b2982, (q31_t)0x38058351, (q31_t)0x37ffdcfe, (q31_t)0x37fa3688, + (q31_t)0x37f48ff0, (q31_t)0x37eee936, (q31_t)0x37e94259, (q31_t)0x37e39b59, (q31_t)0x37ddf437, (q31_t)0x37d84cf2, (q31_t)0x37d2a58b, (q31_t)0x37ccfe02, + (q31_t)0x37c75656, (q31_t)0x37c1ae87, (q31_t)0x37bc0697, (q31_t)0x37b65e84, (q31_t)0x37b0b64e, (q31_t)0x37ab0df6, (q31_t)0x37a5657c, (q31_t)0x379fbce0, + (q31_t)0x379a1421, (q31_t)0x37946b40, (q31_t)0x378ec23d, (q31_t)0x37891917, (q31_t)0x37836fcf, (q31_t)0x377dc665, (q31_t)0x37781cd9, (q31_t)0x3772732a, + (q31_t)0x376cc959, (q31_t)0x37671f66, (q31_t)0x37617551, (q31_t)0x375bcb1a, (q31_t)0x375620c1, (q31_t)0x37507645, (q31_t)0x374acba7, (q31_t)0x374520e7, + (q31_t)0x373f7606, (q31_t)0x3739cb02, (q31_t)0x37341fdc, (q31_t)0x372e7493, (q31_t)0x3728c929, (q31_t)0x37231d9d, (q31_t)0x371d71ef, (q31_t)0x3717c61f, + (q31_t)0x37121a2d, (q31_t)0x370c6e19, (q31_t)0x3706c1e2, (q31_t)0x3701158a, (q31_t)0x36fb6910, (q31_t)0x36f5bc75, (q31_t)0x36f00fb7, (q31_t)0x36ea62d7, + (q31_t)0x36e4b5d6, (q31_t)0x36df08b2, (q31_t)0x36d95b6d, (q31_t)0x36d3ae06, (q31_t)0x36ce007d, (q31_t)0x36c852d2, (q31_t)0x36c2a506, (q31_t)0x36bcf718, + (q31_t)0x36b74908, (q31_t)0x36b19ad6, (q31_t)0x36abec82, (q31_t)0x36a63e0d, (q31_t)0x36a08f76, (q31_t)0x369ae0bd, (q31_t)0x369531e3, (q31_t)0x368f82e7, + (q31_t)0x3689d3c9, (q31_t)0x3684248a, (q31_t)0x367e7529, (q31_t)0x3678c5a7, (q31_t)0x36731602, (q31_t)0x366d663d, (q31_t)0x3667b655, (q31_t)0x3662064c, + (q31_t)0x365c5622, (q31_t)0x3656a5d6, (q31_t)0x3650f569, (q31_t)0x364b44da, (q31_t)0x36459429, (q31_t)0x363fe357, (q31_t)0x363a3264, (q31_t)0x3634814f, + (q31_t)0x362ed019, (q31_t)0x36291ec1, (q31_t)0x36236d48, (q31_t)0x361dbbad, (q31_t)0x361809f1, (q31_t)0x36125814, (q31_t)0x360ca615, (q31_t)0x3606f3f5, + (q31_t)0x360141b4, (q31_t)0x35fb8f52, (q31_t)0x35f5dcce, (q31_t)0x35f02a28, (q31_t)0x35ea7762, (q31_t)0x35e4c47a, (q31_t)0x35df1171, (q31_t)0x35d95e47, + (q31_t)0x35d3aafc, (q31_t)0x35cdf78f, (q31_t)0x35c84401, (q31_t)0x35c29052, (q31_t)0x35bcdc82, (q31_t)0x35b72891, (q31_t)0x35b1747e, (q31_t)0x35abc04b, + (q31_t)0x35a60bf6, (q31_t)0x35a05781, (q31_t)0x359aa2ea, (q31_t)0x3594ee32, (q31_t)0x358f3959, (q31_t)0x3589845f, (q31_t)0x3583cf44, (q31_t)0x357e1a08, + (q31_t)0x357864ab, (q31_t)0x3572af2d, (q31_t)0x356cf98e, (q31_t)0x356743ce, (q31_t)0x35618ded, (q31_t)0x355bd7eb, (q31_t)0x355621c9, (q31_t)0x35506b85, + (q31_t)0x354ab520, (q31_t)0x3544fe9b, (q31_t)0x353f47f5, (q31_t)0x3539912e, (q31_t)0x3533da46, (q31_t)0x352e233d, (q31_t)0x35286c14, (q31_t)0x3522b4c9, + (q31_t)0x351cfd5e, (q31_t)0x351745d2, (q31_t)0x35118e26, (q31_t)0x350bd658, (q31_t)0x35061e6a, (q31_t)0x3500665c, (q31_t)0x34faae2c, (q31_t)0x34f4f5dc, + (q31_t)0x34ef3d6b, (q31_t)0x34e984da, (q31_t)0x34e3cc28, (q31_t)0x34de1355, (q31_t)0x34d85a62, (q31_t)0x34d2a14e, (q31_t)0x34cce819, (q31_t)0x34c72ec4, + (q31_t)0x34c1754e, (q31_t)0x34bbbbb8, (q31_t)0x34b60202, (q31_t)0x34b0482a, (q31_t)0x34aa8e33, (q31_t)0x34a4d41a, (q31_t)0x349f19e2, (q31_t)0x34995f88, + (q31_t)0x3493a50f, (q31_t)0x348dea75, (q31_t)0x34882fba, (q31_t)0x348274e0, (q31_t)0x347cb9e4, (q31_t)0x3476fec9, (q31_t)0x3471438d, (q31_t)0x346b8830, + (q31_t)0x3465ccb4, (q31_t)0x34601117, (q31_t)0x345a5559, (q31_t)0x3454997c, (q31_t)0x344edd7e, (q31_t)0x34492160, (q31_t)0x34436521, (q31_t)0x343da8c3, + (q31_t)0x3437ec44, (q31_t)0x34322fa5, (q31_t)0x342c72e6, (q31_t)0x3426b606, (q31_t)0x3420f907, (q31_t)0x341b3be7, (q31_t)0x34157ea7, (q31_t)0x340fc147, + (q31_t)0x340a03c7, (q31_t)0x34044626, (q31_t)0x33fe8866, (q31_t)0x33f8ca86, (q31_t)0x33f30c85, (q31_t)0x33ed4e65, (q31_t)0x33e79024, (q31_t)0x33e1d1c4, + (q31_t)0x33dc1343, (q31_t)0x33d654a2, (q31_t)0x33d095e2, (q31_t)0x33cad701, (q31_t)0x33c51801, (q31_t)0x33bf58e1, (q31_t)0x33b999a0, (q31_t)0x33b3da40, + (q31_t)0x33ae1ac0, (q31_t)0x33a85b20, (q31_t)0x33a29b60, (q31_t)0x339cdb81, (q31_t)0x33971b81, (q31_t)0x33915b62, (q31_t)0x338b9b22, (q31_t)0x3385dac4, + (q31_t)0x33801a45, (q31_t)0x337a59a6, (q31_t)0x337498e8, (q31_t)0x336ed80a, (q31_t)0x3369170c, (q31_t)0x336355ef, (q31_t)0x335d94b2, (q31_t)0x3357d355, + (q31_t)0x335211d8, (q31_t)0x334c503c, (q31_t)0x33468e80, (q31_t)0x3340cca5, (q31_t)0x333b0aaa, (q31_t)0x3335488f, (q31_t)0x332f8655, (q31_t)0x3329c3fb, + (q31_t)0x33240182, (q31_t)0x331e3ee9, (q31_t)0x33187c31, (q31_t)0x3312b959, (q31_t)0x330cf661, (q31_t)0x3307334a, (q31_t)0x33017014, (q31_t)0x32fbacbe, + (q31_t)0x32f5e948, (q31_t)0x32f025b4, (q31_t)0x32ea61ff, (q31_t)0x32e49e2c, (q31_t)0x32deda39, (q31_t)0x32d91626, (q31_t)0x32d351f5, (q31_t)0x32cd8da4, + (q31_t)0x32c7c933, (q31_t)0x32c204a3, (q31_t)0x32bc3ff4, (q31_t)0x32b67b26, (q31_t)0x32b0b638, (q31_t)0x32aaf12b, (q31_t)0x32a52bff, (q31_t)0x329f66b4, + (q31_t)0x3299a149, (q31_t)0x3293dbbf, (q31_t)0x328e1616, (q31_t)0x3288504e, (q31_t)0x32828a67, (q31_t)0x327cc460, (q31_t)0x3276fe3a, (q31_t)0x327137f6, + (q31_t)0x326b7192, (q31_t)0x3265ab0f, (q31_t)0x325fe46c, (q31_t)0x325a1dab, (q31_t)0x325456cb, (q31_t)0x324e8fcc, (q31_t)0x3248c8ad, (q31_t)0x32430170, + (q31_t)0x323d3a14, (q31_t)0x32377298, (q31_t)0x3231aafe, (q31_t)0x322be345, (q31_t)0x32261b6c, (q31_t)0x32205375, (q31_t)0x321a8b5f, (q31_t)0x3214c32a, + (q31_t)0x320efad6, (q31_t)0x32093263, (q31_t)0x320369d2, (q31_t)0x31fda121, (q31_t)0x31f7d852, (q31_t)0x31f20f64, (q31_t)0x31ec4657, (q31_t)0x31e67d2b, + (q31_t)0x31e0b3e0, (q31_t)0x31daea77, (q31_t)0x31d520ef, (q31_t)0x31cf5748, (q31_t)0x31c98d83, (q31_t)0x31c3c39e, (q31_t)0x31bdf99b, (q31_t)0x31b82f7a, + (q31_t)0x31b2653a, (q31_t)0x31ac9adb, (q31_t)0x31a6d05d, (q31_t)0x31a105c1, (q31_t)0x319b3b06, (q31_t)0x3195702d, (q31_t)0x318fa535, (q31_t)0x3189da1e, + (q31_t)0x31840ee9, (q31_t)0x317e4395, (q31_t)0x31787823, (q31_t)0x3172ac92, (q31_t)0x316ce0e3, (q31_t)0x31671515, (q31_t)0x31614929, (q31_t)0x315b7d1e, + (q31_t)0x3155b0f5, (q31_t)0x314fe4ae, (q31_t)0x314a1848, (q31_t)0x31444bc3, (q31_t)0x313e7f21, (q31_t)0x3138b260, (q31_t)0x3132e580, (q31_t)0x312d1882, + (q31_t)0x31274b66, (q31_t)0x31217e2c, (q31_t)0x311bb0d3, (q31_t)0x3115e35c, (q31_t)0x311015c6, (q31_t)0x310a4813, (q31_t)0x31047a41, (q31_t)0x30feac51, + (q31_t)0x30f8de42, (q31_t)0x30f31016, (q31_t)0x30ed41cb, (q31_t)0x30e77362, (q31_t)0x30e1a4db, (q31_t)0x30dbd636, (q31_t)0x30d60772, (q31_t)0x30d03891, + (q31_t)0x30ca6991, (q31_t)0x30c49a74, (q31_t)0x30becb38, (q31_t)0x30b8fbde, (q31_t)0x30b32c66, (q31_t)0x30ad5cd0, (q31_t)0x30a78d1c, (q31_t)0x30a1bd4a, + (q31_t)0x309bed5a, (q31_t)0x30961d4c, (q31_t)0x30904d20, (q31_t)0x308a7cd6, (q31_t)0x3084ac6e, (q31_t)0x307edbe9, (q31_t)0x30790b45, (q31_t)0x30733a83, + (q31_t)0x306d69a4, (q31_t)0x306798a7, (q31_t)0x3061c78b, (q31_t)0x305bf652, (q31_t)0x305624fb, (q31_t)0x30505387, (q31_t)0x304a81f4, (q31_t)0x3044b044, + (q31_t)0x303ede76, (q31_t)0x30390c8a, (q31_t)0x30333a80, (q31_t)0x302d6859, (q31_t)0x30279614, (q31_t)0x3021c3b1, (q31_t)0x301bf131, (q31_t)0x30161e93, + (q31_t)0x30104bd7, (q31_t)0x300a78fe, (q31_t)0x3004a607, (q31_t)0x2ffed2f2, (q31_t)0x2ff8ffc0, (q31_t)0x2ff32c70, (q31_t)0x2fed5902, (q31_t)0x2fe78577, + (q31_t)0x2fe1b1cf, (q31_t)0x2fdbde09, (q31_t)0x2fd60a25, (q31_t)0x2fd03624, (q31_t)0x2fca6206, (q31_t)0x2fc48dc9, (q31_t)0x2fbeb970, (q31_t)0x2fb8e4f9, + (q31_t)0x2fb31064, (q31_t)0x2fad3bb3, (q31_t)0x2fa766e3, (q31_t)0x2fa191f7, (q31_t)0x2f9bbced, (q31_t)0x2f95e7c5, (q31_t)0x2f901280, (q31_t)0x2f8a3d1e, + (q31_t)0x2f84679f, (q31_t)0x2f7e9202, (q31_t)0x2f78bc48, (q31_t)0x2f72e671, (q31_t)0x2f6d107c, (q31_t)0x2f673a6a, (q31_t)0x2f61643b, (q31_t)0x2f5b8def, + (q31_t)0x2f55b785, (q31_t)0x2f4fe0ff, (q31_t)0x2f4a0a5b, (q31_t)0x2f44339a, (q31_t)0x2f3e5cbb, (q31_t)0x2f3885c0, (q31_t)0x2f32aea8, (q31_t)0x2f2cd772, + (q31_t)0x2f27001f, (q31_t)0x2f2128af, (q31_t)0x2f1b5122, (q31_t)0x2f157979, (q31_t)0x2f0fa1b2, (q31_t)0x2f09c9ce, (q31_t)0x2f03f1cd, (q31_t)0x2efe19ae, + (q31_t)0x2ef84173, (q31_t)0x2ef2691b, (q31_t)0x2eec90a7, (q31_t)0x2ee6b815, (q31_t)0x2ee0df66, (q31_t)0x2edb069a, (q31_t)0x2ed52db1, (q31_t)0x2ecf54ac, + (q31_t)0x2ec97b89, (q31_t)0x2ec3a24a, (q31_t)0x2ebdc8ee, (q31_t)0x2eb7ef75, (q31_t)0x2eb215df, (q31_t)0x2eac3c2d, (q31_t)0x2ea6625d, (q31_t)0x2ea08871, + (q31_t)0x2e9aae68, (q31_t)0x2e94d443, (q31_t)0x2e8efa00, (q31_t)0x2e891fa1, (q31_t)0x2e834525, (q31_t)0x2e7d6a8d, (q31_t)0x2e778fd8, (q31_t)0x2e71b506, + (q31_t)0x2e6bda17, (q31_t)0x2e65ff0c, (q31_t)0x2e6023e5, (q31_t)0x2e5a48a0, (q31_t)0x2e546d3f, (q31_t)0x2e4e91c2, (q31_t)0x2e48b628, (q31_t)0x2e42da71, + (q31_t)0x2e3cfe9e, (q31_t)0x2e3722ae, (q31_t)0x2e3146a2, (q31_t)0x2e2b6a79, (q31_t)0x2e258e34, (q31_t)0x2e1fb1d3, (q31_t)0x2e19d554, (q31_t)0x2e13f8ba, + (q31_t)0x2e0e1c03, (q31_t)0x2e083f30, (q31_t)0x2e026240, (q31_t)0x2dfc8534, (q31_t)0x2df6a80b, (q31_t)0x2df0cac6, (q31_t)0x2deaed65, (q31_t)0x2de50fe8, + (q31_t)0x2ddf324e, (q31_t)0x2dd95498, (q31_t)0x2dd376c5, (q31_t)0x2dcd98d7, (q31_t)0x2dc7bacc, (q31_t)0x2dc1dca4, (q31_t)0x2dbbfe61, (q31_t)0x2db62001, + (q31_t)0x2db04186, (q31_t)0x2daa62ee, (q31_t)0x2da4843a, (q31_t)0x2d9ea569, (q31_t)0x2d98c67d, (q31_t)0x2d92e774, (q31_t)0x2d8d084f, (q31_t)0x2d87290f, + (q31_t)0x2d8149b2, (q31_t)0x2d7b6a39, (q31_t)0x2d758aa4, (q31_t)0x2d6faaf3, (q31_t)0x2d69cb26, (q31_t)0x2d63eb3d, (q31_t)0x2d5e0b38, (q31_t)0x2d582b17, + (q31_t)0x2d524ada, (q31_t)0x2d4c6a81, (q31_t)0x2d468a0c, (q31_t)0x2d40a97b, (q31_t)0x2d3ac8ce, (q31_t)0x2d34e805, (q31_t)0x2d2f0721, (q31_t)0x2d292620, + (q31_t)0x2d234504, (q31_t)0x2d1d63cc, (q31_t)0x2d178278, (q31_t)0x2d11a108, (q31_t)0x2d0bbf7d, (q31_t)0x2d05ddd5, (q31_t)0x2cfffc12, (q31_t)0x2cfa1a33, + (q31_t)0x2cf43839, (q31_t)0x2cee5622, (q31_t)0x2ce873f0, (q31_t)0x2ce291a2, (q31_t)0x2cdcaf39, (q31_t)0x2cd6ccb4, (q31_t)0x2cd0ea13, (q31_t)0x2ccb0756, + (q31_t)0x2cc5247e, (q31_t)0x2cbf418b, (q31_t)0x2cb95e7b, (q31_t)0x2cb37b51, (q31_t)0x2cad980a, (q31_t)0x2ca7b4a8, (q31_t)0x2ca1d12a, (q31_t)0x2c9bed91, + (q31_t)0x2c9609dd, (q31_t)0x2c90260d, (q31_t)0x2c8a4221, (q31_t)0x2c845e1a, (q31_t)0x2c7e79f7, (q31_t)0x2c7895b9, (q31_t)0x2c72b160, (q31_t)0x2c6ccceb, + (q31_t)0x2c66e85b, (q31_t)0x2c6103af, (q31_t)0x2c5b1ee8, (q31_t)0x2c553a06, (q31_t)0x2c4f5508, (q31_t)0x2c496fef, (q31_t)0x2c438abb, (q31_t)0x2c3da56b, + (q31_t)0x2c37c000, (q31_t)0x2c31da7a, (q31_t)0x2c2bf4d8, (q31_t)0x2c260f1c, (q31_t)0x2c202944, (q31_t)0x2c1a4351, (q31_t)0x2c145d42, (q31_t)0x2c0e7719, + (q31_t)0x2c0890d4, (q31_t)0x2c02aa74, (q31_t)0x2bfcc3f9, (q31_t)0x2bf6dd63, (q31_t)0x2bf0f6b1, (q31_t)0x2beb0fe5, (q31_t)0x2be528fd, (q31_t)0x2bdf41fb, + (q31_t)0x2bd95add, (q31_t)0x2bd373a4, (q31_t)0x2bcd8c51, (q31_t)0x2bc7a4e2, (q31_t)0x2bc1bd58, (q31_t)0x2bbbd5b3, (q31_t)0x2bb5edf4, (q31_t)0x2bb00619, + (q31_t)0x2baa1e23, (q31_t)0x2ba43613, (q31_t)0x2b9e4de7, (q31_t)0x2b9865a1, (q31_t)0x2b927d3f, (q31_t)0x2b8c94c3, (q31_t)0x2b86ac2c, (q31_t)0x2b80c37a, + (q31_t)0x2b7adaae, (q31_t)0x2b74f1c6, (q31_t)0x2b6f08c4, (q31_t)0x2b691fa6, (q31_t)0x2b63366f, (q31_t)0x2b5d4d1c, (q31_t)0x2b5763ae, (q31_t)0x2b517a26, + (q31_t)0x2b4b9083, (q31_t)0x2b45a6c6, (q31_t)0x2b3fbced, (q31_t)0x2b39d2fa, (q31_t)0x2b33e8ed, (q31_t)0x2b2dfec5, (q31_t)0x2b281482, (q31_t)0x2b222a24, + (q31_t)0x2b1c3fac, (q31_t)0x2b165519, (q31_t)0x2b106a6c, (q31_t)0x2b0a7fa4, (q31_t)0x2b0494c2, (q31_t)0x2afea9c5, (q31_t)0x2af8bead, (q31_t)0x2af2d37b, + (q31_t)0x2aece82f, (q31_t)0x2ae6fcc8, (q31_t)0x2ae11146, (q31_t)0x2adb25aa, (q31_t)0x2ad539f4, (q31_t)0x2acf4e23, (q31_t)0x2ac96238, (q31_t)0x2ac37633, + (q31_t)0x2abd8a13, (q31_t)0x2ab79dd8, (q31_t)0x2ab1b184, (q31_t)0x2aabc515, (q31_t)0x2aa5d88b, (q31_t)0x2a9febe8, (q31_t)0x2a99ff2a, (q31_t)0x2a941252, + (q31_t)0x2a8e255f, (q31_t)0x2a883853, (q31_t)0x2a824b2c, (q31_t)0x2a7c5deb, (q31_t)0x2a76708f, (q31_t)0x2a70831a, (q31_t)0x2a6a958a, (q31_t)0x2a64a7e0, + (q31_t)0x2a5eba1c, (q31_t)0x2a58cc3e, (q31_t)0x2a52de46, (q31_t)0x2a4cf033, (q31_t)0x2a470207, (q31_t)0x2a4113c0, (q31_t)0x2a3b2560, (q31_t)0x2a3536e5, + (q31_t)0x2a2f4850, (q31_t)0x2a2959a1, (q31_t)0x2a236ad9, (q31_t)0x2a1d7bf6, (q31_t)0x2a178cf9, (q31_t)0x2a119de2, (q31_t)0x2a0baeb2, (q31_t)0x2a05bf67, + (q31_t)0x29ffd003, (q31_t)0x29f9e084, (q31_t)0x29f3f0ec, (q31_t)0x29ee013a, (q31_t)0x29e8116e, (q31_t)0x29e22188, (q31_t)0x29dc3188, (q31_t)0x29d6416f, + (q31_t)0x29d0513b, (q31_t)0x29ca60ee, (q31_t)0x29c47087, (q31_t)0x29be8007, (q31_t)0x29b88f6c, (q31_t)0x29b29eb8, (q31_t)0x29acadea, (q31_t)0x29a6bd02, + (q31_t)0x29a0cc01, (q31_t)0x299adae6, (q31_t)0x2994e9b1, (q31_t)0x298ef863, (q31_t)0x298906fb, (q31_t)0x2983157a, (q31_t)0x297d23df, (q31_t)0x2977322a, + (q31_t)0x2971405b, (q31_t)0x296b4e74, (q31_t)0x29655c72, (q31_t)0x295f6a57, (q31_t)0x29597823, (q31_t)0x295385d5, (q31_t)0x294d936d, (q31_t)0x2947a0ec, + (q31_t)0x2941ae52, (q31_t)0x293bbb9e, (q31_t)0x2935c8d1, (q31_t)0x292fd5ea, (q31_t)0x2929e2ea, (q31_t)0x2923efd0, (q31_t)0x291dfc9d, (q31_t)0x29180951, + (q31_t)0x291215eb, (q31_t)0x290c226c, (q31_t)0x29062ed4, (q31_t)0x29003b23, (q31_t)0x28fa4758, (q31_t)0x28f45374, (q31_t)0x28ee5f76, (q31_t)0x28e86b5f, + (q31_t)0x28e27730, (q31_t)0x28dc82e6, (q31_t)0x28d68e84, (q31_t)0x28d09a09, (q31_t)0x28caa574, (q31_t)0x28c4b0c6, (q31_t)0x28bebbff, (q31_t)0x28b8c71f, + (q31_t)0x28b2d226, (q31_t)0x28acdd13, (q31_t)0x28a6e7e8, (q31_t)0x28a0f2a3, (q31_t)0x289afd46, (q31_t)0x289507cf, (q31_t)0x288f123f, (q31_t)0x28891c97, + (q31_t)0x288326d5, (q31_t)0x287d30fa, (q31_t)0x28773b07, (q31_t)0x287144fa, (q31_t)0x286b4ed5, (q31_t)0x28655896, (q31_t)0x285f623f, (q31_t)0x28596bce, + (q31_t)0x28537545, (q31_t)0x284d7ea3, (q31_t)0x284787e8, (q31_t)0x28419114, (q31_t)0x283b9a28, (q31_t)0x2835a322, (q31_t)0x282fac04, (q31_t)0x2829b4cd, + (q31_t)0x2823bd7d, (q31_t)0x281dc615, (q31_t)0x2817ce93, (q31_t)0x2811d6f9, (q31_t)0x280bdf46, (q31_t)0x2805e77b, (q31_t)0x27ffef97, (q31_t)0x27f9f79a, + (q31_t)0x27f3ff85, (q31_t)0x27ee0756, (q31_t)0x27e80f10, (q31_t)0x27e216b0, (q31_t)0x27dc1e38, (q31_t)0x27d625a8, (q31_t)0x27d02cff, (q31_t)0x27ca343d, + (q31_t)0x27c43b63, (q31_t)0x27be4270, (q31_t)0x27b84965, (q31_t)0x27b25041, (q31_t)0x27ac5705, (q31_t)0x27a65db0, (q31_t)0x27a06443, (q31_t)0x279a6abd, + (q31_t)0x2794711f, (q31_t)0x278e7768, (q31_t)0x27887d99, (q31_t)0x278283b2, (q31_t)0x277c89b3, (q31_t)0x27768f9b, (q31_t)0x2770956a, (q31_t)0x276a9b21, + (q31_t)0x2764a0c0, (q31_t)0x275ea647, (q31_t)0x2758abb6, (q31_t)0x2752b10c, (q31_t)0x274cb64a, (q31_t)0x2746bb6f, (q31_t)0x2740c07d, (q31_t)0x273ac572, + (q31_t)0x2734ca4f, (q31_t)0x272ecf14, (q31_t)0x2728d3c0, (q31_t)0x2722d855, (q31_t)0x271cdcd1, (q31_t)0x2716e136, (q31_t)0x2710e582, (q31_t)0x270ae9b6, + (q31_t)0x2704edd2, (q31_t)0x26fef1d5, (q31_t)0x26f8f5c1, (q31_t)0x26f2f995, (q31_t)0x26ecfd51, (q31_t)0x26e700f5, (q31_t)0x26e10480, (q31_t)0x26db07f4, + (q31_t)0x26d50b50, (q31_t)0x26cf0e94, (q31_t)0x26c911c0, (q31_t)0x26c314d4, (q31_t)0x26bd17d0, (q31_t)0x26b71ab4, (q31_t)0x26b11d80, (q31_t)0x26ab2034, + (q31_t)0x26a522d1, (q31_t)0x269f2556, (q31_t)0x269927c3, (q31_t)0x26932a18, (q31_t)0x268d2c55, (q31_t)0x26872e7b, (q31_t)0x26813088, (q31_t)0x267b327e, + (q31_t)0x2675345d, (q31_t)0x266f3623, (q31_t)0x266937d2, (q31_t)0x26633969, (q31_t)0x265d3ae9, (q31_t)0x26573c50, (q31_t)0x26513da1, (q31_t)0x264b3ed9, + (q31_t)0x26453ffa, (q31_t)0x263f4103, (q31_t)0x263941f5, (q31_t)0x263342cf, (q31_t)0x262d4392, (q31_t)0x2627443d, (q31_t)0x262144d0, (q31_t)0x261b454c, + (q31_t)0x261545b0, (q31_t)0x260f45fd, (q31_t)0x26094633, (q31_t)0x26034651, (q31_t)0x25fd4657, (q31_t)0x25f74646, (q31_t)0x25f1461e, (q31_t)0x25eb45de, + (q31_t)0x25e54587, (q31_t)0x25df4519, (q31_t)0x25d94493, (q31_t)0x25d343f6, (q31_t)0x25cd4341, (q31_t)0x25c74276, (q31_t)0x25c14192, (q31_t)0x25bb4098, + (q31_t)0x25b53f86, (q31_t)0x25af3e5d, (q31_t)0x25a93d1d, (q31_t)0x25a33bc6, (q31_t)0x259d3a57, (q31_t)0x259738d1, (q31_t)0x25913734, (q31_t)0x258b3580, + (q31_t)0x258533b5, (q31_t)0x257f31d2, (q31_t)0x25792fd8, (q31_t)0x25732dc8, (q31_t)0x256d2ba0, (q31_t)0x25672961, (q31_t)0x2561270b, (q31_t)0x255b249e, + (q31_t)0x2555221a, (q31_t)0x254f1f7e, (q31_t)0x25491ccc, (q31_t)0x25431a03, (q31_t)0x253d1723, (q31_t)0x2537142c, (q31_t)0x2531111e, (q31_t)0x252b0df9, + (q31_t)0x25250abd, (q31_t)0x251f076a, (q31_t)0x25190400, (q31_t)0x25130080, (q31_t)0x250cfce8, (q31_t)0x2506f93a, (q31_t)0x2500f574, (q31_t)0x24faf198, + (q31_t)0x24f4eda6, (q31_t)0x24eee99c, (q31_t)0x24e8e57c, (q31_t)0x24e2e144, (q31_t)0x24dcdcf6, (q31_t)0x24d6d892, (q31_t)0x24d0d416, (q31_t)0x24cacf84, + (q31_t)0x24c4cadb, (q31_t)0x24bec61c, (q31_t)0x24b8c146, (q31_t)0x24b2bc59, (q31_t)0x24acb756, (q31_t)0x24a6b23b, (q31_t)0x24a0ad0b, (q31_t)0x249aa7c4, + (q31_t)0x2494a266, (q31_t)0x248e9cf1, (q31_t)0x24889766, (q31_t)0x248291c5, (q31_t)0x247c8c0d, (q31_t)0x2476863e, (q31_t)0x24708059, (q31_t)0x246a7a5e, + (q31_t)0x2464744c, (q31_t)0x245e6e23, (q31_t)0x245867e4, (q31_t)0x2452618f, (q31_t)0x244c5b24, (q31_t)0x244654a1, (q31_t)0x24404e09, (q31_t)0x243a475a, + (q31_t)0x24344095, (q31_t)0x242e39ba, (q31_t)0x242832c8, (q31_t)0x24222bc0, (q31_t)0x241c24a1, (q31_t)0x24161d6d, (q31_t)0x24101622, (q31_t)0x240a0ec1, + (q31_t)0x24040749, (q31_t)0x23fdffbc, (q31_t)0x23f7f818, (q31_t)0x23f1f05e, (q31_t)0x23ebe88e, (q31_t)0x23e5e0a7, (q31_t)0x23dfd8ab, (q31_t)0x23d9d098, + (q31_t)0x23d3c86f, (q31_t)0x23cdc031, (q31_t)0x23c7b7dc, (q31_t)0x23c1af71, (q31_t)0x23bba6f0, (q31_t)0x23b59e59, (q31_t)0x23af95ac, (q31_t)0x23a98ce8, + (q31_t)0x23a3840f, (q31_t)0x239d7b20, (q31_t)0x2397721b, (q31_t)0x23916900, (q31_t)0x238b5fcf, (q31_t)0x23855688, (q31_t)0x237f4d2b, (q31_t)0x237943b9, + (q31_t)0x23733a30, (q31_t)0x236d3092, (q31_t)0x236726dd, (q31_t)0x23611d13, (q31_t)0x235b1333, (q31_t)0x2355093e, (q31_t)0x234eff32, (q31_t)0x2348f511, + (q31_t)0x2342eada, (q31_t)0x233ce08d, (q31_t)0x2336d62a, (q31_t)0x2330cbb2, (q31_t)0x232ac124, (q31_t)0x2324b680, (q31_t)0x231eabc7, (q31_t)0x2318a0f8, + (q31_t)0x23129613, (q31_t)0x230c8b19, (q31_t)0x23068009, (q31_t)0x230074e3, (q31_t)0x22fa69a8, (q31_t)0x22f45e57, (q31_t)0x22ee52f1, (q31_t)0x22e84775, + (q31_t)0x22e23be4, (q31_t)0x22dc303d, (q31_t)0x22d62480, (q31_t)0x22d018ae, (q31_t)0x22ca0cc7, (q31_t)0x22c400ca, (q31_t)0x22bdf4b8, (q31_t)0x22b7e890, + (q31_t)0x22b1dc53, (q31_t)0x22abd001, (q31_t)0x22a5c399, (q31_t)0x229fb71b, (q31_t)0x2299aa89, (q31_t)0x22939de1, (q31_t)0x228d9123, (q31_t)0x22878451, + (q31_t)0x22817769, (q31_t)0x227b6a6c, (q31_t)0x22755d59, (q31_t)0x226f5032, (q31_t)0x226942f5, (q31_t)0x226335a2, (q31_t)0x225d283b, (q31_t)0x22571abe, + (q31_t)0x22510d2d, (q31_t)0x224aff86, (q31_t)0x2244f1c9, (q31_t)0x223ee3f8, (q31_t)0x2238d612, (q31_t)0x2232c816, (q31_t)0x222cba06, (q31_t)0x2226abe0, + (q31_t)0x22209da5, (q31_t)0x221a8f56, (q31_t)0x221480f1, (q31_t)0x220e7277, (q31_t)0x220863e8, (q31_t)0x22025544, (q31_t)0x21fc468b, (q31_t)0x21f637be, + (q31_t)0x21f028db, (q31_t)0x21ea19e3, (q31_t)0x21e40ad7, (q31_t)0x21ddfbb5, (q31_t)0x21d7ec7f, (q31_t)0x21d1dd34, (q31_t)0x21cbcdd3, (q31_t)0x21c5be5e, + (q31_t)0x21bfaed5, (q31_t)0x21b99f36, (q31_t)0x21b38f83, (q31_t)0x21ad7fba, (q31_t)0x21a76fdd, (q31_t)0x21a15fec, (q31_t)0x219b4fe5, (q31_t)0x21953fca, + (q31_t)0x218f2f9a, (q31_t)0x21891f55, (q31_t)0x21830efc, (q31_t)0x217cfe8e, (q31_t)0x2176ee0b, (q31_t)0x2170dd74, (q31_t)0x216accc8, (q31_t)0x2164bc08, + (q31_t)0x215eab33, (q31_t)0x21589a49, (q31_t)0x2152894b, (q31_t)0x214c7838, (q31_t)0x21466710, (q31_t)0x214055d4, (q31_t)0x213a4484, (q31_t)0x2134331f, + (q31_t)0x212e21a6, (q31_t)0x21281018, (q31_t)0x2121fe76, (q31_t)0x211becbf, (q31_t)0x2115daf4, (q31_t)0x210fc914, (q31_t)0x2109b720, (q31_t)0x2103a518, + (q31_t)0x20fd92fb, (q31_t)0x20f780ca, (q31_t)0x20f16e84, (q31_t)0x20eb5c2b, (q31_t)0x20e549bd, (q31_t)0x20df373a, (q31_t)0x20d924a4, (q31_t)0x20d311f9, + (q31_t)0x20ccff3a, (q31_t)0x20c6ec66, (q31_t)0x20c0d97f, (q31_t)0x20bac683, (q31_t)0x20b4b373, (q31_t)0x20aea04f, (q31_t)0x20a88d17, (q31_t)0x20a279ca, + (q31_t)0x209c666a, (q31_t)0x209652f5, (q31_t)0x20903f6c, (q31_t)0x208a2bcf, (q31_t)0x2084181e, (q31_t)0x207e0459, (q31_t)0x2077f080, (q31_t)0x2071dc93, + (q31_t)0x206bc892, (q31_t)0x2065b47d, (q31_t)0x205fa054, (q31_t)0x20598c17, (q31_t)0x205377c6, (q31_t)0x204d6361, (q31_t)0x20474ee8, (q31_t)0x20413a5b, + (q31_t)0x203b25bb, (q31_t)0x20351106, (q31_t)0x202efc3e, (q31_t)0x2028e761, (q31_t)0x2022d271, (q31_t)0x201cbd6d, (q31_t)0x2016a856, (q31_t)0x2010932a, + (q31_t)0x200a7deb, (q31_t)0x20046898, (q31_t)0x1ffe5331, (q31_t)0x1ff83db6, (q31_t)0x1ff22828, (q31_t)0x1fec1286, (q31_t)0x1fe5fcd0, (q31_t)0x1fdfe707, + (q31_t)0x1fd9d12a, (q31_t)0x1fd3bb39, (q31_t)0x1fcda535, (q31_t)0x1fc78f1d, (q31_t)0x1fc178f1, (q31_t)0x1fbb62b2, (q31_t)0x1fb54c60, (q31_t)0x1faf35f9, + (q31_t)0x1fa91f80, (q31_t)0x1fa308f2, (q31_t)0x1f9cf252, (q31_t)0x1f96db9d, (q31_t)0x1f90c4d5, (q31_t)0x1f8aadfa, (q31_t)0x1f84970b, (q31_t)0x1f7e8009, + (q31_t)0x1f7868f4, (q31_t)0x1f7251ca, (q31_t)0x1f6c3a8e, (q31_t)0x1f66233e, (q31_t)0x1f600bdb, (q31_t)0x1f59f465, (q31_t)0x1f53dcdb, (q31_t)0x1f4dc53d, + (q31_t)0x1f47ad8d, (q31_t)0x1f4195c9, (q31_t)0x1f3b7df2, (q31_t)0x1f356608, (q31_t)0x1f2f4e0a, (q31_t)0x1f2935f9, (q31_t)0x1f231dd5, (q31_t)0x1f1d059e, + (q31_t)0x1f16ed54, (q31_t)0x1f10d4f6, (q31_t)0x1f0abc85, (q31_t)0x1f04a401, (q31_t)0x1efe8b6a, (q31_t)0x1ef872c0, (q31_t)0x1ef25a03, (q31_t)0x1eec4132, + (q31_t)0x1ee6284f, (q31_t)0x1ee00f58, (q31_t)0x1ed9f64f, (q31_t)0x1ed3dd32, (q31_t)0x1ecdc402, (q31_t)0x1ec7aac0, (q31_t)0x1ec1916a, (q31_t)0x1ebb7802, + (q31_t)0x1eb55e86, (q31_t)0x1eaf44f8, (q31_t)0x1ea92b56, (q31_t)0x1ea311a2, (q31_t)0x1e9cf7db, (q31_t)0x1e96de01, (q31_t)0x1e90c414, (q31_t)0x1e8aaa14, + (q31_t)0x1e849001, (q31_t)0x1e7e75dc, (q31_t)0x1e785ba3, (q31_t)0x1e724158, (q31_t)0x1e6c26fa, (q31_t)0x1e660c8a, (q31_t)0x1e5ff206, (q31_t)0x1e59d770, + (q31_t)0x1e53bcc7, (q31_t)0x1e4da20c, (q31_t)0x1e47873d, (q31_t)0x1e416c5d, (q31_t)0x1e3b5169, (q31_t)0x1e353663, (q31_t)0x1e2f1b4a, (q31_t)0x1e29001e, + (q31_t)0x1e22e4e0, (q31_t)0x1e1cc990, (q31_t)0x1e16ae2c, (q31_t)0x1e1092b6, (q31_t)0x1e0a772e, (q31_t)0x1e045b93, (q31_t)0x1dfe3fe6, (q31_t)0x1df82426, + (q31_t)0x1df20853, (q31_t)0x1debec6f, (q31_t)0x1de5d077, (q31_t)0x1ddfb46e, (q31_t)0x1dd99851, (q31_t)0x1dd37c23, (q31_t)0x1dcd5fe2, (q31_t)0x1dc7438e, + (q31_t)0x1dc12729, (q31_t)0x1dbb0ab0, (q31_t)0x1db4ee26, (q31_t)0x1daed189, (q31_t)0x1da8b4da, (q31_t)0x1da29819, (q31_t)0x1d9c7b45, (q31_t)0x1d965e5f, + (q31_t)0x1d904167, (q31_t)0x1d8a245c, (q31_t)0x1d840740, (q31_t)0x1d7dea11, (q31_t)0x1d77ccd0, (q31_t)0x1d71af7d, (q31_t)0x1d6b9217, (q31_t)0x1d6574a0, + (q31_t)0x1d5f5716, (q31_t)0x1d59397a, (q31_t)0x1d531bcc, (q31_t)0x1d4cfe0d, (q31_t)0x1d46e03a, (q31_t)0x1d40c256, (q31_t)0x1d3aa460, (q31_t)0x1d348658, + (q31_t)0x1d2e683e, (q31_t)0x1d284a12, (q31_t)0x1d222bd3, (q31_t)0x1d1c0d83, (q31_t)0x1d15ef21, (q31_t)0x1d0fd0ad, (q31_t)0x1d09b227, (q31_t)0x1d03938f, + (q31_t)0x1cfd74e5, (q31_t)0x1cf7562a, (q31_t)0x1cf1375c, (q31_t)0x1ceb187d, (q31_t)0x1ce4f98c, (q31_t)0x1cdeda89, (q31_t)0x1cd8bb74, (q31_t)0x1cd29c4d, + (q31_t)0x1ccc7d15, (q31_t)0x1cc65dca, (q31_t)0x1cc03e6e, (q31_t)0x1cba1f01, (q31_t)0x1cb3ff81, (q31_t)0x1caddff0, (q31_t)0x1ca7c04d, (q31_t)0x1ca1a099, + (q31_t)0x1c9b80d3, (q31_t)0x1c9560fb, (q31_t)0x1c8f4112, (q31_t)0x1c892117, (q31_t)0x1c83010a, (q31_t)0x1c7ce0ec, (q31_t)0x1c76c0bc, (q31_t)0x1c70a07b, + (q31_t)0x1c6a8028, (q31_t)0x1c645fc3, (q31_t)0x1c5e3f4d, (q31_t)0x1c581ec6, (q31_t)0x1c51fe2d, (q31_t)0x1c4bdd83, (q31_t)0x1c45bcc7, (q31_t)0x1c3f9bf9, + (q31_t)0x1c397b1b, (q31_t)0x1c335a2b, (q31_t)0x1c2d3929, (q31_t)0x1c271816, (q31_t)0x1c20f6f2, (q31_t)0x1c1ad5bc, (q31_t)0x1c14b475, (q31_t)0x1c0e931d, + (q31_t)0x1c0871b4, (q31_t)0x1c025039, (q31_t)0x1bfc2ead, (q31_t)0x1bf60d0f, (q31_t)0x1befeb60, (q31_t)0x1be9c9a1, (q31_t)0x1be3a7cf, (q31_t)0x1bdd85ed, + (q31_t)0x1bd763fa, (q31_t)0x1bd141f5, (q31_t)0x1bcb1fdf, (q31_t)0x1bc4fdb8, (q31_t)0x1bbedb80, (q31_t)0x1bb8b937, (q31_t)0x1bb296dc, (q31_t)0x1bac7471, + (q31_t)0x1ba651f5, (q31_t)0x1ba02f67, (q31_t)0x1b9a0cc8, (q31_t)0x1b93ea19, (q31_t)0x1b8dc758, (q31_t)0x1b87a487, (q31_t)0x1b8181a4, (q31_t)0x1b7b5eb0, + (q31_t)0x1b753bac, (q31_t)0x1b6f1897, (q31_t)0x1b68f570, (q31_t)0x1b62d239, (q31_t)0x1b5caef1, (q31_t)0x1b568b98, (q31_t)0x1b50682e, (q31_t)0x1b4a44b3, + (q31_t)0x1b442127, (q31_t)0x1b3dfd8b, (q31_t)0x1b37d9de, (q31_t)0x1b31b620, (q31_t)0x1b2b9251, (q31_t)0x1b256e71, (q31_t)0x1b1f4a81, (q31_t)0x1b192680, + (q31_t)0x1b13026e, (q31_t)0x1b0cde4c, (q31_t)0x1b06ba19, (q31_t)0x1b0095d5, (q31_t)0x1afa7180, (q31_t)0x1af44d1b, (q31_t)0x1aee28a6, (q31_t)0x1ae8041f, + (q31_t)0x1ae1df88, (q31_t)0x1adbbae1, (q31_t)0x1ad59629, (q31_t)0x1acf7160, (q31_t)0x1ac94c87, (q31_t)0x1ac3279d, (q31_t)0x1abd02a3, (q31_t)0x1ab6dd98, + (q31_t)0x1ab0b87d, (q31_t)0x1aaa9352, (q31_t)0x1aa46e16, (q31_t)0x1a9e48c9, (q31_t)0x1a98236c, (q31_t)0x1a91fdff, (q31_t)0x1a8bd881, (q31_t)0x1a85b2f3, + (q31_t)0x1a7f8d54, (q31_t)0x1a7967a6, (q31_t)0x1a7341e6, (q31_t)0x1a6d1c17, (q31_t)0x1a66f637, (q31_t)0x1a60d047, (q31_t)0x1a5aaa47, (q31_t)0x1a548436, + (q31_t)0x1a4e5e15, (q31_t)0x1a4837e4, (q31_t)0x1a4211a3, (q31_t)0x1a3beb52, (q31_t)0x1a35c4f0, (q31_t)0x1a2f9e7e, (q31_t)0x1a2977fc, (q31_t)0x1a23516a, + (q31_t)0x1a1d2ac8, (q31_t)0x1a170416, (q31_t)0x1a10dd53, (q31_t)0x1a0ab681, (q31_t)0x1a048f9e, (q31_t)0x19fe68ac, (q31_t)0x19f841a9, (q31_t)0x19f21a96, + (q31_t)0x19ebf374, (q31_t)0x19e5cc41, (q31_t)0x19dfa4fe, (q31_t)0x19d97dac, (q31_t)0x19d35649, (q31_t)0x19cd2ed7, (q31_t)0x19c70754, (q31_t)0x19c0dfc2, + (q31_t)0x19bab820, (q31_t)0x19b4906e, (q31_t)0x19ae68ac, (q31_t)0x19a840da, (q31_t)0x19a218f9, (q31_t)0x199bf107, (q31_t)0x1995c906, (q31_t)0x198fa0f5, + (q31_t)0x198978d4, (q31_t)0x198350a4, (q31_t)0x197d2864, (q31_t)0x19770014, (q31_t)0x1970d7b4, (q31_t)0x196aaf45, (q31_t)0x196486c6, (q31_t)0x195e5e37, + (q31_t)0x19583599, (q31_t)0x19520ceb, (q31_t)0x194be42d, (q31_t)0x1945bb60, (q31_t)0x193f9283, (q31_t)0x19396997, (q31_t)0x1933409b, (q31_t)0x192d178f, + (q31_t)0x1926ee74, (q31_t)0x1920c54a, (q31_t)0x191a9c10, (q31_t)0x191472c6, (q31_t)0x190e496d, (q31_t)0x19082005, (q31_t)0x1901f68d, (q31_t)0x18fbcd06, + (q31_t)0x18f5a36f, (q31_t)0x18ef79c9, (q31_t)0x18e95014, (q31_t)0x18e3264f, (q31_t)0x18dcfc7b, (q31_t)0x18d6d297, (q31_t)0x18d0a8a4, (q31_t)0x18ca7ea2, + (q31_t)0x18c45491, (q31_t)0x18be2a70, (q31_t)0x18b80040, (q31_t)0x18b1d601, (q31_t)0x18ababb2, (q31_t)0x18a58154, (q31_t)0x189f56e8, (q31_t)0x18992c6b, + (q31_t)0x189301e0, (q31_t)0x188cd746, (q31_t)0x1886ac9c, (q31_t)0x188081e4, (q31_t)0x187a571c, (q31_t)0x18742c45, (q31_t)0x186e015f, (q31_t)0x1867d66a, + (q31_t)0x1861ab66, (q31_t)0x185b8053, (q31_t)0x18555530, (q31_t)0x184f29ff, (q31_t)0x1848febf, (q31_t)0x1842d370, (q31_t)0x183ca812, (q31_t)0x18367ca5, + (q31_t)0x18305129, (q31_t)0x182a259e, (q31_t)0x1823fa04, (q31_t)0x181dce5b, (q31_t)0x1817a2a4, (q31_t)0x181176dd, (q31_t)0x180b4b08, (q31_t)0x18051f24, + (q31_t)0x17fef331, (q31_t)0x17f8c72f, (q31_t)0x17f29b1e, (q31_t)0x17ec6eff, (q31_t)0x17e642d1, (q31_t)0x17e01694, (q31_t)0x17d9ea49, (q31_t)0x17d3bdee, + (q31_t)0x17cd9186, (q31_t)0x17c7650e, (q31_t)0x17c13888, (q31_t)0x17bb0bf3, (q31_t)0x17b4df4f, (q31_t)0x17aeb29d, (q31_t)0x17a885dc, (q31_t)0x17a2590d, + (q31_t)0x179c2c2f, (q31_t)0x1795ff42, (q31_t)0x178fd247, (q31_t)0x1789a53d, (q31_t)0x17837825, (q31_t)0x177d4afe, (q31_t)0x17771dc9, (q31_t)0x1770f086, + (q31_t)0x176ac333, (q31_t)0x176495d3, (q31_t)0x175e6864, (q31_t)0x17583ae7, (q31_t)0x17520d5b, (q31_t)0x174bdfc1, (q31_t)0x1745b218, (q31_t)0x173f8461, + (q31_t)0x1739569c, (q31_t)0x173328c8, (q31_t)0x172cfae6, (q31_t)0x1726ccf6, (q31_t)0x17209ef8, (q31_t)0x171a70eb, (q31_t)0x171442d0, (q31_t)0x170e14a7, + (q31_t)0x1707e670, (q31_t)0x1701b82a, (q31_t)0x16fb89d6, (q31_t)0x16f55b74, (q31_t)0x16ef2d04, (q31_t)0x16e8fe86, (q31_t)0x16e2cff9, (q31_t)0x16dca15f, + (q31_t)0x16d672b6, (q31_t)0x16d043ff, (q31_t)0x16ca153a, (q31_t)0x16c3e667, (q31_t)0x16bdb787, (q31_t)0x16b78898, (q31_t)0x16b1599b, (q31_t)0x16ab2a90, + (q31_t)0x16a4fb77, (q31_t)0x169ecc50, (q31_t)0x16989d1b, (q31_t)0x16926dd8, (q31_t)0x168c3e87, (q31_t)0x16860f29, (q31_t)0x167fdfbc, (q31_t)0x1679b042, + (q31_t)0x167380ba, (q31_t)0x166d5123, (q31_t)0x1667217f, (q31_t)0x1660f1ce, (q31_t)0x165ac20e, (q31_t)0x16549241, (q31_t)0x164e6266, (q31_t)0x1648327d, + (q31_t)0x16420286, (q31_t)0x163bd282, (q31_t)0x1635a270, (q31_t)0x162f7250, (q31_t)0x16294222, (q31_t)0x162311e7, (q31_t)0x161ce19e, (q31_t)0x1616b148, + (q31_t)0x161080e4, (q31_t)0x160a5072, (q31_t)0x16041ff3, (q31_t)0x15fdef66, (q31_t)0x15f7becc, (q31_t)0x15f18e24, (q31_t)0x15eb5d6e, (q31_t)0x15e52cab, + (q31_t)0x15defbdb, (q31_t)0x15d8cafd, (q31_t)0x15d29a11, (q31_t)0x15cc6918, (q31_t)0x15c63812, (q31_t)0x15c006fe, (q31_t)0x15b9d5dd, (q31_t)0x15b3a4ae, + (q31_t)0x15ad7372, (q31_t)0x15a74228, (q31_t)0x15a110d2, (q31_t)0x159adf6e, (q31_t)0x1594adfc, (q31_t)0x158e7c7d, (q31_t)0x15884af1, (q31_t)0x15821958, + (q31_t)0x157be7b1, (q31_t)0x1575b5fe, (q31_t)0x156f843c, (q31_t)0x1569526e, (q31_t)0x15632093, (q31_t)0x155ceeaa, (q31_t)0x1556bcb4, (q31_t)0x15508ab1, + (q31_t)0x154a58a1, (q31_t)0x15442683, (q31_t)0x153df459, (q31_t)0x1537c221, (q31_t)0x15318fdd, (q31_t)0x152b5d8b, (q31_t)0x15252b2c, (q31_t)0x151ef8c0, + (q31_t)0x1518c648, (q31_t)0x151293c2, (q31_t)0x150c612f, (q31_t)0x15062e8f, (q31_t)0x14fffbe2, (q31_t)0x14f9c928, (q31_t)0x14f39662, (q31_t)0x14ed638e, + (q31_t)0x14e730ae, (q31_t)0x14e0fdc0, (q31_t)0x14dacac6, (q31_t)0x14d497bf, (q31_t)0x14ce64ab, (q31_t)0x14c8318a, (q31_t)0x14c1fe5c, (q31_t)0x14bbcb22, + (q31_t)0x14b597da, (q31_t)0x14af6486, (q31_t)0x14a93125, (q31_t)0x14a2fdb8, (q31_t)0x149cca3e, (q31_t)0x149696b7, (q31_t)0x14906323, (q31_t)0x148a2f82, + (q31_t)0x1483fbd5, (q31_t)0x147dc81c, (q31_t)0x14779455, (q31_t)0x14716082, (q31_t)0x146b2ca3, (q31_t)0x1464f8b7, (q31_t)0x145ec4be, (q31_t)0x145890b9, + (q31_t)0x14525ca7, (q31_t)0x144c2888, (q31_t)0x1445f45d, (q31_t)0x143fc026, (q31_t)0x14398be2, (q31_t)0x14335792, (q31_t)0x142d2335, (q31_t)0x1426eecb, + (q31_t)0x1420ba56, (q31_t)0x141a85d3, (q31_t)0x14145145, (q31_t)0x140e1caa, (q31_t)0x1407e803, (q31_t)0x1401b34f, (q31_t)0x13fb7e8f, (q31_t)0x13f549c3, + (q31_t)0x13ef14ea, (q31_t)0x13e8e005, (q31_t)0x13e2ab14, (q31_t)0x13dc7616, (q31_t)0x13d6410d, (q31_t)0x13d00bf7, (q31_t)0x13c9d6d4, (q31_t)0x13c3a1a6, + (q31_t)0x13bd6c6b, (q31_t)0x13b73725, (q31_t)0x13b101d2, (q31_t)0x13aacc73, (q31_t)0x13a49707, (q31_t)0x139e6190, (q31_t)0x13982c0d, (q31_t)0x1391f67d, + (q31_t)0x138bc0e1, (q31_t)0x13858b3a, (q31_t)0x137f5586, (q31_t)0x13791fc6, (q31_t)0x1372e9fb, (q31_t)0x136cb423, (q31_t)0x13667e3f, (q31_t)0x13604850, + (q31_t)0x135a1254, (q31_t)0x1353dc4c, (q31_t)0x134da639, (q31_t)0x1347701a, (q31_t)0x134139ee, (q31_t)0x133b03b7, (q31_t)0x1334cd74, (q31_t)0x132e9725, + (q31_t)0x132860ca, (q31_t)0x13222a64, (q31_t)0x131bf3f2, (q31_t)0x1315bd73, (q31_t)0x130f86ea, (q31_t)0x13095054, (q31_t)0x130319b3, (q31_t)0x12fce305, + (q31_t)0x12f6ac4d, (q31_t)0x12f07588, (q31_t)0x12ea3eb8, (q31_t)0x12e407dc, (q31_t)0x12ddd0f4, (q31_t)0x12d79a01, (q31_t)0x12d16303, (q31_t)0x12cb2bf8, + (q31_t)0x12c4f4e2, (q31_t)0x12bebdc1, (q31_t)0x12b88693, (q31_t)0x12b24f5b, (q31_t)0x12ac1817, (q31_t)0x12a5e0c7, (q31_t)0x129fa96c, (q31_t)0x12997205, + (q31_t)0x12933a93, (q31_t)0x128d0315, (q31_t)0x1286cb8c, (q31_t)0x128093f7, (q31_t)0x127a5c57, (q31_t)0x127424ac, (q31_t)0x126decf5, (q31_t)0x1267b533, + (q31_t)0x12617d66, (q31_t)0x125b458d, (q31_t)0x12550da9, (q31_t)0x124ed5ba, (q31_t)0x12489dbf, (q31_t)0x124265b9, (q31_t)0x123c2da8, (q31_t)0x1235f58b, + (q31_t)0x122fbd63, (q31_t)0x12298530, (q31_t)0x12234cf2, (q31_t)0x121d14a9, (q31_t)0x1216dc54, (q31_t)0x1210a3f5, (q31_t)0x120a6b8a, (q31_t)0x12043314, + (q31_t)0x11fdfa93, (q31_t)0x11f7c207, (q31_t)0x11f18970, (q31_t)0x11eb50cd, (q31_t)0x11e51820, (q31_t)0x11dedf68, (q31_t)0x11d8a6a4, (q31_t)0x11d26dd6, + (q31_t)0x11cc34fc, (q31_t)0x11c5fc18, (q31_t)0x11bfc329, (q31_t)0x11b98a2e, (q31_t)0x11b35129, (q31_t)0x11ad1819, (q31_t)0x11a6defe, (q31_t)0x11a0a5d8, + (q31_t)0x119a6ca7, (q31_t)0x1194336b, (q31_t)0x118dfa25, (q31_t)0x1187c0d3, (q31_t)0x11818777, (q31_t)0x117b4e10, (q31_t)0x1175149e, (q31_t)0x116edb22, + (q31_t)0x1168a19b, (q31_t)0x11626809, (q31_t)0x115c2e6c, (q31_t)0x1155f4c4, (q31_t)0x114fbb12, (q31_t)0x11498156, (q31_t)0x1143478e, (q31_t)0x113d0dbc, + (q31_t)0x1136d3df, (q31_t)0x113099f8, (q31_t)0x112a6006, (q31_t)0x11242609, (q31_t)0x111dec02, (q31_t)0x1117b1f0, (q31_t)0x111177d4, (q31_t)0x110b3dad, + (q31_t)0x1105037c, (q31_t)0x10fec940, (q31_t)0x10f88efa, (q31_t)0x10f254a9, (q31_t)0x10ec1a4e, (q31_t)0x10e5dfe8, (q31_t)0x10dfa578, (q31_t)0x10d96afe, + (q31_t)0x10d33079, (q31_t)0x10ccf5ea, (q31_t)0x10c6bb50, (q31_t)0x10c080ac, (q31_t)0x10ba45fe, (q31_t)0x10b40b45, (q31_t)0x10add082, (q31_t)0x10a795b5, + (q31_t)0x10a15ade, (q31_t)0x109b1ffc, (q31_t)0x1094e510, (q31_t)0x108eaa1a, (q31_t)0x10886f19, (q31_t)0x1082340f, (q31_t)0x107bf8fa, (q31_t)0x1075bddb, + (q31_t)0x106f82b2, (q31_t)0x1069477f, (q31_t)0x10630c41, (q31_t)0x105cd0fa, (q31_t)0x105695a8, (q31_t)0x10505a4d, (q31_t)0x104a1ee7, (q31_t)0x1043e377, + (q31_t)0x103da7fd, (q31_t)0x10376c79, (q31_t)0x103130ec, (q31_t)0x102af554, (q31_t)0x1024b9b2, (q31_t)0x101e7e06, (q31_t)0x10184251, (q31_t)0x10120691, + (q31_t)0x100bcac7, (q31_t)0x10058ef4, (q31_t)0xfff5317, (q31_t)0xff91730, (q31_t)0xff2db3e, (q31_t)0xfec9f44, (q31_t)0xfe6633f, (q31_t)0xfe02730, + (q31_t)0xfd9eb18, (q31_t)0xfd3aef6, (q31_t)0xfcd72ca, (q31_t)0xfc73695, (q31_t)0xfc0fa55, (q31_t)0xfbabe0c, (q31_t)0xfb481ba, (q31_t)0xfae455d, + (q31_t)0xfa808f7, (q31_t)0xfa1cc87, (q31_t)0xf9b900e, (q31_t)0xf95538b, (q31_t)0xf8f16fe, (q31_t)0xf88da68, (q31_t)0xf829dc8, (q31_t)0xf7c611f, + (q31_t)0xf76246c, (q31_t)0xf6fe7af, (q31_t)0xf69aae9, (q31_t)0xf636e1a, (q31_t)0xf5d3141, (q31_t)0xf56f45e, (q31_t)0xf50b773, (q31_t)0xf4a7a7d, + (q31_t)0xf443d7e, (q31_t)0xf3e0076, (q31_t)0xf37c365, (q31_t)0xf318649, (q31_t)0xf2b4925, (q31_t)0xf250bf7, (q31_t)0xf1ecec0, (q31_t)0xf189180, + (q31_t)0xf125436, (q31_t)0xf0c16e3, (q31_t)0xf05d987, (q31_t)0xeff9c21, (q31_t)0xef95eb2, (q31_t)0xef3213a, (q31_t)0xeece3b9, (q31_t)0xee6a62f, + (q31_t)0xee0689b, (q31_t)0xeda2afe, (q31_t)0xed3ed58, (q31_t)0xecdafa9, (q31_t)0xec771f1, (q31_t)0xec1342f, (q31_t)0xebaf665, (q31_t)0xeb4b891, + (q31_t)0xeae7ab4, (q31_t)0xea83ccf, (q31_t)0xea1fee0, (q31_t)0xe9bc0e8, (q31_t)0xe9582e7, (q31_t)0xe8f44dd, (q31_t)0xe8906cb, (q31_t)0xe82c8af, + (q31_t)0xe7c8a8a, (q31_t)0xe764c5c, (q31_t)0xe700e26, (q31_t)0xe69cfe6, (q31_t)0xe63919e, (q31_t)0xe5d534d, (q31_t)0xe5714f3, (q31_t)0xe50d690, + (q31_t)0xe4a9824, (q31_t)0xe4459af, (q31_t)0xe3e1b32, (q31_t)0xe37dcac, (q31_t)0xe319e1d, (q31_t)0xe2b5f85, (q31_t)0xe2520e5, (q31_t)0xe1ee23c, + (q31_t)0xe18a38a, (q31_t)0xe1264cf, (q31_t)0xe0c260c, (q31_t)0xe05e740, (q31_t)0xdffa86b, (q31_t)0xdf9698e, (q31_t)0xdf32aa8, (q31_t)0xdecebba, + (q31_t)0xde6acc3, (q31_t)0xde06dc3, (q31_t)0xdda2ebb, (q31_t)0xdd3efab, (q31_t)0xdcdb091, (q31_t)0xdc77170, (q31_t)0xdc13245, (q31_t)0xdbaf313, + (q31_t)0xdb4b3d7, (q31_t)0xdae7494, (q31_t)0xda83548, (q31_t)0xda1f5f3, (q31_t)0xd9bb696, (q31_t)0xd957731, (q31_t)0xd8f37c3, (q31_t)0xd88f84d, + (q31_t)0xd82b8cf, (q31_t)0xd7c7948, (q31_t)0xd7639b9, (q31_t)0xd6ffa22, (q31_t)0xd69ba82, (q31_t)0xd637ada, (q31_t)0xd5d3b2a, (q31_t)0xd56fb71, + (q31_t)0xd50bbb1, (q31_t)0xd4a7be8, (q31_t)0xd443c17, (q31_t)0xd3dfc3e, (q31_t)0xd37bc5c, (q31_t)0xd317c73, (q31_t)0xd2b3c81, (q31_t)0xd24fc87, + (q31_t)0xd1ebc85, (q31_t)0xd187c7b, (q31_t)0xd123c69, (q31_t)0xd0bfc4f, (q31_t)0xd05bc2d, (q31_t)0xcff7c02, (q31_t)0xcf93bd0, (q31_t)0xcf2fb96, + (q31_t)0xcecbb53, (q31_t)0xce67b09, (q31_t)0xce03ab7, (q31_t)0xcd9fa5d, (q31_t)0xcd3b9fb, (q31_t)0xccd7991, (q31_t)0xcc7391f, (q31_t)0xcc0f8a5, + (q31_t)0xcbab824, (q31_t)0xcb4779a, (q31_t)0xcae3709, (q31_t)0xca7f670, (q31_t)0xca1b5cf, (q31_t)0xc9b7526, (q31_t)0xc953475, (q31_t)0xc8ef3bd, + (q31_t)0xc88b2fd, (q31_t)0xc827235, (q31_t)0xc7c3166, (q31_t)0xc75f08f, (q31_t)0xc6fafb0, (q31_t)0xc696ec9, (q31_t)0xc632ddb, (q31_t)0xc5cece5, + (q31_t)0xc56abe8, (q31_t)0xc506ae3, (q31_t)0xc4a29d6, (q31_t)0xc43e8c2, (q31_t)0xc3da7a6, (q31_t)0xc376683, (q31_t)0xc312558, (q31_t)0xc2ae425, + (q31_t)0xc24a2eb, (q31_t)0xc1e61aa, (q31_t)0xc182061, (q31_t)0xc11df11, (q31_t)0xc0b9db9, (q31_t)0xc055c5a, (q31_t)0xbff1af3, (q31_t)0xbf8d985, + (q31_t)0xbf29810, (q31_t)0xbec5693, (q31_t)0xbe6150f, (q31_t)0xbdfd383, (q31_t)0xbd991f0, (q31_t)0xbd35056, (q31_t)0xbcd0eb5, (q31_t)0xbc6cd0c, + (q31_t)0xbc08b5c, (q31_t)0xbba49a5, (q31_t)0xbb407e7, (q31_t)0xbadc621, (q31_t)0xba78454, (q31_t)0xba14280, (q31_t)0xb9b00a5, (q31_t)0xb94bec2, + (q31_t)0xb8e7cd9, (q31_t)0xb883ae8, (q31_t)0xb81f8f0, (q31_t)0xb7bb6f2, (q31_t)0xb7574ec, (q31_t)0xb6f32df, (q31_t)0xb68f0cb, (q31_t)0xb62aeaf, + (q31_t)0xb5c6c8d, (q31_t)0xb562a64, (q31_t)0xb4fe834, (q31_t)0xb49a5fd, (q31_t)0xb4363bf, (q31_t)0xb3d217a, (q31_t)0xb36df2e, (q31_t)0xb309cdb, + (q31_t)0xb2a5a81, (q31_t)0xb241820, (q31_t)0xb1dd5b9, (q31_t)0xb17934b, (q31_t)0xb1150d5, (q31_t)0xb0b0e59, (q31_t)0xb04cbd6, (q31_t)0xafe894d, + (q31_t)0xaf846bc, (q31_t)0xaf20425, (q31_t)0xaebc187, (q31_t)0xae57ee2, (q31_t)0xadf3c37, (q31_t)0xad8f985, (q31_t)0xad2b6cc, (q31_t)0xacc740c, + (q31_t)0xac63146, (q31_t)0xabfee79, (q31_t)0xab9aba6, (q31_t)0xab368cc, (q31_t)0xaad25eb, (q31_t)0xaa6e304, (q31_t)0xaa0a016, (q31_t)0xa9a5d22, + (q31_t)0xa941a27, (q31_t)0xa8dd725, (q31_t)0xa87941d, (q31_t)0xa81510f, (q31_t)0xa7b0dfa, (q31_t)0xa74cadf, (q31_t)0xa6e87bd, (q31_t)0xa684495, + (q31_t)0xa620166, (q31_t)0xa5bbe31, (q31_t)0xa557af5, (q31_t)0xa4f37b3, (q31_t)0xa48f46b, (q31_t)0xa42b11d, (q31_t)0xa3c6dc8, (q31_t)0xa362a6d, + (q31_t)0xa2fe70b, (q31_t)0xa29a3a3, (q31_t)0xa236035, (q31_t)0xa1d1cc1, (q31_t)0xa16d946, (q31_t)0xa1095c6, (q31_t)0xa0a523f, (q31_t)0xa040eb1, + (q31_t)0x9fdcb1e, (q31_t)0x9f78784, (q31_t)0x9f143e5, (q31_t)0x9eb003f, (q31_t)0x9e4bc93, (q31_t)0x9de78e1, (q31_t)0x9d83529, (q31_t)0x9d1f16b, + (q31_t)0x9cbada7, (q31_t)0x9c569dc, (q31_t)0x9bf260c, (q31_t)0x9b8e236, (q31_t)0x9b29e59, (q31_t)0x9ac5a77, (q31_t)0x9a6168f, (q31_t)0x99fd2a0, + (q31_t)0x9998eac, (q31_t)0x9934ab2, (q31_t)0x98d06b2, (q31_t)0x986c2ac, (q31_t)0x9807ea1, (q31_t)0x97a3a8f, (q31_t)0x973f678, (q31_t)0x96db25a, + (q31_t)0x9676e37, (q31_t)0x9612a0e, (q31_t)0x95ae5e0, (q31_t)0x954a1ab, (q31_t)0x94e5d71, (q31_t)0x9481931, (q31_t)0x941d4eb, (q31_t)0x93b90a0, + (q31_t)0x9354c4f, (q31_t)0x92f07f8, (q31_t)0x928c39b, (q31_t)0x9227f39, (q31_t)0x91c3ad2, (q31_t)0x915f664, (q31_t)0x90fb1f1, (q31_t)0x9096d79, + (q31_t)0x90328fb, (q31_t)0x8fce477, (q31_t)0x8f69fee, (q31_t)0x8f05b5f, (q31_t)0x8ea16cb, (q31_t)0x8e3d231, (q31_t)0x8dd8d92, (q31_t)0x8d748ed, + (q31_t)0x8d10443, (q31_t)0x8cabf93, (q31_t)0x8c47ade, (q31_t)0x8be3624, (q31_t)0x8b7f164, (q31_t)0x8b1ac9f, (q31_t)0x8ab67d4, (q31_t)0x8a52304, + (q31_t)0x89ede2f, (q31_t)0x8989955, (q31_t)0x8925475, (q31_t)0x88c0f90, (q31_t)0x885caa5, (q31_t)0x87f85b5, (q31_t)0x87940c1, (q31_t)0x872fbc6, + (q31_t)0x86cb6c7, (q31_t)0x86671c2, (q31_t)0x8602cb9, (q31_t)0x859e7aa, (q31_t)0x853a296, (q31_t)0x84d5d7d, (q31_t)0x847185e, (q31_t)0x840d33b, + (q31_t)0x83a8e12, (q31_t)0x83448e5, (q31_t)0x82e03b2, (q31_t)0x827be7a, (q31_t)0x821793e, (q31_t)0x81b33fc, (q31_t)0x814eeb5, (q31_t)0x80ea969, + (q31_t)0x8086419, (q31_t)0x8021ec3, (q31_t)0x7fbd968, (q31_t)0x7f59409, (q31_t)0x7ef4ea4, (q31_t)0x7e9093b, (q31_t)0x7e2c3cd, (q31_t)0x7dc7e5a, + (q31_t)0x7d638e2, (q31_t)0x7cff365, (q31_t)0x7c9ade4, (q31_t)0x7c3685d, (q31_t)0x7bd22d2, (q31_t)0x7b6dd42, (q31_t)0x7b097ad, (q31_t)0x7aa5214, + (q31_t)0x7a40c76, (q31_t)0x79dc6d3, (q31_t)0x797812b, (q31_t)0x7913b7f, (q31_t)0x78af5ce, (q31_t)0x784b019, (q31_t)0x77e6a5e, (q31_t)0x77824a0, + (q31_t)0x771dedc, (q31_t)0x76b9914, (q31_t)0x7655347, (q31_t)0x75f0d76, (q31_t)0x758c7a1, (q31_t)0x75281c6, (q31_t)0x74c3be7, (q31_t)0x745f604, + (q31_t)0x73fb01c, (q31_t)0x7396a30, (q31_t)0x733243f, (q31_t)0x72cde4a, (q31_t)0x7269851, (q31_t)0x7205253, (q31_t)0x71a0c50, (q31_t)0x713c64a, + (q31_t)0x70d803f, (q31_t)0x7073a2f, (q31_t)0x700f41b, (q31_t)0x6faae03, (q31_t)0x6f467e7, (q31_t)0x6ee21c6, (q31_t)0x6e7dba1, (q31_t)0x6e19578, + (q31_t)0x6db4f4a, (q31_t)0x6d50919, (q31_t)0x6cec2e3, (q31_t)0x6c87ca9, (q31_t)0x6c2366a, (q31_t)0x6bbf028, (q31_t)0x6b5a9e1, (q31_t)0x6af6396, + (q31_t)0x6a91d47, (q31_t)0x6a2d6f4, (q31_t)0x69c909d, (q31_t)0x6964a42, (q31_t)0x69003e3, (q31_t)0x689bd80, (q31_t)0x6837718, (q31_t)0x67d30ad, + (q31_t)0x676ea3d, (q31_t)0x670a3ca, (q31_t)0x66a5d53, (q31_t)0x66416d8, (q31_t)0x65dd058, (q31_t)0x65789d5, (q31_t)0x651434e, (q31_t)0x64afcc3, + (q31_t)0x644b634, (q31_t)0x63e6fa2, (q31_t)0x638290b, (q31_t)0x631e271, (q31_t)0x62b9bd3, (q31_t)0x6255531, (q31_t)0x61f0e8b, (q31_t)0x618c7e1, + (q31_t)0x6128134, (q31_t)0x60c3a83, (q31_t)0x605f3ce, (q31_t)0x5ffad15, (q31_t)0x5f96659, (q31_t)0x5f31f99, (q31_t)0x5ecd8d6, (q31_t)0x5e6920e, + (q31_t)0x5e04b43, (q31_t)0x5da0475, (q31_t)0x5d3bda3, (q31_t)0x5cd76cd, (q31_t)0x5c72ff4, (q31_t)0x5c0e917, (q31_t)0x5baa237, (q31_t)0x5b45b53, + (q31_t)0x5ae146b, (q31_t)0x5a7cd80, (q31_t)0x5a18692, (q31_t)0x59b3fa0, (q31_t)0x594f8aa, (q31_t)0x58eb1b2, (q31_t)0x5886ab5, (q31_t)0x58223b6, + (q31_t)0x57bdcb3, (q31_t)0x57595ac, (q31_t)0x56f4ea2, (q31_t)0x5690795, (q31_t)0x562c085, (q31_t)0x55c7971, (q31_t)0x556325a, (q31_t)0x54feb3f, + (q31_t)0x549a422, (q31_t)0x5435d01, (q31_t)0x53d15dd, (q31_t)0x536ceb5, (q31_t)0x530878a, (q31_t)0x52a405d, (q31_t)0x523f92c, (q31_t)0x51db1f7, + (q31_t)0x5176ac0, (q31_t)0x5112385, (q31_t)0x50adc48, (q31_t)0x5049507, (q31_t)0x4fe4dc3, (q31_t)0x4f8067c, (q31_t)0x4f1bf32, (q31_t)0x4eb77e5, + (q31_t)0x4e53095, (q31_t)0x4dee942, (q31_t)0x4d8a1ec, (q31_t)0x4d25a93, (q31_t)0x4cc1337, (q31_t)0x4c5cbd8, (q31_t)0x4bf8476, (q31_t)0x4b93d11, + (q31_t)0x4b2f5a9, (q31_t)0x4acae3e, (q31_t)0x4a666d1, (q31_t)0x4a01f60, (q31_t)0x499d7ed, (q31_t)0x4939077, (q31_t)0x48d48fe, (q31_t)0x4870182, + (q31_t)0x480ba04, (q31_t)0x47a7282, (q31_t)0x4742afe, (q31_t)0x46de377, (q31_t)0x4679bee, (q31_t)0x4615461, (q31_t)0x45b0cd2, (q31_t)0x454c541, + (q31_t)0x44e7dac, (q31_t)0x4483615, (q31_t)0x441ee7c, (q31_t)0x43ba6df, (q31_t)0x4355f40, (q31_t)0x42f179f, (q31_t)0x428cffb, (q31_t)0x4228854, + (q31_t)0x41c40ab, (q31_t)0x415f8ff, (q31_t)0x40fb151, (q31_t)0x40969a0, (q31_t)0x40321ed, (q31_t)0x3fcda37, (q31_t)0x3f6927f, (q31_t)0x3f04ac4, + (q31_t)0x3ea0307, (q31_t)0x3e3bb48, (q31_t)0x3dd7386, (q31_t)0x3d72bc2, (q31_t)0x3d0e3fb, (q31_t)0x3ca9c32, (q31_t)0x3c45467, (q31_t)0x3be0c99, + (q31_t)0x3b7c4c9, (q31_t)0x3b17cf7, (q31_t)0x3ab3523, (q31_t)0x3a4ed4c, (q31_t)0x39ea573, (q31_t)0x3985d97, (q31_t)0x39215ba, (q31_t)0x38bcdda, + (q31_t)0x38585f8, (q31_t)0x37f3e14, (q31_t)0x378f62e, (q31_t)0x372ae46, (q31_t)0x36c665b, (q31_t)0x3661e6f, (q31_t)0x35fd680, (q31_t)0x3598e8f, + (q31_t)0x353469c, (q31_t)0x34cfea8, (q31_t)0x346b6b1, (q31_t)0x3406eb8, (q31_t)0x33a26bd, (q31_t)0x333dec0, (q31_t)0x32d96c1, (q31_t)0x3274ec0, + (q31_t)0x32106bd, (q31_t)0x31abeb9, (q31_t)0x31476b2, (q31_t)0x30e2ea9, (q31_t)0x307e69f, (q31_t)0x3019e93, (q31_t)0x2fb5684, (q31_t)0x2f50e74, + (q31_t)0x2eec663, (q31_t)0x2e87e4f, (q31_t)0x2e2363a, (q31_t)0x2dbee22, (q31_t)0x2d5a609, (q31_t)0x2cf5def, (q31_t)0x2c915d2, (q31_t)0x2c2cdb4, + (q31_t)0x2bc8594, (q31_t)0x2b63d73, (q31_t)0x2aff54f, (q31_t)0x2a9ad2a, (q31_t)0x2a36504, (q31_t)0x29d1cdc, (q31_t)0x296d4b2, (q31_t)0x2908c87, + (q31_t)0x28a445a, (q31_t)0x283fc2b, (q31_t)0x27db3fb, (q31_t)0x2776bc9, (q31_t)0x2712396, (q31_t)0x26adb62, (q31_t)0x264932b, (q31_t)0x25e4af4, + (q31_t)0x25802bb, (q31_t)0x251ba80, (q31_t)0x24b7244, (q31_t)0x2452a07, (q31_t)0x23ee1c8, (q31_t)0x2389988, (q31_t)0x2325147, (q31_t)0x22c0904, + (q31_t)0x225c0bf, (q31_t)0x21f787a, (q31_t)0x2193033, (q31_t)0x212e7eb, (q31_t)0x20c9fa1, (q31_t)0x2065757, (q31_t)0x2000f0b, (q31_t)0x1f9c6be, + (q31_t)0x1f37e6f, (q31_t)0x1ed3620, (q31_t)0x1e6edcf, (q31_t)0x1e0a57d, (q31_t)0x1da5d2a, (q31_t)0x1d414d6, (q31_t)0x1cdcc80, (q31_t)0x1c7842a, + (q31_t)0x1c13bd2, (q31_t)0x1baf37a, (q31_t)0x1b4ab20, (q31_t)0x1ae62c5, (q31_t)0x1a81a69, (q31_t)0x1a1d20c, (q31_t)0x19b89ae, (q31_t)0x1954150, + (q31_t)0x18ef8f0, (q31_t)0x188b08f, (q31_t)0x182682d, (q31_t)0x17c1fcb, (q31_t)0x175d767, (q31_t)0x16f8f03, (q31_t)0x169469d, (q31_t)0x162fe37, + (q31_t)0x15cb5d0, (q31_t)0x1566d68, (q31_t)0x15024ff, (q31_t)0x149dc96, (q31_t)0x143942b, (q31_t)0x13d4bc0, (q31_t)0x1370354, (q31_t)0x130bae7, + (q31_t)0x12a727a, (q31_t)0x1242a0c, (q31_t)0x11de19d, (q31_t)0x117992e, (q31_t)0x11150be, (q31_t)0x10b084d, (q31_t)0x104bfdb, (q31_t)0xfe7769, + (q31_t)0xf82ef6, (q31_t)0xf1e683, (q31_t)0xeb9e0f, (q31_t)0xe5559b, (q31_t)0xdf0d26, (q31_t)0xd8c4b0, (q31_t)0xd27c3a, (q31_t)0xcc33c3, + (q31_t)0xc5eb4c, (q31_t)0xbfa2d5, (q31_t)0xb95a5d, (q31_t)0xb311e4, (q31_t)0xacc96b, (q31_t)0xa680f2, (q31_t)0xa03878, (q31_t)0x99effe, + (q31_t)0x93a784, (q31_t)0x8d5f09, (q31_t)0x87168e, (q31_t)0x80ce12, (q31_t)0x7a8597, (q31_t)0x743d1a, (q31_t)0x6df49e, (q31_t)0x67ac21, + (q31_t)0x6163a5, (q31_t)0x5b1b27, (q31_t)0x54d2aa, (q31_t)0x4e8a2c, (q31_t)0x4841af, (q31_t)0x41f931, (q31_t)0x3bb0b3, (q31_t)0x356835, + (q31_t)0x2f1fb6, (q31_t)0x28d738, (q31_t)0x228eb9, (q31_t)0x1c463b, (q31_t)0x15fdbc, (q31_t)0xfb53d, (q31_t)0x96cbe, (q31_t)0x3243f +}; + #endif + +/** + @} end of DCT4_IDCT4_Table group + */ + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +/** + @brief Q15 table for reciprocal +*/ +const q15_t __ALIGNED(4) armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + +/** + @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +/** + @par + Example code for the generation of the floating-point sine table: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ @par + where PI value is 3.14159265358979 + */ +const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1] = { + 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, + 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, + 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, + 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, + 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, + 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, + 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, + 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, + 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, + 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, + 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, + 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, + 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, + 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, + 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, + 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, + 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, + 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, + 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, + 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, + 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, + 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, + 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, + 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, + 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, + 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, + 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, + 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, + 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, + 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, + 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, + 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, + 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, + 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, + 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, + 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, + 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, + 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, + 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, + 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, + 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, + 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, + 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, + -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, + -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, + -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, + -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, + -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, + -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, + -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, + -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, + -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, + -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, + -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, + -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, + -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, + -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, + -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, + -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, + -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, + -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, + -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, + -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, + -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, + -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, + -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, + -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, + -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, + -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, + -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, + -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, + -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, + -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, + -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, + -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, + -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, + -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, + -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, + -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, + -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, + -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, + -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, + -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, + -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, + -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, + -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, + -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, + -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, + -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, + -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, + -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, + -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, + -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, + -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +/** + @par + Table values are in Q31 (1.31 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q31 (Fixed point): + (sinTable[i] * pow(2, 31)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 : -0.5); + */ +const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1] = { + 0L, 26352928L, 52701887L, 79042909L, 105372028L, 131685278L, 157978697L, + 184248325L, 210490206L, 236700388L, 262874923L, 289009871L, 315101295L, + 341145265L, 367137861L, 393075166L, 418953276L, 444768294L, 470516330L, + 496193509L, 521795963L, 547319836L, 572761285L, 598116479L, 623381598L, + 648552838L, 673626408L, 698598533L, 723465451L, 748223418L, 772868706L, + 797397602L, 821806413L, 846091463L, 870249095L, 894275671L, 918167572L, + 941921200L, 965532978L, 988999351L, 1012316784L, 1035481766L, 1058490808L, + 1081340445L, 1104027237L, 1126547765L, 1148898640L, 1171076495L, 1193077991L, + 1214899813L, 1236538675L, 1257991320L, 1279254516L, 1300325060L, 1321199781L, + 1341875533L, 1362349204L, 1382617710L, 1402678000L, 1422527051L, 1442161874L, + 1461579514L, 1480777044L, 1499751576L, 1518500250L, 1537020244L, 1555308768L, + 1573363068L, 1591180426L, 1608758157L, 1626093616L, 1643184191L, 1660027308L, + 1676620432L, 1692961062L, 1709046739L, 1724875040L, 1740443581L, 1755750017L, + 1770792044L, 1785567396L, 1800073849L, 1814309216L, 1828271356L, 1841958164L, + 1855367581L, 1868497586L, 1881346202L, 1893911494L, 1906191570L, 1918184581L, + 1929888720L, 1941302225L, 1952423377L, 1963250501L, 1973781967L, 1984016189L, + 1993951625L, 2003586779L, 2012920201L, 2021950484L, 2030676269L, 2039096241L, + 2047209133L, 2055013723L, 2062508835L, 2069693342L, 2076566160L, 2083126254L, + 2089372638L, 2095304370L, 2100920556L, 2106220352L, 2111202959L, 2115867626L, + 2120213651L, 2124240380L, 2127947206L, 2131333572L, 2134398966L, 2137142927L, + 2139565043L, 2141664948L, 2143442326L, 2144896910L, 2146028480L, 2146836866L, + 2147321946L, 2147483647L, 2147321946L, 2146836866L, 2146028480L, 2144896910L, + 2143442326L, 2141664948L, 2139565043L, 2137142927L, 2134398966L, 2131333572L, + 2127947206L, 2124240380L, 2120213651L, 2115867626L, 2111202959L, 2106220352L, + 2100920556L, 2095304370L, 2089372638L, 2083126254L, 2076566160L, 2069693342L, + 2062508835L, 2055013723L, 2047209133L, 2039096241L, 2030676269L, 2021950484L, + 2012920201L, 2003586779L, 1993951625L, 1984016189L, 1973781967L, 1963250501L, + 1952423377L, 1941302225L, 1929888720L, 1918184581L, 1906191570L, 1893911494L, + 1881346202L, 1868497586L, 1855367581L, 1841958164L, 1828271356L, 1814309216L, + 1800073849L, 1785567396L, 1770792044L, 1755750017L, 1740443581L, 1724875040L, + 1709046739L, 1692961062L, 1676620432L, 1660027308L, 1643184191L, 1626093616L, + 1608758157L, 1591180426L, 1573363068L, 1555308768L, 1537020244L, 1518500250L, + 1499751576L, 1480777044L, 1461579514L, 1442161874L, 1422527051L, 1402678000L, + 1382617710L, 1362349204L, 1341875533L, 1321199781L, 1300325060L, 1279254516L, + 1257991320L, 1236538675L, 1214899813L, 1193077991L, 1171076495L, 1148898640L, + 1126547765L, 1104027237L, 1081340445L, 1058490808L, 1035481766L, 1012316784L, + 988999351L, 965532978L, 941921200L, 918167572L, 894275671L, 870249095L, + 846091463L, 821806413L, 797397602L, 772868706L, 748223418L, 723465451L, + 698598533L, 673626408L, 648552838L, 623381598L, 598116479L, 572761285L, + 547319836L, 521795963L, 496193509L, 470516330L, 444768294L, 418953276L, + 393075166L, 367137861L, 341145265L, 315101295L, 289009871L, 262874923L, + 236700388L, 210490206L, 184248325L, 157978697L, 131685278L, 105372028L, + 79042909L, 52701887L, 26352928L, 0L, -26352928L, -52701887L, -79042909L, + -105372028L, -131685278L, -157978697L, -184248325L, -210490206L, -236700388L, + -262874923L, -289009871L, -315101295L, -341145265L, -367137861L, -393075166L, + -418953276L, -444768294L, -470516330L, -496193509L, -521795963L, -547319836L, + -572761285L, -598116479L, -623381598L, -648552838L, -673626408L, -698598533L, + -723465451L, -748223418L, -772868706L, -797397602L, -821806413L, -846091463L, + -870249095L, -894275671L, -918167572L, -941921200L, -965532978L, -988999351L, + -1012316784L, -1035481766L, -1058490808L, -1081340445L, -1104027237L, + -1126547765L, -1148898640L, -1171076495L, -1193077991L, -1214899813L, + -1236538675L, -1257991320L, -1279254516L, -1300325060L, -1321199781L, + -1341875533L, -1362349204L, -1382617710L, -1402678000L, -1422527051L, + -1442161874L, -1461579514L, -1480777044L, -1499751576L, -1518500250L, + -1537020244L, -1555308768L, -1573363068L, -1591180426L, -1608758157L, + -1626093616L, -1643184191L, -1660027308L, -1676620432L, -1692961062L, + -1709046739L, -1724875040L, -1740443581L, -1755750017L, -1770792044L, + -1785567396L, -1800073849L, -1814309216L, -1828271356L, -1841958164L, + -1855367581L, -1868497586L, -1881346202L, -1893911494L, -1906191570L, + -1918184581L, -1929888720L, -1941302225L, -1952423377L, -1963250501L, + -1973781967L, -1984016189L, -1993951625L, -2003586779L, -2012920201L, + -2021950484L, -2030676269L, -2039096241L, -2047209133L, -2055013723L, + -2062508835L, -2069693342L, -2076566160L, -2083126254L, -2089372638L, + -2095304370L, -2100920556L, -2106220352L, -2111202959L, -2115867626L, + -2120213651L, -2124240380L, -2127947206L, -2131333572L, -2134398966L, + -2137142927L, -2139565043L, -2141664948L, -2143442326L, -2144896910L, + -2146028480L, -2146836866L, -2147321946L, (q31_t)0x80000000, -2147321946L, + -2146836866L, -2146028480L, -2144896910L, -2143442326L, -2141664948L, + -2139565043L, -2137142927L, -2134398966L, -2131333572L, -2127947206L, + -2124240380L, -2120213651L, -2115867626L, -2111202959L, -2106220352L, + -2100920556L, -2095304370L, -2089372638L, -2083126254L, -2076566160L, + -2069693342L, -2062508835L, -2055013723L, -2047209133L, -2039096241L, + -2030676269L, -2021950484L, -2012920201L, -2003586779L, -1993951625L, + -1984016189L, -1973781967L, -1963250501L, -1952423377L, -1941302225L, + -1929888720L, -1918184581L, -1906191570L, -1893911494L, -1881346202L, + -1868497586L, -1855367581L, -1841958164L, -1828271356L, -1814309216L, + -1800073849L, -1785567396L, -1770792044L, -1755750017L, -1740443581L, + -1724875040L, -1709046739L, -1692961062L, -1676620432L, -1660027308L, + -1643184191L, -1626093616L, -1608758157L, -1591180426L, -1573363068L, + -1555308768L, -1537020244L, -1518500250L, -1499751576L, -1480777044L, + -1461579514L, -1442161874L, -1422527051L, -1402678000L, -1382617710L, + -1362349204L, -1341875533L, -1321199781L, -1300325060L, -1279254516L, + -1257991320L, -1236538675L, -1214899813L, -1193077991L, -1171076495L, + -1148898640L, -1126547765L, -1104027237L, -1081340445L, -1058490808L, + -1035481766L, -1012316784L, -988999351L, -965532978L, -941921200L, + -918167572L, -894275671L, -870249095L, -846091463L, -821806413L, -797397602L, + -772868706L, -748223418L, -723465451L, -698598533L, -673626408L, -648552838L, + -623381598L, -598116479L, -572761285L, -547319836L, -521795963L, -496193509L, + -470516330L, -444768294L, -418953276L, -393075166L, -367137861L, -341145265L, + -315101295L, -289009871L, -262874923L, -236700388L, -210490206L, -184248325L, + -157978697L, -131685278L, -105372028L, -79042909L, -52701887L, -26352928L, 0 +}; + +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +/** + @par + Table values are in Q15 (1.15 fixed-point format) and generation is done in + three steps. First, generate sin values in floating point: + 
+  tableSize = 512;
+  for (n = 0; n < (tableSize + 1); n++)
+  {
+ 	sinTable[n] = sin(2*PI*n/tableSize);
+  }
+ where PI value is 3.14159265358979 + @par + Second, convert floating-point to Q15 (Fixed point): + (sinTable[i] * pow(2, 15)) + @par + Finally, round to the nearest integer value: + sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); + */ +const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1] = { + 0, 402, 804, 1206, 1608, 2009, 2411, 2811, 3212, 3612, 4011, 4410, 4808, + 5205, 5602, 5998, 6393, 6787, 7180, 7571, 7962, 8351, 8740, 9127, 9512, + 9896, 10279, 10660, 11039, 11417, 11793, 12167, 12540, 12910, 13279, + 13646, 14010, 14373, 14733, 15091, 15447, 15800, 16151, 16500, 16846, + 17190, 17531, 17869, 18205, 18538, 18868, 19195, 19520, 19841, 20160, + 20475, 20788, 21097, 21403, 21706, 22006, 22302, 22595, 22884, 23170, + 23453, 23732, 24008, 24279, 24548, 24812, 25073, 25330, 25583, 25833, + 26078, 26320, 26557, 26791, 27020, 27246, 27467, 27684, 27897, 28106, + 28311, 28511, 28707, 28899, 29086, 29269, 29448, 29622, 29792, 29957, + 30118, 30274, 30425, 30572, 30715, 30853, 30986, 31114, 31238, 31357, + 31471, 31581, 31686, 31786, 31881, 31972, 32058, 32138, 32214, 32286, + 32352, 32413, 32470, 32522, 32568, 32610, 32647, 32679, 32706, 32729, + 32746, 32758, 32766, 32767, 32766, 32758, 32746, 32729, 32706, 32679, + 32647, 32610, 32568, 32522, 32470, 32413, 32352, 32286, 32214, 32138, + 32058, 31972, 31881, 31786, 31686, 31581, 31471, 31357, 31238, 31114, + 30986, 30853, 30715, 30572, 30425, 30274, 30118, 29957, 29792, 29622, + 29448, 29269, 29086, 28899, 28707, 28511, 28311, 28106, 27897, 27684, + 27467, 27246, 27020, 26791, 26557, 26320, 26078, 25833, 25583, 25330, + 25073, 24812, 24548, 24279, 24008, 23732, 23453, 23170, 22884, 22595, + 22302, 22006, 21706, 21403, 21097, 20788, 20475, 20160, 19841, 19520, + 19195, 18868, 18538, 18205, 17869, 17531, 17190, 16846, 16500, 16151, + 15800, 15447, 15091, 14733, 14373, 14010, 13646, 13279, 12910, 12540, + 12167, 11793, 11417, 11039, 10660, 10279, 9896, 9512, 9127, 8740, 8351, + 7962, 7571, 7180, 6787, 6393, 5998, 5602, 5205, 4808, 4410, 4011, 3612, + 3212, 2811, 2411, 2009, 1608, 1206, 804, 402, 0, -402, -804, -1206, + -1608, -2009, -2411, -2811, -3212, -3612, -4011, -4410, -4808, -5205, + -5602, -5998, -6393, -6787, -7180, -7571, -7962, -8351, -8740, -9127, + -9512, -9896, -10279, -10660, -11039, -11417, -11793, -12167, -12540, + -12910, -13279, -13646, -14010, -14373, -14733, -15091, -15447, -15800, + -16151, -16500, -16846, -17190, -17531, -17869, -18205, -18538, -18868, + -19195, -19520, -19841, -20160, -20475, -20788, -21097, -21403, -21706, + -22006, -22302, -22595, -22884, -23170, -23453, -23732, -24008, -24279, + -24548, -24812, -25073, -25330, -25583, -25833, -26078, -26320, -26557, + -26791, -27020, -27246, -27467, -27684, -27897, -28106, -28311, -28511, + -28707, -28899, -29086, -29269, -29448, -29622, -29792, -29957, -30118, + -30274, -30425, -30572, -30715, -30853, -30986, -31114, -31238, -31357, + -31471, -31581, -31686, -31786, -31881, -31972, -32058, -32138, -32214, + -32286, -32352, -32413, -32470, -32522, -32568, -32610, -32647, -32679, + -32706, -32729, -32746, -32758, -32766, -32768, -32766, -32758, -32746, + -32729, -32706, -32679, -32647, -32610, -32568, -32522, -32470, -32413, + -32352, -32286, -32214, -32138, -32058, -31972, -31881, -31786, -31686, + -31581, -31471, -31357, -31238, -31114, -30986, -30853, -30715, -30572, + -30425, -30274, -30118, -29957, -29792, -29622, -29448, -29269, -29086, + -28899, -28707, -28511, -28311, -28106, -27897, -27684, -27467, -27246, + -27020, -26791, -26557, -26320, -26078, -25833, -25583, -25330, -25073, + -24812, -24548, -24279, -24008, -23732, -23453, -23170, -22884, -22595, + -22302, -22006, -21706, -21403, -21097, -20788, -20475, -20160, -19841, + -19520, -19195, -18868, -18538, -18205, -17869, -17531, -17190, -16846, + -16500, -16151, -15800, -15447, -15091, -14733, -14373, -14010, -13646, + -13279, -12910, -12540, -12167, -11793, -11417, -11039, -10660, -10279, + -9896, -9512, -9127, -8740, -8351, -7962, -7571, -7180, -6787, -6393, + -5998, -5602, -5205, -4808, -4410, -4011, -3612, -3212, -2811, -2411, + -2009, -1608, -1206, -804, -402, 0 +}; +#endif /* defined(ARM_ALL_FAST_TABLES) */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +const q31_t sqrtTable_Q31[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5ffffffe, 0x7ffffffa, 0x5e88c596, 0x7a39e2ff, + 0x5d2238d8, 0x74dfa6b1, 0x5bcb268e, 0x6fe69562, + 0x5a827998, 0x6b454dba, 0x5947373a, 0x66f39063, + 0x58187bf8, 0x62ea1669, 0x56f578e6, 0x5f226e5f, + 0x55dd714e, 0x5b96df40, 0x54cfb8b0, 0x58424fca, + 0x53cbb102, 0x552031c7, 0x52d0c92c, 0x522c7048, + 0x51de7bb2, 0x4f6360a9, 0x50f44d86, 0x4cc1b594, + 0x5011cd0a, 0x4a4473f6, 0x4f36911a, 0x47e8e962, + 0x4e62384e, 0x45aca3d0, 0x4d946838, 0x438d6a6a, + 0x4cccccca, 0x41893746, 0x4c0b17c0, 0x3f9e31fa, + 0x4b4f0022, 0x3dcaaac3, 0x4a9841ce, 0x3c0d1660, + 0x49e69d14, 0x3a640a53, 0x4939d654, 0x38ce39a6, + 0x4891b5b2, 0x374a720b, 0x47ee06ba, 0x35d7993c, + 0x474e9830, 0x3474aacc, 0x46b33bc0, 0x3320b60c, + 0x461bc5d2, 0x31dadc4f, 0x45880d4c, 0x30a24f3c, + 0x44f7eb6a, 0x2f764f6a, 0x446b3b92, 0x2e562b0b, + 0x43e1db32, 0x2d413cc9, 0x435ba98a, 0x2c36eab0, + 0x42d887a4, 0x2b36a542, 0x42585824, 0x2a3fe69b, + 0x41daff34, 0x295231b0, 0x41606266, 0x286d118d, + 0x40e868a4, 0x279018c3, 0x4072fa10, 0x26bae0c8, + 0x3ffffffe, 0x25ed0979, 0x3f8f64d2, 0x25263894, + 0x3f2113f8, 0x24661958, 0x3eb4f9d8, 0x23ac5c10, + 0x3e4b03ba, 0x22f8b5bb, 0x3de31fc4, 0x224adfba, + 0x3d7d3cee, 0x21a2977a, 0x3d194ae8, 0x20ff9e30, + 0x3cb73a24, 0x2061b89a, 0x3c56fbba, 0x1fc8aebb, + 0x3bf88166, 0x1f344ba6, 0x3b9bbd80, 0x1ea45d4b, + 0x3b40a2f0, 0x1e18b448, 0x3ae7252e, 0x1d9123b9, + 0x3a8f382c, 0x1d0d8113, 0x3a38d062, 0x1c8da3fb, + 0x39e3e2b6, 0x1c116628, 0x39906482, 0x1b98a33c, + 0x393e4b8a, 0x1b2338aa, 0x38ed8df6, 0x1ab1059a, + 0x389e2250, 0x1a41eace, 0x384fff7a, 0x19d5ca89, + 0x38031cb2, 0x196c887b, 0x37b77184, 0x190609a9, + 0x376cf5ce, 0x18a2345b, 0x3723a1ba, 0x1840f00a, + 0x36db6db6, 0x17e22550, 0x36945276, 0x1785bdd2, + 0x364e48f4, 0x172ba43e, 0x36094a64, 0x16d3c42c, + 0x35c55036, 0x167e0a1f, 0x35825414, 0x162a6372, + 0x35404fde, 0x15d8be4d, 0x34ff3dac, 0x1589099d, + 0x34bf17c4, 0x153b3508, 0x347fd89e, 0x14ef30e4, + 0x34417ade, 0x14a4ee2a, 0x3403f956, 0x145c5e76, + 0x33c74f02, 0x141573fa, 0x338b7706, 0x13d02171, + 0x33506cae, 0x138c5a28, 0x33162b6a, 0x134a11e6, + 0x32dcaed0, 0x13093cee, 0x32a3f294, 0x12c9cffa, + 0x326bf292, 0x128bc034, 0x3234aac0, 0x124f0330, + 0x31fe1736, 0x12138ee5, 0x31c83428, 0x11d959b0, + 0x3192fde6, 0x11a05a45, 0x315e70de, 0x116887b5, + 0x312a8994, 0x1131d960, 0x30f744aa, 0x10fc46fd, + 0x30c49ed6, 0x10c7c88b, 0x309294ea, 0x10945653, + 0x306123cc, 0x1061e8e6, 0x30304878, 0x10307919 +}; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +const q15_t sqrtTable_Q15[256] = { + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x5fff, 0x7fff, 0x5e88, 0x7a39, + 0x5d22, 0x74df, 0x5bcb, 0x6fe6, + 0x5a82, 0x6b45, 0x5947, 0x66f3, + 0x5818, 0x62ea, 0x56f5, 0x5f22, + 0x55dd, 0x5b96, 0x54cf, 0x5842, + 0x53cb, 0x5520, 0x52d0, 0x522c, + 0x51de, 0x4f63, 0x50f4, 0x4cc1, + 0x5011, 0x4a44, 0x4f36, 0x47e8, + 0x4e62, 0x45ac, 0x4d94, 0x438d, + 0x4ccc, 0x4189, 0x4c0b, 0x3f9e, + 0x4b4f, 0x3dca, 0x4a98, 0x3c0d, + 0x49e6, 0x3a64, 0x4939, 0x38ce, + 0x4891, 0x374a, 0x47ee, 0x35d7, + 0x474e, 0x3474, 0x46b3, 0x3320, + 0x461b, 0x31da, 0x4588, 0x30a2, + 0x44f7, 0x2f76, 0x446b, 0x2e56, + 0x43e1, 0x2d41, 0x435b, 0x2c36, + 0x42d8, 0x2b36, 0x4258, 0x2a3f, + 0x41da, 0x2952, 0x4160, 0x286d, + 0x40e8, 0x2790, 0x4072, 0x26ba, + 0x3fff, 0x25ed, 0x3f8f, 0x2526, + 0x3f21, 0x2466, 0x3eb4, 0x23ac, + 0x3e4b, 0x22f8, 0x3de3, 0x224a, + 0x3d7d, 0x21a2, 0x3d19, 0x20ff, + 0x3cb7, 0x2061, 0x3c56, 0x1fc8, + 0x3bf8, 0x1f34, 0x3b9b, 0x1ea4, + 0x3b40, 0x1e18, 0x3ae7, 0x1d91, + 0x3a8f, 0x1d0d, 0x3a38, 0x1c8d, + 0x39e3, 0x1c11, 0x3990, 0x1b98, + 0x393e, 0x1b23, 0x38ed, 0x1ab1, + 0x389e, 0x1a41, 0x384f, 0x19d5, + 0x3803, 0x196c, 0x37b7, 0x1906, + 0x376c, 0x18a2, 0x3723, 0x1840, + 0x36db, 0x17e2, 0x3694, 0x1785, + 0x364e, 0x172b, 0x3609, 0x16d3, + 0x35c5, 0x167e, 0x3582, 0x162a, + 0x3540, 0x15d8, 0x34ff, 0x1589, + 0x34bf, 0x153b, 0x347f, 0x14ef, + 0x3441, 0x14a4, 0x3403, 0x145c, + 0x33c7, 0x1415, 0x338b, 0x13d0, + 0x3350, 0x138c, 0x3316, 0x134a, + 0x32dc, 0x1309, 0x32a3, 0x12c9, + 0x326b, 0x128b, 0x3234, 0x124f, + 0x31fe, 0x1213, 0x31c8, 0x11d9, + 0x3192, 0x11a0, 0x315e, 0x1168, + 0x312a, 0x1131, 0x30f7, 0x10fc, + 0x30c4, 0x10c7, 0x3092, 0x1094, + 0x3061, 0x1061, 0x3030, 0x1030 +}; + #endif +#endif /* defined(ARM_MATH_MVEI) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) +/* +ClearAll[tofix]; +tofix[q_][a_] := With[{r = Round[a*2^q]}, + If[r > (2^q - 1), 2^q - 1, r] + ]; + +(* For q = format, 2^nb is length of the table *) +With[{q = 15, nb = 4, q12quarter = 16^^2000}, + With[{shift = Echo[q - nb]}, + Table[tofix[q][1.0/Sqrt[1.0*i/2^q]/8.0], {i, 2^(q - 2), + 2^q + q12quarter - 1, 2^shift}]] + ] // CopyToClipboard + +*/ +const q31_t sqrt_initial_lut_q31[32]={536870912, 506166750, 480191942, 457845052, 438353264, 421156193, \ +405836263, 392075079, 379625062, 368290407, 357913941, 348367849, \ +339546978, 331363921, 323745341, 316629190, 309962566, 303700050, \ +297802400, 292235509, 286969573, 281978417, 277238947, 272730696, \ +268435456, 264336964, 260420644, 256673389, 253083375, 249639903, \ +246333269, 243154642}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) +const q15_t sqrt_initial_lut_q15[16]={8192, 7327, 6689, 6193, 5793, 5461, 5181, 4940, 4730, 4544, 4379, \ +4230, 4096, 3974, 3862, 3759}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) */ + + +#endif /* #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float32_t exp_tab[8] = { + (1.f), + (0.0416598916054f), + (0.500000596046f), + (0.0014122662833f), + (1.00000011921f), + (0.00833693705499f), + (0.166665703058f), + (0.000195780929062f), +}; + +const float32_t __logf_lut_f32[8] = { + -2.295614848256274, /*p0*/ + -2.470711633419806, /*p4*/ + -5.686926051100417, /*p2*/ + -0.165253547131978, /*p6*/ + +5.175912446351073, /*p1*/ + +0.844006986174912, /*p5*/ + +4.584458825456749, /*p3*/ + +0.014127821926000 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* haming weight LUT for bytes */ +#define B2(n) n, n + 1, n + 1, n + 2 +#define B4(n) B2(n) , B2(n + 1), B2(n + 1), B2(n + 2) +#define B6(n) B4(n) , B4(n + 1), B4(n + 1), B4(n + 2) + +// Lookup table that store the reverse of each table +const unsigned char hwLUT[256] = { B6(0), B6(1), B6(1), B6(2) }; + +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c new file mode 100644 index 0000000..ef14c84 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables_f16.c @@ -0,0 +1,12586 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types_f16.h" +/** + @ingroup ComplexFFT + */ + +/** + @addtogroup CFFT_CIFFT Complex FFT Tables + @{ + */ + + +/** + @brief Floating-point Twiddle factors Table Generation +*/ + +/* F16 */ +#if !defined(__CC_ARM) + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables_f16.h" + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 16 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_16[32] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.923879533f, (float16_t)-0.382683432f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 32 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_32[64] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.980785280f, (float16_t)-0.195090322f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 64 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_64[128] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.995184727f, (float16_t)-0.098017140f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 128 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ + +const float16_t twiddleCoefF16_128[256] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.998795456f, (float16_t)-0.049067674f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 256 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_256[512] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999698819f, (float16_t)-0.024541229f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 512 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_512[1024] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999924702f, (float16_t)-0.012271538f +}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 1024 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_1024[2048] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999981175f, (float16_t)-0.006135885f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 2048 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_2048[4096] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.003067957f, (float16_t)0.999995294f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.009203755f, (float16_t)0.999957645f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.015339206f, (float16_t)0.999882347f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.021474080f, (float16_t)0.999769405f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.027608146f, (float16_t)0.999618822f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.033741172f, (float16_t)0.999430605f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.039872928f, (float16_t)0.999204759f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.046003182f, (float16_t)0.998941293f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.052131705f, (float16_t)0.998640218f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.058258265f, (float16_t)0.998301545f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.064382631f, (float16_t)0.997925286f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.070504573f, (float16_t)0.997511456f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.076623861f, (float16_t)0.997060070f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.082740265f, (float16_t)0.996571146f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.088853553f, (float16_t)0.996044701f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.094963495f, (float16_t)0.995480755f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.101069863f, (float16_t)0.994879331f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.107172425f, (float16_t)0.994240449f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.113270952f, (float16_t)0.993564136f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.119365215f, (float16_t)0.992850414f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.125454983f, (float16_t)0.992099313f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.131540029f, (float16_t)0.991310860f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.137620122f, (float16_t)0.990485084f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.143695033f, (float16_t)0.989622017f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.149764535f, (float16_t)0.988721692f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.155828398f, (float16_t)0.987784142f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.161886394f, (float16_t)0.986809402f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.167938295f, (float16_t)0.985797509f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.173983873f, (float16_t)0.984748502f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.180022901f, (float16_t)0.983662419f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.186055152f, (float16_t)0.982539302f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.192080397f, (float16_t)0.981379193f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.198098411f, (float16_t)0.980182136f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.204108966f, (float16_t)0.978948175f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.210111837f, (float16_t)0.977677358f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.216106797f, (float16_t)0.976369731f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.222093621f, (float16_t)0.975025345f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.228072083f, (float16_t)0.973644250f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.234041959f, (float16_t)0.972226497f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.240003022f, (float16_t)0.970772141f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.245955050f, (float16_t)0.969281235f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.251897818f, (float16_t)0.967753837f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.257831102f, (float16_t)0.966190003f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.263754679f, (float16_t)0.964589793f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.269668326f, (float16_t)0.962953267f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.275571819f, (float16_t)0.961280486f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.281464938f, (float16_t)0.959571513f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.287347460f, (float16_t)0.957826413f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.293219163f, (float16_t)0.956045251f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.299079826f, (float16_t)0.954228095f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.304929230f, (float16_t)0.952375013f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.310767153f, (float16_t)0.950486074f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.316593376f, (float16_t)0.948561350f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.322407679f, (float16_t)0.946600913f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.328209844f, (float16_t)0.944604837f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.333999651f, (float16_t)0.942573198f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.339776884f, (float16_t)0.940506071f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.345541325f, (float16_t)0.938403534f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.351292756f, (float16_t)0.936265667f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.357030961f, (float16_t)0.934092550f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.362755724f, (float16_t)0.931884266f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.368466830f, (float16_t)0.929640896f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.374164063f, (float16_t)0.927362526f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.379847209f, (float16_t)0.925049241f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.385516054f, (float16_t)0.922701128f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.391170384f, (float16_t)0.920318277f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.396809987f, (float16_t)0.917900776f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.402434651f, (float16_t)0.915448716f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.408044163f, (float16_t)0.912962190f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.413638312f, (float16_t)0.910441292f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.419216888f, (float16_t)0.907886116f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.424779681f, (float16_t)0.905296759f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.430326481f, (float16_t)0.902673318f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.435857080f, (float16_t)0.900015892f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.441371269f, (float16_t)0.897324581f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.446868840f, (float16_t)0.894599486f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.452349587f, (float16_t)0.891840709f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.457813304f, (float16_t)0.889048356f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.463259784f, (float16_t)0.886222530f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.468688822f, (float16_t)0.883363339f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.474100215f, (float16_t)0.880470889f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.479493758f, (float16_t)0.877545290f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.484869248f, (float16_t)0.874586652f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.490226483f, (float16_t)0.871595087f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.495565262f, (float16_t)0.868570706f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.500885383f, (float16_t)0.865513624f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.506186645f, (float16_t)0.862423956f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.511468850f, (float16_t)0.859301818f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.516731799f, (float16_t)0.856147328f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.521975293f, (float16_t)0.852960605f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.527199135f, (float16_t)0.849741768f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.532403128f, (float16_t)0.846490939f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.537587076f, (float16_t)0.843208240f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.542750785f, (float16_t)0.839893794f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.547894059f, (float16_t)0.836547727f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.553016706f, (float16_t)0.833170165f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.558118531f, (float16_t)0.829761234f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.563199344f, (float16_t)0.826321063f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.568258953f, (float16_t)0.822849781f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.573297167f, (float16_t)0.819347520f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.578313796f, (float16_t)0.815814411f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.583308653f, (float16_t)0.812250587f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.588281548f, (float16_t)0.808656182f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.593232295f, (float16_t)0.805031331f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.598160707f, (float16_t)0.801376172f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.603066599f, (float16_t)0.797690841f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.607949785f, (float16_t)0.793975478f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.612810082f, (float16_t)0.790230221f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.617647308f, (float16_t)0.786455214f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.622461279f, (float16_t)0.782650596f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.627251815f, (float16_t)0.778816512f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.632018736f, (float16_t)0.774953107f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.636761861f, (float16_t)0.771060524f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.641481013f, (float16_t)0.767138912f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.646176013f, (float16_t)0.763188417f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.650846685f, (float16_t)0.759209189f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.655492853f, (float16_t)0.755201377f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.660114342f, (float16_t)0.751165132f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.664710978f, (float16_t)0.747100606f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.669282588f, (float16_t)0.743007952f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.673829000f, (float16_t)0.738887324f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.678350043f, (float16_t)0.734738878f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.682845546f, (float16_t)0.730562769f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.687315341f, (float16_t)0.726359155f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.691759258f, (float16_t)0.722128194f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.696177131f, (float16_t)0.717870045f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.700568794f, (float16_t)0.713584869f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.704934080f, (float16_t)0.709272826f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.709272826f, (float16_t)0.704934080f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.713584869f, (float16_t)0.700568794f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.717870045f, (float16_t)0.696177131f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.722128194f, (float16_t)0.691759258f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.726359155f, (float16_t)0.687315341f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.730562769f, (float16_t)0.682845546f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.734738878f, (float16_t)0.678350043f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.738887324f, (float16_t)0.673829000f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.743007952f, (float16_t)0.669282588f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.747100606f, (float16_t)0.664710978f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.751165132f, (float16_t)0.660114342f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.755201377f, (float16_t)0.655492853f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.759209189f, (float16_t)0.650846685f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.763188417f, (float16_t)0.646176013f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.767138912f, (float16_t)0.641481013f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.771060524f, (float16_t)0.636761861f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.774953107f, (float16_t)0.632018736f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.778816512f, (float16_t)0.627251815f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.782650596f, (float16_t)0.622461279f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.786455214f, (float16_t)0.617647308f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.790230221f, (float16_t)0.612810082f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.793975478f, (float16_t)0.607949785f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.797690841f, (float16_t)0.603066599f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.801376172f, (float16_t)0.598160707f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.805031331f, (float16_t)0.593232295f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.808656182f, (float16_t)0.588281548f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.812250587f, (float16_t)0.583308653f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.815814411f, (float16_t)0.578313796f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.819347520f, (float16_t)0.573297167f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.822849781f, (float16_t)0.568258953f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.826321063f, (float16_t)0.563199344f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.829761234f, (float16_t)0.558118531f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.833170165f, (float16_t)0.553016706f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.836547727f, (float16_t)0.547894059f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.839893794f, (float16_t)0.542750785f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.843208240f, (float16_t)0.537587076f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.846490939f, (float16_t)0.532403128f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.849741768f, (float16_t)0.527199135f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.852960605f, (float16_t)0.521975293f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.856147328f, (float16_t)0.516731799f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.859301818f, (float16_t)0.511468850f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.862423956f, (float16_t)0.506186645f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.865513624f, (float16_t)0.500885383f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.868570706f, (float16_t)0.495565262f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.871595087f, (float16_t)0.490226483f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.874586652f, (float16_t)0.484869248f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.877545290f, (float16_t)0.479493758f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.880470889f, (float16_t)0.474100215f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.883363339f, (float16_t)0.468688822f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.886222530f, (float16_t)0.463259784f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.889048356f, (float16_t)0.457813304f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.891840709f, (float16_t)0.452349587f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.894599486f, (float16_t)0.446868840f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.897324581f, (float16_t)0.441371269f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.900015892f, (float16_t)0.435857080f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.902673318f, (float16_t)0.430326481f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.905296759f, (float16_t)0.424779681f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.907886116f, (float16_t)0.419216888f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.910441292f, (float16_t)0.413638312f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.912962190f, (float16_t)0.408044163f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.915448716f, (float16_t)0.402434651f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.917900776f, (float16_t)0.396809987f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.920318277f, (float16_t)0.391170384f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.922701128f, (float16_t)0.385516054f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.925049241f, (float16_t)0.379847209f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.927362526f, (float16_t)0.374164063f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.929640896f, (float16_t)0.368466830f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.931884266f, (float16_t)0.362755724f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.934092550f, (float16_t)0.357030961f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.936265667f, (float16_t)0.351292756f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.938403534f, (float16_t)0.345541325f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.940506071f, (float16_t)0.339776884f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.942573198f, (float16_t)0.333999651f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.944604837f, (float16_t)0.328209844f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.946600913f, (float16_t)0.322407679f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.948561350f, (float16_t)0.316593376f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.950486074f, (float16_t)0.310767153f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.952375013f, (float16_t)0.304929230f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.954228095f, (float16_t)0.299079826f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.956045251f, (float16_t)0.293219163f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.957826413f, (float16_t)0.287347460f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.959571513f, (float16_t)0.281464938f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.961280486f, (float16_t)0.275571819f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.962953267f, (float16_t)0.269668326f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.964589793f, (float16_t)0.263754679f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.966190003f, (float16_t)0.257831102f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.967753837f, (float16_t)0.251897818f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.969281235f, (float16_t)0.245955050f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.970772141f, (float16_t)0.240003022f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.972226497f, (float16_t)0.234041959f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.973644250f, (float16_t)0.228072083f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.975025345f, (float16_t)0.222093621f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.976369731f, (float16_t)0.216106797f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.977677358f, (float16_t)0.210111837f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.978948175f, (float16_t)0.204108966f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.980182136f, (float16_t)0.198098411f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981379193f, (float16_t)0.192080397f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.982539302f, (float16_t)0.186055152f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.983662419f, (float16_t)0.180022901f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.984748502f, (float16_t)0.173983873f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.985797509f, (float16_t)0.167938295f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.986809402f, (float16_t)0.161886394f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.987784142f, (float16_t)0.155828398f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.988721692f, (float16_t)0.149764535f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.989622017f, (float16_t)0.143695033f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990485084f, (float16_t)0.137620122f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991310860f, (float16_t)0.131540029f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.992099313f, (float16_t)0.125454983f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.992850414f, (float16_t)0.119365215f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993564136f, (float16_t)0.113270952f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994240449f, (float16_t)0.107172425f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.994879331f, (float16_t)0.101069863f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995480755f, (float16_t)0.094963495f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.996044701f, (float16_t)0.088853553f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996571146f, (float16_t)0.082740265f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.997060070f, (float16_t)0.076623861f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997511456f, (float16_t)0.070504573f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.997925286f, (float16_t)0.064382631f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998301545f, (float16_t)0.058258265f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998640218f, (float16_t)0.052131705f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.998941293f, (float16_t)0.046003182f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999204759f, (float16_t)0.039872928f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999430605f, (float16_t)0.033741172f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999618822f, (float16_t)0.027608146f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999769405f, (float16_t)0.021474080f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999882347f, (float16_t)0.015339206f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999957645f, (float16_t)0.009203755f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-0.999995294f, (float16_t)0.003067957f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999995294f, (float16_t)-0.003067957f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999957645f, (float16_t)-0.009203755f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999882347f, (float16_t)-0.015339206f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999769405f, (float16_t)-0.021474080f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999618822f, (float16_t)-0.027608146f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999430605f, (float16_t)-0.033741172f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999204759f, (float16_t)-0.039872928f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.998941293f, (float16_t)-0.046003182f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998640218f, (float16_t)-0.052131705f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998301545f, (float16_t)-0.058258265f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.997925286f, (float16_t)-0.064382631f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997511456f, (float16_t)-0.070504573f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.997060070f, (float16_t)-0.076623861f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996571146f, (float16_t)-0.082740265f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.996044701f, (float16_t)-0.088853553f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995480755f, (float16_t)-0.094963495f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.994879331f, (float16_t)-0.101069863f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.994240449f, (float16_t)-0.107172425f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993564136f, (float16_t)-0.113270952f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.992850414f, (float16_t)-0.119365215f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.992099313f, (float16_t)-0.125454983f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.991310860f, (float16_t)-0.131540029f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990485084f, (float16_t)-0.137620122f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989622017f, (float16_t)-0.143695033f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988721692f, (float16_t)-0.149764535f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.987784142f, (float16_t)-0.155828398f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.986809402f, (float16_t)-0.161886394f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.985797509f, (float16_t)-0.167938295f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.984748502f, (float16_t)-0.173983873f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983662419f, (float16_t)-0.180022901f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.982539302f, (float16_t)-0.186055152f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.981379193f, (float16_t)-0.192080397f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.980182136f, (float16_t)-0.198098411f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.978948175f, (float16_t)-0.204108966f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977677358f, (float16_t)-0.210111837f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.976369731f, (float16_t)-0.216106797f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.975025345f, (float16_t)-0.222093621f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.973644250f, (float16_t)-0.228072083f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.972226497f, (float16_t)-0.234041959f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.970772141f, (float16_t)-0.240003022f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.969281235f, (float16_t)-0.245955050f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.967753837f, (float16_t)-0.251897818f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.966190003f, (float16_t)-0.257831102f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.964589793f, (float16_t)-0.263754679f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.962953267f, (float16_t)-0.269668326f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.961280486f, (float16_t)-0.275571819f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.959571513f, (float16_t)-0.281464938f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.957826413f, (float16_t)-0.287347460f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.956045251f, (float16_t)-0.293219163f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.954228095f, (float16_t)-0.299079826f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.952375013f, (float16_t)-0.304929230f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.950486074f, (float16_t)-0.310767153f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.948561350f, (float16_t)-0.316593376f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.946600913f, (float16_t)-0.322407679f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.944604837f, (float16_t)-0.328209844f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.942573198f, (float16_t)-0.333999651f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.940506071f, (float16_t)-0.339776884f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.938403534f, (float16_t)-0.345541325f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.936265667f, (float16_t)-0.351292756f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.934092550f, (float16_t)-0.357030961f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.931884266f, (float16_t)-0.362755724f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.929640896f, (float16_t)-0.368466830f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.927362526f, (float16_t)-0.374164063f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.925049241f, (float16_t)-0.379847209f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.922701128f, (float16_t)-0.385516054f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.920318277f, (float16_t)-0.391170384f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.917900776f, (float16_t)-0.396809987f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.915448716f, (float16_t)-0.402434651f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.912962190f, (float16_t)-0.408044163f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.910441292f, (float16_t)-0.413638312f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.907886116f, (float16_t)-0.419216888f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.905296759f, (float16_t)-0.424779681f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.902673318f, (float16_t)-0.430326481f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.900015892f, (float16_t)-0.435857080f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.897324581f, (float16_t)-0.441371269f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.894599486f, (float16_t)-0.446868840f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.891840709f, (float16_t)-0.452349587f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.889048356f, (float16_t)-0.457813304f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.886222530f, (float16_t)-0.463259784f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.883363339f, (float16_t)-0.468688822f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.880470889f, (float16_t)-0.474100215f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.877545290f, (float16_t)-0.479493758f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.874586652f, (float16_t)-0.484869248f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.871595087f, (float16_t)-0.490226483f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.868570706f, (float16_t)-0.495565262f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.865513624f, (float16_t)-0.500885383f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.862423956f, (float16_t)-0.506186645f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.859301818f, (float16_t)-0.511468850f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.856147328f, (float16_t)-0.516731799f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.852960605f, (float16_t)-0.521975293f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.849741768f, (float16_t)-0.527199135f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.846490939f, (float16_t)-0.532403128f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.843208240f, (float16_t)-0.537587076f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.839893794f, (float16_t)-0.542750785f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.836547727f, (float16_t)-0.547894059f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.833170165f, (float16_t)-0.553016706f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.829761234f, (float16_t)-0.558118531f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.826321063f, (float16_t)-0.563199344f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.822849781f, (float16_t)-0.568258953f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.819347520f, (float16_t)-0.573297167f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.815814411f, (float16_t)-0.578313796f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.812250587f, (float16_t)-0.583308653f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.808656182f, (float16_t)-0.588281548f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.805031331f, (float16_t)-0.593232295f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.801376172f, (float16_t)-0.598160707f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.797690841f, (float16_t)-0.603066599f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.793975478f, (float16_t)-0.607949785f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.790230221f, (float16_t)-0.612810082f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.786455214f, (float16_t)-0.617647308f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.782650596f, (float16_t)-0.622461279f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.778816512f, (float16_t)-0.627251815f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.774953107f, (float16_t)-0.632018736f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.771060524f, (float16_t)-0.636761861f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.767138912f, (float16_t)-0.641481013f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.763188417f, (float16_t)-0.646176013f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.759209189f, (float16_t)-0.650846685f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.755201377f, (float16_t)-0.655492853f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.751165132f, (float16_t)-0.660114342f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.747100606f, (float16_t)-0.664710978f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.743007952f, (float16_t)-0.669282588f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.738887324f, (float16_t)-0.673829000f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.734738878f, (float16_t)-0.678350043f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.730562769f, (float16_t)-0.682845546f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.726359155f, (float16_t)-0.687315341f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.722128194f, (float16_t)-0.691759258f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.717870045f, (float16_t)-0.696177131f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.713584869f, (float16_t)-0.700568794f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.709272826f, (float16_t)-0.704934080f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.704934080f, (float16_t)-0.709272826f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.700568794f, (float16_t)-0.713584869f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.696177131f, (float16_t)-0.717870045f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.691759258f, (float16_t)-0.722128194f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.687315341f, (float16_t)-0.726359155f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.682845546f, (float16_t)-0.730562769f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.678350043f, (float16_t)-0.734738878f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.673829000f, (float16_t)-0.738887324f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.669282588f, (float16_t)-0.743007952f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.664710978f, (float16_t)-0.747100606f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.660114342f, (float16_t)-0.751165132f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.655492853f, (float16_t)-0.755201377f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.650846685f, (float16_t)-0.759209189f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.646176013f, (float16_t)-0.763188417f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.641481013f, (float16_t)-0.767138912f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.636761861f, (float16_t)-0.771060524f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.632018736f, (float16_t)-0.774953107f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.627251815f, (float16_t)-0.778816512f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.622461279f, (float16_t)-0.782650596f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.617647308f, (float16_t)-0.786455214f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.612810082f, (float16_t)-0.790230221f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.607949785f, (float16_t)-0.793975478f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.603066599f, (float16_t)-0.797690841f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.598160707f, (float16_t)-0.801376172f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.593232295f, (float16_t)-0.805031331f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.588281548f, (float16_t)-0.808656182f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.583308653f, (float16_t)-0.812250587f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.578313796f, (float16_t)-0.815814411f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.573297167f, (float16_t)-0.819347520f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.568258953f, (float16_t)-0.822849781f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.563199344f, (float16_t)-0.826321063f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.558118531f, (float16_t)-0.829761234f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.553016706f, (float16_t)-0.833170165f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.547894059f, (float16_t)-0.836547727f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.542750785f, (float16_t)-0.839893794f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.537587076f, (float16_t)-0.843208240f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.532403128f, (float16_t)-0.846490939f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.527199135f, (float16_t)-0.849741768f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.521975293f, (float16_t)-0.852960605f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.516731799f, (float16_t)-0.856147328f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.511468850f, (float16_t)-0.859301818f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.506186645f, (float16_t)-0.862423956f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.500885383f, (float16_t)-0.865513624f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.495565262f, (float16_t)-0.868570706f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.490226483f, (float16_t)-0.871595087f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.484869248f, (float16_t)-0.874586652f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.479493758f, (float16_t)-0.877545290f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.474100215f, (float16_t)-0.880470889f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.468688822f, (float16_t)-0.883363339f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.463259784f, (float16_t)-0.886222530f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.457813304f, (float16_t)-0.889048356f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.452349587f, (float16_t)-0.891840709f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.446868840f, (float16_t)-0.894599486f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.441371269f, (float16_t)-0.897324581f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.435857080f, (float16_t)-0.900015892f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.430326481f, (float16_t)-0.902673318f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.424779681f, (float16_t)-0.905296759f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.419216888f, (float16_t)-0.907886116f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.413638312f, (float16_t)-0.910441292f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.408044163f, (float16_t)-0.912962190f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.402434651f, (float16_t)-0.915448716f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.396809987f, (float16_t)-0.917900776f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.391170384f, (float16_t)-0.920318277f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.385516054f, (float16_t)-0.922701128f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.379847209f, (float16_t)-0.925049241f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.374164063f, (float16_t)-0.927362526f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.368466830f, (float16_t)-0.929640896f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.362755724f, (float16_t)-0.931884266f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.357030961f, (float16_t)-0.934092550f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.351292756f, (float16_t)-0.936265667f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.345541325f, (float16_t)-0.938403534f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.339776884f, (float16_t)-0.940506071f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.333999651f, (float16_t)-0.942573198f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.328209844f, (float16_t)-0.944604837f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.322407679f, (float16_t)-0.946600913f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.316593376f, (float16_t)-0.948561350f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.310767153f, (float16_t)-0.950486074f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.304929230f, (float16_t)-0.952375013f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.299079826f, (float16_t)-0.954228095f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.293219163f, (float16_t)-0.956045251f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.287347460f, (float16_t)-0.957826413f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.281464938f, (float16_t)-0.959571513f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.275571819f, (float16_t)-0.961280486f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.269668326f, (float16_t)-0.962953267f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.263754679f, (float16_t)-0.964589793f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.257831102f, (float16_t)-0.966190003f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.251897818f, (float16_t)-0.967753837f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.245955050f, (float16_t)-0.969281235f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.240003022f, (float16_t)-0.970772141f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.234041959f, (float16_t)-0.972226497f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.228072083f, (float16_t)-0.973644250f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.222093621f, (float16_t)-0.975025345f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.216106797f, (float16_t)-0.976369731f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.210111837f, (float16_t)-0.977677358f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.204108966f, (float16_t)-0.978948175f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.198098411f, (float16_t)-0.980182136f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.192080397f, (float16_t)-0.981379193f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.186055152f, (float16_t)-0.982539302f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.180022901f, (float16_t)-0.983662419f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.173983873f, (float16_t)-0.984748502f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.167938295f, (float16_t)-0.985797509f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.161886394f, (float16_t)-0.986809402f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.155828398f, (float16_t)-0.987784142f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.149764535f, (float16_t)-0.988721692f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.143695033f, (float16_t)-0.989622017f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.137620122f, (float16_t)-0.990485084f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.131540029f, (float16_t)-0.991310860f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.125454983f, (float16_t)-0.992099313f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.119365215f, (float16_t)-0.992850414f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.113270952f, (float16_t)-0.993564136f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.107172425f, (float16_t)-0.994240449f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.101069863f, (float16_t)-0.994879331f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.094963495f, (float16_t)-0.995480755f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.088853553f, (float16_t)-0.996044701f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.082740265f, (float16_t)-0.996571146f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.076623861f, (float16_t)-0.997060070f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.070504573f, (float16_t)-0.997511456f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.064382631f, (float16_t)-0.997925286f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.058258265f, (float16_t)-0.998301545f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.052131705f, (float16_t)-0.998640218f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.046003182f, (float16_t)-0.998941293f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.039872928f, (float16_t)-0.999204759f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.033741172f, (float16_t)-0.999430605f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.027608146f, (float16_t)-0.999618822f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.021474080f, (float16_t)-0.999769405f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.015339206f, (float16_t)-0.999882347f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.009203755f, (float16_t)-0.999957645f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.003067957f, (float16_t)-0.999995294f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999995294f, (float16_t)-0.003067957f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + +/** +* \par +* Example code for Floating-point Twiddle factors Generation: +* \par +* 
for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* }
+* \par +* where N = 4096 and PI = 3.14159265358979 +* \par +* Cos and Sin values are in interleaved fashion +* +*/ +const float16_t twiddleCoefF16_4096[8192] = { + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996443051f, (float16_t)0.084268888f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996179829f, (float16_t)0.087325535f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.995907229f, (float16_t)0.090381361f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995625256f, (float16_t)0.093436336f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995333912f, (float16_t)0.096490431f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995033199f, (float16_t)0.099543619f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.994723121f, (float16_t)0.102595869f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994403680f, (float16_t)0.105647154f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994074879f, (float16_t)0.108697444f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.993736722f, (float16_t)0.111746711f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993389211f, (float16_t)0.114794927f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993032350f, (float16_t)0.117842062f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.992666142f, (float16_t)0.120888087f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992290591f, (float16_t)0.123932975f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.991905700f, (float16_t)0.126976696f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991511473f, (float16_t)0.130019223f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991107914f, (float16_t)0.133060525f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.990695025f, (float16_t)0.136100575f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990272812f, (float16_t)0.139139344f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.989841278f, (float16_t)0.142176804f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989400428f, (float16_t)0.145212925f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.988950265f, (float16_t)0.148247679f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988490793f, (float16_t)0.151281038f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988022017f, (float16_t)0.154312973f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.987543942f, (float16_t)0.157343456f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987056571f, (float16_t)0.160372457f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.986559910f, (float16_t)0.163399949f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986053963f, (float16_t)0.166425904f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.985538735f, (float16_t)0.169450291f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985014231f, (float16_t)0.172473084f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.984480455f, (float16_t)0.175494253f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.983937413f, (float16_t)0.178513771f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983385110f, (float16_t)0.181531608f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.982823551f, (float16_t)0.184547737f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.982252741f, (float16_t)0.187562129f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.981672686f, (float16_t)0.190574755f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981083391f, (float16_t)0.193585587f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.980484862f, (float16_t)0.196594598f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.979877104f, (float16_t)0.199601758f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.979260123f, (float16_t)0.202607039f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.978633924f, (float16_t)0.205610413f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.977998515f, (float16_t)0.208611852f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977353900f, (float16_t)0.211611327f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.976700086f, (float16_t)0.214608811f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.976037079f, (float16_t)0.217604275f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.975364885f, (float16_t)0.220597690f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.974683511f, (float16_t)0.223589029f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.973992962f, (float16_t)0.226578264f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.973293246f, (float16_t)0.229565366f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.972584369f, (float16_t)0.232550307f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.971866337f, (float16_t)0.235533059f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.971139158f, (float16_t)0.238513595f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.970402839f, (float16_t)0.241491885f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.969657385f, (float16_t)0.244467903f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.968902805f, (float16_t)0.247441619f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.968139105f, (float16_t)0.250413007f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.967366292f, (float16_t)0.253382037f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.966584374f, (float16_t)0.256348682f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.965793359f, (float16_t)0.259312915f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.964993253f, (float16_t)0.262274707f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.964184064f, (float16_t)0.265234030f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.963365800f, (float16_t)0.268190857f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.962538468f, (float16_t)0.271145160f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.961702077f, (float16_t)0.274096910f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.960856633f, (float16_t)0.277046080f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.960002146f, (float16_t)0.279992643f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.959138622f, (float16_t)0.282936570f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.958266071f, (float16_t)0.285877835f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.957384501f, (float16_t)0.288816408f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.956493919f, (float16_t)0.291752263f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.955594334f, (float16_t)0.294685372f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.954685755f, (float16_t)0.297615707f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.953768190f, (float16_t)0.300543241f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.952841648f, (float16_t)0.303467947f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.951906137f, (float16_t)0.306389795f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.950961666f, (float16_t)0.309308760f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.950008245f, (float16_t)0.312224814f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.949045882f, (float16_t)0.315137929f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.948074586f, (float16_t)0.318048077f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.947094366f, (float16_t)0.320955232f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.946105232f, (float16_t)0.323859367f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.945107193f, (float16_t)0.326760452f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.944100258f, (float16_t)0.329658463f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.943084437f, (float16_t)0.332553370f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.942059740f, (float16_t)0.335445147f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.941026175f, (float16_t)0.338333767f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.939983753f, (float16_t)0.341219202f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.938932484f, (float16_t)0.344101426f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.937872376f, (float16_t)0.346980411f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.936803442f, (float16_t)0.349856130f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.935725689f, (float16_t)0.352728556f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.934639130f, (float16_t)0.355597662f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.933543773f, (float16_t)0.358463421f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.932439629f, (float16_t)0.361325806f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.931326709f, (float16_t)0.364184790f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.930205023f, (float16_t)0.367040346f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.929074581f, (float16_t)0.369892447f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.927935395f, (float16_t)0.372741067f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.926787474f, (float16_t)0.375586178f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.925630831f, (float16_t)0.378427755f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.924465474f, (float16_t)0.381265769f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.923291417f, (float16_t)0.384100195f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.922108669f, (float16_t)0.386931006f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.920917242f, (float16_t)0.389758174f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.919717146f, (float16_t)0.392581674f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.918508394f, (float16_t)0.395401479f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.917290997f, (float16_t)0.398217562f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.916064966f, (float16_t)0.401029897f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.914830312f, (float16_t)0.403838458f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.913587048f, (float16_t)0.406643217f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.912335185f, (float16_t)0.409444149f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.911074734f, (float16_t)0.412241227f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.909805708f, (float16_t)0.415034424f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.908528119f, (float16_t)0.417823716f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.907241978f, (float16_t)0.420609074f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.905947298f, (float16_t)0.423390474f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.904644091f, (float16_t)0.426167889f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.903332368f, (float16_t)0.428941292f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.902012144f, (float16_t)0.431710658f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.900683429f, (float16_t)0.434475961f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.899346237f, (float16_t)0.437237174f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.898000580f, (float16_t)0.439994271f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.896646470f, (float16_t)0.442747228f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.895283921f, (float16_t)0.445496017f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.893912945f, (float16_t)0.448240612f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.892533555f, (float16_t)0.450980989f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.891145765f, (float16_t)0.453717121f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.889749586f, (float16_t)0.456448982f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.888345033f, (float16_t)0.459176548f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.886932119f, (float16_t)0.461899791f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.885510856f, (float16_t)0.464618686f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.884081259f, (float16_t)0.467333209f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.882643340f, (float16_t)0.470043332f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.881197113f, (float16_t)0.472749032f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.879742593f, (float16_t)0.475450282f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.878279792f, (float16_t)0.478147056f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.876808724f, (float16_t)0.480839331f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.875329403f, (float16_t)0.483527079f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.873841843f, (float16_t)0.486210276f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.872346059f, (float16_t)0.488888897f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.870842063f, (float16_t)0.491562916f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.869329871f, (float16_t)0.494232309f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.867809497f, (float16_t)0.496897049f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.866280954f, (float16_t)0.499557113f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.864744258f, (float16_t)0.502212474f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.863199422f, (float16_t)0.504863109f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.861646461f, (float16_t)0.507508991f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.860085390f, (float16_t)0.510150097f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.858516224f, (float16_t)0.512786401f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.856938977f, (float16_t)0.515417878f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.855353665f, (float16_t)0.518044504f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.853760301f, (float16_t)0.520666254f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.852158902f, (float16_t)0.523283103f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.850549481f, (float16_t)0.525895027f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.848932055f, (float16_t)0.528502002f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.847306639f, (float16_t)0.531104001f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.845673247f, (float16_t)0.533701002f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.844031895f, (float16_t)0.536292979f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.842382600f, (float16_t)0.538879909f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.840725375f, (float16_t)0.541461766f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.839060237f, (float16_t)0.544038527f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.837387202f, (float16_t)0.546610167f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.835706284f, (float16_t)0.549176662f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.834017501f, (float16_t)0.551737988f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.832320868f, (float16_t)0.554294121f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.830616400f, (float16_t)0.556845037f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.828904115f, (float16_t)0.559390712f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.827184027f, (float16_t)0.561931121f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.825456154f, (float16_t)0.564466242f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.823720511f, (float16_t)0.566996049f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.821977115f, (float16_t)0.569520519f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.820225983f, (float16_t)0.572039629f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.818467130f, (float16_t)0.574553355f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.816700573f, (float16_t)0.577061673f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.814926329f, (float16_t)0.579564559f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.813144415f, (float16_t)0.582061990f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.811354847f, (float16_t)0.584553943f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.809557642f, (float16_t)0.587040394f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.807752818f, (float16_t)0.589521319f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.805940391f, (float16_t)0.591996695f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.804120377f, (float16_t)0.594466499f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.802292796f, (float16_t)0.596930708f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.800457662f, (float16_t)0.599389298f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.798614995f, (float16_t)0.601842247f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.796764810f, (float16_t)0.604289531f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.794907126f, (float16_t)0.606731127f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.793041960f, (float16_t)0.609167012f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.791169330f, (float16_t)0.611597164f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.789289253f, (float16_t)0.614021559f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.787401747f, (float16_t)0.616440175f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.785506830f, (float16_t)0.618852988f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.783604519f, (float16_t)0.621259977f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.781694832f, (float16_t)0.623661118f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.779777788f, (float16_t)0.626056388f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.777853404f, (float16_t)0.628445767f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.775921699f, (float16_t)0.630829230f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.773982691f, (float16_t)0.633206755f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.772036397f, (float16_t)0.635578320f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.770082837f, (float16_t)0.637943904f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.768122029f, (float16_t)0.640303482f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.766153990f, (float16_t)0.642657034f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.764178741f, (float16_t)0.645004537f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.762196298f, (float16_t)0.647345969f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.760206682f, (float16_t)0.649681307f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.758209910f, (float16_t)0.652010531f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.756206001f, (float16_t)0.654333618f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.754194975f, (float16_t)0.656650546f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.752176850f, (float16_t)0.658961293f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.750151646f, (float16_t)0.661265838f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.748119380f, (float16_t)0.663564159f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.746080074f, (float16_t)0.665856234f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.744033744f, (float16_t)0.668142041f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.741980412f, (float16_t)0.670421560f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.739920095f, (float16_t)0.672694769f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.737852815f, (float16_t)0.674961646f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.735778589f, (float16_t)0.677222170f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.733697438f, (float16_t)0.679476320f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.731609381f, (float16_t)0.681724074f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.729514438f, (float16_t)0.683965412f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.727412629f, (float16_t)0.686200312f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.725303972f, (float16_t)0.688428753f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.723188489f, (float16_t)0.690650714f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.721066199f, (float16_t)0.692866175f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.718937122f, (float16_t)0.695075114f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.716801279f, (float16_t)0.697277511f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.714658688f, (float16_t)0.699473345f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.712509371f, (float16_t)0.701662595f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.710353347f, (float16_t)0.703845241f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.708190637f, (float16_t)0.706021261f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.706021261f, (float16_t)0.708190637f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.703845241f, (float16_t)0.710353347f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.701662595f, (float16_t)0.712509371f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.699473345f, (float16_t)0.714658688f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.697277511f, (float16_t)0.716801279f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.695075114f, (float16_t)0.718937122f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.692866175f, (float16_t)0.721066199f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.690650714f, (float16_t)0.723188489f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.688428753f, (float16_t)0.725303972f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.686200312f, (float16_t)0.727412629f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.683965412f, (float16_t)0.729514438f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.681724074f, (float16_t)0.731609381f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.679476320f, (float16_t)0.733697438f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.677222170f, (float16_t)0.735778589f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.674961646f, (float16_t)0.737852815f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.672694769f, (float16_t)0.739920095f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.670421560f, (float16_t)0.741980412f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.668142041f, (float16_t)0.744033744f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.665856234f, (float16_t)0.746080074f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.663564159f, (float16_t)0.748119380f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.661265838f, (float16_t)0.750151646f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.658961293f, (float16_t)0.752176850f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.656650546f, (float16_t)0.754194975f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.654333618f, (float16_t)0.756206001f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.652010531f, (float16_t)0.758209910f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.649681307f, (float16_t)0.760206682f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.647345969f, (float16_t)0.762196298f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.645004537f, (float16_t)0.764178741f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.642657034f, (float16_t)0.766153990f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.640303482f, (float16_t)0.768122029f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.637943904f, (float16_t)0.770082837f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.635578320f, (float16_t)0.772036397f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.633206755f, (float16_t)0.773982691f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.630829230f, (float16_t)0.775921699f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.628445767f, (float16_t)0.777853404f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.626056388f, (float16_t)0.779777788f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.623661118f, (float16_t)0.781694832f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.621259977f, (float16_t)0.783604519f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.618852988f, (float16_t)0.785506830f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.616440175f, (float16_t)0.787401747f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.614021559f, (float16_t)0.789289253f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.611597164f, (float16_t)0.791169330f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.609167012f, (float16_t)0.793041960f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.606731127f, (float16_t)0.794907126f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.604289531f, (float16_t)0.796764810f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.601842247f, (float16_t)0.798614995f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.599389298f, (float16_t)0.800457662f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.596930708f, (float16_t)0.802292796f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.594466499f, (float16_t)0.804120377f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.591996695f, (float16_t)0.805940391f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.589521319f, (float16_t)0.807752818f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.587040394f, (float16_t)0.809557642f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.584553943f, (float16_t)0.811354847f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.582061990f, (float16_t)0.813144415f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.579564559f, (float16_t)0.814926329f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.577061673f, (float16_t)0.816700573f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.574553355f, (float16_t)0.818467130f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.572039629f, (float16_t)0.820225983f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.569520519f, (float16_t)0.821977115f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.566996049f, (float16_t)0.823720511f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.564466242f, (float16_t)0.825456154f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.561931121f, (float16_t)0.827184027f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.559390712f, (float16_t)0.828904115f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.556845037f, (float16_t)0.830616400f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.554294121f, (float16_t)0.832320868f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.551737988f, (float16_t)0.834017501f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.549176662f, (float16_t)0.835706284f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.546610167f, (float16_t)0.837387202f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.544038527f, (float16_t)0.839060237f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.541461766f, (float16_t)0.840725375f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.538879909f, (float16_t)0.842382600f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.536292979f, (float16_t)0.844031895f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.533701002f, (float16_t)0.845673247f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.531104001f, (float16_t)0.847306639f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.528502002f, (float16_t)0.848932055f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.525895027f, (float16_t)0.850549481f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.523283103f, (float16_t)0.852158902f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.520666254f, (float16_t)0.853760301f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.518044504f, (float16_t)0.855353665f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.515417878f, (float16_t)0.856938977f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.512786401f, (float16_t)0.858516224f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.510150097f, (float16_t)0.860085390f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.507508991f, (float16_t)0.861646461f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.504863109f, (float16_t)0.863199422f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.502212474f, (float16_t)0.864744258f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.499557113f, (float16_t)0.866280954f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.496897049f, (float16_t)0.867809497f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.494232309f, (float16_t)0.869329871f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.491562916f, (float16_t)0.870842063f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.488888897f, (float16_t)0.872346059f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.486210276f, (float16_t)0.873841843f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.483527079f, (float16_t)0.875329403f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.480839331f, (float16_t)0.876808724f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.478147056f, (float16_t)0.878279792f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.475450282f, (float16_t)0.879742593f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.472749032f, (float16_t)0.881197113f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.470043332f, (float16_t)0.882643340f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.467333209f, (float16_t)0.884081259f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.464618686f, (float16_t)0.885510856f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.461899791f, (float16_t)0.886932119f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.459176548f, (float16_t)0.888345033f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.456448982f, (float16_t)0.889749586f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.453717121f, (float16_t)0.891145765f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.450980989f, (float16_t)0.892533555f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.448240612f, (float16_t)0.893912945f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.445496017f, (float16_t)0.895283921f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.442747228f, (float16_t)0.896646470f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.439994271f, (float16_t)0.898000580f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.437237174f, (float16_t)0.899346237f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.434475961f, (float16_t)0.900683429f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.431710658f, (float16_t)0.902012144f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.428941292f, (float16_t)0.903332368f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.426167889f, (float16_t)0.904644091f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.423390474f, (float16_t)0.905947298f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.420609074f, (float16_t)0.907241978f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.417823716f, (float16_t)0.908528119f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.415034424f, (float16_t)0.909805708f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.412241227f, (float16_t)0.911074734f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.409444149f, (float16_t)0.912335185f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.406643217f, (float16_t)0.913587048f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.403838458f, (float16_t)0.914830312f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.401029897f, (float16_t)0.916064966f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.398217562f, (float16_t)0.917290997f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.395401479f, (float16_t)0.918508394f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.392581674f, (float16_t)0.919717146f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.389758174f, (float16_t)0.920917242f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.386931006f, (float16_t)0.922108669f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.384100195f, (float16_t)0.923291417f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.381265769f, (float16_t)0.924465474f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.378427755f, (float16_t)0.925630831f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.375586178f, (float16_t)0.926787474f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.372741067f, (float16_t)0.927935395f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.369892447f, (float16_t)0.929074581f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.367040346f, (float16_t)0.930205023f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.364184790f, (float16_t)0.931326709f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.361325806f, (float16_t)0.932439629f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.358463421f, (float16_t)0.933543773f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.355597662f, (float16_t)0.934639130f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.352728556f, (float16_t)0.935725689f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.349856130f, (float16_t)0.936803442f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.346980411f, (float16_t)0.937872376f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.344101426f, (float16_t)0.938932484f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.341219202f, (float16_t)0.939983753f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.338333767f, (float16_t)0.941026175f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.335445147f, (float16_t)0.942059740f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.332553370f, (float16_t)0.943084437f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.329658463f, (float16_t)0.944100258f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.326760452f, (float16_t)0.945107193f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.323859367f, (float16_t)0.946105232f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.320955232f, (float16_t)0.947094366f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.318048077f, (float16_t)0.948074586f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.315137929f, (float16_t)0.949045882f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.312224814f, (float16_t)0.950008245f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.309308760f, (float16_t)0.950961666f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.306389795f, (float16_t)0.951906137f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.303467947f, (float16_t)0.952841648f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.300543241f, (float16_t)0.953768190f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.297615707f, (float16_t)0.954685755f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.294685372f, (float16_t)0.955594334f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.291752263f, (float16_t)0.956493919f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.288816408f, (float16_t)0.957384501f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.285877835f, (float16_t)0.958266071f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.282936570f, (float16_t)0.959138622f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.279992643f, (float16_t)0.960002146f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.277046080f, (float16_t)0.960856633f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.274096910f, (float16_t)0.961702077f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.271145160f, (float16_t)0.962538468f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.268190857f, (float16_t)0.963365800f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.265234030f, (float16_t)0.964184064f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.262274707f, (float16_t)0.964993253f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.259312915f, (float16_t)0.965793359f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.256348682f, (float16_t)0.966584374f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.253382037f, (float16_t)0.967366292f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.250413007f, (float16_t)0.968139105f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.247441619f, (float16_t)0.968902805f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.244467903f, (float16_t)0.969657385f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.241491885f, (float16_t)0.970402839f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.238513595f, (float16_t)0.971139158f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.235533059f, (float16_t)0.971866337f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.232550307f, (float16_t)0.972584369f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.229565366f, (float16_t)0.973293246f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.226578264f, (float16_t)0.973992962f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.223589029f, (float16_t)0.974683511f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.220597690f, (float16_t)0.975364885f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.217604275f, (float16_t)0.976037079f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.214608811f, (float16_t)0.976700086f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.211611327f, (float16_t)0.977353900f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.208611852f, (float16_t)0.977998515f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.205610413f, (float16_t)0.978633924f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.202607039f, (float16_t)0.979260123f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.199601758f, (float16_t)0.979877104f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.196594598f, (float16_t)0.980484862f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.193585587f, (float16_t)0.981083391f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.190574755f, (float16_t)0.981672686f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.187562129f, (float16_t)0.982252741f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.184547737f, (float16_t)0.982823551f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.181531608f, (float16_t)0.983385110f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.178513771f, (float16_t)0.983937413f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.175494253f, (float16_t)0.984480455f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.172473084f, (float16_t)0.985014231f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.169450291f, (float16_t)0.985538735f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.166425904f, (float16_t)0.986053963f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.163399949f, (float16_t)0.986559910f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.160372457f, (float16_t)0.987056571f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.157343456f, (float16_t)0.987543942f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.154312973f, (float16_t)0.988022017f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.151281038f, (float16_t)0.988490793f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.148247679f, (float16_t)0.988950265f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.145212925f, (float16_t)0.989400428f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.142176804f, (float16_t)0.989841278f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.139139344f, (float16_t)0.990272812f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.136100575f, (float16_t)0.990695025f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.133060525f, (float16_t)0.991107914f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.130019223f, (float16_t)0.991511473f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.126976696f, (float16_t)0.991905700f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.123932975f, (float16_t)0.992290591f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.120888087f, (float16_t)0.992666142f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.117842062f, (float16_t)0.993032350f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.114794927f, (float16_t)0.993389211f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.111746711f, (float16_t)0.993736722f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.108697444f, (float16_t)0.994074879f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.105647154f, (float16_t)0.994403680f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.102595869f, (float16_t)0.994723121f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.099543619f, (float16_t)0.995033199f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.096490431f, (float16_t)0.995333912f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.093436336f, (float16_t)0.995625256f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.090381361f, (float16_t)0.995907229f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.087325535f, (float16_t)0.996179829f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.084268888f, (float16_t)0.996443051f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.081211447f, (float16_t)0.996696895f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.078153242f, (float16_t)0.996941358f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.075094301f, (float16_t)0.997176437f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.072034653f, (float16_t)0.997402130f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)-0.001533980f, (float16_t)0.999998823f, + (float16_t)-0.003067957f, (float16_t)0.999995294f, + (float16_t)-0.004601926f, (float16_t)0.999989411f, + (float16_t)-0.006135885f, (float16_t)0.999981175f, + (float16_t)-0.007669829f, (float16_t)0.999970586f, + (float16_t)-0.009203755f, (float16_t)0.999957645f, + (float16_t)-0.010737659f, (float16_t)0.999942350f, + (float16_t)-0.012271538f, (float16_t)0.999924702f, + (float16_t)-0.013805389f, (float16_t)0.999904701f, + (float16_t)-0.015339206f, (float16_t)0.999882347f, + (float16_t)-0.016872988f, (float16_t)0.999857641f, + (float16_t)-0.018406730f, (float16_t)0.999830582f, + (float16_t)-0.019940429f, (float16_t)0.999801170f, + (float16_t)-0.021474080f, (float16_t)0.999769405f, + (float16_t)-0.023007681f, (float16_t)0.999735288f, + (float16_t)-0.024541229f, (float16_t)0.999698819f, + (float16_t)-0.026074718f, (float16_t)0.999659997f, + (float16_t)-0.027608146f, (float16_t)0.999618822f, + (float16_t)-0.029141509f, (float16_t)0.999575296f, + (float16_t)-0.030674803f, (float16_t)0.999529418f, + (float16_t)-0.032208025f, (float16_t)0.999481187f, + (float16_t)-0.033741172f, (float16_t)0.999430605f, + (float16_t)-0.035274239f, (float16_t)0.999377670f, + (float16_t)-0.036807223f, (float16_t)0.999322385f, + (float16_t)-0.038340120f, (float16_t)0.999264747f, + (float16_t)-0.039872928f, (float16_t)0.999204759f, + (float16_t)-0.041405641f, (float16_t)0.999142419f, + (float16_t)-0.042938257f, (float16_t)0.999077728f, + (float16_t)-0.044470772f, (float16_t)0.999010686f, + (float16_t)-0.046003182f, (float16_t)0.998941293f, + (float16_t)-0.047535484f, (float16_t)0.998869550f, + (float16_t)-0.049067674f, (float16_t)0.998795456f, + (float16_t)-0.050599749f, (float16_t)0.998719012f, + (float16_t)-0.052131705f, (float16_t)0.998640218f, + (float16_t)-0.053663538f, (float16_t)0.998559074f, + (float16_t)-0.055195244f, (float16_t)0.998475581f, + (float16_t)-0.056726821f, (float16_t)0.998389737f, + (float16_t)-0.058258265f, (float16_t)0.998301545f, + (float16_t)-0.059789571f, (float16_t)0.998211003f, + (float16_t)-0.061320736f, (float16_t)0.998118113f, + (float16_t)-0.062851758f, (float16_t)0.998022874f, + (float16_t)-0.064382631f, (float16_t)0.997925286f, + (float16_t)-0.065913353f, (float16_t)0.997825350f, + (float16_t)-0.067443920f, (float16_t)0.997723067f, + (float16_t)-0.068974328f, (float16_t)0.997618435f, + (float16_t)-0.070504573f, (float16_t)0.997511456f, + (float16_t)-0.072034653f, (float16_t)0.997402130f, + (float16_t)-0.073564564f, (float16_t)0.997290457f, + (float16_t)-0.075094301f, (float16_t)0.997176437f, + (float16_t)-0.076623861f, (float16_t)0.997060070f, + (float16_t)-0.078153242f, (float16_t)0.996941358f, + (float16_t)-0.079682438f, (float16_t)0.996820299f, + (float16_t)-0.081211447f, (float16_t)0.996696895f, + (float16_t)-0.082740265f, (float16_t)0.996571146f, + (float16_t)-0.084268888f, (float16_t)0.996443051f, + (float16_t)-0.085797312f, (float16_t)0.996312612f, + (float16_t)-0.087325535f, (float16_t)0.996179829f, + (float16_t)-0.088853553f, (float16_t)0.996044701f, + (float16_t)-0.090381361f, (float16_t)0.995907229f, + (float16_t)-0.091908956f, (float16_t)0.995767414f, + (float16_t)-0.093436336f, (float16_t)0.995625256f, + (float16_t)-0.094963495f, (float16_t)0.995480755f, + (float16_t)-0.096490431f, (float16_t)0.995333912f, + (float16_t)-0.098017140f, (float16_t)0.995184727f, + (float16_t)-0.099543619f, (float16_t)0.995033199f, + (float16_t)-0.101069863f, (float16_t)0.994879331f, + (float16_t)-0.102595869f, (float16_t)0.994723121f, + (float16_t)-0.104121634f, (float16_t)0.994564571f, + (float16_t)-0.105647154f, (float16_t)0.994403680f, + (float16_t)-0.107172425f, (float16_t)0.994240449f, + (float16_t)-0.108697444f, (float16_t)0.994074879f, + (float16_t)-0.110222207f, (float16_t)0.993906970f, + (float16_t)-0.111746711f, (float16_t)0.993736722f, + (float16_t)-0.113270952f, (float16_t)0.993564136f, + (float16_t)-0.114794927f, (float16_t)0.993389211f, + (float16_t)-0.116318631f, (float16_t)0.993211949f, + (float16_t)-0.117842062f, (float16_t)0.993032350f, + (float16_t)-0.119365215f, (float16_t)0.992850414f, + (float16_t)-0.120888087f, (float16_t)0.992666142f, + (float16_t)-0.122410675f, (float16_t)0.992479535f, + (float16_t)-0.123932975f, (float16_t)0.992290591f, + (float16_t)-0.125454983f, (float16_t)0.992099313f, + (float16_t)-0.126976696f, (float16_t)0.991905700f, + (float16_t)-0.128498111f, (float16_t)0.991709754f, + (float16_t)-0.130019223f, (float16_t)0.991511473f, + (float16_t)-0.131540029f, (float16_t)0.991310860f, + (float16_t)-0.133060525f, (float16_t)0.991107914f, + (float16_t)-0.134580709f, (float16_t)0.990902635f, + (float16_t)-0.136100575f, (float16_t)0.990695025f, + (float16_t)-0.137620122f, (float16_t)0.990485084f, + (float16_t)-0.139139344f, (float16_t)0.990272812f, + (float16_t)-0.140658239f, (float16_t)0.990058210f, + (float16_t)-0.142176804f, (float16_t)0.989841278f, + (float16_t)-0.143695033f, (float16_t)0.989622017f, + (float16_t)-0.145212925f, (float16_t)0.989400428f, + (float16_t)-0.146730474f, (float16_t)0.989176510f, + (float16_t)-0.148247679f, (float16_t)0.988950265f, + (float16_t)-0.149764535f, (float16_t)0.988721692f, + (float16_t)-0.151281038f, (float16_t)0.988490793f, + (float16_t)-0.152797185f, (float16_t)0.988257568f, + (float16_t)-0.154312973f, (float16_t)0.988022017f, + (float16_t)-0.155828398f, (float16_t)0.987784142f, + (float16_t)-0.157343456f, (float16_t)0.987543942f, + (float16_t)-0.158858143f, (float16_t)0.987301418f, + (float16_t)-0.160372457f, (float16_t)0.987056571f, + (float16_t)-0.161886394f, (float16_t)0.986809402f, + (float16_t)-0.163399949f, (float16_t)0.986559910f, + (float16_t)-0.164913120f, (float16_t)0.986308097f, + (float16_t)-0.166425904f, (float16_t)0.986053963f, + (float16_t)-0.167938295f, (float16_t)0.985797509f, + (float16_t)-0.169450291f, (float16_t)0.985538735f, + (float16_t)-0.170961889f, (float16_t)0.985277642f, + (float16_t)-0.172473084f, (float16_t)0.985014231f, + (float16_t)-0.173983873f, (float16_t)0.984748502f, + (float16_t)-0.175494253f, (float16_t)0.984480455f, + (float16_t)-0.177004220f, (float16_t)0.984210092f, + (float16_t)-0.178513771f, (float16_t)0.983937413f, + (float16_t)-0.180022901f, (float16_t)0.983662419f, + (float16_t)-0.181531608f, (float16_t)0.983385110f, + (float16_t)-0.183039888f, (float16_t)0.983105487f, + (float16_t)-0.184547737f, (float16_t)0.982823551f, + (float16_t)-0.186055152f, (float16_t)0.982539302f, + (float16_t)-0.187562129f, (float16_t)0.982252741f, + (float16_t)-0.189068664f, (float16_t)0.981963869f, + (float16_t)-0.190574755f, (float16_t)0.981672686f, + (float16_t)-0.192080397f, (float16_t)0.981379193f, + (float16_t)-0.193585587f, (float16_t)0.981083391f, + (float16_t)-0.195090322f, (float16_t)0.980785280f, + (float16_t)-0.196594598f, (float16_t)0.980484862f, + (float16_t)-0.198098411f, (float16_t)0.980182136f, + (float16_t)-0.199601758f, (float16_t)0.979877104f, + (float16_t)-0.201104635f, (float16_t)0.979569766f, + (float16_t)-0.202607039f, (float16_t)0.979260123f, + (float16_t)-0.204108966f, (float16_t)0.978948175f, + (float16_t)-0.205610413f, (float16_t)0.978633924f, + (float16_t)-0.207111376f, (float16_t)0.978317371f, + (float16_t)-0.208611852f, (float16_t)0.977998515f, + (float16_t)-0.210111837f, (float16_t)0.977677358f, + (float16_t)-0.211611327f, (float16_t)0.977353900f, + (float16_t)-0.213110320f, (float16_t)0.977028143f, + (float16_t)-0.214608811f, (float16_t)0.976700086f, + (float16_t)-0.216106797f, (float16_t)0.976369731f, + (float16_t)-0.217604275f, (float16_t)0.976037079f, + (float16_t)-0.219101240f, (float16_t)0.975702130f, + (float16_t)-0.220597690f, (float16_t)0.975364885f, + (float16_t)-0.222093621f, (float16_t)0.975025345f, + (float16_t)-0.223589029f, (float16_t)0.974683511f, + (float16_t)-0.225083911f, (float16_t)0.974339383f, + (float16_t)-0.226578264f, (float16_t)0.973992962f, + (float16_t)-0.228072083f, (float16_t)0.973644250f, + (float16_t)-0.229565366f, (float16_t)0.973293246f, + (float16_t)-0.231058108f, (float16_t)0.972939952f, + (float16_t)-0.232550307f, (float16_t)0.972584369f, + (float16_t)-0.234041959f, (float16_t)0.972226497f, + (float16_t)-0.235533059f, (float16_t)0.971866337f, + (float16_t)-0.237023606f, (float16_t)0.971503891f, + (float16_t)-0.238513595f, (float16_t)0.971139158f, + (float16_t)-0.240003022f, (float16_t)0.970772141f, + (float16_t)-0.241491885f, (float16_t)0.970402839f, + (float16_t)-0.242980180f, (float16_t)0.970031253f, + (float16_t)-0.244467903f, (float16_t)0.969657385f, + (float16_t)-0.245955050f, (float16_t)0.969281235f, + (float16_t)-0.247441619f, (float16_t)0.968902805f, + (float16_t)-0.248927606f, (float16_t)0.968522094f, + (float16_t)-0.250413007f, (float16_t)0.968139105f, + (float16_t)-0.251897818f, (float16_t)0.967753837f, + (float16_t)-0.253382037f, (float16_t)0.967366292f, + (float16_t)-0.254865660f, (float16_t)0.966976471f, + (float16_t)-0.256348682f, (float16_t)0.966584374f, + (float16_t)-0.257831102f, (float16_t)0.966190003f, + (float16_t)-0.259312915f, (float16_t)0.965793359f, + (float16_t)-0.260794118f, (float16_t)0.965394442f, + (float16_t)-0.262274707f, (float16_t)0.964993253f, + (float16_t)-0.263754679f, (float16_t)0.964589793f, + (float16_t)-0.265234030f, (float16_t)0.964184064f, + (float16_t)-0.266712757f, (float16_t)0.963776066f, + (float16_t)-0.268190857f, (float16_t)0.963365800f, + (float16_t)-0.269668326f, (float16_t)0.962953267f, + (float16_t)-0.271145160f, (float16_t)0.962538468f, + (float16_t)-0.272621355f, (float16_t)0.962121404f, + (float16_t)-0.274096910f, (float16_t)0.961702077f, + (float16_t)-0.275571819f, (float16_t)0.961280486f, + (float16_t)-0.277046080f, (float16_t)0.960856633f, + (float16_t)-0.278519689f, (float16_t)0.960430519f, + (float16_t)-0.279992643f, (float16_t)0.960002146f, + (float16_t)-0.281464938f, (float16_t)0.959571513f, + (float16_t)-0.282936570f, (float16_t)0.959138622f, + (float16_t)-0.284407537f, (float16_t)0.958703475f, + (float16_t)-0.285877835f, (float16_t)0.958266071f, + (float16_t)-0.287347460f, (float16_t)0.957826413f, + (float16_t)-0.288816408f, (float16_t)0.957384501f, + (float16_t)-0.290284677f, (float16_t)0.956940336f, + (float16_t)-0.291752263f, (float16_t)0.956493919f, + (float16_t)-0.293219163f, (float16_t)0.956045251f, + (float16_t)-0.294685372f, (float16_t)0.955594334f, + (float16_t)-0.296150888f, (float16_t)0.955141168f, + (float16_t)-0.297615707f, (float16_t)0.954685755f, + (float16_t)-0.299079826f, (float16_t)0.954228095f, + (float16_t)-0.300543241f, (float16_t)0.953768190f, + (float16_t)-0.302005949f, (float16_t)0.953306040f, + (float16_t)-0.303467947f, (float16_t)0.952841648f, + (float16_t)-0.304929230f, (float16_t)0.952375013f, + (float16_t)-0.306389795f, (float16_t)0.951906137f, + (float16_t)-0.307849640f, (float16_t)0.951435021f, + (float16_t)-0.309308760f, (float16_t)0.950961666f, + (float16_t)-0.310767153f, (float16_t)0.950486074f, + (float16_t)-0.312224814f, (float16_t)0.950008245f, + (float16_t)-0.313681740f, (float16_t)0.949528181f, + (float16_t)-0.315137929f, (float16_t)0.949045882f, + (float16_t)-0.316593376f, (float16_t)0.948561350f, + (float16_t)-0.318048077f, (float16_t)0.948074586f, + (float16_t)-0.319502031f, (float16_t)0.947585591f, + (float16_t)-0.320955232f, (float16_t)0.947094366f, + (float16_t)-0.322407679f, (float16_t)0.946600913f, + (float16_t)-0.323859367f, (float16_t)0.946105232f, + (float16_t)-0.325310292f, (float16_t)0.945607325f, + (float16_t)-0.326760452f, (float16_t)0.945107193f, + (float16_t)-0.328209844f, (float16_t)0.944604837f, + (float16_t)-0.329658463f, (float16_t)0.944100258f, + (float16_t)-0.331106306f, (float16_t)0.943593458f, + (float16_t)-0.332553370f, (float16_t)0.943084437f, + (float16_t)-0.333999651f, (float16_t)0.942573198f, + (float16_t)-0.335445147f, (float16_t)0.942059740f, + (float16_t)-0.336889853f, (float16_t)0.941544065f, + (float16_t)-0.338333767f, (float16_t)0.941026175f, + (float16_t)-0.339776884f, (float16_t)0.940506071f, + (float16_t)-0.341219202f, (float16_t)0.939983753f, + (float16_t)-0.342660717f, (float16_t)0.939459224f, + (float16_t)-0.344101426f, (float16_t)0.938932484f, + (float16_t)-0.345541325f, (float16_t)0.938403534f, + (float16_t)-0.346980411f, (float16_t)0.937872376f, + (float16_t)-0.348418680f, (float16_t)0.937339012f, + (float16_t)-0.349856130f, (float16_t)0.936803442f, + (float16_t)-0.351292756f, (float16_t)0.936265667f, + (float16_t)-0.352728556f, (float16_t)0.935725689f, + (float16_t)-0.354163525f, (float16_t)0.935183510f, + (float16_t)-0.355597662f, (float16_t)0.934639130f, + (float16_t)-0.357030961f, (float16_t)0.934092550f, + (float16_t)-0.358463421f, (float16_t)0.933543773f, + (float16_t)-0.359895037f, (float16_t)0.932992799f, + (float16_t)-0.361325806f, (float16_t)0.932439629f, + (float16_t)-0.362755724f, (float16_t)0.931884266f, + (float16_t)-0.364184790f, (float16_t)0.931326709f, + (float16_t)-0.365612998f, (float16_t)0.930766961f, + (float16_t)-0.367040346f, (float16_t)0.930205023f, + (float16_t)-0.368466830f, (float16_t)0.929640896f, + (float16_t)-0.369892447f, (float16_t)0.929074581f, + (float16_t)-0.371317194f, (float16_t)0.928506080f, + (float16_t)-0.372741067f, (float16_t)0.927935395f, + (float16_t)-0.374164063f, (float16_t)0.927362526f, + (float16_t)-0.375586178f, (float16_t)0.926787474f, + (float16_t)-0.377007410f, (float16_t)0.926210242f, + (float16_t)-0.378427755f, (float16_t)0.925630831f, + (float16_t)-0.379847209f, (float16_t)0.925049241f, + (float16_t)-0.381265769f, (float16_t)0.924465474f, + (float16_t)-0.382683432f, (float16_t)0.923879533f, + (float16_t)-0.384100195f, (float16_t)0.923291417f, + (float16_t)-0.385516054f, (float16_t)0.922701128f, + (float16_t)-0.386931006f, (float16_t)0.922108669f, + (float16_t)-0.388345047f, (float16_t)0.921514039f, + (float16_t)-0.389758174f, (float16_t)0.920917242f, + (float16_t)-0.391170384f, (float16_t)0.920318277f, + (float16_t)-0.392581674f, (float16_t)0.919717146f, + (float16_t)-0.393992040f, (float16_t)0.919113852f, + (float16_t)-0.395401479f, (float16_t)0.918508394f, + (float16_t)-0.396809987f, (float16_t)0.917900776f, + (float16_t)-0.398217562f, (float16_t)0.917290997f, + (float16_t)-0.399624200f, (float16_t)0.916679060f, + (float16_t)-0.401029897f, (float16_t)0.916064966f, + (float16_t)-0.402434651f, (float16_t)0.915448716f, + (float16_t)-0.403838458f, (float16_t)0.914830312f, + (float16_t)-0.405241314f, (float16_t)0.914209756f, + (float16_t)-0.406643217f, (float16_t)0.913587048f, + (float16_t)-0.408044163f, (float16_t)0.912962190f, + (float16_t)-0.409444149f, (float16_t)0.912335185f, + (float16_t)-0.410843171f, (float16_t)0.911706032f, + (float16_t)-0.412241227f, (float16_t)0.911074734f, + (float16_t)-0.413638312f, (float16_t)0.910441292f, + (float16_t)-0.415034424f, (float16_t)0.909805708f, + (float16_t)-0.416429560f, (float16_t)0.909167983f, + (float16_t)-0.417823716f, (float16_t)0.908528119f, + (float16_t)-0.419216888f, (float16_t)0.907886116f, + (float16_t)-0.420609074f, (float16_t)0.907241978f, + (float16_t)-0.422000271f, (float16_t)0.906595705f, + (float16_t)-0.423390474f, (float16_t)0.905947298f, + (float16_t)-0.424779681f, (float16_t)0.905296759f, + (float16_t)-0.426167889f, (float16_t)0.904644091f, + (float16_t)-0.427555093f, (float16_t)0.903989293f, + (float16_t)-0.428941292f, (float16_t)0.903332368f, + (float16_t)-0.430326481f, (float16_t)0.902673318f, + (float16_t)-0.431710658f, (float16_t)0.902012144f, + (float16_t)-0.433093819f, (float16_t)0.901348847f, + (float16_t)-0.434475961f, (float16_t)0.900683429f, + (float16_t)-0.435857080f, (float16_t)0.900015892f, + (float16_t)-0.437237174f, (float16_t)0.899346237f, + (float16_t)-0.438616239f, (float16_t)0.898674466f, + (float16_t)-0.439994271f, (float16_t)0.898000580f, + (float16_t)-0.441371269f, (float16_t)0.897324581f, + (float16_t)-0.442747228f, (float16_t)0.896646470f, + (float16_t)-0.444122145f, (float16_t)0.895966250f, + (float16_t)-0.445496017f, (float16_t)0.895283921f, + (float16_t)-0.446868840f, (float16_t)0.894599486f, + (float16_t)-0.448240612f, (float16_t)0.893912945f, + (float16_t)-0.449611330f, (float16_t)0.893224301f, + (float16_t)-0.450980989f, (float16_t)0.892533555f, + (float16_t)-0.452349587f, (float16_t)0.891840709f, + (float16_t)-0.453717121f, (float16_t)0.891145765f, + (float16_t)-0.455083587f, (float16_t)0.890448723f, + (float16_t)-0.456448982f, (float16_t)0.889749586f, + (float16_t)-0.457813304f, (float16_t)0.889048356f, + (float16_t)-0.459176548f, (float16_t)0.888345033f, + (float16_t)-0.460538711f, (float16_t)0.887639620f, + (float16_t)-0.461899791f, (float16_t)0.886932119f, + (float16_t)-0.463259784f, (float16_t)0.886222530f, + (float16_t)-0.464618686f, (float16_t)0.885510856f, + (float16_t)-0.465976496f, (float16_t)0.884797098f, + (float16_t)-0.467333209f, (float16_t)0.884081259f, + (float16_t)-0.468688822f, (float16_t)0.883363339f, + (float16_t)-0.470043332f, (float16_t)0.882643340f, + (float16_t)-0.471396737f, (float16_t)0.881921264f, + (float16_t)-0.472749032f, (float16_t)0.881197113f, + (float16_t)-0.474100215f, (float16_t)0.880470889f, + (float16_t)-0.475450282f, (float16_t)0.879742593f, + (float16_t)-0.476799230f, (float16_t)0.879012226f, + (float16_t)-0.478147056f, (float16_t)0.878279792f, + (float16_t)-0.479493758f, (float16_t)0.877545290f, + (float16_t)-0.480839331f, (float16_t)0.876808724f, + (float16_t)-0.482183772f, (float16_t)0.876070094f, + (float16_t)-0.483527079f, (float16_t)0.875329403f, + (float16_t)-0.484869248f, (float16_t)0.874586652f, + (float16_t)-0.486210276f, (float16_t)0.873841843f, + (float16_t)-0.487550160f, (float16_t)0.873094978f, + (float16_t)-0.488888897f, (float16_t)0.872346059f, + (float16_t)-0.490226483f, (float16_t)0.871595087f, + (float16_t)-0.491562916f, (float16_t)0.870842063f, + (float16_t)-0.492898192f, (float16_t)0.870086991f, + (float16_t)-0.494232309f, (float16_t)0.869329871f, + (float16_t)-0.495565262f, (float16_t)0.868570706f, + (float16_t)-0.496897049f, (float16_t)0.867809497f, + (float16_t)-0.498227667f, (float16_t)0.867046246f, + (float16_t)-0.499557113f, (float16_t)0.866280954f, + (float16_t)-0.500885383f, (float16_t)0.865513624f, + (float16_t)-0.502212474f, (float16_t)0.864744258f, + (float16_t)-0.503538384f, (float16_t)0.863972856f, + (float16_t)-0.504863109f, (float16_t)0.863199422f, + (float16_t)-0.506186645f, (float16_t)0.862423956f, + (float16_t)-0.507508991f, (float16_t)0.861646461f, + (float16_t)-0.508830143f, (float16_t)0.860866939f, + (float16_t)-0.510150097f, (float16_t)0.860085390f, + (float16_t)-0.511468850f, (float16_t)0.859301818f, + (float16_t)-0.512786401f, (float16_t)0.858516224f, + (float16_t)-0.514102744f, (float16_t)0.857728610f, + (float16_t)-0.515417878f, (float16_t)0.856938977f, + (float16_t)-0.516731799f, (float16_t)0.856147328f, + (float16_t)-0.518044504f, (float16_t)0.855353665f, + (float16_t)-0.519355990f, (float16_t)0.854557988f, + (float16_t)-0.520666254f, (float16_t)0.853760301f, + (float16_t)-0.521975293f, (float16_t)0.852960605f, + (float16_t)-0.523283103f, (float16_t)0.852158902f, + (float16_t)-0.524589683f, (float16_t)0.851355193f, + (float16_t)-0.525895027f, (float16_t)0.850549481f, + (float16_t)-0.527199135f, (float16_t)0.849741768f, + (float16_t)-0.528502002f, (float16_t)0.848932055f, + (float16_t)-0.529803625f, (float16_t)0.848120345f, + (float16_t)-0.531104001f, (float16_t)0.847306639f, + (float16_t)-0.532403128f, (float16_t)0.846490939f, + (float16_t)-0.533701002f, (float16_t)0.845673247f, + (float16_t)-0.534997620f, (float16_t)0.844853565f, + (float16_t)-0.536292979f, (float16_t)0.844031895f, + (float16_t)-0.537587076f, (float16_t)0.843208240f, + (float16_t)-0.538879909f, (float16_t)0.842382600f, + (float16_t)-0.540171473f, (float16_t)0.841554977f, + (float16_t)-0.541461766f, (float16_t)0.840725375f, + (float16_t)-0.542750785f, (float16_t)0.839893794f, + (float16_t)-0.544038527f, (float16_t)0.839060237f, + (float16_t)-0.545324988f, (float16_t)0.838224706f, + (float16_t)-0.546610167f, (float16_t)0.837387202f, + (float16_t)-0.547894059f, (float16_t)0.836547727f, + (float16_t)-0.549176662f, (float16_t)0.835706284f, + (float16_t)-0.550457973f, (float16_t)0.834862875f, + (float16_t)-0.551737988f, (float16_t)0.834017501f, + (float16_t)-0.553016706f, (float16_t)0.833170165f, + (float16_t)-0.554294121f, (float16_t)0.832320868f, + (float16_t)-0.555570233f, (float16_t)0.831469612f, + (float16_t)-0.556845037f, (float16_t)0.830616400f, + (float16_t)-0.558118531f, (float16_t)0.829761234f, + (float16_t)-0.559390712f, (float16_t)0.828904115f, + (float16_t)-0.560661576f, (float16_t)0.828045045f, + (float16_t)-0.561931121f, (float16_t)0.827184027f, + (float16_t)-0.563199344f, (float16_t)0.826321063f, + (float16_t)-0.564466242f, (float16_t)0.825456154f, + (float16_t)-0.565731811f, (float16_t)0.824589303f, + (float16_t)-0.566996049f, (float16_t)0.823720511f, + (float16_t)-0.568258953f, (float16_t)0.822849781f, + (float16_t)-0.569520519f, (float16_t)0.821977115f, + (float16_t)-0.570780746f, (float16_t)0.821102515f, + (float16_t)-0.572039629f, (float16_t)0.820225983f, + (float16_t)-0.573297167f, (float16_t)0.819347520f, + (float16_t)-0.574553355f, (float16_t)0.818467130f, + (float16_t)-0.575808191f, (float16_t)0.817584813f, + (float16_t)-0.577061673f, (float16_t)0.816700573f, + (float16_t)-0.578313796f, (float16_t)0.815814411f, + (float16_t)-0.579564559f, (float16_t)0.814926329f, + (float16_t)-0.580813958f, (float16_t)0.814036330f, + (float16_t)-0.582061990f, (float16_t)0.813144415f, + (float16_t)-0.583308653f, (float16_t)0.812250587f, + (float16_t)-0.584553943f, (float16_t)0.811354847f, + (float16_t)-0.585797857f, (float16_t)0.810457198f, + (float16_t)-0.587040394f, (float16_t)0.809557642f, + (float16_t)-0.588281548f, (float16_t)0.808656182f, + (float16_t)-0.589521319f, (float16_t)0.807752818f, + (float16_t)-0.590759702f, (float16_t)0.806847554f, + (float16_t)-0.591996695f, (float16_t)0.805940391f, + (float16_t)-0.593232295f, (float16_t)0.805031331f, + (float16_t)-0.594466499f, (float16_t)0.804120377f, + (float16_t)-0.595699304f, (float16_t)0.803207531f, + (float16_t)-0.596930708f, (float16_t)0.802292796f, + (float16_t)-0.598160707f, (float16_t)0.801376172f, + (float16_t)-0.599389298f, (float16_t)0.800457662f, + (float16_t)-0.600616479f, (float16_t)0.799537269f, + (float16_t)-0.601842247f, (float16_t)0.798614995f, + (float16_t)-0.603066599f, (float16_t)0.797690841f, + (float16_t)-0.604289531f, (float16_t)0.796764810f, + (float16_t)-0.605511041f, (float16_t)0.795836905f, + (float16_t)-0.606731127f, (float16_t)0.794907126f, + (float16_t)-0.607949785f, (float16_t)0.793975478f, + (float16_t)-0.609167012f, (float16_t)0.793041960f, + (float16_t)-0.610382806f, (float16_t)0.792106577f, + (float16_t)-0.611597164f, (float16_t)0.791169330f, + (float16_t)-0.612810082f, (float16_t)0.790230221f, + (float16_t)-0.614021559f, (float16_t)0.789289253f, + (float16_t)-0.615231591f, (float16_t)0.788346428f, + (float16_t)-0.616440175f, (float16_t)0.787401747f, + (float16_t)-0.617647308f, (float16_t)0.786455214f, + (float16_t)-0.618852988f, (float16_t)0.785506830f, + (float16_t)-0.620057212f, (float16_t)0.784556597f, + (float16_t)-0.621259977f, (float16_t)0.783604519f, + (float16_t)-0.622461279f, (float16_t)0.782650596f, + (float16_t)-0.623661118f, (float16_t)0.781694832f, + (float16_t)-0.624859488f, (float16_t)0.780737229f, + (float16_t)-0.626056388f, (float16_t)0.779777788f, + (float16_t)-0.627251815f, (float16_t)0.778816512f, + (float16_t)-0.628445767f, (float16_t)0.777853404f, + (float16_t)-0.629638239f, (float16_t)0.776888466f, + (float16_t)-0.630829230f, (float16_t)0.775921699f, + (float16_t)-0.632018736f, (float16_t)0.774953107f, + (float16_t)-0.633206755f, (float16_t)0.773982691f, + (float16_t)-0.634393284f, (float16_t)0.773010453f, + (float16_t)-0.635578320f, (float16_t)0.772036397f, + (float16_t)-0.636761861f, (float16_t)0.771060524f, + (float16_t)-0.637943904f, (float16_t)0.770082837f, + (float16_t)-0.639124445f, (float16_t)0.769103338f, + (float16_t)-0.640303482f, (float16_t)0.768122029f, + (float16_t)-0.641481013f, (float16_t)0.767138912f, + (float16_t)-0.642657034f, (float16_t)0.766153990f, + (float16_t)-0.643831543f, (float16_t)0.765167266f, + (float16_t)-0.645004537f, (float16_t)0.764178741f, + (float16_t)-0.646176013f, (float16_t)0.763188417f, + (float16_t)-0.647345969f, (float16_t)0.762196298f, + (float16_t)-0.648514401f, (float16_t)0.761202385f, + (float16_t)-0.649681307f, (float16_t)0.760206682f, + (float16_t)-0.650846685f, (float16_t)0.759209189f, + (float16_t)-0.652010531f, (float16_t)0.758209910f, + (float16_t)-0.653172843f, (float16_t)0.757208847f, + (float16_t)-0.654333618f, (float16_t)0.756206001f, + (float16_t)-0.655492853f, (float16_t)0.755201377f, + (float16_t)-0.656650546f, (float16_t)0.754194975f, + (float16_t)-0.657806693f, (float16_t)0.753186799f, + (float16_t)-0.658961293f, (float16_t)0.752176850f, + (float16_t)-0.660114342f, (float16_t)0.751165132f, + (float16_t)-0.661265838f, (float16_t)0.750151646f, + (float16_t)-0.662415778f, (float16_t)0.749136395f, + (float16_t)-0.663564159f, (float16_t)0.748119380f, + (float16_t)-0.664710978f, (float16_t)0.747100606f, + (float16_t)-0.665856234f, (float16_t)0.746080074f, + (float16_t)-0.666999922f, (float16_t)0.745057785f, + (float16_t)-0.668142041f, (float16_t)0.744033744f, + (float16_t)-0.669282588f, (float16_t)0.743007952f, + (float16_t)-0.670421560f, (float16_t)0.741980412f, + (float16_t)-0.671558955f, (float16_t)0.740951125f, + (float16_t)-0.672694769f, (float16_t)0.739920095f, + (float16_t)-0.673829000f, (float16_t)0.738887324f, + (float16_t)-0.674961646f, (float16_t)0.737852815f, + (float16_t)-0.676092704f, (float16_t)0.736816569f, + (float16_t)-0.677222170f, (float16_t)0.735778589f, + (float16_t)-0.678350043f, (float16_t)0.734738878f, + (float16_t)-0.679476320f, (float16_t)0.733697438f, + (float16_t)-0.680600998f, (float16_t)0.732654272f, + (float16_t)-0.681724074f, (float16_t)0.731609381f, + (float16_t)-0.682845546f, (float16_t)0.730562769f, + (float16_t)-0.683965412f, (float16_t)0.729514438f, + (float16_t)-0.685083668f, (float16_t)0.728464390f, + (float16_t)-0.686200312f, (float16_t)0.727412629f, + (float16_t)-0.687315341f, (float16_t)0.726359155f, + (float16_t)-0.688428753f, (float16_t)0.725303972f, + (float16_t)-0.689540545f, (float16_t)0.724247083f, + (float16_t)-0.690650714f, (float16_t)0.723188489f, + (float16_t)-0.691759258f, (float16_t)0.722128194f, + (float16_t)-0.692866175f, (float16_t)0.721066199f, + (float16_t)-0.693971461f, (float16_t)0.720002508f, + (float16_t)-0.695075114f, (float16_t)0.718937122f, + (float16_t)-0.696177131f, (float16_t)0.717870045f, + (float16_t)-0.697277511f, (float16_t)0.716801279f, + (float16_t)-0.698376249f, (float16_t)0.715730825f, + (float16_t)-0.699473345f, (float16_t)0.714658688f, + (float16_t)-0.700568794f, (float16_t)0.713584869f, + (float16_t)-0.701662595f, (float16_t)0.712509371f, + (float16_t)-0.702754744f, (float16_t)0.711432196f, + (float16_t)-0.703845241f, (float16_t)0.710353347f, + (float16_t)-0.704934080f, (float16_t)0.709272826f, + (float16_t)-0.706021261f, (float16_t)0.708190637f, + (float16_t)-0.707106781f, (float16_t)0.707106781f, + (float16_t)-0.708190637f, (float16_t)0.706021261f, + (float16_t)-0.709272826f, (float16_t)0.704934080f, + (float16_t)-0.710353347f, (float16_t)0.703845241f, + (float16_t)-0.711432196f, (float16_t)0.702754744f, + (float16_t)-0.712509371f, (float16_t)0.701662595f, + (float16_t)-0.713584869f, (float16_t)0.700568794f, + (float16_t)-0.714658688f, (float16_t)0.699473345f, + (float16_t)-0.715730825f, (float16_t)0.698376249f, + (float16_t)-0.716801279f, (float16_t)0.697277511f, + (float16_t)-0.717870045f, (float16_t)0.696177131f, + (float16_t)-0.718937122f, (float16_t)0.695075114f, + (float16_t)-0.720002508f, (float16_t)0.693971461f, + (float16_t)-0.721066199f, (float16_t)0.692866175f, + (float16_t)-0.722128194f, (float16_t)0.691759258f, + (float16_t)-0.723188489f, (float16_t)0.690650714f, + (float16_t)-0.724247083f, (float16_t)0.689540545f, + (float16_t)-0.725303972f, (float16_t)0.688428753f, + (float16_t)-0.726359155f, (float16_t)0.687315341f, + (float16_t)-0.727412629f, (float16_t)0.686200312f, + (float16_t)-0.728464390f, (float16_t)0.685083668f, + (float16_t)-0.729514438f, (float16_t)0.683965412f, + (float16_t)-0.730562769f, (float16_t)0.682845546f, + (float16_t)-0.731609381f, (float16_t)0.681724074f, + (float16_t)-0.732654272f, (float16_t)0.680600998f, + (float16_t)-0.733697438f, (float16_t)0.679476320f, + (float16_t)-0.734738878f, (float16_t)0.678350043f, + (float16_t)-0.735778589f, (float16_t)0.677222170f, + (float16_t)-0.736816569f, (float16_t)0.676092704f, + (float16_t)-0.737852815f, (float16_t)0.674961646f, + (float16_t)-0.738887324f, (float16_t)0.673829000f, + (float16_t)-0.739920095f, (float16_t)0.672694769f, + (float16_t)-0.740951125f, (float16_t)0.671558955f, + (float16_t)-0.741980412f, (float16_t)0.670421560f, + (float16_t)-0.743007952f, (float16_t)0.669282588f, + (float16_t)-0.744033744f, (float16_t)0.668142041f, + (float16_t)-0.745057785f, (float16_t)0.666999922f, + (float16_t)-0.746080074f, (float16_t)0.665856234f, + (float16_t)-0.747100606f, (float16_t)0.664710978f, + (float16_t)-0.748119380f, (float16_t)0.663564159f, + (float16_t)-0.749136395f, (float16_t)0.662415778f, + (float16_t)-0.750151646f, (float16_t)0.661265838f, + (float16_t)-0.751165132f, (float16_t)0.660114342f, + (float16_t)-0.752176850f, (float16_t)0.658961293f, + (float16_t)-0.753186799f, (float16_t)0.657806693f, + (float16_t)-0.754194975f, (float16_t)0.656650546f, + (float16_t)-0.755201377f, (float16_t)0.655492853f, + (float16_t)-0.756206001f, (float16_t)0.654333618f, + (float16_t)-0.757208847f, (float16_t)0.653172843f, + (float16_t)-0.758209910f, (float16_t)0.652010531f, + (float16_t)-0.759209189f, (float16_t)0.650846685f, + (float16_t)-0.760206682f, (float16_t)0.649681307f, + (float16_t)-0.761202385f, (float16_t)0.648514401f, + (float16_t)-0.762196298f, (float16_t)0.647345969f, + (float16_t)-0.763188417f, (float16_t)0.646176013f, + (float16_t)-0.764178741f, (float16_t)0.645004537f, + (float16_t)-0.765167266f, (float16_t)0.643831543f, + (float16_t)-0.766153990f, (float16_t)0.642657034f, + (float16_t)-0.767138912f, (float16_t)0.641481013f, + (float16_t)-0.768122029f, (float16_t)0.640303482f, + (float16_t)-0.769103338f, (float16_t)0.639124445f, + (float16_t)-0.770082837f, (float16_t)0.637943904f, + (float16_t)-0.771060524f, (float16_t)0.636761861f, + (float16_t)-0.772036397f, (float16_t)0.635578320f, + (float16_t)-0.773010453f, (float16_t)0.634393284f, + (float16_t)-0.773982691f, (float16_t)0.633206755f, + (float16_t)-0.774953107f, (float16_t)0.632018736f, + (float16_t)-0.775921699f, (float16_t)0.630829230f, + (float16_t)-0.776888466f, (float16_t)0.629638239f, + (float16_t)-0.777853404f, (float16_t)0.628445767f, + (float16_t)-0.778816512f, (float16_t)0.627251815f, + (float16_t)-0.779777788f, (float16_t)0.626056388f, + (float16_t)-0.780737229f, (float16_t)0.624859488f, + (float16_t)-0.781694832f, (float16_t)0.623661118f, + (float16_t)-0.782650596f, (float16_t)0.622461279f, + (float16_t)-0.783604519f, (float16_t)0.621259977f, + (float16_t)-0.784556597f, (float16_t)0.620057212f, + (float16_t)-0.785506830f, (float16_t)0.618852988f, + (float16_t)-0.786455214f, (float16_t)0.617647308f, + (float16_t)-0.787401747f, (float16_t)0.616440175f, + (float16_t)-0.788346428f, (float16_t)0.615231591f, + (float16_t)-0.789289253f, (float16_t)0.614021559f, + (float16_t)-0.790230221f, (float16_t)0.612810082f, + (float16_t)-0.791169330f, (float16_t)0.611597164f, + (float16_t)-0.792106577f, (float16_t)0.610382806f, + (float16_t)-0.793041960f, (float16_t)0.609167012f, + (float16_t)-0.793975478f, (float16_t)0.607949785f, + (float16_t)-0.794907126f, (float16_t)0.606731127f, + (float16_t)-0.795836905f, (float16_t)0.605511041f, + (float16_t)-0.796764810f, (float16_t)0.604289531f, + (float16_t)-0.797690841f, (float16_t)0.603066599f, + (float16_t)-0.798614995f, (float16_t)0.601842247f, + (float16_t)-0.799537269f, (float16_t)0.600616479f, + (float16_t)-0.800457662f, (float16_t)0.599389298f, + (float16_t)-0.801376172f, (float16_t)0.598160707f, + (float16_t)-0.802292796f, (float16_t)0.596930708f, + (float16_t)-0.803207531f, (float16_t)0.595699304f, + (float16_t)-0.804120377f, (float16_t)0.594466499f, + (float16_t)-0.805031331f, (float16_t)0.593232295f, + (float16_t)-0.805940391f, (float16_t)0.591996695f, + (float16_t)-0.806847554f, (float16_t)0.590759702f, + (float16_t)-0.807752818f, (float16_t)0.589521319f, + (float16_t)-0.808656182f, (float16_t)0.588281548f, + (float16_t)-0.809557642f, (float16_t)0.587040394f, + (float16_t)-0.810457198f, (float16_t)0.585797857f, + (float16_t)-0.811354847f, (float16_t)0.584553943f, + (float16_t)-0.812250587f, (float16_t)0.583308653f, + (float16_t)-0.813144415f, (float16_t)0.582061990f, + (float16_t)-0.814036330f, (float16_t)0.580813958f, + (float16_t)-0.814926329f, (float16_t)0.579564559f, + (float16_t)-0.815814411f, (float16_t)0.578313796f, + (float16_t)-0.816700573f, (float16_t)0.577061673f, + (float16_t)-0.817584813f, (float16_t)0.575808191f, + (float16_t)-0.818467130f, (float16_t)0.574553355f, + (float16_t)-0.819347520f, (float16_t)0.573297167f, + (float16_t)-0.820225983f, (float16_t)0.572039629f, + (float16_t)-0.821102515f, (float16_t)0.570780746f, + (float16_t)-0.821977115f, (float16_t)0.569520519f, + (float16_t)-0.822849781f, (float16_t)0.568258953f, + (float16_t)-0.823720511f, (float16_t)0.566996049f, + (float16_t)-0.824589303f, (float16_t)0.565731811f, + (float16_t)-0.825456154f, (float16_t)0.564466242f, + (float16_t)-0.826321063f, (float16_t)0.563199344f, + (float16_t)-0.827184027f, (float16_t)0.561931121f, + (float16_t)-0.828045045f, (float16_t)0.560661576f, + (float16_t)-0.828904115f, (float16_t)0.559390712f, + (float16_t)-0.829761234f, (float16_t)0.558118531f, + (float16_t)-0.830616400f, (float16_t)0.556845037f, + (float16_t)-0.831469612f, (float16_t)0.555570233f, + (float16_t)-0.832320868f, (float16_t)0.554294121f, + (float16_t)-0.833170165f, (float16_t)0.553016706f, + (float16_t)-0.834017501f, (float16_t)0.551737988f, + (float16_t)-0.834862875f, (float16_t)0.550457973f, + (float16_t)-0.835706284f, (float16_t)0.549176662f, + (float16_t)-0.836547727f, (float16_t)0.547894059f, + (float16_t)-0.837387202f, (float16_t)0.546610167f, + (float16_t)-0.838224706f, (float16_t)0.545324988f, + (float16_t)-0.839060237f, (float16_t)0.544038527f, + (float16_t)-0.839893794f, (float16_t)0.542750785f, + (float16_t)-0.840725375f, (float16_t)0.541461766f, + (float16_t)-0.841554977f, (float16_t)0.540171473f, + (float16_t)-0.842382600f, (float16_t)0.538879909f, + (float16_t)-0.843208240f, (float16_t)0.537587076f, + (float16_t)-0.844031895f, (float16_t)0.536292979f, + (float16_t)-0.844853565f, (float16_t)0.534997620f, + (float16_t)-0.845673247f, (float16_t)0.533701002f, + (float16_t)-0.846490939f, (float16_t)0.532403128f, + (float16_t)-0.847306639f, (float16_t)0.531104001f, + (float16_t)-0.848120345f, (float16_t)0.529803625f, + (float16_t)-0.848932055f, (float16_t)0.528502002f, + (float16_t)-0.849741768f, (float16_t)0.527199135f, + (float16_t)-0.850549481f, (float16_t)0.525895027f, + (float16_t)-0.851355193f, (float16_t)0.524589683f, + (float16_t)-0.852158902f, (float16_t)0.523283103f, + (float16_t)-0.852960605f, (float16_t)0.521975293f, + (float16_t)-0.853760301f, (float16_t)0.520666254f, + (float16_t)-0.854557988f, (float16_t)0.519355990f, + (float16_t)-0.855353665f, (float16_t)0.518044504f, + (float16_t)-0.856147328f, (float16_t)0.516731799f, + (float16_t)-0.856938977f, (float16_t)0.515417878f, + (float16_t)-0.857728610f, (float16_t)0.514102744f, + (float16_t)-0.858516224f, (float16_t)0.512786401f, + (float16_t)-0.859301818f, (float16_t)0.511468850f, + (float16_t)-0.860085390f, (float16_t)0.510150097f, + (float16_t)-0.860866939f, (float16_t)0.508830143f, + (float16_t)-0.861646461f, (float16_t)0.507508991f, + (float16_t)-0.862423956f, (float16_t)0.506186645f, + (float16_t)-0.863199422f, (float16_t)0.504863109f, + (float16_t)-0.863972856f, (float16_t)0.503538384f, + (float16_t)-0.864744258f, (float16_t)0.502212474f, + (float16_t)-0.865513624f, (float16_t)0.500885383f, + (float16_t)-0.866280954f, (float16_t)0.499557113f, + (float16_t)-0.867046246f, (float16_t)0.498227667f, + (float16_t)-0.867809497f, (float16_t)0.496897049f, + (float16_t)-0.868570706f, (float16_t)0.495565262f, + (float16_t)-0.869329871f, (float16_t)0.494232309f, + (float16_t)-0.870086991f, (float16_t)0.492898192f, + (float16_t)-0.870842063f, (float16_t)0.491562916f, + (float16_t)-0.871595087f, (float16_t)0.490226483f, + (float16_t)-0.872346059f, (float16_t)0.488888897f, + (float16_t)-0.873094978f, (float16_t)0.487550160f, + (float16_t)-0.873841843f, (float16_t)0.486210276f, + (float16_t)-0.874586652f, (float16_t)0.484869248f, + (float16_t)-0.875329403f, (float16_t)0.483527079f, + (float16_t)-0.876070094f, (float16_t)0.482183772f, + (float16_t)-0.876808724f, (float16_t)0.480839331f, + (float16_t)-0.877545290f, (float16_t)0.479493758f, + (float16_t)-0.878279792f, (float16_t)0.478147056f, + (float16_t)-0.879012226f, (float16_t)0.476799230f, + (float16_t)-0.879742593f, (float16_t)0.475450282f, + (float16_t)-0.880470889f, (float16_t)0.474100215f, + (float16_t)-0.881197113f, (float16_t)0.472749032f, + (float16_t)-0.881921264f, (float16_t)0.471396737f, + (float16_t)-0.882643340f, (float16_t)0.470043332f, + (float16_t)-0.883363339f, (float16_t)0.468688822f, + (float16_t)-0.884081259f, (float16_t)0.467333209f, + (float16_t)-0.884797098f, (float16_t)0.465976496f, + (float16_t)-0.885510856f, (float16_t)0.464618686f, + (float16_t)-0.886222530f, (float16_t)0.463259784f, + (float16_t)-0.886932119f, (float16_t)0.461899791f, + (float16_t)-0.887639620f, (float16_t)0.460538711f, + (float16_t)-0.888345033f, (float16_t)0.459176548f, + (float16_t)-0.889048356f, (float16_t)0.457813304f, + (float16_t)-0.889749586f, (float16_t)0.456448982f, + (float16_t)-0.890448723f, (float16_t)0.455083587f, + (float16_t)-0.891145765f, (float16_t)0.453717121f, + (float16_t)-0.891840709f, (float16_t)0.452349587f, + (float16_t)-0.892533555f, (float16_t)0.450980989f, + (float16_t)-0.893224301f, (float16_t)0.449611330f, + (float16_t)-0.893912945f, (float16_t)0.448240612f, + (float16_t)-0.894599486f, (float16_t)0.446868840f, + (float16_t)-0.895283921f, (float16_t)0.445496017f, + (float16_t)-0.895966250f, (float16_t)0.444122145f, + (float16_t)-0.896646470f, (float16_t)0.442747228f, + (float16_t)-0.897324581f, (float16_t)0.441371269f, + (float16_t)-0.898000580f, (float16_t)0.439994271f, + (float16_t)-0.898674466f, (float16_t)0.438616239f, + (float16_t)-0.899346237f, (float16_t)0.437237174f, + (float16_t)-0.900015892f, (float16_t)0.435857080f, + (float16_t)-0.900683429f, (float16_t)0.434475961f, + (float16_t)-0.901348847f, (float16_t)0.433093819f, + (float16_t)-0.902012144f, (float16_t)0.431710658f, + (float16_t)-0.902673318f, (float16_t)0.430326481f, + (float16_t)-0.903332368f, (float16_t)0.428941292f, + (float16_t)-0.903989293f, (float16_t)0.427555093f, + (float16_t)-0.904644091f, (float16_t)0.426167889f, + (float16_t)-0.905296759f, (float16_t)0.424779681f, + (float16_t)-0.905947298f, (float16_t)0.423390474f, + (float16_t)-0.906595705f, (float16_t)0.422000271f, + (float16_t)-0.907241978f, (float16_t)0.420609074f, + (float16_t)-0.907886116f, (float16_t)0.419216888f, + (float16_t)-0.908528119f, (float16_t)0.417823716f, + (float16_t)-0.909167983f, (float16_t)0.416429560f, + (float16_t)-0.909805708f, (float16_t)0.415034424f, + (float16_t)-0.910441292f, (float16_t)0.413638312f, + (float16_t)-0.911074734f, (float16_t)0.412241227f, + (float16_t)-0.911706032f, (float16_t)0.410843171f, + (float16_t)-0.912335185f, (float16_t)0.409444149f, + (float16_t)-0.912962190f, (float16_t)0.408044163f, + (float16_t)-0.913587048f, (float16_t)0.406643217f, + (float16_t)-0.914209756f, (float16_t)0.405241314f, + (float16_t)-0.914830312f, (float16_t)0.403838458f, + (float16_t)-0.915448716f, (float16_t)0.402434651f, + (float16_t)-0.916064966f, (float16_t)0.401029897f, + (float16_t)-0.916679060f, (float16_t)0.399624200f, + (float16_t)-0.917290997f, (float16_t)0.398217562f, + (float16_t)-0.917900776f, (float16_t)0.396809987f, + (float16_t)-0.918508394f, (float16_t)0.395401479f, + (float16_t)-0.919113852f, (float16_t)0.393992040f, + (float16_t)-0.919717146f, (float16_t)0.392581674f, + (float16_t)-0.920318277f, (float16_t)0.391170384f, + (float16_t)-0.920917242f, (float16_t)0.389758174f, + (float16_t)-0.921514039f, (float16_t)0.388345047f, + (float16_t)-0.922108669f, (float16_t)0.386931006f, + (float16_t)-0.922701128f, (float16_t)0.385516054f, + (float16_t)-0.923291417f, (float16_t)0.384100195f, + (float16_t)-0.923879533f, (float16_t)0.382683432f, + (float16_t)-0.924465474f, (float16_t)0.381265769f, + (float16_t)-0.925049241f, (float16_t)0.379847209f, + (float16_t)-0.925630831f, (float16_t)0.378427755f, + (float16_t)-0.926210242f, (float16_t)0.377007410f, + (float16_t)-0.926787474f, (float16_t)0.375586178f, + (float16_t)-0.927362526f, (float16_t)0.374164063f, + (float16_t)-0.927935395f, (float16_t)0.372741067f, + (float16_t)-0.928506080f, (float16_t)0.371317194f, + (float16_t)-0.929074581f, (float16_t)0.369892447f, + (float16_t)-0.929640896f, (float16_t)0.368466830f, + (float16_t)-0.930205023f, (float16_t)0.367040346f, + (float16_t)-0.930766961f, (float16_t)0.365612998f, + (float16_t)-0.931326709f, (float16_t)0.364184790f, + (float16_t)-0.931884266f, (float16_t)0.362755724f, + (float16_t)-0.932439629f, (float16_t)0.361325806f, + (float16_t)-0.932992799f, (float16_t)0.359895037f, + (float16_t)-0.933543773f, (float16_t)0.358463421f, + (float16_t)-0.934092550f, (float16_t)0.357030961f, + (float16_t)-0.934639130f, (float16_t)0.355597662f, + (float16_t)-0.935183510f, (float16_t)0.354163525f, + (float16_t)-0.935725689f, (float16_t)0.352728556f, + (float16_t)-0.936265667f, (float16_t)0.351292756f, + (float16_t)-0.936803442f, (float16_t)0.349856130f, + (float16_t)-0.937339012f, (float16_t)0.348418680f, + (float16_t)-0.937872376f, (float16_t)0.346980411f, + (float16_t)-0.938403534f, (float16_t)0.345541325f, + (float16_t)-0.938932484f, (float16_t)0.344101426f, + (float16_t)-0.939459224f, (float16_t)0.342660717f, + (float16_t)-0.939983753f, (float16_t)0.341219202f, + (float16_t)-0.940506071f, (float16_t)0.339776884f, + (float16_t)-0.941026175f, (float16_t)0.338333767f, + (float16_t)-0.941544065f, (float16_t)0.336889853f, + (float16_t)-0.942059740f, (float16_t)0.335445147f, + (float16_t)-0.942573198f, (float16_t)0.333999651f, + (float16_t)-0.943084437f, (float16_t)0.332553370f, + (float16_t)-0.943593458f, (float16_t)0.331106306f, + (float16_t)-0.944100258f, (float16_t)0.329658463f, + (float16_t)-0.944604837f, (float16_t)0.328209844f, + (float16_t)-0.945107193f, (float16_t)0.326760452f, + (float16_t)-0.945607325f, (float16_t)0.325310292f, + (float16_t)-0.946105232f, (float16_t)0.323859367f, + (float16_t)-0.946600913f, (float16_t)0.322407679f, + (float16_t)-0.947094366f, (float16_t)0.320955232f, + (float16_t)-0.947585591f, (float16_t)0.319502031f, + (float16_t)-0.948074586f, (float16_t)0.318048077f, + (float16_t)-0.948561350f, (float16_t)0.316593376f, + (float16_t)-0.949045882f, (float16_t)0.315137929f, + (float16_t)-0.949528181f, (float16_t)0.313681740f, + (float16_t)-0.950008245f, (float16_t)0.312224814f, + (float16_t)-0.950486074f, (float16_t)0.310767153f, + (float16_t)-0.950961666f, (float16_t)0.309308760f, + (float16_t)-0.951435021f, (float16_t)0.307849640f, + (float16_t)-0.951906137f, (float16_t)0.306389795f, + (float16_t)-0.952375013f, (float16_t)0.304929230f, + (float16_t)-0.952841648f, (float16_t)0.303467947f, + (float16_t)-0.953306040f, (float16_t)0.302005949f, + (float16_t)-0.953768190f, (float16_t)0.300543241f, + (float16_t)-0.954228095f, (float16_t)0.299079826f, + (float16_t)-0.954685755f, (float16_t)0.297615707f, + (float16_t)-0.955141168f, (float16_t)0.296150888f, + (float16_t)-0.955594334f, (float16_t)0.294685372f, + (float16_t)-0.956045251f, (float16_t)0.293219163f, + (float16_t)-0.956493919f, (float16_t)0.291752263f, + (float16_t)-0.956940336f, (float16_t)0.290284677f, + (float16_t)-0.957384501f, (float16_t)0.288816408f, + (float16_t)-0.957826413f, (float16_t)0.287347460f, + (float16_t)-0.958266071f, (float16_t)0.285877835f, + (float16_t)-0.958703475f, (float16_t)0.284407537f, + (float16_t)-0.959138622f, (float16_t)0.282936570f, + (float16_t)-0.959571513f, (float16_t)0.281464938f, + (float16_t)-0.960002146f, (float16_t)0.279992643f, + (float16_t)-0.960430519f, (float16_t)0.278519689f, + (float16_t)-0.960856633f, (float16_t)0.277046080f, + (float16_t)-0.961280486f, (float16_t)0.275571819f, + (float16_t)-0.961702077f, (float16_t)0.274096910f, + (float16_t)-0.962121404f, (float16_t)0.272621355f, + (float16_t)-0.962538468f, (float16_t)0.271145160f, + (float16_t)-0.962953267f, (float16_t)0.269668326f, + (float16_t)-0.963365800f, (float16_t)0.268190857f, + (float16_t)-0.963776066f, (float16_t)0.266712757f, + (float16_t)-0.964184064f, (float16_t)0.265234030f, + (float16_t)-0.964589793f, (float16_t)0.263754679f, + (float16_t)-0.964993253f, (float16_t)0.262274707f, + (float16_t)-0.965394442f, (float16_t)0.260794118f, + (float16_t)-0.965793359f, (float16_t)0.259312915f, + (float16_t)-0.966190003f, (float16_t)0.257831102f, + (float16_t)-0.966584374f, (float16_t)0.256348682f, + (float16_t)-0.966976471f, (float16_t)0.254865660f, + (float16_t)-0.967366292f, (float16_t)0.253382037f, + (float16_t)-0.967753837f, (float16_t)0.251897818f, + (float16_t)-0.968139105f, (float16_t)0.250413007f, + (float16_t)-0.968522094f, (float16_t)0.248927606f, + (float16_t)-0.968902805f, (float16_t)0.247441619f, + (float16_t)-0.969281235f, (float16_t)0.245955050f, + (float16_t)-0.969657385f, (float16_t)0.244467903f, + (float16_t)-0.970031253f, (float16_t)0.242980180f, + (float16_t)-0.970402839f, (float16_t)0.241491885f, + (float16_t)-0.970772141f, (float16_t)0.240003022f, + (float16_t)-0.971139158f, (float16_t)0.238513595f, + (float16_t)-0.971503891f, (float16_t)0.237023606f, + (float16_t)-0.971866337f, (float16_t)0.235533059f, + (float16_t)-0.972226497f, (float16_t)0.234041959f, + (float16_t)-0.972584369f, (float16_t)0.232550307f, + (float16_t)-0.972939952f, (float16_t)0.231058108f, + (float16_t)-0.973293246f, (float16_t)0.229565366f, + (float16_t)-0.973644250f, (float16_t)0.228072083f, + (float16_t)-0.973992962f, (float16_t)0.226578264f, + (float16_t)-0.974339383f, (float16_t)0.225083911f, + (float16_t)-0.974683511f, (float16_t)0.223589029f, + (float16_t)-0.975025345f, (float16_t)0.222093621f, + (float16_t)-0.975364885f, (float16_t)0.220597690f, + (float16_t)-0.975702130f, (float16_t)0.219101240f, + (float16_t)-0.976037079f, (float16_t)0.217604275f, + (float16_t)-0.976369731f, (float16_t)0.216106797f, + (float16_t)-0.976700086f, (float16_t)0.214608811f, + (float16_t)-0.977028143f, (float16_t)0.213110320f, + (float16_t)-0.977353900f, (float16_t)0.211611327f, + (float16_t)-0.977677358f, (float16_t)0.210111837f, + (float16_t)-0.977998515f, (float16_t)0.208611852f, + (float16_t)-0.978317371f, (float16_t)0.207111376f, + (float16_t)-0.978633924f, (float16_t)0.205610413f, + (float16_t)-0.978948175f, (float16_t)0.204108966f, + (float16_t)-0.979260123f, (float16_t)0.202607039f, + (float16_t)-0.979569766f, (float16_t)0.201104635f, + (float16_t)-0.979877104f, (float16_t)0.199601758f, + (float16_t)-0.980182136f, (float16_t)0.198098411f, + (float16_t)-0.980484862f, (float16_t)0.196594598f, + (float16_t)-0.980785280f, (float16_t)0.195090322f, + (float16_t)-0.981083391f, (float16_t)0.193585587f, + (float16_t)-0.981379193f, (float16_t)0.192080397f, + (float16_t)-0.981672686f, (float16_t)0.190574755f, + (float16_t)-0.981963869f, (float16_t)0.189068664f, + (float16_t)-0.982252741f, (float16_t)0.187562129f, + (float16_t)-0.982539302f, (float16_t)0.186055152f, + (float16_t)-0.982823551f, (float16_t)0.184547737f, + (float16_t)-0.983105487f, (float16_t)0.183039888f, + (float16_t)-0.983385110f, (float16_t)0.181531608f, + (float16_t)-0.983662419f, (float16_t)0.180022901f, + (float16_t)-0.983937413f, (float16_t)0.178513771f, + (float16_t)-0.984210092f, (float16_t)0.177004220f, + (float16_t)-0.984480455f, (float16_t)0.175494253f, + (float16_t)-0.984748502f, (float16_t)0.173983873f, + (float16_t)-0.985014231f, (float16_t)0.172473084f, + (float16_t)-0.985277642f, (float16_t)0.170961889f, + (float16_t)-0.985538735f, (float16_t)0.169450291f, + (float16_t)-0.985797509f, (float16_t)0.167938295f, + (float16_t)-0.986053963f, (float16_t)0.166425904f, + (float16_t)-0.986308097f, (float16_t)0.164913120f, + (float16_t)-0.986559910f, (float16_t)0.163399949f, + (float16_t)-0.986809402f, (float16_t)0.161886394f, + (float16_t)-0.987056571f, (float16_t)0.160372457f, + (float16_t)-0.987301418f, (float16_t)0.158858143f, + (float16_t)-0.987543942f, (float16_t)0.157343456f, + (float16_t)-0.987784142f, (float16_t)0.155828398f, + (float16_t)-0.988022017f, (float16_t)0.154312973f, + (float16_t)-0.988257568f, (float16_t)0.152797185f, + (float16_t)-0.988490793f, (float16_t)0.151281038f, + (float16_t)-0.988721692f, (float16_t)0.149764535f, + (float16_t)-0.988950265f, (float16_t)0.148247679f, + (float16_t)-0.989176510f, (float16_t)0.146730474f, + (float16_t)-0.989400428f, (float16_t)0.145212925f, + (float16_t)-0.989622017f, (float16_t)0.143695033f, + (float16_t)-0.989841278f, (float16_t)0.142176804f, + (float16_t)-0.990058210f, (float16_t)0.140658239f, + (float16_t)-0.990272812f, (float16_t)0.139139344f, + (float16_t)-0.990485084f, (float16_t)0.137620122f, + (float16_t)-0.990695025f, (float16_t)0.136100575f, + (float16_t)-0.990902635f, (float16_t)0.134580709f, + (float16_t)-0.991107914f, (float16_t)0.133060525f, + (float16_t)-0.991310860f, (float16_t)0.131540029f, + (float16_t)-0.991511473f, (float16_t)0.130019223f, + (float16_t)-0.991709754f, (float16_t)0.128498111f, + (float16_t)-0.991905700f, (float16_t)0.126976696f, + (float16_t)-0.992099313f, (float16_t)0.125454983f, + (float16_t)-0.992290591f, (float16_t)0.123932975f, + (float16_t)-0.992479535f, (float16_t)0.122410675f, + (float16_t)-0.992666142f, (float16_t)0.120888087f, + (float16_t)-0.992850414f, (float16_t)0.119365215f, + (float16_t)-0.993032350f, (float16_t)0.117842062f, + (float16_t)-0.993211949f, (float16_t)0.116318631f, + (float16_t)-0.993389211f, (float16_t)0.114794927f, + (float16_t)-0.993564136f, (float16_t)0.113270952f, + (float16_t)-0.993736722f, (float16_t)0.111746711f, + (float16_t)-0.993906970f, (float16_t)0.110222207f, + (float16_t)-0.994074879f, (float16_t)0.108697444f, + (float16_t)-0.994240449f, (float16_t)0.107172425f, + (float16_t)-0.994403680f, (float16_t)0.105647154f, + (float16_t)-0.994564571f, (float16_t)0.104121634f, + (float16_t)-0.994723121f, (float16_t)0.102595869f, + (float16_t)-0.994879331f, (float16_t)0.101069863f, + (float16_t)-0.995033199f, (float16_t)0.099543619f, + (float16_t)-0.995184727f, (float16_t)0.098017140f, + (float16_t)-0.995333912f, (float16_t)0.096490431f, + (float16_t)-0.995480755f, (float16_t)0.094963495f, + (float16_t)-0.995625256f, (float16_t)0.093436336f, + (float16_t)-0.995767414f, (float16_t)0.091908956f, + (float16_t)-0.995907229f, (float16_t)0.090381361f, + (float16_t)-0.996044701f, (float16_t)0.088853553f, + (float16_t)-0.996179829f, (float16_t)0.087325535f, + (float16_t)-0.996312612f, (float16_t)0.085797312f, + (float16_t)-0.996443051f, (float16_t)0.084268888f, + (float16_t)-0.996571146f, (float16_t)0.082740265f, + (float16_t)-0.996696895f, (float16_t)0.081211447f, + (float16_t)-0.996820299f, (float16_t)0.079682438f, + (float16_t)-0.996941358f, (float16_t)0.078153242f, + (float16_t)-0.997060070f, (float16_t)0.076623861f, + (float16_t)-0.997176437f, (float16_t)0.075094301f, + (float16_t)-0.997290457f, (float16_t)0.073564564f, + (float16_t)-0.997402130f, (float16_t)0.072034653f, + (float16_t)-0.997511456f, (float16_t)0.070504573f, + (float16_t)-0.997618435f, (float16_t)0.068974328f, + (float16_t)-0.997723067f, (float16_t)0.067443920f, + (float16_t)-0.997825350f, (float16_t)0.065913353f, + (float16_t)-0.997925286f, (float16_t)0.064382631f, + (float16_t)-0.998022874f, (float16_t)0.062851758f, + (float16_t)-0.998118113f, (float16_t)0.061320736f, + (float16_t)-0.998211003f, (float16_t)0.059789571f, + (float16_t)-0.998301545f, (float16_t)0.058258265f, + (float16_t)-0.998389737f, (float16_t)0.056726821f, + (float16_t)-0.998475581f, (float16_t)0.055195244f, + (float16_t)-0.998559074f, (float16_t)0.053663538f, + (float16_t)-0.998640218f, (float16_t)0.052131705f, + (float16_t)-0.998719012f, (float16_t)0.050599749f, + (float16_t)-0.998795456f, (float16_t)0.049067674f, + (float16_t)-0.998869550f, (float16_t)0.047535484f, + (float16_t)-0.998941293f, (float16_t)0.046003182f, + (float16_t)-0.999010686f, (float16_t)0.044470772f, + (float16_t)-0.999077728f, (float16_t)0.042938257f, + (float16_t)-0.999142419f, (float16_t)0.041405641f, + (float16_t)-0.999204759f, (float16_t)0.039872928f, + (float16_t)-0.999264747f, (float16_t)0.038340120f, + (float16_t)-0.999322385f, (float16_t)0.036807223f, + (float16_t)-0.999377670f, (float16_t)0.035274239f, + (float16_t)-0.999430605f, (float16_t)0.033741172f, + (float16_t)-0.999481187f, (float16_t)0.032208025f, + (float16_t)-0.999529418f, (float16_t)0.030674803f, + (float16_t)-0.999575296f, (float16_t)0.029141509f, + (float16_t)-0.999618822f, (float16_t)0.027608146f, + (float16_t)-0.999659997f, (float16_t)0.026074718f, + (float16_t)-0.999698819f, (float16_t)0.024541229f, + (float16_t)-0.999735288f, (float16_t)0.023007681f, + (float16_t)-0.999769405f, (float16_t)0.021474080f, + (float16_t)-0.999801170f, (float16_t)0.019940429f, + (float16_t)-0.999830582f, (float16_t)0.018406730f, + (float16_t)-0.999857641f, (float16_t)0.016872988f, + (float16_t)-0.999882347f, (float16_t)0.015339206f, + (float16_t)-0.999904701f, (float16_t)0.013805389f, + (float16_t)-0.999924702f, (float16_t)0.012271538f, + (float16_t)-0.999942350f, (float16_t)0.010737659f, + (float16_t)-0.999957645f, (float16_t)0.009203755f, + (float16_t)-0.999970586f, (float16_t)0.007669829f, + (float16_t)-0.999981175f, (float16_t)0.006135885f, + (float16_t)-0.999989411f, (float16_t)0.004601926f, + (float16_t)-0.999995294f, (float16_t)0.003067957f, + (float16_t)-0.999998823f, (float16_t)0.001533980f, + (float16_t)-1.000000000f, (float16_t)0.000000000f, + (float16_t)-0.999998823f, (float16_t)-0.001533980f, + (float16_t)-0.999995294f, (float16_t)-0.003067957f, + (float16_t)-0.999989411f, (float16_t)-0.004601926f, + (float16_t)-0.999981175f, (float16_t)-0.006135885f, + (float16_t)-0.999970586f, (float16_t)-0.007669829f, + (float16_t)-0.999957645f, (float16_t)-0.009203755f, + (float16_t)-0.999942350f, (float16_t)-0.010737659f, + (float16_t)-0.999924702f, (float16_t)-0.012271538f, + (float16_t)-0.999904701f, (float16_t)-0.013805389f, + (float16_t)-0.999882347f, (float16_t)-0.015339206f, + (float16_t)-0.999857641f, (float16_t)-0.016872988f, + (float16_t)-0.999830582f, (float16_t)-0.018406730f, + (float16_t)-0.999801170f, (float16_t)-0.019940429f, + (float16_t)-0.999769405f, (float16_t)-0.021474080f, + (float16_t)-0.999735288f, (float16_t)-0.023007681f, + (float16_t)-0.999698819f, (float16_t)-0.024541229f, + (float16_t)-0.999659997f, (float16_t)-0.026074718f, + (float16_t)-0.999618822f, (float16_t)-0.027608146f, + (float16_t)-0.999575296f, (float16_t)-0.029141509f, + (float16_t)-0.999529418f, (float16_t)-0.030674803f, + (float16_t)-0.999481187f, (float16_t)-0.032208025f, + (float16_t)-0.999430605f, (float16_t)-0.033741172f, + (float16_t)-0.999377670f, (float16_t)-0.035274239f, + (float16_t)-0.999322385f, (float16_t)-0.036807223f, + (float16_t)-0.999264747f, (float16_t)-0.038340120f, + (float16_t)-0.999204759f, (float16_t)-0.039872928f, + (float16_t)-0.999142419f, (float16_t)-0.041405641f, + (float16_t)-0.999077728f, (float16_t)-0.042938257f, + (float16_t)-0.999010686f, (float16_t)-0.044470772f, + (float16_t)-0.998941293f, (float16_t)-0.046003182f, + (float16_t)-0.998869550f, (float16_t)-0.047535484f, + (float16_t)-0.998795456f, (float16_t)-0.049067674f, + (float16_t)-0.998719012f, (float16_t)-0.050599749f, + (float16_t)-0.998640218f, (float16_t)-0.052131705f, + (float16_t)-0.998559074f, (float16_t)-0.053663538f, + (float16_t)-0.998475581f, (float16_t)-0.055195244f, + (float16_t)-0.998389737f, (float16_t)-0.056726821f, + (float16_t)-0.998301545f, (float16_t)-0.058258265f, + (float16_t)-0.998211003f, (float16_t)-0.059789571f, + (float16_t)-0.998118113f, (float16_t)-0.061320736f, + (float16_t)-0.998022874f, (float16_t)-0.062851758f, + (float16_t)-0.997925286f, (float16_t)-0.064382631f, + (float16_t)-0.997825350f, (float16_t)-0.065913353f, + (float16_t)-0.997723067f, (float16_t)-0.067443920f, + (float16_t)-0.997618435f, (float16_t)-0.068974328f, + (float16_t)-0.997511456f, (float16_t)-0.070504573f, + (float16_t)-0.997402130f, (float16_t)-0.072034653f, + (float16_t)-0.997290457f, (float16_t)-0.073564564f, + (float16_t)-0.997176437f, (float16_t)-0.075094301f, + (float16_t)-0.997060070f, (float16_t)-0.076623861f, + (float16_t)-0.996941358f, (float16_t)-0.078153242f, + (float16_t)-0.996820299f, (float16_t)-0.079682438f, + (float16_t)-0.996696895f, (float16_t)-0.081211447f, + (float16_t)-0.996571146f, (float16_t)-0.082740265f, + (float16_t)-0.996443051f, (float16_t)-0.084268888f, + (float16_t)-0.996312612f, (float16_t)-0.085797312f, + (float16_t)-0.996179829f, (float16_t)-0.087325535f, + (float16_t)-0.996044701f, (float16_t)-0.088853553f, + (float16_t)-0.995907229f, (float16_t)-0.090381361f, + (float16_t)-0.995767414f, (float16_t)-0.091908956f, + (float16_t)-0.995625256f, (float16_t)-0.093436336f, + (float16_t)-0.995480755f, (float16_t)-0.094963495f, + (float16_t)-0.995333912f, (float16_t)-0.096490431f, + (float16_t)-0.995184727f, (float16_t)-0.098017140f, + (float16_t)-0.995033199f, (float16_t)-0.099543619f, + (float16_t)-0.994879331f, (float16_t)-0.101069863f, + (float16_t)-0.994723121f, (float16_t)-0.102595869f, + (float16_t)-0.994564571f, (float16_t)-0.104121634f, + (float16_t)-0.994403680f, (float16_t)-0.105647154f, + (float16_t)-0.994240449f, (float16_t)-0.107172425f, + (float16_t)-0.994074879f, (float16_t)-0.108697444f, + (float16_t)-0.993906970f, (float16_t)-0.110222207f, + (float16_t)-0.993736722f, (float16_t)-0.111746711f, + (float16_t)-0.993564136f, (float16_t)-0.113270952f, + (float16_t)-0.993389211f, (float16_t)-0.114794927f, + (float16_t)-0.993211949f, (float16_t)-0.116318631f, + (float16_t)-0.993032350f, (float16_t)-0.117842062f, + (float16_t)-0.992850414f, (float16_t)-0.119365215f, + (float16_t)-0.992666142f, (float16_t)-0.120888087f, + (float16_t)-0.992479535f, (float16_t)-0.122410675f, + (float16_t)-0.992290591f, (float16_t)-0.123932975f, + (float16_t)-0.992099313f, (float16_t)-0.125454983f, + (float16_t)-0.991905700f, (float16_t)-0.126976696f, + (float16_t)-0.991709754f, (float16_t)-0.128498111f, + (float16_t)-0.991511473f, (float16_t)-0.130019223f, + (float16_t)-0.991310860f, (float16_t)-0.131540029f, + (float16_t)-0.991107914f, (float16_t)-0.133060525f, + (float16_t)-0.990902635f, (float16_t)-0.134580709f, + (float16_t)-0.990695025f, (float16_t)-0.136100575f, + (float16_t)-0.990485084f, (float16_t)-0.137620122f, + (float16_t)-0.990272812f, (float16_t)-0.139139344f, + (float16_t)-0.990058210f, (float16_t)-0.140658239f, + (float16_t)-0.989841278f, (float16_t)-0.142176804f, + (float16_t)-0.989622017f, (float16_t)-0.143695033f, + (float16_t)-0.989400428f, (float16_t)-0.145212925f, + (float16_t)-0.989176510f, (float16_t)-0.146730474f, + (float16_t)-0.988950265f, (float16_t)-0.148247679f, + (float16_t)-0.988721692f, (float16_t)-0.149764535f, + (float16_t)-0.988490793f, (float16_t)-0.151281038f, + (float16_t)-0.988257568f, (float16_t)-0.152797185f, + (float16_t)-0.988022017f, (float16_t)-0.154312973f, + (float16_t)-0.987784142f, (float16_t)-0.155828398f, + (float16_t)-0.987543942f, (float16_t)-0.157343456f, + (float16_t)-0.987301418f, (float16_t)-0.158858143f, + (float16_t)-0.987056571f, (float16_t)-0.160372457f, + (float16_t)-0.986809402f, (float16_t)-0.161886394f, + (float16_t)-0.986559910f, (float16_t)-0.163399949f, + (float16_t)-0.986308097f, (float16_t)-0.164913120f, + (float16_t)-0.986053963f, (float16_t)-0.166425904f, + (float16_t)-0.985797509f, (float16_t)-0.167938295f, + (float16_t)-0.985538735f, (float16_t)-0.169450291f, + (float16_t)-0.985277642f, (float16_t)-0.170961889f, + (float16_t)-0.985014231f, (float16_t)-0.172473084f, + (float16_t)-0.984748502f, (float16_t)-0.173983873f, + (float16_t)-0.984480455f, (float16_t)-0.175494253f, + (float16_t)-0.984210092f, (float16_t)-0.177004220f, + (float16_t)-0.983937413f, (float16_t)-0.178513771f, + (float16_t)-0.983662419f, (float16_t)-0.180022901f, + (float16_t)-0.983385110f, (float16_t)-0.181531608f, + (float16_t)-0.983105487f, (float16_t)-0.183039888f, + (float16_t)-0.982823551f, (float16_t)-0.184547737f, + (float16_t)-0.982539302f, (float16_t)-0.186055152f, + (float16_t)-0.982252741f, (float16_t)-0.187562129f, + (float16_t)-0.981963869f, (float16_t)-0.189068664f, + (float16_t)-0.981672686f, (float16_t)-0.190574755f, + (float16_t)-0.981379193f, (float16_t)-0.192080397f, + (float16_t)-0.981083391f, (float16_t)-0.193585587f, + (float16_t)-0.980785280f, (float16_t)-0.195090322f, + (float16_t)-0.980484862f, (float16_t)-0.196594598f, + (float16_t)-0.980182136f, (float16_t)-0.198098411f, + (float16_t)-0.979877104f, (float16_t)-0.199601758f, + (float16_t)-0.979569766f, (float16_t)-0.201104635f, + (float16_t)-0.979260123f, (float16_t)-0.202607039f, + (float16_t)-0.978948175f, (float16_t)-0.204108966f, + (float16_t)-0.978633924f, (float16_t)-0.205610413f, + (float16_t)-0.978317371f, (float16_t)-0.207111376f, + (float16_t)-0.977998515f, (float16_t)-0.208611852f, + (float16_t)-0.977677358f, (float16_t)-0.210111837f, + (float16_t)-0.977353900f, (float16_t)-0.211611327f, + (float16_t)-0.977028143f, (float16_t)-0.213110320f, + (float16_t)-0.976700086f, (float16_t)-0.214608811f, + (float16_t)-0.976369731f, (float16_t)-0.216106797f, + (float16_t)-0.976037079f, (float16_t)-0.217604275f, + (float16_t)-0.975702130f, (float16_t)-0.219101240f, + (float16_t)-0.975364885f, (float16_t)-0.220597690f, + (float16_t)-0.975025345f, (float16_t)-0.222093621f, + (float16_t)-0.974683511f, (float16_t)-0.223589029f, + (float16_t)-0.974339383f, (float16_t)-0.225083911f, + (float16_t)-0.973992962f, (float16_t)-0.226578264f, + (float16_t)-0.973644250f, (float16_t)-0.228072083f, + (float16_t)-0.973293246f, (float16_t)-0.229565366f, + (float16_t)-0.972939952f, (float16_t)-0.231058108f, + (float16_t)-0.972584369f, (float16_t)-0.232550307f, + (float16_t)-0.972226497f, (float16_t)-0.234041959f, + (float16_t)-0.971866337f, (float16_t)-0.235533059f, + (float16_t)-0.971503891f, (float16_t)-0.237023606f, + (float16_t)-0.971139158f, (float16_t)-0.238513595f, + (float16_t)-0.970772141f, (float16_t)-0.240003022f, + (float16_t)-0.970402839f, (float16_t)-0.241491885f, + (float16_t)-0.970031253f, (float16_t)-0.242980180f, + (float16_t)-0.969657385f, (float16_t)-0.244467903f, + (float16_t)-0.969281235f, (float16_t)-0.245955050f, + (float16_t)-0.968902805f, (float16_t)-0.247441619f, + (float16_t)-0.968522094f, (float16_t)-0.248927606f, + (float16_t)-0.968139105f, (float16_t)-0.250413007f, + (float16_t)-0.967753837f, (float16_t)-0.251897818f, + (float16_t)-0.967366292f, (float16_t)-0.253382037f, + (float16_t)-0.966976471f, (float16_t)-0.254865660f, + (float16_t)-0.966584374f, (float16_t)-0.256348682f, + (float16_t)-0.966190003f, (float16_t)-0.257831102f, + (float16_t)-0.965793359f, (float16_t)-0.259312915f, + (float16_t)-0.965394442f, (float16_t)-0.260794118f, + (float16_t)-0.964993253f, (float16_t)-0.262274707f, + (float16_t)-0.964589793f, (float16_t)-0.263754679f, + (float16_t)-0.964184064f, (float16_t)-0.265234030f, + (float16_t)-0.963776066f, (float16_t)-0.266712757f, + (float16_t)-0.963365800f, (float16_t)-0.268190857f, + (float16_t)-0.962953267f, (float16_t)-0.269668326f, + (float16_t)-0.962538468f, (float16_t)-0.271145160f, + (float16_t)-0.962121404f, (float16_t)-0.272621355f, + (float16_t)-0.961702077f, (float16_t)-0.274096910f, + (float16_t)-0.961280486f, (float16_t)-0.275571819f, + (float16_t)-0.960856633f, (float16_t)-0.277046080f, + (float16_t)-0.960430519f, (float16_t)-0.278519689f, + (float16_t)-0.960002146f, (float16_t)-0.279992643f, + (float16_t)-0.959571513f, (float16_t)-0.281464938f, + (float16_t)-0.959138622f, (float16_t)-0.282936570f, + (float16_t)-0.958703475f, (float16_t)-0.284407537f, + (float16_t)-0.958266071f, (float16_t)-0.285877835f, + (float16_t)-0.957826413f, (float16_t)-0.287347460f, + (float16_t)-0.957384501f, (float16_t)-0.288816408f, + (float16_t)-0.956940336f, (float16_t)-0.290284677f, + (float16_t)-0.956493919f, (float16_t)-0.291752263f, + (float16_t)-0.956045251f, (float16_t)-0.293219163f, + (float16_t)-0.955594334f, (float16_t)-0.294685372f, + (float16_t)-0.955141168f, (float16_t)-0.296150888f, + (float16_t)-0.954685755f, (float16_t)-0.297615707f, + (float16_t)-0.954228095f, (float16_t)-0.299079826f, + (float16_t)-0.953768190f, (float16_t)-0.300543241f, + (float16_t)-0.953306040f, (float16_t)-0.302005949f, + (float16_t)-0.952841648f, (float16_t)-0.303467947f, + (float16_t)-0.952375013f, (float16_t)-0.304929230f, + (float16_t)-0.951906137f, (float16_t)-0.306389795f, + (float16_t)-0.951435021f, (float16_t)-0.307849640f, + (float16_t)-0.950961666f, (float16_t)-0.309308760f, + (float16_t)-0.950486074f, (float16_t)-0.310767153f, + (float16_t)-0.950008245f, (float16_t)-0.312224814f, + (float16_t)-0.949528181f, (float16_t)-0.313681740f, + (float16_t)-0.949045882f, (float16_t)-0.315137929f, + (float16_t)-0.948561350f, (float16_t)-0.316593376f, + (float16_t)-0.948074586f, (float16_t)-0.318048077f, + (float16_t)-0.947585591f, (float16_t)-0.319502031f, + (float16_t)-0.947094366f, (float16_t)-0.320955232f, + (float16_t)-0.946600913f, (float16_t)-0.322407679f, + (float16_t)-0.946105232f, (float16_t)-0.323859367f, + (float16_t)-0.945607325f, (float16_t)-0.325310292f, + (float16_t)-0.945107193f, (float16_t)-0.326760452f, + (float16_t)-0.944604837f, (float16_t)-0.328209844f, + (float16_t)-0.944100258f, (float16_t)-0.329658463f, + (float16_t)-0.943593458f, (float16_t)-0.331106306f, + (float16_t)-0.943084437f, (float16_t)-0.332553370f, + (float16_t)-0.942573198f, (float16_t)-0.333999651f, + (float16_t)-0.942059740f, (float16_t)-0.335445147f, + (float16_t)-0.941544065f, (float16_t)-0.336889853f, + (float16_t)-0.941026175f, (float16_t)-0.338333767f, + (float16_t)-0.940506071f, (float16_t)-0.339776884f, + (float16_t)-0.939983753f, (float16_t)-0.341219202f, + (float16_t)-0.939459224f, (float16_t)-0.342660717f, + (float16_t)-0.938932484f, (float16_t)-0.344101426f, + (float16_t)-0.938403534f, (float16_t)-0.345541325f, + (float16_t)-0.937872376f, (float16_t)-0.346980411f, + (float16_t)-0.937339012f, (float16_t)-0.348418680f, + (float16_t)-0.936803442f, (float16_t)-0.349856130f, + (float16_t)-0.936265667f, (float16_t)-0.351292756f, + (float16_t)-0.935725689f, (float16_t)-0.352728556f, + (float16_t)-0.935183510f, (float16_t)-0.354163525f, + (float16_t)-0.934639130f, (float16_t)-0.355597662f, + (float16_t)-0.934092550f, (float16_t)-0.357030961f, + (float16_t)-0.933543773f, (float16_t)-0.358463421f, + (float16_t)-0.932992799f, (float16_t)-0.359895037f, + (float16_t)-0.932439629f, (float16_t)-0.361325806f, + (float16_t)-0.931884266f, (float16_t)-0.362755724f, + (float16_t)-0.931326709f, (float16_t)-0.364184790f, + (float16_t)-0.930766961f, (float16_t)-0.365612998f, + (float16_t)-0.930205023f, (float16_t)-0.367040346f, + (float16_t)-0.929640896f, (float16_t)-0.368466830f, + (float16_t)-0.929074581f, (float16_t)-0.369892447f, + (float16_t)-0.928506080f, (float16_t)-0.371317194f, + (float16_t)-0.927935395f, (float16_t)-0.372741067f, + (float16_t)-0.927362526f, (float16_t)-0.374164063f, + (float16_t)-0.926787474f, (float16_t)-0.375586178f, + (float16_t)-0.926210242f, (float16_t)-0.377007410f, + (float16_t)-0.925630831f, (float16_t)-0.378427755f, + (float16_t)-0.925049241f, (float16_t)-0.379847209f, + (float16_t)-0.924465474f, (float16_t)-0.381265769f, + (float16_t)-0.923879533f, (float16_t)-0.382683432f, + (float16_t)-0.923291417f, (float16_t)-0.384100195f, + (float16_t)-0.922701128f, (float16_t)-0.385516054f, + (float16_t)-0.922108669f, (float16_t)-0.386931006f, + (float16_t)-0.921514039f, (float16_t)-0.388345047f, + (float16_t)-0.920917242f, (float16_t)-0.389758174f, + (float16_t)-0.920318277f, (float16_t)-0.391170384f, + (float16_t)-0.919717146f, (float16_t)-0.392581674f, + (float16_t)-0.919113852f, (float16_t)-0.393992040f, + (float16_t)-0.918508394f, (float16_t)-0.395401479f, + (float16_t)-0.917900776f, (float16_t)-0.396809987f, + (float16_t)-0.917290997f, (float16_t)-0.398217562f, + (float16_t)-0.916679060f, (float16_t)-0.399624200f, + (float16_t)-0.916064966f, (float16_t)-0.401029897f, + (float16_t)-0.915448716f, (float16_t)-0.402434651f, + (float16_t)-0.914830312f, (float16_t)-0.403838458f, + (float16_t)-0.914209756f, (float16_t)-0.405241314f, + (float16_t)-0.913587048f, (float16_t)-0.406643217f, + (float16_t)-0.912962190f, (float16_t)-0.408044163f, + (float16_t)-0.912335185f, (float16_t)-0.409444149f, + (float16_t)-0.911706032f, (float16_t)-0.410843171f, + (float16_t)-0.911074734f, (float16_t)-0.412241227f, + (float16_t)-0.910441292f, (float16_t)-0.413638312f, + (float16_t)-0.909805708f, (float16_t)-0.415034424f, + (float16_t)-0.909167983f, (float16_t)-0.416429560f, + (float16_t)-0.908528119f, (float16_t)-0.417823716f, + (float16_t)-0.907886116f, (float16_t)-0.419216888f, + (float16_t)-0.907241978f, (float16_t)-0.420609074f, + (float16_t)-0.906595705f, (float16_t)-0.422000271f, + (float16_t)-0.905947298f, (float16_t)-0.423390474f, + (float16_t)-0.905296759f, (float16_t)-0.424779681f, + (float16_t)-0.904644091f, (float16_t)-0.426167889f, + (float16_t)-0.903989293f, (float16_t)-0.427555093f, + (float16_t)-0.903332368f, (float16_t)-0.428941292f, + (float16_t)-0.902673318f, (float16_t)-0.430326481f, + (float16_t)-0.902012144f, (float16_t)-0.431710658f, + (float16_t)-0.901348847f, (float16_t)-0.433093819f, + (float16_t)-0.900683429f, (float16_t)-0.434475961f, + (float16_t)-0.900015892f, (float16_t)-0.435857080f, + (float16_t)-0.899346237f, (float16_t)-0.437237174f, + (float16_t)-0.898674466f, (float16_t)-0.438616239f, + (float16_t)-0.898000580f, (float16_t)-0.439994271f, + (float16_t)-0.897324581f, (float16_t)-0.441371269f, + (float16_t)-0.896646470f, (float16_t)-0.442747228f, + (float16_t)-0.895966250f, (float16_t)-0.444122145f, + (float16_t)-0.895283921f, (float16_t)-0.445496017f, + (float16_t)-0.894599486f, (float16_t)-0.446868840f, + (float16_t)-0.893912945f, (float16_t)-0.448240612f, + (float16_t)-0.893224301f, (float16_t)-0.449611330f, + (float16_t)-0.892533555f, (float16_t)-0.450980989f, + (float16_t)-0.891840709f, (float16_t)-0.452349587f, + (float16_t)-0.891145765f, (float16_t)-0.453717121f, + (float16_t)-0.890448723f, (float16_t)-0.455083587f, + (float16_t)-0.889749586f, (float16_t)-0.456448982f, + (float16_t)-0.889048356f, (float16_t)-0.457813304f, + (float16_t)-0.888345033f, (float16_t)-0.459176548f, + (float16_t)-0.887639620f, (float16_t)-0.460538711f, + (float16_t)-0.886932119f, (float16_t)-0.461899791f, + (float16_t)-0.886222530f, (float16_t)-0.463259784f, + (float16_t)-0.885510856f, (float16_t)-0.464618686f, + (float16_t)-0.884797098f, (float16_t)-0.465976496f, + (float16_t)-0.884081259f, (float16_t)-0.467333209f, + (float16_t)-0.883363339f, (float16_t)-0.468688822f, + (float16_t)-0.882643340f, (float16_t)-0.470043332f, + (float16_t)-0.881921264f, (float16_t)-0.471396737f, + (float16_t)-0.881197113f, (float16_t)-0.472749032f, + (float16_t)-0.880470889f, (float16_t)-0.474100215f, + (float16_t)-0.879742593f, (float16_t)-0.475450282f, + (float16_t)-0.879012226f, (float16_t)-0.476799230f, + (float16_t)-0.878279792f, (float16_t)-0.478147056f, + (float16_t)-0.877545290f, (float16_t)-0.479493758f, + (float16_t)-0.876808724f, (float16_t)-0.480839331f, + (float16_t)-0.876070094f, (float16_t)-0.482183772f, + (float16_t)-0.875329403f, (float16_t)-0.483527079f, + (float16_t)-0.874586652f, (float16_t)-0.484869248f, + (float16_t)-0.873841843f, (float16_t)-0.486210276f, + (float16_t)-0.873094978f, (float16_t)-0.487550160f, + (float16_t)-0.872346059f, (float16_t)-0.488888897f, + (float16_t)-0.871595087f, (float16_t)-0.490226483f, + (float16_t)-0.870842063f, (float16_t)-0.491562916f, + (float16_t)-0.870086991f, (float16_t)-0.492898192f, + (float16_t)-0.869329871f, (float16_t)-0.494232309f, + (float16_t)-0.868570706f, (float16_t)-0.495565262f, + (float16_t)-0.867809497f, (float16_t)-0.496897049f, + (float16_t)-0.867046246f, (float16_t)-0.498227667f, + (float16_t)-0.866280954f, (float16_t)-0.499557113f, + (float16_t)-0.865513624f, (float16_t)-0.500885383f, + (float16_t)-0.864744258f, (float16_t)-0.502212474f, + (float16_t)-0.863972856f, (float16_t)-0.503538384f, + (float16_t)-0.863199422f, (float16_t)-0.504863109f, + (float16_t)-0.862423956f, (float16_t)-0.506186645f, + (float16_t)-0.861646461f, (float16_t)-0.507508991f, + (float16_t)-0.860866939f, (float16_t)-0.508830143f, + (float16_t)-0.860085390f, (float16_t)-0.510150097f, + (float16_t)-0.859301818f, (float16_t)-0.511468850f, + (float16_t)-0.858516224f, (float16_t)-0.512786401f, + (float16_t)-0.857728610f, (float16_t)-0.514102744f, + (float16_t)-0.856938977f, (float16_t)-0.515417878f, + (float16_t)-0.856147328f, (float16_t)-0.516731799f, + (float16_t)-0.855353665f, (float16_t)-0.518044504f, + (float16_t)-0.854557988f, (float16_t)-0.519355990f, + (float16_t)-0.853760301f, (float16_t)-0.520666254f, + (float16_t)-0.852960605f, (float16_t)-0.521975293f, + (float16_t)-0.852158902f, (float16_t)-0.523283103f, + (float16_t)-0.851355193f, (float16_t)-0.524589683f, + (float16_t)-0.850549481f, (float16_t)-0.525895027f, + (float16_t)-0.849741768f, (float16_t)-0.527199135f, + (float16_t)-0.848932055f, (float16_t)-0.528502002f, + (float16_t)-0.848120345f, (float16_t)-0.529803625f, + (float16_t)-0.847306639f, (float16_t)-0.531104001f, + (float16_t)-0.846490939f, (float16_t)-0.532403128f, + (float16_t)-0.845673247f, (float16_t)-0.533701002f, + (float16_t)-0.844853565f, (float16_t)-0.534997620f, + (float16_t)-0.844031895f, (float16_t)-0.536292979f, + (float16_t)-0.843208240f, (float16_t)-0.537587076f, + (float16_t)-0.842382600f, (float16_t)-0.538879909f, + (float16_t)-0.841554977f, (float16_t)-0.540171473f, + (float16_t)-0.840725375f, (float16_t)-0.541461766f, + (float16_t)-0.839893794f, (float16_t)-0.542750785f, + (float16_t)-0.839060237f, (float16_t)-0.544038527f, + (float16_t)-0.838224706f, (float16_t)-0.545324988f, + (float16_t)-0.837387202f, (float16_t)-0.546610167f, + (float16_t)-0.836547727f, (float16_t)-0.547894059f, + (float16_t)-0.835706284f, (float16_t)-0.549176662f, + (float16_t)-0.834862875f, (float16_t)-0.550457973f, + (float16_t)-0.834017501f, (float16_t)-0.551737988f, + (float16_t)-0.833170165f, (float16_t)-0.553016706f, + (float16_t)-0.832320868f, (float16_t)-0.554294121f, + (float16_t)-0.831469612f, (float16_t)-0.555570233f, + (float16_t)-0.830616400f, (float16_t)-0.556845037f, + (float16_t)-0.829761234f, (float16_t)-0.558118531f, + (float16_t)-0.828904115f, (float16_t)-0.559390712f, + (float16_t)-0.828045045f, (float16_t)-0.560661576f, + (float16_t)-0.827184027f, (float16_t)-0.561931121f, + (float16_t)-0.826321063f, (float16_t)-0.563199344f, + (float16_t)-0.825456154f, (float16_t)-0.564466242f, + (float16_t)-0.824589303f, (float16_t)-0.565731811f, + (float16_t)-0.823720511f, (float16_t)-0.566996049f, + (float16_t)-0.822849781f, (float16_t)-0.568258953f, + (float16_t)-0.821977115f, (float16_t)-0.569520519f, + (float16_t)-0.821102515f, (float16_t)-0.570780746f, + (float16_t)-0.820225983f, (float16_t)-0.572039629f, + (float16_t)-0.819347520f, (float16_t)-0.573297167f, + (float16_t)-0.818467130f, (float16_t)-0.574553355f, + (float16_t)-0.817584813f, (float16_t)-0.575808191f, + (float16_t)-0.816700573f, (float16_t)-0.577061673f, + (float16_t)-0.815814411f, (float16_t)-0.578313796f, + (float16_t)-0.814926329f, (float16_t)-0.579564559f, + (float16_t)-0.814036330f, (float16_t)-0.580813958f, + (float16_t)-0.813144415f, (float16_t)-0.582061990f, + (float16_t)-0.812250587f, (float16_t)-0.583308653f, + (float16_t)-0.811354847f, (float16_t)-0.584553943f, + (float16_t)-0.810457198f, (float16_t)-0.585797857f, + (float16_t)-0.809557642f, (float16_t)-0.587040394f, + (float16_t)-0.808656182f, (float16_t)-0.588281548f, + (float16_t)-0.807752818f, (float16_t)-0.589521319f, + (float16_t)-0.806847554f, (float16_t)-0.590759702f, + (float16_t)-0.805940391f, (float16_t)-0.591996695f, + (float16_t)-0.805031331f, (float16_t)-0.593232295f, + (float16_t)-0.804120377f, (float16_t)-0.594466499f, + (float16_t)-0.803207531f, (float16_t)-0.595699304f, + (float16_t)-0.802292796f, (float16_t)-0.596930708f, + (float16_t)-0.801376172f, (float16_t)-0.598160707f, + (float16_t)-0.800457662f, (float16_t)-0.599389298f, + (float16_t)-0.799537269f, (float16_t)-0.600616479f, + (float16_t)-0.798614995f, (float16_t)-0.601842247f, + (float16_t)-0.797690841f, (float16_t)-0.603066599f, + (float16_t)-0.796764810f, (float16_t)-0.604289531f, + (float16_t)-0.795836905f, (float16_t)-0.605511041f, + (float16_t)-0.794907126f, (float16_t)-0.606731127f, + (float16_t)-0.793975478f, (float16_t)-0.607949785f, + (float16_t)-0.793041960f, (float16_t)-0.609167012f, + (float16_t)-0.792106577f, (float16_t)-0.610382806f, + (float16_t)-0.791169330f, (float16_t)-0.611597164f, + (float16_t)-0.790230221f, (float16_t)-0.612810082f, + (float16_t)-0.789289253f, (float16_t)-0.614021559f, + (float16_t)-0.788346428f, (float16_t)-0.615231591f, + (float16_t)-0.787401747f, (float16_t)-0.616440175f, + (float16_t)-0.786455214f, (float16_t)-0.617647308f, + (float16_t)-0.785506830f, (float16_t)-0.618852988f, + (float16_t)-0.784556597f, (float16_t)-0.620057212f, + (float16_t)-0.783604519f, (float16_t)-0.621259977f, + (float16_t)-0.782650596f, (float16_t)-0.622461279f, + (float16_t)-0.781694832f, (float16_t)-0.623661118f, + (float16_t)-0.780737229f, (float16_t)-0.624859488f, + (float16_t)-0.779777788f, (float16_t)-0.626056388f, + (float16_t)-0.778816512f, (float16_t)-0.627251815f, + (float16_t)-0.777853404f, (float16_t)-0.628445767f, + (float16_t)-0.776888466f, (float16_t)-0.629638239f, + (float16_t)-0.775921699f, (float16_t)-0.630829230f, + (float16_t)-0.774953107f, (float16_t)-0.632018736f, + (float16_t)-0.773982691f, (float16_t)-0.633206755f, + (float16_t)-0.773010453f, (float16_t)-0.634393284f, + (float16_t)-0.772036397f, (float16_t)-0.635578320f, + (float16_t)-0.771060524f, (float16_t)-0.636761861f, + (float16_t)-0.770082837f, (float16_t)-0.637943904f, + (float16_t)-0.769103338f, (float16_t)-0.639124445f, + (float16_t)-0.768122029f, (float16_t)-0.640303482f, + (float16_t)-0.767138912f, (float16_t)-0.641481013f, + (float16_t)-0.766153990f, (float16_t)-0.642657034f, + (float16_t)-0.765167266f, (float16_t)-0.643831543f, + (float16_t)-0.764178741f, (float16_t)-0.645004537f, + (float16_t)-0.763188417f, (float16_t)-0.646176013f, + (float16_t)-0.762196298f, (float16_t)-0.647345969f, + (float16_t)-0.761202385f, (float16_t)-0.648514401f, + (float16_t)-0.760206682f, (float16_t)-0.649681307f, + (float16_t)-0.759209189f, (float16_t)-0.650846685f, + (float16_t)-0.758209910f, (float16_t)-0.652010531f, + (float16_t)-0.757208847f, (float16_t)-0.653172843f, + (float16_t)-0.756206001f, (float16_t)-0.654333618f, + (float16_t)-0.755201377f, (float16_t)-0.655492853f, + (float16_t)-0.754194975f, (float16_t)-0.656650546f, + (float16_t)-0.753186799f, (float16_t)-0.657806693f, + (float16_t)-0.752176850f, (float16_t)-0.658961293f, + (float16_t)-0.751165132f, (float16_t)-0.660114342f, + (float16_t)-0.750151646f, (float16_t)-0.661265838f, + (float16_t)-0.749136395f, (float16_t)-0.662415778f, + (float16_t)-0.748119380f, (float16_t)-0.663564159f, + (float16_t)-0.747100606f, (float16_t)-0.664710978f, + (float16_t)-0.746080074f, (float16_t)-0.665856234f, + (float16_t)-0.745057785f, (float16_t)-0.666999922f, + (float16_t)-0.744033744f, (float16_t)-0.668142041f, + (float16_t)-0.743007952f, (float16_t)-0.669282588f, + (float16_t)-0.741980412f, (float16_t)-0.670421560f, + (float16_t)-0.740951125f, (float16_t)-0.671558955f, + (float16_t)-0.739920095f, (float16_t)-0.672694769f, + (float16_t)-0.738887324f, (float16_t)-0.673829000f, + (float16_t)-0.737852815f, (float16_t)-0.674961646f, + (float16_t)-0.736816569f, (float16_t)-0.676092704f, + (float16_t)-0.735778589f, (float16_t)-0.677222170f, + (float16_t)-0.734738878f, (float16_t)-0.678350043f, + (float16_t)-0.733697438f, (float16_t)-0.679476320f, + (float16_t)-0.732654272f, (float16_t)-0.680600998f, + (float16_t)-0.731609381f, (float16_t)-0.681724074f, + (float16_t)-0.730562769f, (float16_t)-0.682845546f, + (float16_t)-0.729514438f, (float16_t)-0.683965412f, + (float16_t)-0.728464390f, (float16_t)-0.685083668f, + (float16_t)-0.727412629f, (float16_t)-0.686200312f, + (float16_t)-0.726359155f, (float16_t)-0.687315341f, + (float16_t)-0.725303972f, (float16_t)-0.688428753f, + (float16_t)-0.724247083f, (float16_t)-0.689540545f, + (float16_t)-0.723188489f, (float16_t)-0.690650714f, + (float16_t)-0.722128194f, (float16_t)-0.691759258f, + (float16_t)-0.721066199f, (float16_t)-0.692866175f, + (float16_t)-0.720002508f, (float16_t)-0.693971461f, + (float16_t)-0.718937122f, (float16_t)-0.695075114f, + (float16_t)-0.717870045f, (float16_t)-0.696177131f, + (float16_t)-0.716801279f, (float16_t)-0.697277511f, + (float16_t)-0.715730825f, (float16_t)-0.698376249f, + (float16_t)-0.714658688f, (float16_t)-0.699473345f, + (float16_t)-0.713584869f, (float16_t)-0.700568794f, + (float16_t)-0.712509371f, (float16_t)-0.701662595f, + (float16_t)-0.711432196f, (float16_t)-0.702754744f, + (float16_t)-0.710353347f, (float16_t)-0.703845241f, + (float16_t)-0.709272826f, (float16_t)-0.704934080f, + (float16_t)-0.708190637f, (float16_t)-0.706021261f, + (float16_t)-0.707106781f, (float16_t)-0.707106781f, + (float16_t)-0.706021261f, (float16_t)-0.708190637f, + (float16_t)-0.704934080f, (float16_t)-0.709272826f, + (float16_t)-0.703845241f, (float16_t)-0.710353347f, + (float16_t)-0.702754744f, (float16_t)-0.711432196f, + (float16_t)-0.701662595f, (float16_t)-0.712509371f, + (float16_t)-0.700568794f, (float16_t)-0.713584869f, + (float16_t)-0.699473345f, (float16_t)-0.714658688f, + (float16_t)-0.698376249f, (float16_t)-0.715730825f, + (float16_t)-0.697277511f, (float16_t)-0.716801279f, + (float16_t)-0.696177131f, (float16_t)-0.717870045f, + (float16_t)-0.695075114f, (float16_t)-0.718937122f, + (float16_t)-0.693971461f, (float16_t)-0.720002508f, + (float16_t)-0.692866175f, (float16_t)-0.721066199f, + (float16_t)-0.691759258f, (float16_t)-0.722128194f, + (float16_t)-0.690650714f, (float16_t)-0.723188489f, + (float16_t)-0.689540545f, (float16_t)-0.724247083f, + (float16_t)-0.688428753f, (float16_t)-0.725303972f, + (float16_t)-0.687315341f, (float16_t)-0.726359155f, + (float16_t)-0.686200312f, (float16_t)-0.727412629f, + (float16_t)-0.685083668f, (float16_t)-0.728464390f, + (float16_t)-0.683965412f, (float16_t)-0.729514438f, + (float16_t)-0.682845546f, (float16_t)-0.730562769f, + (float16_t)-0.681724074f, (float16_t)-0.731609381f, + (float16_t)-0.680600998f, (float16_t)-0.732654272f, + (float16_t)-0.679476320f, (float16_t)-0.733697438f, + (float16_t)-0.678350043f, (float16_t)-0.734738878f, + (float16_t)-0.677222170f, (float16_t)-0.735778589f, + (float16_t)-0.676092704f, (float16_t)-0.736816569f, + (float16_t)-0.674961646f, (float16_t)-0.737852815f, + (float16_t)-0.673829000f, (float16_t)-0.738887324f, + (float16_t)-0.672694769f, (float16_t)-0.739920095f, + (float16_t)-0.671558955f, (float16_t)-0.740951125f, + (float16_t)-0.670421560f, (float16_t)-0.741980412f, + (float16_t)-0.669282588f, (float16_t)-0.743007952f, + (float16_t)-0.668142041f, (float16_t)-0.744033744f, + (float16_t)-0.666999922f, (float16_t)-0.745057785f, + (float16_t)-0.665856234f, (float16_t)-0.746080074f, + (float16_t)-0.664710978f, (float16_t)-0.747100606f, + (float16_t)-0.663564159f, (float16_t)-0.748119380f, + (float16_t)-0.662415778f, (float16_t)-0.749136395f, + (float16_t)-0.661265838f, (float16_t)-0.750151646f, + (float16_t)-0.660114342f, (float16_t)-0.751165132f, + (float16_t)-0.658961293f, (float16_t)-0.752176850f, + (float16_t)-0.657806693f, (float16_t)-0.753186799f, + (float16_t)-0.656650546f, (float16_t)-0.754194975f, + (float16_t)-0.655492853f, (float16_t)-0.755201377f, + (float16_t)-0.654333618f, (float16_t)-0.756206001f, + (float16_t)-0.653172843f, (float16_t)-0.757208847f, + (float16_t)-0.652010531f, (float16_t)-0.758209910f, + (float16_t)-0.650846685f, (float16_t)-0.759209189f, + (float16_t)-0.649681307f, (float16_t)-0.760206682f, + (float16_t)-0.648514401f, (float16_t)-0.761202385f, + (float16_t)-0.647345969f, (float16_t)-0.762196298f, + (float16_t)-0.646176013f, (float16_t)-0.763188417f, + (float16_t)-0.645004537f, (float16_t)-0.764178741f, + (float16_t)-0.643831543f, (float16_t)-0.765167266f, + (float16_t)-0.642657034f, (float16_t)-0.766153990f, + (float16_t)-0.641481013f, (float16_t)-0.767138912f, + (float16_t)-0.640303482f, (float16_t)-0.768122029f, + (float16_t)-0.639124445f, (float16_t)-0.769103338f, + (float16_t)-0.637943904f, (float16_t)-0.770082837f, + (float16_t)-0.636761861f, (float16_t)-0.771060524f, + (float16_t)-0.635578320f, (float16_t)-0.772036397f, + (float16_t)-0.634393284f, (float16_t)-0.773010453f, + (float16_t)-0.633206755f, (float16_t)-0.773982691f, + (float16_t)-0.632018736f, (float16_t)-0.774953107f, + (float16_t)-0.630829230f, (float16_t)-0.775921699f, + (float16_t)-0.629638239f, (float16_t)-0.776888466f, + (float16_t)-0.628445767f, (float16_t)-0.777853404f, + (float16_t)-0.627251815f, (float16_t)-0.778816512f, + (float16_t)-0.626056388f, (float16_t)-0.779777788f, + (float16_t)-0.624859488f, (float16_t)-0.780737229f, + (float16_t)-0.623661118f, (float16_t)-0.781694832f, + (float16_t)-0.622461279f, (float16_t)-0.782650596f, + (float16_t)-0.621259977f, (float16_t)-0.783604519f, + (float16_t)-0.620057212f, (float16_t)-0.784556597f, + (float16_t)-0.618852988f, (float16_t)-0.785506830f, + (float16_t)-0.617647308f, (float16_t)-0.786455214f, + (float16_t)-0.616440175f, (float16_t)-0.787401747f, + (float16_t)-0.615231591f, (float16_t)-0.788346428f, + (float16_t)-0.614021559f, (float16_t)-0.789289253f, + (float16_t)-0.612810082f, (float16_t)-0.790230221f, + (float16_t)-0.611597164f, (float16_t)-0.791169330f, + (float16_t)-0.610382806f, (float16_t)-0.792106577f, + (float16_t)-0.609167012f, (float16_t)-0.793041960f, + (float16_t)-0.607949785f, (float16_t)-0.793975478f, + (float16_t)-0.606731127f, (float16_t)-0.794907126f, + (float16_t)-0.605511041f, (float16_t)-0.795836905f, + (float16_t)-0.604289531f, (float16_t)-0.796764810f, + (float16_t)-0.603066599f, (float16_t)-0.797690841f, + (float16_t)-0.601842247f, (float16_t)-0.798614995f, + (float16_t)-0.600616479f, (float16_t)-0.799537269f, + (float16_t)-0.599389298f, (float16_t)-0.800457662f, + (float16_t)-0.598160707f, (float16_t)-0.801376172f, + (float16_t)-0.596930708f, (float16_t)-0.802292796f, + (float16_t)-0.595699304f, (float16_t)-0.803207531f, + (float16_t)-0.594466499f, (float16_t)-0.804120377f, + (float16_t)-0.593232295f, (float16_t)-0.805031331f, + (float16_t)-0.591996695f, (float16_t)-0.805940391f, + (float16_t)-0.590759702f, (float16_t)-0.806847554f, + (float16_t)-0.589521319f, (float16_t)-0.807752818f, + (float16_t)-0.588281548f, (float16_t)-0.808656182f, + (float16_t)-0.587040394f, (float16_t)-0.809557642f, + (float16_t)-0.585797857f, (float16_t)-0.810457198f, + (float16_t)-0.584553943f, (float16_t)-0.811354847f, + (float16_t)-0.583308653f, (float16_t)-0.812250587f, + (float16_t)-0.582061990f, (float16_t)-0.813144415f, + (float16_t)-0.580813958f, (float16_t)-0.814036330f, + (float16_t)-0.579564559f, (float16_t)-0.814926329f, + (float16_t)-0.578313796f, (float16_t)-0.815814411f, + (float16_t)-0.577061673f, (float16_t)-0.816700573f, + (float16_t)-0.575808191f, (float16_t)-0.817584813f, + (float16_t)-0.574553355f, (float16_t)-0.818467130f, + (float16_t)-0.573297167f, (float16_t)-0.819347520f, + (float16_t)-0.572039629f, (float16_t)-0.820225983f, + (float16_t)-0.570780746f, (float16_t)-0.821102515f, + (float16_t)-0.569520519f, (float16_t)-0.821977115f, + (float16_t)-0.568258953f, (float16_t)-0.822849781f, + (float16_t)-0.566996049f, (float16_t)-0.823720511f, + (float16_t)-0.565731811f, (float16_t)-0.824589303f, + (float16_t)-0.564466242f, (float16_t)-0.825456154f, + (float16_t)-0.563199344f, (float16_t)-0.826321063f, + (float16_t)-0.561931121f, (float16_t)-0.827184027f, + (float16_t)-0.560661576f, (float16_t)-0.828045045f, + (float16_t)-0.559390712f, (float16_t)-0.828904115f, + (float16_t)-0.558118531f, (float16_t)-0.829761234f, + (float16_t)-0.556845037f, (float16_t)-0.830616400f, + (float16_t)-0.555570233f, (float16_t)-0.831469612f, + (float16_t)-0.554294121f, (float16_t)-0.832320868f, + (float16_t)-0.553016706f, (float16_t)-0.833170165f, + (float16_t)-0.551737988f, (float16_t)-0.834017501f, + (float16_t)-0.550457973f, (float16_t)-0.834862875f, + (float16_t)-0.549176662f, (float16_t)-0.835706284f, + (float16_t)-0.547894059f, (float16_t)-0.836547727f, + (float16_t)-0.546610167f, (float16_t)-0.837387202f, + (float16_t)-0.545324988f, (float16_t)-0.838224706f, + (float16_t)-0.544038527f, (float16_t)-0.839060237f, + (float16_t)-0.542750785f, (float16_t)-0.839893794f, + (float16_t)-0.541461766f, (float16_t)-0.840725375f, + (float16_t)-0.540171473f, (float16_t)-0.841554977f, + (float16_t)-0.538879909f, (float16_t)-0.842382600f, + (float16_t)-0.537587076f, (float16_t)-0.843208240f, + (float16_t)-0.536292979f, (float16_t)-0.844031895f, + (float16_t)-0.534997620f, (float16_t)-0.844853565f, + (float16_t)-0.533701002f, (float16_t)-0.845673247f, + (float16_t)-0.532403128f, (float16_t)-0.846490939f, + (float16_t)-0.531104001f, (float16_t)-0.847306639f, + (float16_t)-0.529803625f, (float16_t)-0.848120345f, + (float16_t)-0.528502002f, (float16_t)-0.848932055f, + (float16_t)-0.527199135f, (float16_t)-0.849741768f, + (float16_t)-0.525895027f, (float16_t)-0.850549481f, + (float16_t)-0.524589683f, (float16_t)-0.851355193f, + (float16_t)-0.523283103f, (float16_t)-0.852158902f, + (float16_t)-0.521975293f, (float16_t)-0.852960605f, + (float16_t)-0.520666254f, (float16_t)-0.853760301f, + (float16_t)-0.519355990f, (float16_t)-0.854557988f, + (float16_t)-0.518044504f, (float16_t)-0.855353665f, + (float16_t)-0.516731799f, (float16_t)-0.856147328f, + (float16_t)-0.515417878f, (float16_t)-0.856938977f, + (float16_t)-0.514102744f, (float16_t)-0.857728610f, + (float16_t)-0.512786401f, (float16_t)-0.858516224f, + (float16_t)-0.511468850f, (float16_t)-0.859301818f, + (float16_t)-0.510150097f, (float16_t)-0.860085390f, + (float16_t)-0.508830143f, (float16_t)-0.860866939f, + (float16_t)-0.507508991f, (float16_t)-0.861646461f, + (float16_t)-0.506186645f, (float16_t)-0.862423956f, + (float16_t)-0.504863109f, (float16_t)-0.863199422f, + (float16_t)-0.503538384f, (float16_t)-0.863972856f, + (float16_t)-0.502212474f, (float16_t)-0.864744258f, + (float16_t)-0.500885383f, (float16_t)-0.865513624f, + (float16_t)-0.499557113f, (float16_t)-0.866280954f, + (float16_t)-0.498227667f, (float16_t)-0.867046246f, + (float16_t)-0.496897049f, (float16_t)-0.867809497f, + (float16_t)-0.495565262f, (float16_t)-0.868570706f, + (float16_t)-0.494232309f, (float16_t)-0.869329871f, + (float16_t)-0.492898192f, (float16_t)-0.870086991f, + (float16_t)-0.491562916f, (float16_t)-0.870842063f, + (float16_t)-0.490226483f, (float16_t)-0.871595087f, + (float16_t)-0.488888897f, (float16_t)-0.872346059f, + (float16_t)-0.487550160f, (float16_t)-0.873094978f, + (float16_t)-0.486210276f, (float16_t)-0.873841843f, + (float16_t)-0.484869248f, (float16_t)-0.874586652f, + (float16_t)-0.483527079f, (float16_t)-0.875329403f, + (float16_t)-0.482183772f, (float16_t)-0.876070094f, + (float16_t)-0.480839331f, (float16_t)-0.876808724f, + (float16_t)-0.479493758f, (float16_t)-0.877545290f, + (float16_t)-0.478147056f, (float16_t)-0.878279792f, + (float16_t)-0.476799230f, (float16_t)-0.879012226f, + (float16_t)-0.475450282f, (float16_t)-0.879742593f, + (float16_t)-0.474100215f, (float16_t)-0.880470889f, + (float16_t)-0.472749032f, (float16_t)-0.881197113f, + (float16_t)-0.471396737f, (float16_t)-0.881921264f, + (float16_t)-0.470043332f, (float16_t)-0.882643340f, + (float16_t)-0.468688822f, (float16_t)-0.883363339f, + (float16_t)-0.467333209f, (float16_t)-0.884081259f, + (float16_t)-0.465976496f, (float16_t)-0.884797098f, + (float16_t)-0.464618686f, (float16_t)-0.885510856f, + (float16_t)-0.463259784f, (float16_t)-0.886222530f, + (float16_t)-0.461899791f, (float16_t)-0.886932119f, + (float16_t)-0.460538711f, (float16_t)-0.887639620f, + (float16_t)-0.459176548f, (float16_t)-0.888345033f, + (float16_t)-0.457813304f, (float16_t)-0.889048356f, + (float16_t)-0.456448982f, (float16_t)-0.889749586f, + (float16_t)-0.455083587f, (float16_t)-0.890448723f, + (float16_t)-0.453717121f, (float16_t)-0.891145765f, + (float16_t)-0.452349587f, (float16_t)-0.891840709f, + (float16_t)-0.450980989f, (float16_t)-0.892533555f, + (float16_t)-0.449611330f, (float16_t)-0.893224301f, + (float16_t)-0.448240612f, (float16_t)-0.893912945f, + (float16_t)-0.446868840f, (float16_t)-0.894599486f, + (float16_t)-0.445496017f, (float16_t)-0.895283921f, + (float16_t)-0.444122145f, (float16_t)-0.895966250f, + (float16_t)-0.442747228f, (float16_t)-0.896646470f, + (float16_t)-0.441371269f, (float16_t)-0.897324581f, + (float16_t)-0.439994271f, (float16_t)-0.898000580f, + (float16_t)-0.438616239f, (float16_t)-0.898674466f, + (float16_t)-0.437237174f, (float16_t)-0.899346237f, + (float16_t)-0.435857080f, (float16_t)-0.900015892f, + (float16_t)-0.434475961f, (float16_t)-0.900683429f, + (float16_t)-0.433093819f, (float16_t)-0.901348847f, + (float16_t)-0.431710658f, (float16_t)-0.902012144f, + (float16_t)-0.430326481f, (float16_t)-0.902673318f, + (float16_t)-0.428941292f, (float16_t)-0.903332368f, + (float16_t)-0.427555093f, (float16_t)-0.903989293f, + (float16_t)-0.426167889f, (float16_t)-0.904644091f, + (float16_t)-0.424779681f, (float16_t)-0.905296759f, + (float16_t)-0.423390474f, (float16_t)-0.905947298f, + (float16_t)-0.422000271f, (float16_t)-0.906595705f, + (float16_t)-0.420609074f, (float16_t)-0.907241978f, + (float16_t)-0.419216888f, (float16_t)-0.907886116f, + (float16_t)-0.417823716f, (float16_t)-0.908528119f, + (float16_t)-0.416429560f, (float16_t)-0.909167983f, + (float16_t)-0.415034424f, (float16_t)-0.909805708f, + (float16_t)-0.413638312f, (float16_t)-0.910441292f, + (float16_t)-0.412241227f, (float16_t)-0.911074734f, + (float16_t)-0.410843171f, (float16_t)-0.911706032f, + (float16_t)-0.409444149f, (float16_t)-0.912335185f, + (float16_t)-0.408044163f, (float16_t)-0.912962190f, + (float16_t)-0.406643217f, (float16_t)-0.913587048f, + (float16_t)-0.405241314f, (float16_t)-0.914209756f, + (float16_t)-0.403838458f, (float16_t)-0.914830312f, + (float16_t)-0.402434651f, (float16_t)-0.915448716f, + (float16_t)-0.401029897f, (float16_t)-0.916064966f, + (float16_t)-0.399624200f, (float16_t)-0.916679060f, + (float16_t)-0.398217562f, (float16_t)-0.917290997f, + (float16_t)-0.396809987f, (float16_t)-0.917900776f, + (float16_t)-0.395401479f, (float16_t)-0.918508394f, + (float16_t)-0.393992040f, (float16_t)-0.919113852f, + (float16_t)-0.392581674f, (float16_t)-0.919717146f, + (float16_t)-0.391170384f, (float16_t)-0.920318277f, + (float16_t)-0.389758174f, (float16_t)-0.920917242f, + (float16_t)-0.388345047f, (float16_t)-0.921514039f, + (float16_t)-0.386931006f, (float16_t)-0.922108669f, + (float16_t)-0.385516054f, (float16_t)-0.922701128f, + (float16_t)-0.384100195f, (float16_t)-0.923291417f, + (float16_t)-0.382683432f, (float16_t)-0.923879533f, + (float16_t)-0.381265769f, (float16_t)-0.924465474f, + (float16_t)-0.379847209f, (float16_t)-0.925049241f, + (float16_t)-0.378427755f, (float16_t)-0.925630831f, + (float16_t)-0.377007410f, (float16_t)-0.926210242f, + (float16_t)-0.375586178f, (float16_t)-0.926787474f, + (float16_t)-0.374164063f, (float16_t)-0.927362526f, + (float16_t)-0.372741067f, (float16_t)-0.927935395f, + (float16_t)-0.371317194f, (float16_t)-0.928506080f, + (float16_t)-0.369892447f, (float16_t)-0.929074581f, + (float16_t)-0.368466830f, (float16_t)-0.929640896f, + (float16_t)-0.367040346f, (float16_t)-0.930205023f, + (float16_t)-0.365612998f, (float16_t)-0.930766961f, + (float16_t)-0.364184790f, (float16_t)-0.931326709f, + (float16_t)-0.362755724f, (float16_t)-0.931884266f, + (float16_t)-0.361325806f, (float16_t)-0.932439629f, + (float16_t)-0.359895037f, (float16_t)-0.932992799f, + (float16_t)-0.358463421f, (float16_t)-0.933543773f, + (float16_t)-0.357030961f, (float16_t)-0.934092550f, + (float16_t)-0.355597662f, (float16_t)-0.934639130f, + (float16_t)-0.354163525f, (float16_t)-0.935183510f, + (float16_t)-0.352728556f, (float16_t)-0.935725689f, + (float16_t)-0.351292756f, (float16_t)-0.936265667f, + (float16_t)-0.349856130f, (float16_t)-0.936803442f, + (float16_t)-0.348418680f, (float16_t)-0.937339012f, + (float16_t)-0.346980411f, (float16_t)-0.937872376f, + (float16_t)-0.345541325f, (float16_t)-0.938403534f, + (float16_t)-0.344101426f, (float16_t)-0.938932484f, + (float16_t)-0.342660717f, (float16_t)-0.939459224f, + (float16_t)-0.341219202f, (float16_t)-0.939983753f, + (float16_t)-0.339776884f, (float16_t)-0.940506071f, + (float16_t)-0.338333767f, (float16_t)-0.941026175f, + (float16_t)-0.336889853f, (float16_t)-0.941544065f, + (float16_t)-0.335445147f, (float16_t)-0.942059740f, + (float16_t)-0.333999651f, (float16_t)-0.942573198f, + (float16_t)-0.332553370f, (float16_t)-0.943084437f, + (float16_t)-0.331106306f, (float16_t)-0.943593458f, + (float16_t)-0.329658463f, (float16_t)-0.944100258f, + (float16_t)-0.328209844f, (float16_t)-0.944604837f, + (float16_t)-0.326760452f, (float16_t)-0.945107193f, + (float16_t)-0.325310292f, (float16_t)-0.945607325f, + (float16_t)-0.323859367f, (float16_t)-0.946105232f, + (float16_t)-0.322407679f, (float16_t)-0.946600913f, + (float16_t)-0.320955232f, (float16_t)-0.947094366f, + (float16_t)-0.319502031f, (float16_t)-0.947585591f, + (float16_t)-0.318048077f, (float16_t)-0.948074586f, + (float16_t)-0.316593376f, (float16_t)-0.948561350f, + (float16_t)-0.315137929f, (float16_t)-0.949045882f, + (float16_t)-0.313681740f, (float16_t)-0.949528181f, + (float16_t)-0.312224814f, (float16_t)-0.950008245f, + (float16_t)-0.310767153f, (float16_t)-0.950486074f, + (float16_t)-0.309308760f, (float16_t)-0.950961666f, + (float16_t)-0.307849640f, (float16_t)-0.951435021f, + (float16_t)-0.306389795f, (float16_t)-0.951906137f, + (float16_t)-0.304929230f, (float16_t)-0.952375013f, + (float16_t)-0.303467947f, (float16_t)-0.952841648f, + (float16_t)-0.302005949f, (float16_t)-0.953306040f, + (float16_t)-0.300543241f, (float16_t)-0.953768190f, + (float16_t)-0.299079826f, (float16_t)-0.954228095f, + (float16_t)-0.297615707f, (float16_t)-0.954685755f, + (float16_t)-0.296150888f, (float16_t)-0.955141168f, + (float16_t)-0.294685372f, (float16_t)-0.955594334f, + (float16_t)-0.293219163f, (float16_t)-0.956045251f, + (float16_t)-0.291752263f, (float16_t)-0.956493919f, + (float16_t)-0.290284677f, (float16_t)-0.956940336f, + (float16_t)-0.288816408f, (float16_t)-0.957384501f, + (float16_t)-0.287347460f, (float16_t)-0.957826413f, + (float16_t)-0.285877835f, (float16_t)-0.958266071f, + (float16_t)-0.284407537f, (float16_t)-0.958703475f, + (float16_t)-0.282936570f, (float16_t)-0.959138622f, + (float16_t)-0.281464938f, (float16_t)-0.959571513f, + (float16_t)-0.279992643f, (float16_t)-0.960002146f, + (float16_t)-0.278519689f, (float16_t)-0.960430519f, + (float16_t)-0.277046080f, (float16_t)-0.960856633f, + (float16_t)-0.275571819f, (float16_t)-0.961280486f, + (float16_t)-0.274096910f, (float16_t)-0.961702077f, + (float16_t)-0.272621355f, (float16_t)-0.962121404f, + (float16_t)-0.271145160f, (float16_t)-0.962538468f, + (float16_t)-0.269668326f, (float16_t)-0.962953267f, + (float16_t)-0.268190857f, (float16_t)-0.963365800f, + (float16_t)-0.266712757f, (float16_t)-0.963776066f, + (float16_t)-0.265234030f, (float16_t)-0.964184064f, + (float16_t)-0.263754679f, (float16_t)-0.964589793f, + (float16_t)-0.262274707f, (float16_t)-0.964993253f, + (float16_t)-0.260794118f, (float16_t)-0.965394442f, + (float16_t)-0.259312915f, (float16_t)-0.965793359f, + (float16_t)-0.257831102f, (float16_t)-0.966190003f, + (float16_t)-0.256348682f, (float16_t)-0.966584374f, + (float16_t)-0.254865660f, (float16_t)-0.966976471f, + (float16_t)-0.253382037f, (float16_t)-0.967366292f, + (float16_t)-0.251897818f, (float16_t)-0.967753837f, + (float16_t)-0.250413007f, (float16_t)-0.968139105f, + (float16_t)-0.248927606f, (float16_t)-0.968522094f, + (float16_t)-0.247441619f, (float16_t)-0.968902805f, + (float16_t)-0.245955050f, (float16_t)-0.969281235f, + (float16_t)-0.244467903f, (float16_t)-0.969657385f, + (float16_t)-0.242980180f, (float16_t)-0.970031253f, + (float16_t)-0.241491885f, (float16_t)-0.970402839f, + (float16_t)-0.240003022f, (float16_t)-0.970772141f, + (float16_t)-0.238513595f, (float16_t)-0.971139158f, + (float16_t)-0.237023606f, (float16_t)-0.971503891f, + (float16_t)-0.235533059f, (float16_t)-0.971866337f, + (float16_t)-0.234041959f, (float16_t)-0.972226497f, + (float16_t)-0.232550307f, (float16_t)-0.972584369f, + (float16_t)-0.231058108f, (float16_t)-0.972939952f, + (float16_t)-0.229565366f, (float16_t)-0.973293246f, + (float16_t)-0.228072083f, (float16_t)-0.973644250f, + (float16_t)-0.226578264f, (float16_t)-0.973992962f, + (float16_t)-0.225083911f, (float16_t)-0.974339383f, + (float16_t)-0.223589029f, (float16_t)-0.974683511f, + (float16_t)-0.222093621f, (float16_t)-0.975025345f, + (float16_t)-0.220597690f, (float16_t)-0.975364885f, + (float16_t)-0.219101240f, (float16_t)-0.975702130f, + (float16_t)-0.217604275f, (float16_t)-0.976037079f, + (float16_t)-0.216106797f, (float16_t)-0.976369731f, + (float16_t)-0.214608811f, (float16_t)-0.976700086f, + (float16_t)-0.213110320f, (float16_t)-0.977028143f, + (float16_t)-0.211611327f, (float16_t)-0.977353900f, + (float16_t)-0.210111837f, (float16_t)-0.977677358f, + (float16_t)-0.208611852f, (float16_t)-0.977998515f, + (float16_t)-0.207111376f, (float16_t)-0.978317371f, + (float16_t)-0.205610413f, (float16_t)-0.978633924f, + (float16_t)-0.204108966f, (float16_t)-0.978948175f, + (float16_t)-0.202607039f, (float16_t)-0.979260123f, + (float16_t)-0.201104635f, (float16_t)-0.979569766f, + (float16_t)-0.199601758f, (float16_t)-0.979877104f, + (float16_t)-0.198098411f, (float16_t)-0.980182136f, + (float16_t)-0.196594598f, (float16_t)-0.980484862f, + (float16_t)-0.195090322f, (float16_t)-0.980785280f, + (float16_t)-0.193585587f, (float16_t)-0.981083391f, + (float16_t)-0.192080397f, (float16_t)-0.981379193f, + (float16_t)-0.190574755f, (float16_t)-0.981672686f, + (float16_t)-0.189068664f, (float16_t)-0.981963869f, + (float16_t)-0.187562129f, (float16_t)-0.982252741f, + (float16_t)-0.186055152f, (float16_t)-0.982539302f, + (float16_t)-0.184547737f, (float16_t)-0.982823551f, + (float16_t)-0.183039888f, (float16_t)-0.983105487f, + (float16_t)-0.181531608f, (float16_t)-0.983385110f, + (float16_t)-0.180022901f, (float16_t)-0.983662419f, + (float16_t)-0.178513771f, (float16_t)-0.983937413f, + (float16_t)-0.177004220f, (float16_t)-0.984210092f, + (float16_t)-0.175494253f, (float16_t)-0.984480455f, + (float16_t)-0.173983873f, (float16_t)-0.984748502f, + (float16_t)-0.172473084f, (float16_t)-0.985014231f, + (float16_t)-0.170961889f, (float16_t)-0.985277642f, + (float16_t)-0.169450291f, (float16_t)-0.985538735f, + (float16_t)-0.167938295f, (float16_t)-0.985797509f, + (float16_t)-0.166425904f, (float16_t)-0.986053963f, + (float16_t)-0.164913120f, (float16_t)-0.986308097f, + (float16_t)-0.163399949f, (float16_t)-0.986559910f, + (float16_t)-0.161886394f, (float16_t)-0.986809402f, + (float16_t)-0.160372457f, (float16_t)-0.987056571f, + (float16_t)-0.158858143f, (float16_t)-0.987301418f, + (float16_t)-0.157343456f, (float16_t)-0.987543942f, + (float16_t)-0.155828398f, (float16_t)-0.987784142f, + (float16_t)-0.154312973f, (float16_t)-0.988022017f, + (float16_t)-0.152797185f, (float16_t)-0.988257568f, + (float16_t)-0.151281038f, (float16_t)-0.988490793f, + (float16_t)-0.149764535f, (float16_t)-0.988721692f, + (float16_t)-0.148247679f, (float16_t)-0.988950265f, + (float16_t)-0.146730474f, (float16_t)-0.989176510f, + (float16_t)-0.145212925f, (float16_t)-0.989400428f, + (float16_t)-0.143695033f, (float16_t)-0.989622017f, + (float16_t)-0.142176804f, (float16_t)-0.989841278f, + (float16_t)-0.140658239f, (float16_t)-0.990058210f, + (float16_t)-0.139139344f, (float16_t)-0.990272812f, + (float16_t)-0.137620122f, (float16_t)-0.990485084f, + (float16_t)-0.136100575f, (float16_t)-0.990695025f, + (float16_t)-0.134580709f, (float16_t)-0.990902635f, + (float16_t)-0.133060525f, (float16_t)-0.991107914f, + (float16_t)-0.131540029f, (float16_t)-0.991310860f, + (float16_t)-0.130019223f, (float16_t)-0.991511473f, + (float16_t)-0.128498111f, (float16_t)-0.991709754f, + (float16_t)-0.126976696f, (float16_t)-0.991905700f, + (float16_t)-0.125454983f, (float16_t)-0.992099313f, + (float16_t)-0.123932975f, (float16_t)-0.992290591f, + (float16_t)-0.122410675f, (float16_t)-0.992479535f, + (float16_t)-0.120888087f, (float16_t)-0.992666142f, + (float16_t)-0.119365215f, (float16_t)-0.992850414f, + (float16_t)-0.117842062f, (float16_t)-0.993032350f, + (float16_t)-0.116318631f, (float16_t)-0.993211949f, + (float16_t)-0.114794927f, (float16_t)-0.993389211f, + (float16_t)-0.113270952f, (float16_t)-0.993564136f, + (float16_t)-0.111746711f, (float16_t)-0.993736722f, + (float16_t)-0.110222207f, (float16_t)-0.993906970f, + (float16_t)-0.108697444f, (float16_t)-0.994074879f, + (float16_t)-0.107172425f, (float16_t)-0.994240449f, + (float16_t)-0.105647154f, (float16_t)-0.994403680f, + (float16_t)-0.104121634f, (float16_t)-0.994564571f, + (float16_t)-0.102595869f, (float16_t)-0.994723121f, + (float16_t)-0.101069863f, (float16_t)-0.994879331f, + (float16_t)-0.099543619f, (float16_t)-0.995033199f, + (float16_t)-0.098017140f, (float16_t)-0.995184727f, + (float16_t)-0.096490431f, (float16_t)-0.995333912f, + (float16_t)-0.094963495f, (float16_t)-0.995480755f, + (float16_t)-0.093436336f, (float16_t)-0.995625256f, + (float16_t)-0.091908956f, (float16_t)-0.995767414f, + (float16_t)-0.090381361f, (float16_t)-0.995907229f, + (float16_t)-0.088853553f, (float16_t)-0.996044701f, + (float16_t)-0.087325535f, (float16_t)-0.996179829f, + (float16_t)-0.085797312f, (float16_t)-0.996312612f, + (float16_t)-0.084268888f, (float16_t)-0.996443051f, + (float16_t)-0.082740265f, (float16_t)-0.996571146f, + (float16_t)-0.081211447f, (float16_t)-0.996696895f, + (float16_t)-0.079682438f, (float16_t)-0.996820299f, + (float16_t)-0.078153242f, (float16_t)-0.996941358f, + (float16_t)-0.076623861f, (float16_t)-0.997060070f, + (float16_t)-0.075094301f, (float16_t)-0.997176437f, + (float16_t)-0.073564564f, (float16_t)-0.997290457f, + (float16_t)-0.072034653f, (float16_t)-0.997402130f, + (float16_t)-0.070504573f, (float16_t)-0.997511456f, + (float16_t)-0.068974328f, (float16_t)-0.997618435f, + (float16_t)-0.067443920f, (float16_t)-0.997723067f, + (float16_t)-0.065913353f, (float16_t)-0.997825350f, + (float16_t)-0.064382631f, (float16_t)-0.997925286f, + (float16_t)-0.062851758f, (float16_t)-0.998022874f, + (float16_t)-0.061320736f, (float16_t)-0.998118113f, + (float16_t)-0.059789571f, (float16_t)-0.998211003f, + (float16_t)-0.058258265f, (float16_t)-0.998301545f, + (float16_t)-0.056726821f, (float16_t)-0.998389737f, + (float16_t)-0.055195244f, (float16_t)-0.998475581f, + (float16_t)-0.053663538f, (float16_t)-0.998559074f, + (float16_t)-0.052131705f, (float16_t)-0.998640218f, + (float16_t)-0.050599749f, (float16_t)-0.998719012f, + (float16_t)-0.049067674f, (float16_t)-0.998795456f, + (float16_t)-0.047535484f, (float16_t)-0.998869550f, + (float16_t)-0.046003182f, (float16_t)-0.998941293f, + (float16_t)-0.044470772f, (float16_t)-0.999010686f, + (float16_t)-0.042938257f, (float16_t)-0.999077728f, + (float16_t)-0.041405641f, (float16_t)-0.999142419f, + (float16_t)-0.039872928f, (float16_t)-0.999204759f, + (float16_t)-0.038340120f, (float16_t)-0.999264747f, + (float16_t)-0.036807223f, (float16_t)-0.999322385f, + (float16_t)-0.035274239f, (float16_t)-0.999377670f, + (float16_t)-0.033741172f, (float16_t)-0.999430605f, + (float16_t)-0.032208025f, (float16_t)-0.999481187f, + (float16_t)-0.030674803f, (float16_t)-0.999529418f, + (float16_t)-0.029141509f, (float16_t)-0.999575296f, + (float16_t)-0.027608146f, (float16_t)-0.999618822f, + (float16_t)-0.026074718f, (float16_t)-0.999659997f, + (float16_t)-0.024541229f, (float16_t)-0.999698819f, + (float16_t)-0.023007681f, (float16_t)-0.999735288f, + (float16_t)-0.021474080f, (float16_t)-0.999769405f, + (float16_t)-0.019940429f, (float16_t)-0.999801170f, + (float16_t)-0.018406730f, (float16_t)-0.999830582f, + (float16_t)-0.016872988f, (float16_t)-0.999857641f, + (float16_t)-0.015339206f, (float16_t)-0.999882347f, + (float16_t)-0.013805389f, (float16_t)-0.999904701f, + (float16_t)-0.012271538f, (float16_t)-0.999924702f, + (float16_t)-0.010737659f, (float16_t)-0.999942350f, + (float16_t)-0.009203755f, (float16_t)-0.999957645f, + (float16_t)-0.007669829f, (float16_t)-0.999970586f, + (float16_t)-0.006135885f, (float16_t)-0.999981175f, + (float16_t)-0.004601926f, (float16_t)-0.999989411f, + (float16_t)-0.003067957f, (float16_t)-0.999995294f, + (float16_t)-0.001533980f, (float16_t)-0.999998823f, + (float16_t)-0.000000000f, (float16_t)-1.000000000f, + (float16_t)0.001533980f, (float16_t)-0.999998823f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.084268888f, (float16_t)-0.996443051f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.087325535f, (float16_t)-0.996179829f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.090381361f, (float16_t)-0.995907229f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.093436336f, (float16_t)-0.995625256f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.096490431f, (float16_t)-0.995333912f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.099543619f, (float16_t)-0.995033199f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.102595869f, (float16_t)-0.994723121f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.105647154f, (float16_t)-0.994403680f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.108697444f, (float16_t)-0.994074879f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.111746711f, (float16_t)-0.993736722f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.114794927f, (float16_t)-0.993389211f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.117842062f, (float16_t)-0.993032350f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.120888087f, (float16_t)-0.992666142f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.123932975f, (float16_t)-0.992290591f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.126976696f, (float16_t)-0.991905700f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.130019223f, (float16_t)-0.991511473f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.133060525f, (float16_t)-0.991107914f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.136100575f, (float16_t)-0.990695025f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.139139344f, (float16_t)-0.990272812f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.142176804f, (float16_t)-0.989841278f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.145212925f, (float16_t)-0.989400428f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.148247679f, (float16_t)-0.988950265f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.151281038f, (float16_t)-0.988490793f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.154312973f, (float16_t)-0.988022017f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.157343456f, (float16_t)-0.987543942f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.160372457f, (float16_t)-0.987056571f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.163399949f, (float16_t)-0.986559910f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.166425904f, (float16_t)-0.986053963f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.169450291f, (float16_t)-0.985538735f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.172473084f, (float16_t)-0.985014231f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.175494253f, (float16_t)-0.984480455f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.178513771f, (float16_t)-0.983937413f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.181531608f, (float16_t)-0.983385110f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.184547737f, (float16_t)-0.982823551f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.187562129f, (float16_t)-0.982252741f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.190574755f, (float16_t)-0.981672686f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.193585587f, (float16_t)-0.981083391f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.196594598f, (float16_t)-0.980484862f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.199601758f, (float16_t)-0.979877104f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.202607039f, (float16_t)-0.979260123f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.205610413f, (float16_t)-0.978633924f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.208611852f, (float16_t)-0.977998515f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.211611327f, (float16_t)-0.977353900f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.214608811f, (float16_t)-0.976700086f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.217604275f, (float16_t)-0.976037079f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.220597690f, (float16_t)-0.975364885f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.223589029f, (float16_t)-0.974683511f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.226578264f, (float16_t)-0.973992962f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.229565366f, (float16_t)-0.973293246f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.232550307f, (float16_t)-0.972584369f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.235533059f, (float16_t)-0.971866337f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.238513595f, (float16_t)-0.971139158f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.241491885f, (float16_t)-0.970402839f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.244467903f, (float16_t)-0.969657385f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.247441619f, (float16_t)-0.968902805f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.250413007f, (float16_t)-0.968139105f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.253382037f, (float16_t)-0.967366292f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.256348682f, (float16_t)-0.966584374f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.259312915f, (float16_t)-0.965793359f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.262274707f, (float16_t)-0.964993253f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.265234030f, (float16_t)-0.964184064f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.268190857f, (float16_t)-0.963365800f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.271145160f, (float16_t)-0.962538468f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.274096910f, (float16_t)-0.961702077f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.277046080f, (float16_t)-0.960856633f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.279992643f, (float16_t)-0.960002146f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.282936570f, (float16_t)-0.959138622f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.285877835f, (float16_t)-0.958266071f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.288816408f, (float16_t)-0.957384501f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.291752263f, (float16_t)-0.956493919f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.294685372f, (float16_t)-0.955594334f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.297615707f, (float16_t)-0.954685755f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.300543241f, (float16_t)-0.953768190f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.303467947f, (float16_t)-0.952841648f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.306389795f, (float16_t)-0.951906137f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.309308760f, (float16_t)-0.950961666f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.312224814f, (float16_t)-0.950008245f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.315137929f, (float16_t)-0.949045882f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.318048077f, (float16_t)-0.948074586f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.320955232f, (float16_t)-0.947094366f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.323859367f, (float16_t)-0.946105232f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.326760452f, (float16_t)-0.945107193f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.329658463f, (float16_t)-0.944100258f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.332553370f, (float16_t)-0.943084437f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.335445147f, (float16_t)-0.942059740f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.338333767f, (float16_t)-0.941026175f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.341219202f, (float16_t)-0.939983753f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.344101426f, (float16_t)-0.938932484f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.346980411f, (float16_t)-0.937872376f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.349856130f, (float16_t)-0.936803442f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.352728556f, (float16_t)-0.935725689f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.355597662f, (float16_t)-0.934639130f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.358463421f, (float16_t)-0.933543773f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.361325806f, (float16_t)-0.932439629f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.364184790f, (float16_t)-0.931326709f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.367040346f, (float16_t)-0.930205023f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.369892447f, (float16_t)-0.929074581f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.372741067f, (float16_t)-0.927935395f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.375586178f, (float16_t)-0.926787474f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.378427755f, (float16_t)-0.925630831f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.381265769f, (float16_t)-0.924465474f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.384100195f, (float16_t)-0.923291417f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.386931006f, (float16_t)-0.922108669f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.389758174f, (float16_t)-0.920917242f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.392581674f, (float16_t)-0.919717146f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.395401479f, (float16_t)-0.918508394f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.398217562f, (float16_t)-0.917290997f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.401029897f, (float16_t)-0.916064966f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.403838458f, (float16_t)-0.914830312f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.406643217f, (float16_t)-0.913587048f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.409444149f, (float16_t)-0.912335185f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.412241227f, (float16_t)-0.911074734f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.415034424f, (float16_t)-0.909805708f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.417823716f, (float16_t)-0.908528119f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.420609074f, (float16_t)-0.907241978f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.423390474f, (float16_t)-0.905947298f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.426167889f, (float16_t)-0.904644091f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.428941292f, (float16_t)-0.903332368f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.431710658f, (float16_t)-0.902012144f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.434475961f, (float16_t)-0.900683429f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.437237174f, (float16_t)-0.899346237f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.439994271f, (float16_t)-0.898000580f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.442747228f, (float16_t)-0.896646470f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.445496017f, (float16_t)-0.895283921f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.448240612f, (float16_t)-0.893912945f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.450980989f, (float16_t)-0.892533555f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.453717121f, (float16_t)-0.891145765f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.456448982f, (float16_t)-0.889749586f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.459176548f, (float16_t)-0.888345033f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.461899791f, (float16_t)-0.886932119f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.464618686f, (float16_t)-0.885510856f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.467333209f, (float16_t)-0.884081259f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.470043332f, (float16_t)-0.882643340f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.472749032f, (float16_t)-0.881197113f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.475450282f, (float16_t)-0.879742593f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.478147056f, (float16_t)-0.878279792f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.480839331f, (float16_t)-0.876808724f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.483527079f, (float16_t)-0.875329403f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.486210276f, (float16_t)-0.873841843f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.488888897f, (float16_t)-0.872346059f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.491562916f, (float16_t)-0.870842063f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.494232309f, (float16_t)-0.869329871f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.496897049f, (float16_t)-0.867809497f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.499557113f, (float16_t)-0.866280954f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.502212474f, (float16_t)-0.864744258f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.504863109f, (float16_t)-0.863199422f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.507508991f, (float16_t)-0.861646461f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.510150097f, (float16_t)-0.860085390f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.512786401f, (float16_t)-0.858516224f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.515417878f, (float16_t)-0.856938977f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.518044504f, (float16_t)-0.855353665f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.520666254f, (float16_t)-0.853760301f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.523283103f, (float16_t)-0.852158902f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.525895027f, (float16_t)-0.850549481f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.528502002f, (float16_t)-0.848932055f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.531104001f, (float16_t)-0.847306639f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.533701002f, (float16_t)-0.845673247f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.536292979f, (float16_t)-0.844031895f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.538879909f, (float16_t)-0.842382600f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.541461766f, (float16_t)-0.840725375f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.544038527f, (float16_t)-0.839060237f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.546610167f, (float16_t)-0.837387202f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.549176662f, (float16_t)-0.835706284f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.551737988f, (float16_t)-0.834017501f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.554294121f, (float16_t)-0.832320868f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.556845037f, (float16_t)-0.830616400f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.559390712f, (float16_t)-0.828904115f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.561931121f, (float16_t)-0.827184027f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.564466242f, (float16_t)-0.825456154f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.566996049f, (float16_t)-0.823720511f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.569520519f, (float16_t)-0.821977115f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.572039629f, (float16_t)-0.820225983f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.574553355f, (float16_t)-0.818467130f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.577061673f, (float16_t)-0.816700573f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.579564559f, (float16_t)-0.814926329f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.582061990f, (float16_t)-0.813144415f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.584553943f, (float16_t)-0.811354847f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.587040394f, (float16_t)-0.809557642f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.589521319f, (float16_t)-0.807752818f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.591996695f, (float16_t)-0.805940391f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.594466499f, (float16_t)-0.804120377f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.596930708f, (float16_t)-0.802292796f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.599389298f, (float16_t)-0.800457662f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.601842247f, (float16_t)-0.798614995f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.604289531f, (float16_t)-0.796764810f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.606731127f, (float16_t)-0.794907126f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.609167012f, (float16_t)-0.793041960f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.611597164f, (float16_t)-0.791169330f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.614021559f, (float16_t)-0.789289253f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.616440175f, (float16_t)-0.787401747f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.618852988f, (float16_t)-0.785506830f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.621259977f, (float16_t)-0.783604519f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.623661118f, (float16_t)-0.781694832f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.626056388f, (float16_t)-0.779777788f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.628445767f, (float16_t)-0.777853404f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.630829230f, (float16_t)-0.775921699f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.633206755f, (float16_t)-0.773982691f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.635578320f, (float16_t)-0.772036397f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.637943904f, (float16_t)-0.770082837f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.640303482f, (float16_t)-0.768122029f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.642657034f, (float16_t)-0.766153990f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.645004537f, (float16_t)-0.764178741f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.647345969f, (float16_t)-0.762196298f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.649681307f, (float16_t)-0.760206682f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.652010531f, (float16_t)-0.758209910f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.654333618f, (float16_t)-0.756206001f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.656650546f, (float16_t)-0.754194975f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.658961293f, (float16_t)-0.752176850f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.661265838f, (float16_t)-0.750151646f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.663564159f, (float16_t)-0.748119380f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.665856234f, (float16_t)-0.746080074f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.668142041f, (float16_t)-0.744033744f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.670421560f, (float16_t)-0.741980412f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.672694769f, (float16_t)-0.739920095f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.674961646f, (float16_t)-0.737852815f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.677222170f, (float16_t)-0.735778589f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.679476320f, (float16_t)-0.733697438f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.681724074f, (float16_t)-0.731609381f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.683965412f, (float16_t)-0.729514438f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.686200312f, (float16_t)-0.727412629f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.688428753f, (float16_t)-0.725303972f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.690650714f, (float16_t)-0.723188489f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.692866175f, (float16_t)-0.721066199f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.695075114f, (float16_t)-0.718937122f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.697277511f, (float16_t)-0.716801279f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.699473345f, (float16_t)-0.714658688f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.701662595f, (float16_t)-0.712509371f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.703845241f, (float16_t)-0.710353347f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.706021261f, (float16_t)-0.708190637f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.708190637f, (float16_t)-0.706021261f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.710353347f, (float16_t)-0.703845241f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.712509371f, (float16_t)-0.701662595f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.714658688f, (float16_t)-0.699473345f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.716801279f, (float16_t)-0.697277511f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.718937122f, (float16_t)-0.695075114f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.721066199f, (float16_t)-0.692866175f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.723188489f, (float16_t)-0.690650714f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.725303972f, (float16_t)-0.688428753f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.727412629f, (float16_t)-0.686200312f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.729514438f, (float16_t)-0.683965412f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.731609381f, (float16_t)-0.681724074f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.733697438f, (float16_t)-0.679476320f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.735778589f, (float16_t)-0.677222170f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.737852815f, (float16_t)-0.674961646f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.739920095f, (float16_t)-0.672694769f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.741980412f, (float16_t)-0.670421560f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.744033744f, (float16_t)-0.668142041f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.746080074f, (float16_t)-0.665856234f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.748119380f, (float16_t)-0.663564159f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.750151646f, (float16_t)-0.661265838f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.752176850f, (float16_t)-0.658961293f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.754194975f, (float16_t)-0.656650546f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.756206001f, (float16_t)-0.654333618f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.758209910f, (float16_t)-0.652010531f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.760206682f, (float16_t)-0.649681307f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.762196298f, (float16_t)-0.647345969f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.764178741f, (float16_t)-0.645004537f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.766153990f, (float16_t)-0.642657034f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.768122029f, (float16_t)-0.640303482f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.770082837f, (float16_t)-0.637943904f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.772036397f, (float16_t)-0.635578320f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.773982691f, (float16_t)-0.633206755f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.775921699f, (float16_t)-0.630829230f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.777853404f, (float16_t)-0.628445767f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.779777788f, (float16_t)-0.626056388f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.781694832f, (float16_t)-0.623661118f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.783604519f, (float16_t)-0.621259977f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.785506830f, (float16_t)-0.618852988f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.787401747f, (float16_t)-0.616440175f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.789289253f, (float16_t)-0.614021559f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.791169330f, (float16_t)-0.611597164f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.793041960f, (float16_t)-0.609167012f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.794907126f, (float16_t)-0.606731127f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.796764810f, (float16_t)-0.604289531f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.798614995f, (float16_t)-0.601842247f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.800457662f, (float16_t)-0.599389298f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.802292796f, (float16_t)-0.596930708f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.804120377f, (float16_t)-0.594466499f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.805940391f, (float16_t)-0.591996695f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.807752818f, (float16_t)-0.589521319f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.809557642f, (float16_t)-0.587040394f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.811354847f, (float16_t)-0.584553943f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.813144415f, (float16_t)-0.582061990f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.814926329f, (float16_t)-0.579564559f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.816700573f, (float16_t)-0.577061673f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.818467130f, (float16_t)-0.574553355f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.820225983f, (float16_t)-0.572039629f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.821977115f, (float16_t)-0.569520519f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.823720511f, (float16_t)-0.566996049f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.825456154f, (float16_t)-0.564466242f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.827184027f, (float16_t)-0.561931121f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.828904115f, (float16_t)-0.559390712f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.830616400f, (float16_t)-0.556845037f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.832320868f, (float16_t)-0.554294121f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.834017501f, (float16_t)-0.551737988f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.835706284f, (float16_t)-0.549176662f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.837387202f, (float16_t)-0.546610167f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.839060237f, (float16_t)-0.544038527f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.840725375f, (float16_t)-0.541461766f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.842382600f, (float16_t)-0.538879909f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.844031895f, (float16_t)-0.536292979f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.845673247f, (float16_t)-0.533701002f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.847306639f, (float16_t)-0.531104001f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.848932055f, (float16_t)-0.528502002f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.850549481f, (float16_t)-0.525895027f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.852158902f, (float16_t)-0.523283103f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.853760301f, (float16_t)-0.520666254f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.855353665f, (float16_t)-0.518044504f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.856938977f, (float16_t)-0.515417878f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.858516224f, (float16_t)-0.512786401f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.860085390f, (float16_t)-0.510150097f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.861646461f, (float16_t)-0.507508991f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.863199422f, (float16_t)-0.504863109f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.864744258f, (float16_t)-0.502212474f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.866280954f, (float16_t)-0.499557113f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.867809497f, (float16_t)-0.496897049f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.869329871f, (float16_t)-0.494232309f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.870842063f, (float16_t)-0.491562916f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.872346059f, (float16_t)-0.488888897f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.873841843f, (float16_t)-0.486210276f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.875329403f, (float16_t)-0.483527079f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.876808724f, (float16_t)-0.480839331f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.878279792f, (float16_t)-0.478147056f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.879742593f, (float16_t)-0.475450282f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.881197113f, (float16_t)-0.472749032f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.882643340f, (float16_t)-0.470043332f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.884081259f, (float16_t)-0.467333209f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.885510856f, (float16_t)-0.464618686f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.886932119f, (float16_t)-0.461899791f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.888345033f, (float16_t)-0.459176548f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.889749586f, (float16_t)-0.456448982f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.891145765f, (float16_t)-0.453717121f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.892533555f, (float16_t)-0.450980989f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.893912945f, (float16_t)-0.448240612f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.895283921f, (float16_t)-0.445496017f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.896646470f, (float16_t)-0.442747228f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.898000580f, (float16_t)-0.439994271f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.899346237f, (float16_t)-0.437237174f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.900683429f, (float16_t)-0.434475961f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.902012144f, (float16_t)-0.431710658f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.903332368f, (float16_t)-0.428941292f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.904644091f, (float16_t)-0.426167889f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.905947298f, (float16_t)-0.423390474f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.907241978f, (float16_t)-0.420609074f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.908528119f, (float16_t)-0.417823716f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.909805708f, (float16_t)-0.415034424f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.911074734f, (float16_t)-0.412241227f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.912335185f, (float16_t)-0.409444149f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.913587048f, (float16_t)-0.406643217f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.914830312f, (float16_t)-0.403838458f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.916064966f, (float16_t)-0.401029897f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.917290997f, (float16_t)-0.398217562f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.918508394f, (float16_t)-0.395401479f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.919717146f, (float16_t)-0.392581674f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.920917242f, (float16_t)-0.389758174f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.922108669f, (float16_t)-0.386931006f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.923291417f, (float16_t)-0.384100195f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.924465474f, (float16_t)-0.381265769f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.925630831f, (float16_t)-0.378427755f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.926787474f, (float16_t)-0.375586178f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.927935395f, (float16_t)-0.372741067f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.929074581f, (float16_t)-0.369892447f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.930205023f, (float16_t)-0.367040346f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.931326709f, (float16_t)-0.364184790f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.932439629f, (float16_t)-0.361325806f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.933543773f, (float16_t)-0.358463421f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.934639130f, (float16_t)-0.355597662f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.935725689f, (float16_t)-0.352728556f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.936803442f, (float16_t)-0.349856130f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.937872376f, (float16_t)-0.346980411f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.938932484f, (float16_t)-0.344101426f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.939983753f, (float16_t)-0.341219202f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.941026175f, (float16_t)-0.338333767f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.942059740f, (float16_t)-0.335445147f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.943084437f, (float16_t)-0.332553370f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.944100258f, (float16_t)-0.329658463f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.945107193f, (float16_t)-0.326760452f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.946105232f, (float16_t)-0.323859367f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.947094366f, (float16_t)-0.320955232f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.948074586f, (float16_t)-0.318048077f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.949045882f, (float16_t)-0.315137929f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.950008245f, (float16_t)-0.312224814f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.950961666f, (float16_t)-0.309308760f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.951906137f, (float16_t)-0.306389795f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.952841648f, (float16_t)-0.303467947f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.953768190f, (float16_t)-0.300543241f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.954685755f, (float16_t)-0.297615707f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.955594334f, (float16_t)-0.294685372f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.956493919f, (float16_t)-0.291752263f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.957384501f, (float16_t)-0.288816408f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.958266071f, (float16_t)-0.285877835f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.959138622f, (float16_t)-0.282936570f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.960002146f, (float16_t)-0.279992643f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.960856633f, (float16_t)-0.277046080f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.961702077f, (float16_t)-0.274096910f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.962538468f, (float16_t)-0.271145160f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.963365800f, (float16_t)-0.268190857f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.964184064f, (float16_t)-0.265234030f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.964993253f, (float16_t)-0.262274707f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.965793359f, (float16_t)-0.259312915f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.966584374f, (float16_t)-0.256348682f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.967366292f, (float16_t)-0.253382037f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.968139105f, (float16_t)-0.250413007f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.968902805f, (float16_t)-0.247441619f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.969657385f, (float16_t)-0.244467903f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.970402839f, (float16_t)-0.241491885f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.971139158f, (float16_t)-0.238513595f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.971866337f, (float16_t)-0.235533059f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.972584369f, (float16_t)-0.232550307f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.973293246f, (float16_t)-0.229565366f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.973992962f, (float16_t)-0.226578264f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.974683511f, (float16_t)-0.223589029f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.975364885f, (float16_t)-0.220597690f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.976037079f, (float16_t)-0.217604275f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.976700086f, (float16_t)-0.214608811f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.977353900f, (float16_t)-0.211611327f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977998515f, (float16_t)-0.208611852f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.978633924f, (float16_t)-0.205610413f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.979260123f, (float16_t)-0.202607039f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.979877104f, (float16_t)-0.199601758f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.980484862f, (float16_t)-0.196594598f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.981083391f, (float16_t)-0.193585587f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981672686f, (float16_t)-0.190574755f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.982252741f, (float16_t)-0.187562129f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.982823551f, (float16_t)-0.184547737f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.983385110f, (float16_t)-0.181531608f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983937413f, (float16_t)-0.178513771f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.984480455f, (float16_t)-0.175494253f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.985014231f, (float16_t)-0.172473084f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985538735f, (float16_t)-0.169450291f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.986053963f, (float16_t)-0.166425904f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986559910f, (float16_t)-0.163399949f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.987056571f, (float16_t)-0.160372457f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987543942f, (float16_t)-0.157343456f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.988022017f, (float16_t)-0.154312973f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988490793f, (float16_t)-0.151281038f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988950265f, (float16_t)-0.148247679f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.989400428f, (float16_t)-0.145212925f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989841278f, (float16_t)-0.142176804f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.990272812f, (float16_t)-0.139139344f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990695025f, (float16_t)-0.136100575f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.991107914f, (float16_t)-0.133060525f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991511473f, (float16_t)-0.130019223f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991905700f, (float16_t)-0.126976696f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.992290591f, (float16_t)-0.123932975f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992666142f, (float16_t)-0.120888087f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.993032350f, (float16_t)-0.117842062f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993389211f, (float16_t)-0.114794927f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993736722f, (float16_t)-0.111746711f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.994074879f, (float16_t)-0.108697444f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994403680f, (float16_t)-0.105647154f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994723121f, (float16_t)-0.102595869f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.995033199f, (float16_t)-0.099543619f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995333912f, (float16_t)-0.096490431f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995625256f, (float16_t)-0.093436336f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995907229f, (float16_t)-0.090381361f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.996179829f, (float16_t)-0.087325535f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996443051f, (float16_t)-0.084268888f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996696895f, (float16_t)-0.081211447f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996941358f, (float16_t)-0.078153242f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.997176437f, (float16_t)-0.075094301f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997402130f, (float16_t)-0.072034653f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997618435f, (float16_t)-0.068974328f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997825350f, (float16_t)-0.065913353f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.998022874f, (float16_t)-0.062851758f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998211003f, (float16_t)-0.059789571f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998389737f, (float16_t)-0.056726821f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998559074f, (float16_t)-0.053663538f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998719012f, (float16_t)-0.050599749f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998869550f, (float16_t)-0.047535484f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.999010686f, (float16_t)-0.044470772f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999142419f, (float16_t)-0.041405641f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999264747f, (float16_t)-0.038340120f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999377670f, (float16_t)-0.035274239f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999481187f, (float16_t)-0.032208025f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999998823f, (float16_t)-0.001533980f +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32) +/** + @par + Example code for Floating-point RFFT Twiddle factors Generation: + @par + 
TW = exp(pi/2*i-2*pi*i*[0:L/2-1]/L).'
+ @par + Real and Imag values are in interleaved fashion +*/ +const float16_t twiddleCoefF16_rfft_32[32] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.195090322f, (float16_t)-0.980785280f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64) +const float16_t twiddleCoefF16_rfft_64[64] = { + (float16_t)0.000000000000000f, (float16_t)1.000000000000000f, + (float16_t)0.098017140329561f, (float16_t)0.995184726672197f, + (float16_t)0.195090322016128f, (float16_t)0.980785280403230f, + (float16_t)0.290284677254462f, (float16_t)0.956940335732209f, + (float16_t)0.382683432365090f, (float16_t)0.923879532511287f, + (float16_t)0.471396736825998f, (float16_t)0.881921264348355f, + (float16_t)0.555570233019602f, (float16_t)0.831469612302545f, + (float16_t)0.634393284163645f, (float16_t)0.773010453362737f, + (float16_t)0.707106781186547f, (float16_t)0.707106781186548f, + (float16_t)0.773010453362737f, (float16_t)0.634393284163645f, + (float16_t)0.831469612302545f, (float16_t)0.555570233019602f, + (float16_t)0.881921264348355f, (float16_t)0.471396736825998f, + (float16_t)0.923879532511287f, (float16_t)0.382683432365090f, + (float16_t)0.956940335732209f, (float16_t)0.290284677254462f, + (float16_t)0.980785280403230f, (float16_t)0.195090322016128f, + (float16_t)0.995184726672197f, (float16_t)0.098017140329561f, + (float16_t)1.000000000000000f, (float16_t)0.000000000000000f, + (float16_t)0.995184726672197f, (float16_t)-0.098017140329561f, + (float16_t)0.980785280403230f, (float16_t)-0.195090322016128f, + (float16_t)0.956940335732209f, (float16_t)-0.290284677254462f, + (float16_t)0.923879532511287f, (float16_t)-0.382683432365090f, + (float16_t)0.881921264348355f, (float16_t)-0.471396736825998f, + (float16_t)0.831469612302545f, (float16_t)-0.555570233019602f, + (float16_t)0.773010453362737f, (float16_t)-0.634393284163645f, + (float16_t)0.707106781186548f, (float16_t)-0.707106781186547f, + (float16_t)0.634393284163645f, (float16_t)-0.773010453362737f, + (float16_t)0.555570233019602f, (float16_t)-0.831469612302545f, + (float16_t)0.471396736825998f, (float16_t)-0.881921264348355f, + (float16_t)0.382683432365090f, (float16_t)-0.923879532511287f, + (float16_t)0.290284677254462f, (float16_t)-0.956940335732209f, + (float16_t)0.195090322016129f, (float16_t)-0.980785280403230f, + (float16_t)0.098017140329561f, (float16_t)-0.995184726672197f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128) +const float16_t twiddleCoefF16_rfft_128[128] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.049067674f, (float16_t)-0.998795456f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256) +const float16_t twiddleCoefF16_rfft_256[256] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.024541229f, (float16_t)-0.999698819f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512) +const float16_t twiddleCoefF16_rfft_512[512] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.012271538f, (float16_t)-0.999924702f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024) +const float16_t twiddleCoefF16_rfft_1024[1024] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.006135885f, (float16_t)-0.999981175f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048) +const float16_t twiddleCoefF16_rfft_2048[2048] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.003067957f, (float16_t)-0.999995294f +}; +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096) +const float16_t twiddleCoefF16_rfft_4096[4096] = { + (float16_t)0.000000000f, (float16_t)1.000000000f, + (float16_t)0.001533980f, (float16_t)0.999998823f, + (float16_t)0.003067957f, (float16_t)0.999995294f, + (float16_t)0.004601926f, (float16_t)0.999989411f, + (float16_t)0.006135885f, (float16_t)0.999981175f, + (float16_t)0.007669829f, (float16_t)0.999970586f, + (float16_t)0.009203755f, (float16_t)0.999957645f, + (float16_t)0.010737659f, (float16_t)0.999942350f, + (float16_t)0.012271538f, (float16_t)0.999924702f, + (float16_t)0.013805389f, (float16_t)0.999904701f, + (float16_t)0.015339206f, (float16_t)0.999882347f, + (float16_t)0.016872988f, (float16_t)0.999857641f, + (float16_t)0.018406730f, (float16_t)0.999830582f, + (float16_t)0.019940429f, (float16_t)0.999801170f, + (float16_t)0.021474080f, (float16_t)0.999769405f, + (float16_t)0.023007681f, (float16_t)0.999735288f, + (float16_t)0.024541229f, (float16_t)0.999698819f, + (float16_t)0.026074718f, (float16_t)0.999659997f, + (float16_t)0.027608146f, (float16_t)0.999618822f, + (float16_t)0.029141509f, (float16_t)0.999575296f, + (float16_t)0.030674803f, (float16_t)0.999529418f, + (float16_t)0.032208025f, (float16_t)0.999481187f, + (float16_t)0.033741172f, (float16_t)0.999430605f, + (float16_t)0.035274239f, (float16_t)0.999377670f, + (float16_t)0.036807223f, (float16_t)0.999322385f, + (float16_t)0.038340120f, (float16_t)0.999264747f, + (float16_t)0.039872928f, (float16_t)0.999204759f, + (float16_t)0.041405641f, (float16_t)0.999142419f, + (float16_t)0.042938257f, (float16_t)0.999077728f, + (float16_t)0.044470772f, (float16_t)0.999010686f, + (float16_t)0.046003182f, (float16_t)0.998941293f, + (float16_t)0.047535484f, (float16_t)0.998869550f, + (float16_t)0.049067674f, (float16_t)0.998795456f, + (float16_t)0.050599749f, (float16_t)0.998719012f, + (float16_t)0.052131705f, (float16_t)0.998640218f, + (float16_t)0.053663538f, (float16_t)0.998559074f, + (float16_t)0.055195244f, (float16_t)0.998475581f, + (float16_t)0.056726821f, (float16_t)0.998389737f, + (float16_t)0.058258265f, (float16_t)0.998301545f, + (float16_t)0.059789571f, (float16_t)0.998211003f, + (float16_t)0.061320736f, (float16_t)0.998118113f, + (float16_t)0.062851758f, (float16_t)0.998022874f, + (float16_t)0.064382631f, (float16_t)0.997925286f, + (float16_t)0.065913353f, (float16_t)0.997825350f, + (float16_t)0.067443920f, (float16_t)0.997723067f, + (float16_t)0.068974328f, (float16_t)0.997618435f, + (float16_t)0.070504573f, (float16_t)0.997511456f, + (float16_t)0.072034653f, (float16_t)0.997402130f, + (float16_t)0.073564564f, (float16_t)0.997290457f, + (float16_t)0.075094301f, (float16_t)0.997176437f, + (float16_t)0.076623861f, (float16_t)0.997060070f, + (float16_t)0.078153242f, (float16_t)0.996941358f, + (float16_t)0.079682438f, (float16_t)0.996820299f, + (float16_t)0.081211447f, (float16_t)0.996696895f, + (float16_t)0.082740265f, (float16_t)0.996571146f, + (float16_t)0.084268888f, (float16_t)0.996443051f, + (float16_t)0.085797312f, (float16_t)0.996312612f, + (float16_t)0.087325535f, (float16_t)0.996179829f, + (float16_t)0.088853553f, (float16_t)0.996044701f, + (float16_t)0.090381361f, (float16_t)0.995907229f, + (float16_t)0.091908956f, (float16_t)0.995767414f, + (float16_t)0.093436336f, (float16_t)0.995625256f, + (float16_t)0.094963495f, (float16_t)0.995480755f, + (float16_t)0.096490431f, (float16_t)0.995333912f, + (float16_t)0.098017140f, (float16_t)0.995184727f, + (float16_t)0.099543619f, (float16_t)0.995033199f, + (float16_t)0.101069863f, (float16_t)0.994879331f, + (float16_t)0.102595869f, (float16_t)0.994723121f, + (float16_t)0.104121634f, (float16_t)0.994564571f, + (float16_t)0.105647154f, (float16_t)0.994403680f, + (float16_t)0.107172425f, (float16_t)0.994240449f, + (float16_t)0.108697444f, (float16_t)0.994074879f, + (float16_t)0.110222207f, (float16_t)0.993906970f, + (float16_t)0.111746711f, (float16_t)0.993736722f, + (float16_t)0.113270952f, (float16_t)0.993564136f, + (float16_t)0.114794927f, (float16_t)0.993389211f, + (float16_t)0.116318631f, (float16_t)0.993211949f, + (float16_t)0.117842062f, (float16_t)0.993032350f, + (float16_t)0.119365215f, (float16_t)0.992850414f, + (float16_t)0.120888087f, (float16_t)0.992666142f, + (float16_t)0.122410675f, (float16_t)0.992479535f, + (float16_t)0.123932975f, (float16_t)0.992290591f, + (float16_t)0.125454983f, (float16_t)0.992099313f, + (float16_t)0.126976696f, (float16_t)0.991905700f, + (float16_t)0.128498111f, (float16_t)0.991709754f, + (float16_t)0.130019223f, (float16_t)0.991511473f, + (float16_t)0.131540029f, (float16_t)0.991310860f, + (float16_t)0.133060525f, (float16_t)0.991107914f, + (float16_t)0.134580709f, (float16_t)0.990902635f, + (float16_t)0.136100575f, (float16_t)0.990695025f, + (float16_t)0.137620122f, (float16_t)0.990485084f, + (float16_t)0.139139344f, (float16_t)0.990272812f, + (float16_t)0.140658239f, (float16_t)0.990058210f, + (float16_t)0.142176804f, (float16_t)0.989841278f, + (float16_t)0.143695033f, (float16_t)0.989622017f, + (float16_t)0.145212925f, (float16_t)0.989400428f, + (float16_t)0.146730474f, (float16_t)0.989176510f, + (float16_t)0.148247679f, (float16_t)0.988950265f, + (float16_t)0.149764535f, (float16_t)0.988721692f, + (float16_t)0.151281038f, (float16_t)0.988490793f, + (float16_t)0.152797185f, (float16_t)0.988257568f, + (float16_t)0.154312973f, (float16_t)0.988022017f, + (float16_t)0.155828398f, (float16_t)0.987784142f, + (float16_t)0.157343456f, (float16_t)0.987543942f, + (float16_t)0.158858143f, (float16_t)0.987301418f, + (float16_t)0.160372457f, (float16_t)0.987056571f, + (float16_t)0.161886394f, (float16_t)0.986809402f, + (float16_t)0.163399949f, (float16_t)0.986559910f, + (float16_t)0.164913120f, (float16_t)0.986308097f, + (float16_t)0.166425904f, (float16_t)0.986053963f, + (float16_t)0.167938295f, (float16_t)0.985797509f, + (float16_t)0.169450291f, (float16_t)0.985538735f, + (float16_t)0.170961889f, (float16_t)0.985277642f, + (float16_t)0.172473084f, (float16_t)0.985014231f, + (float16_t)0.173983873f, (float16_t)0.984748502f, + (float16_t)0.175494253f, (float16_t)0.984480455f, + (float16_t)0.177004220f, (float16_t)0.984210092f, + (float16_t)0.178513771f, (float16_t)0.983937413f, + (float16_t)0.180022901f, (float16_t)0.983662419f, + (float16_t)0.181531608f, (float16_t)0.983385110f, + (float16_t)0.183039888f, (float16_t)0.983105487f, + (float16_t)0.184547737f, (float16_t)0.982823551f, + (float16_t)0.186055152f, (float16_t)0.982539302f, + (float16_t)0.187562129f, (float16_t)0.982252741f, + (float16_t)0.189068664f, (float16_t)0.981963869f, + (float16_t)0.190574755f, (float16_t)0.981672686f, + (float16_t)0.192080397f, (float16_t)0.981379193f, + (float16_t)0.193585587f, (float16_t)0.981083391f, + (float16_t)0.195090322f, (float16_t)0.980785280f, + (float16_t)0.196594598f, (float16_t)0.980484862f, + (float16_t)0.198098411f, (float16_t)0.980182136f, + (float16_t)0.199601758f, (float16_t)0.979877104f, + (float16_t)0.201104635f, (float16_t)0.979569766f, + (float16_t)0.202607039f, (float16_t)0.979260123f, + (float16_t)0.204108966f, (float16_t)0.978948175f, + (float16_t)0.205610413f, (float16_t)0.978633924f, + (float16_t)0.207111376f, (float16_t)0.978317371f, + (float16_t)0.208611852f, (float16_t)0.977998515f, + (float16_t)0.210111837f, (float16_t)0.977677358f, + (float16_t)0.211611327f, (float16_t)0.977353900f, + (float16_t)0.213110320f, (float16_t)0.977028143f, + (float16_t)0.214608811f, (float16_t)0.976700086f, + (float16_t)0.216106797f, (float16_t)0.976369731f, + (float16_t)0.217604275f, (float16_t)0.976037079f, + (float16_t)0.219101240f, (float16_t)0.975702130f, + (float16_t)0.220597690f, (float16_t)0.975364885f, + (float16_t)0.222093621f, (float16_t)0.975025345f, + (float16_t)0.223589029f, (float16_t)0.974683511f, + (float16_t)0.225083911f, (float16_t)0.974339383f, + (float16_t)0.226578264f, (float16_t)0.973992962f, + (float16_t)0.228072083f, (float16_t)0.973644250f, + (float16_t)0.229565366f, (float16_t)0.973293246f, + (float16_t)0.231058108f, (float16_t)0.972939952f, + (float16_t)0.232550307f, (float16_t)0.972584369f, + (float16_t)0.234041959f, (float16_t)0.972226497f, + (float16_t)0.235533059f, (float16_t)0.971866337f, + (float16_t)0.237023606f, (float16_t)0.971503891f, + (float16_t)0.238513595f, (float16_t)0.971139158f, + (float16_t)0.240003022f, (float16_t)0.970772141f, + (float16_t)0.241491885f, (float16_t)0.970402839f, + (float16_t)0.242980180f, (float16_t)0.970031253f, + (float16_t)0.244467903f, (float16_t)0.969657385f, + (float16_t)0.245955050f, (float16_t)0.969281235f, + (float16_t)0.247441619f, (float16_t)0.968902805f, + (float16_t)0.248927606f, (float16_t)0.968522094f, + (float16_t)0.250413007f, (float16_t)0.968139105f, + (float16_t)0.251897818f, (float16_t)0.967753837f, + (float16_t)0.253382037f, (float16_t)0.967366292f, + (float16_t)0.254865660f, (float16_t)0.966976471f, + (float16_t)0.256348682f, (float16_t)0.966584374f, + (float16_t)0.257831102f, (float16_t)0.966190003f, + (float16_t)0.259312915f, (float16_t)0.965793359f, + (float16_t)0.260794118f, (float16_t)0.965394442f, + (float16_t)0.262274707f, (float16_t)0.964993253f, + (float16_t)0.263754679f, (float16_t)0.964589793f, + (float16_t)0.265234030f, (float16_t)0.964184064f, + (float16_t)0.266712757f, (float16_t)0.963776066f, + (float16_t)0.268190857f, (float16_t)0.963365800f, + (float16_t)0.269668326f, (float16_t)0.962953267f, + (float16_t)0.271145160f, (float16_t)0.962538468f, + (float16_t)0.272621355f, (float16_t)0.962121404f, + (float16_t)0.274096910f, (float16_t)0.961702077f, + (float16_t)0.275571819f, (float16_t)0.961280486f, + (float16_t)0.277046080f, (float16_t)0.960856633f, + (float16_t)0.278519689f, (float16_t)0.960430519f, + (float16_t)0.279992643f, (float16_t)0.960002146f, + (float16_t)0.281464938f, (float16_t)0.959571513f, + (float16_t)0.282936570f, (float16_t)0.959138622f, + (float16_t)0.284407537f, (float16_t)0.958703475f, + (float16_t)0.285877835f, (float16_t)0.958266071f, + (float16_t)0.287347460f, (float16_t)0.957826413f, + (float16_t)0.288816408f, (float16_t)0.957384501f, + (float16_t)0.290284677f, (float16_t)0.956940336f, + (float16_t)0.291752263f, (float16_t)0.956493919f, + (float16_t)0.293219163f, (float16_t)0.956045251f, + (float16_t)0.294685372f, (float16_t)0.955594334f, + (float16_t)0.296150888f, (float16_t)0.955141168f, + (float16_t)0.297615707f, (float16_t)0.954685755f, + (float16_t)0.299079826f, (float16_t)0.954228095f, + (float16_t)0.300543241f, (float16_t)0.953768190f, + (float16_t)0.302005949f, (float16_t)0.953306040f, + (float16_t)0.303467947f, (float16_t)0.952841648f, + (float16_t)0.304929230f, (float16_t)0.952375013f, + (float16_t)0.306389795f, (float16_t)0.951906137f, + (float16_t)0.307849640f, (float16_t)0.951435021f, + (float16_t)0.309308760f, (float16_t)0.950961666f, + (float16_t)0.310767153f, (float16_t)0.950486074f, + (float16_t)0.312224814f, (float16_t)0.950008245f, + (float16_t)0.313681740f, (float16_t)0.949528181f, + (float16_t)0.315137929f, (float16_t)0.949045882f, + (float16_t)0.316593376f, (float16_t)0.948561350f, + (float16_t)0.318048077f, (float16_t)0.948074586f, + (float16_t)0.319502031f, (float16_t)0.947585591f, + (float16_t)0.320955232f, (float16_t)0.947094366f, + (float16_t)0.322407679f, (float16_t)0.946600913f, + (float16_t)0.323859367f, (float16_t)0.946105232f, + (float16_t)0.325310292f, (float16_t)0.945607325f, + (float16_t)0.326760452f, (float16_t)0.945107193f, + (float16_t)0.328209844f, (float16_t)0.944604837f, + (float16_t)0.329658463f, (float16_t)0.944100258f, + (float16_t)0.331106306f, (float16_t)0.943593458f, + (float16_t)0.332553370f, (float16_t)0.943084437f, + (float16_t)0.333999651f, (float16_t)0.942573198f, + (float16_t)0.335445147f, (float16_t)0.942059740f, + (float16_t)0.336889853f, (float16_t)0.941544065f, + (float16_t)0.338333767f, (float16_t)0.941026175f, + (float16_t)0.339776884f, (float16_t)0.940506071f, + (float16_t)0.341219202f, (float16_t)0.939983753f, + (float16_t)0.342660717f, (float16_t)0.939459224f, + (float16_t)0.344101426f, (float16_t)0.938932484f, + (float16_t)0.345541325f, (float16_t)0.938403534f, + (float16_t)0.346980411f, (float16_t)0.937872376f, + (float16_t)0.348418680f, (float16_t)0.937339012f, + (float16_t)0.349856130f, (float16_t)0.936803442f, + (float16_t)0.351292756f, (float16_t)0.936265667f, + (float16_t)0.352728556f, (float16_t)0.935725689f, + (float16_t)0.354163525f, (float16_t)0.935183510f, + (float16_t)0.355597662f, (float16_t)0.934639130f, + (float16_t)0.357030961f, (float16_t)0.934092550f, + (float16_t)0.358463421f, (float16_t)0.933543773f, + (float16_t)0.359895037f, (float16_t)0.932992799f, + (float16_t)0.361325806f, (float16_t)0.932439629f, + (float16_t)0.362755724f, (float16_t)0.931884266f, + (float16_t)0.364184790f, (float16_t)0.931326709f, + (float16_t)0.365612998f, (float16_t)0.930766961f, + (float16_t)0.367040346f, (float16_t)0.930205023f, + (float16_t)0.368466830f, (float16_t)0.929640896f, + (float16_t)0.369892447f, (float16_t)0.929074581f, + (float16_t)0.371317194f, (float16_t)0.928506080f, + (float16_t)0.372741067f, (float16_t)0.927935395f, + (float16_t)0.374164063f, (float16_t)0.927362526f, + (float16_t)0.375586178f, (float16_t)0.926787474f, + (float16_t)0.377007410f, (float16_t)0.926210242f, + (float16_t)0.378427755f, (float16_t)0.925630831f, + (float16_t)0.379847209f, (float16_t)0.925049241f, + (float16_t)0.381265769f, (float16_t)0.924465474f, + (float16_t)0.382683432f, (float16_t)0.923879533f, + (float16_t)0.384100195f, (float16_t)0.923291417f, + (float16_t)0.385516054f, (float16_t)0.922701128f, + (float16_t)0.386931006f, (float16_t)0.922108669f, + (float16_t)0.388345047f, (float16_t)0.921514039f, + (float16_t)0.389758174f, (float16_t)0.920917242f, + (float16_t)0.391170384f, (float16_t)0.920318277f, + (float16_t)0.392581674f, (float16_t)0.919717146f, + (float16_t)0.393992040f, (float16_t)0.919113852f, + (float16_t)0.395401479f, (float16_t)0.918508394f, + (float16_t)0.396809987f, (float16_t)0.917900776f, + (float16_t)0.398217562f, (float16_t)0.917290997f, + (float16_t)0.399624200f, (float16_t)0.916679060f, + (float16_t)0.401029897f, (float16_t)0.916064966f, + (float16_t)0.402434651f, (float16_t)0.915448716f, + (float16_t)0.403838458f, (float16_t)0.914830312f, + (float16_t)0.405241314f, (float16_t)0.914209756f, + (float16_t)0.406643217f, (float16_t)0.913587048f, + (float16_t)0.408044163f, (float16_t)0.912962190f, + (float16_t)0.409444149f, (float16_t)0.912335185f, + (float16_t)0.410843171f, (float16_t)0.911706032f, + (float16_t)0.412241227f, (float16_t)0.911074734f, + (float16_t)0.413638312f, (float16_t)0.910441292f, + (float16_t)0.415034424f, (float16_t)0.909805708f, + (float16_t)0.416429560f, (float16_t)0.909167983f, + (float16_t)0.417823716f, (float16_t)0.908528119f, + (float16_t)0.419216888f, (float16_t)0.907886116f, + (float16_t)0.420609074f, (float16_t)0.907241978f, + (float16_t)0.422000271f, (float16_t)0.906595705f, + (float16_t)0.423390474f, (float16_t)0.905947298f, + (float16_t)0.424779681f, (float16_t)0.905296759f, + (float16_t)0.426167889f, (float16_t)0.904644091f, + (float16_t)0.427555093f, (float16_t)0.903989293f, + (float16_t)0.428941292f, (float16_t)0.903332368f, + (float16_t)0.430326481f, (float16_t)0.902673318f, + (float16_t)0.431710658f, (float16_t)0.902012144f, + (float16_t)0.433093819f, (float16_t)0.901348847f, + (float16_t)0.434475961f, (float16_t)0.900683429f, + (float16_t)0.435857080f, (float16_t)0.900015892f, + (float16_t)0.437237174f, (float16_t)0.899346237f, + (float16_t)0.438616239f, (float16_t)0.898674466f, + (float16_t)0.439994271f, (float16_t)0.898000580f, + (float16_t)0.441371269f, (float16_t)0.897324581f, + (float16_t)0.442747228f, (float16_t)0.896646470f, + (float16_t)0.444122145f, (float16_t)0.895966250f, + (float16_t)0.445496017f, (float16_t)0.895283921f, + (float16_t)0.446868840f, (float16_t)0.894599486f, + (float16_t)0.448240612f, (float16_t)0.893912945f, + (float16_t)0.449611330f, (float16_t)0.893224301f, + (float16_t)0.450980989f, (float16_t)0.892533555f, + (float16_t)0.452349587f, (float16_t)0.891840709f, + (float16_t)0.453717121f, (float16_t)0.891145765f, + (float16_t)0.455083587f, (float16_t)0.890448723f, + (float16_t)0.456448982f, (float16_t)0.889749586f, + (float16_t)0.457813304f, (float16_t)0.889048356f, + (float16_t)0.459176548f, (float16_t)0.888345033f, + (float16_t)0.460538711f, (float16_t)0.887639620f, + (float16_t)0.461899791f, (float16_t)0.886932119f, + (float16_t)0.463259784f, (float16_t)0.886222530f, + (float16_t)0.464618686f, (float16_t)0.885510856f, + (float16_t)0.465976496f, (float16_t)0.884797098f, + (float16_t)0.467333209f, (float16_t)0.884081259f, + (float16_t)0.468688822f, (float16_t)0.883363339f, + (float16_t)0.470043332f, (float16_t)0.882643340f, + (float16_t)0.471396737f, (float16_t)0.881921264f, + (float16_t)0.472749032f, (float16_t)0.881197113f, + (float16_t)0.474100215f, (float16_t)0.880470889f, + (float16_t)0.475450282f, (float16_t)0.879742593f, + (float16_t)0.476799230f, (float16_t)0.879012226f, + (float16_t)0.478147056f, (float16_t)0.878279792f, + (float16_t)0.479493758f, (float16_t)0.877545290f, + (float16_t)0.480839331f, (float16_t)0.876808724f, + (float16_t)0.482183772f, (float16_t)0.876070094f, + (float16_t)0.483527079f, (float16_t)0.875329403f, + (float16_t)0.484869248f, (float16_t)0.874586652f, + (float16_t)0.486210276f, (float16_t)0.873841843f, + (float16_t)0.487550160f, (float16_t)0.873094978f, + (float16_t)0.488888897f, (float16_t)0.872346059f, + (float16_t)0.490226483f, (float16_t)0.871595087f, + (float16_t)0.491562916f, (float16_t)0.870842063f, + (float16_t)0.492898192f, (float16_t)0.870086991f, + (float16_t)0.494232309f, (float16_t)0.869329871f, + (float16_t)0.495565262f, (float16_t)0.868570706f, + (float16_t)0.496897049f, (float16_t)0.867809497f, + (float16_t)0.498227667f, (float16_t)0.867046246f, + (float16_t)0.499557113f, (float16_t)0.866280954f, + (float16_t)0.500885383f, (float16_t)0.865513624f, + (float16_t)0.502212474f, (float16_t)0.864744258f, + (float16_t)0.503538384f, (float16_t)0.863972856f, + (float16_t)0.504863109f, (float16_t)0.863199422f, + (float16_t)0.506186645f, (float16_t)0.862423956f, + (float16_t)0.507508991f, (float16_t)0.861646461f, + (float16_t)0.508830143f, (float16_t)0.860866939f, + (float16_t)0.510150097f, (float16_t)0.860085390f, + (float16_t)0.511468850f, (float16_t)0.859301818f, + (float16_t)0.512786401f, (float16_t)0.858516224f, + (float16_t)0.514102744f, (float16_t)0.857728610f, + (float16_t)0.515417878f, (float16_t)0.856938977f, + (float16_t)0.516731799f, (float16_t)0.856147328f, + (float16_t)0.518044504f, (float16_t)0.855353665f, + (float16_t)0.519355990f, (float16_t)0.854557988f, + (float16_t)0.520666254f, (float16_t)0.853760301f, + (float16_t)0.521975293f, (float16_t)0.852960605f, + (float16_t)0.523283103f, (float16_t)0.852158902f, + (float16_t)0.524589683f, (float16_t)0.851355193f, + (float16_t)0.525895027f, (float16_t)0.850549481f, + (float16_t)0.527199135f, (float16_t)0.849741768f, + (float16_t)0.528502002f, (float16_t)0.848932055f, + (float16_t)0.529803625f, (float16_t)0.848120345f, + (float16_t)0.531104001f, (float16_t)0.847306639f, + (float16_t)0.532403128f, (float16_t)0.846490939f, + (float16_t)0.533701002f, (float16_t)0.845673247f, + (float16_t)0.534997620f, (float16_t)0.844853565f, + (float16_t)0.536292979f, (float16_t)0.844031895f, + (float16_t)0.537587076f, (float16_t)0.843208240f, + (float16_t)0.538879909f, (float16_t)0.842382600f, + (float16_t)0.540171473f, (float16_t)0.841554977f, + (float16_t)0.541461766f, (float16_t)0.840725375f, + (float16_t)0.542750785f, (float16_t)0.839893794f, + (float16_t)0.544038527f, (float16_t)0.839060237f, + (float16_t)0.545324988f, (float16_t)0.838224706f, + (float16_t)0.546610167f, (float16_t)0.837387202f, + (float16_t)0.547894059f, (float16_t)0.836547727f, + (float16_t)0.549176662f, (float16_t)0.835706284f, + (float16_t)0.550457973f, (float16_t)0.834862875f, + (float16_t)0.551737988f, (float16_t)0.834017501f, + (float16_t)0.553016706f, (float16_t)0.833170165f, + (float16_t)0.554294121f, (float16_t)0.832320868f, + (float16_t)0.555570233f, (float16_t)0.831469612f, + (float16_t)0.556845037f, (float16_t)0.830616400f, + (float16_t)0.558118531f, (float16_t)0.829761234f, + (float16_t)0.559390712f, (float16_t)0.828904115f, + (float16_t)0.560661576f, (float16_t)0.828045045f, + (float16_t)0.561931121f, (float16_t)0.827184027f, + (float16_t)0.563199344f, (float16_t)0.826321063f, + (float16_t)0.564466242f, (float16_t)0.825456154f, + (float16_t)0.565731811f, (float16_t)0.824589303f, + (float16_t)0.566996049f, (float16_t)0.823720511f, + (float16_t)0.568258953f, (float16_t)0.822849781f, + (float16_t)0.569520519f, (float16_t)0.821977115f, + (float16_t)0.570780746f, (float16_t)0.821102515f, + (float16_t)0.572039629f, (float16_t)0.820225983f, + (float16_t)0.573297167f, (float16_t)0.819347520f, + (float16_t)0.574553355f, (float16_t)0.818467130f, + (float16_t)0.575808191f, (float16_t)0.817584813f, + (float16_t)0.577061673f, (float16_t)0.816700573f, + (float16_t)0.578313796f, (float16_t)0.815814411f, + (float16_t)0.579564559f, (float16_t)0.814926329f, + (float16_t)0.580813958f, (float16_t)0.814036330f, + (float16_t)0.582061990f, (float16_t)0.813144415f, + (float16_t)0.583308653f, (float16_t)0.812250587f, + (float16_t)0.584553943f, (float16_t)0.811354847f, + (float16_t)0.585797857f, (float16_t)0.810457198f, + (float16_t)0.587040394f, (float16_t)0.809557642f, + (float16_t)0.588281548f, (float16_t)0.808656182f, + (float16_t)0.589521319f, (float16_t)0.807752818f, + (float16_t)0.590759702f, (float16_t)0.806847554f, + (float16_t)0.591996695f, (float16_t)0.805940391f, + (float16_t)0.593232295f, (float16_t)0.805031331f, + (float16_t)0.594466499f, (float16_t)0.804120377f, + (float16_t)0.595699304f, (float16_t)0.803207531f, + (float16_t)0.596930708f, (float16_t)0.802292796f, + (float16_t)0.598160707f, (float16_t)0.801376172f, + (float16_t)0.599389298f, (float16_t)0.800457662f, + (float16_t)0.600616479f, (float16_t)0.799537269f, + (float16_t)0.601842247f, (float16_t)0.798614995f, + (float16_t)0.603066599f, (float16_t)0.797690841f, + (float16_t)0.604289531f, (float16_t)0.796764810f, + (float16_t)0.605511041f, (float16_t)0.795836905f, + (float16_t)0.606731127f, (float16_t)0.794907126f, + (float16_t)0.607949785f, (float16_t)0.793975478f, + (float16_t)0.609167012f, (float16_t)0.793041960f, + (float16_t)0.610382806f, (float16_t)0.792106577f, + (float16_t)0.611597164f, (float16_t)0.791169330f, + (float16_t)0.612810082f, (float16_t)0.790230221f, + (float16_t)0.614021559f, (float16_t)0.789289253f, + (float16_t)0.615231591f, (float16_t)0.788346428f, + (float16_t)0.616440175f, (float16_t)0.787401747f, + (float16_t)0.617647308f, (float16_t)0.786455214f, + (float16_t)0.618852988f, (float16_t)0.785506830f, + (float16_t)0.620057212f, (float16_t)0.784556597f, + (float16_t)0.621259977f, (float16_t)0.783604519f, + (float16_t)0.622461279f, (float16_t)0.782650596f, + (float16_t)0.623661118f, (float16_t)0.781694832f, + (float16_t)0.624859488f, (float16_t)0.780737229f, + (float16_t)0.626056388f, (float16_t)0.779777788f, + (float16_t)0.627251815f, (float16_t)0.778816512f, + (float16_t)0.628445767f, (float16_t)0.777853404f, + (float16_t)0.629638239f, (float16_t)0.776888466f, + (float16_t)0.630829230f, (float16_t)0.775921699f, + (float16_t)0.632018736f, (float16_t)0.774953107f, + (float16_t)0.633206755f, (float16_t)0.773982691f, + (float16_t)0.634393284f, (float16_t)0.773010453f, + (float16_t)0.635578320f, (float16_t)0.772036397f, + (float16_t)0.636761861f, (float16_t)0.771060524f, + (float16_t)0.637943904f, (float16_t)0.770082837f, + (float16_t)0.639124445f, (float16_t)0.769103338f, + (float16_t)0.640303482f, (float16_t)0.768122029f, + (float16_t)0.641481013f, (float16_t)0.767138912f, + (float16_t)0.642657034f, (float16_t)0.766153990f, + (float16_t)0.643831543f, (float16_t)0.765167266f, + (float16_t)0.645004537f, (float16_t)0.764178741f, + (float16_t)0.646176013f, (float16_t)0.763188417f, + (float16_t)0.647345969f, (float16_t)0.762196298f, + (float16_t)0.648514401f, (float16_t)0.761202385f, + (float16_t)0.649681307f, (float16_t)0.760206682f, + (float16_t)0.650846685f, (float16_t)0.759209189f, + (float16_t)0.652010531f, (float16_t)0.758209910f, + (float16_t)0.653172843f, (float16_t)0.757208847f, + (float16_t)0.654333618f, (float16_t)0.756206001f, + (float16_t)0.655492853f, (float16_t)0.755201377f, + (float16_t)0.656650546f, (float16_t)0.754194975f, + (float16_t)0.657806693f, (float16_t)0.753186799f, + (float16_t)0.658961293f, (float16_t)0.752176850f, + (float16_t)0.660114342f, (float16_t)0.751165132f, + (float16_t)0.661265838f, (float16_t)0.750151646f, + (float16_t)0.662415778f, (float16_t)0.749136395f, + (float16_t)0.663564159f, (float16_t)0.748119380f, + (float16_t)0.664710978f, (float16_t)0.747100606f, + (float16_t)0.665856234f, (float16_t)0.746080074f, + (float16_t)0.666999922f, (float16_t)0.745057785f, + (float16_t)0.668142041f, (float16_t)0.744033744f, + (float16_t)0.669282588f, (float16_t)0.743007952f, + (float16_t)0.670421560f, (float16_t)0.741980412f, + (float16_t)0.671558955f, (float16_t)0.740951125f, + (float16_t)0.672694769f, (float16_t)0.739920095f, + (float16_t)0.673829000f, (float16_t)0.738887324f, + (float16_t)0.674961646f, (float16_t)0.737852815f, + (float16_t)0.676092704f, (float16_t)0.736816569f, + (float16_t)0.677222170f, (float16_t)0.735778589f, + (float16_t)0.678350043f, (float16_t)0.734738878f, + (float16_t)0.679476320f, (float16_t)0.733697438f, + (float16_t)0.680600998f, (float16_t)0.732654272f, + (float16_t)0.681724074f, (float16_t)0.731609381f, + (float16_t)0.682845546f, (float16_t)0.730562769f, + (float16_t)0.683965412f, (float16_t)0.729514438f, + (float16_t)0.685083668f, (float16_t)0.728464390f, + (float16_t)0.686200312f, (float16_t)0.727412629f, + (float16_t)0.687315341f, (float16_t)0.726359155f, + (float16_t)0.688428753f, (float16_t)0.725303972f, + (float16_t)0.689540545f, (float16_t)0.724247083f, + (float16_t)0.690650714f, (float16_t)0.723188489f, + (float16_t)0.691759258f, (float16_t)0.722128194f, + (float16_t)0.692866175f, (float16_t)0.721066199f, + (float16_t)0.693971461f, (float16_t)0.720002508f, + (float16_t)0.695075114f, (float16_t)0.718937122f, + (float16_t)0.696177131f, (float16_t)0.717870045f, + (float16_t)0.697277511f, (float16_t)0.716801279f, + (float16_t)0.698376249f, (float16_t)0.715730825f, + (float16_t)0.699473345f, (float16_t)0.714658688f, + (float16_t)0.700568794f, (float16_t)0.713584869f, + (float16_t)0.701662595f, (float16_t)0.712509371f, + (float16_t)0.702754744f, (float16_t)0.711432196f, + (float16_t)0.703845241f, (float16_t)0.710353347f, + (float16_t)0.704934080f, (float16_t)0.709272826f, + (float16_t)0.706021261f, (float16_t)0.708190637f, + (float16_t)0.707106781f, (float16_t)0.707106781f, + (float16_t)0.708190637f, (float16_t)0.706021261f, + (float16_t)0.709272826f, (float16_t)0.704934080f, + (float16_t)0.710353347f, (float16_t)0.703845241f, + (float16_t)0.711432196f, (float16_t)0.702754744f, + (float16_t)0.712509371f, (float16_t)0.701662595f, + (float16_t)0.713584869f, (float16_t)0.700568794f, + (float16_t)0.714658688f, (float16_t)0.699473345f, + (float16_t)0.715730825f, (float16_t)0.698376249f, + (float16_t)0.716801279f, (float16_t)0.697277511f, + (float16_t)0.717870045f, (float16_t)0.696177131f, + (float16_t)0.718937122f, (float16_t)0.695075114f, + (float16_t)0.720002508f, (float16_t)0.693971461f, + (float16_t)0.721066199f, (float16_t)0.692866175f, + (float16_t)0.722128194f, (float16_t)0.691759258f, + (float16_t)0.723188489f, (float16_t)0.690650714f, + (float16_t)0.724247083f, (float16_t)0.689540545f, + (float16_t)0.725303972f, (float16_t)0.688428753f, + (float16_t)0.726359155f, (float16_t)0.687315341f, + (float16_t)0.727412629f, (float16_t)0.686200312f, + (float16_t)0.728464390f, (float16_t)0.685083668f, + (float16_t)0.729514438f, (float16_t)0.683965412f, + (float16_t)0.730562769f, (float16_t)0.682845546f, + (float16_t)0.731609381f, (float16_t)0.681724074f, + (float16_t)0.732654272f, (float16_t)0.680600998f, + (float16_t)0.733697438f, (float16_t)0.679476320f, + (float16_t)0.734738878f, (float16_t)0.678350043f, + (float16_t)0.735778589f, (float16_t)0.677222170f, + (float16_t)0.736816569f, (float16_t)0.676092704f, + (float16_t)0.737852815f, (float16_t)0.674961646f, + (float16_t)0.738887324f, (float16_t)0.673829000f, + (float16_t)0.739920095f, (float16_t)0.672694769f, + (float16_t)0.740951125f, (float16_t)0.671558955f, + (float16_t)0.741980412f, (float16_t)0.670421560f, + (float16_t)0.743007952f, (float16_t)0.669282588f, + (float16_t)0.744033744f, (float16_t)0.668142041f, + (float16_t)0.745057785f, (float16_t)0.666999922f, + (float16_t)0.746080074f, (float16_t)0.665856234f, + (float16_t)0.747100606f, (float16_t)0.664710978f, + (float16_t)0.748119380f, (float16_t)0.663564159f, + (float16_t)0.749136395f, (float16_t)0.662415778f, + (float16_t)0.750151646f, (float16_t)0.661265838f, + (float16_t)0.751165132f, (float16_t)0.660114342f, + (float16_t)0.752176850f, (float16_t)0.658961293f, + (float16_t)0.753186799f, (float16_t)0.657806693f, + (float16_t)0.754194975f, (float16_t)0.656650546f, + (float16_t)0.755201377f, (float16_t)0.655492853f, + (float16_t)0.756206001f, (float16_t)0.654333618f, + (float16_t)0.757208847f, (float16_t)0.653172843f, + (float16_t)0.758209910f, (float16_t)0.652010531f, + (float16_t)0.759209189f, (float16_t)0.650846685f, + (float16_t)0.760206682f, (float16_t)0.649681307f, + (float16_t)0.761202385f, (float16_t)0.648514401f, + (float16_t)0.762196298f, (float16_t)0.647345969f, + (float16_t)0.763188417f, (float16_t)0.646176013f, + (float16_t)0.764178741f, (float16_t)0.645004537f, + (float16_t)0.765167266f, (float16_t)0.643831543f, + (float16_t)0.766153990f, (float16_t)0.642657034f, + (float16_t)0.767138912f, (float16_t)0.641481013f, + (float16_t)0.768122029f, (float16_t)0.640303482f, + (float16_t)0.769103338f, (float16_t)0.639124445f, + (float16_t)0.770082837f, (float16_t)0.637943904f, + (float16_t)0.771060524f, (float16_t)0.636761861f, + (float16_t)0.772036397f, (float16_t)0.635578320f, + (float16_t)0.773010453f, (float16_t)0.634393284f, + (float16_t)0.773982691f, (float16_t)0.633206755f, + (float16_t)0.774953107f, (float16_t)0.632018736f, + (float16_t)0.775921699f, (float16_t)0.630829230f, + (float16_t)0.776888466f, (float16_t)0.629638239f, + (float16_t)0.777853404f, (float16_t)0.628445767f, + (float16_t)0.778816512f, (float16_t)0.627251815f, + (float16_t)0.779777788f, (float16_t)0.626056388f, + (float16_t)0.780737229f, (float16_t)0.624859488f, + (float16_t)0.781694832f, (float16_t)0.623661118f, + (float16_t)0.782650596f, (float16_t)0.622461279f, + (float16_t)0.783604519f, (float16_t)0.621259977f, + (float16_t)0.784556597f, (float16_t)0.620057212f, + (float16_t)0.785506830f, (float16_t)0.618852988f, + (float16_t)0.786455214f, (float16_t)0.617647308f, + (float16_t)0.787401747f, (float16_t)0.616440175f, + (float16_t)0.788346428f, (float16_t)0.615231591f, + (float16_t)0.789289253f, (float16_t)0.614021559f, + (float16_t)0.790230221f, (float16_t)0.612810082f, + (float16_t)0.791169330f, (float16_t)0.611597164f, + (float16_t)0.792106577f, (float16_t)0.610382806f, + (float16_t)0.793041960f, (float16_t)0.609167012f, + (float16_t)0.793975478f, (float16_t)0.607949785f, + (float16_t)0.794907126f, (float16_t)0.606731127f, + (float16_t)0.795836905f, (float16_t)0.605511041f, + (float16_t)0.796764810f, (float16_t)0.604289531f, + (float16_t)0.797690841f, (float16_t)0.603066599f, + (float16_t)0.798614995f, (float16_t)0.601842247f, + (float16_t)0.799537269f, (float16_t)0.600616479f, + (float16_t)0.800457662f, (float16_t)0.599389298f, + (float16_t)0.801376172f, (float16_t)0.598160707f, + (float16_t)0.802292796f, (float16_t)0.596930708f, + (float16_t)0.803207531f, (float16_t)0.595699304f, + (float16_t)0.804120377f, (float16_t)0.594466499f, + (float16_t)0.805031331f, (float16_t)0.593232295f, + (float16_t)0.805940391f, (float16_t)0.591996695f, + (float16_t)0.806847554f, (float16_t)0.590759702f, + (float16_t)0.807752818f, (float16_t)0.589521319f, + (float16_t)0.808656182f, (float16_t)0.588281548f, + (float16_t)0.809557642f, (float16_t)0.587040394f, + (float16_t)0.810457198f, (float16_t)0.585797857f, + (float16_t)0.811354847f, (float16_t)0.584553943f, + (float16_t)0.812250587f, (float16_t)0.583308653f, + (float16_t)0.813144415f, (float16_t)0.582061990f, + (float16_t)0.814036330f, (float16_t)0.580813958f, + (float16_t)0.814926329f, (float16_t)0.579564559f, + (float16_t)0.815814411f, (float16_t)0.578313796f, + (float16_t)0.816700573f, (float16_t)0.577061673f, + (float16_t)0.817584813f, (float16_t)0.575808191f, + (float16_t)0.818467130f, (float16_t)0.574553355f, + (float16_t)0.819347520f, (float16_t)0.573297167f, + (float16_t)0.820225983f, (float16_t)0.572039629f, + (float16_t)0.821102515f, (float16_t)0.570780746f, + (float16_t)0.821977115f, (float16_t)0.569520519f, + (float16_t)0.822849781f, (float16_t)0.568258953f, + (float16_t)0.823720511f, (float16_t)0.566996049f, + (float16_t)0.824589303f, (float16_t)0.565731811f, + (float16_t)0.825456154f, (float16_t)0.564466242f, + (float16_t)0.826321063f, (float16_t)0.563199344f, + (float16_t)0.827184027f, (float16_t)0.561931121f, + (float16_t)0.828045045f, (float16_t)0.560661576f, + (float16_t)0.828904115f, (float16_t)0.559390712f, + (float16_t)0.829761234f, (float16_t)0.558118531f, + (float16_t)0.830616400f, (float16_t)0.556845037f, + (float16_t)0.831469612f, (float16_t)0.555570233f, + (float16_t)0.832320868f, (float16_t)0.554294121f, + (float16_t)0.833170165f, (float16_t)0.553016706f, + (float16_t)0.834017501f, (float16_t)0.551737988f, + (float16_t)0.834862875f, (float16_t)0.550457973f, + (float16_t)0.835706284f, (float16_t)0.549176662f, + (float16_t)0.836547727f, (float16_t)0.547894059f, + (float16_t)0.837387202f, (float16_t)0.546610167f, + (float16_t)0.838224706f, (float16_t)0.545324988f, + (float16_t)0.839060237f, (float16_t)0.544038527f, + (float16_t)0.839893794f, (float16_t)0.542750785f, + (float16_t)0.840725375f, (float16_t)0.541461766f, + (float16_t)0.841554977f, (float16_t)0.540171473f, + (float16_t)0.842382600f, (float16_t)0.538879909f, + (float16_t)0.843208240f, (float16_t)0.537587076f, + (float16_t)0.844031895f, (float16_t)0.536292979f, + (float16_t)0.844853565f, (float16_t)0.534997620f, + (float16_t)0.845673247f, (float16_t)0.533701002f, + (float16_t)0.846490939f, (float16_t)0.532403128f, + (float16_t)0.847306639f, (float16_t)0.531104001f, + (float16_t)0.848120345f, (float16_t)0.529803625f, + (float16_t)0.848932055f, (float16_t)0.528502002f, + (float16_t)0.849741768f, (float16_t)0.527199135f, + (float16_t)0.850549481f, (float16_t)0.525895027f, + (float16_t)0.851355193f, (float16_t)0.524589683f, + (float16_t)0.852158902f, (float16_t)0.523283103f, + (float16_t)0.852960605f, (float16_t)0.521975293f, + (float16_t)0.853760301f, (float16_t)0.520666254f, + (float16_t)0.854557988f, (float16_t)0.519355990f, + (float16_t)0.855353665f, (float16_t)0.518044504f, + (float16_t)0.856147328f, (float16_t)0.516731799f, + (float16_t)0.856938977f, (float16_t)0.515417878f, + (float16_t)0.857728610f, (float16_t)0.514102744f, + (float16_t)0.858516224f, (float16_t)0.512786401f, + (float16_t)0.859301818f, (float16_t)0.511468850f, + (float16_t)0.860085390f, (float16_t)0.510150097f, + (float16_t)0.860866939f, (float16_t)0.508830143f, + (float16_t)0.861646461f, (float16_t)0.507508991f, + (float16_t)0.862423956f, (float16_t)0.506186645f, + (float16_t)0.863199422f, (float16_t)0.504863109f, + (float16_t)0.863972856f, (float16_t)0.503538384f, + (float16_t)0.864744258f, (float16_t)0.502212474f, + (float16_t)0.865513624f, (float16_t)0.500885383f, + (float16_t)0.866280954f, (float16_t)0.499557113f, + (float16_t)0.867046246f, (float16_t)0.498227667f, + (float16_t)0.867809497f, (float16_t)0.496897049f, + (float16_t)0.868570706f, (float16_t)0.495565262f, + (float16_t)0.869329871f, (float16_t)0.494232309f, + (float16_t)0.870086991f, (float16_t)0.492898192f, + (float16_t)0.870842063f, (float16_t)0.491562916f, + (float16_t)0.871595087f, (float16_t)0.490226483f, + (float16_t)0.872346059f, (float16_t)0.488888897f, + (float16_t)0.873094978f, (float16_t)0.487550160f, + (float16_t)0.873841843f, (float16_t)0.486210276f, + (float16_t)0.874586652f, (float16_t)0.484869248f, + (float16_t)0.875329403f, (float16_t)0.483527079f, + (float16_t)0.876070094f, (float16_t)0.482183772f, + (float16_t)0.876808724f, (float16_t)0.480839331f, + (float16_t)0.877545290f, (float16_t)0.479493758f, + (float16_t)0.878279792f, (float16_t)0.478147056f, + (float16_t)0.879012226f, (float16_t)0.476799230f, + (float16_t)0.879742593f, (float16_t)0.475450282f, + (float16_t)0.880470889f, (float16_t)0.474100215f, + (float16_t)0.881197113f, (float16_t)0.472749032f, + (float16_t)0.881921264f, (float16_t)0.471396737f, + (float16_t)0.882643340f, (float16_t)0.470043332f, + (float16_t)0.883363339f, (float16_t)0.468688822f, + (float16_t)0.884081259f, (float16_t)0.467333209f, + (float16_t)0.884797098f, (float16_t)0.465976496f, + (float16_t)0.885510856f, (float16_t)0.464618686f, + (float16_t)0.886222530f, (float16_t)0.463259784f, + (float16_t)0.886932119f, (float16_t)0.461899791f, + (float16_t)0.887639620f, (float16_t)0.460538711f, + (float16_t)0.888345033f, (float16_t)0.459176548f, + (float16_t)0.889048356f, (float16_t)0.457813304f, + (float16_t)0.889749586f, (float16_t)0.456448982f, + (float16_t)0.890448723f, (float16_t)0.455083587f, + (float16_t)0.891145765f, (float16_t)0.453717121f, + (float16_t)0.891840709f, (float16_t)0.452349587f, + (float16_t)0.892533555f, (float16_t)0.450980989f, + (float16_t)0.893224301f, (float16_t)0.449611330f, + (float16_t)0.893912945f, (float16_t)0.448240612f, + (float16_t)0.894599486f, (float16_t)0.446868840f, + (float16_t)0.895283921f, (float16_t)0.445496017f, + (float16_t)0.895966250f, (float16_t)0.444122145f, + (float16_t)0.896646470f, (float16_t)0.442747228f, + (float16_t)0.897324581f, (float16_t)0.441371269f, + (float16_t)0.898000580f, (float16_t)0.439994271f, + (float16_t)0.898674466f, (float16_t)0.438616239f, + (float16_t)0.899346237f, (float16_t)0.437237174f, + (float16_t)0.900015892f, (float16_t)0.435857080f, + (float16_t)0.900683429f, (float16_t)0.434475961f, + (float16_t)0.901348847f, (float16_t)0.433093819f, + (float16_t)0.902012144f, (float16_t)0.431710658f, + (float16_t)0.902673318f, (float16_t)0.430326481f, + (float16_t)0.903332368f, (float16_t)0.428941292f, + (float16_t)0.903989293f, (float16_t)0.427555093f, + (float16_t)0.904644091f, (float16_t)0.426167889f, + (float16_t)0.905296759f, (float16_t)0.424779681f, + (float16_t)0.905947298f, (float16_t)0.423390474f, + (float16_t)0.906595705f, (float16_t)0.422000271f, + (float16_t)0.907241978f, (float16_t)0.420609074f, + (float16_t)0.907886116f, (float16_t)0.419216888f, + (float16_t)0.908528119f, (float16_t)0.417823716f, + (float16_t)0.909167983f, (float16_t)0.416429560f, + (float16_t)0.909805708f, (float16_t)0.415034424f, + (float16_t)0.910441292f, (float16_t)0.413638312f, + (float16_t)0.911074734f, (float16_t)0.412241227f, + (float16_t)0.911706032f, (float16_t)0.410843171f, + (float16_t)0.912335185f, (float16_t)0.409444149f, + (float16_t)0.912962190f, (float16_t)0.408044163f, + (float16_t)0.913587048f, (float16_t)0.406643217f, + (float16_t)0.914209756f, (float16_t)0.405241314f, + (float16_t)0.914830312f, (float16_t)0.403838458f, + (float16_t)0.915448716f, (float16_t)0.402434651f, + (float16_t)0.916064966f, (float16_t)0.401029897f, + (float16_t)0.916679060f, (float16_t)0.399624200f, + (float16_t)0.917290997f, (float16_t)0.398217562f, + (float16_t)0.917900776f, (float16_t)0.396809987f, + (float16_t)0.918508394f, (float16_t)0.395401479f, + (float16_t)0.919113852f, (float16_t)0.393992040f, + (float16_t)0.919717146f, (float16_t)0.392581674f, + (float16_t)0.920318277f, (float16_t)0.391170384f, + (float16_t)0.920917242f, (float16_t)0.389758174f, + (float16_t)0.921514039f, (float16_t)0.388345047f, + (float16_t)0.922108669f, (float16_t)0.386931006f, + (float16_t)0.922701128f, (float16_t)0.385516054f, + (float16_t)0.923291417f, (float16_t)0.384100195f, + (float16_t)0.923879533f, (float16_t)0.382683432f, + (float16_t)0.924465474f, (float16_t)0.381265769f, + (float16_t)0.925049241f, (float16_t)0.379847209f, + (float16_t)0.925630831f, (float16_t)0.378427755f, + (float16_t)0.926210242f, (float16_t)0.377007410f, + (float16_t)0.926787474f, (float16_t)0.375586178f, + (float16_t)0.927362526f, (float16_t)0.374164063f, + (float16_t)0.927935395f, (float16_t)0.372741067f, + (float16_t)0.928506080f, (float16_t)0.371317194f, + (float16_t)0.929074581f, (float16_t)0.369892447f, + (float16_t)0.929640896f, (float16_t)0.368466830f, + (float16_t)0.930205023f, (float16_t)0.367040346f, + (float16_t)0.930766961f, (float16_t)0.365612998f, + (float16_t)0.931326709f, (float16_t)0.364184790f, + (float16_t)0.931884266f, (float16_t)0.362755724f, + (float16_t)0.932439629f, (float16_t)0.361325806f, + (float16_t)0.932992799f, (float16_t)0.359895037f, + (float16_t)0.933543773f, (float16_t)0.358463421f, + (float16_t)0.934092550f, (float16_t)0.357030961f, + (float16_t)0.934639130f, (float16_t)0.355597662f, + (float16_t)0.935183510f, (float16_t)0.354163525f, + (float16_t)0.935725689f, (float16_t)0.352728556f, + (float16_t)0.936265667f, (float16_t)0.351292756f, + (float16_t)0.936803442f, (float16_t)0.349856130f, + (float16_t)0.937339012f, (float16_t)0.348418680f, + (float16_t)0.937872376f, (float16_t)0.346980411f, + (float16_t)0.938403534f, (float16_t)0.345541325f, + (float16_t)0.938932484f, (float16_t)0.344101426f, + (float16_t)0.939459224f, (float16_t)0.342660717f, + (float16_t)0.939983753f, (float16_t)0.341219202f, + (float16_t)0.940506071f, (float16_t)0.339776884f, + (float16_t)0.941026175f, (float16_t)0.338333767f, + (float16_t)0.941544065f, (float16_t)0.336889853f, + (float16_t)0.942059740f, (float16_t)0.335445147f, + (float16_t)0.942573198f, (float16_t)0.333999651f, + (float16_t)0.943084437f, (float16_t)0.332553370f, + (float16_t)0.943593458f, (float16_t)0.331106306f, + (float16_t)0.944100258f, (float16_t)0.329658463f, + (float16_t)0.944604837f, (float16_t)0.328209844f, + (float16_t)0.945107193f, (float16_t)0.326760452f, + (float16_t)0.945607325f, (float16_t)0.325310292f, + (float16_t)0.946105232f, (float16_t)0.323859367f, + (float16_t)0.946600913f, (float16_t)0.322407679f, + (float16_t)0.947094366f, (float16_t)0.320955232f, + (float16_t)0.947585591f, (float16_t)0.319502031f, + (float16_t)0.948074586f, (float16_t)0.318048077f, + (float16_t)0.948561350f, (float16_t)0.316593376f, + (float16_t)0.949045882f, (float16_t)0.315137929f, + (float16_t)0.949528181f, (float16_t)0.313681740f, + (float16_t)0.950008245f, (float16_t)0.312224814f, + (float16_t)0.950486074f, (float16_t)0.310767153f, + (float16_t)0.950961666f, (float16_t)0.309308760f, + (float16_t)0.951435021f, (float16_t)0.307849640f, + (float16_t)0.951906137f, (float16_t)0.306389795f, + (float16_t)0.952375013f, (float16_t)0.304929230f, + (float16_t)0.952841648f, (float16_t)0.303467947f, + (float16_t)0.953306040f, (float16_t)0.302005949f, + (float16_t)0.953768190f, (float16_t)0.300543241f, + (float16_t)0.954228095f, (float16_t)0.299079826f, + (float16_t)0.954685755f, (float16_t)0.297615707f, + (float16_t)0.955141168f, (float16_t)0.296150888f, + (float16_t)0.955594334f, (float16_t)0.294685372f, + (float16_t)0.956045251f, (float16_t)0.293219163f, + (float16_t)0.956493919f, (float16_t)0.291752263f, + (float16_t)0.956940336f, (float16_t)0.290284677f, + (float16_t)0.957384501f, (float16_t)0.288816408f, + (float16_t)0.957826413f, (float16_t)0.287347460f, + (float16_t)0.958266071f, (float16_t)0.285877835f, + (float16_t)0.958703475f, (float16_t)0.284407537f, + (float16_t)0.959138622f, (float16_t)0.282936570f, + (float16_t)0.959571513f, (float16_t)0.281464938f, + (float16_t)0.960002146f, (float16_t)0.279992643f, + (float16_t)0.960430519f, (float16_t)0.278519689f, + (float16_t)0.960856633f, (float16_t)0.277046080f, + (float16_t)0.961280486f, (float16_t)0.275571819f, + (float16_t)0.961702077f, (float16_t)0.274096910f, + (float16_t)0.962121404f, (float16_t)0.272621355f, + (float16_t)0.962538468f, (float16_t)0.271145160f, + (float16_t)0.962953267f, (float16_t)0.269668326f, + (float16_t)0.963365800f, (float16_t)0.268190857f, + (float16_t)0.963776066f, (float16_t)0.266712757f, + (float16_t)0.964184064f, (float16_t)0.265234030f, + (float16_t)0.964589793f, (float16_t)0.263754679f, + (float16_t)0.964993253f, (float16_t)0.262274707f, + (float16_t)0.965394442f, (float16_t)0.260794118f, + (float16_t)0.965793359f, (float16_t)0.259312915f, + (float16_t)0.966190003f, (float16_t)0.257831102f, + (float16_t)0.966584374f, (float16_t)0.256348682f, + (float16_t)0.966976471f, (float16_t)0.254865660f, + (float16_t)0.967366292f, (float16_t)0.253382037f, + (float16_t)0.967753837f, (float16_t)0.251897818f, + (float16_t)0.968139105f, (float16_t)0.250413007f, + (float16_t)0.968522094f, (float16_t)0.248927606f, + (float16_t)0.968902805f, (float16_t)0.247441619f, + (float16_t)0.969281235f, (float16_t)0.245955050f, + (float16_t)0.969657385f, (float16_t)0.244467903f, + (float16_t)0.970031253f, (float16_t)0.242980180f, + (float16_t)0.970402839f, (float16_t)0.241491885f, + (float16_t)0.970772141f, (float16_t)0.240003022f, + (float16_t)0.971139158f, (float16_t)0.238513595f, + (float16_t)0.971503891f, (float16_t)0.237023606f, + (float16_t)0.971866337f, (float16_t)0.235533059f, + (float16_t)0.972226497f, (float16_t)0.234041959f, + (float16_t)0.972584369f, (float16_t)0.232550307f, + (float16_t)0.972939952f, (float16_t)0.231058108f, + (float16_t)0.973293246f, (float16_t)0.229565366f, + (float16_t)0.973644250f, (float16_t)0.228072083f, + (float16_t)0.973992962f, (float16_t)0.226578264f, + (float16_t)0.974339383f, (float16_t)0.225083911f, + (float16_t)0.974683511f, (float16_t)0.223589029f, + (float16_t)0.975025345f, (float16_t)0.222093621f, + (float16_t)0.975364885f, (float16_t)0.220597690f, + (float16_t)0.975702130f, (float16_t)0.219101240f, + (float16_t)0.976037079f, (float16_t)0.217604275f, + (float16_t)0.976369731f, (float16_t)0.216106797f, + (float16_t)0.976700086f, (float16_t)0.214608811f, + (float16_t)0.977028143f, (float16_t)0.213110320f, + (float16_t)0.977353900f, (float16_t)0.211611327f, + (float16_t)0.977677358f, (float16_t)0.210111837f, + (float16_t)0.977998515f, (float16_t)0.208611852f, + (float16_t)0.978317371f, (float16_t)0.207111376f, + (float16_t)0.978633924f, (float16_t)0.205610413f, + (float16_t)0.978948175f, (float16_t)0.204108966f, + (float16_t)0.979260123f, (float16_t)0.202607039f, + (float16_t)0.979569766f, (float16_t)0.201104635f, + (float16_t)0.979877104f, (float16_t)0.199601758f, + (float16_t)0.980182136f, (float16_t)0.198098411f, + (float16_t)0.980484862f, (float16_t)0.196594598f, + (float16_t)0.980785280f, (float16_t)0.195090322f, + (float16_t)0.981083391f, (float16_t)0.193585587f, + (float16_t)0.981379193f, (float16_t)0.192080397f, + (float16_t)0.981672686f, (float16_t)0.190574755f, + (float16_t)0.981963869f, (float16_t)0.189068664f, + (float16_t)0.982252741f, (float16_t)0.187562129f, + (float16_t)0.982539302f, (float16_t)0.186055152f, + (float16_t)0.982823551f, (float16_t)0.184547737f, + (float16_t)0.983105487f, (float16_t)0.183039888f, + (float16_t)0.983385110f, (float16_t)0.181531608f, + (float16_t)0.983662419f, (float16_t)0.180022901f, + (float16_t)0.983937413f, (float16_t)0.178513771f, + (float16_t)0.984210092f, (float16_t)0.177004220f, + (float16_t)0.984480455f, (float16_t)0.175494253f, + (float16_t)0.984748502f, (float16_t)0.173983873f, + (float16_t)0.985014231f, (float16_t)0.172473084f, + (float16_t)0.985277642f, (float16_t)0.170961889f, + (float16_t)0.985538735f, (float16_t)0.169450291f, + (float16_t)0.985797509f, (float16_t)0.167938295f, + (float16_t)0.986053963f, (float16_t)0.166425904f, + (float16_t)0.986308097f, (float16_t)0.164913120f, + (float16_t)0.986559910f, (float16_t)0.163399949f, + (float16_t)0.986809402f, (float16_t)0.161886394f, + (float16_t)0.987056571f, (float16_t)0.160372457f, + (float16_t)0.987301418f, (float16_t)0.158858143f, + (float16_t)0.987543942f, (float16_t)0.157343456f, + (float16_t)0.987784142f, (float16_t)0.155828398f, + (float16_t)0.988022017f, (float16_t)0.154312973f, + (float16_t)0.988257568f, (float16_t)0.152797185f, + (float16_t)0.988490793f, (float16_t)0.151281038f, + (float16_t)0.988721692f, (float16_t)0.149764535f, + (float16_t)0.988950265f, (float16_t)0.148247679f, + (float16_t)0.989176510f, (float16_t)0.146730474f, + (float16_t)0.989400428f, (float16_t)0.145212925f, + (float16_t)0.989622017f, (float16_t)0.143695033f, + (float16_t)0.989841278f, (float16_t)0.142176804f, + (float16_t)0.990058210f, (float16_t)0.140658239f, + (float16_t)0.990272812f, (float16_t)0.139139344f, + (float16_t)0.990485084f, (float16_t)0.137620122f, + (float16_t)0.990695025f, (float16_t)0.136100575f, + (float16_t)0.990902635f, (float16_t)0.134580709f, + (float16_t)0.991107914f, (float16_t)0.133060525f, + (float16_t)0.991310860f, (float16_t)0.131540029f, + (float16_t)0.991511473f, (float16_t)0.130019223f, + (float16_t)0.991709754f, (float16_t)0.128498111f, + (float16_t)0.991905700f, (float16_t)0.126976696f, + (float16_t)0.992099313f, (float16_t)0.125454983f, + (float16_t)0.992290591f, (float16_t)0.123932975f, + (float16_t)0.992479535f, (float16_t)0.122410675f, + (float16_t)0.992666142f, (float16_t)0.120888087f, + (float16_t)0.992850414f, (float16_t)0.119365215f, + (float16_t)0.993032350f, (float16_t)0.117842062f, + (float16_t)0.993211949f, (float16_t)0.116318631f, + (float16_t)0.993389211f, (float16_t)0.114794927f, + (float16_t)0.993564136f, (float16_t)0.113270952f, + (float16_t)0.993736722f, (float16_t)0.111746711f, + (float16_t)0.993906970f, (float16_t)0.110222207f, + (float16_t)0.994074879f, (float16_t)0.108697444f, + (float16_t)0.994240449f, (float16_t)0.107172425f, + (float16_t)0.994403680f, (float16_t)0.105647154f, + (float16_t)0.994564571f, (float16_t)0.104121634f, + (float16_t)0.994723121f, (float16_t)0.102595869f, + (float16_t)0.994879331f, (float16_t)0.101069863f, + (float16_t)0.995033199f, (float16_t)0.099543619f, + (float16_t)0.995184727f, (float16_t)0.098017140f, + (float16_t)0.995333912f, (float16_t)0.096490431f, + (float16_t)0.995480755f, (float16_t)0.094963495f, + (float16_t)0.995625256f, (float16_t)0.093436336f, + (float16_t)0.995767414f, (float16_t)0.091908956f, + (float16_t)0.995907229f, (float16_t)0.090381361f, + (float16_t)0.996044701f, (float16_t)0.088853553f, + (float16_t)0.996179829f, (float16_t)0.087325535f, + (float16_t)0.996312612f, (float16_t)0.085797312f, + (float16_t)0.996443051f, (float16_t)0.084268888f, + (float16_t)0.996571146f, (float16_t)0.082740265f, + (float16_t)0.996696895f, (float16_t)0.081211447f, + (float16_t)0.996820299f, (float16_t)0.079682438f, + (float16_t)0.996941358f, (float16_t)0.078153242f, + (float16_t)0.997060070f, (float16_t)0.076623861f, + (float16_t)0.997176437f, (float16_t)0.075094301f, + (float16_t)0.997290457f, (float16_t)0.073564564f, + (float16_t)0.997402130f, (float16_t)0.072034653f, + (float16_t)0.997511456f, (float16_t)0.070504573f, + (float16_t)0.997618435f, (float16_t)0.068974328f, + (float16_t)0.997723067f, (float16_t)0.067443920f, + (float16_t)0.997825350f, (float16_t)0.065913353f, + (float16_t)0.997925286f, (float16_t)0.064382631f, + (float16_t)0.998022874f, (float16_t)0.062851758f, + (float16_t)0.998118113f, (float16_t)0.061320736f, + (float16_t)0.998211003f, (float16_t)0.059789571f, + (float16_t)0.998301545f, (float16_t)0.058258265f, + (float16_t)0.998389737f, (float16_t)0.056726821f, + (float16_t)0.998475581f, (float16_t)0.055195244f, + (float16_t)0.998559074f, (float16_t)0.053663538f, + (float16_t)0.998640218f, (float16_t)0.052131705f, + (float16_t)0.998719012f, (float16_t)0.050599749f, + (float16_t)0.998795456f, (float16_t)0.049067674f, + (float16_t)0.998869550f, (float16_t)0.047535484f, + (float16_t)0.998941293f, (float16_t)0.046003182f, + (float16_t)0.999010686f, (float16_t)0.044470772f, + (float16_t)0.999077728f, (float16_t)0.042938257f, + (float16_t)0.999142419f, (float16_t)0.041405641f, + (float16_t)0.999204759f, (float16_t)0.039872928f, + (float16_t)0.999264747f, (float16_t)0.038340120f, + (float16_t)0.999322385f, (float16_t)0.036807223f, + (float16_t)0.999377670f, (float16_t)0.035274239f, + (float16_t)0.999430605f, (float16_t)0.033741172f, + (float16_t)0.999481187f, (float16_t)0.032208025f, + (float16_t)0.999529418f, (float16_t)0.030674803f, + (float16_t)0.999575296f, (float16_t)0.029141509f, + (float16_t)0.999618822f, (float16_t)0.027608146f, + (float16_t)0.999659997f, (float16_t)0.026074718f, + (float16_t)0.999698819f, (float16_t)0.024541229f, + (float16_t)0.999735288f, (float16_t)0.023007681f, + (float16_t)0.999769405f, (float16_t)0.021474080f, + (float16_t)0.999801170f, (float16_t)0.019940429f, + (float16_t)0.999830582f, (float16_t)0.018406730f, + (float16_t)0.999857641f, (float16_t)0.016872988f, + (float16_t)0.999882347f, (float16_t)0.015339206f, + (float16_t)0.999904701f, (float16_t)0.013805389f, + (float16_t)0.999924702f, (float16_t)0.012271538f, + (float16_t)0.999942350f, (float16_t)0.010737659f, + (float16_t)0.999957645f, (float16_t)0.009203755f, + (float16_t)0.999970586f, (float16_t)0.007669829f, + (float16_t)0.999981175f, (float16_t)0.006135885f, + (float16_t)0.999989411f, (float16_t)0.004601926f, + (float16_t)0.999995294f, (float16_t)0.003067957f, + (float16_t)0.999998823f, (float16_t)0.001533980f, + (float16_t)1.000000000f, (float16_t)0.000000000f, + (float16_t)0.999998823f, (float16_t)-0.001533980f, + (float16_t)0.999995294f, (float16_t)-0.003067957f, + (float16_t)0.999989411f, (float16_t)-0.004601926f, + (float16_t)0.999981175f, (float16_t)-0.006135885f, + (float16_t)0.999970586f, (float16_t)-0.007669829f, + (float16_t)0.999957645f, (float16_t)-0.009203755f, + (float16_t)0.999942350f, (float16_t)-0.010737659f, + (float16_t)0.999924702f, (float16_t)-0.012271538f, + (float16_t)0.999904701f, (float16_t)-0.013805389f, + (float16_t)0.999882347f, (float16_t)-0.015339206f, + (float16_t)0.999857641f, (float16_t)-0.016872988f, + (float16_t)0.999830582f, (float16_t)-0.018406730f, + (float16_t)0.999801170f, (float16_t)-0.019940429f, + (float16_t)0.999769405f, (float16_t)-0.021474080f, + (float16_t)0.999735288f, (float16_t)-0.023007681f, + (float16_t)0.999698819f, (float16_t)-0.024541229f, + (float16_t)0.999659997f, (float16_t)-0.026074718f, + (float16_t)0.999618822f, (float16_t)-0.027608146f, + (float16_t)0.999575296f, (float16_t)-0.029141509f, + (float16_t)0.999529418f, (float16_t)-0.030674803f, + (float16_t)0.999481187f, (float16_t)-0.032208025f, + (float16_t)0.999430605f, (float16_t)-0.033741172f, + (float16_t)0.999377670f, (float16_t)-0.035274239f, + (float16_t)0.999322385f, (float16_t)-0.036807223f, + (float16_t)0.999264747f, (float16_t)-0.038340120f, + (float16_t)0.999204759f, (float16_t)-0.039872928f, + (float16_t)0.999142419f, (float16_t)-0.041405641f, + (float16_t)0.999077728f, (float16_t)-0.042938257f, + (float16_t)0.999010686f, (float16_t)-0.044470772f, + (float16_t)0.998941293f, (float16_t)-0.046003182f, + (float16_t)0.998869550f, (float16_t)-0.047535484f, + (float16_t)0.998795456f, (float16_t)-0.049067674f, + (float16_t)0.998719012f, (float16_t)-0.050599749f, + (float16_t)0.998640218f, (float16_t)-0.052131705f, + (float16_t)0.998559074f, (float16_t)-0.053663538f, + (float16_t)0.998475581f, (float16_t)-0.055195244f, + (float16_t)0.998389737f, (float16_t)-0.056726821f, + (float16_t)0.998301545f, (float16_t)-0.058258265f, + (float16_t)0.998211003f, (float16_t)-0.059789571f, + (float16_t)0.998118113f, (float16_t)-0.061320736f, + (float16_t)0.998022874f, (float16_t)-0.062851758f, + (float16_t)0.997925286f, (float16_t)-0.064382631f, + (float16_t)0.997825350f, (float16_t)-0.065913353f, + (float16_t)0.997723067f, (float16_t)-0.067443920f, + (float16_t)0.997618435f, (float16_t)-0.068974328f, + (float16_t)0.997511456f, (float16_t)-0.070504573f, + (float16_t)0.997402130f, (float16_t)-0.072034653f, + (float16_t)0.997290457f, (float16_t)-0.073564564f, + (float16_t)0.997176437f, (float16_t)-0.075094301f, + (float16_t)0.997060070f, (float16_t)-0.076623861f, + (float16_t)0.996941358f, (float16_t)-0.078153242f, + (float16_t)0.996820299f, (float16_t)-0.079682438f, + (float16_t)0.996696895f, (float16_t)-0.081211447f, + (float16_t)0.996571146f, (float16_t)-0.082740265f, + (float16_t)0.996443051f, (float16_t)-0.084268888f, + (float16_t)0.996312612f, (float16_t)-0.085797312f, + (float16_t)0.996179829f, (float16_t)-0.087325535f, + (float16_t)0.996044701f, (float16_t)-0.088853553f, + (float16_t)0.995907229f, (float16_t)-0.090381361f, + (float16_t)0.995767414f, (float16_t)-0.091908956f, + (float16_t)0.995625256f, (float16_t)-0.093436336f, + (float16_t)0.995480755f, (float16_t)-0.094963495f, + (float16_t)0.995333912f, (float16_t)-0.096490431f, + (float16_t)0.995184727f, (float16_t)-0.098017140f, + (float16_t)0.995033199f, (float16_t)-0.099543619f, + (float16_t)0.994879331f, (float16_t)-0.101069863f, + (float16_t)0.994723121f, (float16_t)-0.102595869f, + (float16_t)0.994564571f, (float16_t)-0.104121634f, + (float16_t)0.994403680f, (float16_t)-0.105647154f, + (float16_t)0.994240449f, (float16_t)-0.107172425f, + (float16_t)0.994074879f, (float16_t)-0.108697444f, + (float16_t)0.993906970f, (float16_t)-0.110222207f, + (float16_t)0.993736722f, (float16_t)-0.111746711f, + (float16_t)0.993564136f, (float16_t)-0.113270952f, + (float16_t)0.993389211f, (float16_t)-0.114794927f, + (float16_t)0.993211949f, (float16_t)-0.116318631f, + (float16_t)0.993032350f, (float16_t)-0.117842062f, + (float16_t)0.992850414f, (float16_t)-0.119365215f, + (float16_t)0.992666142f, (float16_t)-0.120888087f, + (float16_t)0.992479535f, (float16_t)-0.122410675f, + (float16_t)0.992290591f, (float16_t)-0.123932975f, + (float16_t)0.992099313f, (float16_t)-0.125454983f, + (float16_t)0.991905700f, (float16_t)-0.126976696f, + (float16_t)0.991709754f, (float16_t)-0.128498111f, + (float16_t)0.991511473f, (float16_t)-0.130019223f, + (float16_t)0.991310860f, (float16_t)-0.131540029f, + (float16_t)0.991107914f, (float16_t)-0.133060525f, + (float16_t)0.990902635f, (float16_t)-0.134580709f, + (float16_t)0.990695025f, (float16_t)-0.136100575f, + (float16_t)0.990485084f, (float16_t)-0.137620122f, + (float16_t)0.990272812f, (float16_t)-0.139139344f, + (float16_t)0.990058210f, (float16_t)-0.140658239f, + (float16_t)0.989841278f, (float16_t)-0.142176804f, + (float16_t)0.989622017f, (float16_t)-0.143695033f, + (float16_t)0.989400428f, (float16_t)-0.145212925f, + (float16_t)0.989176510f, (float16_t)-0.146730474f, + (float16_t)0.988950265f, (float16_t)-0.148247679f, + (float16_t)0.988721692f, (float16_t)-0.149764535f, + (float16_t)0.988490793f, (float16_t)-0.151281038f, + (float16_t)0.988257568f, (float16_t)-0.152797185f, + (float16_t)0.988022017f, (float16_t)-0.154312973f, + (float16_t)0.987784142f, (float16_t)-0.155828398f, + (float16_t)0.987543942f, (float16_t)-0.157343456f, + (float16_t)0.987301418f, (float16_t)-0.158858143f, + (float16_t)0.987056571f, (float16_t)-0.160372457f, + (float16_t)0.986809402f, (float16_t)-0.161886394f, + (float16_t)0.986559910f, (float16_t)-0.163399949f, + (float16_t)0.986308097f, (float16_t)-0.164913120f, + (float16_t)0.986053963f, (float16_t)-0.166425904f, + (float16_t)0.985797509f, (float16_t)-0.167938295f, + (float16_t)0.985538735f, (float16_t)-0.169450291f, + (float16_t)0.985277642f, (float16_t)-0.170961889f, + (float16_t)0.985014231f, (float16_t)-0.172473084f, + (float16_t)0.984748502f, (float16_t)-0.173983873f, + (float16_t)0.984480455f, (float16_t)-0.175494253f, + (float16_t)0.984210092f, (float16_t)-0.177004220f, + (float16_t)0.983937413f, (float16_t)-0.178513771f, + (float16_t)0.983662419f, (float16_t)-0.180022901f, + (float16_t)0.983385110f, (float16_t)-0.181531608f, + (float16_t)0.983105487f, (float16_t)-0.183039888f, + (float16_t)0.982823551f, (float16_t)-0.184547737f, + (float16_t)0.982539302f, (float16_t)-0.186055152f, + (float16_t)0.982252741f, (float16_t)-0.187562129f, + (float16_t)0.981963869f, (float16_t)-0.189068664f, + (float16_t)0.981672686f, (float16_t)-0.190574755f, + (float16_t)0.981379193f, (float16_t)-0.192080397f, + (float16_t)0.981083391f, (float16_t)-0.193585587f, + (float16_t)0.980785280f, (float16_t)-0.195090322f, + (float16_t)0.980484862f, (float16_t)-0.196594598f, + (float16_t)0.980182136f, (float16_t)-0.198098411f, + (float16_t)0.979877104f, (float16_t)-0.199601758f, + (float16_t)0.979569766f, (float16_t)-0.201104635f, + (float16_t)0.979260123f, (float16_t)-0.202607039f, + (float16_t)0.978948175f, (float16_t)-0.204108966f, + (float16_t)0.978633924f, (float16_t)-0.205610413f, + (float16_t)0.978317371f, (float16_t)-0.207111376f, + (float16_t)0.977998515f, (float16_t)-0.208611852f, + (float16_t)0.977677358f, (float16_t)-0.210111837f, + (float16_t)0.977353900f, (float16_t)-0.211611327f, + (float16_t)0.977028143f, (float16_t)-0.213110320f, + (float16_t)0.976700086f, (float16_t)-0.214608811f, + (float16_t)0.976369731f, (float16_t)-0.216106797f, + (float16_t)0.976037079f, (float16_t)-0.217604275f, + (float16_t)0.975702130f, (float16_t)-0.219101240f, + (float16_t)0.975364885f, (float16_t)-0.220597690f, + (float16_t)0.975025345f, (float16_t)-0.222093621f, + (float16_t)0.974683511f, (float16_t)-0.223589029f, + (float16_t)0.974339383f, (float16_t)-0.225083911f, + (float16_t)0.973992962f, (float16_t)-0.226578264f, + (float16_t)0.973644250f, (float16_t)-0.228072083f, + (float16_t)0.973293246f, (float16_t)-0.229565366f, + (float16_t)0.972939952f, (float16_t)-0.231058108f, + (float16_t)0.972584369f, (float16_t)-0.232550307f, + (float16_t)0.972226497f, (float16_t)-0.234041959f, + (float16_t)0.971866337f, (float16_t)-0.235533059f, + (float16_t)0.971503891f, (float16_t)-0.237023606f, + (float16_t)0.971139158f, (float16_t)-0.238513595f, + (float16_t)0.970772141f, (float16_t)-0.240003022f, + (float16_t)0.970402839f, (float16_t)-0.241491885f, + (float16_t)0.970031253f, (float16_t)-0.242980180f, + (float16_t)0.969657385f, (float16_t)-0.244467903f, + (float16_t)0.969281235f, (float16_t)-0.245955050f, + (float16_t)0.968902805f, (float16_t)-0.247441619f, + (float16_t)0.968522094f, (float16_t)-0.248927606f, + (float16_t)0.968139105f, (float16_t)-0.250413007f, + (float16_t)0.967753837f, (float16_t)-0.251897818f, + (float16_t)0.967366292f, (float16_t)-0.253382037f, + (float16_t)0.966976471f, (float16_t)-0.254865660f, + (float16_t)0.966584374f, (float16_t)-0.256348682f, + (float16_t)0.966190003f, (float16_t)-0.257831102f, + (float16_t)0.965793359f, (float16_t)-0.259312915f, + (float16_t)0.965394442f, (float16_t)-0.260794118f, + (float16_t)0.964993253f, (float16_t)-0.262274707f, + (float16_t)0.964589793f, (float16_t)-0.263754679f, + (float16_t)0.964184064f, (float16_t)-0.265234030f, + (float16_t)0.963776066f, (float16_t)-0.266712757f, + (float16_t)0.963365800f, (float16_t)-0.268190857f, + (float16_t)0.962953267f, (float16_t)-0.269668326f, + (float16_t)0.962538468f, (float16_t)-0.271145160f, + (float16_t)0.962121404f, (float16_t)-0.272621355f, + (float16_t)0.961702077f, (float16_t)-0.274096910f, + (float16_t)0.961280486f, (float16_t)-0.275571819f, + (float16_t)0.960856633f, (float16_t)-0.277046080f, + (float16_t)0.960430519f, (float16_t)-0.278519689f, + (float16_t)0.960002146f, (float16_t)-0.279992643f, + (float16_t)0.959571513f, (float16_t)-0.281464938f, + (float16_t)0.959138622f, (float16_t)-0.282936570f, + (float16_t)0.958703475f, (float16_t)-0.284407537f, + (float16_t)0.958266071f, (float16_t)-0.285877835f, + (float16_t)0.957826413f, (float16_t)-0.287347460f, + (float16_t)0.957384501f, (float16_t)-0.288816408f, + (float16_t)0.956940336f, (float16_t)-0.290284677f, + (float16_t)0.956493919f, (float16_t)-0.291752263f, + (float16_t)0.956045251f, (float16_t)-0.293219163f, + (float16_t)0.955594334f, (float16_t)-0.294685372f, + (float16_t)0.955141168f, (float16_t)-0.296150888f, + (float16_t)0.954685755f, (float16_t)-0.297615707f, + (float16_t)0.954228095f, (float16_t)-0.299079826f, + (float16_t)0.953768190f, (float16_t)-0.300543241f, + (float16_t)0.953306040f, (float16_t)-0.302005949f, + (float16_t)0.952841648f, (float16_t)-0.303467947f, + (float16_t)0.952375013f, (float16_t)-0.304929230f, + (float16_t)0.951906137f, (float16_t)-0.306389795f, + (float16_t)0.951435021f, (float16_t)-0.307849640f, + (float16_t)0.950961666f, (float16_t)-0.309308760f, + (float16_t)0.950486074f, (float16_t)-0.310767153f, + (float16_t)0.950008245f, (float16_t)-0.312224814f, + (float16_t)0.949528181f, (float16_t)-0.313681740f, + (float16_t)0.949045882f, (float16_t)-0.315137929f, + (float16_t)0.948561350f, (float16_t)-0.316593376f, + (float16_t)0.948074586f, (float16_t)-0.318048077f, + (float16_t)0.947585591f, (float16_t)-0.319502031f, + (float16_t)0.947094366f, (float16_t)-0.320955232f, + (float16_t)0.946600913f, (float16_t)-0.322407679f, + (float16_t)0.946105232f, (float16_t)-0.323859367f, + (float16_t)0.945607325f, (float16_t)-0.325310292f, + (float16_t)0.945107193f, (float16_t)-0.326760452f, + (float16_t)0.944604837f, (float16_t)-0.328209844f, + (float16_t)0.944100258f, (float16_t)-0.329658463f, + (float16_t)0.943593458f, (float16_t)-0.331106306f, + (float16_t)0.943084437f, (float16_t)-0.332553370f, + (float16_t)0.942573198f, (float16_t)-0.333999651f, + (float16_t)0.942059740f, (float16_t)-0.335445147f, + (float16_t)0.941544065f, (float16_t)-0.336889853f, + (float16_t)0.941026175f, (float16_t)-0.338333767f, + (float16_t)0.940506071f, (float16_t)-0.339776884f, + (float16_t)0.939983753f, (float16_t)-0.341219202f, + (float16_t)0.939459224f, (float16_t)-0.342660717f, + (float16_t)0.938932484f, (float16_t)-0.344101426f, + (float16_t)0.938403534f, (float16_t)-0.345541325f, + (float16_t)0.937872376f, (float16_t)-0.346980411f, + (float16_t)0.937339012f, (float16_t)-0.348418680f, + (float16_t)0.936803442f, (float16_t)-0.349856130f, + (float16_t)0.936265667f, (float16_t)-0.351292756f, + (float16_t)0.935725689f, (float16_t)-0.352728556f, + (float16_t)0.935183510f, (float16_t)-0.354163525f, + (float16_t)0.934639130f, (float16_t)-0.355597662f, + (float16_t)0.934092550f, (float16_t)-0.357030961f, + (float16_t)0.933543773f, (float16_t)-0.358463421f, + (float16_t)0.932992799f, (float16_t)-0.359895037f, + (float16_t)0.932439629f, (float16_t)-0.361325806f, + (float16_t)0.931884266f, (float16_t)-0.362755724f, + (float16_t)0.931326709f, (float16_t)-0.364184790f, + (float16_t)0.930766961f, (float16_t)-0.365612998f, + (float16_t)0.930205023f, (float16_t)-0.367040346f, + (float16_t)0.929640896f, (float16_t)-0.368466830f, + (float16_t)0.929074581f, (float16_t)-0.369892447f, + (float16_t)0.928506080f, (float16_t)-0.371317194f, + (float16_t)0.927935395f, (float16_t)-0.372741067f, + (float16_t)0.927362526f, (float16_t)-0.374164063f, + (float16_t)0.926787474f, (float16_t)-0.375586178f, + (float16_t)0.926210242f, (float16_t)-0.377007410f, + (float16_t)0.925630831f, (float16_t)-0.378427755f, + (float16_t)0.925049241f, (float16_t)-0.379847209f, + (float16_t)0.924465474f, (float16_t)-0.381265769f, + (float16_t)0.923879533f, (float16_t)-0.382683432f, + (float16_t)0.923291417f, (float16_t)-0.384100195f, + (float16_t)0.922701128f, (float16_t)-0.385516054f, + (float16_t)0.922108669f, (float16_t)-0.386931006f, + (float16_t)0.921514039f, (float16_t)-0.388345047f, + (float16_t)0.920917242f, (float16_t)-0.389758174f, + (float16_t)0.920318277f, (float16_t)-0.391170384f, + (float16_t)0.919717146f, (float16_t)-0.392581674f, + (float16_t)0.919113852f, (float16_t)-0.393992040f, + (float16_t)0.918508394f, (float16_t)-0.395401479f, + (float16_t)0.917900776f, (float16_t)-0.396809987f, + (float16_t)0.917290997f, (float16_t)-0.398217562f, + (float16_t)0.916679060f, (float16_t)-0.399624200f, + (float16_t)0.916064966f, (float16_t)-0.401029897f, + (float16_t)0.915448716f, (float16_t)-0.402434651f, + (float16_t)0.914830312f, (float16_t)-0.403838458f, + (float16_t)0.914209756f, (float16_t)-0.405241314f, + (float16_t)0.913587048f, (float16_t)-0.406643217f, + (float16_t)0.912962190f, (float16_t)-0.408044163f, + (float16_t)0.912335185f, (float16_t)-0.409444149f, + (float16_t)0.911706032f, (float16_t)-0.410843171f, + (float16_t)0.911074734f, (float16_t)-0.412241227f, + (float16_t)0.910441292f, (float16_t)-0.413638312f, + (float16_t)0.909805708f, (float16_t)-0.415034424f, + (float16_t)0.909167983f, (float16_t)-0.416429560f, + (float16_t)0.908528119f, (float16_t)-0.417823716f, + (float16_t)0.907886116f, (float16_t)-0.419216888f, + (float16_t)0.907241978f, (float16_t)-0.420609074f, + (float16_t)0.906595705f, (float16_t)-0.422000271f, + (float16_t)0.905947298f, (float16_t)-0.423390474f, + (float16_t)0.905296759f, (float16_t)-0.424779681f, + (float16_t)0.904644091f, (float16_t)-0.426167889f, + (float16_t)0.903989293f, (float16_t)-0.427555093f, + (float16_t)0.903332368f, (float16_t)-0.428941292f, + (float16_t)0.902673318f, (float16_t)-0.430326481f, + (float16_t)0.902012144f, (float16_t)-0.431710658f, + (float16_t)0.901348847f, (float16_t)-0.433093819f, + (float16_t)0.900683429f, (float16_t)-0.434475961f, + (float16_t)0.900015892f, (float16_t)-0.435857080f, + (float16_t)0.899346237f, (float16_t)-0.437237174f, + (float16_t)0.898674466f, (float16_t)-0.438616239f, + (float16_t)0.898000580f, (float16_t)-0.439994271f, + (float16_t)0.897324581f, (float16_t)-0.441371269f, + (float16_t)0.896646470f, (float16_t)-0.442747228f, + (float16_t)0.895966250f, (float16_t)-0.444122145f, + (float16_t)0.895283921f, (float16_t)-0.445496017f, + (float16_t)0.894599486f, (float16_t)-0.446868840f, + (float16_t)0.893912945f, (float16_t)-0.448240612f, + (float16_t)0.893224301f, (float16_t)-0.449611330f, + (float16_t)0.892533555f, (float16_t)-0.450980989f, + (float16_t)0.891840709f, (float16_t)-0.452349587f, + (float16_t)0.891145765f, (float16_t)-0.453717121f, + (float16_t)0.890448723f, (float16_t)-0.455083587f, + (float16_t)0.889749586f, (float16_t)-0.456448982f, + (float16_t)0.889048356f, (float16_t)-0.457813304f, + (float16_t)0.888345033f, (float16_t)-0.459176548f, + (float16_t)0.887639620f, (float16_t)-0.460538711f, + (float16_t)0.886932119f, (float16_t)-0.461899791f, + (float16_t)0.886222530f, (float16_t)-0.463259784f, + (float16_t)0.885510856f, (float16_t)-0.464618686f, + (float16_t)0.884797098f, (float16_t)-0.465976496f, + (float16_t)0.884081259f, (float16_t)-0.467333209f, + (float16_t)0.883363339f, (float16_t)-0.468688822f, + (float16_t)0.882643340f, (float16_t)-0.470043332f, + (float16_t)0.881921264f, (float16_t)-0.471396737f, + (float16_t)0.881197113f, (float16_t)-0.472749032f, + (float16_t)0.880470889f, (float16_t)-0.474100215f, + (float16_t)0.879742593f, (float16_t)-0.475450282f, + (float16_t)0.879012226f, (float16_t)-0.476799230f, + (float16_t)0.878279792f, (float16_t)-0.478147056f, + (float16_t)0.877545290f, (float16_t)-0.479493758f, + (float16_t)0.876808724f, (float16_t)-0.480839331f, + (float16_t)0.876070094f, (float16_t)-0.482183772f, + (float16_t)0.875329403f, (float16_t)-0.483527079f, + (float16_t)0.874586652f, (float16_t)-0.484869248f, + (float16_t)0.873841843f, (float16_t)-0.486210276f, + (float16_t)0.873094978f, (float16_t)-0.487550160f, + (float16_t)0.872346059f, (float16_t)-0.488888897f, + (float16_t)0.871595087f, (float16_t)-0.490226483f, + (float16_t)0.870842063f, (float16_t)-0.491562916f, + (float16_t)0.870086991f, (float16_t)-0.492898192f, + (float16_t)0.869329871f, (float16_t)-0.494232309f, + (float16_t)0.868570706f, (float16_t)-0.495565262f, + (float16_t)0.867809497f, (float16_t)-0.496897049f, + (float16_t)0.867046246f, (float16_t)-0.498227667f, + (float16_t)0.866280954f, (float16_t)-0.499557113f, + (float16_t)0.865513624f, (float16_t)-0.500885383f, + (float16_t)0.864744258f, (float16_t)-0.502212474f, + (float16_t)0.863972856f, (float16_t)-0.503538384f, + (float16_t)0.863199422f, (float16_t)-0.504863109f, + (float16_t)0.862423956f, (float16_t)-0.506186645f, + (float16_t)0.861646461f, (float16_t)-0.507508991f, + (float16_t)0.860866939f, (float16_t)-0.508830143f, + (float16_t)0.860085390f, (float16_t)-0.510150097f, + (float16_t)0.859301818f, (float16_t)-0.511468850f, + (float16_t)0.858516224f, (float16_t)-0.512786401f, + (float16_t)0.857728610f, (float16_t)-0.514102744f, + (float16_t)0.856938977f, (float16_t)-0.515417878f, + (float16_t)0.856147328f, (float16_t)-0.516731799f, + (float16_t)0.855353665f, (float16_t)-0.518044504f, + (float16_t)0.854557988f, (float16_t)-0.519355990f, + (float16_t)0.853760301f, (float16_t)-0.520666254f, + (float16_t)0.852960605f, (float16_t)-0.521975293f, + (float16_t)0.852158902f, (float16_t)-0.523283103f, + (float16_t)0.851355193f, (float16_t)-0.524589683f, + (float16_t)0.850549481f, (float16_t)-0.525895027f, + (float16_t)0.849741768f, (float16_t)-0.527199135f, + (float16_t)0.848932055f, (float16_t)-0.528502002f, + (float16_t)0.848120345f, (float16_t)-0.529803625f, + (float16_t)0.847306639f, (float16_t)-0.531104001f, + (float16_t)0.846490939f, (float16_t)-0.532403128f, + (float16_t)0.845673247f, (float16_t)-0.533701002f, + (float16_t)0.844853565f, (float16_t)-0.534997620f, + (float16_t)0.844031895f, (float16_t)-0.536292979f, + (float16_t)0.843208240f, (float16_t)-0.537587076f, + (float16_t)0.842382600f, (float16_t)-0.538879909f, + (float16_t)0.841554977f, (float16_t)-0.540171473f, + (float16_t)0.840725375f, (float16_t)-0.541461766f, + (float16_t)0.839893794f, (float16_t)-0.542750785f, + (float16_t)0.839060237f, (float16_t)-0.544038527f, + (float16_t)0.838224706f, (float16_t)-0.545324988f, + (float16_t)0.837387202f, (float16_t)-0.546610167f, + (float16_t)0.836547727f, (float16_t)-0.547894059f, + (float16_t)0.835706284f, (float16_t)-0.549176662f, + (float16_t)0.834862875f, (float16_t)-0.550457973f, + (float16_t)0.834017501f, (float16_t)-0.551737988f, + (float16_t)0.833170165f, (float16_t)-0.553016706f, + (float16_t)0.832320868f, (float16_t)-0.554294121f, + (float16_t)0.831469612f, (float16_t)-0.555570233f, + (float16_t)0.830616400f, (float16_t)-0.556845037f, + (float16_t)0.829761234f, (float16_t)-0.558118531f, + (float16_t)0.828904115f, (float16_t)-0.559390712f, + (float16_t)0.828045045f, (float16_t)-0.560661576f, + (float16_t)0.827184027f, (float16_t)-0.561931121f, + (float16_t)0.826321063f, (float16_t)-0.563199344f, + (float16_t)0.825456154f, (float16_t)-0.564466242f, + (float16_t)0.824589303f, (float16_t)-0.565731811f, + (float16_t)0.823720511f, (float16_t)-0.566996049f, + (float16_t)0.822849781f, (float16_t)-0.568258953f, + (float16_t)0.821977115f, (float16_t)-0.569520519f, + (float16_t)0.821102515f, (float16_t)-0.570780746f, + (float16_t)0.820225983f, (float16_t)-0.572039629f, + (float16_t)0.819347520f, (float16_t)-0.573297167f, + (float16_t)0.818467130f, (float16_t)-0.574553355f, + (float16_t)0.817584813f, (float16_t)-0.575808191f, + (float16_t)0.816700573f, (float16_t)-0.577061673f, + (float16_t)0.815814411f, (float16_t)-0.578313796f, + (float16_t)0.814926329f, (float16_t)-0.579564559f, + (float16_t)0.814036330f, (float16_t)-0.580813958f, + (float16_t)0.813144415f, (float16_t)-0.582061990f, + (float16_t)0.812250587f, (float16_t)-0.583308653f, + (float16_t)0.811354847f, (float16_t)-0.584553943f, + (float16_t)0.810457198f, (float16_t)-0.585797857f, + (float16_t)0.809557642f, (float16_t)-0.587040394f, + (float16_t)0.808656182f, (float16_t)-0.588281548f, + (float16_t)0.807752818f, (float16_t)-0.589521319f, + (float16_t)0.806847554f, (float16_t)-0.590759702f, + (float16_t)0.805940391f, (float16_t)-0.591996695f, + (float16_t)0.805031331f, (float16_t)-0.593232295f, + (float16_t)0.804120377f, (float16_t)-0.594466499f, + (float16_t)0.803207531f, (float16_t)-0.595699304f, + (float16_t)0.802292796f, (float16_t)-0.596930708f, + (float16_t)0.801376172f, (float16_t)-0.598160707f, + (float16_t)0.800457662f, (float16_t)-0.599389298f, + (float16_t)0.799537269f, (float16_t)-0.600616479f, + (float16_t)0.798614995f, (float16_t)-0.601842247f, + (float16_t)0.797690841f, (float16_t)-0.603066599f, + (float16_t)0.796764810f, (float16_t)-0.604289531f, + (float16_t)0.795836905f, (float16_t)-0.605511041f, + (float16_t)0.794907126f, (float16_t)-0.606731127f, + (float16_t)0.793975478f, (float16_t)-0.607949785f, + (float16_t)0.793041960f, (float16_t)-0.609167012f, + (float16_t)0.792106577f, (float16_t)-0.610382806f, + (float16_t)0.791169330f, (float16_t)-0.611597164f, + (float16_t)0.790230221f, (float16_t)-0.612810082f, + (float16_t)0.789289253f, (float16_t)-0.614021559f, + (float16_t)0.788346428f, (float16_t)-0.615231591f, + (float16_t)0.787401747f, (float16_t)-0.616440175f, + (float16_t)0.786455214f, (float16_t)-0.617647308f, + (float16_t)0.785506830f, (float16_t)-0.618852988f, + (float16_t)0.784556597f, (float16_t)-0.620057212f, + (float16_t)0.783604519f, (float16_t)-0.621259977f, + (float16_t)0.782650596f, (float16_t)-0.622461279f, + (float16_t)0.781694832f, (float16_t)-0.623661118f, + (float16_t)0.780737229f, (float16_t)-0.624859488f, + (float16_t)0.779777788f, (float16_t)-0.626056388f, + (float16_t)0.778816512f, (float16_t)-0.627251815f, + (float16_t)0.777853404f, (float16_t)-0.628445767f, + (float16_t)0.776888466f, (float16_t)-0.629638239f, + (float16_t)0.775921699f, (float16_t)-0.630829230f, + (float16_t)0.774953107f, (float16_t)-0.632018736f, + (float16_t)0.773982691f, (float16_t)-0.633206755f, + (float16_t)0.773010453f, (float16_t)-0.634393284f, + (float16_t)0.772036397f, (float16_t)-0.635578320f, + (float16_t)0.771060524f, (float16_t)-0.636761861f, + (float16_t)0.770082837f, (float16_t)-0.637943904f, + (float16_t)0.769103338f, (float16_t)-0.639124445f, + (float16_t)0.768122029f, (float16_t)-0.640303482f, + (float16_t)0.767138912f, (float16_t)-0.641481013f, + (float16_t)0.766153990f, (float16_t)-0.642657034f, + (float16_t)0.765167266f, (float16_t)-0.643831543f, + (float16_t)0.764178741f, (float16_t)-0.645004537f, + (float16_t)0.763188417f, (float16_t)-0.646176013f, + (float16_t)0.762196298f, (float16_t)-0.647345969f, + (float16_t)0.761202385f, (float16_t)-0.648514401f, + (float16_t)0.760206682f, (float16_t)-0.649681307f, + (float16_t)0.759209189f, (float16_t)-0.650846685f, + (float16_t)0.758209910f, (float16_t)-0.652010531f, + (float16_t)0.757208847f, (float16_t)-0.653172843f, + (float16_t)0.756206001f, (float16_t)-0.654333618f, + (float16_t)0.755201377f, (float16_t)-0.655492853f, + (float16_t)0.754194975f, (float16_t)-0.656650546f, + (float16_t)0.753186799f, (float16_t)-0.657806693f, + (float16_t)0.752176850f, (float16_t)-0.658961293f, + (float16_t)0.751165132f, (float16_t)-0.660114342f, + (float16_t)0.750151646f, (float16_t)-0.661265838f, + (float16_t)0.749136395f, (float16_t)-0.662415778f, + (float16_t)0.748119380f, (float16_t)-0.663564159f, + (float16_t)0.747100606f, (float16_t)-0.664710978f, + (float16_t)0.746080074f, (float16_t)-0.665856234f, + (float16_t)0.745057785f, (float16_t)-0.666999922f, + (float16_t)0.744033744f, (float16_t)-0.668142041f, + (float16_t)0.743007952f, (float16_t)-0.669282588f, + (float16_t)0.741980412f, (float16_t)-0.670421560f, + (float16_t)0.740951125f, (float16_t)-0.671558955f, + (float16_t)0.739920095f, (float16_t)-0.672694769f, + (float16_t)0.738887324f, (float16_t)-0.673829000f, + (float16_t)0.737852815f, (float16_t)-0.674961646f, + (float16_t)0.736816569f, (float16_t)-0.676092704f, + (float16_t)0.735778589f, (float16_t)-0.677222170f, + (float16_t)0.734738878f, (float16_t)-0.678350043f, + (float16_t)0.733697438f, (float16_t)-0.679476320f, + (float16_t)0.732654272f, (float16_t)-0.680600998f, + (float16_t)0.731609381f, (float16_t)-0.681724074f, + (float16_t)0.730562769f, (float16_t)-0.682845546f, + (float16_t)0.729514438f, (float16_t)-0.683965412f, + (float16_t)0.728464390f, (float16_t)-0.685083668f, + (float16_t)0.727412629f, (float16_t)-0.686200312f, + (float16_t)0.726359155f, (float16_t)-0.687315341f, + (float16_t)0.725303972f, (float16_t)-0.688428753f, + (float16_t)0.724247083f, (float16_t)-0.689540545f, + (float16_t)0.723188489f, (float16_t)-0.690650714f, + (float16_t)0.722128194f, (float16_t)-0.691759258f, + (float16_t)0.721066199f, (float16_t)-0.692866175f, + (float16_t)0.720002508f, (float16_t)-0.693971461f, + (float16_t)0.718937122f, (float16_t)-0.695075114f, + (float16_t)0.717870045f, (float16_t)-0.696177131f, + (float16_t)0.716801279f, (float16_t)-0.697277511f, + (float16_t)0.715730825f, (float16_t)-0.698376249f, + (float16_t)0.714658688f, (float16_t)-0.699473345f, + (float16_t)0.713584869f, (float16_t)-0.700568794f, + (float16_t)0.712509371f, (float16_t)-0.701662595f, + (float16_t)0.711432196f, (float16_t)-0.702754744f, + (float16_t)0.710353347f, (float16_t)-0.703845241f, + (float16_t)0.709272826f, (float16_t)-0.704934080f, + (float16_t)0.708190637f, (float16_t)-0.706021261f, + (float16_t)0.707106781f, (float16_t)-0.707106781f, + (float16_t)0.706021261f, (float16_t)-0.708190637f, + (float16_t)0.704934080f, (float16_t)-0.709272826f, + (float16_t)0.703845241f, (float16_t)-0.710353347f, + (float16_t)0.702754744f, (float16_t)-0.711432196f, + (float16_t)0.701662595f, (float16_t)-0.712509371f, + (float16_t)0.700568794f, (float16_t)-0.713584869f, + (float16_t)0.699473345f, (float16_t)-0.714658688f, + (float16_t)0.698376249f, (float16_t)-0.715730825f, + (float16_t)0.697277511f, (float16_t)-0.716801279f, + (float16_t)0.696177131f, (float16_t)-0.717870045f, + (float16_t)0.695075114f, (float16_t)-0.718937122f, + (float16_t)0.693971461f, (float16_t)-0.720002508f, + (float16_t)0.692866175f, (float16_t)-0.721066199f, + (float16_t)0.691759258f, (float16_t)-0.722128194f, + (float16_t)0.690650714f, (float16_t)-0.723188489f, + (float16_t)0.689540545f, (float16_t)-0.724247083f, + (float16_t)0.688428753f, (float16_t)-0.725303972f, + (float16_t)0.687315341f, (float16_t)-0.726359155f, + (float16_t)0.686200312f, (float16_t)-0.727412629f, + (float16_t)0.685083668f, (float16_t)-0.728464390f, + (float16_t)0.683965412f, (float16_t)-0.729514438f, + (float16_t)0.682845546f, (float16_t)-0.730562769f, + (float16_t)0.681724074f, (float16_t)-0.731609381f, + (float16_t)0.680600998f, (float16_t)-0.732654272f, + (float16_t)0.679476320f, (float16_t)-0.733697438f, + (float16_t)0.678350043f, (float16_t)-0.734738878f, + (float16_t)0.677222170f, (float16_t)-0.735778589f, + (float16_t)0.676092704f, (float16_t)-0.736816569f, + (float16_t)0.674961646f, (float16_t)-0.737852815f, + (float16_t)0.673829000f, (float16_t)-0.738887324f, + (float16_t)0.672694769f, (float16_t)-0.739920095f, + (float16_t)0.671558955f, (float16_t)-0.740951125f, + (float16_t)0.670421560f, (float16_t)-0.741980412f, + (float16_t)0.669282588f, (float16_t)-0.743007952f, + (float16_t)0.668142041f, (float16_t)-0.744033744f, + (float16_t)0.666999922f, (float16_t)-0.745057785f, + (float16_t)0.665856234f, (float16_t)-0.746080074f, + (float16_t)0.664710978f, (float16_t)-0.747100606f, + (float16_t)0.663564159f, (float16_t)-0.748119380f, + (float16_t)0.662415778f, (float16_t)-0.749136395f, + (float16_t)0.661265838f, (float16_t)-0.750151646f, + (float16_t)0.660114342f, (float16_t)-0.751165132f, + (float16_t)0.658961293f, (float16_t)-0.752176850f, + (float16_t)0.657806693f, (float16_t)-0.753186799f, + (float16_t)0.656650546f, (float16_t)-0.754194975f, + (float16_t)0.655492853f, (float16_t)-0.755201377f, + (float16_t)0.654333618f, (float16_t)-0.756206001f, + (float16_t)0.653172843f, (float16_t)-0.757208847f, + (float16_t)0.652010531f, (float16_t)-0.758209910f, + (float16_t)0.650846685f, (float16_t)-0.759209189f, + (float16_t)0.649681307f, (float16_t)-0.760206682f, + (float16_t)0.648514401f, (float16_t)-0.761202385f, + (float16_t)0.647345969f, (float16_t)-0.762196298f, + (float16_t)0.646176013f, (float16_t)-0.763188417f, + (float16_t)0.645004537f, (float16_t)-0.764178741f, + (float16_t)0.643831543f, (float16_t)-0.765167266f, + (float16_t)0.642657034f, (float16_t)-0.766153990f, + (float16_t)0.641481013f, (float16_t)-0.767138912f, + (float16_t)0.640303482f, (float16_t)-0.768122029f, + (float16_t)0.639124445f, (float16_t)-0.769103338f, + (float16_t)0.637943904f, (float16_t)-0.770082837f, + (float16_t)0.636761861f, (float16_t)-0.771060524f, + (float16_t)0.635578320f, (float16_t)-0.772036397f, + (float16_t)0.634393284f, (float16_t)-0.773010453f, + (float16_t)0.633206755f, (float16_t)-0.773982691f, + (float16_t)0.632018736f, (float16_t)-0.774953107f, + (float16_t)0.630829230f, (float16_t)-0.775921699f, + (float16_t)0.629638239f, (float16_t)-0.776888466f, + (float16_t)0.628445767f, (float16_t)-0.777853404f, + (float16_t)0.627251815f, (float16_t)-0.778816512f, + (float16_t)0.626056388f, (float16_t)-0.779777788f, + (float16_t)0.624859488f, (float16_t)-0.780737229f, + (float16_t)0.623661118f, (float16_t)-0.781694832f, + (float16_t)0.622461279f, (float16_t)-0.782650596f, + (float16_t)0.621259977f, (float16_t)-0.783604519f, + (float16_t)0.620057212f, (float16_t)-0.784556597f, + (float16_t)0.618852988f, (float16_t)-0.785506830f, + (float16_t)0.617647308f, (float16_t)-0.786455214f, + (float16_t)0.616440175f, (float16_t)-0.787401747f, + (float16_t)0.615231591f, (float16_t)-0.788346428f, + (float16_t)0.614021559f, (float16_t)-0.789289253f, + (float16_t)0.612810082f, (float16_t)-0.790230221f, + (float16_t)0.611597164f, (float16_t)-0.791169330f, + (float16_t)0.610382806f, (float16_t)-0.792106577f, + (float16_t)0.609167012f, (float16_t)-0.793041960f, + (float16_t)0.607949785f, (float16_t)-0.793975478f, + (float16_t)0.606731127f, (float16_t)-0.794907126f, + (float16_t)0.605511041f, (float16_t)-0.795836905f, + (float16_t)0.604289531f, (float16_t)-0.796764810f, + (float16_t)0.603066599f, (float16_t)-0.797690841f, + (float16_t)0.601842247f, (float16_t)-0.798614995f, + (float16_t)0.600616479f, (float16_t)-0.799537269f, + (float16_t)0.599389298f, (float16_t)-0.800457662f, + (float16_t)0.598160707f, (float16_t)-0.801376172f, + (float16_t)0.596930708f, (float16_t)-0.802292796f, + (float16_t)0.595699304f, (float16_t)-0.803207531f, + (float16_t)0.594466499f, (float16_t)-0.804120377f, + (float16_t)0.593232295f, (float16_t)-0.805031331f, + (float16_t)0.591996695f, (float16_t)-0.805940391f, + (float16_t)0.590759702f, (float16_t)-0.806847554f, + (float16_t)0.589521319f, (float16_t)-0.807752818f, + (float16_t)0.588281548f, (float16_t)-0.808656182f, + (float16_t)0.587040394f, (float16_t)-0.809557642f, + (float16_t)0.585797857f, (float16_t)-0.810457198f, + (float16_t)0.584553943f, (float16_t)-0.811354847f, + (float16_t)0.583308653f, (float16_t)-0.812250587f, + (float16_t)0.582061990f, (float16_t)-0.813144415f, + (float16_t)0.580813958f, (float16_t)-0.814036330f, + (float16_t)0.579564559f, (float16_t)-0.814926329f, + (float16_t)0.578313796f, (float16_t)-0.815814411f, + (float16_t)0.577061673f, (float16_t)-0.816700573f, + (float16_t)0.575808191f, (float16_t)-0.817584813f, + (float16_t)0.574553355f, (float16_t)-0.818467130f, + (float16_t)0.573297167f, (float16_t)-0.819347520f, + (float16_t)0.572039629f, (float16_t)-0.820225983f, + (float16_t)0.570780746f, (float16_t)-0.821102515f, + (float16_t)0.569520519f, (float16_t)-0.821977115f, + (float16_t)0.568258953f, (float16_t)-0.822849781f, + (float16_t)0.566996049f, (float16_t)-0.823720511f, + (float16_t)0.565731811f, (float16_t)-0.824589303f, + (float16_t)0.564466242f, (float16_t)-0.825456154f, + (float16_t)0.563199344f, (float16_t)-0.826321063f, + (float16_t)0.561931121f, (float16_t)-0.827184027f, + (float16_t)0.560661576f, (float16_t)-0.828045045f, + (float16_t)0.559390712f, (float16_t)-0.828904115f, + (float16_t)0.558118531f, (float16_t)-0.829761234f, + (float16_t)0.556845037f, (float16_t)-0.830616400f, + (float16_t)0.555570233f, (float16_t)-0.831469612f, + (float16_t)0.554294121f, (float16_t)-0.832320868f, + (float16_t)0.553016706f, (float16_t)-0.833170165f, + (float16_t)0.551737988f, (float16_t)-0.834017501f, + (float16_t)0.550457973f, (float16_t)-0.834862875f, + (float16_t)0.549176662f, (float16_t)-0.835706284f, + (float16_t)0.547894059f, (float16_t)-0.836547727f, + (float16_t)0.546610167f, (float16_t)-0.837387202f, + (float16_t)0.545324988f, (float16_t)-0.838224706f, + (float16_t)0.544038527f, (float16_t)-0.839060237f, + (float16_t)0.542750785f, (float16_t)-0.839893794f, + (float16_t)0.541461766f, (float16_t)-0.840725375f, + (float16_t)0.540171473f, (float16_t)-0.841554977f, + (float16_t)0.538879909f, (float16_t)-0.842382600f, + (float16_t)0.537587076f, (float16_t)-0.843208240f, + (float16_t)0.536292979f, (float16_t)-0.844031895f, + (float16_t)0.534997620f, (float16_t)-0.844853565f, + (float16_t)0.533701002f, (float16_t)-0.845673247f, + (float16_t)0.532403128f, (float16_t)-0.846490939f, + (float16_t)0.531104001f, (float16_t)-0.847306639f, + (float16_t)0.529803625f, (float16_t)-0.848120345f, + (float16_t)0.528502002f, (float16_t)-0.848932055f, + (float16_t)0.527199135f, (float16_t)-0.849741768f, + (float16_t)0.525895027f, (float16_t)-0.850549481f, + (float16_t)0.524589683f, (float16_t)-0.851355193f, + (float16_t)0.523283103f, (float16_t)-0.852158902f, + (float16_t)0.521975293f, (float16_t)-0.852960605f, + (float16_t)0.520666254f, (float16_t)-0.853760301f, + (float16_t)0.519355990f, (float16_t)-0.854557988f, + (float16_t)0.518044504f, (float16_t)-0.855353665f, + (float16_t)0.516731799f, (float16_t)-0.856147328f, + (float16_t)0.515417878f, (float16_t)-0.856938977f, + (float16_t)0.514102744f, (float16_t)-0.857728610f, + (float16_t)0.512786401f, (float16_t)-0.858516224f, + (float16_t)0.511468850f, (float16_t)-0.859301818f, + (float16_t)0.510150097f, (float16_t)-0.860085390f, + (float16_t)0.508830143f, (float16_t)-0.860866939f, + (float16_t)0.507508991f, (float16_t)-0.861646461f, + (float16_t)0.506186645f, (float16_t)-0.862423956f, + (float16_t)0.504863109f, (float16_t)-0.863199422f, + (float16_t)0.503538384f, (float16_t)-0.863972856f, + (float16_t)0.502212474f, (float16_t)-0.864744258f, + (float16_t)0.500885383f, (float16_t)-0.865513624f, + (float16_t)0.499557113f, (float16_t)-0.866280954f, + (float16_t)0.498227667f, (float16_t)-0.867046246f, + (float16_t)0.496897049f, (float16_t)-0.867809497f, + (float16_t)0.495565262f, (float16_t)-0.868570706f, + (float16_t)0.494232309f, (float16_t)-0.869329871f, + (float16_t)0.492898192f, (float16_t)-0.870086991f, + (float16_t)0.491562916f, (float16_t)-0.870842063f, + (float16_t)0.490226483f, (float16_t)-0.871595087f, + (float16_t)0.488888897f, (float16_t)-0.872346059f, + (float16_t)0.487550160f, (float16_t)-0.873094978f, + (float16_t)0.486210276f, (float16_t)-0.873841843f, + (float16_t)0.484869248f, (float16_t)-0.874586652f, + (float16_t)0.483527079f, (float16_t)-0.875329403f, + (float16_t)0.482183772f, (float16_t)-0.876070094f, + (float16_t)0.480839331f, (float16_t)-0.876808724f, + (float16_t)0.479493758f, (float16_t)-0.877545290f, + (float16_t)0.478147056f, (float16_t)-0.878279792f, + (float16_t)0.476799230f, (float16_t)-0.879012226f, + (float16_t)0.475450282f, (float16_t)-0.879742593f, + (float16_t)0.474100215f, (float16_t)-0.880470889f, + (float16_t)0.472749032f, (float16_t)-0.881197113f, + (float16_t)0.471396737f, (float16_t)-0.881921264f, + (float16_t)0.470043332f, (float16_t)-0.882643340f, + (float16_t)0.468688822f, (float16_t)-0.883363339f, + (float16_t)0.467333209f, (float16_t)-0.884081259f, + (float16_t)0.465976496f, (float16_t)-0.884797098f, + (float16_t)0.464618686f, (float16_t)-0.885510856f, + (float16_t)0.463259784f, (float16_t)-0.886222530f, + (float16_t)0.461899791f, (float16_t)-0.886932119f, + (float16_t)0.460538711f, (float16_t)-0.887639620f, + (float16_t)0.459176548f, (float16_t)-0.888345033f, + (float16_t)0.457813304f, (float16_t)-0.889048356f, + (float16_t)0.456448982f, (float16_t)-0.889749586f, + (float16_t)0.455083587f, (float16_t)-0.890448723f, + (float16_t)0.453717121f, (float16_t)-0.891145765f, + (float16_t)0.452349587f, (float16_t)-0.891840709f, + (float16_t)0.450980989f, (float16_t)-0.892533555f, + (float16_t)0.449611330f, (float16_t)-0.893224301f, + (float16_t)0.448240612f, (float16_t)-0.893912945f, + (float16_t)0.446868840f, (float16_t)-0.894599486f, + (float16_t)0.445496017f, (float16_t)-0.895283921f, + (float16_t)0.444122145f, (float16_t)-0.895966250f, + (float16_t)0.442747228f, (float16_t)-0.896646470f, + (float16_t)0.441371269f, (float16_t)-0.897324581f, + (float16_t)0.439994271f, (float16_t)-0.898000580f, + (float16_t)0.438616239f, (float16_t)-0.898674466f, + (float16_t)0.437237174f, (float16_t)-0.899346237f, + (float16_t)0.435857080f, (float16_t)-0.900015892f, + (float16_t)0.434475961f, (float16_t)-0.900683429f, + (float16_t)0.433093819f, (float16_t)-0.901348847f, + (float16_t)0.431710658f, (float16_t)-0.902012144f, + (float16_t)0.430326481f, (float16_t)-0.902673318f, + (float16_t)0.428941292f, (float16_t)-0.903332368f, + (float16_t)0.427555093f, (float16_t)-0.903989293f, + (float16_t)0.426167889f, (float16_t)-0.904644091f, + (float16_t)0.424779681f, (float16_t)-0.905296759f, + (float16_t)0.423390474f, (float16_t)-0.905947298f, + (float16_t)0.422000271f, (float16_t)-0.906595705f, + (float16_t)0.420609074f, (float16_t)-0.907241978f, + (float16_t)0.419216888f, (float16_t)-0.907886116f, + (float16_t)0.417823716f, (float16_t)-0.908528119f, + (float16_t)0.416429560f, (float16_t)-0.909167983f, + (float16_t)0.415034424f, (float16_t)-0.909805708f, + (float16_t)0.413638312f, (float16_t)-0.910441292f, + (float16_t)0.412241227f, (float16_t)-0.911074734f, + (float16_t)0.410843171f, (float16_t)-0.911706032f, + (float16_t)0.409444149f, (float16_t)-0.912335185f, + (float16_t)0.408044163f, (float16_t)-0.912962190f, + (float16_t)0.406643217f, (float16_t)-0.913587048f, + (float16_t)0.405241314f, (float16_t)-0.914209756f, + (float16_t)0.403838458f, (float16_t)-0.914830312f, + (float16_t)0.402434651f, (float16_t)-0.915448716f, + (float16_t)0.401029897f, (float16_t)-0.916064966f, + (float16_t)0.399624200f, (float16_t)-0.916679060f, + (float16_t)0.398217562f, (float16_t)-0.917290997f, + (float16_t)0.396809987f, (float16_t)-0.917900776f, + (float16_t)0.395401479f, (float16_t)-0.918508394f, + (float16_t)0.393992040f, (float16_t)-0.919113852f, + (float16_t)0.392581674f, (float16_t)-0.919717146f, + (float16_t)0.391170384f, (float16_t)-0.920318277f, + (float16_t)0.389758174f, (float16_t)-0.920917242f, + (float16_t)0.388345047f, (float16_t)-0.921514039f, + (float16_t)0.386931006f, (float16_t)-0.922108669f, + (float16_t)0.385516054f, (float16_t)-0.922701128f, + (float16_t)0.384100195f, (float16_t)-0.923291417f, + (float16_t)0.382683432f, (float16_t)-0.923879533f, + (float16_t)0.381265769f, (float16_t)-0.924465474f, + (float16_t)0.379847209f, (float16_t)-0.925049241f, + (float16_t)0.378427755f, (float16_t)-0.925630831f, + (float16_t)0.377007410f, (float16_t)-0.926210242f, + (float16_t)0.375586178f, (float16_t)-0.926787474f, + (float16_t)0.374164063f, (float16_t)-0.927362526f, + (float16_t)0.372741067f, (float16_t)-0.927935395f, + (float16_t)0.371317194f, (float16_t)-0.928506080f, + (float16_t)0.369892447f, (float16_t)-0.929074581f, + (float16_t)0.368466830f, (float16_t)-0.929640896f, + (float16_t)0.367040346f, (float16_t)-0.930205023f, + (float16_t)0.365612998f, (float16_t)-0.930766961f, + (float16_t)0.364184790f, (float16_t)-0.931326709f, + (float16_t)0.362755724f, (float16_t)-0.931884266f, + (float16_t)0.361325806f, (float16_t)-0.932439629f, + (float16_t)0.359895037f, (float16_t)-0.932992799f, + (float16_t)0.358463421f, (float16_t)-0.933543773f, + (float16_t)0.357030961f, (float16_t)-0.934092550f, + (float16_t)0.355597662f, (float16_t)-0.934639130f, + (float16_t)0.354163525f, (float16_t)-0.935183510f, + (float16_t)0.352728556f, (float16_t)-0.935725689f, + (float16_t)0.351292756f, (float16_t)-0.936265667f, + (float16_t)0.349856130f, (float16_t)-0.936803442f, + (float16_t)0.348418680f, (float16_t)-0.937339012f, + (float16_t)0.346980411f, (float16_t)-0.937872376f, + (float16_t)0.345541325f, (float16_t)-0.938403534f, + (float16_t)0.344101426f, (float16_t)-0.938932484f, + (float16_t)0.342660717f, (float16_t)-0.939459224f, + (float16_t)0.341219202f, (float16_t)-0.939983753f, + (float16_t)0.339776884f, (float16_t)-0.940506071f, + (float16_t)0.338333767f, (float16_t)-0.941026175f, + (float16_t)0.336889853f, (float16_t)-0.941544065f, + (float16_t)0.335445147f, (float16_t)-0.942059740f, + (float16_t)0.333999651f, (float16_t)-0.942573198f, + (float16_t)0.332553370f, (float16_t)-0.943084437f, + (float16_t)0.331106306f, (float16_t)-0.943593458f, + (float16_t)0.329658463f, (float16_t)-0.944100258f, + (float16_t)0.328209844f, (float16_t)-0.944604837f, + (float16_t)0.326760452f, (float16_t)-0.945107193f, + (float16_t)0.325310292f, (float16_t)-0.945607325f, + (float16_t)0.323859367f, (float16_t)-0.946105232f, + (float16_t)0.322407679f, (float16_t)-0.946600913f, + (float16_t)0.320955232f, (float16_t)-0.947094366f, + (float16_t)0.319502031f, (float16_t)-0.947585591f, + (float16_t)0.318048077f, (float16_t)-0.948074586f, + (float16_t)0.316593376f, (float16_t)-0.948561350f, + (float16_t)0.315137929f, (float16_t)-0.949045882f, + (float16_t)0.313681740f, (float16_t)-0.949528181f, + (float16_t)0.312224814f, (float16_t)-0.950008245f, + (float16_t)0.310767153f, (float16_t)-0.950486074f, + (float16_t)0.309308760f, (float16_t)-0.950961666f, + (float16_t)0.307849640f, (float16_t)-0.951435021f, + (float16_t)0.306389795f, (float16_t)-0.951906137f, + (float16_t)0.304929230f, (float16_t)-0.952375013f, + (float16_t)0.303467947f, (float16_t)-0.952841648f, + (float16_t)0.302005949f, (float16_t)-0.953306040f, + (float16_t)0.300543241f, (float16_t)-0.953768190f, + (float16_t)0.299079826f, (float16_t)-0.954228095f, + (float16_t)0.297615707f, (float16_t)-0.954685755f, + (float16_t)0.296150888f, (float16_t)-0.955141168f, + (float16_t)0.294685372f, (float16_t)-0.955594334f, + (float16_t)0.293219163f, (float16_t)-0.956045251f, + (float16_t)0.291752263f, (float16_t)-0.956493919f, + (float16_t)0.290284677f, (float16_t)-0.956940336f, + (float16_t)0.288816408f, (float16_t)-0.957384501f, + (float16_t)0.287347460f, (float16_t)-0.957826413f, + (float16_t)0.285877835f, (float16_t)-0.958266071f, + (float16_t)0.284407537f, (float16_t)-0.958703475f, + (float16_t)0.282936570f, (float16_t)-0.959138622f, + (float16_t)0.281464938f, (float16_t)-0.959571513f, + (float16_t)0.279992643f, (float16_t)-0.960002146f, + (float16_t)0.278519689f, (float16_t)-0.960430519f, + (float16_t)0.277046080f, (float16_t)-0.960856633f, + (float16_t)0.275571819f, (float16_t)-0.961280486f, + (float16_t)0.274096910f, (float16_t)-0.961702077f, + (float16_t)0.272621355f, (float16_t)-0.962121404f, + (float16_t)0.271145160f, (float16_t)-0.962538468f, + (float16_t)0.269668326f, (float16_t)-0.962953267f, + (float16_t)0.268190857f, (float16_t)-0.963365800f, + (float16_t)0.266712757f, (float16_t)-0.963776066f, + (float16_t)0.265234030f, (float16_t)-0.964184064f, + (float16_t)0.263754679f, (float16_t)-0.964589793f, + (float16_t)0.262274707f, (float16_t)-0.964993253f, + (float16_t)0.260794118f, (float16_t)-0.965394442f, + (float16_t)0.259312915f, (float16_t)-0.965793359f, + (float16_t)0.257831102f, (float16_t)-0.966190003f, + (float16_t)0.256348682f, (float16_t)-0.966584374f, + (float16_t)0.254865660f, (float16_t)-0.966976471f, + (float16_t)0.253382037f, (float16_t)-0.967366292f, + (float16_t)0.251897818f, (float16_t)-0.967753837f, + (float16_t)0.250413007f, (float16_t)-0.968139105f, + (float16_t)0.248927606f, (float16_t)-0.968522094f, + (float16_t)0.247441619f, (float16_t)-0.968902805f, + (float16_t)0.245955050f, (float16_t)-0.969281235f, + (float16_t)0.244467903f, (float16_t)-0.969657385f, + (float16_t)0.242980180f, (float16_t)-0.970031253f, + (float16_t)0.241491885f, (float16_t)-0.970402839f, + (float16_t)0.240003022f, (float16_t)-0.970772141f, + (float16_t)0.238513595f, (float16_t)-0.971139158f, + (float16_t)0.237023606f, (float16_t)-0.971503891f, + (float16_t)0.235533059f, (float16_t)-0.971866337f, + (float16_t)0.234041959f, (float16_t)-0.972226497f, + (float16_t)0.232550307f, (float16_t)-0.972584369f, + (float16_t)0.231058108f, (float16_t)-0.972939952f, + (float16_t)0.229565366f, (float16_t)-0.973293246f, + (float16_t)0.228072083f, (float16_t)-0.973644250f, + (float16_t)0.226578264f, (float16_t)-0.973992962f, + (float16_t)0.225083911f, (float16_t)-0.974339383f, + (float16_t)0.223589029f, (float16_t)-0.974683511f, + (float16_t)0.222093621f, (float16_t)-0.975025345f, + (float16_t)0.220597690f, (float16_t)-0.975364885f, + (float16_t)0.219101240f, (float16_t)-0.975702130f, + (float16_t)0.217604275f, (float16_t)-0.976037079f, + (float16_t)0.216106797f, (float16_t)-0.976369731f, + (float16_t)0.214608811f, (float16_t)-0.976700086f, + (float16_t)0.213110320f, (float16_t)-0.977028143f, + (float16_t)0.211611327f, (float16_t)-0.977353900f, + (float16_t)0.210111837f, (float16_t)-0.977677358f, + (float16_t)0.208611852f, (float16_t)-0.977998515f, + (float16_t)0.207111376f, (float16_t)-0.978317371f, + (float16_t)0.205610413f, (float16_t)-0.978633924f, + (float16_t)0.204108966f, (float16_t)-0.978948175f, + (float16_t)0.202607039f, (float16_t)-0.979260123f, + (float16_t)0.201104635f, (float16_t)-0.979569766f, + (float16_t)0.199601758f, (float16_t)-0.979877104f, + (float16_t)0.198098411f, (float16_t)-0.980182136f, + (float16_t)0.196594598f, (float16_t)-0.980484862f, + (float16_t)0.195090322f, (float16_t)-0.980785280f, + (float16_t)0.193585587f, (float16_t)-0.981083391f, + (float16_t)0.192080397f, (float16_t)-0.981379193f, + (float16_t)0.190574755f, (float16_t)-0.981672686f, + (float16_t)0.189068664f, (float16_t)-0.981963869f, + (float16_t)0.187562129f, (float16_t)-0.982252741f, + (float16_t)0.186055152f, (float16_t)-0.982539302f, + (float16_t)0.184547737f, (float16_t)-0.982823551f, + (float16_t)0.183039888f, (float16_t)-0.983105487f, + (float16_t)0.181531608f, (float16_t)-0.983385110f, + (float16_t)0.180022901f, (float16_t)-0.983662419f, + (float16_t)0.178513771f, (float16_t)-0.983937413f, + (float16_t)0.177004220f, (float16_t)-0.984210092f, + (float16_t)0.175494253f, (float16_t)-0.984480455f, + (float16_t)0.173983873f, (float16_t)-0.984748502f, + (float16_t)0.172473084f, (float16_t)-0.985014231f, + (float16_t)0.170961889f, (float16_t)-0.985277642f, + (float16_t)0.169450291f, (float16_t)-0.985538735f, + (float16_t)0.167938295f, (float16_t)-0.985797509f, + (float16_t)0.166425904f, (float16_t)-0.986053963f, + (float16_t)0.164913120f, (float16_t)-0.986308097f, + (float16_t)0.163399949f, (float16_t)-0.986559910f, + (float16_t)0.161886394f, (float16_t)-0.986809402f, + (float16_t)0.160372457f, (float16_t)-0.987056571f, + (float16_t)0.158858143f, (float16_t)-0.987301418f, + (float16_t)0.157343456f, (float16_t)-0.987543942f, + (float16_t)0.155828398f, (float16_t)-0.987784142f, + (float16_t)0.154312973f, (float16_t)-0.988022017f, + (float16_t)0.152797185f, (float16_t)-0.988257568f, + (float16_t)0.151281038f, (float16_t)-0.988490793f, + (float16_t)0.149764535f, (float16_t)-0.988721692f, + (float16_t)0.148247679f, (float16_t)-0.988950265f, + (float16_t)0.146730474f, (float16_t)-0.989176510f, + (float16_t)0.145212925f, (float16_t)-0.989400428f, + (float16_t)0.143695033f, (float16_t)-0.989622017f, + (float16_t)0.142176804f, (float16_t)-0.989841278f, + (float16_t)0.140658239f, (float16_t)-0.990058210f, + (float16_t)0.139139344f, (float16_t)-0.990272812f, + (float16_t)0.137620122f, (float16_t)-0.990485084f, + (float16_t)0.136100575f, (float16_t)-0.990695025f, + (float16_t)0.134580709f, (float16_t)-0.990902635f, + (float16_t)0.133060525f, (float16_t)-0.991107914f, + (float16_t)0.131540029f, (float16_t)-0.991310860f, + (float16_t)0.130019223f, (float16_t)-0.991511473f, + (float16_t)0.128498111f, (float16_t)-0.991709754f, + (float16_t)0.126976696f, (float16_t)-0.991905700f, + (float16_t)0.125454983f, (float16_t)-0.992099313f, + (float16_t)0.123932975f, (float16_t)-0.992290591f, + (float16_t)0.122410675f, (float16_t)-0.992479535f, + (float16_t)0.120888087f, (float16_t)-0.992666142f, + (float16_t)0.119365215f, (float16_t)-0.992850414f, + (float16_t)0.117842062f, (float16_t)-0.993032350f, + (float16_t)0.116318631f, (float16_t)-0.993211949f, + (float16_t)0.114794927f, (float16_t)-0.993389211f, + (float16_t)0.113270952f, (float16_t)-0.993564136f, + (float16_t)0.111746711f, (float16_t)-0.993736722f, + (float16_t)0.110222207f, (float16_t)-0.993906970f, + (float16_t)0.108697444f, (float16_t)-0.994074879f, + (float16_t)0.107172425f, (float16_t)-0.994240449f, + (float16_t)0.105647154f, (float16_t)-0.994403680f, + (float16_t)0.104121634f, (float16_t)-0.994564571f, + (float16_t)0.102595869f, (float16_t)-0.994723121f, + (float16_t)0.101069863f, (float16_t)-0.994879331f, + (float16_t)0.099543619f, (float16_t)-0.995033199f, + (float16_t)0.098017140f, (float16_t)-0.995184727f, + (float16_t)0.096490431f, (float16_t)-0.995333912f, + (float16_t)0.094963495f, (float16_t)-0.995480755f, + (float16_t)0.093436336f, (float16_t)-0.995625256f, + (float16_t)0.091908956f, (float16_t)-0.995767414f, + (float16_t)0.090381361f, (float16_t)-0.995907229f, + (float16_t)0.088853553f, (float16_t)-0.996044701f, + (float16_t)0.087325535f, (float16_t)-0.996179829f, + (float16_t)0.085797312f, (float16_t)-0.996312612f, + (float16_t)0.084268888f, (float16_t)-0.996443051f, + (float16_t)0.082740265f, (float16_t)-0.996571146f, + (float16_t)0.081211447f, (float16_t)-0.996696895f, + (float16_t)0.079682438f, (float16_t)-0.996820299f, + (float16_t)0.078153242f, (float16_t)-0.996941358f, + (float16_t)0.076623861f, (float16_t)-0.997060070f, + (float16_t)0.075094301f, (float16_t)-0.997176437f, + (float16_t)0.073564564f, (float16_t)-0.997290457f, + (float16_t)0.072034653f, (float16_t)-0.997402130f, + (float16_t)0.070504573f, (float16_t)-0.997511456f, + (float16_t)0.068974328f, (float16_t)-0.997618435f, + (float16_t)0.067443920f, (float16_t)-0.997723067f, + (float16_t)0.065913353f, (float16_t)-0.997825350f, + (float16_t)0.064382631f, (float16_t)-0.997925286f, + (float16_t)0.062851758f, (float16_t)-0.998022874f, + (float16_t)0.061320736f, (float16_t)-0.998118113f, + (float16_t)0.059789571f, (float16_t)-0.998211003f, + (float16_t)0.058258265f, (float16_t)-0.998301545f, + (float16_t)0.056726821f, (float16_t)-0.998389737f, + (float16_t)0.055195244f, (float16_t)-0.998475581f, + (float16_t)0.053663538f, (float16_t)-0.998559074f, + (float16_t)0.052131705f, (float16_t)-0.998640218f, + (float16_t)0.050599749f, (float16_t)-0.998719012f, + (float16_t)0.049067674f, (float16_t)-0.998795456f, + (float16_t)0.047535484f, (float16_t)-0.998869550f, + (float16_t)0.046003182f, (float16_t)-0.998941293f, + (float16_t)0.044470772f, (float16_t)-0.999010686f, + (float16_t)0.042938257f, (float16_t)-0.999077728f, + (float16_t)0.041405641f, (float16_t)-0.999142419f, + (float16_t)0.039872928f, (float16_t)-0.999204759f, + (float16_t)0.038340120f, (float16_t)-0.999264747f, + (float16_t)0.036807223f, (float16_t)-0.999322385f, + (float16_t)0.035274239f, (float16_t)-0.999377670f, + (float16_t)0.033741172f, (float16_t)-0.999430605f, + (float16_t)0.032208025f, (float16_t)-0.999481187f, + (float16_t)0.030674803f, (float16_t)-0.999529418f, + (float16_t)0.029141509f, (float16_t)-0.999575296f, + (float16_t)0.027608146f, (float16_t)-0.999618822f, + (float16_t)0.026074718f, (float16_t)-0.999659997f, + (float16_t)0.024541229f, (float16_t)-0.999698819f, + (float16_t)0.023007681f, (float16_t)-0.999735288f, + (float16_t)0.021474080f, (float16_t)-0.999769405f, + (float16_t)0.019940429f, (float16_t)-0.999801170f, + (float16_t)0.018406730f, (float16_t)-0.999830582f, + (float16_t)0.016872988f, (float16_t)-0.999857641f, + (float16_t)0.015339206f, (float16_t)-0.999882347f, + (float16_t)0.013805389f, (float16_t)-0.999904701f, + (float16_t)0.012271538f, (float16_t)-0.999924702f, + (float16_t)0.010737659f, (float16_t)-0.999942350f, + (float16_t)0.009203755f, (float16_t)-0.999957645f, + (float16_t)0.007669829f, (float16_t)-0.999970586f, + (float16_t)0.006135885f, (float16_t)-0.999981175f, + (float16_t)0.004601926f, (float16_t)-0.999989411f, + (float16_t)0.003067957f, (float16_t)-0.999995294f, + (float16_t)0.001533980f, (float16_t)-0.999998823f +}; + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALL_TABLES) */ + +#endif /*!defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)*/ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) +const float16_t exp_tab_f16[8] = { + (1.f16), + (0.0416598916054f16), + (0.500000596046f16), + (0.00138889f16), + (1.00000011921f16), + (0.00833693705499f16), + (0.166665703058f16), + (0.000195780929062f16), +}; + +const float16_t __logf_lut_f16[8] = { + -2.295614848256274f16, /*p0*/ + -2.470711633419806f16, /*p4*/ + -5.686926051100417f16, /*p2*/ + -0.165253547131978f16, /*p6*/ + +5.175912446351073f16, /*p1*/ + +0.844006986174912f16, /*p5*/ + +4.584458825456749f16, /*p3*/ + +0.014127821926000f16 /*p7*/ +}; + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + +#endif /* Not ARM AC5 */ + + +/** + @} end of CFFT_CIFFT group +*/ diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c new file mode 100644 index 0000000..aff3a13 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c @@ -0,0 +1,654 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types.h" +#include "arm_const_structs.h" + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +/* Floating-point structs */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len16 = { + 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len32 = { + 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len64 = { + 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len128 = { + 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len256 = { + 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len512 = { + 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024 = { + 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048 = { + 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096)) +const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096 = { + 4096, (const float64_t *)twiddleCoefF64_4096, armBitRevIndexTableF64_4096, ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH +}; +#endif + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len16 = { + 16, twiddleCoef_16_q31, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len32 = { + 32, twiddleCoef_32_q31, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len64 = { + 64, twiddleCoef_64_q31, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len128 = { + 128, twiddleCoef_128_q31, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len256 = { + 256, twiddleCoef_256_q31, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len512 = { + 512, twiddleCoef_512_q31, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024 = { + 1024, twiddleCoef_1024_q31, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048 = { + 2048, twiddleCoef_2048_q31, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096 = { + 4096, twiddleCoef_4096_q31, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len16 = { + 16, twiddleCoef_16_q15, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len32 = { + 32, twiddleCoef_32_q15, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len64 = { + 64, twiddleCoef_64_q15, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len128 = { + 128, twiddleCoef_128_q15, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len256 = { + 256, twiddleCoef_256_q15, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len512 = { + 512, twiddleCoef_512_q15, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024 = { + 1024, twiddleCoef_1024_q15, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048 = { + 2048, twiddleCoef_2048_q15, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096 = { + 4096, twiddleCoef_4096_q15, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + +/* Structure for real-value inputs */ +/* Double precision strucs */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len32 = { + { 16, (const float64_t *)twiddleCoefF64_16, armBitRevIndexTableF64_16, ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH }, + 32U, + (float64_t *)twiddleCoefF64_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len64 = { + { 32, (const float64_t *)twiddleCoefF64_32, armBitRevIndexTableF64_32, ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH }, + 64U, + (float64_t *)twiddleCoefF64_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len128 = { + { 64, (const float64_t *)twiddleCoefF64_64, armBitRevIndexTableF64_64, ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH }, + 128U, + (float64_t *)twiddleCoefF64_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len256 = { + { 128, (const float64_t *)twiddleCoefF64_128, armBitRevIndexTableF64_128, ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH }, + 256U, + (float64_t *)twiddleCoefF64_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len512 = { + { 256, (const float64_t *)twiddleCoefF64_256, armBitRevIndexTableF64_256, ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH }, + 512U, + (float64_t *)twiddleCoefF64_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len1024 = { + { 512, (const float64_t *)twiddleCoefF64_512, armBitRevIndexTableF64_512, ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH }, + 1024U, + (float64_t *)twiddleCoefF64_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len2048 = { + { 1024, (const float64_t *)twiddleCoefF64_1024, armBitRevIndexTableF64_1024, ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH }, + 2048U, + (float64_t *)twiddleCoefF64_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT64_4096) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +const arm_rfft_fast_instance_f64 arm_rfft_fast_sR_f64_len4096 = { + { 2048, (const float64_t *)twiddleCoefF64_2048, armBitRevIndexTableF64_2048, ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH }, + 4096U, + (float64_t *)twiddleCoefF64_rfft_4096 +}; +#endif + +/* Floating-point structs */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len32 = { + { 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE_16_TABLE_LENGTH }, + 32U, + (float32_t *)twiddleCoef_rfft_32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len64 = { + { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE_32_TABLE_LENGTH }, + 64U, + (float32_t *)twiddleCoef_rfft_64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len128 = { + { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE_64_TABLE_LENGTH }, + 128U, + (float32_t *)twiddleCoef_rfft_128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len256 = { + { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }, + 256U, + (float32_t *)twiddleCoef_rfft_256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len512 = { + { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }, + 512U, + (float32_t *)twiddleCoef_rfft_512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len1024 = { + { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }, + 1024U, + (float32_t *)twiddleCoef_rfft_1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len2048 = { + { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE_1024_TABLE_LENGTH }, + 2048U, + (float32_t *)twiddleCoef_rfft_2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +const arm_rfft_fast_instance_f32 arm_rfft_fast_sR_f32_len4096 = { + { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE_2048_TABLE_LENGTH }, + 4096U, + (float32_t *)twiddleCoef_rfft_4096 +}; +#endif + +#endif /* #if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + +/* Fixed-point structs */ +/* q31_t */ + +#if !defined(ARM_MATH_MVEI) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +Those structures cannot be used to initialize the MVE version of the FFT Q31 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f32 must be used. + + +*/ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len32 = { + 32U, + 0, + 1, + 256U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len64 = { + 64U, + 0, + 1, + 128U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len128 = { + 128U, + 0, + 1, + 64U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len256 = { + 256U, + 0, + 1, + 32U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len512 = { + 512U, + 0, + 1, + 16U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len1024 = { + 1024U, + 0, + 1, + 8U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len2048 = { + 2048U, + 0, + 1, + 4U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len4096 = { + 4096U, + 0, + 1, + 2U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q31) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q31 arm_rfft_sR_q31_len8192 = { + 8192U, + 0, + 1, + 1U, + (q31_t*)realCoefAQ31, + (q31_t*)realCoefBQ31, + &arm_cfft_sR_q31_len4096 +}; +#endif + + + +/* q15_t */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len32 = { + 32U, + 0, + 1, + 256U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len16 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len64 = { + 64U, + 0, + 1, + 128U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len32 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len128 = { + 128U, + 0, + 1, + 64U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len64 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len256 = { + 256U, + 0, + 1, + 32U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len128 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len512 = { + 512U, + 0, + 1, + 16U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len256 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len1024 = { + 1024U, + 0, + 1, + 8U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len512 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len2048 = { + 2048U, + 0, + 1, + 4U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len1024 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len4096 = { + 4096U, + 0, + 1, + 2U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len2048 +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_REALCOEF_Q15) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) +const arm_rfft_instance_q15 arm_rfft_sR_q15_len8192 = { + 8192U, + 0, + 1, + 1U, + (q15_t*)realCoefAQ15, + (q15_t*)realCoefBQ15, + &arm_cfft_sR_q15_len4096 +}; +#endif + +#endif /* !defined(ARM_MATH_MVEI) */ + + +#endif diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c new file mode 100644 index 0000000..c0a20e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs_f16.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs_f16.c + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() or arm_rfft_f32() functions. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math_types_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_const_structs_f16.h" + + +/* +ALLOW TABLE is true when config table is enabled and the Tramsform folder is included +for compilation. +*/ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +/* Floating-point structs */ +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) + + +/* + +Those structures cannot be used to initialize the MVE version of the FFT F32 instances. +So they are not compiled when MVE is defined. + +For the MVE version, the new arm_cfft_init_f16 must be used. + + +*/ + +#if !defined(__CC_ARM) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len16 = { + 16, twiddleCoefF16_16, armBitRevIndexTable_fixed_16, ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len32 = { + 32, twiddleCoefF16_32, armBitRevIndexTable_fixed_32, ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len64 = { + 64, twiddleCoefF16_64, armBitRevIndexTable_fixed_64, ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len128 = { + 128, twiddleCoefF16_128, armBitRevIndexTable_fixed_128, ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len256 = { + 256, twiddleCoefF16_256, armBitRevIndexTable_fixed_256, ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len512 = { + 512, twiddleCoefF16_512, armBitRevIndexTable_fixed_512, ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024 = { + 1024, twiddleCoefF16_1024, armBitRevIndexTable_fixed_1024, ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048 = { + 2048, twiddleCoefF16_2048, armBitRevIndexTable_fixed_2048, ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH +}; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) +const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096 = { + 4096, twiddleCoefF16_4096, armBitRevIndexTable_fixed_4096, ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH +}; +#endif +#endif + +#endif /* !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) */ + + +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c new file mode 100644 index 0000000..cae4bd8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables.c @@ -0,0 +1,6533 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "arm_math_types.h" + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]={ +0,0,}; + +float32_t rearranged_twiddle_stride1_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f, +0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f, +0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f, +0.70710676908493041992f,0.00000000000000006123f,1.00000000000000000000f, +-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_16_f32[8]={ +1.00000000000000000000f,0.00000000000000000000f,0.38268342614173889160f, +0.92387950420379638672f,-0.70710676908493041992f,0.70710676908493041992f, +-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]={ +0,32,0,}; + +float32_t rearranged_twiddle_stride1_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.99518471956253051758f, +0.09801714122295379639f,0.98078525066375732422f,0.19509032368659973145f, +0.95694035291671752930f,0.29028466343879699707f,0.92387950420379638672f, +0.38268342614173889160f,0.88192129135131835938f,0.47139674425125122070f, +0.83146959543228149414f,0.55557024478912353516f,0.77301043272018432617f, +0.63439327478408813477f,0.70710676908493041992f,0.70710676908493041992f, +0.63439327478408813477f,0.77301043272018432617f,0.55557024478912353516f, +0.83146959543228149414f,0.47139674425125122070f,0.88192129135131835938f, +0.38268342614173889160f,0.92387950420379638672f,0.29028466343879699707f, +0.95694035291671752930f,0.19509032368659973145f,0.98078525066375732422f, +0.09801714122295379639f,0.99518471956253051758f,1.00000000000000000000f, +0.00000000000000000000f,0.92387950420379638672f,0.38268342614173889160f, +0.70710676908493041992f,0.70710676908493041992f,0.38268342614173889160f, +0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.98078525066375732422f, +0.19509032368659973145f,0.92387950420379638672f,0.38268342614173889160f, +0.83146959543228149414f,0.55557024478912353516f,0.70710676908493041992f, +0.70710676908493041992f,0.55557024478912353516f,0.83146959543228149414f, +0.38268342614173889160f,0.92387950420379638672f,0.19509032368659973145f, +0.98078525066375732422f,0.00000000000000006123f,1.00000000000000000000f, +-0.19509032368659973145f,0.98078525066375732422f,-0.38268342614173889160f, +0.92387950420379638672f,-0.55557024478912353516f,0.83146959543228149414f, +-0.70710676908493041992f,0.70710676908493041992f,-0.83146959543228149414f, +0.55557024478912353516f,-0.92387950420379638672f,0.38268342614173889160f, +-0.98078525066375732422f,0.19509032368659973145f,1.00000000000000000000f, +0.00000000000000000000f,0.70710676908493041992f,0.70710676908493041992f, +0.00000000000000006123f,1.00000000000000000000f,-0.70710676908493041992f, +0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_64_f32[40]={ +1.00000000000000000000f,0.00000000000000000000f,0.95694035291671752930f, +0.29028466343879699707f,0.83146959543228149414f,0.55557024478912353516f, +0.63439327478408813477f,0.77301043272018432617f,0.38268342614173889160f, +0.92387950420379638672f,0.09801714122295379639f,0.99518471956253051758f, +-0.19509032368659973145f,0.98078525066375732422f,-0.47139674425125122070f, +0.88192129135131835938f,-0.70710676908493041992f,0.70710676908493041992f, +-0.88192129135131835938f,0.47139674425125122070f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]={ +0,128,160,0,}; + +float32_t rearranged_twiddle_stride1_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99969881772994995117f, +0.02454122900962829590f,0.99879544973373413086f,0.04906767606735229492f, +0.99729043245315551758f,0.07356456667184829712f,0.99518471956253051758f, +0.09801714122295379639f,0.99247956275939941406f,0.12241067737340927124f, +0.98917651176452636719f,0.14673046767711639404f,0.98527765274047851562f, +0.17096188664436340332f,0.98078525066375732422f,0.19509032368659973145f, +0.97570210695266723633f,0.21910123527050018311f,0.97003126144409179688f, +0.24298018217086791992f,0.96377605199813842773f,0.26671275496482849121f, +0.95694035291671752930f,0.29028466343879699707f,0.94952815771102905273f, +0.31368175148963928223f,0.94154405593872070312f,0.33688986301422119141f, +0.93299281597137451172f,0.35989505052566528320f,0.92387950420379638672f, +0.38268342614173889160f,0.91420978307723999023f,0.40524131059646606445f, +0.90398931503295898438f,0.42755508422851562500f,0.89322429895401000977f, +0.44961133599281311035f,0.88192129135131835938f,0.47139674425125122070f, +0.87008696794509887695f,0.49289819598197937012f,0.85772860050201416016f, +0.51410275697708129883f,0.84485357999801635742f,0.53499764204025268555f, +0.83146959543228149414f,0.55557024478912353516f,0.81758481264114379883f, +0.57580816745758056641f,0.80320751667022705078f,0.59569931030273437500f, +0.78834640979766845703f,0.61523157358169555664f,0.77301043272018432617f, +0.63439327478408813477f,0.75720882415771484375f,0.65317285060882568359f, +0.74095112085342407227f,0.67155897617340087891f,0.72424709796905517578f, +0.68954056501388549805f,0.70710676908493041992f,0.70710676908493041992f, +0.68954056501388549805f,0.72424709796905517578f,0.67155897617340087891f, +0.74095112085342407227f,0.65317285060882568359f,0.75720882415771484375f, +0.63439327478408813477f,0.77301043272018432617f,0.61523157358169555664f, +0.78834640979766845703f,0.59569931030273437500f,0.80320751667022705078f, +0.57580816745758056641f,0.81758481264114379883f,0.55557024478912353516f, +0.83146959543228149414f,0.53499764204025268555f,0.84485357999801635742f, +0.51410275697708129883f,0.85772860050201416016f,0.49289819598197937012f, +0.87008696794509887695f,0.47139674425125122070f,0.88192129135131835938f, +0.44961133599281311035f,0.89322429895401000977f,0.42755508422851562500f, +0.90398931503295898438f,0.40524131059646606445f,0.91420978307723999023f, +0.38268342614173889160f,0.92387950420379638672f,0.35989505052566528320f, +0.93299281597137451172f,0.33688986301422119141f,0.94154405593872070312f, +0.31368175148963928223f,0.94952815771102905273f,0.29028466343879699707f, +0.95694035291671752930f,0.26671275496482849121f,0.96377605199813842773f, +0.24298018217086791992f,0.97003126144409179688f,0.21910123527050018311f, +0.97570210695266723633f,0.19509032368659973145f,0.98078525066375732422f, +0.17096188664436340332f,0.98527765274047851562f,0.14673046767711639404f, +0.98917651176452636719f,0.12241067737340927124f,0.99247956275939941406f, +0.09801714122295379639f,0.99518471956253051758f,0.07356456667184829712f, +0.99729043245315551758f,0.04906767606735229492f,0.99879544973373413086f, +0.02454122900962829590f,0.99969881772994995117f,1.00000000000000000000f, +0.00000000000000000000f,0.99518471956253051758f,0.09801714122295379639f, +0.98078525066375732422f,0.19509032368659973145f,0.95694035291671752930f, +0.29028466343879699707f,0.92387950420379638672f,0.38268342614173889160f, +0.88192129135131835938f,0.47139674425125122070f,0.83146959543228149414f, +0.55557024478912353516f,0.77301043272018432617f,0.63439327478408813477f, +0.70710676908493041992f,0.70710676908493041992f,0.63439327478408813477f, +0.77301043272018432617f,0.55557024478912353516f,0.83146959543228149414f, +0.47139674425125122070f,0.88192129135131835938f,0.38268342614173889160f, +0.92387950420379638672f,0.29028466343879699707f,0.95694035291671752930f, +0.19509032368659973145f,0.98078525066375732422f,0.09801714122295379639f, +0.99518471956253051758f,1.00000000000000000000f,0.00000000000000000000f, +0.92387950420379638672f,0.38268342614173889160f,0.70710676908493041992f, +0.70710676908493041992f,0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99879544973373413086f, +0.04906767606735229492f,0.99518471956253051758f,0.09801714122295379639f, +0.98917651176452636719f,0.14673046767711639404f,0.98078525066375732422f, +0.19509032368659973145f,0.97003126144409179688f,0.24298018217086791992f, +0.95694035291671752930f,0.29028466343879699707f,0.94154405593872070312f, +0.33688986301422119141f,0.92387950420379638672f,0.38268342614173889160f, +0.90398931503295898438f,0.42755508422851562500f,0.88192129135131835938f, +0.47139674425125122070f,0.85772860050201416016f,0.51410275697708129883f, +0.83146959543228149414f,0.55557024478912353516f,0.80320751667022705078f, +0.59569931030273437500f,0.77301043272018432617f,0.63439327478408813477f, +0.74095112085342407227f,0.67155897617340087891f,0.70710676908493041992f, +0.70710676908493041992f,0.67155897617340087891f,0.74095112085342407227f, +0.63439327478408813477f,0.77301043272018432617f,0.59569931030273437500f, +0.80320751667022705078f,0.55557024478912353516f,0.83146959543228149414f, +0.51410275697708129883f,0.85772860050201416016f,0.47139674425125122070f, +0.88192129135131835938f,0.42755508422851562500f,0.90398931503295898438f, +0.38268342614173889160f,0.92387950420379638672f,0.33688986301422119141f, +0.94154405593872070312f,0.29028466343879699707f,0.95694035291671752930f, +0.24298018217086791992f,0.97003126144409179688f,0.19509032368659973145f, +0.98078525066375732422f,0.14673046767711639404f,0.98917651176452636719f, +0.09801714122295379639f,0.99518471956253051758f,0.04906767606735229492f, +0.99879544973373413086f,0.00000000000000006123f,1.00000000000000000000f, +-0.04906767606735229492f,0.99879544973373413086f,-0.09801714122295379639f, +0.99518471956253051758f,-0.14673046767711639404f,0.98917651176452636719f, +-0.19509032368659973145f,0.98078525066375732422f,-0.24298018217086791992f, +0.97003126144409179688f,-0.29028466343879699707f,0.95694035291671752930f, +-0.33688986301422119141f,0.94154405593872070312f,-0.38268342614173889160f, +0.92387950420379638672f,-0.42755508422851562500f,0.90398931503295898438f, +-0.47139674425125122070f,0.88192129135131835938f,-0.51410275697708129883f, +0.85772860050201416016f,-0.55557024478912353516f,0.83146959543228149414f, +-0.59569931030273437500f,0.80320751667022705078f,-0.63439327478408813477f, +0.77301043272018432617f,-0.67155897617340087891f,0.74095112085342407227f, +-0.70710676908493041992f,0.70710676908493041992f,-0.74095112085342407227f, +0.67155897617340087891f,-0.77301043272018432617f,0.63439327478408813477f, +-0.80320751667022705078f,0.59569931030273437500f,-0.83146959543228149414f, +0.55557024478912353516f,-0.85772860050201416016f,0.51410275697708129883f, +-0.88192129135131835938f,0.47139674425125122070f,-0.90398931503295898438f, +0.42755508422851562500f,-0.92387950420379638672f,0.38268342614173889160f, +-0.94154405593872070312f,0.33688986301422119141f,-0.95694035291671752930f, +0.29028466343879699707f,-0.97003126144409179688f,0.24298018217086791992f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98917651176452636719f, +0.14673046767711639404f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99879544973373413086f,0.04906767606735229492f,1.00000000000000000000f, +0.00000000000000000000f,0.98078525066375732422f,0.19509032368659973145f, +0.92387950420379638672f,0.38268342614173889160f,0.83146959543228149414f, +0.55557024478912353516f,0.70710676908493041992f,0.70710676908493041992f, +0.55557024478912353516f,0.83146959543228149414f,0.38268342614173889160f, +0.92387950420379638672f,0.19509032368659973145f,0.98078525066375732422f, +0.00000000000000006123f,1.00000000000000000000f,-0.19509032368659973145f, +0.98078525066375732422f,-0.38268342614173889160f,0.92387950420379638672f, +-0.55557024478912353516f,0.83146959543228149414f,-0.70710676908493041992f, +0.70710676908493041992f,-0.83146959543228149414f,0.55557024478912353516f, +-0.92387950420379638672f,0.38268342614173889160f,-0.98078525066375732422f, +0.19509032368659973145f,1.00000000000000000000f,0.00000000000000000000f, +0.70710676908493041992f,0.70710676908493041992f,0.00000000000000006123f, +1.00000000000000000000f,-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_256_f32[168]={ +1.00000000000000000000f,0.00000000000000000000f,0.99729043245315551758f, +0.07356456667184829712f,0.98917651176452636719f,0.14673046767711639404f, +0.97570210695266723633f,0.21910123527050018311f,0.95694035291671752930f, +0.29028466343879699707f,0.93299281597137451172f,0.35989505052566528320f, +0.90398931503295898438f,0.42755508422851562500f,0.87008696794509887695f, +0.49289819598197937012f,0.83146959543228149414f,0.55557024478912353516f, +0.78834640979766845703f,0.61523157358169555664f,0.74095112085342407227f, +0.67155897617340087891f,0.68954056501388549805f,0.72424709796905517578f, +0.63439327478408813477f,0.77301043272018432617f,0.57580816745758056641f, +0.81758481264114379883f,0.51410275697708129883f,0.85772860050201416016f, +0.44961133599281311035f,0.89322429895401000977f,0.38268342614173889160f, +0.92387950420379638672f,0.31368175148963928223f,0.94952815771102905273f, +0.24298018217086791992f,0.97003126144409179688f,0.17096188664436340332f, +0.98527765274047851562f,0.09801714122295379639f,0.99518471956253051758f, +0.02454122900962829590f,0.99969881772994995117f,-0.04906767606735229492f, +0.99879544973373413086f,-0.12241067737340927124f,0.99247956275939941406f, +-0.19509032368659973145f,0.98078525066375732422f,-0.26671275496482849121f, +0.96377605199813842773f,-0.33688986301422119141f,0.94154405593872070312f, +-0.40524131059646606445f,0.91420978307723999023f,-0.47139674425125122070f, +0.88192129135131835938f,-0.53499764204025268555f,0.84485357999801635742f, +-0.59569931030273437500f,0.80320751667022705078f,-0.65317285060882568359f, +0.75720882415771484375f,-0.70710676908493041992f,0.70710676908493041992f, +-0.75720882415771484375f,0.65317285060882568359f,-0.80320751667022705078f, +0.59569931030273437500f,-0.84485357999801635742f,0.53499764204025268555f, +-0.88192129135131835938f,0.47139674425125122070f,-0.91420978307723999023f, +0.40524131059646606445f,-0.94154405593872070312f,0.33688986301422119141f, +-0.96377605199813842773f,0.26671275496482849121f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.07356456667184829712f,-0.99729043245315551758f,1.00000000000000000000f, +0.00000000000000000000f,0.95694035291671752930f,0.29028466343879699707f, +0.83146959543228149414f,0.55557024478912353516f,0.63439327478408813477f, +0.77301043272018432617f,0.38268342614173889160f,0.92387950420379638672f, +0.09801714122295379639f,0.99518471956253051758f,-0.19509032368659973145f, +0.98078525066375732422f,-0.47139674425125122070f,0.88192129135131835938f, +-0.70710676908493041992f,0.70710676908493041992f,-0.88192129135131835938f, +0.47139674425125122070f,-0.98078525066375732422f,0.19509032368659973145f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.29028466343879699707f, +-0.95694035291671752930f,1.00000000000000000000f,0.00000000000000000000f, +0.38268342614173889160f,0.92387950420379638672f,-0.70710676908493041992f, +0.70710676908493041992f,-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]={ +0,512,640,672,0,}; + +float32_t rearranged_twiddle_stride1_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99998116493225097656f, +0.00613588467240333557f,0.99992471933364868164f,0.01227153837680816650f, +0.99983060359954833984f,0.01840673014521598816f,0.99969881772994995117f, +0.02454122900962829590f,0.99952942132949829102f,0.03067480400204658508f, +0.99932235479354858398f,0.03680722415447235107f,0.99907773733139038086f, +0.04293825849890708923f,0.99879544973373413086f,0.04906767606735229492f, +0.99847555160522460938f,0.05519524589180946350f,0.99811810255050659180f, +0.06132073700428009033f,0.99772304296493530273f,0.06744392216205596924f, +0.99729043245315551758f,0.07356456667184829712f,0.99682027101516723633f, +0.07968243956565856934f,0.99631261825561523438f,0.08579730987548828125f, +0.99576741456985473633f,0.09190895408391952515f,0.99518471956253051758f, +0.09801714122295379639f,0.99456459283828735352f,0.10412163287401199341f, +0.99390697479248046875f,0.11022220551967620850f,0.99321192502975463867f, +0.11631862819194793701f,0.99247956275939941406f,0.12241067737340927124f, +0.99170976877212524414f,0.12849810719490051270f,0.99090266227722167969f, +0.13458070158958435059f,0.99005818367004394531f,0.14065824449062347412f, +0.98917651176452636719f,0.14673046767711639404f,0.98825758695602416992f, +0.15279719233512878418f,0.98730140924453735352f,0.15885815024375915527f, +0.98630809783935546875f,0.16491311788558959961f,0.98527765274047851562f, +0.17096188664436340332f,0.98421007394790649414f,0.17700421810150146484f, +0.98310548067092895508f,0.18303988873958587646f,0.98196387290954589844f, +0.18906866014003753662f,0.98078525066375732422f,0.19509032368659973145f, +0.97956979274749755859f,0.20110464096069335938f,0.97831737995147705078f, +0.20711137354373931885f,0.97702813148498535156f,0.21311031281948089600f, +0.97570210695266723633f,0.21910123527050018311f,0.97433936595916748047f, +0.22508391737937927246f,0.97293996810913085938f,0.23105810582637786865f, +0.97150391340255737305f,0.23702360689640045166f,0.97003126144409179688f, +0.24298018217086791992f,0.96852207183837890625f,0.24892760813236236572f, +0.96697646379470825195f,0.25486564636230468750f,0.96539443731307983398f, +0.26079410314559936523f,0.96377605199813842773f,0.26671275496482849121f, +0.96212142705917358398f,0.27262136340141296387f,0.96043050289154052734f, +0.27851969003677368164f,0.95870345830917358398f,0.28440752625465393066f, +0.95694035291671752930f,0.29028466343879699707f,0.95514118671417236328f, +0.29615089297294616699f,0.95330601930618286133f,0.30200594663619995117f, +0.95143502950668334961f,0.30784964561462402344f,0.94952815771102905273f, +0.31368175148963928223f,0.94758558273315429688f,0.31950202584266662598f, +0.94560730457305908203f,0.32531028985977172852f,0.94359344244003295898f, +0.33110630512237548828f,0.94154405593872070312f,0.33688986301422119141f, +0.93945920467376708984f,0.34266072511672973633f,0.93733900785446166992f, +0.34841868281364440918f,0.93518352508544921875f,0.35416352748870849609f, +0.93299281597137451172f,0.35989505052566528320f,0.93076694011688232422f, +0.36561298370361328125f,0.92850607633590698242f,0.37131720781326293945f, +0.92621022462844848633f,0.37700742483139038086f,0.92387950420379638672f, +0.38268342614173889160f,0.92151403427124023438f,0.38834503293037414551f, +0.91911387443542480469f,0.39399203658103942871f,0.91667908430099487305f, +0.39962419867515563965f,0.91420978307723999023f,0.40524131059646606445f, +0.91170603036880493164f,0.41084316372871398926f,0.90916800498962402344f, +0.41642954945564270020f,0.90659570693969726562f,0.42200025916099548340f, +0.90398931503295898438f,0.42755508422851562500f,0.90134882926940917969f, +0.43309381604194641113f,0.89867448806762695312f,0.43861624598503112793f, +0.89596623182296752930f,0.44412213563919067383f,0.89322429895401000977f, +0.44961133599281311035f,0.89044874906539916992f,0.45508357882499694824f, +0.88763964176177978516f,0.46053871512413024902f,0.88479709625244140625f, +0.46597650647163391113f,0.88192129135131835938f,0.47139674425125122070f, +0.87901222705841064453f,0.47679921984672546387f,0.87607008218765258789f, +0.48218378424644470215f,0.87309497594833374023f,0.48755016922950744629f, +0.87008696794509887695f,0.49289819598197937012f,0.86704623699188232422f, +0.49822765588760375977f,0.86397284269332885742f,0.50353837013244628906f, +0.86086696386337280273f,0.50883013010025024414f,0.85772860050201416016f, +0.51410275697708129883f,0.85455799102783203125f,0.51935601234436035156f, +0.85135519504547119141f,0.52458965778350830078f,0.84812033176422119141f, +0.52980363368988037109f,0.84485357999801635742f,0.53499764204025268555f, +0.84155499935150146484f,0.54017144441604614258f,0.83822470903396606445f, +0.54532498121261596680f,0.83486288785934448242f,0.55045795440673828125f, +0.83146959543228149414f,0.55557024478912353516f,0.82804507017135620117f, +0.56066155433654785156f,0.82458931207656860352f,0.56573182344436645508f, +0.82110249996185302734f,0.57078075408935546875f,0.81758481264114379883f, +0.57580816745758056641f,0.81403630971908569336f,0.58081394433975219727f, +0.81045717000961303711f,0.58579784631729125977f,0.80684757232666015625f, +0.59075969457626342773f,0.80320751667022705078f,0.59569931030273437500f, +0.79953724145889282227f,0.60061645507812500000f,0.79583692550659179688f, +0.60551106929779052734f,0.79210656881332397461f,0.61038279533386230469f, +0.78834640979766845703f,0.61523157358169555664f,0.78455656766891479492f, +0.62005722522735595703f,0.78073722124099731445f,0.62485951185226440430f, +0.77688848972320556641f,0.62963825464248657227f,0.77301043272018432617f, +0.63439327478408813477f,0.76910334825515747070f,0.63912445306777954102f, +0.76516723632812500000f,0.64383155107498168945f,0.76120239496231079102f, +0.64851438999176025391f,0.75720882415771484375f,0.65317285060882568359f, +0.75318682193756103516f,0.65780669450759887695f,0.74913638830184936523f, +0.66241580247879028320f,0.74505776166915893555f,0.66699993610382080078f, +0.74095112085342407227f,0.67155897617340087891f,0.73681658506393432617f, +0.67609268426895141602f,0.73265427350997924805f,0.68060100078582763672f, +0.72846436500549316406f,0.68508368730545043945f,0.72424709796905517578f, +0.68954056501388549805f,0.72000253200531005859f,0.69397145509719848633f, +0.71573084592819213867f,0.69837623834609985352f,0.71143221855163574219f, +0.70275473594665527344f,0.70710676908493041992f,0.70710676908493041992f, +0.70275473594665527344f,0.71143221855163574219f,0.69837623834609985352f, +0.71573084592819213867f,0.69397145509719848633f,0.72000253200531005859f, +0.68954056501388549805f,0.72424709796905517578f,0.68508368730545043945f, +0.72846436500549316406f,0.68060100078582763672f,0.73265427350997924805f, +0.67609268426895141602f,0.73681658506393432617f,0.67155897617340087891f, +0.74095112085342407227f,0.66699993610382080078f,0.74505776166915893555f, +0.66241580247879028320f,0.74913638830184936523f,0.65780669450759887695f, +0.75318682193756103516f,0.65317285060882568359f,0.75720882415771484375f, +0.64851438999176025391f,0.76120239496231079102f,0.64383155107498168945f, +0.76516723632812500000f,0.63912445306777954102f,0.76910334825515747070f, +0.63439327478408813477f,0.77301043272018432617f,0.62963825464248657227f, +0.77688848972320556641f,0.62485951185226440430f,0.78073722124099731445f, +0.62005722522735595703f,0.78455656766891479492f,0.61523157358169555664f, +0.78834640979766845703f,0.61038279533386230469f,0.79210656881332397461f, +0.60551106929779052734f,0.79583692550659179688f,0.60061645507812500000f, +0.79953724145889282227f,0.59569931030273437500f,0.80320751667022705078f, +0.59075969457626342773f,0.80684757232666015625f,0.58579784631729125977f, +0.81045717000961303711f,0.58081394433975219727f,0.81403630971908569336f, +0.57580816745758056641f,0.81758481264114379883f,0.57078075408935546875f, +0.82110249996185302734f,0.56573182344436645508f,0.82458931207656860352f, +0.56066155433654785156f,0.82804507017135620117f,0.55557024478912353516f, +0.83146959543228149414f,0.55045795440673828125f,0.83486288785934448242f, +0.54532498121261596680f,0.83822470903396606445f,0.54017144441604614258f, +0.84155499935150146484f,0.53499764204025268555f,0.84485357999801635742f, +0.52980363368988037109f,0.84812033176422119141f,0.52458965778350830078f, +0.85135519504547119141f,0.51935601234436035156f,0.85455799102783203125f, +0.51410275697708129883f,0.85772860050201416016f,0.50883013010025024414f, +0.86086696386337280273f,0.50353837013244628906f,0.86397284269332885742f, +0.49822765588760375977f,0.86704623699188232422f,0.49289819598197937012f, +0.87008696794509887695f,0.48755016922950744629f,0.87309497594833374023f, +0.48218378424644470215f,0.87607008218765258789f,0.47679921984672546387f, +0.87901222705841064453f,0.47139674425125122070f,0.88192129135131835938f, +0.46597650647163391113f,0.88479709625244140625f,0.46053871512413024902f, +0.88763964176177978516f,0.45508357882499694824f,0.89044874906539916992f, +0.44961133599281311035f,0.89322429895401000977f,0.44412213563919067383f, +0.89596623182296752930f,0.43861624598503112793f,0.89867448806762695312f, +0.43309381604194641113f,0.90134882926940917969f,0.42755508422851562500f, +0.90398931503295898438f,0.42200025916099548340f,0.90659570693969726562f, +0.41642954945564270020f,0.90916800498962402344f,0.41084316372871398926f, +0.91170603036880493164f,0.40524131059646606445f,0.91420978307723999023f, +0.39962419867515563965f,0.91667908430099487305f,0.39399203658103942871f, +0.91911387443542480469f,0.38834503293037414551f,0.92151403427124023438f, +0.38268342614173889160f,0.92387950420379638672f,0.37700742483139038086f, +0.92621022462844848633f,0.37131720781326293945f,0.92850607633590698242f, +0.36561298370361328125f,0.93076694011688232422f,0.35989505052566528320f, +0.93299281597137451172f,0.35416352748870849609f,0.93518352508544921875f, +0.34841868281364440918f,0.93733900785446166992f,0.34266072511672973633f, +0.93945920467376708984f,0.33688986301422119141f,0.94154405593872070312f, +0.33110630512237548828f,0.94359344244003295898f,0.32531028985977172852f, +0.94560730457305908203f,0.31950202584266662598f,0.94758558273315429688f, +0.31368175148963928223f,0.94952815771102905273f,0.30784964561462402344f, +0.95143502950668334961f,0.30200594663619995117f,0.95330601930618286133f, +0.29615089297294616699f,0.95514118671417236328f,0.29028466343879699707f, +0.95694035291671752930f,0.28440752625465393066f,0.95870345830917358398f, +0.27851969003677368164f,0.96043050289154052734f,0.27262136340141296387f, +0.96212142705917358398f,0.26671275496482849121f,0.96377605199813842773f, +0.26079410314559936523f,0.96539443731307983398f,0.25486564636230468750f, +0.96697646379470825195f,0.24892760813236236572f,0.96852207183837890625f, +0.24298018217086791992f,0.97003126144409179688f,0.23702360689640045166f, +0.97150391340255737305f,0.23105810582637786865f,0.97293996810913085938f, +0.22508391737937927246f,0.97433936595916748047f,0.21910123527050018311f, +0.97570210695266723633f,0.21311031281948089600f,0.97702813148498535156f, +0.20711137354373931885f,0.97831737995147705078f,0.20110464096069335938f, +0.97956979274749755859f,0.19509032368659973145f,0.98078525066375732422f, +0.18906866014003753662f,0.98196387290954589844f,0.18303988873958587646f, +0.98310548067092895508f,0.17700421810150146484f,0.98421007394790649414f, +0.17096188664436340332f,0.98527765274047851562f,0.16491311788558959961f, +0.98630809783935546875f,0.15885815024375915527f,0.98730140924453735352f, +0.15279719233512878418f,0.98825758695602416992f,0.14673046767711639404f, +0.98917651176452636719f,0.14065824449062347412f,0.99005818367004394531f, +0.13458070158958435059f,0.99090266227722167969f,0.12849810719490051270f, +0.99170976877212524414f,0.12241067737340927124f,0.99247956275939941406f, +0.11631862819194793701f,0.99321192502975463867f,0.11022220551967620850f, +0.99390697479248046875f,0.10412163287401199341f,0.99456459283828735352f, +0.09801714122295379639f,0.99518471956253051758f,0.09190895408391952515f, +0.99576741456985473633f,0.08579730987548828125f,0.99631261825561523438f, +0.07968243956565856934f,0.99682027101516723633f,0.07356456667184829712f, +0.99729043245315551758f,0.06744392216205596924f,0.99772304296493530273f, +0.06132073700428009033f,0.99811810255050659180f,0.05519524589180946350f, +0.99847555160522460938f,0.04906767606735229492f,0.99879544973373413086f, +0.04293825849890708923f,0.99907773733139038086f,0.03680722415447235107f, +0.99932235479354858398f,0.03067480400204658508f,0.99952942132949829102f, +0.02454122900962829590f,0.99969881772994995117f,0.01840673014521598816f, +0.99983060359954833984f,0.01227153837680816650f,0.99992471933364868164f, +0.00613588467240333557f,0.99998116493225097656f,1.00000000000000000000f, +0.00000000000000000000f,0.99969881772994995117f,0.02454122900962829590f, +0.99879544973373413086f,0.04906767606735229492f,0.99729043245315551758f, +0.07356456667184829712f,0.99518471956253051758f,0.09801714122295379639f, +0.99247956275939941406f,0.12241067737340927124f,0.98917651176452636719f, +0.14673046767711639404f,0.98527765274047851562f,0.17096188664436340332f, +0.98078525066375732422f,0.19509032368659973145f,0.97570210695266723633f, +0.21910123527050018311f,0.97003126144409179688f,0.24298018217086791992f, +0.96377605199813842773f,0.26671275496482849121f,0.95694035291671752930f, +0.29028466343879699707f,0.94952815771102905273f,0.31368175148963928223f, +0.94154405593872070312f,0.33688986301422119141f,0.93299281597137451172f, +0.35989505052566528320f,0.92387950420379638672f,0.38268342614173889160f, +0.91420978307723999023f,0.40524131059646606445f,0.90398931503295898438f, +0.42755508422851562500f,0.89322429895401000977f,0.44961133599281311035f, +0.88192129135131835938f,0.47139674425125122070f,0.87008696794509887695f, +0.49289819598197937012f,0.85772860050201416016f,0.51410275697708129883f, +0.84485357999801635742f,0.53499764204025268555f,0.83146959543228149414f, +0.55557024478912353516f,0.81758481264114379883f,0.57580816745758056641f, +0.80320751667022705078f,0.59569931030273437500f,0.78834640979766845703f, +0.61523157358169555664f,0.77301043272018432617f,0.63439327478408813477f, +0.75720882415771484375f,0.65317285060882568359f,0.74095112085342407227f, +0.67155897617340087891f,0.72424709796905517578f,0.68954056501388549805f, +0.70710676908493041992f,0.70710676908493041992f,0.68954056501388549805f, +0.72424709796905517578f,0.67155897617340087891f,0.74095112085342407227f, +0.65317285060882568359f,0.75720882415771484375f,0.63439327478408813477f, +0.77301043272018432617f,0.61523157358169555664f,0.78834640979766845703f, +0.59569931030273437500f,0.80320751667022705078f,0.57580816745758056641f, +0.81758481264114379883f,0.55557024478912353516f,0.83146959543228149414f, +0.53499764204025268555f,0.84485357999801635742f,0.51410275697708129883f, +0.85772860050201416016f,0.49289819598197937012f,0.87008696794509887695f, +0.47139674425125122070f,0.88192129135131835938f,0.44961133599281311035f, +0.89322429895401000977f,0.42755508422851562500f,0.90398931503295898438f, +0.40524131059646606445f,0.91420978307723999023f,0.38268342614173889160f, +0.92387950420379638672f,0.35989505052566528320f,0.93299281597137451172f, +0.33688986301422119141f,0.94154405593872070312f,0.31368175148963928223f, +0.94952815771102905273f,0.29028466343879699707f,0.95694035291671752930f, +0.26671275496482849121f,0.96377605199813842773f,0.24298018217086791992f, +0.97003126144409179688f,0.21910123527050018311f,0.97570210695266723633f, +0.19509032368659973145f,0.98078525066375732422f,0.17096188664436340332f, +0.98527765274047851562f,0.14673046767711639404f,0.98917651176452636719f, +0.12241067737340927124f,0.99247956275939941406f,0.09801714122295379639f, +0.99518471956253051758f,0.07356456667184829712f,0.99729043245315551758f, +0.04906767606735229492f,0.99879544973373413086f,0.02454122900962829590f, +0.99969881772994995117f,1.00000000000000000000f,0.00000000000000000000f, +0.99518471956253051758f,0.09801714122295379639f,0.98078525066375732422f, +0.19509032368659973145f,0.95694035291671752930f,0.29028466343879699707f, +0.92387950420379638672f,0.38268342614173889160f,0.88192129135131835938f, +0.47139674425125122070f,0.83146959543228149414f,0.55557024478912353516f, +0.77301043272018432617f,0.63439327478408813477f,0.70710676908493041992f, +0.70710676908493041992f,0.63439327478408813477f,0.77301043272018432617f, +0.55557024478912353516f,0.83146959543228149414f,0.47139674425125122070f, +0.88192129135131835938f,0.38268342614173889160f,0.92387950420379638672f, +0.29028466343879699707f,0.95694035291671752930f,0.19509032368659973145f, +0.98078525066375732422f,0.09801714122295379639f,0.99518471956253051758f, +1.00000000000000000000f,0.00000000000000000000f,0.92387950420379638672f, +0.38268342614173889160f,0.70710676908493041992f,0.70710676908493041992f, +0.38268342614173889160f,0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99992471933364868164f, +0.01227153837680816650f,0.99969881772994995117f,0.02454122900962829590f, +0.99932235479354858398f,0.03680722415447235107f,0.99879544973373413086f, +0.04906767606735229492f,0.99811810255050659180f,0.06132073700428009033f, +0.99729043245315551758f,0.07356456667184829712f,0.99631261825561523438f, +0.08579730987548828125f,0.99518471956253051758f,0.09801714122295379639f, +0.99390697479248046875f,0.11022220551967620850f,0.99247956275939941406f, +0.12241067737340927124f,0.99090266227722167969f,0.13458070158958435059f, +0.98917651176452636719f,0.14673046767711639404f,0.98730140924453735352f, +0.15885815024375915527f,0.98527765274047851562f,0.17096188664436340332f, +0.98310548067092895508f,0.18303988873958587646f,0.98078525066375732422f, +0.19509032368659973145f,0.97831737995147705078f,0.20711137354373931885f, +0.97570210695266723633f,0.21910123527050018311f,0.97293996810913085938f, +0.23105810582637786865f,0.97003126144409179688f,0.24298018217086791992f, +0.96697646379470825195f,0.25486564636230468750f,0.96377605199813842773f, +0.26671275496482849121f,0.96043050289154052734f,0.27851969003677368164f, +0.95694035291671752930f,0.29028466343879699707f,0.95330601930618286133f, +0.30200594663619995117f,0.94952815771102905273f,0.31368175148963928223f, +0.94560730457305908203f,0.32531028985977172852f,0.94154405593872070312f, +0.33688986301422119141f,0.93733900785446166992f,0.34841868281364440918f, +0.93299281597137451172f,0.35989505052566528320f,0.92850607633590698242f, +0.37131720781326293945f,0.92387950420379638672f,0.38268342614173889160f, +0.91911387443542480469f,0.39399203658103942871f,0.91420978307723999023f, +0.40524131059646606445f,0.90916800498962402344f,0.41642954945564270020f, +0.90398931503295898438f,0.42755508422851562500f,0.89867448806762695312f, +0.43861624598503112793f,0.89322429895401000977f,0.44961133599281311035f, +0.88763964176177978516f,0.46053871512413024902f,0.88192129135131835938f, +0.47139674425125122070f,0.87607008218765258789f,0.48218378424644470215f, +0.87008696794509887695f,0.49289819598197937012f,0.86397284269332885742f, +0.50353837013244628906f,0.85772860050201416016f,0.51410275697708129883f, +0.85135519504547119141f,0.52458965778350830078f,0.84485357999801635742f, +0.53499764204025268555f,0.83822470903396606445f,0.54532498121261596680f, +0.83146959543228149414f,0.55557024478912353516f,0.82458931207656860352f, +0.56573182344436645508f,0.81758481264114379883f,0.57580816745758056641f, +0.81045717000961303711f,0.58579784631729125977f,0.80320751667022705078f, +0.59569931030273437500f,0.79583692550659179688f,0.60551106929779052734f, +0.78834640979766845703f,0.61523157358169555664f,0.78073722124099731445f, +0.62485951185226440430f,0.77301043272018432617f,0.63439327478408813477f, +0.76516723632812500000f,0.64383155107498168945f,0.75720882415771484375f, +0.65317285060882568359f,0.74913638830184936523f,0.66241580247879028320f, +0.74095112085342407227f,0.67155897617340087891f,0.73265427350997924805f, +0.68060100078582763672f,0.72424709796905517578f,0.68954056501388549805f, +0.71573084592819213867f,0.69837623834609985352f,0.70710676908493041992f, +0.70710676908493041992f,0.69837623834609985352f,0.71573084592819213867f, +0.68954056501388549805f,0.72424709796905517578f,0.68060100078582763672f, +0.73265427350997924805f,0.67155897617340087891f,0.74095112085342407227f, +0.66241580247879028320f,0.74913638830184936523f,0.65317285060882568359f, +0.75720882415771484375f,0.64383155107498168945f,0.76516723632812500000f, +0.63439327478408813477f,0.77301043272018432617f,0.62485951185226440430f, +0.78073722124099731445f,0.61523157358169555664f,0.78834640979766845703f, +0.60551106929779052734f,0.79583692550659179688f,0.59569931030273437500f, +0.80320751667022705078f,0.58579784631729125977f,0.81045717000961303711f, +0.57580816745758056641f,0.81758481264114379883f,0.56573182344436645508f, +0.82458931207656860352f,0.55557024478912353516f,0.83146959543228149414f, +0.54532498121261596680f,0.83822470903396606445f,0.53499764204025268555f, +0.84485357999801635742f,0.52458965778350830078f,0.85135519504547119141f, +0.51410275697708129883f,0.85772860050201416016f,0.50353837013244628906f, +0.86397284269332885742f,0.49289819598197937012f,0.87008696794509887695f, +0.48218378424644470215f,0.87607008218765258789f,0.47139674425125122070f, +0.88192129135131835938f,0.46053871512413024902f,0.88763964176177978516f, +0.44961133599281311035f,0.89322429895401000977f,0.43861624598503112793f, +0.89867448806762695312f,0.42755508422851562500f,0.90398931503295898438f, +0.41642954945564270020f,0.90916800498962402344f,0.40524131059646606445f, +0.91420978307723999023f,0.39399203658103942871f,0.91911387443542480469f, +0.38268342614173889160f,0.92387950420379638672f,0.37131720781326293945f, +0.92850607633590698242f,0.35989505052566528320f,0.93299281597137451172f, +0.34841868281364440918f,0.93733900785446166992f,0.33688986301422119141f, +0.94154405593872070312f,0.32531028985977172852f,0.94560730457305908203f, +0.31368175148963928223f,0.94952815771102905273f,0.30200594663619995117f, +0.95330601930618286133f,0.29028466343879699707f,0.95694035291671752930f, +0.27851969003677368164f,0.96043050289154052734f,0.26671275496482849121f, +0.96377605199813842773f,0.25486564636230468750f,0.96697646379470825195f, +0.24298018217086791992f,0.97003126144409179688f,0.23105810582637786865f, +0.97293996810913085938f,0.21910123527050018311f,0.97570210695266723633f, +0.20711137354373931885f,0.97831737995147705078f,0.19509032368659973145f, +0.98078525066375732422f,0.18303988873958587646f,0.98310548067092895508f, +0.17096188664436340332f,0.98527765274047851562f,0.15885815024375915527f, +0.98730140924453735352f,0.14673046767711639404f,0.98917651176452636719f, +0.13458070158958435059f,0.99090266227722167969f,0.12241067737340927124f, +0.99247956275939941406f,0.11022220551967620850f,0.99390697479248046875f, +0.09801714122295379639f,0.99518471956253051758f,0.08579730987548828125f, +0.99631261825561523438f,0.07356456667184829712f,0.99729043245315551758f, +0.06132073700428009033f,0.99811810255050659180f,0.04906767606735229492f, +0.99879544973373413086f,0.03680722415447235107f,0.99932235479354858398f, +0.02454122900962829590f,0.99969881772994995117f,0.01227153837680816650f, +0.99992471933364868164f,0.00000000000000006123f,1.00000000000000000000f, +-0.01227153837680816650f,0.99992471933364868164f,-0.02454122900962829590f, +0.99969881772994995117f,-0.03680722415447235107f,0.99932235479354858398f, +-0.04906767606735229492f,0.99879544973373413086f,-0.06132073700428009033f, +0.99811810255050659180f,-0.07356456667184829712f,0.99729043245315551758f, +-0.08579730987548828125f,0.99631261825561523438f,-0.09801714122295379639f, +0.99518471956253051758f,-0.11022220551967620850f,0.99390697479248046875f, +-0.12241067737340927124f,0.99247956275939941406f,-0.13458070158958435059f, +0.99090266227722167969f,-0.14673046767711639404f,0.98917651176452636719f, +-0.15885815024375915527f,0.98730140924453735352f,-0.17096188664436340332f, +0.98527765274047851562f,-0.18303988873958587646f,0.98310548067092895508f, +-0.19509032368659973145f,0.98078525066375732422f,-0.20711137354373931885f, +0.97831737995147705078f,-0.21910123527050018311f,0.97570210695266723633f, +-0.23105810582637786865f,0.97293996810913085938f,-0.24298018217086791992f, +0.97003126144409179688f,-0.25486564636230468750f,0.96697646379470825195f, +-0.26671275496482849121f,0.96377605199813842773f,-0.27851969003677368164f, +0.96043050289154052734f,-0.29028466343879699707f,0.95694035291671752930f, +-0.30200594663619995117f,0.95330601930618286133f,-0.31368175148963928223f, +0.94952815771102905273f,-0.32531028985977172852f,0.94560730457305908203f, +-0.33688986301422119141f,0.94154405593872070312f,-0.34841868281364440918f, +0.93733900785446166992f,-0.35989505052566528320f,0.93299281597137451172f, +-0.37131720781326293945f,0.92850607633590698242f,-0.38268342614173889160f, +0.92387950420379638672f,-0.39399203658103942871f,0.91911387443542480469f, +-0.40524131059646606445f,0.91420978307723999023f,-0.41642954945564270020f, +0.90916800498962402344f,-0.42755508422851562500f,0.90398931503295898438f, +-0.43861624598503112793f,0.89867448806762695312f,-0.44961133599281311035f, +0.89322429895401000977f,-0.46053871512413024902f,0.88763964176177978516f, +-0.47139674425125122070f,0.88192129135131835938f,-0.48218378424644470215f, +0.87607008218765258789f,-0.49289819598197937012f,0.87008696794509887695f, +-0.50353837013244628906f,0.86397284269332885742f,-0.51410275697708129883f, +0.85772860050201416016f,-0.52458965778350830078f,0.85135519504547119141f, +-0.53499764204025268555f,0.84485357999801635742f,-0.54532498121261596680f, +0.83822470903396606445f,-0.55557024478912353516f,0.83146959543228149414f, +-0.56573182344436645508f,0.82458931207656860352f,-0.57580816745758056641f, +0.81758481264114379883f,-0.58579784631729125977f,0.81045717000961303711f, +-0.59569931030273437500f,0.80320751667022705078f,-0.60551106929779052734f, +0.79583692550659179688f,-0.61523157358169555664f,0.78834640979766845703f, +-0.62485951185226440430f,0.78073722124099731445f,-0.63439327478408813477f, +0.77301043272018432617f,-0.64383155107498168945f,0.76516723632812500000f, +-0.65317285060882568359f,0.75720882415771484375f,-0.66241580247879028320f, +0.74913638830184936523f,-0.67155897617340087891f,0.74095112085342407227f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68954056501388549805f, +0.72424709796905517578f,-0.69837623834609985352f,0.71573084592819213867f, +-0.70710676908493041992f,0.70710676908493041992f,-0.71573084592819213867f, +0.69837623834609985352f,-0.72424709796905517578f,0.68954056501388549805f, +-0.73265427350997924805f,0.68060100078582763672f,-0.74095112085342407227f, +0.67155897617340087891f,-0.74913638830184936523f,0.66241580247879028320f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76516723632812500000f, +0.64383155107498168945f,-0.77301043272018432617f,0.63439327478408813477f, +-0.78073722124099731445f,0.62485951185226440430f,-0.78834640979766845703f, +0.61523157358169555664f,-0.79583692550659179688f,0.60551106929779052734f, +-0.80320751667022705078f,0.59569931030273437500f,-0.81045717000961303711f, +0.58579784631729125977f,-0.81758481264114379883f,0.57580816745758056641f, +-0.82458931207656860352f,0.56573182344436645508f,-0.83146959543228149414f, +0.55557024478912353516f,-0.83822470903396606445f,0.54532498121261596680f, +-0.84485357999801635742f,0.53499764204025268555f,-0.85135519504547119141f, +0.52458965778350830078f,-0.85772860050201416016f,0.51410275697708129883f, +-0.86397284269332885742f,0.50353837013244628906f,-0.87008696794509887695f, +0.49289819598197937012f,-0.87607008218765258789f,0.48218378424644470215f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88763964176177978516f, +0.46053871512413024902f,-0.89322429895401000977f,0.44961133599281311035f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90398931503295898438f, +0.42755508422851562500f,-0.90916800498962402344f,0.41642954945564270020f, +-0.91420978307723999023f,0.40524131059646606445f,-0.91911387443542480469f, +0.39399203658103942871f,-0.92387950420379638672f,0.38268342614173889160f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93299281597137451172f, +0.35989505052566528320f,-0.93733900785446166992f,0.34841868281364440918f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94560730457305908203f, +0.32531028985977172852f,-0.94952815771102905273f,0.31368175148963928223f, +-0.95330601930618286133f,0.30200594663619995117f,-0.95694035291671752930f, +0.29028466343879699707f,-0.96043050289154052734f,0.27851969003677368164f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96697646379470825195f, +0.25486564636230468750f,-0.97003126144409179688f,0.24298018217086791992f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97570210695266723633f, +0.21910123527050018311f,-0.97831737995147705078f,0.20711137354373931885f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98310548067092895508f, +0.18303988873958587646f,-0.98527765274047851562f,0.17096188664436340332f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98917651176452636719f, +0.14673046767711639404f,-0.99090266227722167969f,0.13458070158958435059f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99390697479248046875f, +0.11022220551967620850f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99631261825561523438f,0.08579730987548828125f,-0.99729043245315551758f, +0.07356456667184829712f,-0.99811810255050659180f,0.06132073700428009033f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99932235479354858398f, +0.03680722415447235107f,-0.99969881772994995117f,0.02454122900962829590f, +-0.99992471933364868164f,0.01227153837680816650f,1.00000000000000000000f, +0.00000000000000000000f,0.99879544973373413086f,0.04906767606735229492f, +0.99518471956253051758f,0.09801714122295379639f,0.98917651176452636719f, +0.14673046767711639404f,0.98078525066375732422f,0.19509032368659973145f, +0.97003126144409179688f,0.24298018217086791992f,0.95694035291671752930f, +0.29028466343879699707f,0.94154405593872070312f,0.33688986301422119141f, +0.92387950420379638672f,0.38268342614173889160f,0.90398931503295898438f, +0.42755508422851562500f,0.88192129135131835938f,0.47139674425125122070f, +0.85772860050201416016f,0.51410275697708129883f,0.83146959543228149414f, +0.55557024478912353516f,0.80320751667022705078f,0.59569931030273437500f, +0.77301043272018432617f,0.63439327478408813477f,0.74095112085342407227f, +0.67155897617340087891f,0.70710676908493041992f,0.70710676908493041992f, +0.67155897617340087891f,0.74095112085342407227f,0.63439327478408813477f, +0.77301043272018432617f,0.59569931030273437500f,0.80320751667022705078f, +0.55557024478912353516f,0.83146959543228149414f,0.51410275697708129883f, +0.85772860050201416016f,0.47139674425125122070f,0.88192129135131835938f, +0.42755508422851562500f,0.90398931503295898438f,0.38268342614173889160f, +0.92387950420379638672f,0.33688986301422119141f,0.94154405593872070312f, +0.29028466343879699707f,0.95694035291671752930f,0.24298018217086791992f, +0.97003126144409179688f,0.19509032368659973145f,0.98078525066375732422f, +0.14673046767711639404f,0.98917651176452636719f,0.09801714122295379639f, +0.99518471956253051758f,0.04906767606735229492f,0.99879544973373413086f, +0.00000000000000006123f,1.00000000000000000000f,-0.04906767606735229492f, +0.99879544973373413086f,-0.09801714122295379639f,0.99518471956253051758f, +-0.14673046767711639404f,0.98917651176452636719f,-0.19509032368659973145f, +0.98078525066375732422f,-0.24298018217086791992f,0.97003126144409179688f, +-0.29028466343879699707f,0.95694035291671752930f,-0.33688986301422119141f, +0.94154405593872070312f,-0.38268342614173889160f,0.92387950420379638672f, +-0.42755508422851562500f,0.90398931503295898438f,-0.47139674425125122070f, +0.88192129135131835938f,-0.51410275697708129883f,0.85772860050201416016f, +-0.55557024478912353516f,0.83146959543228149414f,-0.59569931030273437500f, +0.80320751667022705078f,-0.63439327478408813477f,0.77301043272018432617f, +-0.67155897617340087891f,0.74095112085342407227f,-0.70710676908493041992f, +0.70710676908493041992f,-0.74095112085342407227f,0.67155897617340087891f, +-0.77301043272018432617f,0.63439327478408813477f,-0.80320751667022705078f, +0.59569931030273437500f,-0.83146959543228149414f,0.55557024478912353516f, +-0.85772860050201416016f,0.51410275697708129883f,-0.88192129135131835938f, +0.47139674425125122070f,-0.90398931503295898438f,0.42755508422851562500f, +-0.92387950420379638672f,0.38268342614173889160f,-0.94154405593872070312f, +0.33688986301422119141f,-0.95694035291671752930f,0.29028466343879699707f, +-0.97003126144409179688f,0.24298018217086791992f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98917651176452636719f,0.14673046767711639404f, +-0.99518471956253051758f,0.09801714122295379639f,-0.99879544973373413086f, +0.04906767606735229492f,1.00000000000000000000f,0.00000000000000000000f, +0.98078525066375732422f,0.19509032368659973145f,0.92387950420379638672f, +0.38268342614173889160f,0.83146959543228149414f,0.55557024478912353516f, +0.70710676908493041992f,0.70710676908493041992f,0.55557024478912353516f, +0.83146959543228149414f,0.38268342614173889160f,0.92387950420379638672f, +0.19509032368659973145f,0.98078525066375732422f,0.00000000000000006123f, +1.00000000000000000000f,-0.19509032368659973145f,0.98078525066375732422f, +-0.38268342614173889160f,0.92387950420379638672f,-0.55557024478912353516f, +0.83146959543228149414f,-0.70710676908493041992f,0.70710676908493041992f, +-0.83146959543228149414f,0.55557024478912353516f,-0.92387950420379638672f, +0.38268342614173889160f,-0.98078525066375732422f,0.19509032368659973145f, +1.00000000000000000000f,0.00000000000000000000f,0.70710676908493041992f, +0.70710676908493041992f,0.00000000000000006123f,1.00000000000000000000f, +-0.70710676908493041992f,0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_1024_f32[680]={ +1.00000000000000000000f,0.00000000000000000000f,0.99983060359954833984f, +0.01840673014521598816f,0.99932235479354858398f,0.03680722415447235107f, +0.99847555160522460938f,0.05519524589180946350f,0.99729043245315551758f, +0.07356456667184829712f,0.99576741456985473633f,0.09190895408391952515f, +0.99390697479248046875f,0.11022220551967620850f,0.99170976877212524414f, +0.12849810719490051270f,0.98917651176452636719f,0.14673046767711639404f, +0.98630809783935546875f,0.16491311788558959961f,0.98310548067092895508f, +0.18303988873958587646f,0.97956979274749755859f,0.20110464096069335938f, +0.97570210695266723633f,0.21910123527050018311f,0.97150391340255737305f, +0.23702360689640045166f,0.96697646379470825195f,0.25486564636230468750f, +0.96212142705917358398f,0.27262136340141296387f,0.95694035291671752930f, +0.29028466343879699707f,0.95143502950668334961f,0.30784964561462402344f, +0.94560730457305908203f,0.32531028985977172852f,0.93945920467376708984f, +0.34266072511672973633f,0.93299281597137451172f,0.35989505052566528320f, +0.92621022462844848633f,0.37700742483139038086f,0.91911387443542480469f, +0.39399203658103942871f,0.91170603036880493164f,0.41084316372871398926f, +0.90398931503295898438f,0.42755508422851562500f,0.89596623182296752930f, +0.44412213563919067383f,0.88763964176177978516f,0.46053871512413024902f, +0.87901222705841064453f,0.47679921984672546387f,0.87008696794509887695f, +0.49289819598197937012f,0.86086696386337280273f,0.50883013010025024414f, +0.85135519504547119141f,0.52458965778350830078f,0.84155499935150146484f, +0.54017144441604614258f,0.83146959543228149414f,0.55557024478912353516f, +0.82110249996185302734f,0.57078075408935546875f,0.81045717000961303711f, +0.58579784631729125977f,0.79953724145889282227f,0.60061645507812500000f, +0.78834640979766845703f,0.61523157358169555664f,0.77688848972320556641f, +0.62963825464248657227f,0.76516723632812500000f,0.64383155107498168945f, +0.75318682193756103516f,0.65780669450759887695f,0.74095112085342407227f, +0.67155897617340087891f,0.72846436500549316406f,0.68508368730545043945f, +0.71573084592819213867f,0.69837623834609985352f,0.70275473594665527344f, +0.71143221855163574219f,0.68954056501388549805f,0.72424709796905517578f, +0.67609268426895141602f,0.73681658506393432617f,0.66241580247879028320f, +0.74913638830184936523f,0.64851438999176025391f,0.76120239496231079102f, +0.63439327478408813477f,0.77301043272018432617f,0.62005722522735595703f, +0.78455656766891479492f,0.60551106929779052734f,0.79583692550659179688f, +0.59075969457626342773f,0.80684757232666015625f,0.57580816745758056641f, +0.81758481264114379883f,0.56066155433654785156f,0.82804507017135620117f, +0.54532498121261596680f,0.83822470903396606445f,0.52980363368988037109f, +0.84812033176422119141f,0.51410275697708129883f,0.85772860050201416016f, +0.49822765588760375977f,0.86704623699188232422f,0.48218378424644470215f, +0.87607008218765258789f,0.46597650647163391113f,0.88479709625244140625f, +0.44961133599281311035f,0.89322429895401000977f,0.43309381604194641113f, +0.90134882926940917969f,0.41642954945564270020f,0.90916800498962402344f, +0.39962419867515563965f,0.91667908430099487305f,0.38268342614173889160f, +0.92387950420379638672f,0.36561298370361328125f,0.93076694011688232422f, +0.34841868281364440918f,0.93733900785446166992f,0.33110630512237548828f, +0.94359344244003295898f,0.31368175148963928223f,0.94952815771102905273f, +0.29615089297294616699f,0.95514118671417236328f,0.27851969003677368164f, +0.96043050289154052734f,0.26079410314559936523f,0.96539443731307983398f, +0.24298018217086791992f,0.97003126144409179688f,0.22508391737937927246f, +0.97433936595916748047f,0.20711137354373931885f,0.97831737995147705078f, +0.18906866014003753662f,0.98196387290954589844f,0.17096188664436340332f, +0.98527765274047851562f,0.15279719233512878418f,0.98825758695602416992f, +0.13458070158958435059f,0.99090266227722167969f,0.11631862819194793701f, +0.99321192502975463867f,0.09801714122295379639f,0.99518471956253051758f, +0.07968243956565856934f,0.99682027101516723633f,0.06132073700428009033f, +0.99811810255050659180f,0.04293825849890708923f,0.99907773733139038086f, +0.02454122900962829590f,0.99969881772994995117f,0.00613588467240333557f, +0.99998116493225097656f,-0.01227153837680816650f,0.99992471933364868164f, +-0.03067480400204658508f,0.99952942132949829102f,-0.04906767606735229492f, +0.99879544973373413086f,-0.06744392216205596924f,0.99772304296493530273f, +-0.08579730987548828125f,0.99631261825561523438f,-0.10412163287401199341f, +0.99456459283828735352f,-0.12241067737340927124f,0.99247956275939941406f, +-0.14065824449062347412f,0.99005818367004394531f,-0.15885815024375915527f, +0.98730140924453735352f,-0.17700421810150146484f,0.98421007394790649414f, +-0.19509032368659973145f,0.98078525066375732422f,-0.21311031281948089600f, +0.97702813148498535156f,-0.23105810582637786865f,0.97293996810913085938f, +-0.24892760813236236572f,0.96852207183837890625f,-0.26671275496482849121f, +0.96377605199813842773f,-0.28440752625465393066f,0.95870345830917358398f, +-0.30200594663619995117f,0.95330601930618286133f,-0.31950202584266662598f, +0.94758558273315429688f,-0.33688986301422119141f,0.94154405593872070312f, +-0.35416352748870849609f,0.93518352508544921875f,-0.37131720781326293945f, +0.92850607633590698242f,-0.38834503293037414551f,0.92151403427124023438f, +-0.40524131059646606445f,0.91420978307723999023f,-0.42200025916099548340f, +0.90659570693969726562f,-0.43861624598503112793f,0.89867448806762695312f, +-0.45508357882499694824f,0.89044874906539916992f,-0.47139674425125122070f, +0.88192129135131835938f,-0.48755016922950744629f,0.87309497594833374023f, +-0.50353837013244628906f,0.86397284269332885742f,-0.51935601234436035156f, +0.85455799102783203125f,-0.53499764204025268555f,0.84485357999801635742f, +-0.55045795440673828125f,0.83486288785934448242f,-0.56573182344436645508f, +0.82458931207656860352f,-0.58081394433975219727f,0.81403630971908569336f, +-0.59569931030273437500f,0.80320751667022705078f,-0.61038279533386230469f, +0.79210656881332397461f,-0.62485951185226440430f,0.78073722124099731445f, +-0.63912445306777954102f,0.76910334825515747070f,-0.65317285060882568359f, +0.75720882415771484375f,-0.66699993610382080078f,0.74505776166915893555f, +-0.68060100078582763672f,0.73265427350997924805f,-0.69397145509719848633f, +0.72000253200531005859f,-0.70710676908493041992f,0.70710676908493041992f, +-0.72000253200531005859f,0.69397145509719848633f,-0.73265427350997924805f, +0.68060100078582763672f,-0.74505776166915893555f,0.66699993610382080078f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76910334825515747070f, +0.63912445306777954102f,-0.78073722124099731445f,0.62485951185226440430f, +-0.79210656881332397461f,0.61038279533386230469f,-0.80320751667022705078f, +0.59569931030273437500f,-0.81403630971908569336f,0.58081394433975219727f, +-0.82458931207656860352f,0.56573182344436645508f,-0.83486288785934448242f, +0.55045795440673828125f,-0.84485357999801635742f,0.53499764204025268555f, +-0.85455799102783203125f,0.51935601234436035156f,-0.86397284269332885742f, +0.50353837013244628906f,-0.87309497594833374023f,0.48755016922950744629f, +-0.88192129135131835938f,0.47139674425125122070f,-0.89044874906539916992f, +0.45508357882499694824f,-0.89867448806762695312f,0.43861624598503112793f, +-0.90659570693969726562f,0.42200025916099548340f,-0.91420978307723999023f, +0.40524131059646606445f,-0.92151403427124023438f,0.38834503293037414551f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93518352508544921875f, +0.35416352748870849609f,-0.94154405593872070312f,0.33688986301422119141f, +-0.94758558273315429688f,0.31950202584266662598f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95870345830917358398f,0.28440752625465393066f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96852207183837890625f, +0.24892760813236236572f,-0.97293996810913085938f,0.23105810582637786865f, +-0.97702813148498535156f,0.21311031281948089600f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98421007394790649414f,0.17700421810150146484f, +-0.98730140924453735352f,0.15885815024375915527f,-0.99005818367004394531f, +0.14065824449062347412f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99772304296493530273f,0.06744392216205596924f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99952942132949829102f, +0.03067480400204658508f,-0.99992471933364868164f,0.01227153837680816650f, +-0.99998116493225097656f,-0.00613588467240333557f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99907773733139038086f,-0.04293825849890708923f, +-0.99811810255050659180f,-0.06132073700428009033f,-0.99682027101516723633f, +-0.07968243956565856934f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.99321192502975463867f,-0.11631862819194793701f,-0.99090266227722167969f, +-0.13458070158958435059f,-0.98825758695602416992f,-0.15279719233512878418f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.98196387290954589844f, +-0.18906866014003753662f,-0.97831737995147705078f,-0.20711137354373931885f, +-0.97433936595916748047f,-0.22508391737937927246f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.96539443731307983398f,-0.26079410314559936523f, +-0.96043050289154052734f,-0.27851969003677368164f,-0.95514118671417236328f, +-0.29615089297294616699f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.94359344244003295898f,-0.33110630512237548828f,-0.93733900785446166992f, +-0.34841868281364440918f,-0.93076694011688232422f,-0.36561298370361328125f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.91667908430099487305f, +-0.39962419867515563965f,-0.90916800498962402344f,-0.41642954945564270020f, +-0.90134882926940917969f,-0.43309381604194641113f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.88479709625244140625f,-0.46597650647163391113f, +-0.87607008218765258789f,-0.48218378424644470215f,-0.86704623699188232422f, +-0.49822765588760375977f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.84812033176422119141f,-0.52980363368988037109f,-0.83822470903396606445f, +-0.54532498121261596680f,-0.82804507017135620117f,-0.56066155433654785156f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.80684757232666015625f, +-0.59075969457626342773f,-0.79583692550659179688f,-0.60551106929779052734f, +-0.78455656766891479492f,-0.62005722522735595703f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.76120239496231079102f,-0.64851438999176025391f, +-0.74913638830184936523f,-0.66241580247879028320f,-0.73681658506393432617f, +-0.67609268426895141602f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.71143221855163574219f,-0.70275473594665527344f,-0.69837623834609985352f, +-0.71573084592819213867f,-0.68508368730545043945f,-0.72846436500549316406f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.65780669450759887695f, +-0.75318682193756103516f,-0.64383155107498168945f,-0.76516723632812500000f, +-0.62963825464248657227f,-0.77688848972320556641f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.60061645507812500000f,-0.79953724145889282227f, +-0.58579784631729125977f,-0.81045717000961303711f,-0.57078075408935546875f, +-0.82110249996185302734f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.54017144441604614258f,-0.84155499935150146484f,-0.52458965778350830078f, +-0.85135519504547119141f,-0.50883013010025024414f,-0.86086696386337280273f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.47679921984672546387f, +-0.87901222705841064453f,-0.46053871512413024902f,-0.88763964176177978516f, +-0.44412213563919067383f,-0.89596623182296752930f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.41084316372871398926f,-0.91170603036880493164f, +-0.39399203658103942871f,-0.91911387443542480469f,-0.37700742483139038086f, +-0.92621022462844848633f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.34266072511672973633f,-0.93945920467376708984f,-0.32531028985977172852f, +-0.94560730457305908203f,-0.30784964561462402344f,-0.95143502950668334961f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.27262136340141296387f, +-0.96212142705917358398f,-0.25486564636230468750f,-0.96697646379470825195f, +-0.23702360689640045166f,-0.97150391340255737305f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.20110464096069335938f,-0.97956979274749755859f, +-0.18303988873958587646f,-0.98310548067092895508f,-0.16491311788558959961f, +-0.98630809783935546875f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.12849810719490051270f,-0.99170976877212524414f,-0.11022220551967620850f, +-0.99390697479248046875f,-0.09190895408391952515f,-0.99576741456985473633f, +-0.07356456667184829712f,-0.99729043245315551758f,-0.05519524589180946350f, +-0.99847555160522460938f,-0.03680722415447235107f,-0.99932235479354858398f, +-0.01840673014521598816f,-0.99983060359954833984f,1.00000000000000000000f, +0.00000000000000000000f,0.99729043245315551758f,0.07356456667184829712f, +0.98917651176452636719f,0.14673046767711639404f,0.97570210695266723633f, +0.21910123527050018311f,0.95694035291671752930f,0.29028466343879699707f, +0.93299281597137451172f,0.35989505052566528320f,0.90398931503295898438f, +0.42755508422851562500f,0.87008696794509887695f,0.49289819598197937012f, +0.83146959543228149414f,0.55557024478912353516f,0.78834640979766845703f, +0.61523157358169555664f,0.74095112085342407227f,0.67155897617340087891f, +0.68954056501388549805f,0.72424709796905517578f,0.63439327478408813477f, +0.77301043272018432617f,0.57580816745758056641f,0.81758481264114379883f, +0.51410275697708129883f,0.85772860050201416016f,0.44961133599281311035f, +0.89322429895401000977f,0.38268342614173889160f,0.92387950420379638672f, +0.31368175148963928223f,0.94952815771102905273f,0.24298018217086791992f, +0.97003126144409179688f,0.17096188664436340332f,0.98527765274047851562f, +0.09801714122295379639f,0.99518471956253051758f,0.02454122900962829590f, +0.99969881772994995117f,-0.04906767606735229492f,0.99879544973373413086f, +-0.12241067737340927124f,0.99247956275939941406f,-0.19509032368659973145f, +0.98078525066375732422f,-0.26671275496482849121f,0.96377605199813842773f, +-0.33688986301422119141f,0.94154405593872070312f,-0.40524131059646606445f, +0.91420978307723999023f,-0.47139674425125122070f,0.88192129135131835938f, +-0.53499764204025268555f,0.84485357999801635742f,-0.59569931030273437500f, +0.80320751667022705078f,-0.65317285060882568359f,0.75720882415771484375f, +-0.70710676908493041992f,0.70710676908493041992f,-0.75720882415771484375f, +0.65317285060882568359f,-0.80320751667022705078f,0.59569931030273437500f, +-0.84485357999801635742f,0.53499764204025268555f,-0.88192129135131835938f, +0.47139674425125122070f,-0.91420978307723999023f,0.40524131059646606445f, +-0.94154405593872070312f,0.33688986301422119141f,-0.96377605199813842773f, +0.26671275496482849121f,-0.98078525066375732422f,0.19509032368659973145f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99969881772994995117f,-0.02454122900962829590f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.98527765274047851562f, +-0.17096188664436340332f,-0.97003126144409179688f,-0.24298018217086791992f, +-0.94952815771102905273f,-0.31368175148963928223f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.89322429895401000977f,-0.44961133599281311035f, +-0.85772860050201416016f,-0.51410275697708129883f,-0.81758481264114379883f, +-0.57580816745758056641f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.72424709796905517578f,-0.68954056501388549805f,-0.67155897617340087891f, +-0.74095112085342407227f,-0.61523157358169555664f,-0.78834640979766845703f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.49289819598197937012f, +-0.87008696794509887695f,-0.42755508422851562500f,-0.90398931503295898438f, +-0.35989505052566528320f,-0.93299281597137451172f,-0.29028466343879699707f, +-0.95694035291671752930f,-0.21910123527050018311f,-0.97570210695266723633f, +-0.14673046767711639404f,-0.98917651176452636719f,-0.07356456667184829712f, +-0.99729043245315551758f,1.00000000000000000000f,0.00000000000000000000f, +0.95694035291671752930f,0.29028466343879699707f,0.83146959543228149414f, +0.55557024478912353516f,0.63439327478408813477f,0.77301043272018432617f, +0.38268342614173889160f,0.92387950420379638672f,0.09801714122295379639f, +0.99518471956253051758f,-0.19509032368659973145f,0.98078525066375732422f, +-0.47139674425125122070f,0.88192129135131835938f,-0.70710676908493041992f, +0.70710676908493041992f,-0.88192129135131835938f,0.47139674425125122070f, +-0.98078525066375732422f,0.19509032368659973145f,-0.99518471956253051758f, +-0.09801714122295379639f,-0.92387950420379638672f,-0.38268342614173889160f, +-0.77301043272018432617f,-0.63439327478408813477f,-0.55557024478912353516f, +-0.83146959543228149414f,-0.29028466343879699707f,-0.95694035291671752930f, +1.00000000000000000000f,0.00000000000000000000f,0.38268342614173889160f, +0.92387950420379638672f,-0.70710676908493041992f,0.70710676908493041992f, +-0.92387950420379638672f,-0.38268342614173889160f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]={ +0,2048,2560,2688,2720,0,}; + +float32_t rearranged_twiddle_stride1_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99999880790710449219f, +0.00153398013208061457f,0.99999529123306274414f,0.00306795677170157433f, +0.99998939037322998047f,0.00460192607715725899f,0.99998116493225097656f, +0.00613588467240333557f,0.99997061491012573242f,0.00766982883214950562f, +0.99995762109756469727f,0.00920375436544418335f,0.99994236230850219727f, +0.01073765940964221954f,0.99992471933364868164f,0.01227153837680816650f, +0.99990469217300415039f,0.01380538847297430038f,0.99988234043121337891f, +0.01533920597285032272f,0.99985766410827636719f,0.01687298715114593506f, +0.99983060359954833984f,0.01840673014521598816f,0.99980115890502929688f, +0.01994042843580245972f,0.99976938962936401367f,0.02147408016026020050f, +0.99973529577255249023f,0.02300768159329891205f,0.99969881772994995117f, +0.02454122900962829590f,0.99966001510620117188f,0.02607471868395805359f, +0.99961882829666137695f,0.02760814502835273743f,0.99957531690597534180f, +0.02914150804281234741f,0.99952942132949829102f,0.03067480400204658508f, +0.99948120117187500000f,0.03220802545547485352f,0.99943059682846069336f, +0.03374117240309715271f,0.99937766790390014648f,0.03527423739433288574f, +0.99932235479354858398f,0.03680722415447235107f,0.99926477670669555664f, +0.03834012150764465332f,0.99920475482940673828f,0.03987292572855949402f, +0.99914240837097167969f,0.04140564054250717163f,0.99907773733139038086f, +0.04293825849890708923f,0.99901068210601806641f,0.04447077214717864990f, +0.99894130229949951172f,0.04600318148732185364f,0.99886953830718994141f, +0.04753548279404640198f,0.99879544973373413086f,0.04906767606735229492f, +0.99871903657913208008f,0.05059975013136863708f,0.99864023923873901367f, +0.05213170498609542847f,0.99855905771255493164f,0.05366353690624237061f, +0.99847555160522460938f,0.05519524589180946350f,0.99838972091674804688f, +0.05672682076692581177f,0.99830156564712524414f,0.05825826525688171387f, +0.99821102619171142578f,0.05978957191109657288f,0.99811810255050659180f, +0.06132073700428009033f,0.99802285432815551758f,0.06285175681114196777f, +0.99792528152465820312f,0.06438262760639190674f,0.99782532453536987305f, +0.06591334939002990723f,0.99772304296493530273f,0.06744392216205596924f, +0.99761843681335449219f,0.06897433102130889893f,0.99751144647598266602f, +0.07050457596778869629f,0.99740213155746459961f,0.07203464955091476440f, +0.99729043245315551758f,0.07356456667184829712f,0.99717640876770019531f, +0.07509429752826690674f,0.99706006050109863281f,0.07662386447191238403f, +0.99694132804870605469f,0.07815324515104293823f,0.99682027101516723633f, +0.07968243956565856934f,0.99669688940048217773f,0.08121144771575927734f, +0.99657112360000610352f,0.08274026215076446533f,0.99644303321838378906f, +0.08426889032125473022f,0.99631261825561523438f,0.08579730987548828125f, +0.99617981910705566406f,0.08732553571462631226f,0.99604469537734985352f, +0.08885355293750762939f,0.99590724706649780273f,0.09038136154413223267f, +0.99576741456985473633f,0.09190895408391952515f,0.99562525749206542969f, +0.09343633800745010376f,0.99548077583312988281f,0.09496349841356277466f, +0.99533390998840332031f,0.09649042785167694092f,0.99518471956253051758f, +0.09801714122295379639f,0.99503320455551147461f,0.09954361617565155029f, +0.99487930536270141602f,0.10106986016035079956f,0.99472314119338989258f, +0.10259586572647094727f,0.99456459283828735352f,0.10412163287401199341f, +0.99440366029739379883f,0.10564715415239334106f,0.99424046277999877930f, +0.10717242211103439331f,0.99407488107681274414f,0.10869744420051574707f, +0.99390697479248046875f,0.11022220551967620850f,0.99373674392700195312f, +0.11174671351909637451f,0.99356412887573242188f,0.11327095329761505127f, +0.99338918924331665039f,0.11479492485523223877f,0.99321192502975463867f, +0.11631862819194793701f,0.99303233623504638672f,0.11784206330776214600f, +0.99285042285919189453f,0.11936521530151367188f,0.99266612529754638672f, +0.12088808417320251465f,0.99247956275939941406f,0.12241067737340927124f, +0.99229061603546142578f,0.12393297255039215088f,0.99209928512573242188f, +0.12545497715473175049f,0.99190568923950195312f,0.12697669863700866699f, +0.99170976877212524414f,0.12849810719490051270f,0.99151146411895751953f, +0.13001921772956848145f,0.99131083488464355469f,0.13154003024101257324f, +0.99110794067382812500f,0.13306052982807159424f,0.99090266227722167969f, +0.13458070158958435059f,0.99069499969482421875f,0.13610057532787322998f, +0.99048507213592529297f,0.13762012124061584473f,0.99027281999588012695f, +0.13913933932781219482f,0.99005818367004394531f,0.14065824449062347412f, +0.98984128236770629883f,0.14217680692672729492f,0.98962199687957763672f, +0.14369502663612365723f,0.98940044641494750977f,0.14521291851997375488f, +0.98917651176452636719f,0.14673046767711639404f,0.98895025253295898438f, +0.14824767410755157471f,0.98872166872024536133f,0.14976453781127929688f, +0.98849081993103027344f,0.15128104388713836670f,0.98825758695602416992f, +0.15279719233512878418f,0.98802202939987182617f,0.15431296825408935547f, +0.98778414726257324219f,0.15582840144634246826f,0.98754394054412841797f, +0.15734346210956573486f,0.98730140924453735352f,0.15885815024375915527f, +0.98705655336380004883f,0.16037245094776153564f,0.98680937290191650391f, +0.16188639402389526367f,0.98655992746353149414f,0.16339994966983795166f, +0.98630809783935546875f,0.16491311788558959961f,0.98605394363403320312f, +0.16642589867115020752f,0.98579752445220947266f,0.16793829202651977539f, +0.98553872108459472656f,0.16945029795169830322f,0.98527765274047851562f, +0.17096188664436340332f,0.98501425981521606445f,0.17247308790683746338f, +0.98474848270416259766f,0.17398387193679809570f,0.98448044061660766602f, +0.17549425363540649414f,0.98421007394790649414f,0.17700421810150146484f, +0.98393744230270385742f,0.17851376533508300781f,0.98366242647171020508f, +0.18002289533615112305f,0.98338508605957031250f,0.18153160810470581055f, +0.98310548067092895508f,0.18303988873958587646f,0.98282355070114135742f, +0.18454773724079132080f,0.98253929615020751953f,0.18605515360832214355f, +0.98225271701812744141f,0.18756212294101715088f,0.98196387290954589844f, +0.18906866014003753662f,0.98167270421981811523f,0.19057475030422210693f, +0.98137921094894409180f,0.19208039343357086182f,0.98108339309692382812f, +0.19358558952808380127f,0.98078525066375732422f,0.19509032368659973145f, +0.98048484325408935547f,0.19659459590911865234f,0.98018211126327514648f, +0.19809840619564056396f,0.97987711429595947266f,0.19960175454616546631f, +0.97956979274749755859f,0.20110464096069335938f,0.97926014661788940430f, +0.20260703563690185547f,0.97894817590713500977f,0.20410896837711334229f, +0.97863394021987915039f,0.20561040937900543213f,0.97831737995147705078f, +0.20711137354373931885f,0.97799849510192871094f,0.20861184597015380859f, +0.97767734527587890625f,0.21011184155941009521f,0.97735387086868286133f, +0.21161133050918579102f,0.97702813148498535156f,0.21311031281948089600f, +0.97670006752014160156f,0.21460881829261779785f,0.97636973857879638672f, +0.21610680222511291504f,0.97603708505630493164f,0.21760427951812744141f, +0.97570210695266723633f,0.21910123527050018311f,0.97536486387252807617f, +0.22059768438339233398f,0.97502535581588745117f,0.22209362685680389404f, +0.97468352317810058594f,0.22358903288841247559f,0.97433936595916748047f, +0.22508391737937927246f,0.97399294376373291016f,0.22657826542854309082f, +0.97364425659179687500f,0.22807207703590393066f,0.97329324483871459961f, +0.22956536710262298584f,0.97293996810913085938f,0.23105810582637786865f, +0.97258436679840087891f,0.23255030810832977295f,0.97222650051116943359f, +0.23404195904731750488f,0.97186630964279174805f,0.23553305864334106445f, +0.97150391340255737305f,0.23702360689640045166f,0.97113913297653198242f, +0.23851358890533447266f,0.97077214717864990234f,0.24000301957130432129f, +0.97040283679962158203f,0.24149188399314880371f,0.97003126144409179688f, +0.24298018217086791992f,0.96965736150741577148f,0.24446789920330047607f, +0.96928125619888305664f,0.24595504999160766602f,0.96890282630920410156f, +0.24744161963462829590f,0.96852207183837890625f,0.24892760813236236572f, +0.96813911199569702148f,0.25041300058364868164f,0.96775382757186889648f, +0.25189781188964843750f,0.96736627817153930664f,0.25338202714920043945f, +0.96697646379470825195f,0.25486564636230468750f,0.96658438444137573242f, +0.25634866952896118164f,0.96618998050689697266f,0.25783109664916992188f, +0.96579337120056152344f,0.25931292772293090820f,0.96539443731307983398f, +0.26079410314559936523f,0.96499323844909667969f,0.26227471232414245605f, +0.96458977460861206055f,0.26375466585159301758f,0.96418404579162597656f, +0.26523402333259582520f,0.96377605199813842773f,0.26671275496482849121f, +0.96336579322814941406f,0.26819086074829101562f,0.96295326948165893555f, +0.26966831088066101074f,0.96253848075866699219f,0.27114516496658325195f, +0.96212142705917358398f,0.27262136340141296387f,0.96170204877853393555f, +0.27409690618515014648f,0.96128046512603759766f,0.27557182312011718750f, +0.96085661649703979492f,0.27704608440399169922f,0.96043050289154052734f, +0.27851969003677368164f,0.96000212430953979492f,0.27999264001846313477f, +0.95957154035568237305f,0.28146493434906005859f,0.95913863182067871094f, +0.28293657302856445312f,0.95870345830917358398f,0.28440752625465393066f, +0.95826607942581176758f,0.28587782382965087891f,0.95782643556594848633f, +0.28734746575355529785f,0.95738452672958374023f,0.28881642222404479980f, +0.95694035291671752930f,0.29028466343879699707f,0.95649391412734985352f, +0.29175224900245666504f,0.95604526996612548828f,0.29321914911270141602f, +0.95559436082839965820f,0.29468536376953125000f,0.95514118671417236328f, +0.29615089297294616699f,0.95468574762344360352f,0.29761570692062377930f, +0.95422810316085815430f,0.29907983541488647461f,0.95376819372177124023f, +0.30054324865341186523f,0.95330601930618286133f,0.30200594663619995117f, +0.95284163951873779297f,0.30346795916557312012f,0.95237499475479125977f, +0.30492922663688659668f,0.95190614461898803711f,0.30638980865478515625f, +0.95143502950668334961f,0.30784964561462402344f,0.95096164941787719727f, +0.30930876731872558594f,0.95048606395721435547f,0.31076714396476745605f, +0.95000827312469482422f,0.31222480535507202148f,0.94952815771102905273f, +0.31368175148963928223f,0.94904589653015136719f,0.31513792276382446289f, +0.94856137037277221680f,0.31659337878227233887f,0.94807457923889160156f, +0.31804808974266052246f,0.94758558273315429688f,0.31950202584266662598f, +0.94709438085556030273f,0.32095524668693542480f,0.94660091400146484375f, +0.32240769267082214355f,0.94610524177551269531f,0.32385936379432678223f, +0.94560730457305908203f,0.32531028985977172852f,0.94510722160339355469f, +0.32676044106483459473f,0.94460481405258178711f,0.32820984721183776855f, +0.94410026073455810547f,0.32965844869613647461f,0.94359344244003295898f, +0.33110630512237548828f,0.94308441877365112305f,0.33255335688591003418f, +0.94257318973541259766f,0.33399966359138488770f,0.94205975532531738281f, +0.33544513583183288574f,0.94154405593872070312f,0.33688986301422119141f, +0.94102615118026733398f,0.33833375573158264160f,0.94050604104995727539f, +0.33977687358856201172f,0.93998372554779052734f,0.34121921658515930176f, +0.93945920467376708984f,0.34266072511672973633f,0.93893247842788696289f, +0.34410142898559570312f,0.93840354681015014648f,0.34554132819175720215f, +0.93787235021591186523f,0.34698042273521423340f,0.93733900785446166992f, +0.34841868281364440918f,0.93680346012115478516f,0.34985613822937011719f, +0.93626564741134643555f,0.35129275918006896973f,0.93572568893432617188f, +0.35272854566574096680f,0.93518352508544921875f,0.35416352748870849609f, +0.93463915586471557617f,0.35559767484664916992f,0.93409252166748046875f, +0.35703095793724060059f,0.93354380130767822266f,0.35846340656280517578f, +0.93299281597137451172f,0.35989505052566528320f,0.93243962526321411133f, +0.36132580041885375977f,0.93188428878784179688f,0.36275571584701538086f, +0.93132668733596801758f,0.36418479681015014648f,0.93076694011688232422f, +0.36561298370361328125f,0.93020504713058471680f,0.36704033613204956055f, +0.92964088916778564453f,0.36846682429313659668f,0.92907458543777465820f, +0.36989244818687438965f,0.92850607633590698242f,0.37131720781326293945f, +0.92793542146682739258f,0.37274107336997985840f,0.92736250162124633789f, +0.37416407465934753418f,0.92678749561309814453f,0.37558618187904357910f, +0.92621022462844848633f,0.37700742483139038086f,0.92563080787658691406f, +0.37842774391174316406f,0.92504924535751342773f,0.37984719872474670410f, +0.92446547746658325195f,0.38126575946807861328f,0.92387950420379638672f, +0.38268342614173889160f,0.92329144477844238281f,0.38410019874572753906f, +0.92270112037658691406f,0.38551604747772216797f,0.92210865020751953125f, +0.38693100214004516602f,0.92151403427124023438f,0.38834503293037414551f, +0.92091721296310424805f,0.38975816965103149414f,0.92031830549240112305f, +0.39117038249969482422f,0.91971713304519653320f,0.39258167147636413574f, +0.91911387443542480469f,0.39399203658103942871f,0.91850841045379638672f, +0.39540147781372070312f,0.91790080070495605469f,0.39680999517440795898f, +0.91729098558425903320f,0.39821755886077880859f,0.91667908430099487305f, +0.39962419867515563965f,0.91606497764587402344f,0.40102988481521606445f, +0.91544872522354125977f,0.40243464708328247070f,0.91483032703399658203f, +0.40383845567703247070f,0.91420978307723999023f,0.40524131059646606445f, +0.91358703374862670898f,0.40664321184158325195f,0.91296219825744628906f, +0.40804415941238403320f,0.91233515739440917969f,0.40944415330886840820f, +0.91170603036880493164f,0.41084316372871398926f,0.91107475757598876953f, +0.41224122047424316406f,0.91044127941131591797f,0.41363832354545593262f, +0.90980571508407592773f,0.41503441333770751953f,0.90916800498962402344f, +0.41642954945564270020f,0.90852808952331542969f,0.41782370209693908691f, +0.90788608789443969727f,0.41921690106391906738f,0.90724200010299682617f, +0.42060908675193786621f,0.90659570693969726562f,0.42200025916099548340f, +0.90594726800918579102f,0.42339047789573669434f,0.90529674291610717773f, +0.42477968335151672363f,0.90464407205581665039f,0.42616787552833557129f, +0.90398931503295898438f,0.42755508422851562500f,0.90333235263824462891f, +0.42894127964973449707f,0.90267330408096313477f,0.43032649159431457520f, +0.90201216936111450195f,0.43171066045761108398f,0.90134882926940917969f, +0.43309381604194641113f,0.90068340301513671875f,0.43447595834732055664f, +0.90001589059829711914f,0.43585708737373352051f,0.89934623241424560547f, +0.43723717331886291504f,0.89867448806762695312f,0.43861624598503112793f, +0.89800059795379638672f,0.43999427556991577148f,0.89732456207275390625f, +0.44137126207351684570f,0.89664649963378906250f,0.44274723529815673828f, +0.89596623182296752930f,0.44412213563919067383f,0.89528393745422363281f, +0.44549602270126342773f,0.89459949731826782227f,0.44686883687973022461f, +0.89391297101974487305f,0.44824060797691345215f,0.89322429895401000977f, +0.44961133599281311035f,0.89253354072570800781f,0.45098099112510681152f, +0.89184069633483886719f,0.45234957337379455566f,0.89114576578140258789f, +0.45371711254119873047f,0.89044874906539916992f,0.45508357882499694824f, +0.88974958658218383789f,0.45644897222518920898f,0.88904833793640136719f, +0.45781329274177551270f,0.88834506273269653320f,0.45917654037475585938f, +0.88763964176177978516f,0.46053871512413024902f,0.88693213462829589844f, +0.46189978718757629395f,0.88622254133224487305f,0.46325978636741638184f, +0.88551086187362670898f,0.46461868286132812500f,0.88479709625244140625f, +0.46597650647163391113f,0.88408124446868896484f,0.46733319759368896484f, +0.88336336612701416016f,0.46868881583213806152f,0.88264334201812744141f, +0.47004333138465881348f,0.88192129135131835938f,0.47139674425125122070f, +0.88119709491729736328f,0.47274902462959289551f,0.88047087192535400391f, +0.47410020232200622559f,0.87974262237548828125f,0.47545027732849121094f, +0.87901222705841064453f,0.47679921984672546387f,0.87827980518341064453f, +0.47814705967903137207f,0.87754529714584350586f,0.47949376702308654785f, +0.87680870294570922852f,0.48083934187889099121f,0.87607008218765258789f, +0.48218378424644470215f,0.87532937526702880859f,0.48352706432342529297f, +0.87458664178848266602f,0.48486924171447753906f,0.87384182214736938477f, +0.48621028661727905273f,0.87309497594833374023f,0.48755016922950744629f, +0.87234604358673095703f,0.48888888955116271973f,0.87159508466720581055f, +0.49022647738456726074f,0.87084203958511352539f,0.49156290292739868164f, +0.87008696794509887695f,0.49289819598197937012f,0.86932986974716186523f, +0.49423229694366455078f,0.86857068538665771484f,0.49556526541709899902f, +0.86780947446823120117f,0.49689704179763793945f,0.86704623699188232422f, +0.49822765588760375977f,0.86628097295761108398f,0.49955710768699645996f, +0.86551362276077270508f,0.50088536739349365234f,0.86474424600601196289f, +0.50221246480941772461f,0.86397284269332885742f,0.50353837013244628906f, +0.86319941282272338867f,0.50486308336257934570f,0.86242395639419555664f, +0.50618666410446166992f,0.86164647340774536133f,0.50750899314880371094f, +0.86086696386337280273f,0.50883013010025024414f,0.86008536815643310547f, +0.51015007495880126953f,0.85930180549621582031f,0.51146882772445678711f, +0.85851621627807617188f,0.51278638839721679688f,0.85772860050201416016f, +0.51410275697708129883f,0.85693895816802978516f,0.51541787385940551758f, +0.85614734888076782227f,0.51673179864883422852f,0.85535365343093872070f, +0.51804453134536743164f,0.85455799102783203125f,0.51935601234436035156f, +0.85376030206680297852f,0.52066624164581298828f,0.85296058654785156250f, +0.52197527885437011719f,0.85215890407562255859f,0.52328312397003173828f, +0.85135519504547119141f,0.52458965778350830078f,0.85054945945739746094f, +0.52589499950408935547f,0.84974175691604614258f,0.52719914913177490234f, +0.84893202781677246094f,0.52850198745727539062f,0.84812033176422119141f, +0.52980363368988037109f,0.84730660915374755859f,0.53110402822494506836f, +0.84649091958999633789f,0.53240311145782470703f,0.84567326307296752930f, +0.53370100259780883789f,0.84485357999801635742f,0.53499764204025268555f, +0.84403187036514282227f,0.53629297018051147461f,0.84320825338363647461f, +0.53758704662322998047f,0.84238260984420776367f,0.53887993097305297852f, +0.84155499935150146484f,0.54017144441604614258f,0.84072536230087280273f, +0.54146176576614379883f,0.83989381790161132812f,0.54275077581405639648f, +0.83906024694442749023f,0.54403853416442871094f,0.83822470903396606445f, +0.54532498121261596680f,0.83738720417022705078f,0.54661017656326293945f, +0.83654773235321044922f,0.54789406061172485352f,0.83570629358291625977f, +0.54917663335800170898f,0.83486288785934448242f,0.55045795440673828125f, +0.83401751518249511719f,0.55173796415328979492f,0.83317017555236816406f, +0.55301672220230102539f,0.83232086896896362305f,0.55429410934448242188f, +0.83146959543228149414f,0.55557024478912353516f,0.83061641454696655273f, +0.55684500932693481445f,0.82976120710372924805f,0.55811852216720581055f, +0.82890409231185913086f,0.55939072370529174805f,0.82804507017135620117f, +0.56066155433654785156f,0.82718402147293090820f,0.56193113327026367188f, +0.82632106542587280273f,0.56319934129714965820f,0.82545614242553710938f, +0.56446623802185058594f,0.82458931207656860352f,0.56573182344436645508f, +0.82372051477432250977f,0.56699603796005249023f,0.82284981012344360352f, +0.56825894117355346680f,0.82197713851928710938f,0.56952053308486938477f, +0.82110249996185302734f,0.57078075408935546875f,0.82022595405578613281f, +0.57203960418701171875f,0.81934750080108642578f,0.57329714298248291016f, +0.81846714019775390625f,0.57455337047576904297f,0.81758481264114379883f, +0.57580816745758056641f,0.81670057773590087891f,0.57706165313720703125f, +0.81581443548202514648f,0.57831376791000366211f,0.81492632627487182617f, +0.57956457138061523438f,0.81403630971908569336f,0.58081394433975219727f, +0.81314438581466674805f,0.58206200599670410156f,0.81225061416625976562f, +0.58330863714218139648f,0.81135487556457519531f,0.58455395698547363281f, +0.81045717000961303711f,0.58579784631729125977f,0.80955761671066284180f, +0.58704036474227905273f,0.80865615606307983398f,0.58828157186508178711f, +0.80775284767150878906f,0.58952128887176513672f,0.80684757232666015625f, +0.59075969457626342773f,0.80594038963317871094f,0.59199666976928710938f, +0.80503135919570922852f,0.59323227405548095703f,0.80412036180496215820f, +0.59446650743484497070f,0.80320751667022705078f,0.59569931030273437500f, +0.80229282379150390625f,0.59693068265914916992f,0.80137616395950317383f, +0.59816068410873413086f,0.80045765638351440430f,0.59938931465148925781f, +0.79953724145889282227f,0.60061645507812500000f,0.79861497879028320312f, +0.60184222459793090820f,0.79769086837768554688f,0.60306662321090698242f, +0.79676479101181030273f,0.60428953170776367188f,0.79583692550659179688f, +0.60551106929779052734f,0.79490715265274047852f,0.60673111677169799805f, +0.79397547245025634766f,0.60794979333877563477f,0.79304194450378417969f, +0.60916703939437866211f,0.79210656881332397461f,0.61038279533386230469f, +0.79116934537887573242f,0.61159718036651611328f,0.79023021459579467773f, +0.61281007528305053711f,0.78928923606872558594f,0.61402153968811035156f, +0.78834640979766845703f,0.61523157358169555664f,0.78740173578262329102f, +0.61644017696380615234f,0.78645521402359008789f,0.61764729022979736328f, +0.78550684452056884766f,0.61885297298431396484f,0.78455656766891479492f, +0.62005722522735595703f,0.78360450267791748047f,0.62125998735427856445f, +0.78265058994293212891f,0.62246125936508178711f,0.78169482946395874023f, +0.62366110086441040039f,0.78073722124099731445f,0.62485951185226440430f, +0.77977776527404785156f,0.62605637311935424805f,0.77881652116775512695f, +0.62725180387496948242f,0.77785342931747436523f,0.62844574451446533203f, +0.77688848972320556641f,0.62963825464248657227f,0.77592170238494873047f, +0.63082921504974365234f,0.77495312690734863281f,0.63201874494552612305f, +0.77398270368576049805f,0.63320678472518920898f,0.77301043272018432617f, +0.63439327478408813477f,0.77203637361526489258f,0.63557833433151245117f, +0.77106052637100219727f,0.63676184415817260742f,0.77008283138275146484f, +0.63794392347335815430f,0.76910334825515747070f,0.63912445306777954102f, +0.76812201738357543945f,0.64030349254608154297f,0.76713889837265014648f, +0.64148104190826416016f,0.76615399122238159180f,0.64265704154968261719f, +0.76516723632812500000f,0.64383155107498168945f,0.76417875289916992188f, +0.64500451087951660156f,0.76318842172622680664f,0.64617604017257690430f, +0.76219630241394042969f,0.64734596014022827148f,0.76120239496231079102f, +0.64851438999176025391f,0.76020669937133789062f,0.64968132972717285156f, +0.75920921564102172852f,0.65084666013717651367f,0.75820988416671752930f, +0.65201056003570556641f,0.75720882415771484375f,0.65317285060882568359f, +0.75620597600936889648f,0.65433359146118164062f,0.75520139932632446289f, +0.65549284219741821289f,0.75419497489929199219f,0.65665054321289062500f, +0.75318682193756103516f,0.65780669450759887695f,0.75217682123184204102f, +0.65896129608154296875f,0.75116515159606933594f,0.66011434793472290039f, +0.75015163421630859375f,0.66126585006713867188f,0.74913638830184936523f, +0.66241580247879028320f,0.74811935424804687500f,0.66356414556503295898f, +0.74710059165954589844f,0.66471099853515625000f,0.74608010053634643555f, +0.66585624217987060547f,0.74505776166915893555f,0.66699993610382080078f, +0.74403375387191772461f,0.66814202070236206055f,0.74300795793533325195f, +0.66928261518478393555f,0.74198043346405029297f,0.67042154073715209961f, +0.74095112085342407227f,0.67155897617340087891f,0.73992007970809936523f, +0.67269474267959594727f,0.73888731002807617188f,0.67382901906967163086f, +0.73785281181335449219f,0.67496162652969360352f,0.73681658506393432617f, +0.67609268426895141602f,0.73577857017517089844f,0.67722219228744506836f, +0.73473888635635375977f,0.67835003137588500977f,0.73369741439819335938f, +0.67947632074356079102f,0.73265427350997924805f,0.68060100078582763672f, +0.73160940408706665039f,0.68172407150268554688f,0.73056274652481079102f, +0.68284553289413452148f,0.72951442003250122070f,0.68396538496017456055f, +0.72846436500549316406f,0.68508368730545043945f,0.72741264104843139648f, +0.68620032072067260742f,0.72635912895202636719f,0.68731534481048583984f, +0.72530394792556762695f,0.68842875957489013672f,0.72424709796905517578f, +0.68954056501388549805f,0.72318845987319946289f,0.69065070152282714844f, +0.72212821245193481445f,0.69175922870635986328f,0.72106617689132690430f, +0.69286614656448364258f,0.72000253200531005859f,0.69397145509719848633f, +0.71893709897994995117f,0.69507509469985961914f,0.71787005662918090820f, +0.69617712497711181641f,0.71680128574371337891f,0.69727748632431030273f, +0.71573084592819213867f,0.69837623834609985352f,0.71465867757797241211f, +0.69947332143783569336f,0.71358484029769897461f,0.70056879520416259766f, +0.71250939369201660156f,0.70166260004043579102f,0.71143221855163574219f, +0.70275473594665527344f,0.71035337448120117188f,0.70384526252746582031f, +0.70927280187606811523f,0.70493406057357788086f,0.70819061994552612305f, +0.70602124929428100586f,0.70710676908493041992f,0.70710676908493041992f, +0.70602124929428100586f,0.70819061994552612305f,0.70493406057357788086f, +0.70927280187606811523f,0.70384526252746582031f,0.71035337448120117188f, +0.70275473594665527344f,0.71143221855163574219f,0.70166260004043579102f, +0.71250939369201660156f,0.70056879520416259766f,0.71358484029769897461f, +0.69947332143783569336f,0.71465867757797241211f,0.69837623834609985352f, +0.71573084592819213867f,0.69727748632431030273f,0.71680128574371337891f, +0.69617712497711181641f,0.71787005662918090820f,0.69507509469985961914f, +0.71893709897994995117f,0.69397145509719848633f,0.72000253200531005859f, +0.69286614656448364258f,0.72106617689132690430f,0.69175922870635986328f, +0.72212821245193481445f,0.69065070152282714844f,0.72318845987319946289f, +0.68954056501388549805f,0.72424709796905517578f,0.68842875957489013672f, +0.72530394792556762695f,0.68731534481048583984f,0.72635912895202636719f, +0.68620032072067260742f,0.72741264104843139648f,0.68508368730545043945f, +0.72846436500549316406f,0.68396538496017456055f,0.72951442003250122070f, +0.68284553289413452148f,0.73056274652481079102f,0.68172407150268554688f, +0.73160940408706665039f,0.68060100078582763672f,0.73265427350997924805f, +0.67947632074356079102f,0.73369741439819335938f,0.67835003137588500977f, +0.73473888635635375977f,0.67722219228744506836f,0.73577857017517089844f, +0.67609268426895141602f,0.73681658506393432617f,0.67496162652969360352f, +0.73785281181335449219f,0.67382901906967163086f,0.73888731002807617188f, +0.67269474267959594727f,0.73992007970809936523f,0.67155897617340087891f, +0.74095112085342407227f,0.67042154073715209961f,0.74198043346405029297f, +0.66928261518478393555f,0.74300795793533325195f,0.66814202070236206055f, +0.74403375387191772461f,0.66699993610382080078f,0.74505776166915893555f, +0.66585624217987060547f,0.74608010053634643555f,0.66471099853515625000f, +0.74710059165954589844f,0.66356414556503295898f,0.74811935424804687500f, +0.66241580247879028320f,0.74913638830184936523f,0.66126585006713867188f, +0.75015163421630859375f,0.66011434793472290039f,0.75116515159606933594f, +0.65896129608154296875f,0.75217682123184204102f,0.65780669450759887695f, +0.75318682193756103516f,0.65665054321289062500f,0.75419497489929199219f, +0.65549284219741821289f,0.75520139932632446289f,0.65433359146118164062f, +0.75620597600936889648f,0.65317285060882568359f,0.75720882415771484375f, +0.65201056003570556641f,0.75820988416671752930f,0.65084666013717651367f, +0.75920921564102172852f,0.64968132972717285156f,0.76020669937133789062f, +0.64851438999176025391f,0.76120239496231079102f,0.64734596014022827148f, +0.76219630241394042969f,0.64617604017257690430f,0.76318842172622680664f, +0.64500451087951660156f,0.76417875289916992188f,0.64383155107498168945f, +0.76516723632812500000f,0.64265704154968261719f,0.76615399122238159180f, +0.64148104190826416016f,0.76713889837265014648f,0.64030349254608154297f, +0.76812201738357543945f,0.63912445306777954102f,0.76910334825515747070f, +0.63794392347335815430f,0.77008283138275146484f,0.63676184415817260742f, +0.77106052637100219727f,0.63557833433151245117f,0.77203637361526489258f, +0.63439327478408813477f,0.77301043272018432617f,0.63320678472518920898f, +0.77398270368576049805f,0.63201874494552612305f,0.77495312690734863281f, +0.63082921504974365234f,0.77592170238494873047f,0.62963825464248657227f, +0.77688848972320556641f,0.62844574451446533203f,0.77785342931747436523f, +0.62725180387496948242f,0.77881652116775512695f,0.62605637311935424805f, +0.77977776527404785156f,0.62485951185226440430f,0.78073722124099731445f, +0.62366110086441040039f,0.78169482946395874023f,0.62246125936508178711f, +0.78265058994293212891f,0.62125998735427856445f,0.78360450267791748047f, +0.62005722522735595703f,0.78455656766891479492f,0.61885297298431396484f, +0.78550684452056884766f,0.61764729022979736328f,0.78645521402359008789f, +0.61644017696380615234f,0.78740173578262329102f,0.61523157358169555664f, +0.78834640979766845703f,0.61402153968811035156f,0.78928923606872558594f, +0.61281007528305053711f,0.79023021459579467773f,0.61159718036651611328f, +0.79116934537887573242f,0.61038279533386230469f,0.79210656881332397461f, +0.60916703939437866211f,0.79304194450378417969f,0.60794979333877563477f, +0.79397547245025634766f,0.60673111677169799805f,0.79490715265274047852f, +0.60551106929779052734f,0.79583692550659179688f,0.60428953170776367188f, +0.79676479101181030273f,0.60306662321090698242f,0.79769086837768554688f, +0.60184222459793090820f,0.79861497879028320312f,0.60061645507812500000f, +0.79953724145889282227f,0.59938931465148925781f,0.80045765638351440430f, +0.59816068410873413086f,0.80137616395950317383f,0.59693068265914916992f, +0.80229282379150390625f,0.59569931030273437500f,0.80320751667022705078f, +0.59446650743484497070f,0.80412036180496215820f,0.59323227405548095703f, +0.80503135919570922852f,0.59199666976928710938f,0.80594038963317871094f, +0.59075969457626342773f,0.80684757232666015625f,0.58952128887176513672f, +0.80775284767150878906f,0.58828157186508178711f,0.80865615606307983398f, +0.58704036474227905273f,0.80955761671066284180f,0.58579784631729125977f, +0.81045717000961303711f,0.58455395698547363281f,0.81135487556457519531f, +0.58330863714218139648f,0.81225061416625976562f,0.58206200599670410156f, +0.81314438581466674805f,0.58081394433975219727f,0.81403630971908569336f, +0.57956457138061523438f,0.81492632627487182617f,0.57831376791000366211f, +0.81581443548202514648f,0.57706165313720703125f,0.81670057773590087891f, +0.57580816745758056641f,0.81758481264114379883f,0.57455337047576904297f, +0.81846714019775390625f,0.57329714298248291016f,0.81934750080108642578f, +0.57203960418701171875f,0.82022595405578613281f,0.57078075408935546875f, +0.82110249996185302734f,0.56952053308486938477f,0.82197713851928710938f, +0.56825894117355346680f,0.82284981012344360352f,0.56699603796005249023f, +0.82372051477432250977f,0.56573182344436645508f,0.82458931207656860352f, +0.56446623802185058594f,0.82545614242553710938f,0.56319934129714965820f, +0.82632106542587280273f,0.56193113327026367188f,0.82718402147293090820f, +0.56066155433654785156f,0.82804507017135620117f,0.55939072370529174805f, +0.82890409231185913086f,0.55811852216720581055f,0.82976120710372924805f, +0.55684500932693481445f,0.83061641454696655273f,0.55557024478912353516f, +0.83146959543228149414f,0.55429410934448242188f,0.83232086896896362305f, +0.55301672220230102539f,0.83317017555236816406f,0.55173796415328979492f, +0.83401751518249511719f,0.55045795440673828125f,0.83486288785934448242f, +0.54917663335800170898f,0.83570629358291625977f,0.54789406061172485352f, +0.83654773235321044922f,0.54661017656326293945f,0.83738720417022705078f, +0.54532498121261596680f,0.83822470903396606445f,0.54403853416442871094f, +0.83906024694442749023f,0.54275077581405639648f,0.83989381790161132812f, +0.54146176576614379883f,0.84072536230087280273f,0.54017144441604614258f, +0.84155499935150146484f,0.53887993097305297852f,0.84238260984420776367f, +0.53758704662322998047f,0.84320825338363647461f,0.53629297018051147461f, +0.84403187036514282227f,0.53499764204025268555f,0.84485357999801635742f, +0.53370100259780883789f,0.84567326307296752930f,0.53240311145782470703f, +0.84649091958999633789f,0.53110402822494506836f,0.84730660915374755859f, +0.52980363368988037109f,0.84812033176422119141f,0.52850198745727539062f, +0.84893202781677246094f,0.52719914913177490234f,0.84974175691604614258f, +0.52589499950408935547f,0.85054945945739746094f,0.52458965778350830078f, +0.85135519504547119141f,0.52328312397003173828f,0.85215890407562255859f, +0.52197527885437011719f,0.85296058654785156250f,0.52066624164581298828f, +0.85376030206680297852f,0.51935601234436035156f,0.85455799102783203125f, +0.51804453134536743164f,0.85535365343093872070f,0.51673179864883422852f, +0.85614734888076782227f,0.51541787385940551758f,0.85693895816802978516f, +0.51410275697708129883f,0.85772860050201416016f,0.51278638839721679688f, +0.85851621627807617188f,0.51146882772445678711f,0.85930180549621582031f, +0.51015007495880126953f,0.86008536815643310547f,0.50883013010025024414f, +0.86086696386337280273f,0.50750899314880371094f,0.86164647340774536133f, +0.50618666410446166992f,0.86242395639419555664f,0.50486308336257934570f, +0.86319941282272338867f,0.50353837013244628906f,0.86397284269332885742f, +0.50221246480941772461f,0.86474424600601196289f,0.50088536739349365234f, +0.86551362276077270508f,0.49955710768699645996f,0.86628097295761108398f, +0.49822765588760375977f,0.86704623699188232422f,0.49689704179763793945f, +0.86780947446823120117f,0.49556526541709899902f,0.86857068538665771484f, +0.49423229694366455078f,0.86932986974716186523f,0.49289819598197937012f, +0.87008696794509887695f,0.49156290292739868164f,0.87084203958511352539f, +0.49022647738456726074f,0.87159508466720581055f,0.48888888955116271973f, +0.87234604358673095703f,0.48755016922950744629f,0.87309497594833374023f, +0.48621028661727905273f,0.87384182214736938477f,0.48486924171447753906f, +0.87458664178848266602f,0.48352706432342529297f,0.87532937526702880859f, +0.48218378424644470215f,0.87607008218765258789f,0.48083934187889099121f, +0.87680870294570922852f,0.47949376702308654785f,0.87754529714584350586f, +0.47814705967903137207f,0.87827980518341064453f,0.47679921984672546387f, +0.87901222705841064453f,0.47545027732849121094f,0.87974262237548828125f, +0.47410020232200622559f,0.88047087192535400391f,0.47274902462959289551f, +0.88119709491729736328f,0.47139674425125122070f,0.88192129135131835938f, +0.47004333138465881348f,0.88264334201812744141f,0.46868881583213806152f, +0.88336336612701416016f,0.46733319759368896484f,0.88408124446868896484f, +0.46597650647163391113f,0.88479709625244140625f,0.46461868286132812500f, +0.88551086187362670898f,0.46325978636741638184f,0.88622254133224487305f, +0.46189978718757629395f,0.88693213462829589844f,0.46053871512413024902f, +0.88763964176177978516f,0.45917654037475585938f,0.88834506273269653320f, +0.45781329274177551270f,0.88904833793640136719f,0.45644897222518920898f, +0.88974958658218383789f,0.45508357882499694824f,0.89044874906539916992f, +0.45371711254119873047f,0.89114576578140258789f,0.45234957337379455566f, +0.89184069633483886719f,0.45098099112510681152f,0.89253354072570800781f, +0.44961133599281311035f,0.89322429895401000977f,0.44824060797691345215f, +0.89391297101974487305f,0.44686883687973022461f,0.89459949731826782227f, +0.44549602270126342773f,0.89528393745422363281f,0.44412213563919067383f, +0.89596623182296752930f,0.44274723529815673828f,0.89664649963378906250f, +0.44137126207351684570f,0.89732456207275390625f,0.43999427556991577148f, +0.89800059795379638672f,0.43861624598503112793f,0.89867448806762695312f, +0.43723717331886291504f,0.89934623241424560547f,0.43585708737373352051f, +0.90001589059829711914f,0.43447595834732055664f,0.90068340301513671875f, +0.43309381604194641113f,0.90134882926940917969f,0.43171066045761108398f, +0.90201216936111450195f,0.43032649159431457520f,0.90267330408096313477f, +0.42894127964973449707f,0.90333235263824462891f,0.42755508422851562500f, +0.90398931503295898438f,0.42616787552833557129f,0.90464407205581665039f, +0.42477968335151672363f,0.90529674291610717773f,0.42339047789573669434f, +0.90594726800918579102f,0.42200025916099548340f,0.90659570693969726562f, +0.42060908675193786621f,0.90724200010299682617f,0.41921690106391906738f, +0.90788608789443969727f,0.41782370209693908691f,0.90852808952331542969f, +0.41642954945564270020f,0.90916800498962402344f,0.41503441333770751953f, +0.90980571508407592773f,0.41363832354545593262f,0.91044127941131591797f, +0.41224122047424316406f,0.91107475757598876953f,0.41084316372871398926f, +0.91170603036880493164f,0.40944415330886840820f,0.91233515739440917969f, +0.40804415941238403320f,0.91296219825744628906f,0.40664321184158325195f, +0.91358703374862670898f,0.40524131059646606445f,0.91420978307723999023f, +0.40383845567703247070f,0.91483032703399658203f,0.40243464708328247070f, +0.91544872522354125977f,0.40102988481521606445f,0.91606497764587402344f, +0.39962419867515563965f,0.91667908430099487305f,0.39821755886077880859f, +0.91729098558425903320f,0.39680999517440795898f,0.91790080070495605469f, +0.39540147781372070312f,0.91850841045379638672f,0.39399203658103942871f, +0.91911387443542480469f,0.39258167147636413574f,0.91971713304519653320f, +0.39117038249969482422f,0.92031830549240112305f,0.38975816965103149414f, +0.92091721296310424805f,0.38834503293037414551f,0.92151403427124023438f, +0.38693100214004516602f,0.92210865020751953125f,0.38551604747772216797f, +0.92270112037658691406f,0.38410019874572753906f,0.92329144477844238281f, +0.38268342614173889160f,0.92387950420379638672f,0.38126575946807861328f, +0.92446547746658325195f,0.37984719872474670410f,0.92504924535751342773f, +0.37842774391174316406f,0.92563080787658691406f,0.37700742483139038086f, +0.92621022462844848633f,0.37558618187904357910f,0.92678749561309814453f, +0.37416407465934753418f,0.92736250162124633789f,0.37274107336997985840f, +0.92793542146682739258f,0.37131720781326293945f,0.92850607633590698242f, +0.36989244818687438965f,0.92907458543777465820f,0.36846682429313659668f, +0.92964088916778564453f,0.36704033613204956055f,0.93020504713058471680f, +0.36561298370361328125f,0.93076694011688232422f,0.36418479681015014648f, +0.93132668733596801758f,0.36275571584701538086f,0.93188428878784179688f, +0.36132580041885375977f,0.93243962526321411133f,0.35989505052566528320f, +0.93299281597137451172f,0.35846340656280517578f,0.93354380130767822266f, +0.35703095793724060059f,0.93409252166748046875f,0.35559767484664916992f, +0.93463915586471557617f,0.35416352748870849609f,0.93518352508544921875f, +0.35272854566574096680f,0.93572568893432617188f,0.35129275918006896973f, +0.93626564741134643555f,0.34985613822937011719f,0.93680346012115478516f, +0.34841868281364440918f,0.93733900785446166992f,0.34698042273521423340f, +0.93787235021591186523f,0.34554132819175720215f,0.93840354681015014648f, +0.34410142898559570312f,0.93893247842788696289f,0.34266072511672973633f, +0.93945920467376708984f,0.34121921658515930176f,0.93998372554779052734f, +0.33977687358856201172f,0.94050604104995727539f,0.33833375573158264160f, +0.94102615118026733398f,0.33688986301422119141f,0.94154405593872070312f, +0.33544513583183288574f,0.94205975532531738281f,0.33399966359138488770f, +0.94257318973541259766f,0.33255335688591003418f,0.94308441877365112305f, +0.33110630512237548828f,0.94359344244003295898f,0.32965844869613647461f, +0.94410026073455810547f,0.32820984721183776855f,0.94460481405258178711f, +0.32676044106483459473f,0.94510722160339355469f,0.32531028985977172852f, +0.94560730457305908203f,0.32385936379432678223f,0.94610524177551269531f, +0.32240769267082214355f,0.94660091400146484375f,0.32095524668693542480f, +0.94709438085556030273f,0.31950202584266662598f,0.94758558273315429688f, +0.31804808974266052246f,0.94807457923889160156f,0.31659337878227233887f, +0.94856137037277221680f,0.31513792276382446289f,0.94904589653015136719f, +0.31368175148963928223f,0.94952815771102905273f,0.31222480535507202148f, +0.95000827312469482422f,0.31076714396476745605f,0.95048606395721435547f, +0.30930876731872558594f,0.95096164941787719727f,0.30784964561462402344f, +0.95143502950668334961f,0.30638980865478515625f,0.95190614461898803711f, +0.30492922663688659668f,0.95237499475479125977f,0.30346795916557312012f, +0.95284163951873779297f,0.30200594663619995117f,0.95330601930618286133f, +0.30054324865341186523f,0.95376819372177124023f,0.29907983541488647461f, +0.95422810316085815430f,0.29761570692062377930f,0.95468574762344360352f, +0.29615089297294616699f,0.95514118671417236328f,0.29468536376953125000f, +0.95559436082839965820f,0.29321914911270141602f,0.95604526996612548828f, +0.29175224900245666504f,0.95649391412734985352f,0.29028466343879699707f, +0.95694035291671752930f,0.28881642222404479980f,0.95738452672958374023f, +0.28734746575355529785f,0.95782643556594848633f,0.28587782382965087891f, +0.95826607942581176758f,0.28440752625465393066f,0.95870345830917358398f, +0.28293657302856445312f,0.95913863182067871094f,0.28146493434906005859f, +0.95957154035568237305f,0.27999264001846313477f,0.96000212430953979492f, +0.27851969003677368164f,0.96043050289154052734f,0.27704608440399169922f, +0.96085661649703979492f,0.27557182312011718750f,0.96128046512603759766f, +0.27409690618515014648f,0.96170204877853393555f,0.27262136340141296387f, +0.96212142705917358398f,0.27114516496658325195f,0.96253848075866699219f, +0.26966831088066101074f,0.96295326948165893555f,0.26819086074829101562f, +0.96336579322814941406f,0.26671275496482849121f,0.96377605199813842773f, +0.26523402333259582520f,0.96418404579162597656f,0.26375466585159301758f, +0.96458977460861206055f,0.26227471232414245605f,0.96499323844909667969f, +0.26079410314559936523f,0.96539443731307983398f,0.25931292772293090820f, +0.96579337120056152344f,0.25783109664916992188f,0.96618998050689697266f, +0.25634866952896118164f,0.96658438444137573242f,0.25486564636230468750f, +0.96697646379470825195f,0.25338202714920043945f,0.96736627817153930664f, +0.25189781188964843750f,0.96775382757186889648f,0.25041300058364868164f, +0.96813911199569702148f,0.24892760813236236572f,0.96852207183837890625f, +0.24744161963462829590f,0.96890282630920410156f,0.24595504999160766602f, +0.96928125619888305664f,0.24446789920330047607f,0.96965736150741577148f, +0.24298018217086791992f,0.97003126144409179688f,0.24149188399314880371f, +0.97040283679962158203f,0.24000301957130432129f,0.97077214717864990234f, +0.23851358890533447266f,0.97113913297653198242f,0.23702360689640045166f, +0.97150391340255737305f,0.23553305864334106445f,0.97186630964279174805f, +0.23404195904731750488f,0.97222650051116943359f,0.23255030810832977295f, +0.97258436679840087891f,0.23105810582637786865f,0.97293996810913085938f, +0.22956536710262298584f,0.97329324483871459961f,0.22807207703590393066f, +0.97364425659179687500f,0.22657826542854309082f,0.97399294376373291016f, +0.22508391737937927246f,0.97433936595916748047f,0.22358903288841247559f, +0.97468352317810058594f,0.22209362685680389404f,0.97502535581588745117f, +0.22059768438339233398f,0.97536486387252807617f,0.21910123527050018311f, +0.97570210695266723633f,0.21760427951812744141f,0.97603708505630493164f, +0.21610680222511291504f,0.97636973857879638672f,0.21460881829261779785f, +0.97670006752014160156f,0.21311031281948089600f,0.97702813148498535156f, +0.21161133050918579102f,0.97735387086868286133f,0.21011184155941009521f, +0.97767734527587890625f,0.20861184597015380859f,0.97799849510192871094f, +0.20711137354373931885f,0.97831737995147705078f,0.20561040937900543213f, +0.97863394021987915039f,0.20410896837711334229f,0.97894817590713500977f, +0.20260703563690185547f,0.97926014661788940430f,0.20110464096069335938f, +0.97956979274749755859f,0.19960175454616546631f,0.97987711429595947266f, +0.19809840619564056396f,0.98018211126327514648f,0.19659459590911865234f, +0.98048484325408935547f,0.19509032368659973145f,0.98078525066375732422f, +0.19358558952808380127f,0.98108339309692382812f,0.19208039343357086182f, +0.98137921094894409180f,0.19057475030422210693f,0.98167270421981811523f, +0.18906866014003753662f,0.98196387290954589844f,0.18756212294101715088f, +0.98225271701812744141f,0.18605515360832214355f,0.98253929615020751953f, +0.18454773724079132080f,0.98282355070114135742f,0.18303988873958587646f, +0.98310548067092895508f,0.18153160810470581055f,0.98338508605957031250f, +0.18002289533615112305f,0.98366242647171020508f,0.17851376533508300781f, +0.98393744230270385742f,0.17700421810150146484f,0.98421007394790649414f, +0.17549425363540649414f,0.98448044061660766602f,0.17398387193679809570f, +0.98474848270416259766f,0.17247308790683746338f,0.98501425981521606445f, +0.17096188664436340332f,0.98527765274047851562f,0.16945029795169830322f, +0.98553872108459472656f,0.16793829202651977539f,0.98579752445220947266f, +0.16642589867115020752f,0.98605394363403320312f,0.16491311788558959961f, +0.98630809783935546875f,0.16339994966983795166f,0.98655992746353149414f, +0.16188639402389526367f,0.98680937290191650391f,0.16037245094776153564f, +0.98705655336380004883f,0.15885815024375915527f,0.98730140924453735352f, +0.15734346210956573486f,0.98754394054412841797f,0.15582840144634246826f, +0.98778414726257324219f,0.15431296825408935547f,0.98802202939987182617f, +0.15279719233512878418f,0.98825758695602416992f,0.15128104388713836670f, +0.98849081993103027344f,0.14976453781127929688f,0.98872166872024536133f, +0.14824767410755157471f,0.98895025253295898438f,0.14673046767711639404f, +0.98917651176452636719f,0.14521291851997375488f,0.98940044641494750977f, +0.14369502663612365723f,0.98962199687957763672f,0.14217680692672729492f, +0.98984128236770629883f,0.14065824449062347412f,0.99005818367004394531f, +0.13913933932781219482f,0.99027281999588012695f,0.13762012124061584473f, +0.99048507213592529297f,0.13610057532787322998f,0.99069499969482421875f, +0.13458070158958435059f,0.99090266227722167969f,0.13306052982807159424f, +0.99110794067382812500f,0.13154003024101257324f,0.99131083488464355469f, +0.13001921772956848145f,0.99151146411895751953f,0.12849810719490051270f, +0.99170976877212524414f,0.12697669863700866699f,0.99190568923950195312f, +0.12545497715473175049f,0.99209928512573242188f,0.12393297255039215088f, +0.99229061603546142578f,0.12241067737340927124f,0.99247956275939941406f, +0.12088808417320251465f,0.99266612529754638672f,0.11936521530151367188f, +0.99285042285919189453f,0.11784206330776214600f,0.99303233623504638672f, +0.11631862819194793701f,0.99321192502975463867f,0.11479492485523223877f, +0.99338918924331665039f,0.11327095329761505127f,0.99356412887573242188f, +0.11174671351909637451f,0.99373674392700195312f,0.11022220551967620850f, +0.99390697479248046875f,0.10869744420051574707f,0.99407488107681274414f, +0.10717242211103439331f,0.99424046277999877930f,0.10564715415239334106f, +0.99440366029739379883f,0.10412163287401199341f,0.99456459283828735352f, +0.10259586572647094727f,0.99472314119338989258f,0.10106986016035079956f, +0.99487930536270141602f,0.09954361617565155029f,0.99503320455551147461f, +0.09801714122295379639f,0.99518471956253051758f,0.09649042785167694092f, +0.99533390998840332031f,0.09496349841356277466f,0.99548077583312988281f, +0.09343633800745010376f,0.99562525749206542969f,0.09190895408391952515f, +0.99576741456985473633f,0.09038136154413223267f,0.99590724706649780273f, +0.08885355293750762939f,0.99604469537734985352f,0.08732553571462631226f, +0.99617981910705566406f,0.08579730987548828125f,0.99631261825561523438f, +0.08426889032125473022f,0.99644303321838378906f,0.08274026215076446533f, +0.99657112360000610352f,0.08121144771575927734f,0.99669688940048217773f, +0.07968243956565856934f,0.99682027101516723633f,0.07815324515104293823f, +0.99694132804870605469f,0.07662386447191238403f,0.99706006050109863281f, +0.07509429752826690674f,0.99717640876770019531f,0.07356456667184829712f, +0.99729043245315551758f,0.07203464955091476440f,0.99740213155746459961f, +0.07050457596778869629f,0.99751144647598266602f,0.06897433102130889893f, +0.99761843681335449219f,0.06744392216205596924f,0.99772304296493530273f, +0.06591334939002990723f,0.99782532453536987305f,0.06438262760639190674f, +0.99792528152465820312f,0.06285175681114196777f,0.99802285432815551758f, +0.06132073700428009033f,0.99811810255050659180f,0.05978957191109657288f, +0.99821102619171142578f,0.05825826525688171387f,0.99830156564712524414f, +0.05672682076692581177f,0.99838972091674804688f,0.05519524589180946350f, +0.99847555160522460938f,0.05366353690624237061f,0.99855905771255493164f, +0.05213170498609542847f,0.99864023923873901367f,0.05059975013136863708f, +0.99871903657913208008f,0.04906767606735229492f,0.99879544973373413086f, +0.04753548279404640198f,0.99886953830718994141f,0.04600318148732185364f, +0.99894130229949951172f,0.04447077214717864990f,0.99901068210601806641f, +0.04293825849890708923f,0.99907773733139038086f,0.04140564054250717163f, +0.99914240837097167969f,0.03987292572855949402f,0.99920475482940673828f, +0.03834012150764465332f,0.99926477670669555664f,0.03680722415447235107f, +0.99932235479354858398f,0.03527423739433288574f,0.99937766790390014648f, +0.03374117240309715271f,0.99943059682846069336f,0.03220802545547485352f, +0.99948120117187500000f,0.03067480400204658508f,0.99952942132949829102f, +0.02914150804281234741f,0.99957531690597534180f,0.02760814502835273743f, +0.99961882829666137695f,0.02607471868395805359f,0.99966001510620117188f, +0.02454122900962829590f,0.99969881772994995117f,0.02300768159329891205f, +0.99973529577255249023f,0.02147408016026020050f,0.99976938962936401367f, +0.01994042843580245972f,0.99980115890502929688f,0.01840673014521598816f, +0.99983060359954833984f,0.01687298715114593506f,0.99985766410827636719f, +0.01533920597285032272f,0.99988234043121337891f,0.01380538847297430038f, +0.99990469217300415039f,0.01227153837680816650f,0.99992471933364868164f, +0.01073765940964221954f,0.99994236230850219727f,0.00920375436544418335f, +0.99995762109756469727f,0.00766982883214950562f,0.99997061491012573242f, +0.00613588467240333557f,0.99998116493225097656f,0.00460192607715725899f, +0.99998939037322998047f,0.00306795677170157433f,0.99999529123306274414f, +0.00153398013208061457f,0.99999880790710449219f,1.00000000000000000000f, +0.00000000000000000000f,0.99998116493225097656f,0.00613588467240333557f, +0.99992471933364868164f,0.01227153837680816650f,0.99983060359954833984f, +0.01840673014521598816f,0.99969881772994995117f,0.02454122900962829590f, +0.99952942132949829102f,0.03067480400204658508f,0.99932235479354858398f, +0.03680722415447235107f,0.99907773733139038086f,0.04293825849890708923f, +0.99879544973373413086f,0.04906767606735229492f,0.99847555160522460938f, +0.05519524589180946350f,0.99811810255050659180f,0.06132073700428009033f, +0.99772304296493530273f,0.06744392216205596924f,0.99729043245315551758f, +0.07356456667184829712f,0.99682027101516723633f,0.07968243956565856934f, +0.99631261825561523438f,0.08579730987548828125f,0.99576741456985473633f, +0.09190895408391952515f,0.99518471956253051758f,0.09801714122295379639f, +0.99456459283828735352f,0.10412163287401199341f,0.99390697479248046875f, +0.11022220551967620850f,0.99321192502975463867f,0.11631862819194793701f, +0.99247956275939941406f,0.12241067737340927124f,0.99170976877212524414f, +0.12849810719490051270f,0.99090266227722167969f,0.13458070158958435059f, +0.99005818367004394531f,0.14065824449062347412f,0.98917651176452636719f, +0.14673046767711639404f,0.98825758695602416992f,0.15279719233512878418f, +0.98730140924453735352f,0.15885815024375915527f,0.98630809783935546875f, +0.16491311788558959961f,0.98527765274047851562f,0.17096188664436340332f, +0.98421007394790649414f,0.17700421810150146484f,0.98310548067092895508f, +0.18303988873958587646f,0.98196387290954589844f,0.18906866014003753662f, +0.98078525066375732422f,0.19509032368659973145f,0.97956979274749755859f, +0.20110464096069335938f,0.97831737995147705078f,0.20711137354373931885f, +0.97702813148498535156f,0.21311031281948089600f,0.97570210695266723633f, +0.21910123527050018311f,0.97433936595916748047f,0.22508391737937927246f, +0.97293996810913085938f,0.23105810582637786865f,0.97150391340255737305f, +0.23702360689640045166f,0.97003126144409179688f,0.24298018217086791992f, +0.96852207183837890625f,0.24892760813236236572f,0.96697646379470825195f, +0.25486564636230468750f,0.96539443731307983398f,0.26079410314559936523f, +0.96377605199813842773f,0.26671275496482849121f,0.96212142705917358398f, +0.27262136340141296387f,0.96043050289154052734f,0.27851969003677368164f, +0.95870345830917358398f,0.28440752625465393066f,0.95694035291671752930f, +0.29028466343879699707f,0.95514118671417236328f,0.29615089297294616699f, +0.95330601930618286133f,0.30200594663619995117f,0.95143502950668334961f, +0.30784964561462402344f,0.94952815771102905273f,0.31368175148963928223f, +0.94758558273315429688f,0.31950202584266662598f,0.94560730457305908203f, +0.32531028985977172852f,0.94359344244003295898f,0.33110630512237548828f, +0.94154405593872070312f,0.33688986301422119141f,0.93945920467376708984f, +0.34266072511672973633f,0.93733900785446166992f,0.34841868281364440918f, +0.93518352508544921875f,0.35416352748870849609f,0.93299281597137451172f, +0.35989505052566528320f,0.93076694011688232422f,0.36561298370361328125f, +0.92850607633590698242f,0.37131720781326293945f,0.92621022462844848633f, +0.37700742483139038086f,0.92387950420379638672f,0.38268342614173889160f, +0.92151403427124023438f,0.38834503293037414551f,0.91911387443542480469f, +0.39399203658103942871f,0.91667908430099487305f,0.39962419867515563965f, +0.91420978307723999023f,0.40524131059646606445f,0.91170603036880493164f, +0.41084316372871398926f,0.90916800498962402344f,0.41642954945564270020f, +0.90659570693969726562f,0.42200025916099548340f,0.90398931503295898438f, +0.42755508422851562500f,0.90134882926940917969f,0.43309381604194641113f, +0.89867448806762695312f,0.43861624598503112793f,0.89596623182296752930f, +0.44412213563919067383f,0.89322429895401000977f,0.44961133599281311035f, +0.89044874906539916992f,0.45508357882499694824f,0.88763964176177978516f, +0.46053871512413024902f,0.88479709625244140625f,0.46597650647163391113f, +0.88192129135131835938f,0.47139674425125122070f,0.87901222705841064453f, +0.47679921984672546387f,0.87607008218765258789f,0.48218378424644470215f, +0.87309497594833374023f,0.48755016922950744629f,0.87008696794509887695f, +0.49289819598197937012f,0.86704623699188232422f,0.49822765588760375977f, +0.86397284269332885742f,0.50353837013244628906f,0.86086696386337280273f, +0.50883013010025024414f,0.85772860050201416016f,0.51410275697708129883f, +0.85455799102783203125f,0.51935601234436035156f,0.85135519504547119141f, +0.52458965778350830078f,0.84812033176422119141f,0.52980363368988037109f, +0.84485357999801635742f,0.53499764204025268555f,0.84155499935150146484f, +0.54017144441604614258f,0.83822470903396606445f,0.54532498121261596680f, +0.83486288785934448242f,0.55045795440673828125f,0.83146959543228149414f, +0.55557024478912353516f,0.82804507017135620117f,0.56066155433654785156f, +0.82458931207656860352f,0.56573182344436645508f,0.82110249996185302734f, +0.57078075408935546875f,0.81758481264114379883f,0.57580816745758056641f, +0.81403630971908569336f,0.58081394433975219727f,0.81045717000961303711f, +0.58579784631729125977f,0.80684757232666015625f,0.59075969457626342773f, +0.80320751667022705078f,0.59569931030273437500f,0.79953724145889282227f, +0.60061645507812500000f,0.79583692550659179688f,0.60551106929779052734f, +0.79210656881332397461f,0.61038279533386230469f,0.78834640979766845703f, +0.61523157358169555664f,0.78455656766891479492f,0.62005722522735595703f, +0.78073722124099731445f,0.62485951185226440430f,0.77688848972320556641f, +0.62963825464248657227f,0.77301043272018432617f,0.63439327478408813477f, +0.76910334825515747070f,0.63912445306777954102f,0.76516723632812500000f, +0.64383155107498168945f,0.76120239496231079102f,0.64851438999176025391f, +0.75720882415771484375f,0.65317285060882568359f,0.75318682193756103516f, +0.65780669450759887695f,0.74913638830184936523f,0.66241580247879028320f, +0.74505776166915893555f,0.66699993610382080078f,0.74095112085342407227f, +0.67155897617340087891f,0.73681658506393432617f,0.67609268426895141602f, +0.73265427350997924805f,0.68060100078582763672f,0.72846436500549316406f, +0.68508368730545043945f,0.72424709796905517578f,0.68954056501388549805f, +0.72000253200531005859f,0.69397145509719848633f,0.71573084592819213867f, +0.69837623834609985352f,0.71143221855163574219f,0.70275473594665527344f, +0.70710676908493041992f,0.70710676908493041992f,0.70275473594665527344f, +0.71143221855163574219f,0.69837623834609985352f,0.71573084592819213867f, +0.69397145509719848633f,0.72000253200531005859f,0.68954056501388549805f, +0.72424709796905517578f,0.68508368730545043945f,0.72846436500549316406f, +0.68060100078582763672f,0.73265427350997924805f,0.67609268426895141602f, +0.73681658506393432617f,0.67155897617340087891f,0.74095112085342407227f, +0.66699993610382080078f,0.74505776166915893555f,0.66241580247879028320f, +0.74913638830184936523f,0.65780669450759887695f,0.75318682193756103516f, +0.65317285060882568359f,0.75720882415771484375f,0.64851438999176025391f, +0.76120239496231079102f,0.64383155107498168945f,0.76516723632812500000f, +0.63912445306777954102f,0.76910334825515747070f,0.63439327478408813477f, +0.77301043272018432617f,0.62963825464248657227f,0.77688848972320556641f, +0.62485951185226440430f,0.78073722124099731445f,0.62005722522735595703f, +0.78455656766891479492f,0.61523157358169555664f,0.78834640979766845703f, +0.61038279533386230469f,0.79210656881332397461f,0.60551106929779052734f, +0.79583692550659179688f,0.60061645507812500000f,0.79953724145889282227f, +0.59569931030273437500f,0.80320751667022705078f,0.59075969457626342773f, +0.80684757232666015625f,0.58579784631729125977f,0.81045717000961303711f, +0.58081394433975219727f,0.81403630971908569336f,0.57580816745758056641f, +0.81758481264114379883f,0.57078075408935546875f,0.82110249996185302734f, +0.56573182344436645508f,0.82458931207656860352f,0.56066155433654785156f, +0.82804507017135620117f,0.55557024478912353516f,0.83146959543228149414f, +0.55045795440673828125f,0.83486288785934448242f,0.54532498121261596680f, +0.83822470903396606445f,0.54017144441604614258f,0.84155499935150146484f, +0.53499764204025268555f,0.84485357999801635742f,0.52980363368988037109f, +0.84812033176422119141f,0.52458965778350830078f,0.85135519504547119141f, +0.51935601234436035156f,0.85455799102783203125f,0.51410275697708129883f, +0.85772860050201416016f,0.50883013010025024414f,0.86086696386337280273f, +0.50353837013244628906f,0.86397284269332885742f,0.49822765588760375977f, +0.86704623699188232422f,0.49289819598197937012f,0.87008696794509887695f, +0.48755016922950744629f,0.87309497594833374023f,0.48218378424644470215f, +0.87607008218765258789f,0.47679921984672546387f,0.87901222705841064453f, +0.47139674425125122070f,0.88192129135131835938f,0.46597650647163391113f, +0.88479709625244140625f,0.46053871512413024902f,0.88763964176177978516f, +0.45508357882499694824f,0.89044874906539916992f,0.44961133599281311035f, +0.89322429895401000977f,0.44412213563919067383f,0.89596623182296752930f, +0.43861624598503112793f,0.89867448806762695312f,0.43309381604194641113f, +0.90134882926940917969f,0.42755508422851562500f,0.90398931503295898438f, +0.42200025916099548340f,0.90659570693969726562f,0.41642954945564270020f, +0.90916800498962402344f,0.41084316372871398926f,0.91170603036880493164f, +0.40524131059646606445f,0.91420978307723999023f,0.39962419867515563965f, +0.91667908430099487305f,0.39399203658103942871f,0.91911387443542480469f, +0.38834503293037414551f,0.92151403427124023438f,0.38268342614173889160f, +0.92387950420379638672f,0.37700742483139038086f,0.92621022462844848633f, +0.37131720781326293945f,0.92850607633590698242f,0.36561298370361328125f, +0.93076694011688232422f,0.35989505052566528320f,0.93299281597137451172f, +0.35416352748870849609f,0.93518352508544921875f,0.34841868281364440918f, +0.93733900785446166992f,0.34266072511672973633f,0.93945920467376708984f, +0.33688986301422119141f,0.94154405593872070312f,0.33110630512237548828f, +0.94359344244003295898f,0.32531028985977172852f,0.94560730457305908203f, +0.31950202584266662598f,0.94758558273315429688f,0.31368175148963928223f, +0.94952815771102905273f,0.30784964561462402344f,0.95143502950668334961f, +0.30200594663619995117f,0.95330601930618286133f,0.29615089297294616699f, +0.95514118671417236328f,0.29028466343879699707f,0.95694035291671752930f, +0.28440752625465393066f,0.95870345830917358398f,0.27851969003677368164f, +0.96043050289154052734f,0.27262136340141296387f,0.96212142705917358398f, +0.26671275496482849121f,0.96377605199813842773f,0.26079410314559936523f, +0.96539443731307983398f,0.25486564636230468750f,0.96697646379470825195f, +0.24892760813236236572f,0.96852207183837890625f,0.24298018217086791992f, +0.97003126144409179688f,0.23702360689640045166f,0.97150391340255737305f, +0.23105810582637786865f,0.97293996810913085938f,0.22508391737937927246f, +0.97433936595916748047f,0.21910123527050018311f,0.97570210695266723633f, +0.21311031281948089600f,0.97702813148498535156f,0.20711137354373931885f, +0.97831737995147705078f,0.20110464096069335938f,0.97956979274749755859f, +0.19509032368659973145f,0.98078525066375732422f,0.18906866014003753662f, +0.98196387290954589844f,0.18303988873958587646f,0.98310548067092895508f, +0.17700421810150146484f,0.98421007394790649414f,0.17096188664436340332f, +0.98527765274047851562f,0.16491311788558959961f,0.98630809783935546875f, +0.15885815024375915527f,0.98730140924453735352f,0.15279719233512878418f, +0.98825758695602416992f,0.14673046767711639404f,0.98917651176452636719f, +0.14065824449062347412f,0.99005818367004394531f,0.13458070158958435059f, +0.99090266227722167969f,0.12849810719490051270f,0.99170976877212524414f, +0.12241067737340927124f,0.99247956275939941406f,0.11631862819194793701f, +0.99321192502975463867f,0.11022220551967620850f,0.99390697479248046875f, +0.10412163287401199341f,0.99456459283828735352f,0.09801714122295379639f, +0.99518471956253051758f,0.09190895408391952515f,0.99576741456985473633f, +0.08579730987548828125f,0.99631261825561523438f,0.07968243956565856934f, +0.99682027101516723633f,0.07356456667184829712f,0.99729043245315551758f, +0.06744392216205596924f,0.99772304296493530273f,0.06132073700428009033f, +0.99811810255050659180f,0.05519524589180946350f,0.99847555160522460938f, +0.04906767606735229492f,0.99879544973373413086f,0.04293825849890708923f, +0.99907773733139038086f,0.03680722415447235107f,0.99932235479354858398f, +0.03067480400204658508f,0.99952942132949829102f,0.02454122900962829590f, +0.99969881772994995117f,0.01840673014521598816f,0.99983060359954833984f, +0.01227153837680816650f,0.99992471933364868164f,0.00613588467240333557f, +0.99998116493225097656f,1.00000000000000000000f,0.00000000000000000000f, +0.99969881772994995117f,0.02454122900962829590f,0.99879544973373413086f, +0.04906767606735229492f,0.99729043245315551758f,0.07356456667184829712f, +0.99518471956253051758f,0.09801714122295379639f,0.99247956275939941406f, +0.12241067737340927124f,0.98917651176452636719f,0.14673046767711639404f, +0.98527765274047851562f,0.17096188664436340332f,0.98078525066375732422f, +0.19509032368659973145f,0.97570210695266723633f,0.21910123527050018311f, +0.97003126144409179688f,0.24298018217086791992f,0.96377605199813842773f, +0.26671275496482849121f,0.95694035291671752930f,0.29028466343879699707f, +0.94952815771102905273f,0.31368175148963928223f,0.94154405593872070312f, +0.33688986301422119141f,0.93299281597137451172f,0.35989505052566528320f, +0.92387950420379638672f,0.38268342614173889160f,0.91420978307723999023f, +0.40524131059646606445f,0.90398931503295898438f,0.42755508422851562500f, +0.89322429895401000977f,0.44961133599281311035f,0.88192129135131835938f, +0.47139674425125122070f,0.87008696794509887695f,0.49289819598197937012f, +0.85772860050201416016f,0.51410275697708129883f,0.84485357999801635742f, +0.53499764204025268555f,0.83146959543228149414f,0.55557024478912353516f, +0.81758481264114379883f,0.57580816745758056641f,0.80320751667022705078f, +0.59569931030273437500f,0.78834640979766845703f,0.61523157358169555664f, +0.77301043272018432617f,0.63439327478408813477f,0.75720882415771484375f, +0.65317285060882568359f,0.74095112085342407227f,0.67155897617340087891f, +0.72424709796905517578f,0.68954056501388549805f,0.70710676908493041992f, +0.70710676908493041992f,0.68954056501388549805f,0.72424709796905517578f, +0.67155897617340087891f,0.74095112085342407227f,0.65317285060882568359f, +0.75720882415771484375f,0.63439327478408813477f,0.77301043272018432617f, +0.61523157358169555664f,0.78834640979766845703f,0.59569931030273437500f, +0.80320751667022705078f,0.57580816745758056641f,0.81758481264114379883f, +0.55557024478912353516f,0.83146959543228149414f,0.53499764204025268555f, +0.84485357999801635742f,0.51410275697708129883f,0.85772860050201416016f, +0.49289819598197937012f,0.87008696794509887695f,0.47139674425125122070f, +0.88192129135131835938f,0.44961133599281311035f,0.89322429895401000977f, +0.42755508422851562500f,0.90398931503295898438f,0.40524131059646606445f, +0.91420978307723999023f,0.38268342614173889160f,0.92387950420379638672f, +0.35989505052566528320f,0.93299281597137451172f,0.33688986301422119141f, +0.94154405593872070312f,0.31368175148963928223f,0.94952815771102905273f, +0.29028466343879699707f,0.95694035291671752930f,0.26671275496482849121f, +0.96377605199813842773f,0.24298018217086791992f,0.97003126144409179688f, +0.21910123527050018311f,0.97570210695266723633f,0.19509032368659973145f, +0.98078525066375732422f,0.17096188664436340332f,0.98527765274047851562f, +0.14673046767711639404f,0.98917651176452636719f,0.12241067737340927124f, +0.99247956275939941406f,0.09801714122295379639f,0.99518471956253051758f, +0.07356456667184829712f,0.99729043245315551758f,0.04906767606735229492f, +0.99879544973373413086f,0.02454122900962829590f,0.99969881772994995117f, +1.00000000000000000000f,0.00000000000000000000f,0.99518471956253051758f, +0.09801714122295379639f,0.98078525066375732422f,0.19509032368659973145f, +0.95694035291671752930f,0.29028466343879699707f,0.92387950420379638672f, +0.38268342614173889160f,0.88192129135131835938f,0.47139674425125122070f, +0.83146959543228149414f,0.55557024478912353516f,0.77301043272018432617f, +0.63439327478408813477f,0.70710676908493041992f,0.70710676908493041992f, +0.63439327478408813477f,0.77301043272018432617f,0.55557024478912353516f, +0.83146959543228149414f,0.47139674425125122070f,0.88192129135131835938f, +0.38268342614173889160f,0.92387950420379638672f,0.29028466343879699707f, +0.95694035291671752930f,0.19509032368659973145f,0.98078525066375732422f, +0.09801714122295379639f,0.99518471956253051758f,1.00000000000000000000f, +0.00000000000000000000f,0.92387950420379638672f,0.38268342614173889160f, +0.70710676908493041992f,0.70710676908493041992f,0.38268342614173889160f, +0.92387950420379638672f,}; + +float32_t rearranged_twiddle_stride2_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99999529123306274414f, +0.00306795677170157433f,0.99998116493225097656f,0.00613588467240333557f, +0.99995762109756469727f,0.00920375436544418335f,0.99992471933364868164f, +0.01227153837680816650f,0.99988234043121337891f,0.01533920597285032272f, +0.99983060359954833984f,0.01840673014521598816f,0.99976938962936401367f, +0.02147408016026020050f,0.99969881772994995117f,0.02454122900962829590f, +0.99961882829666137695f,0.02760814502835273743f,0.99952942132949829102f, +0.03067480400204658508f,0.99943059682846069336f,0.03374117240309715271f, +0.99932235479354858398f,0.03680722415447235107f,0.99920475482940673828f, +0.03987292572855949402f,0.99907773733139038086f,0.04293825849890708923f, +0.99894130229949951172f,0.04600318148732185364f,0.99879544973373413086f, +0.04906767606735229492f,0.99864023923873901367f,0.05213170498609542847f, +0.99847555160522460938f,0.05519524589180946350f,0.99830156564712524414f, +0.05825826525688171387f,0.99811810255050659180f,0.06132073700428009033f, +0.99792528152465820312f,0.06438262760639190674f,0.99772304296493530273f, +0.06744392216205596924f,0.99751144647598266602f,0.07050457596778869629f, +0.99729043245315551758f,0.07356456667184829712f,0.99706006050109863281f, +0.07662386447191238403f,0.99682027101516723633f,0.07968243956565856934f, +0.99657112360000610352f,0.08274026215076446533f,0.99631261825561523438f, +0.08579730987548828125f,0.99604469537734985352f,0.08885355293750762939f, +0.99576741456985473633f,0.09190895408391952515f,0.99548077583312988281f, +0.09496349841356277466f,0.99518471956253051758f,0.09801714122295379639f, +0.99487930536270141602f,0.10106986016035079956f,0.99456459283828735352f, +0.10412163287401199341f,0.99424046277999877930f,0.10717242211103439331f, +0.99390697479248046875f,0.11022220551967620850f,0.99356412887573242188f, +0.11327095329761505127f,0.99321192502975463867f,0.11631862819194793701f, +0.99285042285919189453f,0.11936521530151367188f,0.99247956275939941406f, +0.12241067737340927124f,0.99209928512573242188f,0.12545497715473175049f, +0.99170976877212524414f,0.12849810719490051270f,0.99131083488464355469f, +0.13154003024101257324f,0.99090266227722167969f,0.13458070158958435059f, +0.99048507213592529297f,0.13762012124061584473f,0.99005818367004394531f, +0.14065824449062347412f,0.98962199687957763672f,0.14369502663612365723f, +0.98917651176452636719f,0.14673046767711639404f,0.98872166872024536133f, +0.14976453781127929688f,0.98825758695602416992f,0.15279719233512878418f, +0.98778414726257324219f,0.15582840144634246826f,0.98730140924453735352f, +0.15885815024375915527f,0.98680937290191650391f,0.16188639402389526367f, +0.98630809783935546875f,0.16491311788558959961f,0.98579752445220947266f, +0.16793829202651977539f,0.98527765274047851562f,0.17096188664436340332f, +0.98474848270416259766f,0.17398387193679809570f,0.98421007394790649414f, +0.17700421810150146484f,0.98366242647171020508f,0.18002289533615112305f, +0.98310548067092895508f,0.18303988873958587646f,0.98253929615020751953f, +0.18605515360832214355f,0.98196387290954589844f,0.18906866014003753662f, +0.98137921094894409180f,0.19208039343357086182f,0.98078525066375732422f, +0.19509032368659973145f,0.98018211126327514648f,0.19809840619564056396f, +0.97956979274749755859f,0.20110464096069335938f,0.97894817590713500977f, +0.20410896837711334229f,0.97831737995147705078f,0.20711137354373931885f, +0.97767734527587890625f,0.21011184155941009521f,0.97702813148498535156f, +0.21311031281948089600f,0.97636973857879638672f,0.21610680222511291504f, +0.97570210695266723633f,0.21910123527050018311f,0.97502535581588745117f, +0.22209362685680389404f,0.97433936595916748047f,0.22508391737937927246f, +0.97364425659179687500f,0.22807207703590393066f,0.97293996810913085938f, +0.23105810582637786865f,0.97222650051116943359f,0.23404195904731750488f, +0.97150391340255737305f,0.23702360689640045166f,0.97077214717864990234f, +0.24000301957130432129f,0.97003126144409179688f,0.24298018217086791992f, +0.96928125619888305664f,0.24595504999160766602f,0.96852207183837890625f, +0.24892760813236236572f,0.96775382757186889648f,0.25189781188964843750f, +0.96697646379470825195f,0.25486564636230468750f,0.96618998050689697266f, +0.25783109664916992188f,0.96539443731307983398f,0.26079410314559936523f, +0.96458977460861206055f,0.26375466585159301758f,0.96377605199813842773f, +0.26671275496482849121f,0.96295326948165893555f,0.26966831088066101074f, +0.96212142705917358398f,0.27262136340141296387f,0.96128046512603759766f, +0.27557182312011718750f,0.96043050289154052734f,0.27851969003677368164f, +0.95957154035568237305f,0.28146493434906005859f,0.95870345830917358398f, +0.28440752625465393066f,0.95782643556594848633f,0.28734746575355529785f, +0.95694035291671752930f,0.29028466343879699707f,0.95604526996612548828f, +0.29321914911270141602f,0.95514118671417236328f,0.29615089297294616699f, +0.95422810316085815430f,0.29907983541488647461f,0.95330601930618286133f, +0.30200594663619995117f,0.95237499475479125977f,0.30492922663688659668f, +0.95143502950668334961f,0.30784964561462402344f,0.95048606395721435547f, +0.31076714396476745605f,0.94952815771102905273f,0.31368175148963928223f, +0.94856137037277221680f,0.31659337878227233887f,0.94758558273315429688f, +0.31950202584266662598f,0.94660091400146484375f,0.32240769267082214355f, +0.94560730457305908203f,0.32531028985977172852f,0.94460481405258178711f, +0.32820984721183776855f,0.94359344244003295898f,0.33110630512237548828f, +0.94257318973541259766f,0.33399966359138488770f,0.94154405593872070312f, +0.33688986301422119141f,0.94050604104995727539f,0.33977687358856201172f, +0.93945920467376708984f,0.34266072511672973633f,0.93840354681015014648f, +0.34554132819175720215f,0.93733900785446166992f,0.34841868281364440918f, +0.93626564741134643555f,0.35129275918006896973f,0.93518352508544921875f, +0.35416352748870849609f,0.93409252166748046875f,0.35703095793724060059f, +0.93299281597137451172f,0.35989505052566528320f,0.93188428878784179688f, +0.36275571584701538086f,0.93076694011688232422f,0.36561298370361328125f, +0.92964088916778564453f,0.36846682429313659668f,0.92850607633590698242f, +0.37131720781326293945f,0.92736250162124633789f,0.37416407465934753418f, +0.92621022462844848633f,0.37700742483139038086f,0.92504924535751342773f, +0.37984719872474670410f,0.92387950420379638672f,0.38268342614173889160f, +0.92270112037658691406f,0.38551604747772216797f,0.92151403427124023438f, +0.38834503293037414551f,0.92031830549240112305f,0.39117038249969482422f, +0.91911387443542480469f,0.39399203658103942871f,0.91790080070495605469f, +0.39680999517440795898f,0.91667908430099487305f,0.39962419867515563965f, +0.91544872522354125977f,0.40243464708328247070f,0.91420978307723999023f, +0.40524131059646606445f,0.91296219825744628906f,0.40804415941238403320f, +0.91170603036880493164f,0.41084316372871398926f,0.91044127941131591797f, +0.41363832354545593262f,0.90916800498962402344f,0.41642954945564270020f, +0.90788608789443969727f,0.41921690106391906738f,0.90659570693969726562f, +0.42200025916099548340f,0.90529674291610717773f,0.42477968335151672363f, +0.90398931503295898438f,0.42755508422851562500f,0.90267330408096313477f, +0.43032649159431457520f,0.90134882926940917969f,0.43309381604194641113f, +0.90001589059829711914f,0.43585708737373352051f,0.89867448806762695312f, +0.43861624598503112793f,0.89732456207275390625f,0.44137126207351684570f, +0.89596623182296752930f,0.44412213563919067383f,0.89459949731826782227f, +0.44686883687973022461f,0.89322429895401000977f,0.44961133599281311035f, +0.89184069633483886719f,0.45234957337379455566f,0.89044874906539916992f, +0.45508357882499694824f,0.88904833793640136719f,0.45781329274177551270f, +0.88763964176177978516f,0.46053871512413024902f,0.88622254133224487305f, +0.46325978636741638184f,0.88479709625244140625f,0.46597650647163391113f, +0.88336336612701416016f,0.46868881583213806152f,0.88192129135131835938f, +0.47139674425125122070f,0.88047087192535400391f,0.47410020232200622559f, +0.87901222705841064453f,0.47679921984672546387f,0.87754529714584350586f, +0.47949376702308654785f,0.87607008218765258789f,0.48218378424644470215f, +0.87458664178848266602f,0.48486924171447753906f,0.87309497594833374023f, +0.48755016922950744629f,0.87159508466720581055f,0.49022647738456726074f, +0.87008696794509887695f,0.49289819598197937012f,0.86857068538665771484f, +0.49556526541709899902f,0.86704623699188232422f,0.49822765588760375977f, +0.86551362276077270508f,0.50088536739349365234f,0.86397284269332885742f, +0.50353837013244628906f,0.86242395639419555664f,0.50618666410446166992f, +0.86086696386337280273f,0.50883013010025024414f,0.85930180549621582031f, +0.51146882772445678711f,0.85772860050201416016f,0.51410275697708129883f, +0.85614734888076782227f,0.51673179864883422852f,0.85455799102783203125f, +0.51935601234436035156f,0.85296058654785156250f,0.52197527885437011719f, +0.85135519504547119141f,0.52458965778350830078f,0.84974175691604614258f, +0.52719914913177490234f,0.84812033176422119141f,0.52980363368988037109f, +0.84649091958999633789f,0.53240311145782470703f,0.84485357999801635742f, +0.53499764204025268555f,0.84320825338363647461f,0.53758704662322998047f, +0.84155499935150146484f,0.54017144441604614258f,0.83989381790161132812f, +0.54275077581405639648f,0.83822470903396606445f,0.54532498121261596680f, +0.83654773235321044922f,0.54789406061172485352f,0.83486288785934448242f, +0.55045795440673828125f,0.83317017555236816406f,0.55301672220230102539f, +0.83146959543228149414f,0.55557024478912353516f,0.82976120710372924805f, +0.55811852216720581055f,0.82804507017135620117f,0.56066155433654785156f, +0.82632106542587280273f,0.56319934129714965820f,0.82458931207656860352f, +0.56573182344436645508f,0.82284981012344360352f,0.56825894117355346680f, +0.82110249996185302734f,0.57078075408935546875f,0.81934750080108642578f, +0.57329714298248291016f,0.81758481264114379883f,0.57580816745758056641f, +0.81581443548202514648f,0.57831376791000366211f,0.81403630971908569336f, +0.58081394433975219727f,0.81225061416625976562f,0.58330863714218139648f, +0.81045717000961303711f,0.58579784631729125977f,0.80865615606307983398f, +0.58828157186508178711f,0.80684757232666015625f,0.59075969457626342773f, +0.80503135919570922852f,0.59323227405548095703f,0.80320751667022705078f, +0.59569931030273437500f,0.80137616395950317383f,0.59816068410873413086f, +0.79953724145889282227f,0.60061645507812500000f,0.79769086837768554688f, +0.60306662321090698242f,0.79583692550659179688f,0.60551106929779052734f, +0.79397547245025634766f,0.60794979333877563477f,0.79210656881332397461f, +0.61038279533386230469f,0.79023021459579467773f,0.61281007528305053711f, +0.78834640979766845703f,0.61523157358169555664f,0.78645521402359008789f, +0.61764729022979736328f,0.78455656766891479492f,0.62005722522735595703f, +0.78265058994293212891f,0.62246125936508178711f,0.78073722124099731445f, +0.62485951185226440430f,0.77881652116775512695f,0.62725180387496948242f, +0.77688848972320556641f,0.62963825464248657227f,0.77495312690734863281f, +0.63201874494552612305f,0.77301043272018432617f,0.63439327478408813477f, +0.77106052637100219727f,0.63676184415817260742f,0.76910334825515747070f, +0.63912445306777954102f,0.76713889837265014648f,0.64148104190826416016f, +0.76516723632812500000f,0.64383155107498168945f,0.76318842172622680664f, +0.64617604017257690430f,0.76120239496231079102f,0.64851438999176025391f, +0.75920921564102172852f,0.65084666013717651367f,0.75720882415771484375f, +0.65317285060882568359f,0.75520139932632446289f,0.65549284219741821289f, +0.75318682193756103516f,0.65780669450759887695f,0.75116515159606933594f, +0.66011434793472290039f,0.74913638830184936523f,0.66241580247879028320f, +0.74710059165954589844f,0.66471099853515625000f,0.74505776166915893555f, +0.66699993610382080078f,0.74300795793533325195f,0.66928261518478393555f, +0.74095112085342407227f,0.67155897617340087891f,0.73888731002807617188f, +0.67382901906967163086f,0.73681658506393432617f,0.67609268426895141602f, +0.73473888635635375977f,0.67835003137588500977f,0.73265427350997924805f, +0.68060100078582763672f,0.73056274652481079102f,0.68284553289413452148f, +0.72846436500549316406f,0.68508368730545043945f,0.72635912895202636719f, +0.68731534481048583984f,0.72424709796905517578f,0.68954056501388549805f, +0.72212821245193481445f,0.69175922870635986328f,0.72000253200531005859f, +0.69397145509719848633f,0.71787005662918090820f,0.69617712497711181641f, +0.71573084592819213867f,0.69837623834609985352f,0.71358484029769897461f, +0.70056879520416259766f,0.71143221855163574219f,0.70275473594665527344f, +0.70927280187606811523f,0.70493406057357788086f,0.70710676908493041992f, +0.70710676908493041992f,0.70493406057357788086f,0.70927280187606811523f, +0.70275473594665527344f,0.71143221855163574219f,0.70056879520416259766f, +0.71358484029769897461f,0.69837623834609985352f,0.71573084592819213867f, +0.69617712497711181641f,0.71787005662918090820f,0.69397145509719848633f, +0.72000253200531005859f,0.69175922870635986328f,0.72212821245193481445f, +0.68954056501388549805f,0.72424709796905517578f,0.68731534481048583984f, +0.72635912895202636719f,0.68508368730545043945f,0.72846436500549316406f, +0.68284553289413452148f,0.73056274652481079102f,0.68060100078582763672f, +0.73265427350997924805f,0.67835003137588500977f,0.73473888635635375977f, +0.67609268426895141602f,0.73681658506393432617f,0.67382901906967163086f, +0.73888731002807617188f,0.67155897617340087891f,0.74095112085342407227f, +0.66928261518478393555f,0.74300795793533325195f,0.66699993610382080078f, +0.74505776166915893555f,0.66471099853515625000f,0.74710059165954589844f, +0.66241580247879028320f,0.74913638830184936523f,0.66011434793472290039f, +0.75116515159606933594f,0.65780669450759887695f,0.75318682193756103516f, +0.65549284219741821289f,0.75520139932632446289f,0.65317285060882568359f, +0.75720882415771484375f,0.65084666013717651367f,0.75920921564102172852f, +0.64851438999176025391f,0.76120239496231079102f,0.64617604017257690430f, +0.76318842172622680664f,0.64383155107498168945f,0.76516723632812500000f, +0.64148104190826416016f,0.76713889837265014648f,0.63912445306777954102f, +0.76910334825515747070f,0.63676184415817260742f,0.77106052637100219727f, +0.63439327478408813477f,0.77301043272018432617f,0.63201874494552612305f, +0.77495312690734863281f,0.62963825464248657227f,0.77688848972320556641f, +0.62725180387496948242f,0.77881652116775512695f,0.62485951185226440430f, +0.78073722124099731445f,0.62246125936508178711f,0.78265058994293212891f, +0.62005722522735595703f,0.78455656766891479492f,0.61764729022979736328f, +0.78645521402359008789f,0.61523157358169555664f,0.78834640979766845703f, +0.61281007528305053711f,0.79023021459579467773f,0.61038279533386230469f, +0.79210656881332397461f,0.60794979333877563477f,0.79397547245025634766f, +0.60551106929779052734f,0.79583692550659179688f,0.60306662321090698242f, +0.79769086837768554688f,0.60061645507812500000f,0.79953724145889282227f, +0.59816068410873413086f,0.80137616395950317383f,0.59569931030273437500f, +0.80320751667022705078f,0.59323227405548095703f,0.80503135919570922852f, +0.59075969457626342773f,0.80684757232666015625f,0.58828157186508178711f, +0.80865615606307983398f,0.58579784631729125977f,0.81045717000961303711f, +0.58330863714218139648f,0.81225061416625976562f,0.58081394433975219727f, +0.81403630971908569336f,0.57831376791000366211f,0.81581443548202514648f, +0.57580816745758056641f,0.81758481264114379883f,0.57329714298248291016f, +0.81934750080108642578f,0.57078075408935546875f,0.82110249996185302734f, +0.56825894117355346680f,0.82284981012344360352f,0.56573182344436645508f, +0.82458931207656860352f,0.56319934129714965820f,0.82632106542587280273f, +0.56066155433654785156f,0.82804507017135620117f,0.55811852216720581055f, +0.82976120710372924805f,0.55557024478912353516f,0.83146959543228149414f, +0.55301672220230102539f,0.83317017555236816406f,0.55045795440673828125f, +0.83486288785934448242f,0.54789406061172485352f,0.83654773235321044922f, +0.54532498121261596680f,0.83822470903396606445f,0.54275077581405639648f, +0.83989381790161132812f,0.54017144441604614258f,0.84155499935150146484f, +0.53758704662322998047f,0.84320825338363647461f,0.53499764204025268555f, +0.84485357999801635742f,0.53240311145782470703f,0.84649091958999633789f, +0.52980363368988037109f,0.84812033176422119141f,0.52719914913177490234f, +0.84974175691604614258f,0.52458965778350830078f,0.85135519504547119141f, +0.52197527885437011719f,0.85296058654785156250f,0.51935601234436035156f, +0.85455799102783203125f,0.51673179864883422852f,0.85614734888076782227f, +0.51410275697708129883f,0.85772860050201416016f,0.51146882772445678711f, +0.85930180549621582031f,0.50883013010025024414f,0.86086696386337280273f, +0.50618666410446166992f,0.86242395639419555664f,0.50353837013244628906f, +0.86397284269332885742f,0.50088536739349365234f,0.86551362276077270508f, +0.49822765588760375977f,0.86704623699188232422f,0.49556526541709899902f, +0.86857068538665771484f,0.49289819598197937012f,0.87008696794509887695f, +0.49022647738456726074f,0.87159508466720581055f,0.48755016922950744629f, +0.87309497594833374023f,0.48486924171447753906f,0.87458664178848266602f, +0.48218378424644470215f,0.87607008218765258789f,0.47949376702308654785f, +0.87754529714584350586f,0.47679921984672546387f,0.87901222705841064453f, +0.47410020232200622559f,0.88047087192535400391f,0.47139674425125122070f, +0.88192129135131835938f,0.46868881583213806152f,0.88336336612701416016f, +0.46597650647163391113f,0.88479709625244140625f,0.46325978636741638184f, +0.88622254133224487305f,0.46053871512413024902f,0.88763964176177978516f, +0.45781329274177551270f,0.88904833793640136719f,0.45508357882499694824f, +0.89044874906539916992f,0.45234957337379455566f,0.89184069633483886719f, +0.44961133599281311035f,0.89322429895401000977f,0.44686883687973022461f, +0.89459949731826782227f,0.44412213563919067383f,0.89596623182296752930f, +0.44137126207351684570f,0.89732456207275390625f,0.43861624598503112793f, +0.89867448806762695312f,0.43585708737373352051f,0.90001589059829711914f, +0.43309381604194641113f,0.90134882926940917969f,0.43032649159431457520f, +0.90267330408096313477f,0.42755508422851562500f,0.90398931503295898438f, +0.42477968335151672363f,0.90529674291610717773f,0.42200025916099548340f, +0.90659570693969726562f,0.41921690106391906738f,0.90788608789443969727f, +0.41642954945564270020f,0.90916800498962402344f,0.41363832354545593262f, +0.91044127941131591797f,0.41084316372871398926f,0.91170603036880493164f, +0.40804415941238403320f,0.91296219825744628906f,0.40524131059646606445f, +0.91420978307723999023f,0.40243464708328247070f,0.91544872522354125977f, +0.39962419867515563965f,0.91667908430099487305f,0.39680999517440795898f, +0.91790080070495605469f,0.39399203658103942871f,0.91911387443542480469f, +0.39117038249969482422f,0.92031830549240112305f,0.38834503293037414551f, +0.92151403427124023438f,0.38551604747772216797f,0.92270112037658691406f, +0.38268342614173889160f,0.92387950420379638672f,0.37984719872474670410f, +0.92504924535751342773f,0.37700742483139038086f,0.92621022462844848633f, +0.37416407465934753418f,0.92736250162124633789f,0.37131720781326293945f, +0.92850607633590698242f,0.36846682429313659668f,0.92964088916778564453f, +0.36561298370361328125f,0.93076694011688232422f,0.36275571584701538086f, +0.93188428878784179688f,0.35989505052566528320f,0.93299281597137451172f, +0.35703095793724060059f,0.93409252166748046875f,0.35416352748870849609f, +0.93518352508544921875f,0.35129275918006896973f,0.93626564741134643555f, +0.34841868281364440918f,0.93733900785446166992f,0.34554132819175720215f, +0.93840354681015014648f,0.34266072511672973633f,0.93945920467376708984f, +0.33977687358856201172f,0.94050604104995727539f,0.33688986301422119141f, +0.94154405593872070312f,0.33399966359138488770f,0.94257318973541259766f, +0.33110630512237548828f,0.94359344244003295898f,0.32820984721183776855f, +0.94460481405258178711f,0.32531028985977172852f,0.94560730457305908203f, +0.32240769267082214355f,0.94660091400146484375f,0.31950202584266662598f, +0.94758558273315429688f,0.31659337878227233887f,0.94856137037277221680f, +0.31368175148963928223f,0.94952815771102905273f,0.31076714396476745605f, +0.95048606395721435547f,0.30784964561462402344f,0.95143502950668334961f, +0.30492922663688659668f,0.95237499475479125977f,0.30200594663619995117f, +0.95330601930618286133f,0.29907983541488647461f,0.95422810316085815430f, +0.29615089297294616699f,0.95514118671417236328f,0.29321914911270141602f, +0.95604526996612548828f,0.29028466343879699707f,0.95694035291671752930f, +0.28734746575355529785f,0.95782643556594848633f,0.28440752625465393066f, +0.95870345830917358398f,0.28146493434906005859f,0.95957154035568237305f, +0.27851969003677368164f,0.96043050289154052734f,0.27557182312011718750f, +0.96128046512603759766f,0.27262136340141296387f,0.96212142705917358398f, +0.26966831088066101074f,0.96295326948165893555f,0.26671275496482849121f, +0.96377605199813842773f,0.26375466585159301758f,0.96458977460861206055f, +0.26079410314559936523f,0.96539443731307983398f,0.25783109664916992188f, +0.96618998050689697266f,0.25486564636230468750f,0.96697646379470825195f, +0.25189781188964843750f,0.96775382757186889648f,0.24892760813236236572f, +0.96852207183837890625f,0.24595504999160766602f,0.96928125619888305664f, +0.24298018217086791992f,0.97003126144409179688f,0.24000301957130432129f, +0.97077214717864990234f,0.23702360689640045166f,0.97150391340255737305f, +0.23404195904731750488f,0.97222650051116943359f,0.23105810582637786865f, +0.97293996810913085938f,0.22807207703590393066f,0.97364425659179687500f, +0.22508391737937927246f,0.97433936595916748047f,0.22209362685680389404f, +0.97502535581588745117f,0.21910123527050018311f,0.97570210695266723633f, +0.21610680222511291504f,0.97636973857879638672f,0.21311031281948089600f, +0.97702813148498535156f,0.21011184155941009521f,0.97767734527587890625f, +0.20711137354373931885f,0.97831737995147705078f,0.20410896837711334229f, +0.97894817590713500977f,0.20110464096069335938f,0.97956979274749755859f, +0.19809840619564056396f,0.98018211126327514648f,0.19509032368659973145f, +0.98078525066375732422f,0.19208039343357086182f,0.98137921094894409180f, +0.18906866014003753662f,0.98196387290954589844f,0.18605515360832214355f, +0.98253929615020751953f,0.18303988873958587646f,0.98310548067092895508f, +0.18002289533615112305f,0.98366242647171020508f,0.17700421810150146484f, +0.98421007394790649414f,0.17398387193679809570f,0.98474848270416259766f, +0.17096188664436340332f,0.98527765274047851562f,0.16793829202651977539f, +0.98579752445220947266f,0.16491311788558959961f,0.98630809783935546875f, +0.16188639402389526367f,0.98680937290191650391f,0.15885815024375915527f, +0.98730140924453735352f,0.15582840144634246826f,0.98778414726257324219f, +0.15279719233512878418f,0.98825758695602416992f,0.14976453781127929688f, +0.98872166872024536133f,0.14673046767711639404f,0.98917651176452636719f, +0.14369502663612365723f,0.98962199687957763672f,0.14065824449062347412f, +0.99005818367004394531f,0.13762012124061584473f,0.99048507213592529297f, +0.13458070158958435059f,0.99090266227722167969f,0.13154003024101257324f, +0.99131083488464355469f,0.12849810719490051270f,0.99170976877212524414f, +0.12545497715473175049f,0.99209928512573242188f,0.12241067737340927124f, +0.99247956275939941406f,0.11936521530151367188f,0.99285042285919189453f, +0.11631862819194793701f,0.99321192502975463867f,0.11327095329761505127f, +0.99356412887573242188f,0.11022220551967620850f,0.99390697479248046875f, +0.10717242211103439331f,0.99424046277999877930f,0.10412163287401199341f, +0.99456459283828735352f,0.10106986016035079956f,0.99487930536270141602f, +0.09801714122295379639f,0.99518471956253051758f,0.09496349841356277466f, +0.99548077583312988281f,0.09190895408391952515f,0.99576741456985473633f, +0.08885355293750762939f,0.99604469537734985352f,0.08579730987548828125f, +0.99631261825561523438f,0.08274026215076446533f,0.99657112360000610352f, +0.07968243956565856934f,0.99682027101516723633f,0.07662386447191238403f, +0.99706006050109863281f,0.07356456667184829712f,0.99729043245315551758f, +0.07050457596778869629f,0.99751144647598266602f,0.06744392216205596924f, +0.99772304296493530273f,0.06438262760639190674f,0.99792528152465820312f, +0.06132073700428009033f,0.99811810255050659180f,0.05825826525688171387f, +0.99830156564712524414f,0.05519524589180946350f,0.99847555160522460938f, +0.05213170498609542847f,0.99864023923873901367f,0.04906767606735229492f, +0.99879544973373413086f,0.04600318148732185364f,0.99894130229949951172f, +0.04293825849890708923f,0.99907773733139038086f,0.03987292572855949402f, +0.99920475482940673828f,0.03680722415447235107f,0.99932235479354858398f, +0.03374117240309715271f,0.99943059682846069336f,0.03067480400204658508f, +0.99952942132949829102f,0.02760814502835273743f,0.99961882829666137695f, +0.02454122900962829590f,0.99969881772994995117f,0.02147408016026020050f, +0.99976938962936401367f,0.01840673014521598816f,0.99983060359954833984f, +0.01533920597285032272f,0.99988234043121337891f,0.01227153837680816650f, +0.99992471933364868164f,0.00920375436544418335f,0.99995762109756469727f, +0.00613588467240333557f,0.99998116493225097656f,0.00306795677170157433f, +0.99999529123306274414f,0.00000000000000006123f,1.00000000000000000000f, +-0.00306795677170157433f,0.99999529123306274414f,-0.00613588467240333557f, +0.99998116493225097656f,-0.00920375436544418335f,0.99995762109756469727f, +-0.01227153837680816650f,0.99992471933364868164f,-0.01533920597285032272f, +0.99988234043121337891f,-0.01840673014521598816f,0.99983060359954833984f, +-0.02147408016026020050f,0.99976938962936401367f,-0.02454122900962829590f, +0.99969881772994995117f,-0.02760814502835273743f,0.99961882829666137695f, +-0.03067480400204658508f,0.99952942132949829102f,-0.03374117240309715271f, +0.99943059682846069336f,-0.03680722415447235107f,0.99932235479354858398f, +-0.03987292572855949402f,0.99920475482940673828f,-0.04293825849890708923f, +0.99907773733139038086f,-0.04600318148732185364f,0.99894130229949951172f, +-0.04906767606735229492f,0.99879544973373413086f,-0.05213170498609542847f, +0.99864023923873901367f,-0.05519524589180946350f,0.99847555160522460938f, +-0.05825826525688171387f,0.99830156564712524414f,-0.06132073700428009033f, +0.99811810255050659180f,-0.06438262760639190674f,0.99792528152465820312f, +-0.06744392216205596924f,0.99772304296493530273f,-0.07050457596778869629f, +0.99751144647598266602f,-0.07356456667184829712f,0.99729043245315551758f, +-0.07662386447191238403f,0.99706006050109863281f,-0.07968243956565856934f, +0.99682027101516723633f,-0.08274026215076446533f,0.99657112360000610352f, +-0.08579730987548828125f,0.99631261825561523438f,-0.08885355293750762939f, +0.99604469537734985352f,-0.09190895408391952515f,0.99576741456985473633f, +-0.09496349841356277466f,0.99548077583312988281f,-0.09801714122295379639f, +0.99518471956253051758f,-0.10106986016035079956f,0.99487930536270141602f, +-0.10412163287401199341f,0.99456459283828735352f,-0.10717242211103439331f, +0.99424046277999877930f,-0.11022220551967620850f,0.99390697479248046875f, +-0.11327095329761505127f,0.99356412887573242188f,-0.11631862819194793701f, +0.99321192502975463867f,-0.11936521530151367188f,0.99285042285919189453f, +-0.12241067737340927124f,0.99247956275939941406f,-0.12545497715473175049f, +0.99209928512573242188f,-0.12849810719490051270f,0.99170976877212524414f, +-0.13154003024101257324f,0.99131083488464355469f,-0.13458070158958435059f, +0.99090266227722167969f,-0.13762012124061584473f,0.99048507213592529297f, +-0.14065824449062347412f,0.99005818367004394531f,-0.14369502663612365723f, +0.98962199687957763672f,-0.14673046767711639404f,0.98917651176452636719f, +-0.14976453781127929688f,0.98872166872024536133f,-0.15279719233512878418f, +0.98825758695602416992f,-0.15582840144634246826f,0.98778414726257324219f, +-0.15885815024375915527f,0.98730140924453735352f,-0.16188639402389526367f, +0.98680937290191650391f,-0.16491311788558959961f,0.98630809783935546875f, +-0.16793829202651977539f,0.98579752445220947266f,-0.17096188664436340332f, +0.98527765274047851562f,-0.17398387193679809570f,0.98474848270416259766f, +-0.17700421810150146484f,0.98421007394790649414f,-0.18002289533615112305f, +0.98366242647171020508f,-0.18303988873958587646f,0.98310548067092895508f, +-0.18605515360832214355f,0.98253929615020751953f,-0.18906866014003753662f, +0.98196387290954589844f,-0.19208039343357086182f,0.98137921094894409180f, +-0.19509032368659973145f,0.98078525066375732422f,-0.19809840619564056396f, +0.98018211126327514648f,-0.20110464096069335938f,0.97956979274749755859f, +-0.20410896837711334229f,0.97894817590713500977f,-0.20711137354373931885f, +0.97831737995147705078f,-0.21011184155941009521f,0.97767734527587890625f, +-0.21311031281948089600f,0.97702813148498535156f,-0.21610680222511291504f, +0.97636973857879638672f,-0.21910123527050018311f,0.97570210695266723633f, +-0.22209362685680389404f,0.97502535581588745117f,-0.22508391737937927246f, +0.97433936595916748047f,-0.22807207703590393066f,0.97364425659179687500f, +-0.23105810582637786865f,0.97293996810913085938f,-0.23404195904731750488f, +0.97222650051116943359f,-0.23702360689640045166f,0.97150391340255737305f, +-0.24000301957130432129f,0.97077214717864990234f,-0.24298018217086791992f, +0.97003126144409179688f,-0.24595504999160766602f,0.96928125619888305664f, +-0.24892760813236236572f,0.96852207183837890625f,-0.25189781188964843750f, +0.96775382757186889648f,-0.25486564636230468750f,0.96697646379470825195f, +-0.25783109664916992188f,0.96618998050689697266f,-0.26079410314559936523f, +0.96539443731307983398f,-0.26375466585159301758f,0.96458977460861206055f, +-0.26671275496482849121f,0.96377605199813842773f,-0.26966831088066101074f, +0.96295326948165893555f,-0.27262136340141296387f,0.96212142705917358398f, +-0.27557182312011718750f,0.96128046512603759766f,-0.27851969003677368164f, +0.96043050289154052734f,-0.28146493434906005859f,0.95957154035568237305f, +-0.28440752625465393066f,0.95870345830917358398f,-0.28734746575355529785f, +0.95782643556594848633f,-0.29028466343879699707f,0.95694035291671752930f, +-0.29321914911270141602f,0.95604526996612548828f,-0.29615089297294616699f, +0.95514118671417236328f,-0.29907983541488647461f,0.95422810316085815430f, +-0.30200594663619995117f,0.95330601930618286133f,-0.30492922663688659668f, +0.95237499475479125977f,-0.30784964561462402344f,0.95143502950668334961f, +-0.31076714396476745605f,0.95048606395721435547f,-0.31368175148963928223f, +0.94952815771102905273f,-0.31659337878227233887f,0.94856137037277221680f, +-0.31950202584266662598f,0.94758558273315429688f,-0.32240769267082214355f, +0.94660091400146484375f,-0.32531028985977172852f,0.94560730457305908203f, +-0.32820984721183776855f,0.94460481405258178711f,-0.33110630512237548828f, +0.94359344244003295898f,-0.33399966359138488770f,0.94257318973541259766f, +-0.33688986301422119141f,0.94154405593872070312f,-0.33977687358856201172f, +0.94050604104995727539f,-0.34266072511672973633f,0.93945920467376708984f, +-0.34554132819175720215f,0.93840354681015014648f,-0.34841868281364440918f, +0.93733900785446166992f,-0.35129275918006896973f,0.93626564741134643555f, +-0.35416352748870849609f,0.93518352508544921875f,-0.35703095793724060059f, +0.93409252166748046875f,-0.35989505052566528320f,0.93299281597137451172f, +-0.36275571584701538086f,0.93188428878784179688f,-0.36561298370361328125f, +0.93076694011688232422f,-0.36846682429313659668f,0.92964088916778564453f, +-0.37131720781326293945f,0.92850607633590698242f,-0.37416407465934753418f, +0.92736250162124633789f,-0.37700742483139038086f,0.92621022462844848633f, +-0.37984719872474670410f,0.92504924535751342773f,-0.38268342614173889160f, +0.92387950420379638672f,-0.38551604747772216797f,0.92270112037658691406f, +-0.38834503293037414551f,0.92151403427124023438f,-0.39117038249969482422f, +0.92031830549240112305f,-0.39399203658103942871f,0.91911387443542480469f, +-0.39680999517440795898f,0.91790080070495605469f,-0.39962419867515563965f, +0.91667908430099487305f,-0.40243464708328247070f,0.91544872522354125977f, +-0.40524131059646606445f,0.91420978307723999023f,-0.40804415941238403320f, +0.91296219825744628906f,-0.41084316372871398926f,0.91170603036880493164f, +-0.41363832354545593262f,0.91044127941131591797f,-0.41642954945564270020f, +0.90916800498962402344f,-0.41921690106391906738f,0.90788608789443969727f, +-0.42200025916099548340f,0.90659570693969726562f,-0.42477968335151672363f, +0.90529674291610717773f,-0.42755508422851562500f,0.90398931503295898438f, +-0.43032649159431457520f,0.90267330408096313477f,-0.43309381604194641113f, +0.90134882926940917969f,-0.43585708737373352051f,0.90001589059829711914f, +-0.43861624598503112793f,0.89867448806762695312f,-0.44137126207351684570f, +0.89732456207275390625f,-0.44412213563919067383f,0.89596623182296752930f, +-0.44686883687973022461f,0.89459949731826782227f,-0.44961133599281311035f, +0.89322429895401000977f,-0.45234957337379455566f,0.89184069633483886719f, +-0.45508357882499694824f,0.89044874906539916992f,-0.45781329274177551270f, +0.88904833793640136719f,-0.46053871512413024902f,0.88763964176177978516f, +-0.46325978636741638184f,0.88622254133224487305f,-0.46597650647163391113f, +0.88479709625244140625f,-0.46868881583213806152f,0.88336336612701416016f, +-0.47139674425125122070f,0.88192129135131835938f,-0.47410020232200622559f, +0.88047087192535400391f,-0.47679921984672546387f,0.87901222705841064453f, +-0.47949376702308654785f,0.87754529714584350586f,-0.48218378424644470215f, +0.87607008218765258789f,-0.48486924171447753906f,0.87458664178848266602f, +-0.48755016922950744629f,0.87309497594833374023f,-0.49022647738456726074f, +0.87159508466720581055f,-0.49289819598197937012f,0.87008696794509887695f, +-0.49556526541709899902f,0.86857068538665771484f,-0.49822765588760375977f, +0.86704623699188232422f,-0.50088536739349365234f,0.86551362276077270508f, +-0.50353837013244628906f,0.86397284269332885742f,-0.50618666410446166992f, +0.86242395639419555664f,-0.50883013010025024414f,0.86086696386337280273f, +-0.51146882772445678711f,0.85930180549621582031f,-0.51410275697708129883f, +0.85772860050201416016f,-0.51673179864883422852f,0.85614734888076782227f, +-0.51935601234436035156f,0.85455799102783203125f,-0.52197527885437011719f, +0.85296058654785156250f,-0.52458965778350830078f,0.85135519504547119141f, +-0.52719914913177490234f,0.84974175691604614258f,-0.52980363368988037109f, +0.84812033176422119141f,-0.53240311145782470703f,0.84649091958999633789f, +-0.53499764204025268555f,0.84485357999801635742f,-0.53758704662322998047f, +0.84320825338363647461f,-0.54017144441604614258f,0.84155499935150146484f, +-0.54275077581405639648f,0.83989381790161132812f,-0.54532498121261596680f, +0.83822470903396606445f,-0.54789406061172485352f,0.83654773235321044922f, +-0.55045795440673828125f,0.83486288785934448242f,-0.55301672220230102539f, +0.83317017555236816406f,-0.55557024478912353516f,0.83146959543228149414f, +-0.55811852216720581055f,0.82976120710372924805f,-0.56066155433654785156f, +0.82804507017135620117f,-0.56319934129714965820f,0.82632106542587280273f, +-0.56573182344436645508f,0.82458931207656860352f,-0.56825894117355346680f, +0.82284981012344360352f,-0.57078075408935546875f,0.82110249996185302734f, +-0.57329714298248291016f,0.81934750080108642578f,-0.57580816745758056641f, +0.81758481264114379883f,-0.57831376791000366211f,0.81581443548202514648f, +-0.58081394433975219727f,0.81403630971908569336f,-0.58330863714218139648f, +0.81225061416625976562f,-0.58579784631729125977f,0.81045717000961303711f, +-0.58828157186508178711f,0.80865615606307983398f,-0.59075969457626342773f, +0.80684757232666015625f,-0.59323227405548095703f,0.80503135919570922852f, +-0.59569931030273437500f,0.80320751667022705078f,-0.59816068410873413086f, +0.80137616395950317383f,-0.60061645507812500000f,0.79953724145889282227f, +-0.60306662321090698242f,0.79769086837768554688f,-0.60551106929779052734f, +0.79583692550659179688f,-0.60794979333877563477f,0.79397547245025634766f, +-0.61038279533386230469f,0.79210656881332397461f,-0.61281007528305053711f, +0.79023021459579467773f,-0.61523157358169555664f,0.78834640979766845703f, +-0.61764729022979736328f,0.78645521402359008789f,-0.62005722522735595703f, +0.78455656766891479492f,-0.62246125936508178711f,0.78265058994293212891f, +-0.62485951185226440430f,0.78073722124099731445f,-0.62725180387496948242f, +0.77881652116775512695f,-0.62963825464248657227f,0.77688848972320556641f, +-0.63201874494552612305f,0.77495312690734863281f,-0.63439327478408813477f, +0.77301043272018432617f,-0.63676184415817260742f,0.77106052637100219727f, +-0.63912445306777954102f,0.76910334825515747070f,-0.64148104190826416016f, +0.76713889837265014648f,-0.64383155107498168945f,0.76516723632812500000f, +-0.64617604017257690430f,0.76318842172622680664f,-0.64851438999176025391f, +0.76120239496231079102f,-0.65084666013717651367f,0.75920921564102172852f, +-0.65317285060882568359f,0.75720882415771484375f,-0.65549284219741821289f, +0.75520139932632446289f,-0.65780669450759887695f,0.75318682193756103516f, +-0.66011434793472290039f,0.75116515159606933594f,-0.66241580247879028320f, +0.74913638830184936523f,-0.66471099853515625000f,0.74710059165954589844f, +-0.66699993610382080078f,0.74505776166915893555f,-0.66928261518478393555f, +0.74300795793533325195f,-0.67155897617340087891f,0.74095112085342407227f, +-0.67382901906967163086f,0.73888731002807617188f,-0.67609268426895141602f, +0.73681658506393432617f,-0.67835003137588500977f,0.73473888635635375977f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68284553289413452148f, +0.73056274652481079102f,-0.68508368730545043945f,0.72846436500549316406f, +-0.68731534481048583984f,0.72635912895202636719f,-0.68954056501388549805f, +0.72424709796905517578f,-0.69175922870635986328f,0.72212821245193481445f, +-0.69397145509719848633f,0.72000253200531005859f,-0.69617712497711181641f, +0.71787005662918090820f,-0.69837623834609985352f,0.71573084592819213867f, +-0.70056879520416259766f,0.71358484029769897461f,-0.70275473594665527344f, +0.71143221855163574219f,-0.70493406057357788086f,0.70927280187606811523f, +-0.70710676908493041992f,0.70710676908493041992f,-0.70927280187606811523f, +0.70493406057357788086f,-0.71143221855163574219f,0.70275473594665527344f, +-0.71358484029769897461f,0.70056879520416259766f,-0.71573084592819213867f, +0.69837623834609985352f,-0.71787005662918090820f,0.69617712497711181641f, +-0.72000253200531005859f,0.69397145509719848633f,-0.72212821245193481445f, +0.69175922870635986328f,-0.72424709796905517578f,0.68954056501388549805f, +-0.72635912895202636719f,0.68731534481048583984f,-0.72846436500549316406f, +0.68508368730545043945f,-0.73056274652481079102f,0.68284553289413452148f, +-0.73265427350997924805f,0.68060100078582763672f,-0.73473888635635375977f, +0.67835003137588500977f,-0.73681658506393432617f,0.67609268426895141602f, +-0.73888731002807617188f,0.67382901906967163086f,-0.74095112085342407227f, +0.67155897617340087891f,-0.74300795793533325195f,0.66928261518478393555f, +-0.74505776166915893555f,0.66699993610382080078f,-0.74710059165954589844f, +0.66471099853515625000f,-0.74913638830184936523f,0.66241580247879028320f, +-0.75116515159606933594f,0.66011434793472290039f,-0.75318682193756103516f, +0.65780669450759887695f,-0.75520139932632446289f,0.65549284219741821289f, +-0.75720882415771484375f,0.65317285060882568359f,-0.75920921564102172852f, +0.65084666013717651367f,-0.76120239496231079102f,0.64851438999176025391f, +-0.76318842172622680664f,0.64617604017257690430f,-0.76516723632812500000f, +0.64383155107498168945f,-0.76713889837265014648f,0.64148104190826416016f, +-0.76910334825515747070f,0.63912445306777954102f,-0.77106052637100219727f, +0.63676184415817260742f,-0.77301043272018432617f,0.63439327478408813477f, +-0.77495312690734863281f,0.63201874494552612305f,-0.77688848972320556641f, +0.62963825464248657227f,-0.77881652116775512695f,0.62725180387496948242f, +-0.78073722124099731445f,0.62485951185226440430f,-0.78265058994293212891f, +0.62246125936508178711f,-0.78455656766891479492f,0.62005722522735595703f, +-0.78645521402359008789f,0.61764729022979736328f,-0.78834640979766845703f, +0.61523157358169555664f,-0.79023021459579467773f,0.61281007528305053711f, +-0.79210656881332397461f,0.61038279533386230469f,-0.79397547245025634766f, +0.60794979333877563477f,-0.79583692550659179688f,0.60551106929779052734f, +-0.79769086837768554688f,0.60306662321090698242f,-0.79953724145889282227f, +0.60061645507812500000f,-0.80137616395950317383f,0.59816068410873413086f, +-0.80320751667022705078f,0.59569931030273437500f,-0.80503135919570922852f, +0.59323227405548095703f,-0.80684757232666015625f,0.59075969457626342773f, +-0.80865615606307983398f,0.58828157186508178711f,-0.81045717000961303711f, +0.58579784631729125977f,-0.81225061416625976562f,0.58330863714218139648f, +-0.81403630971908569336f,0.58081394433975219727f,-0.81581443548202514648f, +0.57831376791000366211f,-0.81758481264114379883f,0.57580816745758056641f, +-0.81934750080108642578f,0.57329714298248291016f,-0.82110249996185302734f, +0.57078075408935546875f,-0.82284981012344360352f,0.56825894117355346680f, +-0.82458931207656860352f,0.56573182344436645508f,-0.82632106542587280273f, +0.56319934129714965820f,-0.82804507017135620117f,0.56066155433654785156f, +-0.82976120710372924805f,0.55811852216720581055f,-0.83146959543228149414f, +0.55557024478912353516f,-0.83317017555236816406f,0.55301672220230102539f, +-0.83486288785934448242f,0.55045795440673828125f,-0.83654773235321044922f, +0.54789406061172485352f,-0.83822470903396606445f,0.54532498121261596680f, +-0.83989381790161132812f,0.54275077581405639648f,-0.84155499935150146484f, +0.54017144441604614258f,-0.84320825338363647461f,0.53758704662322998047f, +-0.84485357999801635742f,0.53499764204025268555f,-0.84649091958999633789f, +0.53240311145782470703f,-0.84812033176422119141f,0.52980363368988037109f, +-0.84974175691604614258f,0.52719914913177490234f,-0.85135519504547119141f, +0.52458965778350830078f,-0.85296058654785156250f,0.52197527885437011719f, +-0.85455799102783203125f,0.51935601234436035156f,-0.85614734888076782227f, +0.51673179864883422852f,-0.85772860050201416016f,0.51410275697708129883f, +-0.85930180549621582031f,0.51146882772445678711f,-0.86086696386337280273f, +0.50883013010025024414f,-0.86242395639419555664f,0.50618666410446166992f, +-0.86397284269332885742f,0.50353837013244628906f,-0.86551362276077270508f, +0.50088536739349365234f,-0.86704623699188232422f,0.49822765588760375977f, +-0.86857068538665771484f,0.49556526541709899902f,-0.87008696794509887695f, +0.49289819598197937012f,-0.87159508466720581055f,0.49022647738456726074f, +-0.87309497594833374023f,0.48755016922950744629f,-0.87458664178848266602f, +0.48486924171447753906f,-0.87607008218765258789f,0.48218378424644470215f, +-0.87754529714584350586f,0.47949376702308654785f,-0.87901222705841064453f, +0.47679921984672546387f,-0.88047087192535400391f,0.47410020232200622559f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88336336612701416016f, +0.46868881583213806152f,-0.88479709625244140625f,0.46597650647163391113f, +-0.88622254133224487305f,0.46325978636741638184f,-0.88763964176177978516f, +0.46053871512413024902f,-0.88904833793640136719f,0.45781329274177551270f, +-0.89044874906539916992f,0.45508357882499694824f,-0.89184069633483886719f, +0.45234957337379455566f,-0.89322429895401000977f,0.44961133599281311035f, +-0.89459949731826782227f,0.44686883687973022461f,-0.89596623182296752930f, +0.44412213563919067383f,-0.89732456207275390625f,0.44137126207351684570f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90001589059829711914f, +0.43585708737373352051f,-0.90134882926940917969f,0.43309381604194641113f, +-0.90267330408096313477f,0.43032649159431457520f,-0.90398931503295898438f, +0.42755508422851562500f,-0.90529674291610717773f,0.42477968335151672363f, +-0.90659570693969726562f,0.42200025916099548340f,-0.90788608789443969727f, +0.41921690106391906738f,-0.90916800498962402344f,0.41642954945564270020f, +-0.91044127941131591797f,0.41363832354545593262f,-0.91170603036880493164f, +0.41084316372871398926f,-0.91296219825744628906f,0.40804415941238403320f, +-0.91420978307723999023f,0.40524131059646606445f,-0.91544872522354125977f, +0.40243464708328247070f,-0.91667908430099487305f,0.39962419867515563965f, +-0.91790080070495605469f,0.39680999517440795898f,-0.91911387443542480469f, +0.39399203658103942871f,-0.92031830549240112305f,0.39117038249969482422f, +-0.92151403427124023438f,0.38834503293037414551f,-0.92270112037658691406f, +0.38551604747772216797f,-0.92387950420379638672f,0.38268342614173889160f, +-0.92504924535751342773f,0.37984719872474670410f,-0.92621022462844848633f, +0.37700742483139038086f,-0.92736250162124633789f,0.37416407465934753418f, +-0.92850607633590698242f,0.37131720781326293945f,-0.92964088916778564453f, +0.36846682429313659668f,-0.93076694011688232422f,0.36561298370361328125f, +-0.93188428878784179688f,0.36275571584701538086f,-0.93299281597137451172f, +0.35989505052566528320f,-0.93409252166748046875f,0.35703095793724060059f, +-0.93518352508544921875f,0.35416352748870849609f,-0.93626564741134643555f, +0.35129275918006896973f,-0.93733900785446166992f,0.34841868281364440918f, +-0.93840354681015014648f,0.34554132819175720215f,-0.93945920467376708984f, +0.34266072511672973633f,-0.94050604104995727539f,0.33977687358856201172f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94257318973541259766f, +0.33399966359138488770f,-0.94359344244003295898f,0.33110630512237548828f, +-0.94460481405258178711f,0.32820984721183776855f,-0.94560730457305908203f, +0.32531028985977172852f,-0.94660091400146484375f,0.32240769267082214355f, +-0.94758558273315429688f,0.31950202584266662598f,-0.94856137037277221680f, +0.31659337878227233887f,-0.94952815771102905273f,0.31368175148963928223f, +-0.95048606395721435547f,0.31076714396476745605f,-0.95143502950668334961f, +0.30784964561462402344f,-0.95237499475479125977f,0.30492922663688659668f, +-0.95330601930618286133f,0.30200594663619995117f,-0.95422810316085815430f, +0.29907983541488647461f,-0.95514118671417236328f,0.29615089297294616699f, +-0.95604526996612548828f,0.29321914911270141602f,-0.95694035291671752930f, +0.29028466343879699707f,-0.95782643556594848633f,0.28734746575355529785f, +-0.95870345830917358398f,0.28440752625465393066f,-0.95957154035568237305f, +0.28146493434906005859f,-0.96043050289154052734f,0.27851969003677368164f, +-0.96128046512603759766f,0.27557182312011718750f,-0.96212142705917358398f, +0.27262136340141296387f,-0.96295326948165893555f,0.26966831088066101074f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96458977460861206055f, +0.26375466585159301758f,-0.96539443731307983398f,0.26079410314559936523f, +-0.96618998050689697266f,0.25783109664916992188f,-0.96697646379470825195f, +0.25486564636230468750f,-0.96775382757186889648f,0.25189781188964843750f, +-0.96852207183837890625f,0.24892760813236236572f,-0.96928125619888305664f, +0.24595504999160766602f,-0.97003126144409179688f,0.24298018217086791992f, +-0.97077214717864990234f,0.24000301957130432129f,-0.97150391340255737305f, +0.23702360689640045166f,-0.97222650051116943359f,0.23404195904731750488f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97364425659179687500f, +0.22807207703590393066f,-0.97433936595916748047f,0.22508391737937927246f, +-0.97502535581588745117f,0.22209362685680389404f,-0.97570210695266723633f, +0.21910123527050018311f,-0.97636973857879638672f,0.21610680222511291504f, +-0.97702813148498535156f,0.21311031281948089600f,-0.97767734527587890625f, +0.21011184155941009521f,-0.97831737995147705078f,0.20711137354373931885f, +-0.97894817590713500977f,0.20410896837711334229f,-0.97956979274749755859f, +0.20110464096069335938f,-0.98018211126327514648f,0.19809840619564056396f, +-0.98078525066375732422f,0.19509032368659973145f,-0.98137921094894409180f, +0.19208039343357086182f,-0.98196387290954589844f,0.18906866014003753662f, +-0.98253929615020751953f,0.18605515360832214355f,-0.98310548067092895508f, +0.18303988873958587646f,-0.98366242647171020508f,0.18002289533615112305f, +-0.98421007394790649414f,0.17700421810150146484f,-0.98474848270416259766f, +0.17398387193679809570f,-0.98527765274047851562f,0.17096188664436340332f, +-0.98579752445220947266f,0.16793829202651977539f,-0.98630809783935546875f, +0.16491311788558959961f,-0.98680937290191650391f,0.16188639402389526367f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98778414726257324219f, +0.15582840144634246826f,-0.98825758695602416992f,0.15279719233512878418f, +-0.98872166872024536133f,0.14976453781127929688f,-0.98917651176452636719f, +0.14673046767711639404f,-0.98962199687957763672f,0.14369502663612365723f, +-0.99005818367004394531f,0.14065824449062347412f,-0.99048507213592529297f, +0.13762012124061584473f,-0.99090266227722167969f,0.13458070158958435059f, +-0.99131083488464355469f,0.13154003024101257324f,-0.99170976877212524414f, +0.12849810719490051270f,-0.99209928512573242188f,0.12545497715473175049f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99285042285919189453f, +0.11936521530151367188f,-0.99321192502975463867f,0.11631862819194793701f, +-0.99356412887573242188f,0.11327095329761505127f,-0.99390697479248046875f, +0.11022220551967620850f,-0.99424046277999877930f,0.10717242211103439331f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99487930536270141602f, +0.10106986016035079956f,-0.99518471956253051758f,0.09801714122295379639f, +-0.99548077583312988281f,0.09496349841356277466f,-0.99576741456985473633f, +0.09190895408391952515f,-0.99604469537734985352f,0.08885355293750762939f, +-0.99631261825561523438f,0.08579730987548828125f,-0.99657112360000610352f, +0.08274026215076446533f,-0.99682027101516723633f,0.07968243956565856934f, +-0.99706006050109863281f,0.07662386447191238403f,-0.99729043245315551758f, +0.07356456667184829712f,-0.99751144647598266602f,0.07050457596778869629f, +-0.99772304296493530273f,0.06744392216205596924f,-0.99792528152465820312f, +0.06438262760639190674f,-0.99811810255050659180f,0.06132073700428009033f, +-0.99830156564712524414f,0.05825826525688171387f,-0.99847555160522460938f, +0.05519524589180946350f,-0.99864023923873901367f,0.05213170498609542847f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99894130229949951172f, +0.04600318148732185364f,-0.99907773733139038086f,0.04293825849890708923f, +-0.99920475482940673828f,0.03987292572855949402f,-0.99932235479354858398f, +0.03680722415447235107f,-0.99943059682846069336f,0.03374117240309715271f, +-0.99952942132949829102f,0.03067480400204658508f,-0.99961882829666137695f, +0.02760814502835273743f,-0.99969881772994995117f,0.02454122900962829590f, +-0.99976938962936401367f,0.02147408016026020050f,-0.99983060359954833984f, +0.01840673014521598816f,-0.99988234043121337891f,0.01533920597285032272f, +-0.99992471933364868164f,0.01227153837680816650f,-0.99995762109756469727f, +0.00920375436544418335f,-0.99998116493225097656f,0.00613588467240333557f, +-0.99999529123306274414f,0.00306795677170157433f,1.00000000000000000000f, +0.00000000000000000000f,0.99992471933364868164f,0.01227153837680816650f, +0.99969881772994995117f,0.02454122900962829590f,0.99932235479354858398f, +0.03680722415447235107f,0.99879544973373413086f,0.04906767606735229492f, +0.99811810255050659180f,0.06132073700428009033f,0.99729043245315551758f, +0.07356456667184829712f,0.99631261825561523438f,0.08579730987548828125f, +0.99518471956253051758f,0.09801714122295379639f,0.99390697479248046875f, +0.11022220551967620850f,0.99247956275939941406f,0.12241067737340927124f, +0.99090266227722167969f,0.13458070158958435059f,0.98917651176452636719f, +0.14673046767711639404f,0.98730140924453735352f,0.15885815024375915527f, +0.98527765274047851562f,0.17096188664436340332f,0.98310548067092895508f, +0.18303988873958587646f,0.98078525066375732422f,0.19509032368659973145f, +0.97831737995147705078f,0.20711137354373931885f,0.97570210695266723633f, +0.21910123527050018311f,0.97293996810913085938f,0.23105810582637786865f, +0.97003126144409179688f,0.24298018217086791992f,0.96697646379470825195f, +0.25486564636230468750f,0.96377605199813842773f,0.26671275496482849121f, +0.96043050289154052734f,0.27851969003677368164f,0.95694035291671752930f, +0.29028466343879699707f,0.95330601930618286133f,0.30200594663619995117f, +0.94952815771102905273f,0.31368175148963928223f,0.94560730457305908203f, +0.32531028985977172852f,0.94154405593872070312f,0.33688986301422119141f, +0.93733900785446166992f,0.34841868281364440918f,0.93299281597137451172f, +0.35989505052566528320f,0.92850607633590698242f,0.37131720781326293945f, +0.92387950420379638672f,0.38268342614173889160f,0.91911387443542480469f, +0.39399203658103942871f,0.91420978307723999023f,0.40524131059646606445f, +0.90916800498962402344f,0.41642954945564270020f,0.90398931503295898438f, +0.42755508422851562500f,0.89867448806762695312f,0.43861624598503112793f, +0.89322429895401000977f,0.44961133599281311035f,0.88763964176177978516f, +0.46053871512413024902f,0.88192129135131835938f,0.47139674425125122070f, +0.87607008218765258789f,0.48218378424644470215f,0.87008696794509887695f, +0.49289819598197937012f,0.86397284269332885742f,0.50353837013244628906f, +0.85772860050201416016f,0.51410275697708129883f,0.85135519504547119141f, +0.52458965778350830078f,0.84485357999801635742f,0.53499764204025268555f, +0.83822470903396606445f,0.54532498121261596680f,0.83146959543228149414f, +0.55557024478912353516f,0.82458931207656860352f,0.56573182344436645508f, +0.81758481264114379883f,0.57580816745758056641f,0.81045717000961303711f, +0.58579784631729125977f,0.80320751667022705078f,0.59569931030273437500f, +0.79583692550659179688f,0.60551106929779052734f,0.78834640979766845703f, +0.61523157358169555664f,0.78073722124099731445f,0.62485951185226440430f, +0.77301043272018432617f,0.63439327478408813477f,0.76516723632812500000f, +0.64383155107498168945f,0.75720882415771484375f,0.65317285060882568359f, +0.74913638830184936523f,0.66241580247879028320f,0.74095112085342407227f, +0.67155897617340087891f,0.73265427350997924805f,0.68060100078582763672f, +0.72424709796905517578f,0.68954056501388549805f,0.71573084592819213867f, +0.69837623834609985352f,0.70710676908493041992f,0.70710676908493041992f, +0.69837623834609985352f,0.71573084592819213867f,0.68954056501388549805f, +0.72424709796905517578f,0.68060100078582763672f,0.73265427350997924805f, +0.67155897617340087891f,0.74095112085342407227f,0.66241580247879028320f, +0.74913638830184936523f,0.65317285060882568359f,0.75720882415771484375f, +0.64383155107498168945f,0.76516723632812500000f,0.63439327478408813477f, +0.77301043272018432617f,0.62485951185226440430f,0.78073722124099731445f, +0.61523157358169555664f,0.78834640979766845703f,0.60551106929779052734f, +0.79583692550659179688f,0.59569931030273437500f,0.80320751667022705078f, +0.58579784631729125977f,0.81045717000961303711f,0.57580816745758056641f, +0.81758481264114379883f,0.56573182344436645508f,0.82458931207656860352f, +0.55557024478912353516f,0.83146959543228149414f,0.54532498121261596680f, +0.83822470903396606445f,0.53499764204025268555f,0.84485357999801635742f, +0.52458965778350830078f,0.85135519504547119141f,0.51410275697708129883f, +0.85772860050201416016f,0.50353837013244628906f,0.86397284269332885742f, +0.49289819598197937012f,0.87008696794509887695f,0.48218378424644470215f, +0.87607008218765258789f,0.47139674425125122070f,0.88192129135131835938f, +0.46053871512413024902f,0.88763964176177978516f,0.44961133599281311035f, +0.89322429895401000977f,0.43861624598503112793f,0.89867448806762695312f, +0.42755508422851562500f,0.90398931503295898438f,0.41642954945564270020f, +0.90916800498962402344f,0.40524131059646606445f,0.91420978307723999023f, +0.39399203658103942871f,0.91911387443542480469f,0.38268342614173889160f, +0.92387950420379638672f,0.37131720781326293945f,0.92850607633590698242f, +0.35989505052566528320f,0.93299281597137451172f,0.34841868281364440918f, +0.93733900785446166992f,0.33688986301422119141f,0.94154405593872070312f, +0.32531028985977172852f,0.94560730457305908203f,0.31368175148963928223f, +0.94952815771102905273f,0.30200594663619995117f,0.95330601930618286133f, +0.29028466343879699707f,0.95694035291671752930f,0.27851969003677368164f, +0.96043050289154052734f,0.26671275496482849121f,0.96377605199813842773f, +0.25486564636230468750f,0.96697646379470825195f,0.24298018217086791992f, +0.97003126144409179688f,0.23105810582637786865f,0.97293996810913085938f, +0.21910123527050018311f,0.97570210695266723633f,0.20711137354373931885f, +0.97831737995147705078f,0.19509032368659973145f,0.98078525066375732422f, +0.18303988873958587646f,0.98310548067092895508f,0.17096188664436340332f, +0.98527765274047851562f,0.15885815024375915527f,0.98730140924453735352f, +0.14673046767711639404f,0.98917651176452636719f,0.13458070158958435059f, +0.99090266227722167969f,0.12241067737340927124f,0.99247956275939941406f, +0.11022220551967620850f,0.99390697479248046875f,0.09801714122295379639f, +0.99518471956253051758f,0.08579730987548828125f,0.99631261825561523438f, +0.07356456667184829712f,0.99729043245315551758f,0.06132073700428009033f, +0.99811810255050659180f,0.04906767606735229492f,0.99879544973373413086f, +0.03680722415447235107f,0.99932235479354858398f,0.02454122900962829590f, +0.99969881772994995117f,0.01227153837680816650f,0.99992471933364868164f, +0.00000000000000006123f,1.00000000000000000000f,-0.01227153837680816650f, +0.99992471933364868164f,-0.02454122900962829590f,0.99969881772994995117f, +-0.03680722415447235107f,0.99932235479354858398f,-0.04906767606735229492f, +0.99879544973373413086f,-0.06132073700428009033f,0.99811810255050659180f, +-0.07356456667184829712f,0.99729043245315551758f,-0.08579730987548828125f, +0.99631261825561523438f,-0.09801714122295379639f,0.99518471956253051758f, +-0.11022220551967620850f,0.99390697479248046875f,-0.12241067737340927124f, +0.99247956275939941406f,-0.13458070158958435059f,0.99090266227722167969f, +-0.14673046767711639404f,0.98917651176452636719f,-0.15885815024375915527f, +0.98730140924453735352f,-0.17096188664436340332f,0.98527765274047851562f, +-0.18303988873958587646f,0.98310548067092895508f,-0.19509032368659973145f, +0.98078525066375732422f,-0.20711137354373931885f,0.97831737995147705078f, +-0.21910123527050018311f,0.97570210695266723633f,-0.23105810582637786865f, +0.97293996810913085938f,-0.24298018217086791992f,0.97003126144409179688f, +-0.25486564636230468750f,0.96697646379470825195f,-0.26671275496482849121f, +0.96377605199813842773f,-0.27851969003677368164f,0.96043050289154052734f, +-0.29028466343879699707f,0.95694035291671752930f,-0.30200594663619995117f, +0.95330601930618286133f,-0.31368175148963928223f,0.94952815771102905273f, +-0.32531028985977172852f,0.94560730457305908203f,-0.33688986301422119141f, +0.94154405593872070312f,-0.34841868281364440918f,0.93733900785446166992f, +-0.35989505052566528320f,0.93299281597137451172f,-0.37131720781326293945f, +0.92850607633590698242f,-0.38268342614173889160f,0.92387950420379638672f, +-0.39399203658103942871f,0.91911387443542480469f,-0.40524131059646606445f, +0.91420978307723999023f,-0.41642954945564270020f,0.90916800498962402344f, +-0.42755508422851562500f,0.90398931503295898438f,-0.43861624598503112793f, +0.89867448806762695312f,-0.44961133599281311035f,0.89322429895401000977f, +-0.46053871512413024902f,0.88763964176177978516f,-0.47139674425125122070f, +0.88192129135131835938f,-0.48218378424644470215f,0.87607008218765258789f, +-0.49289819598197937012f,0.87008696794509887695f,-0.50353837013244628906f, +0.86397284269332885742f,-0.51410275697708129883f,0.85772860050201416016f, +-0.52458965778350830078f,0.85135519504547119141f,-0.53499764204025268555f, +0.84485357999801635742f,-0.54532498121261596680f,0.83822470903396606445f, +-0.55557024478912353516f,0.83146959543228149414f,-0.56573182344436645508f, +0.82458931207656860352f,-0.57580816745758056641f,0.81758481264114379883f, +-0.58579784631729125977f,0.81045717000961303711f,-0.59569931030273437500f, +0.80320751667022705078f,-0.60551106929779052734f,0.79583692550659179688f, +-0.61523157358169555664f,0.78834640979766845703f,-0.62485951185226440430f, +0.78073722124099731445f,-0.63439327478408813477f,0.77301043272018432617f, +-0.64383155107498168945f,0.76516723632812500000f,-0.65317285060882568359f, +0.75720882415771484375f,-0.66241580247879028320f,0.74913638830184936523f, +-0.67155897617340087891f,0.74095112085342407227f,-0.68060100078582763672f, +0.73265427350997924805f,-0.68954056501388549805f,0.72424709796905517578f, +-0.69837623834609985352f,0.71573084592819213867f,-0.70710676908493041992f, +0.70710676908493041992f,-0.71573084592819213867f,0.69837623834609985352f, +-0.72424709796905517578f,0.68954056501388549805f,-0.73265427350997924805f, +0.68060100078582763672f,-0.74095112085342407227f,0.67155897617340087891f, +-0.74913638830184936523f,0.66241580247879028320f,-0.75720882415771484375f, +0.65317285060882568359f,-0.76516723632812500000f,0.64383155107498168945f, +-0.77301043272018432617f,0.63439327478408813477f,-0.78073722124099731445f, +0.62485951185226440430f,-0.78834640979766845703f,0.61523157358169555664f, +-0.79583692550659179688f,0.60551106929779052734f,-0.80320751667022705078f, +0.59569931030273437500f,-0.81045717000961303711f,0.58579784631729125977f, +-0.81758481264114379883f,0.57580816745758056641f,-0.82458931207656860352f, +0.56573182344436645508f,-0.83146959543228149414f,0.55557024478912353516f, +-0.83822470903396606445f,0.54532498121261596680f,-0.84485357999801635742f, +0.53499764204025268555f,-0.85135519504547119141f,0.52458965778350830078f, +-0.85772860050201416016f,0.51410275697708129883f,-0.86397284269332885742f, +0.50353837013244628906f,-0.87008696794509887695f,0.49289819598197937012f, +-0.87607008218765258789f,0.48218378424644470215f,-0.88192129135131835938f, +0.47139674425125122070f,-0.88763964176177978516f,0.46053871512413024902f, +-0.89322429895401000977f,0.44961133599281311035f,-0.89867448806762695312f, +0.43861624598503112793f,-0.90398931503295898438f,0.42755508422851562500f, +-0.90916800498962402344f,0.41642954945564270020f,-0.91420978307723999023f, +0.40524131059646606445f,-0.91911387443542480469f,0.39399203658103942871f, +-0.92387950420379638672f,0.38268342614173889160f,-0.92850607633590698242f, +0.37131720781326293945f,-0.93299281597137451172f,0.35989505052566528320f, +-0.93733900785446166992f,0.34841868281364440918f,-0.94154405593872070312f, +0.33688986301422119141f,-0.94560730457305908203f,0.32531028985977172852f, +-0.94952815771102905273f,0.31368175148963928223f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95694035291671752930f,0.29028466343879699707f, +-0.96043050289154052734f,0.27851969003677368164f,-0.96377605199813842773f, +0.26671275496482849121f,-0.96697646379470825195f,0.25486564636230468750f, +-0.97003126144409179688f,0.24298018217086791992f,-0.97293996810913085938f, +0.23105810582637786865f,-0.97570210695266723633f,0.21910123527050018311f, +-0.97831737995147705078f,0.20711137354373931885f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98310548067092895508f,0.18303988873958587646f, +-0.98527765274047851562f,0.17096188664436340332f,-0.98730140924453735352f, +0.15885815024375915527f,-0.98917651176452636719f,0.14673046767711639404f, +-0.99090266227722167969f,0.13458070158958435059f,-0.99247956275939941406f, +0.12241067737340927124f,-0.99390697479248046875f,0.11022220551967620850f, +-0.99518471956253051758f,0.09801714122295379639f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99729043245315551758f,0.07356456667184829712f, +-0.99811810255050659180f,0.06132073700428009033f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99932235479354858398f,0.03680722415447235107f, +-0.99969881772994995117f,0.02454122900962829590f,-0.99992471933364868164f, +0.01227153837680816650f,1.00000000000000000000f,0.00000000000000000000f, +0.99879544973373413086f,0.04906767606735229492f,0.99518471956253051758f, +0.09801714122295379639f,0.98917651176452636719f,0.14673046767711639404f, +0.98078525066375732422f,0.19509032368659973145f,0.97003126144409179688f, +0.24298018217086791992f,0.95694035291671752930f,0.29028466343879699707f, +0.94154405593872070312f,0.33688986301422119141f,0.92387950420379638672f, +0.38268342614173889160f,0.90398931503295898438f,0.42755508422851562500f, +0.88192129135131835938f,0.47139674425125122070f,0.85772860050201416016f, +0.51410275697708129883f,0.83146959543228149414f,0.55557024478912353516f, +0.80320751667022705078f,0.59569931030273437500f,0.77301043272018432617f, +0.63439327478408813477f,0.74095112085342407227f,0.67155897617340087891f, +0.70710676908493041992f,0.70710676908493041992f,0.67155897617340087891f, +0.74095112085342407227f,0.63439327478408813477f,0.77301043272018432617f, +0.59569931030273437500f,0.80320751667022705078f,0.55557024478912353516f, +0.83146959543228149414f,0.51410275697708129883f,0.85772860050201416016f, +0.47139674425125122070f,0.88192129135131835938f,0.42755508422851562500f, +0.90398931503295898438f,0.38268342614173889160f,0.92387950420379638672f, +0.33688986301422119141f,0.94154405593872070312f,0.29028466343879699707f, +0.95694035291671752930f,0.24298018217086791992f,0.97003126144409179688f, +0.19509032368659973145f,0.98078525066375732422f,0.14673046767711639404f, +0.98917651176452636719f,0.09801714122295379639f,0.99518471956253051758f, +0.04906767606735229492f,0.99879544973373413086f,0.00000000000000006123f, +1.00000000000000000000f,-0.04906767606735229492f,0.99879544973373413086f, +-0.09801714122295379639f,0.99518471956253051758f,-0.14673046767711639404f, +0.98917651176452636719f,-0.19509032368659973145f,0.98078525066375732422f, +-0.24298018217086791992f,0.97003126144409179688f,-0.29028466343879699707f, +0.95694035291671752930f,-0.33688986301422119141f,0.94154405593872070312f, +-0.38268342614173889160f,0.92387950420379638672f,-0.42755508422851562500f, +0.90398931503295898438f,-0.47139674425125122070f,0.88192129135131835938f, +-0.51410275697708129883f,0.85772860050201416016f,-0.55557024478912353516f, +0.83146959543228149414f,-0.59569931030273437500f,0.80320751667022705078f, +-0.63439327478408813477f,0.77301043272018432617f,-0.67155897617340087891f, +0.74095112085342407227f,-0.70710676908493041992f,0.70710676908493041992f, +-0.74095112085342407227f,0.67155897617340087891f,-0.77301043272018432617f, +0.63439327478408813477f,-0.80320751667022705078f,0.59569931030273437500f, +-0.83146959543228149414f,0.55557024478912353516f,-0.85772860050201416016f, +0.51410275697708129883f,-0.88192129135131835938f,0.47139674425125122070f, +-0.90398931503295898438f,0.42755508422851562500f,-0.92387950420379638672f, +0.38268342614173889160f,-0.94154405593872070312f,0.33688986301422119141f, +-0.95694035291671752930f,0.29028466343879699707f,-0.97003126144409179688f, +0.24298018217086791992f,-0.98078525066375732422f,0.19509032368659973145f, +-0.98917651176452636719f,0.14673046767711639404f,-0.99518471956253051758f, +0.09801714122295379639f,-0.99879544973373413086f,0.04906767606735229492f, +1.00000000000000000000f,0.00000000000000000000f,0.98078525066375732422f, +0.19509032368659973145f,0.92387950420379638672f,0.38268342614173889160f, +0.83146959543228149414f,0.55557024478912353516f,0.70710676908493041992f, +0.70710676908493041992f,0.55557024478912353516f,0.83146959543228149414f, +0.38268342614173889160f,0.92387950420379638672f,0.19509032368659973145f, +0.98078525066375732422f,0.00000000000000006123f,1.00000000000000000000f, +-0.19509032368659973145f,0.98078525066375732422f,-0.38268342614173889160f, +0.92387950420379638672f,-0.55557024478912353516f,0.83146959543228149414f, +-0.70710676908493041992f,0.70710676908493041992f,-0.83146959543228149414f, +0.55557024478912353516f,-0.92387950420379638672f,0.38268342614173889160f, +-0.98078525066375732422f,0.19509032368659973145f,1.00000000000000000000f, +0.00000000000000000000f,0.70710676908493041992f,0.70710676908493041992f, +0.00000000000000006123f,1.00000000000000000000f,-0.70710676908493041992f, +0.70710676908493041992f,}; + +float32_t rearranged_twiddle_stride3_4096_f32[2728]={ +1.00000000000000000000f,0.00000000000000000000f,0.99998939037322998047f, +0.00460192607715725899f,0.99995762109756469727f,0.00920375436544418335f, +0.99990469217300415039f,0.01380538847297430038f,0.99983060359954833984f, +0.01840673014521598816f,0.99973529577255249023f,0.02300768159329891205f, +0.99961882829666137695f,0.02760814502835273743f,0.99948120117187500000f, +0.03220802545547485352f,0.99932235479354858398f,0.03680722415447235107f, +0.99914240837097167969f,0.04140564054250717163f,0.99894130229949951172f, +0.04600318148732185364f,0.99871903657913208008f,0.05059975013136863708f, +0.99847555160522460938f,0.05519524589180946350f,0.99821102619171142578f, +0.05978957191109657288f,0.99792528152465820312f,0.06438262760639190674f, +0.99761843681335449219f,0.06897433102130889893f,0.99729043245315551758f, +0.07356456667184829712f,0.99694132804870605469f,0.07815324515104293823f, +0.99657112360000610352f,0.08274026215076446533f,0.99617981910705566406f, +0.08732553571462631226f,0.99576741456985473633f,0.09190895408391952515f, +0.99533390998840332031f,0.09649042785167694092f,0.99487930536270141602f, +0.10106986016035079956f,0.99440366029739379883f,0.10564715415239334106f, +0.99390697479248046875f,0.11022220551967620850f,0.99338918924331665039f, +0.11479492485523223877f,0.99285042285919189453f,0.11936521530151367188f, +0.99229061603546142578f,0.12393297255039215088f,0.99170976877212524414f, +0.12849810719490051270f,0.99110794067382812500f,0.13306052982807159424f, +0.99048507213592529297f,0.13762012124061584473f,0.98984128236770629883f, +0.14217680692672729492f,0.98917651176452636719f,0.14673046767711639404f, +0.98849081993103027344f,0.15128104388713836670f,0.98778414726257324219f, +0.15582840144634246826f,0.98705655336380004883f,0.16037245094776153564f, +0.98630809783935546875f,0.16491311788558959961f,0.98553872108459472656f, +0.16945029795169830322f,0.98474848270416259766f,0.17398387193679809570f, +0.98393744230270385742f,0.17851376533508300781f,0.98310548067092895508f, +0.18303988873958587646f,0.98225271701812744141f,0.18756212294101715088f, +0.98137921094894409180f,0.19208039343357086182f,0.98048484325408935547f, +0.19659459590911865234f,0.97956979274749755859f,0.20110464096069335938f, +0.97863394021987915039f,0.20561040937900543213f,0.97767734527587890625f, +0.21011184155941009521f,0.97670006752014160156f,0.21460881829261779785f, +0.97570210695266723633f,0.21910123527050018311f,0.97468352317810058594f, +0.22358903288841247559f,0.97364425659179687500f,0.22807207703590393066f, +0.97258436679840087891f,0.23255030810832977295f,0.97150391340255737305f, +0.23702360689640045166f,0.97040283679962158203f,0.24149188399314880371f, +0.96928125619888305664f,0.24595504999160766602f,0.96813911199569702148f, +0.25041300058364868164f,0.96697646379470825195f,0.25486564636230468750f, +0.96579337120056152344f,0.25931292772293090820f,0.96458977460861206055f, +0.26375466585159301758f,0.96336579322814941406f,0.26819086074829101562f, +0.96212142705917358398f,0.27262136340141296387f,0.96085661649703979492f, +0.27704608440399169922f,0.95957154035568237305f,0.28146493434906005859f, +0.95826607942581176758f,0.28587782382965087891f,0.95694035291671752930f, +0.29028466343879699707f,0.95559436082839965820f,0.29468536376953125000f, +0.95422810316085815430f,0.29907983541488647461f,0.95284163951873779297f, +0.30346795916557312012f,0.95143502950668334961f,0.30784964561462402344f, +0.95000827312469482422f,0.31222480535507202148f,0.94856137037277221680f, +0.31659337878227233887f,0.94709438085556030273f,0.32095524668693542480f, +0.94560730457305908203f,0.32531028985977172852f,0.94410026073455810547f, +0.32965844869613647461f,0.94257318973541259766f,0.33399966359138488770f, +0.94102615118026733398f,0.33833375573158264160f,0.93945920467376708984f, +0.34266072511672973633f,0.93787235021591186523f,0.34698042273521423340f, +0.93626564741134643555f,0.35129275918006896973f,0.93463915586471557617f, +0.35559767484664916992f,0.93299281597137451172f,0.35989505052566528320f, +0.93132668733596801758f,0.36418479681015014648f,0.92964088916778564453f, +0.36846682429313659668f,0.92793542146682739258f,0.37274107336997985840f, +0.92621022462844848633f,0.37700742483139038086f,0.92446547746658325195f, +0.38126575946807861328f,0.92270112037658691406f,0.38551604747772216797f, +0.92091721296310424805f,0.38975816965103149414f,0.91911387443542480469f, +0.39399203658103942871f,0.91729098558425903320f,0.39821755886077880859f, +0.91544872522354125977f,0.40243464708328247070f,0.91358703374862670898f, +0.40664321184158325195f,0.91170603036880493164f,0.41084316372871398926f, +0.90980571508407592773f,0.41503441333770751953f,0.90788608789443969727f, +0.41921690106391906738f,0.90594726800918579102f,0.42339047789573669434f, +0.90398931503295898438f,0.42755508422851562500f,0.90201216936111450195f, +0.43171066045761108398f,0.90001589059829711914f,0.43585708737373352051f, +0.89800059795379638672f,0.43999427556991577148f,0.89596623182296752930f, +0.44412213563919067383f,0.89391297101974487305f,0.44824060797691345215f, +0.89184069633483886719f,0.45234957337379455566f,0.88974958658218383789f, +0.45644897222518920898f,0.88763964176177978516f,0.46053871512413024902f, +0.88551086187362670898f,0.46461868286132812500f,0.88336336612701416016f, +0.46868881583213806152f,0.88119709491729736328f,0.47274902462959289551f, +0.87901222705841064453f,0.47679921984672546387f,0.87680870294570922852f, +0.48083934187889099121f,0.87458664178848266602f,0.48486924171447753906f, +0.87234604358673095703f,0.48888888955116271973f,0.87008696794509887695f, +0.49289819598197937012f,0.86780947446823120117f,0.49689704179763793945f, +0.86551362276077270508f,0.50088536739349365234f,0.86319941282272338867f, +0.50486308336257934570f,0.86086696386337280273f,0.50883013010025024414f, +0.85851621627807617188f,0.51278638839721679688f,0.85614734888076782227f, +0.51673179864883422852f,0.85376030206680297852f,0.52066624164581298828f, +0.85135519504547119141f,0.52458965778350830078f,0.84893202781677246094f, +0.52850198745727539062f,0.84649091958999633789f,0.53240311145782470703f, +0.84403187036514282227f,0.53629297018051147461f,0.84155499935150146484f, +0.54017144441604614258f,0.83906024694442749023f,0.54403853416442871094f, +0.83654773235321044922f,0.54789406061172485352f,0.83401751518249511719f, +0.55173796415328979492f,0.83146959543228149414f,0.55557024478912353516f, +0.82890409231185913086f,0.55939072370529174805f,0.82632106542587280273f, +0.56319934129714965820f,0.82372051477432250977f,0.56699603796005249023f, +0.82110249996185302734f,0.57078075408935546875f,0.81846714019775390625f, +0.57455337047576904297f,0.81581443548202514648f,0.57831376791000366211f, +0.81314438581466674805f,0.58206200599670410156f,0.81045717000961303711f, +0.58579784631729125977f,0.80775284767150878906f,0.58952128887176513672f, +0.80503135919570922852f,0.59323227405548095703f,0.80229282379150390625f, +0.59693068265914916992f,0.79953724145889282227f,0.60061645507812500000f, +0.79676479101181030273f,0.60428953170776367188f,0.79397547245025634766f, +0.60794979333877563477f,0.79116934537887573242f,0.61159718036651611328f, +0.78834640979766845703f,0.61523157358169555664f,0.78550684452056884766f, +0.61885297298431396484f,0.78265058994293212891f,0.62246125936508178711f, +0.77977776527404785156f,0.62605637311935424805f,0.77688848972320556641f, +0.62963825464248657227f,0.77398270368576049805f,0.63320678472518920898f, +0.77106052637100219727f,0.63676184415817260742f,0.76812201738357543945f, +0.64030349254608154297f,0.76516723632812500000f,0.64383155107498168945f, +0.76219630241394042969f,0.64734596014022827148f,0.75920921564102172852f, +0.65084666013717651367f,0.75620597600936889648f,0.65433359146118164062f, +0.75318682193756103516f,0.65780669450759887695f,0.75015163421630859375f, +0.66126585006713867188f,0.74710059165954589844f,0.66471099853515625000f, +0.74403375387191772461f,0.66814202070236206055f,0.74095112085342407227f, +0.67155897617340087891f,0.73785281181335449219f,0.67496162652969360352f, +0.73473888635635375977f,0.67835003137588500977f,0.73160940408706665039f, +0.68172407150268554688f,0.72846436500549316406f,0.68508368730545043945f, +0.72530394792556762695f,0.68842875957489013672f,0.72212821245193481445f, +0.69175922870635986328f,0.71893709897994995117f,0.69507509469985961914f, +0.71573084592819213867f,0.69837623834609985352f,0.71250939369201660156f, +0.70166260004043579102f,0.70927280187606811523f,0.70493406057357788086f, +0.70602124929428100586f,0.70819061994552612305f,0.70275473594665527344f, +0.71143221855163574219f,0.69947332143783569336f,0.71465867757797241211f, +0.69617712497711181641f,0.71787005662918090820f,0.69286614656448364258f, +0.72106617689132690430f,0.68954056501388549805f,0.72424709796905517578f, +0.68620032072067260742f,0.72741264104843139648f,0.68284553289413452148f, +0.73056274652481079102f,0.67947632074356079102f,0.73369741439819335938f, +0.67609268426895141602f,0.73681658506393432617f,0.67269474267959594727f, +0.73992007970809936523f,0.66928261518478393555f,0.74300795793533325195f, +0.66585624217987060547f,0.74608010053634643555f,0.66241580247879028320f, +0.74913638830184936523f,0.65896129608154296875f,0.75217682123184204102f, +0.65549284219741821289f,0.75520139932632446289f,0.65201056003570556641f, +0.75820988416671752930f,0.64851438999176025391f,0.76120239496231079102f, +0.64500451087951660156f,0.76417875289916992188f,0.64148104190826416016f, +0.76713889837265014648f,0.63794392347335815430f,0.77008283138275146484f, +0.63439327478408813477f,0.77301043272018432617f,0.63082921504974365234f, +0.77592170238494873047f,0.62725180387496948242f,0.77881652116775512695f, +0.62366110086441040039f,0.78169482946395874023f,0.62005722522735595703f, +0.78455656766891479492f,0.61644017696380615234f,0.78740173578262329102f, +0.61281007528305053711f,0.79023021459579467773f,0.60916703939437866211f, +0.79304194450378417969f,0.60551106929779052734f,0.79583692550659179688f, +0.60184222459793090820f,0.79861497879028320312f,0.59816068410873413086f, +0.80137616395950317383f,0.59446650743484497070f,0.80412036180496215820f, +0.59075969457626342773f,0.80684757232666015625f,0.58704036474227905273f, +0.80955761671066284180f,0.58330863714218139648f,0.81225061416625976562f, +0.57956457138061523438f,0.81492632627487182617f,0.57580816745758056641f, +0.81758481264114379883f,0.57203960418701171875f,0.82022595405578613281f, +0.56825894117355346680f,0.82284981012344360352f,0.56446623802185058594f, +0.82545614242553710938f,0.56066155433654785156f,0.82804507017135620117f, +0.55684500932693481445f,0.83061641454696655273f,0.55301672220230102539f, +0.83317017555236816406f,0.54917663335800170898f,0.83570629358291625977f, +0.54532498121261596680f,0.83822470903396606445f,0.54146176576614379883f, +0.84072536230087280273f,0.53758704662322998047f,0.84320825338363647461f, +0.53370100259780883789f,0.84567326307296752930f,0.52980363368988037109f, +0.84812033176422119141f,0.52589499950408935547f,0.85054945945739746094f, +0.52197527885437011719f,0.85296058654785156250f,0.51804453134536743164f, +0.85535365343093872070f,0.51410275697708129883f,0.85772860050201416016f, +0.51015007495880126953f,0.86008536815643310547f,0.50618666410446166992f, +0.86242395639419555664f,0.50221246480941772461f,0.86474424600601196289f, +0.49822765588760375977f,0.86704623699188232422f,0.49423229694366455078f, +0.86932986974716186523f,0.49022647738456726074f,0.87159508466720581055f, +0.48621028661727905273f,0.87384182214736938477f,0.48218378424644470215f, +0.87607008218765258789f,0.47814705967903137207f,0.87827980518341064453f, +0.47410020232200622559f,0.88047087192535400391f,0.47004333138465881348f, +0.88264334201812744141f,0.46597650647163391113f,0.88479709625244140625f, +0.46189978718757629395f,0.88693213462829589844f,0.45781329274177551270f, +0.88904833793640136719f,0.45371711254119873047f,0.89114576578140258789f, +0.44961133599281311035f,0.89322429895401000977f,0.44549602270126342773f, +0.89528393745422363281f,0.44137126207351684570f,0.89732456207275390625f, +0.43723717331886291504f,0.89934623241424560547f,0.43309381604194641113f, +0.90134882926940917969f,0.42894127964973449707f,0.90333235263824462891f, +0.42477968335151672363f,0.90529674291610717773f,0.42060908675193786621f, +0.90724200010299682617f,0.41642954945564270020f,0.90916800498962402344f, +0.41224122047424316406f,0.91107475757598876953f,0.40804415941238403320f, +0.91296219825744628906f,0.40383845567703247070f,0.91483032703399658203f, +0.39962419867515563965f,0.91667908430099487305f,0.39540147781372070312f, +0.91850841045379638672f,0.39117038249969482422f,0.92031830549240112305f, +0.38693100214004516602f,0.92210865020751953125f,0.38268342614173889160f, +0.92387950420379638672f,0.37842774391174316406f,0.92563080787658691406f, +0.37416407465934753418f,0.92736250162124633789f,0.36989244818687438965f, +0.92907458543777465820f,0.36561298370361328125f,0.93076694011688232422f, +0.36132580041885375977f,0.93243962526321411133f,0.35703095793724060059f, +0.93409252166748046875f,0.35272854566574096680f,0.93572568893432617188f, +0.34841868281364440918f,0.93733900785446166992f,0.34410142898559570312f, +0.93893247842788696289f,0.33977687358856201172f,0.94050604104995727539f, +0.33544513583183288574f,0.94205975532531738281f,0.33110630512237548828f, +0.94359344244003295898f,0.32676044106483459473f,0.94510722160339355469f, +0.32240769267082214355f,0.94660091400146484375f,0.31804808974266052246f, +0.94807457923889160156f,0.31368175148963928223f,0.94952815771102905273f, +0.30930876731872558594f,0.95096164941787719727f,0.30492922663688659668f, +0.95237499475479125977f,0.30054324865341186523f,0.95376819372177124023f, +0.29615089297294616699f,0.95514118671417236328f,0.29175224900245666504f, +0.95649391412734985352f,0.28734746575355529785f,0.95782643556594848633f, +0.28293657302856445312f,0.95913863182067871094f,0.27851969003677368164f, +0.96043050289154052734f,0.27409690618515014648f,0.96170204877853393555f, +0.26966831088066101074f,0.96295326948165893555f,0.26523402333259582520f, +0.96418404579162597656f,0.26079410314559936523f,0.96539443731307983398f, +0.25634866952896118164f,0.96658438444137573242f,0.25189781188964843750f, +0.96775382757186889648f,0.24744161963462829590f,0.96890282630920410156f, +0.24298018217086791992f,0.97003126144409179688f,0.23851358890533447266f, +0.97113913297653198242f,0.23404195904731750488f,0.97222650051116943359f, +0.22956536710262298584f,0.97329324483871459961f,0.22508391737937927246f, +0.97433936595916748047f,0.22059768438339233398f,0.97536486387252807617f, +0.21610680222511291504f,0.97636973857879638672f,0.21161133050918579102f, +0.97735387086868286133f,0.20711137354373931885f,0.97831737995147705078f, +0.20260703563690185547f,0.97926014661788940430f,0.19809840619564056396f, +0.98018211126327514648f,0.19358558952808380127f,0.98108339309692382812f, +0.18906866014003753662f,0.98196387290954589844f,0.18454773724079132080f, +0.98282355070114135742f,0.18002289533615112305f,0.98366242647171020508f, +0.17549425363540649414f,0.98448044061660766602f,0.17096188664436340332f, +0.98527765274047851562f,0.16642589867115020752f,0.98605394363403320312f, +0.16188639402389526367f,0.98680937290191650391f,0.15734346210956573486f, +0.98754394054412841797f,0.15279719233512878418f,0.98825758695602416992f, +0.14824767410755157471f,0.98895025253295898438f,0.14369502663612365723f, +0.98962199687957763672f,0.13913933932781219482f,0.99027281999588012695f, +0.13458070158958435059f,0.99090266227722167969f,0.13001921772956848145f, +0.99151146411895751953f,0.12545497715473175049f,0.99209928512573242188f, +0.12088808417320251465f,0.99266612529754638672f,0.11631862819194793701f, +0.99321192502975463867f,0.11174671351909637451f,0.99373674392700195312f, +0.10717242211103439331f,0.99424046277999877930f,0.10259586572647094727f, +0.99472314119338989258f,0.09801714122295379639f,0.99518471956253051758f, +0.09343633800745010376f,0.99562525749206542969f,0.08885355293750762939f, +0.99604469537734985352f,0.08426889032125473022f,0.99644303321838378906f, +0.07968243956565856934f,0.99682027101516723633f,0.07509429752826690674f, +0.99717640876770019531f,0.07050457596778869629f,0.99751144647598266602f, +0.06591334939002990723f,0.99782532453536987305f,0.06132073700428009033f, +0.99811810255050659180f,0.05672682076692581177f,0.99838972091674804688f, +0.05213170498609542847f,0.99864023923873901367f,0.04753548279404640198f, +0.99886953830718994141f,0.04293825849890708923f,0.99907773733139038086f, +0.03834012150764465332f,0.99926477670669555664f,0.03374117240309715271f, +0.99943059682846069336f,0.02914150804281234741f,0.99957531690597534180f, +0.02454122900962829590f,0.99969881772994995117f,0.01994042843580245972f, +0.99980115890502929688f,0.01533920597285032272f,0.99988234043121337891f, +0.01073765940964221954f,0.99994236230850219727f,0.00613588467240333557f, +0.99998116493225097656f,0.00153398013208061457f,0.99999880790710449219f, +-0.00306795677170157433f,0.99999529123306274414f,-0.00766982883214950562f, +0.99997061491012573242f,-0.01227153837680816650f,0.99992471933364868164f, +-0.01687298715114593506f,0.99985766410827636719f,-0.02147408016026020050f, +0.99976938962936401367f,-0.02607471868395805359f,0.99966001510620117188f, +-0.03067480400204658508f,0.99952942132949829102f,-0.03527423739433288574f, +0.99937766790390014648f,-0.03987292572855949402f,0.99920475482940673828f, +-0.04447077214717864990f,0.99901068210601806641f,-0.04906767606735229492f, +0.99879544973373413086f,-0.05366353690624237061f,0.99855905771255493164f, +-0.05825826525688171387f,0.99830156564712524414f,-0.06285175681114196777f, +0.99802285432815551758f,-0.06744392216205596924f,0.99772304296493530273f, +-0.07203464955091476440f,0.99740213155746459961f,-0.07662386447191238403f, +0.99706006050109863281f,-0.08121144771575927734f,0.99669688940048217773f, +-0.08579730987548828125f,0.99631261825561523438f,-0.09038136154413223267f, +0.99590724706649780273f,-0.09496349841356277466f,0.99548077583312988281f, +-0.09954361617565155029f,0.99503320455551147461f,-0.10412163287401199341f, +0.99456459283828735352f,-0.10869744420051574707f,0.99407488107681274414f, +-0.11327095329761505127f,0.99356412887573242188f,-0.11784206330776214600f, +0.99303233623504638672f,-0.12241067737340927124f,0.99247956275939941406f, +-0.12697669863700866699f,0.99190568923950195312f,-0.13154003024101257324f, +0.99131083488464355469f,-0.13610057532787322998f,0.99069499969482421875f, +-0.14065824449062347412f,0.99005818367004394531f,-0.14521291851997375488f, +0.98940044641494750977f,-0.14976453781127929688f,0.98872166872024536133f, +-0.15431296825408935547f,0.98802202939987182617f,-0.15885815024375915527f, +0.98730140924453735352f,-0.16339994966983795166f,0.98655992746353149414f, +-0.16793829202651977539f,0.98579752445220947266f,-0.17247308790683746338f, +0.98501425981521606445f,-0.17700421810150146484f,0.98421007394790649414f, +-0.18153160810470581055f,0.98338508605957031250f,-0.18605515360832214355f, +0.98253929615020751953f,-0.19057475030422210693f,0.98167270421981811523f, +-0.19509032368659973145f,0.98078525066375732422f,-0.19960175454616546631f, +0.97987711429595947266f,-0.20410896837711334229f,0.97894817590713500977f, +-0.20861184597015380859f,0.97799849510192871094f,-0.21311031281948089600f, +0.97702813148498535156f,-0.21760427951812744141f,0.97603708505630493164f, +-0.22209362685680389404f,0.97502535581588745117f,-0.22657826542854309082f, +0.97399294376373291016f,-0.23105810582637786865f,0.97293996810913085938f, +-0.23553305864334106445f,0.97186630964279174805f,-0.24000301957130432129f, +0.97077214717864990234f,-0.24446789920330047607f,0.96965736150741577148f, +-0.24892760813236236572f,0.96852207183837890625f,-0.25338202714920043945f, +0.96736627817153930664f,-0.25783109664916992188f,0.96618998050689697266f, +-0.26227471232414245605f,0.96499323844909667969f,-0.26671275496482849121f, +0.96377605199813842773f,-0.27114516496658325195f,0.96253848075866699219f, +-0.27557182312011718750f,0.96128046512603759766f,-0.27999264001846313477f, +0.96000212430953979492f,-0.28440752625465393066f,0.95870345830917358398f, +-0.28881642222404479980f,0.95738452672958374023f,-0.29321914911270141602f, +0.95604526996612548828f,-0.29761570692062377930f,0.95468574762344360352f, +-0.30200594663619995117f,0.95330601930618286133f,-0.30638980865478515625f, +0.95190614461898803711f,-0.31076714396476745605f,0.95048606395721435547f, +-0.31513792276382446289f,0.94904589653015136719f,-0.31950202584266662598f, +0.94758558273315429688f,-0.32385936379432678223f,0.94610524177551269531f, +-0.32820984721183776855f,0.94460481405258178711f,-0.33255335688591003418f, +0.94308441877365112305f,-0.33688986301422119141f,0.94154405593872070312f, +-0.34121921658515930176f,0.93998372554779052734f,-0.34554132819175720215f, +0.93840354681015014648f,-0.34985613822937011719f,0.93680346012115478516f, +-0.35416352748870849609f,0.93518352508544921875f,-0.35846340656280517578f, +0.93354380130767822266f,-0.36275571584701538086f,0.93188428878784179688f, +-0.36704033613204956055f,0.93020504713058471680f,-0.37131720781326293945f, +0.92850607633590698242f,-0.37558618187904357910f,0.92678749561309814453f, +-0.37984719872474670410f,0.92504924535751342773f,-0.38410019874572753906f, +0.92329144477844238281f,-0.38834503293037414551f,0.92151403427124023438f, +-0.39258167147636413574f,0.91971713304519653320f,-0.39680999517440795898f, +0.91790080070495605469f,-0.40102988481521606445f,0.91606497764587402344f, +-0.40524131059646606445f,0.91420978307723999023f,-0.40944415330886840820f, +0.91233515739440917969f,-0.41363832354545593262f,0.91044127941131591797f, +-0.41782370209693908691f,0.90852808952331542969f,-0.42200025916099548340f, +0.90659570693969726562f,-0.42616787552833557129f,0.90464407205581665039f, +-0.43032649159431457520f,0.90267330408096313477f,-0.43447595834732055664f, +0.90068340301513671875f,-0.43861624598503112793f,0.89867448806762695312f, +-0.44274723529815673828f,0.89664649963378906250f,-0.44686883687973022461f, +0.89459949731826782227f,-0.45098099112510681152f,0.89253354072570800781f, +-0.45508357882499694824f,0.89044874906539916992f,-0.45917654037475585938f, +0.88834506273269653320f,-0.46325978636741638184f,0.88622254133224487305f, +-0.46733319759368896484f,0.88408124446868896484f,-0.47139674425125122070f, +0.88192129135131835938f,-0.47545027732849121094f,0.87974262237548828125f, +-0.47949376702308654785f,0.87754529714584350586f,-0.48352706432342529297f, +0.87532937526702880859f,-0.48755016922950744629f,0.87309497594833374023f, +-0.49156290292739868164f,0.87084203958511352539f,-0.49556526541709899902f, +0.86857068538665771484f,-0.49955710768699645996f,0.86628097295761108398f, +-0.50353837013244628906f,0.86397284269332885742f,-0.50750899314880371094f, +0.86164647340774536133f,-0.51146882772445678711f,0.85930180549621582031f, +-0.51541787385940551758f,0.85693895816802978516f,-0.51935601234436035156f, +0.85455799102783203125f,-0.52328312397003173828f,0.85215890407562255859f, +-0.52719914913177490234f,0.84974175691604614258f,-0.53110402822494506836f, +0.84730660915374755859f,-0.53499764204025268555f,0.84485357999801635742f, +-0.53887993097305297852f,0.84238260984420776367f,-0.54275077581405639648f, +0.83989381790161132812f,-0.54661017656326293945f,0.83738720417022705078f, +-0.55045795440673828125f,0.83486288785934448242f,-0.55429410934448242188f, +0.83232086896896362305f,-0.55811852216720581055f,0.82976120710372924805f, +-0.56193113327026367188f,0.82718402147293090820f,-0.56573182344436645508f, +0.82458931207656860352f,-0.56952053308486938477f,0.82197713851928710938f, +-0.57329714298248291016f,0.81934750080108642578f,-0.57706165313720703125f, +0.81670057773590087891f,-0.58081394433975219727f,0.81403630971908569336f, +-0.58455395698547363281f,0.81135487556457519531f,-0.58828157186508178711f, +0.80865615606307983398f,-0.59199666976928710938f,0.80594038963317871094f, +-0.59569931030273437500f,0.80320751667022705078f,-0.59938931465148925781f, +0.80045765638351440430f,-0.60306662321090698242f,0.79769086837768554688f, +-0.60673111677169799805f,0.79490715265274047852f,-0.61038279533386230469f, +0.79210656881332397461f,-0.61402153968811035156f,0.78928923606872558594f, +-0.61764729022979736328f,0.78645521402359008789f,-0.62125998735427856445f, +0.78360450267791748047f,-0.62485951185226440430f,0.78073722124099731445f, +-0.62844574451446533203f,0.77785342931747436523f,-0.63201874494552612305f, +0.77495312690734863281f,-0.63557833433151245117f,0.77203637361526489258f, +-0.63912445306777954102f,0.76910334825515747070f,-0.64265704154968261719f, +0.76615399122238159180f,-0.64617604017257690430f,0.76318842172622680664f, +-0.64968132972717285156f,0.76020669937133789062f,-0.65317285060882568359f, +0.75720882415771484375f,-0.65665054321289062500f,0.75419497489929199219f, +-0.66011434793472290039f,0.75116515159606933594f,-0.66356414556503295898f, +0.74811935424804687500f,-0.66699993610382080078f,0.74505776166915893555f, +-0.67042154073715209961f,0.74198043346405029297f,-0.67382901906967163086f, +0.73888731002807617188f,-0.67722219228744506836f,0.73577857017517089844f, +-0.68060100078582763672f,0.73265427350997924805f,-0.68396538496017456055f, +0.72951442003250122070f,-0.68731534481048583984f,0.72635912895202636719f, +-0.69065070152282714844f,0.72318845987319946289f,-0.69397145509719848633f, +0.72000253200531005859f,-0.69727748632431030273f,0.71680128574371337891f, +-0.70056879520416259766f,0.71358484029769897461f,-0.70384526252746582031f, +0.71035337448120117188f,-0.70710676908493041992f,0.70710676908493041992f, +-0.71035337448120117188f,0.70384526252746582031f,-0.71358484029769897461f, +0.70056879520416259766f,-0.71680128574371337891f,0.69727748632431030273f, +-0.72000253200531005859f,0.69397145509719848633f,-0.72318845987319946289f, +0.69065070152282714844f,-0.72635912895202636719f,0.68731534481048583984f, +-0.72951442003250122070f,0.68396538496017456055f,-0.73265427350997924805f, +0.68060100078582763672f,-0.73577857017517089844f,0.67722219228744506836f, +-0.73888731002807617188f,0.67382901906967163086f,-0.74198043346405029297f, +0.67042154073715209961f,-0.74505776166915893555f,0.66699993610382080078f, +-0.74811935424804687500f,0.66356414556503295898f,-0.75116515159606933594f, +0.66011434793472290039f,-0.75419497489929199219f,0.65665054321289062500f, +-0.75720882415771484375f,0.65317285060882568359f,-0.76020669937133789062f, +0.64968132972717285156f,-0.76318842172622680664f,0.64617604017257690430f, +-0.76615399122238159180f,0.64265704154968261719f,-0.76910334825515747070f, +0.63912445306777954102f,-0.77203637361526489258f,0.63557833433151245117f, +-0.77495312690734863281f,0.63201874494552612305f,-0.77785342931747436523f, +0.62844574451446533203f,-0.78073722124099731445f,0.62485951185226440430f, +-0.78360450267791748047f,0.62125998735427856445f,-0.78645521402359008789f, +0.61764729022979736328f,-0.78928923606872558594f,0.61402153968811035156f, +-0.79210656881332397461f,0.61038279533386230469f,-0.79490715265274047852f, +0.60673111677169799805f,-0.79769086837768554688f,0.60306662321090698242f, +-0.80045765638351440430f,0.59938931465148925781f,-0.80320751667022705078f, +0.59569931030273437500f,-0.80594038963317871094f,0.59199666976928710938f, +-0.80865615606307983398f,0.58828157186508178711f,-0.81135487556457519531f, +0.58455395698547363281f,-0.81403630971908569336f,0.58081394433975219727f, +-0.81670057773590087891f,0.57706165313720703125f,-0.81934750080108642578f, +0.57329714298248291016f,-0.82197713851928710938f,0.56952053308486938477f, +-0.82458931207656860352f,0.56573182344436645508f,-0.82718402147293090820f, +0.56193113327026367188f,-0.82976120710372924805f,0.55811852216720581055f, +-0.83232086896896362305f,0.55429410934448242188f,-0.83486288785934448242f, +0.55045795440673828125f,-0.83738720417022705078f,0.54661017656326293945f, +-0.83989381790161132812f,0.54275077581405639648f,-0.84238260984420776367f, +0.53887993097305297852f,-0.84485357999801635742f,0.53499764204025268555f, +-0.84730660915374755859f,0.53110402822494506836f,-0.84974175691604614258f, +0.52719914913177490234f,-0.85215890407562255859f,0.52328312397003173828f, +-0.85455799102783203125f,0.51935601234436035156f,-0.85693895816802978516f, +0.51541787385940551758f,-0.85930180549621582031f,0.51146882772445678711f, +-0.86164647340774536133f,0.50750899314880371094f,-0.86397284269332885742f, +0.50353837013244628906f,-0.86628097295761108398f,0.49955710768699645996f, +-0.86857068538665771484f,0.49556526541709899902f,-0.87084203958511352539f, +0.49156290292739868164f,-0.87309497594833374023f,0.48755016922950744629f, +-0.87532937526702880859f,0.48352706432342529297f,-0.87754529714584350586f, +0.47949376702308654785f,-0.87974262237548828125f,0.47545027732849121094f, +-0.88192129135131835938f,0.47139674425125122070f,-0.88408124446868896484f, +0.46733319759368896484f,-0.88622254133224487305f,0.46325978636741638184f, +-0.88834506273269653320f,0.45917654037475585938f,-0.89044874906539916992f, +0.45508357882499694824f,-0.89253354072570800781f,0.45098099112510681152f, +-0.89459949731826782227f,0.44686883687973022461f,-0.89664649963378906250f, +0.44274723529815673828f,-0.89867448806762695312f,0.43861624598503112793f, +-0.90068340301513671875f,0.43447595834732055664f,-0.90267330408096313477f, +0.43032649159431457520f,-0.90464407205581665039f,0.42616787552833557129f, +-0.90659570693969726562f,0.42200025916099548340f,-0.90852808952331542969f, +0.41782370209693908691f,-0.91044127941131591797f,0.41363832354545593262f, +-0.91233515739440917969f,0.40944415330886840820f,-0.91420978307723999023f, +0.40524131059646606445f,-0.91606497764587402344f,0.40102988481521606445f, +-0.91790080070495605469f,0.39680999517440795898f,-0.91971713304519653320f, +0.39258167147636413574f,-0.92151403427124023438f,0.38834503293037414551f, +-0.92329144477844238281f,0.38410019874572753906f,-0.92504924535751342773f, +0.37984719872474670410f,-0.92678749561309814453f,0.37558618187904357910f, +-0.92850607633590698242f,0.37131720781326293945f,-0.93020504713058471680f, +0.36704033613204956055f,-0.93188428878784179688f,0.36275571584701538086f, +-0.93354380130767822266f,0.35846340656280517578f,-0.93518352508544921875f, +0.35416352748870849609f,-0.93680346012115478516f,0.34985613822937011719f, +-0.93840354681015014648f,0.34554132819175720215f,-0.93998372554779052734f, +0.34121921658515930176f,-0.94154405593872070312f,0.33688986301422119141f, +-0.94308441877365112305f,0.33255335688591003418f,-0.94460481405258178711f, +0.32820984721183776855f,-0.94610524177551269531f,0.32385936379432678223f, +-0.94758558273315429688f,0.31950202584266662598f,-0.94904589653015136719f, +0.31513792276382446289f,-0.95048606395721435547f,0.31076714396476745605f, +-0.95190614461898803711f,0.30638980865478515625f,-0.95330601930618286133f, +0.30200594663619995117f,-0.95468574762344360352f,0.29761570692062377930f, +-0.95604526996612548828f,0.29321914911270141602f,-0.95738452672958374023f, +0.28881642222404479980f,-0.95870345830917358398f,0.28440752625465393066f, +-0.96000212430953979492f,0.27999264001846313477f,-0.96128046512603759766f, +0.27557182312011718750f,-0.96253848075866699219f,0.27114516496658325195f, +-0.96377605199813842773f,0.26671275496482849121f,-0.96499323844909667969f, +0.26227471232414245605f,-0.96618998050689697266f,0.25783109664916992188f, +-0.96736627817153930664f,0.25338202714920043945f,-0.96852207183837890625f, +0.24892760813236236572f,-0.96965736150741577148f,0.24446789920330047607f, +-0.97077214717864990234f,0.24000301957130432129f,-0.97186630964279174805f, +0.23553305864334106445f,-0.97293996810913085938f,0.23105810582637786865f, +-0.97399294376373291016f,0.22657826542854309082f,-0.97502535581588745117f, +0.22209362685680389404f,-0.97603708505630493164f,0.21760427951812744141f, +-0.97702813148498535156f,0.21311031281948089600f,-0.97799849510192871094f, +0.20861184597015380859f,-0.97894817590713500977f,0.20410896837711334229f, +-0.97987711429595947266f,0.19960175454616546631f,-0.98078525066375732422f, +0.19509032368659973145f,-0.98167270421981811523f,0.19057475030422210693f, +-0.98253929615020751953f,0.18605515360832214355f,-0.98338508605957031250f, +0.18153160810470581055f,-0.98421007394790649414f,0.17700421810150146484f, +-0.98501425981521606445f,0.17247308790683746338f,-0.98579752445220947266f, +0.16793829202651977539f,-0.98655992746353149414f,0.16339994966983795166f, +-0.98730140924453735352f,0.15885815024375915527f,-0.98802202939987182617f, +0.15431296825408935547f,-0.98872166872024536133f,0.14976453781127929688f, +-0.98940044641494750977f,0.14521291851997375488f,-0.99005818367004394531f, +0.14065824449062347412f,-0.99069499969482421875f,0.13610057532787322998f, +-0.99131083488464355469f,0.13154003024101257324f,-0.99190568923950195312f, +0.12697669863700866699f,-0.99247956275939941406f,0.12241067737340927124f, +-0.99303233623504638672f,0.11784206330776214600f,-0.99356412887573242188f, +0.11327095329761505127f,-0.99407488107681274414f,0.10869744420051574707f, +-0.99456459283828735352f,0.10412163287401199341f,-0.99503320455551147461f, +0.09954361617565155029f,-0.99548077583312988281f,0.09496349841356277466f, +-0.99590724706649780273f,0.09038136154413223267f,-0.99631261825561523438f, +0.08579730987548828125f,-0.99669688940048217773f,0.08121144771575927734f, +-0.99706006050109863281f,0.07662386447191238403f,-0.99740213155746459961f, +0.07203464955091476440f,-0.99772304296493530273f,0.06744392216205596924f, +-0.99802285432815551758f,0.06285175681114196777f,-0.99830156564712524414f, +0.05825826525688171387f,-0.99855905771255493164f,0.05366353690624237061f, +-0.99879544973373413086f,0.04906767606735229492f,-0.99901068210601806641f, +0.04447077214717864990f,-0.99920475482940673828f,0.03987292572855949402f, +-0.99937766790390014648f,0.03527423739433288574f,-0.99952942132949829102f, +0.03067480400204658508f,-0.99966001510620117188f,0.02607471868395805359f, +-0.99976938962936401367f,0.02147408016026020050f,-0.99985766410827636719f, +0.01687298715114593506f,-0.99992471933364868164f,0.01227153837680816650f, +-0.99997061491012573242f,0.00766982883214950562f,-0.99999529123306274414f, +0.00306795677170157433f,-0.99999880790710449219f,-0.00153398013208061457f, +-0.99998116493225097656f,-0.00613588467240333557f,-0.99994236230850219727f, +-0.01073765940964221954f,-0.99988234043121337891f,-0.01533920597285032272f, +-0.99980115890502929688f,-0.01994042843580245972f,-0.99969881772994995117f, +-0.02454122900962829590f,-0.99957531690597534180f,-0.02914150804281234741f, +-0.99943059682846069336f,-0.03374117240309715271f,-0.99926477670669555664f, +-0.03834012150764465332f,-0.99907773733139038086f,-0.04293825849890708923f, +-0.99886953830718994141f,-0.04753548279404640198f,-0.99864023923873901367f, +-0.05213170498609542847f,-0.99838972091674804688f,-0.05672682076692581177f, +-0.99811810255050659180f,-0.06132073700428009033f,-0.99782532453536987305f, +-0.06591334939002990723f,-0.99751144647598266602f,-0.07050457596778869629f, +-0.99717640876770019531f,-0.07509429752826690674f,-0.99682027101516723633f, +-0.07968243956565856934f,-0.99644303321838378906f,-0.08426889032125473022f, +-0.99604469537734985352f,-0.08885355293750762939f,-0.99562525749206542969f, +-0.09343633800745010376f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.99472314119338989258f,-0.10259586572647094727f,-0.99424046277999877930f, +-0.10717242211103439331f,-0.99373674392700195312f,-0.11174671351909637451f, +-0.99321192502975463867f,-0.11631862819194793701f,-0.99266612529754638672f, +-0.12088808417320251465f,-0.99209928512573242188f,-0.12545497715473175049f, +-0.99151146411895751953f,-0.13001921772956848145f,-0.99090266227722167969f, +-0.13458070158958435059f,-0.99027281999588012695f,-0.13913933932781219482f, +-0.98962199687957763672f,-0.14369502663612365723f,-0.98895025253295898438f, +-0.14824767410755157471f,-0.98825758695602416992f,-0.15279719233512878418f, +-0.98754394054412841797f,-0.15734346210956573486f,-0.98680937290191650391f, +-0.16188639402389526367f,-0.98605394363403320312f,-0.16642589867115020752f, +-0.98527765274047851562f,-0.17096188664436340332f,-0.98448044061660766602f, +-0.17549425363540649414f,-0.98366242647171020508f,-0.18002289533615112305f, +-0.98282355070114135742f,-0.18454773724079132080f,-0.98196387290954589844f, +-0.18906866014003753662f,-0.98108339309692382812f,-0.19358558952808380127f, +-0.98018211126327514648f,-0.19809840619564056396f,-0.97926014661788940430f, +-0.20260703563690185547f,-0.97831737995147705078f,-0.20711137354373931885f, +-0.97735387086868286133f,-0.21161133050918579102f,-0.97636973857879638672f, +-0.21610680222511291504f,-0.97536486387252807617f,-0.22059768438339233398f, +-0.97433936595916748047f,-0.22508391737937927246f,-0.97329324483871459961f, +-0.22956536710262298584f,-0.97222650051116943359f,-0.23404195904731750488f, +-0.97113913297653198242f,-0.23851358890533447266f,-0.97003126144409179688f, +-0.24298018217086791992f,-0.96890282630920410156f,-0.24744161963462829590f, +-0.96775382757186889648f,-0.25189781188964843750f,-0.96658438444137573242f, +-0.25634866952896118164f,-0.96539443731307983398f,-0.26079410314559936523f, +-0.96418404579162597656f,-0.26523402333259582520f,-0.96295326948165893555f, +-0.26966831088066101074f,-0.96170204877853393555f,-0.27409690618515014648f, +-0.96043050289154052734f,-0.27851969003677368164f,-0.95913863182067871094f, +-0.28293657302856445312f,-0.95782643556594848633f,-0.28734746575355529785f, +-0.95649391412734985352f,-0.29175224900245666504f,-0.95514118671417236328f, +-0.29615089297294616699f,-0.95376819372177124023f,-0.30054324865341186523f, +-0.95237499475479125977f,-0.30492922663688659668f,-0.95096164941787719727f, +-0.30930876731872558594f,-0.94952815771102905273f,-0.31368175148963928223f, +-0.94807457923889160156f,-0.31804808974266052246f,-0.94660091400146484375f, +-0.32240769267082214355f,-0.94510722160339355469f,-0.32676044106483459473f, +-0.94359344244003295898f,-0.33110630512237548828f,-0.94205975532531738281f, +-0.33544513583183288574f,-0.94050604104995727539f,-0.33977687358856201172f, +-0.93893247842788696289f,-0.34410142898559570312f,-0.93733900785446166992f, +-0.34841868281364440918f,-0.93572568893432617188f,-0.35272854566574096680f, +-0.93409252166748046875f,-0.35703095793724060059f,-0.93243962526321411133f, +-0.36132580041885375977f,-0.93076694011688232422f,-0.36561298370361328125f, +-0.92907458543777465820f,-0.36989244818687438965f,-0.92736250162124633789f, +-0.37416407465934753418f,-0.92563080787658691406f,-0.37842774391174316406f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.92210865020751953125f, +-0.38693100214004516602f,-0.92031830549240112305f,-0.39117038249969482422f, +-0.91850841045379638672f,-0.39540147781372070312f,-0.91667908430099487305f, +-0.39962419867515563965f,-0.91483032703399658203f,-0.40383845567703247070f, +-0.91296219825744628906f,-0.40804415941238403320f,-0.91107475757598876953f, +-0.41224122047424316406f,-0.90916800498962402344f,-0.41642954945564270020f, +-0.90724200010299682617f,-0.42060908675193786621f,-0.90529674291610717773f, +-0.42477968335151672363f,-0.90333235263824462891f,-0.42894127964973449707f, +-0.90134882926940917969f,-0.43309381604194641113f,-0.89934623241424560547f, +-0.43723717331886291504f,-0.89732456207275390625f,-0.44137126207351684570f, +-0.89528393745422363281f,-0.44549602270126342773f,-0.89322429895401000977f, +-0.44961133599281311035f,-0.89114576578140258789f,-0.45371711254119873047f, +-0.88904833793640136719f,-0.45781329274177551270f,-0.88693213462829589844f, +-0.46189978718757629395f,-0.88479709625244140625f,-0.46597650647163391113f, +-0.88264334201812744141f,-0.47004333138465881348f,-0.88047087192535400391f, +-0.47410020232200622559f,-0.87827980518341064453f,-0.47814705967903137207f, +-0.87607008218765258789f,-0.48218378424644470215f,-0.87384182214736938477f, +-0.48621028661727905273f,-0.87159508466720581055f,-0.49022647738456726074f, +-0.86932986974716186523f,-0.49423229694366455078f,-0.86704623699188232422f, +-0.49822765588760375977f,-0.86474424600601196289f,-0.50221246480941772461f, +-0.86242395639419555664f,-0.50618666410446166992f,-0.86008536815643310547f, +-0.51015007495880126953f,-0.85772860050201416016f,-0.51410275697708129883f, +-0.85535365343093872070f,-0.51804453134536743164f,-0.85296058654785156250f, +-0.52197527885437011719f,-0.85054945945739746094f,-0.52589499950408935547f, +-0.84812033176422119141f,-0.52980363368988037109f,-0.84567326307296752930f, +-0.53370100259780883789f,-0.84320825338363647461f,-0.53758704662322998047f, +-0.84072536230087280273f,-0.54146176576614379883f,-0.83822470903396606445f, +-0.54532498121261596680f,-0.83570629358291625977f,-0.54917663335800170898f, +-0.83317017555236816406f,-0.55301672220230102539f,-0.83061641454696655273f, +-0.55684500932693481445f,-0.82804507017135620117f,-0.56066155433654785156f, +-0.82545614242553710938f,-0.56446623802185058594f,-0.82284981012344360352f, +-0.56825894117355346680f,-0.82022595405578613281f,-0.57203960418701171875f, +-0.81758481264114379883f,-0.57580816745758056641f,-0.81492632627487182617f, +-0.57956457138061523438f,-0.81225061416625976562f,-0.58330863714218139648f, +-0.80955761671066284180f,-0.58704036474227905273f,-0.80684757232666015625f, +-0.59075969457626342773f,-0.80412036180496215820f,-0.59446650743484497070f, +-0.80137616395950317383f,-0.59816068410873413086f,-0.79861497879028320312f, +-0.60184222459793090820f,-0.79583692550659179688f,-0.60551106929779052734f, +-0.79304194450378417969f,-0.60916703939437866211f,-0.79023021459579467773f, +-0.61281007528305053711f,-0.78740173578262329102f,-0.61644017696380615234f, +-0.78455656766891479492f,-0.62005722522735595703f,-0.78169482946395874023f, +-0.62366110086441040039f,-0.77881652116775512695f,-0.62725180387496948242f, +-0.77592170238494873047f,-0.63082921504974365234f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.77008283138275146484f,-0.63794392347335815430f, +-0.76713889837265014648f,-0.64148104190826416016f,-0.76417875289916992188f, +-0.64500451087951660156f,-0.76120239496231079102f,-0.64851438999176025391f, +-0.75820988416671752930f,-0.65201056003570556641f,-0.75520139932632446289f, +-0.65549284219741821289f,-0.75217682123184204102f,-0.65896129608154296875f, +-0.74913638830184936523f,-0.66241580247879028320f,-0.74608010053634643555f, +-0.66585624217987060547f,-0.74300795793533325195f,-0.66928261518478393555f, +-0.73992007970809936523f,-0.67269474267959594727f,-0.73681658506393432617f, +-0.67609268426895141602f,-0.73369741439819335938f,-0.67947632074356079102f, +-0.73056274652481079102f,-0.68284553289413452148f,-0.72741264104843139648f, +-0.68620032072067260742f,-0.72424709796905517578f,-0.68954056501388549805f, +-0.72106617689132690430f,-0.69286614656448364258f,-0.71787005662918090820f, +-0.69617712497711181641f,-0.71465867757797241211f,-0.69947332143783569336f, +-0.71143221855163574219f,-0.70275473594665527344f,-0.70819061994552612305f, +-0.70602124929428100586f,-0.70493406057357788086f,-0.70927280187606811523f, +-0.70166260004043579102f,-0.71250939369201660156f,-0.69837623834609985352f, +-0.71573084592819213867f,-0.69507509469985961914f,-0.71893709897994995117f, +-0.69175922870635986328f,-0.72212821245193481445f,-0.68842875957489013672f, +-0.72530394792556762695f,-0.68508368730545043945f,-0.72846436500549316406f, +-0.68172407150268554688f,-0.73160940408706665039f,-0.67835003137588500977f, +-0.73473888635635375977f,-0.67496162652969360352f,-0.73785281181335449219f, +-0.67155897617340087891f,-0.74095112085342407227f,-0.66814202070236206055f, +-0.74403375387191772461f,-0.66471099853515625000f,-0.74710059165954589844f, +-0.66126585006713867188f,-0.75015163421630859375f,-0.65780669450759887695f, +-0.75318682193756103516f,-0.65433359146118164062f,-0.75620597600936889648f, +-0.65084666013717651367f,-0.75920921564102172852f,-0.64734596014022827148f, +-0.76219630241394042969f,-0.64383155107498168945f,-0.76516723632812500000f, +-0.64030349254608154297f,-0.76812201738357543945f,-0.63676184415817260742f, +-0.77106052637100219727f,-0.63320678472518920898f,-0.77398270368576049805f, +-0.62963825464248657227f,-0.77688848972320556641f,-0.62605637311935424805f, +-0.77977776527404785156f,-0.62246125936508178711f,-0.78265058994293212891f, +-0.61885297298431396484f,-0.78550684452056884766f,-0.61523157358169555664f, +-0.78834640979766845703f,-0.61159718036651611328f,-0.79116934537887573242f, +-0.60794979333877563477f,-0.79397547245025634766f,-0.60428953170776367188f, +-0.79676479101181030273f,-0.60061645507812500000f,-0.79953724145889282227f, +-0.59693068265914916992f,-0.80229282379150390625f,-0.59323227405548095703f, +-0.80503135919570922852f,-0.58952128887176513672f,-0.80775284767150878906f, +-0.58579784631729125977f,-0.81045717000961303711f,-0.58206200599670410156f, +-0.81314438581466674805f,-0.57831376791000366211f,-0.81581443548202514648f, +-0.57455337047576904297f,-0.81846714019775390625f,-0.57078075408935546875f, +-0.82110249996185302734f,-0.56699603796005249023f,-0.82372051477432250977f, +-0.56319934129714965820f,-0.82632106542587280273f,-0.55939072370529174805f, +-0.82890409231185913086f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.55173796415328979492f,-0.83401751518249511719f,-0.54789406061172485352f, +-0.83654773235321044922f,-0.54403853416442871094f,-0.83906024694442749023f, +-0.54017144441604614258f,-0.84155499935150146484f,-0.53629297018051147461f, +-0.84403187036514282227f,-0.53240311145782470703f,-0.84649091958999633789f, +-0.52850198745727539062f,-0.84893202781677246094f,-0.52458965778350830078f, +-0.85135519504547119141f,-0.52066624164581298828f,-0.85376030206680297852f, +-0.51673179864883422852f,-0.85614734888076782227f,-0.51278638839721679688f, +-0.85851621627807617188f,-0.50883013010025024414f,-0.86086696386337280273f, +-0.50486308336257934570f,-0.86319941282272338867f,-0.50088536739349365234f, +-0.86551362276077270508f,-0.49689704179763793945f,-0.86780947446823120117f, +-0.49289819598197937012f,-0.87008696794509887695f,-0.48888888955116271973f, +-0.87234604358673095703f,-0.48486924171447753906f,-0.87458664178848266602f, +-0.48083934187889099121f,-0.87680870294570922852f,-0.47679921984672546387f, +-0.87901222705841064453f,-0.47274902462959289551f,-0.88119709491729736328f, +-0.46868881583213806152f,-0.88336336612701416016f,-0.46461868286132812500f, +-0.88551086187362670898f,-0.46053871512413024902f,-0.88763964176177978516f, +-0.45644897222518920898f,-0.88974958658218383789f,-0.45234957337379455566f, +-0.89184069633483886719f,-0.44824060797691345215f,-0.89391297101974487305f, +-0.44412213563919067383f,-0.89596623182296752930f,-0.43999427556991577148f, +-0.89800059795379638672f,-0.43585708737373352051f,-0.90001589059829711914f, +-0.43171066045761108398f,-0.90201216936111450195f,-0.42755508422851562500f, +-0.90398931503295898438f,-0.42339047789573669434f,-0.90594726800918579102f, +-0.41921690106391906738f,-0.90788608789443969727f,-0.41503441333770751953f, +-0.90980571508407592773f,-0.41084316372871398926f,-0.91170603036880493164f, +-0.40664321184158325195f,-0.91358703374862670898f,-0.40243464708328247070f, +-0.91544872522354125977f,-0.39821755886077880859f,-0.91729098558425903320f, +-0.39399203658103942871f,-0.91911387443542480469f,-0.38975816965103149414f, +-0.92091721296310424805f,-0.38551604747772216797f,-0.92270112037658691406f, +-0.38126575946807861328f,-0.92446547746658325195f,-0.37700742483139038086f, +-0.92621022462844848633f,-0.37274107336997985840f,-0.92793542146682739258f, +-0.36846682429313659668f,-0.92964088916778564453f,-0.36418479681015014648f, +-0.93132668733596801758f,-0.35989505052566528320f,-0.93299281597137451172f, +-0.35559767484664916992f,-0.93463915586471557617f,-0.35129275918006896973f, +-0.93626564741134643555f,-0.34698042273521423340f,-0.93787235021591186523f, +-0.34266072511672973633f,-0.93945920467376708984f,-0.33833375573158264160f, +-0.94102615118026733398f,-0.33399966359138488770f,-0.94257318973541259766f, +-0.32965844869613647461f,-0.94410026073455810547f,-0.32531028985977172852f, +-0.94560730457305908203f,-0.32095524668693542480f,-0.94709438085556030273f, +-0.31659337878227233887f,-0.94856137037277221680f,-0.31222480535507202148f, +-0.95000827312469482422f,-0.30784964561462402344f,-0.95143502950668334961f, +-0.30346795916557312012f,-0.95284163951873779297f,-0.29907983541488647461f, +-0.95422810316085815430f,-0.29468536376953125000f,-0.95559436082839965820f, +-0.29028466343879699707f,-0.95694035291671752930f,-0.28587782382965087891f, +-0.95826607942581176758f,-0.28146493434906005859f,-0.95957154035568237305f, +-0.27704608440399169922f,-0.96085661649703979492f,-0.27262136340141296387f, +-0.96212142705917358398f,-0.26819086074829101562f,-0.96336579322814941406f, +-0.26375466585159301758f,-0.96458977460861206055f,-0.25931292772293090820f, +-0.96579337120056152344f,-0.25486564636230468750f,-0.96697646379470825195f, +-0.25041300058364868164f,-0.96813911199569702148f,-0.24595504999160766602f, +-0.96928125619888305664f,-0.24149188399314880371f,-0.97040283679962158203f, +-0.23702360689640045166f,-0.97150391340255737305f,-0.23255030810832977295f, +-0.97258436679840087891f,-0.22807207703590393066f,-0.97364425659179687500f, +-0.22358903288841247559f,-0.97468352317810058594f,-0.21910123527050018311f, +-0.97570210695266723633f,-0.21460881829261779785f,-0.97670006752014160156f, +-0.21011184155941009521f,-0.97767734527587890625f,-0.20561040937900543213f, +-0.97863394021987915039f,-0.20110464096069335938f,-0.97956979274749755859f, +-0.19659459590911865234f,-0.98048484325408935547f,-0.19208039343357086182f, +-0.98137921094894409180f,-0.18756212294101715088f,-0.98225271701812744141f, +-0.18303988873958587646f,-0.98310548067092895508f,-0.17851376533508300781f, +-0.98393744230270385742f,-0.17398387193679809570f,-0.98474848270416259766f, +-0.16945029795169830322f,-0.98553872108459472656f,-0.16491311788558959961f, +-0.98630809783935546875f,-0.16037245094776153564f,-0.98705655336380004883f, +-0.15582840144634246826f,-0.98778414726257324219f,-0.15128104388713836670f, +-0.98849081993103027344f,-0.14673046767711639404f,-0.98917651176452636719f, +-0.14217680692672729492f,-0.98984128236770629883f,-0.13762012124061584473f, +-0.99048507213592529297f,-0.13306052982807159424f,-0.99110794067382812500f, +-0.12849810719490051270f,-0.99170976877212524414f,-0.12393297255039215088f, +-0.99229061603546142578f,-0.11936521530151367188f,-0.99285042285919189453f, +-0.11479492485523223877f,-0.99338918924331665039f,-0.11022220551967620850f, +-0.99390697479248046875f,-0.10564715415239334106f,-0.99440366029739379883f, +-0.10106986016035079956f,-0.99487930536270141602f,-0.09649042785167694092f, +-0.99533390998840332031f,-0.09190895408391952515f,-0.99576741456985473633f, +-0.08732553571462631226f,-0.99617981910705566406f,-0.08274026215076446533f, +-0.99657112360000610352f,-0.07815324515104293823f,-0.99694132804870605469f, +-0.07356456667184829712f,-0.99729043245315551758f,-0.06897433102130889893f, +-0.99761843681335449219f,-0.06438262760639190674f,-0.99792528152465820312f, +-0.05978957191109657288f,-0.99821102619171142578f,-0.05519524589180946350f, +-0.99847555160522460938f,-0.05059975013136863708f,-0.99871903657913208008f, +-0.04600318148732185364f,-0.99894130229949951172f,-0.04140564054250717163f, +-0.99914240837097167969f,-0.03680722415447235107f,-0.99932235479354858398f, +-0.03220802545547485352f,-0.99948120117187500000f,-0.02760814502835273743f, +-0.99961882829666137695f,-0.02300768159329891205f,-0.99973529577255249023f, +-0.01840673014521598816f,-0.99983060359954833984f,-0.01380538847297430038f, +-0.99990469217300415039f,-0.00920375436544418335f,-0.99995762109756469727f, +-0.00460192607715725899f,-0.99998939037322998047f,1.00000000000000000000f, +0.00000000000000000000f,0.99983060359954833984f,0.01840673014521598816f, +0.99932235479354858398f,0.03680722415447235107f,0.99847555160522460938f, +0.05519524589180946350f,0.99729043245315551758f,0.07356456667184829712f, +0.99576741456985473633f,0.09190895408391952515f,0.99390697479248046875f, +0.11022220551967620850f,0.99170976877212524414f,0.12849810719490051270f, +0.98917651176452636719f,0.14673046767711639404f,0.98630809783935546875f, +0.16491311788558959961f,0.98310548067092895508f,0.18303988873958587646f, +0.97956979274749755859f,0.20110464096069335938f,0.97570210695266723633f, +0.21910123527050018311f,0.97150391340255737305f,0.23702360689640045166f, +0.96697646379470825195f,0.25486564636230468750f,0.96212142705917358398f, +0.27262136340141296387f,0.95694035291671752930f,0.29028466343879699707f, +0.95143502950668334961f,0.30784964561462402344f,0.94560730457305908203f, +0.32531028985977172852f,0.93945920467376708984f,0.34266072511672973633f, +0.93299281597137451172f,0.35989505052566528320f,0.92621022462844848633f, +0.37700742483139038086f,0.91911387443542480469f,0.39399203658103942871f, +0.91170603036880493164f,0.41084316372871398926f,0.90398931503295898438f, +0.42755508422851562500f,0.89596623182296752930f,0.44412213563919067383f, +0.88763964176177978516f,0.46053871512413024902f,0.87901222705841064453f, +0.47679921984672546387f,0.87008696794509887695f,0.49289819598197937012f, +0.86086696386337280273f,0.50883013010025024414f,0.85135519504547119141f, +0.52458965778350830078f,0.84155499935150146484f,0.54017144441604614258f, +0.83146959543228149414f,0.55557024478912353516f,0.82110249996185302734f, +0.57078075408935546875f,0.81045717000961303711f,0.58579784631729125977f, +0.79953724145889282227f,0.60061645507812500000f,0.78834640979766845703f, +0.61523157358169555664f,0.77688848972320556641f,0.62963825464248657227f, +0.76516723632812500000f,0.64383155107498168945f,0.75318682193756103516f, +0.65780669450759887695f,0.74095112085342407227f,0.67155897617340087891f, +0.72846436500549316406f,0.68508368730545043945f,0.71573084592819213867f, +0.69837623834609985352f,0.70275473594665527344f,0.71143221855163574219f, +0.68954056501388549805f,0.72424709796905517578f,0.67609268426895141602f, +0.73681658506393432617f,0.66241580247879028320f,0.74913638830184936523f, +0.64851438999176025391f,0.76120239496231079102f,0.63439327478408813477f, +0.77301043272018432617f,0.62005722522735595703f,0.78455656766891479492f, +0.60551106929779052734f,0.79583692550659179688f,0.59075969457626342773f, +0.80684757232666015625f,0.57580816745758056641f,0.81758481264114379883f, +0.56066155433654785156f,0.82804507017135620117f,0.54532498121261596680f, +0.83822470903396606445f,0.52980363368988037109f,0.84812033176422119141f, +0.51410275697708129883f,0.85772860050201416016f,0.49822765588760375977f, +0.86704623699188232422f,0.48218378424644470215f,0.87607008218765258789f, +0.46597650647163391113f,0.88479709625244140625f,0.44961133599281311035f, +0.89322429895401000977f,0.43309381604194641113f,0.90134882926940917969f, +0.41642954945564270020f,0.90916800498962402344f,0.39962419867515563965f, +0.91667908430099487305f,0.38268342614173889160f,0.92387950420379638672f, +0.36561298370361328125f,0.93076694011688232422f,0.34841868281364440918f, +0.93733900785446166992f,0.33110630512237548828f,0.94359344244003295898f, +0.31368175148963928223f,0.94952815771102905273f,0.29615089297294616699f, +0.95514118671417236328f,0.27851969003677368164f,0.96043050289154052734f, +0.26079410314559936523f,0.96539443731307983398f,0.24298018217086791992f, +0.97003126144409179688f,0.22508391737937927246f,0.97433936595916748047f, +0.20711137354373931885f,0.97831737995147705078f,0.18906866014003753662f, +0.98196387290954589844f,0.17096188664436340332f,0.98527765274047851562f, +0.15279719233512878418f,0.98825758695602416992f,0.13458070158958435059f, +0.99090266227722167969f,0.11631862819194793701f,0.99321192502975463867f, +0.09801714122295379639f,0.99518471956253051758f,0.07968243956565856934f, +0.99682027101516723633f,0.06132073700428009033f,0.99811810255050659180f, +0.04293825849890708923f,0.99907773733139038086f,0.02454122900962829590f, +0.99969881772994995117f,0.00613588467240333557f,0.99998116493225097656f, +-0.01227153837680816650f,0.99992471933364868164f,-0.03067480400204658508f, +0.99952942132949829102f,-0.04906767606735229492f,0.99879544973373413086f, +-0.06744392216205596924f,0.99772304296493530273f,-0.08579730987548828125f, +0.99631261825561523438f,-0.10412163287401199341f,0.99456459283828735352f, +-0.12241067737340927124f,0.99247956275939941406f,-0.14065824449062347412f, +0.99005818367004394531f,-0.15885815024375915527f,0.98730140924453735352f, +-0.17700421810150146484f,0.98421007394790649414f,-0.19509032368659973145f, +0.98078525066375732422f,-0.21311031281948089600f,0.97702813148498535156f, +-0.23105810582637786865f,0.97293996810913085938f,-0.24892760813236236572f, +0.96852207183837890625f,-0.26671275496482849121f,0.96377605199813842773f, +-0.28440752625465393066f,0.95870345830917358398f,-0.30200594663619995117f, +0.95330601930618286133f,-0.31950202584266662598f,0.94758558273315429688f, +-0.33688986301422119141f,0.94154405593872070312f,-0.35416352748870849609f, +0.93518352508544921875f,-0.37131720781326293945f,0.92850607633590698242f, +-0.38834503293037414551f,0.92151403427124023438f,-0.40524131059646606445f, +0.91420978307723999023f,-0.42200025916099548340f,0.90659570693969726562f, +-0.43861624598503112793f,0.89867448806762695312f,-0.45508357882499694824f, +0.89044874906539916992f,-0.47139674425125122070f,0.88192129135131835938f, +-0.48755016922950744629f,0.87309497594833374023f,-0.50353837013244628906f, +0.86397284269332885742f,-0.51935601234436035156f,0.85455799102783203125f, +-0.53499764204025268555f,0.84485357999801635742f,-0.55045795440673828125f, +0.83486288785934448242f,-0.56573182344436645508f,0.82458931207656860352f, +-0.58081394433975219727f,0.81403630971908569336f,-0.59569931030273437500f, +0.80320751667022705078f,-0.61038279533386230469f,0.79210656881332397461f, +-0.62485951185226440430f,0.78073722124099731445f,-0.63912445306777954102f, +0.76910334825515747070f,-0.65317285060882568359f,0.75720882415771484375f, +-0.66699993610382080078f,0.74505776166915893555f,-0.68060100078582763672f, +0.73265427350997924805f,-0.69397145509719848633f,0.72000253200531005859f, +-0.70710676908493041992f,0.70710676908493041992f,-0.72000253200531005859f, +0.69397145509719848633f,-0.73265427350997924805f,0.68060100078582763672f, +-0.74505776166915893555f,0.66699993610382080078f,-0.75720882415771484375f, +0.65317285060882568359f,-0.76910334825515747070f,0.63912445306777954102f, +-0.78073722124099731445f,0.62485951185226440430f,-0.79210656881332397461f, +0.61038279533386230469f,-0.80320751667022705078f,0.59569931030273437500f, +-0.81403630971908569336f,0.58081394433975219727f,-0.82458931207656860352f, +0.56573182344436645508f,-0.83486288785934448242f,0.55045795440673828125f, +-0.84485357999801635742f,0.53499764204025268555f,-0.85455799102783203125f, +0.51935601234436035156f,-0.86397284269332885742f,0.50353837013244628906f, +-0.87309497594833374023f,0.48755016922950744629f,-0.88192129135131835938f, +0.47139674425125122070f,-0.89044874906539916992f,0.45508357882499694824f, +-0.89867448806762695312f,0.43861624598503112793f,-0.90659570693969726562f, +0.42200025916099548340f,-0.91420978307723999023f,0.40524131059646606445f, +-0.92151403427124023438f,0.38834503293037414551f,-0.92850607633590698242f, +0.37131720781326293945f,-0.93518352508544921875f,0.35416352748870849609f, +-0.94154405593872070312f,0.33688986301422119141f,-0.94758558273315429688f, +0.31950202584266662598f,-0.95330601930618286133f,0.30200594663619995117f, +-0.95870345830917358398f,0.28440752625465393066f,-0.96377605199813842773f, +0.26671275496482849121f,-0.96852207183837890625f,0.24892760813236236572f, +-0.97293996810913085938f,0.23105810582637786865f,-0.97702813148498535156f, +0.21311031281948089600f,-0.98078525066375732422f,0.19509032368659973145f, +-0.98421007394790649414f,0.17700421810150146484f,-0.98730140924453735352f, +0.15885815024375915527f,-0.99005818367004394531f,0.14065824449062347412f, +-0.99247956275939941406f,0.12241067737340927124f,-0.99456459283828735352f, +0.10412163287401199341f,-0.99631261825561523438f,0.08579730987548828125f, +-0.99772304296493530273f,0.06744392216205596924f,-0.99879544973373413086f, +0.04906767606735229492f,-0.99952942132949829102f,0.03067480400204658508f, +-0.99992471933364868164f,0.01227153837680816650f,-0.99998116493225097656f, +-0.00613588467240333557f,-0.99969881772994995117f,-0.02454122900962829590f, +-0.99907773733139038086f,-0.04293825849890708923f,-0.99811810255050659180f, +-0.06132073700428009033f,-0.99682027101516723633f,-0.07968243956565856934f, +-0.99518471956253051758f,-0.09801714122295379639f,-0.99321192502975463867f, +-0.11631862819194793701f,-0.99090266227722167969f,-0.13458070158958435059f, +-0.98825758695602416992f,-0.15279719233512878418f,-0.98527765274047851562f, +-0.17096188664436340332f,-0.98196387290954589844f,-0.18906866014003753662f, +-0.97831737995147705078f,-0.20711137354373931885f,-0.97433936595916748047f, +-0.22508391737937927246f,-0.97003126144409179688f,-0.24298018217086791992f, +-0.96539443731307983398f,-0.26079410314559936523f,-0.96043050289154052734f, +-0.27851969003677368164f,-0.95514118671417236328f,-0.29615089297294616699f, +-0.94952815771102905273f,-0.31368175148963928223f,-0.94359344244003295898f, +-0.33110630512237548828f,-0.93733900785446166992f,-0.34841868281364440918f, +-0.93076694011688232422f,-0.36561298370361328125f,-0.92387950420379638672f, +-0.38268342614173889160f,-0.91667908430099487305f,-0.39962419867515563965f, +-0.90916800498962402344f,-0.41642954945564270020f,-0.90134882926940917969f, +-0.43309381604194641113f,-0.89322429895401000977f,-0.44961133599281311035f, +-0.88479709625244140625f,-0.46597650647163391113f,-0.87607008218765258789f, +-0.48218378424644470215f,-0.86704623699188232422f,-0.49822765588760375977f, +-0.85772860050201416016f,-0.51410275697708129883f,-0.84812033176422119141f, +-0.52980363368988037109f,-0.83822470903396606445f,-0.54532498121261596680f, +-0.82804507017135620117f,-0.56066155433654785156f,-0.81758481264114379883f, +-0.57580816745758056641f,-0.80684757232666015625f,-0.59075969457626342773f, +-0.79583692550659179688f,-0.60551106929779052734f,-0.78455656766891479492f, +-0.62005722522735595703f,-0.77301043272018432617f,-0.63439327478408813477f, +-0.76120239496231079102f,-0.64851438999176025391f,-0.74913638830184936523f, +-0.66241580247879028320f,-0.73681658506393432617f,-0.67609268426895141602f, +-0.72424709796905517578f,-0.68954056501388549805f,-0.71143221855163574219f, +-0.70275473594665527344f,-0.69837623834609985352f,-0.71573084592819213867f, +-0.68508368730545043945f,-0.72846436500549316406f,-0.67155897617340087891f, +-0.74095112085342407227f,-0.65780669450759887695f,-0.75318682193756103516f, +-0.64383155107498168945f,-0.76516723632812500000f,-0.62963825464248657227f, +-0.77688848972320556641f,-0.61523157358169555664f,-0.78834640979766845703f, +-0.60061645507812500000f,-0.79953724145889282227f,-0.58579784631729125977f, +-0.81045717000961303711f,-0.57078075408935546875f,-0.82110249996185302734f, +-0.55557024478912353516f,-0.83146959543228149414f,-0.54017144441604614258f, +-0.84155499935150146484f,-0.52458965778350830078f,-0.85135519504547119141f, +-0.50883013010025024414f,-0.86086696386337280273f,-0.49289819598197937012f, +-0.87008696794509887695f,-0.47679921984672546387f,-0.87901222705841064453f, +-0.46053871512413024902f,-0.88763964176177978516f,-0.44412213563919067383f, +-0.89596623182296752930f,-0.42755508422851562500f,-0.90398931503295898438f, +-0.41084316372871398926f,-0.91170603036880493164f,-0.39399203658103942871f, +-0.91911387443542480469f,-0.37700742483139038086f,-0.92621022462844848633f, +-0.35989505052566528320f,-0.93299281597137451172f,-0.34266072511672973633f, +-0.93945920467376708984f,-0.32531028985977172852f,-0.94560730457305908203f, +-0.30784964561462402344f,-0.95143502950668334961f,-0.29028466343879699707f, +-0.95694035291671752930f,-0.27262136340141296387f,-0.96212142705917358398f, +-0.25486564636230468750f,-0.96697646379470825195f,-0.23702360689640045166f, +-0.97150391340255737305f,-0.21910123527050018311f,-0.97570210695266723633f, +-0.20110464096069335938f,-0.97956979274749755859f,-0.18303988873958587646f, +-0.98310548067092895508f,-0.16491311788558959961f,-0.98630809783935546875f, +-0.14673046767711639404f,-0.98917651176452636719f,-0.12849810719490051270f, +-0.99170976877212524414f,-0.11022220551967620850f,-0.99390697479248046875f, +-0.09190895408391952515f,-0.99576741456985473633f,-0.07356456667184829712f, +-0.99729043245315551758f,-0.05519524589180946350f,-0.99847555160522460938f, +-0.03680722415447235107f,-0.99932235479354858398f,-0.01840673014521598816f, +-0.99983060359954833984f,1.00000000000000000000f,0.00000000000000000000f, +0.99729043245315551758f,0.07356456667184829712f,0.98917651176452636719f, +0.14673046767711639404f,0.97570210695266723633f,0.21910123527050018311f, +0.95694035291671752930f,0.29028466343879699707f,0.93299281597137451172f, +0.35989505052566528320f,0.90398931503295898438f,0.42755508422851562500f, +0.87008696794509887695f,0.49289819598197937012f,0.83146959543228149414f, +0.55557024478912353516f,0.78834640979766845703f,0.61523157358169555664f, +0.74095112085342407227f,0.67155897617340087891f,0.68954056501388549805f, +0.72424709796905517578f,0.63439327478408813477f,0.77301043272018432617f, +0.57580816745758056641f,0.81758481264114379883f,0.51410275697708129883f, +0.85772860050201416016f,0.44961133599281311035f,0.89322429895401000977f, +0.38268342614173889160f,0.92387950420379638672f,0.31368175148963928223f, +0.94952815771102905273f,0.24298018217086791992f,0.97003126144409179688f, +0.17096188664436340332f,0.98527765274047851562f,0.09801714122295379639f, +0.99518471956253051758f,0.02454122900962829590f,0.99969881772994995117f, +-0.04906767606735229492f,0.99879544973373413086f,-0.12241067737340927124f, +0.99247956275939941406f,-0.19509032368659973145f,0.98078525066375732422f, +-0.26671275496482849121f,0.96377605199813842773f,-0.33688986301422119141f, +0.94154405593872070312f,-0.40524131059646606445f,0.91420978307723999023f, +-0.47139674425125122070f,0.88192129135131835938f,-0.53499764204025268555f, +0.84485357999801635742f,-0.59569931030273437500f,0.80320751667022705078f, +-0.65317285060882568359f,0.75720882415771484375f,-0.70710676908493041992f, +0.70710676908493041992f,-0.75720882415771484375f,0.65317285060882568359f, +-0.80320751667022705078f,0.59569931030273437500f,-0.84485357999801635742f, +0.53499764204025268555f,-0.88192129135131835938f,0.47139674425125122070f, +-0.91420978307723999023f,0.40524131059646606445f,-0.94154405593872070312f, +0.33688986301422119141f,-0.96377605199813842773f,0.26671275496482849121f, +-0.98078525066375732422f,0.19509032368659973145f,-0.99247956275939941406f, +0.12241067737340927124f,-0.99879544973373413086f,0.04906767606735229492f, +-0.99969881772994995117f,-0.02454122900962829590f,-0.99518471956253051758f, +-0.09801714122295379639f,-0.98527765274047851562f,-0.17096188664436340332f, +-0.97003126144409179688f,-0.24298018217086791992f,-0.94952815771102905273f, +-0.31368175148963928223f,-0.92387950420379638672f,-0.38268342614173889160f, +-0.89322429895401000977f,-0.44961133599281311035f,-0.85772860050201416016f, +-0.51410275697708129883f,-0.81758481264114379883f,-0.57580816745758056641f, +-0.77301043272018432617f,-0.63439327478408813477f,-0.72424709796905517578f, +-0.68954056501388549805f,-0.67155897617340087891f,-0.74095112085342407227f, +-0.61523157358169555664f,-0.78834640979766845703f,-0.55557024478912353516f, +-0.83146959543228149414f,-0.49289819598197937012f,-0.87008696794509887695f, +-0.42755508422851562500f,-0.90398931503295898438f,-0.35989505052566528320f, +-0.93299281597137451172f,-0.29028466343879699707f,-0.95694035291671752930f, +-0.21910123527050018311f,-0.97570210695266723633f,-0.14673046767711639404f, +-0.98917651176452636719f,-0.07356456667184829712f,-0.99729043245315551758f, +1.00000000000000000000f,0.00000000000000000000f,0.95694035291671752930f, +0.29028466343879699707f,0.83146959543228149414f,0.55557024478912353516f, +0.63439327478408813477f,0.77301043272018432617f,0.38268342614173889160f, +0.92387950420379638672f,0.09801714122295379639f,0.99518471956253051758f, +-0.19509032368659973145f,0.98078525066375732422f,-0.47139674425125122070f, +0.88192129135131835938f,-0.70710676908493041992f,0.70710676908493041992f, +-0.88192129135131835938f,0.47139674425125122070f,-0.98078525066375732422f, +0.19509032368659973145f,-0.99518471956253051758f,-0.09801714122295379639f, +-0.92387950420379638672f,-0.38268342614173889160f,-0.77301043272018432617f, +-0.63439327478408813477f,-0.55557024478912353516f,-0.83146959543228149414f, +-0.29028466343879699707f,-0.95694035291671752930f,1.00000000000000000000f, +0.00000000000000000000f,0.38268342614173889160f,0.92387950420379638672f, +-0.70710676908493041992f,0.70710676908493041992f,-0.92387950420379638672f, +-0.38268342614173889160f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]={ +0,0,}; + +q31_t rearranged_twiddle_stride1_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_16_q31[8]={ +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]={ +0,32,0,}; + +q31_t rearranged_twiddle_stride1_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_64_q31[40]={ +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]={ +0,128,160,0,}; + +q31_t rearranged_twiddle_stride1_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684,0x7FA736B4, +0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC,0xED37EF91, +0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE, +0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8, +0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345, +0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590, +0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4, +0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B, +0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0, +0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376, +0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4, +0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0, +0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32, +0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3, +0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E, +0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E, +0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B, +0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872, +0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40, +0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590, +0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94, +0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3, +0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF, +0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC, +0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2, +0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6, +0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C, +0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2, +0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C, +0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D, +0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412, +0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C, +0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971, +0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2, +0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F, +0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C, +0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666, +0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C, +0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC, +0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412, +0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2, +0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D, +0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C, +0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4, +0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666, +0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF, +0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_256_q31[168]={ +0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2, +0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC, +0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A, +0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F, +0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928, +0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971, +0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4, +0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB, +0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510, +0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C, +0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC, +0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5, +0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16, +0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D, +0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54, +0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926, +0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E, +0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC, +0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4, +0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971, +0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A, +0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D, +0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF, +0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]={ +0,512,640,672,0,}; + +q31_t rearranged_twiddle_stride1_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFF6216,0xFF36F078,0x7FFD885A,0xFE6DE2E0,0x7FFA72D1, +0xFDA4D929,0x7FF62182,0xFCDBD541,0x7FF09478,0xFC12D91A,0x7FE9CBC0,0xFB49E6A3, +0x7FE1C76B,0xFA80FFCB,0x7FD8878E,0xF9B82684,0x7FCE0C3E,0xF8EF5CBB,0x7FC25596, +0xF826A462,0x7FB563B3,0xF75DFF66,0x7FA736B4,0xF6956FB7,0x7F97CEBD,0xF5CCF743, +0x7F872BF3,0xF50497FB,0x7F754E80,0xF43C53CB,0x7F62368F,0xF3742CA2,0x7F4DE451, +0xF2AC246E,0x7F3857F6,0xF1E43D1C,0x7F2191B4,0xF11C789A,0x7F0991C4,0xF054D8D5, +0x7EF05860,0xEF8D5FB8,0x7ED5E5C6,0xEEC60F31,0x7EBA3A39,0xEDFEE92B,0x7E9D55FC, +0xED37EF91,0x7E7F3957,0xEC71244F,0x7E5FE493,0xEBAA894F,0x7E3F57FF,0xEAE4207A, +0x7E1D93EA,0xEA1DEBBB,0x7DFA98A8,0xE957ECFB,0x7DD6668F,0xE8922622,0x7DB0FDF8, +0xE7CC9917,0x7D8A5F40,0xE70747C4,0x7D628AC6,0xE642340D,0x7D3980EC,0xE57D5FDA, +0x7D0F4218,0xE4B8CD11,0x7CE3CEB2,0xE3F47D96,0x7CB72724,0xE330734D,0x7C894BDE, +0xE26CB01B,0x7C5A3D50,0xE1A935E2,0x7C29FBEE,0xE0E60685,0x7BF88830,0xE02323E5, +0x7BC5E290,0xDF608FE4,0x7B920B89,0xDE9E4C60,0x7B5D039E,0xDDDC5B3B,0x7B26CB4F, +0xDD1ABE51,0x7AEF6323,0xDC597781,0x7AB6CBA4,0xDB9888A8,0x7A7D055B,0xDAD7F3A2, +0x7A4210D8,0xDA17BA4A,0x7A05EEAD,0xD957DE7A,0x79C89F6E,0xD898620C,0x798A23B1, +0xD7D946D8,0x794A7C12,0xD71A8EB5,0x7909A92D,0xD65C3B7B,0x78C7ABA2,0xD59E4EFF, +0x78848414,0xD4E0CB15,0x78403329,0xD423B191,0x77FAB989,0xD3670446,0x77B417DF, +0xD2AAC504,0x776C4EDB,0xD1EEF59E,0x77235F2D,0xD13397E2,0x76D94989,0xD078AD9E, +0x768E0EA6,0xCFBE389F,0x7641AF3D,0xCF043AB3,0x75F42C0B,0xCE4AB5A2,0x75A585CF, +0xCD91AB39,0x7555BD4C,0xCCD91D3D,0x7504D345,0xCC210D79,0x74B2C884,0xCB697DB0, +0x745F9DD1,0xCAB26FA9,0x740B53FB,0xC9FBE527,0x73B5EBD1,0xC945DFEC,0x735F6626, +0xC89061BA,0x7307C3D0,0xC7DB6C50,0x72AF05A7,0xC727016D,0x72552C85,0xC67322CE, +0x71FA3949,0xC5BFD22E,0x719E2CD2,0xC50D1149,0x71410805,0xC45AE1D7,0x70E2CBC6, +0xC3A94590,0x708378FF,0xC2F83E2A,0x7023109A,0xC247CD5A,0x6FC19385,0xC197F4D4, +0x6F5F02B2,0xC0E8B648,0x6EFB5F12,0xC03A1368,0x6E96A99D,0xBF8C0DE3,0x6E30E34A, +0xBEDEA765,0x6DCA0D14,0xBE31E19B,0x6D6227FA,0xBD85BE30,0x6CF934FC,0xBCDA3ECB, +0x6C8F351C,0xBC2F6513,0x6C242960,0xBB8532B0,0x6BB812D1,0xBADBA943,0x6B4AF279, +0xBA32CA71,0x6ADCC964,0xB98A97D8,0x6A6D98A4,0xB8E31319,0x69FD614A,0xB83C3DD1, +0x698C246C,0xB796199B,0x6919E320,0xB6F0A812,0x68A69E81,0xB64BEACD,0x683257AB, +0xB5A7E362,0x67BD0FBD,0xB5049368,0x6746C7D8,0xB461FC70,0x66CF8120,0xB3C0200C, +0x66573CBB,0xB31EFFCC,0x65DDFBD3,0xB27E9D3C,0x6563BF92,0xB1DEF9E9,0x64E88926, +0xB140175B,0x646C59BF,0xB0A1F71D,0x63EF3290,0xB0049AB3,0x637114CC,0xAF6803A2, +0x62F201AC,0xAECC336C,0x6271FA69,0xAE312B92,0x61F1003F,0xAD96ED92,0x616F146C, +0xACFD7AE8,0x60EC3830,0xAC64D510,0x60686CCF,0xABCCFD83,0x5FE3B38D,0xAB35F5B5, +0x5F5E0DB3,0xAA9FBF1E,0x5ED77C8A,0xAA0A5B2E,0x5E50015D,0xA975CB57,0x5DC79D7C, +0xA8E21106,0x5D3E5237,0xA84F2DAA,0x5CB420E0,0xA7BD22AC,0x5C290ACC,0xA72BF174, +0x5B9D1154,0xA69B9B68,0x5B1035CF,0xA60C21EE,0x5A82799A,0xA57D8666,0x59F3DE12, +0xA4EFCA31,0x59646498,0xA462EEAC,0x58D40E8C,0xA3D6F534,0x5842DD54,0xA34BDF20, +0x57B0D256,0xA2C1ADC9,0x571DEEFA,0xA2386284,0x568A34A9,0xA1AFFEA3,0x55F5A4D2, +0xA1288376,0x556040E2,0xA0A1F24D,0x54CA0A4B,0xA01C4C73,0x5433027D,0x9F979331, +0x539B2AF0,0x9F13C7D0,0x53028518,0x9E90EB94,0x5269126E,0x9E0EFFC1,0x51CED46E, +0x9D8E0597,0x5133CC94,0x9D0DFE54,0x5097FC5E,0x9C8EEB34,0x4FFB654D,0x9C10CD70, +0x4F5E08E3,0x9B93A641,0x4EBFE8A5,0x9B1776DA,0x4E210617,0x9A9C406E,0x4D8162C4, +0x9A22042D,0x4CE10034,0x99A8C345,0x4C3FDFF4,0x99307EE0,0x4B9E0390,0x98B93828, +0x4AFB6C98,0x9842F043,0x4A581C9E,0x97CDA855,0x49B41533,0x9759617F,0x490F57EE, +0x96E61CE0,0x4869E665,0x9673DB94,0x47C3C22F,0x96029EB6,0x471CECE7,0x9592675C, +0x46756828,0x9523369C,0x45CD358F,0x94B50D87,0x452456BD,0x9447ED2F,0x447ACD50, +0x93DBD6A0,0x43D09AED,0x9370CAE4,0x4325C135,0x9306CB04,0x427A41D0,0x929DD806, +0x41CE1E65,0x9235F2EC,0x4121589B,0x91CF1CB6,0x4073F21D,0x91695663,0x3FC5EC98, +0x9104A0EE,0x3F1749B8,0x90A0FD4E,0x3E680B2C,0x903E6C7B,0x3DB832A6,0x8FDCEF66, +0x3D07C1D6,0x8F7C8701,0x3C56BA70,0x8F1D343A,0x3BA51E29,0x8EBEF7FB,0x3AF2EEB7, +0x8E61D32E,0x3A402DD2,0x8E05C6B7,0x398CDD32,0x8DAAD37B,0x38D8FE93,0x8D50FA59, +0x382493B0,0x8CF83C30,0x376F9E46,0x8CA099DA,0x36BA2014,0x8C4A142F,0x36041AD9, +0x8BF4AC05,0x354D9057,0x8BA0622F,0x34968250,0x8B4D377C,0x33DEF287,0x8AFB2CBB, +0x3326E2C3,0x8AAA42B4,0x326E54C7,0x8A5A7A31,0x31B54A5E,0x8A0BD3F5,0x30FBC54D, +0x89BE50C3,0x3041C761,0x8971F15A,0x2F875262,0x8926B677,0x2ECC681E,0x88DCA0D3, +0x2E110A62,0x8893B125,0x2D553AFC,0x884BE821,0x2C98FBBA,0x88054677,0x2BDC4E6F, +0x87BFCCD7,0x2B1F34EB,0x877B7BEC,0x2A61B101,0x8738545E,0x29A3C485,0x86F656D3, +0x28E5714B,0x86B583EE,0x2826B928,0x8675DC4F,0x27679DF4,0x86376092,0x26A82186, +0x85FA1153,0x25E845B6,0x85BDEF28,0x25280C5E,0x8582FAA5,0x24677758,0x8549345C, +0x23A6887F,0x85109CDD,0x22E541AF,0x84D934B1,0x2223A4C5,0x84A2FC62,0x2161B3A0, +0x846DF477,0x209F701C,0x843A1D70,0x1FDCDC1B,0x840777D0,0x1F19F97B,0x83D60412, +0x1E56CA1E,0x83A5C2B0,0x1D934FE5,0x8376B422,0x1CCF8CB3,0x8348D8DC,0x1C0B826A, +0x831C314E,0x1B4732EF,0x82F0BDE8,0x1A82A026,0x82C67F14,0x19BDCBF3,0x829D753A, +0x18F8B83C,0x8275A0C0,0x183366E9,0x824F0208,0x176DD9DE,0x82299971,0x16A81305, +0x82056758,0x15E21445,0x81E26C16,0x151BDF86,0x81C0A801,0x145576B1,0x81A01B6D, +0x138EDBB1,0x8180C6A9,0x12C8106F,0x8162AA04,0x120116D5,0x8145C5C7,0x1139F0CF, +0x812A1A3A,0x1072A048,0x810FA7A0,0x0FAB272B,0x80F66E3C,0x0EE38766,0x80DE6E4C, +0x0E1BC2E4,0x80C7A80A,0x0D53DB92,0x80B21BAF,0x0C8BD35E,0x809DC971,0x0BC3AC35, +0x808AB180,0x0AFB6805,0x8078D40D,0x0A3308BD,0x80683143,0x096A9049,0x8058C94C, +0x08A2009A,0x804A9C4D,0x07D95B9E,0x803DAA6A,0x0710A345,0x8031F3C2,0x0647D97C, +0x80277872,0x057F0035,0x801E3895,0x04B6195D,0x80163440,0x03ED26E6,0x800F6B88, +0x03242ABF,0x8009DE7E,0x025B26D7,0x80058D2F,0x01921D20,0x800277A6,0x00C90F88, +0x80009DEA,0x7FFFFFFF,0x00000000,0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684, +0x7FA736B4,0xF6956FB7,0x7F62368F,0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC, +0xED37EF91,0x7E1D93EA,0xEA1DEBBB,0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96, +0x7C29FBEE,0xE0E60685,0x7B5D039E,0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1, +0xD7D946D8,0x78848414,0xD4E0CB15,0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3, +0x7504D345,0xCC210D79,0x73B5EBD1,0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6, +0xC3A94590,0x6F5F02B2,0xC0E8B648,0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0, +0x6A6D98A4,0xB8E31319,0x68A69E81,0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926, +0xB140175B,0x62F201AC,0xAECC336C,0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E, +0x5CB420E0,0xA7BD22AC,0x5A82799A,0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2, +0xA1288376,0x539B2AF0,0x9F13C7D0,0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA, +0x4C3FDFF4,0x99307EE0,0x49B41533,0x9759617F,0x471CECE7,0x9592675C,0x447ACD50, +0x93DBD6A0,0x41CE1E65,0x9235F2EC,0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A, +0x398CDD32,0x8DAAD37B,0x36BA2014,0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D, +0x89BE50C3,0x2E110A62,0x8893B125,0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F, +0x25280C5E,0x8582FAA5,0x2223A4C5,0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A, +0x831C314E,0x18F8B83C,0x8275A0C0,0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04, +0x0FAB272B,0x80F66E3C,0x0C8BD35E,0x809DC971,0x096A9049,0x8058C94C,0x0647D97C, +0x80277872,0x03242ABF,0x8009DE7E,0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2, +0x7D8A5F40,0xE70747C4,0x7A7D055B,0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6, +0xC3A94590,0x6A6D98A4,0xB8E31319,0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666, +0x5133CC94,0x9D0DFE54,0x471CECE7,0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D, +0x89BE50C3,0x25280C5E,0x8582FAA5,0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971, +0x7FFFFFFF,0x00000000,0x7641AF3D,0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D, +0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFD885A,0xFE6DE2E0,0x7FF62182,0xFCDBD541,0x7FE9CBC0, +0xFB49E6A3,0x7FD8878E,0xF9B82684,0x7FC25596,0xF826A462,0x7FA736B4,0xF6956FB7, +0x7F872BF3,0xF50497FB,0x7F62368F,0xF3742CA2,0x7F3857F6,0xF1E43D1C,0x7F0991C4, +0xF054D8D5,0x7ED5E5C6,0xEEC60F31,0x7E9D55FC,0xED37EF91,0x7E5FE493,0xEBAA894F, +0x7E1D93EA,0xEA1DEBBB,0x7DD6668F,0xE8922622,0x7D8A5F40,0xE70747C4,0x7D3980EC, +0xE57D5FDA,0x7CE3CEB2,0xE3F47D96,0x7C894BDE,0xE26CB01B,0x7C29FBEE,0xE0E60685, +0x7BC5E290,0xDF608FE4,0x7B5D039E,0xDDDC5B3B,0x7AEF6323,0xDC597781,0x7A7D055B, +0xDAD7F3A2,0x7A05EEAD,0xD957DE7A,0x798A23B1,0xD7D946D8,0x7909A92D,0xD65C3B7B, +0x78848414,0xD4E0CB15,0x77FAB989,0xD3670446,0x776C4EDB,0xD1EEF59E,0x76D94989, +0xD078AD9E,0x7641AF3D,0xCF043AB3,0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79, +0x745F9DD1,0xCAB26FA9,0x73B5EBD1,0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85, +0xC67322CE,0x719E2CD2,0xC50D1149,0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A, +0x6F5F02B2,0xC0E8B648,0x6E96A99D,0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC, +0xBCDA3ECB,0x6C242960,0xBB8532B0,0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319, +0x698C246C,0xB796199B,0x68A69E81,0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120, +0xB3C0200C,0x65DDFBD3,0xB27E9D3C,0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3, +0x62F201AC,0xAECC336C,0x61F1003F,0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D, +0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E,0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC, +0x5B9D1154,0xA69B9B68,0x5A82799A,0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54, +0xA34BDF20,0x571DEEFA,0xA2386284,0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73, +0x539B2AF0,0x9F13C7D0,0x5269126E,0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D, +0x9C10CD70,0x4EBFE8A5,0x9B1776DA,0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0, +0x4AFB6C98,0x9842F043,0x49B41533,0x9759617F,0x4869E665,0x9673DB94,0x471CECE7, +0x9592675C,0x45CD358F,0x94B50D87,0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04, +0x41CE1E65,0x9235F2EC,0x4073F21D,0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6, +0x8FDCEF66,0x3C56BA70,0x8F1D343A,0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B, +0x382493B0,0x8CF83C30,0x36BA2014,0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287, +0x8AFB2CBB,0x326E54C7,0x8A5A7A31,0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677, +0x2E110A62,0x8893B125,0x2C98FBBA,0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485, +0x86F656D3,0x2826B928,0x8675DC4F,0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5, +0x23A6887F,0x85109CDD,0x2223A4C5,0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B, +0x83D60412,0x1D934FE5,0x8376B422,0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14, +0x18F8B83C,0x8275A0C0,0x176DD9DE,0x82299971,0x15E21445,0x81E26C16,0x145576B1, +0x81A01B6D,0x12C8106F,0x8162AA04,0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C, +0x0E1BC2E4,0x80C7A80A,0x0C8BD35E,0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049, +0x8058C94C,0x07D95B9E,0x803DAA6A,0x0647D97C,0x80277872,0x04B6195D,0x80163440, +0x03242ABF,0x8009DE7E,0x01921D20,0x800277A6,0x00000000,0x80000000,0xFE6DE2E0, +0x800277A6,0xFCDBD541,0x8009DE7E,0xFB49E6A3,0x80163440,0xF9B82684,0x80277872, +0xF826A462,0x803DAA6A,0xF6956FB7,0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2, +0x809DC971,0xF1E43D1C,0x80C7A80A,0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A, +0xED37EF91,0x8162AA04,0xEBAA894F,0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622, +0x82299971,0xE70747C4,0x8275A0C0,0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E, +0xE26CB01B,0x8376B422,0xE0E60685,0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B, +0x84A2FC62,0xDC597781,0x85109CDD,0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153, +0xD7D946D8,0x8675DC4F,0xD65C3B7B,0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446, +0x88054677,0xD1EEF59E,0x8893B125,0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3, +0xCD91AB39,0x8A5A7A31,0xCC210D79,0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC, +0x8C4A142F,0xC7DB6C50,0x8CF83C30,0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E, +0xC3A94590,0x8F1D343A,0xC247CD5A,0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3, +0x91695663,0xBE31E19B,0x9235F2EC,0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0, +0xBA32CA71,0x94B50D87,0xB8E31319,0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD, +0x9759617F,0xB5049368,0x9842F043,0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D, +0xB140175B,0x9B1776DA,0xB0049AB3,0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92, +0x9E0EFFC1,0xAC64D510,0x9F13C7D0,0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376, +0xA8E21106,0xA2386284,0xA7BD22AC,0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666, +0xA57D8666,0xA462EEAC,0xA69B9B68,0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106, +0xA1288376,0xAA0A5B2E,0xA01C4C73,0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1, +0xAD96ED92,0x9D0DFE54,0xAECC336C,0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B, +0x9A22042D,0xB27E9D3C,0x99307EE0,0xB3C0200C,0x9842F043,0xB5049368,0x9759617F, +0xB64BEACD,0x9673DB94,0xB796199B,0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71, +0x93DBD6A0,0xBB8532B0,0x9306CB04,0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663, +0xBF8C0DE3,0x90A0FD4E,0xC0E8B648,0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590, +0x8E61D32E,0xC50D1149,0x8DAAD37B,0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F, +0xC945DFEC,0x8BA0622F,0xCAB26FA9,0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39, +0x89BE50C3,0xCF043AB3,0x8926B677,0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677, +0xD3670446,0x877B7BEC,0xD4E0CB15,0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8, +0x85FA1153,0xD957DE7A,0x8582FAA5,0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62, +0xDDDC5B3B,0x843A1D70,0xDF608FE4,0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B, +0x831C314E,0xE3F47D96,0x82C67F14,0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971, +0xE8922622,0x81E26C16,0xEA1DEBBB,0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91, +0x812A1A3A,0xEEC60F31,0x80F66E3C,0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971, +0xF3742CA2,0x8078D40D,0xF50497FB,0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462, +0x80277872,0xF9B82684,0x80163440,0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6, +0xFE6DE2E0,0x7FFFFFFF,0x00000000,0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2, +0x7E9D55FC,0xED37EF91,0x7D8A5F40,0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B, +0xDAD7F3A2,0x78848414,0xD4E0CB15,0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC, +0x70E2CBC6,0xC3A94590,0x6DCA0D14,0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120, +0xB3C0200C,0x62F201AC,0xAECC336C,0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666, +0x55F5A4D2,0xA1288376,0x5133CC94,0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7, +0x9592675C,0x41CE1E65,0x9235F2EC,0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F, +0x30FBC54D,0x89BE50C3,0x2B1F34EB,0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B, +0x83D60412,0x18F8B83C,0x8275A0C0,0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971, +0x0647D97C,0x80277872,0x00000000,0x80000000,0xF9B82684,0x80277872,0xF3742CA2, +0x809DC971,0xED37EF91,0x8162AA04,0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412, +0xDAD7F3A2,0x8582FAA5,0xD4E0CB15,0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC, +0x8C4A142F,0xC3A94590,0x8F1D343A,0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C, +0xB3C0200C,0x99307EE0,0xAECC336C,0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666, +0xA57D8666,0xA1288376,0xAA0A5B2E,0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C, +0x9592675C,0xB8E31319,0x9235F2EC,0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F, +0xC945DFEC,0x89BE50C3,0xCF043AB3,0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2, +0x83D60412,0xE0E60685,0x8275A0C0,0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971, +0xF3742CA2,0x80277872,0xF9B82684,0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4, +0x7641AF3D,0xCF043AB3,0x6A6D98A4,0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7, +0x9592675C,0x30FBC54D,0x89BE50C3,0x18F8B83C,0x8275A0C0,0x00000000,0x80000000, +0xE70747C4,0x8275A0C0,0xCF043AB3,0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666, +0xA57D8666,0x9592675C,0xB8E31319,0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4, +0x7FFFFFFF,0x00000000,0x5A82799A,0xA57D8666,0x00000000,0x80000000,0xA57D8666, +0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_1024_q31[680]={ +0x7FFFFFFF,0x00000000,0x7FFA72D1,0xFDA4D929,0x7FE9CBC0,0xFB49E6A3,0x7FCE0C3E, +0xF8EF5CBB,0x7FA736B4,0xF6956FB7,0x7F754E80,0xF43C53CB,0x7F3857F6,0xF1E43D1C, +0x7EF05860,0xEF8D5FB8,0x7E9D55FC,0xED37EF91,0x7E3F57FF,0xEAE4207A,0x7DD6668F, +0xE8922622,0x7D628AC6,0xE642340D,0x7CE3CEB2,0xE3F47D96,0x7C5A3D50,0xE1A935E2, +0x7BC5E290,0xDF608FE4,0x7B26CB4F,0xDD1ABE51,0x7A7D055B,0xDAD7F3A2,0x79C89F6E, +0xD898620C,0x7909A92D,0xD65C3B7B,0x78403329,0xD423B191,0x776C4EDB,0xD1EEF59E, +0x768E0EA6,0xCFBE389F,0x75A585CF,0xCD91AB39,0x74B2C884,0xCB697DB0,0x73B5EBD1, +0xC945DFEC,0x72AF05A7,0xC727016D,0x719E2CD2,0xC50D1149,0x708378FF,0xC2F83E2A, +0x6F5F02B2,0xC0E8B648,0x6E30E34A,0xBEDEA765,0x6CF934FC,0xBCDA3ECB,0x6BB812D1, +0xBADBA943,0x6A6D98A4,0xB8E31319,0x6919E320,0xB6F0A812,0x67BD0FBD,0xB5049368, +0x66573CBB,0xB31EFFCC,0x64E88926,0xB140175B,0x637114CC,0xAF6803A2,0x61F1003F, +0xAD96ED92,0x60686CCF,0xABCCFD83,0x5ED77C8A,0xAA0A5B2E,0x5D3E5237,0xA84F2DAA, +0x5B9D1154,0xA69B9B68,0x59F3DE12,0xA4EFCA31,0x5842DD54,0xA34BDF20,0x568A34A9, +0xA1AFFEA3,0x54CA0A4B,0xA01C4C73,0x53028518,0x9E90EB94,0x5133CC94,0x9D0DFE54, +0x4F5E08E3,0x9B93A641,0x4D8162C4,0x9A22042D,0x4B9E0390,0x98B93828,0x49B41533, +0x9759617F,0x47C3C22F,0x96029EB6,0x45CD358F,0x94B50D87,0x43D09AED,0x9370CAE4, +0x41CE1E65,0x9235F2EC,0x3FC5EC98,0x9104A0EE,0x3DB832A6,0x8FDCEF66,0x3BA51E29, +0x8EBEF7FB,0x398CDD32,0x8DAAD37B,0x376F9E46,0x8CA099DA,0x354D9057,0x8BA0622F, +0x3326E2C3,0x8AAA42B4,0x30FBC54D,0x89BE50C3,0x2ECC681E,0x88DCA0D3,0x2C98FBBA, +0x88054677,0x2A61B101,0x8738545E,0x2826B928,0x8675DC4F,0x25E845B6,0x85BDEF28, +0x23A6887F,0x85109CDD,0x2161B3A0,0x846DF477,0x1F19F97B,0x83D60412,0x1CCF8CB3, +0x8348D8DC,0x1A82A026,0x82C67F14,0x183366E9,0x824F0208,0x15E21445,0x81E26C16, +0x138EDBB1,0x8180C6A9,0x1139F0CF,0x812A1A3A,0x0EE38766,0x80DE6E4C,0x0C8BD35E, +0x809DC971,0x0A3308BD,0x80683143,0x07D95B9E,0x803DAA6A,0x057F0035,0x801E3895, +0x03242ABF,0x8009DE7E,0x00C90F88,0x80009DEA,0xFE6DE2E0,0x800277A6,0xFC12D91A, +0x800F6B88,0xF9B82684,0x80277872,0xF75DFF66,0x804A9C4D,0xF50497FB,0x8078D40D, +0xF2AC246E,0x80B21BAF,0xF054D8D5,0x80F66E3C,0xEDFEE92B,0x8145C5C7,0xEBAA894F, +0x81A01B6D,0xE957ECFB,0x82056758,0xE70747C4,0x8275A0C0,0xE4B8CD11,0x82F0BDE8, +0xE26CB01B,0x8376B422,0xE02323E5,0x840777D0,0xDDDC5B3B,0x84A2FC62,0xDB9888A8, +0x8549345C,0xD957DE7A,0x85FA1153,0xD71A8EB5,0x86B583EE,0xD4E0CB15,0x877B7BEC, +0xD2AAC504,0x884BE821,0xD078AD9E,0x8926B677,0xCE4AB5A2,0x8A0BD3F5,0xCC210D79, +0x8AFB2CBB,0xC9FBE527,0x8BF4AC05,0xC7DB6C50,0x8CF83C30,0xC5BFD22E,0x8E05C6B7, +0xC3A94590,0x8F1D343A,0xC197F4D4,0x903E6C7B,0xBF8C0DE3,0x91695663,0xBD85BE30, +0x929DD806,0xBB8532B0,0x93DBD6A0,0xB98A97D8,0x9523369C,0xB796199B,0x9673DB94, +0xB5A7E362,0x97CDA855,0xB3C0200C,0x99307EE0,0xB1DEF9E9,0x9A9C406E,0xB0049AB3, +0x9C10CD70,0xAE312B92,0x9D8E0597,0xAC64D510,0x9F13C7D0,0xAA9FBF1E,0xA0A1F24D, +0xA8E21106,0xA2386284,0xA72BF174,0xA3D6F534,0xA57D8666,0xA57D8666,0xA3D6F534, +0xA72BF174,0xA2386284,0xA8E21106,0xA0A1F24D,0xAA9FBF1E,0x9F13C7D0,0xAC64D510, +0x9D8E0597,0xAE312B92,0x9C10CD70,0xB0049AB3,0x9A9C406E,0xB1DEF9E9,0x99307EE0, +0xB3C0200C,0x97CDA855,0xB5A7E362,0x9673DB94,0xB796199B,0x9523369C,0xB98A97D8, +0x93DBD6A0,0xBB8532B0,0x929DD806,0xBD85BE30,0x91695663,0xBF8C0DE3,0x903E6C7B, +0xC197F4D4,0x8F1D343A,0xC3A94590,0x8E05C6B7,0xC5BFD22E,0x8CF83C30,0xC7DB6C50, +0x8BF4AC05,0xC9FBE527,0x8AFB2CBB,0xCC210D79,0x8A0BD3F5,0xCE4AB5A2,0x8926B677, +0xD078AD9E,0x884BE821,0xD2AAC504,0x877B7BEC,0xD4E0CB15,0x86B583EE,0xD71A8EB5, +0x85FA1153,0xD957DE7A,0x8549345C,0xDB9888A8,0x84A2FC62,0xDDDC5B3B,0x840777D0, +0xE02323E5,0x8376B422,0xE26CB01B,0x82F0BDE8,0xE4B8CD11,0x8275A0C0,0xE70747C4, +0x82056758,0xE957ECFB,0x81A01B6D,0xEBAA894F,0x8145C5C7,0xEDFEE92B,0x80F66E3C, +0xF054D8D5,0x80B21BAF,0xF2AC246E,0x8078D40D,0xF50497FB,0x804A9C4D,0xF75DFF66, +0x80277872,0xF9B82684,0x800F6B88,0xFC12D91A,0x800277A6,0xFE6DE2E0,0x80009DEA, +0x00C90F88,0x8009DE7E,0x03242ABF,0x801E3895,0x057F0035,0x803DAA6A,0x07D95B9E, +0x80683143,0x0A3308BD,0x809DC971,0x0C8BD35E,0x80DE6E4C,0x0EE38766,0x812A1A3A, +0x1139F0CF,0x8180C6A9,0x138EDBB1,0x81E26C16,0x15E21445,0x824F0208,0x183366E9, +0x82C67F14,0x1A82A026,0x8348D8DC,0x1CCF8CB3,0x83D60412,0x1F19F97B,0x846DF477, +0x2161B3A0,0x85109CDD,0x23A6887F,0x85BDEF28,0x25E845B6,0x8675DC4F,0x2826B928, +0x8738545E,0x2A61B101,0x88054677,0x2C98FBBA,0x88DCA0D3,0x2ECC681E,0x89BE50C3, +0x30FBC54D,0x8AAA42B4,0x3326E2C3,0x8BA0622F,0x354D9057,0x8CA099DA,0x376F9E46, +0x8DAAD37B,0x398CDD32,0x8EBEF7FB,0x3BA51E29,0x8FDCEF66,0x3DB832A6,0x9104A0EE, +0x3FC5EC98,0x9235F2EC,0x41CE1E65,0x9370CAE4,0x43D09AED,0x94B50D87,0x45CD358F, +0x96029EB6,0x47C3C22F,0x9759617F,0x49B41533,0x98B93828,0x4B9E0390,0x9A22042D, +0x4D8162C4,0x9B93A641,0x4F5E08E3,0x9D0DFE54,0x5133CC94,0x9E90EB94,0x53028518, +0xA01C4C73,0x54CA0A4B,0xA1AFFEA3,0x568A34A9,0xA34BDF20,0x5842DD54,0xA4EFCA31, +0x59F3DE12,0xA69B9B68,0x5B9D1154,0xA84F2DAA,0x5D3E5237,0xAA0A5B2E,0x5ED77C8A, +0xABCCFD83,0x60686CCF,0xAD96ED92,0x61F1003F,0xAF6803A2,0x637114CC,0xB140175B, +0x64E88926,0xB31EFFCC,0x66573CBB,0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320, +0xB8E31319,0x6A6D98A4,0xBADBA943,0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765, +0x6E30E34A,0xC0E8B648,0x6F5F02B2,0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2, +0xC727016D,0x72AF05A7,0xC945DFEC,0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39, +0x75A585CF,0xCFBE389F,0x768E0EA6,0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329, +0xD65C3B7B,0x7909A92D,0xD898620C,0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51, +0x7B26CB4F,0xDF608FE4,0x7BC5E290,0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2, +0xE642340D,0x7D628AC6,0xE8922622,0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91, +0x7E9D55FC,0xEF8D5FB8,0x7EF05860,0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80, +0xF6956FB7,0x7FA736B4,0xF8EF5CBB,0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929, +0x7FFA72D1,0x7FFFFFFF,0x00000000,0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91, +0x7CE3CEB2,0xE3F47D96,0x7A7D055B,0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1, +0xC945DFEC,0x6F5F02B2,0xC0E8B648,0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B, +0x5ED77C8A,0xAA0A5B2E,0x5842DD54,0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533, +0x9759617F,0x41CE1E65,0x9235F2EC,0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3, +0x2826B928,0x8675DC4F,0x1F19F97B,0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E, +0x809DC971,0x03242ABF,0x8009DE7E,0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C, +0xE70747C4,0x8275A0C0,0xDDDC5B3B,0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79, +0x8AFB2CBB,0xC3A94590,0x8F1D343A,0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0, +0xAC64D510,0x9F13C7D0,0xA57D8666,0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0, +0xB3C0200C,0x93DBD6A0,0xBB8532B0,0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79, +0x877B7BEC,0xD4E0CB15,0x84A2FC62,0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C, +0xF054D8D5,0x80277872,0xF9B82684,0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E, +0x81E26C16,0x15E21445,0x83D60412,0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3, +0x30FBC54D,0x8DAAD37B,0x398CDD32,0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533, +0x9D0DFE54,0x5133CC94,0xA34BDF20,0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B, +0x64E88926,0xB8E31319,0x6A6D98A4,0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1, +0xD1EEF59E,0x776C4EDB,0xDAD7F3A2,0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91, +0x7E9D55FC,0xF6956FB7,0x7FA736B4,0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2, +0x6A6D98A4,0xB8E31319,0x5133CC94,0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E, +0x809DC971,0xE70747C4,0x8275A0C0,0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666, +0x8F1D343A,0xC3A94590,0x8275A0C0,0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3, +0x30FBC54D,0x9D0DFE54,0x5133CC94,0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B, +0x7FFFFFFF,0x00000000,0x30FBC54D,0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3, +0x30FBC54D,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]={ +0,2048,2560,2688,2720,0,}; + +q31_t rearranged_twiddle_stride1_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFF621,0xFFCDBC0B,0x7FFFD886,0xFF9B781D,0x7FFFA72C, +0xFF69343F,0x7FFF6216,0xFF36F078,0x7FFF0943,0xFF04ACD0,0x7FFE9CB2,0xFED2694F, +0x7FFE1C65,0xFEA025FD,0x7FFD885A,0xFE6DE2E0,0x7FFCE093,0xFE3BA002,0x7FFC250F, +0xFE095D69,0x7FFB55CE,0xFDD71B1E,0x7FFA72D1,0xFDA4D929,0x7FF97C18,0xFD729790, +0x7FF871A2,0xFD40565C,0x7FF75370,0xFD0E1594,0x7FF62182,0xFCDBD541,0x7FF4DBD9, +0xFCA9956A,0x7FF38274,0xFC775616,0x7FF21553,0xFC45174E,0x7FF09478,0xFC12D91A, +0x7FEEFFE1,0xFBE09B80,0x7FED5791,0xFBAE5E89,0x7FEB9B85,0xFB7C223D,0x7FE9CBC0, +0xFB49E6A3,0x7FE7E841,0xFB17ABC2,0x7FE5F108,0xFAE571A4,0x7FE3E616,0xFAB3384F, +0x7FE1C76B,0xFA80FFCB,0x7FDF9508,0xFA4EC821,0x7FDD4EEC,0xFA1C9157,0x7FDAF519, +0xF9EA5B75,0x7FD8878E,0xF9B82684,0x7FD6064C,0xF985F28A,0x7FD37153,0xF953BF91, +0x7FD0C8A3,0xF9218D9E,0x7FCE0C3E,0xF8EF5CBB,0x7FCB3C23,0xF8BD2CEF,0x7FC85854, +0xF88AFE42,0x7FC560CF,0xF858D0BB,0x7FC25596,0xF826A462,0x7FBF36AA,0xF7F4793E, +0x7FBC040A,0xF7C24F59,0x7FB8BDB8,0xF79026B9,0x7FB563B3,0xF75DFF66,0x7FB1F5FC, +0xF72BD967,0x7FAE7495,0xF6F9B4C6,0x7FAADF7C,0xF6C79188,0x7FA736B4,0xF6956FB7, +0x7FA37A3C,0xF6634F59,0x7F9FAA15,0xF6313077,0x7F9BC640,0xF5FF1318,0x7F97CEBD, +0xF5CCF743,0x7F93C38C,0xF59ADD02,0x7F8FA4B0,0xF568C45B,0x7F8B7227,0xF536AD56, +0x7F872BF3,0xF50497FB,0x7F82D214,0xF4D28451,0x7F7E648C,0xF4A07261,0x7F79E35A, +0xF46E6231,0x7F754E80,0xF43C53CB,0x7F70A5FE,0xF40A4735,0x7F6BE9D4,0xF3D83C77, +0x7F671A05,0xF3A63398,0x7F62368F,0xF3742CA2,0x7F5D3F75,0xF342279B,0x7F5834B7, +0xF310248A,0x7F531655,0xF2DE2379,0x7F4DE451,0xF2AC246E,0x7F489EAA,0xF27A2771, +0x7F434563,0xF2482C8A,0x7F3DD87C,0xF21633C0,0x7F3857F6,0xF1E43D1C,0x7F32C3D1, +0xF1B248A5,0x7F2D1C0E,0xF1805662,0x7F2760AF,0xF14E665C,0x7F2191B4,0xF11C789A, +0x7F1BAF1E,0xF0EA8D24,0x7F15B8EE,0xF0B8A401,0x7F0FAF25,0xF086BD39,0x7F0991C4, +0xF054D8D5,0x7F0360CB,0xF022F6DA,0x7EFD1C3C,0xEFF11753,0x7EF6C418,0xEFBF3A45, +0x7EF05860,0xEF8D5FB8,0x7EE9D914,0xEF5B87B5,0x7EE34636,0xEF29B243,0x7EDC9FC6, +0xEEF7DF6A,0x7ED5E5C6,0xEEC60F31,0x7ECF1837,0xEE9441A0,0x7EC8371A,0xEE6276BF, +0x7EC14270,0xEE30AE96,0x7EBA3A39,0xEDFEE92B,0x7EB31E78,0xEDCD2687,0x7EABEF2C, +0xED9B66B2,0x7EA4AC58,0xED69A9B3,0x7E9D55FC,0xED37EF91,0x7E95EC1A,0xED063856, +0x7E8E6EB2,0xECD48407,0x7E86DDC6,0xECA2D2AD,0x7E7F3957,0xEC71244F,0x7E778166, +0xEC3F78F6,0x7E6FB5F4,0xEC0DD0A8,0x7E67D703,0xEBDC2B6E,0x7E5FE493,0xEBAA894F, +0x7E57DEA7,0xEB78EA52,0x7E4FC53E,0xEB474E81,0x7E47985B,0xEB15B5E1,0x7E3F57FF, +0xEAE4207A,0x7E37042A,0xEAB28E56,0x7E2E9CDF,0xEA80FF7A,0x7E26221F,0xEA4F73EE, +0x7E1D93EA,0xEA1DEBBB,0x7E14F242,0xE9EC66E8,0x7E0C3D29,0xE9BAE57D,0x7E0374A0, +0xE9896781,0x7DFA98A8,0xE957ECFB,0x7DF1A942,0xE92675F4,0x7DE8A670,0xE8F50273, +0x7DDF9034,0xE8C39280,0x7DD6668F,0xE8922622,0x7DCD2981,0xE860BD61,0x7DC3D90D, +0xE82F5844,0x7DBA7534,0xE7FDF6D4,0x7DB0FDF8,0xE7CC9917,0x7DA77359,0xE79B3F16, +0x7D9DD55A,0xE769E8D8,0x7D9423FC,0xE7389665,0x7D8A5F40,0xE70747C4,0x7D808728, +0xE6D5FCFC,0x7D769BB5,0xE6A4B616,0x7D6C9CE9,0xE6737319,0x7D628AC6,0xE642340D, +0x7D58654D,0xE610F8F9,0x7D4E2C7F,0xE5DFC1E5,0x7D43E05E,0xE5AE8ED8,0x7D3980EC, +0xE57D5FDA,0x7D2F0E2B,0xE54C34F3,0x7D24881B,0xE51B0E2A,0x7D19EEBF,0xE4E9EB87, +0x7D0F4218,0xE4B8CD11,0x7D048228,0xE487B2D0,0x7CF9AEF0,0xE4569CCB,0x7CEEC873, +0xE4258B0A,0x7CE3CEB2,0xE3F47D96,0x7CD8C1AE,0xE3C37474,0x7CCDA169,0xE3926FAD, +0x7CC26DE5,0xE3616F48,0x7CB72724,0xE330734D,0x7CABCD28,0xE2FF7BC3,0x7CA05FF1, +0xE2CE88B3,0x7C94DF83,0xE29D9A23,0x7C894BDE,0xE26CB01B,0x7C7DA505,0xE23BCAA2, +0x7C71EAF9,0xE20AE9C1,0x7C661DBC,0xE1DA0D7E,0x7C5A3D50,0xE1A935E2,0x7C4E49B7, +0xE17862F3,0x7C4242F2,0xE14794BA,0x7C362904,0xE116CB3D,0x7C29FBEE,0xE0E60685, +0x7C1DBBB3,0xE0B54698,0x7C116853,0xE0848B7F,0x7C0501D2,0xE053D541,0x7BF88830, +0xE02323E5,0x7BEBFB70,0xDFF27773,0x7BDF5B94,0xDFC1CFF3,0x7BD2A89E,0xDF912D6B, +0x7BC5E290,0xDF608FE4,0x7BB9096B,0xDF2FF764,0x7BAC1D31,0xDEFF63F4,0x7B9F1DE6, +0xDECED59B,0x7B920B89,0xDE9E4C60,0x7B84E61F,0xDE6DC84B,0x7B77ADA8,0xDE3D4964, +0x7B6A6227,0xDE0CCFB1,0x7B5D039E,0xDDDC5B3B,0x7B4F920E,0xDDABEC08,0x7B420D7A, +0xDD7B8220,0x7B3475E5,0xDD4B1D8C,0x7B26CB4F,0xDD1ABE51,0x7B190DBC,0xDCEA6478, +0x7B0B3D2C,0xDCBA1008,0x7AFD59A4,0xDC89C109,0x7AEF6323,0xDC597781,0x7AE159AE, +0xDC293379,0x7AD33D45,0xDBF8F4F8,0x7AC50DEC,0xDBC8BC06,0x7AB6CBA4,0xDB9888A8, +0x7AA8766F,0xDB685AE9,0x7A9A0E50,0xDB3832CD,0x7A8B9348,0xDB08105E,0x7A7D055B, +0xDAD7F3A2,0x7A6E648A,0xDAA7DCA1,0x7A5FB0D8,0xDA77CB63,0x7A50EA47,0xDA47BFEE, +0x7A4210D8,0xDA17BA4A,0x7A332490,0xD9E7BA7F,0x7A24256F,0xD9B7C094,0x7A151378, +0xD987CC90,0x7A05EEAD,0xD957DE7A,0x79F6B711,0xD927F65B,0x79E76CA7,0xD8F81439, +0x79D80F6F,0xD8C8381D,0x79C89F6E,0xD898620C,0x79B91CA4,0xD868920F,0x79A98715, +0xD838C82D,0x7999DEC4,0xD809046E,0x798A23B1,0xD7D946D8,0x797A55E0,0xD7A98F73, +0x796A7554,0xD779DE47,0x795A820E,0xD74A335B,0x794A7C12,0xD71A8EB5,0x793A6361, +0xD6EAF05F,0x792A37FE,0xD6BB585E,0x7919F9EC,0xD68BC6BA,0x7909A92D,0xD65C3B7B, +0x78F945C3,0xD62CB6A8,0x78E8CFB2,0xD5FD3848,0x78D846FB,0xD5CDC062,0x78C7ABA2, +0xD59E4EFF,0x78B6FDA8,0xD56EE424,0x78A63D11,0xD53F7FDA,0x789569DF,0xD5102228, +0x78848414,0xD4E0CB15,0x78738BB3,0xD4B17AA8,0x786280BF,0xD48230E9,0x7851633B, +0xD452EDDF,0x78403329,0xD423B191,0x782EF08B,0xD3F47C06,0x781D9B65,0xD3C54D47, +0x780C33B8,0xD396255A,0x77FAB989,0xD3670446,0x77E92CD9,0xD337EA12,0x77D78DAA, +0xD308D6C7,0x77C5DC01,0xD2D9CA6A,0x77B417DF,0xD2AAC504,0x77A24148,0xD27BC69C, +0x7790583E,0xD24CCF39,0x777E5CC3,0xD21DDEE2,0x776C4EDB,0xD1EEF59E,0x775A2E89, +0xD1C01375,0x7747FBCE,0xD191386E,0x7735B6AF,0xD1626490,0x77235F2D,0xD13397E2, +0x7710F54C,0xD104D26B,0x76FE790E,0xD0D61434,0x76EBEA77,0xD0A75D42,0x76D94989, +0xD078AD9E,0x76C69647,0xD04A054E,0x76B3D0B4,0xD01B6459,0x76A0F8D2,0xCFECCAC7, +0x768E0EA6,0xCFBE389F,0x767B1231,0xCF8FADE9,0x76680376,0xCF612AAA,0x7654E279, +0xCF32AEEB,0x7641AF3D,0xCF043AB3,0x762E69C4,0xCED5CE08,0x761B1211,0xCEA768F2, +0x7607A828,0xCE790B79,0x75F42C0B,0xCE4AB5A2,0x75E09DBD,0xCE1C6777,0x75CCFD42, +0xCDEE20FC,0x75B94A9C,0xCDBFE23A,0x75A585CF,0xCD91AB39,0x7591AEDD,0xCD637BFE, +0x757DC5CA,0xCD355491,0x7569CA99,0xCD0734F9,0x7555BD4C,0xCCD91D3D,0x75419DE7, +0xCCAB0D65,0x752D6C6C,0xCC7D0578,0x751928E0,0xCC4F057C,0x7504D345,0xCC210D79, +0x74F06B9E,0xCBF31D75,0x74DBF1EF,0xCBC53579,0x74C7663A,0xCB97558A,0x74B2C884, +0xCB697DB0,0x749E18CD,0xCB3BADF3,0x7489571C,0xCB0DE658,0x74748371,0xCAE026E8, +0x745F9DD1,0xCAB26FA9,0x744AA63F,0xCA84C0A3,0x74359CBD,0xCA5719DB,0x74208150, +0xCA297B5A,0x740B53FB,0xC9FBE527,0x73F614C0,0xC9CE5748,0x73E0C3A3,0xC9A0D1C5, +0x73CB60A8,0xC97354A4,0x73B5EBD1,0xC945DFEC,0x73A06522,0xC91873A5,0x738ACC9E, +0xC8EB0FD6,0x73752249,0xC8BDB485,0x735F6626,0xC89061BA,0x73499838,0xC863177B, +0x7333B883,0xC835D5D0,0x731DC70A,0xC8089CBF,0x7307C3D0,0xC7DB6C50,0x72F1AED9, +0xC7AE4489,0x72DB8828,0xC7812572,0x72C54FC1,0xC7540F11,0x72AF05A7,0xC727016D, +0x7298A9DD,0xC6F9FC8D,0x72823C67,0xC6CD0079,0x726BBD48,0xC6A00D37,0x72552C85, +0xC67322CE,0x723E8A20,0xC6464144,0x7227D61C,0xC61968A2,0x7211107E,0xC5EC98EE, +0x71FA3949,0xC5BFD22E,0x71E35080,0xC593146A,0x71CC5626,0xC5665FA9,0x71B54A41, +0xC539B3F1,0x719E2CD2,0xC50D1149,0x7186FDDE,0xC4E077B8,0x716FBD68,0xC4B3E746, +0x71586B74,0xC4875FF9,0x71410805,0xC45AE1D7,0x7129931F,0xC42E6CE8,0x71120CC5, +0xC4020133,0x70FA74FC,0xC3D59EBE,0x70E2CBC6,0xC3A94590,0x70CB1128,0xC37CF5B0, +0x70B34525,0xC350AF26,0x709B67C0,0xC32471F7,0x708378FF,0xC2F83E2A,0x706B78E3, +0xC2CC13C7,0x70536771,0xC29FF2D4,0x703B44AD,0xC273DB58,0x7023109A,0xC247CD5A, +0x700ACB3C,0xC21BC8E1,0x6FF27497,0xC1EFCDF3,0x6FDA0CAE,0xC1C3DC97,0x6FC19385, +0xC197F4D4,0x6FA90921,0xC16C16B0,0x6F906D84,0xC1404233,0x6F77C0B3,0xC1147764, +0x6F5F02B2,0xC0E8B648,0x6F463383,0xC0BCFEE7,0x6F2D532C,0xC0915148,0x6F1461B0, +0xC065AD70,0x6EFB5F12,0xC03A1368,0x6EE24B57,0xC00E8336,0x6EC92683,0xBFE2FCDF, +0x6EAFF099,0xBFB7806C,0x6E96A99D,0xBF8C0DE3,0x6E7D5193,0xBF60A54A,0x6E63E87F, +0xBF3546A8,0x6E4A6E66,0xBF09F205,0x6E30E34A,0xBEDEA765,0x6E174730,0xBEB366D1, +0x6DFD9A1C,0xBE88304F,0x6DE3DC11,0xBE5D03E6,0x6DCA0D14,0xBE31E19B,0x6DB02D29, +0xBE06C977,0x6D963C54,0xBDDBBB7F,0x6D7C3A98,0xBDB0B7BB,0x6D6227FA,0xBD85BE30, +0x6D48047E,0xBD5ACEE5,0x6D2DD027,0xBD2FE9E2,0x6D138AFB,0xBD050F2C,0x6CF934FC, +0xBCDA3ECB,0x6CDECE2F,0xBCAF78C4,0x6CC45698,0xBC84BD1F,0x6CA9CE3B,0xBC5A0BE2, +0x6C8F351C,0xBC2F6513,0x6C748B3F,0xBC04C8BA,0x6C59D0A9,0xBBDA36DD,0x6C3F055D, +0xBBAFAF82,0x6C242960,0xBB8532B0,0x6C093CB6,0xBB5AC06D,0x6BEE3F62,0xBB3058C0, +0x6BD3316A,0xBB05FBB0,0x6BB812D1,0xBADBA943,0x6B9CE39B,0xBAB16180,0x6B81A3CD, +0xBA87246D,0x6B66536B,0xBA5CF210,0x6B4AF279,0xBA32CA71,0x6B2F80FB,0xBA08AD95, +0x6B13FEF5,0xB9DE9B83,0x6AF86C6C,0xB9B49442,0x6ADCC964,0xB98A97D8,0x6AC115E2, +0xB960A64C,0x6AA551E9,0xB936BFA4,0x6A897D7D,0xB90CE3E6,0x6A6D98A4,0xB8E31319, +0x6A51A361,0xB8B94D44,0x6A359DB9,0xB88F926D,0x6A1987B0,0xB865E299,0x69FD614A, +0xB83C3DD1,0x69E12A8C,0xB812A41A,0x69C4E37A,0xB7E9157A,0x69A88C19,0xB7BF91F8, +0x698C246C,0xB796199B,0x696FAC78,0xB76CAC69,0x69532442,0xB7434A67,0x69368BCE, +0xB719F39E,0x6919E320,0xB6F0A812,0x68FD2A3D,0xB6C767CA,0x68E06129,0xB69E32CD, +0x68C387E9,0xB6750921,0x68A69E81,0xB64BEACD,0x6889A4F6,0xB622D7D6,0x686C9B4B, +0xB5F9D043,0x684F8186,0xB5D0D41A,0x683257AB,0xB5A7E362,0x68151DBE,0xB57EFE22, +0x67F7D3C5,0xB556245E,0x67DA79C3,0xB52D561E,0x67BD0FBD,0xB5049368,0x679F95B7, +0xB4DBDC42,0x67820BB7,0xB4B330B3,0x676471C0,0xB48A90C0,0x6746C7D8,0xB461FC70, +0x67290E02,0xB43973CA,0x670B4444,0xB410F6D3,0x66ED6AA1,0xB3E88592,0x66CF8120, +0xB3C0200C,0x66B187C3,0xB397C649,0x66937E91,0xB36F784F,0x6675658C,0xB3473623, +0x66573CBB,0xB31EFFCC,0x66390422,0xB2F6D550,0x661ABBC5,0xB2CEB6B5,0x65FC63A9, +0xB2A6A402,0x65DDFBD3,0xB27E9D3C,0x65BF8447,0xB256A26A,0x65A0FD0B,0xB22EB392, +0x65826622,0xB206D0BA,0x6563BF92,0xB1DEF9E9,0x6545095F,0xB1B72F23,0x6526438F, +0xB18F7071,0x65076E25,0xB167BDD7,0x64E88926,0xB140175B,0x64C99498,0xB1187D05, +0x64AA907F,0xB0F0EEDA,0x648B7CE0,0xB0C96CE0,0x646C59BF,0xB0A1F71D,0x644D2722, +0xB07A8D97,0x642DE50D,0xB0533055,0x640E9386,0xB02BDF5C,0x63EF3290,0xB0049AB3, +0x63CFC231,0xAFDD625F,0x63B0426D,0xAFB63667,0x6390B34A,0xAF8F16D1,0x637114CC, +0xAF6803A2,0x635166F9,0xAF40FCE1,0x6331A9D4,0xAF1A0293,0x6311DD64,0xAEF314C0, +0x62F201AC,0xAECC336C,0x62D216B3,0xAEA55E9E,0x62B21C7B,0xAE7E965B,0x6292130C, +0xAE57DAAB,0x6271FA69,0xAE312B92,0x6251D298,0xAE0A8916,0x62319B9D,0xADE3F33E, +0x6211557E,0xADBD6A10,0x61F1003F,0xAD96ED92,0x61D09BE5,0xAD707DC8,0x61B02876, +0xAD4A1ABA,0x618FA5F7,0xAD23C46E,0x616F146C,0xACFD7AE8,0x614E73DA,0xACD73E30, +0x612DC447,0xACB10E4B,0x610D05B7,0xAC8AEB3E,0x60EC3830,0xAC64D510,0x60CB5BB7, +0xAC3ECBC7,0x60AA7050,0xAC18CF69,0x60897601,0xABF2DFFB,0x60686CCF,0xABCCFD83, +0x604754BF,0xABA72807,0x60262DD6,0xAB815F8D,0x6004F819,0xAB5BA41A,0x5FE3B38D, +0xAB35F5B5,0x5FC26038,0xAB105464,0x5FA0FE1F,0xAAEAC02C,0x5F7F8D46,0xAAC53912, +0x5F5E0DB3,0xAA9FBF1E,0x5F3C7F6B,0xAA7A5253,0x5F1AE274,0xAA54F2BA,0x5EF936D1, +0xAA2FA056,0x5ED77C8A,0xAA0A5B2E,0x5EB5B3A2,0xA9E52347,0x5E93DC1F,0xA9BFF8A8, +0x5E71F606,0xA99ADB56,0x5E50015D,0xA975CB57,0x5E2DFE29,0xA950C8B0,0x5E0BEC6E, +0xA92BD367,0x5DE9CC33,0xA906EB82,0x5DC79D7C,0xA8E21106,0x5DA5604F,0xA8BD43FA, +0x5D8314B1,0xA8988463,0x5D60BAA7,0xA873D246,0x5D3E5237,0xA84F2DAA,0x5D1BDB65, +0xA82A9693,0x5CF95638,0xA8060D08,0x5CD6C2B5,0xA7E1910F,0x5CB420E0,0xA7BD22AC, +0x5C9170BF,0xA798C1E5,0x5C6EB258,0xA7746EC0,0x5C4BE5B0,0xA7502943,0x5C290ACC, +0xA72BF174,0x5C0621B2,0xA707C757,0x5BE32A67,0xA6E3AAF2,0x5BC024F0,0xA6BF9C4B, +0x5B9D1154,0xA69B9B68,0x5B79EF96,0xA677A84E,0x5B56BFBD,0xA653C303,0x5B3381CE, +0xA62FEB8B,0x5B1035CF,0xA60C21EE,0x5AECDBC5,0xA5E8662F,0x5AC973B5,0xA5C4B855, +0x5AA5FDA5,0xA5A11866,0x5A82799A,0xA57D8666,0x5A5EE79A,0xA55A025B,0x5A3B47AB, +0xA5368C4B,0x5A1799D1,0xA513243B,0x59F3DE12,0xA4EFCA31,0x59D01475,0xA4CC7E32, +0x59AC3CFD,0xA4A94043,0x598857B2,0xA486106A,0x59646498,0xA462EEAC,0x594063B5, +0xA43FDB10,0x591C550E,0xA41CD599,0x58F838A9,0xA3F9DE4E,0x58D40E8C,0xA3D6F534, +0x58AFD6BD,0xA3B41A50,0x588B9140,0xA3914DA8,0x58673E1B,0xA36E8F41,0x5842DD54, +0xA34BDF20,0x581E6EF1,0xA3293D4B,0x57F9F2F8,0xA306A9C8,0x57D5696D,0xA2E4249B, +0x57B0D256,0xA2C1ADC9,0x578C2DBA,0xA29F4559,0x57677B9D,0xA27CEB4F,0x5742BC06, +0xA25A9FB1,0x571DEEFA,0xA2386284,0x56F9147E,0xA21633CD,0x56D42C99,0xA1F41392, +0x56AF3750,0xA1D201D7,0x568A34A9,0xA1AFFEA3,0x566524AA,0xA18E09FA,0x56400758, +0xA16C23E1,0x561ADCB9,0xA14A4C5E,0x55F5A4D2,0xA1288376,0x55D05FAA,0xA106C92F, +0x55AB0D46,0xA0E51D8C,0x5585ADAD,0xA0C38095,0x556040E2,0xA0A1F24D,0x553AC6EE, +0xA08072BA,0x55153FD4,0xA05F01E1,0x54EFAB9C,0xA03D9FC8,0x54CA0A4B,0xA01C4C73, +0x54A45BE6,0x9FFB07E7,0x547EA073,0x9FD9D22A,0x5458D7F9,0x9FB8AB41,0x5433027D, +0x9F979331,0x540D2005,0x9F7689FF,0x53E73097,0x9F558FB0,0x53C13439,0x9F34A449, +0x539B2AF0,0x9F13C7D0,0x537514C2,0x9EF2FA49,0x534EF1B5,0x9ED23BB9,0x5328C1D0, +0x9EB18C26,0x53028518,0x9E90EB94,0x52DC3B92,0x9E705A09,0x52B5E546,0x9E4FD78A, +0x528F8238,0x9E2F641B,0x5269126E,0x9E0EFFC1,0x524295F0,0x9DEEAA82,0x521C0CC2, +0x9DCE6463,0x51F576EA,0x9DAE2D68,0x51CED46E,0x9D8E0597,0x51A82555,0x9D6DECF4, +0x518169A5,0x9D4DE385,0x515AA162,0x9D2DE94D,0x5133CC94,0x9D0DFE54,0x510CEB40, +0x9CEE229C,0x50E5FD6D,0x9CCE562C,0x50BF031F,0x9CAE9907,0x5097FC5E,0x9C8EEB34, +0x5070E92F,0x9C6F4CB6,0x5049C999,0x9C4FBD93,0x50229DA1,0x9C303DCF,0x4FFB654D, +0x9C10CD70,0x4FD420A4,0x9BF16C7A,0x4FACCFAB,0x9BD21AF3,0x4F857269,0x9BB2D8DE, +0x4F5E08E3,0x9B93A641,0x4F369320,0x9B748320,0x4F0F1126,0x9B556F81,0x4EE782FB, +0x9B366B68,0x4EBFE8A5,0x9B1776DA,0x4E984229,0x9AF891DB,0x4E708F8F,0x9AD9BC71, +0x4E48D0DD,0x9ABAF6A1,0x4E210617,0x9A9C406E,0x4DF92F46,0x9A7D99DE,0x4DD14C6E, +0x9A5F02F5,0x4DA95D96,0x9A407BB9,0x4D8162C4,0x9A22042D,0x4D595BFE,0x9A039C57, +0x4D31494B,0x99E5443B,0x4D092AB0,0x99C6FBDE,0x4CE10034,0x99A8C345,0x4CB8C9DD, +0x998A9A74,0x4C9087B1,0x996C816F,0x4C6839B7,0x994E783D,0x4C3FDFF4,0x99307EE0, +0x4C177A6E,0x9912955F,0x4BEF092D,0x98F4BBBC,0x4BC68C36,0x98D6F1FE,0x4B9E0390, +0x98B93828,0x4B756F40,0x989B8E40,0x4B4CCF4D,0x987DF449,0x4B2423BE,0x98606A49, +0x4AFB6C98,0x9842F043,0x4AD2A9E2,0x9825863D,0x4AA9DBA2,0x98082C3B,0x4A8101DE, +0x97EAE242,0x4A581C9E,0x97CDA855,0x4A2F2BE6,0x97B07E7A,0x4A062FBD,0x979364B5, +0x49DD282A,0x97765B0A,0x49B41533,0x9759617F,0x498AF6DF,0x973C7817,0x4961CD33, +0x971F9ED7,0x49389836,0x9702D5C3,0x490F57EE,0x96E61CE0,0x48E60C62,0x96C97432, +0x48BCB599,0x96ACDBBE,0x48935397,0x96905388,0x4869E665,0x9673DB94,0x48406E08, +0x965773E7,0x4816EA86,0x963B1C86,0x47ED5BE6,0x961ED574,0x47C3C22F,0x96029EB6, +0x479A1D67,0x95E67850,0x47706D93,0x95CA6247,0x4746B2BC,0x95AE5C9F,0x471CECE7, +0x9592675C,0x46F31C1A,0x95768283,0x46C9405C,0x955AAE17,0x469F59B4,0x953EEA1E, +0x46756828,0x9523369C,0x464B6BBE,0x95079394,0x4621647D,0x94EC010B,0x45F7526B, +0x94D07F05,0x45CD358F,0x94B50D87,0x45A30DF0,0x9499AC95,0x4578DB93,0x947E5C33, +0x454E9E80,0x94631C65,0x452456BD,0x9447ED2F,0x44FA0450,0x942CCE96,0x44CFA740, +0x9411C09E,0x44A53F93,0x93F6C34A,0x447ACD50,0x93DBD6A0,0x4450507E,0x93C0FAA3, +0x4425C923,0x93A62F57,0x43FB3746,0x938B74C1,0x43D09AED,0x9370CAE4,0x43A5F41E, +0x935631C5,0x437B42E1,0x933BA968,0x4350873C,0x932131D1,0x4325C135,0x9306CB04, +0x42FAF0D4,0x92EC7505,0x42D0161E,0x92D22FD9,0x42A5311B,0x92B7FB82,0x427A41D0, +0x929DD806,0x424F4845,0x9283C568,0x42244481,0x9269C3AC,0x41F93689,0x924FD2D7, +0x41CE1E65,0x9235F2EC,0x41A2FC1A,0x921C23EF,0x4177CFB1,0x920265E4,0x414C992F, +0x91E8B8D0,0x4121589B,0x91CF1CB6,0x40F60DFB,0x91B5919A,0x40CAB958,0x919C1781, +0x409F5AB6,0x9182AE6D,0x4073F21D,0x91695663,0x40487F94,0x91500F67,0x401D0321, +0x9136D97D,0x3FF17CCA,0x911DB4A9,0x3FC5EC98,0x9104A0EE,0x3F9A5290,0x90EB9E50, +0x3F6EAEB8,0x90D2ACD4,0x3F430119,0x90B9CC7D,0x3F1749B8,0x90A0FD4E,0x3EEB889C, +0x90883F4D,0x3EBFBDCD,0x906F927C,0x3E93E950,0x9056F6DF,0x3E680B2C,0x903E6C7B, +0x3E3C2369,0x9025F352,0x3E10320D,0x900D8B69,0x3DE4371F,0x8FF534C4,0x3DB832A6, +0x8FDCEF66,0x3D8C24A8,0x8FC4BB53,0x3D600D2C,0x8FAC988F,0x3D33EC39,0x8F94871D, +0x3D07C1D6,0x8F7C8701,0x3CDB8E09,0x8F649840,0x3CAF50DA,0x8F4CBADB,0x3C830A50, +0x8F34EED8,0x3C56BA70,0x8F1D343A,0x3C2A6142,0x8F058B04,0x3BFDFECD,0x8EEDF33B, +0x3BD19318,0x8ED66CE1,0x3BA51E29,0x8EBEF7FB,0x3B78A007,0x8EA7948C,0x3B4C18BA, +0x8E904298,0x3B1F8848,0x8E790222,0x3AF2EEB7,0x8E61D32E,0x3AC64C0F,0x8E4AB5BF, +0x3A99A057,0x8E33A9DA,0x3A6CEB96,0x8E1CAF80,0x3A402DD2,0x8E05C6B7,0x3A136712, +0x8DEEEF82,0x39E6975E,0x8DD829E4,0x39B9BEBC,0x8DC175E0,0x398CDD32,0x8DAAD37B, +0x395FF2C9,0x8D9442B8,0x3932FF87,0x8D7DC399,0x39060373,0x8D675623,0x38D8FE93, +0x8D50FA59,0x38ABF0EF,0x8D3AB03F,0x387EDA8E,0x8D2477D8,0x3851BB77,0x8D0E5127, +0x382493B0,0x8CF83C30,0x37F76341,0x8CE238F6,0x37CA2A30,0x8CCC477D,0x379CE885, +0x8CB667C8,0x376F9E46,0x8CA099DA,0x37424B7B,0x8C8ADDB7,0x3714F02A,0x8C753362, +0x36E78C5B,0x8C5F9ADE,0x36BA2014,0x8C4A142F,0x368CAB5C,0x8C349F58,0x365F2E3B, +0x8C1F3C5D,0x3631A8B8,0x8C09EB40,0x36041AD9,0x8BF4AC05,0x35D684A6,0x8BDF7EB0, +0x35A8E625,0x8BCA6343,0x357B3F5D,0x8BB559C1,0x354D9057,0x8BA0622F,0x351FD918, +0x8B8B7C8F,0x34F219A8,0x8B76A8E4,0x34C4520D,0x8B61E733,0x34968250,0x8B4D377C, +0x3468AA76,0x8B3899C6,0x343ACA87,0x8B240E11,0x340CE28B,0x8B0F9462,0x33DEF287, +0x8AFB2CBB,0x33B0FA84,0x8AE6D720,0x3382FA88,0x8AD29394,0x3354F29B,0x8ABE6219, +0x3326E2C3,0x8AAA42B4,0x32F8CB07,0x8A963567,0x32CAAB6F,0x8A823A36,0x329C8402, +0x8A6E5123,0x326E54C7,0x8A5A7A31,0x32401DC6,0x8A46B564,0x3211DF04,0x8A3302BE, +0x31E39889,0x8A1F6243,0x31B54A5E,0x8A0BD3F5,0x3186F487,0x89F857D8,0x3158970E, +0x89E4EDEF,0x312A31F8,0x89D1963C,0x30FBC54D,0x89BE50C3,0x30CD5115,0x89AB1D87, +0x309ED556,0x8997FC8A,0x30705217,0x8984EDCF,0x3041C761,0x8971F15A,0x30133539, +0x895F072E,0x2FE49BA7,0x894C2F4C,0x2FB5FAB2,0x893969B9,0x2F875262,0x8926B677, +0x2F58A2BE,0x89141589,0x2F29EBCC,0x890186F2,0x2EFB2D95,0x88EF0AB4,0x2ECC681E, +0x88DCA0D3,0x2E9D9B70,0x88CA4951,0x2E6EC792,0x88B80432,0x2E3FEC8B,0x88A5D177, +0x2E110A62,0x8893B125,0x2DE2211E,0x8881A33D,0x2DB330C7,0x886FA7C2,0x2D843964, +0x885DBEB8,0x2D553AFC,0x884BE821,0x2D263596,0x883A23FF,0x2CF72939,0x88287256, +0x2CC815EE,0x8816D327,0x2C98FBBA,0x88054677,0x2C69DAA6,0x87F3CC48,0x2C3AB2B9, +0x87E2649B,0x2C0B83FA,0x87D10F75,0x2BDC4E6F,0x87BFCCD7,0x2BAD1221,0x87AE9CC5, +0x2B7DCF17,0x879D7F41,0x2B4E8558,0x878C744D,0x2B1F34EB,0x877B7BEC,0x2AEFDDD8, +0x876A9621,0x2AC08026,0x8759C2EF,0x2A911BDC,0x87490258,0x2A61B101,0x8738545E, +0x2A323F9E,0x8727B905,0x2A02C7B8,0x8717304E,0x29D34958,0x8706BA3D,0x29A3C485, +0x86F656D3,0x29743946,0x86E60614,0x2944A7A2,0x86D5C802,0x29150FA1,0x86C59C9F, +0x28E5714B,0x86B583EE,0x28B5CCA5,0x86A57DF2,0x288621B9,0x86958AAC,0x2856708D, +0x8685AA20,0x2826B928,0x8675DC4F,0x27F6FB92,0x8666213C,0x27C737D3,0x865678EB, +0x27976DF1,0x8646E35C,0x27679DF4,0x86376092,0x2737C7E3,0x8627F091,0x2707EBC7, +0x86189359,0x26D809A5,0x860948EF,0x26A82186,0x85FA1153,0x26783370,0x85EAEC88, +0x26483F6C,0x85DBDA91,0x26184581,0x85CCDB70,0x25E845B6,0x85BDEF28,0x25B84012, +0x85AF15B9,0x2588349D,0x85A04F28,0x2558235F,0x85919B76,0x25280C5E,0x8582FAA5, +0x24F7EFA2,0x85746CB8,0x24C7CD33,0x8565F1B0,0x2497A517,0x85578991,0x24677758, +0x8549345C,0x243743FA,0x853AF214,0x24070B08,0x852CC2BB,0x23D6CC87,0x851EA652, +0x23A6887F,0x85109CDD,0x23763EF7,0x8502A65C,0x2345EFF8,0x84F4C2D4,0x23159B88, +0x84E6F244,0x22E541AF,0x84D934B1,0x22B4E274,0x84CB8A1B,0x22847DE0,0x84BDF286, +0x225413F8,0x84B06DF2,0x2223A4C5,0x84A2FC62,0x21F3304F,0x84959DD9,0x21C2B69C, +0x84885258,0x219237B5,0x847B19E1,0x2161B3A0,0x846DF477,0x21312A65,0x8460E21A, +0x21009C0C,0x8453E2CF,0x20D0089C,0x8446F695,0x209F701C,0x843A1D70,0x206ED295, +0x842D5762,0x203E300D,0x8420A46C,0x200D888D,0x84140490,0x1FDCDC1B,0x840777D0, +0x1FAC2ABF,0x83FAFE2E,0x1F7B7481,0x83EE97AD,0x1F4AB968,0x83E2444D,0x1F19F97B, +0x83D60412,0x1EE934C3,0x83C9D6FC,0x1EB86B46,0x83BDBD0E,0x1E879D0D,0x83B1B649, +0x1E56CA1E,0x83A5C2B0,0x1E25F282,0x8399E244,0x1DF5163F,0x838E1507,0x1DC4355E, +0x83825AFB,0x1D934FE5,0x8376B422,0x1D6265DD,0x836B207D,0x1D31774D,0x835FA00F, +0x1D00843D,0x835432D8,0x1CCF8CB3,0x8348D8DC,0x1C9E90B8,0x833D921B,0x1C6D9053, +0x83325E97,0x1C3C8B8C,0x83273E52,0x1C0B826A,0x831C314E,0x1BDA74F6,0x8311378D, +0x1BA96335,0x83065110,0x1B784D30,0x82FB7DD8,0x1B4732EF,0x82F0BDE8,0x1B161479, +0x82E61141,0x1AE4F1D6,0x82DB77E5,0x1AB3CB0D,0x82D0F1D5,0x1A82A026,0x82C67F14, +0x1A517128,0x82BC1FA2,0x1A203E1B,0x82B1D381,0x19EF0707,0x82A79AB3,0x19BDCBF3, +0x829D753A,0x198C8CE7,0x82936317,0x195B49EA,0x8289644B,0x192A0304,0x827F78D8, +0x18F8B83C,0x8275A0C0,0x18C7699B,0x826BDC04,0x18961728,0x82622AA6,0x1864C0EA, +0x82588CA7,0x183366E9,0x824F0208,0x1802092C,0x82458ACC,0x17D0A7BC,0x823C26F3, +0x179F429F,0x8232D67F,0x176DD9DE,0x82299971,0x173C6D80,0x82206FCC,0x170AFD8D, +0x82175990,0x16D98A0C,0x820E56BE,0x16A81305,0x82056758,0x1676987F,0x81FC8B60, +0x16451A83,0x81F3C2D7,0x16139918,0x81EB0DBE,0x15E21445,0x81E26C16,0x15B08C12, +0x81D9DDE1,0x157F0086,0x81D16321,0x154D71AA,0x81C8FBD6,0x151BDF86,0x81C0A801, +0x14EA4A1F,0x81B867A5,0x14B8B17F,0x81B03AC2,0x148715AE,0x81A82159,0x145576B1, +0x81A01B6D,0x1423D492,0x819828FD,0x13F22F58,0x81904A0C,0x13C0870A,0x81887E9A, +0x138EDBB1,0x8180C6A9,0x135D2D53,0x8179223A,0x132B7BF9,0x8171914E,0x12F9C7AA, +0x816A13E6,0x12C8106F,0x8162AA04,0x1296564D,0x815B53A8,0x1264994E,0x815410D4, +0x1232D979,0x814CE188,0x120116D5,0x8145C5C7,0x11CF516A,0x813EBD90,0x119D8941, +0x8137C8E6,0x116BBE60,0x8130E7C9,0x1139F0CF,0x812A1A3A,0x11082096,0x8123603A, +0x10D64DBD,0x811CB9CA,0x10A4784B,0x811626EC,0x1072A048,0x810FA7A0,0x1040C5BB, +0x81093BE8,0x100EE8AD,0x8102E3C4,0x0FDD0926,0x80FC9F35,0x0FAB272B,0x80F66E3C, +0x0F7942C7,0x80F050DB,0x0F475BFF,0x80EA4712,0x0F1572DC,0x80E450E2,0x0EE38766, +0x80DE6E4C,0x0EB199A4,0x80D89F51,0x0E7FA99E,0x80D2E3F2,0x0E4DB75B,0x80CD3C2F, +0x0E1BC2E4,0x80C7A80A,0x0DE9CC40,0x80C22784,0x0DB7D376,0x80BCBA9D,0x0D85D88F, +0x80B76156,0x0D53DB92,0x80B21BAF,0x0D21DC87,0x80ACE9AB,0x0CEFDB76,0x80A7CB49, +0x0CBDD865,0x80A2C08B,0x0C8BD35E,0x809DC971,0x0C59CC68,0x8098E5FB,0x0C27C389, +0x8094162C,0x0BF5B8CB,0x808F5A02,0x0BC3AC35,0x808AB180,0x0B919DCF,0x80861CA6, +0x0B5F8D9F,0x80819B74,0x0B2D7BAF,0x807D2DEC,0x0AFB6805,0x8078D40D,0x0AC952AA, +0x80748DD9,0x0A973BA5,0x80705B50,0x0A6522FE,0x806C3C74,0x0A3308BD,0x80683143, +0x0A00ECE8,0x806439C0,0x09CECF89,0x806055EB,0x099CB0A7,0x805C85C4,0x096A9049, +0x8058C94C,0x09386E78,0x80552084,0x09064B3A,0x80518B6B,0x08D42699,0x804E0A04, +0x08A2009A,0x804A9C4D,0x086FD947,0x80474248,0x083DB0A7,0x8043FBF6,0x080B86C2, +0x8040C956,0x07D95B9E,0x803DAA6A,0x07A72F45,0x803A9F31,0x077501BE,0x8037A7AC, +0x0742D311,0x8034C3DD,0x0710A345,0x8031F3C2,0x06DE7262,0x802F375D,0x06AC406F, +0x802C8EAD,0x067A0D76,0x8029F9B4,0x0647D97C,0x80277872,0x0615A48B,0x80250AE7, +0x05E36EA9,0x8022B114,0x05B137DF,0x80206AF8,0x057F0035,0x801E3895,0x054CC7B1, +0x801C19EA,0x051A8E5C,0x801A0EF8,0x04E8543E,0x801817BF,0x04B6195D,0x80163440, +0x0483DDC3,0x8014647B,0x0451A177,0x8012A86F,0x041F6480,0x8011001F,0x03ED26E6, +0x800F6B88,0x03BAE8B2,0x800DEAAD,0x0388A9EA,0x800C7D8C,0x03566A96,0x800B2427, +0x03242ABF,0x8009DE7E,0x02F1EA6C,0x8008AC90,0x02BFA9A4,0x80078E5E,0x028D6870, +0x800683E8,0x025B26D7,0x80058D2F,0x0228E4E2,0x8004AA32,0x01F6A297,0x8003DAF1, +0x01C45FFE,0x80031F6D,0x01921D20,0x800277A6,0x015FDA03,0x8001E39B,0x012D96B1, +0x8001634E,0x00FB5330,0x8000F6BD,0x00C90F88,0x80009DEA,0x0096CBC1,0x800058D4, +0x006487E3,0x8000277A,0x003243F5,0x800009DF,0x7FFFFFFF,0x00000000,0x7FFF6216, +0xFF36F078,0x7FFD885A,0xFE6DE2E0,0x7FFA72D1,0xFDA4D929,0x7FF62182,0xFCDBD541, +0x7FF09478,0xFC12D91A,0x7FE9CBC0,0xFB49E6A3,0x7FE1C76B,0xFA80FFCB,0x7FD8878E, +0xF9B82684,0x7FCE0C3E,0xF8EF5CBB,0x7FC25596,0xF826A462,0x7FB563B3,0xF75DFF66, +0x7FA736B4,0xF6956FB7,0x7F97CEBD,0xF5CCF743,0x7F872BF3,0xF50497FB,0x7F754E80, +0xF43C53CB,0x7F62368F,0xF3742CA2,0x7F4DE451,0xF2AC246E,0x7F3857F6,0xF1E43D1C, +0x7F2191B4,0xF11C789A,0x7F0991C4,0xF054D8D5,0x7EF05860,0xEF8D5FB8,0x7ED5E5C6, +0xEEC60F31,0x7EBA3A39,0xEDFEE92B,0x7E9D55FC,0xED37EF91,0x7E7F3957,0xEC71244F, +0x7E5FE493,0xEBAA894F,0x7E3F57FF,0xEAE4207A,0x7E1D93EA,0xEA1DEBBB,0x7DFA98A8, +0xE957ECFB,0x7DD6668F,0xE8922622,0x7DB0FDF8,0xE7CC9917,0x7D8A5F40,0xE70747C4, +0x7D628AC6,0xE642340D,0x7D3980EC,0xE57D5FDA,0x7D0F4218,0xE4B8CD11,0x7CE3CEB2, +0xE3F47D96,0x7CB72724,0xE330734D,0x7C894BDE,0xE26CB01B,0x7C5A3D50,0xE1A935E2, +0x7C29FBEE,0xE0E60685,0x7BF88830,0xE02323E5,0x7BC5E290,0xDF608FE4,0x7B920B89, +0xDE9E4C60,0x7B5D039E,0xDDDC5B3B,0x7B26CB4F,0xDD1ABE51,0x7AEF6323,0xDC597781, +0x7AB6CBA4,0xDB9888A8,0x7A7D055B,0xDAD7F3A2,0x7A4210D8,0xDA17BA4A,0x7A05EEAD, +0xD957DE7A,0x79C89F6E,0xD898620C,0x798A23B1,0xD7D946D8,0x794A7C12,0xD71A8EB5, +0x7909A92D,0xD65C3B7B,0x78C7ABA2,0xD59E4EFF,0x78848414,0xD4E0CB15,0x78403329, +0xD423B191,0x77FAB989,0xD3670446,0x77B417DF,0xD2AAC504,0x776C4EDB,0xD1EEF59E, +0x77235F2D,0xD13397E2,0x76D94989,0xD078AD9E,0x768E0EA6,0xCFBE389F,0x7641AF3D, +0xCF043AB3,0x75F42C0B,0xCE4AB5A2,0x75A585CF,0xCD91AB39,0x7555BD4C,0xCCD91D3D, +0x7504D345,0xCC210D79,0x74B2C884,0xCB697DB0,0x745F9DD1,0xCAB26FA9,0x740B53FB, +0xC9FBE527,0x73B5EBD1,0xC945DFEC,0x735F6626,0xC89061BA,0x7307C3D0,0xC7DB6C50, +0x72AF05A7,0xC727016D,0x72552C85,0xC67322CE,0x71FA3949,0xC5BFD22E,0x719E2CD2, +0xC50D1149,0x71410805,0xC45AE1D7,0x70E2CBC6,0xC3A94590,0x708378FF,0xC2F83E2A, +0x7023109A,0xC247CD5A,0x6FC19385,0xC197F4D4,0x6F5F02B2,0xC0E8B648,0x6EFB5F12, +0xC03A1368,0x6E96A99D,0xBF8C0DE3,0x6E30E34A,0xBEDEA765,0x6DCA0D14,0xBE31E19B, +0x6D6227FA,0xBD85BE30,0x6CF934FC,0xBCDA3ECB,0x6C8F351C,0xBC2F6513,0x6C242960, +0xBB8532B0,0x6BB812D1,0xBADBA943,0x6B4AF279,0xBA32CA71,0x6ADCC964,0xB98A97D8, +0x6A6D98A4,0xB8E31319,0x69FD614A,0xB83C3DD1,0x698C246C,0xB796199B,0x6919E320, +0xB6F0A812,0x68A69E81,0xB64BEACD,0x683257AB,0xB5A7E362,0x67BD0FBD,0xB5049368, +0x6746C7D8,0xB461FC70,0x66CF8120,0xB3C0200C,0x66573CBB,0xB31EFFCC,0x65DDFBD3, +0xB27E9D3C,0x6563BF92,0xB1DEF9E9,0x64E88926,0xB140175B,0x646C59BF,0xB0A1F71D, +0x63EF3290,0xB0049AB3,0x637114CC,0xAF6803A2,0x62F201AC,0xAECC336C,0x6271FA69, +0xAE312B92,0x61F1003F,0xAD96ED92,0x616F146C,0xACFD7AE8,0x60EC3830,0xAC64D510, +0x60686CCF,0xABCCFD83,0x5FE3B38D,0xAB35F5B5,0x5F5E0DB3,0xAA9FBF1E,0x5ED77C8A, +0xAA0A5B2E,0x5E50015D,0xA975CB57,0x5DC79D7C,0xA8E21106,0x5D3E5237,0xA84F2DAA, +0x5CB420E0,0xA7BD22AC,0x5C290ACC,0xA72BF174,0x5B9D1154,0xA69B9B68,0x5B1035CF, +0xA60C21EE,0x5A82799A,0xA57D8666,0x59F3DE12,0xA4EFCA31,0x59646498,0xA462EEAC, +0x58D40E8C,0xA3D6F534,0x5842DD54,0xA34BDF20,0x57B0D256,0xA2C1ADC9,0x571DEEFA, +0xA2386284,0x568A34A9,0xA1AFFEA3,0x55F5A4D2,0xA1288376,0x556040E2,0xA0A1F24D, +0x54CA0A4B,0xA01C4C73,0x5433027D,0x9F979331,0x539B2AF0,0x9F13C7D0,0x53028518, +0x9E90EB94,0x5269126E,0x9E0EFFC1,0x51CED46E,0x9D8E0597,0x5133CC94,0x9D0DFE54, +0x5097FC5E,0x9C8EEB34,0x4FFB654D,0x9C10CD70,0x4F5E08E3,0x9B93A641,0x4EBFE8A5, +0x9B1776DA,0x4E210617,0x9A9C406E,0x4D8162C4,0x9A22042D,0x4CE10034,0x99A8C345, +0x4C3FDFF4,0x99307EE0,0x4B9E0390,0x98B93828,0x4AFB6C98,0x9842F043,0x4A581C9E, +0x97CDA855,0x49B41533,0x9759617F,0x490F57EE,0x96E61CE0,0x4869E665,0x9673DB94, +0x47C3C22F,0x96029EB6,0x471CECE7,0x9592675C,0x46756828,0x9523369C,0x45CD358F, +0x94B50D87,0x452456BD,0x9447ED2F,0x447ACD50,0x93DBD6A0,0x43D09AED,0x9370CAE4, +0x4325C135,0x9306CB04,0x427A41D0,0x929DD806,0x41CE1E65,0x9235F2EC,0x4121589B, +0x91CF1CB6,0x4073F21D,0x91695663,0x3FC5EC98,0x9104A0EE,0x3F1749B8,0x90A0FD4E, +0x3E680B2C,0x903E6C7B,0x3DB832A6,0x8FDCEF66,0x3D07C1D6,0x8F7C8701,0x3C56BA70, +0x8F1D343A,0x3BA51E29,0x8EBEF7FB,0x3AF2EEB7,0x8E61D32E,0x3A402DD2,0x8E05C6B7, +0x398CDD32,0x8DAAD37B,0x38D8FE93,0x8D50FA59,0x382493B0,0x8CF83C30,0x376F9E46, +0x8CA099DA,0x36BA2014,0x8C4A142F,0x36041AD9,0x8BF4AC05,0x354D9057,0x8BA0622F, +0x34968250,0x8B4D377C,0x33DEF287,0x8AFB2CBB,0x3326E2C3,0x8AAA42B4,0x326E54C7, +0x8A5A7A31,0x31B54A5E,0x8A0BD3F5,0x30FBC54D,0x89BE50C3,0x3041C761,0x8971F15A, +0x2F875262,0x8926B677,0x2ECC681E,0x88DCA0D3,0x2E110A62,0x8893B125,0x2D553AFC, +0x884BE821,0x2C98FBBA,0x88054677,0x2BDC4E6F,0x87BFCCD7,0x2B1F34EB,0x877B7BEC, +0x2A61B101,0x8738545E,0x29A3C485,0x86F656D3,0x28E5714B,0x86B583EE,0x2826B928, +0x8675DC4F,0x27679DF4,0x86376092,0x26A82186,0x85FA1153,0x25E845B6,0x85BDEF28, +0x25280C5E,0x8582FAA5,0x24677758,0x8549345C,0x23A6887F,0x85109CDD,0x22E541AF, +0x84D934B1,0x2223A4C5,0x84A2FC62,0x2161B3A0,0x846DF477,0x209F701C,0x843A1D70, +0x1FDCDC1B,0x840777D0,0x1F19F97B,0x83D60412,0x1E56CA1E,0x83A5C2B0,0x1D934FE5, +0x8376B422,0x1CCF8CB3,0x8348D8DC,0x1C0B826A,0x831C314E,0x1B4732EF,0x82F0BDE8, +0x1A82A026,0x82C67F14,0x19BDCBF3,0x829D753A,0x18F8B83C,0x8275A0C0,0x183366E9, +0x824F0208,0x176DD9DE,0x82299971,0x16A81305,0x82056758,0x15E21445,0x81E26C16, +0x151BDF86,0x81C0A801,0x145576B1,0x81A01B6D,0x138EDBB1,0x8180C6A9,0x12C8106F, +0x8162AA04,0x120116D5,0x8145C5C7,0x1139F0CF,0x812A1A3A,0x1072A048,0x810FA7A0, +0x0FAB272B,0x80F66E3C,0x0EE38766,0x80DE6E4C,0x0E1BC2E4,0x80C7A80A,0x0D53DB92, +0x80B21BAF,0x0C8BD35E,0x809DC971,0x0BC3AC35,0x808AB180,0x0AFB6805,0x8078D40D, +0x0A3308BD,0x80683143,0x096A9049,0x8058C94C,0x08A2009A,0x804A9C4D,0x07D95B9E, +0x803DAA6A,0x0710A345,0x8031F3C2,0x0647D97C,0x80277872,0x057F0035,0x801E3895, +0x04B6195D,0x80163440,0x03ED26E6,0x800F6B88,0x03242ABF,0x8009DE7E,0x025B26D7, +0x80058D2F,0x01921D20,0x800277A6,0x00C90F88,0x80009DEA,0x7FFFFFFF,0x00000000, +0x7FF62182,0xFCDBD541,0x7FD8878E,0xF9B82684,0x7FA736B4,0xF6956FB7,0x7F62368F, +0xF3742CA2,0x7F0991C4,0xF054D8D5,0x7E9D55FC,0xED37EF91,0x7E1D93EA,0xEA1DEBBB, +0x7D8A5F40,0xE70747C4,0x7CE3CEB2,0xE3F47D96,0x7C29FBEE,0xE0E60685,0x7B5D039E, +0xDDDC5B3B,0x7A7D055B,0xDAD7F3A2,0x798A23B1,0xD7D946D8,0x78848414,0xD4E0CB15, +0x776C4EDB,0xD1EEF59E,0x7641AF3D,0xCF043AB3,0x7504D345,0xCC210D79,0x73B5EBD1, +0xC945DFEC,0x72552C85,0xC67322CE,0x70E2CBC6,0xC3A94590,0x6F5F02B2,0xC0E8B648, +0x6DCA0D14,0xBE31E19B,0x6C242960,0xBB8532B0,0x6A6D98A4,0xB8E31319,0x68A69E81, +0xB64BEACD,0x66CF8120,0xB3C0200C,0x64E88926,0xB140175B,0x62F201AC,0xAECC336C, +0x60EC3830,0xAC64D510,0x5ED77C8A,0xAA0A5B2E,0x5CB420E0,0xA7BD22AC,0x5A82799A, +0xA57D8666,0x5842DD54,0xA34BDF20,0x55F5A4D2,0xA1288376,0x539B2AF0,0x9F13C7D0, +0x5133CC94,0x9D0DFE54,0x4EBFE8A5,0x9B1776DA,0x4C3FDFF4,0x99307EE0,0x49B41533, +0x9759617F,0x471CECE7,0x9592675C,0x447ACD50,0x93DBD6A0,0x41CE1E65,0x9235F2EC, +0x3F1749B8,0x90A0FD4E,0x3C56BA70,0x8F1D343A,0x398CDD32,0x8DAAD37B,0x36BA2014, +0x8C4A142F,0x33DEF287,0x8AFB2CBB,0x30FBC54D,0x89BE50C3,0x2E110A62,0x8893B125, +0x2B1F34EB,0x877B7BEC,0x2826B928,0x8675DC4F,0x25280C5E,0x8582FAA5,0x2223A4C5, +0x84A2FC62,0x1F19F97B,0x83D60412,0x1C0B826A,0x831C314E,0x18F8B83C,0x8275A0C0, +0x15E21445,0x81E26C16,0x12C8106F,0x8162AA04,0x0FAB272B,0x80F66E3C,0x0C8BD35E, +0x809DC971,0x096A9049,0x8058C94C,0x0647D97C,0x80277872,0x03242ABF,0x8009DE7E, +0x7FFFFFFF,0x00000000,0x7F62368F,0xF3742CA2,0x7D8A5F40,0xE70747C4,0x7A7D055B, +0xDAD7F3A2,0x7641AF3D,0xCF043AB3,0x70E2CBC6,0xC3A94590,0x6A6D98A4,0xB8E31319, +0x62F201AC,0xAECC336C,0x5A82799A,0xA57D8666,0x5133CC94,0x9D0DFE54,0x471CECE7, +0x9592675C,0x3C56BA70,0x8F1D343A,0x30FBC54D,0x89BE50C3,0x25280C5E,0x8582FAA5, +0x18F8B83C,0x8275A0C0,0x0C8BD35E,0x809DC971,0x7FFFFFFF,0x00000000,0x7641AF3D, +0xCF043AB3,0x5A82799A,0xA57D8666,0x30FBC54D,0x89BE50C3,}; + +q31_t rearranged_twiddle_stride2_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFD886,0xFF9B781D,0x7FFF6216,0xFF36F078,0x7FFE9CB2, +0xFED2694F,0x7FFD885A,0xFE6DE2E0,0x7FFC250F,0xFE095D69,0x7FFA72D1,0xFDA4D929, +0x7FF871A2,0xFD40565C,0x7FF62182,0xFCDBD541,0x7FF38274,0xFC775616,0x7FF09478, +0xFC12D91A,0x7FED5791,0xFBAE5E89,0x7FE9CBC0,0xFB49E6A3,0x7FE5F108,0xFAE571A4, +0x7FE1C76B,0xFA80FFCB,0x7FDD4EEC,0xFA1C9157,0x7FD8878E,0xF9B82684,0x7FD37153, +0xF953BF91,0x7FCE0C3E,0xF8EF5CBB,0x7FC85854,0xF88AFE42,0x7FC25596,0xF826A462, +0x7FBC040A,0xF7C24F59,0x7FB563B3,0xF75DFF66,0x7FAE7495,0xF6F9B4C6,0x7FA736B4, +0xF6956FB7,0x7F9FAA15,0xF6313077,0x7F97CEBD,0xF5CCF743,0x7F8FA4B0,0xF568C45B, +0x7F872BF3,0xF50497FB,0x7F7E648C,0xF4A07261,0x7F754E80,0xF43C53CB,0x7F6BE9D4, +0xF3D83C77,0x7F62368F,0xF3742CA2,0x7F5834B7,0xF310248A,0x7F4DE451,0xF2AC246E, +0x7F434563,0xF2482C8A,0x7F3857F6,0xF1E43D1C,0x7F2D1C0E,0xF1805662,0x7F2191B4, +0xF11C789A,0x7F15B8EE,0xF0B8A401,0x7F0991C4,0xF054D8D5,0x7EFD1C3C,0xEFF11753, +0x7EF05860,0xEF8D5FB8,0x7EE34636,0xEF29B243,0x7ED5E5C6,0xEEC60F31,0x7EC8371A, +0xEE6276BF,0x7EBA3A39,0xEDFEE92B,0x7EABEF2C,0xED9B66B2,0x7E9D55FC,0xED37EF91, +0x7E8E6EB2,0xECD48407,0x7E7F3957,0xEC71244F,0x7E6FB5F4,0xEC0DD0A8,0x7E5FE493, +0xEBAA894F,0x7E4FC53E,0xEB474E81,0x7E3F57FF,0xEAE4207A,0x7E2E9CDF,0xEA80FF7A, +0x7E1D93EA,0xEA1DEBBB,0x7E0C3D29,0xE9BAE57D,0x7DFA98A8,0xE957ECFB,0x7DE8A670, +0xE8F50273,0x7DD6668F,0xE8922622,0x7DC3D90D,0xE82F5844,0x7DB0FDF8,0xE7CC9917, +0x7D9DD55A,0xE769E8D8,0x7D8A5F40,0xE70747C4,0x7D769BB5,0xE6A4B616,0x7D628AC6, +0xE642340D,0x7D4E2C7F,0xE5DFC1E5,0x7D3980EC,0xE57D5FDA,0x7D24881B,0xE51B0E2A, +0x7D0F4218,0xE4B8CD11,0x7CF9AEF0,0xE4569CCB,0x7CE3CEB2,0xE3F47D96,0x7CCDA169, +0xE3926FAD,0x7CB72724,0xE330734D,0x7CA05FF1,0xE2CE88B3,0x7C894BDE,0xE26CB01B, +0x7C71EAF9,0xE20AE9C1,0x7C5A3D50,0xE1A935E2,0x7C4242F2,0xE14794BA,0x7C29FBEE, +0xE0E60685,0x7C116853,0xE0848B7F,0x7BF88830,0xE02323E5,0x7BDF5B94,0xDFC1CFF3, +0x7BC5E290,0xDF608FE4,0x7BAC1D31,0xDEFF63F4,0x7B920B89,0xDE9E4C60,0x7B77ADA8, +0xDE3D4964,0x7B5D039E,0xDDDC5B3B,0x7B420D7A,0xDD7B8220,0x7B26CB4F,0xDD1ABE51, +0x7B0B3D2C,0xDCBA1008,0x7AEF6323,0xDC597781,0x7AD33D45,0xDBF8F4F8,0x7AB6CBA4, +0xDB9888A8,0x7A9A0E50,0xDB3832CD,0x7A7D055B,0xDAD7F3A2,0x7A5FB0D8,0xDA77CB63, +0x7A4210D8,0xDA17BA4A,0x7A24256F,0xD9B7C094,0x7A05EEAD,0xD957DE7A,0x79E76CA7, +0xD8F81439,0x79C89F6E,0xD898620C,0x79A98715,0xD838C82D,0x798A23B1,0xD7D946D8, +0x796A7554,0xD779DE47,0x794A7C12,0xD71A8EB5,0x792A37FE,0xD6BB585E,0x7909A92D, +0xD65C3B7B,0x78E8CFB2,0xD5FD3848,0x78C7ABA2,0xD59E4EFF,0x78A63D11,0xD53F7FDA, +0x78848414,0xD4E0CB15,0x786280BF,0xD48230E9,0x78403329,0xD423B191,0x781D9B65, +0xD3C54D47,0x77FAB989,0xD3670446,0x77D78DAA,0xD308D6C7,0x77B417DF,0xD2AAC504, +0x7790583E,0xD24CCF39,0x776C4EDB,0xD1EEF59E,0x7747FBCE,0xD191386E,0x77235F2D, +0xD13397E2,0x76FE790E,0xD0D61434,0x76D94989,0xD078AD9E,0x76B3D0B4,0xD01B6459, +0x768E0EA6,0xCFBE389F,0x76680376,0xCF612AAA,0x7641AF3D,0xCF043AB3,0x761B1211, +0xCEA768F2,0x75F42C0B,0xCE4AB5A2,0x75CCFD42,0xCDEE20FC,0x75A585CF,0xCD91AB39, +0x757DC5CA,0xCD355491,0x7555BD4C,0xCCD91D3D,0x752D6C6C,0xCC7D0578,0x7504D345, +0xCC210D79,0x74DBF1EF,0xCBC53579,0x74B2C884,0xCB697DB0,0x7489571C,0xCB0DE658, +0x745F9DD1,0xCAB26FA9,0x74359CBD,0xCA5719DB,0x740B53FB,0xC9FBE527,0x73E0C3A3, +0xC9A0D1C5,0x73B5EBD1,0xC945DFEC,0x738ACC9E,0xC8EB0FD6,0x735F6626,0xC89061BA, +0x7333B883,0xC835D5D0,0x7307C3D0,0xC7DB6C50,0x72DB8828,0xC7812572,0x72AF05A7, +0xC727016D,0x72823C67,0xC6CD0079,0x72552C85,0xC67322CE,0x7227D61C,0xC61968A2, +0x71FA3949,0xC5BFD22E,0x71CC5626,0xC5665FA9,0x719E2CD2,0xC50D1149,0x716FBD68, +0xC4B3E746,0x71410805,0xC45AE1D7,0x71120CC5,0xC4020133,0x70E2CBC6,0xC3A94590, +0x70B34525,0xC350AF26,0x708378FF,0xC2F83E2A,0x70536771,0xC29FF2D4,0x7023109A, +0xC247CD5A,0x6FF27497,0xC1EFCDF3,0x6FC19385,0xC197F4D4,0x6F906D84,0xC1404233, +0x6F5F02B2,0xC0E8B648,0x6F2D532C,0xC0915148,0x6EFB5F12,0xC03A1368,0x6EC92683, +0xBFE2FCDF,0x6E96A99D,0xBF8C0DE3,0x6E63E87F,0xBF3546A8,0x6E30E34A,0xBEDEA765, +0x6DFD9A1C,0xBE88304F,0x6DCA0D14,0xBE31E19B,0x6D963C54,0xBDDBBB7F,0x6D6227FA, +0xBD85BE30,0x6D2DD027,0xBD2FE9E2,0x6CF934FC,0xBCDA3ECB,0x6CC45698,0xBC84BD1F, +0x6C8F351C,0xBC2F6513,0x6C59D0A9,0xBBDA36DD,0x6C242960,0xBB8532B0,0x6BEE3F62, +0xBB3058C0,0x6BB812D1,0xBADBA943,0x6B81A3CD,0xBA87246D,0x6B4AF279,0xBA32CA71, +0x6B13FEF5,0xB9DE9B83,0x6ADCC964,0xB98A97D8,0x6AA551E9,0xB936BFA4,0x6A6D98A4, +0xB8E31319,0x6A359DB9,0xB88F926D,0x69FD614A,0xB83C3DD1,0x69C4E37A,0xB7E9157A, +0x698C246C,0xB796199B,0x69532442,0xB7434A67,0x6919E320,0xB6F0A812,0x68E06129, +0xB69E32CD,0x68A69E81,0xB64BEACD,0x686C9B4B,0xB5F9D043,0x683257AB,0xB5A7E362, +0x67F7D3C5,0xB556245E,0x67BD0FBD,0xB5049368,0x67820BB7,0xB4B330B3,0x6746C7D8, +0xB461FC70,0x670B4444,0xB410F6D3,0x66CF8120,0xB3C0200C,0x66937E91,0xB36F784F, +0x66573CBB,0xB31EFFCC,0x661ABBC5,0xB2CEB6B5,0x65DDFBD3,0xB27E9D3C,0x65A0FD0B, +0xB22EB392,0x6563BF92,0xB1DEF9E9,0x6526438F,0xB18F7071,0x64E88926,0xB140175B, +0x64AA907F,0xB0F0EEDA,0x646C59BF,0xB0A1F71D,0x642DE50D,0xB0533055,0x63EF3290, +0xB0049AB3,0x63B0426D,0xAFB63667,0x637114CC,0xAF6803A2,0x6331A9D4,0xAF1A0293, +0x62F201AC,0xAECC336C,0x62B21C7B,0xAE7E965B,0x6271FA69,0xAE312B92,0x62319B9D, +0xADE3F33E,0x61F1003F,0xAD96ED92,0x61B02876,0xAD4A1ABA,0x616F146C,0xACFD7AE8, +0x612DC447,0xACB10E4B,0x60EC3830,0xAC64D510,0x60AA7050,0xAC18CF69,0x60686CCF, +0xABCCFD83,0x60262DD6,0xAB815F8D,0x5FE3B38D,0xAB35F5B5,0x5FA0FE1F,0xAAEAC02C, +0x5F5E0DB3,0xAA9FBF1E,0x5F1AE274,0xAA54F2BA,0x5ED77C8A,0xAA0A5B2E,0x5E93DC1F, +0xA9BFF8A8,0x5E50015D,0xA975CB57,0x5E0BEC6E,0xA92BD367,0x5DC79D7C,0xA8E21106, +0x5D8314B1,0xA8988463,0x5D3E5237,0xA84F2DAA,0x5CF95638,0xA8060D08,0x5CB420E0, +0xA7BD22AC,0x5C6EB258,0xA7746EC0,0x5C290ACC,0xA72BF174,0x5BE32A67,0xA6E3AAF2, +0x5B9D1154,0xA69B9B68,0x5B56BFBD,0xA653C303,0x5B1035CF,0xA60C21EE,0x5AC973B5, +0xA5C4B855,0x5A82799A,0xA57D8666,0x5A3B47AB,0xA5368C4B,0x59F3DE12,0xA4EFCA31, +0x59AC3CFD,0xA4A94043,0x59646498,0xA462EEAC,0x591C550E,0xA41CD599,0x58D40E8C, +0xA3D6F534,0x588B9140,0xA3914DA8,0x5842DD54,0xA34BDF20,0x57F9F2F8,0xA306A9C8, +0x57B0D256,0xA2C1ADC9,0x57677B9D,0xA27CEB4F,0x571DEEFA,0xA2386284,0x56D42C99, +0xA1F41392,0x568A34A9,0xA1AFFEA3,0x56400758,0xA16C23E1,0x55F5A4D2,0xA1288376, +0x55AB0D46,0xA0E51D8C,0x556040E2,0xA0A1F24D,0x55153FD4,0xA05F01E1,0x54CA0A4B, +0xA01C4C73,0x547EA073,0x9FD9D22A,0x5433027D,0x9F979331,0x53E73097,0x9F558FB0, +0x539B2AF0,0x9F13C7D0,0x534EF1B5,0x9ED23BB9,0x53028518,0x9E90EB94,0x52B5E546, +0x9E4FD78A,0x5269126E,0x9E0EFFC1,0x521C0CC2,0x9DCE6463,0x51CED46E,0x9D8E0597, +0x518169A5,0x9D4DE385,0x5133CC94,0x9D0DFE54,0x50E5FD6D,0x9CCE562C,0x5097FC5E, +0x9C8EEB34,0x5049C999,0x9C4FBD93,0x4FFB654D,0x9C10CD70,0x4FACCFAB,0x9BD21AF3, +0x4F5E08E3,0x9B93A641,0x4F0F1126,0x9B556F81,0x4EBFE8A5,0x9B1776DA,0x4E708F8F, +0x9AD9BC71,0x4E210617,0x9A9C406E,0x4DD14C6E,0x9A5F02F5,0x4D8162C4,0x9A22042D, +0x4D31494B,0x99E5443B,0x4CE10034,0x99A8C345,0x4C9087B1,0x996C816F,0x4C3FDFF4, +0x99307EE0,0x4BEF092D,0x98F4BBBC,0x4B9E0390,0x98B93828,0x4B4CCF4D,0x987DF449, +0x4AFB6C98,0x9842F043,0x4AA9DBA2,0x98082C3B,0x4A581C9E,0x97CDA855,0x4A062FBD, +0x979364B5,0x49B41533,0x9759617F,0x4961CD33,0x971F9ED7,0x490F57EE,0x96E61CE0, +0x48BCB599,0x96ACDBBE,0x4869E665,0x9673DB94,0x4816EA86,0x963B1C86,0x47C3C22F, +0x96029EB6,0x47706D93,0x95CA6247,0x471CECE7,0x9592675C,0x46C9405C,0x955AAE17, +0x46756828,0x9523369C,0x4621647D,0x94EC010B,0x45CD358F,0x94B50D87,0x4578DB93, +0x947E5C33,0x452456BD,0x9447ED2F,0x44CFA740,0x9411C09E,0x447ACD50,0x93DBD6A0, +0x4425C923,0x93A62F57,0x43D09AED,0x9370CAE4,0x437B42E1,0x933BA968,0x4325C135, +0x9306CB04,0x42D0161E,0x92D22FD9,0x427A41D0,0x929DD806,0x42244481,0x9269C3AC, +0x41CE1E65,0x9235F2EC,0x4177CFB1,0x920265E4,0x4121589B,0x91CF1CB6,0x40CAB958, +0x919C1781,0x4073F21D,0x91695663,0x401D0321,0x9136D97D,0x3FC5EC98,0x9104A0EE, +0x3F6EAEB8,0x90D2ACD4,0x3F1749B8,0x90A0FD4E,0x3EBFBDCD,0x906F927C,0x3E680B2C, +0x903E6C7B,0x3E10320D,0x900D8B69,0x3DB832A6,0x8FDCEF66,0x3D600D2C,0x8FAC988F, +0x3D07C1D6,0x8F7C8701,0x3CAF50DA,0x8F4CBADB,0x3C56BA70,0x8F1D343A,0x3BFDFECD, +0x8EEDF33B,0x3BA51E29,0x8EBEF7FB,0x3B4C18BA,0x8E904298,0x3AF2EEB7,0x8E61D32E, +0x3A99A057,0x8E33A9DA,0x3A402DD2,0x8E05C6B7,0x39E6975E,0x8DD829E4,0x398CDD32, +0x8DAAD37B,0x3932FF87,0x8D7DC399,0x38D8FE93,0x8D50FA59,0x387EDA8E,0x8D2477D8, +0x382493B0,0x8CF83C30,0x37CA2A30,0x8CCC477D,0x376F9E46,0x8CA099DA,0x3714F02A, +0x8C753362,0x36BA2014,0x8C4A142F,0x365F2E3B,0x8C1F3C5D,0x36041AD9,0x8BF4AC05, +0x35A8E625,0x8BCA6343,0x354D9057,0x8BA0622F,0x34F219A8,0x8B76A8E4,0x34968250, +0x8B4D377C,0x343ACA87,0x8B240E11,0x33DEF287,0x8AFB2CBB,0x3382FA88,0x8AD29394, +0x3326E2C3,0x8AAA42B4,0x32CAAB6F,0x8A823A36,0x326E54C7,0x8A5A7A31,0x3211DF04, +0x8A3302BE,0x31B54A5E,0x8A0BD3F5,0x3158970E,0x89E4EDEF,0x30FBC54D,0x89BE50C3, +0x309ED556,0x8997FC8A,0x3041C761,0x8971F15A,0x2FE49BA7,0x894C2F4C,0x2F875262, +0x8926B677,0x2F29EBCC,0x890186F2,0x2ECC681E,0x88DCA0D3,0x2E6EC792,0x88B80432, +0x2E110A62,0x8893B125,0x2DB330C7,0x886FA7C2,0x2D553AFC,0x884BE821,0x2CF72939, +0x88287256,0x2C98FBBA,0x88054677,0x2C3AB2B9,0x87E2649B,0x2BDC4E6F,0x87BFCCD7, +0x2B7DCF17,0x879D7F41,0x2B1F34EB,0x877B7BEC,0x2AC08026,0x8759C2EF,0x2A61B101, +0x8738545E,0x2A02C7B8,0x8717304E,0x29A3C485,0x86F656D3,0x2944A7A2,0x86D5C802, +0x28E5714B,0x86B583EE,0x288621B9,0x86958AAC,0x2826B928,0x8675DC4F,0x27C737D3, +0x865678EB,0x27679DF4,0x86376092,0x2707EBC7,0x86189359,0x26A82186,0x85FA1153, +0x26483F6C,0x85DBDA91,0x25E845B6,0x85BDEF28,0x2588349D,0x85A04F28,0x25280C5E, +0x8582FAA5,0x24C7CD33,0x8565F1B0,0x24677758,0x8549345C,0x24070B08,0x852CC2BB, +0x23A6887F,0x85109CDD,0x2345EFF8,0x84F4C2D4,0x22E541AF,0x84D934B1,0x22847DE0, +0x84BDF286,0x2223A4C5,0x84A2FC62,0x21C2B69C,0x84885258,0x2161B3A0,0x846DF477, +0x21009C0C,0x8453E2CF,0x209F701C,0x843A1D70,0x203E300D,0x8420A46C,0x1FDCDC1B, +0x840777D0,0x1F7B7481,0x83EE97AD,0x1F19F97B,0x83D60412,0x1EB86B46,0x83BDBD0E, +0x1E56CA1E,0x83A5C2B0,0x1DF5163F,0x838E1507,0x1D934FE5,0x8376B422,0x1D31774D, +0x835FA00F,0x1CCF8CB3,0x8348D8DC,0x1C6D9053,0x83325E97,0x1C0B826A,0x831C314E, +0x1BA96335,0x83065110,0x1B4732EF,0x82F0BDE8,0x1AE4F1D6,0x82DB77E5,0x1A82A026, +0x82C67F14,0x1A203E1B,0x82B1D381,0x19BDCBF3,0x829D753A,0x195B49EA,0x8289644B, +0x18F8B83C,0x8275A0C0,0x18961728,0x82622AA6,0x183366E9,0x824F0208,0x17D0A7BC, +0x823C26F3,0x176DD9DE,0x82299971,0x170AFD8D,0x82175990,0x16A81305,0x82056758, +0x16451A83,0x81F3C2D7,0x15E21445,0x81E26C16,0x157F0086,0x81D16321,0x151BDF86, +0x81C0A801,0x14B8B17F,0x81B03AC2,0x145576B1,0x81A01B6D,0x13F22F58,0x81904A0C, +0x138EDBB1,0x8180C6A9,0x132B7BF9,0x8171914E,0x12C8106F,0x8162AA04,0x1264994E, +0x815410D4,0x120116D5,0x8145C5C7,0x119D8941,0x8137C8E6,0x1139F0CF,0x812A1A3A, +0x10D64DBD,0x811CB9CA,0x1072A048,0x810FA7A0,0x100EE8AD,0x8102E3C4,0x0FAB272B, +0x80F66E3C,0x0F475BFF,0x80EA4712,0x0EE38766,0x80DE6E4C,0x0E7FA99E,0x80D2E3F2, +0x0E1BC2E4,0x80C7A80A,0x0DB7D376,0x80BCBA9D,0x0D53DB92,0x80B21BAF,0x0CEFDB76, +0x80A7CB49,0x0C8BD35E,0x809DC971,0x0C27C389,0x8094162C,0x0BC3AC35,0x808AB180, +0x0B5F8D9F,0x80819B74,0x0AFB6805,0x8078D40D,0x0A973BA5,0x80705B50,0x0A3308BD, +0x80683143,0x09CECF89,0x806055EB,0x096A9049,0x8058C94C,0x09064B3A,0x80518B6B, +0x08A2009A,0x804A9C4D,0x083DB0A7,0x8043FBF6,0x07D95B9E,0x803DAA6A,0x077501BE, +0x8037A7AC,0x0710A345,0x8031F3C2,0x06AC406F,0x802C8EAD,0x0647D97C,0x80277872, +0x05E36EA9,0x8022B114,0x057F0035,0x801E3895,0x051A8E5C,0x801A0EF8,0x04B6195D, +0x80163440,0x0451A177,0x8012A86F,0x03ED26E6,0x800F6B88,0x0388A9EA,0x800C7D8C, +0x03242ABF,0x8009DE7E,0x02BFA9A4,0x80078E5E,0x025B26D7,0x80058D2F,0x01F6A297, +0x8003DAF1,0x01921D20,0x800277A6,0x012D96B1,0x8001634E,0x00C90F88,0x80009DEA, +0x006487E3,0x8000277A,0x00000000,0x80000000,0xFF9B781D,0x8000277A,0xFF36F078, +0x80009DEA,0xFED2694F,0x8001634E,0xFE6DE2E0,0x800277A6,0xFE095D69,0x8003DAF1, +0xFDA4D929,0x80058D2F,0xFD40565C,0x80078E5E,0xFCDBD541,0x8009DE7E,0xFC775616, +0x800C7D8C,0xFC12D91A,0x800F6B88,0xFBAE5E89,0x8012A86F,0xFB49E6A3,0x80163440, +0xFAE571A4,0x801A0EF8,0xFA80FFCB,0x801E3895,0xFA1C9157,0x8022B114,0xF9B82684, +0x80277872,0xF953BF91,0x802C8EAD,0xF8EF5CBB,0x8031F3C2,0xF88AFE42,0x8037A7AC, +0xF826A462,0x803DAA6A,0xF7C24F59,0x8043FBF6,0xF75DFF66,0x804A9C4D,0xF6F9B4C6, +0x80518B6B,0xF6956FB7,0x8058C94C,0xF6313077,0x806055EB,0xF5CCF743,0x80683143, +0xF568C45B,0x80705B50,0xF50497FB,0x8078D40D,0xF4A07261,0x80819B74,0xF43C53CB, +0x808AB180,0xF3D83C77,0x8094162C,0xF3742CA2,0x809DC971,0xF310248A,0x80A7CB49, +0xF2AC246E,0x80B21BAF,0xF2482C8A,0x80BCBA9D,0xF1E43D1C,0x80C7A80A,0xF1805662, +0x80D2E3F2,0xF11C789A,0x80DE6E4C,0xF0B8A401,0x80EA4712,0xF054D8D5,0x80F66E3C, +0xEFF11753,0x8102E3C4,0xEF8D5FB8,0x810FA7A0,0xEF29B243,0x811CB9CA,0xEEC60F31, +0x812A1A3A,0xEE6276BF,0x8137C8E6,0xEDFEE92B,0x8145C5C7,0xED9B66B2,0x815410D4, +0xED37EF91,0x8162AA04,0xECD48407,0x8171914E,0xEC71244F,0x8180C6A9,0xEC0DD0A8, +0x81904A0C,0xEBAA894F,0x81A01B6D,0xEB474E81,0x81B03AC2,0xEAE4207A,0x81C0A801, +0xEA80FF7A,0x81D16321,0xEA1DEBBB,0x81E26C16,0xE9BAE57D,0x81F3C2D7,0xE957ECFB, +0x82056758,0xE8F50273,0x82175990,0xE8922622,0x82299971,0xE82F5844,0x823C26F3, +0xE7CC9917,0x824F0208,0xE769E8D8,0x82622AA6,0xE70747C4,0x8275A0C0,0xE6A4B616, +0x8289644B,0xE642340D,0x829D753A,0xE5DFC1E5,0x82B1D381,0xE57D5FDA,0x82C67F14, +0xE51B0E2A,0x82DB77E5,0xE4B8CD11,0x82F0BDE8,0xE4569CCB,0x83065110,0xE3F47D96, +0x831C314E,0xE3926FAD,0x83325E97,0xE330734D,0x8348D8DC,0xE2CE88B3,0x835FA00F, +0xE26CB01B,0x8376B422,0xE20AE9C1,0x838E1507,0xE1A935E2,0x83A5C2B0,0xE14794BA, +0x83BDBD0E,0xE0E60685,0x83D60412,0xE0848B7F,0x83EE97AD,0xE02323E5,0x840777D0, +0xDFC1CFF3,0x8420A46C,0xDF608FE4,0x843A1D70,0xDEFF63F4,0x8453E2CF,0xDE9E4C60, +0x846DF477,0xDE3D4964,0x84885258,0xDDDC5B3B,0x84A2FC62,0xDD7B8220,0x84BDF286, +0xDD1ABE51,0x84D934B1,0xDCBA1008,0x84F4C2D4,0xDC597781,0x85109CDD,0xDBF8F4F8, +0x852CC2BB,0xDB9888A8,0x8549345C,0xDB3832CD,0x8565F1B0,0xDAD7F3A2,0x8582FAA5, +0xDA77CB63,0x85A04F28,0xDA17BA4A,0x85BDEF28,0xD9B7C094,0x85DBDA91,0xD957DE7A, +0x85FA1153,0xD8F81439,0x86189359,0xD898620C,0x86376092,0xD838C82D,0x865678EB, +0xD7D946D8,0x8675DC4F,0xD779DE47,0x86958AAC,0xD71A8EB5,0x86B583EE,0xD6BB585E, +0x86D5C802,0xD65C3B7B,0x86F656D3,0xD5FD3848,0x8717304E,0xD59E4EFF,0x8738545E, +0xD53F7FDA,0x8759C2EF,0xD4E0CB15,0x877B7BEC,0xD48230E9,0x879D7F41,0xD423B191, +0x87BFCCD7,0xD3C54D47,0x87E2649B,0xD3670446,0x88054677,0xD308D6C7,0x88287256, +0xD2AAC504,0x884BE821,0xD24CCF39,0x886FA7C2,0xD1EEF59E,0x8893B125,0xD191386E, +0x88B80432,0xD13397E2,0x88DCA0D3,0xD0D61434,0x890186F2,0xD078AD9E,0x8926B677, +0xD01B6459,0x894C2F4C,0xCFBE389F,0x8971F15A,0xCF612AAA,0x8997FC8A,0xCF043AB3, +0x89BE50C3,0xCEA768F2,0x89E4EDEF,0xCE4AB5A2,0x8A0BD3F5,0xCDEE20FC,0x8A3302BE, +0xCD91AB39,0x8A5A7A31,0xCD355491,0x8A823A36,0xCCD91D3D,0x8AAA42B4,0xCC7D0578, +0x8AD29394,0xCC210D79,0x8AFB2CBB,0xCBC53579,0x8B240E11,0xCB697DB0,0x8B4D377C, +0xCB0DE658,0x8B76A8E4,0xCAB26FA9,0x8BA0622F,0xCA5719DB,0x8BCA6343,0xC9FBE527, +0x8BF4AC05,0xC9A0D1C5,0x8C1F3C5D,0xC945DFEC,0x8C4A142F,0xC8EB0FD6,0x8C753362, +0xC89061BA,0x8CA099DA,0xC835D5D0,0x8CCC477D,0xC7DB6C50,0x8CF83C30,0xC7812572, +0x8D2477D8,0xC727016D,0x8D50FA59,0xC6CD0079,0x8D7DC399,0xC67322CE,0x8DAAD37B, +0xC61968A2,0x8DD829E4,0xC5BFD22E,0x8E05C6B7,0xC5665FA9,0x8E33A9DA,0xC50D1149, +0x8E61D32E,0xC4B3E746,0x8E904298,0xC45AE1D7,0x8EBEF7FB,0xC4020133,0x8EEDF33B, +0xC3A94590,0x8F1D343A,0xC350AF26,0x8F4CBADB,0xC2F83E2A,0x8F7C8701,0xC29FF2D4, +0x8FAC988F,0xC247CD5A,0x8FDCEF66,0xC1EFCDF3,0x900D8B69,0xC197F4D4,0x903E6C7B, +0xC1404233,0x906F927C,0xC0E8B648,0x90A0FD4E,0xC0915148,0x90D2ACD4,0xC03A1368, +0x9104A0EE,0xBFE2FCDF,0x9136D97D,0xBF8C0DE3,0x91695663,0xBF3546A8,0x919C1781, +0xBEDEA765,0x91CF1CB6,0xBE88304F,0x920265E4,0xBE31E19B,0x9235F2EC,0xBDDBBB7F, +0x9269C3AC,0xBD85BE30,0x929DD806,0xBD2FE9E2,0x92D22FD9,0xBCDA3ECB,0x9306CB04, +0xBC84BD1F,0x933BA968,0xBC2F6513,0x9370CAE4,0xBBDA36DD,0x93A62F57,0xBB8532B0, +0x93DBD6A0,0xBB3058C0,0x9411C09E,0xBADBA943,0x9447ED2F,0xBA87246D,0x947E5C33, +0xBA32CA71,0x94B50D87,0xB9DE9B83,0x94EC010B,0xB98A97D8,0x9523369C,0xB936BFA4, +0x955AAE17,0xB8E31319,0x9592675C,0xB88F926D,0x95CA6247,0xB83C3DD1,0x96029EB6, +0xB7E9157A,0x963B1C86,0xB796199B,0x9673DB94,0xB7434A67,0x96ACDBBE,0xB6F0A812, +0x96E61CE0,0xB69E32CD,0x971F9ED7,0xB64BEACD,0x9759617F,0xB5F9D043,0x979364B5, +0xB5A7E362,0x97CDA855,0xB556245E,0x98082C3B,0xB5049368,0x9842F043,0xB4B330B3, +0x987DF449,0xB461FC70,0x98B93828,0xB410F6D3,0x98F4BBBC,0xB3C0200C,0x99307EE0, +0xB36F784F,0x996C816F,0xB31EFFCC,0x99A8C345,0xB2CEB6B5,0x99E5443B,0xB27E9D3C, +0x9A22042D,0xB22EB392,0x9A5F02F5,0xB1DEF9E9,0x9A9C406E,0xB18F7071,0x9AD9BC71, +0xB140175B,0x9B1776DA,0xB0F0EEDA,0x9B556F81,0xB0A1F71D,0x9B93A641,0xB0533055, +0x9BD21AF3,0xB0049AB3,0x9C10CD70,0xAFB63667,0x9C4FBD93,0xAF6803A2,0x9C8EEB34, +0xAF1A0293,0x9CCE562C,0xAECC336C,0x9D0DFE54,0xAE7E965B,0x9D4DE385,0xAE312B92, +0x9D8E0597,0xADE3F33E,0x9DCE6463,0xAD96ED92,0x9E0EFFC1,0xAD4A1ABA,0x9E4FD78A, +0xACFD7AE8,0x9E90EB94,0xACB10E4B,0x9ED23BB9,0xAC64D510,0x9F13C7D0,0xAC18CF69, +0x9F558FB0,0xABCCFD83,0x9F979331,0xAB815F8D,0x9FD9D22A,0xAB35F5B5,0xA01C4C73, +0xAAEAC02C,0xA05F01E1,0xAA9FBF1E,0xA0A1F24D,0xAA54F2BA,0xA0E51D8C,0xAA0A5B2E, +0xA1288376,0xA9BFF8A8,0xA16C23E1,0xA975CB57,0xA1AFFEA3,0xA92BD367,0xA1F41392, +0xA8E21106,0xA2386284,0xA8988463,0xA27CEB4F,0xA84F2DAA,0xA2C1ADC9,0xA8060D08, +0xA306A9C8,0xA7BD22AC,0xA34BDF20,0xA7746EC0,0xA3914DA8,0xA72BF174,0xA3D6F534, +0xA6E3AAF2,0xA41CD599,0xA69B9B68,0xA462EEAC,0xA653C303,0xA4A94043,0xA60C21EE, +0xA4EFCA31,0xA5C4B855,0xA5368C4B,0xA57D8666,0xA57D8666,0xA5368C4B,0xA5C4B855, +0xA4EFCA31,0xA60C21EE,0xA4A94043,0xA653C303,0xA462EEAC,0xA69B9B68,0xA41CD599, +0xA6E3AAF2,0xA3D6F534,0xA72BF174,0xA3914DA8,0xA7746EC0,0xA34BDF20,0xA7BD22AC, +0xA306A9C8,0xA8060D08,0xA2C1ADC9,0xA84F2DAA,0xA27CEB4F,0xA8988463,0xA2386284, +0xA8E21106,0xA1F41392,0xA92BD367,0xA1AFFEA3,0xA975CB57,0xA16C23E1,0xA9BFF8A8, +0xA1288376,0xAA0A5B2E,0xA0E51D8C,0xAA54F2BA,0xA0A1F24D,0xAA9FBF1E,0xA05F01E1, +0xAAEAC02C,0xA01C4C73,0xAB35F5B5,0x9FD9D22A,0xAB815F8D,0x9F979331,0xABCCFD83, +0x9F558FB0,0xAC18CF69,0x9F13C7D0,0xAC64D510,0x9ED23BB9,0xACB10E4B,0x9E90EB94, +0xACFD7AE8,0x9E4FD78A,0xAD4A1ABA,0x9E0EFFC1,0xAD96ED92,0x9DCE6463,0xADE3F33E, +0x9D8E0597,0xAE312B92,0x9D4DE385,0xAE7E965B,0x9D0DFE54,0xAECC336C,0x9CCE562C, +0xAF1A0293,0x9C8EEB34,0xAF6803A2,0x9C4FBD93,0xAFB63667,0x9C10CD70,0xB0049AB3, +0x9BD21AF3,0xB0533055,0x9B93A641,0xB0A1F71D,0x9B556F81,0xB0F0EEDA,0x9B1776DA, +0xB140175B,0x9AD9BC71,0xB18F7071,0x9A9C406E,0xB1DEF9E9,0x9A5F02F5,0xB22EB392, +0x9A22042D,0xB27E9D3C,0x99E5443B,0xB2CEB6B5,0x99A8C345,0xB31EFFCC,0x996C816F, +0xB36F784F,0x99307EE0,0xB3C0200C,0x98F4BBBC,0xB410F6D3,0x98B93828,0xB461FC70, +0x987DF449,0xB4B330B3,0x9842F043,0xB5049368,0x98082C3B,0xB556245E,0x97CDA855, +0xB5A7E362,0x979364B5,0xB5F9D043,0x9759617F,0xB64BEACD,0x971F9ED7,0xB69E32CD, +0x96E61CE0,0xB6F0A812,0x96ACDBBE,0xB7434A67,0x9673DB94,0xB796199B,0x963B1C86, +0xB7E9157A,0x96029EB6,0xB83C3DD1,0x95CA6247,0xB88F926D,0x9592675C,0xB8E31319, +0x955AAE17,0xB936BFA4,0x9523369C,0xB98A97D8,0x94EC010B,0xB9DE9B83,0x94B50D87, +0xBA32CA71,0x947E5C33,0xBA87246D,0x9447ED2F,0xBADBA943,0x9411C09E,0xBB3058C0, +0x93DBD6A0,0xBB8532B0,0x93A62F57,0xBBDA36DD,0x9370CAE4,0xBC2F6513,0x933BA968, +0xBC84BD1F,0x9306CB04,0xBCDA3ECB,0x92D22FD9,0xBD2FE9E2,0x929DD806,0xBD85BE30, +0x9269C3AC,0xBDDBBB7F,0x9235F2EC,0xBE31E19B,0x920265E4,0xBE88304F,0x91CF1CB6, +0xBEDEA765,0x919C1781,0xBF3546A8,0x91695663,0xBF8C0DE3,0x9136D97D,0xBFE2FCDF, +0x9104A0EE,0xC03A1368,0x90D2ACD4,0xC0915148,0x90A0FD4E,0xC0E8B648,0x906F927C, +0xC1404233,0x903E6C7B,0xC197F4D4,0x900D8B69,0xC1EFCDF3,0x8FDCEF66,0xC247CD5A, +0x8FAC988F,0xC29FF2D4,0x8F7C8701,0xC2F83E2A,0x8F4CBADB,0xC350AF26,0x8F1D343A, +0xC3A94590,0x8EEDF33B,0xC4020133,0x8EBEF7FB,0xC45AE1D7,0x8E904298,0xC4B3E746, +0x8E61D32E,0xC50D1149,0x8E33A9DA,0xC5665FA9,0x8E05C6B7,0xC5BFD22E,0x8DD829E4, +0xC61968A2,0x8DAAD37B,0xC67322CE,0x8D7DC399,0xC6CD0079,0x8D50FA59,0xC727016D, +0x8D2477D8,0xC7812572,0x8CF83C30,0xC7DB6C50,0x8CCC477D,0xC835D5D0,0x8CA099DA, +0xC89061BA,0x8C753362,0xC8EB0FD6,0x8C4A142F,0xC945DFEC,0x8C1F3C5D,0xC9A0D1C5, +0x8BF4AC05,0xC9FBE527,0x8BCA6343,0xCA5719DB,0x8BA0622F,0xCAB26FA9,0x8B76A8E4, +0xCB0DE658,0x8B4D377C,0xCB697DB0,0x8B240E11,0xCBC53579,0x8AFB2CBB,0xCC210D79, +0x8AD29394,0xCC7D0578,0x8AAA42B4,0xCCD91D3D,0x8A823A36,0xCD355491,0x8A5A7A31, +0xCD91AB39,0x8A3302BE,0xCDEE20FC,0x8A0BD3F5,0xCE4AB5A2,0x89E4EDEF,0xCEA768F2, +0x89BE50C3,0xCF043AB3,0x8997FC8A,0xCF612AAA,0x8971F15A,0xCFBE389F,0x894C2F4C, +0xD01B6459,0x8926B677,0xD078AD9E,0x890186F2,0xD0D61434,0x88DCA0D3,0xD13397E2, +0x88B80432,0xD191386E,0x8893B125,0xD1EEF59E,0x886FA7C2,0xD24CCF39,0x884BE821, +0xD2AAC504,0x88287256,0xD308D6C7,0x88054677,0xD3670446,0x87E2649B,0xD3C54D47, +0x87BFCCD7,0xD423B191,0x879D7F41,0xD48230E9,0x877B7BEC,0xD4E0CB15,0x8759C2EF, +0xD53F7FDA,0x8738545E,0xD59E4EFF,0x8717304E,0xD5FD3848,0x86F656D3,0xD65C3B7B, +0x86D5C802,0xD6BB585E,0x86B583EE,0xD71A8EB5,0x86958AAC,0xD779DE47,0x8675DC4F, +0xD7D946D8,0x865678EB,0xD838C82D,0x86376092,0xD898620C,0x86189359,0xD8F81439, +0x85FA1153,0xD957DE7A,0x85DBDA91,0xD9B7C094,0x85BDEF28,0xDA17BA4A,0x85A04F28, +0xDA77CB63,0x8582FAA5,0xDAD7F3A2,0x8565F1B0,0xDB3832CD,0x8549345C,0xDB9888A8, +0x852CC2BB,0xDBF8F4F8,0x85109CDD,0xDC597781,0x84F4C2D4,0xDCBA1008,0x84D934B1, +0xDD1ABE51,0x84BDF286,0xDD7B8220,0x84A2FC62,0xDDDC5B3B,0x84885258,0xDE3D4964, +0x846DF477,0xDE9E4C60,0x8453E2CF,0xDEFF63F4,0x843A1D70,0xDF608FE4,0x8420A46C, +0xDFC1CFF3,0x840777D0,0xE02323E5,0x83EE97AD,0xE0848B7F,0x83D60412,0xE0E60685, +0x83BDBD0E,0xE14794BA,0x83A5C2B0,0xE1A935E2,0x838E1507,0xE20AE9C1,0x8376B422, +0xE26CB01B,0x835FA00F,0xE2CE88B3,0x8348D8DC,0xE330734D,0x83325E97,0xE3926FAD, +0x831C314E,0xE3F47D96,0x83065110,0xE4569CCB,0x82F0BDE8,0xE4B8CD11,0x82DB77E5, +0xE51B0E2A,0x82C67F14,0xE57D5FDA,0x82B1D381,0xE5DFC1E5,0x829D753A,0xE642340D, +0x8289644B,0xE6A4B616,0x8275A0C0,0xE70747C4,0x82622AA6,0xE769E8D8,0x824F0208, +0xE7CC9917,0x823C26F3,0xE82F5844,0x82299971,0xE8922622,0x82175990,0xE8F50273, +0x82056758,0xE957ECFB,0x81F3C2D7,0xE9BAE57D,0x81E26C16,0xEA1DEBBB,0x81D16321, +0xEA80FF7A,0x81C0A801,0xEAE4207A,0x81B03AC2,0xEB474E81,0x81A01B6D,0xEBAA894F, +0x81904A0C,0xEC0DD0A8,0x8180C6A9,0xEC71244F,0x8171914E,0xECD48407,0x8162AA04, +0xED37EF91,0x815410D4,0xED9B66B2,0x8145C5C7,0xEDFEE92B,0x8137C8E6,0xEE6276BF, +0x812A1A3A,0xEEC60F31,0x811CB9CA,0xEF29B243,0x810FA7A0,0xEF8D5FB8,0x8102E3C4, +0xEFF11753,0x80F66E3C,0xF054D8D5,0x80EA4712,0xF0B8A401,0x80DE6E4C,0xF11C789A, +0x80D2E3F2,0xF1805662,0x80C7A80A,0xF1E43D1C,0x80BCBA9D,0xF2482C8A,0x80B21BAF, +0xF2AC246E,0x80A7CB49,0xF310248A,0x809DC971,0xF3742CA2,0x8094162C,0xF3D83C77, +0x808AB180,0xF43C53CB,0x80819B74,0xF4A07261,0x8078D40D,0xF50497FB,0x80705B50, +0xF568C45B,0x80683143,0xF5CCF743,0x806055EB,0xF6313077,0x8058C94C,0xF6956FB7, +0x80518B6B,0xF6F9B4C6,0x804A9C4D,0xF75DFF66,0x8043FBF6,0xF7C24F59,0x803DAA6A, +0xF826A462,0x8037A7AC,0xF88AFE42,0x8031F3C2,0xF8EF5CBB,0x802C8EAD,0xF953BF91, +0x80277872,0xF9B82684,0x8022B114,0xFA1C9157,0x801E3895,0xFA80FFCB,0x801A0EF8, +0xFAE571A4,0x80163440,0xFB49E6A3,0x8012A86F,0xFBAE5E89,0x800F6B88,0xFC12D91A, +0x800C7D8C,0xFC775616,0x8009DE7E,0xFCDBD541,0x80078E5E,0xFD40565C,0x80058D2F, +0xFDA4D929,0x8003DAF1,0xFE095D69,0x800277A6,0xFE6DE2E0,0x8001634E,0xFED2694F, +0x80009DEA,0xFF36F078,0x8000277A,0xFF9B781D,0x7FFFFFFF,0x00000000,0x7FFD885A, +0xFE6DE2E0,0x7FF62182,0xFCDBD541,0x7FE9CBC0,0xFB49E6A3,0x7FD8878E,0xF9B82684, +0x7FC25596,0xF826A462,0x7FA736B4,0xF6956FB7,0x7F872BF3,0xF50497FB,0x7F62368F, +0xF3742CA2,0x7F3857F6,0xF1E43D1C,0x7F0991C4,0xF054D8D5,0x7ED5E5C6,0xEEC60F31, +0x7E9D55FC,0xED37EF91,0x7E5FE493,0xEBAA894F,0x7E1D93EA,0xEA1DEBBB,0x7DD6668F, +0xE8922622,0x7D8A5F40,0xE70747C4,0x7D3980EC,0xE57D5FDA,0x7CE3CEB2,0xE3F47D96, +0x7C894BDE,0xE26CB01B,0x7C29FBEE,0xE0E60685,0x7BC5E290,0xDF608FE4,0x7B5D039E, +0xDDDC5B3B,0x7AEF6323,0xDC597781,0x7A7D055B,0xDAD7F3A2,0x7A05EEAD,0xD957DE7A, +0x798A23B1,0xD7D946D8,0x7909A92D,0xD65C3B7B,0x78848414,0xD4E0CB15,0x77FAB989, +0xD3670446,0x776C4EDB,0xD1EEF59E,0x76D94989,0xD078AD9E,0x7641AF3D,0xCF043AB3, +0x75A585CF,0xCD91AB39,0x7504D345,0xCC210D79,0x745F9DD1,0xCAB26FA9,0x73B5EBD1, +0xC945DFEC,0x7307C3D0,0xC7DB6C50,0x72552C85,0xC67322CE,0x719E2CD2,0xC50D1149, +0x70E2CBC6,0xC3A94590,0x7023109A,0xC247CD5A,0x6F5F02B2,0xC0E8B648,0x6E96A99D, +0xBF8C0DE3,0x6DCA0D14,0xBE31E19B,0x6CF934FC,0xBCDA3ECB,0x6C242960,0xBB8532B0, +0x6B4AF279,0xBA32CA71,0x6A6D98A4,0xB8E31319,0x698C246C,0xB796199B,0x68A69E81, +0xB64BEACD,0x67BD0FBD,0xB5049368,0x66CF8120,0xB3C0200C,0x65DDFBD3,0xB27E9D3C, +0x64E88926,0xB140175B,0x63EF3290,0xB0049AB3,0x62F201AC,0xAECC336C,0x61F1003F, +0xAD96ED92,0x60EC3830,0xAC64D510,0x5FE3B38D,0xAB35F5B5,0x5ED77C8A,0xAA0A5B2E, +0x5DC79D7C,0xA8E21106,0x5CB420E0,0xA7BD22AC,0x5B9D1154,0xA69B9B68,0x5A82799A, +0xA57D8666,0x59646498,0xA462EEAC,0x5842DD54,0xA34BDF20,0x571DEEFA,0xA2386284, +0x55F5A4D2,0xA1288376,0x54CA0A4B,0xA01C4C73,0x539B2AF0,0x9F13C7D0,0x5269126E, +0x9E0EFFC1,0x5133CC94,0x9D0DFE54,0x4FFB654D,0x9C10CD70,0x4EBFE8A5,0x9B1776DA, +0x4D8162C4,0x9A22042D,0x4C3FDFF4,0x99307EE0,0x4AFB6C98,0x9842F043,0x49B41533, +0x9759617F,0x4869E665,0x9673DB94,0x471CECE7,0x9592675C,0x45CD358F,0x94B50D87, +0x447ACD50,0x93DBD6A0,0x4325C135,0x9306CB04,0x41CE1E65,0x9235F2EC,0x4073F21D, +0x91695663,0x3F1749B8,0x90A0FD4E,0x3DB832A6,0x8FDCEF66,0x3C56BA70,0x8F1D343A, +0x3AF2EEB7,0x8E61D32E,0x398CDD32,0x8DAAD37B,0x382493B0,0x8CF83C30,0x36BA2014, +0x8C4A142F,0x354D9057,0x8BA0622F,0x33DEF287,0x8AFB2CBB,0x326E54C7,0x8A5A7A31, +0x30FBC54D,0x89BE50C3,0x2F875262,0x8926B677,0x2E110A62,0x8893B125,0x2C98FBBA, +0x88054677,0x2B1F34EB,0x877B7BEC,0x29A3C485,0x86F656D3,0x2826B928,0x8675DC4F, +0x26A82186,0x85FA1153,0x25280C5E,0x8582FAA5,0x23A6887F,0x85109CDD,0x2223A4C5, +0x84A2FC62,0x209F701C,0x843A1D70,0x1F19F97B,0x83D60412,0x1D934FE5,0x8376B422, +0x1C0B826A,0x831C314E,0x1A82A026,0x82C67F14,0x18F8B83C,0x8275A0C0,0x176DD9DE, +0x82299971,0x15E21445,0x81E26C16,0x145576B1,0x81A01B6D,0x12C8106F,0x8162AA04, +0x1139F0CF,0x812A1A3A,0x0FAB272B,0x80F66E3C,0x0E1BC2E4,0x80C7A80A,0x0C8BD35E, +0x809DC971,0x0AFB6805,0x8078D40D,0x096A9049,0x8058C94C,0x07D95B9E,0x803DAA6A, +0x0647D97C,0x80277872,0x04B6195D,0x80163440,0x03242ABF,0x8009DE7E,0x01921D20, +0x800277A6,0x00000000,0x80000000,0xFE6DE2E0,0x800277A6,0xFCDBD541,0x8009DE7E, +0xFB49E6A3,0x80163440,0xF9B82684,0x80277872,0xF826A462,0x803DAA6A,0xF6956FB7, +0x8058C94C,0xF50497FB,0x8078D40D,0xF3742CA2,0x809DC971,0xF1E43D1C,0x80C7A80A, +0xF054D8D5,0x80F66E3C,0xEEC60F31,0x812A1A3A,0xED37EF91,0x8162AA04,0xEBAA894F, +0x81A01B6D,0xEA1DEBBB,0x81E26C16,0xE8922622,0x82299971,0xE70747C4,0x8275A0C0, +0xE57D5FDA,0x82C67F14,0xE3F47D96,0x831C314E,0xE26CB01B,0x8376B422,0xE0E60685, +0x83D60412,0xDF608FE4,0x843A1D70,0xDDDC5B3B,0x84A2FC62,0xDC597781,0x85109CDD, +0xDAD7F3A2,0x8582FAA5,0xD957DE7A,0x85FA1153,0xD7D946D8,0x8675DC4F,0xD65C3B7B, +0x86F656D3,0xD4E0CB15,0x877B7BEC,0xD3670446,0x88054677,0xD1EEF59E,0x8893B125, +0xD078AD9E,0x8926B677,0xCF043AB3,0x89BE50C3,0xCD91AB39,0x8A5A7A31,0xCC210D79, +0x8AFB2CBB,0xCAB26FA9,0x8BA0622F,0xC945DFEC,0x8C4A142F,0xC7DB6C50,0x8CF83C30, +0xC67322CE,0x8DAAD37B,0xC50D1149,0x8E61D32E,0xC3A94590,0x8F1D343A,0xC247CD5A, +0x8FDCEF66,0xC0E8B648,0x90A0FD4E,0xBF8C0DE3,0x91695663,0xBE31E19B,0x9235F2EC, +0xBCDA3ECB,0x9306CB04,0xBB8532B0,0x93DBD6A0,0xBA32CA71,0x94B50D87,0xB8E31319, +0x9592675C,0xB796199B,0x9673DB94,0xB64BEACD,0x9759617F,0xB5049368,0x9842F043, +0xB3C0200C,0x99307EE0,0xB27E9D3C,0x9A22042D,0xB140175B,0x9B1776DA,0xB0049AB3, +0x9C10CD70,0xAECC336C,0x9D0DFE54,0xAD96ED92,0x9E0EFFC1,0xAC64D510,0x9F13C7D0, +0xAB35F5B5,0xA01C4C73,0xAA0A5B2E,0xA1288376,0xA8E21106,0xA2386284,0xA7BD22AC, +0xA34BDF20,0xA69B9B68,0xA462EEAC,0xA57D8666,0xA57D8666,0xA462EEAC,0xA69B9B68, +0xA34BDF20,0xA7BD22AC,0xA2386284,0xA8E21106,0xA1288376,0xAA0A5B2E,0xA01C4C73, +0xAB35F5B5,0x9F13C7D0,0xAC64D510,0x9E0EFFC1,0xAD96ED92,0x9D0DFE54,0xAECC336C, +0x9C10CD70,0xB0049AB3,0x9B1776DA,0xB140175B,0x9A22042D,0xB27E9D3C,0x99307EE0, +0xB3C0200C,0x9842F043,0xB5049368,0x9759617F,0xB64BEACD,0x9673DB94,0xB796199B, +0x9592675C,0xB8E31319,0x94B50D87,0xBA32CA71,0x93DBD6A0,0xBB8532B0,0x9306CB04, +0xBCDA3ECB,0x9235F2EC,0xBE31E19B,0x91695663,0xBF8C0DE3,0x90A0FD4E,0xC0E8B648, +0x8FDCEF66,0xC247CD5A,0x8F1D343A,0xC3A94590,0x8E61D32E,0xC50D1149,0x8DAAD37B, +0xC67322CE,0x8CF83C30,0xC7DB6C50,0x8C4A142F,0xC945DFEC,0x8BA0622F,0xCAB26FA9, +0x8AFB2CBB,0xCC210D79,0x8A5A7A31,0xCD91AB39,0x89BE50C3,0xCF043AB3,0x8926B677, +0xD078AD9E,0x8893B125,0xD1EEF59E,0x88054677,0xD3670446,0x877B7BEC,0xD4E0CB15, +0x86F656D3,0xD65C3B7B,0x8675DC4F,0xD7D946D8,0x85FA1153,0xD957DE7A,0x8582FAA5, +0xDAD7F3A2,0x85109CDD,0xDC597781,0x84A2FC62,0xDDDC5B3B,0x843A1D70,0xDF608FE4, +0x83D60412,0xE0E60685,0x8376B422,0xE26CB01B,0x831C314E,0xE3F47D96,0x82C67F14, +0xE57D5FDA,0x8275A0C0,0xE70747C4,0x82299971,0xE8922622,0x81E26C16,0xEA1DEBBB, +0x81A01B6D,0xEBAA894F,0x8162AA04,0xED37EF91,0x812A1A3A,0xEEC60F31,0x80F66E3C, +0xF054D8D5,0x80C7A80A,0xF1E43D1C,0x809DC971,0xF3742CA2,0x8078D40D,0xF50497FB, +0x8058C94C,0xF6956FB7,0x803DAA6A,0xF826A462,0x80277872,0xF9B82684,0x80163440, +0xFB49E6A3,0x8009DE7E,0xFCDBD541,0x800277A6,0xFE6DE2E0,0x7FFFFFFF,0x00000000, +0x7FD8878E,0xF9B82684,0x7F62368F,0xF3742CA2,0x7E9D55FC,0xED37EF91,0x7D8A5F40, +0xE70747C4,0x7C29FBEE,0xE0E60685,0x7A7D055B,0xDAD7F3A2,0x78848414,0xD4E0CB15, +0x7641AF3D,0xCF043AB3,0x73B5EBD1,0xC945DFEC,0x70E2CBC6,0xC3A94590,0x6DCA0D14, +0xBE31E19B,0x6A6D98A4,0xB8E31319,0x66CF8120,0xB3C0200C,0x62F201AC,0xAECC336C, +0x5ED77C8A,0xAA0A5B2E,0x5A82799A,0xA57D8666,0x55F5A4D2,0xA1288376,0x5133CC94, +0x9D0DFE54,0x4C3FDFF4,0x99307EE0,0x471CECE7,0x9592675C,0x41CE1E65,0x9235F2EC, +0x3C56BA70,0x8F1D343A,0x36BA2014,0x8C4A142F,0x30FBC54D,0x89BE50C3,0x2B1F34EB, +0x877B7BEC,0x25280C5E,0x8582FAA5,0x1F19F97B,0x83D60412,0x18F8B83C,0x8275A0C0, +0x12C8106F,0x8162AA04,0x0C8BD35E,0x809DC971,0x0647D97C,0x80277872,0x00000000, +0x80000000,0xF9B82684,0x80277872,0xF3742CA2,0x809DC971,0xED37EF91,0x8162AA04, +0xE70747C4,0x8275A0C0,0xE0E60685,0x83D60412,0xDAD7F3A2,0x8582FAA5,0xD4E0CB15, +0x877B7BEC,0xCF043AB3,0x89BE50C3,0xC945DFEC,0x8C4A142F,0xC3A94590,0x8F1D343A, +0xBE31E19B,0x9235F2EC,0xB8E31319,0x9592675C,0xB3C0200C,0x99307EE0,0xAECC336C, +0x9D0DFE54,0xAA0A5B2E,0xA1288376,0xA57D8666,0xA57D8666,0xA1288376,0xAA0A5B2E, +0x9D0DFE54,0xAECC336C,0x99307EE0,0xB3C0200C,0x9592675C,0xB8E31319,0x9235F2EC, +0xBE31E19B,0x8F1D343A,0xC3A94590,0x8C4A142F,0xC945DFEC,0x89BE50C3,0xCF043AB3, +0x877B7BEC,0xD4E0CB15,0x8582FAA5,0xDAD7F3A2,0x83D60412,0xE0E60685,0x8275A0C0, +0xE70747C4,0x8162AA04,0xED37EF91,0x809DC971,0xF3742CA2,0x80277872,0xF9B82684, +0x7FFFFFFF,0x00000000,0x7D8A5F40,0xE70747C4,0x7641AF3D,0xCF043AB3,0x6A6D98A4, +0xB8E31319,0x5A82799A,0xA57D8666,0x471CECE7,0x9592675C,0x30FBC54D,0x89BE50C3, +0x18F8B83C,0x8275A0C0,0x00000000,0x80000000,0xE70747C4,0x8275A0C0,0xCF043AB3, +0x89BE50C3,0xB8E31319,0x9592675C,0xA57D8666,0xA57D8666,0x9592675C,0xB8E31319, +0x89BE50C3,0xCF043AB3,0x8275A0C0,0xE70747C4,0x7FFFFFFF,0x00000000,0x5A82799A, +0xA57D8666,0x00000000,0x80000000,0xA57D8666,0xA57D8666,}; + +q31_t rearranged_twiddle_stride3_4096_q31[2728]={ +0x7FFFFFFF,0x00000000,0x7FFFA72C,0xFF69343F,0x7FFE9CB2,0xFED2694F,0x7FFCE093, +0xFE3BA002,0x7FFA72D1,0xFDA4D929,0x7FF75370,0xFD0E1594,0x7FF38274,0xFC775616, +0x7FEEFFE1,0xFBE09B80,0x7FE9CBC0,0xFB49E6A3,0x7FE3E616,0xFAB3384F,0x7FDD4EEC, +0xFA1C9157,0x7FD6064C,0xF985F28A,0x7FCE0C3E,0xF8EF5CBB,0x7FC560CF,0xF858D0BB, +0x7FBC040A,0xF7C24F59,0x7FB1F5FC,0xF72BD967,0x7FA736B4,0xF6956FB7,0x7F9BC640, +0xF5FF1318,0x7F8FA4B0,0xF568C45B,0x7F82D214,0xF4D28451,0x7F754E80,0xF43C53CB, +0x7F671A05,0xF3A63398,0x7F5834B7,0xF310248A,0x7F489EAA,0xF27A2771,0x7F3857F6, +0xF1E43D1C,0x7F2760AF,0xF14E665C,0x7F15B8EE,0xF0B8A401,0x7F0360CB,0xF022F6DA, +0x7EF05860,0xEF8D5FB8,0x7EDC9FC6,0xEEF7DF6A,0x7EC8371A,0xEE6276BF,0x7EB31E78, +0xEDCD2687,0x7E9D55FC,0xED37EF91,0x7E86DDC6,0xECA2D2AD,0x7E6FB5F4,0xEC0DD0A8, +0x7E57DEA7,0xEB78EA52,0x7E3F57FF,0xEAE4207A,0x7E26221F,0xEA4F73EE,0x7E0C3D29, +0xE9BAE57D,0x7DF1A942,0xE92675F4,0x7DD6668F,0xE8922622,0x7DBA7534,0xE7FDF6D4, +0x7D9DD55A,0xE769E8D8,0x7D808728,0xE6D5FCFC,0x7D628AC6,0xE642340D,0x7D43E05E, +0xE5AE8ED8,0x7D24881B,0xE51B0E2A,0x7D048228,0xE487B2D0,0x7CE3CEB2,0xE3F47D96, +0x7CC26DE5,0xE3616F48,0x7CA05FF1,0xE2CE88B3,0x7C7DA505,0xE23BCAA2,0x7C5A3D50, +0xE1A935E2,0x7C362904,0xE116CB3D,0x7C116853,0xE0848B7F,0x7BEBFB70,0xDFF27773, +0x7BC5E290,0xDF608FE4,0x7B9F1DE6,0xDECED59B,0x7B77ADA8,0xDE3D4964,0x7B4F920E, +0xDDABEC08,0x7B26CB4F,0xDD1ABE51,0x7AFD59A4,0xDC89C109,0x7AD33D45,0xDBF8F4F8, +0x7AA8766F,0xDB685AE9,0x7A7D055B,0xDAD7F3A2,0x7A50EA47,0xDA47BFEE,0x7A24256F, +0xD9B7C094,0x79F6B711,0xD927F65B,0x79C89F6E,0xD898620C,0x7999DEC4,0xD809046E, +0x796A7554,0xD779DE47,0x793A6361,0xD6EAF05F,0x7909A92D,0xD65C3B7B,0x78D846FB, +0xD5CDC062,0x78A63D11,0xD53F7FDA,0x78738BB3,0xD4B17AA8,0x78403329,0xD423B191, +0x780C33B8,0xD396255A,0x77D78DAA,0xD308D6C7,0x77A24148,0xD27BC69C,0x776C4EDB, +0xD1EEF59E,0x7735B6AF,0xD1626490,0x76FE790E,0xD0D61434,0x76C69647,0xD04A054E, +0x768E0EA6,0xCFBE389F,0x7654E279,0xCF32AEEB,0x761B1211,0xCEA768F2,0x75E09DBD, +0xCE1C6777,0x75A585CF,0xCD91AB39,0x7569CA99,0xCD0734F9,0x752D6C6C,0xCC7D0578, +0x74F06B9E,0xCBF31D75,0x74B2C884,0xCB697DB0,0x74748371,0xCAE026E8,0x74359CBD, +0xCA5719DB,0x73F614C0,0xC9CE5748,0x73B5EBD1,0xC945DFEC,0x73752249,0xC8BDB485, +0x7333B883,0xC835D5D0,0x72F1AED9,0xC7AE4489,0x72AF05A7,0xC727016D,0x726BBD48, +0xC6A00D37,0x7227D61C,0xC61968A2,0x71E35080,0xC593146A,0x719E2CD2,0xC50D1149, +0x71586B74,0xC4875FF9,0x71120CC5,0xC4020133,0x70CB1128,0xC37CF5B0,0x708378FF, +0xC2F83E2A,0x703B44AD,0xC273DB58,0x6FF27497,0xC1EFCDF3,0x6FA90921,0xC16C16B0, +0x6F5F02B2,0xC0E8B648,0x6F1461B0,0xC065AD70,0x6EC92683,0xBFE2FCDF,0x6E7D5193, +0xBF60A54A,0x6E30E34A,0xBEDEA765,0x6DE3DC11,0xBE5D03E6,0x6D963C54,0xBDDBBB7F, +0x6D48047E,0xBD5ACEE5,0x6CF934FC,0xBCDA3ECB,0x6CA9CE3B,0xBC5A0BE2,0x6C59D0A9, +0xBBDA36DD,0x6C093CB6,0xBB5AC06D,0x6BB812D1,0xBADBA943,0x6B66536B,0xBA5CF210, +0x6B13FEF5,0xB9DE9B83,0x6AC115E2,0xB960A64C,0x6A6D98A4,0xB8E31319,0x6A1987B0, +0xB865E299,0x69C4E37A,0xB7E9157A,0x696FAC78,0xB76CAC69,0x6919E320,0xB6F0A812, +0x68C387E9,0xB6750921,0x686C9B4B,0xB5F9D043,0x68151DBE,0xB57EFE22,0x67BD0FBD, +0xB5049368,0x676471C0,0xB48A90C0,0x670B4444,0xB410F6D3,0x66B187C3,0xB397C649, +0x66573CBB,0xB31EFFCC,0x65FC63A9,0xB2A6A402,0x65A0FD0B,0xB22EB392,0x6545095F, +0xB1B72F23,0x64E88926,0xB140175B,0x648B7CE0,0xB0C96CE0,0x642DE50D,0xB0533055, +0x63CFC231,0xAFDD625F,0x637114CC,0xAF6803A2,0x6311DD64,0xAEF314C0,0x62B21C7B, +0xAE7E965B,0x6251D298,0xAE0A8916,0x61F1003F,0xAD96ED92,0x618FA5F7,0xAD23C46E, +0x612DC447,0xACB10E4B,0x60CB5BB7,0xAC3ECBC7,0x60686CCF,0xABCCFD83,0x6004F819, +0xAB5BA41A,0x5FA0FE1F,0xAAEAC02C,0x5F3C7F6B,0xAA7A5253,0x5ED77C8A,0xAA0A5B2E, +0x5E71F606,0xA99ADB56,0x5E0BEC6E,0xA92BD367,0x5DA5604F,0xA8BD43FA,0x5D3E5237, +0xA84F2DAA,0x5CD6C2B5,0xA7E1910F,0x5C6EB258,0xA7746EC0,0x5C0621B2,0xA707C757, +0x5B9D1154,0xA69B9B68,0x5B3381CE,0xA62FEB8B,0x5AC973B5,0xA5C4B855,0x5A5EE79A, +0xA55A025B,0x59F3DE12,0xA4EFCA31,0x598857B2,0xA486106A,0x591C550E,0xA41CD599, +0x58AFD6BD,0xA3B41A50,0x5842DD54,0xA34BDF20,0x57D5696D,0xA2E4249B,0x57677B9D, +0xA27CEB4F,0x56F9147E,0xA21633CD,0x568A34A9,0xA1AFFEA3,0x561ADCB9,0xA14A4C5E, +0x55AB0D46,0xA0E51D8C,0x553AC6EE,0xA08072BA,0x54CA0A4B,0xA01C4C73,0x5458D7F9, +0x9FB8AB41,0x53E73097,0x9F558FB0,0x537514C2,0x9EF2FA49,0x53028518,0x9E90EB94, +0x528F8238,0x9E2F641B,0x521C0CC2,0x9DCE6463,0x51A82555,0x9D6DECF4,0x5133CC94, +0x9D0DFE54,0x50BF031F,0x9CAE9907,0x5049C999,0x9C4FBD93,0x4FD420A4,0x9BF16C7A, +0x4F5E08E3,0x9B93A641,0x4EE782FB,0x9B366B68,0x4E708F8F,0x9AD9BC71,0x4DF92F46, +0x9A7D99DE,0x4D8162C4,0x9A22042D,0x4D092AB0,0x99C6FBDE,0x4C9087B1,0x996C816F, +0x4C177A6E,0x9912955F,0x4B9E0390,0x98B93828,0x4B2423BE,0x98606A49,0x4AA9DBA2, +0x98082C3B,0x4A2F2BE6,0x97B07E7A,0x49B41533,0x9759617F,0x49389836,0x9702D5C3, +0x48BCB599,0x96ACDBBE,0x48406E08,0x965773E7,0x47C3C22F,0x96029EB6,0x4746B2BC, +0x95AE5C9F,0x46C9405C,0x955AAE17,0x464B6BBE,0x95079394,0x45CD358F,0x94B50D87, +0x454E9E80,0x94631C65,0x44CFA740,0x9411C09E,0x4450507E,0x93C0FAA3,0x43D09AED, +0x9370CAE4,0x4350873C,0x932131D1,0x42D0161E,0x92D22FD9,0x424F4845,0x9283C568, +0x41CE1E65,0x9235F2EC,0x414C992F,0x91E8B8D0,0x40CAB958,0x919C1781,0x40487F94, +0x91500F67,0x3FC5EC98,0x9104A0EE,0x3F430119,0x90B9CC7D,0x3EBFBDCD,0x906F927C, +0x3E3C2369,0x9025F352,0x3DB832A6,0x8FDCEF66,0x3D33EC39,0x8F94871D,0x3CAF50DA, +0x8F4CBADB,0x3C2A6142,0x8F058B04,0x3BA51E29,0x8EBEF7FB,0x3B1F8848,0x8E790222, +0x3A99A057,0x8E33A9DA,0x3A136712,0x8DEEEF82,0x398CDD32,0x8DAAD37B,0x39060373, +0x8D675623,0x387EDA8E,0x8D2477D8,0x37F76341,0x8CE238F6,0x376F9E46,0x8CA099DA, +0x36E78C5B,0x8C5F9ADE,0x365F2E3B,0x8C1F3C5D,0x35D684A6,0x8BDF7EB0,0x354D9057, +0x8BA0622F,0x34C4520D,0x8B61E733,0x343ACA87,0x8B240E11,0x33B0FA84,0x8AE6D720, +0x3326E2C3,0x8AAA42B4,0x329C8402,0x8A6E5123,0x3211DF04,0x8A3302BE,0x3186F487, +0x89F857D8,0x30FBC54D,0x89BE50C3,0x30705217,0x8984EDCF,0x2FE49BA7,0x894C2F4C, +0x2F58A2BE,0x89141589,0x2ECC681E,0x88DCA0D3,0x2E3FEC8B,0x88A5D177,0x2DB330C7, +0x886FA7C2,0x2D263596,0x883A23FF,0x2C98FBBA,0x88054677,0x2C0B83FA,0x87D10F75, +0x2B7DCF17,0x879D7F41,0x2AEFDDD8,0x876A9621,0x2A61B101,0x8738545E,0x29D34958, +0x8706BA3D,0x2944A7A2,0x86D5C802,0x28B5CCA5,0x86A57DF2,0x2826B928,0x8675DC4F, +0x27976DF1,0x8646E35C,0x2707EBC7,0x86189359,0x26783370,0x85EAEC88,0x25E845B6, +0x85BDEF28,0x2558235F,0x85919B76,0x24C7CD33,0x8565F1B0,0x243743FA,0x853AF214, +0x23A6887F,0x85109CDD,0x23159B88,0x84E6F244,0x22847DE0,0x84BDF286,0x21F3304F, +0x84959DD9,0x2161B3A0,0x846DF477,0x20D0089C,0x8446F695,0x203E300D,0x8420A46C, +0x1FAC2ABF,0x83FAFE2E,0x1F19F97B,0x83D60412,0x1E879D0D,0x83B1B649,0x1DF5163F, +0x838E1507,0x1D6265DD,0x836B207D,0x1CCF8CB3,0x8348D8DC,0x1C3C8B8C,0x83273E52, +0x1BA96335,0x83065110,0x1B161479,0x82E61141,0x1A82A026,0x82C67F14,0x19EF0707, +0x82A79AB3,0x195B49EA,0x8289644B,0x18C7699B,0x826BDC04,0x183366E9,0x824F0208, +0x179F429F,0x8232D67F,0x170AFD8D,0x82175990,0x1676987F,0x81FC8B60,0x15E21445, +0x81E26C16,0x154D71AA,0x81C8FBD6,0x14B8B17F,0x81B03AC2,0x1423D492,0x819828FD, +0x138EDBB1,0x8180C6A9,0x12F9C7AA,0x816A13E6,0x1264994E,0x815410D4,0x11CF516A, +0x813EBD90,0x1139F0CF,0x812A1A3A,0x10A4784B,0x811626EC,0x100EE8AD,0x8102E3C4, +0x0F7942C7,0x80F050DB,0x0EE38766,0x80DE6E4C,0x0E4DB75B,0x80CD3C2F,0x0DB7D376, +0x80BCBA9D,0x0D21DC87,0x80ACE9AB,0x0C8BD35E,0x809DC971,0x0BF5B8CB,0x808F5A02, +0x0B5F8D9F,0x80819B74,0x0AC952AA,0x80748DD9,0x0A3308BD,0x80683143,0x099CB0A7, +0x805C85C4,0x09064B3A,0x80518B6B,0x086FD947,0x80474248,0x07D95B9E,0x803DAA6A, +0x0742D311,0x8034C3DD,0x06AC406F,0x802C8EAD,0x0615A48B,0x80250AE7,0x057F0035, +0x801E3895,0x04E8543E,0x801817BF,0x0451A177,0x8012A86F,0x03BAE8B2,0x800DEAAD, +0x03242ABF,0x8009DE7E,0x028D6870,0x800683E8,0x01F6A297,0x8003DAF1,0x015FDA03, +0x8001E39B,0x00C90F88,0x80009DEA,0x003243F5,0x800009DF,0xFF9B781D,0x8000277A, +0xFF04ACD0,0x8000F6BD,0xFE6DE2E0,0x800277A6,0xFDD71B1E,0x8004AA32,0xFD40565C, +0x80078E5E,0xFCA9956A,0x800B2427,0xFC12D91A,0x800F6B88,0xFB7C223D,0x8014647B, +0xFAE571A4,0x801A0EF8,0xFA4EC821,0x80206AF8,0xF9B82684,0x80277872,0xF9218D9E, +0x802F375D,0xF88AFE42,0x8037A7AC,0xF7F4793E,0x8040C956,0xF75DFF66,0x804A9C4D, +0xF6C79188,0x80552084,0xF6313077,0x806055EB,0xF59ADD02,0x806C3C74,0xF50497FB, +0x8078D40D,0xF46E6231,0x80861CA6,0xF3D83C77,0x8094162C,0xF342279B,0x80A2C08B, +0xF2AC246E,0x80B21BAF,0xF21633C0,0x80C22784,0xF1805662,0x80D2E3F2,0xF0EA8D24, +0x80E450E2,0xF054D8D5,0x80F66E3C,0xEFBF3A45,0x81093BE8,0xEF29B243,0x811CB9CA, +0xEE9441A0,0x8130E7C9,0xEDFEE92B,0x8145C5C7,0xED69A9B3,0x815B53A8,0xECD48407, +0x8171914E,0xEC3F78F6,0x81887E9A,0xEBAA894F,0x81A01B6D,0xEB15B5E1,0x81B867A5, +0xEA80FF7A,0x81D16321,0xE9EC66E8,0x81EB0DBE,0xE957ECFB,0x82056758,0xE8C39280, +0x82206FCC,0xE82F5844,0x823C26F3,0xE79B3F16,0x82588CA7,0xE70747C4,0x8275A0C0, +0xE6737319,0x82936317,0xE5DFC1E5,0x82B1D381,0xE54C34F3,0x82D0F1D5,0xE4B8CD11, +0x82F0BDE8,0xE4258B0A,0x8311378D,0xE3926FAD,0x83325E97,0xE2FF7BC3,0x835432D8, +0xE26CB01B,0x8376B422,0xE1DA0D7E,0x8399E244,0xE14794BA,0x83BDBD0E,0xE0B54698, +0x83E2444D,0xE02323E5,0x840777D0,0xDF912D6B,0x842D5762,0xDEFF63F4,0x8453E2CF, +0xDE6DC84B,0x847B19E1,0xDDDC5B3B,0x84A2FC62,0xDD4B1D8C,0x84CB8A1B,0xDCBA1008, +0x84F4C2D4,0xDC293379,0x851EA652,0xDB9888A8,0x8549345C,0xDB08105E,0x85746CB8, +0xDA77CB63,0x85A04F28,0xD9E7BA7F,0x85CCDB70,0xD957DE7A,0x85FA1153,0xD8C8381D, +0x8627F091,0xD838C82D,0x865678EB,0xD7A98F73,0x8685AA20,0xD71A8EB5,0x86B583EE, +0xD68BC6BA,0x86E60614,0xD5FD3848,0x8717304E,0xD56EE424,0x87490258,0xD4E0CB15, +0x877B7BEC,0xD452EDDF,0x87AE9CC5,0xD3C54D47,0x87E2649B,0xD337EA12,0x8816D327, +0xD2AAC504,0x884BE821,0xD21DDEE2,0x8881A33D,0xD191386E,0x88B80432,0xD104D26B, +0x88EF0AB4,0xD078AD9E,0x8926B677,0xCFECCAC7,0x895F072E,0xCF612AAA,0x8997FC8A, +0xCED5CE08,0x89D1963C,0xCE4AB5A2,0x8A0BD3F5,0xCDBFE23A,0x8A46B564,0xCD355491, +0x8A823A36,0xCCAB0D65,0x8ABE6219,0xCC210D79,0x8AFB2CBB,0xCB97558A,0x8B3899C6, +0xCB0DE658,0x8B76A8E4,0xCA84C0A3,0x8BB559C1,0xC9FBE527,0x8BF4AC05,0xC97354A4, +0x8C349F58,0xC8EB0FD6,0x8C753362,0xC863177B,0x8CB667C8,0xC7DB6C50,0x8CF83C30, +0xC7540F11,0x8D3AB03F,0xC6CD0079,0x8D7DC399,0xC6464144,0x8DC175E0,0xC5BFD22E, +0x8E05C6B7,0xC539B3F1,0x8E4AB5BF,0xC4B3E746,0x8E904298,0xC42E6CE8,0x8ED66CE1, +0xC3A94590,0x8F1D343A,0xC32471F7,0x8F649840,0xC29FF2D4,0x8FAC988F,0xC21BC8E1, +0x8FF534C4,0xC197F4D4,0x903E6C7B,0xC1147764,0x90883F4D,0xC0915148,0x90D2ACD4, +0xC00E8336,0x911DB4A9,0xBF8C0DE3,0x91695663,0xBF09F205,0x91B5919A,0xBE88304F, +0x920265E4,0xBE06C977,0x924FD2D7,0xBD85BE30,0x929DD806,0xBD050F2C,0x92EC7505, +0xBC84BD1F,0x933BA968,0xBC04C8BA,0x938B74C1,0xBB8532B0,0x93DBD6A0,0xBB05FBB0, +0x942CCE96,0xBA87246D,0x947E5C33,0xBA08AD95,0x94D07F05,0xB98A97D8,0x9523369C, +0xB90CE3E6,0x95768283,0xB88F926D,0x95CA6247,0xB812A41A,0x961ED574,0xB796199B, +0x9673DB94,0xB719F39E,0x96C97432,0xB69E32CD,0x971F9ED7,0xB622D7D6,0x97765B0A, +0xB5A7E362,0x97CDA855,0xB52D561E,0x9825863D,0xB4B330B3,0x987DF449,0xB43973CA, +0x98D6F1FE,0xB3C0200C,0x99307EE0,0xB3473623,0x998A9A74,0xB2CEB6B5,0x99E5443B, +0xB256A26A,0x9A407BB9,0xB1DEF9E9,0x9A9C406E,0xB167BDD7,0x9AF891DB,0xB0F0EEDA, +0x9B556F81,0xB07A8D97,0x9BB2D8DE,0xB0049AB3,0x9C10CD70,0xAF8F16D1,0x9C6F4CB6, +0xAF1A0293,0x9CCE562C,0xAEA55E9E,0x9D2DE94D,0xAE312B92,0x9D8E0597,0xADBD6A10, +0x9DEEAA82,0xAD4A1ABA,0x9E4FD78A,0xACD73E30,0x9EB18C26,0xAC64D510,0x9F13C7D0, +0xABF2DFFB,0x9F7689FF,0xAB815F8D,0x9FD9D22A,0xAB105464,0xA03D9FC8,0xAA9FBF1E, +0xA0A1F24D,0xAA2FA056,0xA106C92F,0xA9BFF8A8,0xA16C23E1,0xA950C8B0,0xA1D201D7, +0xA8E21106,0xA2386284,0xA873D246,0xA29F4559,0xA8060D08,0xA306A9C8,0xA798C1E5, +0xA36E8F41,0xA72BF174,0xA3D6F534,0xA6BF9C4B,0xA43FDB10,0xA653C303,0xA4A94043, +0xA5E8662F,0xA513243B,0xA57D8666,0xA57D8666,0xA513243B,0xA5E8662F,0xA4A94043, +0xA653C303,0xA43FDB10,0xA6BF9C4B,0xA3D6F534,0xA72BF174,0xA36E8F41,0xA798C1E5, +0xA306A9C8,0xA8060D08,0xA29F4559,0xA873D246,0xA2386284,0xA8E21106,0xA1D201D7, +0xA950C8B0,0xA16C23E1,0xA9BFF8A8,0xA106C92F,0xAA2FA056,0xA0A1F24D,0xAA9FBF1E, +0xA03D9FC8,0xAB105464,0x9FD9D22A,0xAB815F8D,0x9F7689FF,0xABF2DFFB,0x9F13C7D0, +0xAC64D510,0x9EB18C26,0xACD73E30,0x9E4FD78A,0xAD4A1ABA,0x9DEEAA82,0xADBD6A10, +0x9D8E0597,0xAE312B92,0x9D2DE94D,0xAEA55E9E,0x9CCE562C,0xAF1A0293,0x9C6F4CB6, +0xAF8F16D1,0x9C10CD70,0xB0049AB3,0x9BB2D8DE,0xB07A8D97,0x9B556F81,0xB0F0EEDA, +0x9AF891DB,0xB167BDD7,0x9A9C406E,0xB1DEF9E9,0x9A407BB9,0xB256A26A,0x99E5443B, +0xB2CEB6B5,0x998A9A74,0xB3473623,0x99307EE0,0xB3C0200C,0x98D6F1FE,0xB43973CA, +0x987DF449,0xB4B330B3,0x9825863D,0xB52D561E,0x97CDA855,0xB5A7E362,0x97765B0A, +0xB622D7D6,0x971F9ED7,0xB69E32CD,0x96C97432,0xB719F39E,0x9673DB94,0xB796199B, +0x961ED574,0xB812A41A,0x95CA6247,0xB88F926D,0x95768283,0xB90CE3E6,0x9523369C, +0xB98A97D8,0x94D07F05,0xBA08AD95,0x947E5C33,0xBA87246D,0x942CCE96,0xBB05FBB0, +0x93DBD6A0,0xBB8532B0,0x938B74C1,0xBC04C8BA,0x933BA968,0xBC84BD1F,0x92EC7505, +0xBD050F2C,0x929DD806,0xBD85BE30,0x924FD2D7,0xBE06C977,0x920265E4,0xBE88304F, +0x91B5919A,0xBF09F205,0x91695663,0xBF8C0DE3,0x911DB4A9,0xC00E8336,0x90D2ACD4, +0xC0915148,0x90883F4D,0xC1147764,0x903E6C7B,0xC197F4D4,0x8FF534C4,0xC21BC8E1, +0x8FAC988F,0xC29FF2D4,0x8F649840,0xC32471F7,0x8F1D343A,0xC3A94590,0x8ED66CE1, +0xC42E6CE8,0x8E904298,0xC4B3E746,0x8E4AB5BF,0xC539B3F1,0x8E05C6B7,0xC5BFD22E, +0x8DC175E0,0xC6464144,0x8D7DC399,0xC6CD0079,0x8D3AB03F,0xC7540F11,0x8CF83C30, +0xC7DB6C50,0x8CB667C8,0xC863177B,0x8C753362,0xC8EB0FD6,0x8C349F58,0xC97354A4, +0x8BF4AC05,0xC9FBE527,0x8BB559C1,0xCA84C0A3,0x8B76A8E4,0xCB0DE658,0x8B3899C6, +0xCB97558A,0x8AFB2CBB,0xCC210D79,0x8ABE6219,0xCCAB0D65,0x8A823A36,0xCD355491, +0x8A46B564,0xCDBFE23A,0x8A0BD3F5,0xCE4AB5A2,0x89D1963C,0xCED5CE08,0x8997FC8A, +0xCF612AAA,0x895F072E,0xCFECCAC7,0x8926B677,0xD078AD9E,0x88EF0AB4,0xD104D26B, +0x88B80432,0xD191386E,0x8881A33D,0xD21DDEE2,0x884BE821,0xD2AAC504,0x8816D327, +0xD337EA12,0x87E2649B,0xD3C54D47,0x87AE9CC5,0xD452EDDF,0x877B7BEC,0xD4E0CB15, +0x87490258,0xD56EE424,0x8717304E,0xD5FD3848,0x86E60614,0xD68BC6BA,0x86B583EE, +0xD71A8EB5,0x8685AA20,0xD7A98F73,0x865678EB,0xD838C82D,0x8627F091,0xD8C8381D, +0x85FA1153,0xD957DE7A,0x85CCDB70,0xD9E7BA7F,0x85A04F28,0xDA77CB63,0x85746CB8, +0xDB08105E,0x8549345C,0xDB9888A8,0x851EA652,0xDC293379,0x84F4C2D4,0xDCBA1008, +0x84CB8A1B,0xDD4B1D8C,0x84A2FC62,0xDDDC5B3B,0x847B19E1,0xDE6DC84B,0x8453E2CF, +0xDEFF63F4,0x842D5762,0xDF912D6B,0x840777D0,0xE02323E5,0x83E2444D,0xE0B54698, +0x83BDBD0E,0xE14794BA,0x8399E244,0xE1DA0D7E,0x8376B422,0xE26CB01B,0x835432D8, +0xE2FF7BC3,0x83325E97,0xE3926FAD,0x8311378D,0xE4258B0A,0x82F0BDE8,0xE4B8CD11, +0x82D0F1D5,0xE54C34F3,0x82B1D381,0xE5DFC1E5,0x82936317,0xE6737319,0x8275A0C0, +0xE70747C4,0x82588CA7,0xE79B3F16,0x823C26F3,0xE82F5844,0x82206FCC,0xE8C39280, +0x82056758,0xE957ECFB,0x81EB0DBE,0xE9EC66E8,0x81D16321,0xEA80FF7A,0x81B867A5, +0xEB15B5E1,0x81A01B6D,0xEBAA894F,0x81887E9A,0xEC3F78F6,0x8171914E,0xECD48407, +0x815B53A8,0xED69A9B3,0x8145C5C7,0xEDFEE92B,0x8130E7C9,0xEE9441A0,0x811CB9CA, +0xEF29B243,0x81093BE8,0xEFBF3A45,0x80F66E3C,0xF054D8D5,0x80E450E2,0xF0EA8D24, +0x80D2E3F2,0xF1805662,0x80C22784,0xF21633C0,0x80B21BAF,0xF2AC246E,0x80A2C08B, +0xF342279B,0x8094162C,0xF3D83C77,0x80861CA6,0xF46E6231,0x8078D40D,0xF50497FB, +0x806C3C74,0xF59ADD02,0x806055EB,0xF6313077,0x80552084,0xF6C79188,0x804A9C4D, +0xF75DFF66,0x8040C956,0xF7F4793E,0x8037A7AC,0xF88AFE42,0x802F375D,0xF9218D9E, +0x80277872,0xF9B82684,0x80206AF8,0xFA4EC821,0x801A0EF8,0xFAE571A4,0x8014647B, +0xFB7C223D,0x800F6B88,0xFC12D91A,0x800B2427,0xFCA9956A,0x80078E5E,0xFD40565C, +0x8004AA32,0xFDD71B1E,0x800277A6,0xFE6DE2E0,0x8000F6BD,0xFF04ACD0,0x8000277A, +0xFF9B781D,0x800009DF,0x003243F5,0x80009DEA,0x00C90F88,0x8001E39B,0x015FDA03, +0x8003DAF1,0x01F6A297,0x800683E8,0x028D6870,0x8009DE7E,0x03242ABF,0x800DEAAD, +0x03BAE8B2,0x8012A86F,0x0451A177,0x801817BF,0x04E8543E,0x801E3895,0x057F0035, +0x80250AE7,0x0615A48B,0x802C8EAD,0x06AC406F,0x8034C3DD,0x0742D311,0x803DAA6A, +0x07D95B9E,0x80474248,0x086FD947,0x80518B6B,0x09064B3A,0x805C85C4,0x099CB0A7, +0x80683143,0x0A3308BD,0x80748DD9,0x0AC952AA,0x80819B74,0x0B5F8D9F,0x808F5A02, +0x0BF5B8CB,0x809DC971,0x0C8BD35E,0x80ACE9AB,0x0D21DC87,0x80BCBA9D,0x0DB7D376, +0x80CD3C2F,0x0E4DB75B,0x80DE6E4C,0x0EE38766,0x80F050DB,0x0F7942C7,0x8102E3C4, +0x100EE8AD,0x811626EC,0x10A4784B,0x812A1A3A,0x1139F0CF,0x813EBD90,0x11CF516A, +0x815410D4,0x1264994E,0x816A13E6,0x12F9C7AA,0x8180C6A9,0x138EDBB1,0x819828FD, +0x1423D492,0x81B03AC2,0x14B8B17F,0x81C8FBD6,0x154D71AA,0x81E26C16,0x15E21445, +0x81FC8B60,0x1676987F,0x82175990,0x170AFD8D,0x8232D67F,0x179F429F,0x824F0208, +0x183366E9,0x826BDC04,0x18C7699B,0x8289644B,0x195B49EA,0x82A79AB3,0x19EF0707, +0x82C67F14,0x1A82A026,0x82E61141,0x1B161479,0x83065110,0x1BA96335,0x83273E52, +0x1C3C8B8C,0x8348D8DC,0x1CCF8CB3,0x836B207D,0x1D6265DD,0x838E1507,0x1DF5163F, +0x83B1B649,0x1E879D0D,0x83D60412,0x1F19F97B,0x83FAFE2E,0x1FAC2ABF,0x8420A46C, +0x203E300D,0x8446F695,0x20D0089C,0x846DF477,0x2161B3A0,0x84959DD9,0x21F3304F, +0x84BDF286,0x22847DE0,0x84E6F244,0x23159B88,0x85109CDD,0x23A6887F,0x853AF214, +0x243743FA,0x8565F1B0,0x24C7CD33,0x85919B76,0x2558235F,0x85BDEF28,0x25E845B6, +0x85EAEC88,0x26783370,0x86189359,0x2707EBC7,0x8646E35C,0x27976DF1,0x8675DC4F, +0x2826B928,0x86A57DF2,0x28B5CCA5,0x86D5C802,0x2944A7A2,0x8706BA3D,0x29D34958, +0x8738545E,0x2A61B101,0x876A9621,0x2AEFDDD8,0x879D7F41,0x2B7DCF17,0x87D10F75, +0x2C0B83FA,0x88054677,0x2C98FBBA,0x883A23FF,0x2D263596,0x886FA7C2,0x2DB330C7, +0x88A5D177,0x2E3FEC8B,0x88DCA0D3,0x2ECC681E,0x89141589,0x2F58A2BE,0x894C2F4C, +0x2FE49BA7,0x8984EDCF,0x30705217,0x89BE50C3,0x30FBC54D,0x89F857D8,0x3186F487, +0x8A3302BE,0x3211DF04,0x8A6E5123,0x329C8402,0x8AAA42B4,0x3326E2C3,0x8AE6D720, +0x33B0FA84,0x8B240E11,0x343ACA87,0x8B61E733,0x34C4520D,0x8BA0622F,0x354D9057, +0x8BDF7EB0,0x35D684A6,0x8C1F3C5D,0x365F2E3B,0x8C5F9ADE,0x36E78C5B,0x8CA099DA, +0x376F9E46,0x8CE238F6,0x37F76341,0x8D2477D8,0x387EDA8E,0x8D675623,0x39060373, +0x8DAAD37B,0x398CDD32,0x8DEEEF82,0x3A136712,0x8E33A9DA,0x3A99A057,0x8E790222, +0x3B1F8848,0x8EBEF7FB,0x3BA51E29,0x8F058B04,0x3C2A6142,0x8F4CBADB,0x3CAF50DA, +0x8F94871D,0x3D33EC39,0x8FDCEF66,0x3DB832A6,0x9025F352,0x3E3C2369,0x906F927C, +0x3EBFBDCD,0x90B9CC7D,0x3F430119,0x9104A0EE,0x3FC5EC98,0x91500F67,0x40487F94, +0x919C1781,0x40CAB958,0x91E8B8D0,0x414C992F,0x9235F2EC,0x41CE1E65,0x9283C568, +0x424F4845,0x92D22FD9,0x42D0161E,0x932131D1,0x4350873C,0x9370CAE4,0x43D09AED, +0x93C0FAA3,0x4450507E,0x9411C09E,0x44CFA740,0x94631C65,0x454E9E80,0x94B50D87, +0x45CD358F,0x95079394,0x464B6BBE,0x955AAE17,0x46C9405C,0x95AE5C9F,0x4746B2BC, +0x96029EB6,0x47C3C22F,0x965773E7,0x48406E08,0x96ACDBBE,0x48BCB599,0x9702D5C3, +0x49389836,0x9759617F,0x49B41533,0x97B07E7A,0x4A2F2BE6,0x98082C3B,0x4AA9DBA2, +0x98606A49,0x4B2423BE,0x98B93828,0x4B9E0390,0x9912955F,0x4C177A6E,0x996C816F, +0x4C9087B1,0x99C6FBDE,0x4D092AB0,0x9A22042D,0x4D8162C4,0x9A7D99DE,0x4DF92F46, +0x9AD9BC71,0x4E708F8F,0x9B366B68,0x4EE782FB,0x9B93A641,0x4F5E08E3,0x9BF16C7A, +0x4FD420A4,0x9C4FBD93,0x5049C999,0x9CAE9907,0x50BF031F,0x9D0DFE54,0x5133CC94, +0x9D6DECF4,0x51A82555,0x9DCE6463,0x521C0CC2,0x9E2F641B,0x528F8238,0x9E90EB94, +0x53028518,0x9EF2FA49,0x537514C2,0x9F558FB0,0x53E73097,0x9FB8AB41,0x5458D7F9, +0xA01C4C73,0x54CA0A4B,0xA08072BA,0x553AC6EE,0xA0E51D8C,0x55AB0D46,0xA14A4C5E, +0x561ADCB9,0xA1AFFEA3,0x568A34A9,0xA21633CD,0x56F9147E,0xA27CEB4F,0x57677B9D, +0xA2E4249B,0x57D5696D,0xA34BDF20,0x5842DD54,0xA3B41A50,0x58AFD6BD,0xA41CD599, +0x591C550E,0xA486106A,0x598857B2,0xA4EFCA31,0x59F3DE12,0xA55A025B,0x5A5EE79A, +0xA5C4B855,0x5AC973B5,0xA62FEB8B,0x5B3381CE,0xA69B9B68,0x5B9D1154,0xA707C757, +0x5C0621B2,0xA7746EC0,0x5C6EB258,0xA7E1910F,0x5CD6C2B5,0xA84F2DAA,0x5D3E5237, +0xA8BD43FA,0x5DA5604F,0xA92BD367,0x5E0BEC6E,0xA99ADB56,0x5E71F606,0xAA0A5B2E, +0x5ED77C8A,0xAA7A5253,0x5F3C7F6B,0xAAEAC02C,0x5FA0FE1F,0xAB5BA41A,0x6004F819, +0xABCCFD83,0x60686CCF,0xAC3ECBC7,0x60CB5BB7,0xACB10E4B,0x612DC447,0xAD23C46E, +0x618FA5F7,0xAD96ED92,0x61F1003F,0xAE0A8916,0x6251D298,0xAE7E965B,0x62B21C7B, +0xAEF314C0,0x6311DD64,0xAF6803A2,0x637114CC,0xAFDD625F,0x63CFC231,0xB0533055, +0x642DE50D,0xB0C96CE0,0x648B7CE0,0xB140175B,0x64E88926,0xB1B72F23,0x6545095F, +0xB22EB392,0x65A0FD0B,0xB2A6A402,0x65FC63A9,0xB31EFFCC,0x66573CBB,0xB397C649, +0x66B187C3,0xB410F6D3,0x670B4444,0xB48A90C0,0x676471C0,0xB5049368,0x67BD0FBD, +0xB57EFE22,0x68151DBE,0xB5F9D043,0x686C9B4B,0xB6750921,0x68C387E9,0xB6F0A812, +0x6919E320,0xB76CAC69,0x696FAC78,0xB7E9157A,0x69C4E37A,0xB865E299,0x6A1987B0, +0xB8E31319,0x6A6D98A4,0xB960A64C,0x6AC115E2,0xB9DE9B83,0x6B13FEF5,0xBA5CF210, +0x6B66536B,0xBADBA943,0x6BB812D1,0xBB5AC06D,0x6C093CB6,0xBBDA36DD,0x6C59D0A9, +0xBC5A0BE2,0x6CA9CE3B,0xBCDA3ECB,0x6CF934FC,0xBD5ACEE5,0x6D48047E,0xBDDBBB7F, +0x6D963C54,0xBE5D03E6,0x6DE3DC11,0xBEDEA765,0x6E30E34A,0xBF60A54A,0x6E7D5193, +0xBFE2FCDF,0x6EC92683,0xC065AD70,0x6F1461B0,0xC0E8B648,0x6F5F02B2,0xC16C16B0, +0x6FA90921,0xC1EFCDF3,0x6FF27497,0xC273DB58,0x703B44AD,0xC2F83E2A,0x708378FF, +0xC37CF5B0,0x70CB1128,0xC4020133,0x71120CC5,0xC4875FF9,0x71586B74,0xC50D1149, +0x719E2CD2,0xC593146A,0x71E35080,0xC61968A2,0x7227D61C,0xC6A00D37,0x726BBD48, +0xC727016D,0x72AF05A7,0xC7AE4489,0x72F1AED9,0xC835D5D0,0x7333B883,0xC8BDB485, +0x73752249,0xC945DFEC,0x73B5EBD1,0xC9CE5748,0x73F614C0,0xCA5719DB,0x74359CBD, +0xCAE026E8,0x74748371,0xCB697DB0,0x74B2C884,0xCBF31D75,0x74F06B9E,0xCC7D0578, +0x752D6C6C,0xCD0734F9,0x7569CA99,0xCD91AB39,0x75A585CF,0xCE1C6777,0x75E09DBD, +0xCEA768F2,0x761B1211,0xCF32AEEB,0x7654E279,0xCFBE389F,0x768E0EA6,0xD04A054E, +0x76C69647,0xD0D61434,0x76FE790E,0xD1626490,0x7735B6AF,0xD1EEF59E,0x776C4EDB, +0xD27BC69C,0x77A24148,0xD308D6C7,0x77D78DAA,0xD396255A,0x780C33B8,0xD423B191, +0x78403329,0xD4B17AA8,0x78738BB3,0xD53F7FDA,0x78A63D11,0xD5CDC062,0x78D846FB, +0xD65C3B7B,0x7909A92D,0xD6EAF05F,0x793A6361,0xD779DE47,0x796A7554,0xD809046E, +0x7999DEC4,0xD898620C,0x79C89F6E,0xD927F65B,0x79F6B711,0xD9B7C094,0x7A24256F, +0xDA47BFEE,0x7A50EA47,0xDAD7F3A2,0x7A7D055B,0xDB685AE9,0x7AA8766F,0xDBF8F4F8, +0x7AD33D45,0xDC89C109,0x7AFD59A4,0xDD1ABE51,0x7B26CB4F,0xDDABEC08,0x7B4F920E, +0xDE3D4964,0x7B77ADA8,0xDECED59B,0x7B9F1DE6,0xDF608FE4,0x7BC5E290,0xDFF27773, +0x7BEBFB70,0xE0848B7F,0x7C116853,0xE116CB3D,0x7C362904,0xE1A935E2,0x7C5A3D50, +0xE23BCAA2,0x7C7DA505,0xE2CE88B3,0x7CA05FF1,0xE3616F48,0x7CC26DE5,0xE3F47D96, +0x7CE3CEB2,0xE487B2D0,0x7D048228,0xE51B0E2A,0x7D24881B,0xE5AE8ED8,0x7D43E05E, +0xE642340D,0x7D628AC6,0xE6D5FCFC,0x7D808728,0xE769E8D8,0x7D9DD55A,0xE7FDF6D4, +0x7DBA7534,0xE8922622,0x7DD6668F,0xE92675F4,0x7DF1A942,0xE9BAE57D,0x7E0C3D29, +0xEA4F73EE,0x7E26221F,0xEAE4207A,0x7E3F57FF,0xEB78EA52,0x7E57DEA7,0xEC0DD0A8, +0x7E6FB5F4,0xECA2D2AD,0x7E86DDC6,0xED37EF91,0x7E9D55FC,0xEDCD2687,0x7EB31E78, +0xEE6276BF,0x7EC8371A,0xEEF7DF6A,0x7EDC9FC6,0xEF8D5FB8,0x7EF05860,0xF022F6DA, +0x7F0360CB,0xF0B8A401,0x7F15B8EE,0xF14E665C,0x7F2760AF,0xF1E43D1C,0x7F3857F6, +0xF27A2771,0x7F489EAA,0xF310248A,0x7F5834B7,0xF3A63398,0x7F671A05,0xF43C53CB, +0x7F754E80,0xF4D28451,0x7F82D214,0xF568C45B,0x7F8FA4B0,0xF5FF1318,0x7F9BC640, +0xF6956FB7,0x7FA736B4,0xF72BD967,0x7FB1F5FC,0xF7C24F59,0x7FBC040A,0xF858D0BB, +0x7FC560CF,0xF8EF5CBB,0x7FCE0C3E,0xF985F28A,0x7FD6064C,0xFA1C9157,0x7FDD4EEC, +0xFAB3384F,0x7FE3E616,0xFB49E6A3,0x7FE9CBC0,0xFBE09B80,0x7FEEFFE1,0xFC775616, +0x7FF38274,0xFD0E1594,0x7FF75370,0xFDA4D929,0x7FFA72D1,0xFE3BA002,0x7FFCE093, +0xFED2694F,0x7FFE9CB2,0xFF69343F,0x7FFFA72C,0x7FFFFFFF,0x00000000,0x7FFA72D1, +0xFDA4D929,0x7FE9CBC0,0xFB49E6A3,0x7FCE0C3E,0xF8EF5CBB,0x7FA736B4,0xF6956FB7, +0x7F754E80,0xF43C53CB,0x7F3857F6,0xF1E43D1C,0x7EF05860,0xEF8D5FB8,0x7E9D55FC, +0xED37EF91,0x7E3F57FF,0xEAE4207A,0x7DD6668F,0xE8922622,0x7D628AC6,0xE642340D, +0x7CE3CEB2,0xE3F47D96,0x7C5A3D50,0xE1A935E2,0x7BC5E290,0xDF608FE4,0x7B26CB4F, +0xDD1ABE51,0x7A7D055B,0xDAD7F3A2,0x79C89F6E,0xD898620C,0x7909A92D,0xD65C3B7B, +0x78403329,0xD423B191,0x776C4EDB,0xD1EEF59E,0x768E0EA6,0xCFBE389F,0x75A585CF, +0xCD91AB39,0x74B2C884,0xCB697DB0,0x73B5EBD1,0xC945DFEC,0x72AF05A7,0xC727016D, +0x719E2CD2,0xC50D1149,0x708378FF,0xC2F83E2A,0x6F5F02B2,0xC0E8B648,0x6E30E34A, +0xBEDEA765,0x6CF934FC,0xBCDA3ECB,0x6BB812D1,0xBADBA943,0x6A6D98A4,0xB8E31319, +0x6919E320,0xB6F0A812,0x67BD0FBD,0xB5049368,0x66573CBB,0xB31EFFCC,0x64E88926, +0xB140175B,0x637114CC,0xAF6803A2,0x61F1003F,0xAD96ED92,0x60686CCF,0xABCCFD83, +0x5ED77C8A,0xAA0A5B2E,0x5D3E5237,0xA84F2DAA,0x5B9D1154,0xA69B9B68,0x59F3DE12, +0xA4EFCA31,0x5842DD54,0xA34BDF20,0x568A34A9,0xA1AFFEA3,0x54CA0A4B,0xA01C4C73, +0x53028518,0x9E90EB94,0x5133CC94,0x9D0DFE54,0x4F5E08E3,0x9B93A641,0x4D8162C4, +0x9A22042D,0x4B9E0390,0x98B93828,0x49B41533,0x9759617F,0x47C3C22F,0x96029EB6, +0x45CD358F,0x94B50D87,0x43D09AED,0x9370CAE4,0x41CE1E65,0x9235F2EC,0x3FC5EC98, +0x9104A0EE,0x3DB832A6,0x8FDCEF66,0x3BA51E29,0x8EBEF7FB,0x398CDD32,0x8DAAD37B, +0x376F9E46,0x8CA099DA,0x354D9057,0x8BA0622F,0x3326E2C3,0x8AAA42B4,0x30FBC54D, +0x89BE50C3,0x2ECC681E,0x88DCA0D3,0x2C98FBBA,0x88054677,0x2A61B101,0x8738545E, +0x2826B928,0x8675DC4F,0x25E845B6,0x85BDEF28,0x23A6887F,0x85109CDD,0x2161B3A0, +0x846DF477,0x1F19F97B,0x83D60412,0x1CCF8CB3,0x8348D8DC,0x1A82A026,0x82C67F14, +0x183366E9,0x824F0208,0x15E21445,0x81E26C16,0x138EDBB1,0x8180C6A9,0x1139F0CF, +0x812A1A3A,0x0EE38766,0x80DE6E4C,0x0C8BD35E,0x809DC971,0x0A3308BD,0x80683143, +0x07D95B9E,0x803DAA6A,0x057F0035,0x801E3895,0x03242ABF,0x8009DE7E,0x00C90F88, +0x80009DEA,0xFE6DE2E0,0x800277A6,0xFC12D91A,0x800F6B88,0xF9B82684,0x80277872, +0xF75DFF66,0x804A9C4D,0xF50497FB,0x8078D40D,0xF2AC246E,0x80B21BAF,0xF054D8D5, +0x80F66E3C,0xEDFEE92B,0x8145C5C7,0xEBAA894F,0x81A01B6D,0xE957ECFB,0x82056758, +0xE70747C4,0x8275A0C0,0xE4B8CD11,0x82F0BDE8,0xE26CB01B,0x8376B422,0xE02323E5, +0x840777D0,0xDDDC5B3B,0x84A2FC62,0xDB9888A8,0x8549345C,0xD957DE7A,0x85FA1153, +0xD71A8EB5,0x86B583EE,0xD4E0CB15,0x877B7BEC,0xD2AAC504,0x884BE821,0xD078AD9E, +0x8926B677,0xCE4AB5A2,0x8A0BD3F5,0xCC210D79,0x8AFB2CBB,0xC9FBE527,0x8BF4AC05, +0xC7DB6C50,0x8CF83C30,0xC5BFD22E,0x8E05C6B7,0xC3A94590,0x8F1D343A,0xC197F4D4, +0x903E6C7B,0xBF8C0DE3,0x91695663,0xBD85BE30,0x929DD806,0xBB8532B0,0x93DBD6A0, +0xB98A97D8,0x9523369C,0xB796199B,0x9673DB94,0xB5A7E362,0x97CDA855,0xB3C0200C, +0x99307EE0,0xB1DEF9E9,0x9A9C406E,0xB0049AB3,0x9C10CD70,0xAE312B92,0x9D8E0597, +0xAC64D510,0x9F13C7D0,0xAA9FBF1E,0xA0A1F24D,0xA8E21106,0xA2386284,0xA72BF174, +0xA3D6F534,0xA57D8666,0xA57D8666,0xA3D6F534,0xA72BF174,0xA2386284,0xA8E21106, +0xA0A1F24D,0xAA9FBF1E,0x9F13C7D0,0xAC64D510,0x9D8E0597,0xAE312B92,0x9C10CD70, +0xB0049AB3,0x9A9C406E,0xB1DEF9E9,0x99307EE0,0xB3C0200C,0x97CDA855,0xB5A7E362, +0x9673DB94,0xB796199B,0x9523369C,0xB98A97D8,0x93DBD6A0,0xBB8532B0,0x929DD806, +0xBD85BE30,0x91695663,0xBF8C0DE3,0x903E6C7B,0xC197F4D4,0x8F1D343A,0xC3A94590, +0x8E05C6B7,0xC5BFD22E,0x8CF83C30,0xC7DB6C50,0x8BF4AC05,0xC9FBE527,0x8AFB2CBB, +0xCC210D79,0x8A0BD3F5,0xCE4AB5A2,0x8926B677,0xD078AD9E,0x884BE821,0xD2AAC504, +0x877B7BEC,0xD4E0CB15,0x86B583EE,0xD71A8EB5,0x85FA1153,0xD957DE7A,0x8549345C, +0xDB9888A8,0x84A2FC62,0xDDDC5B3B,0x840777D0,0xE02323E5,0x8376B422,0xE26CB01B, +0x82F0BDE8,0xE4B8CD11,0x8275A0C0,0xE70747C4,0x82056758,0xE957ECFB,0x81A01B6D, +0xEBAA894F,0x8145C5C7,0xEDFEE92B,0x80F66E3C,0xF054D8D5,0x80B21BAF,0xF2AC246E, +0x8078D40D,0xF50497FB,0x804A9C4D,0xF75DFF66,0x80277872,0xF9B82684,0x800F6B88, +0xFC12D91A,0x800277A6,0xFE6DE2E0,0x80009DEA,0x00C90F88,0x8009DE7E,0x03242ABF, +0x801E3895,0x057F0035,0x803DAA6A,0x07D95B9E,0x80683143,0x0A3308BD,0x809DC971, +0x0C8BD35E,0x80DE6E4C,0x0EE38766,0x812A1A3A,0x1139F0CF,0x8180C6A9,0x138EDBB1, +0x81E26C16,0x15E21445,0x824F0208,0x183366E9,0x82C67F14,0x1A82A026,0x8348D8DC, +0x1CCF8CB3,0x83D60412,0x1F19F97B,0x846DF477,0x2161B3A0,0x85109CDD,0x23A6887F, +0x85BDEF28,0x25E845B6,0x8675DC4F,0x2826B928,0x8738545E,0x2A61B101,0x88054677, +0x2C98FBBA,0x88DCA0D3,0x2ECC681E,0x89BE50C3,0x30FBC54D,0x8AAA42B4,0x3326E2C3, +0x8BA0622F,0x354D9057,0x8CA099DA,0x376F9E46,0x8DAAD37B,0x398CDD32,0x8EBEF7FB, +0x3BA51E29,0x8FDCEF66,0x3DB832A6,0x9104A0EE,0x3FC5EC98,0x9235F2EC,0x41CE1E65, +0x9370CAE4,0x43D09AED,0x94B50D87,0x45CD358F,0x96029EB6,0x47C3C22F,0x9759617F, +0x49B41533,0x98B93828,0x4B9E0390,0x9A22042D,0x4D8162C4,0x9B93A641,0x4F5E08E3, +0x9D0DFE54,0x5133CC94,0x9E90EB94,0x53028518,0xA01C4C73,0x54CA0A4B,0xA1AFFEA3, +0x568A34A9,0xA34BDF20,0x5842DD54,0xA4EFCA31,0x59F3DE12,0xA69B9B68,0x5B9D1154, +0xA84F2DAA,0x5D3E5237,0xAA0A5B2E,0x5ED77C8A,0xABCCFD83,0x60686CCF,0xAD96ED92, +0x61F1003F,0xAF6803A2,0x637114CC,0xB140175B,0x64E88926,0xB31EFFCC,0x66573CBB, +0xB5049368,0x67BD0FBD,0xB6F0A812,0x6919E320,0xB8E31319,0x6A6D98A4,0xBADBA943, +0x6BB812D1,0xBCDA3ECB,0x6CF934FC,0xBEDEA765,0x6E30E34A,0xC0E8B648,0x6F5F02B2, +0xC2F83E2A,0x708378FF,0xC50D1149,0x719E2CD2,0xC727016D,0x72AF05A7,0xC945DFEC, +0x73B5EBD1,0xCB697DB0,0x74B2C884,0xCD91AB39,0x75A585CF,0xCFBE389F,0x768E0EA6, +0xD1EEF59E,0x776C4EDB,0xD423B191,0x78403329,0xD65C3B7B,0x7909A92D,0xD898620C, +0x79C89F6E,0xDAD7F3A2,0x7A7D055B,0xDD1ABE51,0x7B26CB4F,0xDF608FE4,0x7BC5E290, +0xE1A935E2,0x7C5A3D50,0xE3F47D96,0x7CE3CEB2,0xE642340D,0x7D628AC6,0xE8922622, +0x7DD6668F,0xEAE4207A,0x7E3F57FF,0xED37EF91,0x7E9D55FC,0xEF8D5FB8,0x7EF05860, +0xF1E43D1C,0x7F3857F6,0xF43C53CB,0x7F754E80,0xF6956FB7,0x7FA736B4,0xF8EF5CBB, +0x7FCE0C3E,0xFB49E6A3,0x7FE9CBC0,0xFDA4D929,0x7FFA72D1,0x7FFFFFFF,0x00000000, +0x7FA736B4,0xF6956FB7,0x7E9D55FC,0xED37EF91,0x7CE3CEB2,0xE3F47D96,0x7A7D055B, +0xDAD7F3A2,0x776C4EDB,0xD1EEF59E,0x73B5EBD1,0xC945DFEC,0x6F5F02B2,0xC0E8B648, +0x6A6D98A4,0xB8E31319,0x64E88926,0xB140175B,0x5ED77C8A,0xAA0A5B2E,0x5842DD54, +0xA34BDF20,0x5133CC94,0x9D0DFE54,0x49B41533,0x9759617F,0x41CE1E65,0x9235F2EC, +0x398CDD32,0x8DAAD37B,0x30FBC54D,0x89BE50C3,0x2826B928,0x8675DC4F,0x1F19F97B, +0x83D60412,0x15E21445,0x81E26C16,0x0C8BD35E,0x809DC971,0x03242ABF,0x8009DE7E, +0xF9B82684,0x80277872,0xF054D8D5,0x80F66E3C,0xE70747C4,0x8275A0C0,0xDDDC5B3B, +0x84A2FC62,0xD4E0CB15,0x877B7BEC,0xCC210D79,0x8AFB2CBB,0xC3A94590,0x8F1D343A, +0xBB8532B0,0x93DBD6A0,0xB3C0200C,0x99307EE0,0xAC64D510,0x9F13C7D0,0xA57D8666, +0xA57D8666,0x9F13C7D0,0xAC64D510,0x99307EE0,0xB3C0200C,0x93DBD6A0,0xBB8532B0, +0x8F1D343A,0xC3A94590,0x8AFB2CBB,0xCC210D79,0x877B7BEC,0xD4E0CB15,0x84A2FC62, +0xDDDC5B3B,0x8275A0C0,0xE70747C4,0x80F66E3C,0xF054D8D5,0x80277872,0xF9B82684, +0x8009DE7E,0x03242ABF,0x809DC971,0x0C8BD35E,0x81E26C16,0x15E21445,0x83D60412, +0x1F19F97B,0x8675DC4F,0x2826B928,0x89BE50C3,0x30FBC54D,0x8DAAD37B,0x398CDD32, +0x9235F2EC,0x41CE1E65,0x9759617F,0x49B41533,0x9D0DFE54,0x5133CC94,0xA34BDF20, +0x5842DD54,0xAA0A5B2E,0x5ED77C8A,0xB140175B,0x64E88926,0xB8E31319,0x6A6D98A4, +0xC0E8B648,0x6F5F02B2,0xC945DFEC,0x73B5EBD1,0xD1EEF59E,0x776C4EDB,0xDAD7F3A2, +0x7A7D055B,0xE3F47D96,0x7CE3CEB2,0xED37EF91,0x7E9D55FC,0xF6956FB7,0x7FA736B4, +0x7FFFFFFF,0x00000000,0x7A7D055B,0xDAD7F3A2,0x6A6D98A4,0xB8E31319,0x5133CC94, +0x9D0DFE54,0x30FBC54D,0x89BE50C3,0x0C8BD35E,0x809DC971,0xE70747C4,0x8275A0C0, +0xC3A94590,0x8F1D343A,0xA57D8666,0xA57D8666,0x8F1D343A,0xC3A94590,0x8275A0C0, +0xE70747C4,0x809DC971,0x0C8BD35E,0x89BE50C3,0x30FBC54D,0x9D0DFE54,0x5133CC94, +0xB8E31319,0x6A6D98A4,0xDAD7F3A2,0x7A7D055B,0x7FFFFFFF,0x00000000,0x30FBC54D, +0x89BE50C3,0xA57D8666,0xA57D8666,0x89BE50C3,0x30FBC54D,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]={ +0,0,}; + +q15_t rearranged_twiddle_stride1_16_q15[8]={ +0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_16_q15[8]={ +0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_16_q15[8]={ +0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]={ +0,32,0,}; + +q15_t rearranged_twiddle_stride1_64_q15[40]={ +0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3, +0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592, +0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF, +0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_64_q15[40]={ +0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D, +0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE, +0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF, +0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_64_q15[40]={ +0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C, +0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707, +0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF, +0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]={ +0,128,160,0,}; + +q15_t rearranged_twiddle_stride1_256_q15[168]={ +0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9,0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A, +0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E,0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6, +0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A,0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642, +0xCF04,0x7505,0xCC21,0x73B6,0xC946,0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9, +0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E,0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9, +0xB140,0x62F2,0xAECC,0x60EC,0xAC65,0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E, +0x5843,0xA34C,0x55F6,0xA129,0x539B,0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40, +0x9930,0x49B4,0x9759,0x471D,0x9592,0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1, +0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA,0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11, +0x8894,0x2B1F,0x877B,0x2827,0x8676,0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6, +0x1C0C,0x831C,0x18F9,0x8276,0x15E2,0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C, +0x809E,0x096B,0x8059,0x0648,0x8027,0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374, +0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642,0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2, +0xAECC,0x5A82,0xA57E,0x5134,0x9D0E,0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE, +0x2528,0x8583,0x18F9,0x8276,0x0C8C,0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82, +0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_256_q15[168]={ +0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62,0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A, +0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1,0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9, +0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0,0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82, +0xA57E,0x55F6,0xA129,0x5134,0x9D0E,0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236, +0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC,0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A, +0x83D6,0x18F9,0x8276,0x12C8,0x8163,0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000, +0xF9B8,0x8027,0xF374,0x809E,0xED38,0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8, +0x8583,0xD4E1,0x877B,0xCF04,0x89BE,0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236, +0xB8E3,0x9592,0xB3C0,0x9930,0xAECC,0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129, +0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0,0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9, +0x8C4A,0xC946,0x89BE,0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276, +0xE707,0x8163,0xED38,0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707, +0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9, +0x8276,0x0000,0x8000,0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E, +0x9592,0xB8E3,0x89BE,0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000, +0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_256_q15[168]={ +0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C, +0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A, +0x5843,0xA34C,0x5134,0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC, +0x89BE,0x2827,0x8676,0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A, +0xF9B8,0x8027,0xF055,0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21, +0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E, +0x9F14,0xAC65,0x9930,0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B, +0xD4E1,0x84A3,0xDDDC,0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324, +0x809E,0x0C8C,0x81E2,0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB, +0x398D,0x9236,0x41CE,0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7, +0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8, +0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8, +0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9, +0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC, +0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E, +0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]={ +0,512,640,672,0,}; + +q15_t rearranged_twiddle_stride1_1024_q15[680]={ +0x7FFF,0x0000,0x7FFF,0xFF37,0x7FFE,0xFE6E,0x7FFA,0xFDA5,0x7FF6,0xFCDC,0x7FF1, +0xFC13,0x7FEA,0xFB4A,0x7FE2,0xFA81,0x7FD9,0xF9B8,0x7FCE,0xF8EF,0x7FC2,0xF827, +0x7FB5,0xF75E,0x7FA7,0xF695,0x7F98,0xF5CD,0x7F87,0xF505,0x7F75,0xF43C,0x7F62, +0xF374,0x7F4E,0xF2AC,0x7F38,0xF1E4,0x7F22,0xF11C,0x7F0A,0xF055,0x7EF0,0xEF8D, +0x7ED6,0xEEC6,0x7EBA,0xEDFF,0x7E9D,0xED38,0x7E7F,0xEC71,0x7E60,0xEBAB,0x7E3F, +0xEAE4,0x7E1E,0xEA1E,0x7DFB,0xE958,0x7DD6,0xE892,0x7DB1,0xE7CD,0x7D8A,0xE707, +0x7D63,0xE642,0x7D3A,0xE57D,0x7D0F,0xE4B9,0x7CE4,0xE3F4,0x7CB7,0xE330,0x7C89, +0xE26D,0x7C5A,0xE1A9,0x7C2A,0xE0E6,0x7BF9,0xE023,0x7BC6,0xDF61,0x7B92,0xDE9E, +0x7B5D,0xDDDC,0x7B27,0xDD1B,0x7AEF,0xDC59,0x7AB7,0xDB99,0x7A7D,0xDAD8,0x7A42, +0xDA18,0x7A06,0xD958,0x79C9,0xD898,0x798A,0xD7D9,0x794A,0xD71B,0x790A,0xD65C, +0x78C8,0xD59E,0x7885,0xD4E1,0x7840,0xD424,0x77FB,0xD367,0x77B4,0xD2AB,0x776C, +0xD1EF,0x7723,0xD134,0x76D9,0xD079,0x768E,0xCFBE,0x7642,0xCF04,0x75F4,0xCE4B, +0x75A6,0xCD92,0x7556,0xCCD9,0x7505,0xCC21,0x74B3,0xCB69,0x7460,0xCAB2,0x740B, +0xC9FC,0x73B6,0xC946,0x735F,0xC890,0x7308,0xC7DB,0x72AF,0xC727,0x7255,0xC673, +0x71FA,0xC5C0,0x719E,0xC50D,0x7141,0xC45B,0x70E3,0xC3A9,0x7083,0xC2F8,0x7023, +0xC248,0x6FC2,0xC198,0x6F5F,0xC0E9,0x6EFB,0xC03A,0x6E97,0xBF8C,0x6E31,0xBEDF, +0x6DCA,0xBE32,0x6D62,0xBD86,0x6CF9,0xBCDA,0x6C8F,0xBC2F,0x6C24,0xBB85,0x6BB8, +0xBADC,0x6B4B,0xBA33,0x6ADD,0xB98B,0x6A6E,0xB8E3,0x69FD,0xB83C,0x698C,0xB796, +0x691A,0xB6F1,0x68A7,0xB64C,0x6832,0xB5A8,0x67BD,0xB505,0x6747,0xB462,0x66D0, +0xB3C0,0x6657,0xB31F,0x65DE,0xB27F,0x6564,0xB1DF,0x64E9,0xB140,0x646C,0xB0A2, +0x63EF,0xB005,0x6371,0xAF68,0x62F2,0xAECC,0x6272,0xAE31,0x61F1,0xAD97,0x616F, +0xACFD,0x60EC,0xAC65,0x6068,0xABCD,0x5FE4,0xAB36,0x5F5E,0xAAA0,0x5ED7,0xAA0A, +0x5E50,0xA976,0x5DC8,0xA8E2,0x5D3E,0xA84F,0x5CB4,0xA7BD,0x5C29,0xA72C,0x5B9D, +0xA69C,0x5B10,0xA60C,0x5A82,0xA57E,0x59F4,0xA4F0,0x5964,0xA463,0x58D4,0xA3D7, +0x5843,0xA34C,0x57B1,0xA2C2,0x571E,0xA238,0x568A,0xA1B0,0x55F6,0xA129,0x5560, +0xA0A2,0x54CA,0xA01C,0x5433,0x9F98,0x539B,0x9F14,0x5303,0x9E91,0x5269,0x9E0F, +0x51CF,0x9D8E,0x5134,0x9D0E,0x5098,0x9C8F,0x4FFB,0x9C11,0x4F5E,0x9B94,0x4EC0, +0x9B17,0x4E21,0x9A9C,0x4D81,0x9A22,0x4CE1,0x99A9,0x4C40,0x9930,0x4B9E,0x98B9, +0x4AFB,0x9843,0x4A58,0x97CE,0x49B4,0x9759,0x490F,0x96E6,0x486A,0x9674,0x47C4, +0x9603,0x471D,0x9592,0x4675,0x9523,0x45CD,0x94B5,0x4524,0x9448,0x447B,0x93DC, +0x43D1,0x9371,0x4326,0x9307,0x427A,0x929E,0x41CE,0x9236,0x4121,0x91CF,0x4074, +0x9169,0x3FC6,0x9105,0x3F17,0x90A1,0x3E68,0x903E,0x3DB8,0x8FDD,0x3D08,0x8F7D, +0x3C57,0x8F1D,0x3BA5,0x8EBF,0x3AF3,0x8E62,0x3A40,0x8E06,0x398D,0x8DAB,0x38D9, +0x8D51,0x3825,0x8CF8,0x3770,0x8CA1,0x36BA,0x8C4A,0x3604,0x8BF5,0x354E,0x8BA0, +0x3497,0x8B4D,0x33DF,0x8AFB,0x3327,0x8AAA,0x326E,0x8A5A,0x31B5,0x8A0C,0x30FC, +0x89BE,0x3042,0x8972,0x2F87,0x8927,0x2ECC,0x88DD,0x2E11,0x8894,0x2D55,0x884C, +0x2C99,0x8805,0x2BDC,0x87C0,0x2B1F,0x877B,0x2A62,0x8738,0x29A4,0x86F6,0x28E5, +0x86B6,0x2827,0x8676,0x2768,0x8637,0x26A8,0x85FA,0x25E8,0x85BE,0x2528,0x8583, +0x2467,0x8549,0x23A7,0x8511,0x22E5,0x84D9,0x2224,0x84A3,0x2162,0x846E,0x209F, +0x843A,0x1FDD,0x8407,0x1F1A,0x83D6,0x1E57,0x83A6,0x1D93,0x8377,0x1CD0,0x8349, +0x1C0C,0x831C,0x1B47,0x82F1,0x1A83,0x82C6,0x19BE,0x829D,0x18F9,0x8276,0x1833, +0x824F,0x176E,0x822A,0x16A8,0x8205,0x15E2,0x81E2,0x151C,0x81C1,0x1455,0x81A0, +0x138F,0x8181,0x12C8,0x8163,0x1201,0x8146,0x113A,0x812A,0x1073,0x8110,0x0FAB, +0x80F6,0x0EE4,0x80DE,0x0E1C,0x80C8,0x0D54,0x80B2,0x0C8C,0x809E,0x0BC4,0x808B, +0x0AFB,0x8079,0x0A33,0x8068,0x096B,0x8059,0x08A2,0x804B,0x07D9,0x803E,0x0711, +0x8032,0x0648,0x8027,0x057F,0x801E,0x04B6,0x8016,0x03ED,0x800F,0x0324,0x800A, +0x025B,0x8006,0x0192,0x8002,0x00C9,0x8001,0x7FFF,0x0000,0x7FF6,0xFCDC,0x7FD9, +0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A,0xF055,0x7E9D,0xED38,0x7E1E,0xEA1E, +0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6,0x7B5D,0xDDDC,0x7A7D,0xDAD8,0x798A, +0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642,0xCF04,0x7505,0xCC21,0x73B6,0xC946, +0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9,0x6DCA,0xBE32,0x6C24,0xBB85,0x6A6E, +0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9,0xB140,0x62F2,0xAECC,0x60EC,0xAC65, +0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E,0x5843,0xA34C,0x55F6,0xA129,0x539B, +0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40,0x9930,0x49B4,0x9759,0x471D,0x9592, +0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1,0x3C57,0x8F1D,0x398D,0x8DAB,0x36BA, +0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11,0x8894,0x2B1F,0x877B,0x2827,0x8676, +0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6,0x1C0C,0x831C,0x18F9,0x8276,0x15E2, +0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C,0x809E,0x096B,0x8059,0x0648,0x8027, +0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D,0xDAD8,0x7642, +0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E,0x5134,0x9D0E, +0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9,0x8276,0x0C8C, +0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_1024_q15[680]={ +0x7FFF,0x0000,0x7FFE,0xFE6E,0x7FF6,0xFCDC,0x7FEA,0xFB4A,0x7FD9,0xF9B8,0x7FC2, +0xF827,0x7FA7,0xF695,0x7F87,0xF505,0x7F62,0xF374,0x7F38,0xF1E4,0x7F0A,0xF055, +0x7ED6,0xEEC6,0x7E9D,0xED38,0x7E60,0xEBAB,0x7E1E,0xEA1E,0x7DD6,0xE892,0x7D8A, +0xE707,0x7D3A,0xE57D,0x7CE4,0xE3F4,0x7C89,0xE26D,0x7C2A,0xE0E6,0x7BC6,0xDF61, +0x7B5D,0xDDDC,0x7AEF,0xDC59,0x7A7D,0xDAD8,0x7A06,0xD958,0x798A,0xD7D9,0x790A, +0xD65C,0x7885,0xD4E1,0x77FB,0xD367,0x776C,0xD1EF,0x76D9,0xD079,0x7642,0xCF04, +0x75A6,0xCD92,0x7505,0xCC21,0x7460,0xCAB2,0x73B6,0xC946,0x7308,0xC7DB,0x7255, +0xC673,0x719E,0xC50D,0x70E3,0xC3A9,0x7023,0xC248,0x6F5F,0xC0E9,0x6E97,0xBF8C, +0x6DCA,0xBE32,0x6CF9,0xBCDA,0x6C24,0xBB85,0x6B4B,0xBA33,0x6A6E,0xB8E3,0x698C, +0xB796,0x68A7,0xB64C,0x67BD,0xB505,0x66D0,0xB3C0,0x65DE,0xB27F,0x64E9,0xB140, +0x63EF,0xB005,0x62F2,0xAECC,0x61F1,0xAD97,0x60EC,0xAC65,0x5FE4,0xAB36,0x5ED7, +0xAA0A,0x5DC8,0xA8E2,0x5CB4,0xA7BD,0x5B9D,0xA69C,0x5A82,0xA57E,0x5964,0xA463, +0x5843,0xA34C,0x571E,0xA238,0x55F6,0xA129,0x54CA,0xA01C,0x539B,0x9F14,0x5269, +0x9E0F,0x5134,0x9D0E,0x4FFB,0x9C11,0x4EC0,0x9B17,0x4D81,0x9A22,0x4C40,0x9930, +0x4AFB,0x9843,0x49B4,0x9759,0x486A,0x9674,0x471D,0x9592,0x45CD,0x94B5,0x447B, +0x93DC,0x4326,0x9307,0x41CE,0x9236,0x4074,0x9169,0x3F17,0x90A1,0x3DB8,0x8FDD, +0x3C57,0x8F1D,0x3AF3,0x8E62,0x398D,0x8DAB,0x3825,0x8CF8,0x36BA,0x8C4A,0x354E, +0x8BA0,0x33DF,0x8AFB,0x326E,0x8A5A,0x30FC,0x89BE,0x2F87,0x8927,0x2E11,0x8894, +0x2C99,0x8805,0x2B1F,0x877B,0x29A4,0x86F6,0x2827,0x8676,0x26A8,0x85FA,0x2528, +0x8583,0x23A7,0x8511,0x2224,0x84A3,0x209F,0x843A,0x1F1A,0x83D6,0x1D93,0x8377, +0x1C0C,0x831C,0x1A83,0x82C6,0x18F9,0x8276,0x176E,0x822A,0x15E2,0x81E2,0x1455, +0x81A0,0x12C8,0x8163,0x113A,0x812A,0x0FAB,0x80F6,0x0E1C,0x80C8,0x0C8C,0x809E, +0x0AFB,0x8079,0x096B,0x8059,0x07D9,0x803E,0x0648,0x8027,0x04B6,0x8016,0x0324, +0x800A,0x0192,0x8002,0x0000,0x8000,0xFE6E,0x8002,0xFCDC,0x800A,0xFB4A,0x8016, +0xF9B8,0x8027,0xF827,0x803E,0xF695,0x8059,0xF505,0x8079,0xF374,0x809E,0xF1E4, +0x80C8,0xF055,0x80F6,0xEEC6,0x812A,0xED38,0x8163,0xEBAB,0x81A0,0xEA1E,0x81E2, +0xE892,0x822A,0xE707,0x8276,0xE57D,0x82C6,0xE3F4,0x831C,0xE26D,0x8377,0xE0E6, +0x83D6,0xDF61,0x843A,0xDDDC,0x84A3,0xDC59,0x8511,0xDAD8,0x8583,0xD958,0x85FA, +0xD7D9,0x8676,0xD65C,0x86F6,0xD4E1,0x877B,0xD367,0x8805,0xD1EF,0x8894,0xD079, +0x8927,0xCF04,0x89BE,0xCD92,0x8A5A,0xCC21,0x8AFB,0xCAB2,0x8BA0,0xC946,0x8C4A, +0xC7DB,0x8CF8,0xC673,0x8DAB,0xC50D,0x8E62,0xC3A9,0x8F1D,0xC248,0x8FDD,0xC0E9, +0x90A1,0xBF8C,0x9169,0xBE32,0x9236,0xBCDA,0x9307,0xBB85,0x93DC,0xBA33,0x94B5, +0xB8E3,0x9592,0xB796,0x9674,0xB64C,0x9759,0xB505,0x9843,0xB3C0,0x9930,0xB27F, +0x9A22,0xB140,0x9B17,0xB005,0x9C11,0xAECC,0x9D0E,0xAD97,0x9E0F,0xAC65,0x9F14, +0xAB36,0xA01C,0xAA0A,0xA129,0xA8E2,0xA238,0xA7BD,0xA34C,0xA69C,0xA463,0xA57E, +0xA57E,0xA463,0xA69C,0xA34C,0xA7BD,0xA238,0xA8E2,0xA129,0xAA0A,0xA01C,0xAB36, +0x9F14,0xAC65,0x9E0F,0xAD97,0x9D0E,0xAECC,0x9C11,0xB005,0x9B17,0xB140,0x9A22, +0xB27F,0x9930,0xB3C0,0x9843,0xB505,0x9759,0xB64C,0x9674,0xB796,0x9592,0xB8E3, +0x94B5,0xBA33,0x93DC,0xBB85,0x9307,0xBCDA,0x9236,0xBE32,0x9169,0xBF8C,0x90A1, +0xC0E9,0x8FDD,0xC248,0x8F1D,0xC3A9,0x8E62,0xC50D,0x8DAB,0xC673,0x8CF8,0xC7DB, +0x8C4A,0xC946,0x8BA0,0xCAB2,0x8AFB,0xCC21,0x8A5A,0xCD92,0x89BE,0xCF04,0x8927, +0xD079,0x8894,0xD1EF,0x8805,0xD367,0x877B,0xD4E1,0x86F6,0xD65C,0x8676,0xD7D9, +0x85FA,0xD958,0x8583,0xDAD8,0x8511,0xDC59,0x84A3,0xDDDC,0x843A,0xDF61,0x83D6, +0xE0E6,0x8377,0xE26D,0x831C,0xE3F4,0x82C6,0xE57D,0x8276,0xE707,0x822A,0xE892, +0x81E2,0xEA1E,0x81A0,0xEBAB,0x8163,0xED38,0x812A,0xEEC6,0x80F6,0xF055,0x80C8, +0xF1E4,0x809E,0xF374,0x8079,0xF505,0x8059,0xF695,0x803E,0xF827,0x8027,0xF9B8, +0x8016,0xFB4A,0x800A,0xFCDC,0x8002,0xFE6E,0x7FFF,0x0000,0x7FD9,0xF9B8,0x7F62, +0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A,0xE0E6,0x7A7D,0xDAD8,0x7885,0xD4E1, +0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9,0x6DCA,0xBE32,0x6A6E,0xB8E3,0x66D0, +0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82,0xA57E,0x55F6,0xA129,0x5134,0x9D0E, +0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236,0x3C57,0x8F1D,0x36BA,0x8C4A,0x30FC, +0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A,0x83D6,0x18F9,0x8276,0x12C8,0x8163, +0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000,0xF9B8,0x8027,0xF374,0x809E,0xED38, +0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8,0x8583,0xD4E1,0x877B,0xCF04,0x89BE, +0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236,0xB8E3,0x9592,0xB3C0,0x9930,0xAECC, +0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129,0xAA0A,0x9D0E,0xAECC,0x9930,0xB3C0, +0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9,0x8C4A,0xC946,0x89BE,0xCF04,0x877B, +0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38,0x809E,0xF374, +0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E,0xB8E3,0x5A82, +0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000,0xE707,0x8276, +0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE,0xCF04,0x8276, +0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_1024_q15[680]={ +0x7FFF,0x0000,0x7FFA,0xFDA5,0x7FEA,0xFB4A,0x7FCE,0xF8EF,0x7FA7,0xF695,0x7F75, +0xF43C,0x7F38,0xF1E4,0x7EF0,0xEF8D,0x7E9D,0xED38,0x7E3F,0xEAE4,0x7DD6,0xE892, +0x7D63,0xE642,0x7CE4,0xE3F4,0x7C5A,0xE1A9,0x7BC6,0xDF61,0x7B27,0xDD1B,0x7A7D, +0xDAD8,0x79C9,0xD898,0x790A,0xD65C,0x7840,0xD424,0x776C,0xD1EF,0x768E,0xCFBE, +0x75A6,0xCD92,0x74B3,0xCB69,0x73B6,0xC946,0x72AF,0xC727,0x719E,0xC50D,0x7083, +0xC2F8,0x6F5F,0xC0E9,0x6E31,0xBEDF,0x6CF9,0xBCDA,0x6BB8,0xBADC,0x6A6E,0xB8E3, +0x691A,0xB6F1,0x67BD,0xB505,0x6657,0xB31F,0x64E9,0xB140,0x6371,0xAF68,0x61F1, +0xAD97,0x6068,0xABCD,0x5ED7,0xAA0A,0x5D3E,0xA84F,0x5B9D,0xA69C,0x59F4,0xA4F0, +0x5843,0xA34C,0x568A,0xA1B0,0x54CA,0xA01C,0x5303,0x9E91,0x5134,0x9D0E,0x4F5E, +0x9B94,0x4D81,0x9A22,0x4B9E,0x98B9,0x49B4,0x9759,0x47C4,0x9603,0x45CD,0x94B5, +0x43D1,0x9371,0x41CE,0x9236,0x3FC6,0x9105,0x3DB8,0x8FDD,0x3BA5,0x8EBF,0x398D, +0x8DAB,0x3770,0x8CA1,0x354E,0x8BA0,0x3327,0x8AAA,0x30FC,0x89BE,0x2ECC,0x88DD, +0x2C99,0x8805,0x2A62,0x8738,0x2827,0x8676,0x25E8,0x85BE,0x23A7,0x8511,0x2162, +0x846E,0x1F1A,0x83D6,0x1CD0,0x8349,0x1A83,0x82C6,0x1833,0x824F,0x15E2,0x81E2, +0x138F,0x8181,0x113A,0x812A,0x0EE4,0x80DE,0x0C8C,0x809E,0x0A33,0x8068,0x07D9, +0x803E,0x057F,0x801E,0x0324,0x800A,0x00C9,0x8001,0xFE6E,0x8002,0xFC13,0x800F, +0xF9B8,0x8027,0xF75E,0x804B,0xF505,0x8079,0xF2AC,0x80B2,0xF055,0x80F6,0xEDFF, +0x8146,0xEBAB,0x81A0,0xE958,0x8205,0xE707,0x8276,0xE4B9,0x82F1,0xE26D,0x8377, +0xE023,0x8407,0xDDDC,0x84A3,0xDB99,0x8549,0xD958,0x85FA,0xD71B,0x86B6,0xD4E1, +0x877B,0xD2AB,0x884C,0xD079,0x8927,0xCE4B,0x8A0C,0xCC21,0x8AFB,0xC9FC,0x8BF5, +0xC7DB,0x8CF8,0xC5C0,0x8E06,0xC3A9,0x8F1D,0xC198,0x903E,0xBF8C,0x9169,0xBD86, +0x929E,0xBB85,0x93DC,0xB98B,0x9523,0xB796,0x9674,0xB5A8,0x97CE,0xB3C0,0x9930, +0xB1DF,0x9A9C,0xB005,0x9C11,0xAE31,0x9D8E,0xAC65,0x9F14,0xAAA0,0xA0A2,0xA8E2, +0xA238,0xA72C,0xA3D7,0xA57E,0xA57E,0xA3D7,0xA72C,0xA238,0xA8E2,0xA0A2,0xAAA0, +0x9F14,0xAC65,0x9D8E,0xAE31,0x9C11,0xB005,0x9A9C,0xB1DF,0x9930,0xB3C0,0x97CE, +0xB5A8,0x9674,0xB796,0x9523,0xB98B,0x93DC,0xBB85,0x929E,0xBD86,0x9169,0xBF8C, +0x903E,0xC198,0x8F1D,0xC3A9,0x8E06,0xC5C0,0x8CF8,0xC7DB,0x8BF5,0xC9FC,0x8AFB, +0xCC21,0x8A0C,0xCE4B,0x8927,0xD079,0x884C,0xD2AB,0x877B,0xD4E1,0x86B6,0xD71B, +0x85FA,0xD958,0x8549,0xDB99,0x84A3,0xDDDC,0x8407,0xE023,0x8377,0xE26D,0x82F1, +0xE4B9,0x8276,0xE707,0x8205,0xE958,0x81A0,0xEBAB,0x8146,0xEDFF,0x80F6,0xF055, +0x80B2,0xF2AC,0x8079,0xF505,0x804B,0xF75E,0x8027,0xF9B8,0x800F,0xFC13,0x8002, +0xFE6E,0x8001,0x00C9,0x800A,0x0324,0x801E,0x057F,0x803E,0x07D9,0x8068,0x0A33, +0x809E,0x0C8C,0x80DE,0x0EE4,0x812A,0x113A,0x8181,0x138F,0x81E2,0x15E2,0x824F, +0x1833,0x82C6,0x1A83,0x8349,0x1CD0,0x83D6,0x1F1A,0x846E,0x2162,0x8511,0x23A7, +0x85BE,0x25E8,0x8676,0x2827,0x8738,0x2A62,0x8805,0x2C99,0x88DD,0x2ECC,0x89BE, +0x30FC,0x8AAA,0x3327,0x8BA0,0x354E,0x8CA1,0x3770,0x8DAB,0x398D,0x8EBF,0x3BA5, +0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5,0x45CD,0x9603, +0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E,0x9D0E,0x5134, +0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0,0x59F4,0xA69C, +0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1,0xAF68,0x6371, +0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3,0x6A6E,0xBADC, +0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083,0xC50D,0x719E, +0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE,0x768E,0xD1EF, +0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D,0xDD1B,0x7B27, +0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892,0x7DD6,0xEAE4, +0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75,0xF695,0x7FA7, +0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7,0xF695,0x7E9D, +0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946,0x6F5F,0xC0E9, +0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134,0x9D0E,0x49B4, +0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676,0x1F1A,0x83D6, +0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055,0x80F6,0xE707, +0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D,0xBB85,0x93DC, +0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930,0xB3C0,0x93DC, +0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC,0x8276,0xE707, +0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2,0x15E2,0x83D6, +0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE,0x9759,0x49B4, +0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3,0x6A6E,0xC0E9, +0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4,0xED38,0x7E9D, +0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134,0x9D0E,0x30FC, +0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E,0x8F1D,0xC3A9, +0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3,0x6A6E,0xDAD8, +0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]={ +0,2048,2560,2688,2720,0,}; + +q15_t rearranged_twiddle_stride1_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFFCE,0x7FFF,0xFF9B,0x7FFF,0xFF69,0x7FFF,0xFF37,0x7FFF, +0xFF05,0x7FFF,0xFED2,0x7FFE,0xFEA0,0x7FFE,0xFE6E,0x7FFD,0xFE3C,0x7FFC,0xFE09, +0x7FFB,0xFDD7,0x7FFA,0xFDA5,0x7FF9,0xFD73,0x7FF8,0xFD40,0x7FF7,0xFD0E,0x7FF6, +0xFCDC,0x7FF5,0xFCAA,0x7FF4,0xFC77,0x7FF2,0xFC45,0x7FF1,0xFC13,0x7FEF,0xFBE1, +0x7FED,0xFBAE,0x7FEC,0xFB7C,0x7FEA,0xFB4A,0x7FE8,0xFB18,0x7FE6,0xFAE5,0x7FE4, +0xFAB3,0x7FE2,0xFA81,0x7FE0,0xFA4F,0x7FDD,0xFA1D,0x7FDB,0xF9EA,0x7FD9,0xF9B8, +0x7FD6,0xF986,0x7FD3,0xF954,0x7FD1,0xF922,0x7FCE,0xF8EF,0x7FCB,0xF8BD,0x7FC8, +0xF88B,0x7FC5,0xF859,0x7FC2,0xF827,0x7FBF,0xF7F4,0x7FBC,0xF7C2,0x7FB9,0xF790, +0x7FB5,0xF75E,0x7FB2,0xF72C,0x7FAE,0xF6FA,0x7FAB,0xF6C8,0x7FA7,0xF695,0x7FA3, +0xF663,0x7FA0,0xF631,0x7F9C,0xF5FF,0x7F98,0xF5CD,0x7F94,0xF59B,0x7F90,0xF569, +0x7F8B,0xF537,0x7F87,0xF505,0x7F83,0xF4D3,0x7F7E,0xF4A0,0x7F7A,0xF46E,0x7F75, +0xF43C,0x7F71,0xF40A,0x7F6C,0xF3D8,0x7F67,0xF3A6,0x7F62,0xF374,0x7F5D,0xF342, +0x7F58,0xF310,0x7F53,0xF2DE,0x7F4E,0xF2AC,0x7F49,0xF27A,0x7F43,0xF248,0x7F3E, +0xF216,0x7F38,0xF1E4,0x7F33,0xF1B2,0x7F2D,0xF180,0x7F27,0xF14E,0x7F22,0xF11C, +0x7F1C,0xF0EB,0x7F16,0xF0B9,0x7F10,0xF087,0x7F0A,0xF055,0x7F03,0xF023,0x7EFD, +0xEFF1,0x7EF7,0xEFBF,0x7EF0,0xEF8D,0x7EEA,0xEF5C,0x7EE3,0xEF2A,0x7EDD,0xEEF8, +0x7ED6,0xEEC6,0x7ECF,0xEE94,0x7EC8,0xEE62,0x7EC1,0xEE31,0x7EBA,0xEDFF,0x7EB3, +0xEDCD,0x7EAC,0xED9B,0x7EA5,0xED6A,0x7E9D,0xED38,0x7E96,0xED06,0x7E8E,0xECD5, +0x7E87,0xECA3,0x7E7F,0xEC71,0x7E78,0xEC3F,0x7E70,0xEC0E,0x7E68,0xEBDC,0x7E60, +0xEBAB,0x7E58,0xEB79,0x7E50,0xEB47,0x7E48,0xEB16,0x7E3F,0xEAE4,0x7E37,0xEAB3, +0x7E2F,0xEA81,0x7E26,0xEA4F,0x7E1E,0xEA1E,0x7E15,0xE9EC,0x7E0C,0xE9BB,0x7E03, +0xE989,0x7DFB,0xE958,0x7DF2,0xE926,0x7DE9,0xE8F5,0x7DE0,0xE8C4,0x7DD6,0xE892, +0x7DCD,0xE861,0x7DC4,0xE82F,0x7DBA,0xE7FE,0x7DB1,0xE7CD,0x7DA7,0xE79B,0x7D9E, +0xE76A,0x7D94,0xE739,0x7D8A,0xE707,0x7D81,0xE6D6,0x7D77,0xE6A5,0x7D6D,0xE673, +0x7D63,0xE642,0x7D58,0xE611,0x7D4E,0xE5E0,0x7D44,0xE5AF,0x7D3A,0xE57D,0x7D2F, +0xE54C,0x7D25,0xE51B,0x7D1A,0xE4EA,0x7D0F,0xE4B9,0x7D05,0xE488,0x7CFA,0xE457, +0x7CEF,0xE426,0x7CE4,0xE3F4,0x7CD9,0xE3C3,0x7CCE,0xE392,0x7CC2,0xE361,0x7CB7, +0xE330,0x7CAC,0xE2FF,0x7CA0,0xE2CF,0x7C95,0xE29E,0x7C89,0xE26D,0x7C7E,0xE23C, +0x7C72,0xE20B,0x7C66,0xE1DA,0x7C5A,0xE1A9,0x7C4E,0xE178,0x7C42,0xE148,0x7C36, +0xE117,0x7C2A,0xE0E6,0x7C1E,0xE0B5,0x7C11,0xE085,0x7C05,0xE054,0x7BF9,0xE023, +0x7BEC,0xDFF2,0x7BDF,0xDFC2,0x7BD3,0xDF91,0x7BC6,0xDF61,0x7BB9,0xDF30,0x7BAC, +0xDEFF,0x7B9F,0xDECF,0x7B92,0xDE9E,0x7B85,0xDE6E,0x7B78,0xDE3D,0x7B6A,0xDE0D, +0x7B5D,0xDDDC,0x7B50,0xDDAC,0x7B42,0xDD7C,0x7B34,0xDD4B,0x7B27,0xDD1B,0x7B19, +0xDCEA,0x7B0B,0xDCBA,0x7AFD,0xDC8A,0x7AEF,0xDC59,0x7AE1,0xDC29,0x7AD3,0xDBF9, +0x7AC5,0xDBC9,0x7AB7,0xDB99,0x7AA8,0xDB68,0x7A9A,0xDB38,0x7A8C,0xDB08,0x7A7D, +0xDAD8,0x7A6E,0xDAA8,0x7A60,0xDA78,0x7A51,0xDA48,0x7A42,0xDA18,0x7A33,0xD9E8, +0x7A24,0xD9B8,0x7A15,0xD988,0x7A06,0xD958,0x79F7,0xD928,0x79E7,0xD8F8,0x79D8, +0xD8C8,0x79C9,0xD898,0x79B9,0xD869,0x79AA,0xD839,0x799A,0xD809,0x798A,0xD7D9, +0x797A,0xD7AA,0x796A,0xD77A,0x795B,0xD74A,0x794A,0xD71B,0x793A,0xD6EB,0x792A, +0xD6BB,0x791A,0xD68C,0x790A,0xD65C,0x78F9,0xD62D,0x78E9,0xD5FD,0x78D8,0xD5CE, +0x78C8,0xD59E,0x78B7,0xD56F,0x78A6,0xD53F,0x7895,0xD510,0x7885,0xD4E1,0x7874, +0xD4B1,0x7863,0xD482,0x7851,0xD453,0x7840,0xD424,0x782F,0xD3F4,0x781E,0xD3C5, +0x780C,0xD396,0x77FB,0xD367,0x77E9,0xD338,0x77D8,0xD309,0x77C6,0xD2DA,0x77B4, +0xD2AB,0x77A2,0xD27C,0x7790,0xD24D,0x777E,0xD21E,0x776C,0xD1EF,0x775A,0xD1C0, +0x7748,0xD191,0x7736,0xD162,0x7723,0xD134,0x7711,0xD105,0x76FE,0xD0D6,0x76EC, +0xD0A7,0x76D9,0xD079,0x76C7,0xD04A,0x76B4,0xD01B,0x76A1,0xCFED,0x768E,0xCFBE, +0x767B,0xCF90,0x7668,0xCF61,0x7655,0xCF33,0x7642,0xCF04,0x762E,0xCED6,0x761B, +0xCEA7,0x7608,0xCE79,0x75F4,0xCE4B,0x75E1,0xCE1C,0x75CD,0xCDEE,0x75B9,0xCDC0, +0x75A6,0xCD92,0x7592,0xCD63,0x757E,0xCD35,0x756A,0xCD07,0x7556,0xCCD9,0x7542, +0xCCAB,0x752D,0xCC7D,0x7519,0xCC4F,0x7505,0xCC21,0x74F0,0xCBF3,0x74DC,0xCBC5, +0x74C7,0xCB97,0x74B3,0xCB69,0x749E,0xCB3C,0x7489,0xCB0E,0x7475,0xCAE0,0x7460, +0xCAB2,0x744B,0xCA85,0x7436,0xCA57,0x7421,0xCA29,0x740B,0xC9FC,0x73F6,0xC9CE, +0x73E1,0xC9A1,0x73CB,0xC973,0x73B6,0xC946,0x73A0,0xC918,0x738B,0xC8EB,0x7375, +0xC8BE,0x735F,0xC890,0x734A,0xC863,0x7334,0xC836,0x731E,0xC809,0x7308,0xC7DB, +0x72F2,0xC7AE,0x72DC,0xC781,0x72C5,0xC754,0x72AF,0xC727,0x7299,0xC6FA,0x7282, +0xC6CD,0x726C,0xC6A0,0x7255,0xC673,0x723F,0xC646,0x7228,0xC619,0x7211,0xC5ED, +0x71FA,0xC5C0,0x71E3,0xC593,0x71CC,0xC566,0x71B5,0xC53A,0x719E,0xC50D,0x7187, +0xC4E0,0x7170,0xC4B4,0x7158,0xC487,0x7141,0xC45B,0x712A,0xC42E,0x7112,0xC402, +0x70FA,0xC3D6,0x70E3,0xC3A9,0x70CB,0xC37D,0x70B3,0xC351,0x709B,0xC324,0x7083, +0xC2F8,0x706B,0xC2CC,0x7053,0xC2A0,0x703B,0xC274,0x7023,0xC248,0x700B,0xC21C, +0x6FF2,0xC1F0,0x6FDA,0xC1C4,0x6FC2,0xC198,0x6FA9,0xC16C,0x6F90,0xC140,0x6F78, +0xC114,0x6F5F,0xC0E9,0x6F46,0xC0BD,0x6F2D,0xC091,0x6F14,0xC066,0x6EFB,0xC03A, +0x6EE2,0xC00F,0x6EC9,0xBFE3,0x6EB0,0xBFB8,0x6E97,0xBF8C,0x6E7D,0xBF61,0x6E64, +0xBF35,0x6E4A,0xBF0A,0x6E31,0xBEDF,0x6E17,0xBEB3,0x6DFE,0xBE88,0x6DE4,0xBE5D, +0x6DCA,0xBE32,0x6DB0,0xBE07,0x6D96,0xBDDC,0x6D7C,0xBDB1,0x6D62,0xBD86,0x6D48, +0xBD5B,0x6D2E,0xBD30,0x6D14,0xBD05,0x6CF9,0xBCDA,0x6CDF,0xBCAF,0x6CC4,0xBC85, +0x6CAA,0xBC5A,0x6C8F,0xBC2F,0x6C75,0xBC05,0x6C5A,0xBBDA,0x6C3F,0xBBB0,0x6C24, +0xBB85,0x6C09,0xBB5B,0x6BEE,0xBB30,0x6BD3,0xBB06,0x6BB8,0xBADC,0x6B9D,0xBAB1, +0x6B82,0xBA87,0x6B66,0xBA5D,0x6B4B,0xBA33,0x6B30,0xBA09,0x6B14,0xB9DF,0x6AF8, +0xB9B5,0x6ADD,0xB98B,0x6AC1,0xB961,0x6AA5,0xB937,0x6A89,0xB90D,0x6A6E,0xB8E3, +0x6A52,0xB8B9,0x6A36,0xB890,0x6A1A,0xB866,0x69FD,0xB83C,0x69E1,0xB813,0x69C5, +0xB7E9,0x69A9,0xB7C0,0x698C,0xB796,0x6970,0xB76D,0x6953,0xB743,0x6937,0xB71A, +0x691A,0xB6F1,0x68FD,0xB6C7,0x68E0,0xB69E,0x68C4,0xB675,0x68A7,0xB64C,0x688A, +0xB623,0x686D,0xB5FA,0x6850,0xB5D1,0x6832,0xB5A8,0x6815,0xB57F,0x67F8,0xB556, +0x67DA,0xB52D,0x67BD,0xB505,0x67A0,0xB4DC,0x6782,0xB4B3,0x6764,0xB48B,0x6747, +0xB462,0x6729,0xB439,0x670B,0xB411,0x66ED,0xB3E9,0x66D0,0xB3C0,0x66B2,0xB398, +0x6693,0xB36F,0x6675,0xB347,0x6657,0xB31F,0x6639,0xB2F7,0x661B,0xB2CF,0x65FC, +0xB2A7,0x65DE,0xB27F,0x65C0,0xB257,0x65A1,0xB22F,0x6582,0xB207,0x6564,0xB1DF, +0x6545,0xB1B7,0x6526,0xB18F,0x6507,0xB168,0x64E9,0xB140,0x64CA,0xB118,0x64AB, +0xB0F1,0x648B,0xB0C9,0x646C,0xB0A2,0x644D,0xB07B,0x642E,0xB053,0x640F,0xB02C, +0x63EF,0xB005,0x63D0,0xAFDD,0x63B0,0xAFB6,0x6391,0xAF8F,0x6371,0xAF68,0x6351, +0xAF41,0x6332,0xAF1A,0x6312,0xAEF3,0x62F2,0xAECC,0x62D2,0xAEA5,0x62B2,0xAE7F, +0x6292,0xAE58,0x6272,0xAE31,0x6252,0xAE0B,0x6232,0xADE4,0x6211,0xADBD,0x61F1, +0xAD97,0x61D1,0xAD70,0x61B0,0xAD4A,0x6190,0xAD24,0x616F,0xACFD,0x614E,0xACD7, +0x612E,0xACB1,0x610D,0xAC8B,0x60EC,0xAC65,0x60CB,0xAC3F,0x60AA,0xAC19,0x6089, +0xABF3,0x6068,0xABCD,0x6047,0xABA7,0x6026,0xAB81,0x6005,0xAB5C,0x5FE4,0xAB36, +0x5FC2,0xAB10,0x5FA1,0xAAEB,0x5F80,0xAAC5,0x5F5E,0xAAA0,0x5F3C,0xAA7A,0x5F1B, +0xAA55,0x5EF9,0xAA30,0x5ED7,0xAA0A,0x5EB6,0xA9E5,0x5E94,0xA9C0,0x5E72,0xA99B, +0x5E50,0xA976,0x5E2E,0xA951,0x5E0C,0xA92C,0x5DEA,0xA907,0x5DC8,0xA8E2,0x5DA5, +0xA8BD,0x5D83,0xA899,0x5D61,0xA874,0x5D3E,0xA84F,0x5D1C,0xA82B,0x5CF9,0xA806, +0x5CD7,0xA7E2,0x5CB4,0xA7BD,0x5C91,0xA799,0x5C6F,0xA774,0x5C4C,0xA750,0x5C29, +0xA72C,0x5C06,0xA708,0x5BE3,0xA6E4,0x5BC0,0xA6C0,0x5B9D,0xA69C,0x5B7A,0xA678, +0x5B57,0xA654,0x5B34,0xA630,0x5B10,0xA60C,0x5AED,0xA5E8,0x5AC9,0xA5C5,0x5AA6, +0xA5A1,0x5A82,0xA57E,0x5A5F,0xA55A,0x5A3B,0xA537,0x5A18,0xA513,0x59F4,0xA4F0, +0x59D0,0xA4CC,0x59AC,0xA4A9,0x5988,0xA486,0x5964,0xA463,0x5940,0xA440,0x591C, +0xA41D,0x58F8,0xA3FA,0x58D4,0xA3D7,0x58B0,0xA3B4,0x588C,0xA391,0x5867,0xA36F, +0x5843,0xA34C,0x581E,0xA329,0x57FA,0xA307,0x57D5,0xA2E4,0x57B1,0xA2C2,0x578C, +0xA29F,0x5767,0xA27D,0x5743,0xA25B,0x571E,0xA238,0x56F9,0xA216,0x56D4,0xA1F4, +0x56AF,0xA1D2,0x568A,0xA1B0,0x5665,0xA18E,0x5640,0xA16C,0x561B,0xA14A,0x55F6, +0xA129,0x55D0,0xA107,0x55AB,0xA0E5,0x5586,0xA0C4,0x5560,0xA0A2,0x553B,0xA080, +0x5515,0xA05F,0x54F0,0xA03E,0x54CA,0xA01C,0x54A4,0x9FFB,0x547F,0x9FDA,0x5459, +0x9FB9,0x5433,0x9F98,0x540D,0x9F77,0x53E7,0x9F56,0x53C1,0x9F35,0x539B,0x9F14, +0x5375,0x9EF3,0x534F,0x9ED2,0x5329,0x9EB2,0x5303,0x9E91,0x52DC,0x9E70,0x52B6, +0x9E50,0x5290,0x9E2F,0x5269,0x9E0F,0x5243,0x9DEF,0x521C,0x9DCE,0x51F5,0x9DAE, +0x51CF,0x9D8E,0x51A8,0x9D6E,0x5181,0x9D4E,0x515B,0x9D2E,0x5134,0x9D0E,0x510D, +0x9CEE,0x50E6,0x9CCE,0x50BF,0x9CAF,0x5098,0x9C8F,0x5071,0x9C6F,0x504A,0x9C50, +0x5023,0x9C30,0x4FFB,0x9C11,0x4FD4,0x9BF1,0x4FAD,0x9BD2,0x4F85,0x9BB3,0x4F5E, +0x9B94,0x4F37,0x9B75,0x4F0F,0x9B55,0x4EE8,0x9B36,0x4EC0,0x9B17,0x4E98,0x9AF9, +0x4E71,0x9ADA,0x4E49,0x9ABB,0x4E21,0x9A9C,0x4DF9,0x9A7E,0x4DD1,0x9A5F,0x4DA9, +0x9A40,0x4D81,0x9A22,0x4D59,0x9A04,0x4D31,0x99E5,0x4D09,0x99C7,0x4CE1,0x99A9, +0x4CB9,0x998B,0x4C91,0x996D,0x4C68,0x994E,0x4C40,0x9930,0x4C17,0x9913,0x4BEF, +0x98F5,0x4BC7,0x98D7,0x4B9E,0x98B9,0x4B75,0x989C,0x4B4D,0x987E,0x4B24,0x9860, +0x4AFB,0x9843,0x4AD3,0x9826,0x4AAA,0x9808,0x4A81,0x97EB,0x4A58,0x97CE,0x4A2F, +0x97B0,0x4A06,0x9793,0x49DD,0x9776,0x49B4,0x9759,0x498B,0x973C,0x4962,0x9720, +0x4939,0x9703,0x490F,0x96E6,0x48E6,0x96C9,0x48BD,0x96AD,0x4893,0x9690,0x486A, +0x9674,0x4840,0x9657,0x4817,0x963B,0x47ED,0x961F,0x47C4,0x9603,0x479A,0x95E6, +0x4770,0x95CA,0x4747,0x95AE,0x471D,0x9592,0x46F3,0x9577,0x46C9,0x955B,0x469F, +0x953F,0x4675,0x9523,0x464B,0x9508,0x4621,0x94EC,0x45F7,0x94D0,0x45CD,0x94B5, +0x45A3,0x949A,0x4579,0x947E,0x454F,0x9463,0x4524,0x9448,0x44FA,0x942D,0x44D0, +0x9412,0x44A5,0x93F7,0x447B,0x93DC,0x4450,0x93C1,0x4426,0x93A6,0x43FB,0x938B, +0x43D1,0x9371,0x43A6,0x9356,0x437B,0x933C,0x4351,0x9321,0x4326,0x9307,0x42FB, +0x92EC,0x42D0,0x92D2,0x42A5,0x92B8,0x427A,0x929E,0x424F,0x9284,0x4224,0x926A, +0x41F9,0x9250,0x41CE,0x9236,0x41A3,0x921C,0x4178,0x9202,0x414D,0x91E9,0x4121, +0x91CF,0x40F6,0x91B6,0x40CB,0x919C,0x409F,0x9183,0x4074,0x9169,0x4048,0x9150, +0x401D,0x9137,0x3FF1,0x911E,0x3FC6,0x9105,0x3F9A,0x90EC,0x3F6F,0x90D3,0x3F43, +0x90BA,0x3F17,0x90A1,0x3EEC,0x9088,0x3EC0,0x9070,0x3E94,0x9057,0x3E68,0x903E, +0x3E3C,0x9026,0x3E10,0x900E,0x3DE4,0x8FF5,0x3DB8,0x8FDD,0x3D8C,0x8FC5,0x3D60, +0x8FAD,0x3D34,0x8F95,0x3D08,0x8F7D,0x3CDC,0x8F65,0x3CAF,0x8F4D,0x3C83,0x8F35, +0x3C57,0x8F1D,0x3C2A,0x8F06,0x3BFE,0x8EEE,0x3BD2,0x8ED6,0x3BA5,0x8EBF,0x3B79, +0x8EA8,0x3B4C,0x8E90,0x3B20,0x8E79,0x3AF3,0x8E62,0x3AC6,0x8E4B,0x3A9A,0x8E34, +0x3A6D,0x8E1D,0x3A40,0x8E06,0x3A13,0x8DEF,0x39E7,0x8DD8,0x39BA,0x8DC1,0x398D, +0x8DAB,0x3960,0x8D94,0x3933,0x8D7E,0x3906,0x8D67,0x38D9,0x8D51,0x38AC,0x8D3B, +0x387F,0x8D24,0x3852,0x8D0E,0x3825,0x8CF8,0x37F7,0x8CE2,0x37CA,0x8CCC,0x379D, +0x8CB6,0x3770,0x8CA1,0x3742,0x8C8B,0x3715,0x8C75,0x36E8,0x8C60,0x36BA,0x8C4A, +0x368D,0x8C35,0x365F,0x8C1F,0x3632,0x8C0A,0x3604,0x8BF5,0x35D7,0x8BDF,0x35A9, +0x8BCA,0x357B,0x8BB5,0x354E,0x8BA0,0x3520,0x8B8B,0x34F2,0x8B77,0x34C4,0x8B62, +0x3497,0x8B4D,0x3469,0x8B39,0x343B,0x8B24,0x340D,0x8B10,0x33DF,0x8AFB,0x33B1, +0x8AE7,0x3383,0x8AD3,0x3355,0x8ABE,0x3327,0x8AAA,0x32F9,0x8A96,0x32CB,0x8A82, +0x329D,0x8A6E,0x326E,0x8A5A,0x3240,0x8A47,0x3212,0x8A33,0x31E4,0x8A1F,0x31B5, +0x8A0C,0x3187,0x89F8,0x3159,0x89E5,0x312A,0x89D2,0x30FC,0x89BE,0x30CD,0x89AB, +0x309F,0x8998,0x3070,0x8985,0x3042,0x8972,0x3013,0x895F,0x2FE5,0x894C,0x2FB6, +0x8939,0x2F87,0x8927,0x2F59,0x8914,0x2F2A,0x8902,0x2EFB,0x88EF,0x2ECC,0x88DD, +0x2E9E,0x88CA,0x2E6F,0x88B8,0x2E40,0x88A6,0x2E11,0x8894,0x2DE2,0x8882,0x2DB3, +0x8870,0x2D84,0x885E,0x2D55,0x884C,0x2D26,0x883A,0x2CF7,0x8828,0x2CC8,0x8817, +0x2C99,0x8805,0x2C6A,0x87F4,0x2C3B,0x87E2,0x2C0C,0x87D1,0x2BDC,0x87C0,0x2BAD, +0x87AF,0x2B7E,0x879D,0x2B4F,0x878C,0x2B1F,0x877B,0x2AF0,0x876B,0x2AC1,0x875A, +0x2A91,0x8749,0x2A62,0x8738,0x2A32,0x8728,0x2A03,0x8717,0x29D3,0x8707,0x29A4, +0x86F6,0x2974,0x86E6,0x2945,0x86D6,0x2915,0x86C6,0x28E5,0x86B6,0x28B6,0x86A5, +0x2886,0x8696,0x2856,0x8686,0x2827,0x8676,0x27F7,0x8666,0x27C7,0x8656,0x2797, +0x8647,0x2768,0x8637,0x2738,0x8628,0x2708,0x8619,0x26D8,0x8609,0x26A8,0x85FA, +0x2678,0x85EB,0x2648,0x85DC,0x2618,0x85CD,0x25E8,0x85BE,0x25B8,0x85AF,0x2588, +0x85A0,0x2558,0x8592,0x2528,0x8583,0x24F8,0x8574,0x24C8,0x8566,0x2498,0x8558, +0x2467,0x8549,0x2437,0x853B,0x2407,0x852D,0x23D7,0x851F,0x23A7,0x8511,0x2376, +0x8503,0x2346,0x84F5,0x2316,0x84E7,0x22E5,0x84D9,0x22B5,0x84CC,0x2284,0x84BE, +0x2254,0x84B0,0x2224,0x84A3,0x21F3,0x8496,0x21C3,0x8488,0x2192,0x847B,0x2162, +0x846E,0x2131,0x8461,0x2101,0x8454,0x20D0,0x8447,0x209F,0x843A,0x206F,0x842D, +0x203E,0x8421,0x200E,0x8414,0x1FDD,0x8407,0x1FAC,0x83FB,0x1F7B,0x83EF,0x1F4B, +0x83E2,0x1F1A,0x83D6,0x1EE9,0x83CA,0x1EB8,0x83BE,0x1E88,0x83B2,0x1E57,0x83A6, +0x1E26,0x839A,0x1DF5,0x838E,0x1DC4,0x8382,0x1D93,0x8377,0x1D62,0x836B,0x1D31, +0x8360,0x1D01,0x8354,0x1CD0,0x8349,0x1C9F,0x833E,0x1C6E,0x8332,0x1C3D,0x8327, +0x1C0C,0x831C,0x1BDA,0x8311,0x1BA9,0x8306,0x1B78,0x82FB,0x1B47,0x82F1,0x1B16, +0x82E6,0x1AE5,0x82DB,0x1AB4,0x82D1,0x1A83,0x82C6,0x1A51,0x82BC,0x1A20,0x82B2, +0x19EF,0x82A8,0x19BE,0x829D,0x198D,0x8293,0x195B,0x8289,0x192A,0x827F,0x18F9, +0x8276,0x18C7,0x826C,0x1896,0x8262,0x1865,0x8259,0x1833,0x824F,0x1802,0x8246, +0x17D1,0x823C,0x179F,0x8233,0x176E,0x822A,0x173C,0x8220,0x170B,0x8217,0x16DA, +0x820E,0x16A8,0x8205,0x1677,0x81FD,0x1645,0x81F4,0x1614,0x81EB,0x15E2,0x81E2, +0x15B1,0x81DA,0x157F,0x81D1,0x154D,0x81C9,0x151C,0x81C1,0x14EA,0x81B8,0x14B9, +0x81B0,0x1487,0x81A8,0x1455,0x81A0,0x1424,0x8198,0x13F2,0x8190,0x13C1,0x8188, +0x138F,0x8181,0x135D,0x8179,0x132B,0x8172,0x12FA,0x816A,0x12C8,0x8163,0x1296, +0x815B,0x1265,0x8154,0x1233,0x814D,0x1201,0x8146,0x11CF,0x813F,0x119E,0x8138, +0x116C,0x8131,0x113A,0x812A,0x1108,0x8123,0x10D6,0x811D,0x10A4,0x8116,0x1073, +0x8110,0x1041,0x8109,0x100F,0x8103,0x0FDD,0x80FD,0x0FAB,0x80F6,0x0F79,0x80F0, +0x0F47,0x80EA,0x0F15,0x80E4,0x0EE4,0x80DE,0x0EB2,0x80D9,0x0E80,0x80D3,0x0E4E, +0x80CD,0x0E1C,0x80C8,0x0DEA,0x80C2,0x0DB8,0x80BD,0x0D86,0x80B7,0x0D54,0x80B2, +0x0D22,0x80AD,0x0CF0,0x80A8,0x0CBE,0x80A3,0x0C8C,0x809E,0x0C5A,0x8099,0x0C28, +0x8094,0x0BF6,0x808F,0x0BC4,0x808B,0x0B92,0x8086,0x0B60,0x8082,0x0B2D,0x807D, +0x0AFB,0x8079,0x0AC9,0x8075,0x0A97,0x8070,0x0A65,0x806C,0x0A33,0x8068,0x0A01, +0x8064,0x09CF,0x8060,0x099D,0x805D,0x096B,0x8059,0x0938,0x8055,0x0906,0x8052, +0x08D4,0x804E,0x08A2,0x804B,0x0870,0x8047,0x083E,0x8044,0x080C,0x8041,0x07D9, +0x803E,0x07A7,0x803B,0x0775,0x8038,0x0743,0x8035,0x0711,0x8032,0x06DE,0x802F, +0x06AC,0x802D,0x067A,0x802A,0x0648,0x8027,0x0616,0x8025,0x05E3,0x8023,0x05B1, +0x8020,0x057F,0x801E,0x054D,0x801C,0x051B,0x801A,0x04E8,0x8018,0x04B6,0x8016, +0x0484,0x8014,0x0452,0x8013,0x041F,0x8011,0x03ED,0x800F,0x03BB,0x800E,0x0389, +0x800C,0x0356,0x800B,0x0324,0x800A,0x02F2,0x8009,0x02C0,0x8008,0x028D,0x8007, +0x025B,0x8006,0x0229,0x8005,0x01F7,0x8004,0x01C4,0x8003,0x0192,0x8002,0x0160, +0x8002,0x012E,0x8001,0x00FB,0x8001,0x00C9,0x8001,0x0097,0x8000,0x0065,0x8000, +0x0032,0x8000,0x7FFF,0x0000,0x7FFF,0xFF37,0x7FFE,0xFE6E,0x7FFA,0xFDA5,0x7FF6, +0xFCDC,0x7FF1,0xFC13,0x7FEA,0xFB4A,0x7FE2,0xFA81,0x7FD9,0xF9B8,0x7FCE,0xF8EF, +0x7FC2,0xF827,0x7FB5,0xF75E,0x7FA7,0xF695,0x7F98,0xF5CD,0x7F87,0xF505,0x7F75, +0xF43C,0x7F62,0xF374,0x7F4E,0xF2AC,0x7F38,0xF1E4,0x7F22,0xF11C,0x7F0A,0xF055, +0x7EF0,0xEF8D,0x7ED6,0xEEC6,0x7EBA,0xEDFF,0x7E9D,0xED38,0x7E7F,0xEC71,0x7E60, +0xEBAB,0x7E3F,0xEAE4,0x7E1E,0xEA1E,0x7DFB,0xE958,0x7DD6,0xE892,0x7DB1,0xE7CD, +0x7D8A,0xE707,0x7D63,0xE642,0x7D3A,0xE57D,0x7D0F,0xE4B9,0x7CE4,0xE3F4,0x7CB7, +0xE330,0x7C89,0xE26D,0x7C5A,0xE1A9,0x7C2A,0xE0E6,0x7BF9,0xE023,0x7BC6,0xDF61, +0x7B92,0xDE9E,0x7B5D,0xDDDC,0x7B27,0xDD1B,0x7AEF,0xDC59,0x7AB7,0xDB99,0x7A7D, +0xDAD8,0x7A42,0xDA18,0x7A06,0xD958,0x79C9,0xD898,0x798A,0xD7D9,0x794A,0xD71B, +0x790A,0xD65C,0x78C8,0xD59E,0x7885,0xD4E1,0x7840,0xD424,0x77FB,0xD367,0x77B4, +0xD2AB,0x776C,0xD1EF,0x7723,0xD134,0x76D9,0xD079,0x768E,0xCFBE,0x7642,0xCF04, +0x75F4,0xCE4B,0x75A6,0xCD92,0x7556,0xCCD9,0x7505,0xCC21,0x74B3,0xCB69,0x7460, +0xCAB2,0x740B,0xC9FC,0x73B6,0xC946,0x735F,0xC890,0x7308,0xC7DB,0x72AF,0xC727, +0x7255,0xC673,0x71FA,0xC5C0,0x719E,0xC50D,0x7141,0xC45B,0x70E3,0xC3A9,0x7083, +0xC2F8,0x7023,0xC248,0x6FC2,0xC198,0x6F5F,0xC0E9,0x6EFB,0xC03A,0x6E97,0xBF8C, +0x6E31,0xBEDF,0x6DCA,0xBE32,0x6D62,0xBD86,0x6CF9,0xBCDA,0x6C8F,0xBC2F,0x6C24, +0xBB85,0x6BB8,0xBADC,0x6B4B,0xBA33,0x6ADD,0xB98B,0x6A6E,0xB8E3,0x69FD,0xB83C, +0x698C,0xB796,0x691A,0xB6F1,0x68A7,0xB64C,0x6832,0xB5A8,0x67BD,0xB505,0x6747, +0xB462,0x66D0,0xB3C0,0x6657,0xB31F,0x65DE,0xB27F,0x6564,0xB1DF,0x64E9,0xB140, +0x646C,0xB0A2,0x63EF,0xB005,0x6371,0xAF68,0x62F2,0xAECC,0x6272,0xAE31,0x61F1, +0xAD97,0x616F,0xACFD,0x60EC,0xAC65,0x6068,0xABCD,0x5FE4,0xAB36,0x5F5E,0xAAA0, +0x5ED7,0xAA0A,0x5E50,0xA976,0x5DC8,0xA8E2,0x5D3E,0xA84F,0x5CB4,0xA7BD,0x5C29, +0xA72C,0x5B9D,0xA69C,0x5B10,0xA60C,0x5A82,0xA57E,0x59F4,0xA4F0,0x5964,0xA463, +0x58D4,0xA3D7,0x5843,0xA34C,0x57B1,0xA2C2,0x571E,0xA238,0x568A,0xA1B0,0x55F6, +0xA129,0x5560,0xA0A2,0x54CA,0xA01C,0x5433,0x9F98,0x539B,0x9F14,0x5303,0x9E91, +0x5269,0x9E0F,0x51CF,0x9D8E,0x5134,0x9D0E,0x5098,0x9C8F,0x4FFB,0x9C11,0x4F5E, +0x9B94,0x4EC0,0x9B17,0x4E21,0x9A9C,0x4D81,0x9A22,0x4CE1,0x99A9,0x4C40,0x9930, +0x4B9E,0x98B9,0x4AFB,0x9843,0x4A58,0x97CE,0x49B4,0x9759,0x490F,0x96E6,0x486A, +0x9674,0x47C4,0x9603,0x471D,0x9592,0x4675,0x9523,0x45CD,0x94B5,0x4524,0x9448, +0x447B,0x93DC,0x43D1,0x9371,0x4326,0x9307,0x427A,0x929E,0x41CE,0x9236,0x4121, +0x91CF,0x4074,0x9169,0x3FC6,0x9105,0x3F17,0x90A1,0x3E68,0x903E,0x3DB8,0x8FDD, +0x3D08,0x8F7D,0x3C57,0x8F1D,0x3BA5,0x8EBF,0x3AF3,0x8E62,0x3A40,0x8E06,0x398D, +0x8DAB,0x38D9,0x8D51,0x3825,0x8CF8,0x3770,0x8CA1,0x36BA,0x8C4A,0x3604,0x8BF5, +0x354E,0x8BA0,0x3497,0x8B4D,0x33DF,0x8AFB,0x3327,0x8AAA,0x326E,0x8A5A,0x31B5, +0x8A0C,0x30FC,0x89BE,0x3042,0x8972,0x2F87,0x8927,0x2ECC,0x88DD,0x2E11,0x8894, +0x2D55,0x884C,0x2C99,0x8805,0x2BDC,0x87C0,0x2B1F,0x877B,0x2A62,0x8738,0x29A4, +0x86F6,0x28E5,0x86B6,0x2827,0x8676,0x2768,0x8637,0x26A8,0x85FA,0x25E8,0x85BE, +0x2528,0x8583,0x2467,0x8549,0x23A7,0x8511,0x22E5,0x84D9,0x2224,0x84A3,0x2162, +0x846E,0x209F,0x843A,0x1FDD,0x8407,0x1F1A,0x83D6,0x1E57,0x83A6,0x1D93,0x8377, +0x1CD0,0x8349,0x1C0C,0x831C,0x1B47,0x82F1,0x1A83,0x82C6,0x19BE,0x829D,0x18F9, +0x8276,0x1833,0x824F,0x176E,0x822A,0x16A8,0x8205,0x15E2,0x81E2,0x151C,0x81C1, +0x1455,0x81A0,0x138F,0x8181,0x12C8,0x8163,0x1201,0x8146,0x113A,0x812A,0x1073, +0x8110,0x0FAB,0x80F6,0x0EE4,0x80DE,0x0E1C,0x80C8,0x0D54,0x80B2,0x0C8C,0x809E, +0x0BC4,0x808B,0x0AFB,0x8079,0x0A33,0x8068,0x096B,0x8059,0x08A2,0x804B,0x07D9, +0x803E,0x0711,0x8032,0x0648,0x8027,0x057F,0x801E,0x04B6,0x8016,0x03ED,0x800F, +0x0324,0x800A,0x025B,0x8006,0x0192,0x8002,0x00C9,0x8001,0x7FFF,0x0000,0x7FF6, +0xFCDC,0x7FD9,0xF9B8,0x7FA7,0xF695,0x7F62,0xF374,0x7F0A,0xF055,0x7E9D,0xED38, +0x7E1E,0xEA1E,0x7D8A,0xE707,0x7CE4,0xE3F4,0x7C2A,0xE0E6,0x7B5D,0xDDDC,0x7A7D, +0xDAD8,0x798A,0xD7D9,0x7885,0xD4E1,0x776C,0xD1EF,0x7642,0xCF04,0x7505,0xCC21, +0x73B6,0xC946,0x7255,0xC673,0x70E3,0xC3A9,0x6F5F,0xC0E9,0x6DCA,0xBE32,0x6C24, +0xBB85,0x6A6E,0xB8E3,0x68A7,0xB64C,0x66D0,0xB3C0,0x64E9,0xB140,0x62F2,0xAECC, +0x60EC,0xAC65,0x5ED7,0xAA0A,0x5CB4,0xA7BD,0x5A82,0xA57E,0x5843,0xA34C,0x55F6, +0xA129,0x539B,0x9F14,0x5134,0x9D0E,0x4EC0,0x9B17,0x4C40,0x9930,0x49B4,0x9759, +0x471D,0x9592,0x447B,0x93DC,0x41CE,0x9236,0x3F17,0x90A1,0x3C57,0x8F1D,0x398D, +0x8DAB,0x36BA,0x8C4A,0x33DF,0x8AFB,0x30FC,0x89BE,0x2E11,0x8894,0x2B1F,0x877B, +0x2827,0x8676,0x2528,0x8583,0x2224,0x84A3,0x1F1A,0x83D6,0x1C0C,0x831C,0x18F9, +0x8276,0x15E2,0x81E2,0x12C8,0x8163,0x0FAB,0x80F6,0x0C8C,0x809E,0x096B,0x8059, +0x0648,0x8027,0x0324,0x800A,0x7FFF,0x0000,0x7F62,0xF374,0x7D8A,0xE707,0x7A7D, +0xDAD8,0x7642,0xCF04,0x70E3,0xC3A9,0x6A6E,0xB8E3,0x62F2,0xAECC,0x5A82,0xA57E, +0x5134,0x9D0E,0x471D,0x9592,0x3C57,0x8F1D,0x30FC,0x89BE,0x2528,0x8583,0x18F9, +0x8276,0x0C8C,0x809E,0x7FFF,0x0000,0x7642,0xCF04,0x5A82,0xA57E,0x30FC,0x89BE,}; + +q15_t rearranged_twiddle_stride2_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFF9B,0x7FFF,0xFF37,0x7FFF,0xFED2,0x7FFE,0xFE6E,0x7FFC, +0xFE09,0x7FFA,0xFDA5,0x7FF8,0xFD40,0x7FF6,0xFCDC,0x7FF4,0xFC77,0x7FF1,0xFC13, +0x7FED,0xFBAE,0x7FEA,0xFB4A,0x7FE6,0xFAE5,0x7FE2,0xFA81,0x7FDD,0xFA1D,0x7FD9, +0xF9B8,0x7FD3,0xF954,0x7FCE,0xF8EF,0x7FC8,0xF88B,0x7FC2,0xF827,0x7FBC,0xF7C2, +0x7FB5,0xF75E,0x7FAE,0xF6FA,0x7FA7,0xF695,0x7FA0,0xF631,0x7F98,0xF5CD,0x7F90, +0xF569,0x7F87,0xF505,0x7F7E,0xF4A0,0x7F75,0xF43C,0x7F6C,0xF3D8,0x7F62,0xF374, +0x7F58,0xF310,0x7F4E,0xF2AC,0x7F43,0xF248,0x7F38,0xF1E4,0x7F2D,0xF180,0x7F22, +0xF11C,0x7F16,0xF0B9,0x7F0A,0xF055,0x7EFD,0xEFF1,0x7EF0,0xEF8D,0x7EE3,0xEF2A, +0x7ED6,0xEEC6,0x7EC8,0xEE62,0x7EBA,0xEDFF,0x7EAC,0xED9B,0x7E9D,0xED38,0x7E8E, +0xECD5,0x7E7F,0xEC71,0x7E70,0xEC0E,0x7E60,0xEBAB,0x7E50,0xEB47,0x7E3F,0xEAE4, +0x7E2F,0xEA81,0x7E1E,0xEA1E,0x7E0C,0xE9BB,0x7DFB,0xE958,0x7DE9,0xE8F5,0x7DD6, +0xE892,0x7DC4,0xE82F,0x7DB1,0xE7CD,0x7D9E,0xE76A,0x7D8A,0xE707,0x7D77,0xE6A5, +0x7D63,0xE642,0x7D4E,0xE5E0,0x7D3A,0xE57D,0x7D25,0xE51B,0x7D0F,0xE4B9,0x7CFA, +0xE457,0x7CE4,0xE3F4,0x7CCE,0xE392,0x7CB7,0xE330,0x7CA0,0xE2CF,0x7C89,0xE26D, +0x7C72,0xE20B,0x7C5A,0xE1A9,0x7C42,0xE148,0x7C2A,0xE0E6,0x7C11,0xE085,0x7BF9, +0xE023,0x7BDF,0xDFC2,0x7BC6,0xDF61,0x7BAC,0xDEFF,0x7B92,0xDE9E,0x7B78,0xDE3D, +0x7B5D,0xDDDC,0x7B42,0xDD7C,0x7B27,0xDD1B,0x7B0B,0xDCBA,0x7AEF,0xDC59,0x7AD3, +0xDBF9,0x7AB7,0xDB99,0x7A9A,0xDB38,0x7A7D,0xDAD8,0x7A60,0xDA78,0x7A42,0xDA18, +0x7A24,0xD9B8,0x7A06,0xD958,0x79E7,0xD8F8,0x79C9,0xD898,0x79AA,0xD839,0x798A, +0xD7D9,0x796A,0xD77A,0x794A,0xD71B,0x792A,0xD6BB,0x790A,0xD65C,0x78E9,0xD5FD, +0x78C8,0xD59E,0x78A6,0xD53F,0x7885,0xD4E1,0x7863,0xD482,0x7840,0xD424,0x781E, +0xD3C5,0x77FB,0xD367,0x77D8,0xD309,0x77B4,0xD2AB,0x7790,0xD24D,0x776C,0xD1EF, +0x7748,0xD191,0x7723,0xD134,0x76FE,0xD0D6,0x76D9,0xD079,0x76B4,0xD01B,0x768E, +0xCFBE,0x7668,0xCF61,0x7642,0xCF04,0x761B,0xCEA7,0x75F4,0xCE4B,0x75CD,0xCDEE, +0x75A6,0xCD92,0x757E,0xCD35,0x7556,0xCCD9,0x752D,0xCC7D,0x7505,0xCC21,0x74DC, +0xCBC5,0x74B3,0xCB69,0x7489,0xCB0E,0x7460,0xCAB2,0x7436,0xCA57,0x740B,0xC9FC, +0x73E1,0xC9A1,0x73B6,0xC946,0x738B,0xC8EB,0x735F,0xC890,0x7334,0xC836,0x7308, +0xC7DB,0x72DC,0xC781,0x72AF,0xC727,0x7282,0xC6CD,0x7255,0xC673,0x7228,0xC619, +0x71FA,0xC5C0,0x71CC,0xC566,0x719E,0xC50D,0x7170,0xC4B4,0x7141,0xC45B,0x7112, +0xC402,0x70E3,0xC3A9,0x70B3,0xC351,0x7083,0xC2F8,0x7053,0xC2A0,0x7023,0xC248, +0x6FF2,0xC1F0,0x6FC2,0xC198,0x6F90,0xC140,0x6F5F,0xC0E9,0x6F2D,0xC091,0x6EFB, +0xC03A,0x6EC9,0xBFE3,0x6E97,0xBF8C,0x6E64,0xBF35,0x6E31,0xBEDF,0x6DFE,0xBE88, +0x6DCA,0xBE32,0x6D96,0xBDDC,0x6D62,0xBD86,0x6D2E,0xBD30,0x6CF9,0xBCDA,0x6CC4, +0xBC85,0x6C8F,0xBC2F,0x6C5A,0xBBDA,0x6C24,0xBB85,0x6BEE,0xBB30,0x6BB8,0xBADC, +0x6B82,0xBA87,0x6B4B,0xBA33,0x6B14,0xB9DF,0x6ADD,0xB98B,0x6AA5,0xB937,0x6A6E, +0xB8E3,0x6A36,0xB890,0x69FD,0xB83C,0x69C5,0xB7E9,0x698C,0xB796,0x6953,0xB743, +0x691A,0xB6F1,0x68E0,0xB69E,0x68A7,0xB64C,0x686D,0xB5FA,0x6832,0xB5A8,0x67F8, +0xB556,0x67BD,0xB505,0x6782,0xB4B3,0x6747,0xB462,0x670B,0xB411,0x66D0,0xB3C0, +0x6693,0xB36F,0x6657,0xB31F,0x661B,0xB2CF,0x65DE,0xB27F,0x65A1,0xB22F,0x6564, +0xB1DF,0x6526,0xB18F,0x64E9,0xB140,0x64AB,0xB0F1,0x646C,0xB0A2,0x642E,0xB053, +0x63EF,0xB005,0x63B0,0xAFB6,0x6371,0xAF68,0x6332,0xAF1A,0x62F2,0xAECC,0x62B2, +0xAE7F,0x6272,0xAE31,0x6232,0xADE4,0x61F1,0xAD97,0x61B0,0xAD4A,0x616F,0xACFD, +0x612E,0xACB1,0x60EC,0xAC65,0x60AA,0xAC19,0x6068,0xABCD,0x6026,0xAB81,0x5FE4, +0xAB36,0x5FA1,0xAAEB,0x5F5E,0xAAA0,0x5F1B,0xAA55,0x5ED7,0xAA0A,0x5E94,0xA9C0, +0x5E50,0xA976,0x5E0C,0xA92C,0x5DC8,0xA8E2,0x5D83,0xA899,0x5D3E,0xA84F,0x5CF9, +0xA806,0x5CB4,0xA7BD,0x5C6F,0xA774,0x5C29,0xA72C,0x5BE3,0xA6E4,0x5B9D,0xA69C, +0x5B57,0xA654,0x5B10,0xA60C,0x5AC9,0xA5C5,0x5A82,0xA57E,0x5A3B,0xA537,0x59F4, +0xA4F0,0x59AC,0xA4A9,0x5964,0xA463,0x591C,0xA41D,0x58D4,0xA3D7,0x588C,0xA391, +0x5843,0xA34C,0x57FA,0xA307,0x57B1,0xA2C2,0x5767,0xA27D,0x571E,0xA238,0x56D4, +0xA1F4,0x568A,0xA1B0,0x5640,0xA16C,0x55F6,0xA129,0x55AB,0xA0E5,0x5560,0xA0A2, +0x5515,0xA05F,0x54CA,0xA01C,0x547F,0x9FDA,0x5433,0x9F98,0x53E7,0x9F56,0x539B, +0x9F14,0x534F,0x9ED2,0x5303,0x9E91,0x52B6,0x9E50,0x5269,0x9E0F,0x521C,0x9DCE, +0x51CF,0x9D8E,0x5181,0x9D4E,0x5134,0x9D0E,0x50E6,0x9CCE,0x5098,0x9C8F,0x504A, +0x9C50,0x4FFB,0x9C11,0x4FAD,0x9BD2,0x4F5E,0x9B94,0x4F0F,0x9B55,0x4EC0,0x9B17, +0x4E71,0x9ADA,0x4E21,0x9A9C,0x4DD1,0x9A5F,0x4D81,0x9A22,0x4D31,0x99E5,0x4CE1, +0x99A9,0x4C91,0x996D,0x4C40,0x9930,0x4BEF,0x98F5,0x4B9E,0x98B9,0x4B4D,0x987E, +0x4AFB,0x9843,0x4AAA,0x9808,0x4A58,0x97CE,0x4A06,0x9793,0x49B4,0x9759,0x4962, +0x9720,0x490F,0x96E6,0x48BD,0x96AD,0x486A,0x9674,0x4817,0x963B,0x47C4,0x9603, +0x4770,0x95CA,0x471D,0x9592,0x46C9,0x955B,0x4675,0x9523,0x4621,0x94EC,0x45CD, +0x94B5,0x4579,0x947E,0x4524,0x9448,0x44D0,0x9412,0x447B,0x93DC,0x4426,0x93A6, +0x43D1,0x9371,0x437B,0x933C,0x4326,0x9307,0x42D0,0x92D2,0x427A,0x929E,0x4224, +0x926A,0x41CE,0x9236,0x4178,0x9202,0x4121,0x91CF,0x40CB,0x919C,0x4074,0x9169, +0x401D,0x9137,0x3FC6,0x9105,0x3F6F,0x90D3,0x3F17,0x90A1,0x3EC0,0x9070,0x3E68, +0x903E,0x3E10,0x900E,0x3DB8,0x8FDD,0x3D60,0x8FAD,0x3D08,0x8F7D,0x3CAF,0x8F4D, +0x3C57,0x8F1D,0x3BFE,0x8EEE,0x3BA5,0x8EBF,0x3B4C,0x8E90,0x3AF3,0x8E62,0x3A9A, +0x8E34,0x3A40,0x8E06,0x39E7,0x8DD8,0x398D,0x8DAB,0x3933,0x8D7E,0x38D9,0x8D51, +0x387F,0x8D24,0x3825,0x8CF8,0x37CA,0x8CCC,0x3770,0x8CA1,0x3715,0x8C75,0x36BA, +0x8C4A,0x365F,0x8C1F,0x3604,0x8BF5,0x35A9,0x8BCA,0x354E,0x8BA0,0x34F2,0x8B77, +0x3497,0x8B4D,0x343B,0x8B24,0x33DF,0x8AFB,0x3383,0x8AD3,0x3327,0x8AAA,0x32CB, +0x8A82,0x326E,0x8A5A,0x3212,0x8A33,0x31B5,0x8A0C,0x3159,0x89E5,0x30FC,0x89BE, +0x309F,0x8998,0x3042,0x8972,0x2FE5,0x894C,0x2F87,0x8927,0x2F2A,0x8902,0x2ECC, +0x88DD,0x2E6F,0x88B8,0x2E11,0x8894,0x2DB3,0x8870,0x2D55,0x884C,0x2CF7,0x8828, +0x2C99,0x8805,0x2C3B,0x87E2,0x2BDC,0x87C0,0x2B7E,0x879D,0x2B1F,0x877B,0x2AC1, +0x875A,0x2A62,0x8738,0x2A03,0x8717,0x29A4,0x86F6,0x2945,0x86D6,0x28E5,0x86B6, +0x2886,0x8696,0x2827,0x8676,0x27C7,0x8656,0x2768,0x8637,0x2708,0x8619,0x26A8, +0x85FA,0x2648,0x85DC,0x25E8,0x85BE,0x2588,0x85A0,0x2528,0x8583,0x24C8,0x8566, +0x2467,0x8549,0x2407,0x852D,0x23A7,0x8511,0x2346,0x84F5,0x22E5,0x84D9,0x2284, +0x84BE,0x2224,0x84A3,0x21C3,0x8488,0x2162,0x846E,0x2101,0x8454,0x209F,0x843A, +0x203E,0x8421,0x1FDD,0x8407,0x1F7B,0x83EF,0x1F1A,0x83D6,0x1EB8,0x83BE,0x1E57, +0x83A6,0x1DF5,0x838E,0x1D93,0x8377,0x1D31,0x8360,0x1CD0,0x8349,0x1C6E,0x8332, +0x1C0C,0x831C,0x1BA9,0x8306,0x1B47,0x82F1,0x1AE5,0x82DB,0x1A83,0x82C6,0x1A20, +0x82B2,0x19BE,0x829D,0x195B,0x8289,0x18F9,0x8276,0x1896,0x8262,0x1833,0x824F, +0x17D1,0x823C,0x176E,0x822A,0x170B,0x8217,0x16A8,0x8205,0x1645,0x81F4,0x15E2, +0x81E2,0x157F,0x81D1,0x151C,0x81C1,0x14B9,0x81B0,0x1455,0x81A0,0x13F2,0x8190, +0x138F,0x8181,0x132B,0x8172,0x12C8,0x8163,0x1265,0x8154,0x1201,0x8146,0x119E, +0x8138,0x113A,0x812A,0x10D6,0x811D,0x1073,0x8110,0x100F,0x8103,0x0FAB,0x80F6, +0x0F47,0x80EA,0x0EE4,0x80DE,0x0E80,0x80D3,0x0E1C,0x80C8,0x0DB8,0x80BD,0x0D54, +0x80B2,0x0CF0,0x80A8,0x0C8C,0x809E,0x0C28,0x8094,0x0BC4,0x808B,0x0B60,0x8082, +0x0AFB,0x8079,0x0A97,0x8070,0x0A33,0x8068,0x09CF,0x8060,0x096B,0x8059,0x0906, +0x8052,0x08A2,0x804B,0x083E,0x8044,0x07D9,0x803E,0x0775,0x8038,0x0711,0x8032, +0x06AC,0x802D,0x0648,0x8027,0x05E3,0x8023,0x057F,0x801E,0x051B,0x801A,0x04B6, +0x8016,0x0452,0x8013,0x03ED,0x800F,0x0389,0x800C,0x0324,0x800A,0x02C0,0x8008, +0x025B,0x8006,0x01F7,0x8004,0x0192,0x8002,0x012E,0x8001,0x00C9,0x8001,0x0065, +0x8000,0x0000,0x8000,0xFF9B,0x8000,0xFF37,0x8001,0xFED2,0x8001,0xFE6E,0x8002, +0xFE09,0x8004,0xFDA5,0x8006,0xFD40,0x8008,0xFCDC,0x800A,0xFC77,0x800C,0xFC13, +0x800F,0xFBAE,0x8013,0xFB4A,0x8016,0xFAE5,0x801A,0xFA81,0x801E,0xFA1D,0x8023, +0xF9B8,0x8027,0xF954,0x802D,0xF8EF,0x8032,0xF88B,0x8038,0xF827,0x803E,0xF7C2, +0x8044,0xF75E,0x804B,0xF6FA,0x8052,0xF695,0x8059,0xF631,0x8060,0xF5CD,0x8068, +0xF569,0x8070,0xF505,0x8079,0xF4A0,0x8082,0xF43C,0x808B,0xF3D8,0x8094,0xF374, +0x809E,0xF310,0x80A8,0xF2AC,0x80B2,0xF248,0x80BD,0xF1E4,0x80C8,0xF180,0x80D3, +0xF11C,0x80DE,0xF0B9,0x80EA,0xF055,0x80F6,0xEFF1,0x8103,0xEF8D,0x8110,0xEF2A, +0x811D,0xEEC6,0x812A,0xEE62,0x8138,0xEDFF,0x8146,0xED9B,0x8154,0xED38,0x8163, +0xECD5,0x8172,0xEC71,0x8181,0xEC0E,0x8190,0xEBAB,0x81A0,0xEB47,0x81B0,0xEAE4, +0x81C1,0xEA81,0x81D1,0xEA1E,0x81E2,0xE9BB,0x81F4,0xE958,0x8205,0xE8F5,0x8217, +0xE892,0x822A,0xE82F,0x823C,0xE7CD,0x824F,0xE76A,0x8262,0xE707,0x8276,0xE6A5, +0x8289,0xE642,0x829D,0xE5E0,0x82B2,0xE57D,0x82C6,0xE51B,0x82DB,0xE4B9,0x82F1, +0xE457,0x8306,0xE3F4,0x831C,0xE392,0x8332,0xE330,0x8349,0xE2CF,0x8360,0xE26D, +0x8377,0xE20B,0x838E,0xE1A9,0x83A6,0xE148,0x83BE,0xE0E6,0x83D6,0xE085,0x83EF, +0xE023,0x8407,0xDFC2,0x8421,0xDF61,0x843A,0xDEFF,0x8454,0xDE9E,0x846E,0xDE3D, +0x8488,0xDDDC,0x84A3,0xDD7C,0x84BE,0xDD1B,0x84D9,0xDCBA,0x84F5,0xDC59,0x8511, +0xDBF9,0x852D,0xDB99,0x8549,0xDB38,0x8566,0xDAD8,0x8583,0xDA78,0x85A0,0xDA18, +0x85BE,0xD9B8,0x85DC,0xD958,0x85FA,0xD8F8,0x8619,0xD898,0x8637,0xD839,0x8656, +0xD7D9,0x8676,0xD77A,0x8696,0xD71B,0x86B6,0xD6BB,0x86D6,0xD65C,0x86F6,0xD5FD, +0x8717,0xD59E,0x8738,0xD53F,0x875A,0xD4E1,0x877B,0xD482,0x879D,0xD424,0x87C0, +0xD3C5,0x87E2,0xD367,0x8805,0xD309,0x8828,0xD2AB,0x884C,0xD24D,0x8870,0xD1EF, +0x8894,0xD191,0x88B8,0xD134,0x88DD,0xD0D6,0x8902,0xD079,0x8927,0xD01B,0x894C, +0xCFBE,0x8972,0xCF61,0x8998,0xCF04,0x89BE,0xCEA7,0x89E5,0xCE4B,0x8A0C,0xCDEE, +0x8A33,0xCD92,0x8A5A,0xCD35,0x8A82,0xCCD9,0x8AAA,0xCC7D,0x8AD3,0xCC21,0x8AFB, +0xCBC5,0x8B24,0xCB69,0x8B4D,0xCB0E,0x8B77,0xCAB2,0x8BA0,0xCA57,0x8BCA,0xC9FC, +0x8BF5,0xC9A1,0x8C1F,0xC946,0x8C4A,0xC8EB,0x8C75,0xC890,0x8CA1,0xC836,0x8CCC, +0xC7DB,0x8CF8,0xC781,0x8D24,0xC727,0x8D51,0xC6CD,0x8D7E,0xC673,0x8DAB,0xC619, +0x8DD8,0xC5C0,0x8E06,0xC566,0x8E34,0xC50D,0x8E62,0xC4B4,0x8E90,0xC45B,0x8EBF, +0xC402,0x8EEE,0xC3A9,0x8F1D,0xC351,0x8F4D,0xC2F8,0x8F7D,0xC2A0,0x8FAD,0xC248, +0x8FDD,0xC1F0,0x900E,0xC198,0x903E,0xC140,0x9070,0xC0E9,0x90A1,0xC091,0x90D3, +0xC03A,0x9105,0xBFE3,0x9137,0xBF8C,0x9169,0xBF35,0x919C,0xBEDF,0x91CF,0xBE88, +0x9202,0xBE32,0x9236,0xBDDC,0x926A,0xBD86,0x929E,0xBD30,0x92D2,0xBCDA,0x9307, +0xBC85,0x933C,0xBC2F,0x9371,0xBBDA,0x93A6,0xBB85,0x93DC,0xBB30,0x9412,0xBADC, +0x9448,0xBA87,0x947E,0xBA33,0x94B5,0xB9DF,0x94EC,0xB98B,0x9523,0xB937,0x955B, +0xB8E3,0x9592,0xB890,0x95CA,0xB83C,0x9603,0xB7E9,0x963B,0xB796,0x9674,0xB743, +0x96AD,0xB6F1,0x96E6,0xB69E,0x9720,0xB64C,0x9759,0xB5FA,0x9793,0xB5A8,0x97CE, +0xB556,0x9808,0xB505,0x9843,0xB4B3,0x987E,0xB462,0x98B9,0xB411,0x98F5,0xB3C0, +0x9930,0xB36F,0x996D,0xB31F,0x99A9,0xB2CF,0x99E5,0xB27F,0x9A22,0xB22F,0x9A5F, +0xB1DF,0x9A9C,0xB18F,0x9ADA,0xB140,0x9B17,0xB0F1,0x9B55,0xB0A2,0x9B94,0xB053, +0x9BD2,0xB005,0x9C11,0xAFB6,0x9C50,0xAF68,0x9C8F,0xAF1A,0x9CCE,0xAECC,0x9D0E, +0xAE7F,0x9D4E,0xAE31,0x9D8E,0xADE4,0x9DCE,0xAD97,0x9E0F,0xAD4A,0x9E50,0xACFD, +0x9E91,0xACB1,0x9ED2,0xAC65,0x9F14,0xAC19,0x9F56,0xABCD,0x9F98,0xAB81,0x9FDA, +0xAB36,0xA01C,0xAAEB,0xA05F,0xAAA0,0xA0A2,0xAA55,0xA0E5,0xAA0A,0xA129,0xA9C0, +0xA16C,0xA976,0xA1B0,0xA92C,0xA1F4,0xA8E2,0xA238,0xA899,0xA27D,0xA84F,0xA2C2, +0xA806,0xA307,0xA7BD,0xA34C,0xA774,0xA391,0xA72C,0xA3D7,0xA6E4,0xA41D,0xA69C, +0xA463,0xA654,0xA4A9,0xA60C,0xA4F0,0xA5C5,0xA537,0xA57E,0xA57E,0xA537,0xA5C5, +0xA4F0,0xA60C,0xA4A9,0xA654,0xA463,0xA69C,0xA41D,0xA6E4,0xA3D7,0xA72C,0xA391, +0xA774,0xA34C,0xA7BD,0xA307,0xA806,0xA2C2,0xA84F,0xA27D,0xA899,0xA238,0xA8E2, +0xA1F4,0xA92C,0xA1B0,0xA976,0xA16C,0xA9C0,0xA129,0xAA0A,0xA0E5,0xAA55,0xA0A2, +0xAAA0,0xA05F,0xAAEB,0xA01C,0xAB36,0x9FDA,0xAB81,0x9F98,0xABCD,0x9F56,0xAC19, +0x9F14,0xAC65,0x9ED2,0xACB1,0x9E91,0xACFD,0x9E50,0xAD4A,0x9E0F,0xAD97,0x9DCE, +0xADE4,0x9D8E,0xAE31,0x9D4E,0xAE7F,0x9D0E,0xAECC,0x9CCE,0xAF1A,0x9C8F,0xAF68, +0x9C50,0xAFB6,0x9C11,0xB005,0x9BD2,0xB053,0x9B94,0xB0A2,0x9B55,0xB0F1,0x9B17, +0xB140,0x9ADA,0xB18F,0x9A9C,0xB1DF,0x9A5F,0xB22F,0x9A22,0xB27F,0x99E5,0xB2CF, +0x99A9,0xB31F,0x996D,0xB36F,0x9930,0xB3C0,0x98F5,0xB411,0x98B9,0xB462,0x987E, +0xB4B3,0x9843,0xB505,0x9808,0xB556,0x97CE,0xB5A8,0x9793,0xB5FA,0x9759,0xB64C, +0x9720,0xB69E,0x96E6,0xB6F1,0x96AD,0xB743,0x9674,0xB796,0x963B,0xB7E9,0x9603, +0xB83C,0x95CA,0xB890,0x9592,0xB8E3,0x955B,0xB937,0x9523,0xB98B,0x94EC,0xB9DF, +0x94B5,0xBA33,0x947E,0xBA87,0x9448,0xBADC,0x9412,0xBB30,0x93DC,0xBB85,0x93A6, +0xBBDA,0x9371,0xBC2F,0x933C,0xBC85,0x9307,0xBCDA,0x92D2,0xBD30,0x929E,0xBD86, +0x926A,0xBDDC,0x9236,0xBE32,0x9202,0xBE88,0x91CF,0xBEDF,0x919C,0xBF35,0x9169, +0xBF8C,0x9137,0xBFE3,0x9105,0xC03A,0x90D3,0xC091,0x90A1,0xC0E9,0x9070,0xC140, +0x903E,0xC198,0x900E,0xC1F0,0x8FDD,0xC248,0x8FAD,0xC2A0,0x8F7D,0xC2F8,0x8F4D, +0xC351,0x8F1D,0xC3A9,0x8EEE,0xC402,0x8EBF,0xC45B,0x8E90,0xC4B4,0x8E62,0xC50D, +0x8E34,0xC566,0x8E06,0xC5C0,0x8DD8,0xC619,0x8DAB,0xC673,0x8D7E,0xC6CD,0x8D51, +0xC727,0x8D24,0xC781,0x8CF8,0xC7DB,0x8CCC,0xC836,0x8CA1,0xC890,0x8C75,0xC8EB, +0x8C4A,0xC946,0x8C1F,0xC9A1,0x8BF5,0xC9FC,0x8BCA,0xCA57,0x8BA0,0xCAB2,0x8B77, +0xCB0E,0x8B4D,0xCB69,0x8B24,0xCBC5,0x8AFB,0xCC21,0x8AD3,0xCC7D,0x8AAA,0xCCD9, +0x8A82,0xCD35,0x8A5A,0xCD92,0x8A33,0xCDEE,0x8A0C,0xCE4B,0x89E5,0xCEA7,0x89BE, +0xCF04,0x8998,0xCF61,0x8972,0xCFBE,0x894C,0xD01B,0x8927,0xD079,0x8902,0xD0D6, +0x88DD,0xD134,0x88B8,0xD191,0x8894,0xD1EF,0x8870,0xD24D,0x884C,0xD2AB,0x8828, +0xD309,0x8805,0xD367,0x87E2,0xD3C5,0x87C0,0xD424,0x879D,0xD482,0x877B,0xD4E1, +0x875A,0xD53F,0x8738,0xD59E,0x8717,0xD5FD,0x86F6,0xD65C,0x86D6,0xD6BB,0x86B6, +0xD71B,0x8696,0xD77A,0x8676,0xD7D9,0x8656,0xD839,0x8637,0xD898,0x8619,0xD8F8, +0x85FA,0xD958,0x85DC,0xD9B8,0x85BE,0xDA18,0x85A0,0xDA78,0x8583,0xDAD8,0x8566, +0xDB38,0x8549,0xDB99,0x852D,0xDBF9,0x8511,0xDC59,0x84F5,0xDCBA,0x84D9,0xDD1B, +0x84BE,0xDD7C,0x84A3,0xDDDC,0x8488,0xDE3D,0x846E,0xDE9E,0x8454,0xDEFF,0x843A, +0xDF61,0x8421,0xDFC2,0x8407,0xE023,0x83EF,0xE085,0x83D6,0xE0E6,0x83BE,0xE148, +0x83A6,0xE1A9,0x838E,0xE20B,0x8377,0xE26D,0x8360,0xE2CF,0x8349,0xE330,0x8332, +0xE392,0x831C,0xE3F4,0x8306,0xE457,0x82F1,0xE4B9,0x82DB,0xE51B,0x82C6,0xE57D, +0x82B2,0xE5E0,0x829D,0xE642,0x8289,0xE6A5,0x8276,0xE707,0x8262,0xE76A,0x824F, +0xE7CD,0x823C,0xE82F,0x822A,0xE892,0x8217,0xE8F5,0x8205,0xE958,0x81F4,0xE9BB, +0x81E2,0xEA1E,0x81D1,0xEA81,0x81C1,0xEAE4,0x81B0,0xEB47,0x81A0,0xEBAB,0x8190, +0xEC0E,0x8181,0xEC71,0x8172,0xECD5,0x8163,0xED38,0x8154,0xED9B,0x8146,0xEDFF, +0x8138,0xEE62,0x812A,0xEEC6,0x811D,0xEF2A,0x8110,0xEF8D,0x8103,0xEFF1,0x80F6, +0xF055,0x80EA,0xF0B9,0x80DE,0xF11C,0x80D3,0xF180,0x80C8,0xF1E4,0x80BD,0xF248, +0x80B2,0xF2AC,0x80A8,0xF310,0x809E,0xF374,0x8094,0xF3D8,0x808B,0xF43C,0x8082, +0xF4A0,0x8079,0xF505,0x8070,0xF569,0x8068,0xF5CD,0x8060,0xF631,0x8059,0xF695, +0x8052,0xF6FA,0x804B,0xF75E,0x8044,0xF7C2,0x803E,0xF827,0x8038,0xF88B,0x8032, +0xF8EF,0x802D,0xF954,0x8027,0xF9B8,0x8023,0xFA1D,0x801E,0xFA81,0x801A,0xFAE5, +0x8016,0xFB4A,0x8013,0xFBAE,0x800F,0xFC13,0x800C,0xFC77,0x800A,0xFCDC,0x8008, +0xFD40,0x8006,0xFDA5,0x8004,0xFE09,0x8002,0xFE6E,0x8001,0xFED2,0x8001,0xFF37, +0x8000,0xFF9B,0x7FFF,0x0000,0x7FFE,0xFE6E,0x7FF6,0xFCDC,0x7FEA,0xFB4A,0x7FD9, +0xF9B8,0x7FC2,0xF827,0x7FA7,0xF695,0x7F87,0xF505,0x7F62,0xF374,0x7F38,0xF1E4, +0x7F0A,0xF055,0x7ED6,0xEEC6,0x7E9D,0xED38,0x7E60,0xEBAB,0x7E1E,0xEA1E,0x7DD6, +0xE892,0x7D8A,0xE707,0x7D3A,0xE57D,0x7CE4,0xE3F4,0x7C89,0xE26D,0x7C2A,0xE0E6, +0x7BC6,0xDF61,0x7B5D,0xDDDC,0x7AEF,0xDC59,0x7A7D,0xDAD8,0x7A06,0xD958,0x798A, +0xD7D9,0x790A,0xD65C,0x7885,0xD4E1,0x77FB,0xD367,0x776C,0xD1EF,0x76D9,0xD079, +0x7642,0xCF04,0x75A6,0xCD92,0x7505,0xCC21,0x7460,0xCAB2,0x73B6,0xC946,0x7308, +0xC7DB,0x7255,0xC673,0x719E,0xC50D,0x70E3,0xC3A9,0x7023,0xC248,0x6F5F,0xC0E9, +0x6E97,0xBF8C,0x6DCA,0xBE32,0x6CF9,0xBCDA,0x6C24,0xBB85,0x6B4B,0xBA33,0x6A6E, +0xB8E3,0x698C,0xB796,0x68A7,0xB64C,0x67BD,0xB505,0x66D0,0xB3C0,0x65DE,0xB27F, +0x64E9,0xB140,0x63EF,0xB005,0x62F2,0xAECC,0x61F1,0xAD97,0x60EC,0xAC65,0x5FE4, +0xAB36,0x5ED7,0xAA0A,0x5DC8,0xA8E2,0x5CB4,0xA7BD,0x5B9D,0xA69C,0x5A82,0xA57E, +0x5964,0xA463,0x5843,0xA34C,0x571E,0xA238,0x55F6,0xA129,0x54CA,0xA01C,0x539B, +0x9F14,0x5269,0x9E0F,0x5134,0x9D0E,0x4FFB,0x9C11,0x4EC0,0x9B17,0x4D81,0x9A22, +0x4C40,0x9930,0x4AFB,0x9843,0x49B4,0x9759,0x486A,0x9674,0x471D,0x9592,0x45CD, +0x94B5,0x447B,0x93DC,0x4326,0x9307,0x41CE,0x9236,0x4074,0x9169,0x3F17,0x90A1, +0x3DB8,0x8FDD,0x3C57,0x8F1D,0x3AF3,0x8E62,0x398D,0x8DAB,0x3825,0x8CF8,0x36BA, +0x8C4A,0x354E,0x8BA0,0x33DF,0x8AFB,0x326E,0x8A5A,0x30FC,0x89BE,0x2F87,0x8927, +0x2E11,0x8894,0x2C99,0x8805,0x2B1F,0x877B,0x29A4,0x86F6,0x2827,0x8676,0x26A8, +0x85FA,0x2528,0x8583,0x23A7,0x8511,0x2224,0x84A3,0x209F,0x843A,0x1F1A,0x83D6, +0x1D93,0x8377,0x1C0C,0x831C,0x1A83,0x82C6,0x18F9,0x8276,0x176E,0x822A,0x15E2, +0x81E2,0x1455,0x81A0,0x12C8,0x8163,0x113A,0x812A,0x0FAB,0x80F6,0x0E1C,0x80C8, +0x0C8C,0x809E,0x0AFB,0x8079,0x096B,0x8059,0x07D9,0x803E,0x0648,0x8027,0x04B6, +0x8016,0x0324,0x800A,0x0192,0x8002,0x0000,0x8000,0xFE6E,0x8002,0xFCDC,0x800A, +0xFB4A,0x8016,0xF9B8,0x8027,0xF827,0x803E,0xF695,0x8059,0xF505,0x8079,0xF374, +0x809E,0xF1E4,0x80C8,0xF055,0x80F6,0xEEC6,0x812A,0xED38,0x8163,0xEBAB,0x81A0, +0xEA1E,0x81E2,0xE892,0x822A,0xE707,0x8276,0xE57D,0x82C6,0xE3F4,0x831C,0xE26D, +0x8377,0xE0E6,0x83D6,0xDF61,0x843A,0xDDDC,0x84A3,0xDC59,0x8511,0xDAD8,0x8583, +0xD958,0x85FA,0xD7D9,0x8676,0xD65C,0x86F6,0xD4E1,0x877B,0xD367,0x8805,0xD1EF, +0x8894,0xD079,0x8927,0xCF04,0x89BE,0xCD92,0x8A5A,0xCC21,0x8AFB,0xCAB2,0x8BA0, +0xC946,0x8C4A,0xC7DB,0x8CF8,0xC673,0x8DAB,0xC50D,0x8E62,0xC3A9,0x8F1D,0xC248, +0x8FDD,0xC0E9,0x90A1,0xBF8C,0x9169,0xBE32,0x9236,0xBCDA,0x9307,0xBB85,0x93DC, +0xBA33,0x94B5,0xB8E3,0x9592,0xB796,0x9674,0xB64C,0x9759,0xB505,0x9843,0xB3C0, +0x9930,0xB27F,0x9A22,0xB140,0x9B17,0xB005,0x9C11,0xAECC,0x9D0E,0xAD97,0x9E0F, +0xAC65,0x9F14,0xAB36,0xA01C,0xAA0A,0xA129,0xA8E2,0xA238,0xA7BD,0xA34C,0xA69C, +0xA463,0xA57E,0xA57E,0xA463,0xA69C,0xA34C,0xA7BD,0xA238,0xA8E2,0xA129,0xAA0A, +0xA01C,0xAB36,0x9F14,0xAC65,0x9E0F,0xAD97,0x9D0E,0xAECC,0x9C11,0xB005,0x9B17, +0xB140,0x9A22,0xB27F,0x9930,0xB3C0,0x9843,0xB505,0x9759,0xB64C,0x9674,0xB796, +0x9592,0xB8E3,0x94B5,0xBA33,0x93DC,0xBB85,0x9307,0xBCDA,0x9236,0xBE32,0x9169, +0xBF8C,0x90A1,0xC0E9,0x8FDD,0xC248,0x8F1D,0xC3A9,0x8E62,0xC50D,0x8DAB,0xC673, +0x8CF8,0xC7DB,0x8C4A,0xC946,0x8BA0,0xCAB2,0x8AFB,0xCC21,0x8A5A,0xCD92,0x89BE, +0xCF04,0x8927,0xD079,0x8894,0xD1EF,0x8805,0xD367,0x877B,0xD4E1,0x86F6,0xD65C, +0x8676,0xD7D9,0x85FA,0xD958,0x8583,0xDAD8,0x8511,0xDC59,0x84A3,0xDDDC,0x843A, +0xDF61,0x83D6,0xE0E6,0x8377,0xE26D,0x831C,0xE3F4,0x82C6,0xE57D,0x8276,0xE707, +0x822A,0xE892,0x81E2,0xEA1E,0x81A0,0xEBAB,0x8163,0xED38,0x812A,0xEEC6,0x80F6, +0xF055,0x80C8,0xF1E4,0x809E,0xF374,0x8079,0xF505,0x8059,0xF695,0x803E,0xF827, +0x8027,0xF9B8,0x8016,0xFB4A,0x800A,0xFCDC,0x8002,0xFE6E,0x7FFF,0x0000,0x7FD9, +0xF9B8,0x7F62,0xF374,0x7E9D,0xED38,0x7D8A,0xE707,0x7C2A,0xE0E6,0x7A7D,0xDAD8, +0x7885,0xD4E1,0x7642,0xCF04,0x73B6,0xC946,0x70E3,0xC3A9,0x6DCA,0xBE32,0x6A6E, +0xB8E3,0x66D0,0xB3C0,0x62F2,0xAECC,0x5ED7,0xAA0A,0x5A82,0xA57E,0x55F6,0xA129, +0x5134,0x9D0E,0x4C40,0x9930,0x471D,0x9592,0x41CE,0x9236,0x3C57,0x8F1D,0x36BA, +0x8C4A,0x30FC,0x89BE,0x2B1F,0x877B,0x2528,0x8583,0x1F1A,0x83D6,0x18F9,0x8276, +0x12C8,0x8163,0x0C8C,0x809E,0x0648,0x8027,0x0000,0x8000,0xF9B8,0x8027,0xF374, +0x809E,0xED38,0x8163,0xE707,0x8276,0xE0E6,0x83D6,0xDAD8,0x8583,0xD4E1,0x877B, +0xCF04,0x89BE,0xC946,0x8C4A,0xC3A9,0x8F1D,0xBE32,0x9236,0xB8E3,0x9592,0xB3C0, +0x9930,0xAECC,0x9D0E,0xAA0A,0xA129,0xA57E,0xA57E,0xA129,0xAA0A,0x9D0E,0xAECC, +0x9930,0xB3C0,0x9592,0xB8E3,0x9236,0xBE32,0x8F1D,0xC3A9,0x8C4A,0xC946,0x89BE, +0xCF04,0x877B,0xD4E1,0x8583,0xDAD8,0x83D6,0xE0E6,0x8276,0xE707,0x8163,0xED38, +0x809E,0xF374,0x8027,0xF9B8,0x7FFF,0x0000,0x7D8A,0xE707,0x7642,0xCF04,0x6A6E, +0xB8E3,0x5A82,0xA57E,0x471D,0x9592,0x30FC,0x89BE,0x18F9,0x8276,0x0000,0x8000, +0xE707,0x8276,0xCF04,0x89BE,0xB8E3,0x9592,0xA57E,0xA57E,0x9592,0xB8E3,0x89BE, +0xCF04,0x8276,0xE707,0x7FFF,0x0000,0x5A82,0xA57E,0x0000,0x8000,0xA57E,0xA57E,}; + +q15_t rearranged_twiddle_stride3_4096_q15[2728]={ +0x7FFF,0x0000,0x7FFF,0xFF69,0x7FFF,0xFED2,0x7FFD,0xFE3C,0x7FFA,0xFDA5,0x7FF7, +0xFD0E,0x7FF4,0xFC77,0x7FEF,0xFBE1,0x7FEA,0xFB4A,0x7FE4,0xFAB3,0x7FDD,0xFA1D, +0x7FD6,0xF986,0x7FCE,0xF8EF,0x7FC5,0xF859,0x7FBC,0xF7C2,0x7FB2,0xF72C,0x7FA7, +0xF695,0x7F9C,0xF5FF,0x7F90,0xF569,0x7F83,0xF4D3,0x7F75,0xF43C,0x7F67,0xF3A6, +0x7F58,0xF310,0x7F49,0xF27A,0x7F38,0xF1E4,0x7F27,0xF14E,0x7F16,0xF0B9,0x7F03, +0xF023,0x7EF0,0xEF8D,0x7EDD,0xEEF8,0x7EC8,0xEE62,0x7EB3,0xEDCD,0x7E9D,0xED38, +0x7E87,0xECA3,0x7E70,0xEC0E,0x7E58,0xEB79,0x7E3F,0xEAE4,0x7E26,0xEA4F,0x7E0C, +0xE9BB,0x7DF2,0xE926,0x7DD6,0xE892,0x7DBA,0xE7FE,0x7D9E,0xE76A,0x7D81,0xE6D6, +0x7D63,0xE642,0x7D44,0xE5AF,0x7D25,0xE51B,0x7D05,0xE488,0x7CE4,0xE3F4,0x7CC2, +0xE361,0x7CA0,0xE2CF,0x7C7E,0xE23C,0x7C5A,0xE1A9,0x7C36,0xE117,0x7C11,0xE085, +0x7BEC,0xDFF2,0x7BC6,0xDF61,0x7B9F,0xDECF,0x7B78,0xDE3D,0x7B50,0xDDAC,0x7B27, +0xDD1B,0x7AFD,0xDC8A,0x7AD3,0xDBF9,0x7AA8,0xDB68,0x7A7D,0xDAD8,0x7A51,0xDA48, +0x7A24,0xD9B8,0x79F7,0xD928,0x79C9,0xD898,0x799A,0xD809,0x796A,0xD77A,0x793A, +0xD6EB,0x790A,0xD65C,0x78D8,0xD5CE,0x78A6,0xD53F,0x7874,0xD4B1,0x7840,0xD424, +0x780C,0xD396,0x77D8,0xD309,0x77A2,0xD27C,0x776C,0xD1EF,0x7736,0xD162,0x76FE, +0xD0D6,0x76C7,0xD04A,0x768E,0xCFBE,0x7655,0xCF33,0x761B,0xCEA7,0x75E1,0xCE1C, +0x75A6,0xCD92,0x756A,0xCD07,0x752D,0xCC7D,0x74F0,0xCBF3,0x74B3,0xCB69,0x7475, +0xCAE0,0x7436,0xCA57,0x73F6,0xC9CE,0x73B6,0xC946,0x7375,0xC8BE,0x7334,0xC836, +0x72F2,0xC7AE,0x72AF,0xC727,0x726C,0xC6A0,0x7228,0xC619,0x71E3,0xC593,0x719E, +0xC50D,0x7158,0xC487,0x7112,0xC402,0x70CB,0xC37D,0x7083,0xC2F8,0x703B,0xC274, +0x6FF2,0xC1F0,0x6FA9,0xC16C,0x6F5F,0xC0E9,0x6F14,0xC066,0x6EC9,0xBFE3,0x6E7D, +0xBF61,0x6E31,0xBEDF,0x6DE4,0xBE5D,0x6D96,0xBDDC,0x6D48,0xBD5B,0x6CF9,0xBCDA, +0x6CAA,0xBC5A,0x6C5A,0xBBDA,0x6C09,0xBB5B,0x6BB8,0xBADC,0x6B66,0xBA5D,0x6B14, +0xB9DF,0x6AC1,0xB961,0x6A6E,0xB8E3,0x6A1A,0xB866,0x69C5,0xB7E9,0x6970,0xB76D, +0x691A,0xB6F1,0x68C4,0xB675,0x686D,0xB5FA,0x6815,0xB57F,0x67BD,0xB505,0x6764, +0xB48B,0x670B,0xB411,0x66B2,0xB398,0x6657,0xB31F,0x65FC,0xB2A7,0x65A1,0xB22F, +0x6545,0xB1B7,0x64E9,0xB140,0x648B,0xB0C9,0x642E,0xB053,0x63D0,0xAFDD,0x6371, +0xAF68,0x6312,0xAEF3,0x62B2,0xAE7F,0x6252,0xAE0B,0x61F1,0xAD97,0x6190,0xAD24, +0x612E,0xACB1,0x60CB,0xAC3F,0x6068,0xABCD,0x6005,0xAB5C,0x5FA1,0xAAEB,0x5F3C, +0xAA7A,0x5ED7,0xAA0A,0x5E72,0xA99B,0x5E0C,0xA92C,0x5DA5,0xA8BD,0x5D3E,0xA84F, +0x5CD7,0xA7E2,0x5C6F,0xA774,0x5C06,0xA708,0x5B9D,0xA69C,0x5B34,0xA630,0x5AC9, +0xA5C5,0x5A5F,0xA55A,0x59F4,0xA4F0,0x5988,0xA486,0x591C,0xA41D,0x58B0,0xA3B4, +0x5843,0xA34C,0x57D5,0xA2E4,0x5767,0xA27D,0x56F9,0xA216,0x568A,0xA1B0,0x561B, +0xA14A,0x55AB,0xA0E5,0x553B,0xA080,0x54CA,0xA01C,0x5459,0x9FB9,0x53E7,0x9F56, +0x5375,0x9EF3,0x5303,0x9E91,0x5290,0x9E2F,0x521C,0x9DCE,0x51A8,0x9D6E,0x5134, +0x9D0E,0x50BF,0x9CAF,0x504A,0x9C50,0x4FD4,0x9BF1,0x4F5E,0x9B94,0x4EE8,0x9B36, +0x4E71,0x9ADA,0x4DF9,0x9A7E,0x4D81,0x9A22,0x4D09,0x99C7,0x4C91,0x996D,0x4C17, +0x9913,0x4B9E,0x98B9,0x4B24,0x9860,0x4AAA,0x9808,0x4A2F,0x97B0,0x49B4,0x9759, +0x4939,0x9703,0x48BD,0x96AD,0x4840,0x9657,0x47C4,0x9603,0x4747,0x95AE,0x46C9, +0x955B,0x464B,0x9508,0x45CD,0x94B5,0x454F,0x9463,0x44D0,0x9412,0x4450,0x93C1, +0x43D1,0x9371,0x4351,0x9321,0x42D0,0x92D2,0x424F,0x9284,0x41CE,0x9236,0x414D, +0x91E9,0x40CB,0x919C,0x4048,0x9150,0x3FC6,0x9105,0x3F43,0x90BA,0x3EC0,0x9070, +0x3E3C,0x9026,0x3DB8,0x8FDD,0x3D34,0x8F95,0x3CAF,0x8F4D,0x3C2A,0x8F06,0x3BA5, +0x8EBF,0x3B20,0x8E79,0x3A9A,0x8E34,0x3A13,0x8DEF,0x398D,0x8DAB,0x3906,0x8D67, +0x387F,0x8D24,0x37F7,0x8CE2,0x3770,0x8CA1,0x36E8,0x8C60,0x365F,0x8C1F,0x35D7, +0x8BDF,0x354E,0x8BA0,0x34C4,0x8B62,0x343B,0x8B24,0x33B1,0x8AE7,0x3327,0x8AAA, +0x329D,0x8A6E,0x3212,0x8A33,0x3187,0x89F8,0x30FC,0x89BE,0x3070,0x8985,0x2FE5, +0x894C,0x2F59,0x8914,0x2ECC,0x88DD,0x2E40,0x88A6,0x2DB3,0x8870,0x2D26,0x883A, +0x2C99,0x8805,0x2C0C,0x87D1,0x2B7E,0x879D,0x2AF0,0x876B,0x2A62,0x8738,0x29D3, +0x8707,0x2945,0x86D6,0x28B6,0x86A5,0x2827,0x8676,0x2797,0x8647,0x2708,0x8619, +0x2678,0x85EB,0x25E8,0x85BE,0x2558,0x8592,0x24C8,0x8566,0x2437,0x853B,0x23A7, +0x8511,0x2316,0x84E7,0x2284,0x84BE,0x21F3,0x8496,0x2162,0x846E,0x20D0,0x8447, +0x203E,0x8421,0x1FAC,0x83FB,0x1F1A,0x83D6,0x1E88,0x83B2,0x1DF5,0x838E,0x1D62, +0x836B,0x1CD0,0x8349,0x1C3D,0x8327,0x1BA9,0x8306,0x1B16,0x82E6,0x1A83,0x82C6, +0x19EF,0x82A8,0x195B,0x8289,0x18C7,0x826C,0x1833,0x824F,0x179F,0x8233,0x170B, +0x8217,0x1677,0x81FD,0x15E2,0x81E2,0x154D,0x81C9,0x14B9,0x81B0,0x1424,0x8198, +0x138F,0x8181,0x12FA,0x816A,0x1265,0x8154,0x11CF,0x813F,0x113A,0x812A,0x10A4, +0x8116,0x100F,0x8103,0x0F79,0x80F0,0x0EE4,0x80DE,0x0E4E,0x80CD,0x0DB8,0x80BD, +0x0D22,0x80AD,0x0C8C,0x809E,0x0BF6,0x808F,0x0B60,0x8082,0x0AC9,0x8075,0x0A33, +0x8068,0x099D,0x805D,0x0906,0x8052,0x0870,0x8047,0x07D9,0x803E,0x0743,0x8035, +0x06AC,0x802D,0x0616,0x8025,0x057F,0x801E,0x04E8,0x8018,0x0452,0x8013,0x03BB, +0x800E,0x0324,0x800A,0x028D,0x8007,0x01F7,0x8004,0x0160,0x8002,0x00C9,0x8001, +0x0032,0x8000,0xFF9B,0x8000,0xFF05,0x8001,0xFE6E,0x8002,0xFDD7,0x8005,0xFD40, +0x8008,0xFCAA,0x800B,0xFC13,0x800F,0xFB7C,0x8014,0xFAE5,0x801A,0xFA4F,0x8020, +0xF9B8,0x8027,0xF922,0x802F,0xF88B,0x8038,0xF7F4,0x8041,0xF75E,0x804B,0xF6C8, +0x8055,0xF631,0x8060,0xF59B,0x806C,0xF505,0x8079,0xF46E,0x8086,0xF3D8,0x8094, +0xF342,0x80A3,0xF2AC,0x80B2,0xF216,0x80C2,0xF180,0x80D3,0xF0EB,0x80E4,0xF055, +0x80F6,0xEFBF,0x8109,0xEF2A,0x811D,0xEE94,0x8131,0xEDFF,0x8146,0xED6A,0x815B, +0xECD5,0x8172,0xEC3F,0x8188,0xEBAB,0x81A0,0xEB16,0x81B8,0xEA81,0x81D1,0xE9EC, +0x81EB,0xE958,0x8205,0xE8C4,0x8220,0xE82F,0x823C,0xE79B,0x8259,0xE707,0x8276, +0xE673,0x8293,0xE5E0,0x82B2,0xE54C,0x82D1,0xE4B9,0x82F1,0xE426,0x8311,0xE392, +0x8332,0xE2FF,0x8354,0xE26D,0x8377,0xE1DA,0x839A,0xE148,0x83BE,0xE0B5,0x83E2, +0xE023,0x8407,0xDF91,0x842D,0xDEFF,0x8454,0xDE6E,0x847B,0xDDDC,0x84A3,0xDD4B, +0x84CC,0xDCBA,0x84F5,0xDC29,0x851F,0xDB99,0x8549,0xDB08,0x8574,0xDA78,0x85A0, +0xD9E8,0x85CD,0xD958,0x85FA,0xD8C8,0x8628,0xD839,0x8656,0xD7AA,0x8686,0xD71B, +0x86B6,0xD68C,0x86E6,0xD5FD,0x8717,0xD56F,0x8749,0xD4E1,0x877B,0xD453,0x87AF, +0xD3C5,0x87E2,0xD338,0x8817,0xD2AB,0x884C,0xD21E,0x8882,0xD191,0x88B8,0xD105, +0x88EF,0xD079,0x8927,0xCFED,0x895F,0xCF61,0x8998,0xCED6,0x89D2,0xCE4B,0x8A0C, +0xCDC0,0x8A47,0xCD35,0x8A82,0xCCAB,0x8ABE,0xCC21,0x8AFB,0xCB97,0x8B39,0xCB0E, +0x8B77,0xCA85,0x8BB5,0xC9FC,0x8BF5,0xC973,0x8C35,0xC8EB,0x8C75,0xC863,0x8CB6, +0xC7DB,0x8CF8,0xC754,0x8D3B,0xC6CD,0x8D7E,0xC646,0x8DC1,0xC5C0,0x8E06,0xC53A, +0x8E4B,0xC4B4,0x8E90,0xC42E,0x8ED6,0xC3A9,0x8F1D,0xC324,0x8F65,0xC2A0,0x8FAD, +0xC21C,0x8FF5,0xC198,0x903E,0xC114,0x9088,0xC091,0x90D3,0xC00F,0x911E,0xBF8C, +0x9169,0xBF0A,0x91B6,0xBE88,0x9202,0xBE07,0x9250,0xBD86,0x929E,0xBD05,0x92EC, +0xBC85,0x933C,0xBC05,0x938B,0xBB85,0x93DC,0xBB06,0x942D,0xBA87,0x947E,0xBA09, +0x94D0,0xB98B,0x9523,0xB90D,0x9577,0xB890,0x95CA,0xB813,0x961F,0xB796,0x9674, +0xB71A,0x96C9,0xB69E,0x9720,0xB623,0x9776,0xB5A8,0x97CE,0xB52D,0x9826,0xB4B3, +0x987E,0xB439,0x98D7,0xB3C0,0x9930,0xB347,0x998B,0xB2CF,0x99E5,0xB257,0x9A40, +0xB1DF,0x9A9C,0xB168,0x9AF9,0xB0F1,0x9B55,0xB07B,0x9BB3,0xB005,0x9C11,0xAF8F, +0x9C6F,0xAF1A,0x9CCE,0xAEA5,0x9D2E,0xAE31,0x9D8E,0xADBD,0x9DEF,0xAD4A,0x9E50, +0xACD7,0x9EB2,0xAC65,0x9F14,0xABF3,0x9F77,0xAB81,0x9FDA,0xAB10,0xA03E,0xAAA0, +0xA0A2,0xAA30,0xA107,0xA9C0,0xA16C,0xA951,0xA1D2,0xA8E2,0xA238,0xA874,0xA29F, +0xA806,0xA307,0xA799,0xA36F,0xA72C,0xA3D7,0xA6C0,0xA440,0xA654,0xA4A9,0xA5E8, +0xA513,0xA57E,0xA57E,0xA513,0xA5E8,0xA4A9,0xA654,0xA440,0xA6C0,0xA3D7,0xA72C, +0xA36F,0xA799,0xA307,0xA806,0xA29F,0xA874,0xA238,0xA8E2,0xA1D2,0xA951,0xA16C, +0xA9C0,0xA107,0xAA30,0xA0A2,0xAAA0,0xA03E,0xAB10,0x9FDA,0xAB81,0x9F77,0xABF3, +0x9F14,0xAC65,0x9EB2,0xACD7,0x9E50,0xAD4A,0x9DEF,0xADBD,0x9D8E,0xAE31,0x9D2E, +0xAEA5,0x9CCE,0xAF1A,0x9C6F,0xAF8F,0x9C11,0xB005,0x9BB3,0xB07B,0x9B55,0xB0F1, +0x9AF9,0xB168,0x9A9C,0xB1DF,0x9A40,0xB257,0x99E5,0xB2CF,0x998B,0xB347,0x9930, +0xB3C0,0x98D7,0xB439,0x987E,0xB4B3,0x9826,0xB52D,0x97CE,0xB5A8,0x9776,0xB623, +0x9720,0xB69E,0x96C9,0xB71A,0x9674,0xB796,0x961F,0xB813,0x95CA,0xB890,0x9577, +0xB90D,0x9523,0xB98B,0x94D0,0xBA09,0x947E,0xBA87,0x942D,0xBB06,0x93DC,0xBB85, +0x938B,0xBC05,0x933C,0xBC85,0x92EC,0xBD05,0x929E,0xBD86,0x9250,0xBE07,0x9202, +0xBE88,0x91B6,0xBF0A,0x9169,0xBF8C,0x911E,0xC00F,0x90D3,0xC091,0x9088,0xC114, +0x903E,0xC198,0x8FF5,0xC21C,0x8FAD,0xC2A0,0x8F65,0xC324,0x8F1D,0xC3A9,0x8ED6, +0xC42E,0x8E90,0xC4B4,0x8E4B,0xC53A,0x8E06,0xC5C0,0x8DC1,0xC646,0x8D7E,0xC6CD, +0x8D3B,0xC754,0x8CF8,0xC7DB,0x8CB6,0xC863,0x8C75,0xC8EB,0x8C35,0xC973,0x8BF5, +0xC9FC,0x8BB5,0xCA85,0x8B77,0xCB0E,0x8B39,0xCB97,0x8AFB,0xCC21,0x8ABE,0xCCAB, +0x8A82,0xCD35,0x8A47,0xCDC0,0x8A0C,0xCE4B,0x89D2,0xCED6,0x8998,0xCF61,0x895F, +0xCFED,0x8927,0xD079,0x88EF,0xD105,0x88B8,0xD191,0x8882,0xD21E,0x884C,0xD2AB, +0x8817,0xD338,0x87E2,0xD3C5,0x87AF,0xD453,0x877B,0xD4E1,0x8749,0xD56F,0x8717, +0xD5FD,0x86E6,0xD68C,0x86B6,0xD71B,0x8686,0xD7AA,0x8656,0xD839,0x8628,0xD8C8, +0x85FA,0xD958,0x85CD,0xD9E8,0x85A0,0xDA78,0x8574,0xDB08,0x8549,0xDB99,0x851F, +0xDC29,0x84F5,0xDCBA,0x84CC,0xDD4B,0x84A3,0xDDDC,0x847B,0xDE6E,0x8454,0xDEFF, +0x842D,0xDF91,0x8407,0xE023,0x83E2,0xE0B5,0x83BE,0xE148,0x839A,0xE1DA,0x8377, +0xE26D,0x8354,0xE2FF,0x8332,0xE392,0x8311,0xE426,0x82F1,0xE4B9,0x82D1,0xE54C, +0x82B2,0xE5E0,0x8293,0xE673,0x8276,0xE707,0x8259,0xE79B,0x823C,0xE82F,0x8220, +0xE8C4,0x8205,0xE958,0x81EB,0xE9EC,0x81D1,0xEA81,0x81B8,0xEB16,0x81A0,0xEBAB, +0x8188,0xEC3F,0x8172,0xECD5,0x815B,0xED6A,0x8146,0xEDFF,0x8131,0xEE94,0x811D, +0xEF2A,0x8109,0xEFBF,0x80F6,0xF055,0x80E4,0xF0EB,0x80D3,0xF180,0x80C2,0xF216, +0x80B2,0xF2AC,0x80A3,0xF342,0x8094,0xF3D8,0x8086,0xF46E,0x8079,0xF505,0x806C, +0xF59B,0x8060,0xF631,0x8055,0xF6C8,0x804B,0xF75E,0x8041,0xF7F4,0x8038,0xF88B, +0x802F,0xF922,0x8027,0xF9B8,0x8020,0xFA4F,0x801A,0xFAE5,0x8014,0xFB7C,0x800F, +0xFC13,0x800B,0xFCAA,0x8008,0xFD40,0x8005,0xFDD7,0x8002,0xFE6E,0x8001,0xFF05, +0x8000,0xFF9B,0x8000,0x0032,0x8001,0x00C9,0x8002,0x0160,0x8004,0x01F7,0x8007, +0x028D,0x800A,0x0324,0x800E,0x03BB,0x8013,0x0452,0x8018,0x04E8,0x801E,0x057F, +0x8025,0x0616,0x802D,0x06AC,0x8035,0x0743,0x803E,0x07D9,0x8047,0x0870,0x8052, +0x0906,0x805D,0x099D,0x8068,0x0A33,0x8075,0x0AC9,0x8082,0x0B60,0x808F,0x0BF6, +0x809E,0x0C8C,0x80AD,0x0D22,0x80BD,0x0DB8,0x80CD,0x0E4E,0x80DE,0x0EE4,0x80F0, +0x0F79,0x8103,0x100F,0x8116,0x10A4,0x812A,0x113A,0x813F,0x11CF,0x8154,0x1265, +0x816A,0x12FA,0x8181,0x138F,0x8198,0x1424,0x81B0,0x14B9,0x81C9,0x154D,0x81E2, +0x15E2,0x81FD,0x1677,0x8217,0x170B,0x8233,0x179F,0x824F,0x1833,0x826C,0x18C7, +0x8289,0x195B,0x82A8,0x19EF,0x82C6,0x1A83,0x82E6,0x1B16,0x8306,0x1BA9,0x8327, +0x1C3D,0x8349,0x1CD0,0x836B,0x1D62,0x838E,0x1DF5,0x83B2,0x1E88,0x83D6,0x1F1A, +0x83FB,0x1FAC,0x8421,0x203E,0x8447,0x20D0,0x846E,0x2162,0x8496,0x21F3,0x84BE, +0x2284,0x84E7,0x2316,0x8511,0x23A7,0x853B,0x2437,0x8566,0x24C8,0x8592,0x2558, +0x85BE,0x25E8,0x85EB,0x2678,0x8619,0x2708,0x8647,0x2797,0x8676,0x2827,0x86A5, +0x28B6,0x86D6,0x2945,0x8707,0x29D3,0x8738,0x2A62,0x876B,0x2AF0,0x879D,0x2B7E, +0x87D1,0x2C0C,0x8805,0x2C99,0x883A,0x2D26,0x8870,0x2DB3,0x88A6,0x2E40,0x88DD, +0x2ECC,0x8914,0x2F59,0x894C,0x2FE5,0x8985,0x3070,0x89BE,0x30FC,0x89F8,0x3187, +0x8A33,0x3212,0x8A6E,0x329D,0x8AAA,0x3327,0x8AE7,0x33B1,0x8B24,0x343B,0x8B62, +0x34C4,0x8BA0,0x354E,0x8BDF,0x35D7,0x8C1F,0x365F,0x8C60,0x36E8,0x8CA1,0x3770, +0x8CE2,0x37F7,0x8D24,0x387F,0x8D67,0x3906,0x8DAB,0x398D,0x8DEF,0x3A13,0x8E34, +0x3A9A,0x8E79,0x3B20,0x8EBF,0x3BA5,0x8F06,0x3C2A,0x8F4D,0x3CAF,0x8F95,0x3D34, +0x8FDD,0x3DB8,0x9026,0x3E3C,0x9070,0x3EC0,0x90BA,0x3F43,0x9105,0x3FC6,0x9150, +0x4048,0x919C,0x40CB,0x91E9,0x414D,0x9236,0x41CE,0x9284,0x424F,0x92D2,0x42D0, +0x9321,0x4351,0x9371,0x43D1,0x93C1,0x4450,0x9412,0x44D0,0x9463,0x454F,0x94B5, +0x45CD,0x9508,0x464B,0x955B,0x46C9,0x95AE,0x4747,0x9603,0x47C4,0x9657,0x4840, +0x96AD,0x48BD,0x9703,0x4939,0x9759,0x49B4,0x97B0,0x4A2F,0x9808,0x4AAA,0x9860, +0x4B24,0x98B9,0x4B9E,0x9913,0x4C17,0x996D,0x4C91,0x99C7,0x4D09,0x9A22,0x4D81, +0x9A7E,0x4DF9,0x9ADA,0x4E71,0x9B36,0x4EE8,0x9B94,0x4F5E,0x9BF1,0x4FD4,0x9C50, +0x504A,0x9CAF,0x50BF,0x9D0E,0x5134,0x9D6E,0x51A8,0x9DCE,0x521C,0x9E2F,0x5290, +0x9E91,0x5303,0x9EF3,0x5375,0x9F56,0x53E7,0x9FB9,0x5459,0xA01C,0x54CA,0xA080, +0x553B,0xA0E5,0x55AB,0xA14A,0x561B,0xA1B0,0x568A,0xA216,0x56F9,0xA27D,0x5767, +0xA2E4,0x57D5,0xA34C,0x5843,0xA3B4,0x58B0,0xA41D,0x591C,0xA486,0x5988,0xA4F0, +0x59F4,0xA55A,0x5A5F,0xA5C5,0x5AC9,0xA630,0x5B34,0xA69C,0x5B9D,0xA708,0x5C06, +0xA774,0x5C6F,0xA7E2,0x5CD7,0xA84F,0x5D3E,0xA8BD,0x5DA5,0xA92C,0x5E0C,0xA99B, +0x5E72,0xAA0A,0x5ED7,0xAA7A,0x5F3C,0xAAEB,0x5FA1,0xAB5C,0x6005,0xABCD,0x6068, +0xAC3F,0x60CB,0xACB1,0x612E,0xAD24,0x6190,0xAD97,0x61F1,0xAE0B,0x6252,0xAE7F, +0x62B2,0xAEF3,0x6312,0xAF68,0x6371,0xAFDD,0x63D0,0xB053,0x642E,0xB0C9,0x648B, +0xB140,0x64E9,0xB1B7,0x6545,0xB22F,0x65A1,0xB2A7,0x65FC,0xB31F,0x6657,0xB398, +0x66B2,0xB411,0x670B,0xB48B,0x6764,0xB505,0x67BD,0xB57F,0x6815,0xB5FA,0x686D, +0xB675,0x68C4,0xB6F1,0x691A,0xB76D,0x6970,0xB7E9,0x69C5,0xB866,0x6A1A,0xB8E3, +0x6A6E,0xB961,0x6AC1,0xB9DF,0x6B14,0xBA5D,0x6B66,0xBADC,0x6BB8,0xBB5B,0x6C09, +0xBBDA,0x6C5A,0xBC5A,0x6CAA,0xBCDA,0x6CF9,0xBD5B,0x6D48,0xBDDC,0x6D96,0xBE5D, +0x6DE4,0xBEDF,0x6E31,0xBF61,0x6E7D,0xBFE3,0x6EC9,0xC066,0x6F14,0xC0E9,0x6F5F, +0xC16C,0x6FA9,0xC1F0,0x6FF2,0xC274,0x703B,0xC2F8,0x7083,0xC37D,0x70CB,0xC402, +0x7112,0xC487,0x7158,0xC50D,0x719E,0xC593,0x71E3,0xC619,0x7228,0xC6A0,0x726C, +0xC727,0x72AF,0xC7AE,0x72F2,0xC836,0x7334,0xC8BE,0x7375,0xC946,0x73B6,0xC9CE, +0x73F6,0xCA57,0x7436,0xCAE0,0x7475,0xCB69,0x74B3,0xCBF3,0x74F0,0xCC7D,0x752D, +0xCD07,0x756A,0xCD92,0x75A6,0xCE1C,0x75E1,0xCEA7,0x761B,0xCF33,0x7655,0xCFBE, +0x768E,0xD04A,0x76C7,0xD0D6,0x76FE,0xD162,0x7736,0xD1EF,0x776C,0xD27C,0x77A2, +0xD309,0x77D8,0xD396,0x780C,0xD424,0x7840,0xD4B1,0x7874,0xD53F,0x78A6,0xD5CE, +0x78D8,0xD65C,0x790A,0xD6EB,0x793A,0xD77A,0x796A,0xD809,0x799A,0xD898,0x79C9, +0xD928,0x79F7,0xD9B8,0x7A24,0xDA48,0x7A51,0xDAD8,0x7A7D,0xDB68,0x7AA8,0xDBF9, +0x7AD3,0xDC8A,0x7AFD,0xDD1B,0x7B27,0xDDAC,0x7B50,0xDE3D,0x7B78,0xDECF,0x7B9F, +0xDF61,0x7BC6,0xDFF2,0x7BEC,0xE085,0x7C11,0xE117,0x7C36,0xE1A9,0x7C5A,0xE23C, +0x7C7E,0xE2CF,0x7CA0,0xE361,0x7CC2,0xE3F4,0x7CE4,0xE488,0x7D05,0xE51B,0x7D25, +0xE5AF,0x7D44,0xE642,0x7D63,0xE6D6,0x7D81,0xE76A,0x7D9E,0xE7FE,0x7DBA,0xE892, +0x7DD6,0xE926,0x7DF2,0xE9BB,0x7E0C,0xEA4F,0x7E26,0xEAE4,0x7E3F,0xEB79,0x7E58, +0xEC0E,0x7E70,0xECA3,0x7E87,0xED38,0x7E9D,0xEDCD,0x7EB3,0xEE62,0x7EC8,0xEEF8, +0x7EDD,0xEF8D,0x7EF0,0xF023,0x7F03,0xF0B9,0x7F16,0xF14E,0x7F27,0xF1E4,0x7F38, +0xF27A,0x7F49,0xF310,0x7F58,0xF3A6,0x7F67,0xF43C,0x7F75,0xF4D3,0x7F83,0xF569, +0x7F90,0xF5FF,0x7F9C,0xF695,0x7FA7,0xF72C,0x7FB2,0xF7C2,0x7FBC,0xF859,0x7FC5, +0xF8EF,0x7FCE,0xF986,0x7FD6,0xFA1D,0x7FDD,0xFAB3,0x7FE4,0xFB4A,0x7FEA,0xFBE1, +0x7FEF,0xFC77,0x7FF4,0xFD0E,0x7FF7,0xFDA5,0x7FFA,0xFE3C,0x7FFD,0xFED2,0x7FFF, +0xFF69,0x7FFF,0x7FFF,0x0000,0x7FFA,0xFDA5,0x7FEA,0xFB4A,0x7FCE,0xF8EF,0x7FA7, +0xF695,0x7F75,0xF43C,0x7F38,0xF1E4,0x7EF0,0xEF8D,0x7E9D,0xED38,0x7E3F,0xEAE4, +0x7DD6,0xE892,0x7D63,0xE642,0x7CE4,0xE3F4,0x7C5A,0xE1A9,0x7BC6,0xDF61,0x7B27, +0xDD1B,0x7A7D,0xDAD8,0x79C9,0xD898,0x790A,0xD65C,0x7840,0xD424,0x776C,0xD1EF, +0x768E,0xCFBE,0x75A6,0xCD92,0x74B3,0xCB69,0x73B6,0xC946,0x72AF,0xC727,0x719E, +0xC50D,0x7083,0xC2F8,0x6F5F,0xC0E9,0x6E31,0xBEDF,0x6CF9,0xBCDA,0x6BB8,0xBADC, +0x6A6E,0xB8E3,0x691A,0xB6F1,0x67BD,0xB505,0x6657,0xB31F,0x64E9,0xB140,0x6371, +0xAF68,0x61F1,0xAD97,0x6068,0xABCD,0x5ED7,0xAA0A,0x5D3E,0xA84F,0x5B9D,0xA69C, +0x59F4,0xA4F0,0x5843,0xA34C,0x568A,0xA1B0,0x54CA,0xA01C,0x5303,0x9E91,0x5134, +0x9D0E,0x4F5E,0x9B94,0x4D81,0x9A22,0x4B9E,0x98B9,0x49B4,0x9759,0x47C4,0x9603, +0x45CD,0x94B5,0x43D1,0x9371,0x41CE,0x9236,0x3FC6,0x9105,0x3DB8,0x8FDD,0x3BA5, +0x8EBF,0x398D,0x8DAB,0x3770,0x8CA1,0x354E,0x8BA0,0x3327,0x8AAA,0x30FC,0x89BE, +0x2ECC,0x88DD,0x2C99,0x8805,0x2A62,0x8738,0x2827,0x8676,0x25E8,0x85BE,0x23A7, +0x8511,0x2162,0x846E,0x1F1A,0x83D6,0x1CD0,0x8349,0x1A83,0x82C6,0x1833,0x824F, +0x15E2,0x81E2,0x138F,0x8181,0x113A,0x812A,0x0EE4,0x80DE,0x0C8C,0x809E,0x0A33, +0x8068,0x07D9,0x803E,0x057F,0x801E,0x0324,0x800A,0x00C9,0x8001,0xFE6E,0x8002, +0xFC13,0x800F,0xF9B8,0x8027,0xF75E,0x804B,0xF505,0x8079,0xF2AC,0x80B2,0xF055, +0x80F6,0xEDFF,0x8146,0xEBAB,0x81A0,0xE958,0x8205,0xE707,0x8276,0xE4B9,0x82F1, +0xE26D,0x8377,0xE023,0x8407,0xDDDC,0x84A3,0xDB99,0x8549,0xD958,0x85FA,0xD71B, +0x86B6,0xD4E1,0x877B,0xD2AB,0x884C,0xD079,0x8927,0xCE4B,0x8A0C,0xCC21,0x8AFB, +0xC9FC,0x8BF5,0xC7DB,0x8CF8,0xC5C0,0x8E06,0xC3A9,0x8F1D,0xC198,0x903E,0xBF8C, +0x9169,0xBD86,0x929E,0xBB85,0x93DC,0xB98B,0x9523,0xB796,0x9674,0xB5A8,0x97CE, +0xB3C0,0x9930,0xB1DF,0x9A9C,0xB005,0x9C11,0xAE31,0x9D8E,0xAC65,0x9F14,0xAAA0, +0xA0A2,0xA8E2,0xA238,0xA72C,0xA3D7,0xA57E,0xA57E,0xA3D7,0xA72C,0xA238,0xA8E2, +0xA0A2,0xAAA0,0x9F14,0xAC65,0x9D8E,0xAE31,0x9C11,0xB005,0x9A9C,0xB1DF,0x9930, +0xB3C0,0x97CE,0xB5A8,0x9674,0xB796,0x9523,0xB98B,0x93DC,0xBB85,0x929E,0xBD86, +0x9169,0xBF8C,0x903E,0xC198,0x8F1D,0xC3A9,0x8E06,0xC5C0,0x8CF8,0xC7DB,0x8BF5, +0xC9FC,0x8AFB,0xCC21,0x8A0C,0xCE4B,0x8927,0xD079,0x884C,0xD2AB,0x877B,0xD4E1, +0x86B6,0xD71B,0x85FA,0xD958,0x8549,0xDB99,0x84A3,0xDDDC,0x8407,0xE023,0x8377, +0xE26D,0x82F1,0xE4B9,0x8276,0xE707,0x8205,0xE958,0x81A0,0xEBAB,0x8146,0xEDFF, +0x80F6,0xF055,0x80B2,0xF2AC,0x8079,0xF505,0x804B,0xF75E,0x8027,0xF9B8,0x800F, +0xFC13,0x8002,0xFE6E,0x8001,0x00C9,0x800A,0x0324,0x801E,0x057F,0x803E,0x07D9, +0x8068,0x0A33,0x809E,0x0C8C,0x80DE,0x0EE4,0x812A,0x113A,0x8181,0x138F,0x81E2, +0x15E2,0x824F,0x1833,0x82C6,0x1A83,0x8349,0x1CD0,0x83D6,0x1F1A,0x846E,0x2162, +0x8511,0x23A7,0x85BE,0x25E8,0x8676,0x2827,0x8738,0x2A62,0x8805,0x2C99,0x88DD, +0x2ECC,0x89BE,0x30FC,0x8AAA,0x3327,0x8BA0,0x354E,0x8CA1,0x3770,0x8DAB,0x398D, +0x8EBF,0x3BA5,0x8FDD,0x3DB8,0x9105,0x3FC6,0x9236,0x41CE,0x9371,0x43D1,0x94B5, +0x45CD,0x9603,0x47C4,0x9759,0x49B4,0x98B9,0x4B9E,0x9A22,0x4D81,0x9B94,0x4F5E, +0x9D0E,0x5134,0x9E91,0x5303,0xA01C,0x54CA,0xA1B0,0x568A,0xA34C,0x5843,0xA4F0, +0x59F4,0xA69C,0x5B9D,0xA84F,0x5D3E,0xAA0A,0x5ED7,0xABCD,0x6068,0xAD97,0x61F1, +0xAF68,0x6371,0xB140,0x64E9,0xB31F,0x6657,0xB505,0x67BD,0xB6F1,0x691A,0xB8E3, +0x6A6E,0xBADC,0x6BB8,0xBCDA,0x6CF9,0xBEDF,0x6E31,0xC0E9,0x6F5F,0xC2F8,0x7083, +0xC50D,0x719E,0xC727,0x72AF,0xC946,0x73B6,0xCB69,0x74B3,0xCD92,0x75A6,0xCFBE, +0x768E,0xD1EF,0x776C,0xD424,0x7840,0xD65C,0x790A,0xD898,0x79C9,0xDAD8,0x7A7D, +0xDD1B,0x7B27,0xDF61,0x7BC6,0xE1A9,0x7C5A,0xE3F4,0x7CE4,0xE642,0x7D63,0xE892, +0x7DD6,0xEAE4,0x7E3F,0xED38,0x7E9D,0xEF8D,0x7EF0,0xF1E4,0x7F38,0xF43C,0x7F75, +0xF695,0x7FA7,0xF8EF,0x7FCE,0xFB4A,0x7FEA,0xFDA5,0x7FFA,0x7FFF,0x0000,0x7FA7, +0xF695,0x7E9D,0xED38,0x7CE4,0xE3F4,0x7A7D,0xDAD8,0x776C,0xD1EF,0x73B6,0xC946, +0x6F5F,0xC0E9,0x6A6E,0xB8E3,0x64E9,0xB140,0x5ED7,0xAA0A,0x5843,0xA34C,0x5134, +0x9D0E,0x49B4,0x9759,0x41CE,0x9236,0x398D,0x8DAB,0x30FC,0x89BE,0x2827,0x8676, +0x1F1A,0x83D6,0x15E2,0x81E2,0x0C8C,0x809E,0x0324,0x800A,0xF9B8,0x8027,0xF055, +0x80F6,0xE707,0x8276,0xDDDC,0x84A3,0xD4E1,0x877B,0xCC21,0x8AFB,0xC3A9,0x8F1D, +0xBB85,0x93DC,0xB3C0,0x9930,0xAC65,0x9F14,0xA57E,0xA57E,0x9F14,0xAC65,0x9930, +0xB3C0,0x93DC,0xBB85,0x8F1D,0xC3A9,0x8AFB,0xCC21,0x877B,0xD4E1,0x84A3,0xDDDC, +0x8276,0xE707,0x80F6,0xF055,0x8027,0xF9B8,0x800A,0x0324,0x809E,0x0C8C,0x81E2, +0x15E2,0x83D6,0x1F1A,0x8676,0x2827,0x89BE,0x30FC,0x8DAB,0x398D,0x9236,0x41CE, +0x9759,0x49B4,0x9D0E,0x5134,0xA34C,0x5843,0xAA0A,0x5ED7,0xB140,0x64E9,0xB8E3, +0x6A6E,0xC0E9,0x6F5F,0xC946,0x73B6,0xD1EF,0x776C,0xDAD8,0x7A7D,0xE3F4,0x7CE4, +0xED38,0x7E9D,0xF695,0x7FA7,0x7FFF,0x0000,0x7A7D,0xDAD8,0x6A6E,0xB8E3,0x5134, +0x9D0E,0x30FC,0x89BE,0x0C8C,0x809E,0xE707,0x8276,0xC3A9,0x8F1D,0xA57E,0xA57E, +0x8F1D,0xC3A9,0x8276,0xE707,0x809E,0x0C8C,0x89BE,0x30FC,0x9D0E,0x5134,0xB8E3, +0x6A6E,0xDAD8,0x7A7D,0x7FFF,0x0000,0x30FC,0x89BE,0xA57E,0xA57E,0x89BE,0x30FC,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVEI) */ + diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c b/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c new file mode 100644 index 0000000..cd197e9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/CommonTables/arm_mve_tables_f16.c @@ -0,0 +1,5576 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables_f16.c + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * @version V1.10.0 + * @date 04 October 2021 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "arm_math_types_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + +uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2]={ +0,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2]={ +0,0,}; + +float16_t rearranged_twiddle_stride1_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_16_f16[8]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + +uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3]={ +0,32,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3]={ +0,32,0,}; + +float16_t rearranged_twiddle_stride1_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_64_f16[40]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + +uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4]={ +0,128,160,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4]={ +0,128,160,0,}; + +float16_t rearranged_twiddle_stride1_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_256_f16[168]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + +uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5]={ +0,512,640,672,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5]={ +0,512,640,672,0,}; + +float16_t rearranged_twiddle_stride1_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_1024_f16[680]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192) + +uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6]={ +0,2048,2560,2688,2720,0,}; + +float16_t rearranged_twiddle_stride1_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0015335083008f, +(float16_t)1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0046005249023f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0076713562012f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0107345581055f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0138015747070f, +(float16_t)1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)1.0000000000000f,(float16_t)0.0168762207031f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)1.0000000000000f,(float16_t)0.0199432373047f, +(float16_t)1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)0.9995117187500f,(float16_t)0.0230102539062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0260772705078f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0291442871094f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0321960449219f, +(float16_t)0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)0.9995117187500f,(float16_t)0.0352783203125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0383300781250f, +(float16_t)0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)0.9990234375000f,(float16_t)0.0414123535156f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0444641113281f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9990234375000f,(float16_t)0.0475463867188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0505981445312f, +(float16_t)0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)0.9985351562500f,(float16_t)0.0536499023438f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9985351562500f,(float16_t)0.0567321777344f, +(float16_t)0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)0.9980468750000f,(float16_t)0.0597839355469f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9980468750000f,(float16_t)0.0628662109375f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9980468750000f,(float16_t)0.0659179687500f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9975585937500f,(float16_t)0.0689697265625f, +(float16_t)0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)0.9975585937500f,(float16_t)0.0720214843750f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0750732421875f, +(float16_t)0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)0.9970703125000f,(float16_t)0.0781250000000f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9965820312500f,(float16_t)0.0812377929688f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9965820312500f,(float16_t)0.0842895507812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9960937500000f,(float16_t)0.0873413085938f, +(float16_t)0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)0.9960937500000f,(float16_t)0.0903930664062f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9956054687500f,(float16_t)0.0934448242188f, +(float16_t)0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)0.9951171875000f,(float16_t)0.0964965820312f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9951171875000f,(float16_t)0.0995483398438f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1026000976562f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9946289062500f,(float16_t)0.1056518554688f, +(float16_t)0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)0.9941406250000f,(float16_t)0.1087036132812f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9936523437500f,(float16_t)0.1117553710938f, +(float16_t)0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)0.9931640625000f,(float16_t)0.1148071289062f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9931640625000f,(float16_t)0.1178588867188f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9926757812500f,(float16_t)0.1209106445312f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9921875000000f,(float16_t)0.1239624023438f, +(float16_t)0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)0.9916992187500f,(float16_t)0.1269531250000f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9916992187500f,(float16_t)0.1300048828125f, +(float16_t)0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)0.9912109375000f,(float16_t)0.1330566406250f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9907226562500f,(float16_t)0.1361083984375f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9902343750000f,(float16_t)0.1391601562500f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9897460937500f,(float16_t)0.1422119140625f, +(float16_t)0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)0.9892578125000f,(float16_t)0.1452636718750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9887695312500f,(float16_t)0.1481933593750f, +(float16_t)0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)0.9882812500000f,(float16_t)0.1512451171875f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9877929687500f,(float16_t)0.1542968750000f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9873046875000f,(float16_t)0.1573486328125f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9868164062500f,(float16_t)0.1604003906250f, +(float16_t)0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)0.9863281250000f,(float16_t)0.1634521484375f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9858398437500f,(float16_t)0.1663818359375f, +(float16_t)0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)0.9853515625000f,(float16_t)0.1694335937500f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9848632812500f,(float16_t)0.1724853515625f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9843750000000f,(float16_t)0.1755371093750f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9838867187500f,(float16_t)0.1784667968750f, +(float16_t)0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)0.9833984375000f,(float16_t)0.1815185546875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9829101562500f,(float16_t)0.1845703125000f, +(float16_t)0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)0.9824218750000f,(float16_t)0.1876220703125f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9814453125000f,(float16_t)0.1905517578125f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9809570312500f,(float16_t)0.1936035156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9804687500000f,(float16_t)0.1966552734375f, +(float16_t)0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)0.9799804687500f,(float16_t)0.1995849609375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9794921875000f,(float16_t)0.2026367187500f, +(float16_t)0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)0.9785156250000f,(float16_t)0.2055664062500f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9780273437500f,(float16_t)0.2086181640625f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9775390625000f,(float16_t)0.2116699218750f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9765625000000f,(float16_t)0.2145996093750f, +(float16_t)0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)0.9760742187500f,(float16_t)0.2176513671875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9755859375000f,(float16_t)0.2205810546875f, +(float16_t)0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)0.9746093750000f,(float16_t)0.2236328125000f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9741210937500f,(float16_t)0.2265625000000f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9731445312500f,(float16_t)0.2296142578125f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9726562500000f,(float16_t)0.2325439453125f, +(float16_t)0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)0.9716796875000f,(float16_t)0.2354736328125f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9711914062500f,(float16_t)0.2385253906250f, +(float16_t)0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)0.9702148437500f,(float16_t)0.2414550781250f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9697265625000f,(float16_t)0.2445068359375f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9687500000000f,(float16_t)0.2474365234375f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9682617187500f,(float16_t)0.2504882812500f, +(float16_t)0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)0.9672851562500f,(float16_t)0.2534179687500f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9667968750000f,(float16_t)0.2563476562500f, +(float16_t)0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)0.9658203125000f,(float16_t)0.2592773437500f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9648437500000f,(float16_t)0.2622070312500f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9643554687500f,(float16_t)0.2651367187500f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9633789062500f,(float16_t)0.2683105468750f, +(float16_t)0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)0.9624023437500f,(float16_t)0.2712402343750f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9619140625000f,(float16_t)0.2741699218750f, +(float16_t)0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)0.9609375000000f,(float16_t)0.2770996093750f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9599609375000f,(float16_t)0.2800292968750f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9589843750000f,(float16_t)0.2829589843750f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9584960937500f,(float16_t)0.2858886718750f, +(float16_t)0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)0.9575195312500f,(float16_t)0.2888183593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9565429687500f,(float16_t)0.2917480468750f, +(float16_t)0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)0.9555664062500f,(float16_t)0.2946777343750f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9545898437500f,(float16_t)0.2976074218750f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9536132812500f,(float16_t)0.3005371093750f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9526367187500f,(float16_t)0.3034667968750f, +(float16_t)0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)0.9521484375000f,(float16_t)0.3063964843750f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9511718750000f,(float16_t)0.3093261718750f, +(float16_t)0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)0.9501953125000f,(float16_t)0.3122558593750f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9492187500000f,(float16_t)0.3151855468750f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9482421875000f,(float16_t)0.3181152343750f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9472656250000f,(float16_t)0.3210449218750f, +(float16_t)0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)0.9462890625000f,(float16_t)0.3239746093750f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9453125000000f,(float16_t)0.3266601562500f, +(float16_t)0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)0.9443359375000f,(float16_t)0.3295898437500f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9428710937500f,(float16_t)0.3325195312500f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9418945312500f,(float16_t)0.3354492187500f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9409179687500f,(float16_t)0.3383789062500f, +(float16_t)0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)0.9399414062500f,(float16_t)0.3413085937500f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9389648437500f,(float16_t)0.3439941406250f, +(float16_t)0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)0.9379882812500f,(float16_t)0.3469238281250f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9370117187500f,(float16_t)0.3498535156250f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9355468750000f,(float16_t)0.3527832031250f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9345703125000f,(float16_t)0.3557128906250f, +(float16_t)0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)0.9335937500000f,(float16_t)0.3583984375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9326171875000f,(float16_t)0.3613281250000f, +(float16_t)0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)0.9311523437500f,(float16_t)0.3642578125000f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9301757812500f,(float16_t)0.3669433593750f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9291992187500f,(float16_t)0.3698730468750f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9277343750000f,(float16_t)0.3728027343750f, +(float16_t)0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)0.9267578125000f,(float16_t)0.3754882812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9257812500000f,(float16_t)0.3784179687500f, +(float16_t)0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)0.9243164062500f,(float16_t)0.3813476562500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9233398437500f,(float16_t)0.3840332031250f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9218750000000f,(float16_t)0.3869628906250f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9208984375000f,(float16_t)0.3896484375000f, +(float16_t)0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)0.9199218750000f,(float16_t)0.3925781250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9184570312500f,(float16_t)0.3955078125000f, +(float16_t)0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)0.9174804687500f,(float16_t)0.3981933593750f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9160156250000f,(float16_t)0.4011230468750f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9150390625000f,(float16_t)0.4038085937500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9135742187500f,(float16_t)0.4067382812500f, +(float16_t)0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)0.9121093750000f,(float16_t)0.4094238281250f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9111328125000f,(float16_t)0.4123535156250f, +(float16_t)0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)0.9096679687500f,(float16_t)0.4150390625000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9086914062500f,(float16_t)0.4177246093750f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9072265625000f,(float16_t)0.4206542968750f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9057617187500f,(float16_t)0.4233398437500f, +(float16_t)0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)0.9047851562500f,(float16_t)0.4262695312500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9033203125000f,(float16_t)0.4289550781250f, +(float16_t)0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)0.9018554687500f,(float16_t)0.4316406250000f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.9008789062500f,(float16_t)0.4345703125000f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8994140625000f,(float16_t)0.4372558593750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8979492187500f,(float16_t)0.4399414062500f, +(float16_t)0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)0.8964843750000f,(float16_t)0.4426269531250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8955078125000f,(float16_t)0.4455566406250f, +(float16_t)0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)0.8940429687500f,(float16_t)0.4482421875000f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8925781250000f,(float16_t)0.4509277343750f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8911132812500f,(float16_t)0.4536132812500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8896484375000f,(float16_t)0.4565429687500f, +(float16_t)0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)0.8881835937500f,(float16_t)0.4592285156250f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8867187500000f,(float16_t)0.4619140625000f, +(float16_t)0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)0.8857421875000f,(float16_t)0.4645996093750f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8842773437500f,(float16_t)0.4672851562500f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8828125000000f,(float16_t)0.4699707031250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8813476562500f,(float16_t)0.4726562500000f, +(float16_t)0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)0.8798828125000f,(float16_t)0.4753417968750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8784179687500f,(float16_t)0.4780273437500f, +(float16_t)0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)0.8769531250000f,(float16_t)0.4809570312500f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8754882812500f,(float16_t)0.4836425781250f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8740234375000f,(float16_t)0.4863281250000f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8725585937500f,(float16_t)0.4887695312500f, +(float16_t)0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)0.8706054687500f,(float16_t)0.4914550781250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8691406250000f,(float16_t)0.4941406250000f, +(float16_t)0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)0.8676757812500f,(float16_t)0.4968261718750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8662109375000f,(float16_t)0.4995117187500f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8647460937500f,(float16_t)0.5024414062500f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8632812500000f,(float16_t)0.5048828125000f, +(float16_t)0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)0.8618164062500f,(float16_t)0.5073242187500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8598632812500f,(float16_t)0.5102539062500f, +(float16_t)0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)0.8583984375000f,(float16_t)0.5126953125000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8569335937500f,(float16_t)0.5156250000000f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8554687500000f,(float16_t)0.5180664062500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8540039062500f,(float16_t)0.5205078125000f, +(float16_t)0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)0.8520507812500f,(float16_t)0.5234375000000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8505859375000f,(float16_t)0.5258789062500f, +(float16_t)0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)0.8491210937500f,(float16_t)0.5283203125000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8471679687500f,(float16_t)0.5312500000000f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8457031250000f,(float16_t)0.5336914062500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8442382812500f,(float16_t)0.5361328125000f, +(float16_t)0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)0.8422851562500f,(float16_t)0.5390625000000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8408203125000f,(float16_t)0.5415039062500f, +(float16_t)0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)0.8388671875000f,(float16_t)0.5439453125000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8374023437500f,(float16_t)0.5463867187500f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8359375000000f,(float16_t)0.5493164062500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8339843750000f,(float16_t)0.5517578125000f, +(float16_t)0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)0.8325195312500f,(float16_t)0.5541992187500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8305664062500f,(float16_t)0.5566406250000f, +(float16_t)0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)0.8291015625000f,(float16_t)0.5595703125000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8271484375000f,(float16_t)0.5620117187500f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8256835937500f,(float16_t)0.5644531250000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8237304687500f,(float16_t)0.5668945312500f, +(float16_t)0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)0.8217773437500f,(float16_t)0.5693359375000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8203125000000f,(float16_t)0.5722656250000f, +(float16_t)0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)0.8183593750000f,(float16_t)0.5747070312500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8168945312500f,(float16_t)0.5771484375000f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8149414062500f,(float16_t)0.5795898437500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8129882812500f,(float16_t)0.5820312500000f, +(float16_t)0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)0.8115234375000f,(float16_t)0.5844726562500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8095703125000f,(float16_t)0.5869140625000f, +(float16_t)0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)0.8076171875000f,(float16_t)0.5893554687500f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8061523437500f,(float16_t)0.5917968750000f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8041992187500f,(float16_t)0.5942382812500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.8022460937500f,(float16_t)0.5971679687500f, +(float16_t)0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)0.8002929687500f,(float16_t)0.5996093750000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7988281250000f,(float16_t)0.6020507812500f, +(float16_t)0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)0.7968750000000f,(float16_t)0.6044921875000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7949218750000f,(float16_t)0.6069335937500f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7929687500000f,(float16_t)0.6093750000000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7910156250000f,(float16_t)0.6118164062500f, +(float16_t)0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)0.7890625000000f,(float16_t)0.6142578125000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7875976562500f,(float16_t)0.6162109375000f, +(float16_t)0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)0.7856445312500f,(float16_t)0.6186523437500f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7836914062500f,(float16_t)0.6210937500000f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7817382812500f,(float16_t)0.6235351562500f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7797851562500f,(float16_t)0.6259765625000f, +(float16_t)0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)0.7778320312500f,(float16_t)0.6284179687500f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7758789062500f,(float16_t)0.6308593750000f, +(float16_t)0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)0.7739257812500f,(float16_t)0.6333007812500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7719726562500f,(float16_t)0.6357421875000f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7700195312500f,(float16_t)0.6381835937500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7680664062500f,(float16_t)0.6401367187500f, +(float16_t)0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)0.7661132812500f,(float16_t)0.6425781250000f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7641601562500f,(float16_t)0.6450195312500f, +(float16_t)0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)0.7622070312500f,(float16_t)0.6474609375000f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7602539062500f,(float16_t)0.6499023437500f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7583007812500f,(float16_t)0.6518554687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7563476562500f,(float16_t)0.6542968750000f, +(float16_t)0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)0.7543945312500f,(float16_t)0.6567382812500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7519531250000f,(float16_t)0.6591796875000f, +(float16_t)0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)0.7500000000000f,(float16_t)0.6611328125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7480468750000f,(float16_t)0.6635742187500f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7460937500000f,(float16_t)0.6660156250000f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7441406250000f,(float16_t)0.6679687500000f, +(float16_t)0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)0.7421875000000f,(float16_t)0.6704101562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7397460937500f,(float16_t)0.6728515625000f, +(float16_t)0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)0.7377929687500f,(float16_t)0.6748046875000f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7358398437500f,(float16_t)0.6772460937500f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7338867187500f,(float16_t)0.6796875000000f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7314453125000f,(float16_t)0.6816406250000f, +(float16_t)0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)0.7294921875000f,(float16_t)0.6840820312500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7275390625000f,(float16_t)0.6860351562500f, +(float16_t)0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)0.7250976562500f,(float16_t)0.6884765625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7231445312500f,(float16_t)0.6904296875000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7211914062500f,(float16_t)0.6928710937500f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7187500000000f,(float16_t)0.6953125000000f, +(float16_t)0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)0.7167968750000f,(float16_t)0.6972656250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7148437500000f,(float16_t)0.6997070312500f, +(float16_t)0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)0.7124023437500f,(float16_t)0.7016601562500f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7104492187500f,(float16_t)0.7036132812500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7080078125000f,(float16_t)0.7060546875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7060546875000f,(float16_t)0.7080078125000f, +(float16_t)0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)0.7036132812500f,(float16_t)0.7104492187500f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.7016601562500f,(float16_t)0.7124023437500f, +(float16_t)0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)0.6997070312500f,(float16_t)0.7148437500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6972656250000f,(float16_t)0.7167968750000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6953125000000f,(float16_t)0.7187500000000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6928710937500f,(float16_t)0.7211914062500f, +(float16_t)0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)0.6904296875000f,(float16_t)0.7231445312500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6884765625000f,(float16_t)0.7250976562500f, +(float16_t)0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)0.6860351562500f,(float16_t)0.7275390625000f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6840820312500f,(float16_t)0.7294921875000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6816406250000f,(float16_t)0.7314453125000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6796875000000f,(float16_t)0.7338867187500f, +(float16_t)0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)0.6772460937500f,(float16_t)0.7358398437500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6748046875000f,(float16_t)0.7377929687500f, +(float16_t)0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)0.6728515625000f,(float16_t)0.7397460937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6704101562500f,(float16_t)0.7421875000000f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6679687500000f,(float16_t)0.7441406250000f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6660156250000f,(float16_t)0.7460937500000f, +(float16_t)0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)0.6635742187500f,(float16_t)0.7480468750000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6611328125000f,(float16_t)0.7500000000000f, +(float16_t)0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)0.6591796875000f,(float16_t)0.7519531250000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6567382812500f,(float16_t)0.7543945312500f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6542968750000f,(float16_t)0.7563476562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6518554687500f,(float16_t)0.7583007812500f, +(float16_t)0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)0.6499023437500f,(float16_t)0.7602539062500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6474609375000f,(float16_t)0.7622070312500f, +(float16_t)0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)0.6450195312500f,(float16_t)0.7641601562500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6425781250000f,(float16_t)0.7661132812500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6401367187500f,(float16_t)0.7680664062500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6381835937500f,(float16_t)0.7700195312500f, +(float16_t)0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)0.6357421875000f,(float16_t)0.7719726562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6333007812500f,(float16_t)0.7739257812500f, +(float16_t)0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)0.6308593750000f,(float16_t)0.7758789062500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6284179687500f,(float16_t)0.7778320312500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6259765625000f,(float16_t)0.7797851562500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6235351562500f,(float16_t)0.7817382812500f, +(float16_t)0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)0.6210937500000f,(float16_t)0.7836914062500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6186523437500f,(float16_t)0.7856445312500f, +(float16_t)0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)0.6162109375000f,(float16_t)0.7875976562500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6142578125000f,(float16_t)0.7890625000000f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6118164062500f,(float16_t)0.7910156250000f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6093750000000f,(float16_t)0.7929687500000f, +(float16_t)0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)0.6069335937500f,(float16_t)0.7949218750000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6044921875000f,(float16_t)0.7968750000000f, +(float16_t)0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)0.6020507812500f,(float16_t)0.7988281250000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5996093750000f,(float16_t)0.8002929687500f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5971679687500f,(float16_t)0.8022460937500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5942382812500f,(float16_t)0.8041992187500f, +(float16_t)0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)0.5917968750000f,(float16_t)0.8061523437500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5893554687500f,(float16_t)0.8076171875000f, +(float16_t)0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)0.5869140625000f,(float16_t)0.8095703125000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5844726562500f,(float16_t)0.8115234375000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5820312500000f,(float16_t)0.8129882812500f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5795898437500f,(float16_t)0.8149414062500f, +(float16_t)0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)0.5771484375000f,(float16_t)0.8168945312500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5747070312500f,(float16_t)0.8183593750000f, +(float16_t)0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)0.5722656250000f,(float16_t)0.8203125000000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5693359375000f,(float16_t)0.8217773437500f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5668945312500f,(float16_t)0.8237304687500f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5644531250000f,(float16_t)0.8256835937500f, +(float16_t)0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)0.5620117187500f,(float16_t)0.8271484375000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5595703125000f,(float16_t)0.8291015625000f, +(float16_t)0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)0.5566406250000f,(float16_t)0.8305664062500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5541992187500f,(float16_t)0.8325195312500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5517578125000f,(float16_t)0.8339843750000f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5493164062500f,(float16_t)0.8359375000000f, +(float16_t)0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)0.5463867187500f,(float16_t)0.8374023437500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5439453125000f,(float16_t)0.8388671875000f, +(float16_t)0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)0.5415039062500f,(float16_t)0.8408203125000f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5390625000000f,(float16_t)0.8422851562500f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5361328125000f,(float16_t)0.8442382812500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5336914062500f,(float16_t)0.8457031250000f, +(float16_t)0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)0.5312500000000f,(float16_t)0.8471679687500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5283203125000f,(float16_t)0.8491210937500f, +(float16_t)0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)0.5258789062500f,(float16_t)0.8505859375000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5234375000000f,(float16_t)0.8520507812500f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5205078125000f,(float16_t)0.8540039062500f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5180664062500f,(float16_t)0.8554687500000f, +(float16_t)0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)0.5156250000000f,(float16_t)0.8569335937500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5126953125000f,(float16_t)0.8583984375000f, +(float16_t)0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)0.5102539062500f,(float16_t)0.8598632812500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5073242187500f,(float16_t)0.8618164062500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5048828125000f,(float16_t)0.8632812500000f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.5024414062500f,(float16_t)0.8647460937500f, +(float16_t)0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)0.4995117187500f,(float16_t)0.8662109375000f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4968261718750f,(float16_t)0.8676757812500f, +(float16_t)0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)0.4941406250000f,(float16_t)0.8691406250000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4914550781250f,(float16_t)0.8706054687500f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4887695312500f,(float16_t)0.8725585937500f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4863281250000f,(float16_t)0.8740234375000f, +(float16_t)0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)0.4836425781250f,(float16_t)0.8754882812500f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4809570312500f,(float16_t)0.8769531250000f, +(float16_t)0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)0.4780273437500f,(float16_t)0.8784179687500f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4753417968750f,(float16_t)0.8798828125000f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4726562500000f,(float16_t)0.8813476562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4699707031250f,(float16_t)0.8828125000000f, +(float16_t)0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)0.4672851562500f,(float16_t)0.8842773437500f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4645996093750f,(float16_t)0.8857421875000f, +(float16_t)0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)0.4619140625000f,(float16_t)0.8867187500000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4592285156250f,(float16_t)0.8881835937500f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4565429687500f,(float16_t)0.8896484375000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4536132812500f,(float16_t)0.8911132812500f, +(float16_t)0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)0.4509277343750f,(float16_t)0.8925781250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4482421875000f,(float16_t)0.8940429687500f, +(float16_t)0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)0.4455566406250f,(float16_t)0.8955078125000f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4426269531250f,(float16_t)0.8964843750000f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4399414062500f,(float16_t)0.8979492187500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4372558593750f,(float16_t)0.8994140625000f, +(float16_t)0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)0.4345703125000f,(float16_t)0.9008789062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4316406250000f,(float16_t)0.9018554687500f, +(float16_t)0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)0.4289550781250f,(float16_t)0.9033203125000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4262695312500f,(float16_t)0.9047851562500f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4233398437500f,(float16_t)0.9057617187500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4206542968750f,(float16_t)0.9072265625000f, +(float16_t)0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)0.4177246093750f,(float16_t)0.9086914062500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4150390625000f,(float16_t)0.9096679687500f, +(float16_t)0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)0.4123535156250f,(float16_t)0.9111328125000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4094238281250f,(float16_t)0.9121093750000f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4067382812500f,(float16_t)0.9135742187500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.4038085937500f,(float16_t)0.9150390625000f, +(float16_t)0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)0.4011230468750f,(float16_t)0.9160156250000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3981933593750f,(float16_t)0.9174804687500f, +(float16_t)0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)0.3955078125000f,(float16_t)0.9184570312500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3925781250000f,(float16_t)0.9199218750000f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3896484375000f,(float16_t)0.9208984375000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3869628906250f,(float16_t)0.9218750000000f, +(float16_t)0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)0.3840332031250f,(float16_t)0.9233398437500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3813476562500f,(float16_t)0.9243164062500f, +(float16_t)0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)0.3784179687500f,(float16_t)0.9257812500000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3754882812500f,(float16_t)0.9267578125000f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3728027343750f,(float16_t)0.9277343750000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3698730468750f,(float16_t)0.9291992187500f, +(float16_t)0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)0.3669433593750f,(float16_t)0.9301757812500f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3642578125000f,(float16_t)0.9311523437500f, +(float16_t)0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)0.3613281250000f,(float16_t)0.9326171875000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3583984375000f,(float16_t)0.9335937500000f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3557128906250f,(float16_t)0.9345703125000f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3527832031250f,(float16_t)0.9355468750000f, +(float16_t)0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)0.3498535156250f,(float16_t)0.9370117187500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3469238281250f,(float16_t)0.9379882812500f, +(float16_t)0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)0.3439941406250f,(float16_t)0.9389648437500f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3413085937500f,(float16_t)0.9399414062500f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3383789062500f,(float16_t)0.9409179687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3354492187500f,(float16_t)0.9418945312500f, +(float16_t)0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)0.3325195312500f,(float16_t)0.9428710937500f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3295898437500f,(float16_t)0.9443359375000f, +(float16_t)0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)0.3266601562500f,(float16_t)0.9453125000000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3239746093750f,(float16_t)0.9462890625000f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3210449218750f,(float16_t)0.9472656250000f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3181152343750f,(float16_t)0.9482421875000f, +(float16_t)0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)0.3151855468750f,(float16_t)0.9492187500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3122558593750f,(float16_t)0.9501953125000f, +(float16_t)0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)0.3093261718750f,(float16_t)0.9511718750000f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3063964843750f,(float16_t)0.9521484375000f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3034667968750f,(float16_t)0.9526367187500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.3005371093750f,(float16_t)0.9536132812500f, +(float16_t)0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)0.2976074218750f,(float16_t)0.9545898437500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2946777343750f,(float16_t)0.9555664062500f, +(float16_t)0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)0.2917480468750f,(float16_t)0.9565429687500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2888183593750f,(float16_t)0.9575195312500f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2858886718750f,(float16_t)0.9584960937500f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2829589843750f,(float16_t)0.9589843750000f, +(float16_t)0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)0.2800292968750f,(float16_t)0.9599609375000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2770996093750f,(float16_t)0.9609375000000f, +(float16_t)0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)0.2741699218750f,(float16_t)0.9619140625000f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2712402343750f,(float16_t)0.9624023437500f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2683105468750f,(float16_t)0.9633789062500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2651367187500f,(float16_t)0.9643554687500f, +(float16_t)0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)0.2622070312500f,(float16_t)0.9648437500000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2592773437500f,(float16_t)0.9658203125000f, +(float16_t)0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)0.2563476562500f,(float16_t)0.9667968750000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2534179687500f,(float16_t)0.9672851562500f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2504882812500f,(float16_t)0.9682617187500f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2474365234375f,(float16_t)0.9687500000000f, +(float16_t)0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)0.2445068359375f,(float16_t)0.9697265625000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2414550781250f,(float16_t)0.9702148437500f, +(float16_t)0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)0.2385253906250f,(float16_t)0.9711914062500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2354736328125f,(float16_t)0.9716796875000f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2325439453125f,(float16_t)0.9726562500000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2296142578125f,(float16_t)0.9731445312500f, +(float16_t)0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)0.2265625000000f,(float16_t)0.9741210937500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2236328125000f,(float16_t)0.9746093750000f, +(float16_t)0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)0.2205810546875f,(float16_t)0.9755859375000f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2176513671875f,(float16_t)0.9760742187500f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2145996093750f,(float16_t)0.9765625000000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2116699218750f,(float16_t)0.9775390625000f, +(float16_t)0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)0.2086181640625f,(float16_t)0.9780273437500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2055664062500f,(float16_t)0.9785156250000f, +(float16_t)0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)0.2026367187500f,(float16_t)0.9794921875000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1995849609375f,(float16_t)0.9799804687500f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1966552734375f,(float16_t)0.9804687500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1936035156250f,(float16_t)0.9809570312500f, +(float16_t)0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)0.1905517578125f,(float16_t)0.9814453125000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1876220703125f,(float16_t)0.9824218750000f, +(float16_t)0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)0.1845703125000f,(float16_t)0.9829101562500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1815185546875f,(float16_t)0.9833984375000f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1784667968750f,(float16_t)0.9838867187500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1755371093750f,(float16_t)0.9843750000000f, +(float16_t)0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)0.1724853515625f,(float16_t)0.9848632812500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1694335937500f,(float16_t)0.9853515625000f, +(float16_t)0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)0.1663818359375f,(float16_t)0.9858398437500f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1634521484375f,(float16_t)0.9863281250000f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1604003906250f,(float16_t)0.9868164062500f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1573486328125f,(float16_t)0.9873046875000f, +(float16_t)0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)0.1542968750000f,(float16_t)0.9877929687500f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1512451171875f,(float16_t)0.9882812500000f, +(float16_t)0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)0.1481933593750f,(float16_t)0.9887695312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1452636718750f,(float16_t)0.9892578125000f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1422119140625f,(float16_t)0.9897460937500f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1391601562500f,(float16_t)0.9902343750000f, +(float16_t)0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)0.1361083984375f,(float16_t)0.9907226562500f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1330566406250f,(float16_t)0.9912109375000f, +(float16_t)0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)0.1300048828125f,(float16_t)0.9916992187500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1269531250000f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1239624023438f,(float16_t)0.9921875000000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1209106445312f,(float16_t)0.9926757812500f, +(float16_t)0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)0.1178588867188f,(float16_t)0.9931640625000f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1148071289062f,(float16_t)0.9931640625000f, +(float16_t)0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)0.1117553710938f,(float16_t)0.9936523437500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1087036132812f,(float16_t)0.9941406250000f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1056518554688f,(float16_t)0.9946289062500f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.1026000976562f,(float16_t)0.9946289062500f, +(float16_t)0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)0.0995483398438f,(float16_t)0.9951171875000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0964965820312f,(float16_t)0.9951171875000f, +(float16_t)0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)0.0934448242188f,(float16_t)0.9956054687500f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0903930664062f,(float16_t)0.9960937500000f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0873413085938f,(float16_t)0.9960937500000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0842895507812f,(float16_t)0.9965820312500f, +(float16_t)0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)0.0812377929688f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0781250000000f,(float16_t)0.9970703125000f, +(float16_t)0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)0.0750732421875f,(float16_t)0.9970703125000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0720214843750f,(float16_t)0.9975585937500f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0689697265625f,(float16_t)0.9975585937500f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0659179687500f,(float16_t)0.9980468750000f, +(float16_t)0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)0.0628662109375f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0597839355469f,(float16_t)0.9980468750000f, +(float16_t)0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)0.0567321777344f,(float16_t)0.9985351562500f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0536499023438f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0505981445312f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0475463867188f,(float16_t)0.9990234375000f, +(float16_t)0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)0.0444641113281f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0414123535156f,(float16_t)0.9990234375000f, +(float16_t)0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)0.0383300781250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0352783203125f,(float16_t)0.9995117187500f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0321960449219f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0291442871094f,(float16_t)0.9995117187500f, +(float16_t)0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)0.0260772705078f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0230102539062f,(float16_t)0.9995117187500f, +(float16_t)0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)0.0199432373047f,(float16_t)1.0000000000000f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0168762207031f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0138015747070f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0107345581055f,(float16_t)1.0000000000000f, +(float16_t)0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)0.0076713562012f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0046005249023f,(float16_t)1.0000000000000f, +(float16_t)0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)0.0015335083008f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f,}; + +float16_t rearranged_twiddle_stride2_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)-0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0092010498047f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)-0.0184020996094f,(float16_t)1.0000000000000f, +(float16_t)-0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0276031494141f,(float16_t)0.9995117187500f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)-0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)-0.0459899902344f,(float16_t)0.9990234375000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)-0.0552062988281f,(float16_t)0.9985351562500f, +(float16_t)-0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0643920898438f,(float16_t)0.9980468750000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)-0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)-0.0827636718750f,(float16_t)0.9965820312500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)-0.0919189453125f,(float16_t)0.9956054687500f, +(float16_t)-0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1010742187500f,(float16_t)0.9951171875000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)-0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)-0.1193847656250f,(float16_t)0.9926757812500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)-0.1285400390625f,(float16_t)0.9916992187500f, +(float16_t)-0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1375732421875f,(float16_t)0.9907226562500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)-0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)-0.1558837890625f,(float16_t)0.9877929687500f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)-0.1649169921875f,(float16_t)0.9863281250000f, +(float16_t)-0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1739501953125f,(float16_t)0.9848632812500f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)-0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)-0.1921386718750f,(float16_t)0.9814453125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)-0.2010498046875f,(float16_t)0.9794921875000f, +(float16_t)-0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2100830078125f,(float16_t)0.9775390625000f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)-0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)-0.2280273437500f,(float16_t)0.9736328125000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)-0.2370605468750f,(float16_t)0.9716796875000f, +(float16_t)-0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2459716796875f,(float16_t)0.9692382812500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)-0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)-0.2636718750000f,(float16_t)0.9643554687500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)-0.2727050781250f,(float16_t)0.9619140625000f, +(float16_t)-0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2814941406250f,(float16_t)0.9594726562500f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)-0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)-0.2990722656250f,(float16_t)0.9541015625000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)-0.3078613281250f,(float16_t)0.9516601562500f, +(float16_t)-0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3166503906250f,(float16_t)0.9487304687500f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)-0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)-0.3339843750000f,(float16_t)0.9423828125000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)-0.3427734375000f,(float16_t)0.9394531250000f, +(float16_t)-0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3513183593750f,(float16_t)0.9360351562500f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)-0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)-0.3684082031250f,(float16_t)0.9296875000000f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)-0.3769531250000f,(float16_t)0.9262695312500f, +(float16_t)-0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3854980468750f,(float16_t)0.9228515625000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)-0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)-0.4023437500000f,(float16_t)0.9155273437500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)-0.4108886718750f,(float16_t)0.9116210937500f, +(float16_t)-0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4191894531250f,(float16_t)0.9077148437500f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)-0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)-0.4357910156250f,(float16_t)0.8999023437500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)-0.4440917968750f,(float16_t)0.8959960937500f, +(float16_t)-0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4523925781250f,(float16_t)0.8916015625000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)-0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)-0.4687500000000f,(float16_t)0.8833007812500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)-0.4768066406250f,(float16_t)0.8789062500000f, +(float16_t)-0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4848632812500f,(float16_t)0.8745117187500f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)-0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)-0.5009765625000f,(float16_t)0.8657226562500f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)-0.5087890625000f,(float16_t)0.8608398437500f, +(float16_t)-0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5166015625000f,(float16_t)0.8559570312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)-0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)-0.5322265625000f,(float16_t)0.8466796875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)-0.5400390625000f,(float16_t)0.8417968750000f, +(float16_t)-0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5478515625000f,(float16_t)0.8364257812500f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)-0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)-0.5629882812500f,(float16_t)0.8261718750000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)-0.5708007812500f,(float16_t)0.8212890625000f, +(float16_t)-0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5781250000000f,(float16_t)0.8159179687500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)-0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)-0.5932617187500f,(float16_t)0.8051757812500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)-0.6005859375000f,(float16_t)0.7993164062500f, +(float16_t)-0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6079101562500f,(float16_t)0.7939453125000f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)-0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)-0.6225585937500f,(float16_t)0.7827148437500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)-0.6293945312500f,(float16_t)0.7768554687500f, +(float16_t)-0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6367187500000f,(float16_t)0.7709960937500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)-0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)-0.6508789062500f,(float16_t)0.7592773437500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)-0.6577148437500f,(float16_t)0.7534179687500f, +(float16_t)-0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6645507812500f,(float16_t)0.7470703125000f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)-0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)-0.6782226562500f,(float16_t)0.7348632812500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)-0.6850585937500f,(float16_t)0.7285156250000f, +(float16_t)-0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6918945312500f,(float16_t)0.7221679687500f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)-0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)-0.7050781250000f,(float16_t)0.7094726562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)-0.7114257812500f,(float16_t)0.7026367187500f, +(float16_t)-0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7177734375000f,(float16_t)0.6962890625000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)-0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)-0.7304687500000f,(float16_t)0.6826171875000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)-0.7368164062500f,(float16_t)0.6762695312500f, +(float16_t)-0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7431640625000f,(float16_t)0.6694335937500f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)-0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)-0.7553710937500f,(float16_t)0.6552734375000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)-0.7612304687500f,(float16_t)0.6484375000000f, +(float16_t)-0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7670898437500f,(float16_t)0.6416015625000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)-0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)-0.7788085937500f,(float16_t)0.6274414062500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)-0.7846679687500f,(float16_t)0.6201171875000f, +(float16_t)-0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7900390625000f,(float16_t)0.6127929687500f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)-0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)-0.8012695312500f,(float16_t)0.5981445312500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)-0.8066406250000f,(float16_t)0.5908203125000f, +(float16_t)-0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8120117187500f,(float16_t)0.5834960937500f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)-0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)-0.8227539062500f,(float16_t)0.5683593750000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)-0.8281250000000f,(float16_t)0.5605468750000f, +(float16_t)-0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8330078125000f,(float16_t)0.5532226562500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)-0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)-0.8432617187500f,(float16_t)0.5375976562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)-0.8481445312500f,(float16_t)0.5297851562500f, +(float16_t)-0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8530273437500f,(float16_t)0.5219726562500f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)-0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)-0.8623046875000f,(float16_t)0.5063476562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)-0.8671875000000f,(float16_t)0.4982910156250f, +(float16_t)-0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8715820312500f,(float16_t)0.4902343750000f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)-0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)-0.8803710937500f,(float16_t)0.4741210937500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)-0.8847656250000f,(float16_t)0.4660644531250f, +(float16_t)-0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8891601562500f,(float16_t)0.4577636718750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)-0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)-0.8974609375000f,(float16_t)0.4414062500000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)-0.9013671875000f,(float16_t)0.4331054687500f, +(float16_t)-0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9052734375000f,(float16_t)0.4248046875000f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)-0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)-0.9130859375000f,(float16_t)0.4079589843750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)-0.9165039062500f,(float16_t)0.3996582031250f, +(float16_t)-0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9204101562500f,(float16_t)0.3911132812500f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)-0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)-0.9272460937500f,(float16_t)0.3742675781250f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)-0.9306640625000f,(float16_t)0.3657226562500f, +(float16_t)-0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9340820312500f,(float16_t)0.3569335937500f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)-0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)-0.9404296875000f,(float16_t)0.3398437500000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)-0.9433593750000f,(float16_t)0.3310546875000f, +(float16_t)-0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9467773437500f,(float16_t)0.3225097656250f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)-0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)-0.9521484375000f,(float16_t)0.3049316406250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)-0.9550781250000f,(float16_t)0.2961425781250f, +(float16_t)-0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9580078125000f,(float16_t)0.2873535156250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)-0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)-0.9628906250000f,(float16_t)0.2697753906250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)-0.9653320312500f,(float16_t)0.2607421875000f, +(float16_t)-0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9677734375000f,(float16_t)0.2519531250000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)-0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)-0.9721679687500f,(float16_t)0.2340087890625f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)-0.9741210937500f,(float16_t)0.2250976562500f, +(float16_t)-0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9765625000000f,(float16_t)0.2160644531250f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)-0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)-0.9799804687500f,(float16_t)0.1981201171875f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)-0.9819335937500f,(float16_t)0.1890869140625f, +(float16_t)-0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9838867187500f,(float16_t)0.1800537109375f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)-0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)-0.9868164062500f,(float16_t)0.1618652343750f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)-0.9882812500000f,(float16_t)0.1528320312500f, +(float16_t)-0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9897460937500f,(float16_t)0.1436767578125f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)-0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)-0.9921875000000f,(float16_t)0.1254882812500f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)-0.9931640625000f,(float16_t)0.1163330078125f, +(float16_t)-0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9941406250000f,(float16_t)0.1071777343750f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)-0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)-0.9960937500000f,(float16_t)0.0888671875000f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)-0.9965820312500f,(float16_t)0.0797119140625f, +(float16_t)-0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9975585937500f,(float16_t)0.0704956054688f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)-0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)-0.9985351562500f,(float16_t)0.0521240234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)-0.9990234375000f,(float16_t)0.0429382324219f, +(float16_t)-0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0337524414062f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)-1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)-1.0000000000000f,(float16_t)0.0153427124023f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)-1.0000000000000f,(float16_t)0.0061340332031f, +(float16_t)-1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0368041992188f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)-0.0735473632812f,(float16_t)0.9970703125000f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1102294921875f,(float16_t)0.9941406250000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)-0.1829833984375f,(float16_t)0.9829101562500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)-0.2191162109375f,(float16_t)0.9755859375000f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2548828125000f,(float16_t)0.9667968750000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)-0.3251953125000f,(float16_t)0.9458007812500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)-0.3598632812500f,(float16_t)0.9331054687500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.3940429687500f,(float16_t)0.9189453125000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)-0.4604492187500f,(float16_t)0.8876953125000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)-0.4929199218750f,(float16_t)0.8701171875000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5244140625000f,(float16_t)0.8515625000000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)-0.5859375000000f,(float16_t)0.8105468750000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)-0.6152343750000f,(float16_t)0.7885742187500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6440429687500f,(float16_t)0.7651367187500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)-0.6982421875000f,(float16_t)0.7158203125000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)-0.7241210937500f,(float16_t)0.6894531250000f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7490234375000f,(float16_t)0.6625976562500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)-0.7958984375000f,(float16_t)0.6054687500000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)-0.8173828125000f,(float16_t)0.5756835937500f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8383789062500f,(float16_t)0.5454101562500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)-0.8759765625000f,(float16_t)0.4821777343750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)-0.8930664062500f,(float16_t)0.4497070312500f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9091796875000f,(float16_t)0.4165039062500f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)-0.9375000000000f,(float16_t)0.3483886718750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)-0.9497070312500f,(float16_t)0.3137207031250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9604492187500f,(float16_t)0.2785644531250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)-0.9785156250000f,(float16_t)0.2071533203125f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)-0.9853515625000f,(float16_t)0.1710205078125f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9907226562500f,(float16_t)0.1345214843750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)-0.9980468750000f,(float16_t)0.0613098144531f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)-0.9995117187500f,(float16_t)0.0245361328125f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1467285156250f,(float16_t)0.9892578125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)-0.2902832031250f,(float16_t)0.9570312500000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.4274902343750f,(float16_t)0.9038085937500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)-0.6713867187500f,(float16_t)0.7407226562500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)-0.7729492187500f,(float16_t)0.6342773437500f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.8579101562500f,(float16_t)0.5141601562500f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)-0.9702148437500f,(float16_t)0.2429199218750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)-0.9951171875000f,(float16_t)0.0980224609375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.5556640625000f,(float16_t)0.8315429687500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)-0.9238281250000f,(float16_t)0.3825683593750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)0.0000000000000f,(float16_t)1.0000000000000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f,}; + +float16_t rearranged_twiddle_stride3_4096_f16[2728]={ +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0046005249023f, +(float16_t)1.0000000000000f,(float16_t)0.0092010498047f, +(float16_t)1.0000000000000f,(float16_t)0.0138015747070f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0230102539062f, +(float16_t)0.9995117187500f,(float16_t)0.0276031494141f, +(float16_t)0.9995117187500f,(float16_t)0.0321960449219f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9990234375000f,(float16_t)0.0414123535156f, +(float16_t)0.9990234375000f,(float16_t)0.0459899902344f, +(float16_t)0.9985351562500f,(float16_t)0.0505981445312f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9980468750000f,(float16_t)0.0597839355469f, +(float16_t)0.9980468750000f,(float16_t)0.0643920898438f, +(float16_t)0.9975585937500f,(float16_t)0.0689697265625f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9970703125000f,(float16_t)0.0781250000000f, +(float16_t)0.9965820312500f,(float16_t)0.0827636718750f, +(float16_t)0.9960937500000f,(float16_t)0.0873413085938f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9951171875000f,(float16_t)0.0964965820312f, +(float16_t)0.9951171875000f,(float16_t)0.1010742187500f, +(float16_t)0.9946289062500f,(float16_t)0.1056518554688f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9931640625000f,(float16_t)0.1148071289062f, +(float16_t)0.9926757812500f,(float16_t)0.1193847656250f, +(float16_t)0.9921875000000f,(float16_t)0.1239624023438f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9912109375000f,(float16_t)0.1330566406250f, +(float16_t)0.9907226562500f,(float16_t)0.1375732421875f, +(float16_t)0.9897460937500f,(float16_t)0.1422119140625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9882812500000f,(float16_t)0.1512451171875f, +(float16_t)0.9877929687500f,(float16_t)0.1558837890625f, +(float16_t)0.9868164062500f,(float16_t)0.1604003906250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9853515625000f,(float16_t)0.1694335937500f, +(float16_t)0.9848632812500f,(float16_t)0.1739501953125f, +(float16_t)0.9838867187500f,(float16_t)0.1784667968750f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9824218750000f,(float16_t)0.1876220703125f, +(float16_t)0.9814453125000f,(float16_t)0.1921386718750f, +(float16_t)0.9804687500000f,(float16_t)0.1966552734375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9785156250000f,(float16_t)0.2055664062500f, +(float16_t)0.9775390625000f,(float16_t)0.2100830078125f, +(float16_t)0.9765625000000f,(float16_t)0.2145996093750f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9746093750000f,(float16_t)0.2236328125000f, +(float16_t)0.9736328125000f,(float16_t)0.2280273437500f, +(float16_t)0.9726562500000f,(float16_t)0.2325439453125f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9702148437500f,(float16_t)0.2414550781250f, +(float16_t)0.9692382812500f,(float16_t)0.2459716796875f, +(float16_t)0.9682617187500f,(float16_t)0.2504882812500f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9658203125000f,(float16_t)0.2592773437500f, +(float16_t)0.9643554687500f,(float16_t)0.2636718750000f, +(float16_t)0.9633789062500f,(float16_t)0.2683105468750f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9609375000000f,(float16_t)0.2770996093750f, +(float16_t)0.9594726562500f,(float16_t)0.2814941406250f, +(float16_t)0.9584960937500f,(float16_t)0.2858886718750f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9555664062500f,(float16_t)0.2946777343750f, +(float16_t)0.9541015625000f,(float16_t)0.2990722656250f, +(float16_t)0.9526367187500f,(float16_t)0.3034667968750f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9501953125000f,(float16_t)0.3122558593750f, +(float16_t)0.9487304687500f,(float16_t)0.3166503906250f, +(float16_t)0.9472656250000f,(float16_t)0.3210449218750f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9443359375000f,(float16_t)0.3295898437500f, +(float16_t)0.9423828125000f,(float16_t)0.3339843750000f, +(float16_t)0.9409179687500f,(float16_t)0.3383789062500f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9379882812500f,(float16_t)0.3469238281250f, +(float16_t)0.9360351562500f,(float16_t)0.3513183593750f, +(float16_t)0.9345703125000f,(float16_t)0.3557128906250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9311523437500f,(float16_t)0.3642578125000f, +(float16_t)0.9296875000000f,(float16_t)0.3684082031250f, +(float16_t)0.9277343750000f,(float16_t)0.3728027343750f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9243164062500f,(float16_t)0.3813476562500f, +(float16_t)0.9228515625000f,(float16_t)0.3854980468750f, +(float16_t)0.9208984375000f,(float16_t)0.3896484375000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9174804687500f,(float16_t)0.3981933593750f, +(float16_t)0.9155273437500f,(float16_t)0.4023437500000f, +(float16_t)0.9135742187500f,(float16_t)0.4067382812500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9096679687500f,(float16_t)0.4150390625000f, +(float16_t)0.9077148437500f,(float16_t)0.4191894531250f, +(float16_t)0.9057617187500f,(float16_t)0.4233398437500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.9018554687500f,(float16_t)0.4316406250000f, +(float16_t)0.8999023437500f,(float16_t)0.4357910156250f, +(float16_t)0.8979492187500f,(float16_t)0.4399414062500f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8940429687500f,(float16_t)0.4482421875000f, +(float16_t)0.8916015625000f,(float16_t)0.4523925781250f, +(float16_t)0.8896484375000f,(float16_t)0.4565429687500f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8857421875000f,(float16_t)0.4645996093750f, +(float16_t)0.8833007812500f,(float16_t)0.4687500000000f, +(float16_t)0.8813476562500f,(float16_t)0.4726562500000f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8769531250000f,(float16_t)0.4809570312500f, +(float16_t)0.8745117187500f,(float16_t)0.4848632812500f, +(float16_t)0.8725585937500f,(float16_t)0.4887695312500f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8676757812500f,(float16_t)0.4968261718750f, +(float16_t)0.8657226562500f,(float16_t)0.5009765625000f, +(float16_t)0.8632812500000f,(float16_t)0.5048828125000f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8583984375000f,(float16_t)0.5126953125000f, +(float16_t)0.8559570312500f,(float16_t)0.5166015625000f, +(float16_t)0.8540039062500f,(float16_t)0.5205078125000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8491210937500f,(float16_t)0.5283203125000f, +(float16_t)0.8466796875000f,(float16_t)0.5322265625000f, +(float16_t)0.8442382812500f,(float16_t)0.5361328125000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8388671875000f,(float16_t)0.5439453125000f, +(float16_t)0.8364257812500f,(float16_t)0.5478515625000f, +(float16_t)0.8339843750000f,(float16_t)0.5517578125000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8291015625000f,(float16_t)0.5595703125000f, +(float16_t)0.8261718750000f,(float16_t)0.5629882812500f, +(float16_t)0.8237304687500f,(float16_t)0.5668945312500f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8183593750000f,(float16_t)0.5747070312500f, +(float16_t)0.8159179687500f,(float16_t)0.5781250000000f, +(float16_t)0.8129882812500f,(float16_t)0.5820312500000f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.8076171875000f,(float16_t)0.5893554687500f, +(float16_t)0.8051757812500f,(float16_t)0.5932617187500f, +(float16_t)0.8022460937500f,(float16_t)0.5971679687500f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7968750000000f,(float16_t)0.6044921875000f, +(float16_t)0.7939453125000f,(float16_t)0.6079101562500f, +(float16_t)0.7910156250000f,(float16_t)0.6118164062500f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7856445312500f,(float16_t)0.6186523437500f, +(float16_t)0.7827148437500f,(float16_t)0.6225585937500f, +(float16_t)0.7797851562500f,(float16_t)0.6259765625000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7739257812500f,(float16_t)0.6333007812500f, +(float16_t)0.7709960937500f,(float16_t)0.6367187500000f, +(float16_t)0.7680664062500f,(float16_t)0.6401367187500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7622070312500f,(float16_t)0.6474609375000f, +(float16_t)0.7592773437500f,(float16_t)0.6508789062500f, +(float16_t)0.7563476562500f,(float16_t)0.6542968750000f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7500000000000f,(float16_t)0.6611328125000f, +(float16_t)0.7470703125000f,(float16_t)0.6645507812500f, +(float16_t)0.7441406250000f,(float16_t)0.6679687500000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7377929687500f,(float16_t)0.6748046875000f, +(float16_t)0.7348632812500f,(float16_t)0.6782226562500f, +(float16_t)0.7314453125000f,(float16_t)0.6816406250000f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7250976562500f,(float16_t)0.6884765625000f, +(float16_t)0.7221679687500f,(float16_t)0.6918945312500f, +(float16_t)0.7187500000000f,(float16_t)0.6953125000000f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7124023437500f,(float16_t)0.7016601562500f, +(float16_t)0.7094726562500f,(float16_t)0.7050781250000f, +(float16_t)0.7060546875000f,(float16_t)0.7080078125000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6997070312500f,(float16_t)0.7148437500000f, +(float16_t)0.6962890625000f,(float16_t)0.7177734375000f, +(float16_t)0.6928710937500f,(float16_t)0.7211914062500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6860351562500f,(float16_t)0.7275390625000f, +(float16_t)0.6826171875000f,(float16_t)0.7304687500000f, +(float16_t)0.6796875000000f,(float16_t)0.7338867187500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6728515625000f,(float16_t)0.7397460937500f, +(float16_t)0.6694335937500f,(float16_t)0.7431640625000f, +(float16_t)0.6660156250000f,(float16_t)0.7460937500000f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6591796875000f,(float16_t)0.7519531250000f, +(float16_t)0.6552734375000f,(float16_t)0.7553710937500f, +(float16_t)0.6518554687500f,(float16_t)0.7583007812500f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6450195312500f,(float16_t)0.7641601562500f, +(float16_t)0.6416015625000f,(float16_t)0.7670898437500f, +(float16_t)0.6381835937500f,(float16_t)0.7700195312500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6308593750000f,(float16_t)0.7758789062500f, +(float16_t)0.6274414062500f,(float16_t)0.7788085937500f, +(float16_t)0.6235351562500f,(float16_t)0.7817382812500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6162109375000f,(float16_t)0.7875976562500f, +(float16_t)0.6127929687500f,(float16_t)0.7900390625000f, +(float16_t)0.6093750000000f,(float16_t)0.7929687500000f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.6020507812500f,(float16_t)0.7988281250000f, +(float16_t)0.5981445312500f,(float16_t)0.8012695312500f, +(float16_t)0.5942382812500f,(float16_t)0.8041992187500f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5869140625000f,(float16_t)0.8095703125000f, +(float16_t)0.5834960937500f,(float16_t)0.8120117187500f, +(float16_t)0.5795898437500f,(float16_t)0.8149414062500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5722656250000f,(float16_t)0.8203125000000f, +(float16_t)0.5683593750000f,(float16_t)0.8227539062500f, +(float16_t)0.5644531250000f,(float16_t)0.8256835937500f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5566406250000f,(float16_t)0.8305664062500f, +(float16_t)0.5532226562500f,(float16_t)0.8330078125000f, +(float16_t)0.5493164062500f,(float16_t)0.8359375000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5415039062500f,(float16_t)0.8408203125000f, +(float16_t)0.5375976562500f,(float16_t)0.8432617187500f, +(float16_t)0.5336914062500f,(float16_t)0.8457031250000f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5258789062500f,(float16_t)0.8505859375000f, +(float16_t)0.5219726562500f,(float16_t)0.8530273437500f, +(float16_t)0.5180664062500f,(float16_t)0.8554687500000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.5102539062500f,(float16_t)0.8598632812500f, +(float16_t)0.5063476562500f,(float16_t)0.8623046875000f, +(float16_t)0.5024414062500f,(float16_t)0.8647460937500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4941406250000f,(float16_t)0.8691406250000f, +(float16_t)0.4902343750000f,(float16_t)0.8715820312500f, +(float16_t)0.4863281250000f,(float16_t)0.8740234375000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4780273437500f,(float16_t)0.8784179687500f, +(float16_t)0.4741210937500f,(float16_t)0.8803710937500f, +(float16_t)0.4699707031250f,(float16_t)0.8828125000000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4619140625000f,(float16_t)0.8867187500000f, +(float16_t)0.4577636718750f,(float16_t)0.8891601562500f, +(float16_t)0.4536132812500f,(float16_t)0.8911132812500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4455566406250f,(float16_t)0.8955078125000f, +(float16_t)0.4414062500000f,(float16_t)0.8974609375000f, +(float16_t)0.4372558593750f,(float16_t)0.8994140625000f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4289550781250f,(float16_t)0.9033203125000f, +(float16_t)0.4248046875000f,(float16_t)0.9052734375000f, +(float16_t)0.4206542968750f,(float16_t)0.9072265625000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.4123535156250f,(float16_t)0.9111328125000f, +(float16_t)0.4079589843750f,(float16_t)0.9130859375000f, +(float16_t)0.4038085937500f,(float16_t)0.9150390625000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3955078125000f,(float16_t)0.9184570312500f, +(float16_t)0.3911132812500f,(float16_t)0.9204101562500f, +(float16_t)0.3869628906250f,(float16_t)0.9218750000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3784179687500f,(float16_t)0.9257812500000f, +(float16_t)0.3742675781250f,(float16_t)0.9272460937500f, +(float16_t)0.3698730468750f,(float16_t)0.9291992187500f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3613281250000f,(float16_t)0.9326171875000f, +(float16_t)0.3569335937500f,(float16_t)0.9340820312500f, +(float16_t)0.3527832031250f,(float16_t)0.9355468750000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3439941406250f,(float16_t)0.9389648437500f, +(float16_t)0.3398437500000f,(float16_t)0.9404296875000f, +(float16_t)0.3354492187500f,(float16_t)0.9418945312500f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3266601562500f,(float16_t)0.9453125000000f, +(float16_t)0.3225097656250f,(float16_t)0.9467773437500f, +(float16_t)0.3181152343750f,(float16_t)0.9482421875000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.3093261718750f,(float16_t)0.9511718750000f, +(float16_t)0.3049316406250f,(float16_t)0.9521484375000f, +(float16_t)0.3005371093750f,(float16_t)0.9536132812500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2917480468750f,(float16_t)0.9565429687500f, +(float16_t)0.2873535156250f,(float16_t)0.9580078125000f, +(float16_t)0.2829589843750f,(float16_t)0.9589843750000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2741699218750f,(float16_t)0.9619140625000f, +(float16_t)0.2697753906250f,(float16_t)0.9628906250000f, +(float16_t)0.2651367187500f,(float16_t)0.9643554687500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2563476562500f,(float16_t)0.9667968750000f, +(float16_t)0.2519531250000f,(float16_t)0.9677734375000f, +(float16_t)0.2474365234375f,(float16_t)0.9687500000000f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2385253906250f,(float16_t)0.9711914062500f, +(float16_t)0.2340087890625f,(float16_t)0.9721679687500f, +(float16_t)0.2296142578125f,(float16_t)0.9731445312500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2205810546875f,(float16_t)0.9755859375000f, +(float16_t)0.2160644531250f,(float16_t)0.9765625000000f, +(float16_t)0.2116699218750f,(float16_t)0.9775390625000f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.2026367187500f,(float16_t)0.9794921875000f, +(float16_t)0.1981201171875f,(float16_t)0.9799804687500f, +(float16_t)0.1936035156250f,(float16_t)0.9809570312500f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1845703125000f,(float16_t)0.9829101562500f, +(float16_t)0.1800537109375f,(float16_t)0.9838867187500f, +(float16_t)0.1755371093750f,(float16_t)0.9843750000000f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1663818359375f,(float16_t)0.9858398437500f, +(float16_t)0.1618652343750f,(float16_t)0.9868164062500f, +(float16_t)0.1573486328125f,(float16_t)0.9873046875000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1481933593750f,(float16_t)0.9887695312500f, +(float16_t)0.1436767578125f,(float16_t)0.9897460937500f, +(float16_t)0.1391601562500f,(float16_t)0.9902343750000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1300048828125f,(float16_t)0.9916992187500f, +(float16_t)0.1254882812500f,(float16_t)0.9921875000000f, +(float16_t)0.1209106445312f,(float16_t)0.9926757812500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.1117553710938f,(float16_t)0.9936523437500f, +(float16_t)0.1071777343750f,(float16_t)0.9941406250000f, +(float16_t)0.1026000976562f,(float16_t)0.9946289062500f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0934448242188f,(float16_t)0.9956054687500f, +(float16_t)0.0888671875000f,(float16_t)0.9960937500000f, +(float16_t)0.0842895507812f,(float16_t)0.9965820312500f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0750732421875f,(float16_t)0.9970703125000f, +(float16_t)0.0704956054688f,(float16_t)0.9975585937500f, +(float16_t)0.0659179687500f,(float16_t)0.9980468750000f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0567321777344f,(float16_t)0.9985351562500f, +(float16_t)0.0521240234375f,(float16_t)0.9985351562500f, +(float16_t)0.0475463867188f,(float16_t)0.9990234375000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0383300781250f,(float16_t)0.9990234375000f, +(float16_t)0.0337524414062f,(float16_t)0.9995117187500f, +(float16_t)0.0291442871094f,(float16_t)0.9995117187500f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0199432373047f,(float16_t)1.0000000000000f, +(float16_t)0.0153427124023f,(float16_t)1.0000000000000f, +(float16_t)0.0107345581055f,(float16_t)1.0000000000000f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)0.0015335083008f,(float16_t)1.0000000000000f, +(float16_t)-0.0030670166016f,(float16_t)1.0000000000000f, +(float16_t)-0.0076713562012f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0168762207031f,(float16_t)1.0000000000000f, +(float16_t)-0.0214691162109f,(float16_t)1.0000000000000f, +(float16_t)-0.0260772705078f,(float16_t)0.9995117187500f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0352783203125f,(float16_t)0.9995117187500f, +(float16_t)-0.0398864746094f,(float16_t)0.9990234375000f, +(float16_t)-0.0444641113281f,(float16_t)0.9990234375000f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0536499023438f,(float16_t)0.9985351562500f, +(float16_t)-0.0582580566406f,(float16_t)0.9985351562500f, +(float16_t)-0.0628662109375f,(float16_t)0.9980468750000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0720214843750f,(float16_t)0.9975585937500f, +(float16_t)-0.0765991210938f,(float16_t)0.9970703125000f, +(float16_t)-0.0812377929688f,(float16_t)0.9965820312500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.0903930664062f,(float16_t)0.9960937500000f, +(float16_t)-0.0949707031250f,(float16_t)0.9956054687500f, +(float16_t)-0.0995483398438f,(float16_t)0.9951171875000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1087036132812f,(float16_t)0.9941406250000f, +(float16_t)-0.1132812500000f,(float16_t)0.9936523437500f, +(float16_t)-0.1178588867188f,(float16_t)0.9931640625000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1269531250000f,(float16_t)0.9916992187500f, +(float16_t)-0.1315917968750f,(float16_t)0.9912109375000f, +(float16_t)-0.1361083984375f,(float16_t)0.9907226562500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1452636718750f,(float16_t)0.9892578125000f, +(float16_t)-0.1497802734375f,(float16_t)0.9887695312500f, +(float16_t)-0.1542968750000f,(float16_t)0.9877929687500f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1634521484375f,(float16_t)0.9863281250000f, +(float16_t)-0.1679687500000f,(float16_t)0.9858398437500f, +(float16_t)-0.1724853515625f,(float16_t)0.9848632812500f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1815185546875f,(float16_t)0.9833984375000f, +(float16_t)-0.1860351562500f,(float16_t)0.9824218750000f, +(float16_t)-0.1905517578125f,(float16_t)0.9814453125000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.1995849609375f,(float16_t)0.9799804687500f, +(float16_t)-0.2041015625000f,(float16_t)0.9790039062500f, +(float16_t)-0.2086181640625f,(float16_t)0.9780273437500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2176513671875f,(float16_t)0.9760742187500f, +(float16_t)-0.2220458984375f,(float16_t)0.9750976562500f, +(float16_t)-0.2265625000000f,(float16_t)0.9741210937500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2354736328125f,(float16_t)0.9716796875000f, +(float16_t)-0.2399902343750f,(float16_t)0.9707031250000f, +(float16_t)-0.2445068359375f,(float16_t)0.9697265625000f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2534179687500f,(float16_t)0.9672851562500f, +(float16_t)-0.2578125000000f,(float16_t)0.9663085937500f, +(float16_t)-0.2622070312500f,(float16_t)0.9648437500000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2712402343750f,(float16_t)0.9624023437500f, +(float16_t)-0.2756347656250f,(float16_t)0.9614257812500f, +(float16_t)-0.2800292968750f,(float16_t)0.9599609375000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.2888183593750f,(float16_t)0.9575195312500f, +(float16_t)-0.2932128906250f,(float16_t)0.9560546875000f, +(float16_t)-0.2976074218750f,(float16_t)0.9545898437500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3063964843750f,(float16_t)0.9521484375000f, +(float16_t)-0.3107910156250f,(float16_t)0.9506835937500f, +(float16_t)-0.3151855468750f,(float16_t)0.9492187500000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3239746093750f,(float16_t)0.9462890625000f, +(float16_t)-0.3281250000000f,(float16_t)0.9448242187500f, +(float16_t)-0.3325195312500f,(float16_t)0.9428710937500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3413085937500f,(float16_t)0.9399414062500f, +(float16_t)-0.3454589843750f,(float16_t)0.9384765625000f, +(float16_t)-0.3498535156250f,(float16_t)0.9370117187500f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3583984375000f,(float16_t)0.9335937500000f, +(float16_t)-0.3627929687500f,(float16_t)0.9316406250000f, +(float16_t)-0.3669433593750f,(float16_t)0.9301757812500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3754882812500f,(float16_t)0.9267578125000f, +(float16_t)-0.3798828125000f,(float16_t)0.9252929687500f, +(float16_t)-0.3840332031250f,(float16_t)0.9233398437500f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.3925781250000f,(float16_t)0.9199218750000f, +(float16_t)-0.3967285156250f,(float16_t)0.9179687500000f, +(float16_t)-0.4011230468750f,(float16_t)0.9160156250000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4094238281250f,(float16_t)0.9121093750000f, +(float16_t)-0.4135742187500f,(float16_t)0.9106445312500f, +(float16_t)-0.4177246093750f,(float16_t)0.9086914062500f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4262695312500f,(float16_t)0.9047851562500f, +(float16_t)-0.4304199218750f,(float16_t)0.9028320312500f, +(float16_t)-0.4345703125000f,(float16_t)0.9008789062500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4426269531250f,(float16_t)0.8964843750000f, +(float16_t)-0.4467773437500f,(float16_t)0.8945312500000f, +(float16_t)-0.4509277343750f,(float16_t)0.8925781250000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4592285156250f,(float16_t)0.8881835937500f, +(float16_t)-0.4633789062500f,(float16_t)0.8862304687500f, +(float16_t)-0.4672851562500f,(float16_t)0.8842773437500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4753417968750f,(float16_t)0.8798828125000f, +(float16_t)-0.4794921875000f,(float16_t)0.8774414062500f, +(float16_t)-0.4836425781250f,(float16_t)0.8754882812500f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.4914550781250f,(float16_t)0.8706054687500f, +(float16_t)-0.4956054687500f,(float16_t)0.8686523437500f, +(float16_t)-0.4995117187500f,(float16_t)0.8662109375000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5073242187500f,(float16_t)0.8618164062500f, +(float16_t)-0.5112304687500f,(float16_t)0.8593750000000f, +(float16_t)-0.5156250000000f,(float16_t)0.8569335937500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5234375000000f,(float16_t)0.8520507812500f, +(float16_t)-0.5273437500000f,(float16_t)0.8496093750000f, +(float16_t)-0.5312500000000f,(float16_t)0.8471679687500f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5390625000000f,(float16_t)0.8422851562500f, +(float16_t)-0.5429687500000f,(float16_t)0.8398437500000f, +(float16_t)-0.5463867187500f,(float16_t)0.8374023437500f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5541992187500f,(float16_t)0.8325195312500f, +(float16_t)-0.5581054687500f,(float16_t)0.8295898437500f, +(float16_t)-0.5620117187500f,(float16_t)0.8271484375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5693359375000f,(float16_t)0.8217773437500f, +(float16_t)-0.5732421875000f,(float16_t)0.8193359375000f, +(float16_t)-0.5771484375000f,(float16_t)0.8168945312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5844726562500f,(float16_t)0.8115234375000f, +(float16_t)-0.5883789062500f,(float16_t)0.8085937500000f, +(float16_t)-0.5917968750000f,(float16_t)0.8061523437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.5996093750000f,(float16_t)0.8002929687500f, +(float16_t)-0.6030273437500f,(float16_t)0.7978515625000f, +(float16_t)-0.6069335937500f,(float16_t)0.7949218750000f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6142578125000f,(float16_t)0.7890625000000f, +(float16_t)-0.6176757812500f,(float16_t)0.7866210937500f, +(float16_t)-0.6210937500000f,(float16_t)0.7836914062500f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6284179687500f,(float16_t)0.7778320312500f, +(float16_t)-0.6318359375000f,(float16_t)0.7749023437500f, +(float16_t)-0.6357421875000f,(float16_t)0.7719726562500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6425781250000f,(float16_t)0.7661132812500f, +(float16_t)-0.6459960937500f,(float16_t)0.7631835937500f, +(float16_t)-0.6499023437500f,(float16_t)0.7602539062500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6567382812500f,(float16_t)0.7543945312500f, +(float16_t)-0.6601562500000f,(float16_t)0.7509765625000f, +(float16_t)-0.6635742187500f,(float16_t)0.7480468750000f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6704101562500f,(float16_t)0.7421875000000f, +(float16_t)-0.6738281250000f,(float16_t)0.7387695312500f, +(float16_t)-0.6772460937500f,(float16_t)0.7358398437500f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6840820312500f,(float16_t)0.7294921875000f, +(float16_t)-0.6875000000000f,(float16_t)0.7265625000000f, +(float16_t)-0.6904296875000f,(float16_t)0.7231445312500f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.6972656250000f,(float16_t)0.7167968750000f, +(float16_t)-0.7006835937500f,(float16_t)0.7133789062500f, +(float16_t)-0.7036132812500f,(float16_t)0.7104492187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7104492187500f,(float16_t)0.7036132812500f, +(float16_t)-0.7133789062500f,(float16_t)0.7006835937500f, +(float16_t)-0.7167968750000f,(float16_t)0.6972656250000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7231445312500f,(float16_t)0.6904296875000f, +(float16_t)-0.7265625000000f,(float16_t)0.6875000000000f, +(float16_t)-0.7294921875000f,(float16_t)0.6840820312500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7358398437500f,(float16_t)0.6772460937500f, +(float16_t)-0.7387695312500f,(float16_t)0.6738281250000f, +(float16_t)-0.7421875000000f,(float16_t)0.6704101562500f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7480468750000f,(float16_t)0.6635742187500f, +(float16_t)-0.7509765625000f,(float16_t)0.6601562500000f, +(float16_t)-0.7543945312500f,(float16_t)0.6567382812500f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7602539062500f,(float16_t)0.6499023437500f, +(float16_t)-0.7631835937500f,(float16_t)0.6459960937500f, +(float16_t)-0.7661132812500f,(float16_t)0.6425781250000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7719726562500f,(float16_t)0.6357421875000f, +(float16_t)-0.7749023437500f,(float16_t)0.6318359375000f, +(float16_t)-0.7778320312500f,(float16_t)0.6284179687500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7836914062500f,(float16_t)0.6210937500000f, +(float16_t)-0.7866210937500f,(float16_t)0.6176757812500f, +(float16_t)-0.7890625000000f,(float16_t)0.6142578125000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.7949218750000f,(float16_t)0.6069335937500f, +(float16_t)-0.7978515625000f,(float16_t)0.6030273437500f, +(float16_t)-0.8002929687500f,(float16_t)0.5996093750000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8061523437500f,(float16_t)0.5917968750000f, +(float16_t)-0.8085937500000f,(float16_t)0.5883789062500f, +(float16_t)-0.8115234375000f,(float16_t)0.5844726562500f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8168945312500f,(float16_t)0.5771484375000f, +(float16_t)-0.8193359375000f,(float16_t)0.5732421875000f, +(float16_t)-0.8217773437500f,(float16_t)0.5693359375000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8271484375000f,(float16_t)0.5620117187500f, +(float16_t)-0.8295898437500f,(float16_t)0.5581054687500f, +(float16_t)-0.8325195312500f,(float16_t)0.5541992187500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8374023437500f,(float16_t)0.5463867187500f, +(float16_t)-0.8398437500000f,(float16_t)0.5429687500000f, +(float16_t)-0.8422851562500f,(float16_t)0.5390625000000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8471679687500f,(float16_t)0.5312500000000f, +(float16_t)-0.8496093750000f,(float16_t)0.5273437500000f, +(float16_t)-0.8520507812500f,(float16_t)0.5234375000000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8569335937500f,(float16_t)0.5156250000000f, +(float16_t)-0.8593750000000f,(float16_t)0.5112304687500f, +(float16_t)-0.8618164062500f,(float16_t)0.5073242187500f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8662109375000f,(float16_t)0.4995117187500f, +(float16_t)-0.8686523437500f,(float16_t)0.4956054687500f, +(float16_t)-0.8706054687500f,(float16_t)0.4914550781250f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8754882812500f,(float16_t)0.4836425781250f, +(float16_t)-0.8774414062500f,(float16_t)0.4794921875000f, +(float16_t)-0.8798828125000f,(float16_t)0.4753417968750f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8842773437500f,(float16_t)0.4672851562500f, +(float16_t)-0.8862304687500f,(float16_t)0.4633789062500f, +(float16_t)-0.8881835937500f,(float16_t)0.4592285156250f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8925781250000f,(float16_t)0.4509277343750f, +(float16_t)-0.8945312500000f,(float16_t)0.4467773437500f, +(float16_t)-0.8964843750000f,(float16_t)0.4426269531250f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9008789062500f,(float16_t)0.4345703125000f, +(float16_t)-0.9028320312500f,(float16_t)0.4304199218750f, +(float16_t)-0.9047851562500f,(float16_t)0.4262695312500f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9086914062500f,(float16_t)0.4177246093750f, +(float16_t)-0.9106445312500f,(float16_t)0.4135742187500f, +(float16_t)-0.9121093750000f,(float16_t)0.4094238281250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9160156250000f,(float16_t)0.4011230468750f, +(float16_t)-0.9179687500000f,(float16_t)0.3967285156250f, +(float16_t)-0.9199218750000f,(float16_t)0.3925781250000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9233398437500f,(float16_t)0.3840332031250f, +(float16_t)-0.9252929687500f,(float16_t)0.3798828125000f, +(float16_t)-0.9267578125000f,(float16_t)0.3754882812500f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9301757812500f,(float16_t)0.3669433593750f, +(float16_t)-0.9316406250000f,(float16_t)0.3627929687500f, +(float16_t)-0.9335937500000f,(float16_t)0.3583984375000f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9370117187500f,(float16_t)0.3498535156250f, +(float16_t)-0.9384765625000f,(float16_t)0.3454589843750f, +(float16_t)-0.9399414062500f,(float16_t)0.3413085937500f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9428710937500f,(float16_t)0.3325195312500f, +(float16_t)-0.9448242187500f,(float16_t)0.3281250000000f, +(float16_t)-0.9462890625000f,(float16_t)0.3239746093750f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9492187500000f,(float16_t)0.3151855468750f, +(float16_t)-0.9506835937500f,(float16_t)0.3107910156250f, +(float16_t)-0.9521484375000f,(float16_t)0.3063964843750f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9545898437500f,(float16_t)0.2976074218750f, +(float16_t)-0.9560546875000f,(float16_t)0.2932128906250f, +(float16_t)-0.9575195312500f,(float16_t)0.2888183593750f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9599609375000f,(float16_t)0.2800292968750f, +(float16_t)-0.9614257812500f,(float16_t)0.2756347656250f, +(float16_t)-0.9624023437500f,(float16_t)0.2712402343750f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9648437500000f,(float16_t)0.2622070312500f, +(float16_t)-0.9663085937500f,(float16_t)0.2578125000000f, +(float16_t)-0.9672851562500f,(float16_t)0.2534179687500f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9697265625000f,(float16_t)0.2445068359375f, +(float16_t)-0.9707031250000f,(float16_t)0.2399902343750f, +(float16_t)-0.9716796875000f,(float16_t)0.2354736328125f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9741210937500f,(float16_t)0.2265625000000f, +(float16_t)-0.9750976562500f,(float16_t)0.2220458984375f, +(float16_t)-0.9760742187500f,(float16_t)0.2176513671875f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9780273437500f,(float16_t)0.2086181640625f, +(float16_t)-0.9790039062500f,(float16_t)0.2041015625000f, +(float16_t)-0.9799804687500f,(float16_t)0.1995849609375f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9814453125000f,(float16_t)0.1905517578125f, +(float16_t)-0.9824218750000f,(float16_t)0.1860351562500f, +(float16_t)-0.9833984375000f,(float16_t)0.1815185546875f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9848632812500f,(float16_t)0.1724853515625f, +(float16_t)-0.9858398437500f,(float16_t)0.1679687500000f, +(float16_t)-0.9863281250000f,(float16_t)0.1634521484375f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9877929687500f,(float16_t)0.1542968750000f, +(float16_t)-0.9887695312500f,(float16_t)0.1497802734375f, +(float16_t)-0.9892578125000f,(float16_t)0.1452636718750f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9907226562500f,(float16_t)0.1361083984375f, +(float16_t)-0.9912109375000f,(float16_t)0.1315917968750f, +(float16_t)-0.9916992187500f,(float16_t)0.1269531250000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9931640625000f,(float16_t)0.1178588867188f, +(float16_t)-0.9936523437500f,(float16_t)0.1132812500000f, +(float16_t)-0.9941406250000f,(float16_t)0.1087036132812f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9951171875000f,(float16_t)0.0995483398438f, +(float16_t)-0.9956054687500f,(float16_t)0.0949707031250f, +(float16_t)-0.9960937500000f,(float16_t)0.0903930664062f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9965820312500f,(float16_t)0.0812377929688f, +(float16_t)-0.9970703125000f,(float16_t)0.0765991210938f, +(float16_t)-0.9975585937500f,(float16_t)0.0720214843750f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9980468750000f,(float16_t)0.0628662109375f, +(float16_t)-0.9985351562500f,(float16_t)0.0582580566406f, +(float16_t)-0.9985351562500f,(float16_t)0.0536499023438f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9990234375000f,(float16_t)0.0444641113281f, +(float16_t)-0.9990234375000f,(float16_t)0.0398864746094f, +(float16_t)-0.9995117187500f,(float16_t)0.0352783203125f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-0.9995117187500f,(float16_t)0.0260772705078f, +(float16_t)-1.0000000000000f,(float16_t)0.0214691162109f, +(float16_t)-1.0000000000000f,(float16_t)0.0168762207031f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)0.0076713562012f, +(float16_t)-1.0000000000000f,(float16_t)0.0030670166016f, +(float16_t)-1.0000000000000f,(float16_t)-0.0015335083008f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-1.0000000000000f,(float16_t)-0.0107345581055f, +(float16_t)-1.0000000000000f,(float16_t)-0.0153427124023f, +(float16_t)-1.0000000000000f,(float16_t)-0.0199432373047f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9995117187500f,(float16_t)-0.0291442871094f, +(float16_t)-0.9995117187500f,(float16_t)-0.0337524414062f, +(float16_t)-0.9990234375000f,(float16_t)-0.0383300781250f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9990234375000f,(float16_t)-0.0475463867188f, +(float16_t)-0.9985351562500f,(float16_t)-0.0521240234375f, +(float16_t)-0.9985351562500f,(float16_t)-0.0567321777344f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9980468750000f,(float16_t)-0.0659179687500f, +(float16_t)-0.9975585937500f,(float16_t)-0.0704956054688f, +(float16_t)-0.9970703125000f,(float16_t)-0.0750732421875f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9965820312500f,(float16_t)-0.0842895507812f, +(float16_t)-0.9960937500000f,(float16_t)-0.0888671875000f, +(float16_t)-0.9956054687500f,(float16_t)-0.0934448242188f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9946289062500f,(float16_t)-0.1026000976562f, +(float16_t)-0.9941406250000f,(float16_t)-0.1071777343750f, +(float16_t)-0.9936523437500f,(float16_t)-0.1117553710938f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9926757812500f,(float16_t)-0.1209106445312f, +(float16_t)-0.9921875000000f,(float16_t)-0.1254882812500f, +(float16_t)-0.9916992187500f,(float16_t)-0.1300048828125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9902343750000f,(float16_t)-0.1391601562500f, +(float16_t)-0.9897460937500f,(float16_t)-0.1436767578125f, +(float16_t)-0.9887695312500f,(float16_t)-0.1481933593750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9873046875000f,(float16_t)-0.1573486328125f, +(float16_t)-0.9868164062500f,(float16_t)-0.1618652343750f, +(float16_t)-0.9858398437500f,(float16_t)-0.1663818359375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9843750000000f,(float16_t)-0.1755371093750f, +(float16_t)-0.9838867187500f,(float16_t)-0.1800537109375f, +(float16_t)-0.9829101562500f,(float16_t)-0.1845703125000f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9809570312500f,(float16_t)-0.1936035156250f, +(float16_t)-0.9799804687500f,(float16_t)-0.1981201171875f, +(float16_t)-0.9794921875000f,(float16_t)-0.2026367187500f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9775390625000f,(float16_t)-0.2116699218750f, +(float16_t)-0.9765625000000f,(float16_t)-0.2160644531250f, +(float16_t)-0.9755859375000f,(float16_t)-0.2205810546875f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9731445312500f,(float16_t)-0.2296142578125f, +(float16_t)-0.9721679687500f,(float16_t)-0.2340087890625f, +(float16_t)-0.9711914062500f,(float16_t)-0.2385253906250f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9687500000000f,(float16_t)-0.2474365234375f, +(float16_t)-0.9677734375000f,(float16_t)-0.2519531250000f, +(float16_t)-0.9667968750000f,(float16_t)-0.2563476562500f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9643554687500f,(float16_t)-0.2651367187500f, +(float16_t)-0.9628906250000f,(float16_t)-0.2697753906250f, +(float16_t)-0.9619140625000f,(float16_t)-0.2741699218750f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9589843750000f,(float16_t)-0.2829589843750f, +(float16_t)-0.9580078125000f,(float16_t)-0.2873535156250f, +(float16_t)-0.9565429687500f,(float16_t)-0.2917480468750f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9536132812500f,(float16_t)-0.3005371093750f, +(float16_t)-0.9521484375000f,(float16_t)-0.3049316406250f, +(float16_t)-0.9511718750000f,(float16_t)-0.3093261718750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9482421875000f,(float16_t)-0.3181152343750f, +(float16_t)-0.9467773437500f,(float16_t)-0.3225097656250f, +(float16_t)-0.9453125000000f,(float16_t)-0.3266601562500f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9418945312500f,(float16_t)-0.3354492187500f, +(float16_t)-0.9404296875000f,(float16_t)-0.3398437500000f, +(float16_t)-0.9389648437500f,(float16_t)-0.3439941406250f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9355468750000f,(float16_t)-0.3527832031250f, +(float16_t)-0.9340820312500f,(float16_t)-0.3569335937500f, +(float16_t)-0.9326171875000f,(float16_t)-0.3613281250000f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9291992187500f,(float16_t)-0.3698730468750f, +(float16_t)-0.9272460937500f,(float16_t)-0.3742675781250f, +(float16_t)-0.9257812500000f,(float16_t)-0.3784179687500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9218750000000f,(float16_t)-0.3869628906250f, +(float16_t)-0.9204101562500f,(float16_t)-0.3911132812500f, +(float16_t)-0.9184570312500f,(float16_t)-0.3955078125000f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9150390625000f,(float16_t)-0.4038085937500f, +(float16_t)-0.9130859375000f,(float16_t)-0.4079589843750f, +(float16_t)-0.9111328125000f,(float16_t)-0.4123535156250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9072265625000f,(float16_t)-0.4206542968750f, +(float16_t)-0.9052734375000f,(float16_t)-0.4248046875000f, +(float16_t)-0.9033203125000f,(float16_t)-0.4289550781250f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8994140625000f,(float16_t)-0.4372558593750f, +(float16_t)-0.8974609375000f,(float16_t)-0.4414062500000f, +(float16_t)-0.8955078125000f,(float16_t)-0.4455566406250f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8911132812500f,(float16_t)-0.4536132812500f, +(float16_t)-0.8891601562500f,(float16_t)-0.4577636718750f, +(float16_t)-0.8867187500000f,(float16_t)-0.4619140625000f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8828125000000f,(float16_t)-0.4699707031250f, +(float16_t)-0.8803710937500f,(float16_t)-0.4741210937500f, +(float16_t)-0.8784179687500f,(float16_t)-0.4780273437500f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8740234375000f,(float16_t)-0.4863281250000f, +(float16_t)-0.8715820312500f,(float16_t)-0.4902343750000f, +(float16_t)-0.8691406250000f,(float16_t)-0.4941406250000f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8647460937500f,(float16_t)-0.5024414062500f, +(float16_t)-0.8623046875000f,(float16_t)-0.5063476562500f, +(float16_t)-0.8598632812500f,(float16_t)-0.5102539062500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8554687500000f,(float16_t)-0.5180664062500f, +(float16_t)-0.8530273437500f,(float16_t)-0.5219726562500f, +(float16_t)-0.8505859375000f,(float16_t)-0.5258789062500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8457031250000f,(float16_t)-0.5336914062500f, +(float16_t)-0.8432617187500f,(float16_t)-0.5375976562500f, +(float16_t)-0.8408203125000f,(float16_t)-0.5415039062500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8359375000000f,(float16_t)-0.5493164062500f, +(float16_t)-0.8330078125000f,(float16_t)-0.5532226562500f, +(float16_t)-0.8305664062500f,(float16_t)-0.5566406250000f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8256835937500f,(float16_t)-0.5644531250000f, +(float16_t)-0.8227539062500f,(float16_t)-0.5683593750000f, +(float16_t)-0.8203125000000f,(float16_t)-0.5722656250000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8149414062500f,(float16_t)-0.5795898437500f, +(float16_t)-0.8120117187500f,(float16_t)-0.5834960937500f, +(float16_t)-0.8095703125000f,(float16_t)-0.5869140625000f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.8041992187500f,(float16_t)-0.5942382812500f, +(float16_t)-0.8012695312500f,(float16_t)-0.5981445312500f, +(float16_t)-0.7988281250000f,(float16_t)-0.6020507812500f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7929687500000f,(float16_t)-0.6093750000000f, +(float16_t)-0.7900390625000f,(float16_t)-0.6127929687500f, +(float16_t)-0.7875976562500f,(float16_t)-0.6162109375000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7817382812500f,(float16_t)-0.6235351562500f, +(float16_t)-0.7788085937500f,(float16_t)-0.6274414062500f, +(float16_t)-0.7758789062500f,(float16_t)-0.6308593750000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7700195312500f,(float16_t)-0.6381835937500f, +(float16_t)-0.7670898437500f,(float16_t)-0.6416015625000f, +(float16_t)-0.7641601562500f,(float16_t)-0.6450195312500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7583007812500f,(float16_t)-0.6518554687500f, +(float16_t)-0.7553710937500f,(float16_t)-0.6552734375000f, +(float16_t)-0.7519531250000f,(float16_t)-0.6591796875000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7460937500000f,(float16_t)-0.6660156250000f, +(float16_t)-0.7431640625000f,(float16_t)-0.6694335937500f, +(float16_t)-0.7397460937500f,(float16_t)-0.6728515625000f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7338867187500f,(float16_t)-0.6796875000000f, +(float16_t)-0.7304687500000f,(float16_t)-0.6826171875000f, +(float16_t)-0.7275390625000f,(float16_t)-0.6860351562500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7211914062500f,(float16_t)-0.6928710937500f, +(float16_t)-0.7177734375000f,(float16_t)-0.6962890625000f, +(float16_t)-0.7148437500000f,(float16_t)-0.6997070312500f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.7080078125000f,(float16_t)-0.7060546875000f, +(float16_t)-0.7050781250000f,(float16_t)-0.7094726562500f, +(float16_t)-0.7016601562500f,(float16_t)-0.7124023437500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6953125000000f,(float16_t)-0.7187500000000f, +(float16_t)-0.6918945312500f,(float16_t)-0.7221679687500f, +(float16_t)-0.6884765625000f,(float16_t)-0.7250976562500f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6816406250000f,(float16_t)-0.7314453125000f, +(float16_t)-0.6782226562500f,(float16_t)-0.7348632812500f, +(float16_t)-0.6748046875000f,(float16_t)-0.7377929687500f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6679687500000f,(float16_t)-0.7441406250000f, +(float16_t)-0.6645507812500f,(float16_t)-0.7470703125000f, +(float16_t)-0.6611328125000f,(float16_t)-0.7500000000000f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6542968750000f,(float16_t)-0.7563476562500f, +(float16_t)-0.6508789062500f,(float16_t)-0.7592773437500f, +(float16_t)-0.6474609375000f,(float16_t)-0.7622070312500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6401367187500f,(float16_t)-0.7680664062500f, +(float16_t)-0.6367187500000f,(float16_t)-0.7709960937500f, +(float16_t)-0.6333007812500f,(float16_t)-0.7739257812500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6259765625000f,(float16_t)-0.7797851562500f, +(float16_t)-0.6225585937500f,(float16_t)-0.7827148437500f, +(float16_t)-0.6186523437500f,(float16_t)-0.7856445312500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6118164062500f,(float16_t)-0.7910156250000f, +(float16_t)-0.6079101562500f,(float16_t)-0.7939453125000f, +(float16_t)-0.6044921875000f,(float16_t)-0.7968750000000f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5971679687500f,(float16_t)-0.8022460937500f, +(float16_t)-0.5932617187500f,(float16_t)-0.8051757812500f, +(float16_t)-0.5893554687500f,(float16_t)-0.8076171875000f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5820312500000f,(float16_t)-0.8129882812500f, +(float16_t)-0.5781250000000f,(float16_t)-0.8159179687500f, +(float16_t)-0.5747070312500f,(float16_t)-0.8183593750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5668945312500f,(float16_t)-0.8237304687500f, +(float16_t)-0.5629882812500f,(float16_t)-0.8261718750000f, +(float16_t)-0.5595703125000f,(float16_t)-0.8291015625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5517578125000f,(float16_t)-0.8339843750000f, +(float16_t)-0.5478515625000f,(float16_t)-0.8364257812500f, +(float16_t)-0.5439453125000f,(float16_t)-0.8388671875000f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5361328125000f,(float16_t)-0.8442382812500f, +(float16_t)-0.5322265625000f,(float16_t)-0.8466796875000f, +(float16_t)-0.5283203125000f,(float16_t)-0.8491210937500f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5205078125000f,(float16_t)-0.8540039062500f, +(float16_t)-0.5166015625000f,(float16_t)-0.8559570312500f, +(float16_t)-0.5126953125000f,(float16_t)-0.8583984375000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.5048828125000f,(float16_t)-0.8632812500000f, +(float16_t)-0.5009765625000f,(float16_t)-0.8657226562500f, +(float16_t)-0.4968261718750f,(float16_t)-0.8676757812500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4887695312500f,(float16_t)-0.8725585937500f, +(float16_t)-0.4848632812500f,(float16_t)-0.8745117187500f, +(float16_t)-0.4809570312500f,(float16_t)-0.8769531250000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4726562500000f,(float16_t)-0.8813476562500f, +(float16_t)-0.4687500000000f,(float16_t)-0.8833007812500f, +(float16_t)-0.4645996093750f,(float16_t)-0.8857421875000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4565429687500f,(float16_t)-0.8896484375000f, +(float16_t)-0.4523925781250f,(float16_t)-0.8916015625000f, +(float16_t)-0.4482421875000f,(float16_t)-0.8940429687500f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4399414062500f,(float16_t)-0.8979492187500f, +(float16_t)-0.4357910156250f,(float16_t)-0.8999023437500f, +(float16_t)-0.4316406250000f,(float16_t)-0.9018554687500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4233398437500f,(float16_t)-0.9057617187500f, +(float16_t)-0.4191894531250f,(float16_t)-0.9077148437500f, +(float16_t)-0.4150390625000f,(float16_t)-0.9096679687500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.4067382812500f,(float16_t)-0.9135742187500f, +(float16_t)-0.4023437500000f,(float16_t)-0.9155273437500f, +(float16_t)-0.3981933593750f,(float16_t)-0.9174804687500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3896484375000f,(float16_t)-0.9208984375000f, +(float16_t)-0.3854980468750f,(float16_t)-0.9228515625000f, +(float16_t)-0.3813476562500f,(float16_t)-0.9243164062500f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3728027343750f,(float16_t)-0.9277343750000f, +(float16_t)-0.3684082031250f,(float16_t)-0.9296875000000f, +(float16_t)-0.3642578125000f,(float16_t)-0.9311523437500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3557128906250f,(float16_t)-0.9345703125000f, +(float16_t)-0.3513183593750f,(float16_t)-0.9360351562500f, +(float16_t)-0.3469238281250f,(float16_t)-0.9379882812500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3383789062500f,(float16_t)-0.9409179687500f, +(float16_t)-0.3339843750000f,(float16_t)-0.9423828125000f, +(float16_t)-0.3295898437500f,(float16_t)-0.9443359375000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3210449218750f,(float16_t)-0.9472656250000f, +(float16_t)-0.3166503906250f,(float16_t)-0.9487304687500f, +(float16_t)-0.3122558593750f,(float16_t)-0.9501953125000f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.3034667968750f,(float16_t)-0.9526367187500f, +(float16_t)-0.2990722656250f,(float16_t)-0.9541015625000f, +(float16_t)-0.2946777343750f,(float16_t)-0.9555664062500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2858886718750f,(float16_t)-0.9584960937500f, +(float16_t)-0.2814941406250f,(float16_t)-0.9594726562500f, +(float16_t)-0.2770996093750f,(float16_t)-0.9609375000000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2683105468750f,(float16_t)-0.9633789062500f, +(float16_t)-0.2636718750000f,(float16_t)-0.9643554687500f, +(float16_t)-0.2592773437500f,(float16_t)-0.9658203125000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2504882812500f,(float16_t)-0.9682617187500f, +(float16_t)-0.2459716796875f,(float16_t)-0.9692382812500f, +(float16_t)-0.2414550781250f,(float16_t)-0.9702148437500f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2325439453125f,(float16_t)-0.9726562500000f, +(float16_t)-0.2280273437500f,(float16_t)-0.9736328125000f, +(float16_t)-0.2236328125000f,(float16_t)-0.9746093750000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2145996093750f,(float16_t)-0.9765625000000f, +(float16_t)-0.2100830078125f,(float16_t)-0.9775390625000f, +(float16_t)-0.2055664062500f,(float16_t)-0.9785156250000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1966552734375f,(float16_t)-0.9804687500000f, +(float16_t)-0.1921386718750f,(float16_t)-0.9814453125000f, +(float16_t)-0.1876220703125f,(float16_t)-0.9824218750000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1784667968750f,(float16_t)-0.9838867187500f, +(float16_t)-0.1739501953125f,(float16_t)-0.9848632812500f, +(float16_t)-0.1694335937500f,(float16_t)-0.9853515625000f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1604003906250f,(float16_t)-0.9868164062500f, +(float16_t)-0.1558837890625f,(float16_t)-0.9877929687500f, +(float16_t)-0.1512451171875f,(float16_t)-0.9882812500000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1422119140625f,(float16_t)-0.9897460937500f, +(float16_t)-0.1375732421875f,(float16_t)-0.9907226562500f, +(float16_t)-0.1330566406250f,(float16_t)-0.9912109375000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1239624023438f,(float16_t)-0.9921875000000f, +(float16_t)-0.1193847656250f,(float16_t)-0.9926757812500f, +(float16_t)-0.1148071289062f,(float16_t)-0.9931640625000f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.1056518554688f,(float16_t)-0.9946289062500f, +(float16_t)-0.1010742187500f,(float16_t)-0.9951171875000f, +(float16_t)-0.0964965820312f,(float16_t)-0.9951171875000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0873413085938f,(float16_t)-0.9960937500000f, +(float16_t)-0.0827636718750f,(float16_t)-0.9965820312500f, +(float16_t)-0.0781250000000f,(float16_t)-0.9970703125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0689697265625f,(float16_t)-0.9975585937500f, +(float16_t)-0.0643920898438f,(float16_t)-0.9980468750000f, +(float16_t)-0.0597839355469f,(float16_t)-0.9980468750000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0505981445312f,(float16_t)-0.9985351562500f, +(float16_t)-0.0459899902344f,(float16_t)-0.9990234375000f, +(float16_t)-0.0414123535156f,(float16_t)-0.9990234375000f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0321960449219f,(float16_t)-0.9995117187500f, +(float16_t)-0.0276031494141f,(float16_t)-0.9995117187500f, +(float16_t)-0.0230102539062f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)-0.0138015747070f,(float16_t)-1.0000000000000f, +(float16_t)-0.0092010498047f,(float16_t)-1.0000000000000f, +(float16_t)-0.0046005249023f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0184020996094f, +(float16_t)0.9995117187500f,(float16_t)0.0368041992188f, +(float16_t)0.9985351562500f,(float16_t)0.0552062988281f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9956054687500f,(float16_t)0.0919189453125f, +(float16_t)0.9941406250000f,(float16_t)0.1102294921875f, +(float16_t)0.9916992187500f,(float16_t)0.1285400390625f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9863281250000f,(float16_t)0.1649169921875f, +(float16_t)0.9829101562500f,(float16_t)0.1829833984375f, +(float16_t)0.9794921875000f,(float16_t)0.2010498046875f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9716796875000f,(float16_t)0.2370605468750f, +(float16_t)0.9667968750000f,(float16_t)0.2548828125000f, +(float16_t)0.9619140625000f,(float16_t)0.2727050781250f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9516601562500f,(float16_t)0.3078613281250f, +(float16_t)0.9458007812500f,(float16_t)0.3251953125000f, +(float16_t)0.9394531250000f,(float16_t)0.3427734375000f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9262695312500f,(float16_t)0.3769531250000f, +(float16_t)0.9189453125000f,(float16_t)0.3940429687500f, +(float16_t)0.9116210937500f,(float16_t)0.4108886718750f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8959960937500f,(float16_t)0.4440917968750f, +(float16_t)0.8876953125000f,(float16_t)0.4604492187500f, +(float16_t)0.8789062500000f,(float16_t)0.4768066406250f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8608398437500f,(float16_t)0.5087890625000f, +(float16_t)0.8515625000000f,(float16_t)0.5244140625000f, +(float16_t)0.8417968750000f,(float16_t)0.5400390625000f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.8212890625000f,(float16_t)0.5708007812500f, +(float16_t)0.8105468750000f,(float16_t)0.5859375000000f, +(float16_t)0.7993164062500f,(float16_t)0.6005859375000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7768554687500f,(float16_t)0.6293945312500f, +(float16_t)0.7651367187500f,(float16_t)0.6440429687500f, +(float16_t)0.7534179687500f,(float16_t)0.6577148437500f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.7285156250000f,(float16_t)0.6850585937500f, +(float16_t)0.7158203125000f,(float16_t)0.6982421875000f, +(float16_t)0.7026367187500f,(float16_t)0.7114257812500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6762695312500f,(float16_t)0.7368164062500f, +(float16_t)0.6625976562500f,(float16_t)0.7490234375000f, +(float16_t)0.6484375000000f,(float16_t)0.7612304687500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.6201171875000f,(float16_t)0.7846679687500f, +(float16_t)0.6054687500000f,(float16_t)0.7958984375000f, +(float16_t)0.5908203125000f,(float16_t)0.8066406250000f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5605468750000f,(float16_t)0.8281250000000f, +(float16_t)0.5454101562500f,(float16_t)0.8383789062500f, +(float16_t)0.5297851562500f,(float16_t)0.8481445312500f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4982910156250f,(float16_t)0.8671875000000f, +(float16_t)0.4821777343750f,(float16_t)0.8759765625000f, +(float16_t)0.4660644531250f,(float16_t)0.8847656250000f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.4331054687500f,(float16_t)0.9013671875000f, +(float16_t)0.4165039062500f,(float16_t)0.9091796875000f, +(float16_t)0.3996582031250f,(float16_t)0.9165039062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3657226562500f,(float16_t)0.9306640625000f, +(float16_t)0.3483886718750f,(float16_t)0.9375000000000f, +(float16_t)0.3310546875000f,(float16_t)0.9433593750000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2961425781250f,(float16_t)0.9550781250000f, +(float16_t)0.2785644531250f,(float16_t)0.9604492187500f, +(float16_t)0.2607421875000f,(float16_t)0.9653320312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.2250976562500f,(float16_t)0.9741210937500f, +(float16_t)0.2071533203125f,(float16_t)0.9785156250000f, +(float16_t)0.1890869140625f,(float16_t)0.9819335937500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.1528320312500f,(float16_t)0.9882812500000f, +(float16_t)0.1345214843750f,(float16_t)0.9907226562500f, +(float16_t)0.1163330078125f,(float16_t)0.9931640625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0797119140625f,(float16_t)0.9965820312500f, +(float16_t)0.0613098144531f,(float16_t)0.9980468750000f, +(float16_t)0.0429382324219f,(float16_t)0.9990234375000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)0.0061340332031f,(float16_t)1.0000000000000f, +(float16_t)-0.0122680664062f,(float16_t)1.0000000000000f, +(float16_t)-0.0306701660156f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.0674438476562f,(float16_t)0.9975585937500f, +(float16_t)-0.0858154296875f,(float16_t)0.9960937500000f, +(float16_t)-0.1041259765625f,(float16_t)0.9946289062500f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1406250000000f,(float16_t)0.9902343750000f, +(float16_t)-0.1588134765625f,(float16_t)0.9873046875000f, +(float16_t)-0.1770019531250f,(float16_t)0.9843750000000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2131347656250f,(float16_t)0.9770507812500f, +(float16_t)-0.2310791015625f,(float16_t)0.9731445312500f, +(float16_t)-0.2489013671875f,(float16_t)0.9687500000000f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.2844238281250f,(float16_t)0.9584960937500f, +(float16_t)-0.3020019531250f,(float16_t)0.9531250000000f, +(float16_t)-0.3195800781250f,(float16_t)0.9477539062500f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.3542480468750f,(float16_t)0.9350585937500f, +(float16_t)-0.3713378906250f,(float16_t)0.9287109375000f, +(float16_t)-0.3884277343750f,(float16_t)0.9213867187500f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4221191406250f,(float16_t)0.9067382812500f, +(float16_t)-0.4387207031250f,(float16_t)0.8984375000000f, +(float16_t)-0.4550781250000f,(float16_t)0.8906250000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.4875488281250f,(float16_t)0.8730468750000f, +(float16_t)-0.5034179687500f,(float16_t)0.8637695312500f, +(float16_t)-0.5195312500000f,(float16_t)0.8544921875000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5502929687500f,(float16_t)0.8349609375000f, +(float16_t)-0.5659179687500f,(float16_t)0.8247070312500f, +(float16_t)-0.5810546875000f,(float16_t)0.8139648437500f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6103515625000f,(float16_t)0.7919921875000f, +(float16_t)-0.6250000000000f,(float16_t)0.7807617187500f, +(float16_t)-0.6391601562500f,(float16_t)0.7690429687500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.6669921875000f,(float16_t)0.7451171875000f, +(float16_t)-0.6806640625000f,(float16_t)0.7324218750000f, +(float16_t)-0.6938476562500f,(float16_t)0.7202148437500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7202148437500f,(float16_t)0.6938476562500f, +(float16_t)-0.7324218750000f,(float16_t)0.6806640625000f, +(float16_t)-0.7451171875000f,(float16_t)0.6669921875000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.7690429687500f,(float16_t)0.6391601562500f, +(float16_t)-0.7807617187500f,(float16_t)0.6250000000000f, +(float16_t)-0.7919921875000f,(float16_t)0.6103515625000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8139648437500f,(float16_t)0.5810546875000f, +(float16_t)-0.8247070312500f,(float16_t)0.5659179687500f, +(float16_t)-0.8349609375000f,(float16_t)0.5502929687500f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8544921875000f,(float16_t)0.5195312500000f, +(float16_t)-0.8637695312500f,(float16_t)0.5034179687500f, +(float16_t)-0.8730468750000f,(float16_t)0.4875488281250f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.8906250000000f,(float16_t)0.4550781250000f, +(float16_t)-0.8984375000000f,(float16_t)0.4387207031250f, +(float16_t)-0.9067382812500f,(float16_t)0.4221191406250f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9213867187500f,(float16_t)0.3884277343750f, +(float16_t)-0.9287109375000f,(float16_t)0.3713378906250f, +(float16_t)-0.9350585937500f,(float16_t)0.3542480468750f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9477539062500f,(float16_t)0.3195800781250f, +(float16_t)-0.9531250000000f,(float16_t)0.3020019531250f, +(float16_t)-0.9584960937500f,(float16_t)0.2844238281250f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9687500000000f,(float16_t)0.2489013671875f, +(float16_t)-0.9731445312500f,(float16_t)0.2310791015625f, +(float16_t)-0.9770507812500f,(float16_t)0.2131347656250f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9843750000000f,(float16_t)0.1770019531250f, +(float16_t)-0.9873046875000f,(float16_t)0.1588134765625f, +(float16_t)-0.9902343750000f,(float16_t)0.1406250000000f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9946289062500f,(float16_t)0.1041259765625f, +(float16_t)-0.9960937500000f,(float16_t)0.0858154296875f, +(float16_t)-0.9975585937500f,(float16_t)0.0674438476562f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)0.0306701660156f, +(float16_t)-1.0000000000000f,(float16_t)0.0122680664062f, +(float16_t)-1.0000000000000f,(float16_t)-0.0061340332031f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9990234375000f,(float16_t)-0.0429382324219f, +(float16_t)-0.9980468750000f,(float16_t)-0.0613098144531f, +(float16_t)-0.9965820312500f,(float16_t)-0.0797119140625f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9931640625000f,(float16_t)-0.1163330078125f, +(float16_t)-0.9907226562500f,(float16_t)-0.1345214843750f, +(float16_t)-0.9882812500000f,(float16_t)-0.1528320312500f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9819335937500f,(float16_t)-0.1890869140625f, +(float16_t)-0.9785156250000f,(float16_t)-0.2071533203125f, +(float16_t)-0.9741210937500f,(float16_t)-0.2250976562500f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9653320312500f,(float16_t)-0.2607421875000f, +(float16_t)-0.9604492187500f,(float16_t)-0.2785644531250f, +(float16_t)-0.9550781250000f,(float16_t)-0.2961425781250f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9433593750000f,(float16_t)-0.3310546875000f, +(float16_t)-0.9375000000000f,(float16_t)-0.3483886718750f, +(float16_t)-0.9306640625000f,(float16_t)-0.3657226562500f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.9165039062500f,(float16_t)-0.3996582031250f, +(float16_t)-0.9091796875000f,(float16_t)-0.4165039062500f, +(float16_t)-0.9013671875000f,(float16_t)-0.4331054687500f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8847656250000f,(float16_t)-0.4660644531250f, +(float16_t)-0.8759765625000f,(float16_t)-0.4821777343750f, +(float16_t)-0.8671875000000f,(float16_t)-0.4982910156250f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8481445312500f,(float16_t)-0.5297851562500f, +(float16_t)-0.8383789062500f,(float16_t)-0.5454101562500f, +(float16_t)-0.8281250000000f,(float16_t)-0.5605468750000f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.8066406250000f,(float16_t)-0.5908203125000f, +(float16_t)-0.7958984375000f,(float16_t)-0.6054687500000f, +(float16_t)-0.7846679687500f,(float16_t)-0.6201171875000f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7612304687500f,(float16_t)-0.6484375000000f, +(float16_t)-0.7490234375000f,(float16_t)-0.6625976562500f, +(float16_t)-0.7368164062500f,(float16_t)-0.6762695312500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.7114257812500f,(float16_t)-0.7026367187500f, +(float16_t)-0.6982421875000f,(float16_t)-0.7158203125000f, +(float16_t)-0.6850585937500f,(float16_t)-0.7285156250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6577148437500f,(float16_t)-0.7534179687500f, +(float16_t)-0.6440429687500f,(float16_t)-0.7651367187500f, +(float16_t)-0.6293945312500f,(float16_t)-0.7768554687500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.6005859375000f,(float16_t)-0.7993164062500f, +(float16_t)-0.5859375000000f,(float16_t)-0.8105468750000f, +(float16_t)-0.5708007812500f,(float16_t)-0.8212890625000f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.5400390625000f,(float16_t)-0.8417968750000f, +(float16_t)-0.5244140625000f,(float16_t)-0.8515625000000f, +(float16_t)-0.5087890625000f,(float16_t)-0.8608398437500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4768066406250f,(float16_t)-0.8789062500000f, +(float16_t)-0.4604492187500f,(float16_t)-0.8876953125000f, +(float16_t)-0.4440917968750f,(float16_t)-0.8959960937500f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.4108886718750f,(float16_t)-0.9116210937500f, +(float16_t)-0.3940429687500f,(float16_t)-0.9189453125000f, +(float16_t)-0.3769531250000f,(float16_t)-0.9262695312500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.3427734375000f,(float16_t)-0.9394531250000f, +(float16_t)-0.3251953125000f,(float16_t)-0.9458007812500f, +(float16_t)-0.3078613281250f,(float16_t)-0.9516601562500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2727050781250f,(float16_t)-0.9619140625000f, +(float16_t)-0.2548828125000f,(float16_t)-0.9667968750000f, +(float16_t)-0.2370605468750f,(float16_t)-0.9716796875000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.2010498046875f,(float16_t)-0.9794921875000f, +(float16_t)-0.1829833984375f,(float16_t)-0.9829101562500f, +(float16_t)-0.1649169921875f,(float16_t)-0.9863281250000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.1285400390625f,(float16_t)-0.9916992187500f, +(float16_t)-0.1102294921875f,(float16_t)-0.9941406250000f, +(float16_t)-0.0919189453125f,(float16_t)-0.9956054687500f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)-0.0552062988281f,(float16_t)-0.9985351562500f, +(float16_t)-0.0368041992188f,(float16_t)-0.9995117187500f, +(float16_t)-0.0184020996094f,(float16_t)-1.0000000000000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9970703125000f,(float16_t)0.0735473632812f, +(float16_t)0.9892578125000f,(float16_t)0.1467285156250f, +(float16_t)0.9755859375000f,(float16_t)0.2191162109375f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.9331054687500f,(float16_t)0.3598632812500f, +(float16_t)0.9038085937500f,(float16_t)0.4274902343750f, +(float16_t)0.8701171875000f,(float16_t)0.4929199218750f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.7885742187500f,(float16_t)0.6152343750000f, +(float16_t)0.7407226562500f,(float16_t)0.6713867187500f, +(float16_t)0.6894531250000f,(float16_t)0.7241210937500f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.5756835937500f,(float16_t)0.8173828125000f, +(float16_t)0.5141601562500f,(float16_t)0.8579101562500f, +(float16_t)0.4497070312500f,(float16_t)0.8930664062500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.3137207031250f,(float16_t)0.9497070312500f, +(float16_t)0.2429199218750f,(float16_t)0.9702148437500f, +(float16_t)0.1710205078125f,(float16_t)0.9853515625000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)0.0245361328125f,(float16_t)0.9995117187500f, +(float16_t)-0.0490722656250f,(float16_t)0.9990234375000f, +(float16_t)-0.1224365234375f,(float16_t)0.9926757812500f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.2666015625000f,(float16_t)0.9638671875000f, +(float16_t)-0.3369140625000f,(float16_t)0.9414062500000f, +(float16_t)-0.4052734375000f,(float16_t)0.9140625000000f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.5351562500000f,(float16_t)0.8447265625000f, +(float16_t)-0.5957031250000f,(float16_t)0.8032226562500f, +(float16_t)-0.6533203125000f,(float16_t)0.7573242187500f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.7573242187500f,(float16_t)0.6533203125000f, +(float16_t)-0.8032226562500f,(float16_t)0.5957031250000f, +(float16_t)-0.8447265625000f,(float16_t)0.5351562500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9140625000000f,(float16_t)0.4052734375000f, +(float16_t)-0.9414062500000f,(float16_t)0.3369140625000f, +(float16_t)-0.9638671875000f,(float16_t)0.2666015625000f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9926757812500f,(float16_t)0.1224365234375f, +(float16_t)-0.9990234375000f,(float16_t)0.0490722656250f, +(float16_t)-0.9995117187500f,(float16_t)-0.0245361328125f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9853515625000f,(float16_t)-0.1710205078125f, +(float16_t)-0.9702148437500f,(float16_t)-0.2429199218750f, +(float16_t)-0.9497070312500f,(float16_t)-0.3137207031250f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.8930664062500f,(float16_t)-0.4497070312500f, +(float16_t)-0.8579101562500f,(float16_t)-0.5141601562500f, +(float16_t)-0.8173828125000f,(float16_t)-0.5756835937500f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.7241210937500f,(float16_t)-0.6894531250000f, +(float16_t)-0.6713867187500f,(float16_t)-0.7407226562500f, +(float16_t)-0.6152343750000f,(float16_t)-0.7885742187500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.4929199218750f,(float16_t)-0.8701171875000f, +(float16_t)-0.4274902343750f,(float16_t)-0.9038085937500f, +(float16_t)-0.3598632812500f,(float16_t)-0.9331054687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)-0.2191162109375f,(float16_t)-0.9755859375000f, +(float16_t)-0.1467285156250f,(float16_t)-0.9892578125000f, +(float16_t)-0.0735473632812f,(float16_t)-0.9970703125000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.9570312500000f,(float16_t)0.2902832031250f, +(float16_t)0.8315429687500f,(float16_t)0.5556640625000f, +(float16_t)0.6342773437500f,(float16_t)0.7729492187500f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)0.0980224609375f,(float16_t)0.9951171875000f, +(float16_t)-0.1950683593750f,(float16_t)0.9809570312500f, +(float16_t)-0.4714355468750f,(float16_t)0.8818359375000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.8818359375000f,(float16_t)0.4714355468750f, +(float16_t)-0.9809570312500f,(float16_t)0.1950683593750f, +(float16_t)-0.9951171875000f,(float16_t)-0.0980224609375f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f, +(float16_t)-0.7729492187500f,(float16_t)-0.6342773437500f, +(float16_t)-0.5556640625000f,(float16_t)-0.8315429687500f, +(float16_t)-0.2902832031250f,(float16_t)-0.9570312500000f, +(float16_t)1.0000000000000f,(float16_t)0.0000000000000f, +(float16_t)0.3825683593750f,(float16_t)0.9238281250000f, +(float16_t)-0.7070312500000f,(float16_t)0.7070312500000f, +(float16_t)-0.9238281250000f,(float16_t)-0.3825683593750f,}; + +#endif + + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /* if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..5251dd3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/CMakeLists.txt @@ -0,0 +1,74 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPComplexMath) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPComplexMath STATIC) + +configLib(CMSISDSPComplexMath ${ROOT}) +configDsp(CMSISDSPComplexMath ${ROOT}) + + +include(interpol) +interpol(CMSISDSPComplexMath) + + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPComplexMath PUBLIC ARM_ALL_FAST_TABLES) +endif() + +# Vectorized code is defining sqrt +# so fast tables required even if Fast Math not built. +if (CONFIGTABLE AND (HELIUM OR MVEF OR MVEI)) + target_compile_definitions(CMSISDSPComplexMath PUBLIC ARM_FAST_ALLOW_TABLES) +endif() + + +# MVE code is using a table for computing the fast sqrt arm_cmplx_mag_q31 +# There is the possibility of not compiling this function and not including +# the table. +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_Q31 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_Q15 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_CMPLX_MAG_FAST_Q15 OR (NOT HELIUM AND NOT MVEI)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_fast_q15.c) +endif() + +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f64.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_q31.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_f32.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_q15.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_q31.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_conj_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_dot_prod_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mag_squared_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_cmplx_f16.c) +target_sources(CMSISDSPComplexMath PRIVATE arm_cmplx_mult_real_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPComplexMath PUBLIC "${DSP}/Include") diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c new file mode 100644 index 0000000..9b46bb3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CompexMathFunctions.c + * Description: Combination of all comlex math function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cmplx_conj_f32.c" +#include "arm_cmplx_conj_q15.c" +#include "arm_cmplx_conj_q31.c" +#include "arm_cmplx_dot_prod_f32.c" +#include "arm_cmplx_dot_prod_q15.c" +#include "arm_cmplx_dot_prod_q31.c" +#include "arm_cmplx_mag_f32.c" +#include "arm_cmplx_mag_f64.c" + +#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + #include "arm_cmplx_mag_q15.c" + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + #include "arm_cmplx_mag_fast_q15.c" + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + #include "arm_cmplx_mag_q31.c" + #endif +#else + #include "arm_cmplx_mag_q15.c" + #include "arm_cmplx_mag_fast_q15.c" + #include "arm_cmplx_mag_q31.c" +#endif + +#include "arm_cmplx_mag_squared_f32.c" +#include "arm_cmplx_mag_squared_f64.c" +#include "arm_cmplx_mag_squared_q15.c" +#include "arm_cmplx_mag_squared_q31.c" +#include "arm_cmplx_mult_cmplx_f32.c" +#include "arm_cmplx_mult_cmplx_f64.c" +#include "arm_cmplx_mult_cmplx_q15.c" +#include "arm_cmplx_mult_cmplx_q31.c" +#include "arm_cmplx_mult_real_f32.c" +#include "arm_cmplx_mult_real_q15.c" +#include "arm_cmplx_mult_real_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c new file mode 100644 index 0000000..d2c7784 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: CompexMathFunctionsF16.c + * Description: Combination of all complex math function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cmplx_conj_f16.c" +#include "arm_cmplx_dot_prod_f16.c" +#include "arm_cmplx_mag_f16.c" +#include "arm_cmplx_mag_squared_f16.c" +#include "arm_cmplx_mult_cmplx_f16.c" +#include "arm_cmplx_mult_real_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c new file mode 100644 index 0000000..6cf871e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f16.c @@ -0,0 +1,185 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f16.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + static const float16_t cmplx_conj_sign[8] = { 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t vecSrc; + f16x8_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f16x8_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -(_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000..5920a77 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,213 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_f32.c + * Description: Floating-point complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_conj Complex Conjugate + + Conjugates the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the destination data where the result should be written. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)  ] =  pSrc[(2*n)  ];    // real part
+      pDst[(2*n)+1] = -pSrc[(2*n)+1];    // imag part
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Floating-point complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + static const float32_t cmplx_conj_sign[4] = { 1.0f, -1.0f, 1.0f, -1.0f }; + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t vecSign; + + /* + * load sign vector + */ + vecSign = *(f32x4_t *) cmplx_conj_sign; + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrc); + vst1q(pDst,vmulq(vecSrc, vecSign)); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt--; + } + + /* Tail */ + blkCnt = (blockSize & 0x3) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t zero; + float32x4x2_t vec; + + zero = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0]+jC[1] = A[0]+(-1)*jA[1] */ + /* Calculate Complex Conjugate and then store the results in the destination buffer. */ + vec = vld2q_f32(pSrc); + vec.val[1] = vsubq_f32(zero,vec.val[1]); + vst2q_f32(pDst,vec); + + /* Increment pointers */ + pSrc += 8; + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 0x3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined (ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c new file mode 100644 index 0000000..fb350a0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q15.c + * Description: Q15 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q15 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF. + */ + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in1; + + q15x8x2_t vecSrc; + q15x8_t zero; + + zero = vdupq_n_s16(0); + + /* Compute 8 real samples at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0xF) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = __SSAT(-in1, 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in1; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in2, in3, in4; /* Temporary input variables */ +#endif + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + +#if defined (ARM_MATH_DSP) + in1 = read_q15x2_ia (&pSrc); + in2 = read_q15x2_ia (&pSrc); + in3 = read_q15x2_ia (&pSrc); + in4 = read_q15x2_ia (&pSrc); + +#ifndef ARM_MATH_BIG_ENDIAN + in1 = __QASX(0, in1); + in2 = __QASX(0, in2); + in3 = __QASX(0, in3); + in4 = __QASX(0, in4); +#else + in1 = __QSAX(0, in1); + in2 = __QSAX(0, in2); + in3 = __QSAX(0, in3); + in4 = __QSAX(0, in4); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16); + in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16); + in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16); + in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16); + + write_q15x2_ia (&pDst, in1); + write_q15x2_ia (&pDst, in2); + write_q15x2_ia (&pDst, in3); + write_q15x2_ia (&pDst, in4); +#else + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + + *pDst++ = *pSrc++; + in1 = *pSrc++; + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in1 = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __SSAT(-in1, 16); +#else + *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c new file mode 100644 index 0000000..ec1b5b7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c @@ -0,0 +1,193 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_conj_q31.c + * Description: Q31 complex conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_conj + @{ + */ + +/** + @brief Q31 complex conjugate. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + + uint32_t blockSize = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31x4x2_t vecSrc; + q31_t in; /* Temporary input variable */ + q31x4_t zero; + + zero = vdupq_n_s32(0); + + + /* Compute 4 real samples at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vld2q(pSrc); + vecSrc.val[1] = vqsubq(zero, vecSrc.val[1]); + vst2q(pDst,vecSrc); + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSize & 0x7) >> 1; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; + *pDst++ = __QSUB(0, in); + + /* Decrement loop counter */ + blkCnt--; + } + + +} +#else + +void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary input variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] + jC[1] = A[0]+ j(-1)A[1] */ + + /* Calculate Complex Conjugate and store result in destination buffer. */ + *pDst++ = *pSrc++; + in = *pSrc++; +#if defined (ARM_MATH_DSP) + *pDst++ = __QSUB(0, in); +#else + *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in; +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_conj group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c new file mode 100644 index 0000000..ff45a9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c @@ -0,0 +1,288 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f16.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + int32_t blkCnt; + float16_t real_sum, imag_sum; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vec_acc = vdupq_n_f16(0.0f16); + f16x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q( pSrcA); + vecSrcB = vld1q( pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f16(0.0f16); + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + + /* Sum the partial parts */ + mve_cmplx_sum_intra_r_i_f16(vec_acc, real_sum, imag_sum); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t numSamples, + float16_t * realResult, + float16_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + _Float16 a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c new file mode 100644 index 0000000..af60d32 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c @@ -0,0 +1,340 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_f32.c + * Description: Floating-point complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_dot_prod Complex Dot Product + + Computes the dot product of two complex vectors. + The vectors are multiplied element-by-element and then summed. + + The pSrcA points to the first complex input vector and + pSrcB points to the second complex input vector. + numSamples specifies the number of complex samples + and the data in each array is stored in an interleaved fashion + (real, imag, real, imag, ...). + Each array has a total of 2*numSamples values. + + The underlying algorithm is used: + + 
+  realResult = 0;
+  imagResult = 0;
+  for (n = 0; n < numSamples; n++) {
+      realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Floating-point complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + int32_t blkCnt; + float32_t real_sum, imag_sum; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vec_acc = vdupq_n_f32(0.0f); + f32x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmlaq(vec_acc, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vec_acc = vcmlaq(vec_acc, vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmlaq_m(vec_acc, vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + + real_sum = vgetq_lane(vec_acc, 0) + vgetq_lane(vec_acc, 2); + imag_sum = vgetq_lane(vec_acc, 1) + vgetq_lane(vec_acc, 3); + + /* + * Store the real and imaginary results in the destination buffers + */ + *realResult = real_sum; + *imagResult = imag_sum; +} + +#else +void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */ + float32_t a0,b0,c0,d0; + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vec1,vec2,vec3,vec4; + float32x4_t accR,accI; + float32x2_t accum = vdup_n_f32(0); + + accR = vdupq_n_f32(0.0f); + accI = vdupq_n_f32(0.0f); + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3U; + + while (blkCnt > 0U) + { + /* C = (A[0]+jA[1])*(B[0]+jB[1]) + ... */ + /* Calculate dot product and then store the result in a temporary buffer. */ + + vec1 = vld2q_f32(pSrcA); + vec2 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec1.val[0],vec2.val[0]); + accR = vmlsq_f32(accR,vec1.val[1],vec2.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec1.val[1],vec2.val[0]); + accI = vmlaq_f32(accI,vec1.val[0],vec2.val[1]); + + vec3 = vld2q_f32(pSrcA); + vec4 = vld2q_f32(pSrcB); + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + accR = vmlaq_f32(accR,vec3.val[0],vec4.val[0]); + accR = vmlsq_f32(accR,vec3.val[1],vec4.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + accI = vmlaq_f32(accI,vec3.val[1],vec4.val[0]); + accI = vmlaq_f32(accI,vec3.val[0],vec4.val[1]); + + /* Decrement the loop counter */ + blkCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR), vget_high_f32(accR)); + real_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI), vget_high_f32(accI)); + imag_sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* Tail */ + blkCnt = numSamples & 0x7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += a0 * c0; + imag_sum += a0 * d0; + real_sum -= b0 * d0; + imag_sum += b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in destination buffer. */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c new file mode 100644 index 0000000..1910d8a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q15.c + * Description: Processing function for the Q15 Complex Dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q15 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned her + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result. + These are accumulated in a 64-bit accumulator with 34.30 precision. + As a final step, the accumulators are converted to 8.24 format. + The return results realResult and imagResult are in 8.24 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vmlsldavaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vmlsldavaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vmlaldavaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + accReal = vmlsldavaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vmlaldavaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); +} +#else +void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q15_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += (q31_t)a0 * c0; + imag_sum += (q31_t)a0 * d0; + real_sum -= (q31_t)b0 * d0; + imag_sum += (q31_t)b0 * c0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 8.24 format */ + /* Convert real data in 34.30 to 8.24 by 6 right shifts */ + *realResult = (q31_t) (real_sum >> 6); + /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */ + *imagResult = (q31_t) (imag_sum >> 6); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c new file mode 100644 index 0000000..fac85bd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c @@ -0,0 +1,259 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_dot_prod_q31.c + * Description: Q31 complex dot product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_dot_prod + @{ + */ + +/** + @brief Q31 complex dot product. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] numSamples number of samples in each vector + @param[out] realResult real part of the result returned here + @param[out] imagResult imaginary part of the result returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format. + The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits. + Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768. + The return results realResult and imagResult are in 16.48 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + int32_t blkCnt; + q63_t accReal = 0LL; + q63_t accImag = 0LL; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + accReal = vrmlsldavhaq(accReal, vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + accReal = vrmlsldavhaq(accReal, vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + + accImag = vrmlaldavhaxq(accImag, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + accReal = vrmlsldavhaq_p(accReal, vecSrcA, vecSrcB, p); + accImag = vrmlaldavhaxq_p(accImag, vecSrcA, vecSrcB, p); + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + } + *realResult = asrl(accReal, (14 - 8)); + *imagResult = asrl(accImag, (14 - 8)); + +} + +#else +void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */ + q31_t a0,b0,c0,d0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + a0 = *pSrcA++; + b0 = *pSrcA++; + c0 = *pSrcB++; + d0 = *pSrcB++; + + real_sum += ((q63_t)a0 * c0) >> 14; + imag_sum += ((q63_t)a0 * d0) >> 14; + real_sum -= ((q63_t)b0 * d0) >> 14; + imag_sum += ((q63_t)b0 * c0) >> 14; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store real and imaginary result in 16.48 format */ + *realResult = real_sum; + *imagResult = imag_sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_dot_prod group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c new file mode 100644 index 0000000..1f93598 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c @@ -0,0 +1,241 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f16.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0f, vcmpltq(invSqrt, (float16_t)0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_f16(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + q15x8_t newtonStartVec; + f16x8_t sumHalf, invSqrt; + + vecSrc = vld2q((float16_t const *)pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s16(INVSQRT_MAGIC_F16) - vshrq((q15x8_t) sum, 1); + sumHalf = vmulq(sum, (float16_t)0.5); + /* + * compute 2 x iterations + */ + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, (f16x8_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F16(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, (float16_t)0.0, vcmpltq(invSqrt, (float16_t)0.0)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vstrhq_p_f16(pDst, sum, p0); + } +} + +#else +void arm_cmplx_mag_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + _Float16 real, imag; /* Temporary variables to hold input values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f16((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c new file mode 100644 index 0000000..aac6fba --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c @@ -0,0 +1,273 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f32.c + * Description: Floating-point complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary variables to hold input values */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + q31x4_t newtonStartVec; + f32x4_t sumHalf, invSqrt; + + vecSrc = vld2q(pSrc); + pSrc += 8; + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + + /* + * inlined Fast SQRT using inverse SQRT newton-raphson method + */ + + /* compute initial value */ + newtonStartVec = vdupq_n_s32(INVSQRT_MAGIC_F32) - vshrq((q31x4_t) sum, 1); + sumHalf = sum * 0.5f; + /* + * compute 3 x iterations + * + * The more iterations, the more accuracy. + * If you need to trade a bit of accuracy for more performance, + * you can comment out the 3rd use of the macro. + */ + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, (f32x4_t) newtonStartVec); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + INVSQRT_NEWTON_MVE_F32(invSqrt, sumHalf, invSqrt); + /* + * set negative values to 0 + */ + invSqrt = vdupq_m(invSqrt, 0.0f, vcmpltq(invSqrt, 0.0f)); + /* + * sqrt(x) = x * invSqrt(x) + */ + sum = vmulq(sum, invSqrt); + vst1q(pDst, sum); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float32_t real, imag; /* Temporary variables to hold input values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqA)); + pDst += 4; + + vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqB)); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + real = *pSrc++; + imag = *pSrc++; + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + arm_sqrt_f32((real * real) + (imag * imag), pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c new file mode 100644 index 0000000..c2bcd56 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f64.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_f64.c + * Description: Floating-point complex magnitude + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag Complex Magnitude + + Computes the magnitude of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Floating-point complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* loop counter */ + float64_t real, imag; /* Temporary variables to hold input values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = sqrt((real * real) + (imag * imag)); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c new file mode 100644 index 0000000..eac2a14 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_fast_q15.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_fast_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + Fast functions are less accurate. This function will tend to clamp to 0 + the too small values. So sqrt(x*x) = x will not always be true. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q15x8_t sum; + q31_t in; + q31_t acc0; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + sum = FAST_VSQRT_Q15(sum); + + vst1q(pDst, sum); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_fast_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c new file mode 100644 index 0000000..10ce335 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c @@ -0,0 +1,268 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q15.c + * Description: Q15 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q15 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format. + */ + +/* Sqrt q31 is used otherwise accuracy is not good enough + for small values and for some applications it is + an issue. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q15x8x2_t vecSrc; + q31x4_t prod0; + q31x4_t prod1; + + q31_t in; + q31_t acc0; + q31x4_t acc0V; + q31x4_t acc1V; + + q31_t res; + q15x8_t resV; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + pSrc += 16; + + acc0V = vdupq_n_s32(0); + acc1V = vdupq_n_s32(0); + + prod0 = vmullbq_int_s16(vecSrc.val[0], vecSrc.val[0]); + acc0V = vqaddq_s32(acc0V,prod0); + + prod0 = vmullbq_int_s16(vecSrc.val[1], vecSrc.val[1]); + acc0V = vqaddq_s32(acc0V,prod0); + + + prod1 = vmulltq_int_s16(vecSrc.val[0], vecSrc.val[0]); + acc1V = vqaddq_s32(acc1V,prod1); + + prod1 = vmulltq_int_s16(vecSrc.val[1], vecSrc.val[1]); + acc1V = vqaddq_s32(acc1V,prod1); + + + + acc0V = vshrq(acc0V, 1); + acc1V = vshrq(acc1V, 1); + + acc0V = FAST_VSQRT_Q31(acc0V); + acc1V = FAST_VSQRT_Q31(acc1V); + + resV = vdupq_n_s16(0); + resV = vqshrnbq_n_s32(resV,acc0V,16); + resV = vqshrntq_n_s32(resV,acc1V,16); + + vst1q(pDst, resV); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + q31_t res; /* temporary result */ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31(acc0 >> 1 , &res); + *pDst++ = res >> 16; +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 2.14 format in destination buffer. */ + arm_sqrt_q31((acc0 + acc1) >> 1 , &res); + *pDst++ = res >> 16; + +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c new file mode 100644 index 0000000..57a72f5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_q31.c + * Description: Q31 complex magnitude + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag + @{ + */ + +/** + @brief Q31 complex magnitude. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + + q31x4x2_t vecSrc; + q31x4_t sum; + + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + + sum = vqaddq(vmulhq(vecSrc.val[0], vecSrc.val[0]), + vmulhq(vecSrc.val[1], vecSrc.val[1])); + + sum = vshrq(sum, 1); + + /* + + This function is using a table. There are compilations flags to avoid + including this table (and in this case, arm_cmplx_maq_q31 must not + be built and linked.) + + */ + sum = FAST_VSQRT_Q31(sum); + + vst1q(pDst, sum); + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pSrc += 8; + pDst += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 2.30 format in destination buffer. */ + arm_sqrt_q31(acc0 + acc1, pDst++); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c new file mode 100644 index 0000000..df3cbec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f16.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + f16x8x2_t vecSrc; + f16x8_t sum; + + /* Compute 4 complex samples at a time */ + while (blockSize > 0) + { + mve_pred16_t p = vctp16q(blockSize); + vecSrc = vld2q(pSrc); + sum = vmulq_m(vuninitializedq_f16(),vecSrc.val[0], vecSrc.val[0],p); + sum = vfmaq_m(sum, vecSrc.val[1], vecSrc.val[1],p); + vstrhq_p_f16(pDst, sum,p); + + pSrc += 16; + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blockSize-= 8; + } + +} + +#else +void arm_cmplx_mag_squared_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 real, imag; /* Temporary input variables */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c new file mode 100644 index 0000000..861585f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f32.c + * Description: Floating-point complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup cmplx_mag_squared Complex Magnitude Squared + + Computes the magnitude squared of the elements of a complex data vector. + + The pSrc points to the source data and + pDst points to the where the result should be written. + numSamples specifies the number of complex samples + in the input array and the data is stored in an interleaved fashion + (real, imag, real, imag, ...). + The input array has a total of 2*numSamples values; + the output array has a total of numSamples values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + f32x4x2_t vecSrc; + f32x4_t sum; + float32_t real, imag; /* Temporary input variables */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + sum = vmulq(vecSrc.val[0], vecSrc.val[0]); + sum = vfmaq(sum, vecSrc.val[1], vecSrc.val[1]); + vst1q(pDst, sum); + + pSrc += 8; + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t real, imag; /* Temporary input variables */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t vecA; + float32x4_t vRealA; + float32x4_t vImagA; + float32x4_t vMagSqA; + + float32x4x2_t vecB; + float32x4_t vRealB; + float32x4_t vImagB; + float32x4_t vMagSqB; + + /* Loop unrolling: Compute 8 outputs at a time */ + blkCnt = numSamples >> 3; + + while (blkCnt > 0U) + { + /* out = sqrt((real * real) + (imag * imag)) */ + + vecA = vld2q_f32(pSrc); + pSrc += 8; + + vRealA = vmulq_f32(vecA.val[0], vecA.val[0]); + vImagA = vmulq_f32(vecA.val[1], vecA.val[1]); + vMagSqA = vaddq_f32(vRealA, vImagA); + + vecB = vld2q_f32(pSrc); + pSrc += 8; + + vRealB = vmulq_f32(vecB.val[0], vecB.val[0]); + vImagB = vmulq_f32(vecB.val[1], vecB.val[1]); + vMagSqB = vaddq_f32(vRealB, vImagB); + + /* Store the result in the destination buffer. */ + vst1q_f32(pDst, vMagSqA); + pDst += 4; + + vst1q_f32(pDst, vMagSqB); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + blkCnt = numSamples & 7; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + real = *pSrc++; + imag = *pSrc++; + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c new file mode 100644 index 0000000..fde0321 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f64.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_f64.c + * Description: Floating-point complex magnitude squared + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Floating-point complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ +void arm_cmplx_mag_squared_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t real, imag; /* Temporary input variables */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + + /* store result in destination buffer. */ + *pDst++ = (real * real) + (imag * imag); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c new file mode 100644 index 0000000..727699e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q15.c + * Description: Q15 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q15 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31_t in; + q31_t acc0; /* Accumulators */ + q15x8x2_t vecSrc; + q15x8_t vReal, vImag; + q15x8_t vMagSq; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 16; + pDst += 8; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + in = read_q15x2_ia ((q15_t **) &pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_DSP) + q31_t in; + q31_t acc0; /* Accumulators */ +#else + q15_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); + + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); + + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + +#if defined (ARM_MATH_DSP) + in = read_q15x2_ia (&pSrc); + acc0 = __SMUAD(in, in); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (acc0 >> 17); +#else + real = *pSrc++; + imag = *pSrc++; + acc0 = ((q31_t) real * real); + acc1 = ((q31_t) imag * imag); + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c new file mode 100644 index 0000000..4ccde36 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mag_squared_q31.c + * Description: Q31 complex magnitude squared + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup cmplx_mag_squared + @{ + */ + +/** + @brief Q31 complex magnitude squared. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blockSize = numSamples; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t vecSrc; + q31x4_t vReal, vImag; + q31x4_t vMagSq; + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + + /* Compute 4 complex samples at a time */ + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vld2q(pSrc); + vReal = vmulhq(vecSrc.val[0], vecSrc.val[0]); + vImag = vmulhq(vecSrc.val[1], vecSrc.val[1]); + vMagSq = vqaddq(vReal, vImag); + vMagSq = vshrq(vMagSq, 1); + + vst1q(pDst, vMagSq); + + pSrc += 8; + pDst += 4; + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + blkCnt --; + } + + /* Tail */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t real, imag; /* Temporary input variables */ + q31_t acc0, acc1; /* Accumulators */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + /* store the result in 3.29 format in the destination buffer. */ + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[0] = (A[0] * A[0] + A[1] * A[1]) */ + + real = *pSrc++; + imag = *pSrc++; + acc0 = (q31_t) (((q63_t) real * real) >> 33); + acc1 = (q31_t) (((q63_t) imag * imag) >> 33); + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = acc0 + acc1; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of cmplx_mag_squared group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c new file mode 100644 index 0000000..68e1d1b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c @@ -0,0 +1,271 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f16.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f16x8_t vecSrcA, vecSrcB; + f16x8_t vecSrcC, vecSrcD; + f16x8_t vec_acc; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + vst1q(pDst, vec_acc); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 8; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + blkCnt -= 8; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_f16(pSrcA, p); + vecSrcB = vldrhq_z_f16(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f16(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrhq_p_f16(pDst, vec_acc, p); + pDst += 8; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + } + +} + + +#else +void arm_cmplx_mult_cmplx_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + float16_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c new file mode 100644 index 0000000..5d2c66c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c @@ -0,0 +1,305 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f32.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication + + Multiplies a complex vector by another complex vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+      pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + f32x4_t vecSrcA, vecSrcB; + f32x4_t vecSrcC, vecSrcD; + f32x4_t vec_acc; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + vst1q(pDst, vec_acc); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vec_acc = vcmulq(vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vec_acc = vcmlaq_rot90(vec_acc, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + vst1q(pDst, vec_acc); + pDst += 4; + + vec_acc = vcmulq(vecSrcC, vecSrcD); + vec_acc = vcmlaq_rot90(vec_acc, vecSrcC, vecSrcD); + vst1q(pDst, vec_acc); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + blkCnt -= 4; + } + } else { + /* small vector */ + blkCnt = numSamples * CMPLX_DIM; + vec_acc = vdupq_n_f32(0.0f); + + do { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_f32(pSrcA, p); + vecSrcB = vldrwq_z_f32(pSrcB, p); + + vec_acc = vcmulq_m(vuninitializedq_f32(),vecSrcA, vecSrcB, p); + vec_acc = vcmlaq_rot90_m(vec_acc, vecSrcA, vecSrcB, p); + vstrwq_p_f32(pDst, vec_acc, p); + pDst += 4; + + /* + * Decrement the blkCnt loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + } + +} + +#else +void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4x2_t va, vb; + float32x4x2_t outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + va = vld2q_f32(pSrcA); // load & separate real/imag pSrcA (de-interleave 2) + vb = vld2q_f32(pSrcB); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcA += 8; + pSrcB += 8; + + /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */ + outCplx.val[0] = vmulq_f32(va.val[0], vb.val[0]); + outCplx.val[0] = vmlsq_f32(outCplx.val[0], va.val[1], vb.val[1]); + + /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */ + outCplx.val[1] = vmulq_f32(va.val[0], vb.val[1]); + outCplx.val[1] = vmlaq_f32(outCplx.val[1], va.val[1], vb.val[0]); + + vst2q_f32(pDst, outCplx); + + /* Increment pointer */ + pDst += 8; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; + +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c new file mode 100644 index 0000000..75a044c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f64.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_f64.c + * Description: Floating-point complex-by-complex multiplication + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Floating-point complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +void arm_cmplx_mult_cmplx_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + float64_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t a, b, c, d; /* Temporary variables to store real and imaginary values */ + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in destination buffer. */ + *pDst++ = (a * c) - (b * d); + *pDst++ = (a * d) + (b * c); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c new file mode 100644 index 0000000..53fbe58 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c @@ -0,0 +1,258 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q15.c + * Description: Q15 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q15 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q15x8_t vecSrcA, vecSrcB; + q15x8_t vecSrcC, vecSrcD; + q15x8_t vecDst; + + blkCnt = (numSamples >> 3); + blkCnt -= 1; + if (blkCnt > 0) + { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 8; + pSrcB += 8; + + while (blkCnt > 0) + { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 8; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 8; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 8; + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + vecDst = vqdmlsdhq(vuninitializedq_s16(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vstrhq_s16(pDst, vshrq(vecDst, 2)); + pDst += 8; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 7); + do + { + mve_pred16_t p = vctp16q(blkCnt); + + pSrcA += 8; + pSrcB += 8; + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + pDst += 8; + + blkCnt -= 8; + } + while ((int32_t) blkCnt > 0); + } + else + { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrcA = vldrhq_z_s16(pSrcA, p); + vecSrcB = vldrhq_z_s16(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s16(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s16(), vecDst, 2, p); + vstrhq_p_s16(pDst, vecDst, p); + + pDst += 8; + pSrcA += 8; + pSrcB += 8; + + blkCnt -= 8; + } + } +} +#else +void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.13 format in destination buffer. */ + *pDst++ = (q15_t) ( (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17) ); + *pDst++ = (q15_t) ( (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c new file mode 100644 index 0000000..7f94561 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c @@ -0,0 +1,253 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_cmplx_q31.c + * Description: Q31 complex-by-complex multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByCmplxMult + @{ + */ + +/** + @brief Q31 complex-by-complex multiplication. + @param[in] pSrcA points to first input vector + @param[in] pSrcB points to second input vector + @param[out] pDst points to output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format. + Input down scaling is not required. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + int32_t blkCnt; + q31x4_t vecSrcA, vecSrcB; + q31x4_t vecSrcC, vecSrcD; + q31x4_t vecDst; + + blkCnt = numSamples >> 2; + blkCnt -= 1; + if (blkCnt > 0) { + /* should give more freedom to generate stall free code */ + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + pSrcA += 4; + pSrcB += 4; + + while (blkCnt > 0) { + + /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + pSrcA += 4; + + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */ + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecSrcA = vld1q(pSrcA); + pSrcA += 4; + + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + vecSrcB = vld1q(pSrcB); + pSrcB += 4; + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* process last elements out of the loop avoid the armclang breaking the SW pipeline */ + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcA, vecSrcB); + vecSrcC = vld1q(pSrcA); + + vecDst = vqdmladhxq(vecDst, vecSrcA, vecSrcB); + vecSrcD = vld1q(pSrcB); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + vecDst = vqdmlsdhq(vuninitializedq_s32(), vecSrcC, vecSrcD); + vecDst = vqdmladhxq(vecDst, vecSrcC, vecSrcD); + + vst1q(pDst, vshrq(vecDst, 2)); + pDst += 4; + + /* + * tail + */ + blkCnt = CMPLX_DIM * (numSamples & 3); + do { + mve_pred16_t p = vctp32q(blkCnt); + + pSrcA += 4; + pSrcB += 4; + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + pDst += 4; + + blkCnt -= 4; + } + while ((int32_t) blkCnt > 0); + } else { + blkCnt = numSamples * CMPLX_DIM; + while (blkCnt > 0) { + mve_pred16_t p = vctp32q(blkCnt); + + vecSrcA = vldrwq_z_s32(pSrcA, p); + vecSrcB = vldrwq_z_s32(pSrcB, p); + + vecDst = vqdmlsdhq_m(vuninitializedq_s32(), vecSrcA, vecSrcB, p); + vecDst = vqdmladhxq_m(vecDst, vecSrcA, vecSrcB, p); + + vecDst = vshrq_m(vuninitializedq_s32(), vecDst, 2, p); + vstrwq_p_s32(pDst, vecDst, p); + + pDst += 4; + pSrcA += 4; + pSrcB += 4; + + blkCnt -= 4; + } + } +} +#else +void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t a, b, c, d; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */ + /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */ + + a = *pSrcA++; + b = *pSrcA++; + c = *pSrcB++; + d = *pSrcB++; + + /* store result in 3.29 format in destination buffer. */ + *pDst++ = (q31_t) ( (((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33) ); + *pDst++ = (q31_t) ( (((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33) ); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByCmplxMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c new file mode 100644 index 0000000..f5909fc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f16.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f16.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f16x8_t rVec; + f16x8_t cmplxVec; + f16x8_t dstVec; + uint16x8_t strideVec; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_16); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 3; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt--; + } + + blkCnt = blockSizeC & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_f16(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vstrhq_p_f16(pCmplxDst, dstVec, p0); + } +} + +#else +void arm_cmplx_mult_real_f16( + const float16_t * pSrcCmplx, + const float16_t * pSrcReal, + float16_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + in = *pSrcReal++; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + *pCmplxDst++ = (_Float16)*pSrcCmplx++ * (_Float16)in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c new file mode 100644 index 0000000..bc0f59b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_f32.c + * Description: Floating-point complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @defgroup CmplxByRealMult Complex-by-Real Multiplication + + Multiplies a complex vector by a real vector and generates a complex result. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + The parameter numSamples represents the number of complex + samples processed. The complex arrays have a total of 2*numSamples + real values while the real array has a total of numSamples + real values. + + The underlying algorithm is used: + + 
+  for (n = 0; n < numSamples; n++) {
+      pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+      pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+  }
+
+ + There are separate functions for floating-point, Q15, and Q31 data types. + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Floating-point complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint32_t stride_cmplx_x_real_32[4] = { 0, 0, 1, 1 }; + + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + f32x4_t rVec; + f32x4_t cmplxVec; + f32x4_t dstVec; + uint32x4_t strideVec; + float32_t in; + + + /* stride vector for pairs of real generation */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_f32(pSrcReal, strideVec); + dstVec = vmulq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt--; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t in; /* Temporary variable */ + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + float32x4_t r; + float32x4x2_t ab,outCplx; + + /* Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + ab = vld2q_f32(pSrcCmplx); // load & separate real/imag pSrcA (de-interleave 2) + r = vld1q_f32(pSrcReal); // load & separate real/imag pSrcB + + /* Increment pointers */ + pSrcCmplx += 8; + pSrcReal += 4; + + outCplx.val[0] = vmulq_f32(ab.val[0], r); + outCplx.val[1] = vmulq_f32(ab.val[1], r); + + vst2q_f32(pCmplxDst, outCplx); + pCmplxDst += 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = numSamples & 3; +#else +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + in = *pSrcReal++; + *pCmplxDst++ = *pSrcCmplx++* in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store result in destination buffer. */ + *pCmplxDst++ = *pSrcCmplx++ * in; + *pCmplxDst++ = *pSrcCmplx++ * in; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c new file mode 100644 index 0000000..84e5ae3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c @@ -0,0 +1,238 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q15.c + * Description: Q15 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q15 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + static const uint16_t stride_cmplx_x_real_16[8] = { + 0, 0, 1, 1, 2, 2, 3, 3 + }; + q15x8_t rVec; + q15x8_t cmplxVec; + q15x8_t dstVec; + uint16x8_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q15_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_16); + + blkCnt = blockSizeC >> 3; + + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrhq_gather_shifted_offset_s16(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 4; + pSrcCmplx += 8; + pCmplxDst += 8; + blkCnt --; + } + + /* Tail */ + blkCnt = (blockSizeC & 7) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q15_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + +#if defined (ARM_MATH_DSP) + q31_t inA1, inA2; /* Temporary variables to hold input data */ + q31_t inB1; /* Temporary variables to hold input data */ + q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */ + q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */ +#endif + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + +#if defined (ARM_MATH_DSP) + /* read 2 complex numbers both real and imaginary from complex input buffer */ + inA1 = read_q15x2_ia (&pSrcCmplx); + inA2 = read_q15x2_ia (&pSrcCmplx); + /* read 2 real values at a time from real input buffer */ + inB1 = read_q15x2_ia (&pSrcReal); + + /* multiply complex number with real numbers */ +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* saturate the result */ + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + /* pack real and imaginary outputs and store them to destination */ + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); + + inA1 = read_q15x2_ia (&pSrcCmplx); + inA2 = read_q15x2_ia (&pSrcCmplx); + inB1 = read_q15x2_ia (&pSrcReal); + +#ifndef ARM_MATH_BIG_ENDIAN + mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1)); + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1)); + mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16)); +#else + mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16)); + mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + out1 = (q15_t) __SSAT(mul1 >> 15U, 16); + out2 = (q15_t) __SSAT(mul2 >> 15U, 16); + out3 = (q15_t) __SSAT(mul3 >> 15U, 16); + out4 = (q15_t) __SSAT(mul4 >> 15U, 16); + + write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16)); + write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16)); +#else + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + in = *pSrcReal++; + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store the result in the destination buffer. */ + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c new file mode 100644 index 0000000..de13757 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mult_real_q31.c + * Description: Q31 complex by real multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/complex_math_functions.h" + +/** + @ingroup groupCmplxMath + */ + +/** + @addtogroup CmplxByRealMult + @{ + */ + +/** + @brief Q31 complex-by-real multiplication. + @param[in] pSrcCmplx points to complex input vector + @param[in] pSrcReal points to real input vector + @param[out] pCmplxDst points to complex output vector + @param[in] numSamples number of samples in each vector + @return none + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + + static const uint32_t stride_cmplx_x_real_32[4] = { + 0, 0, 1, 1 + }; + q31x4_t rVec; + q31x4_t cmplxVec; + q31x4_t dstVec; + uint32x4_t strideVec; + uint32_t blockSizeC = numSamples * CMPLX_DIM; /* loop counters */ + uint32_t blkCnt; + q31_t in; + + /* + * stride vector for pairs of real generation + */ + strideVec = vld1q(stride_cmplx_x_real_32); + + /* Compute 4 complex outputs at a time */ + blkCnt = blockSizeC >> 2; + while (blkCnt > 0U) + { + cmplxVec = vld1q(pSrcCmplx); + rVec = vldrwq_gather_shifted_offset_s32(pSrcReal, strideVec); + dstVec = vqdmulhq(cmplxVec, rVec); + vst1q(pCmplxDst, dstVec); + + pSrcReal += 2; + pSrcCmplx += 4; + pCmplxDst += 4; + blkCnt --; + } + + blkCnt = (blockSizeC & 3) >> 1; + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t in; /* Temporary variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C[2 * i ] = A[2 * i ] * B[i]. */ + /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */ + + in = *pSrcReal++; +#if defined (ARM_MATH_DSP) + /* store saturated result in 1.31 format to destination buffer */ + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); + *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1); +#else + /* store result in destination buffer. */ + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); + *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of CmplxByRealMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt new file mode 100644 index 0000000..12dedb4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPController) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPController STATIC) + +configLib(CMSISDSPController ${ROOT}) +configDsp(CMSISDSPController ${ROOT}) + +include(interpol) +interpol(CMSISDSPController) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPController PUBLIC ARM_ALL_FAST_TABLES) +endif() + +target_sources(CMSISDSPController PRIVATE arm_pid_init_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_init_q31.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_f32.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q15.c) +target_sources(CMSISDSPController PRIVATE arm_pid_reset_q31.c) + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_F32) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_COS_Q31) +target_sources(CMSISDSPController PRIVATE arm_sin_cos_q31.c) +endif() + + + +### Includes +target_include_directories(CMSISDSPController PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c new file mode 100644 index 0000000..9abd328 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: ControllerFunctions.c + * Description: Combination of all controller function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_pid_init_f32.c" +#include "arm_pid_init_q15.c" +#include "arm_pid_init_q31.c" +#include "arm_pid_reset_f32.c" +#include "arm_pid_reset_q15.c" +#include "arm_pid_reset_q31.c" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_sin_cos_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_sin_cos_q31.c" +#endif + +#endif diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c new file mode 100644 index 0000000..384994b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_f32.c + * Description: Floating-point PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] S points to an instance of the PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag) +{ + /* Derived coefficient A0 */ + S->A0 = S->Kp + S->Ki + S->Kd; + + /* Derived coefficient A1 */ + S->A1 = (-S->Kp) - ((float32_t) 2.0f * S->Kd); + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c new file mode 100644 index 0000000..e1f510b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q15.c + * Description: Q15 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd); + + /* Derived coefficients and pack into A1 */ + +#ifndef ARM_MATH_BIG_ENDIAN + S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16); +#else + S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16); +#endif + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = S->Kp + S->Ki + S->Kd; + S->A0 = (q15_t) __SSAT(temp, 16); + + /* Derived coefficients and pack into A1 */ + temp = -(S->Kd + S->Kd + S->Kp); + S->A1 = (q15_t) __SSAT(temp, 16); + S->A2 = S->Kd; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c new file mode 100644 index 0000000..53df5ee --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_init_q31.c + * Description: Q31 PID Control initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @param[in] resetStateFlag + - value = 0: no change in state + - value = 1: reset state + @return none + + @par Details + The resetStateFlag specifies whether to set state to zero or not. \n + The function computes the structure fields: A0, A1 A2 + using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd) + also sets the state variables to all zeros. + */ + +void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag) +{ + +#if defined (ARM_MATH_DSP) + + /* Derived coefficient A0 */ + S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd); + + /* Derived coefficient A1 */ + S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp); + +#else + + q31_t temp; /* to store the sum */ + + /* Derived coefficient A0 */ + temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki); + S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd); + + /* Derived coefficient A1 */ + temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); + S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Derived coefficient A2 */ + S->A2 = S->Kd; + + /* Check whether state needs reset or not */ + if (resetStateFlag) + { + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); + } + +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c new file mode 100644 index 0000000..cb267ad --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_f32.c + * Description: Floating-point PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] S points to an instance of the floating-point PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_f32( + arm_pid_instance_f32 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(float32_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c new file mode 100644 index 0000000..aa4076e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q15.c + * Description: Q15 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q15( + arm_pid_instance_q15 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q15_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c new file mode 100644 index 0000000..3e9c39f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_pid_reset_q31.c + * Description: Q31 PID Control reset function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" + +/** + @addtogroup PID + @{ + */ + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID structure + @return none + + @par Details + The function resets the state buffer to zeros. + */ + +void arm_pid_reset_q31( + arm_pid_instance_q31 * S) +{ + /* Reset state to zero, The size will be always 3 samples */ + memset(S->state, 0, 3U * sizeof(q31_t)); +} + +/** + @} end of PID group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c new file mode 100644 index 0000000..e6d9d90 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_f32.c + * Description: Sine and Cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @defgroup SinCos Sine Cosine + + Computes the trigonometric sine and cosine values using a combination of table lookup + and linear interpolation. + There are separate functions for Q31 and floating-point data types. + The input to the floating-point version is in degrees while the + fixed-point Q31 have a scaled input with the range + [-1 0.9999] mapping to [-180 +180] degrees. + + The floating point function also allows values that are out of the usual range. When this happens, the function will + take extra time to adjust the input value to the range of [-180 180]. + + The result is accurate to 5 digits after the decimal point. + + The implementation is based on table lookup using 360 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index. + -# Compute the fractional portion (fract) of the input. + -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1. + -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)). + -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1. + -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)). + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + */ + +void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal) +{ + float32_t fract, in; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + float32_t f1, f2, d1, d2; /* Two nearest output values */ + float32_t Dn, Df; + float32_t temp, findex; + + /* input x is in degrees */ + /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */ + in = theta * 0.00277777777778f; + + if (in < 0.0f) + { + in = -in; + } + + in = in - (int32_t)in; + + /* Calculate the nearest index */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + indexS = ((uint16_t)findex) & 0x1ff; + indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff; + + /* Calculation of fractional value */ + fract = findex - (float32_t) indexS; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexC ]; + f2 = sinTable_f32[indexC+1]; + d1 = -sinTable_f32[indexS ]; + d2 = -sinTable_f32[indexS+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of cosine value */ + *pCosVal = fract * temp + f1; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_f32[indexS ]; + f2 = sinTable_f32[indexS+1]; + d1 = sinTable_f32[indexC ]; + d2 = sinTable_f32[indexC+1]; + + temp = (1.0f - fract) * f1 + fract * f2; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * (d1 + d2) - 2 * Df; + temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn); + temp = fract * temp + d1 * Dn; + + /* Calculation of sine value */ + *pSinVal = fract * temp + f1; + + if (theta < 0.0f) + { + *pSinVal = -*pSinVal; + } +} + +/** + @} end of SinCos group + */ diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c new file mode 100644 index 0000000..990c891 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_cos_q31.c + * Description: Cosine & Sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/controller_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupController + */ + +/** + @addtogroup SinCos + @{ + */ + +/** + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] pSinVal points to processed sine output + @param[out] pCosVal points to processed cosine output + @return none + + The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179]. + */ + +void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal) +{ + q31_t fract; /* Temporary input, output variables */ + uint16_t indexS, indexC; /* Index variable */ + q31_t f1, f2, d1, d2; /* Two nearest output values */ + q31_t Dn, Df; + q63_t temp; + + /* Calculate the nearest index */ + indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT; + indexC = (indexS + 128) & 0x1ff; + + /* Calculation of fractional value */ + fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8; + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexC ]; + f2 = sinTable_q31[indexC+1]; + d1 = -sinTable_q31[indexS ]; + d2 = -sinTable_q31[indexS+1]; + + Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */ + Df = f2 - f1; /* delta between the values of the functions */ + + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of cosine value */ + *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); + + /* Read two nearest values of input value from the cos & sin tables */ + f1 = sinTable_q31[indexS ]; + f2 = sinTable_q31[indexS+1]; + d1 = sinTable_q31[indexC ]; + d2 = sinTable_q31[indexC+1]; + + Df = f2 - f1; // delta between the values of the functions + temp = Dn * ((q63_t)d1 + d2); + temp = temp - ((q63_t)Df << 32); + temp = (q63_t)fract * (temp >> 31); + temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn); + temp = (q63_t)fract * (temp >> 31); + temp = temp + (q63_t)d1 * Dn; + temp = (q63_t)fract * (temp >> 31); + + /* Calculation of sine value */ + *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1); +} + +/** + @} end of SinCos group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt new file mode 100644 index 0000000..0cfd1c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/CMakeLists.txt @@ -0,0 +1,56 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPDistance) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPDistance STATIC) + +target_sources(CMSISDSPDistance PRIVATE arm_boolean_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_braycurtis_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_canberra_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_correlation_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_dice_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f64.c) +target_sources(CMSISDSPDistance PRIVATE arm_hamming_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_jaccard_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_jensenshannon_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_kulsinski_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_minkowski_distance_f32.c) +target_sources(CMSISDSPDistance PRIVATE arm_rogerstanimoto_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_russellrao_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_sokalmichener_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_sokalsneath_distance.c) +target_sources(CMSISDSPDistance PRIVATE arm_yule_distance.c) + + +configLib(CMSISDSPDistance ${ROOT}) +configDsp(CMSISDSPDistance ${ROOT}) + +### Includes +target_include_directories(CMSISDSPDistance PUBLIC "${DSP}/Include") +target_include_directories(CMSISDSPDistance PRIVATE ".") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPDistance PRIVATE arm_braycurtis_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_canberra_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_chebyshev_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_cityblock_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_correlation_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_cosine_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_euclidean_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_jensenshannon_distance_f16.c) +target_sources(CMSISDSPDistance PRIVATE arm_minkowski_distance_f16.c) +endif() + + \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c new file mode 100644 index 0000000..0abcbc5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctions.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all distance function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_boolean_distance.c" +#include "arm_braycurtis_distance_f32.c" +#include "arm_canberra_distance_f32.c" +#include "arm_chebyshev_distance_f32.c" +#include "arm_chebyshev_distance_f64.c" +#include "arm_cityblock_distance_f32.c" +#include "arm_cityblock_distance_f64.c" +#include "arm_correlation_distance_f32.c" +#include "arm_cosine_distance_f32.c" +#include "arm_cosine_distance_f64.c" +#include "arm_dice_distance.c" +#include "arm_euclidean_distance_f32.c" +#include "arm_euclidean_distance_f64.c" +#include "arm_hamming_distance.c" +#include "arm_jaccard_distance.c" +#include "arm_jensenshannon_distance_f32.c" +#include "arm_kulsinski_distance.c" +#include "arm_minkowski_distance_f32.c" +#include "arm_rogerstanimoto_distance.c" +#include "arm_russellrao_distance.c" +#include "arm_sokalmichener_distance.c" +#include "arm_sokalsneath_distance.c" +#include "arm_yule_distance.c" diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c new file mode 100644 index 0000000..a0be2d4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/DistanceFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: DistanceFunctions.c + * Description: Combination of all distance function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_braycurtis_distance_f16.c" +#include "arm_canberra_distance_f16.c" +#include "arm_chebyshev_distance_f16.c" +#include "arm_cityblock_distance_f16.c" +#include "arm_correlation_distance_f16.c" +#include "arm_cosine_distance_f16.c" +#include "arm_euclidean_distance_f16.c" +#include "arm_jensenshannon_distance_f16.c" +#include "arm_minkowski_distance_f16.c" + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c new file mode 100644 index 0000000..57873b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance.c @@ -0,0 +1,80 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +#endif + + +#define TT +#define TF +#define FT +#define EXT _TT_TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TF +#define FT +#define EXT _TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define FF +#define TF +#define FT +#define EXT _TT_FF_TF_FT +#include "arm_boolean_distance_template.h" + +#undef TT +#undef FF +#undef TF +#undef FT +#undef EXT +#define TT +#define EXT _TT +#include "arm_boolean_distance_template.h" + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h new file mode 100644 index 0000000..eb2e2af --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_boolean_distance_template.h @@ -0,0 +1,551 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_boolean_distance.c + * Description: Templates for boolean distances + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + + +/** + * @defgroup DISTANCEF Distance Functions + * + * Computes Distances between vectors. + * + * Distance functions are useful in a lot of algorithms. + * + */ + + +/** + * @addtogroup DISTANCEF + * @{ + */ + + + + +#define _FUNC(A,B) A##B + +#define FUNC(EXT) _FUNC(arm_boolean_distance, EXT) + +/** + * @brief Elements of boolean distances + * + * Different values which are used to compute boolean distances + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return None + * + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a, b, ba, bb; + int shift; + const uint8_t *pA8 = (const uint8_t *) pA; + const uint8_t *pB8 = (const uint8_t *) pB; + + /* handle vector blocks */ + uint32_t blkCnt = numberOfBools / 128; + + + + while (blkCnt > 0U) { + uint8x16_t vecA = vld1q((const uint8_t *) pA8); + uint8x16_t vecB = vld1q((const uint8_t *) pB8); + +#ifdef TT + uint8x16_t vecTT = vecA & vecB; + vecTT = vldrbq_gather_offset_u8(hwLUT, vecTT); + _ctt += vaddvq(vecTT); +#endif +#ifdef FF + uint8x16_t vecFF = vmvnq(vecA) & vmvnq(vecB); + vecFF = vldrbq_gather_offset_u8(hwLUT, vecFF); + _cff += vaddvq(vecFF); +#endif +#ifdef TF + uint8x16_t vecTF = vecA & vmvnq(vecB); + vecTF = vldrbq_gather_offset_u8(hwLUT, vecTF); + _ctf += vaddvq(vecTF); +#endif +#ifdef FT + uint8x16_t vecFT = vmvnq(vecA) & vecB; + vecFT = vldrbq_gather_offset_u8(hwLUT, vecFT); + _cft += vaddvq(vecFT); +#endif + + pA8 += 16; + pB8 += 16; + blkCnt--; + + } + + pA = (const uint32_t *)pA8; + pB = (const uint32_t *)pB8; + + blkCnt = numberOfBools & 0x7F; + while(blkCnt >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + blkCnt -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - blkCnt); + b = b >> (32 - blkCnt); + + while(blkCnt > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + blkCnt --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else +#if defined(ARM_MATH_NEON) + + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t nbBoolBlock; + uint32_t a,b,ba,bb; + int shift; + uint32x4_t aV, bV; +#ifdef TT + uint32x4_t cttV; +#endif +#ifdef FF + uint32x4_t cffV; +#endif +#ifdef TF + uint32x4_t ctfV; +#endif +#ifdef FT + uint32x4_t cftV; +#endif + uint8x16_t tmp; + uint16x8_t tmp2; + uint32x4_t tmp3; + uint64x2_t tmp4; +#ifdef TT + uint64x2_t tmp4tt; +#endif +#ifdef FF + uint64x2_t tmp4ff; +#endif +#ifdef TF + uint64x2_t tmp4tf; +#endif +#ifdef FT + uint64x2_t tmp4ft; +#endif + +#ifdef TT + tmp4tt = vdupq_n_u64(0); +#endif +#ifdef FF + tmp4ff = vdupq_n_u64(0); +#endif +#ifdef TF + tmp4tf = vdupq_n_u64(0); +#endif +#ifdef FT + tmp4ft = vdupq_n_u64(0); +#endif + + nbBoolBlock = numberOfBools >> 7; + while(nbBoolBlock > 0) + { + aV = vld1q_u32(pA); + bV = vld1q_u32(pB); + pA += 4; + pB += 4; + +#ifdef TT + cttV = vandq_u32(aV,bV); +#endif +#ifdef FF + cffV = vandq_u32(vmvnq_u32(aV),vmvnq_u32(bV)); +#endif +#ifdef TF + ctfV = vandq_u32(aV,vmvnq_u32(bV)); +#endif +#ifdef FT + cftV = vandq_u32(vmvnq_u32(aV),bV); +#endif + +#ifdef TT + tmp = vcntq_u8(vreinterpretq_u8_u32(cttV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tt = vaddq_u64(tmp4tt, tmp4); +#endif + +#ifdef FF + tmp = vcntq_u8(vreinterpretq_u8_u32(cffV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ff = vaddq_u64(tmp4ff, tmp4); +#endif + +#ifdef TF + tmp = vcntq_u8(vreinterpretq_u8_u32(ctfV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4tf = vaddq_u64(tmp4tf, tmp4); +#endif + +#ifdef FT + tmp = vcntq_u8(vreinterpretq_u8_u32(cftV)); + tmp2 = vpaddlq_u8(tmp); + tmp3 = vpaddlq_u16(tmp2); + tmp4 = vpaddlq_u32(tmp3); + tmp4ft = vaddq_u64(tmp4ft, tmp4); +#endif + + + nbBoolBlock --; + } + +#ifdef TT + _ctt += vgetq_lane_u64(tmp4tt, 0) + vgetq_lane_u64(tmp4tt, 1); +#endif +#ifdef FF + _cff +=vgetq_lane_u64(tmp4ff, 0) + vgetq_lane_u64(tmp4ff, 1); +#endif +#ifdef TF + _ctf += vgetq_lane_u64(tmp4tf, 0) + vgetq_lane_u64(tmp4tf, 1); +#endif +#ifdef FT + _cft += vgetq_lane_u64(tmp4ft, 0) + vgetq_lane_u64(tmp4ft, 1); +#endif + + nbBoolBlock = numberOfBools & 0x7F; + while(nbBoolBlock >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + nbBoolBlock -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - nbBoolBlock); + b = b >> (32 - nbBoolBlock); + + while(nbBoolBlock > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + nbBoolBlock --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} + +#else + +void FUNC(EXT)(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools +#ifdef TT + , uint32_t *cTT +#endif +#ifdef FF + , uint32_t *cFF +#endif +#ifdef TF + , uint32_t *cTF +#endif +#ifdef FT + , uint32_t *cFT +#endif + ) +{ + +#ifdef TT + uint32_t _ctt=0; +#endif +#ifdef FF + uint32_t _cff=0; +#endif +#ifdef TF + uint32_t _ctf=0; +#endif +#ifdef FT + uint32_t _cft=0; +#endif + uint32_t a,b,ba,bb; + int shift; + + while(numberOfBools >= 32) + { + a = *pA++; + b = *pB++; + shift = 0; + while(shift < 32) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + shift ++; + } + + numberOfBools -= 32; + } + + a = *pA++; + b = *pB++; + + a = a >> (32 - numberOfBools); + b = b >> (32 - numberOfBools); + + while(numberOfBools > 0) + { + ba = a & 1; + bb = b & 1; + a = a >> 1; + b = b >> 1; + +#ifdef TT + _ctt += (ba && bb); +#endif +#ifdef FF + _cff += ((1 ^ ba) && (1 ^ bb)); +#endif +#ifdef TF + _ctf += (ba && (1 ^ bb)); +#endif +#ifdef FT + _cft += ((1 ^ ba) && bb); +#endif + numberOfBools --; + } + +#ifdef TT + *cTT = _ctt; +#endif +#ifdef FF + *cFF = _cff; +#endif +#ifdef TF + *cTF = _ctf; +#endif +#ifdef FT + *cFT = _cft; +#endif +} +#endif +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + * @} end of DISTANCEF group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c new file mode 100644 index 0000000..be5537e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f16.c @@ -0,0 +1,158 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f16.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @ingroup groupDistance + */ + +/** + * @defgroup FloatDist Float Distances + * + * Distances between two vectors of float values. + */ + +/** + @ingroup FloatDist + */ + +/** + @defgroup braycurtis Bray-Curtis distance + + Bray-Curtis distance between two vectors + */ + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f16x8_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f16(0.0f); + accumSumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq(accumSumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f16(a, b); + c = vabsq_f16(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF16Mve(accumDiffV); + accumSum = vecAddAcrossF16Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else + +float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accumDiff=0.0f16, accumSum=0.0f16, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + accumSum += (_Float16)fabsf((float32_t)((_Float16)tmpA + (_Float16)tmpB)); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c new file mode 100644 index 0000000..ae13c35 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_braycurtis_distance_f32.c @@ -0,0 +1,187 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_braycurtis_distance_f32.c + * Description: Bray-Curtis distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup braycurtis + @{ + */ + + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff = 0.0f, accumSum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumDiffV, accumSumV; + + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + accumDiffV = vaddq(accumDiffV, c); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq(accumSumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + accumDiffV = vaddq_m(accumDiffV, accumDiffV, c, p0); + + c = vaddq_f32(a, b); + c = vabsq_f32(c); + accumSumV = vaddq_m(accumSumV, accumSumV, c, p0); + } + + accumDiff = vecAddAcrossF32Mve(accumDiffV); + accumSum = vecAddAcrossF32Mve(accumSumV); + + /* + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + */ + return (accumDiff / accumSum); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f; + uint32_t blkCnt; + float32x4_t a,b,c,accumDiffV, accumSumV; + float32x2_t accumV2; + + accumDiffV = vdupq_n_f32(0.0f); + accumSumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + accumDiffV = vaddq_f32(accumDiffV,c); + + c = vaddq_f32(a,b); + c = vabsq_f32(c); + accumSumV = vaddq_f32(accumSumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumDiffV),vget_high_f32(accumDiffV)); + accumDiff = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + accumV2 = vpadd_f32(vget_low_f32(accumSumV),vget_high_f32(accumSumV)); + accumSum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accumDiff += fabsf(*pA - *pB); + accumSum += fabsf(*pA++ + *pB++); + blkCnt --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} + +#else +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accumDiff=0.0f, accumSum=0.0f, tmpA, tmpB; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accumDiff += fabsf(tmpA - tmpB); + accumSum += fabsf(tmpA + tmpB); + blockSize --; + } + /* + + It is assumed that accumSum is not zero. Since it is the sum of several absolute + values it would imply that all of them are zero. It is very unlikely for long vectors. + + */ + return(accumDiff / accumSum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of braycurtis group + */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c new file mode 100644 index 0000000..bcefc91 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f16.c @@ -0,0 +1,171 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f16.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Canberra Canberra distance + + Canberra distance + */ + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum = 0.0f16; + uint32_t blkCnt; + f16x8_t a, b, c, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 8; + pB += 8; + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_hiprec_f16(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f16(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF16Mve(accumV); + + return (accum); +} + + +#else +float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + sum = (_Float16)fabsf((float32_t)tmpA) + (_Float16)fabsf((float32_t)tmpB); + if (((_Float16)tmpA != 0.0f16) || ((_Float16)tmpB != 0.0f16)) + { + accum += ((_Float16)diff / (_Float16)sum); + } + blockSize --; + } + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c new file mode 100644 index 0000000..c786c04 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_canberra_distance_f32.c @@ -0,0 +1,222 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_canberra_distance_f32.c + * Description: Canberra distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Canberra + @{ + */ + + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum = 0.0f; + uint32_t blkCnt; + f32x4_t a, b, c, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + a = vld1q(pA); + b = vld1q(pB); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq(accumV, c); + + pA += 4; + pB += 4; + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + c = vabdq(a, b); + + a = vabsq(a); + b = vabsq(b); + a = vaddq(a, b); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vrecip_medprec_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vdupq_m_n_f32(a, 0.0f, vcmpeqq(a, 0.0f)); + c = vmulq(c, a); + accumV = vaddq_m(accumV, accumV, c, p0); + } + + accum = vecAddAcrossF32Mve(accumV); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + uint32_t blkCnt; + float32x4_t a,b,c,accumV; + float32x2_t accumV2; + uint32x4_t isZeroV; + float32x4_t zeroV = vdupq_n_f32(0.0f); + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + c = vabdq_f32(a,b); + + a = vabsq_f32(a); + b = vabsq_f32(b); + a = vaddq_f32(a,b); + isZeroV = vceqq_f32(a,zeroV); + + /* + * May divide by zero when a and b have both the same lane at zero. + */ + a = vinvq_f32(a); + + /* + * Force result of a division by 0 to 0. It the behavior of the + * sklearn canberra function. + */ + a = vreinterpretq_f32_s32(vbicq_s32(vreinterpretq_s32_f32(a),vreinterpretq_s32_u32(isZeroV))); + c = vmulq_f32(c,a); + accumV = vaddq_f32(accumV,c); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB,diff,sum; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + + diff = fabsf(tmpA - tmpB); + sum = fabsf(tmpA) + fabsf(tmpB); + if ((tmpA != 0.0f) || (tmpB != 0.0f)) + { + accum += (diff / sum); + } + blockSize --; + } + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Canberra group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c new file mode 100644 index 0000000..8dec141 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f16.c @@ -0,0 +1,146 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f16.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Chebyshev Chebyshev distance + + Chebyshev distance + */ + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecA, vecB; + f16x8_t vecDiff = vdupq_n_f16(0.0); + float16_t maxValue = 0.0f16; + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 8; + vecB = vld1q(pB); + pB += 8; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_z_f16(pA, p0); + vecB = vldrhq_z_f16(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + if ((_Float16)diff > (_Float16)maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c new file mode 100644 index 0000000..41da72d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f32.c @@ -0,0 +1,213 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f32.c + * Description: Chebyshev distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecA, vecB; + f32x4_t vecDiff = vdupq_n_f32(0.0); + float32_t maxValue = 0.0; + + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + vecA = vld1q(pA); + pA += 4; + vecB = vld1q(pB); + pB += 4; + /* + * update per-lane max. + */ + vecDiff = vmaxnmaq(vsubq(vecA, vecB), vecDiff); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_z_f32(pA, p0); + vecB = vldrwq_z_f32(pB, p0); + + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + vecDiff = vmaxnmaq_m(vecDiff, vsubq(vecA, vecB), p0); + } + /* + * Get max value across the vector + */ + return vmaxnmavq(maxValue, vecDiff); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,diffV, maxValV; + float32x2_t maxValV2; + + if (blockSize <= 3) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + } + else + { + + a = vld1q_f32(pA); + b = vld1q_f32(pB); + pA += 4; + pB += 4; + + diffV = vabdq_f32(a,b); + + blockSize -= 4; + + maxValV = diffV; + + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + diffV = vabdq_f32(a,b); + maxValV = vmaxq_f32(maxValV, diffV); + + pA += 4; + pB += 4; + blkCnt --; + } + maxValV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + maxValV2 = vpmax_f32(maxValV2,maxValV2); + maxVal = vget_lane_f32(maxValV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blkCnt --; + } + } + return(maxVal); +} + +#else +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t diff=0.0f, maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabsf(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Chebyshev group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c new file mode 100644 index 0000000..899159d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_chebyshev_distance_f64.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_chebyshev_distance_f64.c + * Description: Chebyshev distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Chebyshev + @{ + */ + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t diff=0., maxVal,tmpA, tmpB; + + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + maxVal = diff; + blockSize--; + + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + diff = fabs(tmpA - tmpB); + if (diff > maxVal) + { + maxVal = diff; + } + blockSize --; + } + + return(maxVal); +} + +/** + * @} end of Chebyshev group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c new file mode 100644 index 0000000..44b3bdf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f16.c @@ -0,0 +1,128 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f16.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Manhattan Cityblock (Manhattan) distance + + Cityblock (Manhattan) distance + */ + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF16Mve(accumV); +} + +#else +float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum,tmpA, tmpB; + + accum = 0.0f16; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += (_Float16)fabsf((float32_t)((_Float16)tmpA - (_Float16)tmpB)); + + blockSize --; + } + + return(accum); +} +#endif + +/** + * @} end of Manhattan group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c new file mode 100644 index 0000000..08d406a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f32.c @@ -0,0 +1,157 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f32.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vabdq(a, b); + accumV = vaddq(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vabdq(a, b); + accumV = vaddq_m(accumV, accumV, tempV, p0); + } + + return vecAddAcrossF32Mve(accumV); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f, tmpA, tmpB; + uint32_t blkCnt; + float32x4_t a,b,accumV, tempV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + tempV = vabdq_f32(a,b); + accumV = vaddq_f32(accumV, tempV); + + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accumV2 = vpadd_f32(accumV2,accumV2); + accum = vget_lane_f32(accumV2,0); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blkCnt --; + } + return(accum); +} + +#else +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum,tmpA, tmpB; + + accum = 0.0f; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabsf(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} +#endif +#endif + +/** + * @} end of Manhattan group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c new file mode 100644 index 0000000..46c0a6d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cityblock_distance_f64.c @@ -0,0 +1,67 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cityblock_distance_f64.c + * Description: Cityblock (Manhattan) distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +/** + @addtogroup Manhattan + @{ + */ + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum,tmpA, tmpB; + + accum = 0.; + while(blockSize > 0) + { + tmpA = *pA++; + tmpB = *pB++; + accum += fabs(tmpA - tmpB); + + blockSize --; + } + + return(accum); +} + +/** + * @} end of Manhattan group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c new file mode 100644 index 0000000..7517cec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f16.c @@ -0,0 +1,99 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f16.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Correlation Correlation distance + + Correlation distance + */ + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize) +{ + float16_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f16(pA, blockSize, &ma); + arm_mean_f16(pB, blockSize, &mb); + + arm_offset_f16(pA, -(_Float16)ma, pA, blockSize); + arm_offset_f16(pB, -(_Float16)mb, pB, blockSize); + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + dot = (_Float16)dot / (_Float16)blockSize; + pwra = (_Float16)pwra / (_Float16)blockSize; + pwrb = (_Float16)pwrb / (_Float16)blockSize; + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb,&tmp); + + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + + +} + + + +/** + * @} end of Correlation group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c new file mode 100644 index 0000000..2578016 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_correlation_distance_f32.c @@ -0,0 +1,84 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlation_distance_f32.c + * Description: Correlation distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Correlation + @{ + */ + + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize) +{ + float32_t ma,mb,pwra,pwrb,dot,tmp; + + arm_mean_f32(pA, blockSize, &ma); + arm_mean_f32(pB, blockSize, &mb); + + arm_offset_f32(pA, -ma, pA, blockSize); + arm_offset_f32(pB, -mb, pB, blockSize); + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + dot = dot / blockSize; + pwra = pwra / blockSize; + pwrb = pwrb / blockSize; + + arm_sqrt_f32(pwra * pwrb,&tmp); + + return(1.0f - dot / tmp); + + +} + + + +/** + * @} end of Correlation group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c new file mode 100644 index 0000000..20f890b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f16.c @@ -0,0 +1,88 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f16.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup CosineDist Cosine distance + + Cosine distance + */ + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + float16_t pwra,pwrb,dot,tmp; + + arm_power_f16(pA, blockSize, &pwra); + arm_power_f16(pB, blockSize, &pwrb); + + arm_dot_prod_f16(pA,pB,blockSize,&dot); + + arm_sqrt_f16((_Float16)pwra * (_Float16)pwrb, &tmp); + return(1.0f16 - (_Float16)dot / (_Float16)tmp); + +} + + + +/** + * @} end of CosineDist group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c new file mode 100644 index 0000000..014bff0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f32.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f32.c + * Description: Cosine distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + * @par Description + * cosine_distance(u,v) is 1 - u . v / (Norm(u) Norm(v)) + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t pwra,pwrb,dot,tmp; + + arm_power_f32(pA, blockSize, &pwra); + arm_power_f32(pB, blockSize, &pwrb); + + arm_dot_prod_f32(pA,pB,blockSize,&dot); + + arm_sqrt_f32(pwra * pwrb, &tmp); + return(1.0f - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c new file mode 100644 index 0000000..c7443a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_cosine_distance_f64.c @@ -0,0 +1,70 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cosine_distance_f64.c + * Description: Cosine distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup CosineDist + @{ + */ + + + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t pwra,pwrb,dot,tmp; + + arm_power_f64(pA, blockSize, &pwra); + arm_power_f64(pB, blockSize, &pwrb); + + arm_dot_prod_f64(pA,pB,blockSize,&dot); + + tmp = sqrt(pwra * pwrb); + return(1. - dot / tmp); + +} + + + +/** + * @} end of CosineDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c new file mode 100644 index 0000000..cae963a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_dice_distance.c @@ -0,0 +1,92 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dice_distance.c + * Description: Dice distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + * @ingroup groupDistance + * @{ + */ + +/** + * @defgroup BoolDist Boolean Distances + * + * Distances between two vectors of boolean values. + * + * Booleans are packed in 32 bit words. + * numberOfBooleans argument is the number of booleans and not the + * number of words. + * + * Bits are packed in big-endian mode (because of behavior of numpy packbits in + * in version < 1.17) + */ + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (2.0*ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ + +/** + * @} end of groupDistance group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c new file mode 100644 index 0000000..64d5d4a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f16.c @@ -0,0 +1,131 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f16.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + @ingroup FloatDist + */ + +/** + @defgroup Euclidean Euclidean distance + + Euclidean distance + */ + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, accumV, tempV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f16(vecAddAcrossF16Mve(accumV), &tmp); + return (tmp); +} + +#else +float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 accum=0.0f,tmp; + float16_t result; + + while(blockSize > 0) + { + tmp = (_Float16)*pA++ - (_Float16)*pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f16(accum,&result); + return(result); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c new file mode 100644 index 0000000..e226617 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f32.c @@ -0,0 +1,152 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f32.c + * Description: Euclidean distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, accumV, tempV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tempV = vsubq(a, b); + accumV = vfmaq(accumV, tempV, tempV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tempV = vsubq(a, b); + accumV = vfmaq_m(accumV, tempV, tempV, p0); + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV), &tmp); + return (tmp); +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + uint32_t blkCnt; + float32x4_t a,b,accumV; + float32x2_t accumV2; + + accumV = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + a = vld1q_f32(pA); + b = vld1q_f32(pB); + + a = vsubq_f32(a,b); + accumV = vmlaq_f32(accumV,a,a); + pA += 4; + pB += 4; + blkCnt --; + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blkCnt --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} + +#else +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum=0.0f,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + arm_sqrt_f32(accum,&tmp); + return(tmp); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Euclidean group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c new file mode 100644 index 0000000..8c8dfde --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_euclidean_distance_f64.c @@ -0,0 +1,66 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_euclidean_distance_f64.c + * Description: Euclidean distance between two vectors + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +/** + @addtogroup Euclidean + @{ + */ + + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize) +{ + float64_t accum=0.,tmp; + + while(blockSize > 0) + { + tmp = *pA++ - *pB++; + accum += SQ(tmp); + blockSize --; + } + tmp = sqrt(accum); + return(tmp); +} + +/** + * @} end of Euclidean group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c new file mode 100644 index 0000000..f95c46e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_hamming_distance.c @@ -0,0 +1,70 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_hamming_distance.c + * Description: Hamming distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctf=0,cft=0; + + arm_boolean_distance_TF_FT(pA, pB, numberOfBools, &ctf, &cft); + + return(1.0*(ctf + cft) / numberOfBools); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c new file mode 100644 index 0000000..26617a5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jaccard_distance.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jaccard_distance.c + * Description: Jaccard distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft) / (ctt + cft + ctf)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c new file mode 100644 index 0000000..b31ef34 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f16.c @@ -0,0 +1,177 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f16.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup JensenShannon Jensen-Shannon distance + + Jensen-Shannon distance + */ + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float16_t rel_entr(float16_t x, float16_t y) +{ + return ((_Float16)x * (_Float16)logf((float32_t)((_Float16)x / (_Float16)y))); +} +#endif + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float16_t tmp; + f16x8_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f16(a, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, a, tmpV, p0); + + tmpV = vmulq_f16(b, vrecip_medprec_f16(t)); + tmpV = vlogq_f16(tmpV); + accumV = vfmaq_m_f16(accumV, b, tmpV, p0); + + } + + arm_sqrt_f16((_Float16)vecAddAcrossF16Mve(accumV) / 2.0f16, &tmp); + return (tmp); +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize) +{ + _Float16 left, right,sum, tmp; + float16_t result; + uint32_t i; + + left = 0.0f16; + right = 0.0f16; + for(i=0; i < blockSize; i++) + { + tmp = ((_Float16)pA[i] + (_Float16)pB[i]) / 2.0f16; + left += (_Float16)rel_entr(pA[i], tmp); + right += (_Float16)rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f16((_Float16)sum/2.0f16, &result); + return(result); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c new file mode 100644 index 0000000..5f1a44c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_jensenshannon_distance_f32.c @@ -0,0 +1,247 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_jensenshannon_distance_f32.c + * Description: Jensen-Shannon distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup JensenShannon + @{ + */ + +#if !defined(ARM_MATH_MVEF) || defined(ARM_MATH_AUTOVECTORIZE) +/// @private +__STATIC_INLINE float32_t rel_entr(float32_t x, float32_t y) +{ + return (x * logf(x / y)); +} +#endif + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t tmp; + f32x4_t a, b, t, tmpV, accumV; + + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, a, tmpV); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq(accumV, b, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + t = vaddq(a, b); + t = vmulq(t, 0.5f); + + tmpV = vmulq_f32(a, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, a, tmpV, p0); + + tmpV = vmulq_f32(b, vrecip_medprec_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vfmaq_m_f32(accumV, b, tmpV, p0); + + } + + arm_sqrt_f32(vecAddAcrossF32Mve(accumV) / 2.0f, &tmp); + return (tmp); +} + +#else + +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t accum, result, tmp,a,b; + uint32_t blkCnt; + float32x4_t aV,bV,t, tmpV, accumV; + float32x2_t accumV2; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + t = vaddq_f32(aV,bV); + t = vmulq_n_f32(t, 0.5f); + + tmpV = vmulq_f32(aV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, aV, tmpV); + + + tmpV = vmulq_f32(bV, vinvq_f32(t)); + tmpV = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, bV, tmpV); + + pA += 4; + pB += 4; + + + blkCnt --; + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + a = *pA; + b = *pB; + tmp = (a + b) / 2.0f; + accum += rel_entr(a, tmp); + accum += rel_entr(b, tmp); + + pA++; + pB++; + + blkCnt --; + } + + + arm_sqrt_f32(accum/2.0f, &result); + return(result); + +} + +#else + + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x == 0 and y == 0, + * it will compute the right result (0) but a division by zero will occur + * and should be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize) +{ + float32_t left, right,sum, result, tmp; + uint32_t i; + + left = 0.0f; + right = 0.0f; + for(i=0; i < blockSize; i++) + { + tmp = (pA[i] + pB[i]) / 2.0f; + left += rel_entr(pA[i], tmp); + right += rel_entr(pB[i], tmp); + } + + + sum = left + right; + arm_sqrt_f32(sum/2.0f, &result); + return(result); + +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of JensenShannon group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c new file mode 100644 index 0000000..239dc0e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_kulsinski_distance.c @@ -0,0 +1,73 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_kulsinski_distance.c + * Description: Kulsinski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,ctf=0,cft=0; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + return(1.0*(ctf + cft - ctt + numberOfBools) / (cft + ctf + numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c new file mode 100644 index 0000000..c5300ab --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f16.c @@ -0,0 +1,137 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f16.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup FloatDist + */ + +/** + @defgroup Minkowski Minkowski distance + + Minkowski distance + */ + +/** + @addtogroup Minkowski + @{ + */ + + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f16x8_t a, b, tmpV, sumV; + + sumV = vdupq_n_f16(0.0f); + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq(sumV, tmpV); + + pA += 8; + pB += 8; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + + a = vldrhq_z_f16(pA, p0); + b = vldrhq_z_f16(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f16(tmpV, vdupq_n_f16(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf((float32_t)vecAddAcrossF16Mve(sumV), (1.0f / (float32_t) order))); +} + + +#else + + +float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize) +{ + _Float16 sum; + uint32_t i; + + sum = 0.0f16; + for(i=0; i < blockSize; i++) + { + sum += (_Float16)powf(fabsf((float32_t)((_Float16)pA[i] - (_Float16)pB[i])),order); + } + + + return(_Float16)(powf((float32_t)sum,(1.0f/(float32_t)order))); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c new file mode 100644 index 0000000..b881fc1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_minkowski_distance_f32.c @@ -0,0 +1,188 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_minkowski_distance_f32.c + * Description: Minkowski distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +/** + @addtogroup Minkowski + @{ + */ + +/* 6.14 bug */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001) + +__attribute__((weak)) float __powisf2(float a, int b) +{ + const int recip = b < 0; + float r = 1; + while (1) + { + if (b & 1) + r *= a; + b /= 2; + if (b == 0) + break; + a *= a; + } + return recip ? 1/r : r; +} +#endif + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + uint32_t blkCnt; + f32x4_t a, b, tmpV, sumV; + + sumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) { + a = vld1q(pA); + b = vld1q(pB); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq(sumV, tmpV); + + pA += 4; + pB += 4; + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + + a = vldrwq_z_f32(pA, p0); + b = vldrwq_z_f32(pB, p0); + + tmpV = vabdq(a, b); + tmpV = vpowq_f32(tmpV, vdupq_n_f32(order)); + sumV = vaddq_m(sumV, sumV, tmpV, p0); + } + + return (powf(vecAddAcrossF32Mve(sumV), (1.0f / (float32_t) order))); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t blkCnt; + float32x4_t sumV,aV,bV, tmpV, n; + float32x2_t sumV2; + + sum = 0.0f; + sumV = vdupq_n_f32(0.0f); + n = vdupq_n_f32(order); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + aV = vld1q_f32(pA); + bV = vld1q_f32(pB); + pA += 4; + pB += 4; + + tmpV = vabdq_f32(aV,bV); + tmpV = vpowq_f32(tmpV,n); + sumV = vaddq_f32(sumV, tmpV); + + + blkCnt --; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + sum += powf(fabsf(*pA++ - *pB++),order); + + blkCnt --; + } + + + return(powf(sum,(1.0f/order))); + +} + +#else + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize) +{ + float32_t sum; + uint32_t i; + + sum = 0.0f; + for(i=0; i < blockSize; i++) + { + sum += powf(fabsf(pA[i] - pB[i]),order); + } + + + return(powf(sum,(1.0f/order))); + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of Minkowski group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c new file mode 100644 index 0000000..b918fad --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_rogerstanimoto_distance.c @@ -0,0 +1,75 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rogerstanimoto_distance.c + * Description: Roger Stanimoto distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Rogers Tanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf + cft); + + return(1.0*r / (r + ctt + cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c new file mode 100644 index 0000000..0698a64 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_russellrao_distance.c @@ -0,0 +1,72 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_russellrao_distance.c + * Description: Russell-Rao distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + + +extern void arm_boolean_distance_TT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0; + + + arm_boolean_distance_TT(pA, pB, numberOfBools, &ctt); + + + return(1.0f*(numberOfBools - ctt) / ((float32_t)numberOfBools)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c new file mode 100644 index 0000000..8015c97 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalmichener_distance.c @@ -0,0 +1,76 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalmichener_distance.c + * Description: Sokal-Michener distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,cft=0,ctf=0; + float32_t r,s; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt, &cff, &ctf, &cft); + + r = 2.0*(ctf + cft); + s = 1.0*(cff + ctt); + + return(r / (s+r)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c new file mode 100644 index 0000000..93d8e50 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_sokalsneath_distance.c @@ -0,0 +1,74 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sokalsneath_distance.c + * Description: Sokal-Sneath distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cTF + , uint32_t *cFT + ); + + +/** + @addtogroup BoolDist + @{ + */ + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cft=0,ctf=0; + float32_t r; + + arm_boolean_distance_TT_TF_FT(pA, pB, numberOfBools, &ctt, &ctf, &cft); + + r = 2.0*(ctf + cft); + + return(r / (r + ctt)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c new file mode 100644 index 0000000..54afebf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/DistanceFunctions/arm_yule_distance.c @@ -0,0 +1,74 @@ + +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_yule_distance.c + * Description: Yule distance between two vectors + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/distance_functions.h" +#include +#include + + +extern void arm_boolean_distance_TT_FF_TF_FT(const uint32_t *pA + , const uint32_t *pB + , uint32_t numberOfBools + , uint32_t *cTT + , uint32_t *cFF + , uint32_t *cTF + , uint32_t *cFT + ); + +/** + @addtogroup BoolDist + @{ + */ + + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools) +{ + uint32_t ctt=0,cff=0,ctf=0,cft=0,r; + + arm_boolean_distance_TT_FF_TF_FT(pA, pB, numberOfBools, &ctt,&cff, &ctf, &cft); + + r = 2*(ctf * cft); + + return(1.0*r / (r/2.0 + ctt * cff)); +} + + +/** + * @} end of BoolDist group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..95a9eb6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/CMakeLists.txt @@ -0,0 +1,80 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPFastMath) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPFastMath STATIC) +configLib(CMSISDSPFastMath ${ROOT}) +configDsp(CMSISDSPFastMath ${ROOT}) + +include(interpol) +interpol(CMSISDSPFastMath) + +if (CONFIGTABLE AND ALLFAST) + target_compile_definitions(CMSISDSPFastMath PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_COS_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_cos_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_F32) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SIN_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_sin_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SQRT_Q31) +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_SQRT_Q15) +target_sources(CMSISDSPFastMath PRIVATE arm_sqrt_q15.c) +endif() + +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f64.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f64.c) + +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_q31.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_q15.c) + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPFastMath PRIVATE arm_vlog_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vexp_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_vinverse_f16.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_f16.c) +endif() + +target_sources(CMSISDSPFastMath PRIVATE arm_divide_q15.c) +target_sources(CMSISDSPFastMath PRIVATE arm_divide_q31.c) + +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_f32.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_q31.c) +target_sources(CMSISDSPFastMath PRIVATE arm_atan2_q15.c) + + +### Includes +target_include_directories(CMSISDSPFastMath PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c new file mode 100644 index 0000000..0146d61 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_cos_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +#include "arm_cos_q15.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_cos_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) +#include "arm_sin_f32.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) +#include "arm_sin_q15.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) +#include "arm_sin_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31) +#include "arm_sqrt_q31.c" +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15) +#include "arm_sqrt_q15.c" +#endif + +#endif + +#include "arm_vexp_f32.c" +#include "arm_vexp_f64.c" +#include "arm_vlog_f32.c" +#include "arm_vlog_f64.c" +#include "arm_divide_q15.c" +#include "arm_divide_q31.c" +#include "arm_vlog_q31.c" +#include "arm_vlog_q15.c" +#include "arm_atan2_f32.c" +#include "arm_atan2_q31.c" +#include "arm_atan2_q15.c" diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c new file mode 100644 index 0000000..79c731f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctionsF16.c @@ -0,0 +1,32 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FastMathFunctions.c + * Description: Combination of all fast math function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_vexp_f16.c" +#include "arm_vlog_f16.c" +#include "arm_vinverse_f16.c" +#include "arm_atan2_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c new file mode 100644 index 0000000..b4a03a4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f16.c + * Description: float16 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define PIF16 3.14f16 +#define PI16HALF 1.571f16 + +#define ATANHALFF16 0.463648f16 + +#define ATAN2_NB_COEFS_F16 5 + +static const float16_t atan2_coefs_f16[ATAN2_NB_COEFS_F16]={0.f16 +,1.f16 +,0.f16 +,-0.367f16 +,0.152f16 +}; + +__STATIC_FORCEINLINE float16_t arm_atan_limited_f16(float16_t x) +{ + float16_t res=atan2_coefs_f16[ATAN2_NB_COEFS_F16-1]; + int i=1; + for(i=1;i 1.0f16) + { + x = 1.0f16 / (_Float16)x; + res = (_Float16)PI16HALF - (_Float16)arm_atan_limited_f16(x); + } + else + { + res += (_Float16)arm_atan_limited_f16(x); + } + + + if (sign) + { + res = -(_Float16)res; + } + + return(res); +} + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. + +*/ +arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result) +{ + if ((_Float16)x > 0.0f16) + { + *result=arm_atan_f16((_Float16)y/(_Float16)x); + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x < 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) + (_Float16)PIF16; + } + else if ((_Float16)y < 0.0f16) + { + *result=(_Float16)arm_atan_f16((_Float16)y/(_Float16)x) - (_Float16)PIF16; + } + else + { + if (signbit(y)) + { + *result= -(_Float16)PIF16; + } + else + { + *result= PIF16; + } + } + return(ARM_MATH_SUCCESS); + } + if ((_Float16)x == 0.0f16) + { + if ((_Float16)y > 0.0f16) + { + *result=PI16HALF; + return(ARM_MATH_SUCCESS); + } + if ((_Float16)y < 0.0f16) + { + *result=-(_Float16)PI16HALF; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of atan2 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c new file mode 100644 index 0000000..3e398f7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_f32.c @@ -0,0 +1,183 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_f32.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" + +/* + +atan for argument between in [0, 1.0] + + +*/ + +#define ATANHALFF32 0.463648f +#define PIHALFF32 1.5707963267948966192313f + +#define ATAN2_NB_COEFS_F32 10 + +static const float32_t atan2_coefs_f32[ATAN2_NB_COEFS_F32]={0.0f +,1.0000001638308195518f +,-0.0000228941363602264f +,-0.3328086544578890873f +,-0.004404814619311061f +,0.2162217461808173258f +,-0.0207504842057097504f +,-0.1745263362250363339f +,0.1340557235283553386f +,-0.0323664125927477625f +}; + +__STATIC_FORCEINLINE float32_t arm_atan_limited_f32(float32_t x) +{ + float32_t res=atan2_coefs_f32[ATAN2_NB_COEFS_F32-1]; + int i=1; + for(i=1;i 1.0f) + { + x = 1.0f / x; + res = PIHALFF32 - arm_atan_limited_f32(x); + } + else + { + res += arm_atan_limited_f32(x); + } + + + if (sign) + { + res = -res; + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + +/** + @defgroup atan2 ArcTan2 + + Computing Arc tangent only using the ratio y/x is not enough to determine the angle + since there is an indeterminacy. Opposite quadrants are giving the same ratio. + + ArcTan2 is not using y/x to compute the angle but y and x and use the sign of y and x + to determine the quadrant. + + */ + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result) +{ + if (x > 0.0f) + { + *result=arm_atan_f32(y/x); + return(ARM_MATH_SUCCESS); + } + if (x < 0.0f) + { + if (y > 0.0f) + { + *result=arm_atan_f32(y/x) + PI; + } + else if (y < 0.0f) + { + *result=arm_atan_f32(y/x) - PI; + } + else + { + if (signbit(y)) + { + *result= -PI; + } + else + { + *result= PI; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0.0f) + { + if (y > 0.0f) + { + *result=PIHALFF32; + return(ARM_MATH_SUCCESS); + } + if (y < 0.0f) + { + *result=-PIHALFF32; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c new file mode 100644 index 0000000..ddf98d8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q15.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.13 */ +#define ATANHALFQ13 0xed6 +#define PIHALFQ13 0x3244 +#define PIQ13 0x6488 + +#define ATAN2_NB_COEFS_Q15 10 + +static const q15_t atan2_coefs_q15[ATAN2_NB_COEFS_Q15]={0x0000 +,0x7fff +,0xffff +,0xd567 +,0xff70 +,0x1bad +,0xfd58 +,0xe9a9 +,0x1129 +,0xfbdb +}; + +__STATIC_FORCEINLINE q15_t arm_atan_limited_q15(q15_t x) +{ + q31_t res=(q31_t)atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1]; + int i=1; + for(i=1;i> 15U; + res = res + ((q31_t) atan2_coefs_q15[ATAN2_NB_COEFS_Q15-1-i]) ; + } + + res = __SSAT(res>>2,16); + + + return(res); +} + + +__STATIC_FORCEINLINE q15_t arm_atan_q15(q15_t y,q15_t x) +{ + int sign=0; + q15_t res=0; + + if (y<0) + { + arm_negate_q15(&y,&y,1); + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + arm_negate_q15(&x,&x,1); + } + + if (y > x) + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(x,y,&ratio,&shift); + + arm_shift_q15(&ratio,shift,&ratio,1); + + res = PIHALFQ13 - arm_atan_limited_q15(ratio); + + } + else + { + q15_t ratio; + int16_t shift; + + arm_divide_q15(y,x,&ratio,&shift); + + arm_shift_q15(&ratio,shift,&ratio,1); + + res = arm_atan_limited_q15(ratio); + + } + + + if (sign) + { + arm_negate_q15(&res,&res,1); + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.13 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result) +{ + if (x > 0) + { + *result=arm_atan_q15(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q15(y,x) + PIQ13; + } + else if (y < 0) + { + *result=arm_atan_q15(y,x) - PIQ13; + } + else + { + if (y<0) + { + *result= -PIQ13; + } + else + { + *result= PIQ13; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALFQ13; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c new file mode 100644 index 0000000..1c83e43 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_atan2_q31.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_atan2_q31.c + * Description: float32 Arc tangent of y/x + * + * $Date: 22 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "dsp/utils.h" + +/* + +atan for argument between in [0, 1.0] + +*/ + + +/* Q2.29 */ +#define ATANHALF_Q29 0xed63383 +#define PIHALF_Q29 0x3243f6a9 +#define PIQ29 0x6487ed51 + +#define ATAN2_NB_COEFS_Q31 13 + +static const q31_t atan2_coefs_q31[ATAN2_NB_COEFS_Q31]={0x00000000 +,0x7ffffffe +,0x000001b6 +,0xd555158e +,0x00036463 +,0x1985f617 +,0x001992ae +,0xeed53a7f +,0xf8f15245 +,0x2215a3a4 +,0xe0fab004 +,0x0cdd4825 +,0xfddbc054 +}; + + +__STATIC_FORCEINLINE q31_t arm_atan_limited_q31(q31_t x) +{ + q63_t res=(q63_t)atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1]; + int i=1; + for(i=1;i> 31U; + res = res + ((q63_t) atan2_coefs_q31[ATAN2_NB_COEFS_Q31-1-i]) ; + } + + return(clip_q63_to_q31(res>>2)); +} + + +__STATIC_FORCEINLINE q31_t arm_atan_q31(q31_t y,q31_t x) +{ + int sign=0; + q31_t res=0; + + if (y<0) + { + arm_negate_q31(&y,&y,1); + sign=1-sign; + } + + if (x < 0) + { + sign=1 - sign; + arm_negate_q31(&x,&x,1); + } + + if (y > x) + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(x,y,&ratio,&shift); + + arm_shift_q31(&ratio,shift,&ratio,1); + + res = PIHALF_Q29 - arm_atan_limited_q31(ratio); + + } + else + { + q31_t ratio; + int16_t shift; + + arm_divide_q31(y,x,&ratio,&shift); + + arm_shift_q31(&ratio,shift,&ratio,1); + + res = arm_atan_limited_q31(ratio); + + } + + + if (sign) + { + arm_negate_q31(&res,&res,1); + } + + return(res); +} + + +/** + @ingroup groupFastMath + */ + + +/** + @addtogroup atan2 + @{ + */ + +/** + @brief Arc Tangent of y/x using sign of y and x to get right quadrant + @param[in] y y coordinate + @param[in] x x coordinate + @param[out] result Result in Q2.29 + @return error status. + + @par Compute the Arc tangent of y/x: + The sign of y and x are used to determine the right quadrant + and compute the right angle. +*/ + + +arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result) +{ + if (x > 0) + { + *result=arm_atan_q31(y,x); + return(ARM_MATH_SUCCESS); + } + if (x < 0) + { + if (y > 0) + { + *result=arm_atan_q31(y,x) + PIQ29; + } + else if (y < 0) + { + *result=arm_atan_q31(y,x) - PIQ29; + } + else + { + if (y<0) + { + *result= -PIQ29; + } + else + { + *result= PIQ29; + } + } + return(ARM_MATH_SUCCESS); + } + if (x == 0) + { + if (y > 0) + { + *result=PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + if (y < 0) + { + *result=-PIHALF_Q29; + return(ARM_MATH_SUCCESS); + } + } + + + return(ARM_MATH_NANINF); + +} + +/** + @} end of atan2 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c new file mode 100644 index 0000000..de037c8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_f32.c + * Description: Fast cosine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup cos Cosine + + Computes the trigonometric cosine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     a = Table[index];
+     b = Table[index+1];
+
+ */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians + @return cos(x) + */ +float32_t arm_cos_f32( + float32_t x) +{ + float32_t cosVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table */ + in = x * 0.159154943092f + 0.25f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the cos table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + cosVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (cosVal); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c new file mode 100644 index 0000000..6b552f1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_cos_q15( + q15_t x) +{ + q15_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint16_t)x + 0x2000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + cosVal = (q31_t) (0x8000 - fract) * a >> 16; + cosVal = (q15_t) ((((q31_t) cosVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c new file mode 100644 index 0000000..8386c8f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup cos + @{ + */ + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians + @return cos(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_cos_q31( + q31_t x) +{ + q31_t cosVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + /* add 0.25 (pi/2) to read sine table */ + x = (uint32_t)x + 0x20000000; + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + cosVal = (q63_t) (0x80000000 - fract) * a >> 32; + cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (cosVal << 1); +} + +/** + @} end of cos group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c new file mode 100644 index 0000000..9c26e06 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q15.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q15.c + * Description: Fast cosine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q15(q15_t numerator, + q15_t denominator, + q15_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q31_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>15) ^ (denominator>>15); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x8000; + } + else + { + *quotient = 0x7FFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q15(&numerator,&numerator,1); + arm_abs_q15(&denominator,&denominator,1); + + temp = ((q31_t)numerator << 15) / ((q31_t)denominator); + + shiftForNormalizing= 17 - __CLZ(temp); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c new file mode 100644 index 0000000..12b727f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_divide_q31.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cos_q31.c + * Description: Fast cosine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#include + +/** + @ingroup groupFastMath + */ + +/** + @defgroup divide Fixed point division + + */ + +/** + @addtogroup divide + @{ + */ + +/** + @brief Fixed point division + @param[in] numerator Numerator + @param[in] denominator Denominator + @param[out] quotient Quotient value normalized between -1.0 and 1.0 + @param[out] shift Shift left value to get the unnormalized quotient + @return error status + + When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced + to the saturated negative or positive value. + */ + +arm_status arm_divide_q31(q31_t numerator, + q31_t denominator, + q31_t *quotient, + int16_t *shift) +{ + int16_t sign=0; + q63_t temp; + int16_t shiftForNormalizing; + + *shift = 0; + + sign = (numerator>>31) ^ (denominator>>31); + + if (denominator == 0) + { + if (sign) + { + *quotient = 0x80000000; + } + else + { + *quotient = 0x7FFFFFFF; + } + return(ARM_MATH_NANINF); + } + + arm_abs_q31(&numerator,&numerator,1); + arm_abs_q31(&denominator,&denominator,1); + + temp = ((q63_t)numerator << 31) / ((q63_t)denominator); + + shiftForNormalizing= 32 - __CLZ(temp >> 31); + if (shiftForNormalizing > 0) + { + *shift = shiftForNormalizing; + temp = temp >> shiftForNormalizing; + } + + if (sign) + { + temp = -temp; + } + + *quotient=(q31_t)temp; + + return(ARM_MATH_SUCCESS); +} + +/** + @} end of divide group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c new file mode 100644 index 0000000..2fcd6bb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_f32.c + * Description: Fast sine calculation for floating-point values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @defgroup sin Sine + + Computes the trigonometric sine function using a combination of table lookup + and linear interpolation. There are separate functions for + Q15, Q31, and floating-point data types. + The input to the floating-point version is in radians while the + fixed-point Q15 and Q31 have a scaled input with the range + [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a + value of 2*pi wraps around to 0. + + The implementation is based on table lookup using 512 values together with linear interpolation. + The steps used are: + -# Calculation of the nearest integer table index + -# Compute the fractional portion (fract) of the table index. + -# The final result equals (1.0f-fract)*a + fract*b; + + where + 
+     b = Table[index];
+     c = Table[index+1];
+
+ */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x) + */ + +float32_t arm_sin_f32( + float32_t x) +{ + float32_t sinVal, fract, in; /* Temporary input, output variables */ + uint16_t index; /* Index variable */ + float32_t a, b; /* Two nearest output values */ + int32_t n; + float32_t findex; + + /* input x is in radians */ + /* Scale input to [0 1] range from [0 2*PI] , divide input by 2*pi */ + in = x * 0.159154943092f; + + /* Calculation of floor value of input */ + n = (int32_t) in; + + /* Make negative values towards -infinity */ + if (in < 0.0f) + { + n--; + } + + /* Map input value to [0 1] */ + in = in - (float32_t) n; + + /* Calculation of index of the table */ + findex = (float32_t)FAST_MATH_TABLE_SIZE * in; + index = (uint16_t)findex; + + /* when "in" is exactly 1, we need to rotate the index down to 0 */ + if (index >= FAST_MATH_TABLE_SIZE) { + index = 0; + findex -= (float32_t)FAST_MATH_TABLE_SIZE; + } + + /* fractional value calculation */ + fract = findex - (float32_t) index; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_f32[index]; + b = sinTable_f32[index+1]; + + /* Linear interpolation process */ + sinVal = (1.0f - fract) * a + fract * b; + + /* Return output value */ + return (sinVal); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c new file mode 100644 index 0000000..81f0d62 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q15.c + * Description: Fast sine calculation for Q15 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q15_t arm_sin_q15( + q15_t x) +{ + q15_t sinVal; /* Temporary input, output variables */ + int32_t index; /* Index variable */ + q15_t a, b; /* Two nearest output values */ + q15_t fract; /* Temporary values for fractional values */ + + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint16_t)x + 0x8000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q15_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q15_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q15[index]; + b = sinTable_q15[index+1]; + + /* Linear interpolation process */ + sinVal = (q31_t) (0x8000 - fract) * a >> 16; + sinVal = (q15_t) ((((q31_t) sinVal << 16) + ((q31_t) fract * b)) >> 16); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c new file mode 100644 index 0000000..06262fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sin_q31.c + * Description: Fast sine calculation for Q31 values + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup sin + @{ + */ + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians + @return sin(x) + + The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*PI). + */ + +q31_t arm_sin_q31( + q31_t x) +{ + q31_t sinVal; /* Temporary variables for input, output */ + int32_t index; /* Index variable */ + q31_t a, b; /* Two nearest output values */ + q31_t fract; /* Temporary values for fractional values */ + + if (x < 0) + { /* convert negative numbers to corresponding positive ones */ + x = (uint32_t)x + 0x80000000; + } + + /* Calculate the nearest index */ + index = (uint32_t)x >> FAST_MATH_Q31_SHIFT; + + /* Calculation of fractional value */ + fract = (x - (index << FAST_MATH_Q31_SHIFT)) << 9; + + /* Read two nearest values of input value from the sin table */ + a = sinTable_q31[index]; + b = sinTable_q31[index+1]; + + /* Linear interpolation process */ + sinVal = (q63_t) (0x80000000 - fract) * a >> 32; + sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) fract * b)) >> 32); + + /* Return output value */ + return (sinVal << 1); +} + +/** + @} end of sin group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c new file mode 100644 index 0000000..defeebe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q15.c + * Description: Q15 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ + +#define Q12QUARTER 0x2000 +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut) +{ + q15_t number, var1, signBits1,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 17; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q15[(number>> 11) - (Q12QUARTER >> 11)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + /* 1st iteration */ + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + temp = ((q31_t) var1 * var1) >> 12; + temp = ((q31_t) number * temp) >> 15; + temp = 0x3000 - temp; + var1 = ((q31_t) var1 * temp) >> 13; + + /* Multiply the inverse square root with the original value */ + + var1 = ((q15_t) (((q31_t) number * var1) >> 12)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c new file mode 100644 index 0000000..8747670 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sqrt_q31.c + * Description: Q31 square root function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup SQRT + @{ + */ + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +#define Q28QUARTER 0x20000000 + +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut) +{ + q31_t number, var1, signBits1 ,temp; + + number = in; + + /* If the input is a positive number then compute the signBits. */ + if (number > 0) + { + signBits1 = __CLZ(number) - 1; + + /* Shift by the number of signBits1 */ + if ((signBits1 % 2) == 0) + { + number = number << signBits1; + } + else + { + number = number << (signBits1 - 1); + } + + /* Start value for 1/sqrt(x) for the Newton iteration */ + var1 = sqrt_initial_lut_q31[(number>> 26) - (Q28QUARTER >> 26)]; + + /* 0.5 var1 * (3 - number * var1 * var1) */ + + /* 1st iteration */ + + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + + /* 2nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* 3nd iteration */ + temp = ((q63_t) var1 * var1) >> 28; + temp = ((q63_t) number * temp) >> 31; + temp = 0x30000000 - temp; + var1 = ((q63_t) var1 * temp) >> 29; + + /* Multiply the inverse square root with the original value */ + var1 = ((q31_t) (((q63_t) number * var1) >> 28)); + + /* Shift the output down accordingly */ + if ((signBits1 % 2) == 0) + { + var1 = var1 >> (signBits1 / 2); + } + else + { + var1 = var1 >> ((signBits1 - 1) / 2); + } + *pOut = var1; + + return (ARM_MATH_SUCCESS); + } + /* If the number is a negative number then store zero as its square root value */ + else + { + *pOut = 0; + + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + @} end of SQRT group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c new file mode 100644 index 0000000..dd7c06e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f16.c @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables.h" + +#include "arm_vec_math_f16.h" + + +void arm_vexp_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = (_Float16)expf((float32_t)*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c new file mode 100644 index 0000000..43b2a86 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f32.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vexpq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vexpq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = expf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c new file mode 100644 index 0000000..76f80ff --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vexp_f64.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +void arm_vexp_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = exp(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c new file mode 100644 index 0000000..1067d02 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vinverse_f16.c @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vinverse_f16.c + * Description: Fast vectorized inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include "arm_common_tables.h" + +#include "arm_vec_math_f16.h" + +void arm_vinverse_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vrecip_hiprec_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + + *pDst++ = 1.0f16 / (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c new file mode 100644 index 0000000..0821d5a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f16.c @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f16.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions_f16.h" +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/* Degree of the polynomial approximation */ +#define NB_DEG_LOGF16 3 + +/* +Related to the Log2 of the number of approximations. +For instance, with 3 there are 1 + 2^3 polynomials +*/ +#define NB_DIV_LOGF16 3 + +/* Length of the LUT table */ +#define NB_LUT_LOGF16 (NB_DEG_LOGF16+1)*(1 + (1< 1000][[2, 1]], {i, 1, 2, (1.0/2^nb)}]; +coefs = Chop@Flatten[CoefficientList[lut, x]]; + +*/ +static float16_t lut_logf16[NB_LUT_LOGF16]={ + 0,0.125,-0.00781197,0.00063974,0.117783, + 0.111111,-0.00617212,0.000447935,0.223144, + 0.1,-0.00499952,0.000327193,0.318454,0.0909091, + -0.00413191,0.000246234,0.405465,0.0833333, + -0.00347199,0.000189928,0.485508,0.0769231, + -0.00295841,0.00014956,0.559616,0.0714286, + -0.0025509,0.000119868,0.628609,0.0666667, + -0.00222213,0.0000975436,0.693147, + 0.0625,-0.00195305,0.0000804357}; + + +float16_t logf16_scalar(float16_t x) +{ + int16_t i = arm_typecast_s16_f16(x); + + int32_t vecExpUnBiased = (i >> 10) - 15; + i = i - (vecExpUnBiased << 10); + float16_t vecTmpFlt1 = arm_typecast_f16_s16(i); + + float16_t *lut; + int n; + float16_t tmp,v; + + tmp = ((_Float16)vecTmpFlt1 - 1.0f16) * (1 << NB_DIV_LOGF16); + n = (int)floor((double)tmp); + v = (_Float16)tmp - (_Float16)n; + + lut = lut_logf16 + n * (1+NB_DEG_LOGF16); + + float16_t res = lut[NB_DEG_LOGF16-1]; + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + res = (_Float16)lut[j] + (_Float16)v * (_Float16)res; + } + + res = (_Float16)res + 0.693147f16 * (_Float16)vecExpUnBiased; + + + return(res); +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_common_tables.h" +#include "arm_vec_math_f16.h" + + +float16x8_t vlogq_lut_f16(float16x8_t vecIn) +{ + int16x8_t i = vreinterpretq_s16_f16(vecIn); + + int16x8_t vecExpUnBiased = vsubq_n_s16(vshrq_n_s16(i,10), 15); + i = vsubq_s16(i,vshlq_n_s16(vecExpUnBiased,10)); + float16x8_t vecTmpFlt1 = vreinterpretq_f16_s16(i); + + + float16x8_t lutV; + int16x8_t n; + int16x8_t offset; + + float16x8_t tmp,v,res; + + tmp = vmulq_n_f16(vsubq_n_f16(vecTmpFlt1,1.0f16),(_Float16)(1 << NB_DIV_LOGF16)); + + n = vcvtq_s16_f16(tmp); + v = vsubq_f16(tmp,vcvtq_f16_s16(n)); + + + offset = vmulq_n_s16(n,(1+NB_DEG_LOGF16)); + offset = vaddq_n_s16(offset,NB_DEG_LOGF16-1); + + res = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + offset = vsubq_n_s16(offset,1); + + for(int j=NB_DEG_LOGF16-2; j >=0 ; j--) + { + lutV = vldrhq_gather_shifted_offset_f16(lut_logf16,(uint16x8_t)offset); + res = vfmaq_f16(lutV,v,res); + offset = vsubq_n_s16(offset,1); + + } + + res = vfmaq_n_f16(res,vcvtq_f16_s16(vecExpUnBiased),0.693147f16); + + + return(res); + +} + +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + + +void arm_vlog_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + f16x8_t src; + f16x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_lut_f16(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; +#else + blkCnt = blockSize; +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf16_scalar(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + + + +/** + @} end of vlog group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c new file mode 100644 index 0000000..888a11f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f32.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f32.c + * Description: Fast vectorized log + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + + +/** + @ingroup groupFastMath + */ + + +/** + @defgroup vlog Vector Log + + Compute the log values of a vector of samples. + + */ + +/** + @addtogroup vlog + @{ + */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM) || defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_f32(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + f32x4_t src; + f32x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q_f32(pSrc); + dst = vlogq_f32(src); + vst1q_f32(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; +#else + blkCnt = blockSize; +#endif +#endif + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = logf(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c new file mode 100644 index 0000000..a60fff6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_f64.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_f64.c + * Description: Fast vectorized log + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" +#include "arm_common_tables.h" + +void arm_vlog_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = log(A) */ + + /* Calculate log and store result in destination buffer. */ + *pDst++ = log(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c new file mode 100644 index 0000000..896988d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q15.c @@ -0,0 +1,264 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q15 + * Description: Q15 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/fast_math_functions.h" + + +#define LOG_Q15_ACCURACY 15 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q15_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q15_ACCURACY + which would give an integer part of -15. +*/ +#define LOG_Q15_INTEGER_PART 4 + +/* 2.0 in q14 */ +#define LOQ_Q15_THRESHOLD (1u << LOG_Q15_ACCURACY) + +/* HALF */ +#define LOQ_Q15_Q16_HALF LOQ_Q15_THRESHOLD +#define LOQ_Q15_Q14_HALF (LOQ_Q15_Q16_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in q15 */ +#define LOG_Q15_INVLOG2EXP 0x58b9u + + +/* Clay Turner algorithm */ +static uint16_t arm_scalar_log_q15(uint16_t src) +{ + int i; + + int16_t c = __CLZ(src)-16; + int16_t normalization=0; + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16_t x; + + /* q11 */ + uint16_t y=0; + + /* q11 */ + int16_t tmp; + + + /* Normalize and convert to q14 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = (((int32_t)x*x)) >> (LOG_Q15_ACCURACY - 1); + + if (x >= LOQ_Q15_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + //tmp = y - ((int32_t)normalization << (LOG_Q15_ACCURACY + 1)); + tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + + /* q4.11 */ + y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q15x8_t vlogq_q15(q15x8_t src) +{ + + int i; + + int16x8_t c = vclzq_s16(src); + int16x8_t normalization = c; + + + /* 0.5 in q11 */ + uint16_t inc = LOQ_Q15_Q16_HALF >> (LOG_Q15_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint16x8_t x; + + + /* q11 */ + uint16x8_t y = vdupq_n_u16(0); + + + /* q11 */ + int16x8_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s16(c,1); + x = vshlq_u16((uint16x8_t)src,vtmp); + + + /* Compute the Log2. Result is in q11 instead of q16 + because we know 0 <= y < 1.0 but + we want a result allowing to do a + product on int16 rather than having to go + through int32 + */ + for(i = 0; i < LOG_Q15_ACCURACY ; i++) + { + x = vmulhq_u16(x,x); + x = vshlq_n_u16(x,2); + + + p = vcmphiq_u16(x,vdupq_n_u16(LOQ_Q15_THRESHOLD)); + y = vaddq_m_n_u16(y, y,inc,p); + x = vshrq_m_n_u16(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s16(normalization,LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART); + vtmp = vsubq_s16((int16x8_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s16(vtmp,LOG_Q15_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q15 vector of log values. + @param[in] pSrc points to the input vector in q15 + @param[out] pDst points to the output vector in q4.11 + @param[in] blockSize number of samples in each vector + @return none + + */ + +void arm_vlog_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + q15x8_t src; + q15x8_t dst; + + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q15(src); + vst1q(pDst, dst); + + pSrc += 8; + pDst += 8; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 7; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++ = arm_scalar_log_q15(*pSrc++); + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of vlog group + */ diff --git a/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c new file mode 100644 index 0000000..0053859 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_vlog_q31.c @@ -0,0 +1,258 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_vlog_q31 + * Description: Q31 vector log + * + * $Date: 19 July 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/fast_math_functions.h" + +#define LOG_Q31_ACCURACY 31 + +/* Bit to represent the normalization factor + It is Ceiling[Log2[LOG_Q31_ACCURACY]] of the previous value. + The Log2 algorithm is assuming that the value x is + 1 <= x < 2. + + But input value could be as small a 2^-LOG_Q31_ACCURACY + which would give an integer part of -31. +*/ +#define LOG_Q31_INTEGER_PART 5 + +/* 2.0 in Q30 */ +#define LOQ_Q31_THRESHOLD (1u << LOG_Q31_ACCURACY) + +/* HALF */ +#define LOQ_Q31_Q32_HALF LOQ_Q31_THRESHOLD +#define LOQ_Q31_Q30_HALF (LOQ_Q31_Q32_HALF >> 2) + + +/* 1.0 / Log2[Exp[1]] in Q31 */ +#define LOG_Q31_INVLOG2EXP 0x58b90bfbuL + +/* Clay Turner algorithm */ +static uint32_t arm_scalar_log_q31(uint32_t src) +{ + int32_t i; + + int32_t c = __CLZ(src); + int32_t normalization=0; + + /* 0.5 in q26 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32_t x; + + /* q26 */ + uint32_t y=0; + + /* q26 */ + int32_t tmp; + + + /* Normalize and convert to q30 format */ + x = src; + if ((c-1) < 0) + { + x = x >> (1-c); + } + else + { + x = x << (c-1); + } + normalization = c; + + /* Compute the Log2. Result is in q26 + because we know 0 <= y < 1.0 but + do not want to use q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = ((int64_t)x*x) >> (LOG_Q31_ACCURACY - 1); + + if (x >= LOQ_Q31_THRESHOLD) + { + y += inc ; + x = x >> 1; + } + inc = inc >> 1; + } + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q26 */ + tmp = (int32_t)y - (normalization << (LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART)); + + + /* q5.26 */ + y = ((int64_t)tmp * LOG_Q31_INVLOG2EXP) >> 31; + + + + return(y); + +} + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + +q31x4_t vlogq_q31(q31x4_t src) +{ + + int32_t i; + + int32x4_t c = vclzq_s32(src); + int32x4_t normalization = c; + + + /* 0.5 in q11 */ + uint32_t inc = LOQ_Q31_Q32_HALF >> (LOG_Q31_INTEGER_PART + 1); + + /* Will compute y = log2(x) for 1 <= x < 2.0 */ + uint32x4_t x; + + + /* q11 */ + uint32x4_t y = vdupq_n_u32(0); + + + /* q11 */ + int32x4_t vtmp; + + + mve_pred16_t p; + + /* Normalize and convert to q14 format */ + + + vtmp = vsubq_n_s32(c,1); + x = vshlq_u32((uint32x4_t)src,vtmp); + + + /* Compute the Log2. Result is in Q26 + because we know 0 <= y < 1.0 but + do not want to use Q32 to allow + following computation with less instructions. + */ + for(i = 0; i < LOG_Q31_ACCURACY ; i++) + { + x = vmulhq_u32(x,x); + x = vshlq_n_u32(x,2); + + + p = vcmphiq_u32(x,vdupq_n_u32(LOQ_Q31_THRESHOLD)); + y = vaddq_m_n_u32(y, y,inc,p); + x = vshrq_m_n_u32(x,x,1,p); + + inc = inc >> 1; + } + + + /* + Convert the Log2 to Log and apply normalization. + We compute (y - normalisation) * (1 / Log2[e]). + + */ + + /* q11 */ + // tmp = (int16_t)y - (normalization << (LOG_Q15_ACCURACY - LOG_Q15_INTEGER_PART)); + vtmp = vshlq_n_s32(normalization,LOG_Q31_ACCURACY - LOG_Q31_INTEGER_PART); + vtmp = vsubq_s32((int32x4_t)y,vtmp); + + + + /* q4.11 */ + // y = ((int32_t)tmp * LOG_Q15_INVLOG2EXP) >> 15; + vtmp = vqdmulhq_n_s32(vtmp,LOG_Q31_INVLOG2EXP); + + return(vtmp); +} +#endif + +/** + @ingroup groupFastMath + */ + +/** + @addtogroup vlog + @{ + */ + +/** + @brief q31 vector of log values. + @param[in] pSrc points to the input vector in q31 + @param[out] pDst points to the output vector q5.26 + @param[in] blockSize number of samples in each vector + @return none + + */ +void arm_vlog_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + q31x4_t src; + q31x4_t dst; + + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + src = vld1q(pSrc); + dst = vlogq_q31(src); + vst1q(pDst, dst); + + pSrc += 4; + pDst += 4; + /* Decrement loop counter */ + blkCnt--; + } + + blkCnt = blockSize & 3; + #else + blkCnt = blockSize; + #endif + + while (blkCnt > 0U) + { + *pDst++=arm_scalar_log_q31(*pSrc++); + + blkCnt--; + } + +} + +/** + @} end of vlog group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt new file mode 100644 index 0000000..9f6ea5d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/CMakeLists.txt @@ -0,0 +1,148 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPFiltering) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPFiltering STATIC) + +include(interpol) +interpol(CMSISDSPFiltering) + +configLib(CMSISDSPFiltering ${ROOT}) +configDsp(CMSISDSPFiltering ${ROOT}) + +if (CONFIGTABLE AND ALLFAST) +target_compile_definitions(CMSISDSPFiltering PUBLIC ARM_ALL_FAST_TABLES) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q31) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFAST OR ARM_LMS_NORM_Q15) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_q15.c) +endif() + +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_32x64_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_partial_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_conv_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_opt_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_decimate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_fast_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f64.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_interpolate_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_init_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_sparse_q7.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_iir_lattice_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_init_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_init_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_norm_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q15.c) +target_sources(CMSISDSPFiltering PRIVATE arm_lms_q31.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_f32.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_q31.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_fir_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df1_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_df2T_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_biquad_cascade_stereo_df2T_init_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_correlate_f16.c) +target_sources(CMSISDSPFiltering PRIVATE arm_levinson_durbin_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPFiltering PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c new file mode 100644 index 0000000..e1b26fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_biquad_cascade_df1_32x64_init_q31.c" +#include "arm_biquad_cascade_df1_32x64_q31.c" +#include "arm_biquad_cascade_df1_f32.c" +#include "arm_biquad_cascade_df1_fast_q15.c" +#include "arm_biquad_cascade_df1_fast_q31.c" +#include "arm_biquad_cascade_df1_init_f32.c" +#include "arm_biquad_cascade_df1_init_q15.c" +#include "arm_biquad_cascade_df1_init_q31.c" +#include "arm_biquad_cascade_df1_q15.c" +#include "arm_biquad_cascade_df1_q31.c" +#include "arm_biquad_cascade_df2T_f32.c" +#include "arm_biquad_cascade_df2T_f64.c" +#include "arm_biquad_cascade_df2T_init_f32.c" +#include "arm_biquad_cascade_df2T_init_f64.c" +#include "arm_biquad_cascade_stereo_df2T_f32.c" +#include "arm_biquad_cascade_stereo_df2T_init_f32.c" +#include "arm_conv_f32.c" +#include "arm_conv_fast_opt_q15.c" +#include "arm_conv_fast_q15.c" +#include "arm_conv_fast_q31.c" +#include "arm_conv_opt_q15.c" +#include "arm_conv_opt_q7.c" +#include "arm_conv_partial_f32.c" +#include "arm_conv_partial_fast_opt_q15.c" +#include "arm_conv_partial_fast_q15.c" +#include "arm_conv_partial_fast_q31.c" +#include "arm_conv_partial_opt_q15.c" +#include "arm_conv_partial_opt_q7.c" +#include "arm_conv_partial_q15.c" +#include "arm_conv_partial_q31.c" +#include "arm_conv_partial_q7.c" +#include "arm_conv_q15.c" +#include "arm_conv_q31.c" +#include "arm_conv_q7.c" +#include "arm_correlate_f32.c" +#include "arm_correlate_f64.c" +#include "arm_correlate_fast_opt_q15.c" +#include "arm_correlate_fast_q15.c" +#include "arm_correlate_fast_q31.c" +#include "arm_correlate_opt_q15.c" +#include "arm_correlate_opt_q7.c" +#include "arm_correlate_q15.c" +#include "arm_correlate_q31.c" +#include "arm_correlate_q7.c" +#include "arm_fir_decimate_f32.c" +#include "arm_fir_decimate_fast_q15.c" +#include "arm_fir_decimate_fast_q31.c" +#include "arm_fir_decimate_init_f32.c" +#include "arm_fir_decimate_init_q15.c" +#include "arm_fir_decimate_init_q31.c" +#include "arm_fir_decimate_q15.c" +#include "arm_fir_decimate_q31.c" +#include "arm_fir_f32.c" +#include "arm_fir_f64.c" +#include "arm_fir_fast_q15.c" +#include "arm_fir_fast_q31.c" +#include "arm_fir_init_f32.c" +#include "arm_fir_init_f64.c" +#include "arm_fir_init_q15.c" +#include "arm_fir_init_q31.c" +#include "arm_fir_init_q7.c" +#include "arm_fir_interpolate_f32.c" +#include "arm_fir_interpolate_init_f32.c" +#include "arm_fir_interpolate_init_q15.c" +#include "arm_fir_interpolate_init_q31.c" +#include "arm_fir_interpolate_q15.c" +#include "arm_fir_interpolate_q31.c" +#include "arm_fir_lattice_f32.c" +#include "arm_fir_lattice_init_f32.c" +#include "arm_fir_lattice_init_q15.c" +#include "arm_fir_lattice_init_q31.c" +#include "arm_fir_lattice_q15.c" +#include "arm_fir_lattice_q31.c" +#include "arm_fir_q15.c" +#include "arm_fir_q31.c" +#include "arm_fir_q7.c" +#include "arm_fir_sparse_f32.c" +#include "arm_fir_sparse_init_f32.c" +#include "arm_fir_sparse_init_q15.c" +#include "arm_fir_sparse_init_q31.c" +#include "arm_fir_sparse_init_q7.c" +#include "arm_fir_sparse_q15.c" +#include "arm_fir_sparse_q31.c" +#include "arm_fir_sparse_q7.c" +#include "arm_iir_lattice_f32.c" +#include "arm_iir_lattice_init_f32.c" +#include "arm_iir_lattice_init_q15.c" +#include "arm_iir_lattice_init_q31.c" +#include "arm_iir_lattice_q15.c" +#include "arm_iir_lattice_q31.c" +#include "arm_lms_f32.c" +#include "arm_lms_init_f32.c" +#include "arm_lms_init_q15.c" +#include "arm_lms_init_q31.c" +#include "arm_lms_norm_f32.c" +#include "arm_lms_norm_init_f32.c" +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) +#include "arm_lms_norm_init_q15.c" +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) +#include "arm_lms_norm_init_q31.c" +#endif +#endif +#include "arm_lms_norm_q15.c" +#include "arm_lms_norm_q31.c" +#include "arm_lms_q15.c" +#include "arm_lms_q31.c" + +#include "arm_levinson_durbin_f32.c" +#include "arm_levinson_durbin_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c new file mode 100644 index 0000000..759e405 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: FilteringFunctions.c + * Description: Combination of all filtering function f16 source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_fir_f16.c" +#include "arm_fir_init_f16.c" +#include "arm_biquad_cascade_df1_f16.c" +#include "arm_biquad_cascade_df1_init_f16.c" +#include "arm_biquad_cascade_df2T_f16.c" +#include "arm_biquad_cascade_df2T_init_f16.c" +#include "arm_biquad_cascade_stereo_df2T_f16.c" +#include "arm_biquad_cascade_stereo_df2T_init_f16.c" +#include "arm_correlate_f16.c" +#include "arm_levinson_durbin_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c new file mode 100644 index 0000000..565b494 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_init_q31.c + * Description: High precision Q31 Biquad cascade filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade 32x64 filter. + @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array and size of each state variable is 1.63 format. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the state array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c new file mode 100644 index 0000000..2c8c911 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c @@ -0,0 +1,807 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_32x64_q31.c + * Description: High precision Q31 Biquad cascade filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter + + This function implements a high precision Biquad cascade filter which operates on + Q31 data values. The filter coefficients are in 1.31 format and the state variables + are in 1.63 format. The double precision state variables reduce quantization noise + in the filter and provide a cleaner output. + These filters are particularly useful when implementing filters in which the + singularities are close to the unit circle. This is common for low pass or high + pass filters with very low cutoff frequencies. + + The function operates on blocks of input and output data + and each call to the function processes blockSize samples through + the filter. pSrc and pDst points to input and output arrays + containing blockSize Q31 values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages + with the coefficients for one of the stages configured as a first order filter + (b2=0 and a2=0). + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision. + The state variables are arranged in the array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values of data in 1.63 format. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Function + There is also an associated initialization function which performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the filter instance structure use + 
+      arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied which is described in detail below. + @par Fixed-Point Behavior + Care must be taken while using Biquad Cascade 32x64 filter function. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par + Filter coefficients are represented as fractional values and + restricted to lie in the range [-1 +1). + The processing function has an additional scaling parameter postShift + which allows the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the Coefficient array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + @par + The second thing to keep in mind is the gain through the filter. + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the + filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 + and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 + or the input signal must be scaled down so that the combination of input and filter are never overflowed. + @par + The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version. + This is described in the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1_32x64 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade 32x64 filter. + @param[in] S points to an instance of the high precision Q31 Biquad cascade filter + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Details + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @par + Two related functions are provided in the CMSIS DSP library. + - \ref arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator. + - \ref arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_biquad_cas_df1_32x64_q31_scalar(const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31x4_t vecCoef, vecIn; + q63_t acc; + + if (blockSize <= 3) + { + arm_biquad_cas_df1_32x64_q31_scalar(S,pSrc,pDst,blockSize); + } + else + { + do + { + uint32_t i; + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + vecCoef[0] = 0; + vecCoef[1] = b2; + vecCoef[2] = b1; + vecCoef[3] = b0; + /* + * Reading the state values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* + * append history with initial samples + */ + q31_t hist[6]; + hist[0] = 0; + hist[1] = Xn2; + hist[2] = Xn1; + hist[3] = pIn[0]; + hist[4] = pIn[1]; + hist[5] = pIn[2]; + + const q31_t *pIn1 = hist; + q31x4_t vecIn0 = *(q31x4_t *) & pIn[0]; + q31x4_t vecIn1 = *(q31x4_t *) & pIn[1]; + q31x4_t vecIn2 = *(q31x4_t *) & pIn[2]; + + i = 3; + do + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + } + while (--i); + + sample = blockSize - 3; + pIn1 = pIn + 3; + + i = sample / 4; + while (i > 0U) + { + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + vecIn = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + /* + * Store the output in the destination buffer in 1.31 format. + */ + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + vecIn0 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + vecIn1 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn, vecCoef); + vecIn2 = vld1q(pIn1); + pIn1 += 1; + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * Decrement the loop counter + */ + i--; + } + /* + * save input state + */ + Xn2 = vecIn[2]; + Xn1 = vecIn[3]; + + int loopRemainder = blockSize - 3 - 4 * ((blockSize - 3) / 4); + if (loopRemainder == 1) + { + /* + * remainder + */ + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn0[2]; + Xn1 = vecIn0[3]; + + } + else if (loopRemainder == 2) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn1[2]; + Xn1 = vecIn1[3]; + + } + else if (loopRemainder == 3) + { + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn0, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn1, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + + acc = mult32x64(Yn1, a1); + acc += mult32x64(Yn2, a2); + Yn2 = Yn1; + Yn1 = acc; + Yn1 = vmlaldavaq(Yn1, vecIn2, vecCoef); + Yn1 = asrl(Yn1, -shift); + *pOut++ = (q31_t) (Yn1 >> 32); + /* + * save input state + */ + Xn2 = vecIn2[2]; + Xn1 = vecIn2[3]; + + } + + /* + * The first stage output is given as input to the second stage. + */ + pIn = pDst; + /* + * Reset to destination buffer working pointer + */ + pOut = pDst; + /* + * Store the updated state variables back into the pState array + */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + } + while (--stage); + } +} +#else +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + q63_t *pState = S->pState; /* state pointer initialization */ + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q63_t acc; /* accumulator */ + q31_t Xn1, Xn2; /* Input Filter state variables */ + q63_t Yn1, Yn2; /* Output Filter state variables */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn; /* temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* loop counters */ + q31_t acc_l, acc_h; /* temporary output */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = (q31_t) (pState[0]); + Xn2 = (q31_t) (pState[1]); + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output value that is being computed and stored in destination buffer + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut = acc_h; + + /* Read the second input into Xn2, to reuse the value */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc += b1 * x[n-1] */ + acc = (q63_t) Xn * b1; + + /* acc = b0 * x[n] */ + acc += (q63_t) Xn2 * b0; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn1 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Read the third input into Xn1, to reuse the value */ + Xn1 = *pIn++; + + /* The result is converted to 1.31 */ + /* Store the output in the destination buffer. */ + *(pOut + 1U) = acc_h; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn1 * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn2 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* The result is converted to 1.63, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 2U) = acc_h; + + /* Read the fourth input into Xn, to reuse the value */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn2, a1); + + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn1, a2); + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *(pOut + 3U) = acc_h; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* update output pointer */ + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + + /* acc = b0 * x[n] */ + acc = (q63_t) Xn * b0; + /* acc += b1 * x[n-1] */ + acc += (q63_t) Xn1 * b1; + /* acc += b[2] * x[n-2] */ + acc += (q63_t) Xn2 * b2; + /* acc += a1 * y[n-1] */ + acc += mult32x64(Yn1, a1); + /* acc += a2 * y[n-2] */ + acc += mult32x64(Yn2, a2); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + + /* The result is converted to 1.63, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the output in the destination buffer in 1.31 format. */ + *pOut++ = acc_h; + /* Yn1 = acc << shift; */ + + /* Store the output in the destination buffer in 1.31 format. */ +/* *pOut++ = (q31_t) (acc >> (32 - shift)); */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage output is given as input to the second stage. */ + pIn = pDst; + + /* Reset to destination buffer working pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = (q63_t) Xn1; + *pState++ = (q63_t) Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1_32x64 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c new file mode 100644 index 0000000..c1ac140 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f16.c @@ -0,0 +1,491 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f16.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float16_t X0, X1, X2, X3; /* temporary input */ + float16_t X4, X5, X6, X7; /* temporary input */ + _Float16 lastX, lastY; /* X,Y history for tail handling */ + f16x8_t coeffs; + f16x8_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 3U; + + /* + * First part of the processing with loop unrolling. Compute 8 outputs at a time. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 8; + + /* + * update recurrence + */ + Xn1 = X7; + Xn2 = X6; + Yn1 = vgetq_lane(accVec, 7); + Yn2 = vgetq_lane(accVec, 6); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 8, + * compute any remaining output samples here. + */ + sample = blockSize & 0x7U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X7; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + X4 = *pIn++; + X5 = *pIn++; + X6 = *pIn++; + X7 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X7); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X6); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, X5); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, X4); + + coeffs = vld1q(&pCoeffs[32]); + accVec = vfmaq(accVec, coeffs, X3); + + coeffs = vld1q(&pCoeffs[40]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[48]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[56]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[64]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[72]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[80]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[88]); + accVec = vfmaq(accVec, coeffs, Yn2); + + switch(sample) + { + case 1: + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + break; + case 2: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + break; + case 3: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + break; + + case 4: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + break; + + case 5: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + Xn1 = X4; + Xn2 = X3; + Yn1 = vgetq_lane(accVec, 4); + Yn2 = vgetq_lane(accVec, 3); + break; + + case 6: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + Xn1 = X5; + Xn2 = X4; + Yn1 = vgetq_lane(accVec, 5); + Yn2 = vgetq_lane(accVec, 4); + break; + + case 7: + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + *pOut++ = vgetq_lane(accVec, 3); + *pOut++ = vgetq_lane(accVec, 4); + *pOut++ = vgetq_lane(accVec, 5); + *pOut++ = vgetq_lane(accVec, 6); + Xn1 = X6; + Xn2 = X5; + Yn1 = vgetq_lane(accVec, 6); + Yn2 = vgetq_lane(accVec, 5); + break; + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f16) / sizeof(float16_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else +void arm_biquad_cascade_df1_f16( + const arm_biquad_casd_df1_inst_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* pState pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + _Float16 Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#endif /*#if defined(ARM_FLOAT16_SUPPORTED)*/ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c new file mode 100644 index 0000000..77d862b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c @@ -0,0 +1,684 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_f32.c + * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure + + This set of functions implements arbitrary order recursive (IIR) filters. + The filters are implemented as a cascade of second order Biquad sections. + The functions support Q15, Q31 and floating-point data types. + Fast version of Q15 and Q31 also available. + + The functions operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage. + \image html Biquad.gif "Single Biquad filter stage" + Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools use the difference equation + 
+      y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 + must be negated when used with the CMSIS DSP Library. + + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages" + A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ + @par + The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Init Function + There is also an associated initialization function for each data type. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+      arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; + postShift shift to be applied. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions. + Following issues must be considered: + - Scaling of coefficients + - Filter gain + - Overflow and saturation + + @par Scaling of coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift + which allow the filter coefficients to exceed the range [+1 -1). + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator" + This essentially scales the filter coefficients by 2^postShift. + For example, to realize the coefficients + 
+     {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the pCoeffs array to: + 
+     {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1 + + @par Filter gain + The frequency response of a Biquad filter is a function of its coefficients. + It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies. + This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter. + To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed. + + @par Overflow and saturation + For Q15 and Q31 versions, it is described separately as part of the function specific documentation below. + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] S points to an instance of the floating-point Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t lastX, lastY; /* X,Y history for tail handling */ + float32_t X0, X1, X2, X3; /* temporary input */ + f32x4_t coeffs; + f32x4_t accVec; /* accumultor vector */ + uint32_t sample, stage = S->numStages; /* loop counters */ + + do + { + /* + * Reading the pState values + */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + sample = blockSize >> 2U; + + /* + * First part of the processing with loop unrolling. Compute 4 outputs at a time. + * second loop below computes the remaining 1 to 3 samples. + */ + while (sample > 0U) + { + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + /* + * Store the result in the accumulator in the destination buffer. + */ + vst1q(pOut, accVec); + pOut += 4; + + /* + * update recurrence + */ + Xn1 = X3; + Xn2 = X2; + Yn1 = vgetq_lane(accVec, 3); + Yn2 = vgetq_lane(accVec, 2); + /* + * decrement the loop counter + */ + sample--; + } + + /* + * If the blockSize is not a multiple of 4, + * compute any remaining output samples here. + */ + sample = blockSize & 0x3U; + if (sample) + { + /* save previous X, Y for modulo 1 length case */ + lastX = X3; + lastY = Yn1; + + X0 = *pIn++; + X1 = *pIn++; + X2 = *pIn++; + X3 = *pIn++; + + coeffs = vld1q(pCoeffs); + accVec = vmulq(coeffs, X3); + + coeffs = vld1q(&pCoeffs[4]); + accVec = vfmaq(accVec, coeffs, X2); + + coeffs = vld1q(&pCoeffs[8]); + accVec = vfmaq(accVec, coeffs, X1); + + coeffs = vld1q(&pCoeffs[12]); + accVec = vfmaq(accVec, coeffs, X0); + + coeffs = vld1q(&pCoeffs[16]); + accVec = vfmaq(accVec, coeffs, Xn1); + + coeffs = vld1q(&pCoeffs[20]); + accVec = vfmaq(accVec, coeffs, Xn2); + + coeffs = vld1q(&pCoeffs[24]); + accVec = vfmaq(accVec, coeffs, Yn1); + + coeffs = vld1q(&pCoeffs[28]); + accVec = vfmaq(accVec, coeffs, Yn2); + + if (sample == 1) + { + *pOut++ = vgetq_lane(accVec, 0); + Xn1 = X0; + Xn2 = lastX; + Yn1 = vgetq_lane(accVec, 0); + Yn2 = lastY; + } + else if (sample == 2) + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + Xn1 = X1; + Xn2 = X0; + Yn1 = vgetq_lane(accVec, 1); + Yn2 = vgetq_lane(accVec, 0); + } + else + { + *pOut++ = vgetq_lane(accVec, 0); + *pOut++ = vgetq_lane(accVec, 1); + *pOut++ = vgetq_lane(accVec, 2); + Xn1 = X2; + Xn2 = X1; + Yn1 = vgetq_lane(accVec, 2); + Yn2 = vgetq_lane(accVec, 1); + } + } + /* + * Store the updated state variables back into the pState array + */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + pCoeffs += sizeof(arm_biquad_mod_coef_f32) / sizeof(float32_t); + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent numStages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset the output pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc; /* Simulates the accumulator */ + + uint32_t sample, stage = S->numStages; /* loop counters */ + + float32x4_t Xn; + float32x2_t Yn; + float32x2_t a; + float32x4_t b; + + float32x4_t x,tmp; + float32x2_t t; + float32x2x2_t y; + + float32_t Xns; + + while (stage > 0U) + { + /* Reading the coefficients */ + Xn = vdupq_n_f32(0.0f); + + Xn = vsetq_lane_f32(pState[0],Xn,2); + Xn = vsetq_lane_f32(pState[1],Xn,3); + Yn = vset_lane_f32(pState[2],Yn,0); + Yn = vset_lane_f32(pState[3],Yn,1); + + b = vld1q_f32(pCoeffs); + b = vrev64q_f32(b); + b = vcombine_f32(vget_high_f32(b), vget_low_f32(b)); + + a = vld1_f32(pCoeffs + 3); + a = vrev64_f32(a); + b = vsetq_lane_f32(0.0f,b,0); + pCoeffs += 5; + + /* Reading the pState values */ + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first 4 inputs */ + x = vld1q_f32(pIn); + + pIn += 4; + + tmp = vextq_f32(Xn, x, 1); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + tmp = vextq_f32(Xn, x, 2); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[0] = Yn; + + tmp = vextq_f32(Xn, x, 3); + t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + Xn = x; + t = vmul_f32(vget_high_f32(b), vget_high_f32(Xn)); + t = vmla_f32(t, vget_low_f32(b), vget_low_f32(Xn)); + t = vmla_f32(t, a, Yn); + t = vpadd_f32(t, t); + Yn = vext_f32(Yn, t, 1); + + y.val[1] = Yn; + + tmp = vcombine_f32(y.val[0], y.val[1]); + + /* Store the 4 outputs and increment the pointer */ + vst1q_f32(pOut, tmp); + pOut += 4; + + /* Decrement the loop counter */ + sample--; + } + + + /* If the block size is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + sample = blockSize & 0x3U; + + while (sample > 0U) + { + /* Read the input */ + Xns = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (vgetq_lane_f32(b, 1) * vgetq_lane_f32(Xn, 2)) + + (vgetq_lane_f32(b, 2) * vgetq_lane_f32(Xn, 3)) + + (vgetq_lane_f32(b, 3) * Xns) + + (vget_lane_f32(a, 0) * vget_lane_f32(Yn, 0)) + + (vget_lane_f32(a, 1) * vget_lane_f32(Yn, 1)); + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn = vsetq_lane_f32(vgetq_lane_f32(Xn, 3),Xn,2); + Xn = vsetq_lane_f32(Xns,Xn,3); + Yn = vset_lane_f32(vget_lane_f32(Yn, 1),Yn,0); + Yn = vset_lane_f32(acc,Yn,1); + + /* Decrement the loop counter */ + sample--; + + } + + vst1q_f32(pState,vcombine_f32((vget_high_f32(Xn)),(Yn))); + pState += 4; + /* Store the updated state variables back into the pState array */ + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + } +} + +#else +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* pState pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + float32_t Xn; /* Temporary input */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1); + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2); + + /* Store output in destination buffer. */ + *pOut++ = acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c new file mode 100644 index 0000000..f2dd334 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q15.c + * Description: Fast processing function for the Q15 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). + The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_q15() for a slower implementation of this function + which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q15() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc; /* Accumulator */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia (&pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia (&pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia (&pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 2 outputs at a time */ + sample = blockSize >> 1U; + + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia (&pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x1U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */ + acc = __SMLAD(b1, state_in, out); + /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */ + acc = __SMLAD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 and then saturation is applied */ + out = __SSAT((acc >> shift), 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent (numStages - 1) occur in-place in the output buffer */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia(&pState, state_in); + write_q15x2_ia(&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c new file mode 100644 index 0000000..cefa592 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c @@ -0,0 +1,296 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_fast_q31.c + * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter (fast variant). + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process per call + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function + arm_biquad_cascade_df1_init_q31() to initialize filter structure. + @remark + Refer to \ref arm_biquad_cascade_df1_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use the function \ref arm_biquad_cascade_df1_init_q31() to initialize the filter structure. + */ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t acc = 0; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variables acc ... acc3 hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/ + mult_32x32_keep32_R(acc, b1, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b0, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the second input */ + Xn2 = *(pIn + 1U); + + /* Store the output in the destination buffer. */ + *pOut = Yn2; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn2); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn1); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Read the third input */ + Xn1 = *(pIn + 2U); + + /* Store the output in the destination buffer. */ + *(pOut + 1U) = Yn1; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn1); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn2); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + Yn2 = acc << shift; + + /* Read the forth input */ + Xn = *(pIn + 3U); + + /* Store the output in the destination buffer. */ + *(pOut + 2U) = Yn2; + pIn += 4U; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn2); + /* acc += a2 * y[n-2] */ + /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn1); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + Xn2 = Xn1; + + /* The result is converted to 1.31, Yn1 variable is reused */ + Yn1 = acc << shift; + + /* Xn1 = Xn */ + Xn1 = Xn; + + /* Store the output in the destination buffer. */ + *(pOut + 3U) = Yn1; + pOut += 4U; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = (blockSize & 0x3U); + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/ + mult_32x32_keep32_R(acc, b0, Xn); + /* acc += b1 * x[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b1, Xn1); + /* acc += b[2] * x[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, b2, Xn2); + /* acc += a1 * y[n-1] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a1, Yn1); + /* acc += a2 * y[n-2] */ + /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/ + multAcc_32x32_keep32_R(acc, a2, Yn2); + + /* The result is converted to 1.31 */ + acc = acc << shift; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = acc; + + /* Store the output in the destination buffer. */ + *pOut++ = acc; + + /* decrement loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c new file mode 100644 index 0000000..d18dd3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f16.c @@ -0,0 +1,166 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f16.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f16. + So, its total size is 96*numStages float16_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f16. + */ + + +void arm_biquad_cascade_df1_init_f16( + arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +/* + +The computation of the coefficients is done in float32 otherwise the +resulting filter is too different from the expected one. + +*/ +static void generateCoefsFastBiquadF16(float16_t b0, float16_t b1, float16_t b2, float16_t a1, float16_t a2, + arm_biquad_mod_coef_f16 * newCoef) +{ + float32_t coeffs[8][12] = { + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, (float32_t)a1, (float32_t)a2}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, (float32_t)a2, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, 0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {0.0f, (float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f}, + {(float32_t)b0, (float32_t)b1, (float32_t)b2, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f} + }; + + for (int i = 0; i < 12; i++) + { + coeffs[1][i] += ((float32_t)a1 * coeffs[0][i]); + coeffs[2][i] += ((float32_t)a1 * coeffs[1][i]) + ((float32_t)a2 * coeffs[0][i]); + coeffs[3][i] += ((float32_t)a1 * coeffs[2][i]) + ((float32_t)a2 * coeffs[1][i]); + coeffs[4][i] += ((float32_t)a1 * coeffs[3][i]) + ((float32_t)a2 * coeffs[2][i]); + coeffs[5][i] += ((float32_t)a1 * coeffs[4][i]) + ((float32_t)a2 * coeffs[3][i]); + coeffs[6][i] += ((float32_t)a1 * coeffs[5][i]) + ((float32_t)a2 * coeffs[4][i]); + coeffs[7][i] += ((float32_t)a1 * coeffs[6][i]) + ((float32_t)a2 * coeffs[5][i]); + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float16_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float16_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float16_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float16_t) coeffs[3][i]; + newCoef->coeffs[i][4] = (float16_t) coeffs[4][i]; + newCoef->coeffs[i][5] = (float16_t) coeffs[5][i]; + newCoef->coeffs[i][6] = (float16_t) coeffs[6][i]; + newCoef->coeffs[i][7] = (float16_t) coeffs[7][i]; + + } +} + +void arm_biquad_cascade_df1_mve_init_f16(arm_biquad_casd_df1_inst_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + arm_biquad_mod_coef_f16 * pCoeffsMod, + float16_t * pState) +{ + arm_biquad_cascade_df1_init_f16(S, numStages, (float16_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF16(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} + +#endif + +/** + @} end of BiquadCascadeDF1 group + */ +#endif /* #if defined(ARMfloat16_t_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c new file mode 100644 index 0000000..1614594 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_f32.c + * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par For MVE code, an additional buffer of modified coefficients is required. + Its size is numStages and each element of this buffer has type arm_biquad_mod_coef_f32. + So, its total size is 32*numStages float32_t elements. + + The initialization function which must be used is arm_biquad_cascade_df1_mve_init_f32. + */ + + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +static void generateCoefsFastBiquadF32(float32_t b0, float32_t b1, float32_t b2, float32_t a1, float32_t a2, + arm_biquad_mod_coef_f32 * newCoef) +{ + float32_t coeffs[4][8] = { + {0, 0, 0, b0, b1, b2, a1, a2}, + {0, 0, b0, b1, b2, 0, a2, 0}, + {0, b0, b1, b2, 0, 0, 0, 0}, + {b0, b1, b2, 0, 0, 0, 0, 0}, + }; + + for (int i = 0; i < 8; i++) + { + coeffs[1][i] += a1 * coeffs[0][i]; + coeffs[2][i] += a1 * coeffs[1][i] + a2 * coeffs[0][i]; + coeffs[3][i] += a1 * coeffs[2][i] + a2 * coeffs[1][i]; + + /* + * transpose + */ + newCoef->coeffs[i][0] = (float32_t) coeffs[0][i]; + newCoef->coeffs[i][1] = (float32_t) coeffs[1][i]; + newCoef->coeffs[i][2] = (float32_t) coeffs[2][i]; + newCoef->coeffs[i][3] = (float32_t) coeffs[3][i]; + } +} + +void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState) +{ + arm_biquad_cascade_df1_init_f32(S, numStages, (float32_t *)pCoeffsMod, pState); + + /* Generate SIMD friendly modified coefs */ + for (int i = 0; i < numStages; i++) + { + generateCoefsFastBiquadF32(pCoeffs[0], pCoeffs[1], pCoeffs[2], pCoeffs[3], pCoeffs[4], pCoeffsMod); + pCoeffs += 5; + pCoeffsMod++; + } +} +#endif + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c new file mode 100644 index 0000000..0fa3825 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q15.c + * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 6*numStages values. + The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4. + @par + The state variables are stored in the array pState. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c new file mode 100644 index 0000000..2b3cb62 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_init_q31.c + * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState points to state variables array. + Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2]. + The state variables are arranged in the pState array as: + 
+      {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on. + The state array has a total length of 4*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign postShift to be applied to the output */ + S->postShift = postShift; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c new file mode 100644 index 0000000..c77a05c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c @@ -0,0 +1,618 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q15.c + * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] S points to an instance of the Q15 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the location where the output result is written + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits. + Finally, the result is saturated to 1.15 format. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* input pointer initialization */ + q15_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t sample, stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q15x8_t bCoeffs0, bCoeffs1, bCoeffs2, bCoeffs3; /* Coefficients vector */ + q15_t *pState = S->pState; /* pState pointer initialization */ + q15x8_t inVec0; + int64_t acc; + const q15_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + shift = (15 - postShift) - 32; + + do { + q15_t a2 = pCoeffs[5]; + q15_t a1 = pCoeffs[4]; + + bCoeffs0 = vdupq_n_s16(0); + bCoeffs0[0] = pCoeffs[3]; // b2 + bCoeffs0[1] = pCoeffs[2]; // b1 + bCoeffs0[2] = pCoeffs[0]; // b0 + + uint32_t zero = 0; + bCoeffs1 = bCoeffs0; + bCoeffs1 = vshlcq_s16(bCoeffs1, &zero, 16); + + bCoeffs2 = bCoeffs1; + bCoeffs2 = vshlcq_s16(bCoeffs2, &zero, 16); + + bCoeffs3 = bCoeffs2; + bCoeffs3 = vshlcq_s16(bCoeffs3, &zero, 16); + + bCoeffs0[6] = a2; + bCoeffs0[7] = a1; + bCoeffs1[7] = a2; + bCoeffs1[6] = a1; + + bCoeffs2 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs0, 3), (q31x4_t) bCoeffs2, 3); + bCoeffs3 = + vsetq_lane_s32(vgetq_lane_s32((q31x4_t) bCoeffs1, 3), (q31x4_t) bCoeffs3, 3); + + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + pIn += 2; + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + inVec0[6] = pState[3]; + inVec0[7] = pState[2]; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0[7] = out; + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0[6] = out1; + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + /* + * main loop + */ + sample = (blockSize - 4) >> 2U; + /* preload (efficient scheduling) */ + inVec0 = vld1q(pIn); + pIn += 4; + + /* + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + inVec0[6] = out1; + inVec0[7] = out; + + /* store */ + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * in { x0 x1 x2 x3 x4 x5 yn2 yn1 } + * x + * bCoeffs0 { b2 b1 b0 0 0 0 a2 a1 } + * + */ + acc = vmlaldavq(bCoeffs0, inVec0); + /* shift + saturate to 16 bit */ + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yn1 } + * x + * bCoeffs1 { 0 b2 b1 b0 0 0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + + inVec0[7] = out; + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 b2 b1 b0 0 a2 a1 } + */ + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + /* + * in { x0 x1 x2 x3 x4 x5 y0 yp1 } + * x + * bCoeffs2 { 0 0 0 b2 b1 b0 a1 a2 } + */ + acc = vmlaldavq(bCoeffs3, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 4; + + /* decrement the loop counter */ + sample--; + } + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + + if (loopRemainder == 3) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + inVec0[7] = out; + acc = vmlaldavq(bCoeffs2, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 4); + pState[1] = vgetq_lane_s16(inVec0, 3); + pState[3] = out; + pState[2] = out1; + + } else if (loopRemainder == 2) { + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + inVec0[6] = out1; + + acc = vmlaldavq(bCoeffs1, inVec0); + acc = sqrshrl_sat48(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = (q15_t) out1; + *pOut++ = (q15_t) out; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 3); + pState[1] = vgetq_lane_s16(inVec0, 2); + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 1) { + + inVec0[6] = out1; + inVec0[7] = out; + + acc = vmlaldavq(bCoeffs0, inVec0); + acc = sqrshrl_sat48(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + *pOut++ = (q15_t) out1; + + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 2); + pState[1] = vgetq_lane_s16(inVec0, 1); + pState[3] = out; + pState[2] = out1; + + + } else { + /* Store the updated state variables back into the pState array */ + pState[0] = vgetq_lane_s16(inVec0, 1); + pState[1] = vgetq_lane_s16(inVec0, 0); + pState[3] = out1; + pState[2] = out; + } + + pState += 4; + pCoeffs += 6; + + /* + * The first stage goes from the input buffer to the output buffer. + * Subsequent stages occur in-place in the output buffer + */ + pIn = pDst; + /* + * Reset to destination pointer + */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q31_t in; /* Temporary variable to hold input value */ + q31_t out; /* Temporary variable to hold output value */ + q31_t b0; /* Temporary variable to hold bo value */ + q31_t b1, a1; /* Filter coefficients */ + q31_t state_in, state_out; /* Filter state variables */ + q31_t acc_l, acc_h; + q63_t acc; /* Accumulator */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + int32_t uShift = (32 - lShift); + + do + { + /* Read the b0 and 0 coefficients using SIMD */ + b0 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the b1 and b2 coefficients using SIMD */ + b1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the a1 and a2 coefficients using SIMD */ + a1 = read_q15x2_ia ((q15_t **) &pCoeffs); + + /* Read the input state values from the state buffer: x[n-1], x[n-2] */ + state_in = read_q15x2_ia (&pState); + + /* Read the output state values from the state buffer: y[n-1], y[n-2] */ + state_out = read_q15x2_da (&pState); + + /* Apply loop unrolling and compute 2 output values simultaneously. */ + /* The variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + sample = blockSize >> 1U; + + /* First part of the processing with loop unrolling. Compute 2 outputs at a time. + ** a second loop below computes the remaining 1 sample. */ + while (sample > 0U) + { + + /* Read the input */ + in = read_q15x2_ia ((q15_t **) &pIn); + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUAD(b0, in); + + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ + +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, (in >> 16), 16); + state_out = __PKHBT(state_out >> 16, (out), 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* out = b0 * x[n] + 0 * 0 */ + out = __SMUADX(b0, in); + /* acc += b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in >> 16, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + sample--; + } + + /* If the blockSize is not a multiple of 2, compute any remaining output samples here. + ** No loop unrolling is used. */ + + if ((blockSize & 0x1U) != 0U) + { + /* Read the input */ + in = *pIn++; + + /* out = b0 * x[n] + 0 * 0 */ +#ifndef ARM_MATH_BIG_ENDIAN + out = __SMUAD(b0, in); +#else + out = __SMUADX(b0, in); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* acc = b1 * x[n-1] + b2 * x[n-2] + out */ + acc = __SMLALD(b1, state_in, out); + /* acc += a1 * y[n-1] + a2 * y[n-2] */ + acc = __SMLALD(a1, state_out, acc); + + /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + out = (uint32_t) acc_l >> lShift | acc_h << uShift; + + out = __SSAT(out, 16); + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) out; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */ + /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */ +#ifndef ARM_MATH_BIG_ENDIAN + state_in = __PKHBT(in, state_in, 16); + state_out = __PKHBT(out, state_out, 16); +#else + state_in = __PKHBT(state_in >> 16, in, 16); + state_out = __PKHBT(state_out >> 16, out, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + } + + /* The first stage goes from the input wire to the output wire. */ + /* Subsequent numStages occur in-place in the output wire */ + pIn = pDst; + + /* Reset the output pointer */ + pOut = pDst; + + /* Store the updated state variables back into the state array */ + write_q15x2_ia (&pState, state_in); + write_q15x2_ia (&pState, state_out); + + /* Decrement loop counter */ + stage--; + + } while (stage > 0U); + +#else + + const q15_t *pIn = pSrc; /* Source pointer */ + q15_t *pOut = pDst; /* Destination pointer */ + q15_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ + q15_t Xn; /* temporary input */ + q63_t acc; /* Accumulator */ + int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */ + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + pCoeffs++; // skip the 0 coefficient + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the state values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + + /* The variables acc holds the output value that is computed: + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + /* acc = b0 * x[n] */ + acc = (q31_t) b0 *Xn; + + /* acc += b1 * x[n-1] */ + acc += (q31_t) b1 *Xn1; + /* acc += b[2] * x[n-2] */ + acc += (q31_t) b2 *Xn2; + /* acc += a1 * y[n-1] */ + acc += (q31_t) a1 *Yn1; + /* acc += a2 * y[n-2] */ + acc += (q31_t) a2 *Yn2; + + /* The result is converted to 1.31 */ + acc = __SSAT((acc >> shift), 16); + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q15_t) acc; + + /* Store the output in the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* decrement the loop counter */ + sample--; + } + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + } while (--stage); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c new file mode 100644 index 0000000..d938025 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c @@ -0,0 +1,510 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df1_q31.c + * Description: Processing function for the Q31 Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF1 + @{ + */ + +/** + @brief Processing function for the Q31 Biquad cascade filter. + @param[in] S points to an instance of the Q31 Biquad cascade structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25). + After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to + 1.31 format by discarding the low 32 bits. + @remark + Refer to \ref arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* input pointer initialization */ + q31_t *pOut = pDst; /* output pointer initialization */ + int shift; + uint32_t stages = S->numStages; /* loop counters */ + int postShift = S->postShift; + q31x4_t b0Coeffs, b1Coeffs, a0Coeffs, a1Coeffs; /* Coefficients vector */ + q31x4_t stateVec; + q31_t *pState = S->pState; /* pState pointer initialization */ + q31x4_t inVec0; + int64_t acc; + const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */ + q31_t out, out1; + + + shift = (postShift + 1 + 8); + + do { + /* + * Reading the coefficients + * generates : + * Fwd0 { b2 b1 b0 0 } + * Fwd1 { 0 b2 b1 b0 } + * Bwd0 { 0 0 a2 a1 } + * Bwd0 { 0 0 a1 a2 } + * (can be moved in init) + */ + b0Coeffs = vdupq_n_s32(0); + a0Coeffs = vdupq_n_s32(0); + + b0Coeffs[0] = pCoeffs[2]; // b2 + b0Coeffs[1] = pCoeffs[1]; // b1 + b0Coeffs[2] = pCoeffs[0]; // b0 + + b1Coeffs = b0Coeffs; + uint32_t zero = 0; + b1Coeffs = vshlcq_s32(b1Coeffs, &zero, 32); + + a0Coeffs[2] = pCoeffs[4]; + a0Coeffs[3] = pCoeffs[3]; + a1Coeffs = vrev64q_s32(a0Coeffs); + + + /* + * prologue consumes history samples + */ + + /* 2 first elements are garbage, will be updated with history */ + inVec0 = vld1q(pIn - 2); + + inVec0[0] = pState[1]; + inVec0[1] = pState[0]; + + stateVec[2] = pState[3]; + stateVec[3] = pState[2]; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + + inVec0 = vld1q(pIn); + pIn += 2; + + /* + * main loop + */ + uint32_t sample = (blockSize - 2) >> 2U; + /* + * First part of the processing with loop unrolling. + * Compute 4 outputs at a time. + */ + while (sample > 0U) { + + stateVec[3] = out1; + + *pOut++ = out; + *pOut++ = out1; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { b2 b1 b0 0 } + */ + acc = vrmlaldavhq(b0Coeffs, inVec0); + /* + * out { 0 0 yn2 yn1 } + * x + * a0Coeffs { 0 0 a2 a1 } + */ + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + /* + * in { x0 x1 x2 x3 } + * x + * b0Coeffs { 0 b2 b1 b0 } + */ + acc = vrmlaldavhq(b1Coeffs, inVec0); + /* + * out { 0 0 y0 yn1 } + * x + * a0Coeffs { 0 0 a1 a2 } + */ + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + /* unrolled part */ + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + inVec0 = vld1q(pIn); + pIn += 2; + + sample--; + } + + *pOut++ = out; + *pOut++ = out1; + + /* + * Tail handling + */ + int32_t loopRemainder = blockSize & 3; + if (loopRemainder == 2) { + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[1]; + pState[1] = inVec0[0]; + pState[3] = out; + pState[2] = out1; + } else if (loopRemainder == 1) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[3] = out1; + + inVec0 = vld1q(pIn); + pIn += 2; + + *pOut++ = out; + *pOut++ = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } else if (loopRemainder == 0) { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + stateVec[2] = out; + + acc = vrmlaldavhq(b1Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a1Coeffs, stateVec); + acc = lsll(acc, shift); + out1 = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + *pOut++ = out1; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[3]; + pState[1] = inVec0[2]; + pState[3] = out; + pState[2] = out1; + } else { + stateVec[3] = out1; + + acc = vrmlaldavhq(b0Coeffs, inVec0); + acc = vrmlaldavhaq(acc, a0Coeffs, stateVec); + acc = lsll(acc, shift); + out = (q31_t) ((acc >> 32) & 0xffffffff); + + *pOut++ = out; + + /* + * Store the updated state variables back into the pState array + */ + pState[0] = inVec0[2]; + pState[1] = inVec0[1]; + pState[3] = out1; + pState[2] = out; + } + + + pCoeffs += 5; + pState += 4; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent stages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset to destination pointer */ + pOut = pDst; + } + while (--stages); +} +#else +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Source pointer */ + q31_t *pOut = pDst; /* Destination pointer */ + q31_t *pState = S->pState; /* pState pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q63_t acc; /* Accumulator */ + q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ + q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */ + q31_t Xn; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc_l, acc_h; /* temporary output variables */ +#endif + + do + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* Reading the pState values */ + Xn1 = pState[0]; + Xn2 = pState[1]; + Yn1 = pState[2]; + Yn2 = pState[3]; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 output values simultaneously. */ + /* Variable acc hold output values that are being computed: + * + * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] + */ + + /* Loop unrolling: Compute 4 outputs at a time */ + sample = blockSize >> 2U; + + while (sample > 0U) + { + /* Read the first input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 , Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the second input */ + Xn2 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Read the third input */ + Xn1 = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31, Yn2 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn2; + + /* Read the forth input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1); + + /* The result is converted to 1.31, Yn1 variable is reused */ + acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */ + acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */ + + /* Apply shift for lower part of acc and upper part of acc */ + Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store output in destination buffer. */ + *pOut++ = Yn1; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x3U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) + { + /* Read the input */ + Xn = *pIn++; + + /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ + acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2); + + /* The result is converted to 1.31 */ + acc = acc >> lShift; + + /* Store output in destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Every time after the output is computed state should be updated. */ + /* The states should be updated as: */ + /* Xn2 = Xn1 */ + /* Xn1 = Xn */ + /* Yn2 = Yn1 */ + /* Yn1 = acc */ + Xn2 = Xn1; + Xn1 = Xn; + Yn2 = Yn1; + Yn1 = (q31_t) acc; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the pState array */ + *pState++ = Xn1; + *pState++ = Xn2; + *pState++ = Yn1; + *pState++ = Yn2; + + /* The first stage goes from the input buffer to the output buffer. */ + /* Subsequent numStages occur in-place in the output buffer */ + pIn = pDst; + + /* Reset output pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BiquadCascadeDF1 group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c new file mode 100644 index 0000000..a7b1c7a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f16.c @@ -0,0 +1,494 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t Xn0, Xn1; + float16_t acc0, acc1; + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float16_t const *pCurCoeffs = /* coefficient pointer */ + (float16_t const *) S->pCoeffs; + f16x8_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f16x8_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f16x8_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x, x, x, x, x} + * a0Coeffs = { x, a1, a2, x, x, x, x, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs += 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0, x, x, x, x} + */ + state = *(f16x8_t *) pState; + state = vsetq_lane((float16_t)0.0, state, 2); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* b1Coeffs = {0, b0, b1, b2, x, x, x, x} */ + /* b1Coeffs = { x, x, a1, a2, x, x, x, x} */ + b1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)b0Coeffs, &tmp, 16); + a1Coeffs = (f16x8_t)vshlcq_s16((int16x8_t)a0Coeffs, &tmp, 16); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc1 \ / b0 \ / d1 \ / 0 \ + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane((float16_t)0.0, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | | b0 | | d1 | | 0 | + * | d1 | | b1 | | d2 | | a1 | + * | d2 | | b2 | | 0 | | a2 | + * | x | = | x | * Xn1 + | x | + | x | x acc1 + * ... ... ... ... + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane((float16_t)0.0, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* compiler does not come back when enabled */ + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq_n_f16(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq_n_f16(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_df2T_f16( + const arm_biquad_cascade_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1; /* Temporary input */ + _Float16 d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c new file mode 100644 index 0000000..922a396 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c @@ -0,0 +1,652 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t Xn0, Xn1; + float32_t acc0, acc1; + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t const *pCurCoeffs = /* coefficient pointer */ + (float32_t const *) S->pCoeffs; + f32x4_t b0Coeffs, a0Coeffs; /* Coefficients vector */ + f32x4_t b1Coeffs, a1Coeffs; /* Modified coef. vector */ + f32x4_t state; /* State vector */ + + do + { + /* + * temporary carry variable for feeding the 128-bit vector shifter + */ + uint32_t tmp = 0; + /* + * Reading the coefficients + * b0Coeffs = {b0, b1, b2, x} + * a0Coeffs = { x, a1, a2, x} + */ + b0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 2; + a0Coeffs = vld1q(pCurCoeffs); pCurCoeffs+= 3; + /* + * Reading the state values + * state = {d1, d2, 0, 0} + */ + state = *(f32x4_t *) pState; + state = vsetq_lane(0.0f, state, 2); + state = vsetq_lane(0.0f, state, 3); + + /* b1Coeffs = {b0, b1, b2, x} */ + /* b1Coeffs = { x, x, a1, a2} */ + b1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)b0Coeffs, &tmp, 32); + a1Coeffs = (f32x4_t)vshlcq_s32((int32x4_t)a0Coeffs, &tmp, 32); + + sample = blockSize / 2; + + /* unrolled 2 x */ + while (sample > 0U) + { + /* + * Read 2 inputs + */ + Xn0 = *pIn++; + Xn1 = *pIn++; + + /* + * 1st half: + * / acc0 \ / b0 \ / d1 \ / 0 \ + * | d1 | = | b1 | * Xn0 + | d2 | + | a1 | x acc0 + * | d2 | | b2 | | 0 | | a2 | + * \ x / \ x / \ x / \ x / + */ + + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + state = vfmaq(state, a0Coeffs, acc0); + state = vsetq_lane(0.0f, state, 3); + + /* + * 2nd half: + * same as 1st half, but all vector elements shifted down. + * / x \ / x \ / x \ / x \ + * | acc1 | = | b0 | * Xn1 + | d1 | + | 0 | x acc1 + * | d1 | | b1 | | d2 | | a1 | + * \ d2 / \ b2 / \ 0 / \ a2 / + */ + + state = vfmaq(state, b1Coeffs, Xn1); + acc1 = vgetq_lane(state, 1); + state = vfmaq(state, a1Coeffs, acc1); + + /* move d1, d2 up + clearing */ + /* expect dual move or long move */ + state = vsetq_lane(vgetq_lane(state, 2), state, 0); + state = vsetq_lane(vgetq_lane(state, 3), state, 1); + state = vsetq_lane(0.0f, state, 2); + /* + * Store the results in the destination buffer. + */ + *pOut++ = acc0; + *pOut++ = acc1; + /* + * decrement the loop counter + */ + sample--; + } + + /* + * tail handling + */ + if (blockSize & 1) + { + Xn0 = *pIn++; + state = vfmaq(state, b0Coeffs, Xn0); + acc0 = vgetq_lane(state, 0); + + state = vfmaq(state, a0Coeffs, acc0); + *pOut++ = acc0; + *pState++ = vgetq_lane(state, 1); + *pState++ = vgetq_lane(state, 2); + } + else + { + *pState++ = vgetq_lane(state, 0); + *pState++ = vgetq_lane(state, 1); + } + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else +#if defined(ARM_MATH_NEON) + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t acc1; /* accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* temporary input */ + float32_t d1, d2; /* state variables */ + uint32_t sample, stageCnt,stage = S->numStages; /* loop counters */ + + + float32x4_t XnV, YnV; + float32x4x2_t dV; + float32x4_t zeroV = vdupq_n_f32(0.0); + float32x4_t t1,t2,t3,t4,b1V,b2V,a1V,a2V,s; + + /* Loop unrolling. Compute 4 outputs at a time */ + stageCnt = stage >> 2; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + t1 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t2 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t3 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + t4 = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + b2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a1V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + a2V = vld1q_f32(pCoeffs); + pCoeffs += 4; + + /* Reading the state values */ + dV = vld2q_f32(pState); + + sample = blockSize; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + + XnV = vdupq_n_f32(*pIn++); + + s = dV.val[0]; + YnV = s; + + s = vextq_f32(zeroV,dV.val[0],3); + YnV = vmlaq_f32(YnV, t1, s); + + s = vextq_f32(zeroV,dV.val[0],2); + YnV = vmlaq_f32(YnV, t2, s); + + s = vextq_f32(zeroV,dV.val[0],1); + YnV = vmlaq_f32(YnV, t3, s); + + YnV = vmlaq_f32(YnV, t4, XnV); + + s = vextq_f32(XnV,YnV,3); + + dV.val[0] = vmlaq_f32(dV.val[1], s, b1V); + dV.val[0] = vmlaq_f32(dV.val[0], YnV, a1V); + + dV.val[1] = vmulq_f32(s, b2V); + dV.val[1] = vmlaq_f32(dV.val[1], YnV, a2V); + + *pOut++ = vgetq_lane_f32(YnV, 3) ; + + sample--; + } + + /* Store the updated state variables back into the state array */ + vst2q_f32(pState,dV); + pState += 8; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + + } + + /* Tail */ + stageCnt = stage & 3; + + while (stageCnt > 0U) + { + /* Reading the coefficients */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /*Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + sample = blockSize; + + while (sample > 0U) + { + /* Read the input */ + Xn1 = *pIn++; + + /* y[n] = b0 * x[n] + d1 */ + acc1 = (b0 * Xn1) + d1; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1 = ((b1 * Xn1) + (a1 * acc1)) + d2; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2 = (b2 * Xn1) + (a2 * acc1); + + /* decrement the loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + *pState++ = d1; + *pState++ = d2; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /*Reset the output working pointer */ + pOut = pDst; + + /* decrement the loop counter */ + stageCnt--; + } +} +#else + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1; /* Temporary input */ + float32_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c new file mode 100644 index 0000000..521f63b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c @@ -0,0 +1,443 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_f64.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure + + This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. + The filters are implemented as a cascade of second order Biquad sections. + These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. + Only floating-point data is supported. + + This function operate on blocks of input and output data and each call to the function + processes blockSize samples through the filter. + pSrc points to the array of input data and + pDst points to the array of output data. + Both arrays contain blockSize values. + + @par Algorithm + Each Biquad stage implements a second order filter using the difference equation: + 
+     y[n] = b0 * x[n] + d1
+     d1 = b1 * x[n] + a1 * y[n] + d2
+     d2 = b2 * x[n] + a2 * y[n]
+
+ where d1 and d2 represent the two state values. + @par + A Biquad filter using a transposed Direct Form II structure is shown below. + \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad" + Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients. + Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients. + Pay careful attention to the sign of the feedback coefficients. + Some design tools flip the sign of the feedback coefficients: + 
+     y[n] = b0 * x[n] + d1;
+     d1 = b1 * x[n] - a1 * y[n] + d2;
+     d2 = b2 * x[n] - a2 * y[n];
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library. + @par + Higher order filters are realized as a cascade of second order sections. + numStages refers to the number of second order stages used. + For example, an 8th order filter would be realized with numStages=4 second order stages. + A 9th order filter would be realized with numStages=5 second order stages with the + coefficients for one of the stages configured as a first order filter (b2=0 and a2=0). + @par + pState points to the state variable array. + Each Biquad stage has 2 state variables d1 and d2. + The state variables are arranged in the pState array as: + 
+      {d11, d12, d21, d22, ...}
+
+ where d1x refers to the state variables for the first Biquad and + d2x refers to the state variables for the second Biquad. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + @par + The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. + The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. + That is why the Direct Form I structure supports Q15 and Q31 data types. + The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2. + Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. + The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + + @par Init Functions + There is also an associated initialization function. + The initialization function performs following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + For example, to statically initialize the instance structure use + 
+      arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+      arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+
+ where numStages is the number of Biquad stages in the filter; + pState is the address of the state buffer. + pCoeffs is the address of the coefficient buffer; +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + + +void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + + const float64_t *pIn = pSrc; /* Source pointer */ + float64_t *pOut = pDst; /* Destination pointer */ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t acc1; /* Accumulator */ + float64_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float64_t Xn1; /* Temporary input */ + float64_t d1, d2; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1 = pState[0]; + d2 = pState[1]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 16 outputs at a time */ + sample = blockSize >> 4U; + + while (sample > 0U) { + + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + +/* 2 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 3 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 4 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 5 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 6 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 7 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 8 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 9 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 10 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 11 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 12 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 13 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 14 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 15 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + +/* 16 */ + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0xFU; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + Xn1 = *pIn++; + + acc1 = b0 * Xn1 + d1; + + d1 = b1 * Xn1 + d2; + d1 += a1 * acc1; + + d2 = b2 * Xn1; + d2 += a2 * acc1; + + *pOut++ = acc1; + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1; + pState[1] = d2; + + pState += 2U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* decrement loop counter */ + stage--; + + } while (stage > 0U); + +} + + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c new file mode 100644 index 0000000..3f619e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f16.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f16 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   arm_biquad_cascade_df2T_init_f16(&SNeon, nbCascade, neonCoefs, stateNeon);
+                   arm_biquad_cascade_df2T_compute_coefs_f16(&SNeon,nbCascade,coefs);
+
+ + @par In this example, neonCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f16( + arm_biquad_cascade_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c new file mode 100644 index 0000000..e3b350c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + + + +#if defined(ARM_MATH_NEON) +/** + @brief Compute new coefficient arrays for use in vectorized filter (Neon only). + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the original filter coefficients. + @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized Neon version. + @return none + + @par Size of coefficient arrays: + pCoeffs has size 5 * numStages + + pComputedCoeffs has size 8 * numStages + + pComputedCoeffs is the array to be used in arm_biquad_cascade_df2T_init_f32. + +*/ +void arm_biquad_cascade_df2T_compute_coefs_f32( + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pComputedCoeffs) +{ + uint8_t cnt; + float32_t b0[4],b1[4],b2[4],a1[4],a2[4]; + + cnt = numStages >> 2; + while(cnt > 0) + { + for(int i=0;i<4;i++) + { + b0[i] = pCoeffs[0]; + b1[i] = pCoeffs[1]; + b2[i] = pCoeffs[2]; + a1[i] = pCoeffs[3]; + a2[i] = pCoeffs[4]; + pCoeffs += 5; + } + + /* Vec 1 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1]; + *pComputedCoeffs++ = b0[2]; + *pComputedCoeffs++ = b0[3]; + + /* Vec 2 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2]; + *pComputedCoeffs++ = b0[2] * b0[3]; + + /* Vec 3 */ + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = 0; + *pComputedCoeffs++ = b0[1] * b0[2] * b0[3]; + + /* Vec 4 */ + *pComputedCoeffs++ = b0[0]; + *pComputedCoeffs++ = b0[0] * b0[1]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2]; + *pComputedCoeffs++ = b0[0] * b0[1] * b0[2] * b0[3]; + + /* Vec 5 */ + *pComputedCoeffs++ = b1[0]; + *pComputedCoeffs++ = b1[1]; + *pComputedCoeffs++ = b1[2]; + *pComputedCoeffs++ = b1[3]; + + /* Vec 6 */ + *pComputedCoeffs++ = b2[0]; + *pComputedCoeffs++ = b2[1]; + *pComputedCoeffs++ = b2[2]; + *pComputedCoeffs++ = b2[3]; + + /* Vec 7 */ + *pComputedCoeffs++ = a1[0]; + *pComputedCoeffs++ = a1[1]; + *pComputedCoeffs++ = a1[2]; + *pComputedCoeffs++ = a1[3]; + + /* Vec 8 */ + *pComputedCoeffs++ = a2[0]; + *pComputedCoeffs++ = a2[1]; + *pComputedCoeffs++ = a2[2]; + *pComputedCoeffs++ = a2[3]; + + cnt--; + } + + cnt = numStages & 0x3; + while(cnt > 0) + { + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + *pComputedCoeffs++ = *pCoeffs++; + cnt--; + } + +} +#endif + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order + in the not Neon version. + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + + For Neon version, this array is bigger. If numstages = 4x + y, then the array has size: + 32*x + 5*y + and it must be initialized using the function + arm_biquad_cascade_df2T_compute_coefs_f32 which is taking the + standard array coefficient as parameters. + + But, an array of 8*numstages is a good approximation. + + Then, the initialization can be done with: + 
+                   arm_biquad_cascade_df2T_compute_coefs_f32(nbCascade,coefs,computedCoefs);
+                   arm_biquad_cascade_df2T_init_f32(&SNeon, nbCascade, computedCoefs, stateNeon);
+
+ + @par In this example, computedCoefs is a bigger array of size 8 * numStages. + coefs is the standard array: + + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ + + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c new file mode 100644 index 0000000..5ab1c9a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_df2T_init_f64.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure + @param[in] numStages number of 2nd order stages in the filter + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 2 * numStages */ + memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c new file mode 100644 index 0000000..60caf8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f16.c @@ -0,0 +1,434 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f16.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_biquad_cascade_stereo_df2T_f16 built. Helium version has build issues with gcc." +#endif + +#if (defined(ARM_MATH_MVE_FLOAT16) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pIn = (float16_t *)pSrc; /* source pointer */ + float16_t *pOut = pDst; /* destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float16_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + static const uint16_t idx2[] = {2, 3, 8, 9, 2, 3, 8, 9}; + f16x8_t aCoeffs, bCoeffs; + float16_t scratch[16]; + uint16x8_t loadIdxVec; + uint16x8_t reshufledIdxVec; + uint16_t startIdx = 0; + f16x8_t stateVec0, stateVec1; + f16x8_t inVec; + + /* + * {0, 1, 0, 1, 0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u16(startIdx, 2, 1); + reshufledIdxVec = *(uint16x8_t *)&idx2; + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b d1a d1b d2a d2b 0 0] + */ + scratch[8] = (float16_t)0.0; + scratch[9] = (float16_t)0.0; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* aCoeffs = {a1 a1 a2 a2 a1 a1 a2 a2} */ + aCoeffs = vdupq_n_f16(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + aCoeffs = vsetq_lane(a2, aCoeffs, 6); + aCoeffs = vsetq_lane(a2, aCoeffs, 7); + + /* bCoeffs = {b1 b1 b2 b2 b1 b1 b2 b2} */ + bCoeffs = vdupq_n_f16(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + bCoeffs = vsetq_lane(b2, bCoeffs, 6); + bCoeffs = vsetq_lane(b2, bCoeffs, 7); + + /* + * Reading the state values + * Save into scratch + */ + *(f16x8_t *) scratch = *(f16x8_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + * 4 | + * 5 | ... + */ + + /* + * load {d1a, d1b, d1a, d1b, d1a, d1b, d1a, d1b} + */ + stateVec0 = vldrhq_gather_shifted_offset((float16_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1 in0 in1 in0 in1} + */ + inVec = vldrhq_gather_shifted_offset_f16(pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + * 4 | + * 5 | ... + */ + + /* + * load {d2a, d2b, 0, 0, d2a, d2b, 0, 0} + */ + stateVec1 = vldrhq_gather_shifted_offset((float16_t const *) scratch, reshufledIdxVec); + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f16x8_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + *pState++ = vgetq_lane(stateVec1, 0); + *pState++ = vgetq_lane(stateVec1, 1); + *pState++ = vgetq_lane(stateVec1, 2); + *pState++ = vgetq_lane(stateVec1, 3); + + /* + * The current stage input is given as the output to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} +#else + +void arm_biquad_cascade_stereo_df2T_f16( + const arm_biquad_cascade_stereo_df2T_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Source pointer */ + float16_t *pOut = pDst; /* Destination pointer */ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + _Float16 acc1a, acc1b; /* Accumulator */ + _Float16 b0, b1, b2, a1, a2; /* Filter coefficients */ + _Float16 Xn1a, Xn1b; /* Temporary input */ + _Float16 d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* #if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c new file mode 100644 index 0000000..ddd1546 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c @@ -0,0 +1,420 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_f32.c + * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters +*/ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] S points to an instance of the filter data structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if (defined(ARM_MATH_MVEF) && defined(ARM_MATH_HELIUM_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* source pointer */ + float32_t *pOut = pDst; /* destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + uint32_t sample, stage = S->numStages; /* loop counters */ + float32_t scratch[6]; + uint32x4_t loadIdxVec; + f32x4_t aCoeffs, bCoeffs; + f32x4_t stateVec0, stateVec1; + f32x4_t inVec; + uint32_t startIdx = 0; + + /* + * {0, 1, 0, 1} generator + */ + loadIdxVec = viwdupq_u32(&startIdx, 2, 1); + + /* + * scratch top clearing + * layout : [d1a d1b d2a d2b 0 0] + */ + scratch[4] = 0.0f; + scratch[5] = 0.0f; + + do + { + /* + * Reading the coefficients + */ + b0 = *pCoeffs++; + b1 = *pCoeffs++; + b2 = *pCoeffs++; + a1 = *pCoeffs++; + a2 = *pCoeffs++; + + /* + * aCoeffs = {a1 a1 a2 a2} + */ + aCoeffs = vdupq_n_f32(a1); + aCoeffs = vsetq_lane(a2, aCoeffs, 2); + aCoeffs = vsetq_lane(a2, aCoeffs, 3); + + /* + * bCoeffs = {b1 b1 b2 b2} + */ + bCoeffs = vdupq_n_f32(b1); + bCoeffs = vsetq_lane(b2, bCoeffs, 2); + bCoeffs = vsetq_lane(b2, bCoeffs, 3); + + /* + * Reading the state values + * Save into scratch + */ + *(f32x4_t *) scratch = *(f32x4_t *) pState; + + sample = blockSize; + + while (sample > 0U) + { + /* + * step 1 + * + * 0 | acc1a = xn1a * b0 + d1a + * 1 | acc1b = xn1b * b0 + d1b + * 2 | acc1a = xn1a * b0 + d1a + * 3 | acc1b = xn1b * b0 + d1b + */ + /* + * load {d1a, d1b, d1a, d1b} + */ + stateVec0 = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) scratch, loadIdxVec); + /* + * load {in0 in1 in0 in1} + */ + inVec = (f32x4_t)vldrwq_gather_shifted_offset((uint32_t const *) pIn, loadIdxVec); + + stateVec0 = vfmaq(stateVec0, inVec, b0); + *pOut++ = vgetq_lane(stateVec0, 0); + *pOut++ = vgetq_lane(stateVec0, 1); + + /* + * step 2 + * + * 0 | d1a = b1 * xn1a + a1 * acc1a + d2a + * 1 | d1b = b1 * xn1b + a1 * acc1b + d2b + * 2 | d2a = b2 * xn1a + a2 * acc1a + 0 + * 3 | d2b = b2 * xn1b + a2 * acc1b + 0 + */ + + /* + * load {d2a, d2b, 0, 0} + */ + stateVec1 = *(f32x4_t *) & scratch[2]; + stateVec1 = vfmaq(stateVec1, stateVec0, aCoeffs); + stateVec1 = vfmaq(stateVec1, inVec, bCoeffs); + *(f32x4_t *) scratch = stateVec1; + + pIn = pIn + 2; + sample--; + } + + /* + * Store the updated state variables back into the state array + */ + vst1q(pState, stateVec1); + pState += 4; + + /* + * The current stage output is given as the input to the next stage + */ + pIn = pDst; + /* + * Reset the output working pointer + */ + pOut = pDst; + /* + * decrement the loop counter + */ + stage--; + } + while (stage > 0U); +} + +#else + +void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Source pointer */ + float32_t *pOut = pDst; /* Destination pointer */ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t acc1a, acc1b; /* Accumulator */ + float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ + float32_t Xn1a, Xn1b; /* Temporary input */ + float32_t d1a, d2a, d1b, d2b; /* State variables */ + uint32_t sample, stage = S->numStages; /* Loop counters */ + + do + { + /* Reading the coefficients */ + b0 = pCoeffs[0]; + b1 = pCoeffs[1]; + b2 = pCoeffs[2]; + a1 = pCoeffs[3]; + a2 = pCoeffs[4]; + + /* Reading the state values */ + d1a = pState[0]; + d2a = pState[1]; + d1b = pState[2]; + d2b = pState[3]; + + pCoeffs += 5U; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 outputs at a time */ + sample = blockSize >> 3U; + + while (sample > 0U) { + /* y[n] = b0 * x[n] + d1 */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + /* d2 = b2 * x[n] + a2 * y[n] */ + +/* 1 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 2 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 3 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 4 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 5 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 6 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 7 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + +/* 8 */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + *pOut++ = acc1a; + *pOut++ = acc1b; + + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Loop unrolling: Compute remaining outputs */ + sample = blockSize & 0x7U; + +#else + + /* Initialize blkCnt with number of samples */ + sample = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (sample > 0U) { + /* Read the input */ + Xn1a = *pIn++; /* Channel a */ + Xn1b = *pIn++; /* Channel b */ + + /* y[n] = b0 * x[n] + d1 */ + acc1a = (b0 * Xn1a) + d1a; + acc1b = (b0 * Xn1b) + d1b; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc1a; + *pOut++ = acc1b; + + /* Every time after the output is computed state should be updated. */ + /* d1 = b1 * x[n] + a1 * y[n] + d2 */ + d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a; + d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b; + + /* d2 = b2 * x[n] + a2 * y[n] */ + d2a = (b2 * Xn1a) + (a2 * acc1a); + d2b = (b2 * Xn1b) + (a2 * acc1b); + + /* decrement loop counter */ + sample--; + } + + /* Store the updated state variables back into the state array */ + pState[0] = d1a; + pState[1] = d2a; + + pState[2] = d1b; + pState[3] = d2b; + + pState += 4U; + + /* The current stage output is given as the input to the next stage */ + pIn = pDst; + + /* Reset the output working pointer */ + pOut = pDst; + + /* Decrement the loop counter */ + stage--; + + } while (stage > 0U); + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c new file mode 100644 index 0000000..633fbfe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f16.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f16.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f16( + arm_biquad_cascade_stereo_df2T_instance_f16 * S, + uint8_t numStages, + const float16_t * pCoeffs, + float16_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float16_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c new file mode 100644 index 0000000..6932b9a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_biquad_cascade_stereo_df2T_init_f32.c + * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup BiquadCascadeDF2T + @{ + */ + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] pCoeffs points to the filter coefficients. + @param[in] pState points to the state buffer. + @return none + + @par Coefficient and State Ordering + The coefficients are stored in the array pCoeffs in the following order: + 
+      {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par + where b1x and a1x are the coefficients for the first stage, + b2x and a2x are the coefficients for the second stage, + and so on. The pCoeffs array contains a total of 5*numStages values. + @par + The pState is a pointer to state array. + Each Biquad stage has 2 state variables d1, and d2 for each channel. + The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on. + The state array has a total length of 2*numStages values. + The state variables are updated after each block of data is processed; the coefficients are untouched. + */ + +void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter stages */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always 4 * numStages */ + memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of BiquadCascadeDF2T group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c new file mode 100644 index 0000000..7f2dd81 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c @@ -0,0 +1,964 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_f32.c + * Description: Convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Conv Convolution + + Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector. + Convolution is similar to correlation and is frequently used in filtering and data analysis. + The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types. + The library also provides fast versions of the Q15 and Q31 functions. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and + srcBLen samples respectively. Then the convolution + 
+     c[n] = a[n] * b[n]
+
+ @par + is defined as + \image html ConvolutionEquation.gif + @par + Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2. + pSrcA points to the first input vector of length srcALen and + pSrcB points to the second input vector of length srcBLen. + The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result. + @par + Conceptually, when two signals a[n] and b[n] are convolved, + the signal b[n] slides over a[n]. + For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together. + @par + Note that convolution is a commutative operation: + 
+     a[n] * b[n] = b[n] * a[n].
+
+ @par + This means that switching the A and B arguments to the convolution functions has no effect. + + @par Fixed-Point Behavior + Convolution requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + + +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const float32_t *pX; + const float32_t *pY; + const float32_t *pA; + const float32_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is incrementing for successive accumulators + * Y pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pB += 2; + } + + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pB++; + } + + for (i = 0; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + float32_t acc0 = 0; + float32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, count); + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + float32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + int32_t count = i; + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for successive accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst++ = acc0; + *pDst++ = acc1; + pA += 2; + } + for (; i >= 1; i--) + { + int32_t count = i; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_F32(acc, pX, pY, count); + + *pDst++ = acc; + pA++; + } +} +#else +void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3, c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* Temporary variables to hold state and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ +#if defined(ARM_MATH_NEON) + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); +#endif /* #if defined(ARM_MATH_NEON) */ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + accum = vdup_n_f32(0); + + /* Compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + + while (k > 0U) + { + vec1 = vld1q_f32(px); + vec2 = vld1q_f32(py-3); + vec2 = vrev64q_f32(vec2); + vec2 = vcombine_f32(vget_high_f32(vec2), vget_low_f32(vec2)); + + res = vmlaq_f32(res,vec1, vec2); + + /* Increment pointers */ + px += 4; + py -= 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count & 3; +#else + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ + +#else /* defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + x2v = vld1q_f32(px+4); + + do + { + c = vld1q_f32(py-3); + + px += 4; + x = x1v; + res = vmlaq_n_f32(res,x,c[3]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[0]); + + py -= 4; + + x1v = x2v ; + x2v = vld1q_f32(px+4); + + } while (--k); + + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + x1v = vld1q_f32(px); + px += 4; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py--); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; + +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *(px + 3U); + px += 4U; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined (ARM_MATH_NEON)*/ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined (ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + /* First part of the processing. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3U; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#endif /* if defined (ARM_MATH_NEON) */ +#else + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined(ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t res = vdupq_n_f32(0) ; + float32x4_t x = vdupq_n_f32(0) ; + float32x4_t y = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0) ; + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py-3); + + y = vrev64q_f32(y); + y = vcombine_f32(vget_high_f32(y), vget_low_f32(y)); + + res = vmlaq_f32(res,x,y); + + px += 4 ; + py -= 4 ; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + +#else + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined (ARM_MATH_NEON) */ + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_NEON) || defined (ARM_MATH_LOOPUNROLL)*/ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c new file mode 100644 index 0000000..06629f1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c @@ -0,0 +1,366 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_opt_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q31_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c new file mode 100644 index 0000000..5337a82 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c @@ -0,0 +1,663 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q15.c + * Description: Fast Q15 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1 + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results + but provides only a single guard bit. There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + */ + +void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + /* Read y[srcBLen - 7] */ + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD(x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((acc1 >> 15), (acc0 >> 15), 16)); + write_q15x2_ia (&pOut, __PKHBT((acc3 >> 15), (acc2 >> 15), 16)); +#endif /*#ifndef ARM_MATH_BIG_ENDIAN*/ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c new file mode 100644 index 0000000..133c322 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c @@ -0,0 +1,558 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_fast_q31.c + * Description: Fast Q31 Convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + @remark + Refer to \ref arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c new file mode 100644 index 0000000..1f3efe0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + */ + +void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q63_t acc0; /* Accumulators */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch1 buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + + /* Initialization of pIn2 pointer */ + pIn2 = py; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c new file mode 100644 index 0000000..1f12f0d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c @@ -0,0 +1,360 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_opt_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + const q7_t *px; /* Temporary input1 pointer */ + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + /* Actual convolution process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2U; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c new file mode 100644 index 0000000..a8a9bd1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c @@ -0,0 +1,678 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_f32.c + * Description: Partial convolution of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup PartialConv Partial Convolution + + Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated. + Each function has two additional arguments. + firstIndex specifies the starting index of the subset of output samples. + numPoints is the number of output samples to compute. + The function computes the output in the range + [firstIndex, ..., firstIndex+numPoints-1]. + The output array pDst contains numPoints values. + + The allowable range of output indices is [0 srcALen+srcBLen-2]. + If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR. + Otherwise the functions return ARM_MATH_SUCCESS. + \note Refer to \ref arm_conv_f32() for details on fixed point behavior. + + @par Fast Versions + Fast versions are supported for Q31 and Q15 of partial convolution. + Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ +#if defined (ARM_MATH_DSP) + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */ + float32_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; /* Accumulator */ + float32_t x0, x1, x2, x3, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + firstIndex; + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* x[1] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* x[2] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* x[3] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc1; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 += x3 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 += x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 += x1 * c0; + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = acc0; + *pOut++ = acc1; + *pOut++ = acc2; + *pOut++ = acc3; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* InputA pointer */ + const float32_t *pIn2 = pSrcB; /* InputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ( pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = sum; + } + + /* Set status as ARM_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* defined(ARM_MATH_DSP) */ +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c new file mode 100644 index 0000000..a6b9ecf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_opt_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2 + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q31_t acc0; /* Accumulator */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c new file mode 100644 index 0000000..3e92818 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c @@ -0,0 +1,707 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q15.c + * Description: Fast Q15 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + @remark + Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLADX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLADX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLADX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLADX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLADX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLADX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLADX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLADX(x0, c0, acc0); + acc1 = __SMLADX(x1, c0, acc1); + acc2 = __SMLADX(x3, c0, acc2); + acc3 = __SMLADX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(acc1 >> 15, acc0 >> 15, 16)); + write_q15x2_ia (&pOut, __PKHBT(acc3 >> 15, acc2 >> 15, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + sum += ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLAD(*px++, *py--, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (sum >> 15); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c new file mode 100644 index 0000000..65269bc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c @@ -0,0 +1,625 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_fast_q31.c + * Description: Fast Q31 Partial convolution + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + */ + +arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t j, k, count, check, blkCnt; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[1] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[2] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* x[3] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[srcBLen - 1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read y[srcBLen - 2] sample */ + c0 = *py--; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[srcBLen - 2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + /* Read y[srcBLen - 4] sample */ + c0 = *py--; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[srcBLen - 4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[srcBLen - 4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[srcBLen - 4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[srcBLen - 4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 << 1); + *pOut++ = (q31_t) (acc1 << 1); + *pOut++ = (q31_t) (acc2 << 1); + *pOut++ = (q31_t) (acc3 << 1); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) * px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py--))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = sum << 1; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c new file mode 100644 index 0000000..7a9d6b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + */ + +arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */ + q63_t acc0; /* Accumulator */ + q31_t x1; /* Temporary variables to hold state and coefficient values */ + q31_t y1; /* State variables */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *px; /* Intermediate inputA pointer */ + q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, k, blkCnt; /* Loop counter */ + uint32_t tapCnt; /* Loop count */ + arm_status status; /* Status variable */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulator */ + q31_t x2, x3; /* Temporary variables to hold state and coefficient values */ + q31_t y2; /* State variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2 + srcBLen - 1; + + /* points to smaller length sequence */ + px = pIn2; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + /* Copy smaller length input sequence in reverse order into second scratch buffer */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + *pScr2-- = *px++; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Assuming scratch1 buffer is aligned by 32-bit */ + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */ + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Initialization of pIn2 pointer */ + pIn2 = py; + + pScratch1 += firstIndex; + + pOut = pDst + firstIndex; + + /* Actual convolution process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numPoints & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numPoints; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + + acc0 = __SMLALD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch1 += 1U; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c new file mode 100644 index 0000000..a5c16c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_opt_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + */ + +arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */ + q15_t x4; /* Temporary input variable */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + const q7_t *px; /* Temporary input1 pointer */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + arm_status status; + q7_t *pOut = pDst; /* Output pointer */ + q7_t out0, out1, out2, out3; /* Temporary variables */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* pointer to take end of scratch2 buffer */ + pScr2 = pScratch2; + + /* points to smaller length sequence */ + px = pIn2 + srcBLen - 1; + + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *px--; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Initialze temporary scratch pointer */ + pScr1 = pScratch1; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + ** a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + ** No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pIn2 pointer */ + pIn2 = (q7_t *) py; + + pScr2 = py; + + pOut = pDst + firstIndex; + + pScratch1 += firstIndex; + + /* Actual convolution process starts here */ + blkCnt = (numPoints) >> 2; + + while (blkCnt > 0) + { + /* Initialize temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumulators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + out0 = (q7_t) (__SSAT(acc0 >> 7U, 8)); + out1 = (q7_t) (__SSAT(acc1 >> 7U, 8)); + out2 = (q7_t) (__SSAT(acc2 >> 7U, 8)); + out3 = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (numPoints) & 0x3; + + /* Calculate convolution for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read two samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x1, y1, acc0); + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c new file mode 100644 index 0000000..cfab516 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c @@ -0,0 +1,759 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q15.c + * Description: Partial convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers. + */ + +arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt, check; + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2 - 1U; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py+1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the results in the accumulators in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + No loop unrolling is used. */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = count >> 2U; + + while ((j > 0U) && (blockSize3 > 0)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c new file mode 100644 index 0000000..bcd5298 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q31.c + * Description: Partial convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_fast_q31() for a faster but less precise implementation of this function. + */ + +arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulator */ + q31_t x0, x1, x2, c0; /* Temporary variables */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll over blkCnt */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += (q63_t) x2 * c0; + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += (q63_t) x1 * c0; + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += (q63_t) x2 * c0; + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += (q63_t) x0 * c0; + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += (q63_t) x2 * c0; + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += (q63_t) x0 * c0; + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += (q63_t) x1 * c0; + + + px += 3U; + + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += (q63_t) x0 * c0; + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += (q63_t) x1 * c0; + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += (q63_t) x2 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c new file mode 100644 index 0000000..0532c51 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c @@ -0,0 +1,759 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_partial_q7.c + * Description: Partial convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup PartialConv + @{ + */ + +/** + @brief Partial convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written + @param[in] firstIndex is the first output sample to start with + @param[in] numPoints is the number of output points to be computed + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2] + + @remark + Refer to \ref arm_conv_partial_opt_q7() for a faster implementation of this function. + */ + +arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints) +{ + +#if defined(ARM_MATH_DSP) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulator */ + uint32_t j, k, count, blkCnt, check; /* Loop counters */ + int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulator */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* Conditions to check which loopCounter holds + * the first and last indices of the output samples to be calculated. */ + check = firstIndex + numPoints; + blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0; + blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3; + blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex; + blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t)numPoints) : 0; + blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex); + blockSize2 = (blockSize2 > 0) ? blockSize2 : 0; + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* Set the output pointer to point to the firstIndex + * of the output sample to be calculated. */ + pOut = pDst + firstIndex; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed. + Since the partial convolution starts from firstIndex + Number of Macs to be performed is firstIndex + 1 */ + count = 1U + firstIndex; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + firstIndex; + py = pSrc2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = ++pSrc2; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0) + { + pSrc1 = pIn1 + firstIndex - srcBLen + 1; + } + else + { + pSrc1 = pIn1; + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = ((uint32_t) blockSize2 >> 2U); + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q31_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q31_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q31_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q31_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (uint32_t) blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = (uint32_t) blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pSrc1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + if (firstIndex > srcALen) + { + pSrc1 = (pIn1 + firstIndex) - (srcBLen - 1U); + } + else + { + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + } + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q31_t) * px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + arm_status status; /* Status of Partial convolution */ + + /* Check for range of output samples to be calculated */ + if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U)))) + { + /* Set status as ARM_MATH_ARGUMENT_ERROR */ + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Loop to calculate convolution for output length number of values */ + for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * (pIn2[i - j])); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of PartialConv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c new file mode 100644 index 0000000..0a28b95 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c @@ -0,0 +1,858 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q15.c + * Description: Convolution of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_conv_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + + + uint16x8_t decrIdxVec = vddupq_u16(7, 1); + + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 7; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + *pDst++ = (q15_t) acc2; + *pDst++ = (q15_t) acc3; + + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + *pDst++ = (q15_t) acc0; + *pDst++ = (q15_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q15(acc, pX, pY, count); + *pDst++ = (q15_t) acc; + pA++; + } +} +#else +void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations less than 4 */ + /* Second part of this stage computes the MAC operations greater than or equal to 4 */ + + /* The first part of the stage starts here */ + while ((count < 4U) && (blockSize1 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Loop over number of MAC operations between + * inputA samples and inputB samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* The second part of the stage starts here */ + /* The internal loop, over count, is unrolled by 4 */ + /* To, read the last two inputB samples using SIMD: + * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */ + py = py - 1; + + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + (count - 1U); + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + py = py - 1U; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the last two inputB samples using SIMD: + * y[srcBLen - 1] and y[srcBLen - 2] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLALDX(x0, c0, acc0); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLALDX(x2, c0, acc2); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLALDX(x3, c0, acc3); + + /* Read y[srcBLen - 3] and y[srcBLen - 4] */ + c0 = read_q15x2_da ((q15_t **) &py); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLALDX(x2, c0, acc0); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLALDX(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + + px += 4U; + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLALDX(x0, c0, acc2); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[srcBLen - 5] */ + c0 = *(py + 1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[srcBLen - 5], y[srcBLen - 6] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALDX(x0, c0, acc0); + acc1 = __SMLALDX(x1, c0, acc1); + acc2 = __SMLALDX(x3, c0, acc2); + acc3 = __SMLALDX(x2, c0, acc3); + + c0 = *(py-1); +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD(x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) ((q31_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT(sum >> 15, 16)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + blockSize3 = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + pIn2 = pSrc2 - 1U; + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + /* For loop unrolling by 4, this stage is divided into two. */ + /* First part of this stage computes the MAC operations greater than 4 */ + /* Second part of this stage computes the MAC operations less than or equal to 4 */ + + /* The first part of the stage starts here */ + j = blockSize3 >> 2U; + + while ((j > 0U) && (blockSize3 > 0U)) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied + * with y[srcBLen - 1], y[srcBLen - 2] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied + * with y[srcBLen - 3], y[srcBLen - 4] respectively */ + sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* For the next MAC operations, the pointer py is used without SIMD + * So, py is incremented by 1 */ + py = py + 1U; + + /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = blockSize3 % 0x4U; + + while (k > 0U) + { + /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement loop counter */ + blockSize3--; + + j--; + } + + /* The second part of the stage starts here */ + /* SIMD is not used for the next MAC operations, + * so pointer py is updated to read only one sample at a time */ + py = py + 1U; + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = blockSize3; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum = __SMLALD(*px++, *py--, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q15_t) (__SSAT((sum >> 15), 16)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of values */ + for (i = 0; i < (srcALen + srcBLen - 1); i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c new file mode 100644 index 0000000..ee37824 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c @@ -0,0 +1,745 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q31.c + * Description: Convolution of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows, + as maximum of min(srcALen, srcBLen) number of additions are carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_conv_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint32_t vddupStartIdx = 3; + uint32x4_t decrIdxVec = vddupq_u32(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 3; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + + *pDst++ = (q31_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + + for (i = block3; i >= 2; i -= 2) + { + uint32_t count = i; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + pA += 2; + } + + for (; i >= 1; i--) + { + uint32_t count = i; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q31(acc, pX, pY, count); + *pDst++ = (q31_t) acc; + pA++; + } + +} + +#else +void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py--); + + /* x[1] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py--); + + /* x[2] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py--); + + /* x[3] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py--); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *(py); + /* Read x[3] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[srcBLen - 1] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[srcBLen - 1] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[srcBLen - 1] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[srcBLen - 2] sample */ + c0 = *(py - 1U); + /* Read x[4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[srcBLen - 2] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[srcBLen - 2] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[srcBLen - 2] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[srcBLen - 3] sample */ + c0 = *(py - 2U); + /* Read x[5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[srcBLen - 3] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[srcBLen - 2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[srcBLen - 2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py -= 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (acc0 >> 31); + *pOut++ = (q31_t) (acc1 >> 31); + *pOut++ = (q31_t) (acc2 >> 31); + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py--; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * *py--; + + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += (q63_t) *px++ * *py--; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q31_t) (sum >> 31); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB; /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c new file mode 100644 index 0000000..e29a16d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c @@ -0,0 +1,860 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_conv_q7.c + * Description: Convolution of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Conv + @{ + */ + +/** + @brief Convolution of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + @remark + Refer to \ref arm_conv_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +#include "arm_vec_filtering.h" + +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB; /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q7_t *pX; + const q7_t *pY; + const q7_t *pA; + const q7_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t block1, block2, block3; + uint8_t vddupStartIdx = 15; + uint8x16_t decrIdxVec = vddupq_u8(vddupStartIdx, 1); + + if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2 - 15; + + for (i = 0; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pB += 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pB++; + } + + for (i = 0; i <= block2 - 4; i += 4) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + *pDst++ = (q7_t) acc2; + *pDst++ = (q7_t) acc3; + pA += 4; + } + for (; i <= block2 - 2; i += 2) + { + uint32_t count = srcBLen; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CONV_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + if (block2 & 1) + { + uint32_t count = srcBLen; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } + + for (i = block3; i >= 1; i -= 2) + { + uint32_t count = i; + int32_t acc0 = 0; + int32_t acc1 = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + *pDst++ = (q7_t) acc0; + *pDst++ = (q7_t) acc1; + pA += 2; + } + for (; i >= 1; i--) + { + uint32_t count = i; + int32_t acc = 0; + + pX = pA; + pY = pB; + + MVE_INTR_CONV_SINGLE_Q7(acc, pX, pY, count); + *pDst++ = (q7_t) acc; + pA++; + } +} + +#else +void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + } + + /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */ + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[0] + * sum = x[0] * y[1] + x[1] * y[0] + * .... + * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] , y[srcBLen - 2] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[0] * y[srcBLen - 1] */ + /* x[1] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] , y[srcBLen - 4] */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* x[2] * y[srcBLen - 3] */ + /* x[3] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pIn2 + count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0] + * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0] + * .... + * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[srcBLen - 1] sample */ + c0 = *py--; + /* Read y[srcBLen - 2] sample */ + c1 = *py--; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 1] and y[srcBLen - 2] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[srcBLen - 3] sample */ + c0 = *py--; + /* Read y[srcBLen - 4] sample */ + c1 = *py--; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[srcBLen - 3] and y[srcBLen - 4] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *py--; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[srcBLen - 5] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[srcBLen - 5] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[srcBLen - 5] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[srcBLen - 5] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8)); + *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pSrc2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1] + * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2] + * .... + * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2] + * sum += x[srcALen-1] * y[srcBLen-1] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The blockSize3 variable holds the number of MAC operations performed */ + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + pSrc2 = pIn2 + (srcBLen - 1U); + py = pSrc2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = blockSize3 >> 2U; + + while (k > 0U) + { + /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */ + /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */ + in1 = (q15_t) *py--; + in2 = (q15_t) *py--; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */ + /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = blockSize3 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = blockSize3; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen-1] * y[srcBLen-1] */ + sum += ((q15_t) *px++ * *py--); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8)); + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pSrc2; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB; /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i, j; /* Loop counters */ + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i < (srcALen + srcBLen - 1U); i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[i - j]); + } + } + + /* Store the output in the destination buffer */ + pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Conv group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c new file mode 100644 index 0000000..5924b7a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f16.c @@ -0,0 +1,1159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f16.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + 
+      c[n] = a[n] * b[n]
+
+ In correlation, one of the signals is flipped in time + 
+       c[n] = a[n] * b[-n]
+
+ @par + and this is mathematically defined as + \image html CorrelateEquation.gif + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +#define MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + while (k > 0U) \ + { \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + k = count % 0x8U; \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires 1 additional sample */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + mve_pred16_t p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + yVec = vldrhq_f16(&pSrcY[-1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec,p0); \ + /* acc0 requires exact number of sample */ \ + /* disable extra lanes in final MAC computation */ \ + p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec,p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t accVec, xVec, yVec; \ + uint16_t k; \ + \ + accVec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq(accVec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* Loop with tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + accVec = vfmaq_m(accVec, xVec, yVec, p0); \ + } \ + \ + acc = vecAddAcrossF16Mve(accVec); \ +} + +#define MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, acc2Vec, acc3Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + acc2Vec = vdupq_n_f16(0.0f); \ + acc3Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_f16(acc2Vec, xVec, yVec); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_f16(acc3Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[2]); \ + acc2Vec = vfmaq_m_f16(acc2Vec, xVec, yVec, p0); \ + xVec = vldrhq_f16(&pSrcX[3]); \ + acc3Vec = vfmaq_m_f16(acc3Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ + acc2 = vecAddAcrossF16Mve(acc2Vec); \ + acc3 = vecAddAcrossF16Mve(acc3Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = count >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* loop + tail predication expected here */ \ + k = count % 0x8U; \ + if (k > 0U) \ + { \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8;; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + } \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + +#define MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count) \ +{ \ + float16_t const *pSrcX, *pSrcY; \ + f16x8_t acc0Vec, acc1Vec, xVec, yVec; \ + uint32_t k; \ + \ + acc0Vec = vdupq_n_f16(0.0f); \ + acc1Vec = vdupq_n_f16(0.0f); \ + pSrcX = (float16_t const *) pX; \ + pSrcY = (float16_t const *) pY; \ + k = (count-1) >> 3; \ + \ + while (k > 0U) \ + { \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_f16(acc1Vec, xVec, yVec); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_f16(acc0Vec, xVec, yVec); \ + /* Decrement the loop counter */ \ + k--; \ + } \ + /* use predication to finalize MAC sum */ \ + /* acc1 requires exact number of sample (count-1) */ \ + /* disable extra lanes in final MAC computation */ \ + k = (count-1) % 0x8U; \ + mve_pred16_t p0 = vctp16q(k); \ + yVec = vld1q(pSrcY); pSrcY += 8; \ + xVec = vldrhq_f16(&pSrcX[1]); \ + acc1Vec = vfmaq_m_f16(acc1Vec, xVec, yVec, p0); \ + /* acc0 requires 1 additional sample (count) */ \ + /* so add 1 to unmask an extra lane in final MAC computation */ \ + p0 = vctp16q(k+1); \ + xVec = vld1q(pSrcX); pSrcX += 8; \ + acc0Vec = vfmaq_m_f16(acc0Vec, xVec, yVec, p0); \ + \ + acc0 = vecAddAcrossF16Mve(acc0Vec); \ + acc1 = vecAddAcrossF16Mve(acc1Vec); \ +} + + + +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + float16_t *pIn1 = (float16_t *)pSrcA; /* inputA pointer */ + float16_t *pIn2 = (float16_t *)pSrcB + (srcBLen - 1U); /* inputB pointer */ + float16_t *pX; + float16_t *pY; + float16_t *pA; + float16_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = (float16_t *)pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = (float16_t *)pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + _Float16 acc0; + _Float16 acc1; + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + _Float16 acc0; + _Float16 acc1; + _Float16 acc2; + _Float16 acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F16(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F16(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + _Float16 acc0; + _Float16 acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F16(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + _Float16 acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F16(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f16( + const float16_t * pSrcA, + uint32_t srcALen, + const float16_t * pSrcB, + uint32_t srcBLen, + float16_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float16_t *pIn1; /* InputA pointer */ + const float16_t *pIn2; /* InputB pointer */ + float16_t *pOut = pDst; /* Output pointer */ + const float16_t *px; /* Intermediate inputA pointer */ + const float16_t *py; /* Intermediate inputB pointer */ + const float16_t *pSrc1; + _Float16 sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc0, acc1, acc2, acc3,c0; /* Accumulators */ + _Float16 x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[1] * y[srcBLen - 3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[2] * y[srcBLen - 2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* x[3] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f16; + acc1 = 0.0f16; + acc2 = 0.0f16; + acc3 = 0.0f16; + + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[1] * y[0] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[2] * y[0] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[3] * y[0] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += (_Float16)x1 * (_Float16)c0; + /* acc1 += x[2] * y[1] */ + acc1 += (_Float16)x2 * (_Float16)c0; + /* acc2 += x[3] * y[1] */ + acc2 += (_Float16)x3 * (_Float16)c0; + /* acc3 += x[4] * y[1] */ + acc3 += (_Float16)x0 * (_Float16)c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += (_Float16)x2 * (_Float16)c0; + /* acc1 += x[3] * y[2] */ + acc1 += (_Float16)x3 * (_Float16)c0; + /* acc2 += x[4] * y[2] */ + acc2 += (_Float16)x0 * (_Float16)c0; + /* acc3 += x[5] * y[2] */ + acc3 += (_Float16)x1 * (_Float16)c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += (_Float16)x3 * (_Float16)c0; + /* acc1 += x[4] * y[3] */ + acc1 += (_Float16)x0 * (_Float16)c0; + /* acc2 += x[5] * y[3] */ + acc2 += (_Float16)x1 * (_Float16)c0; + /* acc3 += x[6] * y[3] */ + acc3 += (_Float16)x2 * (_Float16)c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += (_Float16)x0 * (_Float16)c0; + /* acc1 += x[5] * y[4] */ + acc1 += (_Float16)x1 * (_Float16)c0; + /* acc2 += x[6] * y[4] */ + acc2 += (_Float16)x2 * (_Float16)c0; + /* acc3 += x[7] * y[4] */ + acc3 += (_Float16)x3 * (_Float16)c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f16; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (_Float16)*px++ * (_Float16)*py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float16_t *pIn1 = pSrcA; /* inputA pointer */ + const float16_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + _Float16 sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f16; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += (_Float16)pIn1[j] * (_Float16)pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c new file mode 100644 index 0000000..41a69a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c @@ -0,0 +1,1095 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f32.c + * Description: Correlation of floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup Corr Correlation + + Correlation is a mathematical operation that is similar to convolution. + As with convolution, correlation uses two signals to produce a third signal. + The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution. + Correlation is commonly used to measure the similarity between two signals. + It has applications in pattern recognition, cryptanalysis, and searching. + The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types. + Fast versions of the Q15 and Q31 functions are also provided. + + @par Algorithm + Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively. + The convolution of the two signals is denoted by + 
+      c[n] = a[n] * b[n]
+
+ In correlation, one of the signals is flipped in time + 
+       c[n] = a[n] * b[-n]
+
+ @par + and this is mathematically defined as + \image html CorrelateEquation.gif + @par + The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen. + The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2). + The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result. + + @note + The pDst should be initialized to all zeros before being used. + + @par Fixed-Point Behavior + Correlation requires summing up a large number of intermediate products. + As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation. + Refer to the function specific documentation below for further details of the particular algorithm used. + + @par Fast Versions + Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires + the input signals should be scaled down to avoid intermediate overflows. + + @par Opt Versions + Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation. + These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of correlate + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + + +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const float32_t *pX, *pY; + const float32_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + float32_t acc0; + float32_t acc1; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + float32_t acc0; + float32_t acc1; + float32_t acc2; + float32_t acc3; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_F32(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + *pDst = acc2; + pDst += incr; + *pDst = acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_F32(acc0, acc1, pX, pY, srcBLen); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, srcBLen); + + *pDst = acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + float32_t acc0; + float32_t acc1; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_F32(acc0, acc1, pX, pY, count); + + *pDst = acc0; + pDst += incr; + *pDst = acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + float32_t acc; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_F32(acc, pX, pY, count); + + *pDst = acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_AUTOVECTORIZE) + + const float32_t *pIn1; /* InputA pointer */ + const float32_t *pIn2; /* InputB pointer */ + float32_t *pOut = pDst; /* Output pointer */ + const float32_t *px; /* Intermediate inputA pointer */ + const float32_t *py; /* Intermediate inputB pointer */ + const float32_t *pSrc1; + float32_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + float32_t acc0, acc1, acc2, acc3,c0; /* Accumulators */ +#if !defined(ARM_MATH_NEON) + float32_t x0, x1, x2, x3; /* temporary variables for holding input and coefficient values */ +#endif +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; + + k = count & 0x3; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += *px++ * *py++; + + /* x[1] * y[srcBLen - 3] */ + sum += *px++ * *py++; + + /* x[2] * y[srcBLen - 2] */ + sum += *px++ * *py++; + + /* x[3] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#endif /* #if defined(ARM_MATH_NEON) */ +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t c; + float32x4_t x1v; + float32x4_t x2v; + float32x4_t x; + float32x4_t res = vdupq_n_f32(0) ; +#endif /* #if defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + +#if defined(ARM_MATH_NEON) + /* Compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + res = vdupq_n_f32(0) ; + + x1v = vld1q_f32(px); + px += 4; + do + { + x2v = vld1q_f32(px); + c = vld1q_f32(py); + + py += 4; + + x = x1v; + res = vmlaq_n_f32(res,x,c[0]); + + x = vextq_f32(x1v,x2v,1); + + res = vmlaq_n_f32(res,x,c[1]); + + x = vextq_f32(x1v,x2v,2); + + res = vmlaq_n_f32(res,x,c[2]); + + x = vextq_f32(x1v,x2v,3); + + res = vmlaq_n_f32(res,x,c[3]); + + x1v = x2v; + px+=4; + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen & 0x3; + + while (k > 0U) + { + /* Read y[srcBLen - 5] sample */ + c0 = *(py++); + + res = vmlaq_n_f32(res,x1v,c0); + + /* Reuse the present samples for the next MAC */ + x1v[0] = x1v[1]; + x1v[1] = x1v[2]; + x1v[2] = x1v[3]; + + x1v[3] = *(px++); + + /* Decrement the loop counter */ + k--; + } + + px-=1; + + acc0 = res[0]; + acc1 = res[1]; + acc2 = res[2]; + acc3 = res[3]; +#else + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py++); + /* Read x[3] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += x0 * c0; + /* acc1 += x[1] * y[0] */ + acc1 += x1 * c0; + /* acc2 += x[2] * y[0] */ + acc2 += x2 * c0; + /* acc3 += x[3] * y[0] */ + acc3 += x3 * c0; + + /* Read y[1] sample */ + c0 = *(py++); + /* Read x[4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += x1 * c0; + /* acc1 += x[2] * y[1] */ + acc1 += x2 * c0; + /* acc2 += x[3] * y[1] */ + acc2 += x3 * c0; + /* acc3 += x[4] * y[1] */ + acc3 += x0 * c0; + + /* Read y[2] sample */ + c0 = *(py++); + /* Read x[5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += x2 * c0; + /* acc1 += x[3] * y[2] */ + acc1 += x3 * c0; + /* acc2 += x[4] * y[2] */ + acc2 += x0 * c0; + /* acc3 += x[5] * y[2] */ + acc3 += x1 * c0; + + /* Read y[3] sample */ + c0 = *(py++); + /* Read x[6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[3] * y[3] */ + acc0 += x3 * c0; + /* acc1 += x[4] * y[3] */ + acc1 += x0 * c0; + /* acc2 += x[5] * y[3] */ + acc2 += x1 * c0; + /* acc3 += x[6] * y[3] */ + acc3 += x2 * c0; + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + /* Read x[7] sample */ + x3 = *(px++); + + /* Perform the multiply-accumulate */ + /* acc0 += x[4] * y[4] */ + acc0 += x0 * c0; + /* acc1 += x[5] * y[4] */ + acc1 += x1 * c0; + /* acc2 += x[6] * y[4] */ + acc2 += x2 * c0; + /* acc3 += x[7] * y[4] */ + acc3 += x3 * c0; + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement the loop counter */ + k--; + } + +#endif /* #if defined(ARM_MATH_NEON) */ + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = acc0; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = acc1; + pOut += inc; + + *pOut = acc2; + pOut += inc; + + *pOut = acc3; + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } +#endif /* #if defined(ARM_MATH_NEON) */ + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + +#if defined(ARM_MATH_NEON) + float32x4_t x,y; + float32x4_t res = vdupq_n_f32(0) ; + float32x2_t accum = vdup_n_f32(0); + + while (k > 0U) + { + x = vld1q_f32(px); + y = vld1q_f32(py); + + res = vmlaq_f32(res,x, y); + + px += 4; + py += 4; + + /* Decrement the loop counter */ + k--; + } + + accum = vpadd_f32(vget_low_f32(res), vget_high_f32(res)); + sum += accum[0] + accum[1]; +#else + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + +#endif /* #if defined (ARM_MATH_NEON) */ + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) || defined(ARM_MATH_NEON) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const float32_t *pIn1 = pSrcA; /* inputA pointer */ + const float32_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + float32_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we assume zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0.0f; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if ((((i - j) < srcBLen) && (j < srcALen))) + { + /* z[i] += x[i-j] * y[j] */ + sum += pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]; + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = sum; + else + *pDst++ = sum; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c new file mode 100644 index 0000000..95edd40 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f64.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_f64.c + * Description: Correlation of floating-point sequences + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of floating-point sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ + +void arm_correlate_f64( + const float64_t * pSrcA, + uint32_t srcALen, + const float64_t * pSrcB, + uint32_t srcBLen, + float64_t * pDst) +{ + const float64_t *pIn1; /* InputA pointer */ + const float64_t *pIn2; /* InputB pointer */ + float64_t *pOut = pDst; /* Output pointer */ + const float64_t *px; /* Intermediate inputA pointer */ + const float64_t *py; /* Intermediate inputB pointer */ + const float64_t *pSrc1; + float64_t sum; + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we assume zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding has to be done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize k with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Loop over srcBLen */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0.; + + /* Initialize blkCnt with number of samples */ + k = count; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c new file mode 100644 index 0000000..0b37b18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c @@ -0,0 +1,345 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_opt_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q31_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Destination address modifier */ + uint32_t tapCnt; /* Loop count */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLAD(x2, y2, acc0); + acc2 = __SMLAD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + acc1 = __SMLADX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + ** Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c new file mode 100644 index 0000000..7d8857a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c @@ -0,0 +1,614 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q15.c + * Description: Fast Q15 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result. + + @remark + Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion. + */ + +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* -------------------- + * Stage2 process + * -------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(x1, c0, acc3); + + } while (--k); + + /* For the next MAC operations, SIMD is not used + * So, the 16 bit pointer if inputB, py is updated */ + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; + +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD (x0, c0, acc0); + acc1 = __SMLAD (x1, c0, acc1); + acc2 = __SMLADX(x1, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + acc2 = __SMLAD(x3, c0, acc2); + acc3 = __SMLAD(x2, c0, acc3); + + c0 = (*py); + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLADX(x1, c0, acc0); + acc1 = __SMLAD (x2, c0, acc1); + acc2 = __SMLADX(x2, c0, acc2); + acc3 = __SMLADX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (acc0 >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (acc1 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc2 >> 15); + pOut += inc; + + *pOut = (q15_t) (acc3 >> 15); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q31_t) * px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q31_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = __SMLAD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (sum >> 15); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement the MAC count */ + count--; + + /* Decrement the loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c new file mode 100644 index 0000000..e3d2bbf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c @@ -0,0 +1,601 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_fast_q31.c + * Description: Fast Q31 Correlation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are accumulated in a 32-bit register in 2.30 format. + Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + + @remark + Refer to \ref arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. + */ + +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[1] * y[srcBLen - 3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[2] * y[srcBLen - 2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* x[3] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unroll over blockSize2, by 4 */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read x[3] sample */ + x3 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[1] * y[0] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[2] * y[0] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[3] * y[0] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + + /* Read y[1] sample */ + c0 = *py++; + /* Read x[4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc1 += x[2] * y[1] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc2 += x[3] * y[1] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc3 += x[4] * y[1] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32); + + + /* Read y[2] sample */ + c0 = *py++; + /* Read x[5] sample */ + x1 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[2] * y[2] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc1 += x[3] * y[2] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc2 += x[4] * y[2] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc3 += x[5] * y[2] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32); + + + /* Read y[3] sample */ + c0 = *py++; + /* Read x[6] sample */ + x2 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[3] * y[3] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32); + /* acc1 += x[4] * y[3] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc2 += x[5] * y[3] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc3 += x[6] * y[3] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32); + + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + /* acc1 += x[5] * y[4] */ + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + /* acc2 += x[6] * y[4] */ + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + /* acc3 += x[7] * y[4] */ + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 << 1); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 << 1); + pOut += inc; + + *pOut = (q31_t) (acc2 << 1); + pOut += inc; + + *pOut = (q31_t) (acc3 << 1); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 4 */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U; + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = (q31_t) ((((q63_t) sum << 32) + + ((q63_t) *px++ * (*py++))) >> 32); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = sum << 1; + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c new file mode 100644 index 0000000..00bb088 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + */ + +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch) +{ + q63_t acc0; /* Accumulators */ + q15_t *pOut = pDst; /* Output pointer */ + q15_t *pScr1; /* Temporary pointer for scratch1 */ + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + uint32_t j, blkCnt, outBlockSize; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t tapCnt; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */ + q31_t y1, y2; /* State variables */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + pScr1 = pScratch; + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + arm_copy_q15(pIn1, pScr1, srcALen); + + /* Update pointers */ + pScr1 += srcALen; + + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pIn2; + + + /* Actual correlation process starts here */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia ((q15_t **) &pIn2); + y2 = read_q15x2_ia ((q15_t **) &pIn2); + + /* multiply and accumulate */ + acc0 = __SMLALD(x1, y1, acc0); + acc2 = __SMLALD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLALDX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* multiply and accumulate */ + acc0 = __SMLALD(x2, y2, acc0); + acc2 = __SMLALD(x1, y2, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLALDX(x3, y1, acc3); + acc1 = __SMLALDX(x3, y2, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLALDX(x3, y2, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2); + acc1 += (*pScr1++ * *pIn2); + acc2 += (*pScr1++ * *pIn2); + acc3 += (*pScr1++ * *pIn2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + + /* Store the results in the accumulators in the destination buffer. */ + *pOut = (__SSAT(acc0 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc1 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc2 >> 15U, 16)); + pOut += inc; + *pOut = (__SSAT(acc3 >> 15U, 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 4U; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (srcALen + srcBLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + + /* Read next two samples from scratch1 buffer */ + acc0 += (*pScr1++ * *pIn2++); + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pIn2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pOut = (q15_t) (__SSAT((acc0 >> 15), 16)); + pOut += inc; + + /* Initialization of inputB pointer */ + pIn2 = py; + + pScratch += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c new file mode 100644 index 0000000..145ba2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c @@ -0,0 +1,388 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_opt_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format. + */ + +void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2) +{ + q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */ + q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */ + q15_t x4; /* Temporary input variable */ + q15_t *py; /* Temporary input2 pointer */ + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */ + uint32_t j, k, blkCnt, tapCnt; /* Loop counter */ + int32_t inc = 1; /* Output pointer increment */ + uint32_t outBlockSize; /* Loop counter */ + q31_t x1, x2, x3, y1; /* Temporary input variables */ + q7_t *pOut = pDst; /* Output pointer */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + + /* Copy (srcBLen) samples in scratch buffer */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) *pIn2++; + *pScr2++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros in scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update temporary scratch pointer */ + pScr1 += (srcBLen - 1U); + + /* Copy (srcALen) samples in scratch buffer */ + /* Apply loop unrolling and do 4 Copies simultaneously. */ + k = srcALen >> 2U; + + /* First part of the processing with loop unrolling copies 4 data points at a time. + a second loop below copies for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* copy second buffer in reversal manner */ + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + x4 = (q15_t) *pIn1++; + *pScr1++ = x4; + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, copy remaining samples here. + No loop unrolling is used. */ + k = srcALen % 0x4U; + + while (k > 0U) + { + /* copy second buffer in reversal manner for remaining samples */ + x4 = (q15_t) * pIn1++; + *pScr1++ = x4; + + /* Decrement the loop counter */ + k--; + } + + /* Fill (srcBLen - 1U) zeros at end of scratch buffer */ + arm_fill_q15(0, pScr1, (srcBLen - 1U)); + + /* Update pointer */ + pScr1 += (srcBLen - 1U); + + /* Temporary pointer for scratch2 */ + py = pScratch2; + + /* Initialization of pScr2 pointer */ + pScr2 = pScratch2; + + /* Actual correlation process starts here */ + blkCnt = (srcALen + srcBLen - 1U) >> 2; + + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Read two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* Read next two samples from scratch1 buffer */ + x2 = read_q15x2_ia (&pScr1); + + tapCnt = (srcBLen) >> 2U; + + while (tapCnt > 0U) + { + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + /* multiply and accumulate */ + acc0 = __SMLAD(x1, y1, acc0); + acc2 = __SMLAD(x2, y1, acc2); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + /* multiply and accumulate */ + acc1 = __SMLADX(x3, y1, acc1); + + /* Read next two samples from scratch1 buffer */ + x1 = read_q15x2_ia (&pScr1); + + /* pack input data */ +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x1, x2, 0); +#else + x3 = __PKHBT(x2, x1, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Read four samples from smaller buffer */ + y1 = read_q15x2_ia (&pScr2); + + acc0 = __SMLAD(x2, y1, acc0); + + acc2 = __SMLAD(x1, y1, acc2); + + acc1 = __SMLADX(x3, y1, acc1); + + x2 = read_q15x2_ia (&pScr1); + +#ifndef ARM_MATH_BIG_ENDIAN + x3 = __PKHBT(x2, x1, 0); +#else + x3 = __PKHBT(x1, x2, 0); +#endif + + acc3 = __SMLADX(x3, y1, acc3); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Update scratch pointer for remaining samples of smaller length sequence */ + pScr1 -= 4U; + + /* apply same above for remaining samples of smaller length sequence */ + tapCnt = (srcBLen) & 3U; + + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2); + acc1 += (*pScr1++ * *pScr2); + acc2 += (*pScr1++ * *pScr2); + acc3 += (*pScr1++ * *pScr2++); + + pScr1 -= 3U; + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8)); + pOut += inc; + *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 4U; + } + + blkCnt = (srcALen + srcBLen - 1U) & 0x3; + + /* Calculate correlation for remaining samples of Bigger length sequence */ + while (blkCnt > 0) + { + /* Initialze temporary scratch pointer as scratch1 */ + pScr1 = pScratch1; + + /* Clear Accumlators */ + acc0 = 0; + + tapCnt = (srcBLen) >> 1U; + + while (tapCnt > 0U) + { + acc0 += (*pScr1++ * *pScr2++); + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + tapCnt = (srcBLen) & 1U; + + /* apply same above for remaining samples of smaller length sequence */ + while (tapCnt > 0U) + { + /* accumulate the results */ + acc0 += (*pScr1++ * *pScr2++); + + /* Decrement loop counter */ + tapCnt--; + } + + blkCnt--; + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8)); + pOut += inc; + + /* Initialization of inputB pointer */ + pScr2 = py; + + pScratch1 += 1U; + } + +} + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c new file mode 100644 index 0000000..2dd16d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c @@ -0,0 +1,903 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q15.c + * Description: Correlation of Q15 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both inputs are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + + @remark + Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function. + @remark + Refer to \ref arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" + +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + const q15_t *pIn1 = pSrcA; /* inputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q15_t *pX; + const q15_t *pY; + const q15_t *pA; + const q15_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 2U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -2; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv / 2; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q15(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + *pDst = (q15_t) acc2; + pDst += incr; + *pDst = (q15_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q15(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, srcBLen); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q15(acc0, acc1, pX, pY, count); + + *pDst = (q15_t) acc0; + pDst += incr; + *pDst = (q15_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q15(acc, pX, pY, count); + + *pDst = (q15_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst) +{ + +#if defined (ARM_MATH_DSP) + + const q15_t *pIn1; /* InputA pointer */ + const q15_t *pIn2; /* InputB pointer */ + q15_t *pOut = pDst; /* Output pointer */ + q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */ + const q15_t *px; /* Intermediate inputA pointer */ + const q15_t *py; /* Intermediate inputB pointer */ + const q15_t *pSrc1; /* Intermediate pointers */ + q31_t x0, x1, x2, x3, c0; /* Temporary input variables for holding input and coefficient values */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (srcALen * 2U) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first loop starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is the index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1] samples */ + x0 = read_q15x2 ((q15_t *) px); + + /* read x[1], x[2] samples */ + x1 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read the first two inputB samples using SIMD: + * y[0] and y[1] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLALD(x1, c0, acc1); + + /* Read x[2], x[3] */ + x2 = read_q15x2 ((q15_t *) px); + + /* Read x[3], x[4] */ + x3 = read_q15x2 ((q15_t *) px + 1); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLALD(x3, c0, acc3); + + /* Read y[2] and y[3] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLALD(x3, c0, acc1); + + /* Read x[4], x[5] */ + x0 = read_q15x2 ((q15_t *) px + 2); + + /* Read x[5], x[6] */ + x1 = read_q15x2 ((q15_t *) px + 3); + px += 4U; + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLALD(x1, c0, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + if (k == 1U) + { + /* Read y[4] */ + c0 = *py; +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[7] */ + x3 = read_q15x2 ((q15_t *) px); + px++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD (x0, c0, acc0); + acc1 = __SMLALD (x1, c0, acc1); + acc2 = __SMLALDX(x1, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + if (k == 2U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2 ((q15_t *) py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + px += 2U; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + } + + if (k == 3U) + { + /* Read y[4], y[5] */ + c0 = read_q15x2_ia ((q15_t **) &py); + + /* Read x[7], x[8] */ + x3 = read_q15x2 ((q15_t *) px); + + /* Read x[9] */ + x2 = read_q15x2 ((q15_t *) px + 1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + acc2 = __SMLALD(x3, c0, acc2); + acc3 = __SMLALD(x2, c0, acc3); + + c0 = (*py); + + /* Read y[6] */ +#ifdef ARM_MATH_BIG_ENDIAN + c0 = c0 << 16U; +#else + c0 = c0 & 0x0000FFFF; +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + /* Read x[10] */ + x3 = read_q15x2 ((q15_t *) px + 2); + px += 3U; + + /* Perform the multiply-accumulates */ + acc0 = __SMLALDX(x1, c0, acc0); + acc1 = __SMLALD (x2, c0, acc1); + acc2 = __SMLALDX(x2, c0, acc2); + acc3 = __SMLALDX(x3, c0, acc3); + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(acc0 >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc1 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc2 >> 15, 16)); + pOut += inc; + + *pOut = (q15_t) (__SSAT(acc3 >> 15, 16)); + pOut += inc; + + /* Increment the count by 4 as 4 output values are computed */ + count += 4U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize2 % 0x4U; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + sum += ((q63_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment count by 1, as one output value is computed */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q63_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT(sum >> 15, 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = count >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */ + sum = __SMLALD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum); + + /* Decrement loop counter */ + k--; + } + + /* If the count is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = count % 0x4U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum = __SMLALD(*px++, *py++, sum); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q15_t) (__SSAT((sum >> 15), 16)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + const q15_t *pIn1 = pSrcA; /* InputA pointer */ + const q15_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of values */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry on MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q15_t) __SSAT((sum >> 15U), 16U); + else + *pDst++ = (q15_t) __SSAT((sum >> 15U), 16U); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c new file mode 100644 index 0000000..a5f15fe --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c @@ -0,0 +1,879 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q31.c + * Description: Correlation of Q31 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q31 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + There is no saturation on intermediate additions. + Thus, if the accumulator overflows it wraps around and distorts the result. + The input signals should be scaled down to avoid intermediate overflows. + Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a + maximum of min(srcALen, srcBLen) number of additions is carried internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_correlate_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" +#include "arm_vec_filtering.h" +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + const q31_t *pIn1 = pSrcA; /* inputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + /* + * Loop to perform MAC operations according to correlation equation + */ + const q31_t *pX; + const q31_t *pY; + const q31_t *pA; + const q31_t *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 4; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialization of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -4; + + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + pA = pIn1; + pB = pIn2; + incr = inv / 4; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + /* compute 2 accumulators per loop */ + /* size is incrementing for second accumulator */ + /* Y pointer is decrementing for second accumulator */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + int64_t acc2 = 0LL; + int64_t acc3 = 0LL; + + pX = pA; + pY = pB; + /* compute 4 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for successive accumulators */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q31(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + *pDst = (q31_t) acc2; + pDst += incr; + *pDst = (q31_t) acc3; + pDst += incr; + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is fixed for all accumulators */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q31(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, srcBLen); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + + uint32_t count = (i + 1); + int64_t acc0 = 0LL; + int64_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* compute 2 accumulators per loop */ + /* size is decrementing for second accumulator */ + /* X pointer is incrementing for second accumulator */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q31(acc0, acc1, pX, pY, count); + + *pDst = (q31_t) acc0; + pDst += incr; + *pDst = (q31_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q31(acc, pX, pY, count); + + *pDst = (q31_t) acc; + pDst += incr; + pA++; + } +} +#else +void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q31_t *pIn1; /* InputA pointer */ + const q31_t *pIn2; /* InputB pointer */ + q31_t *pOut = pDst; /* Output pointer */ + const q31_t *px; /* Intermediate inputA pointer */ + const q31_t *py; /* Intermediate inputB pointer */ + const q31_t *pSrc1; /* Intermediate pointers */ + q63_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; /* Destination address modifier */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] * y[srcBLen - 4] */ + sum += (q63_t) *px++ * (*py++); + + /* x[1] * y[srcBLen - 3] */ + sum += (q63_t) *px++ * (*py++); + + /* x[2] * y[srcBLen - 2] */ + sum += (q63_t) *px++ * (*py++); + + /* x[3] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q63_t) *px++ * (*py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unroll by 3 */ + blkCnt = blockSize2 / 3; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* read x[0], x[1] samples */ + x0 = *px++; + x1 = *px++; + + /* Apply loop unrolling and compute 3 MACs simultaneously. */ + k = srcBLen / 3; + + /* First part of the processing with loop unrolling. Compute 3 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 2 samples. */ + do + { + /* Read y[0] sample */ + c0 = *(py); + /* Read x[2] sample */ + x2 = *(px); + + /* Perform the multiply-accumulate */ + /* acc0 += x[0] * y[0] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[1] * y[0] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[2] * y[0] */ + acc2 += ((q63_t) x2 * c0); + + /* Read y[1] sample */ + c0 = *(py + 1U); + /* Read x[3] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[1] * y[1] */ + acc0 += ((q63_t) x1 * c0); + /* acc1 += x[2] * y[1] */ + acc1 += ((q63_t) x2 * c0); + /* acc2 += x[3] * y[1] */ + acc2 += ((q63_t) x0 * c0); + + /* Read y[2] sample */ + c0 = *(py + 2U); + /* Read x[4] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulate */ + /* acc0 += x[2] * y[2] */ + acc0 += ((q63_t) x2 * c0); + /* acc1 += x[3] * y[2] */ + acc1 += ((q63_t) x0 * c0); + /* acc2 += x[4] * y[2] */ + acc2 += ((q63_t) x1 * c0); + + /* update scratch pointers */ + px += 3U; + py += 3U; + + } while (--k); + + /* If the srcBLen is not a multiple of 3, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen - (3 * (srcBLen / 3)); + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *(py++); + + /* Read x[7] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q63_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q63_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (acc0 >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q31_t) (acc1 >> 31); + pOut += inc; + + *pOut = (q31_t) (acc2 >> 31); + pOut += inc; + + /* Increment the pointer pIn1 index, count by 3 */ + count += 3U; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 - 3 * (blockSize2 / 3); + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulates */ + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum += (q63_t) *px++ * *py++; + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += (q63_t) *px++ * *py++; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q31_t) (sum >> 31); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q31_t *pIn1 = pSrcA; /* InputA pointer */ + const q31_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q63_t sum; /* Accumulators */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using correlation but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate correlation for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to correlation equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q31_t) (sum >> 31U); + else + *pDst++ = (q31_t) (sum >> 31U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c new file mode 100644 index 0000000..0b924e8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c @@ -0,0 +1,1002 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_correlate_q7.c + * Description: Correlation of Q7 sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup Corr + @{ + */ + +/** + @brief Correlation of Q7 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072. + The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format. + + @remark + Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_helium_utils.h" + +#include "arm_vec_filtering.h" +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + const q7_t *pIn1 = pSrcA; /* inputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* inputB pointer */ + const q7_t *pX, *pY; + const q7_t *pA, *pB; + int32_t i = 0U, j = 0; /* loop counters */ + int32_t inv = 1U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + int32_t block1, block2, block3; + int32_t incr; + + tot = ((srcALen + srcBLen) - 2U); + if (srcALen > srcBLen) + { + /* + * Calculating the number of zeros to be padded to the output + */ + j = srcALen - srcBLen; + /* + * Initialize the pointer after zero padding + */ + pDst += j; + } + else if (srcALen < srcBLen) + { + /* + * Initialization to inputB pointer + */ + pIn1 = pSrcB; + /* + * Initialization to the end of inputA pointer + */ + pIn2 = pSrcA + (srcALen - 1U); + /* + * Initialisation of the pointer after zero padding + */ + pDst = pDst + tot; + /* + * Swapping the lengths + */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + /* + * Setting the reverse flag + */ + inv = -1; + } + + block1 = srcBLen - 1; + block2 = srcALen - srcBLen + 1; + block3 = srcBLen - 1; + + pA = pIn1; + pB = pIn2; + incr = inv; + + for (i = 0U; i <= block1 - 2; i += 2) + { + uint32_t count = i + 1; + int32_t acc0 = 0; + int32_t acc1 = 0; + + /* + * compute 2 accumulators per loop + * size is incrementing for second accumulator + * Y pointer is decrementing for second accumulator + */ + pX = pA; + pY = pB; + MVE_INTR_CORR_DUAL_DEC_Y_INC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pB -= 2; + } + for (; i < block1; i++) + { + uint32_t count = i + 1; + int32_t acc = 0; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pB--; + } + + for (i = 0U; i <= block2 - 4; i += 4) + { + int32_t acc0 = 0; + int32_t acc1 = 0; + int32_t acc2 = 0; + int32_t acc3 = 0; + + pX = pA; + pY = pB; + /* + * compute 4 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for successive accumulators + */ + MVE_INTR_CORR_QUAD_INC_X_FIXED_SIZE_Q7(acc0, acc1, acc2, acc3, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + *pDst = (q7_t) acc2; + pDst += incr; + *pDst = (q7_t) acc3; + pDst += incr; + + pA += 4; + } + + for (; i <= block2 - 2; i += 2) + { + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is fixed for all accumulators + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_FIXED_SIZE_Q7(acc0, acc1, pX, pY, srcBLen); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + } + + if (block2 & 1) + { + int32_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, srcBLen); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } + + for (i = block3 - 1; i >= 0; i -= 2) + { + uint32_t count = (i + 1); + int32_t acc0 = 0LL; + int32_t acc1 = 0LL; + + pX = pA; + pY = pB; + /* + * compute 2 accumulators per loop + * size is decrementing for second accumulator + * X pointer is incrementing for second accumulator + */ + MVE_INTR_CORR_DUAL_INC_X_DEC_SIZE_Q7(acc0, acc1, pX, pY, count); + + *pDst = (q7_t) acc0; + pDst += incr; + *pDst = (q7_t) acc1; + pDst += incr; + pA += 2; + + } + for (; i >= 0; i--) + { + uint32_t count = (i + 1); + int64_t acc = 0LL; + + pX = pA; + pY = pB; + MVE_INTR_CORR_SINGLE_Q7(acc, pX, pY, count); + + *pDst = (q7_t) acc; + pDst += incr; + pA++; + } +} + +#else +void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst) +{ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + const q7_t *pIn1; /* InputA pointer */ + const q7_t *pIn2; /* InputB pointer */ + q7_t *pOut = pDst; /* Output pointer */ + const q7_t *px; /* Intermediate inputA pointer */ + const q7_t *py; /* Intermediate inputB pointer */ + const q7_t *pSrc1; /* Intermediate pointers */ + q31_t sum; /* Accumulators */ + uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */ + uint32_t j, k, count, blkCnt; /* Loop counters */ + uint32_t outBlockSize; + int32_t inc = 1; + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc0, acc1, acc2, acc3; /* Accumulators */ + q31_t input1, input2; /* Temporary input variables */ + q15_t in1, in2; /* Temporary input variables */ + q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */ +#endif + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and the destination pointer modifier, inc is set to -1 */ + /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */ + /* But to improve the performance, + * we include zeroes in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, + * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */ + /* If srcALen < srcBLen, + * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */ + if (srcALen >= srcBLen) + { + /* Initialization of inputA pointer */ + pIn1 = pSrcA; + + /* Initialization of inputB pointer */ + pIn2 = pSrcB; + + /* Number of output samples is calculated */ + outBlockSize = (2U * srcALen) - 1U; + + /* When srcALen > srcBLen, zero padding is done to srcB + * to make their lengths equal. + * Instead, (outBlockSize - (srcALen + srcBLen - 1)) + * number of output samples are made zero */ + j = outBlockSize - (srcALen + (srcBLen - 1U)); + + /* Updating the pointer position to non zero value */ + pOut += j; + } + else + { + /* Initialization of inputA pointer */ + pIn1 = pSrcB; + + /* Initialization of inputB pointer */ + pIn2 = pSrcA; + + /* srcBLen is always considered as shorter or equal to srcALen */ + j = srcBLen; + srcBLen = srcALen; + srcALen = j; + + /* CORR(x, y) = Reverse order(CORR(y, x)) */ + /* Hence set the destination pointer to point to the last output sample */ + pOut = pDst + ((srcALen + srcBLen) - 2U); + + /* Destination address modifier is set to -1 */ + inc = -1; + } + + /* The function is internally + * divided into three stages according to the number of multiplications that has to be + * taken place between inputA samples and inputB samples. In the first stage of the + * algorithm, the multiplications increase by one for every iteration. + * In the second stage of the algorithm, srcBLen number of multiplications are done. + * In the third stage of the algorithm, the multiplications decrease by one + * for every iteration. */ + + /* The algorithm is implemented in three stages. + The loop counters of each stage is initiated here. */ + blockSize1 = srcBLen - 1U; + blockSize2 = srcALen - (srcBLen - 1U); + blockSize3 = blockSize1; + + /* -------------------------- + * Initializations of stage1 + * -------------------------*/ + + /* sum = x[0] * y[srcBlen - 1] + * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1] + * .... + * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1] + */ + + /* In this stage the MAC operations are increased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = 1U; + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + pSrc1 = pIn2 + (srcBLen - 1U); + py = pSrc1; + + /* ------------------------ + * Stage1 process + * ----------------------*/ + + /* The first stage starts here */ + while (blockSize1 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[0] , x[1] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 4] , y[srcBLen - 3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[0] * y[srcBLen - 4] */ + /* x[1] * y[srcBLen - 3] */ + sum = __SMLAD(input1, input2, sum); + + /* x[2] , x[3] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* y[srcBLen - 2] , y[srcBLen - 1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* x[2] * y[srcBLen - 2] */ + /* x[3] * y[srcBLen - 1] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize k with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + /* x[0] * y[srcBLen - 1] */ + sum += (q31_t) ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + py = pSrc1 - count; + px = pIn1; + + /* Increment MAC count */ + count++; + + /* Decrement loop counter */ + blockSize1--; + } + + /* -------------------------- + * Initializations of stage2 + * ------------------------*/ + + /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1] + * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1] + * .... + * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + */ + + /* Working pointer of inputA */ + px = pIn1; + + /* Working pointer of inputB */ + py = pIn2; + + /* count is index by which the pointer pIn1 to be incremented */ + count = 0U; + + /* ------------------- + * Stage2 process + * ------------------*/ + + /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed. + * So, to loop unroll over blockSize2, + * srcBLen should be greater than or equal to 4 */ + if (srcBLen >= 4U) + { +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize2 >> 2U; + + while (blkCnt > 0U) + { + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* read x[0], x[1], x[2] samples */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + k = srcBLen >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 MACs at a time. + ** a second loop below computes MACs for the remaining 1 to 3 samples. */ + do + { + /* Read y[0] sample */ + c0 = *py++; + /* Read y[1] sample */ + c1 = *py++; + + /* Read x[3] sample */ + x3 = *px++; + + /* x[0] and x[1] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] and y[1] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[0] * y[0] + x[1] * y[1] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[1] and x[2] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[1] * y[0] + x[2] * y[1] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[2] * y[0] + x[3] * y[1] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[4] sample */ + x0 = *px++; + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[3] * y[0] + x[4] * y[1] */ + acc3 = __SMLAD(input1, input2, acc3); + + /* Read y[2] sample */ + c0 = *py++; + /* Read y[3] sample */ + c1 = *py++; + + /* Read x[5] sample */ + x1 = *px++; + + /* x[2] and x[3] are packed */ + in1 = (q15_t) x2; + in2 = (q15_t) x3; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] and y[3] are packed */ + in1 = (q15_t) c0; + in2 = (q15_t) c1; + + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc0 += x[2] * y[2] + x[3] * y[3] */ + acc0 = __SMLAD(input1, input2, acc0); + + /* x[3] and x[4] are packed */ + in1 = (q15_t) x3; + in2 = (q15_t) x0; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc1 += x[3] * y[2] + x[4] * y[3] */ + acc1 = __SMLAD(input1, input2, acc1); + + /* x[4] and x[5] are packed */ + in1 = (q15_t) x0; + in2 = (q15_t) x1; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc2 += x[4] * y[2] + x[5] * y[3] */ + acc2 = __SMLAD(input1, input2, acc2); + + /* Read x[6] sample */ + x2 = *px++; + + /* x[5] and x[6] are packed */ + in1 = (q15_t) x1; + in2 = (q15_t) x2; + + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* acc3 += x[5] * y[2] + x[6] * y[3] */ + acc3 = __SMLAD(input1, input2, acc3); + + } while (--k); + + /* If the srcBLen is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + k = srcBLen % 0x4U; + + while (k > 0U) + { + /* Read y[4] sample */ + c0 = *py++; + /* Read x[7] sample */ + x3 = *px++; + + /* Perform the multiply-accumulates */ + /* acc0 += x[4] * y[4] */ + acc0 += ((q15_t) x0 * c0); + /* acc1 += x[5] * y[4] */ + acc1 += ((q15_t) x1 * c0); + /* acc2 += x[6] * y[4] */ + acc2 += ((q15_t) x2 * c0); + /* acc3 += x[7] * y[4] */ + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present samples for the next MAC */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(acc0 >> 7, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc1 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc2 >> 7, 8)); + pOut += inc; + + *pOut = (q7_t) (__SSAT(acc3 >> 7, 8)); + pOut += inc; + + count += 4U; + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize2 % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize2; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = srcBLen >> 2U; + + while (k > 0U) + { + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* Perform the multiply-accumulate */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = srcBLen % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = srcBLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the pointer pIn1 index, count by 1 */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* If the srcBLen is not a multiple of 4, + * the blockSize2 loop cannot be unrolled by 4 */ + blkCnt = blockSize2; + + while (blkCnt > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + + /* srcBLen number of MACS should be performed */ + k = srcBLen; + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement the loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Increment the MAC count */ + count++; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = pIn1 + count; + py = pIn2; + + /* Decrement loop counter */ + blkCnt--; + } + } + + + /* -------------------------- + * Initializations of stage3 + * -------------------------*/ + + /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1] + * .... + * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1] + * sum += x[srcALen-1] * y[0] + */ + + /* In this stage the MAC operations are decreased by 1 for every iteration. + The count variable holds the number of MAC operations performed */ + count = srcBLen - 1U; + + /* Working pointer of inputA */ + pSrc1 = pIn1 + (srcALen - (srcBLen - 1U)); + px = pSrc1; + + /* Working pointer of inputB */ + py = pIn2; + + /* ------------------- + * Stage3 process + * ------------------*/ + + while (blockSize3 > 0U) + { + /* Accumulator is made zero for every iteration */ + sum = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + k = count >> 2U; + + while (k > 0U) + { + /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[0] , y[1] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 1] * y[0] */ + /* sum += x[srcALen - srcBLen + 2] * y[1] */ + sum = __SMLAD(input1, input2, sum); + + /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */ + in1 = (q15_t) *px++; + in2 = (q15_t) *px++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* y[2] , y[3] */ + in1 = (q15_t) *py++; + in2 = (q15_t) *py++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U); + + /* sum += x[srcALen - srcBLen + 3] * y[2] */ + /* sum += x[srcALen - srcBLen + 4] * y[3] */ + sum = __SMLAD(input1, input2, sum); + + /* Decrement loop counter */ + k--; + } + + /* Loop unrolling: Compute remaining outputs */ + k = count % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + k = count; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (k > 0U) + { + /* Perform the multiply-accumulate */ + sum += ((q15_t) *px++ * *py++); + + /* Decrement loop counter */ + k--; + } + + /* Store the result in the accumulator in the destination buffer. */ + *pOut = (q7_t) (__SSAT(sum >> 7U, 8)); + /* Destination pointer is updated according to the address modifier, inc */ + pOut += inc; + + /* Update the inputA and inputB pointers for next MAC calculation */ + px = ++pSrc1; + py = pIn2; + + /* Decrement MAC count */ + count--; + + /* Decrement loop counter */ + blockSize3--; + } + +#else +/* alternate version for CM0_FAMILY */ + + const q7_t *pIn1 = pSrcA; /* InputA pointer */ + const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */ + q31_t sum; /* Accumulator */ + uint32_t i = 0U, j; /* Loop counters */ + uint32_t inv = 0U; /* Reverse order flag */ + uint32_t tot = 0U; /* Length */ + + /* The algorithm implementation is based on the lengths of the inputs. */ + /* srcB is always made to slide across srcA. */ + /* So srcBLen is always considered as shorter or equal to srcALen */ + /* But CORR(x, y) is reverse of CORR(y, x) */ + /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */ + /* and a varaible, inv is set to 1 */ + /* If lengths are not equal then zero pad has to be done to make the two + * inputs of same length. But to improve the performance, we include zeroes + * in the output instead of zero padding either of the the inputs*/ + /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the + * starting of the output buffer */ + /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the + * ending of the output buffer */ + /* Once the zero padding is done the remaining of the output is calcualted + * using convolution but with the shorter signal time shifted. */ + + /* Calculate the length of the remaining sequence */ + tot = ((srcALen + srcBLen) - 2U); + + if (srcALen > srcBLen) + { + /* Calculating the number of zeros to be padded to the output */ + j = srcALen - srcBLen; + + /* Initialise the pointer after zero padding */ + pDst += j; + } + + else if (srcALen < srcBLen) + { + /* Initialization to inputB pointer */ + pIn1 = pSrcB; + + /* Initialization to the end of inputA pointer */ + pIn2 = pSrcA + (srcALen - 1U); + + /* Initialisation of the pointer after zero padding */ + pDst = pDst + tot; + + /* Swapping the lengths */ + j = srcALen; + srcALen = srcBLen; + srcBLen = j; + + /* Setting the reverse flag */ + inv = 1; + } + + /* Loop to calculate convolution for output length number of times */ + for (i = 0U; i <= tot; i++) + { + /* Initialize sum with zero to carry out MAC operations */ + sum = 0; + + /* Loop to perform MAC operations according to convolution equation */ + for (j = 0U; j <= i; j++) + { + /* Check the array limitations */ + if (((i - j) < srcBLen) && (j < srcALen)) + { + /* z[i] += x[i-j] * y[j] */ + sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - (int32_t) j)]); + } + } + + /* Store the output in the destination buffer */ + if (inv == 1) + *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U); + else + *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U); + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Corr group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c new file mode 100644 index 0000000..443efa0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c @@ -0,0 +1,951 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_f32.c + * Description: FIR decimation for floating-point sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator + + These functions combine an FIR filter together with a decimator. + They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRDecimator.gif "Components included in the FIR Decimator functions" + When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized + cutoff frequency of 1/M in order to prevent aliasing distortion. + The user of the function is responsible for providing the filter coefficients. + + The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner. + Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the + samples output by the decimator are computed. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize/M output values. + In order to have an integer number of output samples blockSize + must always be a multiple of the decimation factor M. + + The library provides separate functions for Q15, Q31 and floating-point data types. + + @par Algorithm: + The FIR portion of the algorithm uses the standard form filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ where, b[n] are the filter coefficients. + @par + The pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the size of the input is a multiple of the decimation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+      arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter; + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR decimate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const float32_t *px0, *px1, *px2, *px3; + f32x4_t accv, acc0v, acc1v, acc2v, acc3v; + f32x4_t x0v, x1v, x2v, x3v; + f32x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vld1q((const float32_t *)pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Set accumulators to zero + */ + acc0v = vdupq_n_f32(0.0f); + acc1v = vdupq_n_f32(0.0f); + acc2v = vdupq_n_f32(0.0f); + acc3v = vdupq_n_f32(0.0f); + + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vld1q((const float32_t *)pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq(acc0v, x0v, c0v); + acc1v = vfmaq(acc1v, x1v, c0v); + acc2v = vfmaq(acc2v, x2v, c0v); + acc3v = vfmaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_f32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vfmaq_f32(acc0v, x0v, c0v); + acc1v = vfmaq_f32(acc1v, x1v, c0v); + acc2v = vfmaq_f32(acc2v, x2v, c0v); + acc3v = vfmaq_f32(acc3v, x3v, c0v); + } + + /* reduction */ + accv[0] = vecAddAcrossF32Mve(acc0v); + accv[1] = vecAddAcrossF32Mve(acc1v); + accv[2] = vecAddAcrossF32Mve(acc2v); + accv[3] = vecAddAcrossF32Mve(acc3v); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + vst1q(pDst, accv); + pDst += 4; + + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = vdupq_n_f32(0.0f); + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_f32(pb); + x0v = vldrwq_f32(px); + pb += 4; + px += 4; + acc0v = vfmaq_f32(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_f32(pb, p0); + x0v = vldrwq_f32(px); + acc0v = vfmaq_f32(acc0v, x0v, c0v); + } + accv[0] = vecAddAcrossF32Mve(acc0v); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = accv[0]; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt =(numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulator */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + uint32_t blkCntN4; + float32_t *px0, *px1, *px2, *px3; + float32_t x1, x2, x3; + + float32x4_t accv,acc0v,acc1v,acc2v,acc3v; + float32x4_t x0v, x1v, x2v, x3v; + float32x4_t c0v; + float32x2_t temp; + float32x4_t sum0v; + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = 4 * S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0v = vdupq_n_f32(0.0); + acc1v = vdupq_n_f32(0.0); + acc2v = vdupq_n_f32(0.0); + acc3v = vdupq_n_f32(0.0); + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0v = vld1q_f32(pb); + pb += 4; + + /* Read x[n-numTaps-1] sample for acc0 */ + x0v = vld1q_f32(px0); + x1v = vld1q_f32(px1); + x2v = vld1q_f32(px2); + x3v = vld1q_f32(px3); + + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vmlaq_f32(acc0v, x0v, c0v); + acc1v = vmlaq_f32(acc1v, x1v, c0v); + acc2v = vmlaq_f32(acc2v, x2v, c0v); + acc3v = vmlaq_f32(acc3v, x3v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(acc0v),vget_high_f32(acc0v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,0); + + temp = vpadd_f32(vget_low_f32(acc1v),vget_high_f32(acc1v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,1); + + temp = vpadd_f32(vget_low_f32(acc2v),vget_high_f32(acc2v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,2); + + temp = vpadd_f32(vget_low_f32(acc3v),vget_high_f32(acc3v)); + accv = vsetq_lane_f32(vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1),accv,3); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 0) + x0 * c0,accv,0); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 1) + x1 * c0,accv,1); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 2) + x2 * c0,accv,2); + accv = vsetq_lane_f32(vgetq_lane_f32(accv, 3) + x3 * c0,accv,3); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + 4 * S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + vst1q_f32(pDst,accv); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCurnt++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Loop over the number of taps. + ** Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + c0v = vld1q_f32(pb); + pb += 4; + + x0v = vld1q_f32(px); + px += 4; + + sum0v = vmlaq_f32(sum0v, x0v, c0v); + + /* Decrement the loop counter */ + tapCnt--; + } + + temp = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(temp, 0) + vget_lane_f32(temp, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + i = (numTaps - 1U) >> 2; + + /* Copy data */ + while (i > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + i--; + } +} +#else +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *px0; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t x0, c0; /* Temporary variables to hold state and coefficient values */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t *px1, *px2, *px3; + float32_t x1, x2, x3; + float32_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = acc0; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +#endif /*defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c new file mode 100644 index 0000000..15bbb78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q15.c + * Description: Fast Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator (fast variant). + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2). + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + @remark + Refer to \ref arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q15() to initialize the filter structure. + */ + +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLAD(x0, c0, acc0); + acc1 = __SMLAD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLAD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q31_t sum0; /* Accumulators */ + q31_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c new file mode 100644 index 0000000..993f7ac --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c @@ -0,0 +1,390 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_fast_q31.c + * Description: Fast Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator (fast variant). + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + + @remark + Refer to \ref arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. + Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_decimate_init_q31() to initialize the filter structure. + */ + +void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32); + acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32); + acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c new file mode 100644 index 0000000..de31b9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_f32.c + * Description: Floating-point FIR Decimator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c new file mode 100644 index 0000000..b43df2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q15.c + * Description: Initialization function for the Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] S points to an instance of the Q15 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples + to the call arm_fir_decimate_q15(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c new file mode 100644 index 0000000..7a9490a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_init_q31.c + * Description: Initialization function for Q31 FIR Decimation filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] S points to an instance of the Q31 FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31(). + M is the decimation factor. + */ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The size of the input block must be a multiple of the decimation factor */ + if ((blockSize % M) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Decimation Factor */ + S->M = M; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +} + +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c new file mode 100644 index 0000000..21f18e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c @@ -0,0 +1,851 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q15.c + * Description: Q15 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] S points to an instance of the Q15 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q15_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q15x8_t x0v, x1v, x2v, x3v; + q15x8_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Need extra temp variables as 4 * S->M is not necessarily a multiple of 8 + * and cause final tail predicated post incremented pointers to jump ahead + */ + const q15_t *pSrcTmp = pSrc; + q15_t *pStateCurntTmp = pStateCurnt; + + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 3; + while (i > 0U) + { + vstrhq_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp)); + pSrcTmp += 8; + pStateCurntTmp += 8; + i--; + } + i = (4 * S->M) & 7; + if (i > 0U) + { + mve_pred16_t p0 = vctp16q(i); + vstrhq_p_s16(pStateCurntTmp, vldrhq_s16(pSrcTmp), p0); + } + + pSrc += (4 * S->M); + pStateCurnt += (4 * S->M); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_s16(pb); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrhq_z_s16(pb, p0); + pb += 8; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 8; + px1 += 8; + px2 += 8; + px3 += 8; + + acc0v = vmlaldavaq(acc0v, x0v, c0v); + acc1v = vmlaldavaq(acc1v, x1v, c0v); + acc2v = vmlaldavaq(acc2v, x2v, c0v); + acc3v = vmlaldavaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 15); + acc1v = asrl(acc1v, 15); + acc2v = asrl(acc2v, 15); + acc3v = asrl(acc3v, 15); + /* + * store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + *pDst++ = (q15_t) __SSAT((q31_t) acc1v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc2v, 16);; + *pDst++ = (q15_t) __SSAT((q31_t) acc3v, 16);; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + + tapCnt = numTaps >> 3; + while (tapCnt > 0U) + { + c0v = vldrhq_s16(pb); + x0v = vldrhq_s16(px); + pb += 8; + px += 8; + acc0v = vmlaldavaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = numTaps & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + c0v = vldrhq_z_s16(pb, p0); + x0v = vldrhq_z_s16(px, p0); + acc0v = vmlaldavaq_p(acc0v, x0v, c0v, p0); + } + + acc0v = asrl(acc0v, 15); + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q15_t) __SSAT((q31_t) acc0v, 16); + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (numTaps - 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +#if defined (ARM_MATH_DSP) + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t c1; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficient */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px0); + x1 = read_q15x2_ia (&px1); + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch state variables for acc0, acc1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 = __SMLALD(x0, c0, acc0); + acc1 = __SMLALD(x1, c0, acc1); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] and b[numTaps-2] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */ + x0 = read_q15x2_ia (&px); + + /* Read the b[numTaps-3] and b[numTaps-4] coefficients */ + c1 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */ + x0 = read_q15x2_ia (&px); + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c1, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 = __SMLALD(x0, c0, sum0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* Copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + +} + +#else /* #if defined (ARM_MATH_DSP) */ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */ + q63_t sum0; /* Accumulators */ + q63_t acc0, acc1; + q15_t *px0, *px1; + uint32_t blkCntN3; + uint32_t numTaps = S->numTaps; /* Number of taps */ + uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + + /* Total number of output samples to be computed */ + blkCnt = outBlockSize / 2; + blkCntN3 = outBlockSize - (2 * blkCnt); + + while (blkCnt > 0U) + { + /* Copy 2 * decimation factor number of new input samples into the state buffer */ + i = S->M * 2; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + + /* Initialize state pointer */ + px0 = pState; + px1 = pState + S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the Read b[numTaps-1] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-1] for sample 0 and for sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-3] coefficients */ + c0 = *pb++; + + /* Read x[n-numTaps-3] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] for sample 0 and sample 1 */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + x1 = *px1++; + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 2; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + while (blkCntN3 > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px++; + + /* Perform the multiply-accumulate */ + sum0 += x0 * c0; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* Store filter output, smlad returns the values in 2.14 format */ + /* so downsacle by 15 to get output in 1.15 */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + blkCntN3--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + i = (numTaps - 1U) >> 2U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } + + i = (numTaps - 1U) % 0x04U; + + /* copy data */ + while (i > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + i--; + } +} + +#endif /* #if defined (ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c new file mode 100644 index 0000000..77bfc16 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c @@ -0,0 +1,634 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_decimate_q31.c + * Description: Q31 FIR Decimator + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_decimate + @{ + */ + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] S points to an instance of the Q31 FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2). + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + + @remark + Refer to \ref arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + uint32_t blkCntN4; + const q31_t *px0, *px1, *px2, *px3; + q63_t acc0v, acc1v, acc2v, acc3v; + q31x4_t x0v, x1v, x2v, x3v; + q31x4_t c0v; + + /* + * S->pState buffer contains previous frame (numTaps - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (numTaps - 1U); + /* + * Total number of output samples to be computed + */ + blkCnt = outBlockSize / 4; + blkCntN4 = outBlockSize - (4 * blkCnt); + + while (blkCnt > 0U) + { + /* + * Copy 4 * decimation factor number of new input samples into the state buffer + */ + i = (4 * S->M) >> 2; + do + { + vst1q(pStateCurnt, vldrwq_s32(pSrc)); + pSrc += 4; + pStateCurnt += 4; + i--; + } + while (i > 0U); + + /* + * Clear all accumulators + */ + acc0v = 0LL; + acc1v = 0LL; + acc2v = 0LL; + acc3v = 0LL; + /* + * Initialize state pointer for all the samples + */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_s32(pb); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + /* + * If the filter length is not a multiple of 4, compute the remaining filter taps + * should be tail predicated + */ + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + /* + * Read the b[numTaps-1] coefficient + */ + c0v = vldrwq_z_s32(pb, p0); + pb += 4; + /* + * Read x[n-numTaps-1] sample for acc0 + */ + x0v = vld1q(px0); + x1v = vld1q(px1); + x2v = vld1q(px2); + x3v = vld1q(px3); + px0 += 4; + px1 += 4; + px2 += 4; + px3 += 4; + + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + acc1v = vrmlaldavhaq(acc1v, x1v, c0v); + acc2v = vrmlaldavhaq(acc2v, x2v, c0v); + acc3v = vrmlaldavhaq(acc3v, x3v, c0v); + } + + acc0v = asrl(acc0v, 31 - 8); + acc1v = asrl(acc1v, 31 - 8); + acc2v = asrl(acc2v, 31 - 8); + acc3v = asrl(acc3v, 31 - 8); + /* + * store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + *pDst++ = (q31_t) acc1v; + *pDst++ = (q31_t) acc2v; + *pDst++ = (q31_t) acc3v; + + /* + * Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples + */ + pState = pState + 4 * S->M; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + while (blkCntN4 > 0U) + { + /* + * Copy decimation factor number of new input samples into the state buffer + */ + i = S->M; + do + { + *pStateCurnt++ = *pSrc++; + } + while (--i); + /* + * Set accumulator to zero + */ + acc0v = 0LL; + /* + * Initialize state pointer + */ + px = pState; + /* + * Initialize coeff. pointer + */ + pb = pCoeffs; + /* + * Loop unrolling. Process 4 taps at a time. + */ + tapCnt = numTaps >> 2; + /* + * Loop over the number of taps. Unroll by a factor of 4. + * Repeat until we've computed numTaps-4 coefficients. + */ + while (tapCnt > 0U) + { + c0v = vldrwq_s32(pb); + x0v = vldrwq_s32(px); + pb += 4; + px += 4; + acc0v = vrmlaldavhaq(acc0v, x0v, c0v); + /* + * Decrement the loop counter + */ + tapCnt--; + } + tapCnt = numTaps % 0x4U; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + c0v = vldrwq_z_s32(pb, p0); + x0v = vldrwq_z_s32(px, p0); + acc0v = vrmlaldavhaq_p(acc0v, x0v, c0v, p0); + } + acc0v = asrl(acc0v, 31 - 8); + + /* + * Advance the state pointer by the decimation factor + * * to process the next group of decimation factor number samples + */ + pState = pState + S->M; + /* + * The result is in the accumulator, store in the destination buffer. + */ + *pDst++ = (q31_t) acc0v; + /* + * Decrement the loop counter + */ + blkCntN4--; + } + + /* + * Processing is complete. + * Now copy the last numTaps - 1 samples to the start of the state buffer. + * This prepares the state buffer for the next function call. + */ + pStateCurnt = S->pState; + blkCnt = (numTaps - 1) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (numTaps - 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *px0; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t x0, c0; /* Temporary variables to hold state and coefficient values */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t *px1, *px2, *px3; + q31_t x1, x2, x3; + q63_t acc1, acc2, acc3; +#endif + + /* S->pState buffer contains previous frame (numTaps - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (numTaps - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 samples at a time */ + blkCnt = outBlockSize >> 2U; + + /* Samples loop unrolled by 4 */ + while (blkCnt > 0U) + { + /* Copy 4 * decimation factor number of new input samples into the state buffer */ + i = S->M * 4; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer for all the samples */ + px0 = pState; + px1 = pState + S->M; + px2 = pState + 2 * S->M; + px3 = pState + 3 * S->M; + + /* Initialize coeff pointer */ + pb = pCoeffs; + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-1] sample for acc0 */ + x0 = *(px0++); + /* Read x[n-numTaps-1] sample for acc1 */ + x1 = *(px1++); + /* Read x[n-numTaps-1] sample for acc2 */ + x2 = *(px2++); + /* Read x[n-numTaps-1] sample for acc3 */ + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch state variables for acc0, acc1, acc2, acc3 */ + x0 = *(px0++); + x1 = *(px1++); + x2 = *(px2++); + x3 = *(px3++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M * 4; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + *pDst++ = (q31_t) (acc1 >> 31); + *pDst++ = (q31_t) (acc2 >> 31); + *pDst++ = (q31_t) (acc3 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining samples */ + blkCnt = outBlockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = outBlockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy decimation factor number of new input samples into the state buffer */ + i = S->M; + + do + { + *pStateCur++ = *pSrc++; + + } while (--i); + + /* Set accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px0 = pState; + + /* Initialize coeff pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-1] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-2] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-3] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *pb++; + + /* Read x[n-numTaps-4] sample */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *pb++; + + /* Fetch 1 state variable */ + x0 = *px0++; + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by the decimation factor + * to process the next group of decimation factor number samples */ + pState = pState + S->M; + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_decimate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c new file mode 100644 index 0000000..f89c2d3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f16.c @@ -0,0 +1,940 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f16.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupFilters + */ + + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F16_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f16(0.0f16); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f16_1_4_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +#define NB_TAPS 8 +__STATIC_INLINE void arm_fir_f16_5_8_mve(const arm_fir_instance_f16 * S, + const float16_t * __restrict pSrc, + float16_t * __restrict pDst, uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCur; /* Points to the current sample of the state */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float16x8_t vecIn0; + float16x8_t vecAcc0; + float16_t c[NB_TAPS]; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + /* + * Copy new data into state so that we obtain a continuous sample buffer + * containing both the tail end of the old data and the new data. + */ + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = pCoeffs[i]; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) { + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 8; + pSamples += 8; + + blkCnt--; + } + + blkCnt = blockSize & 7; + if (blkCnt) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + FIR_F16_CORE(pSamples, c, NB_TAPS); + + vstrhq_p_f16(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } + +} +#undef NB_TAPS + +void arm_fir_f16(const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pRefStatePtr = S->pState + ROUND_UP(blockSize, 8); + float16_t *pState = pRefStatePtr ; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float16_t *pSamples; /* Temporary pointer to the sample buffer */ + float16_t *pOutput; /* Temporary pointer to the output buffer */ + const float16_t *pTempSrc; /* Temporary pointer to the source data */ + float16_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float16_t c0, c1, c2, c3; + float16_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) { + arm_fir_f16_1_4_mve(S, pSrc, pDst, blockSize); + return; + } else if (numTaps <= 8) { + arm_fir_f16_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp16q(cnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 8; + pTempSrc += 8; + cnt -= 8; + } while (cnt > 0); + + float16_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + vecAcc0 += vld1q_f16(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + + } else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 3; + while (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 8; + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vst1q(pOutput, vecAcc0 + pap); + cnt--; + partial_accu_ptr += 8; + pOutput += 8; + } + + cnt = blockSize & 7; + if (cnt > 0) { + float16x8_t vecAcc0; + float16x8_t vecIn0; + + mve_pred16_t p0 = vctp16q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float16x8_t pap = vld1q_f16(partial_accu_ptr); + vstrhq_p_f16(pOutput, vecAcc0 + pap, p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_f16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else + +void arm_fir_f16( + const arm_fir_instance_f16 * S, + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + float16_t *pState = S->pState; /* State pointer */ + const float16_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float16_t *pStateCurnt; /* Points to the current sample of the state */ + float16_t *px; /* Temporary pointer for state buffer */ + const float16_t *pb; /* Temporary pointer for coefficient buffer */ + _Float16 acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + _Float16 x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + _Float16 c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (_Float16)*px++ * (_Float16)*pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** +* @} end of FIR group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c new file mode 100644 index 0000000..f8c1d80 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c @@ -0,0 +1,1285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f32.c + * Description: Floating-point FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR Finite Impulse Response (FIR) Filters + + This set of functions implements Finite Impulse Response (FIR) filters + for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays containing blockSize values. + + @par Algorithm + The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations. + Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n]. + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ @par + \image html FIR.GIF "Finite Impulse Response filter" + @par + pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the following order. + @par + 
+      {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[n](==pSrc[0]), x[n+1](==pSrc[1]), ..., x[n+blockSize-1](==pSrc[blockSize-1])}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1. + The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+      arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + @par Initialization of Helium version + For Helium version the array of coefficients must be padded with zero to contain + a full number of lanes. + + The array length L must be a multiple of x. L = x * a : + - x is 4 for f32 + - x is 4 for q31 + - x is 4 for f16 (so managed like the f32 version and not like the q15 one) + - x is 8 for q15 + - x is 16 for q7 + + The additional coefficients + (x * a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first A samples are temporary data. + The remaining samples are the state of the FIR filter. + @par + So the state buffer has size numTaps + A + blockSize - 1 : + - A is blockSize for f32 + - A is 8*ceil(blockSize/8) for f16 + - A is 8*ceil(blockSize/4) for q31 + - A is 0 for other datatypes (q15 and q7) + + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_F32_MAX_COEF_BLK 8 + +#define FIR_F32_CORE(pSamples, c, NB_TAPS) \ + vecAcc0 = vdupq_n_f32(0.0f); \ + for (int i = 0; i < NB_TAPS; i++) { \ + vecIn0 = vld1q(&pSamples[i]); \ + vecAcc0 = vfmaq(vecAcc0, vecIn0, c[i]); \ + } + + +#define NB_TAPS 4 +__STATIC_INLINE void arm_fir_f32_1_4_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32x4_t vecIn0; + float32x4_t vecAcc0; + float32_t c[NB_TAPS]; + const float32_t *pCoeffsCur = pCoeffs; + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + + pSamples = pState; + pOutput = pDst; + + for (int i = 0; i < NB_TAPS; i++) + c[i] = *pCoeffsCur++; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vst1q(pOutput, vecAcc0); + + pOutput += 4; + pSamples += 4; + + blkCnt--; + } + + blkCnt = blockSize & 3; + if (blkCnt) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + FIR_F32_CORE(pSamples, c, NB_TAPS); + + vstrwq_p_f32(pOutput, vecAcc0, p0); + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_f32(pTempDest, vldrwq_z_f32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} +#undef NB_TAPS + +__STATIC_INLINE void arm_fir_f32_5_8_mve(const arm_fir_instance_f32 * S, + const float32_t * __restrict pSrc, + float32_t * __restrict pDst, uint32_t blockSize) +{ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(pDst, vecAcc0); + cnt--; + pDst += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(pDst, vecAcc0,p0); + } + + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + blkCnt = numTaps; + while (blkCnt > 0) + { + *pTempDest++ = *pTempSrc++; + blkCnt--; + } +} + + + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + /* + S->pState is the arm_fir_partial_accu + S->pState + blockSize is the FIR state + */ + float32_t *pRefStatePtr = S->pState + blockSize; + float32_t *pState = pRefStatePtr ; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + const float32_t *pSamples; /* Temporary pointer to the sample buffer */ + float32_t *pOutput; /* Temporary pointer to the output buffer */ + const float32_t *pTempSrc; /* Temporary pointer to the source data */ + float32_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + float32_t c0, c1, c2, c3; + float32_t c4, c5, c6, c7; + + /* + * [1 to 8 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_f32_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_f32_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + + pTempSrc = pSrc; + pTempDest = &(pState[(numTaps - 1u)]); + int cnt = blockSize; + do { + mve_pred16_t p0 = vctp32q(cnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + pTempDest += 4; + pTempSrc += 4; + cnt -= 4; + } while(cnt > 0); + + float32_t *partial_accu_ptr = S->pState; + + pSamples = pState; + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) + { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + int localTaps = numTaps - FIR_F32_MAX_COEF_BLK; + int sample_offset = FIR_F32_MAX_COEF_BLK; + while (localTaps > FIR_F32_MAX_COEF_BLK) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + + partial_accu_ptr = S->pState; + pSamples = pState + sample_offset; + int cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + vecAcc0 += vld1q_f32(partial_accu_ptr); + vst1q(partial_accu_ptr, vecAcc0); + cnt--; + partial_accu_ptr += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + vecAcc0 += vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(partial_accu_ptr, vecAcc0,p0); + } + + localTaps -= FIR_F32_MAX_COEF_BLK; + sample_offset += FIR_F32_MAX_COEF_BLK; + } + + pSamples = pState + sample_offset; + + if (localTaps > 4) { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + c4 = *pCoeffs++; + c5 = *pCoeffs++; + c6 = *pCoeffs++; + c7 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + vecIn0 = vld1q(&pSamples[4]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c4); + vecIn0 = vld1q(&pSamples[5]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c5); + vecIn0 = vld1q(&pSamples[6]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c6); + vecIn0 = vld1q(&pSamples[7]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c7); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + else { + c0 = *pCoeffs++; + c1 = *pCoeffs++; + c2 = *pCoeffs++; + c3 = *pCoeffs++; + pOutput = pDst; + + partial_accu_ptr = S->pState; + cnt = blockSize >> 2; + while(cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + pSamples += 4; + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vst1q(pOutput, vecAcc0+pap); + cnt--; + partial_accu_ptr += 4; + pOutput += 4; + } + + cnt = blockSize & 3; + if (cnt > 0) { + float32x4_t vecAcc0; + float32x4_t vecIn0; + + mve_pred16_t p0 = vctp32q(cnt); + + vecIn0 = vld1q(pSamples); + vecAcc0 = vmulq(vecIn0, c0); + vecIn0 = vld1q(&pSamples[1]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c1); + vecIn0 = vld1q(&pSamples[2]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c2); + vecIn0 = vld1q(&pSamples[3]); + vecAcc0 = vfmaq(vecAcc0, vecIn0, c3); + float32x4_t pap = vld1q_f32(partial_accu_ptr); + vstrwq_p_f32(pOutput, vecAcc0+pap,p0); + pOutput += cnt; + } + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pRefStatePtr[blockSize]; + pTempDest = pRefStatePtr; + + blkCnt = numTaps >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = numTaps & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) + +void arm_fir_f32( +const arm_fir_instance_f32 * S, +const float32_t * pSrc, +float32_t * pDst, +uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointers for state buffer */ + const float32_t *pb; /* Temporary pointers for coefficient buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + float32x4_t accv0,accv1,samples0,samples1,x0,x1,x2,xa,xb,b; + float32_t acc; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop unrolling */ + blkCnt = blockSize >> 3; + + while (blkCnt > 0U) + { + /* Copy 8 samples at a time into state buffers */ + samples0 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples0); + + pStateCurnt += 4; + pSrc += 4 ; + + samples1 = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,samples1); + + pStateCurnt += 4; + pSrc += 4 ; + + /* Set the accumulators to zero */ + accv0 = vdupq_n_f32(0); + accv1 = vdupq_n_f32(0); + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Loop unroling */ + i = numTaps >> 2; + + /* Perform the multiply-accumulates */ + x0 = vld1q_f32(px); + x1 = vld1q_f32(px + 4); + + while(i > 0) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + x2 = vld1q_f32(px + 8); + b = vld1q_f32(pb); + xa = x0; + xb = x1; + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 0)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 0)); + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 1)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 1)); + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 2)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 2)); + + xa = vextq_f32(x0,x1,3); + xb = vextq_f32(x1,x2,3); + + accv0 = vmlaq_n_f32(accv0,xa,vgetq_lane_f32(b, 3)); + accv1 = vmlaq_n_f32(accv1,xb,vgetq_lane_f32(b, 3)); + + pb += 4; + x0 = x1; + x1 = x2; + px += 4; + i--; + + } + + /* Tail */ + i = numTaps & 3; + x2 = vld1q_f32(px + 8); + + /* Perform the multiply-accumulates */ + switch(i) + { + case 3: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + pb++; + + xa = vextq_f32(x0,x1,2); + xb = vextq_f32(x1,x2,2); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 2: + { + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + pb++; + + xa = vextq_f32(x0,x1,1); + xb = vextq_f32(x1,x2,1); + + accv0 = vmlaq_n_f32(accv0,xa,*pb); + accv1 = vmlaq_n_f32(accv1,xb,*pb); + + } + break; + case 1: + { + + accv0 = vmlaq_n_f32(accv0,x0,*pb); + accv1 = vmlaq_n_f32(accv1,x1,*pb); + + } + break; + default: + break; + } + + /* The result is stored in the destination buffer. */ + vst1q_f32(pDst,accv0); + pDst += 4; + vst1q_f32(pDst,accv1); + pDst += 4; + + /* Advance state pointer by 8 for the next 8 samples */ + pState = pState + 8; + + blkCnt--; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc += *px++ * *pb++; + i--; + + } while (i > 0U); + + /* The result is stored in the destination buffer. */ + *pDst++ = acc; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last numTaps - 1 samples to the starting of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Copy numTaps number of values */ + tapCnt = numTaps - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px; /* Temporary pointer for state buffer */ + const float32_t *pb; /* Temporary pointer for coefficient buffer */ + float32_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */ + float32_t x0, x1, x2, x3, x4, x5, x6, x7; /* Temporary variables to hold state values */ + float32_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 8 output values simultaneously. + * The variables acc0 ... acc7 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + acc4 = 0.0f; + acc5 = 0.0f; + acc6 = 0.0f; + acc7 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* This is separated from the others to avoid + * a call to __aeabi_memmove which would be slower + */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Read the first 7 samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + x3 = *px++; + x4 = *px++; + x5 = *px++; + x6 = *px++; + + /* Loop unrolling: process 8 taps at a time. */ + tapCnt = numTaps >> 3U; + + while (tapCnt > 0U) + { + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-3] sample */ + x7 = *(px++); + + /* acc0 += b[numTaps-1] * x[n-numTaps] */ + acc0 += x0 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-1] */ + acc1 += x1 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-2] */ + acc2 += x2 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-3] */ + acc3 += x3 * c0; + + /* acc4 += b[numTaps-1] * x[n-numTaps-4] */ + acc4 += x4 * c0; + + /* acc1 += b[numTaps-1] * x[n-numTaps-5] */ + acc5 += x5 * c0; + + /* acc2 += b[numTaps-1] * x[n-numTaps-6] */ + acc6 += x6 * c0; + + /* acc3 += b[numTaps-1] * x[n-numTaps-7] */ + acc7 += x7 * c0; + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c0; + acc1 += x2 * c0; + acc2 += x3 * c0; + acc3 += x4 * c0; + acc4 += x5 * c0; + acc5 += x6 * c0; + acc6 += x7 * c0; + acc7 += x0 * c0; + + /* Read the b[numTaps-3] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x2 * c0; + acc1 += x3 * c0; + acc2 += x4 * c0; + acc3 += x5 * c0; + acc4 += x6 * c0; + acc5 += x7 * c0; + acc6 += x0 * c0; + acc7 += x1 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x3 * c0; + acc1 += x4 * c0; + acc2 += x5 * c0; + acc3 += x6 * c0; + acc4 += x7 * c0; + acc5 += x0 * c0; + acc6 += x1 * c0; + acc7 += x2 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x3 = *(px++); + /* Perform the multiply-accumulates */ + acc0 += x4 * c0; + acc1 += x5 * c0; + acc2 += x6 * c0; + acc3 += x7 * c0; + acc4 += x0 * c0; + acc5 += x1 * c0; + acc6 += x2 * c0; + acc7 += x3 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x4 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x5 * c0; + acc1 += x6 * c0; + acc2 += x7 * c0; + acc3 += x0 * c0; + acc4 += x1 * c0; + acc5 += x2 * c0; + acc6 += x3 * c0; + acc7 += x4 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x5 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x6 * c0; + acc1 += x7 * c0; + acc2 += x0 * c0; + acc3 += x1 * c0; + acc4 += x2 * c0; + acc5 += x3 * c0; + acc6 += x4 * c0; + acc7 += x5 * c0; + + /* Read the b[numTaps-4] coefficient */ + c0 = *(pb++); + + /* Read x[n-numTaps-6] sample */ + x6 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x7 * c0; + acc1 += x0 * c0; + acc2 += x1 * c0; + acc3 += x2 * c0; + acc4 += x3 * c0; + acc5 += x4 * c0; + acc6 += x5 * c0; + acc7 += x6 * c0; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x8U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x7 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + acc4 += x4 * c0; + acc5 += x5 * c0; + acc6 += x6 * c0; + acc7 += x7 * c0; + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + x3 = x4; + x4 = x5; + x5 = x6; + x6 = x7; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 8 to process the next group of 8 samples */ + pState = pState + 8; + + /* The results in the 8 accumulators, store in the destination buffer. */ + *pDst++ = acc0; + *pDst++ = acc1; + *pDst++ = acc2; + *pDst++ = acc3; + *pDst++ = acc4; + *pDst++ = acc5; + *pDst++ = acc6; + *pDst++ = acc7; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x8U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.0f; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** +* @} end of FIR group +*/ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c new file mode 100644 index 0000000..62e7e99 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f64.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_f64.c + * Description: Floating-point FIR filter processing function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for floating-point FIR filter. + @param[in] S points to an instance of the floating-point FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_f64( + const arm_fir_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + float64_t *pState = S->pState; /* State pointer */ + const float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float64_t *pStateCurnt; /* Points to the current sample of the state */ + float64_t *px; /* Temporary pointer for state buffer */ + const float64_t *pb; /* Temporary pointer for coefficient buffer */ + float64_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0.; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += *px++ * *pb++; + + i--; + } + + /* Store result in destination buffer. */ + *pDst++ = acc0; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** +* @} end of FIR group +*/ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c new file mode 100644 index 0000000..ccd3ed8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c @@ -0,0 +1,332 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q15.c + * Description: Q15 Fast FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter (fast version). + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This fast version uses a 32-bit accumulator with 2.30 format. + The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result. + + @remark + Refer to \ref arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q15() to initialize the filter structure. + */ + +void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLAD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLAD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLAD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLAD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLADX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia ((q15_t **) &pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLAD(x0, c0, acc0); + acc2 = __SMLAD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLADX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLADX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + do + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + while (tapCnt > 0U); + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c new file mode 100644 index 0000000..bc628c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c @@ -0,0 +1,322 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_fast_q31.c + * Description: Processing function for the Q31 Fast FIR filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q31 FIR filter (fast version). + @param[in] S points to an instance of the Q31 structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + This function is optimized for speed at the expense of fixed-point precision and overflow protection. + The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format. + These intermediate results are added to a 2.30 accumulator. + Finally, the accumulator is saturated and converted to a 1.31 result. + The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + + @remark + Refer to \ref arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure. + Use function \ref arm_fir_init_q31() to initialize the filter structure. + */ + +void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + multAcc_32x32_keep32_R(acc0, x0, c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + multAcc_32x32_keep32_R(acc1, x1, c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + multAcc_32x32_keep32_R(acc2, x2, c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x1, c0); + multAcc_32x32_keep32_R(acc1, x2, c0); + multAcc_32x32_keep32_R(acc2, x3, c0); + multAcc_32x32_keep32_R(acc3, x0, c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x2, c0); + multAcc_32x32_keep32_R(acc1, x3, c0); + multAcc_32x32_keep32_R(acc2, x0, c0); + multAcc_32x32_keep32_R(acc3, x1, c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x3, c0); + multAcc_32x32_keep32_R(acc1, x0, c0); + multAcc_32x32_keep32_R(acc2, x1, c0); + multAcc_32x32_keep32_R(acc3, x2, c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + multAcc_32x32_keep32_R(acc0, x0, c0); + multAcc_32x32_keep32_R(acc1, x1, c0); + multAcc_32x32_keep32_R(acc2, x2, c0); + multAcc_32x32_keep32_R(acc3, x3, c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + *pDst++ = (q31_t) (acc1 << 1); + *pDst++ = (q31_t) (acc2 << 1); + *pDst++ = (q31_t) (acc3 << 1); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + multAcc_32x32_keep32_R(acc0, (*px++), (*pb++)); + i--; + } while (i > 0U); + + /* The result is in 2.30 format. Convert to 1.31 + Then store the output in the destination buffer. */ + *pDst++ = (q31_t) (acc0 << 1); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c new file mode 100644 index 0000000..3491343 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f16.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f16.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f16(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 8*ceil(blockSize/8) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/8) + blockSize - 1 + + */ + +void arm_fir_init_f16( + arm_fir_instance_f16 * S, + uint16_t numTaps, + const float16_t * pCoeffs, + float16_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + ROUND_UP(blockSize, 8)) * sizeof(float16_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float16_t)); +#endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c new file mode 100644 index 0000000..e0a5875 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f32.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + blockSize) * sizeof(float32_t)); +#else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); +#endif + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c new file mode 100644 index 0000000..8c578b5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f64.c @@ -0,0 +1,95 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_f64.c + * Description: Floating-point FIR filter initialization function + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] S points to an instance of the floating-point FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed per call + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables and some working memory for the Helium version. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_f32(). + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first blockSize samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 2 * blockSize - 1 + + */ + +void arm_fir_init_f64( + arm_fir_instance_f64 * S, + uint16_t numTaps, + const float64_t * pCoeffs, + float64_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float64_t)); + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c new file mode 100644 index 0000000..3682fb0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c @@ -0,0 +1,145 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q15.c + * Description: Q15 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] pCoeffs points to the filter coefficients buffer. + @param[in] pState points to the state buffer. + @param[in] blockSize number of samples processed per call. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : numTaps is not greater than or equal to 4 and even + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ Note that numTaps must be even and greater than or equal to 4. + To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero. + For example, to implement a filter with numTaps=3 and coefficients + 
+      {0.3, -0.8, 0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.8, 0.3, 0}.
+
+ Similarly, to implement a two point filter + 
+      {0.3, -0.3}
+
+ set numTaps=4 and use the coefficients: + 
+      {0.3, -0.3, 0, 0}.
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3 and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 8 (8a) even if less + then 8a coefficients are defined in the FIR. The additional coefficients + (8a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + */ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + +#if defined (ARM_MATH_DSP) + + /* The Number of filter coefficients in the filter must be even and at least 4 */ + if (numTaps & 0x1U) + { + status = ARM_MATH_ARGUMENT_ERROR; + } + else + { + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear the state buffer. The size is always (blockSize + numTaps ) */ + memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); + +#else + + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + + return (status); + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c new file mode 100644 index 0000000..96d1fdd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q31.c + * Description: Q31 FIR filter initialization function. + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] S points to an instance of the Q31 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples (except for Helium - see below), where blockSize is the number of input samples processed by each call to arm_fir_q31(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 4 (4a) even if less + then 4a coefficients are defined in the FIR. The additional coefficients + (4a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + @par Helium state buffer + The state buffer must contain some additional temporary data + used during the computation but which is not the state of the FIR. + The first 2*4*ceil(blockSize/4) samples are temporary data. + The remaining samples are the state of the FIR filter. + So the state buffer has size numTaps + 8*ceil(blockSize/4) + blockSize - 1 + + */ + +void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + memset(pState, 0, (numTaps + (blockSize - 1U) + 2*ROUND_UP(blockSize, 4)) * sizeof(q31_t)); + #else + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + #endif + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c new file mode 100644 index 0000000..1ad05a5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_init_q7.c + * Description: Q7 FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] S points to an instance of the Q7 FIR filter structure + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficients buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of samples processed + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to the array of state variables. + pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7(). + + @par Initialization of Helium version + For Helium version the array of coefficients must be a multiple of 16 (16a) even if less + then 16a coefficients are defined in the FIR. The additional coefficients + (16a - numTaps) must be set to 0. + numTaps is still set to its right value in the init function. It means that + the implementation may require to read more coefficients due to the vectorization and + to avoid having to manage too many different cases in the code. + + */ + +void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer. The size is always (blockSize + numTaps - 1) */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c new file mode 100644 index 0000000..b6a6ecb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c @@ -0,0 +1,1252 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_f32.c + * Description: Floating-point FIR interpolation sequences + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator + + These functions combine an upsampler (zero stuffer) and an FIR filter. + They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images. + Conceptually, the functions are equivalent to the block diagram below: + \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions" + After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized + cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum. + The user of the function is responsible for providing the filter coefficients. + + The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner. + The upsampler inserts L-1 zeros between each sample. + Instead of multiplying by these zero values, the FIR filter is designed to skip them. + This leads to an efficient implementation without any wasted effort. + The functions operate on blocks of input and output data. + pSrc points to an array of blockSize input values and + pDst points to an array of blockSize*L output values. + + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Algorithm + The functions use a polyphase filter structure: + 
+      y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+      y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+      ...
+      y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+
+ This approach is more efficient than straightforward upsample-then-filter algorithms. + With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter. + @par + pCoeffs points to a coefficient array of size numTaps. + numTaps must be a multiple of the interpolation factor L and this is checked by the + initialization functions. + Internally, the function divides the FIR filter's impulse response into shorter filters of length + phaseLength=numTaps/L. + Coefficients are stored in time reversed order. + 
+      {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size blockSize + phaseLength - 1. + Samples in the state buffer are stored in the order: + 
+     {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + The state variables are updated after each block of data is processed, the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable array should be allocated separately. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + - Checks to make sure that the length of the filter is a multiple of the interpolation factor. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + The code below statically initializes each of the 3 different data type filter instance structures + 
+      arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+      arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+
+ @par + where L is the interpolation factor; phaseLength=numTaps/L is the + length of each of the shorter FIR filters used internally, + pCoeffs is the address of the coefficient buffer; + pState is the address of the state buffer. + Be sure to set the values in the state buffer to zeros when doing static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR interpolate filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for floating-point FIR interpolator. + @param[in] S points to an instance of the floating-point FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_fir_interpolate2_f32_mve( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * 2, 2 * 2, 3 * 2 }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + f32x4_t acc0, acc1; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Initialize state pointer + */ + ptr1 = pState; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs; + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides1); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + ptr2 += 4 * 2; + ptr1 += 4; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides1, p0); + acc1 = vfmaq_f32(acc1, vecState, vecCoef); + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides0, p0); + acc0 = vfmaq_f32(acc0, vecState, vecCoef); + + } + *pDst++ = vecAddAcrossF32Mve(acc1); + *pDst++ = vecAddAcrossF32Mve(acc0); + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + const float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + uint32_t tapCnt; + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32_t stridesM[4] = { 4, 3, 2, 1 }; + uint32x4_t vec_stridesM = vld1q_u32(stridesM); + uint32x4_t vec_strides = vld1q_u32(strides); + f32x4_t acc; + + + if ( S->L == 2 ) { + arm_fir_interpolate2_f32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + */ + /* + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + (phaseLen - 1U); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + float32_t state0, state1, state2, state3; + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U) - 4; + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_f32(pCoef, vec_stridesM); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + + ptr2 = ptr2 + 4 * S->L; + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef; + const float32_t *pCoef = ptr2; + + state0 = ptr1[0]; + state1 = ptr1[1]; + state2 = ptr1[2]; + state3 = ptr1[3]; + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state1); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state2); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(pCoef, vec_stridesM, p0); + pCoef += S->L; + acc = vfmaq_n_f32(acc, vecCoef, state3); + } + + vst1q(pDst, acc); + pDst += 4; + i -= 4; + } + else + { + acc = vdupq_n_f32(0.0f); + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + f32x4_t vecCoef, vecState; + + vecState = vldrwq_f32(ptr1); + ptr1 += 4; + + vecCoef = vldrwq_gather_shifted_offset_f32(ptr2, vec_strides); + ptr2 += 4 * S->L; + acc = vfmaq_f32(acc, vecState, vecCoef); + /* + * Decrement the loop counter + */ + tapCnt--; + } + + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + f32x4_t vecCoef, vecState; + + vecState = vldrwq_z_f32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_f32(ptr2, vec_strides, p0); + acc = vfmaq_f32(acc, vecState, vecCoef); + } + *pDst++ = vecAddAcrossF32Mve(acc); + /* + * Decrement the loop counter + */ + i--; + } + } + + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_f32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_f32(pStateCurnt, vldrwq_f32(pState), p0); + } +} + +#else +#if defined(ARM_MATH_NEON) +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointers for state buffer */ + const float32_t *ptr2; /* Temporary pointers for coefficient buffer */ + float32_t sum0; /* Accumulators */ + float32_t c0; /* Temporary variables to hold state and coefficient values */ + uint32_t i, blkCnt, j; /* Loop counters */ + uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */ + uint32_t blkCntN4; + float32_t c1, c2, c3; + + float32x4_t sum0v; + float32x4_t accV0,accV1; + float32x4_t x0v,x1v,x2v,xa,xb; + float32x2_t tempV; + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = S->pState + (phaseLen - 1U); + + /* Initialise blkCnt */ + blkCnt = blockSize >> 3; + blkCntN4 = blockSize & 7; + + /* Loop unrolling */ + while (blkCnt > 0U) + { + /* Copy new input samples into the state buffer */ + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + sum0v = vld1q_f32(pSrc); + vst1q_f32(pStateCurnt,sum0v); + pSrc += 4; + pStateCurnt += 4; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + accV0 = vdupq_n_f32(0.0); + accV1 = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0v = vld1q_f32(ptr1); + x1v = vld1q_f32(ptr1 + 4); + + while (tapCnt > 0U) + { + /* Read the input samples */ + x2v = vld1q_f32(ptr1 + 8); + + /* Read the coefficients */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c1 = *(ptr2 + S->L); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c1); + accV1 = vmlaq_n_f32(accV1,xb,c1); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c2 = *(ptr2 + S->L * 2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c2); + accV1 = vmlaq_n_f32(accV1,xb,c2); + + /* Read the coefficients, inputs and perform multiply-accumulate */ + c3 = *(ptr2 + S->L * 3); + + xa = vextq_f32(x0v,x1v,3); + xb = vextq_f32(x1v,x2v,3); + + accV0 = vmlaq_n_f32(accV0,xa,c3); + accV1 = vmlaq_n_f32(accV1,xb,c3); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + ptr1 += 4; + x0v = x1v; + x1v = x2v; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + x2v = vld1q_f32(ptr1 + 8); + + switch (tapCnt) + { + case 3: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,2); + xb = vextq_f32(x1v,x2v,2); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 2: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + c0 = *(ptr2); + + xa = vextq_f32(x0v,x1v,1); + xb = vextq_f32(x1v,x2v,1); + + accV0 = vmlaq_n_f32(accV0,xa,c0); + accV1 = vmlaq_n_f32(accV1,xb,c0); + ptr2 += S->L; + + break; + + case 1: + c0 = *(ptr2); + accV0 = vmlaq_n_f32(accV0,x0v,c0); + accV1 = vmlaq_n_f32(accV1,x1v,c0); + ptr2 += S->L; + + break; + + default: + break; + + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst = vgetq_lane_f32(accV0, 0); + *(pDst + S->L) = vgetq_lane_f32(accV0, 1); + *(pDst + 2 * S->L) = vgetq_lane_f32(accV0, 2); + *(pDst + 3 * S->L) = vgetq_lane_f32(accV0, 3); + + *(pDst + 4 * S->L) = vgetq_lane_f32(accV1, 0); + *(pDst + 5 * S->L) = vgetq_lane_f32(accV1, 1); + *(pDst + 6 * S->L) = vgetq_lane_f32(accV1, 2); + *(pDst + 7 * S->L) = vgetq_lane_f32(accV1, 3); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 8; + + pDst += S->L * 7; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + + while (blkCntN4 > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0v = vdupq_n_f32(0.0); + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + ** Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,0); + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the input sample */ + x0v = vld1q_f32(ptr1); + ptr1 += 4; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,1); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Read the coefficient */ + x1v = vsetq_lane_f32(*(ptr2),x1v,3); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0v = vmlaq_f32(sum0v,x0v,x1v); + + /* Decrement the loop counter */ + tapCnt--; + } + + tempV = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v)); + sum0 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *(ptr1++) * (*ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCntN4--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + + tapCnt = (phaseLen - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + sum0v = vld1q_f32(pState); + vst1q_f32(pStateCurnt,sum0v); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + tapCnt = (phaseLen - 1U) % 0x04U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t acc0, acc1, acc2, acc3; + float32_t x0, x1, x2, x3; + float32_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0.0f; + acc1 = 0.0f; + acc2 = 0.0f; + acc3 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x1 * c1; + acc1 += x2 * c1; + acc2 += x3 * c1; + acc3 += x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x2 * c2; + acc1 += x3 * c2; + acc2 += x0 * c2; + acc3 += x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += x3 * c3; + acc1 += x0 * c3; + acc2 += x1 * c3; + acc3 += x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += x0 * c0; + acc1 += x1 * c0; + acc2 += x2 * c0; + acc3 += x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = acc0; + *(pDst + S->L) = acc1; + *(pDst + 2 * S->L) = acc2; + *(pDst + 3 * S->L) = acc3; + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCur; /* Points to the current sample of the state */ + float32_t *ptr1; /* Temporary pointer for state buffer */ + const float32_t *ptr2; /* Temporary pointer for coefficient buffer */ + float32_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0.0f; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += *ptr1++ * *ptr2; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = sum0; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c new file mode 100644 index 0000000..67bdff9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_f32.c + * Description: Floating-point FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] S points to an instance of the floating-point FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ @par + The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32(). + */ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c new file mode 100644 index 0000000..7436aa4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c @@ -0,0 +1,106 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q15.c + * Description: Q15 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] S points to an instance of the Q15 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15(). + */ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c new file mode 100644 index 0000000..15f9e0d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c @@ -0,0 +1,105 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_init_q31.c + * Description: Q31 FIR interpolator initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] S points to an instance of the Q31 FIR interpolator structure + @param[in] L upsample factor + @param[in] numTaps number of filter coefficients in the filter + @param[in] pCoeffs points to the filter coefficient buffer + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+      {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L. + @par + pState points to the array of state variables. + pState is of length (numTaps/L)+blockSize-1 words + where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31(). + */ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + arm_status status; + + /* The filter length must be a multiple of the interpolation factor */ + if ((numTaps % L) != 0U) + { + /* Set status as ARM_MATH_LENGTH_ERROR */ + status = ARM_MATH_LENGTH_ERROR; + } + else + { + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign Interpolation factor */ + S->L = L; + + /* Assign polyPhaseLength */ + S->phaseLength = numTaps / L; + + /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */ + memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + status = ARM_MATH_SUCCESS; + } + + return (status); +} + +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c new file mode 100644 index 0000000..523e155 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c @@ -0,0 +1,774 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q15.c + * Description: Q15 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] S points to an instance of the Q15 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + const q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint16_t strides[8] = { + 0, 1 * S->L, 2 * S->L, 3 * S->L, + 4 * S->L, 5 * S->L, 6 * S->L, 7 * S->L + }; + uint16x8_t vec_strides0 = *(uint16x8_t *) strides; + uint16x8_t vec_strides1 = vec_strides0 + 1; + uint16x8_t vec_strides2 = vec_strides0 + 2; + uint16x8_t vec_strides3 = vec_strides0 + 3; + q15x8_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q15_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides3); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides3, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc3 = vmlaldavaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + *pDst++ = (q15_t) __SSAT(acc2, 16); + *pDst++ = (q15_t) __SSAT(acc3, 16); + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides2); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides2, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc2 = vmlaldavaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16);; + *pDst++ = (q15_t) __SSAT(acc1, 16);; + *pDst++ = (q15_t) __SSAT(acc2, 16);; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides1); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides1, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc1 = vmlaldavaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + *pDst++ = (q15_t) __SSAT(acc0, 16); + *pDst++ = (q15_t) __SSAT(acc1, 16); + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 3; + while (tapCnt > 0U) + { + vecState = vldrhq_s16(ptr1); + vecCoef = vldrhq_gather_shifted_offset_s16(ptr2, vec_strides0); + + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + + ptr1 += 8; + ptr2 = ptr2 + S->L * 8; + tapCnt--; + } + tapCnt = phaseLen & 7; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp16q(tapCnt); + + vecState = vldrhq_z_s16(ptr1, p0); + vecCoef = vldrhq_gather_shifted_offset_z_s16(ptr2, vec_strides0, p0); + acc0 = vmlaldavaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 15); + *pDst++ = (q15_t) __SSAT(acc0, 16); + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pStateCurnt, vldrhq_s16(pState)); + pState += 8; + pStateCurnt += 8; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pStateCurnt, vldrhq_s16(pState), p0); + } +} +#else +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q15_t x0, x1, x2, x3; + q15_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16)); + *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16)); + *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16)); + *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16)); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + q15_t *ptr1; /* Temporary pointer for state buffer */ + const q15_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result after converting to 1.15 format in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16)); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI)*/ +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c new file mode 100644 index 0000000..ea21760 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c @@ -0,0 +1,773 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_interpolate_q31.c + * Description: Q31 FIR interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Interpolate + @{ + */ + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] S points to an instance of the Q31 FIR interpolator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L). + since numTaps/L additions occur per output sample. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + const q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */ + + uint32_t i, blkCnt; /* Loop counters */ + uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t strides[4] = { 0, 1 * S->L, 2 * S->L, 3 * S->L }; + uint32x4_t vec_strides0 = vld1q_u32(strides); + uint32x4_t vec_strides1 = vec_strides0 + 1; + uint32x4_t vec_strides2 = vec_strides0 + 2; + uint32x4_t vec_strides3 = vec_strides0 + 3; + q31x4_t vecState, vecCoef; + + /* + * S->pState buffer contains previous frame (phaseLen - 1) samples + * pStateCurnt points to the location where the new input data should be written + */ + pStateCurnt = S->pState + ((q31_t) phaseLen - 1); + /* + * Total number of intput samples + */ + blkCnt = blockSize; + /* + * Loop over the blockSize. + */ + while (blkCnt > 0U) + { + /* + * Copy new input sample into the state buffer + */ + *pStateCurnt++ = *pSrc++; + /* + * Loop over the Interpolation factor. + */ + i = S->L; + while (i > 0U) + { + /* + * Initialize state pointer + */ + ptr1 = pState; + if (i >= 4) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1 - 3U); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + q63_t acc3 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides3); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides3, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc3 = vrmlaldavhaq(acc3, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + acc3 = asrl(acc3, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + *pDst++ = (q31_t) acc3; + i -= 4; + } + else if (i >= 3) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 2); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + q63_t acc2 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides2); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides2, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc2 = vrmlaldavhaq(acc2, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + acc2 = asrl(acc2, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + *pDst++ = (q31_t) acc2; + i -= 3; + } + else if (i >= 2) + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U - 1); + + q63_t acc0 = 0LL; + q63_t acc1 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides1); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides1, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc1 = vrmlaldavhaq(acc1, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + acc1 = asrl(acc1, 31 - 8); + + *pDst++ = (q31_t) acc0; + *pDst++ = (q31_t) acc1; + i -= 2; + } + else + { + /* + * Initialize coefficient pointer + */ + ptr2 = pCoeffs + (i - 1U); + + q63_t acc0 = 0LL; + + uint32_t tapCnt = phaseLen >> 2; + while (tapCnt > 0U) + { + vecState = vldrwq_s32(ptr1); + vecCoef = vldrwq_gather_shifted_offset_s32(ptr2, vec_strides0); + + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + + ptr1 += 4; + ptr2 = ptr2 + S->L * 4; + tapCnt--; + } + tapCnt = phaseLen & 3; + if (tapCnt > 0U) + { + mve_pred16_t p0 = vctp32q(tapCnt); + + vecState = vldrwq_z_s32(ptr1, p0); + vecCoef = vldrwq_gather_shifted_offset_z_s32(ptr2, vec_strides0, p0); + acc0 = vrmlaldavhaq(acc0, vecState, vecCoef); + } + + acc0 = asrl(acc0, 31 - 8); + *pDst++ = (q31_t) acc0; + /* + * Decrement the loop counter + */ + i--; + } + } + /* + * Advance the state pointer by 1 + * * to process the next group of interpolation factor number samples + */ + pState = pState + 1; + /* + * Decrement the loop counter + */ + blkCnt--; + } + + /* + * Processing is complete. + * ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + * ** This prepares the state buffer for the next function call. + */ + + /* + * Points to the start of the state buffer + */ + pStateCurnt = S->pState; + blkCnt = (phaseLen - 1U) >> 2; + while (blkCnt > 0U) + { + vst1q(pStateCurnt, vldrwq_s32(pState)); + pState += 4; + pStateCurnt += 4; + blkCnt--; + } + blkCnt = (phaseLen - 1U) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pStateCurnt, vldrwq_s32(pState), p0); + } +} +#else +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + uint32_t j; + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc0, acc1, acc2, acc3; + q31_t x0, x1, x2, x3; + q31_t c0, c1, c2, c3; +#endif + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = (S->L); + + while (i > 0U) + { + /* Set accumulator to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. Unroll by a factor of 4. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + tapCnt = phaseLen >> 2U; + + x0 = *(ptr1++); + x1 = *(ptr1++); + x2 = *(ptr1++); + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Read the coefficient */ + c1 = *(ptr2 + S->L); + + /* Read the input sample */ + x0 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x1 * c1; + acc1 += (q63_t) x2 * c1; + acc2 += (q63_t) x3 * c1; + acc3 += (q63_t) x0 * c1; + + /* Read the coefficient */ + c2 = *(ptr2 + S->L * 2); + + /* Read the input sample */ + x1 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x2 * c2; + acc1 += (q63_t) x3 * c2; + acc2 += (q63_t) x0 * c2; + acc3 += (q63_t) x1 * c2; + + /* Read the coefficient */ + c3 = *(ptr2 + S->L * 3); + + /* Read the input sample */ + x2 = *(ptr1++); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x3 * c3; + acc1 += (q63_t) x0 * c3; + acc2 += (q63_t) x1 * c3; + acc3 += (q63_t) x2 * c3; + + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += 4 * S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = phaseLen % 0x4U; + + while (tapCnt > 0U) + { + /* Read the input sample */ + x3 = *(ptr1++); + + /* Read the coefficient */ + c0 = *(ptr2); + + /* Perform the multiply-accumulate */ + acc0 += (q63_t) x0 * c0; + acc1 += (q63_t) x1 * c0; + acc2 += (q63_t) x2 * c0; + acc3 += (q63_t) x3 * c0; + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* update states for next sample processing */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *(pDst ) = (q31_t) (acc0 >> 31); + *(pDst + S->L) = (q31_t) (acc1 >> 31); + *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31); + *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31); + + pDst++; + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 4; + + pDst += S->L * 3; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Address modifier index of coefficient buffer */ + j = 1U; + + /* Loop over the Interpolation factor. */ + i = S->L; + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (S->L - j); + + /* Loop over the polyPhase length. + Repeat until we've computed numTaps-(4*S->L) coefficients. */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = phaseLen >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + sum0 += (q63_t) *ptr1++ * *ptr2; + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = phaseLen % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = phaseLen; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += (q63_t) *ptr1++ * *ptr2; + + /* Upsampling is done by stuffing L-1 zeros between each sample. + * So instead of multiplying zeros with coefficients, + * Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Increment the address modifier index of coefficient buffer */ + j++; + + /* Decrement the loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last phaseLen - 1 samples to the satrt of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + tapCnt = (phaseLen - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = (phaseLen - 1U) % 0x04U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (phaseLen - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + q31_t *ptr1; /* Temporary pointer for state buffer */ + const q31_t *ptr2; /* Temporary pointer for coefficient buffer */ + q63_t sum0; /* Accumulators */ + uint32_t i, blkCnt, tapCnt; /* Loop counters */ + uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */ + + /* S->pState buffer contains previous frame (phaseLen - 1) samples */ + /* pStateCur points to the location where the new input data should be written */ + pStateCur = S->pState + (phaseLen - 1U); + + /* Total number of intput samples */ + blkCnt = blockSize; + + /* Loop over the blockSize. */ + while (blkCnt > 0U) + { + /* Copy new input sample into the state buffer */ + *pStateCur++ = *pSrc++; + + /* Loop over the Interpolation factor. */ + i = S->L; + + while (i > 0U) + { + /* Set accumulator to zero */ + sum0 = 0; + + /* Initialize state pointer */ + ptr1 = pState; + + /* Initialize coefficient pointer */ + ptr2 = pCoeffs + (i - 1U); + + /* Loop over the polyPhase length */ + tapCnt = phaseLen; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum0 += ((q63_t) *ptr1++ * *ptr2); + + /* Increment the coefficient pointer by interpolation factor times. */ + ptr2 += S->L; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result is in the accumulator, store in the destination buffer. */ + *pDst++ = (q31_t) (sum0 >> 31); + + /* Decrement loop counter */ + i--; + } + + /* Advance the state pointer by 1 + * to process the next group of interpolation factor number samples */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + ** Now copy the last phaseLen - 1 samples to the start of the state buffer. + ** This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCur = S->pState; + + tapCnt = phaseLen - 1U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of FIR_Interpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c new file mode 100644 index 0000000..77ea75c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c @@ -0,0 +1,453 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_f32.c + * Description: Processing function for floating-point FIR Lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters + + This set of functions implements Finite Impulse Response (FIR) lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure is feedforward and + the net impulse response is finite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html FIRLattice.gif "Finite Impulse Response Lattice filter" + The following difference equation is implemented: + @par + 
+      f0[n] = g0[n] = x[n]
+      fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+      gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+      y[n] = fM[n]
+
+ @par + pCoeffs points to tha array of reflection coefficients of size numStages. + Reflection Coefficients are stored in the following order. + @par + 
+      {k1, k2, ..., kM}
+
+ where M is number of stages + @par + pState points to a state array of size numStages. + The state variables (g values) hold previous inputs and are stored in the following order. + 
+    {g0[n], g1[n], g2[n] ...gM-1[n]}
+
+ The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+      arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+
+ @par + where numStages is the number of stages in the filter; + pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the FIR Lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Temporary state pointer */ + const float32_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk)) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (fcurr0 * (*pk)) + fcurr1; + gnext1 = (fcurr1 * (*pk)) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (fcurr1 * (*pk)) + fcurr2; + gnext2 = (fcurr2 * (*pk)) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (fcurr2 * (*pk )) + fcurr3; + gnext3 = (fcurr3 * (*pk++)) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g2(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g3(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (gnext0 * (*pk)) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (gnext1 * (*pk)) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (gcurr0 * (*pk)) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (gnext0 * (*pk)) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (gnext1 * (*pk)) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (gnext2 * (*pk)) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (fnext3 * (*pk)) + gnext2; + + gnext2 = (fnext2 * (*pk)) + gnext1; + + gnext1 = (fnext1 * (*pk)) + gnext0; + + gnext0 = (fnext0 * (*pk++)) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + fnext1 = (gnext0 * (*pk)) + fcurr1; + + fnext2 = (gnext1 * (*pk)) + fcurr2; + + fnext3 = (gnext2 * (*pk)) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (fcurr3 * (*pk)) + gnext2; + + gnext2 = (fcurr2 * (*pk)) + gnext1; + + gnext1 = (fcurr1 * (*pk)) + gnext0; + + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (gcurr0 * (*pk)) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (fcurr0 * (*pk++)) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c new file mode 100644 index 0000000..a3a0c22 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_f32.c + * Description: Floating-point FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] S points to an instance of the floating-point FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c new file mode 100644 index 0000000..3996d48 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q15.c + * Description: Q15 FIR Lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c new file mode 100644 index 0000000..4a91b59 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_init_q31.c + * Description: Q31 FIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] numStages number of filter stages + @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages + @param[in] pState points to the state buffer. The array is of length numStages + @return none + */ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always numStages */ + memset(pState, 0, (numStages) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c new file mode 100644 index 0000000..14b7076 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c @@ -0,0 +1,506 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q15.c + * Description: Q15 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for Q15 FIR lattice filter. + @param[in] S points to an instance of the Q15 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary state pointer */ + const q15_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Process second sample for first tap */ + fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0; + gnext1 = __SSAT(gnext1, 16); + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1; + gnext2 = __SSAT(gnext2, 16); + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2; + gnext3 = __SSAT(gnext3, 16); + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = (q15_t) fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = (q15_t) gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0; + fcurr0 = __SSAT(fcurr0, 16); + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1; + fcurr1 = __SSAT(fcurr1, 16); + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2; + fcurr2 = __SSAT(fcurr2, 16); + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3; + fcurr3 = __SSAT(fcurr3, 16); + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = (q15_t) gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1; + fnext1 = __SSAT(fnext1, 16); + + fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2; + fnext2 = __SSAT(fnext2, 16); + + fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3; + fnext3 = __SSAT(fnext3, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2; + gnext3 = __SSAT(gnext3, 16); + + gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1; + gnext2 = __SSAT(gnext2, 16); + + gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0; + gnext1 = __SSAT(gnext1, 16); + + gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(fcurr1, fcurr0, 16)); + write_q15x2_ia (&pDst, __PKHBT(fcurr3, fcurr2, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save g1(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext, 16); + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* save f0(n) in state buffer */ + *px++ = (q15_t) fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = (q15_t) gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0; + fnext0 = __SSAT(fnext0, 16); + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0; + gnext0 = __SSAT(gnext0, 16); + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = __SSAT(fcurr0, 16); + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c new file mode 100644 index 0000000..3b83551 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c @@ -0,0 +1,505 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_lattice_q31.c + * Description: Q31 FIR lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] S points to an instance of the Q31 FIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits. + */ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Temporary state pointer */ + const q31_t *pk; /* Temporary coefficient pointer */ + uint32_t numStages = S->numStages; /* Number of stages in the filter */ + uint32_t blkCnt, stageCnt; /* Loop counters */ + q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */ + +#if (1) +//#if !defined(ARM_MATH_CM0_FAMILY) + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */ + q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */ + q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */ +#endif + + gcurr0 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Read two samples from input buffer */ + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + fcurr1 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* Read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* Process first sample for first tap */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Process second sample for first tap */ + fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + fcurr0; + + /* Read next two samples from input buffer */ + /* f0(n+2) = x(n+2) */ + fcurr2 = *pSrc++; + fcurr3 = *pSrc++; + + /* Process third sample for first tap */ + fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + fcurr1; + + /* Process fourth sample for first tap */ + fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U); + gnext3 = (gnext3 << 1U) + fcurr2; + + /* Copy only last input sample into the state buffer + which will be used for next samples processing */ + *px++ = fcurr3; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + /* Loop unrolling. Process 4 taps at a time . */ + stageCnt = (numStages - 1U) >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numStages-3 coefficients. */ + + /* Process 2nd, 3rd, 4th and 5th taps ... here */ + while (stageCnt > 0U) + { + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Process first sample for 2nd, 6th .. tap */ + /* Sample processing for K2, K6.... */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 2nd, 6th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 2nd, 6th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 2nd, 6th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K3, K7.... */ + /* Process first sample for 3rd, 7th .. tap */ + /* f3(n) = f2(n) + K3 * g2(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 3rd, 7th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 3rd, 7th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 3rd, 7th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g3(n) = f2(n) * K3 + g2(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g1(n-1), g3(n-1) .... from state */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K4, K8.... */ + /* Process first sample for 4th, 8th .. tap */ + /* f4(n) = f3(n) + K4 * g3(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* Process second sample for 4th, 8th .. tap */ + /* for sample 2 processing */ + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + /* Process third sample for 4th, 8th .. tap */ + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + /* Process fourth sample for 4th, 8th .. tap */ + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g4(n) = f3(n) * K4 + g3(n-1) */ + /* Calculation of state values for next stage */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Read g2(n-1), g4(n-1) .... from state */ + gcurr0 = *px; + + /* save g4(n) in state buffer */ + *px++ = gnext3; + + /* Sample processing for K5, K9.... */ + /* Process first sample for 5th, 9th .. tap */ + /* f5(n) = f4(n) + K5 * g4(n-1) */ + fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fcurr0 = (fcurr0 << 1U) + fnext0; + + /* Process second sample for 5th, 9th .. tap */ + fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fcurr1 = (fcurr1 << 1U) + fnext1; + + /* Process third sample for 5th, 9th .. tap */ + fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fcurr2 = (fcurr2 << 1U) + fnext2; + + /* Process fourth sample for 5th, 9th .. tap */ + fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fcurr3 = (fcurr3 << 1U) + fnext3; + + /* Calculation of state values for next stage */ + /* g5(n) = f4(n) * K5 + g4(n-1) */ + gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + stageCnt--; + } + + /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */ + stageCnt = (numStages - 1U) % 0x4U; + + while (stageCnt > 0U) + { + gcurr0 = *px; + + /* save g value in state buffer */ + *px++ = gnext3; + + /* Process four samples for last three taps here */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U); + fnext1 = (fnext1 << 1U) + fcurr1; + + fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U); + fnext2 = (fnext2 << 1U) + fcurr2; + + fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U); + fnext3 = (fnext3 << 1U) + fcurr3; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U); + gnext3 = (gnext3 << 1U) + gnext2; + + gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U); + gnext2 = (gnext2 << 1U) + gnext1; + + gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U); + gnext1 = (gnext1 << 1U) + gnext0; + + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* Update of f values for next coefficient set processing */ + fcurr0 = fnext0; + fcurr1 = fnext1; + fcurr2 = fnext2; + fcurr3 = fnext3; + + stageCnt--; + } + + /* The results in the 4 accumulators, store in the destination buffer. */ + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + *pDst++ = fcurr1; + *pDst++ = fcurr2; + *pDst++ = fcurr3; + + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save g1(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g2(n) from state buffer */ + gcurr0 = *px; + + /* save g1(n) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#else +/* alternate version for CM0_FAMILY */ + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* f0(n) = x(n) */ + fcurr0 = *pSrc++; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coeff pointer */ + pk = pCoeffs; + + /* read g0(n-1) from state buffer */ + gcurr0 = *px; + + /* for sample 1 processing */ + /* f1(n) = f0(n) + K1 * g0(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext << 1U) + fcurr0; + + /* g1(n) = f0(n) * K1 + g0(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* save f0(n) in state buffer */ + *px++ = fcurr0; + + /* f1(n) is saved in fcurr for next stage processing */ + fcurr0 = fnext0; + + stageCnt = (numStages - 1U); + + /* stage loop */ + while (stageCnt > 0U) + { + /* read g1(n-1) from state buffer */ + gcurr0 = *px; + + /* save g0(n-1) in state buffer */ + *px++ = gnext0; + + /* Sample processing for K2, K3.... */ + /* f2(n) = f1(n) + K2 * g1(n-1) */ + fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U); + fnext0 = (fnext0 << 1U) + fcurr0; + + /* g2(n) = f1(n) * K2 + g1(n-1) */ + gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U); + gnext0 = (gnext0 << 1U) + gcurr0; + + /* f1(n) is saved in fcurr0 for next stage processing */ + fcurr0 = fnext0; + + stageCnt--; + } + + /* y(n) = fN(n) */ + *pDst++ = fcurr0; + + blkCnt--; + } + +#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */ + +} + +/** + @} end of FIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c new file mode 100644 index 0000000..6b7d990 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c @@ -0,0 +1,732 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q15.c + * Description: Q15 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] S points to an instance of the Q15 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + + @remark + Refer to \ref arm_fir_fast_q15() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + + +#define FIR_Q15_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q15_t *pSmp = &pSample[j]; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 8 * i); \ + acc[j] = vmlaldavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc[j], 15); \ + } + +#define FIR_Q15_MAIN_CORE() \ +{ \ + q15_t *pState = S->pState; /* State pointer */ \ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q15_t *pStateCur; /* Points to the current sample of the state */ \ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q15_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ \ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q15x8_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q15x8_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrhq_s16(pCoeffs + 8 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrhq_s32(pStateCur, vldrhq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q15_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q15_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + /* current compiler limitation */ \ + blkCnt = (numTaps - 1) >> 3; \ + while (blkCnt > 0) \ + { \ + vstrhq_s16(pTempDest, vldrhq_s16(pTempSrc)); \ + pTempSrc += 8; \ + pTempDest += 8; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 7; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p = vctp16q(blkCnt); \ + vstrhq_p_s16(pTempDest, vldrhq_z_s16(pTempSrc, p), p); \ + } \ +} + +static void arm_fir_q15_25_32_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_17_24_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q15_9_16_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q15_1_8_mve(const arm_fir_instance_q15 * S, + const q15_t * __restrict pSrc, + q15_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 8) + FIR_Q15_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCur; /* Points to the current sample of the state */ + const q15_t *pSamples; /* Temporary pointer to the sample buffer */ + q15_t *pOutput; /* Temporary pointer to the output buffer */ + const q15_t *pTempSrc; /* Temporary pointer to the source data */ + q15_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q15x8_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 7) / 8; + q63_t acc0, acc1, acc2, acc3; + + +int32_t nbTaps = (numTaps + 7) >> 3; + +switch(nbTaps) { + + case 1: + arm_fir_q15_1_8_mve(S, pSrc, pDst, blockSize); + return; + case 2: + arm_fir_q15_9_16_mve(S, pSrc, pDst, blockSize); + return; + case 3: + arm_fir_q15_17_24_mve(S, pSrc, pDst, blockSize); + return; + case 4: + arm_fir_q15_25_32_mve(S, pSrc, pDst, blockSize); + return; + } + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + blkCnt = blockSize >> 2; + + while (blkCnt > 0U) + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmlaldavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + *(q15x8_t *) pStateCur = *(q15x8_t *) pTempSrc; + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc2 = vmlaldavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + } + break; + + case 2: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc1 = vmlaldavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + } + break; + + case 1: + { + const q15_t *pCoeffsTmp = pCoeffs; + const q15_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 8 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 8; + pTempSrc += 8; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 8 coefs + */ + q15x8_t vecCoeffs = *(q15x8_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmlaldavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 8; + pCoeffsTmp += 8; + /* + * Decrement the taps block loop counter + */ + i--; + } + + *pOutput++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 3; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 8; + pTempDest += 8; + blkCnt--; + } + blkCnt = numTaps & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vstrhq_p_s16(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px; /* Temporary pointer for state buffer */ + const q15_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2, acc3; /* Accumulators */ + q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */ + px = pState; + + /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */ + pb = pCoeffs; + + /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */ + x0 = read_q15x2_ia (&px); + + /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */ + x2 = read_q15x2_ia (&px); + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-(numTaps%4) coefficients. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc0 = __SMLALD(x0, c0, acc0); + + /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */ + acc2 = __SMLALD(x2, c0, acc2); + + /* pack x[n-N-1] and x[n-N-2] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read state x[n-N-4], x[n-N-5] */ + x0 = read_q15x2_ia (&px); + + /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-3] and x[n-N-4] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Read coefficients b[N-2], b[N-3] */ + c0 = read_q15x2_ia (&pb); + + /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */ + acc0 = __SMLALD(x2, c0, acc0); + + /* Read state x[n-N-6], x[n-N-7] with offset */ + x2 = read_q15x2_ia (&px); + + /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */ + acc2 = __SMLALD(x0, c0, acc2); + + /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack x[n-N-5] and x[n-N-6] */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */ + acc3 = __SMLALDX(x1, c0, acc3); + + /* Decrement tap count */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps. + This is always be 2 taps since the filter length is even. */ + if ((numTaps & 0x3U) != 0U) + { + /* Read last two coefficients */ + c0 = read_q15x2_ia (&pb); + + /* Perform the multiply-accumulates */ + acc0 = __SMLALD(x0, c0, acc0); + acc2 = __SMLALD(x2, c0, acc2); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x2, x0, 0); +#else + x1 = __PKHBT(x0, x2, 0); +#endif + + /* Read last state variables */ + x0 = read_q15x2 (px); + + /* Perform the multiply-accumulates */ + acc1 = __SMLALDX(x1, c0, acc1); + + /* pack state variables */ +#ifndef ARM_MATH_BIG_ENDIAN + x1 = __PKHBT(x0, x2, 0); +#else + x1 = __PKHBT(x2, x0, 0); +#endif + + /* Perform the multiply-accumulates */ + acc3 = __SMLALDX(x1, c0, acc3); + } + + /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation. + Then store the 4 outputs in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16)); +#else + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16)); + write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy two samples into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Use SIMD to hold states and coefficients */ + px = pState; + pb = pCoeffs; + + tapCnt = numTaps >> 1U; + + while (tapCnt > 0U) + { + acc0 += (q31_t) *px++ * *pb++; + acc0 += (q31_t) *px++ * *pb++; + + tapCnt--; + } + + + /* The result is in 2.30 format. Convert to 1.15 with saturation. + Then store the output in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16)); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c new file mode 100644 index 0000000..40fe527 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c @@ -0,0 +1,1162 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q31.c + * Description: Q31 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q31 FIR filter. + @param[in] S points to an instance of the Q31 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + + @remark + Refer to \ref arm_fir_fast_q31() for a faster but less precise implementation of this filter. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +#define FIR_Q31_CORE(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + q63_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_CORE_STR_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *arm_fir_partial_accu_ptr++ = acc[j]; \ + } + + +#define FIR_Q31_CORE_LD_PARTIAL(nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q31_t *pSmp = &pSamples[j]; \ + q31x4_t vecIn0; \ + \ + acc[j] = *arm_fir_partial_accu_ptr++; \ + \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 4 * i); \ + acc[j] = vrmlaldavhaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q31_t)asrl(acc[j], 23); \ + } + + +#define FIR_Q31_MAIN_CORE() \ +{ \ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); \ + q31_t *pState = pRefStatePtr; /* State pointer */ \ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q31_t *pStateCur; /* Points to the current sample of the state */ \ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q31_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ \ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + \ + /* \ + * load coefs \ + */ \ + q31x4_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vld1q(pCoeffs + 4 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q31_CORE(4, NBVECTAPS, pSamples, vecCoeffs); \ + \ + pSamples += 4; \ + /* \ + * Decrement the sample block loop counter \ + */ \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + switch (residual) { \ + case 3: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(3, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 2: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(2, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + \ + case 1: \ + { \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q31_CORE(1, NBVECTAPS, pSamples, vecCoeffs); \ + } \ + break; \ + } \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + \ + blkCnt =(numTaps - 1) >> 2; \ + while (blkCnt > 0) \ + { \ + vstrwq_s32(pTempDest, vldrwq_s32(pTempSrc)); \ + pTempSrc += 4; \ + pTempDest += 4; \ + blkCnt--; \ + } \ + blkCnt = (numTaps - 1) & 3; \ + if (blkCnt > 0) \ + { \ + mve_pred16_t p0 = vctp32q(blkCnt); \ + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p0), p0); \ + } \ +} + +static void arm_fir_q31_1_4_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + pOutput = pDst; + + q63_t acc0=0, acc1=0, acc2=0, acc3=0; + /* + * load 4 coefs + */ + q31x4_t vecCoeffs = *(q31x4_t *) pCoeffs; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + const q31_t *pSamplesTmp = pSamples; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + vecIn0 = vld1q(pSamples); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs); + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps-1) >> 2; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps-1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + + + +static void arm_fir_q31_5_8_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 8 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_9_12_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 12 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_13_16_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_17_20_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 20 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_21_24_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 24 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +static void arm_fir_q31_25_28_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 28 + #define NBVECTAPS (NBTAPS / 4) + FIR_Q31_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q31_29_32_mve(const arm_fir_instance_q31 * S, + const q31_t * __restrict pSrc, + q31_t * __restrict pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t blkCnt; + q63_t acc0, acc1, acc2, acc3; + +#define MAX_VECT_BATCH 7 + + /* + * pre-load 28 1st coefs + */ + q31x4_t vecCoeffs0 = vld1q(pCoeffs + 4 * 0); + q31x4_t vecCoeffs1 = vld1q(pCoeffs + 4 * 1); + q31x4_t vecCoeffs2 = vld1q(pCoeffs + 4 * 2); + q31x4_t vecCoeffs3 = vld1q(pCoeffs + 4 * 3); + q31x4_t vecCoeffs4 = vld1q(pCoeffs + 4 * 4); + q31x4_t vecCoeffs5 = vld1q(pCoeffs + 4 * 5); + q31x4_t vecCoeffs6 = vld1q(pCoeffs + 4 * 6); + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pTempSrc = pSrc; + pSamples = pState; + + q63_t *arm_fir_partial_accu_ptr = (q63_t*)S->pState; + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + /* + * Save 4 input samples in the history buffer + */ + vstrwq_s32(pStateCur, vldrwq_s32(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + const q31_t *pSmp; + q31x4_t vecIn0; + + pSmp = &pSamples[0]; + + vecIn0 = vld1q(pSmp); + acc0 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc0; + + pSmp = &pSamples[1]; + + vecIn0 = vld1q(pSmp); + acc1 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc1; + + pSmp = &pSamples[2]; + + vecIn0 = vld1q(pSmp); + acc2 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs6); + *arm_fir_partial_accu_ptr++ = acc2; + + pSmp = &pSamples[3]; + + vecIn0 = vld1q(pSmp); + acc3 = vrmlaldavhq(vecIn0, vecCoeffs0); + vecIn0 = vld1q(pSmp + 4 * 1); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs1); + vecIn0 = vld1q(pSmp + 4 * 2); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs2); + vecIn0 = vld1q(pSmp + 4 * 3); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs3); + vecIn0 = vld1q(pSmp + 4 * 4); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs4); + vecIn0 = vld1q(pSmp + 4 * 5); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs5); + vecIn0 = vld1q(pSmp + 4 * 6); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs6); + + *arm_fir_partial_accu_ptr++ = acc3; + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + + /* reminder */ + + /* load last 4 coef */ + vecCoeffs0 = vld1q(pCoeffs + 4 * MAX_VECT_BATCH); + arm_fir_partial_accu_ptr = (q63_t*)S->pState; + pOutput = pDst; + pSamples = pState + (MAX_VECT_BATCH * 4); + + + blkCnt = blockSize >> 2; + while (blkCnt > 0) { + q31x4_t vecIn0; + + /* reload intermediate MAC */ + acc0 = *arm_fir_partial_accu_ptr++; + acc1 = *arm_fir_partial_accu_ptr++; + acc2 = *arm_fir_partial_accu_ptr++; + acc3 = *arm_fir_partial_accu_ptr++; + + + vecIn0 = vld1q(&pSamples[0]); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs0); + + vecIn0 = vld1q(&pSamples[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs0); + + *pOutput++ = asrl(acc0, 23); + *pOutput++ = asrl(acc1, 23); + *pOutput++ = asrl(acc2, 23); + *pOutput++ = asrl(acc3, 23); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps - 1; + do { + mve_pred16_t p = vctp32q(blkCnt); + + vstrwq_p_s32(pTempDest, vldrwq_z_s32(pTempSrc, p), p); + pTempSrc += 4; + pTempDest += 4; + blkCnt -= 4; + } + while (blkCnt > 0); +} + + + +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pRefStatePtr = S->pState + 2*ROUND_UP(blockSize, 4); + q31_t *pState = pRefStatePtr; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCur; /* Points to the current sample of the state */ + const q31_t *pSamples; /* Temporary pointer to the sample buffer */ + q31_t *pOutput; /* Temporary pointer to the output buffer */ + const q31_t *pTempSrc; /* Temporary pointer to the source data */ + q31_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q31x4_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 3) / 4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecCoeffs; + + + /* + * [1 to 32 taps] specialized routines + */ + if (numTaps <= 4) + { + arm_fir_q31_1_4_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 8) + { + arm_fir_q31_5_8_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 12) + { + arm_fir_q31_9_12_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 16) + { + arm_fir_q31_13_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 20) + { + arm_fir_q31_17_20_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 24) + { + arm_fir_q31_21_24_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 28) + { + arm_fir_q31_25_28_mve(S, pSrc, pDst, blockSize); + return; + } + else if ((numTaps <= 32) && (blockSize >= 32)) + { + arm_fir_q31_29_32_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 4 coefs + */ + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vrmlaldavhaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + /* + * Decrement the taps block loop counter + */ + i--; + } + + /* .54-> .31 conversion and store accumulators */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + *pOutput++ = (q31_t) acc3; + + pSamples += 4; + + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + int32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + *(q31x4_t *) pStateCur = *(q31x4_t *) pTempSrc; + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vrmlaldavhaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + *pOutput++ = (q31_t) acc2; + } + break; + + case 2: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + acc1 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vrmlaldavhaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + *pOutput++ = (q31_t) acc0; + *pOutput++ = (q31_t) acc1; + } + break; + + case 1: + { + const q31_t *pCoeffsTmp = pCoeffs; + const q31_t *pSamplesTmp = pSamples; + + acc0 = 0LL; + + /* + * Save 4 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 4; + pTempSrc += 4; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q31x4_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vrmlaldavhaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 4; + pCoeffsTmp += 4; + i--; + } + + acc0 = asrl(acc0, 23); + + *pOutput++ = (q31_t) acc0; + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = (numTaps - 1U) >> 2; + while (blkCnt > 0) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 4; + pTempDest += 4; + blkCnt--; + } + blkCnt = (numTaps - 1U) & 3; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vstrwq_p_s32(pTempDest, vld1q(pTempSrc), p0); + } +} + +#else +void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px; /* Temporary pointer for state buffer */ + const q31_t *pb; /* Temporary pointer for coefficient buffer */ + q63_t acc0; /* Accumulator */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q63_t acc1, acc2; /* Accumulators */ + q31_t x0, x1, x2; /* Temporary variables to hold state values */ + q31_t c0; /* Temporary variable to hold coefficient value */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + + blkCnt = blockSize / 3; + + while (blkCnt > 0U) + { + /* Copy 3 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 2 samples from the state buffer: x[n-numTaps], x[n-numTaps-1] */ + x0 = *px++; + x1 = *px++; + + /* Loop unrolling: process 3 taps at a time. */ + tapCnt = numTaps / 3; + + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-2] sample */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 1U); + x0 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x1 * c0); + acc1 += ((q63_t) x2 * c0); + acc2 += ((q63_t) x0 * c0); + + /* Read the coefficient and state */ + c0 = *(pb + 2U); + x1 = *(px++); + + /* update coefficient pointer */ + pb += 3U; + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x2 * c0); + acc1 += ((q63_t) x0 * c0); + acc2 += ((q63_t) x1 * c0); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + tapCnt = numTaps % 0x3U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x2 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q63_t) x0 * c0); + acc1 += ((q63_t) x1 * c0); + acc2 += ((q63_t) x2 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Advance the state pointer by 3 to process the next group of 3 samples */ + pState = pState + 3; + + /* The result is in 2.30 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + *pDst++ = (q31_t) (acc1 >> 31U); + *pDst++ = (q31_t) (acc2 >> 31U); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x3U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + do + { + /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */ + acc0 += (q63_t) *px++ * *pb++; + + i--; + } while (i > 0U); + + /* Result is in 2.62 format. Convert to 1.31 and store in destination buffer. */ + *pDst++ = (q31_t) (acc0 >> 31U); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c new file mode 100644 index 0000000..c05fa32 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c @@ -0,0 +1,714 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_q7.c + * Description: Q7 FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR + @{ + */ + +/** + @brief Processing function for Q7 FIR filter. + @param[in] S points to an instance of the Q7 FIR filter structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define FIR_Q7_CORE(pOutput, nbAcc, nbVecTaps, pSample, vecCoeffs) \ + for (int j = 0; j < nbAcc; j++) { \ + const q7_t *pSmp = &pSample[j]; \ + q31_t acc[4]; \ + \ + acc[j] = 0; \ + for (int i = 0; i < nbVecTaps; i++) { \ + vecIn0 = vld1q(pSmp + 16 * i); \ + acc[j] = vmladavaq(acc[j], vecIn0, vecCoeffs[i]); \ + } \ + *pOutput++ = (q7_t) __SSAT((acc[j] >> 7U), 8); \ + } + +#define FIR_Q7_MAIN_CORE() \ +{ \ + q7_t *pState = S->pState; /* State pointer */ \ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ \ + q7_t *pStateCur; /* Points to the current sample of the state */ \ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ \ + q7_t *pOutput; /* Temporary pointer to the output buffer */ \ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ \ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */\ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */\ + int32_t blkCnt; \ + q7x16_t vecIn0; \ + \ + /* \ + * load coefs \ + */ \ + q7x16_t vecCoeffs[NBVECTAPS]; \ + \ + for (int i = 0; i < NBVECTAPS; i++) \ + vecCoeffs[i] = vldrbq_s8(pCoeffs + 16 * i); \ + \ + /* \ + * pState points to state array which contains previous frame (numTaps - 1) samples \ + * pStateCur points to the location where the new input data should be written \ + */ \ + pStateCur = &(pState[(numTaps - 1u)]); \ + pTempSrc = pSrc; \ + pSamples = pState; \ + pOutput = pDst; \ + \ + blkCnt = blockSize >> 2; \ + while (blkCnt > 0) { \ + /* \ + * Save 4 input samples in the history buffer \ + */ \ + vstrbq_s32(pStateCur, vldrbq_s32(pTempSrc)); \ + pStateCur += 4; \ + pTempSrc += 4; \ + \ + FIR_Q7_CORE(pOutput, 4, NBVECTAPS, pSamples, vecCoeffs); \ + pSamples += 4; \ + \ + blkCnt--; \ + } \ + \ + /* tail */ \ + int32_t residual = blockSize & 3; \ + \ + for (int i = 0; i < residual; i++) \ + *pStateCur++ = *pTempSrc++; \ + \ + FIR_Q7_CORE(pOutput, residual, NBVECTAPS, pSamples, vecCoeffs); \ + \ + \ + /* \ + * Copy the samples back into the history buffer start \ + */ \ + pTempSrc = &pState[blockSize]; \ + pTempDest = pState; \ + blkCnt = numTaps - 1; \ + do { \ + mve_pred16_t p = vctp8q(blkCnt); \ + \ + vstrbq_p_s8(pTempDest, vldrbq_z_s8(pTempSrc, p), p); \ + pTempSrc += 16; \ + pTempDest += 16; \ + blkCnt -= 16; \ + } \ + while (blkCnt > 0); \ +} + + +static void arm_fir_q7_49_64_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 64 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_33_48_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 48 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +static void arm_fir_q7_17_32_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 32 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + + +void arm_fir_q7_1_16_mve(const arm_fir_instance_q7 * S, + const q7_t * __restrict pSrc, + q7_t * __restrict pDst, uint32_t blockSize) +{ + #define NBTAPS 16 + #define NBVECTAPS (NBTAPS / 16) + FIR_Q7_MAIN_CORE(); + #undef NBVECTAPS + #undef NBTAPS +} + +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCur; /* Points to the current sample of the state */ + const q7_t *pSamples; /* Temporary pointer to the sample buffer */ + q7_t *pOutput; /* Temporary pointer to the output buffer */ + const q7_t *pTempSrc; /* Temporary pointer to the source data */ + q7_t *pTempDest; /* Temporary pointer to the destination buffer */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t blkCnt; + q7x16_t vecIn0; + uint32_t tapsBlkCnt = (numTaps + 15) / 16; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecCoeffs; + + if (numTaps <= 16) + { + /* + * [1 to 16 taps] specialized routine + */ + arm_fir_q7_1_16_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 32) + { + /* + * [17 to 32 taps] specialized routine + */ + arm_fir_q7_17_32_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 48) + { + /* + * [33 to 48 taps] specialized routine + */ + arm_fir_q7_33_48_mve(S, pSrc, pDst, blockSize); + return; + } + else if (numTaps <= 64) + { + /* + * [49 to 64 taps] specialized routine + */ + arm_fir_q7_49_64_mve(S, pSrc, pDst, blockSize); + return; + } + + /* + * pState points to state array which contains previous frame (numTaps - 1) samples + * pStateCur points to the location where the new input data should be written + */ + pStateCur = &(pState[(numTaps - 1u)]); + pSamples = pState; + pTempSrc = pSrc; + pOutput = pDst; + blkCnt = blockSize >> 2; + + /* + * outer samples loop + */ + while (blkCnt > 0U) + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + /* + * inner coefficients loop + */ + int i = tapsBlkCnt; + while (i > 0) + { + /* + * load 16 coefs + */ + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[1]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[2]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[3]); + acc3 = vmladavaq(acc3, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + /* + * Decrement the taps block loop counter + */ + i--; + } + /* + * Store the 1.7 format filter output in destination buffer + */ + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc3 >> 7U), 8); + + pSamples += 4; + /* + * Decrement the sample block loop counter + */ + blkCnt--; + } + + uint32_t residual = blockSize & 3; + switch (residual) + { + case 3: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + acc2 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[8]); + acc2 = vmladavaq(acc2, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc2 >> 7U), 8); + } + break; + + case 2: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + acc1 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + vecIn0 = vld1q(&pSamplesTmp[4]); + acc1 = vmladavaq(acc1, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + *pOutput++ = (q7_t) __SSAT((acc1 >> 7U), 8); + } + break; + + case 1: + { + const q7_t *pCoeffsTmp = pCoeffs; + const q7_t *pSamplesTmp = pSamples; + + acc0 = 0; + /* + * Save 16 input samples in the history buffer + */ + vst1q(pStateCur, vld1q(pTempSrc)); + pStateCur += 16; + pTempSrc += 16; + + int i = tapsBlkCnt; + while (i > 0) + { + vecCoeffs = *(q7x16_t *) pCoeffsTmp; + + vecIn0 = vld1q(pSamplesTmp); + acc0 = vmladavaq(acc0, vecIn0, vecCoeffs); + + pSamplesTmp += 16; + pCoeffsTmp += 16; + i--; + } + *pOutput++ = (q7_t) __SSAT((acc0 >> 7U), 8); + } + break; + } + + /* + * Copy the samples back into the history buffer start + */ + pTempSrc = &pState[blockSize]; + pTempDest = pState; + + blkCnt = numTaps >> 4; + while (blkCnt > 0U) + { + vst1q(pTempDest, vld1q(pTempSrc)); + pTempSrc += 16; + pTempDest += 16; + blkCnt--; + } + blkCnt = numTaps & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vstrbq_p_s8(pTempDest, vld1q(pTempSrc), p0); + } +} +#else +void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *pStateCurnt; /* Points to the current sample of the state */ + q7_t *px; /* Temporary pointer for state buffer */ + const q7_t *pb; /* Temporary pointer for coefficient buffer */ + q31_t acc0; /* Accumulators */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t i, tapCnt, blkCnt; /* Loop counters */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t acc1, acc2, acc3; /* Accumulators */ + q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */ +#endif + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 output values simultaneously. + * The variables acc0 ... acc3 hold output values that are being computed: + * + * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] + * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1] + * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2] + * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3] + */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Copy 4 new input samples into the state buffer. */ + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + *pStateCurnt++ = *pSrc++; + + /* Set all accumulators to zero */ + acc0 = 0; + acc1 = 0; + acc2 = 0; + acc3 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the first 3 samples from the state buffer: + * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */ + x0 = *px++; + x1 = *px++; + x2 = *px++; + + /* Loop unrolling. Process 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Loop over the number of taps. Unroll by a factor of 4. + Repeat until we've computed numTaps-4 coefficients. */ + while (tapCnt > 0U) + { + /* Read the b[numTaps] coefficient */ + c0 = *pb; + + /* Read x[n-numTaps-3] sample */ + x3 = *px; + + /* acc0 += b[numTaps] * x[n-numTaps] */ + acc0 += ((q15_t) x0 * c0); + + /* acc1 += b[numTaps] * x[n-numTaps-1] */ + acc1 += ((q15_t) x1 * c0); + + /* acc2 += b[numTaps] * x[n-numTaps-2] */ + acc2 += ((q15_t) x2 * c0); + + /* acc3 += b[numTaps] * x[n-numTaps-3] */ + acc3 += ((q15_t) x3 * c0); + + /* Read the b[numTaps-1] coefficient */ + c0 = *(pb + 1U); + + /* Read x[n-numTaps-4] sample */ + x0 = *(px + 1U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x1 * c0); + acc1 += ((q15_t) x2 * c0); + acc2 += ((q15_t) x3 * c0); + acc3 += ((q15_t) x0 * c0); + + /* Read the b[numTaps-2] coefficient */ + c0 = *(pb + 2U); + + /* Read x[n-numTaps-5] sample */ + x1 = *(px + 2U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x2 * c0); + acc1 += ((q15_t) x3 * c0); + acc2 += ((q15_t) x0 * c0); + acc3 += ((q15_t) x1 * c0); + + /* Read the b[numTaps-3] coefficients */ + c0 = *(pb + 3U); + + /* Read x[n-numTaps-6] sample */ + x2 = *(px + 3U); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x3 * c0); + acc1 += ((q15_t) x0 * c0); + acc2 += ((q15_t) x1 * c0); + acc3 += ((q15_t) x2 * c0); + + /* update coefficient pointer */ + pb += 4U; + px += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Read coefficients */ + c0 = *(pb++); + + /* Fetch 1 state variable */ + x3 = *(px++); + + /* Perform the multiply-accumulates */ + acc0 += ((q15_t) x0 * c0); + acc1 += ((q15_t) x1 * c0); + acc2 += ((q15_t) x2 * c0); + acc3 += ((q15_t) x3 * c0); + + /* Reuse the present sample states for next sample */ + x0 = x1; + x1 = x2; + x2 = x3; + + /* Decrement loop counter */ + tapCnt--; + } + + /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31 + Then store the 4 outputs in the destination buffer. */ + acc0 = __SSAT((acc0 >> 7U), 8); + *pDst++ = acc0; + acc1 = __SSAT((acc1 >> 7U), 8); + *pDst++ = acc1; + acc2 = __SSAT((acc2 >> 7U), 8); + *pDst++ = acc2; + acc3 = __SSAT((acc3 >> 7U), 8); + *pDst++ = acc3; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining output samples */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of taps */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Copy one sample at a time into state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Set the accumulator to zero */ + acc0 = 0; + + /* Initialize state pointer */ + px = pState; + + /* Initialize Coefficient pointer */ + pb = pCoeffs; + + i = numTaps; + + /* Perform the multiply-accumulates */ + while (i > 0U) + { + acc0 += (q15_t) * (px++) * (*(pb++)); + i--; + } + + /* The result is in 2.14 format. Convert to 1.7 + Then store the output in the destination buffer. */ + *pDst++ = __SSAT((acc0 >> 7U), 8); + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the state buffer */ + pStateCurnt = S->pState; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time */ + tapCnt = (numTaps - 1U) >> 2U; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of taps */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + /* Copy remaining data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of FIR group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c new file mode 100644 index 0000000..e6f4d78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_f32.c + * Description: Floating-point sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters + + This group of functions implements sparse FIR filters. + Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero. + Sparse filters are used for simulating reflections in communications and audio applications. + + There are separate functions for Q7, Q15, Q31, and floating-point data types. + The functions operate on blocks of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst points to input and output arrays respectively containing blockSize values. + + @par Algorithm + The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients. + This is in addition to the coefficient array b. + The implementation essentially skips the multiplications by zero and leads to an efficient realization. + 
+      y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+
+ @par + \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients" + @par + pCoeffs points to a coefficient array of size numTaps; + pTapDelay points to an array of nonzero indices and is also of size numTaps; + pState points to a state array of size maxDelay + blockSize, where + maxDelay is the largest offset value that is ever used in the pTapDelay array. + Some of the processing functions also require temporary working buffers. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 4 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 4 different data type filter instance structures + 
+      arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+      arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+
+ + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the sparse FIR filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] S points to an instance of the floating-point sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + */ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *px; /* Scratch buffer pointer */ + float32_t *py = pState; /* Temporary pointers for state buffer */ + float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + float32_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + float32_t coeff = *pCoeffs++; /* Read the first coefficient value */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pOut++ += *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c new file mode 100644 index 0000000..dce0d6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_f32.c + * Description: Floating-point sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] S points to an instance of the floating-point sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_f32() function. + */ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c new file mode 100644 index 0000000..6a48743 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q15.c + * Description: Q15 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] S points to an instance of the Q15 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of words processed by arm_fir_sparse_q15() function. + */ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c new file mode 100644 index 0000000..a333f1c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q31.c + * Description: Q31 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] S points to an instance of the Q31 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the number of words processed by arm_fir_sparse_q31() function. + */ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c new file mode 100644 index 0000000..3e2b9c9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_init_q7.c + * Description: Q7 sparse FIR filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] S points to an instance of the Q7 sparse FIR structure + @param[in] numTaps number of nonzero coefficients in the filter + @param[in] pCoeffs points to the array of filter coefficients + @param[in] pState points to the state buffer + @param[in] pTapDelay points to the array of offset times + @param[in] maxDelay maximum offset time supported + @param[in] blockSize number of samples that will be processed per block + @return none + + @par Details + pCoeffs holds the filter coefficients and has length numTaps. + pState holds the filter's state variables and must be of length + maxDelay + blockSize, where maxDelay + is the maximum number of delay line values. + blockSize is the + number of samples processed by the arm_fir_sparse_q7() function. + */ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Assign TapDelay pointer */ + S->pTapDelay = pTapDelay; + + /* Assign MaxDelay */ + S->maxDelay = maxDelay; + + /* reset the stateIndex to 0 */ + S->stateIndex = 0U; + + /* Clear state buffer and size is always maxDelay + blockSize */ + memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c new file mode 100644 index 0000000..6066922 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q15.c + * Description: Q15 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] S points to an instance of the Q15 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process per call + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator. + Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator. + If the accumulator result overflows it will wrap around rather than saturate. + After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *px; /* Temporary pointers for scratch buffer */ + q15_t *py = pState; /* Temporary pointers for state buffer */ + q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q15_t *pOut = pDst; /* Working pointer for output */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q15_t coeff = *pCoeffs++; /* Read the first coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; /* Temporary variables */ +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + *pScratchOut++ += (q31_t) *px++ * coeff; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pScr2++; + in2 = *pScr2++; + +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16)); +#else + write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c new file mode 100644 index 0000000..33c66df --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q31.c + * Description: Q31 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] S points to an instance of the Q31 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The 1.31 x 1.31 multiplications are truncated to 2.30 format. + This leads to loss of precision on the intermediate multiplications and provides only a single guard bit. + If the accumulator result overflows, it wraps around rather than saturate. + In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits. + */ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *px; /* Scratch buffer pointer */ + q31_t *py = pState; /* Temporary pointers for state buffer */ + q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q31_t *pOut; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t coeff = *pCoeffs++; /* Read the first coefficient value */ + q31_t in; + q63_t out; /* Temporary output variable */ + + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, + (int32_t *) pSrc, 1, blockSize); + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiplications and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in destination buffer */ + *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement tap loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1, + (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pOut = pDst; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + out = *pOut; + out += ((q63_t) * px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + out = *pOut; + out += ((q63_t) *px++ * coeff) >> 32; + *pOut++ = (q31_t) (out); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Working output pointer is updated */ + pOut = pDst; + + /* Output is converted into 1.31 format. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + in = *pOut << 1; + *pOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c new file mode 100644 index 0000000..e47d889 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fir_sparse_q7.c + * Description: Q7 sparse FIR filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup FIR_Sparse + @{ + */ + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] S points to an instance of the Q7 sparse FIR structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] pScratchIn points to a temporary buffer of size blockSize + @param[in] pScratchOut points to a temporary buffer of size blockSize + @param[in] blockSize number of input samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result. + The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + The accumulator is then converted to 18.7 format by discarding the low 7 bits. + Finally, the result is truncated to 1.7 format. + */ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize) +{ + q7_t *pState = S->pState; /* State pointer */ + const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q7_t *px; /* Scratch buffer pointer */ + q7_t *py = pState; /* Temporary pointers for state buffer */ + q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */ + q7_t *pOut = pDst; /* Destination pointer */ + int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */ + uint32_t delaySize = S->maxDelay + blockSize; /* state length */ + uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + int32_t readIndex; /* Read index of the state buffer */ + uint32_t tapCnt, blkCnt; /* loop counters */ + q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */ + q31_t in; + q7_t coeff = *pCoeffs++; /* Read the coefficient value */ + +#if defined (ARM_MATH_LOOPUNROLL) + q7_t in1, in2, in3, in4; +#endif + + /* BlockSize of Input samples are copied into the state buffer */ + /* StateIndex points to the starting position to write in the state buffer */ + arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize); + + /* Loop over the number of taps. */ + tapCnt = numTaps; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiplication and store in the scratch buffer */ + *pScratchOut++ = ((q31_t) *px++ * coeff); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Loop over the number of taps. */ + tapCnt = (uint32_t) numTaps - 2U; + + while (tapCnt > 0U) + { + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) * px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Load the coefficient value and + * increment the coefficient buffer for the next set of state values */ + coeff = *pCoeffs++; + + /* Read Index, from where the state buffer should be read, is calculated. */ + readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++; + + /* Wraparound of readIndex */ + if (readIndex < 0) + { + readIndex += (int32_t) delaySize; + } + + /* Decrement loop counter */ + tapCnt--; + } + + /* Compute last tap without the final read of pTapDelay */ + + /* Working pointer for state buffer is updated */ + py = pState; + + /* blockSize samples are read from the state buffer */ + arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, + pb, pb, (int32_t) blockSize, 1, blockSize); + + /* Working pointer for the scratch buffer of state values */ + px = pb; + + /* Working pointer for scratch buffer of output values */ + pScratchOut = pScr2; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Perform Multiply-Accumulate */ + in = *pScratchOut + ((q31_t) *px++ * coeff); + *pScratchOut++ = in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* All the output values are in pScratchOut buffer. + Convert them into 1.15 format, saturate and store in the destination buffer. */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time. */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} + +/** + @} end of FIR_Sparse group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c new file mode 100644 index 0000000..bf0b178 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c @@ -0,0 +1,354 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_f32.c + * Description: Floating-point IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters + + This set of functions implements lattice filters + for Q15, Q31 and floating-point data types. Lattice filters are used in a + variety of adaptive filter applications. The filter structure has feedforward and + feedback components and the net impulse response is infinite length. + The functions operate on blocks + of input and output data and each call to the function processes + blockSize samples through the filter. pSrc and + pDst point to input and output arrays containing blockSize values. + + @par Algorithm + \image html IIRLattice.gif "Infinite Impulse Response Lattice filter" + @par + 
+      fN(n)   = x(n)
+      fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ..., 1
+      gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+      y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+
+ @par + pkCoeffs points to array of reflection coefficients of size numStages. + Reflection Coefficients are stored in time-reversed order. + @par + 
+     {kN, kN-1, ..., k1}
+
+ @par + pvCoeffs points to the array of ladder coefficients of size (numStages+1). + Ladder coefficients are stored in time-reversed order. + 
+      {vN, vN-1, ..., v0}
+
+ @par + pState points to a state array of size numStages + blockSize. + The state variables shown in the figure above (the g values) are stored in the pState array. + The state variables are updated after each block of data is processed; the coefficients are untouched. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter. + Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero. + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros and then manually initialize the instance structure as follows: + 
+      arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+      arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+
+ @par + where numStages is the number of stages in the filter; pState points to the state buffer array; + pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the IIR lattice filter functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pStateCur; /* State current pointer */ + float32_t acc; /* Accumlator */ + float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */ + float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t gcurr2; /* Temporary variables for lattice stages */ + float32_t k1, k2; + float32_t v1, v2, v3, v4; +#endif + + /* initialise loop count */ + blkCnt = blockSize; + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fnext2 = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0.0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages) >> 2U; + + while (tapCnt > 0U) + { + /* Read gN-1(n-1) from state buffer */ + gcurr1 = *px1; + + /* read reflection coefficient kN */ + k1 = *pk; + + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* read ladder coefficient vN */ + v1 = *pv; + + /* read next reflection coefficient kN-1 */ + k2 = *(pk + 1U); + + /* Read gN-2(n-1) from state buffer */ + gcurr2 = *(px1 + 1U); + + /* read next ladder coefficient vN-1 */ + v2 = *(pv + 1U); + + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read reflection coefficient kN-2 */ + k1 = *(pk + 2U); + + /* write gN(n) into state for next sample processing */ + *px2++ = gnext; + + /* Read gN-3(n-1) from state buffer */ + gcurr1 = *(px1 + 2U); + + /* y(n) += gN(n) * vN */ + acc += (gnext * v1); + + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fnext1 = fnext2 - (k1 * gcurr1); + + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = gcurr2 + (k2 * fnext2); + + /* Read gN-4(n-1) from state buffer */ + gcurr2 = *(px1 + 3U); + + /* y(n) += gN-1(n) * vN-1 */ + acc += (gnext * v2); + + /* read reflection coefficient kN-3 */ + k2 = *(pk + 3U); + + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext2 = fnext1 - (k2 * gcurr2); + + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = gcurr1 + (k1 * fnext1); + + /* read ladder coefficient vN-2 */ + v3 = *(pv + 2U); + + /* y(n) += gN-2(n) * vN-2 */ + acc += (gnext * v3); + + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointer */ + pk += 4U; + + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = (fnext2 * k2) + gcurr2; + + /* read next ladder coefficient vN-3 */ + v4 = *(pv + 3U); + + /* y(n) += gN-4(n) * vN-4 */ + acc += (gnext * v4); + + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* update pointers */ + px1 += 4U; + pv += 4U; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr1 = *px1++; + /* Process sample for last taps */ + fnext1 = fnext2 - ((*pk) * gcurr1); + gnext = (fnext1 * (*pk++)) + gcurr1; + /* Output samples for last taps */ + acc += (gnext * (*pv++)); + *px2++ = gnext; + fnext2 = fnext1; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (fnext2 * (*pv)); + + *px2++ = fnext2; + + /* write out into pDst */ + *pDst++ = acc; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = numStages; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c new file mode 100644 index 0000000..389e1ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_f32.c + * Description: Floating-point IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] S points to an instance of the floating-point IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c new file mode 100644 index 0000000..873c342 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q15.c + * Description: Q15 IIR lattice filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c new file mode 100644 index 0000000..59b26d3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_init_q31.c + * Description: Initialization function for the Q31 IIR lattice filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] numStages number of stages in the filter + @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages + @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1 + @param[in] pState points to state buffer. The array is of length numStages+blockSize + @param[in] blockSize number of samples to process + @return none + */ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numStages = numStages; + + /* Assign reflection coefficient pointer */ + S->pkCoeffs = pkCoeffs; + + /* Assign ladder coefficient pointer */ + S->pvCoeffs = pvCoeffs; + + /* Clear state buffer and size is always blockSize + numStages */ + memset(pState, 0, (numStages + blockSize) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c new file mode 100644 index 0000000..d3cf7f6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q15.c + * Description: Q15 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] S points to an instance of the Q15 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + q15_t out; /* Temporary variable for output */ + +#if defined (ARM_MATH_DSP) && defined (ARM_MATH_LOOPUNROLL) + q15_t gnext1, gnext2; /* Temporary variables for lattice stages */ + q31_t v; /* Temporary variable for ladder coefficient */ +#endif + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-1(n) into state for next sample processing */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-2(n) into state */ + *px2++ = (q15_t) gnext2; + + /* Read vN-1 and vN-2 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-1(n) and gN-2(n) */ + +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */ + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext1 = (q15_t) __SSAT(gnext, 16); + /* write gN-3(n) for the next sample process */ + *px2++ = (q15_t) gnext1; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */ + fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15); + fcurr = __SSAT(fcurr, 16); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr; + gnext2 = (q15_t) __SSAT(gnext, 16); + /* write gN-4(n) for the next sample process */ + *px2++ = (q15_t) gnext2; + + /* Read vN-3 and vN-4 at a time */ + v = read_q15x2_ia (&pv); + + /* Pack gN-3(n) and gN-4(n) */ +#ifndef ARM_MATH_BIG_ENDIAN + gnext = __PKHBT(gnext1, gnext2, 16); +#else + gnext = __PKHBT(gnext2, gnext1, 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc = __SMLALD(gnext, v, acc); + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples for last taps */ + acc += (q31_t) (((q31_t) gnext * (*pv++))); + *px2++ = (q15_t) gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) (((q31_t) fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = fcurr - ((gcurr * (*pk)) >> 15); + fnext = __SSAT(fnext, 16); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = ((fnext * (*pk++)) >> 15) + gcurr; + gnext = __SSAT(gnext, 16); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += (q31_t) ((gnext * (*pv++))); + + /* write gN(n) into state for next sample processing */ + *px2++ = (q15_t) gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += (q31_t) ((fnext * (*pv++))); + + out = (q15_t) __SSAT(acc >> 15, 16); + *px2++ = (q15_t) fnext; + + /* write out into pDst */ + *pDst++ = out; + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c new file mode 100644 index 0000000..6334495 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_iir_lattice_q31.c + * Description: Q31 IIR Lattice filter processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup IIR_Lattice + @{ + */ + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] S points to an instance of the Q31 IIR lattice structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits. + After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format. + */ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pStateCur; /* State current pointer */ + q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */ + q63_t acc; /* Accumlator */ + q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */ + uint32_t numStages = S->numStages; /* Number of stages */ + uint32_t blkCnt, tapCnt; /* Temporary variables for counts */ + + + /* initialise loop count */ + blkCnt = blockSize; + +#if defined (ARM_MATH_DSP) + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + /* Process sample for first tap */ + gcurr = *px1++; + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numStages - 1U) >> 2U; + + while (tapCnt > 0U) + { + /* Process sample for 2nd, 6th ...taps */ + /* Read gN-2(n-1) from state buffer */ + gcurr = *px1++; + /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-1(n) * vN-1 */ + /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-1(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 3nd, 7th ...taps */ + /* Read gN-3(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 3rd, 7th .. taps */ + /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-2(n) * vN-2 */ + /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-2(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 4th, 8th ...taps */ + /* Read gN-4(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 4th, 8th .. taps */ + /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + /* y(n) += gN-3(n) * vN-3 */ + /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */ + acc += ((q63_t) gnext * *pv++); + /* write gN-3(n) into state for next sample processing */ + *px2++ = gnext; + + /* Process sample for 5th, 9th ...taps */ + /* Read gN-5(n-1) from state buffer */ + gcurr = *px1++; + /* Process sample for 5th, 9th .. taps */ + /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */ + fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */ + gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31)); + /* y(n) += gN-4(n) * vN-4 */ + /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-4(n) into state for next sample processing */ + *px2++ = gnext; + + /* Decrement loop counter */ + tapCnt--; + } + + fnext = fcurr; + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numStages - 1U) % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample for last taps */ + fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31)); + gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31)); + + /* Output samples for last taps */ + acc += ((q63_t) gnext * *pv++); + *px2++ = gnext; + fcurr = fnext; + + /* Decrement loop counter */ + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 4 to process the next group of 4 samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + /* Copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numStages >> 2U; + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numStages % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + tapCnt = (numStages - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Sample processing */ + while (blkCnt > 0U) + { + /* Read Sample from input buffer */ + /* fN(n) = x(n) */ + fcurr = *pSrc++; + + /* Initialize Ladder coeff pointer */ + pv = &S->pvCoeffs[0]; + + /* Initialize Reflection coeff pointer */ + pk = &S->pkCoeffs[0]; + + /* Initialize state read pointer */ + px1 = pState; + + /* Initialize state write pointer */ + px2 = pState; + + /* Set accumulator to zero */ + acc = 0; + + tapCnt = numStages; + + while (tapCnt > 0U) + { + gcurr = *px1++; + /* Process sample */ + /* fN-1(n) = fN(n) - kN * gN-1(n-1) */ + fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31)))); + + /* gN(n) = kN * fN-1(n) + gN-1(n-1) */ + gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31)))); + + /* Output samples */ + /* y(n) += gN(n) * vN */ + acc += ((q63_t) gnext * *pv++); + + /* write gN-1(n-1) into state for next sample processing */ + *px2++ = gnext; + + /* Update f values for next coefficient processing */ + fcurr = fnext; + + tapCnt--; + } + + /* y(n) += g0(n) * v0 */ + acc += ((q63_t) fnext * *pv++); + + *px2++ = fnext; + + /* write out into pDst */ + *pDst++ = (q31_t) (acc >> 31U); + + /* Advance the state pointer by 1 to process the next group of samples */ + pState = pState + 1U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. Now copy last S->numStages samples to start of the buffer + for the preperation of next frame process */ + + /* Points to the start of the state buffer */ + pStateCur = &S->pState[0]; + pState = &S->pState[blockSize]; + + tapCnt = numStages; + + /* Copy data */ + while (tapCnt > 0U) + { + *pStateCur++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/** + @} end of IIR_Lattice group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c new file mode 100644 index 0000000..36108c2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f16.c @@ -0,0 +1,276 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f16.c + * Description: f16 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions_f16.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define LANE4567_MASK 0xFF00 + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + static const uint16_t revOffsetArray[8] = {7,6,5,4,3,2,1,0}; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma = 0.0f16; + _Float16 sumb = 0.0f16; + f16x8_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + _Float16 k; + uint32_t blkCnt; + const float16_t *pPhi,*pRevPhi,*pA; + uint16x8_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f16(0.0f16); + vecSumB = vdupq_n_f16(0.0f16); + + pRevPhi = &phi[p-7]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 3; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 8; + + vecPhi = vld1q(pPhi); + pPhi += 8; + + vecRevPhi = vldrhq_gather_shifted_offset_f16(pRevPhi,revOffset); + pRevPhi -= 8; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 8; + blkCnt--; + + } + + suma = vecAddAcrossF16Mve(vecSumA); + sumb = vecAddAcrossF16Mve(vecSumB); + + blkCnt = p & 7; + while(blkCnt > 0) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + + i++; + blkCnt--; + } + + k = ((_Float16)phi[p+1] - suma)/((_Float16)phi[0] - sumb); + + f16x8_t vecRevA,tmp; + static int16_t orgOffsetArray[8]={0,1,2,3,-1,-2,-3,-4}; + static const int16_t offsetIncArray[8]={4,4,4,4,-4,-4,-4,-4}; + + uint16x8_t offset,offsetInc,vecTmp; + + + offset = vld1q_u16((uint16_t*)orgOffsetArray); + vecTmp = vdupq_n_u16(p); + + offset = vaddq_m_u16(offset,offset,vecTmp,LANE4567_MASK); + offsetInc = vld1q_u16((uint16_t*)offsetIncArray); + + nb = p >> 3; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrhq_gather_shifted_offset_f16(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f16x8_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f16(vecRevA,k)); + vstrhq_scatter_shifted_offset_f16(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=4; + + } + + blkCnt = p & 7; + + if (blkCnt) + { + nb = blkCnt >> 1; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = blkCnt & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + } + + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_levinson_durbin_f16(const float16_t *phi, + float16_t *a, + float16_t *err, + int nbCoefs) +{ + _Float16 e; + + a[0] = (_Float16)phi[1] / (_Float16)phi[0]; + + e = (_Float16)phi[0] - (_Float16)phi[1] * (_Float16)a[0]; + for(int p=1; p < nbCoefs; p++) + { + _Float16 suma=0.0f16; + _Float16 sumb=0.0f16; + _Float16 k; + int nb,j; + + for(int i=0; i < p; i++) + { + suma += (_Float16)a[i] * (_Float16)phi[p - i]; + sumb += (_Float16)a[i] * (_Float16)phi[i + 1]; + } + + k = ((_Float16)phi[p+1]-suma)/((_Float16)phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(int i =0;i < nb ; i++) + { + _Float16 x,y; + + x=(_Float16)a[j] - (_Float16)k * (_Float16)a[p-1-j]; + y=(_Float16)a[p-1-j] - (_Float16)k * (_Float16)a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=(_Float16)a[j]- (_Float16)k * (_Float16)a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f16 - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_FLOAT16_SUPPORTED */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of LD group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c new file mode 100644 index 0000000..b244048 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_f32.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_f32.c + * Description: f32 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_f32 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define LANE23_MASK 0xFF00 + +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(int p=1; p < nbCoefs; p++) + { + float32_t suma = 0.0f; + float32_t sumb = 0.0f; + f32x4_t vecA,vecRevPhi,vecPhi,vecSumA, vecSumB; + float32_t k; + uint32_t blkCnt; + const float32_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + vecSumA = vdupq_n_f32(0.0f); + vecSumB = vdupq_n_f32(0.0f); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_f32(pRevPhi,revOffset); + pRevPhi -= 4; + + vecSumA = vfmaq(vecSumA,vecA,vecRevPhi); + vecSumB = vfmaq(vecSumB,vecA,vecPhi); + + i += 4; + blkCnt--; + + } + + suma = vecAddAcrossF32Mve(vecSumA); + sumb = vecAddAcrossF32Mve(vecSumB); + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + + i++; + blkCnt--; + } + + k = (phi[p+1] - suma)/(phi[0] - sumb); + + f32x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + nb = p >> 2; + j=0; + for(int i = 0; i < nb ; i++) + { + + /* + x0=a[j] - k * a[p-1-j]; + x1=a[j+1] - k * a[p-2-j]; + x3=a[p-1-j] - k * a[j]; + x4=a[p-2-j] - k * a[j+1]; + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_f32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (f32x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vmulq_n_f32(vecRevA,k)); + vstrwq_scatter_shifted_offset_f32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + + } + + switch(p & 3) + { + case 3: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + a[j+1] = a[j+1] - k * a[p-1-(j+1)]; + } + break; + + case 2: + { + float32_t x,y; + x = a[j] - k * a[p-1-j]; + y = a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + a[j] = a[j]- k * a[p-1-j]; + break; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} + +#else +void arm_levinson_durbin_f32(const float32_t *phi, + float32_t *a, + float32_t *err, + int nbCoefs) +{ + float32_t e; + int p; + + a[0] = phi[1] / phi[0]; + + e = phi[0] - phi[1] * a[0]; + for(p=1; p < nbCoefs; p++) + { + float32_t suma=0.0f; + float32_t sumb=0.0f; + float32_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += a[i] * phi[p - i]; + sumb += a[i] * phi[i + 1]; + } + + k = (phi[p+1]-suma)/(phi[0] - sumb); + + + nb = p >> 1; + j=0; + for(i =0; i < nb ; i++) + { + float32_t x,y; + + x=a[j] - k * a[p-1-j]; + y=a[p-1-j] - k * a[j]; + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + a[j]=a[j]- k * a[p-1-j]; + } + + a[p] = k; + e = e * (1.0f - k*k); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of LD group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c new file mode 100644 index 0000000..1788d97 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_levinson_durbin_q31.c @@ -0,0 +1,379 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_levinson_durbin_q31.c + * Description: q31 version of Levinson Durbin algorithm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +#define ONE_Q31 0x7FFFFFFFL +#define TWO_Q30 0x7FFFFFFFL + +#define HALF_Q31 0x00008000L +#define ONE_Q15 0x7FFF +#define HALF_Q15 0x3FFF +#define LOWPART_MASK 0x07FFF + +__STATIC_FORCEINLINE q31_t mul32x16(q31_t a, q15_t b) +{ + q31_t r = ((q63_t)a * (q63_t)b) >> 15; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t mul32x32(q31_t a, q31_t b) +{ + //q31_t r = __SSAT(((q63_t)a * b) >> 31,31); + q31_t r = ((q63_t)a * b) >> 31; + + return(r); + +} + +__STATIC_FORCEINLINE q31_t divide(q31_t n, q31_t d) +{ + arm_status status; + int16_t shift; + q15_t inverse; + q31_t r; + // We are computing: + // n / d = n / (h + l) where h and l are the high end and low end part. + // 1 / (h + l) = 1 / h (1 - l / h) + // Our division algorithm has a shift. So it is returning a scaled value sh. + // So we need a << shift to convert 1/ sh to 1/h. + // In below code, we are organizing the computation differently. Instead of computing: + // 1 / h (1 - l / h) + // we are computing + // 1 / h (2 - (l + h) / h) + // 1 / h (2 - d / h) + // Also, we are not computing 1/h in Q15 but in Q14. + // 2 is expressed in Q30. + // So at the end of all computation we need a << 2 + + // Result is in Q14 because of use of HALF_Q15 instead of ONE_Q15. + status=arm_divide_q15(HALF_Q15,d>>16,&inverse,&shift); + (void)status; + + // d is used instead of l + // So we will need to substract to 2 instead of 1. + r = mul32x16(d,inverse); + r = TWO_Q30 - (r << shift); + r = mul32x16(r, inverse); + r = mul32x32(r,n) ; + r = r << (shift + 2); + + return(r); + +} + +/** + @ingroup groupFilters + */ + +/** + @defgroup LD Levinson Durbin Algorithm + + */ + +/** + @addtogroup LD + @{ + */ + +/** + @brief Levinson Durbin + @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1) + @param[out] a autoregressive coefficients + @param[out] err prediction error (variance) + @param[in] nbCoefs number of autoregressive coefficients + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_levinson_durbin_q31 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#define LANE23_MASK 0xFF00 + +#include "arm_helium_utils.h" +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + + static const uint32_t revOffsetArray[4] = {3,2,1,0}; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(int p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31x4_t vecA,vecRevPhi,vecPhi; + q31_t k; + uint32_t blkCnt; + const q31_t *pPhi,*pRevPhi,*pA; + uint32x4_t revOffset; + + + int nb,j,i; + + revOffset = vld1q(revOffsetArray); + + pRevPhi = &phi[p-3]; + pPhi = &phi[1]; + pA = a; + + i = 0; + blkCnt = p >> 2; + while(blkCnt > 0) + { + vecA = vld1q(pA); + pA += 4; + + vecPhi = vld1q(pPhi); + pPhi += 4; + + vecRevPhi = vldrwq_gather_shifted_offset_s32(pRevPhi,revOffset); + pRevPhi -= 4; + + suma = vmlaldavaq(suma,vecA,vecRevPhi); + sumb = vmlaldavaq(sumb,vecA,vecPhi); + + i += 4; + blkCnt--; + } + + + blkCnt = p & 3; + while(blkCnt > 0) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + + i++; + blkCnt--; + } + + suma = asrl(suma, 31); + sumb = asrl(sumb, 31); + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + q31x4_t vecRevA,tmp; + static int32_t orgOffsetArray[4]={0,1,-1,-2}; + static const int32_t offsetIncArray[4]={2,2,-2,-2}; + + uint32x4_t offset,offsetInc,vecTmp; + + + offset = vld1q_u32((uint32_t*)orgOffsetArray); + vecTmp = vdupq_n_u32(p); + + offset = vaddq_m_u32(offset,offset,vecTmp,LANE23_MASK); + offsetInc = vld1q_u32((uint32_t*)offsetIncArray); + + + nb = p >> 2; + j=0; + for(int i =0;i < nb ; i++) + { + /* + q31_t x0,x1,x2,x3; + + //x = a[j] - k * a[p-1-j]; + x0 = a[j] - mul32x32(k,a[p-1-j]); + x1 = a[j+1] - mul32x32(k,a[p-2-j]); + + //y = a[p-1-j] - k * a[j]; + x2 = a[p-1-j] - mul32x32(k , a[j]); + x3 = a[p-2-j] - mul32x32(k , a[j+1]); + + a[j] = x0; + a[j+1] = x1; + a[p-1-j] = x2; + a[p-2-j] = x3; + */ + + uint64_t tmpa,tmpb; + vecA = vldrwq_gather_shifted_offset_s32(a,offset); + + + tmpa = vgetq_lane_u64((uint64x2_t)vecA,0); + tmpb = vgetq_lane_u64((uint64x2_t)vecA,1); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpb,(uint64x2_t)vecRevA,0); + vecRevA = (q31x4_t) vsetq_lane_u64(tmpa,(uint64x2_t)vecRevA,1); + + + tmp = vsubq(vecA,vqdmulhq_n_s32(vecRevA,k)); + vstrwq_scatter_shifted_offset_s32(a, offset, tmp); + + offset = vaddq(offset,offsetInc); + + j+=2; + } + + switch(p & 3) + { + case 3: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + //a[j] = a[j]- k * a[p-1-j]; + a[j+1] = a[j+1] - mul32x32(k,a[p-2-j]); + } + break; + + case 2: + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + } + break; + + case 1: + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + break; + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} + +#else + +void arm_levinson_durbin_q31(const q31_t *phi, + q31_t *a, + q31_t *err, + int nbCoefs) +{ + q31_t e; + int p; + + //a[0] = phi[1] / phi[0]; + a[0] = divide(phi[1], phi[0]); + + + //e = phi[0] - phi[1] * a[0]; + e = phi[0] - mul32x32(phi[1],a[0]); + + for(p=1; p < nbCoefs; p++) + { + q63_t suma=0; + q63_t sumb=0; + q31_t k; + int nb,j,i; + + for(i=0; i < p; i++) + { + suma += ((q63_t)a[i] * phi[p - i]); + sumb += ((q63_t)a[i] * phi[i + 1]); + } + + suma = suma >> 31; + sumb = sumb >> 31; + + + + //k = (phi[p+1]-suma)/(phi[0] - sumb); + k = divide(phi[p+1]-(q31_t)suma,phi[0] - (q31_t)sumb); + + + nb = p >> 1; + j=0; + for(i =0;i < nb ; i++) + { + q31_t x,y; + + //x = a[j] - k * a[p-1-j]; + x = a[j] - mul32x32(k,a[p-1-j]); + + //y = a[p-1-j] - k * a[j]; + y = a[p-1-j] - mul32x32(k , a[j]); + + a[j] = x; + a[p-1-j] = y; + + j++; + } + + nb = p & 1; + if (nb) + { + //a[j] = a[j]- k * a[p-1-j]; + a[j] = a[j] - mul32x32(k,a[p-1-j]); + } + + a[p] = k; + + // e = e * (1 - k*k); + e = mul32x32(e,ONE_Q31 - mul32x32(k,k)); + + + } + *err = e; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of LD group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c new file mode 100644 index 0000000..99cbeb4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c @@ -0,0 +1,533 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_f32.c + * Description: Processing function for the floating-point LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS Least Mean Square (LMS) Filters + + LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions. + LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal. + Adaptive filters are often used in communication systems, equalizers, and noise removal. + The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types. + The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal. + + An LMS filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The LMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The LMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the Least Mean Square filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero. + + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Set the values in the state buffer to zeros before static initialization. + The code below statically initializes each of the 3 different data type filter instance structures + 
+     arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+     arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+     arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer; + pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients. + + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ +#if defined(ARM_MATH_NEON) +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w = 0.0f; /* weight factor */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + e = 0.0f; + d = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for the updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb = *pb + (w * (*px++)); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U) samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + + +} +#else +void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + /* S->pState points to state array which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + w = e * mu; + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c new file mode 100644 index 0000000..cf472af --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c @@ -0,0 +1,81 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_f32.c + * Description: Floating-point LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32(). + */ + +void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps */ + memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c new file mode 100644 index 0000000..31c2bff --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q15.c + * Description: Q15 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of + input samples processed by each call to arm_lms_q15(). + */ + +void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c new file mode 100644 index 0000000..e657a93 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_init_q31.c + * Description: Q31 LMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @param[in] postShift bit shift applied to coefficients + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to + arm_lms_q31(). + */ + +void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Assign postShift value to be applied */ + S->postShift = postShift; +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c new file mode 100644 index 0000000..85f8211 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c @@ -0,0 +1,564 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_f32.c + * Description: Processing function for the floating-point NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @defgroup LMS_NORM Normalized LMS Filters + + This set of functions implements a commonly used adaptive filter. + It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization + factor which increases the adaptation rate of the filter. + The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types. + + A normalized least mean square (NLMS) filter consists of two components as shown below. + The first component is a standard transversal or FIR filter. + The second component is a coefficient update mechanism. + The NLMS filter has two input signals. + The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter. + That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input. + The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input. + This "error signal" tends towards zero as the filter adapts. + The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal. + \image html LMS.gif "Internal structure of the NLMS adaptive filter" + + The functions operate on blocks of data and each call to the function processes + blockSize samples through the filter. + pSrc points to input signal, pRef points to reference signal, + pOut points to output signal and pErr points to error signal. + All arrays contain blockSize values. + + The functions operate on a block-by-block basis. + Internally, the filter coefficients b[n] are updated on a sample-by-sample basis. + The convergence of the LMS filter is slower compared to the normalized LMS algorithm. + + @par Algorithm + The output signal y[n] is computed by a standard FIR filter: + 
+      y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ + @par + The error signal equals the difference between the reference signal d[n] and the filter output: + 
+      e[n] = d[n] - y[n].
+
+ + @par + After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated: + 
+     E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+
+ The filter coefficients b[k] are then updated on a sample-by-sample basis: + 
+      b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence. + @par + In the APIs, pCoeffs points to a coefficient array of size numTaps. + Coefficients are stored in time reversed order. + @par + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par + pState points to a state array of size numTaps + blockSize - 1. + Samples in the state buffer are stored in the order: + @par + 
+     {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par + Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples. + The increased state buffer length allows circular addressing, which is traditionally used in FIR filters, + to be avoided and yields a significant speed improvement. + The state variables are updated after each block of data is processed. + + @par Instance Structure + The coefficients and state variables for a filter are stored together in an instance data structure. + A separate instance structure must be defined for each filter and + coefficient and state arrays cannot be shared among instances. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Zeros out the values in the state buffer. + To do this manually without calling the init function, assign the follow subfields of the instance structure: + numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero. + For Q7, Q15, and Q31 the following fields must also be initialized; + recipTable, postShift + @par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + @par Fixed-Point Behavior + Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter. + The following issues must be considered: + - Scaling of coefficients + - Overflow and saturation + + @par Scaling of Coefficients (fixed point versions) + Filter coefficients are represented as fractional values and + coefficients are restricted to lie in the range [-1 +1). + The fixed-point functions have an additional scaling parameter postShift. + At the output of the filter's accumulator is a shift register which shifts the result by postShift bits. + This essentially scales the filter coefficients by 2^postShift and + allows the filter coefficients to exceed the range [+1 -1). + The value of postShift is set by the user based on the expected gain through the system being modeled. + + @par Overflow and Saturation (fixed point versions) + Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are + described separately as part of the function specific documentation below. + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + */ + +#if defined(ARM_MATH_NEON) +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t sum, e, d; /* accumulator, error, reference data sample */ + float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */ + + float32x4_t tempV, sumV, xV, bV; + float32x2_t tempV2; + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + d = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + sum = 0.0f; + sumV = vdupq_n_f32(0.0); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + sumV = vmlaq_f32(sumV, xV, bV); + + px += 4; + pb += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(tempV2, 0) + vget_lane_f32(tempV2, 1); + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + sum += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* The result in the accumulator, store in the destination buffer. */ + *pOut++ = sum; + + /* Compute and store error */ + d = (float32_t) (*pRef++); + e = d - sum; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coeff pointer */ + pb = (pCoeffs); + + /* Process 4 taps at a time. */ + tapCnt = numTaps >> 2; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + xV = vld1q_f32(px); + bV = vld1q_f32(pb); + px += 4; + bV = vmlaq_n_f32(bV,xV,w); + + vst1q_f32(pb,bV); + pb += 4; + + + /* Decrement the loop counter */ + tapCnt--; + } + + /* If the filter length is not a multiple of 4, compute the remaining filter taps */ + tapCnt = numTaps % 0x4U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement the loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement the loop counter */ + blkCnt--; + } + + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. Now copy the last numTaps - 1 samples to the + satrt of the state buffer. This prepares the state buffer for the + next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* Process 4 taps at a time for (numTaps - 1U)/4 samples copy */ + tapCnt = (numTaps - 1U) >> 2U; + + /* copy data */ + while (tapCnt > 0U) + { + tempV = vld1q_f32(pState); + vst1q_f32(pStateCurnt,tempV); + pState += 4; + pStateCurnt += 4; + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calculate remaining number of copies */ + tapCnt = (numTaps - 1U) % 0x4U; + + /* Copy the remaining q31_t data */ + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement the loop counter */ + tapCnt--; + } + +} +#else +void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize) +{ + float32_t *pState = S->pState; /* State pointer */ + float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + float32_t *pStateCurnt; /* Points to the current sample of the state */ + float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + float32_t mu = S->mu; /* Adaptive factor */ + float32_t acc, e; /* Accumulator, error */ + float32_t w; /* Weight factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + float32_t energy; /* Energy of the input */ + float32_t x0, in; /* Temporary variable to hold input sample and state */ + + /* Initializations of error, difference, Coefficient update */ + e = 0.0f; + w = 0.0f; + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= x0 * x0; + energy += in * in; + + /* Set the accumulator to zero */ + acc = 0.0f; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + acc += (*px++) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (*px++) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = acc; + + /* Compute and store error */ + e = (float32_t) *pRef++ - acc; + *pErr++ = e; + + /* Calculation of Weighting factor for updating filter coefficients */ + /* epsilon value 0.000000119209289f */ + w = (e * mu) / (energy + 0.000000119209289f); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + *pb += w * (*px++); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c new file mode 100644 index 0000000..b0b7ea5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_f32.c + * Description: Floating-point NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] S points to an instance of the floating-point LMS filter structure + @param[in] numTaps number of filter coefficients + @param[in] pCoeffs points to coefficient buffer + @param[in] pState points to state buffer + @param[in] mu step size that controls filter coefficient updates + @param[in] blockSize number of samples to process + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_f32(). + */ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t)); + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialise Energy to zero */ + S->energy = 0.0f; + + /* Initialise x0 to zero */ + S->x0 = 0.0f; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c new file mode 100644 index 0000000..5bbfc42 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q15.c + * Description: Q15 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to the array of state variables and size of array is + numTaps+blockSize-1 samples, where blockSize is the number of input samples processed + by each call to arm_lms_norm_q15(). + */ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q15_t *) armRecipTableQ15; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c new file mode 100644 index 0000000..cc429b0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_init_q31.c + * Description: Q31 NLMS filter initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" +#include "arm_common_tables.h" + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] pCoeffs points to coefficient buffer. + @param[in] pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none + + @par Details + pCoeffs points to the array of filter coefficients stored in time reversed order: + 
+     {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter. + pState points to an array of length numTaps+blockSize-1 samples, + where blockSize is the number of input samples processed by each call to arm_lms_norm_q31(). + */ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift) +{ + /* Assign filter taps */ + S->numTaps = numTaps; + + /* Assign coefficient pointer */ + S->pCoeffs = pCoeffs; + + /* Clear state buffer and size is always blockSize + numTaps - 1 */ + memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t)); + + /* Assign post Shift value applied to coefficients */ + S->postShift = postShift; + + /* Assign state pointer */ + S->pState = pState; + + /* Assign Step size value */ + S->mu = mu; + + /* Initialize reciprocal pointer table */ + S->recipTable = (q31_t *) armRecipTableQ31; + + /* Initialise Energy to zero */ + S->energy = 0; + + /* Initialise x0 to zero */ + S->x0 = 0; +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c new file mode 100644 index 0000000..b07efdd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c @@ -0,0 +1,297 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q15.c + * Description: Processing function for Q15 normalized LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] S points to an instance of the Q15 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both coefficients and state variables are represented in 1.15 format and + multiplications yield a 2.30 result. The 2.30 intermediate results are + accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full + precision of intermediate multiplications is preserved. After all additions + have been performed, the accumulator is truncated to 34.15 format by + discarding low 15 bits. Lastly, the accumulator is saturated to yield a + result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t energy; /* Energy of the input */ + q15_t e = 0, d = 0; /* Error, reference data sample */ + q15_t w = 0, in; /* Weight factor and state */ + q15_t x0; /* Temporary variable to hold input sample */ + q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy -= (((q31_t) x0 * (x0)) >> 15); + energy += (((q31_t) in * (in)) >> 15); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + d = *pRef++; + e = d - (q15_t) acc; + *pErr++ = e; + + /* Calculation of 1/energy */ + postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable); + + /* Calculation of e * mu value */ + errorXmu = (q15_t) (((q31_t) e * mu) >> 15); + + /* Calculation of (e * mu) * (1/energy) value */ + acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift)); + + /* Weighting factor for the normalized version */ + w = (q15_t) __SSAT((q31_t) acc, 16); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT(coef, 16); + + /* Decrement loop counter */ + tapCnt--; + } + + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q15_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c new file mode 100644 index 0000000..6375d8f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c @@ -0,0 +1,311 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_norm_q31.c + * Description: Processing function for the Q31 NLMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS_NORM + @{ + */ + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] S points to an instance of the Q31 normalized LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and the + updation of filter cofficients are saturted. + */ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q63_t energy; /* Energy of the input */ + q31_t e = 0; /* Error data sample */ + q31_t w = 0, in; /* Weight factor and state */ + q31_t x0; /* Temporary variable to hold input sample */ + q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */ + q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + energy = S->energy; + x0 = S->x0; + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Read the sample from input buffer */ + in = *pSrc++; + + /* Update the energy calculation */ + energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32); + energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32); + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Calculates the reciprocal of energy */ + postShift = arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]); + + /* Calculation of product of (e * mu) */ + errorXmu = (q31_t) (((q63_t) e * mu) >> 31); + + /* Weighting factor for the normalized version */ + w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift)); + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) w * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Read the sample from state buffer */ + x0 = *pState; + + /* Advance state pointer by 1 for the next sample */ + pState = pState + 1; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Save energy and x0 values for the next frame */ + S->energy = (q31_t) energy; + S->x0 = x0; + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS_NORM group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c new file mode 100644 index 0000000..76cab03 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c @@ -0,0 +1,262 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q15.c + * Description: Processing function for Q15 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q15 LMS filter. + @param[in] S points to an instance of the Q15 LMS filter structure + @param[in] pSrc points to the block of input data + @param[in] pRef points to the block of reference data + @param[out] pOut points to the block of output data + @param[out] pErr points to the block of error data + @param[in] blockSize number of samples to process + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize) +{ + q15_t *pState = S->pState; /* State pointer */ + q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q15_t *pStateCurnt; /* Points to the current sample of the state */ + q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q15_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q15_t e = 0; /* Error of data sample */ + q15_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coefficient */ + q31_t acc_l, acc_h; /* Temporary input */ + int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */ + int32_t uShift = (32 - lShift); + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */ + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += (q63_t) (((q31_t) (*px++) * (*pb++))); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + /* Apply shift for lower part of acc and upper part of acc */ + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Converting the result to 1.15 format and saturate the output */ + acc = __SSAT(acc, 16U); + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q15_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q15_t) acc; + *pErr++ = (q15_t) e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q15_t) (((q31_t) e * (mu)) >> 15); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15); + *pb++ = (q15_t) __SSAT((coef), 16); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState)); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c new file mode 100644 index 0000000..1ed61f2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_lms_q31.c + * Description: Processing function for the Q31 LMS filter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/filtering_functions.h" + +/** + @ingroup groupFilters + */ + +/** + @addtogroup LMS + @{ + */ + +/** + @brief Processing function for Q31 LMS filter. + @param[in] S points to an instance of the Q31 LMS filter structure. + @param[in] pSrc points to the block of input data. + @param[in] pRef points to the block of reference data. + @param[out] pOut points to the block of output data. + @param[out] pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clips. + In order to avoid overflows completely the input signal must be scaled down by + log2(numTaps) bits. + The reference signal should not be scaled down. + After all multiply-accumulates are performed, the 2.62 accumulator is shifted + and saturated to 1.31 format to yield the final result. + The output signal and error signal are in 1.31 format. + @par + In this filter, filter coefficients are updated for each sample and + the updation of filter cofficients are saturted. + */ + +void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize) +{ + q31_t *pState = S->pState; /* State pointer */ + q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */ + q31_t *pStateCurnt; /* Points to the current sample of the state */ + q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */ + q31_t mu = S->mu; /* Adaptive factor */ + uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */ + uint32_t tapCnt, blkCnt; /* Loop counters */ + q63_t acc; /* Accumulator */ + q31_t e = 0; /* Error of data sample */ + q31_t alpha; /* Intermediate constant for taps update */ + q31_t coef; /* Temporary variable for coef */ + q31_t acc_l, acc_h; /* Temporary input */ + uint32_t uShift = ((uint32_t) S->postShift + 1U); + uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */ + + /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */ + /* pStateCurnt points to the location where the new input data should be written */ + pStateCurnt = &(S->pState[(numTaps - 1U)]); + + /* initialise loop count */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* Copy the new input sample into the state buffer */ + *pStateCurnt++ = *pSrc++; + + /* Initialize pState pointer */ + px = pState; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + + /* Set the accumulator to zero */ + acc = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + /* acc += b[N] * x[n-N] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-1] * x[n-N-1] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-2] * x[n-N-2] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* acc += b[N-3] * x[n-N-3] */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + acc += ((q63_t) (*px++)) * (*pb++); + + /* Decrement the loop counter */ + tapCnt--; + } + + /* Converting the result to 1.31 format */ + /* Calc lower part of acc */ + acc_l = acc & 0xffffffff; + + /* Calc upper part of acc */ + acc_h = (acc >> 32) & 0xffffffff; + + acc = (uint32_t) acc_l >> lShift | acc_h << uShift; + + /* Store the result from accumulator into the destination buffer. */ + *pOut++ = (q31_t) acc; + + /* Compute and store error */ + e = *pRef++ - (q31_t) acc; + *pErr++ = e; + + /* Compute alpha i.e. intermediate constant for taps update */ + alpha = (q31_t) (((q63_t) e * mu) >> 31); + + /* Initialize pState pointer */ + /* Advance state pointer by 1 for the next sample */ + px = pState++; + + /* Initialize coefficient pointer */ + pb = pCoeffs; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = numTaps >> 2U; + + /* Update filter coefficients */ + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + + /* coef is in 2.30 format */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + /* get coef in 1.31 format by left shifting */ + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + /* update coefficient buffer to next coefficient */ + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = numTaps % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = numTaps; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + /* Perform the multiply-accumulate */ + coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32)); + *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U)); + pb++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Processing is complete. + Now copy the last numTaps - 1 samples to the start of the state buffer. + This prepares the state buffer for the next function call. */ + + /* Points to the start of the pState buffer */ + pStateCurnt = S->pState; + + /* copy data */ +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 taps at a time. */ + tapCnt = (numTaps - 1U) >> 2U; + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + + /* Loop unrolling: Compute remaining taps */ + tapCnt = (numTaps - 1U) % 0x4U; + +#else + + /* Initialize tapCnt with number of samples */ + tapCnt = (numTaps - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (tapCnt > 0U) + { + *pStateCurnt++ = *pState++; + + /* Decrement loop counter */ + tapCnt--; + } + +} + +/** + @} end of LMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt new file mode 100644 index 0000000..7ce79cf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/CMakeLists.txt @@ -0,0 +1,34 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPInterpolation) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPInterpolation STATIC) + +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q15.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q31.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_q7.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q15.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q31.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_q7.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_spline_interp_f32.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_spline_interp_init_f32.c) + + +configLib(CMSISDSPInterpolation ${ROOT}) +configDsp(CMSISDSPInterpolation ${ROOT}) + +### Includes +target_include_directories(CMSISDSPInterpolation PUBLIC "${DSP}/Include") + + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPInterpolation PRIVATE arm_bilinear_interp_f16.c) +target_sources(CMSISDSPInterpolation PRIVATE arm_linear_interp_f16.c) +endif() \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c new file mode 100644 index 0000000..8462395 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctions.c @@ -0,0 +1,41 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bilinear_interp_f32.c" +#include "arm_bilinear_interp_q15.c" +#include "arm_bilinear_interp_q31.c" +#include "arm_bilinear_interp_q7.c" +#include "arm_linear_interp_f32.c" +#include "arm_linear_interp_q15.c" +#include "arm_linear_interp_q31.c" +#include "arm_linear_interp_q7.c" +#include "arm_spline_interp_f32.c" +#include "arm_spline_interp_init_f32.c" + + + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c new file mode 100644 index 0000000..d778de9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/InterpolationFunctionsF16.c @@ -0,0 +1,33 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: InterpolationFunctions.c + * Description: Combination of all interpolation function source files. + * + * $Date: 22. July 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bilinear_interp_f16.c" +#include "arm_linear_interp_f16.c" + + + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c new file mode 100644 index 0000000..799ed78 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f16.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f16.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float16_t *pData;
+   * } arm_bilinear_interp_instance_f16;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float16_t arm_bilinear_interp_f16( + const arm_bilinear_interp_instance_f16 * S, + float16_t X, + float16_t Y) + { + float16_t out; + float16_t f00, f01, f10, f11; + float16_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float16_t xdiff, ydiff; + float16_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = (_Float16)f01 - (_Float16)f00; + b3 = (_Float16)f10 - (_Float16)f00; + b4 = (_Float16)f00 - (_Float16)f01 - (_Float16)f10 + (_Float16)f11; + + /* Calculation of fractional part in X */ + xdiff = (_Float16)X - (_Float16)xIndex; + + /* Calculation of fractional part in Y */ + ydiff = (_Float16)Y - (_Float16)yIndex; + + /* Calculation of bi-linear interpolated output */ + out = (_Float16)b1 + (_Float16)b2 * (_Float16)xdiff + + (_Float16)b3 * (_Float16)ydiff + (_Float16)b4 * (_Float16)xdiff * (_Float16)ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c new file mode 100644 index 0000000..fc001d7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_f32.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bilinear_interp_f32.c + * Description: Floating-point bilinear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c new file mode 100644 index 0000000..6726736 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q15.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c new file mode 100644 index 0000000..cc8560e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q31.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c new file mode 100644 index 0000000..204342e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_bilinear_interp_q7.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c new file mode 100644 index 0000000..f4ae1e1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f16.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f16.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float16_t arm_linear_interp_f16( + arm_linear_interp_instance_f16 * S, + float16_t x) + { + float16_t y; + float16_t x0, x1; /* Nearest input values */ + float16_t y0, y1; /* Nearest output values */ + float16_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float16_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) (((_Float16)x - (_Float16)S->x1) / (_Float16)xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = (_Float16)S->x1 + (_Float16)i * (_Float16)xSpacing; + x1 = (_Float16)S->x1 + (_Float16)(i + 1) * (_Float16)xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = (_Float16)y0 + ((_Float16)x - (_Float16)x0) * + (((_Float16)y1 - (_Float16)y0) / ((_Float16)x1 - (_Float16)x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c new file mode 100644 index 0000000..fc60bec --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_f32.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_f32.c + * Description: Floating-point linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * @} end of LinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c new file mode 100644 index 0000000..e6339f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q15.c @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q15.c + * Description: Q15 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q15_t arm_linear_interp_q15( + const q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c new file mode 100644 index 0000000..f0c7560 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q31.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q31.c + * Description: Q31 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + q31_t arm_linear_interp_q31( + const q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + + /** + * @} end of LinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c new file mode 100644 index 0000000..8d15432 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_linear_interp_q7.c @@ -0,0 +1,99 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_linear_interp_q7.c + * Description: Q7 linear interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + + +/** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + q7_t arm_linear_interp_q7( + const q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + /** + * @} end of LinearInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c new file mode 100644 index 0000000..3e3d091 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_f32.c @@ -0,0 +1,283 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_f32.c + * Description: Floating-point cubic spline interpolation + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @defgroup SplineInterpolate Cubic Spline Interpolation + + Spline interpolation is a method of interpolation where the interpolant + is a piecewise-defined polynomial called "spline". + + @par Introduction + + Given a function f defined on the interval [a,b], a set of n nodes x(i) + where a=x(1) + S1(x) x(1) < x < x(2) + S(x) = ... + Sn-1(x) x(n-1) < x < x(n) + + + where + + 
 
+  Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3    i=1, ..., n-1
+
+ + @par Algorithm + + Having defined h(i) = x(i+1) - x(i) + + 
+  h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)]    i=2, ..., n-1
+
+ + It is possible to write the previous conditions in matrix form (Ax=B). + In order to solve the system two boundary conidtions are needed. + - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0 + In matrix form: + + 
+  |  1        0         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0         0           1     ||  c(n)  | |                        0                        |
+
+ + - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n) + In matrix form: + + 
+  |  1       -1         0  ...    0         0           0     ||  c(1)  | |                        0                        |
+  | h(0) 2[h(0)+h(1)] h(1) ...    0         0           0     ||  c(2)  | |      3/h(2)*[a(3)-a(2)]-3/h(1)*[a(2)-a(1)]      |
+  | ...      ...       ... ...   ...       ...         ...    ||  ...   |=|                       ...                       |
+  |  0        0         0  ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-3/h(n-2)*[a(n-1)-a(n-2)] |
+  |  0        0         0  ...    0        -1           1     ||  c(n)  | |                        0                        |
+
+ + A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization + algorithms (A=LU) can be simplified considerably because a large number of zeros appear + in regular patterns. The Crout method has been used: + 1) Solve LZ=B + + 
+  u(1,2) = A(1,2)/A(1,1)
+  z(1)   = B(1)/l(11)
+ 
+  FOR i=2, ..., N-1
+    l(i,i)   = A(i,i)-A(i,i-1)u(i-1,i)
+    u(i,i+1) = a(i,i+1)/l(i,i)
+    z(i)     = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
+  
+  l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
+  z(N)   = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
+
+ + 2) Solve UX=Z + + 
+  c(N)=z(N)
+  
+  FOR i=N-1, ..., 1
+    c(i)=z(i)-u(i,i+1)c(i+1) 
+
+ + c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials. + b(i) and d(i) are computed as: + - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 + - d(i) = [c(i+1)-c(i)]/[3*h(i)] + Moreover, a(i)=y(i). + + @par Behaviour outside the given intervals + + It is possible to compute the interpolated vector for x values outside the + input range (xqx(n)). The coefficients used to compute the y values for + xqx(n) the + coefficients used for the last interval. + + */ + +/** + @addtogroup SplineInterpolate + @{ + */ + +/** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values of the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + +void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize) +{ + const float32_t * x = S->x; + const float32_t * y = S->y; + int32_t n = S->n_x; + + /* Coefficients (a==y for i<=n-1) */ + float32_t * b = (S->coeffs); + float32_t * c = (S->coeffs)+(n-1); + float32_t * d = (S->coeffs)+(2*(n-1)); + + const float32_t * pXq = xq; + int32_t blkCnt = (int32_t)blockSize; + int32_t blkCnt2; + int32_t i; + float32_t x_sc; + +#ifdef ARM_MATH_NEON + float32x4_t xiv; + float32x4_t aiv; + float32x4_t biv; + float32x4_t civ; + float32x4_t div; + + float32x4_t xqv; + + float32x4_t temp; + float32x4_t diff; + float32x4_t yv; +#endif + + /* Create output for x(i) 4 ) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt-=4; + } +#endif + while( *pXq <= x[i+1] && blkCnt > 0 ) + { + x_sc = *pXq++; + + *pDst = y[i]+b[i]*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+d[i]*(x_sc-x[i])*(x_sc-x[i])*(x_sc-x[i]); + + pDst++; + blkCnt--; + } + } + + /* Create output for remaining samples (x>=x(n)) */ +#ifdef ARM_MATH_NEON + /* Compute 4 outputs at a time */ + blkCnt2 = blkCnt >> 2; + + while(blkCnt2 > 0) + { + /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */ + xqv = vld1q_f32(pXq); + pXq+=4; + + /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */ + diff = vsubq_f32(xqv, xiv); + temp = diff; + + /* y(i) = a(i) + ... */ + yv = aiv; + /* ... + b(i)*(x-x(i)) + ... */ + yv = vmlaq_f32(yv, biv, temp); + /* ... + c(i)*(x-x(i))^2 + ... */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, civ, temp); + /* ... + d(i)*(x-x(i))^3 */ + temp = vmulq_f32(temp, diff); + yv = vmlaq_f32(yv, div, temp); + + /* Store [y(k) y(k+1) y(k+2) y(k+3)] */ + vst1q_f32(pDst, yv); + pDst+=4; + + blkCnt2--; + } + + /* Tail */ + blkCnt2 = blkCnt & 3; +#else + blkCnt2 = blkCnt; +#endif + + while(blkCnt2 > 0) + { + x_sc = *pXq++; + + *pDst = y[i-1]+b[i-1]*(x_sc-x[i-1])+c[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])+d[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])*(x_sc-x[i-1]); + + pDst++; + blkCnt2--; + } +} + +/** + @} end of SplineInterpolate group + */ diff --git a/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c new file mode 100644 index 0000000..ae3f2da --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/InterpolationFunctions/arm_spline_interp_init_f32.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_spline_interp_init_f32.c + * Description: Floating-point cubic spline initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/interpolation_functions.h" + +/** + @ingroup groupInterpolation + */ + +/** + @addtogroup SplineInterpolate + @{ + + @par Initialization function + + The initialization function takes as input two arrays that the user has to allocate: + coeffs will contain the b, c, and d coefficients for the (n-1) intervals + (n is the number of known points), hence its size must be 3*(n-1); tempBuffer + is temporally used for internal computations and its size is n+n-1. + + @par + + The x input array must be strictly sorted in ascending order and it must + not contain twice the same value (x(i)x = x; + S->y = y; + S->n_x = n; + + /* == Solve LZ=B to obtain z(i) and u(i) == */ + + /* -- Row 1 -- */ + /* B(0) = 0, not computed */ + /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */ + if(type == ARM_SPLINE_NATURAL) + u[0] = 0; /* a(1,2) = 0 */ + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + u[0] = -1; /* a(1,2) = -1 */ + + z[0] = 0; /* z(1) = B(1)/a(1,1) = 0 always */ + + /* -- Rows 2 to N-1 (N=n+1) -- */ + hm1 = x[1] - x[0]; /* Initialize h(i-1) = h(1) = x(2)-x(1) */ + + for (i=1; i<(int32_t)n-1; i++) + { + /* Compute B(i) */ + hi = x[i+1]-x[i]; + Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1; + + /* l(i) = a(i)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */ + li = 2*(hi+hm1) - hm1*u[i-1]; + + /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */ + u[i] = hi/li; + + /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */ + z[i] = (Bi-hm1*z[i-1])/li; + + /* Update h(i-1) for next iteration */ + hm1 = hi; + } + + /* -- Row N -- */ + /* l(N) = a(N,N)-a(N,N-1)u(N-1) */ + /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */ + if(type == ARM_SPLINE_NATURAL) + { + /* li = 1; a(N,N) = 1; a(N,N-1) = 0 */ + z[n-1] = 0; /* a(N,N-1) = 0 */ + } + else if(type == ARM_SPLINE_PARABOLIC_RUNOUT) + { + li = 1+u[n-2]; /* a(N,N) = 1; a(N,N-1) = -1 */ + z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */ + } + + /* == Solve UX = Z to obtain c(i) and */ + /* compute b(i) and d(i) from c(i) == */ + + cp1 = z[n-1]; /* Initialize c(i+1) = c(N) = z(N) */ + + for (i=n-2; i>=0; i--) + { + /* c(i) = z(i)-u(i+1)c(i+1) */ + c[i] = z[i]-u[i]*cp1; + + hi = x[i+1]-x[i]; + /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */ + b[i] = (y[i+1]-y[i])/hi-hi*(cp1+2*c[i])/3; + + /* d(i) = [c(i+1)-c(i)]/[3*h(i)] */ + d[i] = (cp1-c[i])/(3*hi); + + /* Update c(i+1) for next iteration */ + cp1 = c[i]; + } + + /* == Finally, store the coefficients in the instance == */ + + S->coeffs = coeffs; +} + +/** + @} end of SplineInterpolate group + */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt new file mode 100644 index 0000000..f2b3211 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/CMakeLists.txt @@ -0,0 +1,54 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPMatrix) + +include(configLib) +include(configDsp) + +file(GLOB SRCF64 "./*_f64.c") +file(GLOB SRCF32 "./*_f32.c") +file(GLOB SRCF16 "./*_f16.c") +file(GLOB SRCQ31 "./*_q31.c") +file(GLOB SRCQ15 "./*_q15.c") +file(GLOB SRCQ7 "./*_q7.c") + +file(GLOB SRCU32 "./*_u32.c") +file(GLOB SRCU16 "./*_u16.c") +file(GLOB SRCU8 "./*_u8.c") + +add_library(CMSISDSPMatrix STATIC ${SRCF64}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCF32}) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPMatrix PRIVATE ${SRCF16}) +endif() + +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ31}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ15}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCQ7}) + +target_sources(CMSISDSPMatrix PRIVATE ${SRCU32}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCU16}) +target_sources(CMSISDSPMatrix PRIVATE ${SRCU8}) + +configLib(CMSISDSPMatrix ${ROOT}) +configDsp(CMSISDSPMatrix ${ROOT}) + +### Includes +target_include_directories(CMSISDSPMatrix PUBLIC "${DSP}/Include") + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_add_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_sub_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_trans_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_scale_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_vec_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cmplx_trans_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cmplx_mult_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_inverse_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_init_f16.c) +target_sources(CMSISDSPMatrix PRIVATE arm_mat_cholesky_f16.c) + +endif() diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c new file mode 100644 index 0000000..d4fa42c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_mat_add_f32.c" +#include "arm_mat_add_q15.c" +#include "arm_mat_add_q31.c" +#include "arm_mat_cmplx_mult_f32.c" +#include "arm_mat_cmplx_mult_q15.c" +#include "arm_mat_cmplx_mult_q31.c" +#include "arm_mat_init_f32.c" +#include "arm_mat_init_q15.c" +#include "arm_mat_init_q31.c" +#include "arm_mat_inverse_f32.c" +#include "arm_mat_inverse_f64.c" +#include "arm_mat_mult_f64.c" +#include "arm_mat_mult_f32.c" +#include "arm_mat_mult_fast_q15.c" +#include "arm_mat_mult_fast_q31.c" +#include "arm_mat_mult_q7.c" +#include "arm_mat_mult_q15.c" +#include "arm_mat_mult_q31.c" +#include "arm_mat_mult_opt_q31.c" +#include "arm_mat_scale_f32.c" +#include "arm_mat_scale_q15.c" +#include "arm_mat_scale_q31.c" +#include "arm_mat_sub_f64.c" +#include "arm_mat_sub_f32.c" +#include "arm_mat_sub_q15.c" +#include "arm_mat_sub_q31.c" +#include "arm_mat_trans_f32.c" +#include "arm_mat_trans_f64.c" +#include "arm_mat_trans_q7.c" +#include "arm_mat_trans_q15.c" +#include "arm_mat_trans_q31.c" +#include "arm_mat_vec_mult_f32.c" +#include "arm_mat_vec_mult_q31.c" +#include "arm_mat_vec_mult_q15.c" +#include "arm_mat_vec_mult_q7.c" +#include "arm_mat_cmplx_trans_f32.c" +#include "arm_mat_cmplx_trans_q31.c" +#include "arm_mat_cmplx_trans_q15.c" +#include "arm_mat_cholesky_f64.c" +#include "arm_mat_cholesky_f32.c" +#include "arm_mat_solve_upper_triangular_f32.c" +#include "arm_mat_solve_lower_triangular_f32.c" +#include "arm_mat_solve_upper_triangular_f64.c" +#include "arm_mat_solve_lower_triangular_f64.c" +#include "arm_mat_ldlt_f32.c" +#include "arm_mat_ldlt_f64.c" diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c new file mode 100644 index 0000000..9d3a41f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctionsF16.c @@ -0,0 +1,41 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: MatrixFunctions.c + * Description: Combination of all matrix function f16 source files. + * + * $Date: 18. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_mat_add_f16.c" +#include "arm_mat_sub_f16.c" +#include "arm_mat_trans_f16.c" +#include "arm_mat_scale_f16.c" +#include "arm_mat_mult_f16.c" +#include "arm_mat_vec_mult_f16.c" +#include "arm_mat_cmplx_trans_f16.c" +#include "arm_mat_cmplx_mult_f16.c" +#include "arm_mat_inverse_f16.c" +#include "arm_mat_init_f16.c" +#include "arm_mat_cholesky_f16.c" +#include "arm_mat_solve_upper_triangular_f16.c" +#include "arm_mat_solve_lower_triangular_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c new file mode 100644 index 0000000..2db2c2a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f16.c @@ -0,0 +1,217 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f16.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else + +arm_status arm_mat_add_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = (_Float16)*pInA++ + (_Float16)*pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c new file mode 100644 index 0000000..879c8f8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c @@ -0,0 +1,304 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_f32.c + * Description: Floating-point matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixAdd Matrix Addition + + Adds two matrices. + \image html MatrixAddition.gif "Addition of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixAdd + @{ + */ + + +/** + @brief Floating-point matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + return (status); +} +#else +#if defined(ARM_MATH_NEON) +/* + +Neon version is assuming the matrix is small enough. +So no blocking is used for taking into account cache effects. +For big matrix, there exist better libraries for Neon. + +*/ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vaddq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) + (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add and store result in destination buffer. */ + *pOut++ = *pInA++ + *pInB++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c new file mode 100644 index 0000000..e27b72f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c @@ -0,0 +1,227 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q15.c + * Description: Q15 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q15 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + + write_q15x2_ia (&pOut, __QADD16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); + + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) *pInA++ + *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c new file mode 100644 index 0000000..57f67e7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_add_q31.c + * Description: Q31 matrix addition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixAdd + @{ + */ + +/** + @brief Q31 matrix addition. + @param[in] pSrcA points to first input matrix structure + @param[in] pSrcB points to second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix addition */ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* Add and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqaddq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix addition */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + + /* Add, saturate and store result in destination buffer. */ + *pOut++ = __QADD(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixAdd group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c new file mode 100644 index 0000000..9c8acef --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f16.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f16.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + _Float16 invSqrtVj; + float16_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f16x8_t acc, acc0, acc1, acc2, acc3; + f16x8_t vecGi; + f16x8_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + acc0 = vdupq_n_f16(0.0f16); + acc0[0]=pA[(j + 0) * n + i]; + + acc1 = vdupq_n_f16(0.0f16); + acc1[0]=pA[(j + 1) * n + i]; + + acc2 = vdupq_n_f16(0.0f16); + acc2[0]=pA[(j + 2) * n + i]; + + acc3 = vdupq_n_f16(0.0f16); + acc3[0]=pA[(j + 3) * n + i]; + + kCnt = i; + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + + vecGj0=vldrhq_z_f16(&pG[(j + 0) * n + k],p0); + vecGj1=vldrhq_z_f16(&pG[(j + 1) * n + k],p0); + vecGj2=vldrhq_z_f16(&pG[(j + 2) * n + k],p0); + vecGj3=vldrhq_z_f16(&pG[(j + 3) * n + k],p0); + + acc0 = vfmsq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmsq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmsq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmsq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 8; + } + pG[(j + 0) * n + i] = vecAddAcrossF16Mve(acc0); + pG[(j + 1) * n + i] = vecAddAcrossF16Mve(acc1); + pG[(j + 2) * n + i] = vecAddAcrossF16Mve(acc2); + pG[(j + 3) * n + i] = vecAddAcrossF16Mve(acc3); + } + + for(; j < n ; j++) + { + + kCnt = i; + acc = vdupq_n_f16(0.0f16); + acc[0] = pA[j * n + i]; + + for(k=0; k < i ; k+=8) + { + p0 = vctp16q(kCnt); + + vecGi=vldrhq_z_f16(&pG[i * n + k],p0); + vecGj=vldrhq_z_f16(&pG[j * n + k],p0); + + acc = vfmsq_m(acc, vecGi, vecGj,p0); + + kCnt -= 8; + } + pG[j * n + i] = vecAddAcrossF16Mve(acc); + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f16/(_Float16)sqrtf((float32_t)pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] * (_Float16)invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float16_t invSqrtVj; + float16_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] - (_Float16)pG[i * n + k] * (_Float16)pG[j * n + k]; + } + } + + if ((_Float16)pG[i * n + i] <= 0.0f16) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + /* The division is done in float32 for accuracy reason and + because doing it in f16 would not have any impact on the performances. + */ + invSqrtVj = 1.0f/sqrtf((float32_t)pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = (_Float16)pG[j * n + i] * (_Float16)invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c new file mode 100644 index 0000000..94b9689 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f32.c @@ -0,0 +1,438 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f32.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 05 October 2021 + * $Revision: V1.9.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixChol Cholesky and LDLT decompositions + + Computes the Cholesky or LDL^t decomposition of a matrix. + + + If the input matrix does not have a decomposition, then the + algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE. + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + mve_pred16_t p0; + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + kCnt = i; + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + + vecGj0=vldrwq_z_f32(&pG[(j + 0) * n + k],p0); + vecGj1=vldrwq_z_f32(&pG[(j + 1) * n + k],p0); + vecGj2=vldrwq_z_f32(&pG[(j + 2) * n + k],p0); + vecGj3=vldrwq_z_f32(&pG[(j + 3) * n + k],p0); + + acc0 = vfmaq_m(acc0, vecGi, vecGj0, p0); + acc1 = vfmaq_m(acc1, vecGi, vecGj1, p0); + acc2 = vfmaq_m(acc2, vecGi, vecGj2, p0); + acc3 = vfmaq_m(acc3, vecGi, vecGj3, p0); + + kCnt -= 4; + } + pG[(j + 0) * n + i] -= vecAddAcrossF32Mve(acc0); + pG[(j + 1) * n + i] -= vecAddAcrossF32Mve(acc1); + pG[(j + 2) * n + i] -= vecAddAcrossF32Mve(acc2); + pG[(j + 3) * n + i] -= vecAddAcrossF32Mve(acc3); + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + kCnt = i; + acc = vdupq_n_f32(0.0f); + + for(k=0; k < i ; k+=4) + { + p0 = vctp32q(kCnt); + + vecGi=vldrwq_z_f32(&pG[i * n + k],p0); + vecGj=vldrwq_z_f32(&pG[j * n + k],p0); + + acc = vfmaq_m(acc, vecGi, vecGj,p0); + + kCnt -= 4; + } + pG[j * n + i] -= vecAddAcrossF32Mve(acc); + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + int kCnt; + + + f32x4_t acc, acc0, acc1, acc2, acc3; + f32x4_t vecGi; + f32x4_t vecGj,vecGj0,vecGj1,vecGj2,vecGj3; +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0); +#endif + float32_t sum=0.0f; + float32_t sum0=0.0f,sum1=0.0f,sum2=0.0f,sum3=0.0f; + + + pA = pSrc->pData; + pG = pDst->pData; + + for(i=0 ;i < n ; i++) + { + for(j=i ; j+3 < n ; j+=4) + { + pG[(j + 0) * n + i] = pA[(j + 0) * n + i]; + pG[(j + 1) * n + i] = pA[(j + 1) * n + i]; + pG[(j + 2) * n + i] = pA[(j + 2) * n + i]; + pG[(j + 3) * n + i] = pA[(j + 3) * n + i]; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + + vecGj0=vld1q_f32(&pG[(j + 0) * n + k]); + vecGj1=vld1q_f32(&pG[(j + 1) * n + k]); + vecGj2=vld1q_f32(&pG[(j + 2) * n + k]); + vecGj3=vld1q_f32(&pG[(j + 3) * n + k]); + + acc0 = vfmaq_f32(acc0, vecGi, vecGj0); + acc1 = vfmaq_f32(acc1, vecGi, vecGj1); + acc2 = vfmaq_f32(acc2, vecGi, vecGj2); + acc3 = vfmaq_f32(acc3, vecGi, vecGj3); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum0 = vpadds_f32(vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0))); + sum1 = vpadds_f32(vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1))); + sum2 = vpadds_f32(vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2))); + sum3 = vpadds_f32(vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3))); + +#else + tmp = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + + tmp = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + + sum0 = sum0 + pG[i * n + k] * pG[(j + 0) * n + k]; + sum1 = sum1 + pG[i * n + k] * pG[(j + 1) * n + k]; + sum2 = sum2 + pG[i * n + k] * pG[(j + 2) * n + k]; + sum3 = sum3 + pG[i * n + k] * pG[(j + 3) * n + k]; + kCnt--; + k++; + } + + pG[(j + 0) * n + i] -= sum0; + pG[(j + 1) * n + i] -= sum1; + pG[(j + 2) * n + i] -= sum2; + pG[(j + 3) * n + i] -= sum3; + } + + for(; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + acc = vdupq_n_f32(0.0f); + + kCnt = i >> 2; + k=0; + while(kCnt > 0) + { + + vecGi=vld1q_f32(&pG[i * n + k]); + vecGj=vld1q_f32(&pG[j * n + k]); + + acc = vfmaq_f32(acc, vecGi, vecGj); + + kCnt--; + k+=4; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(acc), vget_high_f32(acc))); +#else + tmp = vpadd_f32(vget_low_f32(acc), vget_high_f32(acc)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); +#endif + + kCnt = i & 3; + while(kCnt > 0) + { + sum = sum + pG[i * n + k] * pG[(j + 0) * n + k]; + + + kCnt--; + k++; + } + + pG[j * n + i] -= sum; + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cholesky_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float32_t invSqrtVj; + float32_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0f) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0f/sqrtf(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c new file mode 100644 index 0000000..4e095d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cholesky_f64.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cholesky_f64.c + * Description: Floating-point Cholesky decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point Cholesky decomposition of positive-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pDst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition. + * The decomposition of A is returning a lower triangular matrix U such that A = U U^t + */ + + +arm_status arm_mat_cholesky_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + int i,j,k; + int n = pSrc->numRows; + float64_t invSqrtVj; + float64_t *pA,*pG; + + pA = pSrc->pData; + pG = pDst->pData; + + + for(i=0 ; i < n ; i++) + { + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pA[j * n + i]; + + for(k=0; k < i ; k++) + { + pG[j * n + i] = pG[j * n + i] - pG[i * n + k] * pG[j * n + k]; + } + } + + if (pG[i * n + i] <= 0.0) + { + return(ARM_MATH_DECOMPOSITION_FAILURE); + } + + invSqrtVj = 1.0/sqrt(pG[i * n + i]); + for(j=i ; j < n ; j++) + { + pG[j * n + i] = pG[j * n + i] * invSqrtVj ; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c new file mode 100644 index 0000000..f566696 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f16.c @@ -0,0 +1,935 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_mat_cmplx_mult_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +#include "arm_helium_utils.h" + +#define DONTCARE 0 /* inactive lane content */ + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_2x2_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 2 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0,vecColAOffs0,vecColAOffs1; + float16_t *pInA0 = pInA; + f16x8_t acc0, acc1; + f16x8_t vecB, vecA0, vecA1; + f16x8_t vecTmp; + uint16_t tmp; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2, 3, + MATRIX_DIM * CMPLX_DIM + 2 , MATRIX_DIM * CMPLX_DIM + 3, + }; + + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + tmp = 0; + vecColAOffs0 = viwdupq_u16(tmp, 4, 1); + + tmp = (CMPLX_DIM * MATRIX_DIM); + vecColAOffs1 = vecColAOffs0 + (uint16_t)(CMPLX_DIM * MATRIX_DIM); + + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs0); + vecA1 = vldrhq_gather_shifted_offset_f16(pInA0, vecColAOffs1); + + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + + /* + * Compute + * re0+re1 | im0+im1 | re0+re1 | im0+im1 + * re2+re3 | im2+im3 | re2+re3 | im2+im3 + */ + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc0); + vecTmp = vaddq(vecTmp, acc0); + + + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[0 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + vecTmp = (f16x8_t) vrev64q_s32((int32x4_t) acc1); + vecTmp = vaddq(vecTmp, acc1); + + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM]) = ((f32x4_t)vecTmp)[0]; + *(float32_t *)(&pOut[1 * CMPLX_DIM * MATRIX_DIM + CMPLX_DIM]) = ((f32x4_t)vecTmp)[2]; + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_3x3_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 3 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2; + f16x8_t vecB, vecA0, vecA1, vecA2; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + DONTCARE, DONTCARE + }; + + + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp16q(MATRIX_DIM * CMPLX_DIM); + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecA0 = vldrhq_f16(pInA0); + vecA1 = vldrhq_f16(pInA1); + vecA2 = vldrhq_f16(pInA2); + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecColBOffs0, p0); + + acc0 = vcmulq(vecA0, vecB); + acc0 = vcmlaq_rot90(acc0, vecA0, vecB); + + acc1 = vcmulq(vecA1, vecB); + acc1 = vcmlaq_rot90(acc1, vecA1, vecB); + + acc2 = vcmulq(vecA2, vecB); + acc2 = vcmlaq_rot90(acc2, vecA2, vecB); + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_cmplx_mult_f16_4x4_mve( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ +#define MATRIX_DIM 4 + float16_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs0; + float16_t *pInA0 = pInA; + float16_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM; + float16_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + f16x8_t vecB, vecA; + static const uint16_t offsetB0[8] = { 0, 1, + MATRIX_DIM * CMPLX_DIM, MATRIX_DIM * CMPLX_DIM + 1, + 2 * MATRIX_DIM * CMPLX_DIM, 2 * MATRIX_DIM * CMPLX_DIM + 1, + 3 * MATRIX_DIM * CMPLX_DIM, 3 * MATRIX_DIM * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrhq_u16((uint16_t const *) offsetB0); + + pInB = (float16_t const *)pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrhq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrhq_f16(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrhq_f16(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrhq_f16(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrhq_f16(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + + mve_cmplx_sum_intra_vec_f16(acc0, &pOut[0 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc1, &pOut[1 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc2, &pOut[2 * CMPLX_DIM * MATRIX_DIM]); + mve_cmplx_sum_intra_vec_f16(acc3, &pOut[3 * CMPLX_DIM * MATRIX_DIM]); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +#undef MATRIX_DIM +} + + + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t const *pInB = (float16_t const *) pSrcB->pData; /* input data matrix pointer B */ + float16_t const *pInA = (float16_t const *) pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint16x8_t vecOffs, vecColBOffs; + uint32_t blkCnt,rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ +if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = (_Float16)pInA[0] * (_Float16)pInB[0] - (_Float16)pInA[1] * (_Float16)pInB[1]; + pOut[1] = (_Float16)pInA[0] * (_Float16)pInB[1] + (_Float16)pInA[1] * (_Float16)pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2*numColsB * CMPLX_DIM; + vecColBOffs[5] = 2*(numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3*numColsB * CMPLX_DIM; + vecColBOffs[7] = 3*(numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float16_t const *pInA0 = pInA; + float16_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float16_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float16_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f16x8_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + acc2 = vdupq_n_f16(0.0f16); + acc3 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + pSrcA1Vec = (float16_t const *) pInA1; + pSrcA2Vec = (float16_t const *) pInA2; + pSrcA3Vec = (float16_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_f16(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs , (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 8; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 8; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 8; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + /* + * Unsupported addressing mode compiler crash + */ + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z_f16(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc1, &px[1 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc2, &px[2 * CMPLX_DIM * numColsB + 0]); + mve_cmplx_sum_intra_vec_f16(acc3, &px[3 * CMPLX_DIM * numColsB + 0]); + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float16_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float16_t const *pSrcA0Vec; + float16_t const *pInA0 = pInA; + f16x8_t acc0; + + acc0 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = (float16_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (4*numColsB * CMPLX_DIM)); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecB, vecA; + + vecB = vldrhq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + mve_cmplx_sum_intra_vec_f16(acc0, &px[0]); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float16_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} +#else + +arm_status arm_mat_cmplx_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + _Float16 sumReal, sumImag; /* Accumulator */ + _Float16 a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + _Float16 a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f16; + sumImag = 0.0f16; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c new file mode 100644 index 0000000..5add938 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c @@ -0,0 +1,1407 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup CmplxMatrixMult Complex Matrix Multiplication + + Complex Matrix multiplication is only defined if the number of columns of the + first matrix equals the number of rows of the second matrix. + Multiplying an M x N matrix with an N x P matrix results + in an M x P matrix. + @par + When matrix size checking is enabled, the functions check: + - that the inner dimensions of pSrcA and pSrcB are equal; + - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Floating-point Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_2x2_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + f32x4_t acc0, acc1; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = acc1[1] + acc1[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_3x3_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + f32x4_t acc0, acc1, acc2; + f32x4_t vecB, vecA; + /* enable predication to disable upper half complex vector element */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecColBOffs1, p0); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = acc2[1] + acc2[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_f32_4x4_mve( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + float32_t *pInA0 = pInA; + float32_t *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + float32_t *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + f32x4_t acc0, acc1, acc2, acc3; + f32x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32((uint32_t const *) offsetB0); + vecColBOffs1 = vldrwq_u32((uint32_t const *) offsetB1); + + pInB = (float32_t const *)pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + + vecA = vldrwq_f32(pInA0); + acc0 = vcmulq(vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(pInA1); + acc1 = vcmulq(vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(pInA2); + acc2 = vcmulq(vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(pInA3); + acc3 = vcmulq(vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_f32(&pInA0[4]); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + vecA = vldrwq_f32(&pInA1[4]); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + + vecA = vldrwq_f32(&pInA2[4]); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + + vecA = vldrwq_f32(&pInA3[4]); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc0[0] + acc0[2]; + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc0[1] + acc0[3]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc1[0] + acc1[2]; + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc1[1] + acc1[3]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc2[0] + acc2[2]; + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc2[1] + acc2[3]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = acc3[0] + acc3[2]; + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = acc3[1] + acc3[3]; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t const *pInB = (float32_t const *) pSrcB->pData; /* input data matrix pointer B */ + float32_t const *pInA = (float32_t const *) pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0] - pInA[1] * pInB[1]; + pOut[1] = pInA[0] * pInB[1] + pInA[1] * pInB[0]; + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + float32_t const *pInA0 = pInA; + float32_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + float32_t const *pInA2 = pInA1 + numColsA * CMPLX_DIM; + float32_t const *pInA3 = pInA2 + numColsA * CMPLX_DIM; + f32x4_t acc0, acc1, acc2, acc3; + + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + pSrcA1Vec = (float32_t const *) pInA1; + pSrcA2Vec = (float32_t const *) pInA2; + pSrcA3Vec = (float32_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + blkCnt--; + } + + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc1 = vcmlaq(acc1, vecA, vecB); + acc1 = vcmlaq_rot90(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); + acc2 = vcmlaq(acc2, vecA, vecB); + acc2 = vcmlaq_rot90(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); + acc3 = vcmlaq(acc3, vecA, vecB); + acc3 = vcmlaq_rot90(acc3, vecA, vecB); + + } + + px[0 * CMPLX_DIM * numColsB + 0] = acc0[0] + acc0[2]; + px[0 * CMPLX_DIM * numColsB + 1] = acc0[1] + acc0[3]; + px[1 * CMPLX_DIM * numColsB + 0] = acc1[0] + acc1[2]; + px[1 * CMPLX_DIM * numColsB + 1] = acc1[1] + acc1[3]; + px[2 * CMPLX_DIM * numColsB + 0] = acc2[0] + acc2[2]; + px[2 * CMPLX_DIM * numColsB + 1] = acc2[1] + acc2[3]; + px[3 * CMPLX_DIM * numColsB + 0] = acc3[0] + acc3[2]; + px[3 * CMPLX_DIM * numColsB + 1] = acc3[1] + acc3[3]; + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 3; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (float32_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + float32_t const *pSrcA0Vec; + float32_t const *pInA0 = pInA; + f32x4_t acc0; + + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = (float32_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 4 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + vecA = vld1q(pSrcA0Vec); + acc0 = vcmlaq(acc0, vecA, vecB); + acc0 = vcmlaq_rot90(acc0, vecA, vecB); + + } + + px[0] = acc0[0] + acc0[2]; + px[1] = acc0[1] + acc0[3]; + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (float32_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + float32_t sumReal1, sumImag1; /* accumulator */ + float32_t a1, a1B,b1, b1B, c1, d1; + float32_t sumReal2, sumImag2; /* accumulator */ + + + float32x4x2_t a0V, a1V; + float32x4_t accR0,accI0, accR1,accI1,tempR, tempI; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + + uint16_t col, i = 0U, j, rowCnt, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + float32_t sumReal1B, sumImag1B; + float32_t sumReal2B, sumImag2B; + float32_t *pxB; + +#ifdef ARM_MATH_MATRIX_CHECK + + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + + rowCnt = row >> 1; + + /* Row loop */ + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + pxB = px + 2 * numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + sumReal1B = 0.0f; + sumImag1B = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + sumReal2B = 0.0f; + sumImag2B = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + 2*numColsA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + accR1 = vdupq_n_f32(0.0); + accI1 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + a1V = vld2q_f32(pIn1B); // load & separate real/imag pSrcA (de-interleave 2) + + pIn1 += 8; + pIn1B += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + accR1 = vmlaq_f32(accR1,a1V.val[0],tempR); + accR1 = vmlsq_f32(accR1,a1V.val[1],tempI); + + accI1 = vmlaq_f32(accI1,a1V.val[1],tempR); + accI1 = vmlaq_f32(accI1,a1V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accR1), vget_high_f32(accR1)); + sumReal1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI1), vget_high_f32(accI1)); + sumImag1B += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + a1B = *pIn1B; + + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + b1B = *(pIn1B + 1U); + + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + sumReal1B += a1B * c1; + sumImag1B += b1B * c1; + + pIn1 += 2U; + pIn1B += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + sumReal2B -= b1B * d1; + sumImag2B += a1B * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + sumReal1B += sumReal2B; + sumImag1B += sumImag2B; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + *pxB++ = sumReal1B; + *pxB++ = sumImag1B; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + } + + /* Update the pointer pInA to point to the starting address of the next 2 row */ + i = i + 2*numColsB; + pInA = pInA + 4 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + rowCnt = row & 1; + while (rowCnt > 0U) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal1 = 0.0f; + sumImag1 = 0.0f; + + sumReal2 = 0.0f; + sumImag2 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + accR0 = vdupq_n_f32(0.0); + accI0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* Reading real part of complex matrix A */ + a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 8; + + tempR = vsetq_lane_f32(*pIn2,tempR,0); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,0); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,1); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,1); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,2); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,2); + pIn2 += 2 * numColsB; + + tempR = vsetq_lane_f32(*pIn2,tempR,3); + tempI = vsetq_lane_f32(*(pIn2 + 1U),tempI,3); + pIn2 += 2 * numColsB; + + accR0 = vmlaq_f32(accR0,a0V.val[0],tempR); + accR0 = vmlsq_f32(accR0,a0V.val[1],tempI); + + accI0 = vmlaq_f32(accI0,a0V.val[1],tempR); + accI0 = vmlaq_f32(accI0,a0V.val[0],tempI); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0)); + sumReal1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0)); + sumImag1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a1 = *pIn1; + c1 = *pIn2; + + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + sumReal1 += a1 * c1; + sumImag1 += b1 * c1; + + pIn1 += 2U; + pIn2 += 2 * numColsB; + + sumReal2 -= b1 * d1; + sumImag2 += a1 * d1; + + /* Decrement the loop counter */ + colCnt--; + } + + sumReal1 += sumReal2; + sumImag1 += sumImag2; + + /* Store the result in the destination buffer */ + *px++ = sumReal1; + *px++ = sumImag1; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement the column loop counter */ + col--; + + } + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + float32_t sumReal, sumImag; /* Accumulator */ + float32_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + float32_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0f; + sumImag = 0.0f; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a0 * c0; + sumImag += b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b0 * d0; + sumImag += a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += a1 * c1; + sumImag += b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= b1 * d1; + sumImag += a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sumReal; + *px++ = sumImag; + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c new file mode 100644 index 0000000..5b9db9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cmplx_mat_mult_q15.c + * Description: Q15 complex matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q15 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @param[in] pScratch points to an array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Conditions for optimum performance + Input, output and state buffers should be aligned by 32-bit + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then + truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t const *pInA = (q15_t const *) pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t const *pInB = (q15_t const *) pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t const *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + uint32_t blkCnt; /* loop counters */ + uint16x8_t vecOffs, vecColBOffs; + arm_status status; /* Status of matrix multiplication */ + (void)pScratch; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + vecColBOffs[4] = 2 * numColsB * CMPLX_DIM; + vecColBOffs[5] = 2 * (numColsB * CMPLX_DIM) + 1; + vecColBOffs[6] = 3 * numColsB * CMPLX_DIM; + vecColBOffs[7] = 3 * (numColsB * CMPLX_DIM) + 1; + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA; + px = pDst->pData; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + j = 0; + /* + * column loop + */ + while (col > 0u) + { + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInB2 = pInB + CMPLX_DIM; + + j += 2 * CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecOffs = vecColBOffs; + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + vecB2 = vldrhq_gather_shifted_offset(pInB2, vecOffs); + + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + acc2 = vmlsldavaq_s16(acc2, vecA, vecB2); + acc3 = vmlaldavaxq_s16(acc3, vecA, vecB2); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc2, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc3, 15); + } + + col = numColsB & 1; + /* + * column loop + */ + while (col > 0u) + { + + q15_t const *pSrcAVec; + //, *pSrcBVec, *pSrcB2Vec; + q15x8_t vecA, vecB; + q63_t acc0, acc1; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + + j += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + + /* + * Initiate the pointers + * - current Matrix A rows + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pSrcAVec = (q15_t const *) pInA; + + acc0 = 0LL; + acc1 = 0LL; + + + vecOffs = vecColBOffs; + + + + blkCnt = (numColsA * CMPLX_DIM) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + /* + * move Matrix B read offsets, 4 rows down + */ + vecOffs = vaddq_n_u16(vecOffs, (uint16_t) (numColsB * 4 * CMPLX_DIM)); + + blkCnt--; + } + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vldrhq_gather_shifted_offset(pInB, vecOffs); + vecA = vldrhq_z_s16(pSrcAVec, p0); + + acc0 = vmlsldavaq_s16(acc0, vecA, vecB); + acc1 = vmlaldavaxq_s16(acc1, vecA, vecB); + + } + /* + * Convert to 1.15, Store the results (1 x 2 block) in the destination buffer + */ + *px++ = (q15_t)MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t)MVE_ASRL_SAT16(acc1, 15); + + } + + i = i + numColsA * CMPLX_DIM; + + /* + * Decrement the row loop counter + */ + row--; + } + + + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch) +{ + q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + q63_t sumReal, sumImag; /* accumulator */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t prod1, prod2; + q31_t pSourceA, pSourceB; +#else + q15_t a, b, c, d; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and exchange the columns with row elements */ + col = numColsB >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + col = numColsB; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read two elements from row */ + write_q15x2 (px, read_q15x2_ia (&pInB)); + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB * 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + 2U; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sumReal = 0; + sumImag = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i * 2; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 1U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA buffer */ + a = *pInA; + b = *(pInA + 1U); + /* read real and imag values from pSrcB buffer */ + c = *pInB; + d = *(pInB + 1U); + + /* Multiply and Accumlates */ + sumReal += (q31_t) a *c; + sumImag += (q31_t) a *d; + sumReal -= (q31_t) b *d; + sumImag += (q31_t) b *c; + + /* read next real and imag values from pSrcA buffer */ + a = *(pInA + 2U); + b = *(pInA + 3U); + /* read next real and imag values from pSrcB buffer */ + c = *(pInB + 2U); + d = *(pInB + 3U); + + /* update pointer */ + pInA += 4U; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + /* update pointer */ + pInB += 4U; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ + if ((numColsA & 0x1U) > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + pSourceA = read_q15x2_ia (&pInA); + pSourceB = read_q15x2_ia (&pInB); + + /* Multiply and Accumlates */ +#ifdef ARM_MATH_BIG_ENDIAN + prod1 = -__SMUSD(pSourceA, pSourceB); +#else + prod1 = __SMUSD(pSourceA, pSourceB); +#endif + prod2 = __SMUADX(pSourceA, pSourceB); + sumReal += (q63_t) prod1; + sumImag += (q63_t) prod2; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a = *pInA++; + b = *pInA++; + c = *pInB++; + d = *pInB++; + + /* Multiply and Accumlates */ + sumReal += (q31_t) a * c; + sumImag += (q31_t) a * d; + sumReal -= (q31_t) b * d; + sumImag += (q31_t) b * c; + +#endif /* #if defined (ARM_MATH_DSP) */ + + } + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (__SSAT(sumReal >> 15, 16)); + *px++ = (q15_t) (__SSAT(sumImag >> 15, 16)); + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c new file mode 100644 index 0000000..ee784a6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c @@ -0,0 +1,1061 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_mult_q31.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup CmplxMatrixMult + @{ + */ + +/** + @brief Q31 Complex matrix multiplication. + @param[in] pSrcA points to first input complex matrix structure + @param[in] pSrcB points to second input complex matrix structure + @param[out] pDst points to output complex matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM2; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM2 * CMPLX_DIM, MATRIX_DIM2 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + pOut += CMPLX_DIM; + + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM2 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM3; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM3; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + /* + * enable predication to disable upper half complex vector element + */ + mve_pred16_t p0 = vctp32q(CMPLX_DIM); + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM3 * CMPLX_DIM, MATRIX_DIM3 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM3 * CMPLX_DIM, 2 * MATRIX_DIM3 * CMPLX_DIM + 1, + INACTIVELANE, INACTIVELANE + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA0[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_z_s32(&pInA1[4], p0); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_z_s32(&pInA2[4], p0); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM3 + 1] = (q31_t) asrl(acc1, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_cmplx_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs0, vecColBOffs1; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA2 = pInA1 + CMPLX_DIM * MATRIX_DIM4; + q31_t const *pInA3 = pInA2 + CMPLX_DIM * MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecB1, vecA; + + static const uint32_t offsetB0[4] = { + 0, 1, + MATRIX_DIM4 * CMPLX_DIM, MATRIX_DIM4 * CMPLX_DIM + 1 + }; + static const uint32_t offsetB1[4] = { + 2 * MATRIX_DIM4 * CMPLX_DIM, 2 * MATRIX_DIM4 * CMPLX_DIM + 1, + 3 * MATRIX_DIM4 * CMPLX_DIM, 3 * MATRIX_DIM4 * CMPLX_DIM + 1 + }; + + vecColBOffs0 = vldrwq_u32(offsetB0); + vecColBOffs1 = vldrwq_u32(offsetB1); + + pInB = (q31_t const *) pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + pOut += CMPLX_DIM; + + /* + * move to next B column + */ + pInB = pInB + CMPLX_DIM; + + vecB = vldrwq_gather_shifted_offset(pInB, vecColBOffs0); + vecB1 = vldrwq_gather_shifted_offset(pInB, vecColBOffs1); + + vecA = vldrwq_s32(pInA0); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA1); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA0[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA1[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[0 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[1 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + + vecA = vldrwq_s32(pInA2); + acc0 = vmlsldavq_s32(vecA, vecB); + acc1 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(pInA3); + acc2 = vmlsldavq_s32(vecA, vecB); + acc3 = vmlaldavxq_s32(vecA, vecB); + + vecA = vldrwq_s32(&pInA2[4]); + acc0 = vmlsldavaq_s32(acc0, vecA, vecB1); + acc1 = vmlaldavaxq_s32(acc1, vecA, vecB1); + + vecA = vldrwq_s32(&pInA3[4]); + acc2 = vmlsldavaq_s32(acc2, vecA, vecB1); + acc3 = vmlaldavaxq_s32(acc3, vecA, vecB1); + + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc0, 31); + pOut[2 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc1, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 0] = (q31_t) asrl(acc2, 31); + pOut[3 * CMPLX_DIM * MATRIX_DIM4 + 1] = (q31_t) asrl(acc3, 31); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *) pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *) pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * small squared matrix specialized routines + */ + if (numRowsA == numColsB && numColsB == numColsA) + { + if (numRowsA == 1) + { + q63_t sumReal = (q63_t) pInA[0] * pInB[0]; + sumReal -= (q63_t) pInA[1] * pInB[1]; + + q63_t sumImag = (q63_t) pInA[0] * pInB[1]; + sumImag += (q63_t) pInA[1] * pInB[0]; + + /* Store result in destination buffer */ + pOut[0] = (q31_t) clip_q63_to_q31(sumReal >> 31); + pOut[1] = (q31_t) clip_q63_to_q31(sumImag >> 31); + return (ARM_MATH_SUCCESS); + } + else if (numRowsA == 2) + return arm_mat_cmplx_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_cmplx_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_cmplx_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs[0] = 0; + vecColBOffs[1] = 1; + vecColBOffs[2] = numColsB * CMPLX_DIM; + vecColBOffs[3] = (numColsB * CMPLX_DIM) + 1; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + 2 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA * CMPLX_DIM; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + + vecA = vld1q(pSrcA0Vec); + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + vecA = vld1q(pSrcA1Vec); + acc2 = vmlsldavaq(acc2, vecA, vecB); + acc3 = vmlaldavaxq(acc3, vecA, vecB); + + + } + + px[0 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[0 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + px[1 * CMPLX_DIM * numColsB + 0] = (q31_t) clip_q63_to_q31(acc2 >> 31); + px[1 * CMPLX_DIM * numColsB + 1] = (q31_t) clip_q63_to_q31(acc3 >> 31); + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 2) * CMPLX_DIM; + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + + rowCnt = row & 1; + while (rowCnt > 0u) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i * CMPLX_DIM; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *) pSrcB->pData; + /* + * column loop + */ + while (col > 0u) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0,acc1; + + acc0 = 0LL; + acc1 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* + * process 1 x 2 block output + */ + blkCnt = (numColsA * CMPLX_DIM) >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + blkCnt--; + } + + + /* + * tail + */ + blkCnt = (numColsA * CMPLX_DIM) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + + /* + * move Matrix B read offsets, 2 rows down + */ + vecOffs = vecOffs + (uint32_t) (numColsB * 2 * CMPLX_DIM); + + vecA = vld1q(pSrcA0Vec); + + + acc0 = vmlsldavaq(acc0, vecA, vecB); + acc1 = vmlaldavaxq(acc1, vecA, vecB); + + + } + + px[0] = (q31_t) clip_q63_to_q31(acc0 >> 31); + px[1] = (q31_t) clip_q63_to_q31(acc1 >> 31); + + + px += CMPLX_DIM; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *) pSrcB->pData + (numColsB - col) * CMPLX_DIM; + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA * CMPLX_DIM; + rowCnt--; + } + + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + q63_t sumReal, sumImag; /* Accumulator */ + q31_t a1, b1, c1, d1; + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t a0, b0, c0, d0; +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + 2 * i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sumReal = 0.0; + sumImag = 0.0; + + /* Initiate pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Apply loop unrolling and compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + + /* Reading real part of complex matrix A */ + a0 = *pIn1; + + /* Reading real part of complex matrix B */ + c0 = *pIn2; + + /* Reading imaginary part of complex matrix A */ + b0 = *(pIn1 + 1U); + + /* Reading imaginary part of complex matrix B */ + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + a0 = *(pIn1 ); + c0 = *(pIn2 ); + b0 = *(pIn1 + 1U); + d0 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a0 * c0; + sumImag += (q63_t) b0 * c0; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b0 * d0; + sumImag += (q63_t) a0 * d0; + + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop count */ + colCnt--; + } + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + a1 = *(pIn1 ); + c1 = *(pIn2 ); + b1 = *(pIn1 + 1U); + d1 = *(pIn2 + 1U); + + /* Multiply and Accumlates */ + sumReal += (q63_t) a1 * c1; + sumImag += (q63_t) b1 * c1; + + /* update pointers */ + pIn1 += 2U; + pIn2 += 2 * numColsB; + + /* Multiply and Accumlates */ + sumReal -= (q63_t) b1 * d1; + sumImag += (q63_t) a1 * d1; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31); + *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31); + + /* Update pointer pIn2 to point to starting address of next column */ + j++; + pIn2 = pSrcB->pData + 2U * j; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + 2 * numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c new file mode 100644 index 0000000..5eda8c3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f16.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f16.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f16(const arm_matrix_instance_f16 * pSrc, arm_matrix_instance_f16 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c new file mode 100644 index 0000000..222f349 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_f32.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_f32.c + * Description: Floating-point complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixComplexTrans Complex Matrix Transpose + + Tranposes a complex matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_f32(const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + +#else +arm_status arm_mat_cmplx_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c new file mode 100644 index 0000000..8a3724e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q15 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q15 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_cmplx_trans_q15(const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst) +{ + return arm_mat_cmplx_trans_16bit(pSrc->numRows, pSrc->numCols, (uint16_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint16_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + pOut[0] = *pSrcA++; //real + pOut[1] = *pSrcA++; //imag + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += CMPLX_DIM *nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c new file mode 100644 index 0000000..a8612a3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_trans_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_cmplx_trans_q31.c + * Description: Q31 complex matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + + +/** + @addtogroup MatrixComplexTrans + @{ + */ + +/** + @brief Q31 complex matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +arm_status arm_mat_cmplx_trans_q31(const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst) +{ + return arm_mat_cmplx_trans_32bit(pSrc->numRows, pSrc->numCols, (uint32_t *) pSrc->pData, + pDst->numRows, pDst->numCols, (uint32_t *) pDst->pData); +} + + +#else +arm_status arm_mat_cmplx_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* The pointer px is set to starting address of the column being processed */ + px = pOut + CMPLX_DIM * i; + + /* Initialize column loop counter */ + col = nColumns; + + while (col > 0U) + { + /* Read and store the input element in the destination */ + px[0] = *pIn++; // real + px[1] = *pIn++; // imag + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += CMPLX_DIM * nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } + while (row > 0U); /* row loop end */ + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c new file mode 100644 index 0000000..6a48102 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f16.c @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f16.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f16( + arm_matrix_instance_f16 * S, + uint16_t nRows, + uint16_t nColumns, + float16_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c new file mode 100644 index 0000000..d2a5201 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_f32.c + * Description: Floating-point matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + Initializes the underlying matrix data structure. + The functions set the numRows, + numCols, and pData fields + of the matrix data structure. + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Floating-point matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c new file mode 100644 index 0000000..33942b5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q15.c + * Description: Q15 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q15 matrix initialization. + @param[in,out] S points to an instance of the floating-point matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c new file mode 100644 index 0000000..ab735d0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_init_q31.c + * Description: Q31 matrix initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInit Matrix Initialization + + */ + +/** + @addtogroup MatrixInit + @{ + */ + +/** + @brief Q31 matrix initialization. + @param[in,out] S points to an instance of the Q31 matrix structure + @param[in] nRows number of rows in the matrix + @param[in] nColumns number of columns in the matrix + @param[in] pData points to the matrix data array + @return none + */ + +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData) +{ + /* Assign Number of Rows */ + S->numRows = nRows; + + /* Assign Number of Columns */ + S->numCols = nColumns; + + /* Assign Data pointer */ + S->pData = pData; +} + +/** + @} end of MatrixInit group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c new file mode 100644 index 0000000..90bc06d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f16.c @@ -0,0 +1,891 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f16.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float16_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float16_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + float16_t *pTmpA, *pTmpB; + + _Float16 in = 0.0f16; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + uint32_t blkCnt; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* + * Working pointer for destination matrix + */ + pOutT1 = pOut; + /* + * Loop over the number of rows + */ + rowCnt = numRows; + /* + * Making the destination matrix as identity matrix + */ + while (rowCnt > 0U) + { + /* + * Writing all zeroes in lower triangle of the destination matrix + */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + /* + * Writing all ones in the diagonal of the destination matrix + */ + *pOutT1++ = 1.0f16; + /* + * Writing all zeroes in upper triangle of the destination matrix + */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + /* + * Decrement the loop counter + */ + rowCnt--; + } + + /* + * Loop over the number of columns of the input matrix. + * All the elements in each column are processed by the row operations + */ + loopCnt = numCols; + /* + * Index modifier to navigate through the columns + */ + l = 0U; + while (loopCnt > 0U) + { + /* + * Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. + */ + + /* + * Working pointer for the input matrix that points + * * to the pivot element of the particular row + */ + pInT1 = pIn + (l * numCols); + /* + * Working pointer for the destination matrix that points + * * to the pivot element of the particular row + */ + pOutT1 = pOut + (l * numCols); + /* + * Temporary variable to hold the pivot value + */ + in = *pInT1; + + + /* + * Check if the pivot element is zero + */ + if ((_Float16)*pInT1 == 0.0f16) + { + /* + * Loop over the number rows present below + */ + for (i = 1U; i < numRows-l; i++) + { + /* + * Update the input and destination pointers + */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + /* + * Check if there is a non zero pivot element to + * * replace in the rows below + */ + if ((_Float16)*pInT2 != 0.0f16) + { + f16x8_t vecA, vecB; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + pTmpA = pInT1; + pTmpB = pInT2; + blkCnt = (numCols - l) >> 3; + while (blkCnt > 0U) + { + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_f16(pTmpB, vecA); + vstrhq_f16(pTmpA, vecB); + + pTmpA += 8; + pTmpB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_p_f16(pTmpB, vecA, p0); + vstrhq_p_f16(pTmpA, vecB, p0); + } + + pInT1 += numCols - l; + pInT2 += numCols - l; + pTmpA = pOutT1; + pTmpB = pOutT2; + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_f16(pTmpB, vecA); + vstrhq_f16(pTmpA, vecB); + pTmpA += 8; + pTmpB += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecB = vldrhq_f16(pTmpB); + vstrhq_p_f16(pTmpB, vecA, p0); + vstrhq_p_f16(pTmpA, vecB, p0); + } + + pOutT1 += numCols; + pOutT2 += numCols; + /* + * Flag to indicate whether exchange is done or not + */ + flag = 1U; + + /* + * Break after exchange is done + */ + break; + } + + } + } + + /* + * Update the status if the matrix is singular + */ + if ((flag != 1U) && (in == 0.0f16)) + { + return ARM_MATH_SINGULAR; + } + + /* + * Points to the pivot row of input and destination matrices + */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* + * Temporary pointers to the pivot row pointers + */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* + * Pivot element of the row + */ + in = *(pIn + (l * numCols)); + + pTmpA = pInT1; + + f16x8_t invIn = vdupq_n_f16(1.0f16 / in); + + blkCnt = (numCols - l) >> 3; + f16x8_t vecA; + while (blkCnt > 0U) + { + *(f16x8_t *) pTmpA = *(f16x8_t *) pTmpA * invIn; + pTmpA += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + + vecA = vldrhq_f16(pTmpA); + vecA = vecA * invIn; + vstrhq_p_f16(pTmpA, vecA, p0); + } + + pInT1 += numCols - l; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + + pTmpA = pOutT1; + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + *(f16x8_t *) pTmpA = *(f16x8_t *) pTmpA *invIn; + pTmpA += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecA = vldrhq_f16(pTmpA); + vecA = vecA * invIn; + vstrhq_p_f16(pTmpA, vecA, p0); + } + + pOutT1 += numCols; + + /* + * Replace the rows with the sum of that row and a multiple of row i + * * so that each new element in column i above row i is zero. + */ + + /* + * Temporary pointers for input and destination matrices + */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* + * Check for the pivot element + */ + if (i == l) + { + /* + * If the processing element is the pivot element, + * only the columns to the right are to be processed + */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* + * Element of the reference row + */ + + /* + * Working pointers for input and destination pivot rows + */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + /* + * Loop over the number of columns to the right of the pivot element, + * to replace the elements in the input matrix + */ + + in = *pInT1; + f16x8_t tmpV = vdupq_n_f16(in); + + blkCnt = (numCols - l) >> 3; + while (blkCnt > 0U) + { + f16x8_t vec1, vec2; + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrhq_f16(pInT1); + vec2 = vldrhq_f16(pPRT_in); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_f16(pInT1, vec1); + pPRT_in += 8; + pInT1 += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 7; + if (blkCnt > 0U) + { + f16x8_t vec1, vec2; + mve_pred16_t p0 = vctp16q(blkCnt); + + vec1 = vldrhq_f16(pInT1); + vec2 = vldrhq_f16(pPRT_in); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_p_f16(pInT1, vec1, p0); + pInT1 += blkCnt; + } + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vec1, vec2; + + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrhq_f16(pOutT1); + vec2 = vldrhq_f16(pPRT_pDst); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_f16(pOutT1, vec1); + pPRT_pDst += 8; + pOutT1 += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + f16x8_t vec1, vec2; + mve_pred16_t p0 = vctp16q(blkCnt); + + vec1 = vldrhq_f16(pOutT1); + vec2 = vldrhq_f16(pPRT_pDst); + vec1 = vfmsq_f16(vec1, tmpV, vec2); + vstrhq_p_f16(pOutT1, vec1, p0); + + pInT2 += blkCnt; + pOutT1 += blkCnt; + } + } + /* + * Increment the temporary input pointer + */ + pInT1 = pInT1 + l; + } + /* + * Increment the input pointer + */ + pIn++; + /* + * Decrement the loop counter + */ + loopCnt--; + /* + * Increment the index modifier + */ + l++; + } + + /* + * Set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if ((_Float16)pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_inverse_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float16_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float16_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + _Float16 Xchg, in = 0.0f16, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f16; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f16; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + /* Check if the pivot element is zero */ + if ((_Float16)*pInT1 == 0.0f16) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if ((_Float16)*pInT2 != 0.0f16) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f16)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = (_Float16)in1 - ((_Float16)in * (_Float16)*pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = (_Float16)in1 - ((_Float16)in * (_Float16)*pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && ((_Float16)in == 0.0f16)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if ((_Float16)pIn[i] != 0.0f16) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c new file mode 100644 index 0000000..b0ef760 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c @@ -0,0 +1,1570 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f32.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixInv Matrix Inverse + + Computes the inverse of a matrix. + + The inverse is defined only if the input matrix is square and non-singular (the determinant is non-zero). + The function checks that the input and output matrices are square and of the same size. + + Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix + inversion of floating-point matrices. + + @par Algorithm + The Gauss-Jordan method is used to find the inverse. + The algorithm performs a sequence of elementary row-operations until it + reduces the input matrix to an identity matrix. Applying the same sequence + of elementary row-operations to an identity matrix yields the inverse matrix. + If the input matrix is singular, then the algorithm terminates and returns error status + ARM_MATH_SINGULAR. + \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method" + */ + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + float32_t *pTmpA, *pTmpB; + + float32_t in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + uint32_t blkCnt; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* + * Working pointer for destination matrix + */ + pOutT1 = pOut; + /* + * Loop over the number of rows + */ + rowCnt = numRows; + /* + * Making the destination matrix as identity matrix + */ + while (rowCnt > 0U) + { + /* + * Writing all zeroes in lower triangle of the destination matrix + */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + /* + * Writing all ones in the diagonal of the destination matrix + */ + *pOutT1++ = 1.0f; + /* + * Writing all zeroes in upper triangle of the destination matrix + */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + /* + * Decrement the loop counter + */ + rowCnt--; + } + + /* + * Loop over the number of columns of the input matrix. + * All the elements in each column are processed by the row operations + */ + loopCnt = numCols; + /* + * Index modifier to navigate through the columns + */ + l = 0U; + while (loopCnt > 0U) + { + /* + * Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. + */ + + /* + * Working pointer for the input matrix that points + * * to the pivot element of the particular row + */ + pInT1 = pIn + (l * numCols); + /* + * Working pointer for the destination matrix that points + * * to the pivot element of the particular row + */ + pOutT1 = pOut + (l * numCols); + /* + * Temporary variable to hold the pivot value + */ + in = *pInT1; + + + /* + * Check if the pivot element is zero + */ + if (*pInT1 == 0.0f) + { + /* + * Loop over the number rows present below + */ + for (i = 1U; i < numRows-l; i++) + { + /* + * Update the input and destination pointers + */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + /* + * Check if there is a non zero pivot element to + * * replace in the rows below + */ + if (*pInT2 != 0.0f) + { + f32x4_t vecA, vecB; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + pTmpA = pInT1; + pTmpB = pInT2; + blkCnt = (numCols - l) >> 2; + while (blkCnt > 0U) + { + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_f32(pTmpB, vecA); + vstrwq_f32(pTmpA, vecB); + + pTmpA += 4; + pTmpB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_p_f32(pTmpB, vecA, p0); + vstrwq_p_f32(pTmpA, vecB, p0); + } + + pInT1 += numCols - l; + pInT2 += numCols - l; + pTmpA = pOutT1; + pTmpB = pOutT2; + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_f32(pTmpB, vecA); + vstrwq_f32(pTmpA, vecB); + pTmpA += 4; + pTmpB += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecB = vldrwq_f32(pTmpB); + vstrwq_p_f32(pTmpB, vecA, p0); + vstrwq_p_f32(pTmpA, vecB, p0); + } + + pOutT1 += numCols; + pOutT2 += numCols; + /* + * Flag to indicate whether exchange is done or not + */ + flag = 1U; + + /* + * Break after exchange is done + */ + break; + } + + } + } + + /* + * Update the status if the matrix is singular + */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* + * Points to the pivot row of input and destination matrices + */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* + * Temporary pointers to the pivot row pointers + */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* + * Pivot element of the row + */ + in = *(pIn + (l * numCols)); + + pTmpA = pInT1; + + f32x4_t invIn = vdupq_n_f32(1.0f / in); + + blkCnt = (numCols - l) >> 2; + f32x4_t vecA; + while (blkCnt > 0U) + { + *(f32x4_t *) pTmpA = *(f32x4_t *) pTmpA * invIn; + pTmpA += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + + vecA = vldrwq_f32(pTmpA); + vecA = vecA * invIn; + vstrwq_p_f32(pTmpA, vecA, p0); + } + + pInT1 += numCols - l; + /* + * Loop over number of columns + * * to the right of the pilot element + */ + + pTmpA = pOutT1; + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + *(f32x4_t *) pTmpA = *(f32x4_t *) pTmpA *invIn; + pTmpA += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecA = vldrwq_f32(pTmpA); + vecA = vecA * invIn; + vstrwq_p_f32(pTmpA, vecA, p0); + } + + pOutT1 += numCols; + + /* + * Replace the rows with the sum of that row and a multiple of row i + * * so that each new element in column i above row i is zero. + */ + + /* + * Temporary pointers for input and destination matrices + */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* + * Check for the pivot element + */ + if (i == l) + { + /* + * If the processing element is the pivot element, + * only the columns to the right are to be processed + */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* + * Element of the reference row + */ + + /* + * Working pointers for input and destination pivot rows + */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + /* + * Loop over the number of columns to the right of the pivot element, + * to replace the elements in the input matrix + */ + + in = *pInT1; + f32x4_t tmpV = vdupq_n_f32(in); + + blkCnt = (numCols - l) >> 2; + while (blkCnt > 0U) + { + f32x4_t vec1, vec2; + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrwq_f32(pInT1); + vec2 = vldrwq_f32(pPRT_in); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_f32(pInT1, vec1); + pPRT_in += 4; + pInT1 += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numCols - l) & 3; + if (blkCnt > 0U) + { + f32x4_t vec1, vec2; + mve_pred16_t p0 = vctp32q(blkCnt); + + vec1 = vldrwq_f32(pInT1); + vec2 = vldrwq_f32(pPRT_in); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_p_f32(pInT1, vec1, p0); + pInT1 += blkCnt; + } + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vec1, vec2; + + /* + * Replace the element by the sum of that row + * and a multiple of the reference row + */ + vec1 = vldrwq_f32(pOutT1); + vec2 = vldrwq_f32(pPRT_pDst); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_f32(pOutT1, vec1); + pPRT_pDst += 4; + pOutT1 += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + f32x4_t vec1, vec2; + mve_pred16_t p0 = vctp32q(blkCnt); + + vec1 = vldrwq_f32(pOutT1); + vec2 = vldrwq_f32(pPRT_pDst); + vec1 = vfmsq_f32(vec1, tmpV, vec2); + vstrwq_p_f32(pOutT1, vec1, p0); + + pInT2 += blkCnt; + pOutT1 += blkCnt; + } + } + /* + * Increment the temporary input pointer + */ + pInT1 = pInT1 + l; + } + /* + * Increment the input pointer + */ + pIn++; + /* + * Decrement the loop counter + */ + loopCnt--; + /* + * Increment the index modifier + */ + l++; + } + + /* + * Set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + float32x4_t vec1; + float32x4_t vec2; + float32x4_t tmpV; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) + || (pSrc->numRows != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement the loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + tmpV = vdupq_n_f32(1.0f/in); + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT1); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT1, vec1); + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + vec1 = vld1q_f32(pInT2); + + vec1 = vmulq_f32(vec1, tmpV); + vst1q_f32(pInT2, vec1); + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + tmpV = vdupq_n_f32(in); + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l) >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT1); + vec2 = vld1q_f32(pPRT_in); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT1, vec1); + pPRT_in += 4; + pInT1 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = (numCols - l) & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols >> 2; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + vec1 = vld1q_f32(pInT2); + vec2 = vld1q_f32(pPRT_pDst); + vec1 = vmlsq_f32(vec1, tmpV, vec2); + vst1q_f32(pInT2, vec1); + pPRT_pDst += 4; + pInT2 += 4; + + /* Decrement the loop counter */ + j--; + } + + /* Tail */ + j = numCols & 3; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement the loop counter */ + j--; + } + + } + + /* Increment the temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement the loop counter */ + k--; + + /* Increment the pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float32_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + + float32_t Xchg, in = 0.0f, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float32_t Xchg, in = 0.0f; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0f; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0f; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0f) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0f) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0f)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0f)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0f) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c new file mode 100644 index 0000000..bf99a79 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c @@ -0,0 +1,644 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_inverse_f64.c + * Description: Floating-point matrix inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + @brief Floating-point (64 bit) matrix inverse. + @param[in] pSrc points to input matrix structure. The source matrix is modified by the function. + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible) + */ + +arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */ + float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */ + float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */ + uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */ + uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */ + +#if defined (ARM_MATH_DSP) + + float64_t Xchg, in = 0.0, in1; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, k,l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ + * | a11 a12 | 1 0 | | X11 X12 | + * | | | = | | + * |_ a21 a22 | 0 1 _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc). + * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + + for (i = 1U; i < numRows - l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + j = numCols - l; + + while (j > 0U) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Exchange the row elements of the destination matrix */ + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + + /* Decrement loop counter */ + j--; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + + + /* Decrement loop counter */ + } + } + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pInT2 = pPivotRowDst; + + /* Pivot element of the row */ + in = *pPivotRowIn; + + /* Loop over number of columns + * to the right of the pilot element */ + j = (numCols - l); + + while (j > 0U) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + in1 = *pInT1; + *pInT1++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Loop over number of columns of the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + in1 = *pInT2; + *pInT2++ = in1 / in; + + /* Decrement the loop counter */ + j--; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pInT2 = pOut; + + /* index used to check for pivot element */ + i = 0U; + + /* Loop over number of rows */ + /* to be replaced by the sum of that row and a multiple of row i */ + k = numRows; + + while (k > 0U) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + + pInT2 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + j = (numCols - l); + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT1; + *pInT1++ = in1 - (in * *pPRT_in++); + + /* Decrement the loop counter */ + j--; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + j = numCols; + + while (j > 0U) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + in1 = *pInT2; + *pInT2++ = in1 - (in * *pPRT_pDst++); + + /* Decrement loop counter */ + j--; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + + /* Decrement loop counter */ + k--; + + /* Increment pivot index */ + i++; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + + +#else + + float64_t Xchg, in = 0.0; /* Temporary input values */ + uint32_t i, rowCnt, flag = 0U, j, loopCnt, l; /* loop counters */ + arm_status status; /* status of matrix inverse */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pDst->numRows != pDst->numCols) || + (pSrc->numRows != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + /*-------------------------------------------------------------------------------------------------------------- + * Matrix Inverse can be solved using elementary row operations. + * + * Gauss-Jordan Method: + * + * 1. First combine the identity matrix and the input matrix separated by a bar to form an + * augmented matrix as follows: + * _ _ _ _ _ _ _ _ + * | | a11 a12 | | | 1 0 | | | X11 X12 | + * | | | | | | | = | | + * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _| + * + * 2. In our implementation, pDst Matrix is used as identity matrix. + * + * 3. Begin with the first row. Let i = 1. + * + * 4. Check to see if the pivot for row i is zero. + * The pivot is the element of the main diagonal that is on the current row. + * For instance, if working with row i, then the pivot element is aii. + * If the pivot is zero, exchange that row with a row below it that does not + * contain a zero in column i. If this is not possible, then an inverse + * to that matrix does not exist. + * + * 5. Divide every element of row i by the pivot. + * + * 6. For every row below and row i, replace that row with the sum of that row and + * a multiple of row i so that each new element in column i below row i is zero. + * + * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros + * for every element below and above the main diagonal. + * + * 8. Now an identical matrix is formed to the left of the bar(input matrix, src). + * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst). + *----------------------------------------------------------------------------------------------------------------*/ + + /* Working pointer for destination matrix */ + pOutT1 = pOut; + + /* Loop over the number of rows */ + rowCnt = numRows; + + /* Making the destination matrix as identity matrix */ + while (rowCnt > 0U) + { + /* Writing all zeroes in lower triangle of the destination matrix */ + j = numRows - rowCnt; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Writing all ones in the diagonal of the destination matrix */ + *pOutT1++ = 1.0; + + /* Writing all zeroes in upper triangle of the destination matrix */ + j = rowCnt - 1U; + while (j > 0U) + { + *pOutT1++ = 0.0; + j--; + } + + /* Decrement loop counter */ + rowCnt--; + } + + /* Loop over the number of columns of the input matrix. + All the elements in each column are processed by the row operations */ + loopCnt = numCols; + + /* Index modifier to navigate through the columns */ + l = 0U; + + while (loopCnt > 0U) + { + /* Check if the pivot element is zero.. + * If it is zero then interchange the row with non zero row below. + * If there is no non zero element to replace in the rows below, + * then the matrix is Singular. */ + + /* Working pointer for the input matrix that points + * to the pivot element of the particular row */ + pInT1 = pIn + (l * numCols); + + /* Working pointer for the destination matrix that points + * to the pivot element of the particular row */ + pOutT1 = pOut + (l * numCols); + + /* Temporary variable to hold the pivot value */ + in = *pInT1; + + /* Check if the pivot element is zero */ + if (*pInT1 == 0.0) + { + /* Loop over the number rows present below */ + for (i = 1U; i < numRows-l; i++) + { + /* Update the input and destination pointers */ + pInT2 = pInT1 + (numCols * i); + pOutT2 = pOutT1 + (numCols * i); + + /* Check if there is a non zero pivot element to + * replace in the rows below */ + if (*pInT2 != 0.0) + { + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Exchange the row elements of the input matrix */ + Xchg = *pInT2; + *pInT2++ = *pInT1; + *pInT1++ = Xchg; + } + + for (j = 0U; j < numCols; j++) + { + Xchg = *pOutT2; + *pOutT2++ = *pOutT1; + *pOutT1++ = Xchg; + } + + /* Flag to indicate whether exchange is done or not */ + flag = 1U; + + /* Break after exchange is done */ + break; + } + } + } + + + /* Update the status if the matrix is singular */ + if ((flag != 1U) && (in == 0.0)) + { + return ARM_MATH_SINGULAR; + } + + /* Points to the pivot row of input and destination matrices */ + pPivotRowIn = pIn + (l * numCols); + pPivotRowDst = pOut + (l * numCols); + + /* Temporary pointers to the pivot row pointers */ + pInT1 = pPivotRowIn; + pOutT1 = pPivotRowDst; + + /* Pivot element of the row */ + in = *(pIn + (l * numCols)); + + /* Loop over number of columns + * to the right of the pilot element */ + for (j = 0U; j < (numCols - l); j++) + { + /* Divide each element of the row of the input matrix + * by the pivot element */ + *pInT1 = *pInT1 / in; + pInT1++; + } + for (j = 0U; j < numCols; j++) + { + /* Divide each element of the row of the destination matrix + * by the pivot element */ + *pOutT1 = *pOutT1 / in; + pOutT1++; + } + + /* Replace the rows with the sum of that row and a multiple of row i + * so that each new element in column i above row i is zero.*/ + + /* Temporary pointers for input and destination matrices */ + pInT1 = pIn; + pOutT1 = pOut; + + for (i = 0U; i < numRows; i++) + { + /* Check for the pivot element */ + if (i == l) + { + /* If the processing element is the pivot element, + only the columns to the right are to be processed */ + pInT1 += numCols - l; + pOutT1 += numCols; + } + else + { + /* Element of the reference row */ + in = *pInT1; + + /* Working pointers for input and destination pivot rows */ + pPRT_in = pPivotRowIn; + pPRT_pDst = pPivotRowDst; + + /* Loop over the number of columns to the right of the pivot element, + to replace the elements in the input matrix */ + for (j = 0U; j < (numCols - l); j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pInT1 = *pInT1 - (in * *pPRT_in++); + pInT1++; + } + + /* Loop over the number of columns to + replace the elements in the destination matrix */ + for (j = 0U; j < numCols; j++) + { + /* Replace the element by the sum of that row + and a multiple of the reference row */ + *pOutT1 = *pOutT1 - (in * *pPRT_pDst++); + pOutT1++; + } + + } + + /* Increment temporary input pointer */ + pInT1 = pInT1 + l; + } + + /* Increment the input pointer */ + pIn++; + + /* Decrement the loop counter */ + loopCnt--; + + /* Increment the index modifier */ + l++; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + if ((flag != 1U) && (in == 0.0)) + { + pIn = pSrc->pData; + for (i = 0; i < numRows * numCols; i++) + { + if (pIn[i] != 0.0) + break; + } + + if (i == numRows * numCols) + status = ARM_MATH_SINGULAR; + } + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c new file mode 100644 index 0000000..1d3586c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f32.c @@ -0,0 +1,509 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f32.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + { \ + int cnt = n; \ + \ + for(int w=0;w < n; w+=4) \ + { \ + f32x4_t tmpa,tmpb; \ + mve_pred16_t p0 = vctp32q(cnt); \ + \ + tmpa=vldrwq_z_f32(&A[i*n + w],p0);\ + tmpb=vldrwq_z_f32(&A[j*n + w],p0);\ + \ + vstrwq_p(&A[i*n + w], tmpb, p0); \ + vstrwq_p(&A[j*n + w], tmpa, p0); \ + \ + cnt -= 4; \ + } \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(int w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + int cnt = n; + uint16x8_t vecP; + + for(int k=0;k < n; k+=8) + { + mve_pred16_t p0; + p0 = vctp16q(cnt); + + vecP = vidupq_u16((uint16_t)k, 1); + + vstrhq_p(&pp[k], vecP, p0); + + cnt -= 8; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + for(int r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + float32_t invA; + + invA = 1.0f / a; + + int32x4_t vecOffs; + int w; + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vmulq_n_s32(vecOffs,n); + + for(w=k+1; wpData[row*n+col], zero, p0); + + cnt -= 4; + } + } + } + + for(int row=0; row < n;row++) + { + mve_pred16_t p0; + int cnt= n-row-1; + f32x4_t zero=vdupq_n_f32(0.0f); + + for(int col=row+1; col < n;col+=4) + { + p0 = vctp32q(cnt); + + vstrwq_p(&pl->pData[row*n+col], zero, p0); + + cnt -= 4; + } + } + + for(int d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#else + +/// @private +#define SWAP_ROWS_F32(A,i,j) \ + for(w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } + +/// @private +#define SWAP_COLS_F32(A,i,j) \ + for(w=0;w < n; w++) \ + { \ + float32_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ +arm_status arm_mat_ldlt_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pl, + arm_matrix_instance_f32 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float32_t *pA; + int row,d; + + memset(pd->pData,0,sizeof(float32_t)*n*n); + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float32_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float32_t m=F32_MIN,a; + int j=k; + + + int r; + int w; + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F32(pA,k,j); + SWAP_COLS_F32(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabsf(a) < 1.0e-8f) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixChol group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c new file mode 100644 index 0000000..8f7331d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_ldlt_f64.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_ldl_f64.c + * Description: Floating-point LDL decomposition + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" +#include + + + +/// @private +#define SWAP_ROWS_F64(A,i,j) \ +{ \ + int w; \ + for(w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[i*n + w]; \ + A[i*n + w] = A[j*n + w];\ + A[j*n + w] = tmp; \ + } \ +} + +/// @private +#define SWAP_COLS_F64(A,i,j) \ +{ \ + int w; \ + for(w=0;w < n; w++) \ + { \ + float64_t tmp; \ + tmp = A[w*n + i]; \ + A[w*n + i] = A[w*n + j];\ + A[w*n + j] = tmp; \ + } \ +} + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixChol + @{ + */ + +/** + * @brief Floating-point LDL^t decomposition of positive semi-definite matrix. + * @param[in] pSrc points to the instance of the input floating-point matrix structure. + * @param[out] pl points to the instance of the output floating-point triangular matrix structure. + * @param[out] pd points to the instance of the output floating-point diagonal matrix structure. + * @param[out] pp points to the instance of the output floating-point permutation vector. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + - \ref ARM_MATH_DECOMPOSITION_FAILURE : Input matrix cannot be decomposed + * @par + * Computes the LDL^t decomposition of a matrix A such that P A P^t = L D L^t. + */ + +arm_status arm_mat_ldlt_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pl, + arm_matrix_instance_f64 * pd, + uint16_t * pp) +{ + + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pSrc->numCols) || + (pl->numRows != pl->numCols) || + (pd->numRows != pd->numCols) || + (pl->numRows != pd->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + const int n=pSrc->numRows; + int fullRank = 1, diag,k; + float64_t *pA; + + memset(pd->pData,0,sizeof(float64_t)*n*n); + + memcpy(pl->pData,pSrc->pData,n*n*sizeof(float64_t)); + pA = pl->pData; + + for(k=0;k < n; k++) + { + pp[k] = k; + } + + + for(k=0;k < n; k++) + { + /* Find pivot */ + float64_t m=F64_MIN,a; + int w,r,j=k; + + + for(r=k;r m) + { + m = pA[r*n+r]; + j = r; + } + } + + if(j != k) + { + SWAP_ROWS_F64(pA,k,j); + SWAP_COLS_F64(pA,k,j); + } + + + pp[k] = j; + + a = pA[k*n+k]; + + if (fabs(a) < 1.0e-18) + { + + fullRank = 0; + break; + } + + for(w=k+1;wpData[row*n+col]=0.0; + } + } + } + } + + { + int row; + for(row=0; row < n;row++) + { + int col; + for(col=row+1; col < n;col++) + { + pl->pData[row*n+col] = 0.0; + } + } + } + + { + int d; + for(d=0; d < diag;d++) + { + pd->pData[d*n+d] = pl->pData[d*n+d]; + pl->pData[d*n+d] = 1.0; + } + } + + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixChol group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c new file mode 100644 index 0000000..3d3e820 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f16.c @@ -0,0 +1,763 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f16.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_2x2_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 2, 2, 0, 0, 2, 2 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 0, 1, 0, 1, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + /* + * load {a00 a00 a10 a10 x x x x } + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b00 b01 x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 + * a10 b00 a10 b01 + * x x + * x x } + */ + vecDst = vmulq(vecInA, vecInB); + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a11 a11 x x x x} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 2); + /* + * load {b10, b11, b10, b11, x x x x } + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 + * a10 b00 + a11 b10 a10 b01 + a11 b11 + * x x + * x x } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + mve_pred16_t p0 = vctp16q(2*2); + /* + * Store the result in the destination buffer + * (lower half of the vector) + */ + vstrhq_p(pOut, vecDst, p0); + + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_3x3_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + static const uint16_t offsetA[8] = { 0, 0, 0, 3, 3, 3, 6, 6 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 0, 1, 2, 0, 1 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a10 a10 a10 a20 a20} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b00 b01 b02 b00 b01} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 + * a10 b00 a10 b01 a10 b02 + * a20 b00 a20 b01} + */ + vecDst = vmulq(vecInA, vecInB); + + /* + * move to 2nd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a01 a01 a01 a11 a11 a11 a21 a21} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b10, b11, b12, b10, b11, b12, b10, b11} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 + * a20 b00 + a21 b10 a20 b01 + a21 b11 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + /* + * move to 3rd column of matrix A + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 1); + /* + * load {a02 a02 a02 a12 a12 a12 a22 a22} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 3); + /* + * load {b20, b21, b22, b20, b21, b22, b20, b21} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * {a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22}, + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22}, + * a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 } + */ + vecDst = vfmaq(vecDst, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst); pOut += 8; + + /* last element computed in scalar mode + * a20 b02 + a21 b12 + a22 b22 + */ + _Float16 * pA = (_Float16 *)pSrcA->pData; + _Float16 * pB = (_Float16 *)pSrcB->pData; + *pOut = pA[2*3] * pB[2] + pA[2*3+1] * pB[3+2] + pA[2*3+2] * pB[2*3+2]; + + return (ARM_MATH_SUCCESS); +} + + + + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_f16_4x4_mve( + const arm_matrix_instance_f16 *pSrcA, + const arm_matrix_instance_f16 *pSrcB, + arm_matrix_instance_f16 *pDst) +{ + /* offsetA allows to read and duplicate 2 successive column elements of A */ + static const uint16_t offsetA[8] = { 0, 0, 0, 0, 4, 4, 4, 4 }; + /* offsetB allows to read and duplicate 1 row of B */ + static const uint16_t offsetB[8] = { 0, 1, 2, 3, 0, 1, 2, 3 }; + uint16x8_t vecOffsA, vecOffsB; + f16x8_t vecInA, vecInB, vecDst0, vecDst1; + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + /* + * load initial offsets + */ + vecOffsA = vldrhq_u16((uint16_t const *) offsetA); + vecOffsB = vldrhq_u16((uint16_t const *) offsetB); + + /* + * load {a00 a00 a00 a00 a10 a10 a10 a10} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * load {b00 b01 b02 b03 b00 b01 b02 b03} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 a00 b01 a00 b02 a00 b03 + * a10 b00 a10 b01 a10 b02 a10 b03 } + */ + vecDst0 = vmulq(vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a20 a20 a20 a20 a30 a30 a30 a30} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * { a20 b00 a20 b01 a20 b02 a20 b03 + * a30 b00 a30 b01 a30 b02 + a31 b12 } + */ + vecDst1 = vmulq(vecInA, vecInB); + /* + * rewind back to top half of the A matrix (2nd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a01 a01 a01 a01 a11 a11 a11 a11} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b10, b11, b12, b13, b10, b11, b12, b13} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 a00 b01 + a01 b11 a00 b02 + a01 b12 a00 b03 + a01 b13 + * a10 b00 + a11 b10 a10 b01 + a11 b11 a10 b02 + a11 b12 a10 b03 + a11 b13 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows (2nd half of matrix) + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a21 a21 a21 a21 a31 a31 a31 a31} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 a20 b01 + a21 b11 a20 b02 + a21 b12 a20 b03 + a21 b13 + * a30 b00 + a31 b10 a30 b01 + a31 b11 a30 b02 + a31 b12 a30 b03 + a31 b13 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (3rd column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a02 a02 a02 a02 a12 a12 a12 a12} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b20, b21, b22, b23, b20, b21, b22, b23} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 + a01 b10 + a02 b20 a00 b01 + a01 b11 + a02 b21 a00 b02 + a01 b12 + a02 b22 a00 b03 + a01 b13 + a02 b23 + * a10 b00 + a11 b10 + a12 b20 a10 b01 + a11 b11 + a12 b21 a10 b02 + a11 b12 + a12 b22 a10 b03 + a11 b13 + a12 b23 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + + /* + * load {a22 a22 a22 a22 a32 a32 a32 a32} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 + a21 b10 + a22 b20 a20 b01 + a21 b11 + a22 b21 a20 b02 + a21 b12 + a22 b22 a20 b03 + a21 b13 + a22 b23 + * a30 b00 + a31 b10 + a32 b20 a30 b01 + a31 b11 + a32 b21 a30 b02 + a31 b12 + a32 b22 a30 b03 + a31 b13 + a32 b23 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * rewind back to top half of the A matrix (4th column) + */ + vecOffsA = vsubq(vecOffsA, (uint16_t) 7); + /* + * load {a03 a03 a03 a03 a13 a13 a13 a13} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * move to next B row + */ + vecOffsB = vaddq_n_u16(vecOffsB, (uint16_t) 4); + /* + * load {b30, b31, b32, b33, b30, b31, b32, b33} + */ + vecInB = vldrhq_gather_shifted_offset((float16_t const *) pSrcB->pData, vecOffsB); + /* + * { a00 b00 +...+ a03 b30, a00 b01 +...+ a03 b31, a00 b02 +...+ a03 b32, a00 b03 +...+ a03 b33 + * a10 b00 +...+ a13 b30, a10 b01 +...+ a13 b31, a10 b02 +...+ a13 b32, a10 b03 +...+ a13 b33 } + */ + vecDst0 = vfmaq(vecDst0, vecInA, vecInB); + /* + * jump 2 x A rows + */ + vecOffsA = vaddq_n_u16(vecOffsA, (uint16_t) 8); + /* + * load {a23 a23 a23 a23 a33 a33 a33 a33} + */ + vecInA = vldrhq_gather_shifted_offset((float16_t const *) pSrcA->pData, vecOffsA); + /* + * {a20 b00 +...+ a23 b30, a20 b01 +...+ a23 b31, a20 b02 +...+ a23 b32, a20 b03 +...+ a23 b33 + * a30 b00 +...+ a33 b30, a30 b01 +...+ a33 b31, a30 b02 +...+ a33 b32, a30 b03 +...+ a33 b33 } + */ + vecDst1 = vfmaq(vecDst1, vecInA, vecInB); + + /* + * Store the result in the destination buffer + */ + vst1q(pOut, vecDst0); pOut += 8; + vst1q(pOut, vecDst1); + + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + int i; + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return(ARM_MATH_SIZE_MISMATCH); + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ +{ + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_f16_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f16_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f16_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA / 4; + while(i > 0) + { + float16_t *pInA0, *pInA1, *pInA2, *pInA3; + float16_t *pInB0; + float16_t *pOut0, *pOut1, *pOut2, *pOut3; + f16x8_t vecMac0, vecMac1, vecMac2, vecMac3; + f16x8_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3..., bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + vst1q(pOut1, vecMac1); pOut1 += 8; + vst1q(pOut2, vecMac2); pOut2 += 8; + vst1q(pOut3, vecMac3); pOut3 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + vecMac1 = vdupq_n_f16(0.0f16); + vecMac2 = vdupq_n_f16(0.0f16); + vecMac3 = vdupq_n_f16(0.0f16); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..bi,4n+colBLeft-1, 0, ..} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + vstrhq_p_f16(pOut1, vecMac1, p0); + vstrhq_p_f16(pOut2, vecMac2, p0); + vstrhq_p_f16(pOut3, vecMac3, p0); + } + + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + do + { + float16_t *pInA0; + float16_t *pInB0; + float16_t *pOut0; + f16x8_t vecInB; + f16x8_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + int k = numColsB >> 3; + while(k > 0) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3, ...bi,4n+7} + */ + vecInB = *(f16x8_t *)pInB0; /* vldrhq_f16(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x 8 block) in the destination buffer */ + vst1q(pOut0, vecMac0); pOut0 += 8; + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 8; + k--; + } + + int colBLeft = numColsB & 7; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp16q(colBLeft); + + vecMac0 = vdupq_n_f16(0.0f16); + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, ..., bi,4n+colBLeft, 0, ...} + */ + vecInB = vldrhq_z_f16(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrhq_p_f16(pOut0, vecMac0, p0); + } + + pInA += 1 * numColsA; + pOut += 1 * numColsB; + } + while (--i); + } + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); + } +} +#else + + +arm_status arm_mat_mult_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + _Float16 sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f16; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (_Float16)*pIn1++ * (_Float16)*pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c new file mode 100644 index 0000000..d1fd9ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c @@ -0,0 +1,1001 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f32.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +#if defined(ARM_MATH_NEON) +#define GROUPOFROWS 8 +#endif + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_f32_2x2_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + /* {a00, a00, a10, a10} */ + static const uint32_t offsetA0[4] = { 0, 0, 2, 2 }; + /* {b00, b01, b00, b01} */ + static const uint32_t offsetB0[4] = { 0, 1, 0, 1 }; + /* {a01, a01, a11, a11} */ + static const uint32_t offsetA1[4] = { 1, 1, 3, 3 }; + /* {b10, b11, b10, b11} */ + static const uint32_t offsetB1[4] = { 2, 3, 2, 3 }; + + uint32x4_t vecOffsA, vecOffsB; + f32x4_t vecInA, vecInB, vecDst; + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA0); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB0); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vmulq(vecInA, vecInB); + + vecOffsA = vldrwq_u32((uint32_t const *) offsetA1); + vecOffsB = vldrwq_u32((uint32_t const *) offsetB1); + + vecInA = vldrwq_gather_shifted_offset((float32_t const *) pSrcA->pData, vecOffsA); + vecInB = vldrwq_gather_shifted_offset((float32_t const *) pSrcB->pData, vecOffsB); + + vecDst = vfmaq(vecDst, vecInA, vecInB); + + vstrwq_f32(pDst->pData, vecDst); + + return (ARM_MATH_SUCCESS); + +} + + +/* + * A = {{a00, a01, a02}, + * {a10, a11, a12}, + * {a20, a21, a22}} + * B = {{b00, b01, b02}, + * {b10, b11, b12}, + * {b20, b21, b22}} + * + * Dst = {{a00 b00 + a01 b10 + a02 b20, a00 b01 + a01 b11 + a02 b21, a00 b02 + a01 b12 + a02 b22}, + * {a10 b00 + a11 b10 + a12 b20, a10 b01 + a11 b11 + a12 b21, a10 b02 + a11 b12 + a12 b22}, + * {a20 b00 + a21 b10 + a22 b20, a20 b01 + a21 b11 + a22 b21, a20 b02 + a21 b12 + a22 b22}} + */ +__STATIC_INLINE arm_status arm_mat_mult_f32_3x3_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2; + f32x4_t vecMac0, vecMac1, vecMac2; + f32x4_t vecInB; + float32_t const *pSrBVec; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM3; + pInA2 = pInA1 + MATRIX_DIM3; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + /* + * load {b0,0, b0,1, b0,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + /* + * load {b1,0, b1,1, b1,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + /* + * load {b2,0, b2,1 , b2,2, 0} + */ + vecInB = vldrwq_z_f32(pSrBVec, p0); + pSrBVec += MATRIX_DIM3; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + + /* partial vector stores */ + vstrwq_p_f32(pOut, vecMac0, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac1, p0); + pOut += MATRIX_DIM3; + vstrwq_p_f32(pOut, vecMac2, p0); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + + +__STATIC_INLINE arm_status arm_mat_mult_f32_4x4_mve( + const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, + arm_matrix_instance_f32 *pDst) +{ + float32_t const *pSrBVec; + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + pSrBVec = (float32_t const *) pInB; + + pInA0 = pInA; + pInA1 = pInA0 + MATRIX_DIM4; + pInA2 = pInA1 + MATRIX_DIM4; + pInA3 = pInA2 + MATRIX_DIM4; + /* + * load {b0,0, b0,1, b0,2, b0,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vmulq(vecInB, *pInA0++); + vecMac1 = vmulq(vecInB, *pInA1++); + vecMac2 = vmulq(vecInB, *pInA2++); + vecMac3 = vmulq(vecInB, *pInA3++); + /* + * load {b1,0, b1,1, b1,2, b1,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b2,0, b2,1, b2,2, b2,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + /* + * load {b3,0, b3,1, b3,2, b3,3} + */ + vecInB = vld1q(pSrBVec); + pSrBVec += MATRIX_DIM4; + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + vst1q(pOut, vecMac0); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac1); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac2); + pOut += MATRIX_DIM4; + vst1q(pOut, vecMac3); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + int numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + int numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + int numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t blkCnt; /* loop counters */ + uint32_t i; + arm_status status; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + pOut[0] = pInA[0] * pInB[0]; + return(ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_f32_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_f32_3x3_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 4) + return arm_mat_mult_f32_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* main loop process 4 rows */ + i = numRowsA >> 2; + while (i > 0U) + { + float32_t *pInA0, *pInA1, *pInA2, *pInA3; + float32_t *pInB0; + float32_t *pOut0, *pOut1, *pOut2, *pOut3; + f32x4_t vecMac0, vecMac1, vecMac2, vecMac3; + f32x4_t vecInB; + + /* pointers to 4 consecutive output rows */ + pOut0 = pOut; + pOut1 = pOut0 + numColsB; + pOut2 = pOut1 + numColsB; + pOut3 = pOut2 + numColsB; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + /* pointers to 4 consecutive Matrix A rows */ + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + vst1q(pOut1, vecMac1); + pOut1 += 4; + vst1q(pOut2, vecMac2); + pOut2 += 4; + vst1q(pOut3, vecMac3); + pOut3 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + pInA1 = pInA0 + numColsA; + pInA2 = pInA1 + numColsA; + pInA3 = pInA2 + numColsA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + vecMac1 = vdupq_n_f32(0.0f); + vecMac2 = vdupq_n_f32(0.0f); + vecMac3 = vdupq_n_f32(0.0f); + + blkCnt = numColsA; + + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + vecMac1 = vfmaq(vecMac1, vecInB, *pInA1++); + vecMac2 = vfmaq(vecMac2, vecInB, *pInA2++); + vecMac3 = vfmaq(vecMac3, vecInB, *pInA3++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (4 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + vstrwq_p_f32(pOut1, vecMac1, p0); + vstrwq_p_f32(pOut2, vecMac2, p0); + vstrwq_p_f32(pOut3, vecMac3, p0); + } + + /* move to next rows */ + pInA += 4 * numColsA; + pOut += 4 * numColsB; + i--; + } + + /* + * non multiple of 4 rows for Matrix A + * process single row + */ + if (numRowsA & 3) + { + i = numRowsA & 3; + while (i > 0U) + { + float32_t *pInA0; + float32_t *pInB0; + float32_t *pOut0; + f32x4_t vecInB; + f32x4_t vecMac0; + + pOut0 = pOut; + pInB0 = pInB; + + uint32_t k = numColsB >> 2; + while (k > 0U) + { + pInA0 = pInA; + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = *(f32x4_t *)pInB0; /* vldrwq_f32(pInB0, 0); */ + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* Store the results (1 x 4 block) in the destination buffer */ + vst1q(pOut0, vecMac0); + pOut0 += 4; + + /* + * rewind + */ + pInB0 -= (numColsB * numColsA) - 4; + k--; + } + + int colBLeft = numColsB & 3; + if (colBLeft) + { + pInA0 = pInA; + mve_pred16_t p0 = vctp32q(colBLeft); + + vecMac0 = vdupq_n_f32(0.0f); + blkCnt = numColsA; + while (blkCnt > 0U) + { + /* + * load {bi,4n+0, bi,4n+1, bi,4n+2, bi,4n+3} + */ + vecInB = vldrwq_z_f32(pInB0, p0); + + vecMac0 = vfmaq(vecMac0, vecInB, *pInA0++); + + pInB0 = pInB0 + numColsB; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* Store the results (1 x colBLeft block) in the destination buffer */ + vstrwq_p_f32(pOut0, vecMac0, p0); + } + + /* move to next row */ + pInA += 1 * numColsA; + pOut += 1 * numColsB; + i--; + } + + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else + +#if defined(ARM_MATH_NEON) +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + + + uint16_t col, i = 0U, j, row = numRowsA, rowCnt, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + float32x4_t a0V, a1V, a2V, a3V, a4V, a5V, a6V, a7V; + float32x4_t acc0,acc1,acc2,acc3,acc4,acc5,acc6,acc7,temp; + float32x2_t accum = vdup_n_f32(0); + float32_t *pIn1B = pSrcA->pData; + float32_t *pIn1C = pSrcA->pData; + float32_t *pIn1D = pSrcA->pData; + float32_t *pIn1E = pSrcA->pData; + float32_t *pIn1F = pSrcA->pData; + float32_t *pIn1G = pSrcA->pData; + float32_t *pIn1H = pSrcA->pData; + + float32_t *pxB,*pxC, *pxD, *pxE, *pxF, *pxG, *pxH; /* Temporary output data matrix pointer */ + float32_t sum0,sum1, sum2,sum3, sum4, sum5 , sum6, sum7; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* Row loop */ + rowCnt = row >> 3; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + GROUPOFROWS*i; + pxB = px + numColsB; + pxC = px + 2*numColsB; + pxD = px + 3*numColsB; + pxE = px + 4*numColsB; + pxF = px + 5*numColsB; + pxG = px + 6*numColsB; + pxH = px + 7*numColsB; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum0 = 0.0f; + sum1 = 0.0f; + sum2 = 0.0f; + sum3 = 0.0f; + sum4 = 0.0f; + sum5 = 0.0f; + sum6 = 0.0f; + sum7 = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + pIn1B = pIn1 + numColsA; + pIn1C = pIn1 + 2*numColsA; + pIn1D = pIn1 + 3*numColsA; + pIn1E = pIn1 + 4*numColsA; + pIn1F = pIn1 + 5*numColsA; + pIn1G = pIn1 + 6*numColsA; + pIn1H = pIn1 + 7*numColsA; + + acc0 = vdupq_n_f32(0.0); + acc1 = vdupq_n_f32(0.0); + acc2 = vdupq_n_f32(0.0); + acc3 = vdupq_n_f32(0.0); + acc4 = vdupq_n_f32(0.0); + acc5 = vdupq_n_f32(0.0); + acc6 = vdupq_n_f32(0.0); + acc7 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); + a1V = vld1q_f32(pIn1B); + a2V = vld1q_f32(pIn1C); + a3V = vld1q_f32(pIn1D); + a4V = vld1q_f32(pIn1E); + a5V = vld1q_f32(pIn1F); + a6V = vld1q_f32(pIn1G); + a7V = vld1q_f32(pIn1H); + + pIn1 += 4; + pIn1B += 4; + pIn1C += 4; + pIn1D += 4; + pIn1E += 4; + pIn1F += 4; + pIn1G += 4; + pIn1H += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + acc1 = vmlaq_f32(acc1,a1V,temp); + acc2 = vmlaq_f32(acc2,a2V,temp); + acc3 = vmlaq_f32(acc3,a3V,temp); + acc4 = vmlaq_f32(acc4,a4V,temp); + acc5 = vmlaq_f32(acc5,a5V,temp); + acc6 = vmlaq_f32(acc6,a6V,temp); + acc7 = vmlaq_f32(acc7,a7V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum0 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc1), vget_high_f32(acc1)); + sum1 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc2), vget_high_f32(acc2)); + sum2 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc3), vget_high_f32(acc3)); + sum3 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc4), vget_high_f32(acc4)); + sum4 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc5), vget_high_f32(acc5)); + sum5 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc6), vget_high_f32(acc6)); + sum6 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + accum = vpadd_f32(vget_low_f32(acc7), vget_high_f32(acc7)); + sum7 += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA & 3; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum0 += *pIn1++ * (*pIn2); + sum1 += *pIn1B++ * (*pIn2); + sum2 += *pIn1C++ * (*pIn2); + sum3 += *pIn1D++ * (*pIn2); + sum4 += *pIn1E++ * (*pIn2); + sum5 += *pIn1F++ * (*pIn2); + sum6 += *pIn1G++ * (*pIn2); + sum7 += *pIn1H++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum0; + *pxB++ = sum1; + *pxC++ = sum2; + *pxD++ = sum3; + *pxE++ = sum4; + *pxF++ = sum5; + *pxG++ = sum6; + *pxH++ = sum7; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + GROUPOFROWS*numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + } + + /* + + i was the index of a group of rows computed by previous loop. + Now i is the index of a row since below code is computing row per row + and no more group of row per group of rows. + + */ + + i = GROUPOFROWS*i; + rowCnt = row & 7; + + while(rowCnt > 0) + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + j = 0U; + + /* Column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initiate the pointer pIn1 to point to the starting address of the column being processed */ + pIn1 = pInA; + + acc0 = vdupq_n_f32(0.0); + + /* Compute 4 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* Matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + a0V = vld1q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2) + pIn1 += 4; + + temp = vsetq_lane_f32(*pIn2,temp,0); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,1); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,2); + pIn2 += numColsB; + temp = vsetq_lane_f32(*pIn2,temp,3); + pIn2 += numColsB; + + acc0 = vmlaq_f32(acc0,a0V,temp); + + /* Decrement the loop count */ + colCnt--; + } + + accum = vpadd_f32(vget_low_f32(acc0), vget_high_f32(acc0)); + sum += vget_lane_f32(accum, 0) + vget_lane_f32(accum, 1); + + /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. + ** No loop unrolling is used. */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */ + sum += *pIn1++ * (*pIn2); + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Store the result in the destination buffer */ + *px++ = sum; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + j++; + pIn2 = pSrcB->pData + j; + + /* Decrement the column loop counter */ + col--; + + } while (col > 0U); + + + /* Update the pointer pInA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + rowCnt--; + + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + float32_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0f; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,p) = a(m,1) * b(1,p) + a(m,2) * b(2,p) + .... + a(m,n) * b(n,p) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c new file mode 100644 index 0000000..a7bdf2d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f64.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_f64.c + * Description: Floating-point matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixMult Matrix Multiplication + * + * Multiplies two matrices. + * + * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices" + + * Matrix multiplication is only defined if the number of columns of the + * first matrix equals the number of rows of the second matrix. + * Multiplying an M x N matrix with an N x P matrix results + * in an M x P matrix. + * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of + * pSrcA and pSrcB are equal; and (2) that the size of the output + * matrix equals the outer dimensions of pSrcA and pSrcB. + */ + + +/** + * @addtogroup MatrixMult + * @{ + */ + +/** + * @brief Floating-point matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + +arm_status arm_mat_mult_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* Output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + float64_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint64_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0.0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = sum; + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c new file mode 100644 index 0000000..314b80e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q15.c + * Description: Q15 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q15() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.15 x 1.15 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.15 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 16 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q15() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q31_t sum; /* Accumulator */ + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#if defined (ARM_MATH_DSP) + q31_t in; /* Temporary variable to hold the input value */ + q31_t inA1, inB1, inA2, inB2; + q31_t sum2, sum3, sum4; + q15_t *pInA2, *pInB2, *px2; + uint32_t j = 0; +#else + q15_t in; /* Temporary variable to hold the input value */ + q15_t inA1, inB1, inA2, inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose */ + do + { + /* The pointer px is set to starting address of column being processed */ + px = pSrcBT + i; + + /* Apply loop unrolling and exchange columns with row elements */ + col = numColsB >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (col > 0U) + { + +#if defined (ARM_MATH_DSP) + + /* Read two elements from row */ + in = read_q15x2_ia (&pInB); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = read_q15x2_ia (&pInB); +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) in; +#else + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#ifndef ARM_MATH_BIG_ENDIAN + *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *px = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + px += numRowsB; + +#else /* #if defined (ARM_MATH_DSP) */ + + /* Read one element from row */ + in = *pInB++; + + /* Store one element in destination */ + *px = in; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + + in = *pInB++; + *px = in; + px += numRowsB; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement column loop counter */ + col--; + } + + /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + col = numColsB % 0x4U; + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pInB++; + + /* Update pointer px to point to next row of transposed matrix */ + px += numRowsB; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + +#if defined (ARM_MATH_DSP) + /* Process two rows from matrix A at a time and output two rows at a time */ + row = row >> 1U; + px2 = px + numColsB; +#endif + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + +#if defined (ARM_MATH_DSP) + /* Process two (transposed) columns from matrix B at a time */ + col = col >> 1U; + j = 0; +#endif + + /* column loop */ + while (col > 0U) + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + +#if defined (ARM_MATH_DSP) + sum2 = 0; + sum3 = 0; + sum4 = 0; + pInB = pSrcBT + j; + pInA2 = pInA + numColsA; + pInB2 = pInB + numRowsB; + + /* Read in two elements at once - allows dual MAC instruction */ + colCnt = numColsA >> 1U; +#else + colCnt = numColsA >> 2U; +#endif + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + +#if defined (ARM_MATH_DSP) + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA2); + inB2 = read_q15x2_ia (&pInB2); + + /* Multiply and Accumulates */ + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); +#else + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = *pInA++; + inB1 = *pInB++; + /* Multiply and Accumulates */ + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; + + inA1 = *pInA++; + inB1 = *pInB++; + sum += inA1 * inB1; + + inA2 = *pInA++; + inB2 = *pInB++; + sum += inA2 * inB2; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + colCnt--; + } + + /* process odd column samples */ +#if defined (ARM_MATH_DSP) + if (numColsA & 1U) { + inA1 = *pInA++; + inB1 = *pInB++; + inA2 = *pInA2++; + inB2 = *pInB2++; + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + } +#else + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += (q31_t) *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + +#if defined (ARM_MATH_DSP) + *px++ = (q15_t) (sum2 >> 15); + *px2++ = (q15_t) (sum3 >> 15); + *px2++ = (q15_t) (sum4 >> 15); + j += numRowsB * 2; +#endif + + /* Decrement column loop counter */ + col--; + + } + + i = i + numColsA; + +#if defined (ARM_MATH_DSP) + i = i + numColsA; + px = px2 + (numColsB & 1U); + px2 = px + numColsB; +#endif + + /* Decrement row loop counter */ + row--; + + } + + /* Compute any remaining odd row/column below */ + +#if defined (ARM_MATH_DSP) + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~0x1); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcBT + numRowsB * (numColsB-1); + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA & 3U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + colCnt--; + } + + /* Store result in destination buffer */ + *px = (q15_t) (sum >> 15); + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + pInB = pSrcBT; + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Compute 4 columns at once */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = read_q15x2_ia (&pInA); + inA2 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + inB2 = read_q15x2_ia (&pInB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + colCnt = numColsA % 4U; + while (colCnt > 0U) { + sum += (q31_t) (*pInA++) * (*pInB++); + + colCnt--; + } + + /* Store result in destination buffer */ + *px++ = (q15_t) (sum >> 15); + + /* Decrement column loop counter */ + col--; + } + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c new file mode 100644 index 0000000..99a4232 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c @@ -0,0 +1,374 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_fast_q31.c + * Description: Q31 matrix multiplication (fast variant) + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication (fast variant). + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The difference between the function \ref arm_mat_mult_q31() and this fast variant is that + the fast variant use a 32-bit rather than a 64-bit accumulator. + The result of each 1.31 x 1.31 multiplication is truncated to + 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30 + format. Finally, the accumulator is saturated and converted to a 1.31 result. + @par + The fast version has the same overflow behavior as the standard version but provides + less precision since it discards the low 32 bits of each multiplication result. + In order to avoid overflows completely the input signals must be scaled down. + Scale down one of the input matrices by log2(numColsA) bits to avoid overflows, + as a total of numColsA additions are computed internally for each output element. + @remark + Refer to \ref arm_mat_mult_q31() for a slower implementation of this function + which uses 64-bit accumulation to provide higher precision. + */ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; + q31_t sum1, sum2, sum3, sum4; /* Accumulator */ + q31_t inA1, inA2, inB1, inB2; + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + px = pDst->pData; + + row = row >> 1U; + px2 = px + numColsB; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + while (row > 0U) + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pInB = pSrcB->pData; + + j = 0U; + + col = col >> 1U; + + /* column loop */ + while (col > 0U) + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum1 = 0; + sum2 = 0; + sum3 = 0; + sum4 = 0; + + /* Initiate data pointers */ + pInA = pSrcA->pData + i; + pInB = pSrcB->pData + j; + pInA2 = pInA + numColsA; + + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + inA1 = *pInA++; + inB1 = pInB[0]; + inA2 = *pInA2++; + inB2 = pInB[1]; + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum2 = __SMMLA(inA1, inB2, sum2); + sum3 = __SMMLA(inA2, inB1, sum3); + sum4 = __SMMLA(inA2, inB2, sum4); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32); + sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32); + sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px++ = sum1 << 1; + *px++ = sum2 << 1; + *px2++ = sum3 << 1; + *px2++ = sum4 << 1; + + j += 2; + + /* Decrement column loop counter */ + col--; + } + + i = i + (numColsA << 1U); + px = px2 + (numColsB & 1U); + px2 = px + numColsB; + + /* Decrement row loop counter */ + row--; + } + + /* Compute any remaining odd row/column below */ + + /* Compute remaining output column */ + if (numColsB & 1U) { + + /* Avoid redundant computation of last element */ + row = numRowsA & (~1U); + + /* Point to remaining unfilled column in output matrix */ + px = pDst->pData + numColsB-1; + pInA = pSrcA->pData; + + /* row loop */ + while (row > 0) + { + + /* point to last column in matrix B */ + pInB = pSrcB->pData + numColsB-1; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Convert the result from 2.30 to 1.31 format and store in destination buffer */ + *px = sum1 << 1; + px += numColsB; + + /* Decrement row loop counter */ + row--; + } + } + + /* Compute remaining output row */ + if (numRowsA & 1U) { + + /* point to last row in output matrix */ + px = pDst->pData + (numColsB) * (numRowsA-1); + + col = numColsB; + i = 0U; + + /* col loop */ + while (col > 0) + { + + /* point to last row in matrix A */ + pInA = pSrcA->pData + (numRowsA-1) * numColsA; + pInB = pSrcB->pData + i; + + /* Set variable sum1, that acts as accumulator, to zero */ + sum1 = 0; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 columns at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + inA1 = *pInA++; + inA2 = *pInA++; + inB1 = *pInB; + pInB += numColsB; + inB2 = *pInB; + pInB += numColsB; +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(inA1, inB1, sum1); + sum1 = __SMMLA(inA2, inB2, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32); + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32); +#endif + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining column */ + colCnt = numColsA % 4U; + +#else + + /* Initialize colCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) { +#if defined (ARM_MATH_DSP) + sum1 = __SMMLA(*pInA++, *pInB, sum1); +#else + sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32); +#endif + pInB += numColsB; + + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1 << 1; + i++; + + /* Decrement col loop counter */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c new file mode 100644 index 0000000..91b1bcd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_opt_q31.c @@ -0,0 +1,784 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_opt_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + @remark + This function is a faster implementation of arm_mat_mult_q31 for MVE but it is requiring + additional storage for intermediate results. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_opt_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA2; + q31_t *pInB2; + q31_t *px; /* Temporary output data matrix pointer */ + q31_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q31_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q31 BT; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pDst->pData[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_opt_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_opt_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_opt_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + + /* + * Matrix transpose + */ + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q31(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * main loop + * compute 2 x 2 output blocks + * with dot products (Matrix A rows * Transposed MAtrix B rows) + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + * Compute 2 columns and 2 rows in parrallel + */ + col = numColsB >> 1; + j = 0; + + /* + * column pair loop + */ + while (col > 0u) { + q31_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q31x4_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointers + * - 2 x consecutive Matrix A rows (i increment is 2 x numColsA) + * - 2 x consecutive Matrix B' rows (j increment is 2 x numRowsB) + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q31_t const *) pInA; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcBVec = (q31_t const *) pInB; + pSrcB2Vec = (q31_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + /* load scheduling */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + acc3 = vrmlaldavhaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vrmlaldavhaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vrmlaldavhaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vrmlaldavhaq_p(acc3, vecA2, vecB2, p0); + } + + /* Convert to 1.31 */ + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + /* Store the results (2 x 2 block) in the destination buffer */ + *px++ = (q31_t) acc0; + *px++ = (q31_t) acc2; + *px2++ = (q31_t) acc1; + *px2++ = (q31_t) acc3; + + j += numRowsB * 2; + /* + * Decrement the column pair loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row pair loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + + /* single dot-product */ + acc0 = 0LL; + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px = (q31_t) acc0; + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q31_t const *pSrcAVec, *pSrcBVec; + q31x4_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q31_t const *) pInA; + pSrcBVec = (q31_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA / 4); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (numColsA & 3); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vrmlaldavhaq_p(acc0, vecA, vecB, p0); + } + + acc0 = asrl(acc0, 23); + *px++ = (q31_t) acc0; + + i += numColsA; + /* + * Decrement the col loop counter + */ + col--; + } + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* + * Return to application + */ + return (status); +} + +#else +arm_status arm_mat_mult_opt_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst, + q31_t *pState) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c new file mode 100644 index 0000000..e078681 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c @@ -0,0 +1,843 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q15.c + * Description: Q15 matrix multiplication + * + * $Date: 3 Nov 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q15 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @param[in] pState points to the array for storing intermediate results + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. The inputs to the + multiplications are in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + This approach provides 33 guard bits and there is no risk of overflow. + The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits + and then saturated to 1.15 format. + @par + Refer to \ref arm_mat_mult_fast_q15() for a faster but less precise version of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q15_2x2_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q15x8_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp16q(MATRIX_DIM2); + + vecColBOffs = vidupq_u16((uint32_t)0, 2); /* MATRIX_DIM2 */ + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + + pOut[0 * MATRIX_DIM2] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM2] = (q15_t) __SSAT(acc1, 16); + + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q15_3x3_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM3; + q15_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q15x8_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp16q(MATRIX_DIM3); + + vecColBOffs = vidupq_u16((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + + pOut[0 * MATRIX_DIM3] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM3] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM3] = (q15_t) __SSAT(acc2, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_mult_q15_4x4_mve( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16x8_t vecColBOffs; + q15_t *pInA0 = pInA; + q15_t *pInA1 = pInA0 + MATRIX_DIM4; + q15_t *pInA2 = pInA1 + MATRIX_DIM4; + q15_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q15x8_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp16q(MATRIX_DIM4); + + vecColBOffs = vidupq_u16((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrhq_gather_shifted_offset_z_s16((q15_t const *)pInB, vecColBOffs, p0); + + vecA0 = vldrhq_s16(pInA0); + vecA1 = vldrhq_s16(pInA1); + vecA2 = vldrhq_s16(pInA2); + vecA3 = vldrhq_s16(pInA3); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrhq_gather_shifted_offset_z_s16(pInB, vecColBOffs, p0); + + acc0 = vmlaldavq(vecA0, vecB); + acc1 = vmlaldavq(vecA1, vecB); + acc2 = vmlaldavq(vecA2, vecB); + acc3 = vmlaldavq(vecA3, vecB); + + acc0 = asrl(acc0, 15); + acc1 = asrl(acc1, 15); + acc2 = asrl(acc2, 15); + acc3 = asrl(acc3, 15); + + pOut[0 * MATRIX_DIM4] = (q15_t) __SSAT(acc0, 16); + pOut[1 * MATRIX_DIM4] = (q15_t) __SSAT(acc1, 16); + pOut[2 * MATRIX_DIM4] = (q15_t) __SSAT(acc2, 16); + pOut[3 * MATRIX_DIM4] = (q15_t) __SSAT(acc3, 16); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pInA2; + q15_t *pInB2; + q15_t *px; /* Temporary output data matrix pointer */ + q15_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* Status of matrix multiplication */ + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif + { + /* small squared matrix specialized routines */ + if (numRowsA == numColsB && numColsB == numColsA) { + + if (numRowsA == 1) { + q63_t sum; + sum = pInA[0] * pInB[0]; + pDst->pData[0] = (q15_t) __SSAT((sum >> 15), 16); + return (ARM_MATH_SUCCESS); + } else if (numRowsA == 2) + return arm_mat_mult_q15_2x2_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 3) + return arm_mat_mult_q15_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q15_4x4_mve(pSrcA, pSrcB, pDst); + } + + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB, &BT); + + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) { + q15_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q15x8_t vecA, vecA2, vecB, vecB2; + q63_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + + pSrcAVec = (q15_t const *) pInA; + pSrcA2Vec = (q15_t const *) pInA2; + pSrcBVec = (q15_t const *) pInB; + pSrcB2Vec = (q15_t const *) pInB2; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + + blkCnt = numColsA / 8; + while (blkCnt > 0U) { + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc1 = vmlaldavaq(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 8; + acc2 = vmlaldavaq(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + acc3 = vmlaldavaq(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + */ + blkCnt = numColsA & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmlaldavaq_p(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmlaldavaq_p(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmlaldavaq_p(acc3, vecA2, vecB2, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + *px++ = (q15_t) MVE_ASRL_SAT16(acc2, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc1, 15); + *px2++ = (q15_t) MVE_ASRL_SAT16(acc3, 15); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) / 8; + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) { + q15_t const *pSrcAVec, *pSrcBVec; + q15x8_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q15_t const *) pInA; + pSrcBVec = (q15_t const *) pInB; + acc0 = 0LL; + + blkCnt = ((numColsA) / 8); + while (blkCnt > 0U) { + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + acc0 = vmlaldavaq(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + */ + blkCnt = (numColsA & 7); + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmlaldavaq_p(acc0, vecA, vecB, p0); + } + + *px++ = (q15_t) MVE_ASRL_SAT16(acc0, 15); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState) +{ + q63_t sum; /* Accumulator */ + +#if defined (ARM_MATH_DSP) /* != CM0 */ + + q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix B */ + uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + + q31_t inA1, inB1, inA2, inB2; + arm_matrix_instance_q15 BT; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q15(pSrcB,&BT); + /* Reset variables for usage in following multiplication process */ + row = numRowsA; + i = 0U; + px = pDst->pData; + + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */ + pInB = pSrcBT; + + /* column loop */ + do + { + /* Set variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pInA to point to starting address of column being processed */ + pInA = pSrcA->pData + i; + + /* Apply loop unrolling and compute 2 MACs simultaneously. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* read real and imag values from pSrcA and pSrcB buffer */ + inA1 = read_q15x2_ia (&pInA); + inB1 = read_q15x2_ia (&pInB); + + inA2 = read_q15x2_ia (&pInA); + inB2 = read_q15x2_ia (&pInB); + + /* Multiply and Accumulates */ + sum = __SMLALD(inA1, inB1, sum); + sum = __SMLALD(inA2, inB2, sum); + + /* Decrement loop counter */ + colCnt--; + } + + /* process remaining column samples */ + colCnt = numColsA % 0x4U; + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + sum += *pInA++ * *pInB++; + + /* Decrement loop counter */ + colCnt--; + } + + /* Saturate and store result in destination buffer */ + *px = (q15_t) (__SSAT((sum >> 15), 16)); + px++; + + /* Decrement column loop counter */ + col--; + + } while (col > 0U); + + i = i + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q15_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */ + q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate pointer pIn1 to point to starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform multiply-accumulates */ + sum += (q31_t) * pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 34.30 to 1.15 format and store saturated value in destination buffer */ + + /* Saturate and store result in destination buffer */ + *px++ = (q15_t) __SSAT((sum >> 15), 16); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pSrcA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c new file mode 100644 index 0000000..1873827 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c @@ -0,0 +1,761 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q31.c + * Description: Q31 matrix multiplication + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + @brief Q31 matrix multiplication. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate + multiplication results but provides only a single guard bit. There is no saturation + on intermediate additions. Thus, if the accumulator overflows it wraps around and + distorts the result. The input signals should be scaled down to avoid intermediate + overflows. The input is thus scaled down by log2(numColsA) bits + to avoid overflows, as a total of numColsA additions are performed internally. + The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. + @remark + Refer to \ref arm_mat_mult_fast_q31() for a faster but less precise implementation of this function. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define MATRIX_DIM2 2 +#define MATRIX_DIM3 3 +#define MATRIX_DIM4 4 + +__STATIC_INLINE arm_status arm_mat_mult_q31_2x2_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM2; + q63_t acc0, acc1; + q31x4_t vecB, vecA0, vecA1; + /* enable predication to disable half of vector elements */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM2); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM2; + + pInB = pSrcB->pData; + + /* load 1st B column (partial load) */ + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + /* load A rows */ + vecA0 = vldrwq_s32(pInA0); + vecA1 = vldrwq_s32(pInA1); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + acc0 = vrmlaldavhq(vecA0, vecB); + acc1 = vrmlaldavhq(vecA1, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + + pOut[0 * MATRIX_DIM2] = (q31_t) acc0; + pOut[1 * MATRIX_DIM2] = (q31_t) acc1; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + + +__STATIC_INLINE arm_status arm_mat_mult_q31_3x3_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM3; + q31_t *pInA2 = pInA1 + MATRIX_DIM3; + q63_t acc0, acc1, acc2; + q31x4_t vecB, vecA; + /* enable predication to disable last (4th) vector element */ + mve_pred16_t p0 = vctp32q(MATRIX_DIM3); + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM3; + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_z_s32(pInB, vecColBOffs, p0); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + + pOut[0 * MATRIX_DIM3] = (q31_t) acc0; + pOut[1 * MATRIX_DIM3] = (q31_t) acc1; + pOut[2 * MATRIX_DIM3] = (q31_t) acc2; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_mult_q31_4x4_mve( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32x4_t vecColBOffs; + q31_t *pInA0 = pInA; + q31_t *pInA1 = pInA0 + MATRIX_DIM4; + q31_t *pInA2 = pInA1 + MATRIX_DIM4; + q31_t *pInA3 = pInA2 + MATRIX_DIM4; + q63_t acc0, acc1, acc2, acc3; + q31x4_t vecB, vecA; + + vecColBOffs = vidupq_u32((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrwq_gather_shifted_offset_s32(pInB, vecColBOffs); + + vecA = vldrwq_s32(pInA0); + acc0 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA1); + acc1 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA2); + acc2 = vrmlaldavhq(vecA, vecB); + vecA = vldrwq_s32(pInA3); + acc3 = vrmlaldavhq(vecA, vecB); + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + pOut[0 * MATRIX_DIM4] = (q31_t) acc0; + pOut[1 * MATRIX_DIM4] = (q31_t) acc1; + pOut[2 * MATRIX_DIM4] = (q31_t) acc2; + pOut[3 * MATRIX_DIM4] = (q31_t) acc3; + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t const *pInB = (q31_t const *)pSrcB->pData; /* input data matrix pointer B */ + q31_t const *pInA = (q31_t const *)pSrcA->pData; /* input data matrix pointer A */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t col, i = 0U, row = numRowsA; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + uint32x4_t vecOffs, vecColBOffs; + uint32_t blkCnt, rowCnt; /* loop counters */ + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if (numRowsA == 1) + { + q63_t sum = (q63_t) *pInA * *pInB; + pOut[0] = (q31_t)(sum >> 31); + return (ARM_MATH_SUCCESS); + } + else if(numRowsA == 2) + return arm_mat_mult_q31_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q31_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q31_4x4_mve(pSrcA, pSrcB, pDst); + } + + vecColBOffs = vidupq_u32((uint32_t)0, 1); + vecColBOffs = vecColBOffs * (uint32_t) (numColsB); + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + 4 * numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec; + q31_t const *pInA0 = pInA; + q31_t const *pInA1 = pInA0 + numColsA; + q31_t const *pInA2 = pInA1 + numColsA; + q31_t const *pInA3 = pInA2 + numColsA; + q63_t acc0, acc1, acc2, acc3; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + acc3 = 0LL; + + pSrcA0Vec = (q31_t const *) pInA0; + pSrcA1Vec = (q31_t const *) pInA1; + pSrcA2Vec = (q31_t const *) pInA2; + pSrcA3Vec = (q31_t const *) pInA3; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + vecA = vld1q(pSrcA1Vec); pSrcA1Vec += 4; + acc1 = vrmlaldavhaq(acc1, vecA, vecB); + vecA = vld1q(pSrcA2Vec); pSrcA2Vec += 4; + acc2 = vrmlaldavhaq(acc2, vecA, vecB); + vecA = vld1q(pSrcA3Vec); pSrcA3Vec += 4; + acc3 = vrmlaldavhaq(acc3, vecA, vecB); + } + + acc0 = asrl(acc0, 23); + acc1 = asrl(acc1, 23); + acc2 = asrl(acc2, 23); + acc3 = asrl(acc3, 23); + + px[0] = (q31_t) acc0; + px[1 * numColsB] = (q31_t) acc1; + px[2 * numColsB] = (q31_t) acc2; + px[3 * numColsB] = (q31_t) acc3; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += (numColsA * 4); + /* + * Decrement the row loop counter + */ + rowCnt --; + + } + rowCnt = row & 3; + while (rowCnt > 0U) + { + /* + * Output pointer is set to starting address of the row being processed + */ + px = pOut + i; + i = i + numColsB; + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB; + /* + * For every row wise process, the pInB pointer is set + * to the starting address of the pSrcB data + */ + pInB = (q31_t const *)pSrcB->pData; + /* + * column loop + */ + while (col > 0U) + { + /* + * generate 4 columns elements + */ + /* + * Matrix A columns number of MAC operations are to be performed + */ + + q31_t const *pSrcA0Vec; + q31_t const *pInA0 = pInA; + q63_t acc0; + + acc0 = 0LL; + + + pSrcA0Vec = (q31_t const *) pInA0; + + vecOffs = vecColBOffs; + + /* process 1 x 4 block output */ + blkCnt = numColsA >> 2; + while (blkCnt > 0U) + { + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset(pInB, vecOffs); + /* move Matrix B read offsets, 4 rows down */ + vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + q31x4_t vecB, vecA; + + vecB = vldrwq_gather_shifted_offset_z(pInB, vecOffs, p0); + //vecOffs = vecOffs + (uint32_t) (numColsB * 4); + + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vrmlaldavhaq(acc0, vecA, vecB); + + } + + acc0 = asrl(acc0, 23); + + + px[0] = (q31_t) acc0; + px++; + /* + * Decrement the column loop counter + */ + col--; + /* + * Update the pointer pInB to point to the starting address of the next column + */ + pInB = (q31_t const *)pSrcB->pData + (numColsB - col); + } + + /* + * Update the pointer pInA to point to the starting address of the next row + */ + pInA += numColsA; + /* + * Decrement the row loop counter + */ + rowCnt--; + } + + /* + * set status as ARM_MATH_SUCCESS + */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + q63_t sum; /* Accumulator */ + uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */ + uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */ + uint32_t col, i = 0U, row = numRowsA, colCnt; /* Loop counters */ + arm_status status; /* Status of matrix multiplication */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do + { + /* Output pointer is set to starting address of row being processed */ + px = pOut + i; + + /* For every row wise process, column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do + { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initialize pointer pIn1 to point to starting address of column being processed */ + pIn1 = pInA; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 MACs at a time. */ + colCnt = numColsA >> 2U; + + /* matrix multiplication */ + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Loop unrolling: Compute remaining MACs */ + colCnt = numColsA % 0x4U; + +#else + + /* Initialize cntCnt with number of columns */ + colCnt = numColsA; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (colCnt > 0U) + { + /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */ + + /* Perform the multiply-accumulates */ + sum += (q63_t) *pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement loop counter */ + colCnt--; + } + + /* Convert result from 2.62 to 1.31 format and store in destination buffer */ + *px++ = (q31_t) (sum >> 31); + + /* Decrement column loop counter */ + col--; + + /* Update pointer pIn2 to point to starting address of next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update pointer pInA to point to starting address of next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c new file mode 100644 index 0000000..3ce0fe6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q7.c @@ -0,0 +1,678 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_mult_q7.c + * Description: Q15 matrix multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixMult + @{ + */ + +/** + * @brief Q7 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results (Unused in some versions) + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * Scaling and Overflow Behavior: + * + * \par + * The function is implemented using a 32-bit internal accumulator saturated to 1.7 format. + * + * + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_2x2_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 2; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q31_t acc0, acc1; + q7x16_t vecB, vecA0, vecA1; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 2); /* MATRIX_DIM */ + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_3x3_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint8_t MATRIX_DIM = 3; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q31_t acc0, acc1, acc2; + q7x16_t vecB, vecA0, vecA1, vecA2; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 1); + vecColBOffs = vecColBOffs * MATRIX_DIM; + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + + +__STATIC_FORCEINLINE arm_status arm_mat_mult_q7_4x4_mve( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst) +{ + const uint32_t MATRIX_DIM = 4; + q7_t const *pInB = (q7_t const *)pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint8x16_t vecColBOffs; + q7_t *pInA0 = pInA; + q7_t *pInA1 = pInA0 + MATRIX_DIM; + q7_t *pInA2 = pInA1 + MATRIX_DIM; + q7_t *pInA3 = pInA2 + MATRIX_DIM; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecB, vecA0, vecA1, vecA2, vecA3; + mve_pred16_t p0 = vctp8q(MATRIX_DIM); + + vecColBOffs = vidupq_u8((uint32_t)0, 4); + + pInB = pSrcB->pData; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + vecA0 = vldrbq_s8(pInA0); + vecA1 = vldrbq_s8(pInA1); + vecA2 = vldrbq_s8(pInA2); + vecA3 = vldrbq_s8(pInA3); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + pOut++; + + /* move to next B column */ + pInB = pInB + 1; + + vecB = vldrbq_gather_offset_z(pInB, vecColBOffs, p0); + + acc0 = vmladavq_s8(vecA0, vecB); + acc1 = vmladavq_s8(vecA1, vecB); + acc2 = vmladavq_s8(vecA2, vecB); + acc3 = vmladavq_s8(vecA3, vecB); + + pOut[0 * MATRIX_DIM] = (q7_t) __SSAT(acc0 >> 7, 8); + pOut[1 * MATRIX_DIM] = (q7_t) __SSAT(acc1 >> 7, 8); + pOut[2 * MATRIX_DIM] = (q7_t) __SSAT(acc2 >> 7, 8); + pOut[3 * MATRIX_DIM] = (q7_t) __SSAT(acc3 >> 7, 8); + /* + * Return to application + */ + return (ARM_MATH_SUCCESS); +} + +arm_status arm_mat_mult_q7( + const arm_matrix_instance_q7 * pSrcA, + const arm_matrix_instance_q7 * pSrcB, + arm_matrix_instance_q7 * pDst, + q7_t * pState) +{ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pInA2; + q7_t *pInB2; + q7_t *px; /* Temporary output data matrix pointer */ + q7_t *px2; /* Temporary output data matrix pointer */ + uint32_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint32_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint32_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint32_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */ + uint32_t col, i = 0u, j, row = numRowsB; /* loop counters */ + q7_t *pSrcBT = pState; /* input data matrix pointer for transpose */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + arm_matrix_instance_q7 BT; + + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* small squared matrix specialized routines */ + if(numRowsA == numColsB && numColsB == numColsA) { + if(numRowsA == 2) + return arm_mat_mult_q7_2x2_mve(pSrcA, pSrcB, pDst); + else if(numRowsA == 3) + return arm_mat_mult_q7_3x3_mve(pSrcA, pSrcB, pDst); + else if (numRowsA == 4) + return arm_mat_mult_q7_4x4_mve(pSrcA, pSrcB, pDst); + } + /* + * Matrix transpose + */ + + BT.numRows = numColsB; + BT.numCols = numRowsB; + BT.pData = pSrcBT; + + arm_mat_trans_q7(pSrcB, &BT); + + /* + * Reset the variables for the usage in the following multiplication process + */ + i = 0; + row = numRowsA >> 1; + px = pDst->pData; + px2 = px + numColsB; + + /* + * The following loop performs the dot-product of each row in pSrcA with each column in pSrcB + */ + + /* + * row loop + */ + while (row > 0u) + { + /* + * For every row wise process, the column loop counter is to be initiated + */ + col = numColsB >> 1; + /* + * For every row wise process, the pIn2 pointer is set + * to the starting address of the transposed pSrcB data + */ + pInB = pSrcBT; + pInB2 = pInB + numRowsB; + j = 0; + + /* + * column loop + */ + while (col > 0u) + { + q7_t const *pSrcAVec, *pSrcBVec, *pSrcA2Vec, *pSrcB2Vec; + q7x16_t vecA, vecA2, vecB, vecB2; + q31_t acc0, acc1, acc2, acc3; + + /* + * Initiate the pointer pIn1 to point to the starting address of the column being processed + */ + pInA = pSrcA->pData + i; + pInA2 = pInA + numColsA; + pInB = pSrcBT + j; + pInB2 = pInB + numRowsB; + + pSrcAVec = (q7_t const *) pInA; + pSrcA2Vec = (q7_t const *)pInA2; + pSrcBVec = (q7_t const *) pInB; + pSrcB2Vec = (q7_t const *)pInB2; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + + blkCnt = numColsA >> 4; + while (blkCnt > 0U) + { + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + vecA2 = vld1q(pSrcA2Vec); + pSrcA2Vec += 16; + acc1 = vmladavaq_s8(acc1, vecA2, vecB); + vecB2 = vld1q(pSrcB2Vec); + pSrcB2Vec += 16; + acc2 = vmladavaq_s8(acc2, vecA, vecB2); + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + acc3 = vmladavaq_s8(acc3, vecA2, vecB2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + vecA2 = vld1q(pSrcA2Vec); + acc1 = vmladavaq_p_s8(acc1, vecA2, vecB, p0); + vecB2 = vld1q(pSrcB2Vec); + acc2 = vmladavaq_p_s8(acc2, vecA, vecB2, p0); + vecA = vld1q(pSrcAVec); + acc3 = vmladavaq_p_s8(acc3, vecA2, vecB2, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + *px++ = (q7_t) __SSAT(acc2 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc1 >> 7, 8); + *px2++ = (q7_t) __SSAT(acc3 >> 7, 8); + j += numRowsB * 2; + /* + * Decrement the column loop counter + */ + col--; + + } + + i = i + numColsA * 2; + px = px2 + (numColsB & 1u); + px2 = px + numColsB; + /* + * Decrement the row loop counter + */ + row--; + } + + /* + * Compute remaining row and/or column below + */ + + if (numColsB & 1u) + { + row = numRowsA & (~0x1); //avoid redundant computation + px = pDst->pData + numColsB - 1; + i = 0; + + /* + * row loop + */ + while (row > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last column in matrix B + */ + pInB = pSrcBT + numRowsB * (numColsB - 1); + pInA = pSrcA->pData + i; + + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + + acc0 = 0LL; + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px = (q7_t) __SSAT(acc0 >> 7, 8); + + px += numColsB; + + i += numColsA; + /* + * Decrement the row loop counter + */ + row--; + } + } + + if (numRowsA & 1u) + { + col = numColsB; + i = 0u; + /* + * point to last row in output matrix + */ + px = pDst->pData + (numColsB) * (numRowsA - 1); + /* + * col loop + */ + while (col > 0) + { + q7_t const *pSrcAVec, *pSrcBVec; + q7x16_t vecA, vecB; + q63_t acc0; + + /* + * point to last row in matrix A + */ + pInA = pSrcA->pData + (numRowsA - 1) * numColsA; + pInB = pSrcBT + i; + + /* + * Set the variable sum, that acts as accumulator, to zero + */ + pSrcAVec = (q7_t const *) pInA; + pSrcBVec = (q7_t const *) pInB; + acc0 = 0LL; + + blkCnt = (numColsA) >> 4; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcAVec); + pSrcAVec += 16; + vecB = vld1q(pSrcBVec); + pSrcBVec += 16; + acc0 = vmladavaq_s8(acc0, vecA, vecB); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numColsA & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + acc0 = vmladavaq_p_s8(acc0, vecA, vecB, p0); + } + + *px++ = (q7_t) __SSAT(acc0 >> 7, 8); + + i += numColsA; + + /* + * Decrement the col loop counter + */ + col--; + } + } + /* + * Return to application + */ + status = ARM_MATH_SUCCESS; + } + return(status); +} +#else +arm_status arm_mat_mult_q7(const arm_matrix_instance_q7 *pSrcA, const arm_matrix_instance_q7 *pSrcB, arm_matrix_instance_q7 *pDst, q7_t *pState) +{ + q31_t sum; /* accumulator */ + q7_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + q7_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + q7_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q7 type */ + q7_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q7 type */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + q7_t *px; /* Temporary output data matrix pointer */ + uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */ + uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */ + uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */ + uint16_t col, i = 0U, row = numRowsA, colCnt; /* loop counters */ + arm_status status; /* status of matrix multiplication */ + + (void)pState; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numCols != pSrcB->numRows) || + (pSrcA->numRows != pDst->numRows) || + (pSrcB->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */ + /* row loop */ + do { + /* Output pointer is set to starting address of the row being processed */ + px = pOut + i; + + /* For every row wise process, the column loop counter is to be initiated */ + col = numColsB; + + /* For every row wise process, the pIn2 pointer is set + ** to the starting address of the pSrcB data */ + pIn2 = pSrcB->pData; + + /* column loop */ + do { + /* Set the variable sum, that acts as accumulator, to zero */ + sum = 0; + + /* Initiate the pointer pIn1 to point to the starting address of pSrcA */ + pIn1 = pInA; + + /* Matrix A columns number of MAC operations are to be performed */ + colCnt = numColsA; + + /* matrix multiplication */ + while (colCnt > 0U) { + /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */ + /* Perform the multiply-accumulates */ + sum += (q31_t)*pIn1++ * *pIn2; + pIn2 += numColsB; + + /* Decrement the loop counter */ + colCnt--; + } + + /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */ + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)__SSAT((sum >> 7), 8); + + /* Decrement the column loop counter */ + col--; + + /* Update the pointer pIn2 to point to the starting address of the next column */ + pIn2 = pInB + (numColsB - col); + + } while (col > 0U); + + /* Update the pointer pSrcA to point to the starting address of the next row */ + i = i + numColsB; + pInA = pInA + numColsA; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c new file mode 100644 index 0000000..fc2193d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f16.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f16.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f16x8_t vecIn, vecOut, vecScale; + float16_t const *pInVec; + + pInVec = (float16_t const *) pIn; + + vecScale = vdupq_n_f16(scale); + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 8; + + vecOut = vmulq_f16(vecIn, vecScale); + + vst1q(pOut, vecOut); + pOut += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else + +arm_status arm_mat_scale_f16( + const arm_matrix_instance_f16 * pSrc, + float16_t scale, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float16_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (_Float16)(*pIn++) * (_Float16)scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c new file mode 100644 index 0000000..daebbb3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c @@ -0,0 +1,287 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_f32.c + * Description: Multiplies a floating-point matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixScale Matrix Scale + + Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the + matrix by the scalar. For example: + \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix" + + The function checks to make sure that the input and output matrices are of the same size. + + In the fixed-point Q15 and Q31 functions, scale is represented by + a fractional multiplication scaleFract and an arithmetic shift shift. + The shift allows the gain of the scaling operation to exceed 1.0. + The overall scale factor applied to the fixed-point data is + 
+      scale = scaleFract * 2^shift.
+
+ */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Floating-point matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scale scale factor to be applied + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix scaling */ + #ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecIn, vecOut; + float32_t const *pInVec; + + pInVec = (float32_t const *) pIn; + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + + vecOut = vecIn * scale; + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + vecOut = vecIn * scale; + + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix scaling */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + + blkCnt = numSamples >> 2; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* Scaling and results are stored in the destination buffer. */ + vec1 = vld1q_f32(pIn); + res = vmulq_f32(vec1, vdupq_n_f32(scale)); + vst1q_f32(pOut, res); + + /* update pointers to process next sampels */ + pIn += 4U; + pOut += 4U; + + /* Decrement the numSamples loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + /* The results are stored in the destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* Input data matrix pointer */ + float32_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counters */ + arm_status status; /* Status of matrix scaling */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * scale */ + + /* Scale and store result in destination buffer. */ + *pOut++ = (*pIn++) * scale; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c new file mode 100644 index 0000000..e43de0a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c @@ -0,0 +1,249 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q15.c + * Description: Multiplies a Q15 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q15 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.15 format. + These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* Status of matrix scaling */ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecIn, vecOut; + q15_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + + pInVec = (q15_t const *) pIn; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); pInVec += 8; + + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); pOut += 8; + + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vld1q(pInVec); pInVec += 8; + vecOut = vmulhq(vecIn, vdupq_n_s16(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrhq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q15_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = 15 - shift; /* Total shift to apply after scaling */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t inA1, inA2; + q31_t out1, out2, out3, out4; /* Temporary output variables */ + q15_t in1, in2, in3, in4; /* Temporary input variables */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + +#if defined (ARM_MATH_DSP) + /* read 2 times 2 samples at a time from source */ + inA1 = read_q15x2_ia (&pIn); + inA2 = read_q15x2_ia (&pIn); + + /* Scale inputs and store result in temporary variables + * in single cycle by packing the outputs */ + out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); + out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract); + out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); + out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract); + + /* apply shifting */ + out1 = out1 >> kShift; + out2 = out2 >> kShift; + out3 = out3 >> kShift; + out4 = out4 >> kShift; + + /* saturate the output */ + in1 = (q15_t) (__SSAT(out1, 16)); + in2 = (q15_t) (__SSAT(out2, 16)); + in3 = (q15_t) (__SSAT(out3, 16)); + in4 = (q15_t) (__SSAT(out4, 16)); + + /* store result to destination */ + write_q15x2_ia (&pOut, __PKHBT(in2, in1, 16)); + write_q15x2_ia (&pOut, __PKHBT(in4, in3, 16)); + +#else + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + *pOut++ = (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> kShift, 16)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c new file mode 100644 index 0000000..33c0868 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c @@ -0,0 +1,242 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_scale_q31.c + * Description: Multiplies a Q31 matrix by a scalar + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixScale + @{ + */ + +/** + @brief Q31 matrix scaling. + @param[in] pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The input data *pSrc and scaleFract are in 1.31 format. + These are multiplied to yield a 2.62 intermediate result which is shifted with saturation to 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecIn, vecOut; + q31_t const *pInVec; + int32_t totShift = shift + 1; /* shift to apply after scaling */ + arm_status status; /* Status of matrix scaling */ + + pInVec = (q31_t const *) pIn; + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* + * C(m,n) = A(m,n) * scale + * Scaling and results are stored in the destination buffer. + */ + vecIn = vld1q(pInVec); + pInVec += 4; + /* multiply input with scaler value */ + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + /* apply shifting */ + vecOut = vqshlq_r(vecOut, totShift); + + vst1q(pOut, vecOut); + pOut += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vld1q(pInVec); + pInVec += 4; + vecOut = vmulhq(vecIn, vdupq_n_s32(scaleFract)); + vecOut = vqshlq_r(vecOut, totShift); + vstrwq_p(pOut, vecOut, p0); + } + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* Input data matrix pointer */ + q31_t *pOut = pDst->pData; /* Output data matrix pointer */ + uint32_t numSamples; /* Total number of elements in the matrix */ + uint32_t blkCnt; /* Loop counter */ + arm_status status; /* Status of matrix scaling */ + int32_t kShift = shift + 1; /* Shift to apply after scaling */ + q31_t in, out; /* Temporary variabels */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numRows) || + (pSrc->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrc->numRows * pSrc->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; /* read four inputs from source */ + in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */ + out = in << kShift; /* apply shifting */ + if (in != (out >> kShift)) /* saturate the results. */ + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; /* Store result destination */ + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) * k */ + + /* Scale, saturate and store result in destination buffer. */ + in = *pIn++; + in = ((q63_t) in * scaleFract) >> 32; + out = in << kShift; + if (in != (out >> kShift)) + out = 0x7FFFFFFF ^ (in >> 31); + *pOut++ = out; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixScale group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c new file mode 100644 index 0000000..8dafc14 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f16.c @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f16.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + _Float16 invLT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+7 < cols; j += 8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pLT[n*i + k]),vecX); + } + + if ((_Float16)pLT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f16 / (_Float16)pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_lower_triangular_f16( + const arm_matrix_instance_f16 * lt, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pLT = lt->pData; + float16_t *pA = a->pData; + + float16_t *lt_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + lt_row = &pLT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= (_Float16)lt_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)lt_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c new file mode 100644 index 0000000..c7cdecc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f32.c @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f32.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invLT)); + vst1q(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + float32_t invLT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=0; i < n ; i++) + { + + for(j=0; j+3 < cols; j += 4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=0; k < i; k++) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pLT[n*i + k]),vecX); + } + + if (pLT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invLT = 1.0f / pLT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invLT)); + vst1q_f32(&pX[i*cols+j],vecA); + + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + lt_row = &pLT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#else + arm_status arm_mat_solve_lower_triangular_f32( + const arm_matrix_instance_f32 * lt, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pLT = lt->pData; + float32_t *pA = a->pData; + + float32_t *lt_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst -> numCols; + + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float32_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c new file mode 100644 index 0000000..d54ff67 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_lower_triangular_f64.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_lower_triangular_f64.c + * Description: Solve linear system LT X = A with LT lower triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + + + /** + * @brief Solve LT . X = A where LT is a lower triangular matrix + * @param[in] lt The lower triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of LT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_lower_triangular_f64( + const arm_matrix_instance_f64 * lt, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { + arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((lt->numRows != lt->numCols) || + (lt->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* a1 b1 c1 x1 = a1 + b2 c2 x2 a2 + c3 x3 a3 + + x3 = a3 / c3 + x2 = (a2 - c2 x3) / b2 + + */ + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pLT = lt->pData; + float64_t *pA = a->pData; + + float64_t *lt_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=0; i < n ; i++) + { + float64_t tmp=a_col[i * cols]; + + lt_row = &pLT[n*i]; + + for(k=0; k < i; k++) + { + tmp -= lt_row[k] * pX[cols*k+j]; + } + + if (lt_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / lt_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + /* Return to application */ + return (status); +} +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c new file mode 100644 index 0000000..332280f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f16.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f16.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + _Float16 invUT; + + f16x8_t vecA; + f16x8_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+7 < cols; j +=8) + { + vecA = vld1q_f16(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f16(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f16(pUT[n*i + k]),vecX); + } + + if ((_Float16)pUT[n*i + i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f16 / (_Float16)pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f16(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + _Float16 tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f16( + const arm_matrix_instance_f16 * ut, + const arm_matrix_instance_f16 * a, + arm_matrix_instance_f16 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float16_t *pX = dst->pData; + float16_t *pUT = ut->pData; + float16_t *pA = a->pData; + + float16_t *ut_row; + float16_t *a_col; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + ut_row = &pUT[n*i]; + + float16_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= (_Float16)ut_row[k] * (_Float16)pX[cols*k+j]; + } + + if ((_Float16)ut_row[i]==0.0f16) + { + return(ARM_MATH_SINGULAR); + } + tmp = (_Float16)tmp / (_Float16)ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c new file mode 100644 index 0000000..f58dfbd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f32.c @@ -0,0 +1,319 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f32.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq(vecA,vdupq_n_f32(invUT)); + + + vst1q(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + n = dst->numRows; + cols = dst->numCols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + float32_t invUT; + + f32x4_t vecA; + f32x4_t vecX; + + for(i=n-1; i >= 0 ; i--) + { + for(j=0; j+3 < cols; j +=4) + { + vecA = vld1q_f32(&pA[i * cols + j]); + + for(k=n-1; k > i; k--) + { + vecX = vld1q_f32(&pX[cols*k+j]); + vecA = vfmsq_f32(vecA,vdupq_n_f32(pUT[n*i + k]),vecX); + } + + if (pUT[n*i + i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + + invUT = 1.0f / pUT[n*i + i]; + vecA = vmulq_f32(vecA,vdupq_n_f32(invUT)); + + + vst1q_f32(&pX[i*cols+j],vecA); + } + + for(; j < cols; j ++) + { + a_col = &pA[j]; + + ut_row = &pUT[n*i]; + + float32_t tmp=a_col[i * cols]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + +#else + arm_status arm_mat_solve_upper_triangular_f32( + const arm_matrix_instance_f32 * ut, + const arm_matrix_instance_f32 * a, + arm_matrix_instance_f32 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float32_t *pX = dst->pData; + float32_t *pUT = ut->pData; + float32_t *pA = a->pData; + + float32_t *ut_row; + float32_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float32_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0f) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c new file mode 100644 index 0000000..248273d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_solve_upper_triangular_f64.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_solve_upper_triangular_f64.c + * Description: Solve linear system UT X = A with UT upper triangular matrix + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixInv + @{ + */ + +/** + * @brief Solve UT . X = A where UT is an upper triangular matrix + * @param[in] ut The upper triangular matrix + * @param[in] a The matrix a + * @param[out] dst The solution X of UT . X = A + * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved. + */ + arm_status arm_mat_solve_upper_triangular_f64( + const arm_matrix_instance_f64 * ut, + const arm_matrix_instance_f64 * a, + arm_matrix_instance_f64 * dst) + { +arm_status status; /* status of matrix inverse */ + + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((ut->numRows != ut->numCols) || + (ut->numRows != a->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + + int i,j,k,n,cols; + + float64_t *pX = dst->pData; + float64_t *pUT = ut->pData; + float64_t *pA = a->pData; + + float64_t *ut_row; + float64_t *a_col; + + n = dst->numRows; + cols = dst->numCols; + + for(j=0; j < cols; j ++) + { + a_col = &pA[j]; + + for(i=n-1; i >= 0 ; i--) + { + float64_t tmp=a_col[i * cols]; + + ut_row = &pUT[n*i]; + + for(k=n-1; k > i; k--) + { + tmp -= ut_row[k] * pX[cols*k+j]; + } + + if (ut_row[i]==0.0) + { + return(ARM_MATH_SINGULAR); + } + tmp = tmp / ut_row[i]; + pX[i*cols+j] = tmp; + } + + } + status = ARM_MATH_SUCCESS; + + } + + + /* Return to application */ + return (status); +} + + +/** + @} end of MatrixInv group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c new file mode 100644 index 0000000..13291b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f16.c @@ -0,0 +1,215 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f16.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float16_t *pDataA, *pDataB, *pDataDst; + f16x8_t vecA, vecB, vecDst; + float16_t const *pSrcAVec; + float16_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float16_t const *) pDataA; + pSrcBVec = (float16_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 8; + vecB = vld1q(pSrcBVec); + pSrcBVec += 8; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_sub_f16( + const arm_matrix_instance_f16 * pSrcA, + const arm_matrix_instance_f16 * pSrcB, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float16_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (_Float16)(*pInA++) - (_Float16)(*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c new file mode 100644 index 0000000..e9a17d1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c @@ -0,0 +1,298 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f32.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix subtraction */ + uint32_t numSamples; /* total number of elements in the matrix */ + float32_t *pDataA, *pDataB, *pDataDst; + f32x4_t vecA, vecB, vecDst; + float32_t const *pSrcAVec; + float32_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (float32_t const *) pDataA; + pSrcBVec = (float32_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + vecB = vld1q(pSrcBVec); + vecDst = vsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + float32x4_t vec1; + float32x4_t vec2; + float32x4_t res; + + /* Total number of samples in the input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + + blkCnt = numSamples >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + /* Read values from source A */ + vec1 = vld1q_f32(pIn1); + vec2 = vld1q_f32(pIn2); + res = vsubq_f32(vec1, vec2); + vst1q_f32(pOut, res); + + /* Update pointers to process next samples */ + pIn1 += 4U; + pIn2 += 4U; + pOut += 4U; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the numSamples is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = numSamples % 0x4U; + + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + /* Subtract and then store the results in the destination buffer. */ + *pOut++ = (*pIn1++) - (*pIn2++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c new file mode 100644 index 0000000..245a76d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f64.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_f64.c + * Description: Floating-point matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixSub Matrix Subtraction + + Subtract two matrices. + \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices" + + The functions check to make sure that + pSrcA, pSrcB, and pDst have the same + number of rows and columns. + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Floating-point matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_sub_f64( + const arm_matrix_instance_f64 * pSrcA, + const arm_matrix_instance_f64 * pSrcB, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + float64_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint64_t numSamples; /* total number of elements in the matrix */ + uint64_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint64_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ + *pOut++ = (*pInA++) - (*pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c new file mode 100644 index 0000000..c379996 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c @@ -0,0 +1,219 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q15.c + * Description: Q15 Matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q15 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q15_t *pDataA, *pDataB, *pDataDst; + q15x8_t vecA, vecB, vecDst; + q15_t const *pSrcAVec; + q15_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q15_t const *) pDataA; + pSrcBVec = (q15_t const *) pDataB; + + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 3; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); pDataDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcAVec); pSrcAVec += 8; + vecB = vld1q(pSrcBVec); pSrcBVec += 8; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrhq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, Saturate and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); + write_q15x2_ia (&pOut, __QSUB16(read_q15x2_ia (&pInA), read_q15x2_ia (&pInB))); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract and store result in destination buffer. */ +#if defined (ARM_MATH_DSP) + *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++); +#else + *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16); +#endif + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c new file mode 100644 index 0000000..5045b29 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_sub_q31.c + * Description: Q31 matrix subtraction + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixSub + @{ + */ + +/** + @brief Q31 matrix subtraction. + @param[in] pSrcA points to the first input matrix structure + @param[in] pSrcB points to the second input matrix structure + @param[out] pDst points to output matrix structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + uint32_t numSamples; /* total number of elements in the matrix */ + q31_t *pDataA, *pDataB, *pDataDst; + q31x4_t vecA, vecB, vecDst; + q31_t const *pSrcAVec; + q31_t const *pSrcBVec; + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + + pDataA = pSrcA->pData; + pDataB = pSrcB->pData; + pDataDst = pDst->pData; + pSrcAVec = (q31_t const *) pDataA; + pSrcBVec = (q31_t const *) pDataB; + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + + /* + * Total number of samples in the input matrix + */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + blkCnt = numSamples >> 2; + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) + B(m,n) */ + /* sub and then store the results in the destination buffer. */ + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq(vecA, vecB); + vst1q(pDataDst, vecDst); + pDataDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = numSamples & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcAVec); + pSrcAVec += 4; + vecB = vld1q(pSrcBVec); + pSrcBVec += 4; + vecDst = vqsubq_m(vecDst, vecA, vecB, p0); + vstrwq_p(pDataDst, vecDst, p0); + } + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */ + q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + + uint32_t numSamples; /* total number of elements in the matrix */ + uint32_t blkCnt; /* loop counters */ + arm_status status; /* status of matrix subtraction */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrcA->numRows != pSrcB->numRows) || + (pSrcA->numCols != pSrcB->numCols) || + (pSrcA->numRows != pDst->numRows) || + (pSrcA->numCols != pDst->numCols) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Total number of samples in input matrix */ + numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = numSamples >> 2U; + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and then store the results in the destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = numSamples % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = numSamples; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C(m,n) = A(m,n) - B(m,n) */ + + /* Subtract, saturate and store result in destination buffer. */ + *pOut++ = __QSUB(*pInA++, *pInB++); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixSub group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c new file mode 100644 index 0000000..8a41ccb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f16.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f16.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else + +arm_status arm_mat_trans_f16( + const arm_matrix_instance_f16 * pSrc, + arm_matrix_instance_f16 * pDst) +{ + float16_t *pIn = pSrc->pData; /* input data matrix pointer */ + float16_t *pOut = pDst->pData; /* output data matrix pointer */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c new file mode 100644 index 0000000..b411663 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c @@ -0,0 +1,325 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f32.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +#else +#if defined(ARM_MATH_NEON) + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nColumns = pSrc->numCols; /* number of columns */ + + uint16_t blkCnt, rowCnt, i = 0U, row = nRows; /* loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* Row loop */ + rowCnt = row >> 2; + while (rowCnt > 0U) + { + float32x4_t row0V,row1V,row2V,row3V; + float32x4x2_t ra0,ra1,rb0,rb1; + + blkCnt = nColumns >> 2; + + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) /* Column loop */ + { + row0V = vld1q_f32(pIn); + row1V = vld1q_f32(pIn + 1 * nColumns); + row2V = vld1q_f32(pIn + 2 * nColumns); + row3V = vld1q_f32(pIn + 3 * nColumns); + pIn += 4; + + ra0 = vzipq_f32(row0V,row2V); + ra1 = vzipq_f32(row1V,row3V); + + rb0 = vzipq_f32(ra0.val[0],ra1.val[0]); + rb1 = vzipq_f32(ra0.val[1],ra1.val[1]); + + vst1q_f32(px,rb0.val[0]); + px += nRows; + + vst1q_f32(px,rb0.val[1]); + px += nRows; + + vst1q_f32(px,rb1.val[0]); + px += nRows; + + vst1q_f32(px,rb1.val[1]); + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + + /* Perform matrix transpose for last 3 samples here. */ + blkCnt = nColumns % 0x4U; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px++ = *pIn; + *px++ = *(pIn + 1 * nColumns); + *px++ = *(pIn + 2 * nColumns); + *px++ = *(pIn + 3 * nColumns); + + px += (nRows - 4); + pIn++; + + /* Decrement the column loop counter */ + blkCnt--; + } + + i += 4; + pIn += 3 * nColumns; + + /* Decrement the row loop counter */ + rowCnt--; + + } /* Row loop end */ + + rowCnt = row & 3; + while (rowCnt > 0U) + { + blkCnt = nColumns ; + /* The pointer px is set to starting address of the column being processed */ + px = pOut + i; + + while (blkCnt > 0U) + { + /* Read and store the input element in the destination */ + *px = *pIn++; + + /* Update the pointer px to point to the next row of the transposed matrix */ + px += nRows; + + /* Decrement the column loop counter */ + blkCnt--; + } + i++; + rowCnt -- ; + } + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst) +{ + float32_t *pIn = pSrc->pData; /* input data matrix pointer */ + float32_t *pOut = pDst->pData; /* output data matrix pointer */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c new file mode 100644 index 0000000..57b5043 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f64.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_f64.c + * Description: Floating-point matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @defgroup MatrixTrans Matrix Transpose + + Tranposes a matrix. + + Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix. + \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix" + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Floating-point matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +arm_status arm_mat_trans_f64( + const arm_matrix_instance_f64 * pSrc, + arm_matrix_instance_f64 * pDst) +{ + float64_t *pIn = pSrc->pData; /* input data matrix pointer */ + float64_t *pOut = pDst->pData; /* output data matrix pointer */ + float64_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint64_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} + +/** + * @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c new file mode 100644 index 0000000..e740922 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q15.c + * Description: Q15 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q15 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 1) + { + pDst->pData[0] = pSrc->pData[0]; + return(ARM_MATH_SUCCESS); + } + if (pDst->numCols == 2) + return arm_mat_trans_16bit_2x2((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_16bit_3x3_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_16bit_4x4_mve((uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + } + + arm_mat_trans_16bit_generic(pSrc->numRows, pSrc->numCols, (uint16_t *)pSrc->pData, (uint16_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst) +{ + q15_t *pIn = pSrc->pData; /* input data matrix pointer */ + q15_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; /* variable to hold temporary output */ +#endif + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer pOut is set to starting address of column being processed */ + pOut = pDst->pData + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Read two elements from row */ + in = read_q15x2_ia (&pIn); + + /* Unpack and store one element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) in; +#else + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Unpack and store second element in destination */ +#ifndef ARM_MATH_BIG_ENDIAN + *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16); +#else + *pOut = (q15_t) in; +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *pOut = *pIn++; + + /* Update pointer pOut to point to next row of transposed matrix */ + pOut += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c new file mode 100644 index 0000000..2c77254 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q31.c + * Description: Q31 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q31 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + arm_status status; /* status of matrix transpose */ + #ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + if (pDst->numRows == pDst->numCols) + { + if (pDst->numCols == 2) + return arm_mat_trans_32bit_2x2_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 3) + return arm_mat_trans_32bit_3x3_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + if (pDst->numCols == 4) + return arm_mat_trans_32bit_4x4_mve((uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + } + + arm_mat_trans_32bit_generic_mve(pSrc->numRows, pSrc->numCols, (uint32_t *)pSrc->pData, (uint32_t *)pDst->pData); + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#else +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst) +{ + q31_t *pIn = pSrc->pData; /* input data matrix pointer */ + q31_t *pOut = pDst->pData; /* output data matrix pointer */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of rows */ + uint16_t nCols = pSrc->numCols; /* number of columns */ + uint32_t col, row = nRows, i = 0U; /* Loop counters */ + arm_status status; /* status of matrix transpose */ + +#ifdef ARM_MATH_MATRIX_CHECK + + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || + (pSrc->numCols != pDst->numRows) ) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } + else + +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do + { + /* Pointer px is set to starting address of column being processed */ + px = pOut + i; + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + col = nCols >> 2U; + + while (col > 0U) /* column loop */ + { + /* Read and store input element in destination */ + *px = *pIn++; + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + *px = *pIn++; + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + /* Loop unrolling: Compute remaining outputs */ + col = nCols % 0x4U; + +#else + + /* Initialize col with number of samples */ + col = nCols; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (col > 0U) + { + /* Read and store input element in destination */ + *px = *pIn++; + + /* Update pointer px to point to next row of transposed matrix */ + px += nRows; + + /* Decrement column loop counter */ + col--; + } + + i++; + + /* Decrement row loop counter */ + row--; + + } while (row > 0U); /* row loop end */ + + /* Set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c new file mode 100644 index 0000000..a500d05 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q7.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_trans_q7.c + * Description: Q7 matrix transpose + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + @ingroup groupMatrix + */ + +/** + @addtogroup MatrixTrans + @{ + */ + +/** + @brief Q7 matrix transpose. + @param[in] pSrc points to input matrix + @param[out] pDst points to output matrix + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + + uint16x8_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint8_t const *pDataC; + uint8_t *pDataDestR; + uint16x8_t vecIn; + + const uint8_t * pDataSrc=(const uint8_t *)pSrc->pData; + uint8_t * pDataDst=(uint8_t *)pDst->pData; + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) + { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + return ARM_MATH_SIZE_MISMATCH; + } +#endif + + vecOffs = vidupq_u16((uint32_t)0, 1); + vecOffs = vecOffs * pSrc->numCols; + + i = pSrc->numCols; + do + { + pDataC = (uint8_t const *) pDataSrc; + pDataDestR = (uint8_t*)pDataDst; + + blkCnt = pSrc->numRows >> 3; + while (blkCnt > 0U) + { + /* widened loads */ + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_u16(pDataDestR, vecIn); + pDataDestR += 8; + pDataC = pDataC + pSrc->numCols * 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = pSrc->numRows & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecIn = vldrbq_gather_offset_u16(pDataC, vecOffs); + vstrbq_p_u16(pDataDestR, vecIn, p0); + } + pDataSrc += 1; + pDataDst += pSrc->numRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} +#else +arm_status arm_mat_trans_q7(const arm_matrix_instance_q7 *pSrc, arm_matrix_instance_q7 *pDst) +{ + q7_t *pSrcA = pSrc->pData; /* input data matrix pointer */ + q7_t *pOut = pDst->pData; /* output data matrix pointer */ + uint16_t nRows = pSrc->numRows; /* number of nRows */ + uint16_t nColumns = pSrc->numCols; /* number of nColumns */ + uint16_t col, row = nRows, i = 0U; /* row and column loop counters */ + arm_status status; /* status of matrix transpose */ + + +#ifdef ARM_MATH_MATRIX_CHECK + /* Check for matrix mismatch condition */ + if ((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows)) { + /* Set status as ARM_MATH_SIZE_MISMATCH */ + status = ARM_MATH_SIZE_MISMATCH; + } else +#endif /* #ifdef ARM_MATH_MATRIX_CHECK */ + + { + /* Matrix transpose by exchanging the rows with columns */ + /* row loop */ + do { + /* The pointer pOut is set to starting address of the column being processed */ + pOut = pDst->pData + i; + + /* Initialize column loop counter */ + col = nColumns; + + + while (col > 0U) { + /* Read and store the input element in the destination */ + *pOut = *pSrcA++; + + /* Update the pointer pOut to point to the next row of the transposed matrix */ + pOut += nRows; + + /* Decrement the column loop counter */ + col--; + } + + i++; + + /* Decrement the row loop counter */ + row--; + + } while (row > 0U); + + /* set status as ARM_MATH_SUCCESS */ + status = ARM_MATH_SUCCESS; + } + /* Return to application */ + return (status); +} +#endif /* defined(ARM_MATH_MVEI) */ + + +/** + @} end of MatrixTrans group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c new file mode 100644 index 0000000..f592f6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f16.c @@ -0,0 +1,396 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f16.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + * @ingroup groupMatrix + */ + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_f16( + const arm_matrix_instance_f16 *pSrcMat, + const float16_t *pSrcVec, + float16_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA0; + const float16_t *pInA1; + float16_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + *px++ = vecAddAcrossF16Mve(acc2); + *px++ = vecAddAcrossF16Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) + { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + *px++ = vecAddAcrossF16Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF16Mve(acc0); + } +} +#else +void arm_mat_vec_mult_f16(const arm_matrix_instance_f16 *pSrcMat, const float16_t *pVec, float16_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float16_t *pSrcA = pSrcMat->pData; + const float16_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float16_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float16_t *pInVec; /* input data matrix pointer B of Q31 type */ + float16_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float16_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Initialize accumulators */ + float16_t sum1 = 0.0f16; + float16_t sum2 = 0.0f16; + float16_t sum3 = 0.0f16; + float16_t sum4 = 0.0f16; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA2)++; + sum2 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA3)++; + sum3 += (_Float16)matData * (_Float16)vecData; + matData = *(pInA4)++; + sum4 += (_Float16)matData * (_Float16)vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float16_t sum = 0.0f16; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (_Float16)matData * (_Float16)vecData; + sum += (_Float16)matData2 * (_Float16)vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (_Float16)*pInA1++ * (_Float16)*pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c new file mode 100644 index 0000000..b112d34 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_f32.c @@ -0,0 +1,399 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_f32.c + * Description: Floating-point matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + + +/** + * @ingroup groupMatrix + */ + +/** + * @defgroup MatrixVectMult Matrix Vector Multiplication + * + * Multiplies a matrix and a vector. + * + */ + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Floating-point matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_f32( + const arm_matrix_instance_f32 *pSrcMat, + const float32_t *pSrcVec, + float32_t *pDstVec) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA0; + const float32_t *pInA1; + float32_t *px; + int32_t row; + uint32_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4 rows in parallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + *px++ = vecAddAcrossF32Mve(acc2); + *px++ = vecAddAcrossF32Mve(acc3); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) + { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = pSrcVec; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + *px++ = vecAddAcrossF32Mve(acc1); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) + { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = pSrcVec; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vld1q(pSrcA0Vec); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + *px++ = vecAddAcrossF32Mve(acc0); + } +} +#else + +void arm_mat_vec_mult_f32(const arm_matrix_instance_f32 *pSrcMat, const float32_t *pVec, float32_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const float32_t *pSrcA = pSrcMat->pData; + const float32_t *pInA1; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA2; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA3; /* input data matrix pointer A of Q31 type */ + const float32_t *pInA4; /* input data matrix pointer A of Q31 type */ + const float32_t *pInVec; /* input data matrix pointer B of Q31 type */ + float32_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + float32_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + float32_t sum1 = 0.0f; + float32_t sum2 = 0.0f; + float32_t sum3 = 0.0f; + float32_t sum4 = 0.0f; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += matData * vecData; + matData = *(pInA2)++; + sum2 += matData * vecData; + matData = *(pInA3)++; + sum3 += matData * vecData; + matData = *(pInA4)++; + sum4 += matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = sum1; + *px++ = sum2; + *px++ = sum3; + *px++ = sum4; + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + float32_t sum = 0.0f; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += matData * vecData; + sum += matData2 * vecData2; + colCnt--; + } + // process remainder of row + colCnt = numCols & 1u; + + + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = sum; + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c new file mode 100644 index 0000000..04499f9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q15.c @@ -0,0 +1,388 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q15.c + * Description: Q15 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q15 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to input vector + * @param[out] *pDst points to output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_q15( + const arm_matrix_instance_q15 * pSrcMat, + const q15_t *pSrcVec, + q15_t *pDstVec) +{ + const q15_t *pMatSrc = pSrcMat->pData; + const q15_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q15_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q15_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q15_t *pMat2; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q15x8_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + *px++ = MVE_ASRL_SAT16(acc2, 15); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q15_t const *pMat0Vec, *pMat1Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q15x8_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrhq_z_s16(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = MVE_ASRL_SAT16(acc0, 15); + *px++ = MVE_ASRL_SAT16(acc1, 15); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q15_t const *pMat0Vec, *pVec; + q15_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q15x8_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 8; + vecIn = vld1q(pVec); + pVec += 8; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrhq_z_s16(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + *px++ = MVE_ASRL_SAT16(acc0, 15); + } +} + +#else +void arm_mat_vec_mult_q15(const arm_matrix_instance_q15 *pSrcMat, const q15_t *pVec, q15_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q15_t *pSrcA = pSrcMat->pData; + const q15_t *pInA1; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA2; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA3; /* input data matrix pointer A of Q15 type */ + const q15_t *pInA4; /* input data matrix pointer A of Q15 type */ + const q15_t *pInVec; /* input data matrix pointer B of Q15 type */ + q15_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols >> 1; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = read_q15x2_ia (&pInVec); + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = read_q15x2_ia (&pInA1); + sum1 = __SMLALD(matData, vecData, sum1); + matData = read_q15x2_ia (&pInA2); + sum2 = __SMLALD(matData, vecData, sum2); + matData = read_q15x2_ia (&pInA3); + sum3 = __SMLALD(matData, vecData, sum3); + matData = read_q15x2_ia (&pInA4); + sum4 = __SMLALD(matData, vecData, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + colCnt = numCols & 1u; + if (numCols & 1u) { + vecData = *pInVec++; + sum1 += (q63_t)*pInA1++ * vecData; + sum2 += (q63_t)*pInA2++ * vecData; + sum3 += (q63_t)*pInA3++ * vecData; + sum4 += (q63_t)*pInA4++ * vecData; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q15_t)(__SSAT((sum1 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum2 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum3 >> 15), 16)); + *px++ = (q15_t)(__SSAT((sum4 >> 15), 16)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q15x2_ia (&pInVec); + vecData2 = read_q15x2_ia (&pInVec); + matData = read_q15x2_ia (&pInA1); + matData2 = read_q15x2_ia (&pInA1); + sum = __SMLALD(matData, vecData, sum); + sum = __SMLALD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q15_t)(__SSAT((sum >> 15), 16)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c new file mode 100644 index 0000000..9f491ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q31.c @@ -0,0 +1,376 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q31.c + * Description: Q31 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q31 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mat_vec_mult_q31( + const arm_matrix_instance_q31 * pSrcMat, + const q31_t *pSrcVec, + q31_t *pDstVec) +{ + const q31_t *pMatSrc = pSrcMat->pData; + const q31_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q31_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 3x64-bit accumulators per loop + */ + while (row >= 3) + { + q31_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pVec; + const q31_t *pMat2; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1, acc2; + q31x4_t vecMatA0, vecMatA1, vecMatA2, vecIn; + + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + acc2 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + acc2 = vmlaldavaq(acc2, vecIn, vecMatA2); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + *px++ = asrl(acc2, 31); + + pMatSrc += numCols * 3; + /* + * Decrement the row loop counter + */ + row -= 3; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q31_t const *pMat0Vec, *pMat1Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0, acc1; + q31x4_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0LL; + acc1 = 0LL; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrwq_z_s32(pVec, p0); + + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + acc1 = vmlaldavaq(acc1, vecIn, vecMatA1); + } + + *px++ = asrl(acc0, 31); + *px++ = asrl(acc1, 31); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q31_t const *pMat0Vec, *pVec; + q31_t const *pSrcVecPtr = pSrcVec; + q63_t acc0; + q31x4_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 4; + vecIn = vld1q(pVec); + pVec += 4; + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrwq_z_s32(pVec, p0); + acc0 = vmlaldavaq(acc0, vecIn, vecMatA0); + } + + *px++ = asrl(acc0, 31); + } +} +#else +void arm_mat_vec_mult_q31(const arm_matrix_instance_q31 *pSrcMat, const q31_t *pVec, q31_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q31_t *pSrcA = pSrcMat->pData; + const q31_t *pInA1; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA2; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA3; /* input data matrix pointer A of Q31 type */ + const q31_t *pInA4; /* input data matrix pointer A of Q31 type */ + const q31_t *pInVec; /* input data matrix pointer B of Q31 type */ + q31_t *px; /* Temporary output data matrix pointer */ + uint16_t i, row, colCnt; /* loop counters */ + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + /* row loop */ + while (row > 0) { + /* Initialize accumulators */ + q63_t sum1 = 0; + q63_t sum2 = 0; + q63_t sum3 = 0; + q63_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 2 columns per iteration */ + colCnt = numCols; + + /* Initialize pointers to the starting address of the column being processed */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Main loop: matrix-vector multiplication + while (colCnt > 0u) { + // Read 2 values from vector + vecData = *(pInVec)++; + + // Read 8 values from the matrix - 2 values from each of 4 rows, and do multiply accumulate + matData = *(pInA1)++; + sum1 += (q63_t)matData * vecData; + matData = *(pInA2)++; + sum2 += (q63_t)matData * vecData; + matData = *(pInA3)++; + sum3 += (q63_t)matData * vecData; + matData = *(pInA4)++; + sum4 += (q63_t)matData * vecData; + + // Decrement the loop counter + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q31_t)(sum1 >> 31); + *px++ = (q31_t)(sum2 >> 31); + *px++ = (q31_t)(sum3 >> 31); + *px++ = (q31_t)(sum4 >> 31); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q63_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + colCnt = numCols >> 1; + + while (colCnt > 0) { + vecData = *(pInVec)++; + vecData2 = *(pInVec)++; + matData = *(pInA1)++; + matData2 = *(pInA1)++; + sum += (q63_t)matData * vecData; + sum += (q63_t)matData2 * vecData2; + colCnt--; + } + + // process remainder of row + colCnt = numCols & 1u; + while (colCnt > 0) { + sum += (q63_t)*pInA1++ * *pInVec++; + colCnt--; + } + + *px++ = (q31_t)(sum >> 31); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c new file mode 100644 index 0000000..e7c7281 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_vec_mult_q7.c @@ -0,0 +1,420 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mat_vec_mult_q7.c + * Description: Q7 matrix and vector multiplication + * + * $Date: 23 April 2021 + * + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/matrix_functions.h" + +/** + * @ingroup groupMatrix + */ + + + +/** + * @addtogroup MatrixVectMult + * @{ + */ + +/** + * @brief Q7 matrix and vector multiplication. + * @param[in] *pSrcMat points to the input matrix structure + * @param[in] *pVec points to the input vector + * @param[out] *pDst points to the output vector + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mat_vec_mult_q7( + const arm_matrix_instance_q7 * pSrcMat, + const q7_t *pSrcVec, + q7_t *pDstVec) +{ + const q7_t *pMatSrc = pSrcMat->pData; + const q7_t *pMat0, *pMat1; + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + q7_t *px; + int32_t row; + uint16_t blkCnt; /* loop counters */ + + row = numRows; + px = pDstVec; + + /* + * compute 4x64-bit accumulators per loop + */ + while (row >= 4) + { + q7_t const *pMat0Vec, *pMat1Vec, *pMat2Vec, *pMat3Vec, *pVec; + const q7_t *pMat2, *pMat3; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1, acc2, acc3; + q7x16_t vecMatA0, vecMatA1, vecMatA2, vecMatA3, vecIn; + + pVec = pSrcVec; + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + pMat2 = pMat1 + numCols; + pMat3 = pMat2 + numCols; + + acc0 = 0L; + acc1 = 0L; + acc2 = 0L; + acc3 = 0L; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pMat2Vec = pMat2; + pMat3Vec = pMat3; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecMatA2 = vld1q(pMat2Vec); + pMat2Vec += 16; + vecMatA3 = vld1q(pMat3Vec); + pMat3Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecMatA2 = vld1q(pMat2Vec); + vecMatA3 = vld1q(pMat3Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + acc2 = vmladavaq(acc2, vecIn, vecMatA2); + acc3 = vmladavaq(acc3, vecIn, vecMatA3); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + *px++ = __SSAT(acc2 >> 7, 8); + *px++ = __SSAT(acc3 >> 7, 8); + + pMatSrc += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * process any remaining rows pair + */ + if (row >= 2) + { + q7_t const *pMat0Vec, *pMat1Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0, acc1; + q7x16_t vecMatA0, vecMatA1, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + pMat1 = pMat0 + numCols; + + acc0 = 0; + acc1 = 0; + + pMat0Vec = pMat0; + pMat1Vec = pMat1; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecMatA1 = vld1q(pMat1Vec); + pMat1Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + + blkCnt--; + } + + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecMatA1 = vld1q(pMat1Vec); + vecIn = vldrbq_z_s8(pVec, p0); + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + acc1 = vmladavaq(acc1, vecIn, vecMatA1); + } + + *px++ = __SSAT(acc0 >> 7, 8); + *px++ = __SSAT(acc1 >> 7, 8); + + pMatSrc += numCols * 2; + /* + * Decrement the row loop counter + */ + row -= 2; + } + + if (row >= 1) + { + q7_t const *pMat0Vec, *pVec; + q7_t const *pSrcVecPtr = pSrcVec; + q31_t acc0; + q7x16_t vecMatA0, vecIn; + + /* + * For every row wise process, the pInVec pointer is set + * to the starting address of the vector + */ + pVec = pSrcVec; + + /* + * Initialize the pointer pIn1 to point to the starting address of the column being processed + */ + pMat0 = pMatSrc; + + acc0 = 0LL; + + pMat0Vec = pMat0; + pVec = pSrcVecPtr; + + blkCnt = numCols >> 4; + while (blkCnt > 0U) + { + vecMatA0 = vld1q(pMat0Vec); + pMat0Vec += 16; + vecIn = vld1q(pVec); + pVec += 16; + + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + + vecMatA0 = vld1q(pMat0Vec); + vecIn = vldrbq_z_s8(pVec, p0); + acc0 = vmladavaq(acc0, vecIn, vecMatA0); + } + *px++ = __SSAT(acc0 >> 7, 8); + } +} + +#else +void arm_mat_vec_mult_q7(const arm_matrix_instance_q7 *pSrcMat, const q7_t *pVec, q7_t *pDst) +{ + uint32_t numRows = pSrcMat->numRows; + uint32_t numCols = pSrcMat->numCols; + const q7_t *pSrcA = pSrcMat->pData; + const q7_t *pInA1; /* input data matrix pointer of Q7 type */ + const q7_t *pInA2; /* input data matrix pointer of Q7 type */ + const q7_t *pInA3; /* input data matrix pointer of Q7 type */ + const q7_t *pInA4; /* input data matrix pointer of Q7 type */ + const q7_t *pInVec; /* input data vector pointer of Q7 type */ + q7_t *px; /* output data pointer */ + uint32_t i, row, colCnt; /* loop counters */ + + q31_t matData, matData2, vecData, vecData2; + + + /* Process 4 rows at a time */ + row = numRows >> 2; + i = 0u; + px = pDst; + + + + /* The following loop performs the dot-product of each row in pSrcA with the vector */ + while (row > 0) { + /* Initialize accumulators */ + q31_t sum1 = 0; + q31_t sum2 = 0; + q31_t sum3 = 0; + q31_t sum4 = 0; + + /* For every row wise process, the pInVec pointer is set + ** to the starting address of the vector */ + pInVec = pVec; + + /* Loop unrolling: process 4 columns per iteration */ + colCnt = numCols >> 2; + + /* Initialize row pointers so we can track 4 rows at once */ + pInA1 = pSrcA + i; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + pInA4 = pInA3 + numCols; + + + // Inner loop: matrix-vector multiplication + + while (colCnt > 0u) { + // Read 4 values from vector + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + // Read 16 values from the matrix - 4 values from each of 4 rows, and do multiply accumulate + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum1 = __SMLAD(matData, vecData, sum1); + sum1 = __SMLAD(matData2, vecData2, sum1); + matData = read_q7x4_ia (&pInA2); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum2 = __SMLAD(matData, vecData, sum2); + sum2 = __SMLAD(matData2, vecData2, sum2); + matData = read_q7x4_ia (&pInA3); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum3 = __SMLAD(matData, vecData, sum3); + sum3 = __SMLAD(matData2, vecData2, sum3); + matData = read_q7x4_ia (&pInA4); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum4 = __SMLAD(matData, vecData, sum4); + sum4 = __SMLAD(matData2, vecData2, sum4); + + // Decrement the loop counter + colCnt--; + } + + /* process any remaining columns */ + + colCnt = numCols & 3u; + + while (colCnt > 0) { + vecData = *pInVec++; + sum1 += *pInA1++ * vecData; + sum2 += *pInA2++ * vecData; + sum3 += *pInA3++ * vecData; + sum4 += *pInA4++ * vecData; + colCnt--; + } + + /* Saturate and store the result in the destination buffer */ + *px++ = (q7_t)(__SSAT((sum1 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum2 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum3 >> 7), 8)); + *px++ = (q7_t)(__SSAT((sum4 >> 7), 8)); + + i = i + numCols * 4; + + /* Decrement the row loop counter */ + row--; + } + + /* process any remaining rows */ + row = numRows & 3u; + while (row > 0) { + + q31_t sum = 0; + pInVec = pVec; + pInA1 = pSrcA + i; + + // loop unrolling - process 4 elements at a time + colCnt = numCols >> 2; + + while (colCnt > 0) { + vecData = read_q7x4_ia (&pInVec); + vecData2 = __SXTB16(__ROR(vecData, 8)); + vecData = __SXTB16(vecData); + matData = read_q7x4_ia (&pInA1); + matData2 = __SXTB16(__ROR(matData, 8)); + matData = __SXTB16(matData); + sum = __SMLAD(matData, vecData, sum); + sum = __SMLAD(matData2, vecData2, sum); + colCnt--; + } + + // process remainder of row + colCnt = numCols & 3u; + while (colCnt > 0) { + sum += *pInA1++ * *pInVec++; + colCnt--; + } + *px++ = (q7_t)(__SSAT((sum >> 7), 8)); + i = i + numCols; + row--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + * @} end of MatrixMult group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..267626f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/CMakeLists.txt @@ -0,0 +1,31 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPQuaternionMath) + +include(configLib) +include(configDsp) + + + +add_library(CMSISDSPQuaternionMath STATIC arm_quaternion_norm_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_inverse_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_conjugate_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_normalize_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_product_single_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion_product_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_quaternion2rotation_f32.c) +target_sources(CMSISDSPQuaternionMath PRIVATE arm_rotation2quaternion_f32.c) + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +endif() + + +configLib(CMSISDSPQuaternionMath ${ROOT}) +configDsp(CMSISDSPQuaternionMath ${ROOT}) + +### Includes +target_include_directories(CMSISDSPQuaternionMath PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c new file mode 100644 index 0000000..7c48178 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/QuaternionMathFunctions.c @@ -0,0 +1,34 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: QuaternionMathFunctions.c + * Description: Combination of all quaternion math function source files. + * + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_quaternion_norm_f32.c" +#include "arm_quaternion_inverse_f32.c" +#include "arm_quaternion_conjugate_f32.c" +#include "arm_quaternion_normalize_f32.c" +#include "arm_quaternion_product_single_f32.c" +#include "arm_quaternion_product_f32.c" +#include "arm_quaternion2rotation_f32.c" +#include "arm_rotation2quaternion_f32.c" diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c new file mode 100644 index 0000000..2105341 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion2rotation_f32.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion2rotation_f32.c + * Description: Floating-point quaternion 2 rotation conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConv Quaternion conversions + + Conversions between quaternion and rotation representations. + */ + +/** + @ingroup QuatConv + */ + +/** + @defgroup QuatRot Quaternion to Rotation + + Conversions from quaternion to rotation. + */ + +/** + @addtogroup QuatRot + @{ + */ + +/** + @brief Conversion of quaternion to equivalent rotation matrix. + @param[in] pInputQuaternions points to an array of normalized quaternions + @param[out] pOutputRotations points to an array of 3x3 rotations (in row order) + @param[in] nbQuaternions number of quaternions in the array + @return none. + + @par + Format of rotation matrix + + + The quaternion a + ib + jc + kd is converted into rotation matrix: + 
+     a^2 + b^2 - c^2 - d^2                 2bc - 2ad                 2bd + 2ac
+                 2bc + 2ad     a^2 - b^2 + c^2 - d^2                 2cd - 2ab
+                 2bd - 2ac                 2cd + 2ab     a^2 - b^2 - c^2 + d^2
+
+ Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22 + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + f32x4_t vec0,vec1, vec2 ,vec3; + float32_t q2q3, tmp1, tmp2 ; + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + + // q0 q1 q2 q3 + vec0 = vld1q(pInputQuaternions); + + // q0^2 q1^2 q2^2 q3^2 + vec1 = vmulq(vec0,vec0); + + // q0^2 q1q0 q2q0 q3q0 + vec2 = vmulq_n_f32(vec0, vgetq_lane(vec0,0)); + + // 2 (q0^2 q1q0 q2q0 q3q0) + vec2 = vmulq_n_f32(vec2, 2.0f); + + + // 2 q2q3 + q2q3 = vgetq_lane(vec0,2) * vgetq_lane(vec0,3); + q2q3 = q2q3 * 2.0f; + + // 2 (q0q1 q1^2 q2q1 q3q1) + vec3 = vmulq_n_f32(vec0, vgetq_lane(vec0,1)); + vec3 = vmulq_n_f32(vec3, 2.0f); + + + + vec0 = vsetq_lane(vgetq_lane(vec1,0) + vgetq_lane(vec1,1),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,2),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec0,0) - vgetq_lane(vec1,3),vec0,0); + vec0 = vsetq_lane(vgetq_lane(vec3,2) - vgetq_lane(vec2,3),vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) + vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(vgetq_lane(vec3,2) + vgetq_lane(vec2,3),vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + tmp1 = vgetq_lane(vec1,0) - vgetq_lane(vec1,1); + tmp2 = vgetq_lane(vec1,2) - vgetq_lane(vec1,3); + + + vec0 = vsetq_lane(tmp1 + tmp2,vec0,0); + vec0 = vsetq_lane(q2q3 - vgetq_lane(vec2,1) ,vec0,1); + vec0 = vsetq_lane(vgetq_lane(vec3,3) - vgetq_lane(vec2,2),vec0,2); + vec0 = vsetq_lane(q2q3 + vgetq_lane(vec2,1) ,vec0,3); + + vst1q(pOutputRotations, vec0); + pOutputRotations += 4; + + *pOutputRotations = tmp1 - tmp2; + pOutputRotations ++; + + pInputQuaternions += 4; + } +} + +#else +void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions, + float32_t *pOutputRotations, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + float32_t q00 = SQ(pInputQuaternions[0 + nb * 4]); + float32_t q11 = SQ(pInputQuaternions[1 + nb * 4]); + float32_t q22 = SQ(pInputQuaternions[2 + nb * 4]); + float32_t q33 = SQ(pInputQuaternions[3 + nb * 4]); + float32_t q01 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[1 + nb * 4]; + float32_t q02 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q03 = pInputQuaternions[0 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q12 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[2 + nb * 4]; + float32_t q13 = pInputQuaternions[1 + nb * 4]*pInputQuaternions[3 + nb * 4]; + float32_t q23 = pInputQuaternions[2 + nb * 4]*pInputQuaternions[3 + nb * 4]; + + float32_t xx = q00 + q11 - q22 - q33; + float32_t yy = q00 - q11 + q22 - q33; + float32_t zz = q00 - q11 - q22 + q33; + float32_t xy = 2*(q12 - q03); + float32_t xz = 2*(q13 + q02); + float32_t yx = 2*(q12 + q03); + float32_t yz = 2*(q23 - q01); + float32_t zx = 2*(q13 - q02); + float32_t zy = 2*(q23 + q01); + + pOutputRotations[0 + nb * 9] = xx; pOutputRotations[1 + nb * 9] = xy; pOutputRotations[2 + nb * 9] = xz; + pOutputRotations[3 + nb * 9] = yx; pOutputRotations[4 + nb * 9] = yy; pOutputRotations[5 + nb * 9] = yz; + pOutputRotations[6 + nb * 9] = zx; pOutputRotations[7 + nb * 9] = zy; pOutputRotations[8 + nb * 9] = zz; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatRot group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c new file mode 100644 index 0000000..213a5bb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_conjugate_f32.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_conjugate_f32.c + * Description: Floating-point quaternion conjugate + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatConjugate Quaternion Conjugate + + Compute the conjugate of a quaternion. + */ + +/** + @addtogroup QuatConjugate + @{ + */ + +/** + @brief Floating-point quaternion conjugates. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + + + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pConjugateQuaternions, vec1); + + + pInputQuaternions += 4; + pConjugateQuaternions += 4; + } +} +#else +void arm_quaternion_conjugate_f32(const float32_t *pInputQuaternions, + float32_t *pConjugateQuaternions, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + pConjugateQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0]; + pConjugateQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1]; + pConjugateQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2]; + pConjugateQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3]; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatConjugate group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c new file mode 100644 index 0000000..d82bbbf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_inverse_f32.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_inverse_f32.c + * Description: Floating-point quaternion inverse + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatInverse Quaternion Inverse + + Compute the inverse of a quaternion. + */ + +/** + @addtogroup QuatInverse + @{ + */ + +/** + @brief Floating-point quaternion inverse. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pInverseQuaternions points to the output vector of inverse quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + + + vec1 = vmulq_n_f32(vec1, 1.0f / squaredSum); + vec1 = vsetq_lane_f32(-vgetq_lane(vec1, 0),vec1,0); + vec1 = vnegq_f32(vec1); + + vst1q(pInverseQuaternions, vec1); + + + pInputQuaternions += 4; + pInverseQuaternions += 4; + + } +} + +#else +void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions, + float32_t *pInverseQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + + pInverseQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pInverseQuaternions[4 * i + 1] = -pInputQuaternions[4 * i + 1] / temp; + pInverseQuaternions[4 * i + 2] = -pInputQuaternions[4 * i + 2] / temp; + pInverseQuaternions[4 * i + 3] = -pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatInverse group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c new file mode 100644 index 0000000..af6653a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_norm_f32.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_norm_f32.c + * Description: Floating-point quaternion Norm + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNorm Quaternion Norm + + Compute the norm of a quaternion. + */ + +/** + @addtogroup QuatNorm + @{ + */ + +/** + @brief Floating-point quaternion Norm. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNorms points to the output vector of norms + @param[in] nbQuaternions number of quaternions in the input vector + @return none + */ + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + f32x4_t vec1; + float32_t squaredSum; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec1 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec1); + arm_sqrt_f32(squaredSum,pNorms); + + pInputQuaternions+= 4; + pNorms ++; + } + +} + +#else + +void arm_quaternion_norm_f32(const float32_t *pInputQuaternions, + float32_t *pNorms, + uint32_t nbQuaternions) +{ + float32_t temp; + uint32_t i; + + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + pNorms[i] = sqrtf(temp); + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNorm group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c new file mode 100644 index 0000000..605e558 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_normalize_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_normalize_f32.c + * Description: Floating-point quaternion normalization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatNormalized Quaternion normalization + + Compute a normalized quaternion. + */ + +/** + @addtogroup QuatNormalized + @{ + */ + +/** + @brief Floating-point normalization of quaternions. + @param[in] pInputQuaternions points to the input vector of quaternions + @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions + @param[in] nbQuaternions number of quaternions in each vector + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + f32x4_t vec1,vec2; + float32_t squaredSum,norm; + + for(uint32_t i=0; i < nbQuaternions; i++) + { + vec1 = vld1q(pInputQuaternions); + vec2 = vmulq(vec1,vec1); + squaredSum = vecAddAcrossF32Mve(vec2); + arm_sqrt_f32(squaredSum,&norm); + vec1 = vmulq_n_f32(vec1, 1.0f / norm); + vst1q(pNormalizedQuaternions, vec1); + + pInputQuaternions += 4; + pNormalizedQuaternions += 4; + + } +} + +#else +void arm_quaternion_normalize_f32(const float32_t *pInputQuaternions, + float32_t *pNormalizedQuaternions, + uint32_t nbQuaternions) +{ + float32_t temp; + + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + temp = SQ(pInputQuaternions[4 * i + 0]) + + SQ(pInputQuaternions[4 * i + 1]) + + SQ(pInputQuaternions[4 * i + 2]) + + SQ(pInputQuaternions[4 * i + 3]); + temp = sqrtf(temp); + + pNormalizedQuaternions[4 * i + 0] = pInputQuaternions[4 * i + 0] / temp; + pNormalizedQuaternions[4 * i + 1] = pInputQuaternions[4 * i + 1] / temp; + pNormalizedQuaternions[4 * i + 2] = pInputQuaternions[4 * i + 2] / temp; + pNormalizedQuaternions[4 * i + 3] = pInputQuaternions[4 * i + 3] / temp; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatNormalized group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c new file mode 100644 index 0000000..83ebf5e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_f32.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +/** + @ingroup groupQuaternionMath + */ + +/** + @defgroup QuatProd Quaternion Product + + Compute the product of quaternions. + */ + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdVect Elementwise Quaternion Product + + Compute the elementwise product of quaternions. + */ + +/** + @addtogroup QuatProdVect + @{ + */ + +/** + @brief Floating-point elementwise product two quaternions. + @param[in] qa first array of quaternions + @param[in] qb second array of quaternions + @param[out] qr elementwise product of quaternions + @param[in] nbQuaternions number of quaternions in the array + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + while (nbQuaternions > 0U) + { + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q(qb); + /* + * vcmul(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 0) + */ + vecAcc = vcmulq(vecTmpA, vecTmpB); + /* + * vcmla(r, [a1, a2, a1, a2], [b1, b2, b3, b4], 90) + */ + vecAcc = vcmlaq_rot90(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + /* + * build [-b4, -b3, b2, b1] + */ + vecTmpB = vecTmpB * vecSignA; + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 270) + */ + vecAcc = vcmlaq_rot270(vecAcc, vecTmpA, vecTmpB); + /* + * vcmla(r, [a4, a3, a4, a3], [-b4, -b3, b2, b1], 0) + */ + vecAcc = vcmlaq(vecAcc, vecTmpA, vecTmpB); + /* + * store accumulator + */ + vst1q_f32(qr, vecAcc); + + /* move to next quaternion */ + qa += 4; + qb += 4; + qr += 4; + + nbQuaternions--; + } +} + +#else + +void arm_quaternion_product_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr, + uint32_t nbQuaternions) +{ + uint32_t i; + for(i=0; i < nbQuaternions; i++) + { + arm_quaternion_product_single_f32(qa, qb, qr); + + qa += 4; + qb += 4; + qr += 4; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdVect group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c new file mode 100644 index 0000000..96f23e9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_quaternion_product_single_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quaternion_product_single_f32.c + * Description: Floating-point quaternion product + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + + +/** + @ingroup QuatProd + */ + +/** + @defgroup QuatProdSingle Quaternion Product + + Compute the product of two quaternions. + */ + +/** + @addtogroup QuatProdSingle + @{ + */ + +/** + @brief Floating-point product of two quaternions. + @param[in] qa first quaternion + @param[in] qb second quaternion + @param[out] qr product of two quaternions + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + static uint32_t patternA[4] = { 0, 1, 0, 1 }; + static uint32_t patternB[4] = { 3, 2, 3, 2 }; + static uint32_t patternC[4] = { 3, 2, 1, 0 }; + static float32_t signA[4] = { -1, -1, 1, 1 }; + + uint32x4_t vecA = vld1q_u32(patternA); + uint32x4_t vecB = vld1q_u32(patternB); + uint32x4_t vecC = vld1q_u32(patternC); + f32x4_t vecSignA = vld1q_f32(signA); + + + f32x4_t vecTmpA, vecTmpB, vecAcc; + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecA); + vecTmpB = vld1q_f32(qb); + + vecAcc = vcmulq_f32(vecTmpA, vecTmpB); + vecAcc = vcmlaq_rot90_f32(vecAcc, vecTmpA, vecTmpB); + + vecTmpA = vldrwq_gather_shifted_offset_f32(qa, vecB); + vecTmpB = vldrwq_gather_shifted_offset_f32(qb, vecC); + + vecTmpB = vecTmpB * vecSignA; + + vecAcc = vcmlaq_rot270_f32(vecAcc, vecTmpA, vecTmpB); + vecAcc = vcmlaq_f32(vecAcc, vecTmpA, vecTmpB); + + vst1q_f32(qr, vecAcc); +} + +#else +void arm_quaternion_product_single_f32(const float32_t *qa, + const float32_t *qb, + float32_t *qr) +{ + qr[0] = qa[0] * qb[0] - qa[1] * qb[1] - qa[2] * qb[2] - qa[3] * qb[3]; + qr[1] = qa[0] * qb[1] + qa[1] * qb[0] + qa[2] * qb[3] - qa[3] * qb[2]; + qr[2] = qa[0] * qb[2] + qa[2] * qb[0] + qa[3] * qb[1] - qa[1] * qb[3]; + qr[3] = qa[0] * qb[3] + qa[3] * qb[0] + qa[1] * qb[2] - qa[2] * qb[1]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of QuatProdSingle group + */ diff --git a/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c new file mode 100644 index 0000000..5d57492 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/QuaternionMathFunctions/arm_rotation2quaternion_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rotation2quaternion_f32.c + * Description: Floating-point rotation to quaternion conversion + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/quaternion_math_functions.h" +#include + +#define RI(x,y) r[(3*(x) + (y))] + + +/** + @ingroup QuatConv + */ + +/** + @defgroup RotQuat Rotation to Quaternion + + Conversions from rotation to quaternion. + */ + +/** + @addtogroup RotQuat + @{ + */ + +/** + * @brief Conversion of a rotation matrix to an equivalent quaternion. + * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order) + * @param[out] pOutputQuaternions points to an array quaternions + * @param[in] nbQuaternions number of quaternions in the array + * @return none. + * + * q and -q are representing the same rotation. This ambiguity must be taken into + * account when using the output of this function. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +#define R00 vgetq_lane(q1,0) +#define R01 vgetq_lane(q1,1) +#define R02 vgetq_lane(q1,2) +#define R10 vgetq_lane(q1,3) +#define R11 vgetq_lane(q2,0) +#define R12 vgetq_lane(q2,1) +#define R20 vgetq_lane(q2,2) +#define R21 vgetq_lane(q2,3) +#define R22 ro22 + +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + float32_t ro22, trace; + f32x4_t q1,q2, q; + + float32_t doubler; + float32_t s; + + q = vdupq_n_f32(0.0f); + + for(uint32_t nb=0; nb < nbQuaternions; nb++) + { + q1 = vld1q(pInputRotations); + pInputRotations += 4; + + q2 = vld1q(pInputRotations); + pInputRotations += 4; + + ro22 = *pInputRotations++; + + trace = R00 + R11 + R22; + + + if (trace > 0) + { + (void)arm_sqrt_f32(trace + 1.0f, &doubler) ; // invs=4*qw + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = 0.25f * doubler; + q[1] = R21 - R12; + q[2] = R02 - R20; + q[3] = R10 - R01; + } + else if ((R00 > R11) && (R00 > R22) ) + { + (void)arm_sqrt_f32(1.0f + R00 - R11 - R22,&doubler); // invs=4*qx + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R21 - R12; + q[1] = 0.25f * doubler; + q[2] = R01 + R10; + q[3] = R02 + R20; + } + else if (R11 > R22) + { + (void)arm_sqrt_f32(1.0f + R11 - R00 - R22,&doubler); // invs=4*qy + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R02 - R20; + q[1] = R01 + R10; + q[2] = 0.25f * doubler; + q[3] = R12 + R21; + } + else + { + (void)arm_sqrt_f32(1.0f + R22 - R00 - R11,&doubler); // invs=4*qz + doubler = 2.0f*doubler; + s = 1.0f / doubler; + + q1 = vmulq_n_f32(q1,s); + q2 = vmulq_n_f32(q2,s); + + q[0] = R10 - R01; + q[1] = R02 + R20; + q[2] = R12 + R21; + q[3] = 0.25f * doubler; + } + + vst1q(pOutputQuaternions, q); + pOutputQuaternions += 4; + + } +} + +#else +void arm_rotation2quaternion_f32(const float32_t *pInputRotations, + float32_t *pOutputQuaternions, + uint32_t nbQuaternions) +{ + uint32_t nb; + for(nb=0; nb < nbQuaternions; nb++) + { + const float32_t *r=&pInputRotations[nb*9]; + float32_t *q=&pOutputQuaternions[nb*4]; + + float32_t trace = RI(0,0) + RI(1,1) + RI(2,2); + + float32_t doubler; + float32_t s; + + + + if (trace > 0.0f) + { + doubler = sqrtf(trace + 1.0f) * 2.0f; // invs=4*qw + s = 1.0f / doubler; + q[0] = 0.25f * doubler; + q[1] = (RI(2,1) - RI(1,2)) * s; + q[2] = (RI(0,2) - RI(2,0)) * s; + q[3] = (RI(1,0) - RI(0,1)) * s; + } + else if ((RI(0,0) > RI(1,1)) && (RI(0,0) > RI(2,2)) ) + { + doubler = sqrtf(1.0f + RI(0,0) - RI(1,1) - RI(2,2)) * 2.0f; // invs=4*qx + s = 1.0f / doubler; + q[0] = (RI(2,1) - RI(1,2)) * s; + q[1] = 0.25f * doubler; + q[2] = (RI(0,1) + RI(1,0)) * s; + q[3] = (RI(0,2) + RI(2,0)) * s; + } + else if (RI(1,1) > RI(2,2)) + { + doubler = sqrtf(1.0f + RI(1,1) - RI(0,0) - RI(2,2)) * 2.0f; // invs=4*qy + s = 1.0f / doubler; + q[0] = (RI(0,2) - RI(2,0)) * s; + q[1] = (RI(0,1) + RI(1,0)) * s; + q[2] = 0.25f * doubler; + q[3] = (RI(1,2) + RI(2,1)) * s; + } + else + { + doubler = sqrtf(1.0f + RI(2,2) - RI(0,0) - RI(1,1)) * 2.0f; // invs=4*qz + s = 1.0f / doubler; + q[0] = (RI(1,0) - RI(0,1)) * s; + q[1] = (RI(0,2) + RI(2,0)) * s; + q[2] = (RI(1,2) + RI(2,1)) * s; + q[3] = 0.25f * doubler; + } + + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RotQuat group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt new file mode 100644 index 0000000..eb1e0ca --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPSVM) + +include(configLib) +include(configDsp) + + +add_library(CMSISDSPSVM STATIC) + +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_init_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_predict_f32.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_predict_f32.c) + + + +configLib(CMSISDSPSVM ${ROOT}) +configDsp(CMSISDSPSVM ${ROOT}) + +### Includes +target_include_directories(CMSISDSPSVM PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_linear_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_rbf_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_init_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_polynomial_predict_f16.c) +target_sources(CMSISDSPSVM PRIVATE arm_svm_sigmoid_predict_f16.c) +endif() + + + + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c new file mode 100644 index 0000000..85f19b9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctions.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_svm_linear_init_f32.c" +#include "arm_svm_linear_predict_f32.c" +#include "arm_svm_polynomial_init_f32.c" +#include "arm_svm_polynomial_predict_f32.c" +#include "arm_svm_rbf_init_f32.c" +#include "arm_svm_rbf_predict_f32.c" +#include "arm_svm_sigmoid_init_f32.c" +#include "arm_svm_sigmoid_predict_f32.c" diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c new file mode 100644 index 0000000..74d2665 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/SVMFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: BayesFunctions.c + * Description: Combination of all SVM function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_svm_linear_init_f16.c" +#include "arm_svm_linear_predict_f16.c" +#include "arm_svm_polynomial_init_f16.c" +#include "arm_svm_polynomial_predict_f16.c" +#include "arm_svm_rbf_init_f16.c" +#include "arm_svm_rbf_predict_f16.c" +#include "arm_svm_sigmoid_init_f16.c" +#include "arm_svm_sigmoid_predict_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c new file mode 100644 index 0000000..a3ebc7f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f16.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f16.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c new file mode 100644 index 0000000..75395aa --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_init_f32.c + * Description: SVM Linear Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @defgroup groupSVM SVM Functions + * + */ + +/** + @ingroup groupSVM + */ + +/** + @defgroup linearsvm Linear SVM + + Linear SVM classifier + */ + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S Parameters for the SVM function + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; +} + + + +/** + * @} end of linearsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c new file mode 100644 index 0000000..fe907e5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f16.c @@ -0,0 +1,314 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f16.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc3,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f16(acc0,*pDualCoef++); + acc0 = vfmaq_n_f16(acc0,acc1,*pDualCoef++); + + sum += (_Float16)vecAddAcrossF16Mve(acc0); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += (_Float16)*pDualCoef++ * (_Float16)vecAddAcrossF16Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_linear_predict_f16( + const arm_svm_linear_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c new file mode 100644 index 0000000..caf09df --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_linear_predict_f32.c @@ -0,0 +1,461 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_linear_predict_f32.c + * Description: SVM Linear Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup linearsvm + * @{ + */ + + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) + { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc2,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc3,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + acc0 = vmulq_n_f32(acc0,*pDualCoef++); + acc0 = vfmaq_n_f32(acc0,acc1,*pDualCoef++); + + sum += vecAddAcrossF32Mve(acc0); + + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + sum += *pDualCoef++ * vecAddAcrossF32Mve(acc0); + + } + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * dot; + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_linear_predict_f32( + const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * dot; + } + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of linearsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c new file mode 100644 index 0000000..558ab45 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f16.c @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f16.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + int32_t degree, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c new file mode 100644 index 0000000..7d33cd7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_init_f32.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_init_f32.c + * Description: SVM Polynomial Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup polysvm Polynomial SVM + + Polynomial SVM classifier + */ + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->degree = degree; + S->coef0 = coef0; + S->gamma = gamma; +} + + + +/** + * @} end of polysvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c new file mode 100644 index 0000000..724f286 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f16.c @@ -0,0 +1,369 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f16.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +#if !defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_AUTOVECTORIZE) + +/* + +_Float16 is not supported in g++ so we avoid putting _Float16 definitions +in the public headers. + +This function should at some point be moved in FastMath. + +*/ +__STATIC_INLINE float16_t arm_exponent_f16(float16_t x, int32_t nb) +{ + float16_t r = x; + nb --; + while(nb > 0) + { + r = (_Float16)r * (_Float16)x; + nb--; + } + return(r); +} +#endif + +/** + * @addtogroup polysvm + * @{ + */ + + + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), + S->degree),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f16(vSum, vld1q(pDualCoef), + arm_vec_exponent_f16 + (vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0), S->degree), + vctp16q(1)); + } + sum += (_Float16)vecAddAcrossF16Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f16( + const arm_svm_polynomial_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j]* (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)arm_exponent_f16((_Float16)S->gamma * (_Float16)dot + (_Float16)S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c new file mode 100644 index 0000000..13b1f84 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_polynomial_predict_f32.c @@ -0,0 +1,490 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_polynomial_predict_f32.c + * Description: SVM Polynomial Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +#include "arm_vec_math.h" +#endif + +/** + * @addtogroup polysvm + * @{ + */ + + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = vfmaq_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(2)); + + pDualCoef += 2; + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vSum = vfmaq_m_f32(vSum, vld1q(pDualCoef), + arm_vec_exponent_f32 + (vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0), S->degree), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = arm_vec_exponent_f32(dotV,S->degree); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_polynomial_predict_f32( + const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * arm_exponent_f32(S->gamma * dot + S->coef0, S->degree); + } + + *pResult=S->classes[STEP(sum)]; +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + +/** + * @} end of polysvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c new file mode 100644 index 0000000..43de249 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f16.c @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f16.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c new file mode 100644 index 0000000..77bf282 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_init_f32.c @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_init_f32.c + * Description: SVM Radial Basis Function Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup rbfsvm RBF SVM + + RBF SVM classifier + */ + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM radial basis function instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->gamma = gamma; +} + + + +/** + * @} end of rbfsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c new file mode 100644 index 0000000..91afcc1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f16.c @@ -0,0 +1,352 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f16.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f16); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + acc2 = vdupq_n_f16(0.0f16); + acc3 = vdupq_n_f16(0.0f16); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF16Mve(acc0)); + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)),vctp16q(4)); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f16); + acc1 = vdupq_n_f16(0.0f16); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + f16x8_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)), vctp16q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA, vecDif; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vexpq_f16(vmulq_n_f16(vtmp, -(_Float16)S->gamma)), vctp16q(1)); + + } + + + sum += (_Float16)vecAddAcrossF16Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_rbf_predict_f16( + const arm_svm_rbf_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=00.f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ((_Float16)in[j] - (_Float16) *pSupport); + pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)expf((float32_t)(-(_Float16)S->gamma * (_Float16)dot)); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c new file mode 100644 index 0000000..d3c43bf --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_rbf_predict_f32.c @@ -0,0 +1,523 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_rbf_predict_f32.c + * Description: SVM Radial Basis Function Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + + +/** + * @addtogroup rbfsvm + * @{ + */ + + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA2Vec, p0);; + vecDif = vsubq(vecIn, vecA); + acc2 = vfmaq(acc2, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc3 = vfmaq(acc3, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + + //sum += *pDualCoef++ * expf(-S->gamma * vecReduceF32Mve(acc0)); + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma))); + pDualCoef += 4; + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + f32x4_t vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif);; + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc1 = vfmaq(acc1, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(2)); + pDualCoef += 2; + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA, vecDif; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA, vecDif; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + vecDif = vsubq(vecIn, vecA); + acc0 = vfmaq(acc0, vecDif, vecDif); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vexpq_f32(vmulq_n_f32(vtmp, -S->gamma)), vctp32q(1)); + + } + + + sum += vecAddAcrossF32Mve(vSum); + *pResult = S->classes[STEP(sum)]; +} + + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" + +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t temp; + float32x4_t vec1; + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + temp = vsubq_f32(vec1, vec2a); + accuma = vmlaq_f32(accuma, temp, temp); + + temp = vsubq_f32(vec1, vec2b); + accumb = vmlaq_f32(accumb, temp, temp); + + temp = vsubq_f32(vec1, vec2c); + accumc = vmlaq_f32(accumc, temp, temp); + + temp = vsubq_f32(vec1, vec2d); + accumd = vmlaq_f32(accumd, temp, temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + SQ(*pIn - *pSupporta), dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + SQ(*pIn - *pSupportb), dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + SQ(*pIn - *pSupportc), dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + SQ(*pIn - *pSupportd), dotV,3); + + pSupporta++; + pSupportb++; + pSupportc++; + pSupportd++; + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, -S->gamma); + dotV = vexpq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + temp = vsubq_f32(vec1,vec2); + accum = vmlaq_f32(accum, temp,temp); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + + dot = dot + SQ(*pIn - *pSupport); + pIn++; + pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * expf(-S->gamma * dot); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_rbf_predict_f32( + const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + SQ(in[j] - *pSupport); + pSupport++; + } + sum += S->dualCoefficients[i] * expf(-S->gamma * dot); + } + *pResult=S->classes[STEP(sum)]; +} +#endif + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of rbfsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c new file mode 100644 index 0000000..7a27417 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f16.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float16_t intercept, + const float16_t *dualCoefficients, + const float16_t *supportVectors, + const int32_t *classes, + float16_t coef0, + float16_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c new file mode 100644 index 0000000..a7f16c2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_init_f32.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Instance Initialization + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + @ingroup groupSVM + */ + +/** + @defgroup sigmoidsvm Sigmoid SVM + + Sigmoid SVM classifier + */ + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + +/** + * @brief SVM sigmoid instance init function + * + * Classes are integer used as output of the function (instead of having -1,1 + * as class values). + * + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ) +{ + S->nbOfSupportVectors = nbOfSupportVectors; + S->vectorDimension = vectorDimension; + S->intercept = intercept; + S->dualCoefficients = dualCoefficients; + S->supportVectors = supportVectors; + S->classes = classes; + S->coef0 = coef0; + S->gamma = gamma; +} + + +/** + * @} end of sigmoidsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c new file mode 100644 index 0000000..e2d541f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f16.c @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f16.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float16_t *pSupport = S->supportVectors; + const float16_t *pSrcA = pSupport; + const float16_t *pInA0; + const float16_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float16_t *pDualCoef = S->dualCoefficients; + _Float16 sum = S->intercept; + f16x8_t vSum = vdupq_n_f16(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float16_t *pInA2, *pInA3; + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f16x8_t vecIn, acc0, acc1, acc2, acc3; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + acc2 = vdupq_n_f16(0.0f); + acc3 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 8; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 8; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc3), vtmp, 3); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)),vctp16q(4)); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float16_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f16x8_t vecIn, acc0, acc1; + float16_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + acc1 = vdupq_n_f16(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 8; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrhq_z_f16(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f16x8_t vecIn, acc0; + float16_t const *pSrcA0Vec, *pInVec; + float16_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f16(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 3; + while (blkCnt > 0U) { + f16x8_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 8; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 8; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 7; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp16q(blkCnt); + f16x8_t vecA; + + vecIn = vldrhq_z_f16(pInVec, p0); + vecA = vldrhq_z_f16(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f16x8_t vtmp = vuninitializedq_f16(); + vtmp = vsetq_lane(vecAddAcrossF16Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f16(vSum, vld1q(pDualCoef), + vtanhq_f16(vaddq_n_f16(vmulq_n_f16(vtmp, S->gamma), S->coef0)), + vctp16q(1)); + } + sum += (_Float16)vecAddAcrossF16Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +void arm_svm_sigmoid_predict_f16( + const arm_svm_sigmoid_instance_f16 *S, + const float16_t * in, + int32_t * pResult) +{ + _Float16 sum=S->intercept; + _Float16 dot=0.0f16; + uint32_t i,j; + const float16_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0.0f16; + for(j=0; j < S->vectorDimension; j++) + { + dot = (_Float16)dot + (_Float16)in[j] * (_Float16)*pSupport++; + } + sum += (_Float16)S->dualCoefficients[i] * (_Float16)tanhf((float32_t)((_Float16)S->gamma * (_Float16)dot + (_Float16)S->coef0)); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c new file mode 100644 index 0000000..37c8a08 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SVMFunctions/arm_svm_sigmoid_predict_f32.c @@ -0,0 +1,487 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_svm_sigmoid_predict_f32.c + * Description: SVM Sigmoid Classifier + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/svm_functions.h" +#include +#include + +/** + * @addtogroup sigmoidsvm + * @{ + */ + + + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + /* inlined Matrix x Vector function interleaved with dot prod */ + uint32_t numRows = S->nbOfSupportVectors; + uint32_t numCols = S->vectorDimension; + const float32_t *pSupport = S->supportVectors; + const float32_t *pSrcA = pSupport; + const float32_t *pInA0; + const float32_t *pInA1; + uint32_t row; + uint32_t blkCnt; /* loop counters */ + const float32_t *pDualCoef = S->dualCoefficients; + float32_t sum = S->intercept; + f32x4_t vSum = vdupq_n_f32(0.0f); + + row = numRows; + + /* + * compute 4 rows in parrallel + */ + while (row >= 4) { + const float32_t *pInA2, *pInA3; + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pSrcA2Vec, *pSrcA3Vec, *pInVec; + f32x4_t vecIn, acc0, acc1, acc2, acc3; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 4 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + pInA2 = pInA1 + numCols; + pInA3 = pInA2 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + acc2 = vdupq_n_f32(0.0f); + acc3 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + pSrcA2Vec = pInA2; + pSrcA3Vec = pInA3; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vld1q(pSrcA2Vec); + pSrcA2Vec += 4; + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vld1q(pSrcA3Vec); + pSrcA3Vec += 4; + acc3 = vfmaq(acc3, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA2Vec, p0); + acc2 = vfmaq(acc2, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA3Vec, p0); + acc3 = vfmaq(acc3, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc2), vtmp, 2); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc3), vtmp, 3); + + vSum = + vfmaq_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0))); + + pDualCoef += 4; + + pSrcA += numCols * 4; + /* + * Decrement the row loop counter + */ + row -= 4; + } + + /* + * compute 2 rows in parrallel + */ + if (row >= 2) { + float32_t const *pSrcA0Vec, *pSrcA1Vec, *pInVec; + f32x4_t vecIn, acc0, acc1; + float32_t const *pSrcVecPtr = in; + + /* + * Initialize the pointers to 2 consecutive MatrixA rows + */ + pInA0 = pSrcA; + pInA1 = pInA0 + numCols; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + acc1 = vdupq_n_f32(0.0f); + pSrcA0Vec = pInA0; + pSrcA1Vec = pInA1; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vld1q(pSrcA1Vec); + pSrcA1Vec += 4; + acc1 = vfmaq(acc1, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + vecA = vldrwq_z_f32(pSrcA1Vec, p0); + acc1 = vfmaq(acc1, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc1), vtmp, 1); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(2)); + + pSrcA += numCols * 2; + row -= 2; + } + + if (row >= 1) { + f32x4_t vecIn, acc0; + float32_t const *pSrcA0Vec, *pInVec; + float32_t const *pSrcVecPtr = in; + /* + * Initialize the pointers to last MatrixA row + */ + pInA0 = pSrcA; + /* + * Initialize the vector pointer + */ + pInVec = pSrcVecPtr; + /* + * reset accumulators + */ + acc0 = vdupq_n_f32(0.0f); + + pSrcA0Vec = pInA0; + + blkCnt = numCols >> 2; + while (blkCnt > 0U) { + f32x4_t vecA; + + vecIn = vld1q(pInVec); + pInVec += 4; + vecA = vld1q(pSrcA0Vec); + pSrcA0Vec += 4; + acc0 = vfmaq(acc0, vecIn, vecA); + + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = numCols & 3; + if (blkCnt > 0U) { + mve_pred16_t p0 = vctp32q(blkCnt); + f32x4_t vecA; + + vecIn = vldrwq_z_f32(pInVec, p0); + vecA = vldrwq_z_f32(pSrcA0Vec, p0); + acc0 = vfmaq(acc0, vecIn, vecA); + } + /* + * Sum the partial parts + */ + f32x4_t vtmp = vuninitializedq_f32(); + vtmp = vsetq_lane(vecAddAcrossF32Mve(acc0), vtmp, 0); + + vSum = + vfmaq_m_f32(vSum, vld1q(pDualCoef), + vtanhq_f32(vaddq_n_f32(vmulq_n_f32(vtmp, S->gamma), S->coef0)), + vctp32q(1)); + } + sum += vecAddAcrossF32Mve(vSum); + + *pResult = S->classes[STEP(sum)]; +} + +#else +#if defined(ARM_MATH_NEON) +#include "NEMath.h" + +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum = S->intercept; + + float32_t dot; + float32x4_t dotV; + + float32x4_t accuma,accumb,accumc,accumd,accum; + float32x2_t accum2; + float32x4_t vec1; + float32x4_t coef0 = vdupq_n_f32(S->coef0); + + float32x4_t vec2,vec2a,vec2b,vec2c,vec2d; + + uint32_t blkCnt; + uint32_t vectorBlkCnt; + + const float32_t *pIn = in; + + const float32_t *pSupport = S->supportVectors; + + const float32_t *pSupporta = S->supportVectors; + const float32_t *pSupportb; + const float32_t *pSupportc; + const float32_t *pSupportd; + + pSupportb = pSupporta + S->vectorDimension; + pSupportc = pSupportb + S->vectorDimension; + pSupportd = pSupportc + S->vectorDimension; + + const float32_t *pDualCoefs = S->dualCoefficients; + + vectorBlkCnt = S->nbOfSupportVectors >> 2; + while (vectorBlkCnt > 0U) + { + accuma = vdupq_n_f32(0); + accumb = vdupq_n_f32(0); + accumc = vdupq_n_f32(0); + accumd = vdupq_n_f32(0); + + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2a = vld1q_f32(pSupporta); + vec2b = vld1q_f32(pSupportb); + vec2c = vld1q_f32(pSupportc); + vec2d = vld1q_f32(pSupportd); + + pIn += 4; + pSupporta += 4; + pSupportb += 4; + pSupportc += 4; + pSupportd += 4; + + accuma = vmlaq_f32(accuma, vec1,vec2a); + accumb = vmlaq_f32(accumb, vec1,vec2b); + accumc = vmlaq_f32(accumc, vec1,vec2c); + accumd = vmlaq_f32(accumd, vec1,vec2d); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accuma),vget_high_f32(accuma)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,0); + + accum2 = vpadd_f32(vget_low_f32(accumb),vget_high_f32(accumb)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,1); + + accum2 = vpadd_f32(vget_low_f32(accumc),vget_high_f32(accumc)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,2); + + accum2 = vpadd_f32(vget_low_f32(accumd),vget_high_f32(accumd)); + dotV = vsetq_lane_f32(vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1),dotV,3); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,0) + *pIn * *pSupporta++, dotV,0); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,1) + *pIn * *pSupportb++, dotV,1); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,2) + *pIn * *pSupportc++, dotV,2); + dotV = vsetq_lane_f32(vgetq_lane_f32(dotV,3) + *pIn * *pSupportd++, dotV,3); + + pIn++; + + blkCnt -- ; + } + + vec1 = vld1q_f32(pDualCoefs); + pDualCoefs += 4; + + // To vectorize later + dotV = vmulq_n_f32(dotV, S->gamma); + dotV = vaddq_f32(dotV, coef0); + + dotV = vtanhq_f32(dotV); + + accum = vmulq_f32(vec1,dotV); + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + sum += vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + pSupporta += 3*S->vectorDimension; + pSupportb += 3*S->vectorDimension; + pSupportc += 3*S->vectorDimension; + pSupportd += 3*S->vectorDimension; + + vectorBlkCnt -- ; + } + + pSupport = pSupporta; + vectorBlkCnt = S->nbOfSupportVectors & 3; + + while (vectorBlkCnt > 0U) + { + accum = vdupq_n_f32(0); + dot = 0.0f; + pIn = in; + + blkCnt = S->vectorDimension >> 2; + while (blkCnt > 0U) + { + + vec1 = vld1q_f32(pIn); + vec2 = vld1q_f32(pSupport); + pIn += 4; + pSupport += 4; + + accum = vmlaq_f32(accum, vec1,vec2); + + blkCnt -- ; + } + accum2 = vpadd_f32(vget_low_f32(accum),vget_high_f32(accum)); + dot = vget_lane_f32(accum2, 0) + vget_lane_f32(accum2, 1); + + + blkCnt = S->vectorDimension & 3; + while (blkCnt > 0U) + { + dot = dot + *pIn++ * *pSupport++; + + blkCnt -- ; + } + + sum += *pDualCoefs++ * tanhf(S->gamma * dot + S->coef0); + vectorBlkCnt -- ; + } + + *pResult=S->classes[STEP(sum)]; +} +#else +void arm_svm_sigmoid_predict_f32( + const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult) +{ + float32_t sum=S->intercept; + float32_t dot=0; + uint32_t i,j; + const float32_t *pSupport = S->supportVectors; + + for(i=0; i < S->nbOfSupportVectors; i++) + { + dot=0; + for(j=0; j < S->vectorDimension; j++) + { + dot = dot + in[j]* *pSupport++; + } + sum += S->dualCoefficients[i] * tanhf(S->gamma * dot + S->coef0); + } + *pResult=S->classes[STEP(sum)]; +} + +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of sigmoidsvm group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt new file mode 100644 index 0000000..480985f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/CMakeLists.txt @@ -0,0 +1,117 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPStatistics) + +include(configLib) +include(configDsp) + + + +add_library(CMSISDSPStatistics STATIC) + +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_dot_prod_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_q31.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_q7.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_q7.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_q7.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_f64.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_q7.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_q15.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_q31.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_f32.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mse_f64.c) + +configLib(CMSISDSPStatistics ${ROOT}) +configDsp(CMSISDSPStatistics ${ROOT}) + +### Includes +target_include_directories(CMSISDSPStatistics PUBLIC "${DSP}/Include") + + + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPStatistics PRIVATE arm_max_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_mean_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_power_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_rms_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_std_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_var_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_entropy_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_kullback_leibler_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_dot_prod_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_logsumexp_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_max_no_idx_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_min_no_idx_f16.c) + +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmax_no_idx_f16.c) +target_sources(CMSISDSPStatistics PRIVATE arm_absmin_no_idx_f16.c) +endif() \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c new file mode 100644 index 0000000..5446992 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_entropy_f32.c" +#include "arm_entropy_f64.c" +#include "arm_kullback_leibler_f32.c" +#include "arm_kullback_leibler_f64.c" +#include "arm_logsumexp_dot_prod_f32.c" +#include "arm_logsumexp_f32.c" +#include "arm_max_f32.c" +#include "arm_max_f64.c" +#include "arm_max_q15.c" +#include "arm_max_q31.c" +#include "arm_max_q7.c" +#include "arm_max_no_idx_f32.c" +#include "arm_max_no_idx_f64.c" +#include "arm_max_no_idx_q31.c" +#include "arm_max_no_idx_q15.c" +#include "arm_max_no_idx_q7.c" +#include "arm_mean_f32.c" +#include "arm_mean_f64.c" +#include "arm_mean_q15.c" +#include "arm_mean_q31.c" +#include "arm_mean_q7.c" +#include "arm_min_f32.c" +#include "arm_min_f64.c" +#include "arm_min_q15.c" +#include "arm_min_q31.c" +#include "arm_min_q7.c" +#include "arm_min_no_idx_f32.c" +#include "arm_min_no_idx_f64.c" +#include "arm_min_no_idx_q31.c" +#include "arm_min_no_idx_q15.c" +#include "arm_min_no_idx_q7.c" +#include "arm_power_f32.c" +#include "arm_power_f64.c" +#include "arm_power_q15.c" +#include "arm_power_q31.c" +#include "arm_power_q7.c" +#include "arm_rms_f32.c" +#include "arm_rms_q15.c" +#include "arm_rms_q31.c" +#include "arm_std_f32.c" +#include "arm_std_f64.c" +#include "arm_std_q15.c" +#include "arm_std_q31.c" +#include "arm_var_f32.c" +#include "arm_var_f64.c" +#include "arm_var_q15.c" +#include "arm_var_q31.c" +#include "arm_absmax_f32.c" +#include "arm_absmax_f64.c" +#include "arm_absmax_q15.c" +#include "arm_absmax_q31.c" +#include "arm_absmax_q7.c" +#include "arm_absmin_f32.c" +#include "arm_absmin_f64.c" +#include "arm_absmin_q15.c" +#include "arm_absmin_q31.c" +#include "arm_absmin_q7.c" +#include "arm_absmax_no_idx_f32.c" +#include "arm_absmax_no_idx_f64.c" +#include "arm_absmax_no_idx_q15.c" +#include "arm_absmax_no_idx_q31.c" +#include "arm_absmax_no_idx_q7.c" +#include "arm_absmin_no_idx_f32.c" +#include "arm_absmin_no_idx_f64.c" +#include "arm_absmin_no_idx_q15.c" +#include "arm_absmin_no_idx_q31.c" +#include "arm_absmin_no_idx_q7.c" +#include "arm_mse_q7.c" +#include "arm_mse_q15.c" +#include "arm_mse_q31.c" +#include "arm_mse_f32.c" +#include "arm_mse_f64.c" diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c new file mode 100644 index 0000000..510746e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctionsF16.c @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: StatisticsFunctions.c + * Description: Combination of all statistics function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_max_f16.c" +#include "arm_min_f16.c" +#include "arm_mean_f16.c" +#include "arm_power_f16.c" +#include "arm_rms_f16.c" +#include "arm_std_f16.c" +#include "arm_var_f16.c" +#include "arm_entropy_f16.c" +#include "arm_kullback_leibler_f16.c" +#include "arm_logsumexp_dot_prod_f16.c" +#include "arm_logsumexp_f16.c" +#include "arm_max_no_idx_f16.c" +#include "arm_min_no_idx_f16.c" +#include "arm_absmax_f16.c" +#include "arm_absmin_f16.c" +#include "arm_absmax_no_idx_f16.c" +#include "arm_absmin_no_idx_f16.c" +#include "arm_mse_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c new file mode 100644 index 0000000..4241eb5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f16.c @@ -0,0 +1,274 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c new file mode 100644 index 0000000..a571ae0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f32.c @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMax Absolute Maximum + + Computes the maximum value of absolute values of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkSize = blockSize; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + do { + mve_pred16_t p = vctp32q(blkSize); + + vecSrc = vldrwq_z_f32((float32_t const *) pSrc, p); + vecSrc = vabsq_m(vuninitializedq_f32(), vecSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(vecSrc, curExtremValVec, p); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + /* Does TP detection works here ?? */ + indexVec = vidupq_wb_u32(&curIdx, 1); + + blkSize -= 4; + pSrc += 4; + } + while (blkSize > 0); + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c new file mode 100644 index 0000000..987c32c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_f64.c @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_absmax_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c new file mode 100644 index 0000000..82820c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f16.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f16.c + * Description: Maximum value of a absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMIN); + float16_t maxValue = F16_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = ((_Float16)cur_absmax > 0.0f16) ? cur_absmax : -(_Float16)cur_absmax; \ + if ((_Float16)cur_absmax > (_Float16)out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c new file mode 100644 index 0000000..13d99ba --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f32.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMIN); + float32_t maxValue = F32_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmavq(maxValue, curExtremValVec); + *pResult = maxValue; +} + + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0.0f) ? cur_absmax : -cur_absmax; \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabsf(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c new file mode 100644 index 0000000..23e3400 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_f64.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_f64.c + * Description: Maximum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_absmax_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = fabs(*pSrc++); + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c new file mode 100644 index 0000000..941f2dd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q15.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q15x8_t)curExtremValVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c new file mode 100644 index 0000000..8275a53 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q31.c @@ -0,0 +1,220 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q31x4_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c new file mode 100644 index 0000000..8eaca9b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_no_idx_q7.c @@ -0,0 +1,224 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_no_idx_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + + + +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxavq(maxValue, (q7x16_t)curExtremValVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmax_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c new file mode 100644 index 0000000..7a7816d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q15.c @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q15.c + * Description: Maximum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_ABSMIN); + q15_t maxValue = Q15_ABSMIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q15_t)__QSUB16(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c new file mode 100644 index 0000000..99b38f3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q31.c @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q31.c + * Description: Maximum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_ABSMIN); + q31_t maxValue = Q31_ABSMIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q31_t)__QSUB(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c new file mode 100644 index 0000000..1259667 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmax_q7.c @@ -0,0 +1,294 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmax_q7.c + * Description: Maximum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMax + @{ + */ + +/** + @brief Maximum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmax_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_ABSMIN); + q7_t maxValue = Q7_ABSMIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + + extremIdxVal = vqabsq(extremIdxVal); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmax_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmax_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmax_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +#if defined(ARM_MATH_DSP) +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmax, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmax to next consecutive values one by one */ \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + /* compare for the extrema value */ \ + if (cur_absmax > out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmax; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmax = *pSrc++; \ + cur_absmax = (cur_absmax > 0) ? cur_absmax : (q7_t)__QSUB8(0, cur_absmax); \ + if (cur_absmax > out) \ + { \ + out = cur_absmax; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmax_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMax group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c new file mode 100644 index 0000000..6d2ff50 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f16.c @@ -0,0 +1,276 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + p0 = vctp16q(blkCnt); + + vecSrc = vldrhq_f16(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c new file mode 100644 index 0000000..3a96322 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f32.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup AbsMin Absolute Minimum + + Computes the minimum value of absolute values of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + p0 = vctp32q(blkCnt); + + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c new file mode 100644 index 0000000..7aac970 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_absmin_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c new file mode 100644 index 0000000..62e1054 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f16.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f16.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_ABSMAX); + float16_t minValue = F16_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = ((_Float16)out > 0.0f16) ? out : -(_Float16)out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + /* compare for the extrema value */ \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = ((_Float16)cur_absmin > 0.0f16) ? cur_absmin : -(_Float16)cur_absmin; \ + if ((_Float16)cur_absmin < (_Float16)out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (_Float16)fabsf((float32_t)*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (_Float16)fabsf((float32_t)*pSrc++); + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c new file mode 100644 index 0000000..c7108da --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f32.c @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f32.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_ABSMAX); + float32_t minValue = F32_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminnmaq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminnmaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmavq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_LOOPUNROLL) +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0.0f) ? out : -out; \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0.0f) ? cur_absmin : -cur_absmin; \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = fabsf(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabsf(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +#endif /* defined(ARM_MATH_LOOPUNROLL) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c new file mode 100644 index 0000000..ac1e926 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_f64.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_f64.c + * Description: Minimum value of absolute values of a floating-point vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_absmin_no_idx_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = fabs(*pSrc++); + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = fabs(*pSrc++); + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} + +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c new file mode 100644 index 0000000..76a1788 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q15.c @@ -0,0 +1,222 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + uint16x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q15x8_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c new file mode 100644 index 0000000..b52db17 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q31.c @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + uint32x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q31x4_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c new file mode 100644 index 0000000..f60f113 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_no_idx_q7.c @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_no_idx_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + + + +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + uint8x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminaq(curExtremValVec, vecSrc); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminaq_m(curExtremValVec, vecSrc, p0); + } + /* + * Get min value across the vector + */ + minValue = vminavq(minValue, (q7x16_t)curExtremValVec); + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt; /* Loop counter */ \ + \ + \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ +} +#else +void arm_absmin_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* Loop counter */ + + + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c new file mode 100644 index 0000000..e4d0704 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q15.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q15.c + * Description: Minimum value of absolute values of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_ABSMAX); + q15_t minValue = Q15_ABSMAX; + uint16_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u16(&startIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + vecSrc = vabsq(vecSrc); + + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q15_t)__QSUB16(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q15_t)__QSUB16(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q15_t) 0x8000) ? 0x7fff : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c new file mode 100644 index 0000000..21c769b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q31.c @@ -0,0 +1,269 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q31.c + * Description: Minimum value of absolute values of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_ABSMAX); + q31_t minValue = Q31_ABSMAX; + uint16_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u32(&startIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + vecSrc = vabsq(vecSrc); + + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q31_t)__QSUB(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q31_t)__QSUB(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == INT32_MIN) ? INT32_MAX : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c new file mode 100644 index 0000000..2889891 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_absmin_q7.c @@ -0,0 +1,322 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_absmin_q7.c + * Description: Minimum value of absolute values of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup AbsMin + @{ + */ + +/** + @brief Minimum value of absolute values of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include +#include "arm_helium_utils.h" + +#define MAX_BLKSZ_S8 (UINT8_MAX+1) + +static void arm_small_blk_absmin_q7( + const q7_t *pSrc, + uint32_t blockSize, + q7_t *pResult, + uint32_t *pIndex) +{ + uint16_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_ABSMAX); + q7_t minValue = Q7_ABSMAX; + uint16_t idx = blockSize - 1; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + uint32_t startIdx = 0; + mve_pred16_t p0; + + + indexVec = vidupq_wb_u8(&startIdx, 1); + curExtremIdxVec = vdupq_n_u8(0); + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u8(&startIdx, 1); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + vecSrc = vabsq(vecSrc); + + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + idx = vminvq_p_u8(idx, curExtremIdxVec, p0); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + + +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= MAX_BLKSZ_S8) + { + arm_small_blk_absmin_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= MAX_BLKSZ_S8) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_absmin_q7(curSrc, MAX_BLKSZ_S8, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += MAX_BLKSZ_S8; + totalSize -= MAX_BLKSZ_S8; + } + /* + * remainder + */ + arm_small_blk_absmin_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * MAX_BLKSZ_S8 + curBlkPos; + *pResult = curBlkExtr; + } +} + +#else +#if defined(ARM_MATH_DSP) +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t cur_absmin, out; /* Temporary variables to store the output value. */\ + uint32_t blkCnt, outIndex; /* Loop counter */ \ + uint32_t index; /* index of maximum value */ \ + \ + /* Initialize index value to zero. */ \ + outIndex = 0U; \ + /* Load first input value that act as reference value for comparision */ \ + out = *pSrc++; \ + out = (out > 0) ? out : (q7_t)__QSUB8(0, out); \ + /* Initialize index of extrema value. */ \ + index = 0U; \ + \ + /* Loop unrolling: Compute 4 outputs at a time */ \ + blkCnt = (blockSize - 1U) >> 2U; \ + \ + while (blkCnt > 0U) \ + { \ + /* Initialize cur_absmin to next consecutive values one by one */ \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + /* compare for the extrema value */ \ + if (cur_absmin < out) \ + { \ + /* Update the extrema value and it's index */ \ + out = cur_absmin; \ + outIndex = index + 1U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 2U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 3U; \ + } \ + \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = index + 4U; \ + } \ + \ + index += 4U; \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Loop unrolling: Compute remaining outputs */ \ + blkCnt = (blockSize - 1U) % 4U; \ + \ + \ + while (blkCnt > 0U) \ + { \ + cur_absmin = *pSrc++; \ + cur_absmin = (cur_absmin > 0) ? cur_absmin : (q7_t)__QSUB8(0, cur_absmin); \ + if (cur_absmin < out) \ + { \ + out = cur_absmin; \ + outIndex = blockSize - blkCnt; \ + } \ + \ + /* Decrement loop counter */ \ + blkCnt--; \ + } \ + \ + /* Store the extrema value and it's index into destination pointers */ \ + *pResult = out; \ + *pIndex = outIndex; +} +#else +void arm_absmin_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = (*pSrc > 0) ? *pSrc : ((*pSrc == (q7_t) 0x80) ? (q7_t) 0x7f : -*pSrc); + pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_DSP) */ +#endif /* defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of AbsMin group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c new file mode 100644 index 0000000..9611fd7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f16.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Entropy Entropy + + Computes the entropy of a distribution + + */ + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum=0.0f16,p; + + + blkCnt = blockSize; + + f16x8_t vSum = vdupq_n_f16(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + f16x8_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f16(vSum, vmulq(vecIn, vlogq_f16(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * (_Float16)logf((float32_t)p); + + blkCnt--; + + } + + return (-accum); +} + +#else + +float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize) +{ + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * (_Float16)logf((float32_t)p); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c new file mode 100644 index 0000000..a2160c1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f32.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Entropy + * @{ + */ + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum=0.0f,p; + + + blkCnt = blockSize; + + f32x4_t vSum = vdupq_n_f32(0.0f); + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + f32x4_t vecIn = vld1q(pSrcA); + + vSum = vaddq_f32(vSum, vmulq(vecIn, vlogq_f32(vecIn))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + /* Tail */ + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + p = *pSrcA++; + accum += p * logf(p); + + blkCnt--; + + } + + return (-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpV, tmpV2; + + pIn = pSrcA; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + + tmpV2 = vlogq_f32(tmpV); + accumV = vmlaq_f32(accumV, tmpV, tmpV2); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize) +{ + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + p = *pIn++; + accum += p * logf(p); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Entropy group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c new file mode 100644 index 0000000..d671791 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_entropy_f64.c @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Entropy + * @{ + */ + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize) +{ + const float64_t *pIn; + uint32_t blkCnt; + float64_t accum, p; + + pIn = pSrcA; + blkCnt = blockSize; + + accum = 0.0; + + while(blkCnt > 0) + { + p = *pIn++; + + accum += p * log(p); + + blkCnt--; + + } + + return(-accum); +} + +/** + * @} end of Entropy group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c new file mode 100644 index 0000000..98ac097 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup Kullback-Leibler Kullback-Leibler divergence + + Computes the Kullback-Leibler divergence between two distributions + + */ + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + _Float16 accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f16; + + f16x8_t vSum = vdupq_n_f16(0.0f16); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecA = vld1q(pSrcA); + f16x8_t vecB = vld1q(pSrcB); + f16x8_t vRatio; + + vRatio = vdiv_f16(vecB, vecA); + vSum = vaddq_f16(vSum, vmulq(vecA, vlogq_f16(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 8; + pSrcB += 8; + blkCnt --; + } + + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * (_Float16)logf((float32_t)pB / (float32_t)pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float16_t arm_kullback_leibler_f16(const float16_t * pSrcA,const float16_t * pSrcB,uint32_t blockSize) +{ + const float16_t *pInA, *pInB; + uint32_t blkCnt; + _Float16 accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * (_Float16)logf((float32_t)pB / (float32_t)pA); + + blkCnt--; + + } + + return(-accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c new file mode 100644 index 0000000..45a9624 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f32.c @@ -0,0 +1,193 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + + +/** + * @brief Kullback-Leibler + * + * Distribution A may contain 0 with Neon version. + * Result will be right but some exception flags will be set. + * + * Distribution B must not contain 0 probability. + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t accum, pA,pB; + + + blkCnt = blockSize; + + accum = 0.0f; + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecA = vld1q(pSrcA); + f32x4_t vecB = vld1q(pSrcB); + f32x4_t vRatio; + + vRatio = vdiv_f32(vecB, vecA); + vSum = vaddq_f32(vSum, vmulq(vecA, vlogq_f32(vRatio))); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrcA += 4; + pSrcB += 4; + blkCnt --; + } + + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pSrcA++; + pB = *pSrcB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" + +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + float32x4_t accumV; + float32x2_t accumV2; + float32x4_t tmpVA, tmpVB,tmpV; + + pInA = pSrcA; + pInB = pSrcB; + + accum = 0.0f; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + tmpVA = vld1q_f32(pInA); + pInA += 4; + + tmpVB = vld1q_f32(pInB); + pInB += 4; + + tmpV = vinvq_f32(tmpVA); + tmpVB = vmulq_f32(tmpVB, tmpV); + tmpVB = vlogq_f32(tmpVB); + + accumV = vmlaq_f32(accumV, tmpVA, tmpVB); + + blkCnt--; + + } + + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB/pA); + + blkCnt--; + + } + + return(-accum); +} + +#else +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA,const float32_t * pSrcB,uint32_t blockSize) +{ + const float32_t *pInA, *pInB; + uint32_t blkCnt; + float32_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0f; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + accum += pA * logf(pB / pA); + + blkCnt--; + + } + + return(-accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of Kullback-Leibler group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c new file mode 100644 index 0000000..b43b218 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_kullback_leibler_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f64.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + +/** + * @addtogroup Kullback-Leibler + * @{ + */ + +/** + * @brief Kullback-Leibler + * + * @param[in] *pSrcA points to an array of input values for probaility distribution A. + * @param[in] *pSrcB points to an array of input values for probaility distribution B. + * @param[in] blockSize number of samples in the input array. + * @return Kullback-Leibler divergence D(A || B) + * + */ + +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, const float64_t * pSrcB, uint32_t blockSize) +{ + const float64_t *pInA, *pInB; + uint32_t blkCnt; + float64_t accum, pA,pB; + + pInA = pSrcA; + pInB = pSrcB; + blkCnt = blockSize; + + accum = 0.0; + + while(blkCnt > 0) + { + pA = *pInA++; + pB = *pInB++; + + accum += pA * log(pB / pA); + + blkCnt--; + } + + return(-accum); +} + +/** + * @} end of Kullback-Leibler group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c new file mode 100644 index 0000000..a35ac0e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f16.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupStats + */ + +/** + @defgroup LogSumExp LogSumExp + + LogSumExp optimizations to compute sum of probabilities with Gaussian distributions + + */ + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t *pTmpBuffer) +{ + float16_t result; + arm_add_f16((float16_t*)pSrcA, (float16_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f16(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c new file mode 100644 index 0000000..d2a94da --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_dot_prod_f32.c @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] *pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product. + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer) +{ + float32_t result; + arm_add_f32((float32_t*)pSrcA, (float32_t*)pSrcB, pTmpBuffer, blockSize); + + result = arm_logsumexp_f32(pTmpBuffer, blockSize); + return(result); +} + +/** + * @} end of LogSumExp group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c new file mode 100644 index 0000000..84d4843 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f16.c @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f16.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math_f16.h" + +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + float16_t maxVal; + const float16_t *pIn; + int32_t blkCnt; + _Float16 accum=0.0f16; + _Float16 tmp; + + + arm_max_no_idx_f16((float16_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f16x8_t vSum = vdupq_n_f16(0.0f16); + blkCnt = blockSize >> 3; + while(blkCnt > 0) + { + f16x8_t vecIn = vld1q(pIn); + f16x8_t vecExp; + + vecExp = vexpq_f16(vsubq_n_f16(vecIn, maxVal)); + + vSum = vaddq_f16(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 8; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF16Mve(vSum); + + blkCnt = blockSize & 0x7; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += (_Float16)expf((float32_t)((_Float16)tmp - (_Float16)maxVal)); + blkCnt--; + + } + + accum = (_Float16)maxVal + (_Float16)logf((float32_t)accum); + + return (accum); +} + +#else +float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize) +{ + _Float16 maxVal; + _Float16 tmp; + const float16_t *pIn; + uint32_t blkCnt; + _Float16 accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += (_Float16)expf((float32_t)((_Float16)tmp - (_Float16)maxVal)); + blkCnt--; + + } + accum = (_Float16)maxVal + (_Float16)logf((float32_t)accum); + + return(accum); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c new file mode 100644 index 0000000..72a5d3a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_logsumexp_f32.c @@ -0,0 +1,277 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_logsumexp_f32.c + * Description: LogSumExp + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#include +#include + + +/** + * @addtogroup LogSumExp + * @{ + */ + + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_math.h" + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + const float32_t *pIn; + int32_t blkCnt; + float32_t accum=0.0f; + float32_t tmp; + + + arm_max_no_idx_f32((float32_t *) in, blockSize, &maxVal); + + + blkCnt = blockSize; + pIn = in; + + + f32x4_t vSum = vdupq_n_f32(0.0f); + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + f32x4_t vecIn = vld1q(pIn); + f32x4_t vecExp; + + vecExp = vexpq_f32(vsubq_n_f32(vecIn, maxVal)); + + vSum = vaddq_f32(vSum, vecExp); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pIn += 4; + blkCnt --; + } + + /* sum + log */ + accum = vecAddAcrossF32Mve(vSum); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return (accum); +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + float32x4_t tmpV, tmpVb; + float32x4_t maxValV; + uint32x4_t idxV; + float32x4_t accumV; + float32x2_t accumV2; + + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + + blkCnt = blockSize; + + if (blockSize <= 3) + { + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + } + else + { + maxValV = vld1q_f32(pIn); + pIn += 4; + blkCnt = (blockSize - 4) >> 2; + + while(blkCnt > 0) + { + tmpVb = vld1q_f32(pIn); + pIn += 4; + + idxV = vcgtq_f32(tmpVb, maxValV); + maxValV = vbslq_f32(idxV, tmpVb, maxValV ); + + blkCnt--; + } + + accumV2 = vpmax_f32(vget_low_f32(maxValV),vget_high_f32(maxValV)); + accumV2 = vpmax_f32(accumV2,accumV2); + maxVal = vget_lane_f32(accumV2, 0) ; + + blkCnt = (blockSize - 4) & 3; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + } + + } + + + + maxValV = vdupq_n_f32(maxVal); + pIn = in; + accum = 0; + accumV = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + + while(blkCnt > 0) + { + tmpV = vld1q_f32(pIn); + pIn += 4; + tmpV = vsubq_f32(tmpV, maxValV); + tmpV = vexpq_f32(tmpV); + accumV = vaddq_f32(accumV, tmpV); + + blkCnt--; + + } + accumV2 = vpadd_f32(vget_low_f32(accumV),vget_high_f32(accumV)); + accum = vget_lane_f32(accumV2, 0) + vget_lane_f32(accumV2, 1); + + blkCnt = blockSize & 0x3; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + + accum = maxVal + logf(accum); + + return(accum); +} +#else +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize) +{ + float32_t maxVal; + float32_t tmp; + const float32_t *pIn; + uint32_t blkCnt; + float32_t accum; + + pIn = in; + blkCnt = blockSize; + + maxVal = *pIn++; + blkCnt--; + + while(blkCnt > 0) + { + tmp = *pIn++; + + if (tmp > maxVal) + { + maxVal = tmp; + } + blkCnt--; + + } + + blkCnt = blockSize; + pIn = in; + accum = 0; + while(blkCnt > 0) + { + tmp = *pIn++; + accum += expf(tmp - maxVal); + blkCnt--; + + } + accum = maxVal + logf(accum); + + return(accum); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of LogSumExp group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c new file mode 100644 index 0000000..b5017f1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f16.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f16.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float16_t tmp; + + + indexVec = vidupq_wb_u16(&curIdx, 1); + curExtremIdxVec = vdupq_n_u16(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u16(&curIdx, 1); + + pSrc += 8; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 7; + + while (blkCnt > 0) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +void arm_max_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if ((_Float16)out < (_Float16)maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)out < (_Float16)maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c new file mode 100644 index 0000000..d82b039 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c @@ -0,0 +1,365 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f32.c + * Description: Maximum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + +/** + @defgroup Max Maximum + + Computes the maximum value of an array of data. + The function returns both the maximum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + uint32_t curIdx = 0; + mve_pred16_t p0; + float32_t tmp; + + + indexVec = vidupq_wb_u32(&curIdx, 1); + curExtremIdxVec = vdupq_n_u32(0); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = vidupq_wb_u32(&curIdx, 1); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpgeq(curExtremValVec, maxValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize tmp to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < tmp) + { + /* Update the maximum value and it's index */ + maxValue = tmp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* + * Save result + */ + *pIndex = idx; + *pResult = maxValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + uint32x4_t maxIdx; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(ULONG_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcgtq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmax_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmax_f32(outV2,outV2); + out = vget_lane_f32(outV2, 0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c new file mode 100644 index 0000000..8361219 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_f64.c + * Description: Maximum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +void arm_max_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c new file mode 100644 index 0000000..f989f60 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f16.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f16.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MIN); + float16_t maxValue = F16_MIN; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t maxValue = F16_MIN; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if ((_Float16)maxValue < (_Float16)newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c new file mode 100644 index 0000000..9a2a015 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f32.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MIN); + float32_t maxValue = F32_MIN; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane max. + */ + curExtremValVec = vmaxnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get max value across the vector + */ + maxValue = vmaxnmvq(maxValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blkCnt --; + } + + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t maxValue = F32_MIN; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c new file mode 100644 index 0000000..7eca31c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ +void arm_max_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t maxValue = F64_MIN; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the maximum value */ + if (maxValue < newVal) + { + /* Update the maximum value and it's index */ + maxValue = newVal; + } + + blockSize --; + } + + *pResult = maxValue; +} + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c new file mode 100644 index 0000000..2adea1a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q15.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q15.c + * Description: Maximum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c new file mode 100644 index 0000000..9c7a425 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q31.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q31.c + * Description: Maximum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else +void arm_max_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c new file mode 100644 index 0000000..a6a61b7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_no_idx_q7.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_no_idx_q7.c + * Description: Maximum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane max. + */ + curExtremValVec = vmaxq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + curExtremValVec = vmaxq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get max value across the vector + */ + maxValue = vmaxvq(maxValue, curExtremValVec); + *pResult = maxValue; +} + +#else + +void arm_max_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal1) + { + /* Update the maximum value */ + out = maxVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the maximum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c new file mode 100644 index 0000000..5715e37 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c @@ -0,0 +1,201 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q15.c + * Description: Maximum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MIN); + q15_t maxValue = Q15_MIN; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c new file mode 100644 index 0000000..fed900b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q31.c + * Description: Maximum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MIN); + q31_t maxValue = Q31_MIN; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = maxValue; +} + +#else +void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c new file mode 100644 index 0000000..5deae64 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c @@ -0,0 +1,256 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_max_q7.c + * Description: Maximum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Max + @{ + */ + +/** + @brief Maximum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @param[out] pIndex index of maximum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_small_blk_max_q7( + const q7_t * pSrc, + uint16_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t extremValVec = vdupq_n_s8(Q7_MIN); + q7_t maxValue = Q7_MIN; + uint8x16_t indexVec; + uint8x16_t extremIdxVec; + mve_pred16_t p0; + uint8_t extremIdxArr[16]; + + indexVec = vidupq_u8(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp8q(blkCnt); + q7x16_t extremIdxVal = vld1q_z_s8(pSrc, p); + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpgeq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u8(extremIdxArr, indexVec, p0); + + indexVec += 16; + pSrc += 16; + blkCnt -= 16; + } + while (blkCnt > 0); + + + /* Get max value across the vector */ + maxValue = vmaxvq(maxValue, extremValVec); + + /* set index for lower values to max possible index */ + p0 = vcmpgeq(extremValVec, maxValue); + extremIdxVec = vld1q_u8(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u8(blockSize - 1), p0); + *pIndex = vminvq_u8(blockSize - 1, indexVec); + *pResult = maxValue; +} + +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + const uint16_t sub_blk_sz = UINT8_MAX + 1; + + if (totalSize <= sub_blk_sz) + { + arm_small_blk_max_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MIN; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= sub_blk_sz) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_max_q7(curSrc, sub_blk_sz, pResult, pIndex); + if (*pResult > curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += sub_blk_sz; + totalSize -= sub_blk_sz; + } + /* + * remainder + */ + arm_small_blk_max_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult > curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * sub_blk_sz + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t maxVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = index + 1U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 2U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 3U; + } + + maxVal = *pSrc++; + if (out < maxVal) + { + out = maxVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal = *pSrc++; + + /* compare for the maximum value */ + if (out < maxVal) + { + /* Update the maximum value and it's index */ + out = maxVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Max group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c new file mode 100644 index 0000000..d296482 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f16.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup mean Mean + + Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector. + The underlying algorithm is used: + + 
+      Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+
+ + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + sumVec = vaddq_m_f16(sumVec, sumVec, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = (_Float16)vecAddAcrossF16Mve(sumVec) / (_Float16) blockSize; +} + + +#else + +void arm_mean_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float16_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + sum += (_Float16)*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += (_Float16)*pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = ((_Float16)sum / (_Float16)blockSize); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c new file mode 100644 index 0000000..dd6d817 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c @@ -0,0 +1,198 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f32.c + * Description: Mean value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + sumVec = vaddq_f32(sumVec, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum / (float32_t) blockSize; +} + + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + + uint32_t blkCnt; /* Loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + inV = vld1q_f32(pSrc); + sumV = vaddq_f32(sumV, inV); + + pSrc += 4; + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = sum / (float32_t) blockSize; +} +#else +void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c new file mode 100644 index 0000000..72e6f35 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_f64.c + * Description: Mean value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a floating-point vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult mean value returned here. + @return none + */ +void arm_mean_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (sum / blockSize); +} + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c new file mode 100644 index 0000000..54949a1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q15.c + * Description: Mean value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.15 format and is accumulated in a 32-bit + accumulator in 17.15 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.15 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q31_t sum = 0L; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 0x7; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q15x2_ia (&pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + in = read_q15x2_ia (&pSrc); + sum += ((in << 16U) >> 16U); + sum += (in >> 16U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q15_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c new file mode 100644 index 0000000..b33ed00 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q31.c + * Description: Mean value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format and is accumulated in a 64-bit + accumulator in 33.31 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.31 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* Tail */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + blkCnt --; + } + + *pResult = arm_div_q63_to_q31(sum, blockSize); +} +#else +void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + sum += *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q31_t) (sum / blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c new file mode 100644 index 0000000..f0701eb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mean_q7.c + * Description: Mean value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup mean + @{ + */ + +/** + @brief Mean value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format and is accumulated in a 32-bit + accumulator in 25.7 format. + There is no risk of internal overflow with this approach, and the + full precision of intermediate result is preserved. + Finally, the accumulator is truncated to yield a result of 1.7 format. + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0L; + + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vaddvaq(sum, vecSrc); + + blkCnt--; + pSrc += 16; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store the result to the destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#else +void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + in = read_q7x4_ia (&pSrc); + sum += ((in << 24U) >> 24U); + sum += ((in << 16U) >> 24U); + sum += ((in << 8U) >> 24U); + sum += (in >> 24U); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + sum += *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + /* Store result to destination */ + *pResult = (q7_t) (sum / (int32_t) blockSize); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of mean group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c new file mode 100644 index 0000000..3ff9db4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f16.c @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f16.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + float16_t const *pSrcVec; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + uint32_t idx = blockSize; + uint16x8_t indexVec; + uint16x8_t curExtremIdxVec; + mve_pred16_t p0; + + indexVec = vidupq_u16((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u16(0); + + pSrcVec = (float16_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vldrhq_f16(pSrcVec); pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(vecSrc, curExtremValVec, p0); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u16(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else + +void arm_min_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult, + uint32_t * pIndex) +{ + float16_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if ((_Float16)out > (_Float16)minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)out > (_Float16)minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c new file mode 100644 index 0000000..ad8a472 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c @@ -0,0 +1,363 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f32.c + * Description: Minimum value of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + + +/** + @ingroup groupStats + */ + +/** + @defgroup Min Minimum + + Computes the minimum value of an array of data. + The function returns both the minimum value and its position within the array. + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + float32_t const *pSrcVec; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + uint32_t idx = blockSize; + uint32x4_t indexVec; + uint32x4_t curExtremIdxVec; + float32_t tmp; + mve_pred16_t p0; + + indexVec = vidupq_u32((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u32(0); + + pSrcVec = (float32_t const *) pSrc; + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrcVec); + pSrcVec += 4; + /* + * Get current max per lane and current index per lane + * when a max is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + /* + * set index for lower values to max possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u32(blockSize), p0); + /* + * Get min index which is thus for a max value + */ + idx = vminvq(idx, indexVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + tmp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > tmp) + { + /* Update the minimum value and it's index */ + minValue = tmp; + idx = blockSize - blkCnt; + } + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t maxVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* loop counter */ + + float32x4_t outV, srcV; + float32x2_t outV2; + + uint32x4_t idxV; + static const uint32_t indexInit[4]={4,5,6,7}; + static const uint32_t countVInit[4]={0,1,2,3}; + uint32x4_t maxIdx; + uint32x4_t index; + uint32x4_t delta; + uint32x4_t countV; + uint32x2_t countV2; + + maxIdx = vdupq_n_u32(ULONG_MAX); + delta = vdupq_n_u32(4); + index = vld1q_u32(indexInit); + countV = vld1q_u32(countVInit); + + /* Initialise the index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparison */ + if (blockSize <= 3) + { + out = *pSrc++; + + blkCnt = blockSize - 1; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + outV = vld1q_f32(pSrc); + pSrc += 4; + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize - 4 ) >> 2U; + + while (blkCnt > 0U) + { + srcV = vld1q_f32(pSrc); + pSrc += 4; + + idxV = vcltq_f32(srcV, outV); + outV = vbslq_f32(idxV, srcV, outV ); + countV = vbslq_u32(idxV, index,countV ); + + index = vaddq_u32(index,delta); + + /* Decrement the loop counter */ + blkCnt--; + } + + outV2 = vpmin_f32(vget_low_f32(outV),vget_high_f32(outV)); + outV2 = vpmin_f32(outV2,outV2); + out = vget_lane_f32(outV2,0); + + idxV = vceqq_f32(outV, vdupq_n_f32(out)); + countV = vbslq_u32(idxV, countV,maxIdx); + + countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV)); + countV2 = vpmin_u32(countV2,countV2); + outIndex = vget_lane_u32(countV2,0); + + /* if (blockSize - 1U) is not multiple of 4 */ + blkCnt = (blockSize - 4 ) % 4U; + + while (blkCnt > 0U) + { + /* Initialize maxVal to the next consecutive values one by one */ + maxVal1 = *pSrc++; + + /* compare for the maximum value */ + if (out > maxVal1) + { + /* Update the maximum value and it's index */ + out = maxVal1; + outIndex = blockSize - blkCnt ; + } + + /* Decrement the loop counter */ + blkCnt--; + } + } + + /* Store the maximum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#else +void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex) +{ + float32_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c new file mode 100644 index 0000000..ef25f92 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f64.c @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_f64.c + * Description: Minimum value of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +void arm_min_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult, + uint32_t * pIndex) +{ + float64_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + + /* Initialise index value to zero. */ + outIndex = 0U; + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c new file mode 100644 index 0000000..5b4c0d6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f16.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f16.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + f16x8_t vecSrc; + f16x8_t curExtremValVec = vdupq_n_f16(F16_MAX); + float16_t minValue = F16_MAX; + float16_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 3U; + + while (blkCnt > 0U) + { + + vecSrc = vldrhq_f16(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f16( + const float16_t *pSrc, + uint32_t blockSize, + float16_t *pResult) +{ + float16_t minValue = F16_MAX; + float16_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if ((_Float16)minValue > (_Float16)newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c new file mode 100644 index 0000000..ea7c137 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f32.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f32.c + * Description: Minimum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE) +#include +#endif + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + f32x4_t vecSrc; + f32x4_t curExtremValVec = vdupq_n_f32(F32_MAX); + float32_t minValue = F32_MAX; + float32_t newVal; + uint32_t blkCnt; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * update per-lane min. + */ + curExtremValVec = vminnmq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + blkCnt --; + } + /* + * Get min value across the vector + */ + minValue = vminnmvq(minValue, curExtremValVec); + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blkCnt --; + } + + *pResult = minValue; +} + +#else + +void arm_min_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult) +{ + float32_t minValue = F32_MAX; + float32_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c new file mode 100644 index 0000000..6e69572 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_f64.c @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_f64.c + * Description: Maximum value of a floating-point vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +void arm_min_no_idx_f64( + const float64_t *pSrc, + uint32_t blockSize, + float64_t *pResult) +{ + float64_t minValue = F64_MAX; + float64_t newVal; + + while (blockSize > 0U) + { + newVal = *pSrc++; + + /* compare for the minimum value */ + if (minValue > newVal) + { + /* Update the minimum value and it's index */ + minValue = newVal; + } + + blockSize --; + } + + *pResult = minValue; +} + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c new file mode 100644 index 0000000..207f9ea --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q15.c @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q15.c + * Description: Minimum value of a q15 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q15 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q15_t const *pSrcVec; + q15x8_t curExtremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + mve_pred16_t p0; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 8; + p0 = vctp16q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c new file mode 100644 index 0000000..e425db4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q31.c + * Description: Minimum value of a q31 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q31 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q31_t const *pSrcVec; + q31x4_t curExtremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + mve_pred16_t p0; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + if (blkCnt > 0) + { + vecSrc = vldrwq_s32(pSrcVec); + pSrcVec += 4; + p0 = vctp32q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c new file mode 100644 index 0000000..2ee9a99 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_no_idx_q7.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_no_idx_q7.c + * Description: Minimum value of a q7 vector without returning the index + * + * $Date: 16 November 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + + +/** + @ingroup groupStats + */ + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a q7 vector without index. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7_t const *pSrcVec; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX; + mve_pred16_t p0; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + /* + * update per-lane min. + */ + curExtremValVec = vminq(vecSrc, curExtremValVec); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0) + { + vecSrc = vld1q(pSrcVec); + pSrcVec += 16; + p0 = vctp8q(blkCnt); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + curExtremValVec = vminq_m(curExtremValVec, vecSrc, curExtremValVec, p0); + } + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + *pResult = minValue; +} + +#else +void arm_min_no_idx_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult) +{ + q7_t minVal1, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt; /* loop counter */ + + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + + blkCnt = (blockSize - 1U); + + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal1 = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal1) + { + /* Update the minimum value */ + out = minVal1; + } + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the minimum value into destination pointer */ + *pResult = out; +} + +#endif /* #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) */ +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c new file mode 100644 index 0000000..f31019d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q15.c + * Description: Minimum value of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + + int32_t blkCnt; /* loop counters */ + q15x8_t extremValVec = vdupq_n_s16(Q15_MAX); + q15_t minValue = Q15_MAX; + uint16x8_t indexVec; + uint16x8_t extremIdxVec; + mve_pred16_t p0; + uint16_t extremIdxArr[8]; + + indexVec = vidupq_u16(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + q15x8_t extremIdxVal = vld1q_z_s16(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u16(extremIdxArr, indexVec, p0); + + indexVec += 8; + pSrc += 8; + blkCnt -= 8; + } + while (blkCnt > 0); + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u16(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u16(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; + +} +#else +void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex) +{ + q15_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c new file mode 100644 index 0000000..c993004 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q31.c + * Description: Minimum value of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + int32_t blkCnt; /* loop counters */ + q31x4_t extremValVec = vdupq_n_s32(Q31_MAX); + q31_t minValue = Q31_MAX; + uint32x4_t indexVec; + uint32x4_t extremIdxVec; + mve_pred16_t p0; + uint32_t extremIdxArr[4]; + + indexVec = vidupq_u32(0U, 1); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp32q(blkCnt); + q31x4_t extremIdxVal = vld1q_z_s32(pSrc, p); + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq_m(extremIdxVal, extremValVec, p); + + extremValVec = vorrq_m(extremValVec, extremIdxVal, extremIdxVal, p0); + /* store per-lane extrema indexes */ + vst1q_p_u32(extremIdxArr, indexVec, p0); + + indexVec += 4; + pSrc += 4; + blkCnt -= 4; + } + while (blkCnt > 0); + + + /* Get min value across the vector */ + minValue = vminvq(minValue, extremValVec); + + /* set index for lower values to min possible index */ + p0 = vcmpleq(extremValVec, minValue); + extremIdxVec = vld1q_u32(extremIdxArr); + + indexVec = vpselq(extremIdxVec, vdupq_n_u32(blockSize - 1), p0); + *pIndex = vminvq(blockSize - 1, indexVec); + *pResult = minValue; +} + +#else +void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex) +{ + q31_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c new file mode 100644 index 0000000..3e5aae5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_min_q7.c + * Description: Minimum value of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup Min + @{ + */ + +/** + @brief Minimum value of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult minimum value returned here + @param[out] pIndex index of minimum value returned here + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +static void arm_small_blk_min_q7( + const q7_t * pSrc, + uint8_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q7x16_t curExtremValVec = vdupq_n_s8(Q7_MAX); + q7_t minValue = Q7_MAX,temp; + uint32_t idx = blockSize; + uint8x16_t indexVec; + uint8x16_t curExtremIdxVec; + mve_pred16_t p0; + + + indexVec = vidupq_u8((uint32_t)0, 1); + curExtremIdxVec = vdupq_n_u8(0); + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + pSrc += 16; + /* + * Get current min per lane and current index per lane + * when a min is selected + */ + p0 = vcmpleq(vecSrc, curExtremValVec); + curExtremValVec = vpselq(vecSrc, curExtremValVec, p0); + curExtremIdxVec = vpselq(indexVec, curExtremIdxVec, p0); + + indexVec = indexVec + 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * Get min value across the vector + */ + minValue = vminvq(minValue, curExtremValVec); + /* + * set index for lower values to min possible index + */ + p0 = vcmpleq(curExtremValVec, minValue); + indexVec = vpselq(curExtremIdxVec, vdupq_n_u8(blockSize), p0); + /* + * Get min index which is thus for a min value + */ + idx = vminvq(idx, indexVec); + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + temp = *pSrc++; + + /* compare for the minimum value */ + if (minValue > temp) + { + /* Update the minimum value and it's index */ + minValue = temp; + idx = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + /* + * Save result + */ + *pIndex = idx; + *pResult = minValue; +} + +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + int32_t totalSize = blockSize; + + if (totalSize <= UINT8_MAX) + { + arm_small_blk_min_q7(pSrc, blockSize, pResult, pIndex); + } + else + { + uint32_t curIdx = 0; + q7_t curBlkExtr = Q7_MAX; + uint32_t curBlkPos = 0; + uint32_t curBlkIdx = 0; + /* + * process blocks of 255 elts + */ + while (totalSize >= UINT8_MAX) + { + const q7_t *curSrc = pSrc; + + arm_small_blk_min_q7(curSrc, UINT8_MAX, pResult, pIndex); + if (*pResult < curBlkExtr) + { + /* + * update partial extrema + */ + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + curIdx++; + pSrc += UINT8_MAX; + totalSize -= UINT8_MAX; + } + /* + * remainder + */ + arm_small_blk_min_q7(pSrc, totalSize, pResult, pIndex); + if (*pResult < curBlkExtr) + { + curBlkExtr = *pResult; + curBlkPos = *pIndex; + curBlkIdx = curIdx; + } + *pIndex = curBlkIdx * UINT8_MAX + curBlkPos; + *pResult = curBlkExtr; + } +} +#else +void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex) +{ + q7_t minVal, out; /* Temporary variables to store the output value. */ + uint32_t blkCnt, outIndex; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + uint32_t index; /* index of maximum value */ +#endif + + /* Initialise index value to zero. */ + outIndex = 0U; + /* Load first input value that act as reference value for comparision */ + out = *pSrc++; + +#if defined (ARM_MATH_LOOPUNROLL) + /* Initialise index of maximum value. */ + index = 0U; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize - 1U) >> 2U; + + while (blkCnt > 0U) + { + /* Initialize minVal to next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = index + 1U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 2U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 3U; + } + + minVal = *pSrc++; + if (out > minVal) + { + out = minVal; + outIndex = index + 4U; + } + + index += 4U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize - 1U) % 4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = (blockSize - 1U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* Initialize minVal to the next consecutive values one by one */ + minVal = *pSrc++; + + /* compare for the minimum value */ + if (out > minVal) + { + /* Update the minimum value and it's index */ + out = minVal; + outIndex = blockSize - blkCnt; + } + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store the minimum value and it's index into destination pointers */ + *pResult = out; + *pIndex = outIndex; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Min group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c new file mode 100644 index 0000000..3b192dd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f16.c @@ -0,0 +1,203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f16.c + * Description: Half floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two half floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVE_FLOAT16) +#include "arm_helium_utils.h" + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + float16x8_t vecA, vecB; + float16x8_t vecSum; + uint32_t blkCnt; + _Float16 sum = 0.0f16; + vecSum = vdupq_n_f16(0.0f16); + + blkCnt = (blockSize) >> 3; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 8; + + vecB = vld1q(pSrcB); + pSrcB += 8; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF16Mve(vecSum); + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; + +} + +#endif + + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + +#if defined(ARM_FLOAT16_SUPPORTED) + +#if (!defined(ARM_MATH_MVE_FLOAT16)) || defined(ARM_MATH_AUTOVECTORIZE) + + + +void arm_mse_f16( + const float16_t * pSrcA, + const float16_t * pSrcB, + uint32_t blockSize, + float16_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 inA, inB; + _Float16 sum = 0.0f16; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 3; + + + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 7; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = (_Float16)inA - (_Float16)inB; + sum += (_Float16)inA * (_Float16)inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = (_Float16)sum / (_Float16)blockSize; +} + +#endif /* end of test for vector instruction availability */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c new file mode 100644 index 0000000..1c592f5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f32.c @@ -0,0 +1,247 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f32.c + * Description: Floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + +#if !defined(ARM_MATH_AUTOVECTORIZE) + +#if defined(ARM_MATH_MVEF) +#include "arm_helium_utils.h" + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q(pSrcA); + pSrcA += 4; + + vecB = vld1q(pSrcB); + pSrcB += 4; + + vecA = vsubq(vecA, vecB); + + vecSum = vfmaq(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + + + blkCnt = (blockSize) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecA = vld1q(pSrcA); + vecB = vld1q(pSrcB); + + vecA = vsubq(vecA, vecB); + vecSum = vfmaq_m(vecSum, vecA, vecA, p0); + } + + sum = vecAddAcrossF32Mve(vecSum); + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} + +#endif + +#if defined(ARM_MATH_NEON) +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + float32x4_t vecA, vecB; + float32x4_t vecSum; + uint32_t blkCnt; + float32_t inA, inB; + float32_t sum = 0.0f; + vecSum = vdupq_n_f32(0.0f); +#if !defined(__aarch64__) + f32x2_t tmp = vdup_n_f32(0.0f); +#endif + + /* Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + while (blkCnt > 0U) + { + vecA = vld1q_f32(pSrcA); + pSrcA += 4; + + vecB = vld1q_f32(pSrcB); + pSrcB += 4; + + vecA = vsubq_f32(vecA, vecB); + + vecSum = vfmaq_f32(vecSum, vecA, vecA); + /* + * Decrement the blockSize loop counter + */ + blkCnt --; + } + +#if defined(__aarch64__) + sum = vpadds_f32(vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum))); +#else + tmp = vpadd_f32(vget_low_f32(vecSum), vget_high_f32(vecSum)); + sum = vget_lane_f32(tmp, 0) + vget_lane_f32(tmp, 1); + +#endif + + blkCnt = (blockSize) & 3; + while (blkCnt > 0U) + { + /* Calculate dot product and store result in a temporary buffer. */ + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; + +} +#endif + +#endif /*#if !defined(ARM_MATH_AUTOVECTORIZE)*/ + + + +#if (!defined(ARM_MATH_MVEF) && !defined(ARM_MATH_NEON)) || defined(ARM_MATH_AUTOVECTORIZE) + + +void arm_mse_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float32_t inA, inB; + float32_t sum = 0.0f; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = (blockSize) >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 3; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + +#endif /* end of test for vector instruction availability */ + +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c new file mode 100644 index 0000000..b785bf8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_f64.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_f64.c + * Description: Double floating point mean square error + * + * $Date: 05 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two double floating point vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] result mean square error + @return none + */ + + + + + +void arm_mse_f64( + const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize, + float64_t * result) + +{ + uint32_t blkCnt; /* Loop counter */ + float64_t inA, inB; + float64_t sum = 0.0; /* Temporary return variable */ +#if defined (ARM_MATH_LOOPUNROLL) + blkCnt = (blockSize) >> 1; + + + while (blkCnt > 0U) + { + + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = (blockSize) & 1; +#else + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; +#endif + while (blkCnt > 0U) + { + inA = *pSrcA++; + inB = *pSrcB++; + inA = inA - inB; + sum += inA * inA; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in destination buffer */ + *result = sum / blockSize; +} + + +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c new file mode 100644 index 0000000..9e6f0c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q15.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q15.c + * Description: Mean square error between two Q15 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q15 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 8; + pSrcB += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmlaldavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#else +void arm_mse_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q15_t) __SSAT(((q31_t) inA - (q31_t)inB), 16); + sum += (q63_t)((q31_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q15 format */ + *pResult = (q15_t) __SSAT((q31_t) (sum / blockSize)>>13, 16); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c new file mode 100644 index 0000000..e444404 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q31.c @@ -0,0 +1,176 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q31.c + * Description: Mean square error between two Q31 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q31 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrcA,vecSrcB; + q63_t sum = 0LL; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 4; + pSrcB += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vrmlaldavhaq_p(sum, vecSrcA, vecSrcA, p0); + } + + + *pResult = (q31_t) ((sum / blockSize)>>21); + +} +#else +void arm_mse_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + + q31_t inA32,inB32; /* Temporary variable to store packed input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA32 = *pSrcA++ >> 1; + inB32 = *pSrcB++ >> 1; + inA32 = __QSUB(inA32, inB32); + sum += ((q63_t) inA32 * inA32) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q31 format */ + *pResult = (q31_t) ((sum / blockSize)>>15); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c new file mode 100644 index 0000000..298e9da --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mse_q7.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mse_q7.c + * Description: Mean square error between two Q7 vectors + * + * $Date: 04 April 2022 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2022 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup MSE Mean Square Error + + Calculates the mean square error between two vectors. + + */ + +/** + @addtogroup MSE + @{ + */ + +/** + @brief Mean square error between two Q7 vectors. + @param[in] pSrcA points to the first input vector + @param[in] pSrcB points to the second input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult mean square error + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrcA,vecSrcB; + q31_t sum = 0LL; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrcA, vecSrcA); + + blkCnt--; + pSrcA += 16; + pSrcB += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp8q(blkCnt); + vecSrcA = vld1q(pSrcA); + vecSrcB = vld1q(pSrcB); + + vecSrcA = vshrq(vecSrcA,1); + vecSrcB = vshrq(vecSrcB,1); + + vecSrcA = vqsubq(vecSrcA,vecSrcB); + + sum = vmladavaq_p(sum, vecSrcA, vecSrcA, p0); + } + + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8); +} +#else +void arm_mse_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q7_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t inA,inB; /* Temporary variable to store input value */ + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + inA = *pSrcA++ >> 1; + inB = *pSrcB++ >> 1; + + inA = (q7_t) __SSAT((q15_t) inA - (q15_t)inB, 8); + sum += ((q15_t) inA * inA); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in q7 format */ + *pResult = (q7_t) __SSAT((q15_t) (sum / blockSize)>>5, 8);; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of MSE group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c new file mode 100644 index 0000000..fd135eb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f16.c @@ -0,0 +1,152 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f16.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f); + + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + *pResult = vecAddAcrossF16Mve(sumVec); +} +#else + +void arm_power_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c new file mode 100644 index 0000000..ce12e57 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c @@ -0,0 +1,229 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f32.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup power Power + + Calculates the sum of the squares of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + + Since the result is not divided by the length, those functions are in fact computing + something which is more an energy than a power. + + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t sum = 0.0f; + float32_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result to the destination */ + *pResult = sum; +} +#else +void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c new file mode 100644 index 0000000..057e9f7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f64.c @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_f64.c + * Description: Sum of the squares of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + */ +void arm_power_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t in; /* Temporary variable to store input value */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result to destination */ + *pResult = sum; +} + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c new file mode 100644 index 0000000..2c47f0b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q15.c + * Description: Sum of the squares of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 34.30 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sum = 0LL; + q15_t in; + + /* Compute 8 outputs at a time */ + blkCnt = blockSize >> 3U; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* + * sum lanes + */ + sum = vmlaldavaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* + * tail + */ + blkCnt = blockSize & 0x7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 34.30 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c new file mode 100644 index 0000000..a39b3a7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q31.c + * Description: Sum of the squares of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.31 format. + Intermediate multiplication yields a 2.62 format, and this + result is truncated to 2.48 format by discarding the lower 14 bits. + The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + With 15 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 16.48 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sum = 0LL; + q31_t in; + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* + * sum lanes + */ + sum = vrmlaldavhaq(sum, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 8; + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = asrl(sum, 6); +} +#else +void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q63_t) in * in) >> 14U; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store results in 16.48 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c new file mode 100644 index 0000000..0545f7c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c @@ -0,0 +1,180 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_power_q7.c + * Description: Sum of the squares of the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup power + @{ + */ + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult sum of the squares value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 32-bit internal accumulator. + The input is represented in 1.7 format. + Intermediate multiplication yields a 2.14 format, and this + result is added without saturation to an accumulator in 18.14 format. + With 17 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the return result is in 18.14 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecSrc; + q31_t sum = 0LL; + q7_t in; + + /* Compute 16 outputs at a time */ + blkCnt = blockSize >> 4U; + while (blkCnt > 0U) + { + vecSrc = vldrbq_s8(pSrc); + /* + * sum lanes + */ + sum = vmladavaq(sum, vecSrc, vecSrc); + + blkCnt--; + pSrc += 16; + } + + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + *pResult = sum; +} +#else +void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Temporary result storage */ + q7_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store packed input value */ + q31_t in1, in2; /* Temporary variables to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q7x4_ia (&pSrc); + + in1 = __SXTB16(__ROR(in32, 8)); + in2 = __SXTB16(in32); + + /* calculate power and accumulate to accumulator */ + sum = __SMLAD(in1, in1, sum); + sum = __SMLAD(in2, in2, sum); +#else + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); + + in = *pSrc++; + sum += ((q15_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute Power and store result in a temporary variable, sum. */ + in = *pSrc++; + sum += ((q15_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Store result in 18.14 format */ + *pResult = sum; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of power group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c new file mode 100644 index 0000000..42a00ef --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f16.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f16.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t pow = 0.0f; + + arm_power_f16(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f16((_Float16)pow / (_Float16) blockSize, pResult); +} +#else + +void arm_rms_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f16; /* Temporary result storage */ + _Float16 in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f16((_Float16)sum / (_Float16) blockSize, pResult); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c new file mode 100644 index 0000000..cb45752 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_f32.c + * Description: Root mean square value of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup RMS Root mean square (RMS) + + Calculates the Root Mean Square of the elements in the input vector. + The underlying algorithm is used: + + 
+      Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t pow = 0.0f; + + arm_power_f32(pSrc, blockSize, &pow); + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(pow / (float32_t) blockSize, pResult); +} +#else +#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Compute Rms and store the result in the destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#else +void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + in = *pSrc++; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ( in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Rms and store result in destination */ + arm_sqrt_f32(sum / (float32_t) blockSize, pResult); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c new file mode 100644 index 0000000..1df17b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c @@ -0,0 +1,149 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q15.c + * Description: Root Mean Square of the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q63_t pow = 0.0f; + q15_t normalizedPower; + + arm_power_q15(pSrc, blockSize, &pow); + + normalizedPower=__SSAT((pow / (q63_t) blockSize) >> 15,16); + arm_sqrt_q15(normalizedPower, pResult); +} +#else +void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); + + in32 = read_q15x2_ia (&pSrc); + sum = __SMLALD(in32, in32, sum); +#else + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); + + in = *pSrc++; + sum += ((q31_t) in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q31_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Truncating and saturating the accumulator to 1.15 format */ + /* Store result in destination */ + arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c new file mode 100644 index 0000000..ba39b7b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rms_q31.c + * Description: Root Mean Square of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup RMS + @{ + */ + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult root mean square value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, and intermediate multiplication + yields a 2.62 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a single guard bit. + There is no saturation on intermediate additions. + If the accumulator overflows, it wraps around and distorts the result. + In order to avoid overflows completely, the input signal must be scaled down by + log2(blockSize) bits, as a total of blockSize additions are performed internally. + Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q63_t pow = 0.0f; + q31_t normalizedPower; + arm_power_q31(pSrc, blockSize, &pow); + + normalizedPower=clip_q63_to_q31((pow / (q63_t) blockSize) >> 17); + arm_sqrt_q31(normalizedPower, pResult); + +} + +#else +void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */ + q31_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sum. */ + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + in = *pSrc++; + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable. */ + sum += ((q63_t) in * in); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */ + /* Compute Rms and store result in destination vector */ + arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of RMS group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c new file mode 100644 index 0000000..951d165 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f16.c @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f16.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + float16_t var; + arm_var_f16(pSrc,blockSize,&var); + arm_sqrt_f16(var, pResult); +} + +/** + @} end of STD group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c new file mode 100644 index 0000000..682443d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f32.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup STD Standard deviation + + Calculates the standard deviation of the elements in the input vector. + + The float implementation is relying on arm_var_f32 which is using a two-pass algorithm + to avoid problem of numerical instabilities and cancellation errors. + + Fixed point versions are using the standard textbook algorithm since the fixed point + numerical behavior is different from the float one. + + Algorithm for fixed point versions is summarized below: + + + 
+      Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+      sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+      sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t var; + arm_var_f32(pSrc,blockSize,&var); + arm_sqrt_f32(var, pResult); +} + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c new file mode 100644 index 0000000..620ec04 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f64.c @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_f64.c + * Description: Standard deviation of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + */ +void arm_std_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + float64_t var; + arm_var_f64(pSrc,blockSize,&var); + *pResult = sqrt(var); +} + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c new file mode 100644 index 0000000..88e273a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q15.c + * Description: Standard deviation of an array of Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult standard deviation value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + q15_t var=0; + + arm_var_q15(pSrc, blockSize, &var); + arm_sqrt_q15(var,pResult); +} +#else +void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += (in * in); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + /* Compute standard deviation and store result in destination */ + arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c new file mode 100644 index 0000000..63170e7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_std_q31.c + * Description: Standard deviation of the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup STD + @{ + */ + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] pSrc points to the input vector. + @param[in] blockSize number of samples in input vector. + @param[out] pResult standard deviation value returned here. + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + but provides only a 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + q31_t var=0; + + arm_var_q31(pSrc, blockSize, &var); + arm_sqrt_q31(var, pResult); +} +#else +void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Accumulator */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute standard deviation and store result in destination */ + arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult); +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of STD group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c new file mode 100644 index 0000000..0e3ade5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f16.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f16.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions_f16.h" + + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupStats + */ + + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + int32_t blkCnt; /* loop counters */ + f16x8_t vecSrc; + f16x8_t sumVec = vdupq_n_f16(0.0f16); + float16_t fMean; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + arm_mean_f16(pSrc, blockSize, &fMean); + + blkCnt = blockSize; + do { + mve_pred16_t p = vctp16q(blkCnt); + + vecSrc = vldrhq_z_f16((float16_t const *) pSrc, p); + /* + * sum lanes + */ + vecSrc = vsubq_m(vuninitializedq_f16(), vecSrc, fMean, p); + sumVec = vfmaq_m(sumVec, vecSrc, vecSrc, p); + + blkCnt -= 8; + pSrc += 8; + } + while (blkCnt > 0); + + /* Variance */ + *pResult = (_Float16)vecAddAcrossF16Mve(sumVec) / (_Float16) (blockSize - 1.0f16); +} +#else + +void arm_var_f16( + const float16_t * pSrc, + uint32_t blockSize, + float16_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + _Float16 sum = 0.0f; /* Temporary result storage */ + _Float16 fSum = 0.0f; + _Float16 fMean, fValue; + const float16_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + sum += (_Float16)*pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += (_Float16)*pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = (_Float16)sum / (_Float16) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = (_Float16)*pInput++ - (_Float16)fMean; + fSum += (_Float16)fValue * (_Float16)fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = (_Float16)fSum / ((_Float16)blockSize - 1.0f16); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c new file mode 100644 index 0000000..7ff344c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c @@ -0,0 +1,293 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f32.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @defgroup variance Variance + + Calculates the variance of the elements in the input vector. + The underlying algorithm used is the direct method sometimes referred to as the two-pass method: + + 
+      Result = sum(element - meanOfElements)^2) / numElement - 1
+
+      meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+
+ + There are separate functions for floating point, Q31, and Q15 data types. + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + f32x4_t vecSrc; + f32x4_t sumVec = vdupq_n_f32(0.0f); + float32_t fMean; + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + arm_mean_f32(pSrc, blockSize, &fMean); + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + + vecSrc = vldrwq_f32(pSrc); + /* + * sum lanes + */ + vecSrc = vsubq(vecSrc, fMean); + sumVec = vfmaq(sumVec, vecSrc, vecSrc); + + blkCnt --; + pSrc += 4; + } + + sum = vecAddAcrossF32Mve(sumVec); + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + in = *pSrc++ - fMean; + sum += in * in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t) (blockSize - 1); +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + float32_t mean; + + float32_t sum = 0.0f; /* accumulator */ + float32_t in; /* Temporary variable to store input value */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */ + float32x2_t sumV2; + float32x4_t inV; + float32x4_t avg; + + arm_mean_f32(pSrc,blockSize,&mean); + avg = vdupq_n_f32(mean); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* Compute Power and then store the result in a temporary variable, sum. */ + inV = vld1q_f32(pSrc); + inV = vsubq_f32(inV, avg); + sumV = vmlaq_f32(sumV, inV, inV); + pSrc += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV)); + sum = vget_lane_f32(sumV2, 0) + vget_lane_f32(sumV2, 1); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */ + /* compute power and then store the result in a temporary variable, sum. */ + in = *pSrc++; + in = in - mean; + sum += in * in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = sum / (float32_t)(blockSize - 1.0f); + +} + +#else +void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float32_t sum = 0.0f; /* Temporary result storage */ + float32_t fSum = 0.0f; + float32_t fMean, fValue; + const float32_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + sum += *pInput++; + + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float32_t) blockSize; + + pInput = pSrc; + +#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float32_t)(blockSize - 1.0f); +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c new file mode 100644 index 0000000..6fd106a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f64.c @@ -0,0 +1,100 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_f64.c + * Description: Variance of the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + */ +void arm_var_f64( + const float64_t * pSrc, + uint32_t blockSize, + float64_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + float64_t sum = 0.; /* Temporary result storage */ + float64_t fSum = 0.; + float64_t fMean, fValue; + const float64_t * pInput = pSrc; + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */ + + sum += *pInput++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */ + fMean = sum / (float64_t) blockSize; + + pInput = pSrc; + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + fValue = *pInput++ - fMean; + fSum += fValue * fValue; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Variance */ + *pResult = fSum / (float64_t)(blockSize - 1.); +} + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c new file mode 100644 index 0000000..f020c88 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q15.c + * Description: Variance of an array of Q15 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + The input is represented in 1.15 format. + Intermediate multiplication yields a 2.30 format, and this + result is added without saturation to a 64-bit accumulator in 34.30 format. + With 33 guard bits in the accumulator, there is no risk of overflow, and the + full precision of the intermediate multiplication is preserved. + Finally, the 34.30 result is truncated to 34.15 format by discarding the lower + 15 bits, and then saturated to yield a result in 1.15 format. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q15x8_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q15_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vecSrc = vldrhq_s16(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + sumOfSquares = vmlaldavaq_s16(sumOfSquares, vecSrc, vecSrc); + sum = vaddvaq_s16(sum, vecSrc); + + blkCnt --; + pSrc += 8; + } + + /* Tail */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = arm_div_q63_to_q31(sumOfSquares, (blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = arm_div_q63_to_q31((q63_t)sum * sum, (q31_t)(blockSize * (blockSize - 1U))); + + /* mean of the squares minus the square of the mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15; +} +#else +void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q31_t sum = 0; /* Accumulator */ + q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q15_t in; /* Temporary variable to store input value */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in32; /* Temporary variable to store input value */ +#endif + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + /* Compute sum and store result in a temporary variable, sum. */ +#if defined (ARM_MATH_DSP) + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); + + in32 = read_q15x2_ia (&pSrc); + sumOfSquares = __SMLALD(in32, in32, sumOfSquares); + sum += ((in32 << 16U) >> 16U); + sum += (in32 >> 16U); +#else + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; + + in = *pSrc++; + sumOfSquares += (in * in); + sum += in; +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ +#if defined (ARM_MATH_DSP) + sumOfSquares = __SMLALD(in, in, sumOfSquares); +#else + sumOfSquares += (in * in); +#endif /* #if defined (ARM_MATH_DSP) */ + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* mean of squares minus the square of mean. */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c new file mode 100644 index 0000000..45b6b66 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_var_q31.c + * Description: Variance of an array of Q31 type + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/statistics_functions.h" + +/** + @ingroup groupStats + */ + +/** + @addtogroup variance + @{ + */ + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult variance value returned here + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The input is represented in 1.31 format, which is then downshifted by 8 bits + which yields 1.23, and intermediate multiplication yields a 2.46 format. + The accumulator maintains full precision of the intermediate multiplication results, + and as a consequence has only 16 guard bits. + There is no saturation on intermediate additions. + If the accumulator overflows it wraps around and distorts the result. + In order to avoid overflows completely the input signal must be scaled down by + log2(blockSize)-8 bits, as a total of blockSize additions are performed internally. + After division, internal variables should be Q18.46 + Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value. + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecSrc; + q63_t sumOfSquares = 0LL; + q63_t meanOfSquares, squareOfMean; /* square of mean and mean of square */ + q63_t sum = 0LL; + q31_t in; + + if (blockSize <= 1U) { + *pResult = 0; + return; + } + + + /* Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + while (blkCnt > 0U) + { + vecSrc = vldrwq_s32(pSrc); + /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */ + /* Compute Sum of squares of the input samples + * and then store the result in a temporary variable, sumOfSquares. */ + + /* downscale */ + vecSrc = vshrq(vecSrc, 8); + sumOfSquares = vmlaldavaq(sumOfSquares, vecSrc, vecSrc); + sum = vaddlvaq(sum, vecSrc); + + blkCnt --; + pSrc += 4; + } + + + /* + * tail + */ + blkCnt = blockSize & 0x3; + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares of the input samples + * and then store the result in a temporary variable, meanOfSquares. */ + meanOfSquares = sumOfSquares / (q63_t) (blockSize - 1U); + + /* Compute square of mean */ + squareOfMean = sum * sum / (q63_t) (blockSize * (blockSize - 1U)); + + /* Compute standard deviation and then store the result to the destination */ + *pResult = asrl(meanOfSquares - squareOfMean, 15U); +} +#else +void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult) +{ + uint32_t blkCnt; /* Loop counter */ + q63_t sum = 0; /* Temporary result storage */ + q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */ + q63_t sumOfSquares = 0; /* Sum of squares */ + q31_t in; /* Temporary variable to store input value */ + + if (blockSize <= 1U) + { + *pResult = 0; + return; + } + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + in = *pSrc++ >> 8U; + sumOfSquares += ((q63_t) (in) * (in)); + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */ + /* C = A[0] + A[1] + ... + A[blockSize-1] */ + + in = *pSrc++ >> 8U; + /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */ + sumOfSquares += ((q63_t) (in) * (in)); + /* Compute sum and store result in a temporary variable, sum. */ + sum += in; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */ + meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U)); + + /* Compute square of mean */ + squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U))); + + /* Compute variance and store result in destination */ + *pResult = (meanOfSquares - squareOfMean) >> 15U; +} +#endif +/** + @} end of variance group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt new file mode 100644 index 0000000..41b13f2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/CMakeLists.txt @@ -0,0 +1,28 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPSupport) + +include(configLib) +include(configDsp) + +file(GLOB SRC "./*_*.c") + +add_library(CMSISDSPSupport STATIC ${SRC}) + +configLib(CMSISDSPSupport ${ROOT}) +configDsp(CMSISDSPSupport ${ROOT}) + +### Includes +target_include_directories(CMSISDSPSupport PUBLIC "${DSP}/Include") + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPSupport PRIVATE arm_copy_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_fill_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_f16_to_q15.c) +target_sources(CMSISDSPSupport PRIVATE arm_q15_to_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_float_to_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_f16_to_float.c) +target_sources(CMSISDSPSupport PRIVATE arm_weighted_sum_f16.c) +target_sources(CMSISDSPSupport PRIVATE arm_barycenter_f16.c) +endif() + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c new file mode 100644 index 0000000..ca8b1b6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_barycenter_f32.c" +#include "arm_bitonic_sort_f32.c" +#include "arm_bubble_sort_f32.c" +#include "arm_copy_f32.c" +#include "arm_copy_f64.c" +#include "arm_copy_q15.c" +#include "arm_copy_q31.c" +#include "arm_copy_q7.c" +#include "arm_fill_f32.c" +#include "arm_fill_f64.c" +#include "arm_fill_q15.c" +#include "arm_fill_q31.c" +#include "arm_fill_q7.c" +#include "arm_heap_sort_f32.c" +#include "arm_insertion_sort_f32.c" +#include "arm_merge_sort_f32.c" +#include "arm_merge_sort_init_f32.c" +#include "arm_quick_sort_f32.c" +#include "arm_selection_sort_f32.c" +#include "arm_sort_f32.c" +#include "arm_sort_init_f32.c" +#include "arm_weighted_sum_f32.c" + +#include "arm_float_to_q15.c" +#include "arm_float_to_q31.c" +#include "arm_float_to_q7.c" +#include "arm_q15_to_float.c" +#include "arm_q15_to_q31.c" +#include "arm_q15_to_q7.c" +#include "arm_q31_to_float.c" +#include "arm_q31_to_q15.c" +#include "arm_q31_to_q7.c" +#include "arm_q7_to_float.c" +#include "arm_q7_to_q15.c" +#include "arm_q7_to_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c new file mode 100644 index 0000000..0e39d8d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctionsF16.c @@ -0,0 +1,36 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: SupportFunctions.c + * Description: Combination of all support function source files. + * + * $Date: 16. March 2020 + * $Revision: V1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_copy_f16.c" +#include "arm_fill_f16.c" +#include "arm_f16_to_q15.c" +#include "arm_f16_to_float.c" +#include "arm_q15_to_f16.c" +#include "arm_float_to_f16.c" +#include "arm_weighted_sum_f16.c" +#include "arm_barycenter_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c new file mode 100644 index 0000000..6dfe55c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f16.c @@ -0,0 +1,274 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f16.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +#include +#include + +/** + @ingroup groupSupport + */ + +/** + @defgroup barycenter Barycenter + + Barycenter of weighted vectors + */ + +/** + @addtogroup barycenter + @{ + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_barycenter_f16(const float16_t *in, + const float16_t *weights, + float16_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float16_t *pIn, *pW; + const float16_t *pIn1, *pIn2, *pIn3, *pIn4; + float16_t *pOut; + uint32_t blkCntVector, blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f16(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f16x8_t outV, inV1, inV2, inV3, inV4; + float16_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += (_Float16)w1 + (_Float16)w2 + (_Float16)w3 + (_Float16)w4; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) { + outV = vld1q((const float16_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 8; + pIn1 += 8; + pIn2 += 8; + pIn3 += 8; + pIn4 += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) { + *pOut = (_Float16)*pOut + (_Float16)*pIn1++ * (_Float16)w1; + *pOut = (_Float16)*pOut + (_Float16)*pIn2++ * (_Float16)w2; + *pOut = (_Float16)*pOut + (_Float16)*pIn3++ * (_Float16)w3; + *pOut = (_Float16)*pOut + (_Float16)*pIn4++ * (_Float16)w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f16x8_t inV, outV; + + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + outV = vld1q_f16(pOut); + inV = vld1q_f16(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f16(pOut, outV); + pOut += 8; + pIn += 8; + + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f16 / (_Float16)accum; + + blkCntSample = vecDim >> 3; + while (blkCntSample > 0) + { + f16x8_t tmp; + + tmp = vld1q((const float16_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 8; + blkCntSample--; + } + + blkCntSample = vecDim & 7; + while (blkCntSample > 0) + { + *pOut = (_Float16)*pOut * (_Float16)accum; + pOut++; + blkCntSample--; + } +} +#else +void arm_barycenter_f16(const float16_t *in, const float16_t *weights, float16_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float16_t *pIn,*pW; + float16_t *pOut; + uint32_t blkCntVector,blkCntSample; + float16_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f16; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f16; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += (_Float16)w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut + (_Float16)*pIn++ * (_Float16)w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = (_Float16)*pOut / (_Float16)accum; + pOut++; + blkCntSample--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c new file mode 100644 index 0000000..817bb58 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c @@ -0,0 +1,414 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_barycenter_f32.c + * Description: Barycenter + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include +#include + + +/** + @ingroup barycenter + */ + + +/** + * @brief Barycenter + * + * + * @param[in] *in List of vectors + * @param[in] *weights Weights of the vectors + * @param[out] *out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_barycenter_f32(const float32_t *in, + const float32_t *weights, + float32_t *out, + uint32_t nbVectors, + uint32_t vecDim) +{ + const float32_t *pIn, *pW; + const float32_t *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector, blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + + arm_fill_f32(0.0f, out, vecDim); + + + /* Sum */ + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while (blkCntVector > 0) + { + f32x4_t outV, inV1, inV2, inV3, inV4; + float32_t w1, w2, w3, w4; + + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) { + outV = vld1q((const float32_t *) pOut); + inV1 = vld1q(pIn1); + inV2 = vld1q(pIn2); + inV3 = vld1q(pIn3); + inV4 = vld1q(pIn4); + outV = vfmaq(outV, inV1, w1); + outV = vfmaq(outV, inV2, w2); + outV = vfmaq(outV, inV3, w3); + outV = vfmaq(outV, inV4, w4); + vst1q(pOut, outV); + + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3 * vecDim; + pIn2 += 3 * vecDim; + pIn3 += 3 * vecDim; + pIn4 += 3 * vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while (blkCntVector > 0) + { + f32x4_t inV, outV; + + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vfmaq(outV, inV, w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while (blkCntSample > 0) + { + f32x4_t tmp; + + tmp = vld1q((const float32_t *) pOut); + tmp = vmulq(tmp, accum); + vst1q(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while (blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } +} +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW, *pIn1, *pIn2, *pIn3, *pIn4; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w,w1,w2,w3,w4; + + float32x4_t tmp, inV,outV, inV1, inV2, inV3, inV4; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + tmp = vdupq_n_f32(0.0f); + pOut = out; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + + pIn1 = pIn; + pIn2 = pIn1 + vecDim; + pIn3 = pIn2 + vecDim; + pIn4 = pIn3 + vecDim; + + blkCntVector = nbVectors >> 2; + while(blkCntVector > 0) + { + pOut = out; + w1 = *pW++; + w2 = *pW++; + w3 = *pW++; + w4 = *pW++; + accum += w1 + w2 + w3 + w4; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV1 = vld1q_f32(pIn1); + inV2 = vld1q_f32(pIn2); + inV3 = vld1q_f32(pIn3); + inV4 = vld1q_f32(pIn4); + outV = vmlaq_n_f32(outV,inV1,w1); + outV = vmlaq_n_f32(outV,inV2,w2); + outV = vmlaq_n_f32(outV,inV3,w3); + outV = vmlaq_n_f32(outV,inV4,w4); + vst1q_f32(pOut, outV); + pOut += 4; + pIn1 += 4; + pIn2 += 4; + pIn3 += 4; + pIn4 += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn1++ * w1; + *pOut = *pOut + *pIn2++ * w2; + *pOut = *pOut + *pIn3++ * w3; + *pOut = *pOut + *pIn4++ * w4; + pOut++; + blkCntSample--; + } + + pIn1 += 3*vecDim; + pIn2 += 3*vecDim; + pIn3 += 3*vecDim; + pIn4 += 3*vecDim; + + blkCntVector--; + } + + pIn = pIn1; + + blkCntVector = nbVectors & 3; + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + outV = vld1q_f32(pOut); + inV = vld1q_f32(pIn); + outV = vmlaq_n_f32(outV,inV,w); + vst1q_f32(pOut, outV); + pOut += 4; + pIn += 4; + + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + pOut = out; + accum = 1.0f / accum; + + blkCntSample = vecDim >> 2; + while(blkCntSample > 0) + { + tmp = vld1q_f32(pOut); + tmp = vmulq_n_f32(tmp,accum); + vst1q_f32(pOut, tmp); + pOut += 4; + blkCntSample--; + } + + blkCntSample = vecDim & 3; + while(blkCntSample > 0) + { + *pOut = *pOut * accum; + pOut++; + blkCntSample--; + } + +} +#else +void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbVectors,uint32_t vecDim) +{ + + const float32_t *pIn,*pW; + float32_t *pOut; + uint32_t blkCntVector,blkCntSample; + float32_t accum, w; + + blkCntVector = nbVectors; + blkCntSample = vecDim; + + accum = 0.0f; + + pW = weights; + pIn = in; + + /* Set counters to 0 */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = 0.0f; + pOut++; + blkCntSample--; + } + + /* Sum */ + while(blkCntVector > 0) + { + pOut = out; + w = *pW++; + accum += w; + + blkCntSample = vecDim; + while(blkCntSample > 0) + { + *pOut = *pOut + *pIn++ * w; + pOut++; + blkCntSample--; + } + + blkCntVector--; + } + + /* Normalize */ + blkCntSample = vecDim; + pOut = out; + + while(blkCntSample > 0) + { + *pOut = *pOut / accum; + pOut++; + blkCntSample--; + } + +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of barycenter group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c new file mode 100644 index 0000000..e9612b1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c @@ -0,0 +1,1039 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitonic_sort_f32.c + * Description: Floating point bitonic sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + + +#if !defined(ARM_MATH_NEON) + +static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir) +{ + uint32_t step; + uint32_t k, j; + float32_t *leftPtr, *rightPtr; + float32_t temp; + + step = n>>1; + leftPtr = pSrc; + rightPtr = pSrc+n-1; + + for(k=0; k *rightPtr)) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; // Move right + rightPtr--; // Move left + } + + // Merge + for(step=(n>>2); step>0; step/=2) + { + for(j=0; j *rightPtr) + { + // Swap + temp=*leftPtr; + *leftPtr=*rightPtr; + *rightPtr=temp; + } + + leftPtr++; + rightPtr++; + } + } + } +} +#endif + +#if defined(ARM_MATH_NEON) + + +static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+ + * | a | b | c | d | + * +---+---+---+---+ + * +---+---+---+---+ + * | e | f | g | h | + * +---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) + * vminmax([acbd],[egfh]) + */ + vtrn128_64q(a, b); + /* +---+---+---+---+ + * | a | b | e | f | + * +---+---+---+---+ + * +---+---+---+---+ + * | c | d | g | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + vtrn128_32q(a, b); + /* +---+---+---+---+ + * | a | c | e | g | + * +---+---+---+---+ + * +---+---+---+---+ + * | b | d | f | h | + * +---+---+---+---+ + */ + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + return vzipq_f32(a, b); +} + + +static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + /* a and b are guaranteed to be bitonic */ + // Reverse the element of the second vector + b = vrev128q_f32(b); + + // Compare the two vectors + if(dir) + vminmaxq(a, b); + else + vminmaxq(b, a); + + // Merge the two vectors + float32x4x2_t ab = arm_bitonic_resort_8_f32(a, b, dir); + + return ab; +} + +static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + /* Start with two vectors: + * +---+---+---+---+---+---+---+---+ + * | a | b | c | d | e | f | g | h | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | i | j | k | l | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + * All the elements of the first are guaranteed to be less than or equal to + * all of the elements in the second, and both vectors are bitonic. + * We need to perform these operations to completely sort both lists: + * vminmax([abcd],[efgh]) vminmax([ijkl],[mnop]) + * vminmax([abef],[cdgh]) vminmax([ijmn],[klop]) + * vminmax([acef],[bdfh]) vminmax([ikmo],[jlmp]) + */ + + vtrn256_128q(a, b); + /* +---+---+---+---+---+---+---+---+ + * | a | b | c | d | i | j | k | l | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | e | f | g | h | m | n | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_64q(a, b); + + /* +---+---+---+---+---+---+---+---+ + * | a | b | e | f | i | j | m | n | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | c | d | g | h | k | l | o | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + vtrn256_32q(a, b); + /* We now have: + * +---+---+---+---+---+---+---+---+ + * | a | c | e | g | i | k | m | o | + * +---+---+---+---+---+---+---+---+ + * +---+---+---+---+---+---+---+---+ + * | b | d | f | h | j | l | n | p | + * +---+---+---+---+---+---+---+---+ + */ + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]); + float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]); + + vst1q_f32(pOut, out1.val[0]); + vst1q_f32(pOut+4, out1.val[1]); + vst1q_f32(pOut+8, out2.val[0]); + vst1q_f32(pOut+12, out2.val[1]); +} + +static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t dir) +{ + // Merge two preordered float32x4x2_t + vrev256q_f32(b); + + if(dir) + vminmax256q(a, b); + else + vminmax256q(b, a); + + arm_bitonic_resort_16_f32(pOut, a, b, dir); +} + +static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir) +{ + float32x4_t a; + float32x4_t b; + float32x4_t c; + float32x4_t d; + + // Load 16 samples + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + c = vld1q_f32(pSrc+8); + d = vld1q_f32(pSrc+12); + + // Bitonic sorting network for 4 samples x 4 times + if(dir) + { + vminmaxq(a, b); + vminmaxq(c, d); + + vminmaxq(a, d); + vminmaxq(b, c); + + vminmaxq(a, b); + vminmaxq(c, d); + } + else + { + vminmaxq(b, a); + vminmaxq(d, c); + + vminmaxq(d, a); + vminmaxq(c, b); + + vminmaxq(b, a); + vminmaxq(d, c); + } + + float32x4x2_t ab = vtrnq_f32 (a, b); + float32x4x2_t cd = vtrnq_f32 (c, d); + + // Transpose 4 ordered arrays of 4 samples + a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0])); + b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1])); + c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0])); + d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1])); + + // Merge pairs of arrays of 4 samples + ab = arm_bitonic_merge_8_f32(a, b, dir); + cd = arm_bitonic_merge_8_f32(c, d, dir); + + // Merge arrays of 8 samples + arm_bitonic_merge_16_f32(pDst, ab, cd, dir); +} + + + + + +static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2, float32x4x2_t cd1, float32x4x2_t cd2, uint8_t dir) +{ + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + //Transpose 256 + float32x4_t temp; + + temp = ab2.val[0]; + ab2.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab2.val[1]; + ab2.val[1] = cd1.val[1]; + cd1.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + } + + //Transpose 128 + arm_bitonic_merge_16_f32(pSrc+0, ab1, cd1, dir); + arm_bitonic_merge_16_f32(pSrc+16, ab2, cd2, dir); +} + +static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4; + float32x4x2_t cd1, cd2, cd3, cd4; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + + vldrev128q_f32(cd4.val[1], pSrc+32); + vldrev128q_f32(cd4.val[0], pSrc+36); + vldrev128q_f32(cd3.val[1], pSrc+40); + vldrev128q_f32(cd3.val[0], pSrc+44); + vldrev128q_f32(cd2.val[1], pSrc+48); + vldrev128q_f32(cd2.val[0], pSrc+52); + vldrev128q_f32(cd1.val[1], pSrc+56); + vldrev128q_f32(cd1.val[0], pSrc+60); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 512 + float32x4_t temp; + + temp = ab3.val[0]; + ab3.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab3.val[1]; + ab3.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab4.val[0]; + ab4.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab4.val[1]; + ab4.val[1] = cd2.val[1]; + cd2.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + } + + //Transpose 256 + arm_bitonic_merge_32_f32(pSrc+0, ab1, ab2, cd1, cd2, dir); + arm_bitonic_merge_32_f32(pSrc+32, ab3, ab4, cd3, cd4, dir); +} + +static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12); + ab3.val[0] = vld1q_f32(pSrc+16); + ab3.val[1] = vld1q_f32(pSrc+20); + ab4.val[0] = vld1q_f32(pSrc+24); + ab4.val[1] = vld1q_f32(pSrc+28); + ab5.val[0] = vld1q_f32(pSrc+32); + ab5.val[1] = vld1q_f32(pSrc+36); + ab6.val[0] = vld1q_f32(pSrc+40); + ab6.val[1] = vld1q_f32(pSrc+44); + ab7.val[0] = vld1q_f32(pSrc+48); + ab7.val[1] = vld1q_f32(pSrc+52); + ab8.val[0] = vld1q_f32(pSrc+56); + ab8.val[1] = vld1q_f32(pSrc+60); + + vldrev128q_f32(cd8.val[1], pSrc+64); + vldrev128q_f32(cd8.val[0], pSrc+68); + vldrev128q_f32(cd7.val[1], pSrc+72); + vldrev128q_f32(cd7.val[0], pSrc+76); + vldrev128q_f32(cd6.val[1], pSrc+80); + vldrev128q_f32(cd6.val[0], pSrc+84); + vldrev128q_f32(cd5.val[1], pSrc+88); + vldrev128q_f32(cd5.val[0], pSrc+92); + vldrev128q_f32(cd4.val[1], pSrc+96); + vldrev128q_f32(cd4.val[0], pSrc+100); + vldrev128q_f32(cd3.val[1], pSrc+104); + vldrev128q_f32(cd3.val[0], pSrc+108); + vldrev128q_f32(cd2.val[1], pSrc+112); + vldrev128q_f32(cd2.val[0], pSrc+116); + vldrev128q_f32(cd1.val[1], pSrc+120); + vldrev128q_f32(cd1.val[0], pSrc+124); + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + //Transpose + float32x4_t temp; + + temp = ab5.val[0]; + ab5.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab5.val[1]; + ab5.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab6.val[0]; + ab6.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab6.val[1]; + ab6.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab7.val[0]; + ab7.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab7.val[1]; + ab7.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab8.val[0]; + ab8.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab8.val[1]; + ab8.val[1] = cd4.val[1]; + cd4.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1, cd1); + vminmax256q(ab2, cd2); + vminmax256q(ab3, cd3); + vminmax256q(ab4, cd4); + vminmax256q(ab5, cd5); + vminmax256q(ab6, cd6); + vminmax256q(ab7, cd7); + vminmax256q(ab8, cd8); + } + else + { + vminmax256q(cd1, ab1); + vminmax256q(cd2, ab2); + vminmax256q(cd3, ab3); + vminmax256q(cd4, ab4); + vminmax256q(cd5, ab5); + vminmax256q(cd6, ab6); + vminmax256q(cd7, ab7); + vminmax256q(cd8, ab8); + } + + vst1q_f32(pSrc, ab1.val[0]); + vst1q_f32(pSrc+4, ab1.val[1]); + vst1q_f32(pSrc+8, ab2.val[0]); + vst1q_f32(pSrc+12, ab2.val[1]); + vst1q_f32(pSrc+16, ab3.val[0]); + vst1q_f32(pSrc+20, ab3.val[1]); + vst1q_f32(pSrc+24, ab4.val[0]); + vst1q_f32(pSrc+28, ab4.val[1]); + vst1q_f32(pSrc+32, cd1.val[0]); + vst1q_f32(pSrc+36, cd1.val[1]); + vst1q_f32(pSrc+40, cd2.val[0]); + vst1q_f32(pSrc+44, cd2.val[1]); + vst1q_f32(pSrc+48, cd3.val[0]); + vst1q_f32(pSrc+52, cd3.val[1]); + vst1q_f32(pSrc+56, cd4.val[0]); + vst1q_f32(pSrc+60, cd4.val[1]); + vst1q_f32(pSrc+64, ab5.val[0]); + vst1q_f32(pSrc+68, ab5.val[1]); + vst1q_f32(pSrc+72, ab6.val[0]); + vst1q_f32(pSrc+76, ab6.val[1]); + vst1q_f32(pSrc+80, ab7.val[0]); + vst1q_f32(pSrc+84, ab7.val[1]); + vst1q_f32(pSrc+88, ab8.val[0]); + vst1q_f32(pSrc+92, ab8.val[1]); + vst1q_f32(pSrc+96, cd5.val[0]); + vst1q_f32(pSrc+100, cd5.val[1]); + vst1q_f32(pSrc+104, cd6.val[0]); + vst1q_f32(pSrc+108, cd6.val[1]); + vst1q_f32(pSrc+112, cd7.val[0]); + vst1q_f32(pSrc+116, cd7.val[1]); + vst1q_f32(pSrc+120, cd8.val[0]); + vst1q_f32(pSrc+124, cd8.val[1]); + + //Transpose + arm_bitonic_merge_64_f32(pSrc+0 , dir); + arm_bitonic_merge_64_f32(pSrc+64, dir); +} + +static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir) +{ + float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8; + float32x4x2_t ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16; + float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8; + float32x4x2_t cd9, cd10, cd11, cd12, cd13, cd14, cd15, cd16; + + //Load and reverse second array + ab1.val[0] = vld1q_f32(pSrc+0 ); + ab1.val[1] = vld1q_f32(pSrc+4 ); + ab2.val[0] = vld1q_f32(pSrc+8 ); + ab2.val[1] = vld1q_f32(pSrc+12 ); + ab3.val[0] = vld1q_f32(pSrc+16 ); + ab3.val[1] = vld1q_f32(pSrc+20 ); + ab4.val[0] = vld1q_f32(pSrc+24 ); + ab4.val[1] = vld1q_f32(pSrc+28 ); + ab5.val[0] = vld1q_f32(pSrc+32 ); + ab5.val[1] = vld1q_f32(pSrc+36 ); + ab6.val[0] = vld1q_f32(pSrc+40 ); + ab6.val[1] = vld1q_f32(pSrc+44 ); + ab7.val[0] = vld1q_f32(pSrc+48 ); + ab7.val[1] = vld1q_f32(pSrc+52 ); + ab8.val[0] = vld1q_f32(pSrc+56 ); + ab8.val[1] = vld1q_f32(pSrc+60 ); + ab9.val[0] = vld1q_f32(pSrc+64 ); + ab9.val[1] = vld1q_f32(pSrc+68 ); + ab10.val[0] = vld1q_f32(pSrc+72 ); + ab10.val[1] = vld1q_f32(pSrc+76 ); + ab11.val[0] = vld1q_f32(pSrc+80 ); + ab11.val[1] = vld1q_f32(pSrc+84 ); + ab12.val[0] = vld1q_f32(pSrc+88 ); + ab12.val[1] = vld1q_f32(pSrc+92 ); + ab13.val[0] = vld1q_f32(pSrc+96 ); + ab13.val[1] = vld1q_f32(pSrc+100); + ab14.val[0] = vld1q_f32(pSrc+104); + ab14.val[1] = vld1q_f32(pSrc+108); + ab15.val[0] = vld1q_f32(pSrc+112); + ab15.val[1] = vld1q_f32(pSrc+116); + ab16.val[0] = vld1q_f32(pSrc+120); + ab16.val[1] = vld1q_f32(pSrc+124); + + vldrev128q_f32(cd16.val[1], pSrc+128); + vldrev128q_f32(cd16.val[0], pSrc+132); + vldrev128q_f32(cd15.val[1], pSrc+136); + vldrev128q_f32(cd15.val[0], pSrc+140); + vldrev128q_f32(cd14.val[1], pSrc+144); + vldrev128q_f32(cd14.val[0], pSrc+148); + vldrev128q_f32(cd13.val[1], pSrc+152); + vldrev128q_f32(cd13.val[0], pSrc+156); + vldrev128q_f32(cd12.val[1], pSrc+160); + vldrev128q_f32(cd12.val[0], pSrc+164); + vldrev128q_f32(cd11.val[1], pSrc+168); + vldrev128q_f32(cd11.val[0], pSrc+172); + vldrev128q_f32(cd10.val[1], pSrc+176); + vldrev128q_f32(cd10.val[0], pSrc+180); + vldrev128q_f32(cd9.val[1] , pSrc+184); + vldrev128q_f32(cd9.val[0] , pSrc+188); + vldrev128q_f32(cd8.val[1] , pSrc+192); + vldrev128q_f32(cd8.val[0] , pSrc+196); + vldrev128q_f32(cd7.val[1] , pSrc+200); + vldrev128q_f32(cd7.val[0] , pSrc+204); + vldrev128q_f32(cd6.val[1] , pSrc+208); + vldrev128q_f32(cd6.val[0] , pSrc+212); + vldrev128q_f32(cd5.val[1] , pSrc+216); + vldrev128q_f32(cd5.val[0] , pSrc+220); + vldrev128q_f32(cd4.val[1] , pSrc+224); + vldrev128q_f32(cd4.val[0] , pSrc+228); + vldrev128q_f32(cd3.val[1] , pSrc+232); + vldrev128q_f32(cd3.val[0] , pSrc+236); + vldrev128q_f32(cd2.val[1] , pSrc+240); + vldrev128q_f32(cd2.val[0] , pSrc+244); + vldrev128q_f32(cd1.val[1] , pSrc+248); + vldrev128q_f32(cd1.val[0] , pSrc+252); + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + //Transpose + float32x4_t temp; + + temp = ab9.val[0]; + ab9.val[0] = cd1.val[0]; + cd1.val[0] = temp; + temp = ab9.val[1]; + ab9.val[1] = cd1.val[1]; + cd1.val[1] = temp; + temp = ab10.val[0]; + ab10.val[0] = cd2.val[0]; + cd2.val[0] = temp; + temp = ab10.val[1]; + ab10.val[1] = cd2.val[1]; + cd2.val[1] = temp; + temp = ab11.val[0]; + ab11.val[0] = cd3.val[0]; + cd3.val[0] = temp; + temp = ab11.val[1]; + ab11.val[1] = cd3.val[1]; + cd3.val[1] = temp; + temp = ab12.val[0]; + ab12.val[0] = cd4.val[0]; + cd4.val[0] = temp; + temp = ab12.val[1]; + ab12.val[1] = cd4.val[1]; + cd4.val[1] = temp; + temp = ab13.val[0]; + ab13.val[0] = cd5.val[0]; + cd5.val[0] = temp; + temp = ab13.val[1]; + ab13.val[1] = cd5.val[1]; + cd5.val[1] = temp; + temp = ab14.val[0]; + ab14.val[0] = cd6.val[0]; + cd6.val[0] = temp; + temp = ab14.val[1]; + ab14.val[1] = cd6.val[1]; + cd6.val[1] = temp; + temp = ab15.val[0]; + ab15.val[0] = cd7.val[0]; + cd7.val[0] = temp; + temp = ab15.val[1]; + ab15.val[1] = cd7.val[1]; + cd7.val[1] = temp; + temp = ab16.val[0]; + ab16.val[0] = cd8.val[0]; + cd8.val[0] = temp; + temp = ab16.val[1]; + ab16.val[1] = cd8.val[1]; + cd8.val[1] = temp; + + //Compare + if(dir) + { + vminmax256q(ab1 , cd1 ); + vminmax256q(ab2 , cd2 ); + vminmax256q(ab3 , cd3 ); + vminmax256q(ab4 , cd4 ); + vminmax256q(ab5 , cd5 ); + vminmax256q(ab6 , cd6 ); + vminmax256q(ab7 , cd7 ); + vminmax256q(ab8 , cd8 ); + vminmax256q(ab9 , cd9 ); + vminmax256q(ab10, cd10); + vminmax256q(ab11, cd11); + vminmax256q(ab12, cd12); + vminmax256q(ab13, cd13); + vminmax256q(ab14, cd14); + vminmax256q(ab15, cd15); + vminmax256q(ab16, cd16); + } + else + { + vminmax256q(cd1 , ab1 ); + vminmax256q(cd2 , ab2 ); + vminmax256q(cd3 , ab3 ); + vminmax256q(cd4 , ab4 ); + vminmax256q(cd5 , ab5 ); + vminmax256q(cd6 , ab6 ); + vminmax256q(cd7 , ab7 ); + vminmax256q(cd8 , ab8 ); + vminmax256q(cd9 , ab9 ); + vminmax256q(cd10, ab10); + vminmax256q(cd11, ab11); + vminmax256q(cd12, ab12); + vminmax256q(cd13, ab13); + vminmax256q(cd14, ab14); + vminmax256q(cd15, ab15); + vminmax256q(cd16, ab16); + } + + vst1q_f32(pSrc, ab1.val[0] ); + vst1q_f32(pSrc+4, ab1.val[1] ); + vst1q_f32(pSrc+8, ab2.val[0] ); + vst1q_f32(pSrc+12, ab2.val[1] ); + vst1q_f32(pSrc+16, ab3.val[0] ); + vst1q_f32(pSrc+20, ab3.val[1] ); + vst1q_f32(pSrc+24, ab4.val[0] ); + vst1q_f32(pSrc+28, ab4.val[1] ); + vst1q_f32(pSrc+32, ab5.val[0] ); + vst1q_f32(pSrc+36, ab5.val[1] ); + vst1q_f32(pSrc+40, ab6.val[0] ); + vst1q_f32(pSrc+44, ab6.val[1] ); + vst1q_f32(pSrc+48, ab7.val[0] ); + vst1q_f32(pSrc+52, ab7.val[1] ); + vst1q_f32(pSrc+56, ab8.val[0] ); + vst1q_f32(pSrc+60, ab8.val[1] ); + vst1q_f32(pSrc+64, cd1.val[0] ); + vst1q_f32(pSrc+68, cd1.val[1] ); + vst1q_f32(pSrc+72, cd2.val[0] ); + vst1q_f32(pSrc+76, cd2.val[1] ); + vst1q_f32(pSrc+80, cd3.val[0] ); + vst1q_f32(pSrc+84, cd3.val[1] ); + vst1q_f32(pSrc+88, cd4.val[0] ); + vst1q_f32(pSrc+92, cd4.val[1] ); + vst1q_f32(pSrc+96, cd5.val[0] ); + vst1q_f32(pSrc+100, cd5.val[1] ); + vst1q_f32(pSrc+104, cd6.val[0] ); + vst1q_f32(pSrc+108, cd6.val[1] ); + vst1q_f32(pSrc+112, cd7.val[0] ); + vst1q_f32(pSrc+116, cd7.val[1] ); + vst1q_f32(pSrc+120, cd8.val[0] ); + vst1q_f32(pSrc+124, cd8.val[1] ); + vst1q_f32(pSrc+128, ab9.val[0] ); + vst1q_f32(pSrc+132, ab9.val[1] ); + vst1q_f32(pSrc+136, ab10.val[0]); + vst1q_f32(pSrc+140, ab10.val[1]); + vst1q_f32(pSrc+144, ab11.val[0]); + vst1q_f32(pSrc+148, ab11.val[1]); + vst1q_f32(pSrc+152, ab12.val[0]); + vst1q_f32(pSrc+156, ab12.val[1]); + vst1q_f32(pSrc+160, ab13.val[0]); + vst1q_f32(pSrc+164, ab13.val[1]); + vst1q_f32(pSrc+168, ab14.val[0]); + vst1q_f32(pSrc+172, ab14.val[1]); + vst1q_f32(pSrc+176, ab15.val[0]); + vst1q_f32(pSrc+180, ab15.val[1]); + vst1q_f32(pSrc+184, ab16.val[0]); + vst1q_f32(pSrc+188, ab16.val[1]); + vst1q_f32(pSrc+192, cd9.val[0] ); + vst1q_f32(pSrc+196, cd9.val[1] ); + vst1q_f32(pSrc+200, cd10.val[0]); + vst1q_f32(pSrc+204, cd10.val[1]); + vst1q_f32(pSrc+208, cd11.val[0]); + vst1q_f32(pSrc+212, cd11.val[1]); + vst1q_f32(pSrc+216, cd12.val[0]); + vst1q_f32(pSrc+220, cd12.val[1]); + vst1q_f32(pSrc+224, cd13.val[0]); + vst1q_f32(pSrc+228, cd13.val[1]); + vst1q_f32(pSrc+232, cd14.val[0]); + vst1q_f32(pSrc+236, cd14.val[1]); + vst1q_f32(pSrc+240, cd15.val[0]); + vst1q_f32(pSrc+244, cd15.val[1]); + vst1q_f32(pSrc+248, cd16.val[0]); + vst1q_f32(pSrc+252, cd16.val[1]); + + //Transpose + arm_bitonic_merge_128_f32(pSrc+0 , dir); + arm_bitonic_merge_128_f32(pSrc+128, dir); +} + +#define SWAP(a,i,j) \ + temp = vgetq_lane_f32(a, j); \ + a = vsetq_lane_f32(vgetq_lane_f32(a, i), a, j);\ + a = vsetq_lane_f32(temp, a, i); + +static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir) +{ + float32_t temp; + + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 3)) ) + { + SWAP(a,0,3); + } + if( dir==(vgetq_lane_f32(a, 1) > vgetq_lane_f32(a, 2)) ) + { + SWAP(a,1,2); + } + + if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) ) + { + SWAP(a,0,1); + } + if( dir==(vgetq_lane_f32(a, 2)>vgetq_lane_f32(a, 3)) ) + { + SWAP(a,2,3); + } + + return a; +} + +static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir) +{ + a = arm_bitonic_sort_4_f32(a, dir); + b = arm_bitonic_sort_4_f32(b, dir); + return arm_bitonic_merge_8_f32(a, b, dir); +} + + + +#endif + +/** + @ingroup groupSupport + */ + +/** + @defgroup Sorting Vector sorting algorithms + + Sort the elements of a vector + + There are separate functions for floating-point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ +void arm_bitonic_sort_f32( +const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint16_t s, i; + uint8_t dir = S->dir; + +#ifdef ARM_MATH_NEON + (void)s; + + float32_t * pOut; + uint16_t counter = blockSize>>5; + + if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only + { + if(pSrc == pDst) // in-place + pOut = pSrc; + else + pOut = pDst; + + float32x4x2_t ab1, ab2; + float32x4x2_t cd1, cd2; + + if(blockSize == 1) + pOut = pSrc; + else if(blockSize == 2) + { + float32_t temp; + + if( dir==(pSrc[0]>pSrc[1]) ) + { + temp = pSrc[1]; + pOut[1] = pSrc[0]; + pOut[0] = temp; + } + else + pOut = pSrc; + } + else if(blockSize == 4) + { + float32x4_t a = vld1q_f32(pSrc); + + a = arm_bitonic_sort_4_f32(a, dir); + + vst1q_f32(pOut, a); + } + else if(blockSize == 8) + { + float32x4_t a; + float32x4_t b; + float32x4x2_t ab; + + a = vld1q_f32(pSrc); + b = vld1q_f32(pSrc+4); + + ab = arm_bitonic_sort_8_f32(a, b, dir); + + vst1q_f32(pOut, ab.val[0]); + vst1q_f32(pOut+4, ab.val[1]); + } + else if(blockSize >=16) + { + // Order 16 bits long vectors + for(i=0; i>1; + for(i=0; i>1; + for(i=0; i>1; + for(i=0; idir; + uint32_t i; + uint8_t swapped =1; + float32_t * pA; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + while(swapped==1) // If nothing has been swapped after one loop stop + { + swapped=0; + + for(i=0; ipA[i+1])) + { + // Swap + temp = pA[i]; + pA[i] = pA[i+1]; + pA[i+1] = temp; + + // Update flag + swapped = 1; + } + } + + blockSize--; + } +} + +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c new file mode 100644 index 0000000..d441332 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f16.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f16.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a f16 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vldrhq_z_f16((float16_t const *) pSrc, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_copy_f16( + const float16_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c new file mode 100644 index 0000000..d739f7c --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f32.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup copy Vector Copy + + Copies sample by sample from source vector to destination vector. + + 
+      pDst[n] = pSrc[n];   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_f32(pDst, vldrwq_f32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + inV = vld1q_f32(pSrc); + vst1q_f32(pDst, inV); + pSrc += 4; + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A */ + /* Copy and then store the results in the destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c new file mode 100644 index 0000000..ec1df54 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f64.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_f64.c + * Description: Copies the elements of a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a floating-point vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_copy_f64( + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c new file mode 100644 index 0000000..18f3387 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q15.c + * Description: Copies the elements of a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q15 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + vstrhq_s16(pDst,vldrhq_s16(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + write_q15x2_ia (&pDst, read_q15x2_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c new file mode 100644 index 0000000..8e06bda --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q31.c + * Description: Copies the elements of a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q31 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + vstrwq_s32(pDst,vldrwq_s32(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c new file mode 100644 index 0000000..1918d3e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_copy_q7.c + * Description: Copies the elements of a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup copy + @{ + */ + +/** + @brief Copies the elements of a Q7 vector. + @param[in] pSrc points to input vector + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vldrbq_s8(pSrc)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 16; + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A */ + + /* read 4 samples at a time */ + write_q7x4_ia (&pDst, read_q7x4_ia (&pSrc)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A */ + + /* Copy and store result in destination buffer */ + *pDst++ = *pSrc++; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of BasicCopy group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c new file mode 100644 index 0000000..a004353 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_float.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup f16_to_x Convert 16-bit floating point value + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to f32 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the f32 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_f16_to_float built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float16x8_t vecDst; + float32x4x2_t tmp; + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + vecDst = vldrhq_f16(pSrc); + pSrc += 8; + + tmp.val[0] = vcvtbq_f32_f16(vecDst); + tmp.val[1] = vcvttq_f32_f16(vecDst); + vst2q(pDst,tmp); + + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + while (blkCnt > 0) + { + + *pDst++ = (float32_t) *pSrc++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} + +#else +void arm_f16_to_float( + const float16_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float32_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c new file mode 100644 index 0000000..bb425d1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_f16_to_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup f16_to_x + @{ + */ + +/** + @brief Converts the elements of the f16 vector to Q15 vector. + @param[in] pSrc points to the f16 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding in scalar version, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + float16_t maxQ = (float16_t) Q15_MAX; + float16x8_t vecDst; + + + do { + mve_pred16_t p = vctp16q(blockSize); + + vecDst = vldrhq_z_f16((float16_t const *) pSrc, p); + /* C = A * 32767 */ + /* convert from float to Q15 and then store the results in the destination buffer */ + vecDst = vmulq_m(vuninitializedq_f16(), vecDst, maxQ, p); + + vstrhq_p_s16(pDst, + vcvtaq_m(vuninitializedq_s16(), vecDst, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 8; + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} + +#else + +void arm_f16_to_q15( + const float16_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float16_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ +#ifdef ARM_MATH_ROUNDING + float16_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* + * C = A * 65536 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + in = *pIn++; + in = (in * 32768.0); + in += in > 0.0 ? 0.5 : -0.5; + *pDst++ = clip_q31_to_q15((q31_t) (in)); + +#else + + /* + * C = A * 32768 + */ + /* + * convert from float to Q31 and then store the results in the destination buffer + */ + *pDst++ = clip_q31_to_q15((q31_t) ((_Float16)*pIn++ * 32768.0f16)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* + * Decrement the loop counter + */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of f16_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c new file mode 100644 index 0000000..0b08f12 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f16.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f16.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a f16 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + do { + mve_pred16_t p = vctp16q(blockSize); + + vstrhq_p_f16(pDst, + vdupq_m_n_f16(vuninitializedq_f16(), value, p), p); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blockSize -= 8; + } + while ((int32_t) blockSize > 0); +} +#else +void arm_fill_f16( + float16_t value, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c new file mode 100644 index 0000000..50cdd8f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c @@ -0,0 +1,189 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f32.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @defgroup Fill Vector Fill + + Fills the destination vector with a constant value. + + 
+      pDst[n] = value;   0 <= n < blockSize.
+
+ + There are separate functions for floating point, Q31, Q15, and Q7 data types. + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_f32(pDst,vdupq_n_f32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + + float32x4_t inV = vdupq_n_f32(value); + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + vst1q_f32(pDst, inV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = value */ + /* Fill the value in the destination buffer */ + *pDst++ = value; + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c new file mode 100644 index 0000000..4bc2700 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f64.c @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_f64.c + * Description: Fills a constant value into a floating-point vector + * + * $Date: 13 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +void arm_fill_f64( + float64_t value, + float64_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c new file mode 100644 index 0000000..997a728 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q15.c + * Description: Fills a constant value into a Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + + vstrhq_s16(pDst,vdupq_n_s16(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 8; + blkCnt --; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing two 16 bit values to 32 bit value in order to use SIMD */ + packedValue = __PKHBT(value, value, 16U); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 2 times 2 samples at a time */ + write_q15x2_ia (&pDst, packedValue); + write_q15x2_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c new file mode 100644 index 0000000..7da5fb6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q31.c + * Description: Fills a constant value into a Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time */ + while (blkCnt > 0U) + { + + vstrwq_s32(pDst,vdupq_n_s32(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + +} + +#else +void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c new file mode 100644 index 0000000..830fc73 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_fill_q7.c + * Description: Fills a constant value into a Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Fill + @{ + */ + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] pDst points to output vector + @param[in] blockSize number of samples in each vector + @return none + */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + + vstrbq_s8(pDst,vdupq_n_s8(value)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 16; + blkCnt --; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t packedValue; /* value packed to 32 bits */ + + /* Packing four 8 bit values to 32 bit value in order to use SIMD */ + packedValue = __PACKq7(value, value, value, value); + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = value */ + + /* fill 4 samples at a time */ + write_q7x4_ia (&pDst, packedValue); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = value */ + + /* Fill value in destination buffer */ + *pDst++ = value; + + /* Decrement loop counter */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of Fill group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c new file mode 100644 index 0000000..d627a8a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_f16.c @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to f16 vector. + @param[in] pSrc points to the f32 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && defined(__CMSIS_GCC_H) +#pragma GCC warning "Scalar version of arm_float_to_f16 built. Helium version has build issues with gcc." +#endif + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) && !defined(__CMSIS_GCC_H) + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + float32x4x2_t tmp; + float16x8_t vecDst; + float32_t const *pSrcVec; + + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* convert from float32 to float16 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); pSrcVec += 8; + /* narrow / merge */ + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vst1q(pDst, vecDst); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + tmp = vld2q(pSrcVec); + vecDst = vcvtbq_f16_f32(vecDst, tmp.val[0]); + vecDst = vcvttq_f16_f32(vecDst, tmp.val[1]); + vstrhq_p(pDst, vecDst, p0); + } +} + +#else + +void arm_float_to_f16( + const float32_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + /* + * Loop over blockSize number of values + */ + blkCnt = blockSize; + + while (blkCnt > 0U) + { + + *pDst++ = (float16_t) * pIn++; + /* + * Decrement the loop counter + */ + blkCnt--; + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c new file mode 100644 index 0000000..8061c9f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c @@ -0,0 +1,308 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q15.c + * Description: Converts the elements of the floating-point vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q15_MAX; + f32x4x2_t tmp; + q15x8_t vecDst; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + /* convert from float to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrc); + + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + + vecDst = vqmovnbq(vecDst, vcvtaq_s32_f32(tmp.val[0])); + vecDst = vqmovntq(vecDst, vcvtaq_s32_f32(tmp.val[1])); + vst1q(pDst, vecDst); + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + pDst += 8; + pSrc += 8; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pSrc++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f); + float32x4_t r; + uint32x4_t cmp; + float32_t in; + #endif + + int32x4_t cvt; + int16x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + cvt = vcvtq_n_s32_f32(inV,15); + outV = vqmovn_s32(cvt); + + vst1_s16(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 32768 */ + + /* convert from float to Q15 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 32768.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16)); + +#else + + /* C = A * 32768 */ + /* Convert from float to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c new file mode 100644 index 0000000..a222e49 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c @@ -0,0 +1,314 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q31.c + * Description: Converts the elements of the floating-point vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup float_to_x Convert 32-bit floating point value + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] pSrc points to the floating-point input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.
+
+ + @par Scaling and Overflow Behavior + The function uses saturating arithmetic. + Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated. + + @note + In order to apply rounding, the library should be rebuilt with the ROUNDING macro + defined in the preprocessor section of project options. + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + float32_t maxQ = (float32_t) Q31_MAX; + f32x4_t vecDst; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. */ + while (blkCnt > 0U) + { + + vecDst = vldrwq_f32(pSrc); + /* C = A * 2147483648 */ + /* convert from float to Q31 and then store the results in the destination buffer */ + vecDst = vmulq(vecDst, maxQ); + + vstrwq_s32(pDst, vcvtaq_s32_f32(vecDst)); + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pSrc += 4; + pDst += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrc++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pSrc++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 32768 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + + pIn += 4; + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + + outV = vcvtq_n_s32_f32(inV,31); + + vst1q_s32(pDst, outV); + pDst += 4; + pIn += 4; + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + +} +#else +void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 2147483648 */ + + /* convert from float to Q31 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 2147483648.0f); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = clip_q63_to_q31((q63_t) (in)); + +#else + + /* C = A * 2147483648 */ + /* Convert from float to Q31 and then store the results in the destination buffer */ + *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f)); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c new file mode 100644 index 0000000..27af520 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c @@ -0,0 +1,330 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_float_to_q7.c + * Description: Converts the elements of the floating-point vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup float_to_x + @{ + */ + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + *\par Description: + * \par + * The equation used for the conversion process is: + * 
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + * \note + * In order to apply rounding, the library should be rebuilt with the ROUNDING macro + * defined in the preprocessor section of project options. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + float32_t maxQ = powf(2.0, 7); + f32x4x4_t tmp; + q15x8_t evVec, oddVec; + q7x16_t vecDst; + float32_t const *pSrcVec; +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif + + pSrcVec = (float32_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* + * C = A * 128.0 + * convert from float to q7 and then store the results in the destination buffer + */ + tmp.val[0] = vmulq(tmp.val[0], maxQ); + tmp.val[1] = vmulq(tmp.val[1], maxQ); + tmp.val[2] = vmulq(tmp.val[2], maxQ); + tmp.val[3] = vmulq(tmp.val[3], maxQ); + + /* + * convert and pack evens + */ + evVec = vqmovnbq(evVec, vcvtaq_s32_f32(tmp.val[0])); + evVec = vqmovntq(evVec, vcvtaq_s32_f32(tmp.val[2])); + /* + * convert and pack odds + */ + oddVec = vqmovnbq(oddVec, vcvtaq_s32_f32(tmp.val[1])); + oddVec = vqmovntq(oddVec, vcvtaq_s32_f32(tmp.val[3])); + /* + * merge + */ + vecDst = vqmovnbq(vecDst, evVec); + vecDst = vqmovntq(vecDst, oddVec); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pSrcVec++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pSrcVec++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +#if defined(ARM_MATH_NEON) +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + const float32_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + float32x4_t inV; + #ifdef ARM_MATH_ROUNDING + float32_t in; + float32x4_t zeroV = vdupq_n_f32(0.0f); + float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f); + float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f); + float32x4_t r; + uint32x4_t cmp; + #endif + + int16x4_t cvt1,cvt2; + int8x8_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cmp = vcgtq_f32(inV,zeroV); + r = vbslq_f32(cmp,pHalf,mHalf); + inV = vaddq_f32(inV, r); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + vst1_s8(pDst, outV); + pDst += 8; + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + inV = vld1q_f32(pIn); + cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + inV = vld1q_f32(pIn); + cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7)); + pIn += 4; + + outV = vqmovn_s16(vcombine_s16(cvt1,cvt2)); + + vst1_s8(pDst, outV); + pDst += 8; +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + while (blkCnt > 0U) + { + +#ifdef ARM_MATH_ROUNDING + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + in = *pIn++; + in = (in * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + /* C = A * 128 */ + /* Convert from float to q7 and then store the results in the destination buffer */ + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement the loop counter */ + blkCnt--; + } + +} +#else +void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const float32_t *pIn = pSrc; /* Source pointer */ + +#ifdef ARM_MATH_ROUNDING + float32_t in; +#endif /* #ifdef ARM_MATH_ROUNDING */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = A * 128 */ + + /* Convert from float to q7 and store result in destination buffer */ +#ifdef ARM_MATH_ROUNDING + + in = (*pIn++ * 128); + in += in > 0.0f ? 0.5f : -0.5f; + *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8)); + +#else + + *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8); + +#endif /* #ifdef ARM_MATH_ROUNDING */ + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of float_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c new file mode 100644 index 0000000..5a46caa --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_heap_sort_f32.c + * Description: Floating point heap sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + + + +static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir) +{ + /* Put all the elements of pSrc in heap order */ + uint32_t k = i; // Initialize largest/smallest as root + uint32_t l = 2*i + 1; // left = 2*i + 1 + uint32_t r = 2*i + 2; // right = 2*i + 2 + float32_t temp; + + if (l < n && dir==(pSrc[l] > pSrc[k]) ) + k = l; + + if (r < n && dir==(pSrc[r] > pSrc[k]) ) + k = r; + + if (k != i) + { + temp = pSrc[i]; + pSrc[i]=pSrc[k]; + pSrc[k]=temp; + + arm_heapify(pSrc, n, k, dir); + } +} + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The heap sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted region, + * and shrinks the unsorted region by extracting the largest + * element and moving it to the sorted region. A heap data + * structure is used to find the maximum. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ +void arm_heap_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + float32_t * pA; + int32_t i; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Build the heap array so that the largest value is the root + for (i = blockSize/2 - 1; i >= 0; i--) + arm_heapify(pA, blockSize, i, S->dir); + + for (i = blockSize - 1; i >= 0; i--) + { + // Swap + temp = pA[i]; + pA[i] = pA[0]; + pA[0] = temp; + + // Restore heap order + arm_heapify(pA, i, 0, S->dir); + } +} +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c new file mode 100644 index 0000000..4e85043 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_insertion_sort_f32.c + * Description: Floating point insertion sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The insertion sort is a simple sorting algorithm that + * reads all the element of the input array and removes one element + * at a time, finds the location it belongs in the final sorted list, + * and inserts it there. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_insertion_sort_f32( + const arm_sort_instance_f32 * S, + float32_t *pSrc, + float32_t* pDst, + uint32_t blockSize) +{ + float32_t * pA; + uint8_t dir = S->dir; + uint32_t i, j; + float32_t temp; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + // Real all the element of the input array + for(i=0; i0 && dir==(pA[j]= end || dir==(pA[i] <= pA[j])) ) + { + pB[k] = pA[i]; + i++; + } + else + { + pB[k] = pA[j]; + j++; + } + } +} + +static void arm_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, uint8_t dir) +{ + if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide + { + int32_t middle = (end + begin) / 2; // Take the middle point + + arm_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part + arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part + + topDownMerge(pB, begin, middle, end, pA, dir); + } +} + + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The merge sort algorithm is a comparison algorithm that + * divide the input array in sublists and merge them to produce + * longer sorted sublists until there is only one list remaining. + * + * @par A work array is always needed. It must be allocated by the user + * linked to the instance at initialization time. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed + */ + + +void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize) +{ + float32_t * pA; + + /* Out-of-place */ + if(pSrc != pDst) + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t)); + pA = pDst; + } + else + pA = pSrc; + + /* A working buffer is needed */ + memcpy(S->buffer, pSrc, blockSize*sizeof(float32_t)); + + arm_merge_sort_core_f32(S->buffer, 0, blockSize, pA, S->dir); +} +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c new file mode 100644 index 0000000..bd93a00 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_merge_sort_init_f32.c + * Description: Floating point merge sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ +void arm_merge_sort_init_f32(arm_merge_sort_instance_f32 * S, arm_sort_dir dir, float32_t * buffer) +{ + S->dir = dir; + S->buffer = buffer; +} +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c new file mode 100644 index 0000000..22a7eaa --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_f16.c @@ -0,0 +1,155 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to f16 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the f16 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float16_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + int32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + /* C = (float16_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq(pDst, vcvtq_n_f16_s16(vecDst, 15)); pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 7; + if (blkCnt > 0) + { + mve_pred16_t p0 = vctp16q(blkCnt); + vecDst = vld1q(pSrcVec); pSrcVec += 8; + vstrhq_p(pDst, vcvtq_n_f16_s16(vecDst, 15), p0); + } +} +#else + +void arm_q15_to_f16( + const q15_t * pSrc, + float16_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + *pDst++ = ((_Float16) * pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float16_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((_Float16) *pIn++ / 32768.0f16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c new file mode 100644 index 0000000..1a20def --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_float.c + * Description: Converts the elements of the Q15 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q15_to_x Convert 16-bit fixed point value + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + + q15x8_t vecDst; + q15_t const *pSrcVec; + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + vecDst = vldrhq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 15)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q15_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int16x8_t inV; + int32x4_t inV0, inV1; + float32x4_t outV; + + blkCnt = blockSize >> 3U; + + /* Compute 8 outputs at a time. + ** a second loop below computes the remaining 1 to 7 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + inV = vld1q_s16(pIn); + pIn += 8; + + inV0 = vmovl_s16(vget_low_s16(inV)); + inV1 = vmovl_s16(vget_high_s16(inV)); + + outV = vcvtq_n_f32_s32(inV0,15); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inV1,15); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 8, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 7; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q15 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + *pDst++ = ((float32_t) * pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + + /* Convert from q15 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 32768.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c new file mode 100644 index 0000000..fc3c868 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c @@ -0,0 +1,182 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q31.c + * Description: Converts the elements of the Q15 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; + + q31x4_t vecDst; + + blkCnt = blockSize>> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrhq_s32((q15_t const *) pSrc); + vecDst = vshlq_n(vecDst, 16); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + q31_t in1, in2; + q31_t out1, out2, out3, out4; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t)A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + /* extract lower 16 bits to 32 bit result */ + out1 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out2 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out3 = in2 << 16U; + /* extract upper 16 bits to 32 bit result */ + out4 = in2 & 0xFFFF0000; + +#else + + /* extract upper 16 bits to 32 bit result */ + out1 = in1 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out2 = in1 << 16U; + /* extract upper 16 bits to 32 bit result */ + out3 = in2 & 0xFFFF0000; + /* extract lower 16 bits to 32 bit result */ + out4 = in2 << 16U; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + *pDst++ = out1; + *pDst++ = out2; + *pDst++ = out3; + *pDst++ = out4; + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 16 */ + + /* Convert from q15 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pIn++ << 16; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c new file mode 100644 index 0000000..eac8105 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c @@ -0,0 +1,190 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q15_to_q7.c + * Description: Converts the elements of the Q15 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q15_to_x + @{ + */ + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] pSrc points to the Q15 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8x2_t tmp; + q15_t const *pSrcVec; + q7x16_t vecDst; + + + pSrcVec = (q15_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + /* convert from q15 to q7 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 16; + vecDst = vqshrnbq_n_s16(vecDst, tmp.val[0], 8); + vecDst = vqshrntq_n_s16(vecDst, tmp.val[1], 8); + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q15_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = read_q15x2_ia (&pIn); + in2 = read_q15x2_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in1, in2, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* rotate packed value by 24 */ + out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24); + + /* anding with 0xff00ff00 to get two 8 bit values */ + out1 = out1 & 0xFF00FF00; + /* anding with 0x00ff00ff to get two 8 bit values */ + out2 = out2 & 0x00FF00FF; + + /* oring two values(contains two 8 bit values) to get four packed 8 bit values */ + out1 = out1 | out2; + + /* store 4 samples at a time to destiantion buffer */ + write_q7x4_ia (&pDst, out1); + +#else + + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + *pDst++ = (q7_t) (*pIn++ >> 8); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) A >> 8 */ + + /* Convert from q15 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 8); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q15_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c new file mode 100644 index 0000000..ce7ce42 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_float.c + * Description: Converts the elements of the Q31 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q31_to_x Convert 32-bit fixed point value + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4_t vecDst; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* convert from q31 to float and then store the results in the destination buffer */ + vecDst = vld1q(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 31)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pSrcVec++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +#if defined(ARM_MATH_NEON_EXPERIMENTAL) +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int32x4_t inV; + float32x4_t outV; + + blkCnt = blockSize >> 2U; + + /* Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + inV = vld1q_s32(pIn); + pIn += 4; + + outV = vcvtq_n_f32_s32(inV,31); + + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 3; + + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + /* Convert from q31 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 2147483648.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q31_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 2147483648 */ + + /* Convert from q31 to float and store result in destination buffer */ + *pDst++ = ((float32_t) *pIn++ / 2147483648.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c new file mode 100644 index 0000000..a25a2bb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q15.c + * Description: Converts the elements of the Q31 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x2_t tmp; + q15x8_t vecDst; + q31_t const *pSrcVec; + + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A >> 16 */ + /* convert from q31 to q15 and then store the results in the destination buffer */ + tmp = vld2q(pSrcVec); + pSrcVec += 8; + vecDst = vshrnbq_n_s32(vecDst, tmp.val[0], 16); + vecDst = vshrntq_n_s32(vecDst, tmp.val[1], 16); + vst1q(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pSrcVec++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in1, in2, in3, in4; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in1 = *pIn++; + in2 = *pIn++; + in3 = *pIn++; + in4 = *pIn++; + + /* pack two higher 16-bit values from two 32-bit values */ +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __PKHTB(in2, in1, 16); + out2 = __PKHTB(in4, in3, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHTB(in3, in4, 16); +#endif /* #ifdef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + *pDst++ = (q15_t) (*pIn++ >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) (A >> 16) */ + + /* Convert from q31 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) (*pIn++ >> 16); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c new file mode 100644 index 0000000..16fbe18 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c @@ -0,0 +1,169 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q31_to_q7.c + * Description: Converts the elements of the Q31 vector to Q7 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q31_to_x + @{ + */ + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] pSrc points to the Q31 input vector + @param[out] pDst points to the Q7 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q31x4x4_t tmp; + q15x8_t evVec, oddVec; + q7x16_t vecDst; + q31_t const *pSrcVec; + + pSrcVec = (q31_t const *) pSrc; + blkCnt = blockSize >> 4; + while (blkCnt > 0U) + { + tmp = vld4q(pSrcVec); + pSrcVec += 16; + /* C = (q7_t) A >> 24 */ + /* convert from q31 to q7 and then store the results in the destination buffer */ + /* + * narrow and pack evens + */ + evVec = vshrnbq_n_s32(evVec, tmp.val[0], 16); + evVec = vshrntq_n_s32(evVec, tmp.val[2], 16); + /* + * narrow and pack odds + */ + oddVec = vshrnbq_n_s32(oddVec, tmp.val[1], 16); + oddVec = vshrntq_n_s32(oddVec, tmp.val[3], 16); + /* + * narrow & merge + */ + vecDst = vshrnbq_n_s16(vecDst, evVec, 8); + vecDst = vshrntq_n_s16(vecDst, oddVec, 8); + + vst1q(pDst, vecDst); + pDst += 16; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + /* + * tail + */ + blkCnt = blockSize & 0xF; + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pSrcVec++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q31_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q7_t out1, out2, out3, out4; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + + out1 = (q7_t) (*pIn++ >> 24); + out2 = (q7_t) (*pIn++ >> 24); + out3 = (q7_t) (*pIn++ >> 24); + out4 = (q7_t) (*pIn++ >> 24); + write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4)); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q7_t) (A >> 24) */ + + /* Convert from q31 to q7 and store result in destination buffer */ + *pDst++ = (q7_t) (*pIn++ >> 24); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q31_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c new file mode 100644 index 0000000..9cbf8ad --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_float.c + * Description: Converts the elements of the Q7 vector to floating-point vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + * @defgroup q7_to_x Convert 8-bit fixed point value + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the floating-point output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + q7x16_t vecDst; + q7_t const *pSrcVec; + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 32768 */ + /* convert from q7 to float and then store the results in the destination buffer */ + vecDst = vldrbq_s32(pSrcVec); + pSrcVec += 4; + vstrwq(pDst, vcvtq_n_f32_s32((int32x4_t)vecDst, 7)); + pDst += 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pSrcVec++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } +} +#else +#if defined(ARM_MATH_NEON) +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + + int8x16_t inV; + int16x8_t inVLO, inVHI; + int32x4_t inVLL, inVLH, inVHL, inVHH; + float32x4_t outV; + + blkCnt = blockSize >> 4U; + + /* Compute 16 outputs at a time. + ** a second loop below computes the remaining 1 to 15 samples. */ + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + inV = vld1q_s8(pIn); + pIn += 16; + + inVLO = vmovl_s8(vget_low_s8(inV)); + inVHI = vmovl_s8(vget_high_s8(inV)); + + inVLL = vmovl_s16(vget_low_s16(inVLO)); + inVLH = vmovl_s16(vget_high_s16(inVLO)); + inVHL = vmovl_s16(vget_low_s16(inVHI)); + inVHH = vmovl_s16(vget_high_s16(inVHI)); + + outV = vcvtq_n_f32_s32(inVLL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVLH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHL,7); + vst1q_f32(pDst, outV); + pDst += 4; + + outV = vcvtq_n_f32_s32(inVHH,7); + vst1q_f32(pDst, outV); + pDst += 4; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 16, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize & 0xF; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + /* Convert from q7 to float and then store the results in the destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement the loop counter */ + blkCnt--; + } +} +#else +void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (float32_t) A / 128 */ + + /* Convert from q7 to float and store result in destination buffer */ + *pDst++ = ((float32_t) * pIn++ / 128.0f); + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* #if defined(ARM_MATH_NEON) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c new file mode 100644 index 0000000..be52531 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q15.c + * Description: Converts the elements of the Q7 vector to Q15 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q15 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.
+
+ */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + + uint32_t blkCnt; /* loop counters */ + q15x8_t vecDst; + q7_t const *pSrcVec; + + + pSrcVec = (q7_t const *) pSrc; + blkCnt = blockSize >> 3; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + /* load q7 + 32-bit widening */ + vecDst = vldrbq_s16(pSrcVec); + pSrcVec += 8; + vecDst = vecDst << 8; + vstrhq(pDst, vecDst); + pDst += 8; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + blkCnt = blockSize & 7; + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pSrcVec++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#else +void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; +#endif + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ +#if defined (ARM_MATH_DSP) + + in = read_q7x4_ia (&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + + in1 = in1 << 8U; + in2 = in2 << 8U; + + in1 = in1 & 0xFF00FF00; + in2 = in2 & 0xFF00FF00; + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); +#else + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); +#endif + + write_q15x2_ia (&pDst, out1); + write_q15x2_ia (&pDst, out2); + +#else + + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + *pDst++ = (q15_t) *pIn++ << 8; + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q15_t) A << 8 */ + + /* Convert from q7 to q15 and store result in destination buffer */ + *pDst++ = (q15_t) * pIn++ << 8; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c new file mode 100644 index 0000000..01d5f2b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_q7_to_q31.c + * Description: Converts the elements of the Q7 vector to Q31 vector + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/support_functions.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup q7_to_x + @{ + */ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] pSrc points to the Q7 input vector + @param[out] pDst points to the Q31 output vector + @param[in] blockSize number of samples in each vector + @return none + + @par Details + The equation used for the conversion process is: + 
+      pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.
+
+ */ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; + q31x4_t vecDst; + + blkCnt = blockSize >> 2; + while (blkCnt > 0U) + { + + /* C = (q31_t)A << 16 */ + /* convert from q15 to q31 and then store the results in the destination buffer */ + /* load q15 + 32-bit widening */ + vecDst = vldrbq_s32((q7_t const *) pSrc); + vecDst = vshlq_n(vecDst, 24); + vstrwq_s32(pDst, vecDst); + + /* + * Decrement the blockSize loop counter + * Advance vector source and destination pointers + */ + pDst += 4; + pSrc += 4; + blkCnt --; + } + + blkCnt = blockSize & 3; + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) *pSrc++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } +} + +#else +void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* Loop counter */ + const q7_t *pIn = pSrc; /* Source pointer */ + +#if defined (ARM_MATH_LOOPUNROLL) + + q31_t in; + + /* Loop unrolling: Compute 4 outputs at a time */ + blkCnt = blockSize >> 2U; + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + in = read_q7x4_ia (&pIn); + +#ifndef ARM_MATH_BIG_ENDIAN + + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (in & 0xFF000000); + +#else + + *pDst++ = (in & 0xFF000000); + *pDst++ = (__ROR(in, 24)) & 0xFF000000; + *pDst++ = (__ROR(in, 16)) & 0xFF000000; + *pDst++ = (__ROR(in, 8)) & 0xFF000000; + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement loop counter */ + blkCnt--; + } + + /* Loop unrolling: Compute remaining outputs */ + blkCnt = blockSize % 0x4U; + +#else + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + + while (blkCnt > 0U) + { + /* C = (q31_t) A << 24 */ + + /* Convert from q7 to q31 and store result in destination buffer */ + *pDst++ = (q31_t) * pIn++ << 24; + + /* Decrement loop counter */ + blkCnt--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c new file mode 100644 index 0000000..c6c44d9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_quick_sort_f32.c + * Description: Floating point quick sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +static uint32_t arm_quick_sort_partition_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* This function will be called */ + int32_t i, j, pivot_index; + float32_t pivot; + float32_t temp; + + /* The first element is the pivot */ + pivot_index = first; + pivot = pSrc[pivot_index]; + + /* Initialize indices for do-while loops */ + i = first - 1; + j = last + 1; + + while(i < j) + { + /* The loop will stop as soon as the indices i and j cross each other. + * + * This event will happen surely since the values of the indices are incremented and + * decrement in the do-while loops that are executed at least once. + * It is impossible to loop forever inside the do-while loops since the pivot is + * always an element of the array and the conditions cannot be always true (at least + * the i-th or the j-th element will be equal to the pivot-th element). + * For example, in the extreme case of an ordered array the do-while loop related to i will stop + * at the first iteration (because pSrc[i]=pSrc[pivot] already), and the loop related to j + * will stop after (last-first) iterations (when j=pivot=i=first). j is returned and + * j+1 is going to be used as pivot by other calls of the function, until j=pivot=last. */ + + /* Move indices to the right and to the left */ + if(dir) + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] < pivot && i pivot); + } + else + { + /* Compare left elements with pivot */ + do + { + i++; + } while (pSrc[i] > pivot && i Swap */ + temp=pSrc[i]; + pSrc[i]=pSrc[j]; + pSrc[j]=temp; + } + } + + return j; +} + +static void arm_quick_sort_core_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir) +{ + /* If the array [first ... last] has more than one element */ + if(firstdir); + /* The previous function could be called recursively a maximum + * of (blockSize-1) times, generating a stack consumption of 4*(blockSize-1) bytes. */ +} + +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c new file mode 100644 index 0000000..ad534bc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_selection_sort_f32.c + * Description: Floating point selection sort + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + +/** + * @private + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * + * @par Algorithm + * The Selection sort algorithm is a comparison algorithm that + * divides the input array into a sorted and an unsorted sublist + * (initially the sorted sublist is empty and the unsorted sublist + * is the input array), looks for the smallest (or biggest) + * element in the unsorted sublist, swapping it with the leftmost + * one, and moving the sublists boundary one element to the right. + * + * @par It's an in-place algorithm. In order to obtain an out-of-place + * function, a memcpy of the source vector is performed. + */ + +void arm_selection_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t i, j, k; + uint8_t dir = S->dir; + float32_t temp; + + float32_t * pA; + + if(pSrc != pDst) // out-of-place + { + memcpy(pDst, pSrc, blockSize*sizeof(float32_t) ); + pA = pDst; + } + else + pA = pSrc; + + /* Move the boundary one element to the right */ + for (i=0; ialg) + { + case ARM_SORT_BITONIC: + arm_bitonic_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_BUBBLE: + arm_bubble_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_HEAP: + arm_heap_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_INSERTION: + arm_insertion_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_QUICK: + arm_quick_sort_f32(S, pSrc, pDst, blockSize); + break; + + case ARM_SORT_SELECTION: + arm_selection_sort_f32(S, pSrc, pDst, blockSize); + break; + } +} + +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c new file mode 100644 index 0000000..72ad9c5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c @@ -0,0 +1,54 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_sort_init_f32.c + * Description: Floating point sort initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_sorting.h" + +/** + @ingroup groupSupport + */ + +/** + @addtogroup Sorting + @{ + */ + + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ +void arm_sort_init_f32(arm_sort_instance_f32 * S, arm_sort_alg alg, arm_sort_dir dir) +{ + S->alg = alg; + S->dir = dir; +} + +/** + @} end of Sorting group + */ diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c new file mode 100644 index 0000000..f9aae6b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f16.c @@ -0,0 +1,146 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f16.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupSupport + */ + +/** + @defgroup weightedsum Weighted Sum + + Weighted sum of values + */ + + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float16_t arm_weighted_sum_f16(const float16_t *in,const float16_t *weigths, uint32_t blockSize) +{ + _Float16 accum1, accum2; + float16x8_t accum1V, accum2V; + float16x8_t inV, wV; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f16(0.0f16); + accum2V = vdupq_n_f16(0.0f16); + + blkCnt = blockSize >> 3; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF16Mve(accum1V); + accum2 = vecAddAcrossF16Mve(accum2V); + + blkCnt = blockSize & 7; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else + +float16_t arm_weighted_sum_f16(const float16_t *in, const float16_t *weigths, uint32_t blockSize) +{ + + _Float16 accum1, accum2; + const float16_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f16; + accum2=0.0f16; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += (_Float16)*pIn++ * (_Float16)*pW; + accum2 += (_Float16)*pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ + diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c new file mode 100644 index 0000000..dd37861 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_weighted_sum_f32.c + * Description: Weighted Sum + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "dsp/support_functions.h" + +/** + * @addtogroup weightedsum + * @{ + */ + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" + +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + float32_t accum1, accum2; + f32x4_t accum1V, accum2V; + f32x4_t inV, wV; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + + accum1V = vdupq_n_f32(0.0); + accum2V = vdupq_n_f32(0.0); + + blkCnt = blockSize >> 2; + while (blkCnt > 0) + { + inV = vld1q(pIn); + wV = vld1q(pW); + + pIn += 4; + pW += 4; + + accum1V = vfmaq(accum1V, inV, wV); + accum2V = vaddq(accum2V, wV); + blkCnt--; + } + + accum1 = vecAddAcrossF32Mve(accum1V); + accum2 = vecAddAcrossF32Mve(accum2V); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return (accum1 / accum2); +} + +#else +#if defined(ARM_MATH_NEON) + +#include "NEMath.h" +float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + float32x4_t accum1V, accum2V; + float32x2_t tempV; + + float32x4_t inV,wV; + + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + accum1V = vdupq_n_f32(0.0f); + accum2V = vdupq_n_f32(0.0f); + + blkCnt = blockSize >> 2; + while(blkCnt > 0) + { + inV = vld1q_f32(pIn); + wV = vld1q_f32(pW); + + pIn += 4; + pW += 4; + + accum1V = vmlaq_f32(accum1V,inV,wV); + accum2V = vaddq_f32(accum2V,wV); + blkCnt--; + } + + tempV = vpadd_f32(vget_low_f32(accum1V),vget_high_f32(accum1V)); + accum1 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + tempV = vpadd_f32(vget_low_f32(accum2V),vget_high_f32(accum2V)); + accum2 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1); + + blkCnt = blockSize & 3; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + + return(accum1 / accum2); +} +#else +float32_t arm_weighted_sum_f32(const float32_t *in, const float32_t *weigths, uint32_t blockSize) +{ + + float32_t accum1, accum2; + const float32_t *pIn, *pW; + uint32_t blkCnt; + + + pIn = in; + pW = weigths; + + accum1=0.0f; + accum2=0.0f; + + blkCnt = blockSize; + while(blkCnt > 0) + { + accum1 += *pIn++ * *pW; + accum2 += *pW++; + blkCnt--; + } + + return(accum1 / accum2); +} +#endif +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + * @} end of weightedsum group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt b/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt new file mode 100644 index 0000000..e598f82 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/CMakeLists.txt @@ -0,0 +1,213 @@ +cmake_minimum_required (VERSION 3.14) + +project(CMSISDSPTransform) + +include(configLib) +include(configDsp) + +add_library(CMSISDSPTransform STATIC) +configLib(CMSISDSPTransform ${ROOT}) +configDsp(CMSISDSPTransform ${ROOT}) + +include(fft) +fft(CMSISDSPTransform) + +if (CONFIGTABLE AND ALLFFT) +target_compile_definitions(CMSISDSPTransform PUBLIC ARM_ALL_FFT_TABLES) +endif() + +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal.c) +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal2.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_bitreversal_f16.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F32_16 OR CFFT_F32_32 OR CFFT_F32_64 OR CFFT_F32_128 OR CFFT_F32_256 OR CFFT_F32_512 + OR CFFT_F32_1024 OR CFFT_F32_2048 OR CFFT_F32_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f32.c) +endif() + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F16_16 OR CFFT_F16_32 OR CFFT_F16_64 OR CFFT_F16_128 OR CFFT_F16_256 OR CFFT_F16_512 + OR CFFT_F16_1024 OR CFFT_F16_2048 OR CFFT_F16_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f16.c) +endif() +endif() + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_F16_128 OR RFFT_F16_512 OR RFFT_F16_2048 OR RFFT_F16_8192) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f16.c) +endif() +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_F64_16 OR CFFT_F64_32 OR CFFT_F64_64 OR CFFT_F64_128 OR CFFT_F64_256 OR CFFT_F64_512 + OR CFFT_F64_1024 OR CFFT_F64_2048 OR CFFT_F64_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f64.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f64.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q15_16 OR CFFT_Q15_32 OR CFFT_Q15_64 OR CFFT_Q15_128 OR CFFT_Q15_256 OR CFFT_Q15_512 + OR CFFT_Q15_1024 OR CFFT_Q15_2048 OR CFFT_Q15_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR CFFT_Q31_16 OR CFFT_Q31_32 OR CFFT_Q31_64 OR CFFT_Q31_128 OR CFFT_Q31_256 OR CFFT_Q31_512 + OR CFFT_Q31_1024 OR CFFT_Q31_2048 OR CFFT_Q31_4096) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +endif() + + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_F32_128 OR DCT4_F32_512 OR DCT4_F32_2048 OR DCT4_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_f32.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR DCT4_Q31_128 OR DCT4_Q31_512 OR DCT4_Q31_2048 OR DCT4_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q31.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ALLFFT OR DCT4_Q15_128 OR DCT4_Q15_512 OR DCT4_Q15_2048 OR DCT4_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_dct4_q15.c) + +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F32_32 OR RFFT_FAST_F32_64 OR RFFT_FAST_F32_128 + OR RFFT_FAST_F32_256 OR RFFT_FAST_F32_512 OR RFFT_FAST_F32_1024 OR RFFT_FAST_F32_2048 + OR RFFT_FAST_F32_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F64_32 OR RFFT_FAST_F64_64 OR RFFT_FAST_F64_128 + OR RFFT_FAST_F64_256 OR RFFT_FAST_F64_512 OR RFFT_FAST_F64_1024 OR RFFT_FAST_F64_2048 + OR RFFT_FAST_F64_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f64.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f64.c) +endif() + +if ((NOT DISABLEFLOAT16)) +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_FAST_F16_32 OR RFFT_FAST_F16_64 OR RFFT_FAST_F16_128 + OR RFFT_FAST_F16_256 OR RFFT_FAST_F16_512 OR RFFT_FAST_F16_1024 OR RFFT_FAST_F16_2048 + OR RFFT_FAST_F16_4096 ) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_fast_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix8_f16.c) +endif() +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_F32_128 OR RFFT_F32_512 OR RFFT_F32_2048 OR RFFT_F32_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_f32.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q15_32 OR RFFT_Q15_64 OR RFFT_Q15_128 OR RFFT_Q15_256 + OR RFFT_Q15_512 OR RFFT_Q15_1024 OR RFFT_Q15_2048 OR RFFT_Q15_4096 OR RFFT_Q15_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR RFFT_Q31_32 OR RFFT_Q31_64 OR RFFT_Q31_128 OR RFFT_Q31_256 + OR RFFT_Q31_512 OR RFFT_Q31_1024 OR RFFT_Q31_2048 OR RFFT_Q31_4096 OR RFFT_Q31_8192) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_rfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_q31.c) +endif() + +if (WRAPPER OR ARM_CFFT_RADIX2_Q15) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q15.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ARM_CFFT_RADIX4_Q15) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q15.c) +endif() + +if (WRAPPER OR ARM_CFFT_RADIX2_Q31) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_q31.c) +endif() + +if (NOT CONFIGTABLE OR ALLFFT OR ARM_CFFT_RADIX4_Q31) + target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix4_init_q31.c) +endif() + +# For scipy or wrappers or benchmarks +if (WRAPPER) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_f32.c) +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_cfft_radix2_init_f16.c) +endif() + + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_BITREV_1024) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_F32_4096) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_Q31_4096) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_Q15_4096) +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) + target_compile_definitions(CMSISDSPTransform PUBLIC ARM_TABLE_TWIDDLECOEF_F16_4096) +endif() +endif() + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_f32.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_f32.c) + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_q31.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_q31.c) + +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_q15.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_q15.c) + +if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16)) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_init_f16.c) +target_sources(CMSISDSPTransform PRIVATE arm_mfcc_f16.c) +endif() + +### Includes +target_include_directories(CMSISDSPTransform PUBLIC "${DSP}/Include") + + + diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c new file mode 100644 index 0000000..f327801 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: TransformFunctions.c + * Description: Combination of all transform function source files. + * + * $Date: 18. March 2019 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_bitreversal.c" +#include "arm_bitreversal2.c" +#include "arm_cfft_f32.c" +#include "arm_cfft_f64.c" +#include "arm_cfft_q15.c" +#include "arm_cfft_q31.c" +#include "arm_cfft_init_f32.c" +#include "arm_cfft_init_f64.c" +#include "arm_cfft_init_q15.c" +#include "arm_cfft_init_q31.c" +#include "arm_cfft_radix2_f32.c" +#include "arm_cfft_radix2_q15.c" +#include "arm_cfft_radix2_q31.c" +#include "arm_cfft_radix4_f32.c" +#include "arm_cfft_radix4_q15.c" +#include "arm_cfft_radix4_q31.c" +#include "arm_cfft_radix8_f32.c" +#include "arm_rfft_fast_f32.c" +#include "arm_rfft_fast_f64.c" +#include "arm_rfft_fast_init_f32.c" +#include "arm_rfft_fast_init_f64.c" + +#include "arm_mfcc_init_f32.c" +#include "arm_mfcc_f32.c" + +#include "arm_mfcc_init_q31.c" +#include "arm_mfcc_q31.c" + +#include "arm_mfcc_init_q15.c" +#include "arm_mfcc_q15.c" + +/* Deprecated */ + +#include "arm_dct4_f32.c" +#include "arm_dct4_init_f32.c" +#include "arm_dct4_init_q15.c" +#include "arm_dct4_init_q31.c" +#include "arm_dct4_q15.c" +#include "arm_dct4_q31.c" + +#include "arm_rfft_f32.c" +#include "arm_rfft_q15.c" +#include "arm_rfft_q31.c" + +#include "arm_rfft_init_f32.c" +#include "arm_rfft_init_q15.c" +#include "arm_rfft_init_q31.c" + +#include "arm_cfft_radix4_init_f32.c" +#include "arm_cfft_radix4_init_q15.c" +#include "arm_cfft_radix4_init_q31.c" + +#include "arm_cfft_radix2_init_f32.c" +#include "arm_cfft_radix2_init_q15.c" +#include "arm_cfft_radix2_init_q31.c" diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c new file mode 100644 index 0000000..b082d44 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctionsF16.c @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: TransformFunctionsF16.c + * Description: Combination of all transform function f16 source files. + * + * $Date: 20. April 2020 + * $Revision: V1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_cfft_f16.c" +#include "arm_cfft_init_f16.c" +#include "arm_cfft_radix2_f16.c" +#include "arm_cfft_radix4_f16.c" +#include "arm_rfft_fast_init_f16.c" +#include "arm_rfft_fast_f16.c" +#include "arm_cfft_radix8_f16.c" + +#include "arm_bitreversal_f16.c" + +#include "arm_mfcc_init_f16.c" +#include "arm_mfcc_f16.c" + +/* Deprecated */ +#include "arm_cfft_radix2_init_f16.c" +#include "arm_cfft_radix4_init_f16.c" diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c new file mode 100644 index 0000000..687a9e8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @brief In-place floating-point bit reversal function. + @param[in,out] pSrc points to in-place floating-point data buffer + @param[in] fftSize length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none + */ + +void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float32_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + +/** + @brief In-place Q31 bit reversal function. + @param[in,out] pSrc points to in-place Q31 data buffer. + @param[in] fftLen length of FFT. + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + uint32_t fftLenBy2, fftLenBy2p1, i, j; + q31_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} + + + +/** + @brief In-place Q15 bit reversal function. + @param[in,out] pSrc16 points to in-place Q15 data buffer + @param[in] fftLen length of FFT + @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_q15( + q15_t * pSrc16, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab) +{ + q31_t *pSrc = (q31_t *) pSrc16; + q31_t in; + uint32_t fftLenBy2, fftLenBy2p1; + uint32_t i, j; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftLen / 2U; + fftLenBy2p1 = (fftLen / 2U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[i]; + pSrc[i] = pSrc[j]; + pSrc[j] = in; + + /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */ + /* pSrc[i + fftLenBy2p1+1U] <-> pSrc[j + fftLenBy2p1+1U] */ + in = pSrc[i + fftLenBy2p1]; + pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1]; + pSrc[j + fftLenBy2p1] = in; + } + + /* pSrc[i+1U] <-> pSrc[j+fftLenBy2]; */ + /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1U] */ + in = pSrc[i + 1U]; + pSrc[i + 1U] = pSrc[j + fftLenBy2]; + pSrc[j + fftLenBy2] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S new file mode 100644 index 0000000..c16091b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S @@ -0,0 +1,216 @@ +;/* ---------------------------------------------------------------------- +; * Project: CMSIS DSP Library +; * Title: arm_bitreversal2.S +; * Description: arm_bitreversal_32 function done in assembly for maximum speed. +; * Called after doing an fft to reorder the output. +; * The function is loop unrolled by 2. arm_bitreversal_16 as well. +; * +; * $Date: 18. March 2019 +; * $Revision: V1.5.2 +; * +; * Target Processor: Cortex-M cores +; * -------------------------------------------------------------------- */ +;/* +; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +#if defined ( __CC_ARM ) /* Keil */ + #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2 + #define LABEL +#elif defined ( __IASMARM__ ) /* IAR */ + #define CODESECT SECTION `.text`:CODE + #define PROC + #define LABEL + #define ENDP + #define EXPORT PUBLIC +#elif defined ( __CSMC__ ) /* Cosmic */ + #define CODESECT switch .text + #define THUMB + #define EXPORT xdef + #define PROC : + #define LABEL : + #define ENDP + #define arm_bitreversal_32 _arm_bitreversal_32 +#elif defined ( __TI_ARM__ ) /* TI ARM */ + #define THUMB .thumb + #define CODESECT .text + #define EXPORT .global + #define PROC : .asmfunc + #define LABEL : + #define ENDP .endasmfunc + #define END +#elif defined ( __GNUC__ ) /* GCC */ + #define THUMB .thumb + #define CODESECT .section .text + #define EXPORT .global + #define PROC : + #define LABEL : + #define ENDP + #define END + + .syntax unified +#endif + + CODESECT + THUMB + +;/** +; @brief In-place bit reversal function. +; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type +; @param[in] bitRevLen bit reversal table length +; @param[in] pBitRevTab points to bit reversal table +; @return none +; */ + EXPORT arm_bitreversal_32 + EXPORT arm_bitreversal_16 + +#if defined ( __CC_ARM ) /* Keil */ +#elif defined ( __IASMARM__ ) /* IAR */ +#elif defined ( __CSMC__ ) /* Cosmic */ +#elif defined ( __TI_ARM__ ) /* TI ARM */ +#elif defined ( __GNUC__ ) /* GCC */ + .type arm_bitreversal_16, %function + .type arm_bitreversal_32, %function +#endif + +#if defined (ARM_MATH_CM0_FAMILY) + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_32_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + LDR r5,[r2,#4] + LDR r4,[r6,#4] + STR r5,[r6,#4] + STR r4,[r2,#4] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r6} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + PUSH {r4-r6} + ADDS r1,r2,#0 + LSRS r3,r3,#1 +arm_bitreversal_16_0 LABEL + LDRH r2,[r1,#2] + LDRH r6,[r1,#0] + LSRS r2,r2,#1 + LSRS r6,r6,#1 + ADD r2,r0,r2 + ADD r6,r0,r6 + LDR r5,[r2,#0] + LDR r4,[r6,#0] + STR r5,[r6,#0] + STR r4,[r2,#0] + ADDS r1,r1,#4 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r6} + BX lr + ENDP + +#else + +arm_bitreversal_32 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8 + ADD r9,r0,r9 + ADD r2,r0,r2 + ADD r12,r0,r12 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + LDR r7,[r9,#4] + LDR r6,[r8,#4] + LDR r5,[r2,#4] + LDR r4,[r12,#4] + STR r6,[r9,#4] + STR r7,[r8,#4] + STR r5,[r12,#4] + STR r4,[r2,#4] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_32_0 + POP {r4-r9} + BX lr + ENDP + +arm_bitreversal_16 PROC + ADDS r3,r1,#1 + CMP r3,#1 + IT LS + BXLS lr + PUSH {r4-r9} + ADDS r1,r2,#2 + LSRS r3,r3,#2 +arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */ + LDRH r8,[r1,#4] + LDRH r9,[r1,#2] + LDRH r2,[r1,#0] + LDRH r12,[r1,#-2] + ADD r8,r0,r8,LSR #1 + ADD r9,r0,r9,LSR #1 + ADD r2,r0,r2,LSR #1 + ADD r12,r0,r12,LSR #1 + LDR r7,[r9,#0] + LDR r6,[r8,#0] + LDR r5,[r2,#0] + LDR r4,[r12,#0] + STR r6,[r9,#0] + STR r7,[r8,#0] + STR r5,[r12,#0] + STR r4,[r2,#0] + ADDS r1,r1,#8 + SUBS r3,r3,#1 + BNE arm_bitreversal_16_0 + POP {r4-r9} + BX lr + ENDP + +#endif + + END diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c new file mode 100644 index 0000000..77fac1f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c @@ -0,0 +1,134 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal2.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @brief In-place 64 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 64-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_64( + uint64_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint64_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + +/** + @brief In-place 32 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 32-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_32( + uint32_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint32_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} + + +/** + @brief In-place 16 bit reversal function. + @param[in,out] pSrc points to in-place buffer of unknown 16-bit data type + @param[in] bitRevLen bit reversal table length + @param[in] pBitRevTab points to bit reversal table + @return none +*/ + +void arm_bitreversal_16( + uint16_t *pSrc, + const uint16_t bitRevLen, + const uint16_t *pBitRevTab) +{ + uint16_t a, b, i, tmp; + + for (i = 0; i < bitRevLen; ) + { + a = pBitRevTab[i ] >> 2; + b = pBitRevTab[i + 1] >> 2; + + //real + tmp = pSrc[a]; + pSrc[a] = pSrc[b]; + pSrc[b] = tmp; + + //complex + tmp = pSrc[a+1]; + pSrc[a+1] = pSrc[b+1]; + pSrc[b+1] = tmp; + + i += 2; + } +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c new file mode 100644 index 0000000..2e64636 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal_f16.c @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_bitreversal_f16.c + * Description: Bitreversal functions + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +/* +* @brief In-place bit reversal function. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftSize length of the FFT. +* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. +* @param[in] *pBitRevTab points to the bit reversal table. +* @return none. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_bitreversal_f16( +float16_t * pSrc, +uint16_t fftSize, +uint16_t bitRevFactor, +const uint16_t * pBitRevTab) +{ + uint16_t fftLenBy2, fftLenBy2p1; + uint16_t i, j; + float16_t in; + + /* Initializations */ + j = 0U; + fftLenBy2 = fftSize >> 1U; + fftLenBy2p1 = (fftSize >> 1U) + 1U; + + /* Bit Reversal Implementation */ + for (i = 0U; i <= (fftLenBy2 - 2U); i += 2U) + { + if (i < j) + { + /* pSrc[i] <-> pSrc[j]; */ + in = pSrc[2U * i]; + pSrc[2U * i] = pSrc[2U * j]; + pSrc[2U * j] = in; + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[(2U * i) + 1U]; + pSrc[(2U * i) + 1U] = pSrc[(2U * j) + 1U]; + pSrc[(2U * j) + 1U] = in; + + /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */ + in = pSrc[2U * (i + fftLenBy2p1)]; + pSrc[2U * (i + fftLenBy2p1)] = pSrc[2U * (j + fftLenBy2p1)]; + pSrc[2U * (j + fftLenBy2p1)] = in; + + /* pSrc[i+fftLenBy2p1+1U] <-> pSrc[j+fftLenBy2p1+1U] */ + in = pSrc[(2U * (i + fftLenBy2p1)) + 1U]; + pSrc[(2U * (i + fftLenBy2p1)) + 1U] = + pSrc[(2U * (j + fftLenBy2p1)) + 1U]; + pSrc[(2U * (j + fftLenBy2p1)) + 1U] = in; + + } + + /* pSrc[i+1U] <-> pSrc[j+1U] */ + in = pSrc[2U * (i + 1U)]; + pSrc[2U * (i + 1U)] = pSrc[2U * (j + fftLenBy2)]; + pSrc[2U * (j + fftLenBy2)] = in; + + /* pSrc[i+2U] <-> pSrc[j+2U] */ + in = pSrc[(2U * (i + 1U)) + 1U]; + pSrc[(2U * (i + 1U)) + 1U] = pSrc[(2U * (j + fftLenBy2)) + 1U]; + pSrc[(2U * (j + fftLenBy2)) + 1U] = in; + + /* Reading the index for the bit reversal */ + j = *pBitRevTab; + + /* Updating the bit reversal index depending on the fft length */ + pBitRevTab += bitRevFactor; + } +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c new file mode 100644 index 0000000..edfc0b4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f16.c @@ -0,0 +1,842 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f32.c + * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" +#include "arm_mve_tables_f16.h" + + +static float16_t arm_inverse_fft_length_f16(uint16_t fftLen) +{ + float16_t retValue=1.0; + + switch (fftLen) + { + + case 4096U: + retValue = (float16_t)0.000244140625f; + break; + + case 2048U: + retValue = (float16_t)0.00048828125f; + break; + + case 1024U: + retValue = (float16_t)0.0009765625f; + break; + + case 512U: + retValue = (float16_t)0.001953125f; + break; + + case 256U: + retValue = (float16_t)0.00390625f; + break; + + case 128U: + retValue = (float16_t)0.0078125f; + break; + + case 64U: + retValue = (float16_t)0.015625f; + break; + + case 32U: + retValue = (float16_t)0.03125f; + break; + + case 16U: + retValue = (float16_t)0.0625f; + break; + + + default: + break; + } + return(retValue); +} + + +static void _arm_radix4_butterfly_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = + { ( 0 - 16) * (int32_t)sizeof(float16_t *) + , ( 4 - 16) * (int32_t)sizeof(float16_t *) + , ( 8 - 16) * (int32_t)sizeof(float16_t *) + , (12 - 16) * (int32_t)sizeof(float16_t *)}; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f16 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f16_mve(const arm_cfft_instance_f16 * S, float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_f16_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f16_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t * pSrc, uint32_t fftLen, float16_t onebyfftLen) +{ + f16x8_t vecTmp0, vecTmp1; + f16x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f16x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + ( 0 - 16) * (int32_t)sizeof(q31_t *), + ( 4 - 16) * (int32_t)sizeof(q31_t *), + ( 8 - 16) * (int32_t)sizeof(q31_t *), + (12 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float16_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float16_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float16_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float16_t *inA = pBase; + float16_t *inB = inA + n2 * CMPLX_DIM; + float16_t *inC = inB + n2 * CMPLX_DIM; + float16_t *inD = inC + n2 * CMPLX_DIM; + float16_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float16_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float16_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f16x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 2 f32 complex pair + */ + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_f16(inB); + vecD = vldrhq_f16(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 8; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_f16(inA); + vecC = vldrhq_f16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 4); + vecD = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 12); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = (f16x8_t)vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = (f16x8_t)vldrwq_gather_base_f32(vecScGathAddr, 8); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, (f32x4_t)vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 4, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, (f32x4_t)vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 12, (f32x4_t)vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f16_mve(const arm_cfft_instance_f16 * S,float16_t *pSrc, uint32_t fftLen) +{ + float16_t const *pCoefVec; + float16_t const *pCoef = S->pTwiddle; + float16_t *pIn0, *pIn1; + uint32_t n2; + float16_t onebyfftLen = arm_inverse_fft_length_f16(fftLen); + uint32_t blkCnt; + f16x8_t vecIn0, vecIn1, vecSum, vecDiff; + f16x8_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + while (blkCnt > 0U) + { + vecIn0 = *(f16x8_t *) pIn0; + vecIn1 = *(f16x8_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecSum = vaddq(vecIn0, vecIn1); + vecDiff = vsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 8; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f16_mve(S, pSrc, fftLen, arm_inverse_fft_length_f16(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f16_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f16_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + + +extern void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + +extern void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new arm_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new arm_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f16( + const arm_cfft_instance_f16 * S, + float16_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float16_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f16 ( p1, L, (float16_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_16((uint16_t*)p1, S->bitRevLength,(uint16_t*)S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f16/(_Float16)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; l>= 2u; + for (int k = fftLen / 4u; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 +=4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_Conj_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* load scheduling */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + /* pre-load for next iteration */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_f32_mve(const arm_cfft_instance_f32 * S, float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_Conj_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_f32_mve(S, pSrc, n2); + + _arm_radix4_butterfly_f32_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; +} + +static void _arm_radix4_butterfly_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t * pSrc, uint32_t fftLen, float32_t onebyfftLen) +{ + f32x4_t vecTmp0, vecTmp1; + f32x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + f32x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), + (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), + (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + for (int k = fftLen / 4; k > 1; k >>= 2) + { + float32_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + float32_t const *p_rearranged_twiddle_tab_stride3 = + &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + + float32_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + float32_t *inA = pBase; + float32_t *inB = inA + n2 * CMPLX_DIM; + float32_t *inC = inB + n2 * CMPLX_DIM; + float32_t *inD = inC + n2 * CMPLX_DIM; + float32_t const *pW1 = p_rearranged_twiddle_tab_stride1; + float32_t const *pW2 = p_rearranged_twiddle_tab_stride2; + float32_t const *pW3 = p_rearranged_twiddle_tab_stride3; + f32x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 f32 complex pair + */ + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_f32(inB); + vecD = vldrwq_f32(inD); + + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vecSum0 + vecSum1; + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vecSum0 - vecSum1; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inB, vecTmp1); + inB += 4; + + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inC, vecTmp1); + inC += 4; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FLT_AxB(vecW, vecTmp0); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_f32(inA); + vecC = vldrwq_f32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vecA + vecC; /* vecSum0 = vaddq(vecA, vecC) */ + vecDiff0 = vecA - vecC; /* vecSum0 = vsubq(vecA, vecC) */ + + vecB = vldrwq_gather_base_f32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_f32(vecScGathAddr, 24); + + vecSum1 = vecB + vecD; + vecDiff1 = vecB - vecD; + + vecA = vldrwq_gather_base_wb_f32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_f32(vecScGathAddr, 16); + + vecTmp0 = vecSum0 + vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vecSum0 - vecSum1; + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_A_ixB(vecDiff0, vecDiff1); + vecTmp0 = vecTmp0 * onebyfftLen; + vstrwq_scatter_base_f32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * End of last stage process + */ +} + +static void arm_cfft_radix4by2_inverse_f32_mve(const arm_cfft_instance_f32 * S,float32_t *pSrc, uint32_t fftLen) +{ + float32_t const *pCoefVec; + float32_t const *pCoef = S->pTwiddle; + float32_t *pIn0, *pIn1; + uint32_t n2; + float32_t onebyfftLen = arm_inverse_fft_length_f32(fftLen); + uint32_t blkCnt; + f32x4_t vecIn0, vecIn1, vecSum, vecDiff; + f32x4_t vecCmplxTmp, vecTw; + + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 2; + while (blkCnt > 0U) + { + vecIn0 = *(f32x4_t *) pIn0; + vecIn1 = *(f32x4_t *) pIn1; + vecTw = vld1q(pCoefVec); + pCoefVec += 4; + + vecSum = vecIn0 + vecIn1; + vecDiff = vecIn0 - vecIn1; + + vecCmplxTmp = MVE_CMPLX_MULT_FLT_AxB(vecTw, vecDiff); + + vst1q(pIn0, vecSum); + pIn0 += 4; + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, n2, onebyfftLen); + + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc + fftLen, n2, onebyfftLen); +} + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_f32_mve(S, pSrc, fftLen, arm_inverse_fft_length_f32(S->fftLen)); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_f32_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_f32_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f32_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + + +#else +extern void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** + @ingroup groupTransforms + */ + +/** + @defgroup ComplexFFT Complex FFT Functions + + @par + The Fast Fourier Transform (FFT) is an efficient algorithm for computing the + Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster + than the DFT, especially for long lengths. + The algorithms described in this section + operate on complex data. A separate set of functions is devoted to handling + of real sequences. + @par + There are separate algorithms for handling floating-point, Q15, and Q31 data + types. The algorithms available for each data type are described next. + @par + The FFT functions operate in-place. That is, the array holding the input data + will also be used to hold the corresponding result. The input data is complex + and contains 2*fftLen interleaved values as shown below. + 
{real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain + values will have the same interleaving. + + @par Floating-point + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8 + stages are performed along with a single radix-2 or radix-4 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + For the MVE version, the new arm_cfft_init_f32 initialization function is + mandatory. Compilation flags are available to include only the required tables for the + needed FFTs. Other FFT versions can continue to be initialized as + explained below. + @par + For not MVE versions, pre-initialized data structures containing twiddle factors + and bit reversal tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_f32. For example: + @par + arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_f32 function follows: + @code + const static arm_cfft_instance_f32 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_f32_len16; + break; + case 32: + S = &arm_cfft_sR_f32_len32; + break; + case 64: + S = &arm_cfft_sR_f32_len64; + break; + case 128: + S = &arm_cfft_sR_f32_len128; + break; + case 256: + S = &arm_cfft_sR_f32_len256; + break; + case 512: + S = &arm_cfft_sR_f32_len512; + break; + case 1024: + S = &arm_cfft_sR_f32_len1024; + break; + case 2048: + S = &arm_cfft_sR_f32_len2048; + break; + case 4096: + S = &arm_cfft_sR_f32_len4096; + break; + } + @endcode + @par + The new arm_cfft_init_f32 can also be used. + @par Q15 and Q31 + The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4 + stages are performed along with a single radix-2 stage, as needed. + The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses + a different twiddle factor table. + @par + The function uses the standard FFT definition and output values may grow by a + factor of fftLen when computing the forward transform. The + inverse transform includes a scale of 1/fftLen as part of the + calculation and this matches the textbook definition of the inverse FFT. + @par + Pre-initialized data structures containing twiddle factors and bit reversal + tables are provided and defined in arm_const_structs.h. Include + this header in your function and then pass one of the constant structures as + an argument to arm_cfft_q31. For example: + @par + arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1) + @par + computes a 64-point inverse complex FFT including bit reversal. + The data structures are treated as constant data and not modified during the + calculation. The same data structure can be reused for multiple transforms + including mixing forward and inverse transforms. + @par + Earlier releases of the library provided separate radix-2 and radix-4 + algorithms that operated on floating-point data. These functions are still + provided but are deprecated. The older functions are slower and less general + than the new functions. + @par + An example of initialization of the constants for the arm_cfft_q31 function follows: + @code + const static arm_cfft_instance_q31 *S; + ... + switch (length) { + case 16: + S = &arm_cfft_sR_q31_len16; + break; + case 32: + S = &arm_cfft_sR_q31_len32; + break; + case 64: + S = &arm_cfft_sR_q31_len64; + break; + case 128: + S = &arm_cfft_sR_q31_len128; + break; + case 256: + S = &arm_cfft_sR_q31_len256; + break; + case 512: + S = &arm_cfft_sR_q31_len512; + break; + case 1024: + S = &arm_cfft_sR_q31_len1024; + break; + case 2048: + S = &arm_cfft_sR_q31_len2048; + break; + case 4096: + S = &arm_cfft_sR_q31_len4096; + break; + } + @endcode + + */ + +void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen; + float32_t * pCol1, * pCol2, * pMid1, * pMid2; + float32_t * p2 = p1 + L; + const float32_t * tw = (float32_t *) S->pTwiddle; + float32_t t1[4], t2[4], t3[4], t4[4], twR, twI; + float32_t m0, m1, m2, m3; + uint32_t l; + + pCol1 = p1; + pCol2 = p2; + + /* Define new length */ + L >>= 1; + + /* Initialize mid pointers */ + pMid1 = p1 + L; + pMid2 = p2 + L; + + /* do two dot Fourier transform */ + for (l = L >> 2; l > 0; l-- ) + { + t1[0] = p1[0]; + t1[1] = p1[1]; + t1[2] = p1[2]; + t1[3] = p1[3]; + + t2[0] = p2[0]; + t2[1] = p2[1]; + t2[2] = p2[2]; + t2[3] = p2[3]; + + t3[0] = pMid1[0]; + t3[1] = pMid1[1]; + t3[2] = pMid1[2]; + t3[3] = pMid1[3]; + + t4[0] = pMid2[0]; + t4[1] = pMid2[1]; + t4[2] = pMid2[2]; + t4[3] = pMid2[3]; + + *p1++ = t1[0] + t2[0]; + *p1++ = t1[1] + t2[1]; + *p1++ = t1[2] + t2[2]; + *p1++ = t1[3] + t2[3]; /* col 1 */ + + t2[0] = t1[0] - t2[0]; + t2[1] = t1[1] - t2[1]; + t2[2] = t1[2] - t2[2]; + t2[3] = t1[3] - t2[3]; /* for col 2 */ + + *pMid1++ = t3[0] + t4[0]; + *pMid1++ = t3[1] + t4[1]; + *pMid1++ = t3[2] + t4[2]; + *pMid1++ = t3[3] + t4[3]; /* col 1 */ + + t4[0] = t4[0] - t3[0]; + t4[1] = t4[1] - t3[1]; + t4[2] = t4[2] - t3[2]; + t4[3] = t4[3] - t3[3]; /* for col 2 */ + + twR = *tw++; + twI = *tw++; + + /* multiply by twiddle factors */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + /* R = R * Tr - I * Ti */ + *p2++ = m0 + m1; + /* I = I * Tr + R * Ti */ + *p2++ = m2 - m3; + + /* use vertical symmetry */ + /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */ + m0 = t4[0] * twI; + m1 = t4[1] * twR; + m2 = t4[1] * twI; + m3 = t4[0] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + + twR = *tw++; + twI = *tw++; + + m0 = t2[2] * twR; + m1 = t2[3] * twI; + m2 = t2[3] * twR; + m3 = t2[2] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + + m0 = t4[2] * twI; + m1 = t4[3] * twR; + m2 = t4[3] * twI; + m3 = t4[2] * twR; + + *pMid2++ = m0 - m1; + *pMid2++ = m2 + m3; + } + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U); +} + +void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, float32_t * p1) +{ + uint32_t L = S->fftLen >> 1; + float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4; + const float32_t *tw2, *tw3, *tw4; + float32_t * p2 = p1 + L; + float32_t * p3 = p2 + L; + float32_t * p4 = p3 + L; + float32_t t2[4], t3[4], t4[4], twR, twI; + float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1; + float32_t m0, m1, m2, m3; + uint32_t l, twMod2, twMod3, twMod4; + + pCol1 = p1; /* points to real values by default */ + pCol2 = p2; + pCol3 = p3; + pCol4 = p4; + pEnd1 = p2 - 1; /* points to imaginary values by default */ + pEnd2 = p3 - 1; + pEnd3 = p4 - 1; + pEnd4 = pEnd3 + L; + + tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle; + + L >>= 1; + + /* do four dot Fourier transform */ + + twMod2 = 2; + twMod3 = 4; + twMod4 = 6; + + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* Twiddle factors are ones */ + *p2++ = t2[0]; + *p2++ = t2[1]; + *p3++ = t3[0]; + *p3++ = t3[1]; + *p4++ = t4[0]; + *p4++ = t4[1]; + + tw2 += twMod2; + tw3 += twMod3; + tw4 += twMod4; + + for (l = (L - 2) >> 1; l > 0; l-- ) + { + /* TOP */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* BOTTOM */ + p1ap3_1 = pEnd1[-1] + pEnd3[-1]; + p1sp3_1 = pEnd1[-1] - pEnd3[-1]; + p1ap3_0 = pEnd1[ 0] + pEnd3[0]; + p1sp3_0 = pEnd1[ 0] - pEnd3[0]; + /* col 2 */ + t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1; + t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1]; + /* col 3 */ + t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1]; + t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0]; + /* col 4 */ + t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1; + t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0; + /* col 1 - Bottom */ + *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0]; + *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1]; + + /* COL 2 */ + /* read twiddle factors */ + twR = *tw2++; + twI = *tw2++; + /* multiply by twiddle factors */ + /* let Z1 = a + i(b), Z2 = c + i(d) */ + /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */ + + /* Top */ + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* use vertical symmetry col 2 */ + /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */ + /* Bottom */ + m0 = t2[3] * twI; + m1 = t2[2] * twR; + m2 = t2[2] * twI; + m3 = t2[3] * twR; + + *pEnd2-- = m0 - m1; + *pEnd2-- = m2 + m3; + + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + tw3 += twMod3; + /* Top */ + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* use vertical symmetry col 3 */ + /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */ + /* Bottom */ + m0 = -t3[3] * twR; + m1 = t3[2] * twI; + m2 = t3[2] * twR; + m3 = t3[3] * twI; + + *pEnd3-- = m0 - m1; + *pEnd3-- = m3 - m2; + + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + tw4 += twMod4; + /* Top */ + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + /* use vertical symmetry col 4 */ + /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */ + /* Bottom */ + m0 = t4[3] * twI; + m1 = t4[2] * twR; + m2 = t4[2] * twI; + m3 = t4[3] * twR; + + *pEnd4-- = m0 - m1; + *pEnd4-- = m2 + m3; + } + + /* MIDDLE */ + /* Twiddle factors are */ + /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */ + p1ap3_0 = p1[0] + p3[0]; + p1sp3_0 = p1[0] - p3[0]; + p1ap3_1 = p1[1] + p3[1]; + p1sp3_1 = p1[1] - p3[1]; + + /* col 2 */ + t2[0] = p1sp3_0 + p2[1] - p4[1]; + t2[1] = p1sp3_1 - p2[0] + p4[0]; + /* col 3 */ + t3[0] = p1ap3_0 - p2[0] - p4[0]; + t3[1] = p1ap3_1 - p2[1] - p4[1]; + /* col 4 */ + t4[0] = p1sp3_0 - p2[1] + p4[1]; + t4[1] = p1sp3_1 + p2[0] - p4[0]; + /* col 1 - Top */ + *p1++ = p1ap3_0 + p2[0] + p4[0]; + *p1++ = p1ap3_1 + p2[1] + p4[1]; + + /* COL 2 */ + twR = tw2[0]; + twI = tw2[1]; + + m0 = t2[0] * twR; + m1 = t2[1] * twI; + m2 = t2[1] * twR; + m3 = t2[0] * twI; + + *p2++ = m0 + m1; + *p2++ = m2 - m3; + /* COL 3 */ + twR = tw3[0]; + twI = tw3[1]; + + m0 = t3[0] * twR; + m1 = t3[1] * twI; + m2 = t3[1] * twR; + m3 = t3[0] * twI; + + *p3++ = m0 + m1; + *p3++ = m2 - m3; + /* COL 4 */ + twR = tw4[0]; + twI = tw4[1]; + + m0 = t4[0] * twR; + m1 = t4[1] * twI; + m2 = t4[1] * twR; + m3 = t4[0] * twI; + + *p4++ = m0 + m1; + *p4++ = m2 - m3; + + /* first col */ + arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U); + + /* second col */ + arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U); + + /* third col */ + arm_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U); + + /* fourth col */ + arm_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U); +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the floating-point complex FFT. + @param[in] S points to an instance of the floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float32_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for (l = 0; l < L; l++) + { + *pSrc = -*pSrc; + pSrc += 2; + } + } + + switch (L) + { + case 16: + case 128: + case 1024: + arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 32: + case 256: + case 2048: + arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1); + break; + case 64: + case 512: + case 4096: + arm_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1); + break; + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0f / (float32_t)L; + + /* Conjugate and scale output data */ + pSrc = p1; + for (l= 0; l < L; l++) + { + *pSrc++ *= invL ; + *pSrc = -(*pSrc) * invL; + pSrc++; + } + } +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c new file mode 100644 index 0000000..d686eb8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f64.c @@ -0,0 +1,318 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_f64.c + * Description: Combined Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +extern void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_bitreversal_64( + uint64_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +/** +* @} end of ComplexFFT group +*/ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f64( + float64_t * pSrc, + uint16_t fftLen, + const float64_t * pCoef, + uint16_t twidCoefModifier) +{ + + float64_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + + float64_t t1, t2, r1, r2, s1, s2; + + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } +} + +/* +* @brief Core function for the Double Precision floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of F64 data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f64( + float64_t * pSrc, + uint32_t fftLen, + const float64_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float64_t xt, yt, cosVal, sinVal; + float64_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + } + + // first col + arm_radix4_butterfly_f64( pSrc, n2, (float64_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f64( pSrc + fftLen, n2, (float64_t*)pCoef, 2U); + +} + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Double Precision floating-point complex FFT. + @param[in] S points to an instance of the Double Precision floating-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen, l; + float64_t invL, * pSrc; + + if (ifftFlag == 1U) + { + /* Conjugate input data */ + pSrc = p1 + 1; + for(l=0; lpTwiddle, 1U); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_f64 ( p1, L, (float64_t*)S->pTwiddle); + break; + + } + + if ( bitReverseFlag ) + arm_bitreversal_64((uint64_t*)p1, S->bitRevLength,S->pBitRevTable); + + if (ifftFlag == 1U) + { + invL = 1.0 / (float64_t)L; + /* Conjugate and scale output data */ + pSrc = p1; + for(l=0; lbitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f16 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_const_structs_f16.h" + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables_f16.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f16(arm_cfft_instance_f16 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f16; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f16; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f16; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f16; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f16; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f16; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f16; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f16; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f16; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F16_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float16_t *)twiddleCoefF16_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F16_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float16_t *)twiddleCoefF16_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F16_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float16_t *)twiddleCoefF16_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F16_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float16_t *)twiddleCoefF16_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F16_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float16_t *)twiddleCoefF16_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F16_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float16_t *)twiddleCoefF16_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F16_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float16_t *)twiddleCoefF16_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F16_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float16_t *)twiddleCoefF16_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F16_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float16_t *)twiddleCoefF16_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f16(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_init_f16( + arm_cfft_instance_f16 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f16,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f16,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f16,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f16,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f16,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f16,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c new file mode 100644 index 0000000..abfab4a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f32.c @@ -0,0 +1,358 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f32.c + * Description: Initialization function for cfft f32 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f32 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + +arm_status arm_cfft_radix4by2_rearrange_twiddles_f32(arm_cfft_instance_f32 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_f32; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_f32; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_f32; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) \ + || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_f32; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_f32; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_f32; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_f32; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_f32; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_f32; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_F32_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (float32_t *)twiddleCoef_4096; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (float32_t *)twiddleCoef_2048; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (float32_t *)twiddleCoef_1024; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (float32_t *)twiddleCoef_512; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (float32_t *)twiddleCoef_256; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (float32_t *)twiddleCoef_128; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (float32_t *)twiddleCoef_64; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (float32_t *)twiddleCoef_32; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (float32_t *)twiddleCoef_16; + status=arm_cfft_radix4by2_rearrange_twiddles_f32(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f32,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f32,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f32,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f32,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f32,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f32,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c new file mode 100644 index 0000000..61167fd --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_f64.c @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_f64.c + * Description: Initialization function for cfft f64 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft f64 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + + +arm_status arm_cfft_init_f64( + arm_cfft_instance_f64 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(f64,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT_256)) + case 256U: + FFTINIT(f64,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT_128)) + case 128U: + FFTINIT(f64,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT_64)) + case 64U: + FFTINIT(f64,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT_32)) + case 32U: + FFTINIT(f64,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(f64,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c new file mode 100644 index 0000000..3cf6e3a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q15.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q15.c + * Description: Initialization function for cfft q15 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q15 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q15(arm_cfft_instance_q15 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q15; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q15; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q15; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q15; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q15; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q15; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q15; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q15; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q15; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q15_t *)twiddleCoef_4096_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q15_t *)twiddleCoef_2048_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q15_t *)twiddleCoef_1024_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q15_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q15_t *)twiddleCoef_512_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q15_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q15_t *)twiddleCoef_256_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q15_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q15_t *)twiddleCoef_128_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q15_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q15_t *)twiddleCoef_64_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q15_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q15_t *)twiddleCoef_32_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q15_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q15_t *)twiddleCoef_16_q15; + status=arm_cfft_radix4by2_rearrange_twiddles_q15(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q15,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q15,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q15,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q15,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q15,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q15,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c new file mode 100644 index 0000000..3722a68 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_init_q31.c @@ -0,0 +1,356 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_init_q31.c + * Description: Initialization function for cfft q31 instance + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define FFTINIT(EXT,SIZE) \ + S->bitRevLength = arm_cfft_sR_##EXT##_len##SIZE.bitRevLength; \ + S->pBitRevTable = arm_cfft_sR_##EXT##_len##SIZE.pBitRevTable; \ + S->pTwiddle = arm_cfft_sR_##EXT##_len##SIZE.pTwiddle; + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the cfft q31 function + @param[in,out] S points to an instance of the floating-point CFFT structure + @param[in] fftLen fft length (number of complex samples) + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + + @par Use of this function is mandatory only for the MVE version of the FFT. + Other versions can still initialize directly the data structure using + variables declared in arm_const_structs.h + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" +#include "arm_mve_tables.h" + + +arm_status arm_cfft_radix4by2_rearrange_twiddles_q31(arm_cfft_instance_q31 *S, int twidCoefModifier) +{ + + switch (S->fftLen >> (twidCoefModifier - 1)) { + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_4096_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_4096_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_4096_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_4096_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_4096_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_4096_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + case 1024U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_1024_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_1024_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_1024_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_1024_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_1024_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_1024_q31; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + case 256U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_256_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_256_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_256_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_256_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_256_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_256_q31; + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 64U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_64_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_64_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_64_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_64_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_64_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_64_q31; + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 16U: + S->rearranged_twiddle_tab_stride1_arr = rearranged_twiddle_tab_stride1_arr_16_q31; + S->rearranged_twiddle_stride1 = rearranged_twiddle_stride1_16_q31; + + S->rearranged_twiddle_tab_stride2_arr = rearranged_twiddle_tab_stride2_arr_16_q31; + S->rearranged_twiddle_stride2 = rearranged_twiddle_stride2_16_q31; + + S->rearranged_twiddle_tab_stride3_arr = rearranged_twiddle_tab_stride3_arr_16_q31; + S->rearranged_twiddle_stride3 = rearranged_twiddle_stride3_16_q31; + break; +#endif + + default: + return(ARM_MATH_ARGUMENT_ERROR); + break; + /* invalid sizes already filtered */ + } + + return(ARM_MATH_SUCCESS); + +} + + + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { + /* Initializations of structure parameters for 4096 point FFT */ +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_4096) && defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)) + case 4096U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_4096; + S->pTwiddle = (q31_t *)twiddleCoef_4096_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_2048) && defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_2048; + S->pTwiddle = (q31_t *)twiddleCoef_2048_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_1024) && defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_1024; + S->pTwiddle = (q31_t *)twiddleCoef_1024_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_512) && defined(ARM_TABLE_TWIDDLECOEF_Q31_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_512; + S->pTwiddle = (q31_t *)twiddleCoef_512_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_256) && defined(ARM_TABLE_TWIDDLECOEF_Q31_256)) + case 256U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_256; + S->pTwiddle = (q31_t *)twiddleCoef_256_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_128) && defined(ARM_TABLE_TWIDDLECOEF_Q31_128)) + case 128U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_128; + S->pTwiddle = (q31_t *)twiddleCoef_128_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_64) && defined(ARM_TABLE_TWIDDLECOEF_Q31_64)) + case 64U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_64; + S->pTwiddle = (q31_t *)twiddleCoef_64_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_32) && defined(ARM_TABLE_TWIDDLECOEF_Q31_32)) + case 32U: + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_32; + S->pTwiddle = (q31_t *)twiddleCoef_32_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 2); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_BITREVIDX_FXT_16) && defined(ARM_TABLE_TWIDDLECOEF_Q31_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->bitRevLength = ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH; + S->pBitRevTable = (uint16_t *)armBitRevIndexTable_fixed_16; + S->pTwiddle = (q31_t *)twiddleCoef_16_q31; + status=arm_cfft_radix4by2_rearrange_twiddles_q31(S, 1); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#else +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = NULL; + + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,4096); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,2048); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,1024); + + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the bit reversal table modifier */ + FFTINIT(q31,512); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 256U: + FFTINIT(q31,256); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 128U: + FFTINIT(q31,128); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 64U: + FFTINIT(q31,64); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 32U: + FFTINIT(q31,32); + break; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + FFTINIT(q31,16); + break; +#endif + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + + return (status); +} +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c new file mode 100644 index 0000000..74a6e7a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c @@ -0,0 +1,893 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q15.c + * Description: Combined Radix Decimation in Q15 Frequency CFFT processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q15_mve( + const arm_cfft_instance_q15 * S, + q15_t *pSrc, + uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32 ((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } + +} + +static void arm_cfft_radix4by2_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q15x8_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + _arm_radix4_butterfly_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q15_mve(S, pSrc + fftLen, n2); + + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +static void _arm_radix4_butterfly_inverse_q15_mve(const arm_cfft_instance_q15 *S,q15_t *pSrc, uint32_t fftLen) +{ + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q15x8_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q15_t *), (4 - 16) * (int32_t)sizeof(q15_t *), + (8 - 16) * (int32_t)sizeof(q15_t *), (12 - 16) * (int32_t)sizeof(q15_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q15_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q15_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q15_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q15_t *inA = pBase; + q15_t *inB = inA + n2 * CMPLX_DIM; + q15_t *inC = inB + n2 * CMPLX_DIM; + q15_t *inD = inC + n2 * CMPLX_DIM; + q15_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q15_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q15_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q15x8_t vecW; + + + blkCnt = n2 / 4; + /* + * load 4 x q15 complex pair + */ + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + while (blkCnt > 0U) + { + vecB = vldrhq_s16(inB); + vecD = vldrhq_s16(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 8; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + + vst1q(inB, vecTmp1); + inB += 8; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inC, vecTmp1); + inC += 8; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 8; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q15x8_t); + vst1q(inD, vecTmp1); + inD += 8; + + vecA = vldrhq_s16(inA); + vecC = vldrhq_s16(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + blkCnt = (fftLen >> 4); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 4); + vecD = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 12); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = (q15x8_t) vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = (q15x8_t) vldrwq_gather_base_s32(vecScGathAddr, 8); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, (int32x4_t) vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 4, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, (int32x4_t) vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 12, (int32x4_t) vecTmp0); + + blkCnt--; + } +} + +static void arm_cfft_radix4by2_inverse_q15_mve(const arm_cfft_instance_q15 *S, q15_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q15_t *pIn0; + q15_t *pIn1; + const q15_t *pCoef = S->pTwiddle; + + uint32_t blkCnt; + q15x8_t vecIn0, vecIn1, vecSum, vecDiff; + q15x8_t vecCmplxTmp, vecTw; + q15_t const *pCoefVec; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + pCoefVec = pCoef; + + blkCnt = n2 / 4; + + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn1 = *(q15x8_t *) pIn1; + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 8; + + vecTw = vld1q(pCoefVec); + pCoefVec += 8; + + vecDiff = vhsubq(vecIn0, vecIn1); + vecCmplxTmp = vqrdmlsdhq(vuninitializedq_s16() , vecDiff, vecTw); + vecCmplxTmp = vqrdmladhxq(vecCmplxTmp, vecDiff, vecTw); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 8; + + blkCnt--; + } + + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 3; + while (blkCnt > 0U) + { + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 8; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 7; + while (blkCnt > 0U) + { + mve_pred16_t p0 = vctp16q(blkCnt); + + vecIn0 = *(q15x8_t *) pIn0; + vecIn0 = vecIn0 << 1; + vstrhq_p(pIn0, vecIn0, p0); + } +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q15_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_16_inpl_mve((uint16_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} + +#else + +extern void arm_radix4_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_16( + uint16_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for Q15 complex FFT. + @param[in] S points to an instance of Q15 CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q15 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q15 ( p1, L, (q15_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q15 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_16 ((uint16_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16U; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 ) ); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } + +} + +void arm_cfft_radix4by2_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef) +{ + uint32_t i; + uint32_t n2; + q15_t p0, p1, p2, p3; +#if defined (ARM_MATH_DSP) + q31_t T, S, R; + q31_t coeff, out1, out2; + const q15_t *pC = pCoef; + q15_t *pSi = pSrc; + q15_t *pSl = pSrc + fftLen; +#else + uint32_t l; + q15_t xt, yt, cosVal, sinVal; +#endif + + n2 = fftLen >> 1U; + +#if defined (ARM_MATH_DSP) + + for (i = n2; i > 0; i--) + { + coeff = read_q15x2_ia (&pC); + + T = read_q15x2 (pSi); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + S = read_q15x2 (pSl); + S = __SHADD16(S, 0); /* this is just a SIMD arithmetic shift right by 1 */ + + R = __QSUB16(T, S); + + write_q15x2_ia (&pSi, __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16U; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2_ia (&pSl, (q31_t)__PKHBT( out1, out2, 0 )); + } + +#else /* #if defined (ARM_MATH_DSP) */ + + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16U)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16U)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16U)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16U)) ); + } + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* first col */ + arm_radix4_butterfly_inverse_q15( pSrc, n2, (q15_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q15( pSrc + fftLen, n2, (q15_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + p2 = pSrc[4 * i + 2]; + p3 = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + p2 <<= 1U; + p3 <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = p2; + pSrc[4 * i + 3] = p3; + } +} + +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c new file mode 100644 index 0000000..78ce505 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c @@ -0,0 +1,847 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_q31.c + * Description: Combined Radix Decimation in Frequency CFFT fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_vec_fft.h" + + +static void _arm_radix4_butterfly_q31_mve( + const arm_cfft_instance_q31 * S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxB(vecW, vecTmp0, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + + +static void arm_cfft_radix4by2_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + uint32_t blkCnt; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxConjB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + blkCnt--; + } + + _arm_radix4_butterfly_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +static void _arm_radix4_butterfly_inverse_q31_mve( + const arm_cfft_instance_q31 *S, + q31_t *pSrc, + uint32_t fftLen) +{ + q31x4_t vecTmp0, vecTmp1; + q31x4_t vecSum0, vecDiff0, vecSum1, vecDiff1; + q31x4_t vecA, vecB, vecC, vecD; + uint32_t blkCnt; + uint32_t n1, n2; + uint32_t stage = 0; + int32_t iter = 1; + static const int32_t strides[4] = { + (0 - 16) * (int32_t)sizeof(q31_t *), (1 - 16) * (int32_t)sizeof(q31_t *), + (8 - 16) * (int32_t)sizeof(q31_t *), (9 - 16) * (int32_t)sizeof(q31_t *) + }; + + /* + * Process first stages + * Each stage in middle stages provides two down scaling of the input + */ + n2 = fftLen; + n1 = n2; + n2 >>= 2u; + + for (int k = fftLen / 4u; k > 1; k >>= 2u) + { + q31_t const *p_rearranged_twiddle_tab_stride2 = + &S->rearranged_twiddle_stride2[ + S->rearranged_twiddle_tab_stride2_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride3 = &S->rearranged_twiddle_stride3[ + S->rearranged_twiddle_tab_stride3_arr[stage]]; + q31_t const *p_rearranged_twiddle_tab_stride1 = + &S->rearranged_twiddle_stride1[ + S->rearranged_twiddle_tab_stride1_arr[stage]]; + + q31_t * pBase = pSrc; + for (int i = 0; i < iter; i++) + { + q31_t *inA = pBase; + q31_t *inB = inA + n2 * CMPLX_DIM; + q31_t *inC = inB + n2 * CMPLX_DIM; + q31_t *inD = inC + n2 * CMPLX_DIM; + q31_t const *pW1 = p_rearranged_twiddle_tab_stride1; + q31_t const *pW2 = p_rearranged_twiddle_tab_stride2; + q31_t const *pW3 = p_rearranged_twiddle_tab_stride3; + q31x4_t vecW; + + blkCnt = n2 / 2; + /* + * load 2 x q31 complex pair + */ + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + while (blkCnt > 0U) + { + vecB = vldrwq_s32(inB); + vecD = vldrwq_s32(inD); + + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * [ 1 1 1 1 ] * [ A B C D ]' .* 1 + */ + vecTmp0 = vhaddq(vecSum0, vecSum1); + vst1q(inA, vecTmp0); + inA += 4; + /* + * [ 1 -1 1 -1 ] * [ A B C D ]' + */ + vecTmp0 = vhsubq(vecSum0, vecSum1); + /* + * [ 1 -1 1 -1 ] * [ A B C D ]'.* W2 + */ + vecW = vld1q(pW2); + pW2 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + + vst1q(inB, vecTmp1); + inB += 4; + /* + * [ 1 -i -1 +i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 -i -1 +i ] * [ A B C D ]'.* W1 + */ + vecW = vld1q(pW1); + pW1 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inC, vecTmp1); + inC += 4; + /* + * [ 1 +i -1 -i ] * [ A B C D ]' + */ + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + /* + * [ 1 +i -1 -i ] * [ A B C D ]'.* W3 + */ + vecW = vld1q(pW3); + pW3 += 4; + vecTmp1 = MVE_CMPLX_MULT_FX_AxConjB(vecTmp0, vecW, q31x4_t); + vst1q(inD, vecTmp1); + inD += 4; + + vecA = vldrwq_s32(inA); + vecC = vldrwq_s32(inC); + + blkCnt--; + } + pBase += CMPLX_DIM * n1; + } + n1 = n2; + n2 >>= 2u; + iter = iter << 2; + stage++; + } + + /* + * End of 1st stages process + * data is in 11.21(q21) format for the 1024 point as there are 3 middle stages + * data is in 9.23(q23) format for the 256 point as there are 2 middle stages + * data is in 7.25(q25) format for the 64 point as there are 1 middle stage + * data is in 5.27(q27) format for the 16 point as there are no middle stages + */ + + /* + * start of Last stage process + */ + uint32x4_t vecScGathAddr = vld1q_u32((uint32_t*)strides); + vecScGathAddr = vecScGathAddr + (uint32_t) pSrc; + + /* + * load scheduling + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + blkCnt = (fftLen >> 3); + while (blkCnt > 0U) + { + vecSum0 = vhaddq(vecA, vecC); + vecDiff0 = vhsubq(vecA, vecC); + + vecB = vldrwq_gather_base_s32(vecScGathAddr, 8); + vecD = vldrwq_gather_base_s32(vecScGathAddr, 24); + + vecSum1 = vhaddq(vecB, vecD); + vecDiff1 = vhsubq(vecB, vecD); + /* + * pre-load for next iteration + */ + vecA = vldrwq_gather_base_wb_s32(&vecScGathAddr, 64); + vecC = vldrwq_gather_base_s32(vecScGathAddr, 16); + + vecTmp0 = vhaddq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64, vecTmp0); + + vecTmp0 = vhsubq(vecSum0, vecSum1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 8, vecTmp0); + + vecTmp0 = MVE_CMPLX_ADD_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 16, vecTmp0); + + vecTmp0 = MVE_CMPLX_SUB_FX_A_ixB(vecDiff0, vecDiff1); + vstrwq_scatter_base_s32(vecScGathAddr, -64 + 24, vecTmp0); + + blkCnt--; + } + /* + * output is in 11.21(q21) format for the 1024 point + * output is in 9.23(q23) format for the 256 point + * output is in 7.25(q25) format for the 64 point + * output is in 5.27(q27) format for the 16 point + */ +} + +static void arm_cfft_radix4by2_inverse_q31_mve(const arm_cfft_instance_q31 *S, q31_t *pSrc, uint32_t fftLen) +{ + uint32_t n2; + q31_t *pIn0; + q31_t *pIn1; + const q31_t *pCoef = S->pTwiddle; + + //uint16_t twidCoefModifier = arm_cfft_radix2_twiddle_factor(S->fftLen); + //q31_t twidIncr = (2 * twidCoefModifier * sizeof(q31_t)); + uint32_t blkCnt; + //uint64x2_t vecOffs; + q31x4_t vecIn0, vecIn1, vecSum, vecDiff; + q31x4_t vecCmplxTmp, vecTw; + + n2 = fftLen >> 1; + + pIn0 = pSrc; + pIn1 = pSrc + fftLen; + //vecOffs[0] = 0; + //vecOffs[1] = (uint64_t) twidIncr; + blkCnt = n2 / 2; + + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn1 = vld1q_s32(pIn1); + + vecIn0 = vecIn0 >> 1; + vecIn1 = vecIn1 >> 1; + vecSum = vhaddq(vecIn0, vecIn1); + vst1q(pIn0, vecSum); + pIn0 += 4; + + //vecTw = (q31x4_t) vldrdq_gather_offset_s64(pCoef, vecOffs); + vecTw = vld1q_s32(pCoef); + pCoef += 4; + vecDiff = vhsubq(vecIn0, vecIn1); + + vecCmplxTmp = MVE_CMPLX_MULT_FX_AxB(vecDiff, vecTw, q31x4_t); + vst1q(pIn1, vecCmplxTmp); + pIn1 += 4; + + //vecOffs = vaddq((q31x4_t) vecOffs, 2 * twidIncr); + blkCnt--; + } + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, n2); + + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc + fftLen, n2); + + pIn0 = pSrc; + blkCnt = (fftLen << 1) >> 2; + while (blkCnt > 0U) + { + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vst1q(pIn0, vecIn0); + pIn0 += 4; + blkCnt--; + } + /* + * tail + * (will be merged thru tail predication) + */ + blkCnt = (fftLen << 1) & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + + vecIn0 = vld1q_s32(pIn0); + vecIn0 = vecIn0 << 1; + vstrwq_p(pIn0, vecIn0, p0); + } + +} + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * pSrc, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t fftLen = S->fftLen; + + if (ifftFlag == 1U) { + + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_inverse_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31_mve(S, pSrc, fftLen); + break; + } + } else { + switch (fftLen) { + case 16: + case 64: + case 256: + case 1024: + case 4096: + _arm_radix4_butterfly_q31_mve(S, pSrc, fftLen); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31_mve(S, pSrc, fftLen); + break; + } + } + + + if (bitReverseFlag) + { + + arm_bitreversal_32_inpl_mve((uint32_t*)pSrc, S->bitRevLength, S->pBitRevTable); + + } +} +#else + +extern void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +extern void arm_bitreversal_32( + uint32_t * pSrc, + const uint16_t bitRevLen, + const uint16_t * pBitRevTable); + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 complex FFT. + @param[in] S points to an instance of the fixed-point CFFT structure + @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return none + */ +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + uint32_t L = S->fftLen; + + if (ifftFlag == 1U) + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_inverse_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_inverse_q31 ( p1, L, S->pTwiddle ); + break; + } + } + else + { + switch (L) + { + case 16: + case 64: + case 256: + case 1024: + case 4096: + arm_radix4_butterfly_q31 ( p1, L, (q31_t*)S->pTwiddle, 1 ); + break; + + case 32: + case 128: + case 512: + case 2048: + arm_cfft_radix4by2_q31 ( p1, L, S->pTwiddle ); + break; + } + } + + if ( bitReverseFlag ) + arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_cfft_radix4by2_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1; + pSrc[2 * l + 1] = p1 << 1; + } + + + /* first col */ + arm_radix4_butterfly_q31 (pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_q31 (pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } + +} + +void arm_cfft_radix4by2_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef) +{ + uint32_t i, l; + uint32_t n2; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2 * i]; + sinVal = pCoef[2 * i + 1]; + + l = i + n2; + + xt = (pSrc[2 * i] >> 2U) - (pSrc[2 * l] >> 2U); + pSrc[2 * i] = (pSrc[2 * i] >> 2U) + (pSrc[2 * l] >> 2U); + + yt = (pSrc[2 * i + 1] >> 2U) - (pSrc[2 * l + 1] >> 2U); + pSrc[2 * i + 1] = (pSrc[2 * l + 1] >> 2U) + (pSrc[2 * i + 1] >> 2U); + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2 * l] = p0 << 1U; + pSrc[2 * l + 1] = p1 << 1U; + } + + /* first col */ + arm_radix4_butterfly_inverse_q31( pSrc, n2, (q31_t*)pCoef, 2U); + + /* second col */ + arm_radix4_butterfly_inverse_q31( pSrc + fftLen, n2, (q31_t*)pCoef, 2U); + + n2 = fftLen >> 1U; + for (i = 0; i < n2; i++) + { + p0 = pSrc[4 * i + 0]; + p1 = pSrc[4 * i + 1]; + xt = pSrc[4 * i + 2]; + yt = pSrc[4 * i + 3]; + + p0 <<= 1U; + p1 <<= 1U; + xt <<= 1U; + yt <<= 1U; + + pSrc[4 * i + 0] = p0; + pSrc[4 * i + 1] = p1; + pSrc[4 * i + 2] = xt; + pSrc[4 * i + 3] = yt; + } +} +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c new file mode 100644 index 0000000..8863fbc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f16.c @@ -0,0 +1,475 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f16.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +void arm_radix2_butterfly_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f16( +const arm_cfft_radix2_instance_f16 * S, + float16_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- +** Internal helper function used by the FFTs +** ------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix2_butterfly_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif // #if defined (ARM_MATH_DSP) + +} + + +void arm_radix2_butterfly_inverse_f16( +float16_t * pSrc, +uint32_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1, p2, p3; + float16_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * i + 2]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * i + 2]; + + a1 = (_Float16)pSrc[2 * i + 3] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * i + 3]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 - (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 + (_Float16)p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p2 = (_Float16)xt * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p3 = (_Float16)yt * (_Float16)onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2U * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2U * l + 1U] = p3; + } // butterfly loop end + +#endif // #if defined (ARM_MATH_DSP) + +} + + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c new file mode 100644 index 0000000..ab218a5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c @@ -0,0 +1,470 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_f32.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Radix-2 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future + @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_f32( +const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-2 */ + arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-2 */ + arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, + S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + + +/** + @} end of ComplexFFT group + */ + + + +/* ---------------------------------------------------------------------- + ** Internal helper function used by the FFTs + ** ------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix2_butterfly_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + /* Initializations for the first stage */ + n2 = fftLen >> 1; + ia = 0; + i = 0; + + // loop for groups + for (k = n2; k > 0; k--) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + /* Twiddle coefficients index modifier */ + ia += twidCoefModifier; + + /* index calculation for the input as, */ + /* pSrc[i + 0], pSrc[i + fftLen/1] */ + l = i + n2; + + /* Butterfly implementation */ + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i++; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = n2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2); // groups loop end + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + pSrc[2 * i + 2] = xt; + pSrc[2 * i + 3] = yt; + } // groups loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 1; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 + p1; + pSrc[2 * l + 1] = p2 - p3; + + i += n1; + } while (i < fftLen); + j++; + } while (j < n2); + twidCoefModifier <<= 1U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + float32_t xt, yt, cosVal, sinVal; + float32_t p0, p1, p2, p3; + float32_t a0, a1; + +#if defined (ARM_MATH_DSP) + + n2 = fftLen >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia += twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while (j < n2); // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + // loop for butterfly + for (i = 0; i < fftLen; i += 2) + { + a0 = pSrc[2 * i] + pSrc[2 * i + 2]; + xt = pSrc[2 * i] - pSrc[2 * i + 2]; + + a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * i + 3]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * i + 1] = p1; + pSrc[2 * i + 2] = p2; + pSrc[2 * i + 3] = p3; + } // butterfly loop end + +#else /* #if defined (ARM_MATH_DSP) */ + + n2 = fftLen; + + // loop for stage + for (k = fftLen; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + j = 0; + do + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + do + { + l = i + n2; + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + + p0 = xt * cosVal; + p1 = yt * sinVal; + p2 = yt * cosVal; + p3 = xt * sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = p0 - p1; + pSrc[2 * l + 1] = p2 + p3; + + i += n1; + } while ( i < fftLen ); // butterfly loop end + j++; + } while ( j < n2 ); // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + a0 = pSrc[2 * i] + pSrc[2 * l]; + xt = pSrc[2 * i] - pSrc[2 * l]; + + a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1]; + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + + p0 = a0 * onebyfftLen; + p2 = xt * onebyfftLen; + p1 = a1 * onebyfftLen; + p3 = yt * onebyfftLen; + + pSrc[2 * i] = p0; + pSrc[2 * l] = p2; + + pSrc[2 * i + 1] = p1; + pSrc[2 * l + 1] = p3; + } // butterfly loop end + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c new file mode 100644 index 0000000..e021a0e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f16.c @@ -0,0 +1,214 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f16.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix2_init_f16( + arm_cfft_radix2_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16_4096; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c new file mode 100644 index 0000000..ae9f29a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c @@ -0,0 +1,209 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_f32.c + * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.00048828125; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.001953125; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + S->onebyfftLen = 0.0078125; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 32U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + S->onebyfftLen = 0.03125; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c new file mode 100644 index 0000000..68c9930 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q15.c + * Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 2048U: + /* Initializations of structure parameters for 2048 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 512U: + /* Initializations of structure parameters for 512 point FFT */ + S->twidCoefModifier = 8U; + S->bitRevFactor = 8U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c new file mode 100644 index 0000000..73b8a39 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c @@ -0,0 +1,191 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_init_q31.c + * Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 2048 point FFT */ + case 2048U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 2U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 2U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[1]; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + /* Initializations of structure parameters for 512 point FFT */ + case 512U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 8U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 8U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[7]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 128U: + /* Initializations of structure parameters for 128 point FFT */ + S->twidCoefModifier = 32U; + S->bitRevFactor = 32U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[31]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 32U: + /* Initializations of structure parameters for 32 point FFT */ + S->twidCoefModifier = 128U; + S->bitRevFactor = 128U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[127]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c new file mode 100644 index 0000000..ca15ea1 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c @@ -0,0 +1,689 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q15.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q15 (pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(coeff, R) >> 16; + out2 = __SMUSDX(coeff, R); +#else + out1 = __SMUSDX(R, coeff) >> 16U; + out2 = __SMUAD(coeff, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2U * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + i += n1; + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* groups loop end */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) + + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2U * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) - + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +void arm_radix2_butterfly_inverse_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pCoef, + uint16_t twidCoefModifier) +{ +#if defined (ARM_MATH_DSP) + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t in; + q31_t T, S, R; + q31_t coeff, out1, out2; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (i = 0; i < n2; i++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + i++; + l++; + + T = read_q15x2 (pSrc + (2 * i)); + in = ((int16_t) (T & 0xFFFF)) >> 1; + T = ((T >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + S = read_q15x2 (pSrc + (2 * l)); + in = ((int16_t) (S & 0xFFFF)) >> 1; + S = ((S >> 1) & 0xFFFF0000) | (in & 0xFFFF); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + i += n1; + + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __SHADD16(T, S)); + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(coeff, R) >> 16; + out2 = __SMUADX(coeff, R); +#else + out1 = __SMUADX(R, coeff) >> 16U; + out2 = __SMUSD(__QSUB(0, coeff), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + write_q15x2 (pSrc + (2 * l), (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF)); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + coeff = read_q15x2 ((q15_t *)pCoef + (ia * 2U)); + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + + T = read_q15x2 (pSrc + (2 * i)); + + S = read_q15x2 (pSrc + (2 * l)); + + R = __QSUB16(T, S); + + write_q15x2 (pSrc + (2 * i), __QADD16(T, S)); + + write_q15x2 (pSrc + (2 * l), R); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + +#else /* #if defined (ARM_MATH_DSP) */ + + uint32_t i, j, k, l; + uint32_t n1, n2, ia; + q15_t xt, yt, cosVal, sinVal; + + // N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = ((pSrc[2 * l + 1] >> 1U) + + (pSrc[2 * i + 1] >> 1U) ) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16))); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16))); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + + /* loop for stage */ + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + /* loop for groups */ + for (j = 0; j < n2; j++) + { + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + pSrc[2 * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) - + ((int16_t) (((q31_t) yt * sinVal) >> 16)) ); + + pSrc[2 * l + 1] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) + + ((int16_t) (((q31_t) xt * sinVal) >> 16)) ); + + } /* butterfly loop end */ + + } /* groups loop end */ + + twidCoefModifier = twidCoefModifier << 1U; + } /* stages loop end */ + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[(ia * 2)]; + sinVal = pCoef[(ia * 2) + 1]; + + ia = ia + twidCoefModifier; + + /* loop for butterfly */ + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2 * l] = xt; + + pSrc[2 * l + 1] = yt; + + } /* groups loop end */ + + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c new file mode 100644 index 0000000..996e91d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c @@ -0,0 +1,337 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix2_q31.c + * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the fixed-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the fixed-point CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc) +{ + + if (S->ifftFlag == 1U) + { + arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + else + { + arm_radix2_butterfly_q31(pSrc, S->fftLen, + S->pTwiddle, S->twidCoefModifier); + } + + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); +} + +/** + @} end of ComplexFFT group + */ + +void arm_radix2_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l, m; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + + } // groups loop end + + twidCoefModifier <<= 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + i = j; + m = fftLen / n1; + do + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multAcc_32x32_keep32_R(p0, yt, sinVal); + multSub_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + i += n1; + m--; + } while ( m > 0); // butterfly loop end + + } // groups loop end + + twidCoefModifier <<= 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} + + +void arm_radix2_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint16_t twidCoefModifier) +{ + + unsigned i, j, k, l; + unsigned n1, n2, ia; + q31_t xt, yt, cosVal, sinVal; + q31_t p0, p1; + + //N = fftLen; + n2 = fftLen; + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (i = 0; i < n2; i++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + l = i + n2; + xt = (pSrc[2 * i] >> 1U) - (pSrc[2 * l] >> 1U); + pSrc[2 * i] = ((pSrc[2 * i] >> 1U) + (pSrc[2 * l] >> 1U)) >> 1U; + + yt = (pSrc[2 * i + 1] >> 1U) - (pSrc[2 * l + 1] >> 1U); + pSrc[2 * i + 1] = + ((pSrc[2 * l + 1] >> 1U) + (pSrc[2 * i + 1] >> 1U)) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + + // loop for stage + for (k = fftLen / 2; k > 2; k = k >> 1) + { + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + // loop for groups + for (j = 0; j < n2; j++) + { + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = j; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1U; + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1U; + + mult_32x32_keep32_R(p0, xt, cosVal); + mult_32x32_keep32_R(p1, yt, cosVal); + multSub_32x32_keep32_R(p0, yt, sinVal); + multAcc_32x32_keep32_R(p1, xt, sinVal); + + pSrc[2U * l] = p0; + pSrc[2U * l + 1U] = p1; + } // butterfly loop end + + } // groups loop end + + twidCoefModifier = twidCoefModifier << 1U; + } // stages loop end + + n1 = n2; + n2 = n2 >> 1; + ia = 0; + + cosVal = pCoef[ia * 2]; + sinVal = pCoef[(ia * 2) + 1]; + ia = ia + twidCoefModifier; + + // loop for butterfly + for (i = 0; i < fftLen; i += n1) + { + l = i + n2; + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + i += n1; + l = i + n2; + + xt = pSrc[2 * i] - pSrc[2 * l]; + pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]); + + yt = pSrc[2 * i + 1] - pSrc[2 * l + 1]; + pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]); + + pSrc[2U * l] = xt; + + pSrc[2U * l + 1U] = yt; + + } // butterfly loop end + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c new file mode 100644 index 0000000..1fc5169 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f16.c @@ -0,0 +1,1272 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f16.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +extern void arm_bitreversal_f16( + float16_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier, + float16_t onebyfftLen); + + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef); + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_cfft_radix4by2_f16( + float16_t * pSrc, + uint32_t fftLen, + const float16_t * pCoef) +{ + uint32_t i, l; + uint32_t n2, ia; + float16_t xt, yt, cosVal, sinVal; + float16_t p0, p1,p2,p3,a0,a1; + + n2 = fftLen >> 1; + ia = 0; + for (i = 0; i < n2; i++) + { + cosVal = pCoef[2*ia]; + sinVal = pCoef[2*ia + 1]; + ia++; + + l = i + n2; + + /* Butterfly implementation */ + a0 = (_Float16)pSrc[2 * i] + (_Float16)pSrc[2 * l]; + xt = (_Float16)pSrc[2 * i] - (_Float16)pSrc[2 * l]; + + yt = (_Float16)pSrc[2 * i + 1] - (_Float16)pSrc[2 * l + 1]; + a1 = (_Float16)pSrc[2 * l + 1] + (_Float16)pSrc[2 * i + 1]; + + p0 = (_Float16)xt * (_Float16)cosVal; + p1 = (_Float16)yt * (_Float16)sinVal; + p2 = (_Float16)yt * (_Float16)cosVal; + p3 = (_Float16)xt * (_Float16)sinVal; + + pSrc[2 * i] = a0; + pSrc[2 * i + 1] = a1; + + pSrc[2 * l] = (_Float16)p0 + (_Float16)p1; + pSrc[2 * l + 1] = (_Float16)p2 - (_Float16)p3; + + } + + // first col + arm_radix4_butterfly_f16( pSrc, n2, (float16_t*)pCoef, 2U); + // second col + arm_radix4_butterfly_f16( pSrc + fftLen, n2, (float16_t*)pCoef, 2U); + +} + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f16 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f16( + const arm_cfft_radix4_instance_f16 * S, + float16_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f16(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f16(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/* +* @brief Core function for the floating-point CFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to the twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @return none. +*/ + +void arm_radix4_butterfly_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier) +{ + + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out += (_Float16)p0; + Yb12_out -= (_Float16)p1; + Xc12_out += (_Float16)p2; + Yc12_out -= (_Float16)p3; + Xd12_out += (_Float16)p4; + Yd12_out -= (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = ((_Float16)Xbminusd + (_Float16)Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) + ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) - ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) + (yb - yd) */ + r1 = (_Float16)r2 + (_Float16)t1; + + /* (xa - xc) - (yb - yd) */ + r2 = (_Float16)r2 - (_Float16)t1; + + /* (ya - yc) - (xb - xd) */ + s1 = (_Float16)s2 - (_Float16)t2; + + /* (ya - yc) + (xb - xd) */ + s2 = (_Float16)s2 + (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) + ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) - ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) + ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) - ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + +/* +* @brief Core function for the floating-point CIFFT butterfly process. +* @param[in, out] *pSrc points to the in-place buffer of floating-point data type. +* @param[in] fftLen length of the FFT. +* @param[in] *pCoef points to twiddle coefficient buffer. +* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. +* @param[in] onebyfftLen value of 1/fftLen. +* @return none. +*/ + +void arm_radix4_butterfly_inverse_f16( +float16_t * pSrc, +uint16_t fftLen, +const float16_t * pCoef, +uint16_t twidCoefModifier, +float16_t onebyfftLen) +{ + float16_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_DSP) + + float16_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float16_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float16_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float16_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float16_t *ptr1; + float16_t p0,p1,p2,p3,p4,p5,p6,p7; + float16_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* xb - xd */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* yb - yd */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 =(_Float16) Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + /* (xb - xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + /* (yb - yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + pSrc[(2U * i0)] = (_Float16)Xaplusc + (_Float16)Xbplusd; + pSrc[(2U * i0) + 1U] = (_Float16)Yaplusc + (_Float16)Ybplusd; + + Xb12_out = (_Float16)Xb12C_out * (_Float16)co1; + Yb12_out = (_Float16)Yb12C_out * (_Float16)co1; + Xc12_out = (_Float16)Xc12C_out * (_Float16)co2; + Yc12_out = (_Float16)Yc12C_out * (_Float16)co2; + Xd12_out = (_Float16)Xd12C_out * (_Float16)co3; + Yd12_out = (_Float16)Yd12C_out * (_Float16)co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = (_Float16)Yb12C_out * (_Float16)si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = (_Float16)Xb12C_out * (_Float16)si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = (_Float16)Yc12C_out * (_Float16)si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = (_Float16)Xc12C_out * (_Float16)si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = (_Float16)Yd12C_out * (_Float16)si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = (_Float16)Xd12C_out * (_Float16)si3; + + Xb12_out -= (_Float16)p0; + Yb12_out += (_Float16)p1; + Xc12_out -= (_Float16)p2; + Yc12_out += (_Float16)p3; + Xd12_out -= (_Float16)p4; + Yd12_out += (_Float16)p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = (_Float16)xaIn + (_Float16)xcIn; + + /* xa - xc */ + Xaminusc = (_Float16)xaIn - (_Float16)xcIn; + + /* ya + yc */ + Yaplusc = (_Float16)yaIn + (_Float16)ycIn; + + /* ya - yc */ + Yaminusc = (_Float16)yaIn - (_Float16)ycIn; + + /* xb + xd */ + Xbplusd = (_Float16)xbIn + (_Float16)xdIn; + + /* yb + yd */ + Ybplusd = (_Float16)ybIn + (_Float16)ydIn; + + /* (xb-xd) */ + Xbminusd = (_Float16)xbIn - (_Float16)xdIn; + + /* (yb-yd) */ + Ybminusd = (_Float16)ybIn - (_Float16)ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = ((_Float16)Xaplusc + (_Float16)Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = ((_Float16)Yaplusc + (_Float16)Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = ((_Float16)Xaplusc - (_Float16)Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = ((_Float16)Yaplusc - (_Float16)Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = ((_Float16)Xaminusc - (_Float16)Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = ((_Float16)Yaminusc + (_Float16)Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = ((_Float16)Xaminusc + (_Float16)Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = ((_Float16)Yaminusc - (_Float16)Xbminusd); + + p0 = (_Float16)a0 * (_Float16)onebyfftLen; + p1 = (_Float16)a1 * (_Float16)onebyfftLen; + p2 = (_Float16)a2 * (_Float16)onebyfftLen; + p3 = (_Float16)a3 * (_Float16)onebyfftLen; + p4 = (_Float16)a4 * (_Float16)onebyfftLen; + p5 = (_Float16)a5 * (_Float16)onebyfftLen; + p6 = (_Float16)a6 * (_Float16)onebyfftLen; + p7 = (_Float16)a7 * (_Float16)onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float16_t t1, t2, r1, r2, s1, s2; + + /* Run the below code for Cortex-M0 */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = (_Float16)pSrc[(2U * i0)] + (_Float16)pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = (_Float16)pSrc[(2U * i0)] - (_Float16)pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (_Float16)r1 + (_Float16)t1; + + /* xa + xc -(xb + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (_Float16)s1 + (_Float16)t2; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb - yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = ((_Float16)r1 * (_Float16)co2) - ((_Float16)s1 * (_Float16)si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = ((_Float16)s1 * (_Float16)co2) + ((_Float16)r1 * (_Float16)si2); + + /* (xa - xc) - (yb - yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb - yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb - xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb - xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = ((_Float16)r1 * (_Float16)co1) - ((_Float16)s1 * (_Float16)si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = ((_Float16)s1 * (_Float16)co1) + ((_Float16)r1 * (_Float16)si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = ((_Float16)r2 * (_Float16)co3) - ((_Float16)s2 * (_Float16)si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = ((_Float16)s2 * (_Float16)co3) + ((_Float16)r2 * (_Float16)si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (_Float16)pSrc[2U * i0] + (_Float16)pSrc[2U * i2]; + + /* xa - xc */ + r2 = (_Float16)pSrc[2U * i0] - (_Float16)pSrc[2U * i2]; + + /* ya + yc */ + s1 = (_Float16)pSrc[(2U * i0) + 1U] + (_Float16)pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = (_Float16)pSrc[(2U * i0) + 1U] - (_Float16)pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = (_Float16)pSrc[2U * i1] + (_Float16)pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = ((_Float16)r1 + (_Float16)t1) * (_Float16)onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = (_Float16)r1 - (_Float16)t1; + + /* yb + yd */ + t2 = (_Float16)pSrc[(2U * i1) + 1U] + (_Float16)pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = ((_Float16)s1 + (_Float16)t2) * (_Float16)onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = (_Float16)s1 - (_Float16)t2; + + /* (yb-yd) */ + t1 = (_Float16)pSrc[(2U * i1) + 1U] - (_Float16)pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = (_Float16)pSrc[2U * i1] - (_Float16)pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = (_Float16)r2 - (_Float16)t1; + + /* (xa - xc) + (yb-yd) */ + r2 = (_Float16)r2 + (_Float16)t1; + + /* (ya - yc) + (xb-xd) */ + s1 = (_Float16)s2 + (_Float16)t2; + + /* (ya - yc) - (xb-xd) */ + s2 = (_Float16)s2 - (_Float16)t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (_Float16)r1 * (_Float16)onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (_Float16)s1 * (_Float16)onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (_Float16)r2 * (_Float16)onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (_Float16)s2 * (_Float16)onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_DSP) */ +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c new file mode 100644 index 0000000..9d9d4d5 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c @@ -0,0 +1,1203 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_f32.c + * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + + + + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the floating-point Radix-4 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + */ + +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * ---------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to the twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + return none + */ + +void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + /* Updating input index */ + i0++; + + } + while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 += twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) + (yb - yd) */ + Xb12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yb12C_out = (Yaminusc - Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) - (yb - yd) */ + Xd12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yd12C_out = (Xbminusd + Yaminusc); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out += p0; + Yb12_out -= p1; + Xc12_out += p2; + Yc12_out -= p3; + Xd12_out += p4; + Yd12_out -= p5; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + a0 = (Xaplusc + Xbplusd); + /* ya' = ya + yb + yc + yd */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa+yb-xc-yd) */ + a4 = (Xaminusc + Ybminusd); + /* yb' = (ya-xb-yc+xd) */ + a5 = (Yaminusc - Xbminusd); + /* xd' = (xa-yb-xc+yd)) */ + a6 = (Xaminusc - Ybminusd); + /* yd' = (ya+xb-yc-xd) */ + a7 = (Xbminusd + Yaminusc); + + ptr1[0] = a0; + ptr1[1] = a1; + ptr1[2] = a2; + ptr1[3] = a3; + ptr1[4] = a4; + ptr1[5] = a5; + ptr1[6] = a6; + ptr1[7] = a7; + + /* increment pointer by 8 */ + ptr1 += 8U; + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the fft calculation */ + n2 = fftLen; + n1 = n2; + for (k = fftLen; k > 1U; k >>= 2U) + { + /* Initializations for the fft calculation */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* FFT Calculation */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) + (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2); + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) + (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) + (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + brief Core function for the floating-point CIFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type + param[in] fftLen length of the FFT + param[in] pCoef points to twiddle coefficient buffer + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + param[in] onebyfftLen value of 1/fftLen + return none + */ + +void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen) +{ + float32_t co1, co2, co3, si1, si2, si3; + uint32_t ia1, ia2, ia3; + uint32_t i0, i1, i2, i3; + uint32_t n1, n2, j, k; + +#if defined (ARM_MATH_LOOPUNROLL) + + float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn; + float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc, + Ybminusd; + float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out; + float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out; + float32_t *ptr1; + float32_t p0,p1,p2,p3,p4,p5,p6,p7; + float32_t a0,a1,a2,a3,a4,a5,a6,a7; + + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* xb - xd */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* yb - yd */ + Ybminusd = ybIn - ydIn; + + /* xa' = xa + xb + xc + xd */ + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* (xa + xc) - (xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* index calculation for the coefficients */ + ia3 = ia2 + ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen >> 2U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + xaIn = pSrc[(2U * i0)]; + yaIn = pSrc[(2U * i0) + 1U]; + + xbIn = pSrc[(2U * i1)]; + ybIn = pSrc[(2U * i1) + 1U]; + + xcIn = pSrc[(2U * i2)]; + ycIn = pSrc[(2U * i2) + 1U]; + + xdIn = pSrc[(2U * i3)]; + ydIn = pSrc[(2U * i3) + 1U]; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + /* (xb - xd) */ + Xbminusd = xbIn - xdIn; + /* ya - yc */ + Yaminusc = yaIn - ycIn; + /* (yb - yd) */ + Ybminusd = ybIn - ydIn; + + /* xa + xc */ + Xaplusc = xaIn + xcIn; + /* xb + xd */ + Xbplusd = xbIn + xdIn; + /* ya + yc */ + Yaplusc = yaIn + ycIn; + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xa - xc) - (yb - yd) */ + Xb12C_out = (Xaminusc - Ybminusd); + /* (ya - yc) + (xb - xd) */ + Yb12C_out = (Yaminusc + Xbminusd); + /* xa + xc -(xb + xd) */ + Xc12C_out = (Xaplusc - Xbplusd); + /* (ya + yc) - (yb + yd) */ + Yc12C_out = (Yaplusc - Ybplusd); + /* (xa - xc) + (yb - yd) */ + Xd12C_out = (Xaminusc + Ybminusd); + /* (ya - yc) - (xb - xd) */ + Yd12C_out = (Yaminusc - Xbminusd); + + pSrc[(2U * i0)] = Xaplusc + Xbplusd; + pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd; + + Xb12_out = Xb12C_out * co1; + Yb12_out = Yb12C_out * co1; + Xc12_out = Xc12C_out * co2; + Yc12_out = Yc12C_out * co2; + Xd12_out = Xd12C_out * co3; + Yd12_out = Yd12C_out * co3; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + //Xb12_out -= Yb12C_out * si1; + p0 = Yb12C_out * si1; + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + //Yb12_out += Xb12C_out * si1; + p1 = Xb12C_out * si1; + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + //Xc12_out -= Yc12C_out * si2; + p2 = Yc12C_out * si2; + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + //Yc12_out += Xc12C_out * si2; + p3 = Xc12C_out * si2; + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + //Xd12_out -= Yd12C_out * si3; + p4 = Yd12C_out * si3; + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + //Yd12_out += Xd12C_out * si3; + p5 = Xd12C_out * si3; + + Xb12_out -= p0; + Yb12_out += p1; + Xc12_out -= p2; + Yc12_out += p3; + Xd12_out -= p4; + Yd12_out += p5; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = Xc12_out; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = Yc12_out; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = Xb12_out; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = Yb12_out; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = Xd12_out; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = Yd12_out; + + i0 += n1; + } while (i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + xaIn = ptr1[0]; + yaIn = ptr1[1]; + xbIn = ptr1[2]; + ybIn = ptr1[3]; + xcIn = ptr1[4]; + ycIn = ptr1[5]; + xdIn = ptr1[6]; + ydIn = ptr1[7]; + + /* Butterfly implementation */ + /* xa + xc */ + Xaplusc = xaIn + xcIn; + + /* xa - xc */ + Xaminusc = xaIn - xcIn; + + /* ya + yc */ + Yaplusc = yaIn + ycIn; + + /* ya - yc */ + Yaminusc = yaIn - ycIn; + + /* xb + xd */ + Xbplusd = xbIn + xdIn; + + /* yb + yd */ + Ybplusd = ybIn + ydIn; + + /* (xb-xd) */ + Xbminusd = xbIn - xdIn; + + /* (yb-yd) */ + Ybminusd = ybIn - ydIn; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + a0 = (Xaplusc + Xbplusd); + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + a1 = (Yaplusc + Ybplusd); + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + a2 = (Xaplusc - Xbplusd); + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + a3 = (Yaplusc - Ybplusd); + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + a4 = (Xaminusc - Ybminusd); + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + a5 = (Yaminusc + Xbminusd); + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + a6 = (Xaminusc + Ybminusd); + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + a7 = (Yaminusc - Xbminusd); + + p0 = a0 * onebyfftLen; + p1 = a1 * onebyfftLen; + p2 = a2 * onebyfftLen; + p3 = a3 * onebyfftLen; + p4 = a4 * onebyfftLen; + p5 = a5 * onebyfftLen; + p6 = a6 * onebyfftLen; + p7 = a7 * onebyfftLen; + + /* xa' = (xa+xb+xc+xd) * onebyfftLen */ + ptr1[0] = p0; + /* ya' = (ya+yb+yc+yd) * onebyfftLen */ + ptr1[1] = p1; + /* xc' = (xa-xb+xc-xd) * onebyfftLen */ + ptr1[2] = p2; + /* yc' = (ya-yb+yc-yd) * onebyfftLen */ + ptr1[3] = p3; + /* xb' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[4] = p4; + /* yb' = (ya+xb-yc-xd) * onebyfftLen */ + ptr1[5] = p5; + /* xd' = (xa-yb-xc+yd) * onebyfftLen */ + ptr1[6] = p6; + /* yd' = (ya-xb-yc+xd) * onebyfftLen */ + ptr1[7] = p7; + + /* increment source pointer by 8 for next calculations */ + ptr1 = ptr1 + 8U; + + } while (--j); + +#else + + float32_t t1, t2, r1, r2, s1, s2; + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* Calculation of first stage */ + for (k = fftLen; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + j = 0; + do + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + i0 = j; + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* xa + xc */ + r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)]; + + /* xa - xc */ + r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = r1 + t1; + + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = s1 + t2; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (r1 * co2) - (s1 * si2); + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2); + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (r1 * co1) - (s1 * si1); + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1); + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (r2 * co3) - (s2 * si3); + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3); + + i0 += n1; + } while ( i0 < fftLen); + j++; + } while (j <= (n2 - 1U)); + twidCoefModifier <<= 2U; + } + /* Initializations of last stage */ + n1 = n2; + n2 >>= 2U; + + /* Calculations of last stage */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xc + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) * onebyfftLen; + + /* (xa + xb) - (xc + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb-yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + + /* (xb-xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = r1 * onebyfftLen; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = s1 * onebyfftLen; + + /* (xa - xc) - (yb-yd) */ + r1 = r2 - t1; + + /* (xa - xc) + (yb-yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb-xd) */ + s1 = s2 + t2; + + /* (ya - yc) - (xb-xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = r1 * onebyfftLen; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = s1 * onebyfftLen; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = r2 * onebyfftLen; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = s2 * onebyfftLen; + } + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ +} + + diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c new file mode 100644 index 0000000..cb45cd8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f16.c @@ -0,0 +1,171 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f16.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables.h" +#include "arm_common_tables_f16.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f16 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +#if defined(ARM_FLOAT16_SUPPORTED) + +arm_status arm_cfft_radix4_init_f16( + arm_cfft_radix4_instance_f16 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float16_t *) twiddleCoefF16; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c new file mode 100644 index 0000000..b3aabbb --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_f32.c + * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Initialization function for the floating-point CFFT/CIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialise the FFT length */ + S->fftLen = fftLen; + + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (float32_t *) twiddleCoef; + + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.000244140625; + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + /* Initialise the 1/fftLen Value */ + S->onebyfftLen = 0.0009765625f; + break; + + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + S->onebyfftLen = 0.00390625f; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + S->onebyfftLen = 0.015625f; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + S->onebyfftLen = 0.0625f; + break; + + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } +#endif +#endif +#endif + + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c new file mode 100644 index 0000000..7774243 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c @@ -0,0 +1,157 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q15.c + * Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Initialization function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in,out] S points to an instance of the Q15 CFFT/CIFFT structure + @param[in] fftLen length of the FFT + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q15_t *) twiddleCoef_4096_q15; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLen) + { + case 4096U: + /* Initializations of structure parameters for 4096 point FFT */ + + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + + break; + + case 1024U: + /* Initializations of structure parameters for 1024 point FFT */ + S->twidCoefModifier = 4U; + S->bitRevFactor = 4U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c new file mode 100644 index 0000000..04ba393 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_init_q31.c + * Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + + @brief Initialization function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in,out] S points to an instance of the Q31 CFFT/CIFFT structure. + @param[in] fftLen length of the FFT. + @param[in] ifftFlag flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Details + The parameter ifftFlag controls whether a forward or inverse transform is computed. + Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. +*/ + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag) +{ + + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + /* Initialise the FFT length */ + S->fftLen = fftLen; + /* Initialise the Twiddle coefficient pointer */ + S->pTwiddle = (q31_t *) twiddleCoef_4096_q31; + /* Initialise the Flag for selection of CFFT or CIFFT */ + S->ifftFlag = ifftFlag; + /* Initialise the Flag for calculation Bit reversal or not */ + S->bitReverseFlag = bitReverseFlag; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + + /* Initializations of Instance structure depending on the FFT length */ + switch (S->fftLen) + { + /* Initializations of structure parameters for 4096 point FFT */ + case 4096U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 1U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 1U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) armBitRevTable; + break; + + /* Initializations of structure parameters for 1024 point FFT */ + case 1024U: + /* Initialise the twiddle coef modifier value */ + S->twidCoefModifier = 4U; + /* Initialise the bit reversal table modifier */ + S->bitRevFactor = 4U; + /* Initialise the bit reversal table pointer */ + S->pBitRevTable = (uint16_t *) & armBitRevTable[3]; + break; + + case 256U: + /* Initializations of structure parameters for 256 point FFT */ + S->twidCoefModifier = 16U; + S->bitRevFactor = 16U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[15]; + break; + + case 64U: + /* Initializations of structure parameters for 64 point FFT */ + S->twidCoefModifier = 64U; + S->bitRevFactor = 64U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[63]; + break; + + case 16U: + /* Initializations of structure parameters for 16 point FFT */ + S->twidCoefModifier = 256U; + S->bitRevFactor = 256U; + S->pBitRevTable = (uint16_t *) & armBitRevTable[255]; + break; + + default: + /* Reporting argument error if fftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif +#endif + return (status); +} + +/** + @} end of ComplexFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c new file mode 100644 index 0000000..280acca --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c @@ -0,0 +1,1809 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q15.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier); + +void arm_bitreversal_q15( + q15_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + + +/** + @brief Processing function for the Q15 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q15 and will be removed in the future. + @param[in] S points to an instance of the Q15 CFFT/CIFFT structure. + @param[in,out] pSrc points to the complex data buffer. Processing occurs in-place. + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT" + \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT" + */ + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q15 CFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_radix4_butterfly_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); /* this is just a SIMD arithmetic shift right by 1 */ + T = __SHADD16(T, 0); /* it turns out doing this twice is 2 cycles, the alternative takes 3 cycles */ +/* + in = ((int16_t) (T & 0xFFFF)) >> 2; // alternative code that takes 3 cycles + T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF); +*/ + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUAD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QASX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUAD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUSDX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUSDX(S, C1) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUAD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUSDX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUSDX(R, C3) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUAD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUSDX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUSDX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUAD(C2, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUAD(C1, S) >> 16U; + out2 = __SMUSDX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSDX(S, C1) >> 16U; + out2 = __SMUAD(C1, S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUAD(C3, R) >> 16U; + out2 = __SMUSDX(C3, R); +#else + out1 = __SMUSDX(R, C3) >> 16U; + out2 = __SMUAD(C3, R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + j = n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc) */ + R0 = __SSAT(T0 + S0, 16U); + /* R1 = (xa + xc) */ + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc) */ + S0 = __SSAT(T0 - S0, 16); + /* S1 = (xa - xc) */ + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* input is down scale by 4 to avoid overflow */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1] >> 2U; + + /* T0 = (yb + yd) */ + T0 = __SSAT(T0 + U0, 16U); + /* T1 = (xb + xd) */ + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* ya' = ya + yb + yc + yd */ + /* xa' = xa + xb + xc + xd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd) */ + /* R1 = (xa + xc) - (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1]; + + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2; + T1 = pSrc16[(i1 * 2U) + 1] >> 2; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd */ + U0 = pSrc16[i3 * 2U] >> 2; + U1 = pSrc16[(i3 * 2U) + 1] >> 2; + /* T0 = yb-yd */ + T0 = __SSAT(T0 - U0, 16); + /* T1 = xb-xd */ + T1 = __SSAT(T1 - U1, 16); + + /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */ + R0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */ + S0 = (q15_t) __SSAT(((q31_t) S0 + T1), 16U); + S1 = (q15_t) __SSAT(((q31_t) S1 - T0), 16U); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = (q15_t) ((Si1 * S1 + Co1 * S0) >> 16); + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16); + + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * (ic * 2U)]; + Si2 = pCoef16[(2U * (ic * 2U)) + 1U]; + Co3 = pCoef16[3U * (ic * 2U)]; + Si3 = pCoef16[(3U * (ic * 2U)) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16); + R1 = __SSAT(T1 + S1, 16); + + /* S0 = (ya - yc), S1 =(xa - xc) */ + S0 = __SSAT(T0 - S0, 16); + S1 = __SSAT(T1 - S1, 16); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16); + T1 = __SSAT(T1 + U1, 16); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + out2 = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + pSrc16[i0 * 2U] = out1; + pSrc16[(2U * i0) + 1U] = out2; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 + Si2 * R1) >> 16U); + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((-Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd */ + T0 = __SSAT(T0 - U0, 16); + T1 = __SSAT(T1 - U1, 16); + + /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */ + R0 = (S0 >> 1U) - (T1 >> 1U); + R1 = (S1 >> 1U) + (T0 >> 1U); + + /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */ + S0 = (S0 >> 1U) + (T1 >> 1U); + S1 = (S1 >> 1U) - (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 + Si1 * S1) >> 16U); + + out2 = (q15_t) ((-Si1 * S0 + Co1 * S1) >> 16U); + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Si3 * R1 + Co3 * R0) >> 16U); + + out2 = (q15_t) ((-Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* start of last stage process */ + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd)) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + } + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} + + +/** + @brief Core function for the Q15 CIFFT butterfly process. + @param[in,out] pSrc16 points to the in-place buffer of Q15 data type + @param[in] fftLen length of the FFT + @param[in] pCoef16 points to twiddle coefficient buffer + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q15( + q15_t * pSrc16, + uint32_t fftLen, + const q15_t * pCoef16, + uint32_t twidCoefModifier) +{ + +#if defined (ARM_MATH_DSP) + + q31_t R, S, T, U; + q31_t C1, C2, C3, out1, out2; + uint32_t n1, n2, ic, i0, j, k; + + q15_t *ptr1; + q15_t *pSi0; + q15_t *pSi1; + q15_t *pSi2; + q15_t *pSi3; + + q31_t xaya, xbyb, xcyc, xdyd; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + j = n2; + + pSi0 = pSrc16; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Input is in 1.15(q15) format */ + + /* start of first stage process */ + do + { + /* Butterfly implementation */ + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + S = __SHADD16(S, 0); + S = __SHADD16(S, 0); + + /* R = packed((ya + yc), (xa + xc) ) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc) ) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed((yb + yd), (xb + xd) ) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&pSi0, __SHADD16(R, T)); + + /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */ + R = __QSUB16(R, T); + + /* co2 & si2 are read from SIMD Coefficient pointer */ + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out1 = __SMUSD(C2, R) >> 16U; + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(C2, R) >> 16U; + /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+fftLen/4 */ + /* T = packed(yb, xb) */ + T = read_q15x2 (pSi1); + T = __SHADD16(T, 0); + T = __SHADD16(T, 0); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + write_q15x2_ia (&pSi1, (q31_t) __PKHBT( out1, out2, 0 )); + + /* Butterfly calculations */ + /* U = packed(yd, xd) */ + U = read_q15x2 (pSi3); + U = __SHADD16(U, 0); + U = __SHADD16(U, 0); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QSAX(S, T); + /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */ + S = __QASX(S, T); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __QASX(S, T); + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __QSAX(S, T); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* co1 & si1 are read from SIMD Coefficient pointer */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + /* Butterfly process for the i0+fftLen/2 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out1 = __SMUSD(C1, S) >> 16U; + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out2 = __SMUADX(C1, S); +#else + /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + out1 = __SMUADX(C1, S) >> 16U; + /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xb', yb') in little endian format */ + write_q15x2_ia (&pSi2, __PKHBT( out1, out2, 0 )); + + /* co3 & si3 are read from SIMD Coefficient pointer */ + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out1 = __SMUSD(C3, R) >> 16U; + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out2 = __SMUADX(C3, R); +#else + /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + out1 = __SMUADX(C3, R) >> 16U; + /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* writing output(xd', yd') in little endian format */ + write_q15x2_ia (&pSi3, __PKHBT( out1, out2, 0 )); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + } while (--j); + /* data is in 4.11(q11) format */ + + /* end of first stage process */ + + + /* start of middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + C1 = read_q15x2 ((q15_t *) pCoef16 + (2U * ic)); + C2 = read_q15x2 ((q15_t *) pCoef16 + (4U * ic)); + C3 = read_q15x2 ((q15_t *) pCoef16 + (6U * ic)); + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + pSi0 = pSrc16 + 2 * j; + pSi1 = pSi0 + 2 * n2; + pSi2 = pSi1 + 2 * n2; + pSi3 = pSi2 + 2 * n2; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T = read_q15x2 (pSi0); + + /* Read yc (real), xc(imag) input */ + S = read_q15x2 (pSi2); + + /* R = packed( (ya + yc), (xa + xc)) */ + R = __QADD16(T, S); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(T, S); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed( (yb + yd), (xb + xd)) */ + T = __QADD16(T, U); + + /* writing the butterfly processed i0 sample */ + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + out1 = __SHADD16(R, T); + out1 = __SHADD16(out1, 0); + write_q15x2 (pSi0, out1); + pSi0 += 2 * n1; + + /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */ + R = __SHSUB16(R, T); + +#ifndef ARM_MATH_BIG_ENDIAN + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out1 = __SMUSD(C2, R) >> 16U; + + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out2 = __SMUADX(C2, R); +#else + /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + out1 = __SMUADX(R, C2) >> 16U; + + /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */ + out2 = __SMUSD(__QSUB16(0, C2), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T = read_q15x2 (pSi1); + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */ + write_q15x2 (pSi1, __PKHBT( out1, out2, 0 )); + pSi1 += 2 * n1; + + /* Butterfly calculations */ + + /* Read yd (real), xd(imag) input */ + U = read_q15x2 (pSi3); + + /* T = packed(yb-yd, xb-xd) */ + T = __QSUB16(T, U); + +#ifndef ARM_MATH_BIG_ENDIAN + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHSAX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHASX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUSD(C1, S) >> 16U; + out2 = __SMUADX(C1, S); +#else + /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */ + R = __SHASX(S, T); + + /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */ + S = __SHSAX(S, T); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = __SMUADX(S, C1) >> 16U; + out2 = __SMUSD(__QSUB16(0, C1), S); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */ + /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */ + write_q15x2 (pSi2, __PKHBT( out1, out2, 0 )); + pSi2 += 2 * n1; + + /* Butterfly process for the i0+3fftLen/4 sample */ + +#ifndef ARM_MATH_BIG_ENDIAN + out1 = __SMUSD(C3, R) >> 16U; + out2 = __SMUADX(C3, R); +#else + out1 = __SMUADX(C3, R) >> 16U; + out2 = __SMUSD(__QSUB16(0, C3), R); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */ + /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */ + write_q15x2 (pSi3, __PKHBT( out1, out2, 0 )); + pSi3 += 2 * n1; + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* end of middle stage process */ + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* Initializations for the last stage */ + j = fftLen >> 2; + + ptr1 = &pSrc16[0]; + + /* start of last stage process */ + + /* Butterfly implementation */ + do + { + /* Read xa (real), ya(imag) input */ + xaya = read_q15x2_ia (&ptr1); + + /* Read xb (real), yb(imag) input */ + xbyb = read_q15x2_ia (&ptr1); + + /* Read xc (real), yc(imag) input */ + xcyc = read_q15x2_ia (&ptr1); + + /* Read xd (real), yd(imag) input */ + xdyd = read_q15x2_ia (&ptr1); + + /* R = packed((ya + yc), (xa + xc)) */ + R = __QADD16(xaya, xcyc); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + write_q15x2_ia (&ptr1, __SHADD16(R, T)); + + /* T = packed((yb + yd), (xb + xd)) */ + T = __QADD16(xbyb, xdyd); + + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + write_q15x2_ia (&ptr1, __SHSUB16(R, T)); + + /* S = packed((ya - yc), (xa - xc)) */ + S = __QSUB16(xaya, xcyc); + + /* Read yd (real), xd(imag) input */ + /* T = packed( (yb - yd), (xb - xd)) */ + U = __QSUB16(xbyb, xdyd); + +#ifndef ARM_MATH_BIG_ENDIAN + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); +#else + /* xb' = (xa+yb-xc-yd) */ + /* yb' = (ya-xb-yc+xd) */ + write_q15x2_ia (&ptr1, __SHSAX(S, U)); + + /* xd' = (xa-yb-xc+yd) */ + /* yd' = (ya+xb-yc-xd) */ + write_q15x2_ia (&ptr1, __SHASX(S, U)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + } while (--j); + + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + + +#else /* arm_radix4_butterfly_inverse_q15 */ + + q15_t R0, R1, S0, S1, T0, T1, U0, U1; + q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2; + uint32_t n1, n2, ic, i0, i1, i2, i3, j, k; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + + /* n2 = fftLen/4 */ + n2 >>= 2U; + + /* Index for twiddle coefficient */ + ic = 0U; + + /* Index for input read and output write */ + i0 = 0U; + + j = n2; + + /* Input is in 1.15(q15) format */ + + /* Start of first stage process */ + do + { + /* Butterfly implementation */ + + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U] >> 2U; + T1 = pSrc16[(i0 * 2U) + 1U] >> 2U; + /* input is down scale by 4 to avoid overflow */ + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U] >> 2U; + S1 = pSrc16[(i2 * 2U) + 1U] >> 2U; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* input is down scale by 4 to avoid overflow */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + /* Read yd (real), xd(imag) input */ + /* input is down scale by 4 to avoid overflow */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */ + R0 = __SSAT(R0 - T0, 16U); + R1 = __SSAT(R1 - T1, 16U); + /* co2 & si2 are read from Coefficient pointer */ + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[(2U * ic * 2U) + 1U]; + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16U); + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16U); + + /* Reading i0+fftLen/4 */ + /* input is down scale by 4 to avoid overflow */ + /* T0 = yb, T1 = xb */ + T0 = pSrc16[i1 * 2U] >> 2U; + T1 = pSrc16[(i1 * 2U) + 1U] >> 2U; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* writing output(xc', yc') in little endian format */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* input is down scale by 4 to avoid overflow */ + /* U0 = yd, U1 = xd) */ + U0 = pSrc16[i3 * 2U] >> 2U; + U1 = pSrc16[(i3 * 2U) + 1U] >> 2U; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (q15_t) __SSAT((q31_t) (S0 + T1), 16); + R1 = (q15_t) __SSAT((q31_t) (S1 - T0), 16); + /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (q15_t) __SSAT((q31_t) (S0 - T1), 16); + S1 = (q15_t) __SSAT((q31_t) (S1 + T0), 16); + + /* co1 & si1 are read from Coefficient pointer */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + /* Butterfly process for the i0+fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* writing output(xb', yb') in little endian format */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Co3 & si3 are read from Coefficient pointer */ + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + /* Butterfly process for the i0+3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* writing output(xd', yd') in little endian format */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* End of first stage process */ + + /* data is in 4.11(q11) format */ + + + /* Start of Middle stage process */ + + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + + /* Calculation of Middle stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the middle stage */ + n1 = n2; + n2 >>= 2U; + ic = 0U; + + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + Co1 = pCoef16[ic * 2U]; + Si1 = pCoef16[(ic * 2U) + 1U]; + Co2 = pCoef16[2U * ic * 2U]; + Si2 = pCoef16[2U * ic * 2U + 1U]; + Co3 = pCoef16[3U * ic * 2U]; + Si3 = pCoef16[(3U * ic * 2U) + 1U]; + + /* Twiddle coefficients index modifier */ + ic = ic + twidCoefModifier; + + /* Butterfly implementation */ + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = ((R0 >> 1U) + (T0 >> 1U)) >> 1U; + pSrc16[(i0 * 2U) + 1U] = ((R1 >> 1U) + (T1 >> 1U)) >> 1U; + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */ + out1 = (q15_t) ((Co2 * R0 - Si2 * R1) >> 16); + /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + out2 = (q15_t) ((Si2 * R0 + Co2 * R1) >> 16); + + /* Reading i0+3fftLen/4 */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */ + /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */ + pSrc16[i1 * 2U] = out1; + pSrc16[(i1 * 2U) + 1U] = out2; + + /* Butterfly calculations */ + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = yb-yd, T1 = xb-xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */ + R0 = (S0 >> 1U) + (T1 >> 1U); + R1 = (S1 >> 1U) - (T0 >> 1U); + + /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */ + S0 = (S0 >> 1U) - (T1 >> 1U); + S1 = (S1 >> 1U) + (T0 >> 1U); + + /* Butterfly process for the i0+fftLen/2 sample */ + out1 = (q15_t) ((Co1 * S0 - Si1 * S1) >> 16U); + out2 = (q15_t) ((Si1 * S0 + Co1 * S1) >> 16U); + /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */ + /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */ + pSrc16[i2 * 2U] = out1; + pSrc16[(i2 * 2U) + 1U] = out2; + + /* Butterfly process for the i0+3fftLen/4 sample */ + out1 = (q15_t) ((Co3 * R0 - Si3 * R1) >> 16U); + + out2 = (q15_t) ((Si3 * R0 + Co3 * R1) >> 16U); + /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */ + /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */ + pSrc16[i3 * 2U] = out1; + pSrc16[(i3 * 2U) + 1U] = out2; + + + } + } + /* Twiddle coefficients index modifier */ + twidCoefModifier <<= 2U; + } + /* End of Middle stages process */ + + + /* data is in 10.6(q6) format for the 1024 point */ + /* data is in 8.8(q8) format for the 256 point */ + /* data is in 6.10(q10) format for the 64 point */ + /* data is in 4.12(q12) format for the 16 point */ + + /* start of last stage process */ + + + /* Initializations for the last stage */ + n1 = n2; + n2 >>= 2U; + + /* Butterfly implementation */ + for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Reading i0, i0+fftLen/2 inputs */ + /* Read ya (real), xa(imag) input */ + T0 = pSrc16[i0 * 2U]; + T1 = pSrc16[(i0 * 2U) + 1U]; + /* Read yc (real), xc(imag) input */ + S0 = pSrc16[i2 * 2U]; + S1 = pSrc16[(i2 * 2U) + 1U]; + + /* R0 = (ya + yc), R1 = (xa + xc) */ + R0 = __SSAT(T0 + S0, 16U); + R1 = __SSAT(T1 + S1, 16U); + /* S0 = (ya - yc), S1 = (xa - xc) */ + S0 = __SSAT(T0 - S0, 16U); + S1 = __SSAT(T1 - S1, 16U); + + /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */ + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + + /* T0 = (yb + yd), T1 = (xb + xd) */ + T0 = __SSAT(T0 + U0, 16U); + T1 = __SSAT(T1 + U1, 16U); + + /* writing the butterfly processed i0 sample */ + /* xa' = xa + xb + xc + xd */ + /* ya' = ya + yb + yc + yd */ + pSrc16[i0 * 2U] = (R0 >> 1U) + (T0 >> 1U); + pSrc16[(i0 * 2U) + 1U] = (R1 >> 1U) + (T1 >> 1U); + + /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */ + R0 = (R0 >> 1U) - (T0 >> 1U); + R1 = (R1 >> 1U) - (T1 >> 1U); + + /* Read yb (real), xb(imag) input */ + T0 = pSrc16[i1 * 2U]; + T1 = pSrc16[(i1 * 2U) + 1U]; + + /* writing the butterfly processed i0 + fftLen/4 sample */ + /* xc' = (xa-xb+xc-xd) */ + /* yc' = (ya-yb+yc-yd) */ + pSrc16[i1 * 2U] = R0; + pSrc16[(i1 * 2U) + 1U] = R1; + + /* Read yd (real), xd(imag) input */ + U0 = pSrc16[i3 * 2U]; + U1 = pSrc16[(i3 * 2U) + 1U]; + /* T0 = (yb - yd), T1 = (xb - xd) */ + T0 = __SSAT(T0 - U0, 16U); + T1 = __SSAT(T1 - U1, 16U); + + /* writing the butterfly processed i0 + fftLen/2 sample */ + /* xb' = (xa-yb-xc+yd) */ + /* yb' = (ya+xb-yc-xd) */ + pSrc16[i2 * 2U] = (S0 >> 1U) - (T1 >> 1U); + pSrc16[(i2 * 2U) + 1U] = (S1 >> 1U) + (T0 >> 1U); + + + /* writing the butterfly processed i0 + 3fftLen/4 sample */ + /* xd' = (xa+yb-xc-yd) */ + /* yd' = (ya-xb-yc+xd) */ + pSrc16[i3 * 2U] = (S0 >> 1U) + (T1 >> 1U); + pSrc16[(i3 * 2U) + 1U] = (S1 >> 1U) - (T0 >> 1U); + } + /* end of last stage process */ + + /* output is in 11.5(q5) format for the 1024 point */ + /* output is in 9.7(q7) format for the 256 point */ + /* output is in 7.9(q9) format for the 64 point */ + /* output is in 5.11(q11) format for the 16 point */ + +#endif /* #if defined (ARM_MATH_DSP) */ + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c new file mode 100644 index 0000000..46c1e47 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c @@ -0,0 +1,827 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix4_q31.c + * Description: This file has function definition of Radix-4 FFT & IFFT function and + * In-place bit reversal using bit reversal table + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier); + +void arm_bitreversal_q31( + q31_t * pSrc, + uint32_t fftLen, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup ComplexFFT + @{ + */ + +/** + @brief Processing function for the Q31 CFFT/CIFFT. + @deprecated Do not use this function. It has been superseded by \ref arm_cfft_q31 and will be removed in the future. + @param[in] S points to an instance of the Q31 CFFT/CIFFT structure + @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place + @return none + + @par Input and output formats: + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different FFT sizes. + The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT: + @par + \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT" + \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT" + */ + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc) +{ + if (S->ifftFlag == 1U) + { + /* Complex IFFT radix-4 */ + arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + else + { + /* Complex FFT radix-4 */ + arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier); + } + + if (S->bitReverseFlag == 1U) + { + /* Bit Reversal */ + arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable); + } + +} + +/** + @} end of ComplexFFT group + */ + +/* + * Radix-4 FFT algorithm used is : + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 FFT: + * Wn = co1 + j * (- si1) + * W2n = co2 + j * (- si2) + * W3n = co3 + j * (- si3) + * + * Butterfly implementation: + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) + * yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) + * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) + * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) + * + */ + +/** + @brief Core function for the Q31 CFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +void arm_radix4_butterfly_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* Total process is divided into three stages */ + + /* process first stage, middle stages, & last stage */ + + + /* start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + /* Calculation of first stage */ + do + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[(2U * i0)] >> 4U) + (pSrc[(2U * i2)] >> 4U); + /* xa - xc */ + r2 = (pSrc[(2U * i0)] >> 4U) - (pSrc[(2U * i2)] >> 4U); + + /* xb + xd */ + t1 = (pSrc[(2U * i1)] >> 4U) + (pSrc[(2U * i3)] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[(2U * i1)] >> 4U) - (pSrc[(2U * i3)] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* end of first stage process */ + + /* data is in 5.27(q27) format */ + + + /* start of Middle stages process */ + + + /* each stage in middle stages provides two down scaling of the input */ + + twidCoefModifier <<= 2U; + + + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + /* Calculation of first stage */ + for (j = 0U; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) + + ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) - + ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1U; + + /* (xa - xc) + (yb - yd) */ + r1 = r2 + t1; + /* (xa - xc) - (yb - yd) */ + r2 = r2 - t1; + + /* (ya - yc) - (xb - xd) */ + s1 = s2 - t2; + /* (ya - yc) + (xb - xd) */ + s2 = s2 + t2; + + /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) + + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) - + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) + + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) - + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* start of Last stage process */ + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa + yb - xc - yd); + yb_out = (ya - xb - yc + xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa - yb - xc + yd); + yd_out = (ya + xb - yc - xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ + +} + + +/** + @brief Core function for the Q31 CIFFT butterfly process. + @param[in,out] pSrc points to the in-place buffer of Q31 data type. + @param[in] fftLen length of the FFT. + @param[in] pCoef points to twiddle coefficient buffer. + @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + @return none + */ + +/* + * Radix-4 IFFT algorithm used is : + * + * CIFFT uses same twiddle coefficients as CFFT Function + * x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4] + * + * + * IFFT is implemented with following changes in equations from FFT + * + * Input real and imaginary data: + * x(n) = xa + j * ya + * x(n+N/4 ) = xb + j * yb + * x(n+N/2 ) = xc + j * yc + * x(n+3N 4) = xd + j * yd + * + * + * Output real and imaginary data: + * x(4r) = xa'+ j * ya' + * x(4r+1) = xb'+ j * yb' + * x(4r+2) = xc'+ j * yc' + * x(4r+3) = xd'+ j * yd' + * + * + * Twiddle factors for radix-4 IFFT: + * Wn = co1 + j * (si1) + * W2n = co2 + j * (si2) + * W3n = co3 + j * (si3) + + * The real and imaginary output values for the radix-4 butterfly are + * xa' = xa + xb + xc + xd + * ya' = ya + yb + yc + yd + * xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) + * yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) + * xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) + * yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) + * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) + * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) + * + */ + +void arm_radix4_butterfly_inverse_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pCoef, + uint32_t twidCoefModifier) +{ + uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k; + q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3; + q31_t xa, xb, xc, xd; + q31_t ya, yb, yc, yd; + q31_t xa_out, xb_out, xc_out, xd_out; + q31_t ya_out, yb_out, yc_out, yd_out; + + q31_t *ptr1; + + /* input is be 1.31(q31) format for all FFT sizes */ + /* Total process is divided into three stages */ + /* process first stage, middle stages, & last stage */ + + /* Start of first stage process */ + + /* Initializations for the first stage */ + n2 = fftLen; + n1 = n2; + /* n2 = fftLen/4 */ + n2 >>= 2U; + i0 = 0U; + ia1 = 0U; + + j = n2; + + do + { + /* input is in 1.31(q31) format and provide 4 guard bits for the input */ + + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = (pSrc[2U * i0] >> 4U) + (pSrc[2U * i2] >> 4U); + /* xa - xc */ + r2 = (pSrc[2U * i0] >> 4U) - (pSrc[2U * i2] >> 4U); + + /* xb + xd */ + t1 = (pSrc[2U * i1] >> 4U) + (pSrc[2U * i3] >> 4U); + + /* ya + yc */ + s1 = (pSrc[(2U * i0) + 1U] >> 4U) + (pSrc[(2U * i2) + 1U] >> 4U); + /* ya - yc */ + s2 = (pSrc[(2U * i0) + 1U] >> 4U) - (pSrc[(2U * i2) + 1U] >> 4U); + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1); + /* (xa + xc) - (xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = (pSrc[(2U * i1) + 1U] >> 4U) + (pSrc[(2U * i3) + 1U] >> 4U); + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2); + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* yb - yd */ + t1 = (pSrc[(2U * i1) + 1U] >> 4U) - (pSrc[(2U * i3) + 1U] >> 4U); + /* xb - xd */ + t2 = (pSrc[2U * i1] >> 4U) - (pSrc[2U * i3] >> 4U); + + /* index calculation for the coefficients */ + ia2 = 2U * ia1; + co2 = pCoef[ia2 * 2U]; + si2 = pCoef[(ia2 * 2U) + 1U]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) - + ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[2U * i1 + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32)) + + ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + co1 = pCoef[ia1 * 2U]; + si1 = pCoef[(ia1 * 2U) + 1U]; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1U; + + /* index calculation for the coefficients */ + ia3 = 3U * ia1; + co3 = pCoef[ia3 * 2U]; + si3 = pCoef[(ia3 * 2U) + 1U]; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[2U * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1U; + + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + /* Updating input index */ + i0 = i0 + 1U; + + } while (--j); + + /* data is in 5.27(q27) format */ + /* each stage provides two down scaling of the input */ + + + /* Start of Middle stages process */ + + twidCoefModifier <<= 2U; + + /* Calculation of second stage to excluding last stage */ + for (k = fftLen / 4U; k > 4U; k >>= 2U) + { + /* Initializations for the first stage */ + n1 = n2; + n2 >>= 2U; + ia1 = 0U; + + for (j = 0; j <= (n2 - 1U); j++) + { + /* index calculation for the coefficients */ + ia2 = ia1 + ia1; + ia3 = ia2 + ia1; + co1 = pCoef[(ia1 * 2U)]; + si1 = pCoef[(ia1 * 2U) + 1U]; + co2 = pCoef[(ia2 * 2U)]; + si2 = pCoef[(ia2 * 2U) + 1U]; + co3 = pCoef[(ia3 * 2U)]; + si3 = pCoef[(ia3 * 2U) + 1U]; + /* Twiddle coefficients index modifier */ + ia1 = ia1 + twidCoefModifier; + + for (i0 = j; i0 < fftLen; i0 += n1) + { + /* index calculation for the input as, */ + /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2U], pSrc[i0 + 3fftLen/4] */ + i1 = i0 + n2; + i2 = i1 + n2; + i3 = i2 + n2; + + /* Butterfly implementation */ + /* xa + xc */ + r1 = pSrc[2U * i0] + pSrc[2U * i2]; + /* xa - xc */ + r2 = pSrc[2U * i0] - pSrc[2U * i2]; + + /* ya + yc */ + s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U]; + /* ya - yc */ + s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U]; + + /* xb + xd */ + t1 = pSrc[2U * i1] + pSrc[2U * i3]; + + /* xa' = xa + xb + xc + xd */ + pSrc[2U * i0] = (r1 + t1) >> 2U; + /* xa + xc -(xb + xd) */ + r1 = r1 - t1; + /* yb + yd */ + t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U]; + /* ya' = ya + yb + yc + yd */ + pSrc[(2U * i0) + 1U] = (s1 + t2) >> 2U; + + /* (ya + yc) - (yb + yd) */ + s1 = s1 - t2; + + /* (yb - yd) */ + t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U]; + /* (xb - xd) */ + t2 = pSrc[2U * i1] - pSrc[2U * i3]; + + /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */ + pSrc[2U * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32U)) - + ((int32_t) (((q63_t) s1 * si2) >> 32U))) >> 1U; + + /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */ + pSrc[(2U * i1) + 1U] = (((int32_t) (((q63_t) s1 * co2) >> 32U)) + + ((int32_t) (((q63_t) r1 * si2) >> 32U))) >> 1U; + + /* (xa - xc) - (yb - yd) */ + r1 = r2 - t1; + /* (xa - xc) + (yb - yd) */ + r2 = r2 + t1; + + /* (ya - yc) + (xb - xd) */ + s1 = s2 + t2; + /* (ya - yc) - (xb - xd) */ + s2 = s2 - t2; + + /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */ + pSrc[2U * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) - + ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1U; + + /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */ + pSrc[(2U * i2) + 1U] = (((int32_t) (((q63_t) s1 * co1) >> 32)) + + ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1U; + + /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */ + pSrc[(2U * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) - + ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1U; + + /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */ + pSrc[(2U * i3) + 1U] = (((int32_t) (((q63_t) s2 * co3) >> 32)) + + ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1U; + } + } + twidCoefModifier <<= 2U; + } + + /* End of Middle stages process */ + + /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */ + /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */ + /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */ + /* data is in 5.27(q27) format for the 16 point as there are no middle stages */ + + + /* Start of last stage process */ + + + /* Initializations for the last stage */ + j = fftLen >> 2; + ptr1 = &pSrc[0]; + + /* Calculations of last stage */ + do + { + /* Read xa (real), ya(imag) input */ + xa = *ptr1++; + ya = *ptr1++; + + /* Read xb (real), yb(imag) input */ + xb = *ptr1++; + yb = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xc = *ptr1++; + yc = *ptr1++; + + /* Read xc (real), yc(imag) input */ + xd = *ptr1++; + yd = *ptr1++; + + /* xa' = xa + xb + xc + xd */ + xa_out = xa + xb + xc + xd; + + /* ya' = ya + yb + yc + yd */ + ya_out = ya + yb + yc + yd; + + /* pointer updation for writing */ + ptr1 = ptr1 - 8U; + + /* writing xa' and ya' */ + *ptr1++ = xa_out; + *ptr1++ = ya_out; + + xc_out = (xa - xb + xc - xd); + yc_out = (ya - yb + yc - yd); + + /* writing xc' and yc' */ + *ptr1++ = xc_out; + *ptr1++ = yc_out; + + xb_out = (xa - yb - xc + yd); + yb_out = (ya + xb - yc - xd); + + /* writing xb' and yb' */ + *ptr1++ = xb_out; + *ptr1++ = yb_out; + + xd_out = (xa + yb - xc - yd); + yd_out = (ya - xb - yc + xd); + + /* writing xd' and yd' */ + *ptr1++ = xd_out; + *ptr1++ = yd_out; + + } while (--j); + + /* output is in 11.21(q21) format for the 1024 point */ + /* output is in 9.23(q23) format for the 256 point */ + /* output is in 7.25(q25) format for the 64 point */ + /* output is in 5.27(q27) format for the 16 point */ + + /* End of last stage process */ +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c new file mode 100644 index 0000000..b7eb37a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f16.c @@ -0,0 +1,289 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f16.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f16( + float16_t * pSrc, + uint16_t fftLen, + const float16_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float16_t r1, r2, r3, r4, r5, r6, r7, r8; + float16_t t1, t2; + float16_t s1, s2, s3, s4, s5, s6, s7, s8; + float16_t p1, p2, p3, p4; + float16_t co2, co3, co4, co5, co6, co7, co8; + float16_t si2, si3, si4, si5, si6, si7, si8; + const float16_t C81 = 0.70710678118f16; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5] = (_Float16)r1 - (_Float16)r2; + r1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + r2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + r4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)r1 - (_Float16)s3; + r1 = (_Float16)r1 + (_Float16)s3; + s3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1 + 1] = (_Float16)r1 + (_Float16)r2; + pSrc[2 * i5 + 1] = (_Float16)r1 - (_Float16)r2; + pSrc[2 * i3] = (_Float16)t1 + (_Float16)s3; + pSrc[2 * i7] = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i3 + 1] = (_Float16)t2 - (_Float16)r3; + pSrc[2 * i7 + 1] = (_Float16)t2 + (_Float16)r3; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + r2 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)r2; + s5 = (_Float16)s5 + (_Float16)r2; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + pSrc[2 * i2] = (_Float16)r5 + (_Float16)s7; + pSrc[2 * i8] = (_Float16)r5 - (_Float16)s7; + pSrc[2 * i6] = (_Float16)t1 + (_Float16)s8; + pSrc[2 * i4] = (_Float16)t1 - (_Float16)s8; + pSrc[2 * i2 + 1] = (_Float16)s5 - (_Float16)r7; + pSrc[2 * i8 + 1] = (_Float16)s5 + (_Float16)r7; + pSrc[2 * i6 + 1] = (_Float16)t2 - (_Float16)r8; + pSrc[2 * i4 + 1] = (_Float16)t2 + (_Float16)r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = (_Float16)pSrc[2 * i1] + (_Float16)pSrc[2 * i5]; + r5 = (_Float16)pSrc[2 * i1] - (_Float16)pSrc[2 * i5]; + r2 = (_Float16)pSrc[2 * i2] + (_Float16)pSrc[2 * i6]; + r6 = (_Float16)pSrc[2 * i2] - (_Float16)pSrc[2 * i6]; + r3 = (_Float16)pSrc[2 * i3] + (_Float16)pSrc[2 * i7]; + r7 = (_Float16)pSrc[2 * i3] - (_Float16)pSrc[2 * i7]; + r4 = (_Float16)pSrc[2 * i4] + (_Float16)pSrc[2 * i8]; + r8 = (_Float16)pSrc[2 * i4] - (_Float16)pSrc[2 * i8]; + t1 = (_Float16)r1 - (_Float16)r3; + r1 = (_Float16)r1 + (_Float16)r3; + r3 = (_Float16)r2 - (_Float16)r4; + r2 = (_Float16)r2 + (_Float16)r4; + pSrc[2 * i1] = (_Float16)r1 + (_Float16)r2; + r2 = (_Float16)r1 - (_Float16)r2; + s1 = (_Float16)pSrc[2 * i1 + 1] + (_Float16)pSrc[2 * i5 + 1]; + s5 = (_Float16)pSrc[2 * i1 + 1] - (_Float16)pSrc[2 * i5 + 1]; + s2 = (_Float16)pSrc[2 * i2 + 1] + (_Float16)pSrc[2 * i6 + 1]; + s6 = (_Float16)pSrc[2 * i2 + 1] - (_Float16)pSrc[2 * i6 + 1]; + s3 = (_Float16)pSrc[2 * i3 + 1] + (_Float16)pSrc[2 * i7 + 1]; + s7 = (_Float16)pSrc[2 * i3 + 1] - (_Float16)pSrc[2 * i7 + 1]; + s4 = (_Float16)pSrc[2 * i4 + 1] + (_Float16)pSrc[2 * i8 + 1]; + s8 = (_Float16)pSrc[2 * i4 + 1] - (_Float16)pSrc[2 * i8 + 1]; + t2 = (_Float16)s1 - (_Float16)s3; + s1 = (_Float16)s1 + (_Float16)s3; + s3 = (_Float16)s2 - (_Float16)s4; + s2 = (_Float16)s2 + (_Float16)s4; + r1 = (_Float16)t1 + (_Float16)s3; + t1 = (_Float16)t1 - (_Float16)s3; + pSrc[2 * i1 + 1] = (_Float16)s1 + (_Float16)s2; + s2 = (_Float16)s1 - (_Float16)s2; + s1 = (_Float16)t2 - (_Float16)r3; + t2 = (_Float16)t2 + (_Float16)r3; + p1 = (_Float16)co5 * (_Float16)r2; + p2 = (_Float16)si5 * (_Float16)s2; + p3 = (_Float16)co5 * (_Float16)s2; + p4 = (_Float16)si5 * (_Float16)r2; + pSrc[2 * i5] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i5 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co3 * (_Float16)r1; + p2 = (_Float16)si3 * (_Float16)s1; + p3 = (_Float16)co3 * (_Float16)s1; + p4 = (_Float16)si3 * (_Float16)r1; + pSrc[2 * i3] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i3 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co7 * (_Float16)t1; + p2 = (_Float16)si7 * (_Float16)t2; + p3 = (_Float16)co7 * (_Float16)t2; + p4 = (_Float16)si7 * (_Float16)t1; + pSrc[2 * i7] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i7 + 1] = (_Float16)p3 - (_Float16)p4; + r1 = ((_Float16)r6 - (_Float16)r8) * (_Float16)C81; + r6 = ((_Float16)r6 + (_Float16)r8) * (_Float16)C81; + s1 = ((_Float16)s6 - (_Float16)s8) * (_Float16)C81; + s6 = ((_Float16)s6 + (_Float16)s8) * (_Float16)C81; + t1 = (_Float16)r5 - (_Float16)r1; + r5 = (_Float16)r5 + (_Float16)r1; + r8 = (_Float16)r7 - (_Float16)r6; + r7 = (_Float16)r7 + (_Float16)r6; + t2 = (_Float16)s5 - (_Float16)s1; + s5 = (_Float16)s5 + (_Float16)s1; + s8 = (_Float16)s7 - (_Float16)s6; + s7 = (_Float16)s7 + (_Float16)s6; + r1 = (_Float16)r5 + (_Float16)s7; + r5 = (_Float16)r5 - (_Float16)s7; + r6 = (_Float16)t1 + (_Float16)s8; + t1 = (_Float16)t1 - (_Float16)s8; + s1 = (_Float16)s5 - (_Float16)r7; + s5 = (_Float16)s5 + (_Float16)r7; + s6 = (_Float16)t2 - (_Float16)r8; + t2 = (_Float16)t2 + (_Float16)r8; + p1 = (_Float16)co2 * (_Float16)r1; + p2 = (_Float16)si2 * (_Float16)s1; + p3 = (_Float16)co2 * (_Float16)s1; + p4 = (_Float16)si2 * (_Float16)r1; + pSrc[2 * i2] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i2 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co8 * (_Float16)r5; + p2 = (_Float16)si8 * (_Float16)s5; + p3 = (_Float16)co8 * (_Float16)s5; + p4 = (_Float16)si8 * (_Float16)r5; + pSrc[2 * i8] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i8 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co6 * (_Float16)r6; + p2 = (_Float16)si6 * (_Float16)s6; + p3 = (_Float16)co6 * (_Float16)s6; + p4 = (_Float16)si6 * (_Float16)r6; + pSrc[2 * i6] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i6 + 1] = (_Float16)p3 - (_Float16)p4; + p1 = (_Float16)co4 * (_Float16)t1; + p2 = (_Float16)si4 * (_Float16)t2; + p3 = (_Float16)co4 * (_Float16)t2; + p4 = (_Float16)si4 * (_Float16)t1; + pSrc[2 * i4] = (_Float16)p1 + (_Float16)p2; + pSrc[2 * i4 + 1] = (_Float16)p3 - (_Float16)p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c new file mode 100644 index 0000000..7990d47 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c @@ -0,0 +1,285 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_cfft_radix8_f32.c + * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + + +/* ---------------------------------------------------------------------- + * Internal helper function used by the FFTs + * -------------------------------------------------------------------- */ + +/** + brief Core function for the floating-point CFFT butterfly process. + param[in,out] pSrc points to the in-place buffer of floating-point data type. + param[in] fftLen length of the FFT. + param[in] pCoef points to the twiddle coefficient buffer. + param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. + return none +*/ + +void arm_radix8_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier) +{ + uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7; + uint32_t i1, i2, i3, i4, i5, i6, i7, i8; + uint32_t id; + uint32_t n1, n2, j; + + float32_t r1, r2, r3, r4, r5, r6, r7, r8; + float32_t t1, t2; + float32_t s1, s2, s3, s4, s5, s6, s7, s8; + float32_t p1, p2, p3, p4; + float32_t co2, co3, co4, co5, co6, co7, co8; + float32_t si2, si3, si4, si5, si6, si7, si8; + const float32_t C81 = 0.70710678118f; + + n2 = fftLen; + + do + { + n1 = n2; + n2 = n2 >> 3; + i1 = 0; + + do + { + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + pSrc[2 * i5] = r1 - r2; + r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = r1 - s3; + r1 = r1 + s3; + s3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1 + 1] = r1 + r2; + pSrc[2 * i5 + 1] = r1 - r2; + pSrc[2 * i3] = t1 + s3; + pSrc[2 * i7] = t1 - s3; + pSrc[2 * i3 + 1] = t2 - r3; + pSrc[2 * i7 + 1] = t2 + r3; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + r2 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - r2; + s5 = s5 + r2; + s8 = s7 - s6; + s7 = s7 + s6; + pSrc[2 * i2] = r5 + s7; + pSrc[2 * i8] = r5 - s7; + pSrc[2 * i6] = t1 + s8; + pSrc[2 * i4] = t1 - s8; + pSrc[2 * i2 + 1] = s5 - r7; + pSrc[2 * i8 + 1] = s5 + r7; + pSrc[2 * i6 + 1] = t2 - r8; + pSrc[2 * i4 + 1] = t2 + r8; + + i1 += n1; + } while (i1 < fftLen); + + if (n2 < 8) + break; + + ia1 = 0; + j = 1; + + do + { + /* index calculation for the coefficients */ + id = ia1 + twidCoefModifier; + ia1 = id; + ia2 = ia1 + id; + ia3 = ia2 + id; + ia4 = ia3 + id; + ia5 = ia4 + id; + ia6 = ia5 + id; + ia7 = ia6 + id; + + co2 = pCoef[2 * ia1]; + co3 = pCoef[2 * ia2]; + co4 = pCoef[2 * ia3]; + co5 = pCoef[2 * ia4]; + co6 = pCoef[2 * ia5]; + co7 = pCoef[2 * ia6]; + co8 = pCoef[2 * ia7]; + si2 = pCoef[2 * ia1 + 1]; + si3 = pCoef[2 * ia2 + 1]; + si4 = pCoef[2 * ia3 + 1]; + si5 = pCoef[2 * ia4 + 1]; + si6 = pCoef[2 * ia5 + 1]; + si7 = pCoef[2 * ia6 + 1]; + si8 = pCoef[2 * ia7 + 1]; + + i1 = j; + + do + { + /* index calculation for the input */ + i2 = i1 + n2; + i3 = i2 + n2; + i4 = i3 + n2; + i5 = i4 + n2; + i6 = i5 + n2; + i7 = i6 + n2; + i8 = i7 + n2; + r1 = pSrc[2 * i1] + pSrc[2 * i5]; + r5 = pSrc[2 * i1] - pSrc[2 * i5]; + r2 = pSrc[2 * i2] + pSrc[2 * i6]; + r6 = pSrc[2 * i2] - pSrc[2 * i6]; + r3 = pSrc[2 * i3] + pSrc[2 * i7]; + r7 = pSrc[2 * i3] - pSrc[2 * i7]; + r4 = pSrc[2 * i4] + pSrc[2 * i8]; + r8 = pSrc[2 * i4] - pSrc[2 * i8]; + t1 = r1 - r3; + r1 = r1 + r3; + r3 = r2 - r4; + r2 = r2 + r4; + pSrc[2 * i1] = r1 + r2; + r2 = r1 - r2; + s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1]; + s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1]; + s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1]; + s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1]; + s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1]; + s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1]; + s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1]; + s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1]; + t2 = s1 - s3; + s1 = s1 + s3; + s3 = s2 - s4; + s2 = s2 + s4; + r1 = t1 + s3; + t1 = t1 - s3; + pSrc[2 * i1 + 1] = s1 + s2; + s2 = s1 - s2; + s1 = t2 - r3; + t2 = t2 + r3; + p1 = co5 * r2; + p2 = si5 * s2; + p3 = co5 * s2; + p4 = si5 * r2; + pSrc[2 * i5] = p1 + p2; + pSrc[2 * i5 + 1] = p3 - p4; + p1 = co3 * r1; + p2 = si3 * s1; + p3 = co3 * s1; + p4 = si3 * r1; + pSrc[2 * i3] = p1 + p2; + pSrc[2 * i3 + 1] = p3 - p4; + p1 = co7 * t1; + p2 = si7 * t2; + p3 = co7 * t2; + p4 = si7 * t1; + pSrc[2 * i7] = p1 + p2; + pSrc[2 * i7 + 1] = p3 - p4; + r1 = (r6 - r8) * C81; + r6 = (r6 + r8) * C81; + s1 = (s6 - s8) * C81; + s6 = (s6 + s8) * C81; + t1 = r5 - r1; + r5 = r5 + r1; + r8 = r7 - r6; + r7 = r7 + r6; + t2 = s5 - s1; + s5 = s5 + s1; + s8 = s7 - s6; + s7 = s7 + s6; + r1 = r5 + s7; + r5 = r5 - s7; + r6 = t1 + s8; + t1 = t1 - s8; + s1 = s5 - r7; + s5 = s5 + r7; + s6 = t2 - r8; + t2 = t2 + r8; + p1 = co2 * r1; + p2 = si2 * s1; + p3 = co2 * s1; + p4 = si2 * r1; + pSrc[2 * i2] = p1 + p2; + pSrc[2 * i2 + 1] = p3 - p4; + p1 = co8 * r5; + p2 = si8 * s5; + p3 = co8 * s5; + p4 = si8 * r5; + pSrc[2 * i8] = p1 + p2; + pSrc[2 * i8 + 1] = p3 - p4; + p1 = co6 * r6; + p2 = si6 * s6; + p3 = co6 * s6; + p4 = si6 * r6; + pSrc[2 * i6] = p1 + p2; + pSrc[2 * i6 + 1] = p3 - p4; + p1 = co4 * t1; + p2 = si4 * t2; + p3 = co4 * t2; + p4 = si4 * t1; + pSrc[2 * i4] = p1 + p2; + pSrc[2 * i4 + 1] = p3 - p4; + + i1 += n1; + } while (i1 < fftLen); + + j++; + } while (j < n2); + + twidCoefModifier <<= 3; + } while (n2 > 7); +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c new file mode 100644 index 0000000..b9dff3f --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c @@ -0,0 +1,448 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_f32.c + * Description: Processing function of DCT4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @ingroup groupTransforms + */ + +/** + @defgroup DCT4_IDCT4 DCT Type IV Functions + + Representation of signals by minimum number of values is important for storage and transmission. + The possibility of large discontinuity between the beginning and end of a period of a signal + in DFT can be avoided by extending the signal so that it is even-symmetric. + Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the + spectrum and is very widely used in signal and image coding applications. + The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions. + DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular. + + DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal. + Reordering of the input data makes the computation of DCT just a problem of + computing the DFT of a real signal with a few additional operations. + This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations. + + DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used. + DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing. + DCT2 implementation can be described in the following steps: + - Re-ordering input + - Calculating Real FFT + - Multiplication of weights and Real FFT output and getting real part from the product. + + This process is explained by the block diagram below: + \image html DCT4.gif "Discrete Cosine Transform - type-IV" + + @par Algorithm + The N-point type-IV DCT is defined as a real, linear transformation by the formula: + \image html DCT4Equation.gif + where k = 0, 1, 2, ..., N-1 + @par + Its inverse is defined as follows: + \image html IDCT4Equation.gif + where n = 0, 1, 2, ..., N-1 + @par + The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N). + The symmetry of the transform matrix indicates that the fast algorithms for the forward + and inverse transform computation are identical. + Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both. + + @par Lengths supported by the transform: + As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192. + The library provides separate functions for Q15, Q31, and floating-point data types. + + @par Instance Structure + The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure. + A separate instance structure must be defined for each transform. + There are separate instance structure declarations for each of the 3 supported data types. + + @par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref arm_rfft_init_f32(). + @par + Use of the initialization function is optional. + However, if the initialization function is used, then the instance structure cannot be placed into a const data section. + To place an instance structure into a const data section, the instance structure must be manually initialized. + Manually initialize the instance structure as follows: + 
+      arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+      arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4; + \c normalize is normalizing factor used and is equal to sqrt(2/N); + \c pTwiddle points to the twiddle factor table; + \c pCosFactor points to the cosFactor table; + \c pRfft points to the real FFT instance; + \c pCfft points to the complex FFT instance; + The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32() + and arm_rfft_f32() respectively for details regarding static initialization. + + @par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the DCT4 transform functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure + @param[in] pState points to state buffer + @param[in,out] pInlineBuffer points to the in-place input and output buffer + @return none + */ + +void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer) +{ + const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + float32_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N); + arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement the loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_f32 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ * (float32_t) 0.5; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = in * S->normalize; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c new file mode 100644 index 0000000..e1d80c0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_f32.c + * Description: Initialization function of DCT-4 & IDCT4 F32 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Floating-point normalizing factors are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingF32Table.gif + */ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = Weights_8192; + S->pCosFactor = cos_factors_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + case 2048U: + S->pTwiddle = Weights_2048; + S->pCosFactor = cos_factors_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + case 512U: + S->pTwiddle = Weights_512; + S->pCosFactor = cos_factors_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + case 128U: + S->pTwiddle = Weights_128; + S->pCosFactor = cos_factors_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c new file mode 100644 index 0000000..5390da3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q15.c + * Description: Initialization function of DCT-4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure + @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure + @param[in] N length of the DCT4 + @param[in] Nby2 half of the length of the DCT4 + @param[in] normalize normalizing factor + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ15Table.gif + */ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ15_8192; + S->pCosFactor = cos_factorsQ15_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + case 2048U: + S->pTwiddle = WeightsQ15_2048; + S->pCosFactor = cos_factorsQ15_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + case 512U: + S->pTwiddle = WeightsQ15_512; + S->pCosFactor = cos_factorsQ15_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + case 128U: + S->pTwiddle = WeightsQ15_128; + S->pCosFactor = cos_factorsQ15_128; + break; + #endif + + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT */ + arm_rfft_init_q15(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c new file mode 100644 index 0000000..4c7622a --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_init_q31.c + * Description: Initialization function of DCT-4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + + /** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length + + @par Normalizing factor: + The normalizing factor is sqrt(2/N), which depends on the size of transform N. + Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes: + + \image html dct4NormalizingQ31Table.gif + */ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize) +{ + /* Initialize the default arm status */ + arm_status status = ARM_MATH_SUCCESS; + + /* Initialize the DCT4 length */ + S->N = N; + + /* Initialize the half of DCT4 length */ + S->Nby2 = Nby2; + + /* Initialize the DCT4 Normalizing factor */ + S->normalize = normalize; + + /* Initialize Real FFT Instance */ + S->pRfft = S_RFFT; + + /* Initialize Complex FFT Instance */ + S->pCfft = S_CFFT; + + switch (N) + { + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + /* Initialize the table modifier values */ + case 8192U: + S->pTwiddle = WeightsQ31_8192; + S->pCosFactor = cos_factorsQ31_8192; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + case 2048U: + S->pTwiddle = WeightsQ31_2048; + S->pCosFactor = cos_factorsQ31_2048; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + case 512U: + S->pTwiddle = WeightsQ31_512; + S->pCosFactor = cos_factorsQ31_512; + break; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + case 128U: + S->pTwiddle = WeightsQ31_128; + S->pCosFactor = cos_factorsQ31_128; + break; + #endif + default: + status = ARM_MATH_ARGUMENT_ERROR; + } + + /* Initialize the RFFT/RIFFT Function */ + arm_rfft_init_q31(S->pRfft, S->N, 0U, 1U); + + /* return the status of DCT4 Init function */ + return (status); +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c new file mode 100644 index 0000000..a4650da --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c @@ -0,0 +1,381 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q15.c + * Description: Processing function of DCT4 & IDCT4 Q15 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] S points to an instance of the Q15 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. The input and output + formats for different DCT sizes and number of bits to upscale are mentioned in the table below: + + \image html dct4FormatsQ15Table.gif + */ + +void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer) +{ + const q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q15 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q15 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q15 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q15 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.13 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */ + arm_shift_q15 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15)); + + /* Decrement loop counter */ + i--; + + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c new file mode 100644 index 0000000..6cbccff --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c @@ -0,0 +1,383 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_dct4_q31.c + * Description: Processing function of DCT4 & IDCT4 Q31 + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/** + @addtogroup DCT4_IDCT4 + @{ + */ + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] S points to an instance of the Q31 DCT4 structure. + @param[in] pState points to state buffer. + @param[in,out] pInlineBuffer points to the in-place input and output buffer. + @return none + + @par Input an output formats + Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process, + as the conversion from DCT2 to DCT4 involves one subtraction. + Internally inputs are downscaled in the RFFT process function to avoid overflows. + Number of bits downscaled, depends on the size of the transform. + The input and output formats for different DCT sizes and number of bits to upscale are + mentioned in the table below: + + \image html dct4FormatsQ31Table.gif + */ + +void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer) +{ + const q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */ + const q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */ + q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + uint32_t i; /* Loop counter */ + + + /* DCT4 computation involves DCT2 (which is calculated using RFFT) + * along with some pre-processing and post-processing. + * Computational procedure is explained as follows: + * (a) Pre-processing involves multiplying input with cos factor, + * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n)) + * where, + * r(n) -- output of preprocessing + * u(n) -- input to preprocessing(actual Source buffer) + * (b) Calculation of DCT2 using FFT is divided into three steps: + * Step1: Re-ordering of even and odd elements of input. + * Step2: Calculating FFT of the re-ordered input. + * Step3: Taking the real part of the product of FFT output and weights. + * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation: + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * where, + * Y4 -- DCT4 output, Y2 -- DCT2 output + * (d) Multiplying the output with the normalizing factor sqrt(2/N). + */ + + /*-------- Pre-processing ------------*/ + /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */ + arm_mult_q31 (pInlineBuffer, cosFact, pInlineBuffer, S->N); + arm_shift_q31 (pInlineBuffer, 1, pInlineBuffer, S->N); + + /* ---------------------------------------------------------------- + * Step1: Re-ordering of even and odd elements as + * pState[i] = pInlineBuffer[2*i] and + * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2 + ---------------------------------------------------------------------*/ + + /* pS1 initialized to pState */ + pS1 = pState; + + /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */ + pS2 = pState + (S->N - 1U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + +#if defined (ARM_MATH_LOOPUNROLL) + + /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */ + i = S->Nby2 >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + *pS1++ = *pbuff++; + *pS2-- = *pbuff++; + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. + * Compute 4 outputs at a time */ + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31 (pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */ + i = (S->N - 1U) >> 2U; + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + do + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + /* points to the next real value */ + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + in = *pS1++ - in; + *pbuff++ = in; + pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + i = (S->N - 1U) % 0x4U; + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing the loop counter to N/4 instead of N for loop unrolling */ + i = S->N >> 2U; + + /* pbuff initialized to the pInlineBuffer(now contains the output values) */ + pbuff = pInlineBuffer; + + /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */ + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + + +#else + + /* Initializing the loop counter to N/2 */ + i = S->Nby2; + + do + { + /* Re-ordering of even and odd elements */ + /* pState[i] = pInlineBuffer[2*i] */ + *pS1++ = *pbuff++; + /* pState[N-i-1] = pInlineBuffer[2*i+1] */ + *pS2-- = *pbuff++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + /* pbuff initialized to input buffer */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Initializing the loop counter */ + i = S->N; + + do + { + /* Writing the re-ordered output back to inplace input buffer */ + *pbuff++ = *pS1++; + + /* Decrement the loop counter */ + i--; + } while (i > 0U); + + + /* --------------------------------------------------------- + * Step2: Calculate RFFT for N-point input + * ---------------------------------------------------------- */ + /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */ + arm_rfft_q31 (S->pRfft, pInlineBuffer, pState); + + /*---------------------------------------------------------------------- + * Step3: Multiply the FFT output with the weights. + *----------------------------------------------------------------------*/ + arm_cmplx_mult_cmplx_q31 (pState, weights, pState, S->N); + + /* The output of complex multiplication is in 3.29 format. + * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */ + arm_shift_q31(pState, 2, pState, S->N * 2); + + /* ----------- Post-processing ---------- */ + /* DCT-IV can be obtained from DCT-II by the equation, + * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0) + * Hence, Y4(0) = Y2(0)/2 */ + /* Getting only real part from the output and Converting to DCT-IV */ + + /* pbuff initialized to input buffer. */ + pbuff = pInlineBuffer; + + /* pS1 initialized to pState */ + pS1 = pState; + + /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */ + in = *pS1++ >> 1U; + /* input buffer acts as inplace, so output values are stored in the input itself. */ + *pbuff++ = in; + + /* pState pointer is incremented twice as the real values are located alternatively in the array */ + pS1++; + + /* Initializing the loop counter */ + i = (S->N - 1U); + + while (i > 0U) + { + /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */ + /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */ + in = *pS1++ - in; + *pbuff++ = in; + + /* points to the next real value */ + pS1++; + + /* Decrement loop counter */ + i--; + } + + /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/ + + /* Initializing loop counter */ + i = S->N; + + /* pbuff initialized to the pInlineBuffer (now contains the output values) */ + pbuff = pInlineBuffer; + + do + { + /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */ + in = *pbuff; + *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31)); + + /* Decrement loop counter */ + i--; + } while (i > 0U); + +#endif /* #if defined (ARM_MATH_LOOPUNROLL) */ + +} + +/** + @} end of DCT4_IDCT4 group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c new file mode 100644 index 0000000..4ec6cd9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f16.c @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f16.c + * Description: MFCC function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "dsp/transform_functions_f16.h" +#include "dsp/statistics_functions_f16.h" +#include "dsp/basic_math_functions_f16.h" +#include "dsp/complex_math_functions_f16.h" +#include "dsp/fast_math_functions_f16.h" +#include "dsp/matrix_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F16 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f16( + const arm_mfcc_instance_f16 * S, + float16_t *pSrc, + float16_t *pDst, + float16_t *pTmp + ) +{ + float16_t maxValue; + uint32_t index; + uint32_t i; + float16_t result; + const float16_t *coefs=S->filterCoefs; + arm_matrix_instance_f16 pDctMat; + + /* Normalize */ + arm_absmax_f16(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f16(pSrc,1.0f16/(_Float16)maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f16(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f16; + } + arm_cfft_f16(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f16(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f16; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f16(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f16(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f16(pTmp,1.0e-4f16,pTmp,S->nbMelFilters); + arm_vlog_f16(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float16_t*)S->dctCoefs; + + arm_mat_vec_mult_f16(&pDctMat, pTmp, pDst); + + +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c new file mode 100644 index 0000000..5ac9458 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_f32.c @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_f32.c + * Description: MFCC function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC F32 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples + @param[out] pDst points to the output MFCC values + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples if the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length size when MFCC + is implemented with CFFT. + It has length FFT Length + 2 when implemented with RFFT + (default implementation). + + The source buffer is modified by this function. + + */ +void arm_mfcc_f32( + const arm_mfcc_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + float32_t *pTmp + ) +{ + float32_t maxValue; + uint32_t index; + uint32_t i; + float32_t result; + const float32_t *coefs=S->filterCoefs; + arm_matrix_instance_f32 pDctMat; + + /* Normalize */ + arm_absmax_f32(pSrc,S->fftLen,&maxValue,&index); + + arm_scale_f32(pSrc,1.0f/maxValue,pSrc,S->fftLen); + + /* Multiply by window */ + arm_mult_f32(pSrc,S->windowCoefs,pSrc,S->fftLen); + + /* Compute spectrum magnitude + */ +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp[2*i] = pSrc[i]; + pTmp[2*i+1] = 0.0f; + } + arm_cfft_f32(&(S->cfft),pTmp,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_fast_f32(&(S->rfft),pSrc,pTmp,0); + /* Unpack real values */ + pTmp[S->fftLen]=pTmp[1]; + pTmp[S->fftLen+1]=0.0f; + pTmp[1]=0.0f; +#endif + arm_cmplx_mag_f32(pTmp,pSrc,S->fftLen); + + /* Apply MEL filters */ + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_f32(pSrc+S->filterPos[i], + coefs, + S->filterLengths[i], + &result); + + coefs += S->filterLengths[i]; + + pTmp[i] = result; + + } + + /* Compute the log */ + arm_offset_f32(pTmp,1.0e-6f,pTmp,S->nbMelFilters); + arm_vlog_f32(pTmp,pTmp,S->nbMelFilters); + + /* Multiply with the DCT matrix */ + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(float32_t*)S->dctCoefs; + + arm_mat_vec_mult_f32(&pDctMat, pTmp, pDst); + + +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c new file mode 100644 index 0000000..d90fd0d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f16.c @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f16.c + * Description: MFCC initialization function for the f16 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + + +/** + @brief Initialization of the MFCC F16 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f16( + arm_mfcc_instance_f16 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float16_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float16_t *filterCoefs, + const float16_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f16(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f16(&(S->rfft),fftLen); + #endif + + return(status); +} + +#endif /* defined(ARM_FLOAT16_SUPPORTED) */ +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c new file mode 100644 index 0000000..0690782 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_f32.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_f32.c + * Description: MFCC initialization function for the f32 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_f32( + arm_mfcc_instance_f32 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const float32_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const float32_t *filterCoefs, + const float32_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_f32(&(S->cfft),fftLen); + #else + status=arm_rfft_fast_init_f32(&(S->rfft),fftLen); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c new file mode 100644 index 0000000..60ff9f2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q15.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q15.c + * Description: MFCC initialization function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q15( + arm_mfcc_instance_q15 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q15_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q15_t *filterCoefs, + const q15_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q15(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q15(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c new file mode 100644 index 0000000..ce3d9dc --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_init_q31.c @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_init_q31.c + * Description: MFCC initialization function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + @ingroup groupTransforms + */ + + +/** + @addtogroup MFCC + @{ + */ + + +#include "dsp/transform_functions.h" + + + +/** + @brief Initialization of the MFCC F32 instance structure + @param[out] S points to the mfcc instance structure + @param[in] fftLen fft length + @param[in] nbMelFilters number of Mel filters + @param[in] nbDctOutputs number of Dct outputs + @param[in] dctCoefs points to an array of DCT coefficients + @param[in] filterPos points of the array of filter positions + @param[in] filterLengths points to the array of filter lengths + @param[in] filterCoefs points to the array of filter coefficients + @param[in] windowCoefs points to the array of window coefficients + + @return error status + + @par Description + The matrix of Mel filter coefficients is sparse. + Most of the coefficients are zero. + To avoid multiplying the spectrogram by those zeros, the + filter is applied only to a given position in the spectrogram + and on a given number of FFT bins (the filter length). + It is the reason for the arrays filterPos and filterLengths. + + window coefficients can describe (for instance) a Hamming window. + The array has the same size as the FFT length. + + The folder Scripts is containing a Python script which can be used + to generate the filter, dct and window arrays. + */ + +arm_status arm_mfcc_init_q31( + arm_mfcc_instance_q31 * S, + uint32_t fftLen, + uint32_t nbMelFilters, + uint32_t nbDctOutputs, + const q31_t *dctCoefs, + const uint32_t *filterPos, + const uint32_t *filterLengths, + const q31_t *filterCoefs, + const q31_t *windowCoefs + ) +{ + arm_status status; + + S->fftLen=fftLen; + S->nbMelFilters=nbMelFilters; + S->nbDctOutputs=nbDctOutputs; + S->dctCoefs=dctCoefs; + S->filterPos=filterPos; + S->filterLengths=filterLengths; + S->filterCoefs=filterCoefs; + S->windowCoefs=windowCoefs; + + #if defined(ARM_MFCC_CFFT_BASED) + status=arm_cfft_init_q31(&(S->cfft),fftLen); + #else + status=arm_rfft_init_q31(&(S->rfft),fftLen,0,1); + #endif + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c new file mode 100644 index 0000000..417cf9e --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q15.c @@ -0,0 +1,208 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q15.c + * Description: MFCC function for the q15 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/* Constants for Q15 implementation */ +#define LOG2TOLOG_Q15 0x02C5C860 +#define MICRO_Q15 0x00000219 +#define SHIFT_MELFILTER_SATURATION_Q15 10 +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q15, and Q15 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q15 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q15 + @param[out] pDst points to the output MFCC values in q8.7 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + +arm_status arm_mfcc_q15( + const arm_mfcc_instance_q15 * S, + q15_t *pSrc, + q15_t *pDst, + q31_t *pTmp + ) +{ + q15_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q15 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q15_t *pTmp2=(q15_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q15 + arm_absmax_q15(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q15_t quotient; + int16_t shift; + + status = arm_divide_q15(0x7FFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q15(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q15 + arm_mult_q15(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q15(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q15(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q15 - fftShift + arm_cmplx_mag_q15(pTmp2,pSrc,filterLimit); + // q14 - fftShift + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q15(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q34.29 - fftShift + result += MICRO_Q15; + result >>= SHIFT_MELFILTER_SATURATION_Q15; + // q34.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q34.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q15; + logExponent = logExponent * LOG2TOLOG_Q15; + + + // q8.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-19,pTmp,S->nbMelFilters); + for(i=0; inbMelFilters; i++) + { + pSrc[i] = __SSAT((q15_t)pTmp[i],16); + } + + // q8.7 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q15_t*)S->dctCoefs; + + arm_mat_vec_mult_q15(&pDctMat, pSrc, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c new file mode 100644 index 0000000..57db4b3 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_mfcc_q31.c @@ -0,0 +1,207 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mfcc_q31.c + * Description: MFCC function for the q31 version + * + * $Date: 07 September 2021 + * $Revision: V1.10.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + + +#include "dsp/transform_functions.h" +#include "dsp/statistics_functions.h" +#include "dsp/basic_math_functions.h" +#include "dsp/complex_math_functions.h" +#include "dsp/fast_math_functions.h" +#include "dsp/matrix_functions.h" + +/* Constants for Q31 implementation */ +#define LOG2TOLOG_Q31 0x02C5C860 +#define MICRO_Q31 0x08637BD0 +#define SHIFT_MELFILTER_SATURATION_Q31 10 +/** + @ingroup groupTransforms + */ + + +/** + @defgroup MFCC MFCC + + MFCC Transform + + There are separate functions for floating-point, Q31, and Q31 data types. + */ + + + +/** + @addtogroup MFCC + @{ + */ + +/** + @brief MFCC Q31 + @param[in] S points to the mfcc instance structure + @param[in] pSrc points to the input samples in Q31 + @param[out] pDst points to the output MFCC values in q8.23 format + @param[inout] pTmp points to a temporary buffer of complex + + @return none + + @par Description + The number of input samples is the FFT length used + when initializing the instance data structure. + + The temporary buffer has a 2*fft length. + + The source buffer is modified by this function. + + The function may saturate. If the FFT length is too + big and the number of MEL filters too small then the fixed + point computations may saturate. + + */ + + +arm_status arm_mfcc_q31( + const arm_mfcc_instance_q31 * S, + q31_t *pSrc, + q31_t *pDst, + q31_t *pTmp + ) +{ + q31_t m; + uint32_t index; + uint32_t fftShift=0; + q31_t logExponent; + q63_t result; + arm_matrix_instance_q31 pDctMat; + uint32_t i; + uint32_t coefsPos; + uint32_t filterLimit; + q31_t *pTmp2=(q31_t*)pTmp; + + arm_status status = ARM_MATH_SUCCESS; + + // q31 + arm_absmax_q31(pSrc,S->fftLen,&m,&index); + + if (m !=0) + { + q31_t quotient; + int16_t shift; + + status = arm_divide_q31(0x7FFFFFFF,m,"ient,&shift); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + arm_scale_q31(pSrc,quotient,shift,pSrc,S->fftLen); + } + + + // q31 + arm_mult_q31(pSrc,S->windowCoefs, pSrc, S->fftLen); + + + /* Compute spectrum magnitude + */ + fftShift = 31 - __CLZ(S->fftLen); +#if defined(ARM_MFCC_CFFT_BASED) + /* some HW accelerator for CMSIS-DSP used in some boards + are only providing acceleration for CFFT. + With ARM_MFCC_CFFT_BASED enabled, CFFT is used and the MFCC + will be accelerated on those boards. + + The default is to use RFFT + */ + /* Convert from real to complex */ + for(i=0; i < S->fftLen ; i++) + { + pTmp2[2*i] = pSrc[i]; + pTmp2[2*i+1] = 0; + } + arm_cfft_q31(&(S->cfft),pTmp2,0,1); +#else + /* Default RFFT based implementation */ + arm_rfft_q31(&(S->rfft),pSrc,pTmp2); +#endif + filterLimit = 1 + (S->fftLen >> 1); + + + // q31 - fftShift + arm_cmplx_mag_q31(pTmp2,pSrc,filterLimit); + // q30 - fftShift + + + /* Apply MEL filters */ + coefsPos = 0; + for(i=0; inbMelFilters; i++) + { + arm_dot_prod_q31(pSrc+S->filterPos[i], + &(S->filterCoefs[coefsPos]), + S->filterLengths[i], + &result); + + coefsPos += S->filterLengths[i]; + + // q16.48 - fftShift + result += MICRO_Q31; + result >>= (SHIFT_MELFILTER_SATURATION_Q31 + 18); + // q16.29 - fftShift - satShift + pTmp[i] = __SSAT(result,31) ; + + } + + + // q16.29 - fftShift - satShift + /* Compute the log */ + arm_vlog_q31(pTmp,pTmp,S->nbMelFilters); + + + // q5.26 + + logExponent = fftShift + 2 + SHIFT_MELFILTER_SATURATION_Q31; + logExponent = logExponent * LOG2TOLOG_Q31; + + + // q5.26 + arm_offset_q31(pTmp,logExponent,pTmp,S->nbMelFilters); + arm_shift_q31(pTmp,-3,pTmp,S->nbMelFilters); + + + // q8.23 + + pDctMat.numRows=S->nbDctOutputs; + pDctMat.numCols=S->nbMelFilters; + pDctMat.pData=(q31_t*)S->dctCoefs; + + arm_mat_vec_mult_q31(&pDctMat, pTmp, pDst); + + return(status); +} + +/** + @} end of MFCC group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c new file mode 100644 index 0000000..8844b73 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c @@ -0,0 +1,318 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +extern void arm_radix4_butterfly_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier); + +extern void arm_radix4_butterfly_inverse_f32( + float32_t * pSrc, + uint16_t fftLen, + const float32_t * pCoef, + uint16_t twidCoefModifier, + float32_t onebyfftLen); + +extern void arm_bitreversal_f32( + float32_t * pSrc, + uint16_t fftSize, + uint16_t bitRevFactor, + const uint16_t * pBitRevTab); + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier); + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the floating-point RFFT/RIFFT. + Source buffer is modified by this function. + + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed in the future. + @param[in] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in] pSrc points to the input buffer + @param[out] pDst points to the output buffer + @return none + + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) and 0.0f + */ + +void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst) +{ + const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft; + + /* Calculation of Real IFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + + /* Complex radix-4 IFFT process */ + arm_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + } + else + { + /* Calculation of RFFT of input */ + + /* Complex radix-4 FFT process */ + arm_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier); + + /* Bit reversal process */ + if (S->bitReverseFlagR == 1U) + { + arm_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable); + } + + /* Real FFT core process */ + arm_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rfft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */ + float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */ + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + /* read pATable[2 * i] */ + CoefA1 = *pCoefA++; + /* pATable[2 * i + 1] */ + CoefA2 = *pCoefA; + + /* pSrc[2 * i] * pATable[2 * i] */ + outR = *pSrc1 * CoefA1; + /* pSrc[2 * i] * CoefA2 */ + outI = *pSrc1++ * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR -= (*pSrc1 + *pSrc2) * CoefA2; + /* pSrc[2 * i + 1] * CoefA1 */ + outI += *pSrc1++ * CoefA1; + + CoefB1 = *pCoefB; + + /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI -= *pSrc2 * CoefA2; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2-- * CoefB1; + + /* write output */ + *pDst1++ = outR; + *pDst1++ = outI; + + /* write complex conjugate output */ + *pDst2-- = -outI; + *pDst2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2U); + pCoefA = pCoefA + ((modifier * 2U) - 1U); + + i--; + + } + + pDst[2U * fftLen] = pSrc[0] - pSrc[1]; + pDst[(2U * fftLen) + 1U] = 0.0f; + + pDst[0] = pSrc[0] + pSrc[1]; + pDst[1] = 0.0f; + +} + + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +void arm_split_rifft_f32( + float32_t * pSrc, + uint32_t fftLen, + const float32_t * pATable, + const float32_t * pBTable, + float32_t * pDst, + uint32_t modifier) +{ + float32_t outR, outI; /* Temporary variables for output */ + const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * CoefA1 */ + outR = *pSrc1 * CoefA1; + + /* - pSrc[2 * i] * CoefA2 */ + outI = -(*pSrc1++) * CoefA2; + + /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */ + outR += (*pSrc1 + *pSrc2) * CoefA2; + + /* pSrc[2 * i + 1] * CoefA1 */ + outI += (*pSrc1++) * CoefA1; + + CoefB1 = *pCoefB; + + /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */ + outI -= *pSrc2-- * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefB1 */ + outR += *pSrc2 * CoefB1; + + /* pSrc[2 * fftLen - 2 * i] * CoefA2 */ + outI += *pSrc2-- * CoefA2; + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c new file mode 100644 index 0000000..9048f83 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f16.c @@ -0,0 +1,612 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f16.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + + +#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) + +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k - 14; + pA += 2; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float16x8x2_t tw,xA,xB; + float16x8x2_t tmp1, tmp2, res; + uint16x8_t vecStridesBkwd; + + vecStridesBkwd = vddupq_u16((uint16_t)14, 2); + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k - 14; + pA += 2 ; + + blockCnt = k >> 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f16(pA); + pA += 16; + + xB = vld2q_f16(pB); + + xB.val[0] = vldrhq_gather_shifted_offset_f16(pB, vecStridesBkwd); + xB.val[1] = vldrhq_gather_shifted_offset_f16(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f16(xB.val[1]); + pB -= 16; + + + tw = vld2q_f16(pCoeff); + tw.val[1] = vnegq_f16(tw.val[1]); + pCoeff += 16; + + + tmp1.val[0] = vaddq_f16(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f16(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f16(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f16(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f16(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f16(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f16(res.val[0], 0.5f); + res.val[1] = vmulq_n_f16(res.val[1], 0.5f); + + + vst2q_f16(pOut, res); + pOut += 16; + + + blockCnt--; + } + + pB += 14; + blockCnt = k & 7; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b; /* temporary variables */ + float16_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = (_Float16)xBR + (_Float16)xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f16 * ( (_Float16)t1a + (_Float16)t1b ); + *pOut++ = 0.5f16 * ( (_Float16)t1a - (_Float16)t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xBR - (_Float16)xAR ; + t1b = (_Float16)xBI + (_Float16)xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = (_Float16)twR * (_Float16)t1a; + p1 = (_Float16)twI * (_Float16)t1a; + p2 = (_Float16)twR * (_Float16)t1b; + p3 = (_Float16)twI * (_Float16)t1b; + + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR + (_Float16)p0 + (_Float16)p3 ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)p1 - (_Float16)p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut) +{ + int32_t k; /* Loop Counter */ + float16_t twR, twI; /* RFFT Twiddle coefficients */ + const float16_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float16_t *pA = p; /* increasing pointer */ + float16_t *pB = p; /* decreasing pointer */ + float16_t xAR, xAI, xBR, xBI; /* temporary variables */ + float16_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f16 * ( (_Float16)xAR + (_Float16)xAI ); + *pOut++ = 0.5f16 * ( (_Float16)xAR - (_Float16)xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = (_Float16)xAR - (_Float16)xBR ; + t1b = (_Float16)xAI + (_Float16)xBI ; + + r = (_Float16)twR * (_Float16)t1a; + s = (_Float16)twI * (_Float16)t1b; + t = (_Float16)twI * (_Float16)t1a; + u = (_Float16)twR * (_Float16)t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f16 * ((_Float16)xAR + (_Float16)xBR - (_Float16)r - (_Float16)s ); //xAR + *pOut++ = 0.5f16 * ((_Float16)xAI - (_Float16)xBI + (_Float16)t - (_Float16)u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f16() and \ref arm_rfft_fast_init_f16(). + + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: + 
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f16 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f16( + const arm_rfft_fast_instance_f16 * S, + float16_t * p, + float16_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f16 * Sint = &(S->Sint); + + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f16(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f16( Sint, pOut, ifftFlag, 1); + } + else + { + + /* Calculation of RFFT of input */ + arm_cfft_f16( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f16(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c new file mode 100644 index 0000000..6712504 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c @@ -0,0 +1,603 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f32.c + * Description: RFFT & RIFFT Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + float32x4x2_t tw,xA,xB; + float32x4x2_t tmp1, tmp2, res; + uint32x4_t vecStridesFwd, vecStridesBkwd; + + vecStridesFwd = vidupq_u32((uint32_t)0, 2); + vecStridesBkwd = -vecStridesFwd; + + int blockCnt; + + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + blockCnt = k >> 2; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xA = vld2q_f32(pA); + pA += 8; + + xB = vld2q_f32(pB); + + xB.val[0] = vldrwq_gather_shifted_offset_f32(pB, vecStridesBkwd); + xB.val[1] = vldrwq_gather_shifted_offset_f32(&pB[1], vecStridesBkwd); + + xB.val[1] = vnegq_f32(xB.val[1]); + pB -= 8; + + + tw = vld2q_f32(pCoeff); + tw.val[1] = vnegq_f32(tw.val[1]); + pCoeff += 8; + + + tmp1.val[0] = vaddq_f32(xA.val[0],xB.val[0]); + tmp1.val[1] = vaddq_f32(xA.val[1],xB.val[1]); + + tmp2.val[0] = vsubq_f32(xB.val[0],xA.val[0]); + tmp2.val[1] = vsubq_f32(xB.val[1],xA.val[1]); + + res.val[0] = vmulq(tw.val[0], tmp2.val[0]); + res.val[0] = vfmsq(res.val[0],tw.val[1], tmp2.val[1]); + + res.val[1] = vmulq(tw.val[0], tmp2.val[1]); + res.val[1] = vfmaq(res.val[1], tw.val[1], tmp2.val[0]); + + res.val[0] = vaddq_f32(res.val[0],tmp1.val[0] ); + res.val[1] = vaddq_f32(res.val[1],tmp1.val[1] ); + + res.val[0] = vmulq_n_f32(res.val[0], 0.5f); + res.val[1] = vmulq_n_f32(res.val[1], 0.5f); + + + vst2q_f32(pOut, res); + pOut += 8; + + + blockCnt--; + } + + blockCnt = k & 3; + while (blockCnt > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + blockCnt--; + } + +} +#else +void stage_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b; /* temporary variables */ + float32_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5f * ( t1a + t1b ); + *pOut++ = 0.5f * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI + + + pA += 2; + pB -= 2; + k--; + } while (k > 0); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut) +{ + int32_t k; /* Loop Counter */ + float32_t twR, twI; /* RFFT Twiddle coefficients */ + const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float32_t *pA = p; /* increasing pointer */ + float32_t *pB = p; /* decreasing pointer */ + float32_t xAR, xAI, xBR, xBI; /* temporary variables */ + float32_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5f * ( xAR + xAI ); + *pOut++ = 0.5f * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +/** + @ingroup groupTransforms +*/ + +/** + @defgroup RealFFT Real FFT Functions + + @par + The CMSIS DSP library includes specialized algorithms for computing the + FFT of real data sequences. The FFT is defined over complex data but + in many applications the input is real. Real FFT algorithms take advantage + of the symmetry properties of the FFT and have a speed advantage over complex + algorithms of the same length. + @par + The Fast RFFT algorithm relays on the mixed radix CFFT that save processor usage. + @par + The real length N forward FFT of a sequence is computed using the steps shown below. + @par + \image html RFFT.gif "Real Fast Fourier Transform" + @par + The real sequence is initially treated as if it were complex to perform a CFFT. + Later, a processing stage reshapes the data to obtain half of the frequency spectrum + in complex format. Except the first complex number that contains the two real numbers + X[0] and X[N/2] all the data is complex. In other words, the first complex sample + contains two real values packed. + @par + The input for the inverse RFFT should keep the same format as the output of the + forward RFFT. A first processing stage pre-process the data to later perform an + inverse CFFT. + @par + \image html RIFFT.gif "Real Inverse Fast Fourier Transform" + @par + The algorithms for floating-point, Q15, and Q31 data are slightly different + and we describe each algorithm in turn. + @par Floating-point + The main functions are \ref arm_rfft_fast_f32() and \ref arm_rfft_fast_init_f32(). + The older functions \ref arm_rfft_f32() and \ref arm_rfft_init_f32() have been deprecated + but are still documented. + @par + The FFT of a real N-point sequence has even symmetry in the frequency domain. + The second half of the data equals the conjugate of the first half flipped in frequency. + Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers. + These are packed into the output array in alternating real and imaginary components: + @par + X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ... + real[(N/2)-1], imag[(N/2)-1 } + @par + It happens that the first complex number (real[0], imag[0]) is actually + all real. real[0] represents the DC offset, and imag[0] should be 0. + (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is + the first harmonic and so on. + @par + The real FFT functions pack the frequency domain data in this fashion. + The forward transform outputs the data in this form and the inverse + transform expects input data in this form. The function always performs + the needed bitreversal so that the input and output data is always in + normal order. The functions support lengths of [32, 64, 128, ..., 4096] + samples. + @par Q15 and Q31 + The real algorithms are defined in a similar manner and utilize N/2 complex + transforms behind the scenes. + @par + The complex transforms used internally include scaling to prevent fixed-point + overflows. The overall scaling equals 1/(fftLen/2). + Due to the use of complex transform internally, the source buffer is + modified by the rfft. + @par + A separate instance structure must be defined for each transform used but + twiddle factor and bit reversal tables can be reused. + @par + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Sets the values of the internal structure fields. + - Initializes twiddle factor table and bit reversal table pointers. + - Initializes the internal complex FFT data structure. + @par + Use of the initialization function is optional **except for MVE versions where it is mandatory**. + If you don't use the initialization functions, then the structures should be initialized with code + similar to the one below: + 
+      arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+      arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform; + fftLenBy2 length of the internal complex transform (fftLenReal/2). + ifftFlagR Selects forward (=0) or inverse (=1) transform. + bitReverseFlagR Selects bit reversed output (=0) or normal order + output (=1). + twidCoefRModifier stride modifier for the twiddle factor table. + The value is based on the FFT length; + pTwiddleARealpoints to the A array of twiddle coefficients; + pTwiddleBRealpoints to the B array of twiddle coefficients; + pCfft points to the CFFT Instance structure. The CFFT structure + must also be initialized. +@par + Note that with MVE versions you can't initialize instance structures directly and **must + use the initialization function**. + */ + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f32 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, + float32_t * pOut, + uint8_t ifftFlag) +{ + const arm_cfft_instance_f32 * Sint = &(S->Sint); + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f32(S, p, pOut); + /* Complex radix-4 IFFT process */ + arm_cfft_f32( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f32( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f32(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c new file mode 100644 index 0000000..a1e4ed0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f64.c @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_f64.c + * Description: RFFT & RIFFT Double precision Floating point process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +void stage_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b; /* temporary variables */ + float64_t p0, p1, p2, p3; /* temporary variables */ + + + k = (S->Sint).fftLen - 1; + + /* Pack first and last sample of the frequency domain together */ + + xBR = pB[0]; + xBI = pB[1]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++ ; + twI = *pCoeff++ ; + + // U1 = XA(1) + XB(1); % It is real + t1a = xBR + xAR ; + + // U2 = XB(1) - XA(1); % It is imaginary + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + *pOut++ = 0.5 * ( t1a + t1b ); + *pOut++ = 0.5 * ( t1a - t1b ); + + // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) )); + pB = p + 2*k; + pA += 2; + + do + { + /* + function X = my_split_rfft(X, ifftFlag) + % X is a series of real numbers + L = length(X); + XC = X(1:2:end) +i*X(2:2:end); + XA = fft(XC); + XB = conj(XA([1 end:-1:2])); + TW = i*exp(-2*pi*i*[0:L/2-1]/L).'; + for l = 2:L/2 + XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l))); + end + XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1)))); + X = XA; + */ + + xBI = pB[1]; + xBR = pB[0]; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xBR - xAR ; + t1b = xBI + xAI ; + + // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI); + // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI); + p0 = twR * t1a; + p1 = twI * t1a; + p2 = twR * t1b; + p3 = twI * t1b; + + *pOut++ = 0.5 * (xAR + xBR + p0 + p3 ); //xAR + *pOut++ = 0.5 * (xAI - xBI + p1 - p2 ); //xAI + + pA += 2; + pB -= 2; + k--; + } while (k > 0U); +} + +/* Prepares data for inverse cfft */ +void merge_rfft_f64( + const arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut) +{ + uint32_t k; /* Loop Counter */ + float64_t twR, twI; /* RFFT Twiddle coefficients */ + const float64_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */ + float64_t *pA = p; /* increasing pointer */ + float64_t *pB = p; /* decreasing pointer */ + float64_t xAR, xAI, xBR, xBI; /* temporary variables */ + float64_t t1a, t1b, r, s, t, u; /* temporary variables */ + + k = (S->Sint).fftLen - 1; + + xAR = pA[0]; + xAI = pA[1]; + + pCoeff += 2 ; + + *pOut++ = 0.5 * ( xAR + xAI ); + *pOut++ = 0.5 * ( xAR - xAI ); + + pB = p + 2*k ; + pA += 2 ; + + while (k > 0U) + { + /* G is half of the frequency complex spectrum */ + //for k = 2:N + // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2)))); + xBI = pB[1] ; + xBR = pB[0] ; + xAR = pA[0]; + xAI = pA[1]; + + twR = *pCoeff++; + twI = *pCoeff++; + + t1a = xAR - xBR ; + t1b = xAI + xBI ; + + r = twR * t1a; + s = twI * t1b; + t = twI * t1a; + u = twR * t1b; + + // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI); + // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI); + *pOut++ = 0.5 * (xAR + xBR - r - s ); //xAR + *pOut++ = 0.5 * (xAI - xBI + t - u ); //xAI + + pA += 2; + pB -= 2; + k--; + } + +} + +/** + @ingroup groupTransforms +*/ + + +/** + @addtogroup RealFFT + @{ +*/ + +/** + @brief Processing function for the Double Precision floating-point real FFT. + @param[in] S points to an arm_rfft_fast_instance_f64 structure + @param[in] p points to input buffer (Source buffer is modified by this function.) + @param[in] pOut points to output buffer + @param[in] ifftFlag + - value = 0: RFFT + - value = 1: RIFFT + @return none +*/ + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, + float64_t * pOut, + uint8_t ifftFlag) +{ + arm_cfft_instance_f64 * Sint = &(S->Sint); + Sint->fftLen = S->fftLenRFFT / 2; + + /* Calculation of Real FFT */ + if (ifftFlag) + { + /* Real FFT compression */ + merge_rfft_f64(S, p, pOut); + + /* Complex radix-4 IFFT process */ + arm_cfft_f64( Sint, pOut, ifftFlag, 1); + } + else + { + /* Calculation of RFFT of input */ + arm_cfft_f64( Sint, p, ifftFlag, 1); + + /* Real FFT extraction */ + stage_rfft_f64(S, p, pOut); + } +} + +/** +* @} end of RealFFT group +*/ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c new file mode 100644 index 0000000..158180b --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f16.c @@ -0,0 +1,357 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f16.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions_f16.h" +#include "arm_common_tables_f16.h" +#include "arm_const_structs_f16.h" + +#if defined(ARM_FLOAT16_SUPPORTED) + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f16( arm_rfft_fast_instance_f16 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f16(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float16_t *) twiddleCoefF16_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f16 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f16( + arm_rfft_fast_instance_f16 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f16 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f16; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f16; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ + +#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c new file mode 100644 index 0000000..e8273b4 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c @@ -0,0 +1,352 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f32.c + * Description: Split Radix Decimation in Frequency CFFT Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + +/** + @private + @brief Initialization function for the 32pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + + S->fftLenRFFT = 32U; + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + +/** + @private + @brief Initialization function for the 64pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 64U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + +/** + @private + @brief Initialization function for the 128pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 128; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + +/** + @private + @brief Initialization function for the 256pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 256U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + +/** + @private + @brief Initialization function for the 512pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 512U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) +/** + @private + @brief Initialization function for the 1024pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 1024U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) +/** + @private + @brief Initialization function for the 2048pt floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 2048U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) +/** + @private +* @brief Initialization function for the 4096pt floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f32( arm_rfft_fast_instance_f32 * S ) { + + arm_status status; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + status=arm_cfft_init_f32(&(S->Sint),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + S->fftLenRFFT = 4096U; + + S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f32 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f32( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f32 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f32; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f32; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c new file mode 100644 index 0000000..c6d3e69 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f64.c @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_fast_init_f64.c + * Description: Split Radix Decimation in Frequency CFFT Double Precision Floating point processing function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + +/** + @ingroup groupTransforms + */ + +/** + @addtogroup RealFFT + @{ + */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + +/** + @brief Initialization function for the 32pt double precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_32_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 16U; + S->fftLenRFFT = 32U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_16; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_16; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_32; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + +/** + @brief Initialization function for the 64pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_64_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 32U; + S->fftLenRFFT = 64U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_32; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_32; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_64; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + +/** + @brief Initialization function for the 128pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_128_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 64U; + S->fftLenRFFT = 128U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_64; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_64; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_128; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + +/** + @brief Initialization function for the 256pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected +*/ + +static arm_status arm_rfft_256_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 128U; + S->fftLenRFFT = 256U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_128; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_128; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_256; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + +/** + @brief Initialization function for the 512pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_512_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 256U; + S->fftLenRFFT = 512U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_256; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_256; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_512; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) +/** + @brief Initialization function for the 1024pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_1024_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 512U; + S->fftLenRFFT = 1024U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_512; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_512; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_1024; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) +/** + @brief Initialization function for the 2048pt Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ +static arm_status arm_rfft_2048_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 1024U; + S->fftLenRFFT = 2048U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_1024; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_1024; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_2048; + + return ARM_MATH_SUCCESS; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) +/** +* @brief Initialization function for the 4096pt Double Precision floating-point real FFT. +* @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected + */ + +static arm_status arm_rfft_4096_fast_init_f64( arm_rfft_fast_instance_f64 * S ) { + + arm_cfft_instance_f64 * Sint; + + if( !S ) return ARM_MATH_ARGUMENT_ERROR; + + Sint = &(S->Sint); + Sint->fftLen = 2048U; + S->fftLenRFFT = 4096U; + + Sint->bitRevLength = ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH; + Sint->pBitRevTable = (uint16_t *)armBitRevIndexTableF64_2048; + Sint->pTwiddle = (float64_t *) twiddleCoefF64_2048; + S->pTwiddleRFFT = (float64_t *) twiddleCoefF64_rfft_4096; + + return ARM_MATH_SUCCESS; +} +#endif + +/** + @brief Initialization function for the Double Precision floating-point real FFT. + @param[in,out] S points to an arm_rfft_fast_instance_f64 structure + @param[in] fftLen length of the Real Sequence + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length + + @par Description + The parameter fftLen specifies the length of RFFT/CIFFT process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096. + @par + This Function also initializes Twiddle factor table pointer and Bit reversal table pointer. + */ + +arm_status arm_rfft_fast_init_f64( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen) +{ + typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f64 *); + fft_init_ptr fptr = 0x0; + + switch (fftLen) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_BITREVIDX_FLT64_2048) && defined(ARM_TABLE_TWIDDLECOEF_F64_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)) + case 4096U: + fptr = arm_rfft_4096_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_BITREVIDX_FLT64_1024) && defined(ARM_TABLE_TWIDDLECOEF_F64_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)) + case 2048U: + fptr = arm_rfft_2048_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_BITREVIDX_FLT64_512) && defined(ARM_TABLE_TWIDDLECOEF_F64_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)) + case 1024U: + fptr = arm_rfft_1024_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_BITREVIDX_FLT64_256) && defined(ARM_TABLE_TWIDDLECOEF_F64_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)) + case 512U: + fptr = arm_rfft_512_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_BITREVIDX_FLT64_128) && defined(ARM_TABLE_TWIDDLECOEF_F64_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)) + case 256U: + fptr = arm_rfft_256_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_BITREVIDX_FLT64_64) && defined(ARM_TABLE_TWIDDLECOEF_F64_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)) + case 128U: + fptr = arm_rfft_128_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_BITREVIDX_FLT64_32) && defined(ARM_TABLE_TWIDDLECOEF_F64_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)) + case 64U: + fptr = arm_rfft_64_fast_init_f64; + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_BITREVIDX_FLT64_16) && defined(ARM_TABLE_TWIDDLECOEF_F64_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)) + case 32U: + fptr = arm_rfft_32_fast_init_f64; + break; +#endif + default: + break; + } + + if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR; + return fptr( S ); + +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c new file mode 100644 index 0000000..0a32da6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c @@ -0,0 +1,147 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_f32.c + * Description: RFFT & RIFFT Floating point initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the floating-point RFFT/RIFFT. + @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed in the future. + @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure + @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure + @param[in] fftLenReal length of the FFT. + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Description + The parameter fftLenRealspecifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 128, 512, 2048. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Complex FFT length */ + S->fftLenBy2 = (uint16_t) fftLenReal / 2U; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (float32_t *) realCoefA; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (float32_t *) realCoefB; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initializations of structure parameters depending on the FFT length */ + switch (S->fftLenReal) + { + /* Init table modifier value */ + case 8192U: + S->twidCoefRModifier = 1U; + break; + case 2048U: + S->twidCoefRModifier = 4U; + break; + case 512U: + S->twidCoefRModifier = 16U; + break; + case 128U: + S->twidCoefRModifier = 64U; + break; + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + + /* Init Complex FFT Instance */ + S->pCfft = S_CFFT; + + if (S->ifftFlagR) + { + /* Initializes the CIFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U); + } + else + { + /* Initializes the CFFT Module for fftLenreal/2 length */ + arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U); + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); + +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c new file mode 100644 index 0000000..e70f8af --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c @@ -0,0 +1,248 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q15.c + * Description: RFFT & RIFFT Q15 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q15 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. + */ + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q15_t *) realCoefAQ15; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q15_t *) realCoefBQ15; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q15_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q15(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q15_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c new file mode 100644 index 0000000..0a28719 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c @@ -0,0 +1,246 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_init_q31.c + * Description: RFFT & RIFFT Q31 initialisation function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" +#include "arm_common_tables.h" +#include "arm_const_structs.h" + + + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Initialization function for the Q31 RFFT/RIFFT. + @param[in,out] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] fftLenReal length of the FFT + @param[in] ifftFlagR flag that selects transform direction + - value = 0: forward transform + - value = 1: inverse transform + @param[in] bitReverseFlag flag that enables / disables bit reversal of output + - value = 0: disables bit reversal of output + - value = 1: enables bit reversal of output + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length + + @par Details + The parameter fftLenReal specifies length of RFFT/RIFFT Process. + Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192. + @par + The parameter ifftFlagR controls whether a forward or inverse transform is computed. + Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated. + @par + The parameter bitReverseFlag controls whether output is in normal order or bit reversed order. + Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order. + @par + This function also initializes Twiddle factor table. +*/ + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag) +{ + /* Initialise the default arm status */ + arm_status status = ARM_MATH_ARGUMENT_ERROR; + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + + /* Initialise the default arm status */ + status = ARM_MATH_SUCCESS; + + /* Initialize the Real FFT length */ + S->fftLenReal = (uint16_t) fftLenReal; + + /* Initialize the Twiddle coefficientA pointer */ + S->pTwiddleAReal = (q31_t *) realCoefAQ31; + + /* Initialize the Twiddle coefficientB pointer */ + S->pTwiddleBReal = (q31_t *) realCoefBQ31; + + /* Initialize the Flag for selection of RFFT or RIFFT */ + S->ifftFlagR = (uint8_t) ifftFlagR; + + /* Initialize the Flag for calculation Bit reversal or not */ + S->bitReverseFlagR = (uint8_t) bitReverseFlag; + + /* Initialization of coef modifier depending on the FFT length */ + switch (S->fftLenReal) + { +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) && defined(ARM_TABLE_BITREVIDX_FXT_4096)) + case 8192U: + + + S->twidCoefRModifier = 1U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),4096); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len4096; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) && defined(ARM_TABLE_BITREVIDX_FXT_2048)) + case 4096U: + S->twidCoefRModifier = 2U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),2048); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len2048; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) && defined(ARM_TABLE_BITREVIDX_FXT_1024)) + case 2048U: + S->twidCoefRModifier = 4U; + + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),1024); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len1024; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_512) && defined(ARM_TABLE_BITREVIDX_FXT_512)) + case 1024U: + S->twidCoefRModifier = 8U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),512); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len512; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_256) && defined(ARM_TABLE_BITREVIDX_FXT_256)) + case 512U: + S->twidCoefRModifier = 16U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),256); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len256; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_128) && defined(ARM_TABLE_BITREVIDX_FXT_128)) + case 256U: + S->twidCoefRModifier = 32U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),128); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len128; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_64) && defined(ARM_TABLE_BITREVIDX_FXT_64)) + case 128U: + S->twidCoefRModifier = 64U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),64); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len64; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_32) && defined(ARM_TABLE_BITREVIDX_FXT_32)) + case 64U: + S->twidCoefRModifier = 128U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),32); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len32; + #endif + break; +#endif +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_Q31_16) && defined(ARM_TABLE_BITREVIDX_FXT_16)) + case 32U: + S->twidCoefRModifier = 256U; + #if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + status=arm_cfft_init_q31(&(S->cfftInst),16); + if (status != ARM_MATH_SUCCESS) + { + return(status); + } + #else + S->pCfft = &arm_cfft_sR_q31_len16; + #endif + break; +#endif + default: + /* Reporting argument error if rfftSize is not valid value */ + status = ARM_MATH_ARGUMENT_ERROR; + break; + } + +#endif +#endif + /* return the status of RFFT Init function */ + return (status); +} + +/** + @} end of RealFFT group + */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c new file mode 100644 index 0000000..7d149c6 --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c @@ -0,0 +1,526 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q15.c + * Description: RFFT & RIFFT Q15 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q15 RFFT/RIFFT. + @param[in] S points to an instance of the Q15 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function.) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT" + @par + \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + */ + +void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q15 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q15 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q15 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q15(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q15 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q15 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real FFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) +#define MVE_CMPLX_MULT_FX_AxB_S16(A,B) vqdmladhxq_s16(vqdmlsdhq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S16(A,B) vqdmladhq_s16(vqdmlsdhxq_s16((__typeof(A))vuninitializedq_s16(), A, B), A, B) + +#endif + +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pOut1 = &pDst[2]; + q15_t *pIn1 = &pSrc[2]; + uint16x8_t offsetIn = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + offsetIn = vaddq_n_u16(offsetIn, (2 * fftLen - 8)); + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 4 + 1; + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offsetIn); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + +#if defined(__CMSIS_GCC_H) + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB_S16(in1, coefA), + MVE_CMPLX_MULT_FX_AxConjB_S16(coefB, in2)); +#else + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q15x8_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q15x8_t)); +#endif + vst1q_s16(pOut1, out); + pOut1 += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offsetIn -= 8; + pIn1 += 8; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; +#if defined (ARM_MATH_DSP) + q15_t *pD1, *pD2; +#endif + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + pSrc1 = &pSrc[2]; + pSrc2 = &pSrc[(2U * fftLen) - 2U]; + +#if defined (ARM_MATH_DSP) + + i = 1U; + pD1 = pDst + 2; + pD2 = pDst + (4U * fftLen) - 2; + + for (i = fftLen - 1; i > 0; i--) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]) + */ + + +#ifndef ARM_MATH_BIG_ENDIAN + /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + outR = __SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA)); +#else + /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */ + outR = -(__SMUSD(read_q15x2 (pSrc1), read_q15x2((q15_t *) pCoefA))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMLAD(read_q15x2 (pSrc2), read_q15x2((q15_t *) pCoefB), outR) >> 16U; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMUSDX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + outI = __SMUSDX(read_q15x2 ((q15_t *) pCoefB), read_q15x2_da (&pSrc2)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */ + outI = __SMLADX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), outI); + + /* write output */ + *pD1++ = (q15_t) outR; + *pD1++ = outI >> 16U; + + /* write complex conjugate output */ + pD2[0] = (q15_t) outR; + pD2[1] = -(outI >> 16U); + pD2 -= 2; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; + +#else + + i = 1U; + + while (i < fftLen) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + */ + + outR = *pSrc1 * *pCoefA; + outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1)); + outR = outR + (*pSrc2 * *pCoefB); + outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 16; + + /* + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + outI = *pSrc2 * *(pCoefB + 1); + outI = outI - (*(pSrc2 + 1) * *pCoefB); + outI = outI + (*(pSrc1 + 1) * *pCoefA); + outI = outI + (*pSrc1 * *(pCoefA + 1)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + pDst[2U * i] = (q15_t) outR; + pDst[2U * i + 1U] = outI >> 16U; + + /* write complex conjugate output */ + pDst[(4U * fftLen) - (2U * i)] = (q15_t) outR; + pDst[((4U * fftLen) - (2U * i)) + 1U] = -(outI >> 16U); + + /* update coefficient pointer */ + pCoefB = pCoefB + (2U * modifier); + pCoefA = pCoefA + (2U * modifier); + + i++; + } + + pDst[2U * fftLen] = (pSrc[0] - pSrc[1]) >> 1; + pDst[2U * fftLen + 1U] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1; + pDst[1] = 0; + +#endif /* #if defined (ARM_MATH_DSP) */ +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + + @par + The function implements a Real IFFT + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pIn1; + uint16x8_t offset = { 6, 7, 4, 5, 2, 3, 0, 1 }; + uint16x8_t offsetCoef; + int16x8_t conj = { 1, -1, 1, -1, 1, -1, 1, -1 }; /* conjugate */ + const uint16_t offsetCoefArr[16] = { + 0, 0, 2, 2, 4, 4, 6, 6, + 0, 1, 0, 1, 0, 1, 0, 1 + }; + + offsetCoef = vmulq_n_u16(vld1q_u16(offsetCoefArr), modifier) + vld1q_u16(offsetCoefArr + 8); + + offset = vaddq_n_u16(offset, (2 * fftLen - 6)); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q15_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i / 4; + + while (i > 0U) { + q15x8_t in1 = vld1q_s16(pIn1); + q15x8_t in2 = vldrhq_gather_shifted_offset_s16(pSrc, offset); + q15x8_t coefA = vldrhq_gather_shifted_offset_s16(pCoefAb, offsetCoef); + q15x8_t coefB = vldrhq_gather_shifted_offset_s16(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ + q15x8_t out = vhaddq_s16(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q15x8_t), + vmulq(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q15x8_t))); + + vst1q_s16(pDst, out); + pDst += 8; + + offsetCoef = vaddq_n_u16(offsetCoef, modifier * 8); + offset -= 8; + + pIn1 += 8; + i -= 1; + } +} +#else +void arm_split_rifft_q15( + q15_t * pSrc, + uint32_t fftLen, + const q15_t * pATable, + const q15_t * pBTable, + q15_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q15_t *pSrc1, *pSrc2; + q15_t *pDst1 = &pDst[0]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + pSrc1 = &pSrc[0]; + pSrc2 = &pSrc[2 * fftLen]; + + i = fftLen; + while (i > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + +#if defined (ARM_MATH_DSP) + +#ifndef ARM_MATH_BIG_ENDIAN + /* pIn[2 * n - 2 * i] * pBTable[2 * i] - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */ + outR = __SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB)); +#else + /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */ + outR = -(__SMUSD(read_q15x2(pSrc2), read_q15x2((q15_t *) pCoefB))); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] + pIn[2 * n - 2 * i] * pBTable[2 * i] */ + outR = __SMLAD(read_q15x2(pSrc1), read_q15x2 ((q15_t *) pCoefA), outR) >> 16U; + + /* -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + outI = __SMUADX(read_q15x2_da (&pSrc2), read_q15x2((q15_t *) pCoefB)); + + /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */ +#ifndef ARM_MATH_BIG_ENDIAN + outI = __SMLSDX(read_q15x2 ((q15_t *) pCoefA), read_q15x2_ia (&pSrc1), -outI); +#else + outI = __SMLSDX(read_q15x2_ia (&pSrc1), read_q15x2 ((q15_t *) pCoefA), -outI); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* write output */ +#ifndef ARM_MATH_BIG_ENDIAN + write_q15x2_ia (&pDst1, __PKHBT(outR, (outI >> 16U), 16)); +#else + write_q15x2_ia (&pDst1, __PKHBT((outI >> 16U), outR, 16)); +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + +#else /* #if defined (ARM_MATH_DSP) */ + + outR = *pSrc2 * *pCoefB; + outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1)); + outR = outR + (*pSrc1 * *pCoefA); + outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 16; + + outI = *(pSrc1 + 1) * *pCoefA; + outI = outI - (*pSrc1 * *(pCoefA + 1)); + outI = outI - (*pSrc2 * *(pCoefB + 1)); + outI = outI - (*(pSrc2 + 1) * *(pCoefB)); + + /* update input pointers */ + pSrc1 += 2U; + pSrc2 -= 2U; + + /* write output */ + *pDst1++ = (q15_t) outR; + *pDst1++ = (q15_t) (outI >> 16); + +#endif /* #if defined (ARM_MATH_DSP) */ + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier); + + i--; + } + +} +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c new file mode 100644 index 0000000..ad3212d --- /dev/null +++ b/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c @@ -0,0 +1,430 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_rfft_q31.c + * Description: FFT & RIFFT Q31 process function + * + * $Date: 23 April 2021 + * $Revision: V1.9.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dsp/transform_functions.h" + +/* ---------------------------------------------------------------------- + * Internal functions prototypes + * -------------------------------------------------------------------- */ + +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier); + +/** + @addtogroup RealFFT + @{ + */ + +/** + @brief Processing function for the Q31 RFFT/RIFFT. + @param[in] S points to an instance of the Q31 RFFT/RIFFT structure + @param[in] pSrc points to input buffer (Source buffer is modified by this function) + @param[out] pDst points to output buffer + @return none + + @par Input an output formats + Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process. + Hence the output format is different for different RFFT sizes. + The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT: + @par + \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT" + @par + \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT" + @par + If the input buffer is of length N, the output buffer must have length 2*N. + The input buffer is modified by this function. + @par + For the RIFFT, the source buffer must at least have length + fftLenReal + 2. + The last two elements must be equal to what would be generated + by the RFFT: + (pSrc[0] - pSrc[1]) >> 1 and 0 + + */ + +void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst) +{ +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + const arm_cfft_instance_q31 *S_CFFT = &(S->cfftInst); +#else + const arm_cfft_instance_q31 *S_CFFT = S->pCfft; +#endif + uint32_t L2 = S->fftLenReal >> 1U; + + /* Calculation of RIFFT of input */ + if (S->ifftFlagR == 1U) + { + /* Real IFFT core process */ + arm_split_rifft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + + /* Complex IFFT process */ + arm_cfft_q31 (S_CFFT, pDst, S->ifftFlagR, S->bitReverseFlagR); + + arm_shift_q31(pDst, 1, pDst, S->fftLenReal); + } + else + { + /* Calculation of RFFT of input */ + + /* Complex FFT process */ + arm_cfft_q31 (S_CFFT, pSrc, S->ifftFlagR, S->bitReverseFlagR); + + /* Real FFT core process */ + arm_split_rfft_q31 (pSrc, L2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier); + } + +} + +/** + @} end of RealFFT group + */ + +/** + @brief Core Real FFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "arm_helium_utils.h" +#include "arm_vec_fft.h" + +#if defined(__CMSIS_GCC_H) + +#define MVE_CMPLX_MULT_FX_AxB_S32(A,B) vqdmladhxq_s32(vqdmlsdhq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) +#define MVE_CMPLX_MULT_FX_AxConjB_S32(A,B) vqdmladhq_s32(vqdmlsdhxq_s32((__typeof(A))vuninitializedq_s32(), A, B), A, B) + +#endif + +void arm_split_rfft_q31( + q31_t *pSrc, + uint32_t fftLen, + const q31_t *pATable, + const q31_t *pBTable, + q31_t *pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pOut1 = &pDst[2]; + q31_t *pIn1 = &pSrc[2]; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + + offset = offset + (2 * fftLen - 4); + + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[2]; + + i = fftLen - 1U; + i = i / 2 + 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB_S32(in1, coefA),MVE_CMPLX_MULT_FX_AxConjB_S32(coefB, in2)); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxB(in1, coefA, q31x4_t), + MVE_CMPLX_MULT_FX_AxConjB(coefB, in2, q31x4_t)); +#endif + vst1q(pOut1, out); + pOut1 += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#else +void arm_split_rfft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[4 * fftLen - 1]; + q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[2 * fftLen - 1]; + + /* Init coefficient pointers */ + pCoefA = &pATable[modifier * 2]; + pCoefB = &pBTable[modifier * 2]; + + i = fftLen - 1U; + + while (i > 0U) + { + /* + outR = ( pSrc[2 * i] * pATable[2 * i] + - pSrc[2 * i + 1] * pATable[2 * i + 1] + + pSrc[2 * n - 2 * i] * pBTable[2 * i] + + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + + pIn[2 * i] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pSrc[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* outI = pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, CoefA2); + + /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */ + multSub_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* (pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pOut1++ = outR; + *pOut1++ = outI; + + /* write complex conjugate output */ + *pOut2-- = -outI; + *pOut2-- = outR; + + /* update coefficient pointer */ + pCoefB = pCoefB + (2 * modifier); + pCoefA = pCoefA + (2 * modifier - 1); + + /* Decrement loop count */ + i--; + } + + pDst[2 * fftLen] = (pSrc[0] - pSrc[1]) >> 1U; + pDst[2 * fftLen + 1] = 0; + + pDst[0] = (pSrc[0] + pSrc[1]) >> 1U; + pDst[1] = 0; +} +#endif /* defined(ARM_MATH_MVEI) */ + +/** + @brief Core Real IFFT process + @param[in] pSrc points to input buffer + @param[in] fftLen length of FFT + @param[in] pATable points to twiddle Coef A buffer + @param[in] pBTable points to twiddle Coef B buffer + @param[out] pDst points to output buffer + @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table + @return none + */ + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + uint32_t i; /* Loop Counter */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t *pIn1; + uint32x4_t offset = { 2, 3, 0, 1 }; + uint32x4_t offsetCoef = { 0, 1, modifier * 2, modifier * 2 + 1 }; + int32x4_t conj = { 1, -1, 1, -1 }; + + offset = offset + (2 * fftLen - 2); + + /* Init coefficient pointers */ + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + const q31_t *pCoefAb, *pCoefBb; + pCoefAb = pCoefA; + pCoefBb = pCoefB; + + pIn1 = &pSrc[0]; + + i = fftLen; + i = i >> 1; + while (i > 0U) { + q31x4_t in1 = vld1q_s32(pIn1); + q31x4_t in2 = vldrwq_gather_shifted_offset_s32(pSrc, offset); + q31x4_t coefA = vldrwq_gather_shifted_offset_s32(pCoefAb, offsetCoef); + q31x4_t coefB = vldrwq_gather_shifted_offset_s32(pCoefBb, offsetCoef); + + /* can we avoid the conjugate here ? */ +#if defined(__CMSIS_GCC_H) + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB_S32(in1, coefA), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB_S32(in2, coefB))); +#else + q31x4_t out = vhaddq_s32(MVE_CMPLX_MULT_FX_AxConjB(in1, coefA, q31x4_t), + vmulq_s32(conj, MVE_CMPLX_MULT_FX_AxB(in2, coefB, q31x4_t))); +#endif + vst1q_s32(pDst, out); + pDst += 4; + + offsetCoef += modifier * 4; + offset -= 4; + + pIn1 += 4; + i -= 1; + } +} +#else +void arm_split_rifft_q31( + q31_t * pSrc, + uint32_t fftLen, + const q31_t * pATable, + const q31_t * pBTable, + q31_t * pDst, + uint32_t modifier) +{ + q31_t outR, outI; /* Temporary variables for output */ + const q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */ + q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */ + q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[2 * fftLen + 1]; + + pCoefA = &pATable[0]; + pCoefB = &pBTable[0]; + + while (fftLen > 0U) + { + /* + outR = ( pIn[2 * i] * pATable[2 * i] + + pIn[2 * i + 1] * pATable[2 * i + 1] + + pIn[2 * n - 2 * i] * pBTable[2 * i] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]); + + outI = ( pIn[2 * i + 1] * pATable[2 * i] + - pIn[2 * i] * pATable[2 * i + 1] + - pIn[2 * n - 2 * i] * pBTable[2 * i + 1] + - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); + */ + + CoefA1 = *pCoefA++; + CoefA2 = *pCoefA; + + /* outR = (pIn[2 * i] * pATable[2 * i] */ + mult_32x32_keep32_R (outR, *pIn1, CoefA1); + + /* - pIn[2 * i] * pATable[2 * i + 1] */ + mult_32x32_keep32_R (outI, *pIn1++, -CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn1, CoefA2); + + /* pIn[2 * i + 1] * pATable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn1++, CoefA1); + + /* pIn[2 * n - 2 * i] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefA2); + CoefB1 = *pCoefB; + + /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */ + multSub_32x32_keep32_R (outI, *pIn2--, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */ + multAcc_32x32_keep32_R (outR, *pIn2, CoefB1); + + /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */ + multAcc_32x32_keep32_R (outI, *pIn2--, CoefA2); + + /* write output */ + *pDst++ = outR; + *pDst++ = outI; + + /* update coefficient pointer */ + pCoefB = pCoefB + (modifier * 2); + pCoefA = pCoefA + (modifier * 2 - 1); + + /* Decrement loop count */ + fftLen--; + } + +} + +#endif /* defined(ARM_MATH_MVEI) */ diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h new file mode 100644 index 0000000..c7ca43c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h @@ -0,0 +1,15613 @@ +/** + ****************************************************************************** + * @file stm32f407xx.h + * @author MCD Application Team + * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - peripherals registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f407xx + * @{ + */ + +#ifndef __STM32F407xx_H +#define __STM32F407xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ + /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; +/* Legacy define */ +#define HASH_RNG_IRQn RNG_IRQn + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + uint32_t RESERVED9[565]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ + uint32_t RESERVED1; /*!< Reserved, 0x78 */ + uint32_t RESERVED2; /*!< Reserved, 0x7C */ + __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED3; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FSMC_Bank2_3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ + __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ + __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ + __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ + __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */ +#define SRAM1_BB_BASE 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define CCMDATARAM_END 0x1000FFFFUL /*!< CCM data RAM end address */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) +#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL) +/* Legacy define */ +#define ADC_BASE ADC123_COMMON_BASE +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) + +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) +#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) +#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) + +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) + +/*!< FSMC Bankx registers base address */ +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL) +#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL) +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) + + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x000UL +#define USB_OTG_DEVICE_BASE 0x800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL +#define USB_OTG_EP_REG_SIZE 0x20UL +#define USB_OTG_HOST_BASE 0x400UL +#define USB_OTG_HOST_PORT_BASE 0x440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL +#define USB_OTG_PCGCCTL_BASE 0xE00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +#define UID_BASE 0x1FFF7A10UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FFF7A22UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FFF7BF0UL /*!< Package size register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +/* Legacy define */ +#define ADC ADC123_COMMON +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32F4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000..a955d47 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..6911417 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1e255d5 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..67bda4e --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..65b824b --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..8b4765f --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv81mml.h b/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..94128a1 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..932d3d1 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..c119fbf --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..6441ff3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..4e7179a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..55fff99 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..74fb87e --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..18a2e6f --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm35p.h b/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..3843d95 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,3277 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..e21cd14 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm55.h b/Drivers/CMSIS/Include/core_cm55.h new file mode 100644 index 0000000..faa30ce --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm55.h @@ -0,0 +1,4817 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.2.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2018-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ +#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ + +#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ +#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ + +#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ +#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ + +#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ +#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ + +#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ +#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ + +#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ +#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ +#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ + +#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ +#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ + +#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ +#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup STL_Type Software Test Library Observation Registers + \brief Type definitions for the Software Test Library Observation Registerss (STL) + @{ + */ + +/** + \brief Structure type to access the Software Test Library Observation Registerss (STL). + */ +typedef struct +{ + __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ + __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ + uint32_t RESERVED0[2U]; + __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ + __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ + __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ + __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ + +} STL_Type; + +/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ +#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ +#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ + +#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ +#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ + +#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ +#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ + +#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ +#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ +#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ +#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ + +#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ +#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ + +#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ +#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ + +#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ +#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ + +/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ +#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ +#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ + +#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ +#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ + +#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ +#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ + +/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ +#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ +#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ + +#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ +#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ +#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ +#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ + +#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ +#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ + +/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ +#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ +#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ + +#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ +#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ + +/*@}*/ /* end of group STL_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ + +/* 'SCnSCB' is deprecated and replaced by 'ICB' */ +typedef ICB_Type SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) + +#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) +#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) + +#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) +#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) + +#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) +#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) + +#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) +#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) + +#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) +#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) + +#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) +#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) + +#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) +#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) + +#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) +#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) + +#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) +#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) + +#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) +#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) +#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) + +#define SCnSCB (ICB) +#define SCnSCB_NS (ICB_NS) + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ +#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..010506e --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2366 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.6 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ + uint32_t RESERVED7[5U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ + +#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ +#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm85.h b/Drivers/CMSIS/Include/core_cm85.h new file mode 100644 index 0000000..6046311 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm85.h @@ -0,0 +1,4672 @@ +/**************************************************************************//** + * @file core_cm85.h + * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File + * @version V1.0.4 + * @date 21. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM85_H_GENERIC +#define __CORE_CM85_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M85 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM85 definitions */ + +#define __CORTEX_M (85U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM85_H_DEPENDANT +#define __CORE_CM85_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM85_REV + #define __CM85_REV 0x0001U + #warning "__CM85_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M85 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core EWIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core PMU Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:1; /*!< bit: 20 Reserved */ + uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ + uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_B_Pos 21U /*!< xPSR: B Position */ +#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ + uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ + uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ + uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ + uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ +#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ + +#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ +#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ + +#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ +#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ + +#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ +#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ + +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ICB Implementation Control Block register (ICB) + \brief Type definitions for the Implementation Control Block Register + @{ + */ + +/** + \brief Structure type to access the Implementation Control Block (ICB). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} ICB_Type; + +/* Auxiliary Control Register Definitions */ +#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ +#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ + +#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ +#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ + +#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ +#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ + +#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ +#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ + +#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +/* Interrupt Controller Type Register Definitions */ +#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_ICB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) + @{ + */ + +/** + \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). + */ +typedef struct +{ + __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ + __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ + uint32_t RESERVED1[2U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ + __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ + uint32_t RESERVED2[313U]; + __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ + __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ + uint32_t RESERVED3[2U]; + __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ + uint32_t RESERVED4[44U]; + __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ + __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ + uint32_t RESERVED5[2U]; + __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ +} MemSysCtl_Type; + +/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ +#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ +#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ + +#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ +#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ + +#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ +#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ + +#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ +#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ + +#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ +#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ + +#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ +#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ + +#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ +#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ + +/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ +#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ +#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ + +#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ +#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ + +/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ +#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ +#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ + +#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ +#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ + +/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ +#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ +#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ + +#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ +#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ + +/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ +#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ +#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ + +#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ +#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ + +/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ +#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ +#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ + +/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ +#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ + +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ +#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ + +/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ +#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ + +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ +#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ + +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ +#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ + + +/*@}*/ /* end of group MemSysCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PwrModCtl_Type Power Mode Control Registers + \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) + @{ + */ + +/** + \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). + */ +typedef struct +{ + __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ + __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ +} PwrModCtl_Type; + +/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ + +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ +#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ + +/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ +#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ + +/*@}*/ /* end of group PwrModCtl_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup EWIC_Type External Wakeup Interrupt Controller Registers + \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) + @{ + */ + +/** + \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). + */ +typedef struct +{ + __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ + uint32_t RESERVED0[31U]; + __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ + __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ +} EWIC_Type; + +/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ +#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ +#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ + +#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ +#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ + +#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ +#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ +#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ +#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ + +#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ +#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ + +#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ +#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ + +/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ +#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ +#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ + +/*@}*/ /* end of group EWIC_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Error Banking Registers (ERRBNK) + @{ + */ + +/** + \brief Structure type to access the Error Banking Registers (ERRBNK). + */ +typedef struct +{ + __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ + __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ + uint32_t RESERVED0[2U]; + __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ + __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ +} ErrBnk_Type; + +/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ +#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ +#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ + +#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ +#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ + +#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ +#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ + +#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ +#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ + +#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ +#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ + +/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ +#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ +#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ + +#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ +#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ + +#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ +#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ + +#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ +#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ + +#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ +#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ +#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ +#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ + +#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ +#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ + +#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ +#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ + +#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ +#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ + +#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ +#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ + +#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ +#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ + +/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ +#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ +#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ + +#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ +#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ + +#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ +#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ + +#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ +#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ + +#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ +#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ + +#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ +#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ +#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ +#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ + +#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ +#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ + +#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ +#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ + +#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ +#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ + +#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ +#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ + +#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ +#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ + +#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ +#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ + +/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ +#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ +#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ + +#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ +#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ + +#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ +#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ + +#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ +#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ + +#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ +#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ + +#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ +#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ + +#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ +#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ + +/*@}*/ /* end of group ErrBnk_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) + \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) + @{ + */ + +/** + \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). + */ +typedef struct +{ + __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ + __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ +} PrcCfgInf_Type; + +/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ + +/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ + +/*@}*/ /* end of group PrcCfgInf_Type */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ + #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ + #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ + #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ + #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ + #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ + #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ + #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ + #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M85 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ +#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ +#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ +#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ +#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ +#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ +#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ +#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ +#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ +#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ +#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ +#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ +#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################### PAC Key functions ########################### */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) +#include "pac_armv81.h" +#endif + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM85_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..dbc755f --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..d666210 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.10 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_starmc1.h b/Drivers/CMSIS/Include/core_starmc1.h new file mode 100644 index 0000000..d86c8d3 --- /dev/null +++ b/Drivers/CMSIS/Include/core_starmc1.h @@ -0,0 +1,3592 @@ +/**************************************************************************//** + * @file core_starmc1.h + * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 07. April 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup STAR-MC1 + @{ + */ + +#include "cmsis_version.h" + +/* Macro Define for STAR-MC1 */ +#define __STAR_MC (1U) /*!< STAR-MC Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group STAR-MC1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for STAR-MC1 processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ + +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ + +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ + +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..3de16ef --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/pac_armv81.h b/Drivers/CMSIS/Include/pac_armv81.h new file mode 100644 index 0000000..854b60a --- /dev/null +++ b/Drivers/CMSIS/Include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/Drivers/CMSIS/Include/pmu_armv8.h b/Drivers/CMSIS/Include/pmu_armv8.h new file mode 100644 index 0000000..f8f3d89 --- /dev/null +++ b/Drivers/CMSIS/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/Drivers/CMSIS/NN/CMakeLists.txt b/Drivers/CMSIS/NN/CMakeLists.txt new file mode 100644 index 0000000..ad3b748 --- /dev/null +++ b/Drivers/CMSIS/NN/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +cmake_minimum_required(VERSION 3.15.6) + +project(CMSISNN) + +set(CMSIS_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../..") + +option(BUILD_CMSIS_NN_FUNCTIONS "Build CMSIS-NN Source." ON) + +if(BUILD_CMSIS_NN_FUNCTIONS) + add_subdirectory(Source) +endif() diff --git a/Drivers/CMSIS/NN/Include/arm_nn_math_types.h b/Drivers/CMSIS/NN/Include/arm_nn_math_types.h new file mode 100644 index 0000000..390fe78 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nn_math_types.h @@ -0,0 +1,169 @@ +/****************************************************************************** + * @file arm_nn_math_types.h + * @brief Compiler include and basic types + * @version V1.1.0 + * @date 09 March 2022 + * Target Processor: Cortex-M + ******************************************************************************/ +/* + * Copyright (c) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + Copied from CMSIS/DSP/arm_math_types.h and modified +*/ + +#ifndef _ARM_NN_MATH_TYPES_H_ + +#define _ARM_NN_MATH_TYPES_H_ + +/* DSP inlcude for enum arm_status. */ +#include "arm_math_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +/* Included for instrinsics definitions */ +#if defined(_MSC_VER) +#include +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static __inline +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __declspec(align(x)) +#endif + +#elif defined(__GNUC_PYTHON__) +#include +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif + +#else +#include "cmsis_compiler.h" +#endif + +#include +#include +#include +#include + +/* evaluate ARM DSP feature */ +#if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#ifndef ARM_MATH_DSP +#define ARM_MATH_DSP 1 +#endif +#endif + +#if __ARM_FEATURE_MVE +#ifndef ARM_MATH_MVEI +#define ARM_MATH_MVEI +#endif +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined(__CC_ARM) + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +#elif defined(__GNUC__) +// #pragma GCC diagnostic pop + +#elif defined(__ICCARM__) + +#elif defined(__TI_ARM__) + +#elif defined(__CSMC__) + +#elif defined(__TASKING__) + +#elif defined(_MSC_VER) + +#else +#error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + +#if __ARM_FEATURE_MVE +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Add necessary typedefs + */ + +#define NN_Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define NN_Q15_MAX ((q15_t)(0x7FFF)) +#define NN_Q7_MAX ((q7_t)(0x7F)) +#define NN_Q31_MIN ((q31_t)(0x80000000L)) +#define NN_Q15_MIN ((q15_t)(0x8000)) +#define NN_Q7_MIN ((q7_t)(0x80)) + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum +{ + ARM_CMSIS_NN_SUCCESS = 0, /**< No error */ + ARM_CMSIS_NN_ARG_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_CMSIS_NN_NO_IMPL_ERROR = -2, /**< No implementation available */ +} arm_cmsis_nn_status; + +#ifdef __cplusplus +} +#endif + +#endif /*ifndef _ARM_NN_MATH_TYPES_H_ */ diff --git a/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/Drivers/CMSIS/NN/Include/arm_nn_tables.h new file mode 100644 index 0000000..327294d --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nn_tables.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. August 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "arm_nn_math_types.h" + +/** + * @brief tables for various activation functions + * + */ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + +/** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/Drivers/CMSIS/NN/Include/arm_nn_types.h b/Drivers/CMSIS/NN/Include/arm_nn_types.h new file mode 100644 index 0000000..6040d72 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nn_types.h @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_types.h + * Description: Public header file to contain the CMSIS-NN structs for the + * TensorFlowLite micro compliant functions + * + * $Date: 22. Februari 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NN_TYPES_H +#define _ARM_NN_TYPES_H + +#include + +/** CMSIS-NN object to contain the width and height of a tile */ +typedef struct +{ + int32_t w; /**< Width */ + int32_t h; /**< Height */ +} cmsis_nn_tile; + +/** CMSIS-NN object used for the function context. */ +typedef struct +{ + void *buf; /**< Pointer to a buffer needed for the optimization */ + int32_t size; /**< Buffer size */ +} cmsis_nn_context; + +/** CMSIS-NN object to contain the dimensions of the tensors */ +typedef struct +{ + int32_t n; /**< Generic dimension to contain either the batch size or output channels. + Please refer to the function documentation for more information */ + int32_t h; /**< Height */ + int32_t w; /**< Width */ + int32_t c; /**< Input channels */ +} cmsis_nn_dims; + +/** CMSIS-NN object for the per-channel quantization parameters */ +typedef struct +{ + int32_t *multiplier; /**< Multiplier values */ + int32_t *shift; /**< Shift values */ +} cmsis_nn_per_channel_quant_params; + +/** CMSIS-NN object for the per-tensor quantization parameters */ +typedef struct +{ + int32_t multiplier; /**< Multiplier value */ + int32_t shift; /**< Shift value */ +} cmsis_nn_per_tensor_quant_params; + +/** CMSIS-NN object for the quantized Relu activation */ +typedef struct +{ + int32_t min; /**< Min value used to clamp the result */ + int32_t max; /**< Max value used to clamp the result */ +} cmsis_nn_activation; + +/** CMSIS-NN object for the convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_conv_params; + +/** CMSIS-NN object for Depthwise convolution layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + int32_t ch_mult; /**< Channel Multiplier. ch_mult * in_ch = out_ch */ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_tile dilation; + cmsis_nn_activation activation; +} cmsis_nn_dw_conv_params; +/** CMSIS-NN object for pooling layer parameters */ +typedef struct +{ + cmsis_nn_tile stride; + cmsis_nn_tile padding; + cmsis_nn_activation activation; +} cmsis_nn_pool_params; + +/** CMSIS-NN object for Fully Connected layer parameters */ +typedef struct +{ + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t filter_offset; /**< Zero value for the filter tensor. Not used */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation activation; +} cmsis_nn_fc_params; + +/** CMSIS-NN object for SVDF layer parameters */ +typedef struct +{ + int32_t rank; + int32_t input_offset; /**< Zero value for the input tensor */ + int32_t output_offset; /**< Zero value for the output tensor */ + cmsis_nn_activation input_activation; + cmsis_nn_activation output_activation; +} cmsis_nn_svdf_params; + +/** CMSIS-NN object for Softmax s16 layer parameters */ +typedef struct +{ + const int16_t *exp_lut; + const int16_t *one_by_one_lut; +} cmsis_nn_softmax_lut_s16; + +#endif // _ARM_NN_TYPES_H diff --git a/Drivers/CMSIS/NN/Include/arm_nnfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h new file mode 100644 index 0000000..deaade7 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nnfunctions.h @@ -0,0 +1,2532 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 19 April 2022 + * $Revision: V.9.0.0 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Convolution Functions + * - Activation Functions + * - Fully-connected Layer Functions + * - SVDF Layer Functions + * - Pooling Functions + * - Softmax Functions + * - Basic math Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Supported Processors + * ------- + * CMSIS-NN targets Cortex-M processors with typically three different implementations for each function. Each + * targets a different group of processors. + * - Processors without SIMD capability (e.g, Cortex-M0) + * - Processors with DSP extention (e.g Cortex-M4) + * - Processors with MVE extension (e.g Cortex-M55) + * The right implementation is picked through feature flags and the user usually does not have to explicit set it. + * + * Function Classification + * -------- + * The functions can be classified into two segments + * - Legacy functions supporting ARM's internal symmetric quantization(8 bits). + * - Functions that support TensorFlow Lite framework with symmetric quantization(8 bits). + * + * The legacy functions can be identified with their suffix of _q7 or _q15 and are no new development is done there. + * The article in [2] describes in detail how to run a network using the legacy functions. + * + * The functions supporting TensorFlow Lite framework is identified by the _s8 suffix and can be invoked from TFL + * micro. The functions are bit exact to TensorFlow Lite. Refer to the TensorFlow's documentation in [3] on how to run + * a TensorFlow Lite model using optimized CMSIS-NN kernels. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have different pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions(DSP extension). + * + * - ARM_MATH_MVEI: + * + * Define macro ARM_MATH_MVEI, If the silicon supports M-Profile Vector Extension. + + * - ARM_MATH_AUTOVECTORIZE + * Used in conjucture with ARM_MATH_MVEI to let the compiler auto vectorize for the functions that uses inline + * assembly. It does not affect functions that use C or intrinsics. + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. This is supported only for the legacy + * functions i.e, functions targetted at TensorFlow Lite do not support big endianness. By default library builds for + * little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2019 Arm Limited. All rights reserved. + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + * + * [2] Converting a Neural Network for Arm Cortex-M with CMSIS-NN + * + https://developer.arm.com/solutions/machine-learning-on-arm/developer-material/how-to-guides/converting-a-neural-network-for-arm-cortex-m-with-cmsis-nn/single-page + * [3] https://www.tensorflow.org/lite/microcontrollers/library + * + * [4] https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/NN#legacy-vs-tfl-micro-compliant-apis + */ + +/** + * @defgroup groupNN Neural Network Functions + * A collection of functions to perform basic operations for neural network layers. Functions with a _s8 suffix support + * TensorFlow Lite framework. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "arm_nn_math_types.h" +#include "arm_nn_types.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup NNConv Convolution Functions + * + * Collection of convolution, depthwise convolution functions and their variants. + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + +/** + * @brief s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + cmsis-nn + * to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + */ +arm_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s8 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + cmsis-nn + * to perform the convolution. + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_wrapper_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + */ +arm_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_wrapper_s16 + * + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] input_dims Input (activation) dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the spatial + * filter dimensions + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for s8 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_s16_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * + */ +arm_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); +/** + * @brief Optimized s16 convolution function + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_fast_s16_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK are the + * spatial filter dimensions. (filter_dims->w * filter_dims->h * input_dims->c) must not + exceed 512 + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int16 + + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7/q15 is used as data type eventhough it is s8/s16 data. It is done so to be consistent with existing APIs. + * 3. Additional memory is required for optimization. Refer to argument 'ctx' for details. + * 4. Implementation supports kernel volumes (filter width * filter height * input channels) < 512. + * + */ + +arm_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Get the required buffer size for fast s16 convolution function + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, HK, WK, C_IN] where HK and WK + * are the spatial filter dimensions + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q7 convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast s8 version for 1x1 convolution (non-square shape) + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_1x1_s8_fast_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, 1, C_IN] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->c is a multiple of 4 + * -# conv_params->padding.w = conv_params->padding.h = 0 + * -# conv_params->stride.w = conv_params->stride.h = 1 + * + */ +arm_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for arm_convolve_1x1_s8_fast + * + * @param[in] input_dims Input (activation) dimensions + * @return The function returns the required buffer size in bytes + * + */ +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims); + +/** + * @brief 1xn convolution + * + * @param[in, out] ctx Function context that contains the additional buffer if required by the function. + arm_convolve_1_x_n_s8_get_buffer_size will return the buffer_size if required + * @param[in] conv_params Convolution parameters (e.g. strides, dilations, pads,...). + * Range of conv_params->input_offset : [-127, 128] + * Range of conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the horizontal + * spatial filter dimension + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Optional bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[out] output_data Output data pointer. Data type: int8 + * + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH if argument constraints fail. or, + * ARM_MATH_SUCCESS on successful completion. + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# input_dims->n equals 1 + * -# ouput_dims->w is a multiple of 4 + * -# Explicit constraints(since it is for 1xN convolution) + * -## input_dims->h equals 1 + * -## output_dims->h equals 1 + * -## filter_dims->h equals 1 + *@todo Remove constraint on output_dims->w to make the function generic. + * + */ +arm_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required additional buffer size for 1xn convolution + * + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * @param[in] filter_dims Filter tensor dimensions. Format: [C_OUT, 1, WK, C_IN] where WK is the + * horizontal spatial filter dimension + * @return The function returns required buffer size(bytes) + * + */ +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + * dim_im_out is a multiple of 2 + */ + +arm_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB); + +/** + * @brief Wrapper function to pick the right optimized s8 depthwise convolution function + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if required. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->output_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful completion. + * + * @details + * - Supported framework: TensorFlow Lite + * - Picks one of the the following functions + * -# arm_depthwise_conv_s8() + * -# arm_depthwise_conv_3x3_s8() - Cortex-M CPUs with DSP extension only + * -# arm_depthwise_conv_s8_opt() + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Check details of arm_depthwise_conv_s8_opt() for potential data that can be accessed outside of the + * boundary. + */ +arm_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get size of additional buffer required by arm_depthwise_conv_wrapper_s8() + * + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Batch argument N is not used and assumed to be 1. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] output_dims Output tensor dimensions. Format: [1, H, W, C_OUT] + * @return Size of additional memory required for optimizations in bytes. + * + */ +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims); + +/** + * @brief Basic s8 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * dw_conv_params->dilation is not used. + * Range of dw_conv_params->input_offset : [-127, 128] + * Range of dw_conv_params->input_offset : [-128, 127] + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Basic s16 depthwise convolution function that doesn't have any constraints on the input dimensions. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * exists if additional memory is. + * @param[in] dw_conv_params Depthwise convolution parameters (e.g. strides, dilations, pads,...) + * conv_params->input_offset : Not used + * conv_params->output_offset : Not used + * @param[in] quant_params Per-channel quantization info. + * It contains the multiplier and shift values to be applied to each + * output channel + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Batch argument N is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, H, W, C_OUT] + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function for 3x3 kernel size with some constraints on + * the input arguments(documented below). Refer arm_depthwise_conv_s8() for function + * argument details. + * + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Unsupported dimension of tensors + * ARM_MATH_ARGUMENT_ERROR - Unsupported pad size along the x axis + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported framework : TensorFlow Lite Micro + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels + * -# Filter height and width equals 3 + * -# Padding along x is either 0 or 1. + * + */ +arm_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel. + * Refer arm_depthwise_conv_s8() for function argument details. + * + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - input channel != output channel or + * ch_mult != 1 + * ARM_MATH_SUCCESS - Successful operation + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read out + * for the following if MVE optimizations(Arm Helium Technology) are used. + * - Output shift + * - Output multiplier + * - Output bias + * - kernel + * @details + * - Supported framework: TensorFlow Lite + * - The following constrains on the arguments apply + * -# Number of input channel equals number of output channels or ch_mult equals 1 + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * - Reccomended when number of channels is 4 or greater. + * + */ +arm_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for optimized s8 depthwise convolution + * function with constraint that in_channel equals out_channel. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [1, H, W, C_IN] + * Batch argument N is not used. + * @param[in] filter_dims Filter tensor dimensions. Format: [1, H, W, C_OUT] + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims); + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Collection of fully-connected and matrix multiplication functions. + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + +/** + *@brief Q7 basic fully-connected layer function + *@param[in] pV pointer to input vector + *@param[in] pM pointer to matrix weights + *@param[in] dim_vec length of the vector + *@param[in] num_of_rows number of rows in weight matrix + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias pointer to bias + *@param[in,out] pOut pointer to output vector + *@param[in,out] vec_buffer pointer to buffer space for input + *@return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Basic s8 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] fc_params Fully Connected layer parameters. + * Range of fc_params->input_offset : [-127, 128] + * fc_params->filter_offset : 0 + * Range of fc_params->output_offset : [-128, 127] + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int32 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Basic s16 Fully Connected function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] fc_params Fully Connected layer parameters. + * fc_params->input_offset : 0 + * fc_params->filter_offset : 0 + * fc_params->output_offset : 0 + * @param[in] quant_params Per-tensor quantization info. + * It contains the multiplier and shift values to be applied to the output tensor. + * @param[in] input_dims Input (activation) tensor dimensions. Format: [N, H, W, C_IN] + * Input dimension is taken as Nx(H * W * C_IN) + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Two dimensional filter dimensions. Format: [N, C] + * N : accumulation depth and equals (H * W * C_IN) from input_dims + * C : output depth and equals C_OUT in output_dims + * H & W : Not used + * @param[in] filter_data Filter data pointer. Data type: int8 + * @param[in] bias_dims Bias tensor dimensions. Format: [C_OUT] + * N, H, W : Not used + * @param[in] bias_data Bias data pointer. Data type: int64 + * @param[in] output_dims Output tensor dimensions. Format: [N, C_OUT] + * N : Batches + * C_OUT : Output depth + * H & W : Not used. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * - Supported framework: TensorFlow Lite + * - q15 is used as data type eventhough it is s16 data. It is done so to be consistent with existing APIs. + */ +arm_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data); + +/** + * @brief Get the required buffer size for S16 basic fully-connected and + * matrix multiplication layer function for TF Lite + * @param[in] filter_dims dimension of filter + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims); + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + +/** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup BasicMath Basic math functions + * + * Elementwise add and multiplication functions. + * + */ + +/** + * @brief s8 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise add of two vectors + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_1_mult multiplier for input 1 + * @param[in] input_1_shift shift for input 1 + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in] input_2_mult multiplier for input 2 + * @param[in] input_2_shift shift for input 2 + * @param[in] left_shift input left shift + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + */ +arm_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s8 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Range: -127 to 128 + * @param[in] input_2_offset offset for input 2. Range: -127 to 128 + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Range: -128 to 127 + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -128 + * @param[in] out_activation_max maximum value to clamp output to. Max: 127 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @brief s16 elementwise multiplication + * @param[in] input_1_vect pointer to input vector 1 + * @param[in] input_2_vect pointer to input vector 2 + * @param[in] input_1_offset offset for input 1. Not used. + * @param[in] input_2_offset offset for input 2. Not used. + * @param[in,out] output pointer to output vector + * @param[in] out_offset output offset. Not used. + * @param[in] out_mult output multiplier + * @param[in] out_shift output shift + * @param[in] out_activation_min minimum value to clamp output to. Min: -32768 + * @param[in] out_activation_max maximum value to clamp output to. Max: 32767 + * @param[in] block_size number of samples + * @return The function returns ARM_MATH_SUCCESS + * + * @details Supported framework: TensorFlow Lite micro + */ +arm_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size); + +/** + * @defgroup Acti Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void arm_relu_q7(q7_t *data, uint16_t size); + +/** + * @brief s8 ReLU6 function + * @param[in,out] data pointer to input + * @param[in] size number of elements + */ + +void arm_relu6_s8(q7_t *data, uint16_t size); + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + +void arm_relu_q15(q15_t *data, uint16_t size); + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type); + +/** + * @defgroup Pooling Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + +/** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out); + +/** + * @brief s8 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief Get the required buffer size for S8 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s8_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s16 average pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int16 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *output_data); + +/** + * @brief Get the required buffer size for S16 average pooling function + * @param[in] dim_dst_width output tensor dimension + * @param[in] ch_src number of input tensor channels + * @return The function returns required buffer size in bytes + * + */ +int32_t arm_avgpool_s16_get_buffer_size(const int dim_dst_width, const int ch_src); + +/** + * @brief s8 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] input_data Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int8 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] output_data Output data pointer. Data type: int8 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s16 max pooling function. + * + * @param[in, out] ctx Function context (e.g. temporary buffer). Check the function + * definition file to see if an additional buffer is required. + * Optional function {API}_get_buffer_size() provides the buffer + * size if an additional buffer is required. + * @param[in] pool_params Pooling parameters + * @param[in] input_dims Input (activation) tensor dimensions. Format: [H, W, C_IN] + * Argument 'N' is not used. + * @param[in] src Input (activation) data pointer. The input tensor must not + * overlap with the output tensor. Data type: int16 + * @param[in] filter_dims Filter tensor dimensions. Format: [H, W] + * Argument N and C are not used. + * @param[in] output_dims Output tensor dimensions. Format: [H, W, C_OUT] + * Argument N is not used. + * C_OUT equals C_IN. + * @param[in, out] dst Output data pointer. Data type: int16 + * @return The function returns + * ARM_MATH_SUCCESS - Successful operation + * + * @details + * - Supported Framework: TensorFlow Lite + * + */ +arm_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax functions. + * + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out); + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out); +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimension + * @param[out] p_out pointer to output vector + * @return none. + * + * @note This function is an optimized version which is not bit-accurate with + * TensorFlow Lite's kernel + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out); + +/** + * @brief S8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output); + +/** + * @brief S8 to s16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output); + +/** + * @brief S16 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] softmax_params Softmax s16 layer parameters with two pointers to LUTs speficied below. + * For indexing the high 9 bits are used and 7 remaining for interpolation. + * That means 512 entries for the 9-bit indexing and 1 extra for interpolation, i.e. 513 + * values for each LUT. + * - Lookup table for exp(x), where x uniform distributed between [-10.0 , 0.0] + * - Lookup table for 1 / (1 + x), where x uniform distributed between [0.0 , 1.0] + * @param[out] output Pointer to the output tensor + * @return The function returns + * ARM_MATH_ARGUMENT_ERROR if LUTs are NULL + * ARM_MATH_SUCCESS - Successful operation + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +arm_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output); + +/** + * @brief U8 softmax function + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ + +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output); + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x stride along the width + * @param[in] stride_y stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns the following + * ARM_MATH_SUCCESS - Successful operation + * + */ +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); + +/** + * @defgroup Reshape Reshape Functions + * + */ + +/** + * @brief Reshape a s8 vector into another with different shape + * @param[in] input points to the s8 input vector + * @param[out] output points to the s8 output vector + * @param[in] total_size total size of the input and output vectors in bytes + * + * @note The output is expected to be in a memory area that does not overlap with the input's + * + */ +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size); + +/** + * @defgroup Concatenation Concatenation Functions + * + */ + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the X axis + * This function should be called for each input tensor to concatenate. The argument offset_x + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_x = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_x(&input[i], ..., &output, ..., ..., offset_x) + * offset_x += input_x[i] + * } + * + * This function assumes that the output tensor has: + * -# The same height of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_x + * bytes. + * @param[in] output_x Width of output tensor + * @param[in] offset_x The offset (in number of elements) on the X axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_x is less than output_x + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Y axis + * This function should be called for each input tensor to concatenate. The argument offset_y + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_y = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_y(&input[i], ..., &output, ..., ..., offset_y) + * offset_y += input_y[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same number of channels of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with the output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_z * input_w * input_x * input_y) + offset_y + * bytes. + * @param[in] output_y Height of output tensor + * @param[in] offset_y The offset on the Y axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_y is less than output_y + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the Z axis + * This function should be called for each input tensor to concatenate. The argument offset_z + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_z = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_z(&input[i], ..., &output, ..., ..., offset_z) + * offset_z += input_z[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same batch size of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor. Input tensor must not overlap with output tensor. + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * (input_x * input_y * input_z * input_w) + offset_z + * bytes. + * @param[in] output_z Channels in output tensor + * @param[in] offset_z The offset on the Z axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + * Input constraints + * offset_z is less than output_z + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z); + +/** + * @brief int8/uint8 concatenation function to be used for concatenating N-tensors along the W axis (Batch size) + * This function should be called for each input tensor to concatenate. The argument offset_w + * will be used to store the input tensor in the correct position in the output tensor + * + * i.e. offset_w = 0 + * for(i = 0 i < num_input_tensors; ++i) + * { + * arm_concatenation_s8_w(&input[i], ..., &output, ..., ..., offset_w) + * offset_w += input_w[i] + * } + * + * This function assumes that the output tensor has: + * -# The same width of the input tensor + * -# The same height of the input tensor + * -# The same number o channels of the input tensor + * + * Unless specified otherwise, arguments are mandatory. + * + * @note This function, data layout independent, can be used to concatenate either int8 or uint8 tensors because it + * does not involve any arithmetic operation + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_z Channels in input tensor + * @param[in] input_w Batch size in input tensor + * @param[out] output Pointer to output tensor. Expected to be at least + * input_x * input_y * input_z * input_w + * bytes. + * @param[in] offset_w The offset on the W axis to start concatenating the input tensor + * It is user responsibility to provide the correct value + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w); +/** + * @defgroup SVDF SVDF Layer Functions + * + */ + +/** + * @brief s8 SVDF function with 8 bit state tensor and 8 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * @param[in] output_ctx Temporary output scratch buffer + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q7_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q7_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +/** + * @brief s8 SVDF function with 16 bit state tensor and 16 bit time weights + * + * @param[in] input_ctx Temporary scratch buffer + * @param[in] output_ctx Temporary output scratch buffer + * @param[in] svdf_params SVDF Parameters + * Range of svdf_params->input_offset : [-128, 127] + * Range of svdf_params->output_offset : [-128, 127] + * @param[in] input_quant_params Input quantization parameters + * @param[in] output_quant_params Output quantization parameters + * @param[in] input_dims Input tensor dimensions + * @param[in] input_data Pointer to input tensor + * @param[in] state_dims State tensor dimensions + * @param[in] state_data Pointer to state tensor + * @param[in] weights_feature_dims Weights (feature) tensor dimensions + * @param[in] weights_feature_data Pointer to the weights (feature) tensor + * @param[in] weights_time_dims Weights (time) tensor dimensions + * @param[in] weights_time_data Pointer to the weights (time) tensor + * @param[in] bias_dims Bias tensor dimensions + * @param[in] bias_data Pointer to bias tensor + * @param[in] output_dims Output tensor dimensions + * @param[out] output_data Pointer to the output tensor + * + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * 1. Supported framework: TensorFlow Lite micro + * 2. q7 is used as data type eventhough it is s8 data. It is done so to be consistent with existing APIs. + * + */ +arm_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 0000000..4b50564 --- /dev/null +++ b/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,1186 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 19. April 2022 + * $Revision: V.7.0.1 + * + * Target Processor: Cortex-M CPUs + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "arm_nn_math_types.h" +#include "arm_nn_types.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define MASK_IF_ZERO(x) (x) == 0 ? ~0 : 0 +#define MASK_IF_NON_ZERO(x) (x) != 0 ? ~0 : 0 +#define SELECT_USING_MASK(mask, a, b) ((mask) & (a)) ^ (~(mask) & (b)) + +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#define MIN(A, B) ((A) < (B) ? (A) : (B)) +#define CLAMP(x, h, l) MAX(MIN((x), (h)), (l)) +#define REDUCE_MULTIPLIER(_mult) ((_mult < 0x7FFF0000) ? ((_mult + (1 << 15)) >> 16) : 0x7FFF) + +/** + * @brief definition to pack four 8 bit values. + */ +#define PACK_Q7x4_32x1(v0, v1, v2, v3) \ + ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) + +/** + * @brief Union for SIMD access of q31/q15/q7 types + */ +union arm_nnword +{ + q31_t word; + /**< q31 type */ + q15_t half_words[2]; + /**< q15 type */ + q7_t bytes[4]; + /**< q7 type */ +}; + +/** + * @brief Union for data type long long + */ +struct arm_nn_double +{ + uint32_t low; + int32_t high; +}; + +union arm_nn_long_long +{ + int64_t long_long; + struct arm_nn_double word; +}; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the q7 vector to q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * + */ +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Non-saturating addition of elements of a q7 vector + * @param[in] *input Pointer to the q7 input vector + * @param[out] *output Pointer to the q31 output variable. + * @param[in] block_size length of the input vector + * \par Description: + * + * 2^24 samples can be added without saturating the result. + * + * The equation used for the conversion process is: + * + * 
+ *  sum = input[0] + input[1] + .. + input[block_size -1]
+ *
+ * + * */ +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector without left-shift + * @param[in] *pSrc points to the q7 input vector + * @param[out] *pDst points to the q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements from a q7 vector to a q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset q7 offset to be added to each input vector element. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] = (q15_t) src[n] + offset;   0 <= n < block_size.
+ *
+ * + */ +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements of the q7 vector to reordered q15 vector with an added offset + * @param[in] src pointer to the q7 input vector + * @param[out] dst pointer to the q15 output vector + * @param[in] block_size length of the input vector + * @param[in] offset offset to be added to each input vector element. + * @return none. + * + * @details This function does the q7 to q15 expansion with re-ordering of bytes. Re-ordering is a consequence of + * the sign extension intrinsic(DSP extension). The tail (i.e., last (N % 4) elements) retains its + * original order. + * + */ +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset); + +/** + * @brief Converts the elements from a q7 vector and accumulate to a q15 vector + * @param[in] *src points to the q7 input vector + * @param[out] *dst points to the q15 output vector + * @param[in] block_size length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ *  dst[n] += (q15_t) src[n] ;   0 <= n < block_size.
+ *
+ * + */ +void arm_nn_accumulate_q7_to_q15(q15_t *dst, const q7_t *src, uint32_t block_size); + +/** + * @brief Depthwise conv on an im2col buffer where the input channel equals output channel. + * @param[in] row pointer to row + * @param[in] col pointer to im2col buffer, always consists of 2 columns. + * @param[in] num_ch number of channels + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] kernel_size number of elements in one column. + * @param[in] output_bias per output channel bias. Range : int32 + * @param[out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * @param[in] input_row pointer to row operand + * @param[in] input_col pointer to col operand + * @param[in] output_ch number of rows of input_row + * @param[in] col_batches number of column batches. Range: 1 to 4 + * @param[in] output_shift pointer to per output channel requantization shift parameter. + * @param[in] output_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] col_offset input tensor(col) offset. + * @param[in] row_offset kernel offset(row). Not used. + * @param[in] out_activation_min minimum value to clamp the output to. Range : int8 + * @param[in] out_activation_max maximum value to clamp the output to. Range : int8 + * @param[in] row_len number of elements in each row + * @param[in] bias per output channel bias. Range : int32 + * @param[in,out] out pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details Supported framework: TensorFlow Lite + */ +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t out_activation_min, + const int16_t out_activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out); +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization for 16 bits convolution. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] activation_min minimum value to clamp the output to. Range : int16 + * @param[in] activation_max maximum value to clamp the output to. Range : int16 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int64 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0); +/** + * @brief General Matrix-multiplication without requantization for one row & one column + * @param[in] row_elements number of row elements + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[out] sum_col pointer to store sum of column elements + * @param[out] output pointer to store result of multiply-accumulate + * @return The function returns the multiply-accumulated result of the row by column. + * + * @details Pseudo-code + * *output = 0 + * sum_col = 0 + * for (i = 0; i < row_elements; i++) + * *output += row_base[i] * col_base[i] + * sum_col += col_base[i] + * + */ +arm_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output); + +/** + * @brief Matrix-multiplication with requantization & activation function for four rows and one column + * @param[in] row_elements number of row elements + * @param[in] offset offset between rows. Can be the same as row_elements. + * For e.g, in a 1x1 conv scenario with stride as 1. + * @param[in] row_base pointer to row operand + * @param[in] col_base pointer to col operand + * @param[in] out_ch Number of output channels + * @param[in] conv_params Pointer to convolution parameters like offsets and activation values + * @param[in] quant_params Pointer to per-channel quantization parameters + * @param[in] bias Pointer to per-channel bias + * @param[out] output Pointer to output where int8 results are stored. + * + * @return The function returns the updated output pointer or NULL if implementation is not available. + * + * @details Compliant to TFLM int8 specification. MVE implementation only + */ +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output); + +/** + * @brief General Matrix-multiplication function with per-channel requantization. + * This function assumes: + * - LHS input matrix NOT transposed (nt) + * - RHS input matrix transposed (t) + * + * @note This operation also performs the broadcast bias addition before the requantization + * + * @param[in] lhs Pointer to the LHS input matrix + * @param[in] rhs Pointer to the RHS input matrix + * @param[in] bias Pointer to the bias vector. The length of this vector is equal to the number of + * output columns (or RHS input rows) + * @param[out] dst Pointer to the output matrix with "m" rows and "n" columns + * @param[in] dst_multipliers Pointer to the multipliers vector needed for the per-channel requantization. + * The length of this vector is equal to the number of output columns (or RHS input + * rows) + * @param[in] dst_shifts Pointer to the shifts vector needed for the per-channel requantization. The length + * of this vector is equal to the number of output columns (or RHS input rows) + * @param[in] lhs_rows Number of LHS input rows + * @param[in] rhs_rows Number of RHS input rows + * @param[in] rhs_cols Number of LHS/RHS input columns + * @param[in] lhs_offset Offset to be applied to the LHS input value + * @param[in] dst_offset Offset to be applied the output result + * @param[in] activation_min Minimum value to clamp down the output. Range : int8 + * @param[in] activation_max Maximum value to clamp up the output. Range : int8 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side vector. + * Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] dst_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] address_offset Memory position offset for dst. First output is stored at 'dst', the + * second at 'dst + address_offset' and so on. Default value is typically 1. + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset); + +/** + * @brief s16 Vector by Matrix (transposed) multiplication + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] bias Input bias + * @param[out] dst Output vector + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief s8 Vector by Matrix (transposed) multiplication with s16 output + * + * @param[in] lhs Input left-hand side vector + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[out] dst Output vector + * @param[in] lhs_offset Offset to be added to the input values of the left-hand side + * vector. Range: -127 to 128 + * @param[in] rhs_offset Not used + * @param[in] scatter_offset Address offset for dst. First output is stored at 'dst', the + * second at 'dst + scatter_offset' and so on. + * @param[in] dst_multiplier Output multiplier + * @param[in] dst_shift Output shift + * @param[in] rhs_cols Number of columns in the right-hand side input matrix + * @param[in] rhs_rows Number of rows in the right-hand side input matrix + * @param[in] activation_min Minimum value to clamp the output to. Range: int16 + * @param[in] activation_max Maximum value to clamp the output to. Range: int16 + * + * @return The function returns ARM_MATH_SUCCESS + * + */ +arm_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t scatter_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in padded cases where + * the padding is -lhs_offset(Range: int8). Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + * @brief Depthwise convolution of transposed rhs matrix with 4 lhs matrices. To be used in non-padded cases. + * Dimensions are the same for lhs and rhs. + * + * @param[in] lhs Input left-hand side matrix + * @param[in] rhs Input right-hand side matrix (transposed) + * @param[in] lhs_offset LHS matrix offset(input offset). Range: -127 to 128 + * @param[in] num_ch Number of channels in LHS/RHS + * @param[in] out_shift Per channel output shift. Length of vector is equal to number of channels. + * @param[in] out_mult Per channel output multiplier. Length of vector is equal to number of channels. + * @param[in] out_offset Offset to be added to the output values. Range: -127 to 128 + * @param[in] activation_min Minimum value to clamp the output to. Range: int8 + * @param[in] activation_max Maximum value to clamp the output to. Range: int8 + * @param[in] row_x_col (row_dimension * col_dimension) of LHS/RHS matrix + * @param[in] output_bias Per channel output bias. Length of vector is equal to number of channels. + * @param[in] out Output pointer + * + * @return The function returns one of the two + * - Updated output pointer if an implementation is available + * - NULL if no implementation is available. + * + * @note If number of channels is not a multiple of 4, upto 3 elements outside the boundary will be read + * out for the following. + * - Output shift + * - Output multiplier + * - Output bias + * - rhs + */ +q7_t *arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t lhs_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out); + +/** + *@brief Matrix-multiplication function for convolution with reordered columns + *@param[in] pA pointer to operand A + *@param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + *@param[in] ch_im_out numRow of A + *@param[in] numCol_A numCol of A + *@param[in] bias_shift amount of left-shift for bias + *@param[in] out_shift amount of right-shift for output + *@param[in] bias the bias + *@param[in,out] pOut pointer to output + *@return The function returns the incremented output pointer + * + *@details This function assumes that data in pInBuffer are reordered + */ +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut); + +/** + @brief Read 2 q15 elements and post increment pointer. + @param[in] in_q15 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2_ia(const q15_t **in_q15) +{ + q31_t val; + + memcpy(&val, *in_q15, 4); + *in_q15 += 2; + + return (val); +} + +/** + @brief Read 4 q7 from q7 pointer and post increment pointer. + @param[in] in_q7 Pointer to pointer that holds address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4_ia(const q7_t **in_q7) +{ + q31_t val; + memcpy(&val, *in_q7, 4); + *in_q7 += 4; + + return (val); +} + +/** + @brief Read 2 q15 from q15 pointer. + @param[in] in_q15 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q15x2(const q15_t *in_q15) +{ + q31_t val; + memcpy(&val, in_q15, 4); + + return (val); +} + +/** + @brief Read 4 q7 values. + @param[in] in_q7 pointer to address of input. + @return q31 value + */ +__STATIC_FORCEINLINE q31_t arm_nn_read_q7x4(const q7_t *in_q7) +{ + q31_t val; + memcpy(&val, in_q7, 4); + + return (val); +} + +/** + @brief Write four q7 to q7 pointer and increment pointer afterwards. + @param[in] in Double pointer to input value + @param[in] value Four bytes to copy + */ +__STATIC_FORCEINLINE void arm_nn_write_q7x4_ia(q7_t **in, q31_t value) +{ + memcpy(*in, &value, 4); + *in += 4; +} + +/** + * @brief memset optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] val Value to set + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memset_q7(q7_t *dst, const q7_t val, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" vdup.8 q0, %[set_val] \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vstrb.8 q0, [%[in]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [ in ] "+r"(dst) + : [ cnt ] "r"(block_size), [ set_val ] "r"(val) + : "q0", "memory", "r14"); +#else + memset(dst, val, block_size); +#endif +} + +#if defined(ARM_MATH_DSP) + +/** + * @brief read and expand one q7 word into two q15 words + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + q31_t inAbuf1 = __SXTB16_RORn((uint32_t)inA, 8); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out1 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#else + *out1 = (int32_t)(__PKHTB(inAbuf1, inAbuf2, 16)); + *out2 = (int32_t)(__PKHBT(inAbuf2, inAbuf1, 16)); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering + */ + +__STATIC_FORCEINLINE const q7_t *read_and_pad_reordered(const q7_t *source, q31_t *out1, q31_t *out2) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} + +/** + * @brief read and expand one q7 word into two q15 words with reordering and add an offset + */ +__STATIC_FORCEINLINE const q7_t * +read_and_pad_reordered_with_offset(const q7_t *source, q31_t *out1, q31_t *out2, q31_t offset) +{ + q31_t inA = arm_nn_read_q7x4_ia(&source); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR((uint32_t)inA, 8)); + *out2 = __SXTB16(inA); +#endif + *out1 = __QADD16(*out1, offset); + *out2 = __QADD16(*out2, offset); + + return source; +} + +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize); + +/** + * @brief Matrix-multiplication function for convolution with per-channel requantization. + * @param[in] input_a pointer to operand A + * @param[in] input_b pointer to operand B, always consists of 2 vectors. + * @param[in] output_ch number of rows of A + * @param[in] out_shift pointer to per output channel requantization shift parameter. + * @param[in] out_mult pointer to per output channel requantization multiplier parameter. + * @param[in] out_offset output tensor offset. + * @param[in] activation_min minimum value to clamp the output to. Range : int8 + * @param[in] activation_max maximum value to clamp the output to. Range : int8 + * @param[in] num_col_a number of columns of A + * @param[in] output_bias per output channel bias. Range : int32 + * @param[in,out] out_0 pointer to output + * @return The function returns one of the two + * 1. The incremented output pointer for a successful operation or + * 2. NULL if implementation is not available. + * + * @details This function does the matrix multiplication of weight matrix for all output channels + * with 2 columns from im2col and produces two elements/output_channel. The outputs are + * clamped in the range provided by activation min and max. + * Supported framework: TensorFlow Lite micro. + */ +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0); + +/** + * @brief Common softmax function for s8 input and s8 or s16 output + * @param[in] input Pointer to the input tensor + * @param[in] num_rows Number of rows in the input tensor + * @param[in] row_size Number of elements in each input row + * @param[in] mult Input quantization multiplier + * @param[in] shift Input quantization shift within the range [0, 31] + * @param[in] diff_min Minimum difference with max in row. Used to check if + * the quantized exponential operation can be performed + * @param[in] int16_output Indicating s8 output if 0 else s16 output + * @param[out] output Pointer to the output tensor + * + * @note Supported framework: TensorFlow Lite micro (bit-accurate) + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output); + +/** + * @brief macro for adding rounding offset + */ +#ifndef ARM_NN_TRUNCATE +#define NN_ROUND(out_shift) ((0x1 << out_shift) >> 1) +#else +#define NN_ROUND(out_shift) 0 +#endif + +// Macros for shortening quantization functions' names and avoid long lines +#define MUL_SAT(a, b) arm_nn_doubling_high_mult((a), (b)) +#define MUL_SAT_MVE(a, b) arm_doubling_high_mult_mve_32x4((a), (b)) +#define MUL_POW2(a, b) arm_nn_mult_by_power_of_two((a), (b)) + +#define DIV_POW2(a, b) arm_nn_divide_by_power_of_two((a), (b)) +#define DIV_POW2_MVE(a, b) arm_divide_by_power_of_two_mve((a), (b)) + +#define EXP_ON_NEG(x) arm_nn_exp_on_negative_values((x)) +#define ONE_OVER1(x) arm_nn_one_over_one_plus_x_for_x_in_0_1((x)) + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult / (1ll << 31)); + + if ((m1 == m2) && (m1 == (int32_t)NN_Q31_MIN)) + { + result = NN_Q31_MAX; + } + return result; +} + +/** + * @brief Doubling high multiply without saturation. This is intended + * for requantization where the scale is a positive integer + * + * @param[in] m1 Multiplicand. Range: {NN_Q31_MIN, NN_Q31_MAX} + * @param[in] m2 Multiplier Range: {NN_Q31_MIN, NN_Q31_MAX} + * @return Result of multiplication. + * @note The result of this matches that of neon instruction + * VQRDMULH for m1 in range {NN_Q31_MIN, NN_Q31_MAX} and m2 in + * range {NN_Q31_MIN + 1, NN_Q31_MAX}. Saturation occurs when + * m1 equals m2 equals NN_Q31_MIN and that is not handled by + * this function. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_doubling_high_mult_no_sat(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + union arm_nn_long_long mult; + + // Rounding offset to add for a right shift of 31 + mult.word.low = 1 << 30; + mult.word.high = 0; + + // Gets resolved as a SMLAL instruction + mult.long_long = mult.long_long + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = (int32_t)(mult.long_long >> 31); + + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1 << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +/** + * @brief Requantize a given value. + * @param[in] val Value to be requantized + * @param[in] multiplier multiplier. Range {NN_Q31_MIN + 1, Q32_MAX} + * @param[in] shift left or right shift for 'val * multiplier' + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize(const q31_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int64_t total_shift = 31 - shift; + const int64_t new_val = val * (int64_t)multiplier; + + int32_t result = new_val >> (total_shift - 1); + result = (result + 1) >> 1; + + return result; +#else + return arm_nn_divide_by_power_of_two(arm_nn_doubling_high_mult_no_sat(val * (1 << LEFT_SHIFT(shift)), multiplier), + RIGHT_SHIFT(shift)); +#endif +} + +/** + * @brief Requantize a given 64 bit value. + * @param[in] val Value to be requantized in the range {-(1<<47)} to {(1<<47) - 1} + * @param[in] reduced_multiplier Reduced multiplier in the range {NN_Q31_MIN + 1, Q32_MAX} to {Q16_MIN + 1, + * Q16_MAX} + * @param[in] shift Left or right shift for 'val * multiplier' in the range {-31} to {7} + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_requantize_s64(const q63_t val, const q31_t reduced_multiplier, const q31_t shift) +{ + const q63_t new_val = val * reduced_multiplier; + + q31_t result = new_val >> (14 - shift); // 64->32 bit reduction + result = (result + 1) >> 1; // Last shift position and insert round + + return result; +} + +/** + * @brief memcpy optimized for MVE + * @param[in, out] dst Destination pointer + * @param[in] src Source pointer. + * @param[in] block_size Number of bytes to copy. + * + */ +__STATIC_FORCEINLINE void arm_memcpy_q7(q7_t *__RESTRICT dst, const q7_t *__RESTRICT src, uint32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + __asm volatile(" wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vldrb.8 q0, [%[in]], #16 \n" + " vstrb.8 q0, [%[out]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [ in ] "+r"(src), [ out ] "+r"(dst) + : [ cnt ] "r"(block_size) + : "q0", "memory", "r14"); +#else + memcpy(dst, src, block_size); +#endif +} + +#if defined(ARM_MATH_MVEI) +/** + * @brief Vector saturating doubling high multiply returning high half. + * @param[in] m1 Multiplicand + * @param[in] m2 Multiplier + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve(const int32x4_t m1, const q31_t m2) +{ + return vqrdmulhq_n_s32(m1, m2); +} + +/** + * @brief Vector rounding divide by power of two. + * @param[in] dividend - Dividend vector + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve(const int32x4_t dividend, const q31_t exponent) +{ + const int32x4_t shift = vdupq_n_s32(-exponent); + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +/** + * @brief Requantize a given vector. + * @param[in] val Vector to be requantized + * @param[in] multiplier multiplier + * @param[in] shift shift + * + * @return Returns (val * multiplier)/(2 ^ shift) + * + */ +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve(const int32x4_t val, const q31_t multiplier, const q31_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int right_shift = MIN(-1, shift); + const int left_shift = shift - right_shift; + + const int32x4_t left_shift_dup = vdupq_n_s32(left_shift); + const int32x4_t right_shift_dup = vdupq_n_s32(right_shift); + + int32x4_t result = vqdmulhq_n_s32(vshlq_s32(val, left_shift_dup), multiplier); + result = vrshlq_s32(result, right_shift_dup); + + return result; +#else + return arm_divide_by_power_of_two_mve( + arm_doubling_high_mult_mve(vshlq_s32(val, vdupq_n_s32(LEFT_SHIFT(shift))), multiplier), RIGHT_SHIFT(shift)); +#endif +} + +__STATIC_FORCEINLINE int32x4_t arm_doubling_high_mult_mve_32x4(const int32x4_t m1, const int32x4_t m2) +{ + return vqrdmulhq_s32(m1, m2); +} + +__STATIC_FORCEINLINE int32x4_t arm_divide_by_power_of_two_mve_32x4(const int32x4_t dividend, const int32x4_t exponent) +{ + const int32x4_t shift = -exponent; + const int32x4_t fixup = vshrq_n_s32(vandq_s32(dividend, shift), 31); + const int32x4_t fixed_up_dividend = vqaddq_s32(dividend, fixup); + return vrshlq_s32(fixed_up_dividend, shift); +} + +__STATIC_FORCEINLINE int32x4_t arm_requantize_mve_32x4(const int32x4_t val, + const int32x4_t multiplier, + const int32x4_t shift) +{ +#ifdef CMSIS_NN_USE_SINGLE_ROUNDING + const int32x4_t right_shift = vminq_s32(vdupq_n_s32(-1), shift); + const int32x4_t left_shift = vqsubq_s32(shift, right_shift); + + int32x4_t result = vqdmulhq_s32(vshlq_s32(val, left_shift), multiplier); + result = vrshlq_s32(result, right_shift); + + return result; +#else + const int32x4_t zz = vdupq_n_s32(0); + const mve_pred16_t p = vcmpgtq_n_s32(shift, 0); + + const int32x4_t left_shift = vpselq_s32(shift, zz, p); + const int32x4_t right_shift = -vpselq_s32(zz, shift, p); + + return arm_divide_by_power_of_two_mve_32x4(arm_doubling_high_mult_mve_32x4(vshlq_s32(val, left_shift), multiplier), + right_shift); +#endif +} +#endif + +// @note The following functions are used only for softmax layer, scaled bits = 5 assumed + +__STATIC_FORCEINLINE int32_t arm_nn_exp_on_negative_values(int32_t val) +{ + int32_t mask = 0; + int32_t shift = 24; + + const int32_t val_mod_minus_quarter = (val & ((1 << shift) - 1)) - (1 << shift); + const int32_t remainder = val_mod_minus_quarter - val; + const int32_t x = (val_mod_minus_quarter << 5) + (1 << 28); + const int32_t x2 = MUL_SAT(x, x); + + int32_t result = 1895147668 + + MUL_SAT(1895147668, x + DIV_POW2(MUL_SAT(DIV_POW2(MUL_SAT(x2, x2), 2) + MUL_SAT(x2, x), 715827883) + x2, 1)); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mask = MASK_IF_NON_ZERO(remainder & (1 << shift++)); \ + result = SELECT_USING_MASK(mask, MUL_SAT(result, x), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mask = MASK_IF_ZERO(val); + return SELECT_USING_MASK(mask, NN_Q31_MAX, result); +} + +__STATIC_FORCEINLINE q31_t arm_nn_mult_by_power_of_two(const int32_t val, const int32_t exp) +{ + const int32_t thresh = ((1 << (31 - exp)) - 1); + int32_t result = val << exp; + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val > thresh), NN_Q31_MAX, result); + result = SELECT_USING_MASK(MASK_IF_NON_ZERO(val < -thresh), NN_Q31_MIN, result); + return result; +} + +__STATIC_FORCEINLINE int32_t arm_nn_one_over_one_plus_x_for_x_in_0_1(int32_t val) +{ + const int64_t sum = (int64_t)val + (int64_t)NN_Q31_MAX; + const int32_t half_denominator = (int32_t)((sum + (sum >= 0 ? 1 : -1)) / 2L); + int32_t x = 1515870810 + MUL_SAT(half_denominator, -1010580540); + + const int32_t shift = (1 << 29); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + x += MUL_POW2(MUL_SAT(x, shift - MUL_SAT(half_denominator, x)), 2); + + return MUL_POW2(x, 1); +} + +/** + @brief Write 2 q15 elements and post increment pointer. + @param[in] dest_q15 Pointer to pointer that holds address of destination. + @param[in] src_q31 Input value to be written. + */ +__STATIC_FORCEINLINE void arm_nn_write_q15x2_ia(q15_t **dest_q15, q31_t src_q31) +{ + q31_t val = src_q31; + + memcpy(*dest_q15, &val, 4); + *dest_q15 += 2; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt new file mode 100644 index 0000000..67c3f79 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 0000000..cb8a08f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief neural network activation function using direct table look-up + * + * @note Refer header file for details. + * + */ + +void arm_nn_activations_direct_q15(q15_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t)in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t)(full_frac - frac) * value + (q31_t)value2 * frac) >> shift_size; + } + else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 0000000..72a0b15 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q7(q7_t *data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c new file mode 100644 index 0000000..a460b30 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu6_s8.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu6_s8.c + * Description: Basic s8 version of ReLU6 + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/* + * Basic ReLU6 function + * + * Refer to header file for details. + * + */ + +void arm_relu6_s8(q7_t *data, uint16_t size) +{ + int32_t i; + + for (i = 0; i < size; i++) + { + int32_t ip = data[i]; + + ip = MAX(ip, 0); + data[i] = MIN(ip, 6); + } +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 0000000..1d4ea4e --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 20. July 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q15(q15_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 1; + q15_t *input = data; + q15_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = arm_nn_read_q15x2_ia((const q15_t **)&input); + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + arm_nn_write_q15x2_ia(&output, in & (~mask)); + i--; + } + + if (size & 0x1) + { + if (*input < 0) + { + *input = 0; + } + input++; + } +#else + /* Run the following code as reference implementation for M cores without DSP extension */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 0000000..a3163cd --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 20. July 2021 + * $Revision: V.1.1.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + +/** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q7(q7_t *data, uint16_t size) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for M cores with DSP extension */ + + uint16_t i = size >> 2; + q7_t *input = data; + q7_t *output = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = arm_nn_read_q7x4_ia((const q7_t **)&input); + + /* extract the first bit */ + buf = (int32_t)__ROR((uint32_t)in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + arm_nn_write_q7x4_ia(&output, in & (~mask)); + + i--; + } + + i = size & 0x3; + while (i) + { + if (*input < 0) + { + *input = 0; + } + input++; + i--; + } + +#else + /* Run the following code as reference implementation for cores without DSP extension */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif +} + +/** + * @} end of Acti group + */ diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt new file mode 100644 index 0000000..9d3f543 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_*.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c new file mode 100644 index 0000000..6b1366d --- /dev/null +++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s16.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s16 + * Description: Elementwise add + * + * $Date: 14 Februari 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s16 elementwise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_status arm_elementwise_add_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + + loop_count = block_size; + + while (loop_count > 0) + { + /* C = A + B */ + input_1 = *input_1_vect++ << left_shift; + input_2 = *input_2_vect++ << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (int16_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c new file mode 100644 index 0000000..13b6bb3 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_add_s8.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_add_s8 + * Description: Elementwise add + * + * $Date: 3 Februari 2022 + * $Revision: V.2.6.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/* + * s8 elementwise add + * + * Refer header file for details. + * + */ + +/* Note: __SHIFT is expected to be <=0 */ + +arm_status arm_elementwise_add_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_1_mult, + const int32_t input_1_shift, + const int32_t input_2_offset, + const int32_t input_2_mult, + const int32_t input_2_shift, + const int32_t left_shift, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ +#if defined(ARM_MATH_MVEI) + int32_t count = block_size; + + while (count > 0) + { + int32x4_t vect_1; + int32x4_t vect_2; + + mve_pred16_t p = vctp32q((uint32_t)count); + + vect_1 = vldrbq_z_s32(input_1_vect, p); + vect_2 = vldrbq_z_s32(input_2_vect, p); + + vect_1 = vaddq_s32(vect_1, vdupq_n_s32(input_1_offset)); + vect_2 = vaddq_s32(vect_2, vdupq_n_s32(input_2_offset)); + + vect_1 = vshlq_r_s32(vect_1, left_shift); + vect_2 = vshlq_r_s32(vect_2, left_shift); + + vect_1 = arm_requantize_mve(vect_1, input_1_mult, input_1_shift); + vect_2 = arm_requantize_mve(vect_2, input_2_mult, input_2_shift); + + vect_1 = vaddq_s32(vect_1, vect_2); + vect_1 = arm_requantize_mve(vect_1, out_mult, out_shift); + + vect_1 = vaddq_n_s32(vect_1, out_offset); + + vect_1 = vmaxq_s32(vect_1, vdupq_n_s32(out_activation_min)); + vect_1 = vminq_s32(vect_1, vdupq_n_s32(out_activation_max)); + + input_1_vect += 4; + input_2_vect += 4; + vstrbq_p_s32(output, vect_1, p); + + output += 4; + count -= 4; + } +#else + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t sum; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Sum 1 */ + input_1 = (b_1 & 0x0FFFF) << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = (b_2 & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r1 = (q7_t)sum; + + /* Sum 3 */ + input_1 = ((b_1 >> 16) & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = ((b_2 >> 16) & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r3 = (q7_t)sum; + + /* Sum 2 */ + input_1 = (a_1 & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = (a_2 & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r2 = (q7_t)sum; + + /* Sum 4 */ + input_1 = ((a_1 >> 16) & 0x0FFFF) << left_shift; + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + + input_2 = ((a_2 >> 16) & 0x0FFFF) << left_shift; + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + r4 = (q7_t)sum; + + arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A + B */ + + input_1 = (*input_1_vect++ + input_1_offset) << left_shift; + input_2 = (*input_2_vect++ + input_2_offset) << left_shift; + + input_1 = arm_nn_requantize(input_1, input_1_mult, input_1_shift); + input_2 = arm_nn_requantize(input_2, input_2_mult, input_2_shift); + + sum = input_1 + input_2; + sum = arm_nn_requantize(sum, out_mult, out_shift); + sum += out_offset; + + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + + *output++ = (q7_t)sum; + + /* Decrement loop counter */ + loop_count--; + } + +#endif /* ARM_MATH_MVEI */ + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of BasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c new file mode 100644 index 0000000..4e25574 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s16.c @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s16 + * Description: Element wise multiplication + * + * $Date: 14 Februari 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s16 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ +arm_status arm_elementwise_mul_s16(const int16_t *input_1_vect, + const int16_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int16_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + (void)input_1_offset; + (void)input_2_offset; + (void)out_offset; + int32_t loop_count; + int32_t input_1; + int32_t input_2; + int32_t mul_res; + + loop_count = block_size; + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++; + input_2 = *input_2_vect++; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift); + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (int16_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c new file mode 100644 index 0000000..ff04cbf --- /dev/null +++ b/Drivers/CMSIS/NN/Source/BasicMathFunctions/arm_elementwise_mul_s8.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_elementwise_mul_s8 + * Description: Element wise multiplication + * + * $Date: 3 Februari 2022 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup BasicMath + * @{ + */ + +/** + * @brief s8 element wise multiplication of two vectors + * + * @note Refer header file for details. + * + */ + +arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect, + const int8_t *input_2_vect, + const int32_t input_1_offset, + const int32_t input_2_offset, + int8_t *output, + const int32_t out_offset, + const int32_t out_mult, + const int32_t out_shift, + const int32_t out_activation_min, + const int32_t out_activation_max, + const int32_t block_size) +{ + + int32_t loop_count; +#if defined(ARM_MATH_MVEI) + + loop_count = (block_size + 3) / 4; + uint32_t num_elements = block_size; + + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp32q(num_elements); + + int32x4_t input_1 = vldrbq_z_s32(input_1_vect, p); + input_1 = vaddq_n_s32(input_1, input_1_offset); + + int32x4_t input_2 = vldrbq_z_s32(input_2_vect, p); + input_2 = vaddq_n_s32(input_2, input_2_offset); + + int32x4_t res_0 = vmulq_s32(input_1, input_2); + + res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift)); + + res_0 += vdupq_n_s32(out_offset); + + res_0 = vmaxq_s32(res_0, vdupq_n_s32(out_activation_min)); + res_0 = vminq_s32(res_0, vdupq_n_s32(out_activation_max)); + + vstrbq_p_s32(output, res_0, p); + input_1_vect += 4; + input_2_vect += 4; + output += 4; + num_elements -= 4; + } + +#else + int32_t input_1; + int32_t input_2; + int32_t mul_res; + +#if defined(ARM_MATH_DSP) + int32_t a_1, b_1, a_2, b_2; + + int32_t offset_1_packed, offset_2_packed; + + int8_t r1, r2, r3, r4; + + offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL); + offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL); + + loop_count = block_size >> 2; + + while (loop_count > 0) + { + /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension + intrinsic */ + input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1); + input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2); + + a_1 = __SADD16(a_1, offset_1_packed); + b_1 = __SADD16(b_1, offset_1_packed); + + a_2 = __SADD16(a_2, offset_2_packed); + b_2 = __SADD16(b_2, offset_2_packed); + + /* Mul 1 */ + input_1 = (int16_t)(b_1 & 0x0FFFFL); + input_2 = (int16_t)(b_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r1 = (q7_t)mul_res; + + /* Mul 3 */ + input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r3 = (q7_t)mul_res; + + /* Mul 2 */ + input_1 = (int16_t)(a_1 & 0x0FFFFL); + input_2 = (int16_t)(a_2 & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r2 = (q7_t)mul_res; + + /* Mul 4 */ + input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL); + input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL); + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + r4 = (q7_t)mul_res; + + arm_nn_write_q7x4_ia(&output, PACK_Q7x4_32x1(r1, r2, r3, r4)); + + loop_count--; + } + + loop_count = block_size & 0x3; +#else + loop_count = block_size; +#endif + + while (loop_count > 0) + { + /* C = A * B */ + + input_1 = *input_1_vect++ + input_1_offset; + input_2 = *input_2_vect++ + input_2_offset; + + mul_res = input_1 * input_2; + mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset; + + mul_res = MAX(mul_res, out_activation_min); + mul_res = MIN(mul_res, out_activation_max); + + *output++ = (q7_t)mul_res; + + /* Decrement loop counter */ + loop_count--; + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of BasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/CMakeLists.txt b/Drivers/CMSIS/NN/Source/CMakeLists.txt new file mode 100644 index 0000000..4150df3 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/CMakeLists.txt @@ -0,0 +1,98 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +SET(ROOT ${CMSIS_PATH}) + +# Select which parts of the CMSIS-DSP must be compiled. +# There are some dependencies between the parts but they are not tracked +# by this cmake. So, enabling some functions may require to enable some +# other ones. +option(CONCATENATION "Concatenation" ON) +option(FULLYCONNECTED "Fully Connected" ON) +option(CONVOLUTION "Convolutions" ON) +option(ACTIVATION "Activations" ON) +option(POOLING "Pooling" ON) +option(SOFTMAX "Softmax" ON) +option(BASICMATHSNN "Basic Maths for NN" ON) +option(RESHAPE "Reshape" ON) +option(SVDF "SVDF" ON) + +# When OFF it is the default behavior : all tables are included. +option(NNSUPPORT "NN Support" ON) + + +########################### +# +# CMSIS NN +# +########################### + +# NN Sources +SET(NN ${ROOT}/CMSIS/NN) + +list(APPEND CMAKE_MODULE_PATH ${NN}/Source) + +add_library(cmsis-nn STATIC) + +target_compile_options(cmsis-nn PRIVATE -Ofast) + +### Includes +target_include_directories(cmsis-nn PUBLIC "${NN}/Include") +target_include_directories(cmsis-nn PUBLIC "${ROOT}/CMSIS/Core/Include") +target_include_directories(cmsis-nn PUBLIC "${ROOT}/CMSIS/DSP/Include") + +if (BASICMATHSNN) + add_subdirectory(BasicMathFunctions) +endif() + +if (CONCATENATION) + add_subdirectory(ConcatenationFunctions) +endif() + +if (FULLYCONNECTED) + add_subdirectory(FullyConnectedFunctions) +endif() + +if (CONVOLUTION) + add_subdirectory(ConvolutionFunctions) +endif() + +if (ACTIVATION) + add_subdirectory(ActivationFunctions) +endif() + +if (POOLING) + add_subdirectory(PoolingFunctions) +endif() + +if (SOFTMAX) + add_subdirectory(SoftmaxFunctions) +endif() + +if (SVDF) + add_subdirectory(SVDFunctions) +endif() + +if (RESHAPE) + add_subdirectory(ReshapeFunctions) +endif() + +# Keep NNSUPPORT at the end +if (NNSUPPORT) + add_subdirectory(NNSupportFunctions) +endif() diff --git a/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt new file mode 100644 index 0000000..9d3f543 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_*.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c new file mode 100644 index 0000000..257e6a6 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_w.c + * Description: s8 version of concatenation along the W axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the W axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_w(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint32_t offset_w) +{ + const uint32_t input_copy_size = input_x * input_y * input_z * input_w; + + output += offset_w * (input_x * input_y * input_z); + + arm_memcpy_q7(output, input, input_copy_size); +} + +/** + * @} end of Concatenation group + */ diff --git a/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c new file mode 100644 index 0000000..7e8487a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_x.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_x.c + * Description: s8 version of concatenation along the X axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the X axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_x(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_x, + const uint32_t offset_x) +{ + const uint32_t num_iterations = input_y * input_z * input_w; + + output += offset_x; + + uint32_t i; + + // Copy per row + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_x); + input += input_x; + output += output_x; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c new file mode 100644 index 0000000..075a702 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_y.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_y.c + * Description: s8 version of concatenation along the Y axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Y axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_y(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_y, + const uint32_t offset_y) +{ + const uint32_t num_iterations = input_z * input_w; + const uint32_t input_copy_size = input_x * input_y; + const uint32_t output_stride = input_x * output_y; + + output += offset_y * input_x; + uint32_t i; + + // Copy per tile + for (i = 0; i < num_iterations; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c new file mode 100644 index 0000000..3bd84f2 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConcatenationFunctions/arm_concatenation_s8_z.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_concatenation_s8_z.c + * Description: s8 version of concatenation along the Z axis + * + * $Date: October 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Concatenation + * @{ + */ + +/* + * s8 version of concatenation along the Z axis + * + * Refer to header file for details. + * + */ +void arm_concatenation_s8_z(const int8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_z, + const uint16_t input_w, + int8_t *output, + const uint16_t output_z, + const uint32_t offset_z) +{ + const uint32_t input_copy_size = input_x * input_y * input_z; + const uint32_t output_stride = input_x * input_y * output_z; + + output += offset_z * (input_x * input_y); + + uint32_t i; + + for (i = 0; i < input_w; ++i) + { + arm_memcpy_q7(output, input, input_copy_size); + input += input_copy_size; + output += output_stride; + } +} + +/** + * @} end of Concatenation group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt new file mode 100644 index 0000000..30be0fe --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8*.c") +file(GLOB SRC_S16 "./*_s16*.c") +target_sources(cmsis-nn PRIVATE ${SRC} ${SRC_S16}) + + + diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c new file mode 100644 index 0000000..a3edd40 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1_x_n_s8.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1_x_n_s8.c + * Description: s8 version of 1xN convolution using symmetric quantization. + * + * $Date: December 14, 2021 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * 1xN s8 convolution function. + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_1_x_n_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + arm_status status = ARM_MATH_SUCCESS; + if (output_dims->w % 4 != 0) + { + status = ARM_MATH_SIZE_MISMATCH; + goto out; + } + +#if defined(ARM_MATH_MVEI) + (void)ctx; + + const uint16_t input_x = input_dims->w; + const uint16_t kernel_x = filter_dims->w; + const uint16_t output_x = output_dims->w; + const uint16_t output_ch = output_dims->c; + const uint16_t input_ch = input_dims->c; + const uint16_t pad_x = conv_params->padding.w; + const uint16_t stride_x = conv_params->stride.w; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_out_x = 0; i_out_x <= (output_x - 4); i_out_x += 4) + { + int32_t input_begin_idx[4]; + int32_t ker_begin_idx[4]; + int32_t ker_end_idx[4]; + + for (int i = 0; i < 4; i++) + { + const int32_t est_input_x_idx = stride_x * (i_out_x + i) - pad_x; + input_begin_idx[i] = MAX(0, est_input_x_idx); + ker_begin_idx[i] = MAX(0, -est_input_x_idx); + ker_end_idx[i] = MIN(kernel_x, input_x - est_input_x_idx); + } + + if ((ker_begin_idx[0] != 0) || (ker_end_idx[3] != kernel_x)) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32x4_t s_offset; + int32_t acc[4]; + { + int32_t sum_row[4]; + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[0] - ker_begin_idx[0]) * input_ch, + input_data + input_begin_idx[0] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[0] * input_ch), + &sum_row[0], + &acc[0]); + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[1] - ker_begin_idx[1]) * input_ch, + input_data + input_begin_idx[1] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[1] * input_ch), + &sum_row[1], + &acc[1]); + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[2] - ker_begin_idx[2]) * input_ch, + input_data + input_begin_idx[2] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[2] * input_ch), + &sum_row[2], + &acc[2]); + + (void)arm_nn_mat_mul_core_1x_s8((ker_end_idx[3] - ker_begin_idx[3]) * input_ch, + input_data + input_begin_idx[3] * input_ch, + filter_data + (input_ch * kernel_x * i_out_ch) + + (ker_begin_idx[3] * input_ch), + &sum_row[3], + &acc[3]); + + s_offset = vldrwq_s32(sum_row); + } + int32x4_t res = vldrwq_s32(acc); + s_offset = vmulq_n_s32(s_offset, input_offset); + res = vaddq_s32(res, s_offset); + if (bias_data) + { + res = vaddq_n_s32(res, bias_data[i_out_ch]); + } + res = arm_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); + res = vaddq_n_s32(res, out_offset); + + res = vmaxq_s32(res, vdupq_n_s32(out_activation_min)); + res = vminq_s32(res, vdupq_n_s32(out_activation_max)); + + const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; + vstrbq_scatter_offset_s32(output_data, scatter_offset, res); + output_data++; + } + output_data += (3 * output_ch); + } + else + { + output_data = arm_nn_mat_mul_core_4x_s8(kernel_x * input_ch, + stride_x * input_ch, + input_data + input_begin_idx[0] * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + } + +#else + status = arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif + +out: + /* Return to application */ + return status; +} + +int32_t arm_convolve_1_x_n_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if !defined(ARM_MATH_MVEI) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..3db3ba4 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + (void)dim_im_in_y; + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 || padding_x != 0 || + padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c new file mode 100644 index 0000000..6183f55 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_s8_fast.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_s8_fast.c + * Description: Fast q7 version of 1x1 convolution (non-square shape) + * + * $Date: 12. November 2021 + * $Revision: V.2.0.4 + * + * Target Processor: Cortex-M Processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" +#include + +#define DIM_KER_X (1U) +#define DIM_KER_Y (1U) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Fast s8 version for 1x1 convolution (non-square shape) + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_1x1_s8_fast(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if (input_dims->c % 4 != 0 || conv_params->padding.w != 0 || conv_params->padding.h != 0 || + conv_params->stride.w != 1 || conv_params->stride.h != 1) + { + return ARM_MATH_SIZE_MISMATCH; + } + + (void)ctx; + (void)filter_dims; + (void)bias_dims; + +#if defined(ARM_MATH_MVEI) + + const int32_t col_len = input_dims->w * input_dims->h * input_dims->n; + const int32_t output_ch = output_dims->c; + const int32_t input_ch = input_dims->c; + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_items = 0; i_items <= (col_len - 4); i_items += 4) + { + + output_data = arm_nn_mat_mul_core_4x_s8(input_ch, + input_ch, + input_data + i_items * input_ch, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + output_data); + } + + /* Handle left over elements */ + for (int i_items = (col_len & ~0x3); i_items < col_len; i_items++) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t sum_row = 0; + int32_t acc; + (void)arm_nn_mat_mul_core_1x_s8( + input_ch, input_data + i_items * input_ch, filter_data + i_out_ch * input_ch, &sum_row, &acc); + if (bias_data) + { + acc += bias_data[i_out_ch]; + } + sum_row = (sum_row * input_offset); + acc += sum_row; + acc = arm_nn_requantize(acc, output_mult[i_out_ch], output_shift[i_out_ch]); + acc += out_offset; + + acc = MAX(acc, out_activation_min); + acc = MIN(acc, out_activation_max); + *output_data++ = acc; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M processors with or without DSP extension */ + + const int32_t lhs_rows = input_dims->w * input_dims->h * input_dims->n; + const int32_t rhs_rows = output_dims->c; + const int32_t rhs_cols = input_dims->c; + + arm_nn_mat_mult_nt_t_s8(input_data, + filter_data, + bias_data, + output_data, + quant_params->multiplier, + quant_params->shift, + lhs_rows, + rhs_rows, + rhs_cols, + conv_params->input_offset, + conv_params->output_offset, + conv_params->activation.min, + conv_params->activation.max); + +#endif + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_1x1_s8_fast_get_buffer_size(const cmsis_nn_dims *input_dims) +{ + (void)input_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 0000000..0a6868a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status arm_convolve_HWC_q15_basic(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t)__SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 0000000..66fbc00 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,259 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + * dim_im_out is a multiple of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast(const q15_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0 || dim_im_out & 0x1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 0000000..7babe51 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,270 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multiple of 2 + * + */ + +arm_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, + (q15_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + sizeof(q15_t) * ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = arm_nn_read_q15x2_ia(&pA); + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inA2 = arm_nn_read_q15x2_ia(&pA2); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 0000000..618f492 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status arm_convolve_HWC_q7_RGB(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + arm_memset_q7((q7_t *)pBuffer, (q7_t)0, 3 * sizeof(q15_t)); + pBuffer += 3; + } + else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = arm_nn_read_q7x4(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + int32_t packed_word = __PKHBT(bottom.word, top.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + int32_t packed_word = __PKHTB(top.word, bottom.word, 0); + arm_memcpy_q7((q7_t *)pBuffer, (q7_t *)&packed_word, 4); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia((const q15_t **)&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 0000000..e274413 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status arm_convolve_HWC_q7_basic(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 0000000..b42a57d --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = arm_nn_mat_mult_kernel_q7_q15( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + const q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)bufferA; + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 0000000..51d98fd --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multiple of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +arm_status arm_convolve_HWC_q7_fast(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *)Im_in + + (i_ker_y * dim_im_in + i_out_x * stride - padding) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..25f17bb --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, + ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t) * ch_im_in); + } + else + { + arm_q7_to_q15_reordered_no_shift( + (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = arm_nn_mat_mult_kernel_q7_q15_reordered( + wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + const q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = read_and_pad_reordered(pA, &inA1, &inA2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA1, inB1, sum); + inB2 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t)__SSAT((sum >> out_shift), 8); + pOut++; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c new file mode 100644 index 0000000..f509f26 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_fast_s16.c @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_fast_s16.c + * Description: Optimized s16 version of convolution. + * + * $Date: 12 August 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_fast_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + if (filter_dims->w * filter_dims->h * input_dims->c >= 512) + { + return ARM_MATH_SIZE_MISMATCH; + } + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + + const int16_t out_activation_min = conv_params->activation.min; + const int16_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q15_t *out = output_data; + /* This part implements the im2col function */ + for (int32_t i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int32_t i_out_x = 0; i_out_x < output_x; i_out_x++) + { + for (int32_t i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y; + i_ker_y++) + { + for (int32_t i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + arm_memset_q7((q7_t *)two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + arm_memcpy_q7((q7_t *)two_column_buf, + (const q7_t *)(input_data + (i_ker_y * input_x + i_ker_x) * input_ch), + input_ch * sizeof(q15_t)); + } + two_column_buf += input_ch; + } + } + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_activation_min, + out_activation_max, + (input_ch * kernel_y * kernel_x), + bias_data, + out); + + /* Counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* Left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Init the accumulator*/ + q31_t sum = 0; + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + if (bias_data) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i]); + q63_t acc_64 = sum + bias_data[i]; + sum = arm_nn_requantize_s64(acc_64, reduced_multiplier, output_shift[i]); + } + else + { + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + } + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q15_t)sum; + } + } +#else + (void)input_data; + (void)output_data; + (void)bias_data; + (void)filter_data; + (void)buffer_a; + (void)kernel_x; + (void)kernel_y; + (void)pad_x; + (void)pad_y; + (void)stride_x; + (void)stride_y; + (void)out_activation_min; + (void)out_activation_max; + (void)output_mult; + (void)output_shift; + return ARM_MATH_ARGUMENT_ERROR; +#endif + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_fast_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c new file mode 100644 index 0000000..9702575 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s16.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s16.c + * Description: s16 version of convolution using symmetric quantization. + * + * $Date: January 13, 2022 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s16 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ + (void)bias_dims; + (void)ctx; + + const int32_t input_batches = input_dims->n; + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_ch = output_dims->c; + + const int32_t pad_x = conv_params->padding.w; + const int32_t pad_y = conv_params->padding.h; + const int32_t stride_x = conv_params->stride.w; + const int32_t stride_y = conv_params->stride.h; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (int32_t i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i_out_ch]); + + for (int32_t base_idx_y = -pad_y, i_out_y = 0; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int32_t base_idx_x = -pad_x, i_out_x = 0; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + int64_t conv_out_acc = 0; + + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_start = MAX(0, start_y_max); + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_start = MAX(0, start_x_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + const int32_t ker_y_end = MIN(kernel_y, end_min_y); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + const int32_t ker_x_end = MIN(kernel_x, end_min_x); + + for (int32_t i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + for (int32_t i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t in_row = base_idx_y + dilation_y * i_ker_y; + const int32_t in_col = base_idx_x + dilation_x * i_ker_x; + + for (int32_t i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + conv_out_acc += input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] * + filter_data[i_out_ch * input_ch * kernel_y * kernel_x + + (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch]; + } + } + } + + if (bias_data) + { + conv_out_acc += bias_data[i_out_ch]; + } + + int32_t conv_out = arm_nn_requantize_s64(conv_out_acc, reduced_multiplier, output_shift[i_out_ch]); + conv_out = MAX(conv_out, out_activation_min); + conv_out = MIN(conv_out, out_activation_max); + output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int16_t)conv_out; + } + } + } + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_s16_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ + (void)input_dims; + (void)filter_dims; + return 0; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c new file mode 100644 index 0000000..e884b31 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_s8.c @@ -0,0 +1,335 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_s8.c + * Description: s8 version of convolution using symmetric quantization. + * + * $Date: December 14, 2021 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Basic s8 convolution function. + * + * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels + * are multiples of 4 or atleast greater than 4. + * + */ + +arm_status arm_convolve_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + + if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q15_t *buffer_a = (q15_t *)ctx->buf; + + const int32_t input_batches = input_dims->n; + const uint16_t input_x = input_dims->w; + const uint16_t input_y = input_dims->h; + const uint16_t input_ch = input_dims->c; + const uint16_t kernel_x = filter_dims->w; + const uint16_t kernel_y = filter_dims->h; + const uint16_t output_x = output_dims->w; + const uint16_t output_y = output_dims->h; + const uint16_t output_ch = output_dims->c; + + const uint16_t pad_x = conv_params->padding.w; + const uint16_t pad_y = conv_params->padding.h; + const uint16_t stride_x = conv_params->stride.w; + const uint16_t stride_y = conv_params->stride.h; + + const int32_t input_offset = conv_params->input_offset; + const int32_t out_offset = conv_params->output_offset; + const int32_t out_activation_min = conv_params->activation.min; + const int32_t out_activation_max = conv_params->activation.max; + int32_t *output_mult = quant_params->multiplier; + int32_t *output_shift = quant_params->shift; + + int i_batch; + for (i_batch = 0; i_batch < input_batches; i_batch++) + { +#if defined(ARM_MATH_MVEI) + /* Generate upto four columns from the input tensor a GEMM computation */ + q7_t *im2col_buf = (q7_t *)buffer_a; + q7_t *out = output_data; + int32_t buffer_fill_cnt = 0; + int32_t padded = 0; + const int32_t num_elem = kernel_x * kernel_y * input_ch; + const int32_t dilation_x = conv_params->dilation.w; + const int32_t dilation_y = conv_params->dilation.h; + + /* This part implements the im2col function */ + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + + for (int32_t i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (int32_t i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + memset(im2col_buf, (int8_t)-input_offset, sizeof(q7_t) * input_ch); + padded = 1; + } + else + { + arm_memcpy_q7(im2col_buf, input_data + (k_y * input_x + k_x) * input_ch, input_ch); + } + im2col_buf += input_ch; + } + } + + buffer_fill_cnt++; + + /* Computation is filed for every 4 columns */ + if (buffer_fill_cnt == 4 && (padded == 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mul_core_4x_s8(num_elem, + num_elem, + (q7_t *)buffer_a, + filter_data, + output_ch, + conv_params, + quant_params, + bias_data, + out); + im2col_buf = (q7_t *)buffer_a; + } + else if (buffer_fill_cnt == 4 && (padded != 0)) + { + buffer_fill_cnt = 0; + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + 4, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + + im2col_buf = (q7_t *)buffer_a; + padded = 0; + } + } + } + /* Handle left over columns */ + if (buffer_fill_cnt != 0) + { + out = arm_nn_mat_mult_s8(filter_data, + (q7_t *)buffer_a, + output_ch, + buffer_fill_cnt, + output_shift, + output_mult, + out_offset, + input_offset, + 0, + out_activation_min, + out_activation_max, + num_elem, + bias_data, + out); + } +#else // #if defined(ARM_MATH_MVEI) + const uint16_t dilation_x = conv_params->dilation.w; + const uint16_t dilation_y = conv_params->dilation.h; + + int32_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* Generate two columns from the input tensor a GEMM computation */ + q15_t *two_column_buf = buffer_a; + q7_t *out = output_data; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < output_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int32_t base_idx_y = stride_y * i_out_y - pad_y; + const int32_t base_idx_x = stride_x * i_out_x - pad_x; + + for (i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t k_y = base_idx_y + dilation_y * i_ker_y; + const int32_t k_x = base_idx_x + dilation_x * i_ker_x; + + if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x) + { + /* Filling 0 for out-of-bound paddings */ + memset(two_column_buf, 0, sizeof(q15_t) * input_ch); + } + else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_with_offset( + input_data + (k_y * input_x + k_x) * input_ch, two_column_buf, input_ch, input_offset); + } + two_column_buf += input_ch; + } + } + + /* Computation is filed for every 2 columns */ + if (two_column_buf == buffer_a + 2 * input_ch * kernel_y * kernel_x) + { + out = arm_nn_mat_mult_kernel_s8_s16(filter_data, + buffer_a, + output_ch, + output_shift, + output_mult, + out_offset, + out_activation_min, + out_activation_max, + input_ch * kernel_y * kernel_x, + bias_data, + out); + + /* counter reset */ + two_column_buf = buffer_a; + } + } + } + + /* left-over because odd number of output pixels */ + if (two_column_buf != buffer_a) + { + const q7_t *ker_a = filter_data; + int i; + + for (i = 0; i < output_ch; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = 0; + if (bias_data) + { + sum = bias_data[i]; + } + + /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */ + const q15_t *ip_as_col = buffer_a; + + /* 4 multiply and accumulates are done in one loop. */ +#if defined(ARM_MATH_DSP) + uint16_t col_count = (input_ch * kernel_y * kernel_x) >> 2; + + while (col_count) + { + q31_t ker_a1, ker_a2; + q31_t ip_b1, ip_b2; + + ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2); + + ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a1, ip_b1, sum); + ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col); + sum = __SMLAD(ker_a2, ip_b2, sum); + + col_count--; + } + /* Handle left over mac */ + col_count = input_ch * kernel_y * kernel_x & 0x3; +#else + uint16_t col_count = input_ch * kernel_y * kernel_x; +#endif + while (col_count) + { + q7_t ker_a1 = *ker_a++; + q15_t ip_b1 = *ip_as_col++; + sum += ker_a1 * ip_b1; + col_count--; + } + + sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]); + sum += out_offset; + sum = MAX(sum, out_activation_min); + sum = MIN(sum, out_activation_max); + *out++ = (q7_t)sum; + } + } +#endif // #if defined(ARM_MATH_MVEI) + /* Advance to the next batch */ + input_data += (input_x * input_y * input_ch); + output_data += (output_x * output_y * output_ch); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_convolve_s8_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + int32_t col_length = input_dims->c * filter_dims->w * filter_dims->h; + // Get number of complete int16 lanes(multiple of 8) for given col_length. This is dependent on + // implementation of arm_nn_mat_mult_s8 + col_length = (col_length + 7) / 8; + // 4 -> number of im2col buffers, 8 -> 8 elements per Q register + return 4 * col_length * 8 * (int32_t)sizeof(int8_t); +#else + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t); +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c new file mode 100644 index 0000000..75bb26f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s16.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2021-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s16.c + * Description: s16 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 13 January 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_wrapper_s16(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int64_t *bias_data, + const cmsis_nn_dims *output_dims, + q15_t *output_data) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +#else + return arm_convolve_s16(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); +#endif +} + +int32_t arm_convolve_wrapper_s16_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)conv_params; + (void)output_dims; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + if (filter_dims->w * filter_dims->h * input_dims->c < 512 && + (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_fast_s16_get_buffer_size(input_dims, filter_dims); + } + + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#else + return arm_convolve_s16_get_buffer_size(input_dims, filter_dims); +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c new file mode 100644 index 0000000..bf1cd70 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_wrapper_s8.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_wrapper_s8.c + * Description: s8 convolution layer wrapper function with the main purpose to call the optimal kernel available in + * cmsis-nn to perform the convolution. + * + * $Date: 02. December 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Convolution layer + * + * Refer header file for details. + * + */ + +arm_status arm_convolve_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *filter_dims, + const q7_t *filter_data, + const cmsis_nn_dims *bias_dims, + const int32_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && + (filter_dims->h == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1_x_n_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } + else + { + return arm_convolve_s8(ctx, + conv_params, + quant_params, + input_dims, + input_data, + filter_dims, + filter_data, + bias_dims, + bias_data, + output_dims, + output_data); + } +} + +int32_t arm_convolve_wrapper_s8_get_buffer_size(const cmsis_nn_conv_params *conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + if ((conv_params->padding.w == 0) && (conv_params->padding.h == 0) && (input_dims->c % 4 == 0) && + (conv_params->stride.w == 1) && (conv_params->stride.h == 1) && (filter_dims->w == 1) && + (filter_dims->h == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1x1_s8_fast_get_buffer_size(input_dims); + } + else if ((output_dims->h == 1) && (input_dims->h == 1) && (filter_dims->h == 1) && (output_dims->w % 4 == 0) && + (input_dims->n == 1) && (conv_params->dilation.w == 1 && conv_params->dilation.h == 1)) + { + return arm_convolve_1_x_n_s8_get_buffer_size(input_dims, filter_dims); + } + else + { + return arm_convolve_s8_get_buffer_size(input_dims, filter_dims); + } +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c new file mode 100644 index 0000000..d5569b3 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_3x3_s8.c @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_3x3_s8.c + * Description: Optimized s8 depthwise convolution function for channel + * multiplier of 1 and 3x3 kernel size. + * + * $Date: 09. October 2020 + * $Revision: V.2.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that + * in_channel == out_channel and kernel_x == kernel_y == 3 with pads at most 1 + * + * Refer prototype header file for details. + * + */ + +arm_status arm_depthwise_conv_3x3_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)ctx; + (void)bias_dims; + + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_MATH_SIZE_MISMATCH; + } + /* Check input constraints pad_x <= 1 */ + if (pad_x > 1 || filter_dims->w != 3 || filter_dims->h != 3) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + int32_t in_ch = 0; + int32_t ker_w_start = MAX(0, -in_w); + + for (; in_ch <= (input_ch - 4); in_ch += 4) + { + int32_t out_buff0 = bias[in_ch + 0]; + int32_t out_buff1 = bias[in_ch + 1]; + int32_t out_buff2 = bias[in_ch + 2]; + int32_t out_buff3 = bias[in_ch + 3]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + int32_t in_val = 0; + int32_t ker_val = 0; + + if (ker_w_start == 0) + { + in_val = arm_nn_read_q7x4(input_ptr); + ker_val = arm_nn_read_q7x4(kernel_ptr); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + in_val = arm_nn_read_q7x4(input_ptr + input_ch); + ker_val = arm_nn_read_q7x4(kernel_ptr + input_ch); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + + if ((input_x - in_w) >= 3) + { + in_val = arm_nn_read_q7x4(input_ptr + (input_ch << 1)); + ker_val = arm_nn_read_q7x4(kernel_ptr + (input_ch << 1)); + + out_buff0 += ((int8_t)in_val + input_offset) * (int8_t)ker_val; + out_buff1 += ((int8_t)(in_val >> 8) + input_offset) * (int8_t)(ker_val >> 8); + out_buff2 += ((int8_t)(in_val >> 16) + input_offset) * (int8_t)(ker_val >> 16); + out_buff3 += ((int8_t)(in_val >> 24) + input_offset) * (int8_t)(ker_val >> 24); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff0 = arm_nn_requantize(out_buff0, output_mult[in_ch + 0], output_shift[in_ch + 0]); + out_buff1 = arm_nn_requantize(out_buff1, output_mult[in_ch + 1], output_shift[in_ch + 1]); + out_buff2 = arm_nn_requantize(out_buff2, output_mult[in_ch + 2], output_shift[in_ch + 2]); + out_buff3 = arm_nn_requantize(out_buff3, output_mult[in_ch + 3], output_shift[in_ch + 3]); + + out_buff0 += output_offset; + out_buff1 += output_offset; + out_buff2 += output_offset; + out_buff3 += output_offset; + + out_buff0 = MIN(MAX(out_buff0, output_activation_min), output_activation_max); + out_buff1 = MIN(MAX(out_buff1, output_activation_min), output_activation_max); + out_buff2 = MIN(MAX(out_buff2, output_activation_min), output_activation_max); + out_buff3 = MIN(MAX(out_buff3, output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff0; + output[out_idx++] = (int8_t)out_buff1; + output[out_idx++] = (int8_t)out_buff2; + output[out_idx++] = (int8_t)out_buff3; + } + + // Leftover + for (; in_ch < input_ch; ++in_ch) + { + int32_t out_buff = bias[in_ch]; + + const int8_t *input_ptr = input + (in_h + ker_h_start) * (input_ch * input_x) + in_w * input_ch + in_ch; + const int8_t *kernel_ptr = kernel + ker_h_start * (input_ch * 3) + in_ch; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(3, input_y - in_h); ++ker_h) + { + if (ker_w_start == 0) + { + out_buff += (*(input_ptr) + input_offset) * *(kernel_ptr); + } + + out_buff += (*(input_ptr + input_ch) + input_offset) * *(kernel_ptr + input_ch); + + if ((input_x - in_w) >= 3) + { + out_buff += (*(input_ptr + (input_ch << 1)) + input_offset) * *(kernel_ptr + (input_ch << 1)); + } + + input_ptr += (input_ch * input_x); + kernel_ptr += (input_ch * 3); + } + + out_buff = arm_nn_requantize(out_buff, output_mult[in_ch], output_shift[in_ch]); + out_buff += output_offset; + out_buff = MIN(MAX(out_buff, output_activation_min), output_activation_max); + output[out_idx++] = (int8_t)out_buff; + } + } + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c new file mode 100644 index 0000000..42e4bbd --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s16.c @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s16.c + * Description: s16 version of depthwise convolution. + * + * $Date: 26. Jan 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void __attribute__((unused)) depthwise_conv_s16_mult_4_s16(const int16_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff32[4] = {REDUCE_MULTIPLIER(output_mult[out_ch + 0 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 1 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 2 + mult_tile]), + REDUCE_MULTIPLIER(output_mult[out_ch + 3 + mult_tile])}; + + int64_t out_buff[4] = {0, 0, 0, 0}; + + if (bias) + { + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + // TODO: Unroll of 4 with 64 bit accumulator will probably result in too much register + // spills. Try with unroll of 2 when enabling this. + int32_t in_val = input[in_idx + ker_w * input_ch]; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } + + out_buff32[0] = + arm_nn_requantize_s64(out_buff[0], out_buff32[0], output_shift[out_ch + 0 + mult_tile]); + out_buff32[1] = + arm_nn_requantize_s64(out_buff[1], out_buff32[1], output_shift[out_ch + 1 + mult_tile]); + out_buff32[2] = + arm_nn_requantize_s64(out_buff[2], out_buff32[2], output_shift[out_ch + 2 + mult_tile]); + out_buff32[3] = + arm_nn_requantize_s64(out_buff[3], out_buff32[3], output_shift[out_ch + 3 + mult_tile]); + + out_buff32[0] = MIN(MAX(out_buff32[0], output_activation_min), output_activation_max); + out_buff32[1] = MIN(MAX(out_buff32[1], output_activation_min), output_activation_max); + out_buff32[2] = MIN(MAX(out_buff32[2], output_activation_min), output_activation_max); + out_buff32[3] = MIN(MAX(out_buff32[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int16_t)out_buff32[0]; + output[out_idx++] = (int16_t)out_buff32[1]; + output[out_idx++] = (int16_t)out_buff32[2]; + output[out_idx++] = (int16_t)out_buff32[3]; + } + } + } + } +} + +static void depthwise_conv_s16_generic_s16(const int16_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const int8_t *kernel, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int64_t *bias, + int16_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[idx_out_ch]); + int64_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += input[idx_0] * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + int32_t result = arm_nn_requantize_s64(acc_0, reduced_multiplier, output_shift[idx_out_ch]); + result = MAX(result, output_activation_min); + result = MIN(result, output_activation_max); + *output++ = (int16_t)result; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s16 depthwise convolution function. + * + * Refer header file for details. + * + */ +arm_status arm_depthwise_conv_s16(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)bias_dims; + (void)ctx; + + depthwise_conv_s16_generic_s16(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c new file mode 100644 index 0000000..297b7af --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8.c @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8.c + * Description: s8 version of depthwise convolution. + * + * $Date: 30. Dec 2021 + * $Revision: V.2.7.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_s8_mult_4(const int8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const int8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + int8_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4] = {0, 0, 0, 0}; + if (bias) + { + out_buff[0] = bias[out_ch + 0 + mult_tile]; + out_buff[1] = bias[out_ch + 1 + mult_tile]; + out_buff[2] = bias[out_ch + 2 + mult_tile]; + out_buff[3] = bias[out_ch + 3 + mult_tile]; + } + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang loop unroll(disable) +#endif + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * kernel[ker_idx + 0 + mult_tile]; + out_buff[1] += in_val * kernel[ker_idx + 1 + mult_tile]; + out_buff[2] += in_val * kernel[ker_idx + 2 + mult_tile]; + out_buff[3] += in_val * kernel[ker_idx + 3 + mult_tile]; + } + } +#if defined(ARM_MATH_MVEI) + (void)out_idx; + int32x4_t res = vldrwq_s32(out_buff); + res = arm_requantize_mve_32x4(res, + vldrwq_s32(&output_mult[out_ch + mult_tile]), + vldrwq_s32(&output_shift[out_ch + mult_tile])); + res = vaddq_n_s32(res, output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(output_activation_min)); + res = vminq_s32(res, vdupq_n_s32(output_activation_max)); + vstrbq_s32(output, res); + output += 4; +#else + out_buff[0] = arm_nn_requantize( + out_buff[0], output_mult[out_ch + 0 + mult_tile], output_shift[out_ch + 0 + mult_tile]); + out_buff[1] = arm_nn_requantize( + out_buff[1], output_mult[out_ch + 1 + mult_tile], output_shift[out_ch + 1 + mult_tile]); + out_buff[2] = arm_nn_requantize( + out_buff[2], output_mult[out_ch + 2 + mult_tile], output_shift[out_ch + 2 + mult_tile]); + out_buff[3] = arm_nn_requantize( + out_buff[3], output_mult[out_ch + 3 + mult_tile], output_shift[out_ch + 3 + mult_tile]); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (int8_t)out_buff[0]; + output[out_idx++] = (int8_t)out_buff[1]; + output[out_idx++] = (int8_t)out_buff[2]; + output[out_idx++] = (int8_t)out_buff[3]; + +#endif + } + } + } + } +} + +static void depthwise_conv_s8_generic(const q7_t *input, + const uint16_t input_batches, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const q7_t *kernel, + const uint16_t output_ch, + const uint16_t ch_mult, + const uint16_t kernel_x, + const uint16_t kernel_y, + const uint16_t pad_x, + const uint16_t pad_y, + const uint16_t stride_x, + const uint16_t stride_y, + const int32_t *bias, + q7_t *output, + const int32_t *output_shift, + const int32_t *output_mult, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t output_activation_min, + const int32_t output_activation_max, + const uint16_t dilation_x, + const uint16_t dilation_y) + +{ + (void)output_ch; + int i_out = 0; + int i_batch; + + for (i_batch = 0; i_batch < input_batches; i_batch++) + { + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0 = 0; + + int ker_y_start; + int ker_x_start; + int ker_y_end; + int ker_x_end; + + if (dilation_x > 1) + { + const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x; + ker_x_start = MAX(0, start_x_max); + const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x; + ker_x_end = MIN(kernel_x, end_min_x); + } + else + { + ker_x_start = MAX(0, -base_idx_x); + ker_x_end = MIN(kernel_x, input_x - base_idx_x); + } + + if (dilation_y > 1) + { + const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y; + ker_y_start = MAX(0, start_y_max); + const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y; + ker_y_end = MIN(kernel_y, end_min_y); + } + else + { + ker_y_start = MAX(0, -base_idx_y); + ker_y_end = MIN(kernel_y, input_y - base_idx_y); + } + + if (bias) + { + acc_0 = bias[idx_out_ch]; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + dilation_y * i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + dilation_x * i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * kernel[ker_idx_0]; + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult[idx_out_ch], output_shift[idx_out_ch]); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } + /* Advance to the next batch */ + input += (input_x * input_y * input_ch); + } +} + +/* + * Basic s8 depthwise convolution function. + * + * Refer header file for details. + * Optimization using DSP extension is not available for the generic case where channel multiplier is > 1. + * + */ +arm_status arm_depthwise_conv_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + const uint16_t dilation_x = dw_conv_params->dilation.w; + const uint16_t dilation_y = dw_conv_params->dilation.h; + + (void)dw_conv_params->dilation; + (void)bias_dims; + (void)ctx; + + if (dw_conv_params->ch_mult % 4 == 0 && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + depthwise_conv_s8_mult_4(input, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max); + } + else + { + depthwise_conv_s8_generic(input, + input_dims->n, + input_dims->w, + input_dims->h, + input_dims->c, + kernel, + output_dims->c, + dw_conv_params->ch_mult, + filter_dims->w, + filter_dims->h, + dw_conv_params->padding.w, + dw_conv_params->padding.h, + dw_conv_params->stride.w, + dw_conv_params->stride.h, + bias, + output, + quant_params->shift, + quant_params->multiplier, + output_dims->w, + output_dims->h, + dw_conv_params->output_offset, + dw_conv_params->input_offset, + dw_conv_params->activation.min, + dw_conv_params->activation.max, + dilation_x, + dilation_y); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c new file mode 100644 index 0000000..1edac04 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_s8_opt.c @@ -0,0 +1,433 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_s8_opt.c + * Description: Optimized s8 depthwise separable convolution function for + * channel multiplier of 1. + * + * $Date: January 26, 2021 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * Optimized s8 depthwise convolution function with constraint that in_channel equals out_channel + * + * Refer prototype header file for details. + * + */ + +arm_status arm_depthwise_conv_s8_opt(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + + const int32_t input_ch = input_dims->c; + const int32_t output_ch = output_dims->c; + + /* Check input constraints input_ch == output_ch */ + if (input_ch != output_ch) + { + return ARM_MATH_SIZE_MISMATCH; + } + + if (ctx->buf == NULL && arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims) > 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } +#ifdef ARM_MATH_DSP + const int32_t input_x = input_dims->w; + const int32_t input_y = input_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t kernel_y = filter_dims->h; + const int32_t pad_x = dw_conv_params->padding.w; + const int32_t pad_y = dw_conv_params->padding.h; + const int32_t stride_x = dw_conv_params->stride.w; + const int32_t stride_y = dw_conv_params->stride.h; + const int32_t *output_shift = quant_params->shift; + const int32_t *output_mult = quant_params->multiplier; + const int32_t output_x = output_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_offset = dw_conv_params->output_offset; + const int32_t input_offset = dw_conv_params->input_offset; + const int32_t output_activation_min = dw_conv_params->activation.min; + const int32_t output_activation_max = dw_conv_params->activation.max; + q15_t *buffer_a = (q15_t *)ctx->buf; + +#ifdef ARM_MATH_MVEI + (void)bias_dims; + /* Generate two columns from the input tensor */ + q7_t *lhs_buffer = (q7_t *)buffer_a; + q7_t *out = output; + int padded = 0; + int buffer_count = 0; + const int32_t kernel_size = kernel_x * kernel_y; + + /* This part implements the im2col function */ + for (int i_out_y = 0, base_idx_y = -pad_y; i_out_y < output_y; base_idx_y += stride_y, i_out_y++) + { + for (int i_out_x = 0, base_idx_x = -pad_x; i_out_x < output_x; base_idx_x += stride_x, i_out_x++) + { + for (int i_ker_y = base_idx_y; i_ker_y < base_idx_y + kernel_y; i_ker_y++) + { + for (int i_ker_x = base_idx_x; i_ker_x < base_idx_x + kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x) + { + arm_memset_q7(lhs_buffer, (int8_t)-input_offset, (uint32_t)input_ch); + padded = 1; + } + else + { + arm_memcpy_q7(lhs_buffer, input + (i_ker_y * input_x + i_ker_x) * input_ch, (uint32_t)input_ch); + } + lhs_buffer += input_ch; + } + } + buffer_count++; + + if (buffer_count == 4) + { + lhs_buffer = (q7_t *)buffer_a; + if (padded == 0) + { + out = arm_nn_depthwise_conv_nt_t_s8(lhs_buffer, + kernel, + input_offset, + input_ch, + output_shift, + output_mult, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias, + out); + } + else + { + out = arm_nn_depthwise_conv_nt_t_padded_s8(lhs_buffer, + kernel, + input_offset, + input_ch, + output_shift, + output_mult, + output_offset, + output_activation_min, + output_activation_max, + kernel_size, + bias, + out); + padded = 0; + } + buffer_count = 0; + } + } + } + + /* Handle left over buffers */ + lhs_buffer = (q7_t *)buffer_a; + + for (int i_buf = 0; i_buf < buffer_count; i_buf++) + { + int32_t loop_count = (input_ch + 3) / 4; + + int32_t num_ch_to_process = input_ch; + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; num_ch_to_process -= 4, offset += 4, i_loop_cnt++) + { + const int8_t *col_0 = lhs_buffer + (kernel_size * input_ch * i_buf) + offset; + const int8_t *row_0 = kernel + offset; + int32x4_t out_0 = vldrwq_s32(&bias[offset]); + + for (int i_ker = 0; i_ker < kernel_size; i_ker++) + { + const int32x4_t ker_0 = vldrbq_s32(row_0); + + int32x4_t ip_0 = vldrbq_s32(col_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + col_0 += input_ch; + row_0 += input_ch; + } + + const int32x4_t mult = vldrwq_s32(&output_mult[offset]); + const int32x4_t shift = vldrwq_s32(&output_shift[offset]); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, output_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(output_activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(output_activation_max)); + mve_pred16_t p = vctp32q((uint32_t)num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out += 4; + } + + const int tail_ch = input_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + } + +#else // ARM_MATH_DSP + (void)bias_dims; + /* Run the following code in cores using DSP extension */ + q15_t *const col_buffer_start = buffer_a; + q15_t *col_buffer = col_buffer_start; + const int32_t *const bias_start_pos = bias; + const q31_t *const out_mult_start_pos = output_mult; + const q31_t *const out_shift_start_pos = output_shift; + uint16_t row_count; + uint16_t row_shift; + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + + /* Out of bounds is only considered for the y axis as it provides a contiguous zero'ing opportunity than + along the x axis */ + const int ker_y_start = MAX(0, -base_idx_y); + /* Condition for kernel end dimension: (base_idx_y + ker_y_end) < input_y */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + + int32_t index = 0; + if (ker_y_start != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * ker_y_start * sizeof(q15_t)); + index += (kernel_x * input_ch) * ker_y_start; + } + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + if (idx_x < 0 || idx_x >= input_x) + { + memset(&col_buffer[index], 0, input_ch * sizeof(q15_t)); + } + else + { + arm_q7_to_q15_with_offset((q7_t *)input + (idx_y * input_x + idx_x) * input_ch, + &col_buffer[index], + input_ch, + input_offset); + } + index += input_ch; + } + } + + const int diff = kernel_y - ker_y_end; + if (diff != 0) + { + memset(&col_buffer[index], 0, (kernel_x * input_ch) * diff * sizeof(q15_t)); + } + + row_count = output_ch / 4; + row_shift = 0; + bias = bias_start_pos; + output_mult = out_mult_start_pos; + output_shift = out_shift_start_pos; + + while (row_count) + { + q31_t sum = *bias++; + q31_t sum_2 = *bias++; + q31_t sum_3 = *bias++; + q31_t sum_4 = *bias++; + + uint16_t col_count = (kernel_x * kernel_y) / 2; + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + row_shift += 4; + + while (col_count) + { + /* General idea is to read 4 + 4 (input, kernel) pair and re-arrange them in the right order to + use in a SMLAD instruction . One run of this loop produces 4 partial outputs with 8 MACs. */ + /* Note: variable names can be improved here to align with rows and columns. */ + q31_t ip_a1, ip_a2, ip_b1, ip_b2, op_a, op_b, op_c; + /* Read 4 weights */ + ip_b1 = arm_nn_read_q7x4(row_pos); + ip_a1 = arm_nn_read_q7x4(row_pos + input_ch); + op_a = arm_nn_read_q15x2(col_pos); + op_b = arm_nn_read_q15x2(col_pos + input_ch); + + ip_a2 = __SXTB16(ip_b1); + ip_b1 = __SXTB16(__ROR(ip_b1, 8)); + + ip_b2 = __SXTB16(ip_a1); + ip_a1 = __SXTB16(__ROR(ip_a1, 8)); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHBT(ip_b2, ip_a2, 16); + sum = __SMLAD(op_c, op_b, sum); + + op_b = __PKHBT(ip_b1, ip_a1, 16); + sum_2 = __SMLAD(op_a, op_b, sum_2); + + op_a = arm_nn_read_q15x2(col_pos + 2); + op_b = arm_nn_read_q15x2(col_pos + input_ch + 2); + + op_c = __PKHBT(op_b, op_a, 16); + op_a = __PKHTB(op_b, op_a, 16); + op_b = __PKHTB(ip_a2, ip_b2, 16); + sum_3 = __SMLAD(op_c, op_b, sum_3); + + op_b = __PKHTB(ip_a1, ip_b1, 16); + sum_4 = __SMLAD(op_a, op_b, sum_4); + + row_pos += input_ch << 1; + col_pos += input_ch << 1; + col_count--; + } + + col_count = (kernel_x * kernel_y) & 0x1; + while (col_count) + { + sum += row_pos[0] * col_pos[0]; + sum_2 += row_pos[1] * col_pos[1]; + sum_3 += row_pos[2] * col_pos[2]; + sum_4 += row_pos[3] * col_pos[3]; + + row_pos += input_ch; + col_pos += input_ch; + + col_count--; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + sum_2 = arm_nn_requantize(sum_2, *output_mult++, *output_shift++); + sum_2 += output_offset; + sum_2 = MAX(sum_2, output_activation_min); + sum_2 = MIN(sum_2, output_activation_max); + *output++ = (q7_t)sum_2; + sum_3 = arm_nn_requantize(sum_3, *output_mult++, *output_shift++); + sum_3 += output_offset; + sum_3 = MAX(sum_3, output_activation_min); + sum_3 = MIN(sum_3, output_activation_max); + *output++ = (q7_t)sum_3; + + sum_4 = arm_nn_requantize(sum_4, *output_mult++, *output_shift++); + sum_4 += output_offset; + sum_4 = MAX(sum_4, output_activation_min); + sum_4 = MIN(sum_4, output_activation_max); + *output++ = (q7_t)sum_4; + + row_count--; + } + + row_count = output_ch & 0x3; + while (row_count) + { + q15_t *col_pos = col_buffer_start + row_shift; + const q7_t *row_pos = kernel + row_shift; + q31_t sum = *bias++; + const uint16_t col_count = (kernel_x * kernel_y); + row_shift += 1; + + for (int i = 0; i < col_count; i++) + { + sum += row_pos[i * input_ch] * col_pos[i * input_ch]; + } + sum = arm_nn_requantize(sum, *output_mult++, *output_shift++); + sum += output_offset; + sum = MAX(sum, output_activation_min); + sum = MIN(sum, output_activation_max); + *output++ = (q7_t)sum; + + row_count--; + } + + // clear counter and pointers + col_buffer = col_buffer_start; + } + } +#endif +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + return arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + kernel, + bias_dims, + bias, + output_dims, + output); +#endif /* ARM_MATH_MVEI | ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +int32_t arm_depthwise_conv_s8_opt_get_buffer_size(const cmsis_nn_dims *input_dims, const cmsis_nn_dims *filter_dims) +{ +#if defined(ARM_MATH_MVEI) + /* The + 4 accounts for out of bounds read of the lhs buffers in the *_nt_t_* functions. */ + return (2 * input_dims->c * filter_dims->w * filter_dims->h) * (int32_t)sizeof(int16_t) + 4; +#elif defined(ARM_MATH_DSP) + return (input_dims->c * filter_dims->w * filter_dims->h) * sizeof(int16_t); +#else + (void)input_dims; + (void)filter_dims; + return 0; +#endif +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 0000000..c9d0afc --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: 09. October 2020 + * $Revision: V.1.1.1 + * + * Target : Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +static void depthwise_conv_u8_mult_4(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + for (int32_t in_h = -pad_y, out_h = 0, out_idx = 0; out_h < output_y; in_h += stride_y, ++out_h) + { + for (int32_t in_w = -pad_x, out_w = 0, ker_h_start = MAX(0, -in_h); out_w < output_x; in_w += stride_x, ++out_w) + { + for (int32_t in_ch = 0, out_ch = 0, ker_w_start = MAX(0, -in_w); out_ch < output_ch; + ++in_ch, out_ch += ch_mult) + { + for (int mult_tile = 0; mult_tile < ch_mult; mult_tile += 4) + { + int32_t out_buff[4]; + + out_buff[0] = 0; + out_buff[1] = 0; + out_buff[2] = 0; + out_buff[3] = 0; + + for (int32_t ker_h = ker_h_start; ker_h < MIN(kernel_y, input_y - in_h); ++ker_h) + { + int32_t ker_idx = ker_h * (output_ch * kernel_x) + ker_w_start * output_ch + out_ch; + int32_t in_idx = (in_h + ker_h) * (input_ch * input_x) + in_w * input_ch + in_ch; + + for (int32_t ker_w = ker_w_start; ker_w < MIN(kernel_x, input_x - in_w); + ++ker_w, ker_idx += output_ch) + { + int32_t in_val = input[in_idx + ker_w * input_ch] + input_offset; + out_buff[0] += in_val * (kernel[ker_idx + 0 + mult_tile] + filter_offset); + out_buff[1] += in_val * (kernel[ker_idx + 1 + mult_tile] + filter_offset); + out_buff[2] += in_val * (kernel[ker_idx + 2 + mult_tile] + filter_offset); + out_buff[3] += in_val * (kernel[ker_idx + 3 + mult_tile] + filter_offset); + } + } + + if (bias != NULL) + { + out_buff[0] += bias[out_ch + 0 + mult_tile]; + out_buff[1] += bias[out_ch + 1 + mult_tile]; + out_buff[2] += bias[out_ch + 2 + mult_tile]; + out_buff[3] += bias[out_ch + 3 + mult_tile]; + } + out_buff[0] = arm_nn_requantize(out_buff[0], output_mult, output_shift); + out_buff[1] = arm_nn_requantize(out_buff[1], output_mult, output_shift); + out_buff[2] = arm_nn_requantize(out_buff[2], output_mult, output_shift); + out_buff[3] = arm_nn_requantize(out_buff[3], output_mult, output_shift); + + out_buff[0] += output_offset; + out_buff[1] += output_offset; + out_buff[2] += output_offset; + out_buff[3] += output_offset; + + out_buff[0] = MIN(MAX(out_buff[0], output_activation_min), output_activation_max); + out_buff[1] = MIN(MAX(out_buff[1], output_activation_min), output_activation_max); + out_buff[2] = MIN(MAX(out_buff[2], output_activation_min), output_activation_max); + out_buff[3] = MIN(MAX(out_buff[3], output_activation_min), output_activation_max); + + output[out_idx++] = (uint8_t)out_buff[0]; + output[out_idx++] = (uint8_t)out_buff[1]; + output[out_idx++] = (uint8_t)out_buff[2]; + output[out_idx++] = (uint8_t)out_buff[3]; + } + } + } + } +} + +static void depthwise_conv_u8_generic(const uint8_t *input, + const int32_t input_x, + const int32_t input_y, + const int32_t input_ch, + const uint8_t *kernel, + const int32_t output_ch, + const int32_t ch_mult, + const int32_t kernel_x, + const int32_t kernel_y, + const int32_t pad_x, + const int32_t pad_y, + const int32_t stride_x, + const int32_t stride_y, + const int32_t *bias, + uint8_t *output, + const int32_t output_shift, + const int32_t output_mult, + const int32_t output_x, + const int32_t output_y, + const int32_t output_offset, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_activation_min, + const int32_t output_activation_max) +{ + (void)output_ch; + int i_out = 0; + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + int32_t acc_0; + /* Condition for kernel start dimension: (base_idx_ + ker__start) >= 0 */ + const int ker_y_start = MAX(0, -base_idx_y); + const int ker_x_start = MAX(0, -base_idx_x); + /* Condition for kernel end dimension: (base_idx_ + ker__end) < input_ */ + const int ker_y_end = MIN(kernel_y, input_y - base_idx_y); + const int ker_x_end = MIN(kernel_x, input_x - base_idx_x); + acc_0 = 0; + + for (int i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y; + for (int i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x; + int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + int32_t ker_idx_0 = (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + + acc_0 += (input[idx_0] + input_offset) * (kernel[ker_idx_0] + filter_offset); + } + } + if (bias != NULL) + { + acc_0 += bias[idx_out_ch]; + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_requantize(acc_0, output_mult, output_shift); + acc_0 += output_offset; + acc_0 = MAX(acc_0, output_activation_min); + acc_0 = MIN(acc_0, output_activation_max); + + output[i_out++] = acc_0; + } + } + } + } +} + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * available, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_shift Amount of right-shift for output + * @param[in] output_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * + */ + +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t output_shift, + const int32_t output_mult) +{ + (void)dilation_x; + (void)dilation_y; + + if (ch_mult % 4 == 0) + { + depthwise_conv_u8_mult_4(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + else + { + depthwise_conv_u8_generic(input, + input_x, + input_y, + input_ch, + kernel, + ch_mult * input_ch, + ch_mult, + kernel_x, + kernel_y, + pad_x, + pad_y, + stride_x, + stride_y, + bias, + output, + output_shift, + output_mult, + output_x, + output_y, + output_offset, + input_offset, + filter_offset, + output_activation_min, + output_activation_max); + } + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c new file mode 100644 index 0000000..23c8e46 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_wrapper_s8.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_wrapper_s8.c + * Description: Wrapper API to select appropriate depthwise conv API based + * on dimensions. + * + * $Date: 20. Dec 2021 + * $Revision: V.1.4.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/* + * s8 Depthwise conv wrapper function + * + * Refer header file for details. + * + */ +arm_status arm_depthwise_conv_wrapper_s8(const cmsis_nn_context *ctx, + const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *filter, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + arm_status status = ARM_MATH_SUCCESS; + if (1 == dw_conv_params->ch_mult && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { +#if !defined(ARM_MATH_MVEI) + if ((filter_dims->w == 3) && (filter_dims->h == 3) && (dw_conv_params->padding.h <= 1) && + (dw_conv_params->padding.w <= 1)) + { + status = arm_depthwise_conv_3x3_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + else +#endif + { + status = arm_depthwise_conv_s8_opt(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + } + else + { + status = arm_depthwise_conv_s8(ctx, + dw_conv_params, + quant_params, + input_dims, + input, + filter_dims, + filter, + bias_dims, + bias, + output_dims, + output); + } + + /* Return to application */ + return status; +} + +int32_t arm_depthwise_conv_wrapper_s8_get_buffer_size(const cmsis_nn_dw_conv_params *dw_conv_params, + const cmsis_nn_dims *input_dims, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims) +{ + (void)dw_conv_params; + int32_t size = 0; + + if (input_dims->c == output_dims->c && input_dims->n == 1 && dw_conv_params->dilation.w == 1 && + dw_conv_params->dilation.h == 1) + { + size = arm_depthwise_conv_s8_opt_get_buffer_size(input_dims, filter_dims); + } + + return size; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 0000000..729147f --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,422 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimension + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out, + q15_t *bufferA, + q7_t *bufferB) +{ + (void)bufferB; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 0000000..829acf9 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,427 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimension x + * @param[in] dim_im_in_y input tensor dimension y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some constraints: + * ch_im_in is equal to ch_im_out + * + */ + +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t *wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t *bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t *Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t *bufferA, + q7_t *bufferB) +{ + + (void)bufferB; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *)bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } + else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, + * ch_im_in); */ + memcpy(pBuffer, (q7_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = arm_nn_read_q7x4(pB); + pB += ch_im_in; + opB = arm_nn_read_q7x4(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = arm_nn_read_q7x4(pA); + pA += ch_im_in; + opB = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt), [ ch_im_in ] "r"(ch_im_in) + : "r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = arm_nn_read_q7x4(pA); + pA += ch_im_in; + inB.word = arm_nn_read_q7x4(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + (void)bufferA; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t)__SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c new file mode 100644 index 0000000..481eeba --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_depthwise_conv_s8_core.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_s8_core.c + * Description: Depthwise convolution on im2col buffers. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.4 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/* + * Depthwise conv on an im2col buffer where the input channel equals + * output channel. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_s8_core(const q7_t *row, + const q15_t *col, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t kernel_size, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t ch_per_loop = num_ch / 4; + + const int32_t *bias = output_bias; + int8_t *out_tmp = out; + + int32_t idx = 0; + + while (ch_per_loop > 0) + { + int32x4_t ip_0; + int32x4_t ip_1; + int32_t ker_loop = kernel_size / 3; + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + bias += 4; + + const int32_t offset = idx * 4; + const int8_t *row_0 = row + offset; + const int16_t *col_0 = col + offset; + const int16_t *col_1 = col + kernel_size * num_ch + offset; + + int32x4_t ker_0 = vldrbq_s32(row_0); + + while (ker_loop > 0) + { + const int8_t *row_1 = row_0 + num_ch; + const int8_t *row_2 = row_0 + 2 * num_ch; + const int32x4_t ker_1 = vldrbq_s32(row_1); + const int32x4_t ker_2 = vldrbq_s32(row_2); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_1); + out_1 += vmulq_s32(ip_1, ker_1); + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + col_0 += num_ch; + col_1 += num_ch; + + out_0 += vmulq_s32(ip_0, ker_2); + out_1 += vmulq_s32(ip_1, ker_2); + row_0 += 3 * num_ch; + + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + + idx++; + /* Handle tail kernel elements */ + ker_loop = kernel_size - ((kernel_size / 3) * 3); + while (ker_loop > 0) + { + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + out_0 += vmulq_s32(ip_0, ker_0); + out_1 += vmulq_s32(ip_1, ker_0); + + col_0 += num_ch; + col_1 += num_ch; + + ip_0 = vldrhq_s32(col_0); + ip_1 = vldrhq_s32(col_1); + + row_0 += num_ch; + ker_0 = vldrbq_s32(row_0); + ker_loop--; + } + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp, out_0); + + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_s32(out_tmp + num_ch, out_1); + + out_tmp += 4; + ch_per_loop--; + } + + int32_t tail_ch = num_ch & 3; + if (tail_ch != 0) + { + int32_t ch_idx = (num_ch & ~3); + int32x4_t col_0_sum; + int32x4_t col_1_sum; + + const int32_t single_buffer_size = kernel_size * num_ch; + for (int i = 0; i < tail_ch; i++) + { + const int16_t *col_pos_0 = col + ch_idx; + const int16_t *col_pos_1 = col_pos_0 + single_buffer_size; + + const int8_t *row_pos = row + ch_idx; + int32_t sum_0 = bias[i]; + int32_t sum_1 = bias[i]; + + for (int j = 0; j < kernel_size; j++) + { + const int8_t row_val = row_pos[j * num_ch]; + sum_0 += row_val * col_pos_0[j * num_ch]; + sum_1 += row_val * col_pos_1[j * num_ch]; + } + col_0_sum[i] = sum_0; + col_1_sum[i] = sum_1; + + ch_idx++; + } + const mve_pred16_t p = vctp32q((uint32_t)tail_ch); + const int32x4_t mult = vldrwq_z_s32(out_mult, p); + const int32x4_t shift = vldrwq_z_s32(out_shift, p); + + col_0_sum = arm_requantize_mve_32x4(col_0_sum, mult, shift); + col_1_sum = arm_requantize_mve_32x4(col_1_sum, mult, shift); + + col_0_sum = vaddq_n_s32(col_0_sum, out_offset); + col_0_sum = vmaxq_s32(col_0_sum, vdupq_n_s32(activation_min)); + col_0_sum = vminq_s32(col_0_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp, col_0_sum, p); + + col_1_sum = vaddq_n_s32(col_1_sum, out_offset); + col_1_sum = vmaxq_s32(col_1_sum, vdupq_n_s32(activation_min)); + col_1_sum = vminq_s32(col_1_sum, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out_tmp + num_ch, col_1_sum, p); + + out_tmp += tail_ch; + } + + return out_tmp + num_ch; +#else + (void)row; + (void)col; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)kernel_size; + (void)output_bias; + (void)out; + return NULL; +#endif +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 0000000..05c95b6 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution. + * + * @details Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + pA2 = read_and_pad(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad(pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 0000000..0870ac3 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: January 26, 2021 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @brief Matrix-multiplication function for convolution with re-ordered input. + * + * @details Refer to header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t *pA, + const q15_t *pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut) +{ + +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + + q31_t inB1 = arm_nn_read_q15x2_ia(&pB); + q31_t inB2 = arm_nn_read_q15x2_ia(&pB2); + + pA = read_and_pad_reordered(pA, &inA11, &inA12); + pA2 = read_and_pad_reordered(pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = arm_nn_read_q15x2_ia(&pB); + inB2 = arm_nn_read_q15x2_ia(&pB2); + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + (void)pA; + (void)pInBuffer; + (void)ch_im_out; + (void)numCol_A; + (void)bias_shift; + (void)out_shift; + (void)bias; + (void)pOut; + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c new file mode 100644 index 0000000..cb30068 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16.c @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s8_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 14. December 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_kernel_s8_s16(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + /* Init accumulator with bias for channel N and N + 1 */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + ch_1_out_0 = *bias; + ch_1_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + /* load the bias */ + if (bias) + { + ch_0_out_0 = *bias; + ch_0_out_1 = *bias++; + } + +#if defined(ARM_MATH_DSP) + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; +#else + uint16_t col_count = num_col_a; +#endif + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c new file mode 100644 index 0000000..842a180 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_s8_s16_reordered.c @@ -0,0 +1,201 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s8_s16_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication with re-ordered input and bias inputs for convolution with per-channel + * requantization. The re-ordering is a consequence of sign extension is done by the SXTB16 command. + * + * Refer header file for details. This function differs from arm_nn_mat_mult_kernel_s8_s16(), in that it uses + * read_and_pad_reordered() instead of arm_nn_mat_mult_kernel_s8_s16(). Investigating the cycles impact and + * unifying these two functions is a potential future improvement. + * + */ + +q7_t *arm_nn_mat_mult_kernel_s8_s16_reordered(const q7_t *input_a, + const q15_t *input_b, + const uint16_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t num_col_a, + const int32_t *const output_bias, + q7_t *out_0) +{ +#if defined(ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *out_1 = out_0 + output_ch; + const int32_t *bias = output_bias; + + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator with bias for channel N and N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = *bias++; + q31_t ch_1_out_0 = *bias; + q31_t ch_1_out_1 = *bias++; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + ip_a1 = read_and_pad_reordered(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + out_mult++; + out_shift++; + + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_0 += out_offset; + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q7_t)ch_1_out_0; + + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + ch_1_out_1 += out_offset; + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q7_t)ch_1_out_1; + out_mult++; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + if (output_ch & 1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* Init accumulator with bias for channel N + 1 */ + q31_t ch_0_out_0 = *bias; + q31_t ch_0_out_1 = ch_0_out_0; + + int32_t col_count = num_col_a / 4; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad_reordered(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } /* while over col_count */ + + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_0 += out_offset; + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q7_t)ch_0_out_0; + + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + ch_0_out_1 += out_offset; + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q7_t)ch_0_out_1; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c new file mode 100644 index 0000000..adfa702 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_s8.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 27. October 2021 + * $Revision: V.2.0.6 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/* + * s8 General matrix multiplication function with per-channel requantization for upto 4 column batches. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_mat_mult_s8(const q7_t *input_row, + const q7_t *input_col, + const uint16_t output_ch, + const uint16_t col_batches, + const int32_t *output_shift, + const int32_t *output_mult, + const int32_t out_offset, + const int32_t col_offset, + const int32_t row_offset, + const int16_t activation_min, + const int16_t activation_max, + const uint16_t row_len, + const int32_t *const bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + (void)row_offset; + if (col_batches == 4) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col; + const int8_t *ip_c1 = input_col + row_len; + const int8_t *ip_c2 = input_col + (2 * row_len); + const int8_t *ip_c3 = input_col + (3 * row_len); + + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + int32_t acc_3 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_m_n_s16(vuninitializedq_s16(), col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t c1 = vldrbq_s16(ip_c1); + ip_c1 += 8; + c1 = vaddq_s16(c1, offset); + + int16x8_t c2 = vldrbq_s16(ip_c2); + ip_c2 += 8; + c2 = vaddq_s16(c2, offset); + + int16x8_t c3 = vldrbq_s16(ip_c3); + ip_c3 += 8; + c3 = vaddq_s16(c3, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + acc_1 = vmladavaq_p_s16(acc_1, r0, c1, p); + acc_2 = vmladavaq_p_s16(acc_2, r0, c2, p); + acc_3 = vmladavaq_p_s16(acc_3, r0, c3, p); + } + + int32x4_t res = {acc_0, acc_1, acc_2, acc_3}; + if (bias) + { + res = vaddq_n_s32(res, bias[i_out_ch]); + } + res = arm_requantize_mve(res, output_mult[i_out_ch], output_shift[i_out_ch]); + res = vaddq_n_s32(res, out_offset); + + res = vmaxq_s32(res, vdupq_n_s32(activation_min)); + res = vminq_s32(res, vdupq_n_s32(activation_max)); + + const uint32x4_t scatter_offset = {0, output_ch, output_ch * 2, output_ch * 3}; + vstrbq_scatter_offset_s32(&out[i_out_ch], scatter_offset, res); + } + out += 4 * output_ch; + } + else + { + for (int i_col_batch = (col_batches & ~0x3); i_col_batch < (col_batches & 0x3); i_col_batch++) + { + for (int i_out_ch = 0; i_out_ch < output_ch; i_out_ch++) + { + int32_t row_len_tmp = row_len; + + const int8_t *ip_r0 = input_row + (i_out_ch * row_len); + const int8_t *ip_c0 = input_col + (i_col_batch * row_len); + int32_t acc_0 = 0; + const int32_t row_loop_cnt = (row_len + 7) / 8; + + for (int i_row_loop = 0; i_row_loop < row_loop_cnt; i_row_loop++) + { + const mve_pred16_t p = vctp16q((uint32_t)row_len_tmp); + const int16x8_t offset = vdupq_m_n_s16(vuninitializedq_s16(), col_offset, p); + row_len_tmp -= 8; + + int16x8_t c0 = vldrbq_s16(ip_c0); + ip_c0 += 8; + c0 = vaddq_s16(c0, offset); + + int16x8_t r0 = vldrbq_z_s16(ip_r0, p); + ip_r0 += 8; + acc_0 = vmladavaq_p_s16(acc_0, r0, c0, p); + } + + if (bias) + { + acc_0 += bias[i_out_ch]; + } + acc_0 = arm_nn_requantize(acc_0, output_mult[i_out_ch], output_shift[i_out_ch]); + acc_0 += out_offset; + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + out[i_out_ch] = (q7_t)acc_0; + } + out += output_ch; + } + } + return out; + +#else + (void)input_row; + (void)input_col; + (void)output_ch; + (void)col_batches; + (void)output_shift; + (void)output_mult; + (void)out_offset; + (void)col_offset; + (void)row_offset; + (void)activation_min; + (void)activation_max; + (void)row_len; + (void)bias; + (void)out; + return NULL; +#endif +} diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt new file mode 100644 index 0000000..cccd996 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/CMakeLists.txt @@ -0,0 +1,21 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC} arm_fully_connected_s16.c) + diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 0000000..9eb02eb --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad(pB, &inM11, &inM12); + pB2 = read_and_pad(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 0000000..a2da772 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,417 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 0000000..d8b6887 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + +arm_status arm_fully_connected_q15(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + inM2 = arm_nn_read_q15x2_ia(&pB2); + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt--; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inM1; + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + inV1 = arm_nn_read_q15x2_ia(&pA); + inM1 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t)__SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 0000000..f6c9b16 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +arm_status arm_fully_connected_q15_opt(const q15_t *pV, + const q15_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t *bias, + q15_t *pOut, + q15_t *vec_buffer) +{ + (void)vec_buffer; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q15x2_ia(&pB); + sum = __SMLAD(inV, inM11, sum); + inM12 = arm_nn_read_q15x2_ia(&pB); + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = arm_nn_read_q15x2_ia(&pB); + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = arm_nn_read_q15x2_ia(&pB); + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t)(__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = arm_nn_read_q15x2_ia(&pB); + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM1, sum); + + inM2 = arm_nn_read_q15x2_ia(&pB); + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t)(__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t)__SSAT((sum >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t)__SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t)__SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 0000000..d500efe --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: July 20, 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +arm_status arm_fully_connected_q7(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = read_and_pad_reordered(pB, &inM11, &inM12); + pB2 = read_and_pad_reordered(pB2, &inM21, &inM22); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = arm_nn_read_q15x2_ia(&pA); + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + (void)vec_buffer; + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 0000000..2f3d653 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * arm_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +arm_status arm_fully_connected_q7_opt(const q7_t *pV, + const q7_t *pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t *bias, + q7_t *pOut, + q15_t *vec_buffer) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = arm_nn_read_q15x2_ia(&pA); + inM11 = arm_nn_read_q7x4_ia(&pB); + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = arm_nn_read_q7x4_ia(&pB); + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#else + asm volatile("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n" + : [ sum ] "+r"(sum), + [ sum2 ] "+r"(sum2), + [ sum3 ] "+r"(sum3), + [ sum4 ] "+r"(sum4), + [ pB ] "+r"(pB), + [ pA ] "+r"(pA) + : [ colCnt ] "r"(colCnt) + : "r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t)(__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = read_and_pad_reordered(pB, &inM11, &inM12); + + inV1 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV1, inM11, sum); + + inV2 = arm_nn_read_q15x2_ia(&pA); + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t)(__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + (void)vec_buffer; + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c new file mode 100644 index 0000000..46df578 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s16.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s16 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 3. August 2021 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S16 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ +arm_status arm_fully_connected_s16(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q15_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int64_t *bias, + const cmsis_nn_dims *output_dims, + q15_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + const q31_t reduced_multiplier = REDUCE_MULTIPLIER(quant_params->multiplier); + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s16(input, + kernel, + bias, + output, + reduced_multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + + return (ARM_MATH_SUCCESS); +} + +int32_t arm_fully_connected_s16_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c new file mode 100644 index 0000000..9615701 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_s8.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_s8 + * Description: Fully connected function compatible with TF Lite. + * + * $Date: 8 April 2022 + * $Revision: V.3.1.0 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + +/* + * S8 basic fully-connected and matrix multiplication layer function for TensorFlow Lite + * + * Refer header file for details. + * + */ + +arm_status arm_fully_connected_s8(const cmsis_nn_context *ctx, + const cmsis_nn_fc_params *fc_params, + const cmsis_nn_per_tensor_quant_params *quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input, + const cmsis_nn_dims *filter_dims, + const q7_t *kernel, + const cmsis_nn_dims *bias_dims, + const int32_t *bias, + const cmsis_nn_dims *output_dims, + q7_t *output) +{ + (void)bias_dims; + (void)ctx; + (void)fc_params->filter_offset; + + int32_t batch_cnt = input_dims->n; + + while (batch_cnt) + { + arm_nn_vec_mat_mult_t_s8(input, + kernel, + bias, + output, + fc_params->input_offset, + 0, + fc_params->output_offset, + quant_params->multiplier, + quant_params->shift, + filter_dims->n, /* col_dim or accum_depth */ + output_dims->c, /* row_dim or output_depth */ + fc_params->activation.min, + fc_params->activation.max, + 1L); + input += filter_dims->n; + output += output_dims->c; + batch_cnt--; + } + return (ARM_MATH_SUCCESS); +} + +int32_t arm_fully_connected_s8_get_buffer_size(const cmsis_nn_dims *filter_dims) +{ + (void)filter_dims; + return 0; +} + +/** + * @} end of FC group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt new file mode 100644 index 0000000..0aa9f38 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC} arm_q7_to_q15_with_offset.c + arm_nn_mat_mul_kernel_s16.c + arm_q7_to_q15_with_offset.c + arm_nn_mat_mul_kernel_s16.c + arm_nn_vec_mat_mult_t_s16.c + arm_q7_to_q15_no_shift.c) + diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c new file mode 100644 index 0000000..c3f666a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_accumulate_q7_to_q15.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_accumulate_q7_to_q15.c + * Description: Accumulate q7 vector into q15 one. + * + * $Date: 20 July 2021 + * $Revision: V.1.1.2 + * + * pSrc Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_accumulate_q7_to_q15(q15_t *pDst, const q7_t *pSrc, uint32_t length) +{ + q15_t *pCnt = pDst; + const q7_t *pV = pSrc; + int32_t count = length; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t v1, v2, vo1, vo2; + count = length >> 2; + q31_t in; + + while (count > 0l) + { + q31_t value = arm_nn_read_q7x4_ia(&pV); + v1 = __SXTB16(__ROR((uint32_t)value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + vo2 = (q31_t)__PKHTB(v1, v2, 16); + vo1 = (q31_t)__PKHBT(v2, v1, 16); +#else + vo1 = (q31_t)__PKHTB(v1, v2, 16); + vo2 = (q31_t)__PKHBT(v2, v1, 16); +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + count--; + } + count = length & 0x3; +#endif + while (count > 0l) + { + *pCnt++ += *pV++; + count--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c new file mode 100644 index 0000000..511e586 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_add_q7.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_add_q7.c + * Description: Non saturating addition of elements of a q7 vector. + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nn_tables.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +void arm_nn_add_q7(const q7_t *input, q31_t *output, uint32_t block_size) +{ + uint32_t block_count; + q31_t result = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Loop unrolling: Compute 4 outputs at a time */ + block_count = block_size >> 2U; + + while (block_count > 0U) + { + const int32_t mult_q15x2 = (1UL << 16) | 1UL; + q31_t in_q7x4 = arm_nn_read_q7x4_ia(&input); + q31_t temp_q15x2 = __SXTAB16(__SXTB16(in_q7x4), __ROR((uint32_t)in_q7x4, 8)); + + result = __SMLAD(temp_q15x2, mult_q15x2, result); + + /* Decrement loop counter */ + block_count--; + } + + /* Loop unrolling: Compute remaining outputs */ + block_count = block_size & 0x3; +#else + block_count = block_size; +#endif + while (block_count > 0U) + { + /* Add and store result in destination buffer. */ + result += *input++; + + /* Decrement loop counter */ + block_count--; + } + + *output = result; +} + +/** + * @} end of NNBasicMath group + */ \ No newline at end of file diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c new file mode 100644 index 0000000..b633ef4 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_padded_s8.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_padded_s8.c + * Description: Depthwise convolution with padded matrices. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M processors with MVE extension + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of transposed rhs matrix with 4 lhs matrices. One or more of the rhs matrices are padded. + * Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_nt_t_padded_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (num_ch + 3) / 4; + const int32_t *bias = output_bias; + uint32_t num_ch_to_process = num_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, out += 4, offset += 4, i_loop_cnt++) + { + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + bias += 4; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * num_ch + offset; + const int8_t *lhs_2 = lhs + (row_x_col * num_ch * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * num_ch * 3) + offset; + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + ip_0 = vaddq_n_s32(ip_0, input_offset); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + ip_1 = vaddq_n_s32(ip_1, input_offset); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + ip_2 = vaddq_n_s32(ip_2, input_offset); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + ip_3 = vaddq_n_s32(ip_3, input_offset); + + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += num_ch; + lhs_1 += num_ch; + lhs_2 += num_ch; + lhs_3 += num_ch; + + rhs_0 += num_ch; + } + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + mve_pred16_t p = vctp32q(num_ch_to_process); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + num_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * num_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * num_ch, out_3, p); + } + + const int tail_ch = num_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + return out + (3 * num_ch); + +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c new file mode 100644 index 0000000..dda12fd --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_depthwise_conv_nt_t_s8.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_depthwise_conv_nt_t_s8.c + * Description: Depthwise convolution on matrices with no padding. + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M processors with MVE extension. + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * Depthwise convolution of rhs matrix with 4 lhs matrices with no padding. Dimensions are the same for lhs and rhs. + * + * Refer header file for details. + * + */ + +q7_t *arm_nn_depthwise_conv_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const int32_t input_offset, + const uint16_t num_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int32_t out_offset, + const int32_t activation_min, + const int32_t activation_max, + const uint16_t row_x_col, + const int32_t *const output_bias, + q7_t *out) +{ +#if defined(ARM_MATH_MVEI) + const int32_t *bias = output_bias; + int32_t loop_count = (num_ch + 3) / 4; + uint32_t num_ch_to_process = num_ch; + + for (int i_loop_cnt = 0, offset = 0; i_loop_cnt < loop_count; + num_ch_to_process -= 4, offset += 4, out += 4, i_loop_cnt++) + { + int32x4_t out_0 = vldrwq_s32(bias); + int32x4_t out_1 = out_0; + int32x4_t out_2 = out_0; + int32x4_t out_3 = out_0; + bias += 4; + + const int8_t *rhs_0 = rhs + offset; + const int8_t *lhs_0 = lhs + offset; + const int8_t *lhs_1 = lhs + row_x_col * num_ch + offset; + const int8_t *lhs_2 = lhs + (row_x_col * num_ch * 2) + offset; + const int8_t *lhs_3 = lhs + (row_x_col * num_ch * 3) + offset; + int32x4_t ker_sum = vdupq_n_s32(0); + + for (int i_row_x_col = 0; i_row_x_col < row_x_col; i_row_x_col++) + { + const int32x4_t ker_0 = vldrbq_s32(rhs_0); + ker_sum = vaddq_s32(ker_sum, ker_0); + + int32x4_t ip_0 = vldrbq_s32(lhs_0); + out_0 += vmulq_s32(ip_0, ker_0); + + int32x4_t ip_1 = vldrbq_s32(lhs_1); + out_1 += vmulq_s32(ip_1, ker_0); + + int32x4_t ip_2 = vldrbq_s32(lhs_2); + out_2 += vmulq_s32(ip_2, ker_0); + + int32x4_t ip_3 = vldrbq_s32(lhs_3); + out_3 += vmulq_s32(ip_3, ker_0); + + lhs_0 += num_ch; + lhs_1 += num_ch; + lhs_2 += num_ch; + lhs_3 += num_ch; + + rhs_0 += num_ch; + } + + ker_sum = vmulq_n_s32(ker_sum, input_offset); + out_0 = ker_sum + out_0; + out_1 = ker_sum + out_1; + out_2 = ker_sum + out_2; + out_3 = ker_sum + out_3; + + const int32x4_t mult = vldrwq_s32(out_mult); + const int32x4_t shift = vldrwq_s32(out_shift); + out_mult += 4; + out_shift += 4; + mve_pred16_t p = vctp32q(num_ch_to_process); + + out_0 = arm_requantize_mve_32x4(out_0, mult, shift); + out_0 = vaddq_n_s32(out_0, out_offset); + out_0 = vmaxq_s32(out_0, vdupq_n_s32(activation_min)); + out_0 = vminq_s32(out_0, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out, out_0, p); + + out_1 = arm_requantize_mve_32x4(out_1, mult, shift); + out_1 = vaddq_n_s32(out_1, out_offset); + out_1 = vmaxq_s32(out_1, vdupq_n_s32(activation_min)); + out_1 = vminq_s32(out_1, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + num_ch, out_1, p); + + out_2 = arm_requantize_mve_32x4(out_2, mult, shift); + out_2 = vaddq_n_s32(out_2, out_offset); + out_2 = vmaxq_s32(out_2, vdupq_n_s32(activation_min)); + out_2 = vminq_s32(out_2, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 2 * num_ch, out_2, p); + + out_3 = arm_requantize_mve_32x4(out_3, mult, shift); + out_3 = vaddq_n_s32(out_3, out_offset); + out_3 = vmaxq_s32(out_3, vdupq_n_s32(activation_min)); + out_3 = vminq_s32(out_3, vdupq_n_s32(activation_max)); + vstrbq_p_s32(out + 3 * num_ch, out_3, p); + } + + const int tail_ch = num_ch & 0x3; + if (tail_ch != 0) + { + out -= (4 - tail_ch); + } + + return out + (3 * num_ch); +#else + (void)lhs; + (void)rhs; + (void)input_offset; + (void)num_ch; + (void)out_shift; + (void)out_mult; + (void)out_offset; + (void)activation_min; + (void)activation_max; + (void)row_x_col; + (void)output_bias; + (void)out; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c new file mode 100644 index 0000000..8b1bf6e --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_1x_s8.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_1x_s8.c + * Description: General Matrix-multiplication function + * + * $Date: 19. April 2022 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 1 row + * + * Refer header file for details. + * + */ + +arm_status arm_nn_mat_mul_core_1x_s8(int32_t row_elements, + const int8_t *row_base, + const int8_t *col_base, + int32_t *const sum_col, + int32_t *const output) +{ + int32_t acc_n0 = 0; + int32_t sum_tmp = 0; + +#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE) + + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), [sum] "+Te"(sum_tmp), [row0] "+r"(row_base), [out0] "+Te"(acc_n0) + : [cnt] "r"(row_elements) + : "q0", "q1", "memory", "r14"); +#else + for (int i = 0; i < row_elements; i++) + { + sum_tmp += col_base[i]; + acc_n0 += row_base[i] * col_base[i]; + } +#endif + + *sum_col = sum_tmp; + *output = acc_n0; + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c new file mode 100644 index 0000000..ff427ad --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_core_4x_s8.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mul_core_4x_s8.c + * Description: General matrix multiplication function for MVE extension + * + * $Date: 19. April 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ +#include "arm_nn_types.h" +#include "arm_nnsupportfunctions.h" +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication to process 4 rows and one column + * + * Refer header file for details. + * + */ + +int8_t *arm_nn_mat_mul_core_4x_s8(const int32_t row_elements, + const int32_t offset, + const int8_t *row_base, + const int8_t *col_base_ref, + const int32_t out_ch, + const cmsis_nn_conv_params *conv_params, + const cmsis_nn_per_channel_quant_params *quant_params, + const int32_t *bias, + int8_t *output) +{ + +#if defined(ARM_MATH_MVEI) + for (int i = 0; i < out_ch; i++) + { + int32_t acc_n0 = 0; + int32_t acc_n1 = 0; + int32_t acc_n2 = 0; + int32_t acc_n3 = 0; + + const int8_t *ip_row_0 = row_base; + const int8_t *ip_row_1 = row_base + offset; + const int8_t *ip_row_2 = row_base + (2 * offset); + const int8_t *ip_row_3 = row_base + (3 * offset); + const int8_t *col_base = col_base_ref + i * row_elements; + int32_t sum_tmp = 0; + + __ASM volatile(" vldrb.8 q0, [%[col]], #16 \n" + " wlstp.8 lr, %[cnt], 1f \n" + "2: \n" + " vaddva.s8 %[sum], q0 \n" + " vldrb.8 q1, [%[row0]], #16 \n" + " vmladava.s8 %[out0], q0, q1 \n" + " vldrb.8 q2, [%[row1]], #16 \n" + " vmladava.s8 %[out1], q0, q2 \n" + " vldrb.8 q3, [%[row2]], #16 \n" + " vmladava.s8 %[out2], q0, q3 \n" + " vldrb.8 q4, [%[row3]], #16 \n" + " vmladava.s8 %[out3], q0, q4 \n" + " vldrb.8 q0, [%[col]], #16 \n" + " letp lr, 2b \n" + "1: \n" + : [col] "+r"(col_base), + [sum] "+Te"(sum_tmp), + [row0] "+r"(ip_row_0), + [row1] "+r"(ip_row_1), + [row2] "+r"(ip_row_2), + [row3] "+r"(ip_row_3), + [out0] "+Te"(acc_n0), + [out1] "+Te"(acc_n1), + [out2] "+Te"(acc_n2), + [out3] "+Te"(acc_n3) + : [cnt] "r"(row_elements) + : "q0", "q1", "q2", "q3", "q4", "memory", "r14"); + + int32x4_t res = {acc_n0, acc_n1, acc_n2, acc_n3}; + sum_tmp *= conv_params->input_offset; + if (bias) + { + sum_tmp += bias[i]; + } + res = vaddq_n_s32(res, sum_tmp); + + res = arm_requantize_mve(res, quant_params->multiplier[i], quant_params->shift[i]); + res = vaddq_n_s32(res, conv_params->output_offset); + + res = vmaxq_s32(res, vdupq_n_s32(conv_params->activation.min)); + res = vminq_s32(res, vdupq_n_s32(conv_params->activation.max)); + + const uint32x4_t scatter_offset = {0, (uint32_t)out_ch, (uint32_t)out_ch * 2, (uint32_t)out_ch * 3}; + vstrbq_scatter_offset_s32(output, scatter_offset, res); + output++; + } + + return output + (3 * out_ch); +#else + (void)row_elements; + (void)offset; + (void)row_base; + (void)col_base_ref; + (void)out_ch; + (void)conv_params; + (void)quant_params; + (void)bias; + (void)output; + return NULL; +#endif +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c new file mode 100644 index 0000000..41d0bc9 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mul_kernel_s16.c @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_s16.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 12 August 2021 + * $Revision: V.1.1.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/* + * Matrix-multiplication function for convolution with per-channel requantization. + * + * Refer header file for details. + * + */ + +q15_t *arm_nn_mat_mult_kernel_s16(const q7_t *input_a, + const q15_t *input_b, + const int32_t output_ch, + const int32_t *out_shift, + const int32_t *out_mult, + const int16_t activation_min, + const int16_t activation_max, + const int32_t num_col_a, + const int64_t *const output_bias, + q15_t *out_0) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* set up the second output pointers */ + q15_t *out_1 = out_0 + output_ch; + const int64_t *bias = output_bias; + uint16_t row_count = output_ch / 2; + const q7_t *ip_a0 = input_a; + + /* this loop over rows in A */ + while (row_count) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + /* align the second pointer for A */ + const q7_t *ip_a1 = ip_a0 + num_col_a; + + /* Init accumulator for channel N and N + 1 */ + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + q31_t ch_1_out_0 = 0; + q31_t ch_1_out_1 = 0; + + uint16_t col_count = num_col_a / 4; + /* accumulate over the vector */ + while (col_count) + { + q31_t a01, a02, a11, a12; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + ip_a1 = read_and_pad(ip_a1, &a11, &a12); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a11, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a11, b1, ch_1_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + ch_1_out_0 = __SMLAD(a12, b0, ch_1_out_0); + ch_1_out_1 = __SMLAD(a12, b1, ch_1_out_1); + + col_count--; + } /* while over col_count */ + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q7_t a1 = *ip_a1++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + ch_1_out_0 += a1 * b0; + ch_1_out_1 += a1 * b1; + col_count--; + } /* while over col_count */ + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_shift++; + + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_1_out_0 + *bias; + ch_1_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_1_out_1 + *bias++; + ch_1_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + out_mult++; + } + else + { + ch_1_out_0 = arm_nn_requantize(ch_1_out_0, *out_mult, *out_shift); + ch_1_out_1 = arm_nn_requantize(ch_1_out_1, *out_mult, *out_shift); + out_mult++; + } + ch_1_out_0 = MAX(ch_1_out_0, activation_min); + ch_1_out_0 = MIN(ch_1_out_0, activation_max); + *out_0++ = (q15_t)ch_1_out_0; + + ch_1_out_1 = MAX(ch_1_out_1, activation_min); + ch_1_out_1 = MIN(ch_1_out_1, activation_max); + *out_1++ = (q15_t)ch_1_out_1; + out_shift++; + + /* skip row */ + ip_a0 += num_col_a; + row_count--; + } + + /* compute the last odd numbered row if any */ + if (output_ch & 0x1) + { + /* setup pointers for B */ + const q15_t *ip_b0 = input_b; + const q15_t *ip_b1 = ip_b0 + num_col_a; + + q31_t ch_0_out_0 = 0; + q31_t ch_0_out_1 = 0; + + uint16_t col_count = num_col_a >> 2; + while (col_count) + { + q31_t a01, a02; + q31_t b0 = arm_nn_read_q15x2_ia(&ip_b0); + q31_t b1 = arm_nn_read_q15x2_ia(&ip_b1); + + ip_a0 = read_and_pad(ip_a0, &a01, &a02); + + ch_0_out_0 = __SMLAD(a01, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a01, b1, ch_0_out_1); + + b0 = arm_nn_read_q15x2_ia(&ip_b0); + b1 = arm_nn_read_q15x2_ia(&ip_b1); + ch_0_out_0 = __SMLAD(a02, b0, ch_0_out_0); + ch_0_out_1 = __SMLAD(a02, b1, ch_0_out_1); + + col_count--; + } + col_count = num_col_a & 0x3; + while (col_count) + { + q7_t a0 = *ip_a0++; + q15_t b0 = *ip_b0++; + q15_t b1 = *ip_b1++; + + ch_0_out_0 += a0 * b0; + ch_0_out_1 += a0 * b1; + col_count--; + } + if (bias) + { + q31_t reduced_multiplier = REDUCE_MULTIPLIER(*out_mult); + q63_t acc_64 = ch_0_out_0 + *bias; + ch_0_out_0 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + acc_64 = ch_0_out_1 + *bias++; + ch_0_out_1 = arm_nn_requantize_s64(acc_64, reduced_multiplier, *out_shift); + } + else + { + ch_0_out_0 = arm_nn_requantize(ch_0_out_0, *out_mult, *out_shift); + ch_0_out_1 = arm_nn_requantize(ch_0_out_1, *out_mult, *out_shift); + } + ch_0_out_0 = MAX(ch_0_out_0, activation_min); + ch_0_out_0 = MIN(ch_0_out_0, activation_max); + *out_0++ = (q15_t)ch_0_out_0; + + ch_0_out_1 = MAX(ch_0_out_1, activation_min); + ch_0_out_1 = MIN(ch_0_out_1, activation_max); + *out_1++ = (q15_t)ch_0_out_1; + out_mult++; + out_shift++; + } + + out_0 += output_ch; + + /* return the new output pointer with offset */ + return out_0; +#else + (void)input_a; + (void)input_b; + (void)output_ch; + (void)out_shift; + (void)out_mult; + (void)activation_min; + (void)activation_max; + (void)num_col_a; + (void)output_bias; + (void)out_0; + /* To be completed */ + return NULL; +#endif +} diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c new file mode 100644 index 0000000..d0420c2 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mat_mult_nt_t_s8.c @@ -0,0 +1,582 @@ +/* + * Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_s8_nt_t_s8 + * Description: Matrix multiplication support function with the right-hand-side (rhs) matrix transposed + * + * $Date: 09. October 2020 + * $Revision: V.1.0.3 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 matrix multiplication with the right-hand-side matrix transposed + * + * Refer header file for details. + * + */ +arm_status arm_nn_mat_mult_nt_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t *dst_multipliers, + const int32_t *dst_shifts, + const int32_t lhs_rows, + const int32_t rhs_rows, + const int32_t rhs_cols, + const int32_t lhs_offset, + const int32_t dst_offset, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) + const int32_t off0 = rhs_cols - 4; + + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + val1 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + res11 = __SMLAD(val0, val4, res11); + + val4 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = __SXTB16(val1); + val0 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val1 = __SXTB16_RORn(val1, 8); + val0 = __SXTB16_RORn(val0, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val3, val2, res00); + val5 = __SXTB16(val4); + res00 = __SMLAD(val0, val1, res00); + val4 = __SXTB16_RORn(val4, 8); + res01 = __SMLAD(val3, val5, res01); + res01 = __SMLAD(val0, val4, res01); + + // 4 x MAC res10, res11 + val0 = arm_nn_read_q7x4((const q7_t *)&lhs_ptr[off0]); + val3 = __SXTB16(val0); + val0 = __SXTB16_RORn(val0, 8); + res10 = __SMLAD(val3, val2, res10); + res11 = __SMLAD(val3, val5, res11); + res10 = __SMLAD(val0, val1, res10); + res11 = __SMLAD(val0, val4, res11); + } + + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + int32_t rhs_cols_idx = 0; + + q31_t val0, val1, val2, val3, val4, val5; + for (; rhs_cols_idx <= (rhs_cols - 16); rhs_cols_idx += 16) + { + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + + val0 = arm_nn_read_q7x4_ia((const q7_t **)&rhs_ptr); + val1 = arm_nn_read_q7x4((const q7_t *)&rhs_ptr[off0]); + val2 = arm_nn_read_q7x4_ia((const q7_t **)&lhs_ptr); + val3 = __SXTB16(val0); + val5 = __SXTB16(val2); + val4 = __SXTB16(val1); + val0 = __SXTB16_RORn(val0, 8); + val2 = __SXTB16_RORn(val2, 8); + val1 = __SXTB16_RORn(val1, 8); + + // 4 x MAC res00, res01 + res00 = __SMLAD(val5, val3, res00); + res00 = __SMLAD(val2, val0, res00); + res01 = __SMLAD(val5, val4, res01); + res01 = __SMLAD(val2, val1, res01); + } + + // Left-over accumulations + for (; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#else + for (int32_t rhs_rows_idx = 0; rhs_rows_idx <= (rhs_rows - 2); rhs_rows_idx += 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + q31_t lhs_offset_contribution0 = 0; + q31_t lhs_offset_contribution1 = 0; + + for (int32_t x = 0; x < rhs_cols; ++x) + { + lhs_offset_contribution0 += rhs[x]; + lhs_offset_contribution1 += rhs[x + rhs_cols]; + } + + lhs_offset_contribution0 *= lhs_offset; + lhs_offset_contribution1 *= lhs_offset; + if (bias) + { + lhs_offset_contribution0 += bias[rhs_rows_idx]; + lhs_offset_contribution1 += bias[rhs_rows_idx + 1]; + } + + int32_t lhs_rows_idx = lhs_rows >> 1; + + while (lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + q31_t res10 = lhs_offset_contribution0; + q31_t res11 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + lhs_value = lhs_ptr[rhs_cols]; + res10 += lhs_value * rhs_value0; + res11 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + res10 = arm_nn_requantize(res10, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res11 = arm_nn_requantize(res11, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res10 += dst_offset; + res11 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res10 = MAX(res10, activation_min); + res10 = MIN(res10, activation_max); + res11 = MAX(res11, activation_min); + res11 = MIN(res11, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + dst_ptr += rhs_rows; + dst_ptr[0] = (q7_t)res10; + dst_ptr[1] = (q7_t)res11; + dst_ptr += rhs_rows; + + lhs_ptr += rhs_cols; + + lhs_rows_idx--; + } + + // Left-over rows + if (lhs_rows % 2) + { + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = lhs_offset_contribution0; + q31_t res01 = lhs_offset_contribution1; + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q7_t rhs_value0 = rhs_ptr[0]; + q7_t rhs_value1 = rhs_ptr[rhs_cols]; + q7_t lhs_value = lhs_ptr[0]; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows_idx], dst_shifts[rhs_rows_idx]); + res01 = arm_nn_requantize(res01, dst_multipliers[rhs_rows_idx + 1], dst_shifts[rhs_rows_idx + 1]); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr[1] = (q7_t)res01; + } + + rhs += 2 * rhs_cols; + dst += 2; + } + + if (rhs_rows % 2) + { + const q7_t *lhs_ptr = &lhs[0]; + q7_t *dst_ptr = &dst[0]; + + for (int32_t lhs_rows_idx = 0; lhs_rows_idx < lhs_rows; ++lhs_rows_idx) + { + const q7_t *rhs_ptr = &rhs[0]; + q31_t res00 = 0; + if (bias) + { + res00 = bias[rhs_rows - 1]; + } + + for (int32_t rhs_cols_idx = rhs_cols; rhs_cols_idx != 0; rhs_cols_idx--) + { + q31_t rhs_value = rhs_ptr[0]; + q31_t lhs_value = lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multipliers[rhs_rows - 1], dst_shifts[rhs_rows - 1]); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + dst_ptr[0] = (q7_t)res00; + dst_ptr += rhs_rows; + } + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 0000000..d6a45ef --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 20. July 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t)__SSAT(((q31_t)((q31_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 0000000..fdced4c --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 20. July 2021 + * $Revision: V.1.1.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, const uint16_t out_shift, uint32_t blockSize) +{ + uint32_t blkCnt = blockSize; /* loop counters */ + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t)__SSAT(((q15_t)((q15_t)(*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c new file mode 100644 index 0000000..5956d3a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s16.c @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s16 + * Description: s16 vector by matrix (transposed) multiplication + * + * $Date: 04. January 2022 + * $Revision: V.1.2.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s16 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_s16(const q15_t *lhs, + const q7_t *rhs, + const q63_t *bias, + q15_t *dst, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + const int32_t row_loop_cnt = rhs_rows / 2; + + int32_t rhs_cols_fast = rhs_cols; + + if (rhs_cols > 512) + { + rhs_cols_fast = 512; + } + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + q63_t acc_64_0 = 0; + q63_t acc_64_1 = 0; + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t ker_0, ker_1, vec_part_0, vec_part_1; + vec_part_0 = arm_nn_read_q15x2_ia(&lhs_vec); + vec_part_1 = arm_nn_read_q15x2_ia(&lhs_vec); + + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + acc_0 = __SMLAD(ker_0, vec_part_0, acc_0); + acc_0 = __SMLAD(ker_1, vec_part_1, acc_0); + + rhs_1 = read_and_pad(rhs_1, &ker_0, &ker_1); + + acc_1 = __SMLAD(ker_0, vec_part_0, acc_1); + acc_1 = __SMLAD(ker_1, vec_part_1, acc_1); + } + + acc_64_0 += acc_0; + acc_64_1 += acc_1; + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_64_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + if (bias) + { + acc_64_0 += *bias++; + acc_64_1 += *bias++; + } + q31_t tmp; + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + + tmp = arm_nn_requantize_s64(acc_64_1, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + + if (rhs_rows & 0x1) + { + q63_t acc_64_0 = 0; + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols_fast / 4; + + const int16_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t ker_0, ker_1, vec; + rhs_0 = read_and_pad(rhs_0, &ker_0, &ker_1); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_0, vec, acc_0); + + vec = arm_nn_read_q15x2_ia(&lhs_vec); + acc_0 = __SMLAD(ker_1, vec, acc_0); + } + + acc_64_0 += acc_0; + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec); + lhs_vec++; + acc_64_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + if (bias) + { + acc_64_0 += *bias++; + } + q31_t tmp; + tmp = arm_nn_requantize_s64(acc_64_0, dst_multiplier, dst_shift); + tmp = MAX(tmp, activation_min); + tmp = MIN(tmp, activation_max); + *dst++ = (q15_t)tmp; + } + +#else + for (int i_row_loop_cnt = 0; i_row_loop_cnt < rhs_rows; i_row_loop_cnt++) + { + const q15_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + + q63_t result = 0; + + if (bias) + { + result = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q63_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q63_t lhs_value = *lhs_ptr; + + result += lhs_value * rhs_value0; + + ++rhs_ptr_0; + ++lhs_ptr; + } + + // Quantize down + result = arm_nn_requantize_s64(result, dst_multiplier, dst_shift); + + // Clamp the result + result = ((result) > (activation_min) ? (result) : (activation_min)); + result = ((result) < (activation_max) ? (result) : (activation_max)); + + *dst++ = (q15_t)result; + rhs += rhs_cols; + } +#endif + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c new file mode 100644 index 0000000..c7dfd14 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_s8.c @@ -0,0 +1,402 @@ +/* + * Copyright (C) 2020-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_s8 + * Description: s8 vector by matrix (transposed) multiplication + * + * $Date: 28 April 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_s8(const q7_t *lhs, + const q7_t *rhs, + const q31_t *bias, + q7_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max, + const int32_t address_offset) +{ + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + const int32_t row_loop_cnt = rhs_rows / 3; + const uint32x4_t address_offset_array = {0, address_offset, address_offset * 2, address_offset * 3}; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + mve_pred16_t p = vctp32q(3); + if (bias) + { + int32x4_t b = vldrwq_z_s32(bias, p); + acc = vaddq_m_s32(vuninitializedq_s32(), acc, b, p); + bias += 3; + } + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vaddq_s32(acc, vdupq_n_s32(dst_offset)); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + + if (address_offset > 1L) + { + vstrbq_scatter_offset_s32(dst, address_offset_array, acc); + } + else + { + vstrbq_p_s32(dst, acc, p); + } + dst += 3 * address_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + if (bias) + { + acc_0 += *bias; + bias++; + } + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 += offsets; + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_0 += dst_offset; + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = MIN(acc_0, activation_max); + dst += address_offset; + } + +#elif defined(ARM_MATH_DSP) + const int32_t row_loop_cnt = rhs_rows / 2; + const int16_t lhs_offset_s16 = (int16_t)lhs_offset; + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (bias) + { + acc_0 = *bias++; + acc_1 = *bias++; + } + + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1); + rhs_1++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + acc_1 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (int8_t)acc_0; + *(dst + address_offset) = (int8_t)acc_1; + dst += 2 * address_offset; + } + + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + if (bias) + { + acc_0 = *bias++; + } + const int32_t col_loop_cnt = rhs_cols / 4; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTB16_RORn((uint32_t)ker_0, 8); + ker_0 = __SXTB16(ker_0); + + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0); + rhs_0++; + } + + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Add offset + acc_0 += dst_offset; + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (int8_t)acc_0; + dst += address_offset; + } + +#else + + const int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + if (bias) + { + res00 = *bias++; + res01 = *bias++; + res02 = *bias++; + } + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + res01 += dst_offset; + res02 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q7_t)res00; + *(dst + address_offset) = (q7_t)res01; + *(dst + 2 * address_offset) = (q7_t)res02; + dst += 3 * address_offset; + + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + if (bias) + { + res00 = *bias++; + } + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0]; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Add offset + res00 += dst_offset; + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (int8_t)res00; + dst += address_offset; + rhs += rhs_cols; + } +#endif + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c new file mode 100644 index 0000000..5b821c3 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_vec_mat_mult_t_svdf_s8.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_vec_mat_mult_t_svdf_s8 + * Description: s8 vector by matrix (transposed) multiplication with + * s16 output. Targetted at SVDF operator. + * + * $Date: 15. April 2021 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/* + * s8 vector(lhs) by matrix (transposed) multiplication + * + * Refer header file for details. + * + */ +arm_status arm_nn_vec_mat_mult_t_svdf_s8(const q7_t *lhs, + const q7_t *rhs, + q15_t *dst, + const int32_t lhs_offset, + const int32_t rhs_offset, + const int32_t dst_offset, + const int32_t dst_multiplier, + const int32_t dst_shift, + const int32_t rhs_cols, + const int32_t rhs_rows, + const int32_t activation_min, + const int32_t activation_max) +{ + (void)rhs_offset; + if (rhs_cols < 0 || (NN_Q31_MAX - rhs_cols) < 16 || dst_offset < 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + (void)rhs_offset; +#if defined(ARM_MATH_MVEI) + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + int32_t acc_2 = 0; + + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + const int8_t *rhs_2 = rhs + 2 * rhs_cols; + + int32_t rhs_sum_0 = 0; + int32_t rhs_sum_1 = 0; + int32_t rhs_sum_2 = 0; + + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + const int8x16_t ker_1 = vldrbq_z_s8(rhs_1, p); + rhs_sum_1 = vaddvaq_p_s8(rhs_sum_1, ker_1, p); + acc_1 = vmladavaq_p_s8(acc_1, ker_1, input, p); + + const int8x16_t ker_2 = vldrbq_z_s8(rhs_2, p); + rhs_sum_2 = vaddvaq_p_s8(rhs_sum_2, ker_2, p); + acc_2 = vmladavaq_p_s8(acc_2, ker_2, input, p); + + lhs_vec += 16; + rhs_0 += 16; + rhs_1 += 16; + rhs_2 += 16; + } + rhs += 3 * rhs_cols; + + int32x4_t acc = {acc_0, acc_1, acc_2, 0}; + const int32x4_t rhs_sum = {rhs_sum_0, rhs_sum_1, rhs_sum_2, 0}; + acc += vdupq_n_s32(lhs_offset) * rhs_sum; + + acc = arm_requantize_mve(acc, dst_multiplier, dst_shift); + acc = vmaxq_s32(acc, vdupq_n_s32(activation_min)); + acc = vminq_s32(acc, vdupq_n_s32(activation_max)); + *(dst) = (int16_t)acc[0]; + *(dst + dst_offset) = (int16_t)acc[1]; + *(dst + 2 * dst_offset) = (int16_t)acc[2]; + dst += 3 * dst_offset; + } + + const int loop_cnt = rhs_rows % 3; + for (int i_row_loop_cnt = 0; i_row_loop_cnt < loop_cnt; i_row_loop_cnt++) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = (rhs_cols + 15) / 16; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + int32_t rhs_sum_0 = 0; + uint32_t col_cnt = (uint32_t)rhs_cols; + + for (int i = 0; i < col_loop_cnt; i++) + { + mve_pred16_t p = vctp8q(col_cnt); + col_cnt -= 16; + const int8x16_t input = vldrbq_z_s8(lhs_vec, p); + + const int8x16_t ker_0 = vldrbq_z_s8(rhs_0, p); + rhs_sum_0 = vaddvaq_p_s8(rhs_sum_0, ker_0, p); + acc_0 = vmladavaq_p_s8(acc_0, ker_0, input, p); + + lhs_vec += 16; + rhs_0 += 16; + } + rhs += rhs_cols; + + const int32_t offsets = rhs_sum_0 * lhs_offset; + acc_0 = __QADD(acc_0, offsets); + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + *dst = (q15_t)MIN(acc_0, activation_max); + dst += dst_offset; + } + +#elif defined(ARM_MATH_DSP) + int32_t row_loop_cnt = rhs_rows / 2; + + const int16_t lhs_offset_s16 = lhs_offset; + const int16_t rhs_offset_s16 = rhs_offset; + + const uint32_t lhs_offset_s16x2 = __PKHBT(lhs_offset_s16, lhs_offset_s16, 16); + const uint32_t rhs_offset_s16x2 = __PKHBT(rhs_offset_s16, rhs_offset_s16, 16); + for (int32_t i = 0; i < row_loop_cnt; i++) + { + int32_t acc_0 = 0; + int32_t acc_1 = 0; + + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + const int8_t *rhs_1 = rhs + rhs_cols; + rhs += 2 * rhs_cols; + for (int j = col_loop_cnt; j != 0; j--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16_RORn(lhs_offset_s16x2, (uint32_t)vec_0, 8); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + ker_0 = arm_nn_read_q7x4_ia(&rhs_1); + ker_1 = __SXTAB16_RORn(rhs_offset_s16x2, (uint32_t)ker_0, 8); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_1 = __SMLAD(ker_1, vec_1, acc_1); + acc_1 = __SMLAD(ker_0, vec_0, acc_1); + } + for (int k = col_loop_cnt * 4; k < rhs_cols; k++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + acc_1 += lhs_temp * (*rhs_1 + rhs_offset); + rhs_1++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + acc_1 = arm_nn_requantize(acc_1, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + acc_1 = MAX(acc_1, activation_min); + acc_1 = MIN(acc_1, activation_max); + *dst = (q15_t)acc_0; + *(dst + dst_offset) = (q15_t)acc_1; + dst += 2 * dst_offset; + } + if (rhs_rows & 0x1) + { + int32_t acc_0 = 0; + const int32_t col_loop_cnt = rhs_cols / 4; + const int8_t *lhs_vec = lhs; + const int8_t *rhs_0 = rhs; + for (int i = col_loop_cnt; i != 0; i--) + { + int32_t vec_0 = arm_nn_read_q7x4_ia(&lhs_vec); + int32_t vec_1 = __SXTAB16(lhs_offset_s16x2, __ROR((uint32_t)vec_0, 8)); + vec_0 = __SXTAB16(lhs_offset_s16x2, vec_0); + int32_t ker_0 = arm_nn_read_q7x4_ia(&rhs_0); + int32_t ker_1 = __SXTAB16(rhs_offset_s16x2, __ROR((uint32_t)ker_0, 8)); + ker_0 = __SXTAB16(rhs_offset_s16x2, ker_0); + acc_0 = __SMLAD(ker_1, vec_1, acc_0); + acc_0 = __SMLAD(ker_0, vec_0, acc_0); + } + for (int j = col_loop_cnt * 4; j < rhs_cols; j++) + { + const int32_t lhs_temp = (*lhs_vec + lhs_offset); + lhs_vec++; + acc_0 += lhs_temp * (*rhs_0 + rhs_offset); + rhs_0++; + } + acc_0 = arm_nn_requantize(acc_0, dst_multiplier, dst_shift); + + // Clamp the result + acc_0 = MAX(acc_0, activation_min); + acc_0 = MIN(acc_0, activation_max); + *dst = (q15_t)acc_0; + dst += dst_offset; + } + +#else + + int32_t row_loop_cnt = rhs_rows / 3; + + for (int i_row_loop_cnt = 0; i_row_loop_cnt < row_loop_cnt; i_row_loop_cnt++) + { + const q7_t *lhs_ptr = lhs; + const q7_t *rhs_ptr_0 = &rhs[0]; + const q7_t *rhs_ptr_1 = &rhs[rhs_cols]; + const q7_t *rhs_ptr_2 = &rhs[rhs_cols * 2]; + + q31_t res00 = 0; + q31_t res01 = 0; + q31_t res02 = 0; + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + const q31_t rhs_value0 = (int8_t)*rhs_ptr_0; + const q31_t rhs_value1 = (int8_t)*rhs_ptr_1; + const q31_t rhs_value2 = (int8_t)*rhs_ptr_2; + const q31_t lhs_value = (int8_t)*lhs_ptr + lhs_offset; + + res00 += lhs_value * rhs_value0; + res01 += lhs_value * rhs_value1; + res02 += lhs_value * rhs_value2; + + ++rhs_ptr_0; + ++rhs_ptr_1; + ++rhs_ptr_2; + ++lhs_ptr; + } + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + res01 = arm_nn_requantize(res01, dst_multiplier, dst_shift); + res02 = arm_nn_requantize(res02, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + res01 = MAX(res01, activation_min); + res01 = MIN(res01, activation_max); + res02 = MAX(res02, activation_min); + res02 = MIN(res02, activation_max); + + *dst = (q15_t)res00; + *(dst + dst_offset) = (q15_t)res01; + *(dst + 2 * dst_offset) = (q15_t)res02; + dst += 3 * dst_offset; + rhs += 3 * rhs_cols; + } + + const int loop_cnt = rhs_rows % 3; + + for (int i_loop_cnt = 0; i_loop_cnt < loop_cnt; i_loop_cnt++) + { + const q7_t *lhs_ptr = &lhs[0]; + const q7_t *rhs_ptr = &rhs[0]; + + q31_t res00 = 0; + + for (int32_t rhs_cols_idx = 0; rhs_cols_idx < rhs_cols; ++rhs_cols_idx) + { + q31_t rhs_value0 = (int8_t)rhs_ptr[0] + rhs_offset; + q31_t lhs_value = (int8_t)lhs_ptr[0] + lhs_offset; + + res00 += lhs_value * rhs_value0; + + ++rhs_ptr; + ++lhs_ptr; + } + + // Quantize down + res00 = arm_nn_requantize(res00, dst_multiplier, dst_shift); + + // Clamp the result + res00 = MAX(res00, activation_min); + res00 = MIN(res00, activation_max); + + *dst = (q15_t)res00; + dst += dst_offset; + rhs += rhs_cols; + } +#endif + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 0000000..5a8cea2 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, 0x5e, 0x5f, 0x61, + 0x62, 0x63, 0x65, 0x66, 0x67, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, + 0x75, 0x76, 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, 0x06, + 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, 0x0f, 0x10, 0x11, 0x12, + 0x13, 0x14, 0x15, 0x16, 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, + 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, + 0x5a57, 0x5bfb, 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, 0x68a6, 0x69d2, 0x6af1, 0x6c05, + 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, + 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, + 0x7e69, 0x7e81, 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, + 0x7f55, 0x7f5f, 0x7f69, 0x7f72, 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, + 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, + 0x7ff4, 0x7ff4, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, + 0x0017, 0x0019, 0x001a, 0x001c, 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, + 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, + 0x013e, 0x0152, 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, + 0x02f1, 0x0320, 0x0353, 0x0388, 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, + 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, + 0x1f5f, 0x20e0, 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, 0x3053, 0x3238, 0x3424, 0x3615, + 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, + 0x4cd3, 0x4dc8, 0x4ebb, 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, 0x56ef, 0x57cd, + 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, + 0x62cc, 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, 0x68a6, 0x693d, 0x69d2, 0x6a63, + 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, 0x0f42, + 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, + 0x162e, 0x16c3, 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, 0x1c81, 0x1d34, 0x1dea, + 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, + 0x351b, 0x3615, 0x370f, 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, + 0x792a, 0x798f, 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, + 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, 0x7e98, 0x7eae, + 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, + 0x7fc8, 0x7fcc, 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, + 0x7fe9, 0x7fea, 0x7feb, 0x7fed, 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, 0x000b, 0x000c, + 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, + 0x0048, 0x004c, 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, 0x0085, 0x008e, 0x0097, 0x00a1, + 0x00ab, 0x00b6, 0x00c2, 0x00ce, 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, 0x0168, 0x017f, + 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, + 0x08a5, 0x092a, 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, 0x61, 0x65, 0x68, + 0x6a, 0x6d, 0x6f, 0x71, 0x72, 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, 0x85, 0x85, 0x86, 0x87, + 0x88, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, + 0xbf, 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, + 0x5a1a, 0x5df6, 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, 0x73dc, 0x753a, 0x7672, 0x7788, + 0x787f, 0x795b, 0x7a1e, 0x7acb, 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, + 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, + 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, + 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, + 0x8006, 0x8007, 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, + 0x8024, 0x8029, 0x802f, 0x8035, 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, + 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, + 0x9869, 0x9b50, 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, 0xc4d9, 0xcb52, 0xd221, 0xd941, + 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, + 0x3151, 0x34ae, 0x37f6, 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, 0x514d, 0x53a3, + 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, + 0x6b6e, 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, 0x73dc, 0x7490, 0x753a, 0x75da, + 0x7672, 0x7701, 0x7788, 0x7807, 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, 0x849b, + 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, + 0x8ac6, 0x8b70, 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, 0x936b, 0x9492, 0x95c9, + 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, + 0xd5a8, 0xd941, 0xdcec, 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, + 0x7f30, 0x7f48, 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, + 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, 0x7ff8, 0x7ff9, + 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8002, + 0x8002, 0x8002, 0x8002, 0x8003, 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, 0x8008, 0x8009, + 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, + 0x8156, 0x8183, 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 0000000..6f2f575 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: May 29, 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.
+ *
+ * + */ + +void arm_q7_to_q15_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; + uint32_t blkCnt; + +#if defined(ARM_MATH_DSP) + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + while (blkCnt > 0u) + { + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remaining two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + out2 = (int32_t)__PKHTB(in1, in2, 16); + out1 = (int32_t)__PKHBT(in2, in1, 16); +#else + out1 = (int32_t)__PKHTB(in1, in2, 16); + out2 = (int32_t)__PKHBT(in2, in1, 16); +#endif + arm_nn_write_q15x2_ia(&pDst, out1); + arm_nn_write_q15x2_ia(&pDst, out2); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of nndata_convert group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 0000000..8abbc3a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: July 20, 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t *pSrc, q15_t *pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = arm_nn_read_q7x4_ia(&pIn); + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR((uint32_t)in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); +#else + arm_nn_write_q7x4_ia((q7_t **)&pDst, in1); + arm_nn_write_q7x4_ia((q7_t **)&pDst, in2); +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t)*pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of q7_to_x group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c new file mode 100644 index 0000000..765929d --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_with_offset.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_with_offset.c + * Description: Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. The re-ordering + * is a signature of sign extension intrinsic(DSP extension). + * + * $Date: May 29, 2020 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to a reordered Q15 vector with an added offset. + * + * @note Refer header file for details. + * + */ + +void arm_q7_to_q15_reordered_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + +#if defined(ARM_MATH_DSP) + uint32_t block_cnt; + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = (q31_t)__PKHBT(offset, offset, 16); + while (block_cnt > 0u) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + out_q15x2_1 = __SXTAB16(offset_q15x2, __ROR((uint32_t)in_q7x4, 8)); + out_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4u; + + while (block_cnt > 0u) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +#else + (void)src; + (void)dst; + (void)block_size; + (void)offset; + /* Not available */ +#endif +} + +/** + * @} end of nndata_convert group + */ diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c new file mode 100644 index 0000000..ea29986 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_with_offset.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in_q7x4 compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in_q7x4 writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_with_offset.c + * Description: Converts the elements of the Q7 vector to Q15 vector with an added offset + * + * $Date: March 3, 2020 + * $Revision: V.2.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +void arm_q7_to_q15_with_offset(const q7_t *src, q15_t *dst, uint32_t block_size, q15_t offset) +{ + int block_cnt; + +#if defined(ARM_MATH_MVEI) + + int16x8_t source; + const int16x8_t source_offset = vdupq_n_s16(offset); + block_cnt = block_size / 8; + + while (block_cnt > 0) + { + source = vldrbq_s16(src); + source = vaddq_s16(source, source_offset); + vstrhq_s16(dst, source); + dst += 8; + src += 8; + block_cnt--; + } + + block_cnt = block_size & 0x7; + +#elif defined(ARM_MATH_DSP) + /* Run the below code for cores that support SIMD instructions */ + q31_t in_q7x4; + q31_t in_q15x2_1; + q31_t in_q15x2_2; + q31_t out_q15x2_1; + q31_t out_q15x2_2; + + /*loop unrolling */ + block_cnt = block_size >> 2; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. */ + const q31_t offset_q15x2 = __PKHBT(offset, offset, 16); + while (block_cnt > 0) + { + /* convert from q7 to q15 and then store the results in the destination buffer */ + in_q7x4 = arm_nn_read_q7x4_ia(&src); + + /* Extract and sign extend each of the four q7 values to q15 */ + in_q15x2_1 = __SXTAB16(offset_q15x2, __ROR(in_q7x4, 8)); + in_q15x2_2 = __SXTAB16(offset_q15x2, in_q7x4); + + out_q15x2_2 = __PKHTB(in_q15x2_1, in_q15x2_2, 16); + out_q15x2_1 = __PKHBT(in_q15x2_2, in_q15x2_1, 16); + + arm_nn_write_q15x2_ia(&dst, out_q15x2_1); + arm_nn_write_q15x2_ia(&dst, out_q15x2_2); + + block_cnt--; + } + /* Handle left over samples */ + block_cnt = block_size % 0x4; + +#else + /* Run the below code for Cortex-M0 */ + /* Loop over block_size number of values */ + block_cnt = block_size; +#endif + + while (block_cnt > 0) + { + *dst++ = (q15_t)*src++ + offset; + + /* Decrement the loop counter */ + block_cnt--; + } +} + +/** + * @} end of nndata_convert group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt new file mode 100644 index 0000000..a37503b --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +file(GLOB SRC_S16 "./*_s16.c") +target_sources(cmsis-nn PRIVATE ${SRC} ${SRC_S16}) + + + diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c new file mode 100644 index 0000000..5cd2b1c --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s16.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s16.c + * Description: Pooling function implementations + * + * $Date: 3. February 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s16 average pooling function + * + * Refer to header file for details. + * + */ +arm_status arm_avgpool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q15_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q15_t *dst) +{ + (void)ctx; + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + /* Reference C code adapted from CMSIS-NN arm_avgpool_s8.c. + */ + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + sum += src[i_ch_in + ch_src * (k_x + base_idx_x + (k_y + base_idx_y) * input_x)]; + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + + return ARM_MATH_SUCCESS; +} + +int32_t arm_avgpool_s16_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + (void)ch_src; + return 0; +} + +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c new file mode 100644 index 0000000..3e9861e --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_avgpool_s8.c @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_avgpool_s8.c + * Description: Pooling function implementations + * + * $Date: 01. March 2021 + * $Revision: V.2.0.4 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +static void scale_q31_to_q7_and_clamp(const q31_t *buffer, + q7_t *target, + int32_t length, + const int32_t count, + const int act_min, + const int act_max) +{ + const int half_count = count / 2; + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return; + } + + for (int i = 0; i < length; i++) + { + int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count); + sum = sum / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + target[i] = (q7_t)sum; + } +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * s8 average pooling function + * + * Refer to header file for details. + * + */ + +#if defined(ARM_MATH_MVEI) + +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + (void)ctx; + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + int32_t i_x, i_y; + int32_t k_x, k_y; + + for (i_y = 0; i_y < output_y; i_y++) + { + for (i_x = 0; i_x < output_x; i_x++) + { + + int32_t k_y_start, k_y_end; + int32_t k_x_start, k_x_end; + int32_t chCnt; + const int8_t *pTmp, *pTmpInner; + int8_t *pDst; + + k_y_start = MAX(0, i_y * stride_y - pad_y); + k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y); + + k_x_start = MAX(0, i_x * stride_x - pad_x); + k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x); + + pTmp = src; + pDst = &dst[ch_src * (i_x + i_y * output_x)]; + + chCnt = ch_src >> 4; + while (chCnt > 0) + { + int32x4_t sumV1, sumV2, sumV3, sumV4; + + int8x16_t tempV; + int16x8_t tempVLO, tempVHI; + int32x4_t tempVLOLO, tempVLOHI, tempVHILO, tempVHIHI; + int32_t count = 0; + + sumV1 = vdupq_n_s32(0); + sumV2 = vdupq_n_s32(0); + sumV3 = vdupq_n_s32(0); + sumV4 = vdupq_n_s32(0); + + for (k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (k_x = k_x_start; k_x < k_x_end; k_x++) + { + pTmpInner = pTmp + (ch_src * (k_x + k_y * input_x)); + tempV = vldrbq_s8(pTmpInner); + + tempVLO = vmovlbq_s8(tempV); + tempVHI = vmovltq_s8(tempV); + + tempVLOLO = vmovlbq_s16(tempVLO); + tempVLOHI = vmovltq_s16(tempVLO); + + tempVHILO = vmovlbq_s16(tempVHI); + tempVHIHI = vmovltq_s16(tempVHI); + + sumV1 = vaddq_s32(sumV1, tempVLOLO); + sumV2 = vaddq_s32(sumV2, tempVLOHI); + sumV3 = vaddq_s32(sumV3, tempVHILO); + sumV4 = vaddq_s32(sumV4, tempVHIHI); + + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sumV1[0] = sumV1[0] > 0 ? (sumV1[0] + count / 2) / count : (sumV1[0] - count / 2) / count; + sumV1[1] = sumV1[1] > 0 ? (sumV1[1] + count / 2) / count : (sumV1[1] - count / 2) / count; + sumV1[2] = sumV1[2] > 0 ? (sumV1[2] + count / 2) / count : (sumV1[2] - count / 2) / count; + sumV1[3] = sumV1[3] > 0 ? (sumV1[3] + count / 2) / count : (sumV1[3] - count / 2) / count; + + sumV2[0] = sumV2[0] > 0 ? (sumV2[0] + count / 2) / count : (sumV2[0] - count / 2) / count; + sumV2[1] = sumV2[1] > 0 ? (sumV2[1] + count / 2) / count : (sumV2[1] - count / 2) / count; + sumV2[2] = sumV2[2] > 0 ? (sumV2[2] + count / 2) / count : (sumV2[2] - count / 2) / count; + sumV2[3] = sumV2[3] > 0 ? (sumV2[3] + count / 2) / count : (sumV2[3] - count / 2) / count; + + sumV3[0] = sumV3[0] > 0 ? (sumV3[0] + count / 2) / count : (sumV3[0] - count / 2) / count; + sumV3[1] = sumV3[1] > 0 ? (sumV3[1] + count / 2) / count : (sumV3[1] - count / 2) / count; + sumV3[2] = sumV3[2] > 0 ? (sumV3[2] + count / 2) / count : (sumV3[2] - count / 2) / count; + sumV3[3] = sumV3[3] > 0 ? (sumV3[3] + count / 2) / count : (sumV3[3] - count / 2) / count; + + sumV4[0] = sumV4[0] > 0 ? (sumV4[0] + count / 2) / count : (sumV4[0] - count / 2) / count; + sumV4[1] = sumV4[1] > 0 ? (sumV4[1] + count / 2) / count : (sumV4[1] - count / 2) / count; + sumV4[2] = sumV4[2] > 0 ? (sumV4[2] + count / 2) / count : (sumV4[2] - count / 2) / count; + sumV4[3] = sumV4[3] > 0 ? (sumV4[3] + count / 2) / count : (sumV4[3] - count / 2) / count; + + sumV1 = vmaxq_s32(sumV1, vdupq_n_s32(act_min)); + sumV1 = vminq_s32(sumV1, vdupq_n_s32(act_max)); + + sumV2 = vmaxq_s32(sumV2, vdupq_n_s32(act_min)); + sumV2 = vminq_s32(sumV2, vdupq_n_s32(act_max)); + + sumV3 = vmaxq_s32(sumV3, vdupq_n_s32(act_min)); + sumV3 = vminq_s32(sumV3, vdupq_n_s32(act_max)); + + sumV4 = vmaxq_s32(sumV4, vdupq_n_s32(act_min)); + sumV4 = vminq_s32(sumV4, vdupq_n_s32(act_max)); + + tempVLO = vmovnbq_s32(tempVLO, sumV1); + tempVLO = vmovntq_s32(tempVLO, sumV2); + + tempVHI = vmovnbq_s32(tempVHI, sumV3); + tempVHI = vmovntq_s32(tempVHI, sumV4); + + tempV = vmovnbq_s16(tempV, tempVLO); + tempV = vmovntq_s16(tempV, tempVHI); + + vstrbq_s8(pDst, tempV); + pDst += 16; + + chCnt--; + pTmp += 16; + } + + chCnt = ch_src & 0xF; + while (chCnt > 0) + { + int32_t sum = 0; + int32_t count = 0; + + for (k_y = k_y_start; k_y < k_y_end; k_y++) + { + for (k_x = k_x_start; k_x < k_x_end; k_x++) + { + sum += pTmp[ch_src * (k_x + k_y * input_x)]; + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + *pDst++ = sum; + + chCnt--; + pTmp++; + } + } + } + return ARM_MATH_SUCCESS; +} + +#else +arm_status arm_avgpool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t ch_src = input_dims->c; + + if (ctx->buf == NULL && arm_avgpool_s8_get_buffer_size(output_dims->w, input_dims->c)) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer = (q31_t *)ctx->buf; + +#if defined(ARM_MATH_DSP) + + /* Run the following code for CPU's with DSP extension + */ + for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++) + { + for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: + (base_idx_ + kernel__start) >= 0 */ + const int32_t kernel_y_start = MAX(0, -idx_y); + const int32_t kernel_x_start = MAX(0, -idx_x); + + /* Condition for kernel end dimension: + (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x); + + int count = 0; + + for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x); + + if (count == 0) + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = start[i]; + } + } + else + { + for (int i = 0; i < ch_src; i++) + { + buffer[i] = __QADD(start[i], buffer[i]); + } + } + count++; + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + scale_q31_to_q7_and_clamp(buffer, dst, ch_src, count, act_min, act_max); + dst += ch_src; + } + } +#else + + /* Reference C code adapted from CMSIS-NN arm_avepool_q7_HWC. + */ + (void)buffer; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_y = 0; i_y < output_y; i_y++) + { + for (i_x = 0; i_x < output_x; i_x++) + { + for (i_ch_in = 0; i_ch_in < ch_src; i_ch_in++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - pad_y; k_y < i_y * stride_y - pad_y + kernel_y; k_y++) + { + for (k_x = i_x * stride_x - pad_x; k_x < i_x * stride_x - pad_x + kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < input_y && k_x < input_x) + { + sum += src[i_ch_in + ch_src * (k_x + k_y * input_x)]; + count++; + } + } + } + + // Prevent static code issue DIVIDE_BY_ZERO. + if (count == 0) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count; + sum = MAX(sum, act_min); + sum = MIN(sum, act_max); + + dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum; + } + } + } + +#endif + return ARM_MATH_SUCCESS; +} + +#endif /* ARM_MATH_MVEI */ + +int32_t arm_avgpool_s8_get_buffer_size(const int output_x, const int ch_src) +{ + (void)output_x; + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + return (ch_src * sizeof(int32_t)); +#else + (void)ch_src; + return 0; +#endif +} +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c new file mode 100644 index 0000000..483f874 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s16.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s16.c + * Description: Pooling function implementations + * + * $Date: 24. January 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger(int16_t *base, const int16_t *target, int32_t length) +{ + q15_t *dst = base; + const q15_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q15x2(dst); + comp_max.word = arm_nn_read_q15x2_ia(&src); + + if (comp_max.half_words[0] > ref_max.half_words[0]) + { + ref_max.half_words[0] = comp_max.half_words[0]; + } + if (comp_max.half_words[1] > ref_max.half_words[1]) + { + ref_max.half_words[1] = comp_max.half_words[1]; + } + + arm_nn_write_q15x2_ia(&dst, ref_max.word); + + cnt--; + } + + if (length & 0x1) + { + if (*src > *dst) + { + *dst = *src; + } + } +} + +static void clamp_output(int16_t *source, int32_t length, const int16_t act_min, const int16_t act_max) +{ + union arm_nnword in; + int32_t cnt = length >> 1; + + while (cnt > 0l) + { + in.word = arm_nn_read_q15x2(source); + + in.half_words[0] = MAX(in.half_words[0], act_min); + in.half_words[0] = MIN(in.half_words[0], act_max); + in.half_words[1] = MAX(in.half_words[1], act_min); + in.half_words[1] = MIN(in.half_words[1], act_max); + + arm_nn_write_q15x2_ia(&source, in.word); + cnt--; + } + + if (length & 0x1) + { + int16_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source = comp; + } +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s16 max pooling function + * + * Refer to header file for details. + * + */ + +arm_status arm_max_pool_s16(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const int16_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + int16_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int16_t act_min = pool_params->activation.min; + const int16_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + int16_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const int16_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + memcpy(dst, start, channel_in * sizeof(int16_t)); + count++; + } + else + { + compare_and_replace_if_larger(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c new file mode 100644 index 0000000..4fbbc91 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_max_pool_s8.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_max_pool_s8.c + * Description: Pooling function implementations + * + * $Date: 20. July 2021 + * $Revision: V.2.0.3 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +static void compare_and_replace_if_larger_q7(q7_t *base, const q7_t *target, int32_t length) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + const int8x16_t op_1 = vldrbq_z_s8(base, p); + const int8x16_t op_2 = vldrbq_z_s8(target, p); + const int8x16_t max = vmaxq_m_s8(vuninitializedq_s8(), op_1, op_2, p); + vstrbq_p_s8(base, max, p); + base += 16; + target += 16; + length -= 16; + } +#else + q7_t *dst = base; + const q7_t *src = target; + union arm_nnword ref_max; + union arm_nnword comp_max; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + ref_max.word = arm_nn_read_q7x4(dst); + comp_max.word = arm_nn_read_q7x4_ia(&src); + + if (comp_max.bytes[0] > ref_max.bytes[0]) + { + ref_max.bytes[0] = comp_max.bytes[0]; + } + if (comp_max.bytes[1] > ref_max.bytes[1]) + { + ref_max.bytes[1] = comp_max.bytes[1]; + } + if (comp_max.bytes[2] > ref_max.bytes[2]) + { + ref_max.bytes[2] = comp_max.bytes[2]; + } + if (comp_max.bytes[3] > ref_max.bytes[3]) + { + ref_max.bytes[3] = comp_max.bytes[3]; + } + + arm_nn_write_q7x4_ia(&dst, ref_max.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + if (*src > *dst) + { + *dst = *src; + } + dst++; + src++; + cnt--; + } +#endif +} + +static void clamp_output(q7_t *source, int32_t length, const int32_t act_min, const int32_t act_max) +{ +#if defined(ARM_MATH_MVEI) + int32_t loop_count = (length + 15) / 16; + for (int i = 0; i < loop_count; i++) + { + mve_pred16_t p = vctp8q((uint32_t)length); + length -= 16; + const int8x16_t src = vldrbq_z_s8(source, p); + const int8x16_t predicated_min = vdupq_m_n_s8(vuninitializedq_s8(), (int8_t)act_min, p); + const int8x16_t predicated_max = vdupq_m_n_s8(vuninitializedq_s8(), (int8_t)act_max, p); + int8x16_t res = vmaxq_m_s8(vuninitializedq_s8(), src, predicated_min, p); + res = vminq_m_s8(vuninitializedq_s8(), res, predicated_max, p); + vstrbq_p_s8(source, res, p); + source += 16; + } +#else + union arm_nnword in; + int32_t cnt = length >> 2; + + while (cnt > 0l) + { + in.word = arm_nn_read_q7x4(source); + + in.bytes[0] = MAX(in.bytes[0], act_min); + in.bytes[0] = MIN(in.bytes[0], act_max); + in.bytes[1] = MAX(in.bytes[1], act_min); + in.bytes[1] = MIN(in.bytes[1], act_max); + in.bytes[2] = MAX(in.bytes[2], act_min); + in.bytes[2] = MIN(in.bytes[2], act_max); + in.bytes[3] = MAX(in.bytes[3], act_min); + in.bytes[3] = MIN(in.bytes[3], act_max); + + arm_nn_write_q7x4_ia(&source, in.word); + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0l) + { + int32_t comp = *source; + comp = MAX(comp, act_min); + comp = MIN(comp, act_max); + *source++ = (int8_t)comp; + cnt--; + } +#endif +} + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/* + * Optimized s8 max pooling function + * + * Refer to header file for details. + * + */ + +arm_status arm_max_pool_s8(const cmsis_nn_context *ctx, + const cmsis_nn_pool_params *pool_params, + const cmsis_nn_dims *input_dims, + const q7_t *src, + const cmsis_nn_dims *filter_dims, + const cmsis_nn_dims *output_dims, + q7_t *dst) +{ + const int32_t input_y = input_dims->h; + const int32_t input_x = input_dims->w; + const int32_t output_y = output_dims->h; + const int32_t output_x = output_dims->w; + const int32_t stride_y = pool_params->stride.h; + const int32_t stride_x = pool_params->stride.w; + const int32_t kernel_y = filter_dims->h; + const int32_t kernel_x = filter_dims->w; + const int32_t pad_y = pool_params->padding.h; + const int32_t pad_x = pool_params->padding.w; + const int32_t act_min = pool_params->activation.min; + const int32_t act_max = pool_params->activation.max; + const int32_t channel_in = input_dims->c; + (void)ctx; + q7_t *dst_base = dst; + + for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++) + { + for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++) + { + /* Condition for kernel start dimension: (base_idx_ + kernel__start) >= 0 */ + const int32_t ker_y_start = MAX(0, -base_idx_y); + const int32_t ker_x_start = MAX(0, -base_idx_x); + + /* Condition for kernel end dimension: (base_idx_ + kernel__end) < dim_src_ */ + const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y); + const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x); + + int count = 0; + + for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++) + { + for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++) + { + const q7_t *start = src + channel_in * (k_x + base_idx_x + (k_y + base_idx_y) * input_x); + + if (count == 0) + { + arm_memcpy_q7(dst, start, channel_in); + count++; + } + else + { + compare_and_replace_if_larger_q7(dst, start, channel_in); + } + } + } + /* 'count' is expected to be non-zero here. */ + dst += channel_in; + } + } + + clamp_output(dst_base, output_x * output_y * channel_in, act_min, act_max); + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 0000000..5a3b1af --- /dev/null +++ b/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,464 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 20. July 2021 + * $Revision: V.1.1.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t *buffer, q7_t *target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t)(buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t *base, // base data + const q7_t *target, // compare target + const uint16_t length // data length +) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = arm_nn_read_q7x4((const q7_t *)pIn); + com.word = arm_nn_read_q7x4_ia((const q7_t **)&pCom); + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + arm_nn_write_q7x4_ia(&pIn, in.word); + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t *base, q7_t *target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = arm_nn_read_q7x4_ia((const q7_t **)&pV); + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo1, in)); + + in = arm_nn_read_q15x2(pCnt); + arm_nn_write_q15x2_ia(&pCnt, __QADD16(vo2, in)); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + +/** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA Not used + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_maxpool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + (void)bufferA; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void arm_avepool_q7_HWC(q7_t *Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t *bufferA, + q7_t *Im_out) +{ + +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *)bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } + else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } + else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } + else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } + else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + (void)bufferA; + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ +} + +/** + * @} end of Pooling group + */ diff --git a/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt new file mode 100644 index 0000000..9d3f543 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ReshapeFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_*.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c b/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c new file mode 100644 index 0000000..5464ca1 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/ReshapeFunctions/arm_reshape_s8.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2010-2021 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_reshape_s8.c + * Description: Reshape a s8 vector + * + * $Date: September 2019 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Reshape + * @{ + */ + +/** + * Basic s8 reshape function. + * + * Refer header file for details. + * + */ + +void arm_reshape_s8(const int8_t *input, int8_t *output, const uint32_t total_size) +{ + arm_memcpy_q7(output, input, total_size); +} + +/** + * @} end of Reshape group + */ diff --git a/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt new file mode 100644 index 0000000..67c3f79 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SVDFunctions/CMakeLists.txt @@ -0,0 +1,20 @@ +# +# Copyright (c) 2019-2021 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC}) diff --git a/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c b/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c new file mode 100644 index 0000000..ea092dc --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_s8.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function + * + * $Date: 28 April 2022 + * $Revision: V.3.0.1 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite with 8 bit state tensor + * + * Refer to header file for details. + * + */ + +arm_status arm_svdf_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q7_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q7_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + if (input_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_a = (q31_t *)input_ctx->buf; + + if (output_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + // Left shift state + memmove((int8_t *)state_data, + (int8_t *)state_data + 1, + (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int8_t))); + + // Matrix multiplication input * feature weight + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q7_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_status res = arm_nn_vec_mat_mult_t_s8(input, + weight, + NULL, + res_ptr, + -zp_in, + 0, + 0, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max, + time_batches); + + if (res != ARM_MATH_SUCCESS) + { + return res; + } + } + + // Matrix multiplicate time weight * state tensors + { + q31_t *ptr_a = buffer_a; + const int8_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const int8_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + // Perform matrix multiplication in blocks of four + int j = 0; + int32_t block_count = time_batches >> 2; + for (int i = 0; i < block_count; i++) + { + j += 4; + + q31_t r1_1, r1_2, r2_1, r2_2; + v1 = read_and_pad_reordered(v1, &r1_1, &r1_2); + v2 = read_and_pad_reordered(v2, &r2_1, &r2_2); + sum = __SMLAD(r1_1, r2_1, sum); + sum = __SMLAD(r1_2, r2_2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c b/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c new file mode 100644 index 0000000..988409b --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SVDFunctions/arm_svdf_state_s16_s8.c @@ -0,0 +1,267 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_svdf_s8.c + * Description: S8 basic SVDF layer function with s16 state tensor + * + * $Date: 28 April 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M processors + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup SVDF + * @{ + */ + +/* + * S8 SVDF layer function for TensorFlow Lite with 16 bit state tensor + * + * Refer to header file for details. + * + */ + +arm_status arm_svdf_state_s16_s8(const cmsis_nn_context *input_ctx, + const cmsis_nn_context *output_ctx, + const cmsis_nn_svdf_params *svdf_params, + const cmsis_nn_per_tensor_quant_params *input_quant_params, + const cmsis_nn_per_tensor_quant_params *output_quant_params, + const cmsis_nn_dims *input_dims, + const q7_t *input_data, + const cmsis_nn_dims *state_dims, + q15_t *state_data, + const cmsis_nn_dims *weights_feature_dims, + const q7_t *weights_feature_data, + const cmsis_nn_dims *weights_time_dims, + const q15_t *weights_time_data, + const cmsis_nn_dims *bias_dims, + const q31_t *bias_data, + const cmsis_nn_dims *output_dims, + q7_t *output_data) +{ + (void)bias_dims; + (void)state_dims; + (void)output_dims; + + const q31_t multiplier_in = input_quant_params->multiplier; + const q31_t shift_in = input_quant_params->shift; + const q31_t multiplier_out = output_quant_params->multiplier; + const q31_t shift_2 = output_quant_params->shift; + const int32_t zp_in = svdf_params->input_offset; + const int32_t zp_out = svdf_params->output_offset; + const int32_t in_activation_min = svdf_params->input_activation.min; + const int32_t in_activation_max = svdf_params->input_activation.max; + const int32_t out_activation_min = svdf_params->output_activation.min; + const int32_t out_activation_max = svdf_params->output_activation.max; + const int16_t rank = svdf_params->rank; + + const int32_t input_batches = input_dims->n; + const int32_t input_height = input_dims->h; + const int32_t feature_batches = weights_feature_dims->n; + const int32_t time_batches = weights_time_dims->h; + const int32_t unit_count = feature_batches / rank; + + if (input_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_a = (q31_t *)input_ctx->buf; + + if (output_ctx->buf == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + q31_t *buffer_b = (q31_t *)output_ctx->buf; + + // Left shift state + memmove((q15_t *)state_data, + (q15_t *)state_data + 1, + (size_t)((input_batches * feature_batches * time_batches - 1) * (int32_t)sizeof(int16_t))); + + // Matrix multiplication input * feature weight + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q15_t *res_ptr = state_data + (time_batches * i_batch * feature_batches) + (time_batches - 1); + const q7_t *weight = weights_feature_data; + const q7_t *input = input_data + i_batch * input_height; + + arm_status res = arm_nn_vec_mat_mult_t_svdf_s8(input, + weight, + res_ptr, + -zp_in, + 0, + time_batches, + multiplier_in, + shift_in, + input_height, + feature_batches, + in_activation_min, + in_activation_max); + + if (res != ARM_MATH_SUCCESS) + { + return res; + } + } + + { + // Matrix multiplication time weight * state tensors + q31_t *ptr_a = buffer_a; + const q15_t *v2 = state_data; + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + const q15_t *v1 = weights_time_data; + + for (int i_feature_batch = 0; i_feature_batch < feature_batches; i_feature_batch++) + { + *ptr_a = 0; + int32_t sum = 0; +#if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI) + // Perform matrix multiplication in blocks of two + int j = 0; + int32_t block_count = time_batches >> 1; + for (int i = 0; i < block_count; i++) + { + j += 2; + q31_t r1 = arm_nn_read_q15x2_ia(&v1); + q31_t r2 = arm_nn_read_q15x2_ia(&v2); + + sum = __SMLAD(r1, r2, sum); + } + + // Process the remaining data + for (; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#else + for (int j = 0; j < time_batches; j++) + { + sum += *v1 * *v2; + v1++; + v2++; + } +#endif + + *ptr_a = sum; + ptr_a++; + } + } + } + + if (bias_data) + { + if (unit_count == feature_batches) + { + for (int i = 0; i < input_batches; i++) + { + q31_t *output_temp = buffer_b + i * feature_batches; + const q31_t *ptr_a = buffer_a + i * feature_batches; + + const int32_t *bi = bias_data; + for (int j = 0; j < feature_batches; j++) + { + output_temp[j] = ptr_a[j] + bi[j]; + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = bias_data[i]; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + } + else + { + for (int i_batch = 0; i_batch < input_batches; i_batch++) + { + q31_t *output_data_temp = buffer_b + i_batch * unit_count; + q31_t *ptr_a = buffer_a + i_batch * feature_batches; + + for (int i = 0; i < unit_count; i++) + { + int32_t sum = 0; + for (int j = 0; j < rank; j++) + { + sum += *ptr_a; + ptr_a++; + } + output_data_temp[i] = sum; + } + } + } + +#if defined(ARM_MATH_MVEI) + int32_t num_elements = input_batches * unit_count; + const int32_t loop_count = (num_elements + 3) / 4; + for (int i_op = 0; i_op < loop_count; i_op++) + { + mve_pred16_t p = vctp32q((uint32_t)num_elements); + int32x4_t op = vldrwq_z_s32(buffer_b, p); + op = arm_requantize_mve(op, multiplier_out, shift_2); + op = vaddq_n_s32(op, zp_out); + const int32x4_t min_vec = vdupq_n_s32((int8_t)out_activation_min); + const int32x4_t max_vec = vdupq_n_s32((int8_t)out_activation_max); + op = vmaxq_s32(op, min_vec); + op = vminq_s32(op, max_vec); + vstrbq_p_s32(output_data, op, p); + output_data += 4; + buffer_b += 4; + num_elements -= 4; + } +#else + for (int i = 0; i < input_batches * unit_count; i++) + { + output_data[i] = (q7_t)CLAMP( + arm_nn_requantize(buffer_b[i], multiplier_out, shift_2) + zp_out, out_activation_max, out_activation_min); + } +#endif + + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of SVDF group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt new file mode 100644 index 0000000..622b990 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/CMakeLists.txt @@ -0,0 +1,22 @@ +# +# Copyright (c) 2019-2022 Arm Limited. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +file(GLOB SRC "./*_s8.c") +target_sources(cmsis-nn PRIVATE ${SRC} arm_softmax_s8_s16.c + arm_softmax_s16.c + arm_nn_softmax_common_s8.c) diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c new file mode 100644 index 0000000..84d1ac8 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_nn_softmax_common_s8.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_softmax_common_s8.c + * Description: Softmax with s8 input and output of s8 or s16. + * + * $Date: 17 March 2022 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M processors + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/* + * Softmax function with s8 input and output of s8 or s16. + * + * Refer header file for details. + * + */ +void arm_nn_softmax_common_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + const bool int16_output, + void *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ(sum); + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + int32_t bits_over_unit; + + if (int16_output) + { + int16_t *output_s16 = (int16_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 15; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q15_MIN; + output_s16[col] = (int16_t)CLAMP(res, (int32_t)NN_Q15_MAX, (int32_t)NN_Q15_MIN); + } + else + { + output_s16[col] = NN_Q15_MIN; + } + } + } + else + { + int8_t *output_s8 = (int8_t *)output + row_idx * row_size; + + bits_over_unit = ACCUM_BITS - headroom + 23; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q7_MIN; + output_s8[col] = (int8_t)CLAMP(res, (int32_t)NN_Q7_MAX, (int32_t)NN_Q7_MIN); + } + else + { + output_s8[col] = NN_Q7_MIN; + } + } + } + + input += row_size; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 0000000..18f3e83 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t *vec_in, const uint16_t dim_vec, q15_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17 + base - vec_in[i], 5); + p_out[i] = (q15_t)__SSAT((output_base >> shift), 16); + } + else + { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 0000000..58eb990 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t *vec_in, const uint16_t dim_vec, q7_t *p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -128; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - (1 << 3); + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 3); + sum += 0x1 << shift; + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = (1 << 20) / sum; + + for (i = 0; i < dim_vec; i++) + { + + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__SSAT((output_base >> shift), 8); + } +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c new file mode 100644 index 0000000..e840893 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s16.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s16.c + * Description: S16 softmax function + * + * $Date: 9 March 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @addtogroup Softmax + * @{ + */ + +arm_status arm_softmax_s16(const int16_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const cmsis_nn_softmax_lut_s16 *softmax_params, + int16_t *output) +{ + int32_t col = 0; + int32_t row_idx; + + if (softmax_params->exp_lut == NULL || softmax_params->one_by_one_lut == NULL) + { + return ARM_MATH_ARGUMENT_ERROR; + } + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + int16_t max = *input; + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + int16_t *cached_exp_results = output; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + const int32_t scaled_diff = arm_nn_requantize(diff, mult, shift); + const int32_t symmetric_scaled_diff = scaled_diff + NN_Q15_MAX; + const int16_t saturated_symmetric_scaled_diff = MIN(MAX(symmetric_scaled_diff, NN_Q15_MIN), NN_Q15_MAX); + + // Lookup from exp table and cache result for next step + const int16_t index = (256 + (saturated_symmetric_scaled_diff >> 7)); + const int16_t offset = saturated_symmetric_scaled_diff & 0x7f; + const int16_t base = softmax_params->exp_lut[index]; + const int16_t slope = softmax_params->exp_lut[index + 1] - softmax_params->exp_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t result = (base + delta); + cached_exp_results[col] = result; + + sum += cached_exp_results[col]; + } + + const int32_t headroom = __CLZ(sum); + + // Compute the reciprocal 1/sum + const int32_t shifted_sum = (((sum) << (headroom - 1)) + (1 << 13)) >> 14; + + // Since LUT computes 1/(1 + x), compute x = (sum - 1) => -65536 + // Since LUT expects a symmetrical input, recenter from [UINT16_MIN, UINT16_MAX] to [INT16_MIN, INT16_MAX] => + // -32768 ==> So in total -65536 -32768 => -98304 + const int16_t symmetric_shifted_sum = shifted_sum - 98304; + + // Lookup from one by one table + const int16_t index = (256 + (symmetric_shifted_sum >> 7)); + const int16_t offset = symmetric_shifted_sum & 0x7f; + const int16_t base = softmax_params->one_by_one_lut[index]; + const int16_t slope = softmax_params->one_by_one_lut[index + 1] - softmax_params->one_by_one_lut[index]; + const int16_t delta = (slope * offset + 64) >> 7; + const int16_t one_by_one_result = (base + delta); + + for (col = 0; col < row_size; ++col) + { + const int16_t right_shift = 30 - headroom; + int32_t result = (cached_exp_results[col] * one_by_one_result) >> right_shift; + result = (result + 1) >> 1; // Last shift position and insert round + output[col] = (int16_t)result; + } + + output += row_size; + input += row_size; + } + + return ARM_MATH_SUCCESS; +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c new file mode 100644 index 0000000..fd70597 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2010-2022 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8.c + * Description: S8 softmax function + * + * $Date: 9 March 2022 + * $Revision: V.2.1.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +#ifdef ARM_MATH_MVEI +static int32x4_t arm_exp_on_negative_values_mve_32x4(int32x4_t val) +{ +#define SHIFT_START (24) + int32_t shift = SHIFT_START; + int32x4_t mask; + + const int32x4_t val_mod_minus_quarter = + vandq_s32(val, vdupq_n_s32((1 << SHIFT_START) - 1)) - vdupq_n_s32(1 << SHIFT_START); + const int32x4_t remainder = vsubq_s32(val_mod_minus_quarter, val); + const int32x4_t x = vaddq_n_s32(val_mod_minus_quarter << 5, 1 << 28); + const int32x4_t x2 = MUL_SAT_MVE(x, x); + const int32x4_t op_1 = DIV_POW2_MVE(MUL_SAT_MVE(x2, x2), 2) + MUL_SAT_MVE(x2, x); + const int32x4_t op_2 = x + DIV_POW2_MVE(MUL_SAT_MVE(op_1, vdupq_n_s32(715827883)) + x2, 1); + int32x4_t result = vdupq_n_s32(1895147668) + MUL_SAT_MVE(vdupq_n_s32(1895147668), op_2); + +#define SELECT_IF_NON_ZERO(x) \ + { \ + mve_pred16_t p = vcmpneq_n_s32(remainder & vdupq_n_s32(1 << shift++), 0); \ + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); \ + result = SELECT_USING_MASK(mask, MUL_SAT_MVE(result, vdupq_n_s32(x)), result); \ + } + + SELECT_IF_NON_ZERO(1672461947) + SELECT_IF_NON_ZERO(1302514674) + SELECT_IF_NON_ZERO(790015084) + SELECT_IF_NON_ZERO(290630308) + SELECT_IF_NON_ZERO(39332535) + SELECT_IF_NON_ZERO(720401) + SELECT_IF_NON_ZERO(242) + +#undef SELECT_IF_NON_ZERO + + mve_pred16_t p = vcmpeqq_n_s32(val, 0); + mask = vmvnq_m_s32(vdupq_n_s32(0), vdupq_n_s32(0), p); + + result = SELECT_USING_MASK(mask, vdupq_n_s32(NN_Q31_MAX), result); + return result; +} +#endif + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int8_t *output) +{ +#ifdef ARM_MATH_MVEI + +#define ACT_MIN ((int8_t)NN_Q7_MIN) +#define ACT_MAX ((int8_t)NN_Q7_MAX) + + const int32_t mask = (1 << shift); + + for (int i_num_rows = 0; i_num_rows < num_rows; ++i_num_rows) + { + int8_t max = ACT_MIN; + + int32_t vec_count = (row_size + 15) / 16; + uint32_t r_count = (uint32_t)row_size; + for (int i = 0; i < vec_count; i++) + { + mve_pred16_t p = vctp8q(r_count); + const int8x16_t ip = vldrbq_z_s8(&input[i * 16], p); + max = vmaxvq_p_s8(max, ip, p); + r_count -= 16; + } + + vec_count = row_size / 4; + int32_t idx = 0; + int32_t sum = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx * 4]); + ip = vsubq_n_s32(ip, max); + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + int32x4_t res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + + res = arm_exp_on_negative_values_mve_32x4(res); + res = DIV_POW2_MVE(res, ACCUM_BITS); + res = vpselq_s32(res, vdupq_n_s32(0), p); + sum += vaddvq_s32(res); + } + + vec_count--; + idx++; + } + + const int32_t tail_idx = row_size & ~3; + for (int i = 0; i < (row_size & 3); i++) + { + const int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); + + vec_count = row_size / 4; + idx = 0; + + while (vec_count) + { + int32x4_t ip = vldrbq_s32(&input[idx]); + ip = vsubq_n_s32(ip, max); + + mve_pred16_t p = vcmpgeq_n_s32(ip, diff_min); + + int32x4_t tmp_res; + + if (p != 0) + { + ip = vmulq_n_s32(ip, mask); + + tmp_res = MUL_SAT_MVE(ip, vdupq_n_s32(mult)); + tmp_res = arm_exp_on_negative_values_mve_32x4(tmp_res); + tmp_res = MUL_SAT_MVE(vdupq_n_s32(shifted_scale), tmp_res); + tmp_res = DIV_POW2_MVE(tmp_res, bits_over_unit); + tmp_res += vdupq_n_s32(ACT_MIN); + + tmp_res = vmaxq_s32(tmp_res, vdupq_n_s32(ACT_MIN)); + tmp_res = vminq_s32(tmp_res, vdupq_n_s32(ACT_MAX)); + tmp_res = vpselq_s32(tmp_res, vdupq_n_s32(ACT_MIN), p); + } + else + { + tmp_res = vdupq_n_s32(ACT_MIN); + } + vstrbq_s32(&output[idx], tmp_res); + vec_count--; + idx += 4; + } + + for (int i = 0; i < (row_size & 3); i++) + { + int32_t diff = input[tail_idx + i] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + + NN_Q7_MIN; + output[tail_idx + i] = (int8_t)CLAMP(res, (int32_t)ACT_MAX, (int32_t)ACT_MIN); + } + else + { + output[tail_idx + i] = ACT_MIN; + } + } + + input += row_size; + output += row_size; + } +#else + arm_nn_softmax_common_s8(input, num_rows, row_size, mult, shift, diff_min, false, (void *)output); +#endif +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c new file mode 100644 index 0000000..9ba0b9a --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_s8_s16.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2022 Arm Limited or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_s8_s16.c + * Description: S8 to s16 softmax function + * + * $Date: 7 January 2022 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +void arm_softmax_s8_s16(const int8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + int16_t *output) +{ + arm_nn_softmax_common_s8(input, num_rows, row_size, mult, shift, diff_min, true, (void *)output); +} +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c new file mode 100644 index 0000000..c4df8f8 --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_u8.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_u8.c + * Description: U8 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.2 + * + * Target Processor: Cortex-M CPUs + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_nnsupportfunctions.h" + +#define ACCUM_BITS 12 + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ +void arm_softmax_u8(const uint8_t *input, + const int32_t num_rows, + const int32_t row_size, + const int32_t mult, + const int32_t shift, + const int32_t diff_min, + uint8_t *output) +{ + const int32_t mask = (1 << shift); + + int32_t col = 0; + int32_t row_idx; + + for (row_idx = 0; row_idx < num_rows; ++row_idx) + { + // Find the maximum value in order to ensure numerical stability + uint8_t max = *input; + + for (col = 1; col < row_size; ++col) + { + max = MAX(max, input[col]); + } + + int32_t diff = 0; + int32_t sum = 0; + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); + } + } + + const int32_t headroom = __CLZ((uint32_t)sum); + const int32_t bits_over_unit = ACCUM_BITS - headroom + 23; + const int32_t shifted_scale = ONE_OVER1((sum << headroom) - (1 << 31)); + + for (col = 0; col < row_size; ++col) + { + diff = input[col] - max; + if (diff >= diff_min) + { + const int32_t res = + DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit); + output[col] = (uint8_t)CLAMP(res, (int32_t)255, (int32_t)0); + } + else + { + output[col] = 0; + } + } + input += row_size; + output += row_size; + } +} +/** + * @} end of Softmax group + */ \ No newline at end of file diff --git a/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c new file mode 100644 index 0000000..66e892e --- /dev/null +++ b/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_with_batch_q7.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_with_batch_q7.c + * Description: Q7 softmax function + * + * $Date: 09. October 2020 + * $Revision: V.1.0.1 + * + * Target Processor: Cortex-M and Cortex-A cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + +/** + * @brief Q7 softmax function with batch parameter + * @param[in] vec_in pointer to input vector + * @param[in] nb_batches number of batches + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_with_batch_q7(const q7_t *vec_in, const uint16_t nb_batches, const uint16_t dim_vec, q7_t *p_out) +{ + for (int i = 0; i < nb_batches; i++) + { + arm_softmax_q7(vec_in, dim_vec, p_out); + vec_in += dim_vec; + p_out += dim_vec; + } +} + +/** + * @} end of Softmax group + */ diff --git a/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/Drivers/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 0000000..30068d3 --- /dev/null +++ b/Drivers/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,698 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013-2017 ARM LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h new file mode 100644 index 0000000..76612e2 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h @@ -0,0 +1,756 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 12. June 2020 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Drivers/CMSIS/RTOS2/Include/os_tick.h b/Drivers/CMSIS/RTOS2/Include/os_tick.h new file mode 100644 index 0000000..3cfd895 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Include/os_tick.h @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.2 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#ifdef __cplusplus +} +#endif + +#endif /* OS_TICK_H */ diff --git a/Drivers/CMSIS/RTOS2/Source/os_systick.c b/Drivers/CMSIS/RTOS2/Source/os_systick.c new file mode 100644 index 0000000..3cce53c --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_systick.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.3 + * @date 19. March 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST __attribute__((section(".bss.os"))); + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos); +} + +#endif // SysTick diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c new file mode 100644 index 0000000..22cfa93 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c @@ -0,0 +1,187 @@ +/**************************************************************************//** + * @file os_tick_gtim.c + * @brief CMSIS OS Tick implementation for Generic Timer + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifndef GTIM_IRQ_PRIORITY +#define GTIM_IRQ_PRIORITY 0xFFU +#endif + +#ifndef GTIM_IRQ_NUM +#define GTIM_IRQ_NUM SecurePhyTimer_IRQn +#endif + +// Timer interrupt pending flag +static uint8_t GTIM_PendIRQ; + +// Timer tick frequency +static uint32_t GTIM_Clock; + +// Timer load value +static uint32_t GTIM_Load; + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t prio, bits; + + if (freq == 0U) { + return (-1); + } + + GTIM_PendIRQ = 0U; + + // Get timer clock +#ifdef SCTR_BASE + GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20); +#else + // FVP REFCLK CNTControl 100MHz + GTIM_Clock = 100000000UL; +#endif + + PL1_SetCounterFrequency(GTIM_Clock); + + // Calculate load value + GTIM_Load = (GTIM_Clock / freq) - 1U; + + // Disable Generic Timer and set load value + PL1_SetControl(0U); + PL1_SetLoadValue(GTIM_Load); + + // Disable corresponding IRQ + IRQ_Disable(GTIM_IRQ_NUM); + IRQ_ClearPending(GTIM_IRQ_NUM); + + // Determine number of implemented priority bits + IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU); + + prio = IRQ_GetPriority(GTIM_IRQ_NUM); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(GTIM_IRQ_NUM, handler); + + // Enable corresponding interrupt + IRQ_Enable(GTIM_IRQ_NUM); + + // Enable system counter and timer control +#ifdef SCTR_BASE + *(uint32_t*)SCTR_BASE |= 3U; +#endif + + // Enable timer control + PL1_SetControl(1U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (GTIM_PendIRQ != 0U) { + GTIM_PendIRQ = 0U; + IRQ_SetPending (GTIM_IRQ_NUM); + } + + // Start the Private Timer + ctrl = PL1_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PL1_SetControl(ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PL1_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PL1_SetControl(ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) { + IRQ_ClearPending(GTIM_IRQ_NUM); + GTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + IRQ_ClearPending (GTIM_IRQ_NUM); + PL1_SetLoadValue(GTIM_Load); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (GTIM_IRQ_NUM); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (GTIM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (GTIM_Load + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + return (GTIM_Load - PL1_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + CNTP_CTL_Type cntp_ctl; + cntp_ctl.w = PL1_GetControl(); + return (cntp_ctl.b.ISTATUS); +} diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c new file mode 100644 index 0000000..e75ac3a --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file os_tick_ptim.c + * @brief CMSIS OS Tick implementation for Private Timer + * @version V1.0.2 + * @date 02. March 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#if defined(PTIM) + +#include "os_tick.h" +#include "irq_ctrl.h" + +#ifndef PTIM_IRQ_PRIORITY +#define PTIM_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + PTIM_PendIRQ = 0U; + + // Private Timer runs with the system frequency + load = (SystemCoreClock / freq) - 1U; + + // Disable Private Timer and set load value + PTIM_SetControl (0U); + PTIM_SetLoadValue (load); + + // Disable corresponding IRQ + IRQ_Disable (PrivTimer_IRQn); + IRQ_ClearPending(PrivTimer_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (PrivTimer_IRQn, 0xFFU); + + prio = IRQ_GetPriority (PrivTimer_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(PrivTimer_IRQn, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(PrivTimer_IRQn, handler); + + // Enable corresponding interrupt + IRQ_Enable (PrivTimer_IRQn); + + // Set bits: IRQ enable and Auto reload + PTIM_SetControl (0x06U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (PTIM_PendIRQ != 0U) { + PTIM_PendIRQ = 0U; + IRQ_SetPending (PrivTimer_IRQn); + } + + // Start the Private Timer + ctrl = PTIM_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PTIM_SetControl (ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PTIM_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PTIM_SetControl (ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(PrivTimer_IRQn) != 0) { + IRQ_ClearPending (PrivTimer_IRQn); + PTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + PTIM_ClearEventFlag(); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (PrivTimer_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (PTIM_GetLoadValue() + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t load = PTIM_GetLoadValue(); + return (load - PTIM_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (PTIM->ISR & 1); +} + +#endif // PTIM diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h new file mode 100644 index 0000000..376dbf7 --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os.h @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +/// \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel. +#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string + +/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features. +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available + +#if (osCMSIS >= 0x20000U) +#include "cmsis_os2.h" +#else +#include +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#else +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } } +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = { (function) } +#else +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, NULL, 0U } } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#else +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U } +#endif +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#else +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, NULL, 0U } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#else +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), NULL } +#else +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#else +#define osMailQDef(name, queue_sz, type) \ +static void *os_mail_p_##name[2]; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (&os_mail_p_##name), \ + { NULL, 0U, NULL, 0U, NULL, 0U }, \ + { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c new file mode 100644 index 0000000..de1650c --- /dev/null +++ b/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V1.2 + * + * Project: CMSIS-RTOS API V1 + * Title: cmsis_os_v1.c V1 module file + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +#if (osCMSIS >= 0x20000U) + + +// Thread +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { + + if (thread_def == NULL) { + return (osThreadId)NULL; + } + return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr); +} + + +// Signals + +#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) { + event.status = osEventSignal; + event.value.signals = (int32_t)flags; + } else { + switch ((int32_t)flags) { + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + case osErrorParameter: + event.status = osErrorValue; + break; + default: + event.status = (osStatus)flags; + break; + } + } + return event; +} + + +// Timer +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + + if (timer_def == NULL) { + return (osTimerId)NULL; + } + return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr); +} + + +// Mutex +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { + + if (mutex_def == NULL) { + return (osMutexId)NULL; + } + return osMutexNew(mutex_def); +} + + +// Semaphore + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) + +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + + if (semaphore_def == NULL) { + return (osSemaphoreId)NULL; + } + return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def); +} + +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + osStatus_t status; + uint32_t count; + + status = osSemaphoreAcquire(semaphore_id, millisec); + switch (status) { + case osOK: + count = osSemaphoreGetCount(semaphore_id); + return ((int32_t)count + 1); + case osErrorResource: + case osErrorTimeout: + return 0; + default: + break; + } + return -1; +} + +#endif // Semaphore + + +// Memory Pool + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) + +osPoolId osPoolCreate (const osPoolDef_t *pool_def) { + + if (pool_def == NULL) { + return (osPoolId)NULL; + } + return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr))); +} + +void *osPoolAlloc (osPoolId pool_id) { + return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); +} + +void *osPoolCAlloc (osPoolId pool_id) { + void *block; + uint32_t block_size; + + block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); + if (block != NULL) { + memset(block, 0, block_size); + } + return block; +} + +osStatus osPoolFree (osPoolId pool_id, void *block) { + return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block); +} + +#endif // Memory Pool + + +// Message Queue + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) + +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + (void)thread_id; + + if (queue_def == NULL) { + return (osMessageQId)NULL; + } + return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr))); +} + +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec); +} + +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + osStatus_t status; + osEvent event; + uint32_t message; + + status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMessage; + event.value.v = message; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +#endif // Message Queue + + +// Mail Queue + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) + +typedef struct os_mail_queue_s { + osMemoryPoolId_t mp_id; + osMessageQueueId_t mq_id; +} os_mail_queue_t; + +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + os_mail_queue_t *ptr; + (void)thread_id; + + if (queue_def == NULL) { + return (osMailQId)NULL; + } + + ptr = queue_def->mail; + if (ptr == NULL) { + return (osMailQId)NULL; + } + + ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); + ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); + if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) { + if (ptr->mp_id != (osMemoryPoolId_t)NULL) { + osMemoryPoolDelete(ptr->mp_id); + } + if (ptr->mq_id != (osMessageQueueId_t)NULL) { + osMessageQueueDelete(ptr->mq_id); + } + return (osMailQId)NULL; + } + + return (osMailQId)ptr; +} + +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return NULL; + } + return osMemoryPoolAlloc(ptr->mp_id, millisec); +} + +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + void *block; + uint32_t block_size; + + if (ptr == NULL) { + return NULL; + } + block_size = osMemoryPoolGetBlockSize(ptr->mp_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc(ptr->mp_id, millisec); + if (block != NULL) { + memset(block, 0, block_size); + } + + return block; + +} + +osStatus osMailPut (osMailQId queue_id, const void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U); +} + +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + osStatus_t status; + osEvent event; + void *mail; + + if (ptr == NULL) { + event.status = osErrorParameter; + return event; + } + + status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMail; + event.value.p = mail; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +osStatus osMailFree (osMailQId queue_id, void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMemoryPoolFree(ptr->mp_id, mail); +} + +#endif // Mail Queue + + +#endif // osCMSIS diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000..c3b8473 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4422 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) +#endif /* STM32F3 */ + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 || STM32WB */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h new file mode 100644 index 0000000..f7eb847 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -0,0 +1,297 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_H +#define __STM32F4xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_conf.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ + }while(0); + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ + }while(0); + +/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ + }while(0); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable + * @{ + */ +/** @brief SYSCFG Break Lockup lock + * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ + }while(0) +/** + * @} + */ + +/** @defgroup PVD_Lock_Enable PVD Lock + * @{ + */ +/** @brief SYSCFG Break PVD lock + * Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ + SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ + }while(0) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_H */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h new file mode 100644 index 0000000..b4c229b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -0,0 +1,857 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_CAN_H +#define STM32F4xx_HAL_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#if defined (CAN1) +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + +} CAN_FilterTypeDef; + +/** + * @brief CAN Tx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ + + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +} CAN_HandleTypeDef; + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number + * @{ + */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + + +#endif /* CAN1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_CAN_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h new file mode 100644 index 0000000..7690930 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_CORTEX_H +#define __STM32F4xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +void HAL_CORTEX_ClearEvent(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_CORTEX_H */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h new file mode 100644 index 0000000..1df0d7d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DEF +#define __STM32F4xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5*/ +#define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F4xx_HAL_DEF */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h new file mode 100644 index 0000000..7ff3836 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -0,0 +1,802 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_H +#define __STM32F4xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMA_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Channel_selection DMA Channel selection + * @brief DMA channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (DMA_SxCR_CHSEL_3) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f4xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#if defined (DMA_SxCR_CHSEL_3) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10)|| \ + ((CHANNEL) == DMA_CHANNEL_11)|| \ + ((CHANNEL) == DMA_CHANNEL_12)|| \ + ((CHANNEL) == DMA_CHANNEL_13)|| \ + ((CHANNEL) == DMA_CHANNEL_14)|| \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* DMA_SxCR_CHSEL_3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_DMA_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h new file mode 100644 index 0000000..9858c74 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_DMA_EX_H +#define __STM32F4xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U /*!< Memory 1 */ +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_HAL_DMA_EX_H*/ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h new file mode 100644 index 0000000..b18a228 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32f4xx_HAL_EXTI_H +#define STM32f4xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#if defined(EXTI_IMR_IM18) +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#else +#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM18 */ +#if defined(EXTI_IMR_IM19) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM19 */ +#if defined(EXTI_IMR_IM20) +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#else +#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ +#endif /* EXTI_IMR_IM20 */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#if defined (GPIOD) +#define EXTI_GPIOD 0x00000003u +#endif /* GPIOD */ +#if defined (GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#if defined (GPIOF) +#define EXTI_GPIOF 0x00000005u +#endif /* GPIOF */ +#if defined (GPIOG) +#define EXTI_GPIOG 0x00000006u +#endif /* GPIOG */ +#if defined (GPIOH) +#define EXTI_GPIOH 0x00000007u +#endif /* GPIOH */ +#if defined (GPIOI) +#define EXTI_GPIOI 0x00000008u +#endif /* GPIOI */ +#if defined (GPIOJ) +#define EXTI_GPIOJ 0x00000009u +#endif /* GPIOJ */ +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM23) +#define EXTI_LINE_NB 24UL +#else +#define EXTI_LINE_NB 23UL +#endif /* EXTI_IMR_IM23 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if !defined (GPIOD) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOF) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH)) +#elif !defined (GPIOJ) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /* GPIOD */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32f4xx_HAL_EXTI_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h new file mode 100644 index 0000000..41f77d2 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_H +#define __STM32F4xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ + + __IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ + + __IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/ + + __IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/ + + __IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/ + + __IO uint32_t Address; /*Internal variable to save address selected for program*/ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ +#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ +#if defined(FLASH_SR_RDERR) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ +#endif /* FLASH_SR_RDERR */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U +#define FLASH_PSIZE_HALF_WORD 0x00000100U +#define FLASH_PSIZE_WORD 0x00000200U +#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U +#define CR_PSIZE_MASK 0xFFFFFCFFU +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define RDP_KEY ((uint16_t)0x00A5) +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) + +/** + * @brief Enable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) + +/** + * @brief Disable the FLASH data cache. + * @retval none + */ +#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) + +/** + * @brief Resets the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ + FLASH->ACR &= ~FLASH_ACR_ICRST; \ + }while(0U) + +/** + * @brief Resets the FLASH data Cache. + * @note This function must be used only when the data Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ + FLASH->ACR &= ~FLASH_ACR_DCRST; \ + }while(0U) +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flags to check. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag + * @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) + * (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f4xx_hal_flash_ex.h" +#include "stm32f4xx_hal_flash_ramfunc.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief ACR register byte 0 (Bits[7:0]) base address + */ +#define ACR_BYTE0_ADDRESS 0x40023C00U +/** + * @brief OPTCR register byte 0 (Bits[7:0]) base address + */ +#define OPTCR_BYTE0_ADDRESS 0x40023C14U +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS 0x40023C15U +/** + * @brief OPTCR register byte 2 (Bits[23:16]) base address + */ +#define OPTCR_BYTE2_ADDRESS 0x40023C16U +/** + * @brief OPTCR register byte 3 (Bits[31:24]) base address + */ +#define OPTCR_BYTE3_ADDRESS 0x40023C17U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h new file mode 100644 index 0000000..5fa89db --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -0,0 +1,1063 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_FLASH_EX_H +#define __STM32F4xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint8_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured for extension. + This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */ + + uint32_t PCROPState; /*!< PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + uint16_t Sectors; /*!< specifies the sector(s) set for PCROP. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\ + STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Banks; /*!< Select banks for PCROP activation/deactivation of all sectors. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint16_t SectorsBank1; /*!< Specifies the sector(s) set for PCROP for Bank1. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint16_t SectorsBank2; /*!< Specifies the sector(s) set for PCROP for Bank2. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + + uint8_t BootConfig; /*!< Specifies Option bytes for boot config. + This parameter can be a value of @ref FLASHEx_Dual_Boot */ + +#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +} FLASH_AdvOBProgramInitTypeDef; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || + STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00000000U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x00000001U /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 0x00000001U /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 0x00000002U /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 0x00000003U /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR 0x00000008U /*!< BOR option byte configuration */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAA) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup FLASHEx_PCROP_State FLASH PCROP State + * @{ + */ +#define OB_PCROP_STATE_DISABLE 0x00000000U /*!< Disable PCROP */ +#define OB_PCROP_STATE_ENABLE 0x00000001U /*!< Enable PCROP */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOOTCONFIG 0x00000002U /*!< BOOTConfig option byte configuration */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define OPTIONBYTE_PCROP 0x00000001U /*!= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) + +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xC */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +void FLASH_FlushCaches(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h new file mode 100644 index 0000000..2112e74 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.h + * @author MCD Application Team + * @brief Header file of FLASH RAMFUNC driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_FLASH_RAMFUNC_H +#define __STM32F4xx_FLASH_RAMFUNC_H + +#ifdef __cplusplus +extern "C" { +#endif +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_RAMFUNC_Exported_Functions + * @{ + */ + +/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 + * @{ + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h new file mode 100644 index 0000000..5f3d749 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -0,0 +1,325 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_H +#define __STM32F4xx_HAL_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ +/** + * @} + */ + + /** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f4xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h new file mode 100644 index 0000000..5e0b7cc --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -0,0 +1,1590 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_GPIO_EX_H +#define __STM32F4xx_HAL_GPIO_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +/** @brief GPIO_Legacy + */ +#define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ +#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ +#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ +#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F413xx || STM32F423xx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F411xE */ + +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ +#if defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#endif /* STM32F410Cx || STM32F410Rx */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F446xx -----------------------*/ +#if defined(STM32F446xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U : 7U) +#endif /* STM32F446xx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 7U) +#endif /* STM32F412Vx */ +#if defined(STM32F412Rx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U : 7U) +#endif /* STM32F412Rx */ +#if defined(STM32F412Cx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U : 7U) +#endif /* STM32F412Cx */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/*------------------------- STM32F429xx/STM32F439xx---------------------------*/ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC)) + +#endif /* STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F427xx/STM32F437xx------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1)) + +#endif /* STM32F427xx || STM32F437xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F407xx/STM32F417xx------------------*/ +#if defined(STM32F407xx) || defined(STM32F417xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F405xx/STM32F415xx------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF12_FSMC) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F405xx || STM32F415xx */ + +/*----------------------------------------------------------------------------*/ + +/*---------------------------------------- STM32F401xx------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \ + ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \ + ((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT)) +#endif /* STM32F401xC || STM32F401xE */ +/*----------------------------------------------------------------------------*/ +/*---------------------------------------- STM32F410xx------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/*---------------------------------------- STM32F411xx------------------------*/ +#if defined(STM32F411xE) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ + ((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI4) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF6_SPI5) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF15_EVENTOUT)) + +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------------------- STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF6_SPI2) || \ + ((AF) == GPIO_AF6_SPI4) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPI2) || ((AF) == GPIO_AF7_SPI3) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF9_QSPI) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------------------- STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF8_UART4) || \ + ((AF) == GPIO_AF8_UART5) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF11_ETH) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDIO) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI) || \ + ((AF) == GPIO_AF9_QSPI) || ((AF) == GPIO_AF10_QSPI)) + +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*------------------STM32F413xx/STM32F423xx-----------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U)) +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_GPIO_EX_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h new file mode 100644 index 0000000..9a7a67e --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -0,0 +1,741 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_H +#define __STM32F4xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_general_call_addressing_mode */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_nostretch_mode */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (Peripheral in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ +#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +typedef struct __I2C_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode + * @{ + */ +#define I2C_DUTYCYCLE_2 0x00000000U +#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY +/** + * @} + */ + +/** @defgroup I2C_addressing_mode I2C addressing mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) +/** + * @} + */ + +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +/** + * @} + */ + +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +/** + * @} + */ + +/** @defgroup I2C_nostretch_mode I2C nostretch mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U +#define I2C_NEXT_FRAME 0x00000004U +#define I2C_FIRST_AND_LAST_FRAME 0x00000008U +#define I2C_LAST_FRAME_NO_STOP 0x00000010U +#define I2C_LAST_FRAME 0x00000020U + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x00AA0000U) +#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_BUF I2C_CR2_ITBUFEN +#define I2C_IT_EVT I2C_CR2_ITEVTEN +#define I2C_IT_ERR I2C_CR2_ITERREN +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ + +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif + +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ + (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ + (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) + +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) + +/** @brief Clears the I2C ADDR pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @retval None + */ +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Clears the I2C STOPF pending flag. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) + +/** + * @} + */ + +/* Include I2C HAL Extension module */ +#include "stm32f4xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ +#define I2C_FLAG_MASK 0x0000FFFFU +#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ +#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) +#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters + * @{ + */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) +#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ + ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_I2C_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h new file mode 100644 index 0000000..31ad99c --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -0,0 +1,115 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_I2C_EX_H +#define __STM32F4xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macros I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_I2C_EX_H */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h new file mode 100644 index 0000000..a7273d5 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -0,0 +1,436 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_H +#define __STM32F4xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 0x00000100U +/** + * @} + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON 0x00000000U +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) +#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) + +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) +#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR ((uint8_t)0x03) +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A + * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * This parameter can be: + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ + }while(0U) + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f4xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U +#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) +#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) +/** + * @} + */ + +/** @defgroup PWR_CR_register_alias PWR CR Register alias address + * @{ + */ +/* --- CR Register ---*/ +/* Alias word address of DBP bit */ +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) + +/* Alias word address of PVDE bit */ +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) + +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of EWUP bit */ +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos +#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE) || \ + ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h new file mode 100644 index 0000000..57fd4d9 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_PWR_EX_H +#define __STM32F4xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ +#else +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to + 180 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to + 168 MHz by activating the over-drive mode. */ +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +/** + * @} + */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins + * @{ + */ +#define PWR_WAKEUP_PIN2 0x00000080U +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define PWR_WAKEUP_PIN3 0x00000040U +#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#else +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg = 0x00U; \ + MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to enable or disable the Over drive mode. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Over drive switching. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN)) + +/** @brief Check PWR flag is set or not. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); +#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWREx_Private_Constants PWREx Private Constants + * @{ + */ + +/** @defgroup PWREx_register_alias_address PWREx Register alias address + * @{ + */ +/* ------------- PWR registers bit address in the alias region ---------------*/ +/* --- CR Register ---*/ +/* Alias word address of FPDS bit */ +#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos +#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) + +/* Alias word address of ODEN bit */ +#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos +#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) + +/* Alias word address of ODSWEN bit */ +#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos +#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) + +/* Alias word address of MRLVDS bit */ +#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos +#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) + +/* Alias word address of LPLVDS bit */ +#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos +#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) + + /** + * @} + */ + +/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address + * @{ + */ +/* --- CSR Register ---*/ +/* Alias word address of BRE bit */ +#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos +#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +#else +#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ + +#if defined(STM32F446xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) +#endif /* STM32F446xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F4xx_HAL_PWR_EX_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h new file mode 100644 index 0000000..2e3909a --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -0,0 +1,1458 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_H +#define __STM32F4xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f4xx_hal_rcc_ex.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON ((uint8_t)0x01) + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint8_t)0x00) +#define RCC_LSI_ON ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint8_t)0x00) +#define RCC_PLL_OFF ((uint8_t)0x01) +#define RCC_PLL_ON ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 0x00000002U +#define RCC_PLLP_DIV4 0x00000004U +#define RCC_PLLP_DIV6 0x00000006U +#define RCC_PLLP_DIV8 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U +#define RCC_CLOCKTYPE_HCLK 0x00000002U +#define RCC_CLOCKTYPE_PCLK1 0x00000004U +#define RCC_CLOCKTYPE_PCLK2 0x00000008U +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for + * STM32F446xx devices. + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U +#define RCC_RTCCLKSOURCE_LSE 0x00000100U +#define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U +#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U +#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U +#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U +#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U +#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U +#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U +#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U +#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U +#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U +#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U +#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U +#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U +#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U +#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U +#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U +#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U +#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U +#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U +#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U +#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U +#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U +#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U +#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U +#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U +#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO2 0x00000001U +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI 0x00000000U +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) +#define RCC_IT_CSS ((uint8_t)0x80) +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_BORRST ((uint8_t)0x79) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +/** + * @} + */ + +/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wake-up from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) +#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) +#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. + * User should request a transition to HSE Off first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) +#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wake-up source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while(0U) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) +#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) +#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This + * parameter is available only for STM32F446xx devices. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter + * is available only for STM32F446xx devices. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have + * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1FU) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U)\ + == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) &\ + (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +/* --- CR Register --- */ +/* Alias word address of HSION bit */ +#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) +#define RCC_HSION_BIT_NUMBER 0x00U +#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U)) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER 0x13U +#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER 0x18U +#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) + +/* --- BDCR Register --- */ +/* Alias word address of RTCEN bit */ +#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) +#define RCC_RTCEN_BIT_NUMBER 0x0FU +#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)) +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER 0x10U +#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) + +/* --- CSR Register --- */ +/* Alias word address of LSION bit */ +#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) +#define RCC_LSION_BIT_NUMBER 0x00U +#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U)) + +/* CR register byte 3 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS 0x40023802U + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U)) + +/* BDCR register base address */ +#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET) + +#define RCC_DBP_TIMEOUT_VALUE 2U +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) + +#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) + +#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h new file mode 100644 index 0000000..3b62134 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -0,0 +1,7190 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_RCC_EX_H +#define __STM32F4xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + except for STM32F411xE devices where the Min_Data = 192 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx + and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +} RCC_PLLInitTypeDef; + +#if defined(STM32F446xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ +} RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection. + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection. + This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F446xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLL is selected as Clock Source SAI */ + + uint32_t PLLI2SDivR; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */ + + uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection. + This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ + + uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ + +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t Dfsdm2ClockSelection; /*!< Specifies DFSDM2 Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */ + + uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection. + This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t SaiAClockSelection; /*!< Specifies SAI1_A Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */ + + uint32_t SaiBClockSelection; /*!< Specifies SAI1_B Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */ +#endif /* STM32F413xx || STM32F423xx */ + + uint32_t PLLI2SSelection; /*!< Specifies PLL I2S Clock Source Selection. + This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ +} RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks. + This parameter is only available in STM32F469xx/STM32F479xx devices. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */ +#endif /* STM32F469xx || STM32F479xx */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ + +} RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#if defined(STM32F469xx) || defined(STM32F479xx) + uint32_t Clk48ClockSelection; /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection. + This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */ +#endif /* STM32F469xx || STM32F479xx */ +} RCC_PeriphCLKInitTypeDef; + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ +#if defined(STM32F411xE) + uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 62 */ +#endif /* STM32F411xE */ + + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + Except for STM32F411xE devices where the Min_Data = 192. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + +} RCC_PLLI2SInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection. + This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +} RCC_PeriphCLKInitTypeDef; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_TIM 0x00000004U +#define RCC_PERIPHCLK_RTC 0x00000008U +#define RCC_PERIPHCLK_FMPI2C1 0x00000010U +#define RCC_PERIPHCLK_CLK48 0x00000020U +#define RCC_PERIPHCLK_SDIO 0x00000040U +#define RCC_PERIPHCLK_PLLI2S 0x00000080U +#define RCC_PERIPHCLK_DFSDM1 0x00000100U +#define RCC_PERIPHCLK_DFSDM1_AUDIO 0x00000200U +#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define RCC_PERIPHCLK_DFSDM2 0x00000400U +#define RCC_PERIPHCLK_DFSDM2_AUDIO 0x00000800U +#define RCC_PERIPHCLK_LPTIM1 0x00001000U +#define RCC_PERIPHCLK_SAIA 0x00002000U +#define RCC_PERIPHCLK_SAIB 0x00004000U +#endif /* STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F410xx ----------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_TIM 0x00000002U +#define RCC_PERIPHCLK_RTC 0x00000004U +#define RCC_PERIPHCLK_FMPI2C1 0x00000008U +#define RCC_PERIPHCLK_LPTIM1 0x00000010U +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- Peripheral Clock source for STM32F446xx ----------------*/ +#if defined(STM32F446xx) +#define RCC_PERIPHCLK_I2S_APB1 0x00000001U +#define RCC_PERIPHCLK_I2S_APB2 0x00000002U +#define RCC_PERIPHCLK_SAI1 0x00000004U +#define RCC_PERIPHCLK_SAI2 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_CEC 0x00000040U +#define RCC_PERIPHCLK_FMPI2C1 0x00000080U +#define RCC_PERIPHCLK_CLK48 0x00000100U +#define RCC_PERIPHCLK_SDIO 0x00000200U +#define RCC_PERIPHCLK_SPDIFRX 0x00000400U +#define RCC_PERIPHCLK_PLLI2S 0x00000800U +#endif /* STM32F446xx */ +/*-----------------------------------------------------------------------------*/ + +/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#define RCC_PERIPHCLK_CLK48 0x00000080U +#define RCC_PERIPHCLK_SDIO 0x00000100U +#endif /* STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_SAI_PLLI2S 0x00000002U +#define RCC_PERIPHCLK_SAI_PLLSAI 0x00000004U +#define RCC_PERIPHCLK_LTDC 0x00000008U +#define RCC_PERIPHCLK_TIM 0x00000010U +#define RCC_PERIPHCLK_RTC 0x00000020U +#define RCC_PERIPHCLK_PLLI2S 0x00000040U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/*----------------------------------------------------------------------------*/ + +/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_I2S 0x00000001U +#define RCC_PERIPHCLK_RTC 0x00000002U +#define RCC_PERIPHCLK_PLLI2S 0x00000004U +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define RCC_PERIPHCLK_TIM 0x00000008U +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +/*----------------------------------------------------------------------------*/ +/** + * @} + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \ + defined(STM32F479xx) +/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIDIVR_2 0x00000000U +#define RCC_PLLSAIDIVR_4 0x00010000U +#define RCC_PLLSAIDIVR_8 0x00020000U +#define RCC_PLLSAIDIVR_16 0x00030000U +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) +#define RCC_PLLI2SP_DIV2 0x00000002U +#define RCC_PLLI2SP_DIV4 0x00000004U +#define RCC_PLLI2SP_DIV6 0x00000006U +#define RCC_PLLI2SP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider + * @{ + */ +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define RCC_PLLSAIP_DIV2 0x00000002U +#define RCC_PLLSAIP_DIV4 0x00000004U +#define RCC_PLLSAIP_DIV6 0x00000006U +#define RCC_PLLSAIP_DIV8 0x00000008U +#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIACLKSOURCE_PLLI2S 0x00100000U +#define RCC_SAIACLKSOURCE_EXT 0x00200000U +/** + * @} + */ + +/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAIBCLKSOURCE_PLLI2S 0x00400000U +#define RCC_SAIBCLKSOURCE_EXT 0x00800000U +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL) +/** + * @} + */ +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) +#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) +#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI 0x00000000U +#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0) +#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1) +#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI 0x00000000U +#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source + * @{ + */ +#define RCC_SPDIFRXCLKSOURCE_PLLR 0x00000000U +#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL) +/** + * @} + */ + +#endif /* STM32F446xx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_SAI1_BlockA_Clock_Source RCC SAI BlockA Clock Source + * @{ + */ +#define RCC_SAIACLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIACLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) +#define RCC_SAIACLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) +#define RCC_SAIACLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_BlockB_Clock_Source RCC SAI BlockB Clock Source + * @{ + */ +#define RCC_SAIBCLKSOURCE_PLLI2SR 0x00000000U +#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) +#define RCC_SAIBCLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) +#define RCC_SAIBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ + + +/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source RCC DFSDM2 Audio Clock Source + * @{ + */ +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source RCC DFSDM2 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM2CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM2CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source + * @{ + */ +#define RCC_PLLI2SCLKSOURCE_PLLSRC 0x00000000U +#define RCC_PLLI2SCLKSOURCE_EXT ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source RCC DFSDM1 Audio Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1 0x00000000U +#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCC DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U +#define RCC_DFSDM1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source + * @{ + */ +#define RCC_I2SAPB1CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) +#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) +#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC) +/** + * @} + */ + +/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source + * @{ + */ +#define RCC_I2SAPB2CLKSOURCE_PLLI2S 0x00000000U +#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0) +#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1) +#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCC CLK48 Clock Source + * @{ + */ +#define RCC_CLK48CLKSOURCE_PLLQ 0x00000000U +#define RCC_CLK48CLKSOURCE_PLLI2SQ ((uint32_t)RCC_DCKCFGR2_CK48MSEL) +/** + * @} + */ + +/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source + * @{ + */ +#define RCC_SDIOCLKSOURCE_CLK48 0x00000000U +#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL) +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + +/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source + * @{ + */ +#define RCC_I2SAPBCLKSOURCE_PLLR 0x00000000U +#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) +#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) +/** + * @} + */ + +/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source + * @{ + */ +#define RCC_FMPI2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) +#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) +#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) +#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) +#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\ + STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection + * @{ + */ +#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) +#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) +/** + * @} + */ +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\ + STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK 0x00000000U +#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) + +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) + +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x22E017FFU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F427xx || STM32F429xx || STM32F469xx */ +#if defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#endif /* STM32F469xx || STM32F479xx */ +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x0C777933U) +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F429xx) || defined(STM32F439xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#endif /* STM32F429xx || STM32F439xx */ +#if defined(STM32F427xx) || defined(STM32F437xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00777933U) +#endif /* STM32F427xx || STM32F437xx */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) + +#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F437xx || STM32F439xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) + +#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) + +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F469xx || STM32F479xx */ +/** + * @} + */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0U) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0U) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#if defined(STM32F407xx)|| defined(STM32F417xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F407xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#if defined (STM32F405xx) || defined (STM32F415xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206011FFU) +#endif /* STM32F405xx || STM32F415xx */ +#if defined (STM32F407xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x226011FFU) +#endif /* STM32F407xx || STM32F417xx */ +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined (STM32F415xx) || defined (STM32F417xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000F1U) +#endif /* STM32F415xx || STM32F417xx */ +#if defined (STM32F405xx) || defined (STM32F407xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C1U) +#endif /* STM32F405xx || STM32F407xx */ +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) + +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F415xx || STM32F417xx */ + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000001U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xF6FEC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x04777933U) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#if defined(STM32F407xx)|| defined(STM32F417xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F407xx || STM32F417xx */ + +#if defined(STM32F415xx) || defined(STM32F417xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F415xx || STM32F417xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +/** + * @} + */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- STM32F401xE/STM32F401xC --------------------------*/ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +/** + * @} + */ +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00077931U) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +/** + * @} + */ +#endif /* STM32F401xC || STM32F401xE*/ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F410xx -------------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB1) peripheral clock. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) + +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x80601087U) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() +#define __HAL_RCC_AHB2_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31624A18U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x31620A18U) +#endif /* STM32F410Tx */ +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined (STM32F410Rx) || defined (STM32F410Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00155131U) +#endif /* STM32F410Rx || STM32F410Cx */ +#if defined (STM32F410Tx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00055111U) +#endif /* STM32F410Tx */ +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) + +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +/** + * @} + */ + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*----------------------------------------------------------------------------*/ + +/*-------------------------------- STM32F411xx -------------------------------*/ +#if defined(STM32F411xE) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000080U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x10E2C80FU) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00177931U) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @{ + */ +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +/** + * @} + */ +#endif /* STM32F411xE */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F446xx -----------------------------*/ +#if defined(STM32F446xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) + +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x206010FFU) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000081U) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x3FFFC9FFU) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x00C77933U) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) + +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) + +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +/** + * @} + */ + +#endif /* STM32F446xx */ +/*----------------------------------------------------------------------------*/ + +/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + }while(0U) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#endif /* STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_UART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0U) +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0U) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN)) +#define __HAL_RCC_UART10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET) +#define __HAL_RCC_UART10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_EXTIT_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) +#define __HAL_RCC_UART10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_EXTIT_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#if defined (STM32F412Zx) || defined(STM32F413xx) || defined (STM32F423xx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x006010FFU) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined (STM32F412Cx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x00601087U) +#endif /* STM32F412Cx */ +#if defined (STM32F412Vx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060109FU) +#endif /* STM32F412Vx */ +#if defined (STM32F412Rx) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0060108FU) +#endif /* STM32F412Rx */ +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) + +#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#endif /* STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#endif /* STM32F412Zx || STM32F413xx || STM32F423xx */ +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000D0U) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x000000C0U) +#endif /* STM32F423xx */ +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) + +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset + * @brief Force or release AHB3 peripheral reset. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00000003U) +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) + +#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(STM32F412Cx) +#define __HAL_RCC_AHB3_FORCE_RESET() +#define __HAL_RCC_AHB3_RELEASE_RESET() + +#define __HAL_RCC_FSMC_FORCE_RESET() +#define __HAL_RCC_QSPI_FORCE_RESET() + +#define __HAL_RCC_FSMC_RELEASE_RESET() +#define __HAL_RCC_QSPI_RELEASE_RESET() +#endif /* STM32F412Cx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFECBFFU) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0x17E6C9FFU) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#if defined(STM32F413xx)|| defined(STM32F423xx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x035779F3U) +#endif /* STM32F413xx || STM32F423xx */ +#if defined (STM32F412Zx) || defined (STM32F412Vx) || defined (STM32F412Rx) || defined (STM32F412Cx) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x01177933U) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST)) +#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F423xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F423xx */ + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) +/** + * @} + */ + +/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable + * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) + +#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ + +/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ + +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN)) +#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#if defined(STM32F413xx) || defined(STM32F423xx) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN)) +#endif /* STM32F413xx || STM32F423xx */ +/** + * @} + */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ + STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432 + * Except for STM32F411xE devices where Min_Data = 192. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices + * where frequency is between 192 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*----------------------------------------------------------------------------*/ + +/*----------------------------PLLI2S Configuration ---------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) +#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx */ +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLI2SP parameter is only available with STM32F446xx Devices + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + * @param __PLLI2SQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#else +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + * + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F411xE) +/** @brief Macro to configure the PLLI2S clock multiplication and division factors . + * @note This macro must be used only when the PLLI2S is disabled. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API). + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices + * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLLI2S jitter. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock + * This parameter must be a number between Min_Data = 192 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) +#endif /* STM32F411xE */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx + * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U) |\ + ((__PLLI2SQ__) << 24U) |\ + ((__PLLI2SR__) << 28U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------------ PLLSAI Configuration ------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is only available with STM32F429x/439x Devices. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE) +#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE) + +#if defined(STM32F446xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 1 MHz to limit PLLI2S jitter. + * @note The PLLSAIM parameter is only used with STM32F446xx Devices + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note the PLLSAIP parameter is only available with STM32F446xx Devices + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ + ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. + * This parameter must be a number in the range {2, 4, 6, or 8}. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLL. + * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLR) / __PLLDivR__ + */ +#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U)) +#endif /* STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * + * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter must be a number between Min_Data = 2 and Max_Data = 16. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/*----------------------------------------------------------------------------*/ + +/*------------------------- Peripheral Clock selection -----------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\ + defined(STM32F479xx) +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) + + +/** @brief Macro to get the I2S clock source (I2SCLK). + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin + * used as I2S clock source + */ +#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block A clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to configure SAI1BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 Block B clock. + * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin + * used as SAI1 Block B clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F446xx) +/** @brief Macro to configure SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock. + */ +#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC)) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__))) + +/** @brief Macro to Get SAI2 clock source selection. + * @note This configuration is only available with STM32F446xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock. + */ +#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC)) + +/** @brief Macro to configure I2S APB1 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the CEC clock. + * @param __SOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CEC clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +/** @brief Macro to configure the SPDIFRX clock. + * @param __SOURCE__ specifies the SPDIFRX clock source. + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SPDIFRX clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. + * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. + */ +#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) + +/** @brief Macro to configure the DSI clock. + * @param __SOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL)) + +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the DFSDM1 clock. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. + * @retval None + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock. + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ + STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL)) + +#if defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the DFSDM2 clock. + * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. + * @retval None + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. + * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock. + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) + +/** @brief Macro to configure DFSDM1 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @param __SOURCE__ specifies the DFSDM2 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__))) + +/** @brief Macro to Get DFSDM2 Audio clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock + * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock + */ +#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL)) + +/** @brief Macro to configure SAI1BlockA clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block A clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockA clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC)) + +/** @brief Macro to configure SAI1 BlockB clock source selection. + * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI Block B clock source. + * This parameter can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__))) + +/** @brief Macro to Get SAI1 BlockB clock source selection. + * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. + * @retval The clock source can be one of the following values: + * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock. + * @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F413xx || STM32F423xx */ + +/** @brief Macro to configure I2S APB1 clock source selection. + * @param __SOURCE__ specifies the I2S APB1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB1 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) + +/** @brief Macro to configure I2S APB2 clock source selection. + * @param __SOURCE__ specifies the I2S APB2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__))) + +/** @brief Macro to Get I2S APB2 clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. + * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR. + * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + */ +#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) + +/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). + * @note This macro must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. + * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the CLK48 clock. + * @param __SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. + */ +#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the CLK48 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. + * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock + */ +#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) + +/** @brief Macro to configure the SDIO clock. + * @param __SOURCE__ specifies the SDIO clock source. + * This parameter can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the SDIO clock. + * @retval The clock source can be one of the following values: + * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. + * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. + */ +#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) + +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macro to configure I2S clock source selection. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__))) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. + * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. + * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. + */ +#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) + +/** @brief Macro to configure the FMPI2C1 clock. + * @param __SOURCE__ specifies the FMPI2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the FMPI2C1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock + * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock + */ +#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) + +/** @brief Macro to configure the LPTIM1 clock. + * @param __SOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__))) + +/** @brief Macro to Get the LPTIM1 clock. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** @brief Macro to configure the Timers clocks prescalers + * @note This feature is only available with STM32F429x/439x Devices. + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\ + STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\ + STM32F423xx */ + +/*----------------------------------------------------------------------------*/ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** @brief Macros to enable or disable the RCC MCO1 feature. + */ +#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE) +#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE) + +/** @brief Macros to enable or disable the RCC MCO2 feature. + */ +#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE) +#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE) + +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); + +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +void HAL_RCCEx_SelectLSEMode(uint8_t Mode); +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ + +/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +/* --- CR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of PLLSAION bit */ +#define RCC_PLLSAION_BIT_NUMBER 0x1CU +#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U)) + +#define PLLSAI_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of PLLI2SON bit */ +#define RCC_PLLI2SON_BIT_NUMBER 0x1AU +#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- DCKCFGR Register ---*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/* Alias word address of TIMPRE bit */ +#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8CU) +#define RCC_TIMPRE_BIT_NUMBER 0x18U +#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\ + STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ + STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/* --- CFGR Register ---*/ +#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U) +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +/* Alias word address of I2SSRC bit */ +#define RCC_I2SSRC_BIT_NUMBER 0x17U +#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/* --- PLLI2SCFGR Register ---*/ +#define RCC_PLLI2SCFGR_OFFSET (RCC_OFFSET + 0x84U) +/* Alias word address of PLLI2SSRC bit */ +#define RCC_PLLI2SSRC_BIT_NUMBER 0x16U +#define RCC_PLLI2SCFGR_PLLI2SSRC_BB (PERIPH_BB_BASE\ + + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U)) + +#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 2 ms */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/* Alias word address of MCO1EN bit */ +#define RCC_MCO1EN_BIT_NUMBER 0x8U +#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U)) + +/* Alias word address of MCO2EN bit */ +#define RCC_MCO2EN_BIT_NUMBER 0x9U +#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#define PLL_TIMEOUT_VALUE 2U /* 2 ms */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U)) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU)) +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU)) +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU)) +#endif /* STM32F413xx || STM32F423xx */ + +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) + +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F446xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) + +#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63U) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI1CLKSOURCE_EXT)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) + +#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\ + ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U)) + +#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U)) + +#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \ + ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT)) + +#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC)) + +#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC)) + +#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\ + ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI)) + +#define IS_RCC_CLK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\ + ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ)) + +#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\ + ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2)) + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \ + ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2)) + +#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) + +#define IS_RCC_SAIACLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC)) + +#define IS_RCC_SAIBCLKSOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_EXT) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC)) + +#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U)) + +#endif /* STM32F413xx || STM32F423xx */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \ + STM32F412Rx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_RCC_EX_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h new file mode 100644 index 0000000..84d1b51 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -0,0 +1,733 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_SPI_H +#define STM32F4xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_8BIT (0x00000000U) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + } while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR register. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 register. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_SPI_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h new file mode 100644 index 0000000..53c9bf6 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -0,0 +1,2157 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_H +#define STM32F4xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__HANDLE__)->Instance->CCR4)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + (__HANDLE__)->ChannelState[3]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f4xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_TIM_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h new file mode 100644 index 0000000..4f1d01b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -0,0 +1,357 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_TIM_EX_H +#define STM32F4xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#if defined (TIM2) +#if defined(TIM8) +#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ +#endif /* TIM8 */ +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ +#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ +#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ +#endif /* TIM2 */ + +#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */ +#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */ +#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */ +#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */ + +#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */ +#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */ +#if defined(SPDIFRX) +#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */ +#endif /* SPDIFRX*/ + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define LPTIM_REMAP_MASK 0x10000000U + +#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */ +#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */ + +#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */ +#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */ +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#if defined(SPDIFRX) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#elif defined(TIM2) +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE))) || \ + (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ + (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ + ((TIM_REMAP) == TIM_TIM9_LPTIM)))) +#elif defined(TIM8) +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ + ((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ + ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ + ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ + (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ +#else +#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ + ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ + ((TIM_REMAP) == TIM_TIM5_LSI) || \ + ((TIM_REMAP) == TIM_TIM5_LSE) || \ + ((TIM_REMAP) == TIM_TIM5_RTC))) || \ + (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ + ((TIM_REMAP) == TIM_TIM11_HSE)))) +#endif /* SPDIFRX */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_TIM_EX_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h new file mode 100644 index 0000000..e6ce82f --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -0,0 +1,909 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_UART_H +#define __STM32F4xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) + - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 + Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). + This parameter can be a value of @ref UART_Over_Sampling */ +} UART_InitTypeDef; + +/** + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef enum +{ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ +} HAL_UART_StateTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_Error_Code UART Error Code + * @{ + */ +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Word_Length UART Word Length + * @{ + */ +#define UART_WORDLENGTH_8B 0x00000000U +#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 0x00000000U +#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U +#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U +#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) +#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) +#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX ((uint32_t)USART_CR1_RE) +#define UART_MODE_TX ((uint32_t)USART_CR1_TE) +#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U +#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U +#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) +/** + * @} + */ + +/** @defgroup UART_WakeUp_functions UART Wakeup Functions + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U +#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) +/** + * @} + */ + +/** @defgroup UART_Flags UART FLags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the SR register + * @{ + */ +#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) +#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) +#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) +#define UART_FLAG_TC ((uint32_t)USART_SR_TC) +#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) +#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) +#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) +#define UART_FLAG_NE ((uint32_t)USART_SR_NE) +#define UART_FLAG_FE ((uint32_t)USART_SR_FE) +#define UART_FLAG_PE ((uint32_t)USART_SR_PE) +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupt Definitions + * Elements values convention: 0xY000XXXX + * - XXXX : Interrupt mask (16 bits) in the Y register + * - Y : Interrupt source register (2bits) + * - 0001: CR1 register + * - 0010: CR2 register + * - 0011: CR3 register + * @{ + */ + +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) + +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) + +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle gstate & RxState + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flushes the UART DR register + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) + +/** @brief Checks whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg UART_FLAG_LBD: LIN Break detection flag + * @arg UART_FLAG_TXE: Transmit data register empty flag + * @arg UART_FLAG_TC: Transmission Complete flag + * @arg UART_FLAG_RXNE: Receive data register not empty flag + * @arg UART_FLAG_IDLE: Idle Line detection flag + * @arg UART_FLAG_ORE: Overrun Error flag + * @arg UART_FLAG_NE: Noise Error flag + * @arg UART_FLAG_FE: Framing Error flag + * @arg UART_FLAG_PE: Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg UART_FLAG_LBD: LIN Break detection flag. + * @arg UART_FLAG_TC: Transmission Complete flag. + * @arg UART_FLAG_RXNE: Receive data register not empty flag. + * + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register followed by a read + * operation to USART_DR register. + * @note RXNE flag can be also cleared by a read to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register. + * @note TXE flag is cleared only by a write to the USART_DR register. + * + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Clears the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + +/** @brief Clears the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Clears the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_PE: Parity Error interrupt + * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) + +/** @brief Checks whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * UART Handle selects the USARTx or UARTy peripheral + * (USART,UART availability and x,y values depending on device). + * @param __IT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg UART_IT_LBD: LIN Break detection interrupt + * @arg UART_IT_TXE: Transmit Data Register empty interrupt + * @arg UART_IT_TC: Transmission complete interrupt + * @arg UART_IT_RXNE: Receive Data register not empty interrupt + * @arg UART_IT_IDLE: Idle line detection interrupt + * @arg UART_IT_ERR: Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + +/** @brief Enable CTS flow control + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control + * This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control + * This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) + * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). + * It is used to select the USART peripheral (USART availability and x value depending on device). + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) + +/** @brief Macro to enable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Macro to disable the UART's one bit sample method + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU + +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ + + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_UART_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h new file mode 100644 index 0000000..ce19d4d --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h @@ -0,0 +1,2105 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_BUS_H +#define __STM32F4xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN +#if defined(GPIOD) +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN +#endif /* GPIOD */ +#if defined(GPIOE) +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN +#endif /* GPIOE */ +#if defined(GPIOF) +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN +#endif /* GPIOG */ +#if defined(GPIOH) +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN +#endif /* GPIOH */ +#if defined(GPIOI) +#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#if defined(RCC_AHB1ENR_BKPSRAMEN) +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#endif /* RCC_AHB1ENR_BKPSRAMEN */ +#if defined(RCC_AHB1ENR_CCMDATARAMEN) +#define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN +#endif /* RCC_AHB1ENR_CCMDATARAMEN */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(RCC_AHB1ENR_RNGEN) +#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN +#endif /* RCC_AHB1ENR_RNGEN */ +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#endif /* ETH */ +#if defined(USB_OTG_HS) +#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN +#endif /* USB_OTG_HS */ +#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#if defined(RCC_AHB1LPENR_SRAM2LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +#endif /* RCC_AHB1LPENR_SRAM2LPEN */ +#if defined(RCC_AHB1LPENR_SRAM3LPEN) +#define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN +#endif /* RCC_AHB1LPENR_SRAM3LPEN */ +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#if defined(RCC_AHB2ENR_RNGEN) +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#endif /* RCC_AHB2ENR_RNGEN */ +#if defined(USB_OTG_FS) +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +#endif /* USB_OTG_FS */ +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(FSMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN +#endif /* FSMC_Bank1 */ +#if defined(FMC_Bank1) +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#endif /* FMC_Bank1 */ +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM2) +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#endif /* TIM2 */ +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#endif /* TIM3 */ +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /* TIM4 */ +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /* TIM6 */ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /* TIM7 */ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /* TIM12 */ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /* TIM13 */ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /* TIM14 */ +#if defined(LPTIM1) +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN +#endif /* LPTIM1 */ +#if defined(RCC_APB1ENR_RTCAPBEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN +#endif /* RCC_APB1ENR_RTCAPBEN */ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /* SPI2 */ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /* SPI3 */ +#if defined(SPDIFRX) +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN +#endif /* SPDIFRX */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /* USART3 */ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /* UART4 */ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /* UART5 */ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#if defined(I2C3) +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#endif /* I2C3 */ +#if defined(FMPI2C1) +#define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN +#endif /* FMPI2C1 */ +#if defined(CAN1) +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#endif /* CAN1 */ +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /* CAN2 */ +#if defined(CAN3) +#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN +#endif /* CAN3 */ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /* CEC */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(DAC1) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /* DAC1 */ +#if defined(UART7) +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN +#endif /* UART7 */ +#if defined(UART8) +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN +#endif /* UART8 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /* TIM8 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#if defined(USART6) +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#endif /* USART6 */ +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(UART10) +#define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN +#endif /* UART10 */ +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(ADC2) +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#endif /* ADC2 */ +#if defined(ADC3) +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#endif /* ADC3 */ +#if defined(SDIO) +#define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN +#endif /* SDIO */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(SPI4) +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#endif /* SPI4 */ +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#if defined(RCC_APB2ENR_EXTITEN) +#define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN +#endif /* RCC_APB2ENR_EXTITEN */ +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#if defined(TIM10) +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#endif /* TIM10 */ +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#if defined(SPI5) +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#endif /* SPI5 */ +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#if defined(SAI1) +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /* SAI1 */ +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(DFSDM2_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN +#endif /* DFSDM2_Channel0 */ +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +#if defined(RCC_AHB2_SUPPORT) +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB2_SUPPORT */ + +#if defined(RCC_AHB3_SUPPORT) +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ +#endif /* RCC_AHB3_SUPPORT */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_BUS_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h new file mode 100644 index 0000000..9a183ea --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (MPU services provided only on some devices) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_CORTEX_H +#define __STM32F4xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Clear pending events. + * @retval None + */ +__STATIC_INLINE void LL_LPM_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_CORTEX_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h new file mode 100644 index 0000000..055ba5f --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h @@ -0,0 +1,2868 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_DMA_H +#define __STM32F4xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t STREAM_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Channel; /*!< Specifies the peripheral channel. + This parameter can be a value of @ref DMA_LL_EC_CHANNEL + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ +#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ +#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ +#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ +#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ +#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ +#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ +#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ +#if defined (DMA_SxCR_CHSEL_3) +#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ +#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ +#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ +#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ +#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ +#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ +#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ +#define LL_DMA_CHANNEL_15 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel15 of DMA Instance */ +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); +} + +/** + * @brief Select Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_SetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); +} + +/** + * @brief Get the Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_GetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Get Current target (only in double buffer mode). + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); + } + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) + { + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); + } + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrupt is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); +} + +/** + * @brief Check if Transfer complete interrupt is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); +} + +/** + * @brief Check if FIFO error interrupt is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_DMA_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h new file mode 100644 index 0000000..65ab691 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h @@ -0,0 +1,954 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_EXTI_H +#define __STM32F4xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#if defined(EXTI_IMR_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#endif +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19(*) + * @arg @ref LL_EXTI_LINE_20(*) + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_EXTI_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h new file mode 100644 index 0000000..6bee7fd --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h @@ -0,0 +1,981 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_GPIO_H +#define __STM32F4xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, (PinMask << 16)); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_GPIO_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h new file mode 100644 index 0000000..92d4a74 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -0,0 +1,1890 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_I2C_H +#define __STM32F4xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ + +/* Defines used to perform compute and check in the macros */ +#define LL_I2C_MAX_SPEED_STANDARD 100000U +#define LL_I2C_MAX_SPEED_FAST 400000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz (in Hz) + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() + or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + + This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + +#endif + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ +#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or + Address matched flag (slave mode) */ +#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ +#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */ +#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ +#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ +#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ +#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ +#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ +#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ +#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ +#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ +#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ +#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ +#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ +#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */ +#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */ +#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ +#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ +#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ +/** + * @} + */ + +#if defined(I2C_FLTR_ANOFF) +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/ +/** + * @} + */ + +#endif +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle + * @{ + */ +#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ +#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode + * @{ + */ +#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ +#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ +#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported Macros Helper + * @{ + */ + +/** + * @brief Convert Peripheral Clock Frequency in Mhz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @retval Value of peripheral clock (in Mhz) + */ +#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) + +/** + * @brief Convert Peripheral Clock Frequency in Hz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz). + * @retval Value of peripheral clock (in Hz) + */ +#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) + +/** + * @brief Compute I2C Clock rising time. + * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) + +/** + * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ + (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ + (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) + +/** + * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. + */ +#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) + +/** + * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x001 and Max_Data=0xFFF + */ +#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ + (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ + (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) + +/** + * @brief Get the Least significant bits of a 10-Bits address. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Write direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF0 and Max_Data=0xF6 + */ +#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Read direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF1 and Max_Data=0xF7 + */ +#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); +} + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n + * FLTR DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) + * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter); +} +#endif +#if defined(I2C_FLTR_DNF) + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) + * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF)); +} +#endif +#if defined(I2C_FLTR_ANOFF) + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF)); +} +#endif + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll DR DR LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance. + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) & (I2Cx->DR); +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n + * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n + * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n + * OAR1 ADDMODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL)); +} + +/** + * @brief Configure the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); +} + +/** + * @brief Get the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock + * @param I2Cx I2C Instance. + * @retval Value of Peripheral Clock (in Hz) + */ +__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); +} + +/** + * @brief Configure the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_SetDutyCycle + * @param I2Cx I2C Instance. + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); +} + +/** + * @brief Get the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_GetDutyCycle + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + */ +__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); +} + +/** + * @brief Configure the I2C master clock speed mode. + * @rmtoll CCR FS LL_I2C_SetClockSpeedMode + * @param I2Cx I2C Instance. + * @param ClockSpeedMode This parameter can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); +} + +/** + * @brief Get the the I2C master speed mode. + * @rmtoll CCR FS LL_I2C_GetClockSpeedMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); +} + +/** + * @brief Configure the SCL, SDA rising time. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TRISE TRISE LL_I2C_SetRiseTime + * @param I2Cx I2C Instance. + * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) +{ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); +} + +/** + * @brief Get the SCL, SDA rising time. + * @rmtoll TRISE TRISE LL_I2C_GetRiseTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); +} + +/** + * @brief Configure the SCL high and low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CCR CCR LL_I2C_SetClockPeriod + * @param I2Cx I2C Instance. + * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); +} + +/** + * @brief Get the SCL high and low period. + * @rmtoll CCR CCR LL_I2C_GetClockPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); +} + +/** + * @brief Configure the SCL speed. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n + * TRISE TRISE LL_I2C_ConfigSpeed\n + * CCR FS LL_I2C_ConfigSpeed\n + * CCR DUTY LL_I2C_ConfigSpeed\n + * CCR CCR LL_I2C_ConfigSpeed + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, + uint32_t DutyCycle) +{ + uint32_t freqrange = 0x0U; + uint32_t clockconfig = 0x0U; + + /* Compute frequency range */ + freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); + + /* Configure I2Cx: Frequency range register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); + + /* Configure I2Cx: Rise Time register */ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); + + /* Configure Speed mode, Duty Cycle and Clock control register value */ + if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) + { + /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ + __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ + DutyCycle; + } + else + { + /* Set Speed mode at standard for Clock Speed request in standard clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ + __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); + } + + /* Configure I2Cx: Clock control register */ + MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); +} + +/** + * @brief Configure peripheral mode. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_SetMode\n + * CR1 SMBTYPE LL_I2C_SetMode\n + * CR1 ENARP LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_GetMode\n + * CR1 SMBTYPE LL_I2C_GetMode\n + * CR1 ENARP LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT)); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n + * CR2 ITBUFEN LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n + * CR2 ITBUFEN LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the TXE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n + * CR2 ITBUFEN LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n + * CR2 ITBUFEN LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * + * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Disable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Check if Events interrupts are enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); +} + +/** + * @brief Enable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if Buffer interrupts are enabled or disabled. + * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Error interrupts. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Disable Error interrupts. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); +} + +/** + * @brief Indicate the status of Byte Transfer Finished flag. + * RESET: When Data byte transfer not done. + * SET: When Data byte transfer succeeded. + * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); +} + +/** + * @brief Indicate the status of Start Bit (master mode). + * @note RESET: When No Start condition. + * SET: When Start condition is generated. + * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); +} + +/** + * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). + * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); +} + +/** + * @brief Indicate the status of 10-bit header sent (master mode). + * @note RESET: When no ADD10 event occurred. + * SET: When the master has sent the first address byte (header). + * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10)); +} + +/** + * @brief Indicate the status of Acknowledge failure flag. + * @note RESET: No acknowledge failure. + * SET: When an acknowledge failure is received after a byte transmission. + * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); +} + +/** + * @brief Indicate the status of Stop detection flag (slave mode). + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag. + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT)); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT)); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); +} + +/** + * @brief Indicate the status of Dual flag. + * @note RESET: Received address matched with OAR1. + * SET: Received address matched with OAR2. + * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF)); +} + +/** + * @brief Indicate the status of SMBus Host address reception (Slave mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Host address + * SET: SMBus Host address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST)); +} + +/** + * @brief Indicate the status of SMBus Device default address reception (Slave mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Device default address + * SET: SMBus Device default address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT)); +} + +/** + * @brief Indicate the status of General call address reception (Slave mode). + * @note RESET: No General call address + * SET: General call address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); +} + +/** + * @brief Indicate the status of Master/Slave flag. + * @note RESET: Slave Mode. + * SET: Master Mode. + * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); +} + +/** + * @brief Clear Address Matched flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a read access to the I2Cx_SR2 register. + * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + tmpreg = I2Cx->SR2; + (void) tmpreg; +} + +/** + * @brief Clear Acknowledge failure flag. + * @rmtoll SR1 AF LL_I2C_ClearFlag_AF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); +} + +/** + * @brief Clear Stop detection flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a write access to I2Cx_CR1 register. + * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n + * CR1 PE LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); +} + +/** + * @brief Clear SMBus PEC error flag. + * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_EnableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Disable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_DisableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Check if the I2C peripheral is under reset state or not. + * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave or Master mode. + * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR1 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Enable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_EnableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Disable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_DisableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Check if bit POS is enabled or disabled. + * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); +} + +/** + * @brief Indicate the value of transfer direction. + * @note RESET: Bus is in read transfer (peripheral point of view). + * SET: Bus is in write transfer (peripheral point of view). + * @rmtoll SR2 TRA LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); +} + +/** + * @brief Enable DMA last transfer. + * @note This action mean that next DMA EOT is the last transfer. + * @rmtoll CR2 LAST LL_I2C_EnableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Disable DMA last transfer. + * @note This action mean that next DMA EOT is not the last transfer. + * @rmtoll CR2 LAST LL_I2C_DisableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Check if DMA last transfer is enabled or disabled. + * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); +} + +/** + * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred or compared, + * or by a START or STOP condition, it is also cleared by software. + * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC)); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos); +} + +/** + * @brief Read Receive Data register. + * @rmtoll DR DR LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll DR DR LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_I2C_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h new file mode 100644 index 0000000..ea23dc5 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h @@ -0,0 +1,985 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_PWR_H +#define __STM32F4xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */ +#if defined(PWR_CSR_EWUP) +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */ +#elif defined(PWR_CSR_EWUP1) +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#endif /* PWR_CSR_EWUP */ +#if defined(PWR_CSR_EWUP2) +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#endif /* PWR_CSR_EWUP2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#if defined(PWR_CR_VOS_0) +#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0) +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS) +#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U +#endif /* PWR_CR_VOS_0 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) +#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) +#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */ +#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#if defined(PWR_CSR_EWUP) +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */ +#endif /* PWR_CSR_EWUP */ +#if defined(PWR_CSR_EWUP1) +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#endif /* PWR_CSR_EWUP1 */ +#if defined(PWR_CSR_EWUP2) +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */ +#endif /* PWR_CSR_EWUP2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ +#if defined(PWR_CR_FISSR) +/** + * @brief Enable FLASH interface STOP while system Run is ON + * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP + * @note This mode is enabled only with STOP low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void) +{ + SET_BIT(PWR->CR, PWR_CR_FISSR); +} + +/** + * @brief Disable FLASH Interface STOP while system Run is ON + * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); +} + +/** + * @brief Check if FLASH Interface STOP while system Run feature is enabled + * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR)); +} +#endif /* PWR_CR_FISSR */ + +#if defined(PWR_CR_FMSSR) +/** + * @brief Enable FLASH Memory STOP while system Run is ON + * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP + * @note This mode is enabled only with STOP low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void) +{ + SET_BIT(PWR->CR, PWR_CR_FMSSR); +} + +/** + * @brief Disable FLASH Memory STOP while system Run is ON + * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); +} + +/** + * @brief Check if FLASH Memory STOP while system Run feature is enabled + * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR)); +} +#endif /* PWR_CR_FMSSR */ +#if defined(PWR_CR_UDEN) +/** + * @brief Enable Under Drive Mode + * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main Regulator or the low power Regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage Regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_UDEN); +} + +/** + * @brief Disable Under Drive Mode + * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_UDEN); +} + +/** + * @brief Check if Under Drive Mode is enabled + * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN)); +} +#endif /* PWR_CR_UDEN */ + +#if defined(PWR_CR_ODSWEN) +/** + * @brief Enable Over drive switching + * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) +{ + SET_BIT(PWR->CR, PWR_CR_ODSWEN); +} + +/** + * @brief Disable Over drive switching + * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN)); +} +#endif /* PWR_CR_ODSWEN */ +#if defined(PWR_CR_ODEN) +/** + * @brief Enable Over drive Mode + * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_ODEN); +} + +/** + * @brief Disable Over drive Mode + * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ODEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN)); +} +#endif /* PWR_CR_ODEN */ +#if defined(PWR_CR_MRUDS) +/** + * @brief Enable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_MRUDS); +} + +/** + * @brief Disable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_MRUDS); +} + +/** + * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS)); +} +#endif /* PWR_CR_MRUDS */ + +#if defined(PWR_CR_LPUDS) +/** + * @brief Enable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPUDS); +} + +/** + * @brief Disable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPUDS); +} + +/** + * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS)); +} +#endif /* PWR_CR_LPUDS */ + +#if defined(PWR_CR_MRLVDS) +/** + * @brief Enable Main Regulator low voltage Mode + * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_MRLVDS); +} + +/** + * @brief Disable Main Regulator low voltage Mode + * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS); +} + +/** + * @brief Check if Main Regulator low voltage Mode is enabled + * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS)); +} +#endif /* PWR_CR_MRLVDS */ + +#if defined(PWR_CR_LPLVDS) +/** + * @brief Enable Low Power Regulator low voltage Mode + * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPLVDS); +} + +/** + * @brief Disable Low Power Regulator low voltage Mode + * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS); +} + +/** + * @brief Check if Low Power Regulator low voltage Mode is enabled + * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS)); +} +#endif /* PWR_CR_LPLVDS */ +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*) + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); +} +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR, PWR_CR_FPDS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FPDS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} +/** + * @brief Enable the backup Regulator + * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator + * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. + * The LL_PWR_EnableBkUpAccess() must be called before using this API. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CSR, PWR_CSR_BRE); +} + +/** + * @brief Disable the backup Regulator + * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator + * @note The BRE bit of the PWR_CSR register is protected against parasitic write access. + * The LL_PWR_EnableBkUpAccess() must be called before using this API. + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CSR, PWR_CSR_BRE); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE)); +} + +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n + * @rmtoll CR FPDS LL_PWR_SetPowerMode\n + * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n + * @rmtoll CR FPDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) + * + * (*) not available on all devices + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode); +#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode); +#else + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n + * @rmtoll CR FPDS LL_PWR_GetPowerMode\n + * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n + * @rmtoll CR FPDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*) + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*) + * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*) + * + * (*) not available on all devices + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ +#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS) + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS))); +#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS) + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS))); +#else + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */ +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 (*) + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR)); +} +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); +} +#if defined(PWR_CR_ODEN) +/** + * @brief Indicate whether the Over-Drive mode is ready or not + * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY)); +} +#endif /* PWR_CR_ODEN */ + +#if defined(PWR_CR_ODSWEN) +/** + * @brief Indicate whether the Over-Drive mode switching is ready or not + * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY)); +} +#endif /* PWR_CR_ODSWEN */ + +#if defined(PWR_CR_UDEN) +/** + * @brief Indicate whether the Under-Drive mode is ready or not + * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY)); +} +#endif /* PWR_CR_UDEN */ +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} +#if defined(PWR_CSR_UDRDY) +/** + * @brief Clear Under-Drive ready Flag + * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) +{ + WRITE_REG(PWR->CSR, PWR_CSR_UDRDY); +} +#endif /* PWR_CSR_UDRDY */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_PWR_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h new file mode 100644 index 0000000..0a6a5b9 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @@ -0,0 +1,7101 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_RCC_H +#define __STM32F4xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +#if defined(RCC_PLLSAI_SUPPORT) && defined(LTDC) +static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* RCC_PLLSAI_SUPPORT && LTDC */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ +#endif /* RCC_PLLSAI_SUPPORT */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ +#endif /* RCC_PLLSAI_SUPPORT */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#if defined(RCC_CSR_BORRSTF) +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +#endif /* RCC_CSR_BORRSTF */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_PLLI2S_SUPPORT) +#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +#if defined(RCC_CFGR_SW_PLLR) +#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ +#endif /* RCC_CFGR_SW_PLLR */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +#if defined(RCC_PLLR_SYSCLK_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ +#if defined(RCC_CFGR_MCO2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ +#endif /* RCC_CFGR_MCO2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ +#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ +#if defined(RCC_CFGR_MCO2PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ +#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ +#endif /* RCC_CFGR_MCO2PRE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ +#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ +#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ +#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ +#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ +#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ +#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ +#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ +#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ +#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ +#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ +#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ +#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ +#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ +#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ +#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ +#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ +#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ +#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ +#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ +#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ +#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ +#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ +#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ +#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ +#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ +#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ +#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined(FMPI2C1) +/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection + * @{ + */ +#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ +#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ +#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ +/** + * @} + */ +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ +/** + * @} + */ +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_DCKCFGR_SAI1SRC) +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ +#endif /* RCC_DCKCFGR_SAI1SRC */ +#if defined(RCC_DCKCFGR_SAI2SRC) +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ +#endif /* RCC_DCKCFGR_SAI2SRC */ +#if defined(RCC_DCKCFGR_SAI1ASRC) +#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) +#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ +#else +#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ +#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ +#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ +#endif /* RCC_DCKCFGR_SAI1ASRC */ +#if defined(RCC_DCKCFGR_SAI1BSRC) +#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) +#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ +#else +#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ +#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ +#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ +#endif /* RCC_DCKCFGR_SAI1BSRC */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection + * @{ + */ +#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ +#if defined(RCC_DCKCFGR_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ +#else +#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ +#endif /* RCC_DCKCFGR_SDIOSEL */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#if defined(RCC_CFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ +#endif /* RCC_CFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ +#endif /* RCC_DCKCFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2S1SRC) +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ +#endif /* RCC_DCKCFGR_I2S1SRC */ +#if defined(RCC_DCKCFGR_I2S2SRC) +#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ +#endif /* RCC_DCKCFGR_I2S2SRC */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +#if defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ +#if defined(RCC_PLLSAI_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ +#endif /* RCC_PLLSAI_SUPPORT */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +/** + * @} + */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ +#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ + +#if defined(FMPI2C1) +/** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source + * @{ + */ +#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ +/** + * @} + */ +#endif /* FMPI2C1 */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ +#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ +/** + * @} + */ +#endif /* SPDIFRX */ + +#if defined(LPTIM1) +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_SAI1ASRC) +#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1ASRC */ +#if defined(RCC_DCKCFGR_SAI1BSRC) +#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1BSRC */ +#if defined(RCC_DCKCFGR_SAI1SRC) +#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ +#endif /* RCC_DCKCFGR_SAI1SRC */ +#if defined(RCC_DCKCFGR_SAI2SRC) +#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ +#endif /* RCC_DCKCFGR_SAI2SRC */ +/** + * @} + */ +#endif /* SAI1 */ + +#if defined(SDIO) +/** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ +#elif defined(RCC_DCKCFGR2_SDIOSEL) +#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ +#else +#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ +#endif /* RCC_DCKCFGR_SDIOSEL */ +/** + * @} + */ +#endif /* SDIO */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +#if defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ +#else +#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ +#else +#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ +/** + * @} + */ +#endif /* USB_OTG_FS || USB_OTG_HS */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#if defined(RCC_CFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ +#endif /* RCC_CFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2SSRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ +#endif /* RCC_DCKCFGR_I2SSRC */ +#if defined(RCC_DCKCFGR_I2S1SRC) +#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ +#endif /* RCC_DCKCFGR_I2S1SRC */ +#if defined(RCC_DCKCFGR_I2S2SRC) +#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ +#endif /* RCC_DCKCFGR_I2S2SRC */ +/** + * @} + */ + +#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) +/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ +#if defined(DFSDM2_Channel0) +#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ +/** + * @} + */ +#endif /* SPDIFRX */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_TIMPRE) +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_TIMPRE */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) +#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ +#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ +#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ +#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ +#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ +#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ +#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ +#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ +#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ +#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ +#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ +#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ +#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ +#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ +#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ +#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ +#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ +#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ +#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ +#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ +#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ +#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ +#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ +#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ +#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ +#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ +#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ +#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ +#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ +#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ +#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ +#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ +#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ +#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ +#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ +#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ +#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ +#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ +#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ +#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ +#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ +#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ +#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ +#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ +#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ +#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ +#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ +#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ +#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ +/** + * @} + */ + +#if defined(RCC_PLLCFGR_PLLR) +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +/** + * @} + */ +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_DCKCFGR_PLLDIVR) +/** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) + * @{ + */ +#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ +#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ +#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ +#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ +#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ +#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ +#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ +#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ +#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ +#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ +#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ +#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ +#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ +#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ +#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ +#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ +#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ +#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ +#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ +#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ +#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ +#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ +#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ +#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ +#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ +#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ +#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ +#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ +#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ +#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ +#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLDIVR */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ +#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ +#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ +#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ +#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ +#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ +#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ +#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + * @{ + */ +#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ +#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) + * @{ + */ +#if defined(RCC_PLLI2SCFGR_PLLI2SM) +#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ +#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ +#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ +#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ +#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ +#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ +#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ +#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ +#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ +#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ +#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ +#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ +#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ +#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ +#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ +#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ +#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ +#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ +#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ +#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ +#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ +#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ +#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ +#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ +#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ +#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ +#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ +#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ +#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ +#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ +#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ +#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ +#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ +#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ +#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ +#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ +#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ +#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ +#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ +#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ +#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ +#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ +#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ +#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ +#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ +#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ +#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ +#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ +#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ +#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ +#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ +#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ +#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ +#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ +#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ +#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ +#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ +#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ +#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ +#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ +#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ +#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ +#else +#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ +#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ +#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ +#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ +#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ +#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ +#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ +#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ +#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ +#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ +#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ +#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ +#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ +#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ +#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ +#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ +#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ +#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ +#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ +#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ +#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ +#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ +#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ +#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ +#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ +#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ +#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ +#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ +#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ +#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ +#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ +#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ +#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ +#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ +#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ +#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ +#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ +#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ +#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ +#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ +#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ +#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ +#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ +#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ +#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ +#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ +#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ +#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ +#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ +#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ +#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ +#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ +#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ +#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ +#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ +#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ +#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ +#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ +#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ +#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ +#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ +#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) +/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + * @{ + */ +#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ +#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ +#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ +#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ +#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ +#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ +#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ +#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ +#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ +#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ +#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ +#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ +#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ +#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + * @{ + */ +#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ +#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ +#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ +#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ +#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ +#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ +#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ +#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ +#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ +#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ +#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ +#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ +#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ +#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ +#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ +#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ +#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ +#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ +#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ +#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ +#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ +#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ +#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ +#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ +#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ +#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ +#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ +#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ +#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ +#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ +#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ +#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVR) +/** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) + * @{ + */ +#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ +#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ +#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ +#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ +#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ +#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ +#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ +#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ +#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ +#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ +#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ +#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ +#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ +#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ +#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ +#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ +#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ +#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ +#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ +#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ +#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ +#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ +#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ +#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ +#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ +#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ +#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ +#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ +#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ +#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ +#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLI2SDIVR */ + +/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + * @{ + */ +#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ +#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ +#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ +#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ +#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ +#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + * @{ + */ +#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ +#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ +#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ +#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) + * @{ + */ +#if defined(RCC_PLLSAICFGR_PLLSAIM) +#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ +#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ +#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ +#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ +#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ +#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ +#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ +#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ +#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ +#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ +#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ +#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ +#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ +#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ +#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ +#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ +#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ +#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ +#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ +#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ +#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ +#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ +#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ +#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ +#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ +#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ +#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ +#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ +#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ +#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ +#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ +#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ +#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ +#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ +#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ +#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ +#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ +#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ +#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ +#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ +#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ +#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ +#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ +#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ +#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ +#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ +#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ +#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ +#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ +#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ +#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ +#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ +#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ +#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ +#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ +#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ +#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ +#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ +#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ +#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ +#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ +#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ +#else +#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ +#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ +#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ +#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ +#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ +#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ +#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ +#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ +#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ +#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ +#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ +#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ +#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ +#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ +#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ +#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ +#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ +#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ +#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ +#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ +#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ +#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ +#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ +#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ +#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ +#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ +#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ +#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ +#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ +#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ +#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ +#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ +#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ +#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ +#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ +#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ +#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ +#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ +#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ +#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ +#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ +#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ +#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ +#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ +#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ +#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ +#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ +#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ +#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ +#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ +#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ +#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ +#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ +#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ +#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ +#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ +#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ +#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ +#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ +#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ +#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ +#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + * @{ + */ +#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ +#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ +#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ +#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ +#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ +#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ +#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ +#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ +#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ +#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ +#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ +#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ +#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ +#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ +/** + * @} + */ + +#if defined(RCC_DCKCFGR_PLLSAIDIVQ) +/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + * @{ + */ +#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ +#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ +#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ +#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ +#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ +#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ +#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ +#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ +#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ +#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ +#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ +#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ +#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ +#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ +#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ +#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ +#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ +#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ +#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ +#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ +#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ +#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ +#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ +#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ +#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ +#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ +#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ +#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ +#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ +#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ +#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ +#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLSAIDIVQ */ + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + * @{ + */ +#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ +#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ +#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ +#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ +#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ +#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_DCKCFGR_PLLSAIDIVR) +/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + * @{ + */ +#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ +#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ +#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ +#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR_PLLSAIDIVR */ + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) + * @{ + */ +#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ +#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ +#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ +#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#endif /* RCC_PLLSAI_SUPPORT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) + +#if defined(RCC_PLLR_SYSCLK_SUPPORT) +/** + * @brief Helper macro to calculate the PLLRCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) + +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* DSI */ + +#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on I2S + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* SPDIFRX */ + +#if defined(RCC_PLLCFGR_PLLR) +#if defined(SAI1) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on SAI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @param __PLLDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval PLL clock frequency (in Hz) + */ +#if defined(RCC_DCKCFGR_PLLDIVR) +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) +#else +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* RCC_DCKCFGR_PLLDIVR */ +#endif /* SAI1 */ +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLSAIQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param __PLLSAIDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param __PLLSAIN__ Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLSAIR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param __PLLSAIDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) +#endif /* LTDC */ +#endif /* RCC_PLLSAI_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) +/** + * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLI2SQ_R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval PLLI2S clock frequency (in Hz) + */ +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) +#else +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) + +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) + +#endif /* SPDIFRX */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param __PLLI2SR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) + +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ +#endif /* RCC_PLLI2S_SUPPORT */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) &\ + RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +#if defined(RCC_BDCR_LSEMOD) +/** + * @brief Enable LSE high drive mode. + * @note LSE high drive mode can be enabled only when the LSE clock is disabled + * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); +} + +/** + * @brief Disable LSE high drive mode. + * @note LSE high drive mode can be disabled only when the LSE clock is disabled + * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); +} +#endif /* RCC_BDCR_LSEMOD */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +#if defined(RCC_CFGR_MCO1EN) +/** + * @brief Enable MCO1 output + * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO1_Enable(void) +{ + SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); +} + +/** + * @brief Disable MCO1 output + * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO1_Disable(void) +{ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); +} +#endif /* RCC_CFGR_MCO1EN */ + +#if defined(RCC_CFGR_MCO2EN) +/** + * @brief Enable MCO2 output + * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO2_Enable(void) +{ + SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); +} + +/** + * @brief Disable MCO2 output + * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MCO2_Disable(void) +{ + CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); +} +#endif /* RCC_CFGR_MCO2EN */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ +#if defined(FMPI2C1) +/** + * @brief Configure FMPI2C clock source + * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource + * @param FMPI2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); +} +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** + * @brief Configure LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +} +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** + * @brief Configure SAIx clock source + * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n + * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +} +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** + * @brief Configure SDIO clock source + * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n + * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource + * @param SDIOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) +{ +#if defined(RCC_DCKCFGR_SDIOSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); +#endif /* RCC_DCKCFGR_SDIOSEL */ +} +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** + * @brief Configure 48Mhz domain clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource + * @param CK48MxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} + +#if defined(RNG) +/** + * @brief Configure RNG clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** + * @brief Configure USB clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); +#else + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* USB_OTG_FS || USB_OTG_HS */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +} +#endif /* CEC */ + +/** + * @brief Configure I2S clock source + * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n + * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +{ +#if defined(RCC_CFGR_I2SSRC) + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +#else + MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); +#endif /* RCC_CFGR_I2SSRC */ +} + +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(DFSDM1_Channel0) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n + * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); +} + +/** + * @brief Configure DFSDM Kernel clock source + * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(SPDIFRX) +/** + * @brief Configure SPDIFRX clock source + * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource + * @param SPDIFRXxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); +} +#endif /* SPDIFRX */ + +#if defined(FMPI2C1) +/** + * @brief Get FMPI2C clock source + * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource + * @param FMPI2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); +} +#endif /* FMPI2C1 */ + +#if defined(LPTIM1) +/** + * @brief Get LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +} +#endif /* LPTIM1 */ + +#if defined(SAI1) +/** + * @brief Get SAIx clock source + * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n + * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); +} +#endif /* SAI1 */ + +#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) +/** + * @brief Get SDIOx clock source + * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n + * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource + * @param SDIOx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) +{ +#if defined(RCC_DCKCFGR_SDIOSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); +#endif /* RCC_DCKCFGR_SDIOSEL */ +} +#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ + +#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) +/** + * @brief Get 48Mhz domain clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource + * @param CK48Mx This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} + +#if defined(RNG) +/** + * @brief Get RNGx clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* RNG */ + +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +/** + * @brief Get USBx clock source + * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n + * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ +#if defined(RCC_DCKCFGR_CK48MSEL) + return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +#endif /* RCC_DCKCFGR_CK48MSEL */ +} +#endif /* USB_OTG_FS || USB_OTG_HS */ +#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ + +#if defined(CEC) +/** + * @brief Get CEC Clock Source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +} +#endif /* CEC */ + +/** + * @brief Get I2S Clock Source + * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n + * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ +#if defined(RCC_CFGR_I2SSRC) + return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +#else + return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); +#endif /* RCC_CFGR_I2SSRC */ +} + +#if defined(DFSDM1_Channel0) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n + * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) + * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); +} + +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(SPDIFRX) +/** + * @brief Get SPDIFRX clock source + * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource + * @param SPDIFRXx This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL + * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); +} +#endif /* SPDIFRX */ + +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); +} +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +#if defined(RCC_DCKCFGR_TIMPRE) +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); +} + +/** + * @} + */ +#endif /* RCC_DCKCFGR_TIMPRE */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLP_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLR_DIV_2 (*) + * @arg @ref LL_RCC_PLLR_DIV_3 (*) + * @arg @ref LL_RCC_PLLR_DIV_4 (*) + * @arg @ref LL_RCC_PLLR_DIV_5 (*) + * @arg @ref LL_RCC_PLLR_DIV_6 (*) + * @arg @ref LL_RCC_PLLR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); +#if defined(RCC_PLLR_SYSCLK_SUPPORT) + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); +#endif /* RCC_PLLR_SYSCLK_SUPPORT */ +} + +/** + * @brief Configure PLL used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note This can be selected for USB, RNG, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +} + +#if defined(DSI) +/** + * @brief Configure PLL used for DSI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* DSI */ + +#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) +/** + * @brief Configure PLL used for I2S clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ + +#if defined(SPDIFRX) +/** + * @brief Configure PLL used for SPDIFRX clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* SPDIFRX */ + +#if defined(RCC_PLLCFGR_PLLR) +#if defined(SAI1) +/** + * @brief Configure PLL used for SAI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n + * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +#if defined(RCC_DCKCFGR_PLLDIVR) +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, + uint32_t PLLDIVR) +#else +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +#endif /* RCC_DCKCFGR_PLLDIVR */ +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +#if defined(RCC_DCKCFGR_PLLDIVR) + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); +#endif /* RCC_DCKCFGR_PLLDIVR */ +} +#endif /* SAI1 */ +#endif /* RCC_PLLCFGR_PLLR */ + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +#if defined(RCC_PLLCFGR_PLLR) +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} +#endif /* RCC_PLLCFGR_PLLR */ + +#if defined(RCC_DCKCFGR_PLLDIVR) +/** + * @brief Get Main PLL division factor for PLLDIVR + * @note used for PLLSAICLK (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLDIVR_DIV_1 + * @arg @ref LL_RCC_PLLDIVR_DIV_2 + * @arg @ref LL_RCC_PLLDIVR_DIV_3 + * @arg @ref LL_RCC_PLLDIVR_DIV_4 + * @arg @ref LL_RCC_PLLDIVR_DIV_5 + * @arg @ref LL_RCC_PLLDIVR_DIV_6 + * @arg @ref LL_RCC_PLLDIVR_DIV_7 + * @arg @ref LL_RCC_PLLDIVR_DIV_8 + * @arg @ref LL_RCC_PLLDIVR_DIV_9 + * @arg @ref LL_RCC_PLLDIVR_DIV_10 + * @arg @ref LL_RCC_PLLDIVR_DIV_11 + * @arg @ref LL_RCC_PLLDIVR_DIV_12 + * @arg @ref LL_RCC_PLLDIVR_DIV_13 + * @arg @ref LL_RCC_PLLDIVR_DIV_14 + * @arg @ref LL_RCC_PLLDIVR_DIV_15 + * @arg @ref LL_RCC_PLLDIVR_DIV_16 + * @arg @ref LL_RCC_PLLDIVR_DIV_17 + * @arg @ref LL_RCC_PLLDIVR_DIV_18 + * @arg @ref LL_RCC_PLLDIVR_DIV_19 + * @arg @ref LL_RCC_PLLDIVR_DIV_20 + * @arg @ref LL_RCC_PLLDIVR_DIV_21 + * @arg @ref LL_RCC_PLLDIVR_DIV_22 + * @arg @ref LL_RCC_PLLDIVR_DIV_23 + * @arg @ref LL_RCC_PLLDIVR_DIV_24 + * @arg @ref LL_RCC_PLLDIVR_DIV_25 + * @arg @ref LL_RCC_PLLDIVR_DIV_26 + * @arg @ref LL_RCC_PLLDIVR_DIV_27 + * @arg @ref LL_RCC_PLLDIVR_DIV_28 + * @arg @ref LL_RCC_PLLDIVR_DIV_29 + * @arg @ref LL_RCC_PLLDIVR_DIV_30 + * @arg @ref LL_RCC_PLLDIVR_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); +} +#endif /* RCC_DCKCFGR_PLLDIVR */ + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Configure Spread Spectrum used for PLL + * @note These bits must be written before enabling PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum + * @param Mod Between Min_Data=0 and Max_Data=8191 + * @param Inc Between Min_Data=0 and Max_Data=32767 + * @param Sel This parameter can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +{ + MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Incrementation Step for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +} + +/** + * @brief Enable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +{ + SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +{ + CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); +} + +#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) +/** + * @brief Configure PLLI2S used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) + * + * (*) value not defined in all devices. + * @param PLLDIVQ_R This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, + uint32_t PLLDIVQ_R) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); +#else + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ +} +#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Configure PLLI2S used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLLI2S is disabled + * @note This can be selected for RNG, USB, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(SPDIFRX) +/** + * @brief Configure PLLI2S used for SPDIFRX domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLLI2S is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); +} +#endif /* SPDIFRX */ + +/** + * @brief Configure PLLI2S used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + * @param PLLN Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); + MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); +} + +/** + * @brief Get I2SPLL multiplication factor for VCO + * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN + * @retval Between 50/192(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) +/** + * @brief Get I2SPLL division factor for PLLI2SQ + * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + +/** + * @brief Get I2SPLL division factor for PLLI2SR + * @note used for PLLI2SCLK (I2S clock) + * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** + * @brief Get I2SPLL division factor for PLLI2SP + * @note used for PLLSPDIFRXCLK (SPDIFRX clock) + * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVQ) +/** + * @brief Get I2SPLL division factor for PLLI2SDIVQ + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); +} +#endif /* RCC_DCKCFGR_PLLI2SDIVQ */ + +#if defined(RCC_DCKCFGR_PLLI2SDIVR) +/** + * @brief Get I2SPLL division factor for PLLI2SDIVR + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); +} +#endif /* RCC_DCKCFGR_PLLI2SDIVR */ + +/** + * @brief Get division factor for PLLI2S input clock + * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n + * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SM_DIV_2 + * @arg @ref LL_RCC_PLLI2SM_DIV_3 + * @arg @ref LL_RCC_PLLI2SM_DIV_4 + * @arg @ref LL_RCC_PLLI2SM_DIV_5 + * @arg @ref LL_RCC_PLLI2SM_DIV_6 + * @arg @ref LL_RCC_PLLI2SM_DIV_7 + * @arg @ref LL_RCC_PLLI2SM_DIV_8 + * @arg @ref LL_RCC_PLLI2SM_DIV_9 + * @arg @ref LL_RCC_PLLI2SM_DIV_10 + * @arg @ref LL_RCC_PLLI2SM_DIV_11 + * @arg @ref LL_RCC_PLLI2SM_DIV_12 + * @arg @ref LL_RCC_PLLI2SM_DIV_13 + * @arg @ref LL_RCC_PLLI2SM_DIV_14 + * @arg @ref LL_RCC_PLLI2SM_DIV_15 + * @arg @ref LL_RCC_PLLI2SM_DIV_16 + * @arg @ref LL_RCC_PLLI2SM_DIV_17 + * @arg @ref LL_RCC_PLLI2SM_DIV_18 + * @arg @ref LL_RCC_PLLI2SM_DIV_19 + * @arg @ref LL_RCC_PLLI2SM_DIV_20 + * @arg @ref LL_RCC_PLLI2SM_DIV_21 + * @arg @ref LL_RCC_PLLI2SM_DIV_22 + * @arg @ref LL_RCC_PLLI2SM_DIV_23 + * @arg @ref LL_RCC_PLLI2SM_DIV_24 + * @arg @ref LL_RCC_PLLI2SM_DIV_25 + * @arg @ref LL_RCC_PLLI2SM_DIV_26 + * @arg @ref LL_RCC_PLLI2SM_DIV_27 + * @arg @ref LL_RCC_PLLI2SM_DIV_28 + * @arg @ref LL_RCC_PLLI2SM_DIV_29 + * @arg @ref LL_RCC_PLLI2SM_DIV_30 + * @arg @ref LL_RCC_PLLI2SM_DIV_31 + * @arg @ref LL_RCC_PLLI2SM_DIV_32 + * @arg @ref LL_RCC_PLLI2SM_DIV_33 + * @arg @ref LL_RCC_PLLI2SM_DIV_34 + * @arg @ref LL_RCC_PLLI2SM_DIV_35 + * @arg @ref LL_RCC_PLLI2SM_DIV_36 + * @arg @ref LL_RCC_PLLI2SM_DIV_37 + * @arg @ref LL_RCC_PLLI2SM_DIV_38 + * @arg @ref LL_RCC_PLLI2SM_DIV_39 + * @arg @ref LL_RCC_PLLI2SM_DIV_40 + * @arg @ref LL_RCC_PLLI2SM_DIV_41 + * @arg @ref LL_RCC_PLLI2SM_DIV_42 + * @arg @ref LL_RCC_PLLI2SM_DIV_43 + * @arg @ref LL_RCC_PLLI2SM_DIV_44 + * @arg @ref LL_RCC_PLLI2SM_DIV_45 + * @arg @ref LL_RCC_PLLI2SM_DIV_46 + * @arg @ref LL_RCC_PLLI2SM_DIV_47 + * @arg @ref LL_RCC_PLLI2SM_DIV_48 + * @arg @ref LL_RCC_PLLI2SM_DIV_49 + * @arg @ref LL_RCC_PLLI2SM_DIV_50 + * @arg @ref LL_RCC_PLLI2SM_DIV_51 + * @arg @ref LL_RCC_PLLI2SM_DIV_52 + * @arg @ref LL_RCC_PLLI2SM_DIV_53 + * @arg @ref LL_RCC_PLLI2SM_DIV_54 + * @arg @ref LL_RCC_PLLI2SM_DIV_55 + * @arg @ref LL_RCC_PLLI2SM_DIV_56 + * @arg @ref LL_RCC_PLLI2SM_DIV_57 + * @arg @ref LL_RCC_PLLI2SM_DIV_58 + * @arg @ref LL_RCC_PLLI2SM_DIV_59 + * @arg @ref LL_RCC_PLLI2SM_DIV_60 + * @arg @ref LL_RCC_PLLI2SM_DIV_61 + * @arg @ref LL_RCC_PLLI2SM_DIV_62 + * @arg @ref LL_RCC_PLLI2SM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) +{ +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n + * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) +{ +#if defined(RCC_PLLI2SCFGR_PLLI2SSRC) + uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); + uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); + uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; + return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ +} + +/** + * @} + */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** @defgroup RCC_LL_EF_PLLSAI PLLSAI + * @{ + */ + +/** + * @brief Enable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Disable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Check if PLLSAI Ready + * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); +} + +/** + * @brief Configure PLLSAI used for SAI domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLQ can be written only when PLLSAI is disabled + * @note This can be selected for SAI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n + * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, + uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Configure PLLSAI used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLP can be written only when PLLSAI is disabled + * @note This can be selected for USB, RNG, SDIO + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); +#else + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); +} +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +#if defined(LTDC) +/** + * @brief Configure PLLSAI used for LTDC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI(*) are disabled + * @note PLLN/PLLR can be written only when PLLSAI is disabled + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + * @param PLLN Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, + uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); + MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); +} +#endif /* LTDC */ + +/** + * @brief Get division factor for PLLSAI input clock + * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n + * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIM_DIV_2 + * @arg @ref LL_RCC_PLLSAIM_DIV_3 + * @arg @ref LL_RCC_PLLSAIM_DIV_4 + * @arg @ref LL_RCC_PLLSAIM_DIV_5 + * @arg @ref LL_RCC_PLLSAIM_DIV_6 + * @arg @ref LL_RCC_PLLSAIM_DIV_7 + * @arg @ref LL_RCC_PLLSAIM_DIV_8 + * @arg @ref LL_RCC_PLLSAIM_DIV_9 + * @arg @ref LL_RCC_PLLSAIM_DIV_10 + * @arg @ref LL_RCC_PLLSAIM_DIV_11 + * @arg @ref LL_RCC_PLLSAIM_DIV_12 + * @arg @ref LL_RCC_PLLSAIM_DIV_13 + * @arg @ref LL_RCC_PLLSAIM_DIV_14 + * @arg @ref LL_RCC_PLLSAIM_DIV_15 + * @arg @ref LL_RCC_PLLSAIM_DIV_16 + * @arg @ref LL_RCC_PLLSAIM_DIV_17 + * @arg @ref LL_RCC_PLLSAIM_DIV_18 + * @arg @ref LL_RCC_PLLSAIM_DIV_19 + * @arg @ref LL_RCC_PLLSAIM_DIV_20 + * @arg @ref LL_RCC_PLLSAIM_DIV_21 + * @arg @ref LL_RCC_PLLSAIM_DIV_22 + * @arg @ref LL_RCC_PLLSAIM_DIV_23 + * @arg @ref LL_RCC_PLLSAIM_DIV_24 + * @arg @ref LL_RCC_PLLSAIM_DIV_25 + * @arg @ref LL_RCC_PLLSAIM_DIV_26 + * @arg @ref LL_RCC_PLLSAIM_DIV_27 + * @arg @ref LL_RCC_PLLSAIM_DIV_28 + * @arg @ref LL_RCC_PLLSAIM_DIV_29 + * @arg @ref LL_RCC_PLLSAIM_DIV_30 + * @arg @ref LL_RCC_PLLSAIM_DIV_31 + * @arg @ref LL_RCC_PLLSAIM_DIV_32 + * @arg @ref LL_RCC_PLLSAIM_DIV_33 + * @arg @ref LL_RCC_PLLSAIM_DIV_34 + * @arg @ref LL_RCC_PLLSAIM_DIV_35 + * @arg @ref LL_RCC_PLLSAIM_DIV_36 + * @arg @ref LL_RCC_PLLSAIM_DIV_37 + * @arg @ref LL_RCC_PLLSAIM_DIV_38 + * @arg @ref LL_RCC_PLLSAIM_DIV_39 + * @arg @ref LL_RCC_PLLSAIM_DIV_40 + * @arg @ref LL_RCC_PLLSAIM_DIV_41 + * @arg @ref LL_RCC_PLLSAIM_DIV_42 + * @arg @ref LL_RCC_PLLSAIM_DIV_43 + * @arg @ref LL_RCC_PLLSAIM_DIV_44 + * @arg @ref LL_RCC_PLLSAIM_DIV_45 + * @arg @ref LL_RCC_PLLSAIM_DIV_46 + * @arg @ref LL_RCC_PLLSAIM_DIV_47 + * @arg @ref LL_RCC_PLLSAIM_DIV_48 + * @arg @ref LL_RCC_PLLSAIM_DIV_49 + * @arg @ref LL_RCC_PLLSAIM_DIV_50 + * @arg @ref LL_RCC_PLLSAIM_DIV_51 + * @arg @ref LL_RCC_PLLSAIM_DIV_52 + * @arg @ref LL_RCC_PLLSAIM_DIV_53 + * @arg @ref LL_RCC_PLLSAIM_DIV_54 + * @arg @ref LL_RCC_PLLSAIM_DIV_55 + * @arg @ref LL_RCC_PLLSAIM_DIV_56 + * @arg @ref LL_RCC_PLLSAIM_DIV_57 + * @arg @ref LL_RCC_PLLSAIM_DIV_58 + * @arg @ref LL_RCC_PLLSAIM_DIV_59 + * @arg @ref LL_RCC_PLLSAIM_DIV_60 + * @arg @ref LL_RCC_PLLSAIM_DIV_61 + * @arg @ref LL_RCC_PLLSAIM_DIV_62 + * @arg @ref LL_RCC_PLLSAIM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) +{ +#if defined(RCC_PLLSAICFGR_PLLSAIM) + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); +#else + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +} + +/** + * @brief Get SAIPLL multiplication factor for VCO + * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN + * @retval Between 49/50(*) and 432 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIQ + * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** + * @brief Get SAIPLL division factor for PLLSAIR + * @note used for PLLSAICLK (SAI clock) + * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_PLLSAICFGR_PLLSAIP) +/** + * @brief Get SAIPLL division factor for PLLSAIP + * @note used for PLL48MCLK (48M domain clock) + * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIP */ + +/** + * @brief Get SAIPLL division factor for PLLSAIDIVQ + * @note used PLLSAICLK selected (SAI clock) + * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); +} + +#if defined(RCC_DCKCFGR_PLLSAIDIVR) +/** + * @brief Get SAIPLL division factor for PLLSAIDIVR + * @note used for LTDC domain clock + * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); +} +#endif /* RCC_DCKCFGR_PLLSAIDIVR */ + +/** + * @} + */ +#endif /* RCC_PLLSAI_SUPPORT */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Clear PLLSAI ready interrupt flag + * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Check if PLLSAI ready interrupt occurred or not + * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +#if defined(RCC_CSR_BORRSTF) +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); +} +#endif /* RCC_CSR_BORRSTF */ + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Disable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); +} +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(FMPI2C1) +uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); +#endif /* FMPI2C1 */ +#if defined(LPTIM1) +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#endif /* LPTIM1 */ +#if defined(SAI1) +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +#endif /* SAI1 */ +#if defined(SDIO) +uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); +#endif /* SDIO */ +#if defined(RNG) +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#endif /* RNG */ +#if defined(USB_OTG_FS) || defined(USB_OTG_HS) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB_OTG_HS */ +#if defined(DFSDM1_Channel0) +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM1_Channel0 */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(SPDIFRX) +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +#endif /* SPDIFRX */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_RCC_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h new file mode 100644 index 0000000..164cbb9 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h @@ -0,0 +1,2042 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_SPI_H +#define STM32F4xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set serial protocol used + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR1 DFF LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR1 DFF LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); +} + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) +ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct); +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_SPI_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h new file mode 100644 index 0000000..84ea5c4 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h @@ -0,0 +1,1711 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + *Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_SYSTEM_H +#define __STM32F4xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#if defined(FSMC_Bank1) +#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#endif /* FSMC_Bank1 */ +#if defined(FMC_Bank1) +#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */ +#endif /* FMC_Bank1 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ + +/** + * @} + */ + +#if defined(SYSCFG_PMC_MII_RMII_SEL) + /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC +* @{ +*/ +#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000 /*!< ETH Media MII interface */ +#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ + +/** + * @} + */ +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + + +#if defined(SYSCFG_MEMRMP_UFB_MODE) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) + and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) + and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ +/** + * @} + */ +#endif /* SYSCFG_MEMRMP_UFB_MODE */ +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#if defined(SYSCFG_CFGR_FMPI2C1_SCL) +#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/ +#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI (uint32_t)8 /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9 /*!< EXTI PORT J */ +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_SYSCFG_EXTI_PORTK (uint32_t)10 /*!< EXTI PORT k */ +#endif /* GPIOK */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 + with Break Input of TIM1/8 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#endif /* SYSCFG_CFGR2_CLL */ +/** + * @} + */ + +#if defined(SYSCFG_MCHDLYCR_BSCKSEL) +/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL + * @{ + */ +#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000 +#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN + * @{ + */ +#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN +#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source SYSCFG MCHDLY DFSDMD0SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL +#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL + +#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL) +#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL) +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL +#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL + +#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL) +#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000) +#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL) +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG + * @{ + */ +#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL + * @{ + */ +#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL +/** + * @} + */ + +/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG + * @{ + */ +#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG +/** + * @} + */ +/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL + * @{ + */ +#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000 +#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL +/** + * @} + */ +#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP) +#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP /*!< LPTIM counter stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */ +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FSMC (*) + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @arg @ref LL_SYSCFG_REMAP_FSMC (*) + * @arg @ref LL_SYSCFG_REMAP_FMC (*) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)); +} + +#if defined(SYSCFG_MEMRMP_SWP_FMC) +/** + * @brief Enables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping + * @note SDRAM is accessible at 0x60000000 and NOR/RAM + * is accessible at 0xC0000000 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); +} + +#endif /* SYSCFG_MEMRMP_SWP_FMC */ +/** + * @brief Enables the Compensation cell Power Down + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Disables the Compensation cell Power Down + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); +} + +#if defined(SYSCFG_PMC_MII_RMII_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); +} +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + + +#if defined(SYSCFG_MEMRMP_UFB_MODE) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP UFB_MODE LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE)); +} +#endif /* SYSCFG_MEMRMP_UFB_MODE */ + +#if defined(SYSCFG_CFGR_FMPI2C1_SCL) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR FMPI2C1_SCL LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR FMPI2C1_SDA LL_SYSCFG_DisableFastModePlus\n + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus); +} +#endif /* SYSCFG_CFGR_FMPI2C1_SCL */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF (*) + * @arg @ref LL_SYSCFG_EXTI_PORTG (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); +} + +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +/** + * @brief Set connections to TIM1/8 break inputs + * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n + * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break); +} + +/** + * @brief Get connections to TIM1/8 Break inputs + * @rmtoll SYSCFG_CFGR2 LockUp Lock LL_SYSCFG_SetTIMBreakInputs \n + * SYSCFG_CFGR2 PVD Lock LL_SYSCFG_SetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)); +} +#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ +#if defined(SYSCFG_MCHDLYCR_BSCKSEL) +/** + * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. + * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource); +} +/** + * @brief Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. + * @rmtoll SYSCFG_MCHDLYCR BSCKSEL LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 + * @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL)); +} +/** + * @brief Enables the DFSDM1 or DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock + * @param MCHDLY This parameter can be one of the following values + * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN + * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY) +{ + SET_BIT(SYSCFG->MCHDLYCR, MCHDLY); +} + +/** + * @brief Disables the DFSDM1 or the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock + * @param MCHDLY This parameter can be one of the following values + * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN + * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY) +{ + CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY); +} + +/** + * @brief Select the source for DFSDM1 or DFSDM2 DatIn0 + * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); +} +/** + * @brief Get the source for DFSDM1 or DFSDM2 DatIn0. + * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_GetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0 + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); +} +/** + * @brief Select the source for DFSDM1 or DFSDM2 DatIn2 + * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); +} +/** + * @brief Get the source for DFSDM1 or DFSDM2 DatIn2. + * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_GetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2 + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM4 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM4 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM4 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM4 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL)); +} + +/** + * @brief Select the DFSDM1 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource); +} +/** + * @brief GET the DFSDM1 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_GetClockInSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG)); +} + +/** + * @brief Select the DFSDM1 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource); +} +/** + * @brief GET the DFSDM1 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_GetClockOutSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT + * @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL)); +} + +/** + * @brief Enables the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_EnableDelayClock + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void) +{ + SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); +} + +/** + * @brief Disables the DFSDM2 Delay clock + * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN LL_SYSCFG_DFSDM2_DisableDelayClock + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void) +{ + CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); +} +/** + * @brief Select the source for DFSDM2 DatIn0 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn0. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_GetDataIn0Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn2. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_GetDataIn2Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn4. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_GetDataIn4Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL)); +} + +/** + * @brief Select the source for DFSDM2 DatIn6 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source); +} +/** + * @brief Get the source for DFSDM2 DatIn6. + * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_GetDataIn6Source + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD + * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC3 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC2 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL)); +} + +/** + * @brief Select the distribution of the bitsream lock gated by TIM3 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source); +} +/** + * @brief Get the distribution of the bitsream lock gated by TIM3 OC1 + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 + * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL)); +} + +/** + * @brief Select the DFSDM2 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource); +} +/** + * @brief GET the DFSDM2 Clock In + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_GetClockInSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD + * @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG)); +} + +/** + * @brief Select the DFSDM2 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource) +{ + MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource); +} +/** + * @brief GET the DFSDM2 Clock Out + * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_GetClockOutSourceSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT + * @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27 + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL)); +} + +#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413 + * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419 + * @note For STM32F401xx devices, the device ID is 0x423 + * @note For STM32F401xx devices, the device ID is 0x433 + * @note For STM32F411xx devices, the device ID is 0x431 + * @note For STM32F410xx devices, the device ID is 0x458 + * @note For STM32F412xx devices, the device ID is 0x441 + * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463 + * @note For STM32F446xx devices, the device ID is 0x421 + * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices + For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices + For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices + For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices + For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + +/** + * @brief Enable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Disable Instruction cache + * @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN); +} + +/** + * @brief Enable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCache(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Disable Data cache + * @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCache(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN); +} + +/** + * @brief Enable Instruction cache reset + * @note bit can be written only when the instruction cache is disabled + * @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Disable Instruction cache reset + * @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); +} + +/** + * @brief Enable Data cache reset + * @note bit can be written only when the data cache is disabled + * @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + +/** + * @brief Disable Data cache reset + * @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_SYSTEM_H */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h new file mode 100644 index 0000000..a11f561 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h @@ -0,0 +1,4096 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_TIM_H +#define __STM32F4xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U /* 6: TIMx_CH4 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U /* 6: OC4M, OC4FE, OC4PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U /* 6: CC4S, IC4PSC, IC4F */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U /* 6: CC4P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U /* 6: OIS4 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + +/* Remap mask definitions */ +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) +#define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) +#define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + * @{ + */ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + * @{ + */ +#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS1N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS1N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM1_OR ITR2_RMP LL_TIM_SetRemap\n + * TIM2_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR TI4_RMP LL_TIM_SetRemap\n + * TIM9_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM11_OR TI1_RMP LL_TIM_SetRemap\n + * LPTIM1_OR OR LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of OR registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM1: one of the following values + * + * ITR2_RMP can be one of the following values + * @arg @ref LL_TIM_TIM1_ITR2_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM1_ITR2_RMP_LPTIM (*) + * + * TIM2: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF + * + * TIM5: one of the following values + * + * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE + * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC + * @arg @ref LL_TIM_TIM5_ITR1_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM5_ITR1_RMP_LPTIM (*) + * + * TIM9: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM9_ITR1_RMP_TIM3_TRGO (*) + * @arg @ref LL_TIM_TIM9_ITR1_RMP_LPTIM (*) + * + * TIM11: one of the following values + * + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 (*) + * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2 + * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX (*) + * + * (*) Value not defined in all devices. \n + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) + if ((Remap & LL_TIM_LPTIM_REMAP_MASK) == LL_TIM_LPTIM_REMAP_MASK) + { + /* Connect TIMx internal trigger to LPTIM1 output */ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN); + MODIFY_REG(LPTIM1->OR, + (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), + Remap & ~(LL_TIM_LPTIM_REMAP_MASK)); + } + else + { + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); + } +#else + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */ +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_TIM_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h new file mode 100644 index 0000000..ed83b6c --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -0,0 +1,2521 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_USART_H +#define __STM32F4xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ +#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ +#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ +#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ +#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ +#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ +#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */ +#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported Macros Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__))))) +#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\ + + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__))))) +#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\ + + 50) / 100) +/* USART BRR = mantissa + overflow + fraction + = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_SR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @rmtoll CR2 ADD LL_USART_SetNodeAddress + * @param USARTx USART Instance + * @param NodeAddress 4 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); +} + +/** + * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. + * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + uint32_t usartdiv = 0x0U; + uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll SR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll SR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll SR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll SR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); +} + +/** + * @brief Clear Parity Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * NE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR PE LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Framing Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, ORE, IDLE would also be cleared. + * @rmtoll SR FE LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Noise detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR NF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear OverRun Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, IDLE would also be cleared. + * @rmtoll SR ORE LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear IDLE line detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, ORE would also be cleared. + * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll SR TC LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_TC)); +} + +/** + * @brief Clear RX Not Empty Flag + * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_LBD)); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_USART_DMA_GetRegAddr + * @note Address of Data Register is valid for both Transmit and Receive transfers. + * @param USARTx USART Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) +{ + /* return address of DR register */ + return ((uint32_t) &(USARTx->DR)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll DR DR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll DR DR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll DR DR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->DR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll DR DR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->DR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll CR1 SBK LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_SBK); +} + +/** + * @brief Put USART in Mute mode + * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @brief Put USART in Active mode + * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_USART_H */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h new file mode 100644 index 0000000..accdac7 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h @@ -0,0 +1,307 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_UTILS_H +#define __STM32F4xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE + and Max_Data = @ref RCC_PLLN_MIN_VALUE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U /*!< LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_UTILS_H */ diff --git a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c new file mode 100644 index 0000000..862ec73 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -0,0 +1,616 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F4xx HAL Driver version number V1.8.5 + */ +#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32F4xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK 0x00000FFFU + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET +#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos +#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) + +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) +#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos +#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) + +/* --- MCHDLYCR Register ---*/ +/* Alias word address of BSCKSEL bit */ +#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) +#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos +#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Private_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, instruction and Data caches. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F4xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Enables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_EnableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Internal FLASH Bank Swapping. + * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * + * @retval None + */ +void HAL_DisableMemorySwappingBank(void) +{ + *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c new file mode 100644 index 0000000..fa95eb5 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -0,0 +1,2466 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be triggered by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callback is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) + { + /* CAN3 is single instance with 14 dedicated filters banks */ + can_ip = hcan->Instance; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + } + else + { + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + } +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + can_ip = hcan->Instance; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif /* CAN3 */ + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) + { + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + } + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif /* CAN3 */ + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c new file mode 100644 index 0000000..c3d2ba8 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -0,0 +1,538 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f4xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enables the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disables the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Clear pending events. + * @retval None + */ +void HAL_CORTEX_ClearEvent(void) +{ + __SEV(); + __WFE(); +} + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c new file mode 100644 index 0000000..3dbb477 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -0,0 +1,1305 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT 5U /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = 0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c new file mode 100644 index 0000000..7167e77 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -0,0 +1,313 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Check callback functions */ + if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c new file mode 100644 index 0000000..3e46312 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -0,0 +1,553 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Edge); + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c new file mode 100644 index 0000000..808949e --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -0,0 +1,776 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F4xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash = {.ProcedureOnGoing = FLASH_PROC_NONE, + .NbSectorsToErase = 0U, + .VoltageForErase= FLASH_VOLTAGE_RANGE_1, + .Sector = 0U, + .Bank = FLASH_BANK_1, + .Address = 0U, + .Lock = HAL_UNLOCKED, + .ErrorCode = HAL_FLASH_ERROR_NONE}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + if (TypeProgram == FLASH_TYPEPROGRAM_BYTE) + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + } + else if (TypeProgram == FLASH_TYPEPROGRAM_WORD) + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + } + else + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t addresstmp = 0U; + + /* Check FLASH operation error flags */ +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*return the faulty sector*/ + addresstmp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /*return the faulty bank*/ + addresstmp = pFlash.Bank; + } + else + { + /*return the faulty address*/ + addresstmp = pFlash.Address; + } + + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(addresstmp); + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + if (pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if (pFlash.NbSectorsToErase != 0U) + { + addresstmp = pFlash.Sector; + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(addresstmp); + + /*Increment sector number*/ + pFlash.Sector++; + addresstmp = pFlash.Sector; + FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); + } + else + { + /*No more sectors to Erase, user callback can be called.*/ + /*Reset Sector and stop Erase sectors procedure*/ + pFlash.Sector = addresstmp = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(addresstmp); + } + } + else + { + if (pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + { + /* MassErase ended. Return the selected bank */ + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Bank); + } + else + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + + if (pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Operation is completed, disable the PG, SER, SNB and MER Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); + + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be a combination of: + * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) + * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag + * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) +#else + if (__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) +#endif /* FLASH_SR_RDERR */ + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and Vpp in the range 7V to 9V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program first word */ + *(__IO uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(__IO uint32_t *)(Address + 4) = (uint32_t)(Data >> 32); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t *)Address = Data; +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t *)Address = Data; +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 1.8V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t *)Address = Data; +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + + /* Clear FLASH write protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + + /* Clear FLASH Programming alignment error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + + /* Clear FLASH Programming parallelism error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); + } + + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; + + /* Clear FLASH Programming sequence error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); + } +#if defined(FLASH_SR_RDERR) + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + + /* Clear FLASH Proprietary readout protection error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); + } +#endif /* FLASH_SR_RDERR */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + + /* Clear FLASH Operation error pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c new file mode 100644 index 0000000..839c91b --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -0,0 +1,1344 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and + STM32F429xx/439xx devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx + devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : + (++) Extended space (bank 2) erase function + (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) + (++) Dual Boot activation + (++) Write protection configuration for bank 2 + (++) PCROP protection configuration and control for both banks + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static uint8_t FLASH_OB_GetUser(void); +static uint16_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetBOR(void); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\ + defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFFU means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status; + uint32_t index = 0U; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + /* Flush the caches to be sure of the data consistency */ + FLASH_FlushCaches(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + pFlash.Bank = pEraseInit->Banks; + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /*Write protection configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /*Read protection configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /*USER configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST); + } + + /*BOR Level configuration*/ + if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /*Get WRP*/ + pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR(); +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Program option bytes + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_OBEX(pAdvOBInit->OptionType)); + + /*Program PCROP option byte*/ + if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + /* Check the parameters */ + assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); + if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + else + { + /*Disable of Write protection on the selected Sector*/ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks); +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + } + } + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /*Program BOOT config option byte*/ + if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + { + status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + } +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + return status; +} + +/** + * @brief Get the OBEX byte configuration + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +{ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + /*Get Sector*/ + pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ + /*Get Sector for Bank1*/ + pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); + + /*Get Sector for Bank2*/ + pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); + + /*Get Boot config OB*/ + pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS; +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ +} + +/** + * @brief Select the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + uint8_t optiontmp; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); + + return HAL_OK; +} + +/** + * @brief Deselect the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ + * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + uint8_t optiontmp; + + /* Mask SPRMOD bit */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + + /* Update Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); + + return HAL_OK; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ + STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. + * @retval The FLASH Write Protection Option Bytes value + */ +uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/** + * @} + */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + + if (Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if (Banks == FLASH_BANK_1) + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + else + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if (Sector > FLASH_SECTOR_11) + { + Sector += 4U; + } + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_SECTOR_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + + /*Write protection on all sector of BANK2*/ + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + } + + } + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 + * @arg OB_WRP_Sector_All + * @note BANK2 starts from OB_WRP_SECTOR_12 + * + * @param Banks Disable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) + { + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + } + else + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + + /*Write protection on all sector of BANK2*/ + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + } + + } + + return status; +} + +/** + * @brief Configure the Dual Bank Boot. + * + * @note This function can be used only for STM32F42xxx/43xxx devices. + * + * @param BootConfig specifies the Dual Bank Boot Option byte. + * This parameter can be one of the following values: + * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable + * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled + * @retval None + */ +static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT(BootConfig)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set Dual Bank Boot */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig; + } + + return status; +} + +/** + * @brief Enable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Enable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; + } + else + { + assert_param(IS_OB_PCROP(SectorBank2)); + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + + /*Write protection on all sector of BANK2*/ + if (Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + } + } + + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired + * sectors of Bank 1 and/or Bank 2. + * @note This function can be used only for STM32F42xxx/43xxx devices. + * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 + * @arg OB_PCROP_SECTOR__All + * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 + * @arg OB_PCROP_SECTOR__All + * @param Banks Disable PCROP protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * @arg FLASH_BANK_2: WRP on all sectors of bank2 + * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + { + assert_param(IS_OB_PCROP(SectorBank1)); + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); + } + else + { + /*Write protection done on sectors of BANK2*/ + assert_param(IS_OB_PCROP(SectorBank2)); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + + /*Write protection on all sector of BANK2*/ + if (Banks == FLASH_BANK_BOTH) + { + assert_param(IS_OB_PCROP(SectorBank2)); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /*Write protection done on sectors of BANK2*/ + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + } + } + + } + + return status; + +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ + defined(STM32F423xx) +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * + * @retval None + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* If the previous operation is completed, proceed to erase all sectors */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0U; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; +} + +/** + * @brief Enable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank 1 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * + * @param WRPSector specifies the sector(s) to be write protected. + * The value of this parameter depend on device used within the same series + * + * @param Banks Enable write protection on all the sectors for the specific bank + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: WRP on all sectors of bank1 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } + + return status; +} +#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; + } + + return status; +} + + +/** + * @brief Disable the read/write protection (PCROP) of the desired sectors. + * @note This function can be used only for STM32F401xx devices. + * @param Sector specifies the sector(s) to be read/write protected or unprotected. + * This parameter can be one of the following values: + * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 + * @arg OB_PCROP_Sector_All + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP(Sector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector); + } + + return status; + +} +#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx + STM32F413xx || STM32F423xx */ + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Iwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby) +{ + uint8_t optiontmp; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); + + /* Update User Option Byte */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; + + return HAL_OK; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +static uint8_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint8_t)(FLASH->OPTCR & 0xE0)); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint16_t FLASH Write Protection Option Bytes value + */ +static uint16_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) + { + readstatus = OB_RDP_LEVEL_2; + } + else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) + { + readstatus = OB_RDP_LEVEL_0; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint8_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint8_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); +} + +/** + * @brief Flush the instruction and data caches + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + + /* Flush data cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + /* Disable data cache */ + __HAL_FLASH_DATA_CACHE_DISABLE(); + /* Reset data cache */ + __HAL_FLASH_DATA_CACHE_RESET(); + /* Enable data cache */ + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c new file mode 100644 index 0000000..e6ab3ac --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -0,0 +1,172 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_flash_ramfunc.c + * @author MCD Application Team + * @brief FLASH RAMFUNC module driver. + * This file provides a FLASH firmware functions which should be + * executed from internal SRAM + * + Stop/Start the flash interface while System Run + * + Enable/Disable the flash sleep while System Run + @verbatim + ============================================================================== + ##### APIs executed from Internal RAM ##### + ============================================================================== + [..] + *** ARM Compiler *** + -------------------- + [..] RAM functions are defined using the toolchain options. + Functions that are be executed in RAM should reside in a separate + source module. Using the 'Options for File' dialog you can simply change + the 'Code / Const' area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the + Options for Target' dialog. + + *** ICCARM Compiler *** + ----------------------- + [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". + + *** GNU Compiler *** + -------------------- + [..] RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC + * @brief FLASH functions executed from RAM + * @{ + */ +#ifdef HAL_FLASH_MODULE_ENABLED +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ + defined(STM32F412Rx) || defined(STM32F412Cx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions + * @{ + */ + +/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### ramfunc functions ##### + =============================================================================== + [..] + This subsection provides a set of functions that should be executed from RAM + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Stop the flash interface while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Stop the flash interface while System Run */ + SET_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Start the flash interface while System Run + * @note This mode is only available for STM32F411xx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Start the flash interface while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FISSR); + + return HAL_OK; +} + +/** + * @brief Enable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode could n't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the flash sleep while System Run */ + SET_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @brief Disable the flash sleep while System Run + * @note This mode is only available for STM32F41xxx/STM32F446xx devices. + * @note This mode couldn't be set while executing with the flash itself. + * It should be done with specific routine executed from RAM. + * @retval HAL status + */ +__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) +{ + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Disable the flash sleep while System Run */ + CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +#endif /* HAL_FLASH_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c new file mode 100644 index 0000000..b3ce9bb --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#define GPIO_NUMBER 16U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ + (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the parameters */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FU << (4U * (position & 0x03U))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for(position = 0U; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = 0x01U << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if(iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FU << (4U * (position & 0x03U))); + if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR &= ~((uint32_t)iocurrent); + EXTI->RTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = 0x0FU << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if(PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. + * @param GPIO_Pin Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKR register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c new file mode 100644 index 0000000..d3f4262 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -0,0 +1,7567 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State, Mode and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, + Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XferOptions_definition and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition, an then permit a call the same master sequential interface + several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential + interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) + or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() + or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() + or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() + or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() + or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macros + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); + +/* Private functions for I2C transfer IRQ handler */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); + +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); + +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + +/* Private function to flush DR register */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Communication Speed + (++) Duty cycle + (++) Addressing mode + (++) Own Address 1 + (++) Dual Addressing mode + (++) Own Address 2 + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + uint32_t freqrange; + uint32_t pclk1; + + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*Reset I2C*/ + hi2c->Instance->CR1 |= I2C_CR1_SWRST; + hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; + + /* Get PCLK1 frequency */ + pclk1 = HAL_RCC_GetPCLK1Freq(); + + /* Check the minimum allowed PCLK1 frequency */ + if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) + { + return HAL_ERROR; + } + + /* Calculate frequency range */ + freqrange = I2C_FREQRANGE(pclk1); + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Frequency range */ + MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); + + /*---------------------------- I2Cx TRISE Configuration --------------------*/ + /* Configure I2Cx: Rise Time */ + MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); + + /*---------------------------- I2Cx CCR Configuration ----------------------*/ + /* Configure I2Cx: Speed */ + MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Configure I2Cx: Own Address1 and addressing mode */ + MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Configure I2Cx: Dual mode and Own Address2 */ + MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @brief I2C data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) +{ + /* Write a dummy data in DR to clear TXE flag */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) + { + hi2c->Instance->DR = 0x00U; + } +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address */ + if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + hi2c->XferSize--; + } + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == (uint16_t)0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + while (hi2c->XferSize > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + while (hi2c->XferSize > 0U) + { + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* Wait until BTF flag is set */ + if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferSize == 2U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + while (hi2c->XferSize > 0U) + { + if (hi2c->XferSize <= 3U) + { + /* One byte */ + if (hi2c->XferSize == 1U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* Two bytes */ + else if (hi2c->XferSize == 2U) + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + /* 3 Last bytes */ + else + { + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Wait until BTF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferSize--; + hi2c->XferCount--; + } + } + } + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + if (hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferM1CpltCallback = NULL; + hi2c->hdmatx->XferM1HalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Set the unused I2C DMA transfer complete callback to NULL */ + hi2c->hdmatx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Init tickstart for timeout management*/ + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t count = 0U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferM1CpltCallback = NULL; + hi2c->hdmarx->XferM1HalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Abort the ongoing DMA */ + dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); + + /* Prevent unused argument(s) compilation and MISRA warning */ + UNUSED(dmaxferstatus); + + /* Set the unused I2C DMA transfer complete callback to NULL */ + hi2c->hdmarx->XferCpltCallback = NULL; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferSize = 0U; + hi2c->XferCount = 0U; + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + return HAL_ERROR; + } + + if (hi2c->XferSize == 1U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + /* Get tick */ + uint32_t tickstart = HAL_GetTick(); + uint32_t I2C_Trials = 0U; + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + do + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR or AF flag are set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->State = HAL_I2C_STATE_TIMEOUT; + } + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if the ADDR flag has been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear ADDR Flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Increment Trials */ + I2C_Trials++; + } + while (I2C_Trials < Trials); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ + enableIT &= ~I2C_IT_BUF; + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0U; + uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Check Busy Flag only if FIRST call of Master interface */ + if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_BUSY; + } + } + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Clear Last DMA bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->Devaddress = DevAddress; + + Prev_State = hi2c->PreviousState; + + if (hi2c->XferSize > 0U) + { + if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) + { + if (Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + } + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + if (dmaxferstatus == HAL_OK) + { + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Update interrupt for only EVT and ERR */ + enableIT = (I2C_IT_EVT | I2C_IT_ERR); + } + else + { + /* Update interrupt for only ERR */ + enableIT = I2C_IT_ERR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ + /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ + if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable interrupts */ + __HAL_I2C_ENABLE_IT(hi2c, enableIT); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + + /* Abort Master transfer during Receive or Transmit process */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || + (CurrentMode == HAL_I2C_MODE_MEM))) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + /* Or periphal is not in busy state, mean there is no active sequence to be abort */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t sr1itflags; + uint32_t sr2itflags = 0U; + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t CurrentXferOptions = hi2c->XferOptions; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Master or Memory mode selected */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + + /* Exit IRQ event until Start Bit detected in case of Other frame requested */ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) + { + return; + } + + /* SB Set ----------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + I2C_MasterTransmit_BTF(hi2c); + } + else /* HAL_I2C_MODE_MEM */ + { + if (CurrentMode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + } + } + else + { + /* Do nothing */ + } + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* Do not check buffer and BTF flag if a Xfer DMA is on going */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) + { + /* RXNE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_MasterReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_MasterReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } + } + /* Slave mode selected */ + else + { + /* If an error is detected, read only SR1 register to prevent */ + /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + else + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + sr1itflags = READ_REG(hi2c->Instance->SR1); + } + + /* ADDR set --------------------------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + /* Now time to read SR2, this will clear ADDR flag automatically */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + sr2itflags = READ_REG(hi2c->Instance->SR2); + } + I2C_Slave_ADDR(hi2c, sr2itflags); + } + /* STOPF set --------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_Slave_STOPF(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* TXE set and BTF reset -----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveTransmit_TXE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveTransmit_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + /* I2C in mode Receiver --------------------------------------------------*/ + else + { + /* RXNE set and BTF reset ----------------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) + { + I2C_SlaveReceive_RXNE(hi2c); + } + /* BTF set -------------------------------------------------------------*/ + else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) + { + I2C_SlaveReceive_BTF(hi2c); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + HAL_I2C_ModeTypeDef tmp1; + uint32_t tmp2; + HAL_I2C_StateTypeDef tmp3; + uint32_t tmp4; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + uint32_t error = HAL_I2C_ERROR_NONE; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + + /* I2C Bus error interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* I2C Acknowledge failure error interrupt occurred ------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + tmp1 = CurrentMode; + tmp2 = hi2c->XferCount; + tmp3 = hi2c->State; + tmp4 = hi2c->PreviousState; + if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) + { + I2C_Slave_AF(hi2c); + } + else + { + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + error |= HAL_I2C_ERROR_AF; + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + } + + /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ + if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) + { + error |= HAL_I2C_ERROR_OVR; + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* Call the Error Callback in case of Error detected -----------------------*/ + if (error != HAL_I2C_ERROR_NONE) + { + hi2c->ErrorCode |= error; + I2C_ITError(hi2c); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Handle TXE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) + { + if (hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle BTF flag for Master transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief Handle TXE and BTF flag for Memory transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->EventCount == 0U) + { + /* If Memory address size is 8Bit */ + if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2U; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if (hi2c->EventCount == 1U) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if (hi2c->EventCount == 2U) + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; + } + else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) + { + /* Generate Stop condition then Call TxCpltCallback() */ + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + } + else + { + /* Clear TXE and BTF flags */ + I2C_Flush_DR(hi2c); + } +} + +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp; + uint32_t CurrentXferOptions; + + CurrentXferOptions = hi2c->XferOptions; + tmp = hi2c->XferCount; + if (tmp > 3U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if (hi2c->XferCount == (uint16_t)3) + { + /* Disable BUF interrupt, this help to treat correctly the last 4 bytes + on BTF subroutine */ + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } + else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) + { + if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + } +} + +/** + * @brief Handle BTF flag for Master receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (hi2c->XferCount == 4U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 3U) + { + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + else if (hi2c->XferCount == 2U) + { + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle SB flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + if (hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } + } + else + { + if (hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if (hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + else + { + /* Do nothing */ + } + } + } +} + +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); + + if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) + || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) + { + /* Enable DMA Request */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + } +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + hi2c->EventCount++; + } + else + { + if (hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + else if (hi2c->XferCount == 1U) + { + if (CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + /* Prepare next transfer or stop current transfer */ + else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + } + else if (hi2c->XferCount == 2U) + { + if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Enable Pos */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) + { + /* Enable Last DMA bit */ + SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; + } + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } +} + +/** + * @brief Handle TXE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave transmitter + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle RXNE flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + + if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Handle BTF flag for Slave receiver + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->XferCount != 0U) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } +} + +/** + * @brief Handle ADD flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param IT2Flags Interrupt2 flags to handle. + * @retval None + */ +static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) +{ + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ + __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); + + /* Transfer Direction requested by Master */ + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#else + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief Handle STOPF flag for Slave + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear STOPF flag */ + __HAL_I2C_CLEAR_STOPFLAG(hi2c); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* If a DMA is ongoing, Update handle size context */ + if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else + { + hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Disable, stop the current DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Abort DMA Xfer if any */ + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + /* Update counter */ + hi2c->XferCount--; + } + + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval None + */ +static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Clear TXE flag */ + I2C_Flush_DR(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } +} + +/** + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentError; + + if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + } + + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + hi2c->PreviousState = I2C_STATE_NONE; + } + + /* Abort DMA transfer */ + if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + } + + /* Call user error callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ + CurrentError = hi2c->ErrorCode; + + if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ + ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ + ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ + ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + CurrentState = hi2c->State; + if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start condition if first transfer */ + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + } + else + { + /* Do nothing */ + } + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + } + else + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); + + /* Wait until ADD10 flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +{ + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TXE flag is set */ + if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + return HAL_ERROR; + } + + /* Generate Restart */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + + /* Wait until SB flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) + { + if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) + { + hi2c->ErrorCode = HAL_I2C_WRONG_START; + } + return HAL_TIMEOUT; + } + + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief DMA I2C process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) + { + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Do nothing */ + } + + /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + } + /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ + else if (hi2c->Mode != HAL_I2C_MODE_NONE) + { + if (hi2c->XferCount == (uint16_t)1) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Prepare next transfer or stop current transfer */ + if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + } + + /* Disable Last DMA */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + + /* Disable DMA Request */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + hi2c->XferCount = 0U; + + /* Check if Errors has been detected during transfer */ + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->PreviousState = I2C_STATE_NONE; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) + { + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Do nothing */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Ignore DMA FIFO error */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + __IO uint32_t count = 0U; + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + HAL_I2C_StateTypeDef CurrentState = hi2c->State; + + /* During abort treatment, check that there is no pending STOP request */ + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + break; + } + count--; + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + /* Clear Complete callback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferCpltCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferCpltCallback = NULL; + } + + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + hi2c->XferCount = 0U; + + /* Reset XferAbortCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Check if come from abort from user */ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Renable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for Master addressing phase. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + + /* Clear AF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) +{ + __IO uint32_t count = 0U; + + /* Wait until STOP flag is reset */ + count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); + do + { + count--; + if (count == 0U) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); + + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c new file mode 100644 index 0000000..64aabaa --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extension HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C extension peripheral: + * + Extension features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ + 429xx/439xx devices contains the following additional features : + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter + (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() + (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Functions I2C Exported Functions + * @{ + */ + + +/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions + * @brief Extension features functions + * +@verbatim + =============================================================================== + ##### Extension features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures I2C Analog noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter new state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); + + /* Disable the analog filter */ + hi2c->Instance->FLTR |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures I2C Digital noise filter. + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->FLTR; + + /* Reset I2Cx DNF bit [3:0] */ + tmpreg &= ~(I2C_FLTR_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter; + + /* Store the new register value */ + hi2c->Instance->FLTR = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c new file mode 100644 index 0000000..5ccde64 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -0,0 +1,598 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @note The following sequence is required to bypass the delay between + * DBP bit programming and the effective enabling of the backup domain. + * Please check the Errata Sheet for more details under "Possible delay + * in backup domain protection disabling/enabling after programming the + * DBP bit" section. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + __IO uint32_t dummyread; + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; + dummyread = PWR->CR; + UNUSED(dummyread); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @note The following sequence is required to bypass the delay between + * DBP bit programming and the effective disabling of the backup domain. + * Please check the Errata Sheet for more details under "Possible delay + * in backup domain protection disabling/enabling after programming the + * DBP bit" section. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + __IO uint32_t dummyread; + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; + dummyread = PWR->CR; + UNUSED(dummyread); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. + (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and + no clear of pending event before. + + -@@- The Regulator parameter is not used for the STM32F4 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) + function with: + (++) Regulator: + (+++) Main regulator ON. + (+++) Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and + clear of pending events before. + (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + no clear of pending event before. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, + tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wake-up (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wake-up event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wake-up mode). + + (+) RTC auto-wake-up (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to + configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Enable the wake up pin */ + SET_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Disables the Wake-up PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + /* Disable the wake up pin */ + CLEAR_BIT(PWR->CSR, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F4 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and + * clear of pending events before. + * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and + * no clear of pending event before. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + + /* Request Wait For Event */ + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and + * clear of pending events before. + * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and + * no clear of pending event before. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) + { + /* Clear all pending event */ + __SEV(); + __WFE(); + } + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + SET_BIT(PWR->CR, PWR_CR_PDDS); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c new file mode 100644 index 0000000..77f9c35 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -0,0 +1,600 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U +#define PWR_BKPREG_TIMEOUT_VALUE 1000U +#define PWR_VOSRDY_TIMEOUT_VALUE 1000U +/** + * @} + */ + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. + The new value programmed is active only when the PLL is ON. + When the PLL is OFF, the voltage scale 3 is automatically selected. + Refer to the datasheets for more details. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has + 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0U; + + *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Return Voltage Scaling Range. + * @retval The configured scale for the regulator voltage(VOS bit field). + * The returned value can be one of the following: + * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR & PWR_CR_VOS); +} + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK = 168 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK = 144 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ + defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ + defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * the maximum value of fHCLK is 168 MHz. It can be extended to + * 180 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * the maximum value of fHCLK is 144 MHz. It can be extended to, + * 168 MHz by activating the over-drive mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, + * the maximum value of fHCLK is 120 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0U; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Enable PWR RCC Clock Peripheral */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Enables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xxdevices. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ + * STM32F413xx/STM32F423xx devices. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; +} + +#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || + STM32F413xx || STM32F423xx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Activates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0U; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg1 = PWR->CR; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tmpreg1 |= Regulator; + + /* Store the new value */ + PWR->CR = tmpreg1; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c new file mode 100644 index 0000000..c18fa09 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -0,0 +1,1124 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; + all peripherals mapped on these busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/* Private macro -------------------------------------------------------------*/ +#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 168 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clocks automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB busses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum + frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, + the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, + PCLK2 84 MHz and PCLK1 42 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, + PCLK2 100 MHz and PCLK1 50 MHz. + Depending on the device voltage range, the maximum frequency should + be adapted accordingly (refer to the product datasheets for more details). + +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* RCC_PLLCFGR_PLLR */ + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have + * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + __MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ +#if defined(RCC_CFGR_MCO1EN) + __HAL_RCC_MCO1_ENABLE(); +#endif /* RCC_CFGR_MCO1EN */ + } +#if defined(RCC_CFGR_MCO2) + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + __MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); + + /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */ +#if defined(RCC_CFGR_MCO2EN) + __HAL_RCC_MCO2_ENABLE(); +#endif /* RCC_CFGR_MCO2EN */ + } +#endif /* RCC_CFGR_MCO2 */ +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +__weak uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U; + uint32_t pllvco = 0U; + uint32_t pllp = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); + + sysclockfreq = pllvco / pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c new file mode 100644 index 0000000..0431718 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -0,0 +1,3833 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ + +#if defined(STM32F446xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t plli2sp = 0U; + uint32_t plli2sq = 0U; + uint32_t plli2sr = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t plli2sused = 0U; + uint32_t pllsaiused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------ I2S APB1 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- I2S APB2 configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*--------------------------- SAI1 configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------- SAI2 configuration ----------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- RTC configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ CEC Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- CLK48 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CLK48 */ + if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) + { + pllsaiused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- SDIO Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SPDIFRX Configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* Check the parameters */ + assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); + + /* Configure the SPDIFRX clock source */ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); + /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ + if (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- PLLI2S Configuration ------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, + I2S on APB2 or SPDIFRX */ + if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) + && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, plli2sq, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sp, + PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, + plli2sq, plli2sr); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SP, + PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------- PLLSAI Configuration -----------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ + if (pllsaiused == 1U) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, + PeriphClkInit->PLLSAI.PLLSAIQ, 0U); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ + /* In Case of PLLI2S is selected as source clock for CLK48 */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, + pllsaiq, 0U); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 | \ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO | \ + RCC_PERIPHCLK_SPDIFRX; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CEC clock configuration -----------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ----------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the SPDIFRX clock configuration -------------------------------------*/ + PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg1 = 0U; + /* This variable used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + /* This variable used to store the SAI clock source */ + uint32_t saiclocksource = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_SAI1: + case RCC_PERIPHCLK_SAI2: + { + saiclocksource = RCC->DCKCFGR; + saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); + switch (saiclocksource) + { + case 0U: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U)) / (tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); + frequency = frequency / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); + frequency = frequency / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ + case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ + { + /* Configure the PLLI2S division factor */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + /* SAI_CLK_x = PLL_VCO Output/PLLR */ + tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; + frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U)) / (tmpreg1); + break; + } + case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + frequency = (uint32_t)(HSI_VALUE); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + frequency = (uint32_t)(HSE_VALUE); + } + break; + } + default : + { + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F446xx */ + +#if defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + uint32_t pllsaip = 0U; + uint32_t pllsaiq = 0U; + uint32_t pllsair = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*--------------------------- CLK48 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------ SDIO Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*------------------- Common configuration SAI/I2S -------------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------- I2S configuration -------------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for these peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + + /*---------------------------- CLK48 configuration ------------------------*/ + /* Configure the PLLSAI when it is used as clock source for CLK48 */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && + (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) + { + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | \ + RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration --------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the CLK48 clock configuration -------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F469xx || STM32F479xx */ + +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; +#if defined(STM32F413xx) || defined(STM32F423xx) + uint32_t plli2sq = 0U; +#endif /* STM32F413xx || STM32F423xx */ + uint32_t plli2sused = 0U; + + /* Check the peripheral clock selection parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S APB1 configuration ---------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------------------- I2S APB2 configuration ---------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); + /* Enable the PLLI2S when it's used as clock source for I2S */ + if (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*----------------------- SAI1 Block A configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------- SAI1 Block B configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) + { + plli2sused = 1U; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) + { + /* Check for PLL/DIVR parameters */ + assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); + } + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + /*------------------------------------ RTC configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------ TIM configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- FMPI2C1 Configuration --------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- CLK48 Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for CLK48 */ + if (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) + { + plli2sused = 1U; + } + } + /*--------------------------------------------------------------------------*/ + + /*------------------------------------- SDIO Configuration -----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); + + /* Configure the SDIO clock source */ + __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------------------------- PLLI2S Configuration --------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or + I2S on APB2*/ + if ((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection)); + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + /*-------------------- Set the PLL I2S clock -----------------------------*/ + __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); + + /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) + && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + if (((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) + && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Check for PLLI2S/DIVR parameters */ + assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, + PeriphClkInit->PLLI2S.PLLI2SR); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); + } +#endif /* STM32F413xx || STM32F423xx */ + + /*----------------- In Case of PLLI2S is just selected ------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM1 Audio clock source configuration -------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + +#if defined(STM32F413xx) || defined(STM32F423xx) + /*-------------------- DFSDM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*-------------------- DFSDM2 Audio clock source configuration -------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection)); + + /* Configure the DFSDM1 Audio interface clock source */ + __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + /*--------------------------------------------------------------------------*/ +#endif /* STM32F413xx || STM32F423xx */ + + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2 | \ + RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1 | \ + RCC_PERIPHCLK_SAIA | RCC_PERIPHCLK_SAIB; +#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 | \ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_CLK48 | \ + RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 | \ + RCC_PERIPHCLK_DFSDM1_AUDIO; +#endif /* STM32F413xx || STM32F423xx */ + + + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the PLL/PLLI2S division factors -------------------------------------*/ + PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); + PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the I2S APB1 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); + + /* Get the I2S APB2 clock configuration ------------------------------------*/ + PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the CLK48 clock configuration ---------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDIO clock configuration ----------------------------------------*/ + PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); + + /* Get the DFSDM1 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM1 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); + +#if defined(STM32F413xx) || defined(STM32F423xx) + /* Get the DFSDM2 clock configuration --------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); + + /* Get the DFSDM2 Audio clock configuration --------------------------------*/ + PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); + + /* Get the LPTIM1 clock configuration --------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the SAI1 Block Aclock configuration ---------------------------------*/ + PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); + + /* Get the SAI1 Block B clock configuration --------------------------------*/ + PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); +#endif /* STM32F413xx || STM32F423xx */ + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(I2S..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock + * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S_APB1: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLI2S: + { + if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB1CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + case RCC_PERIPHCLK_I2S_APB2: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLI2S: + { + if ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + } + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPB2CLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- FMPI2C1 Configuration -----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); + + /* Configure the FMPI2C1 clock source */ + __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- LPTIM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*---------------------------- I2S Configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); + + /* Configure the I2S clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); + } + + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } + /* Get the FMPI2C1 clock configuration -------------------------------------*/ + PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); + + /* Get the I2S clock configuration -----------------------------------------*/ + PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + + +} +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_PLLR: + { + /* Configure the PLL division factor R */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLL_VCO Output = PLL_VCO Input * PLLN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); + /* I2S_CLK = PLL_VCO Output/PLLR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U))); + break; + } + /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */ + case RCC_I2SAPBCLKSOURCE_PLLSRC: + { + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + frequency = HSE_VALUE; + } + else + { + frequency = HSI_VALUE; + } + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC RTC and TIM). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) and RCC_BDCR register are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ + /*----------------------- Common configuration SAI/I2S ---------------------*/ + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- I2S configuration -------------------------*/ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) + { + /* Check the PLLI2S division factors */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Configure the PLLI2S multiplication and division factors */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, + PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ + /*----------------------- Common configuration SAI/LTDC --------------------*/ + /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division + factor is common parameters for both peripherals */ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) + { + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is disabled */ + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) + { + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*---------------------------- LTDC configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLSAI is ready */ + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + /*--------------------------------------------------------------------------*/ + + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + return HAL_OK; +} + +/** + * @brief Configures the PeriphClkInit according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0U; + uint32_t tmpreg1 = 0U; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*---------------------------- I2S configuration ---------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + +#if defined(STM32F411xE) + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, + PeriphClkInit->PLLI2S.PLLI2SR); +#else + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#endif /* STM32F411xE */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait till PLLI2S is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*---------------------------- RTC configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while ((PWR->CR & PWR_CR_DBP) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /*---------------------------- TIM configuration ---------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; + + /* Get the PLLI2S Clock configuration --------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); +#if defined(STM32F411xE) + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); +#endif /* STM32F411xE */ + /* Get the RTC Clock configuration -----------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + /* This variable used to store the I2S clock frequency (value in Hz) */ + uint32_t frequency = 0U; + /* This variable used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0U; + uint32_t srcclk = 0U; + /* This variable used to store the VCO Output (value in Hz) */ + uint32_t vcooutput = 0U; + switch (PeriphClk) + { + case RCC_PERIPHCLK_I2S: + { + /* Get the current I2S source */ + srcclk = __HAL_RCC_GET_I2S_SOURCE(); + switch (srcclk) + { + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: + { + /* Set the I2S clock to the external clock value */ + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */ + case RCC_I2SCLKSOURCE_PLLI2S: + { +#if defined(STM32F411xE) + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); + } +#else + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE) + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* Get the I2S source clock value */ + vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } +#endif /* STM32F411xE */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); + /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ + frequency = (uint32_t)(vcooutput / (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U))); + break; + } + /* Clock not enabled for I2S*/ + default: + { + frequency = 0U; + break; + } + } + break; + } + default: + { + break; + } + } + return frequency; +} +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Select LSE mode + * + * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * + * @param Mode specifies the LSE mode. + * This parameter can be one of the following values: + * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection + * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection + * @retval None + */ +void HAL_RCCEx_SelectLSEMode(uint8_t Mode) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_MODE(Mode)); + if (Mode == RCC_LSE_HIGHDRIVE_MODE) + { + SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } + else + { + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); + } +} + +#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + +#if defined(STM32F446xx) +/** + * @brief Returns the SYSCLK frequency + * + * @note This function implementation is valid only for STM32F446xx devices. + * @note This function add the PLL/PLLR System clock source + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0U; + uint32_t pllvco = 0U; + uint32_t pllp = 0U; + uint32_t pllr = 0U; + uint32_t sysclockfreq = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); + + sysclockfreq = pllvco / pllp; + break; + } + case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); + + sysclockfreq = pllvco / pllr; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} +#endif /* STM32F446xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLSAI_SUPPORT */ + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; +#else + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ + + /* Reset PLLI2SCFGR register to default value */ +#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ + defined(STM32F423xx) || defined(STM32F446xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F411xE) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ + + /* Reset PLLSAICFGR register */ +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; +#elif defined(STM32F446xx) + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; +#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | + RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this API. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this API. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ +#if defined(STM32F446xx) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#else + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) +#endif /* STM32F446xx */ + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ +#if defined(STM32F446xx) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#else + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) + || \ + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) +#endif /* STM32F446xx */ + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \ + (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))); + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* RCC_PLLCFGR_PLLR */ + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. + * + * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. + * @note This function add the PLL/PLLR factor management + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); +} +#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c new file mode 100644 index 0000000..92757d8 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -0,0 +1,3945 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/8 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/4 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/32 | Fpclk/2 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/4 | Fpclk/4 | Fpclk/64 | Fpclk/2 | Fpclk/64 | Fpclk/2 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/64 | Fpclk/2 | Fpclk/128 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/32 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/64 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/2 | Fpclk/128| + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 us */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.DataSize & SPI_CR1_DFF) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + + /* Configure : NSS management, TI Mode */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms + * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + __IO uint32_t count; + + hspi->hdmatx->XferAbortCallback = NULL; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check Busy flag */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + else + { + count--; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait the RXNE reset */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Timeout in us */ + count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer + * If Timeout is reached, the transfer is considered as finish. + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + { + break; + } + count--; + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c new file mode 100644 index 0000000..f056ebf --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -0,0 +1,7629 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances + * supporting a break input. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c new file mode 100644 index 0000000..889f8fb --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can have the following values: (**) + * @arg TIM_TIM1_TIM3_TRGO: TIM1 ITR2 is connected to TIM3 TRGO + * @arg TIM_TIM1_LPTIM: TIM1 ITR2 is connected to LPTIM1 output + * + * For TIM2, the parameter can have the following values: (**) + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 is connected to TIM8 TRGO (*) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 is connected to PTP trigger output (*) + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 is connected to OTG FS SOF + * + * For TIM5, the parameter can have the following values: + * @arg TIM_TIM5_GPIO: TIM5 TI4 is connected to GPIO + * @arg TIM_TIM5_LSI: TIM5 TI4 is connected to LSI + * @arg TIM_TIM5_LSE: TIM5 TI4 is connected to LSE + * @arg TIM_TIM5_RTC: TIM5 TI4 is connected to the RTC wakeup interrupt + * @arg TIM_TIM5_TIM3_TRGO: TIM5 ITR1 is connected to TIM3 TRGO (*) + * @arg TIM_TIM5_LPTIM: TIM5 ITR1 is connected to LPTIM1 output (*) + * + * For TIM9, the parameter can have the following values: (**) + * @arg TIM_TIM9_TIM3_TRGO: TIM9 ITR1 is connected to TIM3 TRGO + * @arg TIM_TIM9_LPTIM: TIM9 ITR1 is connected to LPTIM1 output + * + * For TIM11, the parameter can have the following values: + * @arg TIM_TIM11_GPIO: TIM11 TI1 is connected to GPIO + * @arg TIM_TIM11_HSE: TIM11 TI1 is connected to HSE_RTC clock + * @arg TIM_TIM11_SPDIFRX: TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC (*) + * + * (*) Value not defined in all devices. \n + * (**) Register not available in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + + __HAL_LOCK(htim); + +#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) + if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) + { + /* Connect TIMx internal trigger to LPTIM1 output */ + __HAL_RCC_LPTIM1_CLK_ENABLE(); + MODIFY_REG(LPTIM1->OR, + (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP), + Remap & ~(LPTIM_REMAP_MASK)); + } + else + { + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); + } +#else + /* Set the Timer remapping configuration */ + WRITE_REG(htim->Instance->OR, Remap); +#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */ + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c new file mode 100644 index 0000000..cf6d201 --- /dev/null +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -0,0 +1,3807 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (##) Enable the USARTx interface clock. + (##) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure the UART TX/RX pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required + Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx stream. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx stream. + (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode(Receiver/Transmitter) in the huart Init structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. + + (#) For the Multi-Processor mode, initialize the UART registers by calling + the HAL_MultiProcessor_Init() API. + + [..] + (@) The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit + and receive process. + + [..] + (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized + HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + (+) Receive an amount of data in blocking mode using HAL_UART_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() + (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() + (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback + (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_UART_RxCpltCallback + (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_UART_ErrorCallback + (+) Pause the DMA Transfer using HAL_UART_DMAPause() + (+) Resume the DMA Transfer using HAL_UART_DMAResume() + (+) Stop the DMA Transfer using HAL_UART_DMAStop() + + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + + + *** UART HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in UART HAL driver. + + (+) __HAL_UART_ENABLE: Enable the UART peripheral + (+) __HAL_UART_DISABLE: Disable the UART peripheral + (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not + (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag + (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt + (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt + (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not + + [..] + (@) You can refer to the UART HAL driver header file for more useful macros + + @endverbatim + [..] + (@) Additional remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs + follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration + procedures (details for the procedures are available in reference manual + (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs + RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs + RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs + RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)). + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the UART mode according to the specified parameters in + * the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* The hardware flow control is available only for USART1, USART2, USART3 and USART6. + Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5. + */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + } + else + { + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the LIN mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection + * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In LIN mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); + SET_BIT(huart->Instance->CR2, BreakDetectLength); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state*/ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief Initializes the Multi-Processor mode according to the specified + * parameters in the UART_InitTypeDef and create the associated handle. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. + * This parameter can be one of the following values: + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Check the Address & wake up method parameters */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + assert_param(IS_UART_ADDRESS(Address)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + UART_SetConfig(huart); + + /* In Multi-Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Set the USART address node */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); + SET_BIT(huart->Instance->CR2, Address); + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); + SET_BIT(huart->Instance->CR1, WakeUpMethod); + + /* Enable the peripheral */ + __HAL_UART_ENABLE(huart); + + /* Initialize the UART state */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + return HAL_OK; +} + +/** + * @brief DeInitializes the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlock */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief UART MSP Init. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspInit could be implemented in the user file + */ +} + +/** + * @brief UART MSP DeInit. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), + * HAL_MultiProcessor_Init() to register callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() to un-register callbacks for HAL_UART_MSPINIT_CB_ID + * and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Sends an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Check the remain data to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Enable the UART Transmit data register empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in non blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sends an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + const uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA stream */ + tmp = (const uint32_t *)&pData; + if (HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pauses the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + uint32_t dmarequest = 0x00U; + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() + */ + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream */ + if (huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + pdata16bits++; + } + else + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if (errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx stream */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_SR_IDLE) != 0U) + && ((cr1its & USART_CR1_IDLEIE) != 0U)) + { + __HAL_UART_CLEAR_IDLEFLAG(huart); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + return; + } + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + UART_Transmit_IT(huart); + return; + } + + /* UART in mode Transmitter end --------------------------------------------*/ + if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + UART_EndTransmit_IT(huart); + return; + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief UART error callbacks. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART: + (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. + (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. + (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. + (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode + (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode + +@endverbatim + * @{ + */ + +/** + * @brief Transmits break characters. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enters the UART in mute mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Exits the UART mute mode: wake up software. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + + huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART transmitter and disables the UART receiver. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enables the UART receiver and disables the UART transmitter. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg = 0x00U; + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief UART State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + UART communication process, return Peripheral Errors occurred during communication + process + (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. + (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the UART state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART error code + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->TxXferCount = 0x00U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* DMA Normal mode*/ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) + { + huart->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t dmarequest = 0x00U; + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0x00U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0x00U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param Flag specifies the UART flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_OREFLAG(huart); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); + + /* Enable the UART Data Register not empty Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); + + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + uint32_t *tmp; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + tmp = (uint32_t *)&pData; + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); + + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + huart->RxXferCount = 0x00U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief Sends an amount of data in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + huart->pTxBuffPtr += 2U; + } + else + { + huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); + } + + if (--huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + return HAL_OK; +} + +/** + * @brief Receives an amount of data in non blocking mode + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) +{ + uint8_t *pdata8bits = NULL; + uint16_t *pdata16bits = NULL; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + /* Unused pdata8bits */ + UNUSED(pdata8bits); + pdata16bits = (uint16_t *) huart->pRxBuffPtr; + *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); + huart->pRxBuffPtr += 2U; + } + else + { + pdata8bits = (uint8_t *) huart->pRxBuffPtr; + /* Unused pdata16bits */ + UNUSED(pdata16bits); + + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } + huart->pRxBuffPtr += 1U; + } + + if (--huart->RxXferCount == 0U) + { + /* Disable the UART Data Register not empty Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); + + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; + } + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configures the UART peripheral. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits + according to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the UART Word Length, Parity and mode: + Set the M bits according to huart->Init.WordLength value + Set PCE and PS bits according to huart->Init.Parity value + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ + MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); + + +#if defined(USART6) && defined(UART9) && defined(UART10) + if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#else + if (huart->Instance == USART1) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + } + /*-------------------------- USART BRR Configuration ---------------------*/ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Infantry.ioc b/Infantry.ioc new file mode 100644 index 0000000..ffcba7f --- /dev/null +++ b/Infantry.ioc @@ -0,0 +1,357 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +CAN1.BS1=CAN_BS1_10TQ +CAN1.BS2=CAN_BS2_3TQ +CAN1.CalculateBaudRate=1000000 +CAN1.CalculateTimeBit=1000 +CAN1.CalculateTimeQuantum=71.42857142857143 +CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,NART +CAN1.NART=ENABLE +CAN1.Prescaler=3 +CAN2.BS1=CAN_BS1_10TQ +CAN2.BS2=CAN_BS2_3TQ +CAN2.CalculateBaudRate=1000000 +CAN2.CalculateTimeBit=1000 +CAN2.CalculateTimeQuantum=71.42857142857143 +CAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,BS2,Prescaler,NART +CAN2.NART=ENABLE +CAN2.Prescaler=3 +Dma.Request0=SPI1_RX +Dma.Request1=SPI1_TX +Dma.Request2=USART3_RX +Dma.RequestsNb=3 +Dma.SPI1_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.SPI1_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.SPI1_RX.0.Instance=DMA2_Stream2 +Dma.SPI1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.SPI1_RX.0.MemInc=DMA_MINC_ENABLE +Dma.SPI1_RX.0.Mode=DMA_NORMAL +Dma.SPI1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.SPI1_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.SPI1_RX.0.Priority=DMA_PRIORITY_VERY_HIGH +Dma.SPI1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.SPI1_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.SPI1_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.SPI1_TX.1.Instance=DMA2_Stream3 +Dma.SPI1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.SPI1_TX.1.MemInc=DMA_MINC_ENABLE +Dma.SPI1_TX.1.Mode=DMA_NORMAL +Dma.SPI1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.SPI1_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.SPI1_TX.1.Priority=DMA_PRIORITY_HIGH +Dma.SPI1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART3_RX.2.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART3_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART3_RX.2.Instance=DMA1_Stream1 +Dma.USART3_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART3_RX.2.MemInc=DMA_MINC_ENABLE +Dma.USART3_RX.2.Mode=DMA_CIRCULAR +Dma.USART3_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART3_RX.2.PeriphInc=DMA_PINC_DISABLE +Dma.USART3_RX.2.Priority=DMA_PRIORITY_HIGH +Dma.USART3_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +FREERTOS.HEAP_NUMBER=4 +FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,HEAP_NUMBER +FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL +FREERTOS.configTOTAL_HEAP_SIZE=0x19999 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32F407IGH6 +Mcu.Family=STM32F4 +Mcu.IP0=CAN1 +Mcu.IP1=CAN2 +Mcu.IP10=USART1 +Mcu.IP11=USART2 +Mcu.IP12=USART3 +Mcu.IP13=USART6 +Mcu.IP2=DMA +Mcu.IP3=FREERTOS +Mcu.IP4=I2C2 +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=SPI1 +Mcu.IP8=SYS +Mcu.IP9=TIM10 +Mcu.IPNb=14 +Mcu.Name=STM32F407I(E-G)Hx +Mcu.Package=UFBGA176 +Mcu.Pin0=PB8 +Mcu.Pin1=PG14 +Mcu.Pin10=PC11 +Mcu.Pin11=PC10 +Mcu.Pin12=PG9 +Mcu.Pin13=PD5 +Mcu.Pin14=PD1 +Mcu.Pin15=PF0 +Mcu.Pin16=PA9 +Mcu.Pin17=PH0-OSC_IN +Mcu.Pin18=PH1-OSC_OUT +Mcu.Pin19=PF1 +Mcu.Pin2=PB4 +Mcu.Pin20=PG6 +Mcu.Pin21=PG3 +Mcu.Pin22=PA0-WKUP +Mcu.Pin23=PA4 +Mcu.Pin24=PC4 +Mcu.Pin25=PC5 +Mcu.Pin26=PB12 +Mcu.Pin27=PA7 +Mcu.Pin28=PB0 +Mcu.Pin29=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin3=PB3 +Mcu.Pin30=VP_SYS_VS_Systick +Mcu.Pin31=VP_TIM10_VS_ClockSourceINT +Mcu.Pin4=PA14 +Mcu.Pin5=PA13 +Mcu.Pin6=PB7 +Mcu.Pin7=PB6 +Mcu.Pin8=PD6 +Mcu.Pin9=PD0 +Mcu.PinsNb=32 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F407IGHx +MxCube.Version=6.16.1 +MxDb.Version=DB.6.0.161 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.CAN1_RX0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN1_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN1_SCE_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN1_TX_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN2_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN2_SCE_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.CAN2_TX_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.EXTI0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.EXTI3_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.EXTI4_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=true +NVIC.SavedSvcallIrqHandlerGenerated=true +NVIC.SavedSystickIrqHandlerGenerated=true +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true\:false\:true\:false +NVIC.USART1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.USART2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.USART6_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +PA0-WKUP.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PA0-WKUP.GPIO_Label=USER_KEY +PA0-WKUP.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PA0-WKUP.GPIO_PuPd=GPIO_PULLUP +PA0-WKUP.Locked=true +PA0-WKUP.Signal=GPXTI0 +PA13.Mode=Serial_Wire +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=Serial_Wire +PA14.Signal=SYS_JTCK-SWCLK +PA4.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label +PA4.GPIO_Label=ACCL_CS +PA4.GPIO_PuPd=GPIO_PULLUP +PA4.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM +PA4.Locked=true +PA4.PinState=GPIO_PIN_SET +PA4.Signal=GPIO_Output +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP +PB0.GPIO_Label=GYRO_CS +PB0.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP +PB0.GPIO_PuPd=GPIO_PULLUP +PB0.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM +PB0.Locked=true +PB0.PinState=GPIO_PIN_SET +PB0.Signal=GPIO_Output +PB12.Locked=true +PB12.Mode=CAN_Activate +PB12.Signal=CAN2_RX +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI1_SCK +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI1_MISO +PB6.Mode=CAN_Activate +PB6.Signal=CAN2_TX +PB7.Mode=Asynchronous +PB7.Signal=USART1_RX +PB8.Signal=S_TIM10_CH1 +PC10.Mode=Asynchronous +PC10.Signal=USART3_TX +PC11.Mode=Asynchronous +PC11.Signal=USART3_RX +PC4.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PC4.GPIO_Label=ACCL_INT +PC4.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PC4.GPIO_PuPd=GPIO_PULLUP +PC4.Locked=true +PC4.Signal=GPXTI4 +PC5.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PC5.GPIO_Label=GYRO_INT +PC5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PC5.GPIO_PuPd=GPIO_PULLUP +PC5.Locked=true +PC5.Signal=GPXTI5 +PCC.Checker=false +PCC.Line=STM32F407/417 +PCC.MCU=STM32F407I(E-G)Hx +PCC.PartNumber=STM32F407IGHx +PCC.Series=STM32F4 +PCC.Temperature=25 +PCC.Vdd=3.3 +PD0.Locked=true +PD0.Mode=CAN_Activate +PD0.Signal=CAN1_RX +PD1.Locked=true +PD1.Mode=CAN_Activate +PD1.Signal=CAN1_TX +PD5.Mode=Asynchronous +PD5.Signal=USART2_TX +PD6.Mode=Asynchronous +PD6.Signal=USART2_RX +PF0.Mode=I2C +PF0.Signal=I2C2_SDA +PF1.Mode=I2C +PF1.Signal=I2C2_SCL +PG14.Mode=Asynchronous +PG14.Signal=USART6_TX +PG3.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PG3.GPIO_Label=CMPS_INT +PG3.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PG3.GPIO_PuPd=GPIO_PULLUP +PG3.Locked=true +PG3.Signal=GPXTI3 +PG6.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP +PG6.GPIO_Label=CMPS_RST +PG6.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD +PG6.GPIO_PuPd=GPIO_PULLUP +PG6.GPIO_Speed=GPIO_SPEED_FREQ_MEDIUM +PG6.Locked=true +PG6.Signal=GPIO_Output +PG9.Mode=Asynchronous +PG9.Signal=USART6_RX +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F407IGHx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.3 +ProjectManager.FreePins=false +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x1000 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=Infantry.ioc +ProjectManager.ProjectName=Infantry +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x2000 +ProjectManager.TargetToolchain=MDK-ARM V5.32 +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true,5-MX_CAN2_Init-CAN2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true,8-MX_USART2_UART_Init-USART2-false-HAL-true,9-MX_USART3_UART_Init-USART3-false-HAL-true,10-MX_I2C2_Init-I2C2-false-HAL-true,11-MX_USART6_UART_Init-USART6-false-HAL-true,12-MX_TIM10_Init-TIM10-false-HAL-true +RCC.48MHZClocksFreq_Value=84000000 +RCC.AHBFreq_Value=168000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=168000000 +RCC.CortexFreq_Value=168000000 +RCC.EthernetFreq_Value=168000000 +RCC.FCLKCortexFreq_Value=168000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=168000000 +RCC.HSE_VALUE=12000000 +RCC.HSI_VALUE=16000000 +RCC.I2SClocksFreq_Value=192000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=168000000 +RCC.PLLCLKFreq_Value=168000000 +RCC.PLLM=6 +RCC.PLLN=168 +RCC.PLLQCLKFreq_Value=84000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RTCFreq_Value=32000 +RCC.RTCHSEDivFreq_Value=6000000 +RCC.SYSCLKFreq_VALUE=168000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=192000000 +SH.GPXTI0.0=GPIO_EXTI0 +SH.GPXTI0.ConfNb=1 +SH.GPXTI3.0=GPIO_EXTI3 +SH.GPXTI3.ConfNb=1 +SH.GPXTI4.0=GPIO_EXTI4 +SH.GPXTI4.ConfNb=1 +SH.GPXTI5.0=GPIO_EXTI5 +SH.GPXTI5.ConfNb=1 +SH.S_TIM10_CH1.0=TIM10_CH1,PWM Generation1 CH1 +SH.S_TIM10_CH1.ConfNb=1 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 +SPI1.CLKPhase=SPI_PHASE_2EDGE +SPI1.CLKPolarity=SPI_POLARITY_HIGH +SPI1.CalculateBaudRate=5.25 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,CLKPhase,CLKPolarity +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER +TIM10.Channel=TIM_CHANNEL_1 +TIM10.IPParameters=Period,Channel +TIM10.Period=5000 +USART1.IPParameters=VirtualMode +USART1.VirtualMode=VM_ASYNC +USART2.IPParameters=VirtualMode +USART2.VirtualMode=VM_ASYNC +USART3.BaudRate=100000 +USART3.IPParameters=VirtualMode,BaudRate,Parity,StopBits,Mode +USART3.Mode=MODE_RX +USART3.Parity=PARITY_EVEN +USART3.StopBits=STOPBITS_1 +USART3.VirtualMode=VM_ASYNC +USART6.IPParameters=VirtualMode +USART6.VirtualMode=VM_ASYNC +VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2 +VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2 +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT +board=custom +rtos.0.ip=FREERTOS diff --git a/MDK-ARM/.vscode/c_cpp_properties.json b/MDK-ARM/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..8580a56 --- /dev/null +++ b/MDK-ARM/.vscode/c_cpp_properties.json @@ -0,0 +1,435 @@ +{ + "configurations": [ + { + "name": "Infantry", + "includePath": [ + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Core\\Inc", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Drivers\\STM32F4xx_HAL_Driver\\Inc", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Drivers\\STM32F4xx_HAL_Driver\\Inc\\Legacy", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Drivers\\CMSIS\\Device\\ST\\STM32F4xx\\Include", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Drivers\\CMSIS\\Include", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Middlewares\\Third_Party\\FreeRTOS\\Source\\include", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Middlewares\\Third_Party\\FreeRTOS\\Source\\CMSIS_RTOS_V2", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Middlewares\\Third_Party\\FreeRTOS\\Source\\portable\\RVDS\\ARM_CM4F", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User\\bsp", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User\\component", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User\\task", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User\\module", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\User\\device", + "D:\\Keil_v5\\ARM\\ARMCLANG\\include", + "D:\\Keil_v5\\ARM\\ARMCLANG\\include\\arm_linux", + "D:\\Keil_v5\\ARM\\ARMCLANG\\include\\arm_linux_compat", + "D:\\Keil_v5\\ARM\\ARMCLANG\\include\\libcxx", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\MDK-ARM", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Core\\Src", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Drivers\\STM32F4xx_HAL_Driver\\Src", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Middlewares\\Third_Party\\FreeRTOS\\Source", + "d:\\yunha\\git_gimbal\\RM\\Infantry\\Middlewares\\Third_Party\\FreeRTOS\\Source\\portable\\MemMang" + ], + "defines": [ + "USE_HAL_DRIVER", + "STM32F407xx", + "__alignof__(x)=", + "__asm(x)=", + "__asm__(x)=", + "__forceinline=", + "__restrict=", + "__volatile__=", + "__inline=", + "__inline__=", + "__declspec(x)=", + "__attribute__(x)=", + "__nonnull__(x)=", + "__unaligned=", + "__promise(x)=", + "__irq=", + "__swi=", + "__weak=", + "__register=", + "__pure=", + "__value_in_regs=", + "__breakpoint(x)=", + "__current_pc()=0U", + "__current_sp()=0U", + "__disable_fiq()=", + "__disable_irq()=", + "__enable_fiq()=", + "__enable_irq()=", + "__force_stores()=", + "__memory_changed()=", + "__schedule_barrier()=", + "__semihost(x,y)=0", + "__vfp_status(x,y)=0", + "__builtin_arm_nop()=", + "__builtin_arm_wfi()=", + "__builtin_arm_wfe()=", + "__builtin_arm_sev()=", + "__builtin_arm_sevl()=", + "__builtin_arm_yield()=", + "__builtin_arm_isb(x)=", + "__builtin_arm_dsb(x)=", + "__builtin_arm_dmb(x)=", + "__builtin_bswap32(x)=0U", + "__builtin_bswap16(x)=0U", + "__builtin_arm_rbit(x)=0U", + "__builtin_clz(x)=0U", + "__builtin_arm_ldrex(x)=0U", + "__builtin_arm_strex(x,y)=0U", + "__builtin_arm_clrex()=", + "__builtin_arm_ssat(x,y)=0U", + "__builtin_arm_usat(x,y)=0U", + "__builtin_arm_ldaex(x)=0U", + "__builtin_arm_stlex(x,y)=0U", + "_ILP32=1", + "_USE_STATIC_INLINE=1", + "__APCS_32__=1", + "__ARMCC_VERSION=6160001", + "__ARMCOMPILER_VERSION=6160001", + "__ARMEL__=1", + "__ARM_32BIT_STATE=1", + "__ARM_ACLE=200", + "__ARM_ARCH=4", + "__ARM_ARCH_4T__=1", + "__ARM_ARCH_ISA_ARM=1", + "__ARM_ARCH_ISA_THUMB=1", + "__ARM_EABI__=1", + "__ARM_FP16_ARGS=1", + "__ARM_FP16_FORMAT_IEEE=1", + "__ARM_NO_IMAGINARY_TYPE=1", + "__ARM_PCS=1", + "__ARM_PROMISE=__builtin_assume", + "__ARM_SIZEOF_MINIMAL_ENUM=4", + "__ARM_SIZEOF_WCHAR_T=4", + "__ARM_TARGET_COPROC=1", + "__ARM_TARGET_COPROC_V4=1", + "__ATOMIC_ACQUIRE=2", + "__ATOMIC_ACQ_REL=4", + "__ATOMIC_CONSUME=1", + "__ATOMIC_RELAXED=0", + "__ATOMIC_RELEASE=3", + "__ATOMIC_SEQ_CST=5", + "__BIGGEST_ALIGNMENT__=8", + "__BYTE_ORDER__=__ORDER_LITTLE_ENDIAN__", + "__CHAR16_TYPE__=unsigned short", + "__CHAR32_TYPE__=unsigned int", + "__CHAR_BIT__=8", + "__CHAR_UNSIGNED__=1", + "__CLANG_ATOMIC_BOOL_LOCK_FREE=1", + "__CLANG_ATOMIC_CHAR16_T_LOCK_FREE=1", + "__CLANG_ATOMIC_CHAR32_T_LOCK_FREE=1", + "__CLANG_ATOMIC_CHAR_LOCK_FREE=1", + "__CLANG_ATOMIC_INT_LOCK_FREE=1", + "__CLANG_ATOMIC_LLONG_LOCK_FREE=1", + "__CLANG_ATOMIC_LONG_LOCK_FREE=1", + "__CLANG_ATOMIC_POINTER_LOCK_FREE=1", + "__CLANG_ATOMIC_SHORT_LOCK_FREE=1", + "__CLANG_ATOMIC_WCHAR_T_LOCK_FREE=1", + "__CONSTANT_CFSTRINGS__=1", + "__DBL_DECIMAL_DIG__=17", + "__DBL_DENORM_MIN__=4.9406564584124654e-324", + "__DBL_DIG__=15", + "__DBL_EPSILON__=2.2204460492503131e-16", + "__DBL_HAS_DENORM__=1", + "__DBL_HAS_INFINITY__=1", + "__DBL_HAS_QUIET_NAN__=1", + "__DBL_MANT_DIG__=53", + "__DBL_MAX_10_EXP__=308", + "__DBL_MAX_EXP__=1024", + "__DBL_MAX__=1.7976931348623157e+308", + "__DBL_MIN_10_EXP__=(-307)", + "__DBL_MIN_EXP__=(-1021)", + "__DBL_MIN__=2.2250738585072014e-308", + "__DECIMAL_DIG__=__LDBL_DECIMAL_DIG__", + "__ELF__=1", + "__ESCAPE__=", + "__FINITE_MATH_ONLY__=1", + "__FLT16_DECIMAL_DIG__=5", + "__FLT16_DENORM_MIN__=5.9604644775390625e-8F16", + "__FLT16_DIG__=3", + "__FLT16_EPSILON__=9.765625e-4F16", + "__FLT16_HAS_DENORM__=1", + "__FLT16_HAS_INFINITY__=1", + "__FLT16_HAS_QUIET_NAN__=1", + "__FLT16_MANT_DIG__=11", + "__FLT16_MAX_10_EXP__=4", + "__FLT16_MAX_EXP__=16", + "__FLT16_MAX__=6.5504e+4F16", + "__FLT16_MIN_10_EXP__=(-4)", + "__FLT16_MIN_EXP__=(-13)", + "__FLT16_MIN__=6.103515625e-5F16", + "__FLT_DECIMAL_DIG__=9", + "__FLT_DENORM_MIN__=1.40129846e-45F", + "__FLT_DIG__=6", + "__FLT_EPSILON__=1.19209290e-7F", + "__FLT_EVAL_METHOD__=0", + "__FLT_HAS_DENORM__=1", + "__FLT_HAS_INFINITY__=1", + "__FLT_HAS_QUIET_NAN__=1", + "__FLT_MANT_DIG__=24", + "__FLT_MAX_10_EXP__=38", + "__FLT_MAX_EXP__=128", + "__FLT_MAX__=3.40282347e+38F", + "__FLT_MIN_10_EXP__=(-37)", + "__FLT_MIN_EXP__=(-125)", + "__FLT_MIN__=1.17549435e-38F", + "__FLT_RADIX__=2", + "__GCC_ATOMIC_BOOL_LOCK_FREE=1", + "__GCC_ATOMIC_CHAR16_T_LOCK_FREE=1", + "__GCC_ATOMIC_CHAR32_T_LOCK_FREE=1", + "__GCC_ATOMIC_CHAR_LOCK_FREE=1", + "__GCC_ATOMIC_INT_LOCK_FREE=1", + "__GCC_ATOMIC_LLONG_LOCK_FREE=1", + "__GCC_ATOMIC_LONG_LOCK_FREE=1", + "__GCC_ATOMIC_POINTER_LOCK_FREE=1", + "__GCC_ATOMIC_SHORT_LOCK_FREE=1", + "__GCC_ATOMIC_TEST_AND_SET_TRUEVAL=1", + "__GCC_ATOMIC_WCHAR_T_LOCK_FREE=1", + "__GNUC_MINOR__=2", + "__GNUC_PATCHLEVEL__=1", + "__GNUC_STDC_INLINE__=1", + "__GNUC__=4", + "__GXX_ABI_VERSION=1002", + "__ILP32__=1", + "__INT16_C_SUFFIX__=", + "__INT16_FMTd__=\"hd\"", + "__INT16_FMTi__=\"hi\"", + "__INT16_MAX__=32767", + "__INT16_TYPE__=short", + "__INT32_C_SUFFIX__=", + "__INT32_FMTd__=\"d\"", + "__INT32_FMTi__=\"i\"", + "__INT32_MAX__=2147483647", + "__INT32_TYPE__=int", + "__INT64_C_SUFFIX__=LL", + "__INT64_FMTd__=\"lld\"", + "__INT64_FMTi__=\"lli\"", + "__INT64_MAX__=9223372036854775807LL", + "__INT64_TYPE__=long long int", + "__INT8_C_SUFFIX__=", + "__INT8_FMTd__=\"hhd\"", + "__INT8_FMTi__=\"hhi\"", + "__INT8_MAX__=127", + "__INT8_TYPE__=signed char", + "__INTMAX_C_SUFFIX__=LL", + "__INTMAX_FMTd__=\"lld\"", + "__INTMAX_FMTi__=\"lli\"", + "__INTMAX_MAX__=9223372036854775807LL", + "__INTMAX_TYPE__=long long int", + "__INTMAX_WIDTH__=64", + "__INTPTR_FMTd__=\"d\"", + "__INTPTR_FMTi__=\"i\"", + "__INTPTR_MAX__=2147483647", + "__INTPTR_TYPE__=int", + "__INTPTR_WIDTH__=32", + "__INT_FAST16_FMTd__=\"hd\"", + "__INT_FAST16_FMTi__=\"hi\"", + "__INT_FAST16_MAX__=32767", + "__INT_FAST16_TYPE__=short", + "__INT_FAST32_FMTd__=\"d\"", + "__INT_FAST32_FMTi__=\"i\"", + "__INT_FAST32_MAX__=2147483647", + "__INT_FAST32_TYPE__=int", + "__INT_FAST64_FMTd__=\"lld\"", + "__INT_FAST64_FMTi__=\"lli\"", + "__INT_FAST64_MAX__=9223372036854775807LL", + "__INT_FAST64_TYPE__=long long int", + "__INT_FAST8_FMTd__=\"hhd\"", + "__INT_FAST8_FMTi__=\"hhi\"", + "__INT_FAST8_MAX__=127", + "__INT_FAST8_TYPE__=signed char", + "__INT_LEAST16_FMTd__=\"hd\"", + "__INT_LEAST16_FMTi__=\"hi\"", + "__INT_LEAST16_MAX__=32767", + "__INT_LEAST16_TYPE__=short", + "__INT_LEAST32_FMTd__=\"d\"", + "__INT_LEAST32_FMTi__=\"i\"", + "__INT_LEAST32_MAX__=2147483647", + "__INT_LEAST32_TYPE__=int", + "__INT_LEAST64_FMTd__=\"lld\"", + "__INT_LEAST64_FMTi__=\"lli\"", + "__INT_LEAST64_MAX__=9223372036854775807LL", + "__INT_LEAST64_TYPE__=long long int", + "__INT_LEAST8_FMTd__=\"hhd\"", + "__INT_LEAST8_FMTi__=\"hhi\"", + "__INT_LEAST8_MAX__=127", + "__INT_LEAST8_TYPE__=signed char", + "__INT_MAX__=2147483647", + "__I__=1.0if", + "__LDBL_DECIMAL_DIG__=17", + "__LDBL_DENORM_MIN__=4.9406564584124654e-324L", + "__LDBL_DIG__=15", + "__LDBL_EPSILON__=2.2204460492503131e-16L", + "__LDBL_HAS_DENORM__=1", + "__LDBL_HAS_INFINITY__=1", + "__LDBL_HAS_QUIET_NAN__=1", + "__LDBL_MANT_DIG__=53", + "__LDBL_MAX_10_EXP__=308", + "__LDBL_MAX_EXP__=1024", + "__LDBL_MAX__=1.7976931348623157e+308L", + "__LDBL_MIN_10_EXP__=(-307)", + "__LDBL_MIN_EXP__=(-1021)", + "__LDBL_MIN__=2.2250738585072014e-308L", + "__LITTLE_ENDIAN__=1", + "__LONG_LONG_MAX__=9223372036854775807LL", + "__LONG_MAX__=2147483647L", + "__NO_INLINE__=1", + "__OBJC_BOOL_IS_BOOL=0", + "__OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES=3", + "__OPENCL_MEMORY_SCOPE_DEVICE=2", + "__OPENCL_MEMORY_SCOPE_SUB_GROUP=4", + "__OPENCL_MEMORY_SCOPE_WORK_GROUP=1", + "__OPENCL_MEMORY_SCOPE_WORK_ITEM=0", + "__ORDER_BIG_ENDIAN__=4321", + "__ORDER_LITTLE_ENDIAN__=1234", + "__ORDER_PDP_ENDIAN__=3412", + "__POINTER_WIDTH__=32", + "__PRAGMA_REDEFINE_EXTNAME=1", + "__PTRDIFF_FMTd__=\"d\"", + "__PTRDIFF_FMTi__=\"i\"", + "__PTRDIFF_MAX__=2147483647", + "__PTRDIFF_TYPE__=int", + "__PTRDIFF_WIDTH__=32", + "__REGISTER_PREFIX__=", + "__SCHAR_MAX__=127", + "__SHRT_MAX__=32767", + "__SIG_ATOMIC_MAX__=2147483647", + "__SIG_ATOMIC_WIDTH__=32", + "__SIZEOF_DOUBLE__=8", + "__SIZEOF_FLOAT__=4", + "__SIZEOF_INT__=4", + "__SIZEOF_LONG_DOUBLE__=8", + "__SIZEOF_LONG_LONG__=8", + "__SIZEOF_LONG__=4", + "__SIZEOF_POINTER__=4", + "__SIZEOF_PTRDIFF_T__=4", + "__SIZEOF_SHORT__=2", + "__SIZEOF_SIZE_T__=4", + "__SIZEOF_WCHAR_T__=4", + "__SIZEOF_WINT_T__=4", + "__SIZE_FMTX__=\"X\"", + "__SIZE_FMTo__=\"o\"", + "__SIZE_FMTu__=\"u\"", + "__SIZE_FMTx__=\"x\"", + "__SIZE_MAX__=4294967295U", + "__SIZE_TYPE__=unsigned int", + "__SIZE_WIDTH__=32", + "__STDC_HOSTED__=1", + "__STDC_UTF_16__=1", + "__STDC_UTF_32__=1", + "__STDC_VERSION__=201710L", + "__STDC__=1", + "__UINT16_C_SUFFIX__=", + "__UINT16_FMTX__=\"hX\"", + "__UINT16_FMTo__=\"ho\"", + "__UINT16_FMTu__=\"hu\"", + "__UINT16_FMTx__=\"hx\"", + "__UINT16_MAX__=65535", + "__UINT16_TYPE__=unsigned short", + "__UINT32_C_SUFFIX__=U", + "__UINT32_FMTX__=\"X\"", + "__UINT32_FMTo__=\"o\"", + "__UINT32_FMTu__=\"u\"", + "__UINT32_FMTx__=\"x\"", + "__UINT32_MAX__=4294967295U", + "__UINT32_TYPE__=unsigned int", + "__UINT64_C_SUFFIX__=ULL", + "__UINT64_FMTX__=\"llX\"", + "__UINT64_FMTo__=\"llo\"", + "__UINT64_FMTu__=\"llu\"", + "__UINT64_FMTx__=\"llx\"", + "__UINT64_MAX__=18446744073709551615ULL", + "__UINT64_TYPE__=long long unsigned int", + "__UINT8_C_SUFFIX__=", + "__UINT8_FMTX__=\"hhX\"", + "__UINT8_FMTo__=\"hho\"", + "__UINT8_FMTu__=\"hhu\"", + "__UINT8_FMTx__=\"hhx\"", + "__UINT8_MAX__=255", + "__UINT8_TYPE__=unsigned char", + "__UINTMAX_C_SUFFIX__=ULL", + "__UINTMAX_FMTX__=\"llX\"", + "__UINTMAX_FMTo__=\"llo\"", + "__UINTMAX_FMTu__=\"llu\"", + "__UINTMAX_FMTx__=\"llx\"", + "__UINTMAX_MAX__=18446744073709551615ULL", + "__UINTMAX_TYPE__=long long unsigned int", + "__UINTMAX_WIDTH__=64", + "__UINTPTR_FMTX__=\"X\"", + "__UINTPTR_FMTo__=\"o\"", + "__UINTPTR_FMTu__=\"u\"", + "__UINTPTR_FMTx__=\"x\"", + "__UINTPTR_MAX__=4294967295U", + "__UINTPTR_TYPE__=unsigned int", + "__UINTPTR_WIDTH__=32", + "__UINT_FAST16_FMTX__=\"hX\"", + "__UINT_FAST16_FMTo__=\"ho\"", + "__UINT_FAST16_FMTu__=\"hu\"", + "__UINT_FAST16_FMTx__=\"hx\"", + "__UINT_FAST16_MAX__=65535", + "__UINT_FAST16_TYPE__=unsigned short", + "__UINT_FAST32_FMTX__=\"X\"", + "__UINT_FAST32_FMTo__=\"o\"", + "__UINT_FAST32_FMTu__=\"u\"", + "__UINT_FAST32_FMTx__=\"x\"", + "__UINT_FAST32_MAX__=4294967295U", + "__UINT_FAST32_TYPE__=unsigned int", + "__UINT_FAST64_FMTX__=\"llX\"", + "__UINT_FAST64_FMTo__=\"llo\"", + "__UINT_FAST64_FMTu__=\"llu\"", + "__UINT_FAST64_FMTx__=\"llx\"", + "__UINT_FAST64_MAX__=18446744073709551615ULL", + "__UINT_FAST64_TYPE__=long long unsigned int", + "__UINT_FAST8_FMTX__=\"hhX\"", + "__UINT_FAST8_FMTo__=\"hho\"", + "__UINT_FAST8_FMTu__=\"hhu\"", + "__UINT_FAST8_FMTx__=\"hhx\"", + "__UINT_FAST8_MAX__=255", + "__UINT_FAST8_TYPE__=unsigned char", + "__UINT_LEAST16_FMTX__=\"hX\"", + "__UINT_LEAST16_FMTo__=\"ho\"", + "__UINT_LEAST16_FMTu__=\"hu\"", + "__UINT_LEAST16_FMTx__=\"hx\"", + "__UINT_LEAST16_MAX__=65535", + "__UINT_LEAST16_TYPE__=unsigned short", + "__UINT_LEAST32_FMTX__=\"X\"", + "__UINT_LEAST32_FMTo__=\"o\"", + "__UINT_LEAST32_FMTu__=\"u\"", + "__UINT_LEAST32_FMTx__=\"x\"", + "__UINT_LEAST32_MAX__=4294967295U", + "__UINT_LEAST32_TYPE__=unsigned int", + "__UINT_LEAST64_FMTX__=\"llX\"", + "__UINT_LEAST64_FMTo__=\"llo\"", + "__UINT_LEAST64_FMTu__=\"llu\"", + "__UINT_LEAST64_FMTx__=\"llx\"", + "__UINT_LEAST64_MAX__=18446744073709551615ULL", + "__UINT_LEAST64_TYPE__=long long unsigned int", + "__UINT_LEAST8_FMTX__=\"hhX\"", + "__UINT_LEAST8_FMTo__=\"hho\"", + "__UINT_LEAST8_FMTu__=\"hhu\"", + "__UINT_LEAST8_FMTx__=\"hhx\"", + "__UINT_LEAST8_MAX__=255", + "__UINT_LEAST8_TYPE__=unsigned char", + "__USER_LABEL_PREFIX__=", + "__VERSION__=\"Clang 13.0.0 (ssh://ds-gerrit/armcompiler/llvm-project 1f5770d6f72ee4eba2159092bbf4cbb819be323a)\"", + "__WCHAR_MAX__=4294967295U", + "__WCHAR_TYPE__=unsigned int", + "__WCHAR_UNSIGNED__=1", + "__WCHAR_WIDTH__=32", + "__WINT_MAX__=2147483647", + "__WINT_TYPE__=int", + "__WINT_WIDTH__=32", + "__arm=1", + "__arm__=1", + "__clang__=1", + "__clang_major__=13", + "__clang_minor__=0", + "__clang_patchlevel__=0", + "__clang_version__=\"13.0.0 (ssh://ds-gerrit/armcompiler/llvm-project 1f5770d6f72ee4eba2159092bbf4cbb819be323a)\"", + "__llvm__=1" + ], + "intelliSenseMode": "${default}" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/MDK-ARM/.vscode/keil-assistant.log b/MDK-ARM/.vscode/keil-assistant.log new file mode 100644 index 0000000..eea60fc --- /dev/null +++ b/MDK-ARM/.vscode/keil-assistant.log @@ -0,0 +1,7 @@ +[info] Log at : 2026/1/8|21:31:20|GMT+0800 + +[info] Log at : 2026/1/8|21:31:24|GMT+0800 + +[info] project closed: Infantry +[info] Log at : 2026/1/8|22:21:24|GMT+0800 + diff --git a/MDK-ARM/.vscode/settings.json b/MDK-ARM/.vscode/settings.json new file mode 100644 index 0000000..841e1ad --- /dev/null +++ b/MDK-ARM/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "files.associations": { + "user_task.h": "c" + } +} \ No newline at end of file diff --git a/MDK-ARM/.vscode/uv4.log b/MDK-ARM/.vscode/uv4.log new file mode 100644 index 0000000..d2bbb61 --- /dev/null +++ b/MDK-ARM/.vscode/uv4.log @@ -0,0 +1,4 @@ +*** Using Compiler 'V6.16', folder: 'D:\Keil_v5\ARM\ARMCLANG\Bin' +Build target 'Infantry' +Note: source file '..\User\bsp\can.c' - object file renamed from 'Infantry\can.o' to 'Infantry\can_1.o'.Note: source file '..\User\bsp\gpio.c' - object file renamed from 'Infantry\gpio.o' to 'Infantry\gpio_1.o'.Note: source file '..\User\bsp\i2c.c' - object file renamed from 'Infantry\i2c.o' to 'Infantry\i2c_1.o'.Note: source file '..\User\bsp\spi.c' - object file renamed from 'Infantry\spi.o' to 'Infantry\spi_1.o'.Note: source file '..\User\task\ai.c' - object file renamed from 'Infantry\ai.o' to 'Infantry\ai_1.o'.Note: source file '..\User\task\dr16.c' - object file renamed from 'Infantry\dr16.o' to 'Infantry\dr16_1.o'."Infantry\Infantry.axf" - 0 Error(s), 0 Warning(s). +Build Time Elapsed: 00:00:02 diff --git a/MDK-ARM/.vscode/uv4.log.lock b/MDK-ARM/.vscode/uv4.log.lock new file mode 100644 index 0000000..d3edd35 --- /dev/null +++ b/MDK-ARM/.vscode/uv4.log.lock @@ -0,0 +1 @@ +2026/1/8 22:21:37 \ No newline at end of file diff --git a/MDK-ARM/DebugConfig/Infantry_STM32F407IGHx.dbgconf b/MDK-ARM/DebugConfig/Infantry_STM32F407IGHx.dbgconf new file mode 100644 index 0000000..1df0a1b --- /dev/null +++ b/MDK-ARM/DebugConfig/Infantry_STM32F407IGHx.dbgconf @@ -0,0 +1,48 @@ +// File: STM32F405_415_407_417_427_437_429_439.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090) +// refer to STM32F40x STM32F41x datasheets +// refer to STM32F42x STM32F43x datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug Standby Mode +// DBG_STOP Debug Stop Mode +// DBG_SLEEP Debug Sleep Mode +// +DbgMCU_CR = 0x00000007; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_CAN2_STOP CAN2 stopped when core is halted +// DBG_CAN1_STOP CAN2 stopped when core is halted +// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// DBG_WWDG_STOP Window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/MDK-ARM/EventRecorderStub.scvd b/MDK-ARM/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/MDK-ARM/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/MDK-ARM/Infantry.uvguix.yunha b/MDK-ARM/Infantry.uvguix.yunha new file mode 100644 index 0000000..412e2a0 --- /dev/null +++ b/MDK-ARM/Infantry.uvguix.yunha @@ -0,0 +1,3655 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
+ + + D:\yunha\git_gimbal\RM\Infantry\User\task + + + + + + + 38003 + Registers + 115 100 + + + 346 + Code Coverage + 725 155 + + + 204 + Performance Analyzer + 334 130 130 286 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 60 60 60 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 300 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 2 + + -32000 + -32000 + + + -1 + -1 + + + 0 + 367 + 1447 + 602 + + + + 0 + + 566 + 01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000005000000030000000100000035443A5C79756E68615C6769745F67696D62616C5C524D5C496E66616E7472795C557365725C6D6F64756C655C636861737369732E630000000009636861737369732E6300000000C5D4F200FFFFFFFF35443A5C79756E68615C6769745F67696D62616C5C524D5C496E66616E7472795C557365725C6D6F64756C655C636861737369732E680000000009636861737369732E6800000000FFDC7800FFFFFFFF34443A5C79756E68615C6769745F67696D62616C5C524D5C496E66616E7472795C557365725C6D6F64756C655C67696D62616C2E63000000000867696D62616C2E6300000000BECEA100FFFFFFFF34443A5C79756E68615C6769745F67696D62616C5C524D5C496E66616E7472795C557365725C6D6F64756C655C636F6E6669672E630000000008636F6E6669672E6300000000F0A0A100FFFFFFFF34443A5C79756E68615C6769745F67696D62616C5C524D5C496E66616E7472795C557365725C6D6F64756C655C636F6E6669672E680000000008636F6E6669672E6800000000BCA8E100FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000B883FFFF4F83FFFFA088FFFF6C85FFFF + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B80000004F00000028040000BF000000 + + + 16 + B80000006600000028040000D6000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000053020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000053020000 + + + 16 + A4000000BB000000780100007E020000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000053020000 + + + 16 + A4000000BB000000780100007E020000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000053020000 + + + 16 + A4000000BB000000780100007E020000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 0000000084020000A00500002A030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000009C0100002804000020020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000870200009D05000011030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000053020000 + + + 16 + A4000000BB000000780100007E020000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000870200009D05000011030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000870200009D05000011030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000870200009D05000011030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000870200009D05000011030000 + + + 16 + 800000000D03000020060000E7030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB0000006600000025040000A6000000 + + + 16 + A4000000BB000000B80200002B010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + A4000000BB0000005801000060010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 000000002A030000A00500003D030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000B30100002504000007020000 + + + 16 + A4000000BB0000005801000060010000 + + + + 3332 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFB8000000BF00000028040000C3000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000B80000006600000028040000D6000000B80000004F00000028040000BF0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF700300004F00000074030000AC010000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000740300006600000028040000C3010000740300004F00000028040000AC01000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFB40000004F000000B80000006C020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000B400000083020000000000004F000000B40000006C0200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000098010000280400009C01000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB0900000180008000000000000000000000B30100002804000037020000000000009C010000280400002002000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFF140200009C010000180200002002000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF000000006C020000A00500007002000001000000010000100400000001000000000000000000000000000000000000000000000001000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF01000077940000018000800000010000000000000087020000A0050000410300000000000070020000A00500002A0300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF0000000000000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2838 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000D4253505F554152545F44523136960000000000000014000D4253505F554152545F4452313605464443414E08667269635F72706D1353686F6F745F43616C7554617267657452504D0A6D61785472696772706D0F434F4D505F415439535F434D445F74145349474E414C5F445231365F5241575F5245445906445231365F74164F49445F5061727365466565646261636B4672616D6505706172616D095461736B5F496E6974036E6F77067961775B305D096D6F746F722E7961770B7461726765745F66726571056666616273046661627303616273072D3E755F6D617808706172616D2D3E4A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 976 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008496E66616E7472799600000000000000010008496E66616E747279000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1440 + 900 + + + + 1 + Debug + + -1 + -1 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B80000004F00000032040000BF000000 + + + 16 + B80000006600000032040000D6000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000089020000 + + + 16 + BE000000D5000000720100007A010000 + + + + 109 + 109 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000089020000 + + + 16 + BE000000D50000009201000098020000 + + + + 1465 + 1465 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 1935 + 1935 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1936 + 1936 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 195 + 195 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000089020000 + + + 16 + BE000000D50000009201000098020000 + + + + 196 + 196 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000089020000 + + + 16 + BE000000D50000009201000098020000 + + + + 197 + 197 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D5000000D202000045010000 + + + + 198 + 198 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 00000000A6020000320400002A030000 + + + 16 + BE000000D5000000D202000045010000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D5000000D202000045010000 + + + + 203 + 203 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + B80000006300000032040000BF000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 38003 + 38003 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000B100000089020000 + + + 16 + BE000000D50000009201000098020000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D5000000D202000045010000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D50000009201000098020000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D50000009201000098020000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000C70100002504000007020000 + + + 16 + BE000000D50000009201000098020000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + BB000000660000002F040000A6000000 + + + 16 + BE000000D5000000D202000045010000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 77030000660000002504000093010000 + + + 16 + BE000000D5000000720100007A010000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 000000002A030000A00500003D030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 0 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 1 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 000000001C0000006F02000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 39040000660000009D05000011030000 + + + 16 + 3D040000B20100000907000036020000 + + + + 3415 + 000000000C000000000000000020000001000000FFFFFFFFFFFFFFFFB8000000BF00000032040000C3000000010000000100001004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000001000000B80000006600000032040000D6000000B80000004F00000032040000BF0000000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF700300004F00000074030000AC010000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000740300006600000028040000C3010000740300004F00000028040000AC01000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFB40000004F000000B8000000A2020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C400000073940000018000100000010000000000000066000000B4000000B9020000000000004F000000B4000000A20200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF00000000A202000032040000A602000001000000010000100400000001000000000000000000000000000000000000000000000001000000C60000000000000001000000000000000000000001000000FFFFFFFFD0020000A6020000D40200002A03000000000000020000000400000000000000000000000000000000000000000000000000000001000000C600000001000000C6000000000000000080000000000000FFFFFFFFFFFFFFFF00000000AC01000028040000B0010000000000000100000004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF010000779400000180008000000000000000000000C7010000280400003702000000000000B001000028040000200200000000000040820046060000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000040000001000000FFFFFFFFFFFFFFFF320400004F000000360400002A0300000100000002000010040000000100000055FDFFFF3202000000000000000000000000000001000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB090000018000400000010000003604000066000000A005000041030000360400004F000000A00500002A03000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031010000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF0500000000000000000000000000000000000000000000000000000001000000FFFFFFFF8F07000001000000FFFFFFFF8F070000000000000000000000000000 + + + 59392 + File + + 2838 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000000460000000000000000000000000000000001000000010000000180FE880000000000004500000000000000000000000000000000010000000100000001800B810000000000001300000000000000000000000000000000010000000100000001800C810000000000001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000D4253505F554152545F44523136960000000000000014000D4253505F554152545F4452313605464443414E08667269635F72706D1353686F6F745F43616C7554617267657452504D0A6D61785472696772706D0F434F4D505F415439535F434D445F74145349474E414C5F445231365F5241575F5245445906445231365F74164F49445F5061727365466565646261636B4672616D6505706172616D095461736B5F496E6974036E6F77067961775B305D096D6F746F722E7961770B7461726765745F66726571056666616273046661627303616273072D3E755F6D617808706172616D2D3E4A0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000100150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000400160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 955 + 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2362 + 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000004002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000100310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1440 + 900 + + + + + + 1 + 0 + + 100 + 3 + + ..\User\module\chassis.c + 5 + 13 + 41 + 1 + + 0 + + + ..\User\module\chassis.h + 19 + 71 + 72 + 1 + + 0 + + + ..\User\module\gimbal.c + 5 + 555 + 572 + 1 + + 0 + + + ..\User\module\config.c + 21 + 263 + 281 + 1 + + 0 + + + ..\User\module\config.h + 16 + 1 + 17 + 1 + + 0 + + + + + diff --git a/MDK-ARM/Infantry.uvoptx b/MDK-ARM/Infantry.uvoptx new file mode 100644 index 0000000..5aa4ca4 --- /dev/null +++ b/MDK-ARM/Infantry.uvoptx @@ -0,0 +1,1359 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Infantry + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + CMSIS_AGDI + -X"" -O206 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407IGHx$CMSIS\Flash\STM32F4xx_1024.FLM) + + + + + + 0 + 1 + dr16,0x0A + + + 1 + 1 + remote_dr16,0x0A + + + 2 + 1 + s_rc_cmd + + + 3 + 1 + g_rc_cmd + + + 4 + 1 + gimbal + + + 5 + 1 + gimbal_cmd_remote + + + 6 + 1 + gimbal_cmd + + + 7 + 1 + shoot_cmd + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Application/MDK-ARM + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32f407xx.s + startup_stm32f407xx.s + 0 + 0 + + + + + Application/User/Core + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ../Core/Src/main.c + main.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ../Core/Src/gpio.c + gpio.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ../Core/Src/freertos.c + freertos.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ../Core/Src/can.c + can.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ../Core/Src/dma.c + dma.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ../Core/Src/i2c.c + i2c.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ../Core/Src/spi.c + spi.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ../Core/Src/tim.c + tim.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ../Core/Src/usart.c + usart.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ../Core/Src/stm32f4xx_it.c + stm32f4xx_it.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ../Core/Src/stm32f4xx_hal_msp.c + stm32f4xx_hal_msp.c + 0 + 0 + + + + + Drivers/STM32F4xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 13 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + stm32f4xx_hal_can.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + stm32f4xx_hal_rcc.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + stm32f4xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + stm32f4xx_hal_flash.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + stm32f4xx_hal_flash_ex.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + stm32f4xx_hal_flash_ramfunc.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + stm32f4xx_hal_gpio.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + stm32f4xx_hal_dma_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + stm32f4xx_hal_dma.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + stm32f4xx_hal_pwr.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + stm32f4xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + stm32f4xx_hal_cortex.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + stm32f4xx_hal.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c + stm32f4xx_hal_exti.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + stm32f4xx_hal_i2c.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + stm32f4xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + stm32f4xx_hal_spi.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + stm32f4xx_hal_tim.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + stm32f4xx_hal_tim_ex.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + stm32f4xx_hal_uart.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 33 + 1 + 0 + 0 + 0 + ../Core/Src/system_stm32f4xx.c + system_stm32f4xx.c + 0 + 0 + + + + + Middlewares/FreeRTOS + 0 + 0 + 0 + 0 + + 5 + 34 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c + croutine.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c + event_groups.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/list.c + list.c + 0 + 0 + + + 5 + 37 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/queue.c + queue.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c + stream_buffer.c + 0 + 0 + + + 5 + 39 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c + tasks.c + 0 + 0 + + + 5 + 40 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/timers.c + timers.c + 0 + 0 + + + 5 + 41 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c + cmsis_os2.c + 0 + 0 + + + 5 + 42 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + heap_4.c + 0 + 0 + + + 5 + 43 + 1 + 0 + 0 + 0 + ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c + port.c + 0 + 0 + + + + + bsp + 1 + 0 + 0 + 0 + + 6 + 44 + 1 + 0 + 0 + 0 + ..\User\bsp\can.c + can.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\User\bsp\gpio.c + gpio.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\User\bsp\i2c.c + i2c.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\User\bsp\mm.c + mm.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\User\bsp\spi.c + spi.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\User\bsp\uart.c + uart.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\User\bsp\time.c + time.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\User\bsp\pwm.c + pwm.c + 0 + 0 + + + + + component + 1 + 0 + 0 + 0 + + 7 + 52 + 1 + 0 + 0 + 0 + ..\User\component\ahrs.c + ahrs.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\User\component\capacity.c + capacity.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\User\component\crc8.c + crc8.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\User\component\crc16.c + crc16.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\User\component\error_detect.c + error_detect.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\User\component\filter.c + filter.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\User\component\freertos_cli.c + freertos_cli.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\User\component\limiter.c + limiter.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\User\component\mixer.c + mixer.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ..\User\component\pid.c + pid.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\User\component\ui.c + ui.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\User\component\user_math.c + user_math.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\User\component\cmd.c + cmd.c + 0 + 0 + + + + + device + 1 + 0 + 0 + 0 + + 8 + 65 + 1 + 0 + 0 + 0 + ..\User\device\bmi088.c + bmi088.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\User\device\ist8310.c + ist8310.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\User\device\motor.c + motor.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\User\device\motor_rm.c + motor_rm.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\User\device\motor_dm.c + motor_dm.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + ..\User\device\ai.c + ai.c + 0 + 0 + + + 8 + 71 + 1 + 0 + 0 + 0 + ..\User\device\dr16.c + dr16.c + 0 + 0 + + + + + task + 1 + 0 + 0 + 0 + + 9 + 72 + 1 + 0 + 0 + 0 + ..\User\task\init.c + init.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + ..\User\task\ai.c + ai.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + ..\User\task\atti_esti.c + atti_esti.c + 0 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + ..\User\task\chassis_ctrl.c + chassis_ctrl.c + 0 + 0 + + + 9 + 76 + 1 + 0 + 0 + 0 + ..\User\task\dr16.c + dr16.c + 0 + 0 + + + 9 + 77 + 1 + 0 + 0 + 0 + ..\User\task\gimbal_ctrl.c + gimbal_ctrl.c + 0 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + ..\User\task\shoot_ctrl.c + shoot_ctrl.c + 0 + 0 + + + 9 + 79 + 1 + 0 + 0 + 0 + ..\User\task\user_task.c + user_task.c + 0 + 0 + + + 9 + 80 + 1 + 0 + 0 + 0 + ..\User\task\remote.c + remote.c + 0 + 0 + + + + + module + 1 + 0 + 0 + 0 + + 10 + 81 + 1 + 0 + 0 + 0 + ..\User\module\config.c + config.c + 0 + 0 + + + 10 + 82 + 1 + 0 + 0 + 0 + ..\User\module\chassis.c + chassis.c + 0 + 0 + + + 10 + 83 + 1 + 0 + 0 + 0 + ..\User\module\gimbal.c + gimbal.c + 0 + 0 + + + 10 + 84 + 1 + 0 + 0 + 0 + ..\User\module\remote_cmd.c + remote_cmd.c + 0 + 0 + + + 10 + 85 + 1 + 0 + 0 + 0 + ..\User\module\shoot.c + shoot.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/MDK-ARM/Infantry.uvprojx b/MDK-ARM/Infantry.uvprojx new file mode 100644 index 0000000..9fb2ca8 --- /dev/null +++ b/MDK-ARM/Infantry.uvprojx @@ -0,0 +1,2232 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Infantry + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 6160000::V6.16::ARMCLANG + 1 + + + STM32F407IGHx + STMicroelectronics + Keil.STM32F4xx_DFP.2.17.1 + https://www.keil.com/pack/ + IRAM(0x20000000-0x2001BFFF) IRAM2(0x2001C000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") TZ + + + + 0 + + + + + + + + + + + $$Device:STM32F407IGHx$CMSIS\SVD\STM32F407.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + Infantry\ + Infantry + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 1 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1c000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1c000 + + + 0 + 0x2001c000 + 0x4000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32F407xx + + ../Core/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../Middlewares/Third_Party/FreeRTOS/Source/include;../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2;../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F;../User;../User/bsp;../User/component;../User/task;../User/module;../User/device + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + ../Drivers/CMSIS/Include + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32f407xx.s + 2 + startup_stm32f407xx.s + + + + + Application/User/Core + + + main.c + 1 + ../Core/Src/main.c + + + gpio.c + 1 + ../Core/Src/gpio.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + freertos.c + 1 + ../Core/Src/freertos.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + can.c + 1 + ../Core/Src/can.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + dma.c + 1 + ../Core/Src/dma.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c.c + 1 + ../Core/Src/i2c.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + spi.c + 1 + ../Core/Src/spi.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tim.c + 1 + ../Core/Src/tim.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usart.c + 1 + ../Core/Src/usart.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_it.c + 1 + ../Core/Src/stm32f4xx_it.c + + + stm32f4xx_hal_msp.c + 1 + ../Core/Src/stm32f4xx_hal_msp.c + + + + + Drivers/STM32F4xx_HAL_Driver + + + stm32f4xx_hal_can.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_rcc.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c + + + stm32f4xx_hal_rcc_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c + + + stm32f4xx_hal_flash.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c + + + stm32f4xx_hal_flash_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c + + + stm32f4xx_hal_flash_ramfunc.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c + + + stm32f4xx_hal_gpio.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c + + + stm32f4xx_hal_dma_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c + + + stm32f4xx_hal_dma.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c + + + stm32f4xx_hal_pwr.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c + + + stm32f4xx_hal_pwr_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c + + + stm32f4xx_hal_cortex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c + + + stm32f4xx_hal.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c + + + stm32f4xx_hal_exti.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c + + + stm32f4xx_hal_i2c.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_i2c_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_spi.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_tim.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_tim_ex.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32f4xx_hal_uart.c + 1 + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + Drivers/CMSIS + + + system_stm32f4xx.c + 1 + ../Core/Src/system_stm32f4xx.c + + + + + Middlewares/FreeRTOS + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 4 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 1 + + + + + + + + + + + + croutine.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/croutine.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + event_groups.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + list.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/list.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + queue.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/queue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stream_buffer.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tasks.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/tasks.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + timers.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/timers.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + cmsis_os2.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + heap_4.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + port.c + 1 + ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + bsp + + + can.c + 1 + ..\User\bsp\can.c + + + gpio.c + 1 + ..\User\bsp\gpio.c + + + i2c.c + 1 + ..\User\bsp\i2c.c + + + mm.c + 1 + ..\User\bsp\mm.c + + + spi.c + 1 + ..\User\bsp\spi.c + + + uart.c + 1 + ..\User\bsp\uart.c + + + time.c + 1 + ..\User\bsp\time.c + + + pwm.c + 1 + ..\User\bsp\pwm.c + + + + + component + + + ahrs.c + 1 + ..\User\component\ahrs.c + + + capacity.c + 1 + ..\User\component\capacity.c + + + crc8.c + 1 + ..\User\component\crc8.c + + + crc16.c + 1 + ..\User\component\crc16.c + + + error_detect.c + 1 + ..\User\component\error_detect.c + + + filter.c + 1 + ..\User\component\filter.c + + + freertos_cli.c + 1 + ..\User\component\freertos_cli.c + + + limiter.c + 1 + ..\User\component\limiter.c + + + mixer.c + 1 + ..\User\component\mixer.c + + + pid.c + 1 + ..\User\component\pid.c + + + ui.c + 1 + ..\User\component\ui.c + + + user_math.c + 1 + ..\User\component\user_math.c + + + cmd.c + 1 + ..\User\component\cmd.c + + + + + device + + + bmi088.c + 1 + ..\User\device\bmi088.c + + + ist8310.c + 1 + ..\User\device\ist8310.c + + + motor.c + 1 + ..\User\device\motor.c + + + motor_rm.c + 1 + ..\User\device\motor_rm.c + + + motor_dm.c + 1 + ..\User\device\motor_dm.c + + + ai.c + 1 + ..\User\device\ai.c + + + dr16.c + 1 + ..\User\device\dr16.c + + + + + task + + + init.c + 1 + ..\User\task\init.c + + + ai.c + 1 + ..\User\task\ai.c + + + atti_esti.c + 1 + ..\User\task\atti_esti.c + + + chassis_ctrl.c + 1 + ..\User\task\chassis_ctrl.c + + + dr16.c + 1 + ..\User\task\dr16.c + + + gimbal_ctrl.c + 1 + ..\User\task\gimbal_ctrl.c + + + shoot_ctrl.c + 1 + ..\User\task\shoot_ctrl.c + + + user_task.c + 1 + ..\User\task\user_task.c + + + remote.c + 1 + ..\User\task\remote.c + + + + + module + + + config.c + 1 + ..\User\module\config.c + + + chassis.c + 1 + ..\User\module\chassis.c + + + gimbal.c + 1 + ..\User\module\gimbal.c + + + remote_cmd.c + 1 + ..\User\module\remote_cmd.c + + + shoot.c + 1 + ..\User\module\shoot.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + Infantry + 1 + + + + + diff --git a/MDK-ARM/Infantry/ExtDll.iex b/MDK-ARM/Infantry/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/MDK-ARM/Infantry/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/MDK-ARM/Infantry/Infantry.axf b/MDK-ARM/Infantry/Infantry.axf new file mode 100644 index 0000000..61ab963 Binary files /dev/null and b/MDK-ARM/Infantry/Infantry.axf differ diff --git a/MDK-ARM/Infantry/Infantry.build_log.htm b/MDK-ARM/Infantry/Infantry.build_log.htm new file mode 100644 index 0000000..753c50d --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.build_log.htm @@ -0,0 +1,67 @@ + + +
+
Vision Build Log

+
Tool Versions:

+IDE-Version: Vision V5.34.0.0
+Copyright (C) 2021 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 6 6, 6, LIC=P6F5U-SYSX6-RFKIZ-JT2D4-G39T1-9ZMPB
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Professional  Version: 5.34.0.0
+Toolchain Path:  D:\Keil_v5\ARM\ARMCLANG\Bin
+C Compiler:      ArmClang.exe V6.16
+Assembler:       Armasm.exe V6.16
+Linker/Locator:  ArmLink.exe V6.16
+Library Manager: ArmAr.exe V6.16
+Hex Converter:   FromElf.exe V6.16
+CPU DLL:         SARMCM3.DLL V5.34.0.0
+Dialog DLL:      DCM.DLL V1.17.3.0
+Target DLL:      CMSIS_AGDI.dll V1.32.13.0
+Dialog DLL:      TCM.DLL V1.48.0.0
+ 
+
Project:

+D:\yunha\git_gimbal\RM\Infantry\MDK-ARM\Infantry.uvprojx
+Project File Date:  01/09/2026
+
+
Output:

+*** Using Compiler 'V6.16', folder: 'D:\Keil_v5\ARM\ARMCLANG\Bin'
+Build target 'Infantry'
+Note: source file '..\User\bsp\can.c' - object file renamed from 'Infantry\can.o' to 'Infantry\can_1.o'.
+Note: source file '..\User\bsp\gpio.c' - object file renamed from 'Infantry\gpio.o' to 'Infantry\gpio_1.o'.
+Note: source file '..\User\bsp\i2c.c' - object file renamed from 'Infantry\i2c.o' to 'Infantry\i2c_1.o'.
+Note: source file '..\User\bsp\spi.c' - object file renamed from 'Infantry\spi.o' to 'Infantry\spi_1.o'.
+Note: source file '..\User\task\ai.c' - object file renamed from 'Infantry\ai.o' to 'Infantry\ai_1.o'.
+Note: source file '..\User\task\dr16.c' - object file renamed from 'Infantry\dr16.o' to 'Infantry\dr16_1.o'.
+compiling config.c...
+linking...
+Program Size: Code=54888 RO-data=1680 RW-data=832 ZI-data=126600  
+FromELF: creating hex file...
+"Infantry\Infantry.axf" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: ARM
+                http://www.keil.com/pack/ARM.CMSIS.5.7.0.pack
+                ARM.CMSIS.5.7.0
+                CMSIS (Cortex Microcontroller Software Interface Standard)
+   * Component: CORE Version: 5.4.0
+
+Package Vendor: Keil
+                https://www.keil.com/pack/Keil.STM32F4xx_DFP.2.17.1.pack
+                Keil.STM32F4xx_DFP.2.17.1
+                STMicroelectronics STM32F4 Series Device Support, Drivers and Examples
+
+
Collection of Component include folders:

+  .\RTE\_Infantry
+  D:\Keil_v5\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include
+  D:\Keil_v5\Arm\Packs\Keil\STM32F4xx_DFP\2.17.1\Drivers\CMSIS\Device\ST\STM32F4xx\Include
+
+
Collection of Component Files used:

+
+   * Component: ARM::CMSIS:CORE:5.4.0
+      Include file:  CMSIS\Core\Include\tz_context.h
+Build Time Elapsed:  00:00:02
+
+ + diff --git a/MDK-ARM/Infantry/Infantry.hex b/MDK-ARM/Infantry/Infantry.hex new file mode 100644 index 0000000..78d2d14 --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.hex @@ -0,0 +1,3561 @@ +:020000040800F2 +:10000000E8F8012085020008D56C00087D5C000836 +:10001000756B0008ED2000085190000800000000FA +:100020000000000000000000000000003173000824 +:10003000DD25000800000000416F00080D80000869 +:100040009F0200089F0200089F0200089F0200080C +:100050009F0200089F020008E12500089F02000897 +:100060009F020008ED250008F92500089F020008FE +:100070009D2200089F0200089F0200089F020008BE +:100080009F0200089F0200089F020008212100082B +:10009000F1200008012100081121000805260008B0 +:1000A0009F0200089F0200089F0200089F020008AC +:1000B0009F0200089F0200089F0200089F0200089C +:1000C0009F0200089F0200089F0200089F0200088C +:1000D0009F02000811900008299000089F02000864 +:1000E0009F0200089F0200089F0200089F0200086C +:1000F0009F0200089F0200089F0200089F0200085C +:100100009F0200089F0200089F0200089F0200084B +:100110009F0200089F0200089F0200089F0200083B +:100120009F0200089F020008AD220008BD220008BF +:100130009F0200089F0200089F020008512100084A +:100140009F02000831210008412100089F02000899 +:100150009F0200089F0200089F02000839900008D3 +:100160009F0200089F0200089F0200089F020008EB +:100170009F0200089F0200089F0200080000000084 +:100180009F0200089F02000800F002F800F06AF8E1 +:100190000AA090E8000C82448344AAF10107DA45E2 +:1001A00001D100F05FF8AFF2090EBAE80F0013F0CA +:1001B000010F18BFFB1A43F001031847FCDA0000D7 +:1001C0003CDB00000A444FF0000C10F8013B13F038 +:1001D000070408BF10F8014B1D1108BF10F8015BA0 +:1001E000641E05D010F8016B641E01F8016BF9D193 +:1001F00013F0080F1EBF10F8014BAD1C0C1B09D1EA +:100200006D1E58BF01F801CBFAD505E014F8016B5B +:1002100001F8016B6D1EF9D59142D6D370470000ED +:10022000103A24BF78C878C1FAD8520724BF30C822 +:1002300030C144BF04680C607047000000230024F4 +:1002400000250026103A28BF78C1FBD8520728BFE6 +:1002500030C148BF0B6070471FB50DF0B6FA1FBD27 +:1002600010B510BD00F062F91146FFF7F5FF08F078 +:10027000CFFF00F080F903B4FFF7F2FF03BC00F0FA +:1002800083F900000948804709480047FEE7FEE778 +:10029000FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE736 +:1002A00004480549054A064B70470000C580000810 +:1002B00089010008E0A80120E8F80120E0B8012049 +:1002C000E8D8012053EA020C00F069802DE9F04BD8 +:1002D0004FF00006002B1FBFB3FA83F503FA05F4B5 +:1002E00024FA05F65E4012BF1643B2FA82F502FA0E +:1002F00005F4C5F120051EBF22FA05FC44EA0C04F2 +:10030000203556EA044C4FEA144418BF641C4FF0E1 +:1003100000084FF00009904271EB030C39D300291B +:1003200019BFB1FA81F701FA07F6B0FA80F700FABF +:1003300007F6C7F120071EBF20FA07FC46EA0C06A5 +:100340002037B6FBF4FCA7EB0507103F07F01F0BA7 +:10035000CBF120062CFA06F60CFA0BFB44BFB34691 +:100360000026202FA4BF5E464FF0000B5BEA060C70 +:1003700008BF4FF0010B19EB0B0948EB0608ABFB6C +:10038000027C06FB02CC0BFB03CCC01B71EB0C0107 +:10039000C1E70B46024641464846BDE8F08B13B51F +:1003A000084318BF4FF0FF300146AFF30080BDE8AF +:1003B0001C407047032A40F2308010F0030C00F01C +:1003C000158011F8013BBCF1020F624498BF11F88F +:1003D00001CB00F8013B38BF11F8013BA2F1040248 +:1003E00098BF00F801CB38BF00F8013B11F00303C0 +:1003F00000F02580083AC0F0088051F8043B083A24 +:1004000051F804CBA0E80810F5E7121D5CBF51F8C5 +:10041000043B40F8043BAFF30080D20724BF11F83F +:10042000013B11F801CB48BF11F8012B24BF00F8A4 +:10043000013B00F801CB48BF00F8012B704710B515 +:10044000203AC0F00B80B1E81850A0E81850B1E88D +:100450001850A0E81850203ABFF4F5AF5FEA027CCC +:1004600024BFB1E81850A0E8185044BF18C918C0FC +:10047000BDE810405FEA827C24BF51F8043B40F89D +:10048000043B08BF7047D20728BF31F8023B48BF82 +:1004900011F8012B28BF20F8023B48BF00F8012BC0 +:1004A000704702F0FF0343EA032242EA024200F0EF +:1004B00002B84FF0000200B5134694469646203924 +:1004C00022BFA0E80C50A0E80C50B1F12001BFF40D +:1004D000F7AF090728BFA0E80C5048BF0CC05DF873 +:1004E00004EB890028BF40F8042B08BF704748BFC1 +:1004F00020F8022B11F0804F18BF00F8012B704735 +:1005000070477047704710B500F008F8006810BDDC +:1005100010B5044600F002F8046010BD00487047B2 +:100520004003002000487047400300207546FFF755 +:10053000F9FFAE4605006946534620F007008546A0 +:1005400018B020B5FFF7ACFEBDE820404FF0000624 +:100550004FF000074FF000084FF0000BAC46ACE83E +:10056000C009ACE8C009ACE8C009ACE8C00921F09A +:1005700007018D46704710B50446AFF30080204652 +:10058000BDE81040FFF777BE01491820ABBEFEE77B +:100590002600020070470000B0B52DED028B044626 +:1005A00000284FF0FF0061D00D4600295ED095ED88 +:1005B000000A95ED011A95ED022A95ED033A20EE19 +:1005C000010A22EE033A21EE011A22EE022A31EE4E +:1005D000021A30EE030A31EE011AB7EE008A30EE4D +:1005E000000A78EE410A0BF0CFFFB0EE401A95ED0D +:1005F000000A95ED012A95ED023A95ED034A20EEA9 +:10060000030A24EE022A30EE420A30EE000AB0EE6F +:10061000C02AB4EE482AF1EE10FA84ED011A02DA8B +:100620000BF0B0FC01E008F083FD84ED020A95EDCB +:10063000000A95ED011A95ED032A95ED023A20EE98 +:10064000020A21EE031A30EE010A23EE031A22EE0B +:10065000022A32EE011A31EE011A30EE000A78EE6B +:10066000410A0BF091FF002084ED000A40B2BDEC7E +:10067000028BB0BD70B52DED028B00284FD0B7EEC8 +:10068000001A81EE000A0D4604464FF07E51002DFF +:1006900080ED040A4FF00000C4E90010A060E060A3 +:1006A00000F09F80D5E900600CF0EEFF41EC180BE4 +:1006B00030460CF0E9FF41EC110BB0EE480AF0EEC9 +:1006C000680A0BF061FE51EC100B0CF011FB95ED7C +:1006D000000AB5EE400AF1EE10FA22D195ED010ABA +:1006E000B5EE400AF1EE10FA1BD195ED020AB5EE17 +:1006F000400AF1EE10FA14D140F2C560C3F64D7015 +:1007000044F62D214AF2564244F2AD73C3F60D4130 +:10071000CBF63932C3F619730FC4002061E0FF2015 +:100720005FE09FED321A00EE100AB4EE410AF1EEDE +:1007300010FA1EDCB5EE400AF1EE10FA19DB9FED5F +:100740002C2AB4EE420AF1EE10FA25DCB4EE410A8E +:10075000F1EE10FA20DB9FED271AB4EE410AF1EE1C +:1007600010FA2CDCB4EE420AF1EE10FA27DB00207E +:1007700037E045F66E10C3F67F7045F20C3148F64F +:10078000AB0249F28553C3F6B011CBF6BB32C3F6C8 +:1007900097530FC4002024E040F2C560C3F64D70AB +:1007A00044F62D214AF2564244F2AD73C3F60D4190 +:1007B000CBF63932C3F619730FC4002011E040F2B2 +:1007C000C560C3F64D7044F62D214AF2564244F2FC +:1007D000AD73C3F60D41CBF63932C3F619730FC4AE +:1007E000002040B2BDEC028B70BD00BFDB0FC9BF63 +:1007F000DB0F49C00000B4C20021C0E900118160D4 +:1008000070470000B0B52DED108B8EB00446002867 +:100810004FF0FF0018BF002904D140B20EB0BDEC6C +:10082000108BB0BD002AF8D040F204054EF69E7041 +:10083000C2F20005C3F627502860C3B193ED00EA69 +:1008400093ED01FAD3ED028AB5EE40EAF1EE10FA2B +:1008500011D1B5EE40FAF1EE10FA0CD1F5EE408A66 +:10086000F1EE10FA07D1204600F094FAD5E72046C1 +:1008700000F090FAD1E792ED000A92ED011A94EDA2 +:10088000014A94ED025A92ED022A94ED036A94ED26 +:10089000003A24EE407A61EE050A37EE607A62EEA5 +:1008A000060A37EE607A60EE030A62EE051A71EE10 +:1008B000A00A61EE061A70EEE10A61EE031A62EE1A +:1008C000042A22EE032A21EE041A91ED00DA71EED9 +:1008D000E21A20EE066A31EE021A20EE050A36EE22 +:1008E000216AD1ED019AD1ED02AA31EE400AB6EEAD +:1008F000001AB5EE40DA27EE015A60EE810A26EEC4 +:10090000017AF1EE10FA20EE016A0AD1F5EE409A72 +:10091000F1EE10FA05D1F5EE40AAF1EE10FA00F072 +:10092000EC812DEE0D0A29EEA91A30EE010A2AEE0D +:10093000AA1A30EE010A8DED0D6A8DED0C7ACDED1F +:100940000B0A8DED0A5A05F09BF92DEE001A8DED7C +:10095000071A29EE801A2AEE800A8DED081A8DED0D +:10096000090A2EEE0E0A2FEE0F1A30EE010A28EEBB +:10097000A81A30EE010A05F083F994ED001A6EEE24 +:1009800000DA6FEE00AA94ED034A31EE01EA68EE58 +:10099000808A94ED012A94ED023A2AEE8E6A61EE85 +:1009A00001EA8DED026A28EE8E0A2DEEAE5A26EE91 +:1009B000046A62EE02BA35EE465A20EE036A36EE5B +:1009C000055A2DEEAB6A32EE02FA36EE055A2AEEE1 +:1009D0008F6A23EE066A36EE055A28EE8F6A26EEF7 +:1009E000046A63EE03FA36EE055A2DEEAF6A24EE82 +:1009F000048A35EE465A2DEE886A2DEE8E9A35EE33 +:100A0000465A29EE046A2AEEAE7A37EE066A22EEDC +:100A1000000A2DEE8FAA36EE400A23EE0A6A36EE61 +:100A2000000A2AEEAB6A30EE460A2AEEAF6A73EE8F +:100A3000039A36EE000A28EEA96A24EE066A36EE1C +:100A4000000A2AEE886A30EE460A25EE055A20EEA4 +:100A5000000A35EE000A21EE02BA21EE035A21EE19 +:100A6000041A8DED051A22EE031A8DED031A23EEFA +:100A7000041A8DED041A34EE041A8DED015A22EE9B +:100A800004CA6EEE03CA8DED061A29EE84DA05F06B +:100A9000F7F894ED013A94ED022A9DED021A29EE41 +:100AA000024A21EE031A31EE444A94ED031A28EE6D +:100AB000AE5A35EE044A2AEE015A35EE044A28EEC3 +:100AC000AB5AF7EE001A34EE454A2AEEA95A81EEE7 +:100AD000800A25EE015A35EE044A28EEAF5A34EE6C +:100AE000454A28EE885A75EE042A3CEE0C4A9DEDE4 +:100AF000075A34EE6C4A34EE454A3BEE0B5A9DEDF4 +:100B0000086A35EE0D5A35EE465A2FEE056A29EE83 +:100B1000847AF6EE007A76EE470A37EEEF6A36EE22 +:100B2000486A9DED018A20EE066A3CEE487A27EE7F +:100B3000227A36EE076A36EE6D7A22EE226A66EE89 +:100B4000073A70EEE33ADDED050ADDED034A60EEAB +:100B5000015A74EEE00ADDED044A60EE200A7BEEF5 +:100B6000244A64EEA24A70EEA40A63EE224A70EEB2 +:100B7000EA0A74EEE56A66EEA06A77EEEB7A76EE44 +:100B8000A33A78EE0C6A77EEEF7A60EE266A67EEAB +:100B9000A27A76EEA76A76EEE86A60EE027ADDED7A +:100BA000068A27EEA68A38EE23CA68EE843A2EEE2D +:100BB000058A78EE233A3BEEAB8A71EEC81A3FEE17 +:100BC000AF8A71EEC81A9DED098A21EE22AA71EE54 +:100BD000C81AB1EE008A23EE089A21EE899A73EEC4 +:100BE000C93A94ED009A2AEE07BA73EE8B3A29EED1 +:100BF00022BA77EE8B7A67EEA07A72EEA22A77EEAF +:100C0000A33A63EE227A75EEE75A65EEA65A35EE00 +:100C1000A3DA68EE853A6EEE045A73EEE53A62EEB8 +:100C2000085A65EEA11A73EEE11AF8EE003A60EE8A +:100C3000233A62EE235A75EECB5A65EE875A20EEC0 +:100C4000033A71EEA51A73EE0A5A20EE090A22EE53 +:100C5000222A65EEA05A30EE422A75EEA11A22EE43 +:100C6000262A23EE811A32EE218A2FEE042A29EE5B +:100C7000854A31EE241A34EE022A21EE071A36EEA6 +:100C8000400A32EE011A20EE200A30EE010A23EE6D +:100C9000261A31EE009A2CEE0C0A2DEE0D1A30EECB +:100CA000010A28EE081A31EE000A29EE091A31EE7F +:100CB000000A04F0E5FF95ED004A9DED0A5A20EE8A +:100CC0000C1ADDED0B0A20EE0D2A24EE011A9DED23 +:100CD0000C7A9DED0D6A20EE083A20EE090A35EEF9 +:100CE000415A24EE021A70EEC10A24EE031A24EED1 +:100CF000000A37EE417A36EE406A94ED043A94EDFC +:100D0000000A94ED011A25EE035A94ED022A30EE02 +:100D1000050A20EE835A94ED034A35EE011A27EEB8 +:100D2000035A35EE022A26EE033A84ED000A84EDDA +:100D3000011A20EE000A21EE011A33EE043A30EED9 +:100D4000010A22EE021A30EE010A23EE031A30EEF7 +:100D5000010A84ED022A84ED033A04F091FF94ED38 +:100D6000001A94ED012A94ED023A94ED034A20EE24 +:100D7000011A20EE022A20EE033A20EE040A002097 +:100D800084ED001A84ED012A84ED023A84ED030A11 +:100D900043E50000B0B52DED108B044600284FF060 +:100DA000FF0018BF002900F06981002A00F0668169 +:100DB00040F2040542F60230C2F20005C3F60750C5 +:100DC000286092ED000A92ED011A94ED014A94ED2B +:100DD000025A92ED022A94ED036A94ED003A24EE51 +:100DE000407A61EE050A37EE607A62EE060A37EE67 +:100DF000607A60EE030A62EE051A71EEA00A61EEF7 +:100E0000061A70EEE10A61EE031A62EE042A22EE7F +:100E1000032A21EE041A91ED00CA71EEE21A20EEC7 +:100E2000066A31EE021A20EE050A36EE216A91EDCD +:100E300001DA91ED02EA31EE400AB6EE001AB5EEA3 +:100E400040CA27EE01BA20EE81AA26EE019AF1EE01 +:100E500010FA20EE018A0AD1B5EE40DAF1EE10FA6E +:100E600005D1B5EE40EAF1EE10FA00F0BC802CEEB0 +:100E70000C0A2DEE0D1A30EE010A2EEE0E1A30EE8F +:100E8000010A04F0FDFE94ED003A94ED025AF1EEF1 +:100E9000001A2CEE001A94ED014A75EE050A63EE75 +:100EA000212A65EE053A62EEA34A61EE205A74EEFD +:100EB000A54A64EE045A2DEE002A94ED036A34EE3E +:100EC000047A62EEA52A72EEA42A62EE074A32EE96 +:100ED000E4CA76EE062A64EE214A66EE066A64EEFD +:100EE000A67A21EE22DA77EECD7A23EE03DA2DEE22 +:100EF00021DA2EEE000A24EE0DEA33EE033A7EEEFE +:100F0000277A22EE03EA77EECE7AB2EE00EA24EEFA +:100F10000E4A77EEE47A24EE25FA7FEE277A24EE65 +:100F2000234A34EE274A60EE244A34EE84FA2DEE4A +:100F3000054A21EE033A33EE043A25EE0E4A25EE39 +:100F4000215A65EE264A33EE243A62EE222A33EE27 +:100F5000623A33EE453A65EE842A32EE833A24EE65 +:100F6000234A34EE033A20EE050A30EE03DA21EE8E +:100F7000070A25EEA11A21EE061A31EE400A23EEE9 +:100F8000A11A26EE011A30EE010A22EE201A30EEE6 +:100F900041EA2CEE0C0A2FEE0F1A30EE010A2DEE6C +:100FA0000D1A31EE000A2EEE0E1A31EE000A04F090 +:100FB00067FE95ED004A20EE0C1A20EE0F2A24EE73 +:100FC000011A20EE0D3A20EE0E0A3BEE41BA24EE55 +:100FD000021A3AEE41AA24EE031A24EE000A39EE70 +:100FE000419A38EE408A94ED043A94ED000A94ED6B +:100FF000011A2BEE035A94ED022A30EE050A2AEE6E +:10100000035A94ED034A35EE011A29EE035A35EEE0 +:10101000022A28EE033A84ED000A84ED011A20EE3C +:10102000000A21EE011A33EE043A30EE010A22EEF4 +:10103000021A30EE010A23EE031A30EE010A84EDA3 +:10104000022A84ED033A04F01BFE94ED001A94ED9D +:10105000012A94ED023A94ED034A20EE011A20EEA3 +:10106000022A20EE033A20EE040A002084ED001A42 +:1010700084ED012A84ED023A84ED030A40B2BDEC0E +:10108000108BB0BD70B50646044616F82B0F0D4602 +:101090004D2803D094F82C0052281AD130461D2137 +:1010A00001F08CF8A8B1F11C0A68CE68681CD1F870 +:1010B00004C08B68466002604A6994F82D608260C3 +:1010C0000969C3600161C0F814C0002040B22E70ED +:1010D00070BDFF2040B270BDB0B5044645F24D2052 +:1010E00020808869D1E90DECD1E91532254645F813 +:1010F000030FAB61C5F810E0EA61C5F814C0C86918 +:101100004FF6FF726860086AA860486A2921E860A3 +:101110000A20A4F827000020C4F28C102862204680 +:1011200001F03CF8A4F8290020462B2101F046F8F4 +:101130000138B0BD80B500F12B0102201D22012332 +:1011400000F07AFF002818BF4FF0FF3080BD00008C +:1011500080B5014602202B22012300F0A7FF0020CA +:1011600080BD0000B1EE601AB4EE600AF1EE10FA34 +:10117000B4EE401AC8BFB0EE600AF1EE10FAC8BF74 +:10118000B0EE410A7047000080B54DF20400C2F293 +:1011900001000068082108F0C5FA80BD80B54CF256 +:1011A0007812C2F2010200201221132300F086F906 +:1011B000002080BD80B5022001214FF0FF3208F0F1 +:1011C000F1FA80BD9FED010A704700BF0000C843DF +:1011D00080B54DF20400C2F201000068102108F051 +:1011E000A1FA80BD80B54CF27810C2F20100C21D98 +:1011F00001200221062300F061F9002080BD0000DB +:1012000080B5042001214FF0FF3208F0CBFA80BDF9 +:10121000F0B581B000284FF0FE0700F097800C4633 +:10122000002900F0938040F27476C2F20006054671 +:10123000307808B1FD2789E008F012FB4DF2040177 +:10124000C2F20101002808607BD000207E21B62276 +:10125000EC6200F085F901201421B62200F080F93B +:101260001E2000F067FE00201E2100F049F900203A +:10127000002100F045F91E2865D10120002101243C +:1012800000F03EF90F2860D10020002700F03EFD5D +:10129000002000F03BFD41F26D42C0F6000200204C +:1012A000012100F01DFE41F28911C0F6000100206D +:1012B00000F072FD41F2D111C0F60001002000F0F3 +:1012C0006BFD00204021AA2200F04AF900204121B4 +:1012D000012200F045F900205321082200F040F9D6 +:1012E00000205821042200F03BF900207D21042237 +:1012F00000F036F9322000F01DFE01200F210122FE +:1013000000F02EF901201021032200F029F901201C +:101310001621002200F024F901201821012200F0FA +:101320001FF901201521802200F01AF90A2000F08F +:1013300001FE0020347000F001FD002000F0FEFCF2 +:1013400004E0FE2702E0FC2700E0FC2778B201B0B1 +:10135000F0BD0000002841D04CF27811C2F201012A +:10136000B1F901209FED1F3A00EE102AB8EEC00A35 +:1013700080EE030AB1F90330B1F905C001EE103A6D +:1013800002EE10CAB8EEC11AB8EEC22A81EE031AF4 +:1013900082EE032A4FF60003CFF6FF7380ED040AB6 +:1013A0004A7C897CD20042EA51120021B1EB922F93 +:1013B00080ED051A80ED062A18BF1A4300EE102AA8 +:1013C000B8EEC00AB4EE001A20EE010AB3EE071A16 +:1013D00030EE010A80ED0A0A48B27047FE2148B299 +:1013E000704700BF00A0AA45C0B34CF27811C2F20A +:1013F0000101B1F90720B1F90930B1F90B1000EE84 +:10140000102A01EE103A9FED172A03EE101AB8EEDB +:10141000C00AB8EEC11AB8EEC33A80EE020A81EEF5 +:10142000021A83EE022A9FED103AC16A91ED014A39 +:1014300091ED025A20EE030A21EE031A22EE032A4E +:1014400091ED003A31EE441A30EE430A32EE452A6D +:1014500080ED070A80ED081A80ED092A6FF001007F +:10146000704700BF6F12034235FA8E3C10B5012061 +:1014700000F07CFC4DF20404C2F2010438B90120F2 +:10148000012100F0AFFC2068022108F04BF9012097 +:1014900000F06CFC002818BF10BD0120012100F0F5 +:1014A000A1FC2068042108F03DF910BD80B518208A +:1014B00001214FF0FF3208F075F980BD002A08BF06 +:1014C000704770B51C4615460E46012803D801200A +:1014D000002100F087FC40F2414146F08000C2F25A +:1014E0000001087000200122002300F009FD002007 +:1014F00029462246012300F0D9FCBDE87040704720 +:1015000070B5044601200D4600F014FD012C03D8EF +:101510000120002100F066FC45F0800040F24145CA +:10152000C2F200052E4606F8010B002029460122D2 +:10153000002300F0E5FC002029460222002300F0F1 +:10154000B5FC2CB1012C08D140F24146C2F2000694 +:101550000120012100F046FC3078C0B270BD0000CF +:1015600010B5044601F07F0040F24141C2F2000193 +:10157000087001204A7000F0DDFC012C03D8012026 +:10158000002100F02FFC40F24141C2F20001002096 +:101590000222002300F0B4FC012C88BF10BD012002 +:1015A000012100F01FFC10BD2DE9F04381B040F691 +:1015B0002808C2F200080646D8F8000014460D4676 +:1015C0006421002A08BF0A2408F016F808B1FB2499 +:1015D0002FE04CF6CC39C2F20109D9F8000000E046 +:1015E000006930B10178B142FAD14168A942F7D11E +:1015F0001AE0142000F00EFC88B1074620461C219A +:10160000002207F04FFFB86058B1D9F800003C73D2 +:1016100000243E707D603861C9F8007005E0FE244A +:1016200003E0384600F06EFBFF24D8F8000008F015 +:1016300059F860B201B0BDE8F083000070470000C7 +:101640004CF6CC32C2F20102126800E01269002AA4 +:1016500004BF0020704713788342F7D153688B4250 +:10166000F4D1906870470000D0E90212081FB0FA68 +:1016700080F14FF0020008BF0320022A18BF48097A +:10168000704700004CF2085240F28451C2F201024D +:101690000128C2F2000118BF0022002818BF11461D +:1016A000012888BF00210846704700002DE9F0415D +:1016B00015464CF2DC62C2F201021278012A11D105 +:1016C000A5B140F62808C2F200080746D8F8000085 +:1016D0000E4664211C4607F08FFF58B1FB2040B234 +:1016E000BDE8F081FD2040B2BDE8F081FE2040B2AF +:1016F000BDE8F08138463146FFF7A2FFD8F8001068 +:101700000646084607F0EEFF66B13046294600223D +:10171000234607F083FE002818BF4FF0FF3040B289 +:10172000BDE8F081FC2040B2BDE8F0812DE9F04732 +:101730008AB04CF2DC67C2F20107387808B1FD24A8 +:101740008AE040F2A030C2F200006821FEF7B1FE4C +:10175000002400BFE0B200F03BFA0134012CF9D0C4 +:101760004CF2D86041F23D61C2F20100C0F60001C6 +:1017700001600020002407F069FF40F62801C2F252 +:1017800000010028086066D0E8464FF00109404695 +:10179000282187F80090FEF78CFE40F28456C2F2B2 +:1017A00000064FF00E0A30464146CDE90244CDE92D +:1017B0000799CDF824A0049401F05AFC304602F0B9 +:1017C00037F841F6D902C0F600020020062100F0E9 +:1017D00051F841F66D35C0F60005002000212A467B +:1017E00000F048F8002001212A4600F043F80020CC +:1017F00002212A4600F03EF83046032101F0DAFBD0 +:101800004CF20856C2F2010630464146CDE9049A30 +:1018100001F02EFC304602F00BF841F69D12C0F6A6 +:1018200000020120082100F025F8012000212A46AD +:1018300000F020F8012001212A4600F01BF80120C9 +:1018400002212A4600F016F83046112101F0B2FBC1 +:1018500087F8009000E0FF2460B20AB0BDE8F0878E +:1018600080B54CF2D862C2F201021268002A18BF99 +:10187000904780BD4CF2DC63C2F201031B78012B60 +:101880001EBFFD2358B270473AB101284FF0FF0345 +:1018900098BF0C2904D958B27047FE2358B270473C +:1018A00040F2A03CC2F2000C342310FB03C0002322 +:1018B00040F8212058B2704780B54CF2DC63C2F288 +:1018C00001031B78012B03D1FFF76EFE40B280BDF0 +:1018D000FD2040B280BD00002DE9F04F93B003A879 +:1018E0000D3001904FF0000A0CAE002005E000BF63 +:1018F0000298002800F101004CD15FFA80FB0290B1 +:101900005846FFF7BFFE0028F2D0044609E000BFAA +:1019100002F0FEFA0990384603A90022002307F0DE +:1019200011FE2046002101F025FC0028E0D02046D1 +:10193000002132460AAB01F02DFC0028F1D10E98AF +:101940000028304618BF043005683046FFF78CFE8B +:10195000804628464146FFF783FF81465846494660 +:10196000FFF76EFE0028DCD00746DDE90F02CDF858 +:101970000CA00028CDE908AACDE906AA8DF80C80B4 +:10198000CDE904598DF81820C2D101980AA9FEF7B3 +:1019900011FDBDE713B0BDE8F08F00002DE9F04F59 +:1019A00093B003A80D3001904FF0000A0CAE002058 +:1019B00005E000BF0298002800F101004CD15FFA59 +:1019C00080FB02905846FFF75DFE0028F2D00446E7 +:1019D00009E000BF02F09CFA0990384603A90022F2 +:1019E000002307F0AFFD2046012101F0C3FB0028D2 +:1019F000E0D02046012132460AAB01F0CBFB0028A3 +:101A0000F1D10E980028304618BF043005683046E2 +:101A1000FFF72AFE804628464146FFF721FF814610 +:101A200058464946FFF70CFE0028DCD00746DDE9A2 +:101A30000F02CDF80CA00028CDE908AACDE906AA2E +:101A40008DF80C80CDE904598DF81820C2D1019889 +:101A50000AA9FEF7AFFCBDE713B0BDE8F08F0000A8 +:101A60002DE9F04389B017464CF2DC62C2F2010264 +:101A70001278012A04D10446012806D9FF2000E08B +:101A8000FD2040B209B0BDE8F08301F0FE001D4624 +:101A90000E46022802D00DB9FE20F2E7DDF84080A4 +:101AA000B8F1080F01D9FF20EBE72046FFF7EAFD68 +:101AB00098B181460020032E0890CDE90600CDE9BB +:101AC0000400CDE90200019009D8DFE806F0020A1F +:101AD0000D110197002100200DE0FE20D1E7FF202D +:101AE000CFE70297002005E001970220002102E0E5 +:101AF000022002970421CDE903100020002DCDF82B +:101B000014808DF8180018BFB8F1000F05D001A897 +:101B1000183029464246FEF74DFC484601F0CCFB02 +:101B200038B101A901F118026B46484601F056FA96 +:101B300028B101A9204600F0A5F80138A1E700204E +:101B40009FE7000079B180B582B00A6891F804C0BF +:101B50004B1D0021CDF800C0FFF782FF02B0BDE8A9 +:101B6000804040B27047FE2040B270472DE9F043FC +:101B700089B001AC04F118090025E84604E000BF73 +:101B8000002D05F1010520D1EFB23846FFF77AFDAF +:101B90000028F5D0064600BF384600F027F8002898 +:101BA000EED1304601F088FB0028E9D038462146C6 +:101BB00000F02EF80028E3D0304621464A4643463E +:101BC00001F00CFA0028E7D0DAE709B0BDE8F083AD +:101BD0004DF2080100EBC010C2F2010101EBC000A0 +:101BE0000021C0F80014C0F8041470474DF2080139 +:101BF00000EBC010C2F2010101EBC000D0F80014EC +:101C0000D0F80404081AB0FA80F0400970470000C8 +:101C1000002904BF002070472DE9F0414DF2080C67 +:101C200000EBC012C2F2010C0CEBC202D2F800E4CD +:101C3000D2F804349E451FD002F204452C6800EB14 +:101C4000C0100CEBC00000EB4412640150F804C05B +:101C5000D2E901805769D2E90364C1E900C8C1E94A +:101C60000447C1E90206D2E90620C1E90620286836 +:101C7000013000F01F002860BEEB030018BF0120F8 +:101C8000BDE8F08101284FF0000238D8B9B32DE942 +:101C9000F0474DF2080C00EBC012C2F2010C0CEB45 +:101CA000C202D2F80034D2F804E4013303F01F0377 +:101CB00073451ED002F58069D9F8004000EBC010D2 +:101CC0000CEBC00000EB44124FEA441AD1E904C601 +:101CD000D1E90078D1E9025440F80A705661C2E9AE +:101CE000034CC2E90185D1E90610C2E90610C9F822 +:101CF0000030B3EB0E0218BF0122BDE8F0471046DA +:101D00007047000080B508F081FC80BD05284FF0C9 +:101D1000FF0211D801460620DFE801F0080E0E038D +:101D200005070A2002E0172000E0092080B502F034 +:101D30006FFA0022BDE8804050B2704705284FF08E +:101D4000FF0211D801460620DFE801F0080E0E035D +:101D500005070A2002E0172000E0092080B502F004 +:101D60005BFA0022BDE8804050B27047062884BF6D +:101D70000020704780B54DF6C801C0F6000101EBA8 +:101D8000C002526831F83010104602F0B5F8013840 +:101D9000B0FA80F0400980BDB9B1062882BFFF20AB +:101DA00040B270474DF6C802C0F6000232F830C0AB +:101DB000002000232CFA00F2D20709D10E2B03F1E8 +:101DC000010300F10100F5D908E0FE2040B27047A0 +:101DD0004CF20802C2F2010242F82010002040B288 +:101DE00070470000062882BFFF2040B2704780B5D0 +:101DF0000A464DF6C801C0F6000101EBC0035B685E +:101E000031F83010184602F07DF80020BDE880401F +:101E100040B2704780B508F06DFA80BD00281EBF43 +:101E2000FF2040B27047B7EE001A40F26060B4EE97 +:101E3000410AC2F20000F1EE10FAC8BFB0EE410A4A +:101E400000689FED0C1AC16AB5EE400A0131F1EE4F +:101E500010FAB8BFB0EE410A01EE101AB8EE411AFE +:101E600020EE010ABCEEC00A80ED0D0A002040B24F +:101E7000704700BF0000000010B510B1FF2460B231 +:101E800010BD40F26060C2F200000021002403F0A7 +:101E9000DFFA60B210BD00004CF2F051C2F2010155 +:101EA000002818BF002108467047000070B510B127 +:101EB000FF2040B270BD1E4614460D46FFF7ECFFF2 +:101EC0000028F5D02946224616B102F02DFE02E088 +:101ED000142302F06FFD002818BF012040B270BD2E +:101EE000002A0FBFFE2040F20843C2F2000303EBBA +:101EF00040101CBF40F82120002040B27047000075 +:101F000070B510B1FF2040B270BD1E4614460D469C +:101F1000FFF7C2FF0028F5D02946224616B103F08C +:101F2000F1F802E0142302F099FE002818BF012006 +:101F300040B270BD70B5044607F006FA0546FF26AC +:101F400007F0E4F9411C05290BD80120884010F066 +:101F5000310F0BD110F0060F0AD0204601F0C6FE5B +:101F600011E06FF00041884218BF002670B270BDCA +:101F70004FF47A70B0FBF5F1B4FBF1F0A14288BFE9 +:101F8000012007F099F9002670B270BD2DE9F041EB +:101F900007F0DAF9044609F0F3FC4FF47A784EF2D0 +:101FA0001806B8FBF4F4CEF20006376804FB00F51F +:101FB00009F0E6FC60433168854208BF394656F8AF +:101FC000042C01FB08F10132B1FBF2F100FB08F037 +:101FD000401A00F57A700021BDE8F08103288FBF18 +:101FE000002040B201A151F82000704748C60120EE +:101FF00048C60120F006002090C6012080B582B0BE +:1020000001680A68D20614D5002201920A6801927A +:1020100049680191019906F075FE4CF2540100EBFC +:10202000C000C2F2010101EB8000006A002818BF65 +:10203000804702B080BD000070B5032802D9FF20A0 +:1020400040B270BD144602460D4600294FF0FE0016 +:1020500018BF002C01D140B270BD10461E46FFF7DC +:10206000BDFF294622461EB103F02CFD40B270BDD3 +:1020700003F03EFD40B270BD3AB103284FF0FF03BC +:1020800098BF082904D958B27047FE2358B2704748 +:102090004CF2540300EBC000C2F2010303EB8000DA +:1020A000002340F8212058B27047000070B5032883 +:1020B00002D9FF2040B270BD144602460D460029E9 +:1020C0004FF0FE0018BF002C01D140B270BD104689 +:1020D0001E46FFF783FF294622461EB103F046FD48 +:1020E00040B270BD03F088FD40B270BDFEE7000055 +:1020F00080B540F28450C2F2000001F0F1F880BDDA +:1021000080B540F28450C2F2000001F0E9F880BDD1 +:1021100080B540F28450C2F2000001F0E1F880BDC9 +:1021200080B540F28450C2F2000001F0D9F880BDC1 +:1021300080B54CF20850C2F2010001F0D1F880BD28 +:1021400080B54CF20850C2F2010001F0C9F880BD20 +:1021500080B54CF20850C2F2010001F0C1F880BD18 +:102160004FF0030160B146F200420068C4F2000281 +:1021700002F58063984208BF0121801A08BF01461A +:10218000C8B27047C2B251404DF62022C0F60002DC +:1021900032F8111081EA102070470000B0B551B13B +:1021A0000C46451E15F8011F90B2013CFFF7EAFFEF +:1021B000002C0246F6D11046B0BD000002293CBFFB +:1021C00000207047B0B50C4602394FF6FF72054645 +:1021D000FFF7E4FF04F00101294424F00102114457 +:1021E00031F8021C401AB0FA80F04009B0BD00007E +:1021F00090ED001AF5EE400AF1EE10FA31EE000A09 +:1022000010DDB4EE600AF1EE10FAA2BF30EE600A03 +:1022100080ED000A7047B5EE400AF1EE10FAB8BF43 +:1022200030EE200A80ED000A70470000B5EE401A3B +:10223000F1EE10FA30EE600AD8BF7047B6EE002A11 +:1022400021EE022AB4EE420AF1EE10FAC4BF30EEDB +:10225000410A7047B1EE422AB4EE420AF1EE10FA9A +:10226000B8BF30EE010A704790ED001AB4EE601A64 +:10227000F1EE10FAC8BFC0ED000A90ED001AB4EEFE +:10228000401AF1EE10FAB8BF80ED000A7047000066 +:1022900040F21400C2F200007047000080B54CF21A +:1022A0009050C2F2010001F0C1FB80BD80B54CF23C +:1022B0003050C2F2010001F0B9FB80BD80B540F2A0 +:1022C000AC50C2F2000001F0B1FB80BDD0F800C0FC +:1022D0006FF00F024AF6AB2352FA8CF2CAF6AA2329 +:1022E0000146A2FB0330000905A31B5C40F2FF304E +:1022F0002CEA00005F2A88BF0430C1E9160370474A +:1023000000061016000610168269816AB2F5005F99 +:1023100006D06AB9022912D0012914D0D1B90EE031 +:10232000032917D8DFE801F0020B020F01207047E4 +:1023300003293CBF012070471CBF00207047C06AC2 +:10234000C0F300607047C06AA0F1C070B0FA80F0BE +:10235000400970470020704780B5D0F800C0D0F821 +:1023600008E0DCF80000BEF1400F20F48020CCF83B +:1023700000000846CCF8043004BF10460A46CCF8EA +:102380000800CCF80C2080BDD0B101690A466FF37B +:10239000DF22A2F5B672B2F5A56F11D8C1F3CA2239 +:1023A000A2F5B672B2F5A56F0AD8808A890D41EA06 +:1023B00080216FF3DF21A1F5B671B1F5A56F01D9C9 +:1023C0000120704781B2C1F34A02A2F5B67200F44F +:1023D00040500023B2F5A56F4FF00002B0FA80F034 +:1023E00088BF0122B1F5804F38BF012343EA0201C3 +:1023F000400908437047000010B5E8B14CF2DD64B5 +:10240000C2F20104207810B1FD2040B210BD07F0E7 +:1024100027FA40F63001C2F20001086060B142F2D2 +:102420009152C0F6000203200321FFF725FE012090 +:102430002070002040B210BDFE2040B210BD000050 +:1024400010B538B1002400F8244B3421FEF731F8E0 +:1024500060B210BDFE2460B210BD000010B530B1F6 +:102460000446FFF791FF28B1FF2040B210BDFE20C7 +:1024700040B210BD01202070FFF788FDC4E90201C1 +:1024800004F124003421FEF714F82169A08AC1F375 +:10249000CA228B0D6FF3DF2100EE101A43EA802170 +:1024A0006FF3DF2104EE101AC0F34A019FED361AD4 +:1024B00003EE102A05EE101AB8EE400AB8EE433AC1 +:1024C000B8EE444AB8EE455A30EE012A9FED2F0A85 +:1024D00033EE013A34EE014A35EE015A32EE022A69 +:1024E00033EE033A34EE044A35EE055A82EE002A02 +:1024F00083EE003A84EE004A85EE005A820BA16911 +:1025000084F83920E28A94F81CC0C0F3013084F8C2 +:1025100038006287E163BCF1000F84ED0B2A84ED83 +:102520000C3A84ED094A84ED0A5A18BF4FF0010CA9 +:1025300094F81DE084F840C0BEF1000F18BF4FF0C2 +:10254000010EE28B04F14203002084F841E000BF59 +:1025500022FA00F101F00101195401301028F7D1DD +:10256000208C84F852C002EE100AB8EE422A32EEF5 +:10257000011A31EE011A81EE000A002040B284F8FF +:1025800053E084ED0D0A10BD000080C40000A54496 +:1025900080B540F63000C2F200000068012107F06B +:1025A000C1F880BD10B504460320FFF717FD04F104 +:1025B0001001122203F086FA002818BF4FF0FF30F6 +:1025C00010BD000080B502460120012107F0EAF8A5 +:1025D0000138B0FA80F0400980BD0000704700006B +:1025E00080B5012001F0ACFB80BD000080B5082063 +:1025F00001F0A6FB80BD000080B5102001F0A0FB1B +:1026000080BD000080B5202001F09AFB80BD000055 +:1026100072B600BFFEE70000B0B50D4691F8391064 +:102620000446012907D003290AD0022906D1002037 +:1026300020700020B0BD40F2012020800020B0BDFD +:102640000120208028696FF3DF20A0F580600AF068 +:10265000F8FD9FED130B53EC102B0AF01DFE9FEDC0 +:10266000120B53EC102B0AF029FC0AF041FB6060BE +:102670002869C0F3CA2010380AF0E3FD9FED0C0B67 +:1026800053EC102B0AF008FE9FED0B0B53EC102BB4 +:102690000AF014FC0AF02CFBA0600020B0BD00BFC3 +:1026A0009A9999999999E93F0000000000A0844007 +:1026B000333333333333E33F000000000000844002 +:1026C00070B52DED0E8B044600284FF0FF0000F092 +:1026D000B6810D46002900F0B281FFF757FCD4E91E +:1026E0000023801A99410AF0FAFF9FEDD70A01EE04 +:1026F000100A81EE000A84ED020AFFF747FC2A78EF +:10270000C4E900012046114600F05CFB204606F0BB +:10271000A1FD94ED02DA95ED010A95ED02EA04F5CA +:102720003B7004F52D7120EE0DAA06F0A3FD94ED8B +:10273000141AB0EE408A9FEDC59A94ED740A38EEF3 +:10274000011A7AEE010AB0EE491AFFF76FFD94ED17 +:10275000141AB0EE40BA94ED750A38EE011A7AEE0A +:10276000010AB0EE491AFFF761FD607C02280BD028 +:10277000012800F0AC80002840F048810020C4E926 +:102780009800C4F8680241E19FEDB09A04F5F27533 +:102790002846B0EE4A0AF0EE490AFFF729FD94ED0B +:1027A000790A9FEDAB1AB4EE410AF1EE10FA05DD9D +:1027B0009FEDA82A30EE020A85ED000A95ED003A59 +:1027C0009FEDA52AB1EE484AB4EE423AF1EE10FA76 +:1027D000BCBF33EE093A85ED003A9FED9E3AB4EE68 +:1027E000428A33EE485AF1EE10FAB8BFB0EE454ACD +:1027F000B4EE424A94ED796A34EE095AF1EE10FAD9 +:10280000B8BFB0EE454A34EE064AB4EE414A34EE63 +:10281000033AF1EE10FAC8BFB0EE434AB4EE424AB2 +:1028200034EE091AF1EE10FAB8BFB0EE414AE06892 +:1028300094ED151A417A2DEE0E0A30EE010A84ED60 +:10284000144A84ED150A39B1D0ED480A90ED490AD1 +:1028500004F15400FFF708FDD4ED021A94ED130AB9 +:10286000D4EDB70A94EDB81A04F1680004F04AFAFE +:102870009FED7AAA84ED980AD4ED021AD4ED0D0AE0 +:1028800094ED140A04F1E000B0EE4A1A04F03AFAAA +:10289000D4ED021AD4ED0A0A04F58E70B0EE4A1A8D +:1028A000B0EE408A04F02EFA84ED990AD4ED021AB3 +:1028B000D4ED0C0A94ED150A04F5AC70B0EE4A1A8A +:1028C00004F020FAD4ED021AD4ED090A73E0204690 +:1028D0002946B0EE40CA04F1500600F0C1F8E068A5 +:1028E000007A38B13046B0EE4C0AF0EE4B0AFFF7F2 +:1028F000BBFC1BE096ED000A9FED551AB4EE410AB1 +:10290000F1EE10FA05DD9FED531A30EE010A86ED67 +:10291000000A96ED000A9FED501AB4EE410AF1EE5E +:1029200010FABCBF30EE090A86ED000AE068417A71 +:1029300039B1D0ED480A90ED490A04F15400FFF78F +:1029400093FCD4ED021A94ED130AD4EDBB0A94ED76 +:10295000BC1A04F1680004F0D5F99FED40AA84ED9B +:10296000980AD4ED021AD4ED0D0A94ED140A04F17C +:10297000E000B0EE4A1A04F0C5F9D4ED021AD4ED25 +:102980000A0A04F58E70B0EE4A1AB0EE408A04F0DE +:10299000B9F984ED990AD4ED021AD4ED0C0A94ED3C +:1029A000150A04F5AC70B0EE4A1A04F0ABF9D4ED98 +:1029B000021AD4EDAB0AB0EE409A04F5CA70B0EE3C +:1029C0004A1A04F09FF9E06884ED9A0A90F80C1115 +:1029D00069B194EDAC2A90ED441A94ED993A38EE31 +:1029E000422A21EE021A33EE011A84ED991A90F868 +:1029F0000D1159B194EDAA1A90ED452A39EE411AFC +:102A000022EE011A30EE010A84ED9A0A94ED980A3A +:102A100004F5F67003F056F984ED980A94ED990ADE +:102A200004F5037003F04EF984ED990A94ED9A0AC7 +:102A300004F50B7003F046F9002084ED9A0A40B2C9 +:102A4000BDEC0E8B70BD00BF00247449DB0FC94084 +:102A5000DB0F4940DB0FC9C0DB0F49C0000000009D +:102A600000284FF0FF0218BF002901D150B2704773 +:102A70004A78022A19D0AAB991ED010A91ED021AF9 +:102A800090ED022A90ED143A90ED154A20EE020ADC +:102A900022EE011A33EE000A34EE011A80ED140A18 +:102AA00080ED151A002250B27047CA6802650969A4 +:102AB0000022416550B27047002808BF7047C168C6 +:102AC00091F80321022A05D0012A08D05AB990EDC5 +:102AD000AE0A06E090EDAF0AB1EE400A01E090EDDB +:102AE000AD0A80ED0C0A91F80421022A05D0012AD2 +:102AF00006D04AB900F52E7204E000F52F7201E00D +:102B000000F52D721268426391F80021022A05D067 +:102B1000012A06D04AB900F52A7204E000F52C72A9 +:102B200001E000F52B721268426291F8011102294E +:102B300005D0012906D049B900F52A7104E000F555 +:102B40002C7101E000F52B710968816200F5307C81 +:102B50009CE80E103C3080E80E10704710B52DED4B +:102B6000028B002800F094800446C160002060744D +:102B700004F1680001F160020121B0EE408A04F026 +:102B800079F9E16804F1A40001F140020121B0EEFD +:102B9000480A04F06FF9E16804F1E00001F1A002D5 +:102BA0000121B0EE480A04F065F9E16804F58E7081 +:102BB00001F180020121B0EE480A04F05BF9E168FE +:102BC00004F5AC7001F1E0020121B0EE480A04F016 +:102BD00051F9E16804F5CA7001F1C0020121B0EEBB +:102BE000480A04F047F9E06890ED4D0A90ED4E1A5E +:102BF000D0ED460A30EE011A84ED750A04F5F67040 +:102C0000B0EE480A84ED741A03F09AF8E068B0EE6A +:102C1000480AD0ED460A04F5037003F091F8E06825 +:102C2000B0EE480AD0ED460A04F50B7003F088F8C0 +:102C3000FEF77CFDE068817A012902D1163003F0AD +:102C40002FFCE068817A31B90E3003F005FAE068B4 +:102C50000E3003F013F9E068017B012902D1363010 +:102C600003F01EFCE068C17A012902D12E3003F086 +:102C700017FCE068017B31B9263003F0EDF9E0681C +:102C8000263003F0FBF8E068C17A19B1002009E0B2 +:102C9000FF2007E01E3003F0DFF9E0681E3003F08C +:102CA000EDF8002040B2BDEC028B10BD10B504461B +:102CB000C068817A012908D1163003F019FBE06859 +:102CC00094ED980A163003F047FCE068817AE1B988 +:102CD000D0F8481194ED980AC4F87412D0F8501145 +:102CE000C4F87C12D0F84C11C4F87812D0F8441112 +:102CF000C4F8701290ED5F1A04F51B7120EE010A02 +:102D00000E3084ED9B0A03F013F9E068017B012982 +:102D100008D1363003F0ECFAE06894ED990A3630C9 +:102D200003F01AFCE068C17A012908D12E3003F0C3 +:102D3000DFFAE06894ED9A0A2E3003F00DFCE068AB +:102D4000C17AE1B9D0F8701194ED9A0AC4F89C12D6 +:102D5000D0F87811C4F8A412D0F87411C4F8A012F5 +:102D6000D0F86C11C4F8981290ED611A04F5257131 +:102D700020EE010A1E3084EDA50A03F0D9F8E068C0 +:102D8000017B002918BF10BDD0F85C1194ED990AA1 +:102D9000C4F88812D0F86411C4F89012D0F8601109 +:102DA000C4F88C12D0F85811C4F8841290ED601A4F +:102DB00004F5207120EE010A263084EDA00A03F00C +:102DC000B7F810BDB0B52DED028BC8B30446407CFA +:102DD0000D46884234D004F1680004F093F804F101 +:102DE000A40004F08FF804F1E00004F08BF804F57F +:102DF0008E7004F087F804F5AC7004F083F804F5E5 +:102E0000CA7004F07FF89FED108A04F5F670B0EEFA +:102E1000480A02F0E7FF04F50370B0EE480A02F03A +:102E2000E1FF04F50B70B0EE480A02F0DBFF04F19D +:102E30005000FDF7E1FCD4E9AD016574C4E914016B +:102E4000BDEC028BB0BD00BF0000000010B5002833 +:102E500000F085800446C068817A012911D11630BE +:102E600003F0CAFBE068163003F0E0FA48B100F165 +:102E700008030ECB406904F5377C8CE80E00C4F8DB +:102E8000E802E068817A89B90E3003F0C3F9E0689E +:102E90000E3003F021F848B100F11C030ECB806A1C +:102EA00004F5377C8CE80E00C4F8E802E068017B8A +:102EB000012911D1363003F09FFBE068363003F072 +:102EC000B5FA48B100F108030ECB406904F53B7C2C +:102ED0008CE80E00C4F8F802E068C17A012911D12B +:102EE0002E3003F089FBE0682E3003F09FFA48B1E2 +:102EF00000F108030ECB406904F53F7C8CE80E001E +:102F0000C4F80803E068017B89B9263003F082F930 +:102F1000E068263002F0E0FF48B100F11C030ECB60 +:102F2000806A04F53B7C8CE80E00C4F8F802E06887 +:102F3000C17A89B91E3003F06DF9E0681E3002F0E5 +:102F4000CBFF48B100F11C030ECB806A04F53F7C37 +:102F50008CE80E00C4F80803002040B210BDFF202A +:102F600040B210BD10B380B58B68D1E900C2C0F883 +:102F7000B032C0E9AAC24B69D1E903C2C0F8BC3281 +:102F8000C0E9ADC201F1280C9CE80C1000F5347EBC +:102F90008EE80C10D1E906C3D1E90821C0E9B0C31D +:102FA000C0E9B221FFF788FDBDE880404FF0FF3057 +:102FB0007047000090F82020013A012A04D80068E8 +:102FC00000F11402002004E000F1240201204FF47B +:102FD00080211368194311607047000010B590F804 +:102FE00020E0D0F800C0AEF1010EBEF1010FDCF818 +:102FF00008E00ED81EF0E05F11D0CEF3016E012084 +:1030000000FA0EF018608B687BB1486843EAC00391 +:103010000DE000F1240101204FF4802223E000F1B3 +:10302000240101204FF400121DE008684305D1E996 +:10303000030403430CEB0E10C0F88031C0F8844148 +:10304000097D012905D100F5C2710B6843F4807335 +:103050000B605168C0F88C11126800F5C071C0F89F +:103060008821002001220B681A430A6010BD00006D +:10307000B0B590F82020013A012A2FD846F200601E +:10308000C4F20000026842F001020260026822F409 +:103090007C520260D1F814E0CC694A6A0368012CC2 +:1030A00043EA022202600EF01F024FF0010303FA0E +:1030B00002F2C3696FEA020C23EA0203C36113D070 +:1030C0002CBBC36803EA0C03C360CB688C8844EA5A +:1030D000034300EBCE0423640B4611E0416A41F444 +:1030E000802141620120B0BDC3681343C3600B68F7 +:1030F0008C8844EA034300EBCE04236401F10C0303 +:103100008C681B8843EA044300EBCE046364436885 +:103110008D6943EA0204D1F810E0096A002D08BF66 +:1031200003EA0C0444604369BEF1000F43EA020461 +:1031300008BF03EA0C040129446102D1C1691143AB +:10314000C161016821F0010101600020B0BD0000F3 +:1031500080B5FFF705F8032808BF80BD40F2A03115 +:10316000C2F20001342210FB0210006B002818BFCD +:10317000804780BD90F82020013A012A84BF0020BA +:10318000704700681022002908BF0C22805800F008 +:103190000300704710B590F82040013C012C0AD87C +:1031A000046871B12469A4070ED100F12401012043 +:1031B0004FF4001276E000F1240101204FF4802248 +:1031C00070E0E468A40771D0046804EB011CDCF82B +:1031D000B0410CF5D87E14F004049460DCF8B041E2 +:1031E00019BFE4085460640D1460DEF800400CF56B +:1031F000DA7E04F00204D460DCF8B44124075ABF3C +:10320000DEF8004004F00F0408241461DEF80040EA +:103210000029C4F307249461DEF800404FEA144407 +:103220005461DCF8B8211A70026802EB0112D2F87E +:10323000B8214FEA12225A70026802EB0112D2F84A +:10324000B8214FEA12429A70026802EB0112D2F8DA +:10325000B8214FEA1262DA70026802EB0112D2F86A +:10326000BC211A71026802EB0112D2F8BC214FEAAC +:1032700012225A71026802EB0112D2F8BC214FEA05 +:1032800012429A71026802EB0112D2F8BC214FEA95 +:103290001262DA71006814BF00F1100100F10C0134 +:1032A000002020220B681A430A6010BD00F124019F +:1032B00001204FF40012F5E790F8201001390129A0 +:1032C00084BF002070470068816882688068C1F30D +:1032D0008061C2F3C0621144C0F3007008447047BB +:1032E0002DE9F04F81B0044600684669D0F804909B +:1032F0008768D0F80CB0D0F810A0D0F81880F1078B +:1033000003D1002530071CD423E0F90710D0012198 +:10331000BA07816009D4780700F1AA80380700F164 +:10332000B080204600F0B2FA02E0204600F0C0FA79 +:103330000025F80500F18480F80300F1AA80300729 +:1033400007D51BF0100004D0206845F4007510214B +:10335000C160700708D51BF0080005D0206808215F +:10336000C160204600F00AFAB00706D52068C068A0 +:10337000800702D0204600F013FA700607D51AF035 +:10338000100004D0206845F4806510210161B0066A +:1033900008D51AF0080005D02068082101612046F0 +:1033A00000F010FAF00606D520680069800702D008 +:1033B000204600F019FAB00308D519F0100005D026 +:1033C000206810214160204600F020FAF00308D563 +:1033D00019F0080005D0206808214160204600F05F +:1033E000C1FA300440F18F805FEA497040F1888073 +:1033F00006F4807008EA102028435FEA88710146CD +:1034000048BF41F00201B20558BF01465FEA48706B +:103410000D4648BF45F00405700558BF0D46300500 +:103420006ED518F070006BD010380009052862D8EE +:10343000DFE800F0035356595C5F45F008055AE099 +:1034400020684FF48071BA0581600AD4780512D4DF +:10345000380519D4204600F03DFAF8037FF56FAF28 +:1034600017E0204600F048FAF8037FF568AF10E057 +:103470004FF400655DE705F50055F8037FF55FAF94 +:1034800007E04FF4805554E705F58045F8037FF5D4 +:1034900056AF20684FF48031BA0381600AD47803B4 +:1034A0000FD4380313D4204600F038FA30073FF524 +:1034B00048AF4EE7204600F043FA30073FF541AFF2 +:1034C00047E705F5004530073FF53BAF41E705F518 +:1034D000803530073FF535AF3BE745F010050AE092 +:1034E00045F0200507E045F0400504E045F0800583 +:1034F00001E045F480752068816921F070018161E7 +:103500002068042141602DB1606A28436062204632 +:10351000FFF71EFE01B0BDE8F08F0000B0B5C8B1E6 +:10352000044690F8200010B9204600F071F8206899 +:10353000016841F00101016000F0EAFC054600BFAE +:1035400020684168C90707D100F0E2FC401B0B2846 +:10355000F6D312E00120B0BD016821F00201016044 +:1035600000F0D6FC054600BF2068416889070DD5EC +:1035700000F0CEFC401B0B28F6D3606A052140F416 +:1035800000306062012084F82010B0BD217E026806 +:10359000012922F0800208BF80320260617E026849 +:1035A000012922F0400208BF40320260A17E026879 +:1035B000012922F0200208BF20320260E17E026869 +:1035C000012922F0100218BF10320260217F026828 +:1035D000012922F0080208BF08320260617F0268F8 +:1035E000012922F0040208BF04320260D4E901C2BA +:1035F000D4E9033561691A432A431143ACF101024E +:103600001143C16100200121606284F82010B0BD27 +:1036100070B586B0006846F60002C4F200020021D0 +:103620009042CDE90411CDE90211019148D046F252 +:103630000041C4F20001884240F09D804CF24801F4 +:10364000C2F201010A6843F64000C4F20200531CB2 +:103650000B6052B900210091016841F000710160D6 +:10366000016801F00071009100990021009150F86B +:10367000102C42F0080240F8102C50F8100C0222D6 +:1036800000F00800009000980320019004900920A9 +:10369000059040F20040C4F20200CDE9022100F59D +:1036A000006001A900F05AFB13200521002200F060 +:1036B000B7FD132000F0B0FD16241525142642E0B6 +:1036C00043F64000C4F202000091016841F08061BD +:1036D0000160016801F08061009100994CF248019D +:1036E000C2F201010A68531C0B6052B9002100911B +:1036F000016841F000710160016801F00071009102 +:1037000000990021009150F8102C42F0020240F87C +:10371000102C50F8100C00F00200009000984FF4AC +:10372000825001900220CDE902010320049009207B +:10373000059040F20040C4F2020001A900F00EFB27 +:10374000422441253F2630460521002200F068FD35 +:10375000304600F061FD28460521002200F060FDA2 +:10376000284600F059FD20460521002200F058FDB2 +:10377000204600F051FD06B070BD000080B5FEF798 +:10378000EFFC032808BF80BD40F2A031C2F2000167 +:10379000342210FB0210C069002818BF804780BD8A +:1037A00080B5FEF7DDFC032808BF80BD40F2A031E4 +:1037B000C2F20001342210FB02108069002818BFF9 +:1037C000804780BD80B5FEF7CBFC032808BF80BDD5 +:1037D00040F2A031C2F20001342210FB0210406A14 +:1037E000002818BF804780BD80B5FEF7B9FC0328CC +:1037F00008BF80BD40F2A031C2F20001342210FBAC +:103800000210006A002818BF804780BD80B5FEF70F +:10381000A7FC032808BF80BD40F2A031C2F200011E +:10382000342210FB0210806A002818BF804780BD38 +:10383000B0B5044690F8200001281DD1022084F87C +:1038400020002068016821F00101016000F060FBA8 +:10385000054600BF20684068C00713D000F058FB41 +:10386000401B0B28F6D3606A40F4003060620520EC +:1038700084F820000120B0BD606A40F4002060623E +:103880000120B0BD00206062B0BD000080B5FEF731 +:1038900067FC032808BF80BD40F2A031C2F20001DE +:1038A000342210FB0210C068002818BF804780BD7A +:1038B00080B5FEF755FC032808BF80BD342148437E +:1038C00040F2A031C2F200010858002818BF80471A +:1038D00080BD000080B5FEF743FC032808BF80BD13 +:1038E00040F2A031C2F20001342210FB0210006944 +:1038F000002818BF804780BD80B5FEF731FC032843 +:1039000008BF80BD40F2A031C2F20001342210FB9A +:1039100002104068002818BF804780BD80B5FEF7C0 +:103920001FFC032808BF80BD40F2A031C2F2000195 +:10393000342210FB02104069002818BF804780BD68 +:1039400080B5FEF70DFC032808BF80BD40F2A03112 +:10395000C2F20001342210FB02108068002818BF58 +:10396000804780BD80B5FEF7FBFB032808BF80BD04 +:1039700040F2A031C2F20001342210FB0210C06AF2 +:10398000002818BF804780BD70B5866D044600F0E2 +:10399000BFFA94F83510022925D105462068216C1C +:1039A000026822F016020260426922F0800242613F +:1039B00009B9A16C19B1016821F008010160016821 +:1039C00021F00101016000BF20680068C0070ED02F +:1039D00000F09EFA401B0628F6D3202060650320E5 +:1039E00084F835000CE080206065012008E0E06D7F +:1039F0003F2101FA00F0B060012084F8350000207A +:103A0000002184F8341070BD90F83510022909D1D6 +:103A1000052180F835100068016821F0010101607E +:103A2000002070478021416501207047F0B581B0CA +:103A300004460020009040F20000C2F2000002683C +:103A4000D4E9166048F2B51337680821C1F64E3341 +:103A500081403942A2FB03250CD0226813685B0722 +:103A600008D5136823F004031360B160616D41F061 +:103A70000101616501218140394208D02268526903 +:103A8000120604D5B160616D41F002016165042147 +:103A90008140394208D022681268920704D5B1608B +:103AA000616D41F00401616510218140394215D0FA +:103AB00020680268120711D5B160026801685203DC +:103AC00006D4C90506D4016821F00801016001E0AF +:103AD000080342D4216C09B120468847E16D2020BB +:103AE00000FA01F23A4244D020680368DB0640D570 +:103AF000B26094F835300268052B1ED122F0160210 +:103B00000260426922F080024261226C0AB9A26C12 +:103B10001AB1026822F0080202603F208840B060BB +:103B2000012084F83500216D0020002984F834003C +:103B300040D02046884701B0F0BD0168520310D440 +:103B4000C90512D4016821F010010160012084F838 +:103B50003500002084F8340007E0A16C0029BBD1B7 +:103B6000BCE7080301D4616C00E0E16B09B12046B9 +:103B70008847606DF0B1606DC00717D0052084F8EC +:103B800035002068A90A026822F00102026000BF25 +:103B9000009A01328A42009202D80268D207F7D115 +:103BA000012084F83500002084F83400E16C09B16C +:103BB0002046884701B0F0BD2DE9F041044600F0F1 +:103BC000A7F9C4B10546022084F835000020216819 +:103BD00084F83400086820F0010008602668306826 +:103BE000C0070BD000F094F9401B0528F6D903213B +:103BF0002022032042E00120BDE8F081306848F235 +:103C00003F01CFF21001251D00EA010C2ECDD4E9B1 +:103C1000050E41EA0C01114319432943D4E9077801 +:103C2000084340EA0E01606A3943042841EA08016A +:103C300003D1D4E90B23114319433160716904287E +:103C400021F0070141EA00050CD1D4E90A1045EA48 +:103C5000010538B12046FEF757FB18B1012140227B +:103C600001200BE020467561FEF730FBE16D3F223D +:103C700002FA01F18160002201210020626584F8CE +:103C80003510BDE8F0810000B0B5044690F834006E +:103C9000012828D0012084F83400A56D94F835005F +:103CA00001281DD1022084F83500002060652046DF +:103CB000FEF752FBE26D3F23206803FA02F2216C0B +:103CC000AA60026842F01602026019B1016841F070 +:103CD00008010160016841F0010101600020B0BDF0 +:103CE000002084F834000220B0BD0000B0B50446C6 +:103CF00000F00EF905464CF20000C2F20100007817 +:103D0000611C18BF044400BF00F002F9401BA04230 +:103D1000FAD3B0BD70B54CF2080604460025C2F2D5 +:103D2000010603E00135102D08BF70BD24FA05F02F +:103D3000C007F7D056F82500002818BF8047F1E7E4 +:103D400080B543F61441C4F201010A68024208BF7B +:103D500080BD0860FFF7DEFF80BD00002DE9F04F59 +:103D600083B000F13E4202F1FF724FEAB22241F607 +:103D700000470192C4F2020708224FF0010E00250D +:103D80004FF0000A4FF00008B84208BF0722009227 +:103D90000AE000BF08F101080AF1040AB8F1100FA7 +:103DA00005F1020500F0A4800C680EFA08FB14EA85 +:103DB0000B09EFD04C6804F0030CACF1010EBEF11E +:103DC000010F11D80322876802FA05F6CA68B743C3 +:103DD000AA403A4382604268C4F3001722EA0B0209 +:103DE00007FA08F73A434260BCF1030F1CD0C268DF +:103DF00003238E6803FA05F7BA4306FA05F73A4338 +:103E0000BCF1020FC2600FD16FF0030202EA580248 +:103E100002440AF01C060F23176A03FA06F40B6922 +:103E2000A743B3403B431362026803234F68AB4090 +:103E30009A4307F00303AB401A4317F4403F4FF097 +:103E4000010E0260A6D0002243F644030292C4F29F +:103E500002031A6843F6004442F480421A601A686A +:103E6000C4F2010402F480420292029A28F0030292 +:103E70004FF6084B2244CFF6FF7B52F80B300AF086 +:103E80000C070F26BE4023EA060C019B009E072B61 +:103E900038BF1E4606FA07F747EA0C0342F80B3014 +:103EA000A2684B6842EA090743F60C4CDE0258BF91 +:103EB00022EA0907A760C4F2010CDCF800209E0288 +:103EC00042EA090758BF22EA0907CCF80070626885 +:103ED0009E0342EA090758BF22EA09076760226881 +:103EE000DB0342EA090358BF22EA0903236051E7D2 +:103EF00003B0BDE8F08F00000069084018BF012042 +:103F000070470000002A08BF090481617047000063 +:103F10004DF61C00C2F2010000687047F0B581B098 +:103F2000B0B3044690F83D0028B9002084F83C0066 +:103F3000204600F0BFF8242084F83D002068016886 +:103F400021F001010160016841F400410160016854 +:103F500021F40041016000F02DFA48F28041C0F2E6 +:103F60001E0140F60012656888424FF00001C0F261 +:103F70003D0248F2A16C4FF0000338BF012190428E +:103F8000C0F2010C38BF0123654538BF0B4613B1A1 +:103F9000012001B0F0BD4DF68361C4F21B31A0FBDE +:103FA000011221684FEA924E4B684FF4967623F047 +:103FB0003F0343EA92434B6044F6D3530F6A0EFB30 +:103FC00006F6C1F26203A6FB033627F03F03B709EA +:103FD000654538BF970C7A1C1A430A62CA6948F2D1 +:103FE000A0674CF6FF73C0F20107BD4222EA030C42 +:103FF0000AD801386A00B0FBF2F001306FF31F30CD +:10400000042898BF04202BE0A368A0F1010E9BB107 +:1040100019206843BEFBF0F00422013062F31F3028 +:10402000000512D09BB119206843BEFBF0F00422BA +:10403000013062F31F3011E005EB4500BEFBF0F0EC +:1040400001306FF31F300005ECD1012008E005EBD3 +:104050004500BEFBF0F001306FF31F3040F400402C +:1040600040EA0C00C8610868D4E9072320F0C000CA +:10407000104318430860886848F2FF3204F10C07C7 +:1040800090438CCF18431043A6698860C86820F01D +:10409000FF0038433043C860086840F00100086002 +:1040A00000202021206484F83D10206384F83E0025 +:1040B00001B0F0BDB0B586B045F600010068C4F2AD +:1040C0000001002488420594CDE903440294019440 +:1040D00001D006B0B0BD43F630050094C4F202052D +:1040E0002868122240F020002860286800F0200094 +:1040F000009000980320019004900420059001F5A1 +:10410000DE3001A9CDE90224FFF728FE00942869DA +:1041100040F480002861286900F480000090009835 +:1041200006B0B0BD4CF200004DF61C01C2F2010019 +:10413000C2F2010100780A6810440860704700006C +:1041400080B543F60040C4F20200016841F40071FA +:104150000160016841F480610160016841F480718F +:104160000160032000F06CF80F2000F005F800F06B +:104170002BF8002080BD0000B0B54CF20002C2F266 +:10418000010240F200011278C2F200014FF47A738A +:104190000968B3FBF2F20446B1FBF2F1084601F004 +:1041A0005DF80F2C4FF001050CD858B94FF0FF30D7 +:1041B00021460022002500F033F840F23430C2F2EC +:1041C000000004602846B0BD80B582B0002043F6F0 +:1041D00040010190C4F202014A6842F480424A6000 +:1041E0004A6802F480420192019A00900868002215 +:1041F00040F08050086008680F2100F08050009067 +:1042000000986FF0010000F00BF802B080BD0000D4 +:1042100080B504F037FF80BD80B504F047FF80BD56 +:1042200070B514460D46064604F050FF2946224656 +:1042300002F052FD0146304604F050FF70BD000010 +:1042400080B504F065FF80BD2DE9F041002800F045 +:104250008B8043F60808C4F202080446D8F8F80335 +:104260000D4600F00700884207D288F8F853D8F8C6 +:10427000F80300F00700A84276D12068810717D51F +:10428000410705D5D8F8001041F4E051C8F80010F6 +:10429000010705D5D8F8001041F46041C8F80010B6 +:1042A000D8F80010A26821F0F0011143C8F80010FE +:1042B000C0073FD1D8F8F80300F00700A84207D99B +:1042C00088F8F853D8F8F80300F00700A8424BD15B +:1042D0002068410707D5D8F80010E26821F4E051C2 +:1042E0001143C8F80010000708D5D8F8000021696C +:1042F00020F4604040EAC100C8F8000000F07EF8F9 +:10430000D8F800104DF6B002C1F30311C0F6000258 +:10431000515C40F2000220FA01F140F23430C2F266 +:1043200000000068C2F200021160FFF725FF0020C4 +:10433000BDE8F0816068811E022907D258F8081C88 +:1043400089015CBF0120BDE8F08110E0012807D1A0 +:1043500058F8081C89035CBF0120BDE8F08106E025 +:1043600058F8081C890702D40120BDE8F081D8F86C +:10437000001021F003010843C8F80000FFF7C8FD52 +:10438000064641F2883700BFD8F80000616800F0A7 +:104390000C00B0EB810F8DD0FFF7BAFD801BB84247 +:1043A000F2D90320BDE8F08140F20000C2F2000023 +:1043B0000068704780B5FFF7F7FF43F60801C4F2C5 +:1043C000020109684DF6C002C1F38221C0F6000265 +:1043D000515CC84080BD000080B5FFF7E5FF43F6A3 +:1043E0000801C4F2020109684DF6C002C1F342316E +:1043F000C0F60002515CC84080BD000010B543F615 +:104400000404C4F20204606800F00C0008280AD01A +:10441000042819BF42F20040C0F2F40041F6003017 +:10442000C0F2B70010BD206821682368490241F638 +:104430000031C0F2B70100F03F02C3F388105CBF47 +:1044400042F20041C0F2F401A1FB00010023FBF79E +:1044500039FF21680222C1F3014102EB4101B0FBA7 +:10446000F1F010BD2DE9F04182B0002800F0A280EB +:104470000446007843F60006C007C4F2020643D0A3 +:10448000B06800F00C00042805D1306880033BD5EB +:104490006068C8BB8EE0B06800F00C00082802D14C +:1044A00070684002F1D46568B5F5A02F0AD0B5F563 +:1044B000803F0BD0306820F480303060306820F4CA +:1044C000802006E0306840F480203060306840F49E +:1044D00080303060FFF71CFD002D054611D000BF75 +:1044E0003068800310D4FFF713FD401B6428F7D910 +:1044F00022E100BFFFF70CFD401B64284FF00300D2 +:1045000055D830688003F5D4207880071AD5B06874 +:1045100010F00C0F09D0B06800F00C00082840F033 +:104520008A807068400200F186803068800702D57A +:10453000E06801283ED13068216920F0F80040EAA7 +:10454000C10030602078000738D4207840074CD470 +:10455000A5695DB3B06800F00C00082840F09E80AB +:10456000012D27D07068E16900F480028A4221D1D0 +:10457000216A00F03F028A421CD147F6C071626A8C +:104580000140B1EB821F15D1A26A0023CFF6FF7361 +:1045900003EBC23200F440316FF30F02914209D1B4 +:1045A000E16A00F07060B0EB016F03D1002002B04F +:1045B000BDE8F081012002B0BDE8F081606900280B +:1045C00040F20000C4F2472057D00121C0F8801EFD +:1045D000FFF79EFC054600BF706F8007B5D4FFF75C +:1045E00097FC401B0228F7D9A6E0306C10F08058E9 +:1045F0000AD100200190306C40F080503064306C63 +:1046000000F080500190019847F20007C4F20007C3 +:104610003868C00524D4386840F480703860FFF7EB +:1046200077FC05463868C0051AD4FFF771FC401BBB +:104630000228F7D980E0E068002851D00020C4F2B9 +:10464000472001210160FFF763FC054630688007C1 +:104650003FF571AFFFF75CFC401B0228F6D96BE019 +:10466000A568052D50D0012D52D0306F20F00100EB +:104670003067306F20F004004DE00021C0F8801E4C +:10468000FFF746FC054600BF706F80077FF55DAF02 +:10469000FFF73EFC401B0228F6D94DE00027C4F28C +:1046A000472700203866FFF733FC022D05460BD163 +:1046B0003068800158D5FFF72BFC401B02284FF0D3 +:1046C0000300F5D973E700BF306880017FF56EAF56 +:1046D000FFF71EFC401B02284FF00300F4D966E7E9 +:1046E0000020C4F2472000210160FFF711FC0546BD +:1046F000306880077FF526AFFFF70AFC401B0228D1 +:104700004FF00300F4D952E7306F40F004003067F7 +:10471000306F40F001003067FFF7FAFB002D0546CF +:1047200041F2883714D000BF306F800713D4FFF7F1 +:10473000EFFB401BB842F7D9032002B0BDE8F0817F +:10474000FFF7E6FB401BB8424FF003003FF62FAFE8 +:10475000306F8007F4D4B8F1000F7FF4F9AE306CFD +:1047600020F080503064F3E604F11C052FCD08439F +:104770000021CFF6FF7140EA821001EBC3316FF3E5 +:104780000F0140EA05600843706001203866FFF7BA +:10479000BFFB0446306880013FF508AFFFF7B8FB68 +:1047A000001B02284FF00300F4D900E780B502F0A7 +:1047B00045FD022808BF80BD40F20841C2F2000159 +:1047C00001EB40108069002818BF804780BD0000C1 +:1047D00070B538B10446406A30B10020206104F160 +:1047E000140007E0012070BD6068B0F5827F03D03F +:1047F00004F11C00002101600026A66294F851001B +:1048000020B9204684F8506000F03CF8022084F87B +:10481000510094E80F0001F48271056802F404422B +:1048200025F040050560114403F40062236911443A +:1048300003F002026369114403F00102A369E56910 +:10484000114403F40072114405F03802256A114442 +:1048500005F08002A56A114305F40052114301607E +:10486000626A042101EA134102F01002114441601E +:10487000C16921F40061C1610120666584F85100BD +:10488000304670BD2DE9F04F87B0044643F2000773 +:104890000068C4F201070026B8420696CDE9046616 +:1048A0000396029602D007B0BDE8F08F43F63000C1 +:1048B0000196C4F20200416902AD41F480514161A8 +:1048C000416946F2404801F48051019101990196F5 +:1048D00001684FF0020941F00201016001684FF0E8 +:1048E000030A01F0020101910199019601684FF05C +:1048F000050B41F0010101600068294600F001004C +:10490000019001981820029007F55440C4F2020863 +:10491000CDE90396CDF814A0CDF818B0FFF71EFA34 +:104920008020CDE9020904A880E8400C07F550403A +:104930002946FFF713FA4CF23055C2F201054FF445 +:1049400040304FF0C0674FF48069C5E9080628463B +:10495000C5E90087C5E90266C5E90496C5E90666AA +:10496000FFF72AF9002818BFFDF752FEE564AC6393 +:1049700040F2AC5508F11800C2F200054021C5E92B +:10498000000705F10800002280E806024FF400301D +:10499000C5E908022846C5E90522EA61FFF70CF9D6 +:1049A000002818BFFDF734FEA564AC6307B0BDE86E +:1049B000F08F00002DE9F04182B0044690F85100DC +:1049C000012815D10E4600294FF0010060D017468E +:1049D000002A5DD060681D46B0F5827F02D1A068D4 +:1049E000002858D0FFF794FA94F85010012903D109 +:1049F000022002B0BDE8F0818046012084F850001A +:104A0000042084F8510000206065A663A787E7872B +:104A10002063A086E086A1682064B1F5004F606441 +:104A200008D12068016821F040010160016821F48B +:104A30008041016020680168490603D4016841F0A3 +:104A400040010160E168E08F91B3002855D06E1CF1 +:104A50000BE000BFC068A16B21F8020BA163E08FDF +:104A60000138E087E08F002847D020688168C907B7 +:104A7000F0D1FFF74DFA002EF4D0A0EB0800A842C9 +:104A8000F0D3012084F85100002084F85000032066 +:104A900002B0BDE8F081042084F851002046314680 +:104AA00032463B46009500F09FF902B0BDE8F08128 +:104AB00018B36E1C0BE000BF007BA16B0870A06BED +:104AC0000130A063E08F0138E087E08FA8B1206853 +:104AD0008168C907F0D1FFF71BFA002EF5D0A0EBD3 +:104AE0000800A842F1D3012084F85100002084F886 +:104AF0005000032002B0BDE8F0812046294642461E +:104B000002F00EFB00281CBF20206065012084F805 +:104B10005100002084F85000606D002818BF01206B +:104B200002B0BDE8F081000010B5044690F85100D5 +:104B300001281CBF022010BD13460A4600294FF071 +:104B4000010018BF002B00D110BDA06858B96168E2 +:104B5000B1F5827F07D1042084F851002046114628 +:104B600000F03EFA10BD94F85010012904BF022055 +:104B700010BD012184F85010042184F85110002147 +:104B8000B0F5004F6165A263A387E387C4E9101104 +:104B9000A186E18608D12068036823F04003036002 +:104BA000036823F480430360E06C46F6C97E46F652 +:104BB000ED73C0F6000EC0F60003C0E90F3E46F6E6 +:104BC000A573C0F60003D4F800C0C0E91331E38F29 +:104BD0000CF10C01FFF758F840B1606D40F0100087 +:104BE0006065002084F85000012010BD216808682D +:104BF000400603D4086840F040000860002084F8B4 +:104C000050004A6842F020024A604A6842F00102BD +:104C10004A6010BD80B502F011FB022808BF80BDBC +:104C200040F20841C2F2000101EB40104068002848 +:104C300018BF804780BD000080B502F0FFFA02284F +:104C400008BF80BD40F20841C2F2000101EB4010F4 +:104C50000069002818BF804780BD00002DE9F041A1 +:104C600082B01D4616460F460446FFF751F994F8E8 +:104C7000511001290DD18046002F4FF0010018BFBF +:104C8000002E02D102B0BDE8F08194F85000012856 +:104C900003D1022002B0BDE8F081012084F8500069 +:104CA000032084F85100002060652763A686E6860D +:104CB000A063A087E087A168C4E91000B1F5004FA8 +:104CC00008D12068016821F040010160016841F4C9 +:104CD0008041016020680168490603D4016841F001 +:104CE000400101606168731EE268B1FA81F1B3FAB4 +:104CF00083F349095B09B2F5006F41EA030124D14E +:104D000039B1216B0988C160B81C2063E08E01387D +:104D1000E086E08E002846D06E1C09E0216B31F859 +:104D2000022BC2602163E08E0138E086E08ED0B3B2 +:104D3000206881688907F1D4FFF7EAF8002EF5D0E2 +:104D4000A0EB0800A842F1D323E039B13978017310 +:104D5000206B01302063E08E0138E086E08E10B3D6 +:104D60006E1C0AE0216B09780173206B013020630F +:104D7000E08E0138E086E08EA8B12068816889075E +:104D8000F0D4FFF7C5F8002EF5D0A0EB0800A8423C +:104D9000F1D3012084F85100002084F85000032052 +:104DA00002B0BDE8F08120462946424602F000FAF2 +:104DB00000281CBF20206065A06838B90020019041 +:104DC0002068C1680191806801900198012084F8F1 +:104DD0005100002084F85000606D002818BF0120A9 +:104DE00002B0BDE8F08100002DE9F04381B01E461D +:104DF00015460F460446FFF78BF894F8511081468C +:104E0000012909D06068B0F5827F14D104294FF0E0 +:104E1000020007D1A16829B9002F4FF0010018BF87 +:104E2000002D02D101B0BDE8F083002EFAD094F835 +:104E30005000012803D1022001B0BDE8F083012019 +:104E400084F8500094F85100002104281CBF05206C +:104E500084F851006165A563E687A6872763E68627 +:104E60002068A686216461640168490603D401684C +:104E700041F0400101606168731EE268B1FA81F19E +:104E8000B3FA83F3DDF8208049095B09B2F5006FBE +:104E900041EA030139D139B1216B0988C160B81CDD +:104EA0002063E08E0138E086012608F1010500BF8D +:104EB000E08E10B9E08F00286CD0206881688907E7 +:104EC0000CD5E18E012E09D141B1216B002631F8BC +:104ED000022BC2602163E18E0139E1868168C90736 +:104EE0000AD0E18F41B1C068A16B012621F8020B05 +:104EF000A163E08F0138E087FFF70AF8002DD7D0D3 +:104F0000A0EB09004045D3D33AE039B139780173B9 +:104F1000206B01302063E08E0138E086012608F125 +:104F2000010500BFE08E08B9E08F98B32068816862 +:104F300089070DD5E18E012E0AD149B1216B0026DA +:104F400009780173206B01302063E08E0138E08620 +:104F500020688168C9070BD0E18F49B1C068A16B97 +:104F600001260870A06B0130A063E08F0138E08754 +:104F7000FEF7CEFF002DD5D0A0EB09004045D1D3E0 +:104F8000012084F85100002084F85000032001B073 +:104F9000BDE8F083204641464A4602F009F940B197 +:104FA00020206065002084F85000012001B0BDE899 +:104FB000F083A06838B9002000902068C168009193 +:104FC000806800900098012084F85100002084F847 +:104FD0005000606D002818BF012001B0BDE8F083CB +:104FE00070B5044690F85100012806D100294FF011 +:104FF000010018BF002A0CD170BD6568B5F5827F2D +:105000000ED104284FF00200F6D1A568002DEDD096 +:10501000F2E7002B08BF70BD94F85000012801D1C1 +:10502000022070BD012084F8500094F85100002641 +:1050300004281CBF052084F8510066652163A386FF +:10504000E386A263A387E387C4E9106694F851005E +:1050500046F6C97146F6E173C0F60001C0F60003DA +:10506000042808BF0B4646F6ED7047F2C501C0F6AE +:105070000000C0F6000108BF0146E06C2568C0E9E9 +:105080000F1346F6A571C0F60001C0E91316E38FB1 +:1050900005F10C01FEF7F8FD38B1606D40F010002D +:1050A0006065012084F8506070BD2268216BA06C9F +:1050B000536843F001035360C0E90F66C0E913660B +:1050C000E38E0C32FEF7E0FD40B1606D40F0100061 +:1050D0006065002084F85000012070BD21680868D8 +:1050E000400603D4086840F040000860002084F8BF +:1050F00050004A6842F020024A604A6842F00202C8 +:105100004A6070BD10B5044690F8510001280AD1DC +:1051100000294FF0010018BF002A00D110BD94F8FB +:105120005000012801D1022010BD012084F8500058 +:105130000320002384F8510063652163A286E28680 +:10514000A363C4E91033A387E387A068B0F5004FD9 +:1051500008D12068026822F040020260026842F42E +:1051600080420260A06C46F6D57C47F25502C0F63C +:10517000000CC0F60002C0E90F2C46F6A572C0F67E +:105180000002D4F800E0C0E91323E38E0EF10C0214 +:10519000FEF77AFD40B1606D40F0100060650020C0 +:1051A00084F85000012010BD21680868400603D42F +:1051B000086840F040000860002084F850004A6809 +:1051C00042F020024A604A6842F002024A6010BD82 +:1051D00080B502F033F8022808BF80BD40F20841D4 +:1051E0004001C2F200010858002818BF804780BD66 +:1051F00080B502F023F8022808BF80BD40F20841C4 +:10520000C2F2000101EB4010C068002818BF8047BF +:1052100080BD000080B502F011F8022808BF80BDF3 +:1052200040F20841C2F2000101EB40108068002802 +:1052300018BF804780BD000080B501F0FFFF022845 +:1052400008BF80BD40F20841C2F2000101EB4010EE +:105250004069002818BF804780BD000080B502F07B +:10526000BDFE80BD002804BF0120704710B5044674 +:1052700090F83D0028B9002084F83C00204600F05A +:105280001FF8022084F83D002068211D02F024FF51 +:10529000012084F8460084F83E0084F83F0084F83A +:1052A000400084F8410084F8420084F8430084F808 +:1052B000440084F8450084F83D00002010BD000043 +:1052C00081B0006844F20041C4F20101884201D07B +:1052D00001B070470020009043F64400C4F2020081 +:1052E000016841F400310160006800F40030009072 +:1052F000009801B07047000080B586B044F20041CC +:105300000068C4F20101002288420592CDE903221F +:105310000292019201D006B080BD43F630000092A7 +:10532000C4F20200036843F002030360006800F067 +:105330000200009000984FF4807001900220CDE9A7 +:1053400002020320059001F5404001A90492FEF7F6 +:1053500005FD06B080BD0000B0B5044690F83C00E5 +:10536000012804BF0220B0BD0D464FEAB201012062 +:10537000032984F83C0037D8DFE801F0020A122242 +:105380002068294602F050FF206850F8181F0EE0F0 +:105390002068294602F07AFF206850F8181F16E0AE +:1053A0002068294602F0A8FF206850F81C1F41F031 +:1053B00008010160016821F00401016029690FE022 +:1053C0002068294602F0CCFF206850F81C1F41F4E9 +:1053D00000610160016821F48061016029690902AE +:1053E0000268114301600020002184F83C10B0BD28 +:1053F000002804BF0120704710B5044690F83D0016 +:1054000028B9002084F83C00204600F01FF8022054 +:1054100084F83D002068211D02F05EFE012084F822 +:10542000460084F83E0084F83F0084F8400084F889 +:10543000410084F8420084F8430084F8440084F872 +:10544000450084F83D00002010BD000070470000BA +:1054500010B5044641B1082909D0042914BF04F14C +:10546000410004F13F0004E004F13E0001E004F1DA +:105470004000007801281CBF012010BD022041B16E +:10548000082909D0042914BF84F8410084F83F009A +:1054900004E084F83E0001E084F840002068012226 +:1054A00002F0B0FE206841F2FF71C4F200018842B0 +:1054B0000FDC40F2FF71C4F20001884217DCB0F14A +:1054C000804F49D040F20041C4F20001884243D0ED +:1054D00049E040F2FF32C4F20102904214DC41F68E +:1054E0000003C4F20003984236D0002314E040F6D3 +:1054F0000001C4F2000188422ED040F60041C4F2FF +:105500000001884228D02EE044F20003C4F20103D7 +:10551000984221D040F20043C4F20103984222D1C4 +:10552000436C884243F400434364C2DD904207DC8D +:1055300041F60001C4F2000188420DD0002107E0CD +:1055400044F20001C4F20101884205D040F200415A +:10555000C4F20101884206D1816801F007010629E1 +:1055600004BF002010BD016841F00101016000206E +:1055700010BD00007047000080B503F0C3FB052894 +:1055800008BF80BD4CF2540100EBC000C2F2010123 +:1055900001EB80000069002818BF804780BD000033 +:1055A000B0B582B0036804461868D9685A6900F03B +:1055B0002F05202D01F0200505D125B1204603F04F +:1055C000BBFB02B0B0BD5FEA007C1EBF02F0010E63 +:1055D00001F4907212EB0E024AD1226B0840C10610 +:1055E0003DD5012A3BD100200190186801905868F0 +:1055F000019001985869400642D4A08DE18DE28D5A +:10560000002A1CBF401A5FEA004101D102B0B0BDC0 +:10561000216851E8031F226821F4907142E80313C6 +:10562000002BF5D1216851E8051F226821F0010106 +:1056300042E80513002BF5D1202184F84210002107 +:10564000216300BF216851E8031F226821F0100187 +:1056500042E80313002BF5D10221616354E00106F7 +:1056600054D44006D2D5204603F032FB02B0B0BD80 +:10567000C20718BF11F480725DD1420761D467E0A0 +:10568000E06B016849688AB2002A44D0A38D9A422F +:1056900041D2E185C069B0F5807F30D0206850E804 +:1056A000030F216820F4807041E80302002AF5D13D +:1056B000206850E8050F216820F0010041E805024C +:1056C000002AF5D1206850E8050F216820F040003D +:1056D00041E80502002AF5D1202084F8420000208C +:1056E000206300BF206850E8030F216820F01000FD +:1056F00041E80302002AF5D1E06BFEF745F90220EC +:105700006063A08DE18D401A81B20FE0204603F066 +:1057100055FC02B0B0BDA18D91427FF477AFC06956 +:10572000B0F5807F7FF472AF022060632046FFF700 +:1057300021FF02B0B0BD626C42F001026264420718 +:1057400006D5BEF1000F03D0626C42F00202626423 +:10575000820706D5BEF1000F03D0626C42F004024E +:105760006264BCF1000F06D55EEA050203D0626CEC +:1057700042F008026264626C002A3FF447AF0840BE +:10578000800602D5204603F0D7FA20684069616C94 +:1057900000F0400001F00801401827D0204603F037 +:1057A0006FFA2068406940061BD500BF206850E8AA +:1057B000050F216820F0400041E80502002AF5D1DC +:1057C000E06B70B148F63531C0F600010165FEF7B7 +:1057D0001BF900283FF41AAFE06B016D884702B057 +:1057E000B0BD2046FFF7C8FE02B0B0BD2046FFF7AF +:1057F000C3FE0020606402B0B0BD0000002804BFFA +:105800000120704710B5044690F8410028B90020E7 +:1058100084F84000204600F021F8242084F841005C +:105820002068C16821F40051C160204603F0E8FA05 +:105830002068016921F490410161416921F02A0148 +:105840004161C16841F40051C160002020216064C1 +:1058500084F8411084F84210606310BD2DE9F043D4 +:1058600087B00446006840F6FF71C4F20101884227 +:105870004FF000010691CDE90411CDE902115DDC84 +:1058800044F20041C4F20001884200F0AF8044F6C7 +:105890000001C4F20001884240F01081002643F666 +:1058A00030000196C4F20200016941F480210161D7 +:1058B000016901F48021019101990196016841F08B +:1058C00004010160006802A900F004000190019841 +:1058D0004FF4406002900220CDE9030603200590BA +:1058E000072006900020C4F2020000F50060FEF7D9 +:1058F00035FA4CF2905546F22800C2F20105C4F286 +:1059000002004FF0006185E843004FF400304FF48F +:1059100080624FF48073C5E908062846C5E9036232 +:10592000C5E90566EB61FEF747F9002818BFFCF7EB +:105930006FFEE563AC6307B0BDE8F08341F2004160 +:10594000C4F20101884200F0868041F20001C4F2F5 +:105950000101884240F0B280002643F630000196F3 +:10596000C4F202004169002441F010014161416923 +:10597000C4F2020401F0100101910199019601683D +:1059800002AD41F00201016001684FF0020801F030 +:10599000020101910199019601684FF0030941F05C +:1059A000010101600068072700F0010001900198E3 +:1059B0008020029004F580602946CDE90386CDF869 +:1059C00014900697FEF7CAF94FF40070CDE902086B +:1059D00020462946CDE904690697FEF7BFF9252040 +:1059E00005210022FEF71CFC25202FE0002043F6B5 +:1059F00030010190C4F202010A6942F400320A61E6 +:105A00000A6902F400320192019A01900A6842F098 +:105A100008020A60096801F00801019101996021FA +:105A200002910221CDE90310032005900720069082 +:105A30000020C4F2020000F5406002A9FEF78EF9D2 +:105A4000262005210022FEF7EBFB2620FEF7E4FBD3 +:105A500007B0BDE8F083002043F630010190C4F2A6 +:105A600002014A6942F020024A614A6902F02002BA +:105A70000192019A01900A6842F040020A600968A6 +:105A800001F04001019101994FF4844102910221FA +:105A9000CDE9031003200590082006900020C4F2F1 +:105AA000020000F5C05002A9FEF758F94720052171 +:105AB0000022FEF7B5FB4720FEF7AEFB07B0BDE8BE +:105AC000F083000080B590F84230202B1CBF0220EC +:105AD00080BD00294FF0010318BF002A01D11846EC +:105AE00080BD0023036303F0F9F90346184680BD27 +:105AF00010B590F84230202B1CBF022010BD0029A9 +:105B00004FF0010418BF002A01D1204610BD002427 +:105B1000046303F039FA204610BD000080B503F09D +:105B2000F1F8052808BF80BD4CF2540100EBC0001D +:105B3000C2F2010101EB8000C068002818BF804755 +:105B400080BD000080B503F0DDF8052808BF80BDEA +:105B50004CF2540100EBC000C2F2010101EB8000E5 +:105B60008068002818BF804780BD0000B0B504469B +:105B700090F8410020281CBF0220B0BD4FF001006A +:105B8000C9B3002A134608BFB0BD4FF0000C212056 +:105B90002162A384E384C4F844C084F84100A06B6C +:105BA00048F6354E48F675452268C0F6000EC0F638 +:105BB0000005C0E90FE548F64535C0F6000504329A +:105BC000C0E9135CFEF760F830B11020606420205B +:105BD00084F841000120B0BD20686FF040010160F1 +:105BE000206850E8050F216840F0800041E8050278 +:105BF000002AF5D10020B0BD034690F841002028CE +:105C00001CBF0220704700294FF0010018BF002A76 +:105C100000D170471962002021219A84DA845864E7 +:105C200083F841101968CA6842F08002CA60704760 +:105C300080B503F067F8052808BF80BD4CF2540119 +:105C400000EBC000C2F2010101EB800040680028B7 +:105C500018BF804780BD000080B503F053F80528C9 +:105C600008BF80BD4CF2540100EBC000C2F201013C +:105C700051F82000002818BF804780BDFEE70000D3 +:105C800045F6DF1110EE100AC5F63771B6EE001AB0 +:105C9000A1EB600020EE011A00EE100A21EE002AAE +:105CA00022EE002AB7EE083A33EE422A22EE000A2C +:105CB00021EE001A20EE011A33EE411A20EE010AFD +:105CC0007047000010B52DED088B88B3B0EE408A08 +:105CD00090ED010A90ED069A90ED021A90ED07AA58 +:105CE00029EE000A38EE400A2AEE011A30EE41BAD7 +:105CF00004461BEE100A03F0BDF9002808BFB0EE01 +:105D00004B8A94ED030A94ED041A94ED052A20EED3 +:105D1000080A29EE011A30EE010A2AEE021A30EEC4 +:105D2000010A84ED068A84ED079ABDEC088B10BD4C +:105D30009FED020ABDEC088B10BD00BF0000000003 +:105D4000002808BF704710B5F5EE400A0446C0EDC4 +:105D5000000A0020F1EE10FAA061E0612EDD80EE75 +:105D6000200A9FED1E1A81EE000A06F063FD9FEDEA +:105D70001C1AB7EE002A20EE011A31EE023A20EE8C +:105D8000000ABFEE005A30EE033A30EE055A32EE0A +:105D9000411A80EE034A35EE055A30EE010A85EECF +:105DA000035A80EE030A34EE041A84ED034A84EDAC +:105DB000041A84ED054A84ED015A07E04FF07E5144 +:105DC0009FED050AC4E903106061606084ED020A7A +:105DD000BDE81040704700BF00000000DB0F4940E5 +:105DE000F304B53F10B52DED048B10B3B0EE408A2F +:105DF00090ED030A90ED041A90ED052A30EE010AA9 +:105E000030EE020A88EE009A044619EE100A03F0FA +:105E100021F900282046B0EE480A08BFB0EE489AA3 +:105E200084ED069A84ED079AFFF74CFFBDEC048BD6 +:105E300010BD9FED020ABDEC048B10BD00000000F8 +:105E4000B0B5012802D9FF2040B2B0BD4CF28C158C +:105E5000C2F20105044655F8200060B98820FBF71E +:105E6000D9FF002845F82400EDD08821FAF721FB5E +:105E700055F824000470002040B2B0BD80B584B055 +:105E8000D8B100F029F8014600284FF0FC0015D0E9 +:105E90008A888DF80C00009208228DF804204FF0BB +:105EA000FF32CDF80520029208786946FBF74AFEDA +:105EB000002818BF4FF0FF3000E0FE2040B204B0D1 +:105EC00080BD000001288FBF00204CF28C11C2F26F +:105ED000010151F8200070472DE9F04128B3057801 +:105EE00080462846FFF7EEFFF8B1014690F884009F +:105EF000D8B10A1D002309E00126002E08BFBDE825 +:105F0000F08191F884600133B3420ED252F82340FD +:105F1000002CF1D02678AE42EED16688B8F8027037 +:105F2000BE42E9D100262046E7E70020BDE8F08127 +:105F300010B50C46014600284FF0FE0018BF002C9B +:105F400001D140B210BD0846FFF7C6FF20B121467F +:105F500000F0D4F840B210BDFC2040B210BD0000EB +:105F6000B0B52DED028B00286BD00D46002968D00E +:105F70000446B5F801009FED340A0004DFED330A52 +:105F800000BA102104F07CFA84ED070AE878297938 +:105F9000000140EA1110BBEE0E0AF3EE0E0A0C21CE +:105FA00004F06EFA84ED080A2879697900F00F0090 +:105FB000B0EE408A41EA0020BAEE080AF2EE080A82 +:105FC0000C2104F05DFA84ED090AA87994ED071A12 +:105FD00002EE100AB5EE401AB8EE422AF1EE10FABF +:105FE00084ED0A2A0BDA9FED1A2A00BF31EE021A5D +:105FF000B5EE401AF1EE10FAF8DB84ED071A94EDD5 +:10600000071A9FED132AB4EE421AF1EE10FA0ADBDA +:106010009FED103A31EE031AB4EE421AF1EE10FA87 +:10602000F8DA84ED071AE07958B132EE411AB1EE90 +:10603000482AB1EE400A84ED071A84ED082A84ED5F +:10604000090ABDEC028BB0BDDA0F49C1DA0F494134 +:10605000DB0FC940DB0FC9C070B538B1044600780A +:10606000FFF7EEFE28B1FF2040B270BDFE2040B227 +:1060700070BD2078FFF726FF0028F4D090F8842028 +:1060800005469AB1281D002105E000BF95F884203F +:10609000013191420AD250F82120002AF6D05288CC +:1060A00063889A42F2D1FD2040B270BD1F2ADAD82F +:1060B0003020FBF7AFFE0028D5D030210646FAF796 +:1060C000F8F920686168C6E900010020E2793072C1 +:1060D0002078618832760322FBF7EEFB18B1304658 +:1060E000FBF710FEBFE795F8840005EB8001013057 +:1060F00085F88400002040B24E6070BD2DE9F04369 +:1061000081B02DED048B84B0044600284FF0FE00D2 +:1061100071D00D4600296ED095ED001A95ED012A3B +:1061200095ED023AE079B1EE430AB1EE428AB1EE62 +:10613000419A002802BFB0EE430AB0EE428AB0EEA8 +:10614000419ADFED300A9FED301A102003F04AF833 +:106150008046FBEE0E0AB3EE0E1AB0EE480A0C2093 +:1061600003F040F89FED298A95ED030A9FED281A68 +:106170000746F0EE480A0C2003F034F895ED040AC7 +:106180008146B1EE041AF0EE480A0C2003F02AF81A +:106190000646FAEE080AB2EE081AB0EE490A0C20DA +:1061A00003F020F83A094FEA1923A5888DF8072053 +:1061B00022784FEA182143EA0713070A47EA06172D +:1061C0003609009508258DF805108DF80C006946F4 +:1061D00010468DF804508DF806808DF808308DF843 +:1061E00009908DF80A608DF80B70FBF7ABFC002866 +:1061F00018BF4FF0FF3040B204B0BDEC048B01B0CB +:10620000BDE8F083DA0F49C1DA0F49410000000010 +:106210000000FA43F0B587B0A0B3077805463846CA +:10622000FFF750FEA8B390F8841069B3011D002257 +:1062300005E000BF90F8843001329A4224D251F830 +:106240002240002CF6D063886E88B342F2D1F4B1BC +:1062500069886D4638462A460023FBF727FAD0B1F5 +:10626000FBF794FED4E90423801A48F2A162C0F23D +:1062700001029941801A71F1000024BF00202072B0 +:10628000FF2014E0FE2012E00024002CE0D1FC20CE +:106290000DE0FC200BE001202072FBF777FEC4E943 +:1062A000040105F10D012046FFF75AFE002040B21F +:1062B00007B0F0BDB0B5012802D9FF2040B2B0BD93 +:1062C00040F24845C2F20005044655F8200060B986 +:1062D0004820FBF79FFD002845F82400EDD0482119 +:1062E000FAF7E7F855F824000470002040B2B0BD7A +:1062F000B0B584B048B304780546204600F064F891 +:1063000028B36988A1F201210A295BD8012202FA87 +:1063100001F10A071DD111F0F00F30D040F2FF114A +:10632000009108218DF804100A3000216A4600BF50 +:1063300000EB41035B7802EB41056B7110F8113003 +:1063400001310429AB71F3D131E0FE2037E0FC20AC +:1063500035E04FF40071009108218DF804100230EF +:1063600000216A4600EB41035B7802EB41056B714B +:1063700010F8113001310429AB71F3D117E040F26C +:10638000FF21009108218DF80410123000216A4687 +:1063900000EB41035B7802EB41056B7110F81130A3 +:1063A00001310329AB71F3D10020ADF80B00694630 +:1063B0002046FBF7C7FB002818BF4FF0FF3040B264 +:1063C00004B0B0BDFF20FAE701288FBF002040F2E3 +:1063D0004841C2F2000151F82000704748B102283C +:1063E0000BD0012814BF4FF6FF704FF4804000B26D +:1063F000704742F2107000B2704747F2305000B25E +:1064000070470000022905D2A0F2012189B20729B4 +:1064100009D805E007D1A0F2052189B2062902D8E2 +:10642000013840B27047FF2040B27047F0B581B0EC +:1064300008B307460078FFF7C7FFE0B1014690F8C0 +:106440004400C0B101F11802002306E0012585B126 +:1064500091F844500133AB420DD252F82340002C46 +:10646000F4D065887E88B542F0D100252046002D05 +:10647000EED101B0F0BD002001B0F0BD022884BF14 +:10648000B7EE000A704740B202A101EB800090ED28 +:10649000000A7047000010422CA099410000803F84 +:1064A00070B538B104460078FFF704FF28B1FF202B +:1064B00040B270BDFE2040B270BD2078FFF784FF6F +:1064C0000028F4D090F8442005469AB105F1180050 +:1064D000002104E095F84420013191420AD250F89D +:1064E0002120002AF6D0528863889A42F2D1FD20FA +:1064F00040B270BD0A2ADAD85020FBF78BFC002886 +:10650000D5D0064620686168C6E9000106F118008A +:106510002821F9F7CEFF62792078618886F8282053 +:106520000322FBF7C9F918B13046FBF7EBFBBEE7D6 +:1065300095F8440005EB8001013085F84400002007 +:1065400040B28E6170BD000080B59FED020A00F080 +:1065500003F880BD0000000070B52DED048B00280D +:106560003ED005460078B0EE408AFFF72DFFC8B355 +:10657000B7EE000AB4EE408AF1EE10FAC8BFB0EEF2 +:10658000408ABFEE000AB4EE408A0446F1EE10FAEB +:10659000B8BFB0EE408A6879B1EE489A0028284624 +:1065A00008BFB0EE489AFFF741FFE8B12E7968883E +:1065B0003146FFF727FF002818D405463046FFF77D +:1065C0000DFF00EE100AB8EEC00A29EE000ABDEE7B +:1065D000C00A10EE100A04EB45014880002006E0D6 +:1065E000FE2004E0FC2002E0FC2000E0FF2040B29E +:1065F000BDEC048B70BD00002DE9F04F87B0002882 +:1066000052D004460078FFF7DFFE00284ED0054642 +:1066100090F8440000284BD005F11806E8464FF0EA +:10662000010A40F2E93B4FF0000908E0012100298E +:1066300041D095F8441009F1010989453AD256F83C +:106640002970002FF2D07A8861888A42EED12078B2 +:1066500042460023FBF72AF870B1FBF797FCD7E915 +:106660000823801A9941B0EB0B0071F1000016D39A +:1066700000203876FC2013E087F818A0FBF786FC92 +:10668000C7E908013846414600F076FA07F10803E9 +:106690000FCB07F12C0C8CE80F00002000E0FF204E +:1066A00000210029C5D106E0FE2004E0FC2002E024 +:1066B000FC2000E0FC2040B207B0BDE8F08F0000F5 +:1066C00010B540F2845046F20041C2F20000C4F21C +:1066D0000001032200234FF0807480E80E0000F1D7 +:1066E0000C014FF4102C4FF4001E81E80850846117 +:1066F0008383FCF713FF002818BFFBF789FF10BD49 +:1067000010B54CF2085046F60001C2F20100C4F286 +:106710000001032200234FF0807480E80E0000F196 +:106720000C014FF4102C4FF4001E81E808508461D6 +:106730008383FCF7F3FE002818BFFBF769FF10BD49 +:1067400080B582B0002043F630010190C4F202010E +:106750000A6842F480020A600A6802F48002019228 +:10676000019A00900868002240F400100860086850 +:10677000052100F40010009000980C20FDF750FD5A +:106780000C20FDF749FD3A2005210022FDF748FDC8 +:106790003A20FDF741FD3B2005210022FDF740FD99 +:1067A0003B20FDF739FD02B080BD000080B547F603 +:1067B000D1704DF62042C0F60000C0F60002002164 +:1067C00003F052F840F25041C2F20001086048F272 +:1067D000B1304DF6B412C0F60000C0F60002002140 +:1067E00003F042F880BD00002DE9F04786B000209C +:1067F00043F630010590CDE90300CDE9010000909A +:10680000C4F202010A68002442F002020A600A6827 +:10681000C4F2020402F002020092009A00900A6898 +:1068200004F5C05742F040020A600A68402602F0B0 +:1068300040020092009A00900A6842F001020A6049 +:106840000A6802F001020092009A00900A6842F081 +:1068500008020A600A6802F008020092009A00909A +:106860000A6842F004020A600A6802F00402009218 +:10687000009A00900A6842F020020A600A6802F05A +:1068800020020092009A00900868002240F08000E8 +:1068900008600868402100F08000009000983846A9 +:1068A000FDF730FB2046102101224FF01009012591 +:1068B000FDF728FB04F58068404601210122FDF721 +:1068C00021FB0196112001AECDE902053846314683 +:1068D0000495FDF743FA082001904FF4041A384656 +:1068E0003146CDE902A5FDF739FA20463146CDE91A +:1068F000015A0395FDF732FA20463146CDE901955C +:10690000CDE90355FDF72AFA3020CDE9010A04F557 +:10691000006031460395FDF721FA40463146CDE946 +:106920000155CDE90355FDF719FA0620052100228E +:10693000FDF776FC0620FDF76FFC092005210022FB +:10694000FDF76EFC0920FDF767FC0A2005210022F7 +:10695000FDF766FC0A20FDF75FFC172005210022E9 +:10696000FDF75EFC1720FDF757FC06B0BDE8F08789 +:1069700080B540F20C6045F60001C2F20000C4F29E +:10698000000148F2A06200234FF4804CC0F20102E3 +:1069900080E80E00C0E9033CC0E90533C0E90733D5 +:1069A000FDF7BCFA002818BFFBF732FE80BD0000DF +:1069B000B0B54CF2F05043F20001C2F20100C4F253 +:1069C00001014FF48272002380E80E0000F10C01F7 +:1069D0004FF0020C4FF0010E4FF40074182581E8BF +:1069E00008500A21C0E90645C0E90833C0E90A3168 +:1069F000FDF7EEFE002818BFFBF70AFEB0BD000051 +:106A000080B588B040F2606044F200420021C2F2DA +:106A10000000C4F2010241F288330791CDE905116B +:106A2000CDE90311CDE90111C0E90021C0E902134C +:106A300001618161FEF716FC002818BFFBF7E8FD35 +:106A400040F26060C2F20000FEF7D2FC002818BFDE +:106A5000FBF7DEFD602001900020CDE902000590EB +:106A600040F26060C2F2000001A90022FEF774FC4F +:106A7000002818BFFBF7CCFD40F26060C2F20000B6 +:106A8000FEF73AFC08B080BD80B54CF2486041F298 +:106A90000001C2F20100C4F2010100234FF00C0C0E +:106AA0004FF4E13280E80E00C0E90333C0E905C3CA +:106AB000C361FEF7A3FE002818BFFBF7A9FD80BD48 +:106AC00080B540F2A86044F20041C2F20000C4F276 +:106AD000000100234FF00C0C4FF4E13280E80E006F +:106AE000C0E90333C0E905C3C361FEF787FE002890 +:106AF00018BFFBF78DFD80BD80B54CF2906044F669 +:106B00000001C2F20100C4F2000148F2A062C0F22A +:106B10000102002380E80E0000F10C014FF4806CAC +:106B20004FF0040E81E80850C0E90633FEF766FE18 +:106B3000002818BFFBF76CFD80BD000080B540F257 +:106B4000F06041F20041C2F20000C4F201010023F2 +:106B50004FF00C0C4FF4E13280E80E00C0E9033333 +:106B6000C0E905C3C361FEF749FE002818BFFBF763 +:106B70004FFD80BDFEE700002DE9F0478846B1F8E3 +:106B80000D10044608BA4FEA1049B8F811002679EA +:106B9000B8F80F1005BA304691FAB1FAFFF71EFCAB +:106BA00007463046FFF76AFC01EE109A9FED453A22 +:106BB000B8EE412A9FED441A22EE032A22EE014A42 +:106BC00002EE10AA15FB27F0B8EEC23A02EE100A48 +:106BD000A0799FED3E5AB8EEC22A22EE052A48B1AE +:106BE000B4F84000A9EB0000B0F5805F0CDD4FF079 +:106BF000FF300DE00020A4F84090C4E9110084EDBE +:106C0000024A84ED033A1CE010F5805F03DA0120AC +:106C1000616C0844606494ED115A83EE003AB8EE5A +:106C2000C55A25EE015A34EE054A84EE004AA4F80E +:106C3000409020EE022A84ED033A84ED124A84ED5E +:106C4000024A94ED020A84ED042AB5EE400AF1EE00 +:106C500010FA08DA30EE010AB5EE400AF1EE10FA49 +:106C6000F8DB84ED020A94ED020AB4EE410AF1EE7B +:106C700010FA0ADB9FED162A30EE020AB4EE410A42 +:106C8000F1EE10FAF8DA84ED020A94F8280078B1EF +:106C900031EE400A84ED020A94ED030A94ED041AE1 +:106CA000B1EE400A84ED030AB1EE410A84ED040A14 +:106CB00098F8130000EE100AB8EE400A84ED050AB9 +:106CC000BDE8F08700000039DB0FC94000008038C4 +:106CD000DB0FC9C0FEE7000000F0070080F00703EB +:106CE000042B28BF04234FF0FF3C03380CFA03F3B6 +:106CF00038BF0020994381400CFA00F022EA0000DE +:106D000008437047B0B52DED0A8B044610EE100A0B +:106D1000B0EE618AB0EE419AB0EE60AAB0EE40BA31 +:106D200002F0A0F9002800F09C801AEE100A02F090 +:106D300099F9002800F0958019EE100A02F092F9F6 +:106D4000002800F08E8018EE100A02F08BF900285F +:106D500000F087806068B0EE4B0A90ED071AF0EE05 +:106D60004A0AFBF763FA6068B0EE40BA90ED001A89 +:106D700004F11C0020EE01CA21EE0A0AFEF7A2FF70 +:106D8000207888B1012811D194ED051A94ED022ADA +:106D900030EE411AB4EE428AF1EE10FAC8BFB0EEFE +:106DA000482A81EE029A01E09FED309A19EE100A0E +:106DB00084ED04BA84ED050A02F054F965689FED8C +:106DC0002B0A002808BFB0EE409A95ED010A95ED18 +:106DD000032A2CEE000A29EE022A95ED021A30EE63 +:106DE00042AA94ED030A9FED229A2CEE082A32EE75 +:106DF000008AB4EE491AF1EE10FA28EE01BA1ADD53 +:106E000018EE100A02F02EF9A8B13AEE0B0A95ED31 +:106E1000051AB0EEC00AB4EE410AF1EE10FA0ADC2F +:106E200095ED040AB0EEC81AB4EE401AF1EE10FA6D +:106E3000D8BF84ED038A3AEE0B8A18EE100A02F0EE +:106E400011F970B1D5ED050AF4EE490AF1EE10FA28 +:106E500005DDB0EE480AFAF785F9B0EE408A84ED18 +:106E6000068A94ED060ABDEC0A8BB0BD0000000056 +:106E7000BD37863570B52DED048B90B30446506850 +:106E80001646B0EE408A0D4602F0ECF858B3B068F2 +:106E900002F0E8F848B3F06802F0E4F838B330697B +:106EA00002F0E0F828B3706902F0DCF818B3B7EE2E +:106EB000000A80EE089A666019EE100A02F0D2F815 +:106EC000D8B1D6ED060A04F11C00B0EE480A84EDF4 +:106ED000029AFEF735FF2046257000F013F80020D7 +:106EE0000CE0FF200AE0FF2008E0FF2006E0FF2082 +:106EF00004E0FF2002E0FF2000E0FF2040B2BDECF4 +:106F0000048B70BD10B568B100F11C0100249FED29 +:106F1000070AC0E90344C0E905440846FEF762FFDA +:106F200060B210BDFF2460B210BD00BF00000000C1 +:106F300000280EBFFF210021C16048B27047000049 +:106F4000EFF30980BFF36F8F154B1A681EF0100F17 +:106F500008BF20ED108A20E9F04F10602DE90900EC +:106F60004FF0500080F31188BFF34F8FBFF36F8F46 +:106F700003F0F0FD4FF0000080F31188BDE8090038 +:106F800019680868B0E8F04F1EF0100F08BFB0ECA9 +:106F9000108A80F30988BFF36F8F704700BF00BF6E +:106FA00060C7012080B5806B01684A6822F0030247 +:106FB0004A60416D41F010014165012180F8511096 +:106FC000FDF7F4FB80BD000080B5806BFDF734FE5B +:106FD00080BD000080B5806BFEF70AF980BD00001F +:106FE00080B5806BFEF728F980BD0000B0B5846BDA +:106FF0000546FCF78DFF29680968C90526D40246B5 +:107000002068A168436823F02003436031B96168B8 +:10701000B1F5827F02D16FF0030101E06FF0010151 +:107020004368194041602046642100F079F8002847 +:107030001CBF202060650020E087012084F85100FB +:10704000606D18B12046FDF7B1FBB0BD2046FDF7DD +:10705000E1FDB0BDB0B582B0846B0546FCF758FFCA +:1070600029680968C90528D402462068416821F0CA +:1070700020014160416821F0020141602046642105 +:1070800000F096F818B1606D40F020006065A068CF +:1070900038B9002001902068C16801918068019092 +:1070A00001980020E086012084F85100606D20B135 +:1070B0002046FDF77BFB02B0B0BD2046FEF788F806 +:1070C00002B0B0BDB0B5846B0546FCF721FF29685E +:1070D0000968C9051FD402462068416821F02001D3 +:1070E00041602046642100F063F818B1606D40F003 +:1070F000200060652068416821F0030141600020A4 +:10710000E086E087012084F85100606D18B12046C8 +:10711000FDF74CFBB0BD2046FEF77CF8B0BD00008B +:10712000B0B582B0044640680B46B0F5827F20D1EE +:10713000A168B1F5004F02D0B1F5806F04D121688C +:107140000D6825F040050D60B0F5827F11D1A06873 +:10715000B0F5806F1DD1009220460121002200254C +:1071600000F076F890B1606D032540F02000606576 +:107170000CE00092204601210022002500F068F872 +:1071800020B1606D032540F020006065284602B004 +:10719000B0BD0092204680210022002500F058F862 +:1071A0000028F3D0606D032540F020006065EDE716 +:1071B00070B582B00D461646022101222B460446C8 +:1071C000009600F045F838B1606D032540F02000CE +:1071D0006065284602B070BD40F20000C2F20000B7 +:1071E000006849F68171C1F25E61A0FB0101480DA2 +:1071F0004FF47A71484301906068B0F5827F0FD1F7 +:107200002046802100222B460096002500F020F821 +:107210000028DED0606D032540F020006065D8E7CF +:10722000019840B1019801380190206880680006FB +:10723000F6D40025CDE70025CBE70000006843F237 +:107240000001C4F20101401A18BF0120400070473C +:107250002DE9F04782B00A9C984615460E468146B5 +:10726000FCF756FE201A00EB0804FCF751FE40F232 +:107270000001C2F200010968C1F3CB316143019101 +:10728000D9F8001089683140891BB1FA81F14909A8 +:10729000A94203D1002002B0BDE8F087824608F180 +:1072A00001070CE0019801380190D9F800008068CE +:1072B0003040801BB0FA80F04009A842EAD0002F8D +:1072C000F3D0FCF725FEA0EB0A00A04204D20198FF +:1072D0000028E7D10024E8E7D9E900014268B1F5C8 +:1072E000827F22F0E00242600BD1D9F80810B1F59C +:1072F000004F02D0B1F5806F03D1016821F0400149 +:107300000160D9F82810B1F5005F07D1016821F4B8 +:1073100000510160016841F400510160012089F8C9 +:107320005100002089F85000032002B0BDE8F0872A +:10733000074B19680868B0E8F04F80F30988BFF37D +:107340006F8F4FF0000080F31188704700BF00BFBF +:1073500060C7012080B501F0D3FE80BD90ED000A2A +:1073600091ED001AB7EE002A30EE011AB4EE421A7F +:10737000F1EE10FAD8BF704782EE011A20EE010A32 +:1073800080ED000A91ED000A21EE000A81ED000A6D +:1073900070470000002804BFBFEE000A70478269F2 +:1073A000137823B1012B2AD19FED181A01E09FED2C +:1073B000151A02EB810292ED020A90ED3E2A00EBD3 +:1073C000011191ED093A20EE020A30EE430A20EE57 +:1073D000002A21EE013A82EE032AB0EEC03AB7EE5F +:1073E000000AB4EE413AF1EE10FA30EE422A9FED77 +:1073F000060AB8BFB0EE420A80ED2D0A70479FED35 +:10740000020A704700004842000000000000C84324 +:10741000B0B52DED048B10B30446B0F8BC0000B33A +:1074200094ED001A94ED2E2A9FED208AD4ED300AB7 +:1074300094ED3F0A31EE429AB0EE481A0D46FAF743 +:10744000F5FEA169B7EE001A91ED052A81EE022A38 +:10745000B4EE429AF1EE10FA05DA002021E0FF20A6 +:107460001FE0FF201DE0B4EE410AF1EE10FA4FF0EC +:10747000000016DCAA78A2B12068F0EE480AC4F831 +:10748000B80091ED040A04F1FC00B8EE400A88EE61 +:10749000000AFAF7ADFEB4F8BC000138A4F8BC004D +:1074A000002040B2BDEC048BB0BD00BFDB0FC94073 +:1074B00048B181690978012908D061B94EF200010B +:1074C000C4F2AB5105E0FF2040B270470021C4F286 +:1074D0007A51C0F8F810002040B2704791F8381087 +:1074E0000139CAB2022A0BD84FF4FF6202EAC10185 +:1074F00001224FF00113CA4023FA01F1827041705A +:1075000000207047B0B52DED028B054600284FF0E6 +:10751000FF0027D00C4629B3FAF738FD06F0DFF854 +:107520009FED128A00EE100A80EE080A85ED000A2F +:10753000FAF72CFDD5E90223801A994106F0CFF81D +:1075400000EE100A80EE080A85ED040AFAF71EFD27 +:10755000C5E902012846FFF7ABFF2846214600F0A7 +:10756000ABF8002040B2BDEC028BB0BD00247449E2 +:107570002DE9F04F81B02DED028B834600284FF0AE +:10758000FF0000F092808846002900F08E80B5EE62 +:10759000400AB0EE408AF1EE10FA40F3868098F887 +:1075A0000440CBF81880FAF7C1F8B4B308F14409E5 +:1075B00008F1640A08F128050BF580760BF51A77B7 +:1075C0002846FEF76DFF30460121B0EE480A4A46D4 +:1075D000FFF750FC06F178000121B0EE480A524650 +:1075E000FFF748FCDBF81800B0EE480AD0ED410A7E +:1075F0003846FEF7A5FBDBF81800B0EE480AD0EDE0 +:10760000420A07F14000FEF79BFB013C05F10A0529 +:1076100006F13C0607F12007D2D108F13C00FEF745 +:107620003FFFDBF8180090F8400078B101283BD10B +:107630000BF5F87008F1C4020121B0EE480AFFF71B +:1076400019FC0BF50B7008F1E4020CE00BF5F87077 +:1076500008F184020121B0EE480AFFF70BFC0BF59C +:107660000B7008F1A4020121B0EE480AFFF702FCFA +:10767000DBF81800B0EE480AD0ED430A0BF53A707B +:10768000FEF75EFBDBF81800B0EE480AD0ED440AC6 +:107690000BF54270FEF754FB0020CBE92E00CBE93E +:1076A0003000CBF8C80000E0FC2040B2BDEC028BFB +:1076B00001B0BDE8F08F0000B0B5F8B104468069B4 +:1076C000027FF2B194F89C20032A67D8DFE802F029 +:1076D0000259233A94ED140A9FED421A80EE010AF2 +:1076E00090ED081AB4EE410AF1EE10FA68DD226856 +:1076F000012084F89C00C4F8982061E0FF2568B25E +:10770000B0BD0025204684F89C5084F8945000F0C9 +:10771000F5F868B2B0BD90ED040A9FED301AB8EEEE +:10772000400A81EE000A94ED301A00202268A4F885 +:10773000BC00032084F89C00C4F8982031EE000AB5 +:1077400084ED3F0A204600F0D9F894ED000A94ED4C +:10775000261A9FED232A30EE410AB4EE420AF1EEDA +:1077600010FA30DB94ED140A9FED1E1A002580EE0E +:10777000010AB3EE041AB4EE410AF1EE10FAC8DAC7 +:107780000DE094ED140A9FED171A80EE010A90EDBA +:10779000081AB4EE410AF1EE10FA04DA002568B2D4 +:1077A00084F89C50B0BD94ED000A94ED261A90ED3B +:1077B000092A30EE410AB4EE420AF1EE10FA05DA77 +:1077C000204600F09BF8002568B2B0BD012084F887 +:1077D0009400022084F89C00F5E700BFDB0FC9C0CD +:1077E0009A99993E00007A44002843D0F0B581B0C0 +:1077F0002DED028B044680690779EFB19FED1F8A5A +:1078000004F5807504F51A762846FFF77BFB05F131 +:107810007800FFF777FB3046B0EE480AFEF7E2FA51 +:1078200006F14000B0EE480AFEF7DCFA013F05F130 +:107830003C0506F12006E7D104F5F870FFF762FB7E +:1078400004F50B70FFF75EFB9FED0C8A04F53A70B0 +:10785000B0EE480AFEF7C6FA04F54270B0EE480AE8 +:10786000FEF7C0FA0020BDEC028B01B0BDE8F0408D +:1078700040B27047FF2040B2704700BF00000000D8 +:10788000F0B170B504468069067966B104F580757B +:107890002846FFF74DFB05F17800FFF749FB013E55 +:1078A00005F13C05F4D104F5F870FFF741FB04F550 +:1078B0000B70FFF73DFB0020BDE8704040B2704701 +:1078C000FF2040B270470000A0B18169097951B131 +:1078D00000F1C802002300BF42F8043F0139936061 +:1078E00013619361F8D10021C0E93B11C0F8F41095 +:1078F00048B27047FF2148B2704700002DE9F04FB1 +:1079000081B02DED088B84B0824600284FF0FF0037 +:1079100000F048820E46002900F04482DAF8180090 +:107920009AF81C10047940F275770029C2F200071A +:1079300000F0D0809AF89000002800F0EA80022839 +:1079400000F06481012840F01582002C019673D06C +:107950009FEDACBA9FEDAC8AA000262400274FF41F +:107960002A764FF000084FF000090290DAF818006C +:107970009AED3E1A0119897A0139C9B200EB8100EA +:1079800090ED020A5FFA89F120EE010A504680EE7E +:107990000B9AFFF7FFFC0AEB08050AEB070BD5ED86 +:1079A0002A0ADAED041AB0EE40AA0BF58070B0EEA8 +:1079B000490AB0EE481AFFF7A5F9DAF8180085ED84 +:1079C000330A2044807AD5ED2A0A0AEB800090ED34 +:1079D0002B0ADAED041A05F1CC010BF5BC70B0EE00 +:1079E000481A0391FFF78EF903982AEE000A05F171 +:1079F000D40185ED350AFFF7B1FC95ED330A95ED1D +:107A0000351A0AEB060030EE010A85ED370AFEF75B +:107A100059F9DAF8180085ED390A20440230FEF7EA +:107A20009BFD029808F1040809F101090A343C376A +:107A3000404506F1200699D14CF25000C2F20100F7 +:107A40009FEDE98A90ED000ADAED041ADAED300ACA +:107A50000AF5F870B0EE481AFFF754F9DAED041A97 +:107A6000DAED320A0AF50B70B0EE481A8AED3B0ADD +:107A7000FFF748F90AF542708AED3C0AFEF722F951 +:107A8000DAF818008AED3D0A3C30FEF765FD019EEC +:107A90007078002800F08D8140F27577C2F20007FF +:107AA0003878002840F06981B078002800F06581BE +:107AB0009AF81C00022103288AF8901000F08781B0 +:107AC000022800F08981012840F050810120AAF8A5 +:107AD000BC0052E16CB104EB84004400002500BFFF +:107AE000DAF8180028442830FEF72EFD0A35AC429B +:107AF000F6D1DAF818003C30FEF726FD9AED300A90 +:107B00004CF25000C2F201008AED3F0A80ED000AFB +:107B100033E10196BCB304EB84009FEDB38A4FEAD6 +:107B2000400800274FF480796FF0030B4FF42A745C +:107B30000AEB09063046FFF7FBF90AEB0B05D5ED1A +:107B40002B0ADAED041A3046B0EE480AB0EE481AB5 +:107B5000FFF7D8F80AEB040085ED340A85ED380A02 +:107B6000FEF7B0F8DAF8180085ED3A0A3844283004 +:107B7000FEF7F2FC0A3709F13C090BF1040BB8459A +:107B800004F12004D4D14CF25000C2F201009FED68 +:107B9000968A90ED000ADAED041ADAED300A0AF559 +:107BA000F870B0EE481AFFF7ADF8DAED041ADAED26 +:107BB000320A0AF50B70B0EE481A8AED3B0AFFF75D +:107BC000A1F80AF542708AED3C0AFEF77BF8DAF874 +:107BD00018008AED3D0A3C30FEF7BEFC019E40F2E3 +:107BE00075777078C2F20007002800F0C680504612 +:107BF000FFF7FAFD5046FFF743FE5046FFF764FEDD +:107C00000120B8E000C0DA450000000050463146CF +:107C10000196FFF7FDFB002C70D09FED72BA9FED2F +:107C2000728AA00026244FF000084FF42A7900271A +:107C300000260290DAF818009AED3E1A0119897AA6 +:107C40000139C9B200EB810090ED020AF1B220EED9 +:107C5000010A504680EE0B9AFFF79CFB0AEB0705E2 +:107C60000AEB080BD5ED2A0ADAED041AB0EE40AAA9 +:107C70000BF58070B0EE490AB0EE481AFFF742F8F3 +:107C8000DAF8180085ED330A2044807AD5ED2A0A07 +:107C90000AEB800090ED2B0ADAED041A05F1CC0115 +:107CA0000BF5BC70B0EE481A0391FFF72BF8039860 +:107CB0002AEE000A05F1D40185ED350AFFF74EFBE7 +:107CC00095ED330A95ED351A0AEB090030EE010AFD +:107CD00085ED370AFDF7F6FFDAF8180085ED390A69 +:107CE00020440230FEF738FC0298043701360A348B +:107CF00008F13C08B84209F120099BD19FED3A8A6E +:107D0000DAED041ADAED300A9AED3F0A0AF5F87056 +:107D1000B0EE481AFEF7F6FFDAED041ADAED320A91 +:107D20000AF50B70B0EE481A8AED3B0AFEF7EAFF3F +:107D30000AF542708AED3C0AFDF7C4FFDAF8180034 +:107D40008AED3D0A3C30FEF707FC019E40F2757754 +:107D5000B078C2F2000780B901208AF89000DAF802 +:107D6000C0004CF25001C2F2010108600020AAF8E4 +:107D7000BC0002E000208AF89000DAF818002830F1 +:107D8000FEF7B6FADAF818004168052902D3503038 +:107D9000FEF7AEFADAF818003C30FEF7A9FAB07830 +:107DA0003870002040B204B0BDEC088B01B0BDE8D3 +:107DB000F08F5046FFF718FD5046FFF785FD002075 +:107DC00040F275778AF89000C2F20007D5E741F6D5 +:107DD0000A20AAF8BC00D0E7DAF818008069AAF8EF +:107DE000BC00CAE700C0DA450000000000280EBF52 +:107DF000FF200177002040B270470000002800F00B +:107E0000DC802DE9F04381B02DED068B8146806941 +:107E10000079002858D09FED6A8A4FEA8008302602 +:107E200000274FF41A752424B7EE009ABFEE00AA7B +:107E30002FE000BF09EB040090ED000A09EB0500FC +:107E4000FDF740FF80EE081A09EB070080ED280AD5 +:107E5000043720351034B4EE491AF1EE10FAC8BFD9 +:107E6000B0EE491AD9F81810B4EE4A1AF1EE10FA29 +:107E7000B8BFB0EE4A1A895D80ED2A1A09EB81007D +:107E800090ED2B0A0A3630EE010AB84580ED2B0A38 +:107E90001AD0D9F8180030440838FEF7ADFBD9F8ED +:107EA000180030440838FEF7C1FA0028C2D000F1AB +:107EB0002C0C09EB87019CE80C10806B01F1200E63 +:107EC0008EE80C10C862B5E7D9F818003C30FEF710 +:107ED00093FBD9F818003C30FEF7A8FA014609F1E7 +:107EE00040005022F8F7ABFAD9F8180099ED221AA1 +:107EF00090ED030A20EE010AB5EE400AF1EE10FA09 +:107F000089ED300A0BDA9FED2F1A00BF30EE010A1F +:107F1000B5EE400AF1EE10FAF8DB89ED300A99ED82 +:107F2000300A9FED281AB4EE410AF1EE10FA0ADB8E +:107F30009FED252A30EE020AB4EE410AF1EE10FA66 +:107F4000F8DA89ED300A99F8680000281CBF31EE94 +:107F5000400A89ED300A99ED130A09F53A70FDF7E8 +:107F6000B1FE99ED131A9FED192AB7EE003A81EE92 +:107F7000021A89ED310A99ED090A99ED0D2A0020BE +:107F800030EE420AB4EE431AF1EE10FAC8BFB0EE7A +:107F9000431ABFEE003AB4EE431AF1EE10FAB8BF3E +:107FA000B0EE431A89ED321A89EDCA0ABDEC068B90 +:107FB00001B0BDE8F04340B27047FF2040B27047C7 +:107FC00000C0DA45DB0FC940DB0FC9C000007A45AD +:107FD00080B501F045FC01F0A1FC80BDB0B50138D1 +:107FE0000024B4EB106F1CBF0120B0BD4EF2100591 +:107FF000CEF2000568604FF0FF300F2101F06EF8FF +:108000000720AC6028602046B0BD000080B5FCF7BA +:1080100089F803F0A1FC012818BF02F073FE80BDAF +:1080200070B592B006AC20463021F8F742FA002530 +:1080300043F640000595CDE90355CDE9015500957E +:10804000C4F202000168022641F08051016000681C +:1080500000F080500090009847F200000095C4F2B4 +:108060000000016841F480410160006800F4804034 +:1080700000900098012006904FF4803007904FF454 +:1080800080000D9006200E90A820CDE90F06042058 +:10809000119020460C96FCF7E5F988B90F20CDE940 +:1080A00001064FF4A05004904FF48050059001A8B1 +:1080B00005210395FCF7C8F8002804BF12B070BD75 +:1080C000FAF7A6FA4EF68850CEF20000016841F4A5 +:1080D0007001016070470000B0B540F6FF3E0568D2 +:1080E000C4F2000E40F2004C7045C4F2010C0FDCEB +:1080F000B0F1804F19D040F20043C4F2000398421F +:1081000013D040F60003C4F2000398420DD011E0F2 +:1081100040F60043C4F20003984206D0604504D004 +:108120000023C4F20103984204D14B6825F0700289 +:1081300043EA020541F6FF73C4F2000398420DDCE6 +:1081400070451FDCB0F1804F41D040F20043C4F2D3 +:10815000000398423BD040F6000321E043F6FF7352 +:10816000C4F20103984220DC42F20003C4F200038F +:1081700098422CD00023C4F20103984227D06045D6 +:1081800025D029E040F60043C4F2000398421ED0F7 +:1081900041F60003C4F20003984218D041F60043B0 +:1081A000C4F20003984212D016E044F20003C4F275 +:1081B000010398420BD044F60003C4F20103984235 +:1081C00005D044F20043C4F20103984204D1CB68C5 +:1081D00025F4407243EA02050A688C684B69C46260 +:1081E00040F480648262644504BF096901630268E7 +:1081F00025F0800142F0040219430260012242612D +:108200000160B0BD80B501F01F014FF0010CD0F846 +:1082100020E00CFA01F32EEA03030362036A02FA78 +:1082200001F11943016280BDB0B5026A036A40F2F0 +:10823000004523F001030362D0F804E0D0F818C031 +:108240008C6822F0020240F48063C4F20105AB4264 +:1082500042EA040205D1CC6822F00C0224F00404A6 +:1082600022430C68AB4207D1D1E905532EF4407E7E +:1082700045EA0E0545EA030E2CF073032343C0F8CC +:1082800004E08361496841630262B0BD70B5026A6F +:10829000036A40F2004423F010030362D0F804E0C4 +:1082A000D0F818C08D6822F0200240F48063C4F238 +:1082B0000104A34242EA051207D1CD686FF04006DF +:1082C00022F0C00206EA05152A430D68A34207D131 +:1082D000D1E905642EF4406343EA860343EA840E41 +:1082E0002CF4E64343EA0523C0F804E083614968BF +:1082F0008163026270BD000070B5026A036A40F2D9 +:10830000004423F480730362D0F804E0D0F81CC06A +:108310008D6822F4007240F48063C4F20104A34229 +:1083200042EA052207D1CD6840F2FF462D0222F431 +:108330004062B5432A430D68A34207D1D1E90564E1 +:108340002EF4405343EA061343EA041E2CF0730351 +:108350002B43C0F804E0C3614968C163026270BD89 +:1083600070B5D0F820C0026A40F2004622F4805274 +:1083700002624268C3690C68D1F808E040F4806585 +:10838000C4F20106B54204D14D6922F4804242EAAA +:10839000851223F4E64343EA04234260C3612CF4CC +:1083A0000056496846EA0E320164026270BD000060 +:1083B00010B500F0E1FF48F699204DF6FC12C0F62A +:1083C0000000C0F60002002101F04EFA4CF6607485 +:1083D000C2F20104206048F2E1704DF64812C0F686 +:1083E0000000C0F60002002101F03EFA606048F68D +:1083F000A1004DF69012C0F60000C0F60002002168 +:1084000001F032FAA06048F621004DF66C12C0F679 +:108410000000C0F60002002101F026FAE06048F2F8 +:10842000D9404DF60012C0F60000C0F6000200214F +:1084300001F01AFA206148F279504DF62412C0F684 +:108440000000C0F60002002101F00EFA606148F65B +:10845000F9104DF6D812C0F60000C0F60002002157 +:1084600001F002FAA06102200A21002201F01AF8AC +:10847000E06102205821002201F014F8206402205B +:108480003421002201F00EF8606202201421002243 +:1084900001F008F8A06202202821002201F002F871 +:1084A000206302206421002200F0FCFFA063022070 +:1084B0001921002200F0F6FF606302200321002250 +:1084C00000F0F0FF206200F087FF01F0C9F901F031 +:1084D00025FA10BD0000000000F036FF04F0C8FED1 +:1084E0009FED230B53EC102B04F0E8FC04F07CFE12 +:1084F0008146002000F0E0FE00F01CFF4CF66074A6 +:1085000040F2BC484CF2E40740F2284600EB090573 +:10851000C2F20104C2F20008C2F20107C2F2000670 +:1085200017E000BF3846F8F713FE3846F8F702FEAA +:1085300038463146F8F7A6FD606B01F04BF8606BEA +:1085400031460022002300F0FDFF284600F0C4FE63 +:108550004D44A06B41460022002300F05FFF00283D +:10856000E0D138464146F8F7B7FDDBE700BF00BF72 +:108570000000000000407F4082B000F0E5FE04F003 +:1085800077FE9FED910B53EC102B04F097FC04F059 +:108590002BFE0646002000F08FFE00F0CBFE4CF2D2 +:1085A0004815C2F2010540F208010446C2F200017A +:1085B0002846F8F72DFE2846F8F704FE4CF2A847A7 +:1085C000C2F201074CF20471C2F201013846F8F719 +:1085D00051F82846F8F7F6FDB7EE001A81EE000ACA +:1085E00040F238704DF64442C2F20000C0F600027C +:1085F0000021FEF73FFC0020F9F73EFC4CF2E06062 +:1086000040F2B0499FED72AAC2F201009FED718A5B +:108610009FED719A4CF2D04A4CF6607B019626444D +:1086200005F1100405F11C08C2F200091030C2F275 +:10863000010AC2F2010B00904BE000BFD5ED0A0A1F +:1086400040F23870C2F20000B0EE480AB0EE491AAB +:10865000F0EE491AFEF756FB0020F9F7DFFBD7E9E9 +:1086600002017A68CAF820002869CAF824106969EA +:10867000CAF82800A869CAF82C10E969CAF83000BD +:10868000286ACAF80010696ACAF80400D9F800001C +:10869000CAF80810D9F80410CAF80C00D9F8080074 +:1086A000CAF810103968CAF81400DBF82400CAF8B8 +:1086B0001810CAF81C2000F08DFFDBF8240051468A +:1086C0000022002300F03EFF304600F005FE019836 +:1086D0000644F8F7EBFEF8F761FDF8F76BFDF8F7E5 +:1086E00081FDF8F78DFD00F047FE2846F8F732FED1 +:1086F0002846F8F779FE4CF2047338462146424684 +:10870000C2F20103F8F77EF848463946F7F744FF0E +:1087100000F062FE4CF20070C2F201000068012815 +:108720008CD140F27C50C2F2000090ED000A95ED31 +:10873000071A4CF20451C2F2010195ED082A31EEFC +:10874000000A91ED001A40F2805240F24443C2F216 +:108750000002C2F2000395ED093A80ED000A32EE04 +:10876000011A92ED002A188833EE022A013081EDB9 +:10877000001A82ED002A81B241F2883291421880BB +:10878000FFF45CAF80EE0A0A81EE0A1A82EE0A2A32 +:108790004CF2007240F208010020C2F20102C2F263 +:1087A00000011060284681ED000A81ED011A81ED7B +:1087B000022AF8F72DFD2846F8F704FD00993846FF +:1087C000F7F758FF3AE700BF0000000000407F4085 +:1087D00000409C4500002042000000000000000016 +:1087E00000F0B2FD04F044FD9FED0B0B53EC102B99 +:1087F00004F064FB04F0F8FC0446002000F05CFD8B +:1088000000F098FD051900BF284600F065FD2544DD +:10881000FAE700BF00BF00BF0000000000407F403B +:1088200000F092FD04F024FD9FED1B0B53EC102B88 +:1088300004F044FB04F0D8FC0446002000F03CFDAA +:1088400000F078FD40F25845C2F200050646284681 +:10885000F9F7D2FD4CF660772644C2F201070FE02B +:108860002846F9F7EDFD386C00F0B4FE386C294667 +:108870000022002300F066FE304600F02DFD264465 +:108880002846F9F78FFE1420F9F79CFE0028E7D060 +:108890002846F9F7E3FDE6E70000000000407F40CE +:1088A00086B000F051FD04F0E3FC9FED4F0B53EC5C +:1088B000102B04F003FB04F097FC0646002000F0A8 +:1088C000FBFC00F037FD0446F9F7E2FC4CF298158A +:1088D000C2F201059FED460A01462846FAF73EF925 +:1088E00040F24850C2F200004CF22C1AC2F2010AC7 +:1088F00000F10C011430059626444CF66079039083 +:1089000040F234544CF2BC470AF10100C2F20109B2 +:10891000C2F20004C2F2010705F1240B05F52A7822 +:1089200002900AF10500049101902AE078786070C5 +:10893000D7E90101C4E901012846FAF787FA284678 +:108940002146F9F7BDFE2846FAF7B0F9D9F830000C +:1089500000F040FED9F8300059460022002300F014 +:10896000F1FDD9F8380000F035FED9F8380041465D +:108970000022002300F0E6FD304600F0ADFC059833 +:108980000644D9F8240040F24851C2F20001002206 +:10899000002300F043FD30B940F248512846C2F2AE +:1089A0000001FAF7DFFAD9F834005146002200231B +:1089B00000F034FD9AF8000020B1022808D1DDE96A +:1089C000010101E0DDE9030109680068C4E9031061 +:1089D000D9F8280039460022002300F01FFD0028A6 +:1089E000A4D138782070A1E70000000000407F404B +:1089F0000000FA430000000000F0A6FC04F038FC80 +:108A00009FED230B53EC102B04F058FA04F0ECFB11 +:108A10008046002000F050FC00F08CFC4CF66077A3 +:108A20004CF6D03640F220594CF6284400EB0805AD +:108A3000C2F20107C2F20106C2F20009C2F2010449 +:108A4000386C31460022002300F0E8FC48463146ED +:108A5000F9F7E2FD20463146FEF740FDB86A00F026 +:108A6000B9FDB86A49460022002300F06BFD386A60 +:108A700000F0B0FD386A21460022002300F062FDBC +:108A8000284600F029FC4544DAE700BF00BF00BFDC +:108A90000000000000407F4000F056FC04F0E8FBBE +:108AA0009FED210B53EC102B04F008FA04F09CFB13 +:108AB0000446002000F000FC00F03CFC0646F9F7FC +:108AC000E7FB4CF63045C2F201059FED190A00F5AF +:108AD000C4712846FEF74CFD284601214FF00108DD +:108AE000FFF784F94CF6607940F62C072644C2F271 +:108AF0000109C2F2000700BFD9F820003946002260 +:108B0000002300F08BFC284687F80080FFF776F9F9 +:108B100028463946FEF7F6FC304600F0DDFB2644D9 +:108B2000EAE700BF00BF00BF0000000000407F4038 +:108B30000000FA4380B5806B0021C185FCF71CFD65 +:108B400080BD000010B5846B2068406994F8411026 +:108B5000212907D110F0800004D00020E0842046B5 +:108B600000F0C2F82068406994F84210222907D129 +:108B700010F0400004D00020E085204600F080F88E +:108B8000606C40F0100060642046FCF7F5FC10BDFE +:108B900080B50168806B0968C9052FD40021C185A3 +:108BA000016851E8031F026821F4807142E8031351 +:108BB000002BF5D1016851E8051F026821F0010181 +:108BC00042E80513002BF5D1016851E8051F026842 +:108BD00021F0400142E80513002BF5D1202180F857 +:108BE0004210016B012909D1016851E8031F026895 +:108BF00021F0100142E80313002BF5D1002141635D +:108C0000016B012903D1818DFCF7B4FC80BDFCF719 +:108C100085FF80BD80B5806B01214163016B012917 +:108C200004D1818D4908FCF7A5FC80BDFCF78AFFC3 +:108C300080BD000080B50168806B0968C90516D445 +:108C40000021C184016851E8051F026821F08001FC +:108C500042E80513002BF5D1016851E8031F0268B3 +:108C600041F0400142E80313002BF5D180BDFCF731 +:108C7000DFFF80BD80B5806BFCF7EEFF80BD00009C +:108C8000016851E8031F026821F4907142E8031360 +:108C9000002BF5D1016851E8051F026821F00101A0 +:108CA00042E80513002BF5D1016B01290AD100BF61 +:108CB000016851E8031F026821F0100142E8031324 +:108CC000002BF5D1202180F842100021016370476C +:108CD00080B50168CA6822F04002CA60202180F88D +:108CE0004110FCF7A5FF80BD016851E8031F026831 +:108CF00021F0C00142E80313002BF5D1202180F8B8 +:108D000041107047006844F60001C4F20001884237 +:108D100004BF0320704741F20001C4F20101884200 +:108D200004BF0020704741F20041C4F201018842B3 +:108D300014BF05200220704780B582B090F8421021 +:108D400022291ED18268B2F5805F02D10169002913 +:108D50004AD0816AB2F5805F07D00AB9026922B1B0 +:108D60000268526802F07F0201E0026852680A70ED +:108D70000121826A11448162C18D01390A04C185D1 +:108D800001D002B080BD0168CA6822F02002CA602A +:108D9000CA6822F48072CA604A6922F001024A61FC +:108DA000202180F8421000214163026B012A23D167 +:108DB000016300BF016851E8031F026821F0100140 +:108DC00042E80313002BF5D101680A68D20606D5E4 +:108DD000002201920A680192496801910199818DEE +:108DE000FCF7C8FB02B080BD0168826A49686FF376 +:108DF0005F2111800221BCE7FCF790FE02B080BD2C +:108E000010B504460068D4E902C22369016921F45F +:108E1000405111430161626943EA0C01E369114366 +:108E2000C268194349F20C639A431143C160416916 +:108E3000A26921F4407141F20043114340F4806281 +:108E4000C4F201039A42416102D1FBF7C5FA01E085 +:108E5000FBF7B0FAE16963681922B1F5004FA0FB96 +:108E600002011CD15A00DB0FF7F72CFA48F21F5110 +:108E7000C5F2EB11A0FB01235A096FF0630302FB5B +:108E80000300322303EBC000A0FB01014FF4F87094 +:108E900000EA111000EB0210C1F342111AE09A002F +:108EA0009B0FF7F70FFA48F21F51C5F2EB11A0FB29 +:108EB00001235A096FF0630302FB0300322303EB23 +:108EC0000010A0FB0101F02000EA511000EB02109D +:108ED000C1F3431122680843906010BDF0B581B022 +:108EE000134600270446816283854764222084F864 +:108EF0004200E06B48F6913548F615460A4621686F +:108F0000C0F60005C0F60006C0E90F5648F6453623 +:108F1000C0F600060431C0E91367FAF7B5FE38B1B0 +:108F200010206064202084F84200012001B0F0BDD0 +:108F300000972068016800914068009000982069BF +:108F400050B100BF206850E8030F216840F48070E2 +:108F500041E80302002AF5D1206850E8050F216896 +:108F600040F0010041E80502002AF5D1206850E8F0 +:108F7000050F216840F0400041E80502002AF5D1C4 +:108F8000002001B0F0BD0000816200218285C28511 +:108F90004164222180F84210016921B10168CA6848 +:108FA00042F48072CA600168486940F0010048617B +:108FB000C86840F020020020CA60704790F8411055 +:108FC000212923D18168B1F5805F01D1016931B1D7 +:108FD000016A02684B1C03620978516007E0016A6C +:108FE000036831F8022B6FF35F225A600162C18C73 +:108FF00001390A04C18418BF70470068C16821F0B4 +:109000008001C160C16841F04001C160704700004B +:1090100010B54CF24864C2F201042046FCF7C0FAD5 +:109020002046F8F7EBFF10BD80B540F2A860C2F211 +:109030000000FCF7B5FA80BD10B540F2F064C2F252 +:1090400000042046FCF7ACFA2046F8F7D7FF10BD25 +:10905000FEE7000000F0FF40B0F1FF4018BF012024 +:109060007047000000F0FF40B0F1FF4018BF012042 +:109070007047000020F00040A0F1FF40B0FA80F0FF +:1090800040097047002848BF704700F01F010122C7 +:1090900002FA01F14EF280124009CEF2000242F8CB +:1090A0002010BFF34F8FBFF36F8F7047002848BF6A +:1090B000704700F01F01012202FA01F14EF2001286 +:1090C0004009CEF2000242F8201070474EF60C50D4 +:1090D000CEF200000068C0F3022070474EF6145331 +:1090E00000F00F02CEF2000309011A4400F16043C0 +:1090F000B0F1FF3FC8BF03F5644211707047000034 +:109100004EF61F50CEF200000021017070470000A3 +:109110004EF60C51CEF200010A684FF6FF031A40DA +:1091200060F30A2242F0806040F0FD7008607047F2 +:1091300040F6DB7110EE100AC3F6C97161F31E0030 +:1091400000EE100A70470000F0B581B0F0B104469F +:109150004CF26070C2F201000068A0421FD001F022 +:1091600019FA40F62000C2F20000656907684CF267 +:109170006470C2F20100066801F030FABD424FF09F +:10918000020018BFB5420DD101B0F0BD4FF0500044 +:1091900080F31188BFF36F8FBFF34F8FFEE700207E +:1091A00001B0F0BD4DF6C800C2F2010085420CD0FE +:1091B0004AF6C8010120C2F20101002D08BF0420B7 +:1091C0008D4208BF042001B0F0BDA06A10B102209A +:1091D00001B0F0BD94F858100320012908BF022007 +:1091E00001B0F0BD4FF0FF3101FA00F0C04302EED4 +:1091F000100A30EE600AB8EEC22A31EE601A20EE94 +:10920000020A80EE010ABDEEC00A10EE100A704795 +:10921000FAF796FFFEF704FFFDF7E6FAFDF790FA7E +:10922000FDF74EFAFDF76CFAFDF7C2FBFDF72CFCDB +:10923000FDF746FCFDF760FCFDF79AFBFDF77EFCB1 +:10924000FDF7DEFB00F084F8FDF7B0FA00F0AAF8B5 +:10925000FEE700000146C068B6EE002A90ED4E1A07 +:1092600090ED4D0A21EE021A30EE010A002081ED48 +:10927000130A7047401A811000EE101A9FED0B1A66 +:10928000B8EEC00A30EE011A9FED0A2A0C28C8BFBA +:10929000B0EE410A9FED061AB4EE420A30EE011A12 +:1092A000F1EE10FAB8BFB0EE410A7047DB0FC9C04B +:1092B000DB0FC940DB0F49C0EFF3058100291CBF5C +:1092C0006FF005007047002804BF0020704780B58C +:1092D00001F064FA002080BD10B582B0EFF3058183 +:1092E00019B16FF0050002B010BD044602F048FB52 +:1092F000211A0129019005DB01A801F079FA00206B +:1093000002B010BD6FF0030002B010BD80B502F0D6 +:1093100023FB022808BF80BD08B9032080BD4CF2A2 +:109320004C00C2F2010000680138B0FA80F0400938 +:1093300080BD000080B5EFF3058010B102F026FB80 +:1093400080BD02F01DFB80BD4FF47A7070470000B5 +:10935000EFF3058000281CBF6FF0050070474CF24A +:109360004C00C2F201000168002911BF4FF0FF302C +:10937000012101600020704780B5EFF305800028CF +:109380001CBF6FF0050080BD02F0E6FA28B102288C +:1093900005D101F0D7FB002080BD012080BD4FF03A +:1093A000FF3080BD10B5EFF3058000281CBF6FF0C3 +:1093B000050010BD4CF24C04C2F2010420680128E3 +:1093C0001CBF4FF0FF3010BDFDF7C4FF022020602E +:1093D00001F066FB002010BD10B5EFF3058018B159 +:1093E0006FF00504204610BD02F0B6FA02280ED038 +:1093F00080B902F0A3FC01284FF001040CD002F068 +:10940000ABFA002808BF4FF0FF34204610BD0024FF +:10941000204610BD4FF0FF34204610BD10B582B07D +:109420001C46B0FA80F3B1FA81F25B095209EFF3FE +:10943000058CBCF1000F42EA030219D0002C18BFC2 +:109440000124224315D10022019201AA01F05EFFFE +:1094500001281AD10198A8B14EF60450CEF20000AE +:109460004FF080510160BFF34F8FBFF36F8F09E062 +:109470001AB16FF0030002B010BD224601F084FE65 +:10948000012806D1002002B010BD6FF0020002B02A +:1094900010BD6FF00100002C08BF6FF0020002B099 +:1094A00010BD0000B0B582B0144600294FF0000591 +:1094B000EFF3058218BF002802D1284602B0B0BDE4 +:1094C000002AFAD19CB1A568D5B1E268502A16D31A +:1094D0002269A2B1D4F814C001FB00F20023944524 +:1094E0004FF0000228BF012210D24DB10EE001233F +:1094F00000226AB9E3B1002201F03AFC0EE01DB986 +:10950000E2680AB92269C2B100220023002AF1D020 +:10951000A36822690025009501F04EFC054655B16F +:10952000002C14BF21680021284601F001F9C4E78E +:109530000025002DF4D10025BFE76269B2FA82F25E +:109540005309D5E7B0B582B01C46B0FA80F3B1FA42 +:1095500081F5EFF305825B096D09002A43EA0502F4 +:1095600007D0002C18BF0124224306D06FF003055A +:109570002CE0CAB16FF0030528E00022019201AA95 +:10958000002301F077FD01281CD10198E8B14EF6C7 +:109590000450CEF200004FF080510160BFF34F8FB6 +:1095A000BFF36F8F002511E022460023002501F054 +:1095B0008FFC01280AD06FF00105002C08BF6FF066 +:1095C000020503E06FF0020500E00025284602B026 +:1095D000B0BD000010B5EFF3058119B16FF00504BF +:1095E000204610BD00280FBF6FF0030400210024A7 +:1095F00001F02EFC204610BD10B50C46EFF305819E +:1096000000291CBF6FF0050010BD014620F00100CD +:1096100050B111F001010AD1214601F0CDFE01281F +:1096200004BF002010BD09E06FF0030010BD21460B +:1096300001F0A6FF012804BF002010BD6FF001005B +:10964000002C08BF6FF0020010BD000070B5EFF3F2 +:109650000581B9B90028044614BF606800200107DD +:1096600010D494B1A36843B1E26800214F2A4FF0AF +:10967000000288BF01220AD84BB9E168B1FA81F132 +:10968000490903E00025284670BD0121002200F0B1 +:1096900001063AB1A168002E0CBF0120042001F0A0 +:1096A00055FB06E0C9B1002E0CBF0120042001F0DB +:1096B00041FB054635B1002C14BF21680021284626 +:1096C00001F036F8B5FA85F0400986F0010108434B +:1096D00008BF45F00105284670BD0025002DEAD1E0 +:1096E000F0E7000080B5EFF3058100291CBF6FF0A3 +:1096F000050080BD014620F0010040B111F00101DC +:1097000008D100210022002301F0E2FB04E06FF009 +:10971000030080BD01F016FD013818BF6FF0020094 +:1097200080BD0000B0B584B048B3B1F1FF3F26DD85 +:1097300004464FF0FF300390EFF3058018B3002587 +:109740000DF1080C2046012200230295CDF800C03F +:1097500002F066F803AB204600210022009502F0DB +:109760005FF80298D0B14EF60450CEF200004FF0F0 +:1097700080510160BFF34F8FBFF36F8F0EE06FF02A +:10978000030003900AE020460122002301F0CAFFF3 +:1097900003AB20460021002201F0C4FF039804B06F +:1097A000B0BD00002DE9F04F83B00C46EFF305810A +:1097B00029B16FF00507384603B0BDE8F08F0546C4 +:1097C000002849D44FF0000B9246A00758BFAB4683 +:1097D00002F0D6F800906FF0010804F00100544642 +:1097E0000027BAF1000F08BF6FF00208019002E0F5 +:1097F0004746002EDFD00020594602AA234602F039 +:1098000079F906460128F3D1029807EA050140EAF2 +:1098100001090198002809EA050007D100286FF026 +:10982000020718BF4F4607D0C5E700BFA8426FF038 +:10983000020708BF4F46BED0BAF1000FBBD002F0FE +:109840009FF800994F46401A241A4FF0000038BF85 +:109850000446002ECFD1AEE76FF00307ABE7000060 +:1098600080B502F073F880BD70B584B08E460021DB +:1098700000280391EFF3058146D0002944D1FAB1C5 +:109880009369002B08BF1823382B16D81179C90704 +:1098900013D15569946811684FEA950C002D08BFE3 +:1098A0004FF0800CFCB1D6685C2E1BD3D5B1156986 +:1098B000C5B10024012555B91BE0002004B070BDDE +:1098C0000124002118234FF0800C00258DB19468ED +:1098D00012690294CDE900326246734601F0E6FE59 +:1098E000039011E00CB9D4689CB100250024002D30 +:1098F000EDD14CB103AC00931FFA8CF27346019486 +:1099000001F0A0FE012802D1039804B070BD002030 +:10991000E6E71469B4FA84F46409D6E710B5EFF306 +:10992000058100291CBF6FF0050010BD044660B121 +:109930002046FFF709FC042804BF6FF0020010BDA9 +:10994000204600F0A9FF002010BD6FF0030010BDFD +:10995000F0B581B00D464DF6DC014CF26076C2F2F6 +:109960000101C2F201060F6831680446081D00F0CB +:109970009DFD601C0AD14DB13068011D4DF6C80037 +:10998000C2F2010000F0EEFD01B0F0BD3068E41954 +:1099900044600AD34CF26470C2F20100006831687E +:1099A000043100F0C1FD01B0F0BD40F62000C2F26C +:1099B000000000683168043100F0B6FD4AF6680026 +:1099C000C2F2010001688C4238BF046001B0F0BDF2 +:1099D00070B5044600F0DEFD4AF2D010C2F201007C +:1099E00001684CF2607501310160C2F2010529681D +:1099F0004DF6BC06C2F2010641B1306860B9286874 +:109A0000E16AC06A884298BF2C6005E02C6000685B +:109A1000012801D100F0DEF94AF2D810C2F20100AB +:109A200001680131016061644AF2DC11C2F2010196 +:109A3000E06A0A68904288BF08604CF26C7100EBE3 +:109A40008000C2F2010101EB8000211D00F08AFDBF +:109A500000F0C4FD306880B12868E16AC06A8842BD +:109A600028BF70BD4EF60450CEF200004FF080517A +:109A70000160BFF34F8FBFF36F8F70BD70B582B0C1 +:109A800000F088FD4AF6DC06C2F20106306850BBE1 +:109A90004DF68004C2F20104204600F035FD4AF67E +:109AA0003C05C2F20105284600F02EFD40F61C00E0 +:109AB000C2F2000004604CF26870C2F2010040F291 +:109AC00076724CF2107305600025C2F20002C2F2F9 +:109AD00001030A201021009501F06EF9306010B1E9 +:109AE00003A100F025FE00F079FD02B070BD00BFBB +:109AF000546D725100000000F0B581B04DF62005A4 +:109B0000C2F201052868E0B14AF6C8064AF2D01749 +:109B1000C2F20106C2F2010700F03CFDF068C46821 +:109B2000201D00F0C3FC386801383860286801380F +:109B3000286000F053FD204600F058F828680028FF +:109B4000EAD101B0F0BD000080B5026C002A08BF68 +:109B500080BDD0E902C31344C360634524BF0368DA +:109B6000C360C36808461946F6F724FC80BD0000B0 +:109B700070B5866B036C0446E3B115461AB3E06812 +:109B80001A46F6F717FCE168206C2268091A914220 +:109B9000E16003D2A16840420844E060A81EB0FA28 +:109BA00080F040093146002E18BF01210840361AC6 +:109BB000002516E02068002598B9A06801F0E2FFB2 +:109BC000A56005460DE060681A46F6F7F3FB216CC8 +:109BD000D4E90102002508446060904224BF206857 +:109BE0006060711C2846A16370BD000010B504467A +:109BF00090F85900022808BF10BD012803D030B9E1 +:109C0000206B00F003FD204600F000FD10BD4FF07A +:109C1000500080F31188BFF36F8FBFF34F8F00BFE9 +:109C2000FEE70000416A00290FBF0020006B0068BA +:109C3000C0F138007047000040F61C01C2F200017C +:109C400009680A68B2FA82F35B090360002A0EBF52 +:109C50000020C8680068704740F63400C2F2000077 +:109C6000C21D22F0070210F0070CA0EB020318BF80 +:109C700010464DF6C002C2F201020021C2E9000105 +:109C800049F69912C0F20102BCF1000F18BF1A4444 +:109C90000244083A40F6240322F00702C2F200030D +:109CA0001A60C2E90011111A1A68C0E900214AF6C7 +:109CB0006400C2F2010001604DF6AC00C2F2010086 +:109CC00001604DF69400C2F201000121017070475D +:109CD0004CF26C744EF60455C2F20104CEF200054B +:109CE0004FF08056FFF708FF20680228FAD32E6055 +:109CF000BFF34F8FBFF36F8FF4E70000002808BF5A +:109D0000704780B500210160C0E9021100210022E6 +:109D1000002301F0DDF8BDE880407047B0B5049D38 +:109D2000002914BF2A602D60C5E90F0128460121D2 +:109D30001C4601F08DF885F84C40B0BD2DE9F04788 +:109D40000A9C8246206B16460F46DDE908599100B1 +:109D5000A5229846F6F7A5FB206B00EB8600A0F144 +:109D6000040020F007067FB104F13400002100BF99 +:109D70007A5C42547A5C1AB10F2901F10101F7D3E0 +:109D8000002084F8430002E0002084F8340000271B +:109D9000201D372D28BF3725E562C4E9135700F091 +:109DA000BFFB04F1180000F0BBFBC5F13800A06157 +:109DB00030465146424624616462676584F85870B3 +:109DC00000F04AFBB9F1000F206018BFC9F800404D +:109DD000BDE8F087B0B54CF26C750024C2F2010505 +:109DE000281900F091FB1434B4F58C6FF8D14DF6BE +:109DF0009804C2F20104204600F086FB4AF65005A2 +:109E0000C2F20105284600F07FFB4AF67400C2F258 +:109E1000010000F079FB4AF6C800C2F2010000F030 +:109E200073FB4DF6C800C2F2010000F06DFB40F676 +:109E30002000C2F2000004604CF26470C2F2010023 +:109E40000560B0BD80B54DF6C002C2F2010200BF90 +:109E5000114612688242FBD3D1F804C001EB0C0317 +:109E6000834203D14068604448600846D0F804C08B +:109E700000EB0C03934201D013460BE040F62403A1 +:109E8000C2F200031B689A4204D0D2E9003E0EEBF6 +:109E90000C0242608142036018BF086080BD000070 +:109EA00080B58C46014641F804CF9445006108D93D +:109EB0009A4201D29C4511D240F61C00C2F2000029 +:109EC00007E08069D21A824208D24CF26870C2F26E +:109ED0000100006800F028FB002080BD012080BD4B +:109EE00010B5044600F056FBA06BB0FA80F04409B0 +:109EF00000F074FB204610BD10B5044600F04AFB8C +:109F0000A06BE16B401AB0FA80F0440900F066FBE8 +:109F1000204610BD08480068006880F308884FF0AC +:109F2000000080F3148862B661B6BFF34F8FBFF3B1 +:109F30006F8F00DF00BF00BF08ED00E070B582B09A +:109F400040F61C02C2F2000212680546D2680E46B4 +:109F5000D468201D00F0AAFA94F82800410704D420 +:109F600000F0FE0084F8280010E0A0693246411994 +:109F700020462B46FFF794FF40B1002620460021E3 +:109F80002A460023009601F09DFF20B1216A204659 +:109F9000884702B070BD4FF0500080F31188BFF3C6 +:109FA0006F8FBFF34F8F00BFFEE700002DE9F04138 +:109FB00086B04AF6DC07C2F20107386802A900221F +:109FC0004FF0000801F0E0F800286AD001AC02ADC3 +:109FD0000BE000F0FE0086F8280000BF3868294634 +:109FE000002201F0D1F800285BD00298B0F1FF3FC9 +:109FF00003DCDDE903200599904702980028EDD4A1 +:10A00000049E706910B1301D00F050FA204600F037 +:10A01000B3F802990929E1D80246DFE801F00808FF +:10A0200008052A390808052A96F82800D1E796F885 +:10A030002800039BB16940F0010086F8280019440C +:10A040003046FFF72DFF0028C8D0316A30468847D8 +:10A0500096F828004007C1D50398B16900230A1873 +:10A0600030460021CDF8008001F02CFF0028B5D14A +:10A0700023E096F8280040F00101039886F82810A4 +:10A08000B06188B1811830461346FFF709FFA5E794 +:10A0900096F8280081073FF59CAF304600F0B6FAED +:10A0A0009CE706B0BDE8F0814FF0500080F31188C6 +:10A0B000BFF36F8FBFF34F8FFEE74FF0500080F379 +:10A0C0001188BFF36F8FBFF34F8F00BFFEE7000013 +:10A0D00070B582B00E46044600F034FD01A800F0D1 +:10A0E0004BF8019919B101F029FE02B070BD054687 +:10A0F0004EB9A54207D301F021FE20462946FFF7BD +:10A100001DFF02B070BD4EB14CF26870C2F201008A +:10A1100000680068B0FA80F0420900E000224AF6C8 +:10A12000DC00C2F201000068611B00F015FB01F0C9 +:10A1300005FE0028D9D14EF60450CEF200004FF0B3 +:10A1400080510160BFF34F8FBFF36F8F02B070BDBE +:10A1500040F62000C2F200000168096821B10068E1 +:10A16000C068C068406801E04FF0FF304AF66801FF +:10A17000C2F201010860704770B5044601F000FCAE +:10A1800040F61806C2F2000631680546884203D23E +:10A1900000F008F8012000E000202060284635602B +:10A1A00070BD00002DE9F04182B040F61C07C2F2FC +:10A1B00000073868016891B34FF0000809E000BF5C +:10A1C000606038682946246100F0AEF9386801689B +:10A1D00029B3C068C4680668251D284600F066F9E2 +:10A1E000216A2046884794F828004007EED5A069E8 +:10A1F0003044B042E4D82046002132460023CDF856 +:10A20000008001F05FFE0028E0D14FF0500080F3A5 +:10A210001188BFF36F8FBFF34F8F00BFFEE74CF283 +:10A220006871C2F201010A6808603A6002B0BDE8D4 +:10A23000F081000081B00020009040F23830C2F27E +:10A24000000000684FF0500181F31188BFF36F8F59 +:10A25000BFF34F8F013001D0FEE700BF0098002808 +:10A26000FCD001B07047000082B001AC2046FFF77F +:10A27000E3FC0199FFF72CFFFFF798FEF6E70000DB +:10A28000F0B581B0044600F085F994F94560012EDF +:10A290000FDB04F1240500BF286850B1284601F007 +:10A2A00005FD002818BF00F067FB70B2013E0128D1 +:10A2B000F2DCFF2684F8456000F090F900F06AF9BE +:10A2C00094F94470012F0EDB04F11005286850B199 +:10A2D000284601F0EBFC002818BF00F04DFB78B2D7 +:10A2E000013F0128F2DC84F8446000F077F901B006 +:10A2F000F0BD00002DE9F04381B0044600F022FCDF +:10A3000040F62406C2F200063068002808BFFFF7B6 +:10A31000A3FC4DF69408C2F2010898F8000000284A +:10A3200018BF4FF0004020420DD0002401F006FD80 +:10A3300060071ED04FF0500080F31188BFF36F8F7D +:10A34000BFF34F8FFEE7C4B114F0070004F108011A +:10A350001EBF081A00F108015FEA41700ED04FF0ED +:10A36000500080F31188BFF36F8FBFF34F8F00BF92 +:10A37000FEE7204601B0BDE8F08300214DF6AC09B0 +:10A38000C2F20109D9F800004A1E8242CDD24DF630 +:10A39000C000C2F2010005682F4657F8042F8A4218 +:10A3A00011D22B685BB100BF1F4657F8042F284617 +:10A3B0001D468A4207D22B68002BF5D103E04DF6EB +:10A3C000C000C2F2010033689D42AED004682B6821 +:10A3D000521A112A036010D36818430709D04FF0AE +:10A3E000500080F31188BFF36F8FBFF34F8F00BF12 +:10A3F000FEE742603960FFF725FD4AF664003968E0 +:10A40000D9F80020C2F201000368511A9942C9F834 +:10A41000001038BF016098F80000396800284FF03C +:10A42000000018BF41F0004128604DF6B800C2F2AC +:10A430000100026808343960511C016076E70000B1 +:10A440004CF26070C2F20100016819B101680A6D36 +:10A4500001320A650068704703464AF23520C0F6AB +:10A4600000004FF0807C21F0010103E903106FF040 +:10A47000020043F8240CA3F1440043F8202C704759 +:10A4800002EE100A4FF0FF30884030EEC01AB8EEEE +:10A49000C22AC04321EE021A02EE100AB8EEC22A06 +:10A4A00081EE021A31EE000A70470000D0E9013255 +:10A4B00001699A60D1F804C082688445536008BF7E +:10A4C0004A60002202610868013808600868704725 +:10A4D0004DF62403C2F2010303604AF2E010C2F217 +:10A4E0000100086080201060704700004AF2E073AD +:10A4F000C2F2010303604AF2E030C2F201000860D8 +:10A500004FF48070106070474FF0FF31024642F800 +:10A51000081F00214260C0E903220160704700006B +:10A52000002101617047000080B5D1F800C01CF126 +:10A53000010207D000F108039E465B681A68624575 +:10A54000FAD901E0D0F810E0DEF8042008614A6092 +:10A550009160C1F808E0CEF8041001680131016093 +:10A5600080BD0000D0F800C0436808619A684B6065 +:10A570008A609A68996051600CF10101016070472E +:10A58000DFF80C00016841F470010160704700BF02 +:10A5900088ED00E04FF0500080F31188BFF36F8F1B +:10A5A000BFF34F8F40F23830C2F2000001684A1CFE +:10A5B000026001B170474EF60450CEF20000006810 +:10A5C000000608BF70474FF0500080F31188BFF3BA +:10A5D0006F8FBFF34F8F00BFFEE7000040F23830AF +:10A5E000C2F20000016839B10139016018BF70473B +:10A5F000002080F3118870474FF0500080F31188DD +:10A60000BFF36F8FBFF34F8FFEE70000B0B5002898 +:10A6100008BFB0BD04464DF69400C2F201000078B8 +:10A6200054F8041C002818BF4FF0004008420CD01A +:10A63000A4F108052A6892B14FF0500080F3118808 +:10A64000BFF36F8FBFF34F8FFEE74FF0500080F3E3 +:10A650001188BFF36F8FBFF34F8F00BFFEE721EA72 +:10A66000000044F8040C00F06DFA4DF6AC01C2F2A3 +:10A67000010154F8040C0A68104408602846FFF7EA +:10A68000E1FB4AF66C00C2F2010001680131016091 +:10A6900001F054FBB0BD00004EF21000CEF20000FD +:10A6A00000210160816040F20001C2F200010968EE +:10A6B00044F6D352C1F26202A1FB02124FF0FF3105 +:10A6C00001EB92114160072101607047EFF30580B3 +:10A6D000102814D34EF2F031CEF20001405C4AF261 +:10A6E000CD11C2F201010978884208D24FF0500022 +:10A6F00080F31188BFF36F8FBFF34F8FFEE74EF6E5 +:10A700000C50CEF200004DF618010068C2F20101B3 +:10A71000096800F4E060884298BF70474FF050002D +:10A7200080F31188BFF36F8FBFF34F8FFEE70000F8 +:10A730004AF6880C0022C2F2010C00BF5CF83230ED +:10A7400023B10132082A08BF7047F7E70CEBC203B8 +:10A750004CF832105860704770B515460E460446E6 +:10A76000FFF718FF94F84400FF2804BF002084F886 +:10A77000440094F84500FF2804BF002084F84500F9 +:10A78000FFF72CFFA06B28B904F1240031462A46BC +:10A7900000F014F92046FFF773FD70BD10B5D8B175 +:10A7A00004464AF2D410C2F20100006848B14FF0EA +:10A7B000500080F31188BFF36F8FBFF34F8F00BF3E +:10A7C000FEE700F0BFF920460021FFF7C1F801F0D5 +:10A7D000B5FA002818BF10BD4EF60450CEF20000A6 +:10A7E0004FF080510160BFF34F8FBFF36F8F10BDEB +:10A7F000B0B590B10D46D1B104464AF2D410C2F2C0 +:10A8000001000068E8B14FF0500080F31188BFF3F9 +:10A810006F8FBFF34F8F00BFFEE74FF0500080F304 +:10A820001188BFF36F8FBFF34F8F00BFFEE74FF06C +:10A83000500080F31188BFF36F8FBFF34F8F00BFBD +:10A84000FEE700F07FF94DF6DC00C2F2010000687F +:10A850002268904202EB050102D2914202D309E044 +:10A86000914201D3814205D92160081A0021FFF7E6 +:10A870006FF800E0216001F061FA002818BFB0BD58 +:10A880004EF60450CEF200004FF080510160BFF34D +:10A890004F8FBFF36F8FB0BD70B50446FFF77AFEE0 +:10A8A0004CF26076002CC2F2010608BF3468251D08 +:10A8B0002846FFF7FBFDA06A18B104F11800FFF766 +:10A8C000F5FD4AF2D810C2F20100016801310160C1 +:10A8D000306884420CD04AF2D010C2F20100016804 +:10A8E000013901602046FFF781F9FFF731FC0DE0E7 +:10A8F0004AF6C800C2F201002946FFF733FE4DF6C2 +:10A900002000C2F20100016801310160FFF766FE1C +:10A910004DF6BC00C2F201000068E8B13068844224 +:10A9200018BF70BD4AF2D410C2F20100006840B1F5 +:10A930004FF0500080F31188BFF36F8FBFF34F8F3C +:10A94000FEE74EF60450CEF200004FF08051016059 +:10A95000BFF34F8FBFF36F8F70BD00004DF6B40192 +:10A96000C2F20101096801604DF6DC01C2F2010189 +:10A9700009684160704700004DF6E400C2F2010032 +:10A98000012101607047000010B568B10C464CF21F +:10A990006071C2F2010109681831FFF7C5FD204658 +:10A9A0000121FEF7D5FF10BD4FF0500080F3118854 +:10A9B000BFF36F8FBFF34F8FFEE70000B0B590B1CC +:10A9C0000D464CF26071C2F201010968144618315B +:10A9D000FFF7C8FD002C18BF4FF0FF352846214671 +:10A9E000FEF7B6FFB0BD4FF0500080F31188BFF303 +:10A9F0006F8FBFF34F8F00BFFEE7000070B528B325 +:10AA0000026D04461AB3E06C884238BF0846012A3A +:10AA10001CD1E16A814208BF70BD4CF26072C2F283 +:10AA200001021268A2421CD0A269E062002A5CBF47 +:10AA3000C0F13800A0614CF26C76606901EB8101D5 +:10AA4000C2F2010606EB8101884214D070BD4FF0BE +:10AA5000500080F31188BFF36F8FBFF34F8F00BF9B +:10AA6000FEE74FF0500080F31188BFF36F8FBFF304 +:10AA70004F8F00BFFEE7251D2846FFF717FD4AF25E +:10AA8000DC11C2F20101E06A0A68904288BF0860E6 +:10AA900000EB800006EB80002946FFF763FD70BDE8 +:10AAA00010B586B0002405A804A903AACDE9044482 +:10AAB000FFF70EFDDDE9032005990023CDE9010133 +:10AAC00049F6D140C0F600001CA1009400F0EEFD54 +:10AAD0004DF6B001C2F20101086010B101F0B8F901 +:10AAE0000446601C20D0012C1CD14FF0500080F394 +:10AAF0001188BFF36F8FBFF34F8F4AF66800C2F221 +:10AB000001004FF0FF3101604DF6BC00C2F20100C0 +:10AB1000012101604DF6DC00C2F20100002101605C +:10AB200000F066F806B010BD4FF0500080F31188B9 +:10AB3000BFF36F8FBFF34F8FFEE700BF49444C4513 +:10AB4000000000004AF2D410C2F201000168013195 +:10AB5000016070474AF2D410C2F20100006830B1BF +:10AB60004DF6E400C2F201000121016070474DF68C +:10AB7000E400C2F2010000214AF2DC1C0160C2F2D2 +:10AB8000010CDCF800104CF26C7201EB8103C2F294 +:10AB9000010252F8230048B902EB8300A0F114032C +:10ABA000D9B153F8140901390028F9D001EB81001B +:10ABB00002EB800252F8040F4368101D83421360B9 +:10ABC00001D15868106010684CF26072C068C2F21F +:10ABD00001021060CCF8001070474FF0500080F375 +:10ABE0001188BFF36F8FBFF34F8F00BFFEE70000E8 +:10ABF00080B582B04EF20040CEF200004CF27021DF +:10AC0000C4F20F11D0F800294B1C9A4209D14FF021 +:10AC1000500080F31188BFF36F8FBFF34F8F00BFD9 +:10AC2000FEE7D0F800298A4209D14FF0500080F3A6 +:10AC30001188BFF36F8FBFF34F8F00BFFEE701781E +:10AC40004AF2CD120191FF2101700178C2F2010296 +:10AC50008DF803109DF8031001F0500111704DF6AE +:10AC60001801C2F2010107220A609DF90320B2F126 +:10AC7000FF3F0CDC0A6800BF9DF80330013A5B001F +:10AC80008DF803309DF90330002BF5D40A600A6873 +:10AC9000032A2DD14FF4E06303EA02220A600199EE +:10ACA0000170D0F8201941F47001C0F82019D0F8D3 +:10ACB000201941F07041C0F82019FFF7EDFC40F277 +:10ACC0003830C2F2000000210160FFF759FC4EF657 +:10ACD0003470CEF20000016841F040410160FFF79E +:10ACE00019F9FFF737FFFFF7A5FA002002B080BD82 +:10ACF0004FF0500080F31188BFF36F8FBFF34F8F79 +:10AD0000FEE7000080B54FF0500080F31188BFF3DC +:10AD10006F8FBFF34F8F00F043FE30B14EF60450FB +:10AD2000CEF200004FF080510160002080F31188C6 +:10AD300080BD000010B502460120002100F018F887 +:10AD40000446FEF7DBFF204610BD000010B582B0C0 +:10AD50000B468446012000210022CDF800C000F0FF +:10AD60002BF80446FEF7CAFF204602B010BD0000D3 +:10AD7000F0B581B0B0B105464843503014460E4698 +:10AD8000FFF7B8FA074650B1002007F1500287F8E4 +:10AD900046002846314623460097FEF7BFFF384657 +:10ADA00001B0F0BD4FF0500080F31188BFF36F8FFA +:10ADB000BFF34F8FFEE70000B0B582B068B11D460B +:10ADC000ABB1F1B9EAB14FF0500080F31188BFF395 +:10ADD0006F8FBFF34F8F00BFFEE74FF0500080F33F +:10ADE0001188BFF36F8FBFF34F8F00BFFEE74FF0A7 +:10ADF000500080F31188BFF36F8FBFF34F8F00BFF8 +:10AE0000FEE751B14AB94FF0500080F31188BFF30B +:10AE10006F8FBFF34F8F00BFFEE750230193019B5D +:10AE2000502B0AD1069B019C012485F846400095D1 +:10AE3000FEF774FF284602B0B0BD4FF0500080F31B +:10AE40001188BFF36F8FBFF34F8F00BFFEE7000085 +:10AE500070B5F8B104460E46FFF79CFB2068D4E9B4 +:10AE60000F12002502FB0103013901FB0201A5635A +:10AE7000C4E90103FF20E16084F8440084F8450040 +:10AE800004F110007EB1FFF73FFB04F12400FFF74F +:10AE90003BFB18E04FF0500080F31188BFF36F8F39 +:10AEA000BFF34F8FFEE7016869B100F0FFFE50B1BC +:10AEB0004EF60450CEF200004FF080510160BFF317 +:10AEC0004F8FBFF36F8FFFF789FB012070BD00002C +:10AED0002DE9F04F83B00292B8B11D460E460446EC +:10AEE000E9B1022D03D1E06B012840F09A8000F017 +:10AEF00033FD00BB0298F0B14FF0500080F3118891 +:10AF0000BFF36F8FBFF34F8FFEE74FF0500080F31A +:10AF10001188BFF36F8FBFF34F8F00BFFEE7206C28 +:10AF20000028DED04FF0500080F31188BFF36F8F00 +:10AF3000BFF34F8FFEE7FFF72DFBA06B022D58D01C +:10AF4000E16B884255D304F1100801206F464FF0A1 +:10AF5000000B0DF108094FF0805A00BF029900293B +:10AF600000F07B80C00702D03846FFF7F7FCFFF700 +:10AF700035FBFFF7E7FDFFF70DFB94F84400FF28D2 +:10AF800008BF84F844B094F84500FF2808BF84F84F +:10AF900045B0FFF723FB3846494600F00FFB002879 +:10AFA0005ED12046FEF7A8FFA0B102994046FFF708 +:10AFB000EBFC2046FFF764F900F0C0FE78B94EF6CE +:10AFC0000450CEF20000C0F800A0BFF34F8FBFF3D3 +:10AFD0006F8F04E02046FFF753F900F0AFFEFFF754 +:10AFE000D9FAA06B022D04D0E16B88424FF000002B +:10AFF000B4D2204631462A46FEF7BAFD54F8241F43 +:10B00000C9B1204600F052FE08B34EF60450CEF20D +:10B0100000004FF080510160BFF34F8FBFF36F8F7F +:10B0200015E04FF0500080F31188BFF36F8FBFF32E +:10B030004F8F00BFFEE750B14EF60450CEF2000035 +:10B040004FF080510160BFF34F8FBFF36F8FFFF759 +:10B05000C5FA012003B0BDE8F08FFFF7BFFA04E0A6 +:10B060002046FFF70DF900F069FE002003B0BDE8AF +:10B07000F08F00002DE9F04381B0E8B11E46914603 +:10B0800005460F4609B3022E02D1E86B012837D1DD +:10B09000FFF71CFBEFF311884FF0500080F311888D +:10B0A000BFF36F8FBFF34F8FA86B022E19D0E96BE0 +:10B0B000884216D300203FE04FF0500080F3118803 +:10B0C000BFF36F8FBFF34F8FFEE7286C0028DAD0F5 +:10B0D0004FF0500080F31188BFF36F8FBFF34F8F95 +:10B0E000FEE795F84540A86B284639463246FEF7FC +:10B0F0003FFDFF2C0DD0601C85F8450001201BE0B2 +:10B100004FF0500080F31188BFF36F8FBFF34F8F64 +:10B11000FEE755F8240F70B1284600F0C7FD014640 +:10B12000B9F1000F4FF0010006D000291CBF01202B +:10B13000C9F8000000E0012088F3118801B0BDE8E3 +:10B14000F0830000B0B5A8B18568044600F0FEFBAE +:10B1500085421CBF0020B0BDE0680138E0601CBF24 +:10B160000120B0BD2046002100220023FFF7B0FEE1 +:10B170000120B0BD4FF0500080F31188BFF36F8FF6 +:10B18000BFF34F8FFEE700002DE9F04F85B004922A +:10B1900098B10C460546002900F0A58000F0DCFBC4 +:10B1A000A8B9049898B14FF0500080F31188BFF30C +:10B1B0006F8FBFF34F8F00BFFEE74FF0500080F35B +:10B1C0001188BFF36F8FBFF34F8F00BFFEE705F10C +:10B1D000240005F11009019002AF0DF1100A4FF0A3 +:10B1E00000080AE02846FFF74BF800F0A7FD2846C4 +:10B1F000FEF776FE002840F08480FFF7CBF9D5F803 +:10B2000038B0BBF1000F1DD028462146FEF79CFC4C +:10B21000ABF10100A863286970B1484600F046FD13 +:10B2200050B14EF60450CEF200004FF08051016054 +:10B23000BFF34F8FBFF36F8FFFF7D0F900200126C8 +:10B24000A0B95FE0049850B1B8F1000F02D13846C0 +:10B25000FFF784FB4FF00108012038B952E0FFF7F7 +:10B26000BDF90026002000284CD000BFFFF7B6F93A +:10B27000FFF768FCFFF78EF995F84400FF2804BF3C +:10B28000002085F8440095F84500FF2804BF002001 +:10B2900085F84500FFF7A2F93846514600F08EF9CF +:10B2A00000289FD12846FEF71BFEB0B104990198F3 +:10B2B000FFF76AFB2846FEF7E3FF00F03FFD00289A +:10B2C0009BD14EF60450CEF200004FF08051016049 +:10B2D000BFF34F8FBFF36F8F8FE72846FEF7D0FF86 +:10B2E00000F02CFD89E7286C00283FF457AF4FF0A1 +:10B2F000500080F31188BFF36F8FBFF34F8F00BFF3 +:10B30000FEE70026304605B0BDE8F08F2DE9F0439A +:10B3100081B000B3914605460E4631B3FFF7D6F92A +:10B32000EFF311884FF0500080F31188BFF36F8F57 +:10B33000BFF34F8FAC6B24B395F844702846314669 +:10B34000FEF702FC601EFF2FA8631CD0781C85F856 +:10B35000440001202AE04FF0500080F31188BFF331 +:10B360006F8FBFF34F8F00BFFEE7286C0028D5D04A +:10B370004FF0500080F31188BFF36F8FBFF34F8FF2 +:10B38000FEE7002012E055F8100F70B1284600F0DB +:10B390008DFC0146B9F1000F4FF0010006D00029E5 +:10B3A0001CBF0120C9F8000000E0012088F31188CB +:10B3B00001B0BDE8F08300002DE9F04F85B00491A5 +:10B3C00058B10446006C90B14FF0500080F31188E2 +:10B3D000BFF36F8FBFF34F8FFEE74FF0500080F346 +:10B3E0001188BFF36F8FBFF34F8F00BFFEE700F0F0 +:10B3F000B3FA50B9049840B14FF0500080F311886F +:10B40000BFF36F8FBFF34F8FFEE704F1240004F109 +:10B41000100501904FF0000802AF0DF1100A4FF037 +:10B4200000094FF0000B0AE02046FEF729FF00F06C +:10B4300085FC2046FEF754FD002840F07F80FFF792 +:10B44000A9F8A06BF0B10138A063206810B9FEF72D +:10B45000F7FFA060286870B1284600F027FC50B1C3 +:10B460004EF60450CEF200004FF080510160BFF361 +:10B470004F8FBFF36F8FFFF7B1F801260020B8B9E7 +:10B480006FE000BF049850B1BBF1000F02D1384605 +:10B49000FFF764FA4FF0010B012048B961E0B9F100 +:10B4A000000F62D1FFF79AF800200026002858D03C +:10B4B000FFF794F8FFF746FBFFF76CF894F84400A9 +:10B4C000FF2808BF84F8448094F84500FF2808BF8F +:10B4D00084F84580FFF782F83846514600F06EF850 +:10B4E0000028A1D12046FEF7FBFC28B92046FEF734 +:10B4F000C7FE00F023FCA2E7206838B9FFF74AF83E +:10B50000A06800F089FB8146FFF768F8049901986C +:10B51000FFF73AFA2046FEF7B3FE00F00FFC0028D2 +:10B520007FF48DAF4EF60450CEF200004FF0805104 +:10B530000160BFF34F8FBFF36F8F80E7B9F1000F4A +:10B540000ED0FFF727F82046FEF76CFBA1680246F5 +:10B5500008461146FFF752FAFFF740F8002600E0D0 +:10B560000026304605B0BDE8F08F4FF0500080F364 +:10B570001188BFF36F8FBFF34F8F00BFFEE700004E +:10B5800070B568B1866804460D4600F0DFF9864262 +:10B590000FD020462946FFF70FFF58B9002070BD95 +:10B5A0004FF0500080F31188BFF36F8FBFF34F8FC0 +:10B5B000FEE70120E1680131E16070BDB0B5D0B1B6 +:10B5C0000D4611B30446FEF7E5FF4DF6DC00C2F26E +:10B5D000010001682868421C21D04DF6B40362685E +:10B5E000C2F20103D3F800C091421AD323689C45EC +:10B5F00017D0012422E04FF0500080F31188BFF3F0 +:10B600006F8FBFF34F8F00BFFEE74FF0500080F306 +:10B610001188BFF36F8FBFF34F8F00BFFEE7002489 +:10B620000CE0891A884206D9401A28602046FFF7A4 +:10B6300095F9002402E0002001242860FEF7CEFFE7 +:10B640002046B0BD2DE9F04383B0074690009846F0 +:10B6500015468946FEF74EFE78B106465C20FEF799 +:10B6600049FE38B10446066354B94FF0FF3003B0C9 +:10B67000BDE8F0833046FEF7C9FF0024002CF4D06B +:10B68000DDE90A10002284F85920CDE9001038467F +:10B6900049462A4643460294FEF750FB2046FEF7F1 +:10B6A00097F9012003B0BDE8F083000070B586B0C3 +:10B6B0000B9CCCB10C9E06B35C250495049D5C2DBF +:10B6C00025D1049DDDF828C0022586F8595005AD26 +:10B6D0003463CDE900C50296FEF730FB3046FEF735 +:10B6E00077F9059806B070BD4FF0500080F31188CF +:10B6F000BFF36F8FBFF34F8FFEE74FF0500080F323 +:10B700001188BFF36F8FBFF34F8F00BFFEE74FF07D +:10B71000500080F31188BFF36F8FBFF34F8F00BFCE +:10B72000FEE70000F0B581B0D0B11D4617460446D3 +:10B730000E46FEF72FFF002D1CBF606D286094F8A9 +:10B7400058000221042F84F8581012D80125DFE890 +:10B7500007F023031C262000616D314361651FE063 +:10B760004FF0500080F31188BFF36F8FBFF34F8FFE +:10B77000FEE7616D013113D04FF0500080F3118866 +:10B78000BFF36F8FBFF34F8FFEE7616D01316165CE +:10B7900006E0022803D1002501283CD103E06665BC +:10B7A0000125012837D1261D3046FEF77FFE4AF2DB +:10B7B000DC11C2F20101E06A0A68904288BF0860A9 +:10B7C0004CF26C7100EB8000C2F2010101EB8000D1 +:10B7D0003146FEF7C7FEA06A48B14FF0500080F333 +:10B7E0001188BFF36F8FBFF34F8F00BFFEE74CF29E +:10B7F0006071C2F20101E06A0968C96A88420AD927 +:10B800004EF60450CEF200004FF080510160BFF3BD +:10B810004F8FBFF36F8FFEF7E1FE284601B0F0BDFA +:10B820002DE9F04120B31D46174604460E46FEF7AB +:10B830004DFFEFF311884FF0500080F31188BFF3F4 +:10B840006F8FBFF34F8F002D1CBF606D286094F881 +:10B8500058000221042F84F8581012D80125DFE87F +:10B8600007F023031C262000616D314361651FE052 +:10B870004FF0500080F31188BFF36F8FBFF34F8FED +:10B88000FEE7616D013113D04FF0500080F3118855 +:10B89000BFF36F8FBFF34F8FFEE7616D01316165BD +:10B8A00006E0022803D10025012849D103E066659E +:10B8B0000125012844D1A06A48B14FF0500080F31F +:10B8C0001188BFF36F8FBFF34F8F00BFFEE74AF2BF +:10B8D000D410C2F20100006830B14AF6740004F1DD +:10B8E0001801C2F2010015E0261D3046FEF7DEFD0C +:10B8F0004AF2DC11C2F20101E06A0A68904288BF94 +:10B9000008604CF26C7100EB8000C2F2010101EBA7 +:10B9100080003146FEF726FE4CF26071C2F2010152 +:10B92000E06A0968C96A88420AD9069800281CBFDB +:10B93000012101604DF6E400C2F201000121016025 +:10B9400088F311882846BDE8F08100004CF2607051 +:10B95000C2F20100006870474DF6BC00C2F201005F +:10B960000068002804BF012070474AF2D410C2F2D8 +:10B9700001000068B0FA80F0400940007047000004 +:10B980004DF6DC00C2F201000068704780B5FEF79A +:10B990009DFE4DF6DC00C2F20100006880BD000093 +:10B9A0002DE9F04F81B04AF2D410C2F201000068D4 +:10B9B00040B14AF67000C2F2010001680024013172 +:10B9C000016092E04DF6DC00C2F2010001684E1CFD +:10B9D000066021D340F62000C2F200000168096829 +:10B9E00049B14FF0500080F31188BFF36F8FBFF360 +:10B9F0004F8F00BFFEE74CF26472C2F20102016891 +:10BA0000136803604DF6B4001160C2F201000168D2 +:10BA100001310160FEF79CFB4AF66801C2F20101A8 +:10BA200008684CF2607A4CF26C788642C2F2010AE5 +:10BA3000C2F2010801D2002445E040F62007C2F21C +:10BA4000000738680024006898B34AF2DC1BC2F291 +:10BA5000010B19E0D9F82C00DBF80010884288BFF0 +:10BA6000CBF8000000EB800008EB80002946FEF7D1 +:10BA700079FDD9F82C00DAF80010C96A3A688842D2 +:10BA800028BF01241068B8B13868C068D0F80C909D +:10BA90004D4655F8040F864210D32846FEF706FDA2 +:10BAA000D9F828000028D5D009F11800FEF7FEFCCF +:10BAB000D0E74FF0FF3005E04FF0FF304AF6680165 +:10BAC000C2F201010860DAF80000C06A00EB8000F1 +:10BAD00058F8200001284DF6E400C2F2010088BFAA +:10BAE00001240068002818BF0124204601B0BDE8E9 +:10BAF000F08F00002DE9F0411E46154688460746A6 +:10BB0000FEF748FD4CF26074C2F20104206890F820 +:10BB10005800022819D02068416D21EA07014165CB +:10BB200020684FF0010180F8581076B130460121AD +:10BB3000FDF70EFF4EF60450CEF200004FF080519C +:10BB40000160BFF34F8FBFF36F8FFEF747FDFEF726 +:10BB500021FD15B12068406D28602068002590F80F +:10BB600058100020022905D1216801254A6D22EADA +:10BB700008024A65216881F85800FEF72FFD284623 +:10BB8000BDE8F081B0B580B104464CF26070C2F2FD +:10BB900001000068A0420AD04FF0500080F31188E5 +:10BBA000BFF36F8FBFF34F8FFEE70020B0BD206D56 +:10BBB00038B3013820654FF0000018BFB0BDE16A0E +:10BBC000E26C91421CD0251D2846FEF76FFCE06C0C +:10BBD000C0F13801A1614AF2DC11E062C2F2010158 +:10BBE0000A68904288BF08604CF26C7100EB8000DC +:10BBF000C2F2010101EB80002946FEF7B3FC0120EF +:10BC0000B0BD4FF0500080F31188BFF36F8FBFF3CA +:10BC10004F8F00BFFEE70000F0B581B000B34CF2DB +:10BC20006076C2F201060446C06A3168C96A884279 +:10BC300019D2A169002904D43168C96AC1F1380157 +:10BC4000A1614CF26C77616900EB8000C2F20107E0 +:10BC500007EB800081420FD03068C06AE06221E0CB +:10BC6000002001B0F0BDE16C3068C26A0020914252 +:10BC700038BF012001B0F0BD251D2846FEF716FC97 +:10BC800030684AF2DC11C06AC2F20101E0620A685F +:10BC9000904288BF086000EB800007EB80002946D7 +:10BCA000FEF760FC012001B0F0BD0000B0B5C06837 +:10BCB000C5687DB105F118042046FEF7F7FB4AF28E +:10BCC000D410C2F20100006868B14AF67400C2F2F2 +:10BCD00001001DE04FF0500080F31188BFF36F8F1B +:10BCE000BFF34F8FFEE72C1D2046FEF7DFFB4AF225 +:10BCF000DC11C2F20101E86A0A68904288BF08605C +:10BD00004CF26C7100EB8000C2F2010101EB80008B +:10BD10002146FEF727FC4CF26071C2F20101E86A8D +:10BD20000968C96A884291BF00204DF6E401C2F259 +:10BD30000101012088BF0860B0BD00002DE9F04F6F +:10BD400081B04AF2D414C2F20104206868B1FEF74F +:10BD500021FC206801382060206880B10024FEF7B3 +:10BD60003DFC204601B0BDE8F08F4FF0500080F35D +:10BD70001188BFF36F8FBFF34F8F00BFFEE74AF20A +:10BD8000D010C2F20100006800285DD04AF67406A7 +:10BD9000C2F2010630684DF6E408C2F2010890B321 +:10BDA0004AF2DC174CF26C794CF2607BC2F201076C +:10BDB000C2F20109C2F2010B4FF0010AF068C56836 +:10BDC00005F11800FEF772FB2C1D2046FEF76EFBF6 +:10BDD000E86A3968884288BF386000EB800009EB68 +:10BDE00080002146FEF7BEFBE86ADBF80010C96A56 +:10BDF000884228BFC8F800A030680028DED1002D96 +:10BE000018BFFEF7A5F94AF67004C2F201042568CE +:10BE100055B10126FFF7C4FD002818BFC8F800601F +:10BE2000013DF7D100202060D8F8000070B14EF637 +:10BE30000450CEF200004FF080510160BFF34F8FED +:10BE40000124BFF36F8F8AE7002488E7002486E788 +:10BE500080B586B0FDF712FE4AF6DC00C2F20100A2 +:10BE6000006808B30020CDE9040005A804A903AACE +:10BE7000FEF73CFBDDE903200221DDF814C0CDE92B +:10BE800000104AF26920C0F600000CA10023CDF892 +:10BE900008C0FFF70BFC4DF6E001C2F2010108609B +:10BEA00010B1012006B080BD4FF0500080F3118822 +:10BEB000BFF36F8FBFF34F8FFEE700BF546D72204B +:10BEC0005376630010B584B0A8B14AF6DC04C2F220 +:10BED000010484462068C0B10529CDE90012CDF8DF +:10BEE00008C015DCFFF738FD01462068022916D18D +:10BEF000069A694615E04FF0500080F31188BFF3B1 +:10BF00006F8FBFF34F8F00BFFEE7002004B010BD5E +:10BF100069461A460023FFF7ADF804B010BD694624 +:10BF200000220023FEF7D4FF04B010BD03B4019833 +:10BF30004100009850EAC12018BF04204A0D18BFE4 +:10BF400040F0010040F2FF72B2EB515F08BF40F0D9 +:10BF50000200012808BF052002B070474100080216 +:10BF600018BF04200A0E18BF40F001004FF07F42B6 +:10BF700032EA010108BF40F00200012808BF052095 +:10BF80007047000010B54FF00E402DED028BB0EE63 +:10BF9000408A18EE104A00EB4400B0F1506F4AD8C6 +:10BFA0004FF0FC40B0EB440F22D2B0EEC80AF7EEDF +:10BFB000000A30EEC00AF6EE000A60EE208A18EEA3 +:10BFC000900A00F069FE01EE100A14F0004F1DBF48 +:10BFD000DFED2D0A9FED2D0AB1EE411ADFED2C0A9F +:10BFE00008BF9FED2C0AF8EE001A21EE218A05E029 +:10BFF000DFED290A68EE088AB0EE600A9FED271A85 +:10C00000DFED271A30EE080A48EE811A9FED251A57 +:10C0100008EEA11ADFED241A48EE811A9FED231ACB +:10C0200008EEA11A68EE281ABDEC028B01EE810A17 +:10C0300030EE200A10BD4FF0E440B0EB440F0CD9B5 +:10C0400018EE100AFFF78AFF042808BF00F05EFD13 +:10C05000B0EE480ABDEC028B10BD4FF07F40B0EB54 +:10C06000440F07D2B0EE480ABDEC028BBDE8104089 +:10C0700000F03EBD0120F4F74BFABDEC028BBDE8A9 +:10C08000104000F03BBD00000000C9BF22AAFDB96E +:10C090000000C93F22AAFD390000000024FE1C3D1B +:10C0A000C78AD83C1E67383D1B93993DAFAA2A3EEC +:10C0B00070B59B482DED020B2DED068B079D25F0ED +:10C0C0000044A04218DC9748844202DC0AD106985A +:10C0D00040B19DED060BBDEC068B02B0BDE8704093 +:10C0E00000F0E2BC002DCCBF9FED8F0B9FED900BBD +:10C0F000BDEC068B02B070BD8F48A04215DD8F48A5 +:10C10000A042D8BF4FF0FF3458DD9DED060B51EC37 +:10C11000100BFFF70BFF042808BF00F0D9FC9DEDC2 +:10C12000060BBDEC068B02B070BD9DED060B51EC0D +:10C13000100B00F0A5FDCDE9060181489FED828B33 +:10C14000A0423CDD8248A0421FDD00249FED82AB6F +:10C150009DED060B53EC1A2B51EC100B00F0FAFD81 +:10C160009DED060B41EC190B53EC1A2B51EC100B07 +:10C1700001F092F853EC182B01F098F953EC192BBD +:10C1800000F09CFECDE9060149E09DED060B01247F +:10C1900053EC182B51EC100B00F0DCFD9DED060B61 +:10C1A00041EC190B53EC182B51EC100B01F07EF9FC +:10C1B00053EC192B00F082FECDE906012FE0684810 +:10C1C000A0421FDD02249FED689B9DED060B53EC02 +:10C1D000192B51EC100B01F05FF853EC182B00F009 +:10C1E000B9FD9DED060B41EC180B53EC192B51ECEE +:10C1F000100B01F05BF953EC182B00F05FFECDE95A +:10C2000006010CE09DED060B032453EC102B9FED73 +:10C21000580B51EC100B00F051FECDE906019DEDDD +:10C22000060B53EC102B51EC100B01F035F841ECE0 +:10C23000180B53EC182B01F02FF841EC190B4E485A +:10C240000621B0EE490AF0EE690A784400F0B0FB2E +:10C2500053EC182B51EC100B01F01EF841EC180BAD +:10C260004648B0EE490AF0EE690A0521784400F02C +:10C270009FFB53EC192B51EC100B01F00DF841EC26 +:10C28000100B51EC180B53EC102B002C0EDA00F0B5 +:10C2900061FD9DED061B53EC112B00F0FDFF9DEDA4 +:10C2A000061B53EC112B01F0F5F835E000F052FDC0 +:10C2B0009DED061B53EC112B00F0EEFF41EC100B33 +:10C2C0002F48784400EBC40090ED001B51EC100B9C +:10C2D00053EC112B01F0EAF89DED061B53EC112BEA +:10C2E00001F0E4F841EC100B2648784400EBC40060 +:10C2F00090ED001B51EC100B53EC112B01F0CAF820 +:10C3000041EC100B002DA2BFBDEC068B02B070BD3E +:10C3100051EC100B00F0DFFC41EC100B01E70000CA +:10C32000000010440000F07F182D4454FB21F93F19 +:10C33000182D4454FB21F9BF0000DC3F0000203ED3 +:10C340000000F33F00000000000000000000F03F8C +:10C350000000E63F00000000000000000000004078 +:10C360000080034000000000000000000000F83FD3 +:10C37000000000000000F0BF0A160000C015000019 +:10C380004A1500000215000070B56F4E2DED040B2C +:10C390002DED048B82B0DDF824C0DDE907235C427B +:10C3A0002CF000411C4341EAD474069D22F0004069 +:10C3B000B44205D86C422C4340EAD474B4420BD941 +:10C3C0009DED081B9DED060B02B0BDEC048B04B087 +:10C3D000BDE8704000F072BBACF14054A4F17F6442 +:10C3E0001C430BD0022404EAAC7444EAD274054323 +:10C3F0009FED578B9FED582B07D015E09DED060B59 +:10C4000051EC100B00F034FC42E0002C11BF012C69 +:10C410009DED060B02B0BDEC048B04BF04B070BDF3 +:10C42000022C38D0032C3BD00B439FED4D1B9FEDCE +:10C430004E0B0AD0B14218D1B04209D121F080414F +:10C4400020F08040099107900FE0002A15DA10E0F3 +:10C45000474B7B44002C08BF93ED000B0DD0012C03 +:10C4600010D0022C17D0032C1AD0B0421DD1002AB4 +:10C4700003DAB0EE410AF0EE610A02B0BDEC048BC3 +:10C4800004B070BD93ED000B51EC100B00F023FCD9 +:10C4900041EC100BF1E7B0EE480AF0EE680AECE769 +:10C4A000B0EE420AF0EE620AE7E7401A00159FED8F +:10C4B000329B3C28C8BF8DED000B17DCBCF1000F90 +:10C4C000BCBF10F13C0F8DED009B0FDB9DED080B09 +:10C4D00053EC102B9DED060B51EC100B00F0EEFC15 +:10C4E00000F0CEFB00F0C4FBCDE90001B4B1012C9B +:10C4F00010D0022C9FED220B53EC102B9DED000B66 +:10C5000051EC100B19D000F0D1FF53EC182B00F0B8 +:10C51000CDFFBDE7019880F0004001909DED000B3C +:10C5200053EC192B51EC100B00F022FE04BF02203B +:10C53000F3F7EEFF9DED000B9FE700F0B7FF53EC24 +:10C54000182B00F0A7FFA3E70000F07F0000000019 +:10C55000182D4454FB210940182D4454FB2109C0D7 +:10C56000182D4454FB21F9BF182D4454FB21F93FE9 +:10C570003214000000000000000000000000000075 +:10C58000075C143326A6A13C70B54FF068422DED30 +:10C59000048BF0EE408A18EE900AB0EE608A18EE36 +:10C5A000101A02EB4003B3F1654F3CBF02EB4102AE +:10C5B000B2F1654F7DD200BFC0F3C753C1F3C7527C +:10C5C0009A1A1B2A09DD10F0004F14BF9FED830A51 +:10C5D0009FED830ABDEC048B70BD12F11A0F36DAA1 +:10C5E00011F0004F09D010F0004F0CBF9FED7D0AF5 +:10C5F0009FED7D0ABDEC048B70BD88EE889A19EE24 +:10C60000100AFFF7ABFC042808BF00F07FFA18EE11 +:10C61000900AFFF7A3FC054618EE100AFFF79EFCF0 +:10C62000044619EE100AFFF799FC042D18BF052DDA +:10C6300008D1042C18BF052C04D1002804BF022007 +:10C64000F3F766FFB0EE490ABDEC048B70BD420003 +:10C65000B2EB410F3AD910F0004F19BFDFED630A7A +:10C660009FED630ADFED630A9FED630AB0EE481A9F +:10C670000A46B1EE688A80F00041F0EE418A104629 +:10C680000A1A5200B2F1807F34D2484010F0004FB5 +:10C69000DFED5A1A9FED5A2A1DBFBEEE001A70EE4A +:10C6A000E10A30EE420AB6EE001A08BF70EEA10AA7 +:10C6B00000E040E008BF30EE020AB0EE682A01EE6A +:10C6C000482A08EE818AC2EE081A15E011F0004FE0 +:10C6D00004BF9FED4C0AF0EE400AD1D010F0004F9D +:10C6E00019BFDFED490A9FED490ADFED490A9FEDC9 +:10C6F000490AC5E7C8EE881A21EEA11A9FED462A1D +:10C70000DFED462A41EE022A9FED452A01EE222A5C +:10C71000DFED442A41EE022A9FED432ABDEC048B53 +:10C7200001EE222A21EE811A01EE020A30EE210AE0 +:10C7300030EE200A70BD4FF07F42B2EB400F28BFB1 +:10C74000B2EB410F09D2F0EE480AB0EE680ABDEC38 +:10C75000048BBDE8704000F0CEB940EA01035B00F5 +:10C7600008BF41F0FF410BD0B2EB400F08BFB2EB66 +:10C77000410F08D120F0804008EE900A21F080415E +:10C7800008EE101A18E7B2EB400F12BF5FEA410340 +:10C7900040F0FF4001F000413FF40EAFB2EB410F1B +:10C7A00012BF5FEA400200F0004041F0FF413FF459 +:10C7B00003AF4A0092EA40033FF5FEAE002AACBF49 +:10C7C0009FED1A0A9FED1A0A68EE808A28EE008A09 +:10C7D00018EE900A18EE101AEEE60000DB0FC9BF43 +:10C7E000DB0FC93FDB0F4940DB0F49C00000C9BF69 +:10C7F00022AAFDB90000C93F22AAFD390060ED3E22 +:10C80000C30ACE3700000000000049C022AA7DBA4A +:10C810000000494022AA7D3A2DAD65BD8FB8D53DB7 +:10C820000FB511BE61C84C3EA8AAAABE0000804F39 +:10C830000000802F00B510EE101A2DED028B81B094 +:10C840004D4A6846B2EB410F3CD94FF0E640B0EBA1 +:10C85000410F94BF00204FF0FF3000900098B0EEE1 +:10C86000408A00285FDB28EE080ADFED440A9FEDCE +:10C87000441A00EE201ADFED430A40EE010A9FED54 +:10C88000421A00EE201ADFED410A10F0010F40EECF +:10C89000010A9FED3F1A00EE201A61EE000AB0EE89 +:10C8A000480A08EE200A02BF01B0BDEC028B00BDB1 +:10C8B000BFEE001A01B0C1EE000ABDEC028BB0EE73 +:10C8C000600A00BD334B21F00042934228D911F099 +:10C8D000004FDFED310A20EE201ADFED300A19BFDC +:10C8E00031EE601A71EE200A31EE201A71EE600A04 +:10C8F000BDEEE01A11EE100A9FED291A00F00300B8 +:10C9000000EEC10A9FED271A009000EEC10A9FEDCC +:10C91000261A00EEC10A9FED251A00EEC10A9DE716 +:10C9200000F0FCF89AE718EE100A4000B0F17F4FD3 +:10C930000DD218EE100AFFF711FB042808BF00F013 +:10C94000E5F8B0EE480A01B0BDEC028B00BD09D19C +:10C950000120F3F7DDFD01B0BDEC028B5DF804EBC7 +:10C9600000F0CCB801B0B0EE480ABDEC028B5DF827 +:10C9700004EB00F0BDB80000B61F927EBCE9223C7B +:10C980000B6D063B8A76CE3CACB5593D35A1083ED1 +:10C9900029AAAA3E490E494683F9223F0000004BCE +:10C9A0000000C93F00A0FD390020A2331A61342CD9 +:10C9B00070B504462DED028B4D1E00EBC500B0EEA8 +:10C9C000408AF0EE608A90ED000B35F0060017D03B +:10C9D00053EC182B51EC100B00F05EFC41EC100BEB +:10C9E0006D1E04EBC50090ED001B51EC100B53ECD9 +:10C9F000112B00F0AFF941EC100B35F00600E7D138 +:10CA0000022D36D0042D1CD0062D1CBFBDEC028B90 +:10CA100070BD53EC182B51EC100B00F03DFC94ED65 +:10CA20000A1B53EC112B00F095F953EC182B00F076 +:10CA300033FC94ED081B53EC112B00F08BF941EC07 +:10CA4000100B53EC182B51EC100B00F025FC94ED5F +:10CA5000061B53EC112B00F07DF953EC182B00F062 +:10CA60001BFC94ED040B53EC102B00F073F941EC1C +:10CA7000100B53EC182B51EC100B00F00DFC94ED47 +:10CA8000021B53EC112B00F065F953EC182B00F04E +:10CA900003FC94ED001B53EC112B00F05BF9BDEC93 +:10CAA000028B41EC100B70BD10B553EC102B51EC08 +:10CAB000100B00F04FF941EC100B10BD10B553EC0A +:10CAC000112B51EC100B00F045F941EC100B10BD8F +:10CAD0009FED050B10B553EC102B51EC100B00F033 +:10CAE000DBFB41EC100B10BD00000000000000104B +:10CAF00030EE000A704730EE200A7047DFED020A80 +:10CB000080EEA00A70470000000000009FED020ABE +:10CB100020EE000A70470000000000102DE9F0012F +:10CB20004FF07F42B2EB410F9FBF4FF0FF310160EA +:10CB3000BDE8F00170474FF0004242EA0123C1F323 +:10CB4000C752783A551112F01F0C434CCCF1200615 +:10CB50007C44C1F3C752A2F178024FEA621204EB9F +:10CB6000820254F8254008BFD2E9015612D0556818 +:10CB700004FA0CF425FA06F73C43976805FA0CF51D +:10CB800027FA06F8D26807FA0CFCF24045EA0805D5 +:10CB90004CEA0206A4FB034CA5FB0352A6FB03636D +:10CBA0001D449D4234BF012600261319334416B19B +:10CBB000934202D903E0934201D2012200E0002215 +:10CBC000624402F1200C9206DC0C42EA443200EE90 +:10CBD000102A5B03DFED210AF8EEC01A00EE103ACE +:10CBE0004FEA9C1C11F0004FB8EE400AC0F800C09C +:10CBF00020EE201A00EE105ADFED190AB8EE400AB6 +:10CC000020EE200A71EE810A70EE800A10EE902A62 +:10CC100002F500626FF30B0200EE902A70EEE11A4B +:10CC200031EEC11ADFED101A30EE411A9FED0D0AF8 +:10CC300020EE800A01EE210A9FED0C1A00EE810A17 +:10CC400004BFBDE8F0017047CCF180510160BDE840 +:10CC5000F001B1EE400A70473C0D000000000036C4 +:10CC60000000802C22AAFD29DB0FC92F0000C92F4C +:10CC700010B541EC100BFFF71BFA51EC100B10BD77 +:10CC800082B0CDE9000121F0004001909DED000B44 +:10CC900002B051EC100B704710B500EE100A2DEDEC +:10CCA000028BB1EEC08A18EE100A20F00040C0F1ED +:10CCB000FF40C00F0AD010EE100A20F00040C0F173 +:10CCC000FF40C00F04BF0120F3F722FC18EE100A4A +:10CCD000BDEC028B10BD81F00041704780F0004038 +:10CCE000704721F00041704720F00040704700007D +:10CCF00021F0004201F00043A2F16052B2F5801F22 +:10CD000028BFD2F17F6C0BD95FEA001C43EAC20254 +:10CD100042EB507018BF704728BF20F001007047E9 +:10CD2000B2F5801FBCBF184670474FEA410C1CF596 +:10CD3000001F02D2084600F055BD70B500F056FB4A +:10CD400000000089FFF7F6BF4FF00040A0F580001B +:10CD50007047000010B591EA030F48BF83F000430D +:10CD600000F1AC83841A71EB030C05D2121943EB6A +:10CD70000C03001B61EB0C014FEA1154A4EB135C94 +:10CD8000DFF81CE11EEA430F18BF9EEA445F00F083 +:10CD9000748021EA045123EA0E0343F48013DCF18A +:10CDA000200E32D322FA0CFE10EB0E0023FA0CFEFA +:10CDB00041EB0E01CCF1200E03FA0EFE10EB0E003B +:10CDC000CCF1200E51F10001B1F5801F32D201EB00 +:10CDD000045112FA0EF2BDE8104058BF7047401CD3 +:10CDE00038BF5FEA420218BF7047002814BF20F026 +:10CDF000010041F100014FEA410313F5001F38BF64 +:10CE00007047A1F1C04100F03FBB012A43EB030290 +:10CE1000ACF1200CDCF11F0E32BF4FF0000E23FAF4 +:10CE20000CF310EB030041EB0451B4EB115FD0D0D5 +:10CE3000A1EB045101F58011490801EB04515FEAAF +:10CE400030000ED350F1000038BF12FA0EFE08D1A8 +:10CE5000BDE81040C9E7401C38BF5FEA4202CAD1B2 +:10CE6000C3E7BDE810404FEA410313F5001F38BF88 +:10CE70007047A1F1C04100F007BB9EEA445F08D0B3 +:10CE800011EA5E0FBDE8104004BF01F00041002030 +:10CE90007047BDE8104070B500F0A8FA64FBBE3ED4 +:10CEA0000000E0FF491058BFC1F140415B1058BF7E +:10CEB000C3F140438B42EFF3008070472DE9C0413E +:10CEC00030B4DFF8A4C23CEA111418BF3CEA1314D2 +:10CED00000F0ED801CEA111481EA030544EAD574E0 +:10CEE00018BF1CEA131500F0C880A4EB050404F178 +:10CEF0007F7404F500344FF0004545EAC12145EA4E +:10CF0000C32341EA505143EA52534FEAC0204FEA4B +:10CF1000C222994208BF904200F09D804FEA1365FB +:10CF20000FF24416765D4FEA134506FB05F7C7F18D +:10CF3000807706FB07F74FEAD737A7FB03687642EF +:10CF4000A7FB06CEC8F5803838BFA8F1010807FB5B +:10CF500008E6A6FB028C4FF0000EE6FB03CEDCF1E8 +:10CF6000000CCEF1004E38BFAEF1010EA6FB0C58FE +:10CF70004FF00007E6FB0E87A1FB08C6A0FB07CE1B +:10CF800016EB0E064FF0000545F10005E1FB0765C5 +:10CF900015F1E04E7EBFA4F580345FEA46066D4190 +:10CFA00016F1800745F100054FEA172747EA0567A4 +:10CFB0004FEA15254FEA0666A6F1DE46B6F1805F18 +:10CFC00020D9384605EBC47124F0010C01EB0C119B +:10CFD000BCF1FE6F02D8F0BCBDE8008124425CBF0A +:10CFE00001F5801E9EEAC47F02D4F0BCBDE800813A +:10CFF000244200F13980A1F1C041F0BCBDE80041FC +:10D0000000F042BA4FEAD02040EA41504FEAD12125 +:10D010004FEAD22242EA43524FEAD323A7FB0286C9 +:10D0200007FB036605FB02661EEA0E0F58BFA6EB60 +:10D030000056B6EB00564FEA520E4EEAC37E18EB8E +:10D040000E0E56EB530EBCD518EB02085E417F1C4A +:10D0500055F10005B5E74FF480154FF000074FF08C +:10D0600000064FF00008ACE701F1C04101F00041BB +:10D070004FF00000F0BCBDE800810CEA131511EA86 +:10D080000C1F00D00CE013EA0C1F00F026804FF0BC +:10D09000000081EA030101F00041F0BCBDE800811D +:10D0A000F0BCBDE8004181EA030100F0EDB9F0BC3D +:10D0B000BDE8004170B500F099F900BF097EFC3E63 +:10D0C00000F007B84FF0000081EA030101F00041D1 +:10D0D000704781EA030100F0D7B9F0BCBDE8004118 +:10D0E00022494FF000007047FFFDFBF9F7F5F4F21D +:10D0F000F0EEEDEBE9E8E6E4E3E1E0DEDDDBDAD8F3 +:10D10000D7D5D4D3D1D0CFCDCCCBCAC8C7C6C5C450 +:10D11000C2C1C0BFBEBDBCBBBAB9B8B7B6B5B4B367 +:10D12000B2B1B0AFAEADACABAAA9A8A8A7A6A5A452 +:10D13000A3A3A2A1A09F9F9E9D9C9C9B9A99999816 +:10D140009797969595949393929191908F8F8E8EB9 +:10D150008D8C8C8B8B8A8989888887878685858446 +:10D1600084838382828181800000FF070000F87F32 +:10D1700051EA030C17D41CF5801F58BFBCF5801F63 +:10D1800000F10680994218BF704708BF904270476F +:10D1900007D711F5801F58BF13F5801F19D4994286 +:10D1A0007047894270471CF5801F08D5BCF5801F69 +:10D1B000F7D58B4218BF704708BF824270474FF4C3 +:10D1C000001C1CEB410F38BF1CEB430F01D28B42FC +:10D1D000704770B500F00AF9922449004FF00051F1 +:10D1E0004FF08053FFF75EBE4FEA1153A3F5806303 +:10D1F000D3F11E03A8BFD3F1200C08DB4FF000428F +:10D2000042EAC12252EA505232FA03F07047094210 +:10D210000BD4102BC4BF0020704703F5787CBCF101 +:10D22000FF3F05D04FF0FF3070474FF000007047D0 +:10D2300070B500F0DBF800BF4992248000207047F1 +:10D24000F0E710F0004248BF4042B0FA80F310FA15 +:10D2500003F10AD0C3F11D0303F5806302EB03520F +:10D260004FEA415002EBD12170474FF00000704768 +:10D27000B0FA80F310FA03F10AD0C3F11D0303F5ED +:10D2800080634FEA03524FEA415002EBD1217047CD +:10D290004FF000007047000070B5DFF848C11CEA8D +:10D2A000111E1EBF1CEA13159EEA0C0F95EA0C0F07 +:10D2B00000F06F8081EA03044EEAD47EAE4421EA96 +:10D2C0004C1123EA4C1341F4801143F48013AEF166 +:10D2D0007F7EA1FB024CA0FB0365361955EB0C05C4 +:10D2E000A1FB034C4CF10003A0FB021C16EB0C0647 +:10D2F000654153F10003094218BF46F0010613F4DB +:10D30000007F0BD14FEA03314FEA053041EA155156 +:10D3100040EA165034036FF003020AE04FEAC321DB +:10D320004FEAC52041EA555140EA5650F4026FF0E9 +:10D33000020202EB2E4201EB025585EACE710AD0C1 +:10D340005FEA440C18BF24F0004450F1000041F1A2 +:10D35000000120EAD47040F2FE7C624500D270BD2C +:10D36000A84214BF4FF080444FF04044002E08BF45 +:10D370000024BEF1806FA8BFA1F1C041BDE870409C +:10D3800080F2828001F1C04101F000414FF00000C5 +:10D3900070470CEA13159EEA0C0F18BF95EA0C0FA4 +:10D3A00006D081EA030E4FF000000EF0004170BD80 +:10D3B00000F01CF88900013E00F007B800F009B841 +:10D3C0004FEA430C5FEA5C5C08D081EA030100F09D +:10D3D0005BB84FEA410C5FEA5C5CF6D102494FF062 +:10D3E000000070470000FF070000F87F0EF1020EFA +:10D3F0002EF0030E5EF8046B364205D4012A43EB8F +:10D40000030515F5001F12D8012841EB010C1CF58E +:10D41000001F0CD80ED14FEAD17C0CEB4C0C0CF158 +:10D42000020C15F5001F08BF4CEBD37C04E04FF055 +:10D43000080C01E04FEAD37C0CEB4C0526FA05F60C +:10D4400006F00706B6F1040C06D20EEB860CBDE81A +:10D4500070404CF0010C6047DFE80CF0090B020251 +:10D460004FF00041A1F500214FF0000070BD1946BA +:10D470001046012851EB010418BFD4F5001484BFF5 +:10D48000002001F0004170BD0808A0F500114FEA2E +:10D490003101704710B591EA030F81F000413FF56B +:10D4A00061AC83F0004300F009B8000010B591EAC8 +:10D4B000030F48BF83F000433FF554AC841A71EB6F +:10D4C000030C07D28CF0004C121943EB0C03001B29 +:10D4D00061EB0C014FEA1154A4EB135CDFF8A4E1FB +:10D4E0001EEA430F18BF9EEA445F00F0B48021EAB1 +:10D4F000045123EA6E035242C3EB6E0338BF5B1E36 +:10D50000DCF1200E25D322FA0CFE10EB0E0043FABC +:10D510000CFE41EB0E01CCF1200E03FA0EFE10EBD7 +:10D520000E00CCF1200E51F1000129D401EB045181 +:10D5300012FA0EF2BDE8104058BF7047401C1CBFE5 +:10D54000B2F1004F704700280CBF491C20F00100C9 +:10D55000704712EB020E43EB030218BF4FF0010EAF +:10D560004EEA4202ACF1200CDCF11E0E56D943FA11 +:10D570000CFE10EB0E00CCF11E0E51F1FF31D5D593 +:10D580000EF1010E12FA0EFE404141EB010101EBDA +:10D59000445C5FEA5C5C10D901EB045110EBDE7077 +:10D5A00038BFBEF1004FBDE8104018BF70470028DB +:10D5B0000CBF491C20F00100704734D24FEAD42C34 +:10D5C00024F4006411F500111BD0B1FA81F20B3A7A +:10D5D000A41AA41ED2F12003914030FA03F3194398 +:10D5E000904001EBCC7101EB0451002CBDE81040E0 +:10D5F000A8BF704701F1C04101F000414FF00000A9 +:10D600007047B0FA80F310FA03F102D1BDE8104080 +:10D610007047E41A173C4805C90AE2E701EB0451D8 +:10D62000BDE81040704749104FEA300001EB04514B +:10D63000BDE8104002E04FF0000170474A0008BF0B +:10D640000042F8D0B2F5001F28BF704701F000413A +:10D650004FF0000070479EEA445F07D011EA5E0F6A +:10D66000BDE8104004BF002100207047BDE8104015 +:10D6700070B5FFF7BBFE00BF40DFF63E104683F0FB +:10D68000004170470000E0FF43004FEAD30C4FEA2F +:10D690003C0C43401FBF40070CF1605113F0FE4F9C +:10D6A00070471CF0006F03D10CF000410020704760 +:10D6B0000CF0004343EA507040EACC0010B500F093 +:10D6C0003EF800BF000000924FEA0001FFF7DCBE09 +:10D6D0004FF00041A1F500214FF0000070474FF0DE +:10D6E0007E5209E011F0004204D54042C1F1000130 +:10D6F00038BF491E42F07E5202F170620B0012BF29 +:10D7000020235FEA00017047B1FA81FC01FA0CF1B5 +:10D71000A3EB0C0320FA03FC41EA0C0102EBC35219 +:10D72000C3F1200310FA03FC5CEA416C42EB1120C8 +:10D7300018BF5FF0806C28BF20F0010070470EF129 +:10D74000020E2EF0030E5EF8044B244204D44FEA7E +:10D750004102B2F17F4F11D84FEA4003B3F17F4F3E +:10D760000CD80ED14FEAD07C0CEB4C0C0CF1020C17 +:10D77000B2F17F4F08BF4CEBD17C04E04FF0080CB6 +:10D7800001E04FEAD17C0CEB4C0324FA03F404F0E3 +:10D790000704B4F1040C06D20EEB840CBDE8104073 +:10D7A0004CF0010C6047DFE80CF0070802024FF074 +:10D7B0000040A0F5800010BD0846420018BFD2F11D +:10D7C000807288BF00F0004010BDF1EE100A4FF6E5 +:10D7D000FF71C0F2C03120EA010040F04070E1EE7C +:10D7E000100A7047FF2141EAD050C0057047000081 +:10D7F0004FBB610567ACDD3F182D4454FB21E93F69 +:10D800009BF681D20B73EF3F182D4454FB21F93F57 +:10D81000E2652F227F2B7A3C075C143326A6813CDD +:10D82000BDCBF07A8807703C075C143326A6913C88 +:10D83000C4EB98999999C9BF711623FEC671BCBFF4 +:10D840006D9A74AFF2B0B3BF9AFDDE522DDEADBF5C +:10D850002F6C6A2C44B4A2BF0D5555555555D53F74 +:10D86000FF8300922449C23F6E204CC5CD45B73F8F +:10D87000513DD0A0660DB13FEB0D76244B7BA93F07 +:10D8800011DA22E33AAD903F0000000000000000F2 +:10D89000000000006E83F9A22915444ED15727FCE1 +:10D8A000C0DD34F5999562DB4190433CAB6351FE9A +:10D8B0000000000000000000010203040607080940 +:10D8C000000000000102030401000000000002400B +:10D8D00010000000000002400100000000040240AF +:10D8E0001000000000080240200000000008024074 +:10D8F000080000000018024040000000001802402C +:10D900007CDC0008000000000000000000000000B7 +:10D9100000000000000400001800000000000000EB +:10D92000000000007FDC0008000000000000000094 +:10D9300000000000000000000004000018000000CB +:10D94000000000000000000095DC0008000000005E +:10D9500000000000000000000000000000040000C3 +:10D9600018000000000000000000000070DC00084B +:10D9700000000000000000000000000000000000A7 +:10D98000000400001800000000000000000000007B +:10D9900089DC00080000000000000000000000001A +:10D9A000000000000004000018000000000000005B +:10D9B00000000000ADDC00080000000000000000D6 +:10D9C0000000000000000000000400003000000023 +:10D9D000000000000000000075DC000800000000EE +:10D9E0000000000000000000000000000004000033 +:10D9F000180000000000000000000000A2DC000889 +:10DA00000000000000000000000000000000000016 +:10DA100000040000180000000000000000000000EA +:10DA20000000891112239B322446AD573665BF741E +:10DA3000488CC19D5AAFD3BE6CCAE5DB7EE9F7F8CE +:10DA40008110080193331A22A5562C47B7753E64FE +:10DA5000C99C408DDBBF52AEEDDA64CBFFF976E8AE +:10DA600002218B30100299132667AF763444BD55DE +:10DA70004AADC3BC588ED19F6EEBE7FA7CC8F5D98E +:10DA800083310A2091121803A7772E66B5543C45BE +:10DA9000CBBD42ACD99E508FEFFB66EAFDD874C96E +:10DAA00004428D5316619F702004A9153227BB369E +:10DAB0004CCEC5DF5EEDD7FC6888E1997AABF3BA4E +:10DAC00085520C4397711E60A1142805B3373A267E +:10DAD000CDDE44CFDFFD56ECE9986089FBBB72AA2E +:10DAE00006638F7214409D512225AB343006B9175E +:10DAF0004EEFC7FE5CCCD5DD6AA9E3B8788AF19B0E +:10DB000087730E6295501C41A3352A24B11638073D +:10DB1000CFFF46EEDDDC54CDEBB962A8F99A708BED +:10DB2000088481951AA793B62CC2A5D33EE1B7F01D +:10DB30004008C919522BDB3A644EED5F766DFF7CCD +:10DB4000899400859BB712A6ADD224C3BFF136E0FD +:10DB5000C1184809D33B5A2AE55E6C4FF77D7E6CAD +:10DB60000AA583B4188691972EE3A7F23CC0B5D1DD +:10DB70004229CB38500AD91B666FEF7E744CFD5D8D +:10DB80008BB502A499961087AFF326E2BDD034C1BD +:10DB9000C3394A28D11A580BE77F6E6EF55C7C4D6D +:10DBA0000CC685D71EE597F42880A1913AA3B3B29D +:10DBB000444ACD5B5669DF78600CE91D722FFB3E4D +:10DBC0008DD604C79FF516E4A9902081BBB332A27D +:10DBD000C55A4C4BD7795E68E11C680DF33F7A2E2D +:10DBE0000EE787F61CC495D52AA1A3B03882B1935D +:10DBF000466BCF7A5448DD59622DEB3C700EF91F0D +:10DC00008FF706E69DD414C5ABB122A0B99230833C +:10DC1000C77B4E6AD5585C49E33D6A2CF11E780FEC +:10DC200064DC0008000000000000000000000000AC +:10DC300000000000000200001800000000000000CA +:10DC4000000000009A99193E0000803F000000008B +:10DC5000000000000000803F0000803F0000000046 +:10DC60000000000064656661756C745461736B003C +:10DC7000647231360072656D6F74650061690061B0 +:10DC80007474695F657374690067696D62616C5F64 +:10DC90006374726C00636861737369735F63747239 +:10DCA0006C0073686F6F745F6374726C005461739F +:10DCB0006B5F496E69740000F8DC0008000000200A +:10DCC00040030000C401000850DE000800C001202D +:10DCD000080000002002000850DE00084003002079 +:10DCE000A0B501003C02000858DE000808C0012071 +:10DCF000E03800003C020008111324F49011022BBC +:10DD0000073DB6D096BA1D2604BBE3B52EB8120166 +:10DD10001A0103111A1104A1120112122A02077921 +:10DD2000102C0A02022B113A090861A0090AD7A394 +:10DD30003DCDCCCC3D2340415B80BF04223F2396A8 +:10DD4000421FA041CDCC4C3E084A4020180AA041B9 +:10DD5000DB0FC9408FC27514292411290431290C05 +:10DD6000390459402A204C391C1940596439142A65 +:10DD7000BF401908694071E94011192429741A201B +:10DD8000048199401202AA02F29948193C280A7AA1 +:10DD9000443D0A573E14AE0748911CAE47A1609A15 +:10DDA000C074A149E40122492869B849087A020CE3 +:10DDB0005C10420AA8320549A02BD2421C12013A3B +:10DDC00001271908112B02021B290A1A0314120138 +:10DDD0002D6F12833A24295C350AD7233C29581920 +:10DDE0000429CC79D85D40CDCCCCA42A80842904E8 +:10DDF000192029046B40418C4DEC51383D0C3904FD +:10DE000036BFDB0FC94019042EC03F9A999940399B +:10DE1000686920C96401381AF080A9042B0102DE68 +:10DE2000215A02085A03083A040869F099DC79B0CB +:10DE30005990591009102059D0314B484204411AC9 +:10DE40004014290429E8437A4632101AAA014100F5 +:08DE50000100000000000000C9 +:040000050800018965 +:00000001FF diff --git a/MDK-ARM/Infantry/Infantry.htm b/MDK-ARM/Infantry/Infantry.htm new file mode 100644 index 0000000..d32e100 --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.htm @@ -0,0 +1,4902 @@ + + +Static Call Graph - [Infantry\Infantry.axf] +
+

Static Call Graph for image Infantry\Infantry.axf

+

#<CALLGRAPH># ARM Linker, 6160001: Last Updated: Fri Jan 9 09:46:13 2026 +

+

Maximum Stack Usage = 304 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+Task_shoot_ctrl ⇒ Shoot_UpdateFeedback ⇒ MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • ADC_IRQHandler   ⇒   ADC_IRQHandler
    +
  • BusFault_Handler   ⇒   BusFault_Handler
    +
  • HardFault_Handler   ⇒   HardFault_Handler
    +
  • MemManage_Handler   ⇒   MemManage_Handler
    +
  • NMI_Handler   ⇒   NMI_Handler
    +
  • UART_EndRxTransfer   ⇒   UART_EndRxTransfer
    +
  • UsageFault_Handler   ⇒   UsageFault_Handler
    +
  • UART_EndTxTransfer   ⇒   UART_EndTxTransfer
    + +

    +

    +Function Pointers +

      +
    • ADC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • BMI088_AcclIntCallback from bmi088.o(.text.BMI088_AcclIntCallback) referenced 2 times from bmi088.o(.text.BMI088_Init) +
    • BMI088_GyroIntCallback from bmi088.o(.text.BMI088_GyroIntCallback) referenced 2 times from bmi088.o(.text.BMI088_Init) +
    • BMI088_RxCpltCallback from bmi088.o(.text.BMI088_RxCpltCallback) referenced 2 times from bmi088.o(.text.BMI088_Init) +
    • BSP_CAN_DefaultIdParser from can_1.o(.text.BSP_CAN_DefaultIdParser) referenced 2 times from can_1.o(.text.BSP_CAN_Init) +
    • BSP_CAN_RxFifo0Callback from can_1.o(.text.BSP_CAN_RxFifo0Callback) referenced 2 times from can_1.o(.text.BSP_CAN_Init) +
    • BSP_CAN_RxFifo1Callback from can_1.o(.text.BSP_CAN_RxFifo1Callback) referenced 2 times from can_1.o(.text.BSP_CAN_Init) +
    • BSP_CAN_TxCompleteCallback from can_1.o(.text.BSP_CAN_TxCompleteCallback) referenced 2 times from can_1.o(.text.BSP_CAN_Init) +
    • BusFault_Handler from stm32f4xx_it.o(.text.BusFault_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN1_RX0_IRQHandler from stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN1_RX1_IRQHandler from stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN1_SCE_IRQHandler from stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN1_TX_IRQHandler from stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN2_RX0_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • CAN2_RX1_IRQHandler from stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN2_SCE_IRQHandler from stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • CAN2_TX_IRQHandler from stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • DCMI_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream0_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream1_IRQHandler from stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream2_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream3_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream4_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream5_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream6_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA1_Stream7_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream0_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream1_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream2_IRQHandler from stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream3_IRQHandler from stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream4_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream5_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream6_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DMA2_Stream7_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • DR16_RxCpltCallback from dr16.o(.text.DR16_RxCpltCallback) referenced 2 times from dr16.o(.text.DR16_Init) +
    • DebugMon_Handler from stm32f4xx_it.o(.text.DebugMon_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • ETH_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • ETH_WKUP_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI0_IRQHandler from stm32f4xx_it.o(.text.EXTI0_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI3_IRQHandler from stm32f4xx_it.o(.text.EXTI3_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI4_IRQHandler from stm32f4xx_it.o(.text.EXTI4_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • EXTI9_5_IRQHandler from stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • FMC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • FPU_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • HASH_RNG_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • HardFault_Handler from stm32f4xx_it.o(.text.HardFault_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • I2C3_ER_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • I2C3_EV_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • MemManage_Handler from stm32f4xx_it.o(.text.MemManage_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • NMI_Handler from stm32f4xx_it.o(.text.NMI_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_FS_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_FS_WKUP_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_HS_EP1_IN_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_HS_EP1_OUT_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_HS_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • OTG_HS_WKUP_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • PVD_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • PendSV_Handler from port.o(.text.PendSV_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • RCC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • RTC_Alarm_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • RTC_WKUP_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • Reset_Handler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • SDIO_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • SPI3_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • SPI_DMAError from stm32f4xx_hal_spi.o(.text.SPI_DMAError) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • SPI_DMAError from stm32f4xx_hal_spi.o(.text.SPI_DMAError) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    • SPI_DMAError from stm32f4xx_hal_spi.o(.text.SPI_DMAError) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    • SPI_DMAHalfReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • SPI_DMAHalfReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    • SPI_DMAHalfTransmitCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    • SPI_DMAHalfTransmitReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    • SPI_DMAReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • SPI_DMAReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    • SPI_DMATransmitCplt from stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    • SPI_DMATransmitReceiveCplt from stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) referenced 2 times from stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    • SVC_Handler from port.o(.text.SVC_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • StartDefaultTask from freertos.o(.text.StartDefaultTask) referenced 2 times from freertos.o(.text.MX_FREERTOS_Init) +
    • SysTick_Handler from stm32f4xx_it.o(.text.SysTick_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • SystemInit from system_stm32f4xx.o(.text.SystemInit) referenced from startup_stm32f407xx.o(.text) +
    • TAMP_STAMP_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM1_BRK_TIM9_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM1_TRG_COM_TIM11_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM1_UP_TIM10_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM3_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM4_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM5_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM6_DAC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM7_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM8_BRK_TIM12_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM8_CC_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM8_TRG_COM_TIM14_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • TIM8_UP_TIM13_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • Task_Init from init.o(.text.Task_Init) referenced 2 times from freertos.o(.text.MX_FREERTOS_Init) +
    • Task_ai from ai_1.o(.text.Task_ai) referenced 2 times from init.o(.text.Task_Init) +
    • Task_atti_esti from atti_esti.o(.text.Task_atti_esti) referenced 2 times from init.o(.text.Task_Init) +
    • Task_chassis_ctrl from chassis_ctrl.o(.text.Task_chassis_ctrl) referenced 2 times from init.o(.text.Task_Init) +
    • Task_dr16 from dr16_1.o(.text.Task_dr16) referenced 2 times from init.o(.text.Task_Init) +
    • Task_gimbal_ctrl from gimbal_ctrl.o(.text.Task_gimbal_ctrl) referenced 2 times from init.o(.text.Task_Init) +
    • Task_remote from remote.o(.text.Task_remote) referenced 2 times from init.o(.text.Task_Init) +
    • Task_shoot_ctrl from shoot_ctrl.o(.text.Task_shoot_ctrl) referenced 2 times from init.o(.text.Task_Init) +
    • UART4_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • UART5_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • UART_DMAAbortOnError from stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) referenced 2 times from stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) +
    • UART_DMAError from stm32f4xx_hal_uart.o(.text.UART_DMAError) referenced 2 times from stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    • UART_DMAError from stm32f4xx_hal_uart.o(.text.UART_DMAError) referenced 2 times from stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    • UART_DMAReceiveCplt from stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) referenced 2 times from stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    • UART_DMARxHalfCplt from stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) referenced 2 times from stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    • UART_DMATransmitCplt from stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) referenced 2 times from stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    • UART_DMATxHalfCplt from stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) referenced 2 times from stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    • USART1_IRQHandler from stm32f4xx_it.o(.text.USART1_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • USART2_IRQHandler from stm32f4xx_it.o(.text.USART2_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • USART3_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • USART6_IRQHandler from stm32f4xx_it.o(.text.USART6_IRQHandler) referenced from startup_stm32f407xx.o(RESET) +
    • UsageFault_Handler from stm32f4xx_it.o(.text.UsageFault_Handler) referenced from startup_stm32f407xx.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f407xx.o(.text) referenced from startup_stm32f407xx.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32f407xx.o(.text) +
    • prvIdleTask from tasks.o(.text.prvIdleTask) referenced 2 times from tasks.o(.text.vTaskStartScheduler) +
    • prvTaskExitError from port.o(.text.prvTaskExitError) referenced 2 times from port.o(.text.pxPortInitialiseStack) +
    • prvTimerTask from timers.o(.text.prvTimerTask) referenced 2 times from timers.o(.text.xTimerCreateTimerTask) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(.text) +
    +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __decompress (Thumb, 90 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +

    __decompress1 (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +

    __scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED) +

    [Calls]

    • >>   __scatterload_copy +
    +
    [Called By]
    • >>   __scatterload_copy +
    + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000001)) +

    [Calls]

    • >>   _fp_init +
    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 192 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ MX_FREERTOS_Init ⇒ osThreadNew ⇒ xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   main +
    • >>   exit +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    ADC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +

    [Calls]

    • >>   ADC_IRQHandler +
    +
    [Called By]
    • >>   ADC_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DCMI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA1_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    HASH_RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_HS_EP1_IN_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_HS_EP1_OUT_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_HS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    OTG_HS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    RTC_Alarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    RTC_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TAMP_STAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM1_BRK_TIM9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM1_TRG_COM_TIM11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM1_UP_TIM10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM6_DAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM8_BRK_TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM8_TRG_COM_TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    TIM8_UP_TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f407xx.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f407xx.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __aeabi_uldivmod (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = __aeabi_uldivmod +
    +
    [Called By]
    • >>   HAL_RCC_GetSysClockFreq +
    • >>   UART_SetConfig +
    + +

    _ll_udiv (Thumb, 240 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED) + +

    __aeabi_memcpy (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text)) +

    [Called By]

    • >>   prvCopyDataToQueue +
    • >>   prvCopyDataFromQueue +
    • >>   BSP_CAN_Transmit +
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    __rt_memcpy (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memcpy4 +
    + +

    _memcpy_lastbytes (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED) + +

    __aeabi_memcpy4 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) +

    [Called By]

    • >>   __rt_memcpy +
    + +

    __aeabi_memcpy8 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_memcpy8 +
    +
    [Called By]
    • >>   Shoot_UpdateFeedback +
    + +

    __rt_memcpy_w (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) + +

    _memcpy_lastbytes_aligned (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED) + +

    __aeabi_memset4 (Thumb, 16 bytes, Stack size 0 bytes, aeabi_memset4.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = __aeabi_memset4 ⇒ _memset_w +
    +
    [Calls]
    • >>   _memset_w +
    +
    [Called By]
    • >>   prvInitialiseNewTask +
    + +

    __aeabi_memset8 (Thumb, 0 bytes, Stack size 0 bytes, aeabi_memset4.o(.text), UNUSED) + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    • >>   SystemClock_Config +
    • >>   MOTOR_RM_CreateCANManager +
    • >>   BSP_CAN_Init +
    • >>   DR16_ParseData +
    • >>   DR16_Offline +
    • >>   MOTOR_DM_CreateCANManager +
    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    • >>   MOTOR_DM_Register +
    • >>   MOTOR_RM_Register +
    + +

    __rt_memclr_w (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED) + +

    _memset_w (Thumb, 74 bytes, Stack size 4 bytes, rt_memclr_w.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = _memset_w +
    +
    [Called By]
    • >>   __aeabi_memset4 +
    + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __read_errno (Thumb, 10 bytes, Stack size 8 bytes, _rserrno.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_errno_addr +
    + +

    __set_errno (Thumb, 12 bytes, Stack size 8 bytes, _rserrno.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __set_errno +
    +
    [Calls]
    • >>   __aeabi_errno_addr +
    +
    [Called By]
    • >>   sqrtf +
    • >>   __hardfp_tanf +
    • >>   __hardfp_atan2f +
    • >>   __hardfp_atan2 +
    • >>   __hardfp_asinf +
    + +

    __aeabi_errno_addr (Thumb, 8 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text)) +

    [Called By]

    • >>   __set_errno +
    • >>   __read_errno +
    + +

    __errno$intlibspace (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED) + +

    __rt_errno_addr$intlibspace (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED) + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_initial_stackheap +
    • >>   __user_perproc_libspace +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = exit +
    +
    [Calls]
    • >>   __rt_exit +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    _sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __semihosting_library_function (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED) + +

    AHRS_GetEulr (Thumb, 220 bytes, Stack size 24 bytes, ahrs.o(.text.AHRS_GetEulr)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = AHRS_GetEulr ⇒ __hardfp_atan2f ⇒ __set_errno +
    +
    [Calls]
    • >>   copysignf +
    • >>   __hardfp_atan2f +
    • >>   __hardfp_asinf +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    AHRS_Init (Thumb, 388 bytes, Stack size 24 bytes, ahrs.o(.text.AHRS_Init)) +

    [Stack]

    • Max Depth = 192
    • Call Chain = AHRS_Init ⇒ __hardfp_atan2 ⇒ atan ⇒ __hardfp_atan ⇒ __kernel_poly ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   __hardfp_atan2 +
    • >>   __aeabi_f2d +
    • >>   __aeabi_d2f +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    AHRS_ResetEulr (Thumb, 10 bytes, Stack size 0 bytes, ahrs.o(.text.AHRS_ResetEulr)) +

    [Called By]

    • >>   Gimbal_SetMode +
    + +

    AHRS_Update (Thumb, 1422 bytes, Stack size 136 bytes, ahrs.o(.text.AHRS_Update)) +

    [Stack]

    • Max Depth = 216
    • Call Chain = AHRS_Update ⇒ AHRS_UpdateIMU +
    +
    [Calls]
    • >>   InvSqrt +
    • >>   AHRS_UpdateIMU +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    AI_Get_NUC (Thumb, 84 bytes, Stack size 16 bytes, ai.o(.text.AI_Get_NUC)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = AI_Get_NUC ⇒ CRC16_Verify ⇒ CRC16_Calc +
    +
    [Calls]
    • >>   CRC16_Verify +
    +
    [Called By]
    • >>   Task_ai +
    + +

    AI_ParseHost (Thumb, 92 bytes, Stack size 16 bytes, ai.o(.text.AI_ParseHost)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = AI_ParseHost ⇒ CRC16_Verify ⇒ CRC16_Calc +
    +
    [Calls]
    • >>   CRC16_Verify +
    • >>   CRC16_Calc +
    +
    [Called By]
    • >>   Task_ai +
    + +

    AI_StartReceiving (Thumb, 26 bytes, Stack size 8 bytes, ai.o(.text.AI_StartReceiving)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = AI_StartReceiving ⇒ BSP_UART_Receive ⇒ HAL_UART_Receive_DMA ⇒ UART_Start_Receive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   BSP_UART_Receive +
    +
    [Called By]
    • >>   Task_ai +
    + +

    AI_StartSend (Thumb, 18 bytes, Stack size 8 bytes, ai.o(.text.AI_StartSend)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = AI_StartSend ⇒ BSP_UART_Transmit ⇒ HAL_UART_Transmit_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   BSP_UART_Transmit +
    +
    [Called By]
    • >>   Task_ai +
    + +

    AbsClip (Thumb, 34 bytes, Stack size 0 bytes, user_math.o(.text.AbsClip)) +

    [Called By]

    • >>   PID_Calc +
    + +

    BMI088_AcclStartDmaRecv (Thumb, 24 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_AcclStartDmaRecv)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = BMI088_AcclStartDmaRecv ⇒ BMI_Read ⇒ BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   BMI_Read +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BMI088_AcclWaitDmaCplt (Thumb, 16 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_AcclWaitDmaCplt)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BMI088_AcclWaitDmaCplt ⇒ osThreadFlagsWait ⇒ xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   osThreadFlagsWait +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BMI088_GetUpdateFreq (Thumb, 12 bytes, Stack size 0 bytes, bmi088.o(.text.BMI088_GetUpdateFreq)) +

    [Called By]

    • >>   Task_atti_esti +
    + +

    BMI088_GyroStartDmaRecv (Thumb, 26 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_GyroStartDmaRecv)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = BMI088_GyroStartDmaRecv ⇒ BMI_Read ⇒ BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   BMI_Read +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BMI088_GyroWaitDmaCplt (Thumb, 16 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_GyroWaitDmaCplt)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BMI088_GyroWaitDmaCplt ⇒ osThreadFlagsWait ⇒ xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   osThreadFlagsWait +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BMI088_Init (Thumb, 322 bytes, Stack size 24 bytes, bmi088.o(.text.BMI088_Init)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = BMI088_Init ⇒ BMI_ReadSingle ⇒ BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   osThreadGetId +
    • >>   BMI_WriteSingle +
    • >>   BMI_ReadSingle +
    • >>   BSP_TIME_Delay +
    • >>   BSP_SPI_RegisterCallback +
    • >>   BSP_GPIO_RegisterCallback +
    • >>   BSP_GPIO_EnableIRQ +
    • >>   BSP_GPIO_DisableIRQ +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BMI088_ParseAccl (Thumb, 148 bytes, Stack size 0 bytes, bmi088.o(.text.BMI088_ParseAccl)) +

    [Called By]

    • >>   Task_atti_esti +
    + +

    BMI088_ParseGyro (Thumb, 132 bytes, Stack size 0 bytes, bmi088.o(.text.BMI088_ParseGyro)) +

    [Called By]

    • >>   Task_atti_esti +
    + +

    BMI088_WaitNew (Thumb, 16 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_WaitNew)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BMI088_WaitNew ⇒ osThreadFlagsWait ⇒ xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   osThreadFlagsWait +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BSP_CAN_GetHandle (Thumb, 38 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_GetHandle)) +

    [Called By]

    • >>   BSP_CAN_Transmit +
    • >>   BSP_CAN_TxCompleteCallback +
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    BSP_CAN_GetMessage (Thumb, 128 bytes, Stack size 24 bytes, can_1.o(.text.BSP_CAN_GetMessage)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_CAN_FindQueue +
    • >>   osMutexRelease +
    • >>   osMutexAcquire +
    • >>   osMessageQueueGet +
    +
    [Called By]
    • >>   MOTOR_DM_Update +
    • >>   MOTOR_RM_Update +
    + +

    BSP_CAN_Init (Thumb, 308 bytes, Stack size 72 bytes, can_1.o(.text.BSP_CAN_Init)) +

    [Stack]

    • Max Depth = 240 + Unknown Stack Size +
    • Call Chain = BSP_CAN_Init ⇒ osMutexNew ⇒ xQueueCreateMutexStatic ⇒ prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   HAL_CAN_Start +
    • >>   HAL_CAN_ConfigFilter +
    • >>   HAL_CAN_ActivateNotification +
    • >>   BSP_CAN_RegisterCallback +
    • >>   BSP_CAN_TxQueueInit +
    • >>   osMutexNew +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   Shoot_Init +
    • >>   Gimbal_Init +
    + +

    BSP_CAN_ParseId (Thumb, 20 bytes, Stack size 8 bytes, can_1.o(.text.BSP_CAN_ParseId)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BSP_CAN_ParseId +
    +
    [Called By]
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    BSP_CAN_RegisterCallback (Thumb, 68 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_RegisterCallback)) +

    [Called By]

    • >>   BSP_CAN_Init +
    + +

    BSP_CAN_RegisterId (Thumb, 30 bytes, Stack size 8 bytes, can_1.o(.text.BSP_CAN_RegisterId)) +

    [Stack]

    • Max Depth = 200
    • Call Chain = BSP_CAN_RegisterId ⇒ BSP_CAN_CreateIdQueue ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_CAN_CreateIdQueue +
    +
    [Called By]
    • >>   MOTOR_DM_Register +
    • >>   MOTOR_RM_Register +
    + +

    BSP_CAN_Transmit (Thumb, 226 bytes, Stack size 64 bytes, can_1.o(.text.BSP_CAN_Transmit)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   HAL_CAN_GetTxMailboxesFreeLevel +
    • >>   HAL_CAN_AddTxMessage +
    • >>   BSP_CAN_GetHandle +
    • >>   BSP_CAN_TxQueuePush +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   BSP_CAN_TransmitStdDataFrame +
    + +

    BSP_CAN_TransmitStdDataFrame (Thumb, 40 bytes, Stack size 16 bytes, can_1.o(.text.BSP_CAN_TransmitStdDataFrame)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   BSP_CAN_Transmit +
    +
    [Called By]
    • >>   MOTOR_DM_Enable +
    • >>   MOTOR_DM_SendMITCmd +
    • >>   MOTOR_RM_Ctrl +
    + +

    BSP_Free (Thumb, 8 bytes, Stack size 8 bytes, mm.o(.text.BSP_Free)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = BSP_Free ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   vPortFree +
    +
    [Called By]
    • >>   BSP_CAN_CreateIdQueue +
    • >>   MOTOR_DM_Register +
    • >>   MOTOR_RM_Register +
    + +

    BSP_GPIO_DisableIRQ (Thumb, 48 bytes, Stack size 8 bytes, gpio_1.o(.text.BSP_GPIO_DisableIRQ)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = BSP_GPIO_DisableIRQ ⇒ HAL_NVIC_DisableIRQ +
    +
    [Calls]
    • >>   HAL_NVIC_DisableIRQ +
    +
    [Called By]
    • >>   BMI088_Init +
    + +

    BSP_GPIO_EnableIRQ (Thumb, 48 bytes, Stack size 8 bytes, gpio_1.o(.text.BSP_GPIO_EnableIRQ)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = BSP_GPIO_EnableIRQ ⇒ HAL_NVIC_EnableIRQ +
    +
    [Calls]
    • >>   HAL_NVIC_EnableIRQ +
    +
    [Called By]
    • >>   BMI088_Init +
    + +

    BSP_GPIO_ReadPin (Thumb, 44 bytes, Stack size 8 bytes, gpio_1.o(.text.BSP_GPIO_ReadPin)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BSP_GPIO_ReadPin +
    +
    [Calls]
    • >>   HAL_GPIO_ReadPin +
    +
    [Called By]
    • >>   BMI088_RxCpltCallback +
    + +

    BSP_GPIO_RegisterCallback (Thumb, 74 bytes, Stack size 0 bytes, gpio_1.o(.text.BSP_GPIO_RegisterCallback)) +

    [Called By]

    • >>   BMI088_Init +
    + +

    BSP_GPIO_WritePin (Thumb, 48 bytes, Stack size 8 bytes, gpio_1.o(.text.BSP_GPIO_WritePin)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BSP_GPIO_WritePin +
    +
    [Calls]
    • >>   HAL_GPIO_WritePin +
    +
    [Called By]
    • >>   BMI_WriteSingle +
    • >>   BMI_ReadSingle +
    • >>   BMI_Read +
    • >>   BMI088_RxCpltCallback +
    + +

    BSP_Malloc (Thumb, 8 bytes, Stack size 8 bytes, mm.o(.text.BSP_Malloc)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = BSP_Malloc ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   pvPortMalloc +
    +
    [Called By]
    • >>   MOTOR_RM_CreateCANManager +
    • >>   BSP_CAN_CreateIdQueue +
    • >>   MOTOR_DM_Register +
    • >>   MOTOR_DM_CreateCANManager +
    • >>   MOTOR_RM_Register +
    + +

    BSP_PWM_SetComp (Thumb, 92 bytes, Stack size 0 bytes, pwm.o(.text.BSP_PWM_SetComp)) +

    [Called By]

    • >>   Task_atti_esti +
    + +

    BSP_PWM_Start (Thumb, 30 bytes, Stack size 8 bytes, pwm.o(.text.BSP_PWM_Start)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = BSP_PWM_Start ⇒ HAL_TIM_PWM_Start ⇒ TIM_CCxChannelCmd +
    +
    [Calls]
    • >>   HAL_TIM_PWM_Start +
    +
    [Called By]
    • >>   Task_atti_esti +
    + +

    BSP_SPI_GetHandle (Thumb, 18 bytes, Stack size 0 bytes, spi_1.o(.text.BSP_SPI_GetHandle)) +

    [Called By]

    • >>   BSP_SPI_Transmit +
    • >>   BSP_SPI_Receive +
    + +

    BSP_SPI_Receive (Thumb, 52 bytes, Stack size 16 bytes, spi_1.o(.text.BSP_SPI_Receive)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_SPI_Receive_DMA +
    • >>   HAL_SPI_Receive +
    • >>   BSP_SPI_GetHandle +
    +
    [Called By]
    • >>   BMI_ReadSingle +
    • >>   BMI_Read +
    + +

    BSP_SPI_RegisterCallback (Thumb, 30 bytes, Stack size 0 bytes, spi_1.o(.text.BSP_SPI_RegisterCallback)) +

    [Called By]

    • >>   BMI088_Init +
    + +

    BSP_SPI_Transmit (Thumb, 52 bytes, Stack size 16 bytes, spi_1.o(.text.BSP_SPI_Transmit)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BSP_SPI_Transmit ⇒ HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_SPI_Transmit_DMA +
    • >>   HAL_SPI_Transmit +
    • >>   BSP_SPI_GetHandle +
    +
    [Called By]
    • >>   BMI_WriteSingle +
    • >>   BMI_ReadSingle +
    • >>   BMI_Read +
    + +

    BSP_TIME_Delay (Thumb, 88 bytes, Stack size 16 bytes, time.o(.text.BSP_TIME_Delay_ms)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = BSP_TIME_Delay ⇒ osDelay ⇒ vTaskDelay ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   HAL_Delay +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetState +
    • >>   osDelay +
    +
    [Called By]
    • >>   BMI088_Init +
    • >>   BMI_WriteSingle +
    • >>   BMI_ReadSingle +
    + +

    BSP_TIME_Delay_ms (Thumb, 88 bytes, Stack size 16 bytes, time.o(.text.BSP_TIME_Delay_ms), UNUSED) + +

    BSP_TIME_Get (Thumb, 80 bytes, Stack size 24 bytes, time.o(.text.BSP_TIME_Get_us)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = BSP_TIME_Get +
    +
    [Calls]
    • >>   xTaskGetTickCount +
    • >>   osKernelGetTickFreq +
    +
    [Called By]
    • >>   MOTOR_DM_Update +
    • >>   MOTOR_RM_Update +
    + +

    BSP_TIME_Get_us (Thumb, 80 bytes, Stack size 24 bytes, time.o(.text.BSP_TIME_Get_us)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = BSP_TIME_Get_us +
    +
    [Called By]
    • >>   Shoot_Control +
    • >>   Gimbal_Control +
    • >>   DR16_ParseData +
    + +

    BSP_UART_GetHandle (Thumb, 16 bytes, Stack size 0 bytes, uart.o(.text.BSP_UART_GetHandle)) +

    [Called By]

    • >>   BSP_UART_Transmit +
    • >>   BSP_UART_Receive +
    • >>   DR16_StartDmaRecv +
    + +

    BSP_UART_IRQHandler (Thumb, 58 bytes, Stack size 16 bytes, uart.o(.text.BSP_UART_IRQHandler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = BSP_UART_IRQHandler +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   USART6_IRQHandler +
    • >>   USART1_IRQHandler +
    + +

    BSP_UART_Receive (Thumb, 64 bytes, Stack size 16 bytes, uart.o(.text.BSP_UART_Receive)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = BSP_UART_Receive ⇒ HAL_UART_Receive_DMA ⇒ UART_Start_Receive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_UART_Receive_IT +
    • >>   HAL_UART_Receive_DMA +
    • >>   BSP_UART_GetHandle +
    +
    [Called By]
    • >>   AI_StartReceiving +
    + +

    BSP_UART_RegisterCallback (Thumb, 50 bytes, Stack size 0 bytes, uart.o(.text.BSP_UART_RegisterCallback)) +

    [Called By]

    • >>   DR16_Init +
    + +

    BSP_UART_Transmit (Thumb, 64 bytes, Stack size 16 bytes, uart.o(.text.BSP_UART_Transmit)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = BSP_UART_Transmit ⇒ HAL_UART_Transmit_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_UART_Transmit_IT +
    • >>   HAL_UART_Transmit_DMA +
    • >>   BSP_UART_GetHandle +
    +
    [Called By]
    • >>   AI_StartSend +
    + +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.BusFault_Handler)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN1_RX0_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN1_RX0_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN1_RX1_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN1_SCE_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN1_TX_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN1_TX_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN1_TX_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN2_RX1_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN2_RX1_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN2_SCE_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN2_SCE_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CAN2_TX_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.CAN2_TX_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CAN2_TX_IRQHandler ⇒ HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    CRC16_Calc (Thumb, 30 bytes, Stack size 16 bytes, crc16.o(.text.CRC16_Calc)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = CRC16_Calc +
    +
    [Calls]
    • >>   CRC16_Byte +
    +
    [Called By]
    • >>   CRC16_Verify +
    • >>   AI_ParseHost +
    + +

    CRC16_Verify (Thumb, 50 bytes, Stack size 16 bytes, crc16.o(.text.CRC16_Verify)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = CRC16_Verify ⇒ CRC16_Calc +
    +
    [Calls]
    • >>   CRC16_Calc +
    +
    [Called By]
    • >>   AI_ParseHost +
    • >>   AI_Get_NUC +
    + +

    CircleAdd (Thumb, 58 bytes, Stack size 0 bytes, user_math.o(.text.CircleAdd)) +

    [Called By]

    • >>   Shoot_CaluTargetAngle +
    • >>   Gimbal_Control +
    + +

    CircleError (Thumb, 60 bytes, Stack size 0 bytes, user_math.o(.text.CircleError)) +

    [Called By]

    • >>   PID_Calc +
    • >>   Shoot_CaluTargetAngle +
    • >>   Gimbal_Control +
    + +

    Clip (Thumb, 38 bytes, Stack size 0 bytes, user_math.o(.text.Clip)) +

    [Called By]

    • >>   Gimbal_Control +
    + +

    Config_GetRobotParam (Thumb, 10 bytes, Stack size 0 bytes, config.o(.text.Config_GetRobotParam)) +

    [Called By]

    • >>   Task_shoot_ctrl +
    • >>   Task_gimbal_ctrl +
    + +

    DMA1_Stream1_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = DMA1_Stream1_IRQHandler ⇒ HAL_DMA_IRQHandler +
    +
    [Calls]
    • >>   HAL_DMA_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream2_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = DMA2_Stream2_IRQHandler ⇒ HAL_DMA_IRQHandler +
    +
    [Calls]
    • >>   HAL_DMA_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    DMA2_Stream3_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = DMA2_Stream3_IRQHandler ⇒ HAL_DMA_IRQHandler +
    +
    [Calls]
    • >>   HAL_DMA_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    DR16_Init (Thumb, 70 bytes, Stack size 8 bytes, dr16.o(.text.DR16_Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = DR16_Init ⇒ osThreadGetId +
    +
    [Calls]
    • >>   osThreadGetId +
    • >>   BSP_UART_RegisterCallback +
    +
    [Called By]
    • >>   Task_dr16 +
    + +

    DR16_Offline (Thumb, 26 bytes, Stack size 8 bytes, dr16.o(.text.DR16_Offline)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = DR16_Offline +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   Task_dr16 +
    + +

    DR16_ParseData (Thumb, 308 bytes, Stack size 8 bytes, dr16.o(.text.DR16_ParseData)) +

    [Stack]

    • Max Depth = 32 + Unknown Stack Size +
    • Call Chain = DR16_ParseData ⇒ BSP_TIME_Get_us +
    +
    [Calls]
    • >>   BSP_TIME_Get_us +
    • >>   __aeabi_memclr4 +
    • >>   DR16_DataCorrupted +
    +
    [Called By]
    • >>   Task_dr16 +
    + +

    DR16_StartDmaRecv (Thumb, 30 bytes, Stack size 8 bytes, dr16.o(.text.DR16_StartDmaRecv)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = DR16_StartDmaRecv ⇒ HAL_UART_Receive_DMA ⇒ UART_Start_Receive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_UART_Receive_DMA +
    • >>   BSP_UART_GetHandle +
    +
    [Called By]
    • >>   Task_dr16 +
    + +

    DR16_WaitDmaCplt (Thumb, 22 bytes, Stack size 8 bytes, dr16.o(.text.DR16_WaitDmaCplt)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = DR16_WaitDmaCplt ⇒ osThreadFlagsWait ⇒ xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   osThreadFlagsWait +
    +
    [Called By]
    • >>   Task_dr16 +
    + +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.DebugMon_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.EXTI0_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = EXTI0_IRQHandler ⇒ HAL_GPIO_EXTI_IRQHandler ⇒ HAL_GPIO_EXTI_Callback +
    +
    [Calls]
    • >>   HAL_GPIO_EXTI_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.EXTI3_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = EXTI3_IRQHandler ⇒ HAL_GPIO_EXTI_IRQHandler ⇒ HAL_GPIO_EXTI_Callback +
    +
    [Calls]
    • >>   HAL_GPIO_EXTI_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.EXTI4_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = EXTI4_IRQHandler ⇒ HAL_GPIO_EXTI_IRQHandler ⇒ HAL_GPIO_EXTI_Callback +
    +
    [Calls]
    • >>   HAL_GPIO_EXTI_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.EXTI9_5_IRQHandler)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = EXTI9_5_IRQHandler ⇒ HAL_GPIO_EXTI_IRQHandler ⇒ HAL_GPIO_EXTI_Callback +
    +
    [Calls]
    • >>   HAL_GPIO_EXTI_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    Error_Handler (Thumb, 6 bytes, Stack size 0 bytes, main.o(.text.Error_Handler)) +

    [Called By]

    • >>   HAL_UART_MspInit +
    • >>   HAL_SPI_MspInit +
    • >>   SystemClock_Config +
    • >>   MX_USART6_UART_Init +
    • >>   MX_USART3_UART_Init +
    • >>   MX_USART2_UART_Init +
    • >>   MX_USART1_UART_Init +
    • >>   MX_TIM10_Init +
    • >>   MX_SPI1_Init +
    • >>   MX_I2C2_Init +
    • >>   MX_CAN2_Init +
    • >>   MX_CAN1_Init +
    + +

    Gimbal_Cmd (Thumb, 168 bytes, Stack size 16 bytes, remote_cmd.o(.text.Gimbal_Cmd)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = Gimbal_Cmd ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   __aeabi_dmul +
    • >>   __aeabi_i2d +
    • >>   __aeabi_ddiv +
    • >>   __aeabi_d2f +
    +
    [Called By]
    • >>   Task_remote +
    + +

    Gimbal_Control (Thumb, 928 bytes, Stack size 72 bytes, gimbal.o(.text.Gimbal_Control)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = Gimbal_Control ⇒ PID_Calc ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   Clip +
    • >>   CircleAdd +
    • >>   PID_Calc +
    • >>   CircleError +
    • >>   LowPassFilter2p_Apply +
    • >>   BSP_TIME_Get_us +
    • >>   __aeabi_ul2f +
    • >>   major_yaw_Control +
    • >>   Gimbal_Control_mode +
    • >>   motor_imu_offset +
    • >>   Gimbal_SetMode +
    +
    [Called By]
    • >>   Task_gimbal_ctrl +
    + +

    Gimbal_Control_mode (Thumb, 88 bytes, Stack size 0 bytes, gimbal.o(.text.Gimbal_Control_mode)) +

    [Called By]

    • >>   Gimbal_Control +
    + +

    Gimbal_Init (Thumb, 336 bytes, Stack size 16 bytes, gimbal.o(.text.Gimbal_Init)) +

    [Stack]

    • Max Depth = 256 + Unknown Stack Size +
    • Call Chain = Gimbal_Init ⇒ BSP_CAN_Init ⇒ osMutexNew ⇒ xQueueCreateMutexStatic ⇒ prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   PID_Init +
    • >>   LowPassFilter2p_Init +
    • >>   BSP_CAN_Init +
    • >>   MOTOR_DM_Register +
    • >>   MOTOR_DM_Enable +
    • >>   MOTOR_RM_Register +
    +
    [Called By]
    • >>   Task_gimbal_ctrl +
    + +

    Gimbal_Output (Thumb, 280 bytes, Stack size 8 bytes, gimbal.o(.text.Gimbal_Output)) +

    [Stack]

    • Max Depth = 192
    • Call Chain = Gimbal_Output ⇒ MOTOR_DM_MITCtrl ⇒ MOTOR_DM_SendMITCmd ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   MOTOR_DM_MITCtrl +
    • >>   MOTOR_RM_SetOutput +
    • >>   MOTOR_RM_Ctrl +
    +
    [Called By]
    • >>   Task_gimbal_ctrl +
    + +

    Gimbal_UpdateFeedback (Thumb, 280 bytes, Stack size 8 bytes, gimbal.o(.text.Gimbal_UpdateFeedback)) +

    [Stack]

    • Max Depth = 256
    • Call Chain = Gimbal_UpdateFeedback ⇒ MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   MOTOR_DM_Update +
    • >>   MOTOR_DM_GetMotor +
    • >>   MOTOR_RM_Update +
    • >>   MOTOR_RM_GetMotor +
    +
    [Called By]
    • >>   Task_gimbal_ctrl +
    + +

    Gimbal_UpdateIMU (Thumb, 78 bytes, Stack size 8 bytes, gimbal.o(.text.Gimbal_UpdateIMU)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = Gimbal_UpdateIMU +
    +
    [Calls]
    • >>   Gimbal_Direction +
    +
    [Called By]
    • >>   Task_gimbal_ctrl +
    + +

    HAL_CAN_ActivateNotification (Thumb, 38 bytes, Stack size 0 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_ActivateNotification)) +

    [Called By]

    • >>   BSP_CAN_Init +
    + +

    HAL_CAN_AddTxMessage (Thumb, 146 bytes, Stack size 8 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_AddTxMessage +
    +
    [Called By]
    • >>   BSP_CAN_Transmit +
    • >>   BSP_CAN_TxCompleteCallback +
    + +

    HAL_CAN_ConfigFilter (Thumb, 222 bytes, Stack size 16 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_ConfigFilter)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_CAN_ConfigFilter +
    +
    [Called By]
    • >>   BSP_CAN_Init +
    + +

    HAL_CAN_ErrorCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_ErrorCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_ErrorCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_GetRxFifoFillLevel (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel)) +

    [Called By]

    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    HAL_CAN_GetRxMessage (Thumb, 292 bytes, Stack size 8 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_GetRxMessage +
    +
    [Called By]
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    HAL_CAN_GetTxMailboxesFreeLevel (Thumb, 40 bytes, Stack size 0 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel)) +

    [Called By]

    • >>   BSP_CAN_Transmit +
    • >>   BSP_CAN_TxCompleteCallback +
    + +

    HAL_CAN_IRQHandler (Thumb, 570 bytes, Stack size 40 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_CAN_IRQHandler ⇒ HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   HAL_CAN_WakeUpFromRxMsgCallback +
    • >>   HAL_CAN_TxMailbox2CompleteCallback +
    • >>   HAL_CAN_TxMailbox2AbortCallback +
    • >>   HAL_CAN_TxMailbox1CompleteCallback +
    • >>   HAL_CAN_TxMailbox1AbortCallback +
    • >>   HAL_CAN_TxMailbox0CompleteCallback +
    • >>   HAL_CAN_TxMailbox0AbortCallback +
    • >>   HAL_CAN_SleepCallback +
    • >>   HAL_CAN_RxFifo1MsgPendingCallback +
    • >>   HAL_CAN_RxFifo1FullCallback +
    • >>   HAL_CAN_RxFifo0MsgPendingCallback +
    • >>   HAL_CAN_RxFifo0FullCallback +
    • >>   HAL_CAN_ErrorCallback +
    +
    [Called By]
    • >>   CAN2_TX_IRQHandler +
    • >>   CAN2_SCE_IRQHandler +
    • >>   CAN2_RX1_IRQHandler +
    • >>   CAN1_TX_IRQHandler +
    • >>   CAN1_SCE_IRQHandler +
    • >>   CAN1_RX1_IRQHandler +
    • >>   CAN1_RX0_IRQHandler +
    + +

    HAL_CAN_Init (Thumb, 244 bytes, Stack size 16 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_Init)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = HAL_CAN_Init ⇒ HAL_CAN_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   HAL_CAN_MspInit +
    +
    [Called By]
    • >>   MX_CAN2_Init +
    • >>   MX_CAN1_Init +
    + +

    HAL_CAN_MspInit (Thumb, 362 bytes, Stack size 40 bytes, can.o(.text.HAL_CAN_MspInit)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = HAL_CAN_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    • >>   HAL_GPIO_Init +
    +
    [Called By]
    • >>   HAL_CAN_Init +
    + +

    HAL_CAN_RxFifo0FullCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_RxFifo0FullCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_RxFifo0FullCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_RxFifo0MsgPendingCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_RxFifo0MsgPendingCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_RxFifo1FullCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_RxFifo1FullCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_RxFifo1FullCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_RxFifo1MsgPendingCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_RxFifo1MsgPendingCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_SleepCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_SleepCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_SleepCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_Start (Thumb, 90 bytes, Stack size 16 bytes, stm32f4xx_hal_can.o(.text.HAL_CAN_Start)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_CAN_Start +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   BSP_CAN_Init +
    + +

    HAL_CAN_TxMailbox0AbortCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox0AbortCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_TxMailbox0CompleteCallback (Thumb, 34 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox0CompleteCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_TxMailbox1AbortCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox1AbortCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_TxMailbox1CompleteCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox1CompleteCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_TxMailbox2AbortCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox2AbortCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_TxMailbox2CompleteCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_TxMailbox2CompleteCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_CAN_WakeUpFromRxMsgCallback (Thumb, 36 bytes, Stack size 8 bytes, can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_CAN_WakeUpFromRxMsgCallback +
    +
    [Calls]
    • >>   CAN_Get +
    +
    [Called By]
    • >>   HAL_CAN_IRQHandler +
    + +

    HAL_DMA_Abort (Thumb, 128 bytes, Stack size 16 bytes, stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_DMA_Abort +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   HAL_UART_IRQHandler +
    + +

    HAL_DMA_Abort_IT (Thumb, 36 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT)) +

    [Called By]

    • >>   HAL_UART_IRQHandler +
    + +

    HAL_DMA_IRQHandler (Thumb, 396 bytes, Stack size 24 bytes, stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_DMA_IRQHandler +
    +
    [Called By]
    • >>   DMA2_Stream3_IRQHandler +
    • >>   DMA2_Stream2_IRQHandler +
    • >>   DMA1_Stream1_IRQHandler +
    + +

    HAL_DMA_Init (Thumb, 206 bytes, Stack size 24 bytes, stm32f4xx_hal_dma.o(.text.HAL_DMA_Init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_DMA_Init +
    +
    [Calls]
    • >>   DMA_CheckFifoParam +
    • >>   DMA_CalcBaseAndBitshift +
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   HAL_UART_MspInit +
    • >>   HAL_SPI_MspInit +
    + +

    HAL_DMA_Start_IT (Thumb, 98 bytes, Stack size 16 bytes, stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   DMA_SetConfig +
    +
    [Called By]
    • >>   UART_Start_Receive_DMA +
    • >>   HAL_UART_Transmit_DMA +
    • >>   HAL_SPI_Transmit_DMA +
    • >>   HAL_SPI_TransmitReceive_DMA +
    • >>   HAL_SPI_Receive_DMA +
    + +

    HAL_Delay (Thumb, 40 bytes, Stack size 16 bytes, stm32f4xx_hal.o(.text.HAL_Delay)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_Delay +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   BSP_TIME_Delay +
    + +

    HAL_GPIO_EXTI_Callback (Thumb, 44 bytes, Stack size 16 bytes, gpio_1.o(.text.HAL_GPIO_EXTI_Callback)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_GPIO_EXTI_Callback +
    +
    [Called By]
    • >>   HAL_GPIO_EXTI_IRQHandler +
    + +

    HAL_GPIO_EXTI_IRQHandler (Thumb, 26 bytes, Stack size 8 bytes, stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_GPIO_EXTI_IRQHandler ⇒ HAL_GPIO_EXTI_Callback +
    +
    [Calls]
    • >>   HAL_GPIO_EXTI_Callback +
    +
    [Called By]
    • >>   EXTI9_5_IRQHandler +
    • >>   EXTI4_IRQHandler +
    • >>   EXTI3_IRQHandler +
    • >>   EXTI0_IRQHandler +
    + +

    HAL_GPIO_Init (Thumb, 410 bytes, Stack size 48 bytes, stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_GPIO_Init +
    +
    [Called By]
    • >>   HAL_UART_MspInit +
    • >>   HAL_TIM_MspPostInit +
    • >>   HAL_SPI_MspInit +
    • >>   HAL_I2C_MspInit +
    • >>   HAL_CAN_MspInit +
    • >>   MX_GPIO_Init +
    + +

    HAL_GPIO_ReadPin (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(.text.HAL_GPIO_ReadPin)) +

    [Called By]

    • >>   BSP_GPIO_ReadPin +
    + +

    HAL_GPIO_WritePin (Thumb, 10 bytes, Stack size 0 bytes, stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin)) +

    [Called By]

    • >>   MX_GPIO_Init +
    • >>   BSP_GPIO_WritePin +
    + +

    HAL_GetTick (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_hal.o(.text.HAL_GetTick)) +

    [Called By]

    • >>   HAL_Delay +
    • >>   HAL_DMA_Abort +
    • >>   HAL_CAN_Start +
    • >>   HAL_DMA_Init +
    • >>   HAL_CAN_Init +
    • >>   HAL_RCC_OscConfig +
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_SPI_TransmitReceive +
    • >>   HAL_SPI_Transmit +
    • >>   HAL_SPI_Receive +
    • >>   SPI_WaitFlagStateUntilTimeout +
    • >>   SPI_DMATransmitReceiveCplt +
    • >>   SPI_DMATransmitCplt +
    • >>   SPI_DMAReceiveCplt +
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    HAL_I2C_Init (Thumb, 408 bytes, Stack size 24 bytes, stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = HAL_I2C_Init ⇒ HAL_I2C_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_RCC_GetPCLK1Freq +
    • >>   HAL_I2C_MspInit +
    +
    [Called By]
    • >>   MX_I2C2_Init +
    + +

    HAL_I2C_MspInit (Thumb, 112 bytes, Stack size 40 bytes, i2c.o(.text.HAL_I2C_MspInit)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = HAL_I2C_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_GPIO_Init +
    +
    [Called By]
    • >>   HAL_I2C_Init +
    + +

    HAL_IncTick (Thumb, 26 bytes, Stack size 0 bytes, stm32f4xx_hal.o(.text.HAL_IncTick)) +

    [Called By]

    • >>   SysTick_Handler +
    + +

    HAL_Init (Thumb, 54 bytes, Stack size 8 bytes, stm32f4xx_hal.o(.text.HAL_Init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_Init ⇒ HAL_InitTick ⇒ HAL_SYSTICK_Config ⇒ SysTick_Config +
    +
    [Calls]
    • >>   HAL_NVIC_SetPriorityGrouping +
    • >>   HAL_InitTick +
    • >>   HAL_MspInit +
    +
    [Called By]
    • >>   main +
    + +

    HAL_InitTick (Thumb, 80 bytes, Stack size 16 bytes, stm32f4xx_hal.o(.text.HAL_InitTick)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = HAL_InitTick ⇒ HAL_SYSTICK_Config ⇒ SysTick_Config +
    +
    [Calls]
    • >>   HAL_SYSTICK_Config +
    • >>   HAL_NVIC_SetPriority +
    +
    [Called By]
    • >>   HAL_RCC_ClockConfig +
    • >>   HAL_Init +
    + +

    HAL_MspInit (Thumb, 70 bytes, Stack size 16 bytes, stm32f4xx_hal_msp.o(.text.HAL_MspInit)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_MspInit ⇒ HAL_NVIC_SetPriority +
    +
    [Calls]
    • >>   HAL_NVIC_SetPriority +
    +
    [Called By]
    • >>   HAL_Init +
    + +

    HAL_NVIC_DisableIRQ (Thumb, 8 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_NVIC_DisableIRQ +
    +
    [Calls]
    • >>   __NVIC_DisableIRQ +
    +
    [Called By]
    • >>   BSP_GPIO_DisableIRQ +
    + +

    HAL_NVIC_EnableIRQ (Thumb, 8 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_NVIC_EnableIRQ +
    +
    [Calls]
    • >>   __NVIC_EnableIRQ +
    +
    [Called By]
    • >>   HAL_UART_MspInit +
    • >>   HAL_CAN_MspInit +
    • >>   MX_GPIO_Init +
    • >>   MX_DMA_Init +
    • >>   BSP_GPIO_EnableIRQ +
    + +

    HAL_NVIC_SetPriority (Thumb, 30 bytes, Stack size 16 bytes, stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_NVIC_SetPriority +
    +
    [Calls]
    • >>   __NVIC_SetPriority +
    • >>   __NVIC_GetPriorityGrouping +
    • >>   NVIC_EncodePriority +
    +
    [Called By]
    • >>   HAL_InitTick +
    • >>   HAL_MspInit +
    • >>   HAL_UART_MspInit +
    • >>   HAL_CAN_MspInit +
    • >>   MX_GPIO_Init +
    • >>   MX_DMA_Init +
    + +

    HAL_NVIC_SetPriorityGrouping (Thumb, 8 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_NVIC_SetPriorityGrouping +
    +
    [Calls]
    • >>   __NVIC_SetPriorityGrouping +
    +
    [Called By]
    • >>   HAL_Init +
    + +

    HAL_RCC_ClockConfig (Thumb, 352 bytes, Stack size 24 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod +
    +
    [Calls]
    • >>   HAL_RCC_GetSysClockFreq +
    • >>   HAL_InitTick +
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   SystemClock_Config +
    + +

    HAL_RCC_GetHCLKFreq (Thumb, 12 bytes, Stack size 0 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)) +

    [Called By]

    • >>   HAL_RCC_GetPCLK2Freq +
    • >>   HAL_RCC_GetPCLK1Freq +
    + +

    HAL_RCC_GetPCLK1Freq (Thumb, 34 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_RCC_GetPCLK1Freq +
    +
    [Calls]
    • >>   HAL_RCC_GetHCLKFreq +
    +
    [Called By]
    • >>   HAL_I2C_Init +
    • >>   UART_SetConfig +
    + +

    HAL_RCC_GetPCLK2Freq (Thumb, 34 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_RCC_GetPCLK2Freq +
    +
    [Calls]
    • >>   HAL_RCC_GetHCLKFreq +
    +
    [Called By]
    • >>   UART_SetConfig +
    + +

    HAL_RCC_GetSysClockFreq (Thumb, 104 bytes, Stack size 8 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod +
    +
    [Calls]
    • >>   __aeabi_uldivmod +
    +
    [Called By]
    • >>   HAL_RCC_ClockConfig +
    + +

    HAL_RCC_OscConfig (Thumb, 840 bytes, Stack size 32 bytes, stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_RCC_OscConfig +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   SystemClock_Config +
    + +

    HAL_SPI_ErrorCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_ErrorCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_ErrorCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMATransmitReceiveCplt +
    • >>   SPI_DMATransmitCplt +
    • >>   SPI_DMAReceiveCplt +
    • >>   SPI_DMAError +
    + +

    HAL_SPI_Init (Thumb, 180 bytes, Stack size 16 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_Init)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = HAL_SPI_Init ⇒ HAL_SPI_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_SPI_MspInit +
    +
    [Called By]
    • >>   MX_SPI1_Init +
    + +

    HAL_SPI_MspInit (Thumb, 302 bytes, Stack size 64 bytes, spi.o(.text.HAL_SPI_MspInit)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = HAL_SPI_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_DMA_Init +
    • >>   HAL_GPIO_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   HAL_SPI_Init +
    + +

    HAL_SPI_Receive (Thumb, 370 bytes, Stack size 32 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   HAL_SPI_TransmitReceive +
    • >>   SPI_EndRxTransaction +
    +
    [Called By]
    • >>   BSP_SPI_Receive +
    + +

    HAL_SPI_Receive_DMA (Thumb, 236 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_SPI_Receive_DMA ⇒ HAL_SPI_TransmitReceive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_DMA_Start_IT +
    • >>   HAL_SPI_TransmitReceive_DMA +
    +
    [Called By]
    • >>   BSP_SPI_Receive +
    + +

    HAL_SPI_RxCpltCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_RxCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_RxCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMAReceiveCplt +
    + +

    HAL_SPI_RxHalfCpltCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_RxHalfCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_RxHalfCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMAHalfReceiveCplt +
    + +

    HAL_SPI_Transmit (Thumb, 394 bytes, Stack size 32 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = HAL_SPI_Transmit ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   SPI_EndRxTxTransaction +
    +
    [Called By]
    • >>   BSP_SPI_Transmit +
    + +

    HAL_SPI_TransmitReceive (Thumb, 504 bytes, Stack size 32 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   SPI_EndRxTxTransaction +
    +
    [Called By]
    • >>   HAL_SPI_Receive +
    + +

    HAL_SPI_TransmitReceive_DMA (Thumb, 292 bytes, Stack size 16 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = HAL_SPI_TransmitReceive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_DMA_Start_IT +
    +
    [Called By]
    • >>   HAL_SPI_Receive_DMA +
    + +

    HAL_SPI_Transmit_DMA (Thumb, 204 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_SPI_Transmit_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_DMA_Start_IT +
    +
    [Called By]
    • >>   BSP_SPI_Transmit +
    + +

    HAL_SPI_TxCpltCallback (Thumb, 32 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_TxCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_TxCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMATransmitCplt +
    + +

    HAL_SPI_TxHalfCpltCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_TxHalfCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_TxHalfCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMAHalfTransmitCplt +
    + +

    HAL_SPI_TxRxCpltCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_TxRxCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_TxRxCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMATransmitReceiveCplt +
    + +

    HAL_SPI_TxRxHalfCpltCallback (Thumb, 34 bytes, Stack size 8 bytes, spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_SPI_TxRxHalfCpltCallback +
    +
    [Calls]
    • >>   SPI_Get +
    +
    [Called By]
    • >>   SPI_DMAHalfTransmitReceiveCplt +
    + +

    HAL_SYSTICK_Config (Thumb, 8 bytes, Stack size 8 bytes, stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_SYSTICK_Config ⇒ SysTick_Config +
    +
    [Calls]
    • >>   SysTick_Config +
    +
    [Called By]
    • >>   HAL_InitTick +
    + +

    HAL_TIM_Base_Init (Thumb, 90 bytes, Stack size 8 bytes, stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_TIM_Base_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   HAL_TIM_Base_MspInit +
    • >>   TIM_Base_SetConfig +
    +
    [Called By]
    • >>   MX_TIM10_Init +
    + +

    HAL_TIM_Base_MspInit (Thumb, 54 bytes, Stack size 4 bytes, tim.o(.text.HAL_TIM_Base_MspInit)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = HAL_TIM_Base_MspInit +
    +
    [Called By]
    • >>   HAL_TIM_Base_Init +
    + +

    HAL_TIM_MspPostInit (Thumb, 94 bytes, Stack size 32 bytes, tim.o(.text.HAL_TIM_MspPostInit)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = HAL_TIM_MspPostInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_GPIO_Init +
    +
    [Called By]
    • >>   MX_TIM10_Init +
    + +

    HAL_TIM_PWM_ConfigChannel (Thumb, 152 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = HAL_TIM_PWM_ConfigChannel ⇒ TIM_OC2_SetConfig +
    +
    [Calls]
    • >>   TIM_OC2_SetConfig +
    • >>   TIM_OC4_SetConfig +
    • >>   TIM_OC3_SetConfig +
    • >>   TIM_OC1_SetConfig +
    +
    [Called By]
    • >>   MX_TIM10_Init +
    + +

    HAL_TIM_PWM_Init (Thumb, 90 bytes, Stack size 8 bytes, stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = HAL_TIM_PWM_Init ⇒ TIM_Base_SetConfig +
    +
    [Calls]
    • >>   TIM_Base_SetConfig +
    • >>   HAL_TIM_PWM_MspInit +
    +
    [Called By]
    • >>   MX_TIM10_Init +
    + +

    HAL_TIM_PWM_MspInit (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit)) +

    [Called By]

    • >>   HAL_TIM_PWM_Init +
    + +

    HAL_TIM_PWM_Start (Thumb, 290 bytes, Stack size 8 bytes, stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = HAL_TIM_PWM_Start ⇒ TIM_CCxChannelCmd +
    +
    [Calls]
    • >>   TIM_CCxChannelCmd +
    +
    [Called By]
    • >>   BSP_PWM_Start +
    + +

    HAL_UARTEx_RxEventCallback (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback)) +

    [Called By]

    • >>   HAL_UART_IRQHandler +
    • >>   UART_Receive_IT +
    • >>   UART_DMARxHalfCplt +
    • >>   UART_DMAReceiveCplt +
    + +

    HAL_UART_ErrorCallback (Thumb, 38 bytes, Stack size 8 bytes, uart.o(.text.HAL_UART_ErrorCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_ErrorCallback +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   HAL_UART_IRQHandler +
    • >>   UART_DMAError +
    • >>   UART_DMAAbortOnError +
    + +

    HAL_UART_IRQHandler (Thumb, 602 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = HAL_UART_IRQHandler ⇒ UART_Receive_IT ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_DMA_Abort_IT +
    • >>   HAL_DMA_Abort +
    • >>   HAL_UARTEx_RxEventCallback +
    • >>   UART_Transmit_IT +
    • >>   UART_Receive_IT +
    • >>   UART_EndTransmit_IT +
    • >>   UART_EndRxTransfer +
    • >>   HAL_UART_ErrorCallback +
    +
    [Called By]
    • >>   USART6_IRQHandler +
    • >>   USART2_IRQHandler +
    • >>   USART1_IRQHandler +
    + +

    HAL_UART_Init (Thumb, 96 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_Init)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_UART_MspInit +
    • >>   UART_SetConfig +
    +
    [Called By]
    • >>   MX_USART6_UART_Init +
    • >>   MX_USART3_UART_Init +
    • >>   MX_USART2_UART_Init +
    • >>   MX_USART1_UART_Init +
    + +

    HAL_UART_MspInit (Thumb, 614 bytes, Stack size 56 bytes, usart.o(.text.HAL_UART_MspInit)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_DMA_Init +
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    • >>   HAL_GPIO_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   HAL_UART_Init +
    + +

    HAL_UART_Receive_DMA (Thumb, 44 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = HAL_UART_Receive_DMA ⇒ UART_Start_Receive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   UART_Start_Receive_DMA +
    +
    [Called By]
    • >>   BSP_UART_Receive +
    • >>   DR16_StartDmaRecv +
    + +

    HAL_UART_Receive_IT (Thumb, 42 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_Receive_IT +
    +
    [Calls]
    • >>   UART_Start_Receive_IT +
    +
    [Called By]
    • >>   BSP_UART_Receive +
    + +

    HAL_UART_RxCpltCallback (Thumb, 38 bytes, Stack size 8 bytes, uart.o(.text.HAL_UART_RxCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   UART_Receive_IT +
    • >>   UART_DMAReceiveCplt +
    + +

    HAL_UART_RxHalfCpltCallback (Thumb, 38 bytes, Stack size 8 bytes, uart.o(.text.HAL_UART_RxHalfCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_RxHalfCpltCallback +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   UART_DMARxHalfCplt +
    + +

    HAL_UART_Transmit_DMA (Thumb, 140 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = HAL_UART_Transmit_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_DMA_Start_IT +
    +
    [Called By]
    • >>   BSP_UART_Transmit +
    + +

    HAL_UART_Transmit_IT (Thumb, 56 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_IT)) +

    [Called By]

    • >>   BSP_UART_Transmit +
    + +

    HAL_UART_TxCpltCallback (Thumb, 38 bytes, Stack size 8 bytes, uart.o(.text.HAL_UART_TxCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_TxCpltCallback +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   UART_EndTransmit_IT +
    • >>   UART_DMATransmitCplt +
    + +

    HAL_UART_TxHalfCpltCallback (Thumb, 36 bytes, Stack size 8 bytes, uart.o(.text.HAL_UART_TxHalfCpltCallback)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = HAL_UART_TxHalfCpltCallback +
    +
    [Calls]
    • >>   UART_Get +
    +
    [Called By]
    • >>   UART_DMATxHalfCplt +
    + +

    HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.HardFault_Handler)) +

    [Calls]

    • >>   HardFault_Handler +
    +
    [Called By]
    • >>   HardFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    InvSqrt (Thumb, 66 bytes, Stack size 0 bytes, user_math.o(.text.InvSqrt)) +

    [Called By]

    • >>   AHRS_Update +
    • >>   AHRS_UpdateIMU +
    + +

    LowPassFilter2p_Apply (Thumb, 124 bytes, Stack size 40 bytes, filter.o(.text.LowPassFilter2p_Apply)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   __ARM_isinff +
    +
    [Called By]
    • >>   PID_Calc +
    • >>   LowPassFilter2p_Reset +
    • >>   Shoot_RunningFSM +
    • >>   Shoot_UpdateFeedback +
    • >>   Gimbal_Control +
    + +

    LowPassFilter2p_Init (Thumb, 164 bytes, Stack size 8 bytes, filter.o(.text.LowPassFilter2p_Init)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = LowPassFilter2p_Init ⇒ __hardfp_tanf ⇒ __mathlib_rredf2 +
    +
    [Calls]
    • >>   __hardfp_tanf +
    +
    [Called By]
    • >>   PID_Init +
    • >>   Shoot_Init +
    • >>   Gimbal_Init +
    + +

    LowPassFilter2p_Reset (Thumb, 92 bytes, Stack size 24 bytes, filter.o(.text.LowPassFilter2p_Reset)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = LowPassFilter2p_Reset ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   LowPassFilter2p_Apply +
    • >>   __ARM_isfinitef +
    +
    [Called By]
    • >>   PID_Reset +
    • >>   Shoot_ResetCalu +
    • >>   Gimbal_SetMode +
    + +

    MOTOR_DM_Enable (Thumb, 70 bytes, Stack size 24 bytes, motor_dm.o(.text.MOTOR_DM_Enable)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = MOTOR_DM_Enable ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   BSP_CAN_TransmitStdDataFrame +
    • >>   MOTOR_DM_GetMotor +
    +
    [Called By]
    • >>   Gimbal_Init +
    + +

    MOTOR_DM_GetMotor (Thumb, 88 bytes, Stack size 24 bytes, motor_dm.o(.text.MOTOR_DM_GetMotor)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = MOTOR_DM_GetMotor +
    +
    [Calls]
    • >>   MOTOR_DM_GetCANManager +
    +
    [Called By]
    • >>   Gimbal_UpdateFeedback +
    • >>   MOTOR_DM_MITCtrl +
    • >>   MOTOR_DM_Enable +
    + +

    MOTOR_DM_MITCtrl (Thumb, 46 bytes, Stack size 8 bytes, motor_dm.o(.text.MOTOR_DM_MITCtrl)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = MOTOR_DM_MITCtrl ⇒ MOTOR_DM_SendMITCmd ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   MOTOR_DM_GetMotor +
    • >>   MOTOR_DM_SendMITCmd +
    +
    [Called By]
    • >>   Gimbal_Output +
    + +

    MOTOR_DM_Register (Thumb, 164 bytes, Stack size 16 bytes, motor_dm.o(.text.MOTOR_DM_Register)) +

    [Stack]

    • Max Depth = 216 + Unknown Stack Size +
    • Call Chain = MOTOR_DM_Register ⇒ BSP_CAN_RegisterId ⇒ BSP_CAN_CreateIdQueue ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_Malloc +
    • >>   BSP_Free +
    • >>   BSP_CAN_RegisterId +
    • >>   __aeabi_memclr8 +
    • >>   MOTOR_DM_GetCANManager +
    • >>   MOTOR_DM_CreateCANManager +
    +
    [Called By]
    • >>   Gimbal_Init +
    + +

    MOTOR_DM_Update (Thumb, 160 bytes, Stack size 48 bytes, motor_dm.o(.text.MOTOR_DM_Update)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = MOTOR_DM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_TIME_Get +
    • >>   BSP_CAN_GetMessage +
    • >>   MOTOR_DM_ParseFeedbackFrame +
    • >>   MOTOR_DM_GetCANManager +
    +
    [Called By]
    • >>   Gimbal_UpdateFeedback +
    + +

    MOTOR_RM_Ctrl (Thumb, 216 bytes, Stack size 32 bytes, motor_rm.o(.text.MOTOR_RM_Ctrl)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = MOTOR_RM_Ctrl ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   MOTOR_RM_GetCANManager +
    • >>   BSP_CAN_TransmitStdDataFrame +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    • >>   Gimbal_Output +
    + +

    MOTOR_RM_GetMotor (Thumb, 80 bytes, Stack size 24 bytes, motor_rm.o(.text.MOTOR_RM_GetMotor)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = MOTOR_RM_GetMotor +
    +
    [Calls]
    • >>   MOTOR_RM_GetCANManager +
    +
    [Called By]
    • >>   Shoot_UpdateFeedback +
    • >>   Gimbal_UpdateFeedback +
    • >>   MOTOR_RM_SetOutput +
    + +

    MOTOR_RM_Register (Thumb, 166 bytes, Stack size 16 bytes, motor_rm.o(.text.MOTOR_RM_Register)) +

    [Stack]

    • Max Depth = 216 + Unknown Stack Size +
    • Call Chain = MOTOR_RM_Register ⇒ BSP_CAN_RegisterId ⇒ BSP_CAN_CreateIdQueue ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   MOTOR_RM_GetCANManager +
    • >>   MOTOR_RM_CreateCANManager +
    • >>   BSP_Malloc +
    • >>   BSP_Free +
    • >>   BSP_CAN_RegisterId +
    • >>   __aeabi_memclr8 +
    +
    [Called By]
    • >>   Shoot_Init +
    • >>   Gimbal_Init +
    + +

    MOTOR_RM_Relax (Thumb, 16 bytes, Stack size 8 bytes, motor_rm.o(.text.MOTOR_RM_Relax)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = MOTOR_RM_Relax ⇒ MOTOR_RM_SetOutput ⇒ MOTOR_RM_GetMotor +
    +
    [Calls]
    • >>   MOTOR_RM_SetOutput +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    + +

    MOTOR_RM_SetOutput (Thumb, 158 bytes, Stack size 32 bytes, motor_rm.o(.text.MOTOR_RM_SetOutput)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = MOTOR_RM_SetOutput ⇒ MOTOR_RM_GetMotor +
    +
    [Calls]
    • >>   MOTOR_RM_GetLogicalIndex +
    • >>   MOTOR_RM_GetLSB +
    • >>   MOTOR_RM_GetCANManager +
    • >>   MOTOR_RM_GetMotor +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    • >>   Gimbal_Output +
    • >>   MOTOR_RM_Relax +
    + +

    MOTOR_RM_Update (Thumb, 198 bytes, Stack size 64 bytes, motor_rm.o(.text.MOTOR_RM_Update)) +

    [Stack]

    • Max Depth = 248
    • Call Chain = MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   Motor_RM_Decode +
    • >>   MOTOR_RM_GetCANManager +
    • >>   BSP_TIME_Get +
    • >>   BSP_CAN_GetMessage +
    +
    [Called By]
    • >>   Shoot_UpdateFeedback +
    • >>   Gimbal_UpdateFeedback +
    + +

    MX_CAN1_Init (Thumb, 64 bytes, Stack size 8 bytes, can.o(.text.MX_CAN1_Init)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = MX_CAN1_Init ⇒ HAL_CAN_Init ⇒ HAL_CAN_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_CAN_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_CAN2_Init (Thumb, 64 bytes, Stack size 8 bytes, can.o(.text.MX_CAN2_Init)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = MX_CAN2_Init ⇒ HAL_CAN_Init ⇒ HAL_CAN_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_CAN_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_DMA_Init (Thumb, 106 bytes, Stack size 16 bytes, dma.o(.text.MX_DMA_Init)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = MX_DMA_Init ⇒ HAL_NVIC_SetPriority +
    +
    [Calls]
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    +
    [Called By]
    • >>   main +
    + +

    MX_FREERTOS_Init (Thumb, 58 bytes, Stack size 8 bytes, freertos.o(.text.MX_FREERTOS_Init)) +

    [Stack]

    • Max Depth = 192
    • Call Chain = MX_FREERTOS_Init ⇒ osThreadNew ⇒ xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osThreadNew +
    +
    [Called By]
    • >>   main +
    + +

    MX_GPIO_Init (Thumb, 392 bytes, Stack size 56 bytes, gpio.o(.text.MX_GPIO_Init)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = MX_GPIO_Init ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_NVIC_SetPriority +
    • >>   HAL_NVIC_EnableIRQ +
    • >>   HAL_GPIO_WritePin +
    • >>   HAL_GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    MX_I2C2_Init (Thumb, 62 bytes, Stack size 8 bytes, i2c.o(.text.MX_I2C2_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_I2C2_Init ⇒ HAL_I2C_Init ⇒ HAL_I2C_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_I2C_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_SPI1_Init (Thumb, 78 bytes, Stack size 16 bytes, spi.o(.text.MX_SPI1_Init)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = MX_SPI1_Init ⇒ HAL_SPI_Init ⇒ HAL_SPI_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_SPI_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_TIM10_Init (Thumb, 136 bytes, Stack size 40 bytes, tim.o(.text.MX_TIM10_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_TIM10_Init ⇒ HAL_TIM_MspPostInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_TIM_PWM_Init +
    • >>   HAL_TIM_PWM_ConfigChannel +
    • >>   HAL_TIM_MspPostInit +
    • >>   HAL_TIM_Base_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_USART1_UART_Init (Thumb, 56 bytes, Stack size 8 bytes, usart.o(.text.MX_USART1_UART_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_UART_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_USART2_UART_Init (Thumb, 56 bytes, Stack size 8 bytes, usart.o(.text.MX_USART2_UART_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_USART2_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_UART_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_USART3_UART_Init (Thumb, 66 bytes, Stack size 8 bytes, usart.o(.text.MX_USART3_UART_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_USART3_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_UART_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MX_USART6_UART_Init (Thumb, 56 bytes, Stack size 8 bytes, usart.o(.text.MX_USART6_UART_Init)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = MX_USART6_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_GPIO_Init +
    +
    [Calls]
    • >>   HAL_UART_Init +
    • >>   Error_Handler +
    +
    [Called By]
    • >>   main +
    + +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.MemManage_Handler)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.NMI_Handler)) +

    [Calls]

    • >>   NMI_Handler +
    +
    [Called By]
    • >>   NMI_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    PID_Calc (Thumb, 368 bytes, Stack size 56 bytes, pid.o(.text.PID_Calc)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = PID_Calc ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   CircleError +
    • >>   AbsClip +
    • >>   __ARM_isfinitef +
    • >>   LowPassFilter2p_Apply +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    • >>   Gimbal_Control +
    • >>   Task_atti_esti +
    + +

    PID_Init (Thumb, 144 bytes, Stack size 32 bytes, pid.o(.text.PID_Init)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = PID_Init ⇒ PID_Reset ⇒ LowPassFilter2p_Reset ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   PID_Reset +
    • >>   __ARM_isfinitef +
    • >>   LowPassFilter2p_Init +
    +
    [Called By]
    • >>   Shoot_Init +
    • >>   Gimbal_Init +
    • >>   Task_atti_esti +
    + +

    PID_Reset (Thumb, 44 bytes, Stack size 8 bytes, pid.o(.text.PID_Reset)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = PID_Reset ⇒ LowPassFilter2p_Reset ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   LowPassFilter2p_Reset +
    +
    [Called By]
    • >>   PID_Init +
    • >>   Shoot_ResetCalu +
    • >>   Gimbal_SetMode +
    + +

    PID_ResetIntegral (Thumb, 14 bytes, Stack size 0 bytes, pid.o(.text.PID_ResetIntegral)) +

    [Called By]

    • >>   Shoot_RunningFSM +
    • >>   Shoot_ResetIntegral +
    + +

    PendSV_Handler (Thumb, 100 bytes, Stack size 0 bytes, port.o(.text.PendSV_Handler)) +

    [Calls]

    • >>   vTaskSwitchContext +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    SVC_Handler (Thumb, 36 bytes, Stack size 0 bytes, port.o(.text.SVC_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(RESET) +
    +

    ScaleSumTo1 (Thumb, 54 bytes, Stack size 0 bytes, user_math.o(.text.ScaleSumTo1)) +

    [Called By]

    • >>   Shoot_RunningFSM +
    + +

    Shoot_CaluTargetAngle (Thumb, 160 bytes, Stack size 32 bytes, shoot.o(.text.Shoot_CaluTargetAngle)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Shoot_CaluTargetAngle +
    +
    [Calls]
    • >>   CircleAdd +
    • >>   CircleError +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    + +

    Shoot_CaluTargetRPM (Thumb, 44 bytes, Stack size 0 bytes, shoot.o(.text.Shoot_CaluTargetRPM)) +

    [Called By]

    • >>   Shoot_Control +
    + +

    Shoot_Cmd (Thumb, 40 bytes, Stack size 0 bytes, remote_cmd.o(.text.Shoot_Cmd)) +

    [Called By]

    • >>   Task_remote +
    + +

    Shoot_Control (Thumb, 108 bytes, Stack size 24 bytes, shoot.o(.text.Shoot_Control)) +

    [Stack]

    • Max Depth = 272
    • Call Chain = Shoot_Control ⇒ Shoot_JamDetectionFSM ⇒ Shoot_RunningFSM ⇒ MOTOR_RM_Ctrl ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   BSP_TIME_Get_us +
    • >>   __aeabi_ul2f +
    • >>   Shoot_JamDetectionFSM +
    • >>   Shoot_CaluTargetRPM +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    + +

    Shoot_Init (Thumb, 326 bytes, Stack size 48 bytes, shoot.o(.text.Shoot_Init)) +

    [Stack]

    • Max Depth = 288 + Unknown Stack Size +
    • Call Chain = Shoot_Init ⇒ BSP_CAN_Init ⇒ osMutexNew ⇒ xQueueCreateMutexStatic ⇒ prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   PID_Init +
    • >>   LowPassFilter2p_Init +
    • >>   BSP_CAN_Init +
    • >>   MOTOR_RM_Register +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    + +

    Shoot_JamDetectionFSM (Thumb, 304 bytes, Stack size 16 bytes, shoot.o(.text.Shoot_JamDetectionFSM)) +

    [Stack]

    • Max Depth = 248
    • Call Chain = Shoot_JamDetectionFSM ⇒ Shoot_RunningFSM ⇒ MOTOR_RM_Ctrl ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   Shoot_RunningFSM +
    +
    [Called By]
    • >>   Shoot_Control +
    + +

    Shoot_ResetCalu (Thumb, 152 bytes, Stack size 32 bytes, shoot.o(.text.Shoot_ResetCalu)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = Shoot_ResetCalu ⇒ PID_Reset ⇒ LowPassFilter2p_Reset ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   PID_Reset +
    • >>   LowPassFilter2p_Reset +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    + +

    Shoot_ResetIntegral (Thumb, 70 bytes, Stack size 16 bytes, shoot.o(.text.Shoot_ResetIntegral)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = Shoot_ResetIntegral +
    +
    [Calls]
    • >>   PID_ResetIntegral +
    +
    [Called By]
    • >>   Shoot_RunningFSM +
    + +

    Shoot_ResetOutput (Thumb, 50 bytes, Stack size 0 bytes, shoot.o(.text.Shoot_ResetOutput)) +

    [Called By]

    • >>   Shoot_RunningFSM +
    + +

    Shoot_RunningFSM (Thumb, 1264 bytes, Stack size 88 bytes, shoot.o(.text.Shoot_RunningFSM)) +

    [Stack]

    • Max Depth = 232
    • Call Chain = Shoot_RunningFSM ⇒ MOTOR_RM_Ctrl ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   ScaleSumTo1 +
    • >>   PID_ResetIntegral +
    • >>   PID_Calc +
    • >>   LowPassFilter2p_Apply +
    • >>   Shoot_ResetOutput +
    • >>   Shoot_ResetIntegral +
    • >>   Shoot_ResetCalu +
    • >>   Shoot_CaluTargetAngle +
    • >>   Shoot_CaluCoupledWeight +
    • >>   MOTOR_RM_SetOutput +
    • >>   MOTOR_RM_Relax +
    • >>   MOTOR_RM_Ctrl +
    +
    [Called By]
    • >>   Shoot_JamDetectionFSM +
    + +

    Shoot_SetMode (Thumb, 14 bytes, Stack size 0 bytes, shoot.o(.text.Shoot_SetMode)) +

    [Called By]

    • >>   Task_shoot_ctrl +
    + +

    Shoot_UpdateFeedback (Thumb, 468 bytes, Stack size 56 bytes, shoot.o(.text.Shoot_UpdateFeedback)) +

    [Stack]

    • Max Depth = 304
    • Call Chain = Shoot_UpdateFeedback ⇒ MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   LowPassFilter2p_Apply +
    • >>   __aeabi_memcpy8 +
    • >>   MOTOR_RM_Update +
    • >>   MOTOR_RM_GetMotor +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    + +

    StartDefaultTask (Thumb, 12 bytes, Stack size 8 bytes, freertos.o(.text.StartDefaultTask)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = StartDefaultTask ⇒ osThreadTerminate ⇒ vTaskDelete ⇒ prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osThreadTerminate +
    • >>   osThreadGetId +
    +
    [Address Reference Count : 1]
    • freertos.o(.text.MX_FREERTOS_Init) +
    +

    SysTick_Handler (Thumb, 20 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.SysTick_Handler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = SysTick_Handler ⇒ xPortSysTickHandler ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xPortSysTickHandler +
    • >>   HAL_IncTick +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    SystemClock_Config (Thumb, 164 bytes, Stack size 88 bytes, main.o(.text.SystemClock_Config)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SystemClock_Config ⇒ HAL_RCC_ClockConfig ⇒ HAL_RCC_GetSysClockFreq ⇒ __aeabi_uldivmod +
    +
    [Calls]
    • >>   HAL_RCC_OscConfig +
    • >>   HAL_RCC_ClockConfig +
    • >>   Error_Handler +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   main +
    + +

    SystemInit (Thumb, 18 bytes, Stack size 0 bytes, system_stm32f4xx.o(.text.SystemInit)) +
    [Address Reference Count : 1]

    • startup_stm32f407xx.o(.text) +
    +

    TIM_Base_SetConfig (Thumb, 300 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_Base_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_PWM_Init +
    • >>   HAL_TIM_Base_Init +
    + +

    TIM_CCxChannelCmd (Thumb, 36 bytes, Stack size 8 bytes, stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TIM_CCxChannelCmd +
    +
    [Called By]
    • >>   HAL_TIM_PWM_Start +
    + +

    TIM_OC2_SetConfig (Thumb, 106 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_OC2_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_PWM_ConfigChannel +
    + +

    Task_Init (Thumb, 292 bytes, Stack size 8 bytes, init.o(.text.Task_Init)) +

    [Stack]

    • Max Depth = 192
    • Call Chain = Task_Init ⇒ osThreadNew ⇒ xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osThreadTerminate +
    • >>   osThreadNew +
    • >>   osThreadGetId +
    • >>   osMessageQueueNew +
    • >>   osKernelUnlock +
    • >>   osKernelLock +
    +
    [Address Reference Count : 1]
    • freertos.o(.text.MX_FREERTOS_Init) +
    +

    Task_ai (Thumb, 160 bytes, Stack size 0 bytes, ai_1.o(.text.Task_ai)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = Task_ai ⇒ osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osMessageQueueReset +
    • >>   osMessageQueuePut +
    • >>   osMessageQueueGet +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    • >>   AI_StartSend +
    • >>   AI_StartReceiving +
    • >>   AI_ParseHost +
    • >>   AI_Get_NUC +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_atti_esti (Thumb, 612 bytes, Stack size 8 bytes, atti_esti.o(.text.Task_atti_esti)) +

    [Stack]

    • Max Depth = 224
    • Call Chain = Task_atti_esti ⇒ AHRS_Update ⇒ AHRS_UpdateIMU +
    +
    [Calls]
    • >>   BMI088_WaitNew +
    • >>   BMI088_ParseGyro +
    • >>   BMI088_ParseAccl +
    • >>   BMI088_Init +
    • >>   BMI088_GyroWaitDmaCplt +
    • >>   BMI088_GyroStartDmaRecv +
    • >>   BMI088_GetUpdateFreq +
    • >>   BMI088_AcclWaitDmaCplt +
    • >>   BMI088_AcclStartDmaRecv +
    • >>   PID_Init +
    • >>   PID_Calc +
    • >>   AHRS_Update +
    • >>   AHRS_Init +
    • >>   AHRS_GetEulr +
    • >>   BSP_PWM_Start +
    • >>   BSP_PWM_SetComp +
    • >>   osMessageQueueReset +
    • >>   osMessageQueuePut +
    • >>   osKernelUnlock +
    • >>   osKernelLock +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_chassis_ctrl (Thumb, 64 bytes, Stack size 0 bytes, chassis_ctrl.o(.text.Task_chassis_ctrl)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = Task_chassis_ctrl ⇒ osDelayUntil ⇒ vTaskDelayUntil ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_dr16 (Thumb, 128 bytes, Stack size 0 bytes, dr16_1.o(.text.Task_dr16)) +

    [Stack]

    • Max Depth = 152 + Unknown Stack Size +
    • Call Chain = Task_dr16 ⇒ osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osMessageQueueReset +
    • >>   osMessageQueuePut +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    • >>   DR16_WaitDmaCplt +
    • >>   DR16_StartDmaRecv +
    • >>   DR16_ParseData +
    • >>   DR16_Offline +
    • >>   DR16_Init +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_gimbal_ctrl (Thumb, 340 bytes, Stack size 24 bytes, gimbal_ctrl.o(.text.Task_gimbal_ctrl)) +

    [Stack]

    • Max Depth = 280 + Unknown Stack Size +
    • Call Chain = Task_gimbal_ctrl ⇒ Gimbal_UpdateFeedback ⇒ MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osMessageQueueReset +
    • >>   osMessageQueuePut +
    • >>   osMessageQueueGet +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    • >>   Gimbal_UpdateIMU +
    • >>   Gimbal_UpdateFeedback +
    • >>   Gimbal_Output +
    • >>   Gimbal_Init +
    • >>   Gimbal_Control +
    • >>   Config_GetRobotParam +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_remote (Thumb, 160 bytes, Stack size 0 bytes, remote.o(.text.Task_remote)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = Task_remote ⇒ osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osMessageQueueReset +
    • >>   osMessageQueuePut +
    • >>   osMessageQueueGet +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    • >>   Shoot_Cmd +
    • >>   Gimbal_Cmd +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    Task_shoot_ctrl (Thumb, 156 bytes, Stack size 0 bytes, shoot_ctrl.o(.text.Task_shoot_ctrl)) +

    [Stack]

    • Max Depth = 304 + Unknown Stack Size +
    • Call Chain = Task_shoot_ctrl ⇒ Shoot_UpdateFeedback ⇒ MOTOR_RM_Update ⇒ BSP_CAN_GetMessage ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osMessageQueueGet +
    • >>   osKernelGetTickFreq +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    • >>   osDelay +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    • >>   Shoot_UpdateFeedback +
    • >>   Shoot_SetMode +
    • >>   Shoot_Init +
    • >>   Shoot_Control +
    • >>   Config_GetRobotParam +
    +
    [Address Reference Count : 1]
    • init.o(.text.Task_Init) +
    +

    UART_Start_Receive_DMA (Thumb, 170 bytes, Stack size 24 bytes, stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = UART_Start_Receive_DMA ⇒ HAL_DMA_Start_IT ⇒ DMA_SetConfig +
    +
    [Calls]
    • >>   HAL_DMA_Start_IT +
    +
    [Called By]
    • >>   HAL_UART_Receive_DMA +
    + +

    UART_Start_Receive_IT (Thumb, 52 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT)) +

    [Called By]

    • >>   HAL_UART_Receive_IT +
    + +

    USART1_IRQHandler (Thumb, 24 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.USART1_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = USART1_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_IRQHandler +
    • >>   BSP_UART_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    USART2_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.USART2_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = USART2_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    USART6_IRQHandler (Thumb, 24 bytes, Stack size 8 bytes, stm32f4xx_it.o(.text.USART6_IRQHandler)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = USART6_IRQHandler ⇒ HAL_UART_IRQHandler ⇒ UART_Receive_IT ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_IRQHandler +
    • >>   BSP_UART_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f4xx_it.o(.text.UsageFault_Handler)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f407xx.o(RESET) +
    +

    eTaskGetState (Thumb, 156 bytes, Stack size 24 bytes, tasks.o(.text.eTaskGetState)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = eTaskGetState +
    +
    [Calls]
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   osThreadTerminate +
    + +

    main (Thumb, 66 bytes, Stack size 0 bytes, main.o(.text.main)) +

    [Stack]

    • Max Depth = 192 + Unknown Stack Size +
    • Call Chain = main ⇒ MX_FREERTOS_Init ⇒ osThreadNew ⇒ xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   osKernelStart +
    • >>   osKernelInitialize +
    • >>   SystemClock_Config +
    • >>   MX_USART6_UART_Init +
    • >>   MX_USART3_UART_Init +
    • >>   MX_USART2_UART_Init +
    • >>   MX_USART1_UART_Init +
    • >>   MX_TIM10_Init +
    • >>   MX_SPI1_Init +
    • >>   MX_I2C2_Init +
    • >>   MX_GPIO_Init +
    • >>   MX_FREERTOS_Init +
    • >>   MX_DMA_Init +
    • >>   MX_CAN2_Init +
    • >>   MX_CAN1_Init +
    • >>   HAL_Init +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    major_yaw_Control (Thumb, 32 bytes, Stack size 0 bytes, gimbal.o(.text.major_yaw_Control)) +

    [Called By]

    • >>   Gimbal_Control +
    + +

    osDelay (Thumb, 32 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osDelay)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = osDelay ⇒ vTaskDelay ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   vTaskDelay +
    +
    [Called By]
    • >>   BSP_TIME_Delay +
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osDelayUntil (Thumb, 52 bytes, Stack size 16 bytes, cmsis_os2.o(.text.osDelayUntil)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = osDelayUntil ⇒ vTaskDelayUntil ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetTickCount +
    • >>   vTaskDelayUntil +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osKernelGetState (Thumb, 38 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osKernelGetState)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = osKernelGetState +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    +
    [Called By]
    • >>   BSP_TIME_Delay +
    + +

    osKernelGetTickCount (Thumb, 20 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osKernelGetTickCount)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = osKernelGetTickCount ⇒ xTaskGetTickCountFromISR +
    +
    [Calls]
    • >>   xTaskGetTickCountFromISR +
    • >>   xTaskGetTickCount +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osKernelGetTickFreq (Thumb, 6 bytes, Stack size 0 bytes, cmsis_os2.o(.text.osKernelGetTickFreq)) +

    [Called By]

    • >>   BSP_TIME_Get +
    • >>   BSP_TIME_Delay +
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osKernelInitialize (Thumb, 40 bytes, Stack size 0 bytes, cmsis_os2.o(.text.osKernelInitialize)) +

    [Called By]

    • >>   main +
    + +

    osKernelLock (Thumb, 44 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osKernelLock)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = osKernelLock +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   vTaskSuspendAll +
    +
    [Called By]
    • >>   Task_Init +
    • >>   Task_atti_esti +
    + +

    osKernelStart (Thumb, 52 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osKernelStart)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = osKernelStart ⇒ vTaskStartScheduler ⇒ xTimerCreateTimerTask ⇒ prvCheckForValidListAndQueue ⇒ xQueueGenericCreateStatic ⇒ prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   vTaskStartScheduler +
    • >>   SVC_Setup +
    +
    [Called By]
    • >>   main +
    + +

    osKernelUnlock (Thumb, 68 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osKernelUnlock)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = osKernelUnlock ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xTaskResumeAll +
    +
    [Called By]
    • >>   Task_Init +
    • >>   Task_atti_esti +
    + +

    osMessageQueueGet (Thumb, 134 bytes, Stack size 16 bytes, cmsis_os2.o(.text.osMessageQueueGet)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = osMessageQueueGet ⇒ xQueueReceive ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueReceiveFromISR +
    • >>   xQueueReceive +
    +
    [Called By]
    • >>   BSP_CAN_GetMessage +
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_ai +
    + +

    osMessageQueueNew (Thumb, 160 bytes, Stack size 24 bytes, cmsis_os2.o(.text.osMessageQueueNew)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = osMessageQueueNew ⇒ xQueueGenericCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGenericCreateStatic +
    • >>   xQueueGenericCreate +
    • >>   vQueueAddToRegistry +
    +
    [Called By]
    • >>   Task_Init +
    • >>   BSP_CAN_CreateIdQueue +
    + +

    osMessageQueuePut (Thumb, 142 bytes, Stack size 24 bytes, cmsis_os2.o(.text.osMessageQueuePut)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGenericSendFromISR +
    • >>   xQueueGenericSend +
    +
    [Called By]
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osMessageQueueReset (Thumb, 36 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osMessageQueueReset)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = osMessageQueueReset ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xQueueGenericReset +
    +
    [Called By]
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    osMutexAcquire (Thumb, 82 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osMutexAcquire)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueTakeMutexRecursive +
    • >>   xQueueSemaphoreTake +
    +
    [Called By]
    • >>   BSP_CAN_GetMessage +
    • >>   BSP_CAN_CreateIdQueue +
    + +

    osMutexNew (Thumb, 150 bytes, Stack size 16 bytes, cmsis_os2.o(.text.osMutexNew)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = osMutexNew ⇒ xQueueCreateMutexStatic ⇒ prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueCreateMutexStatic +
    • >>   xQueueCreateMutex +
    • >>   vQueueAddToRegistry +
    +
    [Called By]
    • >>   BSP_CAN_Init +
    + +

    osMutexRelease (Thumb, 62 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osMutexRelease)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = osMutexRelease ⇒ xQueueGiveMutexRecursive ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGiveMutexRecursive +
    • >>   xQueueGenericSend +
    +
    [Called By]
    • >>   BSP_CAN_GetMessage +
    • >>   BSP_CAN_CreateIdQueue +
    + +

    osThreadFlagsSet (Thumb, 126 bytes, Stack size 32 bytes, cmsis_os2.o(.text.osThreadFlagsSet)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = osThreadFlagsSet ⇒ xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   xTaskGenericNotifyFromISR +
    • >>   xTaskGenericNotify +
    +
    [Called By]
    • >>   BMI088_RxCpltCallback +
    • >>   BMI088_GyroIntCallback +
    • >>   BMI088_AcclIntCallback +
    • >>   DR16_RxCpltCallback +
    + +

    osThreadFlagsWait (Thumb, 186 bytes, Stack size 48 bytes, cmsis_os2.o(.text.osThreadFlagsWait)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = osThreadFlagsWait ⇒ xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   xTaskGetTickCount +
    • >>   xTaskNotifyWait +
    +
    [Called By]
    • >>   BMI088_WaitNew +
    • >>   BMI088_GyroWaitDmaCplt +
    • >>   BMI088_AcclWaitDmaCplt +
    • >>   DR16_WaitDmaCplt +
    + +

    osThreadGetId (Thumb, 8 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osThreadGetId)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = osThreadGetId +
    +
    [Calls]
    • >>   xTaskGetCurrentTaskHandle +
    +
    [Called By]
    • >>   Task_Init +
    • >>   StartDefaultTask +
    • >>   BMI088_Init +
    • >>   DR16_Init +
    + +

    osThreadNew (Thumb, 180 bytes, Stack size 32 bytes, cmsis_os2.o(.text.osThreadNew)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = osThreadNew ⇒ xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskCreateStatic +
    • >>   xTaskCreate +
    +
    [Called By]
    • >>   Task_Init +
    • >>   MX_FREERTOS_Init +
    + +

    osThreadTerminate (Thumb, 52 bytes, Stack size 8 bytes, cmsis_os2.o(.text.osThreadTerminate)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = osThreadTerminate ⇒ vTaskDelete ⇒ prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   vTaskDelete +
    • >>   eTaskGetState +
    +
    [Called By]
    • >>   Task_Init +
    • >>   StartDefaultTask +
    + +

    pvPortMalloc (Thumb, 330 bytes, Stack size 32 bytes, heap_4.o(.text.pvPortMalloc)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    • >>   prvInsertBlockIntoFreeList +
    • >>   prvHeapInit +
    +
    [Called By]
    • >>   xTaskCreate +
    • >>   xQueueGenericCreate +
    • >>   BSP_Malloc +
    + +

    pvTaskIncrementMutexHeldCount (Thumb, 24 bytes, Stack size 0 bytes, tasks.o(.text.pvTaskIncrementMutexHeldCount)) +

    [Called By]

    • >>   xQueueSemaphoreTake +
    + +

    pxPortInitialiseStack (Thumb, 40 bytes, Stack size 0 bytes, port.o(.text.pxPortInitialiseStack)) +

    [Called By]

    • >>   prvInitialiseNewTask +
    + +

    uxListRemove (Thumb, 36 bytes, Stack size 0 bytes, list.o(.text.uxListRemove)) +

    [Called By]

    • >>   prvProcessReceivedCommands +
    • >>   prvProcessExpiredTimer +
    • >>   xTaskIncrementTick +
    • >>   vTaskDelete +
    • >>   prvCheckTasksWaitingTermination +
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   xTaskGenericNotifyFromISR +
    • >>   xTaskGenericNotify +
    • >>   xTaskRemoveFromEventList +
    • >>   xTaskPriorityInherit +
    • >>   xTaskPriorityDisinherit +
    • >>   vTaskPriorityDisinheritAfterTimeout +
    • >>   xTaskResumeAll +
    • >>   prvSwitchTimerLists +
    + +

    vApplicationGetIdleTaskMemory (Thumb, 26 bytes, Stack size 0 bytes, cmsis_os2.o(.text.vApplicationGetIdleTaskMemory)) +

    [Called By]

    • >>   vTaskStartScheduler +
    + +

    vApplicationGetTimerTaskMemory (Thumb, 28 bytes, Stack size 0 bytes, cmsis_os2.o(.text.vApplicationGetTimerTaskMemory)) +

    [Called By]

    • >>   xTimerCreateTimerTask +
    + +

    vListInitialise (Thumb, 22 bytes, Stack size 0 bytes, list.o(.text.vListInitialise)) +

    [Called By]

    • >>   prvCheckForValidListAndQueue +
    • >>   prvInitialiseTaskLists +
    • >>   xQueueGenericReset +
    + +

    vListInitialiseItem (Thumb, 6 bytes, Stack size 0 bytes, list.o(.text.vListInitialiseItem)) +

    [Called By]

    • >>   prvInitialiseNewTask +
    + +

    vListInsert (Thumb, 58 bytes, Stack size 8 bytes, list.o(.text.vListInsert)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = vListInsert +
    +
    [Called By]
    • >>   prvInsertTimerInActiveList +
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   vTaskPlaceOnEventList +
    • >>   prvSwitchTimerLists +
    + +

    vListInsertEnd (Thumb, 28 bytes, Stack size 0 bytes, list.o(.text.vListInsertEnd)) +

    [Called By]

    • >>   xTaskIncrementTick +
    • >>   vTaskDelete +
    • >>   prvAddNewTaskToReadyList +
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   xTaskGenericNotifyFromISR +
    • >>   xTaskGenericNotify +
    • >>   xTaskRemoveFromEventList +
    • >>   xTaskPriorityInherit +
    • >>   xTaskPriorityDisinherit +
    • >>   vTaskPriorityDisinheritAfterTimeout +
    • >>   vTaskPlaceOnEventListRestricted +
    • >>   xTaskResumeAll +
    + +

    vPortEnterCritical (Thumb, 70 bytes, Stack size 0 bytes, port.o(.text.vPortEnterCritical)) +

    [Called By]

    • >>   prvCheckForValidListAndQueue +
    • >>   vTaskDelete +
    • >>   eTaskGetState +
    • >>   prvCheckTasksWaitingTermination +
    • >>   prvAddNewTaskToReadyList +
    • >>   xTaskNotifyWait +
    • >>   xTaskGenericNotify +
    • >>   xTaskCheckForTimeOut +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   xQueueGenericReset +
    • >>   vQueueWaitForMessageRestricted +
    • >>   prvUnlockQueue +
    • >>   prvIsQueueFull +
    • >>   prvIsQueueEmpty +
    • >>   xTaskResumeAll +
    + +

    vPortExitCritical (Thumb, 46 bytes, Stack size 0 bytes, port.o(.text.vPortExitCritical)) +

    [Called By]

    • >>   prvCheckForValidListAndQueue +
    • >>   vTaskDelete +
    • >>   eTaskGetState +
    • >>   prvCheckTasksWaitingTermination +
    • >>   prvAddNewTaskToReadyList +
    • >>   xTaskNotifyWait +
    • >>   xTaskGenericNotify +
    • >>   xTaskCheckForTimeOut +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   xQueueGenericReset +
    • >>   vQueueWaitForMessageRestricted +
    • >>   prvUnlockQueue +
    • >>   prvIsQueueFull +
    • >>   prvIsQueueEmpty +
    • >>   xTaskResumeAll +
    + +

    vPortFree (Thumb, 138 bytes, Stack size 16 bytes, heap_4.o(.text.vPortFree)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    • >>   prvInsertBlockIntoFreeList +
    +
    [Called By]
    • >>   prvProcessReceivedCommands +
    • >>   xTaskCreate +
    • >>   prvDeleteTCB +
    • >>   BSP_Free +
    + +

    vPortSetupTimerInterrupt (Thumb, 52 bytes, Stack size 0 bytes, port.o(.text.vPortSetupTimerInterrupt)) +

    [Called By]

    • >>   xPortStartScheduler +
    + +

    vPortValidateInterruptPriority (Thumb, 98 bytes, Stack size 0 bytes, port.o(.text.vPortValidateInterruptPriority)) +

    [Called By]

    • >>   xTaskGetTickCountFromISR +
    • >>   xTaskGenericNotifyFromISR +
    • >>   xQueueReceiveFromISR +
    • >>   xQueueGenericSendFromISR +
    + +

    vQueueAddToRegistry (Thumb, 40 bytes, Stack size 0 bytes, queue.o(.text.vQueueAddToRegistry)) +

    [Called By]

    • >>   prvCheckForValidListAndQueue +
    • >>   osMutexNew +
    • >>   osMessageQueueNew +
    + +

    vQueueWaitForMessageRestricted (Thumb, 68 bytes, Stack size 16 bytes, queue.o(.text.vQueueWaitForMessageRestricted)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = vQueueWaitForMessageRestricted ⇒ vTaskPlaceOnEventListRestricted ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   vTaskPlaceOnEventListRestricted +
    • >>   prvUnlockQueue +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   prvProcessTimerOrBlockTask +
    + +

    vTaskDelay (Thumb, 84 bytes, Stack size 8 bytes, tasks.o(.text.vTaskDelay)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = vTaskDelay ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    +
    [Called By]
    • >>   osDelay +
    + +

    vTaskDelayUntil (Thumb, 168 bytes, Stack size 16 bytes, tasks.o(.text.vTaskDelayUntil)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = vTaskDelayUntil ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    +
    [Called By]
    • >>   osDelayUntil +
    + +

    vTaskDelete (Thumb, 194 bytes, Stack size 16 bytes, tasks.o(.text.vTaskDelete)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = vTaskDelete ⇒ prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvResetNextTaskUnblockTime +
    • >>   prvDeleteTCB +
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   osThreadTerminate +
    + +

    vTaskInternalSetTimeOutState (Thumb, 26 bytes, Stack size 0 bytes, tasks.o(.text.vTaskInternalSetTimeOutState)) +

    [Called By]

    • >>   xTaskCheckForTimeOut +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    + +

    vTaskMissedYield (Thumb, 14 bytes, Stack size 0 bytes, tasks.o(.text.vTaskMissedYield)) +

    [Called By]

    • >>   prvUnlockQueue +
    + +

    vTaskPlaceOnEventList (Thumb, 50 bytes, Stack size 8 bytes, tasks.o(.text.vTaskPlaceOnEventList)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = vTaskPlaceOnEventList ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   vListInsert +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    + +

    vTaskPlaceOnEventListRestricted (Thumb, 62 bytes, Stack size 16 bytes, tasks.o(.text.vTaskPlaceOnEventListRestricted)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = vTaskPlaceOnEventListRestricted ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   vListInsertEnd +
    +
    [Called By]
    • >>   vQueueWaitForMessageRestricted +
    + +

    vTaskPriorityDisinheritAfterTimeout (Thumb, 164 bytes, Stack size 16 bytes, tasks.o(.text.vTaskPriorityDisinheritAfterTimeout)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = vTaskPriorityDisinheritAfterTimeout +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    + +

    vTaskStartScheduler (Thumb, 156 bytes, Stack size 32 bytes, tasks.o(.text.vTaskStartScheduler)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = vTaskStartScheduler ⇒ xTimerCreateTimerTask ⇒ prvCheckForValidListAndQueue ⇒ xQueueGenericCreateStatic ⇒ prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xTimerCreateTimerTask +
    • >>   xTaskCreateStatic +
    • >>   xPortStartScheduler +
    • >>   vApplicationGetIdleTaskMemory +
    +
    [Called By]
    • >>   osKernelStart +
    + +

    vTaskSuspendAll (Thumb, 16 bytes, Stack size 0 bytes, tasks.o(.text.vTaskSuspendAll)) +

    [Called By]

    • >>   prvProcessTimerOrBlockTask +
    • >>   vTaskDelayUntil +
    • >>   vTaskDelay +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   vPortFree +
    • >>   pvPortMalloc +
    • >>   osKernelLock +
    + +

    vTaskSwitchContext (Thumb, 154 bytes, Stack size 0 bytes, tasks.o(.text.vTaskSwitchContext)) +

    [Called By]

    • >>   xPortStartScheduler +
    • >>   PendSV_Handler +
    + +

    xPortStartScheduler (Thumb, 274 bytes, Stack size 16 bytes, port.o(.text.xPortStartScheduler)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = xPortStartScheduler ⇒ prvTaskExitError +
    +
    [Calls]
    • >>   vTaskSwitchContext +
    • >>   vPortSetupTimerInterrupt +
    • >>   vPortEnableVFP +
    • >>   prvTaskExitError +
    • >>   prvPortStartFirstTask +
    +
    [Called By]
    • >>   vTaskStartScheduler +
    + +

    xPortSysTickHandler (Thumb, 46 bytes, Stack size 8 bytes, port.o(.text.xPortSysTickHandler)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = xPortSysTickHandler ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskIncrementTick +
    +
    [Called By]
    • >>   SysTick_Handler +
    + +

    xQueueCreateMutex (Thumb, 22 bytes, Stack size 8 bytes, queue.o(.text.xQueueCreateMutex)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = xQueueCreateMutex ⇒ xQueueGenericCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGenericCreate +
    • >>   prvInitialiseMutex +
    +
    [Called By]
    • >>   osMutexNew +
    + +

    xQueueCreateMutexStatic (Thumb, 34 bytes, Stack size 16 bytes, queue.o(.text.xQueueCreateMutexStatic)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = xQueueCreateMutexStatic ⇒ prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGenericCreateStatic +
    • >>   prvInitialiseMutex +
    +
    [Called By]
    • >>   osMutexNew +
    + +

    xQueueGenericCreate (Thumb, 70 bytes, Stack size 24 bytes, queue.o(.text.xQueueGenericCreate)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = xQueueGenericCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvInitialiseNewQueue +
    • >>   pvPortMalloc +
    +
    [Called By]
    • >>   xQueueCreateMutex +
    • >>   osMessageQueueNew +
    + +

    xQueueGenericCreateStatic (Thumb, 150 bytes, Stack size 24 bytes, queue.o(.text.xQueueGenericCreateStatic)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = xQueueGenericCreateStatic ⇒ prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   prvInitialiseNewQueue +
    +
    [Called By]
    • >>   prvCheckForValidListAndQueue +
    • >>   xQueueCreateMutexStatic +
    • >>   osMessageQueueNew +
    + +

    xQueueGenericReset (Thumb, 126 bytes, Stack size 16 bytes, queue.o(.text.xQueueGenericReset)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xTaskRemoveFromEventList +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    • >>   vListInitialise +
    +
    [Called By]
    • >>   prvInitialiseNewQueue +
    • >>   osMessageQueueReset +
    + +

    xQueueGenericSend (Thumb, 418 bytes, Stack size 48 bytes, queue.o(.text.xQueueGenericSend)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xTaskRemoveFromEventList +
    • >>   xTaskCheckForTimeOut +
    • >>   vTaskPlaceOnEventList +
    • >>   vTaskInternalSetTimeOutState +
    • >>   prvUnlockQueue +
    • >>   prvIsQueueFull +
    • >>   prvCopyDataToQueue +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueGiveMutexRecursive +
    • >>   prvInitialiseMutex +
    • >>   osMutexRelease +
    • >>   osMessageQueuePut +
    • >>   xTimerGenericCommand +
    + +

    xQueueGenericSendFromISR (Thumb, 206 bytes, Stack size 32 bytes, queue.o(.text.xQueueGenericSendFromISR)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = xQueueGenericSendFromISR ⇒ prvCopyDataToQueue ⇒ xTaskPriorityDisinherit +
    +
    [Calls]
    • >>   xTaskRemoveFromEventList +
    • >>   vPortValidateInterruptPriority +
    • >>   prvCopyDataToQueue +
    +
    [Called By]
    • >>   osMessageQueuePut +
    • >>   xTimerGenericCommand +
    + +

    xQueueGiveMutexRecursive (Thumb, 66 bytes, Stack size 16 bytes, queue.o(.text.xQueueGiveMutexRecursive)) +

    [Stack]

    • Max Depth = 144
    • Call Chain = xQueueGiveMutexRecursive ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetCurrentTaskHandle +
    • >>   xQueueGenericSend +
    +
    [Called By]
    • >>   osMutexRelease +
    + +

    xQueueReceive (Thumb, 388 bytes, Stack size 56 bytes, queue.o(.text.xQueueReceive)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = xQueueReceive ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xTaskRemoveFromEventList +
    • >>   xTaskCheckForTimeOut +
    • >>   vTaskPlaceOnEventList +
    • >>   vTaskInternalSetTimeOutState +
    • >>   prvUnlockQueue +
    • >>   prvIsQueueEmpty +
    • >>   prvCopyDataFromQueue +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   prvProcessReceivedCommands +
    • >>   osMessageQueueGet +
    + +

    xQueueReceiveFromISR (Thumb, 170 bytes, Stack size 32 bytes, queue.o(.text.xQueueReceiveFromISR)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = xQueueReceiveFromISR ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xTaskRemoveFromEventList +
    • >>   vPortValidateInterruptPriority +
    • >>   prvCopyDataFromQueue +
    +
    [Called By]
    • >>   osMessageQueueGet +
    + +

    xQueueSemaphoreTake (Thumb, 454 bytes, Stack size 56 bytes, queue.o(.text.xQueueSemaphoreTake)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xTaskRemoveFromEventList +
    • >>   xTaskPriorityInherit +
    • >>   xTaskCheckForTimeOut +
    • >>   vTaskPriorityDisinheritAfterTimeout +
    • >>   vTaskPlaceOnEventList +
    • >>   vTaskInternalSetTimeOutState +
    • >>   pvTaskIncrementMutexHeldCount +
    • >>   prvUnlockQueue +
    • >>   prvIsQueueEmpty +
    • >>   prvGetDisinheritPriorityAfterTimeout +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueTakeMutexRecursive +
    • >>   osMutexAcquire +
    + +

    xQueueTakeMutexRecursive (Thumb, 60 bytes, Stack size 16 bytes, queue.o(.text.xQueueTakeMutexRecursive)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetCurrentTaskHandle +
    • >>   xQueueSemaphoreTake +
    +
    [Called By]
    • >>   osMutexAcquire +
    + +

    xTaskCheckForTimeOut (Thumb, 136 bytes, Stack size 16 bytes, tasks.o(.text.xTaskCheckForTimeOut)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = xTaskCheckForTimeOut +
    +
    [Calls]
    • >>   vTaskInternalSetTimeOutState +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    + +

    xTaskCreate (Thumb, 102 bytes, Stack size 40 bytes, tasks.o(.text.xTaskCreate)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = xTaskCreate ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvInitialiseNewTask +
    • >>   prvAddNewTaskToReadyList +
    • >>   vPortFree +
    • >>   pvPortMalloc +
    +
    [Called By]
    • >>   osThreadNew +
    + +

    xTaskCreateStatic (Thumb, 118 bytes, Stack size 40 bytes, tasks.o(.text.xTaskCreateStatic)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = xTaskCreateStatic ⇒ prvInitialiseNewTask ⇒ __aeabi_memset4 ⇒ _memset_w +
    +
    [Calls]
    • >>   prvInitialiseNewTask +
    • >>   prvAddNewTaskToReadyList +
    +
    [Called By]
    • >>   osThreadNew +
    • >>   xTimerCreateTimerTask +
    • >>   vTaskStartScheduler +
    + +

    xTaskGenericNotify (Thumb, 252 bytes, Stack size 24 bytes, tasks.o(.text.xTaskGenericNotify)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = xTaskGenericNotify +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   osThreadFlagsSet +
    + +

    xTaskGenericNotifyFromISR (Thumb, 298 bytes, Stack size 24 bytes, tasks.o(.text.xTaskGenericNotifyFromISR)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   vPortValidateInterruptPriority +
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   osThreadFlagsSet +
    + +

    xTaskGetCurrentTaskHandle (Thumb, 12 bytes, Stack size 0 bytes, tasks.o(.text.xTaskGetCurrentTaskHandle)) +

    [Called By]

    • >>   osThreadGetId +
    • >>   xQueueTakeMutexRecursive +
    • >>   xQueueGiveMutexRecursive +
    + +

    xTaskGetSchedulerState (Thumb, 38 bytes, Stack size 0 bytes, tasks.o(.text.xTaskGetSchedulerState)) +

    [Called By]

    • >>   SysTick_Handler +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   osKernelUnlock +
    • >>   osKernelLock +
    • >>   osKernelGetState +
    • >>   xTimerGenericCommand +
    + +

    xTaskGetTickCount (Thumb, 12 bytes, Stack size 0 bytes, tasks.o(.text.xTaskGetTickCount)) +

    [Called By]

    • >>   prvSampleTimeNow +
    • >>   BSP_TIME_Get +
    • >>   osThreadFlagsWait +
    • >>   osKernelGetTickCount +
    • >>   osDelayUntil +
    + +

    xTaskGetTickCountFromISR (Thumb, 18 bytes, Stack size 8 bytes, tasks.o(.text.xTaskGetTickCountFromISR)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = xTaskGetTickCountFromISR +
    +
    [Calls]
    • >>   vPortValidateInterruptPriority +
    +
    [Called By]
    • >>   osKernelGetTickCount +
    + +

    xTaskIncrementTick (Thumb, 338 bytes, Stack size 40 bytes, tasks.o(.text.xTaskIncrementTick)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = xTaskIncrementTick +
    +
    [Calls]
    • >>   prvResetNextTaskUnblockTime +
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   xPortSysTickHandler +
    • >>   xTaskResumeAll +
    + +

    xTaskNotifyWait (Thumb, 144 bytes, Stack size 24 bytes, tasks.o(.text.xTaskNotifyWait)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = xTaskNotifyWait ⇒ prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   prvAddCurrentTaskToDelayedList +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   osThreadFlagsWait +
    + +

    xTaskPriorityDisinherit (Thumb, 146 bytes, Stack size 16 bytes, tasks.o(.text.xTaskPriorityDisinherit)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = xTaskPriorityDisinherit +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   prvCopyDataToQueue +
    + +

    xTaskPriorityInherit (Thumb, 146 bytes, Stack size 24 bytes, tasks.o(.text.xTaskPriorityInherit)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = xTaskPriorityInherit +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    + +

    xTaskRemoveFromEventList (Thumb, 142 bytes, Stack size 16 bytes, tasks.o(.text.xTaskRemoveFromEventList)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceiveFromISR +
    • >>   xQueueReceive +
    • >>   xQueueGenericSendFromISR +
    • >>   xQueueGenericSend +
    • >>   xQueueGenericReset +
    • >>   prvUnlockQueue +
    + +

    xTaskResumeAll (Thumb, 276 bytes, Stack size 40 bytes, tasks.o(.text.xTaskResumeAll)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskIncrementTick +
    • >>   prvResetNextTaskUnblockTime +
    • >>   vListInsertEnd +
    • >>   uxListRemove +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   prvProcessTimerOrBlockTask +
    • >>   vTaskDelayUntil +
    • >>   vTaskDelay +
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   vPortFree +
    • >>   pvPortMalloc +
    • >>   osKernelUnlock +
    + +

    xTimerCreateTimerTask (Thumb, 108 bytes, Stack size 32 bytes, timers.o(.text.xTimerCreateTimerTask)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = xTimerCreateTimerTask ⇒ prvCheckForValidListAndQueue ⇒ xQueueGenericCreateStatic ⇒ prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   prvCheckForValidListAndQueue +
    • >>   xTaskCreateStatic +
    • >>   vApplicationGetTimerTaskMemory +
    +
    [Called By]
    • >>   vTaskStartScheduler +
    + +

    xTimerGenericCommand (Thumb, 104 bytes, Stack size 24 bytes, timers.o(.text.xTimerGenericCommand)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetSchedulerState +
    • >>   xQueueGenericSendFromISR +
    • >>   xQueueGenericSend +
    +
    [Called By]
    • >>   prvProcessReceivedCommands +
    • >>   prvProcessExpiredTimer +
    • >>   prvSwitchTimerLists +
    + +

    __ARM_fpclassify (Thumb, 48 bytes, Stack size 8 bytes, fpclassify.o(i.__ARM_fpclassify)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __ARM_fpclassify +
    +
    [Called By]
    • >>   __hardfp_atan +
    + +

    __ARM_fpclassifyf (Thumb, 38 bytes, Stack size 0 bytes, fpclassifyf.o(i.__ARM_fpclassifyf)) +

    [Called By]

    • >>   __hardfp_tanf +
    • >>   __hardfp_atan2f +
    • >>   __hardfp_asinf +
    + +

    __hardfp_asinf (Thumb, 258 bytes, Stack size 16 bytes, asinf.o(i.__hardfp_asinf)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = __hardfp_asinf ⇒ sqrtf ⇒ __set_errno +
    +
    [Calls]
    • >>   sqrtf +
    • >>   __mathlib_flt_underflow +
    • >>   __mathlib_flt_invalid +
    • >>   __mathlib_flt_infnan +
    • >>   __ARM_fpclassifyf +
    • >>   __set_errno +
    +
    [Called By]
    • >>   AHRS_GetEulr +
    + +

    __hardfp_atan (Thumb, 622 bytes, Stack size 48 bytes, atan.o(i.__hardfp_atan)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = __hardfp_atan ⇒ __kernel_poly ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   fabs +
    • >>   __mathlib_dbl_underflow +
    • >>   __mathlib_dbl_infnan +
    • >>   __aeabi_dsub +
    • >>   __aeabi_drsub +
    • >>   __aeabi_dadd +
    • >>   __aeabi_dneg +
    • >>   __aeabi_dmul +
    • >>   __aeabi_ddiv +
    • >>   __kernel_poly +
    • >>   __ARM_fpclassify +
    +
    [Called By]
    • >>   atan +
    + +

    __hardfp_atan2 (Thumb, 448 bytes, Stack size 56 bytes, atan2.o(i.__hardfp_atan2)) +

    [Stack]

    • Max Depth = 168
    • Call Chain = __hardfp_atan2 ⇒ atan ⇒ __hardfp_atan ⇒ __kernel_poly ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   fabs +
    • >>   __mathlib_dbl_infnan2 +
    • >>   atan +
    • >>   __aeabi_cdcmpeq +
    • >>   __aeabi_dsub +
    • >>   __aeabi_drsub +
    • >>   __aeabi_dneg +
    • >>   __set_errno +
    • >>   __aeabi_ddiv +
    +
    [Called By]
    • >>   AHRS_Init +
    + +

    __hardfp_atan2f (Thumb, 594 bytes, Stack size 32 bytes, atan2f.o(i.__hardfp_atan2f)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = __hardfp_atan2f ⇒ __set_errno +
    +
    [Calls]
    • >>   __mathlib_flt_underflow +
    • >>   __mathlib_flt_infnan2 +
    • >>   __ARM_fpclassifyf +
    • >>   __set_errno +
    +
    [Called By]
    • >>   AHRS_GetEulr +
    + +

    __hardfp_tanf (Thumb, 322 bytes, Stack size 16 bytes, tanf.o(i.__hardfp_tanf)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = __hardfp_tanf ⇒ __mathlib_rredf2 +
    +
    [Calls]
    • >>   __mathlib_rredf2 +
    • >>   __mathlib_flt_underflow +
    • >>   __mathlib_flt_invalid +
    • >>   __mathlib_flt_infnan +
    • >>   __ARM_fpclassifyf +
    • >>   __set_errno +
    +
    [Called By]
    • >>   LowPassFilter2p_Init +
    + +

    __kernel_poly (Thumb, 248 bytes, Stack size 24 bytes, poly.o(i.__kernel_poly)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = __kernel_poly ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   __aeabi_dadd +
    • >>   __aeabi_dmul +
    +
    [Called By]
    • >>   __hardfp_atan +
    + +

    __mathlib_dbl_infnan (Thumb, 20 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_infnan)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __mathlib_dbl_infnan ⇒ __aeabi_dadd +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   __hardfp_atan +
    + +

    __mathlib_dbl_infnan2 (Thumb, 20 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_infnan2)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __mathlib_dbl_infnan2 ⇒ __aeabi_dadd +
    +
    [Calls]
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   __hardfp_atan2 +
    + +

    __mathlib_dbl_underflow (Thumb, 24 bytes, Stack size 8 bytes, dunder.o(i.__mathlib_dbl_underflow)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = __mathlib_dbl_underflow ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   __aeabi_dmul +
    +
    [Called By]
    • >>   __hardfp_atan +
    + +

    __mathlib_flt_infnan (Thumb, 6 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_infnan)) +

    [Called By]

    • >>   __hardfp_tanf +
    • >>   __hardfp_asinf +
    + +

    __mathlib_flt_infnan2 (Thumb, 6 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_infnan2)) +

    [Called By]

    • >>   __hardfp_atan2f +
    + +

    __mathlib_flt_invalid (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_invalid)) +

    [Called By]

    • >>   __hardfp_tanf +
    • >>   __hardfp_asinf +
    + +

    __mathlib_flt_underflow (Thumb, 10 bytes, Stack size 0 bytes, funder.o(i.__mathlib_flt_underflow)) +

    [Called By]

    • >>   __hardfp_tanf +
    • >>   __hardfp_atan2f +
    • >>   __hardfp_asinf +
    + +

    __mathlib_rredf2 (Thumb, 316 bytes, Stack size 20 bytes, rredf.o(i.__mathlib_rredf2)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = __mathlib_rredf2 +
    +
    [Called By]
    • >>   __hardfp_tanf +
    + +

    atan (Thumb, 16 bytes, Stack size 8 bytes, atan.o(i.atan)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = atan ⇒ __hardfp_atan ⇒ __kernel_poly ⇒ __aeabi_dmul +
    +
    [Calls]
    • >>   __hardfp_atan +
    +
    [Called By]
    • >>   __hardfp_atan2 +
    + +

    fabs (Thumb, 24 bytes, Stack size 8 bytes, fabs.o(i.fabs)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = fabs +
    +
    [Called By]
    • >>   __hardfp_atan +
    • >>   __hardfp_atan2 +
    + +

    sqrtf (Thumb, 62 bytes, Stack size 16 bytes, sqrtf.o(i.sqrtf)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = sqrtf ⇒ __set_errno +
    +
    [Calls]
    • >>   __set_errno +
    +
    [Called By]
    • >>   __hardfp_asinf +
    + +

    __aeabi_dneg (Thumb, 0 bytes, Stack size 0 bytes, basic.o(x$fpl$basic)) +

    [Called By]

    • >>   __hardfp_atan +
    • >>   __hardfp_atan2 +
    + +

    _dneg (Thumb, 6 bytes, Stack size 0 bytes, basic.o(x$fpl$basic), UNUSED) + +

    __aeabi_fneg (Thumb, 0 bytes, Stack size 0 bytes, basic.o(x$fpl$basic), UNUSED) + +

    _fneg (Thumb, 6 bytes, Stack size 0 bytes, basic.o(x$fpl$basic), UNUSED) + +

    _dabs (Thumb, 6 bytes, Stack size 0 bytes, basic.o(x$fpl$basic), UNUSED) + +

    _fabs (Thumb, 6 bytes, Stack size 0 bytes, basic.o(x$fpl$basic), UNUSED) + +

    __aeabi_d2f (Thumb, 0 bytes, Stack size 32 bytes, d2f.o(x$fpl$d2f)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_d2f +
    +
    [Called By]
    • >>   AHRS_Init +
    • >>   Gimbal_Cmd +
    + +

    _d2f (Thumb, 98 bytes, Stack size 32 bytes, d2f.o(x$fpl$d2f), UNUSED) +

    [Calls]

    • >>   __fpl_fretinf +
    • >>   __fpl_dnaninf +
    + +

    __aeabi_dadd (Thumb, 0 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_dadd +
    +
    [Called By]
    • >>   __mathlib_dbl_infnan2 +
    • >>   __mathlib_dbl_infnan +
    • >>   __hardfp_atan +
    • >>   __kernel_poly +
    + +

    _dadd (Thumb, 332 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    • >>   _dsub1 +
    + +

    __fpl_dcmp_Inf (Thumb, 24 bytes, Stack size 0 bytes, dcmpi.o(x$fpl$dcmpinf), UNUSED) +

    [Called By]

    • >>   _dcmpeq +
    + +

    __aeabi_ddiv (Thumb, 0 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_ddiv +
    +
    [Called By]
    • >>   __hardfp_atan +
    • >>   __hardfp_atan2 +
    • >>   Gimbal_Cmd +
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    _ddiv (Thumb, 556 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    + +

    __aeabi_cdcmpeq (Thumb, 0 bytes, Stack size 32 bytes, deqf.o(x$fpl$deqf)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_cdcmpeq +
    +
    [Called By]
    • >>   __hardfp_atan2 +
    + +

    _dcmpeq (Thumb, 120 bytes, Stack size 32 bytes, deqf.o(x$fpl$deqf), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    • >>   __fpl_dcmp_Inf +
    + +

    __aeabi_d2uiz (Thumb, 0 bytes, Stack size 32 bytes, dfixu.o(x$fpl$dfixu)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_d2uiz +
    +
    [Called By]
    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    _dfixu (Thumb, 90 bytes, Stack size 32 bytes, dfixu.o(x$fpl$dfixu), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    + +

    __aeabi_i2d (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt)) +

    [Called By]

    • >>   Gimbal_Cmd +
    + +

    _dflt (Thumb, 46 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dflt), UNUSED) + +

    __aeabi_ui2d (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu)) +

    [Called By]

    • >>   Task_shoot_ctrl +
    • >>   Task_remote +
    • >>   Task_gimbal_ctrl +
    • >>   Task_dr16 +
    • >>   Task_chassis_ctrl +
    • >>   Task_atti_esti +
    • >>   Task_ai +
    + +

    _dfltu (Thumb, 38 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu), UNUSED) + +

    __aeabi_dmul (Thumb, 0 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_dmul +
    +
    [Called By]
    • >>   __mathlib_dbl_underflow +
    • >>   __hardfp_atan +
    • >>   Gimbal_Cmd +
    • >>   __kernel_poly +
    + +

    _dmul (Thumb, 332 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    + +

    __fpl_dnaninf (Thumb, 156 bytes, Stack size 16 bytes, dnaninf.o(x$fpl$dnaninf), UNUSED) +

    [Called By]

    • >>   _dcmpeq +
    • >>   _dsub +
    • >>   _dadd +
    • >>   _dmul +
    • >>   _dfixu +
    • >>   _ddiv +
    • >>   _d2f +
    + +

    __fpl_dretinf (Thumb, 12 bytes, Stack size 0 bytes, dretinf.o(x$fpl$dretinf), UNUSED) +

    [Called By]

    • >>   _dadd +
    • >>   _f2d +
    • >>   _dmul +
    • >>   _ddiv +
    + +

    __aeabi_drsub (Thumb, 0 bytes, Stack size 8 bytes, daddsub_clz.o(x$fpl$drsb)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_drsub +
    +
    [Called By]
    • >>   __hardfp_atan +
    • >>   __hardfp_atan2 +
    + +

    _drsb (Thumb, 22 bytes, Stack size 8 bytes, daddsub_clz.o(x$fpl$drsb), UNUSED) +

    [Calls]

    • >>   _dsub1 +
    • >>   _dadd1 +
    + +

    __aeabi_dsub (Thumb, 0 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_dsub +
    +
    [Called By]
    • >>   __hardfp_atan +
    • >>   __hardfp_atan2 +
    + +

    _dsub (Thumb, 472 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    • >>   _dadd1 +
    + +

    __aeabi_f2d (Thumb, 0 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_f2d +
    +
    [Called By]
    • >>   AHRS_Init +
    + +

    _f2d (Thumb, 86 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d), UNUSED) +

    [Calls]

    • >>   __fpl_fnaninf +
    • >>   __fpl_dretinf +
    + +

    __aeabi_ul2f (Thumb, 0 bytes, Stack size 0 bytes, ffltll_clz.o(x$fpl$ffltll)) +

    [Called By]

    • >>   Shoot_Control +
    • >>   Gimbal_Control +
    + +

    _ll_uto_f (Thumb, 6 bytes, Stack size 0 bytes, ffltll_clz.o(x$fpl$ffltll), UNUSED) + +

    __aeabi_l2f (Thumb, 0 bytes, Stack size 0 bytes, ffltll_clz.o(x$fpl$ffltll), UNUSED) + +

    _ll_sto_f (Thumb, 90 bytes, Stack size 0 bytes, ffltll_clz.o(x$fpl$ffltll), UNUSED) + +

    __fpl_fnaninf (Thumb, 140 bytes, Stack size 8 bytes, fnaninf.o(x$fpl$fnaninf), UNUSED) +

    [Called By]

    • >>   _f2d +
    + +

    _fp_init (Thumb, 26 bytes, Stack size 0 bytes, fpinit.o(x$fpl$fpinit)) +

    [Called By]

    • >>   __rt_lib_init_fp_1 +
    + +

    __fplib_config_fpu_vfp (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) + +

    __fplib_config_pureend_doubles (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) + +

    __fpl_fretinf (Thumb, 10 bytes, Stack size 0 bytes, fretinf.o(x$fpl$fretinf), UNUSED) +

    [Called By]

    • >>   _d2f +
    +

    +

    +Local Symbols +

    +

    DMA_CalcBaseAndBitshift (Thumb, 52 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift)) +

    [Called By]

    • >>   HAL_DMA_Init +
    + +

    DMA_CheckFifoParam (Thumb, 80 bytes, Stack size 0 bytes, stm32f4xx_hal_dma.o(.text.DMA_CheckFifoParam)) +

    [Called By]

    • >>   HAL_DMA_Init +
    + +

    DMA_SetConfig (Thumb, 48 bytes, Stack size 8 bytes, stm32f4xx_hal_dma.o(.text.DMA_SetConfig)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = DMA_SetConfig +
    +
    [Called By]
    • >>   HAL_DMA_Start_IT +
    + +

    NVIC_EncodePriority (Thumb, 44 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.NVIC_EncodePriority)) +

    [Called By]

    • >>   HAL_NVIC_SetPriority +
    + +

    SysTick_Config (Thumb, 46 bytes, Stack size 16 bytes, stm32f4xx_hal_cortex.o(.text.SysTick_Config)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SysTick_Config +
    +
    [Calls]
    • >>   __NVIC_SetPriority +
    +
    [Called By]
    • >>   HAL_SYSTICK_Config +
    + +

    __NVIC_DisableIRQ (Thumb, 40 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.__NVIC_DisableIRQ)) +

    [Called By]

    • >>   HAL_NVIC_DisableIRQ +
    + +

    __NVIC_EnableIRQ (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.__NVIC_EnableIRQ)) +

    [Called By]

    • >>   HAL_NVIC_EnableIRQ +
    + +

    __NVIC_GetPriorityGrouping (Thumb, 16 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping)) +

    [Called By]

    • >>   HAL_NVIC_SetPriority +
    + +

    __NVIC_SetPriority (Thumb, 34 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority)) +

    [Called By]

    • >>   SysTick_Config +
    • >>   HAL_NVIC_SetPriority +
    + +

    __NVIC_SetPriorityGrouping (Thumb, 32 bytes, Stack size 0 bytes, stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping)) +

    [Called By]

    • >>   HAL_NVIC_SetPriorityGrouping +
    + +

    SPI_DMAError (Thumb, 34 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMAError)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_DMAError ⇒ HAL_SPI_ErrorCallback +
    +
    [Calls]
    • >>   HAL_SPI_ErrorCallback +
    +
    [Address Reference Count : 3]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    +

    SPI_DMAHalfReceiveCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_DMAHalfReceiveCplt ⇒ HAL_SPI_RxHalfCpltCallback +
    +
    [Calls]
    • >>   HAL_SPI_RxHalfCpltCallback +
    +
    [Address Reference Count : 2]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    +

    SPI_DMAHalfTransmitCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_DMAHalfTransmitCplt ⇒ HAL_SPI_TxHalfCpltCallback +
    +
    [Calls]
    • >>   HAL_SPI_TxHalfCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    +

    SPI_DMAHalfTransmitReceiveCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = SPI_DMAHalfTransmitReceiveCplt ⇒ HAL_SPI_TxRxHalfCpltCallback +
    +
    [Calls]
    • >>   HAL_SPI_TxRxHalfCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    +

    SPI_DMAReceiveCplt (Thumb, 104 bytes, Stack size 16 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = SPI_DMAReceiveCplt ⇒ SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   SPI_EndRxTransaction +
    • >>   HAL_SPI_RxCpltCallback +
    • >>   HAL_SPI_ErrorCallback +
    +
    [Address Reference Count : 2]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) +
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    +

    SPI_DMATransmitCplt (Thumb, 112 bytes, Stack size 24 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = SPI_DMATransmitCplt ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   SPI_EndRxTxTransaction +
    • >>   HAL_SPI_TxCpltCallback +
    • >>   HAL_SPI_ErrorCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) +
    +

    SPI_DMATransmitReceiveCplt (Thumb, 90 bytes, Stack size 16 bytes, stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = SPI_DMATransmitReceiveCplt ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   SPI_EndRxTxTransaction +
    • >>   HAL_SPI_TxRxCpltCallback +
    • >>   HAL_SPI_ErrorCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) +
    +

    SPI_EndRxTransaction (Thumb, 144 bytes, Stack size 24 bytes, stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_EndRxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   SPI_WaitFlagStateUntilTimeout +
    +
    [Called By]
    • >>   HAL_SPI_Receive +
    • >>   SPI_DMAReceiveCplt +
    + +

    SPI_EndRxTxTransaction (Thumb, 138 bytes, Stack size 24 bytes, stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   SPI_WaitFlagStateUntilTimeout +
    +
    [Called By]
    • >>   HAL_SPI_TransmitReceive +
    • >>   HAL_SPI_Transmit +
    • >>   SPI_DMATransmitReceiveCplt +
    • >>   SPI_DMATransmitCplt +
    + +

    SPI_WaitFlagStateUntilTimeout (Thumb, 224 bytes, Stack size 40 bytes, stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   HAL_GetTick +
    +
    [Called By]
    • >>   SPI_EndRxTxTransaction +
    • >>   SPI_EndRxTransaction +
    + +

    TIM_OC1_SetConfig (Thumb, 100 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_OC1_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_PWM_ConfigChannel +
    + +

    TIM_OC3_SetConfig (Thumb, 104 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_OC3_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_PWM_ConfigChannel +
    + +

    TIM_OC4_SetConfig (Thumb, 78 bytes, Stack size 16 bytes, stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_OC4_SetConfig +
    +
    [Called By]
    • >>   HAL_TIM_PWM_ConfigChannel +
    + +

    UART_DMAAbortOnError (Thumb, 14 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMAAbortOnError ⇒ HAL_UART_ErrorCallback +
    +
    [Calls]
    • >>   HAL_UART_ErrorCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) +
    +

    UART_DMAError (Thumb, 76 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMAError)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMAError ⇒ HAL_UART_ErrorCallback +
    +
    [Calls]
    • >>   UART_EndTxTransfer +
    • >>   UART_EndRxTransfer +
    • >>   HAL_UART_ErrorCallback +
    +
    [Address Reference Count : 2]
    • stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    • stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    +

    UART_DMAReceiveCplt (Thumb, 132 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMAReceiveCplt ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_UARTEx_RxEventCallback +
    • >>   HAL_UART_RxCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    +

    UART_DMARxHalfCplt (Thumb, 30 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMARxHalfCplt ⇒ HAL_UART_RxHalfCpltCallback +
    +
    [Calls]
    • >>   HAL_UARTEx_RxEventCallback +
    • >>   HAL_UART_RxHalfCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) +
    +

    UART_DMATransmitCplt (Thumb, 64 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMATransmitCplt ⇒ HAL_UART_TxCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_TxCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    +

    UART_DMATxHalfCplt (Thumb, 10 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_DMATxHalfCplt ⇒ HAL_UART_TxHalfCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_TxHalfCpltCallback +
    +
    [Address Reference Count : 1]
    • stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) +
    +

    UART_EndRxTransfer (Thumb, 80 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer)) +

    [Calls]

    • >>   UART_EndRxTransfer +
    +
    [Called By]
    • >>   HAL_UART_IRQHandler +
    • >>   UART_EndRxTransfer +
    • >>   UART_DMAError +
    + +

    UART_EndTransmit_IT (Thumb, 24 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = UART_EndTransmit_IT ⇒ HAL_UART_TxCpltCallback +
    +
    [Calls]
    • >>   HAL_UART_TxCpltCallback +
    +
    [Called By]
    • >>   HAL_UART_IRQHandler +
    + +

    UART_EndTxTransfer (Thumb, 28 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer)) +

    [Calls]

    • >>   UART_EndTxTransfer +
    +
    [Called By]
    • >>   UART_EndTxTransfer +
    • >>   UART_DMAError +
    + +

    UART_Receive_IT (Thumb, 200 bytes, Stack size 16 bytes, stm32f4xx_hal_uart.o(.text.UART_Receive_IT)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = UART_Receive_IT ⇒ HAL_UART_RxCpltCallback +
    +
    [Calls]
    • >>   HAL_UARTEx_RxEventCallback +
    • >>   HAL_UART_RxCpltCallback +
    +
    [Called By]
    • >>   HAL_UART_IRQHandler +
    + +

    UART_SetConfig (Thumb, 220 bytes, Stack size 8 bytes, stm32f4xx_hal_uart.o(.text.UART_SetConfig)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = UART_SetConfig ⇒ __aeabi_uldivmod +
    +
    [Calls]
    • >>   HAL_RCC_GetPCLK2Freq +
    • >>   HAL_RCC_GetPCLK1Freq +
    • >>   __aeabi_uldivmod +
    +
    [Called By]
    • >>   HAL_UART_Init +
    + +

    UART_Transmit_IT (Thumb, 82 bytes, Stack size 0 bytes, stm32f4xx_hal_uart.o(.text.UART_Transmit_IT)) +

    [Called By]

    • >>   HAL_UART_IRQHandler +
    + +

    prvCopyDataFromQueue (Thumb, 38 bytes, Stack size 8 bytes, queue.o(.text.prvCopyDataFromQueue)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = prvCopyDataFromQueue +
    +
    [Calls]
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   xQueueReceiveFromISR +
    • >>   xQueueReceive +
    + +

    prvCopyDataToQueue (Thumb, 122 bytes, Stack size 16 bytes, queue.o(.text.prvCopyDataToQueue)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = prvCopyDataToQueue ⇒ xTaskPriorityDisinherit +
    +
    [Calls]
    • >>   xTaskPriorityDisinherit +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   xQueueGenericSendFromISR +
    • >>   xQueueGenericSend +
    + +

    prvGetDisinheritPriorityAfterTimeout (Thumb, 18 bytes, Stack size 0 bytes, queue.o(.text.prvGetDisinheritPriorityAfterTimeout)) +

    [Called By]

    • >>   xQueueSemaphoreTake +
    + +

    prvInitialiseMutex (Thumb, 32 bytes, Stack size 8 bytes, queue.o(.text.prvInitialiseMutex)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = prvInitialiseMutex ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xQueueGenericSend +
    +
    [Called By]
    • >>   xQueueCreateMutexStatic +
    • >>   xQueueCreateMutex +
    + +

    prvInitialiseNewQueue (Thumb, 32 bytes, Stack size 16 bytes, queue.o(.text.prvInitialiseNewQueue)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xQueueGenericReset +
    +
    [Called By]
    • >>   xQueueGenericCreateStatic +
    • >>   xQueueGenericCreate +
    + +

    prvIsQueueEmpty (Thumb, 24 bytes, Stack size 8 bytes, queue.o(.text.prvIsQueueEmpty)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = prvIsQueueEmpty +
    +
    [Calls]
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    + +

    prvIsQueueFull (Thumb, 28 bytes, Stack size 8 bytes, queue.o(.text.prvIsQueueFull)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = prvIsQueueFull +
    +
    [Calls]
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueGenericSend +
    + +

    prvUnlockQueue (Thumb, 114 bytes, Stack size 24 bytes, queue.o(.text.prvUnlockQueue)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = prvUnlockQueue ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xTaskRemoveFromEventList +
    • >>   vTaskMissedYield +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xQueueSemaphoreTake +
    • >>   xQueueReceive +
    • >>   xQueueGenericSend +
    • >>   vQueueWaitForMessageRestricted +
    + +

    prvAddCurrentTaskToDelayedList (Thumb, 128 bytes, Stack size 24 bytes, tasks.o(.text.prvAddCurrentTaskToDelayedList)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = prvAddCurrentTaskToDelayedList ⇒ vListInsert +
    +
    [Calls]
    • >>   vListInsertEnd +
    • >>   vListInsert +
    • >>   uxListRemove +
    +
    [Called By]
    • >>   vTaskDelayUntil +
    • >>   vTaskDelay +
    • >>   xTaskNotifyWait +
    • >>   vTaskPlaceOnEventListRestricted +
    • >>   vTaskPlaceOnEventList +
    + +

    prvAddNewTaskToReadyList (Thumb, 172 bytes, Stack size 16 bytes, tasks.o(.text.prvAddNewTaskToReadyList)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = prvAddNewTaskToReadyList ⇒ prvInitialiseTaskLists +
    +
    [Calls]
    • >>   prvInitialiseTaskLists +
    • >>   vListInsertEnd +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   xTaskCreateStatic +
    • >>   xTaskCreate +
    + +

    prvCheckTasksWaitingTermination (Thumb, 78 bytes, Stack size 24 bytes, tasks.o(.text.prvCheckTasksWaitingTermination)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = prvCheckTasksWaitingTermination ⇒ prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvDeleteTCB +
    • >>   uxListRemove +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    +
    [Called By]
    • >>   prvIdleTask +
    + +

    prvDeleteTCB (Thumb, 54 bytes, Stack size 8 bytes, tasks.o(.text.prvDeleteTCB)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   vPortFree +
    +
    [Called By]
    • >>   vTaskDelete +
    • >>   prvCheckTasksWaitingTermination +
    + +

    prvIdleTask (Thumb, 42 bytes, Stack size 0 bytes, tasks.o(.text.prvIdleTask)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = prvIdleTask ⇒ prvCheckTasksWaitingTermination ⇒ prvDeleteTCB ⇒ vPortFree ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvCheckTasksWaitingTermination +
    +
    [Address Reference Count : 1]
    • tasks.o(.text.vTaskStartScheduler) +
    +

    prvInitialiseNewTask (Thumb, 152 bytes, Stack size 32 bytes, tasks.o(.text.prvInitialiseNewTask)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = prvInitialiseNewTask ⇒ __aeabi_memset4 ⇒ _memset_w +
    +
    [Calls]
    • >>   pxPortInitialiseStack +
    • >>   vListInitialiseItem +
    • >>   __aeabi_memset4 +
    +
    [Called By]
    • >>   xTaskCreateStatic +
    • >>   xTaskCreate +
    + +

    prvInitialiseTaskLists (Thumb, 112 bytes, Stack size 16 bytes, tasks.o(.text.prvInitialiseTaskLists)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = prvInitialiseTaskLists +
    +
    [Calls]
    • >>   vListInitialise +
    +
    [Called By]
    • >>   prvAddNewTaskToReadyList +
    + +

    prvResetNextTaskUnblockTime (Thumb, 40 bytes, Stack size 0 bytes, tasks.o(.text.prvResetNextTaskUnblockTime)) +

    [Called By]

    • >>   xTaskIncrementTick +
    • >>   vTaskDelete +
    • >>   xTaskResumeAll +
    + +

    prvCheckForValidListAndQueue (Thumb, 116 bytes, Stack size 24 bytes, timers.o(.text.prvCheckForValidListAndQueue)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = prvCheckForValidListAndQueue ⇒ xQueueGenericCreateStatic ⇒ prvInitialiseNewQueue ⇒ xQueueGenericReset ⇒ xTaskRemoveFromEventList +
    +
    [Calls]
    • >>   xQueueGenericCreateStatic +
    • >>   vQueueAddToRegistry +
    • >>   vPortExitCritical +
    • >>   vPortEnterCritical +
    • >>   vListInitialise +
    +
    [Called By]
    • >>   xTimerCreateTimerTask +
    + +

    prvGetNextExpireTime (Thumb, 32 bytes, Stack size 0 bytes, timers.o(.text.prvGetNextExpireTime)) +

    [Called By]

    • >>   prvTimerTask +
    + +

    prvInsertTimerInActiveList (Thumb, 64 bytes, Stack size 8 bytes, timers.o(.text.prvInsertTimerInActiveList)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = prvInsertTimerInActiveList ⇒ vListInsert +
    +
    [Calls]
    • >>   vListInsert +
    +
    [Called By]
    • >>   prvProcessReceivedCommands +
    • >>   prvProcessExpiredTimer +
    + +

    prvProcessExpiredTimer (Thumb, 110 bytes, Stack size 24 bytes, timers.o(.text.prvProcessExpiredTimer)) +

    [Stack]

    • Max Depth = 176
    • Call Chain = prvProcessExpiredTimer ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvInsertTimerInActiveList +
    • >>   uxListRemove +
    • >>   xTimerGenericCommand +
    +
    [Called By]
    • >>   prvProcessTimerOrBlockTask +
    + +

    prvProcessReceivedCommands (Thumb, 290 bytes, Stack size 48 bytes, timers.o(.text.prvProcessReceivedCommands)) +

    [Stack]

    • Max Depth = 248
    • Call Chain = prvProcessReceivedCommands ⇒ prvSampleTimeNow ⇒ prvSwitchTimerLists ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvSampleTimeNow +
    • >>   prvInsertTimerInActiveList +
    • >>   xQueueReceive +
    • >>   uxListRemove +
    • >>   vPortFree +
    • >>   xTimerGenericCommand +
    +
    [Called By]
    • >>   prvTimerTask +
    + +

    prvProcessTimerOrBlockTask (Thumb, 128 bytes, Stack size 24 bytes, timers.o(.text.prvProcessTimerOrBlockTask)) +

    [Stack]

    • Max Depth = 224
    • Call Chain = prvProcessTimerOrBlockTask ⇒ prvSampleTimeNow ⇒ prvSwitchTimerLists ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvSampleTimeNow +
    • >>   prvProcessExpiredTimer +
    • >>   vQueueWaitForMessageRestricted +
    • >>   xTaskResumeAll +
    • >>   vTaskSuspendAll +
    +
    [Called By]
    • >>   prvTimerTask +
    + +

    prvSampleTimeNow (Thumb, 42 bytes, Stack size 16 bytes, timers.o(.text.prvSampleTimeNow)) +

    [Stack]

    • Max Depth = 200
    • Call Chain = prvSampleTimeNow ⇒ prvSwitchTimerLists ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   xTaskGetTickCount +
    • >>   prvSwitchTimerLists +
    +
    [Called By]
    • >>   prvProcessTimerOrBlockTask +
    • >>   prvProcessReceivedCommands +
    + +

    prvSwitchTimerLists (Thumb, 142 bytes, Stack size 32 bytes, timers.o(.text.prvSwitchTimerLists)) +

    [Stack]

    • Max Depth = 184
    • Call Chain = prvSwitchTimerLists ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   vListInsert +
    • >>   uxListRemove +
    • >>   xTimerGenericCommand +
    +
    [Called By]
    • >>   prvSampleTimeNow +
    + +

    prvTimerTask (Thumb, 22 bytes, Stack size 8 bytes, timers.o(.text.prvTimerTask)) +

    [Stack]

    • Max Depth = 256
    • Call Chain = prvTimerTask ⇒ prvProcessReceivedCommands ⇒ prvSampleTimeNow ⇒ prvSwitchTimerLists ⇒ xTimerGenericCommand ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   prvProcessTimerOrBlockTask +
    • >>   prvProcessReceivedCommands +
    • >>   prvGetNextExpireTime +
    +
    [Address Reference Count : 1]
    • timers.o(.text.xTimerCreateTimerTask) +
    +

    SVC_Setup (Thumb, 8 bytes, Stack size 8 bytes, cmsis_os2.o(.text.SVC_Setup)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SVC_Setup +
    +
    [Calls]
    • >>   __NVIC_SetPriority +
    +
    [Called By]
    • >>   osKernelStart +
    + +

    __NVIC_SetPriority (Thumb, 14 bytes, Stack size 0 bytes, cmsis_os2.o(.text.__NVIC_SetPriority)) +

    [Called By]

    • >>   SVC_Setup +
    + +

    prvHeapInit (Thumb, 120 bytes, Stack size 0 bytes, heap_4.o(.text.prvHeapInit)) +

    [Called By]

    • >>   pvPortMalloc +
    + +

    prvInsertBlockIntoFreeList (Thumb, 90 bytes, Stack size 8 bytes, heap_4.o(.text.prvInsertBlockIntoFreeList)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = prvInsertBlockIntoFreeList +
    +
    [Called By]
    • >>   vPortFree +
    • >>   pvPortMalloc +
    + +

    prvPortStartFirstTask (Thumb, 34 bytes, Stack size 0 bytes, port.o(.text.prvPortStartFirstTask)) +

    [Called By]

    • >>   xPortStartScheduler +
    + +

    prvTaskExitError (Thumb, 50 bytes, Stack size 4 bytes, port.o(.text.prvTaskExitError)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = prvTaskExitError +
    +
    [Called By]
    • >>   xPortStartScheduler +
    +
    [Address Reference Count : 1]
    • port.o(.text.pxPortInitialiseStack) +
    +

    vPortEnableVFP (Thumb, 14 bytes, Stack size 0 bytes, port.o(.text.vPortEnableVFP)) +

    [Called By]

    • >>   xPortStartScheduler +
    + +

    BSP_CAN_CreateIdQueue (Thumb, 146 bytes, Stack size 32 bytes, can_1.o(.text.BSP_CAN_CreateIdQueue)) +

    [Stack]

    • Max Depth = 192
    • Call Chain = BSP_CAN_CreateIdQueue ⇒ osMutexAcquire ⇒ xQueueTakeMutexRecursive ⇒ xQueueSemaphoreTake ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_Malloc +
    • >>   BSP_Free +
    • >>   osMutexRelease +
    • >>   osMutexAcquire +
    • >>   osMessageQueueNew +
    +
    [Called By]
    • >>   BSP_CAN_RegisterId +
    + +

    BSP_CAN_DefaultIdParser (Thumb, 2 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_DefaultIdParser)) +
    [Address Reference Count : 1]

    • can_1.o(.text.BSP_CAN_Init) +
    +

    BSP_CAN_FindQueue (Thumb, 38 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_FindQueue)) +

    [Called By]

    • >>   BSP_CAN_GetMessage +
    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    BSP_CAN_GetFrameType (Thumb, 26 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_GetFrameType)) +

    [Called By]

    • >>   BSP_CAN_RxFifo1Callback +
    • >>   BSP_CAN_RxFifo0Callback +
    + +

    BSP_CAN_RxFifo0Callback (Thumb, 194 bytes, Stack size 112 bytes, can_1.o(.text.BSP_CAN_RxFifo0Callback)) +

    [Stack]

    • Max Depth = 264
    • Call Chain = BSP_CAN_RxFifo0Callback ⇒ osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   HAL_CAN_GetRxMessage +
    • >>   HAL_CAN_GetRxFifoFillLevel +
    • >>   BSP_CAN_ParseId +
    • >>   BSP_CAN_GetHandle +
    • >>   BSP_CAN_GetFrameType +
    • >>   BSP_CAN_FindQueue +
    • >>   osMessageQueuePut +
    • >>   __aeabi_memcpy +
    +
    [Address Reference Count : 1]
    • can_1.o(.text.BSP_CAN_Init) +
    +

    BSP_CAN_RxFifo1Callback (Thumb, 194 bytes, Stack size 112 bytes, can_1.o(.text.BSP_CAN_RxFifo1Callback)) +

    [Stack]

    • Max Depth = 264
    • Call Chain = BSP_CAN_RxFifo1Callback ⇒ osMessageQueuePut ⇒ xQueueGenericSend ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   HAL_GetTick +
    • >>   HAL_CAN_GetRxMessage +
    • >>   HAL_CAN_GetRxFifoFillLevel +
    • >>   BSP_CAN_ParseId +
    • >>   BSP_CAN_GetHandle +
    • >>   BSP_CAN_GetFrameType +
    • >>   BSP_CAN_FindQueue +
    • >>   osMessageQueuePut +
    • >>   __aeabi_memcpy +
    +
    [Address Reference Count : 1]
    • can_1.o(.text.BSP_CAN_Init) +
    +

    BSP_CAN_TxCompleteCallback (Thumb, 100 bytes, Stack size 64 bytes, can_1.o(.text.BSP_CAN_TxCompleteCallback)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = BSP_CAN_TxCompleteCallback ⇒ BSP_CAN_TxQueuePop +
    +
    [Calls]
    • >>   HAL_CAN_GetTxMailboxesFreeLevel +
    • >>   HAL_CAN_AddTxMessage +
    • >>   BSP_CAN_GetHandle +
    • >>   BSP_CAN_TxQueuePop +
    • >>   BSP_CAN_TxQueueIsEmpty +
    +
    [Address Reference Count : 1]
    • can_1.o(.text.BSP_CAN_Init) +
    +

    BSP_CAN_TxQueueInit (Thumb, 28 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_TxQueueInit)) +

    [Called By]

    • >>   BSP_CAN_Init +
    + +

    BSP_CAN_TxQueueIsEmpty (Thumb, 34 bytes, Stack size 0 bytes, can_1.o(.text.BSP_CAN_TxQueueIsEmpty)) +

    [Called By]

    • >>   BSP_CAN_TxCompleteCallback +
    + +

    BSP_CAN_TxQueuePop (Thumb, 116 bytes, Stack size 24 bytes, can_1.o(.text.BSP_CAN_TxQueuePop)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = BSP_CAN_TxQueuePop +
    +
    [Called By]
    • >>   BSP_CAN_TxCompleteCallback +
    + +

    BSP_CAN_TxQueuePush (Thumb, 126 bytes, Stack size 32 bytes, can_1.o(.text.BSP_CAN_TxQueuePush)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = BSP_CAN_TxQueuePush +
    +
    [Called By]
    • >>   BSP_CAN_Transmit +
    + +

    CAN_Get (Thumb, 36 bytes, Stack size 0 bytes, can_1.o(.text.CAN_Get)) +

    [Called By]

    • >>   HAL_CAN_WakeUpFromRxMsgCallback +
    • >>   HAL_CAN_TxMailbox2CompleteCallback +
    • >>   HAL_CAN_TxMailbox2AbortCallback +
    • >>   HAL_CAN_TxMailbox1CompleteCallback +
    • >>   HAL_CAN_TxMailbox1AbortCallback +
    • >>   HAL_CAN_TxMailbox0CompleteCallback +
    • >>   HAL_CAN_TxMailbox0AbortCallback +
    • >>   HAL_CAN_SleepCallback +
    • >>   HAL_CAN_RxFifo1MsgPendingCallback +
    • >>   HAL_CAN_RxFifo1FullCallback +
    • >>   HAL_CAN_RxFifo0MsgPendingCallback +
    • >>   HAL_CAN_RxFifo0FullCallback +
    • >>   HAL_CAN_ErrorCallback +
    + +

    SPI_Get (Thumb, 20 bytes, Stack size 0 bytes, spi_1.o(.text.SPI_Get)) +

    [Called By]

    • >>   HAL_SPI_TxRxHalfCpltCallback +
    • >>   HAL_SPI_TxRxCpltCallback +
    • >>   HAL_SPI_TxHalfCpltCallback +
    • >>   HAL_SPI_TxCpltCallback +
    • >>   HAL_SPI_RxHalfCpltCallback +
    • >>   HAL_SPI_RxCpltCallback +
    • >>   HAL_SPI_ErrorCallback +
    + +

    UART_Get (Thumb, 52 bytes, Stack size 0 bytes, uart.o(.text.UART_Get)) +

    [Called By]

    • >>   BSP_UART_IRQHandler +
    • >>   HAL_UART_TxHalfCpltCallback +
    • >>   HAL_UART_TxCpltCallback +
    • >>   HAL_UART_RxHalfCpltCallback +
    • >>   HAL_UART_RxCpltCallback +
    • >>   HAL_UART_ErrorCallback +
    + +

    AHRS_UpdateIMU (Thumb, 752 bytes, Stack size 80 bytes, ahrs.o(.text.AHRS_UpdateIMU)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = AHRS_UpdateIMU +
    +
    [Calls]
    • >>   InvSqrt +
    +
    [Called By]
    • >>   AHRS_Update +
    + +

    copysignf (Thumb, 22 bytes, Stack size 0 bytes, ahrs.o(.text.copysignf)) +

    [Called By]

    • >>   AHRS_GetEulr +
    + +

    CRC16_Byte (Thumb, 22 bytes, Stack size 0 bytes, crc16.o(.text.CRC16_Byte)) +

    [Called By]

    • >>   CRC16_Calc +
    + +

    __ARM_isfinitef (Thumb, 14 bytes, Stack size 0 bytes, filter.o(.text.__ARM_isfinitef)) +

    [Called By]

    • >>   LowPassFilter2p_Reset +
    + +

    __ARM_isinff (Thumb, 16 bytes, Stack size 0 bytes, filter.o(.text.__ARM_isinff)) +

    [Called By]

    • >>   LowPassFilter2p_Apply +
    + +

    __ARM_isfinitef (Thumb, 14 bytes, Stack size 0 bytes, pid.o(.text.__ARM_isfinitef)) +

    [Called By]

    • >>   PID_Init +
    • >>   PID_Calc +
    + +

    BMI088_AcclIntCallback (Thumb, 20 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_AcclIntCallback)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = BMI088_AcclIntCallback ⇒ osThreadFlagsSet ⇒ xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   osThreadFlagsSet +
    +
    [Address Reference Count : 1]
    • bmi088.o(.text.BMI088_Init) +
    +

    BMI088_GyroIntCallback (Thumb, 20 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_GyroIntCallback)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = BMI088_GyroIntCallback ⇒ osThreadFlagsSet ⇒ xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   osThreadFlagsSet +
    +
    [Address Reference Count : 1]
    • bmi088.o(.text.BMI088_Init) +
    +

    BMI088_RxCpltCallback (Thumb, 64 bytes, Stack size 8 bytes, bmi088.o(.text.BMI088_RxCpltCallback)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = BMI088_RxCpltCallback ⇒ osThreadFlagsSet ⇒ xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   BSP_GPIO_WritePin +
    • >>   BSP_GPIO_ReadPin +
    • >>   osThreadFlagsSet +
    +
    [Address Reference Count : 1]
    • bmi088.o(.text.BMI088_Init) +
    +

    BMI_Read (Thumb, 68 bytes, Stack size 16 bytes, bmi088.o(.text.BMI_Read)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = BMI_Read ⇒ BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   BSP_SPI_Transmit +
    • >>   BSP_SPI_Receive +
    • >>   BSP_GPIO_WritePin +
    +
    [Called By]
    • >>   BMI088_GyroStartDmaRecv +
    • >>   BMI088_AcclStartDmaRecv +
    + +

    BMI_ReadSingle (Thumb, 94 bytes, Stack size 16 bytes, bmi088.o(.text.BMI_ReadSingle)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = BMI_ReadSingle ⇒ BSP_SPI_Receive ⇒ HAL_SPI_Receive ⇒ HAL_SPI_TransmitReceive ⇒ SPI_EndRxTxTransaction ⇒ SPI_WaitFlagStateUntilTimeout +
    +
    [Calls]
    • >>   BSP_TIME_Delay +
    • >>   BSP_SPI_Transmit +
    • >>   BSP_SPI_Receive +
    • >>   BSP_GPIO_WritePin +
    +
    [Called By]
    • >>   BMI088_Init +
    + +

    BMI_WriteSingle (Thumb, 72 bytes, Stack size 8 bytes, bmi088.o(.text.BMI_WriteSingle)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = BMI_WriteSingle ⇒ BSP_TIME_Delay ⇒ osDelay ⇒ vTaskDelay ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_TIME_Delay +
    • >>   BSP_SPI_Transmit +
    • >>   BSP_GPIO_WritePin +
    +
    [Called By]
    • >>   BMI088_Init +
    + +

    MOTOR_RM_CreateCANManager (Thumb, 60 bytes, Stack size 16 bytes, motor_rm.o(.text.MOTOR_RM_CreateCANManager)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = MOTOR_RM_CreateCANManager ⇒ BSP_Malloc ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_Malloc +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   MOTOR_RM_Register +
    + +

    MOTOR_RM_GetCANManager (Thumb, 20 bytes, Stack size 0 bytes, motor_rm.o(.text.MOTOR_RM_GetCANManager)) +

    [Called By]

    • >>   MOTOR_RM_Update +
    • >>   MOTOR_RM_SetOutput +
    • >>   MOTOR_RM_Register +
    • >>   MOTOR_RM_GetMotor +
    • >>   MOTOR_RM_Ctrl +
    + +

    MOTOR_RM_GetLSB (Thumb, 38 bytes, Stack size 0 bytes, motor_rm.o(.text.MOTOR_RM_GetLSB)) +

    [Called By]

    • >>   Motor_RM_Decode +
    • >>   MOTOR_RM_SetOutput +
    + +

    MOTOR_RM_GetLogicalIndex (Thumb, 40 bytes, Stack size 0 bytes, motor_rm.o(.text.MOTOR_RM_GetLogicalIndex)) +

    [Called By]

    • >>   MOTOR_RM_SetOutput +
    + +

    MOTOR_RM_GetRatio (Thumb, 36 bytes, Stack size 0 bytes, motor_rm.o(.text.MOTOR_RM_GetRatio)) +

    [Called By]

    • >>   Motor_RM_Decode +
    + +

    Motor_RM_Decode (Thumb, 348 bytes, Stack size 32 bytes, motor_rm.o(.text.Motor_RM_Decode)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Motor_RM_Decode +
    +
    [Calls]
    • >>   MOTOR_RM_GetRatio +
    • >>   MOTOR_RM_GetLSB +
    +
    [Called By]
    • >>   MOTOR_RM_Update +
    + +

    MOTOR_DM_CreateCANManager (Thumb, 60 bytes, Stack size 16 bytes, motor_dm.o(.text.MOTOR_DM_CreateCANManager)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = MOTOR_DM_CreateCANManager ⇒ BSP_Malloc ⇒ pvPortMalloc ⇒ xTaskResumeAll ⇒ xTaskIncrementTick +
    +
    [Calls]
    • >>   BSP_Malloc +
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   MOTOR_DM_Register +
    + +

    MOTOR_DM_GetCANManager (Thumb, 20 bytes, Stack size 0 bytes, motor_dm.o(.text.MOTOR_DM_GetCANManager)) +

    [Called By]

    • >>   MOTOR_DM_Update +
    • >>   MOTOR_DM_Register +
    • >>   MOTOR_DM_GetMotor +
    + +

    MOTOR_DM_ParseFeedbackFrame (Thumb, 248 bytes, Stack size 24 bytes, motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = MOTOR_DM_ParseFeedbackFrame +
    +
    [Calls]
    • >>   uint_to_float +
    +
    [Called By]
    • >>   MOTOR_DM_Update +
    + +

    MOTOR_DM_SendMITCmd (Thumb, 280 bytes, Stack size 64 bytes, motor_dm.o(.text.MOTOR_DM_SendMITCmd)) +

    [Stack]

    • Max Depth = 176
    • Call Chain = MOTOR_DM_SendMITCmd ⇒ BSP_CAN_TransmitStdDataFrame ⇒ BSP_CAN_Transmit ⇒ BSP_CAN_TxQueuePush +
    +
    [Calls]
    • >>   BSP_CAN_TransmitStdDataFrame +
    • >>   float_to_uint +
    +
    [Called By]
    • >>   MOTOR_DM_MITCtrl +
    + +

    float_to_uint (Thumb, 44 bytes, Stack size 0 bytes, motor_dm.o(.text.float_to_uint)) +

    [Called By]

    • >>   MOTOR_DM_SendMITCmd +
    + +

    uint_to_float (Thumb, 42 bytes, Stack size 0 bytes, motor_dm.o(.text.uint_to_float)) +

    [Called By]

    • >>   MOTOR_DM_ParseFeedbackFrame +
    + +

    DR16_DataCorrupted (Thumb, 110 bytes, Stack size 0 bytes, dr16.o(.text.DR16_DataCorrupted)) +

    [Called By]

    • >>   DR16_ParseData +
    + +

    DR16_RxCpltCallback (Thumb, 20 bytes, Stack size 8 bytes, dr16.o(.text.DR16_RxCpltCallback)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = DR16_RxCpltCallback ⇒ osThreadFlagsSet ⇒ xTaskGenericNotifyFromISR +
    +
    [Calls]
    • >>   osThreadFlagsSet +
    +
    [Address Reference Count : 1]
    • dr16.o(.text.DR16_Init) +
    +

    Gimbal_Direction (Thumb, 164 bytes, Stack size 0 bytes, gimbal.o(.text.Gimbal_Direction)) +

    [Called By]

    • >>   Gimbal_UpdateIMU +
    + +

    Gimbal_SetMode (Thumb, 136 bytes, Stack size 24 bytes, gimbal.o(.text.Gimbal_SetMode)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = Gimbal_SetMode ⇒ PID_Reset ⇒ LowPassFilter2p_Reset ⇒ LowPassFilter2p_Apply +
    +
    [Calls]
    • >>   PID_Reset +
    • >>   LowPassFilter2p_Reset +
    • >>   AHRS_ResetEulr +
    +
    [Called By]
    • >>   Gimbal_Control +
    + +

    motor_imu_offset (Thumb, 68 bytes, Stack size 0 bytes, gimbal.o(.text.motor_imu_offset)) +

    [Called By]

    • >>   Gimbal_Control +
    + +

    Shoot_CaluCoupledWeight (Thumb, 124 bytes, Stack size 0 bytes, shoot.o(.text.Shoot_CaluCoupledWeight)) +

    [Called By]

    • >>   Shoot_RunningFSM +
    + +

    _dadd1 (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +

    [Called By]

    • >>   _dsub +
    • >>   _drsb +
    + +

    _dsub1 (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +

    [Called By]

    • >>   _drsb +
    • >>   _dadd +
    +

    +

    +Undefined Global Symbols +

    diff --git a/MDK-ARM/Infantry/Infantry.lnp b/MDK-ARM/Infantry/Infantry.lnp new file mode 100644 index 0000000..3600575 --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.lnp @@ -0,0 +1,90 @@ +--cpu=Cortex-M4.fp.sp +"infantry\startup_stm32f407xx.o" +"infantry\main.o" +"infantry\gpio.o" +"infantry\freertos.o" +"infantry\can.o" +"infantry\dma.o" +"infantry\i2c.o" +"infantry\spi.o" +"infantry\tim.o" +"infantry\usart.o" +"infantry\stm32f4xx_it.o" +"infantry\stm32f4xx_hal_msp.o" +"infantry\stm32f4xx_hal_can.o" +"infantry\stm32f4xx_hal_rcc.o" +"infantry\stm32f4xx_hal_rcc_ex.o" +"infantry\stm32f4xx_hal_flash.o" +"infantry\stm32f4xx_hal_flash_ex.o" +"infantry\stm32f4xx_hal_flash_ramfunc.o" +"infantry\stm32f4xx_hal_gpio.o" +"infantry\stm32f4xx_hal_dma_ex.o" +"infantry\stm32f4xx_hal_dma.o" +"infantry\stm32f4xx_hal_pwr.o" +"infantry\stm32f4xx_hal_pwr_ex.o" +"infantry\stm32f4xx_hal_cortex.o" +"infantry\stm32f4xx_hal.o" +"infantry\stm32f4xx_hal_exti.o" +"infantry\stm32f4xx_hal_i2c.o" +"infantry\stm32f4xx_hal_i2c_ex.o" +"infantry\stm32f4xx_hal_spi.o" +"infantry\stm32f4xx_hal_tim.o" +"infantry\stm32f4xx_hal_tim_ex.o" +"infantry\stm32f4xx_hal_uart.o" +"infantry\system_stm32f4xx.o" +"infantry\croutine.o" +"infantry\event_groups.o" +"infantry\list.o" +"infantry\queue.o" +"infantry\stream_buffer.o" +"infantry\tasks.o" +"infantry\timers.o" +"infantry\cmsis_os2.o" +"infantry\heap_4.o" +"infantry\port.o" +"infantry\can_1.o" +"infantry\gpio_1.o" +"infantry\i2c_1.o" +"infantry\mm.o" +"infantry\spi_1.o" +"infantry\uart.o" +"infantry\time.o" +"infantry\pwm.o" +"infantry\ahrs.o" +"infantry\capacity.o" +"infantry\crc8.o" +"infantry\crc16.o" +"infantry\error_detect.o" +"infantry\filter.o" +"infantry\freertos_cli.o" +"infantry\limiter.o" +"infantry\mixer.o" +"infantry\pid.o" +"infantry\ui.o" +"infantry\user_math.o" +"infantry\cmd.o" +"infantry\bmi088.o" +"infantry\ist8310.o" +"infantry\motor.o" +"infantry\motor_rm.o" +"infantry\motor_dm.o" +"infantry\ai.o" +"infantry\dr16.o" +"infantry\init.o" +"infantry\ai_1.o" +"infantry\atti_esti.o" +"infantry\chassis_ctrl.o" +"infantry\dr16_1.o" +"infantry\gimbal_ctrl.o" +"infantry\shoot_ctrl.o" +"infantry\user_task.o" +"infantry\remote.o" +"infantry\config.o" +"infantry\chassis.o" +"infantry\gimbal.o" +"infantry\remote_cmd.o" +"infantry\shoot.o" +--strict --scatter "Infantry\Infantry.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list "Infantry.map" -o Infantry\Infantry.axf \ No newline at end of file diff --git a/MDK-ARM/Infantry/Infantry.map b/MDK-ARM/Infantry/Infantry.map new file mode 100644 index 0000000..33aec84 --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.map @@ -0,0 +1,8735 @@ +Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] + +============================================================================== + +Section Cross References + + startup_stm32f407xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f407xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f407xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f407xx.o(RESET) refers to startup_stm32f407xx.o(STACK) for __initial_sp + startup_stm32f407xx.o(RESET) refers to startup_stm32f407xx.o(.text) for Reset_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.NMI_Handler) for NMI_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.HardFault_Handler) for HardFault_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.MemManage_Handler) for MemManage_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.BusFault_Handler) for BusFault_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.UsageFault_Handler) for UsageFault_Handler + startup_stm32f407xx.o(RESET) refers to port.o(.text.SVC_Handler) for SVC_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.DebugMon_Handler) for DebugMon_Handler + startup_stm32f407xx.o(RESET) refers to port.o(.text.PendSV_Handler) for PendSV_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.SysTick_Handler) for SysTick_Handler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.EXTI0_IRQHandler) for EXTI0_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.EXTI3_IRQHandler) for EXTI3_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.EXTI4_IRQHandler) for EXTI4_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) for DMA1_Stream1_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) for CAN1_TX_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) for CAN1_RX0_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) for CAN1_RX1_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) for CAN1_SCE_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) for EXTI9_5_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.USART2_IRQHandler) for USART2_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) for DMA2_Stream2_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) for DMA2_Stream3_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) for CAN2_TX_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) for CAN2_RX1_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) for CAN2_SCE_IRQHandler + startup_stm32f407xx.o(RESET) refers to stm32f4xx_it.o(.text.USART6_IRQHandler) for USART6_IRQHandler + startup_stm32f407xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f407xx.o(.text) refers to system_stm32f4xx.o(.text.SystemInit) for SystemInit + startup_stm32f407xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f407xx.o(.text) refers to startup_stm32f407xx.o(HEAP) for Heap_Mem + startup_stm32f407xx.o(.text) refers to startup_stm32f407xx.o(STACK) for Stack_Mem + main.o(.text.main) refers to stm32f4xx_hal.o(.text.HAL_Init) for HAL_Init + main.o(.text.main) refers to main.o(.text.SystemClock_Config) for SystemClock_Config + main.o(.text.main) refers to gpio.o(.text.MX_GPIO_Init) for MX_GPIO_Init + main.o(.text.main) refers to dma.o(.text.MX_DMA_Init) for MX_DMA_Init + main.o(.text.main) refers to can.o(.text.MX_CAN1_Init) for MX_CAN1_Init + main.o(.text.main) refers to can.o(.text.MX_CAN2_Init) for MX_CAN2_Init + main.o(.text.main) refers to spi.o(.text.MX_SPI1_Init) for MX_SPI1_Init + main.o(.text.main) refers to usart.o(.text.MX_USART1_UART_Init) for MX_USART1_UART_Init + main.o(.text.main) refers to usart.o(.text.MX_USART2_UART_Init) for MX_USART2_UART_Init + main.o(.text.main) refers to usart.o(.text.MX_USART3_UART_Init) for MX_USART3_UART_Init + main.o(.text.main) refers to i2c.o(.text.MX_I2C2_Init) for MX_I2C2_Init + main.o(.text.main) refers to usart.o(.text.MX_USART6_UART_Init) for MX_USART6_UART_Init + main.o(.text.main) refers to tim.o(.text.MX_TIM10_Init) for MX_TIM10_Init + main.o(.text.main) refers to cmsis_os2.o(.text.osKernelInitialize) for osKernelInitialize + main.o(.text.main) refers to freertos.o(.text.MX_FREERTOS_Init) for MX_FREERTOS_Init + main.o(.text.main) refers to cmsis_os2.o(.text.osKernelStart) for osKernelStart + main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol] + main.o(.text.SystemClock_Config) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + main.o(.text.SystemClock_Config) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for HAL_RCC_OscConfig + main.o(.text.SystemClock_Config) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for HAL_RCC_ClockConfig + main.o(.text.SystemClock_Config) refers to main.o(.text.Error_Handler) for Error_Handler + main.o(.ARM.exidx.text.SystemClock_Config) refers to main.o(.text.SystemClock_Config) for [Anonymous Symbol] + main.o(.ARM.exidx.text.Error_Handler) refers to main.o(.text.Error_Handler) for [Anonymous Symbol] + gpio.o(.text.MX_GPIO_Init) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin + gpio.o(.text.MX_GPIO_Init) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + gpio.o(.text.MX_GPIO_Init) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + gpio.o(.text.MX_GPIO_Init) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + gpio.o(.ARM.exidx.text.MX_GPIO_Init) refers to gpio.o(.text.MX_GPIO_Init) for [Anonymous Symbol] + freertos.o(.text.MX_FREERTOS_Init) refers to freertos.o(.text.StartDefaultTask) for StartDefaultTask + freertos.o(.text.MX_FREERTOS_Init) refers to freertos.o(.rodata.defaultTask_attributes) for defaultTask_attributes + freertos.o(.text.MX_FREERTOS_Init) refers to cmsis_os2.o(.text.osThreadNew) for osThreadNew + freertos.o(.text.MX_FREERTOS_Init) refers to freertos.o(.bss.defaultTaskHandle) for defaultTaskHandle + freertos.o(.text.MX_FREERTOS_Init) refers to init.o(.text.Task_Init) for Task_Init + freertos.o(.text.MX_FREERTOS_Init) refers to user_task.o(.rodata.attr_init) for attr_init + freertos.o(.ARM.exidx.text.MX_FREERTOS_Init) refers to freertos.o(.text.MX_FREERTOS_Init) for [Anonymous Symbol] + freertos.o(.text.StartDefaultTask) refers to cmsis_os2.o(.text.osThreadGetId) for osThreadGetId + freertos.o(.text.StartDefaultTask) refers to cmsis_os2.o(.text.osThreadTerminate) for osThreadTerminate + freertos.o(.ARM.exidx.text.StartDefaultTask) refers to freertos.o(.text.StartDefaultTask) for [Anonymous Symbol] + freertos.o(.rodata.defaultTask_attributes) refers to freertos.o(.rodata.str1.1) for [Anonymous Symbol] + can.o(.text.MX_CAN1_Init) refers to can.o(.bss.hcan1) for hcan1 + can.o(.text.MX_CAN1_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Init) for HAL_CAN_Init + can.o(.text.MX_CAN1_Init) refers to main.o(.text.Error_Handler) for Error_Handler + can.o(.ARM.exidx.text.MX_CAN1_Init) refers to can.o(.text.MX_CAN1_Init) for [Anonymous Symbol] + can.o(.text.MX_CAN2_Init) refers to can.o(.bss.hcan2) for hcan2 + can.o(.text.MX_CAN2_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Init) for HAL_CAN_Init + can.o(.text.MX_CAN2_Init) refers to main.o(.text.Error_Handler) for Error_Handler + can.o(.ARM.exidx.text.MX_CAN2_Init) refers to can.o(.text.MX_CAN2_Init) for [Anonymous Symbol] + can.o(.text.HAL_CAN_MspInit) refers to can.o(.bss.HAL_RCC_CAN1_CLK_ENABLED) for HAL_RCC_CAN1_CLK_ENABLED + can.o(.text.HAL_CAN_MspInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + can.o(.text.HAL_CAN_MspInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + can.o(.text.HAL_CAN_MspInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + can.o(.ARM.exidx.text.HAL_CAN_MspInit) refers to can.o(.text.HAL_CAN_MspInit) for [Anonymous Symbol] + can.o(.text.HAL_CAN_MspDeInit) refers to can.o(.bss.HAL_RCC_CAN1_CLK_ENABLED) for HAL_RCC_CAN1_CLK_ENABLED + can.o(.text.HAL_CAN_MspDeInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + can.o(.text.HAL_CAN_MspDeInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ + can.o(.ARM.exidx.text.HAL_CAN_MspDeInit) refers to can.o(.text.HAL_CAN_MspDeInit) for [Anonymous Symbol] + dma.o(.text.MX_DMA_Init) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + dma.o(.text.MX_DMA_Init) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + dma.o(.ARM.exidx.text.MX_DMA_Init) refers to dma.o(.text.MX_DMA_Init) for [Anonymous Symbol] + i2c.o(.text.MX_I2C2_Init) refers to i2c.o(.bss.hi2c2) for hi2c2 + i2c.o(.text.MX_I2C2_Init) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) for HAL_I2C_Init + i2c.o(.text.MX_I2C2_Init) refers to main.o(.text.Error_Handler) for Error_Handler + i2c.o(.ARM.exidx.text.MX_I2C2_Init) refers to i2c.o(.text.MX_I2C2_Init) for [Anonymous Symbol] + i2c.o(.text.HAL_I2C_MspInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + i2c.o(.ARM.exidx.text.HAL_I2C_MspInit) refers to i2c.o(.text.HAL_I2C_MspInit) for [Anonymous Symbol] + i2c.o(.text.HAL_I2C_MspDeInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit) refers to i2c.o(.text.HAL_I2C_MspDeInit) for [Anonymous Symbol] + spi.o(.text.MX_SPI1_Init) refers to spi.o(.bss.hspi1) for hspi1 + spi.o(.text.MX_SPI1_Init) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Init) for HAL_SPI_Init + spi.o(.text.MX_SPI1_Init) refers to main.o(.text.Error_Handler) for Error_Handler + spi.o(.ARM.exidx.text.MX_SPI1_Init) refers to spi.o(.text.MX_SPI1_Init) for [Anonymous Symbol] + spi.o(.text.HAL_SPI_MspInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + spi.o(.text.HAL_SPI_MspInit) refers to spi.o(.bss.hdma_spi1_rx) for hdma_spi1_rx + spi.o(.text.HAL_SPI_MspInit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) for HAL_DMA_Init + spi.o(.text.HAL_SPI_MspInit) refers to main.o(.text.Error_Handler) for Error_Handler + spi.o(.text.HAL_SPI_MspInit) refers to spi.o(.bss.hdma_spi1_tx) for hdma_spi1_tx + spi.o(.ARM.exidx.text.HAL_SPI_MspInit) refers to spi.o(.text.HAL_SPI_MspInit) for [Anonymous Symbol] + spi.o(.text.HAL_SPI_MspDeInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + spi.o(.text.HAL_SPI_MspDeInit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_DeInit) for HAL_DMA_DeInit + spi.o(.ARM.exidx.text.HAL_SPI_MspDeInit) refers to spi.o(.text.HAL_SPI_MspDeInit) for [Anonymous Symbol] + tim.o(.text.MX_TIM10_Init) refers to tim.o(.bss.htim10) for htim10 + tim.o(.text.MX_TIM10_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) for HAL_TIM_Base_Init + tim.o(.text.MX_TIM10_Init) refers to main.o(.text.Error_Handler) for Error_Handler + tim.o(.text.MX_TIM10_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) for HAL_TIM_PWM_Init + tim.o(.text.MX_TIM10_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) for HAL_TIM_PWM_ConfigChannel + tim.o(.text.MX_TIM10_Init) refers to tim.o(.text.HAL_TIM_MspPostInit) for HAL_TIM_MspPostInit + tim.o(.ARM.exidx.text.MX_TIM10_Init) refers to tim.o(.text.MX_TIM10_Init) for [Anonymous Symbol] + tim.o(.text.HAL_TIM_MspPostInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + tim.o(.ARM.exidx.text.HAL_TIM_MspPostInit) refers to tim.o(.text.HAL_TIM_MspPostInit) for [Anonymous Symbol] + tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol] + tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol] + usart.o(.text.MX_USART1_UART_Init) refers to usart.o(.bss.huart1) for huart1 + usart.o(.text.MX_USART1_UART_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init + usart.o(.text.MX_USART1_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.ARM.exidx.text.MX_USART1_UART_Init) refers to usart.o(.text.MX_USART1_UART_Init) for [Anonymous Symbol] + usart.o(.text.MX_USART2_UART_Init) refers to usart.o(.bss.huart2) for huart2 + usart.o(.text.MX_USART2_UART_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init + usart.o(.text.MX_USART2_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.ARM.exidx.text.MX_USART2_UART_Init) refers to usart.o(.text.MX_USART2_UART_Init) for [Anonymous Symbol] + usart.o(.text.MX_USART3_UART_Init) refers to usart.o(.bss.huart3) for huart3 + usart.o(.text.MX_USART3_UART_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init + usart.o(.text.MX_USART3_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.ARM.exidx.text.MX_USART3_UART_Init) refers to usart.o(.text.MX_USART3_UART_Init) for [Anonymous Symbol] + usart.o(.text.MX_USART6_UART_Init) refers to usart.o(.bss.huart6) for huart6 + usart.o(.text.MX_USART6_UART_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init + usart.o(.text.MX_USART6_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.ARM.exidx.text.MX_USART6_UART_Init) refers to usart.o(.text.MX_USART6_UART_Init) for [Anonymous Symbol] + usart.o(.text.HAL_UART_MspInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.hdma_usart3_rx) for hdma_usart3_rx + usart.o(.text.HAL_UART_MspInit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) for HAL_DMA_Init + usart.o(.text.HAL_UART_MspInit) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.text.HAL_UART_MspInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + usart.o(.text.HAL_UART_MspInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + usart.o(.ARM.exidx.text.HAL_UART_MspInit) refers to usart.o(.text.HAL_UART_MspInit) for [Anonymous Symbol] + usart.o(.text.HAL_UART_MspDeInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + usart.o(.text.HAL_UART_MspDeInit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_DeInit) for HAL_DMA_DeInit + usart.o(.text.HAL_UART_MspDeInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ + usart.o(.ARM.exidx.text.HAL_UART_MspDeInit) refers to usart.o(.text.HAL_UART_MspDeInit) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.NMI_Handler) refers to stm32f4xx_it.o(.text.NMI_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.HardFault_Handler) refers to stm32f4xx_it.o(.text.HardFault_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.MemManage_Handler) refers to stm32f4xx_it.o(.text.MemManage_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.BusFault_Handler) refers to stm32f4xx_it.o(.text.BusFault_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.UsageFault_Handler) refers to stm32f4xx_it.o(.text.UsageFault_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.ARM.exidx.text.DebugMon_Handler) refers to stm32f4xx_it.o(.text.DebugMon_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.SysTick_Handler) refers to stm32f4xx_hal.o(.text.HAL_IncTick) for HAL_IncTick + stm32f4xx_it.o(.text.SysTick_Handler) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + stm32f4xx_it.o(.text.SysTick_Handler) refers to port.o(.text.xPortSysTickHandler) for xPortSysTickHandler + stm32f4xx_it.o(.ARM.exidx.text.SysTick_Handler) refers to stm32f4xx_it.o(.text.SysTick_Handler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.EXTI0_IRQHandler) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for HAL_GPIO_EXTI_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.EXTI0_IRQHandler) refers to stm32f4xx_it.o(.text.EXTI0_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.EXTI3_IRQHandler) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for HAL_GPIO_EXTI_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.EXTI3_IRQHandler) refers to stm32f4xx_it.o(.text.EXTI3_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.EXTI4_IRQHandler) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for HAL_GPIO_EXTI_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.EXTI4_IRQHandler) refers to stm32f4xx_it.o(.text.EXTI4_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) refers to usart.o(.bss.hdma_usart3_rx) for hdma_usart3_rx + stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for HAL_DMA_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.DMA1_Stream1_IRQHandler) refers to stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) refers to can.o(.bss.hcan1) for hcan1 + stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN1_TX_IRQHandler) refers to stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) refers to can.o(.bss.hcan1) for hcan1 + stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN1_RX0_IRQHandler) refers to stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) refers to can.o(.bss.hcan1) for hcan1 + stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN1_RX1_IRQHandler) refers to stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) refers to can.o(.bss.hcan1) for hcan1 + stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN1_SCE_IRQHandler) refers to stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for HAL_GPIO_EXTI_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.EXTI9_5_IRQHandler) refers to stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.USART1_IRQHandler) refers to usart.o(.bss.huart1) for huart1 + stm32f4xx_it.o(.text.USART1_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler + stm32f4xx_it.o(.text.USART1_IRQHandler) refers to uart.o(.text.BSP_UART_IRQHandler) for BSP_UART_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.USART1_IRQHandler) refers to stm32f4xx_it.o(.text.USART1_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.USART2_IRQHandler) refers to usart.o(.bss.huart2) for huart2 + stm32f4xx_it.o(.text.USART2_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.USART2_IRQHandler) refers to stm32f4xx_it.o(.text.USART2_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) refers to spi.o(.bss.hdma_spi1_rx) for hdma_spi1_rx + stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for HAL_DMA_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.DMA2_Stream2_IRQHandler) refers to stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) refers to spi.o(.bss.hdma_spi1_tx) for hdma_spi1_tx + stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for HAL_DMA_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.DMA2_Stream3_IRQHandler) refers to stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) refers to can.o(.bss.hcan2) for hcan2 + stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN2_TX_IRQHandler) refers to stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) refers to can.o(.bss.hcan2) for hcan2 + stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN2_RX1_IRQHandler) refers to stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) refers to can.o(.bss.hcan2) for hcan2 + stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for HAL_CAN_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.CAN2_SCE_IRQHandler) refers to stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) for [Anonymous Symbol] + stm32f4xx_it.o(.text.USART6_IRQHandler) refers to usart.o(.bss.huart6) for huart6 + stm32f4xx_it.o(.text.USART6_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler + stm32f4xx_it.o(.text.USART6_IRQHandler) refers to uart.o(.text.BSP_UART_IRQHandler) for BSP_UART_IRQHandler + stm32f4xx_it.o(.ARM.exidx.text.USART6_IRQHandler) refers to stm32f4xx_it.o(.text.USART6_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_msp.o(.text.HAL_MspInit) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32f4xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit) refers to stm32f4xx_hal_msp.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.text.HAL_CAN_Init) refers to can.o(.text.HAL_CAN_MspInit) for HAL_CAN_MspInit + stm32f4xx_hal_can.o(.text.HAL_CAN_Init) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Init) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_MspInit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.text.HAL_CAN_DeInit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Stop) for HAL_CAN_Stop + stm32f4xx_hal_can.o(.text.HAL_CAN_DeInit) refers to can.o(.text.HAL_CAN_MspDeInit) for HAL_CAN_MspDeInit + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_DeInit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.text.HAL_CAN_Stop) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Stop) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Stop) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_MspDeInit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ConfigFilter) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ConfigFilter) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.text.HAL_CAN_Start) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Start) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Start) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RequestSleep) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_RequestSleep) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_WakeUp) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_WakeUp) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IsSleepActive) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IsSleepActive) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_AddTxMessage) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_AbortTxRequest) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_AbortTxRequest) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetTxMailboxesFreeLevel) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IsTxMessagePending) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IsTxMessagePending) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetTxTimestamp) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxTimestamp) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetRxMessage) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetRxFifoFillLevel) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ActivateNotification) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ActivateNotification) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_DeactivateNotification) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_DeactivateNotification) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) for HAL_CAN_TxMailbox0AbortCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) for HAL_CAN_TxMailbox0CompleteCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_RxFifo0FullCallback) for HAL_CAN_RxFifo0FullCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) for HAL_CAN_RxFifo0MsgPendingCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_RxFifo1FullCallback) for HAL_CAN_RxFifo1FullCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) for HAL_CAN_RxFifo1MsgPendingCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_SleepCallback) for HAL_CAN_SleepCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) for HAL_CAN_WakeUpFromRxMsgCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) for HAL_CAN_TxMailbox1AbortCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) for HAL_CAN_TxMailbox1CompleteCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) for HAL_CAN_TxMailbox2AbortCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) for HAL_CAN_TxMailbox2CompleteCallback + stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) refers to can_1.o(.text.HAL_CAN_ErrorCallback) for HAL_CAN_ErrorCallback + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IRQHandler) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox0CompleteCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox0CompleteCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox0AbortCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox0AbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox1CompleteCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox1CompleteCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox1AbortCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox1AbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox2CompleteCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox2CompleteCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox2AbortCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox2AbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo0FullCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo0FullCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo0MsgPendingCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo1FullCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo1FullCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo1MsgPendingCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_SleepCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_SleepCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_WakeUpFromRxMsgCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ErrorCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetState) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetState) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetError) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetError) for [Anonymous Symbol] + stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ResetError) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ResetError) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32f4xx.o(.rodata.AHBPrescTable) for AHBPrescTable + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32f4xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32f4xx_hal.o(.text.HAL_InitTick) for HAL_InitTick + stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) refers to lludivv7m.o(.text) for __aeabi_uldivmod + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_EnableCSS) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DisableCSS) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_DisableCSS) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to system_stm32f4xx.o(.rodata.APBPrescTable) for APBPrescTable + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to system_stm32f4xx.o(.rodata.APBPrescTable) for APBPrescTable + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for HAL_RCC_CSSCallback + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLLI2S) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLLI2S) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLLI2S) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLLI2S) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLLI2S) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLLI2S) for [Anonymous Symbol] + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit) refers to stm32f4xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit) refers to stm32f4xx_hal.o(.text.HAL_InitTick) for HAL_InitTick + stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCC_DeInit) refers to stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Byte) for FLASH_Program_Byte + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Word) for FLASH_Program_Word + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_HalfWord) for FLASH_Program_HalfWord + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_DoubleWord) for FLASH_Program_DoubleWord + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32f4xx_hal_flash.o(.text.FLASH_SetErrorCode) for FLASH_SetErrorCode + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Byte) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Byte) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_HalfWord) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_HalfWord) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Word) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Word) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_DoubleWord) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_DoubleWord) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Byte) for FLASH_Program_Byte + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_Word) for FLASH_Program_Word + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_HalfWord) for FLASH_Program_HalfWord + stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.text.FLASH_Program_DoubleWord) for FLASH_Program_DoubleWord + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash.o(.text.FLASH_SetErrorCode) for FLASH_SetErrorCode + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for HAL_FLASH_OperationErrorCallback + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for HAL_FLASH_EndOfOperationCallback + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_FlushCaches) for FLASH_FlushCaches + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.FLASH_SetErrorCode) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_SetErrorCode) refers to stm32f4xx_hal_flash.o(.text.FLASH_SetErrorCode) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_Unlock) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_Lock) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Lock) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) for [Anonymous Symbol] + stm32f4xx_hal_flash.o(.text.HAL_FLASH_GetError) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError) refers to stm32f4xx_hal_flash.o(.text.HAL_FLASH_GetError) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_FlushCaches) for FLASH_FlushCaches + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase) refers to stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_MassErase) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_FlushCaches) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_FlushCaches) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT) refers to stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash.o(.data.pFlash) for pFlash + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for FLASH_OB_EnableWRP + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for FLASH_OB_DisableWRP + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_RDP_LevelConfig) for FLASH_OB_RDP_LevelConfig + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for FLASH_OB_UserConfig + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig) for FLASH_OB_BOR_LevelConfig + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram) refers to stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_RDP_LevelConfig) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_RDP_LevelConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_RDP_LevelConfig) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) refers to stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BOR_LevelConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for FLASH_OB_GetWRP + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP) for FLASH_OB_GetRDP + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for FLASH_OB_GetUser + stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR) for FLASH_OB_GetBOR + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig) refers to stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetRDP) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for [Anonymous Symbol] + stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBOR) refers to stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_TogglePin) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_LockPin) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) refers to gpio_1.o(.text.HAL_GPIO_EXTI_Callback) for HAL_GPIO_EXTI_Callback + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Callback) for [Anonymous Symbol] + stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart) refers to stm32f4xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for DMA_MultiBufferSetConfig + stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart) refers to stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart) for [Anonymous Symbol] + stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.DMA_MultiBufferSetConfig) refers to stm32f4xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for [Anonymous Symbol] + stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT) refers to stm32f4xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig) for DMA_MultiBufferSetConfig + stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart_IT) refers to stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT) for [Anonymous Symbol] + stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ChangeMemory) refers to stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_ChangeMemory) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32f4xx_hal_dma.o(.text.DMA_CheckFifoParam) for DMA_CheckFifoParam + stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for DMA_CalcBaseAndBitshift + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_CheckFifoParam) refers to stm32f4xx_hal_dma.o(.text.DMA_CheckFifoParam) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_CalcBaseAndBitshift) refers to stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) for DMA_CalcBaseAndBitshift + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_Start) refers to stm32f4xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig) refers to stm32f4xx_hal_dma.o(.text.DMA_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) refers to stm32f4xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_RegisterCallback) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetState) for [Anonymous Symbol] + stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnablePVD) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisablePVD) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for HAL_PWR_PVDCallback + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend) for [Anonymous Symbol] + stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend) refers to stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkUpReg) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkUpReg) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange) for [Anonymous Symbol] + stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling) refers to stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for __NVIC_SetPriorityGrouping + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32f4xx_hal_cortex.o(.text.NVIC_EncodePriority) for NVIC_EncodePriority + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority) refers to stm32f4xx_hal_cortex.o(.text.NVIC_EncodePriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for __NVIC_EnableIRQ + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for __NVIC_DisableIRQ + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SystemReset) for __NVIC_SystemReset + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SystemReset) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config) refers to stm32f4xx_hal_cortex.o(.text.SysTick_Config) for SysTick_Config + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.SysTick_Config) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + stm32f4xx_hal_cortex.o(.ARM.exidx.text.SysTick_Config) refers to stm32f4xx_hal_cortex.o(.text.SysTick_Config) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable) refers to stm32f4xx_hal_cortex.o(.text.HAL_MPU_Disable) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable) refers to stm32f4xx_hal_cortex.o(.text.HAL_MPU_Enable) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion) refers to stm32f4xx_hal_cortex.o(.text.HAL_MPU_EnableRegion) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion) refers to stm32f4xx_hal_cortex.o(.text.HAL_MPU_DisableRegion) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion) refers to stm32f4xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_CORTEX_ClearEvent) refers to stm32f4xx_hal_cortex.o(.text.HAL_CORTEX_ClearEvent) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriority) for __NVIC_GetPriority + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32f4xx_hal_cortex.o(.text.NVIC_DecodePriority) for NVIC_DecodePriority + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority) refers to stm32f4xx_hal_cortex.o(.text.NVIC_DecodePriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriority) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for __NVIC_SetPendingIRQ + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for __NVIC_GetPendingIRQ + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for __NVIC_ClearPendingIRQ + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetActive) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetActive) for __NVIC_GetActive + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetActive) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive) refers to stm32f4xx_hal_cortex.o(.text.__NVIC_GetActive) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for HAL_SYSTICK_Callback + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_Init) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for HAL_NVIC_SetPriorityGrouping + stm32f4xx_hal.o(.text.HAL_Init) refers to stm32f4xx_hal.o(.text.HAL_InitTick) for HAL_InitTick + stm32f4xx_hal.o(.text.HAL_Init) refers to stm32f4xx_hal_msp.o(.text.HAL_MspInit) for HAL_MspInit + stm32f4xx_hal.o(.ARM.exidx.text.HAL_Init) refers to stm32f4xx_hal.o(.text.HAL_Init) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_InitTick) refers to stm32f4xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32f4xx_hal.o(.text.HAL_InitTick) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal.o(.text.HAL_InitTick) refers to stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for HAL_SYSTICK_Config + stm32f4xx_hal.o(.text.HAL_InitTick) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32f4xx_hal.o(.text.HAL_InitTick) refers to stm32f4xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32f4xx_hal.o(.ARM.exidx.text.HAL_InitTick) refers to stm32f4xx_hal.o(.text.HAL_InitTick) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_MspInit) refers to stm32f4xx_hal.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_DeInit) refers to stm32f4xx_hal.o(.text.HAL_MspDeInit) for HAL_MspDeInit + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DeInit) refers to stm32f4xx_hal.o(.text.HAL_DeInit) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_MspDeInit) refers to stm32f4xx_hal.o(.text.HAL_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_IncTick) refers to stm32f4xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32f4xx_hal.o(.text.HAL_IncTick) refers to stm32f4xx_hal.o(.bss.uwTick) for uwTick + stm32f4xx_hal.o(.ARM.exidx.text.HAL_IncTick) refers to stm32f4xx_hal.o(.text.HAL_IncTick) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_GetTick) refers to stm32f4xx_hal.o(.bss.uwTick) for uwTick + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTick) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_GetTickPrio) refers to stm32f4xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio) refers to stm32f4xx_hal.o(.text.HAL_GetTickPrio) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_SetTickFreq) refers to stm32f4xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32f4xx_hal.o(.text.HAL_SetTickFreq) refers to stm32f4xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32f4xx_hal.o(.text.HAL_SetTickFreq) refers to stm32f4xx_hal.o(.text.HAL_InitTick) for HAL_InitTick + stm32f4xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq) refers to stm32f4xx_hal.o(.text.HAL_SetTickFreq) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_GetTickFreq) refers to stm32f4xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq) refers to stm32f4xx_hal.o(.text.HAL_GetTickFreq) for [Anonymous Symbol] + stm32f4xx_hal.o(.text.HAL_Delay) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal.o(.text.HAL_Delay) refers to stm32f4xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32f4xx_hal.o(.ARM.exidx.text.HAL_Delay) refers to stm32f4xx_hal.o(.text.HAL_Delay) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_SuspendTick) refers to stm32f4xx_hal.o(.text.HAL_SuspendTick) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_ResumeTick) refers to stm32f4xx_hal.o(.text.HAL_ResumeTick) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion) refers to stm32f4xx_hal.o(.text.HAL_GetHalVersion) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetREVID) refers to stm32f4xx_hal.o(.text.HAL_GetREVID) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetDEVID) refers to stm32f4xx_hal.o(.text.HAL_GetDEVID) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGSleepMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGSleepMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGSleepMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGSleepMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode) refers to stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_EnableCompensationCell) refers to stm32f4xx_hal.o(.text.HAL_EnableCompensationCell) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_DisableCompensationCell) refers to stm32f4xx_hal.o(.text.HAL_DisableCompensationCell) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0) refers to stm32f4xx_hal.o(.text.HAL_GetUIDw0) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1) refers to stm32f4xx_hal.o(.text.HAL_GetUIDw1) for [Anonymous Symbol] + stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2) refers to stm32f4xx_hal.o(.text.HAL_GetUIDw2) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetHandle) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetPending) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_ClearPending) for [Anonymous Symbol] + stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI) refers to stm32f4xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) refers to i2c.o(.text.HAL_I2C_MspInit) for HAL_I2C_MspInit + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Init) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspInit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_DeInit) refers to i2c.o(.text.HAL_I2C_MspDeInit) for HAL_I2C_MspDeInit + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DeInit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestWrite) for I2C_MasterRequestWrite + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout) for I2C_WaitOnBTFFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for I2C_WaitOnTXEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) for I2C_WaitOnMasterAddressFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterRequestWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestWrite) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_IsAcknowledgeFailed) for I2C_IsAcknowledgeFailed + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnTXEFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_IsAcknowledgeFailed) for I2C_IsAcknowledgeFailed + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnBTFFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestRead) for I2C_MasterRequestRead + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for I2C_WaitOnRXNEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) for I2C_WaitOnMasterAddressFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterRequestRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestRead) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnRXNEFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for I2C_WaitOnTXEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for I2C_WaitOnRXNEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for I2C_WaitOnSTOPFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_IsAcknowledgeFailed) for I2C_IsAcknowledgeFailed + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) refers to i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) for HAL_I2C_SlaveTxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) refers to i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) for HAL_I2C_SlaveRxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) refers to i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) for HAL_I2C_MemRxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) refers to i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) for HAL_I2C_MasterRxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAXferCplt) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_DMAError) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32f4xx_hal_i2c.o(.text.I2C_DMAError) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAError) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) for I2C_RequestMemoryWrite + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for I2C_WaitOnTXEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout) for I2C_WaitOnBTFFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) for I2C_WaitOnMasterAddressFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for I2C_WaitOnTXEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryWrite) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) for I2C_RequestMemoryRead + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout) for I2C_WaitOnRXNEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) for I2C_WaitOnMasterAddressFlagUntilTimeout + stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout) for I2C_WaitOnTXEFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryRead) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite) for I2C_RequestMemoryWrite + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead) for I2C_RequestMemoryRead + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout) for I2C_WaitOnFlagUntilTimeout + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_IsDeviceReady) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) refers to i2c_1.o(.text.HAL_I2C_AbortCpltCallback) for HAL_I2C_AbortCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAAbort) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt) for I2C_DMAXferCplt + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAError) for I2C_DMAError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_DMA) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EnableListen_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DisableListen_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_DisableListen_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) refers to stm32f4xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Abort_IT) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_ITError) refers to i2c_1.o(.text.HAL_I2C_AbortCpltCallback) for HAL_I2C_AbortCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_ITError) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32f4xx_hal_i2c.o(.text.I2C_ITError) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.text.I2C_ITError) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32f4xx_hal_i2c.o(.text.I2C_ITError) refers to i2c_1.o(.text.HAL_I2C_ListenCpltCallback) for HAL_I2C_ListenCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_ITError) refers to stm32f4xx_hal_i2c.o(.text.I2C_ITError) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_TXE) for I2C_SlaveTransmit_TXE + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) for I2C_MasterReceive_RXNE + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for I2C_ConvertOtherXferOptions + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_SB) for I2C_Master_SB + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_ADDR) for I2C_Slave_ADDR + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) for I2C_Slave_STOPF + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_ADD10) for I2C_Master_ADD10 + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_ADDR) for I2C_Master_ADDR + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE) for I2C_MasterTransmit_TXE + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_RXNE) for I2C_SlaveReceive_RXNE + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_BTF) for I2C_SlaveTransmit_BTF + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_BTF) for I2C_SlaveReceive_BTF + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_BTF) for I2C_MasterReceive_BTF + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_BTF) for I2C_MasterTransmit_BTF + stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF) for I2C_MemoryTransmit_TXE_BTF + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EV_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_ConvertOtherXferOptions) refers to stm32f4xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_SB) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_SB) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ADD10) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_ADD10) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ADDR) refers to stm32f4xx_hal_i2c.o(.text.I2C_Master_ADDR) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE) refers to i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) for HAL_I2C_MemTxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE) refers to stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF) for I2C_MemoryTransmit_TXE_BTF + stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE) refers to i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback) for HAL_I2C_MasterTxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterTransmit_TXE) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_BTF) refers to i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) for HAL_I2C_MemTxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_BTF) refers to i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback) for HAL_I2C_MasterTxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterTransmit_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_BTF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_Flush_DR) for I2C_Flush_DR + stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF) refers to i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) for HAL_I2C_MemTxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MemoryTransmit_TXE_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPRequestThroughIT) for I2C_WaitOnSTOPRequestThroughIT + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for HAL_I2C_ErrorCallback + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) refers to i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) for HAL_I2C_MemRxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) refers to i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) for HAL_I2C_MasterRxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterReceive_RXNE) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_BTF) refers to i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) for HAL_I2C_MemRxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_BTF) refers to i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) for HAL_I2C_MasterRxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterReceive_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_BTF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_Slave_ADDR) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_AddrCallback) for HAL_I2C_AddrCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ADDR) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_ADDR) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetState) for HAL_DMA_GetState + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort) for I2C_DMAAbort + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to stm32f4xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) for HAL_I2C_SlaveRxCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) refers to i2c_1.o(.text.HAL_I2C_ListenCpltCallback) for HAL_I2C_ListenCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_STOPF) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_TXE) refers to i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) for HAL_I2C_SlaveTxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveTransmit_TXE) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_TXE) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveTransmit_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_BTF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_RXNE) refers to i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) for HAL_I2C_SlaveRxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveReceive_RXNE) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_RXNE) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveReceive_BTF) refers to stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_BTF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_ITError) for I2C_ITError + stm32f4xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF) for I2C_Slave_AF + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ER_IRQHandler) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF) refers to i2c_1.o(.text.HAL_I2C_ListenCpltCallback) for HAL_I2C_ListenCpltCallback + stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF) refers to stm32f4xx_hal_i2c.o(.text.I2C_Flush_DR) for I2C_Flush_DR + stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF) refers to i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) for HAL_I2C_SlaveTxCpltCallback + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_AF) refers to stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AddrCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_AddrCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MemTxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_MemRxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ErrorCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_ErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_AbortCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetState) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetState) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetMode) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetMode) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetError) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetError) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Flush_DR) refers to stm32f4xx_hal_i2c.o(.text.I2C_Flush_DR) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPRequestThroughIT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPRequestThroughIT) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPRequestThroughIT) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnMasterAddressFlagUntilTimeout) refers to stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_IsAcknowledgeFailed) refers to stm32f4xx_hal_i2c.o(.text.I2C_IsAcknowledgeFailed) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Init) refers to spi.o(.text.HAL_SPI_MspInit) for HAL_SPI_MspInit + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Init) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Init) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_MspInit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_DeInit) refers to spi.o(.text.HAL_SPI_MspDeInit) for HAL_SPI_MspDeInit + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DeInit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_MspDeInit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) refers to stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) for SPI_WaitFlagStateUntilTimeout + stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_EndRxTxTransaction) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) for HAL_SPI_TransmitReceive + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) for SPI_EndRxTransaction + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) refers to stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) for SPI_WaitFlagStateUntilTimeout + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_EndRxTransaction) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_TxISR_16BIT) for SPI_TxISR_16BIT + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_TxISR_8BIT) for SPI_TxISR_8BIT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit_IT) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_TxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) for SPI_CloseTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_TxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_TxISR_16BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_TxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) for SPI_CloseTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_TxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_TxISR_8BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_IT) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) for HAL_SPI_TransmitReceive_IT + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_RxISR_16BIT) for SPI_RxISR_16BIT + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_RxISR_8BIT) for SPI_RxISR_8BIT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive_IT) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_8BIT) for SPI_2linesRxISR_8BIT + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_16BIT) for SPI_2linesRxISR_16BIT + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_16BIT) for SPI_2linesTxISR_16BIT + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_8BIT) for SPI_2linesTxISR_8BIT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive_IT) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_RxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) for SPI_CloseRx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_RxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_RxISR_16BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_RxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) for SPI_CloseRx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_RxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_RxISR_8BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) for SPI_CloseRxTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesRxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_16BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) for SPI_CloseRxTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesTxISR_16BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_16BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) for SPI_CloseRxTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesRxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_8BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) for SPI_CloseRxTx_ISR + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesTxISR_8BIT) refers to stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_8BIT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) for SPI_DMAHalfTransmitCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) for SPI_DMATransmitCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAError) for SPI_DMAError + stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit_DMA) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) refers to spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) for HAL_SPI_TxHalfCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfTransmitCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) refers to spi_1.o(.text.HAL_SPI_TxCpltCallback) for HAL_SPI_TxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATransmitCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAError) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAError) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAError) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) for HAL_SPI_TransmitReceive_DMA + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) for SPI_DMAHalfReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) for SPI_DMAReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAError) for SPI_DMAError + stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive_DMA) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) for SPI_DMAHalfReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) for SPI_DMAHalfTransmitReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) for SPI_DMAReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) for SPI_DMATransmitReceiveCplt + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAError) for SPI_DMAError + stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive_DMA) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) refers to spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) for HAL_SPI_RxHalfCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) for SPI_EndRxTransaction + stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) refers to spi_1.o(.text.HAL_SPI_RxCpltCallback) for HAL_SPI_RxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) refers to spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) for HAL_SPI_TxRxHalfCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfTransmitReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) refers to spi_1.o(.text.HAL_SPI_TxRxCpltCallback) for HAL_SPI_TxRxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATransmitReceiveCplt) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortTx_ISR) for SPI_AbortTx_ISR + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortRx_ISR) for SPI_AbortRx_ISR + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Abort) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_AbortTx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortTx_ISR) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_AbortRx_ISR) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_AbortRx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortRx_ISR) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortTx_ISR) for SPI_AbortTx_ISR + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_AbortRx_ISR) for SPI_AbortRx_ISR + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATxAbortCallback) for SPI_DMATxAbortCallback + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback) for SPI_DMARxAbortCallback + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) refers to spi_1.o(.text.HAL_SPI_AbortCpltCallback) for HAL_SPI_AbortCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Abort_IT) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMATxAbortCallback) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.text.SPI_DMATxAbortCallback) refers to spi_1.o(.text.HAL_SPI_AbortCpltCallback) for HAL_SPI_AbortCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATxAbortCallback) refers to stm32f4xx_hal_spi.o(.text.SPI_DMATxAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback) refers to spi_1.o(.text.HAL_SPI_AbortCpltCallback) for HAL_SPI_AbortCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMARxAbortCallback) refers to stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_AbortCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_AbortCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAPause) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAPause) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAResume) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAResume) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAStop) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAStop) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAStop) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.HAL_SPI_IRQHandler) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAAbortOnError) for SPI_DMAAbortOnError + stm32f4xx_hal_spi.o(.text.HAL_SPI_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_spi.o(.text.HAL_SPI_IRQHandler) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_IRQHandler) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_DMAAbortOnError) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAAbortOnError) refers to stm32f4xx_hal_spi.o(.text.SPI_DMAAbortOnError) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_ErrorCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_ErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_RxCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_RxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxRxCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TxRxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxHalfCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TxHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_RxHalfCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_RxHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxRxHalfCpltCallback) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TxRxHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_GetState) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_GetState) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_GetError) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_GetError) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to spi_1.o(.text.HAL_SPI_RxCpltCallback) for HAL_SPI_RxCpltCallback + stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) refers to spi_1.o(.text.HAL_SPI_TxRxCpltCallback) for HAL_SPI_TxRxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseRxTx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) for SPI_EndRxTransaction + stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) refers to spi_1.o(.text.HAL_SPI_RxCpltCallback) for HAL_SPI_RxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseRx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) for SPI_EndRxTxTransaction + stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for HAL_SPI_ErrorCallback + stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) refers to spi_1.o(.text.HAL_SPI_TxCpltCallback) for HAL_SPI_TxCpltCallback + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseTx_ISR) refers to stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR) for [Anonymous Symbol] + stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_WaitFlagStateUntilTimeout) refers to stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to tim.o(.text.HAL_TIM_Base_MspInit) for HAL_TIM_Base_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) refers to tim.o(.text.HAL_TIM_Base_MspDeInit) for HAL_TIM_Base_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for HAL_TIM_PeriodElapsedHalfCpltCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMAError) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for HAL_TIM_OC_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for HAL_TIM_OC_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for HAL_TIM_PWM_PulseFinishedHalfCpltCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for HAL_TIM_PWM_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for HAL_TIM_PWM_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for HAL_TIM_IC_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for HAL_TIM_IC_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for HAL_TIM_IC_CaptureHalfCpltCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for HAL_TIM_OnePulse_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for HAL_TIM_OnePulse_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for HAL_TIM_Encoder_MspInit + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for HAL_TIM_Encoder_MspDeInit + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for HAL_TIM_OC_DelayElapsedCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for HAL_TIMEx_BreakCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI3_SetConfig) for TIM_TI3_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI4_SetConfig) for TIM_TI4_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI3_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI4_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for HAL_TIM_DMABurst_MultiWriteStart + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMATriggerCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for HAL_TIM_TriggerHalfCpltCallback + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for HAL_TIM_DMABurst_MultiReadStart + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_GenerateEvent) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) refers to stm32f4xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_ETR_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32f4xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32f4xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for TIM_ITRx_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) refers to stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig) refers to stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_GetChannelState) for [Anonymous Symbol] + stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurstState) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for HAL_TIMEx_HallSensor_MspInit + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for HAL_TIMEx_HallSensor_MspDeInit + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32f4xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for HAL_TIMEx_CommutHalfCpltCallback + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt) refers to stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState) for [Anonymous Symbol] + stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState) refers to stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32f4xx_hal_uart.o(.text.HAL_UART_Init) refers to stm32f4xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Init) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspInit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_MspInit) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_SetConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for HAL_RCC_GetPCLK2Freq + stm32f4xx_hal_uart.o(.text.UART_SetConfig) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + stm32f4xx_hal_uart.o(.text.UART_SetConfig) refers to lludivv7m.o(.text) for __aeabi_uldivmod + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_SetConfig) refers to stm32f4xx_hal_uart.o(.text.UART_SetConfig) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to stm32f4xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_Init) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_LIN_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32f4xx_hal_uart.o(.text.HAL_LIN_Init) refers to stm32f4xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_LIN_Init) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to stm32f4xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_Init) refers to stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_Init) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_DeInit) refers to usart.o(.text.HAL_UART_MspDeInit) for HAL_UART_MspDeInit + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DeInit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_DeInit) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspDeInit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_MspDeInit) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit) refers to stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) refers to stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_WaitOnFlagUntilTimeout) refers to stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Receive) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_uart.o(.text.HAL_UART_Receive) refers to stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT) for UART_Start_Receive_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_IT) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) for UART_DMATransmitCplt + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) for UART_DMATxHalfCplt + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMAError) for UART_DMAError + stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_DMA) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) refers to uart.o(.text.HAL_UART_TxCpltCallback) for HAL_UART_TxCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATransmitCplt) refers to stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) refers to uart.o(.text.HAL_UART_TxHalfCpltCallback) for HAL_UART_TxHalfCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxHalfCplt) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMAError) refers to stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer) for UART_EndTxTransfer + stm32f4xx_hal_uart.o(.text.UART_DMAError) refers to stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32f4xx_hal_uart.o(.text.UART_DMAError) refers to uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAError) refers to stm32f4xx_hal_uart.o(.text.UART_DMAError) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) for UART_Start_Receive_DMA + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) for UART_DMAReceiveCplt + stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) for UART_DMARxHalfCplt + stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_DMAError) for UART_DMAError + stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAPause) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_DMAPause) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAResume) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_DMAResume) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer) for UART_EndTxTransfer + stm32f4xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAStop) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_DMAStop) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndTxTransfer) refers to stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndRxTransfer) refers to stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_IT) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT) for UART_Start_Receive_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_DMA) refers to stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) for UART_Start_Receive_DMA + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_DMA) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_DMA) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_GetRxEventType) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_GetRxEventType) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Abort) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxAbortCallback) for UART_DMATxAbortCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxAbortCallback) for UART_DMARxAbortCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMATxAbortCallback) refers to uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxAbortCallback) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMARxAbortCallback) refers to uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxAbortCallback) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for HAL_UART_AbortTransmitCpltCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) for UART_DMATxOnlyAbortCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) refers to uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for HAL_UART_AbortTransmitCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxOnlyAbortCallback) refers to stm32f4xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for HAL_UART_AbortReceiveCpltCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) for UART_DMARxOnlyAbortCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) refers to uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for HAL_UART_AbortReceiveCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxOnlyAbortCallback) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.UART_Receive_IT) for UART_Receive_IT + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT) for UART_EndTransmit_IT + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.UART_Transmit_IT) for UART_Transmit_IT + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) for UART_DMAAbortOnError + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_IRQHandler) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_Receive_IT) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32f4xx_hal_uart.o(.text.UART_Receive_IT) refers to uart.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Receive_IT) refers to stm32f4xx_hal_uart.o(.text.UART_Receive_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) refers to uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAAbortOnError) refers to stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_RxEventCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Transmit_IT) refers to stm32f4xx_hal_uart.o(.text.UART_Transmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT) refers to uart.o(.text.HAL_UART_TxCpltCallback) for HAL_UART_TxCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndTransmit_IT) refers to stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_TxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_TxHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_RxCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_SendBreak) refers to stm32f4xx_hal_uart.o(.text.HAL_LIN_SendBreak) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnterMuteMode) refers to stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_EnterMuteMode) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_ExitMuteMode) refers to stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_ExitMuteMode) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableTransmitter) refers to stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_EnableTransmitter) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableReceiver) refers to stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_EnableReceiver) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetState) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_GetState) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetError) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_GetError) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) refers to uart.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAReceiveCplt) refers to stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) for [Anonymous Symbol] + stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) refers to stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) refers to uart.o(.text.HAL_UART_RxHalfCpltCallback) for HAL_UART_RxHalfCpltCallback + stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxHalfCplt) refers to stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) for [Anonymous Symbol] + system_stm32f4xx.o(.ARM.exidx.text.SystemInit) refers to system_stm32f4xx.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32f4xx.o(.text.SystemCoreClockUpdate) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32f4xx.o(.text.SystemCoreClockUpdate) refers to system_stm32f4xx.o(.rodata.AHBPrescTable) for AHBPrescTable + system_stm32f4xx.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32f4xx.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupCreateStatic) refers to list.o(.text.vListInitialise) for vListInitialise + event_groups.o(.ARM.exidx.text.xEventGroupCreateStatic) refers to event_groups.o(.text.xEventGroupCreateStatic) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupCreate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + event_groups.o(.text.xEventGroupCreate) refers to list.o(.text.vListInitialise) for vListInitialise + event_groups.o(.ARM.exidx.text.xEventGroupCreate) refers to event_groups.o(.text.xEventGroupCreate) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupSync) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + event_groups.o(.text.xEventGroupSync) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + event_groups.o(.text.xEventGroupSync) refers to event_groups.o(.text.xEventGroupSetBits) for xEventGroupSetBits + event_groups.o(.text.xEventGroupSync) refers to tasks.o(.text.vTaskPlaceOnUnorderedEventList) for vTaskPlaceOnUnorderedEventList + event_groups.o(.text.xEventGroupSync) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + event_groups.o(.text.xEventGroupSync) refers to tasks.o(.text.uxTaskResetEventItemValue) for uxTaskResetEventItemValue + event_groups.o(.text.xEventGroupSync) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + event_groups.o(.text.xEventGroupSync) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + event_groups.o(.ARM.exidx.text.xEventGroupSync) refers to event_groups.o(.text.xEventGroupSync) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupSetBits) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + event_groups.o(.text.xEventGroupSetBits) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + event_groups.o(.text.xEventGroupSetBits) refers to tasks.o(.text.vTaskRemoveFromUnorderedEventList) for vTaskRemoveFromUnorderedEventList + event_groups.o(.ARM.exidx.text.xEventGroupSetBits) refers to event_groups.o(.text.xEventGroupSetBits) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupWaitBits) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + event_groups.o(.text.xEventGroupWaitBits) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + event_groups.o(.text.xEventGroupWaitBits) refers to event_groups.o(.text.prvTestWaitCondition) for prvTestWaitCondition + event_groups.o(.text.xEventGroupWaitBits) refers to tasks.o(.text.vTaskPlaceOnUnorderedEventList) for vTaskPlaceOnUnorderedEventList + event_groups.o(.text.xEventGroupWaitBits) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + event_groups.o(.text.xEventGroupWaitBits) refers to tasks.o(.text.uxTaskResetEventItemValue) for uxTaskResetEventItemValue + event_groups.o(.text.xEventGroupWaitBits) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + event_groups.o(.text.xEventGroupWaitBits) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + event_groups.o(.ARM.exidx.text.xEventGroupWaitBits) refers to event_groups.o(.text.xEventGroupWaitBits) for [Anonymous Symbol] + event_groups.o(.ARM.exidx.text.prvTestWaitCondition) refers to event_groups.o(.text.prvTestWaitCondition) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupClearBits) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + event_groups.o(.text.xEventGroupClearBits) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + event_groups.o(.ARM.exidx.text.xEventGroupClearBits) refers to event_groups.o(.text.xEventGroupClearBits) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupClearBitsFromISR) refers to event_groups.o(.text.vEventGroupClearBitsCallback) for vEventGroupClearBitsCallback + event_groups.o(.text.xEventGroupClearBitsFromISR) refers to timers.o(.text.xTimerPendFunctionCallFromISR) for xTimerPendFunctionCallFromISR + event_groups.o(.ARM.exidx.text.xEventGroupClearBitsFromISR) refers to event_groups.o(.text.xEventGroupClearBitsFromISR) for [Anonymous Symbol] + event_groups.o(.text.vEventGroupClearBitsCallback) refers to event_groups.o(.text.xEventGroupClearBits) for xEventGroupClearBits + event_groups.o(.ARM.exidx.text.vEventGroupClearBitsCallback) refers to event_groups.o(.text.vEventGroupClearBitsCallback) for [Anonymous Symbol] + event_groups.o(.ARM.exidx.text.xEventGroupGetBitsFromISR) refers to event_groups.o(.text.xEventGroupGetBitsFromISR) for [Anonymous Symbol] + event_groups.o(.text.vEventGroupDelete) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + event_groups.o(.text.vEventGroupDelete) refers to tasks.o(.text.vTaskRemoveFromUnorderedEventList) for vTaskRemoveFromUnorderedEventList + event_groups.o(.text.vEventGroupDelete) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + event_groups.o(.text.vEventGroupDelete) refers to heap_4.o(.text.vPortFree) for vPortFree + event_groups.o(.ARM.exidx.text.vEventGroupDelete) refers to event_groups.o(.text.vEventGroupDelete) for [Anonymous Symbol] + event_groups.o(.text.vEventGroupSetBitsCallback) refers to event_groups.o(.text.xEventGroupSetBits) for xEventGroupSetBits + event_groups.o(.ARM.exidx.text.vEventGroupSetBitsCallback) refers to event_groups.o(.text.vEventGroupSetBitsCallback) for [Anonymous Symbol] + event_groups.o(.text.xEventGroupSetBitsFromISR) refers to event_groups.o(.text.vEventGroupSetBitsCallback) for vEventGroupSetBitsCallback + event_groups.o(.text.xEventGroupSetBitsFromISR) refers to timers.o(.text.xTimerPendFunctionCallFromISR) for xTimerPendFunctionCallFromISR + event_groups.o(.ARM.exidx.text.xEventGroupSetBitsFromISR) refers to event_groups.o(.text.xEventGroupSetBitsFromISR) for [Anonymous Symbol] + event_groups.o(.ARM.exidx.text.uxEventGroupGetNumber) refers to event_groups.o(.text.uxEventGroupGetNumber) for [Anonymous Symbol] + event_groups.o(.ARM.exidx.text.vEventGroupSetNumber) refers to event_groups.o(.text.vEventGroupSetNumber) for [Anonymous Symbol] + list.o(.ARM.exidx.text.vListInitialise) refers to list.o(.text.vListInitialise) for [Anonymous Symbol] + list.o(.ARM.exidx.text.vListInitialiseItem) refers to list.o(.text.vListInitialiseItem) for [Anonymous Symbol] + list.o(.ARM.exidx.text.vListInsertEnd) refers to list.o(.text.vListInsertEnd) for [Anonymous Symbol] + list.o(.ARM.exidx.text.vListInsert) refers to list.o(.text.vListInsert) for [Anonymous Symbol] + list.o(.ARM.exidx.text.uxListRemove) refers to list.o(.text.uxListRemove) for [Anonymous Symbol] + queue.o(.text.xQueueGenericReset) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueueGenericReset) refers to list.o(.text.vListInitialise) for vListInitialise + queue.o(.text.xQueueGenericReset) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.text.xQueueGenericReset) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.xQueueGenericReset) refers to queue.o(.text.xQueueGenericReset) for [Anonymous Symbol] + queue.o(.text.xQueueGenericCreateStatic) refers to queue.o(.text.prvInitialiseNewQueue) for prvInitialiseNewQueue + queue.o(.ARM.exidx.text.xQueueGenericCreateStatic) refers to queue.o(.text.xQueueGenericCreateStatic) for [Anonymous Symbol] + queue.o(.text.prvInitialiseNewQueue) refers to queue.o(.text.xQueueGenericReset) for xQueueGenericReset + queue.o(.ARM.exidx.text.prvInitialiseNewQueue) refers to queue.o(.text.prvInitialiseNewQueue) for [Anonymous Symbol] + queue.o(.text.xQueueGenericCreate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + queue.o(.text.xQueueGenericCreate) refers to queue.o(.text.prvInitialiseNewQueue) for prvInitialiseNewQueue + queue.o(.ARM.exidx.text.xQueueGenericCreate) refers to queue.o(.text.xQueueGenericCreate) for [Anonymous Symbol] + queue.o(.text.xQueueCreateMutex) refers to queue.o(.text.xQueueGenericCreate) for xQueueGenericCreate + queue.o(.text.xQueueCreateMutex) refers to queue.o(.text.prvInitialiseMutex) for prvInitialiseMutex + queue.o(.ARM.exidx.text.xQueueCreateMutex) refers to queue.o(.text.xQueueCreateMutex) for [Anonymous Symbol] + queue.o(.text.prvInitialiseMutex) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + queue.o(.ARM.exidx.text.prvInitialiseMutex) refers to queue.o(.text.prvInitialiseMutex) for [Anonymous Symbol] + queue.o(.text.xQueueCreateMutexStatic) refers to queue.o(.text.xQueueGenericCreateStatic) for xQueueGenericCreateStatic + queue.o(.text.xQueueCreateMutexStatic) refers to queue.o(.text.prvInitialiseMutex) for prvInitialiseMutex + queue.o(.ARM.exidx.text.xQueueCreateMutexStatic) refers to queue.o(.text.xQueueCreateMutexStatic) for [Anonymous Symbol] + queue.o(.text.xQueueGetMutexHolder) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueueGetMutexHolder) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.xQueueGetMutexHolder) refers to queue.o(.text.xQueueGetMutexHolder) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.xQueueGetMutexHolderFromISR) refers to queue.o(.text.xQueueGetMutexHolderFromISR) for [Anonymous Symbol] + queue.o(.text.xQueueGiveMutexRecursive) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + queue.o(.text.xQueueGiveMutexRecursive) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + queue.o(.ARM.exidx.text.xQueueGiveMutexRecursive) refers to queue.o(.text.xQueueGiveMutexRecursive) for [Anonymous Symbol] + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + queue.o(.text.xQueueGenericSend) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for vTaskInternalSetTimeOutState + queue.o(.text.xQueueGenericSend) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.xTaskCheckForTimeOut) for xTaskCheckForTimeOut + queue.o(.text.xQueueGenericSend) refers to queue.o(.text.prvIsQueueFull) for prvIsQueueFull + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.vTaskPlaceOnEventList) for vTaskPlaceOnEventList + queue.o(.text.xQueueGenericSend) refers to queue.o(.text.prvUnlockQueue) for prvUnlockQueue + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + queue.o(.text.xQueueGenericSend) refers to queue.o(.text.prvCopyDataToQueue) for prvCopyDataToQueue + queue.o(.text.xQueueGenericSend) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.ARM.exidx.text.xQueueGenericSend) refers to queue.o(.text.xQueueGenericSend) for [Anonymous Symbol] + queue.o(.text.xQueueTakeMutexRecursive) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + queue.o(.text.xQueueTakeMutexRecursive) refers to queue.o(.text.xQueueSemaphoreTake) for xQueueSemaphoreTake + queue.o(.ARM.exidx.text.xQueueTakeMutexRecursive) refers to queue.o(.text.xQueueTakeMutexRecursive) for [Anonymous Symbol] + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + queue.o(.text.xQueueSemaphoreTake) refers to queue.o(.text.prvUnlockQueue) for prvUnlockQueue + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + queue.o(.text.xQueueSemaphoreTake) refers to queue.o(.text.prvIsQueueEmpty) for prvIsQueueEmpty + queue.o(.text.xQueueSemaphoreTake) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.pvTaskIncrementMutexHeldCount) for pvTaskIncrementMutexHeldCount + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.text.xQueueSemaphoreTake) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for vTaskInternalSetTimeOutState + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.xTaskCheckForTimeOut) for xTaskCheckForTimeOut + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.xTaskPriorityInherit) for xTaskPriorityInherit + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.vTaskPlaceOnEventList) for vTaskPlaceOnEventList + queue.o(.text.xQueueSemaphoreTake) refers to queue.o(.text.prvGetDisinheritPriorityAfterTimeout) for prvGetDisinheritPriorityAfterTimeout + queue.o(.text.xQueueSemaphoreTake) refers to tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) for vTaskPriorityDisinheritAfterTimeout + queue.o(.ARM.exidx.text.xQueueSemaphoreTake) refers to queue.o(.text.xQueueSemaphoreTake) for [Anonymous Symbol] + queue.o(.text.xQueueCreateCountingSemaphoreStatic) refers to queue.o(.text.xQueueGenericCreateStatic) for xQueueGenericCreateStatic + queue.o(.ARM.exidx.text.xQueueCreateCountingSemaphoreStatic) refers to queue.o(.text.xQueueCreateCountingSemaphoreStatic) for [Anonymous Symbol] + queue.o(.text.xQueueCreateCountingSemaphore) refers to queue.o(.text.xQueueGenericCreate) for xQueueGenericCreate + queue.o(.ARM.exidx.text.xQueueCreateCountingSemaphore) refers to queue.o(.text.xQueueCreateCountingSemaphore) for [Anonymous Symbol] + queue.o(.text.prvCopyDataToQueue) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + queue.o(.text.prvCopyDataToQueue) refers to tasks.o(.text.xTaskPriorityDisinherit) for xTaskPriorityDisinherit + queue.o(.ARM.exidx.text.prvCopyDataToQueue) refers to queue.o(.text.prvCopyDataToQueue) for [Anonymous Symbol] + queue.o(.text.prvIsQueueFull) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.prvIsQueueFull) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.prvIsQueueFull) refers to queue.o(.text.prvIsQueueFull) for [Anonymous Symbol] + queue.o(.text.prvUnlockQueue) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.prvUnlockQueue) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.text.prvUnlockQueue) refers to tasks.o(.text.vTaskMissedYield) for vTaskMissedYield + queue.o(.text.prvUnlockQueue) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.prvUnlockQueue) refers to queue.o(.text.prvUnlockQueue) for [Anonymous Symbol] + queue.o(.text.xQueueGenericSendFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + queue.o(.text.xQueueGenericSendFromISR) refers to queue.o(.text.prvCopyDataToQueue) for prvCopyDataToQueue + queue.o(.text.xQueueGenericSendFromISR) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.ARM.exidx.text.xQueueGenericSendFromISR) refers to queue.o(.text.xQueueGenericSendFromISR) for [Anonymous Symbol] + queue.o(.text.xQueueGiveFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + queue.o(.text.xQueueGiveFromISR) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.ARM.exidx.text.xQueueGiveFromISR) refers to queue.o(.text.xQueueGiveFromISR) for [Anonymous Symbol] + queue.o(.text.xQueueReceive) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + queue.o(.text.xQueueReceive) refers to queue.o(.text.prvUnlockQueue) for prvUnlockQueue + queue.o(.text.xQueueReceive) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + queue.o(.text.xQueueReceive) refers to queue.o(.text.prvIsQueueEmpty) for prvIsQueueEmpty + queue.o(.text.xQueueReceive) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueueReceive) refers to queue.o(.text.prvCopyDataFromQueue) for prvCopyDataFromQueue + queue.o(.text.xQueueReceive) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.text.xQueueReceive) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.text.xQueueReceive) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for vTaskInternalSetTimeOutState + queue.o(.text.xQueueReceive) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + queue.o(.text.xQueueReceive) refers to tasks.o(.text.xTaskCheckForTimeOut) for xTaskCheckForTimeOut + queue.o(.text.xQueueReceive) refers to tasks.o(.text.vTaskPlaceOnEventList) for vTaskPlaceOnEventList + queue.o(.ARM.exidx.text.xQueueReceive) refers to queue.o(.text.xQueueReceive) for [Anonymous Symbol] + queue.o(.text.prvCopyDataFromQueue) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + queue.o(.ARM.exidx.text.prvCopyDataFromQueue) refers to queue.o(.text.prvCopyDataFromQueue) for [Anonymous Symbol] + queue.o(.text.prvIsQueueEmpty) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.prvIsQueueEmpty) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.prvIsQueueEmpty) refers to queue.o(.text.prvIsQueueEmpty) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.prvGetDisinheritPriorityAfterTimeout) refers to queue.o(.text.prvGetDisinheritPriorityAfterTimeout) for [Anonymous Symbol] + queue.o(.text.xQueuePeek) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + queue.o(.text.xQueuePeek) refers to queue.o(.text.prvUnlockQueue) for prvUnlockQueue + queue.o(.text.xQueuePeek) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + queue.o(.text.xQueuePeek) refers to queue.o(.text.prvIsQueueEmpty) for prvIsQueueEmpty + queue.o(.text.xQueuePeek) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.xQueuePeek) refers to queue.o(.text.prvCopyDataFromQueue) for prvCopyDataFromQueue + queue.o(.text.xQueuePeek) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.text.xQueuePeek) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.text.xQueuePeek) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for vTaskInternalSetTimeOutState + queue.o(.text.xQueuePeek) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + queue.o(.text.xQueuePeek) refers to tasks.o(.text.xTaskCheckForTimeOut) for xTaskCheckForTimeOut + queue.o(.text.xQueuePeek) refers to tasks.o(.text.vTaskPlaceOnEventList) for vTaskPlaceOnEventList + queue.o(.ARM.exidx.text.xQueuePeek) refers to queue.o(.text.xQueuePeek) for [Anonymous Symbol] + queue.o(.text.xQueueReceiveFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + queue.o(.text.xQueueReceiveFromISR) refers to queue.o(.text.prvCopyDataFromQueue) for prvCopyDataFromQueue + queue.o(.text.xQueueReceiveFromISR) refers to tasks.o(.text.xTaskRemoveFromEventList) for xTaskRemoveFromEventList + queue.o(.ARM.exidx.text.xQueueReceiveFromISR) refers to queue.o(.text.xQueueReceiveFromISR) for [Anonymous Symbol] + queue.o(.text.xQueuePeekFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + queue.o(.text.xQueuePeekFromISR) refers to queue.o(.text.prvCopyDataFromQueue) for prvCopyDataFromQueue + queue.o(.ARM.exidx.text.xQueuePeekFromISR) refers to queue.o(.text.xQueuePeekFromISR) for [Anonymous Symbol] + queue.o(.text.uxQueueMessagesWaiting) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.uxQueueMessagesWaiting) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.uxQueueMessagesWaiting) refers to queue.o(.text.uxQueueMessagesWaiting) for [Anonymous Symbol] + queue.o(.text.uxQueueSpacesAvailable) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.uxQueueSpacesAvailable) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.ARM.exidx.text.uxQueueSpacesAvailable) refers to queue.o(.text.uxQueueSpacesAvailable) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.uxQueueMessagesWaitingFromISR) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for [Anonymous Symbol] + queue.o(.text.vQueueDelete) refers to queue.o(.text.vQueueUnregisterQueue) for vQueueUnregisterQueue + queue.o(.text.vQueueDelete) refers to heap_4.o(.text.vPortFree) for vPortFree + queue.o(.ARM.exidx.text.vQueueDelete) refers to queue.o(.text.vQueueDelete) for [Anonymous Symbol] + queue.o(.text.vQueueUnregisterQueue) refers to queue.o(.bss.xQueueRegistry) for xQueueRegistry + queue.o(.ARM.exidx.text.vQueueUnregisterQueue) refers to queue.o(.text.vQueueUnregisterQueue) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.uxQueueGetQueueNumber) refers to queue.o(.text.uxQueueGetQueueNumber) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.vQueueSetQueueNumber) refers to queue.o(.text.vQueueSetQueueNumber) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.ucQueueGetQueueType) refers to queue.o(.text.ucQueueGetQueueType) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.xQueueIsQueueEmptyFromISR) refers to queue.o(.text.xQueueIsQueueEmptyFromISR) for [Anonymous Symbol] + queue.o(.ARM.exidx.text.xQueueIsQueueFullFromISR) refers to queue.o(.text.xQueueIsQueueFullFromISR) for [Anonymous Symbol] + queue.o(.text.vQueueAddToRegistry) refers to queue.o(.bss.xQueueRegistry) for xQueueRegistry + queue.o(.ARM.exidx.text.vQueueAddToRegistry) refers to queue.o(.text.vQueueAddToRegistry) for [Anonymous Symbol] + queue.o(.text.pcQueueGetName) refers to queue.o(.bss.xQueueRegistry) for xQueueRegistry + queue.o(.ARM.exidx.text.pcQueueGetName) refers to queue.o(.text.pcQueueGetName) for [Anonymous Symbol] + queue.o(.text.vQueueWaitForMessageRestricted) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + queue.o(.text.vQueueWaitForMessageRestricted) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + queue.o(.text.vQueueWaitForMessageRestricted) refers to tasks.o(.text.vTaskPlaceOnEventListRestricted) for vTaskPlaceOnEventListRestricted + queue.o(.text.vQueueWaitForMessageRestricted) refers to queue.o(.text.prvUnlockQueue) for prvUnlockQueue + queue.o(.ARM.exidx.text.vQueueWaitForMessageRestricted) refers to queue.o(.text.vQueueWaitForMessageRestricted) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferGenericCreate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + stream_buffer.o(.text.xStreamBufferGenericCreate) refers to stream_buffer.o(.text.prvInitialiseNewStreamBuffer) for prvInitialiseNewStreamBuffer + stream_buffer.o(.ARM.exidx.text.xStreamBufferGenericCreate) refers to stream_buffer.o(.text.xStreamBufferGenericCreate) for [Anonymous Symbol] + stream_buffer.o(.text.prvInitialiseNewStreamBuffer) refers to aeabi_memset.o(.text) for __aeabi_memset + stream_buffer.o(.text.prvInitialiseNewStreamBuffer) refers to rt_memclr.o(.text) for __aeabi_memclr + stream_buffer.o(.ARM.exidx.text.prvInitialiseNewStreamBuffer) refers to stream_buffer.o(.text.prvInitialiseNewStreamBuffer) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferGenericCreateStatic) refers to stream_buffer.o(.text.prvInitialiseNewStreamBuffer) for prvInitialiseNewStreamBuffer + stream_buffer.o(.ARM.exidx.text.xStreamBufferGenericCreateStatic) refers to stream_buffer.o(.text.xStreamBufferGenericCreateStatic) for [Anonymous Symbol] + stream_buffer.o(.text.vStreamBufferDelete) refers to heap_4.o(.text.vPortFree) for vPortFree + stream_buffer.o(.text.vStreamBufferDelete) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + stream_buffer.o(.ARM.exidx.text.vStreamBufferDelete) refers to stream_buffer.o(.text.vStreamBufferDelete) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferReset) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + stream_buffer.o(.text.xStreamBufferReset) refers to stream_buffer.o(.text.prvInitialiseNewStreamBuffer) for prvInitialiseNewStreamBuffer + stream_buffer.o(.text.xStreamBufferReset) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + stream_buffer.o(.ARM.exidx.text.xStreamBufferReset) refers to stream_buffer.o(.text.xStreamBufferReset) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.xStreamBufferSetTriggerLevel) refers to stream_buffer.o(.text.xStreamBufferSetTriggerLevel) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.xStreamBufferSpacesAvailable) refers to stream_buffer.o(.text.xStreamBufferSpacesAvailable) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferBytesAvailable) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.ARM.exidx.text.xStreamBufferBytesAvailable) refers to stream_buffer.o(.text.xStreamBufferBytesAvailable) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.prvBytesInBuffer) refers to stream_buffer.o(.text.prvBytesInBuffer) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.vTaskSetTimeOutState) for vTaskSetTimeOutState + stream_buffer.o(.text.xStreamBufferSend) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + stream_buffer.o(.text.xStreamBufferSend) refers to stream_buffer.o(.text.xStreamBufferSpacesAvailable) for xStreamBufferSpacesAvailable + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskNotifyStateClear) for xTaskNotifyStateClear + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + stream_buffer.o(.text.xStreamBufferSend) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskNotifyWait) for xTaskNotifyWait + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskCheckForTimeOut) for xTaskCheckForTimeOut + stream_buffer.o(.text.xStreamBufferSend) refers to stream_buffer.o(.text.prvWriteMessageToBuffer) for prvWriteMessageToBuffer + stream_buffer.o(.text.xStreamBufferSend) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskGenericNotify) for xTaskGenericNotify + stream_buffer.o(.text.xStreamBufferSend) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + stream_buffer.o(.ARM.exidx.text.xStreamBufferSend) refers to stream_buffer.o(.text.xStreamBufferSend) for [Anonymous Symbol] + stream_buffer.o(.text.prvWriteMessageToBuffer) refers to stream_buffer.o(.text.prvWriteBytesToBuffer) for prvWriteBytesToBuffer + stream_buffer.o(.ARM.exidx.text.prvWriteMessageToBuffer) refers to stream_buffer.o(.text.prvWriteMessageToBuffer) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferSendFromISR) refers to stream_buffer.o(.text.xStreamBufferSpacesAvailable) for xStreamBufferSpacesAvailable + stream_buffer.o(.text.xStreamBufferSendFromISR) refers to stream_buffer.o(.text.prvWriteMessageToBuffer) for prvWriteMessageToBuffer + stream_buffer.o(.text.xStreamBufferSendFromISR) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.text.xStreamBufferSendFromISR) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for xTaskGenericNotifyFromISR + stream_buffer.o(.ARM.exidx.text.xStreamBufferSendFromISR) refers to stream_buffer.o(.text.xStreamBufferSendFromISR) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferReceive) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + stream_buffer.o(.text.xStreamBufferReceive) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.text.xStreamBufferReceive) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.xTaskNotifyStateClear) for xTaskNotifyStateClear + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.xTaskNotifyWait) for xTaskNotifyWait + stream_buffer.o(.text.xStreamBufferReceive) refers to stream_buffer.o(.text.prvReadMessageFromBuffer) for prvReadMessageFromBuffer + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.xTaskGenericNotify) for xTaskGenericNotify + stream_buffer.o(.text.xStreamBufferReceive) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + stream_buffer.o(.ARM.exidx.text.xStreamBufferReceive) refers to stream_buffer.o(.text.xStreamBufferReceive) for [Anonymous Symbol] + stream_buffer.o(.text.prvReadMessageFromBuffer) refers to stream_buffer.o(.text.prvReadBytesFromBuffer) for prvReadBytesFromBuffer + stream_buffer.o(.ARM.exidx.text.prvReadMessageFromBuffer) refers to stream_buffer.o(.text.prvReadMessageFromBuffer) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferNextMessageLengthBytes) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.text.xStreamBufferNextMessageLengthBytes) refers to stream_buffer.o(.text.prvReadBytesFromBuffer) for prvReadBytesFromBuffer + stream_buffer.o(.ARM.exidx.text.xStreamBufferNextMessageLengthBytes) refers to stream_buffer.o(.text.xStreamBufferNextMessageLengthBytes) for [Anonymous Symbol] + stream_buffer.o(.text.prvReadBytesFromBuffer) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + stream_buffer.o(.ARM.exidx.text.prvReadBytesFromBuffer) refers to stream_buffer.o(.text.prvReadBytesFromBuffer) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferReceiveFromISR) refers to stream_buffer.o(.text.prvBytesInBuffer) for prvBytesInBuffer + stream_buffer.o(.text.xStreamBufferReceiveFromISR) refers to stream_buffer.o(.text.prvReadMessageFromBuffer) for prvReadMessageFromBuffer + stream_buffer.o(.text.xStreamBufferReceiveFromISR) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for xTaskGenericNotifyFromISR + stream_buffer.o(.ARM.exidx.text.xStreamBufferReceiveFromISR) refers to stream_buffer.o(.text.xStreamBufferReceiveFromISR) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.xStreamBufferIsEmpty) refers to stream_buffer.o(.text.xStreamBufferIsEmpty) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferIsFull) refers to stream_buffer.o(.text.xStreamBufferSpacesAvailable) for xStreamBufferSpacesAvailable + stream_buffer.o(.ARM.exidx.text.xStreamBufferIsFull) refers to stream_buffer.o(.text.xStreamBufferIsFull) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferSendCompletedFromISR) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for xTaskGenericNotifyFromISR + stream_buffer.o(.ARM.exidx.text.xStreamBufferSendCompletedFromISR) refers to stream_buffer.o(.text.xStreamBufferSendCompletedFromISR) for [Anonymous Symbol] + stream_buffer.o(.text.xStreamBufferReceiveCompletedFromISR) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for xTaskGenericNotifyFromISR + stream_buffer.o(.ARM.exidx.text.xStreamBufferReceiveCompletedFromISR) refers to stream_buffer.o(.text.xStreamBufferReceiveCompletedFromISR) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.uxStreamBufferGetStreamBufferNumber) refers to stream_buffer.o(.text.uxStreamBufferGetStreamBufferNumber) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.vStreamBufferSetStreamBufferNumber) refers to stream_buffer.o(.text.vStreamBufferSetStreamBufferNumber) for [Anonymous Symbol] + stream_buffer.o(.ARM.exidx.text.ucStreamBufferGetStreamBufferType) refers to stream_buffer.o(.text.ucStreamBufferGetStreamBufferType) for [Anonymous Symbol] + stream_buffer.o(.text.prvWriteBytesToBuffer) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + stream_buffer.o(.ARM.exidx.text.prvWriteBytesToBuffer) refers to stream_buffer.o(.text.prvWriteBytesToBuffer) for [Anonymous Symbol] + tasks.o(.text.xTaskCreateStatic) refers to tasks.o(.text.prvInitialiseNewTask) for prvInitialiseNewTask + tasks.o(.text.xTaskCreateStatic) refers to tasks.o(.text.prvAddNewTaskToReadyList) for prvAddNewTaskToReadyList + tasks.o(.ARM.exidx.text.xTaskCreateStatic) refers to tasks.o(.text.xTaskCreateStatic) for [Anonymous Symbol] + tasks.o(.text.prvInitialiseNewTask) refers to aeabi_memset4.o(.text) for __aeabi_memset4 + tasks.o(.text.prvInitialiseNewTask) refers to list.o(.text.vListInitialiseItem) for vListInitialiseItem + tasks.o(.text.prvInitialiseNewTask) refers to port.o(.text.pxPortInitialiseStack) for pxPortInitialiseStack + tasks.o(.ARM.exidx.text.prvInitialiseNewTask) refers to tasks.o(.text.prvInitialiseNewTask) for [Anonymous Symbol] + tasks.o(.text.prvAddNewTaskToReadyList) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.text.prvInitialiseTaskLists) for prvInitialiseTaskLists + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.uxTaskNumber) for uxTaskNumber + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.prvAddNewTaskToReadyList) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.prvAddNewTaskToReadyList) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.prvAddNewTaskToReadyList) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.prvAddNewTaskToReadyList) refers to tasks.o(.text.prvAddNewTaskToReadyList) for [Anonymous Symbol] + tasks.o(.text.xTaskCreate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + tasks.o(.text.xTaskCreate) refers to heap_4.o(.text.vPortFree) for vPortFree + tasks.o(.text.xTaskCreate) refers to tasks.o(.text.prvInitialiseNewTask) for prvInitialiseNewTask + tasks.o(.text.xTaskCreate) refers to tasks.o(.text.prvAddNewTaskToReadyList) for prvAddNewTaskToReadyList + tasks.o(.ARM.exidx.text.xTaskCreate) refers to tasks.o(.text.xTaskCreate) for [Anonymous Symbol] + tasks.o(.text.vTaskDelete) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskDelete) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.uxTaskNumber) for uxTaskNumber + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.vTaskDelete) refers to tasks.o(.text.prvDeleteTCB) for prvDeleteTCB + tasks.o(.text.vTaskDelete) refers to tasks.o(.text.prvResetNextTaskUnblockTime) for prvResetNextTaskUnblockTime + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.xTasksWaitingTermination) for xTasksWaitingTermination + tasks.o(.text.vTaskDelete) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.uxDeletedTasksWaitingCleanUp) for uxDeletedTasksWaitingCleanUp + tasks.o(.text.vTaskDelete) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.vTaskDelete) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.ARM.exidx.text.vTaskDelete) refers to tasks.o(.text.vTaskDelete) for [Anonymous Symbol] + tasks.o(.text.prvDeleteTCB) refers to heap_4.o(.text.vPortFree) for vPortFree + tasks.o(.ARM.exidx.text.prvDeleteTCB) refers to tasks.o(.text.prvDeleteTCB) for [Anonymous Symbol] + tasks.o(.text.prvResetNextTaskUnblockTime) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.prvResetNextTaskUnblockTime) refers to tasks.o(.bss.xNextTaskUnblockTime) for xNextTaskUnblockTime + tasks.o(.ARM.exidx.text.prvResetNextTaskUnblockTime) refers to tasks.o(.text.prvResetNextTaskUnblockTime) for [Anonymous Symbol] + tasks.o(.text.vTaskDelayUntil) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskDelayUntil) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + tasks.o(.text.vTaskDelayUntil) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.vTaskDelayUntil) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.text.vTaskDelayUntil) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + tasks.o(.ARM.exidx.text.vTaskDelayUntil) refers to tasks.o(.text.vTaskDelayUntil) for [Anonymous Symbol] + tasks.o(.text.vTaskSuspendAll) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.ARM.exidx.text.vTaskSuspendAll) refers to tasks.o(.text.vTaskSuspendAll) for [Anonymous Symbol] + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.pxOverflowDelayedTaskList) for pxOverflowDelayedTaskList + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to list.o(.text.vListInsert) for vListInsert + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.bss.xNextTaskUnblockTime) for xNextTaskUnblockTime + tasks.o(.ARM.exidx.text.prvAddCurrentTaskToDelayedList) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for [Anonymous Symbol] + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskResumeAll) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.xTaskResumeAll) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskResumeAll) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskResumeAll) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.text.prvResetNextTaskUnblockTime) for prvResetNextTaskUnblockTime + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.bss.xPendedTicks) for xPendedTicks + tasks.o(.text.xTaskResumeAll) refers to tasks.o(.text.xTaskIncrementTick) for xTaskIncrementTick + tasks.o(.ARM.exidx.text.xTaskResumeAll) refers to tasks.o(.text.xTaskResumeAll) for [Anonymous Symbol] + tasks.o(.text.vTaskDelay) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskDelay) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + tasks.o(.text.vTaskDelay) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.text.vTaskDelay) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + tasks.o(.ARM.exidx.text.vTaskDelay) refers to tasks.o(.text.vTaskDelay) for [Anonymous Symbol] + tasks.o(.text.eTaskGetState) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.eTaskGetState) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.eTaskGetState) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.eTaskGetState) refers to tasks.o(.bss.pxOverflowDelayedTaskList) for pxOverflowDelayedTaskList + tasks.o(.text.eTaskGetState) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.eTaskGetState) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.text.eTaskGetState) refers to tasks.o(.bss.xTasksWaitingTermination) for xTasksWaitingTermination + tasks.o(.ARM.exidx.text.eTaskGetState) refers to tasks.o(.text.eTaskGetState) for [Anonymous Symbol] + tasks.o(.text.uxTaskPriorityGet) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.uxTaskPriorityGet) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.uxTaskPriorityGet) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.uxTaskPriorityGet) refers to tasks.o(.text.uxTaskPriorityGet) for [Anonymous Symbol] + tasks.o(.text.uxTaskPriorityGetFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + tasks.o(.text.uxTaskPriorityGetFromISR) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.uxTaskPriorityGetFromISR) refers to tasks.o(.text.uxTaskPriorityGetFromISR) for [Anonymous Symbol] + tasks.o(.text.vTaskPrioritySet) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.vTaskPrioritySet) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskPrioritySet) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskPrioritySet) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.vTaskPrioritySet) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskPrioritySet) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskPrioritySet) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.ARM.exidx.text.vTaskPrioritySet) refers to tasks.o(.text.vTaskPrioritySet) for [Anonymous Symbol] + tasks.o(.text.vTaskSuspend) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.vTaskSuspend) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskSuspend) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskSuspend) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.text.vTaskSuspend) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskSuspend) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.vTaskSuspend) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.vTaskSuspend) refers to tasks.o(.text.prvResetNextTaskUnblockTime) for prvResetNextTaskUnblockTime + tasks.o(.text.vTaskSuspend) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskSuspend) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.vTaskSuspend) refers to tasks.o(.text.vTaskSwitchContext) for vTaskSwitchContext + tasks.o(.ARM.exidx.text.vTaskSuspend) refers to tasks.o(.text.vTaskSuspend) for [Anonymous Symbol] + tasks.o(.text.vTaskSwitchContext) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskSwitchContext) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.text.vTaskSwitchContext) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskSwitchContext) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskSwitchContext) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.vTaskSwitchContext) refers to tasks.o(.text.vTaskSwitchContext) for [Anonymous Symbol] + tasks.o(.text.vTaskResume) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskResume) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.vTaskResume) refers to tasks.o(.text.prvTaskIsTaskSuspended) for prvTaskIsTaskSuspended + tasks.o(.text.vTaskResume) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskResume) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskResume) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskResume) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskResume) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.vTaskResume) refers to tasks.o(.text.vTaskResume) for [Anonymous Symbol] + tasks.o(.text.prvTaskIsTaskSuspended) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.ARM.exidx.text.prvTaskIsTaskSuspended) refers to tasks.o(.text.prvTaskIsTaskSuspended) for [Anonymous Symbol] + tasks.o(.text.xTaskResumeFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.text.prvTaskIsTaskSuspended) for prvTaskIsTaskSuspended + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.xTaskResumeFromISR) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskResumeFromISR) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskResumeFromISR) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.ARM.exidx.text.xTaskResumeFromISR) refers to tasks.o(.text.xTaskResumeFromISR) for [Anonymous Symbol] + tasks.o(.text.vTaskStartScheduler) refers to cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) for vApplicationGetIdleTaskMemory + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.text.prvIdleTask) for prvIdleTask + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.text.xTaskCreateStatic) for xTaskCreateStatic + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.bss.xIdleTaskHandle) for xIdleTaskHandle + tasks.o(.text.vTaskStartScheduler) refers to timers.o(.text.xTimerCreateTimerTask) for xTimerCreateTimerTask + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.bss.xNextTaskUnblockTime) for xNextTaskUnblockTime + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.vTaskStartScheduler) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.vTaskStartScheduler) refers to port.o(.text.xPortStartScheduler) for xPortStartScheduler + tasks.o(.ARM.exidx.text.vTaskStartScheduler) refers to tasks.o(.text.vTaskStartScheduler) for [Anonymous Symbol] + tasks.o(.text.prvIdleTask) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.prvIdleTask) refers to tasks.o(.text.prvCheckTasksWaitingTermination) for prvCheckTasksWaitingTermination + tasks.o(.ARM.exidx.text.prvIdleTask) refers to tasks.o(.text.prvIdleTask) for [Anonymous Symbol] + tasks.o(.text.vTaskEndScheduler) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.vTaskEndScheduler) refers to port.o(.text.vPortEndScheduler) for vPortEndScheduler + tasks.o(.ARM.exidx.text.vTaskEndScheduler) refers to tasks.o(.text.vTaskEndScheduler) for [Anonymous Symbol] + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.xPendedTicks) for xPendedTicks + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.pxOverflowDelayedTaskList) for pxOverflowDelayedTaskList + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.xNumOfOverflows) for xNumOfOverflows + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.text.prvResetNextTaskUnblockTime) for prvResetNextTaskUnblockTime + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.xNextTaskUnblockTime) for xNextTaskUnblockTime + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskIncrementTick) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskIncrementTick) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskIncrementTick) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.xTaskIncrementTick) refers to tasks.o(.text.xTaskIncrementTick) for [Anonymous Symbol] + tasks.o(.text.xTaskGetTickCount) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.ARM.exidx.text.xTaskGetTickCount) refers to tasks.o(.text.xTaskGetTickCount) for [Anonymous Symbol] + tasks.o(.text.xTaskGetTickCountFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + tasks.o(.text.xTaskGetTickCountFromISR) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.ARM.exidx.text.xTaskGetTickCountFromISR) refers to tasks.o(.text.xTaskGetTickCountFromISR) for [Anonymous Symbol] + tasks.o(.text.uxTaskGetNumberOfTasks) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.ARM.exidx.text.uxTaskGetNumberOfTasks) refers to tasks.o(.text.uxTaskGetNumberOfTasks) for [Anonymous Symbol] + tasks.o(.text.pcTaskGetName) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.pcTaskGetName) refers to tasks.o(.text.pcTaskGetName) for [Anonymous Symbol] + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.text.prvListTasksWithinSingleList) for prvListTasksWithinSingleList + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.pxOverflowDelayedTaskList) for pxOverflowDelayedTaskList + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.xTasksWaitingTermination) for xTasksWaitingTermination + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.text.uxTaskGetSystemState) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + tasks.o(.ARM.exidx.text.uxTaskGetSystemState) refers to tasks.o(.text.uxTaskGetSystemState) for [Anonymous Symbol] + tasks.o(.text.prvListTasksWithinSingleList) refers to tasks.o(.text.vTaskGetInfo) for vTaskGetInfo + tasks.o(.ARM.exidx.text.prvListTasksWithinSingleList) refers to tasks.o(.text.prvListTasksWithinSingleList) for [Anonymous Symbol] + tasks.o(.text.xTaskCatchUpTicks) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskCatchUpTicks) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + tasks.o(.text.xTaskCatchUpTicks) refers to tasks.o(.bss.xPendedTicks) for xPendedTicks + tasks.o(.text.xTaskCatchUpTicks) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + tasks.o(.ARM.exidx.text.xTaskCatchUpTicks) refers to tasks.o(.text.xTaskCatchUpTicks) for [Anonymous Symbol] + tasks.o(.text.vTaskPlaceOnEventList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskPlaceOnEventList) refers to list.o(.text.vListInsert) for vListInsert + tasks.o(.text.vTaskPlaceOnEventList) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.ARM.exidx.text.vTaskPlaceOnEventList) refers to tasks.o(.text.vTaskPlaceOnEventList) for [Anonymous Symbol] + tasks.o(.text.vTaskPlaceOnUnorderedEventList) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskPlaceOnUnorderedEventList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskPlaceOnUnorderedEventList) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskPlaceOnUnorderedEventList) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.ARM.exidx.text.vTaskPlaceOnUnorderedEventList) refers to tasks.o(.text.vTaskPlaceOnUnorderedEventList) for [Anonymous Symbol] + tasks.o(.text.vTaskPlaceOnEventListRestricted) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskPlaceOnEventListRestricted) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskPlaceOnEventListRestricted) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.ARM.exidx.text.vTaskPlaceOnEventListRestricted) refers to tasks.o(.text.vTaskPlaceOnEventListRestricted) for [Anonymous Symbol] + tasks.o(.text.xTaskRemoveFromEventList) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskRemoveFromEventList) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskRemoveFromEventList) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.xTaskRemoveFromEventList) refers to tasks.o(.text.xTaskRemoveFromEventList) for [Anonymous Symbol] + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.vTaskRemoveFromUnorderedEventList) refers to tasks.o(.text.vTaskRemoveFromUnorderedEventList) for [Anonymous Symbol] + tasks.o(.text.vTaskSetTimeOutState) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.vTaskSetTimeOutState) refers to tasks.o(.bss.xNumOfOverflows) for xNumOfOverflows + tasks.o(.text.vTaskSetTimeOutState) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.vTaskSetTimeOutState) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.vTaskSetTimeOutState) refers to tasks.o(.text.vTaskSetTimeOutState) for [Anonymous Symbol] + tasks.o(.text.vTaskInternalSetTimeOutState) refers to tasks.o(.bss.xNumOfOverflows) for xNumOfOverflows + tasks.o(.text.vTaskInternalSetTimeOutState) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.ARM.exidx.text.vTaskInternalSetTimeOutState) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for [Anonymous Symbol] + tasks.o(.text.xTaskCheckForTimeOut) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.xTaskCheckForTimeOut) refers to tasks.o(.bss.xTickCount) for xTickCount + tasks.o(.text.xTaskCheckForTimeOut) refers to tasks.o(.bss.xNumOfOverflows) for xNumOfOverflows + tasks.o(.text.xTaskCheckForTimeOut) refers to tasks.o(.text.vTaskInternalSetTimeOutState) for vTaskInternalSetTimeOutState + tasks.o(.text.xTaskCheckForTimeOut) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.xTaskCheckForTimeOut) refers to tasks.o(.text.xTaskCheckForTimeOut) for [Anonymous Symbol] + tasks.o(.text.vTaskMissedYield) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.vTaskMissedYield) refers to tasks.o(.text.vTaskMissedYield) for [Anonymous Symbol] + tasks.o(.ARM.exidx.text.uxTaskGetTaskNumber) refers to tasks.o(.text.uxTaskGetTaskNumber) for [Anonymous Symbol] + tasks.o(.ARM.exidx.text.vTaskSetTaskNumber) refers to tasks.o(.text.vTaskSetTaskNumber) for [Anonymous Symbol] + tasks.o(.text.vTaskGetInfo) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskGetInfo) refers to tasks.o(.text.eTaskGetState) for eTaskGetState + tasks.o(.text.vTaskGetInfo) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + tasks.o(.text.vTaskGetInfo) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + tasks.o(.text.vTaskGetInfo) refers to tasks.o(.text.prvTaskCheckFreeStackSpace) for prvTaskCheckFreeStackSpace + tasks.o(.ARM.exidx.text.vTaskGetInfo) refers to tasks.o(.text.vTaskGetInfo) for [Anonymous Symbol] + tasks.o(.ARM.exidx.text.prvTaskCheckFreeStackSpace) refers to tasks.o(.text.prvTaskCheckFreeStackSpace) for [Anonymous Symbol] + tasks.o(.text.uxTaskGetStackHighWaterMark) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.uxTaskGetStackHighWaterMark) refers to tasks.o(.text.prvTaskCheckFreeStackSpace) for prvTaskCheckFreeStackSpace + tasks.o(.ARM.exidx.text.uxTaskGetStackHighWaterMark) refers to tasks.o(.text.uxTaskGetStackHighWaterMark) for [Anonymous Symbol] + tasks.o(.text.xTaskGetCurrentTaskHandle) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.xTaskGetCurrentTaskHandle) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for [Anonymous Symbol] + tasks.o(.text.xTaskGetSchedulerState) refers to tasks.o(.bss.xSchedulerRunning) for xSchedulerRunning + tasks.o(.text.xTaskGetSchedulerState) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.ARM.exidx.text.xTaskGetSchedulerState) refers to tasks.o(.text.xTaskGetSchedulerState) for [Anonymous Symbol] + tasks.o(.text.xTaskPriorityInherit) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskPriorityInherit) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskPriorityInherit) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskPriorityInherit) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskPriorityInherit) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.ARM.exidx.text.xTaskPriorityInherit) refers to tasks.o(.text.xTaskPriorityInherit) for [Anonymous Symbol] + tasks.o(.text.xTaskPriorityDisinherit) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskPriorityDisinherit) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskPriorityDisinherit) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskPriorityDisinherit) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskPriorityDisinherit) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.ARM.exidx.text.xTaskPriorityDisinherit) refers to tasks.o(.text.xTaskPriorityDisinherit) for [Anonymous Symbol] + tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.ARM.exidx.text.vTaskPriorityDisinheritAfterTimeout) refers to tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) for [Anonymous Symbol] + tasks.o(.text.uxTaskResetEventItemValue) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.uxTaskResetEventItemValue) refers to tasks.o(.text.uxTaskResetEventItemValue) for [Anonymous Symbol] + tasks.o(.text.pvTaskIncrementMutexHeldCount) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.ARM.exidx.text.pvTaskIncrementMutexHeldCount) refers to tasks.o(.text.pvTaskIncrementMutexHeldCount) for [Anonymous Symbol] + tasks.o(.text.ulTaskNotifyTake) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.ulTaskNotifyTake) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.ulTaskNotifyTake) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.text.ulTaskNotifyTake) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.ulTaskNotifyTake) refers to tasks.o(.text.ulTaskNotifyTake) for [Anonymous Symbol] + tasks.o(.text.xTaskNotifyWait) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.xTaskNotifyWait) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskNotifyWait) refers to tasks.o(.text.prvAddCurrentTaskToDelayedList) for prvAddCurrentTaskToDelayedList + tasks.o(.text.xTaskNotifyWait) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.xTaskNotifyWait) refers to tasks.o(.text.xTaskNotifyWait) for [Anonymous Symbol] + tasks.o(.text.xTaskGenericNotify) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.xTaskGenericNotify) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskGenericNotify) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskGenericNotify) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskGenericNotify) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskGenericNotify) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskGenericNotify) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.xTaskGenericNotify) refers to tasks.o(.text.xTaskGenericNotify) for [Anonymous Symbol] + tasks.o(.text.xTaskGenericNotifyFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.xTaskGenericNotifyFromISR) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.xTaskGenericNotifyFromISR) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskGenericNotifyFromISR) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.xTaskGenericNotifyFromISR) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for [Anonymous Symbol] + tasks.o(.text.vTaskNotifyGiveFromISR) refers to port.o(.text.vPortValidateInterruptPriority) for vPortValidateInterruptPriority + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.uxSchedulerSuspended) for uxSchedulerSuspended + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.vTaskNotifyGiveFromISR) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.uxTopReadyPriority) for uxTopReadyPriority + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.vTaskNotifyGiveFromISR) refers to list.o(.text.vListInsertEnd) for vListInsertEnd + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.vTaskNotifyGiveFromISR) refers to tasks.o(.bss.xYieldPending) for xYieldPending + tasks.o(.ARM.exidx.text.vTaskNotifyGiveFromISR) refers to tasks.o(.text.vTaskNotifyGiveFromISR) for [Anonymous Symbol] + tasks.o(.text.xTaskNotifyStateClear) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.xTaskNotifyStateClear) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.xTaskNotifyStateClear) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.xTaskNotifyStateClear) refers to tasks.o(.text.xTaskNotifyStateClear) for [Anonymous Symbol] + tasks.o(.text.ulTaskNotifyValueClear) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + tasks.o(.text.ulTaskNotifyValueClear) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.ulTaskNotifyValueClear) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.ARM.exidx.text.ulTaskNotifyValueClear) refers to tasks.o(.text.ulTaskNotifyValueClear) for [Anonymous Symbol] + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.pxReadyTasksLists) for pxReadyTasksLists + tasks.o(.text.prvInitialiseTaskLists) refers to list.o(.text.vListInitialise) for vListInitialise + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.xDelayedTaskList1) for xDelayedTaskList1 + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.xDelayedTaskList2) for xDelayedTaskList2 + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.xPendingReadyList) for xPendingReadyList + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.xTasksWaitingTermination) for xTasksWaitingTermination + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.xSuspendedTaskList) for xSuspendedTaskList + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.pxDelayedTaskList) for pxDelayedTaskList + tasks.o(.text.prvInitialiseTaskLists) refers to tasks.o(.bss.pxOverflowDelayedTaskList) for pxOverflowDelayedTaskList + tasks.o(.ARM.exidx.text.prvInitialiseTaskLists) refers to tasks.o(.text.prvInitialiseTaskLists) for [Anonymous Symbol] + tasks.o(.text.prvCheckTasksWaitingTermination) refers to tasks.o(.bss.uxDeletedTasksWaitingCleanUp) for uxDeletedTasksWaitingCleanUp + tasks.o(.text.prvCheckTasksWaitingTermination) refers to tasks.o(.bss.xTasksWaitingTermination) for xTasksWaitingTermination + tasks.o(.text.prvCheckTasksWaitingTermination) refers to tasks.o(.bss.uxCurrentNumberOfTasks) for uxCurrentNumberOfTasks + tasks.o(.text.prvCheckTasksWaitingTermination) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + tasks.o(.text.prvCheckTasksWaitingTermination) refers to list.o(.text.uxListRemove) for uxListRemove + tasks.o(.text.prvCheckTasksWaitingTermination) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + tasks.o(.text.prvCheckTasksWaitingTermination) refers to tasks.o(.text.prvDeleteTCB) for prvDeleteTCB + tasks.o(.ARM.exidx.text.prvCheckTasksWaitingTermination) refers to tasks.o(.text.prvCheckTasksWaitingTermination) for [Anonymous Symbol] + timers.o(.text.xTimerCreateTimerTask) refers to timers.o(.text.prvCheckForValidListAndQueue) for prvCheckForValidListAndQueue + timers.o(.text.xTimerCreateTimerTask) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.xTimerCreateTimerTask) refers to cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) for vApplicationGetTimerTaskMemory + timers.o(.text.xTimerCreateTimerTask) refers to timers.o(.text.prvTimerTask) for prvTimerTask + timers.o(.text.xTimerCreateTimerTask) refers to tasks.o(.text.xTaskCreateStatic) for xTaskCreateStatic + timers.o(.text.xTimerCreateTimerTask) refers to timers.o(.bss.xTimerTaskHandle) for xTimerTaskHandle + timers.o(.ARM.exidx.text.xTimerCreateTimerTask) refers to timers.o(.text.xTimerCreateTimerTask) for [Anonymous Symbol] + timers.o(.text.prvCheckForValidListAndQueue) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.xActiveTimerList1) for xActiveTimerList1 + timers.o(.text.prvCheckForValidListAndQueue) refers to list.o(.text.vListInitialise) for vListInitialise + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.xActiveTimerList2) for xActiveTimerList2 + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.pxCurrentTimerList) for pxCurrentTimerList + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.pxOverflowTimerList) for pxOverflowTimerList + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.prvCheckForValidListAndQueue.ucStaticTimerQueueStorage) for prvCheckForValidListAndQueue.ucStaticTimerQueueStorage + timers.o(.text.prvCheckForValidListAndQueue) refers to timers.o(.bss.prvCheckForValidListAndQueue.xStaticTimerQueue) for prvCheckForValidListAndQueue.xStaticTimerQueue + timers.o(.text.prvCheckForValidListAndQueue) refers to queue.o(.text.xQueueGenericCreateStatic) for xQueueGenericCreateStatic + timers.o(.text.prvCheckForValidListAndQueue) refers to queue.o(.text.vQueueAddToRegistry) for vQueueAddToRegistry + timers.o(.text.prvCheckForValidListAndQueue) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.prvCheckForValidListAndQueue) refers to timers.o(.text.prvCheckForValidListAndQueue) for [Anonymous Symbol] + timers.o(.text.prvTimerTask) refers to timers.o(.text.prvGetNextExpireTime) for prvGetNextExpireTime + timers.o(.text.prvTimerTask) refers to timers.o(.text.prvProcessTimerOrBlockTask) for prvProcessTimerOrBlockTask + timers.o(.text.prvTimerTask) refers to timers.o(.text.prvProcessReceivedCommands) for prvProcessReceivedCommands + timers.o(.ARM.exidx.text.prvTimerTask) refers to timers.o(.text.prvTimerTask) for [Anonymous Symbol] + timers.o(.text.xTimerCreate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + timers.o(.text.xTimerCreate) refers to timers.o(.text.prvInitialiseNewTimer) for prvInitialiseNewTimer + timers.o(.ARM.exidx.text.xTimerCreate) refers to timers.o(.text.xTimerCreate) for [Anonymous Symbol] + timers.o(.text.prvInitialiseNewTimer) refers to timers.o(.text.prvCheckForValidListAndQueue) for prvCheckForValidListAndQueue + timers.o(.text.prvInitialiseNewTimer) refers to list.o(.text.vListInitialiseItem) for vListInitialiseItem + timers.o(.ARM.exidx.text.prvInitialiseNewTimer) refers to timers.o(.text.prvInitialiseNewTimer) for [Anonymous Symbol] + timers.o(.text.xTimerCreateStatic) refers to timers.o(.text.prvInitialiseNewTimer) for prvInitialiseNewTimer + timers.o(.ARM.exidx.text.xTimerCreateStatic) refers to timers.o(.text.xTimerCreateStatic) for [Anonymous Symbol] + timers.o(.text.xTimerGenericCommand) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.xTimerGenericCommand) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + timers.o(.text.xTimerGenericCommand) refers to queue.o(.text.xQueueGenericSendFromISR) for xQueueGenericSendFromISR + timers.o(.text.xTimerGenericCommand) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + timers.o(.ARM.exidx.text.xTimerGenericCommand) refers to timers.o(.text.xTimerGenericCommand) for [Anonymous Symbol] + timers.o(.text.xTimerGetTimerDaemonTaskHandle) refers to timers.o(.bss.xTimerTaskHandle) for xTimerTaskHandle + timers.o(.ARM.exidx.text.xTimerGetTimerDaemonTaskHandle) refers to timers.o(.text.xTimerGetTimerDaemonTaskHandle) for [Anonymous Symbol] + timers.o(.ARM.exidx.text.xTimerGetPeriod) refers to timers.o(.text.xTimerGetPeriod) for [Anonymous Symbol] + timers.o(.text.vTimerSetReloadMode) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.vTimerSetReloadMode) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.vTimerSetReloadMode) refers to timers.o(.text.vTimerSetReloadMode) for [Anonymous Symbol] + timers.o(.text.uxTimerGetReloadMode) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.uxTimerGetReloadMode) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.uxTimerGetReloadMode) refers to timers.o(.text.uxTimerGetReloadMode) for [Anonymous Symbol] + timers.o(.ARM.exidx.text.xTimerGetExpiryTime) refers to timers.o(.text.xTimerGetExpiryTime) for [Anonymous Symbol] + timers.o(.ARM.exidx.text.pcTimerGetName) refers to timers.o(.text.pcTimerGetName) for [Anonymous Symbol] + timers.o(.text.xTimerIsTimerActive) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.xTimerIsTimerActive) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.xTimerIsTimerActive) refers to timers.o(.text.xTimerIsTimerActive) for [Anonymous Symbol] + timers.o(.text.pvTimerGetTimerID) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.pvTimerGetTimerID) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.pvTimerGetTimerID) refers to timers.o(.text.pvTimerGetTimerID) for [Anonymous Symbol] + timers.o(.text.vTimerSetTimerID) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + timers.o(.text.vTimerSetTimerID) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + timers.o(.ARM.exidx.text.vTimerSetTimerID) refers to timers.o(.text.vTimerSetTimerID) for [Anonymous Symbol] + timers.o(.text.xTimerPendFunctionCallFromISR) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.xTimerPendFunctionCallFromISR) refers to queue.o(.text.xQueueGenericSendFromISR) for xQueueGenericSendFromISR + timers.o(.ARM.exidx.text.xTimerPendFunctionCallFromISR) refers to timers.o(.text.xTimerPendFunctionCallFromISR) for [Anonymous Symbol] + timers.o(.text.xTimerPendFunctionCall) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.xTimerPendFunctionCall) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + timers.o(.ARM.exidx.text.xTimerPendFunctionCall) refers to timers.o(.text.xTimerPendFunctionCall) for [Anonymous Symbol] + timers.o(.ARM.exidx.text.uxTimerGetTimerNumber) refers to timers.o(.text.uxTimerGetTimerNumber) for [Anonymous Symbol] + timers.o(.ARM.exidx.text.vTimerSetTimerNumber) refers to timers.o(.text.vTimerSetTimerNumber) for [Anonymous Symbol] + timers.o(.text.prvGetNextExpireTime) refers to timers.o(.bss.pxCurrentTimerList) for pxCurrentTimerList + timers.o(.ARM.exidx.text.prvGetNextExpireTime) refers to timers.o(.text.prvGetNextExpireTime) for [Anonymous Symbol] + timers.o(.text.prvProcessTimerOrBlockTask) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + timers.o(.text.prvProcessTimerOrBlockTask) refers to timers.o(.text.prvSampleTimeNow) for prvSampleTimeNow + timers.o(.text.prvProcessTimerOrBlockTask) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + timers.o(.text.prvProcessTimerOrBlockTask) refers to timers.o(.text.prvProcessExpiredTimer) for prvProcessExpiredTimer + timers.o(.text.prvProcessTimerOrBlockTask) refers to timers.o(.bss.pxOverflowTimerList) for pxOverflowTimerList + timers.o(.text.prvProcessTimerOrBlockTask) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.prvProcessTimerOrBlockTask) refers to queue.o(.text.vQueueWaitForMessageRestricted) for vQueueWaitForMessageRestricted + timers.o(.ARM.exidx.text.prvProcessTimerOrBlockTask) refers to timers.o(.text.prvProcessTimerOrBlockTask) for [Anonymous Symbol] + timers.o(.text.prvProcessReceivedCommands) refers to timers.o(.bss.xTimerQueue) for xTimerQueue + timers.o(.text.prvProcessReceivedCommands) refers to queue.o(.text.xQueueReceive) for xQueueReceive + timers.o(.text.prvProcessReceivedCommands) refers to list.o(.text.uxListRemove) for uxListRemove + timers.o(.text.prvProcessReceivedCommands) refers to timers.o(.text.prvSampleTimeNow) for prvSampleTimeNow + timers.o(.text.prvProcessReceivedCommands) refers to timers.o(.text.prvInsertTimerInActiveList) for prvInsertTimerInActiveList + timers.o(.text.prvProcessReceivedCommands) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + timers.o(.text.prvProcessReceivedCommands) refers to heap_4.o(.text.vPortFree) for vPortFree + timers.o(.ARM.exidx.text.prvProcessReceivedCommands) refers to timers.o(.text.prvProcessReceivedCommands) for [Anonymous Symbol] + timers.o(.text.prvSampleTimeNow) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + timers.o(.text.prvSampleTimeNow) refers to timers.o(.bss.prvSampleTimeNow.xLastTime) for prvSampleTimeNow.xLastTime + timers.o(.text.prvSampleTimeNow) refers to timers.o(.text.prvSwitchTimerLists) for prvSwitchTimerLists + timers.o(.ARM.exidx.text.prvSampleTimeNow) refers to timers.o(.text.prvSampleTimeNow) for [Anonymous Symbol] + timers.o(.text.prvProcessExpiredTimer) refers to timers.o(.bss.pxCurrentTimerList) for pxCurrentTimerList + timers.o(.text.prvProcessExpiredTimer) refers to list.o(.text.uxListRemove) for uxListRemove + timers.o(.text.prvProcessExpiredTimer) refers to timers.o(.text.prvInsertTimerInActiveList) for prvInsertTimerInActiveList + timers.o(.text.prvProcessExpiredTimer) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + timers.o(.ARM.exidx.text.prvProcessExpiredTimer) refers to timers.o(.text.prvProcessExpiredTimer) for [Anonymous Symbol] + timers.o(.text.prvSwitchTimerLists) refers to timers.o(.bss.pxCurrentTimerList) for pxCurrentTimerList + timers.o(.text.prvSwitchTimerLists) refers to list.o(.text.vListInsert) for vListInsert + timers.o(.text.prvSwitchTimerLists) refers to list.o(.text.uxListRemove) for uxListRemove + timers.o(.text.prvSwitchTimerLists) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + timers.o(.text.prvSwitchTimerLists) refers to timers.o(.bss.pxOverflowTimerList) for pxOverflowTimerList + timers.o(.ARM.exidx.text.prvSwitchTimerLists) refers to timers.o(.text.prvSwitchTimerLists) for [Anonymous Symbol] + timers.o(.text.prvInsertTimerInActiveList) refers to timers.o(.bss.pxCurrentTimerList) for pxCurrentTimerList + timers.o(.text.prvInsertTimerInActiveList) refers to timers.o(.bss.pxOverflowTimerList) for pxOverflowTimerList + timers.o(.text.prvInsertTimerInActiveList) refers to list.o(.text.vListInsert) for vListInsert + timers.o(.ARM.exidx.text.prvInsertTimerInActiveList) refers to timers.o(.text.prvInsertTimerInActiveList) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelInitialize) refers to cmsis_os2.o(.bss.KernelState) for KernelState + cmsis_os2.o(.ARM.exidx.text.osKernelInitialize) refers to cmsis_os2.o(.text.osKernelInitialize) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelGetInfo) refers to cmsis_os2.o(.rodata.str1.4) for .L.str + cmsis_os2.o(.text.osKernelGetInfo) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + cmsis_os2.o(.ARM.exidx.text.osKernelGetInfo) refers to cmsis_os2.o(.text.osKernelGetInfo) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelGetState) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + cmsis_os2.o(.text.osKernelGetState) refers to cmsis_os2.o(.bss.KernelState) for KernelState + cmsis_os2.o(.ARM.exidx.text.osKernelGetState) refers to cmsis_os2.o(.text.osKernelGetState) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelStart) refers to cmsis_os2.o(.bss.KernelState) for KernelState + cmsis_os2.o(.text.osKernelStart) refers to cmsis_os2.o(.text.SVC_Setup) for SVC_Setup + cmsis_os2.o(.text.osKernelStart) refers to tasks.o(.text.vTaskStartScheduler) for vTaskStartScheduler + cmsis_os2.o(.ARM.exidx.text.osKernelStart) refers to cmsis_os2.o(.text.osKernelStart) for [Anonymous Symbol] + cmsis_os2.o(.text.SVC_Setup) refers to cmsis_os2.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + cmsis_os2.o(.ARM.exidx.text.SVC_Setup) refers to cmsis_os2.o(.text.SVC_Setup) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelLock) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + cmsis_os2.o(.text.osKernelLock) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + cmsis_os2.o(.ARM.exidx.text.osKernelLock) refers to cmsis_os2.o(.text.osKernelLock) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelUnlock) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + cmsis_os2.o(.text.osKernelUnlock) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + cmsis_os2.o(.ARM.exidx.text.osKernelUnlock) refers to cmsis_os2.o(.text.osKernelUnlock) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelRestoreLock) refers to tasks.o(.text.xTaskGetSchedulerState) for xTaskGetSchedulerState + cmsis_os2.o(.text.osKernelRestoreLock) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + cmsis_os2.o(.text.osKernelRestoreLock) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + cmsis_os2.o(.ARM.exidx.text.osKernelRestoreLock) refers to cmsis_os2.o(.text.osKernelRestoreLock) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelGetTickCount) refers to tasks.o(.text.xTaskGetTickCountFromISR) for xTaskGetTickCountFromISR + cmsis_os2.o(.text.osKernelGetTickCount) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + cmsis_os2.o(.ARM.exidx.text.osKernelGetTickCount) refers to cmsis_os2.o(.text.osKernelGetTickCount) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osKernelGetTickFreq) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelGetSysTimerCount) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + cmsis_os2.o(.text.osKernelGetSysTimerCount) refers to cmsis_os2.o(.text.OS_Tick_GetCount) for OS_Tick_GetCount + cmsis_os2.o(.text.osKernelGetSysTimerCount) refers to cmsis_os2.o(.text.OS_Tick_GetOverflow) for OS_Tick_GetOverflow + cmsis_os2.o(.text.osKernelGetSysTimerCount) refers to cmsis_os2.o(.text.OS_Tick_GetInterval) for OS_Tick_GetInterval + cmsis_os2.o(.ARM.exidx.text.osKernelGetSysTimerCount) refers to cmsis_os2.o(.text.osKernelGetSysTimerCount) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetCount) refers to cmsis_os2.o(.text.OS_Tick_GetCount) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetOverflow) refers to cmsis_os2.o(.text.OS_Tick_GetOverflow) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetInterval) refers to cmsis_os2.o(.text.OS_Tick_GetInterval) for [Anonymous Symbol] + cmsis_os2.o(.text.osKernelGetSysTimerFreq) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + cmsis_os2.o(.ARM.exidx.text.osKernelGetSysTimerFreq) refers to cmsis_os2.o(.text.osKernelGetSysTimerFreq) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadNew) refers to tasks.o(.text.xTaskCreateStatic) for xTaskCreateStatic + cmsis_os2.o(.text.osThreadNew) refers to tasks.o(.text.xTaskCreate) for xTaskCreate + cmsis_os2.o(.ARM.exidx.text.osThreadNew) refers to cmsis_os2.o(.text.osThreadNew) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetName) refers to tasks.o(.text.pcTaskGetName) for pcTaskGetName + cmsis_os2.o(.ARM.exidx.text.osThreadGetName) refers to cmsis_os2.o(.text.osThreadGetName) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetId) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + cmsis_os2.o(.ARM.exidx.text.osThreadGetId) refers to cmsis_os2.o(.text.osThreadGetId) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetState) refers to tasks.o(.text.eTaskGetState) for eTaskGetState + cmsis_os2.o(.ARM.exidx.text.osThreadGetState) refers to cmsis_os2.o(.text.osThreadGetState) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetStackSpace) refers to tasks.o(.text.uxTaskGetStackHighWaterMark) for uxTaskGetStackHighWaterMark + cmsis_os2.o(.ARM.exidx.text.osThreadGetStackSpace) refers to cmsis_os2.o(.text.osThreadGetStackSpace) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadSetPriority) refers to tasks.o(.text.vTaskPrioritySet) for vTaskPrioritySet + cmsis_os2.o(.ARM.exidx.text.osThreadSetPriority) refers to cmsis_os2.o(.text.osThreadSetPriority) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetPriority) refers to tasks.o(.text.uxTaskPriorityGet) for uxTaskPriorityGet + cmsis_os2.o(.ARM.exidx.text.osThreadGetPriority) refers to cmsis_os2.o(.text.osThreadGetPriority) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osThreadYield) refers to cmsis_os2.o(.text.osThreadYield) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadSuspend) refers to tasks.o(.text.vTaskSuspend) for vTaskSuspend + cmsis_os2.o(.ARM.exidx.text.osThreadSuspend) refers to cmsis_os2.o(.text.osThreadSuspend) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadResume) refers to tasks.o(.text.vTaskResume) for vTaskResume + cmsis_os2.o(.ARM.exidx.text.osThreadResume) refers to cmsis_os2.o(.text.osThreadResume) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadExit) refers to tasks.o(.text.vTaskDelete) for vTaskDelete + cmsis_os2.o(.ARM.exidx.text.osThreadExit) refers to cmsis_os2.o(.text.osThreadExit) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadTerminate) refers to tasks.o(.text.eTaskGetState) for eTaskGetState + cmsis_os2.o(.text.osThreadTerminate) refers to tasks.o(.text.vTaskDelete) for vTaskDelete + cmsis_os2.o(.ARM.exidx.text.osThreadTerminate) refers to cmsis_os2.o(.text.osThreadTerminate) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadGetCount) refers to tasks.o(.text.uxTaskGetNumberOfTasks) for uxTaskGetNumberOfTasks + cmsis_os2.o(.ARM.exidx.text.osThreadGetCount) refers to cmsis_os2.o(.text.osThreadGetCount) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadEnumerate) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + cmsis_os2.o(.text.osThreadEnumerate) refers to tasks.o(.text.uxTaskGetNumberOfTasks) for uxTaskGetNumberOfTasks + cmsis_os2.o(.text.osThreadEnumerate) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + cmsis_os2.o(.text.osThreadEnumerate) refers to tasks.o(.text.uxTaskGetSystemState) for uxTaskGetSystemState + cmsis_os2.o(.text.osThreadEnumerate) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + cmsis_os2.o(.text.osThreadEnumerate) refers to heap_4.o(.text.vPortFree) for vPortFree + cmsis_os2.o(.ARM.exidx.text.osThreadEnumerate) refers to cmsis_os2.o(.text.osThreadEnumerate) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadFlagsSet) refers to tasks.o(.text.xTaskGenericNotifyFromISR) for xTaskGenericNotifyFromISR + cmsis_os2.o(.text.osThreadFlagsSet) refers to tasks.o(.text.xTaskGenericNotify) for xTaskGenericNotify + cmsis_os2.o(.ARM.exidx.text.osThreadFlagsSet) refers to cmsis_os2.o(.text.osThreadFlagsSet) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadFlagsClear) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + cmsis_os2.o(.text.osThreadFlagsClear) refers to tasks.o(.text.xTaskGenericNotify) for xTaskGenericNotify + cmsis_os2.o(.ARM.exidx.text.osThreadFlagsClear) refers to cmsis_os2.o(.text.osThreadFlagsClear) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadFlagsGet) refers to tasks.o(.text.xTaskGetCurrentTaskHandle) for xTaskGetCurrentTaskHandle + cmsis_os2.o(.text.osThreadFlagsGet) refers to tasks.o(.text.xTaskGenericNotify) for xTaskGenericNotify + cmsis_os2.o(.ARM.exidx.text.osThreadFlagsGet) refers to cmsis_os2.o(.text.osThreadFlagsGet) for [Anonymous Symbol] + cmsis_os2.o(.text.osThreadFlagsWait) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + cmsis_os2.o(.text.osThreadFlagsWait) refers to tasks.o(.text.xTaskNotifyWait) for xTaskNotifyWait + cmsis_os2.o(.ARM.exidx.text.osThreadFlagsWait) refers to cmsis_os2.o(.text.osThreadFlagsWait) for [Anonymous Symbol] + cmsis_os2.o(.text.osDelay) refers to tasks.o(.text.vTaskDelay) for vTaskDelay + cmsis_os2.o(.ARM.exidx.text.osDelay) refers to cmsis_os2.o(.text.osDelay) for [Anonymous Symbol] + cmsis_os2.o(.text.osDelayUntil) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + cmsis_os2.o(.text.osDelayUntil) refers to tasks.o(.text.vTaskDelayUntil) for vTaskDelayUntil + cmsis_os2.o(.ARM.exidx.text.osDelayUntil) refers to cmsis_os2.o(.text.osDelayUntil) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerNew) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + cmsis_os2.o(.text.osTimerNew) refers to cmsis_os2.o(.text.TimerCallback) for TimerCallback + cmsis_os2.o(.text.osTimerNew) refers to timers.o(.text.xTimerCreateStatic) for xTimerCreateStatic + cmsis_os2.o(.text.osTimerNew) refers to timers.o(.text.xTimerCreate) for xTimerCreate + cmsis_os2.o(.text.osTimerNew) refers to heap_4.o(.text.vPortFree) for vPortFree + cmsis_os2.o(.ARM.exidx.text.osTimerNew) refers to cmsis_os2.o(.text.osTimerNew) for [Anonymous Symbol] + cmsis_os2.o(.text.TimerCallback) refers to timers.o(.text.pvTimerGetTimerID) for pvTimerGetTimerID + cmsis_os2.o(.ARM.exidx.text.TimerCallback) refers to cmsis_os2.o(.text.TimerCallback) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerGetName) refers to timers.o(.text.pcTimerGetName) for pcTimerGetName + cmsis_os2.o(.ARM.exidx.text.osTimerGetName) refers to cmsis_os2.o(.text.osTimerGetName) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerStart) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + cmsis_os2.o(.ARM.exidx.text.osTimerStart) refers to cmsis_os2.o(.text.osTimerStart) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerStop) refers to timers.o(.text.xTimerIsTimerActive) for xTimerIsTimerActive + cmsis_os2.o(.text.osTimerStop) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + cmsis_os2.o(.ARM.exidx.text.osTimerStop) refers to cmsis_os2.o(.text.osTimerStop) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerIsRunning) refers to timers.o(.text.xTimerIsTimerActive) for xTimerIsTimerActive + cmsis_os2.o(.ARM.exidx.text.osTimerIsRunning) refers to cmsis_os2.o(.text.osTimerIsRunning) for [Anonymous Symbol] + cmsis_os2.o(.text.osTimerDelete) refers to timers.o(.text.pvTimerGetTimerID) for pvTimerGetTimerID + cmsis_os2.o(.text.osTimerDelete) refers to timers.o(.text.xTimerGenericCommand) for xTimerGenericCommand + cmsis_os2.o(.text.osTimerDelete) refers to heap_4.o(.text.vPortFree) for vPortFree + cmsis_os2.o(.ARM.exidx.text.osTimerDelete) refers to cmsis_os2.o(.text.osTimerDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsNew) refers to event_groups.o(.text.xEventGroupCreateStatic) for xEventGroupCreateStatic + cmsis_os2.o(.text.osEventFlagsNew) refers to event_groups.o(.text.xEventGroupCreate) for xEventGroupCreate + cmsis_os2.o(.ARM.exidx.text.osEventFlagsNew) refers to cmsis_os2.o(.text.osEventFlagsNew) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsSet) refers to event_groups.o(.text.xEventGroupSetBitsFromISR) for xEventGroupSetBitsFromISR + cmsis_os2.o(.text.osEventFlagsSet) refers to event_groups.o(.text.xEventGroupSetBits) for xEventGroupSetBits + cmsis_os2.o(.ARM.exidx.text.osEventFlagsSet) refers to cmsis_os2.o(.text.osEventFlagsSet) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsClear) refers to event_groups.o(.text.xEventGroupGetBitsFromISR) for xEventGroupGetBitsFromISR + cmsis_os2.o(.text.osEventFlagsClear) refers to event_groups.o(.text.xEventGroupClearBitsFromISR) for xEventGroupClearBitsFromISR + cmsis_os2.o(.text.osEventFlagsClear) refers to event_groups.o(.text.xEventGroupClearBits) for xEventGroupClearBits + cmsis_os2.o(.ARM.exidx.text.osEventFlagsClear) refers to cmsis_os2.o(.text.osEventFlagsClear) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsGet) refers to event_groups.o(.text.xEventGroupGetBitsFromISR) for xEventGroupGetBitsFromISR + cmsis_os2.o(.text.osEventFlagsGet) refers to event_groups.o(.text.xEventGroupClearBits) for xEventGroupClearBits + cmsis_os2.o(.ARM.exidx.text.osEventFlagsGet) refers to cmsis_os2.o(.text.osEventFlagsGet) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsWait) refers to event_groups.o(.text.xEventGroupWaitBits) for xEventGroupWaitBits + cmsis_os2.o(.ARM.exidx.text.osEventFlagsWait) refers to cmsis_os2.o(.text.osEventFlagsWait) for [Anonymous Symbol] + cmsis_os2.o(.text.osEventFlagsDelete) refers to event_groups.o(.text.vEventGroupDelete) for vEventGroupDelete + cmsis_os2.o(.ARM.exidx.text.osEventFlagsDelete) refers to cmsis_os2.o(.text.osEventFlagsDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.osMutexNew) refers to queue.o(.text.xQueueCreateMutexStatic) for xQueueCreateMutexStatic + cmsis_os2.o(.text.osMutexNew) refers to queue.o(.text.xQueueCreateMutex) for xQueueCreateMutex + cmsis_os2.o(.text.osMutexNew) refers to queue.o(.text.vQueueAddToRegistry) for vQueueAddToRegistry + cmsis_os2.o(.ARM.exidx.text.osMutexNew) refers to cmsis_os2.o(.text.osMutexNew) for [Anonymous Symbol] + cmsis_os2.o(.text.osMutexAcquire) refers to queue.o(.text.xQueueSemaphoreTake) for xQueueSemaphoreTake + cmsis_os2.o(.text.osMutexAcquire) refers to queue.o(.text.xQueueTakeMutexRecursive) for xQueueTakeMutexRecursive + cmsis_os2.o(.ARM.exidx.text.osMutexAcquire) refers to cmsis_os2.o(.text.osMutexAcquire) for [Anonymous Symbol] + cmsis_os2.o(.text.osMutexRelease) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.text.osMutexRelease) refers to queue.o(.text.xQueueGiveMutexRecursive) for xQueueGiveMutexRecursive + cmsis_os2.o(.ARM.exidx.text.osMutexRelease) refers to cmsis_os2.o(.text.osMutexRelease) for [Anonymous Symbol] + cmsis_os2.o(.text.osMutexGetOwner) refers to queue.o(.text.xQueueGetMutexHolder) for xQueueGetMutexHolder + cmsis_os2.o(.ARM.exidx.text.osMutexGetOwner) refers to cmsis_os2.o(.text.osMutexGetOwner) for [Anonymous Symbol] + cmsis_os2.o(.text.osMutexDelete) refers to queue.o(.text.vQueueUnregisterQueue) for vQueueUnregisterQueue + cmsis_os2.o(.text.osMutexDelete) refers to queue.o(.text.vQueueDelete) for vQueueDelete + cmsis_os2.o(.ARM.exidx.text.osMutexDelete) refers to cmsis_os2.o(.text.osMutexDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.xQueueGenericCreateStatic) for xQueueGenericCreateStatic + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.xQueueCreateCountingSemaphoreStatic) for xQueueCreateCountingSemaphoreStatic + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.xQueueGenericCreate) for xQueueGenericCreate + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.vQueueDelete) for vQueueDelete + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.xQueueCreateCountingSemaphore) for xQueueCreateCountingSemaphore + cmsis_os2.o(.text.osSemaphoreNew) refers to queue.o(.text.vQueueAddToRegistry) for vQueueAddToRegistry + cmsis_os2.o(.ARM.exidx.text.osSemaphoreNew) refers to cmsis_os2.o(.text.osSemaphoreNew) for [Anonymous Symbol] + cmsis_os2.o(.text.osSemaphoreAcquire) refers to queue.o(.text.xQueueSemaphoreTake) for xQueueSemaphoreTake + cmsis_os2.o(.text.osSemaphoreAcquire) refers to queue.o(.text.xQueueReceiveFromISR) for xQueueReceiveFromISR + cmsis_os2.o(.ARM.exidx.text.osSemaphoreAcquire) refers to cmsis_os2.o(.text.osSemaphoreAcquire) for [Anonymous Symbol] + cmsis_os2.o(.text.osSemaphoreRelease) refers to queue.o(.text.xQueueGiveFromISR) for xQueueGiveFromISR + cmsis_os2.o(.text.osSemaphoreRelease) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.ARM.exidx.text.osSemaphoreRelease) refers to cmsis_os2.o(.text.osSemaphoreRelease) for [Anonymous Symbol] + cmsis_os2.o(.text.osSemaphoreGetCount) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for uxQueueMessagesWaitingFromISR + cmsis_os2.o(.text.osSemaphoreGetCount) refers to queue.o(.text.uxQueueMessagesWaiting) for uxQueueMessagesWaiting + cmsis_os2.o(.ARM.exidx.text.osSemaphoreGetCount) refers to cmsis_os2.o(.text.osSemaphoreGetCount) for [Anonymous Symbol] + cmsis_os2.o(.text.osSemaphoreDelete) refers to queue.o(.text.vQueueUnregisterQueue) for vQueueUnregisterQueue + cmsis_os2.o(.text.osSemaphoreDelete) refers to queue.o(.text.vQueueDelete) for vQueueDelete + cmsis_os2.o(.ARM.exidx.text.osSemaphoreDelete) refers to cmsis_os2.o(.text.osSemaphoreDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueNew) refers to queue.o(.text.xQueueGenericCreate) for xQueueGenericCreate + cmsis_os2.o(.text.osMessageQueueNew) refers to queue.o(.text.xQueueGenericCreateStatic) for xQueueGenericCreateStatic + cmsis_os2.o(.text.osMessageQueueNew) refers to queue.o(.text.vQueueAddToRegistry) for vQueueAddToRegistry + cmsis_os2.o(.ARM.exidx.text.osMessageQueueNew) refers to cmsis_os2.o(.text.osMessageQueueNew) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueuePut) refers to queue.o(.text.xQueueGenericSendFromISR) for xQueueGenericSendFromISR + cmsis_os2.o(.text.osMessageQueuePut) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.ARM.exidx.text.osMessageQueuePut) refers to cmsis_os2.o(.text.osMessageQueuePut) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueGet) refers to queue.o(.text.xQueueReceiveFromISR) for xQueueReceiveFromISR + cmsis_os2.o(.text.osMessageQueueGet) refers to queue.o(.text.xQueueReceive) for xQueueReceive + cmsis_os2.o(.ARM.exidx.text.osMessageQueueGet) refers to cmsis_os2.o(.text.osMessageQueueGet) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetCapacity) refers to cmsis_os2.o(.text.osMessageQueueGetCapacity) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetMsgSize) refers to cmsis_os2.o(.text.osMessageQueueGetMsgSize) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueGetCount) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for uxQueueMessagesWaitingFromISR + cmsis_os2.o(.text.osMessageQueueGetCount) refers to queue.o(.text.uxQueueMessagesWaiting) for uxQueueMessagesWaiting + cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetCount) refers to cmsis_os2.o(.text.osMessageQueueGetCount) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueGetSpace) refers to queue.o(.text.uxQueueSpacesAvailable) for uxQueueSpacesAvailable + cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetSpace) refers to cmsis_os2.o(.text.osMessageQueueGetSpace) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueReset) refers to queue.o(.text.xQueueGenericReset) for xQueueGenericReset + cmsis_os2.o(.ARM.exidx.text.osMessageQueueReset) refers to cmsis_os2.o(.text.osMessageQueueReset) for [Anonymous Symbol] + cmsis_os2.o(.text.osMessageQueueDelete) refers to queue.o(.text.vQueueUnregisterQueue) for vQueueUnregisterQueue + cmsis_os2.o(.text.osMessageQueueDelete) refers to queue.o(.text.vQueueDelete) for vQueueDelete + cmsis_os2.o(.ARM.exidx.text.osMessageQueueDelete) refers to cmsis_os2.o(.text.osMessageQueueDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolNew) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + cmsis_os2.o(.text.osMemoryPoolNew) refers to queue.o(.text.xQueueCreateCountingSemaphoreStatic) for xQueueCreateCountingSemaphoreStatic + cmsis_os2.o(.text.osMemoryPoolNew) refers to heap_4.o(.text.vPortFree) for vPortFree + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolNew) refers to cmsis_os2.o(.text.osMemoryPoolNew) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetName) refers to cmsis_os2.o(.text.osMemoryPoolGetName) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to queue.o(.text.xQueueReceiveFromISR) for xQueueReceiveFromISR + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to cmsis_os2.o(.text.AllocBlock) for AllocBlock + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to cmsis_os2.o(.text.CreateBlock) for CreateBlock + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to queue.o(.text.xQueueSemaphoreTake) for xQueueSemaphoreTake + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + cmsis_os2.o(.text.osMemoryPoolAlloc) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolAlloc) refers to cmsis_os2.o(.text.osMemoryPoolAlloc) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.AllocBlock) refers to cmsis_os2.o(.text.AllocBlock) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.CreateBlock) refers to cmsis_os2.o(.text.CreateBlock) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolFree) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for uxQueueMessagesWaitingFromISR + cmsis_os2.o(.text.osMemoryPoolFree) refers to queue.o(.text.uxQueueMessagesWaiting) for uxQueueMessagesWaiting + cmsis_os2.o(.text.osMemoryPoolFree) refers to cmsis_os2.o(.text.FreeBlock) for FreeBlock + cmsis_os2.o(.text.osMemoryPoolFree) refers to queue.o(.text.xQueueGiveFromISR) for xQueueGiveFromISR + cmsis_os2.o(.text.osMemoryPoolFree) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + cmsis_os2.o(.text.osMemoryPoolFree) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + cmsis_os2.o(.text.osMemoryPoolFree) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolFree) refers to cmsis_os2.o(.text.osMemoryPoolFree) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.FreeBlock) refers to cmsis_os2.o(.text.FreeBlock) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetCapacity) refers to cmsis_os2.o(.text.osMemoryPoolGetCapacity) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetBlockSize) refers to cmsis_os2.o(.text.osMemoryPoolGetBlockSize) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolGetCount) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for uxQueueMessagesWaitingFromISR + cmsis_os2.o(.text.osMemoryPoolGetCount) refers to queue.o(.text.uxQueueMessagesWaiting) for uxQueueMessagesWaiting + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetCount) refers to cmsis_os2.o(.text.osMemoryPoolGetCount) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolGetSpace) refers to queue.o(.text.uxQueueMessagesWaitingFromISR) for uxQueueMessagesWaitingFromISR + cmsis_os2.o(.text.osMemoryPoolGetSpace) refers to queue.o(.text.uxQueueMessagesWaiting) for uxQueueMessagesWaiting + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetSpace) refers to cmsis_os2.o(.text.osMemoryPoolGetSpace) for [Anonymous Symbol] + cmsis_os2.o(.text.osMemoryPoolDelete) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + cmsis_os2.o(.text.osMemoryPoolDelete) refers to queue.o(.text.xQueueGenericSend) for xQueueGenericSend + cmsis_os2.o(.text.osMemoryPoolDelete) refers to heap_4.o(.text.vPortFree) for vPortFree + cmsis_os2.o(.text.osMemoryPoolDelete) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + cmsis_os2.o(.ARM.exidx.text.osMemoryPoolDelete) refers to cmsis_os2.o(.text.osMemoryPoolDelete) for [Anonymous Symbol] + cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) refers to cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_TCB) for vApplicationGetIdleTaskMemory.Idle_TCB + cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) refers to cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_Stack) for vApplicationGetIdleTaskMemory.Idle_Stack + cmsis_os2.o(.ARM.exidx.text.vApplicationGetIdleTaskMemory) refers to cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) for [Anonymous Symbol] + cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) refers to cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_TCB) for vApplicationGetTimerTaskMemory.Timer_TCB + cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) refers to cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_Stack) for vApplicationGetTimerTaskMemory.Timer_Stack + cmsis_os2.o(.ARM.exidx.text.vApplicationGetTimerTaskMemory) refers to cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) for [Anonymous Symbol] + cmsis_os2.o(.ARM.exidx.text.__NVIC_SetPriority) refers to cmsis_os2.o(.text.__NVIC_SetPriority) for [Anonymous Symbol] + heap_4.o(.text.pvPortMalloc) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.pxEnd) for pxEnd + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.text.prvHeapInit) for prvHeapInit + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.xBlockAllocatedBit) for xBlockAllocatedBit + heap_4.o(.text.pvPortMalloc) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.xFreeBytesRemaining) for xFreeBytesRemaining + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.xStart) for xStart + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.text.prvInsertBlockIntoFreeList) for prvInsertBlockIntoFreeList + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.xMinimumEverFreeBytesRemaining) for xMinimumEverFreeBytesRemaining + heap_4.o(.text.pvPortMalloc) refers to heap_4.o(.bss.xNumberOfSuccessfulAllocations) for xNumberOfSuccessfulAllocations + heap_4.o(.ARM.exidx.text.pvPortMalloc) refers to heap_4.o(.text.pvPortMalloc) for [Anonymous Symbol] + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.ucHeap) for ucHeap + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.xStart) for xStart + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.pxEnd) for pxEnd + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.xMinimumEverFreeBytesRemaining) for xMinimumEverFreeBytesRemaining + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.xFreeBytesRemaining) for xFreeBytesRemaining + heap_4.o(.text.prvHeapInit) refers to heap_4.o(.bss.xBlockAllocatedBit) for xBlockAllocatedBit + heap_4.o(.ARM.exidx.text.prvHeapInit) refers to heap_4.o(.text.prvHeapInit) for [Anonymous Symbol] + heap_4.o(.text.prvInsertBlockIntoFreeList) refers to heap_4.o(.bss.xStart) for xStart + heap_4.o(.text.prvInsertBlockIntoFreeList) refers to heap_4.o(.bss.pxEnd) for pxEnd + heap_4.o(.ARM.exidx.text.prvInsertBlockIntoFreeList) refers to heap_4.o(.text.prvInsertBlockIntoFreeList) for [Anonymous Symbol] + heap_4.o(.text.vPortFree) refers to heap_4.o(.bss.xBlockAllocatedBit) for xBlockAllocatedBit + heap_4.o(.text.vPortFree) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + heap_4.o(.text.vPortFree) refers to heap_4.o(.bss.xFreeBytesRemaining) for xFreeBytesRemaining + heap_4.o(.text.vPortFree) refers to heap_4.o(.text.prvInsertBlockIntoFreeList) for prvInsertBlockIntoFreeList + heap_4.o(.text.vPortFree) refers to heap_4.o(.bss.xNumberOfSuccessfulFrees) for xNumberOfSuccessfulFrees + heap_4.o(.text.vPortFree) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + heap_4.o(.ARM.exidx.text.vPortFree) refers to heap_4.o(.text.vPortFree) for [Anonymous Symbol] + heap_4.o(.text.xPortGetFreeHeapSize) refers to heap_4.o(.bss.xFreeBytesRemaining) for xFreeBytesRemaining + heap_4.o(.ARM.exidx.text.xPortGetFreeHeapSize) refers to heap_4.o(.text.xPortGetFreeHeapSize) for [Anonymous Symbol] + heap_4.o(.text.xPortGetMinimumEverFreeHeapSize) refers to heap_4.o(.bss.xMinimumEverFreeBytesRemaining) for xMinimumEverFreeBytesRemaining + heap_4.o(.ARM.exidx.text.xPortGetMinimumEverFreeHeapSize) refers to heap_4.o(.text.xPortGetMinimumEverFreeHeapSize) for [Anonymous Symbol] + heap_4.o(.ARM.exidx.text.vPortInitialiseBlocks) refers to heap_4.o(.text.vPortInitialiseBlocks) for [Anonymous Symbol] + heap_4.o(.text.vPortGetHeapStats) refers to tasks.o(.text.vTaskSuspendAll) for vTaskSuspendAll + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.xStart) for xStart + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.pxEnd) for pxEnd + heap_4.o(.text.vPortGetHeapStats) refers to tasks.o(.text.xTaskResumeAll) for xTaskResumeAll + heap_4.o(.text.vPortGetHeapStats) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.xFreeBytesRemaining) for xFreeBytesRemaining + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.xMinimumEverFreeBytesRemaining) for xMinimumEverFreeBytesRemaining + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.xNumberOfSuccessfulAllocations) for xNumberOfSuccessfulAllocations + heap_4.o(.text.vPortGetHeapStats) refers to heap_4.o(.bss.xNumberOfSuccessfulFrees) for xNumberOfSuccessfulFrees + heap_4.o(.text.vPortGetHeapStats) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + heap_4.o(.ARM.exidx.text.vPortGetHeapStats) refers to heap_4.o(.text.vPortGetHeapStats) for [Anonymous Symbol] + port.o(.text.pxPortInitialiseStack) refers to port.o(.text.prvTaskExitError) for prvTaskExitError + port.o(.ARM.exidx.text.pxPortInitialiseStack) refers to port.o(.text.pxPortInitialiseStack) for [Anonymous Symbol] + port.o(.text.prvTaskExitError) refers to port.o(.data.uxCriticalNesting) for uxCriticalNesting + port.o(.ARM.exidx.text.prvTaskExitError) refers to port.o(.text.prvTaskExitError) for [Anonymous Symbol] + port.o(.text.SVC_Handler) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + port.o(.ARM.exidx.text.SVC_Handler) refers to port.o(.text.SVC_Handler) for [Anonymous Symbol] + port.o(.text.xPortStartScheduler) refers to port.o(.bss.ucMaxSysCallPriority) for ucMaxSysCallPriority + port.o(.text.xPortStartScheduler) refers to port.o(.bss.ulMaxPRIGROUPValue) for ulMaxPRIGROUPValue + port.o(.text.xPortStartScheduler) refers to port.o(.text.vPortSetupTimerInterrupt) for vPortSetupTimerInterrupt + port.o(.text.xPortStartScheduler) refers to port.o(.data.uxCriticalNesting) for uxCriticalNesting + port.o(.text.xPortStartScheduler) refers to port.o(.text.vPortEnableVFP) for vPortEnableVFP + port.o(.text.xPortStartScheduler) refers to port.o(.text.prvPortStartFirstTask) for prvPortStartFirstTask + port.o(.text.xPortStartScheduler) refers to tasks.o(.text.vTaskSwitchContext) for vTaskSwitchContext + port.o(.text.xPortStartScheduler) refers to port.o(.text.prvTaskExitError) for prvTaskExitError + port.o(.ARM.exidx.text.xPortStartScheduler) refers to port.o(.text.xPortStartScheduler) for [Anonymous Symbol] + port.o(.text.vPortSetupTimerInterrupt) refers to system_stm32f4xx.o(.data.SystemCoreClock) for SystemCoreClock + port.o(.ARM.exidx.text.vPortSetupTimerInterrupt) refers to port.o(.text.vPortSetupTimerInterrupt) for [Anonymous Symbol] + port.o(.ARM.exidx.text.vPortEnableVFP) refers to port.o(.text.vPortEnableVFP) for [Anonymous Symbol] + port.o(.ARM.exidx.text.prvPortStartFirstTask) refers to port.o(.text.prvPortStartFirstTask) for [Anonymous Symbol] + port.o(.text.vPortEndScheduler) refers to port.o(.data.uxCriticalNesting) for uxCriticalNesting + port.o(.ARM.exidx.text.vPortEndScheduler) refers to port.o(.text.vPortEndScheduler) for [Anonymous Symbol] + port.o(.text.vPortEnterCritical) refers to port.o(.data.uxCriticalNesting) for uxCriticalNesting + port.o(.ARM.exidx.text.vPortEnterCritical) refers to port.o(.text.vPortEnterCritical) for [Anonymous Symbol] + port.o(.text.vPortExitCritical) refers to port.o(.data.uxCriticalNesting) for uxCriticalNesting + port.o(.ARM.exidx.text.vPortExitCritical) refers to port.o(.text.vPortExitCritical) for [Anonymous Symbol] + port.o(.text.PendSV_Handler) refers to tasks.o(.text.vTaskSwitchContext) for vTaskSwitchContext + port.o(.text.PendSV_Handler) refers to tasks.o(.bss.pxCurrentTCB) for pxCurrentTCB + port.o(.ARM.exidx.text.PendSV_Handler) refers to port.o(.text.PendSV_Handler) for [Anonymous Symbol] + port.o(.text.xPortSysTickHandler) refers to tasks.o(.text.xTaskIncrementTick) for xTaskIncrementTick + port.o(.ARM.exidx.text.xPortSysTickHandler) refers to port.o(.text.xPortSysTickHandler) for [Anonymous Symbol] + port.o(.text.vPortValidateInterruptPriority) refers to port.o(.bss.ucMaxSysCallPriority) for ucMaxSysCallPriority + port.o(.text.vPortValidateInterruptPriority) refers to port.o(.bss.ulMaxPRIGROUPValue) for ulMaxPRIGROUPValue + port.o(.ARM.exidx.text.vPortValidateInterruptPriority) refers to port.o(.text.vPortValidateInterruptPriority) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox0CompleteCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) for [Anonymous Symbol] + can_1.o(.ARM.exidx.text.CAN_Get) refers to can_1.o(.text.CAN_Get) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox1CompleteCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox2CompleteCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox0AbortCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox1AbortCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox2AbortCallback) refers to can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo0MsgPendingCallback) refers to can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_RxFifo0FullCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_RxFifo0FullCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo0FullCallback) refers to can_1.o(.text.HAL_CAN_RxFifo0FullCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo1MsgPendingCallback) refers to can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_RxFifo1FullCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_RxFifo1FullCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo1FullCallback) refers to can_1.o(.text.HAL_CAN_RxFifo1FullCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_SleepCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_SleepCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_SleepCallback) refers to can_1.o(.text.HAL_CAN_SleepCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_WakeUpFromRxMsgCallback) refers to can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) for [Anonymous Symbol] + can_1.o(.text.HAL_CAN_ErrorCallback) refers to can_1.o(.text.CAN_Get) for CAN_Get + can_1.o(.text.HAL_CAN_ErrorCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.HAL_CAN_ErrorCallback) refers to can_1.o(.text.HAL_CAN_ErrorCallback) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.text.BSP_CAN_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_TxQueueInit) for BSP_CAN_TxQueueInit + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.bss.id_parser) for id_parser + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_DefaultIdParser) for BSP_CAN_DefaultIdParser + can_1.o(.text.BSP_CAN_Init) refers to cmsis_os2.o(.text.osMutexNew) for osMutexNew + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.bss.queue_mutex) for queue_mutex + can_1.o(.text.BSP_CAN_Init) refers to can.o(.bss.hcan1) for hcan1 + can_1.o(.text.BSP_CAN_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ConfigFilter) for HAL_CAN_ConfigFilter + can_1.o(.text.BSP_CAN_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_Start) for HAL_CAN_Start + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_RxFifo0Callback) for BSP_CAN_RxFifo0Callback + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_RegisterCallback) for BSP_CAN_RegisterCallback + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_TxCompleteCallback) for BSP_CAN_TxCompleteCallback + can_1.o(.text.BSP_CAN_Init) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_ActivateNotification) for HAL_CAN_ActivateNotification + can_1.o(.text.BSP_CAN_Init) refers to can.o(.bss.hcan2) for hcan2 + can_1.o(.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_RxFifo1Callback) for BSP_CAN_RxFifo1Callback + can_1.o(.ARM.exidx.text.BSP_CAN_Init) refers to can_1.o(.text.BSP_CAN_Init) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TxQueueInit) refers to can_1.o(.bss.tx_queues) for tx_queues + can_1.o(.ARM.exidx.text.BSP_CAN_TxQueueInit) refers to can_1.o(.text.BSP_CAN_TxQueueInit) for [Anonymous Symbol] + can_1.o(.ARM.exidx.text.BSP_CAN_DefaultIdParser) refers to can_1.o(.text.BSP_CAN_DefaultIdParser) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_RegisterCallback) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_RegisterCallback) refers to can_1.o(.bss.CAN_Callback) for CAN_Callback + can_1.o(.ARM.exidx.text.BSP_CAN_RegisterCallback) refers to can_1.o(.text.BSP_CAN_RegisterCallback) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to can_1.o(.text.BSP_CAN_GetHandle) for BSP_CAN_GetHandle + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel) for HAL_CAN_GetRxFifoFillLevel + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage) for HAL_CAN_GetRxMessage + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to can_1.o(.text.BSP_CAN_GetFrameType) for BSP_CAN_GetFrameType + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to can_1.o(.text.BSP_CAN_ParseId) for BSP_CAN_ParseId + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to can_1.o(.text.BSP_CAN_FindQueue) for BSP_CAN_FindQueue + can_1.o(.text.BSP_CAN_RxFifo0Callback) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + can_1.o(.ARM.exidx.text.BSP_CAN_RxFifo0Callback) refers to can_1.o(.text.BSP_CAN_RxFifo0Callback) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TxCompleteCallback) refers to can_1.o(.text.BSP_CAN_GetHandle) for BSP_CAN_GetHandle + can_1.o(.text.BSP_CAN_TxCompleteCallback) refers to can_1.o(.text.BSP_CAN_TxQueueIsEmpty) for BSP_CAN_TxQueueIsEmpty + can_1.o(.text.BSP_CAN_TxCompleteCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel) for HAL_CAN_GetTxMailboxesFreeLevel + can_1.o(.text.BSP_CAN_TxCompleteCallback) refers to can_1.o(.text.BSP_CAN_TxQueuePop) for BSP_CAN_TxQueuePop + can_1.o(.text.BSP_CAN_TxCompleteCallback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage) for HAL_CAN_AddTxMessage + can_1.o(.ARM.exidx.text.BSP_CAN_TxCompleteCallback) refers to can_1.o(.text.BSP_CAN_TxCompleteCallback) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to can_1.o(.text.BSP_CAN_GetHandle) for BSP_CAN_GetHandle + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to stm32f4xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel) for HAL_CAN_GetRxFifoFillLevel + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage) for HAL_CAN_GetRxMessage + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to can_1.o(.text.BSP_CAN_GetFrameType) for BSP_CAN_GetFrameType + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to can_1.o(.text.BSP_CAN_ParseId) for BSP_CAN_ParseId + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to can_1.o(.text.BSP_CAN_FindQueue) for BSP_CAN_FindQueue + can_1.o(.text.BSP_CAN_RxFifo1Callback) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + can_1.o(.ARM.exidx.text.BSP_CAN_RxFifo1Callback) refers to can_1.o(.text.BSP_CAN_RxFifo1Callback) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_GetHandle) refers to can.o(.bss.hcan2) for hcan2 + can_1.o(.text.BSP_CAN_GetHandle) refers to can.o(.bss.hcan1) for hcan1 + can_1.o(.ARM.exidx.text.BSP_CAN_GetHandle) refers to can_1.o(.text.BSP_CAN_GetHandle) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_Transmit) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_Transmit) refers to can_1.o(.text.BSP_CAN_GetHandle) for BSP_CAN_GetHandle + can_1.o(.text.BSP_CAN_Transmit) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + can_1.o(.text.BSP_CAN_Transmit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel) for HAL_CAN_GetTxMailboxesFreeLevel + can_1.o(.text.BSP_CAN_Transmit) refers to stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage) for HAL_CAN_AddTxMessage + can_1.o(.text.BSP_CAN_Transmit) refers to can_1.o(.text.BSP_CAN_TxQueuePush) for BSP_CAN_TxQueuePush + can_1.o(.ARM.exidx.text.BSP_CAN_Transmit) refers to can_1.o(.text.BSP_CAN_Transmit) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TxQueuePush) refers to can_1.o(.bss.tx_queues) for tx_queues + can_1.o(.ARM.exidx.text.BSP_CAN_TxQueuePush) refers to can_1.o(.text.BSP_CAN_TxQueuePush) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TransmitStdDataFrame) refers to can_1.o(.text.BSP_CAN_Transmit) for BSP_CAN_Transmit + can_1.o(.ARM.exidx.text.BSP_CAN_TransmitStdDataFrame) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TransmitExtDataFrame) refers to can_1.o(.text.BSP_CAN_Transmit) for BSP_CAN_Transmit + can_1.o(.ARM.exidx.text.BSP_CAN_TransmitExtDataFrame) refers to can_1.o(.text.BSP_CAN_TransmitExtDataFrame) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TransmitRemoteFrame) refers to can_1.o(.text.BSP_CAN_Transmit) for BSP_CAN_Transmit + can_1.o(.ARM.exidx.text.BSP_CAN_TransmitRemoteFrame) refers to can_1.o(.text.BSP_CAN_TransmitRemoteFrame) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_RegisterId) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_RegisterId) refers to can_1.o(.text.BSP_CAN_CreateIdQueue) for BSP_CAN_CreateIdQueue + can_1.o(.ARM.exidx.text.BSP_CAN_RegisterId) refers to can_1.o(.text.BSP_CAN_RegisterId) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to can_1.o(.bss.queue_mutex) for queue_mutex + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to cmsis_os2.o(.text.osMutexAcquire) for osMutexAcquire + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to can_1.o(.bss.queue_list) for queue_list + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to mm.o(.text.BSP_Malloc) for BSP_Malloc + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to cmsis_os2.o(.text.osMessageQueueNew) for osMessageQueueNew + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to mm.o(.text.BSP_Free) for BSP_Free + can_1.o(.text.BSP_CAN_CreateIdQueue) refers to cmsis_os2.o(.text.osMutexRelease) for osMutexRelease + can_1.o(.ARM.exidx.text.BSP_CAN_CreateIdQueue) refers to can_1.o(.text.BSP_CAN_CreateIdQueue) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_GetMessage) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_GetMessage) refers to can_1.o(.bss.queue_mutex) for queue_mutex + can_1.o(.text.BSP_CAN_GetMessage) refers to cmsis_os2.o(.text.osMutexAcquire) for osMutexAcquire + can_1.o(.text.BSP_CAN_GetMessage) refers to can_1.o(.text.BSP_CAN_FindQueue) for BSP_CAN_FindQueue + can_1.o(.text.BSP_CAN_GetMessage) refers to cmsis_os2.o(.text.osMutexRelease) for osMutexRelease + can_1.o(.text.BSP_CAN_GetMessage) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + can_1.o(.ARM.exidx.text.BSP_CAN_GetMessage) refers to can_1.o(.text.BSP_CAN_GetMessage) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_FindQueue) refers to can_1.o(.bss.queue_list) for queue_list + can_1.o(.ARM.exidx.text.BSP_CAN_FindQueue) refers to can_1.o(.text.BSP_CAN_FindQueue) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_GetQueueCount) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_GetQueueCount) refers to can_1.o(.bss.queue_mutex) for queue_mutex + can_1.o(.text.BSP_CAN_GetQueueCount) refers to cmsis_os2.o(.text.osMutexAcquire) for osMutexAcquire + can_1.o(.text.BSP_CAN_GetQueueCount) refers to can_1.o(.text.BSP_CAN_FindQueue) for BSP_CAN_FindQueue + can_1.o(.text.BSP_CAN_GetQueueCount) refers to cmsis_os2.o(.text.osMutexRelease) for osMutexRelease + can_1.o(.text.BSP_CAN_GetQueueCount) refers to cmsis_os2.o(.text.osMessageQueueGetCount) for osMessageQueueGetCount + can_1.o(.ARM.exidx.text.BSP_CAN_GetQueueCount) refers to can_1.o(.text.BSP_CAN_GetQueueCount) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_FlushQueue) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_FlushQueue) refers to can_1.o(.bss.queue_mutex) for queue_mutex + can_1.o(.text.BSP_CAN_FlushQueue) refers to cmsis_os2.o(.text.osMutexAcquire) for osMutexAcquire + can_1.o(.text.BSP_CAN_FlushQueue) refers to can_1.o(.text.BSP_CAN_FindQueue) for BSP_CAN_FindQueue + can_1.o(.text.BSP_CAN_FlushQueue) refers to cmsis_os2.o(.text.osMutexRelease) for osMutexRelease + can_1.o(.text.BSP_CAN_FlushQueue) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + can_1.o(.ARM.exidx.text.BSP_CAN_FlushQueue) refers to can_1.o(.text.BSP_CAN_FlushQueue) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_RegisterIdParser) refers to can_1.o(.bss.inited) for inited + can_1.o(.text.BSP_CAN_RegisterIdParser) refers to can_1.o(.bss.id_parser) for id_parser + can_1.o(.ARM.exidx.text.BSP_CAN_RegisterIdParser) refers to can_1.o(.text.BSP_CAN_RegisterIdParser) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_ParseId) refers to can_1.o(.bss.id_parser) for id_parser + can_1.o(.ARM.exidx.text.BSP_CAN_ParseId) refers to can_1.o(.text.BSP_CAN_ParseId) for [Anonymous Symbol] + can_1.o(.ARM.exidx.text.BSP_CAN_GetFrameType) refers to can_1.o(.text.BSP_CAN_GetFrameType) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TxQueueIsEmpty) refers to can_1.o(.bss.tx_queues) for tx_queues + can_1.o(.ARM.exidx.text.BSP_CAN_TxQueueIsEmpty) refers to can_1.o(.text.BSP_CAN_TxQueueIsEmpty) for [Anonymous Symbol] + can_1.o(.text.BSP_CAN_TxQueuePop) refers to can_1.o(.bss.tx_queues) for tx_queues + can_1.o(.ARM.exidx.text.BSP_CAN_TxQueuePop) refers to can_1.o(.text.BSP_CAN_TxQueuePop) for [Anonymous Symbol] + gpio_1.o(.text.HAL_GPIO_EXTI_Callback) refers to gpio_1.o(.bss.GPIO_Callback) for GPIO_Callback + gpio_1.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback) refers to gpio_1.o(.text.HAL_GPIO_EXTI_Callback) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_RegisterCallback) refers to gpio_1.o(.rodata.GPIO_Map) for GPIO_Map + gpio_1.o(.text.BSP_GPIO_RegisterCallback) refers to gpio_1.o(.bss.GPIO_Callback) for GPIO_Callback + gpio_1.o(.ARM.exidx.text.BSP_GPIO_RegisterCallback) refers to gpio_1.o(.text.BSP_GPIO_RegisterCallback) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_EnableIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + gpio_1.o(.ARM.exidx.text.BSP_GPIO_EnableIRQ) refers to gpio_1.o(.text.BSP_GPIO_EnableIRQ) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_DisableIRQ) refers to stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ + gpio_1.o(.ARM.exidx.text.BSP_GPIO_DisableIRQ) refers to gpio_1.o(.text.BSP_GPIO_DisableIRQ) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_WritePin) refers to gpio_1.o(.rodata.GPIO_Map) for GPIO_Map + gpio_1.o(.text.BSP_GPIO_WritePin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin + gpio_1.o(.ARM.exidx.text.BSP_GPIO_WritePin) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_TogglePin) refers to gpio_1.o(.rodata.GPIO_Map) for GPIO_Map + gpio_1.o(.text.BSP_GPIO_TogglePin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_TogglePin) for HAL_GPIO_TogglePin + gpio_1.o(.ARM.exidx.text.BSP_GPIO_TogglePin) refers to gpio_1.o(.text.BSP_GPIO_TogglePin) for [Anonymous Symbol] + gpio_1.o(.text.BSP_GPIO_ReadPin) refers to gpio_1.o(.rodata.GPIO_Map) for GPIO_Map + gpio_1.o(.text.BSP_GPIO_ReadPin) refers to stm32f4xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) for HAL_GPIO_ReadPin + gpio_1.o(.ARM.exidx.text.BSP_GPIO_ReadPin) refers to gpio_1.o(.text.BSP_GPIO_ReadPin) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.ARM.exidx.text.I2C_Get) refers to i2c_1.o(.text.I2C_Get) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_ListenCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_ListenCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback) refers to i2c_1.o(.text.HAL_I2C_ListenCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_MemTxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback) refers to i2c_1.o(.text.HAL_I2C_MemRxCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_ErrorCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_ErrorCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_ErrorCallback) refers to i2c_1.o(.text.HAL_I2C_ErrorCallback) for [Anonymous Symbol] + i2c_1.o(.text.HAL_I2C_AbortCpltCallback) refers to i2c_1.o(.text.I2C_Get) for I2C_Get + i2c_1.o(.text.HAL_I2C_AbortCpltCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback) refers to i2c_1.o(.text.HAL_I2C_AbortCpltCallback) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_GetHandle) refers to i2c.o(.bss.hi2c2) for hi2c2 + i2c_1.o(.ARM.exidx.text.BSP_I2C_GetHandle) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_RegisterCallback) refers to i2c_1.o(.bss.I2C_Callback) for I2C_Callback + i2c_1.o(.ARM.exidx.text.BSP_I2C_RegisterCallback) refers to i2c_1.o(.text.BSP_I2C_RegisterCallback) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_Transmit) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_Transmit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA) for HAL_I2C_Master_Transmit_DMA + i2c_1.o(.text.BSP_I2C_Transmit) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit) for HAL_I2C_Master_Transmit + i2c_1.o(.ARM.exidx.text.BSP_I2C_Transmit) refers to i2c_1.o(.text.BSP_I2C_Transmit) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_Receive) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_Receive) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA) for HAL_I2C_Master_Receive_DMA + i2c_1.o(.text.BSP_I2C_Receive) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive) for HAL_I2C_Master_Receive + i2c_1.o(.ARM.exidx.text.BSP_I2C_Receive) refers to i2c_1.o(.text.BSP_I2C_Receive) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_MemReadByte) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_MemReadByte) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) for HAL_I2C_Mem_Read + i2c_1.o(.ARM.exidx.text.BSP_I2C_MemReadByte) refers to i2c_1.o(.text.BSP_I2C_MemReadByte) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_MemWriteByte) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_MemWriteByte) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) for HAL_I2C_Mem_Write + i2c_1.o(.ARM.exidx.text.BSP_I2C_MemWriteByte) refers to i2c_1.o(.text.BSP_I2C_MemWriteByte) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_MemRead) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_MemRead) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA) for HAL_I2C_Mem_Read_DMA + i2c_1.o(.text.BSP_I2C_MemRead) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read) for HAL_I2C_Mem_Read + i2c_1.o(.ARM.exidx.text.BSP_I2C_MemRead) refers to i2c_1.o(.text.BSP_I2C_MemRead) for [Anonymous Symbol] + i2c_1.o(.text.BSP_I2C_MemWrite) refers to i2c_1.o(.text.BSP_I2C_GetHandle) for BSP_I2C_GetHandle + i2c_1.o(.text.BSP_I2C_MemWrite) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA) for HAL_I2C_Mem_Write_DMA + i2c_1.o(.text.BSP_I2C_MemWrite) refers to stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write) for HAL_I2C_Mem_Write + i2c_1.o(.ARM.exidx.text.BSP_I2C_MemWrite) refers to i2c_1.o(.text.BSP_I2C_MemWrite) for [Anonymous Symbol] + mm.o(.text.BSP_Malloc) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + mm.o(.ARM.exidx.text.BSP_Malloc) refers to mm.o(.text.BSP_Malloc) for [Anonymous Symbol] + mm.o(.text.BSP_Free) refers to heap_4.o(.text.vPortFree) for vPortFree + mm.o(.ARM.exidx.text.BSP_Free) refers to mm.o(.text.BSP_Free) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_TxCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_TxCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_TxCpltCallback) refers to spi_1.o(.text.HAL_SPI_TxCpltCallback) for [Anonymous Symbol] + spi_1.o(.ARM.exidx.text.SPI_Get) refers to spi_1.o(.text.SPI_Get) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_RxCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_RxCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_RxCpltCallback) refers to spi_1.o(.text.HAL_SPI_RxCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_TxRxCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_TxRxCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_TxRxCpltCallback) refers to spi_1.o(.text.HAL_SPI_TxRxCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_TxHalfCpltCallback) refers to spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_RxHalfCpltCallback) refers to spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_TxRxHalfCpltCallback) refers to spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_ErrorCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_ErrorCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_ErrorCallback) refers to spi_1.o(.text.HAL_SPI_ErrorCallback) for [Anonymous Symbol] + spi_1.o(.text.HAL_SPI_AbortCpltCallback) refers to spi_1.o(.text.SPI_Get) for SPI_Get + spi_1.o(.text.HAL_SPI_AbortCpltCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.HAL_SPI_AbortCpltCallback) refers to spi_1.o(.text.HAL_SPI_AbortCpltCallback) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_GetHandle) refers to spi.o(.bss.hspi1) for hspi1 + spi_1.o(.ARM.exidx.text.BSP_SPI_GetHandle) refers to spi_1.o(.text.BSP_SPI_GetHandle) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_RegisterCallback) refers to spi_1.o(.bss.SPI_Callback) for SPI_Callback + spi_1.o(.ARM.exidx.text.BSP_SPI_RegisterCallback) refers to spi_1.o(.text.BSP_SPI_RegisterCallback) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_Transmit) refers to spi_1.o(.text.BSP_SPI_GetHandle) for BSP_SPI_GetHandle + spi_1.o(.text.BSP_SPI_Transmit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) for HAL_SPI_Transmit_DMA + spi_1.o(.text.BSP_SPI_Transmit) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) for HAL_SPI_Transmit + spi_1.o(.ARM.exidx.text.BSP_SPI_Transmit) refers to spi_1.o(.text.BSP_SPI_Transmit) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_Receive) refers to spi_1.o(.text.BSP_SPI_GetHandle) for BSP_SPI_GetHandle + spi_1.o(.text.BSP_SPI_Receive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) for HAL_SPI_Receive_DMA + spi_1.o(.text.BSP_SPI_Receive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) for HAL_SPI_Receive + spi_1.o(.ARM.exidx.text.BSP_SPI_Receive) refers to spi_1.o(.text.BSP_SPI_Receive) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_TransmitReceive) refers to spi_1.o(.text.BSP_SPI_GetHandle) for BSP_SPI_GetHandle + spi_1.o(.text.BSP_SPI_TransmitReceive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) for HAL_SPI_TransmitReceive_DMA + spi_1.o(.text.BSP_SPI_TransmitReceive) refers to stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) for HAL_SPI_TransmitReceive + spi_1.o(.ARM.exidx.text.BSP_SPI_TransmitReceive) refers to spi_1.o(.text.BSP_SPI_TransmitReceive) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_MemReadByte) refers to spi_1.o(.text.BSP_SPI_TransmitReceive) for BSP_SPI_TransmitReceive + spi_1.o(.ARM.exidx.text.BSP_SPI_MemReadByte) refers to spi_1.o(.text.BSP_SPI_MemReadByte) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_MemWriteByte) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + spi_1.o(.ARM.exidx.text.BSP_SPI_MemWriteByte) refers to spi_1.o(.text.BSP_SPI_MemWriteByte) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_MemRead) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + spi_1.o(.text.BSP_SPI_MemRead) refers to spi_1.o(.text.BSP_SPI_Receive) for BSP_SPI_Receive + spi_1.o(.ARM.exidx.text.BSP_SPI_MemRead) refers to spi_1.o(.text.BSP_SPI_MemRead) for [Anonymous Symbol] + spi_1.o(.text.BSP_SPI_MemWrite) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + spi_1.o(.ARM.exidx.text.BSP_SPI_MemWrite) refers to spi_1.o(.text.BSP_SPI_MemWrite) for [Anonymous Symbol] + uart.o(.text.HAL_UART_TxCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_TxCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback) refers to uart.o(.text.HAL_UART_TxCpltCallback) for [Anonymous Symbol] + uart.o(.ARM.exidx.text.UART_Get) refers to uart.o(.text.UART_Get) for [Anonymous Symbol] + uart.o(.text.HAL_UART_TxHalfCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_TxHalfCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback) refers to uart.o(.text.HAL_UART_TxHalfCpltCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_RxCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_RxCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback) refers to uart.o(.text.HAL_UART_RxCpltCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_RxHalfCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_RxHalfCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback) refers to uart.o(.text.HAL_UART_RxHalfCpltCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_ErrorCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_ErrorCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback) refers to uart.o(.text.HAL_UART_ErrorCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_AbortCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_AbortCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback) refers to uart.o(.text.HAL_UART_AbortCpltCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_AbortTransmitCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_AbortTransmitCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback) refers to uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for [Anonymous Symbol] + uart.o(.text.HAL_UART_AbortReceiveCpltCallback) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.HAL_UART_AbortReceiveCpltCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback) refers to uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for [Anonymous Symbol] + uart.o(.text.BSP_UART_IRQHandler) refers to uart.o(.text.UART_Get) for UART_Get + uart.o(.text.BSP_UART_IRQHandler) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.BSP_UART_IRQHandler) refers to uart.o(.text.BSP_UART_IRQHandler) for [Anonymous Symbol] + uart.o(.text.BSP_UART_GetHandle) refers to usart.o(.bss.huart1) for huart1 + uart.o(.text.BSP_UART_GetHandle) refers to usart.o(.bss.huart6) for huart6 + uart.o(.text.BSP_UART_GetHandle) refers to usart.o(.bss.huart3) for huart3 + uart.o(.ARM.exidx.text.BSP_UART_GetHandle) refers to uart.o(.text.BSP_UART_GetHandle) for [Anonymous Symbol] + uart.o(.text.BSP_UART_RegisterCallback) refers to uart.o(.bss.UART_Callback) for UART_Callback + uart.o(.ARM.exidx.text.BSP_UART_RegisterCallback) refers to uart.o(.text.BSP_UART_RegisterCallback) for [Anonymous Symbol] + uart.o(.text.BSP_UART_Transmit) refers to uart.o(.text.BSP_UART_GetHandle) for BSP_UART_GetHandle + uart.o(.text.BSP_UART_Transmit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) for HAL_UART_Transmit_DMA + uart.o(.text.BSP_UART_Transmit) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_IT) for HAL_UART_Transmit_IT + uart.o(.ARM.exidx.text.BSP_UART_Transmit) refers to uart.o(.text.BSP_UART_Transmit) for [Anonymous Symbol] + uart.o(.text.BSP_UART_Receive) refers to uart.o(.text.BSP_UART_GetHandle) for BSP_UART_GetHandle + uart.o(.text.BSP_UART_Receive) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) for HAL_UART_Receive_DMA + uart.o(.text.BSP_UART_Receive) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT) for HAL_UART_Receive_IT + uart.o(.ARM.exidx.text.BSP_UART_Receive) refers to uart.o(.text.BSP_UART_Receive) for [Anonymous Symbol] + time.o(.text.BSP_TIME_Get_ms) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + time.o(.ARM.exidx.text.BSP_TIME_Get_ms) refers to time.o(.text.BSP_TIME_Get_ms) for [Anonymous Symbol] + time.o(.text.BSP_TIME_Get_us) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + time.o(.text.BSP_TIME_Get_us) refers to tasks.o(.text.xTaskGetTickCount) for xTaskGetTickCount + time.o(.ARM.exidx.text.BSP_TIME_Get_us) refers to time.o(.text.BSP_TIME_Get_us) for [Anonymous Symbol] + time.o(.text.BSP_TIME_Delay_ms) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + time.o(.text.BSP_TIME_Delay_ms) refers to cmsis_os2.o(.text.osKernelGetState) for osKernelGetState + time.o(.text.BSP_TIME_Delay_ms) refers to stm32f4xx_hal.o(.text.HAL_Delay) for HAL_Delay + time.o(.text.BSP_TIME_Delay_ms) refers to cmsis_os2.o(.text.osDelay) for osDelay + time.o(.ARM.exidx.text.BSP_TIME_Delay_ms) refers to time.o(.text.BSP_TIME_Delay_ms) for [Anonymous Symbol] + time.o(.text.BSP_TIME_Delay_us) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get_us + time.o(.ARM.exidx.text.BSP_TIME_Delay_us) refers to time.o(.text.BSP_TIME_Delay_us) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_Start) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.text.BSP_PWM_Start) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start) for HAL_TIM_PWM_Start + pwm.o(.ARM.exidx.text.BSP_PWM_Start) refers to pwm.o(.text.BSP_PWM_Start) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_SetComp) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.ARM.exidx.text.BSP_PWM_SetComp) refers to pwm.o(.text.BSP_PWM_SetComp) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_SetFreq) refers to stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + pwm.o(.text.BSP_PWM_SetFreq) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.ARM.exidx.text.BSP_PWM_SetFreq) refers to pwm.o(.text.BSP_PWM_SetFreq) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_Stop) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.text.BSP_PWM_Stop) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) for HAL_TIM_PWM_Stop + pwm.o(.ARM.exidx.text.BSP_PWM_Stop) refers to pwm.o(.text.BSP_PWM_Stop) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_GetAutoReloadPreload) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.ARM.exidx.text.BSP_PWM_GetAutoReloadPreload) refers to pwm.o(.text.BSP_PWM_GetAutoReloadPreload) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_GetHandle) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.ARM.exidx.text.BSP_PWM_GetHandle) refers to pwm.o(.text.BSP_PWM_GetHandle) for [Anonymous Symbol] + pwm.o(.ARM.exidx.text.BSP_PWM_GetChannel) refers to pwm.o(.text.BSP_PWM_GetChannel) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_Start_DMA) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.text.BSP_PWM_Start_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) for HAL_TIM_PWM_Start_DMA + pwm.o(.ARM.exidx.text.BSP_PWM_Start_DMA) refers to pwm.o(.text.BSP_PWM_Start_DMA) for [Anonymous Symbol] + pwm.o(.text.BSP_PWM_Stop_DMA) refers to tim.o(.bss.htim10) for htim10 + pwm.o(.text.BSP_PWM_Stop_DMA) refers to stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) for HAL_TIM_PWM_Stop_DMA + pwm.o(.ARM.exidx.text.BSP_PWM_Stop_DMA) refers to pwm.o(.text.BSP_PWM_Stop_DMA) for [Anonymous Symbol] + ahrs.o(.text.AHRS_Init) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + ahrs.o(.text.AHRS_Init) refers to atan2.o(i.__hardfp_atan2) for __hardfp_atan2 + ahrs.o(.text.AHRS_Init) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f + ahrs.o(.ARM.exidx.text.AHRS_Init) refers to ahrs.o(.text.AHRS_Init) for [Anonymous Symbol] + ahrs.o(.text.AHRS_Update) refers to ahrs.o(.data.beta) for beta + ahrs.o(.text.AHRS_Update) refers to ahrs.o(.text.AHRS_UpdateIMU) for AHRS_UpdateIMU + ahrs.o(.text.AHRS_Update) refers to user_math.o(.text.InvSqrt) for InvSqrt + ahrs.o(.ARM.exidx.text.AHRS_Update) refers to ahrs.o(.text.AHRS_Update) for [Anonymous Symbol] + ahrs.o(.text.AHRS_UpdateIMU) refers to ahrs.o(.data.beta) for beta + ahrs.o(.text.AHRS_UpdateIMU) refers to user_math.o(.text.InvSqrt) for InvSqrt + ahrs.o(.ARM.exidx.text.AHRS_UpdateIMU) refers to ahrs.o(.text.AHRS_UpdateIMU) for [Anonymous Symbol] + ahrs.o(.text.AHRS_GetEulr) refers to atan2f.o(i.__hardfp_atan2f) for __hardfp_atan2f + ahrs.o(.text.AHRS_GetEulr) refers to asinf.o(i.__hardfp_asinf) for __hardfp_asinf + ahrs.o(.text.AHRS_GetEulr) refers to ahrs.o(.text.copysignf) for copysignf + ahrs.o(.ARM.exidx.text.AHRS_GetEulr) refers to ahrs.o(.text.AHRS_GetEulr) for [Anonymous Symbol] + ahrs.o(.ARM.exidx.text.copysignf) refers to ahrs.o(.text.copysignf) for [Anonymous Symbol] + ahrs.o(.ARM.exidx.text.AHRS_ResetEulr) refers to ahrs.o(.text.AHRS_ResetEulr) for [Anonymous Symbol] + capacity.o(.ARM.exidx.text.Capacity_GetBatteryRemain) refers to capacity.o(.text.Capacity_GetBatteryRemain) for [Anonymous Symbol] + capacity.o(.ARM.exidx.text.Capacity_GetCapacitorRemain) refers to capacity.o(.text.Capacity_GetCapacitorRemain) for [Anonymous Symbol] + crc8.o(.text.CRC8_Calc) refers to crc8.o(.rodata.crc8_tab) for crc8_tab + crc8.o(.ARM.exidx.text.CRC8_Calc) refers to crc8.o(.text.CRC8_Calc) for [Anonymous Symbol] + crc8.o(.text.CRC8_Verify) refers to crc8.o(.text.CRC8_Calc) for CRC8_Calc + crc8.o(.ARM.exidx.text.CRC8_Verify) refers to crc8.o(.text.CRC8_Verify) for [Anonymous Symbol] + crc16.o(.text.CRC16_Calc) refers to crc16.o(.text.CRC16_Byte) for CRC16_Byte + crc16.o(.ARM.exidx.text.CRC16_Calc) refers to crc16.o(.text.CRC16_Calc) for [Anonymous Symbol] + crc16.o(.text.CRC16_Byte) refers to crc16.o(.rodata.crc16_tab) for crc16_tab + crc16.o(.ARM.exidx.text.CRC16_Byte) refers to crc16.o(.text.CRC16_Byte) for [Anonymous Symbol] + crc16.o(.text.CRC16_Verify) refers to crc16.o(.text.CRC16_Calc) for CRC16_Calc + crc16.o(.ARM.exidx.text.CRC16_Verify) refers to crc16.o(.text.CRC16_Verify) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_Init) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.text.ErrorDetect_Init) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + error_detect.o(.ARM.exidx.text.ErrorDetect_Init) refers to error_detect.o(.text.ErrorDetect_Init) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_Processing) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.ARM.exidx.text.ErrorDetect_Processing) refers to error_detect.o(.text.ErrorDetect_Processing) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_ErrorExist) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.ARM.exidx.text.ErrorDetect_ErrorExist) refers to error_detect.o(.text.ErrorDetect_ErrorExist) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_GetErrorUnit) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.ARM.exidx.text.ErrorDetect_GetErrorUnit) refers to error_detect.o(.text.ErrorDetect_GetErrorUnit) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_GetDetail) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.ARM.exidx.text.ErrorDetect_GetDetail) refers to error_detect.o(.text.ErrorDetect_GetDetail) for [Anonymous Symbol] + error_detect.o(.text.ErrorDetect_Update) refers to error_detect.o(.bss.ged) for ged + error_detect.o(.ARM.exidx.text.ErrorDetect_Update) refers to error_detect.o(.text.ErrorDetect_Update) for [Anonymous Symbol] + filter.o(.text.LowPassFilter2p_Init) refers to tanf.o(i.__hardfp_tanf) for __hardfp_tanf + filter.o(.ARM.exidx.text.LowPassFilter2p_Init) refers to filter.o(.text.LowPassFilter2p_Init) for [Anonymous Symbol] + filter.o(.text.LowPassFilter2p_Apply) refers to filter.o(.text.__ARM_isinff) for __ARM_isinff + filter.o(.ARM.exidx.text.LowPassFilter2p_Apply) refers to filter.o(.text.LowPassFilter2p_Apply) for [Anonymous Symbol] + filter.o(.ARM.exidx.text.__ARM_isinff) refers to filter.o(.text.__ARM_isinff) for [Anonymous Symbol] + filter.o(.text.LowPassFilter2p_Reset) refers to filter.o(.text.__ARM_isfinitef) for __ARM_isfinitef + filter.o(.text.LowPassFilter2p_Reset) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + filter.o(.ARM.exidx.text.LowPassFilter2p_Reset) refers to filter.o(.text.LowPassFilter2p_Reset) for [Anonymous Symbol] + filter.o(.ARM.exidx.text.__ARM_isfinitef) refers to filter.o(.text.__ARM_isfinitef) for [Anonymous Symbol] + filter.o(.text.NotchFilter_Init) refers to tanf.o(i.__hardfp_tanf) for __hardfp_tanf + filter.o(.text.NotchFilter_Init) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + filter.o(.ARM.exidx.text.NotchFilter_Init) refers to filter.o(.text.NotchFilter_Init) for [Anonymous Symbol] + filter.o(.ARM.exidx.text.NotchFilter_Apply) refers to filter.o(.text.NotchFilter_Apply) for [Anonymous Symbol] + filter.o(.text.NotchFilter_Reset) refers to filter.o(.text.NotchFilter_Apply) for NotchFilter_Apply + filter.o(.ARM.exidx.text.NotchFilter_Reset) refers to filter.o(.text.NotchFilter_Reset) for [Anonymous Symbol] + freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand) refers to heap_4.o(.text.pvPortMalloc) for pvPortMalloc + freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand) refers to port.o(.text.vPortEnterCritical) for vPortEnterCritical + freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand) refers to freertos_cli.o(.data.FreeRTOS_CLIRegisterCommand.pxLastCommandInList) for FreeRTOS_CLIRegisterCommand.pxLastCommandInList + freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand) refers to port.o(.text.vPortExitCritical) for vPortExitCritical + freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIRegisterCommand) refers to freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand) for [Anonymous Symbol] + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to freertos_cli.o(.bss.FreeRTOS_CLIProcessCommand.pxCommand) for FreeRTOS_CLIProcessCommand.pxCommand + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to freertos_cli.o(.data.xRegisteredCommands) for xRegisteredCommands + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to strlen.o(.text) for strlen + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to strncmp.o(.text) for strncmp + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to freertos_cli.o(.text.prvGetNumberOfParameters) for prvGetNumberOfParameters + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to freertos_cli.o(.rodata.str1.1) for .L.str + freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) refers to strncpy.o(.text) for strncpy + freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIProcessCommand) refers to freertos_cli.o(.text.FreeRTOS_CLIProcessCommand) for [Anonymous Symbol] + freertos_cli.o(.ARM.exidx.text.prvGetNumberOfParameters) refers to freertos_cli.o(.text.prvGetNumberOfParameters) for [Anonymous Symbol] + freertos_cli.o(.text.FreeRTOS_CLIGetOutputBuffer) refers to freertos_cli.o(.bss.cOutputBuffer) for cOutputBuffer + freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIGetOutputBuffer) refers to freertos_cli.o(.text.FreeRTOS_CLIGetOutputBuffer) for [Anonymous Symbol] + freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIGetParameter) refers to freertos_cli.o(.text.FreeRTOS_CLIGetParameter) for [Anonymous Symbol] + freertos_cli.o(.text.prvHelpCommand) refers to freertos_cli.o(.bss.prvHelpCommand.pxCommand) for prvHelpCommand.pxCommand + freertos_cli.o(.text.prvHelpCommand) refers to freertos_cli.o(.data.xRegisteredCommands) for xRegisteredCommands + freertos_cli.o(.text.prvHelpCommand) refers to strncpy.o(.text) for strncpy + freertos_cli.o(.ARM.exidx.text.prvHelpCommand) refers to freertos_cli.o(.text.prvHelpCommand) for [Anonymous Symbol] + freertos_cli.o(.data.FreeRTOS_CLIRegisterCommand.pxLastCommandInList) refers to freertos_cli.o(.data.xRegisteredCommands) for [Anonymous Symbol] + freertos_cli.o(.data.xRegisteredCommands) refers to freertos_cli.o(.rodata.xHelpCommand) for [Anonymous Symbol] + freertos_cli.o(.rodata.xHelpCommand) refers to freertos_cli.o(.rodata.str1.1) for [Anonymous Symbol] + freertos_cli.o(.rodata.xHelpCommand) refers to freertos_cli.o(.text.prvHelpCommand) for prvHelpCommand + limiter.o(.ARM.exidx.text.PowerLimit_ChassicOutput) refers to limiter.o(.text.PowerLimit_ChassicOutput) for [Anonymous Symbol] + limiter.o(.ARM.exidx.text.PowerLimit_CapInput) refers to limiter.o(.text.PowerLimit_CapInput) for [Anonymous Symbol] + limiter.o(.ARM.exidx.text.PowerLimit_TargetPower) refers to limiter.o(.text.PowerLimit_TargetPower) for [Anonymous Symbol] + limiter.o(.ARM.exidx.text.HeatLimit_ShootFreq) refers to limiter.o(.text.HeatLimit_ShootFreq) for [Anonymous Symbol] + mixer.o(.ARM.exidx.text.Mixer_Init) refers to mixer.o(.text.Mixer_Init) for [Anonymous Symbol] + mixer.o(.ARM.exidx.text.Mixer_Apply) refers to mixer.o(.text.Mixer_Apply) for [Anonymous Symbol] + pid.o(.text.PID_Init) refers to pid.o(.text.__ARM_isfinitef) for __ARM_isfinitef + pid.o(.text.PID_Init) refers to filter.o(.text.LowPassFilter2p_Init) for LowPassFilter2p_Init + pid.o(.text.PID_Init) refers to pid.o(.text.PID_Reset) for PID_Reset + pid.o(.ARM.exidx.text.PID_Init) refers to pid.o(.text.PID_Init) for [Anonymous Symbol] + pid.o(.ARM.exidx.text.__ARM_isfinitef) refers to pid.o(.text.__ARM_isfinitef) for [Anonymous Symbol] + pid.o(.text.PID_Reset) refers to filter.o(.text.LowPassFilter2p_Reset) for LowPassFilter2p_Reset + pid.o(.ARM.exidx.text.PID_Reset) refers to pid.o(.text.PID_Reset) for [Anonymous Symbol] + pid.o(.text.PID_Calc) refers to pid.o(.text.__ARM_isfinitef) for __ARM_isfinitef + pid.o(.text.PID_Calc) refers to user_math.o(.text.CircleError) for CircleError + pid.o(.text.PID_Calc) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + pid.o(.text.PID_Calc) refers to user_math.o(.text.AbsClip) for AbsClip + pid.o(.ARM.exidx.text.PID_Calc) refers to pid.o(.text.PID_Calc) for [Anonymous Symbol] + pid.o(.ARM.exidx.text.PID_ResetIntegral) refers to pid.o(.text.PID_ResetIntegral) for [Anonymous Symbol] + ui.o(.text) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawLine) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawLine) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawLine) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawLine) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawLine) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawLine) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawLine) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawLine) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawLine) refers to ui.o(.text.UI_DrawLine) for [Anonymous Symbol] + ui.o(.text.UI_DrawRectangle) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawRectangle) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawRectangle) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawRectangle) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawRectangle) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawRectangle) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawRectangle) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawRectangle) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawRectangle) refers to ui.o(.text.UI_DrawRectangle) for [Anonymous Symbol] + ui.o(.text.UI_DrawCycle) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawCycle) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawCycle) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawCycle) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawCycle) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawCycle) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawCycle) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawCycle) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawCycle) refers to ui.o(.text.UI_DrawCycle) for [Anonymous Symbol] + ui.o(.text.UI_DrawOval) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawOval) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawOval) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawOval) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawOval) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawOval) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawOval) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawOval) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawOval) refers to ui.o(.text.UI_DrawOval) for [Anonymous Symbol] + ui.o(.text.UI_DrawArc) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawArc) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawArc) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawArc) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawArc) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawArc) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawArc) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawArc) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawArc) refers to ui.o(.text.UI_DrawArc) for [Anonymous Symbol] + ui.o(.text.UI_DrawFloating) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawFloating) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawFloating) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawFloating) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawFloating) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawFloating) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawFloating) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawFloating) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawFloating) refers to ui.o(.text.UI_DrawFloating) for [Anonymous Symbol] + ui.o(.text.UI_DrawInteger) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawInteger) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawInteger) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawInteger) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawInteger) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawInteger) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawInteger) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawInteger) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawInteger) refers to ui.o(.text.UI_DrawInteger) for [Anonymous Symbol] + ui.o(.text.UI_DrawCharacter) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DrawCharacter) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DrawCharacter) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.text.UI_DrawCharacter) refers to ui.o(.rodata.str1.1) for .L.str + ui.o(.text.UI_DrawCharacter) refers to noretval__2snprintf.o(.text) for __2snprintf + ui.o(.ARM.exidx.text.UI_DrawCharacter) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DrawCharacter) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DrawCharacter) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DrawCharacter) refers to ui.o(.text.UI_DrawCharacter) for [Anonymous Symbol] + ui.o(.text.UI_DelLayer) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.text.UI_DelLayer) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.text.UI_DelLayer) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DelLayer) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.ARM.exidx.text.UI_DelLayer) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.ARM.exidx.text.UI_DelLayer) refers (Special) to _printf_str.o(.text) for _printf_str + ui.o(.ARM.exidx.text.UI_DelLayer) refers to ui.o(.text.UI_DelLayer) for [Anonymous Symbol] + ui.o(.rodata.str1.1) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + ui.o(.rodata.str1.1) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + ui.o(.rodata.str1.1) refers (Special) to _printf_str.o(.text) for _printf_str + user_math.o(.ARM.exidx.text.InvSqrt) refers to user_math.o(.text.InvSqrt) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.AbsClip) refers to user_math.o(.text.AbsClip) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.fAbs) refers to user_math.o(.text.fAbs) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.Clip) refers to user_math.o(.text.Clip) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.Sign) refers to user_math.o(.text.Sign) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.ResetMoveVector) refers to user_math.o(.text.ResetMoveVector) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.CircleError) refers to user_math.o(.text.CircleError) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.CircleAdd) refers to user_math.o(.text.CircleAdd) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.CircleReverse) refers to user_math.o(.text.CircleReverse) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.CalculateRpm) refers to user_math.o(.text.CalculateRpm) for [Anonymous Symbol] + user_math.o(.ARM.exidx.text.ScaleSumTo1) refers to user_math.o(.text.ScaleSumTo1) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_Init) refers to cmd.o(.text.CMD_Init) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_CheckHostOverwrite) refers to cmd.o(.text.CMD_CheckHostOverwrite) for [Anonymous Symbol] + cmd.o(.text.CMD_ParseRc) refers to cmd.o(.text.CMD_KeyPressedRc) for CMD_KeyPressedRc + cmd.o(.text.CMD_ParseRc) refers to cmd.o(.text.CMD_PcLogic) for CMD_PcLogic + cmd.o(.text.CMD_ParseRc) refers to cmd.o(.text.CMD_RcLostLogic) for CMD_RcLostLogic + cmd.o(.text.CMD_ParseRc) refers to cmd.o(.text.CMD_RcLogic) for CMD_RcLogic + cmd.o(.ARM.exidx.text.CMD_ParseRc) refers to cmd.o(.text.CMD_ParseRc) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_KeyPressedRc) refers to cmd.o(.text.CMD_KeyPressedRc) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_RcLostLogic) refers to cmd.o(.text.CMD_RcLostLogic) for [Anonymous Symbol] + cmd.o(.text.CMD_PcLogic) refers to cmd.o(.text.CMD_BehaviorOccurredRc) for CMD_BehaviorOccurredRc + cmd.o(.text.CMD_PcLogic) refers to cmd.o(.text.CMD_RefereeAdd) for CMD_RefereeAdd + cmd.o(.ARM.exidx.text.CMD_PcLogic) refers to cmd.o(.text.CMD_PcLogic) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_RcLogic) refers to cmd.o(.text.CMD_RcLogic) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_ParseHost) refers to cmd.o(.text.CMD_ParseHost) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_RefereeAdd) refers to cmd.o(.text.CMD_RefereeAdd) for [Anonymous Symbol] + cmd.o(.text.CMD_BehaviorOccurredRc) refers to cmd.o(.text.CMD_BehaviorToKey) for CMD_BehaviorToKey + cmd.o(.text.CMD_BehaviorOccurredRc) refers to cmd.o(.text.CMD_BehaviorToActive) for CMD_BehaviorToActive + cmd.o(.ARM.exidx.text.CMD_BehaviorOccurredRc) refers to cmd.o(.text.CMD_BehaviorOccurredRc) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_BehaviorToKey) refers to cmd.o(.text.CMD_BehaviorToKey) for [Anonymous Symbol] + cmd.o(.ARM.exidx.text.CMD_BehaviorToActive) refers to cmd.o(.text.CMD_BehaviorToActive) for [Anonymous Symbol] + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.bss.inited) for inited + bmi088.o(.text.BMI088_Init) refers to cmsis_os2.o(.text.osThreadGetId) for osThreadGetId + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.bss.thread_alert) for thread_alert + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.text.BMI_WriteSingle) for BMI_WriteSingle + bmi088.o(.text.BMI088_Init) refers to time.o(.text.BSP_TIME_Delay_ms) for BSP_TIME_Delay + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.text.BMI_ReadSingle) for BMI_ReadSingle + bmi088.o(.text.BMI088_Init) refers to gpio_1.o(.text.BSP_GPIO_DisableIRQ) for BSP_GPIO_DisableIRQ + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.text.BMI088_RxCpltCallback) for BMI088_RxCpltCallback + bmi088.o(.text.BMI088_Init) refers to spi_1.o(.text.BSP_SPI_RegisterCallback) for BSP_SPI_RegisterCallback + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.text.BMI088_AcclIntCallback) for BMI088_AcclIntCallback + bmi088.o(.text.BMI088_Init) refers to gpio_1.o(.text.BSP_GPIO_RegisterCallback) for BSP_GPIO_RegisterCallback + bmi088.o(.text.BMI088_Init) refers to bmi088.o(.text.BMI088_GyroIntCallback) for BMI088_GyroIntCallback + bmi088.o(.text.BMI088_Init) refers to gpio_1.o(.text.BSP_GPIO_EnableIRQ) for BSP_GPIO_EnableIRQ + bmi088.o(.ARM.exidx.text.BMI088_Init) refers to bmi088.o(.text.BMI088_Init) for [Anonymous Symbol] + bmi088.o(.text.BMI_WriteSingle) refers to bmi088.o(.bss.buffer) for buffer + bmi088.o(.text.BMI_WriteSingle) refers to time.o(.text.BSP_TIME_Delay_ms) for BSP_TIME_Delay + bmi088.o(.text.BMI_WriteSingle) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for BSP_GPIO_WritePin + bmi088.o(.text.BMI_WriteSingle) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + bmi088.o(.ARM.exidx.text.BMI_WriteSingle) refers to bmi088.o(.text.BMI_WriteSingle) for [Anonymous Symbol] + bmi088.o(.text.BMI_ReadSingle) refers to time.o(.text.BSP_TIME_Delay_ms) for BSP_TIME_Delay + bmi088.o(.text.BMI_ReadSingle) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for BSP_GPIO_WritePin + bmi088.o(.text.BMI_ReadSingle) refers to bmi088.o(.bss.buffer) for buffer + bmi088.o(.text.BMI_ReadSingle) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + bmi088.o(.text.BMI_ReadSingle) refers to spi_1.o(.text.BSP_SPI_Receive) for BSP_SPI_Receive + bmi088.o(.ARM.exidx.text.BMI_ReadSingle) refers to bmi088.o(.text.BMI_ReadSingle) for [Anonymous Symbol] + bmi088.o(.text.BMI088_RxCpltCallback) refers to gpio_1.o(.text.BSP_GPIO_ReadPin) for BSP_GPIO_ReadPin + bmi088.o(.text.BMI088_RxCpltCallback) refers to bmi088.o(.bss.thread_alert) for thread_alert + bmi088.o(.text.BMI088_RxCpltCallback) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for BSP_GPIO_WritePin + bmi088.o(.text.BMI088_RxCpltCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + bmi088.o(.ARM.exidx.text.BMI088_RxCpltCallback) refers to bmi088.o(.text.BMI088_RxCpltCallback) for [Anonymous Symbol] + bmi088.o(.text.BMI088_AcclIntCallback) refers to bmi088.o(.bss.thread_alert) for thread_alert + bmi088.o(.text.BMI088_AcclIntCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + bmi088.o(.ARM.exidx.text.BMI088_AcclIntCallback) refers to bmi088.o(.text.BMI088_AcclIntCallback) for [Anonymous Symbol] + bmi088.o(.text.BMI088_GyroIntCallback) refers to bmi088.o(.bss.thread_alert) for thread_alert + bmi088.o(.text.BMI088_GyroIntCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + bmi088.o(.ARM.exidx.text.BMI088_GyroIntCallback) refers to bmi088.o(.text.BMI088_GyroIntCallback) for [Anonymous Symbol] + bmi088.o(.ARM.exidx.text.BMI088_GyroStable) refers to bmi088.o(.text.BMI088_GyroStable) for [Anonymous Symbol] + bmi088.o(.text.BMI088_WaitNew) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + bmi088.o(.ARM.exidx.text.BMI088_WaitNew) refers to bmi088.o(.text.BMI088_WaitNew) for [Anonymous Symbol] + bmi088.o(.text.BMI088_AcclStartDmaRecv) refers to bmi088.o(.bss.bmi088_rxbuf) for bmi088_rxbuf + bmi088.o(.text.BMI088_AcclStartDmaRecv) refers to bmi088.o(.text.BMI_Read) for BMI_Read + bmi088.o(.ARM.exidx.text.BMI088_AcclStartDmaRecv) refers to bmi088.o(.text.BMI088_AcclStartDmaRecv) for [Anonymous Symbol] + bmi088.o(.text.BMI_Read) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for BSP_GPIO_WritePin + bmi088.o(.text.BMI_Read) refers to bmi088.o(.bss.buffer) for buffer + bmi088.o(.text.BMI_Read) refers to spi_1.o(.text.BSP_SPI_Transmit) for BSP_SPI_Transmit + bmi088.o(.text.BMI_Read) refers to spi_1.o(.text.BSP_SPI_Receive) for BSP_SPI_Receive + bmi088.o(.ARM.exidx.text.BMI_Read) refers to bmi088.o(.text.BMI_Read) for [Anonymous Symbol] + bmi088.o(.text.BMI088_AcclWaitDmaCplt) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + bmi088.o(.ARM.exidx.text.BMI088_AcclWaitDmaCplt) refers to bmi088.o(.text.BMI088_AcclWaitDmaCplt) for [Anonymous Symbol] + bmi088.o(.text.BMI088_GyroStartDmaRecv) refers to bmi088.o(.bss.bmi088_rxbuf) for bmi088_rxbuf + bmi088.o(.text.BMI088_GyroStartDmaRecv) refers to bmi088.o(.text.BMI_Read) for BMI_Read + bmi088.o(.ARM.exidx.text.BMI088_GyroStartDmaRecv) refers to bmi088.o(.text.BMI088_GyroStartDmaRecv) for [Anonymous Symbol] + bmi088.o(.text.BMI088_GyroWaitDmaCplt) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + bmi088.o(.ARM.exidx.text.BMI088_GyroWaitDmaCplt) refers to bmi088.o(.text.BMI088_GyroWaitDmaCplt) for [Anonymous Symbol] + bmi088.o(.text.BMI088_ParseAccl) refers to bmi088.o(.bss.bmi088_rxbuf) for bmi088_rxbuf + bmi088.o(.ARM.exidx.text.BMI088_ParseAccl) refers to bmi088.o(.text.BMI088_ParseAccl) for [Anonymous Symbol] + bmi088.o(.text.BMI088_ParseGyro) refers to bmi088.o(.bss.bmi088_rxbuf) for bmi088_rxbuf + bmi088.o(.ARM.exidx.text.BMI088_ParseGyro) refers to bmi088.o(.text.BMI088_ParseGyro) for [Anonymous Symbol] + bmi088.o(.ARM.exidx.text.BMI088_GetUpdateFreq) refers to bmi088.o(.text.BMI088_GetUpdateFreq) for [Anonymous Symbol] + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.bss.inited) for inited + ist8310.o(.text.IST8310_Init) refers to cmsis_os2.o(.text.osThreadGetId) for osThreadGetId + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.bss.thread_alert) for thread_alert + ist8310.o(.text.IST8310_Init) refers to gpio_1.o(.text.BSP_GPIO_WritePin) for BSP_GPIO_WritePin + ist8310.o(.text.IST8310_Init) refers to time.o(.text.BSP_TIME_Delay_ms) for BSP_TIME_Delay + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.text.IST8310_ReadSingle) for IST8310_ReadSingle + ist8310.o(.text.IST8310_Init) refers to gpio_1.o(.text.BSP_GPIO_DisableIRQ) for BSP_GPIO_DisableIRQ + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.text.IST8310_MemRxCpltCallback) for IST8310_MemRxCpltCallback + ist8310.o(.text.IST8310_Init) refers to i2c_1.o(.text.BSP_I2C_RegisterCallback) for BSP_I2C_RegisterCallback + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.text.IST8310_IntCallback) for IST8310_IntCallback + ist8310.o(.text.IST8310_Init) refers to gpio_1.o(.text.BSP_GPIO_RegisterCallback) for BSP_GPIO_RegisterCallback + ist8310.o(.text.IST8310_Init) refers to ist8310.o(.text.IST8310_WriteSingle) for IST8310_WriteSingle + ist8310.o(.text.IST8310_Init) refers to gpio_1.o(.text.BSP_GPIO_EnableIRQ) for BSP_GPIO_EnableIRQ + ist8310.o(.ARM.exidx.text.IST8310_Init) refers to ist8310.o(.text.IST8310_Init) for [Anonymous Symbol] + ist8310.o(.text.IST8310_ReadSingle) refers to i2c_1.o(.text.BSP_I2C_MemReadByte) for BSP_I2C_MemReadByte + ist8310.o(.ARM.exidx.text.IST8310_ReadSingle) refers to ist8310.o(.text.IST8310_ReadSingle) for [Anonymous Symbol] + ist8310.o(.text.IST8310_MemRxCpltCallback) refers to ist8310.o(.bss.thread_alert) for thread_alert + ist8310.o(.text.IST8310_MemRxCpltCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + ist8310.o(.ARM.exidx.text.IST8310_MemRxCpltCallback) refers to ist8310.o(.text.IST8310_MemRxCpltCallback) for [Anonymous Symbol] + ist8310.o(.text.IST8310_IntCallback) refers to ist8310.o(.bss.thread_alert) for thread_alert + ist8310.o(.text.IST8310_IntCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + ist8310.o(.ARM.exidx.text.IST8310_IntCallback) refers to ist8310.o(.text.IST8310_IntCallback) for [Anonymous Symbol] + ist8310.o(.text.IST8310_WriteSingle) refers to i2c_1.o(.text.BSP_I2C_MemWriteByte) for BSP_I2C_MemWriteByte + ist8310.o(.ARM.exidx.text.IST8310_WriteSingle) refers to ist8310.o(.text.IST8310_WriteSingle) for [Anonymous Symbol] + ist8310.o(.text.IST8310_WaitNew) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + ist8310.o(.ARM.exidx.text.IST8310_WaitNew) refers to ist8310.o(.text.IST8310_WaitNew) for [Anonymous Symbol] + ist8310.o(.text.IST8310_StartDmaRecv) refers to ist8310.o(.text.IST8310_Read) for IST8310_Read + ist8310.o(.ARM.exidx.text.IST8310_StartDmaRecv) refers to ist8310.o(.text.IST8310_StartDmaRecv) for [Anonymous Symbol] + ist8310.o(.text.IST8310_Read) refers to ist8310.o(.bss.ist8310_rxbuf) for ist8310_rxbuf + ist8310.o(.text.IST8310_Read) refers to i2c_1.o(.text.BSP_I2C_MemRead) for BSP_I2C_MemRead + ist8310.o(.ARM.exidx.text.IST8310_Read) refers to ist8310.o(.text.IST8310_Read) for [Anonymous Symbol] + ist8310.o(.text.IST8310_WaitDmaCplt) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + ist8310.o(.ARM.exidx.text.IST8310_WaitDmaCplt) refers to ist8310.o(.text.IST8310_WaitDmaCplt) for [Anonymous Symbol] + ist8310.o(.text.IST8310_Parse) refers to ist8310.o(.bss.ist8310_rxbuf) for ist8310_rxbuf + ist8310.o(.ARM.exidx.text.IST8310_Parse) refers to ist8310.o(.text.IST8310_Parse) for [Anonymous Symbol] + motor.o(.ARM.exidx.text.MOTOR_GetRotorAbsAngle) refers to motor.o(.text.MOTOR_GetRotorAbsAngle) for [Anonymous Symbol] + motor.o(.ARM.exidx.text.MOTOR_GetRotorSpeed) refers to motor.o(.text.MOTOR_GetRotorSpeed) for [Anonymous Symbol] + motor.o(.ARM.exidx.text.MOTOR_GetTorqueCurrent) refers to motor.o(.text.MOTOR_GetTorqueCurrent) for [Anonymous Symbol] + motor.o(.ARM.exidx.text.MOTOR_GetTemp) refers to motor.o(.text.MOTOR_GetTemp) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_Register) refers to motor_rm.o(.text.MOTOR_RM_CreateCANManager) for MOTOR_RM_CreateCANManager + motor_rm.o(.text.MOTOR_RM_Register) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.text.MOTOR_RM_Register) refers to mm.o(.text.BSP_Malloc) for BSP_Malloc + motor_rm.o(.text.MOTOR_RM_Register) refers to rt_memclr_w.o(.text) for __aeabi_memclr8 + motor_rm.o(.text.MOTOR_RM_Register) refers to can_1.o(.text.BSP_CAN_RegisterId) for BSP_CAN_RegisterId + motor_rm.o(.text.MOTOR_RM_Register) refers to mm.o(.text.BSP_Free) for BSP_Free + motor_rm.o(.ARM.exidx.text.MOTOR_RM_Register) refers to motor_rm.o(.text.MOTOR_RM_Register) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_CreateCANManager) refers to motor_rm.o(.bss.can_managers) for can_managers + motor_rm.o(.text.MOTOR_RM_CreateCANManager) refers to mm.o(.text.BSP_Malloc) for BSP_Malloc + motor_rm.o(.text.MOTOR_RM_CreateCANManager) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + motor_rm.o(.ARM.exidx.text.MOTOR_RM_CreateCANManager) refers to motor_rm.o(.text.MOTOR_RM_CreateCANManager) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_GetCANManager) refers to motor_rm.o(.bss.can_managers) for can_managers + motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetCANManager) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_Update) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.text.MOTOR_RM_Update) refers to can_1.o(.text.BSP_CAN_GetMessage) for BSP_CAN_GetMessage + motor_rm.o(.text.MOTOR_RM_Update) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get + motor_rm.o(.text.MOTOR_RM_Update) refers to motor_rm.o(.text.Motor_RM_Decode) for Motor_RM_Decode + motor_rm.o(.ARM.exidx.text.MOTOR_RM_Update) refers to motor_rm.o(.text.MOTOR_RM_Update) for [Anonymous Symbol] + motor_rm.o(.text.Motor_RM_Decode) refers to motor_rm.o(.text.MOTOR_RM_GetLSB) for MOTOR_RM_GetLSB + motor_rm.o(.text.Motor_RM_Decode) refers to motor_rm.o(.text.MOTOR_RM_GetRatio) for MOTOR_RM_GetRatio + motor_rm.o(.ARM.exidx.text.Motor_RM_Decode) refers to motor_rm.o(.text.Motor_RM_Decode) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_UpdateAll) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.text.MOTOR_RM_UpdateAll) refers to motor_rm.o(.text.MOTOR_RM_Update) for MOTOR_RM_Update + motor_rm.o(.ARM.exidx.text.MOTOR_RM_UpdateAll) refers to motor_rm.o(.text.MOTOR_RM_UpdateAll) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_SetOutput) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.text.MOTOR_RM_SetOutput) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for MOTOR_RM_GetMotor + motor_rm.o(.text.MOTOR_RM_SetOutput) refers to motor_rm.o(.text.MOTOR_RM_GetLogicalIndex) for MOTOR_RM_GetLogicalIndex + motor_rm.o(.text.MOTOR_RM_SetOutput) refers to motor_rm.o(.text.MOTOR_RM_GetLSB) for MOTOR_RM_GetLSB + motor_rm.o(.ARM.exidx.text.MOTOR_RM_SetOutput) refers to motor_rm.o(.text.MOTOR_RM_SetOutput) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_GetMotor) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetMotor) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for [Anonymous Symbol] + motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetLogicalIndex) refers to motor_rm.o(.text.MOTOR_RM_GetLogicalIndex) for [Anonymous Symbol] + motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetLSB) refers to motor_rm.o(.text.MOTOR_RM_GetLSB) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_Ctrl) refers to motor_rm.o(.text.MOTOR_RM_GetCANManager) for MOTOR_RM_GetCANManager + motor_rm.o(.text.MOTOR_RM_Ctrl) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for BSP_CAN_TransmitStdDataFrame + motor_rm.o(.ARM.exidx.text.MOTOR_RM_Ctrl) refers to motor_rm.o(.text.MOTOR_RM_Ctrl) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_Relax) refers to motor_rm.o(.text.MOTOR_RM_SetOutput) for MOTOR_RM_SetOutput + motor_rm.o(.ARM.exidx.text.MOTOR_RM_Relax) refers to motor_rm.o(.text.MOTOR_RM_Relax) for [Anonymous Symbol] + motor_rm.o(.text.MOTOR_RM_Offine) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for MOTOR_RM_GetMotor + motor_rm.o(.ARM.exidx.text.MOTOR_RM_Offine) refers to motor_rm.o(.text.MOTOR_RM_Offine) for [Anonymous Symbol] + motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetRatio) refers to motor_rm.o(.text.MOTOR_RM_GetRatio) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_Register) refers to motor_dm.o(.text.MOTOR_DM_CreateCANManager) for MOTOR_DM_CreateCANManager + motor_dm.o(.text.MOTOR_DM_Register) refers to motor_dm.o(.text.MOTOR_DM_GetCANManager) for MOTOR_DM_GetCANManager + motor_dm.o(.text.MOTOR_DM_Register) refers to mm.o(.text.BSP_Malloc) for BSP_Malloc + motor_dm.o(.text.MOTOR_DM_Register) refers to rt_memclr_w.o(.text) for __aeabi_memclr8 + motor_dm.o(.text.MOTOR_DM_Register) refers to can_1.o(.text.BSP_CAN_RegisterId) for BSP_CAN_RegisterId + motor_dm.o(.text.MOTOR_DM_Register) refers to mm.o(.text.BSP_Free) for BSP_Free + motor_dm.o(.ARM.exidx.text.MOTOR_DM_Register) refers to motor_dm.o(.text.MOTOR_DM_Register) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_CreateCANManager) refers to motor_dm.o(.bss.can_managers) for can_managers + motor_dm.o(.text.MOTOR_DM_CreateCANManager) refers to mm.o(.text.BSP_Malloc) for BSP_Malloc + motor_dm.o(.text.MOTOR_DM_CreateCANManager) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + motor_dm.o(.ARM.exidx.text.MOTOR_DM_CreateCANManager) refers to motor_dm.o(.text.MOTOR_DM_CreateCANManager) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_GetCANManager) refers to motor_dm.o(.bss.can_managers) for can_managers + motor_dm.o(.ARM.exidx.text.MOTOR_DM_GetCANManager) refers to motor_dm.o(.text.MOTOR_DM_GetCANManager) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_Update) refers to motor_dm.o(.text.MOTOR_DM_GetCANManager) for MOTOR_DM_GetCANManager + motor_dm.o(.text.MOTOR_DM_Update) refers to can_1.o(.text.BSP_CAN_GetMessage) for BSP_CAN_GetMessage + motor_dm.o(.text.MOTOR_DM_Update) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get + motor_dm.o(.text.MOTOR_DM_Update) refers to motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame) for MOTOR_DM_ParseFeedbackFrame + motor_dm.o(.ARM.exidx.text.MOTOR_DM_Update) refers to motor_dm.o(.text.MOTOR_DM_Update) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame) refers to motor_dm.o(.text.uint_to_float) for uint_to_float + motor_dm.o(.ARM.exidx.text.MOTOR_DM_ParseFeedbackFrame) refers to motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_UpdateAll) refers to motor_dm.o(.text.MOTOR_DM_GetCANManager) for MOTOR_DM_GetCANManager + motor_dm.o(.text.MOTOR_DM_UpdateAll) refers to motor_dm.o(.text.MOTOR_DM_Update) for MOTOR_DM_Update + motor_dm.o(.ARM.exidx.text.MOTOR_DM_UpdateAll) refers to motor_dm.o(.text.MOTOR_DM_UpdateAll) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_MITCtrl) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + motor_dm.o(.text.MOTOR_DM_MITCtrl) refers to motor_dm.o(.text.MOTOR_DM_SendMITCmd) for MOTOR_DM_SendMITCmd + motor_dm.o(.ARM.exidx.text.MOTOR_DM_MITCtrl) refers to motor_dm.o(.text.MOTOR_DM_MITCtrl) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_GetMotor) refers to motor_dm.o(.text.MOTOR_DM_GetCANManager) for MOTOR_DM_GetCANManager + motor_dm.o(.ARM.exidx.text.MOTOR_DM_GetMotor) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_SendMITCmd) refers to motor_dm.o(.text.float_to_uint) for float_to_uint + motor_dm.o(.text.MOTOR_DM_SendMITCmd) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for BSP_CAN_TransmitStdDataFrame + motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendMITCmd) refers to motor_dm.o(.text.MOTOR_DM_SendMITCmd) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_PosVelCtrl) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + motor_dm.o(.text.MOTOR_DM_PosVelCtrl) refers to motor_dm.o(.text.MOTOR_DM_SendPosVelCmd) for MOTOR_DM_SendPosVelCmd + motor_dm.o(.ARM.exidx.text.MOTOR_DM_PosVelCtrl) refers to motor_dm.o(.text.MOTOR_DM_PosVelCtrl) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_SendPosVelCmd) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for BSP_CAN_TransmitStdDataFrame + motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendPosVelCmd) refers to motor_dm.o(.text.MOTOR_DM_SendPosVelCmd) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_VelCtrl) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + motor_dm.o(.text.MOTOR_DM_VelCtrl) refers to motor_dm.o(.text.MOTOR_DM_SendVelCmd) for MOTOR_DM_SendVelCmd + motor_dm.o(.ARM.exidx.text.MOTOR_DM_VelCtrl) refers to motor_dm.o(.text.MOTOR_DM_VelCtrl) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_SendVelCmd) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for BSP_CAN_TransmitStdDataFrame + motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendVelCmd) refers to motor_dm.o(.text.MOTOR_DM_SendVelCmd) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_Enable) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + motor_dm.o(.text.MOTOR_DM_Enable) refers to can_1.o(.text.BSP_CAN_TransmitStdDataFrame) for BSP_CAN_TransmitStdDataFrame + motor_dm.o(.ARM.exidx.text.MOTOR_DM_Enable) refers to motor_dm.o(.text.MOTOR_DM_Enable) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_Relax) refers to motor_dm.o(.text.MOTOR_DM_MITCtrl) for MOTOR_DM_MITCtrl + motor_dm.o(.ARM.exidx.text.MOTOR_DM_Relax) refers to motor_dm.o(.text.MOTOR_DM_Relax) for [Anonymous Symbol] + motor_dm.o(.text.MOTOR_DM_Offine) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + motor_dm.o(.ARM.exidx.text.MOTOR_DM_Offine) refers to motor_dm.o(.text.MOTOR_DM_Offine) for [Anonymous Symbol] + motor_dm.o(.ARM.exidx.text.uint_to_float) refers to motor_dm.o(.text.uint_to_float) for [Anonymous Symbol] + motor_dm.o(.ARM.exidx.text.float_to_uint) refers to motor_dm.o(.text.float_to_uint) for [Anonymous Symbol] + ai.o(.text.AI_Init) refers to uart.o(.text.BSP_UART_RegisterCallback) for BSP_UART_RegisterCallback + ai.o(.ARM.exidx.text.AI_Init) refers to ai.o(.text.AI_Init) for [Anonymous Symbol] + ai.o(.text.AI_StartReceiving) refers to uart.o(.text.BSP_UART_Receive) for BSP_UART_Receive + ai.o(.ARM.exidx.text.AI_StartReceiving) refers to ai.o(.text.AI_StartReceiving) for [Anonymous Symbol] + ai.o(.text.AI_Get_NUC) refers to crc16.o(.text.CRC16_Verify) for CRC16_Verify + ai.o(.ARM.exidx.text.AI_Get_NUC) refers to ai.o(.text.AI_Get_NUC) for [Anonymous Symbol] + ai.o(.text.AI_ParseHost) refers to crc16.o(.text.CRC16_Calc) for CRC16_Calc + ai.o(.text.AI_ParseHost) refers to crc16.o(.text.CRC16_Verify) for CRC16_Verify + ai.o(.ARM.exidx.text.AI_ParseHost) refers to ai.o(.text.AI_ParseHost) for [Anonymous Symbol] + ai.o(.text.AI_StartSend) refers to uart.o(.text.BSP_UART_Transmit) for BSP_UART_Transmit + ai.o(.ARM.exidx.text.AI_StartSend) refers to ai.o(.text.AI_StartSend) for [Anonymous Symbol] + dr16.o(.text.DR16_Init) refers to dr16.o(.bss.inited) for inited + dr16.o(.text.DR16_Init) refers to cmsis_os2.o(.text.osThreadGetId) for osThreadGetId + dr16.o(.text.DR16_Init) refers to dr16.o(.bss.thread_alert) for thread_alert + dr16.o(.text.DR16_Init) refers to dr16.o(.text.DR16_RxCpltCallback) for DR16_RxCpltCallback + dr16.o(.text.DR16_Init) refers to uart.o(.text.BSP_UART_RegisterCallback) for BSP_UART_RegisterCallback + dr16.o(.ARM.exidx.text.DR16_Init) refers to dr16.o(.text.DR16_Init) for [Anonymous Symbol] + dr16.o(.text.DR16_RxCpltCallback) refers to dr16.o(.bss.thread_alert) for thread_alert + dr16.o(.text.DR16_RxCpltCallback) refers to cmsis_os2.o(.text.osThreadFlagsSet) for osThreadFlagsSet + dr16.o(.ARM.exidx.text.DR16_RxCpltCallback) refers to dr16.o(.text.DR16_RxCpltCallback) for [Anonymous Symbol] + dr16.o(.text.DR16_Restart) refers to uart.o(.text.BSP_UART_GetHandle) for BSP_UART_GetHandle + dr16.o(.ARM.exidx.text.DR16_Restart) refers to dr16.o(.text.DR16_Restart) for [Anonymous Symbol] + dr16.o(.text.DR16_StartDmaRecv) refers to uart.o(.text.BSP_UART_GetHandle) for BSP_UART_GetHandle + dr16.o(.text.DR16_StartDmaRecv) refers to stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) for HAL_UART_Receive_DMA + dr16.o(.ARM.exidx.text.DR16_StartDmaRecv) refers to dr16.o(.text.DR16_StartDmaRecv) for [Anonymous Symbol] + dr16.o(.text.DR16_WaitDmaCplt) refers to cmsis_os2.o(.text.osThreadFlagsWait) for osThreadFlagsWait + dr16.o(.ARM.exidx.text.DR16_WaitDmaCplt) refers to dr16.o(.text.DR16_WaitDmaCplt) for [Anonymous Symbol] + dr16.o(.text.DR16_ParseData) refers to dr16.o(.text.DR16_DataCorrupted) for DR16_DataCorrupted + dr16.o(.text.DR16_ParseData) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get_us + dr16.o(.text.DR16_ParseData) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + dr16.o(.ARM.exidx.text.DR16_ParseData) refers to dr16.o(.text.DR16_ParseData) for [Anonymous Symbol] + dr16.o(.ARM.exidx.text.DR16_DataCorrupted) refers to dr16.o(.text.DR16_DataCorrupted) for [Anonymous Symbol] + dr16.o(.text.DR16_Offline) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + dr16.o(.ARM.exidx.text.DR16_Offline) refers to dr16.o(.text.DR16_Offline) for [Anonymous Symbol] + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osKernelLock) for osKernelLock + init.o(.text.Task_Init) refers to shoot_ctrl.o(.text.Task_shoot_ctrl) for Task_shoot_ctrl + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_shoot_ctrl) for attr_shoot_ctrl + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osThreadNew) for osThreadNew + init.o(.text.Task_Init) refers to user_task.o(.bss.task_runtime) for task_runtime + init.o(.text.Task_Init) refers to chassis_ctrl.o(.text.Task_chassis_ctrl) for Task_chassis_ctrl + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_chassis_ctrl) for attr_chassis_ctrl + init.o(.text.Task_Init) refers to gimbal_ctrl.o(.text.Task_gimbal_ctrl) for Task_gimbal_ctrl + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_gimbal_ctrl) for attr_gimbal_ctrl + init.o(.text.Task_Init) refers to dr16_1.o(.text.Task_dr16) for Task_dr16 + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_dr16) for attr_dr16 + init.o(.text.Task_Init) refers to ai_1.o(.text.Task_ai) for Task_ai + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_ai) for attr_ai + init.o(.text.Task_Init) refers to atti_esti.o(.text.Task_atti_esti) for Task_atti_esti + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_atti_esti) for attr_atti_esti + init.o(.text.Task_Init) refers to remote.o(.text.Task_remote) for Task_remote + init.o(.text.Task_Init) refers to user_task.o(.rodata.attr_remote) for attr_remote + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osMessageQueueNew) for osMessageQueueNew + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osKernelUnlock) for osKernelUnlock + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osThreadGetId) for osThreadGetId + init.o(.text.Task_Init) refers to cmsis_os2.o(.text.osThreadTerminate) for osThreadTerminate + init.o(.ARM.exidx.text.Task_Init) refers to init.o(.text.Task_Init) for [Anonymous Symbol] + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + ai_1.o(.text.Task_ai) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + ai_1.o(.text.Task_ai) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + ai_1.o(.text.Task_ai) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osDelay) for osDelay + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + ai_1.o(.text.Task_ai) refers to user_task.o(.bss.task_runtime) for task_runtime + ai_1.o(.text.Task_ai) refers to ai_1.o(.bss.g_feedback) for g_feedback + ai_1.o(.text.Task_ai) refers to ai_1.o(.bss.ai) for ai + ai_1.o(.text.Task_ai) refers to ai_1.o(.bss.ai_cmd) for ai_cmd + ai_1.o(.text.Task_ai) refers to ai.o(.text.AI_StartSend) for AI_StartSend + ai_1.o(.text.Task_ai) refers to ai.o(.text.AI_StartReceiving) for AI_StartReceiving + ai_1.o(.text.Task_ai) refers to ai.o(.text.AI_Get_NUC) for AI_Get_NUC + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osMessageQueueReset) for osMessageQueueReset + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + ai_1.o(.text.Task_ai) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + ai_1.o(.text.Task_ai) refers to ai.o(.text.AI_ParseHost) for AI_ParseHost + ai_1.o(.ARM.exidx.text.Task_ai) refers to ai_1.o(.text.Task_ai) for [Anonymous Symbol] + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + atti_esti.o(.text.Task_atti_esti) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + atti_esti.o(.text.Task_atti_esti) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + atti_esti.o(.text.Task_atti_esti) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osDelay) for osDelay + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.bmi088) for bmi088 + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.data.cali_bmi088) for cali_bmi088 + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_Init) for BMI088_Init + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_GetUpdateFreq) for BMI088_GetUpdateFreq + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.gimbal_ahrs) for gimbal_ahrs + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.magn) for magn + atti_esti.o(.text.Task_atti_esti) refers to ahrs.o(.text.AHRS_Init) for AHRS_Init + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.imu_temp_ctrl_pid) for imu_temp_ctrl_pid + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.rodata.imu_temp_ctrl_pid_param) for imu_temp_ctrl_pid_param + atti_esti.o(.text.Task_atti_esti) refers to pid.o(.text.PID_Init) for PID_Init + atti_esti.o(.text.Task_atti_esti) refers to pwm.o(.text.BSP_PWM_Start) for BSP_PWM_Start + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.ist8310) for ist8310 + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.eulr_to_send) for eulr_to_send + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.gimbal_to_send) for gimbal_to_send + atti_esti.o(.text.Task_atti_esti) refers to user_task.o(.bss.task_runtime) for task_runtime + atti_esti.o(.text.Task_atti_esti) refers to pid.o(.text.PID_Calc) for PID_Calc + atti_esti.o(.text.Task_atti_esti) refers to pwm.o(.text.BSP_PWM_SetComp) for BSP_PWM_SetComp + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osMessageQueueReset) for osMessageQueueReset + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_WaitNew) for BMI088_WaitNew + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_AcclStartDmaRecv) for BMI088_AcclStartDmaRecv + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_AcclWaitDmaCplt) for BMI088_AcclWaitDmaCplt + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_GyroStartDmaRecv) for BMI088_GyroStartDmaRecv + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_GyroWaitDmaCplt) for BMI088_GyroWaitDmaCplt + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osKernelLock) for osKernelLock + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_ParseAccl) for BMI088_ParseAccl + atti_esti.o(.text.Task_atti_esti) refers to bmi088.o(.text.BMI088_ParseGyro) for BMI088_ParseGyro + atti_esti.o(.text.Task_atti_esti) refers to ahrs.o(.text.AHRS_Update) for AHRS_Update + atti_esti.o(.text.Task_atti_esti) refers to ahrs.o(.text.AHRS_GetEulr) for AHRS_GetEulr + atti_esti.o(.text.Task_atti_esti) refers to cmsis_os2.o(.text.osKernelUnlock) for osKernelUnlock + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.jiaozhun) for jiaozhun + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.gyro_sum.0) for gyro_sum.0 + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.gyro_sum.1) for gyro_sum.1 + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.gyro_sum.2) for gyro_sum.2 + atti_esti.o(.text.Task_atti_esti) refers to atti_esti.o(.bss.calib_count) for calib_count + atti_esti.o(.ARM.exidx.text.Task_atti_esti) refers to atti_esti.o(.text.Task_atti_esti) for [Anonymous Symbol] + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to cmsis_os2.o(.text.osDelay) for osDelay + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + chassis_ctrl.o(.text.Task_chassis_ctrl) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + chassis_ctrl.o(.ARM.exidx.text.Task_chassis_ctrl) refers to chassis_ctrl.o(.text.Task_chassis_ctrl) for [Anonymous Symbol] + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + dr16_1.o(.text.Task_dr16) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + dr16_1.o(.text.Task_dr16) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dr16_1.o(.text.Task_dr16) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osDelay) for osDelay + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + dr16_1.o(.text.Task_dr16) refers to dr16_1.o(.bss.dr16) for dr16 + dr16_1.o(.text.Task_dr16) refers to dr16.o(.text.DR16_Init) for DR16_Init + dr16_1.o(.text.Task_dr16) refers to user_task.o(.bss.task_runtime) for task_runtime + dr16_1.o(.text.Task_dr16) refers to dr16.o(.text.DR16_Offline) for DR16_Offline + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osMessageQueueReset) for osMessageQueueReset + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + dr16_1.o(.text.Task_dr16) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + dr16_1.o(.text.Task_dr16) refers to dr16.o(.text.DR16_StartDmaRecv) for DR16_StartDmaRecv + dr16_1.o(.text.Task_dr16) refers to dr16.o(.text.DR16_WaitDmaCplt) for DR16_WaitDmaCplt + dr16_1.o(.text.Task_dr16) refers to dr16.o(.text.DR16_ParseData) for DR16_ParseData + dr16_1.o(.ARM.exidx.text.Task_dr16) refers to dr16_1.o(.text.Task_dr16) for [Anonymous Symbol] + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osDelay) for osDelay + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to config.o(.text.Config_GetRobotParam) for Config_GetRobotParam + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.bss.gimbal) for gimbal + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal.o(.text.Gimbal_Init) for Gimbal_Init + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.bss.gimbal_imu) for gimbal_imu + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.bss.ai_g_cmd) for ai_g_cmd + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to user_task.o(.bss.task_runtime) for task_runtime + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.bss.gimbal_cmd) for gimbal_cmd + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.bss.gimbal_cmd_remote) for gimbal_cmd_remote + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal.o(.text.Gimbal_UpdateFeedback) for Gimbal_UpdateFeedback + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal.o(.text.Gimbal_Control) for Gimbal_Control + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal.o(.text.Gimbal_Output) for Gimbal_Output + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osMessageQueueReset) for osMessageQueueReset + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + gimbal_ctrl.o(.text.Task_gimbal_ctrl) refers to gimbal.o(.text.Gimbal_UpdateIMU) for Gimbal_UpdateIMU + gimbal_ctrl.o(.ARM.exidx.text.Task_gimbal_ctrl) refers to gimbal_ctrl.o(.text.Task_gimbal_ctrl) for [Anonymous Symbol] + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to cmsis_os2.o(.text.osDelay) for osDelay + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to config.o(.text.Config_GetRobotParam) for Config_GetRobotParam + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot_ctrl.o(.bss.shoot) for shoot + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot.o(.text.Shoot_Init) for Shoot_Init + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot.o(.text.Shoot_SetMode) for Shoot_SetMode + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to user_task.o(.bss.task_runtime) for task_runtime + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot_ctrl.o(.bss.shoot_cmd) for shoot_cmd + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot.o(.text.Shoot_UpdateFeedback) for Shoot_UpdateFeedback + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to shoot.o(.text.Shoot_Control) for Shoot_Control + shoot_ctrl.o(.text.Task_shoot_ctrl) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + shoot_ctrl.o(.ARM.exidx.text.Task_shoot_ctrl) refers to shoot_ctrl.o(.text.Task_shoot_ctrl) for [Anonymous Symbol] + user_task.o(.rodata.attr_init) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_shoot_ctrl) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_chassis_ctrl) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_gimbal_ctrl) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_dr16) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_ai) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_atti_esti) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + user_task.o(.rodata.attr_remote) refers to user_task.o(.rodata.str1.1) for [Anonymous Symbol] + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osKernelGetTickFreq) for osKernelGetTickFreq + remote.o(.text.Task_remote) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + remote.o(.text.Task_remote) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + remote.o(.text.Task_remote) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osDelay) for osDelay + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osKernelGetTickCount) for osKernelGetTickCount + remote.o(.text.Task_remote) refers to user_task.o(.bss.task_runtime) for task_runtime + remote.o(.text.Task_remote) refers to remote.o(.bss.remote_dr16) for remote_dr16 + remote.o(.text.Task_remote) refers to remote.o(.bss.g_rc_cmd) for g_rc_cmd + remote.o(.text.Task_remote) refers to remote.o(.bss.s_rc_cmd) for s_rc_cmd + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osMessageQueueGet) for osMessageQueueGet + remote.o(.text.Task_remote) refers to remote_cmd.o(.text.Gimbal_Cmd) for Gimbal_Cmd + remote.o(.text.Task_remote) refers to remote_cmd.o(.text.Shoot_Cmd) for Shoot_Cmd + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osMessageQueueReset) for osMessageQueueReset + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osMessageQueuePut) for osMessageQueuePut + remote.o(.text.Task_remote) refers to cmsis_os2.o(.text.osDelayUntil) for osDelayUntil + remote.o(.ARM.exidx.text.Task_remote) refers to remote.o(.text.Task_remote) for [Anonymous Symbol] + config.o(.text.Config_GetRobotParam) refers to config.o(.data.robot_config) for robot_config + config.o(.ARM.exidx.text.Config_GetRobotParam) refers to config.o(.text.Config_GetRobotParam) for [Anonymous Symbol] + chassis.o(.text.Chassis_Init) refers to can_1.o(.text.BSP_CAN_Init) for BSP_CAN_Init + chassis.o(.text.Chassis_Init) refers to pid.o(.text.PID_Init) for PID_Init + chassis.o(.text.Chassis_Init) refers to filter.o(.text.LowPassFilter2p_Init) for LowPassFilter2p_Init + chassis.o(.text.Chassis_Init) refers to mixer.o(.text.Mixer_Init) for Mixer_Init + chassis.o(.text.Chassis_Init) refers to motor_rm.o(.text.MOTOR_RM_Register) for MOTOR_RM_Register + chassis.o(.ARM.exidx.text.Chassis_Init) refers to chassis.o(.text.Chassis_Init) for [Anonymous Symbol] + chassis.o(.text.Chassis_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_Update) for MOTOR_RM_Update + chassis.o(.text.Chassis_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for MOTOR_RM_GetMotor + chassis.o(.ARM.exidx.text.Chassis_UpdateFeedback) refers to chassis.o(.text.Chassis_UpdateFeedback) for [Anonymous Symbol] + chassis.o(.text.Chassis_Control) refers to ffltll_clz.o(x$fpl$ffltll) for __aeabi_ul2f + chassis.o(.text.Chassis_Control) refers to chassis.o(.text.__ARM_isfinitef) for __ARM_isfinitef + chassis.o(.text.Chassis_Control) refers to chassis.o(.text.Chassis_SetMode) for Chassis_SetMode + chassis.o(.text.Chassis_Control) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + chassis.o(.text.Chassis_Control) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + chassis.o(.text.Chassis_Control) refers to chassis.o(.text.Chassis_CalcWz) for Chassis_CalcWz + chassis.o(.text.Chassis_Control) refers to pid.o(.text.PID_Calc) for PID_Calc + chassis.o(.text.Chassis_Control) refers to mixer.o(.text.Mixer_Apply) for Mixer_Apply + chassis.o(.text.Chassis_Control) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + chassis.o(.text.Chassis_Control) refers to user_math.o(.text.Clip) for Clip + chassis.o(.ARM.exidx.text.Chassis_Control) refers to chassis.o(.text.Chassis_Control) for [Anonymous Symbol] + chassis.o(.ARM.exidx.text.__ARM_isfinitef) refers to chassis.o(.text.__ARM_isfinitef) for [Anonymous Symbol] + chassis.o(.text.Chassis_SetMode) refers to rand.o(.text) for srand + chassis.o(.text.Chassis_SetMode) refers to rand.o(.emb_text) for rand + chassis.o(.text.Chassis_SetMode) refers to pid.o(.text.PID_Reset) for PID_Reset + chassis.o(.text.Chassis_SetMode) refers to filter.o(.text.LowPassFilter2p_Reset) for LowPassFilter2p_Reset + chassis.o(.ARM.exidx.text.Chassis_SetMode) refers to chassis.o(.text.Chassis_SetMode) for [Anonymous Symbol] + chassis.o(.text.Chassis_CalcWz) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + chassis.o(.ARM.exidx.text.Chassis_CalcWz) refers to chassis.o(.text.Chassis_CalcWz) for [Anonymous Symbol] + chassis.o(.text.Chassis_Output) refers to motor_rm.o(.text.MOTOR_RM_SetOutput) for MOTOR_RM_SetOutput + chassis.o(.text.Chassis_Output) refers to motor_rm.o(.text.MOTOR_RM_Ctrl) for MOTOR_RM_Ctrl + chassis.o(.ARM.exidx.text.Chassis_Output) refers to chassis.o(.text.Chassis_Output) for [Anonymous Symbol] + chassis.o(.text.Chassis_ResetOutput) refers to motor_rm.o(.text.MOTOR_RM_Relax) for MOTOR_RM_Relax + chassis.o(.ARM.exidx.text.Chassis_ResetOutput) refers to chassis.o(.text.Chassis_ResetOutput) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_Init) refers to pid.o(.text.PID_Init) for PID_Init + gimbal.o(.text.Gimbal_Init) refers to filter.o(.text.LowPassFilter2p_Init) for LowPassFilter2p_Init + gimbal.o(.text.Gimbal_Init) refers to can_1.o(.text.BSP_CAN_Init) for BSP_CAN_Init + gimbal.o(.text.Gimbal_Init) refers to motor_rm.o(.text.MOTOR_RM_Register) for MOTOR_RM_Register + gimbal.o(.text.Gimbal_Init) refers to motor_dm.o(.text.MOTOR_DM_Register) for MOTOR_DM_Register + gimbal.o(.text.Gimbal_Init) refers to motor_dm.o(.text.MOTOR_DM_Enable) for MOTOR_DM_Enable + gimbal.o(.ARM.exidx.text.Gimbal_Init) refers to gimbal.o(.text.Gimbal_Init) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_Update) for MOTOR_RM_Update + gimbal.o(.text.Gimbal_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for MOTOR_RM_GetMotor + gimbal.o(.text.Gimbal_UpdateFeedback) refers to motor_dm.o(.text.MOTOR_DM_Update) for MOTOR_DM_Update + gimbal.o(.text.Gimbal_UpdateFeedback) refers to motor_dm.o(.text.MOTOR_DM_GetMotor) for MOTOR_DM_GetMotor + gimbal.o(.ARM.exidx.text.Gimbal_UpdateFeedback) refers to gimbal.o(.text.Gimbal_UpdateFeedback) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_UpdateIMU) refers to gimbal.o(.text.Gimbal_Direction) for Gimbal_Direction + gimbal.o(.ARM.exidx.text.Gimbal_UpdateIMU) refers to gimbal.o(.text.Gimbal_UpdateIMU) for [Anonymous Symbol] + gimbal.o(.ARM.exidx.text.Gimbal_Direction) refers to gimbal.o(.text.Gimbal_Direction) for [Anonymous Symbol] + gimbal.o(.ARM.exidx.text.major_yaw_Control) refers to gimbal.o(.text.major_yaw_Control) for [Anonymous Symbol] + gimbal.o(.ARM.exidx.text.Gimbal_Control_mode) refers to gimbal.o(.text.Gimbal_Control_mode) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_Control) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get_us + gimbal.o(.text.Gimbal_Control) refers to ffltll_clz.o(x$fpl$ffltll) for __aeabi_ul2f + gimbal.o(.text.Gimbal_Control) refers to gimbal.o(.text.Gimbal_SetMode) for Gimbal_SetMode + gimbal.o(.text.Gimbal_Control) refers to gimbal.o(.text.major_yaw_Control) for major_yaw_Control + gimbal.o(.text.Gimbal_Control) refers to gimbal.o(.text.motor_imu_offset) for motor_imu_offset + gimbal.o(.text.Gimbal_Control) refers to user_math.o(.text.CircleError) for CircleError + gimbal.o(.text.Gimbal_Control) refers to user_math.o(.text.CircleAdd) for CircleAdd + gimbal.o(.text.Gimbal_Control) refers to user_math.o(.text.Clip) for Clip + gimbal.o(.text.Gimbal_Control) refers to pid.o(.text.PID_Calc) for PID_Calc + gimbal.o(.text.Gimbal_Control) refers to gimbal.o(.text.Gimbal_Control_mode) for Gimbal_Control_mode + gimbal.o(.text.Gimbal_Control) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + gimbal.o(.ARM.exidx.text.Gimbal_Control) refers to gimbal.o(.text.Gimbal_Control) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_SetMode) refers to pid.o(.text.PID_Reset) for PID_Reset + gimbal.o(.text.Gimbal_SetMode) refers to filter.o(.text.LowPassFilter2p_Reset) for LowPassFilter2p_Reset + gimbal.o(.text.Gimbal_SetMode) refers to ahrs.o(.text.AHRS_ResetEulr) for AHRS_ResetEulr + gimbal.o(.ARM.exidx.text.Gimbal_SetMode) refers to gimbal.o(.text.Gimbal_SetMode) for [Anonymous Symbol] + gimbal.o(.ARM.exidx.text.motor_imu_offset) refers to gimbal.o(.text.motor_imu_offset) for [Anonymous Symbol] + gimbal.o(.text.Gimbal_Output) refers to motor_rm.o(.text.MOTOR_RM_Ctrl) for MOTOR_RM_Ctrl + gimbal.o(.text.Gimbal_Output) refers to motor_rm.o(.text.MOTOR_RM_SetOutput) for MOTOR_RM_SetOutput + gimbal.o(.text.Gimbal_Output) refers to motor_dm.o(.text.MOTOR_DM_MITCtrl) for MOTOR_DM_MITCtrl + gimbal.o(.ARM.exidx.text.Gimbal_Output) refers to gimbal.o(.text.Gimbal_Output) for [Anonymous Symbol] + remote_cmd.o(.text.Gimbal_Cmd) refers to dflt_clz.o(x$fpl$dflt) for __aeabi_i2d + remote_cmd.o(.text.Gimbal_Cmd) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + remote_cmd.o(.text.Gimbal_Cmd) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + remote_cmd.o(.text.Gimbal_Cmd) refers to d2f.o(x$fpl$d2f) for __aeabi_d2f + remote_cmd.o(.ARM.exidx.text.Gimbal_Cmd) refers to remote_cmd.o(.text.Gimbal_Cmd) for [Anonymous Symbol] + remote_cmd.o(.ARM.exidx.text.Shoot_Cmd) refers to remote_cmd.o(.text.Shoot_Cmd) for [Anonymous Symbol] + shoot.o(.ARM.exidx.text.Shoot_SetMode) refers to shoot.o(.text.Shoot_SetMode) for [Anonymous Symbol] + shoot.o(.text.Shoot_ResetIntegral) refers to pid.o(.text.PID_ResetIntegral) for PID_ResetIntegral + shoot.o(.ARM.exidx.text.Shoot_ResetIntegral) refers to shoot.o(.text.Shoot_ResetIntegral) for [Anonymous Symbol] + shoot.o(.text.Shoot_ResetCalu) refers to pid.o(.text.PID_Reset) for PID_Reset + shoot.o(.text.Shoot_ResetCalu) refers to filter.o(.text.LowPassFilter2p_Reset) for LowPassFilter2p_Reset + shoot.o(.ARM.exidx.text.Shoot_ResetCalu) refers to shoot.o(.text.Shoot_ResetCalu) for [Anonymous Symbol] + shoot.o(.ARM.exidx.text.Shoot_ResetOutput) refers to shoot.o(.text.Shoot_ResetOutput) for [Anonymous Symbol] + shoot.o(.ARM.exidx.text.Shoot_CaluTargetRPM) refers to shoot.o(.text.Shoot_CaluTargetRPM) for [Anonymous Symbol] + shoot.o(.text.Shoot_CaluTargetAngle) refers to user_math.o(.text.CircleError) for CircleError + shoot.o(.text.Shoot_CaluTargetAngle) refers to user_math.o(.text.CircleAdd) for CircleAdd + shoot.o(.ARM.exidx.text.Shoot_CaluTargetAngle) refers to shoot.o(.text.Shoot_CaluTargetAngle) for [Anonymous Symbol] + shoot.o(.text.Shoot_UpdateFeedback) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + shoot.o(.text.Shoot_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_Update) for MOTOR_RM_Update + shoot.o(.text.Shoot_UpdateFeedback) refers to motor_rm.o(.text.MOTOR_RM_GetMotor) for MOTOR_RM_GetMotor + shoot.o(.text.Shoot_UpdateFeedback) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy8 + shoot.o(.ARM.exidx.text.Shoot_UpdateFeedback) refers to shoot.o(.text.Shoot_UpdateFeedback) for [Anonymous Symbol] + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.bss.last_firecmd) for last_firecmd + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_CaluCoupledWeight) for Shoot_CaluCoupledWeight + shoot.o(.text.Shoot_RunningFSM) refers to pid.o(.text.PID_Calc) for PID_Calc + shoot.o(.text.Shoot_RunningFSM) refers to user_math.o(.text.ScaleSumTo1) for ScaleSumTo1 + shoot.o(.text.Shoot_RunningFSM) refers to filter.o(.text.LowPassFilter2p_Apply) for LowPassFilter2p_Apply + shoot.o(.text.Shoot_RunningFSM) refers to motor_rm.o(.text.MOTOR_RM_SetOutput) for MOTOR_RM_SetOutput + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.bss.Shoot_RunningFSM.pos) for Shoot_RunningFSM.pos + shoot.o(.text.Shoot_RunningFSM) refers to motor_rm.o(.text.MOTOR_RM_Relax) for MOTOR_RM_Relax + shoot.o(.text.Shoot_RunningFSM) refers to pid.o(.text.PID_ResetIntegral) for PID_ResetIntegral + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_ResetCalu) for Shoot_ResetCalu + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_ResetIntegral) for Shoot_ResetIntegral + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_ResetOutput) for Shoot_ResetOutput + shoot.o(.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_CaluTargetAngle) for Shoot_CaluTargetAngle + shoot.o(.text.Shoot_RunningFSM) refers to motor_rm.o(.text.MOTOR_RM_Ctrl) for MOTOR_RM_Ctrl + shoot.o(.ARM.exidx.text.Shoot_RunningFSM) refers to shoot.o(.text.Shoot_RunningFSM) for [Anonymous Symbol] + shoot.o(.ARM.exidx.text.Shoot_CaluCoupledWeight) refers to shoot.o(.text.Shoot_CaluCoupledWeight) for [Anonymous Symbol] + shoot.o(.text.Shoot_JamDetectionFSM) refers to shoot.o(.text.Shoot_RunningFSM) for Shoot_RunningFSM + shoot.o(.ARM.exidx.text.Shoot_JamDetectionFSM) refers to shoot.o(.text.Shoot_JamDetectionFSM) for [Anonymous Symbol] + shoot.o(.text.Shoot_Init) refers to can_1.o(.text.BSP_CAN_Init) for BSP_CAN_Init + shoot.o(.text.Shoot_Init) refers to motor_rm.o(.text.MOTOR_RM_Register) for MOTOR_RM_Register + shoot.o(.text.Shoot_Init) refers to pid.o(.text.PID_Init) for PID_Init + shoot.o(.text.Shoot_Init) refers to filter.o(.text.LowPassFilter2p_Init) for LowPassFilter2p_Init + shoot.o(.ARM.exidx.text.Shoot_Init) refers to shoot.o(.text.Shoot_Init) for [Anonymous Symbol] + shoot.o(.text.Shoot_Control) refers to time.o(.text.BSP_TIME_Get_us) for BSP_TIME_Get_us + shoot.o(.text.Shoot_Control) refers to ffltll_clz.o(x$fpl$ffltll) for __aeabi_ul2f + shoot.o(.text.Shoot_Control) refers to shoot.o(.text.Shoot_CaluTargetRPM) for Shoot_CaluTargetRPM + shoot.o(.text.Shoot_Control) refers to shoot.o(.text.Shoot_JamDetectionFSM) for Shoot_JamDetectionFSM + shoot.o(.ARM.exidx.text.Shoot_Control) refers to shoot.o(.text.Shoot_Control) for [Anonymous Symbol] + __2snprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + __2snprintf.o(.text) refers to _sputc.o(.text) for _sputc + __2snprintf.o(.text) refers to _snputc.o(.text) for _snputc + noretval__2snprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + noretval__2snprintf.o(.text) refers to _sputc.o(.text) for _sputc + noretval__2snprintf.o(.text) refers to _snputc.o(.text) for _snputc + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + rand.o(.emb_text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.emb_text) refers to rand.o(.text) for _rand_init + rand.o(.emb_text) refers to rand.o(.bss) for _random_number_data + rand.o(.text) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rand.o(.text) refers to rand.o(.bss) for .bss + rand.o(.bss) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000D) for __rt_lib_init_rand_2 + rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + aeabi_memset.o(.text) refers to rt_memclr.o(.text) for _memset + aeabi_memset4.o(.text) refers to rt_memclr_w.o(.text) for _memset_w + rt_memclr.o(.text) refers to rt_memclr_w.o(.text) for _memset_w + strncpy.o(.text) refers to rt_memclr.o(.text) for __aeabi_memclr + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + d2f.o(x$fpl$d2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + d2f.o(x$fpl$d2f) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + d2f.o(x$fpl$d2f) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry + ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfixu.o(x$fpl$dfixu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfixu.o(x$fpl$dfixu) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfixu.o(x$fpl$dfixur) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfixu.o(x$fpl$dfixur) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dmul.o(x$fpl$dmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dmul.o(x$fpl$dmul) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + dmul.o(x$fpl$dmul) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + f2d.o(x$fpl$f2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + f2d.o(x$fpl$f2d) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + f2d.o(x$fpl$f2d) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ffltll_clz.o(x$fpl$ffltll) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + asinf.o(i.__hardfp_asinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + asinf.o(i.__hardfp_asinf) refers to sqrtf.o(i.sqrtf) for sqrtf + asinf.o(i.__hardfp_asinf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf + asinf.o(i.__hardfp_asinf) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow + asinf.o(i.__hardfp_asinf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + asinf.o(i.__hardfp_asinf) refers to _rserrno.o(.text) for __set_errno + asinf.o(i.__hardfp_asinf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + asinf.o(i.__softfp_asinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + asinf.o(i.__softfp_asinf) refers to asinf.o(i.__hardfp_asinf) for __hardfp_asinf + asinf.o(i.asinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + asinf.o(i.asinf) refers to asinf.o(i.__hardfp_asinf) for __hardfp_asinf + atan2.o(i.__hardfp_atan2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2.o(i.__hardfp_atan2) refers to dunder.o(i.__mathlib_dbl_infnan2) for __mathlib_dbl_infnan2 + atan2.o(i.__hardfp_atan2) refers to atan.o(i.atan) for atan + atan2.o(i.__hardfp_atan2) refers to basic.o(x$fpl$basic) for __aeabi_dneg + atan2.o(i.__hardfp_atan2) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + atan2.o(i.__hardfp_atan2) refers to fabs.o(i.fabs) for fabs + atan2.o(i.__hardfp_atan2) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + atan2.o(i.__hardfp_atan2) refers to deqf.o(x$fpl$deqf) for __aeabi_cdcmpeq + atan2.o(i.__hardfp_atan2) refers to _rserrno.o(.text) for __set_errno + atan2.o(i.__hardfp_atan2) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + atan2.o(i.__hardfp_atan2) refers to qnan.o(.constdata) for __mathlib_zero + atan2.o(i.__softfp_atan2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2.o(i.__softfp_atan2) refers to atan2.o(i.__hardfp_atan2) for __hardfp_atan2 + atan2.o(i.atan2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2.o(i.atan2) refers to atan2.o(i.__hardfp_atan2) for __hardfp_atan2 + atan2f.o(i.__hardfp_atan2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2f.o(i.__hardfp_atan2f) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf + atan2f.o(i.__hardfp_atan2f) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow + atan2f.o(i.__hardfp_atan2f) refers to _rserrno.o(.text) for __set_errno + atan2f.o(i.__hardfp_atan2f) refers to funder.o(i.__mathlib_flt_infnan2) for __mathlib_flt_infnan2 + atan2f.o(i.__softfp_atan2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2f.o(i.__softfp_atan2f) refers to atan2f.o(i.__hardfp_atan2f) for __hardfp_atan2f + atan2f.o(i.atan2f) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan2f.o(i.atan2f) refers to atan2f.o(i.__hardfp_atan2f) for __hardfp_atan2f + cosf.o(i.__hardfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.__hardfp_cosf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + cosf.o(i.__hardfp_cosf) refers to _rserrno.o(.text) for __set_errno + cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + cosf.o(i.__hardfp_cosf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + cosf.o(i.__softfp_cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.__softfp_cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + cosf.o(i.cosf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cosf.o(i.cosf) refers to cosf.o(i.__hardfp_cosf) for __hardfp_cosf + sinf.o(i.__hardfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.__hardfp_sinf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + sinf.o(i.__hardfp_sinf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow + sinf.o(i.__hardfp_sinf) refers to _rserrno.o(.text) for __set_errno + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + sinf.o(i.__hardfp_sinf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + sinf.o(i.__softfp_sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.__softfp_sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + sinf.o(i.sinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sinf.o(i.sinf) refers to sinf.o(i.__hardfp_sinf) for __hardfp_sinf + tanf.o(i.__hardfp_tanf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanf.o(i.__hardfp_tanf) refers to rredf.o(i.__mathlib_rredf2) for __mathlib_rredf2 + tanf.o(i.__hardfp_tanf) refers to fpclassifyf.o(i.__ARM_fpclassifyf) for __ARM_fpclassifyf + tanf.o(i.__hardfp_tanf) refers to funder.o(i.__mathlib_flt_underflow) for __mathlib_flt_underflow + tanf.o(i.__hardfp_tanf) refers to _rserrno.o(.text) for __set_errno + tanf.o(i.__hardfp_tanf) refers to funder.o(i.__mathlib_flt_invalid) for __mathlib_flt_invalid + tanf.o(i.__hardfp_tanf) refers to funder.o(i.__mathlib_flt_infnan) for __mathlib_flt_infnan + tanf.o(i.__softfp_tanf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanf.o(i.__softfp_tanf) refers to tanf.o(i.__hardfp_tanf) for __hardfp_tanf + tanf.o(i.tanf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + tanf.o(i.tanf) refers to tanf.o(i.__hardfp_tanf) for __hardfp_tanf + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + _rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr + _printf_char_common.o(.text) refers to __printf.o(.text) for __printf + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init + libinit2.o(.ARM.Collect$$libinit$$0000000D) refers (Weak) to rand.o(.text) for _rand_init + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + basic.o(x$fpl$basic) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dadd) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dadd) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + daddsub_clz.o(x$fpl$dadd) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + daddsub_clz.o(x$fpl$drsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dsub) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$dsub) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + deqf.o(x$fpl$deqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + deqf.o(x$fpl$deqf) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + deqf.o(x$fpl$deqf) refers to dcmpi.o(x$fpl$dcmpinf) for __fpl_dcmp_Inf + dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fnaninf.o(x$fpl$fnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fretinf.o(x$fpl$fretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan.o(i.__hardfp_atan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan.o(i.__hardfp_atan) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + atan.o(i.__hardfp_atan) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + atan.o(i.__hardfp_atan) refers to dunder.o(i.__mathlib_dbl_underflow) for __mathlib_dbl_underflow + atan.o(i.__hardfp_atan) refers to fabs.o(i.fabs) for fabs + atan.o(i.__hardfp_atan) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + atan.o(i.__hardfp_atan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + atan.o(i.__hardfp_atan) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + atan.o(i.__hardfp_atan) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + atan.o(i.__hardfp_atan) refers to poly.o(i.__kernel_poly) for __kernel_poly + atan.o(i.__hardfp_atan) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + atan.o(i.__hardfp_atan) refers to basic.o(x$fpl$basic) for __aeabi_dneg + atan.o(i.__hardfp_atan) refers to atan.o(.constdata) for .constdata + atan.o(i.__softfp_atan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan.o(i.__softfp_atan) refers to atan.o(i.__hardfp_atan) for __hardfp_atan + atan.o(i.atan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + atan.o(i.atan) refers to atan.o(i.__hardfp_atan) for __hardfp_atan + atan.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dunder.o(i.__mathlib_dbl_divzero) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_infnan) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + dunder.o(i.__mathlib_dbl_infnan2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + dunder.o(i.__mathlib_dbl_invalid) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_overflow) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + dunder.o(i.__mathlib_dbl_posinfnan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + dunder.o(i.__mathlib_dbl_underflow) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + fabs.o(i.__hardfp_fabs) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fabs.o(i.__softfp_fabs) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fabs.o(i.fabs) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fpclassifyf.o(i.__ARM_fpclassifyf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + qnan.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rredf.o(i.__mathlib_rredf2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rredf.o(i.__mathlib_rredf2) refers to rredf.o(.constdata) for .constdata + rredf.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf.o(i.__hardfp_sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf.o(i.__hardfp_sqrtf) refers to _rserrno.o(.text) for __set_errno + sqrtf.o(i.__softfp_sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf.o(i.__softfp_sqrtf) refers to _rserrno.o(.text) for __set_errno + sqrtf.o(i.sqrtf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrtf.o(i.sqrtf) refers to _rserrno.o(.text) for __set_errno + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data + rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + dcmpi.o(x$fpl$dcmpinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + poly.o(i.__kernel_poly) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f407xx.o(.text) for __user_initial_stackheap + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.text), (0 bytes). + Removing main.o(.ARM.exidx.text.main), (8 bytes). + Removing main.o(.ARM.exidx.text.SystemClock_Config), (8 bytes). + Removing main.o(.ARM.exidx.text.Error_Handler), (8 bytes). + Removing main.o(.ARM.use_no_argv), (4 bytes). + Removing gpio.o(.text), (0 bytes). + Removing gpio.o(.ARM.exidx.text.MX_GPIO_Init), (8 bytes). + Removing freertos.o(.text), (0 bytes). + Removing freertos.o(.ARM.exidx.text.MX_FREERTOS_Init), (8 bytes). + Removing freertos.o(.ARM.exidx.text.StartDefaultTask), (8 bytes). + Removing can.o(.text), (0 bytes). + Removing can.o(.ARM.exidx.text.MX_CAN1_Init), (8 bytes). + Removing can.o(.ARM.exidx.text.MX_CAN2_Init), (8 bytes). + Removing can.o(.ARM.exidx.text.HAL_CAN_MspInit), (8 bytes). + Removing can.o(.text.HAL_CAN_MspDeInit), (174 bytes). + Removing can.o(.ARM.exidx.text.HAL_CAN_MspDeInit), (8 bytes). + Removing dma.o(.text), (0 bytes). + Removing dma.o(.ARM.exidx.text.MX_DMA_Init), (8 bytes). + Removing i2c.o(.text), (0 bytes). + Removing i2c.o(.ARM.exidx.text.MX_I2C2_Init), (8 bytes). + Removing i2c.o(.ARM.exidx.text.HAL_I2C_MspInit), (8 bytes). + Removing i2c.o(.text.HAL_I2C_MspDeInit), (56 bytes). + Removing i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit), (8 bytes). + Removing spi.o(.text), (0 bytes). + Removing spi.o(.ARM.exidx.text.MX_SPI1_Init), (8 bytes). + Removing spi.o(.ARM.exidx.text.HAL_SPI_MspInit), (8 bytes). + Removing spi.o(.text.HAL_SPI_MspDeInit), (70 bytes). + Removing spi.o(.ARM.exidx.text.HAL_SPI_MspDeInit), (8 bytes). + Removing tim.o(.text), (0 bytes). + Removing tim.o(.ARM.exidx.text.MX_TIM10_Init), (8 bytes). + Removing tim.o(.ARM.exidx.text.HAL_TIM_MspPostInit), (8 bytes). + Removing tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes). + Removing tim.o(.text.HAL_TIM_Base_MspDeInit), (34 bytes). + Removing tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit), (8 bytes). + Removing usart.o(.text), (0 bytes). + Removing usart.o(.ARM.exidx.text.MX_USART1_UART_Init), (8 bytes). + Removing usart.o(.ARM.exidx.text.MX_USART2_UART_Init), (8 bytes). + Removing usart.o(.ARM.exidx.text.MX_USART3_UART_Init), (8 bytes). + Removing usart.o(.ARM.exidx.text.MX_USART6_UART_Init), (8 bytes). + Removing usart.o(.ARM.exidx.text.HAL_UART_MspInit), (8 bytes). + Removing usart.o(.text.HAL_UART_MspDeInit), (242 bytes). + Removing usart.o(.ARM.exidx.text.HAL_UART_MspDeInit), (8 bytes). + Removing stm32f4xx_it.o(.text), (0 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.NMI_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.HardFault_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.MemManage_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.BusFault_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.UsageFault_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.DebugMon_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.SysTick_Handler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.EXTI0_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.EXTI3_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.EXTI4_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.DMA1_Stream1_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN1_TX_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN1_RX0_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN1_RX1_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN1_SCE_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.EXTI9_5_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.USART1_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.USART2_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.DMA2_Stream2_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.DMA2_Stream3_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN2_TX_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN2_RX1_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.CAN2_SCE_IRQHandler), (8 bytes). + Removing stm32f4xx_it.o(.ARM.exidx.text.USART6_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_msp.o(.text), (0 bytes). + Removing stm32f4xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32f4xx_hal_can.o(.text), (0 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Init), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_MspInit), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_MspInit), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_DeInit), (42 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_DeInit), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_Stop), (94 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Stop), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ConfigFilter), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_Start), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_RequestSleep), (36 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RequestSleep), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_WakeUp), (82 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_WakeUp), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_IsSleepActive), (24 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IsSleepActive), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_AddTxMessage), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_AbortTxRequest), (78 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_AbortTxRequest), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetTxMailboxesFreeLevel), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_IsTxMessagePending), (32 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IsTxMessagePending), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxTimestamp), (36 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetTxTimestamp), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetRxMessage), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetRxFifoFillLevel), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ActivateNotification), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_DeactivateNotification), (36 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_DeactivateNotification), (8 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox0CompleteCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox0CompleteCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox0AbortCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox0AbortCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox1CompleteCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox1CompleteCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox1AbortCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox1AbortCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox2CompleteCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox2CompleteCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_TxMailbox2AbortCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_TxMailbox2AbortCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo0FullCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo0FullCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo0MsgPendingCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo0MsgPendingCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo1FullCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo1FullCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_RxFifo1MsgPendingCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_RxFifo1MsgPendingCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_SleepCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_SleepCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_WakeUpFromRxMsgCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_WakeUpFromRxMsgCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_ErrorCallback), (2 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ErrorCallback), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_GetState), (38 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetState), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_GetError), (4 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_GetError), (8 bytes). + Removing stm32f4xx_hal_can.o(.text.HAL_CAN_ResetError), (32 bytes). + Removing stm32f4xx_hal_can.o(.ARM.exidx.text.HAL_CAN_ResetError), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text), (0 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_DeInit), (4 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_MCOConfig), (158 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_EnableCSS), (12 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_DisableCSS), (12 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DisableCSS), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig), (152 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig), (62 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler), (28 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_rcc.o(.text.HAL_RCC_CSSCallback), (2 bytes). + Removing stm32f4xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig), (326 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig), (50 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq), (88 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLLI2S), (104 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLLI2S), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLLI2S), (52 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLLI2S), (8 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.text.HAL_RCC_DeInit), (290 bytes). + Removing stm32f4xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCC_DeInit), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text), (0 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program), (134 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_WaitForLastOperation), (106 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_Program_Byte), (32 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Byte), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_Program_HalfWord), (36 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_HalfWord), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_Program_Word), (36 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Word), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_Program_DoubleWord), (56 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_DoubleWord), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_Program_IT), (104 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_IRQHandler), (206 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.FLASH_SetErrorCode), (110 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.FLASH_SetErrorCode), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback), (2 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback), (2 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_Unlock), (46 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_Lock), (20 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock), (42 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Lock), (20 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_OB_Launch), (28 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch), (8 bytes). + Removing stm32f4xx_hal_flash.o(.text.HAL_FLASH_GetError), (12 bytes). + Removing stm32f4xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError), (8 bytes). + Removing stm32f4xx_hal_flash.o(.data.pFlash), (32 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase), (178 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_MassErase), (38 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_Erase_Sector), (70 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_FlushCaches), (88 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_FlushCaches), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT), (98 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram), (106 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP), (34 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP), (34 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_RDP_LevelConfig), (30 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_RDP_LevelConfig), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig), (48 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_BOR_LevelConfig), (24 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BOR_LevelConfig), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig), (34 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP), (12 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetRDP), (28 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetRDP), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetUser), (16 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser), (8 bytes). + Removing stm32f4xx_hal_flash_ex.o(.text.FLASH_OB_GetBOR), (16 bytes). + Removing stm32f4xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBOR), (8 bytes). + Removing stm32f4xx_hal_flash_ramfunc.o(.text), (0 bytes). + Removing stm32f4xx_hal_gpio.o(.text), (0 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.text.HAL_GPIO_DeInit), (262 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.text.HAL_GPIO_TogglePin), (16 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.text.HAL_GPIO_LockPin), (40 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Callback), (2 bytes). + Removing stm32f4xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback), (8 bytes). + Removing stm32f4xx_hal_dma_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart), (96 bytes). + Removing stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart), (8 bytes). + Removing stm32f4xx_hal_dma_ex.o(.text.DMA_MultiBufferSetConfig), (30 bytes). + Removing stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.DMA_MultiBufferSetConfig), (8 bytes). + Removing stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_MultiBufferStart_IT), (1456 bytes). + Removing stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_MultiBufferStart_IT), (8 bytes). + Removing stm32f4xx_hal_dma_ex.o(.text.HAL_DMAEx_ChangeMemory), (20 bytes). + Removing stm32f4xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ChangeMemory), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text), (0 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_CheckFifoParam), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_CalcBaseAndBitshift), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_DeInit), (90 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_Start), (66 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_PollForTransfer), (340 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer), (8 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_RegisterCallback), (84 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback), (104 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_GetState), (6 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState), (8 bytes). + Removing stm32f4xx_hal_dma.o(.text.HAL_DMA_GetError), (4 bytes). + Removing stm32f4xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text), (0 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DeInit), (26 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess), (30 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess), (30 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD), (128 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnablePVD), (12 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisablePVD), (12 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin), (16 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin), (18 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode), (36 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode), (70 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode), (36 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler), (30 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_PVDCallback), (2 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit), (18 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit), (18 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend), (18 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend), (8 bytes). + Removing stm32f4xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend), (18 bytes). + Removing stm32f4xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkUpReg), (54 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkUpReg), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkUpReg), (54 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkUpReg), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown), (12 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown), (12 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange), (16 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange), (8 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling), (102 bytes). + Removing stm32f4xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text), (0 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SystemReset), (4 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_SystemReset), (36 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.SysTick_Config), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_MPU_Disable), (26 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_MPU_Enable), (32 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_MPU_EnableRegion), (22 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_MPU_DisableRegion), (22 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion), (94 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_CORTEX_ClearEvent), (6 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_CORTEX_ClearEvent), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPriority), (24 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.NVIC_DecodePriority), (56 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriority), (34 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ), (32 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ), (36 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ), (32 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_NVIC_GetActive), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.__NVIC_GetActive), (36 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig), (24 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Callback), (2 bytes). + Removing stm32f4xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback), (8 bytes). + Removing stm32f4xx_hal.o(.text), (0 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_Init), (8 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_InitTick), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_MspInit), (2 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DeInit), (68 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DeInit), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_MspDeInit), (2 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_MspDeInit), (8 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_IncTick), (8 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTick), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetTickPrio), (12 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_SetTickFreq), (46 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetTickFreq), (12 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq), (8 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_Delay), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_SuspendTick), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_SuspendTick), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_ResumeTick), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_ResumeTick), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetHalVersion), (10 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetREVID), (14 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetREVID), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetDEVID), (16 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetDEVID), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGSleepMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGSleepMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGSleepMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGSleepMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode), (18 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_EnableCompensationCell), (14 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_EnableCompensationCell), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_DisableCompensationCell), (14 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_DisableCompensationCell), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetUIDw0), (12 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetUIDw1), (12 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1), (8 bytes). + Removing stm32f4xx_hal.o(.text.HAL_GetUIDw2), (12 bytes). + Removing stm32f4xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text), (0 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine), (180 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine), (156 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine), (136 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback), (12 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetHandle), (12 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_IRQHandler), (44 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_GetPending), (28 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_ClearPending), (24 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending), (8 bytes). + Removing stm32f4xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI), (24 bytes). + Removing stm32f4xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text), (0 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Init), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MspInit), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspInit), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_DeInit), (54 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DeInit), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit), (312 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnFlagUntilTimeout), (148 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestWrite), (176 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterRequestWrite), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnTXEFlagUntilTimeout), (106 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnTXEFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnBTFFlagUntilTimeout), (106 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnBTFFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive), (536 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterRequestRead), (254 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterRequestRead), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnRXNEFlagUntilTimeout), (118 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnRXNEFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit), (366 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive), (342 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPFlagUntilTimeout), (98 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_IT), (272 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_IT), (284 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_IT), (142 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_IT), (142 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Transmit_DMA), (352 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_DMAXferCplt), (298 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAXferCplt), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_DMAError), (74 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAError), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Receive_DMA), (348 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Transmit_DMA), (246 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Receive_DMA), (238 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write), (298 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryWrite), (192 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryWrite), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read), (544 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_RequestMemoryRead), (268 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_RequestMemoryRead), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_IT), (240 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_IT), (258 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Write_DMA), (426 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Write_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Mem_Read_DMA), (496 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Mem_Read_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_IsDeviceReady), (416 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_IsDeviceReady), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_IT), (274 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Transmit_DMA), (430 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_IT), (338 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Seq_Receive_DMA), (524 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Seq_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_IT), (172 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Transmit_DMA), (356 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_DMAAbort), (224 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_DMAAbort), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_IT), (172 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Slave_Seq_Receive_DMA), (354 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Slave_Seq_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_EnableListen_IT), (54 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EnableListen_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_DisableListen_IT), (64 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_DisableListen_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_Master_Abort_IT), (86 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_Master_Abort_IT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_ITError), (336 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_ITError), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_EV_IRQHandler), (412 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_EV_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_ConvertOtherXferOptions), (30 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_ConvertOtherXferOptions), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Master_SB), (136 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_SB), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Master_ADD10), (38 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ADD10), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Master_ADDR), (394 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Master_ADDR), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_TXE), (184 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterTransmit_TXE), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterTransmit_BTF), (136 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterTransmit_BTF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MemoryTransmit_TXE_BTF), (168 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MemoryTransmit_TXE_BTF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_RXNE), (226 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterReceive_RXNE), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_MasterReceive_BTF), (248 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_MasterReceive_BTF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Slave_ADDR), (84 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_ADDR), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Slave_STOPF), (354 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_STOPF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_TXE), (72 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveTransmit_TXE), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_SlaveTransmit_BTF), (28 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveTransmit_BTF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_RXNE), (76 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveReceive_RXNE), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_SlaveReceive_BTF), (30 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_SlaveReceive_BTF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_ER_IRQHandler), (164 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ER_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Slave_AF), (156 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Slave_AF), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MasterTxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MasterRxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_SlaveTxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_SlaveRxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_AddrCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AddrCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_ListenCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MemTxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_MemRxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_ErrorCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_ErrorCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_AbortCpltCallback), (2 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetState), (6 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetState), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetMode), (6 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetMode), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.HAL_I2C_GetError), (4 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.HAL_I2C_GetError), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_Flush_DR), (14 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_Flush_DR), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnSTOPRequestThroughIT), (78 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnSTOPRequestThroughIT), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_WaitOnMasterAddressFlagUntilTimeout), (150 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_WaitOnMasterAddressFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_i2c.o(.text.I2C_IsAcknowledgeFailed), (48 bytes). + Removing stm32f4xx_hal_i2c.o(.ARM.exidx.text.I2C_IsAcknowledgeFailed), (8 bytes). + Removing stm32f4xx_hal_i2c_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_spi.o(.text), (0 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Init), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_MspInit), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_MspInit), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_DeInit), (48 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DeInit), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_EndRxTxTransaction), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_EndRxTransaction), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_IT), (154 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_TxISR_16BIT), (32 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_TxISR_16BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_TxISR_8BIT), (34 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_TxISR_8BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_IT), (196 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_IT), (204 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive_IT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_RxISR_16BIT), (32 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_RxISR_16BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_RxISR_8BIT), (34 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_RxISR_8BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_16BIT), (48 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesRxISR_16BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_16BIT), (48 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesTxISR_16BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_2linesRxISR_8BIT), (52 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesRxISR_8BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_2linesTxISR_8BIT), (52 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_2linesTxISR_8BIT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfTransmitCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATransmitCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAError), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TransmitReceive_DMA), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfReceiveCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAReceiveCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAHalfTransmitReceiveCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATransmitReceiveCplt), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort), (310 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Abort), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_AbortTx_ISR), (26 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_AbortTx_ISR), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_AbortRx_ISR), (98 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_AbortRx_ISR), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_Abort_IT), (338 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_Abort_IT), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_DMATxAbortCallback), (142 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMATxAbortCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_DMARxAbortCallback), (120 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMARxAbortCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_AbortCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_AbortCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAPause), (32 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAPause), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAResume), (32 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAResume), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_DMAStop), (68 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_DMAStop), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_IRQHandler), (262 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_DMAAbortOnError), (16 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_DMAAbortOnError), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_ErrorCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_ErrorCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_TxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_RxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_RxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_TxRxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxRxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_TxHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_RxHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_RxHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_TxRxHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_TxRxHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_GetState), (6 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_GetState), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.HAL_SPI_GetError), (4 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.HAL_SPI_GetError), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_CloseRxTx_ISR), (168 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseRxTx_ISR), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_CloseRx_ISR), (90 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseRx_ISR), (8 bytes). + Removing stm32f4xx_hal_spi.o(.text.SPI_CloseTx_ISR), (150 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_CloseTx_ISR), (8 bytes). + Removing stm32f4xx_hal_spi.o(.ARM.exidx.text.SPI_WaitFlagStateUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text), (0 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_DeInit), (96 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start), (160 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop), (42 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT), (168 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT), (50 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA), (264 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt), (24 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt), (10 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMAError), (92 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA), (60 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Init), (90 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DeInit), (96 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start), (290 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop), (130 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT), (336 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT), (188 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA), (622 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseCplt), (104 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt), (56 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA), (230 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit), (96 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop), (130 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT), (336 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT), (188 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA), (622 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA), (230 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Init), (90 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_DeInit), (96 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start), (296 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop), (116 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT), (348 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT), (176 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA), (604 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMACaptureCplt), (116 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt), (56 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA), (206 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init), (92 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit), (80 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start), (116 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop), (120 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT), (132 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT), (136 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Init), (178 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit), (80 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start), (164 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop), (160 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT), (210 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT), (212 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA), (562 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA), (240 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IRQHandler), (308 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel), (78 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel), (152 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI1_SetConfig), (168 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI2_SetConfig), (60 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI3_SetConfig), (52 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI4_SetConfig), (60 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel), (220 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart), (28 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart), (456 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMATriggerCplt), (24 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt), (10 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop), (134 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart), (28 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart), (454 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop), (134 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_GenerateEvent), (36 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear), (204 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_ETR_SetConfig), (22 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource), (222 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage), (34 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_ITRx_SetConfig), (16 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage), (36 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input), (16 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro), (74 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig), (150 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT), (74 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue), (52 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_ErrorCallback), (2 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OC_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_IC_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel), (4 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_GetChannelState), (32 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState), (8 bytes). + Removing stm32f4xx_hal_tim.o(.text.HAL_TIM_DMABurstState), (6 bytes). + Removing stm32f4xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text), (0 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init), (194 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit), (2 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit), (80 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start), (214 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop), (66 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT), (222 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT), (74 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA), (298 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA), (74 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start), (234 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd), (36 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop), (110 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT), (290 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT), (184 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA), (516 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt), (82 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN), (66 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA), (190 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start), (234 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop), (110 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT), (290 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT), (184 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA), (516 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA), (190 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start), (102 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop), (106 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT), (118 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT), (122 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent), (104 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT), (104 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA), (144 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt), (16 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt), (16 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization), (184 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime), (76 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig), (26 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback), (2 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback), (2 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState), (6 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState), (8 bytes). + Removing stm32f4xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState), (32 bytes). + Removing stm32f4xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text), (0 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Init), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_MspInit), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspInit), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_SetConfig), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_Init), (104 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_Init), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_LIN_Init), (120 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_Init), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_Init), (128 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_Init), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_DeInit), (56 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DeInit), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_MspDeInit), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspDeInit), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit), (180 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout), (136 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_WaitOnFlagUntilTimeout), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_Receive), (194 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_DMA), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATransmitCplt), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxHalfCplt), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAError), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_DMA), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_DMAPause), (124 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAPause), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_DMAResume), (126 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAResume), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_DMAStop), (120 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAStop), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndTxTransfer), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndRxTransfer), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle), (296 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_IT), (92 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UARTEx_ReceiveToIdle_DMA), (92 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_DMA), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UARTEx_GetRxEventType), (4 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_GetRxEventType), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_Abort), (206 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit), (96 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive), (146 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_Abort_IT), (248 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.UART_DMATxAbortCallback), (46 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxAbortCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.UART_DMARxAbortCallback), (46 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxAbortCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT), (124 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback), (20 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMATxOnlyAbortCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT), (178 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback), (22 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxOnlyAbortCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_IRQHandler), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Receive_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAAbortOnError), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_ErrorCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_RxEventCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_Transmit_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_EndTransmit_IT), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_TxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_TxHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_RxCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback), (2 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_LIN_SendBreak), (60 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_SendBreak), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_EnterMuteMode), (62 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnterMuteMode), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_MultiProcessor_ExitMuteMode), (62 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_ExitMuteMode), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_EnableTransmitter), (44 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableTransmitter), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_HalfDuplex_EnableReceiver), (46 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableReceiver), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_GetState), (14 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetState), (8 bytes). + Removing stm32f4xx_hal_uart.o(.text.HAL_UART_GetError), (4 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetError), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMAReceiveCplt), (8 bytes). + Removing stm32f4xx_hal_uart.o(.ARM.exidx.text.UART_DMARxHalfCplt), (8 bytes). + Removing system_stm32f4xx.o(.text), (0 bytes). + Removing system_stm32f4xx.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32f4xx.o(.text.SystemCoreClockUpdate), (126 bytes). + Removing system_stm32f4xx.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing croutine.o(.text), (0 bytes). + Removing event_groups.o(.text), (0 bytes). + Removing event_groups.o(.text.xEventGroupCreateStatic), (78 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupCreateStatic), (8 bytes). + Removing event_groups.o(.text.xEventGroupCreate), (28 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupCreate), (8 bytes). + Removing event_groups.o(.text.xEventGroupSync), (220 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupSync), (8 bytes). + Removing event_groups.o(.text.xEventGroupSetBits), (158 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupSetBits), (8 bytes). + Removing event_groups.o(.text.xEventGroupWaitBits), (288 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupWaitBits), (8 bytes). + Removing event_groups.o(.text.prvTestWaitCondition), (24 bytes). + Removing event_groups.o(.ARM.exidx.text.prvTestWaitCondition), (8 bytes). + Removing event_groups.o(.text.xEventGroupClearBits), (72 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupClearBits), (8 bytes). + Removing event_groups.o(.text.xEventGroupClearBitsFromISR), (22 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupClearBitsFromISR), (8 bytes). + Removing event_groups.o(.text.vEventGroupClearBitsCallback), (8 bytes). + Removing event_groups.o(.ARM.exidx.text.vEventGroupClearBitsCallback), (8 bytes). + Removing event_groups.o(.text.xEventGroupGetBitsFromISR), (28 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupGetBitsFromISR), (8 bytes). + Removing event_groups.o(.text.vEventGroupDelete), (78 bytes). + Removing event_groups.o(.ARM.exidx.text.vEventGroupDelete), (8 bytes). + Removing event_groups.o(.text.vEventGroupSetBitsCallback), (8 bytes). + Removing event_groups.o(.ARM.exidx.text.vEventGroupSetBitsCallback), (8 bytes). + Removing event_groups.o(.text.xEventGroupSetBitsFromISR), (22 bytes). + Removing event_groups.o(.ARM.exidx.text.xEventGroupSetBitsFromISR), (8 bytes). + Removing event_groups.o(.text.uxEventGroupGetNumber), (10 bytes). + Removing event_groups.o(.ARM.exidx.text.uxEventGroupGetNumber), (8 bytes). + Removing event_groups.o(.text.vEventGroupSetNumber), (4 bytes). + Removing event_groups.o(.ARM.exidx.text.vEventGroupSetNumber), (8 bytes). + Removing list.o(.text), (0 bytes). + Removing list.o(.ARM.exidx.text.vListInitialise), (8 bytes). + Removing list.o(.ARM.exidx.text.vListInitialiseItem), (8 bytes). + Removing list.o(.ARM.exidx.text.vListInsertEnd), (8 bytes). + Removing list.o(.ARM.exidx.text.vListInsert), (8 bytes). + Removing list.o(.ARM.exidx.text.uxListRemove), (8 bytes). + Removing queue.o(.text), (0 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGenericReset), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGenericCreateStatic), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvInitialiseNewQueue), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGenericCreate), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueCreateMutex), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvInitialiseMutex), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueCreateMutexStatic), (8 bytes). + Removing queue.o(.text.xQueueGetMutexHolder), (26 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGetMutexHolder), (8 bytes). + Removing queue.o(.text.xQueueGetMutexHolderFromISR), (34 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGetMutexHolderFromISR), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGiveMutexRecursive), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGenericSend), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueTakeMutexRecursive), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueSemaphoreTake), (8 bytes). + Removing queue.o(.text.xQueueCreateCountingSemaphoreStatic), (78 bytes). + Removing queue.o(.ARM.exidx.text.xQueueCreateCountingSemaphoreStatic), (8 bytes). + Removing queue.o(.text.xQueueCreateCountingSemaphore), (66 bytes). + Removing queue.o(.ARM.exidx.text.xQueueCreateCountingSemaphore), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvCopyDataToQueue), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvIsQueueFull), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvUnlockQueue), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGenericSendFromISR), (8 bytes). + Removing queue.o(.text.xQueueGiveFromISR), (192 bytes). + Removing queue.o(.ARM.exidx.text.xQueueGiveFromISR), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueReceive), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvCopyDataFromQueue), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvIsQueueEmpty), (8 bytes). + Removing queue.o(.ARM.exidx.text.prvGetDisinheritPriorityAfterTimeout), (8 bytes). + Removing queue.o(.text.xQueuePeek), (376 bytes). + Removing queue.o(.ARM.exidx.text.xQueuePeek), (8 bytes). + Removing queue.o(.ARM.exidx.text.xQueueReceiveFromISR), (8 bytes). + Removing queue.o(.text.xQueuePeekFromISR), (132 bytes). + Removing queue.o(.ARM.exidx.text.xQueuePeekFromISR), (8 bytes). + Removing queue.o(.text.uxQueueMessagesWaiting), (38 bytes). + Removing queue.o(.ARM.exidx.text.uxQueueMessagesWaiting), (8 bytes). + Removing queue.o(.text.uxQueueSpacesAvailable), (42 bytes). + Removing queue.o(.ARM.exidx.text.uxQueueSpacesAvailable), (8 bytes). + Removing queue.o(.text.uxQueueMessagesWaitingFromISR), (26 bytes). + Removing queue.o(.ARM.exidx.text.uxQueueMessagesWaitingFromISR), (8 bytes). + Removing queue.o(.text.vQueueDelete), (46 bytes). + Removing queue.o(.ARM.exidx.text.vQueueDelete), (8 bytes). + Removing queue.o(.text.vQueueUnregisterQueue), (42 bytes). + Removing queue.o(.ARM.exidx.text.vQueueUnregisterQueue), (8 bytes). + Removing queue.o(.text.uxQueueGetQueueNumber), (4 bytes). + Removing queue.o(.ARM.exidx.text.uxQueueGetQueueNumber), (8 bytes). + Removing queue.o(.text.vQueueSetQueueNumber), (4 bytes). + Removing queue.o(.ARM.exidx.text.vQueueSetQueueNumber), (8 bytes). + Removing queue.o(.text.ucQueueGetQueueType), (6 bytes). + Removing queue.o(.ARM.exidx.text.ucQueueGetQueueType), (8 bytes). + Removing queue.o(.text.xQueueIsQueueEmptyFromISR), (30 bytes). + Removing queue.o(.ARM.exidx.text.xQueueIsQueueEmptyFromISR), (8 bytes). + Removing queue.o(.text.xQueueIsQueueFullFromISR), (34 bytes). + Removing queue.o(.ARM.exidx.text.xQueueIsQueueFullFromISR), (8 bytes). + Removing queue.o(.ARM.exidx.text.vQueueAddToRegistry), (8 bytes). + Removing queue.o(.text.pcQueueGetName), (40 bytes). + Removing queue.o(.ARM.exidx.text.pcQueueGetName), (8 bytes). + Removing queue.o(.ARM.exidx.text.vQueueWaitForMessageRestricted), (8 bytes). + Removing stream_buffer.o(.text), (0 bytes). + Removing stream_buffer.o(.text.xStreamBufferGenericCreate), (126 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferGenericCreate), (8 bytes). + Removing stream_buffer.o(.text.prvInitialiseNewStreamBuffer), (48 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvInitialiseNewStreamBuffer), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferGenericCreateStatic), (178 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferGenericCreateStatic), (8 bytes). + Removing stream_buffer.o(.text.vStreamBufferDelete), (42 bytes). + Removing stream_buffer.o(.ARM.exidx.text.vStreamBufferDelete), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferReset), (84 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferReset), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferSetTriggerLevel), (42 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferSetTriggerLevel), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferSpacesAvailable), (42 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferSpacesAvailable), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferBytesAvailable), (30 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferBytesAvailable), (8 bytes). + Removing stream_buffer.o(.text.prvBytesInBuffer), (18 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvBytesInBuffer), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferSend), (290 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferSend), (8 bytes). + Removing stream_buffer.o(.text.prvWriteMessageToBuffer), (70 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvWriteMessageToBuffer), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferSendFromISR), (162 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferSendFromISR), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferReceive), (226 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferReceive), (8 bytes). + Removing stream_buffer.o(.text.prvReadMessageFromBuffer), (68 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvReadMessageFromBuffer), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferNextMessageLengthBytes), (94 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferNextMessageLengthBytes), (8 bytes). + Removing stream_buffer.o(.text.prvReadBytesFromBuffer), (142 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvReadBytesFromBuffer), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferReceiveFromISR), (160 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferReceiveFromISR), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferIsEmpty), (34 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferIsEmpty), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferIsFull), (46 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferIsFull), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferSendCompletedFromISR), (86 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferSendCompletedFromISR), (8 bytes). + Removing stream_buffer.o(.text.xStreamBufferReceiveCompletedFromISR), (86 bytes). + Removing stream_buffer.o(.ARM.exidx.text.xStreamBufferReceiveCompletedFromISR), (8 bytes). + Removing stream_buffer.o(.text.uxStreamBufferGetStreamBufferNumber), (4 bytes). + Removing stream_buffer.o(.ARM.exidx.text.uxStreamBufferGetStreamBufferNumber), (8 bytes). + Removing stream_buffer.o(.text.vStreamBufferSetStreamBufferNumber), (4 bytes). + Removing stream_buffer.o(.ARM.exidx.text.vStreamBufferSetStreamBufferNumber), (8 bytes). + Removing stream_buffer.o(.text.ucStreamBufferGetStreamBufferType), (8 bytes). + Removing stream_buffer.o(.ARM.exidx.text.ucStreamBufferGetStreamBufferType), (8 bytes). + Removing stream_buffer.o(.text.prvWriteBytesToBuffer), (154 bytes). + Removing stream_buffer.o(.ARM.exidx.text.prvWriteBytesToBuffer), (8 bytes). + Removing tasks.o(.text), (0 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskCreateStatic), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvInitialiseNewTask), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvAddNewTaskToReadyList), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskCreate), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskDelete), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvDeleteTCB), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvResetNextTaskUnblockTime), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskDelayUntil), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskSuspendAll), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvAddCurrentTaskToDelayedList), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskResumeAll), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskDelay), (8 bytes). + Removing tasks.o(.ARM.exidx.text.eTaskGetState), (8 bytes). + Removing tasks.o(.text.uxTaskPriorityGet), (30 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskPriorityGet), (8 bytes). + Removing tasks.o(.text.uxTaskPriorityGetFromISR), (48 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskPriorityGetFromISR), (8 bytes). + Removing tasks.o(.text.vTaskPrioritySet), (214 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskPrioritySet), (8 bytes). + Removing tasks.o(.text.vTaskSuspend), (204 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskSuspend), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskSwitchContext), (8 bytes). + Removing tasks.o(.text.vTaskResume), (138 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskResume), (8 bytes). + Removing tasks.o(.text.prvTaskIsTaskSuspended), (50 bytes). + Removing tasks.o(.ARM.exidx.text.prvTaskIsTaskSuspended), (8 bytes). + Removing tasks.o(.text.xTaskResumeFromISR), (174 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskResumeFromISR), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskStartScheduler), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvIdleTask), (8 bytes). + Removing tasks.o(.text.vTaskEndScheduler), (36 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskEndScheduler), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskIncrementTick), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGetTickCount), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGetTickCountFromISR), (8 bytes). + Removing tasks.o(.text.uxTaskGetNumberOfTasks), (12 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskGetNumberOfTasks), (8 bytes). + Removing tasks.o(.text.pcTaskGetName), (38 bytes). + Removing tasks.o(.ARM.exidx.text.pcTaskGetName), (8 bytes). + Removing tasks.o(.text.uxTaskGetSystemState), (196 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskGetSystemState), (8 bytes). + Removing tasks.o(.text.prvListTasksWithinSingleList), (100 bytes). + Removing tasks.o(.ARM.exidx.text.prvListTasksWithinSingleList), (8 bytes). + Removing tasks.o(.text.xTaskCatchUpTicks), (60 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskCatchUpTicks), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskPlaceOnEventList), (8 bytes). + Removing tasks.o(.text.vTaskPlaceOnUnorderedEventList), (90 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskPlaceOnUnorderedEventList), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskPlaceOnEventListRestricted), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskRemoveFromEventList), (8 bytes). + Removing tasks.o(.text.vTaskRemoveFromUnorderedEventList), (150 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskRemoveFromUnorderedEventList), (8 bytes). + Removing tasks.o(.text.vTaskSetTimeOutState), (58 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskSetTimeOutState), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskInternalSetTimeOutState), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskCheckForTimeOut), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskMissedYield), (8 bytes). + Removing tasks.o(.text.uxTaskGetTaskNumber), (10 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskGetTaskNumber), (8 bytes). + Removing tasks.o(.text.vTaskSetTaskNumber), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskSetTaskNumber), (8 bytes). + Removing tasks.o(.text.vTaskGetInfo), (126 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskGetInfo), (8 bytes). + Removing tasks.o(.text.prvTaskCheckFreeStackSpace), (32 bytes). + Removing tasks.o(.ARM.exidx.text.prvTaskCheckFreeStackSpace), (8 bytes). + Removing tasks.o(.text.uxTaskGetStackHighWaterMark), (22 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskGetStackHighWaterMark), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGetCurrentTaskHandle), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGetSchedulerState), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskPriorityInherit), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskPriorityDisinherit), (8 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskPriorityDisinheritAfterTimeout), (8 bytes). + Removing tasks.o(.text.uxTaskResetEventItemValue), (26 bytes). + Removing tasks.o(.ARM.exidx.text.uxTaskResetEventItemValue), (8 bytes). + Removing tasks.o(.ARM.exidx.text.pvTaskIncrementMutexHeldCount), (8 bytes). + Removing tasks.o(.text.ulTaskNotifyTake), (106 bytes). + Removing tasks.o(.ARM.exidx.text.ulTaskNotifyTake), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskNotifyWait), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGenericNotify), (8 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskGenericNotifyFromISR), (8 bytes). + Removing tasks.o(.text.vTaskNotifyGiveFromISR), (218 bytes). + Removing tasks.o(.ARM.exidx.text.vTaskNotifyGiveFromISR), (8 bytes). + Removing tasks.o(.text.xTaskNotifyStateClear), (44 bytes). + Removing tasks.o(.ARM.exidx.text.xTaskNotifyStateClear), (8 bytes). + Removing tasks.o(.text.ulTaskNotifyValueClear), (42 bytes). + Removing tasks.o(.ARM.exidx.text.ulTaskNotifyValueClear), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvInitialiseTaskLists), (8 bytes). + Removing tasks.o(.ARM.exidx.text.prvCheckTasksWaitingTermination), (8 bytes). + Removing timers.o(.text), (0 bytes). + Removing timers.o(.ARM.exidx.text.xTimerCreateTimerTask), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvCheckForValidListAndQueue), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvTimerTask), (8 bytes). + Removing timers.o(.text.xTimerCreate), (56 bytes). + Removing timers.o(.ARM.exidx.text.xTimerCreate), (8 bytes). + Removing timers.o(.text.prvInitialiseNewTimer), (86 bytes). + Removing timers.o(.ARM.exidx.text.prvInitialiseNewTimer), (8 bytes). + Removing timers.o(.text.xTimerCreateStatic), (82 bytes). + Removing timers.o(.ARM.exidx.text.xTimerCreateStatic), (8 bytes). + Removing timers.o(.ARM.exidx.text.xTimerGenericCommand), (8 bytes). + Removing timers.o(.text.xTimerGetTimerDaemonTaskHandle), (34 bytes). + Removing timers.o(.ARM.exidx.text.xTimerGetTimerDaemonTaskHandle), (8 bytes). + Removing timers.o(.text.xTimerGetPeriod), (26 bytes). + Removing timers.o(.ARM.exidx.text.xTimerGetPeriod), (8 bytes). + Removing timers.o(.text.vTimerSetReloadMode), (58 bytes). + Removing timers.o(.ARM.exidx.text.vTimerSetReloadMode), (8 bytes). + Removing timers.o(.text.uxTimerGetReloadMode), (46 bytes). + Removing timers.o(.ARM.exidx.text.uxTimerGetReloadMode), (8 bytes). + Removing timers.o(.text.xTimerGetExpiryTime), (26 bytes). + Removing timers.o(.ARM.exidx.text.xTimerGetExpiryTime), (8 bytes). + Removing timers.o(.text.pcTimerGetName), (26 bytes). + Removing timers.o(.ARM.exidx.text.pcTimerGetName), (8 bytes). + Removing timers.o(.text.xTimerIsTimerActive), (46 bytes). + Removing timers.o(.ARM.exidx.text.xTimerIsTimerActive), (8 bytes). + Removing timers.o(.text.pvTimerGetTimerID), (38 bytes). + Removing timers.o(.ARM.exidx.text.pvTimerGetTimerID), (8 bytes). + Removing timers.o(.text.vTimerSetTimerID), (38 bytes). + Removing timers.o(.ARM.exidx.text.vTimerSetTimerID), (8 bytes). + Removing timers.o(.text.xTimerPendFunctionCallFromISR), (42 bytes). + Removing timers.o(.ARM.exidx.text.xTimerPendFunctionCallFromISR), (8 bytes). + Removing timers.o(.text.xTimerPendFunctionCall), (70 bytes). + Removing timers.o(.ARM.exidx.text.xTimerPendFunctionCall), (8 bytes). + Removing timers.o(.text.uxTimerGetTimerNumber), (4 bytes). + Removing timers.o(.ARM.exidx.text.uxTimerGetTimerNumber), (8 bytes). + Removing timers.o(.text.vTimerSetTimerNumber), (4 bytes). + Removing timers.o(.ARM.exidx.text.vTimerSetTimerNumber), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvGetNextExpireTime), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvProcessTimerOrBlockTask), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvProcessReceivedCommands), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvSampleTimeNow), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvProcessExpiredTimer), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvSwitchTimerLists), (8 bytes). + Removing timers.o(.ARM.exidx.text.prvInsertTimerInActiveList), (8 bytes). + Removing cmsis_os2.o(.text), (0 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelInitialize), (8 bytes). + Removing cmsis_os2.o(.text.osKernelGetInfo), (56 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetInfo), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetState), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelStart), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.SVC_Setup), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelLock), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelUnlock), (8 bytes). + Removing cmsis_os2.o(.text.osKernelRestoreLock), (76 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelRestoreLock), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetTickCount), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetTickFreq), (8 bytes). + Removing cmsis_os2.o(.text.osKernelGetSysTimerCount), (70 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetSysTimerCount), (8 bytes). + Removing cmsis_os2.o(.text.OS_Tick_GetCount), (16 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetCount), (8 bytes). + Removing cmsis_os2.o(.text.OS_Tick_GetOverflow), (16 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetOverflow), (8 bytes). + Removing cmsis_os2.o(.text.OS_Tick_GetInterval), (14 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.OS_Tick_GetInterval), (8 bytes). + Removing cmsis_os2.o(.text.osKernelGetSysTimerFreq), (12 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osKernelGetSysTimerFreq), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadNew), (8 bytes). + Removing cmsis_os2.o(.text.osThreadGetName), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetName), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetId), (8 bytes). + Removing cmsis_os2.o(.text.osThreadGetState), (56 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetState), (8 bytes). + Removing cmsis_os2.o(.text.osThreadGetStackSpace), (36 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetStackSpace), (8 bytes). + Removing cmsis_os2.o(.text.osThreadSetPriority), (48 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadSetPriority), (8 bytes). + Removing cmsis_os2.o(.text.osThreadGetPriority), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetPriority), (8 bytes). + Removing cmsis_os2.o(.text.osThreadYield), (40 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadYield), (8 bytes). + Removing cmsis_os2.o(.text.osThreadSuspend), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadSuspend), (8 bytes). + Removing cmsis_os2.o(.text.osThreadResume), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadResume), (8 bytes). + Removing cmsis_os2.o(.text.osThreadExit), (10 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadExit), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadTerminate), (8 bytes). + Removing cmsis_os2.o(.text.osThreadGetCount), (20 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadGetCount), (8 bytes). + Removing cmsis_os2.o(.text.osThreadEnumerate), (118 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadEnumerate), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadFlagsSet), (8 bytes). + Removing cmsis_os2.o(.text.osThreadFlagsClear), (82 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadFlagsClear), (8 bytes). + Removing cmsis_os2.o(.text.osThreadFlagsGet), (48 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadFlagsGet), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osThreadFlagsWait), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osDelay), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osDelayUntil), (8 bytes). + Removing cmsis_os2.o(.text.osTimerNew), (176 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerNew), (8 bytes). + Removing cmsis_os2.o(.text.TimerCallback), (20 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.TimerCallback), (8 bytes). + Removing cmsis_os2.o(.text.osTimerGetName), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerGetName), (8 bytes). + Removing cmsis_os2.o(.text.osTimerStart), (58 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerStart), (8 bytes). + Removing cmsis_os2.o(.text.osTimerStop), (78 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerStop), (8 bytes). + Removing cmsis_os2.o(.text.osTimerIsRunning), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerIsRunning), (8 bytes). + Removing cmsis_os2.o(.text.osTimerDelete), (82 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osTimerDelete), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsNew), (74 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsNew), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsSet), (94 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsSet), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsClear), (68 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsClear), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsGet), (28 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsGet), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsWait), (94 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsWait), (8 bytes). + Removing cmsis_os2.o(.text.osEventFlagsDelete), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osEventFlagsDelete), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMutexNew), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMutexAcquire), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMutexRelease), (8 bytes). + Removing cmsis_os2.o(.text.osMutexGetOwner), (34 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMutexGetOwner), (8 bytes). + Removing cmsis_os2.o(.text.osMutexDelete), (44 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMutexDelete), (8 bytes). + Removing cmsis_os2.o(.text.osSemaphoreNew), (196 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osSemaphoreNew), (8 bytes). + Removing cmsis_os2.o(.text.osSemaphoreAcquire), (106 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osSemaphoreAcquire), (8 bytes). + Removing cmsis_os2.o(.text.osSemaphoreRelease), (96 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osSemaphoreRelease), (8 bytes). + Removing cmsis_os2.o(.text.osSemaphoreGetCount), (26 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osSemaphoreGetCount), (8 bytes). + Removing cmsis_os2.o(.text.osSemaphoreDelete), (42 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osSemaphoreDelete), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueNew), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueuePut), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueGet), (8 bytes). + Removing cmsis_os2.o(.text.osMessageQueueGetCapacity), (10 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetCapacity), (8 bytes). + Removing cmsis_os2.o(.text.osMessageQueueGetMsgSize), (10 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetMsgSize), (8 bytes). + Removing cmsis_os2.o(.text.osMessageQueueGetCount), (26 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetCount), (8 bytes). + Removing cmsis_os2.o(.text.osMessageQueueGetSpace), (52 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueGetSpace), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueReset), (8 bytes). + Removing cmsis_os2.o(.text.osMessageQueueDelete), (42 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMessageQueueDelete), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolNew), (284 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolNew), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolGetName), (24 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetName), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolAlloc), (156 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolAlloc), (8 bytes). + Removing cmsis_os2.o(.text.AllocBlock), (16 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.AllocBlock), (8 bytes). + Removing cmsis_os2.o(.text.CreateBlock), (28 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.CreateBlock), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolFree), (216 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolFree), (8 bytes). + Removing cmsis_os2.o(.text.FreeBlock), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.FreeBlock), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolGetCapacity), (24 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetCapacity), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolGetBlockSize), (24 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetBlockSize), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolGetCount), (48 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetCount), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolGetSpace), (42 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolGetSpace), (8 bytes). + Removing cmsis_os2.o(.text.osMemoryPoolDelete), (94 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.osMemoryPoolDelete), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.vApplicationGetIdleTaskMemory), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.vApplicationGetTimerTaskMemory), (8 bytes). + Removing cmsis_os2.o(.ARM.exidx.text.__NVIC_SetPriority), (8 bytes). + Removing cmsis_os2.o(.rodata.str1.4), (17 bytes). + Removing heap_4.o(.text), (0 bytes). + Removing heap_4.o(.ARM.exidx.text.pvPortMalloc), (8 bytes). + Removing heap_4.o(.ARM.exidx.text.prvHeapInit), (8 bytes). + Removing heap_4.o(.ARM.exidx.text.prvInsertBlockIntoFreeList), (8 bytes). + Removing heap_4.o(.ARM.exidx.text.vPortFree), (8 bytes). + Removing heap_4.o(.text.xPortGetFreeHeapSize), (12 bytes). + Removing heap_4.o(.ARM.exidx.text.xPortGetFreeHeapSize), (8 bytes). + Removing heap_4.o(.text.xPortGetMinimumEverFreeHeapSize), (12 bytes). + Removing heap_4.o(.ARM.exidx.text.xPortGetMinimumEverFreeHeapSize), (8 bytes). + Removing heap_4.o(.text.vPortInitialiseBlocks), (2 bytes). + Removing heap_4.o(.ARM.exidx.text.vPortInitialiseBlocks), (8 bytes). + Removing heap_4.o(.text.vPortGetHeapStats), (142 bytes). + Removing heap_4.o(.ARM.exidx.text.vPortGetHeapStats), (8 bytes). + Removing port.o(.text), (0 bytes). + Removing port.o(.ARM.exidx.text.pxPortInitialiseStack), (8 bytes). + Removing port.o(.ARM.exidx.text.prvTaskExitError), (8 bytes). + Removing port.o(.ARM.exidx.text.SVC_Handler), (8 bytes). + Removing port.o(.ARM.exidx.text.xPortStartScheduler), (8 bytes). + Removing port.o(.ARM.exidx.text.vPortSetupTimerInterrupt), (8 bytes). + Removing port.o(.ARM.exidx.text.vPortEnableVFP), (8 bytes). + Removing port.o(.ARM.exidx.text.prvPortStartFirstTask), (8 bytes). + Removing port.o(.text.vPortEndScheduler), (38 bytes). + Removing port.o(.ARM.exidx.text.vPortEndScheduler), (8 bytes). + Removing port.o(.ARM.exidx.text.vPortEnterCritical), (8 bytes). + Removing port.o(.ARM.exidx.text.vPortExitCritical), (8 bytes). + Removing port.o(.ARM.exidx.text.PendSV_Handler), (8 bytes). + Removing port.o(.ARM.exidx.text.xPortSysTickHandler), (8 bytes). + Removing port.o(.ARM.exidx.text.vPortValidateInterruptPriority), (8 bytes). + Removing can_1.o(.text), (0 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox0CompleteCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.CAN_Get), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox1CompleteCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox2CompleteCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox0AbortCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox1AbortCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_TxMailbox2AbortCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo0MsgPendingCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo0FullCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo1MsgPendingCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_RxFifo1FullCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_SleepCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_WakeUpFromRxMsgCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.HAL_CAN_ErrorCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_Init), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TxQueueInit), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_DefaultIdParser), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_RegisterCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_RxFifo0Callback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TxCompleteCallback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_RxFifo1Callback), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_GetHandle), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_Transmit), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TxQueuePush), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TransmitStdDataFrame), (8 bytes). + Removing can_1.o(.text.BSP_CAN_TransmitExtDataFrame), (40 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TransmitExtDataFrame), (8 bytes). + Removing can_1.o(.text.BSP_CAN_TransmitRemoteFrame), (50 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TransmitRemoteFrame), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_RegisterId), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_CreateIdQueue), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_GetMessage), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_FindQueue), (8 bytes). + Removing can_1.o(.text.BSP_CAN_GetQueueCount), (74 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_GetQueueCount), (8 bytes). + Removing can_1.o(.text.BSP_CAN_FlushQueue), (100 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_FlushQueue), (8 bytes). + Removing can_1.o(.text.BSP_CAN_RegisterIdParser), (44 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_RegisterIdParser), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_ParseId), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_GetFrameType), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TxQueueIsEmpty), (8 bytes). + Removing can_1.o(.ARM.exidx.text.BSP_CAN_TxQueuePop), (8 bytes). + Removing gpio_1.o(.text), (0 bytes). + Removing gpio_1.o(.ARM.exidx.text.HAL_GPIO_EXTI_Callback), (8 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_RegisterCallback), (8 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_EnableIRQ), (8 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_DisableIRQ), (8 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_WritePin), (8 bytes). + Removing gpio_1.o(.text.BSP_GPIO_TogglePin), (46 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_TogglePin), (8 bytes). + Removing gpio_1.o(.ARM.exidx.text.BSP_GPIO_ReadPin), (8 bytes). + Removing i2c_1.o(.text), (0 bytes). + Removing i2c_1.o(.text.HAL_I2C_MasterTxCpltCallback), (36 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_MasterTxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.I2C_Get), (20 bytes). + Removing i2c_1.o(.ARM.exidx.text.I2C_Get), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_MasterRxCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_MasterRxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_SlaveTxCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_SlaveTxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_SlaveRxCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_SlaveRxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_ListenCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_ListenCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_MemTxCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_MemTxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_MemRxCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_MemRxCpltCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_ErrorCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_ErrorCallback), (8 bytes). + Removing i2c_1.o(.text.HAL_I2C_AbortCpltCallback), (38 bytes). + Removing i2c_1.o(.ARM.exidx.text.HAL_I2C_AbortCpltCallback), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_GetHandle), (18 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_GetHandle), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_RegisterCallback), (34 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_RegisterCallback), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_Transmit), (66 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_Transmit), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_Receive), (66 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_Receive), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_MemReadByte), (60 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_MemReadByte), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_MemWriteByte), (62 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_MemWriteByte), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_MemRead), (86 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_MemRead), (8 bytes). + Removing i2c_1.o(.text.BSP_I2C_MemWrite), (86 bytes). + Removing i2c_1.o(.ARM.exidx.text.BSP_I2C_MemWrite), (8 bytes). + Removing i2c_1.o(.bss.I2C_Callback), (36 bytes). + Removing mm.o(.text), (0 bytes). + Removing mm.o(.ARM.exidx.text.BSP_Malloc), (8 bytes). + Removing mm.o(.ARM.exidx.text.BSP_Free), (8 bytes). + Removing spi_1.o(.text), (0 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_TxCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.SPI_Get), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_RxCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_TxRxCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_TxHalfCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_RxHalfCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_TxRxHalfCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_ErrorCallback), (8 bytes). + Removing spi_1.o(.text.HAL_SPI_AbortCpltCallback), (34 bytes). + Removing spi_1.o(.ARM.exidx.text.HAL_SPI_AbortCpltCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_GetHandle), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_RegisterCallback), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_Transmit), (8 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_Receive), (8 bytes). + Removing spi_1.o(.text.BSP_SPI_TransmitReceive), (78 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_TransmitReceive), (8 bytes). + Removing spi_1.o(.text.BSP_SPI_MemReadByte), (54 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_MemReadByte), (8 bytes). + Removing spi_1.o(.text.BSP_SPI_MemWriteByte), (48 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_MemWriteByte), (8 bytes). + Removing spi_1.o(.text.BSP_SPI_MemRead), (68 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_MemRead), (8 bytes). + Removing spi_1.o(.text.BSP_SPI_MemWrite), (68 bytes). + Removing spi_1.o(.ARM.exidx.text.BSP_SPI_MemWrite), (8 bytes). + Removing uart.o(.text), (0 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.UART_Get), (8 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback), (8 bytes). + Removing uart.o(.text.HAL_UART_AbortCpltCallback), (38 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback), (8 bytes). + Removing uart.o(.text.HAL_UART_AbortTransmitCpltCallback), (38 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback), (8 bytes). + Removing uart.o(.text.HAL_UART_AbortReceiveCpltCallback), (38 bytes). + Removing uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.BSP_UART_IRQHandler), (8 bytes). + Removing uart.o(.ARM.exidx.text.BSP_UART_GetHandle), (8 bytes). + Removing uart.o(.ARM.exidx.text.BSP_UART_RegisterCallback), (8 bytes). + Removing uart.o(.ARM.exidx.text.BSP_UART_Transmit), (8 bytes). + Removing uart.o(.ARM.exidx.text.BSP_UART_Receive), (8 bytes). + Removing time.o(.text), (0 bytes). + Removing time.o(.text.BSP_TIME_Get_ms), (8 bytes). + Removing time.o(.ARM.exidx.text.BSP_TIME_Get_ms), (8 bytes). + Removing time.o(.ARM.exidx.text.BSP_TIME_Get_us), (8 bytes). + Removing time.o(.ARM.exidx.text.BSP_TIME_Delay_ms), (8 bytes). + Removing time.o(.text.BSP_TIME_Delay_us), (32 bytes). + Removing time.o(.ARM.exidx.text.BSP_TIME_Delay_us), (8 bytes). + Removing pwm.o(.text), (0 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_Start), (8 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_SetComp), (8 bytes). + Removing pwm.o(.text.BSP_PWM_SetFreq), (92 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_SetFreq), (8 bytes). + Removing pwm.o(.text.BSP_PWM_Stop), (30 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_Stop), (8 bytes). + Removing pwm.o(.text.BSP_PWM_GetAutoReloadPreload), (22 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_GetAutoReloadPreload), (8 bytes). + Removing pwm.o(.text.BSP_PWM_GetHandle), (10 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_GetHandle), (8 bytes). + Removing pwm.o(.text.BSP_PWM_GetChannel), (10 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_GetChannel), (8 bytes). + Removing pwm.o(.text.BSP_PWM_Start_DMA), (34 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_Start_DMA), (8 bytes). + Removing pwm.o(.text.BSP_PWM_Stop_DMA), (30 bytes). + Removing pwm.o(.ARM.exidx.text.BSP_PWM_Stop_DMA), (8 bytes). + Removing ahrs.o(.text), (0 bytes). + Removing ahrs.o(.ARM.exidx.text.AHRS_Init), (8 bytes). + Removing ahrs.o(.ARM.exidx.text.AHRS_Update), (8 bytes). + Removing ahrs.o(.ARM.exidx.text.AHRS_UpdateIMU), (8 bytes). + Removing ahrs.o(.ARM.exidx.text.AHRS_GetEulr), (8 bytes). + Removing ahrs.o(.ARM.exidx.text.copysignf), (8 bytes). + Removing ahrs.o(.ARM.exidx.text.AHRS_ResetEulr), (8 bytes). + Removing capacity.o(.text), (0 bytes). + Removing capacity.o(.text.Capacity_GetBatteryRemain), (224 bytes). + Removing capacity.o(.ARM.exidx.text.Capacity_GetBatteryRemain), (8 bytes). + Removing capacity.o(.text.Capacity_GetCapacitorRemain), (52 bytes). + Removing capacity.o(.ARM.exidx.text.Capacity_GetCapacitorRemain), (8 bytes). + Removing crc8.o(.text), (0 bytes). + Removing crc8.o(.text.CRC8_Calc), (32 bytes). + Removing crc8.o(.ARM.exidx.text.CRC8_Calc), (8 bytes). + Removing crc8.o(.text.CRC8_Verify), (34 bytes). + Removing crc8.o(.ARM.exidx.text.CRC8_Verify), (8 bytes). + Removing crc8.o(.rodata.crc8_tab), (256 bytes). + Removing crc16.o(.text), (0 bytes). + Removing crc16.o(.ARM.exidx.text.CRC16_Calc), (8 bytes). + Removing crc16.o(.ARM.exidx.text.CRC16_Byte), (8 bytes). + Removing crc16.o(.ARM.exidx.text.CRC16_Verify), (8 bytes). + Removing error_detect.o(.text), (0 bytes). + Removing error_detect.o(.text.ErrorDetect_Init), (52 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_Init), (8 bytes). + Removing error_detect.o(.text.ErrorDetect_Processing), (66 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_Processing), (8 bytes). + Removing error_detect.o(.text.ErrorDetect_ErrorExist), (90 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_ErrorExist), (8 bytes). + Removing error_detect.o(.text.ErrorDetect_GetErrorUnit), (42 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_GetErrorUnit), (8 bytes). + Removing error_detect.o(.text.ErrorDetect_GetDetail), (18 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_GetDetail), (8 bytes). + Removing error_detect.o(.text.ErrorDetect_Update), (20 bytes). + Removing error_detect.o(.ARM.exidx.text.ErrorDetect_Update), (8 bytes). + Removing error_detect.o(.bss.ged), (560 bytes). + Removing filter.o(.text), (0 bytes). + Removing filter.o(.ARM.exidx.text.LowPassFilter2p_Init), (8 bytes). + Removing filter.o(.ARM.exidx.text.LowPassFilter2p_Apply), (8 bytes). + Removing filter.o(.ARM.exidx.text.__ARM_isinff), (8 bytes). + Removing filter.o(.ARM.exidx.text.LowPassFilter2p_Reset), (8 bytes). + Removing filter.o(.ARM.exidx.text.__ARM_isfinitef), (8 bytes). + Removing filter.o(.text.NotchFilter_Init), (176 bytes). + Removing filter.o(.ARM.exidx.text.NotchFilter_Init), (8 bytes). + Removing filter.o(.text.NotchFilter_Apply), (88 bytes). + Removing filter.o(.ARM.exidx.text.NotchFilter_Apply), (8 bytes). + Removing filter.o(.text.NotchFilter_Reset), (84 bytes). + Removing filter.o(.ARM.exidx.text.NotchFilter_Reset), (8 bytes). + Removing freertos_cli.o(.text), (0 bytes). + Removing freertos_cli.o(.text.FreeRTOS_CLIRegisterCommand), (86 bytes). + Removing freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIRegisterCommand), (8 bytes). + Removing freertos_cli.o(.text.FreeRTOS_CLIProcessCommand), (194 bytes). + Removing freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIProcessCommand), (8 bytes). + Removing freertos_cli.o(.text.prvGetNumberOfParameters), (42 bytes). + Removing freertos_cli.o(.ARM.exidx.text.prvGetNumberOfParameters), (8 bytes). + Removing freertos_cli.o(.text.FreeRTOS_CLIGetOutputBuffer), (10 bytes). + Removing freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIGetOutputBuffer), (8 bytes). + Removing freertos_cli.o(.text.FreeRTOS_CLIGetParameter), (82 bytes). + Removing freertos_cli.o(.ARM.exidx.text.FreeRTOS_CLIGetParameter), (8 bytes). + Removing freertos_cli.o(.text.prvHelpCommand), (48 bytes). + Removing freertos_cli.o(.ARM.exidx.text.prvHelpCommand), (8 bytes). + Removing freertos_cli.o(.data.FreeRTOS_CLIRegisterCommand.pxLastCommandInList), (4 bytes). + Removing freertos_cli.o(.data.xRegisteredCommands), (8 bytes). + Removing freertos_cli.o(.bss.FreeRTOS_CLIProcessCommand.pxCommand), (4 bytes). + Removing freertos_cli.o(.rodata.str1.1), (221 bytes). + Removing freertos_cli.o(.bss.cOutputBuffer), (512 bytes). + Removing freertos_cli.o(.rodata.xHelpCommand), (16 bytes). + Removing freertos_cli.o(.bss.prvHelpCommand.pxCommand), (4 bytes). + Removing limiter.o(.text), (0 bytes). + Removing limiter.o(.text.PowerLimit_ChassicOutput), (136 bytes). + Removing limiter.o(.ARM.exidx.text.PowerLimit_ChassicOutput), (8 bytes). + Removing limiter.o(.text.PowerLimit_CapInput), (52 bytes). + Removing limiter.o(.ARM.exidx.text.PowerLimit_CapInput), (8 bytes). + Removing limiter.o(.text.PowerLimit_TargetPower), (44 bytes). + Removing limiter.o(.ARM.exidx.text.PowerLimit_TargetPower), (8 bytes). + Removing limiter.o(.text.HeatLimit_ShootFreq), (48 bytes). + Removing limiter.o(.ARM.exidx.text.HeatLimit_ShootFreq), (8 bytes). + Removing mixer.o(.text), (0 bytes). + Removing mixer.o(.text.Mixer_Init), (14 bytes). + Removing mixer.o(.ARM.exidx.text.Mixer_Init), (8 bytes). + Removing mixer.o(.text.Mixer_Apply), (356 bytes). + Removing mixer.o(.ARM.exidx.text.Mixer_Apply), (8 bytes). + Removing pid.o(.text), (0 bytes). + Removing pid.o(.ARM.exidx.text.PID_Init), (8 bytes). + Removing pid.o(.ARM.exidx.text.__ARM_isfinitef), (8 bytes). + Removing pid.o(.ARM.exidx.text.PID_Reset), (8 bytes). + Removing pid.o(.ARM.exidx.text.PID_Calc), (8 bytes). + Removing pid.o(.ARM.exidx.text.PID_ResetIntegral), (8 bytes). + Removing ui.o(.text), (0 bytes). + Removing ui.o(.text.UI_DrawLine), (144 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawLine), (8 bytes). + Removing ui.o(.text.UI_DrawRectangle), (146 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawRectangle), (8 bytes). + Removing ui.o(.text.UI_DrawCycle), (132 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawCycle), (8 bytes). + Removing ui.o(.text.UI_DrawOval), (146 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawOval), (8 bytes). + Removing ui.o(.text.UI_DrawArc), (154 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawArc), (8 bytes). + Removing ui.o(.text.UI_DrawFloating), (150 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawFloating), (8 bytes). + Removing ui.o(.text.UI_DrawInteger), (156 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawInteger), (8 bytes). + Removing ui.o(.text.UI_DrawCharacter), (144 bytes). + Removing ui.o(.ARM.exidx.text.UI_DrawCharacter), (8 bytes). + Removing ui.o(.text.UI_DelLayer), (16 bytes). + Removing ui.o(.ARM.exidx.text.UI_DelLayer), (8 bytes). + Removing ui.o(.rodata.str1.1), (3 bytes). + Removing user_math.o(.text), (0 bytes). + Removing user_math.o(.ARM.exidx.text.InvSqrt), (8 bytes). + Removing user_math.o(.ARM.exidx.text.AbsClip), (8 bytes). + Removing user_math.o(.text.fAbs), (6 bytes). + Removing user_math.o(.ARM.exidx.text.fAbs), (8 bytes). + Removing user_math.o(.ARM.exidx.text.Clip), (8 bytes). + Removing user_math.o(.text.Sign), (32 bytes). + Removing user_math.o(.ARM.exidx.text.Sign), (8 bytes). + Removing user_math.o(.text.ResetMoveVector), (10 bytes). + Removing user_math.o(.ARM.exidx.text.ResetMoveVector), (8 bytes). + Removing user_math.o(.ARM.exidx.text.CircleError), (8 bytes). + Removing user_math.o(.ARM.exidx.text.CircleAdd), (8 bytes). + Removing user_math.o(.text.CircleReverse), (24 bytes). + Removing user_math.o(.ARM.exidx.text.CircleReverse), (8 bytes). + Removing user_math.o(.text.CalculateRpm), (176 bytes). + Removing user_math.o(.ARM.exidx.text.CalculateRpm), (8 bytes). + Removing user_math.o(.ARM.exidx.text.ScaleSumTo1), (8 bytes). + Removing cmd.o(.text), (0 bytes). + Removing cmd.o(.text.CMD_Init), (20 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_Init), (8 bytes). + Removing cmd.o(.text.CMD_CheckHostOverwrite), (4 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_CheckHostOverwrite), (8 bytes). + Removing cmd.o(.text.CMD_ParseRc), (158 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_ParseRc), (8 bytes). + Removing cmd.o(.text.CMD_KeyPressedRc), (10 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_KeyPressedRc), (8 bytes). + Removing cmd.o(.text.CMD_RcLostLogic), (14 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_RcLostLogic), (8 bytes). + Removing cmd.o(.text.CMD_PcLogic), (538 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_PcLogic), (8 bytes). + Removing cmd.o(.text.CMD_RcLogic), (152 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_RcLogic), (8 bytes). + Removing cmd.o(.text.CMD_ParseHost), (58 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_ParseHost), (8 bytes). + Removing cmd.o(.text.CMD_RefereeAdd), (28 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_RefereeAdd), (8 bytes). + Removing cmd.o(.text.CMD_BehaviorOccurredRc), (104 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_BehaviorOccurredRc), (8 bytes). + Removing cmd.o(.text.CMD_BehaviorToKey), (10 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_BehaviorToKey), (8 bytes). + Removing cmd.o(.text.CMD_BehaviorToActive), (10 bytes). + Removing cmd.o(.ARM.exidx.text.CMD_BehaviorToActive), (8 bytes). + Removing bmi088.o(.text), (0 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_Init), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI_WriteSingle), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI_ReadSingle), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_RxCpltCallback), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_AcclIntCallback), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_GyroIntCallback), (8 bytes). + Removing bmi088.o(.text.BMI088_GyroStable), (68 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_GyroStable), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_WaitNew), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_AcclStartDmaRecv), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI_Read), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_AcclWaitDmaCplt), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_GyroStartDmaRecv), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_GyroWaitDmaCplt), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_ParseAccl), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_ParseGyro), (8 bytes). + Removing bmi088.o(.ARM.exidx.text.BMI088_GetUpdateFreq), (8 bytes). + Removing ist8310.o(.text), (0 bytes). + Removing ist8310.o(.text.IST8310_Init), (192 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_Init), (8 bytes). + Removing ist8310.o(.text.IST8310_ReadSingle), (14 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_ReadSingle), (8 bytes). + Removing ist8310.o(.text.IST8310_MemRxCpltCallback), (20 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_MemRxCpltCallback), (8 bytes). + Removing ist8310.o(.text.IST8310_IntCallback), (20 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_IntCallback), (8 bytes). + Removing ist8310.o(.text.IST8310_WriteSingle), (16 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_WriteSingle), (8 bytes). + Removing ist8310.o(.text.IST8310_WaitNew), (22 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_WaitNew), (8 bytes). + Removing ist8310.o(.text.IST8310_StartDmaRecv), (10 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_StartDmaRecv), (8 bytes). + Removing ist8310.o(.text.IST8310_Read), (38 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_Read), (8 bytes). + Removing ist8310.o(.text.IST8310_WaitDmaCplt), (16 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_WaitDmaCplt), (8 bytes). + Removing ist8310.o(.text.IST8310_Parse), (140 bytes). + Removing ist8310.o(.ARM.exidx.text.IST8310_Parse), (8 bytes). + Removing ist8310.o(.bss.inited), (1 bytes). + Removing ist8310.o(.bss.thread_alert), (4 bytes). + Removing ist8310.o(.bss.ist8310_rxbuf), (6 bytes). + Removing motor.o(.text), (0 bytes). + Removing motor.o(.text.MOTOR_GetRotorAbsAngle), (14 bytes). + Removing motor.o(.ARM.exidx.text.MOTOR_GetRotorAbsAngle), (8 bytes). + Removing motor.o(.text.MOTOR_GetRotorSpeed), (14 bytes). + Removing motor.o(.ARM.exidx.text.MOTOR_GetRotorSpeed), (8 bytes). + Removing motor.o(.text.MOTOR_GetTorqueCurrent), (14 bytes). + Removing motor.o(.ARM.exidx.text.MOTOR_GetTorqueCurrent), (8 bytes). + Removing motor.o(.text.MOTOR_GetTemp), (14 bytes). + Removing motor.o(.ARM.exidx.text.MOTOR_GetTemp), (8 bytes). + Removing motor_rm.o(.text), (0 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_Register), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_CreateCANManager), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetCANManager), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_Update), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.Motor_RM_Decode), (8 bytes). + Removing motor_rm.o(.text.MOTOR_RM_UpdateAll), (90 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_UpdateAll), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_SetOutput), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetMotor), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetLogicalIndex), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetLSB), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_Ctrl), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_Relax), (8 bytes). + Removing motor_rm.o(.text.MOTOR_RM_Offine), (20 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_Offine), (8 bytes). + Removing motor_rm.o(.ARM.exidx.text.MOTOR_RM_GetRatio), (8 bytes). + Removing motor_dm.o(.text), (0 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_Register), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_CreateCANManager), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_GetCANManager), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_Update), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_ParseFeedbackFrame), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_UpdateAll), (90 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_UpdateAll), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_MITCtrl), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_GetMotor), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendMITCmd), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_PosVelCtrl), (50 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_PosVelCtrl), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_SendPosVelCmd), (92 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendPosVelCmd), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_VelCtrl), (42 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_VelCtrl), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_SendVelCmd), (74 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_SendVelCmd), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_Enable), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_Relax), (40 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_Relax), (8 bytes). + Removing motor_dm.o(.text.MOTOR_DM_Offine), (28 bytes). + Removing motor_dm.o(.ARM.exidx.text.MOTOR_DM_Offine), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.uint_to_float), (8 bytes). + Removing motor_dm.o(.ARM.exidx.text.float_to_uint), (8 bytes). + Removing ai.o(.text), (0 bytes). + Removing ai.o(.text.AI_Init), (30 bytes). + Removing ai.o(.ARM.exidx.text.AI_Init), (8 bytes). + Removing ai.o(.ARM.exidx.text.AI_StartReceiving), (8 bytes). + Removing ai.o(.ARM.exidx.text.AI_Get_NUC), (8 bytes). + Removing ai.o(.ARM.exidx.text.AI_ParseHost), (8 bytes). + Removing ai.o(.ARM.exidx.text.AI_StartSend), (8 bytes). + Removing dr16.o(.text), (0 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_Init), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_RxCpltCallback), (8 bytes). + Removing dr16.o(.text.DR16_Restart), (38 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_Restart), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_StartDmaRecv), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_WaitDmaCplt), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_ParseData), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_DataCorrupted), (8 bytes). + Removing dr16.o(.ARM.exidx.text.DR16_Offline), (8 bytes). + Removing init.o(.text), (0 bytes). + Removing init.o(.ARM.exidx.text.Task_Init), (8 bytes). + Removing ai_1.o(.text), (0 bytes). + Removing ai_1.o(.ARM.exidx.text.Task_ai), (8 bytes). + Removing atti_esti.o(.text), (0 bytes). + Removing atti_esti.o(.ARM.exidx.text.Task_atti_esti), (8 bytes). + Removing chassis_ctrl.o(.text), (0 bytes). + Removing chassis_ctrl.o(.ARM.exidx.text.Task_chassis_ctrl), (8 bytes). + Removing dr16_1.o(.text), (0 bytes). + Removing dr16_1.o(.ARM.exidx.text.Task_dr16), (8 bytes). + Removing gimbal_ctrl.o(.text), (0 bytes). + Removing gimbal_ctrl.o(.ARM.exidx.text.Task_gimbal_ctrl), (8 bytes). + Removing gimbal_ctrl.o(.bss.gimbal_cmd_ai), (20 bytes). + Removing gimbal_ctrl.o(.bss.send_nuc), (40 bytes). + Removing shoot_ctrl.o(.text), (0 bytes). + Removing shoot_ctrl.o(.ARM.exidx.text.Task_shoot_ctrl), (8 bytes). + Removing user_task.o(.text), (0 bytes). + Removing remote.o(.text), (0 bytes). + Removing remote.o(.ARM.exidx.text.Task_remote), (8 bytes). + Removing config.o(.text), (0 bytes). + Removing config.o(.ARM.exidx.text.Config_GetRobotParam), (8 bytes). + Removing chassis.o(.text), (0 bytes). + Removing chassis.o(.text.Chassis_Init), (324 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_Init), (8 bytes). + Removing chassis.o(.text.Chassis_UpdateFeedback), (92 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_UpdateFeedback), (8 bytes). + Removing chassis.o(.text.Chassis_Control), (628 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_Control), (8 bytes). + Removing chassis.o(.text.__ARM_isfinitef), (14 bytes). + Removing chassis.o(.ARM.exidx.text.__ARM_isfinitef), (8 bytes). + Removing chassis.o(.text.Chassis_SetMode), (144 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_SetMode), (8 bytes). + Removing chassis.o(.text.Chassis_CalcWz), (80 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_CalcWz), (8 bytes). + Removing chassis.o(.text.Chassis_Output), (96 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_Output), (8 bytes). + Removing chassis.o(.text.Chassis_ResetOutput), (48 bytes). + Removing chassis.o(.ARM.exidx.text.Chassis_ResetOutput), (8 bytes). + Removing gimbal.o(.text), (0 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_Init), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_UpdateFeedback), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_UpdateIMU), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_Direction), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.major_yaw_Control), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_Control_mode), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_Control), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_SetMode), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.motor_imu_offset), (8 bytes). + Removing gimbal.o(.ARM.exidx.text.Gimbal_Output), (8 bytes). + Removing remote_cmd.o(.text), (0 bytes). + Removing remote_cmd.o(.ARM.exidx.text.Gimbal_Cmd), (8 bytes). + Removing remote_cmd.o(.ARM.exidx.text.Shoot_Cmd), (8 bytes). + Removing shoot.o(.text), (0 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_SetMode), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_ResetIntegral), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_ResetCalu), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_ResetOutput), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_CaluTargetRPM), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_CaluTargetAngle), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_UpdateFeedback), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_RunningFSM), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_CaluCoupledWeight), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_JamDetectionFSM), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_Init), (8 bytes). + Removing shoot.o(.ARM.exidx.text.Shoot_Control), (8 bytes). + Removing shoot.o(.bss.a), (4 bytes). + +2078 unused section(s) (total 80146 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/dczerorl2.s 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr_intlibspace.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/fenv.c 0x00000000 Number 0 _rserrno.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/longlong.s 0x00000000 Number 0 lludivv7m.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_v6.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 aeabi_memset.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 aeabi_memset4.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 strncpy.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2snprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2snprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_str.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _sputc.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _snputc.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_s.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 rand.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 rand.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strlen.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strncmp.o ABSOLUTE + ../fplib/basic.s 0x00000000 Number 0 basic.o ABSOLUTE + ../fplib/d2f.s 0x00000000 Number 0 d2f.o ABSOLUTE + ../fplib/daddsub.s 0x00000000 Number 0 daddsub_clz.o ABSOLUTE + ../fplib/dcmpi.s 0x00000000 Number 0 dcmpi.o ABSOLUTE + ../fplib/ddiv.s 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/deqf.s 0x00000000 Number 0 deqf.o ABSOLUTE + ../fplib/dfixu.s 0x00000000 Number 0 dfixu.o ABSOLUTE + ../fplib/dflt.s 0x00000000 Number 0 dflt_clz.o ABSOLUTE + ../fplib/dmul.s 0x00000000 Number 0 dmul.o ABSOLUTE + ../fplib/dnaninf.s 0x00000000 Number 0 dnaninf.o ABSOLUTE + ../fplib/dretinf.s 0x00000000 Number 0 dretinf.o ABSOLUTE + ../fplib/f2d.s 0x00000000 Number 0 f2d.o ABSOLUTE + ../fplib/ffltll.s 0x00000000 Number 0 ffltll_clz.o ABSOLUTE + ../fplib/fnaninf.s 0x00000000 Number 0 fnaninf.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/fretinf.s 0x00000000 Number 0 fretinf.o ABSOLUTE + ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE + ../mathlib/asinf.c 0x00000000 Number 0 asinf.o ABSOLUTE + ../mathlib/atan.c 0x00000000 Number 0 atan.o ABSOLUTE + ../mathlib/atan2.c 0x00000000 Number 0 atan2.o ABSOLUTE + ../mathlib/atan2f.c 0x00000000 Number 0 atan2f.o ABSOLUTE + ../mathlib/cosf.c 0x00000000 Number 0 cosf.o ABSOLUTE + ../mathlib/dunder.c 0x00000000 Number 0 dunder.o ABSOLUTE + ../mathlib/fabs.c 0x00000000 Number 0 fabs.o ABSOLUTE + ../mathlib/fpclassify.c 0x00000000 Number 0 fpclassify.o ABSOLUTE + ../mathlib/fpclassifyf.c 0x00000000 Number 0 fpclassifyf.o ABSOLUTE + ../mathlib/funder.c 0x00000000 Number 0 funder.o ABSOLUTE + ../mathlib/poly.c 0x00000000 Number 0 poly.o ABSOLUTE + ../mathlib/qnan.c 0x00000000 Number 0 qnan.o ABSOLUTE + ../mathlib/rredf.c 0x00000000 Number 0 rredf.o ABSOLUTE + ../mathlib/sinf.c 0x00000000 Number 0 sinf.o ABSOLUTE + ../mathlib/sqrtf.c 0x00000000 Number 0 sqrtf.o ABSOLUTE + ../mathlib/tanf.c 0x00000000 Number 0 tanf.o ABSOLUTE + ahrs.c 0x00000000 Number 0 ahrs.o ABSOLUTE + ai.c 0x00000000 Number 0 ai.o ABSOLUTE + ai.c 0x00000000 Number 0 ai_1.o ABSOLUTE + atti_esti.c 0x00000000 Number 0 atti_esti.o ABSOLUTE + bmi088.c 0x00000000 Number 0 bmi088.o ABSOLUTE + can.c 0x00000000 Number 0 can.o ABSOLUTE + can.c 0x00000000 Number 0 can_1.o ABSOLUTE + capacity.c 0x00000000 Number 0 capacity.o ABSOLUTE + chassis.c 0x00000000 Number 0 chassis.o ABSOLUTE + chassis_ctrl.c 0x00000000 Number 0 chassis_ctrl.o ABSOLUTE + cmd.c 0x00000000 Number 0 cmd.o ABSOLUTE + cmsis_os2.c 0x00000000 Number 0 cmsis_os2.o ABSOLUTE + config.c 0x00000000 Number 0 config.o ABSOLUTE + crc16.c 0x00000000 Number 0 crc16.o ABSOLUTE + crc8.c 0x00000000 Number 0 crc8.o ABSOLUTE + croutine.c 0x00000000 Number 0 croutine.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + dma.c 0x00000000 Number 0 dma.o ABSOLUTE + dr16.c 0x00000000 Number 0 dr16.o ABSOLUTE + dr16.c 0x00000000 Number 0 dr16_1.o ABSOLUTE + error_detect.c 0x00000000 Number 0 error_detect.o ABSOLUTE + event_groups.c 0x00000000 Number 0 event_groups.o ABSOLUTE + filter.c 0x00000000 Number 0 filter.o ABSOLUTE + freertos.c 0x00000000 Number 0 freertos.o ABSOLUTE + freertos_cli.c 0x00000000 Number 0 freertos_cli.o ABSOLUTE + gimbal.c 0x00000000 Number 0 gimbal.o ABSOLUTE + gimbal_ctrl.c 0x00000000 Number 0 gimbal_ctrl.o ABSOLUTE + gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + gpio.c 0x00000000 Number 0 gpio_1.o ABSOLUTE + heap_4.c 0x00000000 Number 0 heap_4.o ABSOLUTE + i2c.c 0x00000000 Number 0 i2c.o ABSOLUTE + i2c.c 0x00000000 Number 0 i2c_1.o ABSOLUTE + init.c 0x00000000 Number 0 init.o ABSOLUTE + ist8310.c 0x00000000 Number 0 ist8310.o ABSOLUTE + limiter.c 0x00000000 Number 0 limiter.o ABSOLUTE + list.c 0x00000000 Number 0 list.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + mixer.c 0x00000000 Number 0 mixer.o ABSOLUTE + mm.c 0x00000000 Number 0 mm.o ABSOLUTE + motor.c 0x00000000 Number 0 motor.o ABSOLUTE + motor_dm.c 0x00000000 Number 0 motor_dm.o ABSOLUTE + motor_rm.c 0x00000000 Number 0 motor_rm.o ABSOLUTE + pid.c 0x00000000 Number 0 pid.o ABSOLUTE + port.c 0x00000000 Number 0 port.o ABSOLUTE + pwm.c 0x00000000 Number 0 pwm.o ABSOLUTE + queue.c 0x00000000 Number 0 queue.o ABSOLUTE + remote.c 0x00000000 Number 0 remote.o ABSOLUTE + remote_cmd.c 0x00000000 Number 0 remote_cmd.o ABSOLUTE + shoot.c 0x00000000 Number 0 shoot.o ABSOLUTE + shoot_ctrl.c 0x00000000 Number 0 shoot_ctrl.o ABSOLUTE + spi.c 0x00000000 Number 0 spi.o ABSOLUTE + spi.c 0x00000000 Number 0 spi_1.o ABSOLUTE + startup_stm32f407xx.s 0x00000000 Number 0 startup_stm32f407xx.o ABSOLUTE + stm32f4xx_hal.c 0x00000000 Number 0 stm32f4xx_hal.o ABSOLUTE + stm32f4xx_hal_can.c 0x00000000 Number 0 stm32f4xx_hal_can.o ABSOLUTE + stm32f4xx_hal_cortex.c 0x00000000 Number 0 stm32f4xx_hal_cortex.o ABSOLUTE + stm32f4xx_hal_dma.c 0x00000000 Number 0 stm32f4xx_hal_dma.o ABSOLUTE + stm32f4xx_hal_dma_ex.c 0x00000000 Number 0 stm32f4xx_hal_dma_ex.o ABSOLUTE + stm32f4xx_hal_exti.c 0x00000000 Number 0 stm32f4xx_hal_exti.o ABSOLUTE + stm32f4xx_hal_flash.c 0x00000000 Number 0 stm32f4xx_hal_flash.o ABSOLUTE + stm32f4xx_hal_flash_ex.c 0x00000000 Number 0 stm32f4xx_hal_flash_ex.o ABSOLUTE + stm32f4xx_hal_flash_ramfunc.c 0x00000000 Number 0 stm32f4xx_hal_flash_ramfunc.o ABSOLUTE + stm32f4xx_hal_gpio.c 0x00000000 Number 0 stm32f4xx_hal_gpio.o ABSOLUTE + stm32f4xx_hal_i2c.c 0x00000000 Number 0 stm32f4xx_hal_i2c.o ABSOLUTE + stm32f4xx_hal_i2c_ex.c 0x00000000 Number 0 stm32f4xx_hal_i2c_ex.o ABSOLUTE + stm32f4xx_hal_msp.c 0x00000000 Number 0 stm32f4xx_hal_msp.o ABSOLUTE + stm32f4xx_hal_pwr.c 0x00000000 Number 0 stm32f4xx_hal_pwr.o ABSOLUTE + stm32f4xx_hal_pwr_ex.c 0x00000000 Number 0 stm32f4xx_hal_pwr_ex.o ABSOLUTE + stm32f4xx_hal_rcc.c 0x00000000 Number 0 stm32f4xx_hal_rcc.o ABSOLUTE + stm32f4xx_hal_rcc_ex.c 0x00000000 Number 0 stm32f4xx_hal_rcc_ex.o ABSOLUTE + stm32f4xx_hal_spi.c 0x00000000 Number 0 stm32f4xx_hal_spi.o ABSOLUTE + stm32f4xx_hal_tim.c 0x00000000 Number 0 stm32f4xx_hal_tim.o ABSOLUTE + stm32f4xx_hal_tim_ex.c 0x00000000 Number 0 stm32f4xx_hal_tim_ex.o ABSOLUTE + stm32f4xx_hal_uart.c 0x00000000 Number 0 stm32f4xx_hal_uart.o ABSOLUTE + stm32f4xx_it.c 0x00000000 Number 0 stm32f4xx_it.o ABSOLUTE + stream_buffer.c 0x00000000 Number 0 stream_buffer.o ABSOLUTE + system_stm32f4xx.c 0x00000000 Number 0 system_stm32f4xx.o ABSOLUTE + tasks.c 0x00000000 Number 0 tasks.o ABSOLUTE + tim.c 0x00000000 Number 0 tim.o ABSOLUTE + time.c 0x00000000 Number 0 time.o ABSOLUTE + timers.c 0x00000000 Number 0 timers.o ABSOLUTE + uart.c 0x00000000 Number 0 uart.o ABSOLUTE + ui.c 0x00000000 Number 0 ui.o ABSOLUTE + usart.c 0x00000000 Number 0 usart.o ABSOLUTE + user_math.c 0x00000000 Number 0 user_math.o ABSOLUTE + user_task.c 0x00000000 Number 0 user_task.o ABSOLUTE + RESET 0x08000000 Section 392 startup_stm32f407xx.o(RESET) + !!!main 0x08000188 Section 8 __main.o(!!!main) + !!!scatter 0x08000190 Section 52 __scatter.o(!!!scatter) + !!dczerorl2 0x080001c4 Section 90 __dczerorl2.o(!!dczerorl2) + !!handler_copy 0x08000220 Section 26 __scatter_copy.o(!!handler_copy) + !!handler_zi 0x0800023c Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$libinit$$00000000 0x08000258 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000001 0x0800025a Section 4 libinit2.o(.ARM.Collect$$libinit$$00000001) + .ARM.Collect$$libinit$$00000004 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x0800025e Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x0800025e Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x08000260 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x08000262 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x08000262 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x08000264 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x08000264 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x08000264 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0800026a Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0800026a Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x0800026e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x0800026e Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x08000276 Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x08000278 Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x08000278 Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x0800027c Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + $v0 0x08000284 Number 0 startup_stm32f407xx.o(.text) + .text 0x08000284 Section 64 startup_stm32f407xx.o(.text) + .text 0x080002c4 Section 240 lludivv7m.o(.text) + .text 0x080003b4 Section 138 rt_memcpy_v6.o(.text) + .text 0x0800043e Section 100 rt_memcpy_w.o(.text) + .text 0x080004a2 Section 16 aeabi_memset4.o(.text) + .text 0x080004b2 Section 78 rt_memclr_w.o(.text) + .text 0x08000500 Section 0 heapauxi.o(.text) + .text 0x08000506 Section 0 _rserrno.o(.text) + .text 0x0800051c Section 8 rt_errno_addr_intlibspace.o(.text) + .text 0x08000524 Section 8 libspace.o(.text) + .text 0x0800052c Section 74 sys_stackheap_outer.o(.text) + .text 0x08000576 Section 0 exit.o(.text) + .text 0x08000588 Section 0 sys_exit.o(.text) + .text 0x08000594 Section 2 use_no_semi.o(.text) + .text 0x08000596 Section 0 indicate_semi.o(.text) + [Anonymous Symbol] 0x08000598 Section 0 ahrs.o(.text.AHRS_GetEulr) + [Anonymous Symbol] 0x08000674 Section 0 ahrs.o(.text.AHRS_Init) + [Anonymous Symbol] 0x080007f8 Section 0 ahrs.o(.text.AHRS_ResetEulr) + [Anonymous Symbol] 0x08000804 Section 0 ahrs.o(.text.AHRS_Update) + AHRS_UpdateIMU 0x08000d95 Thumb Code 752 ahrs.o(.text.AHRS_UpdateIMU) + [Anonymous Symbol] 0x08000d94 Section 0 ahrs.o(.text.AHRS_UpdateIMU) + [Anonymous Symbol] 0x08001084 Section 0 ai.o(.text.AI_Get_NUC) + [Anonymous Symbol] 0x080010d8 Section 0 ai.o(.text.AI_ParseHost) + [Anonymous Symbol] 0x08001134 Section 0 ai.o(.text.AI_StartReceiving) + [Anonymous Symbol] 0x08001150 Section 0 ai.o(.text.AI_StartSend) + [Anonymous Symbol] 0x08001164 Section 0 user_math.o(.text.AbsClip) + BMI088_AcclIntCallback 0x08001189 Thumb Code 20 bmi088.o(.text.BMI088_AcclIntCallback) + [Anonymous Symbol] 0x08001188 Section 0 bmi088.o(.text.BMI088_AcclIntCallback) + [Anonymous Symbol] 0x0800119c Section 0 bmi088.o(.text.BMI088_AcclStartDmaRecv) + [Anonymous Symbol] 0x080011b4 Section 0 bmi088.o(.text.BMI088_AcclWaitDmaCplt) + [Anonymous Symbol] 0x080011c4 Section 0 bmi088.o(.text.BMI088_GetUpdateFreq) + BMI088_GyroIntCallback 0x080011d1 Thumb Code 20 bmi088.o(.text.BMI088_GyroIntCallback) + [Anonymous Symbol] 0x080011d0 Section 0 bmi088.o(.text.BMI088_GyroIntCallback) + [Anonymous Symbol] 0x080011e4 Section 0 bmi088.o(.text.BMI088_GyroStartDmaRecv) + [Anonymous Symbol] 0x08001200 Section 0 bmi088.o(.text.BMI088_GyroWaitDmaCplt) + [Anonymous Symbol] 0x08001210 Section 0 bmi088.o(.text.BMI088_Init) + [Anonymous Symbol] 0x08001354 Section 0 bmi088.o(.text.BMI088_ParseAccl) + [Anonymous Symbol] 0x080013e8 Section 0 bmi088.o(.text.BMI088_ParseGyro) + BMI088_RxCpltCallback 0x0800146d Thumb Code 64 bmi088.o(.text.BMI088_RxCpltCallback) + [Anonymous Symbol] 0x0800146c Section 0 bmi088.o(.text.BMI088_RxCpltCallback) + [Anonymous Symbol] 0x080014ac Section 0 bmi088.o(.text.BMI088_WaitNew) + BMI_Read 0x080014bd Thumb Code 68 bmi088.o(.text.BMI_Read) + [Anonymous Symbol] 0x080014bc Section 0 bmi088.o(.text.BMI_Read) + BMI_ReadSingle 0x08001501 Thumb Code 94 bmi088.o(.text.BMI_ReadSingle) + [Anonymous Symbol] 0x08001500 Section 0 bmi088.o(.text.BMI_ReadSingle) + BMI_WriteSingle 0x08001561 Thumb Code 72 bmi088.o(.text.BMI_WriteSingle) + [Anonymous Symbol] 0x08001560 Section 0 bmi088.o(.text.BMI_WriteSingle) + BSP_CAN_CreateIdQueue 0x080015a9 Thumb Code 146 can_1.o(.text.BSP_CAN_CreateIdQueue) + [Anonymous Symbol] 0x080015a8 Section 0 can_1.o(.text.BSP_CAN_CreateIdQueue) + BSP_CAN_DefaultIdParser 0x0800163d Thumb Code 2 can_1.o(.text.BSP_CAN_DefaultIdParser) + [Anonymous Symbol] 0x0800163c Section 0 can_1.o(.text.BSP_CAN_DefaultIdParser) + BSP_CAN_FindQueue 0x08001641 Thumb Code 38 can_1.o(.text.BSP_CAN_FindQueue) + [Anonymous Symbol] 0x08001640 Section 0 can_1.o(.text.BSP_CAN_FindQueue) + BSP_CAN_GetFrameType 0x08001669 Thumb Code 26 can_1.o(.text.BSP_CAN_GetFrameType) + [Anonymous Symbol] 0x08001668 Section 0 can_1.o(.text.BSP_CAN_GetFrameType) + [Anonymous Symbol] 0x08001684 Section 0 can_1.o(.text.BSP_CAN_GetHandle) + [Anonymous Symbol] 0x080016ac Section 0 can_1.o(.text.BSP_CAN_GetMessage) + [Anonymous Symbol] 0x0800172c Section 0 can_1.o(.text.BSP_CAN_Init) + [Anonymous Symbol] 0x08001860 Section 0 can_1.o(.text.BSP_CAN_ParseId) + [Anonymous Symbol] 0x08001874 Section 0 can_1.o(.text.BSP_CAN_RegisterCallback) + [Anonymous Symbol] 0x080018b8 Section 0 can_1.o(.text.BSP_CAN_RegisterId) + BSP_CAN_RxFifo0Callback 0x080018d9 Thumb Code 194 can_1.o(.text.BSP_CAN_RxFifo0Callback) + [Anonymous Symbol] 0x080018d8 Section 0 can_1.o(.text.BSP_CAN_RxFifo0Callback) + BSP_CAN_RxFifo1Callback 0x0800199d Thumb Code 194 can_1.o(.text.BSP_CAN_RxFifo1Callback) + [Anonymous Symbol] 0x0800199c Section 0 can_1.o(.text.BSP_CAN_RxFifo1Callback) + [Anonymous Symbol] 0x08001a60 Section 0 can_1.o(.text.BSP_CAN_Transmit) + [Anonymous Symbol] 0x08001b44 Section 0 can_1.o(.text.BSP_CAN_TransmitStdDataFrame) + BSP_CAN_TxCompleteCallback 0x08001b6d Thumb Code 100 can_1.o(.text.BSP_CAN_TxCompleteCallback) + [Anonymous Symbol] 0x08001b6c Section 0 can_1.o(.text.BSP_CAN_TxCompleteCallback) + BSP_CAN_TxQueueInit 0x08001bd1 Thumb Code 28 can_1.o(.text.BSP_CAN_TxQueueInit) + [Anonymous Symbol] 0x08001bd0 Section 0 can_1.o(.text.BSP_CAN_TxQueueInit) + BSP_CAN_TxQueueIsEmpty 0x08001bed Thumb Code 34 can_1.o(.text.BSP_CAN_TxQueueIsEmpty) + [Anonymous Symbol] 0x08001bec Section 0 can_1.o(.text.BSP_CAN_TxQueueIsEmpty) + BSP_CAN_TxQueuePop 0x08001c11 Thumb Code 116 can_1.o(.text.BSP_CAN_TxQueuePop) + [Anonymous Symbol] 0x08001c10 Section 0 can_1.o(.text.BSP_CAN_TxQueuePop) + BSP_CAN_TxQueuePush 0x08001c85 Thumb Code 126 can_1.o(.text.BSP_CAN_TxQueuePush) + [Anonymous Symbol] 0x08001c84 Section 0 can_1.o(.text.BSP_CAN_TxQueuePush) + [Anonymous Symbol] 0x08001d04 Section 0 mm.o(.text.BSP_Free) + [Anonymous Symbol] 0x08001d0c Section 0 gpio_1.o(.text.BSP_GPIO_DisableIRQ) + [Anonymous Symbol] 0x08001d3c Section 0 gpio_1.o(.text.BSP_GPIO_EnableIRQ) + [Anonymous Symbol] 0x08001d6c Section 0 gpio_1.o(.text.BSP_GPIO_ReadPin) + [Anonymous Symbol] 0x08001d98 Section 0 gpio_1.o(.text.BSP_GPIO_RegisterCallback) + [Anonymous Symbol] 0x08001de4 Section 0 gpio_1.o(.text.BSP_GPIO_WritePin) + [Anonymous Symbol] 0x08001e14 Section 0 mm.o(.text.BSP_Malloc) + [Anonymous Symbol] 0x08001e1c Section 0 pwm.o(.text.BSP_PWM_SetComp) + [Anonymous Symbol] 0x08001e78 Section 0 pwm.o(.text.BSP_PWM_Start) + [Anonymous Symbol] 0x08001e98 Section 0 spi_1.o(.text.BSP_SPI_GetHandle) + [Anonymous Symbol] 0x08001eac Section 0 spi_1.o(.text.BSP_SPI_Receive) + [Anonymous Symbol] 0x08001ee0 Section 0 spi_1.o(.text.BSP_SPI_RegisterCallback) + [Anonymous Symbol] 0x08001f00 Section 0 spi_1.o(.text.BSP_SPI_Transmit) + [Anonymous Symbol] 0x08001f34 Section 0 time.o(.text.BSP_TIME_Delay_ms) + [Anonymous Symbol] 0x08001f8c Section 0 time.o(.text.BSP_TIME_Get_us) + [Anonymous Symbol] 0x08001fdc Section 0 uart.o(.text.BSP_UART_GetHandle) + [Anonymous Symbol] 0x08001ffc Section 0 uart.o(.text.BSP_UART_IRQHandler) + [Anonymous Symbol] 0x08002038 Section 0 uart.o(.text.BSP_UART_Receive) + [Anonymous Symbol] 0x08002078 Section 0 uart.o(.text.BSP_UART_RegisterCallback) + [Anonymous Symbol] 0x080020ac Section 0 uart.o(.text.BSP_UART_Transmit) + [Anonymous Symbol] 0x080020ec Section 0 stm32f4xx_it.o(.text.BusFault_Handler) + [Anonymous Symbol] 0x080020f0 Section 0 stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) + [Anonymous Symbol] 0x08002100 Section 0 stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) + [Anonymous Symbol] 0x08002110 Section 0 stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) + [Anonymous Symbol] 0x08002120 Section 0 stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) + [Anonymous Symbol] 0x08002130 Section 0 stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) + [Anonymous Symbol] 0x08002140 Section 0 stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) + [Anonymous Symbol] 0x08002150 Section 0 stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) + CAN_Get 0x08002161 Thumb Code 36 can_1.o(.text.CAN_Get) + [Anonymous Symbol] 0x08002160 Section 0 can_1.o(.text.CAN_Get) + CRC16_Byte 0x08002185 Thumb Code 22 crc16.o(.text.CRC16_Byte) + [Anonymous Symbol] 0x08002184 Section 0 crc16.o(.text.CRC16_Byte) + [Anonymous Symbol] 0x0800219c Section 0 crc16.o(.text.CRC16_Calc) + [Anonymous Symbol] 0x080021bc Section 0 crc16.o(.text.CRC16_Verify) + [Anonymous Symbol] 0x080021f0 Section 0 user_math.o(.text.CircleAdd) + [Anonymous Symbol] 0x0800222c Section 0 user_math.o(.text.CircleError) + [Anonymous Symbol] 0x08002268 Section 0 user_math.o(.text.Clip) + [Anonymous Symbol] 0x08002290 Section 0 config.o(.text.Config_GetRobotParam) + [Anonymous Symbol] 0x0800229c Section 0 stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) + [Anonymous Symbol] 0x080022ac Section 0 stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) + [Anonymous Symbol] 0x080022bc Section 0 stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) + DMA_CalcBaseAndBitshift 0x080022cd Thumb Code 52 stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) + [Anonymous Symbol] 0x080022cc Section 0 stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) + DMA_CalcBaseAndBitshift.flagBitshiftOffset 0x08002300 Number 0 stm32f4xx_hal_dma.o(.text.DMA_CalcBaseAndBitshift) + DMA_CheckFifoParam 0x08002309 Thumb Code 80 stm32f4xx_hal_dma.o(.text.DMA_CheckFifoParam) + [Anonymous Symbol] 0x08002308 Section 0 stm32f4xx_hal_dma.o(.text.DMA_CheckFifoParam) + DMA_SetConfig 0x08002359 Thumb Code 48 stm32f4xx_hal_dma.o(.text.DMA_SetConfig) + [Anonymous Symbol] 0x08002358 Section 0 stm32f4xx_hal_dma.o(.text.DMA_SetConfig) + DR16_DataCorrupted 0x08002389 Thumb Code 110 dr16.o(.text.DR16_DataCorrupted) + [Anonymous Symbol] 0x08002388 Section 0 dr16.o(.text.DR16_DataCorrupted) + [Anonymous Symbol] 0x080023f8 Section 0 dr16.o(.text.DR16_Init) + [Anonymous Symbol] 0x08002440 Section 0 dr16.o(.text.DR16_Offline) + [Anonymous Symbol] 0x0800245c Section 0 dr16.o(.text.DR16_ParseData) + DR16_RxCpltCallback 0x08002591 Thumb Code 20 dr16.o(.text.DR16_RxCpltCallback) + [Anonymous Symbol] 0x08002590 Section 0 dr16.o(.text.DR16_RxCpltCallback) + [Anonymous Symbol] 0x080025a4 Section 0 dr16.o(.text.DR16_StartDmaRecv) + [Anonymous Symbol] 0x080025c4 Section 0 dr16.o(.text.DR16_WaitDmaCplt) + [Anonymous Symbol] 0x080025dc Section 0 stm32f4xx_it.o(.text.DebugMon_Handler) + [Anonymous Symbol] 0x080025e0 Section 0 stm32f4xx_it.o(.text.EXTI0_IRQHandler) + [Anonymous Symbol] 0x080025ec Section 0 stm32f4xx_it.o(.text.EXTI3_IRQHandler) + [Anonymous Symbol] 0x080025f8 Section 0 stm32f4xx_it.o(.text.EXTI4_IRQHandler) + [Anonymous Symbol] 0x08002604 Section 0 stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) + [Anonymous Symbol] 0x08002610 Section 0 main.o(.text.Error_Handler) + [Anonymous Symbol] 0x08002618 Section 0 remote_cmd.o(.text.Gimbal_Cmd) + [Anonymous Symbol] 0x080026c0 Section 0 gimbal.o(.text.Gimbal_Control) + [Anonymous Symbol] 0x08002a60 Section 0 gimbal.o(.text.Gimbal_Control_mode) + Gimbal_Direction 0x08002ab9 Thumb Code 164 gimbal.o(.text.Gimbal_Direction) + [Anonymous Symbol] 0x08002ab8 Section 0 gimbal.o(.text.Gimbal_Direction) + [Anonymous Symbol] 0x08002b5c Section 0 gimbal.o(.text.Gimbal_Init) + [Anonymous Symbol] 0x08002cac Section 0 gimbal.o(.text.Gimbal_Output) + Gimbal_SetMode 0x08002dc5 Thumb Code 136 gimbal.o(.text.Gimbal_SetMode) + [Anonymous Symbol] 0x08002dc4 Section 0 gimbal.o(.text.Gimbal_SetMode) + [Anonymous Symbol] 0x08002e4c Section 0 gimbal.o(.text.Gimbal_UpdateFeedback) + [Anonymous Symbol] 0x08002f64 Section 0 gimbal.o(.text.Gimbal_UpdateIMU) + [Anonymous Symbol] 0x08002fb4 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_ActivateNotification) + [Anonymous Symbol] 0x08002fdc Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage) + [Anonymous Symbol] 0x08003070 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_ConfigFilter) + [Anonymous Symbol] 0x08003150 Section 0 can_1.o(.text.HAL_CAN_ErrorCallback) + [Anonymous Symbol] 0x08003174 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel) + [Anonymous Symbol] 0x08003194 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage) + [Anonymous Symbol] 0x080032b8 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel) + [Anonymous Symbol] 0x080032e0 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) + [Anonymous Symbol] 0x0800351c Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_Init) + [Anonymous Symbol] 0x08003610 Section 0 can.o(.text.HAL_CAN_MspInit) + [Anonymous Symbol] 0x0800377c Section 0 can_1.o(.text.HAL_CAN_RxFifo0FullCallback) + [Anonymous Symbol] 0x080037a0 Section 0 can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) + [Anonymous Symbol] 0x080037c4 Section 0 can_1.o(.text.HAL_CAN_RxFifo1FullCallback) + [Anonymous Symbol] 0x080037e8 Section 0 can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) + [Anonymous Symbol] 0x0800380c Section 0 can_1.o(.text.HAL_CAN_SleepCallback) + [Anonymous Symbol] 0x08003830 Section 0 stm32f4xx_hal_can.o(.text.HAL_CAN_Start) + [Anonymous Symbol] 0x0800388c Section 0 can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) + [Anonymous Symbol] 0x080038b0 Section 0 can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) + [Anonymous Symbol] 0x080038d4 Section 0 can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) + [Anonymous Symbol] 0x080038f8 Section 0 can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) + [Anonymous Symbol] 0x0800391c Section 0 can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) + [Anonymous Symbol] 0x08003940 Section 0 can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) + [Anonymous Symbol] 0x08003964 Section 0 can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) + [Anonymous Symbol] 0x08003988 Section 0 stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) + [Anonymous Symbol] 0x08003a08 Section 0 stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) + [Anonymous Symbol] 0x08003a2c Section 0 stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) + [Anonymous Symbol] 0x08003bb8 Section 0 stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) + [Anonymous Symbol] 0x08003c88 Section 0 stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) + [Anonymous Symbol] 0x08003cec Section 0 stm32f4xx_hal.o(.text.HAL_Delay) + [Anonymous Symbol] 0x08003d14 Section 0 gpio_1.o(.text.HAL_GPIO_EXTI_Callback) + [Anonymous Symbol] 0x08003d40 Section 0 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) + [Anonymous Symbol] 0x08003d5c Section 0 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) + [Anonymous Symbol] 0x08003ef8 Section 0 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) + [Anonymous Symbol] 0x08003f04 Section 0 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin) + [Anonymous Symbol] 0x08003f10 Section 0 stm32f4xx_hal.o(.text.HAL_GetTick) + [Anonymous Symbol] 0x08003f1c Section 0 stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) + [Anonymous Symbol] 0x080040b4 Section 0 i2c.o(.text.HAL_I2C_MspInit) + [Anonymous Symbol] 0x08004124 Section 0 stm32f4xx_hal.o(.text.HAL_IncTick) + [Anonymous Symbol] 0x08004140 Section 0 stm32f4xx_hal.o(.text.HAL_Init) + [Anonymous Symbol] 0x08004178 Section 0 stm32f4xx_hal.o(.text.HAL_InitTick) + [Anonymous Symbol] 0x080041c8 Section 0 stm32f4xx_hal_msp.o(.text.HAL_MspInit) + [Anonymous Symbol] 0x08004210 Section 0 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) + [Anonymous Symbol] 0x08004218 Section 0 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) + [Anonymous Symbol] 0x08004220 Section 0 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) + [Anonymous Symbol] 0x08004240 Section 0 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) + [Anonymous Symbol] 0x08004248 Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) + [Anonymous Symbol] 0x080043a8 Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) + [Anonymous Symbol] 0x080043b4 Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) + [Anonymous Symbol] 0x080043d8 Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) + [Anonymous Symbol] 0x080043fc Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) + [Anonymous Symbol] 0x08004464 Section 0 stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig) + [Anonymous Symbol] 0x080047ac Section 0 spi_1.o(.text.HAL_SPI_ErrorCallback) + [Anonymous Symbol] 0x080047d0 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_Init) + [Anonymous Symbol] 0x08004884 Section 0 spi.o(.text.HAL_SPI_MspInit) + [Anonymous Symbol] 0x080049b4 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) + [Anonymous Symbol] 0x08004b28 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) + [Anonymous Symbol] 0x08004c14 Section 0 spi_1.o(.text.HAL_SPI_RxCpltCallback) + [Anonymous Symbol] 0x08004c38 Section 0 spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) + [Anonymous Symbol] 0x08004c5c Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) + [Anonymous Symbol] 0x08004de8 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) + [Anonymous Symbol] 0x08004fe0 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) + [Anonymous Symbol] 0x08005104 Section 0 stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) + [Anonymous Symbol] 0x080051d0 Section 0 spi_1.o(.text.HAL_SPI_TxCpltCallback) + [Anonymous Symbol] 0x080051f0 Section 0 spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) + [Anonymous Symbol] 0x08005214 Section 0 spi_1.o(.text.HAL_SPI_TxRxCpltCallback) + [Anonymous Symbol] 0x08005238 Section 0 spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) + [Anonymous Symbol] 0x0800525c Section 0 stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config) + [Anonymous Symbol] 0x08005264 Section 0 stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) + [Anonymous Symbol] 0x080052c0 Section 0 tim.o(.text.HAL_TIM_Base_MspInit) + [Anonymous Symbol] 0x080052f8 Section 0 tim.o(.text.HAL_TIM_MspPostInit) + [Anonymous Symbol] 0x08005358 Section 0 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) + [Anonymous Symbol] 0x080053f0 Section 0 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) + [Anonymous Symbol] 0x0800544c Section 0 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) + [Anonymous Symbol] 0x08005450 Section 0 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start) + [Anonymous Symbol] 0x08005574 Section 0 stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) + [Anonymous Symbol] 0x08005578 Section 0 uart.o(.text.HAL_UART_ErrorCallback) + [Anonymous Symbol] 0x080055a0 Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) + [Anonymous Symbol] 0x080057fc Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_Init) + [Anonymous Symbol] 0x0800585c Section 0 usart.o(.text.HAL_UART_MspInit) + [Anonymous Symbol] 0x08005ac4 Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) + [Anonymous Symbol] 0x08005af0 Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT) + [Anonymous Symbol] 0x08005b1c Section 0 uart.o(.text.HAL_UART_RxCpltCallback) + [Anonymous Symbol] 0x08005b44 Section 0 uart.o(.text.HAL_UART_RxHalfCpltCallback) + [Anonymous Symbol] 0x08005b6c Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) + [Anonymous Symbol] 0x08005bf8 Section 0 stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_IT) + [Anonymous Symbol] 0x08005c30 Section 0 uart.o(.text.HAL_UART_TxCpltCallback) + [Anonymous Symbol] 0x08005c58 Section 0 uart.o(.text.HAL_UART_TxHalfCpltCallback) + [Anonymous Symbol] 0x08005c7c Section 0 stm32f4xx_it.o(.text.HardFault_Handler) + [Anonymous Symbol] 0x08005c80 Section 0 user_math.o(.text.InvSqrt) + [Anonymous Symbol] 0x08005cc4 Section 0 filter.o(.text.LowPassFilter2p_Apply) + [Anonymous Symbol] 0x08005d40 Section 0 filter.o(.text.LowPassFilter2p_Init) + [Anonymous Symbol] 0x08005de4 Section 0 filter.o(.text.LowPassFilter2p_Reset) + MOTOR_DM_CreateCANManager 0x08005e41 Thumb Code 60 motor_dm.o(.text.MOTOR_DM_CreateCANManager) + [Anonymous Symbol] 0x08005e40 Section 0 motor_dm.o(.text.MOTOR_DM_CreateCANManager) + [Anonymous Symbol] 0x08005e7c Section 0 motor_dm.o(.text.MOTOR_DM_Enable) + MOTOR_DM_GetCANManager 0x08005ec5 Thumb Code 20 motor_dm.o(.text.MOTOR_DM_GetCANManager) + [Anonymous Symbol] 0x08005ec4 Section 0 motor_dm.o(.text.MOTOR_DM_GetCANManager) + [Anonymous Symbol] 0x08005ed8 Section 0 motor_dm.o(.text.MOTOR_DM_GetMotor) + [Anonymous Symbol] 0x08005f30 Section 0 motor_dm.o(.text.MOTOR_DM_MITCtrl) + MOTOR_DM_ParseFeedbackFrame 0x08005f61 Thumb Code 248 motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame) + [Anonymous Symbol] 0x08005f60 Section 0 motor_dm.o(.text.MOTOR_DM_ParseFeedbackFrame) + [Anonymous Symbol] 0x08006058 Section 0 motor_dm.o(.text.MOTOR_DM_Register) + MOTOR_DM_SendMITCmd 0x080060fd Thumb Code 280 motor_dm.o(.text.MOTOR_DM_SendMITCmd) + [Anonymous Symbol] 0x080060fc Section 0 motor_dm.o(.text.MOTOR_DM_SendMITCmd) + [Anonymous Symbol] 0x08006214 Section 0 motor_dm.o(.text.MOTOR_DM_Update) + MOTOR_RM_CreateCANManager 0x080062b5 Thumb Code 60 motor_rm.o(.text.MOTOR_RM_CreateCANManager) + [Anonymous Symbol] 0x080062b4 Section 0 motor_rm.o(.text.MOTOR_RM_CreateCANManager) + [Anonymous Symbol] 0x080062f0 Section 0 motor_rm.o(.text.MOTOR_RM_Ctrl) + MOTOR_RM_GetCANManager 0x080063c9 Thumb Code 20 motor_rm.o(.text.MOTOR_RM_GetCANManager) + [Anonymous Symbol] 0x080063c8 Section 0 motor_rm.o(.text.MOTOR_RM_GetCANManager) + MOTOR_RM_GetLSB 0x080063dd Thumb Code 38 motor_rm.o(.text.MOTOR_RM_GetLSB) + [Anonymous Symbol] 0x080063dc Section 0 motor_rm.o(.text.MOTOR_RM_GetLSB) + MOTOR_RM_GetLogicalIndex 0x08006405 Thumb Code 40 motor_rm.o(.text.MOTOR_RM_GetLogicalIndex) + [Anonymous Symbol] 0x08006404 Section 0 motor_rm.o(.text.MOTOR_RM_GetLogicalIndex) + [Anonymous Symbol] 0x0800642c Section 0 motor_rm.o(.text.MOTOR_RM_GetMotor) + MOTOR_RM_GetRatio 0x0800647d Thumb Code 36 motor_rm.o(.text.MOTOR_RM_GetRatio) + [Anonymous Symbol] 0x0800647c Section 0 motor_rm.o(.text.MOTOR_RM_GetRatio) + [Anonymous Symbol] 0x080064a0 Section 0 motor_rm.o(.text.MOTOR_RM_Register) + [Anonymous Symbol] 0x08006548 Section 0 motor_rm.o(.text.MOTOR_RM_Relax) + [Anonymous Symbol] 0x08006558 Section 0 motor_rm.o(.text.MOTOR_RM_SetOutput) + [Anonymous Symbol] 0x080065f8 Section 0 motor_rm.o(.text.MOTOR_RM_Update) + [Anonymous Symbol] 0x080066c0 Section 0 can.o(.text.MX_CAN1_Init) + [Anonymous Symbol] 0x08006700 Section 0 can.o(.text.MX_CAN2_Init) + [Anonymous Symbol] 0x08006740 Section 0 dma.o(.text.MX_DMA_Init) + [Anonymous Symbol] 0x080067ac Section 0 freertos.o(.text.MX_FREERTOS_Init) + [Anonymous Symbol] 0x080067e8 Section 0 gpio.o(.text.MX_GPIO_Init) + [Anonymous Symbol] 0x08006970 Section 0 i2c.o(.text.MX_I2C2_Init) + [Anonymous Symbol] 0x080069b0 Section 0 spi.o(.text.MX_SPI1_Init) + [Anonymous Symbol] 0x08006a00 Section 0 tim.o(.text.MX_TIM10_Init) + [Anonymous Symbol] 0x08006a88 Section 0 usart.o(.text.MX_USART1_UART_Init) + [Anonymous Symbol] 0x08006ac0 Section 0 usart.o(.text.MX_USART2_UART_Init) + [Anonymous Symbol] 0x08006af8 Section 0 usart.o(.text.MX_USART3_UART_Init) + [Anonymous Symbol] 0x08006b3c Section 0 usart.o(.text.MX_USART6_UART_Init) + [Anonymous Symbol] 0x08006b74 Section 0 stm32f4xx_it.o(.text.MemManage_Handler) + Motor_RM_Decode 0x08006b79 Thumb Code 348 motor_rm.o(.text.Motor_RM_Decode) + [Anonymous Symbol] 0x08006b78 Section 0 motor_rm.o(.text.Motor_RM_Decode) + [Anonymous Symbol] 0x08006cd4 Section 0 stm32f4xx_it.o(.text.NMI_Handler) + NVIC_EncodePriority 0x08006cd9 Thumb Code 44 stm32f4xx_hal_cortex.o(.text.NVIC_EncodePriority) + [Anonymous Symbol] 0x08006cd8 Section 0 stm32f4xx_hal_cortex.o(.text.NVIC_EncodePriority) + [Anonymous Symbol] 0x08006d04 Section 0 pid.o(.text.PID_Calc) + [Anonymous Symbol] 0x08006e74 Section 0 pid.o(.text.PID_Init) + [Anonymous Symbol] 0x08006f04 Section 0 pid.o(.text.PID_Reset) + [Anonymous Symbol] 0x08006f30 Section 0 pid.o(.text.PID_ResetIntegral) + [Anonymous Symbol] 0x08006f40 Section 0 port.o(.text.PendSV_Handler) + pxCurrentTCBConst 0x08006fa0 Number 0 port.o(.text.PendSV_Handler) + SPI_DMAError 0x08006fa5 Thumb Code 34 stm32f4xx_hal_spi.o(.text.SPI_DMAError) + [Anonymous Symbol] 0x08006fa4 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMAError) + SPI_DMAHalfReceiveCplt 0x08006fc9 Thumb Code 10 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) + [Anonymous Symbol] 0x08006fc8 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfReceiveCplt) + SPI_DMAHalfTransmitCplt 0x08006fd5 Thumb Code 10 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) + [Anonymous Symbol] 0x08006fd4 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitCplt) + SPI_DMAHalfTransmitReceiveCplt 0x08006fe1 Thumb Code 10 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) + [Anonymous Symbol] 0x08006fe0 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMAHalfTransmitReceiveCplt) + SPI_DMAReceiveCplt 0x08006fed Thumb Code 104 stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) + [Anonymous Symbol] 0x08006fec Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMAReceiveCplt) + SPI_DMATransmitCplt 0x08007055 Thumb Code 112 stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) + [Anonymous Symbol] 0x08007054 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMATransmitCplt) + SPI_DMATransmitReceiveCplt 0x080070c5 Thumb Code 90 stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) + [Anonymous Symbol] 0x080070c4 Section 0 stm32f4xx_hal_spi.o(.text.SPI_DMATransmitReceiveCplt) + SPI_EndRxTransaction 0x08007121 Thumb Code 144 stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) + [Anonymous Symbol] 0x08007120 Section 0 stm32f4xx_hal_spi.o(.text.SPI_EndRxTransaction) + SPI_EndRxTxTransaction 0x080071b1 Thumb Code 138 stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) + [Anonymous Symbol] 0x080071b0 Section 0 stm32f4xx_hal_spi.o(.text.SPI_EndRxTxTransaction) + SPI_Get 0x0800723d Thumb Code 20 spi_1.o(.text.SPI_Get) + [Anonymous Symbol] 0x0800723c Section 0 spi_1.o(.text.SPI_Get) + SPI_WaitFlagStateUntilTimeout 0x08007251 Thumb Code 224 stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) + [Anonymous Symbol] 0x08007250 Section 0 stm32f4xx_hal_spi.o(.text.SPI_WaitFlagStateUntilTimeout) + [Anonymous Symbol] 0x08007330 Section 0 port.o(.text.SVC_Handler) + pxCurrentTCBConst2 0x08007350 Number 0 port.o(.text.SVC_Handler) + SVC_Setup 0x08007355 Thumb Code 8 cmsis_os2.o(.text.SVC_Setup) + [Anonymous Symbol] 0x08007354 Section 0 cmsis_os2.o(.text.SVC_Setup) + [Anonymous Symbol] 0x0800735c Section 0 user_math.o(.text.ScaleSumTo1) + Shoot_CaluCoupledWeight 0x08007395 Thumb Code 124 shoot.o(.text.Shoot_CaluCoupledWeight) + [Anonymous Symbol] 0x08007394 Section 0 shoot.o(.text.Shoot_CaluCoupledWeight) + [Anonymous Symbol] 0x08007410 Section 0 shoot.o(.text.Shoot_CaluTargetAngle) + [Anonymous Symbol] 0x080074b0 Section 0 shoot.o(.text.Shoot_CaluTargetRPM) + [Anonymous Symbol] 0x080074dc Section 0 remote_cmd.o(.text.Shoot_Cmd) + [Anonymous Symbol] 0x08007504 Section 0 shoot.o(.text.Shoot_Control) + [Anonymous Symbol] 0x08007570 Section 0 shoot.o(.text.Shoot_Init) + [Anonymous Symbol] 0x080076b8 Section 0 shoot.o(.text.Shoot_JamDetectionFSM) + [Anonymous Symbol] 0x080077e8 Section 0 shoot.o(.text.Shoot_ResetCalu) + [Anonymous Symbol] 0x08007880 Section 0 shoot.o(.text.Shoot_ResetIntegral) + [Anonymous Symbol] 0x080078c8 Section 0 shoot.o(.text.Shoot_ResetOutput) + [Anonymous Symbol] 0x080078fc Section 0 shoot.o(.text.Shoot_RunningFSM) + [Anonymous Symbol] 0x08007dec Section 0 shoot.o(.text.Shoot_SetMode) + [Anonymous Symbol] 0x08007dfc Section 0 shoot.o(.text.Shoot_UpdateFeedback) + [Anonymous Symbol] 0x08007fd0 Section 0 freertos.o(.text.StartDefaultTask) + SysTick_Config 0x08007fdd Thumb Code 46 stm32f4xx_hal_cortex.o(.text.SysTick_Config) + [Anonymous Symbol] 0x08007fdc Section 0 stm32f4xx_hal_cortex.o(.text.SysTick_Config) + [Anonymous Symbol] 0x0800800c Section 0 stm32f4xx_it.o(.text.SysTick_Handler) + [Anonymous Symbol] 0x08008020 Section 0 main.o(.text.SystemClock_Config) + [Anonymous Symbol] 0x080080c4 Section 0 system_stm32f4xx.o(.text.SystemInit) + [Anonymous Symbol] 0x080080d8 Section 0 stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) + [Anonymous Symbol] 0x08008204 Section 0 stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) + TIM_OC1_SetConfig 0x08008229 Thumb Code 100 stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) + [Anonymous Symbol] 0x08008228 Section 0 stm32f4xx_hal_tim.o(.text.TIM_OC1_SetConfig) + [Anonymous Symbol] 0x0800828c Section 0 stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) + TIM_OC3_SetConfig 0x080082f9 Thumb Code 104 stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig) + [Anonymous Symbol] 0x080082f8 Section 0 stm32f4xx_hal_tim.o(.text.TIM_OC3_SetConfig) + TIM_OC4_SetConfig 0x08008361 Thumb Code 78 stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig) + [Anonymous Symbol] 0x08008360 Section 0 stm32f4xx_hal_tim.o(.text.TIM_OC4_SetConfig) + [Anonymous Symbol] 0x080083b0 Section 0 init.o(.text.Task_Init) + [Anonymous Symbol] 0x080084d8 Section 0 ai_1.o(.text.Task_ai) + [Anonymous Symbol] 0x08008578 Section 0 atti_esti.o(.text.Task_atti_esti) + [Anonymous Symbol] 0x080087e0 Section 0 chassis_ctrl.o(.text.Task_chassis_ctrl) + [Anonymous Symbol] 0x08008820 Section 0 dr16_1.o(.text.Task_dr16) + [Anonymous Symbol] 0x080088a0 Section 0 gimbal_ctrl.o(.text.Task_gimbal_ctrl) + [Anonymous Symbol] 0x080089f8 Section 0 remote.o(.text.Task_remote) + [Anonymous Symbol] 0x08008a98 Section 0 shoot_ctrl.o(.text.Task_shoot_ctrl) + UART_DMAAbortOnError 0x08008b35 Thumb Code 14 stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) + [Anonymous Symbol] 0x08008b34 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMAAbortOnError) + UART_DMAError 0x08008b45 Thumb Code 76 stm32f4xx_hal_uart.o(.text.UART_DMAError) + [Anonymous Symbol] 0x08008b44 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMAError) + UART_DMAReceiveCplt 0x08008b91 Thumb Code 132 stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) + [Anonymous Symbol] 0x08008b90 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMAReceiveCplt) + UART_DMARxHalfCplt 0x08008c15 Thumb Code 30 stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) + [Anonymous Symbol] 0x08008c14 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMARxHalfCplt) + UART_DMATransmitCplt 0x08008c35 Thumb Code 64 stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) + [Anonymous Symbol] 0x08008c34 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMATransmitCplt) + UART_DMATxHalfCplt 0x08008c75 Thumb Code 10 stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) + [Anonymous Symbol] 0x08008c74 Section 0 stm32f4xx_hal_uart.o(.text.UART_DMATxHalfCplt) + UART_EndRxTransfer 0x08008c81 Thumb Code 80 stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) + [Anonymous Symbol] 0x08008c80 Section 0 stm32f4xx_hal_uart.o(.text.UART_EndRxTransfer) + UART_EndTransmit_IT 0x08008cd1 Thumb Code 24 stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT) + [Anonymous Symbol] 0x08008cd0 Section 0 stm32f4xx_hal_uart.o(.text.UART_EndTransmit_IT) + UART_EndTxTransfer 0x08008ce9 Thumb Code 28 stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer) + [Anonymous Symbol] 0x08008ce8 Section 0 stm32f4xx_hal_uart.o(.text.UART_EndTxTransfer) + UART_Get 0x08008d05 Thumb Code 52 uart.o(.text.UART_Get) + [Anonymous Symbol] 0x08008d04 Section 0 uart.o(.text.UART_Get) + UART_Receive_IT 0x08008d39 Thumb Code 200 stm32f4xx_hal_uart.o(.text.UART_Receive_IT) + [Anonymous Symbol] 0x08008d38 Section 0 stm32f4xx_hal_uart.o(.text.UART_Receive_IT) + UART_SetConfig 0x08008e01 Thumb Code 220 stm32f4xx_hal_uart.o(.text.UART_SetConfig) + [Anonymous Symbol] 0x08008e00 Section 0 stm32f4xx_hal_uart.o(.text.UART_SetConfig) + [Anonymous Symbol] 0x08008edc Section 0 stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) + [Anonymous Symbol] 0x08008f88 Section 0 stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT) + UART_Transmit_IT 0x08008fbd Thumb Code 82 stm32f4xx_hal_uart.o(.text.UART_Transmit_IT) + [Anonymous Symbol] 0x08008fbc Section 0 stm32f4xx_hal_uart.o(.text.UART_Transmit_IT) + [Anonymous Symbol] 0x08009010 Section 0 stm32f4xx_it.o(.text.USART1_IRQHandler) + [Anonymous Symbol] 0x08009028 Section 0 stm32f4xx_it.o(.text.USART2_IRQHandler) + [Anonymous Symbol] 0x08009038 Section 0 stm32f4xx_it.o(.text.USART6_IRQHandler) + [Anonymous Symbol] 0x08009050 Section 0 stm32f4xx_it.o(.text.UsageFault_Handler) + __ARM_isfinitef 0x08009055 Thumb Code 14 filter.o(.text.__ARM_isfinitef) + [Anonymous Symbol] 0x08009054 Section 0 filter.o(.text.__ARM_isfinitef) + __ARM_isfinitef 0x08009065 Thumb Code 14 pid.o(.text.__ARM_isfinitef) + [Anonymous Symbol] 0x08009064 Section 0 pid.o(.text.__ARM_isfinitef) + __ARM_isinff 0x08009075 Thumb Code 16 filter.o(.text.__ARM_isinff) + [Anonymous Symbol] 0x08009074 Section 0 filter.o(.text.__ARM_isinff) + __NVIC_DisableIRQ 0x08009085 Thumb Code 40 stm32f4xx_hal_cortex.o(.text.__NVIC_DisableIRQ) + [Anonymous Symbol] 0x08009084 Section 0 stm32f4xx_hal_cortex.o(.text.__NVIC_DisableIRQ) + __NVIC_EnableIRQ 0x080090ad Thumb Code 32 stm32f4xx_hal_cortex.o(.text.__NVIC_EnableIRQ) + [Anonymous Symbol] 0x080090ac Section 0 stm32f4xx_hal_cortex.o(.text.__NVIC_EnableIRQ) + __NVIC_GetPriorityGrouping 0x080090cd Thumb Code 16 stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) + [Anonymous Symbol] 0x080090cc Section 0 stm32f4xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) + __NVIC_SetPriority 0x080090dd Thumb Code 34 stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority) + [Anonymous Symbol] 0x080090dc Section 0 stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriority) + __NVIC_SetPriority 0x08009101 Thumb Code 14 cmsis_os2.o(.text.__NVIC_SetPriority) + [Anonymous Symbol] 0x08009100 Section 0 cmsis_os2.o(.text.__NVIC_SetPriority) + __NVIC_SetPriorityGrouping 0x08009111 Thumb Code 32 stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) + [Anonymous Symbol] 0x08009110 Section 0 stm32f4xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) + copysignf 0x08009131 Thumb Code 22 ahrs.o(.text.copysignf) + [Anonymous Symbol] 0x08009130 Section 0 ahrs.o(.text.copysignf) + [Anonymous Symbol] 0x08009148 Section 0 tasks.o(.text.eTaskGetState) + float_to_uint 0x080091e5 Thumb Code 44 motor_dm.o(.text.float_to_uint) + [Anonymous Symbol] 0x080091e4 Section 0 motor_dm.o(.text.float_to_uint) + [Anonymous Symbol] 0x08009210 Section 0 main.o(.text.main) + [Anonymous Symbol] 0x08009254 Section 0 gimbal.o(.text.major_yaw_Control) + motor_imu_offset 0x08009275 Thumb Code 68 gimbal.o(.text.motor_imu_offset) + [Anonymous Symbol] 0x08009274 Section 0 gimbal.o(.text.motor_imu_offset) + [Anonymous Symbol] 0x080092b8 Section 0 cmsis_os2.o(.text.osDelay) + [Anonymous Symbol] 0x080092d8 Section 0 cmsis_os2.o(.text.osDelayUntil) + [Anonymous Symbol] 0x0800930c Section 0 cmsis_os2.o(.text.osKernelGetState) + [Anonymous Symbol] 0x08009334 Section 0 cmsis_os2.o(.text.osKernelGetTickCount) + [Anonymous Symbol] 0x08009348 Section 0 cmsis_os2.o(.text.osKernelGetTickFreq) + [Anonymous Symbol] 0x08009350 Section 0 cmsis_os2.o(.text.osKernelInitialize) + [Anonymous Symbol] 0x08009378 Section 0 cmsis_os2.o(.text.osKernelLock) + [Anonymous Symbol] 0x080093a4 Section 0 cmsis_os2.o(.text.osKernelStart) + [Anonymous Symbol] 0x080093d8 Section 0 cmsis_os2.o(.text.osKernelUnlock) + [Anonymous Symbol] 0x0800941c Section 0 cmsis_os2.o(.text.osMessageQueueGet) + [Anonymous Symbol] 0x080094a4 Section 0 cmsis_os2.o(.text.osMessageQueueNew) + [Anonymous Symbol] 0x08009544 Section 0 cmsis_os2.o(.text.osMessageQueuePut) + [Anonymous Symbol] 0x080095d4 Section 0 cmsis_os2.o(.text.osMessageQueueReset) + [Anonymous Symbol] 0x080095f8 Section 0 cmsis_os2.o(.text.osMutexAcquire) + [Anonymous Symbol] 0x0800964c Section 0 cmsis_os2.o(.text.osMutexNew) + [Anonymous Symbol] 0x080096e4 Section 0 cmsis_os2.o(.text.osMutexRelease) + [Anonymous Symbol] 0x08009724 Section 0 cmsis_os2.o(.text.osThreadFlagsSet) + [Anonymous Symbol] 0x080097a4 Section 0 cmsis_os2.o(.text.osThreadFlagsWait) + [Anonymous Symbol] 0x08009860 Section 0 cmsis_os2.o(.text.osThreadGetId) + [Anonymous Symbol] 0x08009868 Section 0 cmsis_os2.o(.text.osThreadNew) + [Anonymous Symbol] 0x0800991c Section 0 cmsis_os2.o(.text.osThreadTerminate) + prvAddCurrentTaskToDelayedList 0x08009951 Thumb Code 128 tasks.o(.text.prvAddCurrentTaskToDelayedList) + [Anonymous Symbol] 0x08009950 Section 0 tasks.o(.text.prvAddCurrentTaskToDelayedList) + prvAddNewTaskToReadyList 0x080099d1 Thumb Code 172 tasks.o(.text.prvAddNewTaskToReadyList) + [Anonymous Symbol] 0x080099d0 Section 0 tasks.o(.text.prvAddNewTaskToReadyList) + prvCheckForValidListAndQueue 0x08009a7d Thumb Code 116 timers.o(.text.prvCheckForValidListAndQueue) + [Anonymous Symbol] 0x08009a7c Section 0 timers.o(.text.prvCheckForValidListAndQueue) + prvCheckTasksWaitingTermination 0x08009af9 Thumb Code 78 tasks.o(.text.prvCheckTasksWaitingTermination) + [Anonymous Symbol] 0x08009af8 Section 0 tasks.o(.text.prvCheckTasksWaitingTermination) + prvCopyDataFromQueue 0x08009b49 Thumb Code 38 queue.o(.text.prvCopyDataFromQueue) + [Anonymous Symbol] 0x08009b48 Section 0 queue.o(.text.prvCopyDataFromQueue) + prvCopyDataToQueue 0x08009b71 Thumb Code 122 queue.o(.text.prvCopyDataToQueue) + [Anonymous Symbol] 0x08009b70 Section 0 queue.o(.text.prvCopyDataToQueue) + prvDeleteTCB 0x08009bed Thumb Code 54 tasks.o(.text.prvDeleteTCB) + [Anonymous Symbol] 0x08009bec Section 0 tasks.o(.text.prvDeleteTCB) + prvGetDisinheritPriorityAfterTimeout 0x08009c25 Thumb Code 18 queue.o(.text.prvGetDisinheritPriorityAfterTimeout) + [Anonymous Symbol] 0x08009c24 Section 0 queue.o(.text.prvGetDisinheritPriorityAfterTimeout) + prvGetNextExpireTime 0x08009c39 Thumb Code 32 timers.o(.text.prvGetNextExpireTime) + [Anonymous Symbol] 0x08009c38 Section 0 timers.o(.text.prvGetNextExpireTime) + prvHeapInit 0x08009c59 Thumb Code 120 heap_4.o(.text.prvHeapInit) + [Anonymous Symbol] 0x08009c58 Section 0 heap_4.o(.text.prvHeapInit) + prvIdleTask 0x08009cd1 Thumb Code 42 tasks.o(.text.prvIdleTask) + [Anonymous Symbol] 0x08009cd0 Section 0 tasks.o(.text.prvIdleTask) + prvInitialiseMutex 0x08009cfd Thumb Code 32 queue.o(.text.prvInitialiseMutex) + [Anonymous Symbol] 0x08009cfc Section 0 queue.o(.text.prvInitialiseMutex) + prvInitialiseNewQueue 0x08009d1d Thumb Code 32 queue.o(.text.prvInitialiseNewQueue) + [Anonymous Symbol] 0x08009d1c Section 0 queue.o(.text.prvInitialiseNewQueue) + prvInitialiseNewTask 0x08009d3d Thumb Code 152 tasks.o(.text.prvInitialiseNewTask) + [Anonymous Symbol] 0x08009d3c Section 0 tasks.o(.text.prvInitialiseNewTask) + prvInitialiseTaskLists 0x08009dd5 Thumb Code 112 tasks.o(.text.prvInitialiseTaskLists) + [Anonymous Symbol] 0x08009dd4 Section 0 tasks.o(.text.prvInitialiseTaskLists) + prvInsertBlockIntoFreeList 0x08009e45 Thumb Code 90 heap_4.o(.text.prvInsertBlockIntoFreeList) + [Anonymous Symbol] 0x08009e44 Section 0 heap_4.o(.text.prvInsertBlockIntoFreeList) + prvInsertTimerInActiveList 0x08009ea1 Thumb Code 64 timers.o(.text.prvInsertTimerInActiveList) + [Anonymous Symbol] 0x08009ea0 Section 0 timers.o(.text.prvInsertTimerInActiveList) + prvIsQueueEmpty 0x08009ee1 Thumb Code 24 queue.o(.text.prvIsQueueEmpty) + [Anonymous Symbol] 0x08009ee0 Section 0 queue.o(.text.prvIsQueueEmpty) + prvIsQueueFull 0x08009ef9 Thumb Code 28 queue.o(.text.prvIsQueueFull) + [Anonymous Symbol] 0x08009ef8 Section 0 queue.o(.text.prvIsQueueFull) + prvPortStartFirstTask 0x08009f15 Thumb Code 34 port.o(.text.prvPortStartFirstTask) + [Anonymous Symbol] 0x08009f14 Section 0 port.o(.text.prvPortStartFirstTask) + prvProcessExpiredTimer 0x08009f3d Thumb Code 110 timers.o(.text.prvProcessExpiredTimer) + [Anonymous Symbol] 0x08009f3c Section 0 timers.o(.text.prvProcessExpiredTimer) + prvProcessReceivedCommands 0x08009fad Thumb Code 290 timers.o(.text.prvProcessReceivedCommands) + [Anonymous Symbol] 0x08009fac Section 0 timers.o(.text.prvProcessReceivedCommands) + prvProcessTimerOrBlockTask 0x0800a0d1 Thumb Code 128 timers.o(.text.prvProcessTimerOrBlockTask) + [Anonymous Symbol] 0x0800a0d0 Section 0 timers.o(.text.prvProcessTimerOrBlockTask) + prvResetNextTaskUnblockTime 0x0800a151 Thumb Code 40 tasks.o(.text.prvResetNextTaskUnblockTime) + [Anonymous Symbol] 0x0800a150 Section 0 tasks.o(.text.prvResetNextTaskUnblockTime) + prvSampleTimeNow 0x0800a179 Thumb Code 42 timers.o(.text.prvSampleTimeNow) + [Anonymous Symbol] 0x0800a178 Section 0 timers.o(.text.prvSampleTimeNow) + prvSwitchTimerLists 0x0800a1a5 Thumb Code 142 timers.o(.text.prvSwitchTimerLists) + [Anonymous Symbol] 0x0800a1a4 Section 0 timers.o(.text.prvSwitchTimerLists) + prvTaskExitError 0x0800a235 Thumb Code 50 port.o(.text.prvTaskExitError) + [Anonymous Symbol] 0x0800a234 Section 0 port.o(.text.prvTaskExitError) + prvTimerTask 0x0800a269 Thumb Code 22 timers.o(.text.prvTimerTask) + [Anonymous Symbol] 0x0800a268 Section 0 timers.o(.text.prvTimerTask) + prvUnlockQueue 0x0800a281 Thumb Code 114 queue.o(.text.prvUnlockQueue) + [Anonymous Symbol] 0x0800a280 Section 0 queue.o(.text.prvUnlockQueue) + [Anonymous Symbol] 0x0800a2f4 Section 0 heap_4.o(.text.pvPortMalloc) + [Anonymous Symbol] 0x0800a440 Section 0 tasks.o(.text.pvTaskIncrementMutexHeldCount) + [Anonymous Symbol] 0x0800a458 Section 0 port.o(.text.pxPortInitialiseStack) + uint_to_float 0x0800a481 Thumb Code 42 motor_dm.o(.text.uint_to_float) + [Anonymous Symbol] 0x0800a480 Section 0 motor_dm.o(.text.uint_to_float) + [Anonymous Symbol] 0x0800a4ac Section 0 list.o(.text.uxListRemove) + [Anonymous Symbol] 0x0800a4d0 Section 0 cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) + [Anonymous Symbol] 0x0800a4ec Section 0 cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) + [Anonymous Symbol] 0x0800a508 Section 0 list.o(.text.vListInitialise) + [Anonymous Symbol] 0x0800a520 Section 0 list.o(.text.vListInitialiseItem) + [Anonymous Symbol] 0x0800a528 Section 0 list.o(.text.vListInsert) + [Anonymous Symbol] 0x0800a564 Section 0 list.o(.text.vListInsertEnd) + vPortEnableVFP 0x0800a581 Thumb Code 14 port.o(.text.vPortEnableVFP) + [Anonymous Symbol] 0x0800a580 Section 0 port.o(.text.vPortEnableVFP) + [Anonymous Symbol] 0x0800a594 Section 0 port.o(.text.vPortEnterCritical) + [Anonymous Symbol] 0x0800a5dc Section 0 port.o(.text.vPortExitCritical) + [Anonymous Symbol] 0x0800a60c Section 0 heap_4.o(.text.vPortFree) + [Anonymous Symbol] 0x0800a698 Section 0 port.o(.text.vPortSetupTimerInterrupt) + [Anonymous Symbol] 0x0800a6cc Section 0 port.o(.text.vPortValidateInterruptPriority) + [Anonymous Symbol] 0x0800a730 Section 0 queue.o(.text.vQueueAddToRegistry) + [Anonymous Symbol] 0x0800a758 Section 0 queue.o(.text.vQueueWaitForMessageRestricted) + [Anonymous Symbol] 0x0800a79c Section 0 tasks.o(.text.vTaskDelay) + [Anonymous Symbol] 0x0800a7f0 Section 0 tasks.o(.text.vTaskDelayUntil) + [Anonymous Symbol] 0x0800a898 Section 0 tasks.o(.text.vTaskDelete) + [Anonymous Symbol] 0x0800a95c Section 0 tasks.o(.text.vTaskInternalSetTimeOutState) + [Anonymous Symbol] 0x0800a978 Section 0 tasks.o(.text.vTaskMissedYield) + [Anonymous Symbol] 0x0800a988 Section 0 tasks.o(.text.vTaskPlaceOnEventList) + [Anonymous Symbol] 0x0800a9bc Section 0 tasks.o(.text.vTaskPlaceOnEventListRestricted) + [Anonymous Symbol] 0x0800a9fc Section 0 tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) + [Anonymous Symbol] 0x0800aaa0 Section 0 tasks.o(.text.vTaskStartScheduler) + [Anonymous Symbol] 0x0800ab44 Section 0 tasks.o(.text.vTaskSuspendAll) + [Anonymous Symbol] 0x0800ab54 Section 0 tasks.o(.text.vTaskSwitchContext) + [Anonymous Symbol] 0x0800abf0 Section 0 port.o(.text.xPortStartScheduler) + [Anonymous Symbol] 0x0800ad04 Section 0 port.o(.text.xPortSysTickHandler) + [Anonymous Symbol] 0x0800ad34 Section 0 queue.o(.text.xQueueCreateMutex) + [Anonymous Symbol] 0x0800ad4c Section 0 queue.o(.text.xQueueCreateMutexStatic) + [Anonymous Symbol] 0x0800ad70 Section 0 queue.o(.text.xQueueGenericCreate) + [Anonymous Symbol] 0x0800adb8 Section 0 queue.o(.text.xQueueGenericCreateStatic) + [Anonymous Symbol] 0x0800ae50 Section 0 queue.o(.text.xQueueGenericReset) + [Anonymous Symbol] 0x0800aed0 Section 0 queue.o(.text.xQueueGenericSend) + [Anonymous Symbol] 0x0800b074 Section 0 queue.o(.text.xQueueGenericSendFromISR) + [Anonymous Symbol] 0x0800b144 Section 0 queue.o(.text.xQueueGiveMutexRecursive) + [Anonymous Symbol] 0x0800b188 Section 0 queue.o(.text.xQueueReceive) + [Anonymous Symbol] 0x0800b30c Section 0 queue.o(.text.xQueueReceiveFromISR) + [Anonymous Symbol] 0x0800b3b8 Section 0 queue.o(.text.xQueueSemaphoreTake) + [Anonymous Symbol] 0x0800b580 Section 0 queue.o(.text.xQueueTakeMutexRecursive) + [Anonymous Symbol] 0x0800b5bc Section 0 tasks.o(.text.xTaskCheckForTimeOut) + [Anonymous Symbol] 0x0800b644 Section 0 tasks.o(.text.xTaskCreate) + [Anonymous Symbol] 0x0800b6ac Section 0 tasks.o(.text.xTaskCreateStatic) + [Anonymous Symbol] 0x0800b724 Section 0 tasks.o(.text.xTaskGenericNotify) + [Anonymous Symbol] 0x0800b820 Section 0 tasks.o(.text.xTaskGenericNotifyFromISR) + [Anonymous Symbol] 0x0800b94c Section 0 tasks.o(.text.xTaskGetCurrentTaskHandle) + [Anonymous Symbol] 0x0800b958 Section 0 tasks.o(.text.xTaskGetSchedulerState) + [Anonymous Symbol] 0x0800b980 Section 0 tasks.o(.text.xTaskGetTickCount) + [Anonymous Symbol] 0x0800b98c Section 0 tasks.o(.text.xTaskGetTickCountFromISR) + [Anonymous Symbol] 0x0800b9a0 Section 0 tasks.o(.text.xTaskIncrementTick) + [Anonymous Symbol] 0x0800baf4 Section 0 tasks.o(.text.xTaskNotifyWait) + [Anonymous Symbol] 0x0800bb84 Section 0 tasks.o(.text.xTaskPriorityDisinherit) + [Anonymous Symbol] 0x0800bc18 Section 0 tasks.o(.text.xTaskPriorityInherit) + [Anonymous Symbol] 0x0800bcac Section 0 tasks.o(.text.xTaskRemoveFromEventList) + [Anonymous Symbol] 0x0800bd3c Section 0 tasks.o(.text.xTaskResumeAll) + [Anonymous Symbol] 0x0800be50 Section 0 timers.o(.text.xTimerCreateTimerTask) + [Anonymous Symbol] 0x0800bec4 Section 0 timers.o(.text.xTimerGenericCommand) + i.__ARM_fpclassify 0x0800bf2c Section 0 fpclassify.o(i.__ARM_fpclassify) + i.__ARM_fpclassifyf 0x0800bf5c Section 0 fpclassifyf.o(i.__ARM_fpclassifyf) + i.__hardfp_asinf 0x0800bf84 Section 0 asinf.o(i.__hardfp_asinf) + i.__hardfp_atan 0x0800c0b0 Section 0 atan.o(i.__hardfp_atan) + i.__hardfp_atan2 0x0800c388 Section 0 atan2.o(i.__hardfp_atan2) + i.__hardfp_atan2f 0x0800c588 Section 0 atan2f.o(i.__hardfp_atan2f) + i.__hardfp_tanf 0x0800c834 Section 0 tanf.o(i.__hardfp_tanf) + i.__kernel_poly 0x0800c9b0 Section 0 poly.o(i.__kernel_poly) + i.__mathlib_dbl_infnan 0x0800caa8 Section 0 dunder.o(i.__mathlib_dbl_infnan) + i.__mathlib_dbl_infnan2 0x0800cabc Section 0 dunder.o(i.__mathlib_dbl_infnan2) + i.__mathlib_dbl_underflow 0x0800cad0 Section 0 dunder.o(i.__mathlib_dbl_underflow) + i.__mathlib_flt_infnan 0x0800caf0 Section 0 funder.o(i.__mathlib_flt_infnan) + i.__mathlib_flt_infnan2 0x0800caf6 Section 0 funder.o(i.__mathlib_flt_infnan2) + i.__mathlib_flt_invalid 0x0800cafc Section 0 funder.o(i.__mathlib_flt_invalid) + i.__mathlib_flt_underflow 0x0800cb0c Section 0 funder.o(i.__mathlib_flt_underflow) + i.__mathlib_rredf2 0x0800cb1c Section 0 rredf.o(i.__mathlib_rredf2) + i.atan 0x0800cc70 Section 0 atan.o(i.atan) + i.fabs 0x0800cc80 Section 0 fabs.o(i.fabs) + i.sqrtf 0x0800cc98 Section 0 sqrtf.o(i.sqrtf) + $v0 0x0800ccd6 Number 0 basic.o(x$fpl$basic) + x$fpl$basic 0x0800ccd6 Section 24 basic.o(x$fpl$basic) + $v0 0x0800ccf0 Number 0 d2f.o(x$fpl$d2f) + x$fpl$d2f 0x0800ccf0 Section 98 d2f.o(x$fpl$d2f) + $v0 0x0800cd54 Number 0 daddsub_clz.o(x$fpl$dadd) + x$fpl$dadd 0x0800cd54 Section 336 daddsub_clz.o(x$fpl$dadd) + _dadd1 0x0800cd65 Thumb Code 0 daddsub_clz.o(x$fpl$dadd) + $v0 0x0800cea4 Number 0 dcmpi.o(x$fpl$dcmpinf) + x$fpl$dcmpinf 0x0800cea4 Section 24 dcmpi.o(x$fpl$dcmpinf) + $v0 0x0800cebc Number 0 ddiv.o(x$fpl$ddiv) + x$fpl$ddiv 0x0800cebc Section 692 ddiv.o(x$fpl$ddiv) + ddiv_entry 0x0800cec3 Thumb Code 0 ddiv.o(x$fpl$ddiv) + $v0 0x0800d170 Number 0 deqf.o(x$fpl$deqf) + x$fpl$deqf 0x0800d170 Section 120 deqf.o(x$fpl$deqf) + $v0 0x0800d1e8 Number 0 dfixu.o(x$fpl$dfixu) + x$fpl$dfixu 0x0800d1e8 Section 90 dfixu.o(x$fpl$dfixu) + $v0 0x0800d242 Number 0 dflt_clz.o(x$fpl$dflt) + x$fpl$dflt 0x0800d242 Section 46 dflt_clz.o(x$fpl$dflt) + $v0 0x0800d270 Number 0 dflt_clz.o(x$fpl$dfltu) + x$fpl$dfltu 0x0800d270 Section 38 dflt_clz.o(x$fpl$dfltu) + $v0 0x0800d298 Number 0 dmul.o(x$fpl$dmul) + x$fpl$dmul 0x0800d298 Section 340 dmul.o(x$fpl$dmul) + $v0 0x0800d3ec Number 0 dnaninf.o(x$fpl$dnaninf) + x$fpl$dnaninf 0x0800d3ec Section 156 dnaninf.o(x$fpl$dnaninf) + $v0 0x0800d488 Number 0 dretinf.o(x$fpl$dretinf) + x$fpl$dretinf 0x0800d488 Section 12 dretinf.o(x$fpl$dretinf) + $v0 0x0800d494 Number 0 daddsub_clz.o(x$fpl$drsb) + x$fpl$drsb 0x0800d494 Section 22 daddsub_clz.o(x$fpl$drsb) + $v0 0x0800d4ac Number 0 daddsub_clz.o(x$fpl$dsub) + x$fpl$dsub 0x0800d4ac Section 476 daddsub_clz.o(x$fpl$dsub) + _dsub1 0x0800d4bd Thumb Code 0 daddsub_clz.o(x$fpl$dsub) + $v0 0x0800d688 Number 0 f2d.o(x$fpl$f2d) + x$fpl$f2d 0x0800d688 Section 86 f2d.o(x$fpl$f2d) + $v0 0x0800d6de Number 0 ffltll_clz.o(x$fpl$ffltll) + x$fpl$ffltll 0x0800d6de Section 96 ffltll_clz.o(x$fpl$ffltll) + $v0 0x0800d73e Number 0 fnaninf.o(x$fpl$fnaninf) + x$fpl$fnaninf 0x0800d73e Section 140 fnaninf.o(x$fpl$fnaninf) + $v0 0x0800d7ca Number 0 fpinit.o(x$fpl$fpinit) + x$fpl$fpinit 0x0800d7ca Section 26 fpinit.o(x$fpl$fpinit) + $v0 0x0800d7e4 Number 0 fretinf.o(x$fpl$fretinf) + x$fpl$fretinf 0x0800d7e4 Section 10 fretinf.o(x$fpl$fretinf) + x$fpl$usenofp 0x0800d7ee Section 0 usenofp.o(x$fpl$usenofp) + atanhi 0x0800d7f0 Data 32 atan.o(.constdata) + .constdata 0x0800d7f0 Section 152 atan.o(.constdata) + atanlo 0x0800d810 Data 32 atan.o(.constdata) + aTodd 0x0800d830 Data 40 atan.o(.constdata) + aTeven 0x0800d858 Data 48 atan.o(.constdata) + .constdata 0x0800d888 Section 8 qnan.o(.constdata) + twooverpi 0x0800d890 Data 32 rredf.o(.constdata) + .constdata 0x0800d890 Section 32 rredf.o(.constdata) + GPIO_Map 0x0800d8c8 Data 56 gpio_1.o(.rodata.GPIO_Map) + [Anonymous Symbol] 0x0800d8c8 Section 0 gpio_1.o(.rodata.GPIO_Map) + crc16_tab 0x0800da20 Data 512 crc16.o(.rodata.crc16_tab) + [Anonymous Symbol] 0x0800da20 Section 0 crc16.o(.rodata.crc16_tab) + imu_temp_ctrl_pid_param 0x0800dc44 Data 32 atti_esti.o(.rodata.imu_temp_ctrl_pid_param) + [Anonymous Symbol] 0x0800dc44 Section 0 atti_esti.o(.rodata.imu_temp_ctrl_pid_param) + [Anonymous Symbol] 0x0800dc64 Section 0 freertos.o(.rodata.str1.1) + [Anonymous Symbol] 0x0800dc70 Section 0 user_task.o(.rodata.str1.1) + beta 0x20000004 Data 4 ahrs.o(.data.beta) + [Anonymous Symbol] 0x20000004 Section 0 ahrs.o(.data.beta) + uxCriticalNesting 0x20000338 Data 4 port.o(.data.uxCriticalNesting) + [Anonymous Symbol] 0x20000338 Section 0 port.o(.data.uxCriticalNesting) + .bss 0x20000340 Section 96 libspace.o(.bss) + CAN_Callback 0x200003a0 Data 104 can_1.o(.bss.CAN_Callback) + [Anonymous Symbol] 0x200003a0 Section 0 can_1.o(.bss.CAN_Callback) + SPI_Callback 0x20000408 Data 32 spi_1.o(.bss.SPI_Callback) + [Anonymous Symbol] 0x20000408 Section 0 spi_1.o(.bss.SPI_Callback) + buffer 0x20000441 Data 2 bmi088.o(.bss.buffer) + [Anonymous Symbol] 0x20000441 Section 0 bmi088.o(.bss.buffer) + calib_count 0x20000444 Data 2 atti_esti.o(.bss.calib_count) + [Anonymous Symbol] 0x20000444 Section 0 atti_esti.o(.bss.calib_count) + can_managers 0x20000448 Data 8 motor_rm.o(.bss.can_managers) + [Anonymous Symbol] 0x20000448 Section 0 motor_rm.o(.bss.can_managers) + gyro_sum.0 0x2000057c Data 4 atti_esti.o(.bss.gyro_sum.0) + [Anonymous Symbol] 0x2000057c Section 0 atti_esti.o(.bss.gyro_sum.0) + gyro_sum.2 0x20000580 Data 4 atti_esti.o(.bss.gyro_sum.2) + [Anonymous Symbol] 0x20000580 Section 0 atti_esti.o(.bss.gyro_sum.2) + inited 0x20000774 Data 1 bmi088.o(.bss.inited) + [Anonymous Symbol] 0x20000774 Section 0 bmi088.o(.bss.inited) + last_firecmd 0x20000775 Data 1 shoot.o(.bss.last_firecmd) + [Anonymous Symbol] 0x20000775 Section 0 shoot.o(.bss.last_firecmd) + prvCheckForValidListAndQueue.ucStaticTimerQueueStorage 0x20000776 Data 160 timers.o(.bss.prvCheckForValidListAndQueue.ucStaticTimerQueueStorage) + [Anonymous Symbol] 0x20000776 Section 0 timers.o(.bss.prvCheckForValidListAndQueue.ucStaticTimerQueueStorage) + prvSampleTimeNow.xLastTime 0x20000818 Data 4 timers.o(.bss.prvSampleTimeNow.xLastTime) + [Anonymous Symbol] 0x20000818 Section 0 timers.o(.bss.prvSampleTimeNow.xLastTime) + pxCurrentTimerList 0x2000081c Data 4 timers.o(.bss.pxCurrentTimerList) + [Anonymous Symbol] 0x2000081c Section 0 timers.o(.bss.pxCurrentTimerList) + pxDelayedTaskList 0x20000820 Data 4 tasks.o(.bss.pxDelayedTaskList) + [Anonymous Symbol] 0x20000820 Section 0 tasks.o(.bss.pxDelayedTaskList) + pxEnd 0x20000824 Data 4 heap_4.o(.bss.pxEnd) + [Anonymous Symbol] 0x20000824 Section 0 heap_4.o(.bss.pxEnd) + queue_mutex 0x20000828 Data 4 can_1.o(.bss.queue_mutex) + [Anonymous Symbol] 0x20000828 Section 0 can_1.o(.bss.queue_mutex) + thread_alert 0x20000830 Data 4 dr16.o(.bss.thread_alert) + [Anonymous Symbol] 0x20000830 Section 0 dr16.o(.bss.thread_alert) + ucHeap 0x20000834 Data 104857 heap_4.o(.bss.ucHeap) + [Anonymous Symbol] 0x20000834 Section 0 heap_4.o(.bss.ucHeap) + ucMaxSysCallPriority 0x2001a1cd Data 1 port.o(.bss.ucMaxSysCallPriority) + [Anonymous Symbol] 0x2001a1cd Section 0 port.o(.bss.ucMaxSysCallPriority) + uxCurrentNumberOfTasks 0x2001a1d0 Data 4 tasks.o(.bss.uxCurrentNumberOfTasks) + [Anonymous Symbol] 0x2001a1d0 Section 0 tasks.o(.bss.uxCurrentNumberOfTasks) + uxSchedulerSuspended 0x2001a1d4 Data 4 tasks.o(.bss.uxSchedulerSuspended) + [Anonymous Symbol] 0x2001a1d4 Section 0 tasks.o(.bss.uxSchedulerSuspended) + uxTaskNumber 0x2001a1d8 Data 4 tasks.o(.bss.uxTaskNumber) + [Anonymous Symbol] 0x2001a1d8 Section 0 tasks.o(.bss.uxTaskNumber) + uxTopReadyPriority 0x2001a1dc Data 4 tasks.o(.bss.uxTopReadyPriority) + [Anonymous Symbol] 0x2001a1dc Section 0 tasks.o(.bss.uxTopReadyPriority) + vApplicationGetIdleTaskMemory.Idle_Stack 0x2001a1e0 Data 512 cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_Stack) + [Anonymous Symbol] 0x2001a1e0 Section 0 cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_Stack) + vApplicationGetTimerTaskMemory.Timer_Stack 0x2001a3e0 Data 1024 cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_Stack) + [Anonymous Symbol] 0x2001a3e0 Section 0 cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_Stack) + vApplicationGetTimerTaskMemory.Timer_TCB 0x2001a7e0 Data 92 cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_TCB) + [Anonymous Symbol] 0x2001a7e0 Section 0 cmsis_os2.o(.bss.vApplicationGetTimerTaskMemory.Timer_TCB) + xActiveTimerList2 0x2001a83c Data 20 timers.o(.bss.xActiveTimerList2) + [Anonymous Symbol] 0x2001a83c Section 0 timers.o(.bss.xActiveTimerList2) + xDelayedTaskList2 0x2001a850 Data 20 tasks.o(.bss.xDelayedTaskList2) + [Anonymous Symbol] 0x2001a850 Section 0 tasks.o(.bss.xDelayedTaskList2) + xMinimumEverFreeBytesRemaining 0x2001a864 Data 4 heap_4.o(.bss.xMinimumEverFreeBytesRemaining) + [Anonymous Symbol] 0x2001a864 Section 0 heap_4.o(.bss.xMinimumEverFreeBytesRemaining) + xNextTaskUnblockTime 0x2001a868 Data 4 tasks.o(.bss.xNextTaskUnblockTime) + [Anonymous Symbol] 0x2001a868 Section 0 tasks.o(.bss.xNextTaskUnblockTime) + xNumberOfSuccessfulFrees 0x2001a86c Data 4 heap_4.o(.bss.xNumberOfSuccessfulFrees) + [Anonymous Symbol] 0x2001a86c Section 0 heap_4.o(.bss.xNumberOfSuccessfulFrees) + xPendedTicks 0x2001a870 Data 4 tasks.o(.bss.xPendedTicks) + [Anonymous Symbol] 0x2001a870 Section 0 tasks.o(.bss.xPendedTicks) + xPendingReadyList 0x2001a874 Data 20 tasks.o(.bss.xPendingReadyList) + [Anonymous Symbol] 0x2001a874 Section 0 tasks.o(.bss.xPendingReadyList) + xTasksWaitingTermination 0x2001a8c8 Data 20 tasks.o(.bss.xTasksWaitingTermination) + [Anonymous Symbol] 0x2001a8c8 Section 0 tasks.o(.bss.xTasksWaitingTermination) + xTimerQueue 0x2001a8dc Data 4 timers.o(.bss.xTimerQueue) + [Anonymous Symbol] 0x2001a8dc Section 0 timers.o(.bss.xTimerQueue) + Heap_Mem 0x2001a8e0 Data 4096 startup_stm32f407xx.o(HEAP) + HEAP 0x2001a8e0 Section 4096 startup_stm32f407xx.o(HEAP) + GPIO_Callback 0x2001c008 Data 64 gpio_1.o(.bss.GPIO_Callback) + [Anonymous Symbol] 0x2001c008 Section 0 gpio_1.o(.bss.GPIO_Callback) + HAL_RCC_CAN1_CLK_ENABLED 0x2001c048 Data 4 can.o(.bss.HAL_RCC_CAN1_CLK_ENABLED) + [Anonymous Symbol] 0x2001c048 Section 0 can.o(.bss.HAL_RCC_CAN1_CLK_ENABLED) + KernelState 0x2001c04c Data 4 cmsis_os2.o(.bss.KernelState) + [Anonymous Symbol] 0x2001c04c Section 0 cmsis_os2.o(.bss.KernelState) + Shoot_RunningFSM.pos 0x2001c050 Data 4 shoot.o(.bss.Shoot_RunningFSM.pos) + [Anonymous Symbol] 0x2001c050 Section 0 shoot.o(.bss.Shoot_RunningFSM.pos) + UART_Callback 0x2001c054 Data 144 uart.o(.bss.UART_Callback) + [Anonymous Symbol] 0x2001c054 Section 0 uart.o(.bss.UART_Callback) + bmi088_rxbuf 0x2001c178 Data 19 bmi088.o(.bss.bmi088_rxbuf) + [Anonymous Symbol] 0x2001c178 Section 0 bmi088.o(.bss.bmi088_rxbuf) + can_managers 0x2001c18c Data 8 motor_dm.o(.bss.can_managers) + [Anonymous Symbol] 0x2001c18c Section 0 motor_dm.o(.bss.can_managers) + gyro_sum.1 0x2001c504 Data 4 atti_esti.o(.bss.gyro_sum.1) + [Anonymous Symbol] 0x2001c504 Section 0 atti_esti.o(.bss.gyro_sum.1) + id_parser 0x2001c6d8 Data 4 can_1.o(.bss.id_parser) + [Anonymous Symbol] 0x2001c6d8 Section 0 can_1.o(.bss.id_parser) + inited 0x2001c6dc Data 1 can_1.o(.bss.inited) + [Anonymous Symbol] 0x2001c6dc Section 0 can_1.o(.bss.inited) + inited 0x2001c6dd Data 1 dr16.o(.bss.inited) + [Anonymous Symbol] 0x2001c6dd Section 0 dr16.o(.bss.inited) + prvCheckForValidListAndQueue.xStaticTimerQueue 0x2001c710 Data 80 timers.o(.bss.prvCheckForValidListAndQueue.xStaticTimerQueue) + [Anonymous Symbol] 0x2001c710 Section 0 timers.o(.bss.prvCheckForValidListAndQueue.xStaticTimerQueue) + pxOverflowDelayedTaskList 0x2001c764 Data 4 tasks.o(.bss.pxOverflowDelayedTaskList) + [Anonymous Symbol] 0x2001c764 Section 0 tasks.o(.bss.pxOverflowDelayedTaskList) + pxOverflowTimerList 0x2001c768 Data 4 timers.o(.bss.pxOverflowTimerList) + [Anonymous Symbol] 0x2001c768 Section 0 timers.o(.bss.pxOverflowTimerList) + pxReadyTasksLists 0x2001c76c Data 1120 tasks.o(.bss.pxReadyTasksLists) + [Anonymous Symbol] 0x2001c76c Section 0 tasks.o(.bss.pxReadyTasksLists) + queue_list 0x2001cbcc Data 4 can_1.o(.bss.queue_list) + [Anonymous Symbol] 0x2001cbcc Section 0 can_1.o(.bss.queue_list) + thread_alert 0x2001d004 Data 4 bmi088.o(.bss.thread_alert) + [Anonymous Symbol] 0x2001d004 Section 0 bmi088.o(.bss.thread_alert) + tx_queues 0x2001d008 Data 2064 can_1.o(.bss.tx_queues) + [Anonymous Symbol] 0x2001d008 Section 0 can_1.o(.bss.tx_queues) + ulMaxPRIGROUPValue 0x2001d818 Data 4 port.o(.bss.ulMaxPRIGROUPValue) + [Anonymous Symbol] 0x2001d818 Section 0 port.o(.bss.ulMaxPRIGROUPValue) + uxDeletedTasksWaitingCleanUp 0x2001d820 Data 4 tasks.o(.bss.uxDeletedTasksWaitingCleanUp) + [Anonymous Symbol] 0x2001d820 Section 0 tasks.o(.bss.uxDeletedTasksWaitingCleanUp) + vApplicationGetIdleTaskMemory.Idle_TCB 0x2001d824 Data 92 cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_TCB) + [Anonymous Symbol] 0x2001d824 Section 0 cmsis_os2.o(.bss.vApplicationGetIdleTaskMemory.Idle_TCB) + xActiveTimerList1 0x2001d880 Data 20 timers.o(.bss.xActiveTimerList1) + [Anonymous Symbol] 0x2001d880 Section 0 timers.o(.bss.xActiveTimerList1) + xBlockAllocatedBit 0x2001d894 Data 1 heap_4.o(.bss.xBlockAllocatedBit) + [Anonymous Symbol] 0x2001d894 Section 0 heap_4.o(.bss.xBlockAllocatedBit) + xDelayedTaskList1 0x2001d898 Data 20 tasks.o(.bss.xDelayedTaskList1) + [Anonymous Symbol] 0x2001d898 Section 0 tasks.o(.bss.xDelayedTaskList1) + xFreeBytesRemaining 0x2001d8ac Data 4 heap_4.o(.bss.xFreeBytesRemaining) + [Anonymous Symbol] 0x2001d8ac Section 0 heap_4.o(.bss.xFreeBytesRemaining) + xIdleTaskHandle 0x2001d8b0 Data 4 tasks.o(.bss.xIdleTaskHandle) + [Anonymous Symbol] 0x2001d8b0 Section 0 tasks.o(.bss.xIdleTaskHandle) + xNumOfOverflows 0x2001d8b4 Data 4 tasks.o(.bss.xNumOfOverflows) + [Anonymous Symbol] 0x2001d8b4 Section 0 tasks.o(.bss.xNumOfOverflows) + xNumberOfSuccessfulAllocations 0x2001d8b8 Data 4 heap_4.o(.bss.xNumberOfSuccessfulAllocations) + [Anonymous Symbol] 0x2001d8b8 Section 0 heap_4.o(.bss.xNumberOfSuccessfulAllocations) + xSchedulerRunning 0x2001d8bc Data 4 tasks.o(.bss.xSchedulerRunning) + [Anonymous Symbol] 0x2001d8bc Section 0 tasks.o(.bss.xSchedulerRunning) + xStart 0x2001d8c0 Data 8 heap_4.o(.bss.xStart) + [Anonymous Symbol] 0x2001d8c0 Section 0 heap_4.o(.bss.xStart) + xSuspendedTaskList 0x2001d8c8 Data 20 tasks.o(.bss.xSuspendedTaskList) + [Anonymous Symbol] 0x2001d8c8 Section 0 tasks.o(.bss.xSuspendedTaskList) + xTickCount 0x2001d8dc Data 4 tasks.o(.bss.xTickCount) + [Anonymous Symbol] 0x2001d8dc Section 0 tasks.o(.bss.xTickCount) + xTimerTaskHandle 0x2001d8e0 Data 4 timers.o(.bss.xTimerTaskHandle) + [Anonymous Symbol] 0x2001d8e0 Section 0 timers.o(.bss.xTimerTaskHandle) + xYieldPending 0x2001d8e4 Data 4 tasks.o(.bss.xYieldPending) + [Anonymous Symbol] 0x2001d8e4 Section 0 tasks.o(.bss.xYieldPending) + Stack_Mem 0x2001d8e8 Data 8192 startup_stm32f407xx.o(STACK) + STACK 0x2001d8e8 Section 8192 startup_stm32f407xx.o(STACK) + __initial_sp 0x2001f8e8 Data 0 startup_stm32f407xx.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$E$P$D$K$B$S$7EM$VFPi3$EXTD16$VFPS$VFMA$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEX$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _printf_mbtowc - Undefined Weak Reference + _printf_post_padding - Undefined Weak Reference + _printf_pre_padding - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x00000188 Number 0 startup_stm32f407xx.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f407xx.o(RESET) + __Vectors_End 0x08000188 Data 0 startup_stm32f407xx.o(RESET) + __main 0x08000189 Thumb Code 8 __main.o(!!!main) + __scatterload 0x08000191 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x08000191 Thumb Code 44 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x08000191 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x0800019f Thumb Code 0 __scatter.o(!!!scatter) + __decompress 0x080001c5 Thumb Code 90 __dczerorl2.o(!!dczerorl2) + __decompress1 0x080001c5 Thumb Code 0 __dczerorl2.o(!!dczerorl2) + __scatterload_copy 0x08000221 Thumb Code 26 __scatter_copy.o(!!handler_copy) + __scatterload_zeroinit 0x0800023d Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x08000259 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_fp_1 0x0800025b Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000001) + __rt_lib_init_alloca_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_argv_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_atexit_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_clock_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_cpp_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_exceptions_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_fp_trap_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_getenv_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_heap_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_init_lc_collate_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_ctype_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_monetary_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_numeric_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_time_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_preinit_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_rand_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_init_return 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033) + __rt_lib_init_signal_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_stdio_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_init_user_alloc_1 0x0800025f Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_shutdown 0x08000261 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x08000263 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x08000265 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x08000265 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x08000265 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x0800026b Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x0800026b Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x0800026f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x0800026f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x08000277 Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x08000279 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x08000279 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x0800027d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x08000285 Thumb Code 8 startup_stm32f407xx.o(.text) + ADC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + CAN2_RX0_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DCMI_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream0_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream2_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream3_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream4_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream5_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream6_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA1_Stream7_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream0_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream1_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream4_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream5_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream6_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + DMA2_Stream7_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + ETH_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + ETH_WKUP_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + EXTI15_10_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + EXTI1_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + EXTI2_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + FLASH_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + FMC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + FPU_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + HASH_RNG_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C1_ER_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C1_EV_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C2_ER_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C2_EV_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C3_ER_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + I2C3_EV_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_FS_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_FS_WKUP_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_HS_EP1_IN_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_HS_EP1_OUT_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_HS_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + OTG_HS_WKUP_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + PVD_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + RCC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + RTC_Alarm_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + RTC_WKUP_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + SDIO_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + SPI1_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + SPI2_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + SPI3_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TAMP_STAMP_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM1_BRK_TIM9_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM1_CC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM1_TRG_COM_TIM11_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM1_UP_TIM10_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM2_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM3_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM4_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM5_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM6_DAC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM7_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM8_BRK_TIM12_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM8_CC_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM8_TRG_COM_TIM14_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + TIM8_UP_TIM13_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + UART4_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + UART5_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + USART3_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + WWDG_IRQHandler 0x0800029f Thumb Code 0 startup_stm32f407xx.o(.text) + __user_initial_stackheap 0x080002a1 Thumb Code 0 startup_stm32f407xx.o(.text) + __aeabi_uldivmod 0x080002c5 Thumb Code 0 lludivv7m.o(.text) + _ll_udiv 0x080002c5 Thumb Code 240 lludivv7m.o(.text) + __aeabi_memcpy 0x080003b5 Thumb Code 0 rt_memcpy_v6.o(.text) + __rt_memcpy 0x080003b5 Thumb Code 138 rt_memcpy_v6.o(.text) + _memcpy_lastbytes 0x0800041b Thumb Code 0 rt_memcpy_v6.o(.text) + __aeabi_memcpy4 0x0800043f Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_memcpy8 0x0800043f Thumb Code 0 rt_memcpy_w.o(.text) + __rt_memcpy_w 0x0800043f Thumb Code 100 rt_memcpy_w.o(.text) + _memcpy_lastbytes_aligned 0x08000487 Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_memset4 0x080004a3 Thumb Code 16 aeabi_memset4.o(.text) + __aeabi_memset8 0x080004a3 Thumb Code 0 aeabi_memset4.o(.text) + __aeabi_memclr4 0x080004b3 Thumb Code 0 rt_memclr_w.o(.text) + __aeabi_memclr8 0x080004b3 Thumb Code 0 rt_memclr_w.o(.text) + __rt_memclr_w 0x080004b3 Thumb Code 0 rt_memclr_w.o(.text) + _memset_w 0x080004b7 Thumb Code 74 rt_memclr_w.o(.text) + __use_two_region_memory 0x08000501 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08000503 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x08000505 Thumb Code 2 heapauxi.o(.text) + __read_errno 0x08000507 Thumb Code 10 _rserrno.o(.text) + __set_errno 0x08000511 Thumb Code 12 _rserrno.o(.text) + __aeabi_errno_addr 0x0800051d Thumb Code 8 rt_errno_addr_intlibspace.o(.text) + __errno$intlibspace 0x0800051d Thumb Code 0 rt_errno_addr_intlibspace.o(.text) + __rt_errno_addr$intlibspace 0x0800051d Thumb Code 0 rt_errno_addr_intlibspace.o(.text) + __user_libspace 0x08000525 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08000525 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08000525 Thumb Code 0 libspace.o(.text) + __user_setup_stackheap 0x0800052d Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x08000577 Thumb Code 18 exit.o(.text) + _sys_exit 0x08000589 Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x08000595 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x08000595 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x08000597 Thumb Code 0 indicate_semi.o(.text) + AHRS_GetEulr 0x08000599 Thumb Code 220 ahrs.o(.text.AHRS_GetEulr) + AHRS_Init 0x08000675 Thumb Code 388 ahrs.o(.text.AHRS_Init) + AHRS_ResetEulr 0x080007f9 Thumb Code 10 ahrs.o(.text.AHRS_ResetEulr) + AHRS_Update 0x08000805 Thumb Code 1422 ahrs.o(.text.AHRS_Update) + AI_Get_NUC 0x08001085 Thumb Code 84 ai.o(.text.AI_Get_NUC) + AI_ParseHost 0x080010d9 Thumb Code 92 ai.o(.text.AI_ParseHost) + AI_StartReceiving 0x08001135 Thumb Code 26 ai.o(.text.AI_StartReceiving) + AI_StartSend 0x08001151 Thumb Code 18 ai.o(.text.AI_StartSend) + AbsClip 0x08001165 Thumb Code 34 user_math.o(.text.AbsClip) + BMI088_AcclStartDmaRecv 0x0800119d Thumb Code 24 bmi088.o(.text.BMI088_AcclStartDmaRecv) + BMI088_AcclWaitDmaCplt 0x080011b5 Thumb Code 16 bmi088.o(.text.BMI088_AcclWaitDmaCplt) + BMI088_GetUpdateFreq 0x080011c5 Thumb Code 12 bmi088.o(.text.BMI088_GetUpdateFreq) + BMI088_GyroStartDmaRecv 0x080011e5 Thumb Code 26 bmi088.o(.text.BMI088_GyroStartDmaRecv) + BMI088_GyroWaitDmaCplt 0x08001201 Thumb Code 16 bmi088.o(.text.BMI088_GyroWaitDmaCplt) + BMI088_Init 0x08001211 Thumb Code 322 bmi088.o(.text.BMI088_Init) + BMI088_ParseAccl 0x08001355 Thumb Code 148 bmi088.o(.text.BMI088_ParseAccl) + BMI088_ParseGyro 0x080013e9 Thumb Code 132 bmi088.o(.text.BMI088_ParseGyro) + BMI088_WaitNew 0x080014ad Thumb Code 16 bmi088.o(.text.BMI088_WaitNew) + BSP_CAN_GetHandle 0x08001685 Thumb Code 38 can_1.o(.text.BSP_CAN_GetHandle) + BSP_CAN_GetMessage 0x080016ad Thumb Code 128 can_1.o(.text.BSP_CAN_GetMessage) + BSP_CAN_Init 0x0800172d Thumb Code 308 can_1.o(.text.BSP_CAN_Init) + BSP_CAN_ParseId 0x08001861 Thumb Code 20 can_1.o(.text.BSP_CAN_ParseId) + BSP_CAN_RegisterCallback 0x08001875 Thumb Code 68 can_1.o(.text.BSP_CAN_RegisterCallback) + BSP_CAN_RegisterId 0x080018b9 Thumb Code 30 can_1.o(.text.BSP_CAN_RegisterId) + BSP_CAN_Transmit 0x08001a61 Thumb Code 226 can_1.o(.text.BSP_CAN_Transmit) + BSP_CAN_TransmitStdDataFrame 0x08001b45 Thumb Code 40 can_1.o(.text.BSP_CAN_TransmitStdDataFrame) + BSP_Free 0x08001d05 Thumb Code 8 mm.o(.text.BSP_Free) + BSP_GPIO_DisableIRQ 0x08001d0d Thumb Code 48 gpio_1.o(.text.BSP_GPIO_DisableIRQ) + BSP_GPIO_EnableIRQ 0x08001d3d Thumb Code 48 gpio_1.o(.text.BSP_GPIO_EnableIRQ) + BSP_GPIO_ReadPin 0x08001d6d Thumb Code 44 gpio_1.o(.text.BSP_GPIO_ReadPin) + BSP_GPIO_RegisterCallback 0x08001d99 Thumb Code 74 gpio_1.o(.text.BSP_GPIO_RegisterCallback) + BSP_GPIO_WritePin 0x08001de5 Thumb Code 48 gpio_1.o(.text.BSP_GPIO_WritePin) + BSP_Malloc 0x08001e15 Thumb Code 8 mm.o(.text.BSP_Malloc) + BSP_PWM_SetComp 0x08001e1d Thumb Code 92 pwm.o(.text.BSP_PWM_SetComp) + BSP_PWM_Start 0x08001e79 Thumb Code 30 pwm.o(.text.BSP_PWM_Start) + BSP_SPI_GetHandle 0x08001e99 Thumb Code 18 spi_1.o(.text.BSP_SPI_GetHandle) + BSP_SPI_Receive 0x08001ead Thumb Code 52 spi_1.o(.text.BSP_SPI_Receive) + BSP_SPI_RegisterCallback 0x08001ee1 Thumb Code 30 spi_1.o(.text.BSP_SPI_RegisterCallback) + BSP_SPI_Transmit 0x08001f01 Thumb Code 52 spi_1.o(.text.BSP_SPI_Transmit) + BSP_TIME_Delay 0x08001f35 Thumb Code 88 time.o(.text.BSP_TIME_Delay_ms) + BSP_TIME_Delay_ms 0x08001f35 Thumb Code 88 time.o(.text.BSP_TIME_Delay_ms) + BSP_TIME_Get 0x08001f8d Thumb Code 80 time.o(.text.BSP_TIME_Get_us) + BSP_TIME_Get_us 0x08001f8d Thumb Code 80 time.o(.text.BSP_TIME_Get_us) + BSP_UART_GetHandle 0x08001fdd Thumb Code 16 uart.o(.text.BSP_UART_GetHandle) + BSP_UART_IRQHandler 0x08001ffd Thumb Code 58 uart.o(.text.BSP_UART_IRQHandler) + BSP_UART_Receive 0x08002039 Thumb Code 64 uart.o(.text.BSP_UART_Receive) + BSP_UART_RegisterCallback 0x08002079 Thumb Code 50 uart.o(.text.BSP_UART_RegisterCallback) + BSP_UART_Transmit 0x080020ad Thumb Code 64 uart.o(.text.BSP_UART_Transmit) + BusFault_Handler 0x080020ed Thumb Code 2 stm32f4xx_it.o(.text.BusFault_Handler) + CAN1_RX0_IRQHandler 0x080020f1 Thumb Code 16 stm32f4xx_it.o(.text.CAN1_RX0_IRQHandler) + CAN1_RX1_IRQHandler 0x08002101 Thumb Code 16 stm32f4xx_it.o(.text.CAN1_RX1_IRQHandler) + CAN1_SCE_IRQHandler 0x08002111 Thumb Code 16 stm32f4xx_it.o(.text.CAN1_SCE_IRQHandler) + CAN1_TX_IRQHandler 0x08002121 Thumb Code 16 stm32f4xx_it.o(.text.CAN1_TX_IRQHandler) + CAN2_RX1_IRQHandler 0x08002131 Thumb Code 16 stm32f4xx_it.o(.text.CAN2_RX1_IRQHandler) + CAN2_SCE_IRQHandler 0x08002141 Thumb Code 16 stm32f4xx_it.o(.text.CAN2_SCE_IRQHandler) + CAN2_TX_IRQHandler 0x08002151 Thumb Code 16 stm32f4xx_it.o(.text.CAN2_TX_IRQHandler) + CRC16_Calc 0x0800219d Thumb Code 30 crc16.o(.text.CRC16_Calc) + CRC16_Verify 0x080021bd Thumb Code 50 crc16.o(.text.CRC16_Verify) + CircleAdd 0x080021f1 Thumb Code 58 user_math.o(.text.CircleAdd) + CircleError 0x0800222d Thumb Code 60 user_math.o(.text.CircleError) + Clip 0x08002269 Thumb Code 38 user_math.o(.text.Clip) + Config_GetRobotParam 0x08002291 Thumb Code 10 config.o(.text.Config_GetRobotParam) + DMA1_Stream1_IRQHandler 0x0800229d Thumb Code 16 stm32f4xx_it.o(.text.DMA1_Stream1_IRQHandler) + DMA2_Stream2_IRQHandler 0x080022ad Thumb Code 16 stm32f4xx_it.o(.text.DMA2_Stream2_IRQHandler) + DMA2_Stream3_IRQHandler 0x080022bd Thumb Code 16 stm32f4xx_it.o(.text.DMA2_Stream3_IRQHandler) + DR16_Init 0x080023f9 Thumb Code 70 dr16.o(.text.DR16_Init) + DR16_Offline 0x08002441 Thumb Code 26 dr16.o(.text.DR16_Offline) + DR16_ParseData 0x0800245d Thumb Code 308 dr16.o(.text.DR16_ParseData) + DR16_StartDmaRecv 0x080025a5 Thumb Code 30 dr16.o(.text.DR16_StartDmaRecv) + DR16_WaitDmaCplt 0x080025c5 Thumb Code 22 dr16.o(.text.DR16_WaitDmaCplt) + DebugMon_Handler 0x080025dd Thumb Code 2 stm32f4xx_it.o(.text.DebugMon_Handler) + EXTI0_IRQHandler 0x080025e1 Thumb Code 10 stm32f4xx_it.o(.text.EXTI0_IRQHandler) + EXTI3_IRQHandler 0x080025ed Thumb Code 10 stm32f4xx_it.o(.text.EXTI3_IRQHandler) + EXTI4_IRQHandler 0x080025f9 Thumb Code 10 stm32f4xx_it.o(.text.EXTI4_IRQHandler) + EXTI9_5_IRQHandler 0x08002605 Thumb Code 10 stm32f4xx_it.o(.text.EXTI9_5_IRQHandler) + Error_Handler 0x08002611 Thumb Code 6 main.o(.text.Error_Handler) + Gimbal_Cmd 0x08002619 Thumb Code 168 remote_cmd.o(.text.Gimbal_Cmd) + Gimbal_Control 0x080026c1 Thumb Code 928 gimbal.o(.text.Gimbal_Control) + Gimbal_Control_mode 0x08002a61 Thumb Code 88 gimbal.o(.text.Gimbal_Control_mode) + Gimbal_Init 0x08002b5d Thumb Code 336 gimbal.o(.text.Gimbal_Init) + Gimbal_Output 0x08002cad Thumb Code 280 gimbal.o(.text.Gimbal_Output) + Gimbal_UpdateFeedback 0x08002e4d Thumb Code 280 gimbal.o(.text.Gimbal_UpdateFeedback) + Gimbal_UpdateIMU 0x08002f65 Thumb Code 78 gimbal.o(.text.Gimbal_UpdateIMU) + HAL_CAN_ActivateNotification 0x08002fb5 Thumb Code 38 stm32f4xx_hal_can.o(.text.HAL_CAN_ActivateNotification) + HAL_CAN_AddTxMessage 0x08002fdd Thumb Code 146 stm32f4xx_hal_can.o(.text.HAL_CAN_AddTxMessage) + HAL_CAN_ConfigFilter 0x08003071 Thumb Code 222 stm32f4xx_hal_can.o(.text.HAL_CAN_ConfigFilter) + HAL_CAN_ErrorCallback 0x08003151 Thumb Code 36 can_1.o(.text.HAL_CAN_ErrorCallback) + HAL_CAN_GetRxFifoFillLevel 0x08003175 Thumb Code 32 stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxFifoFillLevel) + HAL_CAN_GetRxMessage 0x08003195 Thumb Code 292 stm32f4xx_hal_can.o(.text.HAL_CAN_GetRxMessage) + HAL_CAN_GetTxMailboxesFreeLevel 0x080032b9 Thumb Code 40 stm32f4xx_hal_can.o(.text.HAL_CAN_GetTxMailboxesFreeLevel) + HAL_CAN_IRQHandler 0x080032e1 Thumb Code 570 stm32f4xx_hal_can.o(.text.HAL_CAN_IRQHandler) + HAL_CAN_Init 0x0800351d Thumb Code 244 stm32f4xx_hal_can.o(.text.HAL_CAN_Init) + HAL_CAN_MspInit 0x08003611 Thumb Code 362 can.o(.text.HAL_CAN_MspInit) + HAL_CAN_RxFifo0FullCallback 0x0800377d Thumb Code 36 can_1.o(.text.HAL_CAN_RxFifo0FullCallback) + HAL_CAN_RxFifo0MsgPendingCallback 0x080037a1 Thumb Code 36 can_1.o(.text.HAL_CAN_RxFifo0MsgPendingCallback) + HAL_CAN_RxFifo1FullCallback 0x080037c5 Thumb Code 36 can_1.o(.text.HAL_CAN_RxFifo1FullCallback) + HAL_CAN_RxFifo1MsgPendingCallback 0x080037e9 Thumb Code 36 can_1.o(.text.HAL_CAN_RxFifo1MsgPendingCallback) + HAL_CAN_SleepCallback 0x0800380d Thumb Code 36 can_1.o(.text.HAL_CAN_SleepCallback) + HAL_CAN_Start 0x08003831 Thumb Code 90 stm32f4xx_hal_can.o(.text.HAL_CAN_Start) + HAL_CAN_TxMailbox0AbortCallback 0x0800388d Thumb Code 36 can_1.o(.text.HAL_CAN_TxMailbox0AbortCallback) + HAL_CAN_TxMailbox0CompleteCallback 0x080038b1 Thumb Code 34 can_1.o(.text.HAL_CAN_TxMailbox0CompleteCallback) + HAL_CAN_TxMailbox1AbortCallback 0x080038d5 Thumb Code 36 can_1.o(.text.HAL_CAN_TxMailbox1AbortCallback) + HAL_CAN_TxMailbox1CompleteCallback 0x080038f9 Thumb Code 36 can_1.o(.text.HAL_CAN_TxMailbox1CompleteCallback) + HAL_CAN_TxMailbox2AbortCallback 0x0800391d Thumb Code 36 can_1.o(.text.HAL_CAN_TxMailbox2AbortCallback) + HAL_CAN_TxMailbox2CompleteCallback 0x08003941 Thumb Code 36 can_1.o(.text.HAL_CAN_TxMailbox2CompleteCallback) + HAL_CAN_WakeUpFromRxMsgCallback 0x08003965 Thumb Code 36 can_1.o(.text.HAL_CAN_WakeUpFromRxMsgCallback) + HAL_DMA_Abort 0x08003989 Thumb Code 128 stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort) + HAL_DMA_Abort_IT 0x08003a09 Thumb Code 36 stm32f4xx_hal_dma.o(.text.HAL_DMA_Abort_IT) + HAL_DMA_IRQHandler 0x08003a2d Thumb Code 396 stm32f4xx_hal_dma.o(.text.HAL_DMA_IRQHandler) + HAL_DMA_Init 0x08003bb9 Thumb Code 206 stm32f4xx_hal_dma.o(.text.HAL_DMA_Init) + HAL_DMA_Start_IT 0x08003c89 Thumb Code 98 stm32f4xx_hal_dma.o(.text.HAL_DMA_Start_IT) + HAL_Delay 0x08003ced Thumb Code 40 stm32f4xx_hal.o(.text.HAL_Delay) + HAL_GPIO_EXTI_Callback 0x08003d15 Thumb Code 44 gpio_1.o(.text.HAL_GPIO_EXTI_Callback) + HAL_GPIO_EXTI_IRQHandler 0x08003d41 Thumb Code 26 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) + HAL_GPIO_Init 0x08003d5d Thumb Code 410 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_Init) + HAL_GPIO_ReadPin 0x08003ef9 Thumb Code 10 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) + HAL_GPIO_WritePin 0x08003f05 Thumb Code 10 stm32f4xx_hal_gpio.o(.text.HAL_GPIO_WritePin) + HAL_GetTick 0x08003f11 Thumb Code 12 stm32f4xx_hal.o(.text.HAL_GetTick) + HAL_I2C_Init 0x08003f1d Thumb Code 408 stm32f4xx_hal_i2c.o(.text.HAL_I2C_Init) + HAL_I2C_MspInit 0x080040b5 Thumb Code 112 i2c.o(.text.HAL_I2C_MspInit) + HAL_IncTick 0x08004125 Thumb Code 26 stm32f4xx_hal.o(.text.HAL_IncTick) + HAL_Init 0x08004141 Thumb Code 54 stm32f4xx_hal.o(.text.HAL_Init) + HAL_InitTick 0x08004179 Thumb Code 80 stm32f4xx_hal.o(.text.HAL_InitTick) + HAL_MspInit 0x080041c9 Thumb Code 70 stm32f4xx_hal_msp.o(.text.HAL_MspInit) + HAL_NVIC_DisableIRQ 0x08004211 Thumb Code 8 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) + HAL_NVIC_EnableIRQ 0x08004219 Thumb Code 8 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) + HAL_NVIC_SetPriority 0x08004221 Thumb Code 30 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) + HAL_NVIC_SetPriorityGrouping 0x08004241 Thumb Code 8 stm32f4xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) + HAL_RCC_ClockConfig 0x08004249 Thumb Code 352 stm32f4xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) + HAL_RCC_GetHCLKFreq 0x080043a9 Thumb Code 12 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) + HAL_RCC_GetPCLK1Freq 0x080043b5 Thumb Code 34 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) + HAL_RCC_GetPCLK2Freq 0x080043d9 Thumb Code 34 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) + HAL_RCC_GetSysClockFreq 0x080043fd Thumb Code 104 stm32f4xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) + HAL_RCC_OscConfig 0x08004465 Thumb Code 840 stm32f4xx_hal_rcc.o(.text.HAL_RCC_OscConfig) + HAL_SPI_ErrorCallback 0x080047ad Thumb Code 34 spi_1.o(.text.HAL_SPI_ErrorCallback) + HAL_SPI_Init 0x080047d1 Thumb Code 180 stm32f4xx_hal_spi.o(.text.HAL_SPI_Init) + HAL_SPI_MspInit 0x08004885 Thumb Code 302 spi.o(.text.HAL_SPI_MspInit) + HAL_SPI_Receive 0x080049b5 Thumb Code 370 stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive) + HAL_SPI_Receive_DMA 0x08004b29 Thumb Code 236 stm32f4xx_hal_spi.o(.text.HAL_SPI_Receive_DMA) + HAL_SPI_RxCpltCallback 0x08004c15 Thumb Code 34 spi_1.o(.text.HAL_SPI_RxCpltCallback) + HAL_SPI_RxHalfCpltCallback 0x08004c39 Thumb Code 34 spi_1.o(.text.HAL_SPI_RxHalfCpltCallback) + HAL_SPI_Transmit 0x08004c5d Thumb Code 394 stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit) + HAL_SPI_TransmitReceive 0x08004de9 Thumb Code 504 stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive) + HAL_SPI_TransmitReceive_DMA 0x08004fe1 Thumb Code 292 stm32f4xx_hal_spi.o(.text.HAL_SPI_TransmitReceive_DMA) + HAL_SPI_Transmit_DMA 0x08005105 Thumb Code 204 stm32f4xx_hal_spi.o(.text.HAL_SPI_Transmit_DMA) + HAL_SPI_TxCpltCallback 0x080051d1 Thumb Code 32 spi_1.o(.text.HAL_SPI_TxCpltCallback) + HAL_SPI_TxHalfCpltCallback 0x080051f1 Thumb Code 34 spi_1.o(.text.HAL_SPI_TxHalfCpltCallback) + HAL_SPI_TxRxCpltCallback 0x08005215 Thumb Code 34 spi_1.o(.text.HAL_SPI_TxRxCpltCallback) + HAL_SPI_TxRxHalfCpltCallback 0x08005239 Thumb Code 34 spi_1.o(.text.HAL_SPI_TxRxHalfCpltCallback) + HAL_SYSTICK_Config 0x0800525d Thumb Code 8 stm32f4xx_hal_cortex.o(.text.HAL_SYSTICK_Config) + HAL_TIM_Base_Init 0x08005265 Thumb Code 90 stm32f4xx_hal_tim.o(.text.HAL_TIM_Base_Init) + HAL_TIM_Base_MspInit 0x080052c1 Thumb Code 54 tim.o(.text.HAL_TIM_Base_MspInit) + HAL_TIM_MspPostInit 0x080052f9 Thumb Code 94 tim.o(.text.HAL_TIM_MspPostInit) + HAL_TIM_PWM_ConfigChannel 0x08005359 Thumb Code 152 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) + HAL_TIM_PWM_Init 0x080053f1 Thumb Code 90 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Init) + HAL_TIM_PWM_MspInit 0x0800544d Thumb Code 2 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) + HAL_TIM_PWM_Start 0x08005451 Thumb Code 290 stm32f4xx_hal_tim.o(.text.HAL_TIM_PWM_Start) + HAL_UARTEx_RxEventCallback 0x08005575 Thumb Code 2 stm32f4xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) + HAL_UART_ErrorCallback 0x08005579 Thumb Code 38 uart.o(.text.HAL_UART_ErrorCallback) + HAL_UART_IRQHandler 0x080055a1 Thumb Code 602 stm32f4xx_hal_uart.o(.text.HAL_UART_IRQHandler) + HAL_UART_Init 0x080057fd Thumb Code 96 stm32f4xx_hal_uart.o(.text.HAL_UART_Init) + HAL_UART_MspInit 0x0800585d Thumb Code 614 usart.o(.text.HAL_UART_MspInit) + HAL_UART_Receive_DMA 0x08005ac5 Thumb Code 44 stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_DMA) + HAL_UART_Receive_IT 0x08005af1 Thumb Code 42 stm32f4xx_hal_uart.o(.text.HAL_UART_Receive_IT) + HAL_UART_RxCpltCallback 0x08005b1d Thumb Code 38 uart.o(.text.HAL_UART_RxCpltCallback) + HAL_UART_RxHalfCpltCallback 0x08005b45 Thumb Code 38 uart.o(.text.HAL_UART_RxHalfCpltCallback) + HAL_UART_Transmit_DMA 0x08005b6d Thumb Code 140 stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) + HAL_UART_Transmit_IT 0x08005bf9 Thumb Code 56 stm32f4xx_hal_uart.o(.text.HAL_UART_Transmit_IT) + HAL_UART_TxCpltCallback 0x08005c31 Thumb Code 38 uart.o(.text.HAL_UART_TxCpltCallback) + HAL_UART_TxHalfCpltCallback 0x08005c59 Thumb Code 36 uart.o(.text.HAL_UART_TxHalfCpltCallback) + HardFault_Handler 0x08005c7d Thumb Code 2 stm32f4xx_it.o(.text.HardFault_Handler) + InvSqrt 0x08005c81 Thumb Code 66 user_math.o(.text.InvSqrt) + LowPassFilter2p_Apply 0x08005cc5 Thumb Code 124 filter.o(.text.LowPassFilter2p_Apply) + LowPassFilter2p_Init 0x08005d41 Thumb Code 164 filter.o(.text.LowPassFilter2p_Init) + LowPassFilter2p_Reset 0x08005de5 Thumb Code 92 filter.o(.text.LowPassFilter2p_Reset) + MOTOR_DM_Enable 0x08005e7d Thumb Code 70 motor_dm.o(.text.MOTOR_DM_Enable) + MOTOR_DM_GetMotor 0x08005ed9 Thumb Code 88 motor_dm.o(.text.MOTOR_DM_GetMotor) + MOTOR_DM_MITCtrl 0x08005f31 Thumb Code 46 motor_dm.o(.text.MOTOR_DM_MITCtrl) + MOTOR_DM_Register 0x08006059 Thumb Code 164 motor_dm.o(.text.MOTOR_DM_Register) + MOTOR_DM_Update 0x08006215 Thumb Code 160 motor_dm.o(.text.MOTOR_DM_Update) + MOTOR_RM_Ctrl 0x080062f1 Thumb Code 216 motor_rm.o(.text.MOTOR_RM_Ctrl) + MOTOR_RM_GetMotor 0x0800642d Thumb Code 80 motor_rm.o(.text.MOTOR_RM_GetMotor) + MOTOR_RM_Register 0x080064a1 Thumb Code 166 motor_rm.o(.text.MOTOR_RM_Register) + MOTOR_RM_Relax 0x08006549 Thumb Code 16 motor_rm.o(.text.MOTOR_RM_Relax) + MOTOR_RM_SetOutput 0x08006559 Thumb Code 158 motor_rm.o(.text.MOTOR_RM_SetOutput) + MOTOR_RM_Update 0x080065f9 Thumb Code 198 motor_rm.o(.text.MOTOR_RM_Update) + MX_CAN1_Init 0x080066c1 Thumb Code 64 can.o(.text.MX_CAN1_Init) + MX_CAN2_Init 0x08006701 Thumb Code 64 can.o(.text.MX_CAN2_Init) + MX_DMA_Init 0x08006741 Thumb Code 106 dma.o(.text.MX_DMA_Init) + MX_FREERTOS_Init 0x080067ad Thumb Code 58 freertos.o(.text.MX_FREERTOS_Init) + MX_GPIO_Init 0x080067e9 Thumb Code 392 gpio.o(.text.MX_GPIO_Init) + MX_I2C2_Init 0x08006971 Thumb Code 62 i2c.o(.text.MX_I2C2_Init) + MX_SPI1_Init 0x080069b1 Thumb Code 78 spi.o(.text.MX_SPI1_Init) + MX_TIM10_Init 0x08006a01 Thumb Code 136 tim.o(.text.MX_TIM10_Init) + MX_USART1_UART_Init 0x08006a89 Thumb Code 56 usart.o(.text.MX_USART1_UART_Init) + MX_USART2_UART_Init 0x08006ac1 Thumb Code 56 usart.o(.text.MX_USART2_UART_Init) + MX_USART3_UART_Init 0x08006af9 Thumb Code 66 usart.o(.text.MX_USART3_UART_Init) + MX_USART6_UART_Init 0x08006b3d Thumb Code 56 usart.o(.text.MX_USART6_UART_Init) + MemManage_Handler 0x08006b75 Thumb Code 2 stm32f4xx_it.o(.text.MemManage_Handler) + NMI_Handler 0x08006cd5 Thumb Code 2 stm32f4xx_it.o(.text.NMI_Handler) + PID_Calc 0x08006d05 Thumb Code 368 pid.o(.text.PID_Calc) + PID_Init 0x08006e75 Thumb Code 144 pid.o(.text.PID_Init) + PID_Reset 0x08006f05 Thumb Code 44 pid.o(.text.PID_Reset) + PID_ResetIntegral 0x08006f31 Thumb Code 14 pid.o(.text.PID_ResetIntegral) + PendSV_Handler 0x08006f41 Thumb Code 100 port.o(.text.PendSV_Handler) + SVC_Handler 0x08007331 Thumb Code 36 port.o(.text.SVC_Handler) + ScaleSumTo1 0x0800735d Thumb Code 54 user_math.o(.text.ScaleSumTo1) + Shoot_CaluTargetAngle 0x08007411 Thumb Code 160 shoot.o(.text.Shoot_CaluTargetAngle) + Shoot_CaluTargetRPM 0x080074b1 Thumb Code 44 shoot.o(.text.Shoot_CaluTargetRPM) + Shoot_Cmd 0x080074dd Thumb Code 40 remote_cmd.o(.text.Shoot_Cmd) + Shoot_Control 0x08007505 Thumb Code 108 shoot.o(.text.Shoot_Control) + Shoot_Init 0x08007571 Thumb Code 326 shoot.o(.text.Shoot_Init) + Shoot_JamDetectionFSM 0x080076b9 Thumb Code 304 shoot.o(.text.Shoot_JamDetectionFSM) + Shoot_ResetCalu 0x080077e9 Thumb Code 152 shoot.o(.text.Shoot_ResetCalu) + Shoot_ResetIntegral 0x08007881 Thumb Code 70 shoot.o(.text.Shoot_ResetIntegral) + Shoot_ResetOutput 0x080078c9 Thumb Code 50 shoot.o(.text.Shoot_ResetOutput) + Shoot_RunningFSM 0x080078fd Thumb Code 1264 shoot.o(.text.Shoot_RunningFSM) + Shoot_SetMode 0x08007ded Thumb Code 14 shoot.o(.text.Shoot_SetMode) + Shoot_UpdateFeedback 0x08007dfd Thumb Code 468 shoot.o(.text.Shoot_UpdateFeedback) + StartDefaultTask 0x08007fd1 Thumb Code 12 freertos.o(.text.StartDefaultTask) + SysTick_Handler 0x0800800d Thumb Code 20 stm32f4xx_it.o(.text.SysTick_Handler) + SystemClock_Config 0x08008021 Thumb Code 164 main.o(.text.SystemClock_Config) + SystemInit 0x080080c5 Thumb Code 18 system_stm32f4xx.o(.text.SystemInit) + TIM_Base_SetConfig 0x080080d9 Thumb Code 300 stm32f4xx_hal_tim.o(.text.TIM_Base_SetConfig) + TIM_CCxChannelCmd 0x08008205 Thumb Code 36 stm32f4xx_hal_tim.o(.text.TIM_CCxChannelCmd) + TIM_OC2_SetConfig 0x0800828d Thumb Code 106 stm32f4xx_hal_tim.o(.text.TIM_OC2_SetConfig) + Task_Init 0x080083b1 Thumb Code 292 init.o(.text.Task_Init) + Task_ai 0x080084d9 Thumb Code 160 ai_1.o(.text.Task_ai) + Task_atti_esti 0x08008579 Thumb Code 612 atti_esti.o(.text.Task_atti_esti) + Task_chassis_ctrl 0x080087e1 Thumb Code 64 chassis_ctrl.o(.text.Task_chassis_ctrl) + Task_dr16 0x08008821 Thumb Code 128 dr16_1.o(.text.Task_dr16) + Task_gimbal_ctrl 0x080088a1 Thumb Code 340 gimbal_ctrl.o(.text.Task_gimbal_ctrl) + Task_remote 0x080089f9 Thumb Code 160 remote.o(.text.Task_remote) + Task_shoot_ctrl 0x08008a99 Thumb Code 156 shoot_ctrl.o(.text.Task_shoot_ctrl) + UART_Start_Receive_DMA 0x08008edd Thumb Code 170 stm32f4xx_hal_uart.o(.text.UART_Start_Receive_DMA) + UART_Start_Receive_IT 0x08008f89 Thumb Code 52 stm32f4xx_hal_uart.o(.text.UART_Start_Receive_IT) + USART1_IRQHandler 0x08009011 Thumb Code 24 stm32f4xx_it.o(.text.USART1_IRQHandler) + USART2_IRQHandler 0x08009029 Thumb Code 16 stm32f4xx_it.o(.text.USART2_IRQHandler) + USART6_IRQHandler 0x08009039 Thumb Code 24 stm32f4xx_it.o(.text.USART6_IRQHandler) + UsageFault_Handler 0x08009051 Thumb Code 2 stm32f4xx_it.o(.text.UsageFault_Handler) + eTaskGetState 0x08009149 Thumb Code 156 tasks.o(.text.eTaskGetState) + main 0x08009211 Thumb Code 66 main.o(.text.main) + major_yaw_Control 0x08009255 Thumb Code 32 gimbal.o(.text.major_yaw_Control) + osDelay 0x080092b9 Thumb Code 32 cmsis_os2.o(.text.osDelay) + osDelayUntil 0x080092d9 Thumb Code 52 cmsis_os2.o(.text.osDelayUntil) + osKernelGetState 0x0800930d Thumb Code 38 cmsis_os2.o(.text.osKernelGetState) + osKernelGetTickCount 0x08009335 Thumb Code 20 cmsis_os2.o(.text.osKernelGetTickCount) + osKernelGetTickFreq 0x08009349 Thumb Code 6 cmsis_os2.o(.text.osKernelGetTickFreq) + osKernelInitialize 0x08009351 Thumb Code 40 cmsis_os2.o(.text.osKernelInitialize) + osKernelLock 0x08009379 Thumb Code 44 cmsis_os2.o(.text.osKernelLock) + osKernelStart 0x080093a5 Thumb Code 52 cmsis_os2.o(.text.osKernelStart) + osKernelUnlock 0x080093d9 Thumb Code 68 cmsis_os2.o(.text.osKernelUnlock) + osMessageQueueGet 0x0800941d Thumb Code 134 cmsis_os2.o(.text.osMessageQueueGet) + osMessageQueueNew 0x080094a5 Thumb Code 160 cmsis_os2.o(.text.osMessageQueueNew) + osMessageQueuePut 0x08009545 Thumb Code 142 cmsis_os2.o(.text.osMessageQueuePut) + osMessageQueueReset 0x080095d5 Thumb Code 36 cmsis_os2.o(.text.osMessageQueueReset) + osMutexAcquire 0x080095f9 Thumb Code 82 cmsis_os2.o(.text.osMutexAcquire) + osMutexNew 0x0800964d Thumb Code 150 cmsis_os2.o(.text.osMutexNew) + osMutexRelease 0x080096e5 Thumb Code 62 cmsis_os2.o(.text.osMutexRelease) + osThreadFlagsSet 0x08009725 Thumb Code 126 cmsis_os2.o(.text.osThreadFlagsSet) + osThreadFlagsWait 0x080097a5 Thumb Code 186 cmsis_os2.o(.text.osThreadFlagsWait) + osThreadGetId 0x08009861 Thumb Code 8 cmsis_os2.o(.text.osThreadGetId) + osThreadNew 0x08009869 Thumb Code 180 cmsis_os2.o(.text.osThreadNew) + osThreadTerminate 0x0800991d Thumb Code 52 cmsis_os2.o(.text.osThreadTerminate) + pvPortMalloc 0x0800a2f5 Thumb Code 330 heap_4.o(.text.pvPortMalloc) + pvTaskIncrementMutexHeldCount 0x0800a441 Thumb Code 24 tasks.o(.text.pvTaskIncrementMutexHeldCount) + pxPortInitialiseStack 0x0800a459 Thumb Code 40 port.o(.text.pxPortInitialiseStack) + uxListRemove 0x0800a4ad Thumb Code 36 list.o(.text.uxListRemove) + vApplicationGetIdleTaskMemory 0x0800a4d1 Thumb Code 26 cmsis_os2.o(.text.vApplicationGetIdleTaskMemory) + vApplicationGetTimerTaskMemory 0x0800a4ed Thumb Code 28 cmsis_os2.o(.text.vApplicationGetTimerTaskMemory) + vListInitialise 0x0800a509 Thumb Code 22 list.o(.text.vListInitialise) + vListInitialiseItem 0x0800a521 Thumb Code 6 list.o(.text.vListInitialiseItem) + vListInsert 0x0800a529 Thumb Code 58 list.o(.text.vListInsert) + vListInsertEnd 0x0800a565 Thumb Code 28 list.o(.text.vListInsertEnd) + vPortEnterCritical 0x0800a595 Thumb Code 70 port.o(.text.vPortEnterCritical) + vPortExitCritical 0x0800a5dd Thumb Code 46 port.o(.text.vPortExitCritical) + vPortFree 0x0800a60d Thumb Code 138 heap_4.o(.text.vPortFree) + vPortSetupTimerInterrupt 0x0800a699 Thumb Code 52 port.o(.text.vPortSetupTimerInterrupt) + vPortValidateInterruptPriority 0x0800a6cd Thumb Code 98 port.o(.text.vPortValidateInterruptPriority) + vQueueAddToRegistry 0x0800a731 Thumb Code 40 queue.o(.text.vQueueAddToRegistry) + vQueueWaitForMessageRestricted 0x0800a759 Thumb Code 68 queue.o(.text.vQueueWaitForMessageRestricted) + vTaskDelay 0x0800a79d Thumb Code 84 tasks.o(.text.vTaskDelay) + vTaskDelayUntil 0x0800a7f1 Thumb Code 168 tasks.o(.text.vTaskDelayUntil) + vTaskDelete 0x0800a899 Thumb Code 194 tasks.o(.text.vTaskDelete) + vTaskInternalSetTimeOutState 0x0800a95d Thumb Code 26 tasks.o(.text.vTaskInternalSetTimeOutState) + vTaskMissedYield 0x0800a979 Thumb Code 14 tasks.o(.text.vTaskMissedYield) + vTaskPlaceOnEventList 0x0800a989 Thumb Code 50 tasks.o(.text.vTaskPlaceOnEventList) + vTaskPlaceOnEventListRestricted 0x0800a9bd Thumb Code 62 tasks.o(.text.vTaskPlaceOnEventListRestricted) + vTaskPriorityDisinheritAfterTimeout 0x0800a9fd Thumb Code 164 tasks.o(.text.vTaskPriorityDisinheritAfterTimeout) + vTaskStartScheduler 0x0800aaa1 Thumb Code 156 tasks.o(.text.vTaskStartScheduler) + vTaskSuspendAll 0x0800ab45 Thumb Code 16 tasks.o(.text.vTaskSuspendAll) + vTaskSwitchContext 0x0800ab55 Thumb Code 154 tasks.o(.text.vTaskSwitchContext) + xPortStartScheduler 0x0800abf1 Thumb Code 274 port.o(.text.xPortStartScheduler) + xPortSysTickHandler 0x0800ad05 Thumb Code 46 port.o(.text.xPortSysTickHandler) + xQueueCreateMutex 0x0800ad35 Thumb Code 22 queue.o(.text.xQueueCreateMutex) + xQueueCreateMutexStatic 0x0800ad4d Thumb Code 34 queue.o(.text.xQueueCreateMutexStatic) + xQueueGenericCreate 0x0800ad71 Thumb Code 70 queue.o(.text.xQueueGenericCreate) + xQueueGenericCreateStatic 0x0800adb9 Thumb Code 150 queue.o(.text.xQueueGenericCreateStatic) + xQueueGenericReset 0x0800ae51 Thumb Code 126 queue.o(.text.xQueueGenericReset) + xQueueGenericSend 0x0800aed1 Thumb Code 418 queue.o(.text.xQueueGenericSend) + xQueueGenericSendFromISR 0x0800b075 Thumb Code 206 queue.o(.text.xQueueGenericSendFromISR) + xQueueGiveMutexRecursive 0x0800b145 Thumb Code 66 queue.o(.text.xQueueGiveMutexRecursive) + xQueueReceive 0x0800b189 Thumb Code 388 queue.o(.text.xQueueReceive) + xQueueReceiveFromISR 0x0800b30d Thumb Code 170 queue.o(.text.xQueueReceiveFromISR) + xQueueSemaphoreTake 0x0800b3b9 Thumb Code 454 queue.o(.text.xQueueSemaphoreTake) + xQueueTakeMutexRecursive 0x0800b581 Thumb Code 60 queue.o(.text.xQueueTakeMutexRecursive) + xTaskCheckForTimeOut 0x0800b5bd Thumb Code 136 tasks.o(.text.xTaskCheckForTimeOut) + xTaskCreate 0x0800b645 Thumb Code 102 tasks.o(.text.xTaskCreate) + xTaskCreateStatic 0x0800b6ad Thumb Code 118 tasks.o(.text.xTaskCreateStatic) + xTaskGenericNotify 0x0800b725 Thumb Code 252 tasks.o(.text.xTaskGenericNotify) + xTaskGenericNotifyFromISR 0x0800b821 Thumb Code 298 tasks.o(.text.xTaskGenericNotifyFromISR) + xTaskGetCurrentTaskHandle 0x0800b94d Thumb Code 12 tasks.o(.text.xTaskGetCurrentTaskHandle) + xTaskGetSchedulerState 0x0800b959 Thumb Code 38 tasks.o(.text.xTaskGetSchedulerState) + xTaskGetTickCount 0x0800b981 Thumb Code 12 tasks.o(.text.xTaskGetTickCount) + xTaskGetTickCountFromISR 0x0800b98d Thumb Code 18 tasks.o(.text.xTaskGetTickCountFromISR) + xTaskIncrementTick 0x0800b9a1 Thumb Code 338 tasks.o(.text.xTaskIncrementTick) + xTaskNotifyWait 0x0800baf5 Thumb Code 144 tasks.o(.text.xTaskNotifyWait) + xTaskPriorityDisinherit 0x0800bb85 Thumb Code 146 tasks.o(.text.xTaskPriorityDisinherit) + xTaskPriorityInherit 0x0800bc19 Thumb Code 146 tasks.o(.text.xTaskPriorityInherit) + xTaskRemoveFromEventList 0x0800bcad Thumb Code 142 tasks.o(.text.xTaskRemoveFromEventList) + xTaskResumeAll 0x0800bd3d Thumb Code 276 tasks.o(.text.xTaskResumeAll) + xTimerCreateTimerTask 0x0800be51 Thumb Code 108 timers.o(.text.xTimerCreateTimerTask) + xTimerGenericCommand 0x0800bec5 Thumb Code 104 timers.o(.text.xTimerGenericCommand) + __ARM_fpclassify 0x0800bf2d Thumb Code 48 fpclassify.o(i.__ARM_fpclassify) + __ARM_fpclassifyf 0x0800bf5d Thumb Code 38 fpclassifyf.o(i.__ARM_fpclassifyf) + __hardfp_asinf 0x0800bf85 Thumb Code 258 asinf.o(i.__hardfp_asinf) + __hardfp_atan 0x0800c0b1 Thumb Code 622 atan.o(i.__hardfp_atan) + __hardfp_atan2 0x0800c389 Thumb Code 448 atan2.o(i.__hardfp_atan2) + __hardfp_atan2f 0x0800c589 Thumb Code 594 atan2f.o(i.__hardfp_atan2f) + __hardfp_tanf 0x0800c835 Thumb Code 322 tanf.o(i.__hardfp_tanf) + __kernel_poly 0x0800c9b1 Thumb Code 248 poly.o(i.__kernel_poly) + __mathlib_dbl_infnan 0x0800caa9 Thumb Code 20 dunder.o(i.__mathlib_dbl_infnan) + __mathlib_dbl_infnan2 0x0800cabd Thumb Code 20 dunder.o(i.__mathlib_dbl_infnan2) + __mathlib_dbl_underflow 0x0800cad1 Thumb Code 24 dunder.o(i.__mathlib_dbl_underflow) + __mathlib_flt_infnan 0x0800caf1 Thumb Code 6 funder.o(i.__mathlib_flt_infnan) + __mathlib_flt_infnan2 0x0800caf7 Thumb Code 6 funder.o(i.__mathlib_flt_infnan2) + __mathlib_flt_invalid 0x0800cafd Thumb Code 10 funder.o(i.__mathlib_flt_invalid) + __mathlib_flt_underflow 0x0800cb0d Thumb Code 10 funder.o(i.__mathlib_flt_underflow) + __mathlib_rredf2 0x0800cb1d Thumb Code 316 rredf.o(i.__mathlib_rredf2) + atan 0x0800cc71 Thumb Code 16 atan.o(i.atan) + fabs 0x0800cc81 Thumb Code 24 fabs.o(i.fabs) + sqrtf 0x0800cc99 Thumb Code 62 sqrtf.o(i.sqrtf) + __aeabi_dneg 0x0800ccd7 Thumb Code 0 basic.o(x$fpl$basic) + _dneg 0x0800ccd7 Thumb Code 6 basic.o(x$fpl$basic) + __aeabi_fneg 0x0800ccdd Thumb Code 0 basic.o(x$fpl$basic) + _fneg 0x0800ccdd Thumb Code 6 basic.o(x$fpl$basic) + _dabs 0x0800cce3 Thumb Code 6 basic.o(x$fpl$basic) + _fabs 0x0800cce9 Thumb Code 6 basic.o(x$fpl$basic) + __aeabi_d2f 0x0800ccf1 Thumb Code 0 d2f.o(x$fpl$d2f) + _d2f 0x0800ccf1 Thumb Code 98 d2f.o(x$fpl$d2f) + __aeabi_dadd 0x0800cd55 Thumb Code 0 daddsub_clz.o(x$fpl$dadd) + _dadd 0x0800cd55 Thumb Code 332 daddsub_clz.o(x$fpl$dadd) + __fpl_dcmp_Inf 0x0800cea5 Thumb Code 24 dcmpi.o(x$fpl$dcmpinf) + __aeabi_ddiv 0x0800cebd Thumb Code 0 ddiv.o(x$fpl$ddiv) + _ddiv 0x0800cebd Thumb Code 556 ddiv.o(x$fpl$ddiv) + __aeabi_cdcmpeq 0x0800d171 Thumb Code 0 deqf.o(x$fpl$deqf) + _dcmpeq 0x0800d171 Thumb Code 120 deqf.o(x$fpl$deqf) + __aeabi_d2uiz 0x0800d1e9 Thumb Code 0 dfixu.o(x$fpl$dfixu) + _dfixu 0x0800d1e9 Thumb Code 90 dfixu.o(x$fpl$dfixu) + __aeabi_i2d 0x0800d243 Thumb Code 0 dflt_clz.o(x$fpl$dflt) + _dflt 0x0800d243 Thumb Code 46 dflt_clz.o(x$fpl$dflt) + __aeabi_ui2d 0x0800d271 Thumb Code 0 dflt_clz.o(x$fpl$dfltu) + _dfltu 0x0800d271 Thumb Code 38 dflt_clz.o(x$fpl$dfltu) + __aeabi_dmul 0x0800d299 Thumb Code 0 dmul.o(x$fpl$dmul) + _dmul 0x0800d299 Thumb Code 332 dmul.o(x$fpl$dmul) + __fpl_dnaninf 0x0800d3ed Thumb Code 156 dnaninf.o(x$fpl$dnaninf) + __fpl_dretinf 0x0800d489 Thumb Code 12 dretinf.o(x$fpl$dretinf) + __aeabi_drsub 0x0800d495 Thumb Code 0 daddsub_clz.o(x$fpl$drsb) + _drsb 0x0800d495 Thumb Code 22 daddsub_clz.o(x$fpl$drsb) + __aeabi_dsub 0x0800d4ad Thumb Code 0 daddsub_clz.o(x$fpl$dsub) + _dsub 0x0800d4ad Thumb Code 472 daddsub_clz.o(x$fpl$dsub) + __aeabi_f2d 0x0800d689 Thumb Code 0 f2d.o(x$fpl$f2d) + _f2d 0x0800d689 Thumb Code 86 f2d.o(x$fpl$f2d) + __aeabi_ul2f 0x0800d6df Thumb Code 0 ffltll_clz.o(x$fpl$ffltll) + _ll_uto_f 0x0800d6df Thumb Code 6 ffltll_clz.o(x$fpl$ffltll) + __aeabi_l2f 0x0800d6e5 Thumb Code 0 ffltll_clz.o(x$fpl$ffltll) + _ll_sto_f 0x0800d6e5 Thumb Code 90 ffltll_clz.o(x$fpl$ffltll) + __fpl_fnaninf 0x0800d73f Thumb Code 140 fnaninf.o(x$fpl$fnaninf) + _fp_init 0x0800d7cb Thumb Code 26 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x0800d7e3 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x0800d7e3 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fpl_fretinf 0x0800d7e5 Thumb Code 10 fretinf.o(x$fpl$fretinf) + __I$use$fp 0x0800d7ee Number 0 usenofp.o(x$fpl$usenofp) + __mathlib_zero 0x0800d888 Data 8 qnan.o(.constdata) + AHBPrescTable 0x0800d8b0 Data 16 system_stm32f4xx.o(.rodata.AHBPrescTable) + APBPrescTable 0x0800d8c0 Data 8 system_stm32f4xx.o(.rodata.APBPrescTable) + attr_ai 0x0800d900 Data 36 user_task.o(.rodata.attr_ai) + attr_atti_esti 0x0800d924 Data 36 user_task.o(.rodata.attr_atti_esti) + attr_chassis_ctrl 0x0800d948 Data 36 user_task.o(.rodata.attr_chassis_ctrl) + attr_dr16 0x0800d96c Data 36 user_task.o(.rodata.attr_dr16) + attr_gimbal_ctrl 0x0800d990 Data 36 user_task.o(.rodata.attr_gimbal_ctrl) + attr_init 0x0800d9b4 Data 36 user_task.o(.rodata.attr_init) + attr_remote 0x0800d9d8 Data 36 user_task.o(.rodata.attr_remote) + attr_shoot_ctrl 0x0800d9fc Data 36 user_task.o(.rodata.attr_shoot_ctrl) + defaultTask_attributes 0x0800dc20 Data 36 freertos.o(.rodata.defaultTask_attributes) + Region$$Table$$Base 0x0800dcb8 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800dcf8 Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000000 Data 4 system_stm32f4xx.o(.data.SystemCoreClock) + cali_bmi088 0x20000008 Data 12 atti_esti.o(.data.cali_bmi088) + robot_config 0x20000014 Data 800 config.o(.data.robot_config) + uwTickPrio 0x20000334 Data 4 stm32f4xx_hal.o(.data.uwTickPrio) + __libspace_start 0x20000340 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x200003a0 Data 0 libspace.o(.bss) + ai_cmd 0x20000428 Data 25 ai_1.o(.bss.ai_cmd) + defaultTaskHandle 0x20000450 Data 4 freertos.o(.bss.defaultTaskHandle) + dr16 0x20000458 Data 88 dr16_1.o(.bss.dr16) + eulr_to_send 0x200004b0 Data 12 atti_esti.o(.bss.eulr_to_send) + g_feedback 0x200004bc Data 100 ai_1.o(.bss.g_feedback) + g_rc_cmd 0x20000520 Data 20 remote.o(.bss.g_rc_cmd) + gimbal_cmd 0x20000534 Data 20 gimbal_ctrl.o(.bss.gimbal_cmd) + gimbal_imu 0x20000548 Data 52 gimbal_ctrl.o(.bss.gimbal_imu) + hcan1 0x20000584 Data 40 can.o(.bss.hcan1) + hdma_spi1_tx 0x200005ac Data 96 spi.o(.bss.hdma_spi1_tx) + hi2c2 0x2000060c Data 84 i2c.o(.bss.hi2c2) + htim10 0x20000660 Data 72 tim.o(.bss.htim10) + huart2 0x200006a8 Data 72 usart.o(.bss.huart2) + huart6 0x200006f0 Data 72 usart.o(.bss.huart6) + imu_temp_ctrl_pid 0x20000738 Data 60 atti_esti.o(.bss.imu_temp_ctrl_pid) + shoot_cmd 0x2000082c Data 3 shoot_ctrl.o(.bss.shoot_cmd) + xQueueRegistry 0x2001a888 Data 64 queue.o(.bss.xQueueRegistry) + uwTickFreq 0x2001c000 Data 1 stm32f4xx_hal.o(.data.uwTickFreq) + ai 0x2001c0e4 Data 72 ai_1.o(.bss.ai) + ai_g_cmd 0x2001c12c Data 25 gimbal_ctrl.o(.bss.ai_g_cmd) + bmi088 0x2001c148 Data 48 atti_esti.o(.bss.bmi088) + gimbal 0x2001c198 Data 784 gimbal_ctrl.o(.bss.gimbal) + gimbal_ahrs 0x2001c4a8 Data 20 atti_esti.o(.bss.gimbal_ahrs) + gimbal_cmd_remote 0x2001c4bc Data 20 gimbal_ctrl.o(.bss.gimbal_cmd_remote) + gimbal_to_send 0x2001c4d0 Data 52 atti_esti.o(.bss.gimbal_to_send) + hcan2 0x2001c508 Data 40 can.o(.bss.hcan2) + hdma_spi1_rx 0x2001c530 Data 96 spi.o(.bss.hdma_spi1_rx) + hdma_usart3_rx 0x2001c590 Data 96 usart.o(.bss.hdma_usart3_rx) + hspi1 0x2001c5f0 Data 88 spi.o(.bss.hspi1) + huart1 0x2001c648 Data 72 usart.o(.bss.huart1) + huart3 0x2001c690 Data 72 usart.o(.bss.huart3) + ist8310 0x2001c6e0 Data 32 atti_esti.o(.bss.ist8310) + jiaozhun 0x2001c700 Data 4 atti_esti.o(.bss.jiaozhun) + magn 0x2001c704 Data 12 atti_esti.o(.bss.magn) + pxCurrentTCB 0x2001c760 Data 4 tasks.o(.bss.pxCurrentTCB) + remote_dr16 0x2001cbd0 Data 88 remote.o(.bss.remote_dr16) + s_rc_cmd 0x2001cc28 Data 3 remote.o(.bss.s_rc_cmd) + shoot 0x2001cc30 Data 816 shoot_ctrl.o(.bss.shoot) + task_runtime 0x2001cf60 Data 164 user_task.o(.bss.task_runtime) + uwTick 0x2001d81c Data 4 stm32f4xx_hal.o(.bss.uwTick) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000189 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000e040, Max: 0x00100000, ABSOLUTE, COMPRESSED[0x0000de58]) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000dcf8, Max: 0x00100000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x00000188 Data RO 3 RESET startup_stm32f407xx.o + 0x08000188 0x08000188 0x00000008 Code RO 3256 * !!!main c_w.l(__main.o) + 0x08000190 0x08000190 0x00000034 Code RO 3585 !!!scatter c_w.l(__scatter.o) + 0x080001c4 0x080001c4 0x0000005a Code RO 3583 !!dczerorl2 c_w.l(__dczerorl2.o) + 0x0800021e 0x0800021e 0x00000002 PAD + 0x08000220 0x08000220 0x0000001a Code RO 3587 !!handler_copy c_w.l(__scatter_copy.o) + 0x0800023a 0x0800023a 0x00000002 PAD + 0x0800023c 0x0800023c 0x0000001c Code RO 3589 !!handler_zi c_w.l(__scatter_zi.o) + 0x08000258 0x08000258 0x00000002 Code RO 3503 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x0800025a 0x0800025a 0x00000004 Code RO 3332 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3335 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3338 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3340 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3342 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3345 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3347 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3349 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3351 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3353 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3355 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3357 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3359 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3361 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3363 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3365 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3369 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3371 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3373 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000000 Code RO 3375 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x0800025e 0x0800025e 0x00000002 Code RO 3376 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x08000260 0x08000260 0x00000002 Code RO 3550 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x08000262 0x08000262 0x00000000 Code RO 3566 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000000 Code RO 3568 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000000 Code RO 3571 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000000 Code RO 3574 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000000 Code RO 3576 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000000 Code RO 3579 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x08000262 0x08000262 0x00000002 Code RO 3580 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x08000264 0x08000264 0x00000000 Code RO 3316 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x08000264 0x08000264 0x00000000 Code RO 3450 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x08000264 0x08000264 0x00000006 Code RO 3462 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0800026a 0x0800026a 0x00000000 Code RO 3452 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0800026a 0x0800026a 0x00000004 Code RO 3453 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x0800026e 0x0800026e 0x00000000 Code RO 3455 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x0800026e 0x0800026e 0x00000008 Code RO 3456 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x08000276 0x08000276 0x00000002 Code RO 3508 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x08000278 0x08000278 0x00000000 Code RO 3530 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x08000278 0x08000278 0x00000004 Code RO 3531 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x0800027c 0x0800027c 0x00000006 Code RO 3532 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x08000282 0x08000282 0x00000002 PAD + 0x08000284 0x08000284 0x00000040 Code RO 4 .text startup_stm32f407xx.o + 0x080002c4 0x080002c4 0x000000f0 Code RO 3199 .text c_w.l(lludivv7m.o) + 0x080003b4 0x080003b4 0x0000008a Code RO 3240 .text c_w.l(rt_memcpy_v6.o) + 0x0800043e 0x0800043e 0x00000064 Code RO 3242 .text c_w.l(rt_memcpy_w.o) + 0x080004a2 0x080004a2 0x00000010 Code RO 3246 .text c_w.l(aeabi_memset4.o) + 0x080004b2 0x080004b2 0x0000004e Code RO 3250 .text c_w.l(rt_memclr_w.o) + 0x08000500 0x08000500 0x00000006 Code RO 3254 .text c_w.l(heapauxi.o) + 0x08000506 0x08000506 0x00000016 Code RO 3321 .text c_w.l(_rserrno.o) + 0x0800051c 0x0800051c 0x00000008 Code RO 3469 .text c_w.l(rt_errno_addr_intlibspace.o) + 0x08000524 0x08000524 0x00000008 Code RO 3483 .text c_w.l(libspace.o) + 0x0800052c 0x0800052c 0x0000004a Code RO 3486 .text c_w.l(sys_stackheap_outer.o) + 0x08000576 0x08000576 0x00000012 Code RO 3488 .text c_w.l(exit.o) + 0x08000588 0x08000588 0x0000000c Code RO 3522 .text c_w.l(sys_exit.o) + 0x08000594 0x08000594 0x00000002 Code RO 3526 .text c_w.l(use_no_semi.o) + 0x08000596 0x08000596 0x00000000 Code RO 3528 .text c_w.l(indicate_semi.o) + 0x08000596 0x08000596 0x00000002 PAD + 0x08000598 0x08000598 0x000000dc Code RO 2495 .text.AHRS_GetEulr ahrs.o + 0x08000674 0x08000674 0x00000184 Code RO 2489 .text.AHRS_Init ahrs.o + 0x080007f8 0x080007f8 0x0000000a Code RO 2499 .text.AHRS_ResetEulr ahrs.o + 0x08000802 0x08000802 0x00000002 PAD + 0x08000804 0x08000804 0x0000058e Code RO 2491 .text.AHRS_Update ahrs.o + 0x08000d92 0x08000d92 0x00000002 PAD + 0x08000d94 0x08000d94 0x000002f0 Code RO 2493 .text.AHRS_UpdateIMU ahrs.o + 0x08001084 0x08001084 0x00000054 Code RO 2933 .text.AI_Get_NUC ai.o + 0x080010d8 0x080010d8 0x0000005c Code RO 2935 .text.AI_ParseHost ai.o + 0x08001134 0x08001134 0x0000001a Code RO 2931 .text.AI_StartReceiving ai.o + 0x0800114e 0x0800114e 0x00000002 PAD + 0x08001150 0x08001150 0x00000012 Code RO 2937 .text.AI_StartSend ai.o + 0x08001162 0x08001162 0x00000002 PAD + 0x08001164 0x08001164 0x00000022 Code RO 2697 .text.AbsClip user_math.o + 0x08001186 0x08001186 0x00000002 PAD + 0x08001188 0x08001188 0x00000014 Code RO 2765 .text.BMI088_AcclIntCallback bmi088.o + 0x0800119c 0x0800119c 0x00000018 Code RO 2773 .text.BMI088_AcclStartDmaRecv bmi088.o + 0x080011b4 0x080011b4 0x00000010 Code RO 2777 .text.BMI088_AcclWaitDmaCplt bmi088.o + 0x080011c4 0x080011c4 0x0000000c Code RO 2787 .text.BMI088_GetUpdateFreq bmi088.o + 0x080011d0 0x080011d0 0x00000014 Code RO 2767 .text.BMI088_GyroIntCallback bmi088.o + 0x080011e4 0x080011e4 0x0000001a Code RO 2779 .text.BMI088_GyroStartDmaRecv bmi088.o + 0x080011fe 0x080011fe 0x00000002 PAD + 0x08001200 0x08001200 0x00000010 Code RO 2781 .text.BMI088_GyroWaitDmaCplt bmi088.o + 0x08001210 0x08001210 0x00000142 Code RO 2757 .text.BMI088_Init bmi088.o + 0x08001352 0x08001352 0x00000002 PAD + 0x08001354 0x08001354 0x00000094 Code RO 2783 .text.BMI088_ParseAccl bmi088.o + 0x080013e8 0x080013e8 0x00000084 Code RO 2785 .text.BMI088_ParseGyro bmi088.o + 0x0800146c 0x0800146c 0x00000040 Code RO 2763 .text.BMI088_RxCpltCallback bmi088.o + 0x080014ac 0x080014ac 0x00000010 Code RO 2771 .text.BMI088_WaitNew bmi088.o + 0x080014bc 0x080014bc 0x00000044 Code RO 2775 .text.BMI_Read bmi088.o + 0x08001500 0x08001500 0x0000005e Code RO 2761 .text.BMI_ReadSingle bmi088.o + 0x0800155e 0x0800155e 0x00000002 PAD + 0x08001560 0x08001560 0x00000048 Code RO 2759 .text.BMI_WriteSingle bmi088.o + 0x080015a8 0x080015a8 0x00000092 Code RO 2250 .text.BSP_CAN_CreateIdQueue can_1.o + 0x0800163a 0x0800163a 0x00000002 PAD + 0x0800163c 0x0800163c 0x00000002 Code RO 2226 .text.BSP_CAN_DefaultIdParser can_1.o + 0x0800163e 0x0800163e 0x00000002 PAD + 0x08001640 0x08001640 0x00000026 Code RO 2254 .text.BSP_CAN_FindQueue can_1.o + 0x08001666 0x08001666 0x00000002 PAD + 0x08001668 0x08001668 0x0000001a Code RO 2264 .text.BSP_CAN_GetFrameType can_1.o + 0x08001682 0x08001682 0x00000002 PAD + 0x08001684 0x08001684 0x00000026 Code RO 2236 .text.BSP_CAN_GetHandle can_1.o + 0x080016aa 0x080016aa 0x00000002 PAD + 0x080016ac 0x080016ac 0x00000080 Code RO 2252 .text.BSP_CAN_GetMessage can_1.o + 0x0800172c 0x0800172c 0x00000134 Code RO 2222 .text.BSP_CAN_Init can_1.o + 0x08001860 0x08001860 0x00000014 Code RO 2262 .text.BSP_CAN_ParseId can_1.o + 0x08001874 0x08001874 0x00000044 Code RO 2228 .text.BSP_CAN_RegisterCallback can_1.o + 0x080018b8 0x080018b8 0x0000001e Code RO 2248 .text.BSP_CAN_RegisterId can_1.o + 0x080018d6 0x080018d6 0x00000002 PAD + 0x080018d8 0x080018d8 0x000000c2 Code RO 2230 .text.BSP_CAN_RxFifo0Callback can_1.o + 0x0800199a 0x0800199a 0x00000002 PAD + 0x0800199c 0x0800199c 0x000000c2 Code RO 2234 .text.BSP_CAN_RxFifo1Callback can_1.o + 0x08001a5e 0x08001a5e 0x00000002 PAD + 0x08001a60 0x08001a60 0x000000e2 Code RO 2238 .text.BSP_CAN_Transmit can_1.o + 0x08001b42 0x08001b42 0x00000002 PAD + 0x08001b44 0x08001b44 0x00000028 Code RO 2242 .text.BSP_CAN_TransmitStdDataFrame can_1.o + 0x08001b6c 0x08001b6c 0x00000064 Code RO 2232 .text.BSP_CAN_TxCompleteCallback can_1.o + 0x08001bd0 0x08001bd0 0x0000001c Code RO 2224 .text.BSP_CAN_TxQueueInit can_1.o + 0x08001bec 0x08001bec 0x00000022 Code RO 2266 .text.BSP_CAN_TxQueueIsEmpty can_1.o + 0x08001c0e 0x08001c0e 0x00000002 PAD + 0x08001c10 0x08001c10 0x00000074 Code RO 2268 .text.BSP_CAN_TxQueuePop can_1.o + 0x08001c84 0x08001c84 0x0000007e Code RO 2240 .text.BSP_CAN_TxQueuePush can_1.o + 0x08001d02 0x08001d02 0x00000002 PAD + 0x08001d04 0x08001d04 0x00000008 Code RO 2355 .text.BSP_Free mm.o + 0x08001d0c 0x08001d0c 0x00000030 Code RO 2290 .text.BSP_GPIO_DisableIRQ gpio_1.o + 0x08001d3c 0x08001d3c 0x00000030 Code RO 2288 .text.BSP_GPIO_EnableIRQ gpio_1.o + 0x08001d6c 0x08001d6c 0x0000002c Code RO 2296 .text.BSP_GPIO_ReadPin gpio_1.o + 0x08001d98 0x08001d98 0x0000004a Code RO 2286 .text.BSP_GPIO_RegisterCallback gpio_1.o + 0x08001de2 0x08001de2 0x00000002 PAD + 0x08001de4 0x08001de4 0x00000030 Code RO 2292 .text.BSP_GPIO_WritePin gpio_1.o + 0x08001e14 0x08001e14 0x00000008 Code RO 2353 .text.BSP_Malloc mm.o + 0x08001e1c 0x08001e1c 0x0000005c Code RO 2465 .text.BSP_PWM_SetComp pwm.o + 0x08001e78 0x08001e78 0x0000001e Code RO 2463 .text.BSP_PWM_Start pwm.o + 0x08001e96 0x08001e96 0x00000002 PAD + 0x08001e98 0x08001e98 0x00000012 Code RO 2383 .text.BSP_SPI_GetHandle spi_1.o + 0x08001eaa 0x08001eaa 0x00000002 PAD + 0x08001eac 0x08001eac 0x00000034 Code RO 2389 .text.BSP_SPI_Receive spi_1.o + 0x08001ee0 0x08001ee0 0x0000001e Code RO 2385 .text.BSP_SPI_RegisterCallback spi_1.o + 0x08001efe 0x08001efe 0x00000002 PAD + 0x08001f00 0x08001f00 0x00000034 Code RO 2387 .text.BSP_SPI_Transmit spi_1.o + 0x08001f34 0x08001f34 0x00000058 Code RO 2451 .text.BSP_TIME_Delay_ms time.o + 0x08001f8c 0x08001f8c 0x00000050 Code RO 2449 .text.BSP_TIME_Get_us time.o + 0x08001fdc 0x08001fdc 0x00000020 Code RO 2430 .text.BSP_UART_GetHandle uart.o + 0x08001ffc 0x08001ffc 0x0000003a Code RO 2428 .text.BSP_UART_IRQHandler uart.o + 0x08002036 0x08002036 0x00000002 PAD + 0x08002038 0x08002038 0x00000040 Code RO 2436 .text.BSP_UART_Receive uart.o + 0x08002078 0x08002078 0x00000032 Code RO 2432 .text.BSP_UART_RegisterCallback uart.o + 0x080020aa 0x080020aa 0x00000002 PAD + 0x080020ac 0x080020ac 0x00000040 Code RO 2434 .text.BSP_UART_Transmit uart.o + 0x080020ec 0x080020ec 0x00000002 Code RO 156 .text.BusFault_Handler stm32f4xx_it.o + 0x080020ee 0x080020ee 0x00000002 PAD + 0x080020f0 0x080020f0 0x00000010 Code RO 174 .text.CAN1_RX0_IRQHandler stm32f4xx_it.o + 0x08002100 0x08002100 0x00000010 Code RO 176 .text.CAN1_RX1_IRQHandler stm32f4xx_it.o + 0x08002110 0x08002110 0x00000010 Code RO 178 .text.CAN1_SCE_IRQHandler stm32f4xx_it.o + 0x08002120 0x08002120 0x00000010 Code RO 172 .text.CAN1_TX_IRQHandler stm32f4xx_it.o + 0x08002130 0x08002130 0x00000010 Code RO 192 .text.CAN2_RX1_IRQHandler stm32f4xx_it.o + 0x08002140 0x08002140 0x00000010 Code RO 194 .text.CAN2_SCE_IRQHandler stm32f4xx_it.o + 0x08002150 0x08002150 0x00000010 Code RO 190 .text.CAN2_TX_IRQHandler stm32f4xx_it.o + 0x08002160 0x08002160 0x00000024 Code RO 2196 .text.CAN_Get can_1.o + 0x08002184 0x08002184 0x00000016 Code RO 2537 .text.CRC16_Byte crc16.o + 0x0800219a 0x0800219a 0x00000002 PAD + 0x0800219c 0x0800219c 0x0000001e Code RO 2535 .text.CRC16_Calc crc16.o + 0x080021ba 0x080021ba 0x00000002 PAD + 0x080021bc 0x080021bc 0x00000032 Code RO 2539 .text.CRC16_Verify crc16.o + 0x080021ee 0x080021ee 0x00000002 PAD + 0x080021f0 0x080021f0 0x0000003a Code RO 2709 .text.CircleAdd user_math.o + 0x0800222a 0x0800222a 0x00000002 PAD + 0x0800222c 0x0800222c 0x0000003c Code RO 2707 .text.CircleError user_math.o + 0x08002268 0x08002268 0x00000026 Code RO 2701 .text.Clip user_math.o + 0x0800228e 0x0800228e 0x00000002 PAD + 0x08002290 0x08002290 0x0000000a Code RO 3090 .text.Config_GetRobotParam config.o + 0x0800229a 0x0800229a 0x00000002 PAD + 0x0800229c 0x0800229c 0x00000010 Code RO 170 .text.DMA1_Stream1_IRQHandler stm32f4xx_it.o + 0x080022ac 0x080022ac 0x00000010 Code RO 186 .text.DMA2_Stream2_IRQHandler stm32f4xx_it.o + 0x080022bc 0x080022bc 0x00000010 Code RO 188 .text.DMA2_Stream3_IRQHandler stm32f4xx_it.o + 0x080022cc 0x080022cc 0x0000003c Code RO 478 .text.DMA_CalcBaseAndBitshift stm32f4xx_hal_dma.o + 0x08002308 0x08002308 0x00000050 Code RO 476 .text.DMA_CheckFifoParam stm32f4xx_hal_dma.o + 0x08002358 0x08002358 0x00000030 Code RO 484 .text.DMA_SetConfig stm32f4xx_hal_dma.o + 0x08002388 0x08002388 0x0000006e Code RO 2959 .text.DR16_DataCorrupted dr16.o + 0x080023f6 0x080023f6 0x00000002 PAD + 0x080023f8 0x080023f8 0x00000046 Code RO 2947 .text.DR16_Init dr16.o + 0x0800243e 0x0800243e 0x00000002 PAD + 0x08002440 0x08002440 0x0000001a Code RO 2961 .text.DR16_Offline dr16.o + 0x0800245a 0x0800245a 0x00000002 PAD + 0x0800245c 0x0800245c 0x00000134 Code RO 2957 .text.DR16_ParseData dr16.o + 0x08002590 0x08002590 0x00000014 Code RO 2949 .text.DR16_RxCpltCallback dr16.o + 0x080025a4 0x080025a4 0x0000001e Code RO 2953 .text.DR16_StartDmaRecv dr16.o + 0x080025c2 0x080025c2 0x00000002 PAD + 0x080025c4 0x080025c4 0x00000016 Code RO 2955 .text.DR16_WaitDmaCplt dr16.o + 0x080025da 0x080025da 0x00000002 PAD + 0x080025dc 0x080025dc 0x00000002 Code RO 160 .text.DebugMon_Handler stm32f4xx_it.o + 0x080025de 0x080025de 0x00000002 PAD + 0x080025e0 0x080025e0 0x0000000a Code RO 164 .text.EXTI0_IRQHandler stm32f4xx_it.o + 0x080025ea 0x080025ea 0x00000002 PAD + 0x080025ec 0x080025ec 0x0000000a Code RO 166 .text.EXTI3_IRQHandler stm32f4xx_it.o + 0x080025f6 0x080025f6 0x00000002 PAD + 0x080025f8 0x080025f8 0x0000000a Code RO 168 .text.EXTI4_IRQHandler stm32f4xx_it.o + 0x08002602 0x08002602 0x00000002 PAD + 0x08002604 0x08002604 0x0000000a Code RO 180 .text.EXTI9_5_IRQHandler stm32f4xx_it.o + 0x0800260e 0x0800260e 0x00000002 PAD + 0x08002610 0x08002610 0x00000006 Code RO 15 .text.Error_Handler main.o + 0x08002616 0x08002616 0x00000002 PAD + 0x08002618 0x08002618 0x000000a8 Code RO 3151 .text.Gimbal_Cmd remote_cmd.o + 0x080026c0 0x080026c0 0x000003a0 Code RO 3135 .text.Gimbal_Control gimbal.o + 0x08002a60 0x08002a60 0x00000058 Code RO 3133 .text.Gimbal_Control_mode gimbal.o + 0x08002ab8 0x08002ab8 0x000000a4 Code RO 3129 .text.Gimbal_Direction gimbal.o + 0x08002b5c 0x08002b5c 0x00000150 Code RO 3123 .text.Gimbal_Init gimbal.o + 0x08002cac 0x08002cac 0x00000118 Code RO 3141 .text.Gimbal_Output gimbal.o + 0x08002dc4 0x08002dc4 0x00000088 Code RO 3137 .text.Gimbal_SetMode gimbal.o + 0x08002e4c 0x08002e4c 0x00000118 Code RO 3125 .text.Gimbal_UpdateFeedback gimbal.o + 0x08002f64 0x08002f64 0x0000004e Code RO 3127 .text.Gimbal_UpdateIMU gimbal.o + 0x08002fb2 0x08002fb2 0x00000002 PAD + 0x08002fb4 0x08002fb4 0x00000026 Code RO 248 .text.HAL_CAN_ActivateNotification stm32f4xx_hal_can.o + 0x08002fda 0x08002fda 0x00000002 PAD + 0x08002fdc 0x08002fdc 0x00000092 Code RO 234 .text.HAL_CAN_AddTxMessage stm32f4xx_hal_can.o + 0x0800306e 0x0800306e 0x00000002 PAD + 0x08003070 0x08003070 0x000000de Code RO 224 .text.HAL_CAN_ConfigFilter stm32f4xx_hal_can.o + 0x0800314e 0x0800314e 0x00000002 PAD + 0x08003150 0x08003150 0x00000024 Code RO 2220 .text.HAL_CAN_ErrorCallback can_1.o + 0x08003174 0x08003174 0x00000020 Code RO 246 .text.HAL_CAN_GetRxFifoFillLevel stm32f4xx_hal_can.o + 0x08003194 0x08003194 0x00000124 Code RO 244 .text.HAL_CAN_GetRxMessage stm32f4xx_hal_can.o + 0x080032b8 0x080032b8 0x00000028 Code RO 238 .text.HAL_CAN_GetTxMailboxesFreeLevel stm32f4xx_hal_can.o + 0x080032e0 0x080032e0 0x0000023a Code RO 252 .text.HAL_CAN_IRQHandler stm32f4xx_hal_can.o + 0x0800351a 0x0800351a 0x00000002 PAD + 0x0800351c 0x0800351c 0x000000f4 Code RO 214 .text.HAL_CAN_Init stm32f4xx_hal_can.o + 0x08003610 0x08003610 0x0000016a Code RO 52 .text.HAL_CAN_MspInit can.o + 0x0800377a 0x0800377a 0x00000002 PAD + 0x0800377c 0x0800377c 0x00000024 Code RO 2210 .text.HAL_CAN_RxFifo0FullCallback can_1.o + 0x080037a0 0x080037a0 0x00000024 Code RO 2208 .text.HAL_CAN_RxFifo0MsgPendingCallback can_1.o + 0x080037c4 0x080037c4 0x00000024 Code RO 2214 .text.HAL_CAN_RxFifo1FullCallback can_1.o + 0x080037e8 0x080037e8 0x00000024 Code RO 2212 .text.HAL_CAN_RxFifo1MsgPendingCallback can_1.o + 0x0800380c 0x0800380c 0x00000024 Code RO 2216 .text.HAL_CAN_SleepCallback can_1.o + 0x08003830 0x08003830 0x0000005a Code RO 226 .text.HAL_CAN_Start stm32f4xx_hal_can.o + 0x0800388a 0x0800388a 0x00000002 PAD + 0x0800388c 0x0800388c 0x00000024 Code RO 2202 .text.HAL_CAN_TxMailbox0AbortCallback can_1.o + 0x080038b0 0x080038b0 0x00000022 Code RO 2194 .text.HAL_CAN_TxMailbox0CompleteCallback can_1.o + 0x080038d2 0x080038d2 0x00000002 PAD + 0x080038d4 0x080038d4 0x00000024 Code RO 2204 .text.HAL_CAN_TxMailbox1AbortCallback can_1.o + 0x080038f8 0x080038f8 0x00000024 Code RO 2198 .text.HAL_CAN_TxMailbox1CompleteCallback can_1.o + 0x0800391c 0x0800391c 0x00000024 Code RO 2206 .text.HAL_CAN_TxMailbox2AbortCallback can_1.o + 0x08003940 0x08003940 0x00000024 Code RO 2200 .text.HAL_CAN_TxMailbox2CompleteCallback can_1.o + 0x08003964 0x08003964 0x00000024 Code RO 2218 .text.HAL_CAN_WakeUpFromRxMsgCallback can_1.o + 0x08003988 0x08003988 0x00000080 Code RO 488 .text.HAL_DMA_Abort stm32f4xx_hal_dma.o + 0x08003a08 0x08003a08 0x00000024 Code RO 490 .text.HAL_DMA_Abort_IT stm32f4xx_hal_dma.o + 0x08003a2c 0x08003a2c 0x0000018c Code RO 494 .text.HAL_DMA_IRQHandler stm32f4xx_hal_dma.o + 0x08003bb8 0x08003bb8 0x000000ce Code RO 474 .text.HAL_DMA_Init stm32f4xx_hal_dma.o + 0x08003c86 0x08003c86 0x00000002 PAD + 0x08003c88 0x08003c88 0x00000062 Code RO 486 .text.HAL_DMA_Start_IT stm32f4xx_hal_dma.o + 0x08003cea 0x08003cea 0x00000002 PAD + 0x08003cec 0x08003cec 0x00000028 Code RO 672 .text.HAL_Delay stm32f4xx_hal.o + 0x08003d14 0x08003d14 0x0000002c Code RO 2284 .text.HAL_GPIO_EXTI_Callback gpio_1.o + 0x08003d40 0x08003d40 0x0000001a Code RO 446 .text.HAL_GPIO_EXTI_IRQHandler stm32f4xx_hal_gpio.o + 0x08003d5a 0x08003d5a 0x00000002 PAD + 0x08003d5c 0x08003d5c 0x0000019a Code RO 434 .text.HAL_GPIO_Init stm32f4xx_hal_gpio.o + 0x08003ef6 0x08003ef6 0x00000002 PAD + 0x08003ef8 0x08003ef8 0x0000000a Code RO 438 .text.HAL_GPIO_ReadPin stm32f4xx_hal_gpio.o + 0x08003f02 0x08003f02 0x00000002 PAD + 0x08003f04 0x08003f04 0x0000000a Code RO 440 .text.HAL_GPIO_WritePin stm32f4xx_hal_gpio.o + 0x08003f0e 0x08003f0e 0x00000002 PAD + 0x08003f10 0x08003f10 0x0000000c Code RO 664 .text.HAL_GetTick stm32f4xx_hal.o + 0x08003f1c 0x08003f1c 0x00000198 Code RO 743 .text.HAL_I2C_Init stm32f4xx_hal_i2c.o + 0x080040b4 0x080040b4 0x00000070 Code RO 78 .text.HAL_I2C_MspInit i2c.o + 0x08004124 0x08004124 0x0000001a Code RO 662 .text.HAL_IncTick stm32f4xx_hal.o + 0x0800413e 0x0800413e 0x00000002 PAD + 0x08004140 0x08004140 0x00000036 Code RO 652 .text.HAL_Init stm32f4xx_hal.o + 0x08004176 0x08004176 0x00000002 PAD + 0x08004178 0x08004178 0x00000050 Code RO 654 .text.HAL_InitTick stm32f4xx_hal.o + 0x080041c8 0x080041c8 0x00000046 Code RO 205 .text.HAL_MspInit stm32f4xx_hal_msp.o + 0x0800420e 0x0800420e 0x00000002 PAD + 0x08004210 0x08004210 0x00000008 Code RO 590 .text.HAL_NVIC_DisableIRQ stm32f4xx_hal_cortex.o + 0x08004218 0x08004218 0x00000008 Code RO 586 .text.HAL_NVIC_EnableIRQ stm32f4xx_hal_cortex.o + 0x08004220 0x08004220 0x0000001e Code RO 578 .text.HAL_NVIC_SetPriority stm32f4xx_hal_cortex.o + 0x0800423e 0x0800423e 0x00000002 PAD + 0x08004240 0x08004240 0x00000008 Code RO 574 .text.HAL_NVIC_SetPriorityGrouping stm32f4xx_hal_cortex.o + 0x08004248 0x08004248 0x00000160 Code RO 298 .text.HAL_RCC_ClockConfig stm32f4xx_hal_rcc.o + 0x080043a8 0x080043a8 0x0000000c Code RO 308 .text.HAL_RCC_GetHCLKFreq stm32f4xx_hal_rcc.o + 0x080043b4 0x080043b4 0x00000022 Code RO 310 .text.HAL_RCC_GetPCLK1Freq stm32f4xx_hal_rcc.o + 0x080043d6 0x080043d6 0x00000002 PAD + 0x080043d8 0x080043d8 0x00000022 Code RO 312 .text.HAL_RCC_GetPCLK2Freq stm32f4xx_hal_rcc.o + 0x080043fa 0x080043fa 0x00000002 PAD + 0x080043fc 0x080043fc 0x00000068 Code RO 300 .text.HAL_RCC_GetSysClockFreq stm32f4xx_hal_rcc.o + 0x08004464 0x08004464 0x00000348 Code RO 296 .text.HAL_RCC_OscConfig stm32f4xx_hal_rcc.o + 0x080047ac 0x080047ac 0x00000022 Code RO 2379 .text.HAL_SPI_ErrorCallback spi_1.o + 0x080047ce 0x080047ce 0x00000002 PAD + 0x080047d0 0x080047d0 0x000000b4 Code RO 916 .text.HAL_SPI_Init stm32f4xx_hal_spi.o + 0x08004884 0x08004884 0x0000012e Code RO 93 .text.HAL_SPI_MspInit spi.o + 0x080049b2 0x080049b2 0x00000002 PAD + 0x080049b4 0x080049b4 0x00000172 Code RO 928 .text.HAL_SPI_Receive stm32f4xx_hal_spi.o + 0x08004b26 0x08004b26 0x00000002 PAD + 0x08004b28 0x08004b28 0x000000ec Code RO 964 .text.HAL_SPI_Receive_DMA stm32f4xx_hal_spi.o + 0x08004c14 0x08004c14 0x00000022 Code RO 2369 .text.HAL_SPI_RxCpltCallback spi_1.o + 0x08004c36 0x08004c36 0x00000002 PAD + 0x08004c38 0x08004c38 0x00000022 Code RO 2375 .text.HAL_SPI_RxHalfCpltCallback spi_1.o + 0x08004c5a 0x08004c5a 0x00000002 PAD + 0x08004c5c 0x08004c5c 0x0000018a Code RO 924 .text.HAL_SPI_Transmit stm32f4xx_hal_spi.o + 0x08004de6 0x08004de6 0x00000002 PAD + 0x08004de8 0x08004de8 0x000001f8 Code RO 930 .text.HAL_SPI_TransmitReceive stm32f4xx_hal_spi.o + 0x08004fe0 0x08004fe0 0x00000124 Code RO 966 .text.HAL_SPI_TransmitReceive_DMA stm32f4xx_hal_spi.o + 0x08005104 0x08005104 0x000000cc Code RO 956 .text.HAL_SPI_Transmit_DMA stm32f4xx_hal_spi.o + 0x080051d0 0x080051d0 0x00000020 Code RO 2365 .text.HAL_SPI_TxCpltCallback spi_1.o + 0x080051f0 0x080051f0 0x00000022 Code RO 2373 .text.HAL_SPI_TxHalfCpltCallback spi_1.o + 0x08005212 0x08005212 0x00000002 PAD + 0x08005214 0x08005214 0x00000022 Code RO 2371 .text.HAL_SPI_TxRxCpltCallback spi_1.o + 0x08005236 0x08005236 0x00000002 PAD + 0x08005238 0x08005238 0x00000022 Code RO 2377 .text.HAL_SPI_TxRxHalfCpltCallback spi_1.o + 0x0800525a 0x0800525a 0x00000002 PAD + 0x0800525c 0x0800525c 0x00000008 Code RO 598 .text.HAL_SYSTICK_Config stm32f4xx_hal_cortex.o + 0x08005264 0x08005264 0x0000005a Code RO 1034 .text.HAL_TIM_Base_Init stm32f4xx_hal_tim.o + 0x080052be 0x080052be 0x00000002 PAD + 0x080052c0 0x080052c0 0x00000036 Code RO 112 .text.HAL_TIM_Base_MspInit tim.o + 0x080052f6 0x080052f6 0x00000002 PAD + 0x080052f8 0x080052f8 0x0000005e Code RO 110 .text.HAL_TIM_MspPostInit tim.o + 0x08005356 0x08005356 0x00000002 PAD + 0x08005358 0x08005358 0x00000098 Code RO 1200 .text.HAL_TIM_PWM_ConfigChannel stm32f4xx_hal_tim.o + 0x080053f0 0x080053f0 0x0000005a Code RO 1088 .text.HAL_TIM_PWM_Init stm32f4xx_hal_tim.o + 0x0800544a 0x0800544a 0x00000002 PAD + 0x0800544c 0x0800544c 0x00000002 Code RO 1090 .text.HAL_TIM_PWM_MspInit stm32f4xx_hal_tim.o + 0x0800544e 0x0800544e 0x00000002 PAD + 0x08005450 0x08005450 0x00000122 Code RO 1096 .text.HAL_TIM_PWM_Start stm32f4xx_hal_tim.o + 0x08005572 0x08005572 0x00000002 PAD + 0x08005574 0x08005574 0x00000002 Code RO 1464 .text.HAL_UARTEx_RxEventCallback stm32f4xx_hal_uart.o + 0x08005576 0x08005576 0x00000002 PAD + 0x08005578 0x08005578 0x00000026 Code RO 2420 .text.HAL_UART_ErrorCallback uart.o + 0x0800559e 0x0800559e 0x00000002 PAD + 0x080055a0 0x080055a0 0x0000025a Code RO 1456 .text.HAL_UART_IRQHandler stm32f4xx_hal_uart.o + 0x080057fa 0x080057fa 0x00000002 PAD + 0x080057fc 0x080057fc 0x00000060 Code RO 1372 .text.HAL_UART_Init stm32f4xx_hal_uart.o + 0x0800585c 0x0800585c 0x00000266 Code RO 133 .text.HAL_UART_MspInit usart.o + 0x08005ac2 0x08005ac2 0x00000002 PAD + 0x08005ac4 0x08005ac4 0x0000002c Code RO 1408 .text.HAL_UART_Receive_DMA stm32f4xx_hal_uart.o + 0x08005af0 0x08005af0 0x0000002a Code RO 1396 .text.HAL_UART_Receive_IT stm32f4xx_hal_uart.o + 0x08005b1a 0x08005b1a 0x00000002 PAD + 0x08005b1c 0x08005b1c 0x00000026 Code RO 2416 .text.HAL_UART_RxCpltCallback uart.o + 0x08005b42 0x08005b42 0x00000002 PAD + 0x08005b44 0x08005b44 0x00000026 Code RO 2418 .text.HAL_UART_RxHalfCpltCallback uart.o + 0x08005b6a 0x08005b6a 0x00000002 PAD + 0x08005b6c 0x08005b6c 0x0000008c Code RO 1400 .text.HAL_UART_Transmit_DMA stm32f4xx_hal_uart.o + 0x08005bf8 0x08005bf8 0x00000038 Code RO 1394 .text.HAL_UART_Transmit_IT stm32f4xx_hal_uart.o + 0x08005c30 0x08005c30 0x00000026 Code RO 2410 .text.HAL_UART_TxCpltCallback uart.o + 0x08005c56 0x08005c56 0x00000002 PAD + 0x08005c58 0x08005c58 0x00000024 Code RO 2414 .text.HAL_UART_TxHalfCpltCallback uart.o + 0x08005c7c 0x08005c7c 0x00000002 Code RO 152 .text.HardFault_Handler stm32f4xx_it.o + 0x08005c7e 0x08005c7e 0x00000002 PAD + 0x08005c80 0x08005c80 0x00000042 Code RO 2695 .text.InvSqrt user_math.o + 0x08005cc2 0x08005cc2 0x00000002 PAD + 0x08005cc4 0x08005cc4 0x0000007c Code RO 2573 .text.LowPassFilter2p_Apply filter.o + 0x08005d40 0x08005d40 0x000000a4 Code RO 2571 .text.LowPassFilter2p_Init filter.o + 0x08005de4 0x08005de4 0x0000005c Code RO 2577 .text.LowPassFilter2p_Reset filter.o + 0x08005e40 0x08005e40 0x0000003c Code RO 2886 .text.MOTOR_DM_CreateCANManager motor_dm.o + 0x08005e7c 0x08005e7c 0x00000046 Code RO 2910 .text.MOTOR_DM_Enable motor_dm.o + 0x08005ec2 0x08005ec2 0x00000002 PAD + 0x08005ec4 0x08005ec4 0x00000014 Code RO 2888 .text.MOTOR_DM_GetCANManager motor_dm.o + 0x08005ed8 0x08005ed8 0x00000058 Code RO 2898 .text.MOTOR_DM_GetMotor motor_dm.o + 0x08005f30 0x08005f30 0x0000002e Code RO 2896 .text.MOTOR_DM_MITCtrl motor_dm.o + 0x08005f5e 0x08005f5e 0x00000002 PAD + 0x08005f60 0x08005f60 0x000000f8 Code RO 2892 .text.MOTOR_DM_ParseFeedbackFrame motor_dm.o + 0x08006058 0x08006058 0x000000a4 Code RO 2884 .text.MOTOR_DM_Register motor_dm.o + 0x080060fc 0x080060fc 0x00000118 Code RO 2900 .text.MOTOR_DM_SendMITCmd motor_dm.o + 0x08006214 0x08006214 0x000000a0 Code RO 2890 .text.MOTOR_DM_Update motor_dm.o + 0x080062b4 0x080062b4 0x0000003c Code RO 2849 .text.MOTOR_RM_CreateCANManager motor_rm.o + 0x080062f0 0x080062f0 0x000000d8 Code RO 2867 .text.MOTOR_RM_Ctrl motor_rm.o + 0x080063c8 0x080063c8 0x00000014 Code RO 2851 .text.MOTOR_RM_GetCANManager motor_rm.o + 0x080063dc 0x080063dc 0x00000026 Code RO 2865 .text.MOTOR_RM_GetLSB motor_rm.o + 0x08006402 0x08006402 0x00000002 PAD + 0x08006404 0x08006404 0x00000028 Code RO 2863 .text.MOTOR_RM_GetLogicalIndex motor_rm.o + 0x0800642c 0x0800642c 0x00000050 Code RO 2861 .text.MOTOR_RM_GetMotor motor_rm.o + 0x0800647c 0x0800647c 0x00000024 Code RO 2873 .text.MOTOR_RM_GetRatio motor_rm.o + 0x080064a0 0x080064a0 0x000000a6 Code RO 2847 .text.MOTOR_RM_Register motor_rm.o + 0x08006546 0x08006546 0x00000002 PAD + 0x08006548 0x08006548 0x00000010 Code RO 2869 .text.MOTOR_RM_Relax motor_rm.o + 0x08006558 0x08006558 0x0000009e Code RO 2859 .text.MOTOR_RM_SetOutput motor_rm.o + 0x080065f6 0x080065f6 0x00000002 PAD + 0x080065f8 0x080065f8 0x000000c6 Code RO 2853 .text.MOTOR_RM_Update motor_rm.o + 0x080066be 0x080066be 0x00000002 PAD + 0x080066c0 0x080066c0 0x00000040 Code RO 48 .text.MX_CAN1_Init can.o + 0x08006700 0x08006700 0x00000040 Code RO 50 .text.MX_CAN2_Init can.o + 0x08006740 0x08006740 0x0000006a Code RO 67 .text.MX_DMA_Init dma.o + 0x080067aa 0x080067aa 0x00000002 PAD + 0x080067ac 0x080067ac 0x0000003a Code RO 34 .text.MX_FREERTOS_Init freertos.o + 0x080067e6 0x080067e6 0x00000002 PAD + 0x080067e8 0x080067e8 0x00000188 Code RO 25 .text.MX_GPIO_Init gpio.o + 0x08006970 0x08006970 0x0000003e Code RO 76 .text.MX_I2C2_Init i2c.o + 0x080069ae 0x080069ae 0x00000002 PAD + 0x080069b0 0x080069b0 0x0000004e Code RO 91 .text.MX_SPI1_Init spi.o + 0x080069fe 0x080069fe 0x00000002 PAD + 0x08006a00 0x08006a00 0x00000088 Code RO 108 .text.MX_TIM10_Init tim.o + 0x08006a88 0x08006a88 0x00000038 Code RO 125 .text.MX_USART1_UART_Init usart.o + 0x08006ac0 0x08006ac0 0x00000038 Code RO 127 .text.MX_USART2_UART_Init usart.o + 0x08006af8 0x08006af8 0x00000042 Code RO 129 .text.MX_USART3_UART_Init usart.o + 0x08006b3a 0x08006b3a 0x00000002 PAD + 0x08006b3c 0x08006b3c 0x00000038 Code RO 131 .text.MX_USART6_UART_Init usart.o + 0x08006b74 0x08006b74 0x00000002 Code RO 154 .text.MemManage_Handler stm32f4xx_it.o + 0x08006b76 0x08006b76 0x00000002 PAD + 0x08006b78 0x08006b78 0x0000015c Code RO 2855 .text.Motor_RM_Decode motor_rm.o + 0x08006cd4 0x08006cd4 0x00000002 Code RO 150 .text.NMI_Handler stm32f4xx_it.o + 0x08006cd6 0x08006cd6 0x00000002 PAD + 0x08006cd8 0x08006cd8 0x0000002c Code RO 584 .text.NVIC_EncodePriority stm32f4xx_hal_cortex.o + 0x08006d04 0x08006d04 0x00000170 Code RO 2656 .text.PID_Calc pid.o + 0x08006e74 0x08006e74 0x00000090 Code RO 2650 .text.PID_Init pid.o + 0x08006f04 0x08006f04 0x0000002c Code RO 2654 .text.PID_Reset pid.o + 0x08006f30 0x08006f30 0x0000000e Code RO 2658 .text.PID_ResetIntegral pid.o + 0x08006f3e 0x08006f3e 0x00000002 PAD + 0x08006f40 0x08006f40 0x00000064 Code RO 2177 .text.PendSV_Handler port.o + 0x08006fa4 0x08006fa4 0x00000022 Code RO 962 .text.SPI_DMAError stm32f4xx_hal_spi.o + 0x08006fc6 0x08006fc6 0x00000002 PAD + 0x08006fc8 0x08006fc8 0x0000000a Code RO 968 .text.SPI_DMAHalfReceiveCplt stm32f4xx_hal_spi.o + 0x08006fd2 0x08006fd2 0x00000002 PAD + 0x08006fd4 0x08006fd4 0x0000000a Code RO 958 .text.SPI_DMAHalfTransmitCplt stm32f4xx_hal_spi.o + 0x08006fde 0x08006fde 0x00000002 PAD + 0x08006fe0 0x08006fe0 0x0000000a Code RO 972 .text.SPI_DMAHalfTransmitReceiveCplt stm32f4xx_hal_spi.o + 0x08006fea 0x08006fea 0x00000002 PAD + 0x08006fec 0x08006fec 0x00000068 Code RO 970 .text.SPI_DMAReceiveCplt stm32f4xx_hal_spi.o + 0x08007054 0x08007054 0x00000070 Code RO 960 .text.SPI_DMATransmitCplt stm32f4xx_hal_spi.o + 0x080070c4 0x080070c4 0x0000005a Code RO 974 .text.SPI_DMATransmitReceiveCplt stm32f4xx_hal_spi.o + 0x0800711e 0x0800711e 0x00000002 PAD + 0x08007120 0x08007120 0x00000090 Code RO 932 .text.SPI_EndRxTransaction stm32f4xx_hal_spi.o + 0x080071b0 0x080071b0 0x0000008a Code RO 926 .text.SPI_EndRxTxTransaction stm32f4xx_hal_spi.o + 0x0800723a 0x0800723a 0x00000002 PAD + 0x0800723c 0x0800723c 0x00000014 Code RO 2367 .text.SPI_Get spi_1.o + 0x08007250 0x08007250 0x000000e0 Code RO 1024 .text.SPI_WaitFlagStateUntilTimeout stm32f4xx_hal_spi.o + 0x08007330 0x08007330 0x00000024 Code RO 2161 .text.SVC_Handler port.o + 0x08007354 0x08007354 0x00000008 Code RO 1955 .text.SVC_Setup cmsis_os2.o + 0x0800735c 0x0800735c 0x00000036 Code RO 2715 .text.ScaleSumTo1 user_math.o + 0x08007392 0x08007392 0x00000002 PAD + 0x08007394 0x08007394 0x0000007c Code RO 3179 .text.Shoot_CaluCoupledWeight shoot.o + 0x08007410 0x08007410 0x000000a0 Code RO 3173 .text.Shoot_CaluTargetAngle shoot.o + 0x080074b0 0x080074b0 0x0000002c Code RO 3171 .text.Shoot_CaluTargetRPM shoot.o + 0x080074dc 0x080074dc 0x00000028 Code RO 3153 .text.Shoot_Cmd remote_cmd.o + 0x08007504 0x08007504 0x0000006c Code RO 3185 .text.Shoot_Control shoot.o + 0x08007570 0x08007570 0x00000146 Code RO 3183 .text.Shoot_Init shoot.o + 0x080076b6 0x080076b6 0x00000002 PAD + 0x080076b8 0x080076b8 0x00000130 Code RO 3181 .text.Shoot_JamDetectionFSM shoot.o + 0x080077e8 0x080077e8 0x00000098 Code RO 3167 .text.Shoot_ResetCalu shoot.o + 0x08007880 0x08007880 0x00000046 Code RO 3165 .text.Shoot_ResetIntegral shoot.o + 0x080078c6 0x080078c6 0x00000002 PAD + 0x080078c8 0x080078c8 0x00000032 Code RO 3169 .text.Shoot_ResetOutput shoot.o + 0x080078fa 0x080078fa 0x00000002 PAD + 0x080078fc 0x080078fc 0x000004f0 Code RO 3177 .text.Shoot_RunningFSM shoot.o + 0x08007dec 0x08007dec 0x0000000e Code RO 3163 .text.Shoot_SetMode shoot.o + 0x08007dfa 0x08007dfa 0x00000002 PAD + 0x08007dfc 0x08007dfc 0x000001d4 Code RO 3175 .text.Shoot_UpdateFeedback shoot.o + 0x08007fd0 0x08007fd0 0x0000000c Code RO 36 .text.StartDefaultTask freertos.o + 0x08007fdc 0x08007fdc 0x0000002e Code RO 600 .text.SysTick_Config stm32f4xx_hal_cortex.o + 0x0800800a 0x0800800a 0x00000002 PAD + 0x0800800c 0x0800800c 0x00000014 Code RO 162 .text.SysTick_Handler stm32f4xx_it.o + 0x08008020 0x08008020 0x000000a4 Code RO 13 .text.SystemClock_Config main.o + 0x080080c4 0x080080c4 0x00000012 Code RO 1504 .text.SystemInit system_stm32f4xx.o + 0x080080d6 0x080080d6 0x00000002 PAD + 0x080080d8 0x080080d8 0x0000012c Code RO 1038 .text.TIM_Base_SetConfig stm32f4xx_hal_tim.o + 0x08008204 0x08008204 0x00000024 Code RO 1072 .text.TIM_CCxChannelCmd stm32f4xx_hal_tim.o + 0x08008228 0x08008228 0x00000064 Code RO 1182 .text.TIM_OC1_SetConfig stm32f4xx_hal_tim.o + 0x0800828c 0x0800828c 0x0000006a Code RO 1184 .text.TIM_OC2_SetConfig stm32f4xx_hal_tim.o + 0x080082f6 0x080082f6 0x00000002 PAD + 0x080082f8 0x080082f8 0x00000068 Code RO 1186 .text.TIM_OC3_SetConfig stm32f4xx_hal_tim.o + 0x08008360 0x08008360 0x0000004e Code RO 1188 .text.TIM_OC4_SetConfig stm32f4xx_hal_tim.o + 0x080083ae 0x080083ae 0x00000002 PAD + 0x080083b0 0x080083b0 0x00000124 Code RO 2973 .text.Task_Init init.o + 0x080084d4 0x080084d4 0x00000004 PAD + 0x080084d8 0x080084d8 0x000000a0 Code RO 2982 .text.Task_ai ai_1.o + 0x08008578 0x08008578 0x00000264 Code RO 2994 .text.Task_atti_esti atti_esti.o + 0x080087dc 0x080087dc 0x00000004 PAD + 0x080087e0 0x080087e0 0x00000040 Code RO 3017 .text.Task_chassis_ctrl chassis_ctrl.o + 0x08008820 0x08008820 0x00000080 Code RO 3026 .text.Task_dr16 dr16_1.o + 0x080088a0 0x080088a0 0x00000154 Code RO 3036 .text.Task_gimbal_ctrl gimbal_ctrl.o + 0x080089f4 0x080089f4 0x00000004 PAD + 0x080089f8 0x080089f8 0x000000a0 Code RO 3078 .text.Task_remote remote.o + 0x08008a98 0x08008a98 0x0000009c Code RO 3052 .text.Task_shoot_ctrl shoot_ctrl.o + 0x08008b34 0x08008b34 0x0000000e Code RO 1460 .text.UART_DMAAbortOnError stm32f4xx_hal_uart.o + 0x08008b42 0x08008b42 0x00000002 PAD + 0x08008b44 0x08008b44 0x0000004c Code RO 1406 .text.UART_DMAError stm32f4xx_hal_uart.o + 0x08008b90 0x08008b90 0x00000084 Code RO 1492 .text.UART_DMAReceiveCplt stm32f4xx_hal_uart.o + 0x08008c14 0x08008c14 0x0000001e Code RO 1494 .text.UART_DMARxHalfCplt stm32f4xx_hal_uart.o + 0x08008c32 0x08008c32 0x00000002 PAD + 0x08008c34 0x08008c34 0x00000040 Code RO 1402 .text.UART_DMATransmitCplt stm32f4xx_hal_uart.o + 0x08008c74 0x08008c74 0x0000000a Code RO 1404 .text.UART_DMATxHalfCplt stm32f4xx_hal_uart.o + 0x08008c7e 0x08008c7e 0x00000002 PAD + 0x08008c80 0x08008c80 0x00000050 Code RO 1420 .text.UART_EndRxTransfer stm32f4xx_hal_uart.o + 0x08008cd0 0x08008cd0 0x00000018 Code RO 1468 .text.UART_EndTransmit_IT stm32f4xx_hal_uart.o + 0x08008ce8 0x08008ce8 0x0000001c Code RO 1418 .text.UART_EndTxTransfer stm32f4xx_hal_uart.o + 0x08008d04 0x08008d04 0x00000034 Code RO 2412 .text.UART_Get uart.o + 0x08008d38 0x08008d38 0x000000c8 Code RO 1458 .text.UART_Receive_IT stm32f4xx_hal_uart.o + 0x08008e00 0x08008e00 0x000000dc Code RO 1376 .text.UART_SetConfig stm32f4xx_hal_uart.o + 0x08008edc 0x08008edc 0x000000aa Code RO 1410 .text.UART_Start_Receive_DMA stm32f4xx_hal_uart.o + 0x08008f86 0x08008f86 0x00000002 PAD + 0x08008f88 0x08008f88 0x00000034 Code RO 1398 .text.UART_Start_Receive_IT stm32f4xx_hal_uart.o + 0x08008fbc 0x08008fbc 0x00000052 Code RO 1466 .text.UART_Transmit_IT stm32f4xx_hal_uart.o + 0x0800900e 0x0800900e 0x00000002 PAD + 0x08009010 0x08009010 0x00000018 Code RO 182 .text.USART1_IRQHandler stm32f4xx_it.o + 0x08009028 0x08009028 0x00000010 Code RO 184 .text.USART2_IRQHandler stm32f4xx_it.o + 0x08009038 0x08009038 0x00000018 Code RO 196 .text.USART6_IRQHandler stm32f4xx_it.o + 0x08009050 0x08009050 0x00000002 Code RO 158 .text.UsageFault_Handler stm32f4xx_it.o + 0x08009052 0x08009052 0x00000002 PAD + 0x08009054 0x08009054 0x0000000e Code RO 2579 .text.__ARM_isfinitef filter.o + 0x08009062 0x08009062 0x00000002 PAD + 0x08009064 0x08009064 0x0000000e Code RO 2652 .text.__ARM_isfinitef pid.o + 0x08009072 0x08009072 0x00000002 PAD + 0x08009074 0x08009074 0x00000010 Code RO 2575 .text.__ARM_isinff filter.o + 0x08009084 0x08009084 0x00000028 Code RO 592 .text.__NVIC_DisableIRQ stm32f4xx_hal_cortex.o + 0x080090ac 0x080090ac 0x00000020 Code RO 588 .text.__NVIC_EnableIRQ stm32f4xx_hal_cortex.o + 0x080090cc 0x080090cc 0x00000010 Code RO 580 .text.__NVIC_GetPriorityGrouping stm32f4xx_hal_cortex.o + 0x080090dc 0x080090dc 0x00000022 Code RO 582 .text.__NVIC_SetPriority stm32f4xx_hal_cortex.o + 0x080090fe 0x080090fe 0x00000002 PAD + 0x08009100 0x08009100 0x0000000e Code RO 2109 .text.__NVIC_SetPriority cmsis_os2.o + 0x0800910e 0x0800910e 0x00000002 PAD + 0x08009110 0x08009110 0x00000020 Code RO 576 .text.__NVIC_SetPriorityGrouping stm32f4xx_hal_cortex.o + 0x08009130 0x08009130 0x00000016 Code RO 2497 .text.copysignf ahrs.o + 0x08009146 0x08009146 0x00000002 PAD + 0x08009148 0x08009148 0x0000009c Code RO 1747 .text.eTaskGetState tasks.o + 0x080091e4 0x080091e4 0x0000002c Code RO 2918 .text.float_to_uint motor_dm.o + 0x08009210 0x08009210 0x00000042 Code RO 11 .text.main main.o + 0x08009252 0x08009252 0x00000002 PAD + 0x08009254 0x08009254 0x00000020 Code RO 3131 .text.major_yaw_Control gimbal.o + 0x08009274 0x08009274 0x00000044 Code RO 3139 .text.motor_imu_offset gimbal.o + 0x080092b8 0x080092b8 0x00000020 Code RO 2013 .text.osDelay cmsis_os2.o + 0x080092d8 0x080092d8 0x00000034 Code RO 2015 .text.osDelayUntil cmsis_os2.o + 0x0800930c 0x0800930c 0x00000026 Code RO 1951 .text.osKernelGetState cmsis_os2.o + 0x08009332 0x08009332 0x00000002 PAD + 0x08009334 0x08009334 0x00000014 Code RO 1963 .text.osKernelGetTickCount cmsis_os2.o + 0x08009348 0x08009348 0x00000006 Code RO 1965 .text.osKernelGetTickFreq cmsis_os2.o + 0x0800934e 0x0800934e 0x00000002 PAD + 0x08009350 0x08009350 0x00000028 Code RO 1947 .text.osKernelInitialize cmsis_os2.o + 0x08009378 0x08009378 0x0000002c Code RO 1957 .text.osKernelLock cmsis_os2.o + 0x080093a4 0x080093a4 0x00000034 Code RO 1953 .text.osKernelStart cmsis_os2.o + 0x080093d8 0x080093d8 0x00000044 Code RO 1959 .text.osKernelUnlock cmsis_os2.o + 0x0800941c 0x0800941c 0x00000086 Code RO 2067 .text.osMessageQueueGet cmsis_os2.o + 0x080094a2 0x080094a2 0x00000002 PAD + 0x080094a4 0x080094a4 0x000000a0 Code RO 2063 .text.osMessageQueueNew cmsis_os2.o + 0x08009544 0x08009544 0x0000008e Code RO 2065 .text.osMessageQueuePut cmsis_os2.o + 0x080095d2 0x080095d2 0x00000002 PAD + 0x080095d4 0x080095d4 0x00000024 Code RO 2077 .text.osMessageQueueReset cmsis_os2.o + 0x080095f8 0x080095f8 0x00000052 Code RO 2045 .text.osMutexAcquire cmsis_os2.o + 0x0800964a 0x0800964a 0x00000002 PAD + 0x0800964c 0x0800964c 0x00000096 Code RO 2043 .text.osMutexNew cmsis_os2.o + 0x080096e2 0x080096e2 0x00000002 PAD + 0x080096e4 0x080096e4 0x0000003e Code RO 2047 .text.osMutexRelease cmsis_os2.o + 0x08009722 0x08009722 0x00000002 PAD + 0x08009724 0x08009724 0x0000007e Code RO 2005 .text.osThreadFlagsSet cmsis_os2.o + 0x080097a2 0x080097a2 0x00000002 PAD + 0x080097a4 0x080097a4 0x000000ba Code RO 2011 .text.osThreadFlagsWait cmsis_os2.o + 0x0800985e 0x0800985e 0x00000002 PAD + 0x08009860 0x08009860 0x00000008 Code RO 1981 .text.osThreadGetId cmsis_os2.o + 0x08009868 0x08009868 0x000000b4 Code RO 1977 .text.osThreadNew cmsis_os2.o + 0x0800991c 0x0800991c 0x00000034 Code RO 1999 .text.osThreadTerminate cmsis_os2.o + 0x08009950 0x08009950 0x00000080 Code RO 1741 .text.prvAddCurrentTaskToDelayedList tasks.o + 0x080099d0 0x080099d0 0x000000ac Code RO 1727 .text.prvAddNewTaskToReadyList tasks.o + 0x08009a7c 0x08009a7c 0x0000007c Code RO 1878 .text.prvCheckForValidListAndQueue timers.o + 0x08009af8 0x08009af8 0x0000004e Code RO 1845 .text.prvCheckTasksWaitingTermination tasks.o + 0x08009b46 0x08009b46 0x00000002 PAD + 0x08009b48 0x08009b48 0x00000026 Code RO 1618 .text.prvCopyDataFromQueue queue.o + 0x08009b6e 0x08009b6e 0x00000002 PAD + 0x08009b70 0x08009b70 0x0000007a Code RO 1606 .text.prvCopyDataToQueue queue.o + 0x08009bea 0x08009bea 0x00000002 PAD + 0x08009bec 0x08009bec 0x00000036 Code RO 1733 .text.prvDeleteTCB tasks.o + 0x08009c22 0x08009c22 0x00000002 PAD + 0x08009c24 0x08009c24 0x00000012 Code RO 1622 .text.prvGetDisinheritPriorityAfterTimeout queue.o + 0x08009c36 0x08009c36 0x00000002 PAD + 0x08009c38 0x08009c38 0x00000020 Code RO 1916 .text.prvGetNextExpireTime timers.o + 0x08009c58 0x08009c58 0x00000078 Code RO 2127 .text.prvHeapInit heap_4.o + 0x08009cd0 0x08009cd0 0x0000002a Code RO 1767 .text.prvIdleTask tasks.o + 0x08009cfa 0x08009cfa 0x00000002 PAD + 0x08009cfc 0x08009cfc 0x00000020 Code RO 1586 .text.prvInitialiseMutex queue.o + 0x08009d1c 0x08009d1c 0x00000020 Code RO 1580 .text.prvInitialiseNewQueue queue.o + 0x08009d3c 0x08009d3c 0x00000098 Code RO 1725 .text.prvInitialiseNewTask tasks.o + 0x08009dd4 0x08009dd4 0x00000070 Code RO 1843 .text.prvInitialiseTaskLists tasks.o + 0x08009e44 0x08009e44 0x0000005a Code RO 2129 .text.prvInsertBlockIntoFreeList heap_4.o + 0x08009e9e 0x08009e9e 0x00000002 PAD + 0x08009ea0 0x08009ea0 0x00000040 Code RO 1928 .text.prvInsertTimerInActiveList timers.o + 0x08009ee0 0x08009ee0 0x00000018 Code RO 1620 .text.prvIsQueueEmpty queue.o + 0x08009ef8 0x08009ef8 0x0000001c Code RO 1608 .text.prvIsQueueFull queue.o + 0x08009f14 0x08009f14 0x00000028 Code RO 2169 .text.prvPortStartFirstTask port.o + 0x08009f3c 0x08009f3c 0x0000006e Code RO 1924 .text.prvProcessExpiredTimer timers.o + 0x08009faa 0x08009faa 0x00000002 PAD + 0x08009fac 0x08009fac 0x00000122 Code RO 1920 .text.prvProcessReceivedCommands timers.o + 0x0800a0ce 0x0800a0ce 0x00000002 PAD + 0x0800a0d0 0x0800a0d0 0x00000080 Code RO 1918 .text.prvProcessTimerOrBlockTask timers.o + 0x0800a150 0x0800a150 0x00000028 Code RO 1735 .text.prvResetNextTaskUnblockTime tasks.o + 0x0800a178 0x0800a178 0x0000002a Code RO 1922 .text.prvSampleTimeNow timers.o + 0x0800a1a2 0x0800a1a2 0x00000002 PAD + 0x0800a1a4 0x0800a1a4 0x0000008e Code RO 1926 .text.prvSwitchTimerLists timers.o + 0x0800a232 0x0800a232 0x00000002 PAD + 0x0800a234 0x0800a234 0x00000032 Code RO 2159 .text.prvTaskExitError port.o + 0x0800a266 0x0800a266 0x00000002 PAD + 0x0800a268 0x0800a268 0x00000016 Code RO 1880 .text.prvTimerTask timers.o + 0x0800a27e 0x0800a27e 0x00000002 PAD + 0x0800a280 0x0800a280 0x00000072 Code RO 1610 .text.prvUnlockQueue queue.o + 0x0800a2f2 0x0800a2f2 0x00000002 PAD + 0x0800a2f4 0x0800a2f4 0x0000014a Code RO 2125 .text.pvPortMalloc heap_4.o + 0x0800a43e 0x0800a43e 0x00000002 PAD + 0x0800a440 0x0800a440 0x00000018 Code RO 1827 .text.pvTaskIncrementMutexHeldCount tasks.o + 0x0800a458 0x0800a458 0x00000028 Code RO 2157 .text.pxPortInitialiseStack port.o + 0x0800a480 0x0800a480 0x0000002a Code RO 2916 .text.uint_to_float motor_dm.o + 0x0800a4aa 0x0800a4aa 0x00000002 PAD + 0x0800a4ac 0x0800a4ac 0x00000024 Code RO 1566 .text.uxListRemove list.o + 0x0800a4d0 0x0800a4d0 0x0000001a Code RO 2105 .text.vApplicationGetIdleTaskMemory cmsis_os2.o + 0x0800a4ea 0x0800a4ea 0x00000002 PAD + 0x0800a4ec 0x0800a4ec 0x0000001c Code RO 2107 .text.vApplicationGetTimerTaskMemory cmsis_os2.o + 0x0800a508 0x0800a508 0x00000016 Code RO 1558 .text.vListInitialise list.o + 0x0800a51e 0x0800a51e 0x00000002 PAD + 0x0800a520 0x0800a520 0x00000006 Code RO 1560 .text.vListInitialiseItem list.o + 0x0800a526 0x0800a526 0x00000002 PAD + 0x0800a528 0x0800a528 0x0000003a Code RO 1564 .text.vListInsert list.o + 0x0800a562 0x0800a562 0x00000002 PAD + 0x0800a564 0x0800a564 0x0000001c Code RO 1562 .text.vListInsertEnd list.o + 0x0800a580 0x0800a580 0x00000014 Code RO 2167 .text.vPortEnableVFP port.o + 0x0800a594 0x0800a594 0x00000046 Code RO 2173 .text.vPortEnterCritical port.o + 0x0800a5da 0x0800a5da 0x00000002 PAD + 0x0800a5dc 0x0800a5dc 0x0000002e Code RO 2175 .text.vPortExitCritical port.o + 0x0800a60a 0x0800a60a 0x00000002 PAD + 0x0800a60c 0x0800a60c 0x0000008a Code RO 2131 .text.vPortFree heap_4.o + 0x0800a696 0x0800a696 0x00000002 PAD + 0x0800a698 0x0800a698 0x00000034 Code RO 2165 .text.vPortSetupTimerInterrupt port.o + 0x0800a6cc 0x0800a6cc 0x00000062 Code RO 2181 .text.vPortValidateInterruptPriority port.o + 0x0800a72e 0x0800a72e 0x00000002 PAD + 0x0800a730 0x0800a730 0x00000028 Code RO 1650 .text.vQueueAddToRegistry queue.o + 0x0800a758 0x0800a758 0x00000044 Code RO 1654 .text.vQueueWaitForMessageRestricted queue.o + 0x0800a79c 0x0800a79c 0x00000054 Code RO 1745 .text.vTaskDelay tasks.o + 0x0800a7f0 0x0800a7f0 0x000000a8 Code RO 1737 .text.vTaskDelayUntil tasks.o + 0x0800a898 0x0800a898 0x000000c2 Code RO 1731 .text.vTaskDelete tasks.o + 0x0800a95a 0x0800a95a 0x00000002 PAD + 0x0800a95c 0x0800a95c 0x0000001a Code RO 1799 .text.vTaskInternalSetTimeOutState tasks.o + 0x0800a976 0x0800a976 0x00000002 PAD + 0x0800a978 0x0800a978 0x0000000e Code RO 1803 .text.vTaskMissedYield tasks.o + 0x0800a986 0x0800a986 0x00000002 PAD + 0x0800a988 0x0800a988 0x00000032 Code RO 1787 .text.vTaskPlaceOnEventList tasks.o + 0x0800a9ba 0x0800a9ba 0x00000002 PAD + 0x0800a9bc 0x0800a9bc 0x0000003e Code RO 1791 .text.vTaskPlaceOnEventListRestricted tasks.o + 0x0800a9fa 0x0800a9fa 0x00000002 PAD + 0x0800a9fc 0x0800a9fc 0x000000a4 Code RO 1823 .text.vTaskPriorityDisinheritAfterTimeout tasks.o + 0x0800aaa0 0x0800aaa0 0x000000a4 Code RO 1765 .text.vTaskStartScheduler tasks.o + 0x0800ab44 0x0800ab44 0x00000010 Code RO 1739 .text.vTaskSuspendAll tasks.o + 0x0800ab54 0x0800ab54 0x0000009a Code RO 1757 .text.vTaskSwitchContext tasks.o + 0x0800abee 0x0800abee 0x00000002 PAD + 0x0800abf0 0x0800abf0 0x00000112 Code RO 2163 .text.xPortStartScheduler port.o + 0x0800ad02 0x0800ad02 0x00000002 PAD + 0x0800ad04 0x0800ad04 0x0000002e Code RO 2179 .text.xPortSysTickHandler port.o + 0x0800ad32 0x0800ad32 0x00000002 PAD + 0x0800ad34 0x0800ad34 0x00000016 Code RO 1584 .text.xQueueCreateMutex queue.o + 0x0800ad4a 0x0800ad4a 0x00000002 PAD + 0x0800ad4c 0x0800ad4c 0x00000022 Code RO 1588 .text.xQueueCreateMutexStatic queue.o + 0x0800ad6e 0x0800ad6e 0x00000002 PAD + 0x0800ad70 0x0800ad70 0x00000046 Code RO 1582 .text.xQueueGenericCreate queue.o + 0x0800adb6 0x0800adb6 0x00000002 PAD + 0x0800adb8 0x0800adb8 0x00000096 Code RO 1578 .text.xQueueGenericCreateStatic queue.o + 0x0800ae4e 0x0800ae4e 0x00000002 PAD + 0x0800ae50 0x0800ae50 0x0000007e Code RO 1576 .text.xQueueGenericReset queue.o + 0x0800aece 0x0800aece 0x00000002 PAD + 0x0800aed0 0x0800aed0 0x000001a2 Code RO 1596 .text.xQueueGenericSend queue.o + 0x0800b072 0x0800b072 0x00000002 PAD + 0x0800b074 0x0800b074 0x000000ce Code RO 1612 .text.xQueueGenericSendFromISR queue.o + 0x0800b142 0x0800b142 0x00000002 PAD + 0x0800b144 0x0800b144 0x00000042 Code RO 1594 .text.xQueueGiveMutexRecursive queue.o + 0x0800b186 0x0800b186 0x00000002 PAD + 0x0800b188 0x0800b188 0x00000184 Code RO 1616 .text.xQueueReceive queue.o + 0x0800b30c 0x0800b30c 0x000000aa Code RO 1626 .text.xQueueReceiveFromISR queue.o + 0x0800b3b6 0x0800b3b6 0x00000002 PAD + 0x0800b3b8 0x0800b3b8 0x000001c6 Code RO 1600 .text.xQueueSemaphoreTake queue.o + 0x0800b57e 0x0800b57e 0x00000002 PAD + 0x0800b580 0x0800b580 0x0000003c Code RO 1598 .text.xQueueTakeMutexRecursive queue.o + 0x0800b5bc 0x0800b5bc 0x00000088 Code RO 1801 .text.xTaskCheckForTimeOut tasks.o + 0x0800b644 0x0800b644 0x00000066 Code RO 1729 .text.xTaskCreate tasks.o + 0x0800b6aa 0x0800b6aa 0x00000002 PAD + 0x0800b6ac 0x0800b6ac 0x00000076 Code RO 1723 .text.xTaskCreateStatic tasks.o + 0x0800b722 0x0800b722 0x00000002 PAD + 0x0800b724 0x0800b724 0x000000fc Code RO 1833 .text.xTaskGenericNotify tasks.o + 0x0800b820 0x0800b820 0x0000012a Code RO 1835 .text.xTaskGenericNotifyFromISR tasks.o + 0x0800b94a 0x0800b94a 0x00000002 PAD + 0x0800b94c 0x0800b94c 0x0000000c Code RO 1815 .text.xTaskGetCurrentTaskHandle tasks.o + 0x0800b958 0x0800b958 0x00000026 Code RO 1817 .text.xTaskGetSchedulerState tasks.o + 0x0800b97e 0x0800b97e 0x00000002 PAD + 0x0800b980 0x0800b980 0x0000000c Code RO 1773 .text.xTaskGetTickCount tasks.o + 0x0800b98c 0x0800b98c 0x00000012 Code RO 1775 .text.xTaskGetTickCountFromISR tasks.o + 0x0800b99e 0x0800b99e 0x00000002 PAD + 0x0800b9a0 0x0800b9a0 0x00000152 Code RO 1771 .text.xTaskIncrementTick tasks.o + 0x0800baf2 0x0800baf2 0x00000002 PAD + 0x0800baf4 0x0800baf4 0x00000090 Code RO 1831 .text.xTaskNotifyWait tasks.o + 0x0800bb84 0x0800bb84 0x00000092 Code RO 1821 .text.xTaskPriorityDisinherit tasks.o + 0x0800bc16 0x0800bc16 0x00000002 PAD + 0x0800bc18 0x0800bc18 0x00000092 Code RO 1819 .text.xTaskPriorityInherit tasks.o + 0x0800bcaa 0x0800bcaa 0x00000002 PAD + 0x0800bcac 0x0800bcac 0x0000008e Code RO 1793 .text.xTaskRemoveFromEventList tasks.o + 0x0800bd3a 0x0800bd3a 0x00000002 PAD + 0x0800bd3c 0x0800bd3c 0x00000114 Code RO 1743 .text.xTaskResumeAll tasks.o + 0x0800be50 0x0800be50 0x00000074 Code RO 1876 .text.xTimerCreateTimerTask timers.o + 0x0800bec4 0x0800bec4 0x00000068 Code RO 1888 .text.xTimerGenericCommand timers.o + 0x0800bf2c 0x0800bf2c 0x00000030 Code RO 3479 i.__ARM_fpclassify m_wm.l(fpclassify.o) + 0x0800bf5c 0x0800bf5c 0x00000026 Code RO 3423 i.__ARM_fpclassifyf m_wm.l(fpclassifyf.o) + 0x0800bf82 0x0800bf82 0x00000002 PAD + 0x0800bf84 0x0800bf84 0x0000012c Code RO 3280 i.__hardfp_asinf m_wm.l(asinf.o) + 0x0800c0b0 0x0800c0b0 0x000002d8 Code RO 3396 i.__hardfp_atan m_wm.l(atan.o) + 0x0800c388 0x0800c388 0x00000200 Code RO 3286 i.__hardfp_atan2 m_wm.l(atan2.o) + 0x0800c588 0x0800c588 0x000002ac Code RO 3292 i.__hardfp_atan2f m_wm.l(atan2f.o) + 0x0800c834 0x0800c834 0x0000017c Code RO 3310 i.__hardfp_tanf m_wm.l(tanf.o) + 0x0800c9b0 0x0800c9b0 0x000000f8 Code RO 3481 i.__kernel_poly m_wm.l(poly.o) + 0x0800caa8 0x0800caa8 0x00000014 Code RO 3404 i.__mathlib_dbl_infnan m_wm.l(dunder.o) + 0x0800cabc 0x0800cabc 0x00000014 Code RO 3405 i.__mathlib_dbl_infnan2 m_wm.l(dunder.o) + 0x0800cad0 0x0800cad0 0x00000020 Code RO 3409 i.__mathlib_dbl_underflow m_wm.l(dunder.o) + 0x0800caf0 0x0800caf0 0x00000006 Code RO 3426 i.__mathlib_flt_infnan m_wm.l(funder.o) + 0x0800caf6 0x0800caf6 0x00000006 Code RO 3427 i.__mathlib_flt_infnan2 m_wm.l(funder.o) + 0x0800cafc 0x0800cafc 0x00000010 Code RO 3428 i.__mathlib_flt_invalid m_wm.l(funder.o) + 0x0800cb0c 0x0800cb0c 0x00000010 Code RO 3431 i.__mathlib_flt_underflow m_wm.l(funder.o) + 0x0800cb1c 0x0800cb1c 0x00000154 Code RO 3440 i.__mathlib_rredf2 m_wm.l(rredf.o) + 0x0800cc70 0x0800cc70 0x00000010 Code RO 3398 i.atan m_wm.l(atan.o) + 0x0800cc80 0x0800cc80 0x00000018 Code RO 3419 i.fabs m_wm.l(fabs.o) + 0x0800cc98 0x0800cc98 0x0000003e Code RO 3445 i.sqrtf m_wm.l(sqrtf.o) + 0x0800ccd6 0x0800ccd6 0x00000018 Code RO 3377 x$fpl$basic fz_wm.l(basic.o) + 0x0800ccee 0x0800ccee 0x00000002 PAD + 0x0800ccf0 0x0800ccf0 0x00000062 Code RO 3258 x$fpl$d2f fz_wm.l(d2f.o) + 0x0800cd52 0x0800cd52 0x00000002 PAD + 0x0800cd54 0x0800cd54 0x00000150 Code RO 3379 x$fpl$dadd fz_wm.l(daddsub_clz.o) + 0x0800cea4 0x0800cea4 0x00000018 Code RO 3475 x$fpl$dcmpinf fz_wm.l(dcmpi.o) + 0x0800cebc 0x0800cebc 0x000002b4 Code RO 3261 x$fpl$ddiv fz_wm.l(ddiv.o) + 0x0800d170 0x0800d170 0x00000078 Code RO 3385 x$fpl$deqf fz_wm.l(deqf.o) + 0x0800d1e8 0x0800d1e8 0x0000005a Code RO 3264 x$fpl$dfixu fz_wm.l(dfixu.o) + 0x0800d242 0x0800d242 0x0000002e Code RO 3269 x$fpl$dflt fz_wm.l(dflt_clz.o) + 0x0800d270 0x0800d270 0x00000026 Code RO 3268 x$fpl$dfltu fz_wm.l(dflt_clz.o) + 0x0800d296 0x0800d296 0x00000002 PAD + 0x0800d298 0x0800d298 0x00000154 Code RO 3274 x$fpl$dmul fz_wm.l(dmul.o) + 0x0800d3ec 0x0800d3ec 0x0000009c Code RO 3387 x$fpl$dnaninf fz_wm.l(dnaninf.o) + 0x0800d488 0x0800d488 0x0000000c Code RO 3389 x$fpl$dretinf fz_wm.l(dretinf.o) + 0x0800d494 0x0800d494 0x00000016 Code RO 3380 x$fpl$drsb fz_wm.l(daddsub_clz.o) + 0x0800d4aa 0x0800d4aa 0x00000002 PAD + 0x0800d4ac 0x0800d4ac 0x000001dc Code RO 3381 x$fpl$dsub fz_wm.l(daddsub_clz.o) + 0x0800d688 0x0800d688 0x00000056 Code RO 3276 x$fpl$f2d fz_wm.l(f2d.o) + 0x0800d6de 0x0800d6de 0x00000060 Code RO 3278 x$fpl$ffltll fz_wm.l(ffltll_clz.o) + 0x0800d73e 0x0800d73e 0x0000008c Code RO 3391 x$fpl$fnaninf fz_wm.l(fnaninf.o) + 0x0800d7ca 0x0800d7ca 0x0000001a Code RO 3477 x$fpl$fpinit fz_wm.l(fpinit.o) + 0x0800d7e4 0x0800d7e4 0x0000000a Code RO 3393 x$fpl$fretinf fz_wm.l(fretinf.o) + 0x0800d7ee 0x0800d7ee 0x00000000 Code RO 3395 x$fpl$usenofp fz_wm.l(usenofp.o) + 0x0800d7ee 0x0800d7ee 0x00000002 PAD + 0x0800d7f0 0x0800d7f0 0x00000098 Data RO 3399 .constdata m_wm.l(atan.o) + 0x0800d888 0x0800d888 0x00000008 Data RO 3439 .constdata m_wm.l(qnan.o) + 0x0800d890 0x0800d890 0x00000020 Data RO 3441 .constdata m_wm.l(rredf.o) + 0x0800d8b0 0x0800d8b0 0x00000010 Data RO 1509 .rodata.AHBPrescTable system_stm32f4xx.o + 0x0800d8c0 0x0800d8c0 0x00000008 Data RO 1510 .rodata.APBPrescTable system_stm32f4xx.o + 0x0800d8c8 0x0800d8c8 0x00000038 Data RO 2299 .rodata.GPIO_Map gpio_1.o + 0x0800d900 0x0800d900 0x00000024 Data RO 3069 .rodata.attr_ai user_task.o + 0x0800d924 0x0800d924 0x00000024 Data RO 3070 .rodata.attr_atti_esti user_task.o + 0x0800d948 0x0800d948 0x00000024 Data RO 3066 .rodata.attr_chassis_ctrl user_task.o + 0x0800d96c 0x0800d96c 0x00000024 Data RO 3068 .rodata.attr_dr16 user_task.o + 0x0800d990 0x0800d990 0x00000024 Data RO 3067 .rodata.attr_gimbal_ctrl user_task.o + 0x0800d9b4 0x0800d9b4 0x00000024 Data RO 3064 .rodata.attr_init user_task.o + 0x0800d9d8 0x0800d9d8 0x00000024 Data RO 3071 .rodata.attr_remote user_task.o + 0x0800d9fc 0x0800d9fc 0x00000024 Data RO 3065 .rodata.attr_shoot_ctrl user_task.o + 0x0800da20 0x0800da20 0x00000200 Data RO 2541 .rodata.crc16_tab crc16.o + 0x0800dc20 0x0800dc20 0x00000024 Data RO 39 .rodata.defaultTask_attributes freertos.o + 0x0800dc44 0x0800dc44 0x00000020 Data RO 3002 .rodata.imu_temp_ctrl_pid_param atti_esti.o + 0x0800dc64 0x0800dc64 0x0000000c Data RO 38 .rodata.str1.1 freertos.o + 0x0800dc70 0x0800dc70 0x00000047 Data RO 3063 .rodata.str1.1 user_task.o + 0x0800dcb7 0x0800dcb7 0x00000001 PAD + 0x0800dcb8 0x0800dcb8 0x00000040 Data RO 3582 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x0800dcf8, Size: 0x0001b8e0, Max: 0x0001c000, ABSOLUTE, COMPRESSED[0x00000158]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 COMPRESSED 0x00000004 Data RW 1508 .data.SystemCoreClock system_stm32f4xx.o + 0x20000004 COMPRESSED 0x00000004 Data RW 2501 .data.beta ahrs.o + 0x20000008 COMPRESSED 0x0000000c Data RW 2996 .data.cali_bmi088 atti_esti.o + 0x20000014 COMPRESSED 0x00000320 Data RW 3092 .data.robot_config config.o + 0x20000334 COMPRESSED 0x00000004 Data RW 706 .data.uwTickPrio stm32f4xx_hal.o + 0x20000338 COMPRESSED 0x00000004 Data RW 2185 .data.uxCriticalNesting port.o + 0x2000033c COMPRESSED 0x00000004 PAD + 0x20000340 - 0x00000060 Zero RW 3484 .bss c_w.l(libspace.o) + 0x200003a0 - 0x00000068 Zero RW 2270 .bss.CAN_Callback can_1.o + 0x20000408 - 0x00000020 Zero RW 2401 .bss.SPI_Callback spi_1.o + 0x20000428 - 0x00000019 Zero RW 2986 .bss.ai_cmd ai_1.o + 0x20000441 - 0x00000002 Zero RW 2792 .bss.buffer bmi088.o + 0x20000443 COMPRESSED 0x00000001 PAD + 0x20000444 - 0x00000002 Zero RW 3004 .bss.calib_count atti_esti.o + 0x20000446 COMPRESSED 0x00000002 PAD + 0x20000448 - 0x00000008 Zero RW 2875 .bss.can_managers motor_rm.o + 0x20000450 - 0x00000004 Zero RW 40 .bss.defaultTaskHandle freertos.o + 0x20000454 COMPRESSED 0x00000004 PAD + 0x20000458 - 0x00000058 Zero RW 3028 .bss.dr16 dr16_1.o + 0x200004b0 - 0x0000000c Zero RW 3003 .bss.eulr_to_send atti_esti.o + 0x200004bc - 0x00000064 Zero RW 2984 .bss.g_feedback ai_1.o + 0x20000520 - 0x00000014 Zero RW 3081 .bss.g_rc_cmd remote.o + 0x20000534 - 0x00000014 Zero RW 3041 .bss.gimbal_cmd gimbal_ctrl.o + 0x20000548 - 0x00000034 Zero RW 3039 .bss.gimbal_imu gimbal_ctrl.o + 0x2000057c - 0x00000004 Zero RW 3007 .bss.gyro_sum.0 atti_esti.o + 0x20000580 - 0x00000004 Zero RW 3009 .bss.gyro_sum.2 atti_esti.o + 0x20000584 - 0x00000028 Zero RW 56 .bss.hcan1 can.o + 0x200005ac - 0x00000060 Zero RW 99 .bss.hdma_spi1_tx spi.o + 0x2000060c - 0x00000054 Zero RW 82 .bss.hi2c2 i2c.o + 0x20000660 - 0x00000048 Zero RW 116 .bss.htim10 tim.o + 0x200006a8 - 0x00000048 Zero RW 138 .bss.huart2 usart.o + 0x200006f0 - 0x00000048 Zero RW 140 .bss.huart6 usart.o + 0x20000738 - 0x0000003c Zero RW 3001 .bss.imu_temp_ctrl_pid atti_esti.o + 0x20000774 - 0x00000001 Zero RW 2789 .bss.inited bmi088.o + 0x20000775 - 0x00000001 Zero RW 3188 .bss.last_firecmd shoot.o + 0x20000776 - 0x000000a0 Zero RW 1938 .bss.prvCheckForValidListAndQueue.ucStaticTimerQueueStorage timers.o + 0x20000816 COMPRESSED 0x00000002 PAD + 0x20000818 - 0x00000004 Zero RW 1934 .bss.prvSampleTimeNow.xLastTime timers.o + 0x2000081c - 0x00000004 Zero RW 1932 .bss.pxCurrentTimerList timers.o + 0x20000820 - 0x00000004 Zero RW 1855 .bss.pxDelayedTaskList tasks.o + 0x20000824 - 0x00000004 Zero RW 2141 .bss.pxEnd heap_4.o + 0x20000828 - 0x00000004 Zero RW 2273 .bss.queue_mutex can_1.o + 0x2000082c - 0x00000003 Zero RW 3055 .bss.shoot_cmd shoot_ctrl.o + 0x2000082f COMPRESSED 0x00000001 PAD + 0x20000830 - 0x00000004 Zero RW 2964 .bss.thread_alert dr16.o + 0x20000834 - 0x00019999 Zero RW 2148 .bss.ucHeap heap_4.o + 0x2001a1cd - 0x00000001 Zero RW 2183 .bss.ucMaxSysCallPriority port.o + 0x2001a1ce COMPRESSED 0x00000002 PAD + 0x2001a1d0 - 0x00000004 Zero RW 1851 .bss.uxCurrentNumberOfTasks tasks.o + 0x2001a1d4 - 0x00000004 Zero RW 1853 .bss.uxSchedulerSuspended tasks.o + 0x2001a1d8 - 0x00000004 Zero RW 1848 .bss.uxTaskNumber tasks.o + 0x2001a1dc - 0x00000004 Zero RW 1859 .bss.uxTopReadyPriority tasks.o + 0x2001a1e0 - 0x00000200 Zero RW 2114 .bss.vApplicationGetIdleTaskMemory.Idle_Stack cmsis_os2.o + 0x2001a3e0 - 0x00000400 Zero RW 2116 .bss.vApplicationGetTimerTaskMemory.Timer_Stack cmsis_os2.o + 0x2001a7e0 - 0x0000005c Zero RW 2115 .bss.vApplicationGetTimerTaskMemory.Timer_TCB cmsis_os2.o + 0x2001a83c - 0x00000014 Zero RW 1936 .bss.xActiveTimerList2 timers.o + 0x2001a850 - 0x00000014 Zero RW 1867 .bss.xDelayedTaskList2 tasks.o + 0x2001a864 - 0x00000004 Zero RW 2145 .bss.xMinimumEverFreeBytesRemaining heap_4.o + 0x2001a868 - 0x00000004 Zero RW 1862 .bss.xNextTaskUnblockTime tasks.o + 0x2001a86c - 0x00000004 Zero RW 2147 .bss.xNumberOfSuccessfulFrees heap_4.o + 0x2001a870 - 0x00000004 Zero RW 1864 .bss.xPendedTicks tasks.o + 0x2001a874 - 0x00000014 Zero RW 1860 .bss.xPendingReadyList tasks.o + 0x2001a888 - 0x00000040 Zero RW 1656 .bss.xQueueRegistry queue.o + 0x2001a8c8 - 0x00000014 Zero RW 1849 .bss.xTasksWaitingTermination tasks.o + 0x2001a8dc - 0x00000004 Zero RW 1930 .bss.xTimerQueue timers.o + 0x2001a8e0 - 0x00001000 Zero RW 2 HEAP startup_stm32f407xx.o + + + Execution Region RW_IRAM2 (Exec base: 0x2001c000, Load base: 0x0800de50, Size: 0x000038e8, Max: 0x00004000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x2001c000 0x0800de50 0x00000001 Data RW 707 .data.uwTickFreq stm32f4xx_hal.o + 0x2001c001 0x0800de51 0x00000007 PAD + 0x2001c008 - 0x00000040 Zero RW 2298 .bss.GPIO_Callback gpio_1.o + 0x2001c048 - 0x00000004 Zero RW 58 .bss.HAL_RCC_CAN1_CLK_ENABLED can.o + 0x2001c04c - 0x00000004 Zero RW 2111 .bss.KernelState cmsis_os2.o + 0x2001c050 - 0x00000004 Zero RW 3187 .bss.Shoot_RunningFSM.pos shoot.o + 0x2001c054 - 0x00000090 Zero RW 2438 .bss.UART_Callback uart.o + 0x2001c0e4 - 0x00000048 Zero RW 2985 .bss.ai ai_1.o + 0x2001c12c - 0x00000019 Zero RW 3040 .bss.ai_g_cmd gimbal_ctrl.o + 0x2001c145 0x0800de51 0x00000003 PAD + 0x2001c148 - 0x00000030 Zero RW 2998 .bss.bmi088 atti_esti.o + 0x2001c178 - 0x00000013 Zero RW 2791 .bss.bmi088_rxbuf bmi088.o + 0x2001c18b 0x0800de51 0x00000001 PAD + 0x2001c18c - 0x00000008 Zero RW 2920 .bss.can_managers motor_dm.o + 0x2001c194 0x0800de51 0x00000004 PAD + 0x2001c198 - 0x00000310 Zero RW 3038 .bss.gimbal gimbal_ctrl.o + 0x2001c4a8 - 0x00000014 Zero RW 2999 .bss.gimbal_ahrs atti_esti.o + 0x2001c4bc - 0x00000014 Zero RW 3042 .bss.gimbal_cmd_remote gimbal_ctrl.o + 0x2001c4d0 - 0x00000034 Zero RW 3006 .bss.gimbal_to_send atti_esti.o + 0x2001c504 - 0x00000004 Zero RW 3008 .bss.gyro_sum.1 atti_esti.o + 0x2001c508 - 0x00000028 Zero RW 57 .bss.hcan2 can.o + 0x2001c530 - 0x00000060 Zero RW 98 .bss.hdma_spi1_rx spi.o + 0x2001c590 - 0x00000060 Zero RW 141 .bss.hdma_usart3_rx usart.o + 0x2001c5f0 - 0x00000058 Zero RW 97 .bss.hspi1 spi.o + 0x2001c648 - 0x00000048 Zero RW 137 .bss.huart1 usart.o + 0x2001c690 - 0x00000048 Zero RW 139 .bss.huart3 usart.o + 0x2001c6d8 - 0x00000004 Zero RW 2272 .bss.id_parser can_1.o + 0x2001c6dc - 0x00000001 Zero RW 2271 .bss.inited can_1.o + 0x2001c6dd - 0x00000001 Zero RW 2963 .bss.inited dr16.o + 0x2001c6de 0x0800de51 0x00000002 PAD + 0x2001c6e0 - 0x00000020 Zero RW 3005 .bss.ist8310 atti_esti.o + 0x2001c700 - 0x00000004 Zero RW 2997 .bss.jiaozhun atti_esti.o + 0x2001c704 - 0x0000000c Zero RW 3000 .bss.magn atti_esti.o + 0x2001c710 - 0x00000050 Zero RW 1937 .bss.prvCheckForValidListAndQueue.xStaticTimerQueue timers.o + 0x2001c760 - 0x00000004 Zero RW 1847 .bss.pxCurrentTCB tasks.o + 0x2001c764 - 0x00000004 Zero RW 1856 .bss.pxOverflowDelayedTaskList tasks.o + 0x2001c768 - 0x00000004 Zero RW 1933 .bss.pxOverflowTimerList timers.o + 0x2001c76c - 0x00000460 Zero RW 1858 .bss.pxReadyTasksLists tasks.o + 0x2001cbcc - 0x00000004 Zero RW 2275 .bss.queue_list can_1.o + 0x2001cbd0 - 0x00000058 Zero RW 3080 .bss.remote_dr16 remote.o + 0x2001cc28 - 0x00000003 Zero RW 3082 .bss.s_rc_cmd remote.o + 0x2001cc2b 0x0800de51 0x00000005 PAD + 0x2001cc30 - 0x00000330 Zero RW 3054 .bss.shoot shoot_ctrl.o + 0x2001cf60 - 0x000000a4 Zero RW 3072 .bss.task_runtime user_task.o + 0x2001d004 - 0x00000004 Zero RW 2790 .bss.thread_alert bmi088.o + 0x2001d008 - 0x00000810 Zero RW 2274 .bss.tx_queues can_1.o + 0x2001d818 - 0x00000004 Zero RW 2184 .bss.ulMaxPRIGROUPValue port.o + 0x2001d81c - 0x00000004 Zero RW 708 .bss.uwTick stm32f4xx_hal.o + 0x2001d820 - 0x00000004 Zero RW 1850 .bss.uxDeletedTasksWaitingCleanUp tasks.o + 0x2001d824 - 0x0000005c Zero RW 2113 .bss.vApplicationGetIdleTaskMemory.Idle_TCB cmsis_os2.o + 0x2001d880 - 0x00000014 Zero RW 1935 .bss.xActiveTimerList1 timers.o + 0x2001d894 - 0x00000001 Zero RW 2142 .bss.xBlockAllocatedBit heap_4.o + 0x2001d895 0x0800de51 0x00000003 PAD + 0x2001d898 - 0x00000014 Zero RW 1866 .bss.xDelayedTaskList1 tasks.o + 0x2001d8ac - 0x00000004 Zero RW 2143 .bss.xFreeBytesRemaining heap_4.o + 0x2001d8b0 - 0x00000004 Zero RW 1861 .bss.xIdleTaskHandle tasks.o + 0x2001d8b4 - 0x00000004 Zero RW 1865 .bss.xNumOfOverflows tasks.o + 0x2001d8b8 - 0x00000004 Zero RW 2146 .bss.xNumberOfSuccessfulAllocations heap_4.o + 0x2001d8bc - 0x00000004 Zero RW 1852 .bss.xSchedulerRunning tasks.o + 0x2001d8c0 - 0x00000008 Zero RW 2144 .bss.xStart heap_4.o + 0x2001d8c8 - 0x00000014 Zero RW 1857 .bss.xSuspendedTaskList tasks.o + 0x2001d8dc - 0x00000004 Zero RW 1854 .bss.xTickCount tasks.o + 0x2001d8e0 - 0x00000004 Zero RW 1931 .bss.xTimerTaskHandle timers.o + 0x2001d8e4 - 0x00000004 Zero RW 1863 .bss.xYieldPending tasks.o + 0x2001d8e8 - 0x00002000 Zero RW 1 STACK startup_stm32f407xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 2814 12 0 4 0 9033 ahrs.o + 220 0 0 0 0 3628 ai.o + 160 8 0 0 197 2645 ai_1.o + 612 20 32 12 254 3627 atti_esti.o + 1050 16 0 0 26 5466 bmi088.o + 490 0 0 0 84 6451 can.o + 2364 4 0 0 2181 17071 can_1.o + 64 8 0 0 0 694 chassis_ctrl.o + 1746 0 0 0 1724 42607 cmsis_os2.o + 10 0 0 800 0 4986 config.o + 102 0 512 0 0 1503 crc16.o + 106 0 0 0 0 3310 dma.o + 586 8 0 0 5 4567 dr16.o + 128 8 0 0 88 2008 dr16_1.o + 410 20 0 0 0 4115 filter.o + 70 0 48 0 4 2538 freertos.o + 2390 40 0 0 0 11581 gimbal.o + 340 12 0 0 901 7014 gimbal_ctrl.o + 392 0 0 0 0 4130 gpio.o + 306 12 56 0 64 4887 gpio_1.o + 678 0 0 0 104886 4722 heap_4.o + 174 0 0 0 84 5113 i2c.o + 292 0 0 0 0 552 init.o + 150 0 0 0 0 2198 list.o + 236 0 0 0 0 2726 main.o + 16 0 0 0 0 715 mm.o + 1222 32 0 0 8 9733 motor_dm.o + 1376 32 0 0 8 8756 motor_rm.o + 584 12 0 0 0 3404 pid.o + 872 16 0 4 5 3807 port.o + 122 4 0 0 0 5979 pwm.o + 2680 0 0 0 64 22592 queue.o + 160 8 0 0 111 2979 remote.o + 208 32 0 0 0 2833 remote_cmd.o + 3084 72 0 0 5 11481 shoot.o + 156 12 0 0 819 5433 shoot_ctrl.o + 380 0 0 0 280 5139 spi.o + 408 0 0 0 32 8705 spi_1.o + 64 26 392 0 12288 820 startup_stm32f407xx.o + 212 0 0 5 4 7291 stm32f4xx_hal.o + 1674 6 0 0 0 13160 stm32f4xx_hal_can.o + 306 0 0 0 0 10963 stm32f4xx_hal_cortex.o + 1052 12 0 0 0 9233 stm32f4xx_hal_dma.o + 456 0 0 0 0 5162 stm32f4xx_hal_gpio.o + 408 0 0 0 0 39555 stm32f4xx_hal_i2c.o + 70 0 0 0 0 3333 stm32f4xx_hal_msp.o + 1376 0 0 0 0 7270 stm32f4xx_hal_rcc.o + 3056 0 0 0 0 20870 stm32f4xx_hal_spi.o + 1348 4 0 0 0 44558 stm32f4xx_hal_tim.o + 2164 0 0 0 0 24663 stm32f4xx_hal_uart.o + 296 0 0 0 0 2775 stm32f4xx_it.o + 18 0 24 4 0 2527 system_stm32f4xx.o + 4232 20 0 0 1280 29917 tasks.o + 284 0 0 0 72 5770 tim.o + 168 0 0 0 0 1798 time.o + 1174 26 0 0 300 14810 timers.o + 508 16 0 0 144 7083 uart.o + 848 0 0 0 384 7770 usart.o + 310 0 0 0 0 2871 user_math.o + 0 0 359 0 164 3508 user_task.o + + ---------------------------------------------------------------------- + 47572 506 1488 832 126504 514435 Object Totals + 0 0 64 0 0 0 (incl. Generated) + 390 8 1 3 38 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 90 0 0 0 0 0 __dczerorl2.o + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 22 0 0 0 0 100 _rserrno.o + 16 0 0 0 0 68 aeabi_memset4.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 240 0 0 0 0 100 lludivv7m.o + 8 4 0 0 0 68 rt_errno_addr_intlibspace.o + 78 0 0 0 0 80 rt_memclr_w.o + 138 0 0 0 0 68 rt_memcpy_v6.o + 100 0 0 0 0 80 rt_memcpy_w.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 24 0 0 0 0 164 basic.o + 98 4 0 0 0 140 d2f.o + 834 16 0 0 0 516 daddsub_clz.o + 24 0 0 0 0 116 dcmpi.o + 692 140 0 0 0 264 ddiv.o + 120 4 0 0 0 140 deqf.o + 90 4 0 0 0 140 dfixu.o + 84 0 0 0 0 232 dflt_clz.o + 340 12 0 0 0 152 dmul.o + 156 4 0 0 0 140 dnaninf.o + 12 0 0 0 0 116 dretinf.o + 86 4 0 0 0 132 f2d.o + 96 0 0 0 0 132 ffltll_clz.o + 140 4 0 0 0 132 fnaninf.o + 26 0 0 0 0 116 fpinit.o + 10 0 0 0 0 116 fretinf.o + 0 0 0 0 0 0 usenofp.o + 300 42 0 0 0 176 asinf.o + 744 106 152 0 0 352 atan.o + 512 64 0 0 0 208 atan2.o + 684 90 0 0 0 208 atan2f.o + 72 8 0 0 0 372 dunder.o + 24 0 0 0 0 124 fabs.o + 48 0 0 0 0 124 fpclassify.o + 38 0 0 0 0 116 fpclassifyf.o + 44 12 0 0 0 464 funder.o + 248 0 0 0 0 152 poly.o + 0 0 8 0 0 0 qnan.o + 340 24 32 0 0 160 rredf.o + 62 0 0 0 0 136 sqrtf.o + 380 58 0 0 0 200 tanf.o + + ---------------------------------------------------------------------- + 7316 616 192 0 96 6688 Library Totals + 20 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 968 20 0 0 96 1148 c_w.l + 2832 192 0 0 0 2748 fz_wm.l + 3496 404 192 0 0 2792 m_wm.l + + ---------------------------------------------------------------------- + 7316 616 192 0 96 6688 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 54888 1122 1680 832 126600 516159 Grand Totals + 54888 1122 1680 348 126600 516159 ELF Image Totals (compressed) + 54888 1122 1680 348 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 56568 ( 55.24kB) + Total RW Size (RW Data + ZI Data) 127432 ( 124.45kB) + Total ROM Size (Code + RO Data + RW Data) 56916 ( 55.58kB) + +============================================================================== + diff --git a/MDK-ARM/Infantry/Infantry.sct b/MDK-ARM/Infantry/Infantry.sct new file mode 100644 index 0000000..a335d3e --- /dev/null +++ b/MDK-ARM/Infantry/Infantry.sct @@ -0,0 +1,19 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00100000 { ; load region size_region + ER_IROM1 0x08000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x0001C000 { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM2 0x2001C000 0x00004000 { + .ANY (+RW +ZI) + } +} + diff --git a/MDK-ARM/Infantry/Infantry_Infantry.dep b/MDK-ARM/Infantry/Infantry_Infantry.dep new file mode 100644 index 0000000..32f5560 --- /dev/null +++ b/MDK-ARM/Infantry/Infantry_Infantry.dep @@ -0,0 +1,2954 @@ +Dependencies for Project 'Infantry', Target 'Infantry': (DO NOT MODIFY !) +CompilerVersion: 6160000::V6.16::ARMCLANG +F (startup_stm32f407xx.s)(0x695FAFE7)(--target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -masm=auto -c -gdwarf-3 -I ../Drivers/CMSIS/Include -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -Wa,armasm,--pd,"__UVISION_VERSION SETA 534" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"STM32F407xx SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -o infantry/startup_stm32f407xx.o) +F (../Core/Src/main.c)(0x695F9C44)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/main.o -MD) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\dma.h)(0x695F99C3) +I (..\Core\Inc\i2c.h)(0x695F99C4) +I (..\Core\Inc\spi.h)(0x695F99C4) +I (..\Core\Inc\tim.h)(0x695FA10B) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\Core\Inc\gpio.h)(0x695F99C2) +F (../Core/Src/gpio.c)(0x695FA108)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/gpio.o -MD) +I (..\Core\Inc\gpio.h)(0x695F99C2) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/freertos.c)(0x695FAA14)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/freertos.o -MD) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\task\user_task.h)(0x695FB706) +F (../Core/Src/can.c)(0x695F9C42)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/can.o -MD) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/dma.c)(0x695F9C42)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/dma.o -MD) +I (..\Core\Inc\dma.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/i2c.c)(0x695F99C3)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/i2c.o -MD) +I (..\Core\Inc\i2c.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/spi.c)(0x695F99C4)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/spi.o -MD) +I (..\Core\Inc\spi.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/tim.c)(0x695FA10B)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/tim.o -MD) +I (..\Core\Inc\tim.h)(0x695FA10B) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/usart.c)(0x695FAFE4)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/usart.o -MD) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/stm32f4xx_it.c)(0x695FAFBE)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_it.o -MD) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_it.h)(0x695FAFBF) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\bsp\uart.h)(0x695FAA4C) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +F (../Core/Src/stm32f4xx_hal_msp.c)(0x695F9C44)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_msp.o -MD) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_can.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_rcc.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_rcc_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_flash.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_flash_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_flash_ramfunc.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_gpio.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_dma_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_dma.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_pwr.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_pwr_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_cortex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_exti.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_i2c.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_i2c_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_spi.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_tim.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_tim_ex.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c)(0x68B05645)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stm32f4xx_hal_uart.o -MD) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Core/Src/system_stm32f4xx.c)(0x68B05646)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/system_stm32f4xx.o -MD) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Middlewares/Third_Party/FreeRTOS/Source/croutine.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/croutine.o -MD) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/event_groups.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/event_groups.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/list.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/list.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/queue.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/queue.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/stream_buffer.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/tasks.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/tasks.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/timers.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/timers.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/cmsis_os2.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h)(0x68B055DB) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (../Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/heap_4.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c)(0x68B055DB)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-covered-switch-default -Wno-unreachable-code-break -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/port.o -MD) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (..\User\bsp\can.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/can_1.o -MD) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\bsp\gpio.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/gpio_1.o -MD) +I (..\User\bsp\gpio.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\Core\Inc\gpio.h)(0x695F99C2) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +F (..\User\bsp\i2c.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/i2c_1.o -MD) +I (..\User\bsp\i2c.h)(0x695FAA4C) +I (..\Core\Inc\i2c.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +F (..\User\bsp\mm.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/mm.o -MD) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +F (..\User\bsp\spi.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/spi_1.o -MD) +I (..\Core\Inc\spi.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\spi.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +F (..\User\bsp\uart.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/uart.o -MD) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\uart.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +F (..\User\bsp\time.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/time.o -MD) +I (..\User\bsp\time.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (..\User\bsp\pwm.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/pwm.o -MD) +I (..\Core\Inc\tim.h)(0x695FA10B) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\pwm.h)(0x695FAA4C) +I (..\User\bsp\bsp.h)(0x695FAA4C) +F (..\User\component\ahrs.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/ahrs.o -MD) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\component\capacity.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/capacity.o -MD) +I (..\User\component\capacity.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\crc8.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/crc8.o -MD) +I (..\User\component\crc8.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +F (..\User\component\crc16.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/crc16.o -MD) +I (..\User\component\crc16.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\error_detect.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/error_detect.o -MD) +I (..\User\component\error_detect.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\bsp\mm.h)(0x695FAA4C) +F (..\User\component\filter.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/filter.o -MD) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\freertos_cli.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/freertos_cli.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\component\FreeRTOS_CLI.h)(0x695FAA4C) +F (..\User\component\limiter.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/limiter.o -MD) +I (..\User\component\limiter.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\mixer.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/mixer.o -MD) +I (..\User\component\mixer.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\pid.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/pid.o -MD) +I (..\User\component\pid.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +F (..\User\component\ui.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/ui.o -MD) +I (..\User\component\ui.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdio.h)(0x6035A4A8) +F (..\User\component\user_math.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/user_math.o -MD) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\component\cmd.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/cmd.o -MD) +I (..\User\component\cmd.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\device\bmi088.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/bmi088.o -MD) +I (..\User\device\bmi088.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\device\device.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\Core\Inc\gpio.h)(0x695F99C2) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\bsp\time.h)(0x695FAA4C) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\gpio.h)(0x695FAA4C) +I (..\User\bsp\spi.h)(0x695FAA4C) +I (..\Core\Inc\spi.h)(0x695F99C4) +F (..\User\device\ist8310.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/ist8310.o -MD) +I (..\User\device\ist8310.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (..\User\device\device.h)(0x695FAA4C) +I (..\Core\Inc\gpio.h)(0x695F99C2) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\bsp\time.h)(0x695FAA4C) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\gpio.h)(0x695FAA4C) +I (..\User\bsp\i2c.h)(0x695FAA4C) +I (..\Core\Inc\i2c.h)(0x695F99C4) +F (..\User\device\motor.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/motor.o -MD) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\device\motor_rm.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/motor_rm.o -MD) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\bsp\time.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +F (..\User\device\motor_dm.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/motor_dm.o -MD) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\bsp\time.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\device\ai.c)(0x695FA26C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/ai.o -MD) +I (..\User\device\ai.h)(0x695FA26C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\bsp\uart.h)(0x695FAA4C) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\User\component\crc16.h)(0x695FAA4C) +F (..\User\device\dr16.c)(0x695FAA4C)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/dr16.o -MD) +I (..\User\device\dr16.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\bsp\uart.h)(0x695FAA4C) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\time.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +F (..\User\task\init.c)(0x695FB9FE)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/init.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\ai.h)(0x695FA26C) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\User\device\dr16.h)(0x695FAA4C) +F (..\User\task\ai.c)(0x695FB706)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/ai_1.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\device\ai.h)(0x695FA26C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +F (..\User\task\atti_esti.c)(0x695FB706)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/atti_esti.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\bsp\pwm.h)(0x695FAA4C) +I (..\Core\Inc\tim.h)(0x695FA10B) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\device\bmi088.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\ist8310.h)(0x695FAA4C) +F (..\User\task\chassis_ctrl.c)(0x695FB706)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/chassis_ctrl.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (..\User\task\dr16.c)(0x695FB964)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/dr16_1.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\device\dr16.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\module\remote_cmd.h)(0x695FB807) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\module\shoot.h)(0x69588E9B) +F (..\User\task\gimbal_ctrl.c)(0x695FBBA5)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/gimbal_ctrl.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\device\ai.h)(0x695FA26C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\module\config.h)(0x69605CCE) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\User\module\chassis.h)(0x69605BA8) +I (..\User\component\mixer.h)(0x695FAA4C) +F (..\User\task\shoot_ctrl.c)(0x695FBD1A)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/shoot_ctrl.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\module\config.h)(0x69605CCE) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\module\chassis.h)(0x69605BA8) +I (..\User\component\mixer.h)(0x695FAA4C) +F (..\User\task\user_task.c)(0x695FB706)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/user_task.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +F (..\User\task\remote.c)(0x695FB8F5)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/remote.o -MD) +I (..\User\task\user_task.h)(0x695FB706) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\User\module\remote_cmd.h)(0x695FB807) +I (..\User\device\dr16.h)(0x695FAA4C) +F (..\User\module\config.c)(0x69605DE3)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/config.o -MD) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\module\config.h)(0x69605CCE) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\User\module\chassis.h)(0x69605BA8) +I (..\User\component\mixer.h)(0x695FAA4C) +F (..\User\module\chassis.c)(0x69605BA8)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/chassis.o -MD) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdlib.h)(0x6035A4A8) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\module\chassis.h)(0x69605BA8) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\mixer.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +F (..\User\module\gimbal.c)(0x695FBD53)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/gimbal.o -MD) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\bsp\time.h)(0x695FAA4C) +F (..\User\module\remote_cmd.c)(0x69605B20)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/remote_cmd.o -MD) +I (..\User\module\remote_cmd.h)(0x695FB807) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\User\module\gimbal.h)(0x6958E7C0) +I (..\User\component\ahrs.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\device\motor_dm.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\module\shoot.h)(0x69588E9B) +I (..\User\device\dr16.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\bsp\uart.h)(0x695FAA4C) +I (..\Core\Inc\usart.h)(0x695F99C4) +I (..\User\component\crc16.h)(0x695FAA4C) +I (..\User\component\crc8.h)(0x695FAA4C) +F (..\User\module\shoot.c)(0x6958CBDF)(-xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-3 -O1 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -I ../Core/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc -I ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I ../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I ../Drivers/CMSIS/Include -I ../Middlewares/Third_Party/FreeRTOS/Source/include -I ../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2 -I ../Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F -I ../User -I ../User/bsp -I ../User/component -I ../User/task -I ../User/module -I ../User/device -I./RTE/_Infantry -ID:/Keil_v5/Arm/Packs/ARM/CMSIS/5.7.0/CMSIS/Core/Include -ID:/Keil_v5/Arm/Packs/Keil/STM32F4xx_DFP/2.17.1/Drivers/CMSIS/Device/ST/STM32F4xx/Include -D__UVISION_VERSION="534" -D_RTE_ -DSTM32F407xx -D_RTE_ -DUSE_HAL_DRIVER -DSTM32F407xx -o infantry/shoot.o -MD) +I (D:\Keil_v5\ARM\ARMCLANG\include\math.h)(0x6035A4A8) +I (D:\Keil_v5\ARM\ARMCLANG\include\string.h)(0x6035A4A8) +I (..\User\module\shoot.h)(0x69588E9B) +I (D:\Keil_v5\ARM\ARMCLANG\include\stddef.h)(0x6035A4A8) +I (..\Core\Inc\main.h)(0x695F9AF0) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h)(0x68B05645) +I (..\Core\Inc\stm32f4xx_hal_conf.h)(0x695F99C5) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h)(0x68B05645) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\core_cm4.h)(0x68B05646) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdint.h)(0x6035A4A8) +I (..\Drivers\CMSIS\Include\cmsis_version.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_compiler.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\cmsis_armclang.h)(0x68B05646) +I (..\Drivers\CMSIS\Include\mpu_armv7.h)(0x68B05646) +I (..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h)(0x68B05646) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h)(0x68B05645) +I (..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h)(0x68B05645) +I (..\User\component\pid.h)(0x695FAA4C) +I (..\User\component\filter.h)(0x695FAA4C) +I (..\User\component\user_math.h)(0x695FAA4C) +I (D:\Keil_v5\ARM\ARMCLANG\include\float.h)(0x6035A4A0) +I (D:\Keil_v5\ARM\ARMCLANG\include\stdbool.h)(0x6035A4A8) +I (..\User\device\motor_rm.h)(0x695FAA4C) +I (..\User\device\motor.h)(0x695FAA4C) +I (..\User\device\device.h)(0x695FAA4C) +I (..\User\bsp\can.h)(0x695FAA4C) +I (..\Core\Inc\can.h)(0x695F99C3) +I (..\User\bsp\bsp.h)(0x695FAA4C) +I (..\User\bsp\mm.h)(0x695FAA4C) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h)(0x68B055DB) +I (..\Core\Inc\FreeRTOSConfig.h)(0x695F9C42) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h)(0x68B055DB) +I (..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h)(0x68B055DB) +I (..\User\bsp\time.h)(0x695FAA4C) diff --git a/MDK-ARM/Infantry/ahrs.d b/MDK-ARM/Infantry/ahrs.d new file mode 100644 index 0000000..30044ef --- /dev/null +++ b/MDK-ARM/Infantry/ahrs.d @@ -0,0 +1,8 @@ +infantry/ahrs.o: ..\User\component\ahrs.c ..\User\component\ahrs.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/ahrs.o b/MDK-ARM/Infantry/ahrs.o new file mode 100644 index 0000000..bd1c5a7 Binary files /dev/null and b/MDK-ARM/Infantry/ahrs.o differ diff --git a/MDK-ARM/Infantry/ai.d b/MDK-ARM/Infantry/ai.d new file mode 100644 index 0000000..d0fd9b2 --- /dev/null +++ b/MDK-ARM/Infantry/ai.d @@ -0,0 +1,58 @@ +infantry/ai.o: ..\User\device\ai.c ..\User\device\ai.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h ..\User\component\filter.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\device\motor.h ..\User\device\device.h \ + ..\User\device\motor_dm.h ..\User\bsp\can.h ..\Core\Inc\can.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h ..\User\bsp\uart.h \ + ..\Core\Inc\usart.h ..\User\component\crc16.h diff --git a/MDK-ARM/Infantry/ai.o b/MDK-ARM/Infantry/ai.o new file mode 100644 index 0000000..596773f Binary files /dev/null and b/MDK-ARM/Infantry/ai.o differ diff --git a/MDK-ARM/Infantry/ai_1.d b/MDK-ARM/Infantry/ai_1.d new file mode 100644 index 0000000..e9bfd44 --- /dev/null +++ b/MDK-ARM/Infantry/ai_1.d @@ -0,0 +1,58 @@ +infantry/ai_1.o: ..\User\task\ai.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\device\ai.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h ..\User\component\filter.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\device\motor.h ..\User\device\device.h \ + ..\User\device\motor_dm.h ..\User\bsp\can.h ..\Core\Inc\can.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h diff --git a/MDK-ARM/Infantry/ai_1.o b/MDK-ARM/Infantry/ai_1.o new file mode 100644 index 0000000..f6304c4 Binary files /dev/null and b/MDK-ARM/Infantry/ai_1.o differ diff --git a/MDK-ARM/Infantry/atti_esti.d b/MDK-ARM/Infantry/atti_esti.d new file mode 100644 index 0000000..88c76de --- /dev/null +++ b/MDK-ARM/Infantry/atti_esti.d @@ -0,0 +1,60 @@ +infantry/atti_esti.o: ..\User\task\atti_esti.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\bsp\pwm.h ..\Core\Inc\tim.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\device\bmi088.h ..\User\device\device.h \ + ..\User\module\gimbal.h ..\User\component\filter.h \ + ..\User\device\motor.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\device\ist8310.h diff --git a/MDK-ARM/Infantry/atti_esti.o b/MDK-ARM/Infantry/atti_esti.o new file mode 100644 index 0000000..cbba545 Binary files /dev/null and b/MDK-ARM/Infantry/atti_esti.o differ diff --git a/MDK-ARM/Infantry/bmi088.d b/MDK-ARM/Infantry/bmi088.d new file mode 100644 index 0000000..65088c6 --- /dev/null +++ b/MDK-ARM/Infantry/bmi088.d @@ -0,0 +1,45 @@ +infantry/bmi088.o: ..\User\device\bmi088.c ..\User\device\bmi088.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\device\device.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\Core\Inc\gpio.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\bsp\time.h \ + ..\User\bsp\bsp.h ..\User\bsp\gpio.h ..\User\bsp\spi.h \ + ..\Core\Inc\spi.h ..\User\component\user_math.h diff --git a/MDK-ARM/Infantry/bmi088.o b/MDK-ARM/Infantry/bmi088.o new file mode 100644 index 0000000..a831d7b Binary files /dev/null and b/MDK-ARM/Infantry/bmi088.o differ diff --git a/MDK-ARM/Infantry/can.crf b/MDK-ARM/Infantry/can.crf new file mode 100644 index 0000000..9733a9f Binary files /dev/null and b/MDK-ARM/Infantry/can.crf differ diff --git a/MDK-ARM/Infantry/can.d b/MDK-ARM/Infantry/can.d new file mode 100644 index 0000000..1ae66b6 --- /dev/null +++ b/MDK-ARM/Infantry/can.d @@ -0,0 +1,35 @@ +infantry/can.o: ..\Core\Src\can.c ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/can.o b/MDK-ARM/Infantry/can.o new file mode 100644 index 0000000..0dc44aa Binary files /dev/null and b/MDK-ARM/Infantry/can.o differ diff --git a/MDK-ARM/Infantry/can_1.d b/MDK-ARM/Infantry/can_1.d new file mode 100644 index 0000000..0f8a7f0 --- /dev/null +++ b/MDK-ARM/Infantry/can_1.d @@ -0,0 +1,50 @@ +infantry/can_1.o: ..\User\bsp\can.c ..\User\bsp\can.h ..\Core\Inc\can.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/can_1.o b/MDK-ARM/Infantry/can_1.o new file mode 100644 index 0000000..993e58f Binary files /dev/null and b/MDK-ARM/Infantry/can_1.o differ diff --git a/MDK-ARM/Infantry/capacity.d b/MDK-ARM/Infantry/capacity.d new file mode 100644 index 0000000..bcf638f --- /dev/null +++ b/MDK-ARM/Infantry/capacity.d @@ -0,0 +1,7 @@ +infantry/capacity.o: ..\User\component\capacity.c \ + ..\User\component\capacity.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/capacity.o b/MDK-ARM/Infantry/capacity.o new file mode 100644 index 0000000..aaa3890 Binary files /dev/null and b/MDK-ARM/Infantry/capacity.o differ diff --git a/MDK-ARM/Infantry/chassis.d b/MDK-ARM/Infantry/chassis.d new file mode 100644 index 0000000..d88519a --- /dev/null +++ b/MDK-ARM/Infantry/chassis.d @@ -0,0 +1,58 @@ +infantry/chassis.o: ..\User\module\chassis.c \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h ..\User\bsp\mm.h \ + ..\User\bsp\can.h ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor.h \ + ..\User\module\chassis.h ..\User\component\filter.h \ + ..\User\component\mixer.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\component\ahrs.h diff --git a/MDK-ARM/Infantry/chassis.o b/MDK-ARM/Infantry/chassis.o new file mode 100644 index 0000000..9561654 Binary files /dev/null and b/MDK-ARM/Infantry/chassis.o differ diff --git a/MDK-ARM/Infantry/chassis_ctrl.d b/MDK-ARM/Infantry/chassis_ctrl.d new file mode 100644 index 0000000..044f439 --- /dev/null +++ b/MDK-ARM/Infantry/chassis_ctrl.d @@ -0,0 +1,14 @@ +infantry/chassis_ctrl.o: ..\User\task\chassis_ctrl.c \ + ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/chassis_ctrl.o b/MDK-ARM/Infantry/chassis_ctrl.o new file mode 100644 index 0000000..6345576 Binary files /dev/null and b/MDK-ARM/Infantry/chassis_ctrl.o differ diff --git a/MDK-ARM/Infantry/cmd.d b/MDK-ARM/Infantry/cmd.d new file mode 100644 index 0000000..8e10e16 --- /dev/null +++ b/MDK-ARM/Infantry/cmd.d @@ -0,0 +1,8 @@ +infantry/cmd.o: ..\User\component\cmd.c ..\User\component\cmd.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/cmd.o b/MDK-ARM/Infantry/cmd.o new file mode 100644 index 0000000..c0f74be Binary files /dev/null and b/MDK-ARM/Infantry/cmd.o differ diff --git a/MDK-ARM/Infantry/cmsis_os2.crf b/MDK-ARM/Infantry/cmsis_os2.crf new file mode 100644 index 0000000..2e8126d Binary files /dev/null and b/MDK-ARM/Infantry/cmsis_os2.crf differ diff --git a/MDK-ARM/Infantry/cmsis_os2.d b/MDK-ARM/Infantry/cmsis_os2.d new file mode 100644 index 0000000..293d688 --- /dev/null +++ b/MDK-ARM/Infantry/cmsis_os2.d @@ -0,0 +1,55 @@ +infantry/cmsis_os2.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_mpool.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\freertos_os2.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/cmsis_os2.o b/MDK-ARM/Infantry/cmsis_os2.o new file mode 100644 index 0000000..2951888 Binary files /dev/null and b/MDK-ARM/Infantry/cmsis_os2.o differ diff --git a/MDK-ARM/Infantry/config.d b/MDK-ARM/Infantry/config.d new file mode 100644 index 0000000..71162c0 --- /dev/null +++ b/MDK-ARM/Infantry/config.d @@ -0,0 +1,61 @@ +infantry/config.o: ..\User\module\config.c ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\module\config.h ..\User\module\gimbal.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + ..\User\component\filter.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\module\shoot.h ..\Core\Inc\main.h ..\User\module\chassis.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\component\filter.h ..\User\component\mixer.h \ + ..\User\component\pid.h ..\User\component\ahrs.h diff --git a/MDK-ARM/Infantry/config.o b/MDK-ARM/Infantry/config.o new file mode 100644 index 0000000..24144bf Binary files /dev/null and b/MDK-ARM/Infantry/config.o differ diff --git a/MDK-ARM/Infantry/crc16.d b/MDK-ARM/Infantry/crc16.d new file mode 100644 index 0000000..aba28f3 --- /dev/null +++ b/MDK-ARM/Infantry/crc16.d @@ -0,0 +1,7 @@ +infantry/crc16.o: ..\User\component\crc16.c ..\User\component\crc16.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/crc16.o b/MDK-ARM/Infantry/crc16.o new file mode 100644 index 0000000..bdaf776 Binary files /dev/null and b/MDK-ARM/Infantry/crc16.o differ diff --git a/MDK-ARM/Infantry/crc8.d b/MDK-ARM/Infantry/crc8.d new file mode 100644 index 0000000..697a747 --- /dev/null +++ b/MDK-ARM/Infantry/crc8.d @@ -0,0 +1,4 @@ +infantry/crc8.o: ..\User\component\crc8.c ..\User\component\crc8.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h diff --git a/MDK-ARM/Infantry/crc8.o b/MDK-ARM/Infantry/crc8.o new file mode 100644 index 0000000..3954a58 Binary files /dev/null and b/MDK-ARM/Infantry/crc8.o differ diff --git a/MDK-ARM/Infantry/croutine.crf b/MDK-ARM/Infantry/croutine.crf new file mode 100644 index 0000000..7274e32 Binary files /dev/null and b/MDK-ARM/Infantry/croutine.crf differ diff --git a/MDK-ARM/Infantry/croutine.d b/MDK-ARM/Infantry/croutine.d new file mode 100644 index 0000000..5ea88d6 --- /dev/null +++ b/MDK-ARM/Infantry/croutine.d @@ -0,0 +1,14 @@ +infantry/croutine.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\croutine.c \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h diff --git a/MDK-ARM/Infantry/croutine.o b/MDK-ARM/Infantry/croutine.o new file mode 100644 index 0000000..cbbdd9b Binary files /dev/null and b/MDK-ARM/Infantry/croutine.o differ diff --git a/MDK-ARM/Infantry/dma.crf b/MDK-ARM/Infantry/dma.crf new file mode 100644 index 0000000..5902aee Binary files /dev/null and b/MDK-ARM/Infantry/dma.crf differ diff --git a/MDK-ARM/Infantry/dma.d b/MDK-ARM/Infantry/dma.d new file mode 100644 index 0000000..d12fd84 --- /dev/null +++ b/MDK-ARM/Infantry/dma.d @@ -0,0 +1,35 @@ +infantry/dma.o: ..\Core\Src\dma.c ..\Core\Inc\dma.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/dma.o b/MDK-ARM/Infantry/dma.o new file mode 100644 index 0000000..9d1ff89 Binary files /dev/null and b/MDK-ARM/Infantry/dma.o differ diff --git a/MDK-ARM/Infantry/dr16.d b/MDK-ARM/Infantry/dr16.d new file mode 100644 index 0000000..a09398a --- /dev/null +++ b/MDK-ARM/Infantry/dr16.d @@ -0,0 +1,43 @@ +infantry/dr16.o: ..\User\device\dr16.c ..\User\device\dr16.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\device\device.h ..\User\bsp\uart.h ..\Core\Inc\usart.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\time.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/dr16.o b/MDK-ARM/Infantry/dr16.o new file mode 100644 index 0000000..97a1595 Binary files /dev/null and b/MDK-ARM/Infantry/dr16.o differ diff --git a/MDK-ARM/Infantry/dr16_1.d b/MDK-ARM/Infantry/dr16_1.d new file mode 100644 index 0000000..59dc57a --- /dev/null +++ b/MDK-ARM/Infantry/dr16_1.d @@ -0,0 +1,61 @@ +infantry/dr16_1.o: ..\User\task\dr16.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\device\dr16.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\device\device.h ..\User\module\remote_cmd.h \ + ..\User\component\user_math.h ..\User\module\gimbal.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + ..\User\component\filter.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\module\shoot.h ..\Core\Inc\main.h ..\User\device\dr16.h diff --git a/MDK-ARM/Infantry/dr16_1.o b/MDK-ARM/Infantry/dr16_1.o new file mode 100644 index 0000000..76deaea Binary files /dev/null and b/MDK-ARM/Infantry/dr16_1.o differ diff --git a/MDK-ARM/Infantry/error_detect.d b/MDK-ARM/Infantry/error_detect.d new file mode 100644 index 0000000..a3bea7b --- /dev/null +++ b/MDK-ARM/Infantry/error_detect.d @@ -0,0 +1,6 @@ +infantry/error_detect.o: ..\User\component\error_detect.c \ + ..\User\component\error_detect.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\bsp\mm.h diff --git a/MDK-ARM/Infantry/error_detect.o b/MDK-ARM/Infantry/error_detect.o new file mode 100644 index 0000000..55aa368 Binary files /dev/null and b/MDK-ARM/Infantry/error_detect.o differ diff --git a/MDK-ARM/Infantry/event_groups.crf b/MDK-ARM/Infantry/event_groups.crf new file mode 100644 index 0000000..0f82702 Binary files /dev/null and b/MDK-ARM/Infantry/event_groups.crf differ diff --git a/MDK-ARM/Infantry/event_groups.d b/MDK-ARM/Infantry/event_groups.d new file mode 100644 index 0000000..2a883d2 --- /dev/null +++ b/MDK-ARM/Infantry/event_groups.d @@ -0,0 +1,18 @@ +infantry/event_groups.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\event_groups.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h diff --git a/MDK-ARM/Infantry/event_groups.o b/MDK-ARM/Infantry/event_groups.o new file mode 100644 index 0000000..4652354 Binary files /dev/null and b/MDK-ARM/Infantry/event_groups.o differ diff --git a/MDK-ARM/Infantry/filter.d b/MDK-ARM/Infantry/filter.d new file mode 100644 index 0000000..75c2a1f --- /dev/null +++ b/MDK-ARM/Infantry/filter.d @@ -0,0 +1,7 @@ +infantry/filter.o: ..\User\component\filter.c ..\User\component\filter.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/filter.o b/MDK-ARM/Infantry/filter.o new file mode 100644 index 0000000..7c3a44c Binary files /dev/null and b/MDK-ARM/Infantry/filter.o differ diff --git a/MDK-ARM/Infantry/freertos.crf b/MDK-ARM/Infantry/freertos.crf new file mode 100644 index 0000000..a20be28 Binary files /dev/null and b/MDK-ARM/Infantry/freertos.crf differ diff --git a/MDK-ARM/Infantry/freertos.d b/MDK-ARM/Infantry/freertos.d new file mode 100644 index 0000000..a938d66 --- /dev/null +++ b/MDK-ARM/Infantry/freertos.d @@ -0,0 +1,48 @@ +infantry/freertos.o: ..\Core\Src\freertos.c \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h diff --git a/MDK-ARM/Infantry/freertos.o b/MDK-ARM/Infantry/freertos.o new file mode 100644 index 0000000..3fbe947 Binary files /dev/null and b/MDK-ARM/Infantry/freertos.o differ diff --git a/MDK-ARM/Infantry/freertos_cli.d b/MDK-ARM/Infantry/freertos_cli.d new file mode 100644 index 0000000..7da289c --- /dev/null +++ b/MDK-ARM/Infantry/freertos_cli.d @@ -0,0 +1,14 @@ +infantry/freertos_cli.o: ..\User\component\freertos_cli.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\component\FreeRTOS_CLI.h diff --git a/MDK-ARM/Infantry/freertos_cli.o b/MDK-ARM/Infantry/freertos_cli.o new file mode 100644 index 0000000..0663d85 Binary files /dev/null and b/MDK-ARM/Infantry/freertos_cli.o differ diff --git a/MDK-ARM/Infantry/gimbal.d b/MDK-ARM/Infantry/gimbal.d new file mode 100644 index 0000000..d8ac720 --- /dev/null +++ b/MDK-ARM/Infantry/gimbal.d @@ -0,0 +1,56 @@ +infantry/gimbal.o: ..\User\module\gimbal.c ..\User\module\gimbal.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\component\filter.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h ..\User\bsp\time.h diff --git a/MDK-ARM/Infantry/gimbal.o b/MDK-ARM/Infantry/gimbal.o new file mode 100644 index 0000000..685cc98 Binary files /dev/null and b/MDK-ARM/Infantry/gimbal.o differ diff --git a/MDK-ARM/Infantry/gimbal_ctrl.d b/MDK-ARM/Infantry/gimbal_ctrl.d new file mode 100644 index 0000000..0e12c7c --- /dev/null +++ b/MDK-ARM/Infantry/gimbal_ctrl.d @@ -0,0 +1,63 @@ +infantry/gimbal_ctrl.o: ..\User\task\gimbal_ctrl.c \ + ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\device\ai.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h ..\User\component\filter.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\device\motor.h ..\User\device\device.h \ + ..\User\device\motor_dm.h ..\User\bsp\can.h ..\Core\Inc\can.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\module\config.h ..\User\module\gimbal.h ..\User\module\shoot.h \ + ..\Core\Inc\main.h ..\User\module\chassis.h ..\User\component\filter.h \ + ..\User\component\mixer.h ..\User\component\pid.h \ + ..\User\component\ahrs.h diff --git a/MDK-ARM/Infantry/gimbal_ctrl.o b/MDK-ARM/Infantry/gimbal_ctrl.o new file mode 100644 index 0000000..b34549f Binary files /dev/null and b/MDK-ARM/Infantry/gimbal_ctrl.o differ diff --git a/MDK-ARM/Infantry/gpio.crf b/MDK-ARM/Infantry/gpio.crf new file mode 100644 index 0000000..7331319 Binary files /dev/null and b/MDK-ARM/Infantry/gpio.crf differ diff --git a/MDK-ARM/Infantry/gpio.d b/MDK-ARM/Infantry/gpio.d new file mode 100644 index 0000000..77761a8 --- /dev/null +++ b/MDK-ARM/Infantry/gpio.d @@ -0,0 +1,35 @@ +infantry/gpio.o: ..\Core\Src\gpio.c ..\Core\Inc\gpio.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/gpio.o b/MDK-ARM/Infantry/gpio.o new file mode 100644 index 0000000..d31a6b5 Binary files /dev/null and b/MDK-ARM/Infantry/gpio.o differ diff --git a/MDK-ARM/Infantry/gpio_1.d b/MDK-ARM/Infantry/gpio_1.d new file mode 100644 index 0000000..60fac5f --- /dev/null +++ b/MDK-ARM/Infantry/gpio_1.d @@ -0,0 +1,38 @@ +infantry/gpio_1.o: ..\User\bsp\gpio.c ..\User\bsp\gpio.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h ..\User\bsp\bsp.h \ + ..\Core\Inc\gpio.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\Core\Inc\main.h diff --git a/MDK-ARM/Infantry/gpio_1.o b/MDK-ARM/Infantry/gpio_1.o new file mode 100644 index 0000000..d199a86 Binary files /dev/null and b/MDK-ARM/Infantry/gpio_1.o differ diff --git a/MDK-ARM/Infantry/heap_4.crf b/MDK-ARM/Infantry/heap_4.crf new file mode 100644 index 0000000..5cd4c1b Binary files /dev/null and b/MDK-ARM/Infantry/heap_4.crf differ diff --git a/MDK-ARM/Infantry/heap_4.d b/MDK-ARM/Infantry/heap_4.d new file mode 100644 index 0000000..919ea85 --- /dev/null +++ b/MDK-ARM/Infantry/heap_4.d @@ -0,0 +1,14 @@ +infantry/heap_4.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/heap_4.o b/MDK-ARM/Infantry/heap_4.o new file mode 100644 index 0000000..2dadaea Binary files /dev/null and b/MDK-ARM/Infantry/heap_4.o differ diff --git a/MDK-ARM/Infantry/i2c.crf b/MDK-ARM/Infantry/i2c.crf new file mode 100644 index 0000000..86a4c7f Binary files /dev/null and b/MDK-ARM/Infantry/i2c.crf differ diff --git a/MDK-ARM/Infantry/i2c.d b/MDK-ARM/Infantry/i2c.d new file mode 100644 index 0000000..a9ea83d --- /dev/null +++ b/MDK-ARM/Infantry/i2c.d @@ -0,0 +1,35 @@ +infantry/i2c.o: ..\Core\Src\i2c.c ..\Core\Inc\i2c.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/i2c.o b/MDK-ARM/Infantry/i2c.o new file mode 100644 index 0000000..1a47a7e Binary files /dev/null and b/MDK-ARM/Infantry/i2c.o differ diff --git a/MDK-ARM/Infantry/i2c_1.d b/MDK-ARM/Infantry/i2c_1.d new file mode 100644 index 0000000..d87dd7d --- /dev/null +++ b/MDK-ARM/Infantry/i2c_1.d @@ -0,0 +1,36 @@ +infantry/i2c_1.o: ..\User\bsp\i2c.c ..\User\bsp\i2c.h ..\Core\Inc\i2c.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h ..\User\bsp\bsp.h diff --git a/MDK-ARM/Infantry/i2c_1.o b/MDK-ARM/Infantry/i2c_1.o new file mode 100644 index 0000000..527a478 Binary files /dev/null and b/MDK-ARM/Infantry/i2c_1.o differ diff --git a/MDK-ARM/Infantry/init.d b/MDK-ARM/Infantry/init.d new file mode 100644 index 0000000..794fcd5 --- /dev/null +++ b/MDK-ARM/Infantry/init.d @@ -0,0 +1,61 @@ +infantry/init.o: ..\User\task\init.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\component\filter.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h ..\User\device\ai.h \ + ..\User\component\user_math.h ..\User\module\shoot.h \ + ..\Core\Inc\main.h ..\User\device\dr16.h ..\User\component\user_math.h \ + ..\User\device\device.h diff --git a/MDK-ARM/Infantry/init.o b/MDK-ARM/Infantry/init.o new file mode 100644 index 0000000..6839701 Binary files /dev/null and b/MDK-ARM/Infantry/init.o differ diff --git a/MDK-ARM/Infantry/ist8310.d b/MDK-ARM/Infantry/ist8310.d new file mode 100644 index 0000000..e641f0e --- /dev/null +++ b/MDK-ARM/Infantry/ist8310.d @@ -0,0 +1,44 @@ +infantry/ist8310.o: ..\User\device\ist8310.c ..\User\device\ist8310.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\component\ahrs.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h ..\User\device\device.h \ + ..\Core\Inc\gpio.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\bsp\time.h \ + ..\User\bsp\bsp.h ..\User\bsp\gpio.h ..\User\bsp\i2c.h \ + ..\Core\Inc\i2c.h diff --git a/MDK-ARM/Infantry/ist8310.o b/MDK-ARM/Infantry/ist8310.o new file mode 100644 index 0000000..692d6bd Binary files /dev/null and b/MDK-ARM/Infantry/ist8310.o differ diff --git a/MDK-ARM/Infantry/limiter.d b/MDK-ARM/Infantry/limiter.d new file mode 100644 index 0000000..0ae5a17 --- /dev/null +++ b/MDK-ARM/Infantry/limiter.d @@ -0,0 +1,6 @@ +infantry/limiter.o: ..\User\component\limiter.c \ + ..\User\component\limiter.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/limiter.o b/MDK-ARM/Infantry/limiter.o new file mode 100644 index 0000000..5d13ab2 Binary files /dev/null and b/MDK-ARM/Infantry/limiter.o differ diff --git a/MDK-ARM/Infantry/list.crf b/MDK-ARM/Infantry/list.crf new file mode 100644 index 0000000..3f23ed8 Binary files /dev/null and b/MDK-ARM/Infantry/list.crf differ diff --git a/MDK-ARM/Infantry/list.d b/MDK-ARM/Infantry/list.d new file mode 100644 index 0000000..2de2f96 --- /dev/null +++ b/MDK-ARM/Infantry/list.d @@ -0,0 +1,12 @@ +infantry/list.o: ..\Middlewares\Third_Party\FreeRTOS\Source\list.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/list.o b/MDK-ARM/Infantry/list.o new file mode 100644 index 0000000..3bab9a2 Binary files /dev/null and b/MDK-ARM/Infantry/list.o differ diff --git a/MDK-ARM/Infantry/main.crf b/MDK-ARM/Infantry/main.crf new file mode 100644 index 0000000..f42b5c7 Binary files /dev/null and b/MDK-ARM/Infantry/main.crf differ diff --git a/MDK-ARM/Infantry/main.d b/MDK-ARM/Infantry/main.d new file mode 100644 index 0000000..1584ad9 --- /dev/null +++ b/MDK-ARM/Infantry/main.d @@ -0,0 +1,49 @@ +infantry/main.o: ..\Core\Src\main.c ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h ..\Core\Inc\dma.h \ + ..\Core\Inc\i2c.h ..\Core\Inc\spi.h ..\Core\Inc\tim.h \ + ..\Core\Inc\usart.h ..\Core\Inc\gpio.h diff --git a/MDK-ARM/Infantry/main.o b/MDK-ARM/Infantry/main.o new file mode 100644 index 0000000..cb8d852 Binary files /dev/null and b/MDK-ARM/Infantry/main.o differ diff --git a/MDK-ARM/Infantry/mixer.d b/MDK-ARM/Infantry/mixer.d new file mode 100644 index 0000000..3cc8d50 --- /dev/null +++ b/MDK-ARM/Infantry/mixer.d @@ -0,0 +1,7 @@ +infantry/mixer.o: ..\User\component\mixer.c ..\User\component\mixer.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/mixer.o b/MDK-ARM/Infantry/mixer.o new file mode 100644 index 0000000..e463779 Binary files /dev/null and b/MDK-ARM/Infantry/mixer.o differ diff --git a/MDK-ARM/Infantry/mm.d b/MDK-ARM/Infantry/mm.d new file mode 100644 index 0000000..70a591f --- /dev/null +++ b/MDK-ARM/Infantry/mm.d @@ -0,0 +1,10 @@ +infantry/mm.o: ..\User\bsp\mm.c ..\User\bsp\mm.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h diff --git a/MDK-ARM/Infantry/mm.o b/MDK-ARM/Infantry/mm.o new file mode 100644 index 0000000..7a1b211 Binary files /dev/null and b/MDK-ARM/Infantry/mm.o differ diff --git a/MDK-ARM/Infantry/motor.d b/MDK-ARM/Infantry/motor.d new file mode 100644 index 0000000..7a51c71 --- /dev/null +++ b/MDK-ARM/Infantry/motor.d @@ -0,0 +1,5 @@ +infantry/motor.o: ..\User\device\motor.c ..\User\device\motor.h \ + ..\User\device\device.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/motor.o b/MDK-ARM/Infantry/motor.o new file mode 100644 index 0000000..aeba122 Binary files /dev/null and b/MDK-ARM/Infantry/motor.o differ diff --git a/MDK-ARM/Infantry/motor_dm.d b/MDK-ARM/Infantry/motor_dm.d new file mode 100644 index 0000000..059529e --- /dev/null +++ b/MDK-ARM/Infantry/motor_dm.d @@ -0,0 +1,54 @@ +infantry/motor_dm.o: ..\User\device\motor_dm.c ..\User\device\motor_dm.h \ + ..\User\device\device.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h ..\User\device\motor.h \ + ..\User\bsp\can.h ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\bsp\time.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/motor_dm.o b/MDK-ARM/Infantry/motor_dm.o new file mode 100644 index 0000000..9969158 Binary files /dev/null and b/MDK-ARM/Infantry/motor_dm.o differ diff --git a/MDK-ARM/Infantry/motor_rm.d b/MDK-ARM/Infantry/motor_rm.d new file mode 100644 index 0000000..2240f6d --- /dev/null +++ b/MDK-ARM/Infantry/motor_rm.d @@ -0,0 +1,54 @@ +infantry/motor_rm.o: ..\User\device\motor_rm.c ..\User\device\motor_rm.h \ + ..\User\device\motor.h ..\User\device\device.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h ..\User\device\motor.h \ + ..\User\bsp\can.h ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\bsp\time.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h diff --git a/MDK-ARM/Infantry/motor_rm.o b/MDK-ARM/Infantry/motor_rm.o new file mode 100644 index 0000000..afa6974 Binary files /dev/null and b/MDK-ARM/Infantry/motor_rm.o differ diff --git a/MDK-ARM/Infantry/pid.d b/MDK-ARM/Infantry/pid.d new file mode 100644 index 0000000..f5e617c --- /dev/null +++ b/MDK-ARM/Infantry/pid.d @@ -0,0 +1,7 @@ +infantry/pid.o: ..\User\component\pid.c ..\User\component\pid.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\User\component\filter.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h diff --git a/MDK-ARM/Infantry/pid.o b/MDK-ARM/Infantry/pid.o new file mode 100644 index 0000000..a973eef Binary files /dev/null and b/MDK-ARM/Infantry/pid.o differ diff --git a/MDK-ARM/Infantry/port.d b/MDK-ARM/Infantry/port.d new file mode 100644 index 0000000..9b86332 --- /dev/null +++ b/MDK-ARM/Infantry/port.d @@ -0,0 +1,13 @@ +infantry/port.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\port.c \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/port.o b/MDK-ARM/Infantry/port.o new file mode 100644 index 0000000..69fe1af Binary files /dev/null and b/MDK-ARM/Infantry/port.o differ diff --git a/MDK-ARM/Infantry/pwm.d b/MDK-ARM/Infantry/pwm.d new file mode 100644 index 0000000..b5a5db0 --- /dev/null +++ b/MDK-ARM/Infantry/pwm.d @@ -0,0 +1,36 @@ +infantry/pwm.o: ..\User\bsp\pwm.c ..\Core\Inc\tim.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\pwm.h ..\User\bsp\bsp.h diff --git a/MDK-ARM/Infantry/pwm.o b/MDK-ARM/Infantry/pwm.o new file mode 100644 index 0000000..c080142 Binary files /dev/null and b/MDK-ARM/Infantry/pwm.o differ diff --git a/MDK-ARM/Infantry/queue.crf b/MDK-ARM/Infantry/queue.crf new file mode 100644 index 0000000..9126ad8 Binary files /dev/null and b/MDK-ARM/Infantry/queue.crf differ diff --git a/MDK-ARM/Infantry/queue.d b/MDK-ARM/Infantry/queue.d new file mode 100644 index 0000000..252c382 --- /dev/null +++ b/MDK-ARM/Infantry/queue.d @@ -0,0 +1,16 @@ +infantry/queue.o: ..\Middlewares\Third_Party\FreeRTOS\Source\queue.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h diff --git a/MDK-ARM/Infantry/queue.o b/MDK-ARM/Infantry/queue.o new file mode 100644 index 0000000..9e477d8 Binary files /dev/null and b/MDK-ARM/Infantry/queue.o differ diff --git a/MDK-ARM/Infantry/remote.d b/MDK-ARM/Infantry/remote.d new file mode 100644 index 0000000..9db6615 --- /dev/null +++ b/MDK-ARM/Infantry/remote.d @@ -0,0 +1,63 @@ +infantry/remote.o: ..\User\task\remote.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\component\filter.h ..\User\component\pid.h \ + ..\User\component\filter.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor_dm.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\module\shoot.h ..\Core\Inc\main.h ..\User\module\remote_cmd.h \ + ..\User\component\user_math.h ..\User\module\gimbal.h \ + ..\User\module\shoot.h ..\User\device\dr16.h \ + ..\User\component\user_math.h ..\User\device\device.h \ + ..\User\device\dr16.h diff --git a/MDK-ARM/Infantry/remote.o b/MDK-ARM/Infantry/remote.o new file mode 100644 index 0000000..967059f Binary files /dev/null and b/MDK-ARM/Infantry/remote.o differ diff --git a/MDK-ARM/Infantry/remote_cmd.d b/MDK-ARM/Infantry/remote_cmd.d new file mode 100644 index 0000000..ba858c8 --- /dev/null +++ b/MDK-ARM/Infantry/remote_cmd.d @@ -0,0 +1,63 @@ +infantry/remote_cmd.o: ..\User\module\remote_cmd.c \ + ..\User\module\remote_cmd.h ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\User\module\gimbal.h ..\User\component\ahrs.h \ + ..\User\component\user_math.h ..\User\component\filter.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\device\motor.h ..\User\device\device.h \ + ..\User\device\motor_dm.h ..\User\bsp\can.h ..\Core\Inc\can.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\bsp.h ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\module\shoot.h ..\Core\Inc\main.h ..\User\device\dr16.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\component\user_math.h ..\User\device\device.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\bsp\uart.h \ + ..\Core\Inc\usart.h ..\User\component\crc16.h ..\User\component\crc8.h \ + ..\User\device\dr16.h diff --git a/MDK-ARM/Infantry/remote_cmd.o b/MDK-ARM/Infantry/remote_cmd.o new file mode 100644 index 0000000..8364195 Binary files /dev/null and b/MDK-ARM/Infantry/remote_cmd.o differ diff --git a/MDK-ARM/Infantry/shoot.d b/MDK-ARM/Infantry/shoot.d new file mode 100644 index 0000000..2b0ed80 --- /dev/null +++ b/MDK-ARM/Infantry/shoot.d @@ -0,0 +1,58 @@ +infantry/shoot.o: ..\User\module\shoot.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h ..\User\module\shoot.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h ..\User\bsp\bsp.h \ + ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\bsp\time.h ..\User\component\filter.h \ + ..\User\component\user_math.h diff --git a/MDK-ARM/Infantry/shoot.o b/MDK-ARM/Infantry/shoot.o new file mode 100644 index 0000000..6e6ed55 Binary files /dev/null and b/MDK-ARM/Infantry/shoot.o differ diff --git a/MDK-ARM/Infantry/shoot_ctrl.d b/MDK-ARM/Infantry/shoot_ctrl.d new file mode 100644 index 0000000..96fefae --- /dev/null +++ b/MDK-ARM/Infantry/shoot_ctrl.d @@ -0,0 +1,63 @@ +infantry/shoot_ctrl.o: ..\User\task\shoot_ctrl.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\module\shoot.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\component\pid.h ..\User\component\filter.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\device\motor_rm.h ..\User\device\motor.h \ + ..\User\device\device.h ..\User\device\motor.h ..\User\bsp\can.h \ + ..\Core\Inc\can.h ..\Core\Inc\main.h ..\User\bsp\bsp.h \ + ..\User\bsp\mm.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + ..\User\module\config.h ..\User\module\gimbal.h \ + ..\User\component\ahrs.h ..\User\component\filter.h \ + ..\User\device\motor_dm.h ..\User\module\shoot.h \ + ..\User\module\chassis.h ..\User\component\filter.h \ + ..\User\component\mixer.h ..\User\component\pid.h \ + ..\User\component\ahrs.h diff --git a/MDK-ARM/Infantry/shoot_ctrl.o b/MDK-ARM/Infantry/shoot_ctrl.o new file mode 100644 index 0000000..fb8471c Binary files /dev/null and b/MDK-ARM/Infantry/shoot_ctrl.o differ diff --git a/MDK-ARM/Infantry/spi.crf b/MDK-ARM/Infantry/spi.crf new file mode 100644 index 0000000..9e0fb61 Binary files /dev/null and b/MDK-ARM/Infantry/spi.crf differ diff --git a/MDK-ARM/Infantry/spi.d b/MDK-ARM/Infantry/spi.d new file mode 100644 index 0000000..1fa4271 --- /dev/null +++ b/MDK-ARM/Infantry/spi.d @@ -0,0 +1,35 @@ +infantry/spi.o: ..\Core\Src\spi.c ..\Core\Inc\spi.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/spi.o b/MDK-ARM/Infantry/spi.o new file mode 100644 index 0000000..5fb4f91 Binary files /dev/null and b/MDK-ARM/Infantry/spi.o differ diff --git a/MDK-ARM/Infantry/spi_1.d b/MDK-ARM/Infantry/spi_1.d new file mode 100644 index 0000000..f7bc55b --- /dev/null +++ b/MDK-ARM/Infantry/spi_1.d @@ -0,0 +1,37 @@ +infantry/spi_1.o: ..\User\bsp\spi.c ..\Core\Inc\spi.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\spi.h D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\bsp\bsp.h diff --git a/MDK-ARM/Infantry/spi_1.o b/MDK-ARM/Infantry/spi_1.o new file mode 100644 index 0000000..13d782a Binary files /dev/null and b/MDK-ARM/Infantry/spi_1.o differ diff --git a/MDK-ARM/Infantry/startup_stm32f407xx.d b/MDK-ARM/Infantry/startup_stm32f407xx.d new file mode 100644 index 0000000..da0b261 --- /dev/null +++ b/MDK-ARM/Infantry/startup_stm32f407xx.d @@ -0,0 +1 @@ +infantry\startup_stm32f407xx.o: startup_stm32f407xx.s diff --git a/MDK-ARM/Infantry/startup_stm32f407xx.o b/MDK-ARM/Infantry/startup_stm32f407xx.o new file mode 100644 index 0000000..a4651f3 Binary files /dev/null and b/MDK-ARM/Infantry/startup_stm32f407xx.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal.crf b/MDK-ARM/Infantry/stm32f4xx_hal.crf new file mode 100644 index 0000000..df95d93 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal.d b/MDK-ARM/Infantry/stm32f4xx_hal.d new file mode 100644 index 0000000..53745bd --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal.o b/MDK-ARM/Infantry/stm32f4xx_hal.o new file mode 100644 index 0000000..3bac706 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_can.crf b/MDK-ARM/Infantry/stm32f4xx_hal_can.crf new file mode 100644 index 0000000..d778369 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_can.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_can.d b/MDK-ARM/Infantry/stm32f4xx_hal_can.d new file mode 100644 index 0000000..8395be4 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_can.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_can.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_can.o b/MDK-ARM/Infantry/stm32f4xx_hal_can.o new file mode 100644 index 0000000..d0ca9d4 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_can.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_cortex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.crf new file mode 100644 index 0000000..61242e0 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_cortex.d b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.d new file mode 100644 index 0000000..75df3b9 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_cortex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_cortex.o b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.o new file mode 100644 index 0000000..33a3787 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_cortex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma.crf b/MDK-ARM/Infantry/stm32f4xx_hal_dma.crf new file mode 100644 index 0000000..7bc7e33 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_dma.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma.d b/MDK-ARM/Infantry/stm32f4xx_hal_dma.d new file mode 100644 index 0000000..ab91cb0 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_dma.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_dma.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma.o b/MDK-ARM/Infantry/stm32f4xx_hal_dma.o new file mode 100644 index 0000000..3e1df80 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_dma.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.crf new file mode 100644 index 0000000..ca474a0 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.d new file mode 100644 index 0000000..78ace5e --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_dma_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.o new file mode 100644 index 0000000..a7b5140 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_dma_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_exti.crf b/MDK-ARM/Infantry/stm32f4xx_hal_exti.crf new file mode 100644 index 0000000..ceb702a Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_exti.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_exti.d b/MDK-ARM/Infantry/stm32f4xx_hal_exti.d new file mode 100644 index 0000000..08a60bf --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_exti.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_exti.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_exti.o b/MDK-ARM/Infantry/stm32f4xx_hal_exti.o new file mode 100644 index 0000000..bc806d1 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_exti.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash.crf b/MDK-ARM/Infantry/stm32f4xx_hal_flash.crf new file mode 100644 index 0000000..7333c83 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash.d b/MDK-ARM/Infantry/stm32f4xx_hal_flash.d new file mode 100644 index 0000000..2c828ad --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_flash.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_flash.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash.o b/MDK-ARM/Infantry/stm32f4xx_hal_flash.o new file mode 100644 index 0000000..750c3f4 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.crf new file mode 100644 index 0000000..1949497 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.d new file mode 100644 index 0000000..727f601 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_flash_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.o new file mode 100644 index 0000000..51381fc Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.crf b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.crf new file mode 100644 index 0000000..cba8ade Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.d b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.d new file mode 100644 index 0000000..82d09dd --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_flash_ramfunc.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.o b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.o new file mode 100644 index 0000000..0178bc4 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_gpio.crf b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.crf new file mode 100644 index 0000000..29d8d1d Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_gpio.d b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.d new file mode 100644 index 0000000..5a31d8e --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_gpio.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_gpio.o b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.o new file mode 100644 index 0000000..e8130b2 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_gpio.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c.crf b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.crf new file mode 100644 index 0000000..5b6a500 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c.d b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.d new file mode 100644 index 0000000..6173bb7 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_i2c.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c.o b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.o new file mode 100644 index 0000000..8b7ae35 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_i2c.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.crf new file mode 100644 index 0000000..66d934d Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.d new file mode 100644 index 0000000..8b539cd --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_i2c_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_i2c_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.o new file mode 100644 index 0000000..5e89720 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_i2c_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_msp.crf b/MDK-ARM/Infantry/stm32f4xx_hal_msp.crf new file mode 100644 index 0000000..6839f24 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_msp.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_msp.d b/MDK-ARM/Infantry/stm32f4xx_hal_msp.d new file mode 100644 index 0000000..4fc1833 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_msp.d @@ -0,0 +1,35 @@ +infantry/stm32f4xx_hal_msp.o: ..\Core\Src\stm32f4xx_hal_msp.c \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_msp.o b/MDK-ARM/Infantry/stm32f4xx_hal_msp.o new file mode 100644 index 0000000..af9f9f0 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_msp.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr.crf b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.crf new file mode 100644 index 0000000..cfb0e3f Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr.d b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.d new file mode 100644 index 0000000..f850dc3 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_pwr.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr.o b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.o new file mode 100644 index 0000000..6cea13c Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_pwr.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.crf new file mode 100644 index 0000000..913029e Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.d new file mode 100644 index 0000000..00580c8 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_pwr_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.o new file mode 100644 index 0000000..13bfbe6 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_pwr_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc.crf b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.crf new file mode 100644 index 0000000..b546ae0 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc.d b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.d new file mode 100644 index 0000000..511fb1d --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_rcc.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc.o b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.o new file mode 100644 index 0000000..66395fa Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_rcc.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.crf new file mode 100644 index 0000000..0b41c19 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.d new file mode 100644 index 0000000..387d394 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_rcc_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.o new file mode 100644 index 0000000..fb8f427 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_rcc_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_spi.crf b/MDK-ARM/Infantry/stm32f4xx_hal_spi.crf new file mode 100644 index 0000000..b6a459a Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_spi.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_spi.d b/MDK-ARM/Infantry/stm32f4xx_hal_spi.d new file mode 100644 index 0000000..696f484 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_spi.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_spi.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_spi.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_spi.o b/MDK-ARM/Infantry/stm32f4xx_hal_spi.o new file mode 100644 index 0000000..1f3703a Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_spi.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim.crf b/MDK-ARM/Infantry/stm32f4xx_hal_tim.crf new file mode 100644 index 0000000..5b196df Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_tim.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim.d b/MDK-ARM/Infantry/stm32f4xx_hal_tim.d new file mode 100644 index 0000000..858d5d4 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_tim.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_tim.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim.o b/MDK-ARM/Infantry/stm32f4xx_hal_tim.o new file mode 100644 index 0000000..b0725c5 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_tim.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.crf b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.crf new file mode 100644 index 0000000..466fdb0 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.d b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.d new file mode 100644 index 0000000..7eafd4b --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_tim_ex.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.o b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.o new file mode 100644 index 0000000..5f8eba1 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_tim_ex.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_uart.crf b/MDK-ARM/Infantry/stm32f4xx_hal_uart.crf new file mode 100644 index 0000000..2e4f386 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_uart.crf differ diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_uart.d b/MDK-ARM/Infantry/stm32f4xx_hal_uart.d new file mode 100644 index 0000000..fb7875e --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_hal_uart.d @@ -0,0 +1,36 @@ +infantry/stm32f4xx_hal_uart.o: \ + ..\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/stm32f4xx_hal_uart.o b/MDK-ARM/Infantry/stm32f4xx_hal_uart.o new file mode 100644 index 0000000..03fc4b7 Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_hal_uart.o differ diff --git a/MDK-ARM/Infantry/stm32f4xx_it.d b/MDK-ARM/Infantry/stm32f4xx_it.d new file mode 100644 index 0000000..cf379b3 --- /dev/null +++ b/MDK-ARM/Infantry/stm32f4xx_it.d @@ -0,0 +1,47 @@ +infantry/stm32f4xx_it.o: ..\Core\Src\stm32f4xx_it.c ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\Core\Inc\stm32f4xx_it.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\User\bsp\uart.h ..\Core\Inc\usart.h ..\Core\Inc\main.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h ..\User\bsp\bsp.h diff --git a/MDK-ARM/Infantry/stm32f4xx_it.o b/MDK-ARM/Infantry/stm32f4xx_it.o new file mode 100644 index 0000000..2e4df5c Binary files /dev/null and b/MDK-ARM/Infantry/stm32f4xx_it.o differ diff --git a/MDK-ARM/Infantry/stream_buffer.crf b/MDK-ARM/Infantry/stream_buffer.crf new file mode 100644 index 0000000..2e6add9 Binary files /dev/null and b/MDK-ARM/Infantry/stream_buffer.crf differ diff --git a/MDK-ARM/Infantry/stream_buffer.d b/MDK-ARM/Infantry/stream_buffer.d new file mode 100644 index 0000000..51a3423 --- /dev/null +++ b/MDK-ARM/Infantry/stream_buffer.d @@ -0,0 +1,15 @@ +infantry/stream_buffer.o: \ + ..\Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h diff --git a/MDK-ARM/Infantry/stream_buffer.o b/MDK-ARM/Infantry/stream_buffer.o new file mode 100644 index 0000000..7c09c15 Binary files /dev/null and b/MDK-ARM/Infantry/stream_buffer.o differ diff --git a/MDK-ARM/Infantry/system_stm32f4xx.crf b/MDK-ARM/Infantry/system_stm32f4xx.crf new file mode 100644 index 0000000..2ea2c63 Binary files /dev/null and b/MDK-ARM/Infantry/system_stm32f4xx.crf differ diff --git a/MDK-ARM/Infantry/system_stm32f4xx.d b/MDK-ARM/Infantry/system_stm32f4xx.d new file mode 100644 index 0000000..1bb7a90 --- /dev/null +++ b/MDK-ARM/Infantry/system_stm32f4xx.d @@ -0,0 +1,35 @@ +infantry/system_stm32f4xx.o: ..\Core\Src\system_stm32f4xx.c \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/system_stm32f4xx.o b/MDK-ARM/Infantry/system_stm32f4xx.o new file mode 100644 index 0000000..991d56a Binary files /dev/null and b/MDK-ARM/Infantry/system_stm32f4xx.o differ diff --git a/MDK-ARM/Infantry/tasks.crf b/MDK-ARM/Infantry/tasks.crf new file mode 100644 index 0000000..82027a4 Binary files /dev/null and b/MDK-ARM/Infantry/tasks.crf differ diff --git a/MDK-ARM/Infantry/tasks.d b/MDK-ARM/Infantry/tasks.d new file mode 100644 index 0000000..3051531 --- /dev/null +++ b/MDK-ARM/Infantry/tasks.d @@ -0,0 +1,17 @@ +infantry/tasks.o: ..\Middlewares\Third_Party\FreeRTOS\Source\tasks.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h diff --git a/MDK-ARM/Infantry/tasks.o b/MDK-ARM/Infantry/tasks.o new file mode 100644 index 0000000..536db73 Binary files /dev/null and b/MDK-ARM/Infantry/tasks.o differ diff --git a/MDK-ARM/Infantry/tim.crf b/MDK-ARM/Infantry/tim.crf new file mode 100644 index 0000000..ded4776 Binary files /dev/null and b/MDK-ARM/Infantry/tim.crf differ diff --git a/MDK-ARM/Infantry/tim.d b/MDK-ARM/Infantry/tim.d new file mode 100644 index 0000000..fab734d --- /dev/null +++ b/MDK-ARM/Infantry/tim.d @@ -0,0 +1,35 @@ +infantry/tim.o: ..\Core\Src\tim.c ..\Core\Inc\tim.h ..\Core\Inc\main.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/tim.o b/MDK-ARM/Infantry/tim.o new file mode 100644 index 0000000..e9cf1f6 Binary files /dev/null and b/MDK-ARM/Infantry/tim.o differ diff --git a/MDK-ARM/Infantry/time.d b/MDK-ARM/Infantry/time.d new file mode 100644 index 0000000..d59b2ee --- /dev/null +++ b/MDK-ARM/Infantry/time.d @@ -0,0 +1,46 @@ +infantry/time.o: ..\User\bsp\time.c ..\User\bsp\time.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h ..\User\bsp\bsp.h \ + ..\User\bsp\bsp.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/time.o b/MDK-ARM/Infantry/time.o new file mode 100644 index 0000000..db29791 Binary files /dev/null and b/MDK-ARM/Infantry/time.o differ diff --git a/MDK-ARM/Infantry/timers.crf b/MDK-ARM/Infantry/timers.crf new file mode 100644 index 0000000..c518618 Binary files /dev/null and b/MDK-ARM/Infantry/timers.crf differ diff --git a/MDK-ARM/Infantry/timers.d b/MDK-ARM/Infantry/timers.d new file mode 100644 index 0000000..998f9d5 --- /dev/null +++ b/MDK-ARM/Infantry/timers.d @@ -0,0 +1,16 @@ +infantry/timers.o: ..\Middlewares\Third_Party\FreeRTOS\Source\timers.c \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdlib.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\queue.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\timers.h diff --git a/MDK-ARM/Infantry/timers.o b/MDK-ARM/Infantry/timers.o new file mode 100644 index 0000000..87e0fa4 Binary files /dev/null and b/MDK-ARM/Infantry/timers.o differ diff --git a/MDK-ARM/Infantry/uart.d b/MDK-ARM/Infantry/uart.d new file mode 100644 index 0000000..4d92859 --- /dev/null +++ b/MDK-ARM/Infantry/uart.d @@ -0,0 +1,37 @@ +infantry/uart.o: ..\User\bsp\uart.c ..\Core\Inc\usart.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h \ + ..\User\bsp\uart.h D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + ..\User\bsp\bsp.h diff --git a/MDK-ARM/Infantry/uart.o b/MDK-ARM/Infantry/uart.o new file mode 100644 index 0000000..997d461 Binary files /dev/null and b/MDK-ARM/Infantry/uart.o differ diff --git a/MDK-ARM/Infantry/ui.d b/MDK-ARM/Infantry/ui.d new file mode 100644 index 0000000..2ce8777 --- /dev/null +++ b/MDK-ARM/Infantry/ui.d @@ -0,0 +1,9 @@ +infantry/ui.o: ..\User\component\ui.c ..\User\component\ui.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdio.h diff --git a/MDK-ARM/Infantry/ui.o b/MDK-ARM/Infantry/ui.o new file mode 100644 index 0000000..2ec8bb4 Binary files /dev/null and b/MDK-ARM/Infantry/ui.o differ diff --git a/MDK-ARM/Infantry/usart.crf b/MDK-ARM/Infantry/usart.crf new file mode 100644 index 0000000..82c9c1f Binary files /dev/null and b/MDK-ARM/Infantry/usart.crf differ diff --git a/MDK-ARM/Infantry/usart.d b/MDK-ARM/Infantry/usart.d new file mode 100644 index 0000000..ae21cec --- /dev/null +++ b/MDK-ARM/Infantry/usart.d @@ -0,0 +1,35 @@ +infantry/usart.o: ..\Core\Src\usart.c ..\Core\Inc\usart.h \ + ..\Core\Inc\main.h ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h \ + ..\Core\Inc\stm32f4xx_hal_conf.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h \ + ..\Drivers\CMSIS\Include\core_cm4.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + ..\Drivers\CMSIS\Include\cmsis_version.h \ + ..\Drivers\CMSIS\Include\cmsis_compiler.h \ + ..\Drivers\CMSIS\Include\cmsis_armclang.h \ + ..\Drivers\CMSIS\Include\mpu_armv7.h \ + ..\Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h \ + ..\Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h diff --git a/MDK-ARM/Infantry/usart.o b/MDK-ARM/Infantry/usart.o new file mode 100644 index 0000000..fdf076b Binary files /dev/null and b/MDK-ARM/Infantry/usart.o differ diff --git a/MDK-ARM/Infantry/user_math.d b/MDK-ARM/Infantry/user_math.d new file mode 100644 index 0000000..883f0fa --- /dev/null +++ b/MDK-ARM/Infantry/user_math.d @@ -0,0 +1,8 @@ +infantry/user_math.o: ..\User\component\user_math.c \ + ..\User\component\user_math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\float.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\math.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdbool.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\string.h diff --git a/MDK-ARM/Infantry/user_math.o b/MDK-ARM/Infantry/user_math.o new file mode 100644 index 0000000..60bf995 Binary files /dev/null and b/MDK-ARM/Infantry/user_math.o differ diff --git a/MDK-ARM/Infantry/user_task.d b/MDK-ARM/Infantry/user_task.d new file mode 100644 index 0000000..1906b7a --- /dev/null +++ b/MDK-ARM/Infantry/user_task.d @@ -0,0 +1,13 @@ +infantry/user_task.o: ..\User\task\user_task.c ..\User\task\user_task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stdint.h \ + D:\Keil_v5\ARM\ARMCLANG\Bin\..\include\stddef.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h \ + ..\Core\Inc\FreeRTOSConfig.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\portable.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\portable\RVDS\ARM_CM4F\portmacro.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\task.h \ + ..\Middlewares\Third_Party\FreeRTOS\Source\include\list.h diff --git a/MDK-ARM/Infantry/user_task.o b/MDK-ARM/Infantry/user_task.o new file mode 100644 index 0000000..a86e816 Binary files /dev/null and b/MDK-ARM/Infantry/user_task.o differ diff --git a/MDK-ARM/RTE/_Infantry/RTE_Components.h b/MDK-ARM/RTE/_Infantry/RTE_Components.h new file mode 100644 index 0000000..1bdec3b --- /dev/null +++ b/MDK-ARM/RTE/_Infantry/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'Infantry' + * Target: 'Infantry' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f4xx.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK-ARM/startup_stm32f407xx.lst b/MDK-ARM/startup_stm32f407xx.lst new file mode 100644 index 0000000..f013092 --- /dev/null +++ b/MDK-ARM/startup_stm32f407xx.lst @@ -0,0 +1,1960 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************************************************* + ************************ + 2 00000000 ;* File Name : startup_stm32f407xx.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Description : STM32F407xx devices vector table + for MDK-ARM toolchain. + 5 00000000 ;* This module performs: + 6 00000000 ;* - Set the initial SP + 7 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 8 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 9 00000000 ;* - Branches to __main in the C li + brary (which eventually + 10 00000000 ;* calls main()). + 11 00000000 ;* After Reset the CortexM4 process + or is in Thread mode, + 12 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 13 00000000 ;******************************************************* + ************************ + 14 00000000 ;* @attention + 15 00000000 ;* + 16 00000000 ;* Copyright (c) 2017 STMicroelectronics. + 17 00000000 ;* All rights reserved. + 18 00000000 ;* + 19 00000000 ;* This software is licensed under terms that can be fou + nd in the LICENSE file + 20 00000000 ;* in the root directory of this software component. + 21 00000000 ;* If no LICENSE file comes with this software, it is pr + ovided AS-IS. + 22 00000000 ;* + 23 00000000 ;******************************************************* + ************************ + 24 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 25 00000000 ; + 26 00000000 ; Amount of memory (in bytes) allocated for Stack + 27 00000000 ; Tailor this value to your application needs + 28 00000000 ; Stack Configuration + 29 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 30 00000000 ; + 31 00000000 + 32 00000000 00002000 + Stack_Size + EQU 0x2000 + 33 00000000 + 34 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 35 00000000 Stack_Mem + SPACE Stack_Size + 36 00002000 __initial_sp + 37 00002000 + 38 00002000 + 39 00002000 ; Heap Configuration + 40 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00002000 ; + 42 00002000 + 43 00002000 00001000 + Heap_Size + + + +ARM Macro Assembler Page 2 + + + EQU 0x1000 + 44 00002000 + 45 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 46 00000000 __heap_base + 47 00000000 Heap_Mem + SPACE Heap_Size + 48 00001000 __heap_limit + 49 00001000 + 50 00001000 PRESERVE8 + 51 00001000 THUMB + 52 00001000 + 53 00001000 + 54 00001000 ; Vector Table Mapped to Address 0 at Reset + 55 00001000 AREA RESET, DATA, READONLY + 56 00000000 EXPORT __Vectors + 57 00000000 EXPORT __Vectors_End + 58 00000000 EXPORT __Vectors_Size + 59 00000000 + 60 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 61 00000004 00000000 DCD Reset_Handler ; Reset Handler + 62 00000008 00000000 DCD NMI_Handler ; NMI Handler + 63 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 64 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 65 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 66 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 67 0000001C 00000000 DCD 0 ; Reserved + 68 00000020 00000000 DCD 0 ; Reserved + 69 00000024 00000000 DCD 0 ; Reserved + 70 00000028 00000000 DCD 0 ; Reserved + 71 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 72 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 73 00000034 00000000 DCD 0 ; Reserved + 74 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 75 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 76 00000040 + 77 00000040 ; External Interrupts + 78 00000040 00000000 DCD WWDG_IRQHandler ; Window WatchD + og + + + 79 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detection + + + 80 00000048 00000000 DCD TAMP_STAMP_IRQHandler ; Tamper + and TimeStamps thro + ugh the EXTI line + + + +ARM Macro Assembler Page 3 + + + + 81 0000004C 00000000 DCD RTC_WKUP_IRQHandler ; RTC Wakeu + p through the EXTI + line + + 82 00000050 00000000 DCD FLASH_IRQHandler ; FLASH + + + 83 00000054 00000000 DCD RCC_IRQHandler ; RCC + + + 84 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line0 + + + + 85 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line1 + + + + 86 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line2 + + + + 87 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line3 + + + + 88 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line4 + + + + 89 0000006C 00000000 DCD DMA1_Stream0_IRQHandler ; DMA1 + Stream 0 + + + 90 00000070 00000000 DCD DMA1_Stream1_IRQHandler ; DMA1 + Stream 1 + + + 91 00000074 00000000 DCD DMA1_Stream2_IRQHandler ; DMA1 + Stream 2 + + + 92 00000078 00000000 DCD DMA1_Stream3_IRQHandler ; DMA1 + Stream 3 + + + 93 0000007C 00000000 DCD DMA1_Stream4_IRQHandler ; DMA1 + Stream 4 + + + 94 00000080 00000000 DCD DMA1_Stream5_IRQHandler ; DMA1 + Stream 5 + + + 95 00000084 00000000 DCD DMA1_Stream6_IRQHandler ; DMA1 + Stream 6 + + + + + +ARM Macro Assembler Page 4 + + + 96 00000088 00000000 DCD ADC_IRQHandler ; ADC1, ADC2 and + ADC3s + + 97 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX + + + + 98 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + + + + 99 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + + + + 100 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + + + + 101 0000009C 00000000 DCD EXTI9_5_IRQHandler ; External L + ine[9:5]s + + + 102 000000A0 00000000 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 + Break and TIM9 + + 103 000000A4 00000000 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 + Update and TIM10 + + 104 000000A8 00000000 DCD TIM1_TRG_COM_TIM11_IRQHandler ; + TIM1 Trigger and C + ommutation and TIM1 + 1 + 105 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + + + 106 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + + + 107 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + + + 108 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + + + 109 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + + + 110 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + + + 111 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + + + 112 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + + +ARM Macro Assembler Page 5 + + + + + + 113 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + + + 114 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + + + 115 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + + + 116 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + + + 117 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + + + 118 000000E0 00000000 DCD EXTI15_10_IRQHandler ; External + Line[15:10]s + + + 119 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar + m (A and B) through + EXTI Line + + 120 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT + G FS Wakeup through + EXTI line + + 121 000000EC 00000000 DCD TIM8_BRK_TIM12_IRQHandler ; TIM + 8 Break and TIM12 + + 122 000000F0 00000000 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 + Update and TIM13 + + 123 000000F4 00000000 DCD TIM8_TRG_COM_TIM14_IRQHandler ; + TIM8 Trigger and C + ommutation and TIM1 + 4 + 124 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare + + + 125 000000FC 00000000 DCD DMA1_Stream7_IRQHandler ; DMA1 + Stream7 + + + 126 00000100 00000000 DCD FMC_IRQHandler ; FMC + + + 127 00000104 00000000 DCD SDIO_IRQHandler ; SDIO + + + 128 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + + + 129 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + + + + +ARM Macro Assembler Page 6 + + + + 130 00000110 00000000 DCD UART4_IRQHandler ; UART4 + + + 131 00000114 00000000 DCD UART5_IRQHandler ; UART5 + + + 132 00000118 00000000 DCD TIM6_DAC_IRQHandler ; TIM6 and + DAC1&2 underrun err + ors + + 133 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + + 134 00000120 00000000 DCD DMA2_Stream0_IRQHandler ; DMA2 + Stream 0 + + + 135 00000124 00000000 DCD DMA2_Stream1_IRQHandler ; DMA2 + Stream 1 + + + 136 00000128 00000000 DCD DMA2_Stream2_IRQHandler ; DMA2 + Stream 2 + + + 137 0000012C 00000000 DCD DMA2_Stream3_IRQHandler ; DMA2 + Stream 3 + + + 138 00000130 00000000 DCD DMA2_Stream4_IRQHandler ; DMA2 + Stream 4 + + + 139 00000134 00000000 DCD ETH_IRQHandler ; Ethernet + + + 140 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet + Wakeup through EXTI + line + + 141 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX + + + + 142 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + + + + 143 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + + + + 144 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE + + + + 145 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS + + + + + +ARM Macro Assembler Page 7 + + + 146 00000150 00000000 DCD DMA2_Stream5_IRQHandler ; DMA2 + Stream 5 + + + 147 00000154 00000000 DCD DMA2_Stream6_IRQHandler ; DMA2 + Stream 6 + + + 148 00000158 00000000 DCD DMA2_Stream7_IRQHandler ; DMA2 + Stream 7 + + + 149 0000015C 00000000 DCD USART6_IRQHandler ; USART6 + + + + 150 00000160 00000000 DCD I2C3_EV_IRQHandler ; I2C3 event + + + + 151 00000164 00000000 DCD I2C3_ER_IRQHandler ; I2C3 error + + + + 152 00000168 00000000 DCD OTG_HS_EP1_OUT_IRQHandler ; USB + OTG HS End Point 1 + Out + + 153 0000016C 00000000 DCD OTG_HS_EP1_IN_IRQHandler ; USB + OTG HS End Point 1 + In + + 154 00000170 00000000 DCD OTG_HS_WKUP_IRQHandler ; USB OT + G HS Wakeup through + EXTI + + 155 00000174 00000000 DCD OTG_HS_IRQHandler ; USB OTG HS + + + 156 00000178 00000000 DCD DCMI_IRQHandler ; DCMI + 157 0000017C 00000000 DCD 0 ; Reserved + + + 158 00000180 00000000 DCD HASH_RNG_IRQHandler + ; Hash and Rng + 159 00000184 00000000 DCD FPU_IRQHandler ; FPU + 160 00000188 + 161 00000188 + 162 00000188 __Vectors_End + 163 00000188 + 164 00000188 00000188 + __Vectors_Size + EQU __Vectors_End - __Vectors + 165 00000188 + 166 00000188 AREA |.text|, CODE, READONLY + 167 00000000 + 168 00000000 ; Reset handler + 169 00000000 Reset_Handler + PROC + + + +ARM Macro Assembler Page 8 + + + 170 00000000 EXPORT Reset_Handler [WEAK +] + 171 00000000 IMPORT SystemInit + 172 00000000 IMPORT __main + 173 00000000 + 174 00000000 4809 LDR R0, =SystemInit + 175 00000002 4780 BLX R0 + 176 00000004 4809 LDR R0, =__main + 177 00000006 4700 BX R0 + 178 00000008 ENDP + 179 00000008 + 180 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 181 00000008 + 182 00000008 NMI_Handler + PROC + 183 00000008 EXPORT NMI_Handler [WEA +K] + 184 00000008 E7FE B . + 185 0000000A ENDP + 187 0000000A HardFault_Handler + PROC + 188 0000000A EXPORT HardFault_Handler [WEA +K] + 189 0000000A E7FE B . + 190 0000000C ENDP + 192 0000000C MemManage_Handler + PROC + 193 0000000C EXPORT MemManage_Handler [WEA +K] + 194 0000000C E7FE B . + 195 0000000E ENDP + 197 0000000E BusFault_Handler + PROC + 198 0000000E EXPORT BusFault_Handler [WEA +K] + 199 0000000E E7FE B . + 200 00000010 ENDP + 202 00000010 UsageFault_Handler + PROC + 203 00000010 EXPORT UsageFault_Handler [WEA +K] + 204 00000010 E7FE B . + 205 00000012 ENDP + 206 00000012 SVC_Handler + PROC + 207 00000012 EXPORT SVC_Handler [WEA +K] + 208 00000012 E7FE B . + 209 00000014 ENDP + 211 00000014 DebugMon_Handler + PROC + 212 00000014 EXPORT DebugMon_Handler [WEA +K] + 213 00000014 E7FE B . + 214 00000016 ENDP + 215 00000016 PendSV_Handler + PROC + 216 00000016 EXPORT PendSV_Handler [WEA + + + +ARM Macro Assembler Page 9 + + +K] + 217 00000016 E7FE B . + 218 00000018 ENDP + 219 00000018 SysTick_Handler + PROC + 220 00000018 EXPORT SysTick_Handler [WEA +K] + 221 00000018 E7FE B . + 222 0000001A ENDP + 223 0000001A + 224 0000001A Default_Handler + PROC + 225 0000001A + 226 0000001A EXPORT WWDG_IRQHandler + [WEAK] + 227 0000001A EXPORT PVD_IRQHandler + [WEAK] + 228 0000001A EXPORT TAMP_STAMP_IRQHandler + [WEAK] + 229 0000001A EXPORT RTC_WKUP_IRQHandler + [WEAK] + 230 0000001A EXPORT FLASH_IRQHandler + [WEAK] + 231 0000001A EXPORT RCC_IRQHandler + [WEAK] + 232 0000001A EXPORT EXTI0_IRQHandler + [WEAK] + 233 0000001A EXPORT EXTI1_IRQHandler + [WEAK] + 234 0000001A EXPORT EXTI2_IRQHandler + [WEAK] + 235 0000001A EXPORT EXTI3_IRQHandler + [WEAK] + 236 0000001A EXPORT EXTI4_IRQHandler + [WEAK] + 237 0000001A EXPORT DMA1_Stream0_IRQHandler + [WEAK] + 238 0000001A EXPORT DMA1_Stream1_IRQHandler + [WEAK] + 239 0000001A EXPORT DMA1_Stream2_IRQHandler + [WEAK] + 240 0000001A EXPORT DMA1_Stream3_IRQHandler + [WEAK] + 241 0000001A EXPORT DMA1_Stream4_IRQHandler + [WEAK] + 242 0000001A EXPORT DMA1_Stream5_IRQHandler + [WEAK] + 243 0000001A EXPORT DMA1_Stream6_IRQHandler + [WEAK] + 244 0000001A EXPORT ADC_IRQHandler + [WEAK] + 245 0000001A EXPORT CAN1_TX_IRQHandler + [WEAK] + 246 0000001A EXPORT CAN1_RX0_IRQHandler + [WEAK] + 247 0000001A EXPORT CAN1_RX1_IRQHandler + [WEAK] + 248 0000001A EXPORT CAN1_SCE_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 10 + + + 249 0000001A EXPORT EXTI9_5_IRQHandler + [WEAK] + 250 0000001A EXPORT TIM1_BRK_TIM9_IRQHandler + [WEAK] + 251 0000001A EXPORT TIM1_UP_TIM10_IRQHandler + [WEAK] + 252 0000001A EXPORT TIM1_TRG_COM_TIM11_IRQHandler + [WEAK] + 253 0000001A EXPORT TIM1_CC_IRQHandler + [WEAK] + 254 0000001A EXPORT TIM2_IRQHandler + [WEAK] + 255 0000001A EXPORT TIM3_IRQHandler + [WEAK] + 256 0000001A EXPORT TIM4_IRQHandler + [WEAK] + 257 0000001A EXPORT I2C1_EV_IRQHandler + [WEAK] + 258 0000001A EXPORT I2C1_ER_IRQHandler + [WEAK] + 259 0000001A EXPORT I2C2_EV_IRQHandler + [WEAK] + 260 0000001A EXPORT I2C2_ER_IRQHandler + [WEAK] + 261 0000001A EXPORT SPI1_IRQHandler + [WEAK] + 262 0000001A EXPORT SPI2_IRQHandler + [WEAK] + 263 0000001A EXPORT USART1_IRQHandler + [WEAK] + 264 0000001A EXPORT USART2_IRQHandler + [WEAK] + 265 0000001A EXPORT USART3_IRQHandler + [WEAK] + 266 0000001A EXPORT EXTI15_10_IRQHandler + [WEAK] + 267 0000001A EXPORT RTC_Alarm_IRQHandler + [WEAK] + 268 0000001A EXPORT OTG_FS_WKUP_IRQHandler + [WEAK] + 269 0000001A EXPORT TIM8_BRK_TIM12_IRQHandler + [WEAK] + 270 0000001A EXPORT TIM8_UP_TIM13_IRQHandler + [WEAK] + 271 0000001A EXPORT TIM8_TRG_COM_TIM14_IRQHandler + [WEAK] + 272 0000001A EXPORT TIM8_CC_IRQHandler + [WEAK] + 273 0000001A EXPORT DMA1_Stream7_IRQHandler + [WEAK] + 274 0000001A EXPORT FMC_IRQHandler + [WEAK] + 275 0000001A EXPORT SDIO_IRQHandler + [WEAK] + 276 0000001A EXPORT TIM5_IRQHandler + [WEAK] + 277 0000001A EXPORT SPI3_IRQHandler + [WEAK] + 278 0000001A EXPORT UART4_IRQHandler + + + +ARM Macro Assembler Page 11 + + + [WEAK] + 279 0000001A EXPORT UART5_IRQHandler + [WEAK] + 280 0000001A EXPORT TIM6_DAC_IRQHandler + [WEAK] + 281 0000001A EXPORT TIM7_IRQHandler + [WEAK] + 282 0000001A EXPORT DMA2_Stream0_IRQHandler + [WEAK] + 283 0000001A EXPORT DMA2_Stream1_IRQHandler + [WEAK] + 284 0000001A EXPORT DMA2_Stream2_IRQHandler + [WEAK] + 285 0000001A EXPORT DMA2_Stream3_IRQHandler + [WEAK] + 286 0000001A EXPORT DMA2_Stream4_IRQHandler + [WEAK] + 287 0000001A EXPORT ETH_IRQHandler + [WEAK] + 288 0000001A EXPORT ETH_WKUP_IRQHandler + [WEAK] + 289 0000001A EXPORT CAN2_TX_IRQHandler + [WEAK] + 290 0000001A EXPORT CAN2_RX0_IRQHandler + [WEAK] + 291 0000001A EXPORT CAN2_RX1_IRQHandler + [WEAK] + 292 0000001A EXPORT CAN2_SCE_IRQHandler + [WEAK] + 293 0000001A EXPORT OTG_FS_IRQHandler + [WEAK] + 294 0000001A EXPORT DMA2_Stream5_IRQHandler + [WEAK] + 295 0000001A EXPORT DMA2_Stream6_IRQHandler + [WEAK] + 296 0000001A EXPORT DMA2_Stream7_IRQHandler + [WEAK] + 297 0000001A EXPORT USART6_IRQHandler + [WEAK] + 298 0000001A EXPORT I2C3_EV_IRQHandler + [WEAK] + 299 0000001A EXPORT I2C3_ER_IRQHandler + [WEAK] + 300 0000001A EXPORT OTG_HS_EP1_OUT_IRQHandler + [WEAK] + 301 0000001A EXPORT OTG_HS_EP1_IN_IRQHandler + [WEAK] + 302 0000001A EXPORT OTG_HS_WKUP_IRQHandler + [WEAK] + 303 0000001A EXPORT OTG_HS_IRQHandler + [WEAK] + 304 0000001A EXPORT DCMI_IRQHandler + [WEAK] + 305 0000001A EXPORT HASH_RNG_IRQHandler + [WEAK] + 306 0000001A EXPORT FPU_IRQHandler + [WEAK] + 307 0000001A + 308 0000001A WWDG_IRQHandler + + + +ARM Macro Assembler Page 12 + + + 309 0000001A PVD_IRQHandler + 310 0000001A TAMP_STAMP_IRQHandler + 311 0000001A RTC_WKUP_IRQHandler + 312 0000001A FLASH_IRQHandler + 313 0000001A RCC_IRQHandler + 314 0000001A EXTI0_IRQHandler + 315 0000001A EXTI1_IRQHandler + 316 0000001A EXTI2_IRQHandler + 317 0000001A EXTI3_IRQHandler + 318 0000001A EXTI4_IRQHandler + 319 0000001A DMA1_Stream0_IRQHandler + 320 0000001A DMA1_Stream1_IRQHandler + 321 0000001A DMA1_Stream2_IRQHandler + 322 0000001A DMA1_Stream3_IRQHandler + 323 0000001A DMA1_Stream4_IRQHandler + 324 0000001A DMA1_Stream5_IRQHandler + 325 0000001A DMA1_Stream6_IRQHandler + 326 0000001A ADC_IRQHandler + 327 0000001A CAN1_TX_IRQHandler + 328 0000001A CAN1_RX0_IRQHandler + 329 0000001A CAN1_RX1_IRQHandler + 330 0000001A CAN1_SCE_IRQHandler + 331 0000001A EXTI9_5_IRQHandler + 332 0000001A TIM1_BRK_TIM9_IRQHandler + 333 0000001A TIM1_UP_TIM10_IRQHandler + 334 0000001A TIM1_TRG_COM_TIM11_IRQHandler + 335 0000001A TIM1_CC_IRQHandler + 336 0000001A TIM2_IRQHandler + 337 0000001A TIM3_IRQHandler + 338 0000001A TIM4_IRQHandler + 339 0000001A I2C1_EV_IRQHandler + 340 0000001A I2C1_ER_IRQHandler + 341 0000001A I2C2_EV_IRQHandler + 342 0000001A I2C2_ER_IRQHandler + 343 0000001A SPI1_IRQHandler + 344 0000001A SPI2_IRQHandler + 345 0000001A USART1_IRQHandler + 346 0000001A USART2_IRQHandler + 347 0000001A USART3_IRQHandler + 348 0000001A EXTI15_10_IRQHandler + 349 0000001A RTC_Alarm_IRQHandler + 350 0000001A OTG_FS_WKUP_IRQHandler + 351 0000001A TIM8_BRK_TIM12_IRQHandler + 352 0000001A TIM8_UP_TIM13_IRQHandler + 353 0000001A TIM8_TRG_COM_TIM14_IRQHandler + 354 0000001A TIM8_CC_IRQHandler + 355 0000001A DMA1_Stream7_IRQHandler + 356 0000001A FMC_IRQHandler + 357 0000001A SDIO_IRQHandler + 358 0000001A TIM5_IRQHandler + 359 0000001A SPI3_IRQHandler + 360 0000001A UART4_IRQHandler + 361 0000001A UART5_IRQHandler + 362 0000001A TIM6_DAC_IRQHandler + 363 0000001A TIM7_IRQHandler + 364 0000001A DMA2_Stream0_IRQHandler + 365 0000001A DMA2_Stream1_IRQHandler + 366 0000001A DMA2_Stream2_IRQHandler + 367 0000001A DMA2_Stream3_IRQHandler + + + +ARM Macro Assembler Page 13 + + + 368 0000001A DMA2_Stream4_IRQHandler + 369 0000001A ETH_IRQHandler + 370 0000001A ETH_WKUP_IRQHandler + 371 0000001A CAN2_TX_IRQHandler + 372 0000001A CAN2_RX0_IRQHandler + 373 0000001A CAN2_RX1_IRQHandler + 374 0000001A CAN2_SCE_IRQHandler + 375 0000001A OTG_FS_IRQHandler + 376 0000001A DMA2_Stream5_IRQHandler + 377 0000001A DMA2_Stream6_IRQHandler + 378 0000001A DMA2_Stream7_IRQHandler + 379 0000001A USART6_IRQHandler + 380 0000001A I2C3_EV_IRQHandler + 381 0000001A I2C3_ER_IRQHandler + 382 0000001A OTG_HS_EP1_OUT_IRQHandler + 383 0000001A OTG_HS_EP1_IN_IRQHandler + 384 0000001A OTG_HS_WKUP_IRQHandler + 385 0000001A OTG_HS_IRQHandler + 386 0000001A DCMI_IRQHandler + 387 0000001A HASH_RNG_IRQHandler + 388 0000001A FPU_IRQHandler + 389 0000001A + 390 0000001A E7FE B . + 391 0000001C + 392 0000001C ENDP + 393 0000001C + 394 0000001C ALIGN + 395 0000001C + 396 0000001C ;******************************************************* + ************************ + 397 0000001C ; User Stack and Heap initialization + 398 0000001C ;******************************************************* + ************************ + 399 0000001C IF :DEF:__MICROLIB + 406 0000001C + 407 0000001C IMPORT __use_two_region_memory + 408 0000001C EXPORT __user_initial_stackheap + 409 0000001C + 410 0000001C __user_initial_stackheap + 411 0000001C + 412 0000001C 4804 LDR R0, = Heap_Mem + 413 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + 414 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 415 00000022 4B06 LDR R3, = Stack_Mem + 416 00000024 4770 BX LR + 417 00000026 + 418 00000026 00 00 ALIGN + 419 00000028 + 420 00000028 ENDIF + 421 00000028 + 422 00000028 END + 00000000 + 00000000 + 00000000 + 00002000 + 00001000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --apcs= +interwork --depend=infantry\startup_stm32f407xx.d -oinfantry\startup_stm32f407x + + + +ARM Macro Assembler Page 14 + + +x.o -I../Drivers/CMSIS/Include -I.\RTE\_Infantry -ID:\Keil_v5\Arm\Packs\ARM\CMS +IS\5.7.0\CMSIS\Core\Include -ID:\Keil_v5\Arm\Packs\Keil\STM32F4xx_DFP\2.17.1\Dr +ivers\CMSIS\Device\ST\STM32F4xx\Include --predefine="__UVISION_VERSION SETA 534 +" --predefine="_RTE_ SETA 1" --predefine="STM32F407xx SETA 1" --predefine="_RTE +_ SETA 1" --list=startup_stm32f407xx.lst startup_stm32f407xx.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 34 in file startup_stm32f407xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 35 in file startup_stm32f407xx.s + Uses + At line 413 in file startup_stm32f407xx.s + At line 415 in file startup_stm32f407xx.s + +__initial_sp 00002000 + +Symbol: __initial_sp + Definitions + At line 36 in file startup_stm32f407xx.s + Uses + At line 60 in file startup_stm32f407xx.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 45 in file startup_stm32f407xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 47 in file startup_stm32f407xx.s + Uses + At line 412 in file startup_stm32f407xx.s + At line 414 in file startup_stm32f407xx.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 46 in file startup_stm32f407xx.s + Uses + None +Comment: __heap_base unused +__heap_limit 00001000 + +Symbol: __heap_limit + Definitions + At line 48 in file startup_stm32f407xx.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 55 in file startup_stm32f407xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 60 in file startup_stm32f407xx.s + Uses + At line 56 in file startup_stm32f407xx.s + At line 164 in file startup_stm32f407xx.s + +__Vectors_End 00000188 + +Symbol: __Vectors_End + Definitions + At line 162 in file startup_stm32f407xx.s + Uses + At line 57 in file startup_stm32f407xx.s + At line 164 in file startup_stm32f407xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 166 in file startup_stm32f407xx.s + Uses + None +Comment: .text unused +ADC_IRQHandler 0000001A + +Symbol: ADC_IRQHandler + Definitions + At line 326 in file startup_stm32f407xx.s + Uses + At line 96 in file startup_stm32f407xx.s + At line 244 in file startup_stm32f407xx.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 197 in file startup_stm32f407xx.s + Uses + At line 65 in file startup_stm32f407xx.s + At line 198 in file startup_stm32f407xx.s + +CAN1_RX0_IRQHandler 0000001A + +Symbol: CAN1_RX0_IRQHandler + Definitions + At line 328 in file startup_stm32f407xx.s + Uses + At line 98 in file startup_stm32f407xx.s + At line 246 in file startup_stm32f407xx.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 329 in file startup_stm32f407xx.s + Uses + At line 99 in file startup_stm32f407xx.s + At line 247 in file startup_stm32f407xx.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 330 in file startup_stm32f407xx.s + Uses + At line 100 in file startup_stm32f407xx.s + At line 248 in file startup_stm32f407xx.s + +CAN1_TX_IRQHandler 0000001A + +Symbol: CAN1_TX_IRQHandler + Definitions + At line 327 in file startup_stm32f407xx.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 97 in file startup_stm32f407xx.s + At line 245 in file startup_stm32f407xx.s + +CAN2_RX0_IRQHandler 0000001A + +Symbol: CAN2_RX0_IRQHandler + Definitions + At line 372 in file startup_stm32f407xx.s + Uses + At line 142 in file startup_stm32f407xx.s + At line 290 in file startup_stm32f407xx.s + +CAN2_RX1_IRQHandler 0000001A + +Symbol: CAN2_RX1_IRQHandler + Definitions + At line 373 in file startup_stm32f407xx.s + Uses + At line 143 in file startup_stm32f407xx.s + At line 291 in file startup_stm32f407xx.s + +CAN2_SCE_IRQHandler 0000001A + +Symbol: CAN2_SCE_IRQHandler + Definitions + At line 374 in file startup_stm32f407xx.s + Uses + At line 144 in file startup_stm32f407xx.s + At line 292 in file startup_stm32f407xx.s + +CAN2_TX_IRQHandler 0000001A + +Symbol: CAN2_TX_IRQHandler + Definitions + At line 371 in file startup_stm32f407xx.s + Uses + At line 141 in file startup_stm32f407xx.s + At line 289 in file startup_stm32f407xx.s + +DCMI_IRQHandler 0000001A + +Symbol: DCMI_IRQHandler + Definitions + At line 386 in file startup_stm32f407xx.s + Uses + At line 156 in file startup_stm32f407xx.s + At line 304 in file startup_stm32f407xx.s + +DMA1_Stream0_IRQHandler 0000001A + +Symbol: DMA1_Stream0_IRQHandler + Definitions + At line 319 in file startup_stm32f407xx.s + Uses + At line 89 in file startup_stm32f407xx.s + At line 237 in file startup_stm32f407xx.s + +DMA1_Stream1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA1_Stream1_IRQHandler + Definitions + At line 320 in file startup_stm32f407xx.s + Uses + At line 90 in file startup_stm32f407xx.s + At line 238 in file startup_stm32f407xx.s + +DMA1_Stream2_IRQHandler 0000001A + +Symbol: DMA1_Stream2_IRQHandler + Definitions + At line 321 in file startup_stm32f407xx.s + Uses + At line 91 in file startup_stm32f407xx.s + At line 239 in file startup_stm32f407xx.s + +DMA1_Stream3_IRQHandler 0000001A + +Symbol: DMA1_Stream3_IRQHandler + Definitions + At line 322 in file startup_stm32f407xx.s + Uses + At line 92 in file startup_stm32f407xx.s + At line 240 in file startup_stm32f407xx.s + +DMA1_Stream4_IRQHandler 0000001A + +Symbol: DMA1_Stream4_IRQHandler + Definitions + At line 323 in file startup_stm32f407xx.s + Uses + At line 93 in file startup_stm32f407xx.s + At line 241 in file startup_stm32f407xx.s + +DMA1_Stream5_IRQHandler 0000001A + +Symbol: DMA1_Stream5_IRQHandler + Definitions + At line 324 in file startup_stm32f407xx.s + Uses + At line 94 in file startup_stm32f407xx.s + At line 242 in file startup_stm32f407xx.s + +DMA1_Stream6_IRQHandler 0000001A + +Symbol: DMA1_Stream6_IRQHandler + Definitions + At line 325 in file startup_stm32f407xx.s + Uses + At line 95 in file startup_stm32f407xx.s + At line 243 in file startup_stm32f407xx.s + +DMA1_Stream7_IRQHandler 0000001A + +Symbol: DMA1_Stream7_IRQHandler + Definitions + At line 355 in file startup_stm32f407xx.s + Uses + At line 125 in file startup_stm32f407xx.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + At line 273 in file startup_stm32f407xx.s + +DMA2_Stream0_IRQHandler 0000001A + +Symbol: DMA2_Stream0_IRQHandler + Definitions + At line 364 in file startup_stm32f407xx.s + Uses + At line 134 in file startup_stm32f407xx.s + At line 282 in file startup_stm32f407xx.s + +DMA2_Stream1_IRQHandler 0000001A + +Symbol: DMA2_Stream1_IRQHandler + Definitions + At line 365 in file startup_stm32f407xx.s + Uses + At line 135 in file startup_stm32f407xx.s + At line 283 in file startup_stm32f407xx.s + +DMA2_Stream2_IRQHandler 0000001A + +Symbol: DMA2_Stream2_IRQHandler + Definitions + At line 366 in file startup_stm32f407xx.s + Uses + At line 136 in file startup_stm32f407xx.s + At line 284 in file startup_stm32f407xx.s + +DMA2_Stream3_IRQHandler 0000001A + +Symbol: DMA2_Stream3_IRQHandler + Definitions + At line 367 in file startup_stm32f407xx.s + Uses + At line 137 in file startup_stm32f407xx.s + At line 285 in file startup_stm32f407xx.s + +DMA2_Stream4_IRQHandler 0000001A + +Symbol: DMA2_Stream4_IRQHandler + Definitions + At line 368 in file startup_stm32f407xx.s + Uses + At line 138 in file startup_stm32f407xx.s + At line 286 in file startup_stm32f407xx.s + +DMA2_Stream5_IRQHandler 0000001A + +Symbol: DMA2_Stream5_IRQHandler + Definitions + At line 376 in file startup_stm32f407xx.s + Uses + At line 146 in file startup_stm32f407xx.s + At line 294 in file startup_stm32f407xx.s + +DMA2_Stream6_IRQHandler 0000001A + +Symbol: DMA2_Stream6_IRQHandler + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 377 in file startup_stm32f407xx.s + Uses + At line 147 in file startup_stm32f407xx.s + At line 295 in file startup_stm32f407xx.s + +DMA2_Stream7_IRQHandler 0000001A + +Symbol: DMA2_Stream7_IRQHandler + Definitions + At line 378 in file startup_stm32f407xx.s + Uses + At line 148 in file startup_stm32f407xx.s + At line 296 in file startup_stm32f407xx.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 211 in file startup_stm32f407xx.s + Uses + At line 72 in file startup_stm32f407xx.s + At line 212 in file startup_stm32f407xx.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 224 in file startup_stm32f407xx.s + Uses + None +Comment: Default_Handler unused +ETH_IRQHandler 0000001A + +Symbol: ETH_IRQHandler + Definitions + At line 369 in file startup_stm32f407xx.s + Uses + At line 139 in file startup_stm32f407xx.s + At line 287 in file startup_stm32f407xx.s + +ETH_WKUP_IRQHandler 0000001A + +Symbol: ETH_WKUP_IRQHandler + Definitions + At line 370 in file startup_stm32f407xx.s + Uses + At line 140 in file startup_stm32f407xx.s + At line 288 in file startup_stm32f407xx.s + +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 314 in file startup_stm32f407xx.s + Uses + At line 84 in file startup_stm32f407xx.s + At line 232 in file startup_stm32f407xx.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 348 in file startup_stm32f407xx.s + Uses + At line 118 in file startup_stm32f407xx.s + At line 266 in file startup_stm32f407xx.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 315 in file startup_stm32f407xx.s + Uses + At line 85 in file startup_stm32f407xx.s + At line 233 in file startup_stm32f407xx.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 316 in file startup_stm32f407xx.s + Uses + At line 86 in file startup_stm32f407xx.s + At line 234 in file startup_stm32f407xx.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 317 in file startup_stm32f407xx.s + Uses + At line 87 in file startup_stm32f407xx.s + At line 235 in file startup_stm32f407xx.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 318 in file startup_stm32f407xx.s + Uses + At line 88 in file startup_stm32f407xx.s + At line 236 in file startup_stm32f407xx.s + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 331 in file startup_stm32f407xx.s + Uses + At line 101 in file startup_stm32f407xx.s + At line 249 in file startup_stm32f407xx.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 312 in file startup_stm32f407xx.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 82 in file startup_stm32f407xx.s + At line 230 in file startup_stm32f407xx.s + +FMC_IRQHandler 0000001A + +Symbol: FMC_IRQHandler + Definitions + At line 356 in file startup_stm32f407xx.s + Uses + At line 126 in file startup_stm32f407xx.s + At line 274 in file startup_stm32f407xx.s + +FPU_IRQHandler 0000001A + +Symbol: FPU_IRQHandler + Definitions + At line 388 in file startup_stm32f407xx.s + Uses + At line 159 in file startup_stm32f407xx.s + At line 306 in file startup_stm32f407xx.s + +HASH_RNG_IRQHandler 0000001A + +Symbol: HASH_RNG_IRQHandler + Definitions + At line 387 in file startup_stm32f407xx.s + Uses + At line 158 in file startup_stm32f407xx.s + At line 305 in file startup_stm32f407xx.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 187 in file startup_stm32f407xx.s + Uses + At line 63 in file startup_stm32f407xx.s + At line 188 in file startup_stm32f407xx.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 340 in file startup_stm32f407xx.s + Uses + At line 110 in file startup_stm32f407xx.s + At line 258 in file startup_stm32f407xx.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 339 in file startup_stm32f407xx.s + Uses + At line 109 in file startup_stm32f407xx.s + At line 257 in file startup_stm32f407xx.s + +I2C2_ER_IRQHandler 0000001A + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 342 in file startup_stm32f407xx.s + Uses + At line 112 in file startup_stm32f407xx.s + At line 260 in file startup_stm32f407xx.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 341 in file startup_stm32f407xx.s + Uses + At line 111 in file startup_stm32f407xx.s + At line 259 in file startup_stm32f407xx.s + +I2C3_ER_IRQHandler 0000001A + +Symbol: I2C3_ER_IRQHandler + Definitions + At line 381 in file startup_stm32f407xx.s + Uses + At line 151 in file startup_stm32f407xx.s + At line 299 in file startup_stm32f407xx.s + +I2C3_EV_IRQHandler 0000001A + +Symbol: I2C3_EV_IRQHandler + Definitions + At line 380 in file startup_stm32f407xx.s + Uses + At line 150 in file startup_stm32f407xx.s + At line 298 in file startup_stm32f407xx.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 192 in file startup_stm32f407xx.s + Uses + At line 64 in file startup_stm32f407xx.s + At line 193 in file startup_stm32f407xx.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 182 in file startup_stm32f407xx.s + Uses + At line 62 in file startup_stm32f407xx.s + At line 183 in file startup_stm32f407xx.s + +OTG_FS_IRQHandler 0000001A + +Symbol: OTG_FS_IRQHandler + Definitions + At line 375 in file startup_stm32f407xx.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 145 in file startup_stm32f407xx.s + At line 293 in file startup_stm32f407xx.s + +OTG_FS_WKUP_IRQHandler 0000001A + +Symbol: OTG_FS_WKUP_IRQHandler + Definitions + At line 350 in file startup_stm32f407xx.s + Uses + At line 120 in file startup_stm32f407xx.s + At line 268 in file startup_stm32f407xx.s + +OTG_HS_EP1_IN_IRQHandler 0000001A + +Symbol: OTG_HS_EP1_IN_IRQHandler + Definitions + At line 383 in file startup_stm32f407xx.s + Uses + At line 153 in file startup_stm32f407xx.s + At line 301 in file startup_stm32f407xx.s + +OTG_HS_EP1_OUT_IRQHandler 0000001A + +Symbol: OTG_HS_EP1_OUT_IRQHandler + Definitions + At line 382 in file startup_stm32f407xx.s + Uses + At line 152 in file startup_stm32f407xx.s + At line 300 in file startup_stm32f407xx.s + +OTG_HS_IRQHandler 0000001A + +Symbol: OTG_HS_IRQHandler + Definitions + At line 385 in file startup_stm32f407xx.s + Uses + At line 155 in file startup_stm32f407xx.s + At line 303 in file startup_stm32f407xx.s + +OTG_HS_WKUP_IRQHandler 0000001A + +Symbol: OTG_HS_WKUP_IRQHandler + Definitions + At line 384 in file startup_stm32f407xx.s + Uses + At line 154 in file startup_stm32f407xx.s + At line 302 in file startup_stm32f407xx.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 309 in file startup_stm32f407xx.s + Uses + At line 79 in file startup_stm32f407xx.s + At line 227 in file startup_stm32f407xx.s + +PendSV_Handler 00000016 + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: PendSV_Handler + Definitions + At line 215 in file startup_stm32f407xx.s + Uses + At line 74 in file startup_stm32f407xx.s + At line 216 in file startup_stm32f407xx.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 313 in file startup_stm32f407xx.s + Uses + At line 83 in file startup_stm32f407xx.s + At line 231 in file startup_stm32f407xx.s + +RTC_Alarm_IRQHandler 0000001A + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 349 in file startup_stm32f407xx.s + Uses + At line 119 in file startup_stm32f407xx.s + At line 267 in file startup_stm32f407xx.s + +RTC_WKUP_IRQHandler 0000001A + +Symbol: RTC_WKUP_IRQHandler + Definitions + At line 311 in file startup_stm32f407xx.s + Uses + At line 81 in file startup_stm32f407xx.s + At line 229 in file startup_stm32f407xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 169 in file startup_stm32f407xx.s + Uses + At line 61 in file startup_stm32f407xx.s + At line 170 in file startup_stm32f407xx.s + +SDIO_IRQHandler 0000001A + +Symbol: SDIO_IRQHandler + Definitions + At line 357 in file startup_stm32f407xx.s + Uses + At line 127 in file startup_stm32f407xx.s + At line 275 in file startup_stm32f407xx.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 343 in file startup_stm32f407xx.s + Uses + At line 113 in file startup_stm32f407xx.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 261 in file startup_stm32f407xx.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 344 in file startup_stm32f407xx.s + Uses + At line 114 in file startup_stm32f407xx.s + At line 262 in file startup_stm32f407xx.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 359 in file startup_stm32f407xx.s + Uses + At line 129 in file startup_stm32f407xx.s + At line 277 in file startup_stm32f407xx.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 206 in file startup_stm32f407xx.s + Uses + At line 71 in file startup_stm32f407xx.s + At line 207 in file startup_stm32f407xx.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 219 in file startup_stm32f407xx.s + Uses + At line 75 in file startup_stm32f407xx.s + At line 220 in file startup_stm32f407xx.s + +TAMP_STAMP_IRQHandler 0000001A + +Symbol: TAMP_STAMP_IRQHandler + Definitions + At line 310 in file startup_stm32f407xx.s + Uses + At line 80 in file startup_stm32f407xx.s + At line 228 in file startup_stm32f407xx.s + +TIM1_BRK_TIM9_IRQHandler 0000001A + +Symbol: TIM1_BRK_TIM9_IRQHandler + Definitions + At line 332 in file startup_stm32f407xx.s + Uses + At line 102 in file startup_stm32f407xx.s + At line 250 in file startup_stm32f407xx.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 335 in file startup_stm32f407xx.s + Uses + At line 105 in file startup_stm32f407xx.s + At line 253 in file startup_stm32f407xx.s + +TIM1_TRG_COM_TIM11_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_TIM11_IRQHandler + Definitions + At line 334 in file startup_stm32f407xx.s + Uses + At line 104 in file startup_stm32f407xx.s + At line 252 in file startup_stm32f407xx.s + +TIM1_UP_TIM10_IRQHandler 0000001A + +Symbol: TIM1_UP_TIM10_IRQHandler + Definitions + At line 333 in file startup_stm32f407xx.s + Uses + At line 103 in file startup_stm32f407xx.s + At line 251 in file startup_stm32f407xx.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 336 in file startup_stm32f407xx.s + Uses + At line 106 in file startup_stm32f407xx.s + At line 254 in file startup_stm32f407xx.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 337 in file startup_stm32f407xx.s + Uses + At line 107 in file startup_stm32f407xx.s + At line 255 in file startup_stm32f407xx.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 338 in file startup_stm32f407xx.s + Uses + At line 108 in file startup_stm32f407xx.s + At line 256 in file startup_stm32f407xx.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + At line 358 in file startup_stm32f407xx.s + Uses + At line 128 in file startup_stm32f407xx.s + At line 276 in file startup_stm32f407xx.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + +TIM6_DAC_IRQHandler 0000001A + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 362 in file startup_stm32f407xx.s + Uses + At line 132 in file startup_stm32f407xx.s + At line 280 in file startup_stm32f407xx.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 363 in file startup_stm32f407xx.s + Uses + At line 133 in file startup_stm32f407xx.s + At line 281 in file startup_stm32f407xx.s + +TIM8_BRK_TIM12_IRQHandler 0000001A + +Symbol: TIM8_BRK_TIM12_IRQHandler + Definitions + At line 351 in file startup_stm32f407xx.s + Uses + At line 121 in file startup_stm32f407xx.s + At line 269 in file startup_stm32f407xx.s + +TIM8_CC_IRQHandler 0000001A + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 354 in file startup_stm32f407xx.s + Uses + At line 124 in file startup_stm32f407xx.s + At line 272 in file startup_stm32f407xx.s + +TIM8_TRG_COM_TIM14_IRQHandler 0000001A + +Symbol: TIM8_TRG_COM_TIM14_IRQHandler + Definitions + At line 353 in file startup_stm32f407xx.s + Uses + At line 123 in file startup_stm32f407xx.s + At line 271 in file startup_stm32f407xx.s + +TIM8_UP_TIM13_IRQHandler 0000001A + +Symbol: TIM8_UP_TIM13_IRQHandler + Definitions + At line 352 in file startup_stm32f407xx.s + Uses + At line 122 in file startup_stm32f407xx.s + At line 270 in file startup_stm32f407xx.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + + At line 360 in file startup_stm32f407xx.s + Uses + At line 130 in file startup_stm32f407xx.s + At line 278 in file startup_stm32f407xx.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 361 in file startup_stm32f407xx.s + Uses + At line 131 in file startup_stm32f407xx.s + At line 279 in file startup_stm32f407xx.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 345 in file startup_stm32f407xx.s + Uses + At line 115 in file startup_stm32f407xx.s + At line 263 in file startup_stm32f407xx.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 346 in file startup_stm32f407xx.s + Uses + At line 116 in file startup_stm32f407xx.s + At line 264 in file startup_stm32f407xx.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 347 in file startup_stm32f407xx.s + Uses + At line 117 in file startup_stm32f407xx.s + At line 265 in file startup_stm32f407xx.s + +USART6_IRQHandler 0000001A + +Symbol: USART6_IRQHandler + Definitions + At line 379 in file startup_stm32f407xx.s + Uses + At line 149 in file startup_stm32f407xx.s + At line 297 in file startup_stm32f407xx.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 202 in file startup_stm32f407xx.s + Uses + At line 66 in file startup_stm32f407xx.s + At line 203 in file startup_stm32f407xx.s + + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 308 in file startup_stm32f407xx.s + Uses + At line 78 in file startup_stm32f407xx.s + At line 226 in file startup_stm32f407xx.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + Definitions + At line 410 in file startup_stm32f407xx.s + Uses + At line 408 in file startup_stm32f407xx.s +Comment: __user_initial_stackheap used once +94 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00001000 + +Symbol: Heap_Size + Definitions + At line 43 in file startup_stm32f407xx.s + Uses + At line 47 in file startup_stm32f407xx.s + At line 414 in file startup_stm32f407xx.s + +Stack_Size 00002000 + +Symbol: Stack_Size + Definitions + At line 32 in file startup_stm32f407xx.s + Uses + At line 35 in file startup_stm32f407xx.s + At line 413 in file startup_stm32f407xx.s + +__Vectors_Size 00000188 + +Symbol: __Vectors_Size + Definitions + At line 164 in file startup_stm32f407xx.s + Uses + At line 58 in file startup_stm32f407xx.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 171 in file startup_stm32f407xx.s + Uses + At line 174 in file startup_stm32f407xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 172 in file startup_stm32f407xx.s + Uses + At line 176 in file startup_stm32f407xx.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 407 in file startup_stm32f407xx.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +448 symbols in table diff --git a/MDK-ARM/startup_stm32f407xx.s b/MDK-ARM/startup_stm32f407xx.s new file mode 100644 index 0000000..3b597c7 --- /dev/null +++ b/MDK-ARM/startup_stm32f407xx.s @@ -0,0 +1,422 @@ +;******************************************************************************* +;* File Name : startup_stm32f407xx.s +;* Author : MCD Application Team +;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x2000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x1000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h new file mode 100644 index 0000000..711408a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2013-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V2.1.0 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h FreeRTOS header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +#include "FreeRTOS.h" +#include "task.h" + +#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR)) +#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0]) + +#define osKernelSystemId RTOS_ID_s ///< RTOS identification string + +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available + +#if defined(__CC_ARM) +#define os_InRegs __value_in_regs +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define os_InRegs __attribute__((value_in_regs)) +#else +#define os_InRegs +#endif + +#include "cmsis_os2.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \ +static StaticTask_t os_thread_cb_##name; \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, \ + (instances == 1) ? (&os_thread_cb_##name) : NULL,\ + (instances == 1) ? sizeof(StaticTask_t) : 0U, \ + ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \ + 8*((stacksz+7)/8), \ + (priority), 0U, 0U } } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +os_InRegs osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +static StaticTimer_t os_timer_cb_##name; \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +static StaticSemaphore_t os_mutex_cb_##name; \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +static StaticSemaphore_t os_semaphore_cb_##name; \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), {NULL} } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +static StaticQueue_t os_mq_cb_##name; \ +static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), \ + { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \ + (&os_mq_data_##name), sizeof(os_mq_data_##name) } } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c new file mode 100644 index 0000000..69ac328 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c @@ -0,0 +1,2482 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.c + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#include + +#include "cmsis_os2.h" // ::CMSIS:RTOS2 +#include "cmsis_compiler.h" // Compiler agnostic definitions + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core +#include "task.h" // ARM.FreeRTOS::RTOS:Core +#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups +#include "semphr.h" // ARM.FreeRTOS::RTOS:Core + +#include "freertos_mpool.h" // osMemoryPool definitions +#include "freertos_os2.h" // Configuration check and setup + +/*---------------------------------------------------------------------------*/ +#ifndef __ARM_ARCH_6M__ + #define __ARM_ARCH_6M__ 0 +#endif +#ifndef __ARM_ARCH_7M__ + #define __ARM_ARCH_7M__ 0 +#endif +#ifndef __ARM_ARCH_7EM__ + #define __ARM_ARCH_7EM__ 0 +#endif +#ifndef __ARM_ARCH_8M_MAIN__ + #define __ARM_ARCH_8M_MAIN__ 0 +#endif +#ifndef __ARM_ARCH_7A__ + #define __ARM_ARCH_7A__ 0 +#endif + +#if ((__ARM_ARCH_7M__ == 1U) || \ + (__ARM_ARCH_7EM__ == 1U) || \ + (__ARM_ARCH_8M_MAIN__ == 1U)) +#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) +#elif (__ARM_ARCH_6M__ == 1U) +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#elif (__ARM_ARCH_7A__ == 1U) +/* CPSR mask bits */ +#define CPSR_MASKBIT_I 0x80U + +#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U) +#else +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#endif + +#if (__ARM_ARCH_7A__ == 1U) +/* CPSR mode bitmasks */ +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) +#else +#define IS_IRQ_MODE() (__get_IPSR() != 0U) +#endif + +#define IS_IRQ() IS_IRQ_MODE() + +#define SVCall_IRQ_NBR (IRQn_Type) -5 /* SVCall_IRQ_NBR added as SV_Call handler name is not the same for CM0 and for all other CMx */ + +/* Limits */ +#define MAX_BITS_TASK_NOTIFY 31U +#define MAX_BITS_EVENT_GROUPS 24U + +#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U)) +#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U)) + +/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */ +#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \ + ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \ + ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL)) + +#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +/* Timer callback information structure definition */ +typedef struct { + osTimerFunc_t func; + void *arg; +} TimerCallback_t; + +/* Kernel initialization state */ +static osKernelState_t KernelState = osKernelInactive; + +/* + Heap region definition used by heap_5 variant + + Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if + heap regions are already defined and vPortDefineHeapRegions is called in application. + + Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using + definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS + is possible by defining it globally or in FreeRTOSConfig.h. +*/ +#if defined(USE_FreeRTOS_HEAP_5) +#if (configAPPLICATION_ALLOCATED_HEAP == 0) + /* + FreeRTOS heap is not defined by the application. + Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h) + is provided by default. Define configHEAP_5_REGIONS to provide custom + HeapRegion_t array. + */ + #define HEAP_5_REGION_SETUP 1 + + #ifndef configHEAP_5_REGIONS + #define configHEAP_5_REGIONS xHeapRegions + + static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + + static HeapRegion_t xHeapRegions[] = { + { ucHeap, configTOTAL_HEAP_SIZE }, + { NULL, 0 } + }; + #else + /* Global definition is provided to override default heap array */ + extern HeapRegion_t configHEAP_5_REGIONS[]; + #endif +#else + /* + The application already defined the array used for the FreeRTOS heap and + called vPortDefineHeapRegions to initialize heap. + */ + #define HEAP_5_REGION_SETUP 0 +#endif /* configAPPLICATION_ALLOCATED_HEAP */ +#endif /* USE_FreeRTOS_HEAP_5 */ + +#if defined(SysTick) +#undef SysTick_Handler + +/* CMSIS SysTick interrupt handler prototype */ +extern void SysTick_Handler (void); +/* FreeRTOS tick timer interrupt handler prototype */ +extern void xPortSysTickHandler (void); + +/* + SysTick handler implementation that also clears overflow flag. +*/ +#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) +void SysTick_Handler (void) { + /* Clear overflow flag */ + SysTick->CTRL; + + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + /* Call tick handler */ + xPortSysTickHandler(); + } +} +#endif +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + NVIC_SetPriority (SVCall_IRQ_NBR, 0U); +#endif +} + +/* + Function macro used to retrieve semaphore count from ISR +*/ +#ifndef uxSemaphoreGetCountFromISR +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) +#endif + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void); +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void); +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void); +/*---------------------------------------------------------------------------*/ + +osStatus_t osKernelInitialize (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelInactive) { + #if defined(USE_TRACE_EVENT_RECORDER) + EvrFreeRTOSSetup(0U); + #endif + #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); + #endif + KernelState = osKernelReady; + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + + if (version != NULL) { + /* Version encoding is major.minor.rev: mmnnnrrrr dec */ + version->api = KERNEL_VERSION; + version->kernel = KERNEL_VERSION; + } + + if ((id_buf != NULL) && (id_size != 0U)) { + if (id_size > sizeof(KERNEL_ID)) { + id_size = sizeof(KERNEL_ID); + } + memcpy(id_buf, KERNEL_ID, id_size); + } + + return (osOK); +} + +osKernelState_t osKernelGetState (void) { + osKernelState_t state; + + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_RUNNING: + state = osKernelRunning; + break; + + case taskSCHEDULER_SUSPENDED: + state = osKernelLocked; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + if (KernelState == osKernelReady) { + state = osKernelReady; + } else { + state = osKernelInactive; + } + break; + } + + return (state); +} + +osStatus_t osKernelStart (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelReady) { + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + /* Start the kernel scheduler */ + vTaskStartScheduler(); + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +int32_t osKernelLock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + break; + + case taskSCHEDULER_RUNNING: + vTaskSuspendAll(); + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelUnlock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) { + lock = (int32_t)osError; + } + } + break; + + case taskSCHEDULER_RUNNING: + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelRestoreLock (int32_t lock) { + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + case taskSCHEDULER_RUNNING: + if (lock == 1) { + vTaskSuspendAll(); + } + else { + if (lock != 0) { + lock = (int32_t)osError; + } + else { + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { + lock = (int32_t)osError; + } + } + } + } + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +uint32_t osKernelGetTickCount (void) { + TickType_t ticks; + + if (IS_IRQ()) { + ticks = xTaskGetTickCountFromISR(); + } else { + ticks = xTaskGetTickCount(); + } + + return (ticks); +} + +uint32_t osKernelGetTickFreq (void) { + return (configTICK_RATE_HZ); +} + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +uint32_t osKernelGetSysTimerCount (void) { + uint32_t irqmask = IS_IRQ_MASKED(); + TickType_t ticks; + uint32_t val; + + __disable_irq(); + + ticks = xTaskGetTickCount(); + val = OS_Tick_GetCount(); + + if (OS_Tick_GetOverflow() != 0U) { + val = OS_Tick_GetCount(); + ticks++; + } + val += ticks * OS_Tick_GetInterval(); + + if (irqmask == 0U) { + __enable_irq(); + } + + return (val); +} + +uint32_t osKernelGetSysTimerFreq (void) { + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + const char *name; + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + + if (!IS_IRQ() && (func != NULL)) { + stack = configMINIMAL_STACK_SIZE; + prio = (UBaseType_t)osPriorityNormal; + + name = NULL; + mem = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + if (attr->priority != osPriorityNone) { + prio = (UBaseType_t)attr->priority; + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + return (NULL); + } + + if (attr->stack_size > 0U) { + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + (StaticTask_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + hTask = NULL; + } + #endif + } + } + } + + return ((osThreadId_t)hTask); +} + +const char *osThreadGetName (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + const char *name; + + if (IS_IRQ() || (hTask == NULL)) { + name = NULL; + } else { + name = pcTaskGetName (hTask); + } + + return (name); +} + +osThreadId_t osThreadGetId (void) { + osThreadId_t id; + + id = (osThreadId_t)xTaskGetCurrentTaskHandle(); + + return (id); +} + +osThreadState_t osThreadGetState (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osThreadState_t state; + + if (IS_IRQ() || (hTask == NULL)) { + state = osThreadError; + } + else { + switch (eTaskGetState (hTask)) { + case eRunning: state = osThreadRunning; break; + case eReady: state = osThreadReady; break; + case eBlocked: + case eSuspended: state = osThreadBlocked; break; + case eDeleted: state = osThreadTerminated; break; + case eInvalid: + default: state = osThreadError; break; + } + } + + return (state); +} + +uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t sz; + + if (IS_IRQ() || (hTask == NULL)) { + sz = 0U; + } else { + sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t)); + } + + return (sz); +} + +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskPrioritySet (hTask, (UBaseType_t)priority); + } + + return (stat); +} + +osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osPriority_t prio; + + if (IS_IRQ() || (hTask == NULL)) { + prio = osPriorityError; + } else { + prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask)); + } + + return (prio); +} + +osStatus_t osThreadYield (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else { + stat = osOK; + taskYIELD(); + } + + return (stat); +} + +#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) +osStatus_t osThreadSuspend (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskSuspend (hTask); + } + + return (stat); +} + +osStatus_t osThreadResume (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskResume (hTask); + } + + return (stat); +} +#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */ + +__NO_RETURN void osThreadExit (void) { +#ifndef USE_FreeRTOS_HEAP_1 + vTaskDelete (NULL); +#endif + for (;;); +} + +osStatus_t osThreadTerminate (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + eTaskState tstate; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + tstate = eTaskGetState (hTask); + + if (tstate != eDeleted) { + stat = osOK; + vTaskDelete (hTask); + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} + +uint32_t osThreadGetCount (void) { + uint32_t count; + + if (IS_IRQ()) { + count = 0U; + } else { + count = uxTaskGetNumberOfTasks(); + } + + return (count); +} + +#if (configUSE_OS2_THREAD_ENUMERATE == 1) +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + uint32_t i, count; + TaskStatus_t *task; + + if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) { + count = 0U; + } else { + vTaskSuspendAll(); + + count = uxTaskGetNumberOfTasks(); + task = pvPortMalloc (count * sizeof(TaskStatus_t)); + + if (task != NULL) { + count = uxTaskGetSystemState (task, count, NULL); + + for (i = 0U; (i < count) && (i < array_items); i++) { + thread_array[i] = (osThreadId_t)task[i].xHandle; + } + count = i; + } + (void)xTaskResumeAll(); + + vPortFree (task); + } + + return (count); +} +#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */ + +#if (configUSE_OS2_THREAD_FLAGS == 1) +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t rflags; + BaseType_t yield; + + if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else { + rflags = (uint32_t)osError; + + if (IS_IRQ()) { + yield = pdFALSE; + + (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); + (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); + + portYIELD_FROM_ISR (yield); + } + else { + (void)xTaskNotify (hTask, flags, eSetBits); + (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); + } + } + /* Return flags after setting */ + return (rflags); +} + +uint32_t osThreadFlagsClear (uint32_t flags) { + TaskHandle_t hTask; + uint32_t rflags, cflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) { + rflags = cflags; + cflags &= ~flags; + + if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) { + rflags = (uint32_t)osError; + } + } + else { + rflags = (uint32_t)osError; + } + } + + /* Return flags before clearing */ + return (rflags); +} + +uint32_t osThreadFlagsGet (void) { + TaskHandle_t hTask; + uint32_t rflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) { + rflags = (uint32_t)osError; + } + } + + return (rflags); +} + +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t rflags, nval; + uint32_t clear; + TickType_t t0, td, tout; + BaseType_t rval; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + if ((options & osFlagsNoClear) == osFlagsNoClear) { + clear = 0U; + } else { + clear = flags; + } + + rflags = 0U; + tout = timeout; + + t0 = xTaskGetTickCount(); + do { + rval = xTaskNotifyWait (0, clear, &nval, tout); + + if (rval == pdPASS) { + rflags &= flags; + rflags |= nval; + + if ((options & osFlagsWaitAll) == osFlagsWaitAll) { + if ((flags & rflags) == flags) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + else { + if ((flags & rflags) != 0) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + + /* Update timeout */ + td = xTaskGetTickCount() - t0; + + if (td > tout) { + tout = 0; + } else { + tout -= td; + } + } + else { + if (timeout == 0) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = (uint32_t)osErrorTimeout; + } + } + } + while (rval != pdFAIL); + } + + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +osStatus_t osDelay (uint32_t ticks) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + + if (ticks != 0U) { + vTaskDelay(ticks); + } + } + + return (stat); +} + +osStatus_t osDelayUntil (uint32_t ticks) { + TickType_t tcnt, delay; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + tcnt = xTaskGetTickCount(); + + /* Determine remaining number of ticks to delay */ + delay = (TickType_t)ticks - tcnt; + + /* Check if target tick has not expired */ + if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) { + vTaskDelayUntil (&tcnt, delay); + } + else + { + /* No delay or already expired */ + stat = osErrorParameter; + } + } + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_TIMER == 1) + +static void TimerCallback (TimerHandle_t hTimer) { + TimerCallback_t *callb; + + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (callb != NULL) { + callb->func (callb->arg); + } +} + +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + const char *name; + TimerHandle_t hTimer; + TimerCallback_t *callb; + UBaseType_t reload; + int32_t mem; + + hTimer = NULL; + + if (!IS_IRQ() && (func != NULL)) { + /* Allocate memory to store callback function and argument */ + callb = pvPortMalloc (sizeof(TimerCallback_t)); + + if (callb != NULL) { + callb->func = func; + callb->arg = argument; + + if (type == osTimerOnce) { + reload = pdFALSE; + } else { + reload = pdTRUE; + } + + mem = -1; + name = NULL; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); + #endif + } + } + + if ((hTimer == NULL) && (callb != NULL)) { + vPortFree (callb); + } + } + } + + return ((osTimerId_t)hTimer); +} + +const char *osTimerGetName (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + const char *p; + + if (IS_IRQ() || (hTimer == NULL)) { + p = NULL; + } else { + p = pcTimerGetName (hTimer); + } + + return (p); +} + +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { + stat = osOK; + } else { + stat = osErrorResource; + } + } + + return (stat); +} + +osStatus_t osTimerStop (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerIsTimerActive (hTimer) == pdFALSE) { + stat = osErrorResource; + } + else { + if (xTimerStop (hTimer, 0) == pdPASS) { + stat = osOK; + } else { + stat = osError; + } + } + } + + return (stat); +} + +uint32_t osTimerIsRunning (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + uint32_t running; + + if (IS_IRQ() || (hTimer == NULL)) { + running = 0U; + } else { + running = (uint32_t)xTimerIsTimerActive (hTimer); + } + + return (running); +} + +osStatus_t osTimerDelete (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + TimerCallback_t *callb; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (xTimerDelete (hTimer, 0) == pdPASS) { + vPortFree (callb); + stat = osOK; + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_TIMER == 1) */ + +/*---------------------------------------------------------------------------*/ + +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + EventGroupHandle_t hEventGroup; + int32_t mem; + + hEventGroup = NULL; + + if (!IS_IRQ()) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreateStatic (attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreate(); + #endif + } + } + } + + return ((osEventFlagsId_t)hEventGroup); +} + +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + BaseType_t yield; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + (void)yield; + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + yield = pdFALSE; + + if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = flags; + portYIELD_FROM_ISR (yield); + } + #endif + } + else { + rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; + #else + rflags = xEventGroupGetBitsFromISR (hEventGroup); + + if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } + #endif + } + else { + rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if (ef_id == NULL) { + rflags = 0U; + } + else if (IS_IRQ()) { + rflags = xEventGroupGetBitsFromISR (hEventGroup); + } + else { + rflags = xEventGroupGetBits (hEventGroup); + } + + return (rflags); +} + +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + BaseType_t wait_all; + BaseType_t exit_clr; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + if (options & osFlagsWaitAll) { + wait_all = pdTRUE; + } else { + wait_all = pdFAIL; + } + + if (options & osFlagsNoClear) { + exit_clr = pdFAIL; + } else { + exit_clr = pdTRUE; + } + + rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout); + + if (options & osFlagsWaitAll) { + if ((flags & rflags) != flags) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + else { + if ((flags & rflags) == 0U) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + } + + return (rflags); +} + +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hEventGroup == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vEventGroupDelete (hEventGroup); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_MUTEX == 1) + +osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + SemaphoreHandle_t hMutex; + uint32_t type; + uint32_t rmtx; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hMutex = NULL; + + if (!IS_IRQ()) { + if (attr != NULL) { + type = attr->attr_bits; + } else { + type = 0U; + } + + if ((type & osMutexRecursive) == osMutexRecursive) { + rmtx = 1U; + } else { + rmtx = 0U; + } + + if ((type & osMutexRobust) != osMutexRobust) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); + #endif + } + else { + hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); + } + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutex (); + #endif + } else { + hMutex = xSemaphoreCreateMutex (); + } + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hMutex != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hMutex, name); + } + #endif + + if ((hMutex != NULL) && (rmtx != 0U)) { + hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); + } + } + } + + return ((osMutexId_t)hMutex); +} + +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + #endif + } + else { + if (xSemaphoreTake (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMutexRelease (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { + #if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { + stat = osErrorResource; + } + #endif + } + else { + if (xSemaphoreGive (hMutex) != pdPASS) { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osThreadId_t owner; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ() || (hMutex == NULL)) { + owner = NULL; + } else { + owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex); + } + + return (owner); +} + +osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + SemaphoreHandle_t hMutex; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hMutex); + #endif + stat = osOK; + vSemaphoreDelete (hMutex); + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_MUTEX == 1) */ + +/*---------------------------------------------------------------------------*/ + +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + SemaphoreHandle_t hSemaphore; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hSemaphore = NULL; + + if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem != -1) { + if (max_count == 1U) { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinary(); + #endif + } + + if ((hSemaphore != NULL) && (initial_count != 0U)) { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + vSemaphoreDelete (hSemaphore); + hSemaphore = NULL; + } + } + } + else { + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); + #endif + } + else { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hSemaphore != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hSemaphore, name); + } + #endif + } + } + + return ((osSemaphoreId_t)hSemaphore); +} + +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + if (timeout != 0U) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + yield = pdFALSE; + + if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + else { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + stat = osErrorResource; + } + } + + return (stat); +} + +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + uint32_t count; + + if (hSemaphore == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hSemaphore); + } else { + count = (uint32_t)uxSemaphoreGetCount (hSemaphore); + } + + return (count); +} + +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hSemaphore); + #endif + + stat = osOK; + vSemaphoreDelete (hSemaphore); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ + +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + QueueHandle_t hQueue; + int32_t mem; + #if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; + #endif + + hQueue = NULL; + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { + #if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); + #endif + } + else { + if (mem == 0) { + #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); + #endif + } + } + + #if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hQueue, name); + } + #endif + + } + + return ((osMessageQueueId_t)hQueue); +} + +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t capacity; + + if (mq == NULL) { + capacity = 0U; + } else { + /* capacity = pxQueue->uxLength */ + capacity = mq->uxDummy4[1]; + } + + return (capacity); +} + +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t size; + + if (mq == NULL) { + size = 0U; + } else { + /* size = pxQueue->uxItemSize */ + size = mq->uxDummy4[2]; + } + + return (size); +} + +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hQueue); + } + else { + count = uxQueueMessagesWaiting (hQueue); + } + + return ((uint32_t)count); +} + +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } + else if (IS_IRQ()) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + else { + space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq); + } + + return (space); +} + +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + (void)xQueueReset (hQueue); + } + + return (stat); +} + +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + #if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hQueue); + #endif + + stat = osOK; + vQueueDelete (hQueue); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#ifdef FREERTOS_MPOOL_H_ + +/* Static memory pool functions */ +static void FreeBlock (MemPool_t *mp, void *block); +static void *AllocBlock (MemPool_t *mp); +static void *CreateBlock (MemPool_t *mp); + +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + MemPool_t *mp; + const char *name; + int32_t mem_cb, mem_mp; + uint32_t sz; + + if (IS_IRQ()) { + mp = NULL; + } + else if ((block_count == 0U) || (block_size == 0U)) { + mp = NULL; + } + else { + mp = NULL; + sz = MEMPOOL_ARR_SIZE (block_count, block_size); + + name = NULL; + mem_cb = -1; + mem_mp = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) { + /* Static control block is provided */ + mem_cb = 1; + } + else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + /* Allocate control block memory on heap */ + mem_cb = 0; + } + + if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) { + /* Allocate memory array on heap */ + mem_mp = 0; + } + else { + if (attr->mp_mem != NULL) { + /* Check if array is 4-byte aligned */ + if (((uint32_t)attr->mp_mem & 3U) == 0U) { + /* Check if array big enough */ + if (attr->mp_size >= sz) { + /* Static memory pool array is provided */ + mem_mp = 1; + } + } + } + } + } + else { + /* Attributes not provided, allocate memory on heap */ + mem_cb = 0; + mem_mp = 0; + } + + if (mem_cb == 0) { + mp = pvPortMalloc (sizeof(MemPool_t)); + } else { + mp = attr->cb_mem; + } + + if (mp != NULL) { + /* Create a semaphore (max count == initial count == block_count) */ + #if (configSUPPORT_STATIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem); + #elif (configSUPPORT_DYNAMIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCounting (block_count, block_count); + #else + mp->sem == NULL; + #endif + + if (mp->sem != NULL) { + /* Setup memory array */ + if (mem_mp == 0) { + mp->mem_arr = pvPortMalloc (sz); + } else { + mp->mem_arr = attr->mp_mem; + } + } + } + + if ((mp != NULL) && (mp->mem_arr != NULL)) { + /* Memory pool can be created */ + mp->head = NULL; + mp->mem_sz = sz; + mp->name = name; + mp->bl_sz = block_size; + mp->bl_cnt = block_count; + mp->n = 0U; + + /* Set heap allocated memory flags */ + mp->status = MPOOL_STATUS; + + if (mem_cb == 0) { + /* Control block on heap */ + mp->status |= 1U; + } + if (mem_mp == 0) { + /* Memory array on heap */ + mp->status |= 2U; + } + } + else { + /* Memory pool cannot be created, release allocated resources */ + if ((mem_cb == 0) && (mp != NULL)) { + /* Free control block memory */ + vPortFree (mp); + } + mp = NULL; + } + } + + return (mp); +} + +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { + MemPool_t *mp = (osMemoryPoolId_t)mp_id; + const char *p; + + if (IS_IRQ()) { + p = NULL; + } + else if (mp_id == NULL) { + p = NULL; + } + else { + p = mp->name; + } + + return (p); +} + +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + MemPool_t *mp; + void *block; + uint32_t isrm; + + if (mp_id == NULL) { + /* Invalid input parameters */ + block = NULL; + } + else { + block = NULL; + + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + if (IS_IRQ()) { + if (timeout == 0U) { + if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + } + } + } + else { + if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + taskENTER_CRITICAL(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL(); + } + } + } + } + } + + return (block); +} + +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + MemPool_t *mp; + osStatus_t stat; + uint32_t isrm; + BaseType_t yield; + + if ((mp_id == NULL) || (block == NULL)) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + stat = osErrorResource; + } + else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) { + /* Block pointer outside of memory array area */ + stat = osErrorParameter; + } + else { + stat = osOK; + + if (IS_IRQ()) { + if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL_FROM_ISR(isrm); + + yield = pdFALSE; + xSemaphoreGiveFromISR (mp->sem, &yield); + portYIELD_FROM_ISR (yield); + } + } + else { + if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + taskENTER_CRITICAL(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL(); + + xSemaphoreGive (mp->sem); + } + } + } + } + + return (stat); +} + +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + n = mp->bl_cnt; + } + } + + /* Return maximum number of memory blocks */ + return (n); +} + +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t sz; + + if (mp_id == NULL) { + /* Invalid input parameters */ + sz = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + sz = 0U; + } + else { + sz = mp->bl_sz; + } + } + + /* Return memory block size in bytes */ + return (sz); +} + +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + + n = mp->bl_cnt - n; + } + } + + /* Return number of memory blocks used */ + return (n); +} + +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + } + } + + /* Return number of memory blocks available */ + return (n); +} + +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + osStatus_t stat; + + if (mp_id == NULL) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else if (IS_IRQ()) { + stat = osErrorISR; + } + else { + mp = (MemPool_t *)mp_id; + + taskENTER_CRITICAL(); + + /* Invalidate control block status */ + mp->status = mp->status & 3U; + + /* Wake-up tasks waiting for pool semaphore */ + while (xSemaphoreGive (mp->sem) == pdTRUE); + + mp->head = NULL; + mp->bl_sz = 0U; + mp->bl_cnt = 0U; + + if ((mp->status & 2U) != 0U) { + /* Memory pool array allocated on heap */ + vPortFree (mp->mem_arr); + } + if ((mp->status & 1U) != 0U) { + /* Memory pool control block allocated on heap */ + vPortFree (mp); + } + + taskEXIT_CRITICAL(); + + stat = osOK; + } + + return (stat); +} + +/* + Create new block given according to the current block index. +*/ +static void *CreateBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->n < mp->bl_cnt) { + /* Unallocated blocks exist, set pointer to new block */ + p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n)); + + /* Increment block index */ + mp->n += 1U; + } + + return (p); +} + +/* + Allocate a block by reading the list of free blocks. +*/ +static void *AllocBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->head != NULL) { + /* List of free block exists, get head block */ + p = mp->head; + + /* Head block is now next on the list */ + mp->head = p->next; + } + + return (p); +} + +/* + Free block by putting it to the list of free blocks. +*/ +static void FreeBlock (MemPool_t *mp, void *block) { + MemPoolBlock_t *p = block; + + /* Store current head into block memory space */ + p->next = mp->head; + + /* Store current block as new head */ + mp->head = p; +} +#endif /* FREERTOS_MPOOL_H_ */ +/*---------------------------------------------------------------------------*/ + +/* Callback function prototypes */ +extern void vApplicationIdleHook (void); +extern void vApplicationTickHook (void); +extern void vApplicationMallocFailedHook (void); +extern void vApplicationDaemonTaskStartupHook (void); +extern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName); + +/** + Dummy implementation of the callback function vApplicationIdleHook(). +*/ +#if (configUSE_IDLE_HOOK == 1) +__WEAK void vApplicationIdleHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationTickHook(). +*/ +#if (configUSE_TICK_HOOK == 1) + __WEAK void vApplicationTickHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationMallocFailedHook(). +*/ +#if (configUSE_MALLOC_FAILED_HOOK == 1) +__WEAK void vApplicationMallocFailedHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationDaemonTaskStartupHook(). +*/ +#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1) +__WEAK void vApplicationDaemonTaskStartupHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationStackOverflowHook(). +*/ +#if (configCHECK_FOR_STACK_OVERFLOW > 0) +__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) { + (void)xTask; + (void)pcTaskName; + configASSERT(0); +} +#endif + +/*---------------------------------------------------------------------------*/ +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* External Idle and Timer task static memory allocation functions */ +extern void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize); +extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize); + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; +} + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; +} +#endif diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h new file mode 100644 index 0000000..9774cc7 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h @@ -0,0 +1,734 @@ +/* -------------------------------------------------------------------------- + * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * -------------------------------------------------------------------------- + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as NULL terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as NULL terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as NULL terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as NULL terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as NULL terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as NULL terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as NULL terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h new file mode 100644 index 0000000..cea5017 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h @@ -0,0 +1,63 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_mpool.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_MPOOL_H_ +#define FREERTOS_MPOOL_H_ + +#include +#include "FreeRTOS.h" +#include "semphr.h" + +/* Memory Pool implementation definitions */ +#define MPOOL_STATUS 0x5EED0000U + +/* Memory Block header */ +typedef struct { + void *next; /* Pointer to next block */ +} MemPoolBlock_t; + +/* Memory Pool control block */ +typedef struct MemPoolDef_t { + MemPoolBlock_t *head; /* Pointer to head block */ + SemaphoreHandle_t sem; /* Pool semaphore handle */ + uint8_t *mem_arr; /* Pool memory array */ + uint32_t mem_sz; /* Pool memory array size */ + const char *name; /* Pointer to name string */ + uint32_t bl_sz; /* Size of a single block */ + uint32_t bl_cnt; /* Number of blocks */ + uint32_t n; /* Block allocation index */ + volatile uint32_t status; /* Object status flags */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mem_sem; /* Semaphore object memory */ +#endif +} MemPool_t; + +/* No need to hide static object type, just align to coding style */ +#define StaticMemPool_t MemPool_t + +/* Define memory pool control block size */ +#define MEMPOOL_CB_SIZE (sizeof(StaticMemPool_t)) + +/* Define size of the byte array required to create count of blocks of given size */ +#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count)) + +#endif /* FREERTOS_MPOOL_H_ */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h new file mode 100644 index 0000000..c125e2a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h @@ -0,0 +1,310 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_OS2_H_ +#define FREERTOS_OS2_H_ + +#include +#include + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core + +#include CMSIS_device_header + +/* + CMSIS-RTOS2 FreeRTOS image size optimization definitions. + + Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when + certain functionality is not required when using CMSIS-RTOS2 API. + In general optimization decisions are left to the tool chain but in cases + when coding style prevents it to optimize the code following optional + definitions can be used. +*/ + +/* + Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from + the application image. +*/ +#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image. +*/ +#ifndef configUSE_OS2_THREAD_ENUMERATE +#define configUSE_OS2_THREAD_ENUMERATE 1 +#endif + +/* + Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear + operation from ISR. +*/ +#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image. +*/ +#ifndef configUSE_OS2_THREAD_FLAGS +#define configUSE_OS2_THREAD_FLAGS configUSE_TASK_NOTIFICATIONS +#endif + +/* + Option to exclude CMSIS-RTOS2 Timer API functions from the application image. +*/ +#ifndef configUSE_OS2_TIMER +#define configUSE_OS2_TIMER configUSE_TIMERS +#endif + +/* + Option to exclude CMSIS-RTOS2 Mutex API functions from the application image. +*/ +#ifndef configUSE_OS2_MUTEX +#define configUSE_OS2_MUTEX configUSE_MUTEXES +#endif + + +/* + CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h). + + Note: CMSIS-RTOS API requires functions included by using following definitions. + In case if certain API function is not used compiler will optimize it away. +*/ +#if (INCLUDE_xSemaphoreGetMutexHolder == 0) + /* + CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if + osMutexGetOwner is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error. + */ + #error "Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API." +#endif +#if (INCLUDE_vTaskDelay == 0) + /* + CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if + osDelay is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelay 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelayUntil == 0) + /* + CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if + osDelayUntil is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelayUntil 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelete == 0) + /* + CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function + vTaskDelete. In case if they are not used in the application image, compiler + will optimize them away. + Set #define INCLUDE_vTaskDelete 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetCurrentTaskHandle == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement + functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these + functions are not used in the application image, compiler will optimize them away. + Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetSchedulerState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel + tick handling and therefore it is vital that xTaskGetSchedulerState is included into + the application image. + Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API." +#endif +#if (INCLUDE_uxTaskGetStackHighWaterMark == 0) + /* + CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark. + In case if osThreadGetStackSpace is not used in the application image, compiler will + optimize it away. + Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_uxTaskPriorityGet == 0) + /* + CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if + osThreadGetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskPrioritySet == 0) + /* + CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if + osThreadSetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskPrioritySet 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_eTaskGetState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState + and osThreadTerminate. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define INCLUDE_eTaskGetState 1 to fix this error. + */ + #error "Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskSuspend == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement + functions osThreadSuspend and osThreadResume. In case if these functions are not + used in the application image, compiler will optimize them away. + Set #define INCLUDE_vTaskSuspend 1 to fix this error. + + Alternatively, if the application does not use osThreadSuspend and + osThreadResume they can be excluded from the image code by setting: + #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) + #error "Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API." + #endif +#endif +#if (INCLUDE_xTimerPendFunctionCall == 0) + /* + CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from + the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and + xEventGroupClearBitsFromISR which are only enabled if timers are operational and + xTimerPendFunctionCall in enabled. + Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1 + to fix this error. + + Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear + from the ISR their operation from ISR can be restricted by setting: + #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1) + #error "Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API." + #endif +#endif + +#if (configUSE_TIMERS == 0) + /* + CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement + timer management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TIMERS 1 to fix this error. + + Alternatively, if the application does not use timer functions they can be + excluded from the image code by setting: + #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_TIMER == 1) + #error "Definition configUSE_TIMERS must equal 1 to implement Timer Management API." + #endif +#endif + +#if (configUSE_MUTEXES == 0) + /* + CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement + mutex management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_MUTEXES 1 to fix this error. + + Alternatively, if the application does not use mutex functions they can be + excluded from the image code by setting: + #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_MUTEX == 1) + #error "Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API." + #endif +#endif + +#if (configUSE_COUNTING_SEMAPHORES == 0) + /* + CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting + to implement memory pools. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error. + */ + #error "Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API." +#endif +#if (configUSE_TASK_NOTIFICATIONS == 0) + /* + CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement + thread flag management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error. + + Alternatively, if the application does not use thread flags functions they can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_FLAGS == 1) + #error "Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API." + #endif +#endif + +#if (configUSE_TRACE_FACILITY == 0) + /* + CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState + which is only enabled if configUSE_TRACE_FACILITY == 1. + Set #define configUSE_TRACE_FACILITY 1 to fix this error. + + Alternatively, if the application does not use osThreadEnumerate it can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_ENUMERATE == 1) + #error "Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate." + #endif +#endif + +#if (configUSE_16_BIT_TICKS == 1) + /* + CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on + a 32-bit CPU architectures. + Set #define configUSE_16_BIT_TICKS 0 to fix this error. + */ + #error "Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API." +#endif + +#if (configMAX_PRIORITIES != 56) + /* + CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2 + implementation should implement the same number of priorities. + Set #define configMAX_PRIORITIES 56 to fix this error. + */ + #error "Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API." +#endif +#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0) + /* + CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port + optimised selection for Cortex core only handles 32 different priorities. + Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error. + */ + #error "Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API." +#endif + +#endif /* FREERTOS_OS2_H_ */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE new file mode 100644 index 0000000..2ce4711 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE @@ -0,0 +1,18 @@ +Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. +Permission is hereby granted, free of charge, to any person obtaining a copy of +this software and associated documentation files (the "Software"), to deal in +the Software without restriction, including without limitation the rights to +use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +the Software, and to permit persons to whom the Software is furnished to do so, +subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c new file mode 100644 index 0000000..9ce5003 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -0,0 +1,353 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER + #define static +#endif + + +/* Lists for ready and blocked co-routines. --------------------*/ +static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ +static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ +static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ +static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ +static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ +static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ +CRCB_t * pxCurrentCoRoutine = NULL; +static UBaseType_t uxTopCoRoutineReadyPriority = 0; +static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ +#define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ +#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ +{ \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ +} + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ +static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ +static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ +static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ) +{ +BaseType_t xReturn; +CRCB_t *pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + This is so we can get back to the containing CRCB from a generic item + in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ) +{ +TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + ourselves to the blocked list as the same list item is used for + both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckPendingReadyList( void ) +{ + /* Are there any co-routines waiting to get moved to the ready list? These + are co-routines that have been readied by an ISR. The ISR cannot access + the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t *pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } +} +/*-----------------------------------------------------------*/ + +static void prvCheckDelayedList( void ) +{ +CRCB_t *pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + section. If this is the case then the generic list item will + have been moved to the pending ready list and the following + line is still valid. Also the pvContainer parameter will have + been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; +} +/*-----------------------------------------------------------*/ + +void vCoRoutineSchedule( void ) +{ + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + + return; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseCoRoutineLists( void ) +{ +UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; +} +/*-----------------------------------------------------------*/ + +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ) +{ +CRCB_t *pxUnblockedCRCB; +BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + event lists and the pending ready list. This function assumes that a + check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} + +#endif /* configUSE_CO_ROUTINES == 0 */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c new file mode 100644 index 0000000..bf4ec24 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -0,0 +1,753 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified +because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined +for the header files above, but not in this file, in order to generate the +correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list +item value. It is important they don't clash with the +taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) + { + EventGroup_t *pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + variable of type StaticEventGroup_t equals the size of the real + event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + this event group was created statically in case the event group + is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + pxEventGroupBuffer pointing to a pre-allocated (compile time + allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t *pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + follows: pvPortMalloc() always ensures returned memory blocks are + aligned per the requirements of the MCU stack. In this case + pvPortMalloc() must return a pointer that is guaranteed to meet the + alignment requirements of the EventGroup_t structure - which (if you + follow it through) is the alignment requirements of the TickType_t type + (EventBits_t being of TickType_t itself). Therefore, whenever the + stack alignment requirements are greater than or equal to the + TickType_t alignment requirements the cast is safe. In other cases, + where the natural word size of the architecture is less than + sizeof( TickType_t ), the TickType_t variables will be accessed in two + or more reads operations, and the alignment requirements is only that + of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + event group was allocated statically in case the event group is + later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) +{ +EventBits_t uxOriginalBitValue, uxReturn; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + the task unblocks, but some compilers mistakenly generate a + warning about uxReturn being returned without being set if the + assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + bits it was waiting for were set, it is possible that since it + unblocked another task has set the bits. If this is the case + then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn, uxControlBits = 0; +BaseType_t xWaitConditionMet, xAlreadyYielded; +BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + set. uxControlBits are used to remember the specified behaviour of + this call to xEventGroupWaitBits() - for use when the event bits + unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + task's event list item so the kernel knows when a match is + found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + some compilers mistakenly generate a warning about the variable + being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + point either the required bits were set or the block time expired. If + the required bits were set they will have been stored in the task's + event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) +{ +EventGroup_t *pxEventBits = xEventGroup; +EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ +UBaseType_t uxSavedInterruptStatus; +EventGroup_t const * const pxEventBits = xEventGroup; +EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) +{ +ListItem_t *pxListItem, *pxNext; +ListItem_t const *pxListEnd; +List_t const * pxList; +EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; +EventGroup_t *pxEventBits = xEventGroup; +BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + item before removing the task from the event list. The + eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + that is was unblocked due to its required bits matching, rather + than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + used here as the list item may have been removed from the event list + and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ +EventGroup_t *pxEventBits = xEventGroup; +const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + it again. */ + vPortFree( pxEventBits ); + } + #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from +an interrupt. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from +an interrupt. */ +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) +{ +BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h new file mode 100644 index 0000000..ceb469a --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -0,0 +1,1295 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifndef INCLUDE_vTaskDelayUntil + #define INCLUDE_vTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. +The CBMC proofs need a way to track assumptions and assertions. +A configPRECONDITION statement should express an implicit invariant or +assumption made. A configASSERT statement should express an invariant that must +hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT(X) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + /* Used to perform any necessary initialisation - for example, open a file + into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + /* Use to close a trace, for example close a file into which trace has been + written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + /* Called after a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + /* Called before stepping the tick count after waking from tickless idle + sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + /* Called before a task has been selected to run. pxCurrentTCB holds a pointer + to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + /* Called when a task attempts to take a mutex that is already held by a + lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + that holds the mutex. uxInheritedPriority is the priority the mutex holder + will inherit (the priority of the task that is attempting to obtain the + muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + /* Called when a task releases a mutex, the holding of which had resulted in + the task inheriting the priority of a higher priority task. + pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + /* Task is about to block because it cannot read from a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the read was attempted. pxCurrentTCB points to the TCB of the + task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + /* Task is about to block because it cannot write to a + queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + upon which the write was attempted. pxCurrentTCB points to the TCB of the + task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 0 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE() +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK() +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT() +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY() +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR() +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR() +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + /* Defaults to uint16_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + /* Defaults to size_t for backward compatibility, but can be overridden + in FreeRTOSConfig.h if lengths will always be less than the number of bytes + in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if( configUSE_TICKLESS_IDLE != 0 ) + #if( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if( portTICK_TYPE_IS_ATOMIC == 0 ) + /* Either variables of tick type cannot be read atomically, or + portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + /* The tick type can be read atomically, so critical sections used when the + tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to +V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + /* configPRINTF() was not defined, so define it away to nothing. To use + configPRINTF() then define it as follows (where MyPrintFunction() is + provided by the application writer): + + void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + + Then call like a standard printf() function, but placing brackets around + all parameters so they are passed as a single parameter. For example: + configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + /* The application writer has not provided their own MAX macro, so define + the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + + /* Backward compatibility within the scheduler code only - these definitions + are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + + /* For libraries that break the list data hiding, and access list structure + members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even +if floating point hardware is otherwise supported by the FreeRTOS port in use. +This constant is not supported by all FreeRTOS ports that include floating +point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is +currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. +This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on +the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 4 ]; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void *pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void *pvDummy3; + StaticMiniListItem_t xDummy4; + #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void *pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void *pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void *pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void *pxDummy14; + #endif + #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18; + uint8_t ucDummy19; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void *pvDummy1[ 3 ]; + + union + { + void *pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint8_t ucDummy5[ 2 ]; + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void *pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif + +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif + +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void *pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void *pvDummy5; + TaskFunction_t pvDummy6; + #if( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; + +} StaticTimer_t; + +/* +* In line with software engineering best practice, especially when supplying a +* library that is likely to change in future versions, FreeRTOS implements a +* strict data hiding policy. This means the stream buffer structure used +* internally by FreeRTOS is not accessible to application code. However, if +* the application writer wants to statically allocate the memory required to +* create a stream buffer then the size of the stream buffer object needs to be +* know. The StaticStreamBuffer_t structure below is provided for this purpose. +* Its size and alignment requirements are guaranteed to match those of the +* genuine structure, no matter which architecture is being used, and no matter +* how the values in FreeRTOSConfig.h are set. Its contents are somewhat +* obfuscated in the hope users will recognise that it would be unwise to make +* direct use of the structure members. +*/ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +#ifdef __cplusplus +} +#endif + +#endif /* INC_FREERTOS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h new file mode 100644 index 0000000..5643991 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -0,0 +1,133 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + + /* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h new file mode 100644 index 0000000..ceca696 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h @@ -0,0 +1,414 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + + /* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + + /* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ +uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ +void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ +uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ +uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +#ifdef __cplusplus +} +#endif + +#endif /* ATOMIC_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h new file mode 100644 index 0000000..8d7069c --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h @@ -0,0 +1,720 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Used to hide the implementation of the co-routine control block. The +control block structure however has to be included in the header due to +the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + *
    + BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );
    + * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+
    + * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex ); + + +/** + * croutine. h + *
    + void vCoRoutineSchedule( void );
    + * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + 
    + // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineSchedule() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+
    + * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
    + crSTART( CoRoutineHandle_t xHandle );
    + * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0: + +/** + * croutine. h + * 
    + crEND();
    + * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): +#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): + +/** + * croutine. h + *
    + crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
    + * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + 
    + // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
    + * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
    + crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + 
    + // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }
    + * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )
    + * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + 
    + // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }
    + * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ +{ \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ +} + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + 
    + // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }
    + * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
    +  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )
    + * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + 
    + // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }
    + * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList ); + +#ifdef __cplusplus +} +#endif + +#endif /* CO_ROUTINE_H */ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h new file mode 100644 index 0000000..21657b9 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a +pre-processor definition was used to ensure the pre-processor found the correct +portmacro.h file for the port being used. That scheme was deprecated in favour +of setting the compiler's include path such that it found the correct +portmacro.h file - removing the need for the constant and allowing the +portmacro.h file to be located anywhere in relation to the port being used. The +definitions below remain in the code for backward compatibility only. New +projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + /* A short file name has to be used in place of the normal + FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far *pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h new file mode 100644 index 0000000..a87fdf3 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -0,0 +1,757 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + *
    + EventGroupHandle_t xEventGroupCreate( void );
+
    + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See http://www.freertos.org/a00111.html + * + * Example usage: + 
    +	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+
    + * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
    + EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+
    + * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see http://www.freertos.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + 
    +	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+
    + */ +#if( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+
    + * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+
    + * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
    + * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+
    + * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
    + * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+
    + * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
    + * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+
    + * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
    + * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + 
    +   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+
    + * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+
    + * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + 
    + // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+
    + * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
    + * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + *
    +	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
    + * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + *
    +	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
    + * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* EVENT_GROUPS_H */ + + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h new file mode 100644 index 0000000..a3e3024 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -0,0 +1,412 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + +#ifndef INC_FREERTOS_H + #error FreeRTOS.h must be included before list.h +#endif + +#ifndef LIST_H +#define LIST_H + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros that can be used to place known values within the list structures, +then check that the known values do not get corrupted during the execution of +the application. These may catch the list data structures being overwritten in +memory. They will not catch data errors caused by incorrect configuration or +use of FreeRTOS.*/ +#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + + /* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + + /* Define macros that will assert if one of the structure members does not + contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ +{ \ +List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ +} + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h new file mode 100644 index 0000000..0c3edb9 --- /dev/null +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h @@ -0,0 +1,803 @@ +/* + * FreeRTOS Kernel V10.3.1 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +#if defined( __cplusplus ) +extern "C" { +#endif + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * +
    +MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+
    + * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: +
    +
+void vAFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+const size_t xMessageBufferSizeBytes = 100;
+
+    // Create a message buffer that can hold 100 bytes.  The memory used to hold
+    // both the message buffer structure and the messages themselves is allocated
+    // dynamically.  Each message added to the buffer consumes an additional 4
+    // bytes which are used to hold the lengh of the message.
+    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+
+    if( xMessageBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // message buffer.
+    }
+    else
+    {
+        // The message buffer was created successfully and can now be used.
+    }
+
+
    + * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * +
    +MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+                                                  uint8_t *pucMessageBufferStorageArea,
+                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
+
    + * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: +
    +
+// Used to dimension the array used to hold the messages.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the messages within the message
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the message buffer structure.
+StaticMessageBuffer_t xMessageBufferStruct;
+
+void MyFunction( void )
+{
+MessageBufferHandle_t xMessageBuffer;
+
+    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+                                                 ucBufferStorage,
+                                                 &xMessageBufferStruct );
+
+    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+    // reference the created message buffer in other message buffer API calls.
+
+    // Other code that uses the message buffer can go here.
+}
+
+
    + * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * +
    +size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+                           const void *pvTxData,
+                           size_t xDataLengthBytes,
+                           TickType_t xTicksToWait );
+
    + *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+
    +void vAFunction( MessageBufferHandle_t xMessageBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the message buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the message buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xMessageBufferSend() times out before there was enough
+        // space in the buffer for the data to be written.
+    }
+
+    // Send the string to the message buffer.  Return immediately if there is
+    // not enough space in the buffer.
+    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+}
+
    
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+                                  const void *pvTxData,
+                                  size_t xDataLengthBytes,
+                                  BaseType_t *pxHigherPriorityTaskWoken );
+
    + *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+
    +// A message buffer that has already been created.
+MessageBufferHandle_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the message buffer.
+    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+                                            ( void * ) pcStringToSend,
+                                            strlen( pcStringToSend ),
+                                            &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The string could not be added to the message buffer because there was
+        // not enough free space in the buffer.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+                              void *pvRxData,
+                              size_t xBufferLengthBytes,
+                              TickType_t xTicksToWait );
+
    
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+
    +void vAFunction( MessageBuffer_t xMessageBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive the next message from the message buffer.  Wait in the Blocked
+    // state (so not using any CPU processing time) for a maximum of 100ms for
+    // a message to become available.
+    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+                                            ( void * ) ucRxData,
+                                            sizeof( ucRxData ),
+                                            xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+}
+
    
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+
    +size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+                                     void *pvRxData,
+                                     size_t xBufferLengthBytes,
+                                     BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+
    +// A message buffer that has already been created.
+MessageBuffer_t xMessageBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next message from the message buffer.
+    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains a message that is xReceivedBytes long.  Process
+        // the message here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xMessageBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+
    
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+
    +BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+
    
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+
    +size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+
    
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ 
    + size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ 
    
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+
    +BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+
    +BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+#if defined( __cplusplus )
+} /* extern "C" */
+#endif
+
+#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..a21b7a6
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,160 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..5f63d4f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
+		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueReceive							MPU_xQueueReceive
+		#define xQueuePeek								MPU_xQueuePeek
+		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
+		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Map standard message/stream_buffer.h API functions to the MPU
+		equivalents. */
+		#define xStreamBufferSend						MPU_xStreamBufferSend
+		#define xStreamBufferReceive					MPU_xStreamBufferReceive
+		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
+		#define vStreamBufferDelete						MPU_vStreamBufferDelete
+		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
+		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
+		#define xStreamBufferReset						MPU_xStreamBufferReset
+		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
+		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
+		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
+		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
+		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+
+
+		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+		macro so applications can place data in privileged access sections
+		(useful when using statically allocated objects). */
+		#define PRIVILEGED_FUNCTION
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define FREERTOS_SYSTEM_CALL
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..a2099c3
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,199 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+	#define portHAS_STACK_OVERFLOW_CHECKING 0
+#endif
+
+#ifndef portARCH_NAME
+	#define portARCH_NAME NULL
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+	#endif
+#else
+	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#else
+		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+	#endif
+#endif
+
+/* Used by heap_5.c to define the start address and size of each memory region
+that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..0d95130
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN		0
+#define pdFREERTOS_BIG_ENDIAN			1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..52ccca5
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1655 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * 
    + QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * 
    
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * 
    + QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * 
    
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 
    
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * 
    
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * 
    
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * 
    
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   
    +
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ 
    
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * 
    
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void * const pvBuffer,
+							 TickType_t xTicksToWait
+						 );
    
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);
    
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);
    
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    + struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ 
    
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
    
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
    
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    void vQueueDelete( QueueHandle_t xQueue );
    
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * 
    
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   
    +
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ 
    
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ 
    
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ 
    
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   
    + void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		portYIELD_FROM_ISR();
+	}
+ }
+ 
    
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * 
    + BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * 
    
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   
    +
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ 
    
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..787c791
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1140 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * 
    vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )
    
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateBinary( void )
    
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )
    
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )
    
+ *
+ * Macro to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+            // code these would not be just sequential calls as this would make
+            // no sense.  Instead the calls are likely to be buried inside
+            // a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+            // available to another task until it has also been given back
+            // three times.  Again it is unlikely that real code would have
+            // these calls sequentially, but instead buried in a more complex
+            // call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+            xSemaphoreGiveRecursive( xMutex );
+
+            // Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    xSemaphoreGive( SemaphoreHandle_t xSemaphore )
    
+ *
+ * Macro to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * 
    xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )
    
+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    + xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
    
+ *
+ * Macro to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ 
    + \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
    + xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )
    
+ *
+ * Macro to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateMutex( void )
    
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )
    
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )
    
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )
    
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )
    
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ 
    
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * 
    SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )
    
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ 
    + SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ 
    
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * 
    void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
    
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
    
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
    
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * 
    UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
    
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..b5bac08
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,129 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
+			( pulStack[ 1 ] != ulCheckValue ) ||														\
+			( pulStack[ 2 ] != ulCheckValue ) ||														\
+			( pulStack[ 3 ] != ulCheckValue ) )															\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..a8b68ad
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,859 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+#if defined( __cplusplus )
+extern "C" {
+#endif
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+
    +StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+
    
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+
    +
+void vAFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+
+    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+    // both the stream buffer structure and the data in the stream buffer is
+    // allocated dynamically.
+    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+
+    if( xStreamBuffer == NULL )
+    {
+        // There was not enough heap memory space available to create the
+        // stream buffer.
+    }
+    else
+    {
+        // The stream buffer was created successfully and can now be used.
+    }
+}
+
    
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+
    +StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+                                                size_t xTriggerLevelBytes,
+                                                uint8_t *pucStreamBufferStorageArea,
+                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
+
    
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+
    +
+// Used to dimension the array used to hold the streams.  The available space
+// will actually be one less than this, so 999.
+#define STORAGE_SIZE_BYTES 1000
+
+// Defines the memory that will actually hold the streams within the stream
+// buffer.
+static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+
+// The variable used to hold the stream buffer structure.
+StaticStreamBuffer_t xStreamBufferStruct;
+
+void MyFunction( void )
+{
+StreamBufferHandle_t xStreamBuffer;
+const size_t xTriggerLevel = 1;
+
+    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+                                               xTriggerLevel,
+                                               ucBufferStorage,
+                                               &xStreamBufferStruct );
+
+    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+    // reference the created stream buffer in other stream buffer API calls.
+
+    // Other code that uses the stream buffer can go here.
+}
+
+
    
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void *pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait );
+
    
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+
    +void vAFunction( StreamBufferHandle_t xStreamBuffer )
+{
+size_t xBytesSent;
+uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+char *pcStringToSend = "String to send";
+const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+
+    // Send an array to the stream buffer, blocking for a maximum of 100ms to
+    // wait for enough space to be available in the stream buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+
+    if( xBytesSent != sizeof( ucArrayToSend ) )
+    {
+        // The call to xStreamBufferSend() times out before there was enough
+        // space in the buffer for the data to be written, but it did
+        // successfully write xBytesSent bytes.
+    }
+
+    // Send the string to the stream buffer.  Return immediately if there is not
+    // enough space in the buffer.
+    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // The entire string could not be added to the stream buffer because
+        // there was not enough free space in the buffer, but xBytesSent bytes
+        // were sent.  Could try again to send the remaining bytes.
+    }
+}
+
    
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void *pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+
    +// A stream buffer that has already been created.
+StreamBufferHandle_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+size_t xBytesSent;
+char *pcStringToSend = "String to send";
+BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+
+    // Attempt to send the string to the stream buffer.
+    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+                                           ( void * ) pcStringToSend,
+                                           strlen( pcStringToSend ),
+                                           &xHigherPriorityTaskWoken );
+
+    if( xBytesSent != strlen( pcStringToSend ) )
+    {
+        // There was not enough free space in the stream buffer for the entire
+        // string to be written, ut xBytesSent bytes were written.
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferSendFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void *pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait );
+
    
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+
    +void vAFunction( StreamBuffer_t xStreamBuffer )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+
+    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+    // Wait in the Blocked state (so not using any CPU processing time) for a
+    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+    // available.
+    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+                                           ( void * ) ucRxData,
+                                           sizeof( ucRxData ),
+                                           xBlockTime );
+
+    if( xReceivedBytes > 0 )
+    {
+        // A ucRxData contains another xRecievedBytes bytes of data, which can
+        // be processed here....
+    }
+}
+
    
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void *pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+
    +// A stream buffer that has already been created.
+StreamBuffer_t xStreamBuffer;
+
+void vAnInterruptServiceRoutine( void )
+{
+uint8_t ucRxData[ 20 ];
+size_t xReceivedBytes;
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+
+    // Receive the next stream from the stream buffer.
+    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+                                                  ( void * ) ucRxData,
+                                                  sizeof( ucRxData ),
+                                                  &xHigherPriorityTaskWoken );
+
+    if( xReceivedBytes > 0 )
+    {
+        // ucRxData contains xReceivedBytes read from the stream buffer.
+        // Process the stream here....
+    }
+
+    // If xHigherPriorityTaskWoken was set to pdTRUE inside
+    // xStreamBufferReceiveFromISR() then a task that has a priority above the
+    // priority of the currently executing task was unblocked and a context
+    // switch should be performed to ensure the ISR returns to the unblocked
+    // task.  In most FreeRTOS ports this is done by simply passing
+    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+    // variables value, and perform the context switch if necessary.  Check the
+    // documentation for the port in use for port specific instructions.
+    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
    
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+
    
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+
    
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+
    +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+
    
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+												 size_t xTriggerLevelBytes,
+												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+													   size_t xTriggerLevelBytes,
+													   BaseType_t xIsMessageBuffer,
+													   uint8_t * const pucStreamBufferStorageArea,
+													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if defined( __cplusplus )
+}
+#endif
+
+#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..b0cc60b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h
@@ -0,0 +1,2543 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V10.3.1"
+#define tskKERNEL_VERSION_MAJOR 10
+#define tskKERNEL_VERSION_MINOR 3
+#define tskKERNEL_VERSION_BUILD 1
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock* TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid		/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	configSTACK_DEPTH_TYPE usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		StaticTask_t * const pxTaskBuffer;
+	#endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  configSTACK_DEPTH_TYPE usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );
    
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    + // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+	 configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+	 if( xHandle != NULL )
+	 {
+	 	vTaskDelete( xHandle );
+	 }
+ }
+   
    
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );
    
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+   
    +
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   
    
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
    
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    +// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   
    
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
    
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   
    +// Create an TaskParameters_t structure that defines the task to be created.
+// The StaticTask_t variable is only included in the structure when
+// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+// be used to force the variable into the RTOS kernel's privileged data area.
+static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+		{ cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+		{ cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+		{ cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+
+	&xTaskBuffer; // Holds the task's data structure.
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   
    
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *
    + void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
    
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   
    +// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   
    
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskDelete( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   
    + void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   
    
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    void vTaskDelay( const TickType_t xTicksToDelay );
    
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
    
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   
    + // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   
    
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   
    
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
    
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    eTaskState eTaskGetState( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
    
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   
    
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
    
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   
    
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskSuspend( TaskHandle_t xTaskToSuspend );
    
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   
    
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskResume( TaskHandle_t xTaskToResume );
    
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   
    
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
    
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    void vTaskStartScheduler( void );
    
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   
    + void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   
    
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskEndScheduler( void );
    
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   
    + void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   
    
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskSuspendAll( void );
    
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   
    + void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   
    
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskResumeAll( void );
    
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   
    + void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   
    
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * 
    TickType_t xTaskGetTickCount( void );
    
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    TickType_t xTaskGetTickCountFromISR( void );
    
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    uint16_t uxTaskGetNumberOfTasks( void );
    
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    char *pcTaskGetName( TaskHandle_t xTaskToQuery );
    
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
    TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
    
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * 
    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
    
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * 
    void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
    
+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
    void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
    
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
+		 * call from an interrupt service routine - call
+		 * xTaskGetApplicationTaskTagFromISR() instead.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * 
    void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
    
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.  Can
+		 * be called from an interrupt service routine.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * 
    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
    
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   
    +    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	
    
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    void vTaskList( char *pcWriteBuffer );
    
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * 
    void vTaskGetRunTimeStats( char *pcWriteBuffer );
    
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+* task. h
+* 
    uint32_t ulTaskGetIdleRunTimeCounter( void );
    
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * 
    void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
    
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * 
    BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
    
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/**
+* task. h
+* 
    uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
    
+*
+* Clears the bits specified by the ulBitsToClear bit mask in the notification
+* value of the task referenced by xTask.
+*
+* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+* the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+* notification value without clearing any bits.
+*
+* @return The value of the target task's notification value before the bits
+* specified by ulBitsToClear were cleared.
+* \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+* \ingroup TaskNotifications
+*/
+uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
    
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * 
    BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
    
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.freertos.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * 
    +	// Driver library function used to receive uxWantedBytes from an Rx buffer
+	// that is filled by a UART interrupt. If there are not enough bytes in the
+	// Rx buffer then the task enters the Blocked state until it is notified that
+	// more data has been placed into the buffer. If there is still not enough
+	// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+	// is used to re-calculate the Block time to ensure the total amount of time
+	// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+	// continues until either the buffer contains at least uxWantedBytes bytes,
+	// or the total amount of time spent in the Blocked state reaches
+	// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+	// available up to a maximum of uxWantedBytes.
+
+	size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+	{
+	size_t uxReceived = 0;
+	TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+	TimeOut_t xTimeOut;
+
+		// Initialize xTimeOut.  This records the time at which this function
+		// was entered.
+		vTaskSetTimeOutState( &xTimeOut );
+
+		// Loop until the buffer contains the wanted number of bytes, or a
+		// timeout occurs.
+		while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+		{
+			// The buffer didn't contain enough data so this task is going to
+			// enter the Blocked state. Adjusting xTicksToWait to account for
+			// any time that has been spent in the Blocked state within this
+			// function so far to ensure the total amount of time spent in the
+			// Blocked state does not exceed MAX_TIME_TO_WAIT.
+			if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+			{
+				//Timed out before the wanted number of bytes were available,
+				// exit the loop.
+				break;
+			}
+
+			// Wait for a maximum of xTicksToWait ticks to be notified that the
+			// receive interrupt has placed more data into the buffer.
+			ulTaskNotifyTake( pdTRUE, xTicksToWait );
+		}
+
+		// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+		// The actual number of bytes read (which might be less than
+		// uxWantedBytes) is returned.
+		uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+													pucBuffer,
+													uxWantedBytes );
+
+		return uxReceived;
+	}
+ 
    
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/* Correct the tick count value after the application code has held
+interrupts disabled for an extended period.  xTicksToCatchUp is the number
+of tick interrupts that have been missed due to interrupts being disabled.
+Its value is not computed automatically, so must be computed by the
+application writer.
+
+This function is similar to vTaskStepTick(), however, unlike
+vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+time at which a task should be removed from the blocked state.  That means
+tasks may have to be removed from the blocked state as the tick count is
+moved. */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..307ea1f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1309 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+*
+* Queries a timer to determine if it is an auto-reload timer, in which case the timer
+* automatically resets itself each time it expires, or a one-shot timer, in
+* which case the timer will only expire once unless it is manually restarted.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+* pdFALSE is returned.
+*/
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..7618ee8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c
@@ -0,0 +1,198 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include 
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pxContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCBs which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		https://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   https://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pxContainer = pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = pxItemToRemove->pxContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pxContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..eaf443f
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,492 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( pxNewBlockLink );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+					xNumberOfSuccessfulAllocations++;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+					xNumberOfSuccessfulFrees++;
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	uxAddress = ( size_t ) ucHeap;
+
+	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		uxAddress += ( portBYTE_ALIGNMENT - 1 );
+		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+	uxAddress -= xHeapStructSize;
+	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) uxAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t *pxHeapStats )
+{
+BlockLink_t *pxBlock;
+size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+	vTaskSuspendAll();
+	{
+		pxBlock = xStart.pxNextFreeBlock;
+
+		/* pxBlock will be NULL if the heap has not been initialised.  The heap
+		is initialised automatically when the first allocation is made. */
+		if( pxBlock != NULL )
+		{
+			do
+			{
+				/* Increment the number of blocks and record the largest block seen
+				so far. */
+				xBlocks++;
+
+				if( pxBlock->xBlockSize > xMaxSize )
+				{
+					xMaxSize = pxBlock->xBlockSize;
+				}
+
+				if( pxBlock->xBlockSize < xMinSize )
+				{
+					xMinSize = pxBlock->xBlockSize;
+				}
+
+				/* Move to the next block in the chain until the last block is
+				reached. */
+				pxBlock = pxBlock->pxNextFreeBlock;
+			} while( pxBlock != pxEnd );
+		}
+	}
+	xTaskResumeAll();
+
+	pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+	pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+	pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+	taskENTER_CRITICAL();
+	{
+		pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+		pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+		pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+		pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+	}
+	taskEXIT_CRITICAL();
+}
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
new file mode 100644
index 0000000..89a912c
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM4F port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+	#error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+r0p1 port. */
+#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_EXC_RETURN				( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if( configUSE_TICKLESS_IDLE == 1 )
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+
+	/* Offset added to account for the way the MCU uses the stack on entry/exit
+	of interrupts, and to ensure alignment. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+
+	/* Save code space by skipping register initialisation. */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+
+	/* A save method is being used that requires each task to maintain its
+	own exec return value. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_EXC_RETURN;
+
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0;
+
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	while( ulDummy == 0 )
+	{
+		/* This file calls prvTaskExitError() after the scheduler has been
+		started to remove a compiler warning about the function being defined
+		but never called.  ulDummy is used purely to quieten other warnings
+		about code appearing after this function is called - making ulDummy
+		volatile makes the compiler think the function could return and
+		therefore not output an 'unreachable code' warning for code that appears
+		after it. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the SVC stack
+	for lazy saving of FPU registers. */
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
+					" msr control, r0		\n"
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	/* This port can be used on all revisions of the Cortex-M7 core other than
+	the r0p1 parts.  r0p1 parts should use the port from the
+	/source/portable/GCC/ARM_CM7/r0p1 directory. */
+	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		#ifdef __NVIC_PRIO_BITS
+		{
+			/* Check the CMSIS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+		}
+		#endif
+
+		#ifdef configPRIO_BITS
+		{
+			/* Check the FreeRTOS configuration that defines the number of
+			priority bits matches the number of priority bits actually queried
+			from the hardware. */
+			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+		}
+		#endif
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	vPortSetupTimerInterrupt();
+
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Ensure the VFP is enabled - it should be anyway. */
+	vPortEnableVFP();
+
+	/* Lazy save always. */
+	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS.  Call
+	vTaskSwitchContext() so link time optimisation does not remove the
+	symbol. */
+	vTaskSwitchContext();
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
+	"	it eq								\n"
+	"	vstmdbeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r0, r3}					\n"
+	"	mov r0, %0 							\n"
+	"	msr basepri, r0						\n"
+	"	dsb									\n"
+	"	isb									\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r0, r3}					\n"
+	"										\n"
+	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldr r0, [r1]						\n"
+	"										\n"
+	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
+	"										\n"
+	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+	"	it eq								\n"
+	"	vldmiaeq r0!, {s16-s31}				\n"
+	"										\n"
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"										\n"
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+		#if WORKAROUND_PMU_CM001 == 1
+	"			push { r14 }				\n"
+	"			pop { pc }					\n"
+		#endif
+	#endif
+	"										\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE == 1 )
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" ::: "memory" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" ::: "memory" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Re-enable interrupts to allow the interrupt that brought the MCU
+			out of sleep mode to execute immediately.  see comments above
+			__disable_interrupt() call above. */
+			__asm volatile( "cpsie i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable interrupts again because the clock is about to be stopped
+			and interrupts that execute while the clock is stopped will increase
+			any slippage between the time maintained by the RTOS and calendar
+			time. */
+			__asm volatile( "cpsid i" ::: "memory" );
+			__asm volatile( "dsb" );
+			__asm volatile( "isb" );
+
+			/* Disable the SysTick clock without reading the
+			portNVIC_SYSTICK_CTRL_REG register to ensure the
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+			the time the SysTick is stopped for is accounted for as best it can
+			be, but using the tickless mode will inevitably result in some tiny
+			drift of the time maintained by the kernel with respect to calendar
+			time*/
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt is already pending, and the SysTick count
+				reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* As the pending tick will be processed as soon as this
+				function exits, the tick value maintained by the tick is stepped
+				forward by one less than the time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+			vTaskStepTick( ulCompleteTickPeriods );
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Exit with interrupts enabled. */
+			__asm volatile( "cpsie i" ::: "memory" );
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if( configUSE_TICKLESS_IDLE == 1 )
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Stop and clear the SysTick. */
+	portNVIC_SYSTICK_CTRL_REG = 0UL;
+	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+	__asm volatile
+	(
+		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
+		"	ldr r1, [r0]				\n"
+		"								\n"
+		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
+		"	str r1, [r0]				\n"
+		"	bx r14						"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredictable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..d0a566a
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -0,0 +1,243 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" ::: "memory" );										\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
+	);
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..b3203b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c
@@ -0,0 +1,2945 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+structure instead holds a pointer to the mutex holder (if any).  Map alternative
+names to the pcHead and structure member to ensure the readability of the code
+is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+a union as their usage is mutually exclusive dependent on what the queue is
+being used for. */
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+typedef struct QueuePointers
+{
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
+	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union
+	{
+		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
+		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if( configUSE_MUTEXES == 1 )
+	/*
+	 * If a task waiting for a mutex causes the mutex holder to inherit a
+	 * priority, but the waiting task times out, then the holder should
+	 * disinherit the priority - but only down to the highest priority of any
+	 * other tasks that are waiting for the same mutex.  This function returns
+	 * that priority.
+	 */
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* Allocate enough space to hold the maximum number of items that
+		can be in the queue at any time.  It is valid for uxItemSize to be
+		zero in the case the queue is used as a semaphore. */
+		xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+		/* Allocate the queue and storage area.  Justification for MISRA
+		deviation as follows:  pvPortMalloc() always ensures returned memory
+		blocks are aligned per the requirements of the MCU stack.  In this case
+		pvPortMalloc() must return a pointer that is guaranteed to meet the
+		alignment requirements of the Queue_t structure - which in this case
+		is an int8_t *.  Therefore, whenever the stack alignment requirements
+		are greater than or equal to the pointer to char requirements the cast
+		is safe.  In other cases alignment requirements are not strict (one or
+		two bytes). */
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( uint8_t * ) pxNewQueue;
+			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+		else
+		{
+			traceQUEUE_CREATE_FAILED( ucQueueType );
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+		return xNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+	{
+	TaskHandle_t pxReturn;
+
+		configASSERT( xSemaphore );
+
+		/* Mutexes cannot be used in interrupt service routines, so the mutex
+		holder should not change in an ISR, and therefore a critical section is
+		not required here. */
+		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+		{
+			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+		}
+		else
+		{
+			pxReturn = NULL;
+		}
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then xMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+		{
+			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+				const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible that interrupts occurring now
+				remove this task from the event list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+						{
+							/* Do not notify the queue set as an existing item
+							was overwritten in the queue so the number of items
+							in the queue has not changed. */
+							mtCOVERAGE_TEST_MARKER();
+						}
+						else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					
+					/* Not used in this path. */
+					( void ) uxPreviousMessagesWaiting;
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data available, remove one item. */
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_RECEIVE( pxQueue );
+				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+				/* There is now space in the queue, were any tasks waiting to
+				post to the queue?  If so, unblock the highest priority waiting
+				task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* The timeout has not expired.  If the queue is still empty place
+			the task on the list of tasks waiting to receive from the queue. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The queue contains data again.  Loop back to try and read the
+				data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out.  If there is no data in the queue exit, otherwise loop
+			back and attempt to read the data. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = xQueue;
+
+#if( configUSE_MUTEXES == 1 )
+	BaseType_t xInheritanceOccurred = pdFALSE;
+#endif
+
+	/* Check the queue pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* Check this really is a semaphore, in which case the item size will be
+	0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Semaphores are queues with an item size of 0, and where the
+			number of messages in the queue is the semaphore's count value. */
+			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+			{
+				traceQUEUE_RECEIVE( pxQueue );
+
+				/* Semaphores are queues with a data size of zero and where the
+				messages waiting is the semaphore's count.  Reduce the count. */
+				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						/* Record the information required to implement
+						priority inheritance should it become necessary. */
+						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				/* Check to see if other tasks are blocked waiting to give the
+				semaphore, and if so, unblock the highest priority such task. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* For inheritance to have occurred there must have been an
+					initial timeout, and an adjusted timeout cannot become 0, as
+					if it were 0 the function would have exited. */
+					#if( configUSE_MUTEXES == 1 )
+					{
+						configASSERT( xInheritanceOccurred == pdFALSE );
+					}
+					#endif /* configUSE_MUTEXES */
+
+					/* The semaphore count was 0 and no block time is specified
+					(or the block time has expired) so exit now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The semaphore count was 0 and a block time was specified
+					so configure the timeout structure ready to block. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can give to and take from the semaphore
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* A block time is specified and not expired.  If the semaphore
+			count is 0 then enter the Blocked state to wait for a semaphore to
+			become available.  As semaphores are implemented with queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There was no timeout and the semaphore count was not 0, so
+				attempt to take the semaphore again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* Timed out. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			/* If the semaphore count is 0 exit now as the timeout has
+			expired.  Otherwise return to attempt to take the semaphore that is
+			known to be available.  As semaphores are implemented by queues the
+			queue being empty is equivalent to the semaphore count being 0. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* xInheritanceOccurred could only have be set if
+					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+					test the mutex type again to check it is actually a mutex. */
+					if( xInheritanceOccurred != pdFALSE )
+					{
+						taskENTER_CRITICAL();
+						{
+							UBaseType_t uxHighestWaitingPriority;
+
+							/* This task blocking on the mutex caused another
+							task to inherit this task's priority.  Now this task
+							has timed out the priority should be disinherited
+							again, but only as low as the next highest priority
+							task that is waiting for the same mutex. */
+							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+						}
+						taskEXIT_CRITICAL();
+					}
+				}
+				#endif /* configUSE_MUTEXES */
+
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	/* Check the pointer is not NULL. */
+	configASSERT( ( pxQueue ) );
+
+	/* The buffer into which data is received can only be NULL if the data size
+	is zero (so no data is copied into the buffer. */
+	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* Cannot block if the scheduler is suspended. */
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/*lint -save -e904  This function relaxes the coding standard somewhat to
+	allow return statements within the function itself.  This is done in the
+	interest of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position so it can be reset after the data
+				is read from the queue as this function is only peeking the
+				data, not removing it. */
+				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+				traceQUEUE_PEEK( pxQueue );
+
+				/* The data is not being removed, so reset the read pointer. */
+				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+				/* The data is being left in the queue, so see if there are
+				any other tasks waiting for the data. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than this task. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_PEEK_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure ready to enter the blocked
+					state. */
+					vTaskInternalSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			/* Timeout has not expired yet, check to see if there is data in the
+			queue now, and if not enter the Blocked state to wait for data. */
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* There is data in the queue now, so don't enter the blocked
+				state, instead return to try and obtain the data. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired.  If there is still no data in the queue
+			exit, otherwise go back and try to read the data again. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_PEEK_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	} /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	uxReturn = pxQueue->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+	{
+	UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+		/* If a task waiting for a mutex causes the mutex holder to inherit a
+		priority, but the waiting task times out, then the holder should
+		disinherit the priority - but only down to the highest priority of any
+		other tasks that are waiting for the same mutex.  For this purpose,
+		return the priority of the highest priority task that is waiting for the
+		mutex. */
+		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+		{
+			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+		else
+		{
+			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+		}
+
+		return uxHighestPriorityOfWaitingTasks;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+				pxQueue->u.xSemaphore.xMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+Queue_t * const pxQueue = xQueue;
+
+	configASSERT( pxQueue );
+	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+				{
+					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+			{
+				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..7ad5d54
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1263 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if( configUSE_TASK_NOTIFICATIONS != 1 )
+	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+or #defined the notification macros away, them provide default implementations
+that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
+#ifndef sbRECEIVE_COMPLETED
+	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
+										  pxHigherPriorityTaskWoken )					\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+or #defined the notification macro away, them provide a default implementation
+that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+	#define sbSEND_COMPLETED( pxStreamBuffer )											\
+		vTaskSuspendAll();																\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
+									  ( uint32_t ) 0,									\
+									  eNoAction );										\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
+	{																					\
+	UBaseType_t uxSavedInterruptStatus;													\
+																						\
+		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
+		{																				\
+			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
+			{																			\
+				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
+											 ( uint32_t ) 0,							\
+											 eNoAction,									\
+											 pxHigherPriorityTaskWoken );				\
+				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
+			}																			\
+		}																				\
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
+	}
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
+{
+	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
+	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
+	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
+	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
+	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+	uint8_t ucFlags;
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
+	#endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
+										const void * pvTxData,
+										size_t xDataLengthBytes,
+										size_t xSpace,
+										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
+									  uint8_t *pucData,
+									  size_t xMaxCount,
+									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
+	{
+	uint8_t *pucAllocatedMemory;
+	uint8_t ucFlags;
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		if( xIsMessageBuffer == pdTRUE )
+		{
+			/* Is a message buffer but not statically allocated. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+		}
+		else
+		{
+			/* Not a message buffer and not statically allocated. */
+			ucFlags = 0;
+			configASSERT( xBufferSizeBytes > 0 );
+		}
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
+		Both are allocated in a single call to pvPortMalloc().  The
+		StreamBuffer_t structure is placed at the start of the allocated memory
+		and the buffer follows immediately after.  The requested size is
+		incremented so the free space is returned as the user would expect -
+		this is a quirk of the implementation that means otherwise the free
+		space would be reported as one byte smaller than would be logically
+		expected. */
+		xBufferSizeBytes++;
+		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+
+		if( pucAllocatedMemory != NULL )
+		{
+			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+										   xBufferSizeBytes,
+										   xTriggerLevelBytes,
+										   ucFlags );
+
+			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+		}
+		else
+		{
+			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+		}
+
+		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+														   size_t xTriggerLevelBytes,
+														   BaseType_t xIsMessageBuffer,
+														   uint8_t * const pucStreamBufferStorageArea,
+														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
+	{
+	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+	StreamBufferHandle_t xReturn;
+	uint8_t ucFlags;
+
+		configASSERT( pucStreamBufferStorageArea );
+		configASSERT( pxStaticStreamBuffer );
+		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+		/* A trigger level of 0 would cause a waiting task to unblock even when
+		the buffer was empty. */
+		if( xTriggerLevelBytes == ( size_t ) 0 )
+		{
+			xTriggerLevelBytes = ( size_t ) 1;
+		}
+
+		if( xIsMessageBuffer != pdFALSE )
+		{
+			/* Statically allocated message buffer. */
+			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+		else
+		{
+			/* Statically allocated stream buffer. */
+			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+		}
+
+		/* In case the stream buffer is going to be used as a message buffer
+		(that is, it will hold discrete messages with a little meta data that
+		says how big the next message is) check the buffer will be large enough
+		to hold at least one message. */
+		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticStreamBuffer_t equals the size of the real
+			message buffer structure. */
+			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+			configASSERT( xSize == sizeof( StreamBuffer_t ) );
+		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
+		#endif /* configASSERT_DEFINED */
+
+		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+		{
+			prvInitialiseNewStreamBuffer( pxStreamBuffer,
+										  pucStreamBufferStorageArea,
+										  xBufferSizeBytes,
+										  xTriggerLevelBytes,
+										  ucFlags );
+
+			/* Remember this was statically allocated in case it is ever deleted
+			again. */
+			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+		}
+		else
+		{
+			xReturn = NULL;
+			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+	{
+		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+		{
+			/* Both the structure and the buffer were allocated using a single call
+			to pvPortMalloc(), hence only one call to vPortFree() is required. */
+			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+		}
+		#else
+		{
+			/* Should not be possible to get here, ucFlags must be corrupt.
+			Force an assert. */
+			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+		}
+		#endif
+	}
+	else
+	{
+		/* The structure and buffer were not allocated dynamically and cannot be
+		freed - just scrub the structure so future use will assert. */
+		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn = pdFAIL;
+
+#if( configUSE_TRACE_FACILITY == 1 )
+	UBaseType_t uxStreamBufferNumber;
+#endif
+
+	configASSERT( pxStreamBuffer );
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+	{
+		/* Store the stream buffer number so it can be restored after the
+		reset. */
+		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+	}
+	#endif
+
+	/* Can only reset a message buffer if there are no tasks blocked on it. */
+	taskENTER_CRITICAL();
+	{
+		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+		{
+			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+			{
+				prvInitialiseNewStreamBuffer( pxStreamBuffer,
+											  pxStreamBuffer->pucBuffer,
+											  pxStreamBuffer->xLength,
+											  pxStreamBuffer->xTriggerLevelBytes,
+											  pxStreamBuffer->ucFlags );
+				xReturn = pdPASS;
+
+				#if( configUSE_TRACE_FACILITY == 1 )
+				{
+					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+				}
+				#endif
+
+				traceSTREAM_BUFFER_RESET( xStreamBuffer );
+			}
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* It is not valid for the trigger level to be 0. */
+	if( xTriggerLevel == ( size_t ) 0 )
+	{
+		xTriggerLevel = ( size_t ) 1;
+	}
+
+	/* The trigger level is the number of bytes that must be in the stream
+	buffer before a task that is waiting for data is unblocked. */
+	if( xTriggerLevel <= pxStreamBuffer->xLength )
+	{
+		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xSpace;
+
+	configASSERT( pxStreamBuffer );
+
+	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+	xSpace -= pxStreamBuffer->xHead;
+	xSpace -= ( size_t ) 1;
+
+	if( xSpace >= pxStreamBuffer->xLength )
+	{
+		xSpace -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	xReturn = prvBytesInBuffer( pxStreamBuffer );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+						  const void *pvTxData,
+						  size_t xDataLengthBytes,
+						  TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace = 0;
+size_t xRequiredSpace = xDataLengthBytes;
+TimeOut_t xTimeOut;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+		/* Overflow? */
+		configASSERT( xRequiredSpace > xDataLengthBytes );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		vTaskSetTimeOutState( &xTimeOut );
+
+		do
+		{
+			/* Wait until the required number of bytes are free in the message
+			buffer. */
+			taskENTER_CRITICAL();
+			{
+				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+				if( xSpace < xRequiredSpace )
+				{
+					/* Clear notification state as going to wait for space. */
+					( void ) xTaskNotifyStateClear( NULL );
+
+					/* Should only be one writer. */
+					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+				}
+				else
+				{
+					taskEXIT_CRITICAL();
+					break;
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToSend = NULL;
+
+		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+								 const void *pvTxData,
+								 size_t xDataLengthBytes,
+								 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xSpace;
+size_t xRequiredSpace = xDataLengthBytes;
+
+	configASSERT( pvTxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This send function is used to write to both message buffers and stream
+	buffers.  If this is a message buffer then the space needed must be
+	increased by the amount of bytes needed to store the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+	if( xReturn > ( size_t ) 0 )
+	{
+		/* Was a task waiting for the data? */
+		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+		{
+			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+									   const void * pvTxData,
+									   size_t xDataLengthBytes,
+									   size_t xSpace,
+									   size_t xRequiredSpace )
+{
+	BaseType_t xShouldWrite;
+	size_t xReturn;
+
+	if( xSpace == ( size_t ) 0 )
+	{
+		/* Doesn't matter if this is a stream buffer or a message buffer, there
+		is no space to write. */
+		xShouldWrite = pdFALSE;
+	}
+	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+	{
+		/* This is a stream buffer, as opposed to a message buffer, so writing a
+		stream of bytes rather than discrete messages.  Write as many bytes as
+		possible. */
+		xShouldWrite = pdTRUE;
+		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+	}
+	else if( xSpace >= xRequiredSpace )
+	{
+		/* This is a message buffer, as opposed to a stream buffer, and there
+		is enough space to write both the message length and the message itself
+		into the buffer.  Start by writing the length of the data, the data
+		itself will be written later in this function. */
+		xShouldWrite = pdTRUE;
+		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+	}
+	else
+	{
+		/* There is space available, but not enough space. */
+		xShouldWrite = pdFALSE;
+	}
+
+	if( xShouldWrite != pdFALSE )
+	{
+		/* Writes the data itself. */
+		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+							 void *pvRxData,
+							 size_t xBufferLengthBytes,
+							 TickType_t xTicksToWait )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		/* Checking if there is data and clearing the notification state must be
+		performed atomically. */
+		taskENTER_CRITICAL();
+		{
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+			/* If this function was invoked by a message buffer read then
+			xBytesToStoreMessageLength holds the number of bytes used to hold
+			the length of the next discrete message.  If this function was
+			invoked by a stream buffer read then xBytesToStoreMessageLength will
+			be 0. */
+			if( xBytesAvailable <= xBytesToStoreMessageLength )
+			{
+				/* Clear notification state as going to wait for data. */
+				( void ) xTaskNotifyStateClear( NULL );
+
+				/* Should only be one reader. */
+				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		if( xBytesAvailable <= xBytesToStoreMessageLength )
+		{
+			/* Wait for data to be available. */
+			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+			pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+			/* Recheck the data available after blocking. */
+			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+	}
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+			sbRECEIVE_COMPLETED( pxStreamBuffer );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReturn, xBytesAvailable, xOriginalTail;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+	configASSERT( pxStreamBuffer );
+
+	/* Ensure the stream buffer is being used as a message buffer. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+		{
+			/* The number of bytes available is greater than the number of bytes
+			required to hold the length of the next message, so another message
+			is available.  Return its length without removing the length bytes
+			from the buffer.  A copy of the tail is stored so the buffer can be
+			returned to its prior state as the message is not actually being
+			removed from the buffer. */
+			xOriginalTail = pxStreamBuffer->xTail;
+			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+			xReturn = ( size_t ) xTempReturn;
+			pxStreamBuffer->xTail = xOriginalTail;
+		}
+		else
+		{
+			/* The minimum amount of bytes in a message buffer is
+			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+			value is 0. */
+			configASSERT( xBytesAvailable == 0 );
+			xReturn = 0;
+		}
+	}
+	else
+	{
+		xReturn = 0;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+									void *pvRxData,
+									size_t xBufferLengthBytes,
+									BaseType_t * const pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+	configASSERT( pvRxData );
+	configASSERT( pxStreamBuffer );
+
+	/* This receive function is used by both message buffers, which store
+	discrete messages, and stream buffers, which store a continuous stream of
+	bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+	message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
+	holds the number of bytes used to store the message length) or a stream of
+	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+	available must be greater than xBytesToStoreMessageLength to be able to
+	read bytes from the buffer. */
+	if( xBytesAvailable > xBytesToStoreMessageLength )
+	{
+		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+		/* Was a task waiting for space in the buffer? */
+		if( xReceivedLength != ( size_t ) 0 )
+		{
+			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
+										void *pvRxData,
+										size_t xBufferLengthBytes,
+										size_t xBytesAvailable,
+										size_t xBytesToStoreMessageLength )
+{
+size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+	if( xBytesToStoreMessageLength != ( size_t ) 0 )
+	{
+		/* A discrete message is being received.  First receive the length
+		of the message.  A copy of the tail is stored so the buffer can be
+		returned to its prior state if the length of the message is too
+		large for the provided buffer. */
+		xOriginalTail = pxStreamBuffer->xTail;
+		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+		xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+		/* Reduce the number of bytes available by the number of bytes just
+		read out. */
+		xBytesAvailable -= xBytesToStoreMessageLength;
+
+		/* Check there is enough space in the buffer provided by the
+		user. */
+		if( xNextMessageLength > xBufferLengthBytes )
+		{
+			/* The user has provided insufficient space to read the message
+			so return the buffer to its previous state (so the length of
+			the message is in the buffer again). */
+			pxStreamBuffer->xTail = xOriginalTail;
+			xNextMessageLength = 0;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* A stream of bytes is being received (as opposed to a discrete
+		message), so read as many bytes as possible. */
+		xNextMessageLength = xBufferLengthBytes;
+	}
+
+	/* Read the actual data. */
+	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+	return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+size_t xTail;
+
+	configASSERT( pxStreamBuffer );
+
+	/* True if no bytes are available. */
+	xTail = pxStreamBuffer->xTail;
+	if( pxStreamBuffer->xHead == xTail )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+BaseType_t xReturn;
+size_t xBytesToStoreMessageLength;
+const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+	configASSERT( pxStreamBuffer );
+
+	/* This generic version of the receive function is used by both message
+	buffers, which store discrete messages, and stream buffers, which store a
+	continuous stream of bytes.  Discrete messages include an additional
+	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+	{
+		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+	}
+	else
+	{
+		xBytesToStoreMessageLength = 0;
+	}
+
+	/* True if the available space equals zero. */
+	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
+{
+StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	configASSERT( pxStreamBuffer );
+
+	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+		{
+			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+										 ( uint32_t ) 0,
+										 eNoAction,
+										 pxHigherPriorityTaskWoken );
+			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
+{
+size_t xNextHead, xFirstLength;
+
+	configASSERT( xCount > ( size_t ) 0 );
+
+	xNextHead = pxStreamBuffer->xHead;
+
+	/* Calculate the number of bytes that can be added in the first write -
+	which may be less than the total number of bytes that need to be added if
+	the buffer will wrap back to the beginning. */
+	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+	/* Write as many bytes as can be written in the first write. */
+	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+	/* If the number of bytes written was less than the number that could be
+	written in the first write... */
+	if( xCount > xFirstLength )
+	{
+		/* ...then write the remaining bytes to the start of the buffer. */
+		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	xNextHead += xCount;
+	if( xNextHead >= pxStreamBuffer->xLength )
+	{
+		xNextHead -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxStreamBuffer->xHead = xNextHead;
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
+{
+size_t xCount, xFirstLength, xNextTail;
+
+	/* Use the minimum of the wanted bytes and the available bytes. */
+	xCount = configMIN( xBytesAvailable, xMaxCount );
+
+	if( xCount > ( size_t ) 0 )
+	{
+		xNextTail = pxStreamBuffer->xTail;
+
+		/* Calculate the number of bytes that can be read - which may be
+		less than the number wanted if the data wraps around to the start of
+		the buffer. */
+		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+		/* Obtain the number of bytes it is possible to obtain in the first
+		read.  Asserts check bounds of read and write. */
+		configASSERT( xFirstLength <= xMaxCount );
+		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+		/* If the total number of wanted bytes is greater than the number
+		that could be read in the first read... */
+		if( xCount > xFirstLength )
+		{
+			/*...then read the remaining bytes from the start of the buffer. */
+			configASSERT( xCount <= xMaxCount );
+			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Move the tail pointer to effectively remove the data read from
+		the buffer. */
+		xNextTail += xCount;
+
+		if( xNextTail >= pxStreamBuffer->xLength )
+		{
+			xNextTail -= pxStreamBuffer->xLength;
+		}
+
+		pxStreamBuffer->xTail = xNextTail;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+size_t xCount;
+
+	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+	xCount -= pxStreamBuffer->xTail;
+	if ( xCount >= pxStreamBuffer->xLength )
+	{
+		xCount -= pxStreamBuffer->xLength;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+										  uint8_t * const pucBuffer,
+										  size_t xBufferSizeBytes,
+										  size_t xTriggerLevelBytes,
+										  uint8_t ucFlags )
+{
+	/* Assert here is deliberately writing to the entire buffer to ensure it can
+	be written to without generating exceptions, and is setting the buffer to a
+	known value to assist in development/debugging. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		/* The value written just has to be identifiable when looking at the
+		memory.  Don't use 0xA5 as that is the stack fill value and could
+		result in confusion as to what is actually being observed. */
+		const BaseType_t xWriteValue = 0x55;
+		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+	#endif
+
+	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+	pxStreamBuffer->pucBuffer = pucBuffer;
+	pxStreamBuffer->xLength = xBufferSizeBytes;
+	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+	pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+	{
+		return xStreamBuffer->uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
+	{
+		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+	{
+		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..f6a6a9b
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5310 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include 
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+value so the high water mark can be determined.  If none of the following are
+set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
+#else
+	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR		( 'X' )
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+	#define configIDLE_TASK_NAME "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks.
+
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments in FreeRTOS.h with the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+	#if( configUSE_POSIX_ERRNO == 1 )
+		int iTaskErrno;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+doing so breaks some kernel aware debuggers and debuggers that rely on removing
+the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+	int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks 			= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	/* Do not move these variables to function scope as doing so prevents the
+	code working with debuggers that need to remove the static qualifier. */
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+
+	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer )
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTask_t equals the size of the real task
+			structure. */
+			volatile size_t xSize = sizeof( StaticTask_t );
+			configASSERT( xSize == sizeof( TCB_t ) );
+			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+			/* Store the stack location in the TCB. */
+			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+									pxTaskDefinition->pcName,
+									( uint32_t ) pxTaskDefinition->usStackDepth,
+									pxTaskDefinition->pvParameters,
+									pxTaskDefinition->uxPriority,
+									pxCreatedTask, pxNewTCB,
+									pxTaskDefinition->xRegions );
+
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+				{
+					/* Tasks can be created statically or dynamically, so note
+					this task had a statically allocated stack in case it is
+					later deleted.  The TCB was allocated dynamically. */
+					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+				}
+				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+							const configSTACK_DEPTH_TYPE usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions )
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
+		{
+			/* Also record the stack's high address, which may assist
+			debugging. */
+			pxNewTCB->pxEndOfStack = pxTopOfStack;
+		}
+		#endif /* configRECORD_STACK_HIGH_ADDRESS */
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	if( pcName != NULL )
+	{
+		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+		{
+			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+			configMAX_TASK_NAME_LEN characters just in case the memory after the
+			string is not accessible (extremely unlikely). */
+			if( pcName[ x ] == ( char ) 0x00 )
+			{
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Ensure the name string is terminated in the case that the string length
+		was greater or equal to configMAX_TASK_NAME_LEN. */
+		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+	}
+	else
+	{
+		/* The task has not been given a name, so just ensure there is a NULL
+		terminator when it is read out. */
+		pxNewTCB->pcTaskName[ 0 ] = 0x00;
+	}
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		/* If the port has capability to detect stack overflow,
+		pass the stack end address to the stack initialization
+		function as well. */
+		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+		{
+			#if( portSTACK_GROWTH < 0 )
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+			}
+			#else /* portSTACK_GROWTH */
+			{
+				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+			}
+			#endif /* portSTACK_GROWTH */
+		}
+		#else /* portHAS_STACK_OVERFLOW_CHECKING */
+		{
+			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+		}
+		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready/delayed list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+				portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+				traceTASK_DELETE( pxTCB );
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				traceTASK_DELETE( pxTCB );
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
+	const TCB_t * const pxTCB = xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+				pxDelayedList = pxDelayedTaskList;
+				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it blocked
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						#if( configUSE_TASK_NOTIFICATIONS == 1 )
+						{
+							/* The task does not appear on the event list item of
+							and of the RTOS objects, but could still be in the
+							blocked state if it is waiting on its notification
+							rather than waiting on an object. */
+							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+							{
+								eReturn = eBlocked;
+							}
+							else
+							{
+								eReturn = eSuspended;
+							}
+						}
+						#else
+						{
+							eReturn = eSuspended;
+						}
+						#endif
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the task
+			that called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+	{
+	TCB_t const *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change its priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before
+					adding it to it's new ready list.  As we are in a critical
+					section we can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+			#if( configUSE_TASK_NOTIFICATIONS == 1 )
+			{
+				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+				{
+					/* The task was blocked to wait for a notification, but is
+					now suspended, so no notification was received. */
+					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				}
+			}
+			#endif
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* The ready list can be accessed even if the scheduler is
+					suspended because this is inside a critical section. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A higher priority task may have just been resumed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												configIDLE_TASK_NAME,
+												ulIdleTaskStackSize,
+												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
+												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								configIDLE_TASK_NAME,
+								configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* freertos_tasks_c_additions_init() should only be called if the user
+		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+		the only macro called by the function. */
+		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		{
+			freertos_tasks_c_additions_init();
+		}
+		#endif
+
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+		is set to 0 and the following line fails to build then ensure you do not
+		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+		FreeRTOSConfig.h file. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		traceTASK_SWITCHED_IN();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+
+	/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+	do not otherwise exhibit real time behaviour. */
+	portSOFTWARE_BARRIER();
+
+	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+	is used to allow calls to vTaskSuspendAll() to nest. */
+	++uxSchedulerSuspended;
+
+	/* Enforces ordering for ports and optimised compilers that may otherwise place
+	the above increment elsewhere. */
+	portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+					if( xPendedCounts > ( TickType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--xPendedCounts;
+						} while( xPendedCounts > ( TickType_t ) 0U );
+
+						xPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+	BaseType_t xBreakLoop;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				xBreakLoop = pdFALSE;
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						xBreakLoop = pdTRUE;
+					}
+					else if( cNextChar == ( char ) 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						xBreakLoop = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					if( xBreakLoop != pdFALSE )
+					{
+						break;
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+BaseType_t xYieldRequired = pdFALSE;
+
+	/* Must not be called with the scheduler suspended as the implementation
+	relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+	configASSERT( uxSchedulerSuspended == 0 );
+
+	/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+	the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+	vTaskSuspendAll();
+	xPendedTicks += xTicksToCatchUp;
+	xYieldRequired = xTaskResumeAll();
+
+	return xYieldRequired;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = xTask;
+	BaseType_t xReturn;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				xReturn = pdPASS;
+
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+						/* This lets the task know it was forcibly removed from the
+						blocked state so it should not re-evaluate its block time and
+						then block again. */
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( xPendedTicks == ( TickType_t ) 0 )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+
+		#if ( configUSE_PREEMPTION == 1 )
+		{
+			if( xYieldPending != pdFALSE )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_PREEMPTION */
+	}
+	else
+	{
+		++xPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xTCB->pxTaskTag = pxHookFunction;
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	TaskHookFunction_t xReturn;
+	UBaseType_t uxSavedInterruptStatus;
+
+		/* If xTask is NULL then set the calling task's hook. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			xReturn = pxTCB->pxTaskTag;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+			#else
+				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+			#endif
+
+			/* Add the amount of time the task has been running to the
+			accumulated time so far.  The time the task started running was
+			stored in ulTaskSwitchedInTime.  Note that there is no overflow
+			protection here so count values are only valid until the timer
+			overflows.  The guard against negative values is to protect
+			against suspect run time stat counter implementations - which
+			are provided by the application, not the kernel. */
+			if( ulTotalRunTime > ulTaskSwitchedInTime )
+			{
+				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Before the currently running task is switched out, save its errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+		}
+		#endif
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		traceTASK_SWITCHED_IN();
+
+		/* After the new task is switched in, update the global errno. */
+		#if( configUSE_POSIX_ERRNO == 1 )
+		{
+			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+		}
+		#endif
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task.
+			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+			for additional information. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+
+		#if( configUSE_TICKLESS_IDLE != 0 )
+		{
+			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+			might be set to the blocked task's time out time.  If the task is
+			unblocked for a reason other than a timeout xNextTaskUnblockTime is
+			normally left unchanged, because it is automatically reset to a new
+			value when the tick count equals xNextTaskUnblockTime.  However if
+			tickless idling is used it might be more important to enter sleep mode
+			at the earliest possible time - so reset xNextTaskUnblockTime here to
+			ensure it is updated at the earliest possible time. */
+			prvResetNextTaskUnblockTime();
+		}
+		#endif
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* The unblocked task has a priority above that of the calling task, so
+		a context switch is required.  This function is called with the
+		scheduler suspended so xYieldPending is set so the context switch
+		occurs immediately that the scheduler is resumed (unsuspended). */
+		xYieldPending = pdTRUE;
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	taskENTER_CRITICAL();
+	{
+		pxTimeOut->xOverflowCount = xNumOfOverflows;
+		pxTimeOut->xTimeOnEntering = xTickCount;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	/* For internal use only as it does not use a critical section. */
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= xElapsedTime;
+			vTaskInternalSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			*pxTicksToWait = 0;
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t const *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t * pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	/* In case a task that has a secure context deletes itself, in which case
+	the idle task is responsible for deleting the task's secure context, if
+	any. */
+	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					/* Define the following macro to set xExpectedIdleTime to 0
+					if the application does not want
+					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		/* This function must be called from a critical section. */
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			configASSERT( pxTCB != NULL );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		TCB_t *pxTCB;
+
+		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+		being called too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			taskENTER_CRITICAL();
+			{
+				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				--uxCurrentNumberOfTasks;
+				--uxDeletedTasksWaitingCleanUp;
+			}
+			taskEXIT_CRITICAL();
+
+			prvDeleteTCB( pxTCB );
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the
+		value of eState passed into this function is eInvalid - otherwise the
+		state is just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				pxTaskStatus->eCurrentState = eRunning;
+			}
+			else
+			{
+				pxTaskStatus->eCurrentState = eState;
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* If the task is in the suspended list then there is a
+					chance it is actually just blocked indefinitely - so really
+					it should be reported as being in the Blocked state. */
+					if( eState == eSuspended )
+					{
+						vTaskSuspendAll();
+						{
+							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+							{
+								pxTaskStatus->eCurrentState = eBlocked;
+							}
+						}
+						( void ) xTaskResumeAll();
+					}
+				}
+				#endif /* INCLUDE_vTaskSuspend */
+			}
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( configSTACK_DEPTH_TYPE ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+	user to determine the return type.  It gets around the problem of the value
+	overflowing on 8-bit types without breaking backward compatibility for
+	applications that expect an 8-bit return type. */
+	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	configSTACK_DEPTH_TYPE uxReturn;
+
+		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+		the same except for their return type.  Using configSTACK_DEPTH_TYPE
+		allows the user to determine the return type.  It gets around the
+		problem of the value overflowing on 8-bit types without breaking
+		backward compatibility for applications that expect an 8-bit return
+		type. */
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level.
+		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+		for additional information. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL.  _RB_ Is this still
+		needed as interrupts can no longer use mutexes? */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxMutexHolderTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+				/* Inheritance occurred. */
+				xReturn = pdTRUE;
+			}
+			else
+			{
+				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+				{
+					/* The base priority of the mutex holder is lower than the
+					priority of the task attempting to take the mutex, but the
+					current priority of the mutex holder is not lower than the
+					priority of the task attempting to take the mutex.
+					Therefore the mutex holder must have already inherited a
+					priority, but inheritance would have occurred if that had
+					not been the case. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding task then it must be the running state task.  Remove
+					the holding task from the ready/delayed list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
+	{
+	TCB_t * const pxTCB = pxMutexHolder;
+	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* If pxMutexHolder is not NULL then the holder must hold at least
+			one mutex. */
+			configASSERT( pxTCB->uxMutexesHeld );
+
+			/* Determine the priority to which the priority of the task that
+			holds the mutex should be set.  This will be the greater of the
+			holding task's base priority and the priority of the highest
+			priority task that is waiting to obtain the mutex. */
+			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+			{
+				uxPriorityToUse = uxHighestPriorityWaitingTask;
+			}
+			else
+			{
+				uxPriorityToUse = pxTCB->uxBasePriority;
+			}
+
+			/* Does the priority need to change? */
+			if( pxTCB->uxPriority != uxPriorityToUse )
+			{
+				/* Only disinherit if no other mutexes are held.  This is a
+				simplification in the priority inheritance implementation.  If
+				the task that holds the mutex is also holding other mutexes then
+				the other mutexes may have caused the priority inheritance. */
+				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+				{
+					/* If a task has timed out because it already holds the
+					mutex it was trying to obtain then it cannot of inherited
+					its own priority. */
+					configASSERT( pxTCB != pxCurrentTCB );
+
+					/* Disinherit the priority, remembering the previous
+					priority to facilitate determining the subject task's
+					state. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					uxPriorityUsedOnEntry = pxTCB->uxPriority;
+					pxTCB->uxPriority = uxPriorityToUse;
+
+					/* Only reset the event list item value if the value is not
+					being used for anything else. */
+					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+					{
+						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* If the running task is not the task that holds the mutex
+					then the task that holds the mutex could be in either the
+					Ready, Blocked or Suspended states.  Only remove the task
+					from its current state list if it is in the Ready state as
+					the task's priority is going to change and there is one
+					Ready list per priority. */
+					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+					{
+						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+						{
+							/* It is known that the task is in its ready list so
+							there is no need to check again and the port level
+							reset macro can be called directly. */
+							portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+
+						prvAddTaskToReadyList( pxTCB );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = ( char ) 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eRunning:		cStatus = tskRUNNING_CHAR;
+										break;
+
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					case eInvalid:		/* Fall through. */
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = ( char ) 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = ( char ) 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0UL )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+
+				default:
+					/* Should not get here if all enums are handled.
+					Artificially force an assert by testing a value the
+					compiler can't assume is const. */
+					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter to an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+
+					/* Mark that a yield is pending in case the user is not
+					using the "xHigherPriorityTaskWoken" parameter in an ISR
+					safe FreeRTOS function. */
+					xYieldPending = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )
+	{
+	TCB_t *pxTCB;
+	uint32_t ulReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			/* Return the notification as it was before the bits were cleared,
+			then clear the bit mask. */
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+			pxTCB->ulNotifiedValue &= ~ulBitsToClear;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+	uint32_t ulTaskGetIdleRunTimeCounter( void )
+	{
+		return xIdleTaskHandle->ulRunTimeCounter;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+especially where access to file scope functions and data is needed (for example
+when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
+
+#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+	#include "freertos_tasks_c_additions.h"
+
+	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+		static void freertos_tasks_c_additions_init( void )
+		{
+			FREERTOS_TASKS_C_ADDITIONS_INIT();
+		}
+	#endif
+
+#endif
+
+
diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..00200b8
--- /dev/null
+++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c
@@ -0,0 +1,1127 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+for the header files above, but not in this file, in order to generate the
+correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configTIMER_SERVICE_TASK_NAME
+	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
+#endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
+#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
+#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists.
+xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+breaks some kernel aware debuggers, and debuggers that reply on removing the
+static qualifier. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													configTIMER_SERVICE_TASK_NAME,
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									configTIMER_SERVICE_TASK_NAME,
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction )
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Status is thus far zero as the timer is not created statically
+			and has not been started.  The auto-reload bit may get set in
+			prvInitialiseNewTimer. */
+			pxNewTimer->ucStatus = 0x00;
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer )
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structure. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+		if( pxNewTimer != NULL )
+		{
+			/* Timers can be created statically or dynamically so note this
+			timer was created statically in case it is later deleted.  The
+			auto-reload bit may get set in prvInitialiseNewTimer(). */
+			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer )
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		if( uxAutoReload != pdFALSE )
+		{
+			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
+{
+Timer_t * pxTimer =  xTimer;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( uxAutoReload != pdFALSE )
+		{
+			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+		}
+		else
+		{
+			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+UBaseType_t uxReturn;
+
+	configASSERT( xTimer );
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+		{
+			/* Not an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdFALSE;
+		}
+		else
+		{
+			/* Is an auto-reload timer. */
+			uxReturn = ( UBaseType_t ) pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer =  xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto-reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( prvTimerTask, pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+				case tmrCOMMAND_START_FROM_ISR :
+				case tmrCOMMAND_RESET :
+				case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list. */
+					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+					{
+						/* The timer has already been removed from the active list,
+						just free up the memory if the memory was dynamically
+						allocated. */
+						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+						}
+					}
+					#else
+					{
+						/* If dynamic allocation is not enabled, the memory
+						could not have been dynamically allocated. So there is
+						no need to free the memory - just mark the timer as
+						"not active". */
+						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xReturn;
+Timer_t *pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+		{
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+	{
+		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
+	{
+		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/User/bsp/bsp.h b/User/bsp/bsp.h
new file mode 100644
index 0000000..1f8cbfd
--- /dev/null
+++ b/User/bsp/bsp.h
@@ -0,0 +1,28 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define BSP_OK (0)
+#define BSP_ERR (-1)
+#define BSP_ERR_NULL (-2)
+#define BSP_ERR_INITED (-3)
+#define BSP_ERR_NO_DEV (-4)
+#define BSP_ERR_TIMEOUT (-5)
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/bsp_config.yaml b/User/bsp/bsp_config.yaml
new file mode 100644
index 0000000..c5becf0
--- /dev/null
+++ b/User/bsp/bsp_config.yaml
@@ -0,0 +1,77 @@
+can:
+  devices:
+  - instance: CAN1
+    name: '1'
+  - instance: CAN2
+    name: '2'
+  enabled: true
+gpio:
+  configs:
+  - custom_name: USER_KEY
+    has_exti: true
+    ioc_label: USER_KEY
+    pin: PA0-WKUP
+    type: EXTI
+  - custom_name: ACCL_CS
+    has_exti: false
+    ioc_label: ACCL_CS
+    pin: PA4
+    type: OUTPUT
+  - custom_name: GYRO_CS
+    has_exti: false
+    ioc_label: GYRO_CS
+    pin: PB0
+    type: OUTPUT
+  - custom_name: ACCL_INT
+    has_exti: true
+    ioc_label: ACCL_INT
+    pin: PC4
+    type: EXTI
+  - custom_name: GYRO_INT
+    has_exti: true
+    ioc_label: GYRO_INT
+    pin: PC5
+    type: EXTI
+  - custom_name: CMPS_INT
+    has_exti: true
+    ioc_label: CMPS_INT
+    pin: PG3
+    type: EXTI
+  - custom_name: CMPS_RST
+    has_exti: false
+    ioc_label: CMPS_RST
+    pin: PG6
+    type: OUTPUT
+  enabled: true
+i2c:
+  devices:
+  - instance: I2C2
+    name: '2'
+  enabled: true
+mm:
+  enabled: true
+pwm:
+  configs:
+  - channel: TIM_CHANNEL_1
+    custom_name: IMU_HEAT
+    label: TIM10_CH1
+    timer: TIM10
+  enabled: true
+spi:
+  devices:
+  - instance: SPI1
+    name: BMI088
+  enabled: true
+time:
+  enabled: true
+uart:
+  devices:
+  - instance: USART1
+    name: '1'
+  - instance: USART1
+    name: '2'
+  - instance: USART6
+    name: AI
+  - instance: USART3
+    name: '3'
+  enabled: true
diff --git a/User/bsp/can.c b/User/bsp/can.c
new file mode 100644
index 0000000..e401cdd
--- /dev/null
+++ b/User/bsp/can.c
@@ -0,0 +1,708 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/can.h"
+#include "bsp/bsp.h"
+#include 
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+#define CAN_QUEUE_MUTEX_TIMEOUT         100   /* 队列互斥锁超时时间(ms) */
+#define CAN_TX_MAILBOX_NUM              3     /* CAN发送邮箱数量 */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+typedef struct BSP_CAN_QueueNode {
+    BSP_CAN_t can;         /* CAN通道 */
+    uint32_t can_id; /* 解析后的CAN ID */
+    osMessageQueueId_t queue; /* 消息队列ID */
+    uint8_t queue_size; /* 队列大小 */
+    struct BSP_CAN_QueueNode *next; /* 指向下一个节点的指针 */
+} BSP_CAN_QueueNode_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static BSP_CAN_QueueNode_t *queue_list = NULL;
+static osMutexId_t queue_mutex = NULL;
+static void (*CAN_Callback[BSP_CAN_NUM][BSP_CAN_CB_NUM])(void);
+static bool inited = false;
+static BSP_CAN_IdParser_t id_parser = NULL; /* ID解析器 */
+static BSP_CAN_TxQueue_t tx_queues[BSP_CAN_NUM]; /* 每个CAN的发送队列 */
+
+/* Private function prototypes ---------------------------------------------- */
+static BSP_CAN_t CAN_Get(CAN_HandleTypeDef *hcan);
+static osMessageQueueId_t BSP_CAN_FindQueue(BSP_CAN_t can, uint32_t can_id);
+static int8_t BSP_CAN_CreateIdQueue(BSP_CAN_t can, uint32_t can_id, uint8_t queue_size);
+static void BSP_CAN_RxFifo0Callback(void);
+static void BSP_CAN_RxFifo1Callback(void);
+static void BSP_CAN_TxCompleteCallback(void);
+static BSP_CAN_FrameType_t BSP_CAN_GetFrameType(CAN_RxHeaderTypeDef *header);
+static uint32_t BSP_CAN_DefaultIdParser(uint32_t original_id, BSP_CAN_FrameType_t frame_type);
+static void BSP_CAN_TxQueueInit(BSP_CAN_t can);
+static bool BSP_CAN_TxQueuePush(BSP_CAN_t can, BSP_CAN_TxMessage_t *msg);
+static bool BSP_CAN_TxQueuePop(BSP_CAN_t can, BSP_CAN_TxMessage_t *msg);
+static bool BSP_CAN_TxQueueIsEmpty(BSP_CAN_t can);
+
+/* Private functions -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+/**
+ * @brief 根据CAN句柄获取BSP_CAN实例
+ */
+static BSP_CAN_t CAN_Get(CAN_HandleTypeDef *hcan) {
+    if (hcan == NULL) return BSP_CAN_ERR;
+    
+    if (hcan->Instance == CAN1)
+        return BSP_CAN_1;
+    else if (hcan->Instance == CAN2)
+        return BSP_CAN_2;
+    else
+        return BSP_CAN_ERR;
+}
+
+/**
+ * @brief 查找指定CAN ID的消息队列
+ * @note 调用前需要获取互斥锁
+ */
+static osMessageQueueId_t BSP_CAN_FindQueue(BSP_CAN_t can, uint32_t can_id) {
+    BSP_CAN_QueueNode_t *node = queue_list;
+    while (node != NULL) {
+        if (node->can == can && node->can_id == can_id) {
+            return node->queue;
+        }
+        node = node->next;
+    }
+    return NULL;
+}
+
+/**
+ * @brief 创建指定CAN ID的消息队列
+ * @note 内部函数，已包含互斥锁保护
+ */
+static int8_t BSP_CAN_CreateIdQueue(BSP_CAN_t can, uint32_t can_id, uint8_t queue_size) {
+    if (queue_size == 0) {
+        queue_size = BSP_CAN_DEFAULT_QUEUE_SIZE;
+    }
+    if (osMutexAcquire(queue_mutex, CAN_QUEUE_MUTEX_TIMEOUT) != osOK) {
+        return BSP_ERR_TIMEOUT;
+    }
+    BSP_CAN_QueueNode_t *node = queue_list;
+    while (node != NULL) {
+        if (node->can == can && node->can_id == can_id) {
+            osMutexRelease(queue_mutex);
+            return BSP_ERR;  // 已存在
+        }
+        node = node->next;
+    }
+    BSP_CAN_QueueNode_t *new_node = (BSP_CAN_QueueNode_t *)BSP_Malloc(sizeof(BSP_CAN_QueueNode_t));
+    if (new_node == NULL) {
+        osMutexRelease(queue_mutex);
+        return BSP_ERR_NULL;
+    }
+    new_node->queue = osMessageQueueNew(queue_size, sizeof(BSP_CAN_Message_t), NULL);
+    if (new_node->queue == NULL) {
+        BSP_Free(new_node);
+        osMutexRelease(queue_mutex);
+        return BSP_ERR;
+    }
+    new_node->can = can;
+    new_node->can_id = can_id;
+    new_node->queue_size = queue_size;
+    new_node->next = queue_list;
+    queue_list = new_node;
+    osMutexRelease(queue_mutex);
+    return BSP_OK;
+}
+
+
+/**
+ * @brief 获取帧类型
+ */
+static BSP_CAN_FrameType_t BSP_CAN_GetFrameType(CAN_RxHeaderTypeDef *header) {
+    if (header->RTR == CAN_RTR_REMOTE) {
+        return (header->IDE == CAN_ID_EXT) ? BSP_CAN_FRAME_EXT_REMOTE : BSP_CAN_FRAME_STD_REMOTE;
+    } else {
+        return (header->IDE == CAN_ID_EXT) ? BSP_CAN_FRAME_EXT_DATA : BSP_CAN_FRAME_STD_DATA;
+    }
+}
+
+/**
+ * @brief 默认ID解析器（直接返回原始ID）
+ */
+static uint32_t BSP_CAN_DefaultIdParser(uint32_t original_id, BSP_CAN_FrameType_t frame_type) {
+    (void)frame_type;  // 避免未使用参数警告
+    return original_id;
+}
+
+/**
+ * @brief 初始化发送队列
+ */
+static void BSP_CAN_TxQueueInit(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) return;
+    
+    tx_queues[can].head = 0;
+    tx_queues[can].tail = 0;
+}
+
+/**
+ * @brief 向发送队列添加消息（无锁）
+ */
+static bool BSP_CAN_TxQueuePush(BSP_CAN_t can, BSP_CAN_TxMessage_t *msg) {
+    if (can >= BSP_CAN_NUM || msg == NULL) return false;
+    
+    BSP_CAN_TxQueue_t *queue = &tx_queues[can];
+    uint32_t next_head = (queue->head + 1) % BSP_CAN_TX_QUEUE_SIZE;
+    
+    // 队列满
+    if (next_head == queue->tail) {
+        return false;
+    }
+    
+    // 复制消息
+    queue->buffer[queue->head] = *msg;
+    
+    // 更新头指针（原子操作）
+    queue->head = next_head;
+    
+    return true;
+}
+
+
+/**
+ * @brief 从发送队列取出消息（无锁）
+ */
+static bool BSP_CAN_TxQueuePop(BSP_CAN_t can, BSP_CAN_TxMessage_t *msg) {
+    if (can >= BSP_CAN_NUM || msg == NULL) return false;
+    
+    BSP_CAN_TxQueue_t *queue = &tx_queues[can];
+    
+    // 队列空
+    if (queue->head == queue->tail) {
+        return false;
+    }
+    
+    // 复制消息
+    *msg = queue->buffer[queue->tail];
+    
+    // 更新尾指针（原子操作）
+    queue->tail = (queue->tail + 1) % BSP_CAN_TX_QUEUE_SIZE;
+    
+    return true;
+}
+
+/**
+ * @brief 检查发送队列是否为空
+ */
+static bool BSP_CAN_TxQueueIsEmpty(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) return true;
+    
+    return tx_queues[can].head == tx_queues[can].tail;
+}
+
+/**
+ * @brief 处理所有CAN实例的发送队列
+ */
+static void BSP_CAN_TxCompleteCallback(void) {
+    // 处理所有CAN实例的发送队列
+    for (int i = 0; i < BSP_CAN_NUM; i++) {
+        BSP_CAN_t can = (BSP_CAN_t)i;
+        CAN_HandleTypeDef *hcan = BSP_CAN_GetHandle(can);
+        if (hcan == NULL) continue;
+        
+        BSP_CAN_TxMessage_t msg;
+        uint32_t mailbox;
+        
+        // 尝试发送队列中的消息
+        while (!BSP_CAN_TxQueueIsEmpty(can)) {
+            // 检查是否有空闲邮箱
+            if (HAL_CAN_GetTxMailboxesFreeLevel(hcan) == 0) {
+                break; // 没有空闲邮箱，等待下次中断
+            }
+            
+            // 从队列中取出消息
+            if (!BSP_CAN_TxQueuePop(can, &msg)) {
+                break;
+            }
+            
+            // 发送消息
+            if (HAL_CAN_AddTxMessage(hcan, &msg.header, msg.data, &mailbox) != HAL_OK) {
+                // 发送失败，消息已经从队列中移除，直接丢弃
+                break;
+            }
+        }
+    }
+}
+
+
+/**
+ * @brief FIFO0接收处理函数
+ */
+static void BSP_CAN_RxFifo0Callback(void) {
+    CAN_RxHeaderTypeDef rx_header;
+    uint8_t rx_data[BSP_CAN_MAX_DLC];
+    for (int can_idx = 0; can_idx < BSP_CAN_NUM; can_idx++) {
+        CAN_HandleTypeDef *hcan = BSP_CAN_GetHandle((BSP_CAN_t)can_idx);
+        if (hcan == NULL) continue;
+        while (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) > 0) {
+            if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &rx_header, rx_data) == HAL_OK) {
+                uint32_t original_id = (rx_header.IDE == CAN_ID_STD) ? rx_header.StdId : rx_header.ExtId;
+                BSP_CAN_FrameType_t frame_type = BSP_CAN_GetFrameType(&rx_header);
+                uint32_t parsed_id = BSP_CAN_ParseId(original_id, frame_type);
+                osMessageQueueId_t queue = BSP_CAN_FindQueue((BSP_CAN_t)can_idx, parsed_id);
+                if (queue != NULL) {
+                    BSP_CAN_Message_t msg = {0};
+                    msg.frame_type = frame_type;
+                    msg.original_id = original_id;
+                    msg.parsed_id = parsed_id;
+                    msg.dlc = rx_header.DLC;
+                    if (rx_header.RTR == CAN_RTR_DATA) {
+                        memcpy(msg.data, rx_data, rx_header.DLC);
+                    }
+                    msg.timestamp = HAL_GetTick();
+                    osMessageQueuePut(queue, &msg, 0, BSP_CAN_TIMEOUT_IMMEDIATE);
+                }
+            }
+        }
+    }
+}
+
+/**
+ * @brief FIFO1接收处理函数
+ */
+static void BSP_CAN_RxFifo1Callback(void) {
+    CAN_RxHeaderTypeDef rx_header;
+    uint8_t rx_data[BSP_CAN_MAX_DLC];
+    for (int can_idx = 0; can_idx < BSP_CAN_NUM; can_idx++) {
+        CAN_HandleTypeDef *hcan = BSP_CAN_GetHandle((BSP_CAN_t)can_idx);
+        if (hcan == NULL) continue;
+        while (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) > 0) {
+            if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO1, &rx_header, rx_data) == HAL_OK) {
+                uint32_t original_id = (rx_header.IDE == CAN_ID_STD) ? rx_header.StdId : rx_header.ExtId;
+                BSP_CAN_FrameType_t frame_type = BSP_CAN_GetFrameType(&rx_header);
+                uint32_t parsed_id = BSP_CAN_ParseId(original_id, frame_type);
+                osMessageQueueId_t queue = BSP_CAN_FindQueue((BSP_CAN_t)can_idx, parsed_id);
+                if (queue != NULL) {
+                    BSP_CAN_Message_t msg = {0};
+                    msg.frame_type = frame_type;
+                    msg.original_id = original_id;
+                    msg.parsed_id = parsed_id;
+                    msg.dlc = rx_header.DLC;
+                    if (rx_header.RTR == CAN_RTR_DATA) {
+                        memcpy(msg.data, rx_data, rx_header.DLC);
+                    }
+                    msg.timestamp = HAL_GetTick();
+                    osMessageQueuePut(queue, &msg, 0, BSP_CAN_TIMEOUT_IMMEDIATE);
+                }
+            }
+        }
+    }
+}
+
+/* HAL Callback Functions --------------------------------------------------- */
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX0_CPLT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX0_CPLT_CB]();
+    }
+}
+
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX1_CPLT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX1_CPLT_CB]();
+    }
+}
+
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX2_CPLT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX2_CPLT_CB]();
+    }
+}
+
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX0_ABORT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX0_ABORT_CB]();
+    }
+}
+
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX1_ABORT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX1_ABORT_CB]();
+    }
+}
+
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) {
+    BSP_CAN_t bsp_can = CAN_Get(hcan);
+    if (bsp_can != BSP_CAN_ERR) {
+        // 调用用户回调
+        if (CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX2_ABORT_CB])
+            CAN_Callback[bsp_can][HAL_CAN_TX_MAILBOX2_ABORT_CB]();
+    }
+}
+
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_RX_FIFO0_MSG_PENDING_CB])
+      CAN_Callback[bsp_can][HAL_CAN_RX_FIFO0_MSG_PENDING_CB]();
+  }
+}
+
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_RX_FIFO0_FULL_CB])
+      CAN_Callback[bsp_can][HAL_CAN_RX_FIFO0_FULL_CB]();
+  }
+}
+
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_RX_FIFO1_MSG_PENDING_CB])
+      CAN_Callback[bsp_can][HAL_CAN_RX_FIFO1_MSG_PENDING_CB]();
+  }
+}
+
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_RX_FIFO1_FULL_CB])
+      CAN_Callback[bsp_can][HAL_CAN_RX_FIFO1_FULL_CB]();
+  }
+}
+
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_SLEEP_CB])
+      CAN_Callback[bsp_can][HAL_CAN_SLEEP_CB]();
+  }
+}
+
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_WAKEUP_FROM_RX_MSG_CB])
+      CAN_Callback[bsp_can][HAL_CAN_WAKEUP_FROM_RX_MSG_CB]();
+  }
+}
+
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) {
+  BSP_CAN_t bsp_can = CAN_Get(hcan);
+  if (bsp_can != BSP_CAN_ERR) {
+    if (CAN_Callback[bsp_can][HAL_CAN_ERROR_CB])
+      CAN_Callback[bsp_can][HAL_CAN_ERROR_CB]();
+  }
+}
+
+/* Exported functions ------------------------------------------------------- */
+
+int8_t BSP_CAN_Init(void) {
+    if (inited) {
+        return BSP_ERR_INITED;
+    }
+    
+    // 清零回调函数数组
+    memset(CAN_Callback, 0, sizeof(CAN_Callback));
+        
+    // 初始化发送队列
+    for (int i = 0; i < BSP_CAN_NUM; i++) {
+        BSP_CAN_TxQueueInit((BSP_CAN_t)i);
+    }
+
+    // 初始化ID解析器为默认解析器
+    id_parser = BSP_CAN_DefaultIdParser;
+    
+    // 创建互斥锁
+    queue_mutex = osMutexNew(NULL);
+    if (queue_mutex == NULL) {
+        return BSP_ERR;
+    }
+    
+    // 先设置初始化标志，以便后续回调注册能通过检查
+    inited = true;
+
+    // 初始化 CAN1 - 使用 FIFO0
+    CAN_FilterTypeDef can1_filter = {0};
+    can1_filter.FilterBank = 0;
+    can1_filter.FilterIdHigh = 0;
+    can1_filter.FilterIdLow = 0;
+    can1_filter.FilterMode = CAN_FILTERMODE_IDMASK;
+    can1_filter.FilterScale = CAN_FILTERSCALE_32BIT;
+    can1_filter.FilterMaskIdHigh = 0;
+    can1_filter.FilterMaskIdLow = 0;
+    can1_filter.FilterActivation = ENABLE;
+    can1_filter.SlaveStartFilterBank = 14;
+    can1_filter.FilterFIFOAssignment = CAN_RX_FIFO0;
+    HAL_CAN_ConfigFilter(&hcan1, &can1_filter);
+    HAL_CAN_Start(&hcan1);
+
+    // 自动注册CAN1接收回调函数
+    BSP_CAN_RegisterCallback(BSP_CAN_1, HAL_CAN_RX_FIFO0_MSG_PENDING_CB, BSP_CAN_RxFifo0Callback);
+    BSP_CAN_RegisterCallback(BSP_CAN_1, HAL_CAN_TX_MAILBOX0_CPLT_CB, BSP_CAN_TxCompleteCallback);
+    BSP_CAN_RegisterCallback(BSP_CAN_1, HAL_CAN_TX_MAILBOX1_CPLT_CB, BSP_CAN_TxCompleteCallback);
+    BSP_CAN_RegisterCallback(BSP_CAN_1, HAL_CAN_TX_MAILBOX2_CPLT_CB, BSP_CAN_TxCompleteCallback);
+
+    // 激活CAN1中断
+    HAL_CAN_ActivateNotification(&hcan1, CAN_IT_RX_FIFO0_MSG_PENDING | 
+                                        CAN_IT_TX_MAILBOX_EMPTY);  // 激活发送邮箱空中断
+
+    // 初始化 CAN2 - 使用 FIFO1
+    can1_filter.FilterBank = 14;
+    can1_filter.FilterFIFOAssignment = CAN_RX_FIFO1;
+    HAL_CAN_ConfigFilter(&hcan2, &can1_filter);  // 通过 CAN1 配置
+    HAL_CAN_Start(&hcan2);
+
+    // 自动注册CAN2接收回调函数
+    BSP_CAN_RegisterCallback(BSP_CAN_2, HAL_CAN_RX_FIFO1_MSG_PENDING_CB, BSP_CAN_RxFifo1Callback);
+    BSP_CAN_RegisterCallback(BSP_CAN_2, HAL_CAN_TX_MAILBOX0_CPLT_CB, BSP_CAN_TxCompleteCallback);
+    BSP_CAN_RegisterCallback(BSP_CAN_2, HAL_CAN_TX_MAILBOX1_CPLT_CB, BSP_CAN_TxCompleteCallback);
+    BSP_CAN_RegisterCallback(BSP_CAN_2, HAL_CAN_TX_MAILBOX2_CPLT_CB, BSP_CAN_TxCompleteCallback);
+
+    // 激活CAN2中断
+    HAL_CAN_ActivateNotification(&hcan2, CAN_IT_RX_FIFO1_MSG_PENDING | 
+                                        CAN_IT_TX_MAILBOX_EMPTY);  // 激活发送邮箱空中断
+
+    
+    inited = true;
+    return BSP_OK;
+}
+
+
+CAN_HandleTypeDef *BSP_CAN_GetHandle(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) {
+        return NULL;
+    }
+    
+    switch (can) {
+    case BSP_CAN_1:
+      return &hcan1;
+    case BSP_CAN_2:
+      return &hcan2;
+        default:
+            return NULL;
+    }
+}
+
+int8_t BSP_CAN_RegisterCallback(BSP_CAN_t can, BSP_CAN_Callback_t type,
+                                void (*callback)(void)) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    if (callback == NULL) {
+        return BSP_ERR_NULL;
+    }
+    if (can >= BSP_CAN_NUM) {
+        return BSP_ERR;
+    }
+    if (type >= BSP_CAN_CB_NUM) {
+        return BSP_ERR;
+    }
+    
+    CAN_Callback[can][type] = callback;
+    return BSP_OK;
+}
+
+int8_t BSP_CAN_Transmit(BSP_CAN_t can, BSP_CAN_Format_t format,
+                        uint32_t id, uint8_t *data, uint8_t dlc) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    if (can >= BSP_CAN_NUM) {
+        return BSP_ERR;
+    }
+    if (data == NULL && format != BSP_CAN_FORMAT_STD_REMOTE && format != BSP_CAN_FORMAT_EXT_REMOTE) {
+        return BSP_ERR_NULL;
+    }
+    if (dlc > BSP_CAN_MAX_DLC) {
+        return BSP_ERR;
+    }
+    
+    CAN_HandleTypeDef *hcan = BSP_CAN_GetHandle(can);
+    if (hcan == NULL) {
+        return BSP_ERR_NULL;
+    }
+    
+    // 准备发送消息
+    BSP_CAN_TxMessage_t tx_msg = {0};
+    
+    switch (format) {
+        case BSP_CAN_FORMAT_STD_DATA:
+            tx_msg.header.StdId = id;
+            tx_msg.header.IDE = CAN_ID_STD;
+            tx_msg.header.RTR = CAN_RTR_DATA;
+            break;
+        case BSP_CAN_FORMAT_EXT_DATA:
+            tx_msg.header.ExtId = id;
+            tx_msg.header.IDE = CAN_ID_EXT;
+            tx_msg.header.RTR = CAN_RTR_DATA;
+            break;
+        case BSP_CAN_FORMAT_STD_REMOTE:
+            tx_msg.header.StdId = id;
+            tx_msg.header.IDE = CAN_ID_STD;
+            tx_msg.header.RTR = CAN_RTR_REMOTE;
+            break;
+        case BSP_CAN_FORMAT_EXT_REMOTE:
+            tx_msg.header.ExtId = id;
+            tx_msg.header.IDE = CAN_ID_EXT;
+            tx_msg.header.RTR = CAN_RTR_REMOTE;
+            break;
+        default:
+            return BSP_ERR;
+    }
+    
+    tx_msg.header.DLC = dlc;
+    tx_msg.header.TransmitGlobalTime = DISABLE;
+    
+    // 复制数据
+    if (data != NULL && dlc > 0) {
+        memcpy(tx_msg.data, data, dlc);
+    }
+    
+    // 尝试直接发送到邮箱
+    uint32_t mailbox;
+    if (HAL_CAN_GetTxMailboxesFreeLevel(hcan) > 0) {
+        HAL_StatusTypeDef result = HAL_CAN_AddTxMessage(hcan, &tx_msg.header, tx_msg.data, &mailbox);
+        if (result == HAL_OK) {
+            return BSP_OK; // 发送成功
+        }
+    }
+    
+    // 邮箱满，尝试放入队列
+    if (BSP_CAN_TxQueuePush(can, &tx_msg)) {
+        return BSP_OK; // 成功放入队列
+    }
+    
+    // 队列也满，丢弃数据
+    return BSP_ERR; // 数据丢弃
+}
+
+int8_t BSP_CAN_TransmitStdDataFrame(BSP_CAN_t can, BSP_CAN_StdDataFrame_t *frame) {
+    if (frame == NULL) {
+        return BSP_ERR_NULL;
+    }
+    return BSP_CAN_Transmit(can, BSP_CAN_FORMAT_STD_DATA, frame->id, frame->data, frame->dlc);
+}
+
+int8_t BSP_CAN_TransmitExtDataFrame(BSP_CAN_t can, BSP_CAN_ExtDataFrame_t *frame) {
+    if (frame == NULL) {
+        return BSP_ERR_NULL;
+    }
+    return BSP_CAN_Transmit(can, BSP_CAN_FORMAT_EXT_DATA, frame->id, frame->data, frame->dlc);
+}
+
+int8_t BSP_CAN_TransmitRemoteFrame(BSP_CAN_t can, BSP_CAN_RemoteFrame_t *frame) {
+    if (frame == NULL) {
+        return BSP_ERR_NULL;
+    }
+    BSP_CAN_Format_t format = frame->is_extended ? BSP_CAN_FORMAT_EXT_REMOTE : BSP_CAN_FORMAT_STD_REMOTE;
+    return BSP_CAN_Transmit(can, format, frame->id, NULL, frame->dlc);
+}
+
+int8_t BSP_CAN_RegisterId(BSP_CAN_t can, uint32_t can_id, uint8_t queue_size) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    return BSP_CAN_CreateIdQueue(can, can_id, queue_size);
+}
+
+
+int8_t BSP_CAN_GetMessage(BSP_CAN_t can, uint32_t can_id, BSP_CAN_Message_t *msg, uint32_t timeout) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    if (msg == NULL) {
+        return BSP_ERR_NULL;
+    }
+    if (osMutexAcquire(queue_mutex, CAN_QUEUE_MUTEX_TIMEOUT) != osOK) {
+        return BSP_ERR_TIMEOUT;
+    }
+    osMessageQueueId_t queue = BSP_CAN_FindQueue(can, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) {
+        return BSP_ERR_NO_DEV;
+    }
+    osStatus_t result = osMessageQueueGet(queue, msg, NULL, timeout);
+    return (result == osOK) ? BSP_OK : BSP_ERR;
+}
+
+int32_t BSP_CAN_GetQueueCount(BSP_CAN_t can, uint32_t can_id) {
+    if (!inited) {
+        return -1;
+    }
+    if (osMutexAcquire(queue_mutex, CAN_QUEUE_MUTEX_TIMEOUT) != osOK) {
+        return -1;
+    }
+    osMessageQueueId_t queue = BSP_CAN_FindQueue(can, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) {
+        return -1;
+    }
+    return (int32_t)osMessageQueueGetCount(queue);
+}
+
+int8_t BSP_CAN_FlushQueue(BSP_CAN_t can, uint32_t can_id) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    if (osMutexAcquire(queue_mutex, CAN_QUEUE_MUTEX_TIMEOUT) != osOK) {
+        return BSP_ERR_TIMEOUT;
+    }
+    osMessageQueueId_t queue = BSP_CAN_FindQueue(can, can_id);
+    osMutexRelease(queue_mutex);
+    if (queue == NULL) {
+        return BSP_ERR_NO_DEV;
+    }
+    BSP_CAN_Message_t temp_msg;
+    while (osMessageQueueGet(queue, &temp_msg, NULL, BSP_CAN_TIMEOUT_IMMEDIATE) == osOK) {
+        // 清空
+    }
+    return BSP_OK;
+}
+
+int8_t BSP_CAN_RegisterIdParser(BSP_CAN_IdParser_t parser) {
+    if (!inited) {
+        return BSP_ERR_INITED;
+    }
+    if (parser == NULL) {
+        return BSP_ERR_NULL;
+    }
+    
+    id_parser = parser;
+    return BSP_OK;
+}
+
+uint32_t BSP_CAN_ParseId(uint32_t original_id, BSP_CAN_FrameType_t frame_type) {
+    if (id_parser != NULL) {
+        return id_parser(original_id, frame_type);
+    }
+    return BSP_CAN_DefaultIdParser(original_id, frame_type);
+}
+
+
diff --git a/User/bsp/can.h b/User/bsp/can.h
new file mode 100644
index 0000000..e6b5f71
--- /dev/null
+++ b/User/bsp/can.h
@@ -0,0 +1,259 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "bsp/bsp.h"
+#include "bsp/mm.h"
+#include 
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+#define BSP_CAN_MAX_DLC                 8
+#define BSP_CAN_DEFAULT_QUEUE_SIZE      10
+#define BSP_CAN_TIMEOUT_IMMEDIATE       0
+#define BSP_CAN_TIMEOUT_FOREVER         osWaitForever
+#define BSP_CAN_TX_QUEUE_SIZE           32    /* 发送队列大小 */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+  BSP_CAN_1,
+  BSP_CAN_2,
+  BSP_CAN_NUM,
+  BSP_CAN_ERR,
+} BSP_CAN_t;
+
+typedef enum {
+  HAL_CAN_TX_MAILBOX0_CPLT_CB,
+  HAL_CAN_TX_MAILBOX1_CPLT_CB,
+  HAL_CAN_TX_MAILBOX2_CPLT_CB,
+  HAL_CAN_TX_MAILBOX0_ABORT_CB,
+  HAL_CAN_TX_MAILBOX1_ABORT_CB,
+  HAL_CAN_TX_MAILBOX2_ABORT_CB,
+  HAL_CAN_RX_FIFO0_MSG_PENDING_CB,
+  HAL_CAN_RX_FIFO0_FULL_CB,
+  HAL_CAN_RX_FIFO1_MSG_PENDING_CB,
+  HAL_CAN_RX_FIFO1_FULL_CB,
+  HAL_CAN_SLEEP_CB,
+  HAL_CAN_WAKEUP_FROM_RX_MSG_CB,
+  HAL_CAN_ERROR_CB,
+  BSP_CAN_CB_NUM,
+} BSP_CAN_Callback_t;
+
+/* CAN消息格式枚举 - 用于发送和接收消息时指定格式 */
+typedef enum {
+  BSP_CAN_FORMAT_STD_DATA,    /* 标准数据帧 */
+  BSP_CAN_FORMAT_EXT_DATA,    /* 扩展数据帧 */
+  BSP_CAN_FORMAT_STD_REMOTE,  /* 标准远程帧 */
+  BSP_CAN_FORMAT_EXT_REMOTE,  /* 扩展远程帧 */
+} BSP_CAN_Format_t;
+
+/* CAN帧类型枚举 - 用于区分不同类型的CAN帧 */
+typedef enum {
+  BSP_CAN_FRAME_STD_DATA,     /* 标准数据帧 */
+  BSP_CAN_FRAME_EXT_DATA,     /* 扩展数据帧 */
+  BSP_CAN_FRAME_STD_REMOTE,   /* 标准远程帧 */
+  BSP_CAN_FRAME_EXT_REMOTE,   /* 扩展远程帧 */
+} BSP_CAN_FrameType_t;
+
+/* CAN消息结构体 - 支持不同类型帧 */
+typedef struct {
+    BSP_CAN_FrameType_t frame_type;     /* 帧类型 */
+    uint32_t original_id;               /* 原始ID（未解析） */
+    uint32_t parsed_id;                 /* 解析后的实际ID */
+    uint8_t dlc;                        /* 数据长度 */
+    uint8_t data[BSP_CAN_MAX_DLC];      /* 数据 */
+    uint32_t timestamp;                 /* 时间戳（可选） */
+} BSP_CAN_Message_t;
+
+/* 标准数据帧结构 */
+typedef struct {
+    uint32_t id;                        /* CAN ID */
+    uint8_t dlc;                        /* 数据长度 */
+    uint8_t data[BSP_CAN_MAX_DLC];      /* 数据 */
+} BSP_CAN_StdDataFrame_t;
+
+/* 扩展数据帧结构 */
+typedef struct {
+    uint32_t id;                        /* 扩展CAN ID */
+    uint8_t dlc;                        /* 数据长度 */
+    uint8_t data[BSP_CAN_MAX_DLC];      /* 数据 */
+} BSP_CAN_ExtDataFrame_t;
+
+/* 远程帧结构 */
+typedef struct {
+    uint32_t id;                        /* CAN ID */
+    uint8_t dlc;                        /* 请求的数据长度 */
+    bool is_extended;                   /* 是否为扩展帧 */
+} BSP_CAN_RemoteFrame_t;
+
+/* ID解析回调函数类型 */
+typedef uint32_t (*BSP_CAN_IdParser_t)(uint32_t original_id, BSP_CAN_FrameType_t frame_type);
+
+/* CAN发送消息结构体 */
+typedef struct {
+    CAN_TxHeaderTypeDef header;         /* 发送头 */
+    uint8_t data[BSP_CAN_MAX_DLC];      /* 数据 */
+} BSP_CAN_TxMessage_t;
+
+/* 无锁环形队列结构体 */
+typedef struct {
+    BSP_CAN_TxMessage_t buffer[BSP_CAN_TX_QUEUE_SIZE];  /* 缓冲区 */
+    volatile uint32_t head;             /* 队列头 */
+    volatile uint32_t tail;             /* 队列尾 */
+} BSP_CAN_TxQueue_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * @brief 初始化 CAN 模块
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_Init(void);
+
+/**
+ * @brief 获取 CAN 句柄
+ * @param can CAN 枚举
+ * @return CAN_HandleTypeDef 指针，失败返回 NULL
+ */
+CAN_HandleTypeDef *BSP_CAN_GetHandle(BSP_CAN_t can);
+
+/**
+ * @brief 注册 CAN 回调函数
+ * @param can CAN 枚举
+ * @param type 回调类型
+ * @param callback 回调函数指针
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_RegisterCallback(BSP_CAN_t can, BSP_CAN_Callback_t type,
+                                void (*callback)(void));
+
+/**
+ * @brief 发送 CAN 消息
+ * @param can CAN 枚举
+ * @param format 消息格式
+ * @param id CAN ID
+ * @param data 数据指针
+ * @param dlc 数据长度
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_Transmit(BSP_CAN_t can, BSP_CAN_Format_t format,
+                        uint32_t id, uint8_t *data, uint8_t dlc);
+
+/**
+ * @brief 发送标准数据帧
+ * @param can CAN 枚举
+ * @param frame 标准数据帧指针
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_TransmitStdDataFrame(BSP_CAN_t can, BSP_CAN_StdDataFrame_t *frame);
+
+/**
+ * @brief 发送扩展数据帧
+ * @param can CAN 枚举
+ * @param frame 扩展数据帧指针
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_TransmitExtDataFrame(BSP_CAN_t can, BSP_CAN_ExtDataFrame_t *frame);
+
+/**
+ * @brief 发送远程帧
+ * @param can CAN 枚举
+ * @param frame 远程帧指针
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_TransmitRemoteFrame(BSP_CAN_t can, BSP_CAN_RemoteFrame_t *frame);
+
+
+/**
+ * @brief 获取发送队列中待发送消息数量
+ * @param can CAN 枚举
+ * @return 队列中消息数量，-1表示错误
+ */
+int32_t BSP_CAN_GetTxQueueCount(BSP_CAN_t can);
+
+/**
+ * @brief 清空发送队列
+ * @param can CAN 枚举
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_FlushTxQueue(BSP_CAN_t can);
+
+/**
+ * @brief 注册 CAN ID 接收队列
+ * @param can CAN 枚举
+ * @param can_id 解析后的CAN ID
+ * @param queue_size 队列大小，0使用默认值
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_RegisterId(BSP_CAN_t can, uint32_t can_id, uint8_t queue_size);
+
+
+
+/**
+ * @brief 获取 CAN 消息
+ * @param can CAN 枚举
+ * @param can_id 解析后的CAN ID
+ * @param msg 存储消息的结构体指针
+ * @param timeout 超时时间（毫秒），0为立即返回，osWaitForever为永久等待
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_GetMessage(BSP_CAN_t can, uint32_t can_id, BSP_CAN_Message_t *msg, uint32_t timeout);
+
+/**
+ * @brief 获取指定ID队列中的消息数量
+ * @param can CAN 枚举
+ * @param can_id 解析后的CAN ID
+ * @return 消息数量，-1表示队列不存在
+ */
+int32_t BSP_CAN_GetQueueCount(BSP_CAN_t can, uint32_t can_id);
+
+/**
+ * @brief 清空指定ID队列中的所有消息
+ * @param can CAN 枚举
+ * @param can_id 解析后的CAN ID
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_FlushQueue(BSP_CAN_t can, uint32_t can_id);
+
+/**
+ * @brief 注册ID解析器
+ * @param parser ID解析回调函数
+ * @return BSP_OK 成功，其他值失败
+ */
+int8_t BSP_CAN_RegisterIdParser(BSP_CAN_IdParser_t parser);
+
+
+/**
+ * @brief 解析CAN ID
+ * @param original_id 原始ID
+ * @param frame_type 帧类型
+ * @return 解析后的ID
+ */
+uint32_t BSP_CAN_ParseId(uint32_t original_id, BSP_CAN_FrameType_t frame_type);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/bsp/gpio.c b/User/bsp/gpio.c
new file mode 100644
index 0000000..580696e
--- /dev/null
+++ b/User/bsp/gpio.c
@@ -0,0 +1,126 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/gpio.h"
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+typedef struct {
+  uint16_t pin;
+  GPIO_TypeDef *gpio;
+} BSP_GPIO_MAP_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static const BSP_GPIO_MAP_t GPIO_Map[BSP_GPIO_NUM] = {
+    {USER_KEY_Pin, USER_KEY_GPIO_Port},
+    {ACCL_CS_Pin, ACCL_CS_GPIO_Port},
+    {GYRO_CS_Pin, GYRO_CS_GPIO_Port},
+    {ACCL_INT_Pin, ACCL_INT_GPIO_Port},
+    {GYRO_INT_Pin, GYRO_INT_GPIO_Port},
+    {CMPS_INT_Pin, CMPS_INT_GPIO_Port},
+    {CMPS_RST_Pin, CMPS_RST_GPIO_Port},
+};
+
+static void (*GPIO_Callback[16])(void);
+
+/* Private function  -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
+  for (uint8_t i = 0; i < 16; i++) {
+    if (GPIO_Pin & (1 << i)) {
+      if (GPIO_Callback[i]) {
+        GPIO_Callback[i]();
+      }
+    }
+  }
+}
+
+/* Exported functions ------------------------------------------------------- */
+int8_t BSP_GPIO_RegisterCallback(BSP_GPIO_t gpio, void (*callback)(void)) {
+  if (callback == NULL) return BSP_ERR_NULL;
+  if (gpio >= BSP_GPIO_NUM) return BSP_ERR;
+
+  // 从GPIO映射中获取对应的pin值
+  uint16_t pin = GPIO_Map[gpio].pin;
+  
+  for (uint8_t i = 0; i < 16; i++) {
+    if (pin & (1 << i)) {
+      GPIO_Callback[i] = callback;
+      break;
+    }
+  }
+  return BSP_OK;
+}
+
+int8_t BSP_GPIO_EnableIRQ(BSP_GPIO_t gpio) {
+  switch (gpio) {
+    case BSP_GPIO_USER_KEY:
+      HAL_NVIC_EnableIRQ(USER_KEY_EXTI_IRQn);
+      break;
+    case BSP_GPIO_ACCL_INT:
+      HAL_NVIC_EnableIRQ(ACCL_INT_EXTI_IRQn);
+      break;
+    case BSP_GPIO_GYRO_INT:
+      HAL_NVIC_EnableIRQ(GYRO_INT_EXTI_IRQn);
+      break;
+    case BSP_GPIO_CMPS_INT:
+      HAL_NVIC_EnableIRQ(CMPS_INT_EXTI_IRQn);
+      break;
+    default:
+      return BSP_ERR;
+  }
+  return BSP_OK;
+}
+
+int8_t BSP_GPIO_DisableIRQ(BSP_GPIO_t gpio) {
+  switch (gpio) {
+    case BSP_GPIO_USER_KEY:
+      HAL_NVIC_DisableIRQ(USER_KEY_EXTI_IRQn);
+      break;
+    case BSP_GPIO_ACCL_INT:
+      HAL_NVIC_DisableIRQ(ACCL_INT_EXTI_IRQn);
+      break;
+    case BSP_GPIO_GYRO_INT:
+      HAL_NVIC_DisableIRQ(GYRO_INT_EXTI_IRQn);
+      break;
+    case BSP_GPIO_CMPS_INT:
+      HAL_NVIC_DisableIRQ(CMPS_INT_EXTI_IRQn);
+      break;
+    default:
+      return BSP_ERR;
+  }
+  return BSP_OK;
+}
+int8_t BSP_GPIO_WritePin(BSP_GPIO_t gpio, bool value){
+  if (gpio >= BSP_GPIO_NUM) return BSP_ERR;
+  HAL_GPIO_WritePin(GPIO_Map[gpio].gpio, GPIO_Map[gpio].pin, value);
+  return BSP_OK;
+}
+
+int8_t BSP_GPIO_TogglePin(BSP_GPIO_t gpio){
+  if (gpio >= BSP_GPIO_NUM) return BSP_ERR;
+  HAL_GPIO_TogglePin(GPIO_Map[gpio].gpio, GPIO_Map[gpio].pin);
+  return BSP_OK;
+}
+
+bool BSP_GPIO_ReadPin(BSP_GPIO_t gpio){
+  if (gpio >= BSP_GPIO_NUM) return false;
+  return HAL_GPIO_ReadPin(GPIO_Map[gpio].gpio, GPIO_Map[gpio].pin) == GPIO_PIN_SET;
+}
\ No newline at end of file
diff --git a/User/bsp/gpio.h b/User/bsp/gpio.h
new file mode 100644
index 0000000..b5d92ef
--- /dev/null
+++ b/User/bsp/gpio.h
@@ -0,0 +1,53 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+  BSP_GPIO_USER_KEY,
+  BSP_GPIO_ACCL_CS,
+  BSP_GPIO_GYRO_CS,
+  BSP_GPIO_ACCL_INT,
+  BSP_GPIO_GYRO_INT,
+  BSP_GPIO_CMPS_INT,
+  BSP_GPIO_CMPS_RST,
+  BSP_GPIO_NUM,
+  BSP_GPIO_ERR,
+} BSP_GPIO_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t BSP_GPIO_RegisterCallback(BSP_GPIO_t gpio, void (*callback)(void));
+
+int8_t BSP_GPIO_EnableIRQ(BSP_GPIO_t gpio);
+int8_t BSP_GPIO_DisableIRQ(BSP_GPIO_t gpio);
+
+int8_t BSP_GPIO_WritePin(BSP_GPIO_t gpio, bool value);
+int8_t BSP_GPIO_TogglePin(BSP_GPIO_t gpio);
+
+bool BSP_GPIO_ReadPin(BSP_GPIO_t gpio);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/bsp/i2c.c b/User/bsp/i2c.c
new file mode 100644
index 0000000..74dba61
--- /dev/null
+++ b/User/bsp/i2c.c
@@ -0,0 +1,190 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp\i2c.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static void (*I2C_Callback[BSP_I2C_NUM][BSP_I2C_CB_NUM])(void);
+
+/* Private function  -------------------------------------------------------- */
+static BSP_I2C_t I2C_Get(I2C_HandleTypeDef *hi2c) {
+  if (hi2c->Instance == I2C2)
+    return BSP_I2C_2;
+  else
+    return BSP_I2C_ERR;
+}
+
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_MASTER_TX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_MASTER_TX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_MASTER_RX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_MASTER_RX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_SLAVE_TX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_SLAVE_TX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_SLAVE_RX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_SLAVE_RX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_LISTEN_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_LISTEN_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_MEM_TX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_MEM_TX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_MEM_RX_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_MEM_RX_CPLT_CB]();
+  }
+}
+
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_ERROR_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_ERROR_CB]();
+  }
+}
+
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) {
+  BSP_I2C_t bsp_i2c = I2C_Get(hi2c);
+  if (bsp_i2c != BSP_I2C_ERR) {
+    if (I2C_Callback[bsp_i2c][HAL_I2C_ABORT_CPLT_CB])
+      I2C_Callback[bsp_i2c][HAL_I2C_ABORT_CPLT_CB]();
+  }
+}
+
+/* Exported functions ------------------------------------------------------- */
+I2C_HandleTypeDef *BSP_I2C_GetHandle(BSP_I2C_t i2c) {
+  switch (i2c) {
+    case BSP_I2C_2:
+      return &hi2c2;
+    default:
+      return NULL;
+  }
+}
+
+int8_t BSP_I2C_RegisterCallback(BSP_I2C_t i2c, BSP_I2C_Callback_t type,
+                                void (*callback)(void)) {
+  if (callback == NULL) return BSP_ERR_NULL;
+  I2C_Callback[i2c][type] = callback;
+  return BSP_OK;
+}
+
+int8_t BSP_I2C_Transmit(BSP_I2C_t i2c, uint16_t devAddr, uint8_t *data,
+                        uint16_t size, bool dma) {
+  if (i2c >= BSP_I2C_NUM) return BSP_ERR;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_I2C_Master_Transmit_DMA(hi2c, devAddr, data, size);
+  } else {
+    return HAL_I2C_Master_Transmit(hi2c, devAddr, data, size, 10);
+  }
+}
+
+int8_t BSP_I2C_Receive(BSP_I2C_t i2c, uint16_t devAddr, uint8_t *data,
+                       uint16_t size, bool dma) {
+  if (i2c >= BSP_I2C_NUM) return BSP_ERR;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_I2C_Master_Receive_DMA(hi2c, devAddr, data, size);
+  } else {
+    return HAL_I2C_Master_Receive(hi2c, devAddr, data, size, 10);
+  }
+}
+
+uint8_t BSP_I2C_MemReadByte(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr) {
+  if (i2c >= BSP_I2C_NUM) return 0xFF;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return 0xFF;
+
+  uint8_t data;
+  HAL_I2C_Mem_Read(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, &data, 1, HAL_MAX_DELAY);
+  return data;
+}
+
+int8_t BSP_I2C_MemWriteByte(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                            uint8_t data) {
+  if (i2c >= BSP_I2C_NUM) return BSP_ERR;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return BSP_ERR;
+
+  return HAL_I2C_Mem_Write(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, &data, 1, HAL_MAX_DELAY);
+}
+
+int8_t BSP_I2C_MemRead(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                       uint8_t *data, uint16_t size, bool dma) {
+  if (i2c >= BSP_I2C_NUM || data == NULL || size == 0) return BSP_ERR;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_I2C_Mem_Read_DMA(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, data, size);
+  }
+  else {
+    return HAL_I2C_Mem_Read(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, data, size, HAL_MAX_DELAY);
+  }
+}
+
+
+int8_t BSP_I2C_MemWrite(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                        uint8_t *data, uint16_t size, bool dma) {
+  if (i2c >= BSP_I2C_NUM || data == NULL || size == 0) return BSP_ERR;
+  I2C_HandleTypeDef *hi2c = BSP_I2C_GetHandle(i2c);
+  if (hi2c == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_I2C_Mem_Write_DMA(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, data, size);
+  } else {
+    return HAL_I2C_Mem_Write(hi2c, devAddr, memAddr, I2C_MEMADD_SIZE_16BIT, data, size, HAL_MAX_DELAY);
+  }
+}
\ No newline at end of file
diff --git a/User/bsp/i2c.h b/User/bsp/i2c.h
new file mode 100644
index 0000000..fa9a881
--- /dev/null
+++ b/User/bsp/i2c.h
@@ -0,0 +1,78 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+
+/* 要添加使用I2C的新设备，需要先在此添加对应的枚举值 */
+
+/* I2C实体枚举，与设备对应 */
+typedef enum {
+  BSP_I2C_2,
+  /* USER BSP_I2C BEGIN*/
+  /* USER_I2C_XXX */
+  /* USER BSP_I2C END */
+  BSP_I2C_NUM,
+  BSP_I2C_ERR,
+} BSP_I2C_t;
+
+/* I2C支持的中断回调函数类型*/
+typedef enum {
+  HAL_I2C_MASTER_TX_CPLT_CB,
+  HAL_I2C_MASTER_RX_CPLT_CB,
+  HAL_I2C_SLAVE_TX_CPLT_CB,
+  HAL_I2C_SLAVE_RX_CPLT_CB,
+  HAL_I2C_LISTEN_CPLT_CB,
+  HAL_I2C_MEM_TX_CPLT_CB,
+  HAL_I2C_MEM_RX_CPLT_CB,
+  HAL_I2C_ERROR_CB,
+  HAL_I2C_ABORT_CPLT_CB,
+  BSP_I2C_CB_NUM,
+} BSP_I2C_Callback_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+I2C_HandleTypeDef *BSP_I2C_GetHandle(BSP_I2C_t i2c);
+int8_t BSP_I2C_RegisterCallback(BSP_I2C_t i2c, BSP_I2C_Callback_t type,
+                                void (*callback)(void));
+
+int8_t BSP_I2C_Transmit(BSP_I2C_t i2c, uint16_t devAddr, uint8_t *data,
+                        uint16_t size, bool dma);
+int8_t BSP_I2C_Receive(BSP_I2C_t i2c, uint16_t devAddr, uint8_t *data,
+                       uint16_t size, bool dma);
+
+
+uint8_t BSP_I2C_MemReadByte(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr);
+int8_t BSP_I2C_MemWriteByte(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                            uint8_t data);
+
+int8_t BSP_I2C_MemRead(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                       uint8_t *data, uint16_t size, bool dma);
+int8_t BSP_I2C_MemWrite(BSP_I2C_t i2c, uint16_t devAddr, uint16_t memAddr,
+                        uint8_t *data, uint16_t size, bool dma);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/mm.c b/User/bsp/mm.c
new file mode 100644
index 0000000..13d20c0
--- /dev/null
+++ b/User/bsp/mm.c
@@ -0,0 +1,30 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/mm.h"
+
+#include "FreeRTOS.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private function  -------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+inline void *BSP_Malloc(size_t size) { return pvPortMalloc(size); }
+
+inline void BSP_Free(void *pv) { vPortFree(pv); }
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/bsp/mm.h b/User/bsp/mm.h
new file mode 100644
index 0000000..d24634e
--- /dev/null
+++ b/User/bsp/mm.h
@@ -0,0 +1,32 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+/* Exported functions prototypes -------------------------------------------- */
+void *BSP_Malloc(size_t size);
+void BSP_Free(void *pv);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/pwm.c b/User/bsp/pwm.c
new file mode 100644
index 0000000..743e791
--- /dev/null
+++ b/User/bsp/pwm.c
@@ -0,0 +1,110 @@
+/* Includes ----------------------------------------------------------------- */
+#include "tim.h"
+#include "bsp/pwm.h"
+#include "bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+typedef struct {
+  TIM_HandleTypeDef *tim;
+  uint16_t channel;
+} BSP_PWM_Config_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static const BSP_PWM_Config_t PWM_Map[BSP_PWM_NUM] = {
+  {&htim10, TIM_CHANNEL_1},
+};
+
+/* Private function  -------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+
+int8_t BSP_PWM_Start(BSP_PWM_Channel_t ch) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  
+  HAL_TIM_PWM_Start(PWM_Map[ch].tim, PWM_Map[ch].channel);
+  return BSP_OK;
+}
+
+int8_t BSP_PWM_SetComp(BSP_PWM_Channel_t ch, float duty_cycle) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  
+  if (duty_cycle > 1.0f) {
+    duty_cycle = 1.0f;
+  }
+  if (duty_cycle < 0.0f) {
+    duty_cycle = 0.0f;
+  }
+  // 获取ARR值（周期值）
+  uint32_t arr = __HAL_TIM_GET_AUTORELOAD(PWM_Map[ch].tim);
+  
+  // 计算比较值：CCR = duty_cycle * (ARR + 1)
+  uint32_t ccr = (uint32_t)(duty_cycle * (arr + 1));
+  
+  __HAL_TIM_SET_COMPARE(PWM_Map[ch].tim, PWM_Map[ch].channel, ccr);
+
+  return BSP_OK;
+}
+
+int8_t BSP_PWM_SetFreq(BSP_PWM_Channel_t ch, float freq) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+
+  uint32_t timer_clock = HAL_RCC_GetPCLK1Freq(); // Get the timer clock frequency
+  uint32_t prescaler = PWM_Map[ch].tim->Init.Prescaler;
+  uint32_t period = (timer_clock / (prescaler + 1)) / freq - 1;
+  
+  if (period > UINT16_MAX) {
+    return BSP_ERR; // Frequency too low
+  }
+  __HAL_TIM_SET_AUTORELOAD(PWM_Map[ch].tim, period);
+  
+  return BSP_OK;
+}
+
+int8_t BSP_PWM_Stop(BSP_PWM_Channel_t ch) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  
+  HAL_TIM_PWM_Stop(PWM_Map[ch].tim, PWM_Map[ch].channel);
+  return BSP_OK;
+}
+
+uint32_t BSP_PWM_GetAutoReloadPreload(BSP_PWM_Channel_t ch) {
+    if (ch >= BSP_PWM_NUM) return BSP_ERR;
+    return PWM_Map[ch].tim->Init.AutoReloadPreload;  
+}
+
+TIM_HandleTypeDef* BSP_PWM_GetHandle(BSP_PWM_Channel_t ch) {
+  return PWM_Map[ch].tim;
+}
+
+
+uint16_t BSP_PWM_GetChannel(BSP_PWM_Channel_t ch) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  return PWM_Map[ch].channel;
+}
+
+int8_t BSP_PWM_Start_DMA(BSP_PWM_Channel_t ch, uint32_t *pData, uint16_t Length) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  
+  HAL_TIM_PWM_Start_DMA(PWM_Map[ch].tim, PWM_Map[ch].channel, pData, Length);
+  return BSP_OK;
+}
+
+int8_t BSP_PWM_Stop_DMA(BSP_PWM_Channel_t ch) {
+  if (ch >= BSP_PWM_NUM) return BSP_ERR;
+  
+  HAL_TIM_PWM_Stop_DMA(PWM_Map[ch].tim, PWM_Map[ch].channel);
+  return BSP_OK;
+}
\ No newline at end of file
diff --git a/User/bsp/pwm.h b/User/bsp/pwm.h
new file mode 100644
index 0000000..b472d48
--- /dev/null
+++ b/User/bsp/pwm.h
@@ -0,0 +1,48 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "tim.h"
+#include "bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+/* PWM通道 */
+typedef enum {
+  BSP_PWM_IMU_HEAT,
+  BSP_PWM_NUM,
+  BSP_PWM_ERR,
+} BSP_PWM_Channel_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t BSP_PWM_Start(BSP_PWM_Channel_t ch);
+int8_t BSP_PWM_SetComp(BSP_PWM_Channel_t ch, float duty_cycle);
+int8_t BSP_PWM_SetFreq(BSP_PWM_Channel_t ch, float freq);
+int8_t BSP_PWM_Stop(BSP_PWM_Channel_t ch);
+uint32_t BSP_PWM_GetAutoReloadPreload(BSP_PWM_Channel_t ch);
+uint16_t BSP_PWM_GetChannel(BSP_PWM_Channel_t ch);
+TIM_HandleTypeDef* BSP_PWM_GetHandle(BSP_PWM_Channel_t ch);
+int8_t BSP_PWM_Start_DMA(BSP_PWM_Channel_t ch, uint32_t *pData, uint16_t Length);
+int8_t BSP_PWM_Stop_DMA(BSP_PWM_Channel_t ch);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/bsp/spi.c b/User/bsp/spi.c
new file mode 100644
index 0000000..d8ac00e
--- /dev/null
+++ b/User/bsp/spi.c
@@ -0,0 +1,181 @@
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "bsp/spi.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static void (*SPI_Callback[BSP_SPI_NUM][BSP_SPI_CB_NUM])(void);
+
+/* Private function  -------------------------------------------------------- */
+static BSP_SPI_t SPI_Get(SPI_HandleTypeDef *hspi) {
+  if (hspi->Instance == SPI1)
+    return BSP_SPI_BMI088;
+  else
+    return BSP_SPI_ERR;
+}
+
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[bsp_spi][BSP_SPI_TX_CPLT_CB]) {
+      SPI_Callback[bsp_spi][BSP_SPI_TX_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_RX_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_RX_CPLT_CB]();
+  }
+}
+
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_RX_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_RX_CPLT_CB]();
+  }
+}
+
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_HALF_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_HALF_CPLT_CB]();
+  }
+}
+
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_RX_HALF_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_RX_HALF_CPLT_CB]();
+  }
+}
+
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_RX_HALF_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_TX_RX_HALF_CPLT_CB]();
+  }
+}
+
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_ERROR_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_ERROR_CB]();
+  }
+}
+
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) {
+  BSP_SPI_t bsp_spi = SPI_Get(hspi);
+  if (bsp_spi != BSP_SPI_ERR) {
+    if (SPI_Callback[SPI_Get(hspi)][BSP_SPI_ABORT_CPLT_CB])
+      SPI_Callback[SPI_Get(hspi)][BSP_SPI_ABORT_CPLT_CB]();
+  }
+}
+
+/* Exported functions ------------------------------------------------------- */
+SPI_HandleTypeDef *BSP_SPI_GetHandle(BSP_SPI_t spi) {
+  switch (spi) {
+    case BSP_SPI_BMI088:
+      return &hspi1;
+    default:
+      return NULL;
+  }
+}
+
+int8_t BSP_SPI_RegisterCallback(BSP_SPI_t spi, BSP_SPI_Callback_t type,
+                                void (*callback)(void)) {
+  if (callback == NULL) return BSP_ERR_NULL;
+  SPI_Callback[spi][type] = callback;
+  return BSP_OK;
+}
+
+int8_t BSP_SPI_Transmit(BSP_SPI_t spi, uint8_t *data, uint16_t size, bool dma) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  SPI_HandleTypeDef *hspi = BSP_SPI_GetHandle(spi);
+  if (hspi == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_SPI_Transmit_DMA(hspi, data, size)!= HAL_OK;;
+  } else {
+    return HAL_SPI_Transmit(hspi, data, size, 20)!= HAL_OK;;
+  }
+}
+
+int8_t BSP_SPI_Receive(BSP_SPI_t spi, uint8_t *data, uint16_t size, bool dma) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  SPI_HandleTypeDef *hspi = BSP_SPI_GetHandle(spi);
+  if (hspi == NULL) return BSP_ERR;
+
+  if (dma) {
+    return HAL_SPI_Receive_DMA(hspi, data, size)!= HAL_OK;;
+  } else {
+    return HAL_SPI_Receive(hspi, data, size, 20)!= HAL_OK;;
+  }
+}
+
+int8_t BSP_SPI_TransmitReceive(BSP_SPI_t spi, uint8_t *txData, uint8_t *rxData,
+                               uint16_t size, bool dma) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  SPI_HandleTypeDef *hspi = BSP_SPI_GetHandle(spi);
+  if (hspi == NULL) return BSP_ERR;
+  
+  if (dma) {
+    return HAL_SPI_TransmitReceive_DMA(hspi, txData, rxData, size)!= HAL_OK;;
+  } else {
+    return HAL_SPI_TransmitReceive(hspi, txData, rxData, size, 20)!= HAL_OK;;
+  }
+}
+
+uint8_t BSP_SPI_MemReadByte(BSP_SPI_t spi, uint8_t reg) {
+  if (spi >= BSP_SPI_NUM) return 0xFF;
+  uint8_t tmp[2] = {reg | 0x80, 0x00};
+  BSP_SPI_TransmitReceive(spi, tmp, tmp, 2u, true);
+  return tmp[1];
+}
+
+int8_t BSP_SPI_MemWriteByte(BSP_SPI_t spi, uint8_t reg, uint8_t data) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  uint8_t tmp[2] = {reg & 0x7f, data};
+  return BSP_SPI_Transmit(spi, tmp, 2u, true);
+}
+
+int8_t BSP_SPI_MemRead(BSP_SPI_t spi, uint8_t reg, uint8_t *data, uint16_t size) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  if (data == NULL || size == 0) return BSP_ERR_NULL;
+  reg = reg | 0x80;
+  BSP_SPI_Transmit(spi, ®, 1u, true);
+  return BSP_SPI_Receive(spi, data, size, true);
+}
+
+int8_t BSP_SPI_MemWrite(BSP_SPI_t spi, uint8_t reg, uint8_t *data, uint16_t size) {
+  if (spi >= BSP_SPI_NUM) return BSP_ERR;
+  if (data == NULL || size == 0) return BSP_ERR_NULL;
+  reg = reg & 0x7f;
+  BSP_SPI_Transmit(spi, ®, 1u, true);
+  return BSP_SPI_Transmit(spi, data, size, true);
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/bsp/spi.h b/User/bsp/spi.h
new file mode 100644
index 0000000..2abb0c6
--- /dev/null
+++ b/User/bsp/spi.h
@@ -0,0 +1,70 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+
+/* 要添加使用SPI的新设备，需要先在此添加对应的枚举值 */
+
+/* SPI实体枚举，与设备对应 */
+typedef enum {
+  BSP_SPI_BMI088,
+  BSP_SPI_NUM,
+  BSP_SPI_ERR,
+} BSP_SPI_t;
+
+/* SPI支持的中断回调函数类型，具体参考HAL中定义 */
+typedef enum {
+  BSP_SPI_TX_CPLT_CB,
+  BSP_SPI_RX_CPLT_CB,
+  BSP_SPI_TX_RX_CPLT_CB,
+  BSP_SPI_TX_HALF_CPLT_CB,
+  BSP_SPI_RX_HALF_CPLT_CB,
+  BSP_SPI_TX_RX_HALF_CPLT_CB,
+  BSP_SPI_ERROR_CB,
+  BSP_SPI_ABORT_CPLT_CB,
+  BSP_SPI_CB_NUM,
+} BSP_SPI_Callback_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+SPI_HandleTypeDef *BSP_SPI_GetHandle(BSP_SPI_t spi);
+int8_t BSP_SPI_RegisterCallback(BSP_SPI_t spi, BSP_SPI_Callback_t type,
+                                void (*callback)(void));
+
+
+int8_t BSP_SPI_Transmit(BSP_SPI_t spi, uint8_t *data, uint16_t size, bool dma);
+int8_t BSP_SPI_Receive(BSP_SPI_t spi, uint8_t *data, uint16_t size, bool dma);
+int8_t BSP_SPI_TransmitReceive(BSP_SPI_t spi, uint8_t *txData, uint8_t *rxData,
+                               uint16_t size, bool dma);
+
+uint8_t BSP_SPI_MemReadByte(BSP_SPI_t spi, uint8_t reg);
+int8_t BSP_SPI_MemWriteByte(BSP_SPI_t spi, uint8_t reg, uint8_t data);
+int8_t BSP_SPI_MemRead(BSP_SPI_t spi, uint8_t reg, uint8_t *data, uint16_t size);
+int8_t BSP_SPI_MemWrite(BSP_SPI_t spi, uint8_t reg, uint8_t *data, uint16_t size);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/time.c b/User/bsp/time.c
new file mode 100644
index 0000000..21918ed
--- /dev/null
+++ b/User/bsp/time.c
@@ -0,0 +1,81 @@
+/* Includes ----------------------------------------------------------------- */
+#include "bsp/time.h"
+#include "bsp.h"
+
+#include 
+#include "FreeRTOS.h"
+#include "main.h"
+#include "task.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+/* Private function  -------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+
+uint32_t BSP_TIME_Get_ms() { return xTaskGetTickCount(); }
+
+uint64_t BSP_TIME_Get_us() {
+  uint32_t tick_freq = osKernelGetTickFreq();
+  uint32_t ticks_old = xTaskGetTickCount()*(1000/tick_freq);
+  uint32_t tick_value_old = SysTick->VAL;
+  uint32_t ticks_new = xTaskGetTickCount()*(1000/tick_freq);
+  uint32_t tick_value_new = SysTick->VAL;
+  if (ticks_old == ticks_new) {
+    return ticks_new * 1000 + 1000 - tick_value_old * 1000 / (SysTick->LOAD + 1);
+  } else {
+    return ticks_new * 1000 + 1000 - tick_value_new * 1000 / (SysTick->LOAD + 1);
+  }
+}
+
+uint64_t BSP_TIME_Get() __attribute__((alias("BSP_TIME_Get_us")));
+
+int8_t BSP_TIME_Delay_ms(uint32_t ms) {
+  uint32_t tick_period = 1000u / osKernelGetTickFreq();
+  uint32_t ticks = ms / tick_period;
+
+  switch (osKernelGetState()) {
+    case osKernelError:
+    case osKernelReserved:
+    case osKernelLocked:
+    case osKernelSuspended:
+      return BSP_ERR;
+
+    case osKernelRunning:
+      osDelay(ticks ? ticks : 1);
+      break;
+
+    case osKernelInactive:
+    case osKernelReady:
+      HAL_Delay(ms);
+      break;
+  }
+  return BSP_OK;
+}
+
+/*阻塞us延迟*/
+int8_t BSP_TIME_Delay_us(uint32_t us) {
+    uint64_t start = BSP_TIME_Get_us();
+    while (BSP_TIME_Get_us() - start < us) {
+        // 等待us时间
+    }
+    return BSP_OK;
+}
+
+int8_t BSP_TIME_Delay(uint32_t ms) __attribute__((alias("BSP_TIME_Delay_ms")));
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/bsp/time.h b/User/bsp/time.h
new file mode 100644
index 0000000..c69085b
--- /dev/null
+++ b/User/bsp/time.h
@@ -0,0 +1,43 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+/* Exported functions prototypes -------------------------------------------- */
+uint32_t BSP_TIME_Get_ms();
+
+uint64_t BSP_TIME_Get_us();
+
+uint64_t BSP_TIME_Get();
+
+int8_t BSP_TIME_Delay_ms(uint32_t ms);
+
+/*微秒阻塞延时，一般别用*/
+int8_t BSP_TIME_Delay_us(uint32_t us);
+
+int8_t BSP_TIME_Delay(uint32_t ms);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/bsp/uart.c b/User/bsp/uart.c
new file mode 100644
index 0000000..45e95b4
--- /dev/null
+++ b/User/bsp/uart.c
@@ -0,0 +1,167 @@
+/* Includes ----------------------------------------------------------------- */
+#include 
+
+#include "bsp/uart.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static void (*UART_Callback[BSP_UART_NUM][BSP_UART_CB_NUM])(void);
+
+/* Private function  -------------------------------------------------------- */
+static BSP_UART_t UART_Get(UART_HandleTypeDef *huart) {
+  if (huart->Instance == USART1)
+    return BSP_UART_1;
+  else if (huart->Instance == USART1)
+    return BSP_UART_2;
+  else if (huart->Instance == USART6)
+    return BSP_UART_AI;
+  else if (huart->Instance == USART3)
+    return BSP_UART_3;
+  else
+    return BSP_UART_ERR;
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_TX_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_TX_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_TX_HALF_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_TX_HALF_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_RX_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_RX_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_RX_HALF_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_RX_HALF_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_ERROR_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_ERROR_CB]();
+    }
+  }
+}
+
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_ABORT_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_ABORT_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_ABORT_TX_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_ABORT_TX_CPLT_CB]();
+    }
+  }
+}
+
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) {
+  BSP_UART_t bsp_uart = UART_Get(huart);
+  if (bsp_uart != BSP_UART_ERR) {
+    if (UART_Callback[bsp_uart][BSP_UART_ABORT_RX_CPLT_CB]) {
+      UART_Callback[bsp_uart][BSP_UART_ABORT_RX_CPLT_CB]();
+    }
+  }
+}
+
+/* Exported functions ------------------------------------------------------- */
+void BSP_UART_IRQHandler(UART_HandleTypeDef *huart) {
+  if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) {
+    __HAL_UART_CLEAR_IDLEFLAG(huart);
+    if (UART_Callback[UART_Get(huart)][BSP_UART_IDLE_LINE_CB]) {
+      UART_Callback[UART_Get(huart)][BSP_UART_IDLE_LINE_CB]();
+    }
+  }
+}
+
+UART_HandleTypeDef *BSP_UART_GetHandle(BSP_UART_t uart) {
+  switch (uart) {
+    case BSP_UART_1:
+      return &huart1;
+    case BSP_UART_2:
+      return &huart1;
+    case BSP_UART_AI:
+      return &huart6;
+    case BSP_UART_3:
+      return &huart3;
+    default:
+      return NULL;
+  }
+}
+
+int8_t BSP_UART_RegisterCallback(BSP_UART_t uart, BSP_UART_Callback_t type,
+                                 void (*callback)(void)) {
+  if (callback == NULL) return BSP_ERR_NULL;
+  if (uart >= BSP_UART_NUM || type >= BSP_UART_CB_NUM) return BSP_ERR;
+  UART_Callback[uart][type] = callback;
+  return BSP_OK;
+}
+
+int8_t BSP_UART_Transmit(BSP_UART_t uart, uint8_t *data, uint16_t size, bool dma) {
+  if (uart >= BSP_UART_NUM) return BSP_ERR;
+  if (data == NULL || size == 0) return BSP_ERR_NULL;
+
+  if (dma) {
+    return HAL_UART_Transmit_DMA(BSP_UART_GetHandle(uart), data, size);
+  } else {
+    return HAL_UART_Transmit_IT(BSP_UART_GetHandle(uart), data, size);
+  }
+}
+
+int8_t BSP_UART_Receive(BSP_UART_t uart, uint8_t *data, uint16_t size, bool dma) {
+  if (uart >= BSP_UART_NUM) return BSP_ERR;
+  if (data == NULL || size == 0) return BSP_ERR_NULL;
+
+  if (dma) {
+    return HAL_UART_Receive_DMA(BSP_UART_GetHandle(uart), data, size);
+  } else {
+    return HAL_UART_Receive_IT(BSP_UART_GetHandle(uart), data, size);
+  }
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/bsp/uart.h b/User/bsp/uart.h
new file mode 100644
index 0000000..209fe98
--- /dev/null
+++ b/User/bsp/uart.h
@@ -0,0 +1,71 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include 
+
+#include "bsp/bsp.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported types ----------------------------------------------------------- */
+
+/* 要添加使用UART的新设备，需要先在此添加对应的枚举值 */
+
+/* UART实体枚举，与设备对应 */
+typedef enum {
+  BSP_UART_1,
+  BSP_UART_2,
+  BSP_UART_AI,
+  BSP_UART_3,
+  BSP_UART_NUM,
+  BSP_UART_ERR,
+} BSP_UART_t;
+
+/* UART支持的中断回调函数类型，具体参考HAL中定义 */
+typedef enum {
+  BSP_UART_TX_HALF_CPLT_CB,
+  BSP_UART_TX_CPLT_CB,
+  BSP_UART_RX_HALF_CPLT_CB,
+  BSP_UART_RX_CPLT_CB,
+  BSP_UART_ERROR_CB,
+  BSP_UART_ABORT_CPLT_CB,
+  BSP_UART_ABORT_TX_CPLT_CB,
+  BSP_UART_ABORT_RX_CPLT_CB,
+
+  BSP_UART_IDLE_LINE_CB,
+  BSP_UART_CB_NUM,
+} BSP_UART_Callback_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+UART_HandleTypeDef *BSP_UART_GetHandle(BSP_UART_t uart);
+
+void BSP_UART_IRQHandler(UART_HandleTypeDef *huart);
+
+int8_t BSP_UART_RegisterCallback(BSP_UART_t uart, BSP_UART_Callback_t type,
+                                 void (*callback)(void));
+
+int8_t BSP_UART_Transmit(BSP_UART_t uart, uint8_t *data, uint16_t size, bool dma);
+int8_t BSP_UART_Receive(BSP_UART_t uart, uint8_t *data, uint16_t size, bool dma);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/ahrs.c b/User/component/ahrs.c
new file mode 100644
index 0000000..ffdb870
--- /dev/null
+++ b/User/component/ahrs.c
@@ -0,0 +1,417 @@
+/*
+  开源的AHRS算法。
+  MadgwickAHRS
+*/
+
+#include "ahrs.h"
+
+#include 
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define BETA_IMU (0.033f)
+#define BETA_AHRS (0.041f)
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 2 * proportional gain (Kp) */
+static float beta = BETA_IMU;
+
+/**
+ * @brief 不使用磁力计计算姿态
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @return int8_t 0对应没有错误
+ */
+static int8_t AHRS_UpdateIMU(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                             const AHRS_Gyro_t *gyro) {
+  if (ahrs == NULL) return -1;
+  if (accl == NULL) return -1;
+  if (gyro == NULL) return -1;
+
+  beta = BETA_IMU;
+
+  float ax = accl->x;
+  float ay = accl->y;
+  float az = accl->z;
+
+  float gx = gyro->x;
+  float gy = gyro->y;
+  float gz = gyro->z;
+
+  float recip_norm;
+  float s0, s1, s2, s3;
+  float q_dot1, q_dot2, q_dot3, q_dot4;
+  float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2, _8q1, _8q2, q0q0, q1q1, q2q2,
+      q3q3;
+
+  /* Rate of change of quaternion from gyroscope */
+  q_dot1 = 0.5f * (-ahrs->quat.q1 * gx - ahrs->quat.q2 * gy -
+                   ahrs->quat.q3 * gz);
+  q_dot2 = 0.5f * (ahrs->quat.q0 * gx + ahrs->quat.q2 * gz -
+                   ahrs->quat.q3 * gy);
+  q_dot3 = 0.5f * (ahrs->quat.q0 * gy - ahrs->quat.q1 * gz +
+                   ahrs->quat.q3 * gx);
+  q_dot4 = 0.5f * (ahrs->quat.q0 * gz + ahrs->quat.q1 * gy -
+                   ahrs->quat.q2 * gx);
+
+  /* Compute feedback only if accelerometer measurement valid (avoids NaN in
+   * accelerometer normalisation) */
+  if (!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
+    /* Normalise accelerometer measurement */
+    recip_norm = InvSqrt(ax * ax + ay * ay + az * az);
+    ax *= recip_norm;
+    ay *= recip_norm;
+    az *= recip_norm;
+
+    /* Auxiliary variables to avoid repeated arithmetic */
+    _2q0 = 2.0f * ahrs->quat.q0;
+    _2q1 = 2.0f * ahrs->quat.q1;
+    _2q2 = 2.0f * ahrs->quat.q2;
+    _2q3 = 2.0f * ahrs->quat.q3;
+    _4q0 = 4.0f * ahrs->quat.q0;
+    _4q1 = 4.0f * ahrs->quat.q1;
+    _4q2 = 4.0f * ahrs->quat.q2;
+    _8q1 = 8.0f * ahrs->quat.q1;
+    _8q2 = 8.0f * ahrs->quat.q2;
+    q0q0 = ahrs->quat.q0 * ahrs->quat.q0;
+    q1q1 = ahrs->quat.q1 * ahrs->quat.q1;
+    q2q2 = ahrs->quat.q2 * ahrs->quat.q2;
+    q3q3 = ahrs->quat.q3 * ahrs->quat.q3;
+
+    /* Gradient decent algorithm corrective step */
+    s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay;
+    s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * ahrs->quat.q1 -
+         _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az;
+    s2 = 4.0f * q0q0 * ahrs->quat.q2 + _2q0 * ax + _4q2 * q3q3 -
+         _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az;
+    s3 = 4.0f * q1q1 * ahrs->quat.q3 - _2q1 * ax +
+         4.0f * q2q2 * ahrs->quat.q3 - _2q2 * ay;
+
+    /* normalise step magnitude */
+    recip_norm = InvSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3);
+
+    s0 *= recip_norm;
+    s1 *= recip_norm;
+    s2 *= recip_norm;
+    s3 *= recip_norm;
+
+    /* Apply feedback step */
+    q_dot1 -= beta * s0;
+    q_dot2 -= beta * s1;
+    q_dot3 -= beta * s2;
+    q_dot4 -= beta * s3;
+  }
+
+  /* Integrate rate of change of quaternion to yield quaternion */
+  ahrs->quat.q0 += q_dot1 * ahrs->inv_sample_freq;
+  ahrs->quat.q1 += q_dot2 * ahrs->inv_sample_freq;
+  ahrs->quat.q2 += q_dot3 * ahrs->inv_sample_freq;
+  ahrs->quat.q3 += q_dot4 * ahrs->inv_sample_freq;
+
+  /* Normalise quaternion */
+  recip_norm = InvSqrt(ahrs->quat.q0 * ahrs->quat.q0 +
+                       ahrs->quat.q1 * ahrs->quat.q1 +
+                       ahrs->quat.q2 * ahrs->quat.q2 +
+                       ahrs->quat.q3 * ahrs->quat.q3);
+  ahrs->quat.q0 *= recip_norm;
+  ahrs->quat.q1 *= recip_norm;
+  ahrs->quat.q2 *= recip_norm;
+  ahrs->quat.q3 *= recip_norm;
+
+  return 0;
+}
+
+/**
+ * @brief 初始化姿态解算
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param magn 磁力计数据
+ * @param sample_freq 采样频率
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Init(AHRS_t *ahrs, const AHRS_Magn_t *magn, float sample_freq) {
+  if (ahrs == NULL) return -1;
+
+  ahrs->inv_sample_freq = 1.0f / sample_freq;
+
+  ahrs->quat.q0 = 1.0f;
+  ahrs->quat.q1 = 0.0f;
+  ahrs->quat.q2 = 0.0f;
+  ahrs->quat.q3 = 0.0f;
+
+  if (magn) {
+    float yaw = -atan2(magn->y, magn->x);
+
+    if ((magn->x == 0.0f) && (magn->y == 0.0f) && (magn->z == 0.0f)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < (M_PI / 2.0f)) || (yaw > 0.0f)) {
+      ahrs->quat.q0 = 0.997458339f;
+      ahrs->quat.q1 = 0.000336312107f;
+      ahrs->quat.q2 = -0.0057230792f;
+      ahrs->quat.q3 = 0.0740156546;
+
+    } else if ((yaw < M_PI) || (yaw > (M_PI / 2.0f))) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < 90.0f) || (yaw > M_PI)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < 90.0f) || (yaw > 0.0f)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+    }
+  }
+  return 0;
+}
+
+/**
+ * @brief 姿态运算更新一次
+ * @note 输入数据必须是NED(North East Down) 参考坐标系
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @param magn 磁力计数据
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Update(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                   const AHRS_Gyro_t *gyro, const AHRS_Magn_t *magn) {
+  if (ahrs == NULL) return -1;
+  if (accl == NULL) return -1;
+  if (gyro == NULL) return -1;
+
+  beta = BETA_AHRS;
+
+  float recip_norm;
+  float s0, s1, s2, s3;
+  float q_dot1, q_dot2, q_dot3, q_dot4;
+  float hx, hy;
+  float _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1,
+      _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3,
+      q2q2, q2q3, q3q3;
+
+  if (magn == NULL) return AHRS_UpdateIMU(ahrs, accl, gyro);
+
+  float mx = magn->x;
+  float my = magn->y;
+  float mz = magn->z;
+
+  /* Use IMU algorithm if magnetometer measurement invalid (avoids NaN in */
+  /* magnetometer normalisation) */
+  if ((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) {
+    return AHRS_UpdateIMU(ahrs, accl, gyro);
+  }
+
+  float ax = accl->x;
+  float ay = accl->y;
+  float az = accl->z;
+
+  float gx = gyro->x;
+  float gy = gyro->y;
+  float gz = gyro->z;
+
+  /* Rate of change of quaternion from gyroscope */
+  q_dot1 = 0.5f * (-ahrs->quat.q1 * gx - ahrs->quat.q2 * gy -
+                   ahrs->quat.q3 * gz);
+  q_dot2 = 0.5f * (ahrs->quat.q0 * gx + ahrs->quat.q2 * gz -
+                   ahrs->quat.q3 * gy);
+  q_dot3 = 0.5f * (ahrs->quat.q0 * gy - ahrs->quat.q1 * gz +
+                   ahrs->quat.q3 * gx);
+  q_dot4 = 0.5f * (ahrs->quat.q0 * gz + ahrs->quat.q1 * gy -
+                   ahrs->quat.q2 * gx);
+
+  /* Compute feedback only if accelerometer measurement valid (avoids NaN in
+   * accelerometer normalisation) */
+  if (!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
+    /* Normalise accelerometer measurement */
+    recip_norm = InvSqrt(ax * ax + ay * ay + az * az);
+    ax *= recip_norm;
+    ay *= recip_norm;
+    az *= recip_norm;
+
+    /* Normalise magnetometer measurement */
+    recip_norm = InvSqrt(mx * mx + my * my + mz * mz);
+    mx *= recip_norm;
+    my *= recip_norm;
+    mz *= recip_norm;
+
+    /* Auxiliary variables to avoid repeated arithmetic */
+    _2q0mx = 2.0f * ahrs->quat.q0 * mx;
+    _2q0my = 2.0f * ahrs->quat.q0 * my;
+    _2q0mz = 2.0f * ahrs->quat.q0 * mz;
+    _2q1mx = 2.0f * ahrs->quat.q1 * mx;
+    _2q0 = 2.0f * ahrs->quat.q0;
+    _2q1 = 2.0f * ahrs->quat.q1;
+    _2q2 = 2.0f * ahrs->quat.q2;
+    _2q3 = 2.0f * ahrs->quat.q3;
+    _2q0q2 = 2.0f * ahrs->quat.q0 * ahrs->quat.q2;
+    _2q2q3 = 2.0f * ahrs->quat.q2 * ahrs->quat.q3;
+    q0q0 = ahrs->quat.q0 * ahrs->quat.q0;
+    q0q1 = ahrs->quat.q0 * ahrs->quat.q1;
+    q0q2 = ahrs->quat.q0 * ahrs->quat.q2;
+    q0q3 = ahrs->quat.q0 * ahrs->quat.q3;
+    q1q1 = ahrs->quat.q1 * ahrs->quat.q1;
+    q1q2 = ahrs->quat.q1 * ahrs->quat.q2;
+    q1q3 = ahrs->quat.q1 * ahrs->quat.q3;
+    q2q2 = ahrs->quat.q2 * ahrs->quat.q2;
+    q2q3 = ahrs->quat.q2 * ahrs->quat.q3;
+    q3q3 = ahrs->quat.q3 * ahrs->quat.q3;
+
+    /* Reference direction of Earth's magnetic field */
+    hx = mx * q0q0 - _2q0my * ahrs->quat.q3 +
+         _2q0mz * ahrs->quat.q2 + mx * q1q1 +
+         _2q1 * my * ahrs->quat.q2 + _2q1 * mz * ahrs->quat.q3 -
+         mx * q2q2 - mx * q3q3;
+    hy = _2q0mx * ahrs->quat.q3 + my * q0q0 -
+         _2q0mz * ahrs->quat.q1 + _2q1mx * ahrs->quat.q2 -
+         my * q1q1 + my * q2q2 + _2q2 * mz * ahrs->quat.q3 - my * q3q3;
+    // _2bx = sqrtf(hx * hx + hy * hy);
+    // 改为invsqrt
+    _2bx = 1.f / InvSqrt(hx * hx + hy * hy);
+    _2bz = -_2q0mx * ahrs->quat.q2 + _2q0my * ahrs->quat.q1 +
+           mz * q0q0 + _2q1mx * ahrs->quat.q3 - mz * q1q1 +
+           _2q2 * my * ahrs->quat.q3 - mz * q2q2 + mz * q3q3;
+    _4bx = 2.0f * _2bx;
+    _4bz = 2.0f * _2bz;
+
+    /* Gradient decent algorithm corrective step */
+    s0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q1 * (2.0f * q0q1 + _2q2q3 - ay) -
+         _2bz * ahrs->quat.q2 *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (-_2bx * ahrs->quat.q3 + _2bz * ahrs->quat.q1) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         _2bx * ahrs->quat.q2 *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q0 * (2.0f * q0q1 + _2q2q3 - ay) -
+         4.0f * ahrs->quat.q1 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) +
+         _2bz * ahrs->quat.q3 *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (_2bx * ahrs->quat.q2 + _2bz * ahrs->quat.q0) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         (_2bx * ahrs->quat.q3 - _4bz * ahrs->quat.q1) *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q3 * (2.0f * q0q1 + _2q2q3 - ay) -
+         4.0f * ahrs->quat.q2 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) +
+         (-_4bx * ahrs->quat.q2 - _2bz * ahrs->quat.q0) *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (_2bx * ahrs->quat.q1 + _2bz * ahrs->quat.q3) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         (_2bx * ahrs->quat.q0 - _4bz * ahrs->quat.q2) *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q2 * (2.0f * q0q1 + _2q2q3 - ay) +
+         (-_4bx * ahrs->quat.q3 + _2bz * ahrs->quat.q1) *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (-_2bx * ahrs->quat.q0 + _2bz * ahrs->quat.q2) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         _2bx * ahrs->quat.q1 *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    /* normalise step magnitude */
+    recip_norm = InvSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3);
+    s0 *= recip_norm;
+    s1 *= recip_norm;
+    s2 *= recip_norm;
+    s3 *= recip_norm;
+
+    /* Apply feedback step */
+    q_dot1 -= beta * s0;
+    q_dot2 -= beta * s1;
+    q_dot3 -= beta * s2;
+    q_dot4 -= beta * s3;
+  }
+
+  /* Integrate rate of change of quaternion to yield quaternion */
+  ahrs->quat.q0 += q_dot1 * ahrs->inv_sample_freq;
+  ahrs->quat.q1 += q_dot2 * ahrs->inv_sample_freq;
+  ahrs->quat.q2 += q_dot3 * ahrs->inv_sample_freq;
+  ahrs->quat.q3 += q_dot4 * ahrs->inv_sample_freq;
+
+  /* Normalise quaternion */
+  recip_norm = InvSqrt(ahrs->quat.q0 * ahrs->quat.q0 +
+                       ahrs->quat.q1 * ahrs->quat.q1 +
+                       ahrs->quat.q2 * ahrs->quat.q2 +
+                       ahrs->quat.q3 * ahrs->quat.q3);
+  ahrs->quat.q0 *= recip_norm;
+  ahrs->quat.q1 *= recip_norm;
+  ahrs->quat.q2 *= recip_norm;
+  ahrs->quat.q3 *= recip_norm;
+
+  return 0;
+}
+
+/**
+ * @brief 通过姿态解算主结构体中的四元数计算欧拉角
+ *
+ * @param eulr 欧拉角
+ * @param ahrs 姿态解算主结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_GetEulr(AHRS_Eulr_t *eulr, const AHRS_t *ahrs) {
+  if (eulr == NULL) return -1;
+  if (ahrs == NULL) return -1;
+
+  const float sinr_cosp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q1 +
+                                  ahrs->quat.q2 * ahrs->quat.q3);
+  const float cosr_cosp =
+      1.0f - 2.0f * (ahrs->quat.q1 * ahrs->quat.q1 +
+                     ahrs->quat.q2 * ahrs->quat.q2);
+  eulr->pit = atan2f(sinr_cosp, cosr_cosp);
+
+  const float sinp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q2 -
+                             ahrs->quat.q3 * ahrs->quat.q1);
+
+  if (fabsf(sinp) >= 1.0f)
+    eulr->rol = copysignf(M_PI / 2.0f, sinp);
+  else
+    eulr->rol = asinf(sinp);
+
+  const float siny_cosp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q3 +
+                                  ahrs->quat.q1 * ahrs->quat.q2);
+  const float cosy_cosp =
+      1.0f - 2.0f * (ahrs->quat.q2 * ahrs->quat.q2 +
+                     ahrs->quat.q3 * ahrs->quat.q3);
+  eulr->yaw = atan2f(siny_cosp, cosy_cosp);
+
+#if 0
+  eulr->yaw *= M_RAD2DEG_MULT;
+  eulr->rol *= M_RAD2DEG_MULT;
+  eulr->pit *= M_RAD2DEG_MULT;
+#endif
+
+  return 0;
+}
+
+/**
+ * \brief 将对应数据置零
+ *
+ * \param eulr 被操作的数据
+ */
+void AHRS_ResetEulr(AHRS_Eulr_t *eulr) { memset(eulr, 0, sizeof(*eulr)); }
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/ahrs.h b/User/component/ahrs.h
new file mode 100644
index 0000000..2245b1f
--- /dev/null
+++ b/User/component/ahrs.h
@@ -0,0 +1,114 @@
+/*
+  开源的AHRS算法。
+  MadgwickAHRS
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 欧拉角（Euler angle） */
+typedef struct {
+  float yaw; /* 偏航角（Yaw angle） */
+  float pit; /* 俯仰角（Pitch angle） */
+  float rol; /* 翻滚角（Roll angle） */
+} AHRS_Eulr_t;
+
+/* 加速度计 Accelerometer */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Accl_t;
+
+/* 陀螺仪 Gyroscope */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Gyro_t;
+
+/* 磁力计 Magnetometer */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Magn_t;
+
+/* 四元数 */
+typedef struct {
+  float q0;
+  float q1;
+  float q2;
+  float q3;
+} AHRS_Quaternion_t;
+
+/* 姿态解算算法主结构体 */
+typedef struct {
+  /* 四元数 */
+  AHRS_Quaternion_t quat;
+
+  float inv_sample_freq; /* 采样频率的的倒数 */
+} AHRS_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化姿态解算
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param magn 磁力计数据
+ * @param sample_freq 采样频率
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Init(AHRS_t *ahrs, const AHRS_Magn_t *magn, float sample_freq);
+
+/**
+ * @brief 姿态运算更新一次
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @param magn 磁力计数据
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Update(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                   const AHRS_Gyro_t *gyro, const AHRS_Magn_t *magn);
+
+/**
+ * @brief 通过姿态解算主结构体中的四元数计算欧拉角
+ *
+ * @param eulr 欧拉角
+ * @param ahrs 姿态解算主结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_GetEulr(AHRS_Eulr_t *eulr, const AHRS_t *ahrs);
+
+/**
+ * \brief 将对应数据置零
+ *
+ * \param eulr 被操作的数据
+ */
+void AHRS_ResetEulr(AHRS_Eulr_t *eulr);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/ahrs/ahrs.c b/User/component/ahrs/ahrs.c
new file mode 100644
index 0000000..ffdb870
--- /dev/null
+++ b/User/component/ahrs/ahrs.c
@@ -0,0 +1,417 @@
+/*
+  开源的AHRS算法。
+  MadgwickAHRS
+*/
+
+#include "ahrs.h"
+
+#include 
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define BETA_IMU (0.033f)
+#define BETA_AHRS (0.041f)
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 2 * proportional gain (Kp) */
+static float beta = BETA_IMU;
+
+/**
+ * @brief 不使用磁力计计算姿态
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @return int8_t 0对应没有错误
+ */
+static int8_t AHRS_UpdateIMU(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                             const AHRS_Gyro_t *gyro) {
+  if (ahrs == NULL) return -1;
+  if (accl == NULL) return -1;
+  if (gyro == NULL) return -1;
+
+  beta = BETA_IMU;
+
+  float ax = accl->x;
+  float ay = accl->y;
+  float az = accl->z;
+
+  float gx = gyro->x;
+  float gy = gyro->y;
+  float gz = gyro->z;
+
+  float recip_norm;
+  float s0, s1, s2, s3;
+  float q_dot1, q_dot2, q_dot3, q_dot4;
+  float _2q0, _2q1, _2q2, _2q3, _4q0, _4q1, _4q2, _8q1, _8q2, q0q0, q1q1, q2q2,
+      q3q3;
+
+  /* Rate of change of quaternion from gyroscope */
+  q_dot1 = 0.5f * (-ahrs->quat.q1 * gx - ahrs->quat.q2 * gy -
+                   ahrs->quat.q3 * gz);
+  q_dot2 = 0.5f * (ahrs->quat.q0 * gx + ahrs->quat.q2 * gz -
+                   ahrs->quat.q3 * gy);
+  q_dot3 = 0.5f * (ahrs->quat.q0 * gy - ahrs->quat.q1 * gz +
+                   ahrs->quat.q3 * gx);
+  q_dot4 = 0.5f * (ahrs->quat.q0 * gz + ahrs->quat.q1 * gy -
+                   ahrs->quat.q2 * gx);
+
+  /* Compute feedback only if accelerometer measurement valid (avoids NaN in
+   * accelerometer normalisation) */
+  if (!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
+    /* Normalise accelerometer measurement */
+    recip_norm = InvSqrt(ax * ax + ay * ay + az * az);
+    ax *= recip_norm;
+    ay *= recip_norm;
+    az *= recip_norm;
+
+    /* Auxiliary variables to avoid repeated arithmetic */
+    _2q0 = 2.0f * ahrs->quat.q0;
+    _2q1 = 2.0f * ahrs->quat.q1;
+    _2q2 = 2.0f * ahrs->quat.q2;
+    _2q3 = 2.0f * ahrs->quat.q3;
+    _4q0 = 4.0f * ahrs->quat.q0;
+    _4q1 = 4.0f * ahrs->quat.q1;
+    _4q2 = 4.0f * ahrs->quat.q2;
+    _8q1 = 8.0f * ahrs->quat.q1;
+    _8q2 = 8.0f * ahrs->quat.q2;
+    q0q0 = ahrs->quat.q0 * ahrs->quat.q0;
+    q1q1 = ahrs->quat.q1 * ahrs->quat.q1;
+    q2q2 = ahrs->quat.q2 * ahrs->quat.q2;
+    q3q3 = ahrs->quat.q3 * ahrs->quat.q3;
+
+    /* Gradient decent algorithm corrective step */
+    s0 = _4q0 * q2q2 + _2q2 * ax + _4q0 * q1q1 - _2q1 * ay;
+    s1 = _4q1 * q3q3 - _2q3 * ax + 4.0f * q0q0 * ahrs->quat.q1 -
+         _2q0 * ay - _4q1 + _8q1 * q1q1 + _8q1 * q2q2 + _4q1 * az;
+    s2 = 4.0f * q0q0 * ahrs->quat.q2 + _2q0 * ax + _4q2 * q3q3 -
+         _2q3 * ay - _4q2 + _8q2 * q1q1 + _8q2 * q2q2 + _4q2 * az;
+    s3 = 4.0f * q1q1 * ahrs->quat.q3 - _2q1 * ax +
+         4.0f * q2q2 * ahrs->quat.q3 - _2q2 * ay;
+
+    /* normalise step magnitude */
+    recip_norm = InvSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3);
+
+    s0 *= recip_norm;
+    s1 *= recip_norm;
+    s2 *= recip_norm;
+    s3 *= recip_norm;
+
+    /* Apply feedback step */
+    q_dot1 -= beta * s0;
+    q_dot2 -= beta * s1;
+    q_dot3 -= beta * s2;
+    q_dot4 -= beta * s3;
+  }
+
+  /* Integrate rate of change of quaternion to yield quaternion */
+  ahrs->quat.q0 += q_dot1 * ahrs->inv_sample_freq;
+  ahrs->quat.q1 += q_dot2 * ahrs->inv_sample_freq;
+  ahrs->quat.q2 += q_dot3 * ahrs->inv_sample_freq;
+  ahrs->quat.q3 += q_dot4 * ahrs->inv_sample_freq;
+
+  /* Normalise quaternion */
+  recip_norm = InvSqrt(ahrs->quat.q0 * ahrs->quat.q0 +
+                       ahrs->quat.q1 * ahrs->quat.q1 +
+                       ahrs->quat.q2 * ahrs->quat.q2 +
+                       ahrs->quat.q3 * ahrs->quat.q3);
+  ahrs->quat.q0 *= recip_norm;
+  ahrs->quat.q1 *= recip_norm;
+  ahrs->quat.q2 *= recip_norm;
+  ahrs->quat.q3 *= recip_norm;
+
+  return 0;
+}
+
+/**
+ * @brief 初始化姿态解算
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param magn 磁力计数据
+ * @param sample_freq 采样频率
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Init(AHRS_t *ahrs, const AHRS_Magn_t *magn, float sample_freq) {
+  if (ahrs == NULL) return -1;
+
+  ahrs->inv_sample_freq = 1.0f / sample_freq;
+
+  ahrs->quat.q0 = 1.0f;
+  ahrs->quat.q1 = 0.0f;
+  ahrs->quat.q2 = 0.0f;
+  ahrs->quat.q3 = 0.0f;
+
+  if (magn) {
+    float yaw = -atan2(magn->y, magn->x);
+
+    if ((magn->x == 0.0f) && (magn->y == 0.0f) && (magn->z == 0.0f)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < (M_PI / 2.0f)) || (yaw > 0.0f)) {
+      ahrs->quat.q0 = 0.997458339f;
+      ahrs->quat.q1 = 0.000336312107f;
+      ahrs->quat.q2 = -0.0057230792f;
+      ahrs->quat.q3 = 0.0740156546;
+
+    } else if ((yaw < M_PI) || (yaw > (M_PI / 2.0f))) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < 90.0f) || (yaw > M_PI)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+
+    } else if ((yaw < 90.0f) || (yaw > 0.0f)) {
+      ahrs->quat.q0 = 0.800884545f;
+      ahrs->quat.q1 = 0.00862364192f;
+      ahrs->quat.q2 = -0.00283267116f;
+      ahrs->quat.q3 = 0.598749936f;
+    }
+  }
+  return 0;
+}
+
+/**
+ * @brief 姿态运算更新一次
+ * @note 输入数据必须是NED(North East Down) 参考坐标系
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @param magn 磁力计数据
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Update(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                   const AHRS_Gyro_t *gyro, const AHRS_Magn_t *magn) {
+  if (ahrs == NULL) return -1;
+  if (accl == NULL) return -1;
+  if (gyro == NULL) return -1;
+
+  beta = BETA_AHRS;
+
+  float recip_norm;
+  float s0, s1, s2, s3;
+  float q_dot1, q_dot2, q_dot3, q_dot4;
+  float hx, hy;
+  float _2q0mx, _2q0my, _2q0mz, _2q1mx, _2bx, _2bz, _4bx, _4bz, _2q0, _2q1,
+      _2q2, _2q3, _2q0q2, _2q2q3, q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3,
+      q2q2, q2q3, q3q3;
+
+  if (magn == NULL) return AHRS_UpdateIMU(ahrs, accl, gyro);
+
+  float mx = magn->x;
+  float my = magn->y;
+  float mz = magn->z;
+
+  /* Use IMU algorithm if magnetometer measurement invalid (avoids NaN in */
+  /* magnetometer normalisation) */
+  if ((mx == 0.0f) && (my == 0.0f) && (mz == 0.0f)) {
+    return AHRS_UpdateIMU(ahrs, accl, gyro);
+  }
+
+  float ax = accl->x;
+  float ay = accl->y;
+  float az = accl->z;
+
+  float gx = gyro->x;
+  float gy = gyro->y;
+  float gz = gyro->z;
+
+  /* Rate of change of quaternion from gyroscope */
+  q_dot1 = 0.5f * (-ahrs->quat.q1 * gx - ahrs->quat.q2 * gy -
+                   ahrs->quat.q3 * gz);
+  q_dot2 = 0.5f * (ahrs->quat.q0 * gx + ahrs->quat.q2 * gz -
+                   ahrs->quat.q3 * gy);
+  q_dot3 = 0.5f * (ahrs->quat.q0 * gy - ahrs->quat.q1 * gz +
+                   ahrs->quat.q3 * gx);
+  q_dot4 = 0.5f * (ahrs->quat.q0 * gz + ahrs->quat.q1 * gy -
+                   ahrs->quat.q2 * gx);
+
+  /* Compute feedback only if accelerometer measurement valid (avoids NaN in
+   * accelerometer normalisation) */
+  if (!((ax == 0.0f) && (ay == 0.0f) && (az == 0.0f))) {
+    /* Normalise accelerometer measurement */
+    recip_norm = InvSqrt(ax * ax + ay * ay + az * az);
+    ax *= recip_norm;
+    ay *= recip_norm;
+    az *= recip_norm;
+
+    /* Normalise magnetometer measurement */
+    recip_norm = InvSqrt(mx * mx + my * my + mz * mz);
+    mx *= recip_norm;
+    my *= recip_norm;
+    mz *= recip_norm;
+
+    /* Auxiliary variables to avoid repeated arithmetic */
+    _2q0mx = 2.0f * ahrs->quat.q0 * mx;
+    _2q0my = 2.0f * ahrs->quat.q0 * my;
+    _2q0mz = 2.0f * ahrs->quat.q0 * mz;
+    _2q1mx = 2.0f * ahrs->quat.q1 * mx;
+    _2q0 = 2.0f * ahrs->quat.q0;
+    _2q1 = 2.0f * ahrs->quat.q1;
+    _2q2 = 2.0f * ahrs->quat.q2;
+    _2q3 = 2.0f * ahrs->quat.q3;
+    _2q0q2 = 2.0f * ahrs->quat.q0 * ahrs->quat.q2;
+    _2q2q3 = 2.0f * ahrs->quat.q2 * ahrs->quat.q3;
+    q0q0 = ahrs->quat.q0 * ahrs->quat.q0;
+    q0q1 = ahrs->quat.q0 * ahrs->quat.q1;
+    q0q2 = ahrs->quat.q0 * ahrs->quat.q2;
+    q0q3 = ahrs->quat.q0 * ahrs->quat.q3;
+    q1q1 = ahrs->quat.q1 * ahrs->quat.q1;
+    q1q2 = ahrs->quat.q1 * ahrs->quat.q2;
+    q1q3 = ahrs->quat.q1 * ahrs->quat.q3;
+    q2q2 = ahrs->quat.q2 * ahrs->quat.q2;
+    q2q3 = ahrs->quat.q2 * ahrs->quat.q3;
+    q3q3 = ahrs->quat.q3 * ahrs->quat.q3;
+
+    /* Reference direction of Earth's magnetic field */
+    hx = mx * q0q0 - _2q0my * ahrs->quat.q3 +
+         _2q0mz * ahrs->quat.q2 + mx * q1q1 +
+         _2q1 * my * ahrs->quat.q2 + _2q1 * mz * ahrs->quat.q3 -
+         mx * q2q2 - mx * q3q3;
+    hy = _2q0mx * ahrs->quat.q3 + my * q0q0 -
+         _2q0mz * ahrs->quat.q1 + _2q1mx * ahrs->quat.q2 -
+         my * q1q1 + my * q2q2 + _2q2 * mz * ahrs->quat.q3 - my * q3q3;
+    // _2bx = sqrtf(hx * hx + hy * hy);
+    // 改为invsqrt
+    _2bx = 1.f / InvSqrt(hx * hx + hy * hy);
+    _2bz = -_2q0mx * ahrs->quat.q2 + _2q0my * ahrs->quat.q1 +
+           mz * q0q0 + _2q1mx * ahrs->quat.q3 - mz * q1q1 +
+           _2q2 * my * ahrs->quat.q3 - mz * q2q2 + mz * q3q3;
+    _4bx = 2.0f * _2bx;
+    _4bz = 2.0f * _2bz;
+
+    /* Gradient decent algorithm corrective step */
+    s0 = -_2q2 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q1 * (2.0f * q0q1 + _2q2q3 - ay) -
+         _2bz * ahrs->quat.q2 *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (-_2bx * ahrs->quat.q3 + _2bz * ahrs->quat.q1) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         _2bx * ahrs->quat.q2 *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s1 = _2q3 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q0 * (2.0f * q0q1 + _2q2q3 - ay) -
+         4.0f * ahrs->quat.q1 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) +
+         _2bz * ahrs->quat.q3 *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (_2bx * ahrs->quat.q2 + _2bz * ahrs->quat.q0) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         (_2bx * ahrs->quat.q3 - _4bz * ahrs->quat.q1) *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s2 = -_2q0 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q3 * (2.0f * q0q1 + _2q2q3 - ay) -
+         4.0f * ahrs->quat.q2 * (1 - 2.0f * q1q1 - 2.0f * q2q2 - az) +
+         (-_4bx * ahrs->quat.q2 - _2bz * ahrs->quat.q0) *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (_2bx * ahrs->quat.q1 + _2bz * ahrs->quat.q3) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         (_2bx * ahrs->quat.q0 - _4bz * ahrs->quat.q2) *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    s3 = _2q1 * (2.0f * q1q3 - _2q0q2 - ax) +
+         _2q2 * (2.0f * q0q1 + _2q2q3 - ay) +
+         (-_4bx * ahrs->quat.q3 + _2bz * ahrs->quat.q1) *
+             (_2bx * (0.5f - q2q2 - q3q3) + _2bz * (q1q3 - q0q2) - mx) +
+         (-_2bx * ahrs->quat.q0 + _2bz * ahrs->quat.q2) *
+             (_2bx * (q1q2 - q0q3) + _2bz * (q0q1 + q2q3) - my) +
+         _2bx * ahrs->quat.q1 *
+             (_2bx * (q0q2 + q1q3) + _2bz * (0.5f - q1q1 - q2q2) - mz);
+    /* normalise step magnitude */
+    recip_norm = InvSqrt(s0 * s0 + s1 * s1 + s2 * s2 + s3 * s3);
+    s0 *= recip_norm;
+    s1 *= recip_norm;
+    s2 *= recip_norm;
+    s3 *= recip_norm;
+
+    /* Apply feedback step */
+    q_dot1 -= beta * s0;
+    q_dot2 -= beta * s1;
+    q_dot3 -= beta * s2;
+    q_dot4 -= beta * s3;
+  }
+
+  /* Integrate rate of change of quaternion to yield quaternion */
+  ahrs->quat.q0 += q_dot1 * ahrs->inv_sample_freq;
+  ahrs->quat.q1 += q_dot2 * ahrs->inv_sample_freq;
+  ahrs->quat.q2 += q_dot3 * ahrs->inv_sample_freq;
+  ahrs->quat.q3 += q_dot4 * ahrs->inv_sample_freq;
+
+  /* Normalise quaternion */
+  recip_norm = InvSqrt(ahrs->quat.q0 * ahrs->quat.q0 +
+                       ahrs->quat.q1 * ahrs->quat.q1 +
+                       ahrs->quat.q2 * ahrs->quat.q2 +
+                       ahrs->quat.q3 * ahrs->quat.q3);
+  ahrs->quat.q0 *= recip_norm;
+  ahrs->quat.q1 *= recip_norm;
+  ahrs->quat.q2 *= recip_norm;
+  ahrs->quat.q3 *= recip_norm;
+
+  return 0;
+}
+
+/**
+ * @brief 通过姿态解算主结构体中的四元数计算欧拉角
+ *
+ * @param eulr 欧拉角
+ * @param ahrs 姿态解算主结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_GetEulr(AHRS_Eulr_t *eulr, const AHRS_t *ahrs) {
+  if (eulr == NULL) return -1;
+  if (ahrs == NULL) return -1;
+
+  const float sinr_cosp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q1 +
+                                  ahrs->quat.q2 * ahrs->quat.q3);
+  const float cosr_cosp =
+      1.0f - 2.0f * (ahrs->quat.q1 * ahrs->quat.q1 +
+                     ahrs->quat.q2 * ahrs->quat.q2);
+  eulr->pit = atan2f(sinr_cosp, cosr_cosp);
+
+  const float sinp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q2 -
+                             ahrs->quat.q3 * ahrs->quat.q1);
+
+  if (fabsf(sinp) >= 1.0f)
+    eulr->rol = copysignf(M_PI / 2.0f, sinp);
+  else
+    eulr->rol = asinf(sinp);
+
+  const float siny_cosp = 2.0f * (ahrs->quat.q0 * ahrs->quat.q3 +
+                                  ahrs->quat.q1 * ahrs->quat.q2);
+  const float cosy_cosp =
+      1.0f - 2.0f * (ahrs->quat.q2 * ahrs->quat.q2 +
+                     ahrs->quat.q3 * ahrs->quat.q3);
+  eulr->yaw = atan2f(siny_cosp, cosy_cosp);
+
+#if 0
+  eulr->yaw *= M_RAD2DEG_MULT;
+  eulr->rol *= M_RAD2DEG_MULT;
+  eulr->pit *= M_RAD2DEG_MULT;
+#endif
+
+  return 0;
+}
+
+/**
+ * \brief 将对应数据置零
+ *
+ * \param eulr 被操作的数据
+ */
+void AHRS_ResetEulr(AHRS_Eulr_t *eulr) { memset(eulr, 0, sizeof(*eulr)); }
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/ahrs/ahrs.h b/User/component/ahrs/ahrs.h
new file mode 100644
index 0000000..2245b1f
--- /dev/null
+++ b/User/component/ahrs/ahrs.h
@@ -0,0 +1,114 @@
+/*
+  开源的AHRS算法。
+  MadgwickAHRS
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 欧拉角（Euler angle） */
+typedef struct {
+  float yaw; /* 偏航角（Yaw angle） */
+  float pit; /* 俯仰角（Pitch angle） */
+  float rol; /* 翻滚角（Roll angle） */
+} AHRS_Eulr_t;
+
+/* 加速度计 Accelerometer */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Accl_t;
+
+/* 陀螺仪 Gyroscope */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Gyro_t;
+
+/* 磁力计 Magnetometer */
+typedef struct {
+  float x;
+  float y;
+  float z;
+} AHRS_Magn_t;
+
+/* 四元数 */
+typedef struct {
+  float q0;
+  float q1;
+  float q2;
+  float q3;
+} AHRS_Quaternion_t;
+
+/* 姿态解算算法主结构体 */
+typedef struct {
+  /* 四元数 */
+  AHRS_Quaternion_t quat;
+
+  float inv_sample_freq; /* 采样频率的的倒数 */
+} AHRS_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化姿态解算
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param magn 磁力计数据
+ * @param sample_freq 采样频率
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Init(AHRS_t *ahrs, const AHRS_Magn_t *magn, float sample_freq);
+
+/**
+ * @brief 姿态运算更新一次
+ *
+ * @param ahrs 姿态解算主结构体
+ * @param accl 加速度计数据
+ * @param gyro 陀螺仪数据
+ * @param magn 磁力计数据
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_Update(AHRS_t *ahrs, const AHRS_Accl_t *accl,
+                   const AHRS_Gyro_t *gyro, const AHRS_Magn_t *magn);
+
+/**
+ * @brief 通过姿态解算主结构体中的四元数计算欧拉角
+ *
+ * @param eulr 欧拉角
+ * @param ahrs 姿态解算主结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t AHRS_GetEulr(AHRS_Eulr_t *eulr, const AHRS_t *ahrs);
+
+/**
+ * \brief 将对应数据置零
+ *
+ * \param eulr 被操作的数据
+ */
+void AHRS_ResetEulr(AHRS_Eulr_t *eulr);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/capacity.c b/User/component/capacity.c
new file mode 100644
index 0000000..fd64eb2
--- /dev/null
+++ b/User/component/capacity.c
@@ -0,0 +1,70 @@
+/*
+  剩余电量算法。
+  通过电压值计算剩余电量。
+*/
+
+#include "capacity.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/**
+ * @brief 通过电压计算电池剩余电量
+ *
+ * @param volt 电压值
+ * @return float 剩余电量比例
+ */
+float Capacity_GetBatteryRemain(float volt) {
+  float percentage;
+  float volt_2 = volt * volt;
+  float volt_3 = volt_2 * volt;
+
+  if (volt < 19.5f)
+    percentage = 0.0f;
+
+  else if (volt < 21.9f)
+    percentage = 0.005664f * volt_3 - 0.3386f * volt_2 + 6.765f * volt - 45.17f;
+
+  else if (volt < 25.5f)
+    percentage = 0.02269f * volt_3 - 1.654f * volt_2 + 40.34f * volt - 328.4f;
+
+  else
+    percentage = 1.0f;
+
+  if (percentage < 0.0f)
+    percentage = 0.0f;
+
+  else if (percentage > 1.0f)
+    percentage = 1.0f;
+
+  return percentage;
+}
+
+/**
+ * @brief
+ *
+ * @param vcap 电容电压
+ * @param vbat 电池电压
+ * @param v_cutoff 截止电压
+ * @return float 电容剩余电量比例
+ */
+float Capacity_GetCapacitorRemain(float vcap, float vbat, float v_cutoff) {
+  float percentage = (vcap - v_cutoff) / (vbat - v_cutoff);
+
+  if (percentage < 0.0f)
+    percentage = 0.0f;
+
+  else if (percentage > 1.0f)
+    percentage = 1.0f;
+
+  return percentage;
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/capacity.h b/User/component/capacity.h
new file mode 100644
index 0000000..b4010e9
--- /dev/null
+++ b/User/component/capacity.h
@@ -0,0 +1,47 @@
+/*
+  剩余电量算法。
+
+  通过电压值计算剩余电量。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/**
+ * @brief 通过电压计算电池剩余电量
+ *
+ * @param volt 电压值
+ * @return float 剩余电量比例
+ */
+float Capacity_GetBatteryRemain(float volt);
+
+/**
+ * @brief
+ *
+ * @param vcap 电容电压
+ * @param vbat 电池电压
+ * @param v_cutoff 截止电压
+ * @return float 电容剩余电量比例
+ */
+float Capacity_GetCapacitorRemain(float vcap, float vbat, float v_cutoff);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/cmd.c b/User/component/cmd.c
new file mode 100644
index 0000000..1effe69
--- /dev/null
+++ b/User/component/cmd.c
@@ -0,0 +1,387 @@
+/*
+  控制命令
+*/
+
+#include "cmd.h"
+
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/**
+ * @brief 行为转换为对应按键
+ *
+ * @param cmd 主结构体
+ * @param behavior 行为
+ * @return uint16_t 行为对应的按键
+ */
+static inline CMD_KeyValue_t CMD_BehaviorToKey(CMD_t *cmd,
+                                               CMD_Behavior_t behavior) {
+  return cmd->param->map.key_map[behavior].key;
+}
+
+static inline CMD_ActiveType_t CMD_BehaviorToActive(CMD_t *cmd,
+                                                    CMD_Behavior_t behavior) {
+  return cmd->param->map.key_map[behavior].active;
+}
+
+/**
+ * @brief 检查按键是否按下
+ *
+ * @param rc 遥控器数据
+ * @param key 按键名称
+ * @param stateful 是否为状态切换按键
+ * @return true 按下
+ * @return false 未按下
+ */
+static bool CMD_KeyPressedRc(const CMD_RC_t *rc, CMD_KeyValue_t key) {
+  /* 按下按键为鼠标左、右键 */
+  if (key == CMD_L_CLICK) {
+    return rc->mouse.l_click;
+  }
+  if (key == CMD_R_CLICK) {
+    return rc->mouse.r_click;
+  }
+  return rc->key & (1u << key);
+}
+
+static bool CMD_BehaviorOccurredRc(const CMD_RC_t *rc, CMD_t *cmd,
+                                   CMD_Behavior_t behavior) {
+  CMD_KeyValue_t key = CMD_BehaviorToKey(cmd, behavior);
+  CMD_ActiveType_t active = CMD_BehaviorToActive(cmd, behavior);
+
+  bool now_key_pressed, last_key_pressed;
+
+  /* 按下按键为鼠标左、右键 */
+  if (key == CMD_L_CLICK) {
+    now_key_pressed = rc->mouse.l_click;
+    last_key_pressed = cmd->mouse_last.l_click;
+  } else if (key == CMD_R_CLICK) {
+    now_key_pressed = rc->mouse.r_click;
+    last_key_pressed = cmd->mouse_last.r_click;
+  } else {
+    now_key_pressed = rc->key & (1u << key);
+    last_key_pressed = cmd->key_last & (1u << key);
+  }
+
+  switch (active) {
+    case CMD_ACTIVE_PRESSING:
+      return now_key_pressed && !last_key_pressed;
+    case CMD_ACTIVE_RASING:
+      return !now_key_pressed && last_key_pressed;
+    case CMD_ACTIVE_PRESSED:
+      return now_key_pressed;
+  }
+}
+
+/**
+ * @brief 解析pc行为逻辑
+ *
+ * @param rc 遥控器数据
+ * @param cmd 主结构体
+ * @param dt_sec 两次解析的间隔
+ */
+static void CMD_PcLogic(const CMD_RC_t *rc, CMD_t *cmd, float dt_sec) {
+  cmd->gimbal.mode = GIMBAL_MODE_ABSOLUTE;
+
+  /* 云台设置为鼠标控制欧拉角的变化，底盘的控制向量设置为零 */
+  cmd->gimbal.delta_eulr.yaw =
+      (float)rc->mouse.x * dt_sec * cmd->param->sens_mouse;
+  cmd->gimbal.delta_eulr.pit =
+      (float)(-rc->mouse.y) * dt_sec * cmd->param->sens_mouse;
+  cmd->chassis.ctrl_vec.vx = cmd->chassis.ctrl_vec.vy = 0.0f;
+  cmd->shoot.reverse_trig = false;
+
+  /* 按键行为映射相关逻辑 */
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_FORE)) {
+    cmd->chassis.ctrl_vec.vy += cmd->param->move.move_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_BACK)) {
+    cmd->chassis.ctrl_vec.vy -= cmd->param->move.move_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_LEFT)) {
+    cmd->chassis.ctrl_vec.vx -= cmd->param->move.move_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_RIGHT)) {
+    cmd->chassis.ctrl_vec.vx += cmd->param->move.move_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_ACCELERATE)) {
+    cmd->chassis.ctrl_vec.vx *= cmd->param->move.move_fast_sense;
+    cmd->chassis.ctrl_vec.vy *= cmd->param->move.move_fast_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_DECELEBRATE)) {
+    cmd->chassis.ctrl_vec.vx *= cmd->param->move.move_slow_sense;
+    cmd->chassis.ctrl_vec.vy *= cmd->param->move.move_slow_sense;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_FIRE)) {
+    /* 切换至开火模式，设置相应的射击频率和弹丸初速度 */
+    cmd->shoot.mode = SHOOT_MODE_LOADED;
+    cmd->shoot.fire = true;
+  } else {
+    /* 切换至准备模式，停止射击 */
+    cmd->shoot.mode = SHOOT_MODE_LOADED;
+    cmd->shoot.fire = false;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_FIRE_MODE)) {
+    /* 每按一次依次切换开火下一个模式 */
+    cmd->shoot.fire_mode++;
+    cmd->shoot.fire_mode %= FIRE_MODE_NUM;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_ROTOR)) {
+    /* 切换到小陀螺模式 */
+    cmd->chassis.mode = CHASSIS_MODE_ROTOR;
+    cmd->chassis.mode_rotor = ROTOR_MODE_RAND;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_OPENCOVER)) {
+    /* 每按一次开、关弹舱盖 */
+    cmd->shoot.cover_open = !cmd->shoot.cover_open;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_BUFF)) {
+    if (cmd->ai_status == AI_STATUS_HITSWITCH) {
+      /* 停止ai的打符模式，停用host控制 */
+      CMD_RefereeAdd(&(cmd->referee), CMD_UI_HIT_SWITCH_STOP);
+      cmd->host_overwrite = false;
+      cmd->ai_status = AI_STATUS_STOP;
+    } else if (cmd->ai_status == AI_STATUS_AUTOAIM) {
+      /* 自瞄模式中切换失败提醒 */
+    } else {
+      /* ai切换至打符模式，启用host控制 */
+      CMD_RefereeAdd(&(cmd->referee), CMD_UI_HIT_SWITCH_START);
+      cmd->ai_status = AI_STATUS_HITSWITCH;
+      cmd->host_overwrite = true;
+    }
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_AUTOAIM)) {
+    if (cmd->ai_status == AI_STATUS_AUTOAIM) {
+      /* 停止ai的自瞄模式，停用host控制 */
+      cmd->host_overwrite = false;
+      cmd->ai_status = AI_STATUS_STOP;
+      CMD_RefereeAdd(&(cmd->referee), CMD_UI_AUTO_AIM_STOP);
+    } else {
+      /* ai切换至自瞄模式，启用host控制 */
+      cmd->ai_status = AI_STATUS_AUTOAIM;
+      cmd->host_overwrite = true;
+      CMD_RefereeAdd(&(cmd->referee), CMD_UI_AUTO_AIM_START);
+    }
+  } else {
+    cmd->host_overwrite = false;
+    // TODO: 修复逻辑
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_REVTRIG)) {
+    /* 按下拨弹反转 */
+    cmd->shoot.reverse_trig = true;
+  }
+  if (CMD_BehaviorOccurredRc(rc, cmd, CMD_BEHAVIOR_FOLLOWGIMBAL35)) {
+    cmd->chassis.mode = CHASSIS_MODE_FOLLOW_GIMBAL_35;
+  }
+  /* 保存当前按下的键位状态 */
+  cmd->key_last = rc->key;
+  memcpy(&(cmd->mouse_last), &(rc->mouse), sizeof(cmd->mouse_last));
+}
+
+/**
+ * @brief 解析rc行为逻辑
+ *
+ * @param rc 遥控器数据
+ * @param cmd 主结构体
+ * @param dt_sec 两次解析的间隔
+ */
+static void CMD_RcLogic(const CMD_RC_t *rc, CMD_t *cmd, float dt_sec) {
+  switch (rc->sw_l) {
+      /* 左拨杆相应行为选择和解析 */
+    case CMD_SW_UP:
+      cmd->chassis.mode = CHASSIS_MODE_BREAK;
+      break;
+
+    case CMD_SW_MID:
+      cmd->chassis.mode = CHASSIS_MODE_FOLLOW_GIMBAL;
+      break;
+
+    case CMD_SW_DOWN:
+      cmd->chassis.mode = CHASSIS_MODE_ROTOR;
+      cmd->chassis.mode_rotor = ROTOR_MODE_CW;
+      break;
+
+    case CMD_SW_ERR:
+      cmd->chassis.mode = CHASSIS_MODE_RELAX;
+      break;
+  }
+  switch (rc->sw_r) {
+      /* 右拨杆相应行为选择和解析*/ 
+    case CMD_SW_UP:
+      cmd->gimbal.mode = GIMBAL_MODE_ABSOLUTE;
+      cmd->shoot.mode = SHOOT_MODE_SAFE;
+      break;
+
+    case CMD_SW_MID:
+      cmd->gimbal.mode = GIMBAL_MODE_ABSOLUTE;
+      cmd->shoot.fire = false;
+      cmd->shoot.mode = SHOOT_MODE_LOADED;
+      break;
+
+    case CMD_SW_DOWN:
+      cmd->gimbal.mode = GIMBAL_MODE_ABSOLUTE;
+      cmd->shoot.mode = SHOOT_MODE_LOADED;
+      cmd->shoot.fire_mode = FIRE_MODE_SINGLE;
+      cmd->shoot.fire = true;
+      break;
+		/*
+		    case CMD_SW_UP:
+      cmd->gimbal.mode = GIMBAL_MODE_RELAX;
+      cmd->shoot.mode = SHOOT_MODE_SAFE;
+      break;
+
+    case CMD_SW_MID:
+      cmd->gimbal.mode = GIMBAL_MODE_RELAX;
+      cmd->shoot.fire = false;
+      cmd->shoot.mode = SHOOT_MODE_LOADED;
+      break;
+
+    case CMD_SW_DOWN:
+      cmd->gimbal.mode = GIMBAL_MODE_RELAX;
+      cmd->shoot.mode = SHOOT_MODE_LOADED;
+      cmd->shoot.fire_mode = FIRE_MODE_SINGLE;
+      cmd->shoot.fire = true;
+      break;
+		*/
+    case CMD_SW_ERR:
+      cmd->gimbal.mode = GIMBAL_MODE_RELAX;
+      cmd->shoot.mode = SHOOT_MODE_RELAX;
+  }
+  /* 将操纵杆的对应值转换为底盘的控制向量和云台变化的欧拉角 */
+  cmd->chassis.ctrl_vec.vx = rc->ch_l_x;
+  cmd->chassis.ctrl_vec.vy = rc->ch_l_y;
+  cmd->gimbal.delta_eulr.yaw = rc->ch_r_x * dt_sec * cmd->param->sens_rc;
+  cmd->gimbal.delta_eulr.pit = rc->ch_r_y * dt_sec * cmd->param->sens_rc;
+}
+
+/**
+ * @brief rc失控时机器人恢复放松模式
+ *
+ * @param cmd 主结构体
+ */
+static void CMD_RcLostLogic(CMD_t *cmd) {
+  /* 机器人底盘、云台、射击运行模式恢复至放松模式 */
+  cmd->chassis.mode = CHASSIS_MODE_RELAX;
+  cmd->gimbal.mode = GIMBAL_MODE_RELAX;
+  cmd->shoot.mode = SHOOT_MODE_RELAX;
+}
+
+/**
+ * @brief 初始化命令解析
+ *
+ * @param cmd 主结构体
+ * @param param 参数
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_Init(CMD_t *cmd, const CMD_Params_t *param) {
+  /* 指针检测 */
+  if (cmd == NULL) return -1;
+  if (param == NULL) return -1;
+
+  /* 设置机器人的命令参数，初始化控制方式为rc控制 */
+  cmd->pc_ctrl = false;
+  cmd->param = param;
+
+  return 0;
+}
+
+/**
+ * @brief 检查是否启用上位机控制指令覆盖
+ *
+ * @param cmd 主结构体
+ * @return true 启用
+ * @return false 不启用
+ */
+inline bool CMD_CheckHostOverwrite(CMD_t *cmd) { return cmd->host_overwrite; }
+
+/**
+ * @brief 解析命令
+ *
+ * @param rc 遥控器数据
+ * @param cmd 命令
+ * @param dt_sec 两次解析的间隔
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_ParseRc(CMD_RC_t *rc, CMD_t *cmd, float dt_sec) {
+  /* 指针检测 */
+  if (rc == NULL) return -1;
+  if (cmd == NULL) return -1;
+
+  /* 在pc控制和rc控制间切换 */
+  if (CMD_KeyPressedRc(rc, CMD_KEY_SHIFT) &&
+      CMD_KeyPressedRc(rc, CMD_KEY_CTRL) && CMD_KeyPressedRc(rc, CMD_KEY_Q))
+    cmd->pc_ctrl = true;
+
+  if (CMD_KeyPressedRc(rc, CMD_KEY_SHIFT) &&
+      CMD_KeyPressedRc(rc, CMD_KEY_CTRL) && CMD_KeyPressedRc(rc, CMD_KEY_E))
+    cmd->pc_ctrl = false;
+  /*c当rc丢控时，恢复机器人至默认状态 */
+  if ((rc->sw_l == CMD_SW_ERR) || (rc->sw_r == CMD_SW_ERR)) {
+    CMD_RcLostLogic(cmd);
+  } else {
+    if (cmd->pc_ctrl) {
+      CMD_PcLogic(rc, cmd, dt_sec);
+    } else {
+      CMD_RcLogic(rc, cmd, dt_sec);
+    }
+  }
+  return 0;
+}
+
+/**
+ * @brief 解析上位机命令
+ *
+ * @param host host数据
+ * @param cmd 命令
+ * @param dt_sec 两次解析的间隔
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_ParseHost(const CMD_Host_t *host, CMD_t *cmd, float dt_sec) {
+  (void)dt_sec; /* 未使用dt_sec，消除警告 */
+  /* 指针检测 */
+  if (host == NULL) return -1;
+  if (cmd == NULL) return -1;
+
+  /* 云台欧拉角设置为host相应的变化的欧拉角 */
+  cmd->gimbal.delta_eulr.yaw = host->gimbal_delta.yaw;
+  cmd->gimbal.delta_eulr.pit = host->gimbal_delta.pit;
+
+  /* host射击命令，设置不同的射击频率和弹丸初速度 */
+  if (host->fire) {
+    cmd->shoot.mode = SHOOT_MODE_LOADED;
+    cmd->shoot.fire = true;
+  } else {
+    cmd->shoot.mode = SHOOT_MODE_SAFE;
+  }
+  return 0;
+}
+
+/**
+ * @brief 添加向Referee发送的命令
+ *
+ * @param ref 命令队列
+ * @param cmd 要添加的命令
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_RefereeAdd(CMD_RefereeCmd_t *ref, CMD_UI_t cmd) {
+  /* 指针检测 */
+  if (ref == NULL) return -1;
+  /* 越界检测 */
+  if (ref->counter >= CMD_REFEREE_MAX_NUM || ref->counter < 0) return -1;
+
+  /* 添加机器人当前行为状态到画图的命令队列中 */
+  ref->cmd[ref->counter] = cmd;
+  ref->counter++;
+  return 0;
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/cmd.h b/User/component/cmd.h
new file mode 100644
index 0000000..df84538
--- /dev/null
+++ b/User/component/cmd.h
@@ -0,0 +1,318 @@
+/*
+  控制命令
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+#include "component/ahrs.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define CMD_REFEREE_MAX_NUM (3) /* Lines 16 omitted */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 机器人型号 */
+typedef enum {
+  ROBOT_MODEL_INFANTRY = 0, /* 步兵机器人 */
+  ROBOT_MODEL_HERO,         /* 英雄机器人 */
+  ROBOT_MODEL_ENGINEER,     /* 工程机器人 */
+  ROBOT_MODEL_DRONE,        /* 空中机器人 */
+  ROBOT_MODEL_SENTRY,       /* 哨兵机器人 */
+  ROBOT_MODEL_NUM,          /* 型号数量 */
+} CMD_RobotModel_t;
+
+/* 底盘运行模式 */
+typedef enum {
+  CHASSIS_MODE_RELAX, /* 放松模式，电机不输出。一般情况底盘初始化之后的模式 */
+  CHASSIS_MODE_BREAK, /* 刹车模式，电机闭环控制保持静止。用于机器人停止状态 */
+  CHASSIS_MODE_FOLLOW_GIMBAL, /* 通过闭环控制使车头方向跟随云台 */
+  CHASSIS_MODE_FOLLOW_GIMBAL_35, /* 通过闭环控制使车头方向35度跟随云台 */
+  CHASSIS_MODE_ROTOR, /* 小陀螺模式，通过闭环控制使底盘不停旋转 */
+  CHASSIS_MODE_INDENPENDENT, /* 独立模式。底盘运行不受云台影响 */
+  CHASSIS_MODE_OPEN, /* 开环模式。底盘运行不受PID控制，直接输出到电机 */
+} CMD_ChassisMode_t;
+
+/* 云台运行模式 */
+typedef enum {
+  GIMBAL_MODE_RELAX, /* 放松模式，电机不输出。一般情况云台初始化之后的模式 */
+  GIMBAL_MODE_ABSOLUTE, /* 绝对坐标系控制，控制在空间内的绝对姿态 */
+  GIMBAL_MODE_RELATIVE, /* 相对坐标系控制，控制相对于底盘的姿态 */
+} CMD_GimbalMode_t;
+
+/* 射击运行模式 */
+typedef enum {
+  SHOOT_MODE_RELAX,  /* 放松模式，电机不输出 */
+  SHOOT_MODE_SAFE,   /* 保险模式，电机闭环控制保持静止 */
+  SHOOT_MODE_LOADED, /* 上膛模式，摩擦轮开启。随时准备开火 */
+} CMD_ShootMode_t;
+
+typedef enum {
+  FIRE_MODE_SINGLE, /* 单发开火模式  */
+  FIRE_MODE_BURST,  /* N连发开火模式 */
+  FIRE_MODE_CONT,   /* 持续开火模式 */
+  FIRE_MODE_NUM,
+} CMD_FireMode_t;
+
+/* 小陀螺转动模式 */
+typedef enum {
+  ROTOR_MODE_CW,   /* 顺时针转动 */
+  ROTOR_MODE_CCW,  /* 逆时针转动 */
+  ROTOR_MODE_RAND, /* 随机转动 */
+} CMD_RotorMode_t;
+
+/* 底盘控制命令 */
+typedef struct {
+  CMD_ChassisMode_t mode;     /* 底盘运行模式 */
+  CMD_RotorMode_t mode_rotor; /* 小陀螺转动模式 */
+  MoveVector_t ctrl_vec;      /* 底盘控制向量 */
+} CMD_ChassisCmd_t;
+
+/* 云台控制命令 */
+typedef struct {
+  CMD_GimbalMode_t mode;  /* 云台运行模式 */
+  AHRS_Eulr_t delta_eulr; /* 欧拉角变化角度 */
+} CMD_GimbalCmd_t;
+
+/* 射击控制命令 */
+typedef struct {
+  CMD_ShootMode_t mode;     /* 射击运行模式 */
+  CMD_FireMode_t fire_mode; /* 开火模式 */
+  bool fire;                /*开火*/
+  bool cover_open;          /* 弹舱盖开关 */
+  bool reverse_trig;        /* 拨弹电机状态 */
+} CMD_ShootCmd_t;
+
+/* 拨杆位置 */
+typedef enum {
+  CMD_SW_ERR = 0,
+  CMD_SW_UP = 1,
+  CMD_SW_MID = 3,
+  CMD_SW_DOWN = 2,
+} CMD_SwitchPos_t;
+
+/* 键盘按键值 */
+typedef enum {
+  CMD_KEY_W = 0,
+  CMD_KEY_S,
+  CMD_KEY_A,
+  CMD_KEY_D,
+  CMD_KEY_SHIFT,
+  CMD_KEY_CTRL,
+  CMD_KEY_Q,
+  CMD_KEY_E,
+  CMD_KEY_R,
+  CMD_KEY_F,
+  CMD_KEY_G,
+  CMD_KEY_Z,
+  CMD_KEY_X,
+  CMD_KEY_C,
+  CMD_KEY_V,
+  CMD_KEY_B,
+  CMD_L_CLICK,
+  CMD_R_CLICK,
+  CMD_KEY_NUM,
+} CMD_KeyValue_t;
+
+/* 行为值序列 */
+typedef enum {
+  CMD_BEHAVIOR_FORE = 0,       /* 向前 */
+  CMD_BEHAVIOR_BACK,           /* 向后 */
+  CMD_BEHAVIOR_LEFT,           /* 向左 */
+  CMD_BEHAVIOR_RIGHT,          /* 向右 */
+  CMD_BEHAVIOR_ACCELERATE,     /* 加速 */
+  CMD_BEHAVIOR_DECELEBRATE,    /* 减速 */
+  CMD_BEHAVIOR_FIRE,           /* 开火 */
+  CMD_BEHAVIOR_FIRE_MODE,      /* 切换开火模式 */
+  CMD_BEHAVIOR_BUFF,           /* 打符模式 */
+  CMD_BEHAVIOR_AUTOAIM,        /* 自瞄模式 */
+  CMD_BEHAVIOR_OPENCOVER,      /* 弹舱盖开关 */
+  CMD_BEHAVIOR_ROTOR,          /* 小陀螺模式 */
+  CMD_BEHAVIOR_REVTRIG,        /* 反转拨弹 */
+  CMD_BEHAVIOR_FOLLOWGIMBAL35, /* 跟随云台呈35度 */
+  CMD_BEHAVIOR_NUM,
+} CMD_Behavior_t;
+
+typedef enum {
+  CMD_ACTIVE_PRESSING, /* 按下时触发 */
+  CMD_ACTIVE_RASING,   /* 抬起时触发 */
+  CMD_ACTIVE_PRESSED,  /* 按住时触发 */
+} CMD_ActiveType_t;
+
+typedef struct {
+  CMD_ActiveType_t active;
+  CMD_KeyValue_t key;
+} CMD_KeyMapItem_t;
+
+/* 行为映射的对应按键数组 */
+typedef struct {
+  CMD_KeyMapItem_t key_map[CMD_BEHAVIOR_NUM];
+} CMD_KeyMap_Params_t;
+
+/* 位移灵敏度参数 */
+typedef struct {
+  float move_sense;      /* 移动灵敏度 */
+  float move_fast_sense; /* 加速灵敏度 */
+  float move_slow_sense; /* 减速灵敏度 */
+} CMD_Move_Params_t;
+
+typedef struct {
+  uint16_t width;
+  uint16_t height;
+} CMD_Screen_t;
+
+/* 命令参数 */
+typedef struct {
+  float sens_mouse;        /* 鼠标灵敏度 */
+  float sens_rc;           /* 遥控器摇杆灵敏度 */
+  CMD_KeyMap_Params_t map; /* 按键映射行为命令 */
+  CMD_Move_Params_t move;  /* 位移灵敏度参数 */
+  CMD_Screen_t screen;     /* 屏幕分辨率参数 */
+} CMD_Params_t;
+
+/* AI行为状态 */
+typedef enum {
+  AI_STATUS_STOP,      /* 停止状态 */
+  AI_STATUS_AUTOAIM,   /* 自瞄状态 */
+  AI_STATUS_HITSWITCH, /* 打符状态 */
+  AI_STATUS_AUTOMATIC  /* 自动状态 */
+} CMD_AI_Status_t;
+
+/* UI所用行为状态 */
+typedef enum {
+  CMD_UI_NOTHING,          /* 当前无状态 */
+  CMD_UI_AUTO_AIM_START,   /* 自瞄状态开启 */
+  CMD_UI_AUTO_AIM_STOP,    /* 自瞄状态关闭 */
+  CMD_UI_HIT_SWITCH_START, /* 打符状态开启 */
+  CMD_UI_HIT_SWITCH_STOP   /* 打符状态关闭 */
+} CMD_UI_t;
+
+/*裁判系统发送的命令*/
+typedef struct {
+  CMD_UI_t cmd[CMD_REFEREE_MAX_NUM]; /* 命令数组 */
+  uint8_t counter;                   /* 命令计数 */
+} CMD_RefereeCmd_t;
+
+typedef struct {
+  bool pc_ctrl;        /* 是否使用键鼠控制 */
+  bool host_overwrite; /* 是否Host控制 */
+  uint16_t key_last;   /* 上次按键键值 */
+
+  struct {
+    int16_t x;
+    int16_t y;
+    int16_t z;
+    bool l_click; /* 左键 */
+    bool r_click; /* 右键 */
+  } mouse_last;   /* 鼠标值 */
+
+  CMD_AI_Status_t ai_status; /* AI状态 */
+
+  const CMD_Params_t *param; /* 命令参数 */
+
+  CMD_ChassisCmd_t chassis; /* 底盘控制命令 */
+  CMD_GimbalCmd_t gimbal;   /* 云台控制命令 */
+  CMD_ShootCmd_t shoot;     /* 射击控制命令 */
+  CMD_RefereeCmd_t referee; /* 裁判系统发送命令 */
+} CMD_t;
+
+typedef struct {
+  float ch_l_x; /* 遥控器左侧摇杆横轴值，上为正 */
+  float ch_l_y; /* 遥控器左侧摇杆纵轴值，右为正 */
+  float ch_r_x; /* 遥控器右侧摇杆横轴值，上为正 */
+  float ch_r_y; /* 遥控器右侧摇杆纵轴值，右为正 */
+
+  float ch_res; /* 第五通道值 */
+
+  CMD_SwitchPos_t sw_r; /* 右侧拨杆位置 */
+  CMD_SwitchPos_t sw_l; /* 左侧拨杆位置 */
+
+  struct {
+    int16_t x;
+    int16_t y;
+    int16_t z;
+    bool l_click; /* 左键 */
+    bool r_click; /* 右键 */
+  } mouse;        /* 鼠标值 */
+
+  uint16_t key; /* 按键值 */
+
+  uint16_t res; /* 保留，未启用 */
+} CMD_RC_t;
+
+typedef struct {
+  AHRS_Eulr_t gimbal_delta; /* 欧拉角的变化量 */
+
+  struct {
+    float vx;         /* x轴移动速度 */
+    float vy;         /* y轴移动速度 */
+    float wz;         /* z轴转动速度 */
+  } chassis_move_vec; /* 底盘移动向量 */
+
+  bool fire; /* 开火状态 */
+} CMD_Host_t;
+
+/**
+ * @brief 解析行为命令
+ *
+ * @param rc 遥控器数据
+ * @param cmd 主结构体
+ */
+int8_t CMD_Init(CMD_t *cmd, const CMD_Params_t *param);
+
+/**
+ * @brief 检查是否启用上位机控制指令覆盖
+ *
+ * @param cmd 主结构体
+ * @return true 启用
+ * @return false 不启用
+ */
+bool CMD_CheckHostOverwrite(CMD_t *cmd);
+
+/**
+ * @brief 解析命令
+ *
+ * @param rc 遥控器数据
+ * @param cmd 命令
+ * @param dt_sec 两次解析的间隔
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_ParseRc(CMD_RC_t *rc, CMD_t *cmd, float dt_sec);
+
+/**
+ * @brief 解析上位机命令
+ *
+ * @param host host数据
+ * @param cmd 命令
+ * @param dt_sec 两次解析的间隔
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_ParseHost(const CMD_Host_t *host, CMD_t *cmd, float dt_sec);
+
+/**
+ * @brief 添加向Referee发送的命令
+ *
+ * @param ref 命令队列
+ * @param cmd 要添加的命令
+ * @return int8_t 0对应没有错误
+ */
+int8_t CMD_RefereeAdd(CMD_RefereeCmd_t *ref, CMD_UI_t cmd);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/component_config.yaml b/User/component/component_config.yaml
new file mode 100644
index 0000000..d378c3a
--- /dev/null
+++ b/User/component/component_config.yaml
@@ -0,0 +1,47 @@
+ahrs:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+capacity:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+cmd:
+  dependencies:
+  - component/ahrs
+  enabled: true
+crc16:
+  dependencies: []
+  enabled: true
+crc8:
+  dependencies: []
+  enabled: true
+error_detect:
+  dependencies:
+  - bsp/mm
+  enabled: true
+filter:
+  dependencies:
+  - component/ahrs
+  enabled: true
+freertos_cli:
+  dependencies: []
+  enabled: true
+limiter:
+  dependencies: []
+  enabled: true
+mixer:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+pid:
+  dependencies:
+  - component/filter
+  enabled: true
+ui:
+  dependencies:
+  - component/user_math.h
+  enabled: true
+user_math:
+  dependencies: []
+  enabled: true
diff --git a/User/component/crc16.c b/User/component/crc16.c
new file mode 100644
index 0000000..0d17eb0
--- /dev/null
+++ b/User/component/crc16.c
@@ -0,0 +1,62 @@
+#include "crc16.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+static const uint16_t crc16_tab[256] = {
+    0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48,
+    0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108,
+    0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb,
+    0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399,
+    0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e,
+    0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e,
+    0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd,
+    0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
+    0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285,
+    0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44,
+    0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, 0x6306, 0x728f, 0x4014,
+    0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, 0xef4e, 0xfec7, 0xcc5c, 0xddd5,
+    0xa96a, 0xb8e3, 0x8a78, 0x9bf1, 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3,
+    0x242a, 0x16b1, 0x0738, 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862,
+    0x9af9, 0x8b70, 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e,
+    0xf0b7, 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
+    0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, 0x18c1,
+    0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, 0xa50a, 0xb483,
+    0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, 0x2942, 0x38cb, 0x0a50,
+    0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, 0xb58b, 0xa402, 0x9699, 0x8710,
+    0xf3af, 0xe226, 0xd0bd, 0xc134, 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7,
+    0x6e6e, 0x5cf5, 0x4d7c, 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1,
+    0xa33a, 0xb2b3, 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72,
+    0x3efb, 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
+    0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, 0xe70e,
+    0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, 0x6b46, 0x7acf,
+    0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, 0xf78f, 0xe606, 0xd49d,
+    0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, 0x7bc7, 0x6a4e, 0x58d5, 0x495c,
+    0x3de3, 0x2c6a, 0x1ef1, 0x0f78};
+
+static inline uint16_t CRC16_Byte(uint16_t crc, const uint8_t data) {
+  return (crc >> 8) ^ crc16_tab[(crc ^ data) & 0xff];
+}
+
+uint16_t CRC16_Calc(const uint8_t *buf, size_t len, uint16_t crc) {
+  while (len--) crc = CRC16_Byte(crc, *buf++);
+  return crc;
+}
+
+bool CRC16_Verify(const uint8_t *buf, size_t len) {
+  if (len < 2) return false;
+
+  uint16_t expected = CRC16_Calc(buf, len - sizeof(uint16_t), CRC16_INIT);
+  return expected ==
+         ((const uint16_t *)((const uint8_t *)buf +
+                             (len % 2)))[len / sizeof(uint16_t) - 1];
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/crc16.h b/User/component/crc16.h
new file mode 100644
index 0000000..68b0a87
--- /dev/null
+++ b/User/component/crc16.h
@@ -0,0 +1,30 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define CRC16_INIT 0XFFFF
+
+uint16_t CRC16_Calc(const uint8_t *buf, size_t len, uint16_t crc);
+bool CRC16_Verify(const uint8_t *buf, size_t len);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/crc8.c b/User/component/crc8.c
new file mode 100644
index 0000000..66f4ad2
--- /dev/null
+++ b/User/component/crc8.c
@@ -0,0 +1,52 @@
+#include "crc8.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+static const uint8_t crc8_tab[256] = {
+    0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83, 0xc2, 0x9c, 0x7e, 0x20,
+    0xa3, 0xfd, 0x1f, 0x41, 0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+    0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc, 0x23, 0x7d, 0x9f, 0xc1,
+    0x42, 0x1c, 0xfe, 0xa0, 0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+    0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d, 0x7c, 0x22, 0xc0, 0x9e,
+    0x1d, 0x43, 0xa1, 0xff, 0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+    0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07, 0xdb, 0x85, 0x67, 0x39,
+    0xba, 0xe4, 0x06, 0x58, 0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+    0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6, 0xa7, 0xf9, 0x1b, 0x45,
+    0xc6, 0x98, 0x7a, 0x24, 0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+    0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9, 0x8c, 0xd2, 0x30, 0x6e,
+    0xed, 0xb3, 0x51, 0x0f, 0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+    0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92, 0xd3, 0x8d, 0x6f, 0x31,
+    0xb2, 0xec, 0x0e, 0x50, 0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+    0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee, 0x32, 0x6c, 0x8e, 0xd0,
+    0x53, 0x0d, 0xef, 0xb1, 0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+    0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49, 0x08, 0x56, 0xb4, 0xea,
+    0x69, 0x37, 0xd5, 0x8b, 0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+    0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16, 0xe9, 0xb7, 0x55, 0x0b,
+    0x88, 0xd6, 0x34, 0x6a, 0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+    0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7, 0xb6, 0xe8, 0x0a, 0x54,
+    0xd7, 0x89, 0x6b, 0x35,
+};
+
+uint8_t CRC8_Calc(const uint8_t *buf, size_t len, uint8_t crc) {
+  /* loop over the buffer data */
+  while (len-- > 0) crc = crc8_tab[(crc ^ *buf++) & 0xff];
+
+  return crc;
+}
+
+bool CRC8_Verify(const uint8_t *buf, size_t len) {
+  if (len < 2) return false;
+
+  uint8_t expected = CRC8_Calc(buf, len - sizeof(uint8_t), CRC8_INIT);
+  return expected == buf[len - sizeof(uint8_t)];
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/component/crc8.h b/User/component/crc8.h
new file mode 100644
index 0000000..a376c71
--- /dev/null
+++ b/User/component/crc8.h
@@ -0,0 +1,30 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define CRC8_INIT 0xFF
+
+uint8_t CRC8_Calc(const uint8_t *buf, size_t len, uint8_t crc);
+bool CRC8_Verify(const uint8_t *buf, size_t len);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/error_detect.c b/User/component/error_detect.c
new file mode 100644
index 0000000..b29e591
--- /dev/null
+++ b/User/component/error_detect.c
@@ -0,0 +1,67 @@
+/*
+  错误检测。
+*/
+
+#include "error_detect.h"
+
+#include 
+#include 
+
+#include "bsp/mm.h"
+
+static ErrorDetect_t ged;
+static bool inited = false;
+
+int8_t ErrorDetect_Init(void) {
+  if (inited) return -1;
+
+  memset(&ged, 0x00, sizeof(ged));
+
+  for (uint8_t i = 0; i < ERROR_DETECT_UNIT_NUM; i++) {
+    ged.error[i].enable = true;
+    ged.error[i].priority = i;
+    ged.error[i].patient_lost = 500;
+    ged.error[i].patient_work = 500;
+  }
+  return 0;
+}
+
+void ErrorDetect_Processing(uint32_t sys_time) {
+  for (uint8_t i = 0; i < ERROR_DETECT_UNIT_NUM; i++) {
+    if (!ged.error[i].enable) continue;
+
+    if (sys_time - ged.error[i].showup > ged.error[i].patient_lost) {
+      ged.error[i].is_lost = true;
+      ged.error[i].found_lost = sys_time;
+    } else if (sys_time - ged.error[i].showup > ged.error[i].patient_lost) {
+    } else {
+      ged.error[i].cycle_time = ged.error[i].showup - ged.error[i].showup_last;
+    }
+  }
+}
+
+bool ErrorDetect_ErrorExist(ErrorDetect_Unit_t unit) {
+  if (unit == ERROR_DETECT_UNIT_NO_DEV) {
+    for (uint8_t i = ERROR_DETECT_UNIT_NUM; i > 0; i--) {
+      if (ged.error[i].error_exist) return true;
+    }
+    return false;
+  } else {
+    return ged.error[unit].error_exist;
+  }
+}
+
+ErrorDetect_Unit_t ErrorDetect_GetErrorUnit(void) {
+  for (uint8_t i = ERROR_DETECT_UNIT_NUM; i > 0; i--) {
+    if (ged.error[i].error_exist) return i;
+  }
+  return ERROR_DETECT_UNIT_NO_DEV;
+}
+
+const ErrorDetect_Error_t *ErrorDetect_GetDetail(ErrorDetect_Unit_t unit) {
+  return &ged.error[unit];
+}
+
+void ErrorDetect_Update(ErrorDetect_Unit_t unit, uint32_t time_current) {
+  ged.error[unit].showup = time_current;
+}
diff --git a/User/component/error_detect.h b/User/component/error_detect.h
new file mode 100644
index 0000000..3dba7a2
--- /dev/null
+++ b/User/component/error_detect.h
@@ -0,0 +1,82 @@
+/*
+  错误检测。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+typedef enum {
+  /* Low priority */
+  ERROR_DETECT_UNIT_NO_DEV = 0,
+  ERROR_DETECT_UNIT_REFEREE,
+  ERROR_DETECT_UNIT_CHASSIS_M1,
+  ERROR_DETECT_UNIT_CHASSIS_M2,
+  ERROR_DETECT_UNIT_CHASSIS_M3,
+  ERROR_DETECT_UNIT_CHASSIS_M4,
+  ERROR_DETECT_UNIT_TRIGGER,
+  ERROR_DETECT_UNIT_FEED,
+  ERROR_DETECT_UNIT_GIMBAL_YAW,
+  ERROR_DETECT_UNIT_GIMBAL_PIT,
+  ERROR_DETECT_UNIT_GYRO,
+  ERROR_DETECT_UNIT_ACCL,
+  ERROR_DETECT_UNIT_MAGN,
+  ERROR_DETECT_UNIT_DBUS,
+  ERROR_DETECT_UNIT_NUM,
+  /* High priority */
+} ErrorDetect_Unit_t;
+
+typedef struct {
+  bool enable;
+  uint8_t priority;
+  uint32_t patient_lost;
+  uint32_t patient_work;
+
+  uint32_t showup;
+  uint32_t showup_last;
+  uint32_t cycle_time;
+  uint32_t duration_lost;
+  uint32_t duration_work;
+  uint32_t found_lost;
+  bool error_exist;
+  bool is_lost;
+  uint8_t data_is_error;
+
+} ErrorDetect_Error_t;
+
+typedef struct {
+  ErrorDetect_Error_t error[ERROR_DETECT_UNIT_NUM];
+} ErrorDetect_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+int8_t ErrorDetect_Init(void);
+void ErrorDetect_Processing(uint32_t sys_time);
+bool ErrorDetect_ErrorExist(ErrorDetect_Unit_t unit);
+ErrorDetect_Unit_t ErrorDetect_GetErrorUnit(void);
+const ErrorDetect_Error_t *ErrorDetect_GetDetail(ErrorDetect_Unit_t unit);
+
+void ErrorDetect_Update(ErrorDetect_Unit_t unit, uint32_t time_current);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/filter.c b/User/component/filter.c
new file mode 100644
index 0000000..5375b8e
--- /dev/null
+++ b/User/component/filter.c
@@ -0,0 +1,185 @@
+/*
+  各类滤波器。
+*/
+
+#include "filter.h"
+
+#include "user_math.h"
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq) {
+  if (f == NULL) return;
+
+  f->cutoff_freq = cutoff_freq;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (f->cutoff_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+  const float fr = sample_freq / f->cutoff_freq;
+  const float ohm = tanf(M_PI / fr);
+  const float c = 1.0f + 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm;
+
+  f->b0 = ohm * ohm / c;
+  f->b1 = 2.0f * f->b0;
+  f->b2 = f->b0;
+
+  f->a1 = 2.0f * (ohm * ohm - 1.0f) / c;
+  f->a2 = (1.0f - 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm) / c;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* do the filtering */
+  float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+
+  if (isinf(delay_element_0)) {
+    /* don't allow bad values to propagate via the filter */
+    delay_element_0 = sample;
+  }
+
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  /* return the value. Should be no need to check limits */
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  const float dval = sample / (f->b0 + f->b1 + f->b2);
+
+  if (isfinite(dval)) {
+    f->delay_element_1 = dval;
+    f->delay_element_2 = dval;
+
+  } else {
+    f->delay_element_1 = sample;
+    f->delay_element_2 = sample;
+  }
+
+  return LowPassFilter2p_Apply(f, sample);
+}
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth) {
+  if (f == NULL) return;
+
+  f->notch_freq = notch_freq;
+  f->bandwidth = bandwidth;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (notch_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+
+  const float alpha = tanf(M_PI * bandwidth / sample_freq);
+  const float beta = -cosf(M_2PI * notch_freq / sample_freq);
+  const float a0_inv = 1.0f / (alpha + 1.0f);
+
+  f->b0 = a0_inv;
+  f->b1 = 2.0f * beta * a0_inv;
+  f->b2 = a0_inv;
+
+  f->a1 = f->b1;
+  f->a2 = (1.0f - alpha) * a0_inv;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+inline float NotchFilter_Apply(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* Direct Form II implementation */
+  const float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  float dval = sample;
+
+  if (fabsf(f->b0 + f->b1 + f->b2) > FLT_EPSILON) {
+    dval = dval / (f->b0 + f->b1 + f->b2);
+  }
+
+  f->delay_element_1 = dval;
+  f->delay_element_2 = dval;
+
+  return NotchFilter_Apply(f, sample);
+}
diff --git a/User/component/filter.h b/User/component/filter.h
new file mode 100644
index 0000000..ae2b072
--- /dev/null
+++ b/User/component/filter.h
@@ -0,0 +1,120 @@
+/*
+  各类滤波器。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 二阶低通滤波器 */
+typedef struct {
+  float cutoff_freq; /* 截止频率 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+
+  float delay_element_1;
+  float delay_element_2;
+
+} LowPassFilter2p_t;
+
+/* 带阻滤波器 */
+typedef struct {
+  float notch_freq; /* 阻止频率 */
+  float bandwidth;  /* 带宽 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+  float delay_element_1;
+  float delay_element_2;
+
+} NotchFilter_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Apply(NotchFilter_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/filter/filter.c b/User/component/filter/filter.c
new file mode 100644
index 0000000..5375b8e
--- /dev/null
+++ b/User/component/filter/filter.c
@@ -0,0 +1,185 @@
+/*
+  各类滤波器。
+*/
+
+#include "filter.h"
+
+#include "user_math.h"
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq) {
+  if (f == NULL) return;
+
+  f->cutoff_freq = cutoff_freq;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (f->cutoff_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+  const float fr = sample_freq / f->cutoff_freq;
+  const float ohm = tanf(M_PI / fr);
+  const float c = 1.0f + 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm;
+
+  f->b0 = ohm * ohm / c;
+  f->b1 = 2.0f * f->b0;
+  f->b2 = f->b0;
+
+  f->a1 = 2.0f * (ohm * ohm - 1.0f) / c;
+  f->a2 = (1.0f - 2.0f * cosf(M_PI / 4.0f) * ohm + ohm * ohm) / c;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* do the filtering */
+  float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+
+  if (isinf(delay_element_0)) {
+    /* don't allow bad values to propagate via the filter */
+    delay_element_0 = sample;
+  }
+
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  /* return the value. Should be no need to check limits */
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  const float dval = sample / (f->b0 + f->b1 + f->b2);
+
+  if (isfinite(dval)) {
+    f->delay_element_1 = dval;
+    f->delay_element_2 = dval;
+
+  } else {
+    f->delay_element_1 = sample;
+    f->delay_element_2 = sample;
+  }
+
+  return LowPassFilter2p_Apply(f, sample);
+}
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth) {
+  if (f == NULL) return;
+
+  f->notch_freq = notch_freq;
+  f->bandwidth = bandwidth;
+
+  f->delay_element_1 = 0.0f;
+  f->delay_element_2 = 0.0f;
+
+  if (notch_freq <= 0.0f) {
+    /* no filtering */
+    f->b0 = 1.0f;
+    f->b1 = 0.0f;
+    f->b2 = 0.0f;
+
+    f->a1 = 0.0f;
+    f->a2 = 0.0f;
+
+    return;
+  }
+
+  const float alpha = tanf(M_PI * bandwidth / sample_freq);
+  const float beta = -cosf(M_2PI * notch_freq / sample_freq);
+  const float a0_inv = 1.0f / (alpha + 1.0f);
+
+  f->b0 = a0_inv;
+  f->b1 = 2.0f * beta * a0_inv;
+  f->b2 = a0_inv;
+
+  f->a1 = f->b1;
+  f->a2 = (1.0f - alpha) * a0_inv;
+}
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+inline float NotchFilter_Apply(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  /* Direct Form II implementation */
+  const float delay_element_0 =
+      sample - f->delay_element_1 * f->a1 - f->delay_element_2 * f->a2;
+  const float output = delay_element_0 * f->b0 + f->delay_element_1 * f->b1 +
+                       f->delay_element_2 * f->b2;
+
+  f->delay_element_2 = f->delay_element_1;
+  f->delay_element_1 = delay_element_0;
+
+  return output;
+}
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample) {
+  if (f == NULL) return 0.0f;
+
+  float dval = sample;
+
+  if (fabsf(f->b0 + f->b1 + f->b2) > FLT_EPSILON) {
+    dval = dval / (f->b0 + f->b1 + f->b2);
+  }
+
+  f->delay_element_1 = dval;
+  f->delay_element_2 = dval;
+
+  return NotchFilter_Apply(f, sample);
+}
diff --git a/User/component/filter/filter.h b/User/component/filter/filter.h
new file mode 100644
index 0000000..ae2b072
--- /dev/null
+++ b/User/component/filter/filter.h
@@ -0,0 +1,120 @@
+/*
+  各类滤波器。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* 二阶低通滤波器 */
+typedef struct {
+  float cutoff_freq; /* 截止频率 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+
+  float delay_element_1;
+  float delay_element_2;
+
+} LowPassFilter2p_t;
+
+/* 带阻滤波器 */
+typedef struct {
+  float notch_freq; /* 阻止频率 */
+  float bandwidth;  /* 带宽 */
+
+  float a1;
+  float a2;
+
+  float b0;
+  float b1;
+  float b2;
+  float delay_element_1;
+  float delay_element_2;
+
+} NotchFilter_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param cutoff_freq 截止频率
+ */
+void LowPassFilter2p_Init(LowPassFilter2p_t *f, float sample_freq,
+                          float cutoff_freq);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Apply(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float LowPassFilter2p_Reset(LowPassFilter2p_t *f, float sample);
+
+/**
+ * @brief 初始化滤波器
+ *
+ * @param f 滤波器
+ * @param sample_freq 采样频率
+ * @param notch_freq 中心频率
+ * @param bandwidth 带宽
+ */
+void NotchFilter_Init(NotchFilter_t *f, float sample_freq, float notch_freq,
+                      float bandwidth);
+
+/**
+ * @brief 施加一次滤波计算
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Apply(NotchFilter_t *f, float sample);
+
+/**
+ * @brief 重置滤波器
+ *
+ * @param f 滤波器
+ * @param sample 采样的值
+ * @return float 滤波后的值
+ */
+float NotchFilter_Reset(NotchFilter_t *f, float sample);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/freertos_cli.c b/User/component/freertos_cli.c
new file mode 100644
index 0000000..32421de
--- /dev/null
+++ b/User/component/freertos_cli.c
@@ -0,0 +1,352 @@
+/*
+ * FreeRTOS+CLI V1.0.4
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include 
+#include 
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Utils includes. */
+#include "FreeRTOS_CLI.h"
+
+/* If the application writer needs to place the buffer used by the CLI at a
+fixed address then set configAPPLICATION_PROVIDES_cOutputBuffer to 1 in
+FreeRTOSConfig.h, then declare an array with the following name and size in 
+one of the application files:
+	char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ];
+*/
+#ifndef configAPPLICATION_PROVIDES_cOutputBuffer
+	#define configAPPLICATION_PROVIDES_cOutputBuffer 0
+#endif
+
+typedef struct xCOMMAND_INPUT_LIST
+{
+	const CLI_Command_Definition_t *pxCommandLineDefinition;
+	struct xCOMMAND_INPUT_LIST *pxNext;
+} CLI_Definition_List_Item_t;
+
+/*
+ * The callback function that is executed when "help" is entered.  This is the
+ * only default command that is always present.
+ */
+static BaseType_t prvHelpCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/*
+ * Return the number of parameters that follow the command name.
+ */
+static int8_t prvGetNumberOfParameters( const char *pcCommandString );
+
+/* The definition of the "help" command.  This command is always at the front
+of the list of registered commands. */
+static const CLI_Command_Definition_t xHelpCommand =
+{
+	"help",
+	"\r\nhelp:\r\n Lists all the registered commands\r\n\r\n",
+	prvHelpCommand,
+	0
+};
+
+/* The definition of the list of commands.  Commands that are registered are
+added to this list. */
+static CLI_Definition_List_Item_t xRegisteredCommands =
+{
+	&xHelpCommand,	/* The first command in the list is always the help command, defined in this file. */
+	NULL			/* The next pointer is initialised to NULL, as there are no other registered commands yet. */
+};
+
+/* A buffer into which command outputs can be written is declared here, rather
+than in the command console implementation, to allow multiple command consoles
+to share the same buffer.  For example, an application may allow access to the
+command interpreter by UART and by Ethernet.  Sharing a buffer is done purely
+to save RAM.  Note, however, that the command console itself is not re-entrant,
+so only one command interpreter interface can be used at any one time.  For that
+reason, no attempt at providing mutual exclusion to the cOutputBuffer array is
+attempted.
+
+configAPPLICATION_PROVIDES_cOutputBuffer is provided to allow the application
+writer to provide their own cOutputBuffer declaration in cases where the
+buffer needs to be placed at a fixed address (rather than by the linker). */
+
+#if( configAPPLICATION_PROVIDES_cOutputBuffer == 0 )
+	static char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ];
+#else
+	extern char cOutputBuffer[ configCOMMAND_INT_MAX_OUTPUT_SIZE ];
+#endif
+
+
+/*---------------------------------------------------------- */
+
+BaseType_t FreeRTOS_CLIRegisterCommand( const CLI_Command_Definition_t * const pxCommandToRegister )
+{
+static CLI_Definition_List_Item_t *pxLastCommandInList = &xRegisteredCommands;
+CLI_Definition_List_Item_t *pxNewListItem;
+BaseType_t xReturn = pdFAIL;
+
+	/* Check the parameter is not NULL. */
+	configASSERT( pxCommandToRegister );
+
+	/* Create a new list item that will reference the command being registered. */
+	pxNewListItem = ( CLI_Definition_List_Item_t * ) pvPortMalloc( sizeof( CLI_Definition_List_Item_t ) );
+	configASSERT( pxNewListItem );
+
+	if( pxNewListItem != NULL )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Reference the command being registered from the newly created
+			list item. */
+			pxNewListItem->pxCommandLineDefinition = pxCommandToRegister;
+
+			/* The new list item will get added to the end of the list, so
+			pxNext has nowhere to point. */
+			pxNewListItem->pxNext = NULL;
+
+			/* Add the newly created list item to the end of the already existing
+			list. */
+			pxLastCommandInList->pxNext = pxNewListItem;
+
+			/* Set the end of list marker to the new list item. */
+			pxLastCommandInList = pxNewListItem;
+		}
+		taskEXIT_CRITICAL();
+
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
+/*---------------------------------------------------------- */
+
+BaseType_t FreeRTOS_CLIProcessCommand( const char * const pcCommandInput, char * pcWriteBuffer, size_t xWriteBufferLen  )
+{
+static const CLI_Definition_List_Item_t *pxCommand = NULL;
+BaseType_t xReturn = pdTRUE;
+const char *pcRegisteredCommandString;
+size_t xCommandStringLength;
+
+	/* Note:  This function is not re-entrant.  It must not be called from more
+	thank one task. */
+
+	if( pxCommand == NULL )
+	{
+		/* Search for the command string in the list of registered commands. */
+		for( pxCommand = &xRegisteredCommands; pxCommand != NULL; pxCommand = pxCommand->pxNext )
+		{
+			pcRegisteredCommandString = pxCommand->pxCommandLineDefinition->pcCommand;
+			xCommandStringLength = strlen( pcRegisteredCommandString );
+
+			/* To ensure the string lengths match exactly, so as not to pick up
+			a sub-string of a longer command, check the byte after the expected
+			end of the string is either the end of the string or a space before
+			a parameter. */
+			if( ( pcCommandInput[ xCommandStringLength ] == ' ' ) || ( pcCommandInput[ xCommandStringLength ] == 0x00 ) )
+			{
+				if( strncmp( pcCommandInput, pcRegisteredCommandString, xCommandStringLength ) == 0 )
+				{
+					/* The command has been found.  Check it has the expected
+					number of parameters.  If cExpectedNumberOfParameters is -1,
+					then there could be a variable number of parameters and no
+					check is made. */
+					if( pxCommand->pxCommandLineDefinition->cExpectedNumberOfParameters >= 0 )
+					{
+						if( prvGetNumberOfParameters( pcCommandInput ) != pxCommand->pxCommandLineDefinition->cExpectedNumberOfParameters )
+						{
+							xReturn = pdFALSE;
+						}
+					}
+
+					break;
+				}
+			}
+		}
+	}
+
+	if( ( pxCommand != NULL ) && ( xReturn == pdFALSE ) )
+	{
+		/* The command was found, but the number of parameters with the command
+		was incorrect. */
+		strncpy( pcWriteBuffer, "Incorrect command parameter(s).  Enter \"help\" to view a list of available commands.\r\n\r\n", xWriteBufferLen );
+		pxCommand = NULL;
+	}
+	else if( pxCommand != NULL )
+	{
+		/* Call the callback function that is registered to this command. */
+		xReturn = pxCommand->pxCommandLineDefinition->pxCommandInterpreter( pcWriteBuffer, xWriteBufferLen, pcCommandInput );
+
+		/* If xReturn is pdFALSE, then no further strings will be returned
+		after this one, and	pxCommand can be reset to NULL ready to search
+		for the next entered command. */
+		if( xReturn == pdFALSE )
+		{
+			pxCommand = NULL;
+		}
+	}
+	else
+	{
+		/* pxCommand was NULL, the command was not found. */
+		strncpy( pcWriteBuffer, "Command not recognised.  Enter 'help' to view a list of available commands.\r\n\r\n", xWriteBufferLen );
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*---------------------------------------------------------- */
+
+char *FreeRTOS_CLIGetOutputBuffer( void )
+{
+	return cOutputBuffer;
+}
+/*---------------------------------------------------------- */
+
+const char *FreeRTOS_CLIGetParameter( const char *pcCommandString, UBaseType_t uxWantedParameter, BaseType_t *pxParameterStringLength )
+{
+UBaseType_t uxParametersFound = 0;
+const char *pcReturn = NULL;
+
+	*pxParameterStringLength = 0;
+
+	while( uxParametersFound < uxWantedParameter )
+	{
+		/* Index the character pointer past the current word.  If this is the start
+		of the command string then the first word is the command itself. */
+		while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) != ' ' ) )
+		{
+			pcCommandString++;
+		}
+
+		/* Find the start of the next string. */
+		while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) == ' ' ) )
+		{
+			pcCommandString++;
+		}
+
+		/* Was a string found? */
+		if( *pcCommandString != 0x00 )
+		{
+			/* Is this the start of the required parameter? */
+			uxParametersFound++;
+
+			if( uxParametersFound == uxWantedParameter )
+			{
+				/* How long is the parameter? */
+				pcReturn = pcCommandString;
+				while( ( ( *pcCommandString ) != 0x00 ) && ( ( *pcCommandString ) != ' ' ) )
+				{
+					( *pxParameterStringLength )++;
+					pcCommandString++;
+				}
+
+				if( *pxParameterStringLength == 0 )
+				{
+					pcReturn = NULL;
+				}
+
+				break;
+			}
+		}
+		else
+		{
+			break;
+		}
+	}
+
+	return pcReturn;
+}
+/*---------------------------------------------------------- */
+
+static BaseType_t prvHelpCommand( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString )
+{
+static const CLI_Definition_List_Item_t * pxCommand = NULL;
+BaseType_t xReturn;
+
+	( void ) pcCommandString;
+
+	if( pxCommand == NULL )
+	{
+		/* Reset the pxCommand pointer back to the start of the list. */
+		pxCommand = &xRegisteredCommands;
+	}
+
+	/* Return the next command help string, before moving the pointer on to
+	the next command in the list. */
+	strncpy( pcWriteBuffer, pxCommand->pxCommandLineDefinition->pcHelpString, xWriteBufferLen );
+	pxCommand = pxCommand->pxNext;
+
+	if( pxCommand == NULL )
+	{
+		/* There are no more commands in the list, so there will be no more
+		strings to return after this one and pdFALSE should be returned. */
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+/*---------------------------------------------------------- */
+
+static int8_t prvGetNumberOfParameters( const char *pcCommandString )
+{
+int8_t cParameters = 0;
+BaseType_t xLastCharacterWasSpace = pdFALSE;
+
+	/* Count the number of space delimited words in pcCommandString. */
+	while( *pcCommandString != 0x00 )
+	{
+		if( ( *pcCommandString ) == ' ' )
+		{
+			if( xLastCharacterWasSpace != pdTRUE )
+			{
+				cParameters++;
+				xLastCharacterWasSpace = pdTRUE;
+			}
+		}
+		else
+		{
+			xLastCharacterWasSpace = pdFALSE;
+		}
+
+		pcCommandString++;
+	}
+
+	/* If the command string ended with spaces, then there will have been too
+	many parameters counted. */
+	if( xLastCharacterWasSpace == pdTRUE )
+	{
+		cParameters--;
+	}
+
+	/* The value returned is one less than the number of space delimited words,
+	as the first word should be the command itself. */
+	return cParameters;
+}
+
diff --git a/User/component/freertos_cli.h b/User/component/freertos_cli.h
new file mode 100644
index 0000000..e6d8266
--- /dev/null
+++ b/User/component/freertos_cli.h
@@ -0,0 +1,108 @@
+/*
+ * FreeRTOS+CLI V1.0.4
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef COMMAND_INTERPRETER_H
+#define COMMAND_INTERPRETER_H
+
+/* This config should be defined in FreeRTOSConfig.h. But due to the limition of CubeMX I put it here. */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE  512
+
+/* The prototype to which callback functions used to process command line
+commands must comply.  pcWriteBuffer is a buffer into which the output from
+executing the command can be written, xWriteBufferLen is the length, in bytes of
+the pcWriteBuffer buffer, and pcCommandString is the entire string as input by
+the user (from which parameters can be extracted).*/
+typedef BaseType_t (*pdCOMMAND_LINE_CALLBACK)( char *pcWriteBuffer, size_t xWriteBufferLen, const char *pcCommandString );
+
+/* The structure that defines command line commands.  A command line command
+should be defined by declaring a const structure of this type. */
+typedef struct xCOMMAND_LINE_INPUT
+{
+	const char * const pcCommand;				/* The command that causes pxCommandInterpreter to be executed.  For example "help".  Must be all lower case. */
+	const char * const pcHelpString;			/* String that describes how to use the command.  Should start with the command itself, and end with "\r\n".  For example "help: Returns a list of all the commands\r\n". */
+	const pdCOMMAND_LINE_CALLBACK pxCommandInterpreter;	/* A pointer to the callback function that will return the output generated by the command. */
+	int8_t cExpectedNumberOfParameters;			/* Commands expect a fixed number of parameters, which may be zero. */
+} CLI_Command_Definition_t;
+
+/* For backward compatibility. */
+#define xCommandLineInput CLI_Command_Definition_t
+
+/*
+ * Register the command passed in using the pxCommandToRegister parameter.
+ * Registering a command adds the command to the list of commands that are
+ * handled by the command interpreter.  Once a command has been registered it
+ * can be executed from the command line.
+ */
+BaseType_t FreeRTOS_CLIRegisterCommand( const CLI_Command_Definition_t * const pxCommandToRegister );
+
+/*
+ * Runs the command interpreter for the command string "pcCommandInput".  Any
+ * output generated by running the command will be placed into pcWriteBuffer.
+ * xWriteBufferLen must indicate the size, in bytes, of the buffer pointed to
+ * by pcWriteBuffer.
+ *
+ * FreeRTOS_CLIProcessCommand should be called repeatedly until it returns pdFALSE.
+ *
+ * pcCmdIntProcessCommand is not reentrant.  It must not be called from more
+ * than one task - or at least - by more than one task at a time.
+ */
+BaseType_t FreeRTOS_CLIProcessCommand( const char * const pcCommandInput, char * pcWriteBuffer, size_t xWriteBufferLen  );
+
+/*---------------------------------------------------------- */
+
+/*
+ * A buffer into which command outputs can be written is declared in the
+ * main command interpreter, rather than in the command console implementation,
+ * to allow application that provide access to the command console via multiple
+ * interfaces to share a buffer, and therefore save RAM.  Note, however, that
+ * the command interpreter itself is not re-entrant, so only one command
+ * console interface can be used at any one time.  For that reason, no attempt
+ * is made to provide any mutual exclusion mechanism on the output buffer.
+ *
+ * FreeRTOS_CLIGetOutputBuffer() returns the address of the output buffer.
+ */
+char *FreeRTOS_CLIGetOutputBuffer( void );
+
+/*
+ * Return a pointer to the xParameterNumber'th word in pcCommandString.
+ */
+const char *FreeRTOS_CLIGetParameter( const char *pcCommandString, UBaseType_t uxWantedParameter, BaseType_t *pxParameterStringLength );
+
+#endif /* COMMAND_INTERPRETER_H */
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/User/component/limiter.c b/User/component/limiter.c
new file mode 100644
index 0000000..71e4bf1
--- /dev/null
+++ b/User/component/limiter.c
@@ -0,0 +1,107 @@
+/*
+  限制器
+*/
+
+#include "limiter.h"
+
+#include 
+#include 
+
+#define POWER_BUFF_THRESHOLD 20
+#define CHASSIS_POWER_CHECK_FREQ 10
+#define CHASSIS_POWER_FACTOR_PASS 0.9f
+#define CHASSIS_POWER_FACTOR_NO_PASS 1.5f
+
+#define CHASSIS_MOTOR_CIRCUMFERENCE 0.12f
+
+/**
+ * @brief 限制底盘功率不超过power_limit
+ *
+ * @param power_limit 最大功率
+ * @param motor_out 电机输出值
+ * @param speed 电机转速
+ * @param len 电机数量
+ * @return int8_t 0对应没有错误
+ */
+int8_t PowerLimit_ChassicOutput(float power_limit, float *motor_out,
+                                float *speed, uint32_t len) {
+  /* power_limit小于0时不进行限制 */
+  if (motor_out == NULL || speed == NULL || power_limit < 0) return -1;
+
+  float sum_motor_out = 0.0f;
+  for (uint32_t i = 0; i < len; i++) {
+    /* 总功率计算 P=F(由转矩电流表示)*V(由转速表示) */
+    sum_motor_out +=
+        fabsf(motor_out[i]) * fabsf(speed[i]) * CHASSIS_MOTOR_CIRCUMFERENCE;
+  }
+
+  /* 保持每个电机输出值缩小时比例不变 */
+  if (sum_motor_out > power_limit) {
+    for (uint32_t i = 0; i < len; i++) {
+      motor_out[i] *= power_limit / sum_motor_out;
+    }
+  }
+
+  return 0;
+}
+
+/**
+ * @brief 电容输入功率计算
+ *
+ * @param power_in 底盘当前功率
+ * @param power_limit 裁判系统功率限制值
+ * @param power_buffer 缓冲能量
+ * @return float 裁判系统输出最大值
+ */
+float PowerLimit_CapInput(float power_in, float power_limit,
+                          float power_buffer) {
+  float target_power = 0.0f;
+
+  /* 计算下一个检测周期的剩余缓冲能量 */
+  float heat_buff = power_buffer - (float)(power_in - power_limit) /
+                                       (float)CHASSIS_POWER_CHECK_FREQ;
+  if (heat_buff < POWER_BUFF_THRESHOLD) { /* 功率限制 */
+    target_power = power_limit * CHASSIS_POWER_FACTOR_PASS;
+  } else {
+    target_power = power_limit * CHASSIS_POWER_FACTOR_NO_PASS;
+  }
+
+  return target_power;
+}
+
+/**
+ * @brief 使用缓冲能量计算底盘最大功率
+ *
+ * @param power_limit 裁判系统功率限制值
+ * @param power_buffer 缓冲能量
+ * @return float 底盘输出最大值
+ */
+float PowerLimit_TargetPower(float power_limit, float power_buffer) {
+  float target_power = 0.0f;
+
+  /* 根据剩余缓冲能量计算输出功率 */
+  target_power = power_limit * (power_buffer - 10.0f) / 20.0f;
+  if (target_power < 0.0f) target_power = 0.0f;
+
+  return target_power;
+}
+
+/**
+ * @brief 射击频率控制
+ *
+ * @param heat 当前热量
+ * @param heat_limit 热量上限
+ * @param cooling_rate 冷却速率
+ * @param heat_increase 冷却增加
+ * @param shoot_freq 经过热量限制后的射击频率
+ * @return float 射击频率
+ */
+float HeatLimit_ShootFreq(float heat, float heat_limit, float cooling_rate,
+                          float heat_increase, bool is_big) {
+  float heat_percent = heat / heat_limit;
+  float stable_freq = cooling_rate / heat_increase;
+  if (is_big)
+    return stable_freq;
+  else
+    return (heat_percent > 0.7f) ? stable_freq : 3.0f * stable_freq;
+}
diff --git a/User/component/limiter.h b/User/component/limiter.h
new file mode 100644
index 0000000..d0aa92a
--- /dev/null
+++ b/User/component/limiter.h
@@ -0,0 +1,63 @@
+/*
+  限制器
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/**
+ * @brief 限制底盘功率不超过power_limit
+ *
+ * @param power_limit 最大功率
+ * @param motor_out 电机输出值
+ * @param speed 电机转速
+ * @param len 电机数量
+ * @return int8_t 0对应没有错误
+ */
+int8_t PowerLimit_ChassicOutput(float power_limit, float *motor_out,
+                                float *speed, uint32_t len);
+/**
+ * @brief 电容输入功率计算
+ *
+ * @param power_in 底盘当前功率
+ * @param power_limit 裁判系统功率限制值
+ * @param power_buffer 缓冲能量
+ * @return float 裁判系统输出最大值
+ */
+float PowerLimit_CapInput(float power_in, float power_limit,
+                          float power_buffer);
+/**
+ * @brief 使用缓冲能量计算底盘最大功率
+ *
+ * @param power_limit 裁判系统功率限制值
+ * @param power_buffer 缓冲能量
+ * @return float 底盘输出最大值
+ */
+float PowerLimit_TargetPower(float power_limit, float power_buffer);
+
+/**
+ * @brief 射击频率控制
+ *
+ * @param heat 当前热量
+ * @param heat_limit 热量上限
+ * @param cooling_rate 冷却速率
+ * @param heat_increase 冷却增加
+ * @param shoot_freq 经过热量限制后的射击频率
+ * @return float 射击频率
+ */
+float HeatLimit_ShootFreq(float heat, float heat_limit, float cooling_rate,
+                          float heat_increase, bool is_big);
diff --git a/User/component/mixer.c b/User/component/mixer.c
new file mode 100644
index 0000000..554b92e
--- /dev/null
+++ b/User/component/mixer.c
@@ -0,0 +1,94 @@
+/*
+  混合器
+*/
+
+#include "mixer.h"
+
+#include "math.h"
+
+/**
+ * @brief 初始化混合器
+ *
+ * @param mixer 混合器
+ * @param mode 混合器模式
+ * @return int8_t 0对应没有错误
+ */
+int8_t Mixer_Init(Mixer_t *mixer, Mixer_Mode_t mode) {
+  if (mixer == NULL) return -1;
+
+  mixer->mode = mode;
+  return 0;
+}
+
+/**
+ * @brief 计算输出
+ *
+ * @param mixer 混合器
+ * @param move_vec 运动向量
+ * @param out 输出数组
+ * @param len 输出数组长短
+ * @param scale 输出放大因子
+ * @return int8_t 0对应没有错误
+ */
+int8_t Mixer_Apply(Mixer_t *mixer, MoveVector_t *move_vec, float *out,
+                   int8_t len, float scale) {
+  if (mixer == NULL) return -1;
+
+  switch (mixer->mode) {
+    case MIXER_MECANUM:
+      if (len == 4) {
+        out[0] = move_vec->vx - move_vec->vy + move_vec->wz;
+        out[1] = move_vec->vx + move_vec->vy + move_vec->wz;
+        out[2] = -move_vec->vx + move_vec->vy + move_vec->wz;
+        out[3] = -move_vec->vx - move_vec->vy + move_vec->wz;
+      } else {
+        goto error;
+      }
+      break;
+
+    case MIXER_PARLFIX4:
+      if (len == 4) {
+        out[0] = -move_vec->vx;
+        out[1] = move_vec->vx;
+        out[2] = move_vec->vx;
+        out[3] = -move_vec->vx;
+      } else {
+        goto error;
+      }
+    case MIXER_PARLFIX2:
+      if (len == 2) {
+        out[0] = -move_vec->vx;
+        out[1] = move_vec->vx;
+      } else {
+        goto error;
+      }
+    case MIXER_SINGLE:
+      if (len == 1) {
+        out[0] = move_vec->vx;
+      } else {
+        goto error;
+      }
+    case MIXER_OMNICROSS:
+    case MIXER_OMNIPLUS:
+      goto error;
+  }
+
+  float abs_max = 0.f;
+  for (int8_t i = 0; i < len; i++) {
+    const float abs_val = fabsf(out[i]);
+    abs_max = (abs_val > abs_max) ? abs_val : abs_max;
+  }
+  if (abs_max > 1.f) {
+    for (int8_t i = 0; i < len; i++) {
+      out[i] /= abs_max;
+    }
+  }
+  for (int8_t i = 0; i < len; i++) {
+    out[i] *= scale;
+  }
+  return 0;
+
+error:
+  for (uint8_t i = 0; i < len; i++) out[i] = 0;
+  return -1;
+}
diff --git a/User/component/mixer.h b/User/component/mixer.h
new file mode 100644
index 0000000..b8e4401
--- /dev/null
+++ b/User/component/mixer.h
@@ -0,0 +1,76 @@
+/*
+  混合器
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/** 四轮布局 */
+/* 前 */
+/* 2 1 */
+/* 3 4 */
+
+/* 两轮布局 */
+/* 前 */
+/* 2 1 */
+
+/* 混合器模式 */
+typedef enum {
+  MIXER_MECANUM,   /* 麦克纳姆轮 */
+  MIXER_PARLFIX4,  /* 平行四驱动轮 */
+  MIXER_PARLFIX2,  /* 平行对侧两驱动轮 */
+  MIXER_OMNICROSS, /* 叉形全向轮 */
+  MIXER_OMNIPLUS,  /* 十字全向轮 */
+  MIXER_SINGLE,    /* 单个摩擦轮 */
+} Mixer_Mode_t;
+
+typedef struct {
+  Mixer_Mode_t mode;
+} Mixer_t; /* 混合器主结构体 */
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/**
+ * @brief 初始化混合器
+ *
+ * @param mixer 混合器
+ * @param mode 混合器模式
+ * @return int8_t 0对应没有错误
+ */
+int8_t Mixer_Init(Mixer_t *mixer, Mixer_Mode_t mode);
+
+/**
+ * @brief 计算输出
+ *
+ * @param mixer 混合器
+ * @param move_vec 运动向量
+ * @param out 输出数组
+ * @param len 输出数组长短
+ * @param scale 输出放大因子
+ * @return int8_t 0对应没有错误
+ */
+int8_t Mixer_Apply(Mixer_t *mixer, MoveVector_t *move_vec, float *out,
+                   int8_t len, float scale);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/pid.c b/User/component/pid.c
new file mode 100644
index 0000000..0a3c7d4
--- /dev/null
+++ b/User/component/pid.c
@@ -0,0 +1,158 @@
+/*
+   Modified from
+   https://github.com/PX4/Firmware/blob/master/src/lib/pid/pid.cpp
+
+   参考资料：
+   https://github.com/PX4/Firmware/issues/12362
+   https://dev.px4.io/master/en/flight_stack/controller_diagrams.html
+   https://docs.px4.io/master/en/config_mc/pid_tuning_guide_multicopter.html#standard_form
+   https://www.controleng.com/articles/not-all-pid-controllers-are-the-same/
+   https://en.wikipedia.org/wiki/PID_controller
+   http://brettbeauregard.com/blog/2011/04/improving-the-beginner%E2%80%99s-pid-derivative-kick/
+*/
+
+#include "pid.h"
+
+#define SIGMA 0.000001f
+
+/**
+ * @brief 初始化PID
+ *
+ * @param pid PID结构体
+ * @param mode PID模式
+ * @param sample_freq 采样频率
+ * @param param PID参数
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Init(KPID_t *pid, KPID_Mode_t mode, float sample_freq,
+                const KPID_Params_t *param) {
+  if (pid == NULL) return -1;
+
+  if (!isfinite(param->p)) return -1;
+  if (!isfinite(param->i)) return -1;
+  if (!isfinite(param->d)) return -1;
+  if (!isfinite(param->i_limit)) return -1;
+  if (!isfinite(param->out_limit)) return -1;
+  pid->param = param;
+
+  float dt_min = 1.0f / sample_freq;
+  if (isfinite(dt_min))
+    pid->dt_min = dt_min;
+  else
+    return -1;
+
+  LowPassFilter2p_Init(&(pid->dfilter), sample_freq, pid->param->d_cutoff_freq);
+
+  pid->mode = mode;
+  PID_Reset(pid);
+  return 0;
+}
+
+/**
+ * @brief PID计算
+ *
+ * @param pid PID结构体
+ * @param sp 设定值
+ * @param fb 反馈值
+ * @param fb_dot 反馈值微分
+ * @param dt 间隔时间
+ * @return float 计算的输出
+ */
+float PID_Calc(KPID_t *pid, float sp, float fb, float fb_dot, float dt) {
+  if (!isfinite(sp) || !isfinite(fb) || !isfinite(fb_dot) || !isfinite(dt)) {
+    return pid->last.out;
+  }
+
+  /* 计算误差值 */
+  const float err = CircleError(sp, fb, pid->param->range);
+
+  /* 计算P项 */
+  const float k_err = err * pid->param->k;
+
+  /* 计算D项 */
+  const float k_fb = pid->param->k * fb;
+  const float filtered_k_fb = LowPassFilter2p_Apply(&(pid->dfilter), k_fb);
+
+  float d;
+  switch (pid->mode) {
+    case KPID_MODE_CALC_D:
+      /* 通过fb计算D，避免了由于sp变化导致err突变的问题 */
+      /* 当sp不变时，err的微分等于负的fb的微分 */
+      d = (filtered_k_fb - pid->last.k_fb) / fmaxf(dt, pid->dt_min);
+      break;
+
+    case KPID_MODE_SET_D:
+      d = fb_dot;
+      break;
+
+    case KPID_MODE_NO_D:
+      d = 0.0f;
+      break;
+  }
+  pid->last.err = err;
+  pid->last.k_fb = filtered_k_fb;
+
+  if (!isfinite(d)) d = 0.0f;
+
+  /* 计算PD输出 */
+  float output = (k_err * pid->param->p) - (d * pid->param->d);
+
+  /* 计算I项 */
+  const float i = pid->i + (k_err * dt);
+  const float i_out = i * pid->param->i;
+  
+  if (pid->param->i > SIGMA) {
+    /* 检查是否饱和 */
+    if (isfinite(i)) {
+      if ((fabsf(output + i_out) <= pid->param->out_limit) &&
+          (fabsf(i) <= pid->param->i_limit)) {
+        /* 未饱和，使用新积分 */
+        pid->i = i;
+      }
+    }
+  }
+  
+  /* 计算PID输出 */
+  output += i_out;
+ 
+  /* 限制输出 */
+  if (isfinite(output)) {
+    if (pid->param->out_limit > SIGMA) {
+      output = AbsClip(output, pid->param->out_limit);
+    }
+    pid->last.out = output;
+  }
+  return pid->last.out;
+}
+
+/**
+ * @brief 重置微分项
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_ResetIntegral(KPID_t *pid) {
+  if (pid == NULL) return -1;
+
+  pid->i = 0.0f;
+
+  return 0;
+}
+
+/**
+ * @brief 重置PID
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Reset(KPID_t *pid) {
+  if (pid == NULL) return -1;
+
+  pid->i = 0.0f;
+  pid->last.err = 0.0f;
+  pid->last.k_fb = 0.0f;
+  pid->last.out = 0.0f;
+  LowPassFilter2p_Reset(&(pid->dfilter), 0.0f);
+
+  return 0;
+}
diff --git a/User/component/pid.h b/User/component/pid.h
new file mode 100644
index 0000000..4b451eb
--- /dev/null
+++ b/User/component/pid.h
@@ -0,0 +1,107 @@
+/*
+  Modified from
+  https://github.com/PX4/Firmware/blob/master/src/lib/pid/pid.h
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+
+#include "filter.h"
+#include "user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* PID模式 */
+typedef enum {
+  KPID_MODE_NO_D = 0, /* 不使用微分项，PI控制器 */
+  KPID_MODE_CALC_D, /* 根据反馈的值计算离散微分，忽略PID_Calc中的fb_dot */
+  KPID_MODE_SET_D /* 直接提供微分值，PID_Calc中的fb_dot将被使用，(Gyros) */
+} KPID_Mode_t;
+
+/* PID参数 */
+typedef struct {
+  float k;             /* 控制器增益，设置为1用于并行模式 */
+  float p;             /* 比例项增益，设置为1用于标准形式 */
+  float i;             /* 积分项增益 */
+  float d;             /* 微分项增益 */
+  float i_limit;       /* 积分项上限 */
+  float out_limit;     /* 输出绝对值限制 */
+  float d_cutoff_freq; /* D项低通截止频率 */
+  float range;         /* 计算循环误差时使用，大于0时启用 */
+} KPID_Params_t;
+
+/* PID主结构体 */
+typedef struct {
+  KPID_Mode_t mode;
+  const KPID_Params_t *param;
+
+  float dt_min; /* 最小PID_Calc调用间隔 */
+  float i;      /* 积分 */
+
+  struct {
+    float err;  /* 上次误差 */
+    float k_fb; /* 上次反馈值 */
+    float out;  /* 上次输出 */
+  } last;
+
+  LowPassFilter2p_t dfilter; /* D项低通滤波器 */
+} KPID_t;
+
+/**
+ * @brief 初始化PID
+ *
+ * @param pid PID结构体
+ * @param mode PID模式
+ * @param sample_freq 采样频率
+ * @param param PID参数
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Init(KPID_t *pid, KPID_Mode_t mode, float sample_freq,
+                const KPID_Params_t *param);
+
+/**
+ * @brief PID计算
+ *
+ * @param pid PID结构体
+ * @param sp 设定值
+ * @param fb 反馈值
+ * @param fb_dot 反馈值微分
+ * @param dt 间隔时间
+ * @return float 计算的输出
+ */
+float PID_Calc(KPID_t *pid, float sp, float fb, float fb_dot, float dt);
+
+/**
+ * @brief 重置微分项
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_ResetIntegral(KPID_t *pid);
+
+/**
+ * @brief 重置PID
+ *
+ * @param pid PID结构体
+ * @return int8_t 0对应没有错误
+ */
+int8_t PID_Reset(KPID_t *pid);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/component/ui.c b/User/component/ui.c
new file mode 100644
index 0000000..c3126bd
--- /dev/null
+++ b/User/component/ui.c
@@ -0,0 +1,301 @@
+/*
+  UI相关命令
+*/
+#include "component/ui.h"
+
+#include 
+
+/**
+ * @brief UI_绘制直线段
+ *
+ * @param grapic_line 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param x_end 终点x坐标
+ * @param y_end 终点y坐标
+ * @return int8_t
+ */
+int8_t UI_DrawLine(UI_Ele_t *grapic_line, const char *name, uint8_t type_op,
+                   uint8_t layer, uint8_t color, uint16_t width,
+                   uint16_t x_start, uint16_t y_start, uint16_t x_end,
+                   uint16_t y_end) {
+  if (grapic_line == NULL) return -1;
+  snprintf((char *)grapic_line->name, 2, "%s", name);
+  grapic_line->layer = layer;
+  grapic_line->type_op = type_op;
+  grapic_line->type_ele = 0;
+  grapic_line->color = color;
+  grapic_line->width = width;
+  grapic_line->x_start = x_start;
+  grapic_line->y_start = y_start;
+  grapic_line->x_end = x_end;
+  grapic_line->y_end = y_end;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制矩形
+ *
+ * @param grapic_rectangle 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param x_end 对角顶点x坐标
+ * @param y_end 对角顶点y坐标
+ * @return int8_t
+ */
+int8_t UI_DrawRectangle(UI_Ele_t *grapic_rectangle, const char *name,
+                        uint8_t type_op, uint8_t layer, uint8_t color,
+                        uint16_t width, uint16_t x_start, uint16_t y_start,
+                        uint16_t x_end, uint16_t y_end) {
+  if (grapic_rectangle == NULL) return -1;
+  snprintf((char *)grapic_rectangle->name, 2, "%s", name);
+  grapic_rectangle->type_op = type_op;
+  grapic_rectangle->type_ele = 1;
+  grapic_rectangle->layer = layer;
+  grapic_rectangle->color = color;
+  grapic_rectangle->width = width;
+  grapic_rectangle->x_start = x_start;
+  grapic_rectangle->y_start = y_start;
+  grapic_rectangle->x_end = x_end;
+  grapic_rectangle->y_end = y_end;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制正圆
+ *
+ * @param grapic_cycle 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param radius 半径
+ * @return int8_t
+ */
+int8_t UI_DrawCycle(UI_Ele_t *grapic_cycle, const char *name, uint8_t type_op,
+                    uint8_t layer, uint8_t color, uint16_t width,
+                    uint16_t x_center, uint16_t y_center, uint16_t radius) {
+  if (grapic_cycle == NULL) return -1;
+  snprintf((char *)grapic_cycle->name, 2, "%s", name);
+  grapic_cycle->type_op = type_op;
+  grapic_cycle->layer = layer;
+  grapic_cycle->type_ele = 2;
+  grapic_cycle->color = color;
+  grapic_cycle->width = width;
+  grapic_cycle->x_start = x_center;
+  grapic_cycle->y_start = y_center;
+  grapic_cycle->radius = radius;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制椭圆
+ *
+ * @param grapic_oval 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param x_semiaxis x半轴长度
+ * @param y_semiaxis y半轴长度
+ * @return int8_t
+ */
+int8_t UI_DrawOval(UI_Ele_t *grapic_oval, const char *name, uint8_t type_op,
+                   uint8_t layer, uint8_t color, uint16_t width,
+                   uint16_t x_center, uint16_t y_center, uint16_t x_semiaxis,
+                   uint16_t y_semiaxis) {
+  if (grapic_oval == NULL) return -1;
+  snprintf((char *)grapic_oval->name, 2, "%s", name);
+  grapic_oval->type_op = type_op;
+  grapic_oval->type_ele = 3;
+  grapic_oval->layer = layer;
+  grapic_oval->color = color;
+  grapic_oval->width = width;
+  grapic_oval->x_start = x_center;
+  grapic_oval->y_start = y_center;
+  grapic_oval->x_end = x_semiaxis;
+  grapic_oval->y_end = y_semiaxis;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制圆弧
+ *
+ * @param grapic_arc 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param angle_start 起始角度
+ * @param angle_end 终止角度
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param x_semiaxis x半轴长度
+ * @param y_semiaxis y半轴长度
+ * @return int8_t
+ */
+int8_t UI_DrawArc(UI_Ele_t *grapic_arc, const char *name, uint8_t type_op,
+                  uint8_t layer, uint8_t color, uint16_t angle_start,
+                  uint16_t angle_end, uint16_t width, uint16_t x_center,
+                  uint16_t y_center, uint16_t x_semiaxis, uint16_t y_semiaxis) {
+  if (grapic_arc == NULL) return -1;
+  snprintf((char *)grapic_arc->name, 2, "%s", name);
+  grapic_arc->type_op = type_op;
+  grapic_arc->type_ele = 4;
+  grapic_arc->layer = layer;
+  grapic_arc->color = color;
+  grapic_arc->angle_start = angle_start;
+  grapic_arc->angle_end = angle_end;
+  grapic_arc->width = width;
+  grapic_arc->x_start = x_center;
+  grapic_arc->y_start = y_center;
+  grapic_arc->x_end = x_semiaxis;
+  grapic_arc->y_end = y_semiaxis;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制浮点数
+ *
+ * @param grapic_float 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param digits 小数点后有效位数
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param float_high 32位浮点数
+ * @param float_middle 32位浮点数
+ * @param float_low 32位浮点数
+ * @return int8_t
+ */
+int8_t UI_DrawFloating(UI_Ele_t *grapic_floating, const char *name,
+                       uint8_t type_op, uint8_t layer, uint8_t color,
+                       uint16_t font_size, uint16_t digits, uint16_t width,
+                       uint16_t x_start, uint16_t y_start, uint16_t float_high,
+                       uint16_t float_middle, uint16_t float_low) {
+  if (grapic_floating == NULL) return -1;
+  snprintf((char *)grapic_floating->name, 2, "%s", name);
+  grapic_floating->type_op = type_op;
+  grapic_floating->type_ele = 5;
+  grapic_floating->layer = layer;
+  grapic_floating->color = color;
+  grapic_floating->angle_start = font_size;
+  grapic_floating->angle_end = digits;
+  grapic_floating->width = width;
+  grapic_floating->x_start = x_start;
+  grapic_floating->y_start = y_start;
+  grapic_floating->radius = float_high;
+  grapic_floating->x_end = float_middle;
+  grapic_floating->y_end = float_low;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制整型数
+ *
+ * @param grapic_integer 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param int32_t_high 32位整型数
+ * @param int32_t_middle 32位整型数
+ * @param int32_t_low 32位整型数
+ * @return int8_t
+ */
+int8_t UI_DrawInteger(UI_Ele_t *grapic_integer, const char *name,
+                      uint8_t type_op, uint8_t layer, uint8_t color,
+                      uint16_t font_size, uint16_t width, uint16_t x_start,
+                      uint16_t y_start, uint16_t int32_t_high,
+                      uint16_t int32_t_middle, uint16_t int32_t_low) {
+  if (grapic_integer == NULL) return -1;
+  snprintf((char *)grapic_integer->name, 2, "%s", name);
+  grapic_integer->type_op = type_op;
+  grapic_integer->type_ele = 6;
+  grapic_integer->layer = layer;
+  grapic_integer->color = color;
+  grapic_integer->angle_start = font_size;
+  grapic_integer->width = width;
+  grapic_integer->x_start = x_start;
+  grapic_integer->y_start = y_start;
+  grapic_integer->radius = int32_t_high;
+  grapic_integer->x_end = int32_t_middle;
+  grapic_integer->y_end = int32_t_low;
+  return 0;
+}
+
+/**
+ * @brief UI_绘制字符
+ *
+ * @param grapic_character 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param length 字符长度
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param character 字符串首地址
+ * @return int8_t
+ */
+int8_t UI_DrawCharacter(UI_Drawcharacter_t *grapic_character, const char *name,
+                        uint8_t type_op, uint8_t layer, uint8_t color,
+                        uint16_t font_size, uint16_t length, uint16_t width,
+                        uint16_t x_start, uint16_t y_start,
+                        const char *character) {
+  if (grapic_character == NULL) return -1;
+  snprintf((char *)grapic_character->grapic.name, 2, "%s", name);
+  grapic_character->grapic.type_op = type_op;
+  grapic_character->grapic.type_ele = 7;
+  grapic_character->grapic.layer = layer;
+  grapic_character->grapic.color = color;
+  grapic_character->grapic.angle_start = font_size;
+  grapic_character->grapic.angle_end = length;
+  grapic_character->grapic.width = width;
+  grapic_character->grapic.x_start = x_start;
+  grapic_character->grapic.y_start = y_start;
+  snprintf((char *)grapic_character->character, 29, "%s", character);
+  return 0;
+}
+
+/**
+ * @brief UI_删除图层
+ *
+ * @param del 结构体
+ * @param opt 操作
+ * @param layer 图层
+ * @return int8_t
+ */
+int8_t UI_DelLayer(UI_Del_t *del, uint8_t opt, uint8_t layer) {
+  if (del == NULL) return -1;
+  del->del_operation = opt;
+  del->layer = layer;
+  return 0;
+}
\ No newline at end of file
diff --git a/User/component/ui.h b/User/component/ui.h
new file mode 100644
index 0000000..4f742d3
--- /dev/null
+++ b/User/component/ui.h
@@ -0,0 +1,284 @@
+/*
+  UI相关命令
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+#include "component/user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define UI_DEL_OPERATION_NOTHING (0)
+#define UI_DEL_OPERATION_DEL (1)
+#define UI_DEL_OPERATION_DEL_ALL (2)
+
+#define UI_GRAPIC_OPERATION_NOTHING (0)
+#define UI_GRAPIC_OPERATION_ADD (1)
+#define UI_GRAPIC_OPERATION_REWRITE (2)
+#define UI_GRAPIC_OPERATION_DEL (3)
+
+#define UI_GRAPIC_LAYER_CONST (0)
+#define UI_GRAPIC_LAYER_AUTOAIM (1)
+#define UI_GRAPIC_LAYER_CHASSIS (2)
+#define UI_GRAPIC_LAYER_CAP (3)
+#define UI_GRAPIC_LAYER_GIMBAL (4)
+#define UI_GRAPIC_LAYER_SHOOT (5)
+#define UI_GRAPIC_LAYER_CMD (6)
+
+#define UI_DEFAULT_WIDTH (0x01)
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+#define UI_CHAR_DEFAULT_WIDTH (0x02)
+
+typedef enum {
+  RED_BLUE,
+  YELLOW,
+  GREEN,
+  ORANGE,
+  PURPLISH_RED,
+  PINK,
+  CYAN,
+  BLACK,
+  WHITE
+} UI_Color_t;
+
+typedef struct __packed {
+  uint8_t op;
+  uint8_t num_layer;
+} UI_InterStudent_UIDel_t;
+
+typedef struct __packed {
+  uint8_t name[3];
+  uint8_t type_op : 3;
+  uint8_t type_ele : 3;
+  uint8_t layer : 4;
+  uint8_t color : 4;
+  uint16_t angle_start : 9;
+  uint16_t angle_end : 9;
+  uint16_t width : 10;
+  uint16_t x_start : 11;
+  uint16_t y_start : 11;
+  uint16_t radius : 10;
+  uint16_t x_end : 11;
+  uint16_t y_end : 11;
+} UI_Ele_t;
+
+typedef struct __packed {
+  UI_Ele_t grapic;
+} UI_Drawgrapic_1_t;
+
+typedef struct __packed {
+  UI_Ele_t grapic[2];
+} UI_Drawgrapic_2_t;
+
+typedef struct __packed {
+  UI_Ele_t grapic[5];
+} UI_Drawgrapic_5_t;
+
+typedef struct __packed {
+  UI_Ele_t grapic[7];
+} UI_Drawgrapic_7_t;
+
+typedef struct __packed {
+  UI_Ele_t grapic;
+  uint8_t character[30];
+} UI_Drawcharacter_t;
+
+typedef struct __packed {
+  uint8_t del_operation;
+  uint8_t layer;
+} UI_Del_t;
+
+/**
+ * @brief UI_绘制直线段
+ *
+ * @param grapic_line 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param x_end 终点x坐标
+ * @param y_end 终点y坐标
+ * @return int8_t
+ */
+int8_t UI_DrawLine(UI_Ele_t *grapic_line, const char *name, uint8_t type_op,
+                   uint8_t layer, uint8_t color, uint16_t width,
+                   uint16_t x_start, uint16_t y_start, uint16_t x_end,
+                   uint16_t y_end);
+
+/**
+ * @brief UI_绘制矩形
+ *
+ * @param grapic_rectangle 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param x_end 对角顶点x坐标
+ * @param y_end 对角顶点y坐标
+ * @return int8_t
+ */
+int8_t UI_DrawRectangle(UI_Ele_t *grapic_rectangle, const char *name,
+                        uint8_t type_op, uint8_t layer, uint8_t color,
+                        uint16_t width, uint16_t x_start, uint16_t y_start,
+                        uint16_t x_end, uint16_t y_end);
+
+/**
+ * @brief UI_绘制正圆
+ *
+ * @param grapic_cycle 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param radius 半径
+ * @return int8_t
+ */
+int8_t UI_DrawCycle(UI_Ele_t *grapic_cycle, const char *name, uint8_t type_op,
+                    uint8_t layer, uint8_t color, uint16_t width,
+                    uint16_t x_center, uint16_t y_center, uint16_t radius);
+
+/**
+ * @brief UI_绘制椭圆
+ *
+ * @param grapic_oval 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param x_semiaxis x半轴长度
+ * @param y_semiaxis y半轴长度
+ * @return int8_t
+ */
+int8_t UI_DrawOval(UI_Ele_t *grapic_oval, const char *name, uint8_t type_op,
+                   uint8_t layer, uint8_t color, uint16_t width,
+                   uint16_t x_center, uint16_t y_center, uint16_t x_semiaxis,
+                   uint16_t y_semiaxis);
+
+/**
+ * @brief UI_绘制圆弧
+ *
+ * @param grapic_arc 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param angle_start 起始角度
+ * @param angle_end 终止角度
+ * @param width 线条宽度
+ * @param x_center 圆心x坐标
+ * @param y_center 圆心y坐标
+ * @param x_semiaxis x半轴长度
+ * @param y_semiaxis y半轴长度
+ * @return int8_t
+ */
+int8_t UI_DrawArc(UI_Ele_t *grapic_arc, const char *name, uint8_t type_op,
+                  uint8_t layer, uint8_t color, uint16_t angle_start,
+                  uint16_t angle_end, uint16_t width, uint16_t x_center,
+                  uint16_t y_center, uint16_t x_semiaxis, uint16_t y_semiaxis);
+
+/**
+ * @brief UI_绘制浮点数
+ *
+ * @param grapic_float 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param digits 小数点后有效位数
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param float_high 32位浮点数
+ * @param float_middle 32位浮点数
+ * @param float_low 32位浮点数
+ * @return int8_t
+ */
+int8_t UI_DrawFloating(UI_Ele_t *grapic_floating, const char *name,
+                       uint8_t type_op, uint8_t layer, uint8_t color,
+                       uint16_t font_size, uint16_t digits, uint16_t width,
+                       uint16_t x_start, uint16_t y_start, uint16_t float_high,
+                       uint16_t float_middle, uint16_t float_low);
+
+/**
+ * @brief UI_绘制整型数
+ *
+ * @param grapic_integer 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param int32_t_high 32位整型数
+ * @param int32_t_middle 32位整型数
+ * @param int32_t_low 32位整型数
+ * @return int8_t
+ */
+int8_t UI_DrawInteger(UI_Ele_t *grapic_integer, const char *name,
+                      uint8_t type_op, uint8_t layer, uint8_t color,
+                      uint16_t font_size, uint16_t width, uint16_t x_start,
+                      uint16_t y_start, uint16_t int32_t_high,
+                      uint16_t int32_t_middle, uint16_t int32_t_low);
+
+/**
+ * @brief UI_绘制字符
+ *
+ * @param grapic_character 结构体
+ * @param name 图形名首地址
+ * @param type_op 操作类型
+ * @param layer 图层数
+ * @param color 颜色
+ * @param font_size 字体大小
+ * @param length 字符长度
+ * @param width 线条宽度
+ * @param x_start 起点x坐标
+ * @param y_start 起点y坐标
+ * @param character 字符串首地址
+ * @return int8_t
+ */
+int8_t UI_DrawCharacter(UI_Drawcharacter_t *grapic_character, const char *name,
+                        uint8_t type_op, uint8_t layer, uint8_t color,
+                        uint16_t font_size, uint16_t length, uint16_t width,
+                        uint16_t x_start, uint16_t y_start,
+                        const char *character);
+
+/**
+ * @brief UI_删除图层
+ *
+ * @param del 结构体
+ * @param opt 操作
+ * @param layer 图层
+ * @return int8_t
+ */
+int8_t UI_DelLayer(UI_Del_t *del, uint8_t opt, uint8_t layer);
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/component/user_math.c b/User/component/user_math.c
new file mode 100644
index 0000000..978141d
--- /dev/null
+++ b/User/component/user_math.c
@@ -0,0 +1,147 @@
+/*
+  自定义的数学运算。
+*/
+
+#include "user_math.h"
+#include 
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+inline float InvSqrt(float x) {
+//#if 0
+  /* Fast inverse square-root */
+  /* See: http://en.wikipedia.org/wiki/Fast_inverse_square_root */
+	float halfx = 0.5f * x;
+	float y = x;
+	long i = *(long*)&y;
+	i = 0x5f3759df - (i>>1);
+	y = *(float*)&i;
+	y = y * (1.5f - (halfx * y * y));
+	y = y * (1.5f - (halfx * y * y));
+	return y;	
+//#else
+//  return 1.0f / sqrtf(x);
+//#endif
+}
+
+inline float AbsClip(float in, float limit) {
+  return (in < -limit) ? -limit : ((in > limit) ? limit : in);
+}
+
+float fAbs(float in){
+  return (in > 0) ? in : -in;
+}
+
+inline void Clip(float *origin, float min, float max) {
+  if (*origin > max) *origin = max;
+  if (*origin < min) *origin = min;
+}
+
+inline float Sign(float in) { return (in > 0) ? 1.0f : 0.0f; }
+
+/**
+ * \brief 将运动向量置零
+ *
+ * \param mv 被操作的值
+ */
+inline void ResetMoveVector(MoveVector_t *mv) { memset(mv, 0, sizeof(*mv)); }
+
+/**
+ * \brief 计算循环值的误差，适用于设定值与反馈值均在（x,y）范围内循环的情况，range应设定为y-x
+ * 例如：（-M_PI,M_PI）range=M_2PI;(0,M_2PI)range=M_2PI;（a,a+b）range=b;
+ * \param sp 设定值
+ * \param fb 反馈值
+ * \param range 被操作的值变化范围，正数时起效
+ * \return 函数运行结果
+ */
+inline float CircleError(float sp, float fb, float range) {
+  float error = sp - fb;
+  if (range > 0.0f) {
+    float half_range = range / 2.0f;
+
+    if (error > half_range)
+      error -= range;
+    else if (error < -half_range)
+      error += range;
+  }
+  return error;
+}
+
+/**
+ * \brief 循环加法，适用于被操作的值在（0,range）范围内循环的情况
+ * \param origin 被操作的值
+ * \param delta 变化量
+ * \param range 被操作的值变化范围，正数时起效
+ */
+inline void CircleAdd(float *origin, float delta, float range) {
+  float out = *origin + delta;
+  if (range > 0.0f) {
+    if (out >= range)
+      out -= range;
+    else if (out < 0.0f)
+      out += range;
+  }
+  *origin = out;
+}
+
+/**
+ * @brief 循环值取反
+ *
+ * @param origin 被操作的值
+ */
+inline void CircleReverse(float *origin) { *origin = -(*origin) + M_2PI; }
+
+/**
+ * @brief 根据目标弹丸速度计算摩擦轮转速
+ *
+ * @param bullet_speed 弹丸速度
+ * @param fric_radius 摩擦轮半径
+ * @param is17mm 是否为17mm
+ * @return 摩擦轮转速
+ */
+inline float CalculateRpm(float bullet_speed, float fric_radius, bool is17mm) {
+  if (bullet_speed == 0.0f) return 0.f;
+  if (is17mm) {
+    if (bullet_speed == 15.0f) return 4670.f;
+    if (bullet_speed == 18.0f) return 5200.f;
+    if (bullet_speed == 30.0f) return 7350.f;
+  } else {
+    if (bullet_speed == 10.0f) return 4450.f;
+    if (bullet_speed == 16.0f) return 5800.f;
+  }
+
+  /* 不为裁判系统设定值时,计算转速 */
+  return 60.0f * (float)bullet_speed / (M_2PI * fric_radius);
+}
+
+// /**
+//  * @brief 断言失败处理
+//  *
+//  * @param file 文件名
+//  * @param line 行号
+//  */
+// void VerifyFailed(const char *file, uint32_t line) {
+//   UNUSED(file);
+//   UNUSED(line);
+//   while (1) {
+//     __NOP();
+//   }
+// }
+
+/* USER FUNCTION BEGIN */
+		/**
+ * @brief 按比例缩放
+ *
+ * @param a 传入值1
+ * @param b 传入值2
+ */
+	inline void ScaleSumTo1(float *a, float *b) {
+    float sum = *a + *b;
+    if (sum > 1.0f) {
+        float scale = 1.0f / sum;
+        *a *= scale;
+        *b *= scale;
+    }
+}
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/component/user_math.h b/User/component/user_math.h
new file mode 100644
index 0000000..fccc8dc
--- /dev/null
+++ b/User/component/user_math.h
@@ -0,0 +1,179 @@
+/*
+  自定义的数学运算。
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+#define M_DEG2RAD_MULT (0.01745329251f)
+#define M_RAD2DEG_MULT (57.2957795131f)
+
+#ifndef M_PI_2
+#define M_PI_2 1.57079632679f
+#endif
+
+#ifndef M_PI
+#define M_PI 3.14159265358979323846f
+#endif
+
+#ifndef M_2PI
+#define M_2PI 6.28318530717958647692f
+#endif
+
+#ifndef __packed
+  #define __packed __attribute__((__packed__))
+#endif /* __packed */
+
+#define max(a, b)           \
+  ({                        \
+    __typeof__(a) _a = (a); \
+    __typeof__(b) _b = (b); \
+    _a > _b ? _a : _b;      \
+  })
+
+#define min(a, b)           \
+  ({                        \
+    __typeof__(a) _a = (a); \
+    __typeof__(b) _b = (b); \
+    _a < _b ? _a : _b;      \
+  })
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+
+
+/* 移动向量 */
+typedef struct {
+  float vx; /* 前后平移 */
+  float vy; /* 左右平移 */
+  float wz; /* 转动 */
+} MoveVector_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+float InvSqrt(float x);
+
+float AbsClip(float in, float limit);
+
+float fAbs(float in);
+
+void Clip(float *origin, float min, float max);
+
+float Sign(float in);
+
+/**
+ * \brief 将运动向量置零
+ *
+ * \param mv 被操作的值
+ */
+void ResetMoveVector(MoveVector_t *mv);
+
+/**
+ * \brief 计算循环值的误差，适用于设定值与反馈值均在（x,y）范围内循环的情况，range应设定为y-x
+ * 例如：（-M_PI,M_PI）range=M_2PI;(0,M_2PI)range=M_2PI;（a,a+b）range=b;
+ * \param sp 设定值
+ * \param fb 反馈值
+ * \param range 被操作的值变化范围，正数时起效
+ * \return 函数运行结果
+ */
+float CircleError(float sp, float fb, float range);
+
+/**
+ * \brief 循环加法，适用于被操作的值在（0,range）范围内循环的情况
+ * \param origin 被操作的值
+ * \param delta 变化量
+ * \param range 被操作的值变化范围，正数时起效
+ */
+void CircleAdd(float *origin, float delta, float range);
+
+/**
+ * @brief 循环值取反
+ *
+ * @param origin 被操作的值
+ */
+void CircleReverse(float *origin);
+
+/**
+ * @brief 根据目标弹丸速度计算摩擦轮转速
+ *
+ * @param bullet_speed 弹丸速度
+ * @param fric_radius 摩擦轮半径
+ * @param is17mm 是否为17mm
+ * @return 摩擦轮转速
+ */
+float CalculateRpm(float bullet_speed, float fric_radius, bool is17mm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef DEBUG
+
+/**
+ * @brief 如果表达式的值为假则运行处理函数
+ *
+ */
+#define ASSERT(expr)                    \
+  do {                                  \
+    if (!(expr)) {                      \
+      VerifyFailed(__FILE__, __LINE__); \
+    }                                   \
+  } while (0)
+#else
+
+/**
+ * @brief 未定DEBUG，表达式不会运行，断言被忽略
+ *
+ */
+#define ASSERT(expr) ((void)(0))
+#endif
+
+#ifdef DEBUG
+
+/**
+ * @brief 如果表达式的值为假则运行处理函数
+ *
+ */
+#define VERIFY(expr)                    \
+  do {                                  \
+    if (!(expr)) {                      \
+      VerifyFailed(__FILE__, __LINE__); \
+    }                                   \
+  } while (0)
+#else
+
+/**
+ * @brief 表达式会运行，忽略表达式结果
+ *
+ */
+#define VERIFY(expr) ((void)(expr))
+#endif
+
+// /**
+//  * @brief 断言失败处理
+//  *
+//  * @param file 文件名
+//  * @param line 行号
+//  */
+// void VerifyFailed(const char *file, uint32_t line);
+
+/* USER FUNCTION BEGIN */
+	 void ScaleSumTo1(float *a, float *b);
+/* USER FUNCTION END */
\ No newline at end of file
diff --git a/User/device/ai.c b/User/device/ai.c
new file mode 100644
index 0000000..5041a3b
--- /dev/null
+++ b/User/device/ai.c
@@ -0,0 +1,81 @@
+#include "device/ai.h"
+#include "device/device.h"
+#include "bsp/uart.h"
+#include "component/crc16.h"
+
+
+int8_t AI_Init(AI_t *ai) {
+  if (ai == NULL) return DEVICE_ERR_NULL;
+//  if (inited) return DEVICE_ERR_INITED;
+//  if ((thread_alert = osThreadGetId()) == NULL) return DEVICE_ERR_NULL;
+
+  BSP_UART_RegisterCallback(BSP_UART_AI, BSP_UART_AI,
+                            BSP_UART_RX_CPLT_CB);
+//  inited = true;
+  return 0;
+}
+
+
+int8_t AI_StartReceiving(AI_t *ai) {
+  if (BSP_UART_Receive(BSP_UART_AI,&ai->RX,sizeof(ai->RX), true)==HAL_OK) {
+    return DEVICE_OK;}
+  return DEVICE_ERR;
+}
+
+int8_t AI_Get_NUC(AI_t *ai,AI_cmd_t* ai_cmd) {
+		if(ai->RX.head[0]!='M'&&ai->RX.head[1]!='R'){
+					return DEVICE_ERR;
+		}
+//		CRC16_Calc(&ai->RX,sizeof(ai->RX),ai->RX.crc16);
+		if(CRC16_Verify((const uint8_t*)&(ai->RX), sizeof(ai->RX))!=true){
+				  return DEVICE_ERR;
+		}
+		ai_cmd->gimbal_t.setpoint.pit=ai->RX.pitch;
+		ai_cmd->gimbal_t.setpoint.yaw=ai->RX.yaw;
+		ai_cmd->mode=ai->RX.mode;
+		ai_cmd->gimbal_t.accl.pit=ai->RX.pitch_acc;
+		ai_cmd->gimbal_t.vel.pit=ai->RX.pitch_vel;
+		ai_cmd->gimbal_t.accl.yaw=ai->RX.yaw_acc;
+		ai_cmd->gimbal_t.vel.yaw=ai->RX.yaw_vel;		
+  return DEVICE_OK;
+}
+
+
+int8_t AI_ParseHost(AI_t* ai,Gimbal_Feedback_t* g_feedback){
+		ai->TX.head[0]='M';
+		ai->TX.head[1]='R';	
+//		ai->TX.mode=2;
+		ai->TX.pitch=g_feedback->motor.pit.rotor_abs_angle;
+		ai->TX.yaw=g_feedback->motor.major_yaw.rotor_abs_angle;	
+		ai->TX.pitch_vel=g_feedback->motor.pit.rotor_speed;
+		ai->TX.yaw_vel=g_feedback->motor.major_yaw.rotor_speed;	
+		ai->TX.q[0]=g_feedback->imu.quat.q0;	
+		ai->TX.q[1]=g_feedback->imu.quat.q1;	
+		ai->TX.q[2]=g_feedback->imu.quat.q2;	
+		ai->TX.q[3]=g_feedback->imu.quat.q3;		
+
+		ai->TX.bullet_count=10;
+		ai->TX.bullet_speed=17.5;	
+		
+		ai->TX.crc16=CRC16_Calc(((const uint8_t*)&(ai->TX)),sizeof(ai->TX)-sizeof(uint16_t), CRC16_INIT );
+		if(CRC16_Verify(((const uint8_t*)&(ai->TX)), sizeof(ai->TX))!=true){
+				  return DEVICE_ERR;
+		}
+		      return DEVICE_OK;
+}
+
+int8_t AI_StartSend(AI_t *ai) {
+
+      if (BSP_UART_Transmit(BSP_UART_AI,&ai->TX,sizeof(ai->TX), true)==HAL_OK)  
+      return DEVICE_OK;
+//    else
+//      return DEVICE_ERR;
+//  } else {
+//    if (HAL_UART_Transmit_DMA(BSP_UART_GetHandle(BSP_UART_AI),
+//                              (uint8_t *)&(ai->TX),
+//                              sizeof(ai->TX)) == HAL_OK)
+//      return DEVICE_OK;
+//    else
+//      return DEVICE_ERR;
+//  }
+}
diff --git a/User/device/ai.h b/User/device/ai.h
new file mode 100644
index 0000000..e83f8df
--- /dev/null
+++ b/User/device/ai.h
@@ -0,0 +1,80 @@
+/*
+ * 自瞄模组
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "component\user_math.h"
+#include "gimbal.h"
+struct __attribute__((packed)) GimbalToVision
+{
+  uint8_t head[2];
+  uint8_t mode;  // 0: 空闲, 1: 自瞄, 2: 小符, 3: 大符
+  float q[4];    // wxyz顺序	/q4,q0,q1,q2/
+  float yaw;
+  float yaw_vel;
+  float pitch;
+  float pitch_vel;
+  float bullet_speed;
+  uint16_t bullet_count;  // 子弹累计发送次数
+  uint16_t crc16;
+};
+
+struct __attribute__((packed)) VisionToGimbal
+{
+  uint8_t head[2];
+  uint8_t mode;  // 0: 不控制, 1: 控制云台但不开火，2: 控制云台且开火
+  float yaw;
+  float yaw_vel;
+  float yaw_acc;
+  float pitch;
+  float pitch_vel;
+  float pitch_acc;
+  uint16_t crc16;
+};
+
+typedef struct __attribute__((packed)) {
+	uint8_t mode;
+	struct{
+//	Gimbal_CMD_t g_cmd;
+		struct{
+				float yaw;
+				float pit;		
+		}setpoint;
+		
+		
+		struct{
+					float pit;
+					float yaw;	
+					}accl;
+		struct{
+					float pit;
+					float yaw;	
+					}vel;		
+	}gimbal_t;
+	
+}AI_cmd_t;
+
+
+typedef struct __attribute__((packed)) {
+	struct GimbalToVision TX;
+	struct VisionToGimbal RX;
+}AI_t;
+
+
+int8_t AI_StartReceiving(AI_t *ai);
+
+int8_t AI_Get_NUC(AI_t *ai,AI_cmd_t* ai_cmd);
+
+int8_t AI_ParseHost(AI_t* ai,Gimbal_Feedback_t* g_feedback);
+
+int8_t AI_StartSend(AI_t *ai);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/bmi088.c b/User/device/bmi088.c
new file mode 100644
index 0000000..f627793
--- /dev/null
+++ b/User/device/bmi088.c
@@ -0,0 +1,381 @@
+/*
+     BMI088 陀螺仪+加速度计传感器。
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "bmi088.h"
+
+#include 
+#include 
+#include 
+#include 
+
+#include "bsp/time.h"
+#include "bsp/gpio.h"
+#include "bsp/spi.h"
+#include "component/user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+#define BMI088_REG_ACCL_CHIP_ID (0x00)
+#define BMI088_REG_ACCL_ERR (0x02)
+#define BMI088_REG_ACCL_STATUS (0x03)
+#define BMI088_REG_ACCL_X_LSB (0x12)
+#define BMI088_REG_ACCL_X_MSB (0x13)
+#define BMI088_REG_ACCL_Y_LSB (0x14)
+#define BMI088_REG_ACCL_Y_MSB (0x15)
+#define BMI088_REG_ACCL_Z_LSB (0x16)
+#define BMI088_REG_ACCL_Z_MSB (0x17)
+#define BMI088_REG_ACCL_SENSORTIME_0 (0x18)
+#define BMI088_REG_ACCL_SENSORTIME_1 (0x19)
+#define BMI088_REG_ACCL_SENSORTIME_2 (0x1A)
+#define BMI088_REG_ACCL_INT_STAT_1 (0x1D)
+#define BMI088_REG_ACCL_TEMP_MSB (0x22)
+#define BMI088_REG_ACCL_TEMP_LSB (0x23)
+#define BMI088_REG_ACCL_CONF (0x40)
+#define BMI088_REG_ACCL_RANGE (0x41)
+#define BMI088_REG_ACCL_INT1_IO_CONF (0x53)
+#define BMI088_REG_ACCL_INT2_IO_CONF (0x54)
+#define BMI088_REG_ACCL_INT1_INT2_MAP_DATA (0x58)
+#define BMI088_REG_ACCL_SELF_TEST (0x6D)
+#define BMI088_REG_ACCL_PWR_CONF (0x7C)
+#define BMI088_REG_ACCL_PWR_CTRL (0x7D)
+#define BMI088_REG_ACCL_SOFTRESET (0x7E)
+
+#define BMI088_REG_GYRO_CHIP_ID (0x00)
+#define BMI088_REG_GYRO_X_LSB (0x02)
+#define BMI088_REG_GYRO_X_MSB (0x03)
+#define BMI088_REG_GYRO_Y_LSB (0x04)
+#define BMI088_REG_GYRO_Y_MSB (0x05)
+#define BMI088_REG_GYRO_Z_LSB (0x06)
+#define BMI088_REG_GYRO_Z_MSB (0x07)
+#define BMI088_REG_GYRO_INT_STAT_1 (0x0A)
+#define BMI088_REG_GYRO_RANGE (0x0F)
+#define BMI088_REG_GYRO_BANDWIDTH (0x10)
+#define BMI088_REG_GYRO_LPM1 (0x11)
+#define BMI088_REG_GYRO_SOFTRESET (0x14)
+#define BMI088_REG_GYRO_INT_CTRL (0x15)
+#define BMI088_REG_GYRO_INT3_INT4_IO_CONF (0x16)
+#define BMI088_REG_GYRO_INT3_INT4_IO_MAP (0x18)
+#define BMI088_REG_GYRO_SELF_TEST (0x3C)
+
+#define BMI088_CHIP_ID_ACCL (0x1E)
+#define BMI088_CHIP_ID_GYRO (0x0F)
+
+#define BMI088_LEN_RX_BUFF (19)
+/* Private macro ------------------------------------------------------------ */
+#define BMI088_ACCL_NSS_SET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_SET)
+#define BMI088_ACCL_NSS_RESET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_RESET)
+
+#define BMI088_GYRO_NSS_SET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_SET)
+#define BMI088_GYRO_NSS_RESET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_RESET)
+
+/* Private typedef ---------------------------------------------------------- */
+typedef enum {
+  BMI_ACCL,
+  BMI_GYRO,
+} BMI_Device_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static uint8_t buffer[2];
+static uint8_t bmi088_rxbuf[BMI088_LEN_RX_BUFF];
+
+static osThreadId_t thread_alert;
+static bool inited = false;
+
+/* Private function  -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+static void BMI_WriteSingle(BMI_Device_t dv, uint8_t reg, uint8_t data) {
+  buffer[0] = (reg & 0x7f);
+  buffer[1] = data;
+
+  BSP_TIME_Delay(1);
+  switch (dv) {
+    case BMI_ACCL:
+      BMI088_ACCL_NSS_RESET();
+      break;
+
+    case BMI_GYRO:
+      BMI088_GYRO_NSS_RESET();
+      break;
+  }
+
+  BSP_SPI_Transmit(BSP_SPI_BMI088, buffer, 2u, false);
+
+  switch (dv) {
+    case BMI_ACCL:
+      BMI088_ACCL_NSS_SET();
+      break;
+
+    case BMI_GYRO:
+      BMI088_GYRO_NSS_SET();
+      break;
+  }
+}
+
+static uint8_t BMI_ReadSingle(BMI_Device_t dv, uint8_t reg) {
+  BSP_TIME_Delay(1);
+  switch (dv) {
+    case BMI_ACCL:
+      BMI088_ACCL_NSS_RESET();
+      break;
+
+    case BMI_GYRO:
+      BMI088_GYRO_NSS_RESET();
+      break;
+  }
+  buffer[0] = (uint8_t)(reg | 0x80);
+  BSP_SPI_Transmit(BSP_SPI_BMI088, buffer, 1u, false);
+  BSP_SPI_Receive(BSP_SPI_BMI088, buffer, 2u, false);
+
+  switch (dv) {
+    case BMI_ACCL:
+      BMI088_ACCL_NSS_SET();
+      return buffer[1];
+
+    case BMI_GYRO:
+      BMI088_GYRO_NSS_SET();
+      return buffer[0];
+  }
+}
+
+static void BMI_Read(BMI_Device_t dv, uint8_t reg, uint8_t *data, uint8_t len) {
+  if (data == NULL) return;
+
+  switch (dv) {
+    case BMI_ACCL:
+      BMI088_ACCL_NSS_RESET();
+      break;
+
+    case BMI_GYRO:
+      BMI088_GYRO_NSS_RESET();
+      break;
+  }
+  buffer[0] = (uint8_t)(reg | 0x80);
+  BSP_SPI_Transmit(BSP_SPI_BMI088, buffer, 1u, false); 
+  BSP_SPI_Receive(BSP_SPI_BMI088, data, len, true);
+}
+
+static void BMI088_RxCpltCallback(void) {
+  if (BSP_GPIO_ReadPin(BSP_GPIO_ACCL_CS) == GPIO_PIN_RESET) {
+    BMI088_ACCL_NSS_SET();
+    osThreadFlagsSet(thread_alert, SIGNAL_BMI088_ACCL_RAW_REDY);
+  }
+  if (BSP_GPIO_ReadPin(BSP_GPIO_ACCL_CS) == GPIO_PIN_RESET) {
+    BMI088_GYRO_NSS_SET();
+    osThreadFlagsSet(thread_alert, SIGNAL_BMI088_GYRO_RAW_REDY);
+  }
+}
+
+static void BMI088_AcclIntCallback(void) {
+  osThreadFlagsSet(thread_alert, SIGNAL_BMI088_ACCL_NEW_DATA);
+}
+
+static void BMI088_GyroIntCallback(void) {
+  osThreadFlagsSet(thread_alert, SIGNAL_BMI088_GYRO_NEW_DATA);
+}
+
+/* Exported functions ------------------------------------------------------- */
+int8_t BMI088_Init(BMI088_t *bmi088, const BMI088_Cali_t *cali) {
+  if (bmi088 == NULL) return DEVICE_ERR_NULL;
+  if (cali == NULL) return DEVICE_ERR_NULL;
+  if (inited) return DEVICE_ERR_INITED;
+  if ((thread_alert = osThreadGetId()) == NULL) return DEVICE_ERR_NULL;
+
+  bmi088->cali = cali;
+
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_SOFTRESET, 0xB6);
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_SOFTRESET, 0xB6);
+  BSP_TIME_Delay(30);
+
+  /* Switch accl to SPI mode. */
+  BMI_ReadSingle(BMI_ACCL, BMI088_CHIP_ID_ACCL);
+
+  if (BMI_ReadSingle(BMI_ACCL, BMI088_REG_ACCL_CHIP_ID) != BMI088_CHIP_ID_ACCL)
+    return DEVICE_ERR_NO_DEV;
+
+  if (BMI_ReadSingle(BMI_GYRO, BMI088_REG_GYRO_CHIP_ID) != BMI088_CHIP_ID_GYRO)
+    return DEVICE_ERR_NO_DEV;
+
+  BSP_GPIO_DisableIRQ(BSP_GPIO_USER_KEY);
+  BSP_GPIO_DisableIRQ(BSP_GPIO_USER_KEY);
+
+  BSP_SPI_RegisterCallback(BSP_SPI_BMI088, BSP_SPI_RX_CPLT_CB,
+                           BMI088_RxCpltCallback);
+  BSP_GPIO_RegisterCallback(BSP_GPIO_USER_KEY, BMI088_AcclIntCallback);
+  BSP_GPIO_RegisterCallback(BSP_GPIO_USER_KEY, BMI088_GyroIntCallback);
+
+  /* Accl init. */
+  /* Filter setting: Normal. */
+  /* ODR: 0xAB: 800Hz. 0xAA: 400Hz. 0xA9: 200Hz. 0xA8: 100Hz. 0xA6: 25Hz. */
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_CONF, 0xAA);
+
+  /* 0x00: +-3G. 0x01: +-6G. 0x02: +-12G. 0x03: +-24G. */
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_RANGE, 0x01);
+
+  /* INT1 as output. Push-pull. Active low. Output. */
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_INT1_IO_CONF, 0x08);
+
+  /* Map data ready interrupt to INT1. */
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_INT1_INT2_MAP_DATA, 0x04);
+
+  /* Turn on accl. Now we can read data. */
+  BMI_WriteSingle(BMI_ACCL, BMI088_REG_ACCL_PWR_CTRL, 0x04);
+  BSP_TIME_Delay(50);
+
+  /* Gyro init. */
+  /* 0x00: +-2000. 0x01: +-1000. 0x02: +-500. 0x03: +-250. 0x04: +-125. */
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_RANGE, 0x01);
+
+  /* Filter bw: 47Hz. */
+  /* ODR: 0x02: 1000Hz. 0x03: 400Hz. 0x06: 200Hz. 0x07: 100Hz. */
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_BANDWIDTH, 0x03);
+
+  /* INT3 and INT4 as output. Push-pull. Active low. */
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_INT3_INT4_IO_CONF, 0x00);
+
+  /* Map data ready interrupt to INT3. */
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_INT3_INT4_IO_MAP, 0x01);
+
+  /* Enable new data interrupt. */
+  BMI_WriteSingle(BMI_GYRO, BMI088_REG_GYRO_INT_CTRL, 0x80);
+
+  BSP_TIME_Delay(10);
+
+  inited = true;
+
+  BSP_GPIO_EnableIRQ(BSP_GPIO_USER_KEY);
+  BSP_GPIO_EnableIRQ(BSP_GPIO_USER_KEY);
+  return DEVICE_OK;
+}
+
+bool BMI088_GyroStable(AHRS_Gyro_t *gyro) {
+  return ((gyro->x < 0.03f) && (gyro->y < 0.03f) && (gyro->z < 0.03f));
+}
+
+uint32_t BMI088_WaitNew() {
+  return osThreadFlagsWait(
+      SIGNAL_BMI088_ACCL_NEW_DATA | SIGNAL_BMI088_GYRO_NEW_DATA, osFlagsWaitAll,
+      osWaitForever);
+}
+
+int8_t BMI088_AcclStartDmaRecv() {
+  BMI_Read(BMI_ACCL, BMI088_REG_ACCL_X_LSB, bmi088_rxbuf, BMI088_LEN_RX_BUFF);
+  return DEVICE_OK;
+}
+
+uint32_t BMI088_AcclWaitDmaCplt() {
+  return osThreadFlagsWait(SIGNAL_BMI088_ACCL_RAW_REDY, osFlagsWaitAll,
+                           osWaitForever);
+}
+
+int8_t BMI088_GyroStartDmaRecv() {
+  BMI_Read(BMI_GYRO, BMI088_REG_GYRO_X_LSB, bmi088_rxbuf + 7, 6u);
+  return DEVICE_OK;
+}
+
+uint32_t BMI088_GyroWaitDmaCplt() {
+  return osThreadFlagsWait(SIGNAL_BMI088_GYRO_RAW_REDY, osFlagsWaitAll,
+                           osWaitForever);
+}
+
+int8_t BMI088_ParseAccl(BMI088_t *bmi088) {
+  if (bmi088 == NULL) return DEVICE_ERR_NULL;
+
+#if 1
+  int16_t raw_x, raw_y, raw_z;
+  memcpy(&raw_x, bmi088_rxbuf + 1, sizeof(raw_x));
+  memcpy(&raw_y, bmi088_rxbuf + 3, sizeof(raw_y));
+  memcpy(&raw_z, bmi088_rxbuf + 5, sizeof(raw_z));
+
+  bmi088->accl.x = (float)raw_x;
+  bmi088->accl.y = (float)raw_y;
+  bmi088->accl.z = (float)raw_z;
+
+#else
+  const int16_t *praw_x = (int16_t *)(bmi088_rxbuf + 1);
+  const int16_t *praw_y = (int16_t *)(bmi088_rxbuf + 3);
+  const int16_t *praw_z = (int16_t *)(bmi088_rxbuf + 5);
+
+  bmi088->accl.x = (float)*praw_x;
+  bmi088->accl.y = (float)*praw_y;
+  bmi088->accl.z = (float)*praw_z;
+
+#endif
+
+  /* 3G: 10920. 6G: 5460. 12G: 2730. 24G: 1365. */
+  bmi088->accl.x /= 5460.0f;
+  bmi088->accl.y /= 5460.0f;
+  bmi088->accl.z /= 5460.0f;
+
+  int16_t raw_temp =
+      (uint16_t)((bmi088_rxbuf[17] << 3) | (bmi088_rxbuf[18] >> 5));
+
+  if (raw_temp > 1023) raw_temp -= 2048;
+
+  bmi088->temp = (float)raw_temp * 0.125f + 23.0f;
+
+  return DEVICE_OK;
+}
+
+int8_t BMI088_ParseGyro(BMI088_t *bmi088) {
+  if (bmi088 == NULL) return DEVICE_ERR_NULL;
+
+#if 1
+  /* Gyroscope imu_raw -> degrees/sec -> radians/sec */
+  int16_t raw_x, raw_y, raw_z;
+  memcpy(&raw_x, bmi088_rxbuf + 7, sizeof(raw_x));
+  memcpy(&raw_y, bmi088_rxbuf + 9, sizeof(raw_y));
+  memcpy(&raw_z, bmi088_rxbuf + 11, sizeof(raw_z));
+
+  bmi088->gyro.x = (float)raw_x;
+  bmi088->gyro.y = (float)raw_y;
+  bmi088->gyro.z = (float)raw_z;
+
+#else
+  /* Gyroscope imu_raw -> degrees/sec -> radians/sec */
+  const int16_t *raw_x = (int16_t *)(bmi088_rxbuf + 7);
+  const int16_t *raw_y = (int16_t *)(bmi088_rxbuf + 9);
+  const int16_t *raw_z = (int16_t *)(bmi088_rxbuf + 11);
+
+  bmi088->gyro.x = (float)*raw_x;
+  bmi088->gyro.y = (float)*raw_y;
+  bmi088->gyro.z = (float)*raw_z;
+#endif
+
+  /* FS125: 262.144. FS250: 131.072. FS500: 65.536. FS1000: 32.768.
+   * FS2000: 16.384.*/
+  bmi088->gyro.x /= 32.768f;
+  bmi088->gyro.y /= 32.768f;
+  bmi088->gyro.z /= 32.768f;
+
+  bmi088->gyro.x *= M_DEG2RAD_MULT;
+  bmi088->gyro.y *= M_DEG2RAD_MULT;
+  bmi088->gyro.z *= M_DEG2RAD_MULT;
+
+  bmi088->gyro.x -= bmi088->cali->gyro_offset.x;
+  bmi088->gyro.y -= bmi088->cali->gyro_offset.y;
+  bmi088->gyro.z -= bmi088->cali->gyro_offset.z;
+
+  return DEVICE_ERR_NULL;
+}
+
+float BMI088_GetUpdateFreq(BMI088_t *bmi088) {
+  (void)bmi088;
+  return 400.0f;
+}
diff --git a/User/device/bmi088.h b/User/device/bmi088.h
new file mode 100644
index 0000000..eb44e0c
--- /dev/null
+++ b/User/device/bmi088.h
@@ -0,0 +1,81 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+
+#include "component/ahrs.h"
+#include "device/device.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef struct {
+  struct {
+    float x;
+    float y;
+    float z;
+  } gyro_offset; /* 陀螺仪偏置 */
+} BMI088_Cali_t; /* BMI088校准数据 */
+
+typedef struct {
+  DEVICE_Header_t header;
+  AHRS_Accl_t accl;
+  AHRS_Gyro_t gyro;
+
+  float temp; /* 温度 */
+
+  const BMI088_Cali_t *cali;
+} BMI088_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t BMI088_Init(BMI088_t *bmi088, const BMI088_Cali_t *cali);
+int8_t BMI088_Restart(void);
+
+bool BMI088_GyroStable(AHRS_Gyro_t *gyro);
+
+/* Sensor use right-handed coordinate system. */
+/*
+                x < R(logo)
+                        y
+                UP is z
+        All implementation should follow this rule.
+ */
+uint32_t BMI088_WaitNew();
+
+/*
+  BMI088的Accl和Gyro共用同一个DMA通道，所以一次只能读一个传感器。
+  即BMI088_AcclStartDmaRecv() 和 BMI088_AcclWaitDmaCplt() 中间不能
+  出现 BMI088_GyroStartDmaRecv()。
+*/
+int8_t BMI088_AcclStartDmaRecv();
+uint32_t BMI088_AcclWaitDmaCplt();
+int8_t BMI088_GyroStartDmaRecv();
+uint32_t BMI088_GyroWaitDmaCplt();
+int8_t BMI088_ParseAccl(BMI088_t *bmi088);
+int8_t BMI088_ParseGyro(BMI088_t *bmi088);
+float BMI088_GetUpdateFreq(BMI088_t *bmi088);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/device.h b/User/device/device.h
new file mode 100644
index 0000000..fb236b3
--- /dev/null
+++ b/User/device/device.h
@@ -0,0 +1,53 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+#define DEVICE_OK (0)
+#define DEVICE_ERR (-1)
+#define DEVICE_ERR_NULL (-2)
+#define DEVICE_ERR_INITED (-3)
+#define DEVICE_ERR_NO_DEV (-4)
+
+/* AUTO GENERATED SIGNALS BEGIN */
+#define SIGNAL_DR16_RAW_REDY (1u << 0)
+#define SIGNAL_BMI088_ACCL_RAW_REDY (1u << 1)
+#define SIGNAL_BMI088_GYRO_RAW_REDY (1u << 2)
+#define SIGNAL_BMI088_ACCL_NEW_DATA (1u << 3)
+#define SIGNAL_BMI088_GYRO_NEW_DATA (1u << 4)
+#define SIGNAL_IST8310_MAGN_RAW_REDY (1u << 5)
+#define SIGNAL_IST8310_MAGN_NEW_DATA (1u << 6)
+/* AUTO GENERATED SIGNALS END */
+
+/* USER SIGNALS BEGIN */
+
+/* USER SIGNALS END */
+/*设备层通用Header*/
+typedef struct {
+    bool online;
+    uint64_t last_online_time;
+} DEVICE_Header_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/device_config.yaml b/User/device/device_config.yaml
new file mode 100644
index 0000000..b23a29f
--- /dev/null
+++ b/User/device/device_config.yaml
@@ -0,0 +1,27 @@
+bmi088:
+  bsp_config:
+    BSP_GPIO_ACCL_CS: BSP_GPIO_ACCL_CS
+    BSP_GPIO_ACCL_INT: BSP_GPIO_USER_KEY
+    BSP_GPIO_GYRO_CS: BSP_GPIO_ACCL_CS
+    BSP_GPIO_GYRO_INT: BSP_GPIO_USER_KEY
+    BSP_SPI_BMI088: BSP_SPI_BMI088
+  enabled: true
+dr16:
+  bsp_config:
+    BSP_UART_DR16: BSP_UART_3
+  enabled: true
+ist8310:
+  bsp_config:
+    BSP_I2C_COMP: BSP_I2C_2
+    CMPS_INT_Pin: BSP_GPIO_USER_KEY
+    CMPS_RST_Pin: BSP_GPIO_ACCL_CS
+  enabled: true
+motor:
+  bsp_config: {}
+  enabled: true
+motor_dm:
+  bsp_config: {}
+  enabled: true
+motor_rm:
+  bsp_config: {}
+  enabled: true
diff --git a/User/device/dr16.c b/User/device/dr16.c
new file mode 100644
index 0000000..5d9397b
--- /dev/null
+++ b/User/device/dr16.c
@@ -0,0 +1,169 @@
+/*
+    DR16接收机
+    Example：
+
+  DR16_Init(&dr16);
+  
+  while (1) {
+    DR16_StartDmaRecv(&dr16);
+    if (DR16_WaitDmaCplt(20)) {
+      DR16_ParseData(&dr16);
+    } else {
+      DR16_Offline(&dr16);
+    }
+}
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "dr16.h"
+#include "bsp/uart.h"
+#include "bsp/time.h"
+#include "device.h"
+
+#include 
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+/* Private define ----------------------------------------------------------- */
+#define DR16_CH_VALUE_MIN (364u)
+#define DR16_CH_VALUE_MID (1024u)
+#define DR16_CH_VALUE_MAX (1684u)
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* Private variables -------------------------------------------------------- */
+
+static osThreadId_t thread_alert;
+static bool inited = false;
+
+/* Private function  -------------------------------------------------------- */
+static void DR16_RxCpltCallback(void) {
+  osThreadFlagsSet(thread_alert, SIGNAL_DR16_RAW_REDY);
+}
+
+static bool DR16_DataCorrupted(const DR16_t *dr16) {
+  if (dr16 == NULL) return DEVICE_ERR_NULL;
+
+  if ((dr16->raw_data.ch_r_x < DR16_CH_VALUE_MIN) ||
+      (dr16->raw_data.ch_r_x > DR16_CH_VALUE_MAX))
+    return DEVICE_ERR;
+
+  if ((dr16->raw_data.ch_r_y < DR16_CH_VALUE_MIN) ||
+      (dr16->raw_data.ch_r_y > DR16_CH_VALUE_MAX))
+    return DEVICE_ERR;
+
+  if ((dr16->raw_data.ch_l_x < DR16_CH_VALUE_MIN) ||
+      (dr16->raw_data.ch_l_x > DR16_CH_VALUE_MAX))
+    return DEVICE_ERR;
+
+  if ((dr16->raw_data.ch_l_y < DR16_CH_VALUE_MIN) ||
+      (dr16->raw_data.ch_l_y > DR16_CH_VALUE_MAX))
+    return DEVICE_ERR;
+
+  if (dr16->raw_data.sw_l == 0) return DEVICE_ERR;
+
+  if (dr16->raw_data.sw_r == 0) return DEVICE_ERR;
+
+  return DEVICE_OK;
+}
+
+/* Exported functions ------------------------------------------------------- */
+int8_t DR16_Init(DR16_t *dr16) {
+  if (dr16 == NULL) return DEVICE_ERR_NULL;
+  if (inited) return DEVICE_ERR_INITED;
+  if ((thread_alert = osThreadGetId()) == NULL) return DEVICE_ERR_NULL;
+
+  BSP_UART_RegisterCallback(BSP_UART_3, BSP_UART_RX_CPLT_CB,
+                            DR16_RxCpltCallback);
+
+  inited = true;
+  return DEVICE_OK;
+}
+
+int8_t DR16_Restart(void) {
+  __HAL_UART_DISABLE(BSP_UART_GetHandle(BSP_UART_3));
+  __HAL_UART_ENABLE(BSP_UART_GetHandle(BSP_UART_3));
+  return DEVICE_OK;
+}
+
+int8_t DR16_StartDmaRecv(DR16_t *dr16) {
+  if (HAL_UART_Receive_DMA(BSP_UART_GetHandle(BSP_UART_3),
+                           (uint8_t *)&(dr16->raw_data),
+                           sizeof(dr16->raw_data)) == HAL_OK)
+    return DEVICE_OK;
+  return DEVICE_ERR;
+}
+
+bool DR16_WaitDmaCplt(uint32_t timeout) {
+  return (osThreadFlagsWait(SIGNAL_DR16_RAW_REDY, osFlagsWaitAll, timeout) ==
+          SIGNAL_DR16_RAW_REDY);
+}
+
+int8_t DR16_ParseData(DR16_t *dr16){
+  if (dr16 == NULL) return DEVICE_ERR_NULL;
+
+  if (DR16_DataCorrupted(dr16)) {
+    return DEVICE_ERR;
+  }
+
+  dr16->header.online = true;
+  dr16->header.last_online_time = BSP_TIME_Get_us();
+  
+  memset(&(dr16->data), 0, sizeof(dr16->data));
+
+  float full_range = (float)(DR16_CH_VALUE_MAX - DR16_CH_VALUE_MIN);
+
+  // 解析摇杆数据
+  dr16->data.ch_r_x = 2.0f * ((float)dr16->raw_data.ch_r_x - DR16_CH_VALUE_MID) / full_range;
+  dr16->data.ch_r_y = 2.0f * ((float)dr16->raw_data.ch_r_y - DR16_CH_VALUE_MID) / full_range;
+  dr16->data.ch_l_x = 2.0f * ((float)dr16->raw_data.ch_l_x - DR16_CH_VALUE_MID) / full_range;
+  dr16->data.ch_l_y = 2.0f * ((float)dr16->raw_data.ch_l_y - DR16_CH_VALUE_MID) / full_range;
+
+  // 解析拨杆位置
+  dr16->data.sw_l = (DR16_SwitchPos_t)dr16->raw_data.sw_l;
+  dr16->data.sw_r = (DR16_SwitchPos_t)dr16->raw_data.sw_r;
+
+  // 解析鼠标数据
+  dr16->data.mouse.x = dr16->raw_data.x;
+  dr16->data.mouse.y = dr16->raw_data.y;
+  dr16->data.mouse.z = dr16->raw_data.z;
+
+  dr16->data.mouse.l_click = dr16->raw_data.press_l;
+  dr16->data.mouse.r_click = dr16->raw_data.press_r;
+
+  // 解析键盘按键 - 使用union简化代码
+  uint16_t key_value = dr16->raw_data.key;
+  
+  // 解析键盘位映射（W-B键，位0-15）
+  for (int i = DR16_KEY_W; i <= DR16_KEY_B; i++) {
+    dr16->data.keyboard.key[i] = (key_value & (1 << i)) != 0;
+  }
+
+  // 解析鼠标点击
+  dr16->data.keyboard.key[DR16_L_CLICK] = dr16->data.mouse.l_click;
+  dr16->data.keyboard.key[DR16_R_CLICK] = dr16->data.mouse.r_click;
+
+  // 解析第五通道
+  dr16->data.ch_res = 2.0f * ((float)dr16->raw_data.res - DR16_CH_VALUE_MID) / full_range;
+  
+  return DEVICE_OK;
+}
+
+int8_t DR16_Offline(DR16_t *dr16){
+  if (dr16 == NULL) return DEVICE_ERR_NULL;
+
+  dr16->header.online = false;
+  memset(&(dr16->data), 0, sizeof(dr16->data));
+
+  return DEVICE_OK;
+}
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
diff --git a/User/device/dr16.h b/User/device/dr16.h
new file mode 100644
index 0000000..03fa526
--- /dev/null
+++ b/User/device/dr16.h
@@ -0,0 +1,117 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+
+#include "component/user_math.h"
+#include "device.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef struct __packed {
+  uint16_t ch_r_x : 11;
+  uint16_t ch_r_y : 11;
+  uint16_t ch_l_x : 11;
+  uint16_t ch_l_y : 11;
+  uint8_t sw_r : 2;
+  uint8_t sw_l : 2;
+  int16_t x;
+  int16_t y;
+  int16_t z;
+  uint8_t press_l;
+  uint8_t press_r;
+  uint16_t key;
+  uint16_t res;
+} DR16_RawData_t;
+
+typedef enum {
+  DR16_SW_ERR = 0,
+  DR16_SW_UP = 1,
+  DR16_SW_MID = 3,
+  DR16_SW_DOWN = 2,
+} DR16_SwitchPos_t;
+
+/* 键盘按键值 */
+typedef enum {
+  DR16_KEY_W = 0,
+  DR16_KEY_S,
+  DR16_KEY_A,
+  DR16_KEY_D,
+  DR16_KEY_SHIFT,
+  DR16_KEY_CTRL,
+  DR16_KEY_Q,
+  DR16_KEY_E,
+  DR16_KEY_R,
+  DR16_KEY_F,
+  DR16_KEY_G,
+  DR16_KEY_Z,
+  DR16_KEY_X,
+  DR16_KEY_C,
+  DR16_KEY_V,
+  DR16_KEY_B,
+  DR16_L_CLICK,
+  DR16_R_CLICK,
+  DR16_KEY_NUM,
+} DR16_Key_t;
+
+typedef struct {
+  float ch_l_x; /* 遥控器左侧摇杆横轴值，上为正 */
+  float ch_l_y; /* 遥控器左侧摇杆纵轴值，右为正 */
+  float ch_r_x; /* 遥控器右侧摇杆横轴值，上为正 */
+  float ch_r_y; /* 遥控器右侧摇杆纵轴值，右为正 */
+
+  float ch_res; /* 第五通道值 */
+
+   DR16_SwitchPos_t sw_r; /* 右侧拨杆位置 */
+   DR16_SwitchPos_t sw_l; /* 左侧拨杆位置 */
+
+  struct {
+    int16_t x;
+    int16_t y;
+    int16_t z;
+    bool l_click; /* 左键 */
+    bool r_click; /* 右键 */
+  } mouse;        /* 鼠标值 */
+
+  union {
+    bool key[DR16_KEY_NUM]; /* 键盘按键值 */
+    uint16_t value;        /* 键盘按键值的位映射 */
+  } keyboard;
+
+  uint16_t res; /* 保留，未启用 */
+} DR16_Data_t;
+
+typedef struct {
+  DEVICE_Header_t header;
+  DR16_RawData_t raw_data;
+  DR16_Data_t data;
+} DR16_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t DR16_Init(DR16_t *dr16);
+int8_t DR16_Restart(void);
+int8_t DR16_StartDmaRecv(DR16_t *dr16);
+bool DR16_WaitDmaCplt(uint32_t timeout);
+int8_t DR16_ParseData(DR16_t *dr16);
+int8_t DR16_Offline(DR16_t *dr16);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/ist8310.c b/User/device/ist8310.c
new file mode 100644
index 0000000..6b994e6
--- /dev/null
+++ b/User/device/ist8310.c
@@ -0,0 +1,178 @@
+/*
+    IST8310 地磁传感器。
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "ist8310.h"
+
+#include 
+#include 
+#include 
+
+#include "bsp/time.h"
+#include "bsp/gpio.h"
+#include "bsp/i2c.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+#define IST8310_WAI (0x00)
+#define IST8310_STAT1 (0x02)
+#define IST8310_DATAXL (0x03)
+#define IST8310_STAT2 (0x09)
+#define IST8310_CNTL1 (0x0A)
+#define IST8310_CNTL2 (0x0B)
+#define IST8310_STR (0x0C)
+#define IST8310_TEMPL (0x1C)
+#define IST8310_TEMPH (0x1D)
+#define IST8310_AVGCNTL (0x41)
+#define IST8310_PDCNTL (0x42)
+
+#define IST8310_CHIP_ID (0x10)
+
+#define IST8310_IIC_ADDRESS (0x0E << 1)
+
+#define IST8310_LEN_RX_BUFF (6)
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+#define IST8310_SET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_SET)
+#define IST8310_RESET() \
+  BSP_GPIO_WritePin(BSP_GPIO_ACCL_CS, GPIO_PIN_RESET)
+
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+uint8_t ist8310_rxbuf[IST8310_LEN_RX_BUFF];
+
+static osThreadId_t thread_alert;
+static bool inited = false;
+
+/* Private function  -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+static void IST8310_WriteSingle(uint8_t reg, uint8_t data) {
+  BSP_I2C_MemWriteByte(BSP_I2C_2, IST8310_IIC_ADDRESS, reg, data);
+}
+
+static uint8_t IST8310_ReadSingle(uint8_t reg) {
+  return BSP_I2C_MemReadByte(BSP_I2C_2, IST8310_IIC_ADDRESS, reg);
+}
+
+
+static void IST8310_Read(uint8_t reg, uint8_t *data, uint8_t len) {
+  if (data == NULL) return;
+  BSP_I2C_MemRead(BSP_I2C_2, IST8310_IIC_ADDRESS, reg, data, len, true);
+}
+
+static void IST8310_MemRxCpltCallback(void) {
+  osThreadFlagsSet(thread_alert, SIGNAL_IST8310_MAGN_RAW_REDY);
+}
+
+static void IST8310_IntCallback(void) {
+  osThreadFlagsSet(thread_alert, SIGNAL_IST8310_MAGN_NEW_DATA);
+}
+
+/* Exported functions ------------------------------------------------------- */
+int8_t IST8310_Init(IST8310_t *ist8310, const IST8310_Cali_t *cali) {
+  if (ist8310 == NULL) return DEVICE_ERR_NULL;
+  if (cali == NULL) return DEVICE_ERR_NULL;
+  if (inited) return DEVICE_ERR_INITED;
+  if ((thread_alert = osThreadGetId()) == NULL) return DEVICE_ERR_NULL;
+
+  ist8310->cali = cali;
+
+  IST8310_RESET();
+  BSP_TIME_Delay(50);
+  IST8310_SET();
+  BSP_TIME_Delay(50);
+
+  if (IST8310_ReadSingle(IST8310_WAI) != IST8310_CHIP_ID)
+    return DEVICE_ERR_NO_DEV;
+
+  BSP_GPIO_DisableIRQ(BSP_GPIO_USER_KEY);
+
+  BSP_I2C_RegisterCallback(BSP_I2C_2, HAL_I2C_MEM_RX_CPLT_CB,
+                           IST8310_MemRxCpltCallback);
+  BSP_GPIO_RegisterCallback(BSP_GPIO_USER_KEY, IST8310_IntCallback);
+
+  /* Init. */
+  /* 0x00: Stand-By mode. 0x01: Single measurement mode. */
+
+  /* 0x08: Data ready function enable. DRDY signal active low*/
+  IST8310_WriteSingle(IST8310_CNTL2, 0x08);
+
+  IST8310_WriteSingle(IST8310_AVGCNTL, 0x09);
+  IST8310_WriteSingle(IST8310_PDCNTL, 0xC0);
+  IST8310_WriteSingle(IST8310_CNTL1, 0x0B);
+  BSP_TIME_Delay(10);
+
+  inited = true;
+
+  BSP_GPIO_EnableIRQ(BSP_GPIO_USER_KEY);
+  return DEVICE_OK;
+}
+
+bool IST8310_WaitNew(uint32_t timeout) {
+  return (osThreadFlagsWait(SIGNAL_IST8310_MAGN_NEW_DATA, osFlagsWaitAll,
+                            timeout) == SIGNAL_IST8310_MAGN_NEW_DATA);
+}
+
+int8_t IST8310_StartDmaRecv() {
+  IST8310_Read(IST8310_DATAXL, ist8310_rxbuf, IST8310_LEN_RX_BUFF);
+  return DEVICE_OK;
+}
+
+uint32_t IST8310_WaitDmaCplt() {
+  return osThreadFlagsWait(SIGNAL_IST8310_MAGN_RAW_REDY, osFlagsWaitAll,
+                           osWaitForever);
+}
+
+int8_t IST8310_Parse(IST8310_t *ist8310) {
+  if (ist8310 == NULL) return DEVICE_ERR_NULL;
+
+#if 1
+  /* Magn -> T */
+  int16_t raw_x, raw_y, raw_z;
+  memcpy(&raw_x, ist8310_rxbuf + 0, sizeof(raw_x));
+  memcpy(&raw_y, ist8310_rxbuf + 2, sizeof(raw_y));
+  memcpy(&raw_z, ist8310_rxbuf + 4, sizeof(raw_z));
+
+  ist8310->magn.x = (float)raw_x;
+  ist8310->magn.y = (float)raw_y;
+  ist8310->magn.z = (float)-raw_z;
+
+#else
+  const int16_t *raw_x = (int16_t *)(ist8310_rxbuf + 0);
+  const int16_t *raw_y = (int16_t *)(ist8310_rxbuf + 2);
+  const int16_t *raw_z = (int16_t *)(ist8310_rxbuf + 4);
+
+  ist8310->magn.x = (float)*raw_x;
+  ist8310->magn.y = (float)*raw_y;
+  ist8310->magn.z = -(float)*raw_z;
+#endif
+
+  ist8310->magn.x *= 3.0f / 20.0f;
+  ist8310->magn.y *= 3.0f / 20.0f;
+  ist8310->magn.z *= 3.0f / 20.0f;
+
+  ist8310->magn.x = (ist8310->magn.x - ist8310->cali->magn_offset.x) *
+                    ist8310->cali->magn_scale.x;
+  ist8310->magn.y = (ist8310->magn.y - ist8310->cali->magn_offset.y) *
+                    ist8310->cali->magn_scale.y;
+  ist8310->magn.z = (ist8310->magn.z - ist8310->cali->magn_offset.y) *
+                    ist8310->cali->magn_scale.z;
+
+  return DEVICE_OK;
+}
diff --git a/User/device/ist8310.h b/User/device/ist8310.h
new file mode 100644
index 0000000..df16cdd
--- /dev/null
+++ b/User/device/ist8310.h
@@ -0,0 +1,49 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include 
+
+#include "component/ahrs.h"
+#include "device/device.h"
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef struct {
+  struct {
+    float x;
+    float y;
+    float z;
+  } magn_offset; /* 磁力计偏置 */
+
+  struct {
+    float x;
+    float y;
+    float z;
+  } magn_scale;   /* 磁力计缩放 */
+} IST8310_Cali_t; /* IST8310校准数据 */
+
+typedef struct {
+  DEVICE_Header_t header;
+  AHRS_Magn_t magn;
+  const IST8310_Cali_t *cali;
+} IST8310_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+int8_t IST8310_Init(IST8310_t *ist8310, const IST8310_Cali_t *cali);
+int8_t IST8310_Restart(void);
+
+bool IST8310_WaitNew(uint32_t timeout);
+int8_t IST8310_StartDmaRecv();
+uint32_t IST8310_WaitDmaCplt();
+int8_t IST8310_Parse(IST8310_t *ist8310);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/motor.c b/User/device/motor.c
new file mode 100644
index 0000000..1fb059d
--- /dev/null
+++ b/User/device/motor.c
@@ -0,0 +1,52 @@
+/*
+    电机通用函数
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "motor.h"
+
+#include 
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+
+/* Private define ----------------------------------------------------------- */
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+
+/* Private function  -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+/* Exported functions ------------------------------------------------------- */
+float MOTOR_GetRotorAbsAngle(const MOTOR_t *motor) {
+  if (motor == NULL) return DEVICE_ERR_NULL;
+  return motor->feedback.rotor_abs_angle;
+}
+
+float MOTOR_GetRotorSpeed(const MOTOR_t *motor) {
+  if (motor == NULL) return DEVICE_ERR_NULL;
+  return motor->feedback.rotor_speed;
+}
+
+float MOTOR_GetTorqueCurrent(const MOTOR_t *motor) {
+  if (motor == NULL) return DEVICE_ERR_NULL;
+  return motor->feedback.torque_current;
+}
+
+float MOTOR_GetTemp(const MOTOR_t *motor) {
+  if (motor == NULL) return DEVICE_ERR_NULL;
+  return motor->feedback.temp;
+}
diff --git a/User/device/motor.h b/User/device/motor.h
new file mode 100644
index 0000000..e1f945b
--- /dev/null
+++ b/User/device/motor.h
@@ -0,0 +1,68 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "device/device.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Exported constants ------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef struct {
+    float rotor_abs_angle; /* 转子绝对角度 */
+    float rotor_speed; /* 实际转子转速 */
+    float torque_current; /* 转矩电流 */
+    float temp; /* 温度 */
+} MOTOR_Feedback_t;
+
+/**
+ * @brief mit电机输出参数结构体
+ */
+typedef struct {
+    float torque;      /* 目标力矩 */
+    float velocity;    /* 目标速度 */
+    float angle;       /* 目标位置 */
+    float kp;         /* 位置环增益 */
+    float kd;         /* 速度环增益 */
+} MOTOR_MIT_Output_t;
+
+/**
+ * @brief 转矩电流控制模式参数结构体
+ */
+typedef struct {
+    float current;    /* 目标电流 */
+} MOTOR_Current_Output_t;
+
+typedef struct {
+    DEVICE_Header_t header;
+    bool reverse; /* 是否反装 true表示反装 */
+    MOTOR_Feedback_t feedback;
+} MOTOR_t;
+
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Exported functions prototypes -------------------------------------------- */
+float MOTOR_GetRotorAbsAngle(const MOTOR_t *motor);
+float MOTOR_GetRotorSpeed(const MOTOR_t *motor);
+float MOTOR_GetTorqueCurrent(const MOTOR_t *motor);
+float MOTOR_GetTemp(const MOTOR_t *motor);
+
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/device/motor_dm.c b/User/device/motor_dm.c
new file mode 100644
index 0000000..703c936
--- /dev/null
+++ b/User/device/motor_dm.c
@@ -0,0 +1,516 @@
+#define MOTOR_DM_FLOAT_TO_INT_SIGNED(x, x_min, x_max, bits) \
+    ((int32_t)roundf(((x) / ((x_max) - (x_min))) * (1 << (bits)) + (1 << ((bits) - 1))))
+
+#define MOTOR_DM_INT_TO_FLOAT_SIGNED(x_int, x_min, x_max, bits) \
+    (((float)((int32_t)(x_int) - (1 << ((bits) - 1))) * ((x_max) - (x_min)) / (float)(1 << (bits))))
+/* Includes ----------------------------------------------------------------- */
+#include "device/motor_dm.h"
+#include "bsp/mm.h"
+#include "bsp/time.h"
+#include "component/user_math.h"
+#include "string.h"
+#include "math.h"
+
+/* Private constants -------------------------------------------------------- */
+/* DM电机数据映射范围 */
+#define DM_P_MIN   (-12.56637f)
+#define DM_P_MAX   (12.56637f)
+#define DM_V_MIN   (-30.0f)
+#define DM_V_MAX   (30.0f)
+#define DM_T_MIN   (-12.0f)
+#define DM_T_MAX   (12.0f)
+#define DM_KP_MIN  (0.0f)
+#define DM_KP_MAX  (500.0f)
+#define DM_KD_MIN  (0.0f)
+#define DM_KD_MAX  (5.0f)
+
+/* CAN ID偏移量 */
+#define DM_CAN_ID_OFFSET_POS_VEL  0x100
+#define DM_CAN_ID_OFFSET_VEL      0x200
+
+/* Private macro ------------------------------------------------------------ */
+#define FLOAT_TO_UINT(x, x_min, x_max, bits) \
+    (uint32_t)((x - x_min) * ((1 << bits) - 1) / (x_max - x_min))
+
+#define UINT_TO_FLOAT(x_int, x_min, x_max, bits) \
+    ((float)(x_int) * (x_max - x_min) / ((1 << bits) - 1) + x_min)
+
+
+/* Private variables -------------------------------------------------------- */
+static MOTOR_DM_CANManager_t *can_managers[BSP_CAN_NUM] = {NULL};
+
+static int float_to_uint(float x_float, float x_min, float x_max, int bits)
+{
+	/* Converts a float to an unsigned int, given range and number of bits */
+	float span = x_max - x_min;
+	float offset = x_min;
+	return (int) ((x_float-offset)*((float)((1<motor.feedback.rotor_abs_angle = uint_to_float(p_int, DM_P_MIN, DM_P_MAX, 16); // (-12.5,12.5)
+    uint16_t v_int=(data[3]<<4)|(data[4]>>4);
+    motor->motor.feedback.rotor_speed = uint_to_float(v_int, DM_V_MIN, DM_V_MAX, 12); // (-30.0,30.0)
+    uint16_t t_int=((data[4]&0xF)<<8)|data[5];
+    motor->motor.feedback.torque_current = uint_to_float(t_int, DM_T_MIN, DM_T_MAX, 12);  // (-12.0,12.0)
+    motor->motor.feedback.temp = (float)(data[6]);
+
+    while (motor->motor.feedback.rotor_abs_angle < 0) {
+        motor->motor.feedback.rotor_abs_angle += M_2PI;
+    }
+    while (motor->motor.feedback.rotor_abs_angle >= M_2PI) {
+        motor->motor.feedback.rotor_abs_angle -= M_2PI;
+    }
+
+    if (motor->param.reverse) {
+        motor->motor.feedback.rotor_abs_angle = M_2PI - motor->motor.feedback.rotor_abs_angle;
+        motor->motor.feedback.rotor_speed = -motor->motor.feedback.rotor_speed;
+        motor->motor.feedback.torque_current = -motor->motor.feedback.torque_current;
+    }
+    return DEVICE_OK;
+}
+
+/**
+ * @brief 发送MIT模式控制命令
+ * @param motor 电机实例
+ * @param output MIT控制参数
+ * @return 发送结果
+ */
+static int8_t MOTOR_DM_SendMITCmd(MOTOR_DM_t *motor, MOTOR_MIT_Output_t *output) {
+    if (motor == NULL || output == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+	uint8_t data[8];
+	uint16_t pos_tmp,vel_tmp,kp_tmp,kd_tmp,tor_tmp;
+	uint16_t id = motor->param.can_id;
+
+    /* 根据 reverse 参数调整控制值 */
+    float angle = output->angle;
+    float velocity = output->velocity;
+    float torque = output->torque;
+    if (motor->param.reverse) {
+        angle = -angle;
+        velocity = -velocity;
+        torque = -torque;
+    }
+
+	pos_tmp = float_to_uint(angle, DM_P_MIN , DM_P_MAX, 16);
+	vel_tmp = float_to_uint(velocity, DM_V_MIN , DM_V_MAX, 12);
+	kp_tmp  = float_to_uint(output->kp,   DM_KP_MIN, DM_KP_MAX, 12);
+	kd_tmp  = float_to_uint(output->kd,   DM_KD_MIN, DM_KD_MAX, 12);
+	tor_tmp = float_to_uint(torque, DM_T_MIN , DM_T_MAX, 12);
+
+    /* 打包数据 */
+	data[0] = (pos_tmp >> 8);
+	data[1] = pos_tmp;
+	data[2] = (vel_tmp >> 4);
+	data[3] = ((vel_tmp&0xF)<<4)|(kp_tmp>>8);
+	data[4] = kp_tmp;
+	data[5] = (kd_tmp >> 4);
+	data[6] = ((kd_tmp&0xF)<<4)|(tor_tmp>>8);
+	data[7] = tor_tmp;
+    
+    /* 发送CAN消息 */
+    BSP_CAN_StdDataFrame_t frame;
+    frame.id = motor->param.can_id;
+    frame.dlc = 8;
+    memcpy(frame.data, data, 8);
+    
+
+    return BSP_CAN_TransmitStdDataFrame(motor->param.can, &frame) == BSP_OK ? DEVICE_OK : DEVICE_ERR;
+}
+
+/**
+ * @brief 发送位置速度模式控制命令
+ * @param motor 电机实例
+ * @param pos 目标位置
+ * @param vel 目标速度
+ * @return 发送结果
+ */
+static int8_t MOTOR_DM_SendPosVelCmd(MOTOR_DM_t *motor, float pos, float vel) {
+    if (motor == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    uint8_t data[8] = {0};
+
+    /* 根据 reverse 参数调整控制值 */
+    if (motor->param.reverse) {
+        pos = -pos;
+        vel = -vel;
+    }
+    
+    /* 直接发送浮点数数据 */
+    memcpy(&data[0], &pos, 4);  // 位置，低位在前
+    memcpy(&data[4], &vel, 4);  // 速度，低位在前
+    
+    /* 发送CAN消息，ID为原ID+0x100 */
+    uint32_t can_id = DM_CAN_ID_OFFSET_POS_VEL + motor->param.can_id;
+    BSP_CAN_StdDataFrame_t frame;
+    frame.id = can_id;
+    frame.dlc = 8;
+    memcpy(frame.data, data, 8);
+    
+    return BSP_CAN_TransmitStdDataFrame(motor->param.can, &frame) == BSP_OK ? DEVICE_OK : DEVICE_ERR;
+}
+
+/**
+ * @brief 发送速度模式控制命令
+ * @param motor 电机实例
+ * @param vel 目标速度
+ * @return 发送结果
+ */
+static int8_t MOTOR_DM_SendVelCmd(MOTOR_DM_t *motor, float vel) {
+    if (motor == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    uint8_t data[4] = {0};
+    
+    /* 根据 reverse 参数调整控制值 */
+    if (motor->param.reverse) {
+        vel = -vel;
+    }
+    
+    /* 直接发送浮点数数据 */
+    memcpy(&data[0], &vel, 4);  // 速度，低位在前
+    
+    /* 发送CAN消息，ID为原ID+0x200 */
+    uint32_t can_id = DM_CAN_ID_OFFSET_VEL + motor->param.can_id;
+    BSP_CAN_StdDataFrame_t frame;
+    frame.id = can_id;
+    frame.dlc = 4;
+    memcpy(frame.data, data, 4);
+    
+    return BSP_CAN_TransmitStdDataFrame(motor->param.can, &frame) == BSP_OK ? DEVICE_OK : DEVICE_ERR;
+}
+
+/**
+ * @brief 获取指定CAN总线的管理器
+ * @param can CAN总线
+ * @return CAN管理器指针
+ */
+static MOTOR_DM_CANManager_t* MOTOR_DM_GetCANManager(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) {
+        return NULL;
+    }
+    
+    return can_managers[can];
+}
+
+/**
+ * @brief 创建CAN管理器
+ * @param can CAN总线
+ * @return 创建结果
+ */
+static int8_t MOTOR_DM_CreateCANManager(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) return DEVICE_ERR;
+    if (can_managers[can] != NULL) return DEVICE_OK;
+    
+    can_managers[can] = (MOTOR_DM_CANManager_t*)BSP_Malloc(sizeof(MOTOR_DM_CANManager_t));
+    if (can_managers[can] == NULL) return DEVICE_ERR;
+    
+    memset(can_managers[can], 0, sizeof(MOTOR_DM_CANManager_t));
+    can_managers[can]->can = can;
+    return DEVICE_OK;
+}
+
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * @brief 注册一个DM电机
+ * @param param 电机参数
+ * @return 注册结果
+ */
+int8_t MOTOR_DM_Register(MOTOR_DM_Param_t *param) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    /* 创建CAN管理器 */
+    if (MOTOR_DM_CreateCANManager(param->can) != DEVICE_OK) {
+        return DEVICE_ERR;
+    }
+    
+    /* 获取CAN管理器 */
+    MOTOR_DM_CANManager_t *manager = MOTOR_DM_GetCANManager(param->can);
+    if (manager == NULL) {
+        return DEVICE_ERR;
+    }
+    
+    /* 检查是否已注册 */
+    for (int i = 0; i < manager->motor_count; i++) {
+        if (manager->motors[i] && manager->motors[i]->param.master_id == param->master_id) {
+            return DEVICE_ERR_INITED;
+        }
+    }
+    
+    /* 检查是否已达到最大数量 */
+    if (manager->motor_count >= MOTOR_DM_MAX_MOTORS) {
+        return DEVICE_ERR;
+    }
+    
+    /* 分配内存 */
+    MOTOR_DM_t *motor = (MOTOR_DM_t *)BSP_Malloc(sizeof(MOTOR_DM_t));
+    if (motor == NULL) {
+        return DEVICE_ERR;
+    }
+    
+    /* 初始化电机 */
+    memset(motor, 0, sizeof(MOTOR_DM_t));
+    memcpy(&motor->param, param, sizeof(MOTOR_DM_Param_t));
+    motor->motor.header.online = false;
+    motor->motor.reverse = param->reverse;
+    
+    /* 注册CAN接收ID - DM电机使用Master ID接收反馈 */
+    uint16_t feedback_id = param->master_id;
+    if (BSP_CAN_RegisterId(param->can, feedback_id, 3) != BSP_OK) {
+        BSP_Free(motor);
+        return DEVICE_ERR;
+    }
+    
+    /* 添加到管理器 */
+    manager->motors[manager->motor_count] = motor;
+    manager->motor_count++;
+    
+    return DEVICE_OK;
+}
+
+/**
+ * @brief 更新指定电机数据
+ * @param param 电机参数
+ * @return 更新结果
+ */
+int8_t MOTOR_DM_Update(MOTOR_DM_Param_t *param) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_CANManager_t *manager = MOTOR_DM_GetCANManager(param->can);
+    if (manager == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    /* 查找电机 */
+    MOTOR_DM_t *motor = NULL;
+    for (int i = 0; i < manager->motor_count; i++) {
+        if (manager->motors[i] && manager->motors[i]->param.master_id == param->master_id) {
+            motor = manager->motors[i];
+            break;
+        }
+    }
+    
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    /* 主动接收CAN消息 */
+    uint16_t feedback_id = param->master_id;
+    BSP_CAN_Message_t rx_msg;
+    if (BSP_CAN_GetMessage(param->can, feedback_id, &rx_msg, BSP_CAN_TIMEOUT_IMMEDIATE) != BSP_OK) {
+        uint64_t now_time = BSP_TIME_Get();
+        if (now_time - motor->motor.header.last_online_time > 100000) {  // 100ms超时，单位微秒
+            motor->motor.header.online = false;
+        }
+        return DEVICE_ERR;
+    }
+    
+    motor->motor.header.online = true;
+    motor->motor.header.last_online_time = BSP_TIME_Get();
+    MOTOR_DM_ParseFeedbackFrame(motor, rx_msg.data);
+    
+    return DEVICE_OK;
+}
+
+/**
+ * @brief 更新所有电机数据
+ * @return 更新结果
+ */
+int8_t MOTOR_DM_UpdateAll(void) {
+    int8_t ret = DEVICE_OK;
+    for (int can = 0; can < BSP_CAN_NUM; can++) {
+        MOTOR_DM_CANManager_t *manager = MOTOR_DM_GetCANManager((BSP_CAN_t)can);
+        if (manager == NULL) continue;
+        
+        for (int i = 0; i < manager->motor_count; i++) {
+            MOTOR_DM_t *motor = manager->motors[i];
+            if (motor != NULL) {
+                if (MOTOR_DM_Update(&motor->param) != DEVICE_OK) {
+                    ret = DEVICE_ERR;
+                }
+            }
+        }
+    }
+    return ret;
+}
+
+/**
+ * @brief MIT模式控制
+ * @param param 电机参数
+ * @param output MIT控制参数
+ * @return 控制结果
+ */
+int8_t MOTOR_DM_MITCtrl(MOTOR_DM_Param_t *param, MOTOR_MIT_Output_t *output) {
+    if (param == NULL || output == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_t *motor = MOTOR_DM_GetMotor(param);
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    return MOTOR_DM_SendMITCmd(motor, output);
+}
+
+/**
+ * @brief 位置速度模式控制
+ * @param param 电机参数
+ * @param target_pos 目标位置
+ * @param target_vel 目标速度
+ * @return 控制结果
+ */
+int8_t MOTOR_DM_PosVelCtrl(MOTOR_DM_Param_t *param, float target_pos, float target_vel) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_t *motor = MOTOR_DM_GetMotor(param);
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    return MOTOR_DM_SendPosVelCmd(motor, target_pos, target_vel);
+}
+
+/**
+ * @brief 速度模式控制
+ * @param param 电机参数
+ * @param target_vel 目标速度
+ * @return 控制结果
+ */
+int8_t MOTOR_DM_VelCtrl(MOTOR_DM_Param_t *param, float target_vel) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_t *motor = MOTOR_DM_GetMotor(param);
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    return MOTOR_DM_SendVelCmd(motor, target_vel);
+}
+
+/**
+ * @brief 获取指定电机的实例指针
+ * @param param 电机参数
+ * @return 电机实例指针
+ */
+MOTOR_DM_t* MOTOR_DM_GetMotor(MOTOR_DM_Param_t *param) {
+    if (param == NULL) {
+        return NULL;
+    }
+    
+    MOTOR_DM_CANManager_t *manager = MOTOR_DM_GetCANManager(param->can);
+    if (manager == NULL) {
+        return NULL;
+    }
+    
+    /* 查找对应的电机 */
+    for (int i = 0; i < manager->motor_count; i++) {
+        MOTOR_DM_t *motor = manager->motors[i];
+        if (motor && motor->param.can == param->can && 
+            motor->param.master_id == param->master_id) {
+            return motor;
+        }
+    }
+    
+    return NULL;
+}
+
+
+int8_t MOTOR_DM_Enable(MOTOR_DM_Param_t *param){
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_t *motor = MOTOR_DM_GetMotor(param);
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+
+    BSP_CAN_StdDataFrame_t frame;
+    frame.id = motor->param.can_id;
+    frame.dlc = 8;
+    frame.data[0] = 0XFF;
+    frame.data[1] = 0xFF;
+    frame.data[2] = 0xFF;
+    frame.data[3] = 0xFF;
+    frame.data[4] = 0xFF;
+    frame.data[5] = 0xFF;
+    frame.data[6] = 0xFF;
+    frame.data[7] = 0xFC;
+
+    return BSP_CAN_TransmitStdDataFrame(motor->param.can, &frame) == BSP_OK ? DEVICE_OK : DEVICE_ERR;
+}
+
+/**
+ * @brief 使电机松弛（设置输出为0）
+ * @param param 电机参数
+ * @return 操作结果
+ */
+int8_t MOTOR_DM_Relax(MOTOR_DM_Param_t *param) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_MIT_Output_t output = {0};
+    return MOTOR_DM_MITCtrl(param, &output);
+}
+
+/**
+ * @brief 使电机离线（设置在线状态为false）
+ * @param param 电机参数
+ * @return 操作结果
+ */
+int8_t MOTOR_DM_Offine(MOTOR_DM_Param_t *param) {
+    if (param == NULL) {
+        return DEVICE_ERR_NULL;
+    }
+    
+    MOTOR_DM_t *motor = MOTOR_DM_GetMotor(param);
+    if (motor == NULL) {
+        return DEVICE_ERR_NO_DEV;
+    }
+    
+    motor->motor.header.online = false;
+    return DEVICE_OK;
+}
diff --git a/User/device/motor_dm.h b/User/device/motor_dm.h
new file mode 100644
index 0000000..20e91d4
--- /dev/null
+++ b/User/device/motor_dm.h
@@ -0,0 +1,98 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "device/device.h"
+#include "device/motor.h"
+#include "bsp/can.h"
+
+/* Exported constants ------------------------------------------------------- */
+#define MOTOR_DM_MAX_MOTORS 32
+
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+    MOTOR_DM_J4310,
+} MOTOR_DM_Module_t;
+
+/*每个电机需要的参数*/
+typedef struct {
+    BSP_CAN_t can;
+    uint16_t master_id;    /* 主站ID，用于发送控制命令 */
+    uint16_t can_id;       /* 反馈ID，用于接收电机反馈 */
+    MOTOR_DM_Module_t module;
+    bool reverse;
+} MOTOR_DM_Param_t;
+
+/*电机实例*/
+typedef struct{
+    MOTOR_DM_Param_t param;
+    MOTOR_t motor;
+} MOTOR_DM_t;
+
+/*CAN管理器，管理一个CAN总线上所有的电机*/
+typedef struct {
+    BSP_CAN_t can;
+    MOTOR_DM_t *motors[MOTOR_DM_MAX_MOTORS];
+    uint8_t motor_count;
+} MOTOR_DM_CANManager_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * @brief 注册一个LK电机
+ * @param param 电机参数
+ * @return 
+ */
+int8_t MOTOR_DM_Register(MOTOR_DM_Param_t *param);
+
+/**
+ * @brief 更新指定电机数据
+ * @param param 电机参数
+ * @return 
+ */
+int8_t MOTOR_DM_Update(MOTOR_DM_Param_t *param);
+
+/**
+ * @brief 更新所有电机数据
+ * @return 
+ */
+int8_t MOTOR_DM_UpdateAll(void);
+
+int8_t MOTOR_DM_MITCtrl(MOTOR_DM_Param_t *param, MOTOR_MIT_Output_t *output);
+
+int8_t MOTOR_DM_PosVelCtrl(MOTOR_DM_Param_t *param, float target_pos, float target_vel);
+
+int8_t MOTOR_DM_VelCtrl(MOTOR_DM_Param_t *param, float target_vel);
+
+/**
+ * @brief 获取指定电机的实例指针
+ * @param param 电机参数
+ * @return 
+ */
+MOTOR_DM_t* MOTOR_DM_GetMotor(MOTOR_DM_Param_t *param);
+
+int8_t MOTOR_DM_Enable(MOTOR_DM_Param_t *param);
+
+/**
+ * @brief 使电机松弛（设置输出为0）
+ * @param param 
+ * @return 
+ */
+int8_t MOTOR_DM_Relax(MOTOR_DM_Param_t *param);
+
+/**
+ * @brief 使电机离线（设置在线状态为false）
+ * @param param 
+ * @return 
+ */
+int8_t MOTOR_DM_Offine(MOTOR_DM_Param_t *param);
+
+
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/device/motor_rm.c b/User/device/motor_rm.c
new file mode 100644
index 0000000..88c1ef4
--- /dev/null
+++ b/User/device/motor_rm.c
@@ -0,0 +1,321 @@
+/*
+  RM电机驱动
+*/
+/* Includes ----------------------------------------------------------------- */
+#include "motor_rm.h"
+#include 
+#include 
+#include "bsp/can.h"
+#include "bsp/mm.h"
+#include "bsp/time.h"
+#include "component/user_math.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private define ----------------------------------------------------------- */
+#define GM6020_FB_ID_BASE        (0x205)
+#define GM6020_CTRL_ID_BASE      (0x1ff)
+#define GM6020_CTRL_ID_EXTAND    (0x2ff)
+
+#define M3508_M2006_FB_ID_BASE   (0x201)
+#define M3508_M2006_CTRL_ID_BASE (0x200)
+#define M3508_M2006_CTRL_ID_EXTAND (0x1ff)
+#define M3508_M2006_ID_SETTING_ID (0x700)
+
+#define GM6020_MAX_ABS_LSB       (30000)
+#define M3508_MAX_ABS_LSB        (16384)
+#define M2006_MAX_ABS_LSB        (10000)
+
+#define MOTOR_TX_BUF_SIZE        (8)
+#define MOTOR_RX_BUF_SIZE        (8)
+
+#define MOTOR_ENC_RES            (8192)   /* 电机编码器分辨率 */
+#define MOTOR_CUR_RES            (16384)  /* 电机转矩电流分辨率 */
+
+/* USER DEFINE BEGIN */
+
+/* USER DEFINE END */
+
+/* Private macro ------------------------------------------------------------ */
+/* Private typedef ---------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private variables -------------------------------------------------------- */
+static MOTOR_RM_CANManager_t *can_managers[BSP_CAN_NUM] = {NULL};
+
+/* Private function  -------------------------------------------------------- */
+/* USER FUNCTION BEGIN */
+
+/* USER FUNCTION END */
+
+static int8_t MOTOR_RM_GetLogicalIndex(uint16_t can_id, MOTOR_RM_Module_t module) {
+    switch (module) {
+        case MOTOR_M2006:
+        case MOTOR_M3508:
+            if (can_id >= M3508_M2006_FB_ID_BASE && can_id <= M3508_M2006_FB_ID_BASE + 7) {
+                return can_id - M3508_M2006_FB_ID_BASE;
+            }
+            break;
+        case MOTOR_GM6020:
+            if (can_id >= GM6020_FB_ID_BASE && can_id <= GM6020_FB_ID_BASE + 6) {
+                return can_id - GM6020_FB_ID_BASE + 4;
+            }
+            break;
+        default:
+            break;
+    }
+    return DEVICE_ERR;
+}
+
+static float MOTOR_RM_GetRatio(MOTOR_RM_Module_t module) {
+    switch (module) {
+        case MOTOR_M2006: return 36.0f;
+        case MOTOR_M3508: return 3591.0f / 187.0f;
+        case MOTOR_GM6020: return 1.0f;
+        default: return 1.0f;
+    }
+}
+
+static int16_t MOTOR_RM_GetLSB(MOTOR_RM_Module_t module) {
+    switch (module) {
+        case MOTOR_M2006: return M2006_MAX_ABS_LSB;
+        case MOTOR_M3508: return M3508_MAX_ABS_LSB;
+        case MOTOR_GM6020: return GM6020_MAX_ABS_LSB;
+        default: return DEVICE_ERR;
+    }
+}
+
+static MOTOR_RM_CANManager_t* MOTOR_RM_GetCANManager(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) return NULL;
+    return can_managers[can];
+}
+
+static int8_t MOTOR_RM_CreateCANManager(BSP_CAN_t can) {
+    if (can >= BSP_CAN_NUM) return DEVICE_ERR;
+    if (can_managers[can] != NULL) return DEVICE_OK;
+    can_managers[can] = (MOTOR_RM_CANManager_t*)BSP_Malloc(sizeof(MOTOR_RM_CANManager_t));
+    if (can_managers[can] == NULL) return DEVICE_ERR;
+    memset(can_managers[can], 0, sizeof(MOTOR_RM_CANManager_t));
+    can_managers[can]->can = can;
+    return DEVICE_OK;
+}
+
+static void Motor_RM_Decode(MOTOR_RM_t *motor, BSP_CAN_Message_t *msg) {
+    uint16_t raw_angle = (uint16_t)((msg->data[0] << 8) | msg->data[1]);
+    int16_t raw_speed = (int16_t)((msg->data[2] << 8) | msg->data[3]);
+    int16_t raw_current = (int16_t)((msg->data[4] << 8) | msg->data[5]);
+    int16_t lsb = MOTOR_RM_GetLSB(motor->param.module);
+    float ratio = MOTOR_RM_GetRatio(motor->param.module);
+
+    float rotor_angle = raw_angle / (float)MOTOR_ENC_RES * M_2PI;
+    float rotor_speed = raw_speed;
+    float torque_current = raw_current * lsb / (float)MOTOR_CUR_RES;
+
+    if (motor->param.gear) {
+        // 多圈累加
+        int32_t delta = (int32_t)raw_angle - (int32_t)motor->last_raw_angle;
+        if (delta > (MOTOR_ENC_RES / 2)) {
+            motor->gearbox_round_count--;
+        } else if (delta < -(MOTOR_ENC_RES / 2)) {
+            motor->gearbox_round_count++;
+        }
+        motor->last_raw_angle = raw_angle;
+        float single_turn = rotor_angle;
+        motor->gearbox_total_angle = (motor->gearbox_round_count * M_2PI + single_turn) / ratio;
+        // 输出轴多圈绝对值
+        motor->feedback.rotor_abs_angle = motor->gearbox_total_angle;
+        motor->feedback.rotor_speed = rotor_speed / ratio;
+        motor->feedback.torque_current = torque_current * ratio;
+    } else {
+        // 非gear模式，直接用转子单圈
+        motor->gearbox_round_count = 0;
+        motor->last_raw_angle = raw_angle;
+        motor->gearbox_total_angle = 0.0f;
+        motor->feedback.rotor_abs_angle = rotor_angle;
+        motor->feedback.rotor_speed = rotor_speed;
+        motor->feedback.torque_current = torque_current;
+    }
+        while (motor->feedback.rotor_abs_angle < 0) {
+            motor->feedback.rotor_abs_angle += M_2PI;
+        }
+        while (motor->feedback.rotor_abs_angle >= M_2PI) {
+            motor->feedback.rotor_abs_angle -= M_2PI;
+        }
+    if (motor->motor.reverse) {
+        motor->feedback.rotor_abs_angle = M_2PI - motor->feedback.rotor_abs_angle;
+        motor->feedback.rotor_speed = -motor->feedback.rotor_speed;
+        motor->feedback.torque_current = -motor->feedback.torque_current;
+    }
+    motor->feedback.temp = msg->data[6];
+}
+
+/* Exported functions ------------------------------------------------------- */
+
+int8_t MOTOR_RM_Register(MOTOR_RM_Param_t *param) {
+    if (param == NULL) return DEVICE_ERR_NULL;
+    if (MOTOR_RM_CreateCANManager(param->can) != DEVICE_OK) return DEVICE_ERR;
+    MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager(param->can);
+    if (manager == NULL) return DEVICE_ERR;
+    // 检查是否已注册
+    for (int i = 0; i < manager->motor_count; i++) {
+        if (manager->motors[i] && manager->motors[i]->param.id == param->id) {
+            return DEVICE_ERR_INITED;
+        }
+    }
+    // 检查数量
+    if (manager->motor_count >= MOTOR_RM_MAX_MOTORS) return DEVICE_ERR;
+    // 创建新电机实例
+    MOTOR_RM_t *new_motor = (MOTOR_RM_t*)BSP_Malloc(sizeof(MOTOR_RM_t));
+    if (new_motor == NULL) return DEVICE_ERR;
+    memcpy(&new_motor->param, param, sizeof(MOTOR_RM_Param_t));
+    memset(&new_motor->motor, 0, sizeof(MOTOR_t));
+    new_motor->motor.reverse = param->reverse;
+    // 注册CAN接收ID
+    if (BSP_CAN_RegisterId(param->can, param->id, 3) != BSP_OK) {
+        BSP_Free(new_motor);
+        return DEVICE_ERR;
+    }
+    manager->motors[manager->motor_count] = new_motor;
+    manager->motor_count++;
+    return DEVICE_OK;
+}
+
+int8_t MOTOR_RM_Update(MOTOR_RM_Param_t *param) {
+    if (param == NULL) return DEVICE_ERR_NULL;
+    MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager(param->can);
+    if (manager == NULL) return DEVICE_ERR_NO_DEV;
+    for (int i = 0; i < manager->motor_count; i++) {
+        MOTOR_RM_t *motor = manager->motors[i];
+        if (motor && motor->param.id == param->id) {
+            BSP_CAN_Message_t rx_msg;
+            if (BSP_CAN_GetMessage(param->can, param->id, &rx_msg, BSP_CAN_TIMEOUT_IMMEDIATE) != BSP_OK) {
+                uint64_t now_time = BSP_TIME_Get();
+                if (now_time - motor->motor.header.last_online_time > 1000) {
+                    motor->motor.header.online = false;
+                    return DEVICE_ERR_NO_DEV;
+                }
+                return DEVICE_ERR;
+            }
+            motor->motor.header.online = true;
+            motor->motor.header.last_online_time = BSP_TIME_Get();
+            Motor_RM_Decode(motor, &rx_msg);
+            motor->motor.feedback = motor->feedback;
+            return DEVICE_OK;
+        }
+    }
+    return DEVICE_ERR_NO_DEV;
+}
+
+int8_t MOTOR_RM_UpdateAll(void) {
+    int8_t ret = DEVICE_OK;
+    for (int can = 0; can < BSP_CAN_NUM; can++) {
+        MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager((BSP_CAN_t)can);
+        if (manager == NULL) continue;
+        for (int i = 0; i < manager->motor_count; i++) {
+            MOTOR_RM_t *motor = manager->motors[i];
+            if (motor != NULL) {
+                if (MOTOR_RM_Update(&motor->param) != DEVICE_OK) {
+                    ret = DEVICE_ERR;
+                }
+            }
+        }
+    }
+    return ret;
+}
+
+int8_t MOTOR_RM_SetOutput(MOTOR_RM_Param_t *param, float value) {
+    if (param == NULL) return DEVICE_ERR_NULL;
+    MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager(param->can);
+    if (manager == NULL) return DEVICE_ERR_NO_DEV;
+    if (value > 1.0f) value = 1.0f;
+    if (value < -1.0f) value = -1.0f;
+    if (param->reverse){
+        value = -value;
+    }
+    MOTOR_RM_t *motor = MOTOR_RM_GetMotor(param);
+    if (motor == NULL) return DEVICE_ERR_NO_DEV;
+    int8_t logical_index = MOTOR_RM_GetLogicalIndex(param->id, param->module);
+    if (logical_index < 0) return DEVICE_ERR;
+    MOTOR_RM_MsgOutput_t *output_msg = &manager->output_msg;
+    int16_t output_value = (int16_t)(value * (float)MOTOR_RM_GetLSB(param->module));
+    output_msg->output[logical_index] = output_value;
+    return DEVICE_OK;
+}
+
+int8_t MOTOR_RM_Ctrl(MOTOR_RM_Param_t *param) {
+    if (param == NULL) return DEVICE_ERR_NULL;
+    MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager(param->can);
+    if (manager == NULL) return DEVICE_ERR_NO_DEV;
+    MOTOR_RM_MsgOutput_t *output_msg = &manager->output_msg;
+    BSP_CAN_StdDataFrame_t tx_frame;
+    uint16_t id = param->id;
+    switch (id) {
+        case M3508_M2006_FB_ID_BASE:
+        case M3508_M2006_FB_ID_BASE+1:
+        case M3508_M2006_FB_ID_BASE+2:
+        case M3508_M2006_FB_ID_BASE+3:
+            tx_frame.id = M3508_M2006_CTRL_ID_BASE;
+            tx_frame.dlc = MOTOR_TX_BUF_SIZE;
+            for (int i = 0; i < 4; i++) {
+                tx_frame.data[i*2] = (uint8_t)((output_msg->output[i] >> 8) & 0xFF);
+                tx_frame.data[i*2+1] = (uint8_t)(output_msg->output[i] & 0xFF);
+            }
+            break;
+        case M3508_M2006_FB_ID_BASE+4:
+        case M3508_M2006_FB_ID_BASE+5:
+        case M3508_M2006_FB_ID_BASE+6:
+        case M3508_M2006_FB_ID_BASE+7:
+            tx_frame.id = M3508_M2006_CTRL_ID_EXTAND;
+            tx_frame.dlc = MOTOR_TX_BUF_SIZE;
+            for (int i = 4; i < 8; i++) {
+                tx_frame.data[(i-4)*2] = (uint8_t)((output_msg->output[i] >> 8) & 0xFF);
+                tx_frame.data[(i-4)*2+1] = (uint8_t)(output_msg->output[i] & 0xFF);
+            }
+            break;
+        case GM6020_FB_ID_BASE+4:
+        case GM6020_FB_ID_BASE+5:
+        case GM6020_FB_ID_BASE+6:
+            tx_frame.id = GM6020_CTRL_ID_EXTAND;
+            tx_frame.dlc = MOTOR_TX_BUF_SIZE;
+            for (int i = 8; i < 11; i++) {
+                tx_frame.data[(i-8)*2] = (uint8_t)((output_msg->output[i] >> 8) & 0xFF);
+                tx_frame.data[(i-8)*2+1] = (uint8_t)(output_msg->output[i] & 0xFF);
+            }
+            tx_frame.data[6] = 0;
+            tx_frame.data[7] = 0;
+            break;
+        default:
+            return DEVICE_ERR;
+    }
+    return BSP_CAN_TransmitStdDataFrame(param->can, &tx_frame) == BSP_OK ? DEVICE_OK : DEVICE_ERR;
+}
+
+MOTOR_RM_t* MOTOR_RM_GetMotor(MOTOR_RM_Param_t *param) {
+    if (param == NULL) return NULL;
+    MOTOR_RM_CANManager_t *manager = MOTOR_RM_GetCANManager(param->can);
+    if (manager == NULL) return NULL;
+    for (int i = 0; i < manager->motor_count; i++) {
+        MOTOR_RM_t *motor = manager->motors[i];
+        if (motor && motor->param.id == param->id) {
+            return motor;
+        }
+    }
+    return NULL;
+}
+
+int8_t MOTOR_RM_Relax(MOTOR_RM_Param_t *param) {
+    return MOTOR_RM_SetOutput(param, 0.0f);
+}
+
+int8_t MOTOR_RM_Offine(MOTOR_RM_Param_t *param) {
+    MOTOR_RM_t *motor = MOTOR_RM_GetMotor(param);
+    if (motor) {
+        motor->motor.header.online = false;
+        return DEVICE_OK;
+    }
+    return DEVICE_ERR_NO_DEV;
+}
\ No newline at end of file
diff --git a/User/device/motor_rm.h b/User/device/motor_rm.h
new file mode 100644
index 0000000..670b427
--- /dev/null
+++ b/User/device/motor_rm.h
@@ -0,0 +1,132 @@
+#pragma once
+
+#include "motor.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "device/device.h"
+#include "device/motor.h"
+#include "bsp/can.h"
+
+/* Exported constants ------------------------------------------------------- */
+#define MOTOR_RM_MAX_MOTORS 11
+
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+    MOTOR_M2006,
+    MOTOR_M3508,
+    MOTOR_GM6020,
+} MOTOR_RM_Module_t;
+
+/*一个can最多控制11个电机*/
+typedef union {
+  int16_t output[MOTOR_RM_MAX_MOTORS];
+  struct {
+    int16_t m3508_m2006_id201;
+    int16_t m3508_m2006_id202;
+    int16_t m3508_m2006_id203;
+    int16_t m3508_m2006_id204;
+    int16_t m3508_m2006_gm6020_id205;
+    int16_t m3508_m2006_gm6020_id206;
+    int16_t m3508_m2006_gm6020_id207;
+    int16_t m3508_m2006_gm6020_id208;
+    int16_t gm6020_id209;
+    int16_t gm6020_id20A;
+    int16_t gm6020_id20B;
+  } named;
+} MOTOR_RM_MsgOutput_t;
+
+/*每个电机需要的参数*/
+typedef struct {
+    BSP_CAN_t can;
+    uint16_t id;
+    MOTOR_RM_Module_t module;
+    bool reverse;
+    bool gear;
+} MOTOR_RM_Param_t;
+
+typedef MOTOR_Feedback_t MOTOR_RM_Feedback_t;
+
+typedef struct {
+    MOTOR_RM_Param_t param;
+    MOTOR_RM_Feedback_t feedback;
+    MOTOR_t motor;
+    // 多圈相关变量，仅gear模式下有效
+    uint16_t last_raw_angle;
+    int32_t gearbox_round_count;
+    float gearbox_total_angle;
+} MOTOR_RM_t;
+
+/*CAN管理器，管理一个CAN总线上所有的电机*/
+typedef struct {
+    BSP_CAN_t can;
+    MOTOR_RM_MsgOutput_t output_msg;
+    MOTOR_RM_t *motors[MOTOR_RM_MAX_MOTORS];
+    uint8_t motor_count;
+} MOTOR_RM_CANManager_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * @brief 注册一个RM电机
+ * @param param 电机参数
+ * @return 
+ */
+int8_t MOTOR_RM_Register(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 更新指定电机数据
+ * @param param 电机参数
+ * @return 
+ */
+int8_t MOTOR_RM_Update(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 设置一个电机的输出
+ * @param param 电机参数
+ * @param value 输出值，范围[-1.0, 1.0]
+ * @return 
+ */
+int8_t MOTOR_RM_SetOutput(MOTOR_RM_Param_t *param, float value);
+
+/**
+ * @brief 发送控制命令到电机，注意一个CAN可以控制多个电机，所以只需要发送一次即可
+ * @param param 电机参数
+ * @return 
+ */
+int8_t MOTOR_RM_Ctrl(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 获取指定电机的实例指针
+ * @param param 电机参数
+ * @return 
+ */
+MOTOR_RM_t* MOTOR_RM_GetMotor(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 使电机松弛（设置输出为0）
+ * @param param 
+ * @return 
+ */
+int8_t MOTOR_RM_Relax(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 使电机离线（设置在线状态为false）
+ * @param param 
+ * @return 
+ */
+int8_t MOTOR_RM_Offine(MOTOR_RM_Param_t *param);
+
+/**
+ * @brief 
+ * @param  
+ * @return 
+ */
+int8_t MOTOR_RM_UpdateAll(void);
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file
diff --git a/User/module/chassis.c b/User/module/chassis.c
new file mode 100644
index 0000000..8b1c493
--- /dev/null
+++ b/User/module/chassis.c
@@ -0,0 +1,300 @@
+/*
+底盘模组
+*/
+
+
+#include "cmsis_os2.h"
+#include 
+#include "bsp/mm.h"
+#include "bsp/can.h"
+#include "component/ahrs.h"
+#include "device/motor_rm.h"
+#include "device/motor.h"
+#include "module/chassis.h"
+
+/**
+ * @brief 底盘小陀螺模式相关参数
+ */
+#define CHASSIS_ROTOR_WZ_MIN 0.6f       //小陀螺最小速度
+#define CHASSIS_ROTOR_WZ_MAX 0.8f				//小陀螺最大速度
+#define M_7OVER72PI (M_2PI * 7.0f / 72.0f)   //角度偏移量（用在跟随云台35°）
+#define CHASSIS_ROTOR_OMEGA 0.001f        //角速度变化频率
+
+
+
+/**
+ * @brief 设置底盘模式
+ * @param c 底盘结构体指针
+ * @param mode 目标控制模式
+ * @param now 当前时间戳(ms)
+ * @return CHASSIS_OK:成功   CHASSIS_ERR_NULL:空
+ */
+static int8_t Chassis_SetMode(Chassis_t *c, Chassis_Mode_t mode, uint32_t now) {
+    if (!c) 
+			return CHASSIS_ERR_NULL;
+    if (mode == c->mode)
+			return CHASSIS_OK;
+//随机种子，小陀螺模式随机设置旋转方向
+    if (mode == CHASSIS_MODE_ROTOR && c->mode != CHASSIS_MODE_ROTOR) {
+        srand(now);
+        c->wz_multi = (rand() % 2) ? -1 : 1;
+    }
+//重置PID和滤波
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+        PID_Reset(&c->pid.motor[i]);
+        LowPassFilter2p_Reset(&c->filter.in[i], 0.0f);
+        LowPassFilter2p_Reset(&c->filter.out[i], 0.0f);
+    }
+
+    c->mode = mode;
+    return CHASSIS_OK;
+}
+
+/**
+ * @brief 小陀螺模式动态角速度
+ * @param min 最小速度
+ * @param max 最大速度
+ * @param now 当前时间戳(ms)
+ * @return 角速度值
+ */
+static float Chassis_CalcWz(const float min, const float max, uint32_t now) {
+    float wz_vary = fabsf(0.2f * sinf(CHASSIS_ROTOR_OMEGA * (float)now)) + min;
+    return (wz_vary > max) ? max : wz_vary;
+}
+
+/**
+ * @brief 底盘模式初始化
+ * @param c 底盘结构体指针
+ * @param param  底盘参数结构体指针
+ * @param mech_zero 机械零点欧拉角
+ * @param target_freq 控制频率(Hz)
+ * @return CHASSIS_OK:成功 CHASSIS_ERR_NULL:空 CHASSIS_ERR_TYPE:不支持的模式
+ */
+int8_t Chassis_Init(Chassis_t *c, const Chassis_Params_t *param,
+                    float target_freq) {
+    if (!c) return CHASSIS_ERR_NULL;
+											
+		//初始化CAN通信									
+		BSP_CAN_Init();
+    c->param = param;
+    c->mode = CHASSIS_MODE_RELAX;
+		c->param->feedforward.coefficient = 0.1f;				//前馈系数				
+//根据底盘不同设置模式轮子与混合器
+    Mixer_Mode_t mixer_mode;
+    switch (param->type) {
+        case CHASSIS_TYPE_MECANUM://麦轮
+					c->num_wheel = 4; 
+				mixer_mode = MIXER_MECANUM;
+				break;
+        case CHASSIS_TYPE_PARLFIX4:
+					c->num_wheel = 4; 
+				mixer_mode = MIXER_PARLFIX4;
+				break;
+        case CHASSIS_TYPE_PARLFIX2:
+					c->num_wheel = 2; 
+				mixer_mode = MIXER_PARLFIX2; 
+				break;
+        case CHASSIS_TYPE_OMNI_CROSS:
+					c->num_wheel = 4;
+				mixer_mode = MIXER_OMNICROSS;
+				break;
+        case CHASSIS_TYPE_OMNI_PLUS: //全向轮（老步兵类型）
+					c->num_wheel = 4;
+				mixer_mode = MIXER_OMNIPLUS;
+				break;
+        case CHASSIS_TYPE_SINGLE:
+					c->num_wheel = 1; 
+				mixer_mode = MIXER_SINGLE;
+				break;
+        default: 
+					return CHASSIS_ERR_TYPE;
+    }
+		//初始化时间戳
+				c->last_wakeup = 0;
+				c->dt = 0.0f;
+		//初始化PID和滤波
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+        PID_Init(&c->pid.motor[i], KPID_MODE_NO_D, target_freq, ¶m->pid.motor_pid_param);
+        LowPassFilter2p_Init(&c->filter.in[i], target_freq, param->low_pass_cutoff_freq.in);
+        LowPassFilter2p_Init(&c->filter.out[i], target_freq, param->low_pass_cutoff_freq.out);
+			//清零电机反馈
+				c->feedback.motor[i].rotor_speed = 0;
+        c->feedback.motor[i].torque_current = 0;
+        c->feedback.motor[i].rotor_abs_angle = 0;
+        c->feedback.motor[i].temp = 0;
+    }
+     //初始化PID和混合器
+    PID_Init(&c->pid.follow, KPID_MODE_NO_D, target_freq, ¶m->pid.follow_pid_param);
+    Mixer_Init(&c->mixer, mixer_mode);
+     //清零运动向量和输出
+    c->move_vec.vx = c->move_vec.vy = c->move_vec.wz = 0.0f;
+		for (uint8_t i = 0; i < c->num_wheel; i++) { 
+				c->out.motor[i] = 0.0f;
+		}
+		//注册大疆电机
+		for (int i = 0; i < c->num_wheel; i++) {
+			MOTOR_RM_Register(&(c->param->motor_param[i]));
+			 
+		}
+    return CHASSIS_OK;
+}
+
+/**
+ * @brief 更新电机反馈(IMU+电机状态)
+ * @param c 底盘结构体指针
+ * @param feedback 底盘反馈指针结构体
+ * @return CHASSIS_OK:成功 CHASSIS_ERR_NULL:空
+ */
+int8_t Chassis_UpdateFeedback(Chassis_t *c) {
+
+		//更新所有电机反馈
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+			MOTOR_RM_Update(&(c->param->motor_param[i])); 
+			MOTOR_RM_t *rm_motor = MOTOR_RM_GetMotor(&(c->param->motor_param[i]));
+			c->motors[i] = rm_motor;
+			MOTOR_RM_t *rm = c->motors[i];
+         if (rm_motor != NULL) {
+            c->feedback.motor[i] = rm_motor->feedback;
+             }else 
+					{ 
+					return CHASSIS_ERR_NULL; 
+					} 
+		}
+    return CHASSIS_OK;
+}
+
+
+/**
+ * @brief 底盘电机控制
+ * @param c 底盘结构体指针
+ * @param c_cmd 控制命令
+ * @param now 当前时间戳(ms)
+ * @return CHASSIS_OK:成功 CHASSIS_ERR_NULL:空
+ */
+int8_t Chassis_Control(Chassis_t *c, const Chassis_CMD_t *c_cmd, uint32_t now) {
+    if (!c || !c_cmd) return CHASSIS_ERR_NULL;
+		//计算控制周期
+    c->dt = (float)(now - c->last_wakeup) / 1000.0f; 
+    c->last_wakeup = now;
+		if (!isfinite(c->dt) || c->dt <= 0.0f) {
+				c->dt = 0.001f;            
+		}
+		if (c->dt < 0.0005f) c->dt = 0.0005f;   
+		if (c->dt > 0.050f)  c->dt = 0.050f;    
+    //设置模式
+    Chassis_SetMode(c, c_cmd->mode, now);
+    //不同模式下对应解算（运动向量）
+    switch (c->mode) {
+        case CHASSIS_MODE_BREAK:
+            c->move_vec.vx = c->move_vec.vy = 0.0f;
+            break;
+        case CHASSIS_MODE_INDEPENDENT:
+            c->move_vec.vx = c_cmd->ctrl_vec.vx ;
+            c->move_vec.vy = c_cmd->ctrl_vec.vy ;
+            break;
+        default: {      //遥控器坐标->机体坐标系
+            float beta = c->feedback.encoder_gimbalYawMotor - c->mech_zero;
+            float cosb = cosf(beta);
+            float sinb = sinf(beta);
+            c->move_vec.vx = cosb * c_cmd->ctrl_vec.vx - sinb * c_cmd->ctrl_vec.vy ;
+            c->move_vec.vy = sinb * c_cmd->ctrl_vec.vx + cosb * c_cmd->ctrl_vec.vy ;
+            break;
+        }
+    }
+		//根据模式计算底盘角速度
+    switch (c->mode) {
+        case CHASSIS_MODE_RELAX:
+        case CHASSIS_MODE_BREAK:
+        case CHASSIS_MODE_INDEPENDENT:
+            c->move_vec.wz = 0.0f;
+            break;
+        case CHASSIS_MODE_OPEN:
+						c->move_vec.wz = c_cmd->ctrl_vec.wz ;
+						break;
+				//云台跟随
+        case CHASSIS_MODE_FOLLOW_GIMBAL:
+            c->move_vec.wz = PID_Calc(&c->pid.follow, c->mech_zero, c->feedback.encoder_gimbalYawMotor, 0.0f, c->dt) ;
+            break;
+				//云台跟随（偏移）
+        case CHASSIS_MODE_FOLLOW_GIMBAL_35:
+            c->move_vec.wz = PID_Calc(&c->pid.follow,c->mech_zero +M_7OVER72PI, c->feedback.encoder_gimbalYawMotor, 0.0f, c->dt) ;
+            break;
+				//小陀螺
+        case CHASSIS_MODE_ROTOR:
+            c->move_vec.wz = c->wz_multi * Chassis_CalcWz(CHASSIS_ROTOR_WZ_MIN,CHASSIS_ROTOR_WZ_MAX, now) ;
+            break;
+    }
+        //运动学逆解算，运动向量分解为电机转速
+    Mixer_Apply(&c->mixer, &c->move_vec, c->setpoint.motor_rpm, c->num_wheel, 500.0f);
+
+
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+				float rf = c->setpoint.motor_rpm[i];///目标转速
+        float fb = LowPassFilter2p_Apply(&c->filter.in[i], (float)c->feedback.motor[i].rotor_speed);
+				float out_current;
+        switch (c->mode) {
+            case CHASSIS_MODE_BREAK:
+            case CHASSIS_MODE_FOLLOW_GIMBAL:
+            case CHASSIS_MODE_FOLLOW_GIMBAL_35:
+            case CHASSIS_MODE_ROTOR:
+            case CHASSIS_MODE_INDEPENDENT:
+                out_current = PID_Calc(&c->pid.motor[i], c->setpoint.motor_rpm[i], fb, 0.0f, c->dt);
+								const float K_FF = c->param->feedforward.coefficient; //前馈系数，具体值在初始化部分，使用时可以自己修改。
+                float feedforward_current = K_FF * c->setpoint.motor_rpm[i];
+                out_current += feedforward_current; //总电流 = 前馈电流 + 反馈电流
+                break;
+            case CHASSIS_MODE_OPEN:
+                out_current = c->setpoint.motor_rpm[i] / 7000.0f ;
+                break;
+            case CHASSIS_MODE_RELAX:
+                out_current = 0.0f ;
+                break;
+        }
+
+       //低通滤波和限幅
+         c->out.motor[i] = LowPassFilter2p_Apply(&c->filter.out[i], out_current);
+				 Clip(&c->out.motor[i], -c->param->limit.max_current, c->param->limit.max_current);
+    }
+
+			
+    return CHASSIS_OK;
+}
+
+/**
+ * @brief 电机输出
+ * @param c 底盘结构体指针
+ */
+void Chassis_Output(Chassis_t *c) {
+    if (!c) 
+			return;
+
+    //每个电机目标输出
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+        MOTOR_RM_t *rm = c->motors[i];
+        if (!rm) continue;
+        MOTOR_RM_SetOutput(&rm->param, c->out.motor[i]);
+    }
+
+    //调用ctrl
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+        MOTOR_RM_t *rm = c->motors[i];
+        if (rm) {
+            MOTOR_RM_Ctrl(&rm->param);
+        }
+    }
+}
+
+/**
+ * @brief 重置底盘输出
+ * @param c  底盘结构体指针
+ */
+void Chassis_ResetOutput(Chassis_t *c) {
+    if (!c) return;
+    for (uint8_t i = 0; i < c->num_wheel; i++) {
+        MOTOR_RM_t *m = c->motors[i];
+        if (m) {
+            MOTOR_RM_Relax(&(m->param));
+        }
+    }
+}
+
diff --git a/User/module/chassis.h b/User/module/chassis.h
new file mode 100644
index 0000000..d9d8051
--- /dev/null
+++ b/User/module/chassis.h
@@ -0,0 +1,241 @@
+/*
+底盘头文件
+ */
+#pragma once
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "bsp/can.h"
+#include "component\filter.h"
+#include "component\mixer.h"
+#include "component\pid.h"
+#include "component\ahrs.h"
+#include "device/motor_rm.h"
+/* Exported constants ------------------------------------------------------- */
+#define CHASSIS_OK (0)        /*运行正常*/
+#define CHASSIS_ERR (-1)      /*运行错误*/
+#define CHASSIS_ERR_NULL (-2) /*空指针错误*/
+#define CHASSIS_ERR_MODE (-3) /*模式错误*/
+#define CHASSIS_ERR_TYPE (-4) /*类型错误*/
+	
+#define MAX_MOTOR_CURRENT 20.0f 
+/* 底盘控制模式 */
+typedef enum {
+  CHASSIS_MODE_RELAX, /*放松模式，电机不转动*/
+  CHASSIS_MODE_BREAK, /* 制动模式，电机立即停止 */
+  CHASSIS_MODE_FOLLOW_GIMBAL, /* 跟随模式，电机根据云台角度旋转 */
+  CHASSIS_MODE_FOLLOW_GIMBAL_35, /* 跟随模式，电机根据云台角度旋转35度 */
+  CHASSIS_MODE_ROTOR, /* 旋转模式，电机根据旋转角度旋转 */
+  CHASSIS_MODE_INDEPENDENT,/* 独立模式，电机根据指令独立旋转 */
+  CHASSIS_MODE_OPEN, /* 开放模式，电机根据指令直接旋转 */
+} Chassis_Mode_t;
+	
+/* 底盘小陀螺模式 */
+typedef enum {
+  ROTOR_MODE_CW,  // 顺时针旋转
+  ROTOR_MODE_CCW,  // 逆时针旋转
+  ROTOR_MODE_RAND, // 随机旋转
+} Chassis_RotorMode_t;
+
+/* 底盘控制命令 */
+typedef struct {
+  Chassis_Mode_t mode;     /* 底盘运动模式*/
+  Chassis_RotorMode_t mode_rotor; /* 小陀螺模式旋转方向*/
+  MoveVector_t ctrl_vec;  /* 底盘运动控制向量*/
+} Chassis_CMD_t;
+
+/* 限位好像没用到 */
+typedef struct {
+  float max;
+  float min;
+} Chassis_Limit_t;
+
+	/* 底盘类型 */
+typedef enum {
+  CHASSIS_TYPE_MECANUM,    /* 麦克纳姆轮底盘 */
+  CHASSIS_TYPE_PARLFIX4,   /* 平行固定4轮底盘 */
+  CHASSIS_TYPE_PARLFIX2,   /* 平行固定2轮底盘 */
+  CHASSIS_TYPE_OMNI_CROSS, /* 十字.omni轮底盘 */
+  CHASSIS_TYPE_OMNI_PLUS,  /* X型.omni轮底盘 */
+  CHASSIS_TYPE_DRONE,     /* 无人机底盘 */
+  CHASSIS_TYPE_SINGLE,     /* 单轮底盘 */
+} Chassis_Type_t;
+
+
+/* 底盘参数结构体 ，初始化参数*/
+typedef struct {
+	MOTOR_RM_Param_t motor_param[4];
+	  struct {
+    KPID_Params_t motor_pid_param;  /* 电机转速PID参数 */
+    KPID_Params_t follow_pid_param; /* 跟随PID参数 */
+  } pid;
+  Chassis_Type_t type; /* 底盘类型 */
+
+/* 低通滤波器截止频率设置 */
+  struct {
+    float in;  /* 输入 */
+    float out; /* 输出 */
+  } low_pass_cutoff_freq;
+
+  /*电机反装，设置与云台相同，但貌似没啥用*/
+  struct {
+    bool yaw;
+  } reverse;
+	struct {
+        float max_vx, max_vy, max_wz;
+        float max_current; 
+    } limit; 
+	
+	/*前馈相关系数*/
+	struct {
+    float coefficient; 
+  } feedforward;  
+
+} Chassis_Params_t;
+
+typedef struct {
+  AHRS_Gyro_t gyro;
+  AHRS_Eulr_t eulr;
+} Chassis_IMU_t;
+
+typedef struct {
+  MOTOR_Feedback_t motor[4];           /* 电机反馈 */
+	float encoder_gimbalYawMotor;
+} Chassis_Feedback_t;
+
+/* 底盘输出结构体 */
+typedef struct {
+	float motor[4];  /* 电机输出电流目标值，范围[-1,1],对应最大电流 */
+} Chassis_Output_t;
+
+/* 底盘主结构体 */
+typedef struct {
+  uint64_t last_wakeup;
+  float dt;
+
+  Chassis_Params_t *param; /* 底盘参数指针 */
+
+  /* 底盘状态 */
+  Chassis_Mode_t mode; /* 底盘运动模式 */
+
+
+  /* 底盘设计 */
+  int8_t num_wheel; /* 底盘轮子数量 */
+  Mixer_t mixer;   /* 混合器 */
+  MoveVector_t move_vec; /* 底盘运动控制向量 */
+  MOTOR_RM_t *motors[4]; /* 电机指针数组 */
+	float mech_zero; /* 机械零点 */
+  float wz_multi; /* 小陀螺模式旋转角度系数 */
+
+  /*PID计算目标值*/
+  struct {
+    float motor_rpm[4]; /* 电机转速目标值，单位rpm */
+  } setpoint;
+
+/* 反馈控制PID计算 */
+  struct {
+    KPID_t motor[4]; /* 电机转速PID */
+    KPID_t follow; /* 跟随PID */
+  } pid;
+ 
+	struct {
+        Chassis_Limit_t vx, vy, wz; 
+    } limit; 
+
+  /*滤波器*/
+  struct {
+    LowPassFilter2p_t in[4];  /* 电机速度反馈滤波器 */
+    LowPassFilter2p_t out[4]; /* 电机速度输出滤波器 */
+  } filter;
+
+  Chassis_Output_t out;;          /* 底盘输出结构体 */
+	Chassis_Feedback_t feedback;
+	//float out_motor[4];
+} Chassis_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * \brief 底盘初始化
+ *
+ * \param c 底盘结构体指针
+ * \param param 底盘参数指针
+ * \param target_freq 目标频率，单位Hz
+ *
+ * \return 运行结果，CHASSIS_OK:成功
+ */
+int8_t Chassis_Init(Chassis_t *c, const Chassis_Params_t *param,
+                    float target_freq);
+
+/**
+ * \brief 更新底盘反馈
+ *
+ * \param c 底盘结构体指针
+ *
+ * \return 运行结果，CHASSIS_OK:成功
+ */
+int8_t Chassis_UpdateFeedback(Chassis_t *c);
+
+/**
+ * \brief 底盘控制
+ *
+ * \param c 底盘结构体指针
+ * \param c_cmd 底盘控制命令指针
+ * \param now 当前时间戳，单位ms
+ *
+ * \return 运行结果，CHASSIS_OK:成功
+ */
+int8_t Chassis_Control(Chassis_t *c, const Chassis_CMD_t *c_cmd,
+                       uint32_t now);
+
+
+/**
+  * \brief 底盘输出
+  * \param c 底盘结构体指针
+ */
+
+void Chassis_Output(Chassis_t *c);
+
+/**
+ * \brief 底盘输出重置
+ *
+ * \param c 底盘结构体指针
+ */
+void Chassis_ResetOutput(Chassis_t *c);
+
+/**
+ * \brief 底盘功率限制
+ *
+ * \param c 底盘结构体指针
+ * \param cap 电容数据指针
+ * \param ref 比赛数据指针
+ *
+ * \return 运行结果，CHASSIS_OK:成功
+ */
+//<2F><>ûм룬waiting<6E><67>int8_t Chassis_PowerLimit(Chassis_t *c, const CAN_Capacitor_t *cap,
+//                          const Referee_ForChassis_t *ref);
+
+
+/**
+ * \brief 底盘UI数据填充
+ *
+ * \param c 底盘结构体指针
+ * \param ui 底盘UI数据指针
+ *
+ * \return 无
+ */
+//void Chassis_DumpUI(const Chassis_t *c, Referee_ChassisUI_t *ui);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+
diff --git a/User/module/config.c b/User/module/config.c
new file mode 100644
index 0000000..458e752
--- /dev/null
+++ b/User/module/config.c
@@ -0,0 +1,375 @@
+/*
+ * 配置相关
+ */
+
+/* Includes ----------------------------------------------------------------- */
+#include "user_math.h"
+#include "module/config.h"
+#include "bsp/can.h"
+#include "shoot.h"
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+
+/* Exported variables ------------------------------------------------------- */
+
+// 机器人参数配置
+Config_RobotParam_t robot_config = {
+
+
+	
+.gimbal_param = {
+	/* 云台欧拉角与角速度自由选择 */
+	.Direction={
+			.Eulr={
+					.pit=Rol,
+					.yaw=Yaw,			
+				},
+			.Gyro={
+					.pit=Gyro_x,
+					.yaw=Gyro_z,
+			},	
+
+			
+	},
+	/*欧拉角限位和电机角度限位*/
+	 .Limit_t= {
+						.pit_max= 0.21,
+						.pit_min=-0.53,
+		 			/*零点参数*/
+				.zero={
+					.yaw_encoder=1.26,
+					
+					.travel={
+						.yaw=1.5,				
+					},
+				},
+			},
+	 
+
+			.feedforward={
+				.imu = {
+					.yaw=false,
+					.pit=false,
+					},
+
+			},
+			
+
+				
+				.motor={
+					/*按自己需求选择电机*/
+//					.major_yaw=DM,
+					.pit=RM,
+					.yaw=RM,
+					/*是否开启限位*/
+					.limit_yaw=false,
+					.limit_pit=true,
+					.pit_rm_motor={BSP_CAN_2,0x20A,MOTOR_GM6020,false,true},
+					.yaw_rm_motor={BSP_CAN_2,0x209,MOTOR_GM6020,false,true},	
+						/*达妙电机参数自己配*/
+					.major_yaw_dm_motor={
+					    .can=BSP_CAN_2,
+							.can_id = 0x1,
+							.master_id=0x11,
+							.module = MOTOR_DM_J4310,
+							.reverse=false
+					},
+					.pit_dm_motor={
+					    .can=BSP_CAN_2,
+							.can_id = 0x2,
+							.master_id=0x12,
+							.module = MOTOR_DM_J4310,
+							.reverse=true,					
+					},
+//					.yaw_dm_motor={},
+				},
+			.dm_Params_t={
+//			.yaw_dm={.kd=0.1,},
+//			.yaw_dm_Reduction_ratio=1.0f,//减速比
+			.pit_dm={.kd=0.2,},
+			.pit_dm_Reduction_ratio=1.0f,
+			.major_yaw_dm={.kd=0.2,},
+			.major_yaw_dm_Reduction_ratio=1.0f,//减速比
+		},
+			
+    .low_pass_cutoff_freq = {
+      .out = -1.0f,
+      .gyro = 1000.0f,
+    },
+
+        .pid = {
+					/* 大yaw参数 */
+						.major_yaw_omega={
+								.k = 0.0f,
+								.p = 0.08f,
+								.i = 0.1f,
+								.d = 0.0f,
+								.i_limit = 0.0f,
+								.out_limit = 12.0f,
+								.d_cutoff_freq = -1.0f,
+								.range = -1.0f						
+						},
+						.major_yaw_angle={
+								.k = 1.0f,
+								.p = 75.0f,//36.5
+								.i = 20.0f,
+								.d = 0.2f,
+								.i_limit =5.0f,
+								.out_limit = 12.0f,
+								.d_cutoff_freq = 20.0f,
+								.range = M_2PI							
+						},					
+					
+					/*欧拉角控制参数*/
+			
+             .yaw_omega = {
+							.k = 0.24f,
+							.p = 1.0f,
+							.i = 0.5f,
+							.d = 0.0f,
+							.i_limit = 1.0f,
+							.out_limit = 1.0f,
+							.d_cutoff_freq = -1.0f,
+							.range = -1.0f,
+            },
+            .yaw_angle = {
+							.k = 10.0f,
+							.p = 1.0f,
+							.i = 0.0f,
+							.d = 0.05f,
+							.i_limit = 0.0f,
+							.out_limit = 10.0f,
+							.d_cutoff_freq = -1.0f,
+							.range = M_2PI,
+            },
+            .pit_omega = {
+							.k = 0.25f,
+							.p = 1.0f,
+							.i = 0.0f,
+							.d = 0.0f,
+							.i_limit = 1.0f,
+							.out_limit = 1.0f,
+							.d_cutoff_freq = -1.0f,
+							.range = -1.0f,
+            },
+            .pit_angle = {
+							.k = 2.0f,
+							.p = 5.0f,
+							.i = 2.5f,
+							.d = 0.0f,
+							.i_limit = 0.0f,
+							.out_limit = 10.0f,
+							.d_cutoff_freq = -1.0f,
+							.range = M_2PI,
+            },		
+
+						
+					}       
+		},
+
+		.shoot_param = {
+        .basic={
+          .projectileType=SHOOT_PROJECTILE_17MM,
+		      .fric_num=2,
+		      .extra_deceleration_ratio=36.0f,
+          .num_trig_tooth=10,
+          .shot_freq=10.0f,
+          .shot_burst_num=5,
+          .ratio_multilevel = {1.0f},
+        },   
+        .jamDetection={
+            .enable=true,
+            .threshold=105.0f, 
+            .suspectedTime=1.0f, 
+        },
+        .motor={
+            .fric = {
+                {
+                    .param = {
+                        .can = BSP_CAN_2,
+                        .id = 0x201,
+                        .module = MOTOR_M2006,
+                        .reverse = false,
+                        .gear = false,
+                    },
+                    .level=1,
+                },
+                {
+                    .param = {
+                        .can = BSP_CAN_2,
+                        .id = 0x202,
+                        .module = MOTOR_M2006,
+                        .reverse = true,
+                        .gear = false,
+                    },
+                    .level=1,
+                },
+
+            },
+            .trig = {
+                .can = BSP_CAN_2,
+                .id = 0x203,
+                .module = MOTOR_M2006,
+                .reverse = false,
+                .gear=true,
+            },
+        },
+        .pid={      
+            .fric_follow = {
+								.k = 0.001f,
+								.p = 1.0f,
+								.i = 0.2f,
+								.d = 0.01f,
+								.i_limit = 0.5f,
+								.out_limit = 0.5f,
+								.d_cutoff_freq = -1.0f,
+            },
+            .fric_err = {
+                .k=0.0f,
+                .p=4.0f,
+                .i=0.4f,
+                .d=0.0f,
+                .i_limit=0.25f,
+                .out_limit=0.25f, 
+                .d_cutoff_freq=-1.0f,
+                .range=-1.0f, 
+            },
+            .trig_2006 = {
+									.k = 12.0f,
+									.p = 1.0f,
+									.i = 0.0f,
+									.d = 0.0450000018f,
+									.i_limit = 1.0f,
+									.out_limit = 1.0f,
+									.d_cutoff_freq = -1.0f,
+									.range = M_2PI,
+            },
+            .trig_omg_2006 = {
+                .k=2.0f,
+                .p=1.5f,
+                .i=0.3f,
+                .d=0.5f,
+                .i_limit=0.2f,
+                .out_limit=1.0f,
+                .d_cutoff_freq=-1.0f,
+                .range=-1.0f,
+            },
+//            .trig_3508 = {
+//                .k=0.5f,
+//                .p=1.8f,
+//                .i=0.3f,
+//                .d=0.1f,
+//                .i_limit=0.15f,
+//                .out_limit=1.0f,
+//                .d_cutoff_freq=-1.0f,
+//                .range=M_2PI,
+//            },
+//            .trig_omg_3508 = {
+//                .k=1.0f,
+//                .p=1.0f,
+//                .i=0.0f,
+//                .d=0.0f,
+//                .i_limit=0.0f,
+//                .out_limit=1.0f,
+//                .d_cutoff_freq=-1.0f,
+//                .range=-1.0f,
+//            },
+        },
+		.filter={
+            .fric = {
+                .in = 30.0f,
+                .out = 30.0f,
+            },
+            .trig = {
+                .in = 30.0f,
+                .out = 30.0f,
+            },
+        },  
+    },		
+		.chassis_param = {
+    /* DJI3508电机*/
+    .motor_param = {
+      { 
+			.can = BSP_CAN_1, 
+			.id = 0x201, 
+			.module = MOTOR_M3508, 
+			.reverse = false,
+			.gear =  true
+			},
+      { 
+			.can = BSP_CAN_1,
+			.id = 0x202, 
+			.module = MOTOR_M3508, 
+			.reverse = false,
+			.gear =  true
+			},
+      { 
+			.can = BSP_CAN_1, 
+			.id = 0x203, 
+			.module = MOTOR_M3508, 
+			.reverse = false,
+			.gear =  true				
+			},
+      { 
+			.can = BSP_CAN_1,
+			.id = 0x204, 
+			.module = MOTOR_M3508, 
+			.reverse = false,
+			.gear =  true	
+			},
+    },
+		.type = CHASSIS_TYPE_MECANUM,
+    /* PID  */
+    .pid = {
+      /* 底盘电机 PID */
+      .motor_pid_param = {
+				.k = 0.001f,
+				.p = 1.0f,
+				.i = 0.0f,
+				.d = 0.0f,
+				.i_limit = 1.0f,
+				.out_limit = 1.0f,
+				.d_cutoff_freq = -1.0f,
+				.range = -1.0f,
+      },
+
+      /* 跟随 */
+      .follow_pid_param = {
+					.k = 0.5f,
+					.p = 1.0f,
+					.i = 0.0f,
+					.d = 0.0f,
+					.i_limit = 1.0f,
+					.out_limit = 1.0f,
+					.d_cutoff_freq = -1.0f,
+					.range = M_2PI,
+      },
+    },
+
+    .low_pass_cutoff_freq = {
+      .in = 50.0f,
+      .out = 50.0f,
+    },
+
+    .reverse = {
+      .yaw = false,
+    },
+		.limit = {
+      .max_vx = 3.0f,     
+      .max_vy = 3.0f,
+      .max_wz = 2.0f,    
+      .max_current = 16000.0f 
+    },
+  },
+};
+
+/**
+ * @brief 获取机器人配置参数
+ * @return 机器人配置参数指针
+ */
+Config_RobotParam_t* Config_GetRobotParam(void) {
+    return &robot_config;
+}
+
diff --git a/User/module/config.h b/User/module/config.h
new file mode 100644
index 0000000..3bf7e76
--- /dev/null
+++ b/User/module/config.h
@@ -0,0 +1,33 @@
+/*
+ * 配置相关
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+//#include "device/dm_imu.h"
+#include "gimbal.h"
+#include "shoot.h"
+#include "module/chassis.h"
+
+typedef struct {
+    Gimbal_Params_t gimbal_param;
+    Shoot_Params_t shoot_param;
+		Chassis_Params_t chassis_param;
+} Config_RobotParam_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * @brief 获取机器人配置参数
+ * @return 机器人配置参数指针
+ */
+Config_RobotParam_t* Config_GetRobotParam(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/module/gimbal.c b/User/module/gimbal.c
new file mode 100644
index 0000000..1a43a92
--- /dev/null
+++ b/User/module/gimbal.c
@@ -0,0 +1,575 @@
+/*
+ * 云台模组
+ 模式自行选择：遥控器改变或自行初始化
+ delta获取从遥控器自行获取
+ example:
+	Gimbal_t gimbal;
+	Gimbal_IMU_t gimbal_imu;
+	Gimbal_CMD_t gimbal_cmd;
+
+	Gimbal_Init(&gimbal,&Config_GetRobotParam()->gimbal_param,GIMBAL_CTRL_FREQ);
+ 
+	while(1){
+	//这里写遥控器获取gimbal_cmd数据
+		if(osMessageQueueGet(task_runtime.msgq.gimbal.imu, &gimbal_imu, NULL, 0))
+    Gimbal_UpdateIMU(&gimbal, &gimbal_imu);
+		
+ 		Gimbal_UpdateFeedback(&gimbal);
+    Gimbal_Control(&gimbal,&gimbal_cmd);
+    Gimbal_Output(&gimbal);
+		}
+ */
+
+/* Includes ----------------------------------------------------------------- */
+#include "gimbal.h"
+#include "bsp/can.h"
+#include "bsp/time.h"
+#include "component/filter.h"
+#include "component/pid.h"
+#include "device/motor_rm.h"
+#include "device/motor_dm.h"
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* Private function  -------------------------------------------------------- */
+/**
+ * \brief 计算角度偏差
+ *
+ * \param 
+ * \param  
+ *
+ * \return 函数运行结果
+ */
+static float motor_imu_offset(float* motor, float* imu){
+
+	float motor_imu_offset = motor - imu;
+    /* 处理跨越±π的情况 */
+   if (motor_imu_offset > M_PI) motor_imu_offset -= M_2PI;
+   if (motor_imu_offset < -M_PI) motor_imu_offset += M_2PI;
+
+	return motor_imu_offset;
+}
+
+/**
+ * \brief 设置云台模式
+ *
+ * \param c 包含云台数据的结构体
+ * \param mode 要设置的模式
+ *
+ * \return 函数运行结果
+ */
+static int8_t Gimbal_SetMode(Gimbal_t *g, Gimbal_Mode_t mode) {
+  if (g == NULL)
+    return -1;
+  if (mode == g->mode)
+    return GIMBAL_OK;
+
+	PID_Reset(&g->pid.major_yaw_angle);
+  PID_Reset(&g->pid.major_yaw_omega);
+	
+  PID_Reset(&g->pid.yaw_angle);
+  PID_Reset(&g->pid.yaw_omega);
+  PID_Reset(&g->pid.pit_angle);
+  PID_Reset(&g->pid.pit_omega);
+  LowPassFilter2p_Reset(&g->filter_out.major_yaw, 0.0f);	
+	
+  LowPassFilter2p_Reset(&g->filter_out.yaw, 0.0f);
+  LowPassFilter2p_Reset(&g->filter_out.pit, 0.0f);
+
+
+  
+  AHRS_ResetEulr(&(g->setpoint.eulr)); /* 切换模式后重置设定值 */
+	
+  g->setpoint.eulr.pit = g->feedback.imu.eulr.pit;
+  g->setpoint.eulr.yaw = g->feedback.imu.eulr.yaw;
+
+
+  g->mode = mode;
+  return 0;
+}
+
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * \brief 初始化云台
+ *
+ * \param g 包含云台数据的结构体
+ * \param param 包含云台参数的结构体指针
+ * \param target_freq 任务预期的运行频率
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_Init(Gimbal_t *g,Gimbal_Params_t *param,
+                   float target_freq) {
+  if (g == NULL)
+    return -1;
+
+  g->param = param;
+  g->mode = GIMBAL_MODE_RELAX; /* 设置默认模式 */
+
+  /* 初始化云台电机控制PID和LPF */
+	PID_Init(&(g->pid.major_yaw_angle), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.major_yaw_angle));
+  PID_Init(&(g->pid.major_yaw_omega), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.major_yaw_omega));
+	
+  PID_Init(&(g->pid.yaw_angle), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.yaw_angle));
+  PID_Init(&(g->pid.yaw_omega), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.yaw_omega));
+  PID_Init(&(g->pid.pit_angle), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.pit_angle));
+  PID_Init(&(g->pid.pit_omega), KPID_MODE_CALC_D, target_freq,
+           &(g->param->pid.pit_omega));
+
+
+	
+	g->limit.yaw.max = g->param->Limit_t.zero.yaw_encoder+g->param->Limit_t.zero.travel.yaw;			 
+	g->limit.yaw.min = g->param->Limit_t.zero.yaw_encoder;
+
+  LowPassFilter2p_Init(&g->filter_out.major_yaw, target_freq,
+                       g->param->low_pass_cutoff_freq.out);	
+	
+  LowPassFilter2p_Init(&g->filter_out.yaw, target_freq,
+                       g->param->low_pass_cutoff_freq.out);
+  LowPassFilter2p_Init(&g->filter_out.pit, target_freq,
+                       g->param->low_pass_cutoff_freq.out);
+
+  BSP_CAN_Init();
+	/* 大yaw电机注册 */
+	if(g->param->motor.major_yaw==RM)
+			MOTOR_RM_Register(&(g->param->motor.major_yaw_rm_motor));	
+	
+	if(g->param->motor.major_yaw==DM){
+			MOTOR_DM_Register(&(g->param->motor.major_yaw_dm_motor));
+			MOTOR_DM_Enable(&(g->param->motor.major_yaw_dm_motor));
+	}	
+	
+	/*大疆电机注册*/
+	if(g->param->motor.yaw==RM)
+			MOTOR_RM_Register(&(g->param->motor.yaw_rm_motor));
+	if(g->param->motor.pit==RM)
+			MOTOR_RM_Register(&(g->param->motor.pit_rm_motor));
+	
+	/*达妙电机注册*/
+	if(g->param->motor.yaw==DM){
+			MOTOR_DM_Register(&(g->param->motor.yaw_dm_motor));
+			MOTOR_DM_Enable(&(g->param->motor.yaw_dm_motor));
+	}
+	
+	if(g->param->motor.pit==DM){
+			MOTOR_DM_Register(&(g->param->motor.pit_dm_motor));
+			MOTOR_DM_Enable(&(g->param->motor.pit_dm_motor));
+	}
+	
+  return 0;
+}
+static int8_t Gimbal_Direction(Gimbal_t *g){
+
+  if (g == NULL) {
+    return -1;
+  }
+	/* 欧拉角方向选择 */
+	switch(g->param->Direction.Eulr.pit){
+		case Pit:
+			g->direction.Eulr.pit=g->feedback.imu.eulr.pit;
+			break;
+		case Yaw:
+			g->direction.Eulr.pit=g->feedback.imu.eulr.yaw;
+			break;	
+		case Rol:
+			g->direction.Eulr.pit=-g->feedback.imu.eulr.rol;
+			break;	
+	}
+	
+	switch(g->param->Direction.Eulr.yaw){
+		case Pit:
+			g->direction.Eulr.yaw=g->feedback.imu.eulr.pit;
+			break;
+		case Yaw:
+			g->direction.Eulr.yaw=g->feedback.imu.eulr.yaw;
+			break;	
+		case Rol:
+			g->direction.Eulr.yaw=g->feedback.imu.eulr.rol;
+			break;	
+	}	
+	/* 角速度方向选择 */
+	switch(g->param->Direction.Gyro.pit){
+		case Gyro_x:
+			g->direction.Gyro.pit=g->feedback.imu.gyro.x;
+			break;
+		case Gyro_y:
+			g->direction.Gyro.pit=g->feedback.imu.gyro.y;
+			break;	
+		case Gyro_z:
+			g->direction.Gyro.pit=g->feedback.imu.gyro.z;
+			break;	
+	}
+	
+	switch(g->param->Direction.Gyro.yaw){
+		case Gyro_x:
+			g->direction.Gyro.yaw=g->feedback.imu.gyro.x;
+			break;
+		case Gyro_y:
+			g->direction.Gyro.yaw=g->feedback.imu.gyro.y;
+			break;	
+		case Gyro_z:
+			g->direction.Gyro.yaw=g->feedback.imu.gyro.z;
+			break;	
+	}
+			g->direction.Quaternion_t.q0=g->feedback.imu.quat.q0;
+			g->direction.Quaternion_t.q1=g->feedback.imu.quat.q1;	
+			g->direction.Quaternion_t.q2=g->feedback.imu.quat.q2;
+			g->direction.Quaternion_t.q3=g->feedback.imu.quat.q3;		
+	
+    return 0;
+}
+/**
+ * \brief 通过CAN设备更新云台反馈信息
+ *
+ * \param gimbal 云台
+ * \param can CAN设备
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_UpdateFeedback(Gimbal_t *gimbal) {
+  if (gimbal == NULL)
+    return -1;
+
+	
+		  /* 更新大yaw电机反馈数据（RM和DM） */	
+	if(gimbal->param->motor.major_yaw==RM){
+		MOTOR_RM_Update(&(gimbal->param->motor.major_yaw_rm_motor));
+		MOTOR_RM_t *rm_motor_yaw = MOTOR_RM_GetMotor(&(gimbal->param->motor.major_yaw_rm_motor));
+		if(rm_motor_yaw != NULL)
+		 gimbal->feedback.motor.major_yaw = rm_motor_yaw->feedback;
+	}	
+	
+	if(gimbal->param->motor.major_yaw==DM){
+		MOTOR_DM_Update(&(gimbal->param->motor.major_yaw_dm_motor));
+		MOTOR_DM_t *dm_motor = MOTOR_DM_GetMotor(&(gimbal->param->motor.major_yaw_dm_motor));
+			if (dm_motor != NULL) {
+				gimbal->feedback.motor.major_yaw = dm_motor->motor.feedback;
+		}
+	}	
+	
+  /* 更新RM电机反馈数据 */
+	if(gimbal->param->motor.yaw==RM){
+		MOTOR_RM_Update(&(gimbal->param->motor.yaw_rm_motor));
+		MOTOR_RM_t *rm_motor_yaw = MOTOR_RM_GetMotor(&(gimbal->param->motor.yaw_rm_motor));
+		if(rm_motor_yaw != NULL)
+		 gimbal->feedback.motor.yaw = rm_motor_yaw->feedback;
+	}
+	
+	
+	if(gimbal->param->motor.pit==RM){
+	MOTOR_RM_Update(&(gimbal->param->motor.pit_rm_motor));
+	MOTOR_RM_t *rm_motor_pit = MOTOR_RM_GetMotor(&(gimbal->param->motor.pit_rm_motor));
+	if (rm_motor_pit != NULL)
+		gimbal->feedback.motor.pit = rm_motor_pit->feedback;
+	}
+	
+	  /* 更新DM电机反馈数据 */
+	if(gimbal->param->motor.yaw==DM){
+		MOTOR_DM_Update(&(gimbal->param->motor.yaw_dm_motor));
+		MOTOR_DM_t *dm_motor = MOTOR_DM_GetMotor(&(gimbal->param->motor.yaw_dm_motor));
+			if (dm_motor != NULL) {
+				gimbal->feedback.motor.yaw = dm_motor->motor.feedback;
+		}
+	}
+	if(gimbal->param->motor.pit==DM){
+		MOTOR_DM_Update(&(gimbal->param->motor.pit_dm_motor));
+		MOTOR_DM_t *dm_motor = MOTOR_DM_GetMotor(&(gimbal->param->motor.pit_dm_motor));
+			if (dm_motor != NULL) {
+				gimbal->feedback.motor.pit = dm_motor->motor.feedback;
+		}
+	}
+
+  return 0;
+}
+
+int8_t Gimbal_UpdateIMU(Gimbal_t *gimbal, const Gimbal_IMU_t *imu){
+
+  if (gimbal == NULL) {
+    return -1;
+  }
+  gimbal->feedback.imu.gyro = imu->gyro;
+  gimbal->feedback.imu.eulr = imu->eulr;
+  gimbal->feedback.imu.accl = imu->accl;
+  gimbal->feedback.imu.quat = imu->quat;	
+	Gimbal_Direction(gimbal);
+}
+/**
+ * \brief 运行大yaw控制逻辑
+ *
+ * \param g 包含云台数据的结构体
+ * \param 
+ *
+ * \return 函数运行结果
+ */
+ int8_t major_yaw_Control(Gimbal_t *g){
+
+	 /*处理大yaw控制命令，软件限位 - 使用电机绝对角度*/
+ /*获得小YAW的中点位置，如果小YAW大于中点的一定范围，大YAW开始运动，
+ 跟随小YAW向相同方向运动，将遥控数据进行分配*/
+
+ /*小YAW中点*/
+ float small_yaw_center_offset = g->param->Limit_t.zero.yaw_encoder  + 
+																 g->param->Limit_t.zero.travel.yaw* 0.5f;
+	g->setpoint.major_yaw=small_yaw_center_offset;
+ 
+// /* 小yaw是否开启 */
+//	float err = g->feedback.motor.yaw.rotor_abs_angle - small_yaw_center_offset; 
+
+//	float threshold = (g->param->Limit_t.zero.travel.yaw * 0.35f);
+//    /* 超出阈值范围，让大yaw跟随 */
+//	if (fabsf(err) > threshold) {
+//		/* 此时让大yaw动起来，跟随err的符号 */
+////		g->setpoint.major_yaw = g->feedback.motor.major_yaw.rotor_abs_angle - err;
+//    g->setpoint.major_yaw = small_yaw_center_offset;;
+//	} else {
+//    /* 阈值以内，大yaw不动*/
+//    g->setpoint.major_yaw = g->feedback.motor.major_yaw.rotor_abs_angle; //当前值，不动
+//	}
+	return 0;
+}
+
+
+int8_t Gimbal_Control_mode(Gimbal_t *g,Gimbal_CMD_t *g_cmd){
+	  if (g == NULL || g_cmd == NULL) {
+    return -1;
+  }
+		switch(g_cmd->ctrl_mode){
+			case GIMBAL_MODE_REMOTE:
+				g->setpoint.eulr.yaw+=(g_cmd->delta_yaw*g->dt);	
+				g->setpoint.eulr.pit+=(g_cmd->delta_pit*g->dt);
+				break;
+			case GIMBAL_MODE_AI:				
+			g->setpoint.eulr.yaw=g_cmd->set_yaw;	
+			g->setpoint.eulr.pit=g_cmd->set_pit;			
+				break;
+			case GIMBAL_MODE_NUC:
+				/* 可能用不上，还在想 */
+				break;			
+		}
+		return GIMBAL_OK;
+};
+
+
+/**
+ * \brief 运行云台控制逻辑
+ *
+ * \param g 包含云台数据的结构体
+ * \param g_cmd 云台控制指令
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_Control(Gimbal_t *g, Gimbal_CMD_t *g_cmd) {
+  if (g == NULL || g_cmd == NULL) {
+    return -1;
+  }
+
+  g->dt = (BSP_TIME_Get_us() - g->lask_wakeup) / 1000000.0f;
+  g->lask_wakeup = BSP_TIME_Get_us();
+  Gimbal_SetMode(g, g_cmd->mode);
+	/* 双yaw的大yaw,setpoint从这设立 */
+	major_yaw_Control(g);
+  /* 欧拉角控制相关逻辑 */
+  float yaw_omega_set_point, pit_omega_set_point,major_yaw_omega_set_point;
+	
+	float delta_yaw = g_cmd->delta_yaw*g->dt;
+	float delta_pit = g_cmd->delta_pit*g->dt;
+	
+		float yaw_motor_imu_offset=motor_imu_offset(&g->feedback.motor.yaw.rotor_abs_angle,
+			&g->feedback.imu.eulr.yaw);
+
+    float delta_max = CircleError(g->limit.yaw.max,
+        (g->setpoint.eulr.yaw + yaw_motor_imu_offset + delta_yaw), M_2PI);
+    float delta_min = CircleError(g->limit.yaw.min,
+        (g->setpoint.eulr.yaw + yaw_motor_imu_offset + delta_yaw), M_2PI);		
+			
+  switch (g->mode) {
+  case GIMBAL_MODE_RELAX:/*放松模式*/
+ 
+    g->out.major_yaw = 0.0f;
+		g->out.yaw = 0.0f;
+    g->out.pit = 0.0f;
+    break;
+  case GIMBAL_MODE_ABSOLUTE:/*绝对模式*/
+		/* 手动和自瞄 */
+		Gimbal_Control_mode(g, g_cmd);
+		if (g->param->motor.limit_yaw==true)
+		Clip(&(g->setpoint.eulr.yaw),delta_min,delta_max);		
+		else{
+		/*限制在-3.14~3.14*/
+		if (g->setpoint.eulr.yaw > M_PI) g->setpoint.eulr.yaw -= M_2PI;
+		if (g->setpoint.eulr.yaw < -M_PI) g->setpoint.eulr.yaw += M_2PI;			
+		}
+
+
+  /* 处理pitch控制命令，软件限位 - 使用电机绝对角度 */
+
+	  /* 限制pit控制命令 */	
+		if (g->param->motor.limit_pit == true)
+		Clip(&(g->setpoint.eulr.pit),g->param->Limit_t.pit_min,g->param->Limit_t.pit_max);	
+ /*4310大YAW控制
+    这里是单环控制的，有需要加双环
+    */
+		
+		
+    major_yaw_omega_set_point =PID_Calc(&g->pid.major_yaw_angle,
+																				 g->setpoint.major_yaw,
+																				 g->feedback.motor.yaw.rotor_abs_angle,
+																				 g->feedback.motor.yaw.rotor_speed,g->dt);
+//	     g->out.yaw_4310 = PID_Calc(&g->pid.yaw_4310_omega,yaw_omega_set_point,
+//                               g->feedback.imu.gyro.z,0.0f,g->dt);
+    g->out.major_yaw = major_yaw_omega_set_point;  // 直接输出速度环目标值作为电机输出		
+		
+    yaw_omega_set_point = PID_Calc(&(g->pid.yaw_angle), g->setpoint.eulr.yaw,
+                                   g->direction.Eulr.yaw, 0.0f, g->dt);
+    g->out.yaw = PID_Calc(&(g->pid.yaw_omega), yaw_omega_set_point,
+                          g->direction.Gyro.yaw, 0.f, g->dt);
+
+		pit_omega_set_point = PID_Calc(&(g->pid.pit_angle), g->setpoint.eulr.pit,
+                                   g->direction.Eulr.pit, 0.0f, g->dt);
+		g->out.pit = PID_Calc(&(g->pid.pit_omega), pit_omega_set_point,
+													g->feedback.imu.gyro.y, 0.f, g->dt);
+
+		/*前馈添加*/
+		if(g->param->feedforward.imu.yaw==true)
+		g->out.yaw+=g->param->feedforward.imu.K_yaw*(yaw_omega_set_point - g->feedback.imu.gyro.z);
+		if(g->param->feedforward.imu.pit==true)
+		g->out.pit+=g->param->feedforward.imu.K_pit*(pit_omega_set_point - g->feedback.imu.gyro.x);
+		
+    break;
+	case GIMBAL_MODE_RELATIVE:
+		/*计算零点*/
+		CircleAdd(&(g->relative_angle.yaw), delta_yaw, M_2PI);
+		
+		/*  -PI~PI 归一化 */
+		if(g->relative_angle.yaw > M_PI) g->relative_angle.yaw -= M_2PI;
+		if(g->relative_angle.yaw < -M_PI) g->relative_angle.yaw += M_2PI;
+
+		/*  计算底盘当前在世界坐标系的方向 (坐标系转换) */
+		/* 底盘Yaw(世界) = 云台Yaw(世界) - 云台电机Yaw(机械) */
+		
+		float current_chassis_yaw_world=-motor_imu_offset(&g->feedback.motor.yaw.rotor_abs_angle,&g->feedback.imu.eulr.yaw);
+		/* 归一化底盘角度 */
+		if(current_chassis_yaw_world > M_PI) current_chassis_yaw_world -= M_2PI;
+		if(current_chassis_yaw_world < -M_PI) current_chassis_yaw_world += M_2PI;
+
+
+		/*  最终的欧拉角控制目标 (Setpoint) */
+		/* 目标(世界) = 底盘(世界) + 期望相对角(相对) */
+		g->setpoint.eulr.yaw = current_chassis_yaw_world + g->relative_angle.yaw;
+		
+		/* 再次归一化 Setpoint，防止数值溢出 */
+		if(g->setpoint.eulr.yaw >  M_PI) g->setpoint.eulr.yaw -= M_2PI;
+		if(g->setpoint.eulr.yaw < -M_PI) g->setpoint.eulr.yaw += M_2PI;
+
+		/*  Pitch 轴处理 ( Pitch 保持绝对水平，不随底盘颠簸) */
+		g->setpoint.eulr.pit += delta_pit; 
+		/* Pitch 限位 */
+		if (g->param->motor.limit_pit == true)
+		Clip(&(g->setpoint.eulr.pit), g->param->Limit_t.pit_min, g->param->Limit_t.pit_max);
+
+ /*4310大YAW控制
+    这里是单环控制的，有需要加双环
+    */
+    major_yaw_omega_set_point =PID_Calc(&g->pid.major_yaw_angle,
+																				 g->setpoint.major_yaw,
+																				 g->feedback.motor.major_yaw.rotor_abs_angle,
+																				 g->feedback.motor.major_yaw.rotor_speed,g->dt);
+//	     g->out.yaw_4310 = PID_Calc(&g->pid.yaw_4310_omega,yaw_omega_set_point,
+//                               g->feedback.imu.gyro.z,0.0f,g->dt);
+    g->out.major_yaw = major_yaw_omega_set_point;  // 直接输出速度环目标值作为电机输出				
+		
+    yaw_omega_set_point = PID_Calc(&(g->pid.yaw_angle), g->setpoint.eulr.yaw,
+                                   g->direction.Eulr.yaw, 0.0f, g->dt);
+    g->out.yaw = PID_Calc(&(g->pid.yaw_omega), yaw_omega_set_point,
+                          g->direction.Gyro.yaw, 0.f, g->dt);
+
+		pit_omega_set_point = PID_Calc(&(g->pid.pit_angle), g->setpoint.eulr.pit,
+                                   g->direction.Eulr.pit, 0.0f, g->dt);
+		g->out.pit = PID_Calc(&(g->pid.pit_omega), pit_omega_set_point,
+													g->direction.Gyro.pit, 0.f, g->dt);
+		/*前馈添加*/
+		if(g->param->feedforward.imu.yaw==true)
+		g->out.yaw+=g->param->feedforward.imu.K_yaw*(yaw_omega_set_point - g->feedback.imu.gyro.z);
+		if(g->param->feedforward.imu.pit==true)
+		g->out.pit+=g->param->feedforward.imu.K_pit*(pit_omega_set_point - g->feedback.imu.gyro.x);
+		break;
+  }
+	    /* 输出滤波 */
+    g->out.major_yaw = LowPassFilter2p_Apply(&g->filter_out.major_yaw, g->out.major_yaw);	
+    g->out.yaw = LowPassFilter2p_Apply(&g->filter_out.yaw, g->out.yaw);
+    g->out.pit = LowPassFilter2p_Apply(&g->filter_out.pit, g->out.pit);
+	 return 0;
+}
+
+
+
+
+
+  /**
+   * \brief 云台输出
+   *
+   * \param s 包含云台数据的结构体
+   * \param out CAN设备云台输出结构体
+   */
+void Gimbal_Output(Gimbal_t *g){
+	
+	/*大yaw电机输出*/
+	if(g->param->motor.major_yaw==RM){
+			MOTOR_RM_Ctrl(&g->param->motor.major_yaw_rm_motor);
+			MOTOR_RM_SetOutput(&g->param->motor.major_yaw_rm_motor, g->out.major_yaw);
+	}	
+
+	if(g->param->motor.major_yaw==DM){
+		
+			g->out.major_yaw_dm.angle=g->param->dm_Params_t.major_yaw_dm.angle;
+			g->out.major_yaw_dm.kd=g->param->dm_Params_t.major_yaw_dm.kd;
+			g->out.major_yaw_dm.kp=g->param->dm_Params_t.major_yaw_dm.kp;
+			g->out.major_yaw_dm.velocity=g->param->dm_Params_t.major_yaw_dm.velocity;
+		
+			g->out.major_yaw_dm.torque= g->out.major_yaw * g->param->dm_Params_t.major_yaw_dm_Reduction_ratio; // 乘以减速比
+		
+			 MOTOR_DM_MITCtrl(&g->param->motor.major_yaw_dm_motor,&(g->out.major_yaw_dm));
+	}	
+	
+	/*大疆电机输出*/
+	if(g->param->motor.yaw==RM){
+			MOTOR_RM_Ctrl(&g->param->motor.yaw_rm_motor);
+			MOTOR_RM_SetOutput(&g->param->motor.yaw_rm_motor, g->out.yaw);
+	}
+	if(g->param->motor.pit==RM){
+			MOTOR_RM_Ctrl(&g->param->motor.pit_rm_motor);
+			MOTOR_RM_SetOutput(&g->param->motor.pit_rm_motor, g->out.pit);//
+	}
+	
+	/*达妙电机输出*/
+	if(g->param->motor.pit==DM){
+		
+			g->out.pit_dm.angle=g->param->dm_Params_t.pit_dm.angle;
+			g->out.pit_dm.kd=g->param->dm_Params_t.pit_dm.kd;
+			g->out.pit_dm.kp=g->param->dm_Params_t.pit_dm.kp;
+			g->out.pit_dm.velocity=g->param->dm_Params_t.pit_dm.velocity;
+		
+			g->out.pit_dm.torque= g->out.pit * g->param->dm_Params_t.pit_dm_Reduction_ratio; // 乘以减速比
+		
+			 MOTOR_DM_MITCtrl(&g->param->motor.pit_dm_motor,&(g->out.pit_dm));
+	}
+	if(g->param->motor.yaw==DM){
+			g->out.yaw_dm.angle=g->param->dm_Params_t.yaw_dm.angle;
+			g->out.yaw_dm.kd=g->param->dm_Params_t.yaw_dm.kd;
+			g->out.yaw_dm.kp=g->param->dm_Params_t.yaw_dm.kp;
+			g->out.yaw_dm.velocity=g->param->dm_Params_t.yaw_dm.velocity;
+
+			g->out.yaw_dm.torque= g->out.yaw * g->param->dm_Params_t.yaw_dm_Reduction_ratio; // 乘以减速比
+		
+			 MOTOR_DM_MITCtrl(&g->param->motor.yaw_dm_motor,&(g->out.yaw_dm));	
+		}
+	
+}
+
diff --git a/User/module/gimbal.h b/User/module/gimbal.h
new file mode 100644
index 0000000..b373826
--- /dev/null
+++ b/User/module/gimbal.h
@@ -0,0 +1,374 @@
+/*
+ * 云台模组
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "component/ahrs.h"
+#include "component/filter.h"
+#include "component/pid.h"
+#include "device/motor.h"
+#include "device/motor_dm.h"
+#include "device/motor_rm.h"
+/* Exported constants ------------------------------------------------------- */
+#define GIMBAL_OK (0)        /* 运行正常 */
+#define GIMBAL_ERR (-1)      /* 运行时发现了其他错误 */
+#define GIMBAL_ERR_NULL (-2) /* 运行时发现NULL指针 */
+#define GIMBAL_ERR_MODE (-3) /* 运行时配置了错误的CMD_GimbalMode_t */
+
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+
+typedef enum {
+  GIMBAL_MODE_RELAX,    /* 放松模式，电机不输出。一般情况云台初始化之后的模式 */
+  GIMBAL_MODE_ABSOLUTE, /* 绝对坐标系控制，控制在空间内的绝对姿态 */
+  GIMBAL_MODE_RELATIVE, /* 相对坐标系控制，控制相对于底盘的姿态 */
+} Gimbal_Mode_t;
+
+typedef enum {
+  GIMBAL_MODE_REMOTE,    /* 遥控器模式 */
+  GIMBAL_MODE_NUC, 			 /* 操作手模式 */	
+  GIMBAL_MODE_AI, 			 /* 自瞄模式 */
+	
+} Gimbal_Control_Mode_t;
+
+typedef enum {
+  DM,    /*大妙*/
+  RM, 		/*大疆 */
+} Gimbal_MOTOR_t;
+
+typedef enum {
+  Gyro_x,   
+  Gyro_y, 		
+	Gyro_z,
+} Gimbal_Gyro_t;
+
+typedef enum {
+  Pit,   
+  Yaw, 		
+	Rol,
+} Gimbal_Eulr_t;
+
+typedef enum {
+  Accl_x,   
+  Accl_y, 		
+	Accl_z,
+} Gimbal_Accl_t;
+
+typedef enum {
+  Q0,   
+  Q1, 		
+	Q2,
+	Q3,
+} Gimbal_Quat_t;
+
+typedef struct {
+  Gimbal_Mode_t mode; 
+  Gimbal_Control_Mode_t ctrl_mode; 	
+  float delta_yaw;
+  float delta_pit;
+  float set_yaw;
+  float set_pit;	
+} Gimbal_CMD_t;
+
+/* 软件限位 */
+typedef struct {
+  float max;
+  float min;
+} Gimbal_Limit_t;
+
+typedef	struct{
+	struct{
+    float yaw; /*  零点行程 */
+    float pit;
+  }travel;
+  float pit;		/*零点*/
+  float yaw;
+} Gimbal_zero_t;	
+
+
+typedef struct {
+		struct{
+		float pit;
+		float yaw;
+		float rol;
+		}Gyro;
+		
+		struct{
+		float pit;
+		float yaw;
+		float rol;
+		}Eulr;
+		
+		struct {
+		float q0;
+		float q1;
+		float q2;
+		float q3;
+		} Quaternion_t;
+		
+  } Gimbal_Direction_t;
+
+typedef struct {
+
+	bool limit_yaw;/*是否开启限位*/
+	bool limit_pit;
+	
+	Gimbal_MOTOR_t major_yaw;	
+
+	Gimbal_MOTOR_t pit;
+	Gimbal_MOTOR_t yaw;
+	
+	MOTOR_DM_Param_t major_yaw_dm_motor; /* 大yaw轴电机参数 */
+  MOTOR_RM_Param_t major_yaw_rm_motor; /* 大yaw轴电机参数 */	
+	
+  MOTOR_DM_Param_t pit_dm_motor; /* pitch轴电机参数 */
+  MOTOR_DM_Param_t yaw_dm_motor; /* yaw轴电机参数 */
+	
+	MOTOR_RM_Param_t pit_rm_motor; /* pitch轴电机参数 */
+  MOTOR_RM_Param_t yaw_rm_motor; /* yaw轴电机参数 */
+	
+}Gimbal_MOTOR_t_Param_t;
+
+/* 云台参数的结构体，包含所有初始化用的参数，通常是const，存好几组。*/
+typedef struct {
+	struct{
+
+	float k;
+	float p;	
+	}acclctrl;
+	
+	
+	Gimbal_MOTOR_t_Param_t motor;
+  struct {
+		KPID_Params_t major_yaw_omega; /* yaw轴角速度环PID参数 */
+    KPID_Params_t major_yaw_angle; /* yaw轴角位置环PID参数 */
+		
+    KPID_Params_t yaw_omega; /* yaw轴角速度环PID参数 */
+    KPID_Params_t yaw_angle; /* yaw轴角位置环PID参数 */
+    KPID_Params_t pit_omega; /* pitch轴角速度环PID参数 */
+    KPID_Params_t pit_angle; /* pitch轴角位置环PID参数 */
+		
+  } pid;
+
+  struct {
+		struct{
+		Gimbal_Gyro_t pit;
+		Gimbal_Gyro_t yaw;
+		Gimbal_Gyro_t rol;
+		}Gyro;
+		struct{
+		Gimbal_Eulr_t pit;
+		Gimbal_Eulr_t yaw;
+		Gimbal_Eulr_t rol;
+		}Eulr;
+		struct{
+		Gimbal_Accl_t pit;
+		Gimbal_Accl_t yaw;
+		Gimbal_Accl_t rol;
+		}Accl;
+  } Direction;
+
+	
+	  /* 前馈系数 */
+  struct {
+		struct{
+		bool yaw;
+		bool pit;
+		float K_yaw;  
+    float K_pit;			
+		}imu;
+		
+  }feedforward;
+
+
+
+
+	
+  /* 低通滤波器截止频率 */
+  struct {
+    float out;  /* 电机输出 */
+    float gyro; /* 陀螺仪数据 */
+  } low_pass_cutoff_freq;
+
+
+	struct {
+  float pit_max;		/*pit的限位*/
+  float pit_min;
+	float yaw_max;		/*yaw的限位*/
+  float yaw_min;		
+		 struct {
+			float pit_encoder;		/*零点*/
+			float yaw_encoder;
+				struct{	
+						float yaw;
+						float pit;
+			}travel;
+  }zero;
+		
+		
+	}Limit_t;
+	
+	struct {
+
+	/*大yaw的参数*/
+	MOTOR_MIT_Output_t major_yaw_dm;			
+	MOTOR_MIT_Output_t yaw_dm;		/*达妙的参数*/
+	MOTOR_MIT_Output_t pit_dm;	
+	float major_yaw_dm_Reduction_ratio;						
+	float yaw_dm_Reduction_ratio;
+	float pit_dm_Reduction_ratio;	
+	}dm_Params_t;
+} Gimbal_Params_t;
+
+typedef struct {
+  AHRS_Gyro_t gyro;
+  AHRS_Eulr_t eulr;
+  AHRS_Quaternion_t quat;		
+	AHRS_Accl_t accl;	
+} Gimbal_IMU_t;
+/* 云台反馈数据的结构体，包含反馈控制用的反馈数据 */
+typedef struct {
+  Gimbal_IMU_t imu;
+  struct {
+    MOTOR_Feedback_t major_yaw; /* 大yaw轴电机反馈 */
+    MOTOR_Feedback_t yaw; /* yaw轴电机反馈 */
+    MOTOR_Feedback_t pit; /* pitch轴电机反馈 */
+  } motor;
+} Gimbal_Feedback_t;
+
+/* 云台输出数据的结构体*/
+typedef struct {
+
+
+	float major_yaw;	
+  float yaw; /* yaw轴电机输出 */
+  float pit; /* pitch轴电机输出 */
+
+	MOTOR_MIT_Output_t major_yaw_dm;			
+	MOTOR_MIT_Output_t yaw_dm;		/*达妙的参数*/
+	MOTOR_MIT_Output_t pit_dm;	
+
+} Gimbal_Output_t;
+/*
+ * 运行的主结构体，所有这个文件里的函数都在操作这个结构体。
+ * 包含了初始化参数，中间变量，输出变量。
+ */
+typedef struct {
+  uint64_t lask_wakeup;
+  float dt;
+
+  Gimbal_Params_t *param; /* 云台的参数，用Gimbal_Init设定 */
+	
+  /* 模块通用 */
+	Gimbal_Control_Mode_t ctrl_mode;
+  Gimbal_Mode_t mode; /* 云台模式 */
+	Gimbal_MOTOR_t MOTOR;
+	Gimbal_zero_t zero;
+	Gimbal_Direction_t direction;
+  /* PID计算的目标值 */
+  struct {
+		float major_yaw;
+    AHRS_Eulr_t eulr; /* 表示云台姿态的欧拉角 */
+		AHRS_Eulr_t ecd;
+  } setpoint;
+
+  struct {	
+    KPID_t major_yaw_angle; /* 大yaw轴角位置环PID */
+    KPID_t major_yaw_omega; /* 大yaw轴角速度环PID */		
+		
+    KPID_t yaw_angle; /* yaw轴角位置环PID */
+    KPID_t yaw_omega; /* yaw轴角速度环PID */
+    KPID_t pit_angle; /* pitch轴角位置环PID */
+    KPID_t pit_omega; /* pitch轴角速度环PID */	
+  } pid;
+
+  struct {
+		Gimbal_Limit_t yaw;
+    Gimbal_Limit_t pit;
+  } limit;
+
+  struct {		
+		float major_yaw;
+		float yaw;
+		float pit;
+  } relative_angle;
+	
+  struct {
+    LowPassFilter2p_t major_yaw;		
+		
+    LowPassFilter2p_t yaw;
+    LowPassFilter2p_t pit;
+  } filter_out;
+	struct{
+	float p_err;
+	float v_err;
+		
+
+		float v;
+		float p;
+		float accl;
+	}ai;
+	
+	
+	
+	
+	
+  Gimbal_Output_t out;        /* 云台输出 */
+  Gimbal_Feedback_t feedback; /* 反馈 */
+
+} Gimbal_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * \brief 初始化云台
+ *
+ * \param g 包含云台数据的结构体
+ * \param param 包含云台参数的结构体指针
+ * \param target_freq 任务预期的运行频率
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_Init(Gimbal_t *g,Gimbal_Params_t *param,
+                   float target_freq);
+
+/**
+ * \brief 通过CAN设备更新云台反馈信息
+ *
+ * \param gimbal 云台
+ * \param can CAN设备
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_UpdateFeedback(Gimbal_t *gimbal);
+
+int8_t Gimbal_UpdateIMU(Gimbal_t *gimbal, const Gimbal_IMU_t *imu);
+/**
+ * \brief 运行云台控制逻辑
+ *
+ * \param g 包含云台数据的结构体
+ * \param fb 云台反馈信息
+ * \param g_cmd 云台控制指令
+ * \param dt_sec 两次调用的时间间隔
+ *
+ * \return 函数运行结果
+ */
+int8_t Gimbal_Control(Gimbal_t *g, Gimbal_CMD_t *g_cmd);
+
+/**
+ * \brief 云台输出
+ *
+ * \param s 包含云台数据的结构体
+ * \param out CAN设备云台输出结构体
+ */
+void Gimbal_Output(Gimbal_t *g);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/module/remote_cmd.c b/User/module/remote_cmd.c
new file mode 100644
index 0000000..17aa01a
--- /dev/null
+++ b/User/module/remote_cmd.c
@@ -0,0 +1,58 @@
+#include "remote_cmd.h"
+#include 
+#include "bsp\uart.h"
+#include "component\crc16.h"
+#include "component\crc8.h"
+#include "component\user_math.h"
+#include "gimbal.h"
+#include "device\dr16.h"
+#include "shoot.h"
+
+int8_t Gimbal_Cmd( Gimbal_CMD_t *g_cmd, DR16_t *dr16) 
+{
+
+    switch (dr16->data.sw_l)
+    {
+    case DR16_SW_DOWN:
+        g_cmd->mode=  GIMBAL_MODE_RELAX;   /* 放松模式 */  
+        break;
+      case DR16_SW_MID:
+        g_cmd->ctrl_mode=  GIMBAL_MODE_REMOTE;   /* 遥控器模式 */
+        g_cmd->mode=  GIMBAL_MODE_ABSOLUTE;    
+        g_cmd->delta_yaw=0.8*(dr16->raw_data.ch_r_x-1024)/660; /* 云台Yaw速度设定 */
+        g_cmd->delta_pit=0.6*(dr16->raw_data.ch_r_y-16)/640; /* 云台Pitch速度设定 */
+        break;  
+     case DR16_SW_UP:
+       g_cmd->ctrl_mode=  GIMBAL_MODE_AI;   /* 遥控器模式 */
+        g_cmd->mode=  GIMBAL_MODE_ABSOLUTE;   
+        break;
+    }
+
+}
+
+int8_t Shoot_Cmd(Shoot_CMD_t *s_cmd,DR16_t *dr16) 
+{
+
+    switch (dr16->data.sw_r)
+    {
+    case DR16_SW_DOWN:
+				s_cmd->firecmd=false;
+				s_cmd->ready=false;
+        break;
+      case DR16_SW_MID:
+        s_cmd->firecmd=false;
+				s_cmd->ready=true;
+        break;  
+     case DR16_SW_UP:
+        s_cmd->firecmd=true;
+        s_cmd->ready=true;
+        break;
+    }
+
+}
+
+
+
+
+
+
diff --git a/User/module/remote_cmd.h b/User/module/remote_cmd.h
new file mode 100644
index 0000000..c2e3d21
--- /dev/null
+++ b/User/module/remote_cmd.h
@@ -0,0 +1,23 @@
+/*
+ * cmd模组
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ----------------------------------------------------------------- */
+#include "component\user_math.h"
+#include "gimbal.h"
+#include "shoot.h"
+#include "dr16.h"
+int8_t Gimbal_Cmd(Gimbal_CMD_t *g_cmd,DR16_t *dr16) ;
+int8_t Shoot_Cmd(Shoot_CMD_t *s_cmd,DR16_t *dr16) ;	
+	
+	
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/User/module/shoot.c b/User/module/shoot.c
new file mode 100644
index 0000000..9132eda
--- /dev/null
+++ b/User/module/shoot.c
@@ -0,0 +1,657 @@
+/*
+ * far♂蛇模块
+ */
+ 
+/********************************* 使用示例 **********************************/
+/*1.配置config参数以及Config_ShootInit函数参数*/
+/*2.
+COMP_AT9S_CMD_t shoot_ctrl_cmd_rc;
+Shoot_t shoot;
+Shoot_CMD_t shoot_cmd;
+
+void Task(void *argument) {
+
+	Config_ShootInit();
+	Shoot_Init(&shoot,&Config_GetRobotParam()->shoot_param,SHOOT_CTRL_FREQ);
+	Shoot_SetMode(&shoot,SHOOT_MODE_SINGLE);					关于模式选择：初始化一个模式
+	
+  while (1) {
+  
+	  shoot_cmd.online	=shoot_ctrl_cmd_rc.online;
+	  shoot_cmd.ready	=shoot_ctrl_cmd_rc.shoot.ready;
+	  shoot_cmd.firecmd	=shoot_ctrl_cmd_rc.shoot.firecmd;
+	  
+	  shoot.mode		=shoot_ctrl_cmd_rc.mode;			    关于模式选择：或者用遥控器随时切换模式，二选一
+	  
+	  Chassis_UpdateFeedback(&shoot);
+	  Shoot_Control(&shoot,&shoot_cmd);
+  }
+}
+*******************************************************************************/
+
+
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include 
+#include "shoot.h"
+#include "bsp/mm.h"
+#include "bsp/time.h"
+#include "component/filter.h"
+#include "component/user_math.h"
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+#define MAX_FRIC_RPM 7000.0f
+#define MAX_TRIG_RPM 4000.0f//这里可能也会影响最高发射频率，待测试
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+static bool last_firecmd;
+
+/* Private function  -------------------------------------------------------- */
+
+/**
+ * \brief 设置射击模式
+ *
+ * \param s 包含射击数据的结构体
+ * \param mode 要设置的模式
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_SetMode(Shoot_t *s, Shoot_Mode_t mode)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    s->mode=mode;
+    return SHOOT_OK;
+}
+
+/**
+ * \brief 重置PID积分
+ *
+ * \param s 包含射击数据的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_ResetIntegral(Shoot_t *s)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = s->param->basic.fric_num;
+    for(int i=0;ipid.fric_follow[i]);
+        PID_ResetIntegral(&s->pid.fric_err[i]);
+    }
+    PID_ResetIntegral(&s->pid.trig);
+    PID_ResetIntegral(&s->pid.trig_omg);
+    return SHOOT_OK;
+}
+
+/**
+ * \brief 重置计算模块
+ *
+ * \param s 包含射击数据的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_ResetCalu(Shoot_t *s)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = s->param->basic.fric_num;
+    for(int i=0;ipid.fric_follow[i]);
+        PID_Reset(&s->pid.fric_err[i]);
+        LowPassFilter2p_Reset(&s->filter.fric.in[i], 0.0f);
+        LowPassFilter2p_Reset(&s->filter.fric.out[i], 0.0f);
+    }
+    PID_Reset(&s->pid.trig);
+    PID_Reset(&s->pid.trig_omg);
+    LowPassFilter2p_Reset(&s->filter.trig.in, 0.0f);
+    LowPassFilter2p_Reset(&s->filter.trig.out, 0.0f);
+    return SHOOT_OK;
+}
+
+/**
+ * \brief 重置输出
+ *
+ * \param s 包含射击数据的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_ResetOutput(Shoot_t *s)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = s->param->basic.fric_num;
+    for(int i=0;ioutput.out_follow[i]=0.0f;
+        s->output.out_err[i]=0.0f;
+        s->output.out_fric[i]=0.0f;
+        s->output.lpfout_fric[i]=0.0f;
+    }
+	s->output.outagl_trig=0.0f;
+	s->output.outomg_trig=0.0f;
+    s->output.outlpf_trig=0.0f;
+    return SHOOT_OK;
+}
+//float last_angle=0.0f;
+//float speed=0.0f;
+//int8_t Shoot_CalufeedbackRPM(Shoot_t *s)
+//{
+//    if (s == NULL) {
+//        return SHOOT_ERR_NULL; // 参数错误
+//    }
+////    static 
+//    float err;
+//    err=CircleError(s->feedback.fric[0].rotor_abs_angle,last_angle,M_2PI);
+//    speed=err/s->dt/M_2PI*60.0f;
+//    last_angle=s->feedback.fric->rotor_abs_angle;
+
+
+//    return SHOOT_OK;
+//}
+
+/**
+ * \brief 根据目标弹丸速度计算摩擦轮目标转速
+ *
+ * \param s 包含射击数据的结构体
+ * \param target_speed 目标弹丸速度，单位m/s
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_CaluTargetRPM(Shoot_t *s, float target_speed)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+	switch(s->param->basic.projectileType)
+	{
+		case SHOOT_PROJECTILE_17MM:
+		s->target_variable.fric_rpm=5500.0f;
+		break;
+		case SHOOT_PROJECTILE_42MM:
+		s->target_variable.fric_rpm=4000.0f;
+		break;	
+	}
+    return SHOOT_OK;
+}
+
+/**
+ * \brief 根据发射弹丸数量及发射频率计算拨弹电机目标角度
+ *
+ * \param s 包含发射数据的结构体
+ * \param cmd 包含射击指令的结构体
+ * 
+ * \return 函数运行结果
+ */
+int8_t Shoot_CaluTargetAngle(Shoot_t *s, Shoot_CMD_t *cmd)
+{
+    if (s == NULL  || s->var_trig.num_toShoot == 0) {
+        return SHOOT_ERR_NULL; 
+    }
+    float dt = s->timer.now - s->var_trig.time_lastShoot;
+	float dpos;
+    dpos = CircleError(s->target_variable.trig_angle, s->var_trig.trig_agl, M_2PI);
+    if(dt >= 1.0f/s->param->basic.shot_freq && cmd->firecmd && dpos<=1.0f)
+    {
+        s->var_trig.time_lastShoot=s->timer.now;
+        CircleAdd(&s->target_variable.trig_angle, M_2PI/s->param->basic.num_trig_tooth, M_2PI);
+		s->var_trig.num_toShoot--;
+    }
+    return SHOOT_OK;
+}
+
+static float Shoot_CaluCoupledWeight(Shoot_t *s, uint8_t fric_index)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+
+    float Threshold;
+    switch (s->param->basic.projectileType) {
+        case SHOOT_PROJECTILE_17MM:
+            Threshold=50.0f;
+            break;
+        case SHOOT_PROJECTILE_42MM:
+            Threshold=400.0f;
+            break;
+        default:
+            return 0.0f;
+    }
+
+    float err;
+    err=fabs((s->param->basic.ratio_multilevel[fric_index]
+                *s->target_variable.fric_rpm)
+                -s->feedback.fric[fric_index].rotor_speed);
+    if (errvar_fric.coupled_control_weights=1.0f-(err*err)/(Threshold*Threshold);
+    }
+    else
+    {
+        s->var_fric.coupled_control_weights=0.0f;
+    }
+    return s->var_fric.coupled_control_weights;
+}
+
+/**
+ * \brief 更新射击模块的电机反馈信息
+ *
+ * \param s 包含射击数据的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_UpdateFeedback(Shoot_t *s)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = s->param->basic.fric_num;
+    for(int i = 0; i < fric_num; i++) {
+        /* 更新摩擦轮电机反馈 */
+        MOTOR_RM_Update(&s->param->motor.fric[i].param);
+		MOTOR_RM_t *motor_fed = MOTOR_RM_GetMotor(&s->param->motor.fric[i].param);
+		if(motor_fed!=NULL)
+		{
+			s->feedback.fric[i]=motor_fed->motor.feedback;
+		}
+        /* 滤波摩擦轮电机转速反馈 */
+        s->var_fric.fil_rpm[i] = LowPassFilter2p_Apply(&s->filter.fric.in[i], s->feedback.fric[i].rotor_speed);
+        /* 归一化摩擦轮电机转速反馈 */
+        s->var_fric.normalized_fil_rpm[i] = s->var_fric.fil_rpm[i] / MAX_FRIC_RPM;
+        if(s->var_fric.normalized_fil_rpm[i]>1.0f)s->var_fric.normalized_fil_rpm[i]=1.0f;
+        if(s->var_fric.normalized_fil_rpm[i]<-1.0f)s->var_fric.normalized_fil_rpm[i]=-1.0f;
+        /* 计算平均摩擦轮电机转速反馈 */
+        s->var_fric.normalized_fil_avgrpm[s->param->motor.fric[i].level-1]+=s->var_fric.normalized_fil_rpm[i];
+    }
+    for (int i=1; ivar_fric.normalized_fil_avgrpm[i]=s->var_fric.normalized_fil_avgrpm[i]/fric_num/MAX_NUM_MULTILEVEL;
+    }
+	/* 更新拨弹电机反馈 */
+    MOTOR_RM_Update(&s->param->motor.trig);
+	s->feedback.trig = *MOTOR_RM_GetMotor(&s->param->motor.trig); 
+	s->var_trig.trig_agl=s->param->basic.extra_deceleration_ratio*s->feedback.trig.gearbox_total_angle; 
+	while(s->var_trig.trig_agl<0)s->var_trig.trig_agl+=M_2PI;
+	while(s->var_trig.trig_agl>=M_2PI)s->var_trig.trig_agl-=M_2PI;
+	if (s->feedback.trig.motor.reverse) {
+        s->var_trig.trig_agl = M_2PI - s->var_trig.trig_agl;
+	}
+    s->var_trig.fil_trig_rpm = LowPassFilter2p_Apply(&s->filter.trig.in, s->feedback.trig.feedback.rotor_speed);
+    s->var_trig.trig_rpm = s->feedback.trig.feedback.rotor_speed / MAX_TRIG_RPM;
+    if(s->var_trig.trig_rpm>1.0f)s->var_trig.trig_rpm=1.0f;
+    if(s->var_trig.trig_rpm<-1.0f)s->var_trig.trig_rpm=-1.0f;
+    
+    s->errtosee = s->feedback.fric[0].rotor_speed - s->feedback.fric[1].rotor_speed;
+	return SHOOT_OK;
+}
+
+/**
+ * \brief 射击模块运行状态机
+ *
+ * \param s 包含射击数据的结构体
+ * \param cmd 包含射击指令的结构体
+ *
+ * \return 函数运行结果
+ */float a;
+int8_t Shoot_RunningFSM(Shoot_t *s, Shoot_CMD_t *cmd)
+{
+    if (s == NULL || cmd == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = s->param->basic.fric_num;
+    static float pos;
+    if(s->mode==SHOOT_MODE_SAFE){
+      for(int i=0;iparam->motor.fric[i].param);
+      }
+      MOTOR_RM_Relax(&s->param->motor.trig);\
+      pos=s->target_variable.trig_angle=s->var_trig.trig_agl;
+    }
+    else{
+        switch(s->running_state)
+        {
+            case SHOOT_STATE_IDLE:/*熄火等待*/
+                for(int i=0;ipid.fric_follow[i]);
+                    s->output.out_follow[i]=PID_Calc(&s->pid.fric_follow[i],0.0f,s->var_fric.normalized_fil_rpm[i],0,s->timer.dt);
+                    s->output.out_fric[i]=s->output.out_follow[i];
+                    s->output.lpfout_fric[i] = LowPassFilter2p_Apply(&s->filter.fric.out[i], s->output.out_fric[i]);
+                    MOTOR_RM_SetOutput(&s->param->motor.fric[i].param, s->output.lpfout_fric[i]);
+                }
+                
+                s->output.outagl_trig   =PID_Calc(&s->pid.trig,pos,s->var_trig.trig_agl,0,s->timer.dt);
+                s->output.outomg_trig  	=PID_Calc(&s->pid.trig_omg,s->output.outagl_trig,s->var_trig.trig_rpm,0,s->timer.dt);
+                s->output.outlpf_trig   =LowPassFilter2p_Apply(&s->filter.trig.out, s->output.outomg_trig);
+                MOTOR_RM_SetOutput(&s->param->motor.trig, s->output.outlpf_trig);
+
+                /* 检查状态机 */
+                if(cmd->ready)
+                    {   
+                        Shoot_ResetCalu(s);
+                        Shoot_ResetIntegral(s);
+                        Shoot_ResetOutput(s);
+                        s->running_state=SHOOT_STATE_READY;
+                    }
+                break;
+                
+            case SHOOT_STATE_READY:/*准备射击*/
+					for(int i=0;iparam->motor.fric[i].level-1;
+                        float target_rpm=s->param->basic.ratio_multilevel[level]
+                                    *s->target_variable.fric_rpm/MAX_FRIC_RPM;
+						/* 计算耦合控制权重 */
+                        float w=Shoot_CaluCoupledWeight(s,i);
+                        /* 计算跟随输出、计算修正输出 */
+						s->output.out_follow[i]=PID_Calc(&s->pid.fric_follow[i],
+														target_rpm,
+														s->var_fric.normalized_fil_rpm[i],
+														0,
+														s->timer.dt);
+						s->output.out_err[i]=w*PID_Calc(&s->pid.fric_err[i],
+														s->var_fric.normalized_fil_avgrpm[s->param->motor.fric[i].level-1],
+														s->var_fric.normalized_fil_rpm[i],
+														0,
+														s->timer.dt);
+						/* 按比例缩放并加和输出 */
+						ScaleSumTo1(&s->output.out_follow[i], &s->output.out_err[i]);                    
+						s->output.out_fric[i]=s->output.out_follow[i]+s->output.out_err[i];
+						/* 滤波 */
+						s->output.lpfout_fric[i] = LowPassFilter2p_Apply(&s->filter.fric.out[i], s->output.out_fric[i]);
+						/* 设置输出 */
+						MOTOR_RM_SetOutput(&s->param->motor.fric[i].param, s->output.lpfout_fric[i]);
+					}
+                /* 设置拨弹电机输出 */
+                s->output.outagl_trig   =PID_Calc(&s->pid.trig,
+													pos,
+													s->var_trig.trig_agl,
+													0,
+													s->timer.dt);
+                s->output.outomg_trig   =PID_Calc(&s->pid.trig_omg,
+													s->output.outagl_trig,
+													s->var_trig.trig_rpm,
+													0,
+													s->timer.dt);
+                s->output.outlpf_trig   =LowPassFilter2p_Apply(&s->filter.trig.out, s->output.outomg_trig);
+                MOTOR_RM_SetOutput(&s->param->motor.trig, s->output.outlpf_trig);
+                
+                /* 检查状态机 */
+                if(!cmd->ready)
+                    {
+                        Shoot_ResetCalu(s);
+                        Shoot_ResetOutput(s);
+                        s->running_state=SHOOT_STATE_IDLE;
+                    }
+                else if(last_firecmd==false&&cmd->firecmd==true)
+                    {
+                        s->running_state=SHOOT_STATE_FIRE;
+                        /* 根据模式设置待发射弹数 */
+                        switch(s->mode)
+                        {
+                            case SHOOT_MODE_SINGLE:
+                                s->var_trig.num_toShoot=1;
+                                break;
+                            case SHOOT_MODE_BURST:
+                                s->var_trig.num_toShoot=s->param->basic.shot_burst_num;
+                                break;
+                            case SHOOT_MODE_CONTINUE:
+                                s->var_trig.num_toShoot=6666;
+                                break;
+                            default:
+                                s->var_trig.num_toShoot=0;
+                                break;
+                        }
+                    }
+                break;
+
+            case SHOOT_STATE_FIRE:/*射击*/
+				Shoot_CaluTargetAngle(s, cmd);
+                for(int i=0;iparam->motor.fric[i].level-1;
+                    float target_rpm=s->param->basic.ratio_multilevel[level]
+                                    *s->target_variable.fric_rpm/MAX_FRIC_RPM;
+					/* 计算耦合控制权重 */
+                    float w=Shoot_CaluCoupledWeight(s,i);
+                    /* 计算跟随输出、计算修正输出 */ 
+                    s->output.out_follow[i]=PID_Calc(&s->pid.fric_follow[i],
+														target_rpm,
+														s->var_fric.normalized_fil_rpm[i],
+														0,
+														s->timer.dt);
+					s->output.out_err[i]=w*PID_Calc(&s->pid.fric_err[i],
+														s->var_fric.normalized_fil_avgrpm[s->param->motor.fric[i].level-1],
+														s->var_fric.normalized_fil_rpm[i],
+														0,
+														s->timer.dt);
+                    /* 按比例缩放并加和输出 */
+                    ScaleSumTo1(&s->output.out_follow[i], &s->output.out_err[i]);
+                    s->output.out_fric[i]=s->output.out_follow[i]+s->output.out_err[i];
+                    /* 滤波 */
+                    s->output.lpfout_fric[i] = LowPassFilter2p_Apply(&s->filter.fric.out[i], s->output.out_fric[i]);
+                    /* 设置输出 */
+                    MOTOR_RM_SetOutput(&s->param->motor.fric[i].param, s->output.lpfout_fric[i]);
+                }
+                /* 设置拨弹电机输出 */
+                s->output.outagl_trig   =PID_Calc(&s->pid.trig,
+													s->target_variable.trig_angle,
+													s->var_trig.trig_agl,
+													0,
+													s->timer.dt);
+                s->output.outomg_trig   =PID_Calc(&s->pid.trig_omg,
+													s->output.outagl_trig,
+													s->var_trig.trig_rpm,
+													0,
+													s->timer.dt);
+                s->output.outlpf_trig   =LowPassFilter2p_Apply(&s->filter.trig.out, s->output.outomg_trig);
+                MOTOR_RM_SetOutput(&s->param->motor.trig, s->output.outlpf_trig);
+
+                /* 检查状态机 */
+                if(!cmd->firecmd)
+                    {
+                      s->running_state=SHOOT_STATE_READY;
+						          pos=s->var_trig.trig_agl;
+                      s->var_trig.num_toShoot=0;
+                    }
+                break;
+
+            default:
+                s->running_state=SHOOT_STATE_IDLE;
+                break;
+        }
+    }
+    /* 输出 */
+	MOTOR_RM_Ctrl(&s->param->motor.fric[0].param);
+    if(s->param->basic.fric_num>4)
+    {
+        MOTOR_RM_Ctrl(&s->param->motor.fric[4].param);
+    }
+    MOTOR_RM_Ctrl(&s->param->motor.trig);
+    last_firecmd = cmd->firecmd;
+    return SHOOT_OK;
+}
+
+/**
+ * \brief 射击模块堵塞检测状态机
+ *
+ * \param s 包含射击数据的结构体
+ * \param cmd 包含射击指令的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_JamDetectionFSM(Shoot_t *s, Shoot_CMD_t *cmd)
+{
+    if (s == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    if(s->param->jamDetection.enable){
+        switch (s->jamdetection.fsmState) {
+            case SHOOT_JAMFSM_STATE_NORMAL:/* 正常运行 */
+                /* 检测电流是否超过阈值 */
+                if (s->feedback.trig.feedback.torque_current/1000.0f > s->param->jamDetection.threshold) {
+                    s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_SUSPECTED;
+                    s->jamdetection.lastTime = s->timer.now; /* 记录怀疑开始时间 */
+                }
+                /* 正常运行射击状态机 */
+                Shoot_RunningFSM(s, cmd);
+                break;
+            case SHOOT_JAMFSM_STATE_SUSPECTED:/* 怀疑堵塞 */
+                /* 检测电流是否低于阈值 */
+                if (s->feedback.trig.feedback.torque_current/1000.0f < s->param->jamDetection.threshold) {
+                    s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_NORMAL;
+                    break;
+                } 
+                /* 检测高阈值状态是否超过设定怀疑时间 */
+                else if ((s->timer.now - s->jamdetection.lastTime) >= s->param->jamDetection.suspectedTime) {
+                    s->jamdetection.detected =true;
+	    			s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_CONFIRMED;
+                    break;
+                }
+                /* 正常运行射击状态机 */
+                Shoot_RunningFSM(s, cmd);
+                break;
+            case SHOOT_JAMFSM_STATE_CONFIRMED:/* 确认堵塞 */
+                /* 清空待发射弹 */
+                s->var_trig.num_toShoot=0;
+                /* 修改拨弹盘目标角度 */
+                s->target_variable.trig_angle = s->var_trig.trig_agl-(M_2PI/s->param->basic.num_trig_tooth);
+                /* 切换状态 */
+                s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_DEAL;
+                /* 记录处理开始时间 */
+                s->jamdetection.lastTime = s->timer.now; 
+            case SHOOT_JAMFSM_STATE_DEAL:/* 堵塞处理 */
+                /* 正常运行射击状态机 */
+                Shoot_RunningFSM(s, cmd);
+                /* 给予0.3秒响应时间并检测电流小于20A，认为堵塞已解除 */
+                if ((s->timer.now - s->jamdetection.lastTime)>=0.3f&&s->feedback.trig.feedback.torque_current/1000.0f < 20.0f) { 
+                    s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_NORMAL;
+                }
+                break;
+            default:
+                s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_NORMAL;
+                break;
+        }
+    }
+    else{   
+        s->jamdetection.fsmState = SHOOT_JAMFSM_STATE_NORMAL;
+        s->jamdetection.detected = false;
+        Shoot_RunningFSM(s, cmd);
+    }
+
+    return SHOOT_OK;
+}
+/* Exported functions ------------------------------------------------------- */
+/**
+ * \brief 初始化射击模块
+ *
+ * \param s 包含射击数据的结构体
+ * \param param 包含射击参数的结构体
+ * \param target_freq 控制循环频率，单位Hz
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_Init(Shoot_t *s, Shoot_Params_t *param, float target_freq)
+{
+    if (s == NULL || param == NULL || target_freq <= 0.0f) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    uint8_t fric_num = param->basic.fric_num;
+    s->param=param;
+    BSP_CAN_Init();
+    /* 初始化摩擦轮PID和滤波器 */
+    for(int i=0;imotor.fric[i].param);
+        PID_Init(&s->pid.fric_follow[i], 
+            KPID_MODE_CALC_D, 
+            target_freq,
+            ¶m->pid.fric_follow);
+	    PID_Init(&s->pid.fric_err[i], 
+            KPID_MODE_CALC_D, 
+            target_freq,
+            ¶m->pid.fric_err);
+        LowPassFilter2p_Init(&s->filter.fric.in[i], 
+            target_freq, 
+            s->param->filter.fric.in);
+        LowPassFilter2p_Init(&s->filter.fric.out[i], 
+            target_freq, 
+            s->param->filter.fric.out);
+    }
+    /* 初始化拨弹PID和滤波器 */
+	MOTOR_RM_Register(¶m->motor.trig);
+    switch(s->param->motor.trig.module)
+    {
+        case MOTOR_M3508:
+            PID_Init(&s->pid.trig, 
+                KPID_MODE_CALC_D, 
+                target_freq,
+                ¶m->pid.trig_3508);
+            PID_Init(&s->pid.trig_omg, 
+                KPID_MODE_CALC_D, 
+                target_freq,
+                ¶m->pid.trig_omg_3508);
+            break;
+        case MOTOR_M2006:
+            PID_Init(&s->pid.trig, 
+                KPID_MODE_CALC_D, 
+                target_freq,
+                ¶m->pid.trig_2006);
+            PID_Init(&s->pid.trig_omg, 
+                KPID_MODE_CALC_D, 
+                target_freq,
+                ¶m->pid.trig_omg_2006);
+            break;
+        default:
+            return SHOOT_ERR_MOTOR;
+        break;
+    }
+    LowPassFilter2p_Init(&s->filter.trig.in, 
+        target_freq, 
+        s->param->filter.trig.in);
+    LowPassFilter2p_Init(&s->filter.trig.out, 
+        target_freq, 
+        s->param->filter.trig.out);
+
+	/* 归零变量 */
+    memset(&s->var_trig,0,sizeof(s->var_trig));
+	return SHOOT_OK;
+}
+
+/**
+ * \brief 射击模块控制主函数
+ *
+ * \param s 包含射击数据的结构体
+ * \param cmd 包含射击指令的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_Control(Shoot_t *s, Shoot_CMD_t *cmd)
+{
+    if (s == NULL || cmd == NULL) {
+        return SHOOT_ERR_NULL; // 参数错误
+    }
+    s->timer.now = BSP_TIME_Get_us() / 1000000.0f;
+    s->timer.dt = (BSP_TIME_Get_us() - s->timer.lask_wakeup) / 1000000.0f;
+    s->timer.lask_wakeup = BSP_TIME_Get_us();
+    Shoot_CaluTargetRPM(s,233);
+
+    Shoot_JamDetectionFSM(s, cmd);
+//    Shoot_CalufeedbackRPM(s);
+    return SHOOT_OK;
+}
+
+
+
+
+
+
+
+
diff --git a/User/module/shoot.h b/User/module/shoot.h
new file mode 100644
index 0000000..f119468
--- /dev/null
+++ b/User/module/shoot.h
@@ -0,0 +1,243 @@
+/*
+ * far♂蛇模块
+ */
+
+#pragma once
+
+#include 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "main.h"
+#include "component/pid.h"
+#include "device/motor_rm.h"
+/* Exported constants ------------------------------------------------------- */
+#define MAX_FRIC_NUM 2
+#define MAX_NUM_MULTILEVEL 1 /* 多级发射级数 */
+
+#define SHOOT_OK (0)        /* 运行正常 */
+#define SHOOT_ERR_NULL (-1) /* 运行时发现NULL指针 */    
+#define SHOOT_ERR_ERR (-2)  /* 运行时发现了其他错误 */
+#define SHOOT_ERR_MODE (-3) /* 运行时配置了错误的Mode */
+#define SHOOT_ERR_MOTOR (-4) /* 运行时配置了不存在的电机类型 */
+#define SHOOT_ERR_MALLOC (-5) /* 内存分配失败 */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+typedef enum {
+    SHOOT_JAMFSM_STATE_NORMAL = 0,/* 常规状态 */
+    SHOOT_JAMFSM_STATE_SUSPECTED, /* 怀疑状态 */
+    SHOOT_JAMFSM_STATE_CONFIRMED, /* 确认状态 */
+    SHOOT_JAMFSM_STATE_DEAL       /* 处理状态 */
+}Shoot_JamDetectionFSM_State_t;
+typedef enum {
+    SHOOT_STATE_IDLE = 0,/* 熄火 */
+    SHOOT_STATE_READY,   /* 准备射击 */
+    SHOOT_STATE_FIRE     /* 射击 */
+}Shoot_Running_State_t;
+
+typedef enum {
+    SHOOT_MODE_SAFE = 0,/* 安全模式 */
+    SHOOT_MODE_SINGLE,  /* 单发模式 */
+    SHOOT_MODE_BURST,   /* 多发模式 */
+    SHOOT_MODE_CONTINUE,/* 连发模式 */
+    SHOOT_MODE_NUM
+}Shoot_Mode_t;
+
+typedef enum {
+	SHOOT_PROJECTILE_17MM,
+	SHOOT_PROJECTILE_42MM,
+}Shoot_Projectile_t;
+
+typedef struct{
+	MOTOR_RM_Param_t param;
+	uint8_t level; /* 电机属于第几级发射；1起始 */
+}Shoot_MOTOR_RM_Param_t;
+
+typedef struct {
+  MOTOR_Feedback_t fric[MAX_FRIC_NUM];/* 摩擦轮电机反馈 */
+  MOTOR_RM_t trig;                    /* 拨弹电机反馈 */
+  
+}Shoot_Feedback_t;
+
+typedef struct{
+  float fil_rpm[MAX_FRIC_NUM]; /* 滤波后的摩擦轮原始转速 */
+  float normalized_fil_rpm[MAX_FRIC_NUM]; /* 归一化摩擦轮转速 */
+  float normalized_fil_avgrpm[MAX_NUM_MULTILEVEL];            /* 归一化摩擦轮平均转速 */
+  float coupled_control_weights; /* 耦合控制权重 */
+}Shoot_VARSForFricCtrl_t;
+
+typedef struct{
+  float time_lastShoot;/* 上次射击时间 */
+  uint16_t num_toShoot;/* 剩余待发射弹数 */
+  uint16_t num_shooted;/* 已发射弹数 */
+
+  float trig_agl;	     /*计算所有减速比后的拨弹盘的角度*/
+  float fil_trig_rpm;  /* 滤波后的拨弹电机转速*/
+  float trig_rpm;      /* 归一化拨弹电机转速 */
+}Shoot_VARSForTrigCtrl_t;
+
+typedef struct {
+  bool detected; /* 卡弹检测结果 */
+  float lastTime;/* 用于记录怀疑状态或处理状态的开始时间 */
+  Shoot_JamDetectionFSM_State_t fsmState; /* 卡弹检测状态机 */
+}Shoot_JamDetection_t;
+typedef struct {
+  float out_follow[MAX_FRIC_NUM];
+  float out_err[MAX_FRIC_NUM];
+  float out_fric[MAX_FRIC_NUM];
+  float lpfout_fric[MAX_FRIC_NUM];
+
+  float outagl_trig;
+  float outomg_trig;
+  float outlpf_trig;
+}Shoot_Output_t;
+
+typedef struct {
+  Shoot_Mode_t mode;/* 射击模式 */
+  bool ready;       /* 准备射击 */
+  bool firecmd;     /* 射击 */
+}Shoot_CMD_t;
+/* 底盘参数的结构体，包含所有初始化用的参数，通常是const，存好几组 */
+typedef struct {
+  struct{
+    Shoot_Projectile_t projectileType; /* 发射弹丸类型 */;
+    size_t fric_num;                   /* 摩擦轮电机数量 */
+    float ratio_multilevel[MAX_NUM_MULTILEVEL]; /* 多级发射各级速度比例 */
+    float extra_deceleration_ratio;	            /*电机出轴到拨盘的额外减速比；没有写1*/
+    size_t num_trig_tooth;  /* 拨弹盘每圈弹丸数量 */
+    float shot_freq;        /* 射击频率，单位Hz */
+    size_t shot_burst_num;  /* 多发模式一次射击的数量 */
+  }basic;/* 发射基础参数 */
+  struct {
+    bool  enable;       /* 是否启用卡弹检测 */ 
+    float threshold;    /* 卡弹检测阈值，单位A (dji2006建议设置为120A，dji3508建议设置为235A,根据实际测试调整)*/
+    float suspectedTime;/* 卡弹怀疑时间，单位秒 */
+  }jamDetection;/* 卡弹检测参数 */
+  struct {
+  Shoot_MOTOR_RM_Param_t fric[MAX_FRIC_NUM];
+  MOTOR_RM_Param_t trig;
+  }motor; /* 电机参数 */
+  struct{
+    KPID_Params_t fric_follow;  /* 摩擦轮电机PID控制参数，用于跟随目标速度 */
+    KPID_Params_t fric_err;     /* 摩擦轮电机PID控制参数，用于消除转速误差 */
+    KPID_Params_t trig_2006;    /* 拨弹电机PID控制参数 */
+    KPID_Params_t trig_omg_2006;/* 拨弹电机PID控制参数 */
+    KPID_Params_t trig_3508;    /* 拨弹电机PID控制参数 */
+    KPID_Params_t trig_omg_3508;/* 拨弹电机PID控制参数 */
+  }pid; /* PID参数 */
+  struct {
+    struct{
+    float in;  /* 反馈值滤波器截止频率 */
+    float out; /* 输出值滤波器截止频率 */
+    }fric;
+    struct{
+    float in;  /* 反馈值滤波器截止频率 */
+    float out; /* 输出值滤波器截止频率 */
+    }trig;
+  } filter;/* 滤波器截止频率参数 */
+} Shoot_Params_t;
+
+typedef struct {
+  float now;            /* 当前时间，单位秒 */
+  uint64_t lask_wakeup; /* 上次唤醒时间，单位微秒 */
+  float dt;             /* 两次唤醒间隔时间，单位秒 */
+}Shoot_Timer_t;
+
+/*
+ * 运行的主结构体，所有这个文件里的函数都在操作这个结构体
+ * 包含了初始化参数，中间变量，输出变量
+ */
+typedef struct {
+  Shoot_Timer_t timer; /* 计时器 */
+  Shoot_Params_t *param; /* 发射参数 */
+  /* 模块通用 */           
+  Shoot_Mode_t mode; /* 射击模式 */
+  /* 反馈信息 */           
+  Shoot_Feedback_t feedback;
+  /* 控制信息*/         
+  Shoot_Running_State_t running_state; /* 运行状态机 */ 
+  Shoot_JamDetection_t jamdetection; /* 卡弹检测控制信息 */
+  Shoot_VARSForFricCtrl_t var_fric; /* 摩擦轮控制信息 */
+  Shoot_VARSForTrigCtrl_t var_trig; /* 角度计算控制信息 */
+  Shoot_Output_t output; /* 输出信息 */
+  /* 目标控制量 */           
+  struct {           
+    float fric_rpm;  /* 目标摩擦轮转速 */
+    float trig_angle;/* 目标拨弹位置 */
+  }target_variable;
+
+  /* 反馈控制用的PID */
+  struct {
+    KPID_t fric_follow[MAX_FRIC_NUM];/* 摩擦轮PID主结构体 */
+    KPID_t fric_err[MAX_FRIC_NUM];   /* 摩擦轮PID主结构体 */
+    KPID_t trig;                     /* 拨弹PID主结构体 */
+    KPID_t trig_omg;                 /* 拨弹PID主结构体 */
+  } pid;
+
+  /* 滤波器 */
+  struct {
+    struct{
+    LowPassFilter2p_t in[MAX_FRIC_NUM]; /* 反馈值滤波器 */
+    LowPassFilter2p_t out[MAX_FRIC_NUM];/* 输出值滤波器 */
+    }fric;
+    struct{
+    LowPassFilter2p_t in; /* 反馈值滤波器 */
+    LowPassFilter2p_t out;/* 输出值滤波器 */
+    }trig;
+  } filter;
+
+  float errtosee; /*调试用*/
+
+} Shoot_t;
+
+/* Exported functions prototypes -------------------------------------------- */
+
+/**
+ * \brief 初始化发射
+ *
+ * \param s 包含发射数据的结构体
+ * \param param 包含发射参数的结构体指针
+ * \param target_freq 任务预期的运行频率
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_Init(Shoot_t *s, Shoot_Params_t *param, float target_freq);
+
+/**
+ * \brief 设置发射模式
+ *
+ * \param s 包含发射数据的结构体
+ * \param mode 包含发射模式的枚举
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_SetMode(Shoot_t *s, Shoot_Mode_t mode);
+
+/**
+ * \brief 更新反馈
+ *
+ * \param s 包含发射数据的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_UpdateFeedback(Shoot_t *s);
+
+/**
+ * \brief 初始化发射
+ *
+ * \param s 包含发射数据的结构体
+ * \param cmd 包含发射命令的结构体
+ *
+ * \return 函数运行结果
+ */
+int8_t Shoot_Control(Shoot_t *s, Shoot_CMD_t *cmd);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
diff --git a/User/module/struct_typedef.h b/User/module/struct_typedef.h
new file mode 100644
index 0000000..4d4fbc5
--- /dev/null
+++ b/User/module/struct_typedef.h
@@ -0,0 +1,23 @@
+#ifndef STRUCT_TYPEDEF_H
+#define STRUCT_TYPEDEF_H
+
+
+typedef signed char int8_t;
+typedef signed short int int16_t;
+typedef signed int int32_t;
+typedef signed long long int64_t;
+
+/* exact-width unsigned integer types */
+typedef unsigned char uint8_t;
+typedef unsigned short int uint16_t;
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+typedef unsigned char bool_t;
+typedef float fp32;
+typedef double fp64;
+
+////
+#endif
+
+
+
diff --git a/User/task/ai.c b/User/task/ai.c
new file mode 100644
index 0000000..d665d36
--- /dev/null
+++ b/User/task/ai.c
@@ -0,0 +1,55 @@
+/*
+    ai Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "device/ai.h"
+#include "gimbal.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+AI_t ai;
+AI_cmd_t ai_cmd;
+Gimbal_Feedback_t g_feedback;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_ai(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / AI_FREQ;
+
+  osDelay(AI_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+		
+		if(osMessageQueueGet(task_runtime.msgq.ai.motor, &g_feedback, NULL, 0)==osOK)		
+		AI_ParseHost(&ai,&g_feedback);
+		AI_StartSend(&ai);
+		
+		AI_StartReceiving(&ai);		
+		AI_Get_NUC(&ai,&ai_cmd);		
+    osMessageQueueReset(task_runtime.msgq.ai.g_cmd);
+    osMessageQueuePut(task_runtime.msgq.ai.g_cmd, &ai_cmd, 0, 0);		
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/atti_esti.c b/User/task/atti_esti.c
new file mode 100644
index 0000000..14e0837
--- /dev/null
+++ b/User/task/atti_esti.c
@@ -0,0 +1,157 @@
+/*
+    atti_esti Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "bsp/pwm.h"
+#include "component/ahrs.h"
+#include "component/pid.h"
+#include "device/bmi088.h"
+#include "module/gimbal.h"
+#include "ist8310.h"
+
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+BMI088_t bmi088;
+IST8310_t ist8310;
+AHRS_t gimbal_ahrs;
+AHRS_Magn_t magn;
+AHRS_Eulr_t eulr_to_send;
+
+KPID_t imu_temp_ctrl_pid;
+
+Gimbal_IMU_t gimbal_to_send;
+
+BMI088_Cali_t cali_bmi088= {
+  .gyro_offset = {-0.00115062925,-0.00201643188,-4.1654228e-05},
+};
+
+static const KPID_Params_t imu_temp_ctrl_pid_param = {
+    .k = 0.15f,
+    .p = 1.0f,
+    .i = 0.0f,
+    .d = 0.0f,
+    .i_limit = 1.0f,
+    .out_limit = 1.0f,
+};
+
+/* 校准相关变量 */
+typedef enum {
+  CALIB_IDLE,     // 空闲状态
+  CALIB_RUNNING,  // 正在校准
+  CALIB_DONE      // 校准完成
+} CalibState_t;
+
+static CalibState_t calib_state = CALIB_IDLE;
+static uint16_t calib_count = 0;
+static struct {
+  float x_sum;
+  float y_sum; 
+  float z_sum;
+} gyro_sum= {0.0f,0.0f,0.0f};
+
+static void start_gyro_calibration(void) {
+  if (calib_state == CALIB_IDLE) {
+    BSP_TIME_Delay(1000);
+    calib_state = CALIB_RUNNING;
+    calib_count = 0;
+    gyro_sum.x_sum = 0.0f;
+    gyro_sum.y_sum = 0.0f;
+    gyro_sum.z_sum = 0.0f;
+  }
+}
+#define CALIB_SAMPLES 5000  // 校准采样数量
+
+int jiaozhun=0;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_atti_esti(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / ATTI_ESTI_FREQ;
+
+  osDelay(ATTI_ESTI_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+  BMI088_Init(&bmi088,&cali_bmi088);
+  AHRS_Init(&gimbal_ahrs, &magn, BMI088_GetUpdateFreq(&bmi088));
+	PID_Init(&imu_temp_ctrl_pid, KPID_MODE_NO_D,
+           1.0f / BMI088_GetUpdateFreq(&bmi088), &imu_temp_ctrl_pid_param);
+
+  /* IMU温度控制PWM输出 */
+  BSP_PWM_Start(BSP_PWM_IMU_HEAT);
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+    BMI088_WaitNew();
+    BMI088_AcclStartDmaRecv();
+    BMI088_AcclWaitDmaCplt();
+
+    BMI088_GyroStartDmaRecv();
+    BMI088_GyroWaitDmaCplt();
+
+    /* 锁住RTOS内核防止数据解析过程中断，造成错误 */
+    osKernelLock();
+    /* 接收完所有数据后，把数据从原始字节加工成方便计算的数据 */
+    BMI088_ParseAccl(&bmi088);
+    BMI088_ParseGyro(&bmi088);
+		/* 根据设备接收到的数据进行姿态解析 */
+    AHRS_Update(&gimbal_ahrs, &bmi088.accl, &bmi088.gyro, &magn);
+
+    /* 根据解析出来的四元数计算欧拉角 */
+    AHRS_GetEulr(&eulr_to_send, &gimbal_ahrs);
+    osKernelUnlock();
+
+/* 累加陀螺仪数据用于计算零偏 */
+    if(jiaozhun==1){
+      /* 累加陀螺仪数据用于计算零偏 */
+      gyro_sum.x_sum += bmi088.gyro.x;
+      gyro_sum.y_sum += bmi088.gyro.y;
+      gyro_sum.z_sum += bmi088.gyro.z;
+      calib_count++;
+
+      /* 达到采样数量后计算平均值并更新零偏 */
+      if (calib_count >= CALIB_SAMPLES) {
+        /* 计算平均值作为零偏 */
+        cali_bmi088.gyro_offset.x = gyro_sum.x_sum / CALIB_SAMPLES;
+        cali_bmi088.gyro_offset.y = gyro_sum.y_sum / CALIB_SAMPLES;
+        cali_bmi088.gyro_offset.z = gyro_sum.z_sum / CALIB_SAMPLES;
+        
+        /* 校准完成，重置为空闲状态以便下次校准 */
+       calib_state = CALIB_IDLE;
+        jiaozhun=0;
+        /* 重新初始化BMI088以应用新的校准数据 */
+       BMI088_Init(&bmi088, &cali_bmi088);
+       AHRS_Init(&gimbal_ahrs, &ist8310.magn, BMI088_GetUpdateFreq(&bmi088));
+      }
+    }
+
+
+		BSP_PWM_SetComp(BSP_PWM_IMU_HEAT,
+		PID_Calc(&imu_temp_ctrl_pid, 40.0f, bmi088.temp, 0.0f, 0.0f));				
+    gimbal_to_send.eulr = eulr_to_send;
+    gimbal_to_send.gyro = bmi088.gyro;
+    gimbal_to_send.accl = bmi088.accl;
+    gimbal_to_send.quat = gimbal_ahrs.quat;		
+    osMessageQueueReset(task_runtime.msgq.gimbal.imu);
+    osMessageQueuePut(task_runtime.msgq.gimbal.imu, &gimbal_to_send, 0, 0);
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/chassis_ctrl.c b/User/task/chassis_ctrl.c
new file mode 100644
index 0000000..9c350ab
--- /dev/null
+++ b/User/task/chassis_ctrl.c
@@ -0,0 +1,44 @@
+/*
+    chassis_ctrl Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_chassis_ctrl(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / CHASSIS_CTRL_FREQ;
+
+  osDelay(CHASSIS_CTRL_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/config.yaml b/User/task/config.yaml
new file mode 100644
index 0000000..f1073ee
--- /dev/null
+++ b/User/task/config.yaml
@@ -0,0 +1,49 @@
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_shoot_ctrl
+  name: shoot_ctrl
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_chassis_ctrl
+  name: chassis_ctrl
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_gimbal_ctrl
+  name: gimbal_ctrl
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_dr16
+  name: dr16
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_ai
+  name: ai
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_atti_esti
+  name: atti_esti
+  stack: 256
+- delay: 0
+  description: ''
+  freq_control: true
+  frequency: 500.0
+  function: Task_remote
+  name: remote
+  stack: 256
diff --git a/User/task/dr16.c b/User/task/dr16.c
new file mode 100644
index 0000000..fee40d3
--- /dev/null
+++ b/User/task/dr16.c
@@ -0,0 +1,56 @@
+/*
+    dr16 Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "device/dr16.h"
+#include "module/remote_cmd.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+DR16_t dr16;
+//CMD_RC_t cmd_rc;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_dr16(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / DR16_FREQ;
+
+  osDelay(DR16_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+  DR16_Init(&dr16); /* 初始化dr16 */
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+    DR16_StartDmaRecv(&dr16);
+    if (DR16_WaitDmaCplt(20)) {
+      DR16_ParseData(&dr16);
+      
+    } 
+		else {
+      DR16_Offline(&dr16);
+    }
+		
+		osMessageQueueReset(task_runtime.msgq.remote.dr16);
+    osMessageQueuePut(task_runtime.msgq.remote.dr16,&dr16, 0, 0);				
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/gimbal_ctrl.c b/User/task/gimbal_ctrl.c
new file mode 100644
index 0000000..b8e39ac
--- /dev/null
+++ b/User/task/gimbal_ctrl.c
@@ -0,0 +1,79 @@
+/*
+    gimbal_ctrl Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "ai.h"
+#include "gimbal.h"
+#include "module/config.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+AI_cmd_t ai_g_cmd;
+Gimbal_t gimbal;
+Gimbal_IMU_t gimbal_imu;
+Gimbal_CMD_t gimbal_cmd;
+Gimbal_CMD_t gimbal_cmd_ai;
+Gimbal_CMD_t gimbal_cmd_remote;
+Gimbal_Direction_t send_nuc;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_gimbal_ctrl(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / GIMBAL_CTRL_FREQ;
+
+  osDelay(GIMBAL_CTRL_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+ Gimbal_Init(&gimbal,&Config_GetRobotParam()->gimbal_param,GIMBAL_CTRL_FREQ);
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+		/* 陀螺仪数据更新 */
+		if(osMessageQueueGet(task_runtime.msgq.gimbal.imu, &gimbal_imu, NULL, 0)==osOK){
+      Gimbal_UpdateIMU(&gimbal, &gimbal_imu);
+		}
+		/* ai指令 */
+		if(osMessageQueueGet(task_runtime.msgq.ai.g_cmd, &ai_g_cmd, NULL, 0)==osOK);
+			if(ai_g_cmd.mode==0){
+      gimbal_cmd.set_pit=gimbal_imu.eulr.rol;
+      gimbal_cmd.set_yaw=gimbal_imu.eulr.yaw;			
+			}
+			if(ai_g_cmd.mode==2){
+      gimbal_cmd.set_pit=ai_g_cmd.gimbal_t.setpoint.pit;
+      gimbal_cmd.set_yaw=ai_g_cmd.gimbal_t.setpoint.yaw;
+			}				
+		if(osMessageQueueGet(task_runtime.msgq.gimbal.cmd, &gimbal_cmd_remote, NULL, 0)==osOK)
+		gimbal_cmd.mode=gimbal_cmd_remote.mode;
+		gimbal_cmd.ctrl_mode=gimbal_cmd_remote.ctrl_mode;
+		gimbal_cmd.delta_pit=gimbal_cmd_remote.delta_pit;
+		gimbal_cmd.delta_yaw=gimbal_cmd_remote.delta_yaw;
+		
+		Gimbal_UpdateFeedback(&gimbal);
+    Gimbal_Control(&gimbal,&gimbal_cmd);
+    Gimbal_Output(&gimbal);
+		osMessageQueueReset(task_runtime.msgq.ai.imu);
+    osMessageQueuePut(task_runtime.msgq.ai.imu,&gimbal.direction, 0, 0);
+		osMessageQueueReset(task_runtime.msgq.ai.motor);
+    osMessageQueuePut(task_runtime.msgq.ai.motor,&gimbal.feedback, 0, 0);		
+		
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/init.c b/User/task/init.c
new file mode 100644
index 0000000..81646b6
--- /dev/null
+++ b/User/task/init.c
@@ -0,0 +1,59 @@
+/*
+    Init Task
+    任务初始化，创建各个线程任务和消息队列
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+
+/* USER INCLUDE BEGIN */
+#include "gimbal.h"
+#include "ai.h"
+#include "shoot.h"
+#include "dr16.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+
+/**
+ * \brief 初始化
+ *
+ * \param argument 未使用
+ */
+void Task_Init(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+    /* USER CODE INIT BEGIN */
+
+    /* USER CODE INIT END */
+  osKernelLock(); /* 锁定内核，防止任务切换 */
+  
+  /* 创建任务线程 */
+  task_runtime.thread.shoot_ctrl = osThreadNew(Task_shoot_ctrl, NULL, &attr_shoot_ctrl);
+  task_runtime.thread.chassis_ctrl = osThreadNew(Task_chassis_ctrl, NULL, &attr_chassis_ctrl);
+  task_runtime.thread.gimbal_ctrl = osThreadNew(Task_gimbal_ctrl, NULL, &attr_gimbal_ctrl);
+  task_runtime.thread.dr16 = osThreadNew(Task_dr16, NULL, &attr_dr16);
+  task_runtime.thread.ai = osThreadNew(Task_ai, NULL, &attr_ai);
+  task_runtime.thread.atti_esti = osThreadNew(Task_atti_esti, NULL, &attr_atti_esti);
+  task_runtime.thread.remote = osThreadNew(Task_remote, NULL, &attr_remote);
+
+  // 创建消息队列
+  /* USER MESSAGE BEGIN */
+  task_runtime.msgq.user_msg= osMessageQueueNew(2u, 10, NULL);
+   task_runtime.msgq.remote.dr16= osMessageQueueNew(2u, sizeof(DR16_t), NULL);
+	task_runtime.msgq.gimbal.imu= osMessageQueueNew(2u, sizeof(Gimbal_IMU_t), NULL);
+  task_runtime.msgq.gimbal.cmd= osMessageQueueNew(2u, sizeof(Gimbal_CMD_t), NULL);
+
+	task_runtime.msgq.ai.imu= osMessageQueueNew(2u, sizeof(Gimbal_Direction_t), NULL);
+	task_runtime.msgq.ai.motor= osMessageQueueNew(2u, sizeof(Gimbal_Feedback_t), NULL);	
+	task_runtime.msgq.ai.g_cmd= osMessageQueueNew(2u, sizeof(AI_cmd_t), NULL);	
+	task_runtime.msgq.shoot.cmd= osMessageQueueNew(2u, sizeof(Shoot_CMD_t), NULL);
+  /* USER MESSAGE END */
+
+  osKernelUnlock(); // 解锁内核
+  osThreadTerminate(osThreadGetId()); // 任务完成后结束自身
+}
\ No newline at end of file
diff --git a/User/task/remote.c b/User/task/remote.c
new file mode 100644
index 0000000..891db1f
--- /dev/null
+++ b/User/task/remote.c
@@ -0,0 +1,56 @@
+/*
+    remote Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "module/gimbal.h"
+#include "module/shoot.h"
+#include "module/remote_cmd.h"
+#include "device/dr16.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+Gimbal_CMD_t g_rc_cmd;
+Shoot_CMD_t s_rc_cmd;
+DR16_t remote_dr16;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_remote(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / REMOTE_FREQ;
+
+  osDelay(REMOTE_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */\
+		
+		if(osMessageQueueGet(task_runtime.msgq.remote.dr16, &remote_dr16, NULL, 0)==osOK);				
+		Gimbal_Cmd(&g_rc_cmd,&remote_dr16);
+		Shoot_Cmd(&s_rc_cmd,&remote_dr16); 
+		osMessageQueueReset(task_runtime.msgq.gimbal.cmd);
+    osMessageQueuePut(task_runtime.msgq.gimbal.cmd,&g_rc_cmd, 0, 0);				
+		osMessageQueueReset(task_runtime.msgq.shoot.cmd);
+    osMessageQueuePut(task_runtime.msgq.shoot.cmd,&s_rc_cmd, 0, 0);						
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/shoot_ctrl.c b/User/task/shoot_ctrl.c
new file mode 100644
index 0000000..43f6e50
--- /dev/null
+++ b/User/task/shoot_ctrl.c
@@ -0,0 +1,51 @@
+/*
+    shoot_ctrl Task
+    
+*/
+
+/* Includes ----------------------------------------------------------------- */
+#include "task/user_task.h"
+/* USER INCLUDE BEGIN */
+#include "module/shoot.h"
+#include "module/config.h"
+/* USER INCLUDE END */
+
+/* Private typedef ---------------------------------------------------------- */
+/* Private define ----------------------------------------------------------- */
+/* Private macro ------------------------------------------------------------ */
+/* Private variables -------------------------------------------------------- */
+/* USER STRUCT BEGIN */
+//Remote_Mode s_mode;
+Shoot_t shoot;
+Shoot_CMD_t shoot_cmd;
+/* USER STRUCT END */
+
+/* Private function --------------------------------------------------------- */
+/* Exported functions ------------------------------------------------------- */
+void Task_shoot_ctrl(void *argument) {
+  (void)argument; /* 未使用argument，消除警告 */
+
+  
+  /* 计算任务运行到指定频率需要等待的tick数 */
+  const uint32_t delay_tick = osKernelGetTickFreq() / SHOOT_CTRL_FREQ;
+
+  osDelay(SHOOT_CTRL_INIT_DELAY); /* 延时一段时间再开启任务 */
+
+  uint32_t tick = osKernelGetTickCount(); /* 控制任务运行频率的计时 */
+  /* USER CODE INIT BEGIN */
+	Shoot_Init(&shoot,&Config_GetRobotParam()->shoot_param,SHOOT_CTRL_FREQ);
+	Shoot_SetMode(&shoot,SHOOT_MODE_SINGLE);			
+  /* USER CODE INIT END */
+  
+  while (1) {
+    tick += delay_tick; /* 计算下一个唤醒时刻 */
+    /* USER CODE BEGIN */
+	  osMessageQueueGet(task_runtime.msgq.shoot.cmd, &shoot_cmd, NULL, 0);
+		shoot_cmd.mode=SHOOT_MODE_SINGLE;
+	  Shoot_UpdateFeedback(&shoot);
+	  Shoot_Control(&shoot,&shoot_cmd);
+    /* USER CODE END */
+    osDelayUntil(tick); /* 运行结束，等待下一次唤醒 */
+  }
+  
+}
\ No newline at end of file
diff --git a/User/task/user_task.c b/User/task/user_task.c
new file mode 100644
index 0000000..bb4ad13
--- /dev/null
+++ b/User/task/user_task.c
@@ -0,0 +1,46 @@
+#include "task/user_task.h"
+
+Task_Runtime_t task_runtime;
+
+const osThreadAttr_t attr_init = {
+    .name = "Task_Init",
+    .priority = osPriorityRealtime,
+    .stack_size = 256 * 4,
+};
+
+/* User_task */
+const osThreadAttr_t attr_shoot_ctrl = {
+    .name = "shoot_ctrl",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_chassis_ctrl = {
+    .name = "chassis_ctrl",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_gimbal_ctrl = {
+    .name = "gimbal_ctrl",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_dr16 = {
+    .name = "dr16",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_ai = {
+    .name = "ai",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_atti_esti = {
+    .name = "atti_esti",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
+const osThreadAttr_t attr_remote = {
+    .name = "remote",
+    .priority = osPriorityNormal,
+    .stack_size = 256 * 4,
+};
\ No newline at end of file
diff --git a/User/task/user_task.h b/User/task/user_task.h
new file mode 100644
index 0000000..17341f9
--- /dev/null
+++ b/User/task/user_task.h
@@ -0,0 +1,150 @@
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Includes ----------------------------------------------------------------- */
+#include 
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* USER INCLUDE BEGIN */
+
+/* USER INCLUDE END */
+/* Exported constants ------------------------------------------------------- */
+/* 任务运行频率 */
+#define SHOOT_CTRL_FREQ (500.0)
+#define CHASSIS_CTRL_FREQ (500.0)
+#define GIMBAL_CTRL_FREQ (500.0)
+#define DR16_FREQ (500.0)
+#define AI_FREQ (500.0)
+#define ATTI_ESTI_FREQ (500.0)
+#define REMOTE_FREQ (500.0)
+
+/* 任务初始化延时ms */
+#define TASK_INIT_DELAY (100u)
+#define SHOOT_CTRL_INIT_DELAY (0)
+#define CHASSIS_CTRL_INIT_DELAY (0)
+#define GIMBAL_CTRL_INIT_DELAY (0)
+#define DR16_INIT_DELAY (0)
+#define AI_INIT_DELAY (0)
+#define ATTI_ESTI_INIT_DELAY (0)
+#define REMOTE_INIT_DELAY (0)
+
+/* Exported defines --------------------------------------------------------- */
+/* Exported macro ----------------------------------------------------------- */
+/* Exported types ----------------------------------------------------------- */
+
+/* 任务运行时结构体 */
+typedef struct {
+    /* 各任务，也可以叫做线程 */
+    struct {
+        osThreadId_t shoot_ctrl;
+        osThreadId_t chassis_ctrl;
+        osThreadId_t gimbal_ctrl;
+        osThreadId_t dr16;
+        osThreadId_t ai;
+        osThreadId_t atti_esti;
+        osThreadId_t remote;
+    } thread;
+
+    /* USER MESSAGE BEGIN */
+    struct {
+        osMessageQueueId_t user_msg; /* 用户自定义任务消息队列 */
+							struct {
+            osMessageQueueId_t cmd; /* 发射命令队列 */
+        }shoot;
+        struct {
+            osMessageQueueId_t imu;
+            osMessageQueueId_t cmd;
+			osMessageQueueId_t remote;
+        }gimbal;
+				 struct {
+            osMessageQueueId_t imu;
+            osMessageQueueId_t g_cmd;
+						osMessageQueueId_t motor;
+        }ai;
+				struct {
+            osMessageQueueId_t mode; /* 发射命令队列 */
+            osMessageQueueId_t dr16/* 发射命令队列 */
+        }remote;
+			
+			
+			
+			
+			
+    } msgq;
+    /* USER MESSAGE END */
+
+    /* 机器人状态 */
+    struct {
+        float battery; /* 电池电量百分比 */
+        float vbat; /* 电池电压 */
+        float cpu_temp; /* CPU温度 */
+    } status;
+
+    /* USER CONFIG BEGIN */
+
+    /* USER CONFIG END */
+
+    /* 各任务的stack使用 */
+    struct {
+        UBaseType_t shoot_ctrl;
+        UBaseType_t chassis_ctrl;
+        UBaseType_t gimbal_ctrl;
+        UBaseType_t dr16;
+        UBaseType_t ai;
+        UBaseType_t atti_esti;
+        UBaseType_t remote;
+    } stack_water_mark;
+
+    /* 各任务运行频率 */
+    struct {
+        float shoot_ctrl;
+        float chassis_ctrl;
+        float gimbal_ctrl;
+        float dr16;
+        float ai;
+        float atti_esti;
+        float remote;
+    } freq;
+
+    /* 任务最近运行时间 */
+    struct {
+        float shoot_ctrl;
+        float chassis_ctrl;
+        float gimbal_ctrl;
+        float dr16;
+        float ai;
+        float atti_esti;
+        float remote;
+    } last_up_time;
+
+} Task_Runtime_t;
+
+/* 任务运行时结构体 */
+extern Task_Runtime_t task_runtime;
+
+/* 初始化任务句柄 */
+extern const osThreadAttr_t attr_init;
+extern const osThreadAttr_t attr_shoot_ctrl;
+extern const osThreadAttr_t attr_chassis_ctrl;
+extern const osThreadAttr_t attr_gimbal_ctrl;
+extern const osThreadAttr_t attr_dr16;
+extern const osThreadAttr_t attr_ai;
+extern const osThreadAttr_t attr_atti_esti;
+extern const osThreadAttr_t attr_remote;
+
+/* 任务函数声明 */
+void Task_Init(void *argument);
+void Task_shoot_ctrl(void *argument);
+void Task_chassis_ctrl(void *argument);
+void Task_gimbal_ctrl(void *argument);
+void Task_dr16(void *argument);
+void Task_ai(void *argument);
+void Task_atti_esti(void *argument);
+void Task_remote(void *argument);
+
+#ifdef __cplusplus
+}
+#endif
\ No newline at end of file